From 7703dea25f926770493b7b16d936ffb0365e933e Mon Sep 17 00:00:00 2001
From: sakumisu <1203593632@qq.com>
Date: Sat, 11 Oct 2025 21:53:47 +0800
Subject: [PATCH] feat: add cherryecat demo

Signed-off-by: sakumisu <1203593632@qq.com>
---
 .github/workflows/action.yml                  |      1 +
 README.md                                     |      1 +
 README_zh.md                                  |      1 +
 projects/etherkit_driver_ethernet/project.ewp |   5635 +-
 .../etherkit_ethercat_cherryecat/.api_xml     |      2 +
 projects/etherkit_ethercat_cherryecat/.config |   1332 +
 .../etherkit_ethercat_cherryecat/.cproject    |    233 +
 .../etherkit_ethercat_cherryecat/.gitignore   |     14 +
 .../etherkit_ethercat_cherryecat/.project     |     28 +
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 .../etherkit_ethernet.JLink.Debug.rttlaunch   |     93 +
 ...gnumcueclipse.managedbuild.cross.arm.prefs |      2 +
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 projects/etherkit_ethercat_cherryecat/Kconfig |     34 +
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 .../etherkit_ethercat_cherryecat/SConscript   |     27 +
 .../etherkit_ethercat_cherryecat/SConstruct   |     56 +
 .../board/Kconfig                             |    572 +
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 .../buildinfo.ipcf                            |     40 +
 .../buildinfo.json                            |     35 +
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 .../packages/CherryECAT-latest/.clang-format  |    171 +
 .../packages/CherryECAT-latest/.gitattributes |     47 +
 .../.github/workflows/build_demo.yml          |     36 +
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 .../CherryECAT-latest/.readthedocs.yaml       |     35 +
 .../packages/CherryECAT-latest/CMakeLists.txt |     39 +
 .../packages/CherryECAT-latest/LICENSE        |    201 +
 .../packages/CherryECAT-latest/README.md      |    111 +
 .../packages/CherryECAT-latest/README_zh.md   |    111 +
 .../packages/CherryECAT-latest/SConscript     |     35 +
 .../packages/CherryECAT-latest/VERSION        |      5 +
 .../cherryec_config_template.h                |     83 +
 .../demo/hpmicro/CMakeLists.txt               |     49 +
 .../demo/hpmicro/inc/FreeRTOSConfig.h         |    152 +
 .../demo/hpmicro/inc/cia402_def.h             |    136 +
 .../demo/hpmicro/inc/csh_config.h             |     89 +
 .../demo/hpmicro/inc/ec_config.h              |     83 +
 .../demo/hpmicro/inc/shell.h                  |     19 +
 .../CherryECAT-latest/demo/hpmicro/main.c     |    216 +
 .../CherryECAT-latest/docs/.gitignore         |      1 +
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 .../CherryECAT-latest/docs/source/conf.py     |     37 +
 .../docs/source/ethercat.rst                  |     32 +
 .../CherryECAT-latest/docs/source/index.rst   |     17 +
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 .../CherryECAT-latest/include/phy/chry_mii.h  |    112 +
 .../CherryECAT-latest/include/phy/chry_phy.h  |     76 +
 .../include/phy/chry_phy_dp83847.h            |     60 +
 .../include/phy/chry_phy_dp83848.h            |     50 +
 .../include/phy/chry_phy_jl1111.h             |     49 +
 .../include/phy/chry_phy_ksz8081.h            |     62 +
 .../include/phy/chry_phy_lan8720.h            |     56 +
 .../include/phy/chry_phy_rtl8201.h            |     56 +
 .../include/phy/chry_phy_rtl8211.h            |     60 +
 .../include/phy/chry_phy_yt8522.h             |     60 +
 .../CherryECAT-latest/osal/ec_osal_freertos.c |    208 +
 .../CherryECAT-latest/osal/ec_osal_rtthread.c |    178 +
 .../CherryECAT-latest/osal/ec_osal_threadx.c  |    267 +
 .../CherryECAT-latest/port/netdev_hpmicro.c   |    464 +
 .../CherryECAT-latest/port/netdev_renesas.c   |    304 +
 .../scripts/ECAT_CIA402_ENI.xml               |   1094 +
 .../scripts/ECAT_CIA402_ESI.xml               |   2141 +
 .../CherryECAT-latest/scripts/eeprom.bin      |    Bin 0 -> 2048 bytes
 .../CherryECAT-latest/scripts/eeprom.h        |    138 +
 .../CherryECAT-latest/scripts/eni_parser.py   |    381 +
 .../CherryECAT-latest/scripts/esi_parser.py   |    510 +
 .../CherryECAT-latest/scripts/sync_config.h   |     35 +
 .../packages/CherryECAT-latest/src/ec_cmd.c   |   1059 +
 .../packages/CherryECAT-latest/src/ec_coe.c   |    526 +
 .../CherryECAT-latest/src/ec_common.c         |    381 +
 .../CherryECAT-latest/src/ec_datagram.c       |    195 +
 .../packages/CherryECAT-latest/src/ec_foe.c   |      0
 .../CherryECAT-latest/src/ec_mailbox.c        |    133 +
 .../CherryECAT-latest/src/ec_master.c         |    856 +
 .../CherryECAT-latest/src/ec_netdev.c         |    163 +
 .../packages/CherryECAT-latest/src/ec_perf.c  |     80 +
 .../packages/CherryECAT-latest/src/ec_sii.c   |    176 +
 .../packages/CherryECAT-latest/src/ec_slave.c |   1360 +
 .../CherryECAT-latest/src/ec_timestamp.c      |    111 +
 .../CherryECAT-latest/src/phy/chry_phy.c      |    156 +
 .../packages/SConscript                       |     12 +
 .../packages/pkgs.json                        |      1 +
 .../packages/pkgs_error.json                  |      1 +
 .../etherkit_ethercat_cherryecat/project.ewd  |   3276 +
 .../etherkit_ethercat_cherryecat/project.ewp  |   2728 +
 .../etherkit_ethercat_cherryecat/project.ewt  |   3304 +
 .../etherkit_ethercat_cherryecat/project.eww  |     10 +
 .../etherkit_ethercat_cherryecat/rtconfig.h   |    366 +
 .../etherkit_ethercat_cherryecat/rtconfig.py  |    121 +
 .../rzn/SConscript                            |     25 +
 .../CMSIS/Core_R/Include/cmsis_compiler.h     |    290 +
 .../CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h |    783 +
 .../CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h  |   2233 +
 .../CMSIS/Core_R/Include/cmsis_iccarm.h       |    958 +
 .../CMSIS/Core_R/Include/cmsis_version.h      |     46 +
 .../CMSIS_5/CMSIS/Core_R/Include/core_cr52.h  |    312 +
 .../rzn/arm/CMSIS_5/LICENSE.txt               |    201 +
 .../rzn/board/rzn2l_rsk/board.h               |     59 +
 .../rzn/board/rzn2l_rsk/board_ethernet_phy.h  |     46 +
 .../rzn/board/rzn2l_rsk/board_init.c          |     53 +
 .../rzn/board/rzn2l_rsk/board_init.h          |     50 +
 .../rzn/board/rzn2l_rsk/board_leds.c          |     63 +
 .../rzn/board/rzn2l_rsk/board_leds.h          |     72 +
 .../rzn/fsp/inc/api/bsp_api.h                 |     97 +
 .../rzn/fsp/inc/api/r_ether_api.h             |    245 +
 .../rzn/fsp/inc/api/r_ether_phy_api.h         |    187 +
 .../rzn/fsp/inc/api/r_ether_selector_api.h    |    141 +
 .../rzn/fsp/inc/api/r_ether_switch_api.h      |    102 +
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 .../rzn/fsp/inc/api/r_timer_api.h             |    291 +
 .../rzn/fsp/inc/api/r_transfer_api.h          |    388 +
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 .../rzn/fsp/inc/fsp_features.h                |    564 +
 .../rzn/fsp/inc/fsp_version.h                 |     66 +
 .../rzn/fsp/inc/instances/r_ether_phy.h       |    154 +
 .../rzn/fsp/inc/instances/r_ether_selector.h  |     78 +
 .../rzn/fsp/inc/instances/r_ethsw.h           |   1242 +
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 .../rzn/fsp/inc/instances/r_gpt.h             |    520 +
 .../rzn/fsp/inc/instances/r_ioport.h          |    198 +
 .../rzn/fsp/inc/instances/r_mtu3.h            |    455 +
 .../rzn/fsp/inc/instances/r_sci_uart.h        |    245 +
 .../cmsis/Device/RENESAS/Include/R9A07G084.h  |  46264 +++++++
 .../cmsis/Device/RENESAS/Include/R9A09G087.h  | 101834 +++++++++++++++
 .../cmsis/Device/RENESAS/Include/renesas.h    |    125 +
 .../bsp/cmsis/Device/RENESAS/Include/system.h |     44 +
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 .../Device/RENESAS/Source/cr/system_core.c    |    699 +
 .../bsp/cmsis/Device/RENESAS/Source/startup.c |    221 +
 .../bsp/cmsis/Device/RENESAS/Source/system.c  |   1703 +
 .../src/bsp/mcu/all/bsp_address_expander.c    |     77 +
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 .../rzn/fsp/src/bsp/mcu/all/bsp_cache.c       |    738 +
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 .../src/bsp/mcu/all/bsp_compiler_support.h    |    104 +
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 .../fsp/src/bsp/mcu/all/bsp_ddr_fw_param.c    |  32797 +++++
 .../fsp/src/bsp/mcu/all/bsp_ddr_fw_param.h    |     29 +
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 .../rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h  |     36 +
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 .../rzn/fsp/src/bsp/mcu/all/bsp_irq.h         |    624 +
 .../rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h     |     62 +
 .../rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h |    487 +
 .../src/bsp/mcu/all/bsp_register_protection.c |    102 +
 .../src/bsp/mcu/all/bsp_register_protection.h |     62 +
 .../rzn/fsp/src/bsp/mcu/all/bsp_reset.c       |    372 +
 .../rzn/fsp/src/bsp/mcu/all/bsp_reset.h       |    196 +
 .../rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c        |     94 +
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 .../rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.c  |     88 +
 .../rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.h  |     69 +
 .../rzn/fsp/src/bsp/mcu/all/bsp_tfu.h         |    836 +
 .../rzn/fsp/src/bsp/mcu/all/bsp_tzc400.c      |    146 +
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 .../fsp/src/bsp/mcu/all/cr/bsp_cache_core.c   |     34 +
 .../fsp/src/bsp/mcu/all/cr/bsp_cache_core.h   |     38 +
 .../fsp/src/bsp/mcu/all/cr/bsp_delay_core.c   |     49 +
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 .../rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c |    256 +
 .../rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h |    348 +
 .../rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h       |    509 +
 .../rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h   |    455 +
 .../rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c |     72 +
 .../fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c  |     54 +
 .../rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h  |     50 +
 .../rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h  |   1431 +
 .../rzn/fsp/src/r_ether_phy/r_ether_phy.c     |   2120 +
 .../src/r_ether_selector/r_ether_selector.c   |    464 +
 .../rzn/fsp/src/r_ethsw/r_ethsw.c             |   6491 +
 .../rzn/fsp/src/r_gmac/r_gmac.c               |   2423 +
 .../rzn/fsp/src/r_gpt/r_gpt.c                 |   1939 +
 .../rzn/fsp/src/r_ioport/r_ioport.c           |   1269 +
 .../rzn/fsp/src/r_mtu3/r_mtu3.c               |   2501 +
 .../rzn/fsp/src/r_sci_uart/r_sci_uart.c       |   1920 +
 .../etherkit_ethercat_cherryecat/rzn_cfg.txt  |   1524 +
 .../rzn_cfg/SConscript                        |     17 +
 .../rzn_cfg/fsp_cfg/bsp/board_cfg.h           |     26 +
 .../rzn_cfg/fsp_cfg/bsp/bsp_cfg.h             |     37 +
 .../rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h  |     14 +
 .../fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h   |    552 +
 .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h       |     12 +
 .../rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h  |     15 +
 .../rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h      |      5 +
 .../rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h         |    105 +
 .../rzn_cfg/fsp_cfg/r_ether_cfg.h             |      9 +
 .../rzn_cfg/fsp_cfg/r_ether_phy_cfg.h         |     33 +
 .../rzn_cfg/fsp_cfg/r_ether_selector_cfg.h    |      6 +
 .../rzn_cfg/fsp_cfg/r_ether_switch_cfg.h      |      5 +
 .../rzn_cfg/fsp_cfg/r_gpt_cfg.h               |     16 +
 .../rzn_cfg/fsp_cfg/r_ioport_cfg.h            |     13 +
 .../rzn_cfg/fsp_cfg/r_mtu3_cfg.h              |     15 +
 .../rzn_cfg/fsp_cfg/r_sci_uart_cfg.h          |     16 +
 .../rzn_gen/SConscript                        |     17 +
 .../rzn_gen/bsp_clock_cfg.h                   |     42 +
 .../rzn_gen/common_data.c                     |     75 +
 .../rzn_gen/common_data.h                     |     16 +
 .../rzn_gen/hal_data.c                        |    791 +
 .../rzn_gen/hal_data.h                        |    263 +
 .../rzn_gen/main.c                            |      6 +
 .../rzn_gen/pin_data.c                        |    420 +
 .../rzn_gen/vector_data.c                     |     33 +
 .../rzn_gen/vector_data.h                     |     75 +
 .../script/fsp_xspi0_boot.icf                 |    735 +
 .../script/fsp_xspi0_boot.ld                  |    689 +
 .../script/fsp_xspi0_boot_scons.ld            |    696 +
 .../src/hal_entry.c                           |    139 +
 .../etherkit_ethercat_cherryecat/template.ewd |   3276 +
 .../etherkit_ethercat_cherryecat/template.ewp |   2281 +
 .../etherkit_ethercat_cherryecat/template.eww |      7 +
 sdk-bsp-rzn2l-etherkit.yaml                   |     21 +
 287 files changed, 276453 insertions(+), 2818 deletions(-)
 create mode 100644 projects/etherkit_ethercat_cherryecat/.api_xml
 create mode 100644 projects/etherkit_ethercat_cherryecat/.config
 create mode 100644 projects/etherkit_ethercat_cherryecat/.cproject
 create mode 100644 projects/etherkit_ethercat_cherryecat/.gitignore
 create mode 100644 projects/etherkit_ethercat_cherryecat/.project
 create mode 100644 projects/etherkit_ethercat_cherryecat/.secure_azone
 create mode 100644 projects/etherkit_ethercat_cherryecat/.secure_rzone
 create mode 100644 projects/etherkit_ethercat_cherryecat/.secure_xml
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/.rtmenus
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/etherkit_ethernet.JLink.Debug.rttlaunch
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/language.settings.xml
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/local_temp_storage.prefs
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.resources.prefs
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.runtime.prefs
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/projcfg.ini
 create mode 100644 projects/etherkit_ethercat_cherryecat/.settings/standalone.prefs
 create mode 100644 projects/etherkit_ethercat_cherryecat/Kconfig
 create mode 100644 projects/etherkit_ethercat_cherryecat/README.md
 create mode 100644 projects/etherkit_ethercat_cherryecat/README_zh.md
 create mode 100644 projects/etherkit_ethercat_cherryecat/SConscript
 create mode 100644 projects/etherkit_ethercat_cherryecat/SConstruct
 create mode 100644 projects/etherkit_ethercat_cherryecat/board/Kconfig
 create mode 100644 projects/etherkit_ethercat_cherryecat/board/SConscript
 create mode 100644 projects/etherkit_ethercat_cherryecat/board/board.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/board/ec_config.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/board/ports/SConscript
 create mode 100644 projects/etherkit_ethercat_cherryecat/board/ports/gpio_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/buildinfo.ipcf
 create mode 100644 projects/etherkit_ethercat_cherryecat/buildinfo.json
 create mode 100644 projects/etherkit_ethercat_cherryecat/configuration.xml
 create mode 100644 projects/etherkit_ethercat_cherryecat/envsetup.sh
 create mode 100644 projects/etherkit_ethercat_cherryecat/figures/cherryecat1.png
 create mode 100644 projects/etherkit_ethercat_cherryecat/figures/cherryecat2.png
 create mode 100644 projects/etherkit_ethercat_cherryecat/figures/cherryecat3.png
 create mode 100644 projects/etherkit_ethercat_cherryecat/figures/cherryecat4.png
 create mode 100644 projects/etherkit_ethercat_cherryecat/figures/cherryecat5.png
 create mode 100644 projects/etherkit_ethercat_cherryecat/figures/image-20241126104408737.png
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 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_phy_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_selector_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_switch_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_gpt_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ioport_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_mtu3_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_sci_uart_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/SConscript
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/bsp_clock_cfg.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/common_data.c
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/common_data.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/hal_data.c
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/hal_data.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/main.c
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/pin_data.c
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/vector_data.c
 create mode 100644 projects/etherkit_ethercat_cherryecat/rzn_gen/vector_data.h
 create mode 100644 projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot.icf
 create mode 100644 projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot.ld
 create mode 100644 projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot_scons.ld
 create mode 100644 projects/etherkit_ethercat_cherryecat/src/hal_entry.c
 create mode 100644 projects/etherkit_ethercat_cherryecat/template.ewd
 create mode 100644 projects/etherkit_ethercat_cherryecat/template.ewp
 create mode 100644 projects/etherkit_ethercat_cherryecat/template.eww

diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml
index 0c42e682..adc79779 100644
--- a/.github/workflows/action.yml
+++ b/.github/workflows/action.yml
@@ -76,6 +76,7 @@ jobs:
          - {RTT_BSP: "etherkit_profinet_pnet"}
          - {RTT_BSP: "etherkit_ethernetip_opener"}
          - {RTT_BSP: "etherkit_factory"}
+         - {RTT_BSP: "etherkit_ethercat_cherryecat"}
     steps:
       - uses: actions/checkout@v2
       - name: Set up Python
diff --git a/README.md b/README.md
index c9f5aee7..1c09152c 100644
--- a/README.md
+++ b/README.md
@@ -34,6 +34,7 @@ $ sdk-bsp-rzn2l-etherkit
 │   ├── etherkit_driver_rs485
 │   ├── etherkit_driver_spi
 │   ├── etherkit_driver_wdt
+│   ├── etherkit_ethercat_cherryecat
 │   ├── etherkit_driver_hyperram
 │   ├── etherkit_ethernet
 │   ├── etherkit_usb_pcdc
diff --git a/README_zh.md b/README_zh.md
index 412dcacd..d64590b0 100644
--- a/README_zh.md
+++ b/README_zh.md
@@ -36,6 +36,7 @@ $ sdk-bsp-rzn2l-etherkit
 │   ├── etherkit_driver_rs485
 │   ├── etherkit_driver_spi
 │   ├── etherkit_driver_wdt
+│   ├── etherkit_ethercat_cherryecat
 │   ├── etherkit_driver_hyperram
 │   ├── etherkit_ethernet
 │   ├── etherkit_usb_pcdc
diff --git a/projects/etherkit_driver_ethernet/project.ewp b/projects/etherkit_driver_ethernet/project.ewp
index 87d72760..4497ca44 100644
--- a/projects/etherkit_driver_ethernet/project.ewp
+++ b/projects/etherkit_driver_ethernet/project.ewp
@@ -1,2823 +1,2822 @@
+<?xml version="1.0" encoding="UTF-8"?>
 <project>
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-    <settings>
-      <name>General</name>
-      <archiveVersion>3</archiveVersion>
-      <data>
-        <version>36</version>
-        <wantNonLocal>1</wantNonLocal>
+    <fileVersion>4</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
         <debug>1</debug>
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-          <state>Debug\BrowseInfo</state>
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-          <state>Debug\Exe</state>
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-          <name>ObjPath</name>
-          <state>Debug\Obj</state>
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-          <state>Debug\List</state>
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+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$/script/fsp_xspi0_boot.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state>--config_search "$PROJ_DIR$"</state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>system_init</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>template_import_lib.o</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkFpuProcessor</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>2</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
         <debug>0</debug>
-        <option>
-          <name>IlinkLogCrtRoutineSelection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogFragmentInfo</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogInlining</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogMerging</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkDemangle</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkWrapperFileEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkWrapperFile</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkLibIOConfig</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkInputFileSlave</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOutputFile</name>
-          <state>###Unitialized###</state>
-        </option>
-        <option>
-          <name>IlinkDebugInfoEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkKeepSymbols</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkRawBinaryFile</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkRawBinarySymbol</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkRawBinarySegment</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkRawBinaryAlign</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkDefines</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkConfigDefines</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkMapFile</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkLogFile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogInitialization</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogModule</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogSection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogVeneer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$/script/fsp_xspi0_boot.icf</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state>--config_search "$PROJ_DIR$"</state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>system_init</state>
-        </option>
-        <option>
-          <name>DoFill</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
-        </option>
-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>FillerEnd</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>CrcSize</name>
-          <version>0</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcAlign</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcPoly</name>
-          <state>0x11021</state>
-        </option>
-        <option>
-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
-        </option>
-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogAutoLibSelect</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogRedirSymbols</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogUnusedFragments</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcReverseByteOrder</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCrcUseAsInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptInline</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsAllow</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptExceptionsForce</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkCmsis</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptMergeDuplSections</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkOptUseVfe</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkOptForceVfe</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackAnalysisEnable</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkStackControlFile</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkStackCallGraphFile</name>
-          <state />
-        </option>
-        <option>
-          <name>CrcAlgorithm</name>
-          <version>1</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcUnitSize</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkThreadsSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkLogCallGraph</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile_AltDefault</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkEncInput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkEncOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkEncOutputBom</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkHeapSelect</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkLocaleSelect</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkTrustzoneImportLibraryOut</name>
-          <state>###Unitialized###</state>
-        </option>
-        <option>
-          <name>OILinkExtraOption</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkRawBinaryFile2</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkRawBinarySymbol2</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkRawBinarySegment2</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkRawBinaryAlign2</name>
-          <state />
-        </option>
-        <option>
-          <name>IlinkProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkFpuProcessor</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>0</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state />
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>BUILDACTION</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <buildActions>
-          <buildAction>
-            <cmdline>cmd /c ""$PROJ_DIR$\rasc_launcher.bat" "$PROJ_DIR$\rasc_version.txt" -nosplash --launcher.suppressErrors --generate --compiler IAR --devicefamily $RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" 2&gt; "$BUILD_FILES_DIR$\.rasc_stderr.txt" &amp;&amp; echo. &gt; "$BUILD_FILES_DIR$\$TARGET_BNAME$.rasc""</cmdline>
-            <workingDirectory>$PROJ_DIR$</workingDirectory>
-            <buildSequence>preCompile</buildSequence>
-            <outputs>
-              <file>
-                <name>$BUILD_FILES_DIR$/$TARGET_BNAME$.rasc</name>
-              </file>
-            </outputs>
-            <dependencies>
-              <file>
-                <name>configuration.xml</name>
-              </file>
-            </dependencies>
-          </buildAction>
-          <buildAction>
-            <cmdline>cmd /c ""$PROJ_DIR$\rasc_launcher.bat" "$PROJ_DIR$\rasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily $RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2&gt; "$BUILD_FILES_DIR$\.rasc_stderr.txt""</cmdline>
-            <workingDirectory>$PROJ_DIR$</workingDirectory>
-            <buildSequence>postLink</buildSequence>
-            <outputs>
-              <file>
-                <name>$TARGET_BPATH$.sbd</name>
-              </file>
-            </outputs>
-            <dependencies>
-              <file>
-                <name>$TARGET_PATH$</name>
-              </file>
-            </dependencies>
-          </buildAction>
-        </buildActions>
-      </data>
-    </settings>
-  </configuration>
-  <file>
-    <name>$PROJ_DIR$\buildinfo.ipcf</name>
-    <tag>IAR.ControlFile</tag>
-  </file>
-  <group>
-    <name>Applications</name>
-    <file>
-      <name>$PROJ_DIR$\src\hal_entry.c</name>
-    </file>
-  </group>
-  <group>
-    <name>Compiler</name>
-    <file>
-      <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cctype.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cstdlib.c</name>
-    </file>
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+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$/script/fsp_xspi0_boot.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state>--config_search "$PROJ_DIR$"</state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>system_init</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkFpuProcessor</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <buildActions>
+                    <buildAction>
+                        <cmdline>cmd /c ""$PROJ_DIR$\rasc_launcher.bat" "$PROJ_DIR$\rasc_version.txt" -nosplash --launcher.suppressErrors --generate --compiler IAR --devicefamily $RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" 2&gt; "$BUILD_FILES_DIR$\.rasc_stderr.txt" &amp;&amp; echo. &gt; "$BUILD_FILES_DIR$\$TARGET_BNAME$.rasc""</cmdline>
+                        <workingDirectory>$PROJ_DIR$</workingDirectory>
+                        <buildSequence>preCompile</buildSequence>
+                        <outputs>
+                            <file>
+                                <name>$BUILD_FILES_DIR$/$TARGET_BNAME$.rasc</name>
+                            </file>
+                        </outputs>
+                        <dependencies>
+                            <file>
+                                <name>configuration.xml</name>
+                            </file>
+                        </dependencies>
+                    </buildAction>
+                    <buildAction>
+                        <cmdline>cmd /c ""$PROJ_DIR$\rasc_launcher.bat" "$PROJ_DIR$\rasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily $RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2&gt; "$BUILD_FILES_DIR$\.rasc_stderr.txt""</cmdline>
+                        <workingDirectory>$PROJ_DIR$</workingDirectory>
+                        <buildSequence>postLink</buildSequence>
+                        <outputs>
+                            <file>
+                                <name>$TARGET_BPATH$.sbd</name>
+                            </file>
+                        </outputs>
+                        <dependencies>
+                            <file>
+                                <name>$TARGET_PATH$</name>
+                            </file>
+                        </dependencies>
+                    </buildAction>
+                </buildActions>
+            </data>
+        </settings>
+    </configuration>
+    <group>
+        <name>Applications</name>
+        <file>
+            <name>$PROJ_DIR$\src\hal_entry.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Compiler</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cctype.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cstdlib.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cstring.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\ctime.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cunistd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cwchar.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\environ.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_close.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_lseek.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_mem.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_open.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_read.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_remove.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_write.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscalls.c</name>
+        </file>
+    </group>
+    <group>
+        <name>CPU</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\backtrace.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\context_iar.S</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\cpuport.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\gicv3.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\interrupt.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\stack.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\start_iar.S</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\trap.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\vector_iar.S</name>
+        </file>
+    </group>
+    <group>
+        <name>DeviceDrivers</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\completion.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\condvar.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\dataqueue.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\core\device.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\pin\pin.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\pipe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\ringblk_buf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\ringbuffer.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\serial\serial_v2.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\waitqueue.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\workqueue.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Drivers</name>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_common.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_eth.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_gpio.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_usart_v2.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Finsh</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\cmd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\msh.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\msh_parse.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\shell.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Kernel</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\clock.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\components.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\idle.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\ipc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\irq.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\kservice.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\klibc\kstdio.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\klibc\kstring.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\mem.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\mempool.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\object.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\scheduler_comm.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\scheduler_up.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\thread.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\timer.c</name>
+        </file>
+    </group>
+    <group>
+        <name>libcpu</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\common\atomic_arm.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\common\div0.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\common\showmem.c</name>
+        </file>
+    </group>
+    <group>
+        <name>lwIP</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\api_lib.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\api_msg.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\autoip.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\def.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\dhcp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\dns.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\err.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\etharp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\netif\ethernet.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\port\ethernetif.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\icmp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\igmp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\inet_chksum.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\init.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ip.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_addr.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_frag.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\netif\lowpan6.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\memp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\netbuf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\netdb.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\netif.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\netifapi.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\pbuf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\apps\ping\ping.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\raw.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\sockets.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\stats.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\sys.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\port\sys_arch.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\tcp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\tcp_in.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\tcp_out.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\tcpip.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\timeouts.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\udp.c</name>
+        </file>
+    </group>
+    <group>
+        <name>POSIX</name>
+    </group>
+    <group>
+        <name>RZN</name>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_address_expander.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_cache.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_cache_core.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_clocks.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_common.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_ddr.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_ddr_fw_param.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_delay.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_delay_core.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_io.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_irq.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_irq_core.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_irq_sense.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_loader_param.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_register_protection.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_reset.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_sbrk.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_semaphore.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_slave_stop.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_tzc400.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_ether_phy\r_ether_phy.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_ether_selector\r_ether_selector.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_ethsw\r_ethsw.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_gmac\r_gmac.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_ioport\r_ioport.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_sci_uart\r_sci_uart.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\startup.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\startup_core.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\system.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\system_core.c</name>
+        </file>
+    </group>
+    <group>
+        <name>RZN_cfg</name>
+    </group>
+    <group>
+        <name>RZN_gen</name>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\common_data.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\hal_data.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\main.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\pin_data.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\vector_data.c</name>
+        </file>
+    </group>
+    <group>
+        <name>SAL</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\sal\impl\af_inet_lwip.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\sal\socket\net_netdb.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\netdev\src\netdev.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\netdev\src\netdev_ipaddr.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\net\sal\src\sal_socket.c</name>
+        </file>
+    </group>
+    <file>
+        <name>$PROJ_DIR$\buildinfo.ipcf</name>
+        <tag>IAR.ControlFile</tag>
     </file>
-  </group>
 </project>
diff --git a/projects/etherkit_ethercat_cherryecat/.api_xml b/projects/etherkit_ethercat_cherryecat/.api_xml
new file mode 100644
index 00000000..fc9bf0b3
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.api_xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<ddscApi/>
diff --git a/projects/etherkit_ethercat_cherryecat/.config b/projects/etherkit_ethercat_cherryecat/.config
new file mode 100644
index 00000000..3f43f787
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.config
@@ -0,0 +1,1332 @@
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+# end of kservice optimization
+
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=512
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50100
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# end of RT-Thread Kernel
+
+CONFIG_RT_USING_HW_ATOMIC=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_R=y
+CONFIG_ARCH_ARM_CORTEX_R52=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# end of DFS: device virtual file system
+
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+CONFIG_RT_USING_HWTIMER=y
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB
+# end of Device Drivers
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+# CONFIG_RT_LIBC_USING_LIGHT_TZ_DST is not set
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+# end of Network
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
+# CONFIG_RT_USING_VBUS is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+# CONFIG_PKG_USING_ESP_HOSTED is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# CONFIG_PKG_USING_PNET is not set
+# CONFIG_PKG_USING_OPENER is not set
+# CONFIG_PKG_USING_FREEMQTT is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+# CONFIG_PKG_USING_RYAN_JSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_MCOREDUMP is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+# CONFIG_PKG_USING_RVBACKTRACE is not set
+# CONFIG_PKG_USING_HPATCHLITE is not set
+# CONFIG_PKG_USING_THREAD_METRIC is not set
+# end of tools packages
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_UART_FRAMEWORK is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_RMP is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+# CONFIG_PKG_USING_HEARTBEAT is not set
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
+CONFIG_PKG_USING_CHERRYECAT=y
+# CONFIG_PKG_CHERRYECAT_NETDEV_CUSTOM is not set
+# CONFIG_PKG_CHERRYECAT_NETDEV_HPMICRO is not set
+CONFIG_PKG_CHERRYECAT_NETDEV_RENESAS=y
+CONFIG_PKG_CHERRYECAT_PATH="/packages/system/CherryECAT"
+CONFIG_PKG_USING_CHERRYECAT_LATEST_VERSION=y
+CONFIG_PKG_CHERRYECAT_VER="latest"
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_MM32 is not set
+
+#
+# WCH HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_CH32V20x_SDK is not set
+# CONFIG_PKG_USING_CH32V307_SDK is not set
+# end of WCH HAL & SDK Drivers
+
+#
+# AT32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set
+# end of AT32 HAL & SDK Drivers
+
+#
+# HC32 DDL Drivers
+#
+# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
+# end of HC32 DDL Drivers
+
+#
+# NXP HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set
+# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
+# end of NXP HAL & SDK Drivers
+
+#
+# NUVOTON Drivers
+#
+# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
+# end of NUVOTON Drivers
+
+#
+# GD32 Drivers
+#
+# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
+# end of GD32 Drivers
+
+#
+# HPMicro SDK
+#
+# CONFIG_PKG_USING_HPM_SDK is not set
+# end of HPMicro SDK
+# end of HAL & SDK Drivers
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_MAX31855 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90382 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90394 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+# CONFIG_PKG_USING_P3T1755 is not set
+# CONFIG_PKG_USING_QMI8658 is not set
+# CONFIG_PKG_USING_ICM20948 is not set
+# end of sensors drivers
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_BT_MX02 is not set
+# CONFIG_PKG_USING_GC9A01 is not set
+# CONFIG_PKG_USING_IK485 is not set
+# CONFIG_PKG_USING_SERVO is not set
+# CONFIG_PKG_USING_SEAN_WS2812B is not set
+# CONFIG_PKG_USING_IC74HC165 is not set
+# CONFIG_PKG_USING_IST8310 is not set
+# CONFIG_PKG_USING_ST7789_SPI is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+# CONFIG_PKG_USING_LLMCHAT is not set
+# end of AI packages
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_APID is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# end of Signal Processing and Control Algorithm Packages
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+# end of project laboratory
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# end of entertainment: terminal games and other interesting software packages
+
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LIBCRC is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+# CONFIG_PKG_USING_DRMP is not set
+# end of miscellaneous packages
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
+
+#
+# Uncategorized
+#
+# end of Arduino libraries
+# end of RT-Thread online packages
+
+CONFIG_SOC_FAMILY_RENESAS_RZ=y
+CONFIG_SOC_SERIES_R9A07G0=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_R9A07G084=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_UART0_RX_USING_DMA is not set
+# CONFIG_BSP_UART0_TX_USING_DMA is not set
+CONFIG_BSP_UART0_RX_BUFSIZE=256
+CONFIG_BSP_UART0_TX_BUFSIZE=0
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_CANFD is not set
+# CONFIG_BSP_USING_SCI is not set
+# CONFIG_BSP_USING_HYPERRAM is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_TIM is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_ETH is not set
+# end of On-chip Peripheral Drivers
+
+#
+# Board extended module Drivers
+#
+# CONFIG_BSP_USING_RW007 is not set
+# end of Board extended module Drivers
+# end of Hardware Drivers Config
diff --git a/projects/etherkit_ethercat_cherryecat/.cproject b/projects/etherkit_ethercat_cherryecat/.cproject
new file mode 100644
index 00000000..319b0e6e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.cproject
@@ -0,0 +1,233 @@
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+          <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
+          <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
+          <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
+          <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser" />
+          <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
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diff --git a/projects/etherkit_ethercat_cherryecat/.gitignore b/projects/etherkit_ethercat_cherryecat/.gitignore
new file mode 100644
index 00000000..4a339a10
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.gitignore
@@ -0,0 +1,14 @@
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+/Listings
+/Objects
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+/build
+/makefile.targets
+/rtconfig.pyc
+/rt-thread
+/libraries
+/project.custom_argvars
+/.vscode
+/__pycache
+/settings
+/rtconfig_preinc.h
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/.project b/projects/etherkit_ethercat_cherryecat/.project
new file mode 100644
index 00000000..2fca752f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.project
@@ -0,0 +1,28 @@
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diff --git a/projects/etherkit_ethercat_cherryecat/.secure_azone b/projects/etherkit_ethercat_cherryecat/.secure_azone
new file mode 100644
index 00000000..585ba89c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.secure_azone
@@ -0,0 +1,4 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
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diff --git a/projects/etherkit_ethercat_cherryecat/.secure_rzone b/projects/etherkit_ethercat_cherryecat/.secure_rzone
new file mode 100644
index 00000000..ecf37361
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.secure_rzone
@@ -0,0 +1,29 @@
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+            <memory name="xSPI0_CS0_SPACE_MIRROR" type="ROM" start="0x40000000" size="0x04000000" security=""/>
+            <memory name="xSPI0_CS1_SPACE_MIRROR" type="ROM" start="0x44000000" size="0x04000000" security=""/>
+            <memory name="xSPI1_CS0_SPACE_MIRROR" type="ROM" start="0x48000000" size="0x04000000" security=""/>
+            <memory name="CS0_SPACE_MIRROR" type="ROM" start="0x50000000" size="0x04000000" security=""/>
+            <memory name="CS2_SPACE_MIRROR" type="ROM" start="0x54000000" size="0x04000000" security=""/>
+            <memory name="CS3_SPACE_MIRROR" type="ROM" start="0x58000000" size="0x04000000" security=""/>
+            <memory name="CS5_SPACE_MIRROR" type="ROM" start="0x5C000000" size="0x04000000" security=""/>
+            <memory name="xSPI0_CS0_SPACE" type="ROM" start="0x60000000" size="0x04000000" security=""/>
+            <memory name="xSPI0_CS1_SPACE" type="ROM" start="0x64000000" size="0x04000000" security=""/>
+            <memory name="xSPI1_CS0_SPACE" type="ROM" start="0x68000000" size="0x04000000" security=""/>
+            <memory name="CS0_SPACE" type="ROM" start="0x70000000" size="0x04000000" security=""/>
+            <memory name="CS2_SPACE" type="ROM" start="0x74000000" size="0x04000000" security=""/>
+            <memory name="CS3_SPACE" type="ROM" start="0x78000000" size="0x04000000" security=""/>
+            <memory name="CS5_SPACE" type="ROM" start="0x7C000000" size="0x04000000" security=""/>
+        </memories>
+        <peripherals/>
+    </resources>
+</rzone>
diff --git a/projects/etherkit_ethercat_cherryecat/.secure_xml b/projects/etherkit_ethercat_cherryecat/.secure_xml
new file mode 100644
index 00000000..12fd5370
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.secure_xml
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="10">
+  <generalSettings>
+    <option key="#Board#" value="board.rzn2lrsk.xspi0_x1"/>
+    <option key="CPU" value="RZN2L"/>
+    <option key="Core" value="CR52_0"/>
+    <option key="#TargetName#" value="R9A07G084M04GBG"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-r52"/>
+    <option key="#DeviceCommand#" value="R9A07G084M04"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R9A07G084M04GBG.pincfg"/>
+    <option key="#FSPVersion#" value="2.2.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##rzn2l_rsk##xspi0_x1_boot"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="gcc-arm-embedded"/>
+    <option key="#ToolchainVersion#" value=""/>
+  </generalSettings>
+  <raBspConfiguration/>
+  <raClockConfiguration>
+    <node id="board.clock.main.freq" option="board.clock.main.freq.25m"/>
+    <node id="board.clock.loco.enable" option="board.clock.loco.enable.enabled"/>
+    <node id="board.clock.pll0.display" option="board.clock.pll0.display.value"/>
+    <node id="board.clock.pll1" option="board.clock.pll1.initial"/>
+    <node id="board.clock.pll1.display" option="board.clock.pll1.display.value"/>
+    <node id="board.clock.ethernet.source" option="board.clock.ethernet.source.main"/>
+    <node id="board.clock.reference.display" option="board.clock.reference.display.value"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.240k"/>
+    <node id="board.clock.clma0.enable" option="board.clock.clma0.enable.enabled"/>
+    <node id="board.clock.clma0.error" option="board.clock.clma0.error.not_mask"/>
+    <node id="board.clock.clma3.error" option="board.clock.clma3.error.not_mask"/>
+    <node id="board.clock.clma1.error" option="board.clock.clma1.error.mask"/>
+    <node id="board.clock.clma3.enable" option="board.clock.clma3.enable.enabled"/>
+    <node id="board.clock.clma1.enable" option="board.clock.clma1.enable.enabled"/>
+    <node id="board.clock.clma2.enable" option="board.clock.clma2.enable.enabled"/>
+    <node id="board.clock.clma0.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma1.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma2.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma3.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.alternative.source" option="board.clock.alternative.source.loco"/>
+    <node id="board.clock.clma0.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma1.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma2.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma3.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.iclk.freq" option="board.clock.iclk.freq.200m"/>
+    <node id="board.clock.cpu0clk.mul" option="board.clock.cpu0clk.mul.2"/>
+    <node id="board.clock.cpu0clk.display" option="board.clock.cpu0clk.display.value"/>
+    <node id="board.clock.ckio.div" option="board.clock.ckio.div.4"/>
+    <node id="board.clock.ckio.display" option="board.clock.ckio.display.value"/>
+    <node id="board.clock.sci0asyncclk.sel" option="board.clock.sci0asyncclk.sel.1"/>
+    <node id="board.clock.sci1asyncclk.sel" option="board.clock.sci1asyncclk.sel.1"/>
+    <node id="board.clock.sci2asyncclk.sel" option="board.clock.sci2asyncclk.sel.1"/>
+    <node id="board.clock.sci3asyncclk.sel" option="board.clock.sci3asyncclk.sel.1"/>
+    <node id="board.clock.sci4asyncclk.sel" option="board.clock.sci4asyncclk.sel.1"/>
+    <node id="board.clock.sci5asyncclk.sel" option="board.clock.sci5asyncclk.sel.1"/>
+    <node id="board.clock.spi0asyncclk.sel" option="board.clock.spi0asyncclk.sel.1"/>
+    <node id="board.clock.spi1asyncclk.sel" option="board.clock.spi1asyncclk.sel.1"/>
+    <node id="board.clock.spi2asyncclk.sel" option="board.clock.spi2asyncclk.sel.1"/>
+    <node id="board.clock.spi3asyncclk.sel" option="board.clock.spi3asyncclk.sel.1"/>
+    <node id="board.clock.pclkshost.display" option="board.clock.pclkshost.display.value"/>
+    <node id="board.clock.pclkgptl.display" option="board.clock.pclkgptl.display.value"/>
+    <node id="board.clock.pclkh.display" option="board.clock.pclkh.display.value"/>
+    <node id="board.clock.pclkm.display" option="board.clock.pclkm.display.value"/>
+    <node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
+    <node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
+    <node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
+    <node id="board.clock.pclkcan.freq.display" option="board.clock.pclkcan.freq.display.value"/>
+    <node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.133m"/>
+    <node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
+    <node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
+  </raClockConfiguration>
+  <raPinConfiguration>
+    <pincfg active="true" name="" symbol="">
+      <configSetting altId="canfd0.canrx0.p01_7" configurationId="canfd0.canrx0" peripheral="CANFD0"/>
+      <configSetting altId="canfd0.cantx0.p02_2" configurationId="canfd0.cantx0" peripheral="CANFD0"/>
+      <configSetting altId="ether_eth0.eth0_refclk.p09_1" configurationId="ether_eth0.eth0_refclk" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_rxclk_ref_clk_rxc.p08_6" configurationId="ether_eth0.eth0_rxclk_ref_clk_rxc" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_rxd0.p10_1" configurationId="ether_eth0.eth0_rxd0" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_rxd1.p10_2" configurationId="ether_eth0.eth0_rxd1" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_rxd2.p10_3" configurationId="ether_eth0.eth0_rxd2" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_rxd3.p08_4" configurationId="ether_eth0.eth0_rxd3" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_rxdv_crsdv_rxctl.p08_5" configurationId="ether_eth0.eth0_rxdv_crsdv_rxctl" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_txclk_txc.p09_7" configurationId="ether_eth0.eth0_txclk_txc" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_txd0.p09_6" configurationId="ether_eth0.eth0_txd0" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_txd1.p09_5" configurationId="ether_eth0.eth0_txd1" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_txd2.p09_4" configurationId="ether_eth0.eth0_txd2" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_txd3.p09_3" configurationId="ether_eth0.eth0_txd3" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth0.eth0_txen_txctl.p10_0" configurationId="ether_eth0.eth0_txen_txctl" peripheral="ETHER_ETH0"/>
+      <configSetting altId="ether_eth1.eth1_refclk.p06_1" configurationId="ether_eth1.eth1_refclk" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_rxclk_ref_clk_rxc.p07_3" configurationId="ether_eth1.eth1_rxclk_ref_clk_rxc" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_rxd0.p06_6" configurationId="ether_eth1.eth1_rxd0" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_rxd1.p06_7" configurationId="ether_eth1.eth1_rxd1" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_rxd2.p07_0" configurationId="ether_eth1.eth1_rxd2" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_rxd3.p07_1" configurationId="ether_eth1.eth1_rxd3" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_rxdv_crsdv_rxctl.p07_2" configurationId="ether_eth1.eth1_rxdv_crsdv_rxctl" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_txclk_txc.p06_4" configurationId="ether_eth1.eth1_txclk_txc" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_txd0.p06_3" configurationId="ether_eth1.eth1_txd0" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_txd1.p06_2" configurationId="ether_eth1.eth1_txd1" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_txd2.p05_7" configurationId="ether_eth1.eth1_txd2" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_txd3.p06_0" configurationId="ether_eth1.eth1_txd3" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth1.eth1_txen_txctl.p06_5" configurationId="ether_eth1.eth1_txen_txctl" peripheral="ETHER_ETH1"/>
+      <configSetting altId="ether_eth2.eth2_refclk.p00_3" configurationId="ether_eth2.eth2_refclk" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_rxclk_ref_clk_rxc.p24_1" configurationId="ether_eth2.eth2_rxclk_ref_clk_rxc" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_rxd0.p23_7" configurationId="ether_eth2.eth2_rxd0" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_rxd1.p24_0" configurationId="ether_eth2.eth2_rxd1" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_rxd2.p24_2" configurationId="ether_eth2.eth2_rxd2" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_rxd3.p00_0" configurationId="ether_eth2.eth2_rxd3" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_rxdv_crsdv_rxctl.p00_1" configurationId="ether_eth2.eth2_rxdv_crsdv_rxctl" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_txclk_txc.p00_6" configurationId="ether_eth2.eth2_txclk_txc" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_txd0.p01_5" configurationId="ether_eth2.eth2_txd0" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_txd1.p01_4" configurationId="ether_eth2.eth2_txd1" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_txd2.p01_3" configurationId="ether_eth2.eth2_txd2" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_txd3.p01_2" configurationId="ether_eth2.eth2_txd3" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_eth2.eth2_txen_txctl.p00_2" configurationId="ether_eth2.eth2_txen_txctl" peripheral="ETHER_ETH2"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink0.p10_4" configurationId="ether_ethsw.ethsw_phylink0" peripheral="ETHER_ETHSW"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink1.p05_5" configurationId="ether_ethsw.ethsw_phylink1" peripheral="ETHER_ETHSW"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink2.p00_5" configurationId="ether_ethsw.ethsw_phylink2" peripheral="ETHER_ETHSW"/>
+      <configSetting altId="ether_gmac.gmac_mdc.p08_7" configurationId="ether_gmac.gmac_mdc" peripheral="ETHER_GMAC"/>
+      <configSetting altId="ether_gmac.gmac_mdio.p09_0" configurationId="ether_gmac.gmac_mdio" peripheral="ETHER_GMAC"/>
+      <configSetting altId="iic0.iic_scl0.p13_2" configurationId="iic0.iic_scl0" peripheral="IIC0"/>
+      <configSetting altId="iic0.iic_sda0.p13_3" configurationId="iic0.iic_sda0" peripheral="IIC0"/>
+      <configSetting altId="iic1.iic_scl1.p05_2" configurationId="iic1.iic_scl1" peripheral="IIC1"/>
+      <configSetting altId="iic1.iic_sda1.p05_3" configurationId="iic1.iic_sda1" peripheral="IIC1"/>
+      <configSetting altId="jtag_fslash_swd.tck_swclk.p02_7" configurationId="jtag_fslash_swd.tck_swclk" isUsedByDriver="true" peripheral="JTAG/SWD"/>
+      <configSetting altId="jtag_fslash_swd.tdi.p02_5" configurationId="jtag_fslash_swd.tdi" isUsedByDriver="true" peripheral="JTAG/SWD"/>
+      <configSetting altId="jtag_fslash_swd.tdo.p02_4" configurationId="jtag_fslash_swd.tdo" isUsedByDriver="true" peripheral="JTAG/SWD"/>
+      <configSetting altId="jtag_fslash_swd.tms_swdio.p02_6" configurationId="jtag_fslash_swd.tms_swdio" isUsedByDriver="true" peripheral="JTAG/SWD"/>
+      <configSetting altId="p03_0.output.low" configurationId="p03_0"/>
+      <configSetting altId="p04_1.output.low" configurationId="p04_1"/>
+      <configSetting altId="p04_4.output.low" configurationId="p04_4"/>
+      <configSetting altId="p05_0.output.low" configurationId="p05_0"/>
+      <configSetting altId="p05_4.input" configurationId="p05_4"/>
+      <configSetting altId="p13_4.output.low" configurationId="p13_4"/>
+      <configSetting altId="p13_5.input" configurationId="p13_5"/>
+      <configSetting altId="p13_6.input" configurationId="p13_6"/>
+      <configSetting altId="p13_7.input" configurationId="p13_7"/>
+      <configSetting altId="p14_0.output.low" configurationId="p14_0"/>
+      <configSetting altId="p14_1.output.low" configurationId="p14_1"/>
+      <configSetting altId="p14_3.output.low" configurationId="p14_3"/>
+      <configSetting altId="p16_3.input" configurationId="p16_3"/>
+      <configSetting altId="p17_3.output.low" configurationId="p17_3"/>
+      <configSetting altId="p18_2.output.low" configurationId="p18_2"/>
+      <configSetting altId="p20_1.output.low" configurationId="p20_1"/>
+      <configSetting altId="p20_2.output.low" configurationId="p20_2"/>
+      <configSetting altId="p20_3.output.low" configurationId="p20_3"/>
+      <configSetting altId="p20_4.output.low" configurationId="p20_4"/>
+      <configSetting altId="p22_1.output.low" configurationId="p22_1"/>
+      <configSetting altId="p22_3.output.low" configurationId="p22_3"/>
+      <configSetting altId="sci0.rxd_miso0.p16_6" configurationId="sci0.rxd_miso0" isUsedByDriver="true" peripheral="SCI0"/>
+      <configSetting altId="sci0.txd_mosi0.p16_5" configurationId="sci0.txd_mosi0" isUsedByDriver="true" peripheral="SCI0"/>
+      <configSetting altId="sci3.rxd_miso3.p17_7" configurationId="sci3.rxd_miso3" peripheral="SCI3"/>
+      <configSetting altId="sci3.txd_mosi3.p18_0" configurationId="sci3.txd_mosi3" peripheral="SCI3"/>
+      <configSetting altId="spi2.spi_miso2.p18_6" configurationId="spi2.spi_miso2" peripheral="SPI2"/>
+      <configSetting altId="spi2.spi_mosi2.p18_5" configurationId="spi2.spi_mosi2" peripheral="SPI2"/>
+      <configSetting altId="spi2.spi_rspck2.p18_4" configurationId="spi2.spi_rspck2" peripheral="SPI2"/>
+      <configSetting altId="spi2.spi_ssl20.p21_1" configurationId="spi2.spi_ssl20" peripheral="SPI2"/>
+      <configSetting altId="usb_hs.usb_ovrcur.p17_5" configurationId="usb_hs.usb_ovrcur" peripheral="USB_HS"/>
+      <configSetting altId="usb_hs.usb_vbusen.p19_0" configurationId="usb_hs.usb_vbusen" peripheral="USB_HS"/>
+      <configSetting altId="usb_hs.usb_vbusin.p07_4" configurationId="usb_hs.usb_vbusin" peripheral="USB_HS"/>
+      <configSetting altId="xspi0.xspi0_ckn.p14_5" configurationId="xspi0.xspi0_ckn" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_ckp.p14_6" configurationId="xspi0.xspi0_ckp" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_cs0_hash.p15_7" configurationId="xspi0.xspi0_cs0_hash" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_cs1_hash.p16_0" configurationId="xspi0.xspi0_cs1_hash" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_ds.p14_4" configurationId="xspi0.xspi0_ds" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_ecs0_hash.p14_2" configurationId="xspi0.xspi0_ecs0_hash" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_io0.p14_7" configurationId="xspi0.xspi0_io0" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_io1.p15_0" configurationId="xspi0.xspi0_io1" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_io2.p15_1" configurationId="xspi0.xspi0_io2" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_io3.p15_2" configurationId="xspi0.xspi0_io3" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_io4.p15_3" configurationId="xspi0.xspi0_io4" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_io5.p15_4" configurationId="xspi0.xspi0_io5" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_io6.p15_5" configurationId="xspi0.xspi0_io6" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_io7.p15_6" configurationId="xspi0.xspi0_io7" peripheral="XSPI0"/>
+      <configSetting altId="xspi0.xspi0_reset0_hash.p16_1" configurationId="xspi0.xspi0_reset0_hash" peripheral="XSPI0"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/projects/etherkit_ethercat_cherryecat/.settings/.rtmenus b/projects/etherkit_ethercat_cherryecat/.settings/.rtmenus
new file mode 100644
index 0000000000000000000000000000000000000000..37ba1251d128c4d33f160005fb30e493a9a696d2
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diff --git a/projects/etherkit_ethercat_cherryecat/.settings/etherkit_ethernet.JLink.Debug.rttlaunch b/projects/etherkit_ethercat_cherryecat/.settings/etherkit_ethernet.JLink.Debug.rttlaunch
new file mode 100644
index 00000000..a818e2d3
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.settings/etherkit_ethernet.JLink.Debug.rttlaunch
@@ -0,0 +1,93 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDeviceName" value="STM32F103VETx"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDownloadHex" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.forceQuitGdbServer" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="R9A07G084M04"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${debugger_install_path}/${jlink_debugger_relative_path}\JLinkGDBServerCL.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerRunAfterStopDebug" value="true"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.jlinkExecutable" value="${debugger_install_path}/${jlink_debugger_relative_path}\JLink.exe"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.runAfterDownload" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.serailBaudRate" value="115200"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.serailPort" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${studio_install_path}/repo/Extract/ToolChain_Support_Packages/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="etherkit_ethercat_cherryecat"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/etherkit_ethercat_cherryecat"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="UTF-8"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/projects/etherkit_ethercat_cherryecat/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs b/projects/etherkit_ethercat_cherryecat/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs
new file mode 100644
index 00000000..7dbfc8a7
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin
diff --git a/projects/etherkit_ethercat_cherryecat/.settings/language.settings.xml b/projects/etherkit_ethercat_cherryecat/.settings/language.settings.xml
new file mode 100644
index 00000000..1ba416b6
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1293010401648171129" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/projects/etherkit_ethercat_cherryecat/.settings/local_temp_storage.prefs b/projects/etherkit_ethercat_cherryecat/.settings/local_temp_storage.prefs
new file mode 100644
index 00000000..5ef7b9c4
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.settings/local_temp_storage.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+temp.toolchain.exec.path=C\:\\Softwares\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\10.2.1/bin
diff --git a/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.resources.prefs b/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 00000000..12ffae0b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+rtt-studio.preferences.renesas.configurator.root=C\:\\Renesas\\rzn\\sc_v2025-01_fsp_v2.2.0
diff --git a/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.runtime.prefs b/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.runtime.prefs
new file mode 100644
index 00000000..9f1acfcf
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.runtime.prefs
@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/.settings/projcfg.ini b/projects/etherkit_ethercat_cherryecat/.settings/projcfg.ini
new file mode 100644
index 00000000..4f926ed7
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.settings/projcfg.ini
@@ -0,0 +1,20 @@
+#RT-Thread Studio Project Configuration
+#Mon Sep 29 17:43:37 CST 2025
+project_type=rt-thread
+chip_name=R9A07G084
+os_branch=full
+example_name=
+os_version=5.1.0
+selected_rtt_version=5.1.0
+cfg_version=v3.0
+board_base_nano_proj=False
+is_use_scons_build=True
+output_project_path=C\:\\Users\\RTT\\Desktop\\github\\sdk-bsp-rzn2l-etherkit\\projects
+project_base_bsp=true
+hardware_adapter=J-Link
+project_name=etherkit_ethercat_cherryecat
+is_base_example_project=False
+board_name=EtherKit
+device_vendor=RENESAS
+bsp_path=repo/Extract/Board_Support_Packages/RealThread/EtherKit/1.3.0
+bsp_version=1.3.0
diff --git a/projects/etherkit_ethercat_cherryecat/.settings/standalone.prefs b/projects/etherkit_ethercat_cherryecat/.settings/standalone.prefs
new file mode 100644
index 00000000..91d11822
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/.settings/standalone.prefs
@@ -0,0 +1,43 @@
+#Sat Oct 11 14:47:50 CST 2025
+com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.ld
+com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.3.fsp.2.2.0/all=1441545198,rzn/arm/CMSIS_5/LICENSE.txt|4247764709,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.3.fsp.2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.2.0/all=3491271161,script/fsp_xspi0_boot.ld|2137037368,rzn/board/rzn2l_rsk/board_leds.c|1608455294,rzn/board/rzn2l_rsk/board_init.c|2679402475,rzn/board/rzn2l_rsk/board.h|1041253830,rzn/board/rzn2l_rsk/board_ethernet_phy.h|3351740966,rzn/board/rzn2l_rsk/board_leds.h|1088084076,rzn/board/rzn2l_rsk/board_init.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.2.0/all=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.2.0/all=3932580821,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.2.0/all=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.2.0/all=1460414581,rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c|2321958380,rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h|4149273342,rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h|4147125589,rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c|3928882208,rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h|3186817992,rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.2.0/all=500553905,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1691547853,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|71901562,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c|3810050431,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c|1181297824,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A09G087.h|3932580821,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1374776167,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|4128110811,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h|1949300192,rzn/fsp/src/bsp/mcu/all/bsp_io.h|3419808366,rzn/fsp/src/bsp/mcu/all/bsp_cache.h|4281041128,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h|1056966381,rzn/fsp/src/bsp/mcu/all/bsp_tzc400.h|1853261550,rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.h|2340541415,rzn/fsp/src/bsp/mcu/all/bsp_io.c|777766746,rzn/fsp/src/bsp/mcu/all/bsp_common.h|2159935905,rzn/fsp/src/bsp/mcu/all/bsp_reset.h|3805041378,rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h|1518075339,rzn/fsp/src/bsp/mcu/all/bsp_irq.h|2813797547,rzn/fsp/src/bsp/mcu/all/bsp_tfu.h|3052576126,rzn/fsp/src/bsp/mcu/all/bsp_delay.c|620909623,rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2485735290,rzn/fsp/src/bsp/mcu/all/bsp_clocks.h|3899420712,rzn/fsp/src/bsp/mcu/all/bsp_common.c|155435521,rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.c|288171482,rzn/fsp/src/bsp/mcu/all/bsp_clocks.c|358325813,rzn/fsp/src/bsp/mcu/all/bsp_irq.c|3035572228,rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c|1122404825,rzn/fsp/src/bsp/mcu/all/bsp_cache.c|3375215354,rzn/fsp/src/bsp/mcu/all/bsp_tzc400.c|4004178582,rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h|4171127952,rzn/fsp/src/bsp/mcu/all/bsp_address_expander.h|4237692344,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c|3075072751,rzn/fsp/src/bsp/mcu/all/bsp_reset.c|3404759526,rzn/fsp/src/bsp/mcu/all/bsp_ddr.h|3509889979,rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h|779228178,rzn/fsp/src/bsp/mcu/all/bsp_ddr.c|1356272951,rzn/fsp/src/bsp/mcu/all/bsp_address_expander.c|1889702459,rzn/fsp/src/bsp/mcu/all/bsp_semaphore.h|2618260322,rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.h|3762948597,rzn/fsp/src/bsp/mcu/all/bsp_delay.h|3775213019,rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.c|3027953462,rzn/fsp/src/bsp/mcu/all/bsp_semaphore.c|3902133153,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h|2249528202,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h|1591030987,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c|2628857650,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c|1476552636,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c|237502674,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h|310861080,rzn/fsp/inc/fsp_features.h|610410096,rzn/fsp/inc/fsp_version.h|4252924486,rzn/fsp/inc/fsp_common_api.h|4017611099,rzn/fsp/inc/instances/r_ioport.h|474542689,rzn/fsp/inc/api/bsp_api.h|2795021536,rzn/fsp/inc/api/r_ioport_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_phy\#\#\#\#2.2.0/all=3419091927,rzn/fsp/src/r_ether_phy/r_ether_phy.c|204740734,rzn/fsp/inc/instances/r_ether_phy.h|3519950923,rzn/fsp/inc/api/r_ether_phy_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_phy\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_selector\#\#\#\#2.2.0/all=3452251033,rzn/fsp/src/r_ether_selector/r_ether_selector.c|1141164539,rzn/fsp/inc/instances/r_ether_selector.h|786475994,rzn/fsp/inc/api/r_ether_selector_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_selector\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ethsw\#\#\#\#2.2.0/all=1725931930,rzn/fsp/src/r_ethsw/r_ethsw.c|3863987970,rzn/fsp/inc/instances/r_ethsw.h|3935299353,rzn/fsp/inc/api/r_ether_switch_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ethsw\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gmac\#\#\#\#2.2.0/all=2767674387,rzn/fsp/src/r_gmac/r_gmac.c|3604085163,rzn/fsp/inc/instances/r_gmac.h|1576079366,rzn/fsp/inc/api/r_ether_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gmac\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#2.2.0/all=1701283242,rzn/fsp/src/r_gpt/r_gpt.c|3514125611,rzn/fsp/inc/instances/r_gpt.h|2833340986,rzn/fsp/inc/api/r_timer_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.2.0/all=824647496,rzn/fsp/src/r_ioport/r_ioport.c|4017611099,rzn/fsp/inc/instances/r_ioport.h|2795021536,rzn/fsp/inc/api/r_ioport_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_mtu3\#\#\#\#2.2.0/all=3441005877,rzn/fsp/src/r_mtu3/r_mtu3.c|2585942167,rzn/fsp/inc/instances/r_mtu3.h|2833340986,rzn/fsp/inc/api/r_timer_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_mtu3\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.2.0/all=2555335099,rzn/fsp/src/r_sci_uart/r_sci_uart.c|257214413,rzn/fsp/inc/instances/r_sci_uart.h|300185683,rzn/fsp/inc/api/r_uart_api.h|2744795673,rzn/fsp/inc/api/r_transfer_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#2.2.0/all=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#2.2.0/libraries=
+com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false
+com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_on_ether.1094288014=false
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_phy_on_ether_phy.277662383=false
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_phy_on_ether_phy.513125102=false
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_phy_on_ether_phy.518802053=false
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.1968866849=false
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.86814920=false
diff --git a/projects/etherkit_ethercat_cherryecat/Kconfig b/projects/etherkit_ethercat_cherryecat/Kconfig
new file mode 100644
index 00000000..3a9e894c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/Kconfig
@@ -0,0 +1,34 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "rt-thread"
+
+# you can change the RTT_ROOT default "rt-thread"
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config ENV_DIR
+    string
+    option env="ENV_ROOT"
+    default "/"
+
+config PLATFORM_DIR
+    string
+    option env="PLATFORM_DIR"
+    default "C:/Users/RTT/Desktop/github/sdk-bsp-rzn2l-etherkit/projects/etherkit_ethercat_cherryecat/platform"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "libraries/Kconfig"
+source "$BSP_DIR/board/Kconfig"
diff --git a/projects/etherkit_ethercat_cherryecat/README.md b/projects/etherkit_ethercat_cherryecat/README.md
new file mode 100644
index 00000000..855ade92
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/README.md
@@ -0,0 +1,51 @@
+# CherryECAT Driver Usage Instructions
+
+**English** | [**中文**](./README_zh.md)
+
+## Introduction
+
+This project provides cherryecat demo.
+
+## Hardware Connection
+
+To use Ethernet, connect the development board to any one of the three network ports using an Ethernet cable, and the other end should be connected to a network switch that has internet access.
+
+## FSP Configuration Instructions
+
+Open the project configuration file `configuration.xml` and add the `r_gamc` stack:
+
+![image-20241126104408737](figures/image-20241126104408737.png)
+
+Next, click on `g_ether0 Ethernet`, and configure the interrupt callback function to `user_ether0_callback`:
+
+![image-20241126104422910](figures/image-20241126104422910.png)
+
+Now configure the PHY settings. Select `g_ether_phy0`, set the common configuration to "User Own Target", change the PHY LSI address to `1` (refer to the schematic for the exact address), and set the PHY initialization callback function to `ether_phy_targets_initialize_rtl8211_rgmii()`. Also, set the MDIO to GMAC.
+
+![image-20241126104437432](figures/image-20241126104437432.png)
+
+Next, configure `g_ether_selector0`, set the Ethernet mode to "Switch Mode", set the PHY link to "Default Active-Low", and choose "RGMII" for the PHY interface mode.
+
+![image-20241126104519290](figures/image-20241126104519290.png)
+
+Configure the Ethernet pin parameters and select the operating mode to RGMII:
+
+![image-20241126104533098](figures/image-20241126104533098.png)
+
+Finally, configure `ETHER_GMAC`:
+
+![image-20241126104603633](figures/image-20241126104603633.png)
+
+## RT-Thread Studio Configuration
+
+Return to the Studio project, and configure RT-Thread Settings. Click on "Hardware", find the chip device driver, and enable Ethernet:
+
+![image-20241126104852383](figures/image-20241126104852383.png)
+
+## Running Results
+
+![cherryecat](figures/cherryecat1.png)
+![cherryecat](figures/cherryecat2.png)
+![cherryecat](figures/cherryecat3.png)
+![cherryecat](figures/cherryecat4.png)
+![cherryecat](figures/cherryecat5.png)
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/README_zh.md b/projects/etherkit_ethercat_cherryecat/README_zh.md
new file mode 100644
index 00000000..b9d5e994
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/README_zh.md
@@ -0,0 +1,51 @@
+# CherryECAT 驱动示例
+
+**中文** | [**English**](./README.md)
+
+## 简介
+
+本工程提供 cherryecat 的基础功能
+
+## 硬件连接
+
+需要使用网线连接到开发板的三网口其中任意一个网口，另一头连接到可以联网的交换机上。
+
+## FSP配置说明
+
+打开工程配置文件configuration.xml，新增r_gamc Stack：
+
+![image-20241126104408737](figures/image-20241126104408737.png)
+
+点击g_ether0 Ethernet，配置中断回调函数为user_ether0_callback：
+
+![image-20241126104422910](figures/image-20241126104422910.png)
+
+下面配置phy信息，选择g_ether_phy0，Common配置为User Own Target；修改PHY LSI地址为1（根据原理图查询具体地址）；设置phy初始化回调函数为ether_phy_targets_initialize_rtl8211_rgmii()；同时设置MDIO为GMAC。
+
+![image-20241126104437432](figures/image-20241126104437432.png)
+
+配置g_ether_selector0，选择以太网模式为交换机模式，PHY link设置为默认active-low，PHY接口模式设置为RGMII。
+
+![image-20241126104519290](figures/image-20241126104519290.png)
+
+网卡引脚参数配置，选择操作模式为RGMII：
+
+![image-20241126104533098](figures/image-20241126104533098.png)
+
+ETHER_GMAC配置：
+
+![image-20241126104603633](figures/image-20241126104603633.png)
+
+## RT-Thread Studio配置
+
+回到Studio工程，配置RT-Thread Settings，点击选择硬件选项，找到芯片设备驱动，使能以太网；
+
+![image-20241126104852383](figures/image-20241126104852383.png)
+
+## 运行效果
+
+![cherryecat](figures/cherryecat1.png)
+![cherryecat](figures/cherryecat2.png)
+![cherryecat](figures/cherryecat3.png)
+![cherryecat](figures/cherryecat4.png)
+![cherryecat](figures/cherryecat5.png)
diff --git a/projects/etherkit_ethercat_cherryecat/SConscript b/projects/etherkit_ethercat_cherryecat/SConscript
new file mode 100644
index 00000000..1b700776
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/SConscript
@@ -0,0 +1,27 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+from gcc import *
+
+cwd = GetCurrentDir()
+src = []
+CPPPATH = [cwd]
+group = []
+list = os.listdir(cwd)
+
+CPPDEFINES = ['_RZN_ORDINAL=1']
+
+if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM():
+    if rtconfig.PLATFORM == 'iccarm' or GetOption('target') != 'mdk5':
+        CPPPATH = [cwd + '/src']
+        src = Glob('./src/*.c')
+        group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        group = group + SConscript(os.path.join(d, 'SConscript'))
+
+Return('group')
diff --git a/projects/etherkit_ethercat_cherryecat/SConstruct b/projects/etherkit_ethercat_cherryecat/SConstruct
new file mode 100644
index 00000000..e900110c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/SConstruct
@@ -0,0 +1,56 @@
+import os
+import sys
+import rtconfig
+
+if os.path.exists('rt-thread'):
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/rt-thread')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except Exception as e:
+    print("Error message:", e.message)
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    sys.exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+rtconfig.BSP_LIBRARY_TYPE = None
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/projects/etherkit_ethercat_cherryecat/board/Kconfig b/projects/etherkit_ethercat_cherryecat/board/Kconfig
new file mode 100644
index 00000000..4c3fef35
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/board/Kconfig
@@ -0,0 +1,572 @@
+menu "Hardware Drivers Config"
+
+    config SOC_R9A07G084
+        bool
+        select SOC_SERIES_R9A07G0
+        select RT_USING_COMPONENTS_INIT
+        select RT_USING_USER_MAIN
+        default y
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "On-chip Peripheral Drivers"
+
+        source "libraries/HAL_Drivers/Kconfig"
+
+        menuconfig BSP_USING_UART
+            bool "Enable UART"
+            default y
+            select RT_USING_SERIAL
+            select RT_USING_SERIAL_V2
+            if BSP_USING_UART
+                menuconfig BSP_USING_UART0
+                    bool "Enable UART0"
+                    default n
+                    if BSP_USING_UART0
+                        config BSP_UART0_RX_USING_DMA
+                            bool "Enable UART0 RX DMA"
+                            depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART0_TX_USING_DMA
+                            bool "Enable UART0 TX DMA"
+                            depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART0_RX_BUFSIZE
+                            int "Set UART0 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART0_TX_BUFSIZE
+                            int "Set UART0 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+                    
+                menuconfig BSP_USING_UART5
+                    bool "Enable UART5"
+                    default n
+                    if BSP_USING_UART5
+                        config BSP_UART5_RX_USING_DMA
+                            bool "Enable UART5 RX DMA"
+                            depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART5_TX_USING_DMA
+                            bool "Enable UART5 TX DMA"
+                            depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART5_RX_BUFSIZE
+                            int "Set UART5 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART5_TX_BUFSIZE
+                            int "Set UART5 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+            endif
+
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            default n
+            select RT_USING_ADC
+            if BSP_USING_ADC
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
+                config BSP_USING_ADC1
+                    bool "Enable ADC1"
+                config BSP_USING_ADC2
+                    bool "Enable ADC2"
+                config BSP_USING_ADC3
+                    bool "Enable ADC3"                    
+                    default n
+            endif
+
+        menuconfig BSP_USING_CANFD
+            bool "Enable CANFD"
+            default n
+            select RT_USING_CAN
+            select RT_CAN_USING_CANFD
+            if BSP_USING_CANFD
+            	config BSP_USING_CAN_RZ
+                    bool "Enabled this option means turning on standard CAN, while disabling it means switching to CANFD."
+                    default n
+                config BSP_USING_CANFD0
+                    bool "Enable CANFD0"
+                    default n
+                config BSP_USING_CANFD1
+                    bool "Enable CANFD1"
+                    default n
+            endif
+
+        menuconfig BSP_USING_SCI
+            bool "Enable SCI Controller"
+            default n
+            config BSP_USING_SCIn_SPI
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_SPI
+                default n
+
+            config BSP_USING_SCIn_I2C
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_I2C
+                default n
+
+            config BSP_USING_SCIn_UART
+                bool
+                depends on BSP_USING_SCI
+                select RT_USING_SERIAL
+                select RT_USING_SERIAL_V2
+                default n
+
+            if BSP_USING_SCI
+                config BSP_USING_SCI0
+                    bool "Enable SCI0"
+                    default n
+                    if BSP_USING_SCI0
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI0_SPI
+                        config BSP_USING_SCI0_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI0_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI0_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI0_UART
+                            config BSP_SCI0_UART_RX_BUFSIZE
+                                int "Set UART0 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI0_UART_TX_BUFSIZE
+                                int "Set UART0 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI1
+                    bool "Enable SCI1"
+                    default n
+                    if BSP_USING_SCI1
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI1_SPI
+                        config BSP_USING_SCI1_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI1_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI1_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI1_UART
+                            config BSP_SCI1_UART_RX_BUFSIZE
+                                int "Set UART1 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI1_UART_TX_BUFSIZE
+                                int "Set UART1 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI2
+                    bool "Enable SCI2"
+                    default n
+                    if BSP_USING_SCI2
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI2_SPI
+                        config BSP_USING_SCI2_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI2_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI2_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI2_UART
+                            config BSP_SCI2_UART_RX_BUFSIZE
+                                int "Set UART2 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI2_UART_TX_BUFSIZE
+                                int "Set UART2 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI3
+                    bool "Enable SCI3"
+                    default n
+                    if BSP_USING_SCI3
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI3_SPI
+                        config BSP_USING_SCI3_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI3_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI3_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI3_UART
+                            config BSP_SCI3_UART_RX_BUFSIZE
+                                int "Set UART3 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI3_UART_TX_BUFSIZE
+                                int "Set UART3 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI4
+                    bool "Enable SCI4"
+                    default n
+                    if BSP_USING_SCI4
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI4_SPI
+                        config BSP_USING_SCI4_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI4_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI4_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI4_UART
+                            config BSP_SCI4_UART_RX_BUFSIZE
+                                int "Set UART4 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI4_UART_TX_BUFSIZE
+                                int "Set UART4 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI5
+                    bool "Enable SCI5"
+                    default n
+                    if BSP_USING_SCI5
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI5_SPI
+                        config BSP_USING_SCI5_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI5_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI5_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI5_UART
+                            config BSP_SCI5_UART_RX_BUFSIZE
+                                int "Set UART5 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI5_UART_TX_BUFSIZE
+                                int "Set UART5 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI6
+                    bool "Enable SCI6"
+                    default n
+                    if BSP_USING_SCI6
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI6_SPI
+                        config BSP_USING_SCI6_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI6_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI6_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI6_UART
+                            config BSP_SCI6_UART_RX_BUFSIZE
+                                int "Set UART6 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI6_UART_TX_BUFSIZE
+                                int "Set UART6 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI7
+                    bool "Enable SCI7"
+                    default n
+                    if BSP_USING_SCI7
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI7_SPI
+                        config BSP_USING_SCI7_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI7_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI7_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI7_UART
+                            config BSP_SCI7_UART_RX_BUFSIZE
+                                int "Set UART7 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI7_UART_TX_BUFSIZE
+                                int "Set UART7 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI8
+                    bool "Enable SCI8"
+                    default n
+                    if BSP_USING_SCI8
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI8_SPI
+                        config BSP_USING_SCI8_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI8_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI8_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI8_UART
+                            config BSP_SCI8_UART_RX_BUFSIZE
+                                int "Set UART8 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI8_UART_TX_BUFSIZE
+                                int "Set UART8 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+                config BSP_USING_SCI9
+                    bool "Enable SCI9"
+                    default n
+                    if BSP_USING_SCI9
+                        choice
+                        prompt "choice sci mode"
+                        default BSP_USING_SCI9_SPI
+                        config BSP_USING_SCI9_SPI
+                            select BSP_USING_SCIn_SPI
+                            bool "SPI mode"
+                        config BSP_USING_SCI9_I2C
+                            select BSP_USING_SCIn_I2C
+                            bool "I2C mode"
+                        config BSP_USING_SCI9_UART
+                            select BSP_USING_SCIn_UART
+                            bool "UART mode"
+                        endchoice
+                        if BSP_USING_SCI9_UART
+                            config BSP_SCI9_UART_RX_BUFSIZE
+                                int "Set UART9 RX buffer size"
+                                range 64 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 256
+
+                            config BSP_SCI9_UART_TX_BUFSIZE
+                                int "Set UART9 TX buffer size"
+                                range 0 65535
+                                depends on RT_USING_SERIAL_V2
+                                default 0
+                        endif
+                    endif
+            endif
+
+        config BSP_USING_HYPERRAM
+            bool "Enable XSPI0 CS1 Winbond octal hyperRAM"
+            default n
+
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C BUS"
+            default n
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            select RT_USING_PIN
+            if BSP_USING_I2C
+                config BSP_USING_HW_I2C
+                    bool "Enable Hardware I2C BUS"
+                    default n
+                if BSP_USING_HW_I2C
+                    config BSP_USING_HW_I2C0
+                        bool "Enable Hardware I2C0 BUS"
+                        default n
+                endif
+                if BSP_USING_HW_I2C
+                    config BSP_USING_HW_I2C1
+                        bool "Enable Hardware I2C1 BUS"
+                        default n
+                endif
+            if !BSP_USING_HW_I2C
+                    menuconfig BSP_USING_I2C1
+                        bool "Enable I2C1 BUS (software simulation)"
+                        default y
+                        if BSP_USING_I2C1
+                            config BSP_I2C1_SCL_PIN
+                                hex "i2c1 scl pin number"
+                                range 0x0000 0x0B0F
+                                default 0x0B03
+                            config BSP_I2C1_SDA_PIN
+                                hex "I2C1 sda pin number"
+                                range 0x0000 0x0B0F
+                                default 0x050E
+                    endif
+                endif
+            endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI BUS"
+            default n
+            select RT_USING_SPI
+            if BSP_USING_SPI 
+                config BSP_USING_SPI0
+                    bool "Enable SPI0 BUS"
+                    default n
+                config BSP_USING_SPI1
+                    bool "Enable SPI1 BUS"
+                    default n
+                config BSP_USING_SPI2
+                    bool "Enable SPI2 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_TIM
+	        bool "Enable timer"
+	        default n
+	        select RT_USING_HWTIMER
+	        if BSP_USING_TIM
+	            config BSP_USING_TIM0
+	                bool "Enable TIM0"
+	                default n
+	            config BSP_USING_TIM1
+	                bool "Enable TIM1"
+	                default n
+	        endif
+
+        menuconfig BSP_USING_PWM
+            bool "Enable PWM"
+            default n
+            select RT_USING_PWM
+            if BSP_USING_PWM
+                config BSP_USING_PWM5
+                    bool "Enable GPT5 (32-Bits) output PWM"
+                    default n
+            endif
+
+        config BSP_USING_ETH
+            bool "Enable Ethernet"
+            select RT_USING_SAL
+            select RT_USING_LWIP
+            select RT_USING_NETDEV
+            default n
+
+    endmenu
+    
+    menu "Board extended module Drivers"
+         menuconfig BSP_USING_RW007
+                bool "Enable RW007"
+                default n
+                select PKG_USING_RW007
+                select BSP_USING_SPI
+                select BSP_USING_SPI2
+                select RT_USING_MEMPOOL
+                select RW007_NOT_USE_EXAMPLE_DRIVERS
+
+            if BSP_USING_RW007
+                config RA_RW007_SPI_BUS_NAME
+                    string "RW007 BUS NAME"
+                    default "spi2"
+
+                config RA_RW007_CS_PIN
+                    hex "(HEX)CS pin index"
+                    default 0x1207
+
+                config RA_RW007_BOOT0_PIN
+                    hex "(HEX)BOOT0 pin index (same as spi clk pin)"
+                    default 0x1204
+
+                config RA_RW007_BOOT1_PIN
+                    hex "(HEX)BOOT1 pin index (same as spi cs pin)"
+                    default 0x1207
+
+                config RA_RW007_INT_BUSY_PIN
+                    hex "(HEX)INT/BUSY pin index"
+                    default 0x1102
+
+                config RA_RW007_RST_PIN
+                    hex "(HEX)RESET pin index"
+                    default 0x1706
+            endif
+    endmenu
+endmenu
diff --git a/projects/etherkit_ethercat_cherryecat/board/SConscript b/projects/etherkit_ethercat_cherryecat/board/SConscript
new file mode 100644
index 00000000..a27ea8e4
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/board/SConscript
@@ -0,0 +1,16 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+CPPPATH = [cwd]
+src = Glob('*.c')
+
+objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
diff --git a/projects/etherkit_ethercat_cherryecat/board/board.h b/projects/etherkit_ethercat_cherryecat/board/board.h
new file mode 100644
index 00000000..8d16dfc1
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/board/board.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-03-11    Wangyuqiang   first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtdef.h>
+#include <cp15.h>
+#include <hal_data.h>
+
+#define RZ_SRAM_SIZE    1536 /* The SRAM size of the chip needs to be modified */
+#define RZ_SRAM_END     (0x10000000 + RZ_SRAM_SIZE * 1024 - 1)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RAM_END$$ZI$$Base;
+#define HEAP_BEGIN  ((void *)&Image$$RAM_END$$ZI$$Base)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end__;
+#define HEAP_BEGIN      ((void *)&__bss_end__)
+#endif
+
+#define HEAP_END        RZ_SRAM_END
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define MAX_HANDLERS BSP_VECTOR_TABLE_MAX_ENTRIES
+#define GIC_IRQ_START   0
+#define GIC_ACK_INTID_MASK  (0x000003FFU)
+/* number of interrupts on board */
+#define ARM_GIC_NR_IRQS     (448)
+/* only one GIC available */
+#define ARM_GIC_MAX_NR      1
+/*  end defined */
+
+#define GICV3_DISTRIBUTOR_BASE_ADDR     (0x100000)
+
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    rt_uint32_t gic_base;
+
+    __get_cp(15, 1, gic_base, 15, 3, 0);
+    return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/board/ec_config.h b/projects/etherkit_ethercat_cherryecat/board/ec_config.h
new file mode 100644
index 00000000..a57bb284
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/board/ec_config.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_CONFIG_H
+#define EC_CONFIG_H
+
+#include "rtthread.h"
+
+#define CONFIG_EC_PRINTF(...) rt_kprintf(__VA_ARGS__)
+
+#ifndef CONFIG_EC_DBG_LEVEL
+#define CONFIG_EC_DBG_LEVEL EC_DBG_INFO
+#endif
+
+#ifndef CONFIG_EC_SLAVE_DBG_LEVEL
+#define CONFIG_EC_SLAVE_DBG_LEVEL EC_DBG_INFO
+#endif
+
+/* Enable print with color */
+#define CONFIG_EC_PRINTF_COLOR_ENABLE
+
+#define EC_FAST_CODE_SECTION
+
+#ifndef CONFIG_EC_MAX_NETDEVS
+#define CONFIG_EC_MAX_NETDEVS 1
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_PRIO
+#define CONFIG_EC_NONPERIOD_PRIO 0
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_STACKSIZE
+#define CONFIG_EC_NONPERIOD_STACKSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_INTERVAL_MS
+#define CONFIG_EC_NONPERIOD_INTERVAL_MS 10
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_WAITERS
+#define CONFIG_EC_NONPERIOD_WAITERS 20
+#endif
+
+#ifndef CONFIG_EC_SCAN_PRIO
+#define CONFIG_EC_SCAN_PRIO 1
+#endif
+
+#ifndef CONFIG_EC_SCAN_STACKSIZE
+#define CONFIG_EC_SCAN_STACKSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_SCAN_INTERVAL_MS
+#define CONFIG_EC_SCAN_INTERVAL_MS 100
+#endif
+
+#ifndef CONFIG_EC_PER_SM_MAX_PDOS
+#define CONFIG_EC_PER_SM_MAX_PDOS 8
+#endif
+
+#ifndef CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES
+#define CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES 8
+#endif
+
+#define CONFIG_EC_PERF_ENABLE
+#define CONFIG_EC_CMD_ENABLE
+#define CONFIG_EC_TIMESTAMP_CUSTOM
+#define CONFIG_EC_PHY_CUSTOM
+
+#ifndef CONFIG_EC_MAX_PDO_BUFSIZE
+#define CONFIG_EC_MAX_PDO_BUFSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_MAX_ENET_TXBUF_COUNT
+#define CONFIG_EC_MAX_ENET_TXBUF_COUNT 10
+#endif
+
+#ifndef CONFIG_EC_MAX_ENET_RXBUF_COUNT
+#define CONFIG_EC_MAX_ENET_RXBUF_COUNT 10
+#endif
+
+// #define CONFIG_EC_FOE
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/board/ports/SConscript b/projects/etherkit_ethercat_cherryecat/board/ports/SConscript
new file mode 100644
index 00000000..e8ac9ae5
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/board/ports/SConscript
@@ -0,0 +1,16 @@
+import os
+from building import *
+
+objs = []
+src = Glob('*.c')
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
diff --git a/projects/etherkit_ethercat_cherryecat/board/ports/gpio_cfg.h b/projects/etherkit_ethercat_cherryecat/board/ports/gpio_cfg.h
new file mode 100644
index 00000000..d179d4ab
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/board/ports/gpio_cfg.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2024-03-11    Wangyuqiang   first version
+ */
+
+/* Number of IRQ channels on the device */
+#define RA_IRQ_MAX  16
+
+/* PIN to IRQx table */
+#define PIN2IRQX_TABLE                      \
+{                                           \
+    switch (pin)                            \
+    {                                       \
+    case BSP_IO_PORT_00_PIN_1:             \
+    case BSP_IO_PORT_09_PIN_2:             \
+    case BSP_IO_PORT_18_PIN_3:             \
+        return 0;                           \
+    case BSP_IO_PORT_00_PIN_3:             \
+    case BSP_IO_PORT_07_PIN_4:             \
+    case BSP_IO_PORT_18_PIN_4:             \
+        return 1;                           \
+    case BSP_IO_PORT_01_PIN_2:             \
+        return 2;                           \
+    case BSP_IO_PORT_01_PIN_4:             \
+        return 3;                           \
+    case BSP_IO_PORT_02_PIN_0:             \
+    case BSP_IO_PORT_22_PIN_2:             \
+        return 4;                           \
+    case BSP_IO_PORT_03_PIN_5:             \
+    case BSP_IO_PORT_13_PIN_2:             \
+        return 5;                           \
+    case BSP_IO_PORT_14_PIN_2:             \
+    case BSP_IO_PORT_21_PIN_5:             \
+        return 6;                           \
+    case BSP_IO_PORT_16_PIN_3:             \
+        return 7;                           \
+    case BSP_IO_PORT_03_PIN_6:             \
+    case BSP_IO_PORT_16_PIN_6:             \
+        return 8;                           \
+    case BSP_IO_PORT_03_PIN_7:             \
+    case BSP_IO_PORT_21_PIN_6:             \
+        return 9;                           \
+    case BSP_IO_PORT_04_PIN_4:             \
+    case BSP_IO_PORT_18_PIN_1:             \
+    case BSP_IO_PORT_21_PIN_7:             \
+        return 10;                          \
+    case BSP_IO_PORT_10_PIN_4:             \
+    case BSP_IO_PORT_18_PIN_6:             \
+        return 11;                          \
+    case BSP_IO_PORT_05_PIN_0:             \
+    case BSP_IO_PORT_05_PIN_4:             \
+    case BSP_IO_PORT_05_PIN_6:             \
+        return 12;                          \
+    case BSP_IO_PORT_00_PIN_4:             \
+    case BSP_IO_PORT_00_PIN_7:             \
+    case BSP_IO_PORT_05_PIN_1:             \
+        return 13;                          \
+    case BSP_IO_PORT_02_PIN_2:             \
+    case BSP_IO_PORT_03_PIN_0:             \
+    case BSP_IO_PORT_05_PIN_2:             \
+        return 14;                          \
+    case BSP_IO_PORT_02_PIN_3:             \
+    case BSP_IO_PORT_05_PIN_3:             \
+    case BSP_IO_PORT_22_PIN_0:             \
+        return 15;                          \
+    default  :                              \
+        return -1;                          \
+    }                                       \
+}
diff --git a/projects/etherkit_ethercat_cherryecat/buildinfo.ipcf b/projects/etherkit_ethercat_cherryecat/buildinfo.ipcf
new file mode 100644
index 00000000..f9b42655
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/buildinfo.ipcf
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<iarProjectConnection version="1.8" name="Flex Software">
+    <device>
+        <name>R9A07G084M04</name>
+    </device>
+    <includePath>
+    </includePath>
+    <defines>
+        <define>_RZN_ORDINAL=1</define>
+        <define>_RZN_CORE=CR52_0</define>
+        <define>_RENESAS_RZN_</define>
+    </defines>
+    <asmIncludePath>
+    </asmIncludePath>
+    <asmDefines>
+        <define>_RZN_ORDINAL=1</define>
+        <define>_RZN_CORE=CR52_0</define>
+        <define>_RENESAS_RZN_</define>
+    </asmDefines>
+    <linkerFile>
+        <override>true</override>
+        <path>$PROJ_DIR$/script/fsp_xspi0_boot.icf</path>
+    </linkerFile>
+    <linkerExtraOptions>
+        <arg>--config_search "$PROJ_DIR$"</arg>
+    </linkerExtraOptions>
+    <programEntryPoint>
+        <symbol>system_init</symbol>
+    </programEntryPoint>
+    <customArgVars>
+        <group name="RA Smart Configurator">
+            <argVar>
+                <name>RASC_EXE_PATH</name>
+                <value>C:\Renesas\rzn\sc_v2024-01.1_fsp_v2.0.0\eclipse\rasc.exe</value>
+            </argVar>
+        </group>
+    </customArgVars>
+    <files>
+    </files>
+</iarProjectConnection>
diff --git a/projects/etherkit_ethercat_cherryecat/buildinfo.json b/projects/etherkit_ethercat_cherryecat/buildinfo.json
new file mode 100644
index 00000000..27190c01
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/buildinfo.json
@@ -0,0 +1,35 @@
+{
+  "definedMacros": [
+    "_RZN_ORDINAL=1",
+    "_RZN_CORE=CR52_0",
+    "_RENESAS_RZN_"
+  ],
+  "sourcePaths": [
+    "rzn",
+    "rzn_gen",
+    "src"
+  ],
+  "excludedFilePaths": [],
+  "includePaths": [
+    "rzn/arm/CMSIS_5/CMSIS/Core_A/Include",
+    "rzn/arm/CMSIS_5/CMSIS/Core_R/Include",
+    "rzn/fsp/inc",
+    "rzn/fsp/inc/api",
+    "rzn/fsp/inc/instances",
+    "rzn/fsp/src/bsp/mcu/all/cr",
+    "rzn_cfg/fsp_cfg",
+    "rzn_cfg/fsp_cfg/bsp",
+    "rzn_gen",
+    "src"
+  ],
+  "libraryPaths": [],
+  "libraryNames": [],
+  "objectFiles": [],
+  "linkerScript": "script/fsp_xspi0_boot.ld",
+  "targetDeviceName": "R9A07G084M04GBG",
+  "entrySymbol": "system_init",
+  "isPreBuildContentGenEnabled": true,
+  "isPostBuildContentGenEnabled": true,
+  "isTargetDeviceSupportsTrustZone": false,
+  "buildOptionsMap": {}
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/configuration.xml b/projects/etherkit_ethercat_cherryecat/configuration.xml
new file mode 100644
index 00000000..f1046a25
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/configuration.xml
@@ -0,0 +1,1694 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="10">
+  <generalSettings>
+    <option key="#Board#" value="board.rzn2lrsk.xspi0_x1"/>
+    <option key="CPU" value="RZN2L"/>
+    <option key="Core" value="CR52_0"/>
+    <option key="#TargetName#" value="R9A07G084M04GBG"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-r52"/>
+    <option key="#DeviceCommand#" value="R9A07G084M04"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R9A07G084M04GBG.pincfg"/>
+    <option key="#FSPVersion#" value="2.2.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##rzn2l_rsk##xspi0_x1_boot"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="gcc-arm-embedded"/>
+    <option key="#ToolchainVersion#" value=""/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.board.rzn2lrsk.xspi0_x1">
+      <property id="config.board.cache_flg" value="0x00000000"/>
+      <property id="config.board.wrapcfg_v" value="0x00000000"/>
+      <property id="config.board.comcfg_v" value="0x00000000"/>
+      <property id="config.board.bmcfg_v" value="0x00000000"/>
+      <property id="config.board.xspi_flg" value="0x00000000"/>
+      <property id="config.board.ldr_addr_nml" value="0x6000004C"/>
+      <property id="config.board.ldr_size_nml" value="0x00006000"/>
+      <property id="config.board.dest_addr_nml" value="0x00102000"/>
+      <property id="config.board.cssctl_v" value="0x0000003F"/>
+      <property id="config.board.liocfgcs0_v" value="0x00070000"/>
+      <property id="config.board.access_speed" value="0x00000006"/>
+      <property id="config.board.check_sum" value="Auto Calculate."/>
+      <property id="config.board.use_loader_parameter" value="config.board.use_loader_parameter.used"/>
+    </config>
+    <config id="config.bsp.rzn2l.R9A07G084M04GBG">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.atcm_size_bytes" value="config.bsp.atcm_size_bytes.value"/>
+      <property id="config.bsp.btcm_size_bytes" value="config.bsp.btcm_size_bytes.value"/>
+      <property id="config.bsp.system_ram_size_bytes" value="config.bsp.system_ram_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.cpu" value="config.bsp.cpu.cpu0"/>
+    </config>
+    <config id="config.bsp.rzn2l.cr520_mpu">
+      <property id="config.bsp.fsp.mpu0_read_reg0" value="config.bsp.fsp.mpu0_read_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu0_write_reg0" value="config.bsp.fsp.mpu0_write_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu0_reg0_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu0_reg0_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu0_read_reg1" value="config.bsp.fsp.mpu0_read_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu0_write_reg1" value="config.bsp.fsp.mpu0_write_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu0_reg1_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu0_reg1_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu0_read_reg2" value="config.bsp.fsp.mpu0_read_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu0_write_reg2" value="config.bsp.fsp.mpu0_write_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu0_reg2_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu0_reg2_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu0_read_reg3" value="config.bsp.fsp.mpu0_read_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu0_write_reg3" value="config.bsp.fsp.mpu0_write_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu0_reg3_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu0_reg3_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu0_read_reg4" value="config.bsp.fsp.mpu0_read_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu0_write_reg4" value="config.bsp.fsp.mpu0_write_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu0_reg4_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu0_reg4_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu0_read_reg5" value="config.bsp.fsp.mpu0_read_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu0_write_reg5" value="config.bsp.fsp.mpu0_write_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu0_reg5_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu0_reg5_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu0_read_reg6" value="config.bsp.fsp.mpu0_read_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu0_write_reg6" value="config.bsp.fsp.mpu0_write_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu0_reg6_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu0_reg6_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu0_read_reg7" value="config.bsp.fsp.mpu0_read_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu0_write_reg7" value="config.bsp.fsp.mpu0_write_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu0_reg7_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu0_reg7_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu1_read_reg0" value="config.bsp.fsp.mpu1_read_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu1_write_reg0" value="config.bsp.fsp.mpu1_write_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu1_reg0_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu1_reg0_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu1_read_reg1" value="config.bsp.fsp.mpu1_read_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu1_write_reg1" value="config.bsp.fsp.mpu1_write_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu1_reg1_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu1_reg1_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu1_read_reg2" value="config.bsp.fsp.mpu1_read_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu1_write_reg2" value="config.bsp.fsp.mpu1_write_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu1_reg2_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu1_reg2_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu1_read_reg3" value="config.bsp.fsp.mpu1_read_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu1_write_reg3" value="config.bsp.fsp.mpu1_write_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu1_reg3_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu1_reg3_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu1_read_reg4" value="config.bsp.fsp.mpu1_read_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu1_write_reg4" value="config.bsp.fsp.mpu1_write_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu1_reg4_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu1_reg4_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu1_read_reg5" value="config.bsp.fsp.mpu1_read_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu1_write_reg5" value="config.bsp.fsp.mpu1_write_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu1_reg5_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu1_reg5_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu1_read_reg6" value="config.bsp.fsp.mpu1_read_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu1_write_reg6" value="config.bsp.fsp.mpu1_write_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu1_reg6_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu1_reg6_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu1_read_reg7" value="config.bsp.fsp.mpu1_read_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu1_write_reg7" value="config.bsp.fsp.mpu1_write_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu1_reg7_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu1_reg7_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu2_read_reg0" value="config.bsp.fsp.mpu2_read_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu2_write_reg0" value="config.bsp.fsp.mpu2_write_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu2_reg0_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu2_reg0_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu2_read_reg1" value="config.bsp.fsp.mpu2_read_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu2_write_reg1" value="config.bsp.fsp.mpu2_write_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu2_reg1_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu2_reg1_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu2_read_reg2" value="config.bsp.fsp.mpu2_read_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu2_write_reg2" value="config.bsp.fsp.mpu2_write_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu2_reg2_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu2_reg2_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu2_read_reg3" value="config.bsp.fsp.mpu2_read_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu2_write_reg3" value="config.bsp.fsp.mpu2_write_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu2_reg3_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu2_reg3_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu2_read_reg4" value="config.bsp.fsp.mpu2_read_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu2_write_reg4" value="config.bsp.fsp.mpu2_write_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu2_reg4_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu2_reg4_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu2_read_reg5" value="config.bsp.fsp.mpu2_read_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu2_write_reg5" value="config.bsp.fsp.mpu2_write_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu2_reg5_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu2_reg5_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu2_read_reg6" value="config.bsp.fsp.mpu2_read_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu2_write_reg6" value="config.bsp.fsp.mpu2_write_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu2_reg6_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu2_reg6_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu2_read_reg7" value="config.bsp.fsp.mpu2_read_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu2_write_reg7" value="config.bsp.fsp.mpu2_write_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu2_reg7_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu2_reg7_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu3_read_reg0" value="config.bsp.fsp.mpu3_read_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu3_write_reg0" value="config.bsp.fsp.mpu3_write_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu3_reg0_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_reg0_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_read_reg1" value="config.bsp.fsp.mpu3_read_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu3_write_reg1" value="config.bsp.fsp.mpu3_write_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu3_reg1_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_reg1_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_read_reg2" value="config.bsp.fsp.mpu3_read_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu3_write_reg2" value="config.bsp.fsp.mpu3_write_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu3_reg2_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_reg2_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_read_reg3" value="config.bsp.fsp.mpu3_read_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu3_write_reg3" value="config.bsp.fsp.mpu3_write_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu3_reg3_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_reg3_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_read_reg4" value="config.bsp.fsp.mpu3_read_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu3_write_reg4" value="config.bsp.fsp.mpu3_write_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu3_reg4_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_reg4_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_read_reg5" value="config.bsp.fsp.mpu3_read_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu3_write_reg5" value="config.bsp.fsp.mpu3_write_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu3_reg5_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_reg5_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_read_reg6" value="config.bsp.fsp.mpu3_read_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu3_write_reg6" value="config.bsp.fsp.mpu3_write_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu3_reg6_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_reg6_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_read_reg7" value="config.bsp.fsp.mpu3_read_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu3_write_reg7" value="config.bsp.fsp.mpu3_write_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu3_reg7_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu3_reg7_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_read_reg0" value="config.bsp.fsp.mpu4_read_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu4_write_reg0" value="config.bsp.fsp.mpu4_write_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu4_reg0_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_reg0_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_read_reg1" value="config.bsp.fsp.mpu4_read_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu4_write_reg1" value="config.bsp.fsp.mpu4_write_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu4_reg1_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_reg1_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_read_reg2" value="config.bsp.fsp.mpu4_read_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu4_write_reg2" value="config.bsp.fsp.mpu4_write_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu4_reg2_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_reg2_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_read_reg3" value="config.bsp.fsp.mpu4_read_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu4_write_reg3" value="config.bsp.fsp.mpu4_write_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu4_reg3_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_reg3_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_read_reg4" value="config.bsp.fsp.mpu4_read_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu4_write_reg4" value="config.bsp.fsp.mpu4_write_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu4_reg4_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_reg4_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_read_reg5" value="config.bsp.fsp.mpu4_read_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu4_write_reg5" value="config.bsp.fsp.mpu4_write_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu4_reg5_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_reg5_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_read_reg6" value="config.bsp.fsp.mpu4_read_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu4_write_reg6" value="config.bsp.fsp.mpu4_write_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu4_reg6_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_reg6_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_read_reg7" value="config.bsp.fsp.mpu4_read_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu4_write_reg7" value="config.bsp.fsp.mpu4_write_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu4_reg7_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu4_reg7_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_read_reg0" value="config.bsp.fsp.mpu6_read_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu6_write_reg0" value="config.bsp.fsp.mpu6_write_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu6_reg0_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_reg0_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu6_read_reg1" value="config.bsp.fsp.mpu6_read_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu6_write_reg1" value="config.bsp.fsp.mpu6_write_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu6_reg1_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_reg1_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu6_read_reg2" value="config.bsp.fsp.mpu6_read_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu6_write_reg2" value="config.bsp.fsp.mpu6_write_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu6_reg2_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_reg2_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu6_read_reg3" value="config.bsp.fsp.mpu6_read_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu6_write_reg3" value="config.bsp.fsp.mpu6_write_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu6_reg3_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_reg3_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu6_read_reg4" value="config.bsp.fsp.mpu6_read_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu6_write_reg4" value="config.bsp.fsp.mpu6_write_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu6_reg4_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_reg4_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu6_read_reg5" value="config.bsp.fsp.mpu6_read_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu6_write_reg5" value="config.bsp.fsp.mpu6_write_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu6_reg5_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_reg5_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu6_read_reg6" value="config.bsp.fsp.mpu6_read_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu6_write_reg6" value="config.bsp.fsp.mpu6_write_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu6_reg6_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_reg6_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu6_read_reg7" value="config.bsp.fsp.mpu6_read_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu6_write_reg7" value="config.bsp.fsp.mpu6_write_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu6_reg7_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu6_reg7_end" value="0x00000C00"/>
+      <property id="config.bsp.fsp.mpu7_read_reg0" value="config.bsp.fsp.mpu7_read_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu7_write_reg0" value="config.bsp.fsp.mpu7_write_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu7_reg0_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_reg0_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_read_reg1" value="config.bsp.fsp.mpu7_read_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu7_write_reg1" value="config.bsp.fsp.mpu7_write_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu7_reg1_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_reg1_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_read_reg2" value="config.bsp.fsp.mpu7_read_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu7_write_reg2" value="config.bsp.fsp.mpu7_write_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu7_reg2_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_reg2_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_read_reg3" value="config.bsp.fsp.mpu7_read_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu7_write_reg3" value="config.bsp.fsp.mpu7_write_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu7_reg3_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_reg3_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_read_reg4" value="config.bsp.fsp.mpu7_read_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu7_write_reg4" value="config.bsp.fsp.mpu7_write_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu7_reg4_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_reg4_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_read_reg5" value="config.bsp.fsp.mpu7_read_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu7_write_reg5" value="config.bsp.fsp.mpu7_write_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu7_reg5_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_reg5_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_read_reg6" value="config.bsp.fsp.mpu7_read_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu7_write_reg6" value="config.bsp.fsp.mpu7_write_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu7_reg6_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_reg6_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_read_reg7" value="config.bsp.fsp.mpu7_read_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu7_write_reg7" value="config.bsp.fsp.mpu7_write_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu7_reg7_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu7_reg7_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_read_reg0" value="config.bsp.fsp.mpu8_read_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu8_write_reg0" value="config.bsp.fsp.mpu8_write_reg0.disabled"/>
+      <property id="config.bsp.fsp.mpu8_reg0_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_reg0_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_read_reg1" value="config.bsp.fsp.mpu8_read_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu8_write_reg1" value="config.bsp.fsp.mpu8_write_reg1.disabled"/>
+      <property id="config.bsp.fsp.mpu8_reg1_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_reg1_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_read_reg2" value="config.bsp.fsp.mpu8_read_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu8_write_reg2" value="config.bsp.fsp.mpu8_write_reg2.disabled"/>
+      <property id="config.bsp.fsp.mpu8_reg2_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_reg2_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_read_reg3" value="config.bsp.fsp.mpu8_read_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu8_write_reg3" value="config.bsp.fsp.mpu8_write_reg3.disabled"/>
+      <property id="config.bsp.fsp.mpu8_reg3_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_reg3_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_read_reg4" value="config.bsp.fsp.mpu8_read_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu8_write_reg4" value="config.bsp.fsp.mpu8_write_reg4.disabled"/>
+      <property id="config.bsp.fsp.mpu8_reg4_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_reg4_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_read_reg5" value="config.bsp.fsp.mpu8_read_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu8_write_reg5" value="config.bsp.fsp.mpu8_write_reg5.disabled"/>
+      <property id="config.bsp.fsp.mpu8_reg5_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_reg5_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_read_reg6" value="config.bsp.fsp.mpu8_read_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu8_write_reg6" value="config.bsp.fsp.mpu8_write_reg6.disabled"/>
+      <property id="config.bsp.fsp.mpu8_reg6_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_reg6_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_read_reg7" value="config.bsp.fsp.mpu8_read_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu8_write_reg7" value="config.bsp.fsp.mpu8_write_reg7.disabled"/>
+      <property id="config.bsp.fsp.mpu8_reg7_start" value="0x00000000"/>
+      <property id="config.bsp.fsp.mpu8_reg7_end" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr0.type" value="config.bsp.fsp.cpu.mpu_attr0.type.normal_memory"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr0.memory.inner" value="config.bsp.fsp.cpu.mpu_attr0.memory.inner.write_back_non_transient"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr0.memory.inner.read" value="config.bsp.fsp.cpu.mpu_attr0.memory.inner.read.allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr0.memory.inner.write" value="config.bsp.fsp.cpu.mpu_attr0.memory.inner.write.allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr0.memory.outer" value="config.bsp.fsp.cpu.mpu_attr0.memory.outer.write_back_non_transient"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr0.memory.outer.read" value="config.bsp.fsp.cpu.mpu_attr0.memory.outer.read.allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr0.memory.outer.write" value="config.bsp.fsp.cpu.mpu_attr0.memory.outer.write.allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr0.device" value="config.bsp.fsp.cpu.mpu_attr0.device.nGnRnE"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr1.type" value="config.bsp.fsp.cpu.mpu_attr1.type.normal_memory"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr1.memory.inner" value="config.bsp.fsp.cpu.mpu_attr1.memory.inner.write_through_non_transient"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr1.memory.inner.read" value="config.bsp.fsp.cpu.mpu_attr1.memory.inner.read.allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr1.memory.inner.write" value="config.bsp.fsp.cpu.mpu_attr1.memory.inner.write.allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr1.memory.outer" value="config.bsp.fsp.cpu.mpu_attr1.memory.outer.write_through_non_transient"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr1.memory.outer.read" value="config.bsp.fsp.cpu.mpu_attr1.memory.outer.read.allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr1.memory.outer.write" value="config.bsp.fsp.cpu.mpu_attr1.memory.outer.write.allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr1.device" value="config.bsp.fsp.cpu.mpu_attr1.device.nGnRnE"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr2.type" value="config.bsp.fsp.cpu.mpu_attr2.type.normal_memory"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr2.memory.inner" value="config.bsp.fsp.cpu.mpu_attr2.memory.inner.write_through_non_transient"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr2.memory.inner.read" value="config.bsp.fsp.cpu.mpu_attr2.memory.inner.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr2.memory.inner.write" value="config.bsp.fsp.cpu.mpu_attr2.memory.inner.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr2.memory.outer" value="config.bsp.fsp.cpu.mpu_attr2.memory.outer.write_through_non_transient"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr2.memory.outer.read" value="config.bsp.fsp.cpu.mpu_attr2.memory.outer.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr2.memory.outer.write" value="config.bsp.fsp.cpu.mpu_attr2.memory.outer.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr2.device" value="config.bsp.fsp.cpu.mpu_attr2.device.nGnRnE"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr3.type" value="config.bsp.fsp.cpu.mpu_attr3.type.normal_memory"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr3.memory.inner" value="config.bsp.fsp.cpu.mpu_attr3.memory.inner.non_chacheable"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr3.memory.inner.read" value="config.bsp.fsp.cpu.mpu_attr3.memory.inner.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr3.memory.inner.write" value="config.bsp.fsp.cpu.mpu_attr3.memory.inner.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr3.memory.outer" value="config.bsp.fsp.cpu.mpu_attr3.memory.outer.non_chacheable"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr3.memory.outer.read" value="config.bsp.fsp.cpu.mpu_attr3.memory.outer.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr3.memory.outer.write" value="config.bsp.fsp.cpu.mpu_attr3.memory.outer.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr3.device" value="config.bsp.fsp.cpu.mpu_attr3.device.nGnRnE"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr4.type" value="config.bsp.fsp.cpu.mpu_attr4.type.device"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr4.memory.inner" value="config.bsp.fsp.cpu.mpu_attr4.memory.inner.write_through"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr4.memory.inner.read" value="config.bsp.fsp.cpu.mpu_attr4.memory.inner.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr4.memory.inner.write" value="config.bsp.fsp.cpu.mpu_attr4.memory.inner.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr4.memory.outer" value="config.bsp.fsp.cpu.mpu_attr4.memory.outer.write_through"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr4.memory.outer.read" value="config.bsp.fsp.cpu.mpu_attr4.memory.outer.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr4.memory.outer.write" value="config.bsp.fsp.cpu.mpu_attr4.memory.outer.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr4.device" value="config.bsp.fsp.cpu.mpu_attr4.device.nGnRnE"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr5.type" value="config.bsp.fsp.cpu.mpu_attr5.type.device"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr5.memory.inner" value="config.bsp.fsp.cpu.mpu_attr5.memory.inner.write_through"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr5.memory.inner.read" value="config.bsp.fsp.cpu.mpu_attr5.memory.inner.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr5.memory.inner.write" value="config.bsp.fsp.cpu.mpu_attr5.memory.inner.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr5.memory.outer" value="config.bsp.fsp.cpu.mpu_attr5.memory.outer.write_through"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr5.memory.outer.read" value="config.bsp.fsp.cpu.mpu_attr5.memory.outer.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr5.memory.outer.write" value="config.bsp.fsp.cpu.mpu_attr5.memory.outer.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr5.device" value="config.bsp.fsp.cpu.mpu_attr5.device.nGnRE"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr6.type" value="config.bsp.fsp.cpu.mpu_attr6.type.device"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr6.memory.inner" value="config.bsp.fsp.cpu.mpu_attr6.memory.inner.write_through"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr6.memory.inner.read" value="config.bsp.fsp.cpu.mpu_attr6.memory.inner.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr6.memory.inner.write" value="config.bsp.fsp.cpu.mpu_attr6.memory.inner.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr6.memory.outer" value="config.bsp.fsp.cpu.mpu_attr6.memory.outer.write_through"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr6.memory.outer.read" value="config.bsp.fsp.cpu.mpu_attr6.memory.outer.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr6.memory.outer.write" value="config.bsp.fsp.cpu.mpu_attr6.memory.outer.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr6.device" value="config.bsp.fsp.cpu.mpu_attr6.device.nGRE"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr7.type" value="config.bsp.fsp.cpu.mpu_attr7.type.device"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr7.memory.inner" value="config.bsp.fsp.cpu.mpu_attr7.memory.inner.write_through"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr7.memory.inner.read" value="config.bsp.fsp.cpu.mpu_attr7.memory.inner.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr7.memory.inner.write" value="config.bsp.fsp.cpu.mpu_attr7.memory.inner.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr7.memory.outer" value="config.bsp.fsp.cpu.mpu_attr7.memory.outer.write_through"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr7.memory.outer.read" value="config.bsp.fsp.cpu.mpu_attr7.memory.outer.read.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr7.memory.outer.write" value="config.bsp.fsp.cpu.mpu_attr7.memory.outer.write.not_allocate"/>
+      <property id="config.bsp.fsp.cpu.mpu_attr7.device" value="config.bsp.fsp.cpu.mpu_attr7.device.GRE"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg00.name" value="ATCM"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg00.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg00.limit" value="0x0001FFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg00.sh" value="config.bsp.fsp.cpu.mpu_reg00.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg00.ap" value="config.bsp.fsp.cpu.mpu_reg00.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg00.xn" value="config.bsp.fsp.cpu.mpu_reg00.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg00.attr_index" value="config.bsp.fsp.cpu.mpu_reg00.attr_index.atrr3"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg00.region_enable" value="config.bsp.fsp.cpu.mpu_reg00.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg01.name" value="BTCM"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg01.base" value="0x00100000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg01.limit" value="0x0011FFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg01.sh" value="config.bsp.fsp.cpu.mpu_reg01.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg01.ap" value="config.bsp.fsp.cpu.mpu_reg01.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg01.xn" value="config.bsp.fsp.cpu.mpu_reg01.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg01.attr_index" value="config.bsp.fsp.cpu.mpu_reg01.attr_index.atrr3"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg01.region_enable" value="config.bsp.fsp.cpu.mpu_reg01.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg02.name" value="System RAM"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg02.base" value="0x10000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg02.limit" value="0x1017FFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg02.sh" value="config.bsp.fsp.cpu.mpu_reg02.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg02.ap" value="config.bsp.fsp.cpu.mpu_reg02.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg02.xn" value="config.bsp.fsp.cpu.mpu_reg02.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg02.attr_index" value="config.bsp.fsp.cpu.mpu_reg02.attr_index.atrr1"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg02.region_enable" value="config.bsp.fsp.cpu.mpu_reg02.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg03.name" value="Mirror area of System RAM"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg03.base" value="0x30000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg03.limit" value="0x3017FFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg03.sh" value="config.bsp.fsp.cpu.mpu_reg03.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg03.ap" value="config.bsp.fsp.cpu.mpu_reg03.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg03.xn" value="config.bsp.fsp.cpu.mpu_reg03.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg03.attr_index" value="config.bsp.fsp.cpu.mpu_reg03.attr_index.atrr3"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg03.region_enable" value="config.bsp.fsp.cpu.mpu_reg03.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg04.name" value="Mirror area of external address space"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg04.base" value="0x40000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg04.limit" value="0x5FFFFFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg04.sh" value="config.bsp.fsp.cpu.mpu_reg04.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg04.ap" value="config.bsp.fsp.cpu.mpu_reg04.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg04.xn" value="config.bsp.fsp.cpu.mpu_reg04.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg04.attr_index" value="config.bsp.fsp.cpu.mpu_reg04.attr_index.atrr3"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg04.region_enable" value="config.bsp.fsp.cpu.mpu_reg04.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg05.name" value="External address space"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg05.base" value="0x60000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg05.limit" value="0x7FFFFFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg05.sh" value="config.bsp.fsp.cpu.mpu_reg05.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg05.ap" value="config.bsp.fsp.cpu.mpu_reg05.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg05.xn" value="config.bsp.fsp.cpu.mpu_reg05.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg05.attr_index" value="config.bsp.fsp.cpu.mpu_reg05.attr_index.atrr1"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg05.region_enable" value="config.bsp.fsp.cpu.mpu_reg05.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg06.name" value="Non-Safety Peripheral"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg06.base" value="0x80000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg06.limit" value="0x80FFFFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg06.sh" value="config.bsp.fsp.cpu.mpu_reg06.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg06.ap" value="config.bsp.fsp.cpu.mpu_reg06.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg06.xn" value="config.bsp.fsp.cpu.mpu_reg06.xn.execute_never"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg06.attr_index" value="config.bsp.fsp.cpu.mpu_reg06.attr_index.atrr5"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg06.region_enable" value="config.bsp.fsp.cpu.mpu_reg06.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg07.name" value="Safety Peripheral"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg07.base" value="0x81000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg07.limit" value="0x81FFFFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg07.sh" value="config.bsp.fsp.cpu.mpu_reg07.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg07.ap" value="config.bsp.fsp.cpu.mpu_reg07.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg07.xn" value="config.bsp.fsp.cpu.mpu_reg07.xn.execute_never"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg07.attr_index" value="config.bsp.fsp.cpu.mpu_reg07.attr_index.atrr5"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg07.region_enable" value="config.bsp.fsp.cpu.mpu_reg07.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg08.name" value="LLPP Peripheral"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg08.base" value="0x90000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg08.limit" value="0x901FFFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg08.sh" value="config.bsp.fsp.cpu.mpu_reg08.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg08.ap" value="config.bsp.fsp.cpu.mpu_reg08.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg08.xn" value="config.bsp.fsp.cpu.mpu_reg08.xn.execute_never"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg08.attr_index" value="config.bsp.fsp.cpu.mpu_reg08.attr_index.atrr5"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg08.region_enable" value="config.bsp.fsp.cpu.mpu_reg08.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg09.name" value="GIC0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg09.base" value="0x94000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg09.limit" value="0x941FFFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg09.sh" value="config.bsp.fsp.cpu.mpu_reg09.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg09.ap" value="config.bsp.fsp.cpu.mpu_reg09.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg09.xn" value="config.bsp.fsp.cpu.mpu_reg09.xn.execute_never"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg09.attr_index" value="config.bsp.fsp.cpu.mpu_reg09.attr_index.atrr4"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg09.region_enable" value="config.bsp.fsp.cpu.mpu_reg09.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg10.name" value="Debug Private"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg10.base" value="0xC0000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg10.limit" value="0xC0FFFFFF"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg10.sh" value="config.bsp.fsp.cpu.mpu_reg10.sh.outer_shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg10.ap" value="config.bsp.fsp.cpu.mpu_reg10.ap.rw_rw"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg10.xn" value="config.bsp.fsp.cpu.mpu_reg10.xn.execute_never"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg10.attr_index" value="config.bsp.fsp.cpu.mpu_reg10.attr_index.atrr4"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg10.region_enable" value="config.bsp.fsp.cpu.mpu_reg10.region_enable.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg11.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg11.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg11.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg11.sh" value="config.bsp.fsp.cpu.mpu_reg11.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg11.ap" value="config.bsp.fsp.cpu.mpu_reg11.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg11.xn" value="config.bsp.fsp.cpu.mpu_reg11.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg11.attr_index" value="config.bsp.fsp.cpu.mpu_reg11.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg11.region_enable" value="config.bsp.fsp.cpu.mpu_reg11.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg12.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg12.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg12.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg12.sh" value="config.bsp.fsp.cpu.mpu_reg12.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg12.ap" value="config.bsp.fsp.cpu.mpu_reg12.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg12.xn" value="config.bsp.fsp.cpu.mpu_reg12.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg12.attr_index" value="config.bsp.fsp.cpu.mpu_reg12.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg12.region_enable" value="config.bsp.fsp.cpu.mpu_reg12.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg13.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg13.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg13.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg13.sh" value="config.bsp.fsp.cpu.mpu_reg13.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg13.ap" value="config.bsp.fsp.cpu.mpu_reg13.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg13.xn" value="config.bsp.fsp.cpu.mpu_reg13.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg13.attr_index" value="config.bsp.fsp.cpu.mpu_reg13.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg13.region_enable" value="config.bsp.fsp.cpu.mpu_reg13.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg14.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg14.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg14.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg14.sh" value="config.bsp.fsp.cpu.mpu_reg14.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg14.ap" value="config.bsp.fsp.cpu.mpu_reg14.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg14.xn" value="config.bsp.fsp.cpu.mpu_reg14.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg14.attr_index" value="config.bsp.fsp.cpu.mpu_reg14.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg14.region_enable" value="config.bsp.fsp.cpu.mpu_reg14.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg15.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg15.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg15.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg15.sh" value="config.bsp.fsp.cpu.mpu_reg15.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg15.ap" value="config.bsp.fsp.cpu.mpu_reg15.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg15.xn" value="config.bsp.fsp.cpu.mpu_reg15.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg15.attr_index" value="config.bsp.fsp.cpu.mpu_reg15.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg15.region_enable" value="config.bsp.fsp.cpu.mpu_reg15.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg16.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg16.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg16.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg16.sh" value="config.bsp.fsp.cpu.mpu_reg16.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg16.ap" value="config.bsp.fsp.cpu.mpu_reg16.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg16.xn" value="config.bsp.fsp.cpu.mpu_reg16.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg16.attr_index" value="config.bsp.fsp.cpu.mpu_reg16.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg16.region_enable" value="config.bsp.fsp.cpu.mpu_reg16.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg17.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg17.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg17.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg17.sh" value="config.bsp.fsp.cpu.mpu_reg17.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg17.ap" value="config.bsp.fsp.cpu.mpu_reg17.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg17.xn" value="config.bsp.fsp.cpu.mpu_reg17.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg17.attr_index" value="config.bsp.fsp.cpu.mpu_reg17.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg17.region_enable" value="config.bsp.fsp.cpu.mpu_reg17.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg18.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg18.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg18.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg18.sh" value="config.bsp.fsp.cpu.mpu_reg18.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg18.ap" value="config.bsp.fsp.cpu.mpu_reg18.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg18.xn" value="config.bsp.fsp.cpu.mpu_reg18.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg18.attr_index" value="config.bsp.fsp.cpu.mpu_reg18.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg18.region_enable" value="config.bsp.fsp.cpu.mpu_reg18.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg19.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg19.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg19.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg19.sh" value="config.bsp.fsp.cpu.mpu_reg19.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg19.ap" value="config.bsp.fsp.cpu.mpu_reg19.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg19.xn" value="config.bsp.fsp.cpu.mpu_reg19.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg19.attr_index" value="config.bsp.fsp.cpu.mpu_reg19.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg19.region_enable" value="config.bsp.fsp.cpu.mpu_reg19.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg20.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg20.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg20.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg20.sh" value="config.bsp.fsp.cpu.mpu_reg20.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg20.ap" value="config.bsp.fsp.cpu.mpu_reg20.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg20.xn" value="config.bsp.fsp.cpu.mpu_reg20.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg20.attr_index" value="config.bsp.fsp.cpu.mpu_reg20.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg20.region_enable" value="config.bsp.fsp.cpu.mpu_reg20.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg21.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg21.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg21.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg21.sh" value="config.bsp.fsp.cpu.mpu_reg21.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg21.ap" value="config.bsp.fsp.cpu.mpu_reg21.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg21.xn" value="config.bsp.fsp.cpu.mpu_reg21.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg21.attr_index" value="config.bsp.fsp.cpu.mpu_reg21.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg21.region_enable" value="config.bsp.fsp.cpu.mpu_reg21.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg22.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg22.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg22.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg22.sh" value="config.bsp.fsp.cpu.mpu_reg22.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg22.ap" value="config.bsp.fsp.cpu.mpu_reg22.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg22.xn" value="config.bsp.fsp.cpu.mpu_reg22.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg22.attr_index" value="config.bsp.fsp.cpu.mpu_reg22.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg22.region_enable" value="config.bsp.fsp.cpu.mpu_reg22.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg23.name" value="Not Used"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg23.base" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg23.limit" value="0x00000000"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg23.sh" value="config.bsp.fsp.cpu.mpu_reg23.sh.non-shareable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg23.ap" value="config.bsp.fsp.cpu.mpu_reg23.ap.rw_none"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg23.xn" value="config.bsp.fsp.cpu.mpu_reg23.xn.execute_enable"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg23.attr_index" value="config.bsp.fsp.cpu.mpu_reg23.attr_index.atrr0"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg23.region_enable" value="config.bsp.fsp.cpu.mpu_reg23.region_enable.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg.br" value="config.bsp.fsp.cpu.mpu_reg.br.disabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg.i" value="config.bsp.fsp.cpu.mpu_reg.i.enabled"/>
+      <property id="config.bsp.fsp.cpu.mpu_reg.c" value="config.bsp.fsp.cpu.mpu_reg.c.enabled"/>
+    </config>
+    <config id="config.bsp.rzn2l">
+      <property id="config.bsp.common.fiq" value="0x400"/>
+      <property id="config.bsp.common.irq" value="0x400"/>
+      <property id="config.bsp.common.abt" value="0x400"/>
+      <property id="config.bsp.common.und" value="0x400"/>
+      <property id="config.bsp.common.sys" value="0x400"/>
+      <property id="config.bsp.common.svc" value="0x400"/>
+      <property id="config.bsp.common.heap" value="0x2000"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.tfu_mathlib" value="config.bsp.common.tfu_mathlib.enabled"/>
+    </config>
+    <config id="config.bsp.rzn2l.fsp">
+      <property id="config.bsp.fsp.mcu.sci_uart.ctspen_channels" value="0x03F"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16000000"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="37500000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="1"/>
+      <property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="4864"/>
+    </config>
+    <config id="config.bsp.rz">
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.port_protect" value="config.bsp.common.port_protect.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.multiplex_interrupt" value="config.bsp.common.multiplex_interrupt.disabled"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.main.freq" option="board.clock.main.freq.25m"/>
+    <node id="board.clock.loco.enable" option="board.clock.loco.enable.enabled"/>
+    <node id="board.clock.pll0.display" option="board.clock.pll0.display.value"/>
+    <node id="board.clock.pll1" option="board.clock.pll1.initial"/>
+    <node id="board.clock.pll1.display" option="board.clock.pll1.display.value"/>
+    <node id="board.clock.ethernet.source" option="board.clock.ethernet.source.main"/>
+    <node id="board.clock.reference.display" option="board.clock.reference.display.value"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.240k"/>
+    <node id="board.clock.clma0.enable" option="board.clock.clma0.enable.enabled"/>
+    <node id="board.clock.clma0.error" option="board.clock.clma0.error.not_mask"/>
+    <node id="board.clock.clma3.error" option="board.clock.clma3.error.not_mask"/>
+    <node id="board.clock.clma1.error" option="board.clock.clma1.error.mask"/>
+    <node id="board.clock.clma3.enable" option="board.clock.clma3.enable.enabled"/>
+    <node id="board.clock.clma1.enable" option="board.clock.clma1.enable.enabled"/>
+    <node id="board.clock.clma2.enable" option="board.clock.clma2.enable.enabled"/>
+    <node id="board.clock.clma0.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma1.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma2.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma3.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.alternative.source" option="board.clock.alternative.source.loco"/>
+    <node id="board.clock.clma0.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma1.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma2.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma3.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.iclk.freq" option="board.clock.iclk.freq.200m"/>
+    <node id="board.clock.cpu0clk.mul" option="board.clock.cpu0clk.mul.2"/>
+    <node id="board.clock.cpu0clk.display" option="board.clock.cpu0clk.display.value"/>
+    <node id="board.clock.ckio.div" option="board.clock.ckio.div.4"/>
+    <node id="board.clock.ckio.display" option="board.clock.ckio.display.value"/>
+    <node id="board.clock.sci0asyncclk.sel" option="board.clock.sci0asyncclk.sel.1"/>
+    <node id="board.clock.sci1asyncclk.sel" option="board.clock.sci1asyncclk.sel.1"/>
+    <node id="board.clock.sci2asyncclk.sel" option="board.clock.sci2asyncclk.sel.1"/>
+    <node id="board.clock.sci3asyncclk.sel" option="board.clock.sci3asyncclk.sel.1"/>
+    <node id="board.clock.sci4asyncclk.sel" option="board.clock.sci4asyncclk.sel.1"/>
+    <node id="board.clock.sci5asyncclk.sel" option="board.clock.sci5asyncclk.sel.1"/>
+    <node id="board.clock.spi0asyncclk.sel" option="board.clock.spi0asyncclk.sel.1"/>
+    <node id="board.clock.spi1asyncclk.sel" option="board.clock.spi1asyncclk.sel.1"/>
+    <node id="board.clock.spi2asyncclk.sel" option="board.clock.spi2asyncclk.sel.1"/>
+    <node id="board.clock.spi3asyncclk.sel" option="board.clock.spi3asyncclk.sel.1"/>
+    <node id="board.clock.pclkshost.display" option="board.clock.pclkshost.display.value"/>
+    <node id="board.clock.pclkgptl.display" option="board.clock.pclkgptl.display.value"/>
+    <node id="board.clock.pclkh.display" option="board.clock.pclkh.display.value"/>
+    <node id="board.clock.pclkm.display" option="board.clock.pclkm.display.value"/>
+    <node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
+    <node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
+    <node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
+    <node id="board.clock.pclkcan.freq.display" option="board.clock.pclkcan.freq.display.value"/>
+    <node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.133m"/>
+    <node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
+    <node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="2.2.0">
+      <description>Simple application that blinks an LED. No RTOS included.</description>
+      <originalPack>Renesas.RZN_baremetal_blinky.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="2.2.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="all" subgroup="Memory" variant="" vendor="Renesas" version="2.2.0">
+      <description>Memory Config Checking</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="2.2.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="Core" variant="" vendor="Arm" version="5.7.0+renesas.3.fsp.2.2.0">
+      <description>Arm CMSIS Version 5 - Core</description>
+      <originalPack>Arm.CMSIS5.5.7.0+renesas.3.fsp.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="rzn2l_rsk" variant="xspi0_x1_boot" vendor="Renesas" version="2.2.0">
+      <description>RSK+RZN2L Board Support Files (xSPI0 x1 boot mode)</description>
+      <originalPack>Renesas.RZN_board_rzn2l_rsk.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="rzn2l" subgroup="device" variant="R9A07G084M04GBG" vendor="Renesas" version="2.2.0">
+      <description>Board support package for R9A07G084M04GBG</description>
+      <originalPack>Renesas.RZN_mcu_rzn2l.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="rzn2l" subgroup="device" variant="" vendor="Renesas" version="2.2.0">
+      <description>Board support package for RZN2L</description>
+      <originalPack>Renesas.RZN_mcu_rzn2l.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="rzn2l" subgroup="fsp" variant="" vendor="Renesas" version="2.2.0">
+      <description>Board support package for RZN2L - FSP Data</description>
+      <originalPack>Renesas.RZN_mcu_rzn2l.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="2.2.0">
+      <description>SCI UART</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ether_phy" variant="" vendor="Renesas" version="2.2.0">
+      <description>Ethernet PHY</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ether_selector" variant="" vendor="Renesas" version="2.2.0">
+      <description>Ethernet Selector</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ethsw" variant="" vendor="Renesas" version="2.2.0">
+      <description>Ethernet Switch</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_gmac" variant="" vendor="Renesas" version="2.2.0">
+      <description>Ethernet</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_gpt" variant="" vendor="Renesas" version="2.2.0">
+      <description>General PWM Timer</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_mtu3" variant="" vendor="Renesas" version="2.2.0">
+      <description>Multi-Function Timer Pulse Unit 3</description>
+      <originalPack>Renesas.RZN.2.2.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_output_group1" value="_disabled"/>
+      <property id="module.driver.ioport.port_select_output_group1" value=""/>
+      <property id="module.driver.ioport.operation_output_group1" value="Low output"/>
+      <property id="module.driver.ioport.elc_trigger_output_group2" value="_disabled"/>
+      <property id="module.driver.ioport.port_select_output_group2" value=""/>
+      <property id="module.driver.ioport.operation_output_group2" value="Low output"/>
+      <property id="module.driver.ioport.elc_trigger_input_group1" value="_disabled"/>
+      <property id="module.driver.ioport.event_control_input_group1" value="Disabled"/>
+      <property id="module.driver.ioport.port_select_input_group1" value=""/>
+      <property id="module.driver.ioport.edge_detect_input_group1" value="Rising edge"/>
+      <property id="module.driver.ioport.buffer_overwrite_input_group1" value="Disabled"/>
+      <property id="module.driver.ioport.p16_0_initial_value_input_group1" value="module.driver.ioport.p16_0_initial_value_input_group1.low"/>
+      <property id="module.driver.ioport.p16_1_initial_value_input_group1" value="module.driver.ioport.p16_1_initial_value_input_group1.low"/>
+      <property id="module.driver.ioport.p16_2_initial_value_input_group1" value="module.driver.ioport.p16_2_initial_value_input_group1.low"/>
+      <property id="module.driver.ioport.p16_3_initial_value_input_group1" value="module.driver.ioport.p16_3_initial_value_input_group1.low"/>
+      <property id="module.driver.ioport.p16_4_initial_value_input_group1" value="module.driver.ioport.p16_4_initial_value_input_group1.low"/>
+      <property id="module.driver.ioport.p16_5_initial_value_input_group1" value="module.driver.ioport.p16_5_initial_value_input_group1.low"/>
+      <property id="module.driver.ioport.p16_6_initial_value_input_group1" value="module.driver.ioport.p16_6_initial_value_input_group1.low"/>
+      <property id="module.driver.ioport.p16_7_initial_value_input_group1" value="module.driver.ioport.p16_7_initial_value_input_group1.low"/>
+      <property id="module.driver.ioport.elc_trigger_input_group2" value="_disabled"/>
+      <property id="module.driver.ioport.event_control_input_group2" value="Disabled"/>
+      <property id="module.driver.ioport.port_select_input_group2" value=""/>
+      <property id="module.driver.ioport.edge_detect_input_group2" value="Rising edge"/>
+      <property id="module.driver.ioport.buffer_overwrite_input_group2" value="Disabled"/>
+      <property id="module.driver.ioport.p18_0_initial_value_input_group2" value="module.driver.ioport.p18_0_initial_value_input_group2.low"/>
+      <property id="module.driver.ioport.p18_1_initial_value_input_group2" value="module.driver.ioport.p18_1_initial_value_input_group2.low"/>
+      <property id="module.driver.ioport.p18_2_initial_value_input_group2" value="module.driver.ioport.p18_2_initial_value_input_group2.low"/>
+      <property id="module.driver.ioport.p18_3_initial_value_input_group2" value="module.driver.ioport.p18_3_initial_value_input_group2.low"/>
+      <property id="module.driver.ioport.p18_4_initial_value_input_group2" value="module.driver.ioport.p18_4_initial_value_input_group2.low"/>
+      <property id="module.driver.ioport.p18_5_initial_value_input_group2" value="module.driver.ioport.p18_5_initial_value_input_group2.low"/>
+      <property id="module.driver.ioport.p18_6_initial_value_input_group2" value="module.driver.ioport.p18_6_initial_value_input_group2.low"/>
+      <property id="module.driver.ioport.p18_7_initial_value_input_group2" value="module.driver.ioport.p18_7_initial_value_input_group2.low"/>
+      <property id="module.driver.ioport.event_control_single_port0" value="Disabled"/>
+      <property id="module.driver.ioport.event_direction_single_port0" value="Output direction"/>
+      <property id="module.driver.ioport.port_number_single_port0" value="module.driver.ioport.port_number_single_port0.p16_0"/>
+      <property id="module.driver.ioport.elc_trigger_single_output_port0" value="_disabled"/>
+      <property id="module.driver.ioport.operation_single_output_port0" value="Low output"/>
+      <property id="module.driver.ioport.edge_detect_single_output_port0" value="Rising edge"/>
+      <property id="module.driver.ioport.event_control_single_port1" value="Disabled"/>
+      <property id="module.driver.ioport.event_direction_single_port1" value="Output direction"/>
+      <property id="module.driver.ioport.port_number_single_port1" value="module.driver.ioport.port_number_single_port1.p16_0"/>
+      <property id="module.driver.ioport.elc_trigger_single_output_port1" value="_disabled"/>
+      <property id="module.driver.ioport.operation_single_output_port1" value="Low output"/>
+      <property id="module.driver.ioport.edge_detect_single_output_port1" value="Rising edge"/>
+      <property id="module.driver.ioport.event_control_single_port2" value="Disabled"/>
+      <property id="module.driver.ioport.event_direction_single_port2" value="Output direction"/>
+      <property id="module.driver.ioport.port_number_single_port2" value="module.driver.ioport.port_number_single_port2.p16_0"/>
+      <property id="module.driver.ioport.elc_trigger_single_output_port2" value="_disabled"/>
+      <property id="module.driver.ioport.operation_single_output_port2" value="Low output"/>
+      <property id="module.driver.ioport.edge_detect_single_output_port2" value="Rising edge"/>
+      <property id="module.driver.ioport.event_control_single_port3" value="Disabled"/>
+      <property id="module.driver.ioport.event_direction_single_port3" value="Output direction"/>
+      <property id="module.driver.ioport.port_number_single_port3" value="module.driver.ioport.port_number_single_port3.p16_0"/>
+      <property id="module.driver.ioport.elc_trigger_single_output_port3" value="_disabled"/>
+      <property id="module.driver.ioport.operation_single_output_port3" value="Low output"/>
+      <property id="module.driver.ioport.edge_detect_single_output_port3" value="Rising edge"/>
+    </module>
+    <module id="module.bsp.memory_config.0"/>
+    <module id="module.driver.uart_on_sci_uart.1968866849">
+      <property id="module.driver.uart.name" value="g_uart0"/>
+      <property id="module.driver.uart.channel" value="0"/>
+      <property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
+      <property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
+      <property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
+      <property id="module.driver.uart.baud" value="115200"/>
+      <property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
+      <property id="module.driver.uart.baudrate_max_err" value="5"/>
+      <property id="module.driver.uart.clock_source" value="module.driver.uart.clock_source.scinasyncclk"/>
+      <property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
+      <property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
+      <property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
+      <property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
+      <property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
+      <property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
+      <property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
+      <property id="module.driver.uart.rs485.de_enable" value="module.driver.uart.rs485.de_enable.disabled"/>
+      <property id="module.driver.uart.rs485.de_polarity" value="module.driver.uart.rs485.de_polarity.high"/>
+      <property id="module.driver.uart.rs485.de_assertion_time" value="1"/>
+      <property id="module.driver.uart.rs485.de_negation_time" value="1"/>
+      <property id="module.driver.uart.callback" value="user_uart0_callback"/>
+      <property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
+    </module>
+    <module id="module.driver.ether_on_ether.1094288014">
+      <property id="module.driver.ether.name" value="g_ether0"/>
+      <property id="module.driver.ether.channel" value="module.driver.ether.channel.0"/>
+      <property id="module.driver.ether.mac_address" value="00:11:22:33:44:55"/>
+      <property id="module.driver.ether.mac_address_1" value="NULL"/>
+      <property id="module.driver.ether.mac_address_2" value="NULL"/>
+      <property id="module.driver.ether.zerocopy" value="module.driver.ether.zerocopy.1"/>
+      <property id="module.driver.ether.flow_control" value="module.driver.ether.flow_control.disable"/>
+      <property id="module.driver.ether.promiscuous" value="module.driver.ether.promiscuous.1"/>
+      <property id="module.driver.ether.num_tx_descriptors" value="8"/>
+      <property id="module.driver.ether.num_rx_descriptors" value="8"/>
+      <property id="module.driver.ether.ether_buffer_size" value="1524"/>
+      <property id="module.driver.ether.sbd_interrupt_priority" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.ether.pmt_interrupt_priority" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.ether.p_callback" value="user_ether0_callback"/>
+      <property id="module.driver.ether.phylink" value="module.driver.ether.phylink.disable"/>
+    </module>
+    <module id="module.driver.ether_phy_on_ether_phy.277662383">
+      <property id="module.driver.ether_phy.name" value="g_ether_phy0"/>
+      <property id="module.driver.ether_phy.channel" value="module.driver.ether_phy.channel.0"/>
+      <property id="module.driver.ether_phy.phy_lsi_address" value="1"/>
+      <property id="module.driver.ether_phy.phy_reset_wait_time" value="0x00020000"/>
+      <property id="module.driver.ether_phy.flow_control" value="module.driver.ether_phy.flow_control.disable"/>
+      <property id="module.driver.ether_phy.port_type" value="module.driver.ether_phy.port_type.0"/>
+      <property id="module.driver.ether_phy.phy_lsi_type" value="module.driver.ether_phy.phy_lsi_type.custom"/>
+      <property id="module.driver.ether_phy.target_init" value="ether_phy_targets_initialize_rtl8211_rgmii"/>
+      <property id="module.driver.ether_phy.mdio_type" value="module.driver.ether_phy.mdio_type.0"/>
+      <property id="module.driver.ether_phy.auto_negotiation" value="module.driver.ether_phy.auto_negotiation.1"/>
+      <property id="module.driver.ether_phy.bps" value="module.driver.ether_phy.bps.3"/>
+      <property id="module.driver.ether_phy.duplex" value="module.driver.ether_phy.duplex.1"/>
+      <property id="module.driver.ether_phy.reset_port" value="module.driver.ether_phy.reset_port.PORT_13"/>
+      <property id="module.driver.ether_phy.reset_pin" value="module.driver.ether_phy.reset_pin.PIN_04"/>
+      <property id="module.driver.ether_phy.reset_time" value="15000"/>
+    </module>
+    <module id="module.driver.ether_selector_on_ether_selector.305883093">
+      <property id="module.driver.ether_selector.name" value="g_ether_selector0"/>
+      <property id="module.driver.ether_selector.channel" value="module.driver.ether_selector.channel.0"/>
+      <property id="module.driver.ether_selector.phylink" value="module.driver.ether_selector.phylink.low"/>
+      <property id="module.driver.ether_selector.interface_type" value="module.driver.ether_selector.interface_type.rgmii"/>
+      <property id="module.driver.ether_selector.speed" value="module.driver.ether_selector.speed.bps1000m"/>
+      <property id="module.driver.ether_selector.duplex" value="module.driver.ether_selector.duplex.full"/>
+      <property id="module.driver.ether_selector.ref_clock" value="module.driver.ether_selector.ref_clock.input"/>
+    </module>
+    <module id="module.driver.ether_switch_on_ether_switch.95659619">
+      <property id="module.driver.ethsw.name" value="g_ethsw0"/>
+      <property id="module.driver.ethsw.channel" value="module.driver.ethsw.channel.0"/>
+      <property id="module.driver.ethsw.specific_tag" value="module.driver.ethsw.specific_tag.0"/>
+      <property id="module.driver.ethsw.specific_tag_id" value="0xE001"/>
+      <property id="module.driver.ethsw.phylink" value="module.driver.ethsw.phylink.disable"/>
+      <property id="module.driver.ethsw.priority" value="board.icu.common.irq.priority12"/>
+      <property id="module.driver.ethsw.p_callback" value="NULL"/>
+      <property id="module.driver.ethsw.p_context" value="NULL"/>
+    </module>
+    <module id="module.driver.ether_phy_on_ether_phy.518802053">
+      <property id="module.driver.ether_phy.name" value="g_ether_phy1"/>
+      <property id="module.driver.ether_phy.channel" value="module.driver.ether_phy.channel.0"/>
+      <property id="module.driver.ether_phy.phy_lsi_address" value="2"/>
+      <property id="module.driver.ether_phy.phy_reset_wait_time" value="0x00020000"/>
+      <property id="module.driver.ether_phy.flow_control" value="module.driver.ether_phy.flow_control.disable"/>
+      <property id="module.driver.ether_phy.port_type" value="module.driver.ether_phy.port_type.0"/>
+      <property id="module.driver.ether_phy.phy_lsi_type" value="module.driver.ether_phy.phy_lsi_type.custom"/>
+      <property id="module.driver.ether_phy.target_init" value="ether_phy_targets_initialize_rtl8211_rgmii"/>
+      <property id="module.driver.ether_phy.mdio_type" value="module.driver.ether_phy.mdio_type.0"/>
+      <property id="module.driver.ether_phy.auto_negotiation" value="module.driver.ether_phy.auto_negotiation.1"/>
+      <property id="module.driver.ether_phy.bps" value="module.driver.ether_phy.bps.3"/>
+      <property id="module.driver.ether_phy.duplex" value="module.driver.ether_phy.duplex.1"/>
+      <property id="module.driver.ether_phy.reset_port" value="module.driver.ether_phy.reset_port.PORT_13"/>
+      <property id="module.driver.ether_phy.reset_pin" value="module.driver.ether_phy.reset_pin.PIN_04"/>
+      <property id="module.driver.ether_phy.reset_time" value="15000"/>
+    </module>
+    <module id="module.driver.ether_selector_on_ether_selector.671552947">
+      <property id="module.driver.ether_selector.name" value="g_ether_selector1"/>
+      <property id="module.driver.ether_selector.channel" value="module.driver.ether_selector.channel.0"/>
+      <property id="module.driver.ether_selector.phylink" value="module.driver.ether_selector.phylink.low"/>
+      <property id="module.driver.ether_selector.interface_type" value="module.driver.ether_selector.interface_type.rgmii"/>
+      <property id="module.driver.ether_selector.speed" value="module.driver.ether_selector.speed.bps1000m"/>
+      <property id="module.driver.ether_selector.duplex" value="module.driver.ether_selector.duplex.full"/>
+      <property id="module.driver.ether_selector.ref_clock" value="module.driver.ether_selector.ref_clock.input"/>
+    </module>
+    <module id="module.driver.ether_phy_on_ether_phy.513125102">
+      <property id="module.driver.ether_phy.name" value="g_ether_phy2"/>
+      <property id="module.driver.ether_phy.channel" value="module.driver.ether_phy.channel.0"/>
+      <property id="module.driver.ether_phy.phy_lsi_address" value="3"/>
+      <property id="module.driver.ether_phy.phy_reset_wait_time" value="0x00020000"/>
+      <property id="module.driver.ether_phy.flow_control" value="module.driver.ether_phy.flow_control.disable"/>
+      <property id="module.driver.ether_phy.port_type" value="module.driver.ether_phy.port_type.0"/>
+      <property id="module.driver.ether_phy.phy_lsi_type" value="module.driver.ether_phy.phy_lsi_type.custom"/>
+      <property id="module.driver.ether_phy.target_init" value="ether_phy_targets_initialize_rtl8211_rgmii"/>
+      <property id="module.driver.ether_phy.mdio_type" value="module.driver.ether_phy.mdio_type.0"/>
+      <property id="module.driver.ether_phy.auto_negotiation" value="module.driver.ether_phy.auto_negotiation.1"/>
+      <property id="module.driver.ether_phy.bps" value="module.driver.ether_phy.bps.3"/>
+      <property id="module.driver.ether_phy.duplex" value="module.driver.ether_phy.duplex.1"/>
+      <property id="module.driver.ether_phy.reset_port" value="module.driver.ether_phy.reset_port.PORT_13"/>
+      <property id="module.driver.ether_phy.reset_pin" value="module.driver.ether_phy.reset_pin.PIN_04"/>
+      <property id="module.driver.ether_phy.reset_time" value="15000"/>
+    </module>
+    <module id="module.driver.ether_selector_on_ether_selector.1980936079">
+      <property id="module.driver.ether_selector.name" value="g_ether_selector2"/>
+      <property id="module.driver.ether_selector.channel" value="module.driver.ether_selector.channel.0"/>
+      <property id="module.driver.ether_selector.phylink" value="module.driver.ether_selector.phylink.low"/>
+      <property id="module.driver.ether_selector.interface_type" value="module.driver.ether_selector.interface_type.rgmii"/>
+      <property id="module.driver.ether_selector.speed" value="module.driver.ether_selector.speed.bps1000m"/>
+      <property id="module.driver.ether_selector.duplex" value="module.driver.ether_selector.duplex.full"/>
+      <property id="module.driver.ether_selector.ref_clock" value="module.driver.ether_selector.ref_clock.input"/>
+    </module>
+    <module id="module.driver.timer_on_gpt.1285445287">
+      <property id="module.driver.timer.name" value="g_timer0"/>
+      <property id="module.driver.gpt.unit" value="0"/>
+      <property id="module.driver.gpt.channel" value="0"/>
+      <property id="module.driver.timer.mode" value="module.driver.timer.mode.mode_periodic"/>
+      <property id="module.driver.timer.period" value="0x100000000"/>
+      <property id="module.driver.timer.unit" value="module.driver.timer.unit.unit_period_raw_counts"/>
+      <property id="module.driver.timer.duty_cycle" value="50"/>
+      <property id="module.driver.timer.gtioca_output_enabled" value="module.driver.timer.gtioca_output_enabled.false"/>
+      <property id="module.driver.timer.gtioca_stop_level" value="module.driver.timer.gtioca_stop_level.pin_level_low"/>
+      <property id="module.driver.timer.gtiocb_output_enabled" value="module.driver.timer.gtiocb_output_enabled.false"/>
+      <property id="module.driver.timer.gtiocb_stop_level" value="module.driver.timer.gtiocb_stop_level.pin_level_low"/>
+      <property id="module.driver.timer.count_up_source" value=""/>
+      <property id="module.driver.timer.count_down_source" value=""/>
+      <property id="module.driver.timer.phase_count_setting_automatically_enable" value="module.driver.timer.phase_count_setting_automatically_enable.disabled"/>
+      <property id="module.driver.timer.counting_mode" value="module.driver.timer.counting_mode.mode1"/>
+      <property id="module.driver.timer.start_source" value=""/>
+      <property id="module.driver.timer.stop_source" value=""/>
+      <property id="module.driver.timer.clear_source" value=""/>
+      <property id="module.driver.timer.capture_a_source" value=""/>
+      <property id="module.driver.timer.capture_b_source" value=""/>
+      <property id="module.driver.timer.gtioca_filter" value="module.driver.timer.gtioc_filter.gtioc_filter_none"/>
+      <property id="module.driver.timer.gtiocb_filter" value="module.driver.timer.gtioc_filter.gtioc_filter_none"/>
+      <property id="module.driver.timer.p_callback" value="timer0_esc_callback"/>
+      <property id="module.driver.timer.ipl" value="board.icu.common.irq.priority10"/>
+      <property id="module.driver.timer.capture_a_ipl" value="_disabled"/>
+      <property id="module.driver.timer.capture_b_ipl" value="_disabled"/>
+      <property id="module.driver.timer.trough_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.p_callback" value="NULL"/>
+      <property id="module.driver.timer.gpt_sel.overflow_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.capture_a_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.capture_b_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.trough_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.dead_time_error_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.int0_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int1_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int2_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int3_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int4_ipl" value="_disabled"/>
+      <property id="module.driver.timer.extra" value="module.driver.timer.extra.disabled"/>
+      <property id="module.driver.timer.poeg_link" value="module.driver.timer.poeg_link.poeg_link_poeg0"/>
+      <property id="module.driver.timer.output_disable" value=""/>
+      <property id="module.driver.timer.adc_trigger" value=""/>
+      <property id="module.driver.timer.dead_time_count_up" value="0"/>
+      <property id="module.driver.timer.dead_time_count_down" value="0"/>
+      <property id="module.driver.timer.adc_a_compare_match" value="0"/>
+      <property id="module.driver.timer.adc_b_compare_match" value="0"/>
+      <property id="module.driver.timer.interrupt_skip.source" value="module.driver.timer.interrupt_skip.source.none"/>
+      <property id="module.driver.timer.interrupt_skip.count" value="module.driver.timer.interrupt_skip.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip.adc" value="module.driver.timer.interrupt_skip.skip_sources.interrupt_skip.adc.none"/>
+      <property id="module.driver.timer.gtioca_disable_setting" value="module.driver.timer.gtioca_disable_setting.gtioc_disable_prohibited"/>
+      <property id="module.driver.timer.gtiocb_disable_setting" value="module.driver.timer.gtiocb_disable_setting.gtioc_disable_prohibited"/>
+      <property id="module.driver.timer.interrupt_skip_ext1.source" value="module.driver.timer.interrupt_skip_ext1.source.none"/>
+      <property id="module.driver.timer.interrupt_skip_ext1.count" value="module.driver.timer.interrupt_skip_ext1.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_ext2.source" value="module.driver.timer.interrupt_skip_ext2.source.none"/>
+      <property id="module.driver.timer.interrupt_skip_ext2.count" value="module.driver.timer.interrupt_skip_ext2.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_func.ovf" value="module.driver.timer.interrupt_skip_func.ovf.none"/>
+      <property id="module.driver.timer.interrupt_skip_func.unf" value="module.driver.timer.interrupt_skip_func.unf.none"/>
+      <property id="module.driver.timer.interrupt_skip_func.adc_a" value="module.driver.timer.interrupt_skip_func.adc_a.none"/>
+      <property id="module.driver.timer.interrupt_skip_func.adc_b" value="module.driver.timer.interrupt_skip_func.adc_b.none"/>
+      <property id="module.driver.timer.dead_time_error_ipl" value="_disabled"/>
+      <property id="module.driver.timer.input_capture" value="module.driver.timer.input_capture.enabled"/>
+      <property id="module.driver.timer.gtioc_isel" value="module.driver.timer.gtioc_isel.not_supported"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_a" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_b" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_c" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_d" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_e" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_f" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_g" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_h" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_a" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_b" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_c" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_d" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_e" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_f" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_g" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_h" value="_disabled"/>
+    </module>
+    <module id="module.driver.timer_on_mtu3.1982797798">
+      <property id="module.driver.timer.name" value="g_mtu3"/>
+      <property id="module.driver.timer.channel" value="0"/>
+      <property id="module.driver.timer.mode" value="module.driver.timer.mode.mode_periodic"/>
+      <property id="module.driver.timer.tgra_val" value="0xFFFF"/>
+      <property id="module.driver.timer.tgrb_val" value="0xFFFF"/>
+      <property id="module.driver.timer.mtu3_clk_div" value="module.driver.timer.mtu3_clk_div.div1"/>
+      <property id="module.driver.timer.clk_edge" value="module.driver.timer.clk_edge.rising"/>
+      <property id="module.driver.timer.mtu3_clear" value="module.driver.timer.mtu3_clear.disabled"/>
+      <property id="module.driver.timer.bit_mode" value="module.driver.timer.bit_mode.16"/>
+      <property id="module.driver.timer.mtu3.counting_mode" value="module.driver.timer.mtu3.counting_mode.none"/>
+      <property id="module.driver.timer.input_clock_pin" value="module.driver.timer.input_clock_pin.a_b"/>
+      <property id="module.driver.timer.external_noise_filter.enable" value=""/>
+      <property id="module.driver.timer.external_noise_filter.clock" value="module.driver.timer.external_noise_filter.clock.div1"/>
+      <property id="module.driver.timer.input_noise_filter.enable" value=""/>
+      <property id="module.driver.timer.input_noise_filter.clock" value="module.driver.timer.input_noise_filter.clock.div1"/>
+      <property id="module.driver.timer.output_pin_level_a" value="module.driver.timer.output_pin_level_a.no_output"/>
+      <property id="module.driver.timer.output_pin_level_b" value="module.driver.timer.output_pin_level_b.no_output"/>
+      <property id="module.driver.timer.p_callback" value="g_mtu3_callback"/>
+      <property id="module.driver.timer.ipl" value="board.icu.common.irq.priority8"/>
+      <property id="module.driver.timer.capture_a_ipl" value="_disabled"/>
+      <property id="module.driver.timer.capture_b_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.p_callback" value="NULL"/>
+      <property id="module.driver.timer.gpt_sel.overflow_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.capture_a_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.capture_b_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.int0_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int1_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int2_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int3_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int4_ipl" value="_disabled"/>
+      <property id="module.driver.timer.extra" value="module.driver.timer.extra.disabled"/>
+      <property id="module.driver.timer.tgru_val" value="0x0000"/>
+      <property id="module.driver.timer.tgrv_val" value="0x0000"/>
+      <property id="module.driver.timer.tgrw_val" value="0x0000"/>
+      <property id="module.driver.timer.mtu3_clk_div_u" value="module.driver.timer.mtu3_clk_div_u.div1"/>
+      <property id="module.driver.timer.mtu3_clk_div_v" value="module.driver.timer.mtu3_clk_div_v.div1"/>
+      <property id="module.driver.timer.mtu3_clk_div_w" value="module.driver.timer.mtu3_clk_div_w.div1"/>
+      <property id="module.driver.timer.output_pin_level_u" value="module.driver.timer.output_pin_level_u.no_func"/>
+      <property id="module.driver.timer.output_pin_level_v" value="module.driver.timer.output_pin_level_v.no_func"/>
+      <property id="module.driver.timer.output_pin_level_w" value="module.driver.timer.output_pin_level_w.no_func"/>
+      <property id="module.driver.timer.capture_u_ipl" value="_disabled"/>
+      <property id="module.driver.timer.capture_v_ipl" value="_disabled"/>
+      <property id="module.driver.timer.capture_w_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.capture_u_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.capture_v_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.capture_w_interrupt_source" value=""/>
+      <property id="module.driver.timer.noise_filter_mtioc_setting_uvw" value="module.driver.timer.noise_filter_mtioc_setting_uvw.disabled"/>
+      <property id="module.driver.timer.noise_filter_mtioc_clk_uvw" value="module.driver.timer.noise_filter_mtioc_clk_uvw.div1"/>
+      <property id="module.driver.timer.interrupt_skip_mode_a" value="module.driver.timer.interrupt_skip_mode_a.mode1"/>
+      <property id="module.driver.timer.interrupt_skip_mode_b" value="module.driver.timer.interrupt_skip_mode_b.mode1"/>
+      <property id="module.driver.timer.adc_a_compare_match" value="0x0000"/>
+      <property id="module.driver.timer.adc_b_compare_match" value="0x0000"/>
+      <property id="module.driver.timer.interrupt_skip_tciv4.count" value="module.driver.timer.interrupt_skip_tciv4.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_tgia3.count" value="module.driver.timer.interrupt_skip_tgia3.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_tciv7.count" value="module.driver.timer.interrupt_skip_tciv7.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_tgia6.count" value="module.driver.timer.interrupt_skip_tgia6.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_tgr4an_bn.count" value="module.driver.timer.interrupt_skip_tgr4an_bn.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_tgr7an_bn.count" value="module.driver.timer.interrupt_skip_tgr7an_bn.count.count_0"/>
+      <property id="module.driver.timer.ad_start" value="module.driver.timer.ad_start.disabled"/>
+      <property id="module.driver.timer.elc_trigger_mtu0" value="_disabled"/>
+      <property id="module.driver.timer.operation_select_mtu0" value="Disabled"/>
+      <property id="module.driver.timer.elc_trigger_mtu3" value="_disabled"/>
+      <property id="module.driver.timer.operation_select_mtu3" value="Disabled"/>
+      <property id="module.driver.timer.elc_trigger_mtu4" value="_disabled"/>
+      <property id="module.driver.timer.operation_select_mtu4" value="Disabled"/>
+    </module>
+    <module id="module.driver.timer_on_gpt.1352861500">
+      <property id="module.driver.timer.name" value="g_timer1"/>
+      <property id="module.driver.gpt.unit" value="0"/>
+      <property id="module.driver.gpt.channel" value="1"/>
+      <property id="module.driver.timer.mode" value="module.driver.timer.mode.mode_periodic"/>
+      <property id="module.driver.timer.period" value="1"/>
+      <property id="module.driver.timer.unit" value="module.driver.timer.unit.unit_period_usec"/>
+      <property id="module.driver.timer.duty_cycle" value="50"/>
+      <property id="module.driver.timer.gtioca_output_enabled" value="module.driver.timer.gtioca_output_enabled.false"/>
+      <property id="module.driver.timer.gtioca_stop_level" value="module.driver.timer.gtioca_stop_level.pin_level_low"/>
+      <property id="module.driver.timer.gtiocb_output_enabled" value="module.driver.timer.gtiocb_output_enabled.false"/>
+      <property id="module.driver.timer.gtiocb_stop_level" value="module.driver.timer.gtiocb_stop_level.pin_level_low"/>
+      <property id="module.driver.timer.count_up_source" value=""/>
+      <property id="module.driver.timer.count_down_source" value=""/>
+      <property id="module.driver.timer.phase_count_setting_automatically_enable" value="module.driver.timer.phase_count_setting_automatically_enable.disabled"/>
+      <property id="module.driver.timer.counting_mode" value="module.driver.timer.counting_mode.mode1"/>
+      <property id="module.driver.timer.start_source" value=""/>
+      <property id="module.driver.timer.stop_source" value=""/>
+      <property id="module.driver.timer.clear_source" value=""/>
+      <property id="module.driver.timer.capture_a_source" value=""/>
+      <property id="module.driver.timer.capture_b_source" value=""/>
+      <property id="module.driver.timer.gtioca_filter" value="module.driver.timer.gtioc_filter.gtioc_filter_none"/>
+      <property id="module.driver.timer.gtiocb_filter" value="module.driver.timer.gtioc_filter.gtioc_filter_none"/>
+      <property id="module.driver.timer.p_callback" value="g_timer1_callback"/>
+      <property id="module.driver.timer.ipl" value="board.icu.common.irq.priority10"/>
+      <property id="module.driver.timer.capture_a_ipl" value="_disabled"/>
+      <property id="module.driver.timer.capture_b_ipl" value="_disabled"/>
+      <property id="module.driver.timer.trough_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.p_callback" value="NULL"/>
+      <property id="module.driver.timer.gpt_sel.overflow_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.capture_a_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.capture_b_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.trough_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.dead_time_error_interrupt_source" value=""/>
+      <property id="module.driver.timer.gpt_sel.int0_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int1_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int2_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int3_ipl" value="_disabled"/>
+      <property id="module.driver.timer.gpt_sel.int4_ipl" value="_disabled"/>
+      <property id="module.driver.timer.extra" value="module.driver.timer.extra.disabled"/>
+      <property id="module.driver.timer.poeg_link" value="module.driver.timer.poeg_link.poeg_link_poeg0"/>
+      <property id="module.driver.timer.output_disable" value=""/>
+      <property id="module.driver.timer.adc_trigger" value=""/>
+      <property id="module.driver.timer.dead_time_count_up" value="0"/>
+      <property id="module.driver.timer.dead_time_count_down" value="0"/>
+      <property id="module.driver.timer.adc_a_compare_match" value="0"/>
+      <property id="module.driver.timer.adc_b_compare_match" value="0"/>
+      <property id="module.driver.timer.interrupt_skip.source" value="module.driver.timer.interrupt_skip.source.none"/>
+      <property id="module.driver.timer.interrupt_skip.count" value="module.driver.timer.interrupt_skip.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip.adc" value="module.driver.timer.interrupt_skip.skip_sources.interrupt_skip.adc.none"/>
+      <property id="module.driver.timer.gtioca_disable_setting" value="module.driver.timer.gtioca_disable_setting.gtioc_disable_prohibited"/>
+      <property id="module.driver.timer.gtiocb_disable_setting" value="module.driver.timer.gtiocb_disable_setting.gtioc_disable_prohibited"/>
+      <property id="module.driver.timer.interrupt_skip_ext1.source" value="module.driver.timer.interrupt_skip_ext1.source.none"/>
+      <property id="module.driver.timer.interrupt_skip_ext1.count" value="module.driver.timer.interrupt_skip_ext1.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_ext2.source" value="module.driver.timer.interrupt_skip_ext2.source.none"/>
+      <property id="module.driver.timer.interrupt_skip_ext2.count" value="module.driver.timer.interrupt_skip_ext2.count.count_0"/>
+      <property id="module.driver.timer.interrupt_skip_func.ovf" value="module.driver.timer.interrupt_skip_func.ovf.none"/>
+      <property id="module.driver.timer.interrupt_skip_func.unf" value="module.driver.timer.interrupt_skip_func.unf.none"/>
+      <property id="module.driver.timer.interrupt_skip_func.adc_a" value="module.driver.timer.interrupt_skip_func.adc_a.none"/>
+      <property id="module.driver.timer.interrupt_skip_func.adc_b" value="module.driver.timer.interrupt_skip_func.adc_b.none"/>
+      <property id="module.driver.timer.dead_time_error_ipl" value="_disabled"/>
+      <property id="module.driver.timer.input_capture" value="module.driver.timer.input_capture.enabled"/>
+      <property id="module.driver.timer.gtioc_isel" value="module.driver.timer.gtioc_isel.not_supported"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_a" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_b" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_c" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_d" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_e" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_f" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_g" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_llpp_event_h" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_a" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_b" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_c" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_d" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_e" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_f" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_g" value="_disabled"/>
+      <property id="module.driver.timer.elc_trigger_nonsafty_event_h" value="_disabled"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+      <stack module="module.bsp.memory_config.0"/>
+      <stack module="module.driver.uart_on_sci_uart.1968866849"/>
+      <stack module="module.driver.ether_on_ether.1094288014">
+        <stack module="module.driver.ether_phy_on_ether_phy.277662383" requires="module.driver.ether.requires.ether_phy0">
+          <stack module="module.driver.ether_selector_on_ether_selector.305883093" requires="module.driver.ether.requires.ether_selector"/>
+        </stack>
+        <stack module="module.driver.ether_phy_on_ether_phy.518802053" requires="module.driver.ether.requires.ether_phy1">
+          <stack module="module.driver.ether_selector_on_ether_selector.671552947" requires="module.driver.ether.requires.ether_selector"/>
+        </stack>
+        <stack module="module.driver.ether_phy_on_ether_phy.513125102" requires="module.driver.ether.requires.ether_phy2">
+          <stack module="module.driver.ether_selector_on_ether_selector.1980936079" requires="module.driver.ether.requires.ether_selector"/>
+        </stack>
+        <stack module="module.driver.ether_switch_on_ether_switch.95659619" requires="module.driver.ether.requires.ethsw"/>
+      </stack>
+      <stack module="module.driver.timer_on_gpt.1285445287"/>
+      <stack module="module.driver.timer_on_mtu3.1982797798"/>
+      <stack module="module.driver.timer_on_gpt.1352861500"/>
+    </context>
+    <config id="config.driver.ether_selector">
+      <property id="config.driver.ether_selector.param_checking_enable" value="config.driver.ether_selector.param_checking_enable.bsp"/>
+      <property id="module.driver.ether_selector.mode" value="module.driver.ether_selector.mode.0"/>
+    </config>
+    <config id="config.driver.ether_phy">
+      <property id="config.driver.ether_phy.param_checking_enable" value="config.driver.ether_phy.param_checking_enable.bsp"/>
+      <property id="config.driver.ether_phy.target_vsc8541" value="config.driver.ether_phy.target_vsc8541.disabled"/>
+      <property id="config.driver.ether_phy.target_ksz9131" value="config.driver.ether_phy.target_ksz9131.disabled"/>
+      <property id="config.driver.ether_phy.target_ksz9031" value="config.driver.ether_phy.target_ksz9031.disabled"/>
+      <property id="config.driver.ether_phy.target_ksz8081" value="config.driver.ether_phy.target_ksz8081.disabled"/>
+      <property id="config.driver.ether_phy.target_ksz8041" value="config.driver.ether_phy.target_ksz8041.disabled"/>
+      <property id="config.driver.ether_phy.use_custom_phy_lsi" value="config.driver.ether_phy.use_custom_phy_lsi.enabled"/>
+    </config>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+    <config id="config.driver.mtu3">
+      <property id="config.driver.mtu3.param_checking_enable" value="config.driver.mtu3.param_checking_enable.bsp"/>
+      <property id="config.driver.mtu3.output_support_enable" value="config.driver.mtu3.output_support_enable.disabled"/>
+      <property id="config.driver.mtu3.uvw_support_enable" value="config.driver.mtu3.uvw_support_enable.disabled"/>
+      <property id="config.driver.mtu3.multiplex_interrupt" value="config.driver.mtu3.multiplex_interrupt.disabled"/>
+    </config>
+    <config id="config.driver.ether">
+      <property id="config.driver.ether.param_checking_enable" value="config.driver.ether.param_checking_enable.bsp"/>
+    </config>
+    <config id="config.driver.sci_uart">
+      <property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
+      <property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.enabled"/>
+      <property id="config.driver.sci_uart.dmac_support" value="config.driver.sci_uart.dmac_support.disabled"/>
+      <property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
+      <property id="config.driver.sci_uart.multiplex_interrupt" value="config.driver.sci_uart.multiplex_interrupt.disabled"/>
+    </config>
+    <config id="config.driver.ether_switch">
+      <property id="config.driver.ether_switch.param_checking_enable" value="config.driver.ether_switch.param_checking_enable.bsp"/>
+    </config>
+    <config id="config.bsp.memory_config">
+      <property id="config.bsp.memory_config.mpu_type" value="config.bsp.memory_config.mpu_type.mpu"/>
+    </config>
+    <config id="config.driver.gpt">
+      <property id="config.driver.gpt.param_checking_enable" value="config.driver.gpt.param_checking_enable.bsp"/>
+      <property id="config.driver.gpt.output_support_enable" value="config.driver.gpt.output_support_enable.disabled"/>
+      <property id="config.driver.gpt.write_protect_enable" value="config.driver.gpt.write_protect_enable.disabled"/>
+      <property id="config.driver.gpt.multiplex_interrupt" value="config.driver.gpt.multiplex_interrupt.disabled"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p00_0.symbolic_name" value="ETH2_RXD3"/>
+    <symbolicName propertyId="p00_1.symbolic_name" value="ETH2_RXDV"/>
+    <symbolicName propertyId="p00_2.symbolic_name" value="ETH2_TXEN"/>
+    <symbolicName propertyId="p00_3.symbolic_name" value="ETH2_REFCLK"/>
+    <symbolicName propertyId="p00_5.symbolic_name" value="ETH2_LINK"/>
+    <symbolicName propertyId="p00_6.symbolic_name" value="ETH2_TXCLK"/>
+    <symbolicName propertyId="p01_2.symbolic_name" value="ETH2_TXD3"/>
+    <symbolicName propertyId="p01_3.symbolic_name" value="ETH2_TXD2"/>
+    <symbolicName propertyId="p01_4.symbolic_name" value="ETH2_TXD1"/>
+    <symbolicName propertyId="p01_5.symbolic_name" value="ETH2_TXD0"/>
+    <symbolicName propertyId="p01_7.symbolic_name" value="CAN_RX"/>
+    <symbolicName propertyId="p02_2.symbolic_name" value="CAN_TX"/>
+    <symbolicName propertyId="p02_4.symbolic_name" value="TDO"/>
+    <symbolicName propertyId="p02_5.symbolic_name" value="TDI"/>
+    <symbolicName propertyId="p02_6.symbolic_name" value="TMS"/>
+    <symbolicName propertyId="p02_7.symbolic_name" value="TCK"/>
+    <symbolicName propertyId="p03_0.symbolic_name" value="ETH_LED4"/>
+    <symbolicName propertyId="p04_1.symbolic_name" value="LED_RED1"/>
+    <symbolicName propertyId="p04_4.symbolic_name" value="ETH_LED6"/>
+    <symbolicName propertyId="p05_0.symbolic_name" value="ETH_LED7"/>
+    <symbolicName propertyId="p05_2.symbolic_name" value="SCL"/>
+    <symbolicName propertyId="p05_3.symbolic_name" value="SDA"/>
+    <symbolicName propertyId="p05_4.symbolic_name" value="SW2"/>
+    <symbolicName propertyId="p05_5.symbolic_name" value="ETH1_LINK"/>
+    <symbolicName propertyId="p05_7.symbolic_name" value="ETH1_TXD2"/>
+    <symbolicName propertyId="p06_0.symbolic_name" value="ETH1_TXD3"/>
+    <symbolicName propertyId="p06_1.symbolic_name" value="ETH1_REFCLK"/>
+    <symbolicName propertyId="p06_2.symbolic_name" value="ETH1_TXD1"/>
+    <symbolicName propertyId="p06_3.symbolic_name" value="ETH1_TXD0"/>
+    <symbolicName propertyId="p06_4.symbolic_name" value="ETH1_TXCLK"/>
+    <symbolicName propertyId="p06_5.symbolic_name" value="ETH1_TXEN"/>
+    <symbolicName propertyId="p06_6.symbolic_name" value="ETH1_RXD0"/>
+    <symbolicName propertyId="p06_7.symbolic_name" value="ETH1_RXD1"/>
+    <symbolicName propertyId="p07_0.symbolic_name" value="ETH1_RXD2"/>
+    <symbolicName propertyId="p07_1.symbolic_name" value="ETH1_RXD3"/>
+    <symbolicName propertyId="p07_2.symbolic_name" value="ETH1_RXDV"/>
+    <symbolicName propertyId="p07_3.symbolic_name" value="ETH1_RXCLK"/>
+    <symbolicName propertyId="p07_4.symbolic_name" value="USB_VBUSIN"/>
+    <symbolicName propertyId="p08_4.symbolic_name" value="ETH0_RXD3"/>
+    <symbolicName propertyId="p08_5.symbolic_name" value="ETH0_RXDV"/>
+    <symbolicName propertyId="p08_6.symbolic_name" value="ETH0_RXCLK"/>
+    <symbolicName propertyId="p08_7.symbolic_name" value="ETH_MDC"/>
+    <symbolicName propertyId="p09_0.symbolic_name" value="ETH_MDIO"/>
+    <symbolicName propertyId="p09_1.symbolic_name" value="ETH0_REFCLK"/>
+    <symbolicName propertyId="p09_3.symbolic_name" value="ETH0_TXD3"/>
+    <symbolicName propertyId="p09_4.symbolic_name" value="ETH0_TXD2"/>
+    <symbolicName propertyId="p09_5.symbolic_name" value="ETH0_TXD1"/>
+    <symbolicName propertyId="p09_6.symbolic_name" value="ETH0_TXD0"/>
+    <symbolicName propertyId="p09_7.symbolic_name" value="ETH0_TXCLK"/>
+    <symbolicName propertyId="p10_0.symbolic_name" value="ETH0_TXEN"/>
+    <symbolicName propertyId="p10_1.symbolic_name" value="ETH0_RXD0"/>
+    <symbolicName propertyId="p10_2.symbolic_name" value="ETH0_RXD1"/>
+    <symbolicName propertyId="p10_3.symbolic_name" value="ETH0_RXD2"/>
+    <symbolicName propertyId="p10_4.symbolic_name" value="ETH0_LINK"/>
+    <symbolicName propertyId="p13_2.symbolic_name" value="EEPROM_SCL"/>
+    <symbolicName propertyId="p13_3.symbolic_name" value="EEPROM_SDA"/>
+    <symbolicName propertyId="p13_4.symbolic_name" value="ESC_RESETOUT"/>
+    <symbolicName propertyId="p13_5.symbolic_name" value="SW3_Pin2"/>
+    <symbolicName propertyId="p13_6.symbolic_name" value="SW3_Pin1"/>
+    <symbolicName propertyId="p13_7.symbolic_name" value="SW3_Pin4"/>
+    <symbolicName propertyId="p14_0.symbolic_name" value="SW3_Pin3"/>
+    <symbolicName propertyId="p14_2.symbolic_name" value="XSPI0_ECS"/>
+    <symbolicName propertyId="p14_4.symbolic_name" value="XSPI0_DS"/>
+    <symbolicName propertyId="p14_5.symbolic_name" value="XSPI0_CKN"/>
+    <symbolicName propertyId="p14_6.symbolic_name" value="XSPI0_CKP"/>
+    <symbolicName propertyId="p14_7.symbolic_name" value="XSPI0_IO0"/>
+    <symbolicName propertyId="p15_0.symbolic_name" value="XSPI0_IO1"/>
+    <symbolicName propertyId="p15_1.symbolic_name" value="XSPI0_IO2"/>
+    <symbolicName propertyId="p15_2.symbolic_name" value="XSPI0_IO3"/>
+    <symbolicName propertyId="p15_3.symbolic_name" value="XSPI0_IO4"/>
+    <symbolicName propertyId="p15_4.symbolic_name" value="XSPI0_IO5"/>
+    <symbolicName propertyId="p15_5.symbolic_name" value="XSPI0_IO6"/>
+    <symbolicName propertyId="p15_6.symbolic_name" value="XSPI0_IO7"/>
+    <symbolicName propertyId="p15_7.symbolic_name" value="OSPI_CS"/>
+    <symbolicName propertyId="p16_0.symbolic_name" value="ORAM_CS0"/>
+    <symbolicName propertyId="p16_1.symbolic_name" value="XSPI0_RESET0"/>
+    <symbolicName propertyId="p16_3.symbolic_name" value="SW1"/>
+    <symbolicName propertyId="p16_5.symbolic_name" value="UART_USB_TX"/>
+    <symbolicName propertyId="p16_6.symbolic_name" value="UART_USB_RX"/>
+    <symbolicName propertyId="p17_3.symbolic_name" value="LED_RED2"/>
+    <symbolicName propertyId="p17_5.symbolic_name" value="USB_OVRCUR"/>
+    <symbolicName propertyId="p17_7.symbolic_name" value="SCI_RXD"/>
+    <symbolicName propertyId="p18_0.symbolic_name" value="SCI_TXD"/>
+    <symbolicName propertyId="p18_2.symbolic_name" value="LED_GREEN"/>
+    <symbolicName propertyId="p18_4.symbolic_name" value="SCK"/>
+    <symbolicName propertyId="p18_5.symbolic_name" value="MOSI"/>
+    <symbolicName propertyId="p18_6.symbolic_name" value="MISO"/>
+    <symbolicName propertyId="p19_0.symbolic_name" value="USB_VBUSEN"/>
+    <symbolicName propertyId="p20_1.symbolic_name" value="ETH_LED2_MDV0"/>
+    <symbolicName propertyId="p20_2.symbolic_name" value="ETH_LED0_MDV1"/>
+    <symbolicName propertyId="p20_3.symbolic_name" value="ETH_LED1_MDV2"/>
+    <symbolicName propertyId="p20_4.symbolic_name" value="ETH_LED3_MDV3"/>
+    <symbolicName propertyId="p21_1.symbolic_name" value="CS"/>
+    <symbolicName propertyId="p22_1.symbolic_name" value="ETH_LED5"/>
+    <symbolicName propertyId="p22_3.symbolic_name" value="LED_ORANGE"/>
+    <symbolicName propertyId="p23_7.symbolic_name" value="ETH2_RXD0"/>
+    <symbolicName propertyId="p24_0.symbolic_name" value="ETH2_RXD1"/>
+    <symbolicName propertyId="p24_1.symbolic_name" value="ETH2_RXCLK"/>
+    <symbolicName propertyId="p24_2.symbolic_name" value="ETH2_RXD2"/>
+    <pincfg active="true" name="RSK+RZN2L" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="canfd0.canrx0.p01_7" configurationId="canfd0.canrx0"/>
+      <configSetting altId="canfd0.cantx0.p02_2" configurationId="canfd0.cantx0"/>
+      <configSetting altId="canfd0.mode.enabled.free" configurationId="canfd0.mode"/>
+      <configSetting altId="ether_eth0.eth0_refclk.p09_1" configurationId="ether_eth0.eth0_refclk"/>
+      <configSetting altId="ether_eth0.eth0_rxclk_ref_clk_rxc.p08_6" configurationId="ether_eth0.eth0_rxclk_ref_clk_rxc"/>
+      <configSetting altId="ether_eth0.eth0_rxd0.p10_1" configurationId="ether_eth0.eth0_rxd0"/>
+      <configSetting altId="ether_eth0.eth0_rxd1.p10_2" configurationId="ether_eth0.eth0_rxd1"/>
+      <configSetting altId="ether_eth0.eth0_rxd2.p10_3" configurationId="ether_eth0.eth0_rxd2"/>
+      <configSetting altId="ether_eth0.eth0_rxd3.p08_4" configurationId="ether_eth0.eth0_rxd3"/>
+      <configSetting altId="ether_eth0.eth0_rxdv_crsdv_rxctl.p08_5" configurationId="ether_eth0.eth0_rxdv_crsdv_rxctl"/>
+      <configSetting altId="ether_eth0.eth0_txclk_txc.p09_7" configurationId="ether_eth0.eth0_txclk_txc"/>
+      <configSetting altId="ether_eth0.eth0_txd0.p09_6" configurationId="ether_eth0.eth0_txd0"/>
+      <configSetting altId="ether_eth0.eth0_txd1.p09_5" configurationId="ether_eth0.eth0_txd1"/>
+      <configSetting altId="ether_eth0.eth0_txd2.p09_4" configurationId="ether_eth0.eth0_txd2"/>
+      <configSetting altId="ether_eth0.eth0_txd3.p09_3" configurationId="ether_eth0.eth0_txd3"/>
+      <configSetting altId="ether_eth0.eth0_txen_txctl.p10_0" configurationId="ether_eth0.eth0_txen_txctl"/>
+      <configSetting altId="ether_eth0.mode.rgmiimode.free" configurationId="ether_eth0.mode"/>
+      <configSetting altId="ether_eth1.eth1_refclk.p06_1" configurationId="ether_eth1.eth1_refclk"/>
+      <configSetting altId="ether_eth1.eth1_rxclk_ref_clk_rxc.p07_3" configurationId="ether_eth1.eth1_rxclk_ref_clk_rxc"/>
+      <configSetting altId="ether_eth1.eth1_rxd0.p06_6" configurationId="ether_eth1.eth1_rxd0"/>
+      <configSetting altId="ether_eth1.eth1_rxd1.p06_7" configurationId="ether_eth1.eth1_rxd1"/>
+      <configSetting altId="ether_eth1.eth1_rxd2.p07_0" configurationId="ether_eth1.eth1_rxd2"/>
+      <configSetting altId="ether_eth1.eth1_rxd3.p07_1" configurationId="ether_eth1.eth1_rxd3"/>
+      <configSetting altId="ether_eth1.eth1_rxdv_crsdv_rxctl.p07_2" configurationId="ether_eth1.eth1_rxdv_crsdv_rxctl"/>
+      <configSetting altId="ether_eth1.eth1_txclk_txc.p06_4" configurationId="ether_eth1.eth1_txclk_txc"/>
+      <configSetting altId="ether_eth1.eth1_txd0.p06_3" configurationId="ether_eth1.eth1_txd0"/>
+      <configSetting altId="ether_eth1.eth1_txd1.p06_2" configurationId="ether_eth1.eth1_txd1"/>
+      <configSetting altId="ether_eth1.eth1_txd2.p05_7" configurationId="ether_eth1.eth1_txd2"/>
+      <configSetting altId="ether_eth1.eth1_txd3.p06_0" configurationId="ether_eth1.eth1_txd3"/>
+      <configSetting altId="ether_eth1.eth1_txen_txctl.p06_5" configurationId="ether_eth1.eth1_txen_txctl"/>
+      <configSetting altId="ether_eth1.mode.rgmiimode.free" configurationId="ether_eth1.mode"/>
+      <configSetting altId="ether_eth2.eth2_refclk.p00_3" configurationId="ether_eth2.eth2_refclk"/>
+      <configSetting altId="ether_eth2.eth2_rxclk_ref_clk_rxc.p24_1" configurationId="ether_eth2.eth2_rxclk_ref_clk_rxc"/>
+      <configSetting altId="ether_eth2.eth2_rxd0.p23_7" configurationId="ether_eth2.eth2_rxd0"/>
+      <configSetting altId="ether_eth2.eth2_rxd1.p24_0" configurationId="ether_eth2.eth2_rxd1"/>
+      <configSetting altId="ether_eth2.eth2_rxd2.p24_2" configurationId="ether_eth2.eth2_rxd2"/>
+      <configSetting altId="ether_eth2.eth2_rxd3.p00_0" configurationId="ether_eth2.eth2_rxd3"/>
+      <configSetting altId="ether_eth2.eth2_rxdv_crsdv_rxctl.p00_1" configurationId="ether_eth2.eth2_rxdv_crsdv_rxctl"/>
+      <configSetting altId="ether_eth2.eth2_txclk_txc.p00_6" configurationId="ether_eth2.eth2_txclk_txc"/>
+      <configSetting altId="ether_eth2.eth2_txd0.p01_5" configurationId="ether_eth2.eth2_txd0"/>
+      <configSetting altId="ether_eth2.eth2_txd1.p01_4" configurationId="ether_eth2.eth2_txd1"/>
+      <configSetting altId="ether_eth2.eth2_txd2.p01_3" configurationId="ether_eth2.eth2_txd2"/>
+      <configSetting altId="ether_eth2.eth2_txd3.p01_2" configurationId="ether_eth2.eth2_txd3"/>
+      <configSetting altId="ether_eth2.eth2_txen_txctl.p00_2" configurationId="ether_eth2.eth2_txen_txctl"/>
+      <configSetting altId="ether_eth2.mode.rgmiimode.free" configurationId="ether_eth2.mode"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink0.p10_4" configurationId="ether_ethsw.ethsw_phylink0"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink1.p05_5" configurationId="ether_ethsw.ethsw_phylink1"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink2.p00_5" configurationId="ether_ethsw.ethsw_phylink2"/>
+      <configSetting altId="ether_ethsw.mode.custom_40_1.8v_41.free" configurationId="ether_ethsw.mode"/>
+      <configSetting altId="ether_gmac.gmac_mdc.p08_7" configurationId="ether_gmac.gmac_mdc"/>
+      <configSetting altId="ether_gmac.gmac_mdio.p09_0" configurationId="ether_gmac.gmac_mdio"/>
+      <configSetting altId="ether_gmac.mode.custom_40_1.8v_41.free" configurationId="ether_gmac.mode"/>
+      <configSetting altId="iic0.iic_scl0.p13_2" configurationId="iic0.iic_scl0"/>
+      <configSetting altId="iic0.iic_sda0.p13_3" configurationId="iic0.iic_sda0"/>
+      <configSetting altId="iic0.mode.enabled.free" configurationId="iic0.mode"/>
+      <configSetting altId="iic1.iic_scl1.p05_2" configurationId="iic1.iic_scl1"/>
+      <configSetting altId="iic1.iic_sda1.p05_3" configurationId="iic1.iic_sda1"/>
+      <configSetting altId="iic1.mode.enabled.free" configurationId="iic1.mode"/>
+      <configSetting altId="jtag_fslash_swd.mode.jtag.free" configurationId="jtag_fslash_swd.mode"/>
+      <configSetting altId="jtag_fslash_swd.tck_swclk.p02_7" configurationId="jtag_fslash_swd.tck_swclk"/>
+      <configSetting altId="jtag_fslash_swd.tdi.p02_5" configurationId="jtag_fslash_swd.tdi"/>
+      <configSetting altId="jtag_fslash_swd.tdo.p02_4" configurationId="jtag_fslash_swd.tdo"/>
+      <configSetting altId="jtag_fslash_swd.tms_swdio.p02_6" configurationId="jtag_fslash_swd.tms_swdio"/>
+      <configSetting altId="p00_0.ether_eth2.eth2_rxd3" configurationId="p00_0"/>
+      <configSetting altId="p00_0.gpio_mode.gpio_mode_peripheral" configurationId="p00_0.gpio_mode"/>
+      <configSetting altId="p00_1.ether_eth2.eth2_rxdv_crsdv_rxctl" configurationId="p00_1"/>
+      <configSetting altId="p00_1.gpio_mode.gpio_mode_peripheral" configurationId="p00_1.gpio_mode"/>
+      <configSetting altId="p00_2.ether_eth2.eth2_txen_txctl" configurationId="p00_2"/>
+      <configSetting altId="p00_2.gpio_mode.gpio_mode_peripheral" configurationId="p00_2.gpio_mode"/>
+      <configSetting altId="p00_3.ether_eth2.eth2_refclk" configurationId="p00_3"/>
+      <configSetting altId="p00_3.gpio_mode.gpio_mode_peripheral" configurationId="p00_3.gpio_mode"/>
+      <configSetting altId="p00_5.ether_ethsw.ethsw_phylink2" configurationId="p00_5"/>
+      <configSetting altId="p00_5.gpio_mode.gpio_mode_peripheral" configurationId="p00_5.gpio_mode"/>
+      <configSetting altId="p00_6.ether_eth2.eth2_txclk_txc" configurationId="p00_6"/>
+      <configSetting altId="p00_6.gpio_speed.gpio_speed_high" configurationId="p00_6.gpio_drivecapacity"/>
+      <configSetting altId="p00_6.gpio_mode.gpio_mode_peripheral" configurationId="p00_6.gpio_mode"/>
+      <configSetting altId="p00_6.sr.sr.fast" configurationId="p00_6.sr"/>
+      <configSetting altId="p01_2.ether_eth2.eth2_txd3" configurationId="p01_2"/>
+      <configSetting altId="p01_2.gpio_speed.gpio_speed_high" configurationId="p01_2.gpio_drivecapacity"/>
+      <configSetting altId="p01_2.gpio_mode.gpio_mode_peripheral" configurationId="p01_2.gpio_mode"/>
+      <configSetting altId="p01_2.sr.sr.fast" configurationId="p01_2.sr"/>
+      <configSetting altId="p01_3.ether_eth2.eth2_txd2" configurationId="p01_3"/>
+      <configSetting altId="p01_3.gpio_speed.gpio_speed_high" configurationId="p01_3.gpio_drivecapacity"/>
+      <configSetting altId="p01_3.gpio_mode.gpio_mode_peripheral" configurationId="p01_3.gpio_mode"/>
+      <configSetting altId="p01_3.sr.sr.fast" configurationId="p01_3.sr"/>
+      <configSetting altId="p01_4.ether_eth2.eth2_txd1" configurationId="p01_4"/>
+      <configSetting altId="p01_4.gpio_speed.gpio_speed_high" configurationId="p01_4.gpio_drivecapacity"/>
+      <configSetting altId="p01_4.gpio_mode.gpio_mode_peripheral" configurationId="p01_4.gpio_mode"/>
+      <configSetting altId="p01_4.sr.sr.fast" configurationId="p01_4.sr"/>
+      <configSetting altId="p01_5.ether_eth2.eth2_txd0" configurationId="p01_5"/>
+      <configSetting altId="p01_5.gpio_speed.gpio_speed_high" configurationId="p01_5.gpio_drivecapacity"/>
+      <configSetting altId="p01_5.gpio_mode.gpio_mode_peripheral" configurationId="p01_5.gpio_mode"/>
+      <configSetting altId="p01_5.sr.sr.fast" configurationId="p01_5.sr"/>
+      <configSetting altId="p01_7.canfd0.canrx0" configurationId="p01_7"/>
+      <configSetting altId="p01_7.gpio_speed.gpio_speed_middle" configurationId="p01_7.gpio_drivecapacity"/>
+      <configSetting altId="p01_7.gpio_mode.gpio_mode_peripheral" configurationId="p01_7.gpio_mode"/>
+      <configSetting altId="p02_2.canfd0.cantx0" configurationId="p02_2"/>
+      <configSetting altId="p02_2.gpio_speed.gpio_speed_middle" configurationId="p02_2.gpio_drivecapacity"/>
+      <configSetting altId="p02_2.gpio_mode.gpio_mode_peripheral" configurationId="p02_2.gpio_mode"/>
+      <configSetting altId="p02_4.jtag_fslash_swd.tdo" configurationId="p02_4"/>
+      <configSetting altId="p02_4.gpio_speed.gpio_speed_high" configurationId="p02_4.gpio_drivecapacity"/>
+      <configSetting altId="p02_4.gpio_mode.gpio_mode_peripheral" configurationId="p02_4.gpio_mode"/>
+      <configSetting altId="p02_4.sr.sr.fast" configurationId="p02_4.sr"/>
+      <configSetting altId="p02_5.jtag_fslash_swd.tdi" configurationId="p02_5"/>
+      <configSetting altId="p02_5.gpio_mode.gpio_mode_peripheral" configurationId="p02_5.gpio_mode"/>
+      <configSetting altId="p02_6.jtag_fslash_swd.tms_swdio" configurationId="p02_6"/>
+      <configSetting altId="p02_6.gpio_speed.gpio_speed_high" configurationId="p02_6.gpio_drivecapacity"/>
+      <configSetting altId="p02_6.gpio_mode.gpio_mode_peripheral" configurationId="p02_6.gpio_mode"/>
+      <configSetting altId="p02_6.sr.sr.fast" configurationId="p02_6.sr"/>
+      <configSetting altId="p02_7.jtag_fslash_swd.tck_swclk" configurationId="p02_7"/>
+      <configSetting altId="p02_7.gpio_mode.gpio_mode_peripheral" configurationId="p02_7.gpio_mode"/>
+      <configSetting altId="p03_0.output.low" configurationId="p03_0"/>
+      <configSetting altId="p03_0.gpio_mode.gpio_mode_out.low" configurationId="p03_0.gpio_mode"/>
+      <configSetting altId="p04_1.output.low" configurationId="p04_1"/>
+      <configSetting altId="p04_1.gpio_mode.gpio_mode_out.low" configurationId="p04_1.gpio_mode"/>
+      <configSetting altId="p04_4.output.low" configurationId="p04_4"/>
+      <configSetting altId="p04_4.gpio_mode.gpio_mode_out.low" configurationId="p04_4.gpio_mode"/>
+      <configSetting altId="p05_0.output.low" configurationId="p05_0"/>
+      <configSetting altId="p05_0.gpio_mode.gpio_mode_out.low" configurationId="p05_0.gpio_mode"/>
+      <configSetting altId="p05_2.iic1.iic_scl1" configurationId="p05_2"/>
+      <configSetting altId="p05_2.gpio_speed.gpio_speed_middle" configurationId="p05_2.gpio_drivecapacity"/>
+      <configSetting altId="p05_2.gpio_mode.gpio_mode_peripheral" configurationId="p05_2.gpio_mode"/>
+      <configSetting altId="p05_3.iic1.iic_sda1" configurationId="p05_3"/>
+      <configSetting altId="p05_3.gpio_speed.gpio_speed_middle" configurationId="p05_3.gpio_drivecapacity"/>
+      <configSetting altId="p05_3.gpio_mode.gpio_mode_peripheral" configurationId="p05_3.gpio_mode"/>
+      <configSetting altId="p05_4.input" configurationId="p05_4"/>
+      <configSetting altId="p05_4.gpio_mode.gpio_mode_in" configurationId="p05_4.gpio_mode"/>
+      <configSetting altId="p05_5.ether_ethsw.ethsw_phylink1" configurationId="p05_5"/>
+      <configSetting altId="p05_5.gpio_mode.gpio_mode_peripheral" configurationId="p05_5.gpio_mode"/>
+      <configSetting altId="p05_7.ether_eth1.eth1_txd2" configurationId="p05_7"/>
+      <configSetting altId="p05_7.gpio_speed.gpio_speed_high" configurationId="p05_7.gpio_drivecapacity"/>
+      <configSetting altId="p05_7.gpio_mode.gpio_mode_peripheral" configurationId="p05_7.gpio_mode"/>
+      <configSetting altId="p05_7.sr.sr.fast" configurationId="p05_7.sr"/>
+      <configSetting altId="p06_0.ether_eth1.eth1_txd3" configurationId="p06_0"/>
+      <configSetting altId="p06_0.gpio_speed.gpio_speed_high" configurationId="p06_0.gpio_drivecapacity"/>
+      <configSetting altId="p06_0.gpio_mode.gpio_mode_peripheral" configurationId="p06_0.gpio_mode"/>
+      <configSetting altId="p06_0.sr.sr.fast" configurationId="p06_0.sr"/>
+      <configSetting altId="p06_1.ether_eth1.eth1_refclk" configurationId="p06_1"/>
+      <configSetting altId="p06_1.gpio_mode.gpio_mode_peripheral" configurationId="p06_1.gpio_mode"/>
+      <configSetting altId="p06_2.ether_eth1.eth1_txd1" configurationId="p06_2"/>
+      <configSetting altId="p06_2.gpio_speed.gpio_speed_high" configurationId="p06_2.gpio_drivecapacity"/>
+      <configSetting altId="p06_2.gpio_mode.gpio_mode_peripheral" configurationId="p06_2.gpio_mode"/>
+      <configSetting altId="p06_2.sr.sr.fast" configurationId="p06_2.sr"/>
+      <configSetting altId="p06_3.ether_eth1.eth1_txd0" configurationId="p06_3"/>
+      <configSetting altId="p06_3.gpio_speed.gpio_speed_high" configurationId="p06_3.gpio_drivecapacity"/>
+      <configSetting altId="p06_3.gpio_mode.gpio_mode_peripheral" configurationId="p06_3.gpio_mode"/>
+      <configSetting altId="p06_3.sr.sr.fast" configurationId="p06_3.sr"/>
+      <configSetting altId="p06_4.ether_eth1.eth1_txclk_txc" configurationId="p06_4"/>
+      <configSetting altId="p06_4.gpio_speed.gpio_speed_high" configurationId="p06_4.gpio_drivecapacity"/>
+      <configSetting altId="p06_4.gpio_mode.gpio_mode_peripheral" configurationId="p06_4.gpio_mode"/>
+      <configSetting altId="p06_4.sr.sr.fast" configurationId="p06_4.sr"/>
+      <configSetting altId="p06_5.ether_eth1.eth1_txen_txctl" configurationId="p06_5"/>
+      <configSetting altId="p06_5.gpio_mode.gpio_mode_peripheral" configurationId="p06_5.gpio_mode"/>
+      <configSetting altId="p06_6.ether_eth1.eth1_rxd0" configurationId="p06_6"/>
+      <configSetting altId="p06_6.gpio_mode.gpio_mode_peripheral" configurationId="p06_6.gpio_mode"/>
+      <configSetting altId="p06_7.ether_eth1.eth1_rxd1" configurationId="p06_7"/>
+      <configSetting altId="p06_7.gpio_mode.gpio_mode_peripheral" configurationId="p06_7.gpio_mode"/>
+      <configSetting altId="p07_0.ether_eth1.eth1_rxd2" configurationId="p07_0"/>
+      <configSetting altId="p07_0.gpio_mode.gpio_mode_peripheral" configurationId="p07_0.gpio_mode"/>
+      <configSetting altId="p07_1.ether_eth1.eth1_rxd3" configurationId="p07_1"/>
+      <configSetting altId="p07_1.gpio_mode.gpio_mode_peripheral" configurationId="p07_1.gpio_mode"/>
+      <configSetting altId="p07_2.ether_eth1.eth1_rxdv_crsdv_rxctl" configurationId="p07_2"/>
+      <configSetting altId="p07_2.gpio_mode.gpio_mode_peripheral" configurationId="p07_2.gpio_mode"/>
+      <configSetting altId="p07_3.ether_eth1.eth1_rxclk_ref_clk_rxc" configurationId="p07_3"/>
+      <configSetting altId="p07_3.gpio_mode.gpio_mode_peripheral" configurationId="p07_3.gpio_mode"/>
+      <configSetting altId="p07_4.usb_hs.usb_vbusin" configurationId="p07_4"/>
+      <configSetting altId="p07_4.gpio_mode.gpio_mode_peripheral" configurationId="p07_4.gpio_mode"/>
+      <configSetting altId="p08_4.ether_eth0.eth0_rxd3" configurationId="p08_4"/>
+      <configSetting altId="p08_4.gpio_mode.gpio_mode_peripheral" configurationId="p08_4.gpio_mode"/>
+      <configSetting altId="p08_5.ether_eth0.eth0_rxdv_crsdv_rxctl" configurationId="p08_5"/>
+      <configSetting altId="p08_5.gpio_mode.gpio_mode_peripheral" configurationId="p08_5.gpio_mode"/>
+      <configSetting altId="p08_6.ether_eth0.eth0_rxclk_ref_clk_rxc" configurationId="p08_6"/>
+      <configSetting altId="p08_6.gpio_mode.gpio_mode_peripheral" configurationId="p08_6.gpio_mode"/>
+      <configSetting altId="p08_7.ether_gmac.gmac_mdc" configurationId="p08_7"/>
+      <configSetting altId="p08_7.gpio_mode.gpio_mode_peripheral" configurationId="p08_7.gpio_mode"/>
+      <configSetting altId="p09_0.ether_gmac.gmac_mdio" configurationId="p09_0"/>
+      <configSetting altId="p09_0.gpio_mode.gpio_mode_peripheral" configurationId="p09_0.gpio_mode"/>
+      <configSetting altId="p09_1.ether_eth0.eth0_refclk" configurationId="p09_1"/>
+      <configSetting altId="p09_1.gpio_mode.gpio_mode_peripheral" configurationId="p09_1.gpio_mode"/>
+      <configSetting altId="p09_3.ether_eth0.eth0_txd3" configurationId="p09_3"/>
+      <configSetting altId="p09_3.gpio_speed.gpio_speed_high" configurationId="p09_3.gpio_drivecapacity"/>
+      <configSetting altId="p09_3.gpio_mode.gpio_mode_peripheral" configurationId="p09_3.gpio_mode"/>
+      <configSetting altId="p09_3.sr.sr.fast" configurationId="p09_3.sr"/>
+      <configSetting altId="p09_4.ether_eth0.eth0_txd2" configurationId="p09_4"/>
+      <configSetting altId="p09_4.gpio_speed.gpio_speed_high" configurationId="p09_4.gpio_drivecapacity"/>
+      <configSetting altId="p09_4.gpio_mode.gpio_mode_peripheral" configurationId="p09_4.gpio_mode"/>
+      <configSetting altId="p09_4.sr.sr.fast" configurationId="p09_4.sr"/>
+      <configSetting altId="p09_5.ether_eth0.eth0_txd1" configurationId="p09_5"/>
+      <configSetting altId="p09_5.gpio_speed.gpio_speed_high" configurationId="p09_5.gpio_drivecapacity"/>
+      <configSetting altId="p09_5.gpio_mode.gpio_mode_peripheral" configurationId="p09_5.gpio_mode"/>
+      <configSetting altId="p09_5.sr.sr.fast" configurationId="p09_5.sr"/>
+      <configSetting altId="p09_6.ether_eth0.eth0_txd0" configurationId="p09_6"/>
+      <configSetting altId="p09_6.gpio_speed.gpio_speed_high" configurationId="p09_6.gpio_drivecapacity"/>
+      <configSetting altId="p09_6.gpio_mode.gpio_mode_peripheral" configurationId="p09_6.gpio_mode"/>
+      <configSetting altId="p09_6.sr.sr.fast" configurationId="p09_6.sr"/>
+      <configSetting altId="p09_7.ether_eth0.eth0_txclk_txc" configurationId="p09_7"/>
+      <configSetting altId="p09_7.gpio_speed.gpio_speed_high" configurationId="p09_7.gpio_drivecapacity"/>
+      <configSetting altId="p09_7.gpio_mode.gpio_mode_peripheral" configurationId="p09_7.gpio_mode"/>
+      <configSetting altId="p09_7.sr.sr.fast" configurationId="p09_7.sr"/>
+      <configSetting altId="p10_0.ether_eth0.eth0_txen_txctl" configurationId="p10_0"/>
+      <configSetting altId="p10_0.gpio_mode.gpio_mode_peripheral" configurationId="p10_0.gpio_mode"/>
+      <configSetting altId="p10_1.ether_eth0.eth0_rxd0" configurationId="p10_1"/>
+      <configSetting altId="p10_1.gpio_mode.gpio_mode_peripheral" configurationId="p10_1.gpio_mode"/>
+      <configSetting altId="p10_2.ether_eth0.eth0_rxd1" configurationId="p10_2"/>
+      <configSetting altId="p10_2.gpio_mode.gpio_mode_peripheral" configurationId="p10_2.gpio_mode"/>
+      <configSetting altId="p10_3.ether_eth0.eth0_rxd2" configurationId="p10_3"/>
+      <configSetting altId="p10_3.gpio_mode.gpio_mode_peripheral" configurationId="p10_3.gpio_mode"/>
+      <configSetting altId="p10_4.ether_ethsw.ethsw_phylink0" configurationId="p10_4"/>
+      <configSetting altId="p10_4.gpio_mode.gpio_mode_peripheral" configurationId="p10_4.gpio_mode"/>
+      <configSetting altId="p13_2.iic0.iic_scl0" configurationId="p13_2"/>
+      <configSetting altId="p13_2.gpio_speed.gpio_speed_middle" configurationId="p13_2.gpio_drivecapacity"/>
+      <configSetting altId="p13_2.gpio_mode.gpio_mode_peripheral" configurationId="p13_2.gpio_mode"/>
+      <configSetting altId="p13_3.iic0.iic_sda0" configurationId="p13_3"/>
+      <configSetting altId="p13_3.gpio_speed.gpio_speed_middle" configurationId="p13_3.gpio_drivecapacity"/>
+      <configSetting altId="p13_3.gpio_mode.gpio_mode_peripheral" configurationId="p13_3.gpio_mode"/>
+      <configSetting altId="p13_4.output.low" configurationId="p13_4"/>
+      <configSetting altId="p13_4.gpio_mode.gpio_mode_out.low" configurationId="p13_4.gpio_mode"/>
+      <configSetting altId="p13_5.input" configurationId="p13_5"/>
+      <configSetting altId="p13_5.gpio_mode.gpio_mode_in" configurationId="p13_5.gpio_mode"/>
+      <configSetting altId="p13_6.input" configurationId="p13_6"/>
+      <configSetting altId="p13_6.gpio_mode.gpio_mode_in" configurationId="p13_6.gpio_mode"/>
+      <configSetting altId="p13_7.input" configurationId="p13_7"/>
+      <configSetting altId="p13_7.gpio_mode.gpio_mode_in" configurationId="p13_7.gpio_mode"/>
+      <configSetting altId="p14_0.output.low" configurationId="p14_0"/>
+      <configSetting altId="p14_0.gpio_mode.gpio_mode_out.low" configurationId="p14_0.gpio_mode"/>
+      <configSetting altId="p14_1.output.low" configurationId="p14_1"/>
+      <configSetting altId="p14_1.gpio_mode.gpio_mode_out.low" configurationId="p14_1.gpio_mode"/>
+      <configSetting altId="p14_2.xspi0.xspi0_ecs0_hash" configurationId="p14_2"/>
+      <configSetting altId="p14_2.gpio_mode.gpio_mode_peripheral" configurationId="p14_2.gpio_mode"/>
+      <configSetting altId="p14_3.output.low" configurationId="p14_3"/>
+      <configSetting altId="p14_3.gpio_mode.gpio_mode_out.low" configurationId="p14_3.gpio_mode"/>
+      <configSetting altId="p14_4.xspi0.xspi0_ds" configurationId="p14_4"/>
+      <configSetting altId="p14_4.gpio_speed.gpio_speed_high" configurationId="p14_4.gpio_drivecapacity"/>
+      <configSetting altId="p14_4.gpio_mode.gpio_mode_peripheral" configurationId="p14_4.gpio_mode"/>
+      <configSetting altId="p14_4.sr.sr.fast" configurationId="p14_4.sr"/>
+      <configSetting altId="p14_5.xspi0.xspi0_ckn" configurationId="p14_5"/>
+      <configSetting altId="p14_5.gpio_speed.gpio_speed_high" configurationId="p14_5.gpio_drivecapacity"/>
+      <configSetting altId="p14_5.gpio_mode.gpio_mode_peripheral" configurationId="p14_5.gpio_mode"/>
+      <configSetting altId="p14_5.sr.sr.fast" configurationId="p14_5.sr"/>
+      <configSetting altId="p14_6.xspi0.xspi0_ckp" configurationId="p14_6"/>
+      <configSetting altId="p14_6.gpio_speed.gpio_speed_high" configurationId="p14_6.gpio_drivecapacity"/>
+      <configSetting altId="p14_6.gpio_mode.gpio_mode_peripheral" configurationId="p14_6.gpio_mode"/>
+      <configSetting altId="p14_6.sr.sr.fast" configurationId="p14_6.sr"/>
+      <configSetting altId="p14_7.xspi0.xspi0_io0" configurationId="p14_7"/>
+      <configSetting altId="p14_7.gpio_speed.gpio_speed_high" configurationId="p14_7.gpio_drivecapacity"/>
+      <configSetting altId="p14_7.gpio_mode.gpio_mode_peripheral" configurationId="p14_7.gpio_mode"/>
+      <configSetting altId="p14_7.sr.sr.fast" configurationId="p14_7.sr"/>
+      <configSetting altId="p15_0.xspi0.xspi0_io1" configurationId="p15_0"/>
+      <configSetting altId="p15_0.gpio_speed.gpio_speed_high" configurationId="p15_0.gpio_drivecapacity"/>
+      <configSetting altId="p15_0.gpio_mode.gpio_mode_peripheral" configurationId="p15_0.gpio_mode"/>
+      <configSetting altId="p15_0.sr.sr.fast" configurationId="p15_0.sr"/>
+      <configSetting altId="p15_1.xspi0.xspi0_io2" configurationId="p15_1"/>
+      <configSetting altId="p15_1.gpio_speed.gpio_speed_high" configurationId="p15_1.gpio_drivecapacity"/>
+      <configSetting altId="p15_1.gpio_mode.gpio_mode_peripheral" configurationId="p15_1.gpio_mode"/>
+      <configSetting altId="p15_1.sr.sr.fast" configurationId="p15_1.sr"/>
+      <configSetting altId="p15_2.xspi0.xspi0_io3" configurationId="p15_2"/>
+      <configSetting altId="p15_2.gpio_speed.gpio_speed_high" configurationId="p15_2.gpio_drivecapacity"/>
+      <configSetting altId="p15_2.gpio_mode.gpio_mode_peripheral" configurationId="p15_2.gpio_mode"/>
+      <configSetting altId="p15_2.sr.sr.fast" configurationId="p15_2.sr"/>
+      <configSetting altId="p15_3.xspi0.xspi0_io4" configurationId="p15_3"/>
+      <configSetting altId="p15_3.gpio_speed.gpio_speed_high" configurationId="p15_3.gpio_drivecapacity"/>
+      <configSetting altId="p15_3.gpio_mode.gpio_mode_peripheral" configurationId="p15_3.gpio_mode"/>
+      <configSetting altId="p15_3.sr.sr.fast" configurationId="p15_3.sr"/>
+      <configSetting altId="p15_4.xspi0.xspi0_io5" configurationId="p15_4"/>
+      <configSetting altId="p15_4.gpio_speed.gpio_speed_high" configurationId="p15_4.gpio_drivecapacity"/>
+      <configSetting altId="p15_4.gpio_mode.gpio_mode_peripheral" configurationId="p15_4.gpio_mode"/>
+      <configSetting altId="p15_4.sr.sr.fast" configurationId="p15_4.sr"/>
+      <configSetting altId="p15_5.xspi0.xspi0_io6" configurationId="p15_5"/>
+      <configSetting altId="p15_5.gpio_speed.gpio_speed_high" configurationId="p15_5.gpio_drivecapacity"/>
+      <configSetting altId="p15_5.gpio_mode.gpio_mode_peripheral" configurationId="p15_5.gpio_mode"/>
+      <configSetting altId="p15_5.sr.sr.fast" configurationId="p15_5.sr"/>
+      <configSetting altId="p15_6.xspi0.xspi0_io7" configurationId="p15_6"/>
+      <configSetting altId="p15_6.gpio_speed.gpio_speed_high" configurationId="p15_6.gpio_drivecapacity"/>
+      <configSetting altId="p15_6.gpio_mode.gpio_mode_peripheral" configurationId="p15_6.gpio_mode"/>
+      <configSetting altId="p15_6.sr.sr.fast" configurationId="p15_6.sr"/>
+      <configSetting altId="p15_7.xspi0.xspi0_cs0_hash" configurationId="p15_7"/>
+      <configSetting altId="p15_7.gpio_speed.gpio_speed_high" configurationId="p15_7.gpio_drivecapacity"/>
+      <configSetting altId="p15_7.gpio_mode.gpio_mode_peripheral" configurationId="p15_7.gpio_mode"/>
+      <configSetting altId="p15_7.sr.sr.fast" configurationId="p15_7.sr"/>
+      <configSetting altId="p16_0.xspi0.xspi0_cs1_hash" configurationId="p16_0"/>
+      <configSetting altId="p16_0.gpio_speed.gpio_speed_high" configurationId="p16_0.gpio_drivecapacity"/>
+      <configSetting altId="p16_0.gpio_mode.gpio_mode_peripheral" configurationId="p16_0.gpio_mode"/>
+      <configSetting altId="p16_0.sr.sr.fast" configurationId="p16_0.sr"/>
+      <configSetting altId="p16_1.xspi0.xspi0_reset0_hash" configurationId="p16_1"/>
+      <configSetting altId="p16_1.gpio_mode.gpio_mode_peripheral" configurationId="p16_1.gpio_mode"/>
+      <configSetting altId="p16_3.input" configurationId="p16_3"/>
+      <configSetting altId="p16_3.gpio_mode.gpio_mode_in" configurationId="p16_3.gpio_mode"/>
+      <configSetting altId="p16_5.sci0.txd_mosi0" configurationId="p16_5"/>
+      <configSetting altId="p16_5.gpio_speed.gpio_speed_high" configurationId="p16_5.gpio_drivecapacity"/>
+      <configSetting altId="p16_5.gpio_mode.gpio_mode_peripheral" configurationId="p16_5.gpio_mode"/>
+      <configSetting altId="p16_5.sr.sr.fast" configurationId="p16_5.sr"/>
+      <configSetting altId="p16_6.sci0.rxd_miso0" configurationId="p16_6"/>
+      <configSetting altId="p16_6.gpio_speed.gpio_speed_high" configurationId="p16_6.gpio_drivecapacity"/>
+      <configSetting altId="p16_6.gpio_mode.gpio_mode_peripheral" configurationId="p16_6.gpio_mode"/>
+      <configSetting altId="p16_6.sr.sr.fast" configurationId="p16_6.sr"/>
+      <configSetting altId="p17_3.output.low" configurationId="p17_3"/>
+      <configSetting altId="p17_3.gpio_mode.gpio_mode_out.low" configurationId="p17_3.gpio_mode"/>
+      <configSetting altId="p17_5.usb_hs.usb_ovrcur" configurationId="p17_5"/>
+      <configSetting altId="p17_5.gpio_mode.gpio_mode_peripheral" configurationId="p17_5.gpio_mode"/>
+      <configSetting altId="p17_7.sci3.rxd_miso3" configurationId="p17_7"/>
+      <configSetting altId="p17_7.gpio_speed.gpio_speed_high" configurationId="p17_7.gpio_drivecapacity"/>
+      <configSetting altId="p17_7.gpio_mode.gpio_mode_peripheral" configurationId="p17_7.gpio_mode"/>
+      <configSetting altId="p17_7.sr.sr.fast" configurationId="p17_7.sr"/>
+      <configSetting altId="p18_0.sci3.txd_mosi3" configurationId="p18_0"/>
+      <configSetting altId="p18_0.gpio_speed.gpio_speed_high" configurationId="p18_0.gpio_drivecapacity"/>
+      <configSetting altId="p18_0.gpio_mode.gpio_mode_peripheral" configurationId="p18_0.gpio_mode"/>
+      <configSetting altId="p18_0.sr.sr.fast" configurationId="p18_0.sr"/>
+      <configSetting altId="p18_2.output.low" configurationId="p18_2"/>
+      <configSetting altId="p18_2.gpio_mode.gpio_mode_out.low" configurationId="p18_2.gpio_mode"/>
+      <configSetting altId="p18_4.spi2.spi_rspck2" configurationId="p18_4"/>
+      <configSetting altId="p18_4.gpio_speed.gpio_speed_high" configurationId="p18_4.gpio_drivecapacity"/>
+      <configSetting altId="p18_4.gpio_mode.gpio_mode_peripheral" configurationId="p18_4.gpio_mode"/>
+      <configSetting altId="p18_4.sr.sr.fast" configurationId="p18_4.sr"/>
+      <configSetting altId="p18_5.spi2.spi_mosi2" configurationId="p18_5"/>
+      <configSetting altId="p18_5.gpio_speed.gpio_speed_high" configurationId="p18_5.gpio_drivecapacity"/>
+      <configSetting altId="p18_5.gpio_mode.gpio_mode_peripheral" configurationId="p18_5.gpio_mode"/>
+      <configSetting altId="p18_5.sr.sr.fast" configurationId="p18_5.sr"/>
+      <configSetting altId="p18_6.spi2.spi_miso2" configurationId="p18_6"/>
+      <configSetting altId="p18_6.gpio_speed.gpio_speed_high" configurationId="p18_6.gpio_drivecapacity"/>
+      <configSetting altId="p18_6.gpio_mode.gpio_mode_peripheral" configurationId="p18_6.gpio_mode"/>
+      <configSetting altId="p18_6.sr.sr.fast" configurationId="p18_6.sr"/>
+      <configSetting altId="p19_0.usb_hs.usb_vbusen" configurationId="p19_0"/>
+      <configSetting altId="p19_0.gpio_mode.gpio_mode_peripheral" configurationId="p19_0.gpio_mode"/>
+      <configSetting altId="p20_1.output.low" configurationId="p20_1"/>
+      <configSetting altId="p20_1.gpio_mode.gpio_mode_out.low" configurationId="p20_1.gpio_mode"/>
+      <configSetting altId="p20_2.output.low" configurationId="p20_2"/>
+      <configSetting altId="p20_2.gpio_mode.gpio_mode_out.low" configurationId="p20_2.gpio_mode"/>
+      <configSetting altId="p20_3.output.low" configurationId="p20_3"/>
+      <configSetting altId="p20_3.gpio_mode.gpio_mode_out.low" configurationId="p20_3.gpio_mode"/>
+      <configSetting altId="p20_4.output.low" configurationId="p20_4"/>
+      <configSetting altId="p20_4.gpio_mode.gpio_mode_out.low" configurationId="p20_4.gpio_mode"/>
+      <configSetting altId="p21_1.spi2.spi_ssl20" configurationId="p21_1"/>
+      <configSetting altId="p21_1.gpio_speed.gpio_speed_high" configurationId="p21_1.gpio_drivecapacity"/>
+      <configSetting altId="p21_1.gpio_mode.gpio_mode_peripheral" configurationId="p21_1.gpio_mode"/>
+      <configSetting altId="p21_1.sr.sr.fast" configurationId="p21_1.sr"/>
+      <configSetting altId="p22_1.output.low" configurationId="p22_1"/>
+      <configSetting altId="p22_1.gpio_mode.gpio_mode_out.low" configurationId="p22_1.gpio_mode"/>
+      <configSetting altId="p22_3.output.low" configurationId="p22_3"/>
+      <configSetting altId="p22_3.gpio_mode.gpio_mode_out.low" configurationId="p22_3.gpio_mode"/>
+      <configSetting altId="p23_7.ether_eth2.eth2_rxd0" configurationId="p23_7"/>
+      <configSetting altId="p23_7.gpio_mode.gpio_mode_peripheral" configurationId="p23_7.gpio_mode"/>
+      <configSetting altId="p24_0.ether_eth2.eth2_rxd1" configurationId="p24_0"/>
+      <configSetting altId="p24_0.gpio_mode.gpio_mode_peripheral" configurationId="p24_0.gpio_mode"/>
+      <configSetting altId="p24_1.ether_eth2.eth2_rxclk_ref_clk_rxc" configurationId="p24_1"/>
+      <configSetting altId="p24_1.gpio_mode.gpio_mode_peripheral" configurationId="p24_1.gpio_mode"/>
+      <configSetting altId="p24_2.ether_eth2.eth2_rxd2" configurationId="p24_2"/>
+      <configSetting altId="p24_2.gpio_mode.gpio_mode_peripheral" configurationId="p24_2.gpio_mode"/>
+      <configSetting altId="sci0.mode.asynchronousmode.free" configurationId="sci0.mode"/>
+      <configSetting altId="sci0.rxd_miso0.p16_6" configurationId="sci0.rxd_miso0"/>
+      <configSetting altId="sci0.txd_mosi0.p16_5" configurationId="sci0.txd_mosi0"/>
+      <configSetting altId="sci3.mode.asynchronousmode.free" configurationId="sci3.mode"/>
+      <configSetting altId="sci3.rxd_miso3.p17_7" configurationId="sci3.rxd_miso3"/>
+      <configSetting altId="sci3.txd_mosi3.p18_0" configurationId="sci3.txd_mosi3"/>
+      <configSetting altId="spi2.mode.enabled.free" configurationId="spi2.mode"/>
+      <configSetting altId="spi2.spi_miso2.p18_6" configurationId="spi2.spi_miso2"/>
+      <configSetting altId="spi2.spi_mosi2.p18_5" configurationId="spi2.spi_mosi2"/>
+      <configSetting altId="spi2.spi_rspck2.p18_4" configurationId="spi2.spi_rspck2"/>
+      <configSetting altId="spi2.spi_ssl20.p21_1" configurationId="spi2.spi_ssl20"/>
+      <configSetting altId="usb_hs.mode.enabeld.free" configurationId="usb_hs.mode"/>
+      <configSetting altId="usb_hs.usb_ovrcur.p17_5" configurationId="usb_hs.usb_ovrcur"/>
+      <configSetting altId="usb_hs.usb_vbusen.p19_0" configurationId="usb_hs.usb_vbusen"/>
+      <configSetting altId="usb_hs.usb_vbusin.p07_4" configurationId="usb_hs.usb_vbusin"/>
+      <configSetting altId="xspi0.mode.octa_40_1.8v_41.free" configurationId="xspi0.mode"/>
+      <configSetting altId="xspi0.xspi0_ckn.p14_5" configurationId="xspi0.xspi0_ckn"/>
+      <configSetting altId="xspi0.xspi0_ckp.p14_6" configurationId="xspi0.xspi0_ckp"/>
+      <configSetting altId="xspi0.xspi0_cs0_hash.p15_7" configurationId="xspi0.xspi0_cs0_hash"/>
+      <configSetting altId="xspi0.xspi0_cs1_hash.p16_0" configurationId="xspi0.xspi0_cs1_hash"/>
+      <configSetting altId="xspi0.xspi0_ds.p14_4" configurationId="xspi0.xspi0_ds"/>
+      <configSetting altId="xspi0.xspi0_ecs0_hash.p14_2" configurationId="xspi0.xspi0_ecs0_hash"/>
+      <configSetting altId="xspi0.xspi0_io0.p14_7" configurationId="xspi0.xspi0_io0"/>
+      <configSetting altId="xspi0.xspi0_io1.p15_0" configurationId="xspi0.xspi0_io1"/>
+      <configSetting altId="xspi0.xspi0_io2.p15_1" configurationId="xspi0.xspi0_io2"/>
+      <configSetting altId="xspi0.xspi0_io3.p15_2" configurationId="xspi0.xspi0_io3"/>
+      <configSetting altId="xspi0.xspi0_io4.p15_3" configurationId="xspi0.xspi0_io4"/>
+      <configSetting altId="xspi0.xspi0_io5.p15_4" configurationId="xspi0.xspi0_io5"/>
+      <configSetting altId="xspi0.xspi0_io6.p15_5" configurationId="xspi0.xspi0_io6"/>
+      <configSetting altId="xspi0.xspi0_io7.p15_6" configurationId="xspi0.xspi0_io7"/>
+      <configSetting altId="xspi0.xspi0_reset0_hash.p16_1" configurationId="xspi0.xspi0_reset0_hash"/>
+    </pincfg>
+    <pincfg active="false" name="R9A07G084M04GBG.pincfg" selected="false" symbol="">
+      <configSetting altId="jtag_fslash_swd.mode.jtag.free" configurationId="jtag_fslash_swd.mode"/>
+      <configSetting altId="jtag_fslash_swd.tck_swclk.p02_7" configurationId="jtag_fslash_swd.tck_swclk"/>
+      <configSetting altId="jtag_fslash_swd.tdi.p02_5" configurationId="jtag_fslash_swd.tdi"/>
+      <configSetting altId="jtag_fslash_swd.tdo.p02_4" configurationId="jtag_fslash_swd.tdo"/>
+      <configSetting altId="jtag_fslash_swd.tms_swdio.p02_6" configurationId="jtag_fslash_swd.tms_swdio"/>
+      <configSetting altId="p02_4.jtag_fslash_swd.tdo" configurationId="p02_4"/>
+      <configSetting altId="p02_4.gpio_speed.gpio_speed_high" configurationId="p02_4.gpio_drivecapacity"/>
+      <configSetting altId="p02_4.gpio_mode.gpio_mode_peripheral" configurationId="p02_4.gpio_mode"/>
+      <configSetting altId="p02_4.sr.sr.fast" configurationId="p02_4.sr"/>
+      <configSetting altId="p02_5.jtag_fslash_swd.tdi" configurationId="p02_5"/>
+      <configSetting altId="p02_5.gpio_mode.gpio_mode_peripheral" configurationId="p02_5.gpio_mode"/>
+      <configSetting altId="p02_6.jtag_fslash_swd.tms_swdio" configurationId="p02_6"/>
+      <configSetting altId="p02_6.gpio_speed.gpio_speed_high" configurationId="p02_6.gpio_drivecapacity"/>
+      <configSetting altId="p02_6.gpio_mode.gpio_mode_peripheral" configurationId="p02_6.gpio_mode"/>
+      <configSetting altId="p02_6.sr.sr.fast" configurationId="p02_6.sr"/>
+      <configSetting altId="p02_7.jtag_fslash_swd.tck_swclk" configurationId="p02_7"/>
+      <configSetting altId="p02_7.gpio_mode.gpio_mode_peripheral" configurationId="p02_7.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
diff --git a/projects/etherkit_ethercat_cherryecat/envsetup.sh b/projects/etherkit_ethercat_cherryecat/envsetup.sh
new file mode 100644
index 00000000..cb56dd85
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/envsetup.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+
+export RTT_ROOT=${PWD}/rt-thread
+export ENV_ROOT=${HOME}/.env
+export BSP_ROOT=${PWD}
+export RTT_CC='gcc'
+export RTT_EXEC_PATH='/usr/bin'
+
+rtt_dir='../../rt-thread'
+lib_dir='../../libraries'
+
+if [ ! -L "rt-thread" ]; then
+	if [ -d $rtt_dir ]; then
+		ln -s $rtt_dir ./rt-thread
+	fi
+fi
+
+if [ ! -L "libraries" ]; then
+	if [ -d $lib_dir ]; then
+		ln -s $lib_dir ./libraries
+	fi
+fi
diff --git a/projects/etherkit_ethercat_cherryecat/figures/cherryecat1.png b/projects/etherkit_ethercat_cherryecat/figures/cherryecat1.png
new file mode 100644
index 0000000000000000000000000000000000000000..931a2052dc125a68511b08e2a6c144f519939c27
GIT binary patch
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Cf6Z(F

literal 0
HcmV?d00001

diff --git a/projects/etherkit_ethercat_cherryecat/memory_regions.ld b/projects/etherkit_ethercat_cherryecat/memory_regions.ld
new file mode 100644
index 00000000..e95adf7c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/memory_regions.ld
@@ -0,0 +1,40 @@
+
+            /* generated memory regions file - do not edit */
+                                ATCM_START  = 0x00000000;
+                    ATCM_LENGTH = 0x20000;
+                    BTCM_START  = 0x00100000;
+                    BTCM_LENGTH = 0x20000;
+                    SYSTEM_RAM_START  = 0x10000000;
+                    SYSTEM_RAM_LENGTH = 0x180000;
+                    SYSTEM_RAM_MIRROR_START  = 0x30000000;
+                    SYSTEM_RAM_MIRROR_LENGTH = 0x180000;
+                    xSPI0_CS0_SPACE_MIRROR_START  = 0x40000000;
+                    xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+                    xSPI0_CS1_SPACE_MIRROR_START  = 0x44000000;
+                    xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000;
+                    xSPI1_CS0_SPACE_MIRROR_START  = 0x48000000;
+                    xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+                    CS0_SPACE_MIRROR_START  = 0x50000000;
+                    CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+                    CS2_SPACE_MIRROR_START  = 0x54000000;
+                    CS2_SPACE_MIRROR_LENGTH = 0x4000000;
+                    CS3_SPACE_MIRROR_START  = 0x58000000;
+                    CS3_SPACE_MIRROR_LENGTH = 0x4000000;
+                    CS5_SPACE_MIRROR_START  = 0x5C000000;
+                    CS5_SPACE_MIRROR_LENGTH = 0x4000000;
+                    xSPI0_CS0_SPACE_START  = 0x60000000;
+                    xSPI0_CS0_SPACE_LENGTH = 0x4000000;
+                    xSPI0_CS1_SPACE_START  = 0x64000000;
+                    xSPI0_CS1_SPACE_LENGTH = 0x4000000;
+                    xSPI1_CS0_SPACE_START  = 0x68000000;
+                    xSPI1_CS0_SPACE_LENGTH = 0x4000000;
+                    CS0_SPACE_START  = 0x70000000;
+                    CS0_SPACE_LENGTH = 0x4000000;
+                    CS2_SPACE_START  = 0x74000000;
+                    CS2_SPACE_LENGTH = 0x4000000;
+                    CS3_SPACE_START  = 0x78000000;
+                    CS3_SPACE_LENGTH = 0x4000000;
+                    CS5_SPACE_START  = 0x7C000000;
+                    CS5_SPACE_LENGTH = 0x4000000;
+                    RAM_NS_BUFFER_LENGTH = 0x6100;
+                CR52_0 = 1;
diff --git a/projects/etherkit_ethercat_cherryecat/mklinks.bat b/projects/etherkit_ethercat_cherryecat/mklinks.bat
new file mode 100644
index 00000000..24046fcd
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/mklinks.bat
@@ -0,0 +1,6 @@
+@echo off
+%1 mshta vbscript:CreateObject("Shell.Application").ShellExecute("cmd.exe","/c %~s0 ::","","runas",1)(window.close)&&exit
+cd /d "%~dp0"
+@echo on
+mklink /D rt-thread ..\..\rt-thread
+mklink /D libraries ..\..\libraries
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/mklinks.sh b/projects/etherkit_ethercat_cherryecat/mklinks.sh
new file mode 100644
index 00000000..04fe15d6
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/mklinks.sh
@@ -0,0 +1,3 @@
+#!/bin/bash
+ln -s ../../rt-thread  rt-thread
+ln -s ../../libraries libraries
diff --git a/projects/etherkit_ethercat_cherryecat/ozone_scons.jdebug b/projects/etherkit_ethercat_cherryecat/ozone_scons.jdebug
new file mode 100644
index 00000000..0e4132ec
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/ozone_scons.jdebug
@@ -0,0 +1,361 @@
+/*********************************************************************
+*                 (c) SEGGER Microcontroller GmbH                    *
+*                      The Embedded Experts                          *
+*                         www.segger.com                             *
+**********************************************************************
+
+File          : ozone_scons.jdebug
+Created       : 2 Dec 2024 10:53
+Ozone Version : V3.38b
+*/
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  //
+  // Dialog-generated settings
+  //
+  Project.AddPathSubstitute ("./", "$(ProjectDir)");
+  Project.AddPathSubstitute ("./", "$(ProjectDir)");
+  Project.SetDevice ("R9A07G084M04");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-R52_AArch32.svd");
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-R52_AArch32.svd");
+  //
+  // User settings
+  //
+  File.Open ("$(ProjectDir)/rtthread.elf");
+}
+
+/*********************************************************************
+*
+*       OnStartupComplete
+*
+* Function description
+*   Called when program execution has reached/passed
+*   the startup completion point. Optional.
+*
+**********************************************************************
+*/
+//void OnStartupComplete (void) {
+//}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging an application in RAM on a Cortex-M target device.
+*
+**********************************************************************
+*/
+void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//  //
+//  // Set up initial stack pointer
+//  //
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//  }
+//  //
+//  // Set up entry point PC
+//  //
+//  PC = Elf.GetEntryPointPC();
+//
+//  if (PC != 0xFFFFFFFF) {
+//    Target.SetReg("PC", PC);
+//  } else if (VectorTableAddr != 0xFFFFFFFF) {
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  } else {
+//    Util.Error("Project file error: failed to set entry point PC", 1);
+//  }
+}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+**
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetResume
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetResume (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotLoad
+*
+* Function description
+*   Called upon loading a snapshot. Optional.
+*
+* Additional information
+*   This function is used to restore the target state in cases
+*   where values cannot simply be written to the target.
+*   Typical use: GPIO clock needs to be enabled, before
+*   GPIO is configured.
+*
+**********************************************************************
+*/
+//void OnSnapshotLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotSave
+*
+* Function description
+*   Called upon saving a snapshot. Optional.
+*
+* Additional information
+*   This function is usually used to save values of the target
+*   state which can either not be trivially read,
+*   or need to be restored in a specific way or order.
+*   Typically use: Memory Mapped Registers,
+*   such as PLL and GPIO configuration.
+*
+**********************************************************************
+*/
+//void OnSnapshotSave (void) {
+//}
+
+/*********************************************************************
+*
+*       OnError
+*
+* Function description
+*   Called when an error ocurred. Optional.
+*
+**********************************************************************
+*/
+//void OnError (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterProjectLoad
+*
+* Function description
+*   After Project load routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterProjectLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       _SetupTarget
+*
+* Function description
+*   Setup the target.
+*   Called by AfterTargetReset() and AfterTargetDownload().
+*
+*   Auto-generated function. May be overridden by Ozone.
+*
+**********************************************************************
+*/
+void _SetupTarget(void) {
+  //
+  // this function is intentionally empty because both inital PC and
+  // initial SP were chosen not to be set
+  //
+
+    U64 PC;
+     U32 cpsr;
+  int ElfClass;
+
+  ElfClass = Elf.GetFileClass();
+  //
+  // Set up initial PC
+  //
+  PC = Elf.GetExprValue("system_init");
+  if (PC != 0xFFFFFFFF) {
+    if (ElfClass == ELF_CLASS_64) {
+      //
+      // AArch64
+      //
+      Target.SetReg("PC", PC);
+    } else if (ElfClass == ELF_CLASS_32) {
+      //
+      // AArch32
+      //
+      Exec.Reset();
+      Target.SetReg("CPSR", 0x01da);
+      Target.SetReg("R15 (PC)", PC);
+    } else {
+      Util.Error("Project script error: failed to set initial PC", 1);
+    }
+  } else {
+    Util.Error("Project script error: failed to set initial PC", 1);
+  }
+}
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.clang-format b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.clang-format
new file mode 100644
index 00000000..336989de
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.clang-format
@@ -0,0 +1,171 @@
+# clang-format configuration file. Intended for clang-format >= 11.0
+#
+# For more information, see:
+#
+#   https://clang.llvm.org/docs/ClangFormat.html
+#   https://clang.llvm.org/docs/ClangFormatStyleOptions.html
+#
+---
+# 语言: None, Cpp, Java, JavaScript, ObjC, Proto, TableGen, TextProto
+Language:	Cpp
+# BasedOnStyle:	LLVM
+# 访问说明符(public、private等)的偏移
+AccessModifierOffset:	-4
+# 开括号(开圆括号、开尖括号、开方括号)后的对齐: Align, DontAlign, AlwaysBreak(总是在开括号后换行)
+AlignAfterOpenBracket:	Align
+# 连续赋值时，对齐所有等号
+AlignConsecutiveAssignments:	false
+# 对齐位域
+AlignConsecutiveBitFields: true
+# 连续声明时，对齐所有声明的变量名
+AlignConsecutiveDeclarations:	false
+# 连续宏时，进行对齐
+AlignConsecutiveMacros: true
+# 左对齐逃脱换行(使用反斜杠换行)的反斜杠
+AlignEscapedNewlines:	Left
+# 水平对齐二元和三元表达式的操作数
+AlignOperands:	true
+# 对齐连续的尾随的注释
+AlignTrailingComments:	true
+# 允许函数声明的所有参数在放在下一行
+AllowAllParametersOfDeclarationOnNextLine:	false
+# 允许短的块放在同一行
+AllowShortBlocksOnASingleLine:	false
+# 允许短的case标签放在同一行
+AllowShortCaseLabelsOnASingleLine:	false
+# 允许短的函数放在同一行: None, InlineOnly(定义在类中), Empty(空函数), Inline(定义在类中，空函数), All
+AllowShortFunctionsOnASingleLine:	None
+# 允许短的if语句保持在同一行
+AllowShortIfStatementsOnASingleLine:	false
+# 允许短的循环保持在同一行
+AllowShortLoopsOnASingleLine:	false
+# 总是在定义返回类型后换行(deprecated)
+AlwaysBreakAfterDefinitionReturnType:	None
+# 总是在返回类型后换行: None, All, TopLevel(顶级函数，不包括在类中的函数),
+#  AllDefinitions(所有的定义，不包括声明), TopLevelDefinitions(所有的顶级函数的定义)
+AlwaysBreakAfterReturnType:	None
+# 总是在多行string字面量前换行
+AlwaysBreakBeforeMultilineStrings:	false
+# 总是在template声明后换行
+AlwaysBreakTemplateDeclarations:	false
+# false表示函数实参要么都在同一行，要么都各自一行
+BinPackArguments:	true
+# false表示所有形参要么都在同一行，要么都各自一行
+BinPackParameters:	true
+# 大括号换行，只有当BreakBeforeBraces设置为Custom时才有效
+BraceWrapping:
+    AfterClass: false
+    AfterControlStatement: false
+    AfterEnum: false
+    AfterFunction: true
+    AfterNamespace: false
+    AfterObjCDeclaration: false
+    AfterStruct: false
+    AfterUnion: false
+    AfterExternBlock: false # Unknown to clang-format-5.0
+    BeforeCatch: false
+    BeforeElse: false
+    IndentBraces: false
+    SplitEmptyFunction: true # Unknown to clang-format-4.0
+    SplitEmptyRecord: true # Unknown to clang-format-4.0
+    SplitEmptyNamespace: true # Unknown to clang-format-4.0
+# 在二元运算符前换行: None(在操作符后换行), NonAssignment(在非赋值的操作符前换行), All(在操作符前换行)
+BreakBeforeBinaryOperators:	None
+BreakBeforeBraces:	Custom
+#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0
+# 在三元运算符前换行
+BreakBeforeTernaryOperators:	false
+# 在构造函数的初始化列表的逗号前换行
+BreakConstructorInitializersBeforeComma:	false
+BreakAfterJavaFieldAnnotations: false
+BreakStringLiterals: false
+# 每行字符的限制，0表示没有限制
+ColumnLimit:	0
+# 描述具有特殊意义的注释的正则表达式，它不应该被分割为多行或以其它方式改变
+CommentPragmas:	'^ IWYU pragma:'
+CompactNamespaces: false # Unknown to clang-format-4.0
+# 构造函数的初始化列表要么都在同一行，要么都各自一行
+ConstructorInitializerAllOnOneLineOrOnePerLine:	false
+# 构造函数的初始化列表的缩进宽度
+ConstructorInitializerIndentWidth:	4
+# 延续的行的缩进宽度
+ContinuationIndentWidth:	4
+# 去除C++11的列表初始化的大括号{后和}前的空格
+Cpp11BracedListStyle:	false
+# 继承最常用的指针和引用的对齐方式
+DerivePointerAlignment:	false
+# 关闭格式化
+DisableFormat:	false
+ForEachMacros:
+  - 'SHELL_EXPORT_CMD'
+
+# 自动检测函数的调用和定义是否被格式为每行一个参数(Experimental)
+ExperimentalAutoDetectBinPacking:	false
+# 缩进case标签
+IndentCaseLabels:	true
+# 缩进宽度
+IndentWidth:	4
+# 函数返回类型换行时，缩进函数声明或函数定义的函数名
+IndentWrappedFunctionNames:	false
+# 保留在块开始处的空行
+KeepEmptyLinesAtTheStartOfBlocks:	false
+# 开始一个块的宏的正则表达式
+MacroBlockBegin:	''
+# 结束一个块的宏的正则表达式
+MacroBlockEnd:	''
+# 连续空行的最大数量
+MaxEmptyLinesToKeep:	1
+# 命名空间的缩进: None, Inner(缩进嵌套的命名空间中的内容), All
+NamespaceIndentation:	None
+# 使用ObjC块时缩进宽度
+ObjCBlockIndentWidth:	4
+# 在ObjC的@property后添加一个空格
+ObjCSpaceAfterProperty:	false
+# 在ObjC的protocol列表前添加一个空格
+ObjCSpaceBeforeProtocolList:	true
+# 在call(后对函数调用换行的penalty
+PenaltyBreakBeforeFirstCallParameter:	30
+# 在一个注释中引入换行的penalty
+PenaltyBreakComment:	10
+# 第一次在<<前换行的penalty
+PenaltyBreakFirstLessLess:	0
+# 在一个字符串字面量中引入换行的penalty
+PenaltyBreakString:	10
+# 对于每个在行字符数限制之外的字符的penalty
+PenaltyExcessCharacter:	100
+# 将函数的返回类型放到它自己的行的penalty
+PenaltyReturnTypeOnItsOwnLine:	60
+# 指针和引用的对齐: Left, Right, Middle
+PointerAlignment:	Right
+# 允许重新排版注释
+ReflowComments:	false
+# 允许排序#include
+SortIncludes:	false
+# 在C风格类型转换后添加空格
+SpaceAfterCStyleCast:	false
+# 在赋值运算符之前添加空格
+SpaceBeforeAssignmentOperators:	true
+# 开圆括号之前添加一个空格: Never, ControlStatements, Always
+SpaceBeforeParens:	ControlStatements
+# 在空的圆括号中添加空格
+SpaceInEmptyParentheses:	false
+# 在尾随的评论前添加的空格数(只适用于//)
+SpacesBeforeTrailingComments:	1
+# 在尖括号的<后和>前添加空格
+SpacesInAngles:	false
+# 在容器(ObjC和JavaScript的数组和字典等)字面量中添加空格
+SpacesInContainerLiterals:	false
+# 在C风格类型转换的括号中添加空格
+SpacesInCStyleCastParentheses:	false
+# 在圆括号的(后和)前添加空格
+SpacesInParentheses:	false
+# 在方括号的[后和]前添加空格，lamda表达式和未指明大小的数组的声明不受影响
+SpacesInSquareBrackets:	false
+# 标准: Cpp03, Cpp11, Auto
+Standard:	Cpp03
+# tab宽度
+TabWidth:	4
+# 使用tab字符: Never, ForIndentation, ForContinuationAndIndentation, Always
+UseTab:	Never
+...
+
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitattributes b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitattributes
new file mode 100644
index 00000000..74d8c6b2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitattributes
@@ -0,0 +1,47 @@
+*.c linguist-language=C
+*.C linguist-language=C
+*.h linguist-language=C
+*.H linguist-language=C
+
+* text=auto
+
+*.S text
+*.asm text
+*.c text
+*.cc text
+*.cpp text
+*.cxx text
+*.h text
+*.htm text
+*.html text
+*.in text
+*.ld text
+*.m4 text
+*.mak text
+*.mk text
+*.py text
+*.rb text
+*.s text
+*.sct text
+*.sh text
+*.txt text
+*.xml text
+SConscript text
+Makefile text
+AUTHORS text
+COPYING text
+
+*.LZO -text
+*.Opt -text
+*.Uv2 -text
+*.ewp -text
+*.eww -text
+*.vcproj -text
+*.bat -text
+*.dos -text
+*.icf -text
+*.inf -text
+*.ini -text
+*.sct -text
+*.xsd -text
+Jamfile -text
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.github/workflows/build_demo.yml b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.github/workflows/build_demo.yml
new file mode 100644
index 00000000..9d6fbc28
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.github/workflows/build_demo.yml
@@ -0,0 +1,36 @@
+name: Build Demo
+
+on:
+  push:
+    branches: [ master ]
+  pull_request:
+    branches: [ master ]
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v3
+
+      - name: Install dependencies
+        run: sudo apt-get update && sudo apt-get install -y cmake ninja-build
+
+      - name: Download hpm_sdk
+        run: |
+          cd ~
+          git clone https://github.com/hpmicro/hpm_sdk.git
+
+      - name: Download RISC-V toolchain
+        run: |
+          cd ~
+          wget https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2023.10.18/rv32imac_zicsr_zifencei_multilib_b_ext-linux.tar.gz
+          tar -xzf rv32imac_zicsr_zifencei_multilib_b_ext-linux.tar.gz
+
+      - name: Build demo
+        run: |
+          cd demo/hpmicro
+          export HPM_SDK_BASE=~/hpm_sdk
+          export GNURISCV_TOOLCHAIN_PATH=~/rv32imac_zicsr_zifencei_multilib_b_ext-linux
+          export HPM_SDK_TOOLCHAIN_VARIANT=
+          cmake -S . -B build -GNinja -DBOARD=hpm6800evk -DHPM_BUILD_TYPE=ram -DCMAKE_BUILD_TYPE=debug;cmake --build build
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitignore b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitignore
new file mode 100644
index 00000000..cf458423
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitignore
@@ -0,0 +1,23 @@
+.vscode
+build
+**/Drivers/**
+**/MDK-ARM/DebugConfig/**
+**/MDK-ARM/RTE/**
+**/obj/**
+**/RET/**
+**/Listings/**
+**/Objects/**
+*.map
+*.o
+*.d
+*.htm
+*.dep
+*.lnp
+*.iex
+*.lst
+*.axf
+*.crf
+*.hex
+*.Bak
+*.uvguix.*
+*.scvd
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.readthedocs.yaml b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.readthedocs.yaml
new file mode 100644
index 00000000..ed14f4de
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.readthedocs.yaml
@@ -0,0 +1,35 @@
+# Read the Docs configuration file for Sphinx projects
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+# Required
+version: 2
+
+# Set the OS, Python version and other tools you might need
+build:
+  os: ubuntu-22.04
+  tools:
+    python: "3.11"
+    # You can also specify other tool versions:
+    # nodejs: "20"
+    # rust: "1.70"
+    # golang: "1.20"
+
+# Build documentation in the "docs/" directory with Sphinx
+sphinx:
+  configuration: docs/source/conf.py
+  # You can configure Sphinx to use a different builder, for instance use the dirhtml builder for simpler URLs
+  # builder: "dirhtml"
+  # Fail on all warnings to avoid broken references
+  # fail_on_warning: true
+
+# Optionally build your docs in additional formats such as PDF and ePub
+# formats:
+#    - pdf
+#    - epub
+
+# Optional but recommended, declare the Python requirements required
+# to build your documentation
+# See https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html
+python:
+   install:
+   - requirements: docs/requirements.txt
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/CMakeLists.txt b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/CMakeLists.txt
new file mode 100644
index 00000000..bfcc5abc
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/CMakeLists.txt
@@ -0,0 +1,39 @@
+if(CONFIG_CHERRYECAT)
+
+    list(APPEND cherryec_incs
+        ${CMAKE_CURRENT_LIST_DIR}/include
+    )
+
+    list(APPEND cherryec_srcs
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_cmd.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_coe.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_common.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_datagram.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_foe.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_mailbox.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_master.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_netdev.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_perf.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_sii.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_slave.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/ec_timestamp.c
+        ${CMAKE_CURRENT_LIST_DIR}/src/phy/chry_phy.c
+    )
+
+    if(DEFINED CONFIG_CHERRYECAT_OSAL)
+        if("${CONFIG_CHERRYECAT_OSAL}" STREQUAL "freertos")
+            list(APPEND cherryec_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/ec_osal_freertos.c)
+        elseif("${CONFIG_CHERRYECAT_OSAL}" STREQUAL "rtthread")
+            list(APPEND cherryec_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/ec_osal_rtthread.c)
+        elseif("${CONFIG_CHERRYECAT_OSAL}" STREQUAL "threadx")
+            list(APPEND cherryec_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/ec_osal_threadx.c)
+        endif()
+    endif()
+
+    if(HPM_SDK_BASE)
+        list(APPEND cherryec_srcs port/netdev_hpmicro.c)
+        sdk_inc(${cherryec_incs})
+        sdk_src(${cherryec_srcs})
+    endif()
+
+endif()
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/LICENSE b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/LICENSE
new file mode 100644
index 00000000..261eeb9e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/LICENSE
@@ -0,0 +1,201 @@
+                                 Apache License
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+
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diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README.md b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README.md
new file mode 100644
index 00000000..0dd6330d
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README.md
@@ -0,0 +1,111 @@
+**English | [简体中文](README_zh.md)**
+
+<h1 align="center" style="margin: 30px 0 30px; font-weight: bold;">CherryECAT</h1>
+<p align="center">
+	<a href="https://github.com/cherry-embedded/CherryECAT/releases"><img src="https://img.shields.io/github/release/cherry-embedded/CherryECAT.svg"></a>
+	<a href="https://github.com/cherry-embedded/CherryECAT/blob/master/LICENSE"><img src="https://img.shields.io/github/license/cherry-embedded/CherryECAT.svg?style=flat-square"></a>
+	<a href="https://github.com/cherry-embedded/CherryECAT/actions/workflows/build_demo.yml"><img src="https://github.com/cherry-embedded/CherryECAT/actions/workflows/build_demo.yml/badge.svg"> </a>
+</p>
+
+CherryECAT is a tiny and beautiful, high real-time and low-jitter EtherCAT master stack, specially designed for MCUs running with RTOS.
+
+## Feature
+
+- ~ 4K ram, ~32K flash(24K + 8K shell cmd + debug log)
+- Asynchronous queue-based transfer (one transfer can carry multiple datagrams)
+- Zero-copy technology: directly use enet tx/rx buffer to fill and parse ethercat data
+- Support hot-plugging
+	- Automatic scanning bus
+	- Automatic updating slave information when the topology changes
+- Support automatic monitoring slave status
+- Support distributed clocks
+- Support CANopen over EtherCAT(COE)
+- Support File over EtherCAT(FOE)
+- Support Ethernet over EtherCAT(EOE)
+- Support Slave SII access
+- Support Slave register access
+- Support multi master
+- Support backup redundancy
+- Minimum PDO cyclic time < 40 us (depends on master and slave hardware)
+- Support multi cyclic time(every slave can use different proportional cyclic time)
+- Support ethercat cmd with shell, ref to IgH
+
+## Hardware limitations
+
+- **Master**
+	- CPU (cache > 16K, memcpy speed > 100MB/s)
+	- ENET must support descriptor dma and iperf with lwip > 90 Mbps
+	- Code must run in ram, ignore if no dc
+	- Must support High-Precision Timer (jitter < 1us)
+	- Must support High-Precision timestamp (ARM DWT/RISC-V MCYCLE)
+	- Must support long long print
+
+- **Slave**
+	- Must support COE
+	- Must support sdo complete access
+	- SII must have sync manager information
+
+## Shell cmd
+
+![ethercat](docs/assets/ethercat.png)
+![ethercat](docs/assets/ethercat1.png)
+![ethercat](docs/assets/ethercat2.png)
+![ethercat](docs/assets/ethercat3.png)
+![ethercat](docs/assets/ethercat4.png)
+![ethercat](docs/assets/ethercat5.png)
+![ethercat](docs/assets/ethercat6.png)
+![ethercat](docs/assets/ethercat7.png)
+![ethercat](docs/assets/ethercat8.png)
+
+## Tool
+
+- esi_parser
+
+Use **esi_parser.py** to generate slave eeprom information and download eeprom to slave.
+
+```
+python ./esi_parser.py ECAT_CIA402_ESI.xml eeprom.bin eeprom.h
+
+Parsing XML file: ECAT_CIA402_ESI.xml
+Parsed XML: Vendor=0x0048504D, Product=0x00000003
+Device Name: ECAT_CIA402
+Mailbox RX: 0x1000(128)
+Mailbox TX: 0x1080(128)
+Generating EEPROM data...
+✓ Successfully converted 'ECAT_CIA402_ESI.xml' to 'eeprom.bin'
+✓ Generated 2048 bytes of EEPROM data
+✓ Vendor ID: 0x0048504D
+✓ Product Code: 0x00000003
+✓ Revision: 0x00000001
+✓ Device Name: ECAT_CIA402
+✓ Generated C header file: eeprom.h
+```
+
+- eni_parser
+
+Use **eni_parser.py** to generate CherryECAT slave sync config.
+
+```
+python ./eni_parser.py ECAT_CIA402_ENI.xml sync_config.h
+
+Parsing ENI file: ECAT_CIA402_ENI.xml
+Generating C code...
+✓ Successfully converted 'ECAT_CIA402_ENI.xml' to 'sync_config.h'
+✓ Generated C code for 1 slave(s)
+✓ Slave 1:
+  - RxPDO 0x1602: 3 entries
+  - TxPDO 0x1A02: 3 entries
+```
+
+## Support Boards
+
+- HPM6750EVK2/HPM6800EVK/**HPM5E00EVK**(hybrid internal)
+- RT-Thread RZN2L-EtherKit
+
+## Contact
+
+QQ group: 563650597
+
+## License
+
+FOE,EOE and Backup redundancy features are available for commercial charge; other are free to use
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README_zh.md b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README_zh.md
new file mode 100644
index 00000000..d606147f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README_zh.md
@@ -0,0 +1,111 @@
+**[English](README.md) | 简体中文**
+
+<h1 align="center" style="margin: 30px 0 30px; font-weight: bold;">CherryECAT</h1>
+<p align="center">
+	<a href="https://github.com/cherry-embedded/CherryECAT/releases"><img src="https://img.shields.io/github/release/cherry-embedded/CherryECAT.svg"></a>
+	<a href="https://github.com/cherry-embedded/CherryECAT/blob/master/LICENSE"><img src="https://img.shields.io/github/license/cherry-embedded/CherryECAT.svg?style=flat-square"></a>
+	<a href="https://github.com/cherry-embedded/CherryECAT/actions/workflows/build_demo.yml"><img src="https://github.com/cherry-embedded/CherryECAT/actions/workflows/build_demo.yml/badge.svg"> </a>
+</p>
+
+CherryECAT 是一个小而美的、高实时性、低抖动的 EtherCAT 主机协议栈，专为跑在 RTOS 下的 MCU 设计。
+
+## 特性
+
+- ~ 4K ram，~32K flash（24K + 8K shell cmd + debug log）
+- 异步队列式传输（一次传输可以携带多个 datagram）
+- 零拷贝技术：直接使用 enet tx/rx buffer 填充和解析 ethercat 数据
+- 支持热插拔
+	- 自动扫描总线
+	- 拓扑结构发生变化时自动更新 Slave 信息
+- 支持自动监控 Slave 状态
+- 支持分布式时钟
+- 支持 CANopen over EtherCAT (COE)
+- 支持 File over EtherCAT(FOE)
+- 支持 Ethernet over EtherCAT(EOE)
+- 支持 Slave SII 读写
+- 支持 Slave 寄存器读写
+- 支持多主站
+- 支持备份冗余
+- 最小 PDO cyclic time < 40 us (实际数值受主站硬件和从站硬件影响)
+- 支持多周期（每个从站可以使用不同的成比例的周期）
+- 支持 ethercat 命令行交互，参考 IgH
+
+## 硬件限制
+
+- 主站
+	- CPU (cache > 16K, memcpy speed > 100MB/s)
+	- 以太网必须支持 descriptor dma 并且 iperf with lwip > 90 Mbps
+	- 代码必须跑在 ram 上，如果不使用 DC 同步则忽视
+	- 必须支持高精度定时器（抖动小于 1us）
+	- 必须支持高精度时间戳 (ARM DWT/RISC-V MCYCLE)
+	- 必须支持 64 位打印
+
+- 从站
+	- 必须支持 COE
+	- 必须支持 sdo complete access
+	- SII 必须携带 sync manager 信息
+
+## Shell 命令
+
+![ethercat](docs/assets/ethercat.png)
+![ethercat](docs/assets/ethercat1.png)
+![ethercat](docs/assets/ethercat2.png)
+![ethercat](docs/assets/ethercat3.png)
+![ethercat](docs/assets/ethercat4.png)
+![ethercat](docs/assets/ethercat5.png)
+![ethercat](docs/assets/ethercat6.png)
+![ethercat](docs/assets/ethercat7.png)
+![ethercat](docs/assets/ethercat8.png)
+
+## 工具
+
+- esi_parser
+
+使用 **esi_parser.py** 生成从站 eeprom 信息用于烧录从站
+
+```
+python ./esi_parser.py ECAT_CIA402_ESI.xml eeprom.bin eeprom.h
+
+Parsing XML file: ECAT_CIA402_ESI.xml
+Parsed XML: Vendor=0x0048504D, Product=0x00000003
+Device Name: ECAT_CIA402
+Mailbox RX: 0x1000(128)
+Mailbox TX: 0x1080(128)
+Generating EEPROM data...
+✓ Successfully converted 'ECAT_CIA402_ESI.xml' to 'eeprom.bin'
+✓ Generated 2048 bytes of EEPROM data
+✓ Vendor ID: 0x0048504D
+✓ Product Code: 0x00000003
+✓ Revision: 0x00000001
+✓ Device Name: ECAT_CIA402
+✓ Generated C header file: eeprom.h
+```
+
+- eni_parser
+
+使用 **eni_parser.py** 生成 CherryECAT slave sync 配置
+
+```
+python ./eni_parser.py ECAT_CIA402_ENI.xml sync_config.h
+
+Parsing ENI file: ECAT_CIA402_ENI.xml
+Generating C code...
+✓ Successfully converted 'ECAT_CIA402_ENI.xml' to 'sync_config.h'
+✓ Generated C code for 1 slave(s)
+✓ Slave 1:
+  - RxPDO 0x1602: 3 entries
+  - TxPDO 0x1A02: 3 entries
+```
+
+## 支持的开发板
+
+- HPM6750EVK2/HPM6800EVK/**HPM5E00EVK**(hybrid internal)
+- RT-Thread RZN2L-EtherKit
+
+## 联系
+
+QQ group: 563650597
+
+## License
+
+FOE，EOE，备份冗余功能为商用收费，其余功能免费商用
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/SConscript b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/SConscript
new file mode 100644
index 00000000..0427c62f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/SConscript
@@ -0,0 +1,35 @@
+from building import *
+
+cwd = GetCurrentDir()
+path = [cwd + '/include']
+src = []
+
+LIBS    = []
+LIBPATH = []
+CPPDEFINES = []
+
+src += Glob('src/ec_cmd.c')
+src += Glob('src/ec_coe.c')
+src += Glob('src/ec_common.c')
+src += Glob('src/ec_datagram.c')
+src += Glob('src/ec_foe.c')
+src += Glob('src/ec_mailbox.c')
+src += Glob('src/ec_master.c')
+src += Glob('src/ec_netdev.c')
+src += Glob('src/ec_perf.c')
+src += Glob('src/ec_sii.c')
+src += Glob('src/ec_slave.c')
+src += Glob('src/ec_timestamp.c')
+src += Glob('src/phy/chry_phy.c')
+src += Glob('osal/ec_osal_rtthread.c')
+
+if GetDepend(['PKG_CHERRYECAT_NETDEV_HPMICRO']):
+    src += Glob('port/netdev_hpmicro.c')
+
+if GetDepend(['PKG_CHERRYECAT_NETDEV_RENESAS']):
+    src += Glob('port/netdev_renesas.c')
+
+group = DefineGroup('CherryECAT', src, depend = ['PKG_USING_CHERRYECAT'], LIBS = LIBS, LIBPATH=LIBPATH, CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
+
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/VERSION b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/VERSION
new file mode 100644
index 00000000..d57fdb9f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/VERSION
@@ -0,0 +1,5 @@
+VERSION_MAJOR = 0
+VERSION_MINOR = 1
+PATCHLEVEL = 0
+VERSION_TWEAK = 0
+EXTRAVERSION = 0
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/cherryec_config_template.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/cherryec_config_template.h
new file mode 100644
index 00000000..5af4f443
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/cherryec_config_template.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_CONFIG_H
+#define EC_CONFIG_H
+
+#define CONFIG_EC_PRINTF(...) printf(__VA_ARGS__)
+
+#ifndef CONFIG_EC_DBG_LEVEL
+#define CONFIG_EC_DBG_LEVEL EC_DBG_INFO
+#endif
+
+#ifndef CONFIG_EC_SLAVE_DBG_LEVEL
+#define CONFIG_EC_SLAVE_DBG_LEVEL EC_DBG_INFO
+#endif
+
+/* Enable print with color */
+#define CONFIG_EC_PRINTF_COLOR_ENABLE
+
+#define EC_FAST_CODE_SECTION
+
+#ifndef CONFIG_EC_MAX_NETDEVS
+#define CONFIG_EC_MAX_NETDEVS 1
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_PRIO
+#define CONFIG_EC_NONPERIOD_PRIO 0
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_STACKSIZE
+#define CONFIG_EC_NONPERIOD_STACKSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_INTERVAL_MS
+#define CONFIG_EC_NONPERIOD_INTERVAL_MS 10
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_WAITERS
+#define CONFIG_EC_NONPERIOD_WAITERS 20
+#endif
+
+#ifndef CONFIG_EC_SCAN_PRIO
+#define CONFIG_EC_SCAN_PRIO 1
+#endif
+
+#ifndef CONFIG_EC_SCAN_STACKSIZE
+#define CONFIG_EC_SCAN_STACKSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_SCAN_INTERVAL_MS
+#define CONFIG_EC_SCAN_INTERVAL_MS 100
+#endif
+
+#ifndef CONFIG_EC_PER_SM_MAX_PDOS
+#define CONFIG_EC_PER_SM_MAX_PDOS 8
+#endif
+
+#ifndef CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES
+#define CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES 8
+#endif
+
+#define CONFIG_EC_PERF_ENABLE
+#define CONFIG_EC_CMD_ENABLE
+// #define CONFIG_EC_TIMESTAMP_CUSTOM
+// #define CONFIG_EC_PHY_CUSTOM
+
+#ifndef CONFIG_EC_MAX_PDO_BUFSIZE
+#define CONFIG_EC_MAX_PDO_BUFSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_MAX_ENET_TXBUF_COUNT
+#define CONFIG_EC_MAX_ENET_TXBUF_COUNT 10
+#endif
+
+#ifndef CONFIG_EC_MAX_ENET_RXBUF_COUNT
+#define CONFIG_EC_MAX_ENET_RXBUF_COUNT 10
+#endif
+
+// #define CONFIG_EC_FOE
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/CMakeLists.txt b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/CMakeLists.txt
new file mode 100644
index 00000000..1d05040f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/CMakeLists.txt
@@ -0,0 +1,49 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+cmake_minimum_required(VERSION 3.13)
+
+set(HPM_SDK_LD_NO_NANO_SPECS 1)
+
+set(CONFIG_FREERTOS 1)
+# set(CONFIG_CHERRYRB 1)
+set(CONFIG_CHERRYSH 1)
+set(CONFIG_CHERRYSH_INTERFACE "uart")
+
+set(CONFIG_ENET_PHY 1)
+set(APP_USE_ENET_PORT_COUNT 1)
+#set(APP_USE_ENET_ITF_RGMII 1)
+#set(APP_USE_ENET_ITF_RMII 1)
+#set(APP_USE_ENET_PHY_DP83867 1)
+#set(APP_USE_ENET_PHY_RTL8211 1)
+#set(APP_USE_ENET_PHY_DP83848 1)
+set(APP_USE_ENET_PHY_RTL8201 1)
+
+set(CONFIG_CHERRYECAT 1)
+set(CONFIG_CHERRYECAT_OSAL "freertos")
+
+if(NOT (HPM_BUILD_TYPE STREQUAL "ram"))
+message(FATAL_ERROR "Only support ram build for demo")
+endif()
+
+#Set CONFIG_FREERTOS_TIMER_RESOURCE_GPTMR to use GPTMR as system's tick source
+#set(CONFIG_FREERTOS_TIMER_RESOURCE_GPTMR 1)
+
+find_package(hpm-sdk REQUIRED HINTS $ENV{HPM_SDK_BASE})
+
+project(cherryec)
+
+sdk_compile_definitions(-D__freertos_irq_stack_top=_stack)
+sdk_compile_definitions(-DCONFIG_FREERTOS=1)
+sdk_compile_definitions(-DUSE_NONVECTOR_MODE=1)
+sdk_compile_definitions(-DDISABLE_IRQ_PREEMPTIVE=1)
+
+sdk_compile_options("-O2")
+
+sdk_inc(.)
+sdk_inc(inc)
+sdk_app_src(main.c)
+
+add_subdirectory(../.. cherryec)
+generate_ses_project()
+
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/FreeRTOSConfig.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/FreeRTOSConfig.h
new file mode 100644
index 00000000..2a9cb035
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/FreeRTOSConfig.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2024 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ */
+
+#include "board.h"
+
+#if (portasmHAS_MTIME == 0)
+#define configMTIME_BASE_ADDRESS                (0)
+#define configMTIMECMP_BASE_ADDRESS             (0)
+#else
+#define configMTIME_BASE_ADDRESS                (HPM_MCHTMR_BASE)
+#define configMTIMECMP_BASE_ADDRESS             (HPM_MCHTMR_BASE + 8UL)
+#endif
+
+#define configUSE_PREEMPTION                    1
+#define configCPU_CLOCK_HZ                      ((uint32_t) 24000000)
+#define configTICK_RATE_HZ                      ((TickType_t) 1000)
+#define configMAX_PRIORITIES                    (32)
+#define configMINIMAL_STACK_SIZE                (256)
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 0
+#define configUSE_APPLICATION_TASK_TAG          0
+#define configGENERATE_RUN_TIME_STATS           0
+
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configUSE_MUTEXES                       1
+
+/* Memory allocation definitions. */
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+#define configTOTAL_HEAP_SIZE                   ((size_t) (64 * 1024))
+
+/* Hook function definitions. */
+#define configUSE_IDLE_HOOK                     0
+#define configUSE_TICK_HOOK                     0
+#define configCHECK_FOR_STACK_OVERFLOW          0
+#define configUSE_MALLOC_FAILED_HOOK            0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK      0
+
+/* Run time and task stats gathering definitions. */
+#define configGENERATE_RUN_TIME_STATS           0
+#define configUSE_TRACE_FACILITY                1
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+
+/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet                1
+#define INCLUDE_uxTaskPriorityGet               1
+#define INCLUDE_vTaskDelete                     1
+#define INCLUDE_vTaskCleanUpResources           1
+#define INCLUDE_vTaskSuspend                    1
+#define INCLUDE_vTaskDelayUntil                 1
+#define INCLUDE_vTaskDelay                      1
+#define INCLUDE_xTaskGetCurrentTaskHandle       1
+#define INCLUDE_xTimerPendFunctionCall          1
+#define INCLUDE_eTaskGetState                   1
+#define INCLUDE_xTaskAbortDelay                 1
+#define INCLUDE_xTaskGetHandle                  1
+#define INCLUDE_xSemaphoreGetMutexHolder        1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                   0
+#define configMAX_CO_ROUTINE_PRIORITIES         2
+
+/* Software timer definitions. */
+#define configUSE_TIMERS                        1
+#define configTIMER_TASK_PRIORITY               (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH                4
+#define configTIMER_TASK_STACK_DEPTH            (configMINIMAL_STACK_SIZE)
+
+/* Task priorities.*/
+#ifndef uartPRIMARY_PRIORITY
+    #define uartPRIMARY_PRIORITY                (configMAX_PRIORITIES - 3)
+#endif
+
+/* Normal assert() semantics without relying on the provision of an assert.h header file. */
+#define configASSERT(x) if ((x) == 0) { taskDISABLE_INTERRUPTS(); __asm volatile("ebreak"); for (;;); }
+
+/*
+ * The size of the global output buffer that is available for use when there
+ * are multiple command interpreters running at once (for example, one on a UART
+ * and one on TCP/IP).  This is done to prevent an output buffer being defined by
+ * each implementation - which would waste RAM.  In this case, there is only one
+ * command interpreter running.
+ */
+
+/*
+ * The buffer into which output generated by FreeRTOS+CLI is placed.  This must
+ * be at least big enough to contain the output of the task-stats command, as the
+ * example implementation does not include buffer overlow checking.
+ */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE        2096
+#define configINCLUDE_QUERY_HEAP_COMMAND         1
+
+/* This file is included from assembler files - make sure C code is not included in assembler files. */
+#ifndef __ASSEMBLER__
+    void vAssertCalled(const char *pcFile, unsigned long ulLine);
+    void vConfigureTickInterrupt(void);
+    void vClearTickInterrupt(void);
+    void vPreSleepProcessing(unsigned long uxExpectedIdleTime);
+    void vPostSleepProcessing(unsigned long uxExpectedIdleTime);
+#endif /* __ASSEMBLER__ */
+
+/****** Hardware/compiler specific settings. *******/
+/*
+ * The application must provide a function that configures a peripheral to
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
+ * in FreeRTOSConfig.h to call the function.
+ */
+#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
+#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt()
+
+/*
+ * The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros
+ * allow the application writer to add additional code before and after the MCU is
+ * placed into the low power state respectively.  The empty implementations
+ * provided in this demo can be extended to save even more power.
+ */
+#define configPRE_SLEEP_PROCESSING(uxExpectedIdleTime) vPreSleepProcessing(uxExpectedIdleTime);
+#define configPOST_SLEEP_PROCESSING(uxExpectedIdleTime) vPostSleepProcessing(uxExpectedIdleTime);
+
+
+/* Compiler specifics. */
+#define fabs(x) __builtin_fabs(x)
+
+/* Enable Hardware Stack Protection and Recording mechanism. */
+#define configHSP_ENABLE                       0
+
+/* Record the highest address of stack. */
+#if (configHSP_ENABLE == 1 && configRECORD_STACK_HIGH_ADDRESS != 1)
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#endif
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/cia402_def.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/cia402_def.h
new file mode 100644
index 00000000..0277b235
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/cia402_def.h
@@ -0,0 +1,136 @@
+#ifndef CIA402_DEF_H
+#define CIA402_DEF_H
+
+/**
+STRUCT_PACKED_START: Is defined before the typedef struct construct to pack the generic structures if necessary */
+#ifndef STRUCT_PACKED_START
+#define STRUCT_PACKED_START                       ATTR_PACKED
+#endif
+
+/**
+STRUCT_PACKED_END: Is defined after the typedef struct {} construct to pack the generic structures if necessary */
+#ifndef STRUCT_PACKED_END
+#define STRUCT_PACKED_END
+#endif
+
+/*---------------------------------------------
+-    ControlWord Commands (IEC61800_184e)
+-----------------------------------------------*/
+#define CONTROLWORD_COMMAND_SHUTDOWN                 0x0006 /**< \brief Shutdown command*/
+#define CONTROLWORD_COMMAND_SWITCHON                 0x0007 /**< \brief Switch on command*/
+#define CONTROLWORD_COMMAND_SWITCHON_ENABLEOPERATION 0x000F /**< \brief Switch on & Enable command*/
+#define CONTROLWORD_COMMAND_DISABLEVOLTAGE           0x0000 /**< \brief Disable voltage command*/
+#define CONTROLWORD_COMMAND_QUICKSTOP                0x0002 /**< \brief Quickstop command*/
+#define CONTROLWORD_COMMAND_DISABLEOPERATION         0x0007 /**< \brief Disable operation command*/
+#define CONTROLWORD_COMMAND_ENABLEOPERATION          0x000F /**< \brief Enable operation command*/
+#define CONTROLWORD_COMMAND_FAULTRESET               0x0080 /**< \brief Fault reset command*/
+
+/*---------------------------------------------
+-    StatusWord Masks and Flags
+-----------------------------------------------*/
+#define STATUSWORD_STATE_MASK                        0x006F /**< \brief State mask*/
+#define STATUSWORD_VOLTAGE_ENABLED                   0x0010 /**< \brief Indicate high voltage enabled*/
+#define STATUSWORD_WARNING                           0x0080 /**< \brief Warning active*/
+#define STATUSWORD_MANUFACTORSPECIFIC                0x0100 /**< \brief Manufacturer specific*/
+#define STATUSWORD_INTERNAL_LIMIT                    0x0800 /**< \brief Internal limit*/
+#define STATUSWORD_REMOTE                            0x0200 /**< \brief Set if the control word is processed*/
+#define STATUSWORD_TARGET_REACHED                    0x0400 /**< \brief Target reached*/
+#define STATUSWORD_INTERNALLIMITACTIVE               0x0800 /**< \brief Internal limit active*/
+#define STATUSWORD_DRIVE_FOLLOWS_COMMAND             0x1000 /**< \brief Drive follows command (used in cyclic synchronous modes)*/
+
+/*---------------------------------------------
+-    StatusWord
+-----------------------------------------------*/
+#define STATUSWORD_STATE_NOTREADYTOSWITCHON          0x0000 /**< \brief Not ready to switch on*/
+#define STATUSWORD_STATE_SWITCHEDONDISABLED          0x0040 /**< \brief Switched on but disabled*/
+#define STATUSWORD_STATE_READYTOSWITCHON             0x0021 /**< \brief Ready to switch on*/
+#define STATUSWORD_STATE_SWITCHEDON                  0x0023 /**< \brief Switched on*/
+#define STATUSWORD_STATE_OPERATIONENABLED            0x0027 /**< \brief Operation enabled*/
+#define STATUSWORD_STATE_QUICKSTOPACTIVE             0x0007 /**< \brief Quickstop active*/
+#define STATUSWORD_STATE_FAULTREACTIONACTIVE         0x000F /**< \brief Fault reaction active*/
+#define STATUSWORD_STATE_FAULT                       0x0008 /**< \brief Fault state*/
+
+/*---------------------------------------------
+-    CiA402 Modes of Operation (object 0x6060) (IEC61800_184e)
+-----------------------------------------------*/
+// -128 to -1 Manufacturer-specific operation modes
+#define NO_MODE                                      0 /**< \brief No mode*/
+#define PROFILE_POSITION_MODE                        1 /**< \brief Position Profile mode*/
+#define VELOCITY_MODE                                2 /**< \brief Velocity mode*/
+#define PROFILE_VELOCITY_MOCE                        3 /**< \brief Velocity Profile mode*/
+#define PROFILE_TORQUE_MODE                          4 /**< \brief Torque Profile mode*/
+//5 reserved
+#define HOMING_MODE                                  6  /**< \brief Homing mode*/
+#define INTERPOLATION_POSITION_MODE                  7  /**< \brief Interpolation Position mode*/
+#define CYCLIC_SYNC_POSITION_MODE                    8  /**< \brief Cyclic Synchronous Position mode*/
+#define CYCLIC_SYNC_VELOCITY_MODE                    9  /**< \brief Cyclic Synchronous Velocity mode*/
+#define CYCLIC_SYNC_TORQUE_MODE                      10 /**< \brief Cyclic Synchronous Torque mode*/
+//+11 to +127 reserved
+
+/**
+ * \addtogroup PDO Process Data Objects
+ * @{
+ */
+/** \brief Data structure to handle the process data transmitted via 0x1A00 (csp/csv TxPDO)*/
+typedef struct STRUCT_PACKED_START
+{
+    uint16_t ObjStatusWord; /**< \brief Status word (0x6041)*/
+    int32_t ObjPositionActualValue; /**< \brief Actual position (0x6064)*/
+    int32_t ObjVelocityActualValue; /**< \brief Actual velocity (0x606C)*/
+    int16_t ObjModesOfOperationDisplay; /**< \brief Current mode of operation (0x6061)*/
+}STRUCT_PACKED_END
+TCiA402PDO1A00;
+
+
+/** \brief Data structure to handle the process data transmitted via 0x1A01 (csp TxPDO)*/
+typedef struct STRUCT_PACKED_START
+{
+    uint16_t ObjStatusWord; /**< \brief Status word (0x6041)*/
+    int32_t ObjPositionActualValue; /**< \brief Actual position (0x6064)*/
+    uint16_t Padding16Bit; /**< \brief 16bit padding*/
+}STRUCT_PACKED_END
+TCiA402PDO1A01;
+
+
+/** \brief Data structure to handle the process data transmitted via 0x1A02 (csv TxPDO)*/
+typedef struct STRUCT_PACKED_START
+{
+    uint16_t ObjStatusWord; /**< \brief Status word (0x6041)*/
+    int32_t ObjPositionActualValue; /**< \brief Actual position (0x6064)*/
+    uint16_t Padding16Bit; /**< \brief 16bit padding*/
+}STRUCT_PACKED_END
+TCiA402PDO1A02;
+
+
+/** \brief Data structure to handle the process data transmitted via 0x1600 (csp/csv RxPDO)*/
+typedef struct STRUCT_PACKED_START
+{
+    uint16_t ObjControlWord; /**< \brief Control word (0x6040)*/
+    int32_t ObjTargetPosition; /**< \brief Target position (0x607A)*/
+    int32_t ObjTargetVelocity; /**< \brief Target velocity (0x60FF)*/
+    int16_t ObjModesOfOperation; /**< \brief Mode of operation (0x6060)*/
+}STRUCT_PACKED_END
+TCiA402PDO1600;
+
+
+/** \brief Data structure to handle the process data transmitted via 0x1601 (csp RxPDO)*/
+typedef struct STRUCT_PACKED_START
+{
+    uint16_t ObjControlWord; /**< \brief Control word (0x6040)*/
+    int32_t ObjTargetPosition; /**< \brief Target position (0x607A)*/
+    uint16_t Padding16Bit; /**< \brief 16bit padding*/
+}STRUCT_PACKED_END
+TCiA402PDO1601;
+
+
+/** \brief Data structure to handle the process data transmitted via 0x1602 (csv RxPDO)*/
+typedef struct STRUCT_PACKED_START
+{
+    uint16_t ObjControlWord; /**< \brief Control word (0x6040)*/
+    int32_t ObjTargetVelocity; /**< \brief Target velocity (0x60FF)*/
+    uint16_t Padding16Bit; /**< \brief 16bit padding*/
+}STRUCT_PACKED_END
+TCiA402PDO1602;
+/** @}*/
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/csh_config.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/csh_config.h
new file mode 100644
index 00000000..00ffd1a3
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/csh_config.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2022, Egahp
+ * Copyright (c) 2024, HPMicro
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef CSH_CONFIG_H
+#define CSH_CONFIG_H
+
+/*!< argument check */
+#define CONFIG_CSH_DEBUG 0
+
+/*!< default row */
+#define CONFIG_CSH_DFTROW 25
+
+/*!< default column */
+#define CONFIG_CSH_DFTCOL 80
+
+/*!< history support <+550byte> */
+#define CONFIG_CSH_HISTORY 1
+
+/*!< completion support <+1100byte> */
+#define CONFIG_CSH_COMPLETION 1
+
+/*!< max completion item list count (use stack 4 x count byte) */
+#define CONFIG_CSH_MAX_COMPLETION 40
+
+/*!< prompt edit support <+1000byte>  */
+#define CONFIG_CSH_PROMPTEDIT 1
+
+/*!< prompt segment count */
+#define CONFIG_CSH_PROMPTSEG 7
+
+/*!< xterm support */
+#define CONFIG_CSH_XTERM 0
+
+/*!< newline */
+#define CONFIG_CSH_NEWLINE "\r\n"
+
+/*!< tab space count */
+#define CONFIG_CSH_SPACE 4
+
+/*!< independent ctrl map */
+#define CONFIG_CSH_CTRLMAP 0
+
+/*!< independent alt map */
+#define CONFIG_CSH_ALTMAP 0
+
+/*!< refresh prompt */
+#define CONFIG_CSH_REFRESH_PROMPT 1
+
+/*!< no waiting for sget */
+#define CONFIG_CSH_NOBLOCK 1
+
+/*!< help information */
+#define CONFIG_CSH_HELP ""
+
+/*!< path length 0:const path, <=255:variable path */
+#define CONFIG_CSH_MAXLEN_PATH 128
+
+/*!< path segment count */
+#define CONFIG_CSH_MAXSEG_PATH 16
+
+/*!< user count */
+#define CONFIG_CSH_MAX_USER 1
+
+/*!< max argument count */
+#define CONFIG_CSH_MAX_ARG 8
+
+/*!< linebuffer static or on stack */
+#define CONFIG_CSH_LNBUFF_STATIC 1
+
+/*!< linebuffer size (valid only if lnbuff on stack) */
+#define CONFIG_CSH_LNBUFF_SIZE 256
+
+/*!< multi-thread mode */
+#define CONFIG_CSH_MULTI_THREAD 1
+
+/*!< independent signal handler (for multi instances) */
+#define CONFIG_CSH_SIGNAL_HANDLER 0
+
+/*!< Ctrl+c/d/q/s/z/\ F1-F12 UE <+120byte> */
+#define CONFIG_CSH_USER_CALLBACK 1
+
+/*!< enable macro export symbol table */
+#define CONFIG_CSH_SYMTAB 1
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/ec_config.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/ec_config.h
new file mode 100644
index 00000000..7419e55e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/ec_config.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_CONFIG_H
+#define EC_CONFIG_H
+
+#define CONFIG_EC_PRINTF(...) printf(__VA_ARGS__)
+
+#ifndef CONFIG_EC_DBG_LEVEL
+#define CONFIG_EC_DBG_LEVEL EC_DBG_INFO
+#endif
+
+#ifndef CONFIG_EC_SLAVE_DBG_LEVEL
+#define CONFIG_EC_SLAVE_DBG_LEVEL EC_DBG_INFO
+#endif
+
+/* Enable print with color */
+#define CONFIG_EC_PRINTF_COLOR_ENABLE
+
+#define EC_FAST_CODE_SECTION __attribute__((section(".fast")))
+
+#ifndef CONFIG_EC_MAX_NETDEVS
+#define CONFIG_EC_MAX_NETDEVS 1
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_PRIO
+#define CONFIG_EC_NONPERIOD_PRIO 0
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_STACKSIZE
+#define CONFIG_EC_NONPERIOD_STACKSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_INTERVAL_MS
+#define CONFIG_EC_NONPERIOD_INTERVAL_MS 10
+#endif
+
+#ifndef CONFIG_EC_NONPERIOD_WAITERS
+#define CONFIG_EC_NONPERIOD_WAITERS 20
+#endif
+
+#ifndef CONFIG_EC_SCAN_PRIO
+#define CONFIG_EC_SCAN_PRIO 1
+#endif
+
+#ifndef CONFIG_EC_SCAN_STACKSIZE
+#define CONFIG_EC_SCAN_STACKSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_SCAN_INTERVAL_MS
+#define CONFIG_EC_SCAN_INTERVAL_MS 100
+#endif
+
+#ifndef CONFIG_EC_PER_SM_MAX_PDOS
+#define CONFIG_EC_PER_SM_MAX_PDOS 8
+#endif
+
+#ifndef CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES
+#define CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES 8
+#endif
+
+#define CONFIG_EC_PERF_ENABLE
+#define CONFIG_EC_CMD_ENABLE
+// #define CONFIG_EC_TIMESTAMP_CUSTOM
+// #define CONFIG_EC_PHY_CUSTOM
+
+#ifndef CONFIG_EC_MAX_PDO_BUFSIZE
+#define CONFIG_EC_MAX_PDO_BUFSIZE 2048
+#endif
+
+#ifndef CONFIG_EC_MAX_ENET_TXBUF_COUNT
+#define CONFIG_EC_MAX_ENET_TXBUF_COUNT 10
+#endif
+
+#ifndef CONFIG_EC_MAX_ENET_RXBUF_COUNT
+#define CONFIG_EC_MAX_ENET_RXBUF_COUNT 10
+#endif
+
+// #define CONFIG_EC_FOE
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/shell.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/shell.h
new file mode 100644
index 00000000..1bf5ef5d
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/shell.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2022, Egahp
+ * Copyright (c) 2024, HPMicro
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SHELL_H
+#define SHELL_H
+
+#include "hpm_uart_drv.h"
+#include "csh.h"
+
+extern int shell_init(UART_Type *uart, bool need_login);
+extern void shell_uart_isr(void);
+extern void shell_lock(void);
+extern void shell_unlock(void);
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/main.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/main.c
new file mode 100644
index 00000000..45ac78fc
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/main.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2024 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/* FreeRTOS kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*  HPM example includes. */
+#include <stdio.h>
+#include "board.h"
+#include "hpm_clock_drv.h"
+#include "hpm_uart_drv.h"
+#include "shell.h"
+#include "hpm_gptmr_drv.h"
+#include "cia402_def.h"
+#include "ec_master.h"
+
+SDK_DECLARE_EXT_ISR_M(BOARD_CONSOLE_UART_IRQ, shell_uart_isr)
+
+#define task_start_PRIORITY (configMAX_PRIORITIES - 2U)
+
+#define MOTOR_MODE_CSV_CSP  0
+#define MOTOR_MODE_CSP      1
+#define MOTOR_MODE_CSV      2
+
+volatile uint8_t motor_mode = MOTOR_MODE_CSV;
+
+ec_master_t g_ec_master;
+
+static void task_start(void *param);
+
+int main(void)
+{
+    board_init();
+
+    if (pdPASS != xTaskCreate(task_start, "task_start", 1024U, NULL, task_start_PRIORITY, NULL)) {
+        printf("Task start creation failed!\r\n");
+        while (1) {
+        };
+    }
+
+    vTaskStartScheduler();
+    printf("Unexpected scheduler exit!\r\n");
+    while (1) {
+    };
+
+    return 0;
+}
+
+static void task_start(void *param)
+{
+    (void)param;
+
+    printf("Try to initialize the uart\r\n"
+           "  if you are using the console uart as the shell uart\r\n"
+           "  failure to initialize may result in no log\r\n");
+
+    uart_config_t shell_uart_config = { 0 };
+    uart_default_config(BOARD_CONSOLE_UART_BASE, &shell_uart_config);
+    shell_uart_config.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
+    shell_uart_config.baudrate = 115200;
+
+    if (status_success != uart_init(BOARD_CONSOLE_UART_BASE, &shell_uart_config)) {
+        /* uart failed to be initialized */
+        printf("Failed to initialize uart\r\n");
+        while (1) {
+        };
+    }
+
+    printf("Initialize shell uart successfully\r\n");
+
+    /* default password is : 12345678 */
+    /* shell_init() must be called in-task */
+    if (0 != shell_init(BOARD_CONSOLE_UART_BASE, false)) {
+        /* shell failed to be initialized */
+        printf("Failed to initialize shell\r\n");
+        while (1) {
+        };
+    }
+
+    printf("Initialize shell successfully\r\n");
+
+    /* irq must be enabled after shell_init() */
+    uart_enable_irq(BOARD_CONSOLE_UART_BASE, uart_intr_rx_data_avail_or_timeout);
+    intc_m_enable_irq_with_priority(BOARD_CONSOLE_UART_IRQ, 1);
+
+    printf("Enable shell uart interrupt\r\n");
+
+    ec_master_cmd_init(&g_ec_master);
+    ec_master_init(&g_ec_master, 0);
+
+    printf("Exit start task\r\n");
+
+    vTaskDelete(NULL);
+}
+
+CSH_CMD_EXPORT(ethercat, );
+
+unsigned char cherryecat_eepromdata[2048]; // EEPROM data buffer, please generate by esi_parse.py
+
+static ec_pdo_entry_info_t dio_1600[] = {
+    { 0x6000, 0x00, 0x20 },
+};
+
+static ec_pdo_entry_info_t dio_1a00[] = {
+    { 0x7010, 0x00, 0x20 },
+};
+
+static ec_pdo_info_t dio_rxpdos[] = {
+    { 0x1600, 1, &dio_1600[0] },
+};
+
+static ec_pdo_info_t dio_txpdos[] = {
+    { 0x1a00, 1, &dio_1a00[0] },
+};
+
+static ec_sync_info_t dio_syncs[] = {
+    { 2, EC_DIR_OUTPUT, 1, dio_rxpdos },
+    { 3, EC_DIR_INPUT, 1, dio_txpdos },
+};
+
+static ec_pdo_entry_info_t coe402_1602[] = {
+    { 0x6040, 0x00, 0x10 },
+    { 0x60ff, 0x00, 0x20 },
+    { 0x0000, 0x00, 0x10 },
+};
+
+static ec_pdo_entry_info_t coe402_1a02[] = {
+    { 0x6041, 0x00, 0x10 },
+    { 0x6064, 0x00, 0x20 },
+    { 0x0000, 0x00, 0x10 },
+};
+
+static ec_pdo_info_t cia402_rxpdos[] = {
+    { 0x1602, 3, &coe402_1602[0] },
+};
+
+static ec_pdo_info_t cia402_txpdos[] = {
+    { 0x1a02, 3, &coe402_1a02[0] },
+};
+
+static ec_sync_info_t cia402_syncs[] = {
+    { 2, EC_DIR_OUTPUT, 1, cia402_rxpdos },
+    { 3, EC_DIR_INPUT, 1, cia402_txpdos },
+};
+
+int ec_start(int argc, const char **argv)
+{
+    static ec_slave_config_t slave_cia402_config;
+    static ec_slave_config_t slave_dio_config;
+
+    if (g_ec_master.slave_count == 0) {
+        printf("No slave found, please check the connection\r\n");
+        return -1;
+    }
+
+    if (argc < 2) {
+        printf("Please input: ec_start <cyclic time in us>\r\n");
+        return -1;
+    }
+
+    slave_cia402_config.dc_assign_activate = 0x300;
+
+    slave_cia402_config.dc_sync[0].cycle_time = atoi(argv[1]) * 1000;
+    slave_cia402_config.dc_sync[0].shift_time = 1000000;
+    slave_cia402_config.dc_sync[1].cycle_time = 0;
+    slave_cia402_config.dc_sync[1].shift_time = 0;
+
+    slave_cia402_config.sync = cia402_syncs;
+    slave_cia402_config.sync_count = sizeof(cia402_syncs) / sizeof(ec_sync_info_t);
+
+    slave_dio_config.dc_assign_activate = 0x300;
+
+    slave_dio_config.dc_sync[0].cycle_time = atoi(argv[1]) * 1000;
+    slave_dio_config.dc_sync[0].shift_time = 1000000;
+    slave_dio_config.dc_sync[1].cycle_time = 0;
+    slave_dio_config.dc_sync[1].shift_time = 0;
+    slave_dio_config.sync = dio_syncs;
+    slave_dio_config.sync_count = sizeof(dio_syncs) / sizeof(ec_sync_info_t);
+
+    for (uint32_t i = 0; i < g_ec_master.slave_count; i++) {
+        if (g_ec_master.slaves[i].sii.vendor_id != 0x0048504D) { // HPMicro
+            EC_LOG_ERR("Unsupported slave found: vendor_id=0x%08x\n", g_ec_master.slaves[i].sii.vendor_id);
+            return -1;
+        }
+
+        switch (g_ec_master.slaves[i].sii.product_code) {
+            case 0x00000001: // DIO
+                g_ec_master.slaves[i].config = &slave_dio_config;
+                break;
+            case 0x00000002: // FOE
+                break;
+            case 0x00000003: // CIA402
+                g_ec_master.slaves[i].config = &slave_cia402_config;
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    ec_master_start(&g_ec_master, atoi(argv[1]));
+    return 0;
+}
+CSH_CMD_EXPORT(ec_start, );
+
+int ec_stop(int argc, const char **argv)
+{
+    ec_master_stop(&g_ec_master);
+    return 0;
+}
+CSH_CMD_EXPORT(ec_stop, );
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/.gitignore b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/.gitignore
new file mode 100644
index 00000000..c809c12d
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/.gitignore
@@ -0,0 +1 @@
+*build
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/Makefile b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/Makefile
new file mode 100644
index 00000000..d0c3cbf1
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/Makefile
@@ -0,0 +1,20 @@
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS    ?=
+SPHINXBUILD   ?= sphinx-build
+SOURCEDIR     = source
+BUILDDIR      = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/assets/ethercat.png b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/assets/ethercat.png
new file mode 100644
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diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/assets/ethercat6.png b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/assets/ethercat6.png
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diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/make.bat b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/make.bat
new file mode 100644
index 00000000..6247f7e2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/make.bat
@@ -0,0 +1,35 @@
+@ECHO OFF
+
+pushd %~dp0
+
+REM Command file for Sphinx documentation
+
+if "%SPHINXBUILD%" == "" (
+	set SPHINXBUILD=sphinx-build
+)
+set SOURCEDIR=source
+set BUILDDIR=build
+
+if "%1" == "" goto help
+
+%SPHINXBUILD% >NUL 2>NUL
+if errorlevel 9009 (
+	echo.
+	echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
+	echo.installed, then set the SPHINXBUILD environment variable to point
+	echo.to the full path of the 'sphinx-build' executable. Alternatively you
+	echo.may add the Sphinx directory to PATH.
+	echo.
+	echo.If you don't have Sphinx installed, grab it from
+	echo.http://sphinx-doc.org/
+	exit /b 1
+)
+
+%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%
+goto end
+
+:help
+%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%
+
+:end
+popd
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/requirements.txt b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/requirements.txt
new file mode 100644
index 00000000..03cfbf10
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/requirements.txt
@@ -0,0 +1,9 @@
+# markdown suport
+recommonmark
+# markdown table suport
+sphinx-markdown-tables
+
+# theme default rtd
+
+# crate-docs-theme
+sphinx-rtd-theme
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/api.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/api.rst
new file mode 100644
index 00000000..6d549339
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/api.rst
@@ -0,0 +1,2 @@
+API 手册
+===========================
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/conf.py b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/conf.py
new file mode 100644
index 00000000..361d9daa
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/conf.py
@@ -0,0 +1,37 @@
+# Configuration file for the Sphinx documentation builder.
+
+# -- Project information
+
+project = 'CherryEC'
+copyright = '2025 ~ 2026, sakumisu'
+author = 'sakumisu'
+
+release = '0.1.0'
+version = '0.1.0'
+
+# -- General configuration
+
+extensions = [
+    'sphinx.ext.duration',
+    'sphinx.ext.doctest',
+    'sphinx.ext.autodoc',
+    'sphinx.ext.autosummary',
+    'sphinx.ext.intersphinx',
+    'recommonmark',
+    'sphinx_markdown_tables'
+]
+
+intersphinx_mapping = {
+#    'python': ('https://docs.python.org/3/', None),
+#    'sphinx': ('https://www.sphinx-doc.org/en/master/', None),
+}
+intersphinx_disabled_domains = ['std']
+
+templates_path = ['_templates']
+
+# -- Options for HTML output
+
+html_theme = 'sphinx_rtd_theme'
+
+# -- Options for EPUB output
+epub_show_urls = 'footnote'
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/ethercat.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/ethercat.rst
new file mode 100644
index 00000000..303cecea
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/ethercat.rst
@@ -0,0 +1,32 @@
+EtherCAT 概念
+===========================
+
+EtherCAT 官方文档汇总
+-----------------------------
+
+EtherCAT 数据格式
+--------------------
+
+EtherCAT 寻址模式
+--------------------
+
+EtherCAT 状态机
+--------------------
+
+EtherCAT 同步
+--------------------
+
+EtherCAT SII EEPROM
+-----------------------
+
+EtherCAT SM & FMMU
+-----------------------
+
+EtherCAT SDO & PDO
+-----------------------
+
+EtherCAT COE
+-----------------------
+
+EtherCAT FOE
+-----------------------
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/index.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/index.rst
new file mode 100644
index 00000000..5eb0a418
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/index.rst
@@ -0,0 +1,17 @@
+.. CherryEC 使用指南 documentation master file, created by
+   sphinx-quickstart on Thu Nov 21 10:50:33 2019.
+   You can adapt this file completely to your liking, but it should at least
+   contain the root `toctree` directive.
+
+CherryEC 使用指南
+======================================================
+
+CherryEC 是一个小而美的、高实时性、低抖动 EtherCAT 主机协议栈，专为跑在 RTOS 下的 MCU 设计。
+
+.. toctree::
+   :maxdepth: 1
+
+   quickstart
+   api
+   ethercat
+   version
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/quickstart.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/quickstart.rst
new file mode 100644
index 00000000..34e204d5
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/quickstart.rst
@@ -0,0 +1,9 @@
+快速入门
+===========================
+
+
+HPMicro Boards
+-----------------------------
+
+RT-Thread RuiQing
+-----------------------------
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/version.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/version.rst
new file mode 100644
index 00000000..ebccbc07
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/version.rst
@@ -0,0 +1,2 @@
+版本说明
+===========================
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_cmd.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_cmd.h
new file mode 100644
index 00000000..1513ad37
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_cmd.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_CMD_H
+#define EC_CMD_H
+
+typedef struct ec_master ec_master_t;
+
+void ec_master_cmd_init(ec_master_t *master);
+int ethercat(int argc, const char **argv);
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_coe.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_coe.h
new file mode 100644
index 00000000..66334039
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_coe.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_COE_H
+#define EC_COE_H
+
+int ec_coe_download(ec_master_t *master,
+                    uint16_t slave_index,
+                    ec_datagram_t *datagram,
+                    uint16_t index,
+                    uint8_t subindex,
+                    const void *buf,
+                    uint32_t size,
+                    bool complete_access);
+
+int ec_coe_upload(ec_master_t *master,
+                  uint16_t slave_index,
+                  ec_datagram_t *datagram,
+                  uint16_t index,
+                  uint8_t subindex,
+                  const void *buf,
+                  uint32_t maxsize,
+                  uint32_t *size,
+                  bool complete_access);
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_common.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_common.h
new file mode 100644
index 00000000..a5ccaf1e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_COMMON_H
+#define EC_COMMON_H
+
+void *ec_memcpy(void *s1, const void *s2, size_t n);
+void ec_memset(void *s, int c, size_t n);
+const char *ec_state_string(uint8_t states, uint8_t multi);
+const char *ec_mbox_protocol_string(uint8_t prot);
+const char *ec_alstatus_string(uint16_t errorcode);
+const char *ec_mbox_error_string(uint16_t errorcode);
+const char *ec_sdo_abort_string(uint32_t errorcode);
+const char *foe_errorcode_string(uint16_t errorcode);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_datagram.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_datagram.h
new file mode 100644
index 00000000..d99719e6
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_datagram.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_DATAGRAM_H
+#define EC_DATAGRAM_H
+
+/** EtherCAT datagram type.
+ */
+typedef enum {
+    EC_DATAGRAM_NONE = 0x00, /**< Dummy. */
+    EC_DATAGRAM_APRD = 0x01, /**< Auto Increment Physical Read. */
+    EC_DATAGRAM_APWR = 0x02, /**< Auto Increment Physical Write. */
+    EC_DATAGRAM_APRW = 0x03, /**< Auto Increment Physical ReadWrite. */
+    EC_DATAGRAM_FPRD = 0x04, /**< Configured Address Physical Read. */
+    EC_DATAGRAM_FPWR = 0x05, /**< Configured Address Physical Write. */
+    EC_DATAGRAM_FPRW = 0x06, /**< Configured Address Physical ReadWrite. */
+    EC_DATAGRAM_BRD = 0x07,  /**< Broadcast Read. */
+    EC_DATAGRAM_BWR = 0x08,  /**< Broadcast Write. */
+    EC_DATAGRAM_BRW = 0x09,  /**< Broadcast ReadWrite. */
+    EC_DATAGRAM_LRD = 0x0A,  /**< Logical Read. */
+    EC_DATAGRAM_LWR = 0x0B,  /**< Logical Write. */
+    EC_DATAGRAM_LRW = 0x0C,  /**< Logical ReadWrite. */
+    EC_DATAGRAM_ARMW = 0x0D, /**< Auto Increment Physical Read Multiple
+                               Write.  */
+    EC_DATAGRAM_FRMW = 0x0E, /**< Configured Address Physical Read Multiple
+                               Write. */
+} ec_datagram_type_t;
+
+/** EtherCAT datagram state.
+ */
+typedef enum {
+    EC_DATAGRAM_INIT,      /**< Initial state of a new datagram. */
+    EC_DATAGRAM_QUEUED,    /**< Queued for sending. */
+    EC_DATAGRAM_SENT,      /**< Sent (still in the queue). */
+    EC_DATAGRAM_RECEIVED,  /**< Received (dequeued). */
+    EC_DATAGRAM_TIMED_OUT, /**< Timed out (dequeued). */
+    EC_DATAGRAM_ERROR      /**< Error while sending/receiving (dequeued). */
+} ec_datagram_state_t;
+
+/** EtherCAT datagram.
+ */
+typedef struct {
+    ec_dlist_t queue;
+    ec_dlist_t ext_queue;
+    ec_dlist_t sent;
+    ec_netdev_index_t netdev_idx;     /**< Netdev via which the datagram shall be / was sent. */
+    ec_datagram_type_t type;          /**< Datagram type (APRD, BWR, etc.). */
+    bool static_alloc;                /**< True, if \a data is statically allocated. */
+    uint8_t address[EC_ADDR_LEN];     /**< Recipient address. */
+    uint8_t *data;                    /**< Datagram payload. */
+    size_t mem_size;                  /**< Datagram \a data memory size. */
+    size_t data_size;                 /**< Size of the data in \a data. */
+    uint8_t index;                    /**< Index (set by master). */
+    uint16_t working_counter;         /**< Working counter. */
+    ec_datagram_state_t state;        /**< State. */
+    uint32_t lrw_read_offset;         /**< Read Offset in LRW datagram. */
+    uint32_t lrw_read_size;           /**< Read Size in LRW datagram. */
+    uint64_t jiffies_sent;            /**< Jiffies, when the datagram was sent. */
+    uint64_t jiffies_received;        /**< Jiffies, when the datagram was received. */
+    char name[EC_DATAGRAM_NAME_SIZE]; /**< Description of the datagram. */
+    bool waiter;                      /**< True, if someone is waiting for the datagram. */
+    ec_osal_sem_t wait;               /**< Semaphore for waiting. */
+} ec_datagram_t;
+
+void ec_datagram_init(ec_datagram_t *datagram, size_t mem_size);
+void ec_datagram_init_static(ec_datagram_t *datagram, uint8_t *data, size_t mem_size);
+void ec_datagram_clear(ec_datagram_t *datagram);
+void ec_datagram_unqueue(ec_datagram_t *datagram);
+void ec_datagram_zero(ec_datagram_t *datagram);
+void ec_datagram_fill(ec_datagram_t *datagram,
+                      ec_datagram_type_t type,
+                      uint16_t adp,
+                      uint16_t ado,
+                      uint16_t size);
+void ec_datagram_aprd(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size);
+void ec_datagram_apwr(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size);
+void ec_datagram_aprw(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size);
+void ec_datagram_armw(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size);
+void ec_datagram_fprd(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size);
+void ec_datagram_fpwr(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size);
+void ec_datagram_fprw(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size);
+void ec_datagram_frmw(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size);
+void ec_datagram_brd(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size);
+void ec_datagram_bwr(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size);
+void ec_datagram_brw(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size);
+void ec_datagram_lrd(ec_datagram_t *datagram, uint32_t offset, size_t data_size);
+void ec_datagram_lwr(ec_datagram_t *datagram, uint32_t offset, size_t data_size);
+void ec_datagram_lrw(ec_datagram_t *datagram, uint32_t offset, size_t data_size);
+const char *ec_datagram_type_string(const ec_datagram_t *datagram);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_def.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_def.h
new file mode 100644
index 00000000..f64ecb1b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_def.h
@@ -0,0 +1,541 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_DEF_H
+#define EC_DEF_H
+
+/*
+ *	IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
+ *	and FCS/CRC (frame check sequence).
+ */
+#define ETH_ALEN      6    /* Octets in one ethernet addr	 */
+#define ETH_TLEN      2    /* Octets in ethernet type field */
+#define ETH_HLEN      14   /* Total octets in header.	 */
+#define ETH_ZLEN      60   /* Min. octets in frame sans FCS */
+#define ETH_DATA_LEN  1500 /* Max. octets in payload	 */
+#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
+#define ETH_FCS_LEN   4    /* Octets in the FCS		 */
+
+#define ETH_MIN_MTU 68      /* Min IPv4 MTU per RFC791	*/
+#define ETH_MAX_MTU 0xFFFFU /* 65535, same as IP_MAX_MTU	*/
+
+/** Datagram timeout in microseconds. */
+#define EC_IO_TIMEOUT 500
+
+/** Time to send a byte in nanoseconds.
+ *
+ * t_ns = 1 / (100 MBit/s / 8 bit/byte) = 80 ns/byte
+ */
+#define EC_BYTE_TRANSMISSION_TIME_NS 80
+
+/** Minimum size of a buffer used with ec_state_string(). */
+#define EC_STATE_STRING_SIZE 32
+
+/** Maximum SII size in words, to avoid infinite reading. */
+#define EC_MAX_SII_SIZE 4096
+
+/** Number of statistic rate intervals to maintain. */
+#define EC_RATE_COUNT 3
+
+/*****************************************************************************
+ * EtherCAT protocol
+ ****************************************************************************/
+
+/** Size of an EtherCAT frame header. */
+#define EC_FRAME_HEADER_SIZE 2
+
+/** Size of an EtherCAT datagram header. */
+#define EC_DATAGRAM_HEADER_SIZE 10
+
+/** Size of an EtherCAT datagram workcounter. */
+#define EC_DATAGRAM_WC_SIZE 2
+
+/** Size of the EtherCAT address field. */
+#define EC_ADDR_LEN 4
+
+/** Resulting maximum data size of a single datagram in a frame. */
+#define EC_MAX_DATA_SIZE (ETH_DATA_LEN - EC_FRAME_HEADER_SIZE - EC_DATAGRAM_HEADER_SIZE - EC_DATAGRAM_WC_SIZE)
+
+/** Mailbox header size.  */
+#define EC_MBOX_HEADER_SIZE 6
+
+/** Word offset of first SII category. */
+#define EC_FIRST_SII_CATEGORY_OFFSET 0x40
+
+/** Size of a sync manager configuration page. */
+#define EC_SYNC_PAGE_SIZE 8
+
+/** Maximum number of FMMUs per slave. */
+#define EC_MAX_FMMUS 16
+
+/** Size of an FMMU configuration page. */
+#define EC_FMMU_PAGE_SIZE 16
+
+/** Number of DC sync signals. */
+#define EC_SYNC_SIGNAL_COUNT 2
+
+/** Size of the datagram decription string.
+ *
+ * This is also used as the maximum lenth of EoE device names.
+ **/
+#define EC_DATAGRAM_NAME_SIZE 20
+
+/** Maximum hostname size.
+ *
+ * Used inside the EoE set IP parameter request.
+ */
+#define EC_MAX_HOSTNAME_SIZE 32
+
+/** Maximum number of sync managers per slave.
+ */
+#define EC_MAX_SYNC_MANAGERS 16
+
+/** Maximum string length.
+ *
+ * Used in ec_slave_info_t.
+ */
+#define EC_MAX_STRING_LENGTH 64
+
+/** Maximum number of slave ports. */
+#define EC_MAX_PORTS 4
+
+/** Slave state mask.
+ *
+ * Apply this mask to a slave state byte to get the slave state without
+ * the error flag.
+ */
+#define EC_SLAVE_STATE_MASK 0x0F
+
+/** State of an EtherCAT slave.
+ */
+typedef enum {
+    EC_SLAVE_STATE_UNKNOWN = 0x00,
+    /**< unknown state */
+    EC_SLAVE_STATE_INIT = 0x01,
+    /**< INIT state (no mailbox communication, no IO) */
+    EC_SLAVE_STATE_PREOP = 0x02,
+    /**< PREOP state (mailbox communication, no IO) */
+    EC_SLAVE_STATE_BOOT = 0x03,
+    /**< Bootstrap state (mailbox communication, firmware update) */
+    EC_SLAVE_STATE_SAFEOP = 0x04,
+    /**< SAFEOP (mailbox communication and input update) */
+    EC_SLAVE_STATE_OP = 0x08,
+    /**< OP (mailbox communication and input/output update) */
+    EC_SLAVE_STATE_ACK_ERR = 0x10
+    /**< Acknowledge/Error bit (no actual state) */
+} ec_slave_state_t;
+
+/** Slave information interface CANopen over EtherCAT details flags.
+ */
+typedef struct {
+    uint8_t enable_sdo                 : 1; /**< Enable SDO access. */
+    uint8_t enable_sdo_info            : 1; /**< SDO information service available. */
+    uint8_t enable_pdo_assign          : 1; /**< PDO mapping configurable. */
+    uint8_t enable_pdo_configuration   : 1; /**< PDO configuration possible. */
+    uint8_t enable_upload_at_startup   : 1; /**< ?. */
+    uint8_t enable_sdo_complete_access : 1; /**< Complete access possible. */
+    uint8_t                            : 2; /**< Reserved bits. */
+} ec_sii_coe_details_t;
+
+/** Slave information interface general flags.
+ */
+typedef struct {
+    uint8_t enable_safeop  : 1; /**< ?. */
+    uint8_t enable_not_lrw : 1; /**< Slave does not support LRW. */
+    uint8_t                : 6; /**< Reserved bits. */
+} ec_sii_general_flags_t;
+
+/** EtherCAT slave distributed clocks range.
+ */
+typedef enum {
+    EC_DC_32, /**< 32 bit. */
+    EC_DC_64  /*< 64 bit for system time, system time offset and
+               port 0 receive time. */
+} ec_slave_dc_range_t;
+
+/** EtherCAT slave sync signal configuration.
+ */
+typedef struct {
+    uint32_t cycle_time; /**< Cycle time [ns]. */
+    int32_t shift_time;  /**< Shift time [ns]. */
+} ec_sync_signal_t;
+
+/** Master netdev.
+ */
+typedef enum {
+    EC_NETDEV_MAIN,  /**< Main netdev. */
+    EC_NETDEV_BACKUP /**< Backup netdev */
+} ec_netdev_index_t;
+
+typedef struct ec_alstatus {
+    uint16_t alstatus;
+    uint16_t unused;
+    uint16_t alstatuscode;
+} ec_alstatus_t;
+
+/* AL Status Codes */
+#define EC_ALSTATUSCODE_NOERROR                    0x0000 /**< No error*/
+#define EC_ALSTATUSCODE_UNSPECIFIEDERROR           0x0001 /**< Unspecified error*/
+#define EC_ALSTATUSCODE_NOMEMORY                   0x0002 /**< No Memory*/
+#define EC_ALSTATUSCODE_INVALID_REVISION           0x0004 /**< Output/Input mapping is not valid for this hardware or software revision (0x1018:03)*/
+#define EC_ALSTATUSCODE_FW_SII_NOT_MATCH           0x0006 /**< Firmware and EEPROM do not match. Slave needs BOOT-INIT transition*/
+#define EC_ALSTATUSCODE_FW_UPDATE_FAILED           0x0007 /**< Firmware update not successful. Old firmware still running*/
+#define EC_ALSTATUSCODE_INVALIDALCONTROL           0x0011 /**< Invalid requested state change*/
+#define EC_ALSTATUSCODE_UNKNOWNALCONTROL           0x0012 /**< Unknown requested state*/
+#define EC_ALSTATUSCODE_BOOTNOTSUPP                0x0013 /**< Bootstrap not supported*/
+#define EC_ALSTATUSCODE_NOVALIDFIRMWARE            0x0014 /**< No valid firmware*/
+#define EC_ALSTATUSCODE_INVALIDMBXCFGINBOOT        0x0015 /**< Invalid mailbox configuration (BOOT state)*/
+#define EC_ALSTATUSCODE_INVALIDMBXCFGINPREOP       0x0016 /**< Invalid mailbox configuration (PreOP state)*/
+#define EC_ALSTATUSCODE_INVALIDSMCFG               0x0017 /**< Invalid sync manager configuration*/
+#define EC_ALSTATUSCODE_NOVALIDINPUTS              0x0018 /**< No valid inputs available*/
+#define EC_ALSTATUSCODE_NOVALIDOUTPUTS             0x0019 /**< No valid outputs*/
+#define EC_ALSTATUSCODE_SYNCERROR                  0x001A /**< Synchronization error*/
+#define EC_ALSTATUSCODE_SMWATCHDOG                 0x001B /**< Sync manager watchdog*/
+#define EC_ALSTATUSCODE_SYNCTYPESNOTCOMPATIBLE     0x001C /**< Invalid Sync Manager Types*/
+#define EC_ALSTATUSCODE_INVALIDSMOUTCFG            0x001D /**< Invalid Output Configuration*/
+#define EC_ALSTATUSCODE_INVALIDSMINCFG             0x001E /**< Invalid Input Configuration*/
+#define EC_ALSTATUSCODE_INVALIDWDCFG               0x001F /**< Invalid Watchdog Configuration*/
+#define EC_ALSTATUSCODE_WAITFORCOLDSTART           0x0020 /**< Slave needs cold start*/
+#define EC_ALSTATUSCODE_WAITFORINIT                0x0021 /**< Slave needs INIT*/
+#define EC_ALSTATUSCODE_WAITFORPREOP               0x0022 /**< Slave needs PREOP*/
+#define EC_ALSTATUSCODE_WAITFORSAFEOP              0x0023 /**< Slave needs SAFEOP*/
+#define EC_ALSTATUSCODE_INVALIDINPUTMAPPING        0x0024 /**< Invalid Input Mapping*/
+#define EC_ALSTATUSCODE_INVALIDOUTPUTMAPPING       0x0025 /**< Invalid Output Mapping*/
+#define EC_ALSTATUSCODE_INCONSISTENTSETTINGS       0x0026 /**< Inconsistent Settings*/
+#define EC_ALSTATUSCODE_FREERUNNOTSUPPORTED        0x0027 /**< FreeRun not supported*/
+#define EC_ALSTATUSCODE_SYNCHRONNOTSUPPORTED       0x0028 /**< SyncMode not supported*/
+#define EC_ALSTATUSCODE_FREERUNNEEDS3BUFFERMODE    0x0029 /**< FreeRun needs 3Buffer Mode*/
+#define EC_ALSTATUSCODE_BACKGROUNDWATCHDOG         0x002A /**< Background Watchdog*/
+#define EC_ALSTATUSCODE_NOVALIDINPUTSANDOUTPUTS    0x002B /**< No Valid Inputs and Outputs*/
+#define EC_ALSTATUSCODE_FATALSYNCERROR             0x002C /**< Fatal Sync Error*/
+#define EC_ALSTATUSCODE_NOSYNCERROR                0x002D /**< No Sync Error*/
+#define EC_ALSTATUSCODE_CYCLETIMETOOSMALL          0x002E /**< EtherCAT cycle time smaller Minimum Cycle Time supported by slave*/
+#define EC_ALSTATUSCODE_DCINVALIDSYNCCFG           0x0030 /**< Invalid DC SYNCH Configuration*/
+#define EC_ALSTATUSCODE_DCINVALIDLATCHCFG          0x0031 /**< Invalid DC Latch Configuration*/
+#define EC_ALSTATUSCODE_DCPLLSYNCERROR             0x0032 /**< PLL Error*/
+#define EC_ALSTATUSCODE_DCSYNCIOERROR              0x0033 /**< DC Sync IO Error*/
+#define EC_ALSTATUSCODE_DCSYNCMISSEDERROR          0x0034 /**< DC Sync Timeout Error*/
+#define EC_ALSTATUSCODE_DCINVALIDSYNCCYCLETIME     0x0035 /**< DC Invalid Sync Cycle Time*/
+#define EC_ALSTATUSCODE_DCSYNC0CYCLETIME           0x0036 /**< DC Sync0 Cycle Time*/
+#define EC_ALSTATUSCODE_DCSYNC1CYCLETIME           0x0037 /**< DC Sync1 Cycle Time*/
+#define EC_ALSTATUSCODE_MBX_AOE                    0x0041 /**< MBX_AOE*/
+#define EC_ALSTATUSCODE_MBX_EOE                    0x0042 /**< MBX_EOE*/
+#define EC_ALSTATUSCODE_MBX_COE                    0x0043 /**< MBX_COE*/
+#define EC_ALSTATUSCODE_MBX_FOE                    0x0044 /**< MBX_FOE*/
+#define EC_ALSTATUSCODE_MBX_SOE                    0x0045 /**< MBX_SOE*/
+#define EC_ALSTATUSCODE_MBX_VOE                    0x004F /**< MBX_VOE*/
+#define EC_ALSTATUSCODE_EE_NOACCESS                0x0050 /**< EEPROM no access*/
+#define EC_ALSTATUSCODE_EE_ERROR                   0x0051 /**< EEPROM Error*/
+#define EC_ALSTATUSCODE_EXT_HARDWARE_NOT_READY     0x0052 /**< External hardware not ready. This AL Status Code should be used if the EtherCAT-Slave refused the state transition due to an external connection to another device or signal is missing*/
+#define EC_ALSTATUSCODE_DEVICE_IDENT_VALUE_UPDATED 0x0061 /**< In legacy identification mode (dip switch mapped to register 0x12) this error is returned if the EEPROM ID value does not match to dipswitch value*/
+#define EC_ALSTATUSCODE_MODULE_ID_LIST_NOT_MATCH   0x0070 /**< Detected Module Ident List (0xF030) and Configured Module Ident List (0xF050) does not match*/
+#define EC_ALSTATUSCODE_SUPPLY_VOLTAGE_TOO_LOW     0x0080 /**< The slave supply voltage is too low*/
+#define EC_ALSTATUSCODE_SUPPLY_VOLTAGE_TOO_HIGH    0x0081 /**< The slave supply voltage is too high*/
+#define EC_ALSTATUSCODE_TEMPERATURE_TOO_LOW        0x0082 /**< The slave temperature is too low*/
+#define EC_ALSTATUSCODE_TEMPERATURE_TOO_HIGH       0x0083 /**< The slave temperature is too high*/
+
+#define EC_SII_ADDRESS_MANUF           (0x0008)
+#define EC_SII_ADDRESS_PRODUCTCODE     (0x000a)
+#define EC_SII_ADDRESS_REVISION        (0x000c)
+#define EC_SII_ADDRESS_SN              (0x000E)
+#define EC_SII_ADDRESS_BOOTRXMBX       (0x0014)
+#define EC_SII_ADDRESS_BOOTTXMBX       (0x0016)
+#define EC_SII_ADDRESS_MBXSIZE         (0x0019)
+#define EC_SII_ADDRESS_TXMBXADR        (0x001a)
+#define EC_SII_ADDRESS_RXMBXADR        (0x0018)
+#define EC_SII_ADDRESS_MBXPROTO        (0x001c)
+#define EC_SII_ADDRESS_ADDITIONAL_INFO (0x0040)
+
+#define EC_SII_TYPE_NOP       0x0000
+#define EC_SII_TYPE_STRINGS   0x000A
+#define EC_SII_TYPE_DATATYPES 0x0014
+#define EC_SII_TYPE_GENERAL   0x001E
+#define EC_SII_TYPE_FMMU      0x0028
+#define EC_SII_TYPE_SM        0x0029
+#define EC_SII_TYPE_FMMUX     0x002A
+#define EC_SII_TYPE_SYNCUNIT  0x002B
+#define EC_SII_TYPE_TXPDO     0x0032
+#define EC_SII_TYPE_RXPDO     0x0033
+#define EC_SII_TYPE_DC        0x003C
+#define EC_SII_TYPE_END       0xFFFF
+
+#define EC_SII_FMMU_NONE      0x0000
+#define EC_SII_FMMU_READ      0x0001
+#define EC_SII_FMMU_WRITE     0x0002
+#define EC_SII_FMMU_SM_STATUS 0x0003
+
+#define EC_SII_SM_UNKNOWN             0x0000
+#define EC_SII_SM_MBX_OUT             0x0001
+#define EC_SII_SM_MBX_IN              0x0002
+#define EC_SII_SM_PROCESS_DATA_OUTPUT 0x0003
+#define EC_SII_SM_PROCESS_DATA_INPUT  0x0004
+
+typedef struct __PACKED ec_sii_base {
+    uint16_t pdi_control;
+    uint16_t pdi_config;
+    uint16_t sync_impulselen;
+    uint16_t pdi_config2;
+    uint16_t aliasaddr; /**< Configured station alias. */
+    uint8_t reserved[4];
+    uint16_t checksum;
+    uint32_t vendor_id;       /**< Vendor ID. */
+    uint32_t product_code;    /**< Vendor-specific product code. */
+    uint32_t revision_number; /**< Revision number. */
+    uint32_t serial_number;   /**< Serial number. */
+    uint8_t reserved2[8];
+    uint16_t boot_rx_mailbox_offset; /**< Bootstrap receive mailbox address. */
+    uint16_t boot_rx_mailbox_size;   /**< Bootstrap receive mailbox size. */
+    uint16_t boot_tx_mailbox_offset; /**< Bootstrap transmit mailbox address. */
+    uint16_t boot_tx_mailbox_size;   /**< Bootstrap transmit mailbox size. */
+    uint16_t std_rx_mailbox_offset;  /**< Standard receive mailbox address. */
+    uint16_t std_rx_mailbox_size;    /**< Standard receive mailbox size. */
+    uint16_t std_tx_mailbox_offset;  /**< Standard transmit mailbox address. */
+    uint16_t std_tx_mailbox_size;    /**< Standard transmit mailbox size. */
+    uint16_t mailbox_protocols;      /**< Supported mailbox protocols. */
+    uint8_t reserved3[66];
+    uint16_t size;
+    uint16_t version;
+} ec_sii_base_t;
+
+typedef struct __PACKED ec_sii_general {
+    uint8_t groupidx;
+    uint8_t imgidx;
+    uint8_t orderidx;
+    uint8_t nameidx;
+    uint8_t reserved1;
+    ec_sii_coe_details_t coe_details;
+    uint8_t foe_details;
+    uint8_t eoe_details;
+    uint8_t soe_channels;
+    uint8_t ds402_channels;
+    uint8_t sysmanclass;
+    ec_sii_general_flags_t flags;
+    int16_t current_on_ebus;
+    uint8_t reserved2;
+    uint8_t reserved3;
+    uint16_t phy_port;
+    uint16_t phy_memaddress;
+    uint8_t pad[12];
+} ec_sii_general_t;
+
+typedef struct __PACKED ec_sii_sm {
+    uint16_t physical_start_address;
+    uint16_t length;
+    uint8_t control;
+    uint8_t status;
+    uint8_t active;
+    uint8_t type;
+} ec_sii_sm_t;
+
+typedef struct __PACKED ec_sii_pdo_entry {
+    uint16_t index;
+    uint8_t subindex;
+    uint8_t nameidx;
+    uint8_t data_type;
+    uint8_t bitlen;
+    uint16_t flags;
+} ec_sii_pdo_entry_t;
+
+typedef struct __PACKED ec_sii_pdo_mapping {
+    uint16_t index; /* txpdo: 1a00~1bff, rxpdo: 1600~17ff */
+    uint8_t nentry;
+    uint8_t sm_idx;
+    uint8_t synchronization;
+    uint8_t nameidx;
+    uint16_t flags;
+    ec_sii_pdo_entry_t entry[];
+} ec_sii_pdo_mapping_t;
+
+typedef struct __PACKED ec_sm_reg {
+    uint16_t physical_start_address;
+    uint16_t length;
+    uint8_t control;
+    uint8_t status;
+    uint8_t active;
+    uint8_t pdi_control;
+} ec_sm_reg_t;
+
+typedef struct __PACKED ec_fmmu_reg {
+    uint32_t logical_start_address;
+    uint16_t length;
+    uint8_t logical_start_bit;
+    uint8_t logical_stop_bit;
+    uint16_t physical_start_address;
+    uint8_t physical_start_bit;
+    uint8_t type;
+    uint8_t active;
+    uint8_t reserved[3];
+} ec_fmmu_reg_t;
+
+/**
+ * \brief SmAssignObjects SyncManager Assignment Objects
+ * SyncManager 2 : 0x1C12<br>
+ * SyncManager 3 : 0x1C13<br>
+ */
+typedef struct __PACKED ec_pdo_assign_t {
+    uint16_t count; /**< PDO mapping count. */
+    uint16_t entry[CONFIG_EC_PER_SM_MAX_PDOS];
+} ec_pdo_assign_t;
+
+typedef struct __PACKED ec_pdo_mapping_t {
+    uint16_t count; /**< PDO entry count. */
+    uint32_t entry[CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES];
+} ec_pdo_mapping_t;
+
+typedef struct __PACKED ec_mailbox_header {
+    uint16_t length;
+    uint16_t address;
+    uint8_t channel  : 6;
+    uint8_t priority : 2;
+    uint8_t type     : 4;
+    uint8_t counter  : 3;
+    uint8_t reserved : 1;
+} ec_mailbox_header_t;
+
+/** Size of the mailbox header.
+ */
+#define EC_MBOX_HEADER_SIZE 6
+
+#define EC_MBXPROT_AOE 0x0001
+#define EC_MBXPROT_EOE 0x0002
+#define EC_MBXPROT_COE 0x0004
+#define EC_MBXPROT_FOE 0x0008
+#define EC_MBXPROT_SOE 0x0010
+#define EC_MBXPROT_VOE 0x0020
+
+/** Mailbox types.
+ *
+ * These are used in the 'Type' field of the mailbox header.
+ */
+enum {
+    EC_MBOX_TYPE_EOE = 0x02,
+    EC_MBOX_TYPE_COE = 0x03,
+    EC_MBOX_TYPE_FOE = 0x04,
+    EC_MBOX_TYPE_SOE = 0x05,
+    EC_MBOX_TYPE_VOE = 0x0f,
+};
+
+#define EC_SM_INDEX_MBX_WRITE           0x0000
+#define EC_SM_INDEX_MBX_READ            0x0001
+#define EC_SM_INDEX_PROCESS_DATA_OUTPUT 0x0002
+#define EC_SM_INDEX_PROCESS_DATA_INPUT  0x0003
+
+typedef struct __PACKED ec_coe_header {
+    uint16_t number   : 9;
+    uint16_t reserved : 3;
+    uint16_t service  : 4;
+} ec_coe_header_t;
+
+typedef struct __PACKED ec_sdo_header_common {
+    uint8_t size_indicator  : 1;
+    uint8_t transfertype    : 1; // expedited transfer
+    uint8_t data_set_size   : 2;
+    uint8_t complete_access : 1;
+    uint8_t command         : 3;
+} ec_sdo_header_common_t;
+
+typedef struct __PACKED ec_sdo_header_segment {
+    uint8_t more_follows : 1;
+    uint8_t segdata_size : 3;
+    uint8_t toggle       : 1;
+    uint8_t command      : 3;
+} ec_sdo_header_segment_t;
+
+typedef struct __PACKED ec_sdo_header {
+    union {
+        uint8_t byte;
+        ec_sdo_header_common_t common;
+        ec_sdo_header_segment_t segment;
+    };
+    uint16_t index;
+    uint8_t subindex;
+} ec_sdo_header_t;
+
+#define EC_COE_SERVICE_EMERGENCY            0x01
+#define EC_COE_SERVICE_SDO_REQUEST          0x02
+#define EC_COE_SERVICE_SDO_RESPONSE         0x03
+#define EC_COE_SERVICE_TXPDO                0x04
+#define EC_COE_SERVICE_RXPDO                0x05
+#define EC_COE_SERVICE_TXPDO_REMOTE_REQUSET 0x06
+#define EC_COE_SERVICE_RXPDO_REMOTE_REQUEST 0x07
+#define EC_COE_SERVICE_SDOINFO              0x08
+
+#define EC_COE_REQUEST_SEGMENT_DOWNLOAD 0x00
+#define EC_COE_REQUEST_DOWNLOAD         0x01
+#define EC_COE_REQUEST_UPLOAD           0x02
+#define EC_COE_REQUEST_SEGMENT_UPLOAD   0x03
+#define EC_COE_REQUEST_ABORT            0x04
+
+#define EC_COE_RESPONSE_SEGMENT_UPLOAD   0x00
+#define EC_COE_RESPONSE_SEGMENT_DOWNLOAD 0x01
+#define EC_COE_RESPONSE_UPLOAD           0x02
+#define EC_COE_RESPONSE_DOWNLOAD         0x03
+
+typedef struct __PACKED {
+    uint16_t opcode;
+    union {
+        uint32_t password;
+        uint32_t packet_number;
+        uint32_t error_code;
+    };
+} ec_foe_header_t;
+
+#define EC_FOE_OPCODE_READ  0x0001
+#define EC_FOE_OPCODE_WRITE 0x0002
+#define EC_FOE_OPCODE_DATA  0x0003
+#define EC_FOE_OPCODE_ACK   0x0004
+#define EC_FOE_OPCODE_ERROR 0x0005
+#define EC_FOE_OPCODE_BUSY  0x0006
+
+#define EC_FOE_ERRCODE_NOTDEFINED       0x8000 /**< \brief Not defined*/
+#define EC_FOE_ERRCODE_NOTFOUND         0x8001 /**< \brief The file requested by an FoE upload service could not be found on the server*/
+#define EC_FOE_ERRCODE_ACCESS           0x8002 /**< \brief Read or write access to this file not allowed (e.g. due to local control).*/
+#define EC_FOE_ERRCODE_DISKFULL         0x8003 /**< \brief Disk to store file is full or memory allocation exceeded*/
+#define EC_FOE_ERRCODE_ILLEGAL          0x8004 /**< \brief Illegal FoE operation, e.g. service identifier invalid*/
+#define EC_FOE_ERRCODE_PACKENO          0x8005 /**< \brief FoE packet number invalid*/
+#define EC_FOE_ERRCODE_EXISTS           0x8006 /**< \brief The file which is requested to be downloaded does already exist*/
+#define EC_FOE_ERRCODE_NOUSER           0x8007 /**< \brief No User*/
+#define EC_FOE_ERRCODE_BOOTSTRAPONLY    0x8008 /**< \brief FoE only supported in Bootstrap*/
+#define EC_FOE_ERRCODE_NOTINBOOTSTRAP   0x8009 /**< \brief This file may not be accessed in BOOTSTRAP state*/
+#define EC_FOE_ERRCODE_NORIGHTS         0x800A /**< \brief Password invalid*/
+#define EC_FOE_ERRCODE_PROGERROR        0x800B /**< \brief Generic programming error. Should only be returned if  error reason cannot be distinguished*/
+#define EC_FOE_ERRCODE_INVALID_CHECKSUM 0x800C /**< \brief checksum included in the file is invalid*/
+#define EC_FOE_ERRCODE_INVALID_FIRMWARE 0x800D /**< \brief The hardware does not support the downloaded firmware*/
+#define EC_FOE_ERRCODE_NO_FILE          0x800F /**< \brief Do not use (identical with 0x8001)*/
+#define EC_FOE_ERRCODE_NO_FILE_HEADER   0x8010 /**< \brief Missing file header of error in file header*/
+#define EC_FOE_ERRCODE_FLASH_ERROR      0x8011 /**< \brief Flash cannot be accessed*/
+
+typedef enum {
+    EC_DIR_OUTPUT, /**< Values written by the master. */
+    EC_DIR_INPUT,  /**< Values read by the master. */
+} ec_direction_t;
+
+typedef enum {
+    EC_WD_DEFAULT, /**< Use the default setting of the sync manager. */
+    EC_WD_ENABLE,  /**< Enable the watchdog. */
+    EC_WD_DISABLE, /**< Disable the watchdog. */
+} ec_watchdog_mode_t;
+
+typedef struct {
+    uint16_t index;     /**< PDO entry index. */
+    uint8_t subindex;   /**< PDO entry subindex. */
+    uint8_t bit_length; /**< Size of the PDO entry in bit. */
+} ec_pdo_entry_info_t;
+
+typedef struct {
+    uint16_t index; /**< PDO index. */
+    uint32_t n_entries;
+    ec_pdo_entry_info_t const *entries;
+} ec_pdo_info_t;
+
+typedef struct {
+    uint8_t index; /**< Sync manager index. */
+    ec_direction_t dir;
+    uint32_t n_pdos;
+    ec_pdo_info_t const *pdos;
+    ec_watchdog_mode_t watchdog_mode;
+} ec_sync_info_t;
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_errno.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_errno.h
new file mode 100644
index 00000000..c8efe23a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_errno.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_ERRNO_H
+#define EC_ERRNO_H
+
+#define EC_ERR_OK          0  /**< No error */
+#define EC_ERR_NOMEM       1  /**< Out of memory */
+#define EC_ERR_INVAL       2  /**< Invalid argument */
+#define EC_ERR_TIMEOUT     3  /**< Timeout */
+#define EC_ERR_IO          4  /**< I/O error */
+#define EC_ERR_WC          5  /**< working counter error */
+#define EC_ERR_ALERR       6  /**< AL status error */
+#define EC_ERR_SII         7  /**< SII error */
+#define EC_ERR_MBOX        8  /**< mailbox error */
+#define EC_ERR_COE_TYPE    9  /**< COE type error */
+#define EC_ERR_COE_SIZE    10 /**< COE size error */
+#define EC_ERR_COE_REQUEST 11 /**< COE request & index & subindex error */
+#define EC_ERR_COE_TOGGLE  12 /**< COE toggle error */
+#define EC_ERR_COE_ABORT   13 /**< COE abort error */
+#define EC_ERR_FOE_TYPE    14 /**< FOE type error */
+#define EC_ERR_FOE_SIZE    15 /**< FOE size error */
+#define EC_ERR_FOE_OPCODE  16 /**< FOE opcode error */
+#define EC_ERR_FOE_PACKNO  17 /**< FOE packet number error */
+
+#define EC_ERR_UNKNOWN     255
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_foe.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_foe.h
new file mode 100644
index 00000000..bdcd133c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_foe.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_FOE_H
+#define EC_FOE_H
+
+int ec_foe_write(ec_master_t *master,
+                 uint16_t slave_index,
+                 ec_datagram_t *datagram,
+                 const char *filename,
+                 uint32_t password,
+                 const void *buf,
+                 uint32_t size);
+
+int ec_foe_read(ec_master_t *master,
+                uint16_t slave_index,
+                ec_datagram_t *datagram,
+                const char *filename,
+                uint32_t password,
+                void *buf,
+                uint32_t maxsize,
+                uint32_t *size);
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_list.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_list.h
new file mode 100644
index 00000000..7778edb6
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_list.h
@@ -0,0 +1,468 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_LIST_H
+#define EC_LIST_H
+
+#include <string.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * ec_container_of - return the member address of ptr, if the type of ptr is the
+ * struct type.
+ */
+#define ec_container_of(ptr, type, member) \
+    ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
+
+/**
+ * Single List structure
+ */
+struct ec_slist_node {
+    struct ec_slist_node *next; /**< point to next node. */
+};
+typedef struct ec_slist_node ec_slist_t; /**< Type for single list. */
+
+/**
+ * @brief initialize a single list
+ *
+ * @param l the single list to be initialized
+ */
+static inline void ec_slist_init(ec_slist_t *l)
+{
+    l->next = NULL;
+}
+
+static inline void ec_slist_add_head(ec_slist_t *l, ec_slist_t *n)
+{
+    n->next = l->next;
+    l->next = n;
+}
+
+static inline void ec_slist_add_tail(ec_slist_t *l, ec_slist_t *n)
+{
+    ec_slist_t *tmp = l;
+
+    while (tmp->next) {
+        tmp = tmp->next;
+    }
+
+    /* append the node to the tail */
+    tmp->next = n;
+    n->next = NULL;
+}
+
+static inline void ec_slist_insert(ec_slist_t *l, ec_slist_t *next, ec_slist_t *n)
+{
+    if (!next) {
+        ec_slist_add_tail(next, l);
+        return;
+    }
+
+    while (l->next) {
+        if (l->next == next) {
+            l->next = n;
+            n->next = next;
+        }
+
+        l = l->next;
+    }
+}
+
+static inline ec_slist_t *ec_slist_remove(ec_slist_t *l, ec_slist_t *n)
+{
+    ec_slist_t *tmp = l;
+    /* remove slist head */
+    while (tmp->next && tmp->next != n) {
+        tmp = tmp->next;
+    }
+
+    /* remove node */
+    if (tmp->next != (ec_slist_t *)0) {
+        tmp->next = tmp->next->next;
+    }
+
+    return l;
+}
+
+static inline unsigned int ec_slist_len(const ec_slist_t *l)
+{
+    unsigned int len = 0;
+    const ec_slist_t *list = l->next;
+
+    while (list != NULL) {
+        list = list->next;
+        len++;
+    }
+
+    return len;
+}
+
+static inline unsigned int ec_slist_contains(ec_slist_t *l, ec_slist_t *n)
+{
+    while (l->next) {
+        if (l->next == n) {
+            return 0;
+        }
+
+        l = l->next;
+    }
+
+    return 1;
+}
+
+static inline ec_slist_t *ec_slist_head(ec_slist_t *l)
+{
+    return l->next;
+}
+
+static inline ec_slist_t *ec_slist_tail(ec_slist_t *l)
+{
+    while (l->next) {
+        l = l->next;
+    }
+
+    return l;
+}
+
+static inline ec_slist_t *ec_slist_next(ec_slist_t *n)
+{
+    return n->next;
+}
+
+static inline int ec_slist_isempty(ec_slist_t *l)
+{
+    return l->next == NULL;
+}
+
+/**
+ * @brief initialize a slist object
+ */
+#define EC_SLIST_OBJESCT_INIT(object) \
+    {                                 \
+        NULL                          \
+    }
+
+/**
+ * @brief initialize a slist object
+ */
+#define EC_SLIST_DEFINE(slist) \
+    ec_slist_t slist = { NULL }
+
+/**
+ * @brief get the struct for this single list node
+ * @param node the entry point
+ * @param type the type of structure
+ * @param member the name of list in structure
+ */
+#define ec_slist_entry(node, type, member) \
+    ec_container_of(node, type, member)
+
+/**
+ * ec_slist_first_entry - get the first element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define ec_slist_first_entry(ptr, type, member) \
+    ec_slist_entry((ptr)->next, type, member)
+
+/**
+ * ec_slist_tail_entry - get the tail element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define ec_slist_tail_entry(ptr, type, member) \
+    ec_slist_entry(ec_slist_tail(ptr), type, member)
+
+/**
+ * ec_slist_first_entry_or_null - get the first element from a slist
+ * @ptr:    the slist head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the slist_struct within the struct.
+ *
+ * Note, that slist is expected to be not empty.
+ */
+#define ec_slist_first_entry_or_null(ptr, type, member) \
+    (ec_slist_isempty(ptr) ? NULL : ec_slist_first_entry(ptr, type, member))
+
+/**
+ * ec_slist_for_each - iterate over a single list
+ * @pos:    the ec_slist_t * to use as a loop cursor.
+ * @head:   the head for your single list.
+ */
+#define ec_slist_for_each(pos, head) \
+    for (pos = (head)->next; pos != NULL; pos = pos->next)
+
+#define ec_slist_for_each_safe(pos, next, head)    \
+    for (pos = (head)->next, next = pos->next; pos; \
+         pos = next, next = pos->next)
+
+/**
+ * ec_slist_for_each_entry  -   iterate over single list of given type
+ * @pos:    the type * to use as a loop cursor.
+ * @head:   the head for your single list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define ec_slist_for_each_entry(pos, head, member)                 \
+    for (pos = ec_slist_entry((head)->next, typeof(*pos), member); \
+         &pos->member != (NULL);                                    \
+         pos = ec_slist_entry(pos->member.next, typeof(*pos), member))
+
+#define ec_slist_for_each_entry_safe(pos, n, head, member)          \
+    for (pos = ec_slist_entry((head)->next, typeof(*pos), member),  \
+        n = ec_slist_entry(pos->member.next, typeof(*pos), member); \
+         &pos->member != (NULL);                                     \
+         pos = n, n = ec_slist_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * Double List structure
+ */
+struct ec_dlist_node {
+    struct ec_dlist_node *next; /**< point to next node. */
+    struct ec_dlist_node *prev; /**< point to prev node. */
+};
+typedef struct ec_dlist_node ec_dlist_t; /**< Type for lists. */
+
+/**
+ * @brief initialize a list
+ *
+ * @param l list to be initialized
+ */
+static inline void ec_dlist_init(ec_dlist_t *l)
+{
+    l->next = l->prev = l;
+}
+
+/**
+ * @brief insert a node after a list
+ *
+ * @param l list to insert it
+ * @param n new node to be inserted
+ */
+static inline void ec_dlist_add_head(ec_dlist_t *l, ec_dlist_t *n)
+{
+    l->next->prev = n;
+    n->next = l->next;
+
+    l->next = n;
+    n->prev = l;
+}
+
+/**
+ * @brief insert a node before a list
+ *
+ * @param n new node to be inserted
+ * @param l list to insert it
+ */
+static inline void ec_dlist_add_tail(ec_dlist_t *l, ec_dlist_t *n)
+{
+    l->prev->next = n;
+    n->prev = l->prev;
+
+    l->prev = n;
+    n->next = l;
+}
+
+/**
+ * @brief remove node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void ec_dlist_remove(ec_dlist_t *n)
+{
+    n->next->prev = n->prev;
+    n->prev->next = n->next;
+
+    n->next = n->prev = n;
+}
+
+/**
+ * @brief move node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void ec_dlist_move_head(ec_dlist_t *l, ec_dlist_t *n)
+{
+    ec_dlist_remove(n);
+    ec_dlist_add_head(l, n);
+}
+
+/**
+ * @brief move node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void ec_dlist_move_tail(ec_dlist_t *l, ec_dlist_t *n)
+{
+    ec_dlist_remove(n);
+    ec_dlist_add_tail(l, n);
+}
+
+/**
+ * @brief tests whether a list is empty
+ * @param l the list to test.
+ */
+static inline int ec_dlist_isempty(const ec_dlist_t *l)
+{
+    return l->next == l;
+}
+
+/**
+ * @brief get the list length
+ * @param l the list to get.
+ */
+static inline unsigned int ec_dlist_len(const ec_dlist_t *l)
+{
+    unsigned int len = 0;
+    const ec_dlist_t *p = l;
+
+    while (p->next != l) {
+        p = p->next;
+        len++;
+    }
+
+    return len;
+}
+
+/**
+ * @brief remove and init list
+ * @param n the list to get.
+ */
+static inline void ec_dlist_del_init(ec_dlist_t *n)
+{
+    ec_dlist_remove(n);
+}
+
+/**
+ * @brief initialize a dlist object
+ */
+#define EC_DLIST_OBJESCT_INIT(object) \
+    {                                 \
+        &(object), &(object)          \
+    }
+/**
+ * @brief initialize a dlist object
+ */
+#define EC_DLIST_DEFINE(list) \
+    ec_dlist_t list = { &(list), &(list) }
+
+/**
+ * @brief get the struct for this entry
+ * @param node the entry point
+ * @param type the type of structure
+ * @param member the name of list in structure
+ */
+#define ec_dlist_entry(node, type, member) \
+    ec_container_of(node, type, member)
+
+/**
+ * dlist_first_entry - get the first element from a list
+ * @ptr:    the list head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define ec_dlist_first_entry(ptr, type, member) \
+    ec_dlist_entry((ptr)->next, type, member)
+/**
+ * dlist_first_entry_or_null - get the first element from a list
+ * @ptr:    the list head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define ec_dlist_first_entry_or_null(ptr, type, member) \
+    (ec_dlist_isempty(ptr) ? NULL : ec_dlist_first_entry(ptr, type, member))
+
+/**
+ * ec_dlist_for_each - iterate over a list
+ * @pos:    the ec_dlist_t * to use as a loop cursor.
+ * @head:   the head for your list.
+ */
+#define ec_dlist_for_each(pos, head) \
+    for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ * ec_dlist_for_each_prev - iterate over a list
+ * @pos:    the dlist_t * to use as a loop cursor.
+ * @head:   the head for your list.
+ */
+#define ec_dlist_for_each_prev(pos, head) \
+    for (pos = (head)->prev; pos != (head); pos = pos->prev)
+
+/**
+ * ec_dlist_for_each_safe - iterate over a list safe against removal of list entry
+ * @pos:    the dlist_t * to use as a loop cursor.
+ * @n:      another dlist_t * to use as temporary storage
+ * @head:   the head for your list.
+ */
+#define ec_dlist_for_each_safe(pos, n, head)              \
+    for (pos = (head)->next, n = pos->next; pos != (head); \
+         pos = n, n = pos->next)
+
+#define ec_dlist_for_each_prev_safe(pos, n, head)         \
+    for (pos = (head)->prev, n = pos->prev; pos != (head); \
+         pos = n, n = pos->prev)
+/**
+ * ec_dlist_for_each_entry  -   iterate over list of given type
+ * @pos:    the type * to use as a loop cursor.
+ * @head:   the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define ec_dlist_for_each_entry(pos, head, member)                 \
+    for (pos = ec_dlist_entry((head)->next, typeof(*pos), member); \
+         &pos->member != (head);                                    \
+         pos = ec_dlist_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * ec_dlist_for_each_entry_reverse  -   iterate over list of given type
+ * @pos:    the type * to use as a loop cursor.
+ * @head:   the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define ec_dlist_for_each_entry_reverse(pos, head, member)         \
+    for (pos = ec_dlist_entry((head)->prev, typeof(*pos), member); \
+         &pos->member != (head);                                    \
+         pos = ec_dlist_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * ec_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos:    the type * to use as a loop cursor.
+ * @n:      another type * to use as temporary storage
+ * @head:   the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define ec_dlist_for_each_entry_safe(pos, n, head, member)          \
+    for (pos = ec_dlist_entry((head)->next, typeof(*pos), member),  \
+        n = ec_dlist_entry(pos->member.next, typeof(*pos), member); \
+         &pos->member != (head);                                     \
+         pos = n, n = ec_dlist_entry(n->member.next, typeof(*n), member))
+
+/**
+ * ec_dlist_for_each_entry_safe_reverse - iterate over list of given type safe against removal of list entry
+ * @pos:    the type * to use as a loop cursor.
+ * @n:      another type * to use as temporary storage
+ * @head:   the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define ec_dlist_for_each_entry_safe_reverse(pos, n, head, member)  \
+    for (pos = ec_dlist_entry((head)->prev, typeof(*pos), field),   \
+        n = ec_dlist_entry(pos->member.prev, typeof(*pos), member); \
+         &pos->member != (head);                                     \
+         pos = n, n = ec_dlist_entry(pos->member.prev, typeof(*pos), member))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EC_LIST_H */
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_log.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_log.h
new file mode 100644
index 00000000..5f4c48a7
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_log.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_LOG_H
+#define EC_LOG_H
+
+#include <stdio.h>
+
+/* DEBUG level */
+#define EC_DBG_ERROR   0
+#define EC_DBG_WARNING 1
+#define EC_DBG_INFO    2
+#define EC_DBG_LOG     3
+
+#ifndef EC_DBG_TAG
+#define EC_DBG_TAG "EC"
+#endif
+/*
+ * The color for terminal (foreground)
+ * BLACK    30
+ * RED      31
+ * GREEN    32
+ * YELLOW   33
+ * BLUE     34
+ * PURPLE   35
+ * CYAN     36
+ * WHITE    37
+ */
+
+#define ec_master_dbg_log_line(lvl, color_n, fmt, ...)          \
+    do {                                                        \
+        CONFIG_EC_PRINTF("\033[" #color_n "m[" lvl "/ec_master" \
+                         "] ");                                 \
+        CONFIG_EC_PRINTF(fmt, ##__VA_ARGS__);                   \
+        CONFIG_EC_PRINTF("\033[0m");                            \
+    } while (0)
+
+#define ec_slave_dbg_log_line(lvl, color_n, fmt, ...)          \
+    do {                                                       \
+        CONFIG_EC_PRINTF("\033[" #color_n "m[" lvl "/ec_slave" \
+                         "] ");                                \
+        CONFIG_EC_PRINTF(fmt, ##__VA_ARGS__);                  \
+        CONFIG_EC_PRINTF("\033[0m");                           \
+    } while (0)
+
+#if (CONFIG_EC_DBG_LEVEL >= EC_DBG_LOG)
+#define EC_LOG_DBG(fmt, ...) ec_master_dbg_log_line("D", 0, fmt, ##__VA_ARGS__)
+#else
+#define EC_LOG_DBG(...) \
+    {                   \
+    }
+#endif
+
+#if (CONFIG_EC_DBG_LEVEL >= EC_DBG_INFO)
+#define EC_LOG_INFO(fmt, ...) ec_master_dbg_log_line("I", 32, fmt, ##__VA_ARGS__)
+#else
+#define EC_LOG_INFO(...) \
+    {                    \
+    }
+#endif
+
+#if (CONFIG_EC_DBG_LEVEL >= EC_DBG_WARNING)
+#define EC_LOG_WRN(fmt, ...) ec_master_dbg_log_line("W", 33, fmt, ##__VA_ARGS__)
+#else
+#define EC_LOG_WRN(...) \
+    {                   \
+    }
+#endif
+
+#if (CONFIG_EC_DBG_LEVEL >= EC_DBG_ERROR)
+#define EC_LOG_ERR(fmt, ...) ec_master_dbg_log_line("E", 31, fmt, ##__VA_ARGS__)
+#else
+#define EC_LOG_ERR(...) \
+    {                   \
+    }
+#endif
+
+#if (CONFIG_EC_SLAVE_DBG_LEVEL >= EC_DBG_LOG)
+#define EC_SLAVE_LOG_DBG(fmt, ...) ec_slave_dbg_log_line("D", 0, fmt, ##__VA_ARGS__)
+#else
+#define EC_SLAVE_LOG_DBG(...) \
+    {                         \
+    }
+#endif
+
+#if (CONFIG_EC_SLAVE_DBG_LEVEL >= EC_DBG_INFO)
+#define EC_SLAVE_LOG_INFO(fmt, ...) ec_slave_dbg_log_line("I", 32, fmt, ##__VA_ARGS__)
+#else
+#define EC_SLAVE_LOG_INFO(...) \
+    {                          \
+    }
+#endif
+
+#if (CONFIG_EC_SLAVE_DBG_LEVEL >= EC_DBG_WARNING)
+#define EC_SLAVE_LOG_WRN(fmt, ...) ec_slave_dbg_log_line("W", 33, fmt, ##__VA_ARGS__)
+#else
+#define EC_SLAVE_LOG_WRN(...) \
+    {                         \
+    }
+#endif
+
+#if (CONFIG_EC_SLAVE_DBG_LEVEL >= EC_DBG_ERROR)
+#define EC_SLAVE_LOG_ERR(fmt, ...) ec_slave_dbg_log_line("E", 31, fmt, ##__VA_ARGS__)
+#else
+#define EC_SLAVE_LOG_ERR(...) \
+    {                         \
+    }
+#endif
+
+#define EC_LOG_RAW(...) CONFIG_EC_PRINTF(__VA_ARGS__)
+
+#ifndef CONFIG_EC_ASSERT_DISABLE
+#define EC_ASSERT(f)                                                            \
+    do {                                                                        \
+        if (!(f)) {                                                             \
+            EC_LOG_ERR("ASSERT FAIL [%s] @ %s:%d\r\n", #f, __FILE__, __LINE__); \
+            while (1) {                                                         \
+            }                                                                   \
+        }                                                                       \
+    } while (false)
+
+#define EC_ASSERT_MSG(f, fmt, ...)                                              \
+    do {                                                                        \
+        if (!(f)) {                                                             \
+            EC_LOG_ERR("ASSERT FAIL [%s] @ %s:%d\r\n", #f, __FILE__, __LINE__); \
+            EC_LOG_ERR(fmt "\r\n", ##__VA_ARGS__);                              \
+            while (1) {                                                         \
+            }                                                                   \
+        }                                                                       \
+    } while (false)
+#else
+#define EC_ASSERT(f) \
+    {                \
+    }
+#define EC_ASSERT_MSG(f, fmt, ...) \
+    {                              \
+    }
+#endif
+
+#define ___is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+static inline void ec_hexdump(const void *ptr, uint32_t buflen)
+{
+    unsigned char *buf = (unsigned char *)ptr;
+    unsigned int i, j;
+
+    (void)buf;
+
+    for (i = 0; i < buflen; i += 16) {
+        CONFIG_EC_PRINTF("%08x:", i);
+
+        for (j = 0; j < 16; j++)
+            if (i + j < buflen) {
+                if ((j % 8) == 0) {
+                    CONFIG_EC_PRINTF("  ");
+                }
+
+                CONFIG_EC_PRINTF("%02X ", buf[i + j]);
+            } else
+                CONFIG_EC_PRINTF("   ");
+        CONFIG_EC_PRINTF(" ");
+
+        for (j = 0; j < 16; j++)
+            if (i + j < buflen)
+                CONFIG_EC_PRINTF("%c", ___is_print(buf[i + j]) ? buf[i + j] : '.');
+        CONFIG_EC_PRINTF("\n");
+    }
+}
+
+#endif /* EC_LOG_H */
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_mailbox.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_mailbox.h
new file mode 100644
index 00000000..43079d8e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_mailbox.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_MAILBOX_H
+#define EC_MAILBOX_H
+
+uint8_t *ec_mailbox_fill_send(ec_master_t *master,
+                              uint16_t slave_index,
+                              ec_datagram_t *datagram,
+                              uint8_t type,
+                              uint16_t size);
+int ec_mailbox_send(ec_master_t *master,
+                    uint16_t slave_index,
+                    ec_datagram_t *datagram);
+int ec_mailbox_read_status(ec_master_t *master,
+                           uint16_t slave_index,
+                           ec_datagram_t *datagram,
+                           uint32_t timeout_us);
+int ec_mailbox_receive(ec_master_t *master,
+                       uint16_t slave_index,
+                       ec_datagram_t *datagram,
+                       uint8_t *type,
+                       uint32_t *size,
+                       uint32_t timeout_us);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_master.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_master.h
new file mode 100644
index 00000000..4432e13e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_master.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_MASTER_H
+#define EC_MASTER_H
+
+#include <stdbool.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "ec_config.h"
+#include "ec_util.h"
+#include "ec_list.h"
+#include "ec_errno.h"
+#include "ec_log.h"
+#include "esc_register.h"
+#include "ec_def.h"
+#include "ec_osal.h"
+#include "ec_port.h"
+#include "ec_datagram.h"
+#include "ec_common.h"
+#include "ec_sii.h"
+#include "ec_slave.h"
+#include "ec_mailbox.h"
+#include "ec_coe.h"
+#include "ec_cmd.h"
+#include "ec_perf.h"
+#include "ec_timestamp.h"
+#include "ec_version.h"
+#include "ec_foe.h"
+
+/** Netdev statistics.
+ */
+typedef struct {
+    uint64_t tx_count;                     /**< Number of frames sent. */
+    uint64_t last_tx_count;                /**< Number of frames sent of last statistics cycle. */
+    uint64_t rx_count;                     /**< Number of frames received. */
+    uint64_t last_rx_count;                /**< Number of frames received of last statistics cycle. */
+    uint64_t tx_bytes;                     /**< Number of bytes sent. */
+    uint64_t last_tx_bytes;                /**< Number of bytes sent of last statistics cycle. */
+    uint64_t rx_bytes;                     /**< Number of bytes received. */
+    uint64_t last_rx_bytes;                /**< Number of bytes received of last statistics cycle. */
+    uint64_t last_loss;                    /**< Tx/Rx difference of last statistics cycle. */
+    int32_t tx_frame_rates[EC_RATE_COUNT]; /**< Transmit rates in frames/s for different statistics cycle periods.*/
+    int32_t rx_frame_rates[EC_RATE_COUNT]; /**< Receive rates in frames/s for different statistics cycle periods.*/
+    int32_t tx_byte_rates[EC_RATE_COUNT];  /**< Transmit rates in byte/s for different statistics cycle periods. */
+    int32_t rx_byte_rates[EC_RATE_COUNT];  /**< Receive rates in byte/s for different statistics cycle periods. */
+    int32_t loss_rates[EC_RATE_COUNT];     /**< Frame loss rates for different statistics cycle periods. */
+    uint64_t last_jiffies;                 /**< Jiffies of last statistic cycle. */
+} ec_netdev_stats_t;
+
+/** Cyclic statistics.
+ */
+typedef struct {
+    unsigned int timeouts;        /**< datagram timeouts */
+    unsigned int corrupted;       /**< corrupted frames */
+    unsigned int unmatched;       /**< unmatched datagrams (received, but not queued any longer) */
+    unsigned long output_jiffies; /**< time of last output */
+} ec_stats_t;
+
+typedef enum {
+    EC_ORPHANED, /**< Orphaned phase. The master has no Ethernet device attached. */
+    EC_IDLE,     /**< Idle phase. An Ethernet device is attached, but the master is not in use, yet. */
+    EC_OPERATION /**< Operation phase. The master was requested by a realtime application. */
+} ec_master_phase_t;
+
+typedef struct {
+    ec_dlist_t queue;
+    ec_datagram_t datagrams[CONFIG_EC_MAX_NETDEVS];
+#if CONFIG_EC_MAX_NETDEVS > 1
+    uint8_t *send_buffer;
+#endif
+    uint32_t expected_working_counter;
+    ec_slave_t *slave;
+} ec_pdo_datagram_t;
+
+typedef struct ec_master {
+    uint8_t index;
+    ec_netdev_t *netdev[CONFIG_EC_MAX_NETDEVS];
+    bool link_state[CONFIG_EC_MAX_NETDEVS];
+    uint32_t slaves_responding[CONFIG_EC_MAX_NETDEVS];
+    ec_slave_state_t slaves_state[CONFIG_EC_MAX_NETDEVS];
+    ec_netdev_stats_t netdev_stats;
+    ec_stats_t stats;
+    ec_master_phase_t phase;
+    bool active;    /**< Master is started. */
+    bool scan_done; /**< Slave scan is done. */
+
+    ec_datagram_t main_datagram; /**< Main datagram for slave scan & state change & config & sii */
+
+    ec_dlist_t datagram_queue;     /**< Queue of pending datagrams*/
+    ec_dlist_t pdo_datagram_queue; /**< Queue of pdo datagrams*/
+    uint8_t datagram_index;
+
+    ec_slave_t *dc_ref_clock;                /**< DC reference clock slave. */
+    ec_datagram_t dc_ref_sync_datagram;      /**< Datagram used for synchronizing the reference clock to the master clock. */
+    ec_datagram_t dc_all_sync_datagram;      /**< Datagram used for synchronizing all slaves to the dc ref clock. */
+    ec_datagram_t systime_diff_mon_datagram; /**< Datagram used for reading the system time difference between master and reference clock. */
+
+    uint32_t min_systime_diff;
+    uint32_t max_systime_diff;
+    uint32_t curr_systime_diff;
+    uint32_t systime_diff_count;
+    uint64_t total_systime_diff;
+    bool systime_diff_enable;
+
+    uint64_t interval;
+
+    ec_slave_t *slaves;
+    uint32_t slave_count;
+
+#ifdef CONFIG_EC_PERF_ENABLE
+    ec_perf_t perf;
+#endif
+
+    ec_osal_mutex_t scan_lock;
+    ec_osal_thread_t scan_thread;
+    ec_osal_thread_t nonperiod_thread;
+    ec_osal_sem_t nonperiod_sem;
+    struct ec_osal_timer *linkdetect_timer;
+    bool nonperiod_suspend;
+
+    uint8_t pdo_buffer[CONFIG_EC_MAX_NETDEVS][CONFIG_EC_MAX_PDO_BUFSIZE];
+    uint32_t actual_pdo_size;
+    uint32_t expected_working_counter;
+    uint32_t actual_working_counter;
+} ec_master_t;
+
+int ec_master_init(ec_master_t *master, uint8_t master_index);
+void ec_master_deinit(ec_master_t *master);
+int ec_master_start(ec_master_t *master, uint32_t period_us);
+int ec_master_stop(ec_master_t *master);
+int ec_master_queue_ext_datagram(ec_master_t *master, ec_datagram_t *datagram, bool wakep_poll, bool waiter);
+uint8_t *ec_master_get_slave_domain(ec_master_t *master, uint32_t slave_index);
+uint8_t *ec_master_get_slave_domain_output(ec_master_t *master, uint32_t slave_index);
+uint8_t *ec_master_get_slave_domain_input(ec_master_t *master, uint32_t slave_index);
+uint32_t ec_master_get_slave_domain_size(ec_master_t *master, uint32_t slave_index);
+uint32_t ec_master_get_slave_domain_osize(ec_master_t *master, uint32_t slave_index);
+uint32_t ec_master_get_slave_domain_isize(ec_master_t *master, uint32_t slave_index);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_netdev.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_netdev.h
new file mode 100644
index 00000000..2641b4f2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_netdev.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_NETDEV_H
+#define EC_NETDEV_H
+
+#include "phy/chry_phy.h"
+
+typedef struct ec_master ec_master_t;
+
+typedef struct ec_netdev {
+    ec_master_t *master;
+    struct chry_phy_device phydev;
+    uint8_t index;
+    char name[20];
+    uint8_t mac_addr[6];
+    bool link_state;
+    uint8_t tx_frame_index;
+    unsigned long jiffies_poll;
+
+    // Frame statistics
+    uint64_t tx_count;                     /**< Number of frames sent. */
+    uint64_t last_tx_count;                /**< Number of frames sent of last statistics cycle.*/
+    uint64_t rx_count;                     /**< Number of frames received. */
+    uint64_t last_rx_count;                /**< Number of frames received of last statistics cycle.*/
+    uint64_t tx_bytes;                     /**< Number of bytes sent. */
+    uint64_t last_tx_bytes;                /**< Number of bytes sent of last statistics cycle.*/
+    uint64_t rx_bytes;                     /**< Number of bytes received. */
+    uint64_t last_rx_bytes;                /**< Number of bytes received of last statistics cycle.*/
+    uint64_t tx_errors;                    /**< Number of transmit errors. */
+    int32_t tx_frame_rates[EC_RATE_COUNT]; /**< Transmit rates in frames/s for different statistics cycle periods.*/
+    int32_t rx_frame_rates[EC_RATE_COUNT]; /**< Receive rates in frames/s for different statistics cycle periods.*/
+    int32_t tx_byte_rates[EC_RATE_COUNT];  /**< Transmit rates in byte/s for different statistics cycle periods.*/
+    int32_t rx_byte_rates[EC_RATE_COUNT];  /**< Receive rates in byte/s for different statistics cycle periods.*/
+
+} ec_netdev_t;
+
+void ec_netdev_clear_stats(ec_netdev_t *netdev);
+void ec_netdev_update_stats(ec_netdev_t *netdev);
+
+ec_netdev_t *ec_netdev_init(uint8_t netdev_index);
+void ec_netdev_poll_link_state(ec_netdev_t *netdev);
+uint8_t *ec_netdev_get_txbuf(ec_netdev_t *netdev);
+int ec_netdev_send(ec_netdev_t *netdev, uint32_t size);
+void ec_netdev_receive(ec_netdev_t *netdev, uint8_t *frame, uint32_t size);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_osal.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_osal.h
new file mode 100644
index 00000000..618fae7e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_osal.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_OSAL_H
+#define EC_OSAL_H
+
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+
+#ifdef __INCLUDE_NUTTX_CONFIG_H
+#define CONFIG_EC_OSAL_THREAD_SET_ARGV int argc, char **argv
+#define CONFIG_EC_OSAL_THREAD_GET_ARGV ((uintptr_t)strtoul(argv[1], NULL, 16))
+#elif defined(__ZEPHYR__)
+#define CONFIG_EC_OSAL_THREAD_SET_ARGV void *p1, void *p2, void *p3
+#define CONFIG_EC_OSAL_THREAD_GET_ARGV ((uintptr_t)p1)
+#else
+#define CONFIG_EC_OSAL_THREAD_SET_ARGV void *argument
+#define CONFIG_EC_OSAL_THREAD_GET_ARGV ((uintptr_t)argument)
+#endif
+
+#define EC_OSAL_WAITING_FOREVER (0xFFFFFFFFU)
+
+typedef void *ec_osal_thread_t;
+typedef void *ec_osal_sem_t;
+typedef void *ec_osal_mutex_t;
+typedef void (*ec_thread_entry_t)(CONFIG_EC_OSAL_THREAD_SET_ARGV);
+typedef void (*ec_timer_handler_t)(void *argument);
+struct ec_osal_timer {
+    ec_timer_handler_t handler;
+    void *argument;
+    bool is_period;
+    uint32_t timeout_ms;
+    void *timer;
+};
+
+/*
+ * Task with smaller priority value indicates higher task priority
+*/
+ec_osal_thread_t ec_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, ec_thread_entry_t entry, void *args);
+void ec_osal_thread_delete(ec_osal_thread_t thread);
+void ec_osal_thread_suspend(ec_osal_thread_t thread);
+void ec_osal_thread_resume(ec_osal_thread_t thread);
+
+ec_osal_sem_t ec_osal_sem_create(uint32_t max_count, uint32_t initial_count);
+void ec_osal_sem_delete(ec_osal_sem_t sem);
+int ec_osal_sem_take(ec_osal_sem_t sem, uint32_t timeout);
+int ec_osal_sem_give(ec_osal_sem_t sem);
+void ec_osal_sem_reset(ec_osal_sem_t sem);
+
+ec_osal_mutex_t ec_osal_mutex_create(void);
+void ec_osal_mutex_delete(ec_osal_mutex_t mutex);
+int ec_osal_mutex_take(ec_osal_mutex_t mutex);
+int ec_osal_mutex_give(ec_osal_mutex_t mutex);
+
+struct ec_osal_timer *ec_osal_timer_create(const char *name, uint32_t timeout_ms, ec_timer_handler_t handler, void *argument, bool is_period);
+void ec_osal_timer_delete(struct ec_osal_timer *timer);
+void ec_osal_timer_start(struct ec_osal_timer *timer);
+void ec_osal_timer_stop(struct ec_osal_timer *timer);
+
+size_t ec_osal_enter_critical_section(void);
+void ec_osal_leave_critical_section(size_t flag);
+
+void ec_osal_msleep(uint32_t delay);
+
+void *ec_osal_malloc(size_t size);
+void ec_osal_free(void *ptr);
+
+#endif /* EC_OSAL_H */
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_perf.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_perf.h
new file mode 100644
index 00000000..2ad471ea
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_perf.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_PERF_H
+#define EC_PERF_H
+
+typedef struct {
+    bool enable;    // Enable performance measurement
+    uint64_t count; // Current measurement count
+
+    uint64_t min_interval;    // Minimum interval
+    uint64_t max_interval;    // Maximum interval
+    int64_t min_jitter;       // Minimum jitter
+    int64_t max_jitter;       // Maximum jitter
+    uint64_t total_interval;  // Total interval time
+    int64_t total_jitter;     // Total jitter (for average calculation)
+
+    uint32_t ignore_count;      // Number of ignored measurements
+    uint64_t last_timestamp;    // Last interrupt timestamp
+    uint64_t expected_interval; // Expected interrupt interval
+} ec_perf_t;
+
+void ec_perf_init(ec_perf_t *perf, uint64_t expected_interval_us);
+void ec_perf_polling(ec_perf_t *perf);
+bool ec_perf_is_complete(ec_perf_t *perf);
+void ec_perf_print_statistics(ec_perf_t *perf);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_port.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_port.h
new file mode 100644
index 00000000..d0c504be
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_port.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_PORT_H
+#define EC_PORT_H
+
+#include "ec_netdev.h"
+
+typedef void (*ec_htimer_cb)(void *arg);
+
+ec_netdev_t *ec_netdev_low_level_init(uint8_t netdev_index);
+#ifndef CONFIG_EC_PHY_CUSTOM
+void ec_netdev_low_level_link_up(ec_netdev_t *netdev, struct chry_phy_status *status);
+#else
+void ec_netdev_low_level_poll_link_state(ec_netdev_t *netdev);
+#endif
+uint8_t *ec_netdev_low_level_get_txbuf(ec_netdev_t *netdev);
+int ec_netdev_low_level_output(ec_netdev_t *netdev, uint32_t size);
+int ec_netdev_low_level_input(ec_netdev_t *netdev);
+
+void ec_mdio_low_level_write(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum, uint16_t val);
+uint16_t ec_mdio_low_level_read(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum);
+
+void ec_htimer_start(uint32_t us, ec_htimer_cb cb, void *arg);
+void ec_htimer_stop(void);
+
+uint32_t ec_get_cpu_frequency(void);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_sii.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_sii.h
new file mode 100644
index 00000000..74b44d8f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_sii.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_SII_H
+#define EC_SII_H
+
+typedef struct ec_slave ec_slave_t;
+
+typedef struct ec_sii {
+    // Non-category data
+    uint16_t aliasaddr;              /**< Configured station alias. */
+    uint32_t vendor_id;              /**< Vendor ID. */
+    uint32_t product_code;           /**< Vendor-specific product code. */
+    uint32_t revision_number;        /**< Revision number. */
+    uint32_t serial_number;          /**< Serial number. */
+    uint16_t boot_rx_mailbox_offset; /**< Bootstrap receive mailbox address. */
+    uint16_t boot_rx_mailbox_size;   /**< Bootstrap receive mailbox size. */
+    uint16_t boot_tx_mailbox_offset; /**< Bootstrap transmit mailbox address. */
+    uint16_t boot_tx_mailbox_size;   /**< Bootstrap transmit mailbox size. */
+    uint16_t std_rx_mailbox_offset;  /**< Standard receive mailbox address. */
+    uint16_t std_rx_mailbox_size;    /**< Standard receive mailbox size. */
+    uint16_t std_tx_mailbox_offset;  /**< Standard transmit mailbox address. */
+    uint16_t std_tx_mailbox_size;    /**< Standard transmit mailbox size. */
+    uint16_t mailbox_protocols;      /**< Supported mailbox protocols. */
+
+    // General
+    ec_sii_general_t general;
+    bool has_general;
+
+    // Strings
+    char **strings;        /**< Strings in SII categories. */
+    uint32_t string_count; /**< Number of SII strings. */
+} ec_sii_t;
+
+int ec_sii_read(ec_master_t *master, uint16_t slave_index, ec_datagram_t *datagram, uint16_t woffset, uint32_t *buf, uint32_t len);
+int ec_sii_write(ec_master_t *master, uint16_t slave_index, ec_datagram_t *datagram, uint16_t woffset, const uint16_t *buf, uint32_t len);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_slave.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_slave.h
new file mode 100644
index 00000000..6c34d6b2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_slave.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_SALVE_H
+#define EC_SALVE_H
+
+typedef struct ec_master ec_master_t;
+typedef struct ec_slave ec_slave_t;
+
+typedef struct
+{
+    ec_direction_t dir;
+    uint32_t logical_start_address;
+    uint32_t data_size;
+} ec_fmmu_info_t;
+
+typedef struct {
+    uint16_t physical_start_address;
+    uint16_t length;
+    uint8_t control;
+    uint8_t enable;
+    ec_pdo_assign_t pdo_assign;
+    ec_pdo_mapping_t pdo_mapping[CONFIG_EC_PER_SM_MAX_PDOS];
+    ec_fmmu_info_t fmmu;
+    bool fmmu_enable;
+} ec_sm_info_t;
+
+typedef struct {
+    ec_sync_info_t *sync;                           /**< Sync manager configuration. */
+    uint8_t sync_count;                             /**< Number of sync managers. */
+    uint16_t dc_assign_activate;                    /**< dc assign control */
+    ec_sync_signal_t dc_sync[EC_SYNC_SIGNAL_COUNT]; /**< DC sync signals. */
+} ec_slave_config_t;
+
+/** EtherCAT slave port descriptor.
+ */
+typedef enum {
+    EC_PORT_NOT_IMPLEMENTED, /**< Port is not implemented. */
+    EC_PORT_NOT_CONFIGURED,  /**< Port is not configured. */
+    EC_PORT_EBUS,            /**< Port is an E-Bus. */
+    EC_PORT_MII              /**< Port is a MII. */
+} ec_slave_port_desc_t;
+
+/** EtherCAT slave port information.
+ */
+typedef struct {
+    uint8_t link_up;         /**< Link detected. */
+    uint8_t loop_closed;     /**< Loop closed. */
+    uint8_t signal_detected; /**< Detected signal on RX port. */
+} ec_slave_port_link_t;
+
+typedef struct {
+    ec_slave_port_desc_t desc; /**< Port descriptors. */
+    ec_slave_port_link_t link; /**< Port link status. */
+    ec_slave_t *next_slave;    /**< Connected slaves. */
+    uint32_t receive_time;     /**< Port receive times for delay measurement. */
+    uint32_t delay_to_next_dc; /**< Delay to next slave with DC support behind this port [ns]. */
+} ec_slave_port_t;
+
+typedef struct ec_slave {
+    uint32_t index;               /**< Index of the slave in the master slave array. */
+    ec_master_t *master;          /**< Master owning the slave. */
+    ec_netdev_index_t netdev_idx; /**< Index of device the slave responds on. */
+
+    uint16_t autoinc_address; /**< Auto-increment address. */
+    uint16_t station_address; /**< Configured station address. */
+    uint16_t effective_alias; /**< Effective alias address. */
+
+    ec_slave_port_t ports[EC_MAX_PORTS]; /**< Port information. */
+
+    ec_slave_state_t requested_state; /**< Requested application state. */
+    ec_slave_state_t current_state;   /**< Current application state. */
+    uint32_t alstatus_code;           /**< Error code in AL Status register. */
+    bool force_update;                /**< Force update of the slave. */
+
+    uint16_t configured_rx_mailbox_offset; /**< Configured receive mailbox offset. */
+    uint16_t configured_rx_mailbox_size;   /**< Configured receive mailbox size.*/
+    uint16_t configured_tx_mailbox_offset; /**< Configured send mailbox offset. */
+    uint16_t configured_tx_mailbox_size;   /**< Configured send mailbox size. */
+
+    uint8_t base_type;                 /**< Slave type. */
+    uint8_t base_revision;             /**< Revision. */
+    uint16_t base_build;               /**< Build number. */
+    uint8_t base_fmmu_count;           /**< Number of supported FMMUs. */
+    uint8_t base_sync_count;           /**< Number of supported sync managers. */
+    uint8_t base_fmmu_bit_operation;   /**< FMMU bit operation is supported. */
+    uint8_t base_dc_supported;         /**< Distributed clocks are supported. */
+    ec_slave_dc_range_t base_dc_range; /**< DC range. */
+    uint8_t has_dc_system_time;        /**< The slave supports the DC system time register. Otherwise it can only be used for delay measurement. */
+    uint32_t transmission_delay;       /**< DC system time transmission delay (offset from reference clock). */
+
+    uint32_t logical_start_address;
+    uint32_t odata_size;
+    uint32_t idata_size;
+    uint32_t expected_working_counter;
+    uint32_t actual_working_counter;
+
+    uint16_t *sii_image; /**< Complete SII image. */
+    size_t sii_nwords;   /**< Size of the SII contents in words. */
+
+    ec_sii_t sii; /**< Extracted SII data. */
+
+    ec_sm_info_t sm_info[EC_MAX_SYNC_MANAGERS];
+    uint8_t sm_count; /**< Number of sync managers. */
+
+    ec_slave_config_t *config; /**< Slave custom configuration. */
+} ec_slave_t;
+
+void ec_slaves_scanning(ec_master_t *master);
+char *ec_slave_get_sii_string(const ec_slave_t *slave, uint32_t index);
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_timestamp.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_timestamp.h
new file mode 100644
index 00000000..6af7af55
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_timestamp.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_TIMESTAMP_H
+#define EC_TIMESTAMP_H
+
+void ec_timestamp_init(void);
+uint64_t ec_timestamp_get_time_ns(void);
+uint64_t ec_timestamp_get_time_us(void);
+
+#define jiffies ec_timestamp_get_time_us()
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_util.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_util.h
new file mode 100644
index 00000000..97e8a792
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_util.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_UTIL_H
+#define EC_UTIL_H
+
+#if defined(__CC_ARM)
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+#define __PACKED_UNION __packed union
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#elif defined(__GNUC__)
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+#define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__)
+#if (__VER__ >= 8000000)
+#define __ICCARM_V8 1
+#else
+#define __ICCARM_V8 0
+#endif
+
+#ifndef __USED
+#if defined(__ICCARM_V8) || defined(__ICCRISCV__)
+#define __USED __attribute__((used))
+#else
+#define __USED __root
+#endif
+#endif
+
+#ifndef __WEAK
+#if defined(__ICCARM_V8) || defined(__ICCRISCV__)
+#define __WEAK __attribute__((weak))
+#else
+#define __WEAK _Pragma("__weak")
+#endif
+#endif
+
+#ifndef __PACKED
+#if defined(__ICCARM_V8) || defined(__ICCRISCV__)
+#define __PACKED __attribute__((packed, aligned(1)))
+#else
+/* Needs IAR language extensions */
+#define __PACKED __packed
+#endif
+#endif
+
+#ifndef __PACKED_STRUCT
+#if defined(__ICCARM_V8) || defined(__ICCRISCV__)
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#else
+/* Needs IAR language extensions */
+#define __PACKED_STRUCT __packed struct
+#endif
+#endif
+
+#ifndef __PACKED_UNION
+#if defined(__ICCARM_V8) || defined(__ICCRISCV__)
+#define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#else
+/* Needs IAR language extensions */
+#define __PACKED_UNION __packed union
+#endif
+#endif
+
+#ifndef __ALIGNED
+#if defined(__ICCARM_V8) || defined(__ICCRISCV__)
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#elif (__VER__ >= 7080000)
+/* Needs IAR language extensions */
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#else
+#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#endif
+
+#endif
+
+#ifndef MAX
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define EC_ALIGN_UP(size, align) (((size) + (align)-1) & ~((align)-1))
+
+#define EC_WRITE_U8(DATA, VAL)                   \
+    do {                                         \
+        *((uint8_t *)(DATA)) = ((uint8_t)(VAL)); \
+    } while (0)
+
+#define EC_WRITE_U16(DATA, VAL)                    \
+    do {                                           \
+        *((uint16_t *)(DATA)) = ((uint16_t)(VAL)); \
+    } while (0)
+
+#define EC_WRITE_U32(DATA, VAL)                    \
+    do {                                           \
+        *((uint32_t *)(DATA)) = ((uint32_t)(VAL)); \
+    } while (0)
+
+#define EC_WRITE_U64(DATA, VAL)                    \
+    do {                                           \
+        *((uint64_t *)(DATA)) = ((uint64_t)(VAL)); \
+    } while (0)
+
+#define EC_READ_U8(DATA) \
+    ((uint8_t) * ((uint8_t *)(DATA)))
+
+#define EC_READ_U16(DATA) \
+    ((uint16_t) * ((uint16_t *)(DATA)))
+
+#define EC_READ_U32(DATA) \
+    ((uint32_t) * ((uint32_t *)(DATA)))
+
+#define EC_READ_U64(DATA) \
+    ((uint64_t) * ((uint64_t *)(DATA)))
+
+#define ec_htons(A) ((((uint16_t)(A)&0xff00) >> 8) | \
+                     (((uint16_t)(A)&0x00ff) << 8))
+#define ec_htonl(A) ((((uint32_t)(A)&0xff000000) >> 24) | \
+                     (((uint32_t)(A)&0x00ff0000) >> 8) |  \
+                     (((uint32_t)(A)&0x0000ff00) << 8) |  \
+                     (((uint32_t)(A)&0x000000ff) << 24))
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_version.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_version.h
new file mode 100644
index 00000000..b0afffe8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_version.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef EC_VERSION_H
+#define EC_VERSION_H
+
+#define CHERRYECAT_VERSION     0x000100
+#define CHERRYECAT_VERSION_STR "v0.1.0"
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/esc_register.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/esc_register.h
new file mode 100644
index 00000000..9760549b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/esc_register.h
@@ -0,0 +1,4552 @@
+/*
+ * Copyright (c) 2021-2025 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#ifndef ESC_REGISTER_H
+#define ESC_REGISTER_H
+
+#define __R volatile const /* Define "read-only" permission */
+#define __RW volatile      /* Define "read-write" permission */
+#define __W volatile       /* Define "write-only" permission */
+
+typedef struct {
+    __R  uint8_t  TYPE;                        /* 0x0: Type of EtherCAT controller */
+    __R  uint8_t  REVISION;                    /* 0x1: Revision of EtherCAT controller */
+    __R  uint16_t BUILD;                       /* 0x2: Build of EtherCAT controller */
+    __R  uint8_t  FMMU_NUM;                    /* 0x4: FMMU supported */
+    __R  uint8_t  SYNCM_NUM;                   /* 0x5: SyncManagers supported */
+    __R  uint8_t  RAM_SIZE;                    /* 0x6: RAM Size */
+    __R  uint8_t  PORT_DESC;                   /* 0x7: Port Descriptor */
+    __R  uint16_t FEATURE;                     /* 0x8: ESC Feature supported */
+    __R  uint8_t  RESERVED0[6];                /* 0xA - 0xF: Reserved */
+    __R  uint16_t STATION_ADDR;                /* 0x10: Configured Station Address */
+    __RW uint16_t STATION_ALS;                 /* 0x12: Configured Station Alias */
+    __R  uint8_t  RESERVED1[12];               /* 0x14 - 0x1F: Reserved */
+    __R  uint8_t  REG_WEN;                     /* 0x20: Register Write Enable */
+    __R  uint8_t  REG_WP;                      /* 0x21: Register Write Protection */
+    __R  uint8_t  RESERVED2[14];               /* 0x22 - 0x2F: Reserved */
+    __R  uint8_t  ESC_WEN;                     /* 0x30: ESC Write Enable */
+    __R  uint8_t  ESC_WP;                      /* 0x31: ESC Write Protection */
+    __R  uint8_t  RESERVED3[14];               /* 0x32 - 0x3F: Reserved */
+    __R  uint8_t  ESC_RST_ECAT;                /* 0x40: ESC Reset ECAT */
+    __RW uint8_t  ESC_RST_PDI;                 /* 0x41: ESC Reset PDI */
+    __R  uint8_t  RESERVED4[190];              /* 0x42 - 0xFF: Reserved */
+    __R  uint32_t ESC_DL_CTRL;                 /* 0x100: ESC DL Control */
+    __R  uint8_t  RESERVED5[4];                /* 0x104 - 0x107: Reserved */
+    __R  uint16_t PHYSICAL_RW_OFFSET;          /* 0x108: Physical Read/Write Offset */
+    __R  uint8_t  RESERVED6[6];                /* 0x10A - 0x10F: Reserved */
+    __R  uint16_t ESC_DL_STAT;                 /* 0x110: ESC DL Status */
+    __R  uint8_t  RESERVED7[14];               /* 0x112 - 0x11F: Reserved */
+    __RW uint16_t AL_CTRL;                     /* 0x120: AL Control */
+    __R  uint8_t  RESERVED8[14];               /* 0x122 - 0x12F: Reserved */
+    __RW uint16_t AL_STAT;                     /* 0x130: AL Status */
+    __R  uint8_t  RESERVED9[2];                /* 0x132 - 0x133: Reserved */
+    __RW uint16_t AL_STAT_CODE;                /* 0x134: AL Status Code */
+    __R  uint8_t  RESERVED10[2];               /* 0x136 - 0x137: Reserved */
+    __RW uint8_t  RUN_LED_OVRD;                /* 0x138: RUN LED Override */
+    __RW uint8_t  ERR_LED_OVRD;                /* 0x139: ERR LED Override */
+    __R  uint8_t  RESERVED11[6];               /* 0x13A - 0x13F: Reserved */
+    __R  uint8_t  PDI_CTRL;                    /* 0x140: PDI Control */
+    __R  uint8_t  ESC_CFG;                     /* 0x141: ESC Configuration */
+    __R  uint8_t  RESERVED12[12];              /* 0x142 - 0x14D: Reserved */
+    __R  uint16_t PDI_INFO;                    /* 0x14E: PDI Information */
+    __R  uint8_t  PDI_CFG;                     /* 0x150: PDI Configuration */
+    __R  uint8_t  PDI_SL_CFG;                  /* 0x151: PDI Sync/Latch[1:0] Configuration */
+    __RW uint16_t PDI_EXT_CFG;                 /* 0x152: PDI Extended Configuration */
+    __R  uint8_t  RESERVED13[172];             /* 0x154 - 0x1FF: Reserved */
+    __R  uint16_t ECAT_EVT_MSK;                /* 0x200: ECAT Event Mask */
+    __R  uint8_t  RESERVED14[2];               /* 0x202 - 0x203: Reserved */
+    __RW uint32_t PDI_AL_EVT_MSK;              /* 0x204: PDI AL Event Mask */
+    __R  uint8_t  RESERVED15[8];               /* 0x208 - 0x20F: Reserved */
+    __R  uint16_t ECAT_EVT_REQ;                /* 0x210: ECAT Event Request */
+    __R  uint8_t  RESERVED16[14];              /* 0x212 - 0x21F: Reserved */
+    __R  uint32_t AL_EVT_REQ;                  /* 0x220: AL Event Request */
+    __R  uint8_t  RESERVED17[220];             /* 0x224 - 0x2FF: Reserved */
+    __R  uint16_t RX_ERR_CNT[4];               /* 0x300 - 0x306: RX Error Counter */
+    __R  uint8_t  FWD_RX_ERR_CNT[4];           /* 0x308 - 0x30B: Forwarded RX Error Counter */
+    __R  uint8_t  ECAT_PU_ERR_CNT;             /* 0x30C: ECAT Processing Unit Error Counter */
+    __R  uint8_t  PDI_ERR_CNT;                 /* 0x30D: PDI Error Counter */
+    __R  uint8_t  RESERVED18[2];               /* 0x30E - 0x30F: Reserved */
+    __R  uint8_t  LOST_LINK_CNT[4];            /* 0x310 - 0x313: Lost Link Counter */
+    __R  uint8_t  RESERVED19[236];             /* 0x314 - 0x3FF: Reserved */
+    __R  uint16_t WDG_DIV;                     /* 0x400: Watchdog Divider */
+    __R  uint8_t  RESERVED20[14];              /* 0x402 - 0x40F: Reserved */
+    __R  uint16_t WDG_TIME_PDI;                /* 0x410: Watchdog Time PDI */
+    __R  uint8_t  RESERVED21[14];              /* 0x412 - 0x41F: Reserved */
+    __R  uint16_t WDG_TIME_PDAT;               /* 0x420: Watchdog Time Process Data */
+    __R  uint8_t  RESERVED22[30];              /* 0x422 - 0x43F: Reserved */
+    __RW uint16_t WDG_STAT_PDAT;               /* 0x440: Watchdog Status Process Data */
+    __R  uint8_t  WDG_CNT_PDAT;                /* 0x442: Watchdog Counter Process Data */
+    __R  uint8_t  WDG_CNT_PDI;                 /* 0x443: Watchdog Counter PDI */
+    __R  uint8_t  RESERVED23[188];             /* 0x444 - 0x4FF: Reserved */
+    __R  uint8_t  EEPROM_CFG;                  /* 0x500: EEPROM Configuration */
+    __RW uint8_t  EEPROM_PDI_ACC_STAT;         /* 0x501: EEPROM PDI Access State */
+    __RW uint16_t EEPROM_CTRL_STAT;            /* 0x502: EEPROM Control/Status */
+    __RW uint32_t EEPROM_ADDR;                 /* 0x504: EEPROM Address */
+    __RW uint64_t EEPROM_DATA;                 /* 0x508: EEPROM Data */
+    __RW uint16_t MII_MNG_CS;                  /* 0x510: MII Management Control/Status */
+    __RW uint8_t  PHY_ADDR;                    /* 0x512: PHY Address */
+    __RW uint8_t  PHY_REG_ADDR;                /* 0x513: PHY Register Address */
+    __RW uint16_t PHY_DATA;                    /* 0x514: PHY Data */
+    __R  uint8_t  MIIM_ECAT_ACC_STAT;          /* 0x516: MII Management ECAT Access State */
+    __RW uint8_t  MIIM_PDI_ACC_STAT;           /* 0x517: MII Management PDI Access State */
+    __RW uint8_t  PHY_STAT[4];                 /* 0x518 - 0x51B: PHY Port */
+    __R  uint8_t  RESERVED24[228];             /* 0x51C - 0x5FF: Reserved */
+    struct {
+        __R  uint32_t LOGIC_START_ADDR;        /* 0x600: Logical Start Address */
+        __R  uint16_t LENGTH;                  /* 0x604: Length */
+        __R  uint8_t  LOGIC_START_BIT;         /* 0x606: Logical Start Bit */
+        __R  uint8_t  LOGIC_STOP_BIT;          /* 0x607: Logical Stop Bit */
+        __R  uint16_t PHYSICAL_START_ADDR;     /* 0x608: Physical Start Address */
+        __R  uint8_t  PHYSICAL_START_BIT;      /* 0x60A: Physical Start Bit */
+        __R  uint8_t  TYPE;                    /* 0x60B: Type */
+        __R  uint8_t  ACTIVATE;                /* 0x60C: Activate */
+        __R  uint8_t  RESERVED0[3];            /* 0x60D - 0x60F: Reserved */
+    } FMMU[8];
+    __R  uint8_t  RESERVED25[384];             /* 0x680 - 0x7FF: Reserved */
+    struct {
+        __R  uint16_t PHYSICAL_START_ADDR;     /* 0x800: Physical Start Address */
+        __R  uint16_t LENGTH;                  /* 0x802: Length */
+        __R  uint8_t  CONTROL;                 /* 0x804: Control */
+        __R  uint8_t  STATUS;                  /* 0x805: Status */
+        __RW uint8_t  ACTIVATE;                /* 0x806: Activate */
+        __RW uint8_t  PDI_CTRL;                /* 0x807: PDI Control */
+    } SYNCM[8];
+    __R  uint8_t  RESERVED26[192];             /* 0x840 - 0x8FF: Reserved */
+    __R  uint32_t RCV_TIME[4];                 /* 0x900 - 0x90C: Receive Time */
+    __RW uint64_t SYS_TIME;                    /* 0x910: System Time */
+    __R  uint64_t RCVT_ECAT_PU;                /* 0x918: Receive Time ECAT Processing Unit */
+    __RW uint64_t SYS_TIME_OFFSET;             /* 0x920: System Time Offset */
+    __RW uint32_t SYS_TIME_DELAY;              /* 0x928: System Time Delay */
+    __R  uint32_t SYS_TIME_DIFF;               /* 0x92C: System Time Difference */
+    __RW uint16_t SPD_CNT_START;               /* 0x930: Speed Counter Start */
+    __R  uint16_t SPD_CNT_DIFF;                /* 0x932: Speed Counter Diff */
+    __RW uint8_t  SYS_TIME_DIFF_FD;            /* 0x934: System Time Difference Filter Depth */
+    __RW uint8_t  SPD_CNT_FD;                  /* 0x935: Speed Counter Filter Depth */
+    __R  uint8_t  RCV_TIME_LM;                 /* 0x936: Receive Time Latch Mode */
+    __R  uint8_t  RESERVED27[73];              /* 0x937 - 0x97F: Reserved */
+    __R  uint8_t  CYC_UNIT_CTRL;               /* 0x980: Cyclic Unit Control */
+    __RW uint8_t  SYNCO_ACT;                   /* 0x981: SYNC Out Unit Activation */
+    __R  uint16_t PULSE_LEN;                   /* 0x982: Pulse Length of SyncSignals */
+    __R  uint8_t  ACT_STAT;                    /* 0x984: Activation Status */
+    __R  uint8_t  RESERVED28[9];               /* 0x985 - 0x98D: Reserved */
+    __RW uint8_t  SYNC0_STAT;                  /* 0x98E: SYNC0 Status */
+    __RW uint8_t  SYNC1_STAT;                  /* 0x98F: SYNC1 Status */
+    __RW uint64_t START_TIME_CO;               /* 0x990: Start Time Cyclic Operation */
+    __R  uint64_t NXT_SYNC1_PULSE;             /* 0x998: Next SYNC1 Pulse */
+    __RW uint32_t SYNC0_CYC_TIME;              /* 0x9A0: SYNC0 Cycle Time */
+    __RW uint32_t SYNC1_CYC_TIME;              /* 0x9A4: SYNC1 Cycle Time */
+    __RW uint8_t  LATCH0_CTRL;                 /* 0x9A8: Latch0 Control */
+    __RW uint8_t  LATCH1_CTRL;                 /* 0x9A9: Latch1 Control */
+    __R  uint8_t  RESERVED29[4];               /* 0x9AA - 0x9AD: Reserved */
+    __R  uint8_t  LATCH0_STAT;                 /* 0x9AE: Latch0 Status */
+    __R  uint8_t  LATCH1_STAT;                 /* 0x9AF: Latch1 Status */
+    __RW uint64_t LATCH0_TIME_PE;              /* 0x9B0: Latch0 Time Positive Edge */
+    __RW uint64_t LATCH0_TIME_NE;              /* 0x9B8: Latch0 Time Negative Edge */
+    __RW uint64_t LATCH1_TIME_PE;              /* 0x9C0: Latch1 Time Positive Edge */
+    __RW uint64_t LATCH1_TIME_NE;              /* 0x9C8: Latch1 Time Negative Edge */
+    __R  uint8_t  RESERVED30[32];              /* 0x9D0 - 0x9EF: Reserved */
+    __R  uint32_t ECAT_BUF_CET;                /* 0x9F0: EtherCAT Buffer Change Event Time */
+    __R  uint8_t  RESERVED31[4];               /* 0x9F4 - 0x9F7: Reserved */
+    __R  uint32_t PDI_BUF_SET;                 /* 0x9F8: PDI Buffer Start Event Time */
+    __R  uint32_t PDI_BUF_CET;                 /* 0x9FC: PDI Buffer Change Event Time */
+    __R  uint8_t  RESERVED32[1024];            /* 0xA00 - 0xDFF: Reserved */
+    __R  uint64_t PID;                         /* 0xE00: Product ID */
+    __R  uint64_t VID;                         /* 0xE08: Vendor ID */
+    __R  uint8_t  RESERVED33[240];             /* 0xE10 - 0xEFF: Reserved */
+    __R  uint32_t DIO_OUT_DATA;                /* 0xF00: Digital I/O Output Data */
+    __R  uint8_t  RESERVED34[12];              /* 0xF04 - 0xF0F: Reserved */
+    __RW uint64_t GPO;                         /* 0xF10: General Purpose Outputs */
+    __R  uint64_t GPI;                         /* 0xF18: General Purpose Inputs */
+    __R  uint8_t  RESERVED35[96];              /* 0xF20 - 0xF7F: Reserved */
+    __RW uint8_t  USER_RAM_BYTE0;              /* 0xF80: User Ram Byte 0 */
+    __RW uint8_t  USER_RAM_BYTE1;              /* 0xF81: User Ram Byte 1 */
+    __RW uint8_t  USER_RAM_BYTE2;              /* 0xF82: User Ram Byte 2 */
+    __RW uint8_t  USER_RAM_BYTE3;              /* 0xF83: User Ram Byte 3 */
+    __RW uint8_t  USER_RAM_BYTE4;              /* 0xF84: User Ram Byte 4 */
+    __RW uint8_t  USER_RAM_BYTE5;              /* 0xF85: User Ram Byte 5 */
+    __RW uint8_t  USER_RAM_BYTE6;              /* 0xF86: User Ram Byte 6 */
+    __RW uint8_t  USER_RAM_BYTE7;              /* 0xF87: User Ram Byte 7 */
+    __RW uint8_t  USER_RAM_BYTE8;              /* 0xF88: User Ram Byte 8 */
+    __RW uint8_t  USER_RAM_BYTE9;              /* 0xF89: User Ram Byte 9 */
+    __RW uint8_t  USER_RAM_BYTE10;             /* 0xF8A: User Ram Byte 10 */
+    __RW uint8_t  USER_RAM_BYTE11;             /* 0xF8B: User Ram Byte 11 */
+    __R  uint8_t  RESERVED36[2];               /* 0xF8C - 0xF8D: Reserved */
+    __RW uint8_t  USER_RAM_BYTE14;             /* 0xF8E: User Ram Byte 14 */
+    __RW uint8_t  USER_RAM_BYTE15;             /* 0xF8F: User Ram Byte 15 */
+    __R  uint8_t  RESERVED37[3];               /* 0xF90 - 0xF92: Reserved */
+    __RW uint8_t  USER_RAM_BYTE19;             /* 0xF93: User Ram Byte 19 */
+    __R  uint8_t  RESERVED38[108];             /* 0xF94 - 0xFFF: Reserved */
+    __RW uint32_t PDRAM;                       /* 0x1000: Process Data Ram */
+    __R  uint8_t  RESERVED39[61436];           /* 0x1004 - 0xFFFF: Reserved */
+    __RW uint32_t PDRAM_ALS;                   /* 0x10000: Process Data Ram Alias */
+    __R  uint8_t  RESERVED40[61436];           /* 0x10004 - 0x1EFFF: Reserved */
+    __RW uint32_t GPR_CFG0;                    /* 0x1F000: General Purpose Configure 0 */
+    __RW uint32_t GPR_CFG1;                    /* 0x1F004: General Purpose Configure 1 */
+    __RW uint32_t GPR_CFG2;                    /* 0x1F008: General Purpose Configure 2 */
+    __R  uint8_t  RESERVED41[4];               /* 0x1F00C - 0x1F00F: Reserved */
+    __RW uint32_t PHY_CFG0;                    /* 0x1F010: PHY Configure 0 */
+    __RW uint32_t PHY_CFG1;                    /* 0x1F014: PHY Configure 1 */
+    __R  uint8_t  RESERVED42[8];               /* 0x1F018 - 0x1F01F: Reserved */
+    __RW uint32_t GPIO_CTRL;                   /* 0x1F020: GPIO Output Enable */
+    __R  uint8_t  RESERVED43[12];              /* 0x1F024 - 0x1F02F: Reserved */
+    __RW uint32_t GPI_OVERRIDE0;               /* 0x1F030: GPI low word Override value */
+    __RW uint32_t GPI_OVERRIDE1;               /* 0x1F034: GPI high word Override value */
+    __R  uint32_t GPO_REG0;                    /* 0x1F038: GPO low word read value */
+    __R  uint32_t GPO_REG1;                    /* 0x1F03C: GPO high word read value */
+    __R  uint32_t GPI_REG0;                    /* 0x1F040: GPI low word read value */
+    __R  uint32_t GPI_REG1;                    /* 0x1F044: GPI high word read value */
+    __R  uint8_t  RESERVED44[24];              /* 0x1F048 - 0x1F05F: Reserved */
+    __R  uint32_t GPR_STATUS;                  /* 0x1F060: global status register */
+    __R  uint8_t  RESERVED45[28];              /* 0x1F064 - 0x1F07F: Reserved */
+    __RW uint32_t IO_CFG[9];                   /* 0x1F080 - 0x1F0A0: CTR IO Configure */
+} ESC_t;
+
+#define ESCREG_BASE (0x00000000UL) /* Base address of ESC peripheral */
+#define ESCREG      ((ESC_t *) ESCREG_BASE) /* Pointer to ESC peripheral */
+#define ESCREG_OF(n) ((size_t)&(n)) /* offset of ESC peripheral */
+
+/* Bitfield definition for register: TYPE */
+/*
+ * TYPE (RO)
+ *
+ * Controller type
+ */
+#define ESC_TYPE_TYPE_MASK (0xFFU)
+#define ESC_TYPE_TYPE_SHIFT (0U)
+#define ESC_TYPE_TYPE_GET(x) (((uint8_t)(x) & ESC_TYPE_TYPE_MASK) >> ESC_TYPE_TYPE_SHIFT)
+
+/* Bitfield definition for register: REVISION */
+/*
+ * X (RO)
+ *
+ * major version X
+ */
+#define ESC_REVISION_X_MASK (0xFFU)
+#define ESC_REVISION_X_SHIFT (0U)
+#define ESC_REVISION_X_GET(x) (((uint8_t)(x) & ESC_REVISION_X_MASK) >> ESC_REVISION_X_SHIFT)
+
+/* Bitfield definition for register: BUILD */
+/*
+ * BUILD (RO)
+ *
+ */
+#define ESC_BUILD_BUILD_MASK (0xFF00U)
+#define ESC_BUILD_BUILD_SHIFT (8U)
+#define ESC_BUILD_BUILD_GET(x) (((uint16_t)(x) & ESC_BUILD_BUILD_MASK) >> ESC_BUILD_BUILD_SHIFT)
+
+/*
+ * Y (RO)
+ *
+ * minor version Y
+ */
+#define ESC_BUILD_Y_MASK (0xF0U)
+#define ESC_BUILD_Y_SHIFT (4U)
+#define ESC_BUILD_Y_GET(x) (((uint16_t)(x) & ESC_BUILD_Y_MASK) >> ESC_BUILD_Y_SHIFT)
+
+/*
+ * Z (RO)
+ *
+ * maintenance version Z
+ */
+#define ESC_BUILD_Z_MASK (0xFU)
+#define ESC_BUILD_Z_SHIFT (0U)
+#define ESC_BUILD_Z_GET(x) (((uint16_t)(x) & ESC_BUILD_Z_MASK) >> ESC_BUILD_Z_SHIFT)
+
+/* Bitfield definition for register: FMMU_NUM */
+/*
+ * NUM (RO)
+ *
+ * Number of supported FMMU channels (or entities)
+ */
+#define ESC_FMMU_NUM_NUM_MASK (0xFFU)
+#define ESC_FMMU_NUM_NUM_SHIFT (0U)
+#define ESC_FMMU_NUM_NUM_GET(x) (((uint8_t)(x) & ESC_FMMU_NUM_NUM_MASK) >> ESC_FMMU_NUM_NUM_SHIFT)
+
+/* Bitfield definition for register: SYNCM_NUM */
+/*
+ * NUM (RO)
+ *
+ * Number of supported SyncManager channels (or entities)
+ */
+#define ESC_SYNCM_NUM_NUM_MASK (0xFFU)
+#define ESC_SYNCM_NUM_NUM_SHIFT (0U)
+#define ESC_SYNCM_NUM_NUM_GET(x) (((uint8_t)(x) & ESC_SYNCM_NUM_NUM_MASK) >> ESC_SYNCM_NUM_NUM_SHIFT)
+
+/* Bitfield definition for register: RAM_SIZE */
+/*
+ * SIZE (RO)
+ *
+ * Process Data RAM size supported in KByte
+ */
+#define ESC_RAM_SIZE_SIZE_MASK (0xFFU)
+#define ESC_RAM_SIZE_SIZE_SHIFT (0U)
+#define ESC_RAM_SIZE_SIZE_GET(x) (((uint8_t)(x) & ESC_RAM_SIZE_SIZE_MASK) >> ESC_RAM_SIZE_SIZE_SHIFT)
+
+/* Bitfield definition for register: PORT_DESC */
+/*
+ * PORT3 (RO)
+ *
+ * Port configuration:
+ * 00:Not implemented
+ * 01:Not configured (SII EEPROM)
+ * 10:EBUS
+ * 11:MII/RMII/RGMII
+ */
+#define ESC_PORT_DESC_PORT3_MASK (0xC0U)
+#define ESC_PORT_DESC_PORT3_SHIFT (6U)
+#define ESC_PORT_DESC_PORT3_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT3_MASK) >> ESC_PORT_DESC_PORT3_SHIFT)
+
+/*
+ * PORT2 (RO)
+ *
+ * Port configuration:
+ * 00:Not implemented
+ * 01:Not configured (SII EEPROM)
+ * 10:EBUS
+ * 11:MII/RMII/RGMII
+ */
+#define ESC_PORT_DESC_PORT2_MASK (0x30U)
+#define ESC_PORT_DESC_PORT2_SHIFT (4U)
+#define ESC_PORT_DESC_PORT2_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT2_MASK) >> ESC_PORT_DESC_PORT2_SHIFT)
+
+/*
+ * PORT1 (RO)
+ *
+ * Port configuration:
+ * 00:Not implemented
+ * 01:Not configured (SII EEPROM)
+ * 10:EBUS
+ * 11:MII/RMII/RGMII
+ */
+#define ESC_PORT_DESC_PORT1_MASK (0xCU)
+#define ESC_PORT_DESC_PORT1_SHIFT (2U)
+#define ESC_PORT_DESC_PORT1_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT1_MASK) >> ESC_PORT_DESC_PORT1_SHIFT)
+
+/*
+ * PORT0 (RO)
+ *
+ * Port configuration:
+ * 00:Not implemented
+ * 01:Not configured (SII EEPROM)
+ * 10:EBUS
+ * 11:MII/RMII/RGMII
+ */
+#define ESC_PORT_DESC_PORT0_MASK (0x3U)
+#define ESC_PORT_DESC_PORT0_SHIFT (0U)
+#define ESC_PORT_DESC_PORT0_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT0_MASK) >> ESC_PORT_DESC_PORT0_SHIFT)
+
+/* Bitfield definition for register: FEATURE */
+/*
+ * FFSC (RO)
+ *
+ * Fixed FMMU/SyncManager configuration:
+ * 0:Variable configuration
+ * 1:Fixed configuration (refer to documentation of supporting ESCs)
+ */
+#define ESC_FEATURE_FFSC_MASK (0x800U)
+#define ESC_FEATURE_FFSC_SHIFT (11U)
+#define ESC_FEATURE_FFSC_GET(x) (((uint16_t)(x) & ESC_FEATURE_FFSC_MASK) >> ESC_FEATURE_FFSC_SHIFT)
+
+/*
+ * RWC (RO)
+ *
+ * EtherCAT read/write command support(BRW,APRW,FPRW):
+ * 0:Supported
+ * 1:Not supported
+ */
+#define ESC_FEATURE_RWC_MASK (0x400U)
+#define ESC_FEATURE_RWC_SHIFT (10U)
+#define ESC_FEATURE_RWC_GET(x) (((uint16_t)(x) & ESC_FEATURE_RWC_MASK) >> ESC_FEATURE_RWC_SHIFT)
+
+/*
+ * LRW (RO)
+ *
+ * EtherCAT LRW command support:
+ * 0:Supported
+ * 1:Not supported
+ */
+#define ESC_FEATURE_LRW_MASK (0x200U)
+#define ESC_FEATURE_LRW_SHIFT (9U)
+#define ESC_FEATURE_LRW_GET(x) (((uint16_t)(x) & ESC_FEATURE_LRW_MASK) >> ESC_FEATURE_LRW_SHIFT)
+
+/*
+ * EDSA (RO)
+ *
+ * Enhanced DC SYNC Activation:
+ * 0:Not available
+ * 1:Available
+ * Note:This feature refers to registers 0x981[7:3] and 0x0984
+ */
+#define ESC_FEATURE_EDSA_MASK (0x100U)
+#define ESC_FEATURE_EDSA_SHIFT (8U)
+#define ESC_FEATURE_EDSA_GET(x) (((uint16_t)(x) & ESC_FEATURE_EDSA_MASK) >> ESC_FEATURE_EDSA_SHIFT)
+
+/*
+ * SHFE (RO)
+ *
+ * Seperate Handling of FCS Errors:
+ * 0:Not supported
+ * 1:Supported, frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter
+ */
+#define ESC_FEATURE_SHFE_MASK (0x80U)
+#define ESC_FEATURE_SHFE_SHIFT (7U)
+#define ESC_FEATURE_SHFE_GET(x) (((uint16_t)(x) & ESC_FEATURE_SHFE_MASK) >> ESC_FEATURE_SHFE_SHIFT)
+
+/*
+ * ELDM (RO)
+ *
+ * Enhanced Link Detection MII:
+ * 0:Not available
+ * 1:Available
+ */
+#define ESC_FEATURE_ELDM_MASK (0x40U)
+#define ESC_FEATURE_ELDM_SHIFT (6U)
+#define ESC_FEATURE_ELDM_GET(x) (((uint16_t)(x) & ESC_FEATURE_ELDM_MASK) >> ESC_FEATURE_ELDM_SHIFT)
+
+/*
+ * DCW (RO)
+ *
+ * Distributed Clocks width:
+ * 0:32 bit
+ * 1:64 bit
+ */
+#define ESC_FEATURE_DCW_MASK (0x8U)
+#define ESC_FEATURE_DCW_SHIFT (3U)
+#define ESC_FEATURE_DCW_GET(x) (((uint16_t)(x) & ESC_FEATURE_DCW_MASK) >> ESC_FEATURE_DCW_SHIFT)
+
+/*
+ * DC (RO)
+ *
+ * Distributed Clocks:
+ * 0:Not available
+ * 1:Available
+ */
+#define ESC_FEATURE_DC_MASK (0x4U)
+#define ESC_FEATURE_DC_SHIFT (2U)
+#define ESC_FEATURE_DC_GET(x) (((uint16_t)(x) & ESC_FEATURE_DC_MASK) >> ESC_FEATURE_DC_SHIFT)
+
+/*
+ * FMMU (RO)
+ *
+ * FMMU Operation:
+ * 0:Bit oriented
+ * 1:Byte oriented
+ */
+#define ESC_FEATURE_FMMU_MASK (0x1U)
+#define ESC_FEATURE_FMMU_SHIFT (0U)
+#define ESC_FEATURE_FMMU_GET(x) (((uint16_t)(x) & ESC_FEATURE_FMMU_MASK) >> ESC_FEATURE_FMMU_SHIFT)
+
+/* Bitfield definition for register: STATION_ADDR */
+/*
+ * ADDR (RO)
+ *
+ * Address used for node addressing
+ * (FPRD/FPWR/FPRW/FRMW commands)
+ */
+#define ESC_STATION_ADDR_ADDR_MASK (0xFFFFU)
+#define ESC_STATION_ADDR_ADDR_SHIFT (0U)
+#define ESC_STATION_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_STATION_ADDR_ADDR_MASK) >> ESC_STATION_ADDR_ADDR_SHIFT)
+
+/* Bitfield definition for register: STATION_ALS */
+/*
+ * ADDR (RW)
+ *
+ * Alias Address used for node addressing
+ * (FPRD/FPWR/FPRW/FRMW commands).
+ * The use of this alias is activated by Register
+ * DL Control Bit 0x0100[24].
+ * NOTE:EEPROM value is only transferred into this
+ * register at first EEPROM load after power-on or
+ * reset.
+ * ESC20 exception:EEPROM value is transferred
+ * into this register after each EEPROM reload
+ * command.
+ */
+#define ESC_STATION_ALS_ADDR_MASK (0xFFFFU)
+#define ESC_STATION_ALS_ADDR_SHIFT (0U)
+#define ESC_STATION_ALS_ADDR_SET(x) (((uint16_t)(x) << ESC_STATION_ALS_ADDR_SHIFT) & ESC_STATION_ALS_ADDR_MASK)
+#define ESC_STATION_ALS_ADDR_GET(x) (((uint16_t)(x) & ESC_STATION_ALS_ADDR_MASK) >> ESC_STATION_ALS_ADDR_SHIFT)
+
+/* Bitfield definition for register: REG_WEN */
+/*
+ * EN (RO)
+ *
+ * If register write protection is enabled, this
+ * register has to be written in the same
+ * Ethernet frame (value does not matter)
+ * before other writes to this station are allowed.
+ * This bit is self-clearing at the beginning of the
+ * next frame (SOF), or if Register Write
+ * Protection is disabled.
+ */
+#define ESC_REG_WEN_EN_MASK (0x1U)
+#define ESC_REG_WEN_EN_SHIFT (0U)
+#define ESC_REG_WEN_EN_GET(x) (((uint8_t)(x) & ESC_REG_WEN_EN_MASK) >> ESC_REG_WEN_EN_SHIFT)
+
+/* Bitfield definition for register: REG_WP */
+/*
+ * WP (RO)
+ *
+ * Register write protection:
+ * 0:Protection disabled
+ * 1:Protection enabled
+ * Registers 0x0000:0x0F7F are write-protected,
+ * except for 0x0020 and 0x0030
+ */
+#define ESC_REG_WP_WP_MASK (0x1U)
+#define ESC_REG_WP_WP_SHIFT (0U)
+#define ESC_REG_WP_WP_GET(x) (((uint8_t)(x) & ESC_REG_WP_WP_MASK) >> ESC_REG_WP_WP_SHIFT)
+
+/* Bitfield definition for register: ESC_WEN */
+/*
+ * EN (RO)
+ *
+ * If ESC write protection is enabled, this
+ * register has to be written in the same
+ * Ethernet frame (value does not matter)
+ * before other writes to this station are allowed.
+ * This bit is self-clearing at the beginning of the
+ * next frame (SOF), or if ESC Write Protection
+ * is disabled.
+ */
+#define ESC_ESC_WEN_EN_MASK (0x1U)
+#define ESC_ESC_WEN_EN_SHIFT (0U)
+#define ESC_ESC_WEN_EN_GET(x) (((uint8_t)(x) & ESC_ESC_WEN_EN_MASK) >> ESC_ESC_WEN_EN_SHIFT)
+
+/* Bitfield definition for register: ESC_WP */
+/*
+ * WP (RO)
+ *
+ * Write protect:
+ * 0:Protection disabled
+ * 1:Protection enabled
+ * All areas are write-protected, except for 0x0030.
+ */
+#define ESC_ESC_WP_WP_MASK (0x1U)
+#define ESC_ESC_WP_WP_SHIFT (0U)
+#define ESC_ESC_WP_WP_GET(x) (((uint8_t)(x) & ESC_ESC_WP_WP_MASK) >> ESC_ESC_WP_WP_SHIFT)
+
+/* Bitfield definition for register: ESC_RST_ECAT */
+/*
+ * PR (RO)
+ *
+ * Progress of the reset procedure:
+ * 00:initial/reset state
+ * 01:after writing 0x52 ('R'), when previous
+ * state was 00
+ * 10:after writing 0x45 ('E'), when previous
+ * state was 01
+ * 11:after writing 0x53 ('S'), when previous
+ * state was 10.
+ * This value must not be observed
+ * because the ESC enters reset when this
+ * state is reached, resulting in state 00
+ */
+#define ESC_ESC_RST_ECAT_PR_MASK (0x3U)
+#define ESC_ESC_RST_ECAT_PR_SHIFT (0U)
+#define ESC_ESC_RST_ECAT_PR_GET(x) (((uint8_t)(x) & ESC_ESC_RST_ECAT_PR_MASK) >> ESC_ESC_RST_ECAT_PR_SHIFT)
+
+/* Bitfield definition for register: ESC_RST_PDI */
+/*
+ * RST (RW)
+ *
+ * A reset is asserted after writing the reset
+ * sequence 0x52 ('R'), 0x45 ('E') and 0x53 ('S')
+ * in this register with 3 consecutive commands.
+ * Any other command which does not continue
+ * the sequence by writing the next expected
+ * value will cancel the reset procedure
+ */
+#define ESC_ESC_RST_PDI_RST_MASK (0xFFU)
+#define ESC_ESC_RST_PDI_RST_SHIFT (0U)
+#define ESC_ESC_RST_PDI_RST_SET(x) (((uint8_t)(x) << ESC_ESC_RST_PDI_RST_SHIFT) & ESC_ESC_RST_PDI_RST_MASK)
+#define ESC_ESC_RST_PDI_RST_GET(x) (((uint8_t)(x) & ESC_ESC_RST_PDI_RST_MASK) >> ESC_ESC_RST_PDI_RST_SHIFT)
+
+/* Bitfield definition for register: ESC_DL_CTRL */
+/*
+ * SA (RO)
+ *
+ * Station alias:
+ * 0:Ignore Station Alias
+ * 1:Alias can be used for all configured
+ * address comm
+ */
+#define ESC_ESC_DL_CTRL_SA_MASK (0x1000000UL)
+#define ESC_ESC_DL_CTRL_SA_SHIFT (24U)
+#define ESC_ESC_DL_CTRL_SA_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_SA_MASK) >> ESC_ESC_DL_CTRL_SA_SHIFT)
+
+/*
+ * RFS (RO)
+ *
+ * RX FIFO Size (ESC delays start of
+ * forwarding until FIFO is at least half full).
+ * RX FIFO Size/RX delay reduction** :
+ * Value:EBUS:MII:
+ * 0:-50 ns -40 ns (-80 ns***)
+ * 1:-40 ns -40 ns (-80 ns***)
+ * 2:-30 ns -40 ns
+ * 3:-20 ns -40 ns
+ * 4:-10 ns no change
+ * 5:no change no change
+ * 6:no change no change
+ * 7:default default
+ * NOTE:EEPROM value is only taken over at first
+ * EEPROM load after power-on or reset
+ */
+#define ESC_ESC_DL_CTRL_RFS_MASK (0x70000UL)
+#define ESC_ESC_DL_CTRL_RFS_SHIFT (16U)
+#define ESC_ESC_DL_CTRL_RFS_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_RFS_MASK) >> ESC_ESC_DL_CTRL_RFS_SHIFT)
+
+/*
+ * LP3 (RO)
+ *
+ * Loop Port 3:
+ * 00:Auto
+ * 01:Auto Close
+ * 10:Open
+ * 11:Closed
+ */
+#define ESC_ESC_DL_CTRL_LP3_MASK (0xC000U)
+#define ESC_ESC_DL_CTRL_LP3_SHIFT (14U)
+#define ESC_ESC_DL_CTRL_LP3_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP3_MASK) >> ESC_ESC_DL_CTRL_LP3_SHIFT)
+
+/*
+ * LP2 (RO)
+ *
+ * Loop Port 2:
+ * 00:Auto
+ * 01:Auto Close
+ * 10:Open
+ * 11:Closed
+ */
+#define ESC_ESC_DL_CTRL_LP2_MASK (0x3000U)
+#define ESC_ESC_DL_CTRL_LP2_SHIFT (12U)
+#define ESC_ESC_DL_CTRL_LP2_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP2_MASK) >> ESC_ESC_DL_CTRL_LP2_SHIFT)
+
+/*
+ * LP1 (RO)
+ *
+ * Loop Port 1:
+ * 00:Auto
+ * 01:Auto Close
+ * 10:Open
+ * 11:Closed
+ */
+#define ESC_ESC_DL_CTRL_LP1_MASK (0xC00U)
+#define ESC_ESC_DL_CTRL_LP1_SHIFT (10U)
+#define ESC_ESC_DL_CTRL_LP1_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP1_MASK) >> ESC_ESC_DL_CTRL_LP1_SHIFT)
+
+/*
+ * LP0 (RO)
+ *
+ * Loop Port 0:
+ * 00:Auto
+ * 01:Auto Close
+ * 10:Open
+ * 11:Closed
+ * NOTE:
+ * Loop open means sending/receiving over this port
+ * is enabled, loop closed means sending/receiving
+ * is disabled and frames are forwarded to the next
+ * open port internally.
+ * Auto:loop closed at link down, opened at link up
+ * Auto Close:loop closed at link down, opened with
+ * writing 01 again after link up (or receiving a valid
+ * Ethernet frame at the closed port)
+ * Open:loop open regardless of link state
+ * Closed:loop closed regardless of link state
+ */
+#define ESC_ESC_DL_CTRL_LP0_MASK (0x300U)
+#define ESC_ESC_DL_CTRL_LP0_SHIFT (8U)
+#define ESC_ESC_DL_CTRL_LP0_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP0_MASK) >> ESC_ESC_DL_CTRL_LP0_SHIFT)
+
+/*
+ * TU (RO)
+ *
+ * Temporary use of settings in
+ * 0x0100:0x0103[8:15]:
+ * 0:permanent use
+ * 1:use for about 1 second, then revert to
+ * previous settings
+ */
+#define ESC_ESC_DL_CTRL_TU_MASK (0x2U)
+#define ESC_ESC_DL_CTRL_TU_SHIFT (1U)
+#define ESC_ESC_DL_CTRL_TU_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_TU_MASK) >> ESC_ESC_DL_CTRL_TU_SHIFT)
+
+/*
+ * FR (RO)
+ *
+ * Forwarding rule:
+ * 0:Forward non-EtherCAT frames:
+ * EtherCAT frames are processed,
+ * non-EtherCAT frames are forwarded
+ * without processing or modification.
+ * The source MAC address is not
+ * changed for any frame.
+ * 1:Destroy non-EtherCAT frames:
+ * EtherCAT frames are processed, non-EtherCAT frames are destroyed.
+ * The source MAC address is changed by
+ * the Processing Unit for every frame
+ * (SOURCE_MAC[1] is set
+ */
+#define ESC_ESC_DL_CTRL_FR_MASK (0x1U)
+#define ESC_ESC_DL_CTRL_FR_SHIFT (0U)
+#define ESC_ESC_DL_CTRL_FR_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_FR_MASK) >> ESC_ESC_DL_CTRL_FR_SHIFT)
+
+/* Bitfield definition for register: PHYSICAL_RW_OFFSET */
+/*
+ * OFFSET (RO)
+ *
+ * This register is used for ReadWrite
+ * commands in Device Addressing mode
+ * (FPRW, APRW, BRW).
+ * The internal read address is directly taken
+ * from the offset address field of the EtherCAT
+ * datagram header, while the internal write
+ * address is calculated by adding the Physical
+ * Read/Write Offset value to the offset address
+ * field.
+ * Internal read address = ADR,
+ * internal write address = ADR + R/W-Offset
+ */
+#define ESC_PHYSICAL_RW_OFFSET_OFFSET_MASK (0xFFFFU)
+#define ESC_PHYSICAL_RW_OFFSET_OFFSET_SHIFT (0U)
+#define ESC_PHYSICAL_RW_OFFSET_OFFSET_GET(x) (((uint16_t)(x) & ESC_PHYSICAL_RW_OFFSET_OFFSET_MASK) >> ESC_PHYSICAL_RW_OFFSET_OFFSET_SHIFT)
+
+/* Bitfield definition for register: ESC_DL_STAT */
+/*
+ * CP3 (RO)
+ *
+ * Communication on Port 3:
+ * 0:No stable communication
+ * 1:Communication established
+ */
+#define ESC_ESC_DL_STAT_CP3_MASK (0x8000U)
+#define ESC_ESC_DL_STAT_CP3_SHIFT (15U)
+#define ESC_ESC_DL_STAT_CP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP3_MASK) >> ESC_ESC_DL_STAT_CP3_SHIFT)
+
+/*
+ * LP3 (RO)
+ *
+ * Loop Port 3:
+ * 0:Open
+ * 1:Closed
+ */
+#define ESC_ESC_DL_STAT_LP3_MASK (0x4000U)
+#define ESC_ESC_DL_STAT_LP3_SHIFT (14U)
+#define ESC_ESC_DL_STAT_LP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP3_MASK) >> ESC_ESC_DL_STAT_LP3_SHIFT)
+
+/*
+ * CP2 (RO)
+ *
+ * Communication on Port 2:
+ * 0:No stable communication
+ * 1:Communication established
+ */
+#define ESC_ESC_DL_STAT_CP2_MASK (0x2000U)
+#define ESC_ESC_DL_STAT_CP2_SHIFT (13U)
+#define ESC_ESC_DL_STAT_CP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP2_MASK) >> ESC_ESC_DL_STAT_CP2_SHIFT)
+
+/*
+ * LP2 (RO)
+ *
+ * Loop Port 2:
+ * 0:Open
+ * 1:Closed
+ */
+#define ESC_ESC_DL_STAT_LP2_MASK (0x1000U)
+#define ESC_ESC_DL_STAT_LP2_SHIFT (12U)
+#define ESC_ESC_DL_STAT_LP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP2_MASK) >> ESC_ESC_DL_STAT_LP2_SHIFT)
+
+/*
+ * CP1 (RO)
+ *
+ * Communication on Port 1:
+ * 0:No stable communication
+ * 1:Communication established
+ */
+#define ESC_ESC_DL_STAT_CP1_MASK (0x800U)
+#define ESC_ESC_DL_STAT_CP1_SHIFT (11U)
+#define ESC_ESC_DL_STAT_CP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP1_MASK) >> ESC_ESC_DL_STAT_CP1_SHIFT)
+
+/*
+ * LP1 (RO)
+ *
+ * Loop Port 1:
+ * 0:Open
+ * 1:Closed
+ */
+#define ESC_ESC_DL_STAT_LP1_MASK (0x400U)
+#define ESC_ESC_DL_STAT_LP1_SHIFT (10U)
+#define ESC_ESC_DL_STAT_LP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP1_MASK) >> ESC_ESC_DL_STAT_LP1_SHIFT)
+
+/*
+ * CP0 (RO)
+ *
+ * Communication on Port 0:
+ * 0:No stable communication
+ * 1:Communication established
+ */
+#define ESC_ESC_DL_STAT_CP0_MASK (0x200U)
+#define ESC_ESC_DL_STAT_CP0_SHIFT (9U)
+#define ESC_ESC_DL_STAT_CP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP0_MASK) >> ESC_ESC_DL_STAT_CP0_SHIFT)
+
+/*
+ * LP0 (RO)
+ *
+ * Loop Port 0:
+ * 0:Open
+ * 1:Closed
+ */
+#define ESC_ESC_DL_STAT_LP0_MASK (0x100U)
+#define ESC_ESC_DL_STAT_LP0_SHIFT (8U)
+#define ESC_ESC_DL_STAT_LP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP0_MASK) >> ESC_ESC_DL_STAT_LP0_SHIFT)
+
+/*
+ * PLP3 (RO)
+ *
+ * Physical link on Port 3:
+ * 0:No link
+ * 1:Link detected
+ */
+#define ESC_ESC_DL_STAT_PLP3_MASK (0x80U)
+#define ESC_ESC_DL_STAT_PLP3_SHIFT (7U)
+#define ESC_ESC_DL_STAT_PLP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP3_MASK) >> ESC_ESC_DL_STAT_PLP3_SHIFT)
+
+/*
+ * PLP2 (RO)
+ *
+ * Physical link on Port 2:
+ * 0:No link
+ * 1:Link detected
+ */
+#define ESC_ESC_DL_STAT_PLP2_MASK (0x40U)
+#define ESC_ESC_DL_STAT_PLP2_SHIFT (6U)
+#define ESC_ESC_DL_STAT_PLP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP2_MASK) >> ESC_ESC_DL_STAT_PLP2_SHIFT)
+
+/*
+ * PLP1 (RO)
+ *
+ * Physical link on Port 1:
+ * 0:No link
+ * 1:Link detected
+ */
+#define ESC_ESC_DL_STAT_PLP1_MASK (0x20U)
+#define ESC_ESC_DL_STAT_PLP1_SHIFT (5U)
+#define ESC_ESC_DL_STAT_PLP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP1_MASK) >> ESC_ESC_DL_STAT_PLP1_SHIFT)
+
+/*
+ * PLP0 (RO)
+ *
+ * Physical link on Port 0:
+ * 0:No link
+ * 1:Link detected
+ */
+#define ESC_ESC_DL_STAT_PLP0_MASK (0x10U)
+#define ESC_ESC_DL_STAT_PLP0_SHIFT (4U)
+#define ESC_ESC_DL_STAT_PLP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP0_MASK) >> ESC_ESC_DL_STAT_PLP0_SHIFT)
+
+/*
+ * ELD (RO)
+ *
+ * Enhanced Link detection:
+ * 0:Deactivated for all ports
+ * 1:Activated for at least one port
+ * NOTE:EEPROM value is only transferred into this
+ * register at first EEPROM load after power-on or
+ * reset
+ */
+#define ESC_ESC_DL_STAT_ELD_MASK (0x4U)
+#define ESC_ESC_DL_STAT_ELD_SHIFT (2U)
+#define ESC_ESC_DL_STAT_ELD_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_ELD_MASK) >> ESC_ESC_DL_STAT_ELD_SHIFT)
+
+/*
+ * WDS (RO)
+ *
+ * PDI Watchdog Status:
+ * 0:Watchdog expired
+ * 1:Watchdog reloaded
+ */
+#define ESC_ESC_DL_STAT_WDS_MASK (0x2U)
+#define ESC_ESC_DL_STAT_WDS_SHIFT (1U)
+#define ESC_ESC_DL_STAT_WDS_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_WDS_MASK) >> ESC_ESC_DL_STAT_WDS_SHIFT)
+
+/*
+ * EPLC (RO)
+ *
+ * PDI operational/EEPROM loaded correctly:
+ * 0:EEPROM not loaded, PDI not
+ * operational (no access to Process Data
+ * RAM)
+ * 1:EEPROM loaded correctly, PDI
+ * operational (access to Process Data
+ * RAM)
+ */
+#define ESC_ESC_DL_STAT_EPLC_MASK (0x1U)
+#define ESC_ESC_DL_STAT_EPLC_SHIFT (0U)
+#define ESC_ESC_DL_STAT_EPLC_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_EPLC_MASK) >> ESC_ESC_DL_STAT_EPLC_SHIFT)
+
+/* Bitfield definition for register: AL_CTRL */
+/*
+ * DI (RW)
+ *
+ * Device Identification:
+ * 0:No request
+ * 1:Device Identification request
+ */
+#define ESC_AL_CTRL_DI_MASK (0x20U)
+#define ESC_AL_CTRL_DI_SHIFT (5U)
+#define ESC_AL_CTRL_DI_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_DI_SHIFT) & ESC_AL_CTRL_DI_MASK)
+#define ESC_AL_CTRL_DI_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_DI_MASK) >> ESC_AL_CTRL_DI_SHIFT)
+
+/*
+ * EIA (RW)
+ *
+ * Error Ind Ack:
+ * 0:No Ack of Error Ind in AL status register
+ * 1:Ack of Error Ind in AL status register
+ */
+#define ESC_AL_CTRL_EIA_MASK (0x10U)
+#define ESC_AL_CTRL_EIA_SHIFT (4U)
+#define ESC_AL_CTRL_EIA_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_EIA_SHIFT) & ESC_AL_CTRL_EIA_MASK)
+#define ESC_AL_CTRL_EIA_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_EIA_MASK) >> ESC_AL_CTRL_EIA_SHIFT)
+
+/*
+ * IST (RW)
+ *
+ * Initiate State Transition of the Device State
+ * Machine:
+ * 1:Request Init State
+ * 3:Request Bootstrap State
+ * 2:Request Pre-Operational State
+ * 4:Request Safe-Operational State
+ * 8:Request Operational State
+ */
+#define ESC_AL_CTRL_IST_MASK (0xFU)
+#define ESC_AL_CTRL_IST_SHIFT (0U)
+#define ESC_AL_CTRL_IST_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_IST_SHIFT) & ESC_AL_CTRL_IST_MASK)
+#define ESC_AL_CTRL_IST_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_IST_MASK) >> ESC_AL_CTRL_IST_SHIFT)
+
+/* Bitfield definition for register: AL_STAT */
+/*
+ * DI (RW)
+ *
+ * Device Identification:
+ * 0:Device Identification not valid
+ * 1:Device Identification loaded
+ */
+#define ESC_AL_STAT_DI_MASK (0x20U)
+#define ESC_AL_STAT_DI_SHIFT (5U)
+#define ESC_AL_STAT_DI_SET(x) (((uint16_t)(x) << ESC_AL_STAT_DI_SHIFT) & ESC_AL_STAT_DI_MASK)
+#define ESC_AL_STAT_DI_GET(x) (((uint16_t)(x) & ESC_AL_STAT_DI_MASK) >> ESC_AL_STAT_DI_SHIFT)
+
+/*
+ * EI (RW)
+ *
+ * Error Ind:
+ * 0:Device is in State as requested or Flag
+ * cleared by command
+ * 1:Device has not entered requested State
+ * or changed State as result of a local
+ * action
+ */
+#define ESC_AL_STAT_EI_MASK (0x10U)
+#define ESC_AL_STAT_EI_SHIFT (4U)
+#define ESC_AL_STAT_EI_SET(x) (((uint16_t)(x) << ESC_AL_STAT_EI_SHIFT) & ESC_AL_STAT_EI_MASK)
+#define ESC_AL_STAT_EI_GET(x) (((uint16_t)(x) & ESC_AL_STAT_EI_MASK) >> ESC_AL_STAT_EI_SHIFT)
+
+/*
+ * AS (RW)
+ *
+ * Actual State of the Device State Machine:
+ * 1:Init State
+ * 3:Bootstrap State
+ * 2:Pre-Operational State
+ * 4:Safe-Operational State
+ * 8:Operational State
+ */
+#define ESC_AL_STAT_AS_MASK (0xFU)
+#define ESC_AL_STAT_AS_SHIFT (0U)
+#define ESC_AL_STAT_AS_SET(x) (((uint16_t)(x) << ESC_AL_STAT_AS_SHIFT) & ESC_AL_STAT_AS_MASK)
+#define ESC_AL_STAT_AS_GET(x) (((uint16_t)(x) & ESC_AL_STAT_AS_MASK) >> ESC_AL_STAT_AS_SHIFT)
+
+/* Bitfield definition for register: AL_STAT_CODE */
+/*
+ * CODE (RW)
+ *
+ * AL Status Code
+ */
+#define ESC_AL_STAT_CODE_CODE_MASK (0xFFFFU)
+#define ESC_AL_STAT_CODE_CODE_SHIFT (0U)
+#define ESC_AL_STAT_CODE_CODE_SET(x) (((uint16_t)(x) << ESC_AL_STAT_CODE_CODE_SHIFT) & ESC_AL_STAT_CODE_CODE_MASK)
+#define ESC_AL_STAT_CODE_CODE_GET(x) (((uint16_t)(x) & ESC_AL_STAT_CODE_CODE_MASK) >> ESC_AL_STAT_CODE_CODE_SHIFT)
+
+/* Bitfield definition for register: RUN_LED_OVRD */
+/*
+ * EN_OVRD (RW)
+ *
+ * Enable Override:
+ * 0:Override disabled
+ * 1:Override enabled
+ */
+#define ESC_RUN_LED_OVRD_EN_OVRD_MASK (0x10U)
+#define ESC_RUN_LED_OVRD_EN_OVRD_SHIFT (4U)
+#define ESC_RUN_LED_OVRD_EN_OVRD_SET(x) (((uint8_t)(x) << ESC_RUN_LED_OVRD_EN_OVRD_SHIFT) & ESC_RUN_LED_OVRD_EN_OVRD_MASK)
+#define ESC_RUN_LED_OVRD_EN_OVRD_GET(x) (((uint8_t)(x) & ESC_RUN_LED_OVRD_EN_OVRD_MASK) >> ESC_RUN_LED_OVRD_EN_OVRD_SHIFT)
+
+/*
+ * LED_CODE (RW)
+ *
+ * LED code:
+ * 0x0:Off
+ * 0x1:Flash 1x
+ * 0x2-0xC:Flash 2x – 12x
+ * 0xD:Blinking
+ * 0xE:Flickering
+ * 0xF:On
+ */
+#define ESC_RUN_LED_OVRD_LED_CODE_MASK (0xFU)
+#define ESC_RUN_LED_OVRD_LED_CODE_SHIFT (0U)
+#define ESC_RUN_LED_OVRD_LED_CODE_SET(x) (((uint8_t)(x) << ESC_RUN_LED_OVRD_LED_CODE_SHIFT) & ESC_RUN_LED_OVRD_LED_CODE_MASK)
+#define ESC_RUN_LED_OVRD_LED_CODE_GET(x) (((uint8_t)(x) & ESC_RUN_LED_OVRD_LED_CODE_MASK) >> ESC_RUN_LED_OVRD_LED_CODE_SHIFT)
+
+/* Bitfield definition for register: ERR_LED_OVRD */
+/*
+ * EN_OVRD (RW)
+ *
+ * Enable Override:
+ * 0:Override disabled
+ * 1:Override enabled
+ */
+#define ESC_ERR_LED_OVRD_EN_OVRD_MASK (0x10U)
+#define ESC_ERR_LED_OVRD_EN_OVRD_SHIFT (4U)
+#define ESC_ERR_LED_OVRD_EN_OVRD_SET(x) (((uint8_t)(x) << ESC_ERR_LED_OVRD_EN_OVRD_SHIFT) & ESC_ERR_LED_OVRD_EN_OVRD_MASK)
+#define ESC_ERR_LED_OVRD_EN_OVRD_GET(x) (((uint8_t)(x) & ESC_ERR_LED_OVRD_EN_OVRD_MASK) >> ESC_ERR_LED_OVRD_EN_OVRD_SHIFT)
+
+/*
+ * LED_CODE (RW)
+ *
+ * LED code:
+ * 0x0:Off
+ * 0x1-0xC:Flash 1x – 12x
+ * 0xD:Blinking
+ * 0xE:Flickering
+ * 0xF:On
+ */
+#define ESC_ERR_LED_OVRD_LED_CODE_MASK (0xFU)
+#define ESC_ERR_LED_OVRD_LED_CODE_SHIFT (0U)
+#define ESC_ERR_LED_OVRD_LED_CODE_SET(x) (((uint8_t)(x) << ESC_ERR_LED_OVRD_LED_CODE_SHIFT) & ESC_ERR_LED_OVRD_LED_CODE_MASK)
+#define ESC_ERR_LED_OVRD_LED_CODE_GET(x) (((uint8_t)(x) & ESC_ERR_LED_OVRD_LED_CODE_MASK) >> ESC_ERR_LED_OVRD_LED_CODE_SHIFT)
+
+/* Bitfield definition for register: PDI_CTRL */
+/*
+ * PDI (RO)
+ *
+ * Process data interface:
+ * 0x00:Interface deactivated (no PDI)
+ * 0x01:4 Digital Input
+ * 0x02:4 Digital Output
+ * 0x03:2 Digital Input and 2 Digital Output
+ * 0x04:Digital I/O
+ * 0x05:SPI Slave
+ * 0x06:Oversampling I/O
+ * 0x07:EtherCAT Bridge (port 3)
+ * 0x08:16 Bit asynchronous Microcontroller
+ * interface
+ * 0x09:8 Bit asynchronous Microcontroller
+ * interface
+ * 0x0A:16 Bit synchronous Microcontroller
+ * interface
+ * 0x0B:8 Bit synchronous Microcontroller
+ * interface
+ * 0x10:32 Digital Input and 0 Digital Output
+ * 0x11:24 Digital Input and 8 Digital Output
+ * 0x12:16 Digital Input and 16 Digital Output
+ * 0x13:8 Digital Input and 24 Digital Output
+ * 0x14:0 Digital Input and 32 Digital Output
+ * 0x80:On-chip bus
+ * Others:Reserved
+ */
+#define ESC_PDI_CTRL_PDI_MASK (0xFFU)
+#define ESC_PDI_CTRL_PDI_SHIFT (0U)
+#define ESC_PDI_CTRL_PDI_GET(x) (((uint8_t)(x) & ESC_PDI_CTRL_PDI_MASK) >> ESC_PDI_CTRL_PDI_SHIFT)
+
+/* Bitfield definition for register: ESC_CFG */
+/*
+ * ELP3 (RO)
+ *
+ * Enhanced Link port 3:
+ * 0:disabled (if bit 1=0)
+ * 1:enabled
+ */
+#define ESC_ESC_CFG_ELP3_MASK (0x80U)
+#define ESC_ESC_CFG_ELP3_SHIFT (7U)
+#define ESC_ESC_CFG_ELP3_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP3_MASK) >> ESC_ESC_CFG_ELP3_SHIFT)
+
+/*
+ * ELP2 (RO)
+ *
+ * Enhanced Link port 2:
+ * 0:disabled (if bit 1=0)
+ * 1:enabled
+ */
+#define ESC_ESC_CFG_ELP2_MASK (0x40U)
+#define ESC_ESC_CFG_ELP2_SHIFT (6U)
+#define ESC_ESC_CFG_ELP2_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP2_MASK) >> ESC_ESC_CFG_ELP2_SHIFT)
+
+/*
+ * ELP1 (RO)
+ *
+ * Enhanced Link port 1:
+ * 0:disabled (if bit 1=0)
+ * 1:enabled
+ */
+#define ESC_ESC_CFG_ELP1_MASK (0x20U)
+#define ESC_ESC_CFG_ELP1_SHIFT (5U)
+#define ESC_ESC_CFG_ELP1_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP1_MASK) >> ESC_ESC_CFG_ELP1_SHIFT)
+
+/*
+ * ELP0 (RO)
+ *
+ * Enhanced Link port 0:
+ * 0:disabled (if bit 1=0)
+ * 1:enabled
+ */
+#define ESC_ESC_CFG_ELP0_MASK (0x10U)
+#define ESC_ESC_CFG_ELP0_SHIFT (4U)
+#define ESC_ESC_CFG_ELP0_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP0_MASK) >> ESC_ESC_CFG_ELP0_SHIFT)
+
+/*
+ * CDLIU (RO)
+ *
+ * Distributed Clocks Latch In Unit:
+ * 0:disabled (power saving)
+ * 1:enabled
+ */
+#define ESC_ESC_CFG_CDLIU_MASK (0x8U)
+#define ESC_ESC_CFG_CDLIU_SHIFT (3U)
+#define ESC_ESC_CFG_CDLIU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_CDLIU_MASK) >> ESC_ESC_CFG_CDLIU_SHIFT)
+
+/*
+ * DCSOU (RO)
+ *
+ * Distributed Clocks SYNC Out Unit:
+ * 0:disabled (power saving)
+ * 1:enabled
+ */
+#define ESC_ESC_CFG_DCSOU_MASK (0x4U)
+#define ESC_ESC_CFG_DCSOU_SHIFT (2U)
+#define ESC_ESC_CFG_DCSOU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_DCSOU_MASK) >> ESC_ESC_CFG_DCSOU_SHIFT)
+
+/*
+ * ELDAP (RO)
+ *
+ * Enhanced Link detection all ports:
+ * 0:disabled (if bits [7:4]=0)
+ * 1:enabled at all ports (overrides bits [7:4])
+ */
+#define ESC_ESC_CFG_ELDAP_MASK (0x2U)
+#define ESC_ESC_CFG_ELDAP_SHIFT (1U)
+#define ESC_ESC_CFG_ELDAP_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELDAP_MASK) >> ESC_ESC_CFG_ELDAP_SHIFT)
+
+/*
+ * DEV_EMU (RO)
+ *
+ * Device emulation (control of AL status):
+ * 0:AL status register has to be set by PDI
+ * 1:AL status register will be set to value
+ * written to AL control register
+ */
+#define ESC_ESC_CFG_DEV_EMU_MASK (0x1U)
+#define ESC_ESC_CFG_DEV_EMU_SHIFT (0U)
+#define ESC_ESC_CFG_DEV_EMU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_DEV_EMU_MASK) >> ESC_ESC_CFG_DEV_EMU_SHIFT)
+
+/* Bitfield definition for register: PDI_INFO */
+/*
+ * PDICN (RO)
+ *
+ * PDI configuration invalid:
+ * 0:PDI configuration ok
+ * 1:PDI configuration invalid
+ */
+#define ESC_PDI_INFO_PDICN_MASK (0x8U)
+#define ESC_PDI_INFO_PDICN_SHIFT (3U)
+#define ESC_PDI_INFO_PDICN_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PDICN_MASK) >> ESC_PDI_INFO_PDICN_SHIFT)
+
+/*
+ * PDIA (RO)
+ *
+ * PDI active:
+ * 0:PDI not active
+ * 1:PDI active
+ */
+#define ESC_PDI_INFO_PDIA_MASK (0x4U)
+#define ESC_PDI_INFO_PDIA_SHIFT (2U)
+#define ESC_PDI_INFO_PDIA_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PDIA_MASK) >> ESC_PDI_INFO_PDIA_SHIFT)
+
+/*
+ * ECLFE (RO)
+ *
+ * ESC configuration area loaded from
+ * EEPROM:
+ * 0:not loaded
+ * 1:loaded
+ */
+#define ESC_PDI_INFO_ECLFE_MASK (0x2U)
+#define ESC_PDI_INFO_ECLFE_SHIFT (1U)
+#define ESC_PDI_INFO_ECLFE_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_ECLFE_MASK) >> ESC_PDI_INFO_ECLFE_SHIFT)
+
+/*
+ * PFABW (RO)
+ *
+ * DI function acknowledge by write:
+ * 0:Disabled
+ * 1:Enabled
+ */
+#define ESC_PDI_INFO_PFABW_MASK (0x1U)
+#define ESC_PDI_INFO_PFABW_SHIFT (0U)
+#define ESC_PDI_INFO_PFABW_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PFABW_MASK) >> ESC_PDI_INFO_PFABW_SHIFT)
+
+/* Bitfield definition for register: PDI_CFG */
+/*
+ * BUS (RO)
+ *
+ * On-chip bus:
+ * 000:Intel® Avalon®
+ * 001:AXI®
+ * 010:Xilinx® PLB v4.6
+ * 100:Xilinx OPB
+ * others:reserved
+ */
+#define ESC_PDI_CFG_BUS_MASK (0xE0U)
+#define ESC_PDI_CFG_BUS_SHIFT (5U)
+#define ESC_PDI_CFG_BUS_GET(x) (((uint8_t)(x) & ESC_PDI_CFG_BUS_MASK) >> ESC_PDI_CFG_BUS_SHIFT)
+
+/*
+ * CLK (RO)
+ *
+ * On-chip bus clock:
+ * 0:asynchronous
+ * 1-31:synchronous multiplication factor
+ * (N * 25 MHz)
+ */
+#define ESC_PDI_CFG_CLK_MASK (0x1FU)
+#define ESC_PDI_CFG_CLK_SHIFT (0U)
+#define ESC_PDI_CFG_CLK_GET(x) (((uint8_t)(x) & ESC_PDI_CFG_CLK_MASK) >> ESC_PDI_CFG_CLK_SHIFT)
+
+/* Bitfield definition for register: PDI_SL_CFG */
+/*
+ * SYNC1_MAER (RO)
+ *
+ * SYNC1 mapped to AL Event Request
+ * register 0x0220[3]:
+ * 0:Disabled
+ * 1:Enabled
+ */
+#define ESC_PDI_SL_CFG_SYNC1_MAER_MASK (0x80U)
+#define ESC_PDI_SL_CFG_SYNC1_MAER_SHIFT (7U)
+#define ESC_PDI_SL_CFG_SYNC1_MAER_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_MAER_MASK) >> ESC_PDI_SL_CFG_SYNC1_MAER_SHIFT)
+
+/*
+ * SYNC1_CFG (RO)
+ *
+ * SYNC1/LATCH1 configuration*:
+ * 0:LATCH1 input
+ * 1:SYNC1 output
+ */
+#define ESC_PDI_SL_CFG_SYNC1_CFG_MASK (0x40U)
+#define ESC_PDI_SL_CFG_SYNC1_CFG_SHIFT (6U)
+#define ESC_PDI_SL_CFG_SYNC1_CFG_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_CFG_MASK) >> ESC_PDI_SL_CFG_SYNC1_CFG_SHIFT)
+
+/*
+ * SYNC1_ODP (RO)
+ *
+ * SYNC1 output driver/polarity:
+ * 00:Push-Pull active low
+ * 01:Open Drain (active low)
+ * 10:Push-Pull active high
+ * 11:Open Source (active high)
+ */
+#define ESC_PDI_SL_CFG_SYNC1_ODP_MASK (0x30U)
+#define ESC_PDI_SL_CFG_SYNC1_ODP_SHIFT (4U)
+#define ESC_PDI_SL_CFG_SYNC1_ODP_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_ODP_MASK) >> ESC_PDI_SL_CFG_SYNC1_ODP_SHIFT)
+
+/*
+ * SYNC0_MAER (RO)
+ *
+ * SYNC0 mapped to AL Event Request
+ * register 0x0220[2]:
+ * 0:Disabled
+ * 1:Enabled
+ */
+#define ESC_PDI_SL_CFG_SYNC0_MAER_MASK (0x8U)
+#define ESC_PDI_SL_CFG_SYNC0_MAER_SHIFT (3U)
+#define ESC_PDI_SL_CFG_SYNC0_MAER_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_MAER_MASK) >> ESC_PDI_SL_CFG_SYNC0_MAER_SHIFT)
+
+/*
+ * SYNC0_CFG (RO)
+ *
+ * SYNC0/LATCH0 configuration*:
+ * 0:LATCH0 Input
+ * 1:SYNC0 Output
+ */
+#define ESC_PDI_SL_CFG_SYNC0_CFG_MASK (0x4U)
+#define ESC_PDI_SL_CFG_SYNC0_CFG_SHIFT (2U)
+#define ESC_PDI_SL_CFG_SYNC0_CFG_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_CFG_MASK) >> ESC_PDI_SL_CFG_SYNC0_CFG_SHIFT)
+
+/*
+ * SYNC0_ODP (RO)
+ *
+ * SYNC0 output driver/polarity:
+ * 00:Push-Pull active low
+ * 01:Open Drain (active low)
+ * 10:Push-Pull active high
+ * 11:Open Source (active high)
+ */
+#define ESC_PDI_SL_CFG_SYNC0_ODP_MASK (0x3U)
+#define ESC_PDI_SL_CFG_SYNC0_ODP_SHIFT (0U)
+#define ESC_PDI_SL_CFG_SYNC0_ODP_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_ODP_MASK) >> ESC_PDI_SL_CFG_SYNC0_ODP_SHIFT)
+
+/* Bitfield definition for register: PDI_EXT_CFG */
+/*
+ * OCBST (RW)
+ *
+ * On-chip bus sub-type for AXI:
+ * 000:AXI3
+ * 001:AXI4
+ * 010:AXI4 LITE
+ * others:reserved
+ */
+#define ESC_PDI_EXT_CFG_OCBST_MASK (0x700U)
+#define ESC_PDI_EXT_CFG_OCBST_SHIFT (8U)
+#define ESC_PDI_EXT_CFG_OCBST_SET(x) (((uint16_t)(x) << ESC_PDI_EXT_CFG_OCBST_SHIFT) & ESC_PDI_EXT_CFG_OCBST_MASK)
+#define ESC_PDI_EXT_CFG_OCBST_GET(x) (((uint16_t)(x) & ESC_PDI_EXT_CFG_OCBST_MASK) >> ESC_PDI_EXT_CFG_OCBST_SHIFT)
+
+/*
+ * RPS (RO)
+ *
+ * Read prefetch size (in cycles of PDI width):
+ * 0:4 cycles
+ * 1:1 cycle (typical)
+ * 2:2 cycles
+ * 3:Reserved
+ */
+#define ESC_PDI_EXT_CFG_RPS_MASK (0x3U)
+#define ESC_PDI_EXT_CFG_RPS_SHIFT (0U)
+#define ESC_PDI_EXT_CFG_RPS_GET(x) (((uint16_t)(x) & ESC_PDI_EXT_CFG_RPS_MASK) >> ESC_PDI_EXT_CFG_RPS_SHIFT)
+
+/* Bitfield definition for register: ECAT_EVT_MSK */
+/*
+ * MASK (RO)
+ *
+ * ECAT Event masking of the ECAT Event
+ * Request Events for mapping into ECAT event
+ * field of EtherCAT frames:
+ * 0:Corresponding ECAT Event Request
+ * register bit is not mapped
+ * 1:Corresponding ECAT Event Request
+ * register bit is mapped
+ */
+#define ESC_ECAT_EVT_MSK_MASK_MASK (0xFFFFU)
+#define ESC_ECAT_EVT_MSK_MASK_SHIFT (0U)
+#define ESC_ECAT_EVT_MSK_MASK_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_MSK_MASK_MASK) >> ESC_ECAT_EVT_MSK_MASK_SHIFT)
+
+/* Bitfield definition for register: PDI_AL_EVT_MSK */
+/*
+ * MASK (RW)
+ *
+ * AL Event masking of the AL Event Request
+ * register Events for mapping to PDI IRQ
+ * signal:
+ * 0:Corresponding AL Event Request
+ * register bit is not mapped
+ * 1:Corresponding AL Event Request
+ * register bit is mapped
+ */
+#define ESC_PDI_AL_EVT_MSK_MASK_MASK (0xFFFFFFFFUL)
+#define ESC_PDI_AL_EVT_MSK_MASK_SHIFT (0U)
+#define ESC_PDI_AL_EVT_MSK_MASK_SET(x) (((uint32_t)(x) << ESC_PDI_AL_EVT_MSK_MASK_SHIFT) & ESC_PDI_AL_EVT_MSK_MASK_MASK)
+#define ESC_PDI_AL_EVT_MSK_MASK_GET(x) (((uint32_t)(x) & ESC_PDI_AL_EVT_MSK_MASK_MASK) >> ESC_PDI_AL_EVT_MSK_MASK_SHIFT)
+
+/* Bitfield definition for register: ECAT_EVT_REQ */
+/*
+ * MV (RO)
+ *
+ * Mirrors values of each SyncManager Status:
+ * 0:No Sync Channel 0 event
+ * 1:Sync Channel 0 event pending
+ * 0:No Sync Channel 1 event
+ * 1:Sync Channel 1 event pending
+ * …
+ * 0:No Sync Channel 7 event
+ * 1:Sync Channel 7 event pending
+ */
+#define ESC_ECAT_EVT_REQ_MV_MASK (0xFF0U)
+#define ESC_ECAT_EVT_REQ_MV_SHIFT (4U)
+#define ESC_ECAT_EVT_REQ_MV_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_MV_MASK) >> ESC_ECAT_EVT_REQ_MV_SHIFT)
+
+/*
+ * ALS_EVT (RO)
+ *
+ * AL Status event:
+ * 0:No change in AL Status
+ * 1:AL Status change
+ * (Bit is cleared by reading out AL Status
+ * 0x0130:0x0131 from ECAT)
+ */
+#define ESC_ECAT_EVT_REQ_ALS_EVT_MASK (0x8U)
+#define ESC_ECAT_EVT_REQ_ALS_EVT_SHIFT (3U)
+#define ESC_ECAT_EVT_REQ_ALS_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_ALS_EVT_MASK) >> ESC_ECAT_EVT_REQ_ALS_EVT_SHIFT)
+
+/*
+ * DLS_EVT (RO)
+ *
+ * DL Status event:
+ * 0:No change in DL Status
+ * 1:DL Status change
+ * (Bit is cleared by reading out DL Status
+ * 0x0110:0x0111 from ECAT)
+ */
+#define ESC_ECAT_EVT_REQ_DLS_EVT_MASK (0x4U)
+#define ESC_ECAT_EVT_REQ_DLS_EVT_SHIFT (2U)
+#define ESC_ECAT_EVT_REQ_DLS_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_DLS_EVT_MASK) >> ESC_ECAT_EVT_REQ_DLS_EVT_SHIFT)
+
+/*
+ * DCL_EVT (RO)
+ *
+ * DC Latch event:
+ * 0:No change on DC Latch Inputs
+ * 1:At least one change on DC Latch Inputs
+ * (Bit is cleared by reading DC Latch event
+ * times from ECAT for ECAT-controlled Latch
+ * Units, so that Latch 0/1 Status
+ * 0x09AE:0x09AF indicates no event)
+ */
+#define ESC_ECAT_EVT_REQ_DCL_EVT_MASK (0x1U)
+#define ESC_ECAT_EVT_REQ_DCL_EVT_SHIFT (0U)
+#define ESC_ECAT_EVT_REQ_DCL_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_DCL_EVT_MASK) >> ESC_ECAT_EVT_REQ_DCL_EVT_SHIFT)
+
+/* Bitfield definition for register: AL_EVT_REQ */
+/*
+ * SM_INT (RO)
+ *
+ * SyncManager interrupts (SyncManager
+ * register offset 0x5, bit [0] or [1]):
+ * 0:No SyncManager 0 interrupt
+ * 1:SyncManager 0 interrupt pending
+ * 0:No SyncManager 1 interrupt
+ * 1:SyncManager 1 interrupt pending
+ * …
+ * 0:No SyncManager 15 interrupt
+ * 1:SyncManager 15 interrupt pending
+ */
+#define ESC_AL_EVT_REQ_SM_INT_MASK (0xFFFF00UL)
+#define ESC_AL_EVT_REQ_SM_INT_SHIFT (8U)
+#define ESC_AL_EVT_REQ_SM_INT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_SM_INT_MASK) >> ESC_AL_EVT_REQ_SM_INT_SHIFT)
+
+/*
+ * WDG_PD (RO)
+ *
+ * Watchdog Process Data:
+ * 0:Has not expired
+ * 1:Has expired
+ * (Bit is cleared by reading Watchdog Status
+ * Process Data 0x0440 from PDI)
+ */
+#define ESC_AL_EVT_REQ_WDG_PD_MASK (0x40U)
+#define ESC_AL_EVT_REQ_WDG_PD_SHIFT (6U)
+#define ESC_AL_EVT_REQ_WDG_PD_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_WDG_PD_MASK) >> ESC_AL_EVT_REQ_WDG_PD_SHIFT)
+
+/*
+ * EE_EMU (RO)
+ *
+ * EEPROM Emulation:
+ * 0:No command pending
+ * 1:EEPROM command pending
+ * (Bit is cleared by acknowledging the
+ * command in EEPROM Control/Status
+ * register 0x0502:0x0503[10:8] from PDI)
+ */
+#define ESC_AL_EVT_REQ_EE_EMU_MASK (0x20U)
+#define ESC_AL_EVT_REQ_EE_EMU_SHIFT (5U)
+#define ESC_AL_EVT_REQ_EE_EMU_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_EE_EMU_MASK) >> ESC_AL_EVT_REQ_EE_EMU_SHIFT)
+
+/*
+ * SM_ACT (RO)
+ *
+ * SyncManager activation register
+ * (SyncManager register offset 0x6) changed:
+ * 0:No change in any SyncManager
+ * 1:At least one SyncManager changed
+ * (Bit is cleared by reading SyncManager
+ * Activation registers 0x0806 etc. from PDI)
+ */
+#define ESC_AL_EVT_REQ_SM_ACT_MASK (0x10U)
+#define ESC_AL_EVT_REQ_SM_ACT_SHIFT (4U)
+#define ESC_AL_EVT_REQ_SM_ACT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_SM_ACT_MASK) >> ESC_AL_EVT_REQ_SM_ACT_SHIFT)
+
+/*
+ * ST_DC_SYNC1 (RO)
+ *
+ * State of DC SYNC1 (if register
+ * 0x0151[7]=1):
+ * (Bit is cleared by reading of SYNC1 status
+ * 0x098F from PDI, use only in Acknowledge
+ * mode)
+ */
+#define ESC_AL_EVT_REQ_ST_DC_SYNC1_MASK (0x8U)
+#define ESC_AL_EVT_REQ_ST_DC_SYNC1_SHIFT (3U)
+#define ESC_AL_EVT_REQ_ST_DC_SYNC1_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ST_DC_SYNC1_MASK) >> ESC_AL_EVT_REQ_ST_DC_SYNC1_SHIFT)
+
+/*
+ * ST_DC_SYNC0 (RO)
+ *
+ * State of DC SYNC0 (if register
+ * 0x0151[3]=1):
+ * (Bit is cleared by reading SYNC0 status
+ * 0x098E from PDI, use only in Acknowledge
+ * mode)
+ */
+#define ESC_AL_EVT_REQ_ST_DC_SYNC0_MASK (0x4U)
+#define ESC_AL_EVT_REQ_ST_DC_SYNC0_SHIFT (2U)
+#define ESC_AL_EVT_REQ_ST_DC_SYNC0_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ST_DC_SYNC0_MASK) >> ESC_AL_EVT_REQ_ST_DC_SYNC0_SHIFT)
+
+/*
+ * DCL_EVT (RO)
+ *
+ * DC Latch event:
+ * 0:No change on DC Latch Inputs
+ * 1:At least one change on DC Latch Inputs
+ * (Bit is cleared by reading DC Latch event
+ * times from PDI, so that Latch 0/1 Status
+ * 0x09AE:0x09AF indicates no event. Available
+ * if Latch Unit is PDI-controlled)
+ */
+#define ESC_AL_EVT_REQ_DCL_EVT_MASK (0x2U)
+#define ESC_AL_EVT_REQ_DCL_EVT_SHIFT (1U)
+#define ESC_AL_EVT_REQ_DCL_EVT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_DCL_EVT_MASK) >> ESC_AL_EVT_REQ_DCL_EVT_SHIFT)
+
+/*
+ * ALC_EVT (RO)
+ *
+ * AL Control event:
+ * 0:No AL Control Register change
+ * 1:AL Control Register has been written3
+ * (Bit is cleared by reading AL Control register
+ * 0x0120:0x0121 from PDI)
+ */
+#define ESC_AL_EVT_REQ_ALC_EVT_MASK (0x1U)
+#define ESC_AL_EVT_REQ_ALC_EVT_SHIFT (0U)
+#define ESC_AL_EVT_REQ_ALC_EVT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ALC_EVT_MASK) >> ESC_AL_EVT_REQ_ALC_EVT_SHIFT)
+
+/* Bitfield definition for register array: RX_ERR_CNT */
+/*
+ * RX_ERR (RO)
+ *
+ * RX Error counter of Port y (counting is
+ * stopped when 0xFF is reached).
+ */
+#define ESC_RX_ERR_CNT_RX_ERR_MASK (0xFF00U)
+#define ESC_RX_ERR_CNT_RX_ERR_SHIFT (8U)
+#define ESC_RX_ERR_CNT_RX_ERR_GET(x) (((uint16_t)(x) & ESC_RX_ERR_CNT_RX_ERR_MASK) >> ESC_RX_ERR_CNT_RX_ERR_SHIFT)
+
+/*
+ * IVD_FRM (RO)
+ *
+ * Invalid frame counter of Port y (counting is
+ * stopped when 0xFF is reached).
+ */
+#define ESC_RX_ERR_CNT_IVD_FRM_MASK (0xFFU)
+#define ESC_RX_ERR_CNT_IVD_FRM_SHIFT (0U)
+#define ESC_RX_ERR_CNT_IVD_FRM_GET(x) (((uint16_t)(x) & ESC_RX_ERR_CNT_IVD_FRM_MASK) >> ESC_RX_ERR_CNT_IVD_FRM_SHIFT)
+
+/* Bitfield definition for register array: FWD_RX_ERR_CNT */
+/*
+ * ERR_CNT (RO)
+ *
+ * Forwarded error counter of Port y (counting is
+ * stopped when 0xFF is reached).
+ */
+#define ESC_FWD_RX_ERR_CNT_ERR_CNT_MASK (0xFFU)
+#define ESC_FWD_RX_ERR_CNT_ERR_CNT_SHIFT (0U)
+#define ESC_FWD_RX_ERR_CNT_ERR_CNT_GET(x) (((uint8_t)(x) & ESC_FWD_RX_ERR_CNT_ERR_CNT_MASK) >> ESC_FWD_RX_ERR_CNT_ERR_CNT_SHIFT)
+
+/* Bitfield definition for register: ECAT_PU_ERR_CNT */
+/*
+ * CNT (RO)
+ *
+ * ECAT Processing Unit error counter
+ * (counting is stopped when 0xFF is reached).
+ * Counts errors of frames passing the
+ * Processing Unit.
+ */
+#define ESC_ECAT_PU_ERR_CNT_CNT_MASK (0xFFU)
+#define ESC_ECAT_PU_ERR_CNT_CNT_SHIFT (0U)
+#define ESC_ECAT_PU_ERR_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_ECAT_PU_ERR_CNT_CNT_MASK) >> ESC_ECAT_PU_ERR_CNT_CNT_SHIFT)
+
+/* Bitfield definition for register: PDI_ERR_CNT */
+/*
+ * CNT (RO)
+ *
+ * PDI Error counter (counting is stopped when
+ * 0xFF is reached). Counts if a PDI access has
+ * an interface error.
+ */
+#define ESC_PDI_ERR_CNT_CNT_MASK (0xFFU)
+#define ESC_PDI_ERR_CNT_CNT_SHIFT (0U)
+#define ESC_PDI_ERR_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_PDI_ERR_CNT_CNT_MASK) >> ESC_PDI_ERR_CNT_CNT_SHIFT)
+
+/* Bitfield definition for register array: LOST_LINK_CNT */
+/*
+ * CNT (RO)
+ *
+ * Lost Link counter of Port y (counting is
+ * stopped when 0xff is reached). Counts only if
+ * port is open and loop is Auto.
+ */
+#define ESC_LOST_LINK_CNT_CNT_MASK (0xFFU)
+#define ESC_LOST_LINK_CNT_CNT_SHIFT (0U)
+#define ESC_LOST_LINK_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_LOST_LINK_CNT_CNT_MASK) >> ESC_LOST_LINK_CNT_CNT_SHIFT)
+
+/* Bitfield definition for register: WDG_DIV */
+/*
+ * DIV (RO)
+ *
+ * Watchdog divider:Number of 25 MHz tics
+ * (minus 2) that represent the basic watchdog
+ * increment. (Default value is 100µs = 2498)
+ */
+#define ESC_WDG_DIV_DIV_MASK (0xFFFFU)
+#define ESC_WDG_DIV_DIV_SHIFT (0U)
+#define ESC_WDG_DIV_DIV_GET(x) (((uint16_t)(x) & ESC_WDG_DIV_DIV_MASK) >> ESC_WDG_DIV_DIV_SHIFT)
+
+/* Bitfield definition for register: WDG_TIME_PDI */
+/*
+ * TIME (RO)
+ *
+ * Watchdog Time PDI:number of basic
+ * watchdog increments
+ * (Default value with Watchdog divider 100µs
+ * means 100ms Watchdog)
+ */
+#define ESC_WDG_TIME_PDI_TIME_MASK (0xFFFFU)
+#define ESC_WDG_TIME_PDI_TIME_SHIFT (0U)
+#define ESC_WDG_TIME_PDI_TIME_GET(x) (((uint16_t)(x) & ESC_WDG_TIME_PDI_TIME_MASK) >> ESC_WDG_TIME_PDI_TIME_SHIFT)
+
+/* Bitfield definition for register: WDG_TIME_PDAT */
+/*
+ * TIME (RO)
+ *
+ * Watchdog Time Process Data:number of
+ * basic watchdog increments
+ * (Default value with Watchdog divider 100µs
+ * means 100ms Watchdog)
+ */
+#define ESC_WDG_TIME_PDAT_TIME_MASK (0xFFFFU)
+#define ESC_WDG_TIME_PDAT_TIME_SHIFT (0U)
+#define ESC_WDG_TIME_PDAT_TIME_GET(x) (((uint16_t)(x) & ESC_WDG_TIME_PDAT_TIME_MASK) >> ESC_WDG_TIME_PDAT_TIME_SHIFT)
+
+/* Bitfield definition for register: WDG_STAT_PDAT */
+/*
+ * ST (RW)
+ *
+ * Watchdog Status of Process Data (triggered
+ * by SyncManagers)
+ * 0:Watchdog Process Data expired
+ * 1:Watchdog Process Data is active or
+ * disabled
+ */
+#define ESC_WDG_STAT_PDAT_ST_MASK (0x1U)
+#define ESC_WDG_STAT_PDAT_ST_SHIFT (0U)
+#define ESC_WDG_STAT_PDAT_ST_SET(x) (((uint16_t)(x) << ESC_WDG_STAT_PDAT_ST_SHIFT) & ESC_WDG_STAT_PDAT_ST_MASK)
+#define ESC_WDG_STAT_PDAT_ST_GET(x) (((uint16_t)(x) & ESC_WDG_STAT_PDAT_ST_MASK) >> ESC_WDG_STAT_PDAT_ST_SHIFT)
+
+/* Bitfield definition for register: WDG_CNT_PDAT */
+/*
+ * CNT (RO)
+ *
+ * Watchdog Counter Process Data (counting is
+ * stopped when 0xFF is reached). Counts if
+ * Process Data Watchdog expires.
+ */
+#define ESC_WDG_CNT_PDAT_CNT_MASK (0xFFU)
+#define ESC_WDG_CNT_PDAT_CNT_SHIFT (0U)
+#define ESC_WDG_CNT_PDAT_CNT_GET(x) (((uint8_t)(x) & ESC_WDG_CNT_PDAT_CNT_MASK) >> ESC_WDG_CNT_PDAT_CNT_SHIFT)
+
+/* Bitfield definition for register: WDG_CNT_PDI */
+/*
+ * CNT (RO)
+ *
+ * Watchdog PDI counter (counting is stopped
+ * when 0xFF is reached). Counts if PDI
+ * Watchdog expires.
+ */
+#define ESC_WDG_CNT_PDI_CNT_MASK (0xFFU)
+#define ESC_WDG_CNT_PDI_CNT_SHIFT (0U)
+#define ESC_WDG_CNT_PDI_CNT_GET(x) (((uint8_t)(x) & ESC_WDG_CNT_PDI_CNT_MASK) >> ESC_WDG_CNT_PDI_CNT_SHIFT)
+
+/* Bitfield definition for register: EEPROM_CFG */
+/*
+ * FORCE_ECAT (RO)
+ *
+ * Force ECAT access:
+ * 0:Do not change Bit 0x0501[0]
+ * 1:Reset Bit 0x0501[0] to 0
+ */
+#define ESC_EEPROM_CFG_FORCE_ECAT_MASK (0x2U)
+#define ESC_EEPROM_CFG_FORCE_ECAT_SHIFT (1U)
+#define ESC_EEPROM_CFG_FORCE_ECAT_GET(x) (((uint8_t)(x) & ESC_EEPROM_CFG_FORCE_ECAT_MASK) >> ESC_EEPROM_CFG_FORCE_ECAT_SHIFT)
+
+/*
+ * PDI (RO)
+ *
+ * EEPROM control is offered to PDI:
+ * 0:no
+ * 1:yes (PDI has EEPROM control)
+ */
+#define ESC_EEPROM_CFG_PDI_MASK (0x1U)
+#define ESC_EEPROM_CFG_PDI_SHIFT (0U)
+#define ESC_EEPROM_CFG_PDI_GET(x) (((uint8_t)(x) & ESC_EEPROM_CFG_PDI_MASK) >> ESC_EEPROM_CFG_PDI_SHIFT)
+
+/* Bitfield definition for register: EEPROM_PDI_ACC_STAT */
+/*
+ * ACCESS (RW)
+ *
+ * Access to EEPROM:
+ * 0:PDI releases EEPROM access
+ * 1:PDI takes EEPROM access (PDI has
+ * EEPROM control)
+ */
+#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK (0x1U)
+#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT (0U)
+#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_SET(x) (((uint8_t)(x) << ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT) & ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK)
+#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_GET(x) (((uint8_t)(x) & ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK) >> ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT)
+
+/* Bitfield definition for register: EEPROM_CTRL_STAT */
+/*
+ * BUSY (RO)
+ *
+ * Busy:
+ * 0:EEPROM Interface is idle
+ * 1:EEPROM Interface is busy
+ */
+#define ESC_EEPROM_CTRL_STAT_BUSY_MASK (0x8000U)
+#define ESC_EEPROM_CTRL_STAT_BUSY_SHIFT (15U)
+#define ESC_EEPROM_CTRL_STAT_BUSY_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_BUSY_MASK) >> ESC_EEPROM_CTRL_STAT_BUSY_SHIFT)
+
+/*
+ * ERR_WEN (RO)
+ *
+ * Error Write Enable*3
+ * :
+ * 0:No error
+ * 1:Write Command without Write enable
+ */
+#define ESC_EEPROM_CTRL_STAT_ERR_WEN_MASK (0x4000U)
+#define ESC_EEPROM_CTRL_STAT_ERR_WEN_SHIFT (14U)
+#define ESC_EEPROM_CTRL_STAT_ERR_WEN_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ERR_WEN_MASK) >> ESC_EEPROM_CTRL_STAT_ERR_WEN_SHIFT)
+
+/*
+ * ERR_ACK_CMD (RW)
+ *
+ * Error Acknowledge/Command*3
+ * :
+ * 0:No error
+ * 1:Missing EEPROM acknowledge or invalid
+ * command
+ * EEPROM emulation only:PDI writes 1 if a temporary
+ * failure has occurred.
+ */
+#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK (0x2000U)
+#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT (13U)
+#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT) & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK)
+#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK) >> ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT)
+
+/*
+ * EE_LDS (RO)
+ *
+ * EEPROM loading status:
+ * 0:EEPROM loaded, device information ok
+ * 1:EEPROM not loaded, device information not
+ * available (EEPROM loading in progress or
+ * finished with a failure)
+ */
+#define ESC_EEPROM_CTRL_STAT_EE_LDS_MASK (0x1000U)
+#define ESC_EEPROM_CTRL_STAT_EE_LDS_SHIFT (12U)
+#define ESC_EEPROM_CTRL_STAT_EE_LDS_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_LDS_MASK) >> ESC_EEPROM_CTRL_STAT_EE_LDS_SHIFT)
+
+/*
+ * CKSM_ERR (RW)
+ *
+ * Checksum Error in ESC Configuration Area:
+ * 0:Checksum ok
+ * 1:Checksum error
+ * EEPROM emulation for IP Core only:PDI writes 1 if a
+ * CRC failure has occurred for a reload command.
+ */
+#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK (0x800U)
+#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT (11U)
+#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT) & ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK)
+#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK) >> ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT)
+
+/*
+ * CMD (RW)
+ *
+ * Command register*2:
+ * Write:Initiate command.
+ * Read:Currently executed command
+ * Commands:
+ * 000:No command/EEPROM idle (clear error bits)
+ * 001:Read
+ * 010:Write
+ * 100:Reload
+ * Others:Reserved/invalid commands (do not issue)
+ * EEPROM emulation only:after execution, PDI writes
+ * command value to indicate operation is ready.
+ */
+#define ESC_EEPROM_CTRL_STAT_CMD_MASK (0x700U)
+#define ESC_EEPROM_CTRL_STAT_CMD_SHIFT (8U)
+#define ESC_EEPROM_CTRL_STAT_CMD_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_CMD_SHIFT) & ESC_EEPROM_CTRL_STAT_CMD_MASK)
+#define ESC_EEPROM_CTRL_STAT_CMD_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_CMD_MASK) >> ESC_EEPROM_CTRL_STAT_CMD_SHIFT)
+
+/*
+ * EE_ALGM (RO)
+ *
+ * Selected EEPROM Algorithm:
+ * 0:1 address byte (1Kbit – 16Kbit EEPROMs)
+ * 1:2 address bytes (32Kbit – 4 Mbit EEPROMs)
+ */
+#define ESC_EEPROM_CTRL_STAT_EE_ALGM_MASK (0x80U)
+#define ESC_EEPROM_CTRL_STAT_EE_ALGM_SHIFT (7U)
+#define ESC_EEPROM_CTRL_STAT_EE_ALGM_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_ALGM_MASK) >> ESC_EEPROM_CTRL_STAT_EE_ALGM_SHIFT)
+
+/*
+ * NUM_RD_BYTE (RO)
+ *
+ * Supported number of EEPROM read bytes:
+ * 0:4 Bytes
+ * 1:8 Bytes
+ */
+#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_MASK (0x40U)
+#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_SHIFT (6U)
+#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_MASK) >> ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_SHIFT)
+
+/*
+ * EE_EMU (RO)
+ *
+ * EPROM emulation:
+ * 0:Normal operation (I²C interface used)
+ * 1:PDI emulates EEPROM (I²C not used)
+ */
+#define ESC_EEPROM_CTRL_STAT_EE_EMU_MASK (0x20U)
+#define ESC_EEPROM_CTRL_STAT_EE_EMU_SHIFT (5U)
+#define ESC_EEPROM_CTRL_STAT_EE_EMU_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_EMU_MASK) >> ESC_EEPROM_CTRL_STAT_EE_EMU_SHIFT)
+
+/*
+ * ECAT_WEN (RO)
+ *
+ * ECAT write enable*2
+ * :
+ * 0:Write requests are disabled
+ * 1:Write requests are enabled
+ * This bit is always 1 if PDI has EEPROM control.
+ */
+#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_MASK (0x1U)
+#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_SHIFT (0U)
+#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ECAT_WEN_MASK) >> ESC_EEPROM_CTRL_STAT_ECAT_WEN_SHIFT)
+
+/* Bitfield definition for register: EEPROM_ADDR */
+/*
+ * ADDR (RW)
+ *
+ * EEPROM Address
+ * 0:First word (= 16 bit)
+ * 1:Second word
+ * …
+ * Actually used EEPROM Address bits:
+ * 9-0: EEPROM size up to 16 Kbit
+ * 17-0: EEPROM size 32 Kbit – 4 Mbit
+ * 31-0: EEPROM Emulation
+ */
+#define ESC_EEPROM_ADDR_ADDR_MASK (0xFFFFFFFFUL)
+#define ESC_EEPROM_ADDR_ADDR_SHIFT (0U)
+#define ESC_EEPROM_ADDR_ADDR_SET(x) (((uint32_t)(x) << ESC_EEPROM_ADDR_ADDR_SHIFT) & ESC_EEPROM_ADDR_ADDR_MASK)
+#define ESC_EEPROM_ADDR_ADDR_GET(x) (((uint32_t)(x) & ESC_EEPROM_ADDR_ADDR_MASK) >> ESC_EEPROM_ADDR_ADDR_SHIFT)
+
+/* Bitfield definition for register: EEPROM_DATA */
+/*
+ * HI (RW)
+ *
+ * EEPROM Read data (data read from
+ * EEPROM, higher bytes)
+ */
+#define ESC_EEPROM_DATA_HI_MASK (0xFFFFFFFFFFFF0000ULL)
+#define ESC_EEPROM_DATA_HI_SHIFT (16U)
+#define ESC_EEPROM_DATA_HI_SET(x) (((uint64_t)(x) << ESC_EEPROM_DATA_HI_SHIFT) & ESC_EEPROM_DATA_HI_MASK)
+#define ESC_EEPROM_DATA_HI_GET(x) (((uint64_t)(x) & ESC_EEPROM_DATA_HI_MASK) >> ESC_EEPROM_DATA_HI_SHIFT)
+
+/*
+ * LO (RW)
+ *
+ * EEPROM Write data (data to be written to
+ * EEPROM) or
+ * EEPROM Read data (data read from
+ * EEPROM, lower bytes)
+ */
+#define ESC_EEPROM_DATA_LO_MASK (0xFFFFU)
+#define ESC_EEPROM_DATA_LO_SHIFT (0U)
+#define ESC_EEPROM_DATA_LO_SET(x) (((uint64_t)(x) << ESC_EEPROM_DATA_LO_SHIFT) & ESC_EEPROM_DATA_LO_MASK)
+#define ESC_EEPROM_DATA_LO_GET(x) (((uint64_t)(x) & ESC_EEPROM_DATA_LO_MASK) >> ESC_EEPROM_DATA_LO_SHIFT)
+
+/* Bitfield definition for register: MII_MNG_CS */
+/*
+ * BUSY (RO)
+ *
+ * Busy:
+ * 0:MII Management Interface is idle
+ * 1:MII Management Interface is busy
+ */
+#define ESC_MII_MNG_CS_BUSY_MASK (0x8000U)
+#define ESC_MII_MNG_CS_BUSY_SHIFT (15U)
+#define ESC_MII_MNG_CS_BUSY_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_BUSY_MASK) >> ESC_MII_MNG_CS_BUSY_SHIFT)
+
+/*
+ * CMD_ERR (RO)
+ *
+ * Command error:
+ * 0:Last Command was successful
+ * 1:Invalid command or write command
+ * without Write Enable
+ * Cleared by executing a valid command or by
+ * writing “00” to Command register bits [9:8].
+ */
+#define ESC_MII_MNG_CS_CMD_ERR_MASK (0x4000U)
+#define ESC_MII_MNG_CS_CMD_ERR_SHIFT (14U)
+#define ESC_MII_MNG_CS_CMD_ERR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_CMD_ERR_MASK) >> ESC_MII_MNG_CS_CMD_ERR_SHIFT)
+
+/*
+ * RD_ERR (RO)
+ *
+ * Read error:
+ * 0:No read error
+ * 1:Read error occurred (PHY or register
+ * not available)
+ * Cleared by writing to register 0x0511
+ */
+#define ESC_MII_MNG_CS_RD_ERR_MASK (0x2000U)
+#define ESC_MII_MNG_CS_RD_ERR_SHIFT (13U)
+#define ESC_MII_MNG_CS_RD_ERR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_RD_ERR_MASK) >> ESC_MII_MNG_CS_RD_ERR_SHIFT)
+
+/*
+ * CMD (RW)
+ *
+ * Command register*:
+ * Write:Initiate command.
+ * Read:Currently executed command
+ * 00:No command/MI idle (clear error bits)
+ * 01:Read
+ * 10:Write
+ * Others:Reserved/invalid command (do not
+ * issue)
+ */
+#define ESC_MII_MNG_CS_CMD_MASK (0x300U)
+#define ESC_MII_MNG_CS_CMD_SHIFT (8U)
+#define ESC_MII_MNG_CS_CMD_SET(x) (((uint16_t)(x) << ESC_MII_MNG_CS_CMD_SHIFT) & ESC_MII_MNG_CS_CMD_MASK)
+#define ESC_MII_MNG_CS_CMD_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_CMD_MASK) >> ESC_MII_MNG_CS_CMD_SHIFT)
+
+/*
+ * PHY_ADDR (RO)
+ *
+ * PHY address of port 0
+ * (this is equal to the PHY address offset, if the
+ * PHY addresses are consecutive)
+ * IP Core since V3.0.0/3.00c:
+ * Translation 0x0512[7]=0:
+ * Register 0x0510[7:3] shows PHY address of
+ * port 0
+ * Translation 0x0512[7]=1:
+ * Register 0x0510[7:3] shows the PHY address
+ * which will be used for port 0-3 as requested
+ * by 0x0512[4:0] (valid values 0-3)
+ */
+#define ESC_MII_MNG_CS_PHY_ADDR_MASK (0xF8U)
+#define ESC_MII_MNG_CS_PHY_ADDR_SHIFT (3U)
+#define ESC_MII_MNG_CS_PHY_ADDR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_PHY_ADDR_MASK) >> ESC_MII_MNG_CS_PHY_ADDR_SHIFT)
+
+/*
+ * LINK_DC (RO)
+ *
+ * MI link detection and configuration:
+ * 0:Disabled for all ports
+ * 1:Enabled for at least one MII port, refer
+ * to PHY Port Status (0x0518 ff.) for
+ * details
+ */
+#define ESC_MII_MNG_CS_LINK_DC_MASK (0x4U)
+#define ESC_MII_MNG_CS_LINK_DC_SHIFT (2U)
+#define ESC_MII_MNG_CS_LINK_DC_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_LINK_DC_MASK) >> ESC_MII_MNG_CS_LINK_DC_SHIFT)
+
+/*
+ * PDI (RO)
+ *
+ * Management Interface can be controlled by
+ * PDI (registers 0x0516-0x0517):
+ * 0:Only ECAT control
+ * 1:PDI control possible
+ */
+#define ESC_MII_MNG_CS_PDI_MASK (0x2U)
+#define ESC_MII_MNG_CS_PDI_SHIFT (1U)
+#define ESC_MII_MNG_CS_PDI_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_PDI_MASK) >> ESC_MII_MNG_CS_PDI_SHIFT)
+
+/*
+ * WEN (RO)
+ *
+ * Write enable*:
+ * 0:Write disabled
+ * 1:Write enabled
+ * This bit is always 1 if PDI has MI control.
+ * ET1100-0000/-0001 exception:
+ * Bit is not always 1 if PDI has MI control, and
+ * bit is writable by PDI.
+ */
+#define ESC_MII_MNG_CS_WEN_MASK (0x1U)
+#define ESC_MII_MNG_CS_WEN_SHIFT (0U)
+#define ESC_MII_MNG_CS_WEN_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_WEN_MASK) >> ESC_MII_MNG_CS_WEN_SHIFT)
+
+/* Bitfield definition for register: PHY_ADDR */
+/*
+ * SHOW (RW)
+ *
+ * Target PHY Address translation:
+ * 0:Enabled
+ * 1:Disabled
+ * Refer to 0x0512[4:0] and 0x0510[7:3] for
+ * details.
+ */
+#define ESC_PHY_ADDR_SHOW_MASK (0x80U)
+#define ESC_PHY_ADDR_SHOW_SHIFT (7U)
+#define ESC_PHY_ADDR_SHOW_SET(x) (((uint8_t)(x) << ESC_PHY_ADDR_SHOW_SHIFT) & ESC_PHY_ADDR_SHOW_MASK)
+#define ESC_PHY_ADDR_SHOW_GET(x) (((uint8_t)(x) & ESC_PHY_ADDR_SHOW_MASK) >> ESC_PHY_ADDR_SHOW_SHIFT)
+
+/*
+ * ADDR (RW)
+ *
+ * Target PHY Address
+ * Translation 0x0512[7]=0:
+ * 0-3:Target PHY Addresses 0-3 are used
+ * to access the PHYs at port 0-3, when
+ * the PHY addresses are properly
+ * configured
+ * 4-31:The configured PHY address of port 0
+ * (PHY address offset) is added to the
+ * Target PHY Address values 4-31
+ * when accessing a PHY
+ * Translation 0x0512[7]=1:
+ * 0-31:Target PHY Addresses is used when
+ * accessing a PHY without translation
+ */
+#define ESC_PHY_ADDR_ADDR_MASK (0x1FU)
+#define ESC_PHY_ADDR_ADDR_SHIFT (0U)
+#define ESC_PHY_ADDR_ADDR_SET(x) (((uint8_t)(x) << ESC_PHY_ADDR_ADDR_SHIFT) & ESC_PHY_ADDR_ADDR_MASK)
+#define ESC_PHY_ADDR_ADDR_GET(x) (((uint8_t)(x) & ESC_PHY_ADDR_ADDR_MASK) >> ESC_PHY_ADDR_ADDR_SHIFT)
+
+/* Bitfield definition for register: PHY_REG_ADDR */
+/*
+ * ADDR (RW)
+ *
+ * Address of PHY Register that shall be
+ * read/written
+ */
+#define ESC_PHY_REG_ADDR_ADDR_MASK (0x1FU)
+#define ESC_PHY_REG_ADDR_ADDR_SHIFT (0U)
+#define ESC_PHY_REG_ADDR_ADDR_SET(x) (((uint8_t)(x) << ESC_PHY_REG_ADDR_ADDR_SHIFT) & ESC_PHY_REG_ADDR_ADDR_MASK)
+#define ESC_PHY_REG_ADDR_ADDR_GET(x) (((uint8_t)(x) & ESC_PHY_REG_ADDR_ADDR_MASK) >> ESC_PHY_REG_ADDR_ADDR_SHIFT)
+
+/* Bitfield definition for register: PHY_DATA */
+/*
+ * DATA (RW)
+ *
+ * PHY Read/Write Data
+ */
+#define ESC_PHY_DATA_DATA_MASK (0xFFFFU)
+#define ESC_PHY_DATA_DATA_SHIFT (0U)
+#define ESC_PHY_DATA_DATA_SET(x) (((uint16_t)(x) << ESC_PHY_DATA_DATA_SHIFT) & ESC_PHY_DATA_DATA_MASK)
+#define ESC_PHY_DATA_DATA_GET(x) (((uint16_t)(x) & ESC_PHY_DATA_DATA_MASK) >> ESC_PHY_DATA_DATA_SHIFT)
+
+/* Bitfield definition for register: MIIM_ECAT_ACC_STAT */
+/*
+ * ACC (RO)
+ *
+ * Access to MII management:
+ * 0:ECAT enables PDI takeover of MII
+ * management interface
+ * 1:ECAT claims exclusive access to MII
+ * management interface
+ */
+#define ESC_MIIM_ECAT_ACC_STAT_ACC_MASK (0x1U)
+#define ESC_MIIM_ECAT_ACC_STAT_ACC_SHIFT (0U)
+#define ESC_MIIM_ECAT_ACC_STAT_ACC_GET(x) (((uint8_t)(x) & ESC_MIIM_ECAT_ACC_STAT_ACC_MASK) >> ESC_MIIM_ECAT_ACC_STAT_ACC_SHIFT)
+
+/* Bitfield definition for register: MIIM_PDI_ACC_STAT */
+/*
+ * FORCE (RO)
+ *
+ * Force PDI Access State:
+ * 0:Do not change Bit 0x0517[0]
+ * 1:Reset Bit 0x0517[0] to 0
+ */
+#define ESC_MIIM_PDI_ACC_STAT_FORCE_MASK (0x2U)
+#define ESC_MIIM_PDI_ACC_STAT_FORCE_SHIFT (1U)
+#define ESC_MIIM_PDI_ACC_STAT_FORCE_GET(x) (((uint8_t)(x) & ESC_MIIM_PDI_ACC_STAT_FORCE_MASK) >> ESC_MIIM_PDI_ACC_STAT_FORCE_SHIFT)
+
+/*
+ * ACC (RW)
+ *
+ * Access to MII management:
+ * 0:ECAT has access to MII management
+ * 1:PDI has access to MII management
+ */
+#define ESC_MIIM_PDI_ACC_STAT_ACC_MASK (0x1U)
+#define ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT (0U)
+#define ESC_MIIM_PDI_ACC_STAT_ACC_SET(x) (((uint8_t)(x) << ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT) & ESC_MIIM_PDI_ACC_STAT_ACC_MASK)
+#define ESC_MIIM_PDI_ACC_STAT_ACC_GET(x) (((uint8_t)(x) & ESC_MIIM_PDI_ACC_STAT_ACC_MASK) >> ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT)
+
+/* Bitfield definition for register array: PHY_STAT */
+/*
+ * PCU (RW)
+ *
+ * PHY configuration updated:
+ * 0:No update
+ * 1:PHY configuration was updated
+ * Cleared by writing any value to at least one
+ * of the PHY Port y Status registers.
+ */
+#define ESC_PHY_STAT_PCU_MASK (0x20U)
+#define ESC_PHY_STAT_PCU_SHIFT (5U)
+#define ESC_PHY_STAT_PCU_SET(x) (((uint8_t)(x) << ESC_PHY_STAT_PCU_SHIFT) & ESC_PHY_STAT_PCU_MASK)
+#define ESC_PHY_STAT_PCU_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_PCU_MASK) >> ESC_PHY_STAT_PCU_SHIFT)
+
+/*
+ * LPE (RO)
+ *
+ * Link partner error:
+ * 0:No error detected
+ * 1:Link partner error
+ */
+#define ESC_PHY_STAT_LPE_MASK (0x10U)
+#define ESC_PHY_STAT_LPE_SHIFT (4U)
+#define ESC_PHY_STAT_LPE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LPE_MASK) >> ESC_PHY_STAT_LPE_SHIFT)
+
+/*
+ * RE (RW)
+ *
+ * Read error:
+ * 0:No read error occurred
+ * 1:A read error has occurred
+ * Cleared by writing any value to at least one
+ * of the PHY Port y Status registers.
+ */
+#define ESC_PHY_STAT_RE_MASK (0x8U)
+#define ESC_PHY_STAT_RE_SHIFT (3U)
+#define ESC_PHY_STAT_RE_SET(x) (((uint8_t)(x) << ESC_PHY_STAT_RE_SHIFT) & ESC_PHY_STAT_RE_MASK)
+#define ESC_PHY_STAT_RE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_RE_MASK) >> ESC_PHY_STAT_RE_SHIFT)
+
+/*
+ * LSE (RO)
+ *
+ * Link status error:
+ * 0:No error
+ * 1:Link error, link inhibited
+ */
+#define ESC_PHY_STAT_LSE_MASK (0x4U)
+#define ESC_PHY_STAT_LSE_SHIFT (2U)
+#define ESC_PHY_STAT_LSE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LSE_MASK) >> ESC_PHY_STAT_LSE_SHIFT)
+
+/*
+ * LS (RO)
+ *
+ * Link status (100 Mbit/s, Full Duplex, Auto
+ * negotiation):
+ * 0:No link
+ * 1:Link detected
+ */
+#define ESC_PHY_STAT_LS_MASK (0x2U)
+#define ESC_PHY_STAT_LS_SHIFT (1U)
+#define ESC_PHY_STAT_LS_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LS_MASK) >> ESC_PHY_STAT_LS_SHIFT)
+
+/*
+ * PLS (RO)
+ *
+ * Physical link status (PHY status register 1.2):
+ * 0:No physical link
+ * 1:Physical link detected
+ */
+#define ESC_PHY_STAT_PLS_MASK (0x1U)
+#define ESC_PHY_STAT_PLS_SHIFT (0U)
+#define ESC_PHY_STAT_PLS_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_PLS_MASK) >> ESC_PHY_STAT_PLS_SHIFT)
+
+/* Bitfield definition for register of struct array FMMU: LOGIC_START_ADDR */
+/*
+ * ADDR (RO)
+ *
+ * Logical start address within the EtherCAT
+ * Address Space.
+ */
+#define ESC_FMMU_LOGIC_START_ADDR_ADDR_MASK (0xFFFFFFFFUL)
+#define ESC_FMMU_LOGIC_START_ADDR_ADDR_SHIFT (0U)
+#define ESC_FMMU_LOGIC_START_ADDR_ADDR_GET(x) (((uint32_t)(x) & ESC_FMMU_LOGIC_START_ADDR_ADDR_MASK) >> ESC_FMMU_LOGIC_START_ADDR_ADDR_SHIFT)
+
+/* Bitfield definition for register of struct array FMMU: LENGTH */
+/*
+ * OFFSET (RO)
+ *
+ * Offset from the first logical FMMU byte to the
+ * last FMMU byte + 1 (e.g., if two bytes are
+ * used, then this parameter shall contain 2)
+ */
+#define ESC_FMMU_LENGTH_OFFSET_MASK (0xFFFFU)
+#define ESC_FMMU_LENGTH_OFFSET_SHIFT (0U)
+#define ESC_FMMU_LENGTH_OFFSET_GET(x) (((uint16_t)(x) & ESC_FMMU_LENGTH_OFFSET_MASK) >> ESC_FMMU_LENGTH_OFFSET_SHIFT)
+
+/* Bitfield definition for register of struct array FMMU: LOGIC_START_BIT */
+/*
+ * START (RO)
+ *
+ * Logical starting bit that shall be mapped (bits
+ * are counted from least significant bit 0 to
+ * most significant bit 7)
+ */
+#define ESC_FMMU_LOGIC_START_BIT_START_MASK (0x7U)
+#define ESC_FMMU_LOGIC_START_BIT_START_SHIFT (0U)
+#define ESC_FMMU_LOGIC_START_BIT_START_GET(x) (((uint8_t)(x) & ESC_FMMU_LOGIC_START_BIT_START_MASK) >> ESC_FMMU_LOGIC_START_BIT_START_SHIFT)
+
+/* Bitfield definition for register of struct array FMMU: LOGIC_STOP_BIT */
+/*
+ * STOP (RO)
+ *
+ * Last logical bit that shall be mapped (bits are
+ * counted from least significant bit 0 to most
+ * significant bit 7)
+ */
+#define ESC_FMMU_LOGIC_STOP_BIT_STOP_MASK (0x7U)
+#define ESC_FMMU_LOGIC_STOP_BIT_STOP_SHIFT (0U)
+#define ESC_FMMU_LOGIC_STOP_BIT_STOP_GET(x) (((uint8_t)(x) & ESC_FMMU_LOGIC_STOP_BIT_STOP_MASK) >> ESC_FMMU_LOGIC_STOP_BIT_STOP_SHIFT)
+
+/* Bitfield definition for register of struct array FMMU: PHYSICAL_START_ADDR */
+/*
+ * ADDR (RO)
+ *
+ * Physical Start Address (mapped to logical
+ * Start address)
+ */
+#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_MASK (0xFFFFU)
+#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_SHIFT (0U)
+#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_FMMU_PHYSICAL_START_ADDR_ADDR_MASK) >> ESC_FMMU_PHYSICAL_START_ADDR_ADDR_SHIFT)
+
+/* Bitfield definition for register of struct array FMMU: PHYSICAL_START_BIT */
+/*
+ * START (RO)
+ *
+ * Physical starting bit as target of logical start
+ * bit mapping (bits are counted from least
+ * significant bit 0 to most significant bit 7)
+ */
+#define ESC_FMMU_PHYSICAL_START_BIT_START_MASK (0x7U)
+#define ESC_FMMU_PHYSICAL_START_BIT_START_SHIFT (0U)
+#define ESC_FMMU_PHYSICAL_START_BIT_START_GET(x) (((uint8_t)(x) & ESC_FMMU_PHYSICAL_START_BIT_START_MASK) >> ESC_FMMU_PHYSICAL_START_BIT_START_SHIFT)
+
+/* Bitfield definition for register of struct array FMMU: TYPE */
+/*
+ * MAP_WR (RO)
+ *
+ * 0:Ignore mapping for write accesses
+ * 1:Use mapping for write accesses
+ */
+#define ESC_FMMU_TYPE_MAP_WR_MASK (0x2U)
+#define ESC_FMMU_TYPE_MAP_WR_SHIFT (1U)
+#define ESC_FMMU_TYPE_MAP_WR_GET(x) (((uint8_t)(x) & ESC_FMMU_TYPE_MAP_WR_MASK) >> ESC_FMMU_TYPE_MAP_WR_SHIFT)
+
+/*
+ * MAP_RD (RO)
+ *
+ * 0:Ignore mapping for read accesses
+ * 1:Use mapping for read accesses
+ */
+#define ESC_FMMU_TYPE_MAP_RD_MASK (0x1U)
+#define ESC_FMMU_TYPE_MAP_RD_SHIFT (0U)
+#define ESC_FMMU_TYPE_MAP_RD_GET(x) (((uint8_t)(x) & ESC_FMMU_TYPE_MAP_RD_MASK) >> ESC_FMMU_TYPE_MAP_RD_SHIFT)
+
+/* Bitfield definition for register of struct array FMMU: ACTIVATE */
+/*
+ * ACT (RO)
+ *
+ * 0:FMMU deactivated
+ * 1:FMMU activated. FMMU checks
+ * logically addressed blocks to be
+ * mapped according to configured
+ * mapping
+ */
+#define ESC_FMMU_ACTIVATE_ACT_MASK (0x1U)
+#define ESC_FMMU_ACTIVATE_ACT_SHIFT (0U)
+#define ESC_FMMU_ACTIVATE_ACT_GET(x) (((uint8_t)(x) & ESC_FMMU_ACTIVATE_ACT_MASK) >> ESC_FMMU_ACTIVATE_ACT_SHIFT)
+
+/* Bitfield definition for register of struct array SYNCM: PHYSICAL_START_ADDR */
+/*
+ * ADDR (RO)
+ *
+ * First byte that will be handled by
+ * SyncManager
+ */
+#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_MASK (0xFFFFU)
+#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_SHIFT (0U)
+#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_MASK) >> ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_SHIFT)
+
+/* Bitfield definition for register of struct array SYNCM: LENGTH */
+/*
+ * LEN (RO)
+ *
+ * Number of bytes assigned to SyncManager
+ * (shall be greater than 1, otherwise
+ * SyncManager is not activated. If set to 1, only
+ * Watchdog Trigger is generated if configured)
+ */
+#define ESC_SYNCM_LENGTH_LEN_MASK (0xFFFFU)
+#define ESC_SYNCM_LENGTH_LEN_SHIFT (0U)
+#define ESC_SYNCM_LENGTH_LEN_GET(x) (((uint16_t)(x) & ESC_SYNCM_LENGTH_LEN_MASK) >> ESC_SYNCM_LENGTH_LEN_SHIFT)
+
+/* Bitfield definition for register of struct array SYNCM: CONTROL */
+/*
+ * WDG_TRG_EN (RO)
+ *
+ * Watchdog Trigger Enable:
+ * 0:Disabled
+ * 1:Enabled
+ */
+#define ESC_SYNCM_CONTROL_WDG_TRG_EN_MASK (0x40U)
+#define ESC_SYNCM_CONTROL_WDG_TRG_EN_SHIFT (6U)
+#define ESC_SYNCM_CONTROL_WDG_TRG_EN_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_WDG_TRG_EN_MASK) >> ESC_SYNCM_CONTROL_WDG_TRG_EN_SHIFT)
+
+/*
+ * INT_AL (RO)
+ *
+ * Interrupt in AL Event Request Register:
+ * 0:Disabled
+ * 1:Enabled
+ */
+#define ESC_SYNCM_CONTROL_INT_AL_MASK (0x20U)
+#define ESC_SYNCM_CONTROL_INT_AL_SHIFT (5U)
+#define ESC_SYNCM_CONTROL_INT_AL_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_INT_AL_MASK) >> ESC_SYNCM_CONTROL_INT_AL_SHIFT)
+
+/*
+ * INT_ECAT (RO)
+ *
+ * Interrupt in ECAT Event Request Register:
+ * 0:Disabled
+ * 1:Enabled
+ */
+#define ESC_SYNCM_CONTROL_INT_ECAT_MASK (0x10U)
+#define ESC_SYNCM_CONTROL_INT_ECAT_SHIFT (4U)
+#define ESC_SYNCM_CONTROL_INT_ECAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_INT_ECAT_MASK) >> ESC_SYNCM_CONTROL_INT_ECAT_SHIFT)
+
+/*
+ * DIR (RO)
+ *
+ * Direction:
+ * 00:Read:ECAT read access, PDI write
+ * access.
+ * 01:Write:ECAT write access, PDI read
+ * access.
+ * 10:Reserved
+ * 11:Reserved
+ */
+#define ESC_SYNCM_CONTROL_DIR_MASK (0xCU)
+#define ESC_SYNCM_CONTROL_DIR_SHIFT (2U)
+#define ESC_SYNCM_CONTROL_DIR_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_DIR_MASK) >> ESC_SYNCM_CONTROL_DIR_SHIFT)
+
+/*
+ * OP_MODE (RO)
+ *
+ * Operation Mode:
+ * 00:Buffered (3 buffer mode)
+ * 01:Reserved
+ * 10:Mailbox (Single buffer mode)
+ * 11:Reserved
+ */
+#define ESC_SYNCM_CONTROL_OP_MODE_MASK (0x3U)
+#define ESC_SYNCM_CONTROL_OP_MODE_SHIFT (0U)
+#define ESC_SYNCM_CONTROL_OP_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_OP_MODE_MASK) >> ESC_SYNCM_CONTROL_OP_MODE_SHIFT)
+
+/* Bitfield definition for register of struct array SYNCM: STATUS */
+/*
+ * WB_INUSE (RO)
+ *
+ * Write buffer in use (opened)
+ */
+#define ESC_SYNCM_STATUS_WB_INUSE_MASK (0x80U)
+#define ESC_SYNCM_STATUS_WB_INUSE_SHIFT (7U)
+#define ESC_SYNCM_STATUS_WB_INUSE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_WB_INUSE_MASK) >> ESC_SYNCM_STATUS_WB_INUSE_SHIFT)
+
+/*
+ * RB_INUSE (RO)
+ *
+ * Read buffer in use (opened)
+ */
+#define ESC_SYNCM_STATUS_RB_INUSE_MASK (0x40U)
+#define ESC_SYNCM_STATUS_RB_INUSE_SHIFT (6U)
+#define ESC_SYNCM_STATUS_RB_INUSE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_RB_INUSE_MASK) >> ESC_SYNCM_STATUS_RB_INUSE_SHIFT)
+
+/*
+ * BUF_MODE (RO)
+ *
+ * Buffered mode:buffer status (last written
+ * buffer):
+ * 00:1
+ * st buffer
+ * 01:2
+ * nd buffer
+ * 10:3
+ * rd buffer
+ * 11:(no buffer written)
+ * Mailbox mode:reserved
+ */
+#define ESC_SYNCM_STATUS_BUF_MODE_MASK (0x30U)
+#define ESC_SYNCM_STATUS_BUF_MODE_SHIFT (4U)
+#define ESC_SYNCM_STATUS_BUF_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_BUF_MODE_MASK) >> ESC_SYNCM_STATUS_BUF_MODE_SHIFT)
+
+/*
+ * MBX_MODE (RO)
+ *
+ * Mailbox mode:mailbox status:
+ * 0:Mailbox empty
+ * 1:Mailbox full
+ * Buffered mode:reserved
+ */
+#define ESC_SYNCM_STATUS_MBX_MODE_MASK (0x8U)
+#define ESC_SYNCM_STATUS_MBX_MODE_SHIFT (3U)
+#define ESC_SYNCM_STATUS_MBX_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_MBX_MODE_MASK) >> ESC_SYNCM_STATUS_MBX_MODE_SHIFT)
+
+/*
+ * INT_RD (RO)
+ *
+ * Interrupt Read:
+ * 1:Interrupt after buffer was completely and
+ * successfully read
+ * 0:Interrupt cleared after first byte of buffer
+ * was written
+ * NOTE:This interrupt is signalled to the writing
+ * side if enabled in the SM Control register
+ */
+#define ESC_SYNCM_STATUS_INT_RD_MASK (0x2U)
+#define ESC_SYNCM_STATUS_INT_RD_SHIFT (1U)
+#define ESC_SYNCM_STATUS_INT_RD_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_INT_RD_MASK) >> ESC_SYNCM_STATUS_INT_RD_SHIFT)
+
+/*
+ * INT_WR (RO)
+ *
+ * Interrupt Write:
+ * 1:Interrupt after buffer was completely and
+ * successfully written
+ * 0:Interrupt cleared after first byte of buffer
+ * was read
+ * NOTE:This interrupt is signalled to the reading
+ * side if enabled in the SM Control register
+ */
+#define ESC_SYNCM_STATUS_INT_WR_MASK (0x1U)
+#define ESC_SYNCM_STATUS_INT_WR_SHIFT (0U)
+#define ESC_SYNCM_STATUS_INT_WR_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_INT_WR_MASK) >> ESC_SYNCM_STATUS_INT_WR_SHIFT)
+
+/* Bitfield definition for register of struct array SYNCM: ACTIVATE */
+/*
+ * LATCH_PDI (RO)
+ *
+ * Latch Event PDI:
+ * 0:No
+ * 1:Generate Latch events when PDI issues
+ * a buffer exchange or when PDI
+ * accesses buffer start address
+ */
+#define ESC_SYNCM_ACTIVATE_LATCH_PDI_MASK (0x80U)
+#define ESC_SYNCM_ACTIVATE_LATCH_PDI_SHIFT (7U)
+#define ESC_SYNCM_ACTIVATE_LATCH_PDI_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_LATCH_PDI_MASK) >> ESC_SYNCM_ACTIVATE_LATCH_PDI_SHIFT)
+
+/*
+ * LATCH_ECAT (RO)
+ *
+ * Latch Event ECAT:
+ * 0:No
+ * 1:Generate Latch event when EtherCAT
+ * master issues a buffer exchange
+ */
+#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_MASK (0x40U)
+#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_SHIFT (6U)
+#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_LATCH_ECAT_MASK) >> ESC_SYNCM_ACTIVATE_LATCH_ECAT_SHIFT)
+
+/*
+ * REPEAT (RO)
+ *
+ * Repeat Request:
+ * A toggle of Repeat Request means that a
+ * mailbox retry is needed (primarily used in
+ * conjunction with ECAT Read Mailbox)
+ */
+#define ESC_SYNCM_ACTIVATE_REPEAT_MASK (0x2U)
+#define ESC_SYNCM_ACTIVATE_REPEAT_SHIFT (1U)
+#define ESC_SYNCM_ACTIVATE_REPEAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_REPEAT_MASK) >> ESC_SYNCM_ACTIVATE_REPEAT_SHIFT)
+
+/*
+ * EN (RW)
+ *
+ * SyncManager Enable/Disable:
+ * 0:Disable:Access to Memory without
+ * SyncManager control
+ * 1:Enable:SyncManager is active and
+ * controls Memory area set in
+ * configuration
+ */
+#define ESC_SYNCM_ACTIVATE_EN_MASK (0x1U)
+#define ESC_SYNCM_ACTIVATE_EN_SHIFT (0U)
+#define ESC_SYNCM_ACTIVATE_EN_SET(x) (((uint8_t)(x) << ESC_SYNCM_ACTIVATE_EN_SHIFT) & ESC_SYNCM_ACTIVATE_EN_MASK)
+#define ESC_SYNCM_ACTIVATE_EN_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_EN_MASK) >> ESC_SYNCM_ACTIVATE_EN_SHIFT)
+
+/* Bitfield definition for register of struct array SYNCM: PDI_CTRL */
+/*
+ * REPEAT_ACK (RW)
+ *
+ * Repeat Ack:
+ * If this is set to the same value as that set by
+ * Repeat Request, the PDI acknowledges the
+ * execution of a previous set Repeat request.
+ */
+#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK (0x2U)
+#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT (1U)
+#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT) & ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK)
+#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK) >> ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT)
+
+/*
+ * DEACT (RW)
+ *
+ * Deactivate SyncManager:
+ * Read:
+ * 0:Normal operation, SyncManager
+ * activated.
+ * 1:SyncManager deactivated and reset.
+ * SyncManager locks access to Memory
+ * area.
+ * Write:
+ * 0:Activate SyncManager
+ * 1:Request SyncManager deactivation
+ * NOTE:Writing 1 is delayed until the end of the
+ * frame, which is currently processed.
+ */
+#define ESC_SYNCM_PDI_CTRL_DEACT_MASK (0x1U)
+#define ESC_SYNCM_PDI_CTRL_DEACT_SHIFT (0U)
+#define ESC_SYNCM_PDI_CTRL_DEACT_SET(x) (((uint8_t)(x) << ESC_SYNCM_PDI_CTRL_DEACT_SHIFT) & ESC_SYNCM_PDI_CTRL_DEACT_MASK)
+#define ESC_SYNCM_PDI_CTRL_DEACT_GET(x) (((uint8_t)(x) & ESC_SYNCM_PDI_CTRL_DEACT_MASK) >> ESC_SYNCM_PDI_CTRL_DEACT_SHIFT)
+
+/* Bitfield definition for register array: RCV_TIME */
+/*
+ * LT (RO)
+ *
+ * Local time at the beginning of the last receive
+ * frame containing a write access to register
+ * 0x0900.
+ */
+#define ESC_RCV_TIME_LT_MASK (0xFFFFFF00UL)
+#define ESC_RCV_TIME_LT_SHIFT (8U)
+#define ESC_RCV_TIME_LT_GET(x) (((uint32_t)(x) & ESC_RCV_TIME_LT_MASK) >> ESC_RCV_TIME_LT_SHIFT)
+
+/*
+ * REQ (RO)
+ *
+ * Write:
+ * A write access to register 0x0900 with
+ * BWR or FPWR latches the local time at
+ * the beginning of the receive frame (start
+ * first bit of preamble) at each port.
+ * Write (ESC20, ET1200 exception):
+ * A write access latches the local time at
+ * the beginning of the receive frame at
+ * port 0. It enables the time stamping at
+ * the other ports.
+ * Read:
+ * Local time at the beginning of the last
+ * receive frame containing a write access
+ * to this register.
+ * NOTE:FPWR requires an address match for
+ * accessing this register like any FPWR command.
+ * All write commands with address match will
+ * increment the working counter (e.g., APWR), but
+ * they will not trigger receive time latching.
+ */
+#define ESC_RCV_TIME_REQ_MASK (0xFFU)
+#define ESC_RCV_TIME_REQ_SHIFT (0U)
+#define ESC_RCV_TIME_REQ_GET(x) (((uint32_t)(x) & ESC_RCV_TIME_REQ_MASK) >> ESC_RCV_TIME_REQ_SHIFT)
+
+/* Bitfield definition for register: SYS_TIME */
+/*
+ * ST (RW)
+ *
+ */
+#define ESC_SYS_TIME_ST_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_SYS_TIME_ST_SHIFT (0U)
+#define ESC_SYS_TIME_ST_SET(x) (((uint64_t)(x) << ESC_SYS_TIME_ST_SHIFT) & ESC_SYS_TIME_ST_MASK)
+#define ESC_SYS_TIME_ST_GET(x) (((uint64_t)(x) & ESC_SYS_TIME_ST_MASK) >> ESC_SYS_TIME_ST_SHIFT)
+
+/* Bitfield definition for register: RCVT_ECAT_PU */
+/*
+ * LT (RO)
+ *
+ * Local time at the beginning of a frame (start
+ * first bit of preamble) received at the ECAT
+ * Processing Unit containing a write access to
+ * register 0x0900
+ * NOTE:E.g., if port 0 is open, this register reflects
+ * the Receive Time Port 0 as a 64 Bit value.
+ * Any valid EtherCAT write access to register
+ * 0x0900 triggers latching, not only BWR/FPWR
+ * commands as with register 0x0900.
+ */
+#define ESC_RCVT_ECAT_PU_LT_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_RCVT_ECAT_PU_LT_SHIFT (0U)
+#define ESC_RCVT_ECAT_PU_LT_GET(x) (((uint64_t)(x) & ESC_RCVT_ECAT_PU_LT_MASK) >> ESC_RCVT_ECAT_PU_LT_SHIFT)
+
+/* Bitfield definition for register: SYS_TIME_OFFSET */
+/*
+ * OFFSET (RW)
+ *
+ * Difference between local time and System
+ * Time. Offset is added to the local time.
+ */
+#define ESC_SYS_TIME_OFFSET_OFFSET_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_SYS_TIME_OFFSET_OFFSET_SHIFT (0U)
+#define ESC_SYS_TIME_OFFSET_OFFSET_SET(x) (((uint64_t)(x) << ESC_SYS_TIME_OFFSET_OFFSET_SHIFT) & ESC_SYS_TIME_OFFSET_OFFSET_MASK)
+#define ESC_SYS_TIME_OFFSET_OFFSET_GET(x) (((uint64_t)(x) & ESC_SYS_TIME_OFFSET_OFFSET_MASK) >> ESC_SYS_TIME_OFFSET_OFFSET_SHIFT)
+
+/* Bitfield definition for register: SYS_TIME_DELAY */
+/*
+ * DLY (RW)
+ *
+ * Delay between Reference Clock and the
+ * ESC
+ */
+#define ESC_SYS_TIME_DELAY_DLY_MASK (0xFFFFFFFFUL)
+#define ESC_SYS_TIME_DELAY_DLY_SHIFT (0U)
+#define ESC_SYS_TIME_DELAY_DLY_SET(x) (((uint32_t)(x) << ESC_SYS_TIME_DELAY_DLY_SHIFT) & ESC_SYS_TIME_DELAY_DLY_MASK)
+#define ESC_SYS_TIME_DELAY_DLY_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DELAY_DLY_MASK) >> ESC_SYS_TIME_DELAY_DLY_SHIFT)
+
+/* Bitfield definition for register: SYS_TIME_DIFF */
+/*
+ * DIFF (RO)
+ *
+ * 0:Local copy of System Time less than
+ * received System Time
+ * 1:Local copy of System Time greater than
+ * or equal to received System Time
+ */
+#define ESC_SYS_TIME_DIFF_DIFF_MASK (0x80000000UL)
+#define ESC_SYS_TIME_DIFF_DIFF_SHIFT (31U)
+#define ESC_SYS_TIME_DIFF_DIFF_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DIFF_DIFF_MASK) >> ESC_SYS_TIME_DIFF_DIFF_SHIFT)
+
+/*
+ * NUM (RO)
+ *
+ * Mean difference between local copy of
+ * System Time and received System Time
+ * values
+ * Difference = Received System Time –
+ * local copy of System Time
+ */
+#define ESC_SYS_TIME_DIFF_NUM_MASK (0x7FFFFFFFUL)
+#define ESC_SYS_TIME_DIFF_NUM_SHIFT (0U)
+#define ESC_SYS_TIME_DIFF_NUM_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DIFF_NUM_MASK) >> ESC_SYS_TIME_DIFF_NUM_SHIFT)
+
+/* Bitfield definition for register: SPD_CNT_START */
+/*
+ * BW (RW)
+ *
+ * Bandwidth for adjustment of local copy of
+ * System Time (larger values → smaller
+ * bandwidth and smoother adjustment)
+ * A write access resets System Time
+ * Difference (0x092C:0x092F) and Speed
+ * Counter Diff (0x0932:0x0933).
+ * Valid values:0x0080 to 0x3FFF
+ */
+#define ESC_SPD_CNT_START_BW_MASK (0x7FFFU)
+#define ESC_SPD_CNT_START_BW_SHIFT (0U)
+#define ESC_SPD_CNT_START_BW_SET(x) (((uint16_t)(x) << ESC_SPD_CNT_START_BW_SHIFT) & ESC_SPD_CNT_START_BW_MASK)
+#define ESC_SPD_CNT_START_BW_GET(x) (((uint16_t)(x) & ESC_SPD_CNT_START_BW_MASK) >> ESC_SPD_CNT_START_BW_SHIFT)
+
+/* Bitfield definition for register: SPD_CNT_DIFF */
+/*
+ * DIFF (RO)
+ *
+ * Representation of the deviation between
+ * local clock period and Reference Clock's
+ * clock period (representation:two's
+ * complement)
+ * Range:±(Speed Counter Start – 0x7F)
+ */
+#define ESC_SPD_CNT_DIFF_DIFF_MASK (0xFFFFU)
+#define ESC_SPD_CNT_DIFF_DIFF_SHIFT (0U)
+#define ESC_SPD_CNT_DIFF_DIFF_GET(x) (((uint16_t)(x) & ESC_SPD_CNT_DIFF_DIFF_MASK) >> ESC_SPD_CNT_DIFF_DIFF_SHIFT)
+
+/* Bitfield definition for register: SYS_TIME_DIFF_FD */
+/*
+ * DEPTH (RW)
+ *
+ * Filter depth for averaging the received
+ * System Time deviation
+ * IP Core since V2.2.0/V2.02a:
+ * A write access resets System Time
+ * Difference (0x092C:0x092F)
+ */
+#define ESC_SYS_TIME_DIFF_FD_DEPTH_MASK (0xFU)
+#define ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT (0U)
+#define ESC_SYS_TIME_DIFF_FD_DEPTH_SET(x) (((uint8_t)(x) << ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT) & ESC_SYS_TIME_DIFF_FD_DEPTH_MASK)
+#define ESC_SYS_TIME_DIFF_FD_DEPTH_GET(x) (((uint8_t)(x) & ESC_SYS_TIME_DIFF_FD_DEPTH_MASK) >> ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT)
+
+/* Bitfield definition for register: SPD_CNT_FD */
+/*
+ * DEPTH (RW)
+ *
+ * Filter depth for averaging the clock period
+ * deviation
+ * IP Core since V2.2.0/V2.02a:
+ * A write access resets the internal speed
+ * counter filter
+ */
+#define ESC_SPD_CNT_FD_DEPTH_MASK (0xFU)
+#define ESC_SPD_CNT_FD_DEPTH_SHIFT (0U)
+#define ESC_SPD_CNT_FD_DEPTH_SET(x) (((uint8_t)(x) << ESC_SPD_CNT_FD_DEPTH_SHIFT) & ESC_SPD_CNT_FD_DEPTH_MASK)
+#define ESC_SPD_CNT_FD_DEPTH_GET(x) (((uint8_t)(x) & ESC_SPD_CNT_FD_DEPTH_MASK) >> ESC_SPD_CNT_FD_DEPTH_SHIFT)
+
+/* Bitfield definition for register: RCV_TIME_LM */
+/*
+ * LATCH_MODE (RO)
+ *
+ * Receive Time Latch Mode:
+ * 0:Forwarding mode (used if frames are
+ * entering the ESC at port 0 first):
+ * Receive time stamps of ports 1-3 are
+ * enabled after the write access to
+ * 0x0900, so the following frame at ports
+ * 1-3 will be time stamped (this is typically
+ * the write frame to 0x0900 coming back
+ * from the network behind the ESC).
+ * 1:Reverse mode (used if frames are
+ * entering ESC at port 1-3 first):
+ * Receive time stamps of ports 1-3 are
+ * immediately taken over from the internal
+ * hidden time stamp registers, so the
+ * previous frame entering the ESC at
+ * ports 1-3 will be time stamped when the
+ * write frame to 0x0900 enters port 0 (the
+ * previous frame at ports 1-3 is typically
+ * the write frame to 0x0900 coming from
+ * the master, which will enable time
+ * stamp
+ */
+#define ESC_RCV_TIME_LM_LATCH_MODE_MASK (0x1U)
+#define ESC_RCV_TIME_LM_LATCH_MODE_SHIFT (0U)
+#define ESC_RCV_TIME_LM_LATCH_MODE_GET(x) (((uint8_t)(x) & ESC_RCV_TIME_LM_LATCH_MODE_MASK) >> ESC_RCV_TIME_LM_LATCH_MODE_SHIFT)
+
+/* Bitfield definition for register: CYC_UNIT_CTRL */
+/*
+ * LATCHI1 (RO)
+ *
+ * Latch In unit 1:
+ * 0:ECAT-controlled
+ * 1:PDI-controlled
+ * NOTE:Latch interrupt is routed to ECAT/PDI
+ * depending on this setting
+ */
+#define ESC_CYC_UNIT_CTRL_LATCHI1_MASK (0x20U)
+#define ESC_CYC_UNIT_CTRL_LATCHI1_SHIFT (5U)
+#define ESC_CYC_UNIT_CTRL_LATCHI1_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_LATCHI1_MASK) >> ESC_CYC_UNIT_CTRL_LATCHI1_SHIFT)
+
+/*
+ * LATCHI0 (RO)
+ *
+ * Latch In unit 0:
+ * 0:ECAT-controlled
+ * 1:PDI-controlled
+ * NOTE:Latch interrupt is routed to ECAT/PDI
+ * depending on this setting.
+ * Always 1 (PDI-controlled) if System Time is PDIcontrolled.
+ */
+#define ESC_CYC_UNIT_CTRL_LATCHI0_MASK (0x10U)
+#define ESC_CYC_UNIT_CTRL_LATCHI0_SHIFT (4U)
+#define ESC_CYC_UNIT_CTRL_LATCHI0_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_LATCHI0_MASK) >> ESC_CYC_UNIT_CTRL_LATCHI0_SHIFT)
+
+/*
+ * SYNCO (RO)
+ *
+ * Cyclic Unit and SYNC0 out unit control:
+ * 0:ECAT-controlled
+ * 1:PDI-controlled
+ */
+#define ESC_CYC_UNIT_CTRL_SYNCO_MASK (0x1U)
+#define ESC_CYC_UNIT_CTRL_SYNCO_SHIFT (0U)
+#define ESC_CYC_UNIT_CTRL_SYNCO_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_SYNCO_MASK) >> ESC_CYC_UNIT_CTRL_SYNCO_SHIFT)
+
+/* Bitfield definition for register: SYNCO_ACT */
+/*
+ * SSDP (RW)
+ *
+ * SyncSignal debug pulse (Vasily bit):
+ * 0:Deactivated
+ * 1:Immediately generate one ping only on
+ * SYNC0-1 according to 0x0981[2:1 for
+ * debugging
+ * This bit is self-clearing, always read 0.
+ * All pulses are generated at the same time,
+ * the cycle time is ignored. The configured
+ * pulse length is used.
+ */
+#define ESC_SYNCO_ACT_SSDP_MASK (0x80U)
+#define ESC_SYNCO_ACT_SSDP_SHIFT (7U)
+#define ESC_SYNCO_ACT_SSDP_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SSDP_SHIFT) & ESC_SYNCO_ACT_SSDP_MASK)
+#define ESC_SYNCO_ACT_SSDP_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SSDP_MASK) >> ESC_SYNCO_ACT_SSDP_SHIFT)
+
+/*
+ * NFC (RW)
+ *
+ * Near future configuration (approx.):
+ * 0:½ DC width future (231 ns or 263 ns)
+ * 1:~2.1 sec. future (231 ns)
+ */
+#define ESC_SYNCO_ACT_NFC_MASK (0x40U)
+#define ESC_SYNCO_ACT_NFC_SHIFT (6U)
+#define ESC_SYNCO_ACT_NFC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_NFC_SHIFT) & ESC_SYNCO_ACT_NFC_MASK)
+#define ESC_SYNCO_ACT_NFC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_NFC_MASK) >> ESC_SYNCO_ACT_NFC_SHIFT)
+
+/*
+ * STPC (RW)
+ *
+ * Start Time plausibility check:
+ * 0:Disabled. SyncSignal generation if Start
+ * Time is reached.
+ * 1:Immediate SyncSignal generation if
+ * Start Time is outside near future (see
+ * 0x0981[6])
+ */
+#define ESC_SYNCO_ACT_STPC_MASK (0x20U)
+#define ESC_SYNCO_ACT_STPC_SHIFT (5U)
+#define ESC_SYNCO_ACT_STPC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_STPC_SHIFT) & ESC_SYNCO_ACT_STPC_MASK)
+#define ESC_SYNCO_ACT_STPC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_STPC_MASK) >> ESC_SYNCO_ACT_STPC_SHIFT)
+
+/*
+ * EXT (RW)
+ *
+ * Extension of Start Time Cyclic Operation
+ * (0x0990:0x0993):
+ * 0:No extension
+ * 1:Extend 32 bit written Start Time to 64 bit
+ */
+#define ESC_SYNCO_ACT_EXT_MASK (0x10U)
+#define ESC_SYNCO_ACT_EXT_SHIFT (4U)
+#define ESC_SYNCO_ACT_EXT_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_EXT_SHIFT) & ESC_SYNCO_ACT_EXT_MASK)
+#define ESC_SYNCO_ACT_EXT_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_EXT_MASK) >> ESC_SYNCO_ACT_EXT_SHIFT)
+
+/*
+ * AC (RW)
+ *
+ * Auto-activation by writing Start Time Cyclic
+ * Operation (0x0990:0x0997):
+ * 0:Disabled
+ * 1:Auto-activation enabled. 0x0981[0] is
+ * set automatically after Start Time is
+ * written.
+ */
+#define ESC_SYNCO_ACT_AC_MASK (0x8U)
+#define ESC_SYNCO_ACT_AC_SHIFT (3U)
+#define ESC_SYNCO_ACT_AC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_AC_SHIFT) & ESC_SYNCO_ACT_AC_MASK)
+#define ESC_SYNCO_ACT_AC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_AC_MASK) >> ESC_SYNCO_ACT_AC_SHIFT)
+
+/*
+ * SYNC1_GEN (RW)
+ *
+ * SYNC1 generation:
+ * 0:Deactivated
+ * 1:SYNC1 pulse is generated
+ */
+#define ESC_SYNCO_ACT_SYNC1_GEN_MASK (0x4U)
+#define ESC_SYNCO_ACT_SYNC1_GEN_SHIFT (2U)
+#define ESC_SYNCO_ACT_SYNC1_GEN_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SYNC1_GEN_SHIFT) & ESC_SYNCO_ACT_SYNC1_GEN_MASK)
+#define ESC_SYNCO_ACT_SYNC1_GEN_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SYNC1_GEN_MASK) >> ESC_SYNCO_ACT_SYNC1_GEN_SHIFT)
+
+/*
+ * SYNC0_GEN (RW)
+ *
+ * SYNC0 generation:
+ * 0:Deactivated
+ * 1:SYNC0 pulse is generated
+ */
+#define ESC_SYNCO_ACT_SYNC0_GEN_MASK (0x2U)
+#define ESC_SYNCO_ACT_SYNC0_GEN_SHIFT (1U)
+#define ESC_SYNCO_ACT_SYNC0_GEN_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SYNC0_GEN_SHIFT) & ESC_SYNCO_ACT_SYNC0_GEN_MASK)
+#define ESC_SYNCO_ACT_SYNC0_GEN_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SYNC0_GEN_MASK) >> ESC_SYNCO_ACT_SYNC0_GEN_SHIFT)
+
+/*
+ * SOUA (RW)
+ *
+ * Sync Out Unit activation:
+ * 0:Deactivated
+ * 1:Activated
+ */
+#define ESC_SYNCO_ACT_SOUA_MASK (0x1U)
+#define ESC_SYNCO_ACT_SOUA_SHIFT (0U)
+#define ESC_SYNCO_ACT_SOUA_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SOUA_SHIFT) & ESC_SYNCO_ACT_SOUA_MASK)
+#define ESC_SYNCO_ACT_SOUA_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SOUA_MASK) >> ESC_SYNCO_ACT_SOUA_SHIFT)
+
+/* Bitfield definition for register: PULSE_LEN */
+/*
+ * LEN (RO)
+ *
+ * Pulse length of SyncSignals (in Units of
+ * 10ns)
+ * 0:Acknowledge mode:SyncSignal will be
+ * cleared by reading SYNC[1:0] Status
+ * register
+ */
+#define ESC_PULSE_LEN_LEN_MASK (0xFFFFU)
+#define ESC_PULSE_LEN_LEN_SHIFT (0U)
+#define ESC_PULSE_LEN_LEN_GET(x) (((uint16_t)(x) & ESC_PULSE_LEN_LEN_MASK) >> ESC_PULSE_LEN_LEN_SHIFT)
+
+/* Bitfield definition for register: ACT_STAT */
+/*
+ * CHK_RSLT (RO)
+ *
+ * Start Time Cyclic Operation (0x0990:0x0997)
+ * plausibility check result when Sync Out Unit
+ * was activated:
+ * 0:Start Time was within near future
+ * 1:Start Time was out of near future
+ * (0x0981[6])
+ */
+#define ESC_ACT_STAT_CHK_RSLT_MASK (0x4U)
+#define ESC_ACT_STAT_CHK_RSLT_SHIFT (2U)
+#define ESC_ACT_STAT_CHK_RSLT_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_CHK_RSLT_MASK) >> ESC_ACT_STAT_CHK_RSLT_SHIFT)
+
+/*
+ * SYNC1 (RO)
+ *
+ * SYNC1 activation state:
+ * 0:First SYNC1 pulse is not pending
+ * 1:First SYNC1 pulse is pending
+ */
+#define ESC_ACT_STAT_SYNC1_MASK (0x2U)
+#define ESC_ACT_STAT_SYNC1_SHIFT (1U)
+#define ESC_ACT_STAT_SYNC1_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_SYNC1_MASK) >> ESC_ACT_STAT_SYNC1_SHIFT)
+
+/*
+ * SYNC0 (RO)
+ *
+ * SYNC0 activation state:
+ * 0:First SYNC0 pulse is not pending
+ * 1:First SYNC0 pulse is pending
+ */
+#define ESC_ACT_STAT_SYNC0_MASK (0x1U)
+#define ESC_ACT_STAT_SYNC0_SHIFT (0U)
+#define ESC_ACT_STAT_SYNC0_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_SYNC0_MASK) >> ESC_ACT_STAT_SYNC0_SHIFT)
+
+/* Bitfield definition for register: SYNC0_STAT */
+/*
+ * ACK (RW)
+ *
+ * SYNC0 state for Acknowledge mode.
+ * SYNC0 in Acknowledge mode is cleared by
+ * reading this register from PDI, use only in
+ * Acknowledge mode
+ */
+#define ESC_SYNC0_STAT_ACK_MASK (0x1U)
+#define ESC_SYNC0_STAT_ACK_SHIFT (0U)
+#define ESC_SYNC0_STAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNC0_STAT_ACK_SHIFT) & ESC_SYNC0_STAT_ACK_MASK)
+#define ESC_SYNC0_STAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNC0_STAT_ACK_MASK) >> ESC_SYNC0_STAT_ACK_SHIFT)
+
+/* Bitfield definition for register: SYNC1_STAT */
+/*
+ * ACK (RW)
+ *
+ * SYNC1 state for Acknowledge mode.
+ * SYNC1 in Acknowledge mode is cleared by
+ * reading this register from PDI, use only in
+ * Acknowledge mode
+ */
+#define ESC_SYNC1_STAT_ACK_MASK (0x1U)
+#define ESC_SYNC1_STAT_ACK_SHIFT (0U)
+#define ESC_SYNC1_STAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNC1_STAT_ACK_SHIFT) & ESC_SYNC1_STAT_ACK_MASK)
+#define ESC_SYNC1_STAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNC1_STAT_ACK_MASK) >> ESC_SYNC1_STAT_ACK_SHIFT)
+
+/* Bitfield definition for register: START_TIME_CO */
+/*
+ * ST (RW)
+ *
+ * Write:Start time (System time) of cyclic
+ * operation in ns
+ * Read:System time of next SYNC0 pulse in
+ * ns
+ */
+#define ESC_START_TIME_CO_ST_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_START_TIME_CO_ST_SHIFT (0U)
+#define ESC_START_TIME_CO_ST_SET(x) (((uint64_t)(x) << ESC_START_TIME_CO_ST_SHIFT) & ESC_START_TIME_CO_ST_MASK)
+#define ESC_START_TIME_CO_ST_GET(x) (((uint64_t)(x) & ESC_START_TIME_CO_ST_MASK) >> ESC_START_TIME_CO_ST_SHIFT)
+
+/* Bitfield definition for register: NXT_SYNC1_PULSE */
+/*
+ * TIME (RO)
+ *
+ * System time of next SYNC1 pulse in ns
+ */
+#define ESC_NXT_SYNC1_PULSE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_NXT_SYNC1_PULSE_TIME_SHIFT (0U)
+#define ESC_NXT_SYNC1_PULSE_TIME_GET(x) (((uint64_t)(x) & ESC_NXT_SYNC1_PULSE_TIME_MASK) >> ESC_NXT_SYNC1_PULSE_TIME_SHIFT)
+
+/* Bitfield definition for register: SYNC0_CYC_TIME */
+/*
+ * CYC (RW)
+ *
+ * Time between two consecutive SYNC0
+ * pulses in ns.
+ * 0:Single shot mode, generate only one
+ * SYNC0 pulse.
+ */
+#define ESC_SYNC0_CYC_TIME_CYC_MASK (0xFFFFFFFFUL)
+#define ESC_SYNC0_CYC_TIME_CYC_SHIFT (0U)
+#define ESC_SYNC0_CYC_TIME_CYC_SET(x) (((uint32_t)(x) << ESC_SYNC0_CYC_TIME_CYC_SHIFT) & ESC_SYNC0_CYC_TIME_CYC_MASK)
+#define ESC_SYNC0_CYC_TIME_CYC_GET(x) (((uint32_t)(x) & ESC_SYNC0_CYC_TIME_CYC_MASK) >> ESC_SYNC0_CYC_TIME_CYC_SHIFT)
+
+/* Bitfield definition for register: SYNC1_CYC_TIME */
+/*
+ * CYC (RW)
+ *
+ * Time between SYNC0 pulse and SYNC1
+ * pulse in ns
+ */
+#define ESC_SYNC1_CYC_TIME_CYC_MASK (0xFFFFFFFFUL)
+#define ESC_SYNC1_CYC_TIME_CYC_SHIFT (0U)
+#define ESC_SYNC1_CYC_TIME_CYC_SET(x) (((uint32_t)(x) << ESC_SYNC1_CYC_TIME_CYC_SHIFT) & ESC_SYNC1_CYC_TIME_CYC_MASK)
+#define ESC_SYNC1_CYC_TIME_CYC_GET(x) (((uint32_t)(x) & ESC_SYNC1_CYC_TIME_CYC_MASK) >> ESC_SYNC1_CYC_TIME_CYC_SHIFT)
+
+/* Bitfield definition for register: LATCH0_CTRL */
+/*
+ * NEG_EDGE (RW)
+ *
+ * Latch0 negative edge:
+ * 0:Continuous Latch active
+ * 1:Single event (only first event active)
+ */
+#define ESC_LATCH0_CTRL_NEG_EDGE_MASK (0x2U)
+#define ESC_LATCH0_CTRL_NEG_EDGE_SHIFT (1U)
+#define ESC_LATCH0_CTRL_NEG_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH0_CTRL_NEG_EDGE_SHIFT) & ESC_LATCH0_CTRL_NEG_EDGE_MASK)
+#define ESC_LATCH0_CTRL_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_CTRL_NEG_EDGE_MASK) >> ESC_LATCH0_CTRL_NEG_EDGE_SHIFT)
+
+/*
+ * POS_EDGE (RW)
+ *
+ * Latch0 positive edge:
+ * 0:Continuous Latch active
+ * 1:Single event (only first event active)
+ */
+#define ESC_LATCH0_CTRL_POS_EDGE_MASK (0x1U)
+#define ESC_LATCH0_CTRL_POS_EDGE_SHIFT (0U)
+#define ESC_LATCH0_CTRL_POS_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH0_CTRL_POS_EDGE_SHIFT) & ESC_LATCH0_CTRL_POS_EDGE_MASK)
+#define ESC_LATCH0_CTRL_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_CTRL_POS_EDGE_MASK) >> ESC_LATCH0_CTRL_POS_EDGE_SHIFT)
+
+/* Bitfield definition for register: LATCH1_CTRL */
+/*
+ * NEG_EDGE (RW)
+ *
+ * Latch1 negative edge:
+ * 0:Continuous Latch active
+ * 1:Single event (only first event active)
+ */
+#define ESC_LATCH1_CTRL_NEG_EDGE_MASK (0x2U)
+#define ESC_LATCH1_CTRL_NEG_EDGE_SHIFT (1U)
+#define ESC_LATCH1_CTRL_NEG_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH1_CTRL_NEG_EDGE_SHIFT) & ESC_LATCH1_CTRL_NEG_EDGE_MASK)
+#define ESC_LATCH1_CTRL_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_CTRL_NEG_EDGE_MASK) >> ESC_LATCH1_CTRL_NEG_EDGE_SHIFT)
+
+/*
+ * POS_EDGE (RW)
+ *
+ * Latch1 positive edge:
+ * 0:Continuous Latch active
+ * 1:Single event (only first event active)
+ */
+#define ESC_LATCH1_CTRL_POS_EDGE_MASK (0x1U)
+#define ESC_LATCH1_CTRL_POS_EDGE_SHIFT (0U)
+#define ESC_LATCH1_CTRL_POS_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH1_CTRL_POS_EDGE_SHIFT) & ESC_LATCH1_CTRL_POS_EDGE_MASK)
+#define ESC_LATCH1_CTRL_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_CTRL_POS_EDGE_MASK) >> ESC_LATCH1_CTRL_POS_EDGE_SHIFT)
+
+/* Bitfield definition for register: LATCH0_STAT */
+/*
+ * PIN_STAT (RO)
+ *
+ * Latch0 pin state
+ */
+#define ESC_LATCH0_STAT_PIN_STAT_MASK (0x4U)
+#define ESC_LATCH0_STAT_PIN_STAT_SHIFT (2U)
+#define ESC_LATCH0_STAT_PIN_STAT_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_PIN_STAT_MASK) >> ESC_LATCH0_STAT_PIN_STAT_SHIFT)
+
+/*
+ * NEG_EDGE (RO)
+ *
+ * Event Latch0 negative edge.
+ * 0:Negative edge not detected or
+ * continuous mode
+ * 1:Negative edge detected in single event
+ * mode only.
+ * Flag cleared by reading out Latch0 Time
+ * Negative Edge.
+ */
+#define ESC_LATCH0_STAT_NEG_EDGE_MASK (0x2U)
+#define ESC_LATCH0_STAT_NEG_EDGE_SHIFT (1U)
+#define ESC_LATCH0_STAT_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_NEG_EDGE_MASK) >> ESC_LATCH0_STAT_NEG_EDGE_SHIFT)
+
+/*
+ * POS_EDGE (RO)
+ *
+ * Event Latch0 positive edge.
+ * 0:Positive edge not detected or
+ * continuous mode
+ * 1:Positive edge detected in single event
+ * mode only.
+ * Flag cleared by reading out Latch0 Time
+ * Positive Edge.
+ */
+#define ESC_LATCH0_STAT_POS_EDGE_MASK (0x1U)
+#define ESC_LATCH0_STAT_POS_EDGE_SHIFT (0U)
+#define ESC_LATCH0_STAT_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_POS_EDGE_MASK) >> ESC_LATCH0_STAT_POS_EDGE_SHIFT)
+
+/* Bitfield definition for register: LATCH1_STAT */
+/*
+ * PIN_STAT (RO)
+ *
+ * Latch1 pin state
+ */
+#define ESC_LATCH1_STAT_PIN_STAT_MASK (0x4U)
+#define ESC_LATCH1_STAT_PIN_STAT_SHIFT (2U)
+#define ESC_LATCH1_STAT_PIN_STAT_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_PIN_STAT_MASK) >> ESC_LATCH1_STAT_PIN_STAT_SHIFT)
+
+/*
+ * NEG_EDGE (RO)
+ *
+ * Event Latch1 negative edge.
+ * 0:Negative edge not detected or
+ * continuous mode
+ * 1:Negative edge detected in single event
+ * mode only.
+ * Flag cleared by reading out Latch1 Time
+ * Negative Edge.
+ */
+#define ESC_LATCH1_STAT_NEG_EDGE_MASK (0x2U)
+#define ESC_LATCH1_STAT_NEG_EDGE_SHIFT (1U)
+#define ESC_LATCH1_STAT_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_NEG_EDGE_MASK) >> ESC_LATCH1_STAT_NEG_EDGE_SHIFT)
+
+/*
+ * POS_EDGE (RO)
+ *
+ * Event Latch1 positive edge.
+ * 0:Positive edge not detected or
+ * continuous mode
+ * 1:Positive edge detected in single event
+ * mode only.
+ * Flag cleared by reading out Latch1 Time
+ * Positive Edge.
+ */
+#define ESC_LATCH1_STAT_POS_EDGE_MASK (0x1U)
+#define ESC_LATCH1_STAT_POS_EDGE_SHIFT (0U)
+#define ESC_LATCH1_STAT_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_POS_EDGE_MASK) >> ESC_LATCH1_STAT_POS_EDGE_SHIFT)
+
+/* Bitfield definition for register: LATCH0_TIME_PE */
+/*
+ * TIME (RW)
+ *
+ * System time at the positive edge of the
+ * Latch0 signal.
+ */
+#define ESC_LATCH0_TIME_PE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_LATCH0_TIME_PE_TIME_SHIFT (0U)
+#define ESC_LATCH0_TIME_PE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH0_TIME_PE_TIME_SHIFT) & ESC_LATCH0_TIME_PE_TIME_MASK)
+#define ESC_LATCH0_TIME_PE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH0_TIME_PE_TIME_MASK) >> ESC_LATCH0_TIME_PE_TIME_SHIFT)
+
+/* Bitfield definition for register: LATCH0_TIME_NE */
+/*
+ * TIME (RW)
+ *
+ * System time at the negative edge of the
+ * Latch0 signal.
+ */
+#define ESC_LATCH0_TIME_NE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_LATCH0_TIME_NE_TIME_SHIFT (0U)
+#define ESC_LATCH0_TIME_NE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH0_TIME_NE_TIME_SHIFT) & ESC_LATCH0_TIME_NE_TIME_MASK)
+#define ESC_LATCH0_TIME_NE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH0_TIME_NE_TIME_MASK) >> ESC_LATCH0_TIME_NE_TIME_SHIFT)
+
+/* Bitfield definition for register: LATCH1_TIME_PE */
+/*
+ * TIME (RW)
+ *
+ * System time at the positive edge of the
+ * Latch1 signal.
+ */
+#define ESC_LATCH1_TIME_PE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_LATCH1_TIME_PE_TIME_SHIFT (0U)
+#define ESC_LATCH1_TIME_PE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH1_TIME_PE_TIME_SHIFT) & ESC_LATCH1_TIME_PE_TIME_MASK)
+#define ESC_LATCH1_TIME_PE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH1_TIME_PE_TIME_MASK) >> ESC_LATCH1_TIME_PE_TIME_SHIFT)
+
+/* Bitfield definition for register: LATCH1_TIME_NE */
+/*
+ * TIME (RW)
+ *
+ * System time at the negative edge of the
+ * Latch1 signal.
+ */
+#define ESC_LATCH1_TIME_NE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_LATCH1_TIME_NE_TIME_SHIFT (0U)
+#define ESC_LATCH1_TIME_NE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH1_TIME_NE_TIME_SHIFT) & ESC_LATCH1_TIME_NE_TIME_MASK)
+#define ESC_LATCH1_TIME_NE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH1_TIME_NE_TIME_MASK) >> ESC_LATCH1_TIME_NE_TIME_SHIFT)
+
+/* Bitfield definition for register: ECAT_BUF_CET */
+/*
+ * TIME (RO)
+ *
+ * Local time at the beginning of the frame
+ * which causes at least one SyncManager to
+ * assert an ECAT event
+ */
+#define ESC_ECAT_BUF_CET_TIME_MASK (0xFFFFFFFFUL)
+#define ESC_ECAT_BUF_CET_TIME_SHIFT (0U)
+#define ESC_ECAT_BUF_CET_TIME_GET(x) (((uint32_t)(x) & ESC_ECAT_BUF_CET_TIME_MASK) >> ESC_ECAT_BUF_CET_TIME_SHIFT)
+
+/* Bitfield definition for register: PDI_BUF_SET */
+/*
+ * TIME (RO)
+ *
+ * Local time when at least one SyncManager
+ * asserts a PDI buffer start event
+ */
+#define ESC_PDI_BUF_SET_TIME_MASK (0xFFFFFFFFUL)
+#define ESC_PDI_BUF_SET_TIME_SHIFT (0U)
+#define ESC_PDI_BUF_SET_TIME_GET(x) (((uint32_t)(x) & ESC_PDI_BUF_SET_TIME_MASK) >> ESC_PDI_BUF_SET_TIME_SHIFT)
+
+/* Bitfield definition for register: PDI_BUF_CET */
+/*
+ * TIME (RO)
+ *
+ * Local time when at least one SyncManager
+ * asserts a PDI buffer change event
+ */
+#define ESC_PDI_BUF_CET_TIME_MASK (0xFFFFFFFFUL)
+#define ESC_PDI_BUF_CET_TIME_SHIFT (0U)
+#define ESC_PDI_BUF_CET_TIME_GET(x) (((uint32_t)(x) & ESC_PDI_BUF_CET_TIME_MASK) >> ESC_PDI_BUF_CET_TIME_SHIFT)
+
+/* Bitfield definition for register: PID */
+/*
+ * PID (RO)
+ *
+ * Product ID
+ */
+#define ESC_PID_PID_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_PID_PID_SHIFT (0U)
+#define ESC_PID_PID_GET(x) (((uint64_t)(x) & ESC_PID_PID_MASK) >> ESC_PID_PID_SHIFT)
+
+/* Bitfield definition for register: VID */
+/*
+ * VID (RO)
+ *
+ * Vendor ID:
+ * 23-0: Company
+ * 31-24: Department
+ * NOTE:Test Vendor IDs have [31:28]=0xE
+ */
+#define ESC_VID_VID_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_VID_VID_SHIFT (0U)
+#define ESC_VID_VID_GET(x) (((uint64_t)(x) & ESC_VID_VID_MASK) >> ESC_VID_VID_SHIFT)
+
+/* Bitfield definition for register: DIO_OUT_DATA */
+/*
+ * OD (RO)
+ *
+ * Output Data
+ */
+#define ESC_DIO_OUT_DATA_OD_MASK (0xFFFFFFFFUL)
+#define ESC_DIO_OUT_DATA_OD_SHIFT (0U)
+#define ESC_DIO_OUT_DATA_OD_GET(x) (((uint32_t)(x) & ESC_DIO_OUT_DATA_OD_MASK) >> ESC_DIO_OUT_DATA_OD_SHIFT)
+
+/* Bitfield definition for register: GPO */
+/*
+ * GPOD (RW)
+ *
+ * General Purpose Output Data
+ */
+#define ESC_GPO_GPOD_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_GPO_GPOD_SHIFT (0U)
+#define ESC_GPO_GPOD_SET(x) (((uint64_t)(x) << ESC_GPO_GPOD_SHIFT) & ESC_GPO_GPOD_MASK)
+#define ESC_GPO_GPOD_GET(x) (((uint64_t)(x) & ESC_GPO_GPOD_MASK) >> ESC_GPO_GPOD_SHIFT)
+
+/* Bitfield definition for register: GPI */
+/*
+ * GPID (RO)
+ *
+ * General Purpose Input Data
+ */
+#define ESC_GPI_GPID_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ESC_GPI_GPID_SHIFT (0U)
+#define ESC_GPI_GPID_GET(x) (((uint64_t)(x) & ESC_GPI_GPID_MASK) >> ESC_GPI_GPID_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE0 */
+/*
+ * EXTF (RW)
+ *
+ * Number of extended feature bits
+ */
+#define ESC_USER_RAM_BYTE0_EXTF_MASK (0xFFU)
+#define ESC_USER_RAM_BYTE0_EXTF_SHIFT (0U)
+#define ESC_USER_RAM_BYTE0_EXTF_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE0_EXTF_SHIFT) & ESC_USER_RAM_BYTE0_EXTF_MASK)
+#define ESC_USER_RAM_BYTE0_EXTF_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE0_EXTF_MASK) >> ESC_USER_RAM_BYTE0_EXTF_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE1 */
+/*
+ * PRWO (RW)
+ *
+ * Physical Read/Write Offset (0x0108:0x0109)
+ */
+#define ESC_USER_RAM_BYTE1_PRWO_MASK (0x80U)
+#define ESC_USER_RAM_BYTE1_PRWO_SHIFT (7U)
+#define ESC_USER_RAM_BYTE1_PRWO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_PRWO_SHIFT) & ESC_USER_RAM_BYTE1_PRWO_MASK)
+#define ESC_USER_RAM_BYTE1_PRWO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_PRWO_MASK) >> ESC_USER_RAM_BYTE1_PRWO_SHIFT)
+
+/*
+ * AEMW (RW)
+ *
+ * AL Event Mask writable (0x0204:0x0207)
+ */
+#define ESC_USER_RAM_BYTE1_AEMW_MASK (0x40U)
+#define ESC_USER_RAM_BYTE1_AEMW_SHIFT (6U)
+#define ESC_USER_RAM_BYTE1_AEMW_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_AEMW_SHIFT) & ESC_USER_RAM_BYTE1_AEMW_MASK)
+#define ESC_USER_RAM_BYTE1_AEMW_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_AEMW_MASK) >> ESC_USER_RAM_BYTE1_AEMW_SHIFT)
+
+/*
+ * GPO (RW)
+ *
+ * General Purpose Outputs (0x0F10:0x0F17)
+ */
+#define ESC_USER_RAM_BYTE1_GPO_MASK (0x20U)
+#define ESC_USER_RAM_BYTE1_GPO_SHIFT (5U)
+#define ESC_USER_RAM_BYTE1_GPO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_GPO_SHIFT) & ESC_USER_RAM_BYTE1_GPO_MASK)
+#define ESC_USER_RAM_BYTE1_GPO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_GPO_MASK) >> ESC_USER_RAM_BYTE1_GPO_SHIFT)
+
+/*
+ * GPI (RW)
+ *
+ * General Purpose Inputs (0x0F18:0x0F1F)
+ */
+#define ESC_USER_RAM_BYTE1_GPI_MASK (0x10U)
+#define ESC_USER_RAM_BYTE1_GPI_SHIFT (4U)
+#define ESC_USER_RAM_BYTE1_GPI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_GPI_SHIFT) & ESC_USER_RAM_BYTE1_GPI_MASK)
+#define ESC_USER_RAM_BYTE1_GPI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_GPI_MASK) >> ESC_USER_RAM_BYTE1_GPI_SHIFT)
+
+/*
+ * CSA (RW)
+ *
+ * Configured Station Alias (0x0012:0x0013)
+ */
+#define ESC_USER_RAM_BYTE1_CSA_MASK (0x8U)
+#define ESC_USER_RAM_BYTE1_CSA_SHIFT (3U)
+#define ESC_USER_RAM_BYTE1_CSA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_CSA_SHIFT) & ESC_USER_RAM_BYTE1_CSA_MASK)
+#define ESC_USER_RAM_BYTE1_CSA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_CSA_MASK) >> ESC_USER_RAM_BYTE1_CSA_SHIFT)
+
+/*
+ * EIM (RW)
+ *
+ * ECAT Interrupt Mask (0x0200:0x0201)
+ */
+#define ESC_USER_RAM_BYTE1_EIM_MASK (0x4U)
+#define ESC_USER_RAM_BYTE1_EIM_SHIFT (2U)
+#define ESC_USER_RAM_BYTE1_EIM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_EIM_SHIFT) & ESC_USER_RAM_BYTE1_EIM_MASK)
+#define ESC_USER_RAM_BYTE1_EIM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_EIM_MASK) >> ESC_USER_RAM_BYTE1_EIM_SHIFT)
+
+/*
+ * ALSCR (RW)
+ *
+ * AL Status Code Register (0x0134:0x0135)
+ */
+#define ESC_USER_RAM_BYTE1_ALSCR_MASK (0x2U)
+#define ESC_USER_RAM_BYTE1_ALSCR_SHIFT (1U)
+#define ESC_USER_RAM_BYTE1_ALSCR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_ALSCR_SHIFT) & ESC_USER_RAM_BYTE1_ALSCR_MASK)
+#define ESC_USER_RAM_BYTE1_ALSCR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_ALSCR_MASK) >> ESC_USER_RAM_BYTE1_ALSCR_SHIFT)
+
+/*
+ * EDLCR (RW)
+ *
+ * Extended DL Control Register (0x0102:0x0103)
+ */
+#define ESC_USER_RAM_BYTE1_EDLCR_MASK (0x1U)
+#define ESC_USER_RAM_BYTE1_EDLCR_SHIFT (0U)
+#define ESC_USER_RAM_BYTE1_EDLCR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_EDLCR_SHIFT) & ESC_USER_RAM_BYTE1_EDLCR_MASK)
+#define ESC_USER_RAM_BYTE1_EDLCR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_EDLCR_MASK) >> ESC_USER_RAM_BYTE1_EDLCR_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE2 */
+/*
+ * ESCFG (RW)
+ *
+ * EEPROM Size configurable (0x0502[7]):
+ * 0:EEPROM Size fixed to sizes up to 16 Kbit
+ * 1:EEPROM Size configurable
+ */
+#define ESC_USER_RAM_BYTE2_ESCFG_MASK (0x80U)
+#define ESC_USER_RAM_BYTE2_ESCFG_SHIFT (7U)
+#define ESC_USER_RAM_BYTE2_ESCFG_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_ESCFG_SHIFT) & ESC_USER_RAM_BYTE2_ESCFG_MASK)
+#define ESC_USER_RAM_BYTE2_ESCFG_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_ESCFG_MASK) >> ESC_USER_RAM_BYTE2_ESCFG_SHIFT)
+
+/*
+ * EPUPEC (RW)
+ *
+ * ECAT Processing Unit/PDI Error Counter
+ * (0x030C:0x030D)
+ */
+#define ESC_USER_RAM_BYTE2_EPUPEC_MASK (0x40U)
+#define ESC_USER_RAM_BYTE2_EPUPEC_SHIFT (6U)
+#define ESC_USER_RAM_BYTE2_EPUPEC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_EPUPEC_SHIFT) & ESC_USER_RAM_BYTE2_EPUPEC_MASK)
+#define ESC_USER_RAM_BYTE2_EPUPEC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_EPUPEC_MASK) >> ESC_USER_RAM_BYTE2_EPUPEC_SHIFT)
+
+/*
+ * DCSMET (RW)
+ *
+ * DC SyncManager Event Times (0x09F0:0x09FF)
+ */
+#define ESC_USER_RAM_BYTE2_DCSMET_MASK (0x20U)
+#define ESC_USER_RAM_BYTE2_DCSMET_SHIFT (5U)
+#define ESC_USER_RAM_BYTE2_DCSMET_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_DCSMET_SHIFT) & ESC_USER_RAM_BYTE2_DCSMET_MASK)
+#define ESC_USER_RAM_BYTE2_DCSMET_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_DCSMET_MASK) >> ESC_USER_RAM_BYTE2_DCSMET_SHIFT)
+
+/*
+ * RESET (RW)
+ *
+ * Reset (0x0040:0x0041)
+ */
+#define ESC_USER_RAM_BYTE2_RESET_MASK (0x8U)
+#define ESC_USER_RAM_BYTE2_RESET_SHIFT (3U)
+#define ESC_USER_RAM_BYTE2_RESET_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_RESET_SHIFT) & ESC_USER_RAM_BYTE2_RESET_MASK)
+#define ESC_USER_RAM_BYTE2_RESET_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_RESET_MASK) >> ESC_USER_RAM_BYTE2_RESET_SHIFT)
+
+/*
+ * WP (RW)
+ *
+ * Write Protection (0x0020:0x0031)
+ */
+#define ESC_USER_RAM_BYTE2_WP_MASK (0x4U)
+#define ESC_USER_RAM_BYTE2_WP_SHIFT (2U)
+#define ESC_USER_RAM_BYTE2_WP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WP_SHIFT) & ESC_USER_RAM_BYTE2_WP_MASK)
+#define ESC_USER_RAM_BYTE2_WP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WP_MASK) >> ESC_USER_RAM_BYTE2_WP_SHIFT)
+
+/*
+ * WDGCNT (RW)
+ *
+ * Watchdog counters (0x0442:0x0443)
+ */
+#define ESC_USER_RAM_BYTE2_WDGCNT_MASK (0x2U)
+#define ESC_USER_RAM_BYTE2_WDGCNT_SHIFT (1U)
+#define ESC_USER_RAM_BYTE2_WDGCNT_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WDGCNT_SHIFT) & ESC_USER_RAM_BYTE2_WDGCNT_MASK)
+#define ESC_USER_RAM_BYTE2_WDGCNT_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WDGCNT_MASK) >> ESC_USER_RAM_BYTE2_WDGCNT_SHIFT)
+
+/*
+ * WDW (RW)
+ *
+ * Watchdog divider writable (0x0400:0x0401) and
+ * Watchdog PDI (0x0410:0x0411)
+ */
+#define ESC_USER_RAM_BYTE2_WDW_MASK (0x1U)
+#define ESC_USER_RAM_BYTE2_WDW_SHIFT (0U)
+#define ESC_USER_RAM_BYTE2_WDW_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WDW_SHIFT) & ESC_USER_RAM_BYTE2_WDW_MASK)
+#define ESC_USER_RAM_BYTE2_WDW_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WDW_MASK) >> ESC_USER_RAM_BYTE2_WDW_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE3 */
+/*
+ * RLED (RW)
+ *
+ * Run LED (DEV_STATE LED)
+ */
+#define ESC_USER_RAM_BYTE3_RLED_MASK (0x80U)
+#define ESC_USER_RAM_BYTE3_RLED_SHIFT (7U)
+#define ESC_USER_RAM_BYTE3_RLED_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_RLED_SHIFT) & ESC_USER_RAM_BYTE3_RLED_MASK)
+#define ESC_USER_RAM_BYTE3_RLED_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_RLED_MASK) >> ESC_USER_RAM_BYTE3_RLED_SHIFT)
+
+/*
+ * ELDE (RW)
+ *
+ * Enhanced Link Detection EBUS
+ */
+#define ESC_USER_RAM_BYTE3_ELDE_MASK (0x40U)
+#define ESC_USER_RAM_BYTE3_ELDE_SHIFT (6U)
+#define ESC_USER_RAM_BYTE3_ELDE_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_ELDE_SHIFT) & ESC_USER_RAM_BYTE3_ELDE_MASK)
+#define ESC_USER_RAM_BYTE3_ELDE_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_ELDE_MASK) >> ESC_USER_RAM_BYTE3_ELDE_SHIFT)
+
+/*
+ * ELDM (RW)
+ *
+ * Enhanced Link Detection MII
+ */
+#define ESC_USER_RAM_BYTE3_ELDM_MASK (0x20U)
+#define ESC_USER_RAM_BYTE3_ELDM_SHIFT (5U)
+#define ESC_USER_RAM_BYTE3_ELDM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_ELDM_SHIFT) & ESC_USER_RAM_BYTE3_ELDM_MASK)
+#define ESC_USER_RAM_BYTE3_ELDM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_ELDM_MASK) >> ESC_USER_RAM_BYTE3_ELDM_SHIFT)
+
+/*
+ * MMI (RW)
+ *
+ * MII Management Interface (0x0510:0x0515)
+ */
+#define ESC_USER_RAM_BYTE3_MMI_MASK (0x10U)
+#define ESC_USER_RAM_BYTE3_MMI_SHIFT (4U)
+#define ESC_USER_RAM_BYTE3_MMI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_MMI_SHIFT) & ESC_USER_RAM_BYTE3_MMI_MASK)
+#define ESC_USER_RAM_BYTE3_MMI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_MMI_MASK) >> ESC_USER_RAM_BYTE3_MMI_SHIFT)
+
+/*
+ * LLC (RW)
+ *
+ * Lost Link Counter (0x0310:0x0313)
+ */
+#define ESC_USER_RAM_BYTE3_LLC_MASK (0x8U)
+#define ESC_USER_RAM_BYTE3_LLC_SHIFT (3U)
+#define ESC_USER_RAM_BYTE3_LLC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_LLC_SHIFT) & ESC_USER_RAM_BYTE3_LLC_MASK)
+#define ESC_USER_RAM_BYTE3_LLC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_LLC_MASK) >> ESC_USER_RAM_BYTE3_LLC_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE4 */
+/*
+ * LDCM (RW)
+ *
+ * Link detection and configuration by MI
+ */
+#define ESC_USER_RAM_BYTE4_LDCM_MASK (0x80U)
+#define ESC_USER_RAM_BYTE4_LDCM_SHIFT (7U)
+#define ESC_USER_RAM_BYTE4_LDCM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_LDCM_SHIFT) & ESC_USER_RAM_BYTE4_LDCM_MASK)
+#define ESC_USER_RAM_BYTE4_LDCM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_LDCM_MASK) >> ESC_USER_RAM_BYTE4_LDCM_SHIFT)
+
+/*
+ * DTLC (RW)
+ *
+ * DC Time loop control assigned to PDI
+ */
+#define ESC_USER_RAM_BYTE4_DTLC_MASK (0x40U)
+#define ESC_USER_RAM_BYTE4_DTLC_SHIFT (6U)
+#define ESC_USER_RAM_BYTE4_DTLC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DTLC_SHIFT) & ESC_USER_RAM_BYTE4_DTLC_MASK)
+#define ESC_USER_RAM_BYTE4_DTLC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DTLC_MASK) >> ESC_USER_RAM_BYTE4_DTLC_SHIFT)
+
+/*
+ * DSOU (RW)
+ *
+ * DC Sync Out Unit
+ */
+#define ESC_USER_RAM_BYTE4_DSOU_MASK (0x20U)
+#define ESC_USER_RAM_BYTE4_DSOU_SHIFT (5U)
+#define ESC_USER_RAM_BYTE4_DSOU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DSOU_SHIFT) & ESC_USER_RAM_BYTE4_DSOU_MASK)
+#define ESC_USER_RAM_BYTE4_DSOU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DSOU_MASK) >> ESC_USER_RAM_BYTE4_DSOU_SHIFT)
+
+/*
+ * DLIU (RW)
+ *
+ * DC Latch In Unit
+ */
+#define ESC_USER_RAM_BYTE4_DLIU_MASK (0x8U)
+#define ESC_USER_RAM_BYTE4_DLIU_SHIFT (3U)
+#define ESC_USER_RAM_BYTE4_DLIU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DLIU_SHIFT) & ESC_USER_RAM_BYTE4_DLIU_MASK)
+#define ESC_USER_RAM_BYTE4_DLIU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DLIU_MASK) >> ESC_USER_RAM_BYTE4_DLIU_SHIFT)
+
+/*
+ * LALED (RW)
+ *
+ * Link/Activity LED
+ */
+#define ESC_USER_RAM_BYTE4_LALED_MASK (0x1U)
+#define ESC_USER_RAM_BYTE4_LALED_SHIFT (0U)
+#define ESC_USER_RAM_BYTE4_LALED_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_LALED_SHIFT) & ESC_USER_RAM_BYTE4_LALED_MASK)
+#define ESC_USER_RAM_BYTE4_LALED_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_LALED_MASK) >> ESC_USER_RAM_BYTE4_LALED_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE5 */
+/*
+ * DDIOR (RW)
+ *
+ * Disable Digital I/O register (0x0F00:0x0F03)
+ */
+#define ESC_USER_RAM_BYTE5_DDIOR_MASK (0x20U)
+#define ESC_USER_RAM_BYTE5_DDIOR_SHIFT (5U)
+#define ESC_USER_RAM_BYTE5_DDIOR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_DDIOR_SHIFT) & ESC_USER_RAM_BYTE5_DDIOR_MASK)
+#define ESC_USER_RAM_BYTE5_DDIOR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_DDIOR_MASK) >> ESC_USER_RAM_BYTE5_DDIOR_SHIFT)
+
+/*
+ * EEU (RW)
+ *
+ * EEPROM emulation by µController
+ */
+#define ESC_USER_RAM_BYTE5_EEU_MASK (0x4U)
+#define ESC_USER_RAM_BYTE5_EEU_SHIFT (2U)
+#define ESC_USER_RAM_BYTE5_EEU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_EEU_SHIFT) & ESC_USER_RAM_BYTE5_EEU_MASK)
+#define ESC_USER_RAM_BYTE5_EEU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_EEU_MASK) >> ESC_USER_RAM_BYTE5_EEU_SHIFT)
+
+/*
+ * ATS (RW)
+ *
+ * Automatic TX shift
+ */
+#define ESC_USER_RAM_BYTE5_ATS_MASK (0x2U)
+#define ESC_USER_RAM_BYTE5_ATS_SHIFT (1U)
+#define ESC_USER_RAM_BYTE5_ATS_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_ATS_SHIFT) & ESC_USER_RAM_BYTE5_ATS_MASK)
+#define ESC_USER_RAM_BYTE5_ATS_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_ATS_MASK) >> ESC_USER_RAM_BYTE5_ATS_SHIFT)
+
+/*
+ * MCPP (RW)
+ *
+ * MI control by PDI possible
+ */
+#define ESC_USER_RAM_BYTE5_MCPP_MASK (0x1U)
+#define ESC_USER_RAM_BYTE5_MCPP_SHIFT (0U)
+#define ESC_USER_RAM_BYTE5_MCPP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_MCPP_SHIFT) & ESC_USER_RAM_BYTE5_MCPP_MASK)
+#define ESC_USER_RAM_BYTE5_MCPP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_MCPP_MASK) >> ESC_USER_RAM_BYTE5_MCPP_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE6 */
+/*
+ * RELEDOR (RW)
+ *
+ * RUN/ERR LED Override (0x0138:0x0139)
+ */
+#define ESC_USER_RAM_BYTE6_RELEDOR_MASK (0x4U)
+#define ESC_USER_RAM_BYTE6_RELEDOR_SHIFT (2U)
+#define ESC_USER_RAM_BYTE6_RELEDOR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE6_RELEDOR_SHIFT) & ESC_USER_RAM_BYTE6_RELEDOR_MASK)
+#define ESC_USER_RAM_BYTE6_RELEDOR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE6_RELEDOR_MASK) >> ESC_USER_RAM_BYTE6_RELEDOR_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE7 */
+/*
+ * DCST (RW)
+ *
+ * DC System Time (0x0910:0x0936)
+ */
+#define ESC_USER_RAM_BYTE7_DCST_MASK (0x80U)
+#define ESC_USER_RAM_BYTE7_DCST_SHIFT (7U)
+#define ESC_USER_RAM_BYTE7_DCST_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCST_SHIFT) & ESC_USER_RAM_BYTE7_DCST_MASK)
+#define ESC_USER_RAM_BYTE7_DCST_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCST_MASK) >> ESC_USER_RAM_BYTE7_DCST_SHIFT)
+
+/*
+ * DCRT (RW)
+ *
+ * DC Receive Times (0x0900:0x090F)
+ */
+#define ESC_USER_RAM_BYTE7_DCRT_MASK (0x40U)
+#define ESC_USER_RAM_BYTE7_DCRT_SHIFT (6U)
+#define ESC_USER_RAM_BYTE7_DCRT_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCRT_SHIFT) & ESC_USER_RAM_BYTE7_DCRT_MASK)
+#define ESC_USER_RAM_BYTE7_DCRT_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCRT_MASK) >> ESC_USER_RAM_BYTE7_DCRT_SHIFT)
+
+/*
+ * DCS1D (RW)
+ *
+ * DC Sync1 disable
+ */
+#define ESC_USER_RAM_BYTE7_DCS1D_MASK (0x8U)
+#define ESC_USER_RAM_BYTE7_DCS1D_SHIFT (3U)
+#define ESC_USER_RAM_BYTE7_DCS1D_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCS1D_SHIFT) & ESC_USER_RAM_BYTE7_DCS1D_MASK)
+#define ESC_USER_RAM_BYTE7_DCS1D_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCS1D_MASK) >> ESC_USER_RAM_BYTE7_DCS1D_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE8 */
+/*
+ * PPDI (RW)
+ *
+ * PLB PDI
+ */
+#define ESC_USER_RAM_BYTE8_PPDI_MASK (0x20U)
+#define ESC_USER_RAM_BYTE8_PPDI_SHIFT (5U)
+#define ESC_USER_RAM_BYTE8_PPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_PPDI_SHIFT) & ESC_USER_RAM_BYTE8_PPDI_MASK)
+#define ESC_USER_RAM_BYTE8_PPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_PPDI_MASK) >> ESC_USER_RAM_BYTE8_PPDI_SHIFT)
+
+/*
+ * OPDI (RW)
+ *
+ * OPB PDI
+ */
+#define ESC_USER_RAM_BYTE8_OPDI_MASK (0x10U)
+#define ESC_USER_RAM_BYTE8_OPDI_SHIFT (4U)
+#define ESC_USER_RAM_BYTE8_OPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_OPDI_SHIFT) & ESC_USER_RAM_BYTE8_OPDI_MASK)
+#define ESC_USER_RAM_BYTE8_OPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_OPDI_MASK) >> ESC_USER_RAM_BYTE8_OPDI_SHIFT)
+
+/*
+ * APDI (RW)
+ *
+ * Avalon PDI
+ */
+#define ESC_USER_RAM_BYTE8_APDI_MASK (0x8U)
+#define ESC_USER_RAM_BYTE8_APDI_SHIFT (3U)
+#define ESC_USER_RAM_BYTE8_APDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_APDI_SHIFT) & ESC_USER_RAM_BYTE8_APDI_MASK)
+#define ESC_USER_RAM_BYTE8_APDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_APDI_MASK) >> ESC_USER_RAM_BYTE8_APDI_SHIFT)
+
+/*
+ * PDICEC (RW)
+ *
+ * PDI clears error counter
+ */
+#define ESC_USER_RAM_BYTE8_PDICEC_MASK (0x4U)
+#define ESC_USER_RAM_BYTE8_PDICEC_SHIFT (2U)
+#define ESC_USER_RAM_BYTE8_PDICEC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_PDICEC_SHIFT) & ESC_USER_RAM_BYTE8_PDICEC_MASK)
+#define ESC_USER_RAM_BYTE8_PDICEC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_PDICEC_MASK) >> ESC_USER_RAM_BYTE8_PDICEC_SHIFT)
+
+/*
+ * DC64 (RW)
+ *
+ * DC 64 bit
+ */
+#define ESC_USER_RAM_BYTE8_DC64_MASK (0x1U)
+#define ESC_USER_RAM_BYTE8_DC64_SHIFT (0U)
+#define ESC_USER_RAM_BYTE8_DC64_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_DC64_SHIFT) & ESC_USER_RAM_BYTE8_DC64_MASK)
+#define ESC_USER_RAM_BYTE8_DC64_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_DC64_MASK) >> ESC_USER_RAM_BYTE8_DC64_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE9 */
+/*
+ * DR (RW)
+ *
+ * Direct RESET
+ */
+#define ESC_USER_RAM_BYTE9_DR_MASK (0x80U)
+#define ESC_USER_RAM_BYTE9_DR_SHIFT (7U)
+#define ESC_USER_RAM_BYTE9_DR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE9_DR_SHIFT) & ESC_USER_RAM_BYTE9_DR_MASK)
+#define ESC_USER_RAM_BYTE9_DR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE9_DR_MASK) >> ESC_USER_RAM_BYTE9_DR_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE10 */
+/*
+ * PDIIR (RW)
+ *
+ * PDI Information register (0x014E:0x014F)
+ */
+#define ESC_USER_RAM_BYTE10_PDIIR_MASK (0x80U)
+#define ESC_USER_RAM_BYTE10_PDIIR_SHIFT (7U)
+#define ESC_USER_RAM_BYTE10_PDIIR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_PDIIR_SHIFT) & ESC_USER_RAM_BYTE10_PDIIR_MASK)
+#define ESC_USER_RAM_BYTE10_PDIIR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_PDIIR_MASK) >> ESC_USER_RAM_BYTE10_PDIIR_SHIFT)
+
+/*
+ * PDIFA (RW)
+ *
+ * PDI function acknowledge by PDI write
+ */
+#define ESC_USER_RAM_BYTE10_PDIFA_MASK (0x40U)
+#define ESC_USER_RAM_BYTE10_PDIFA_SHIFT (6U)
+#define ESC_USER_RAM_BYTE10_PDIFA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_PDIFA_SHIFT) & ESC_USER_RAM_BYTE10_PDIFA_MASK)
+#define ESC_USER_RAM_BYTE10_PDIFA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_PDIFA_MASK) >> ESC_USER_RAM_BYTE10_PDIFA_SHIFT)
+
+/*
+ * APDI (RW)
+ *
+ * AXI PDI
+ */
+#define ESC_USER_RAM_BYTE10_APDI_MASK (0x8U)
+#define ESC_USER_RAM_BYTE10_APDI_SHIFT (3U)
+#define ESC_USER_RAM_BYTE10_APDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_APDI_SHIFT) & ESC_USER_RAM_BYTE10_APDI_MASK)
+#define ESC_USER_RAM_BYTE10_APDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_APDI_MASK) >> ESC_USER_RAM_BYTE10_APDI_SHIFT)
+
+/*
+ * DCL1D (RW)
+ *
+ * DC Latch1 disable
+ */
+#define ESC_USER_RAM_BYTE10_DCL1D_MASK (0x4U)
+#define ESC_USER_RAM_BYTE10_DCL1D_SHIFT (2U)
+#define ESC_USER_RAM_BYTE10_DCL1D_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_DCL1D_SHIFT) & ESC_USER_RAM_BYTE10_DCL1D_MASK)
+#define ESC_USER_RAM_BYTE10_DCL1D_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_DCL1D_MASK) >> ESC_USER_RAM_BYTE10_DCL1D_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE11 */
+/*
+ * LEDTST (RW)
+ *
+ * LED test
+ */
+#define ESC_USER_RAM_BYTE11_LEDTST_MASK (0x8U)
+#define ESC_USER_RAM_BYTE11_LEDTST_SHIFT (3U)
+#define ESC_USER_RAM_BYTE11_LEDTST_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE11_LEDTST_SHIFT) & ESC_USER_RAM_BYTE11_LEDTST_MASK)
+#define ESC_USER_RAM_BYTE11_LEDTST_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE11_LEDTST_MASK) >> ESC_USER_RAM_BYTE11_LEDTST_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE14 */
+/*
+ * DIOBS (RW)
+ *
+ * Digital I/O PDI byte size
+ */
+#define ESC_USER_RAM_BYTE14_DIOBS_MASK (0xC0U)
+#define ESC_USER_RAM_BYTE14_DIOBS_SHIFT (6U)
+#define ESC_USER_RAM_BYTE14_DIOBS_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE14_DIOBS_SHIFT) & ESC_USER_RAM_BYTE14_DIOBS_MASK)
+#define ESC_USER_RAM_BYTE14_DIOBS_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE14_DIOBS_MASK) >> ESC_USER_RAM_BYTE14_DIOBS_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE15 */
+/*
+ * AUCPDI (RW)
+ *
+ * Asynchronous µC PDI
+ */
+#define ESC_USER_RAM_BYTE15_AUCPDI_MASK (0x10U)
+#define ESC_USER_RAM_BYTE15_AUCPDI_SHIFT (4U)
+#define ESC_USER_RAM_BYTE15_AUCPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_AUCPDI_SHIFT) & ESC_USER_RAM_BYTE15_AUCPDI_MASK)
+#define ESC_USER_RAM_BYTE15_AUCPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_AUCPDI_MASK) >> ESC_USER_RAM_BYTE15_AUCPDI_SHIFT)
+
+/*
+ * SSPDI (RW)
+ *
+ * SPI Slave PDI
+ */
+#define ESC_USER_RAM_BYTE15_SSPDI_MASK (0x8U)
+#define ESC_USER_RAM_BYTE15_SSPDI_SHIFT (3U)
+#define ESC_USER_RAM_BYTE15_SSPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_SSPDI_SHIFT) & ESC_USER_RAM_BYTE15_SSPDI_MASK)
+#define ESC_USER_RAM_BYTE15_SSPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_SSPDI_MASK) >> ESC_USER_RAM_BYTE15_SSPDI_SHIFT)
+
+/*
+ * DIOPDI (RW)
+ *
+ * Digital I/O PDI
+ */
+#define ESC_USER_RAM_BYTE15_DIOPDI_MASK (0x4U)
+#define ESC_USER_RAM_BYTE15_DIOPDI_SHIFT (2U)
+#define ESC_USER_RAM_BYTE15_DIOPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_DIOPDI_SHIFT) & ESC_USER_RAM_BYTE15_DIOPDI_MASK)
+#define ESC_USER_RAM_BYTE15_DIOPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_DIOPDI_MASK) >> ESC_USER_RAM_BYTE15_DIOPDI_SHIFT)
+
+/* Bitfield definition for register: USER_RAM_BYTE19 */
+/*
+ * SCP (RW)
+ *
+ * Security CPLD protection
+ */
+#define ESC_USER_RAM_BYTE19_SCP_MASK (0x40U)
+#define ESC_USER_RAM_BYTE19_SCP_SHIFT (6U)
+#define ESC_USER_RAM_BYTE19_SCP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_SCP_SHIFT) & ESC_USER_RAM_BYTE19_SCP_MASK)
+#define ESC_USER_RAM_BYTE19_SCP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_SCP_MASK) >> ESC_USER_RAM_BYTE19_SCP_SHIFT)
+
+/*
+ * RMII (RW)
+ *
+ * RMII
+ */
+#define ESC_USER_RAM_BYTE19_RMII_MASK (0x20U)
+#define ESC_USER_RAM_BYTE19_RMII_SHIFT (5U)
+#define ESC_USER_RAM_BYTE19_RMII_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_RMII_SHIFT) & ESC_USER_RAM_BYTE19_RMII_MASK)
+#define ESC_USER_RAM_BYTE19_RMII_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_RMII_MASK) >> ESC_USER_RAM_BYTE19_RMII_SHIFT)
+
+/*
+ * URGP (RW)
+ *
+ * Use RGMII GTX_CLK phase shifted clock input
+ */
+#define ESC_USER_RAM_BYTE19_URGP_MASK (0x10U)
+#define ESC_USER_RAM_BYTE19_URGP_SHIFT (4U)
+#define ESC_USER_RAM_BYTE19_URGP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_URGP_SHIFT) & ESC_USER_RAM_BYTE19_URGP_MASK)
+#define ESC_USER_RAM_BYTE19_URGP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_URGP_MASK) >> ESC_USER_RAM_BYTE19_URGP_SHIFT)
+
+/*
+ * CIA (RW)
+ *
+ * CLK_PDI_EXT is asynchronous
+ */
+#define ESC_USER_RAM_BYTE19_CIA_MASK (0x4U)
+#define ESC_USER_RAM_BYTE19_CIA_SHIFT (2U)
+#define ESC_USER_RAM_BYTE19_CIA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_CIA_SHIFT) & ESC_USER_RAM_BYTE19_CIA_MASK)
+#define ESC_USER_RAM_BYTE19_CIA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_CIA_MASK) >> ESC_USER_RAM_BYTE19_CIA_SHIFT)
+
+/*
+ * IPARO (RW)
+ *
+ * Individual PHY address read out (0x0510[7:3])
+ */
+#define ESC_USER_RAM_BYTE19_IPARO_MASK (0x2U)
+#define ESC_USER_RAM_BYTE19_IPARO_SHIFT (1U)
+#define ESC_USER_RAM_BYTE19_IPARO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_IPARO_SHIFT) & ESC_USER_RAM_BYTE19_IPARO_MASK)
+#define ESC_USER_RAM_BYTE19_IPARO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_IPARO_MASK) >> ESC_USER_RAM_BYTE19_IPARO_SHIFT)
+
+/*
+ * RGMII (RW)
+ *
+ * RGMII
+ */
+#define ESC_USER_RAM_BYTE19_RGMII_MASK (0x1U)
+#define ESC_USER_RAM_BYTE19_RGMII_SHIFT (0U)
+#define ESC_USER_RAM_BYTE19_RGMII_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_RGMII_SHIFT) & ESC_USER_RAM_BYTE19_RGMII_MASK)
+#define ESC_USER_RAM_BYTE19_RGMII_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_RGMII_MASK) >> ESC_USER_RAM_BYTE19_RGMII_SHIFT)
+
+/* Bitfield definition for register: PDRAM */
+/*
+ * DATA (RW)
+ *
+ * Input Data
+ */
+#define ESC_PDRAM_DATA_MASK (0xFFFFFFFFUL)
+#define ESC_PDRAM_DATA_SHIFT (0U)
+#define ESC_PDRAM_DATA_SET(x) (((uint32_t)(x) << ESC_PDRAM_DATA_SHIFT) & ESC_PDRAM_DATA_MASK)
+#define ESC_PDRAM_DATA_GET(x) (((uint32_t)(x) & ESC_PDRAM_DATA_MASK) >> ESC_PDRAM_DATA_SHIFT)
+
+/* Bitfield definition for register: PDRAM_ALS */
+/*
+ * DATA (RW)
+ *
+ */
+#define ESC_PDRAM_ALS_DATA_MASK (0xFFFFFFFFUL)
+#define ESC_PDRAM_ALS_DATA_SHIFT (0U)
+#define ESC_PDRAM_ALS_DATA_SET(x) (((uint32_t)(x) << ESC_PDRAM_ALS_DATA_SHIFT) & ESC_PDRAM_ALS_DATA_MASK)
+#define ESC_PDRAM_ALS_DATA_GET(x) (((uint32_t)(x) & ESC_PDRAM_ALS_DATA_MASK) >> ESC_PDRAM_ALS_DATA_SHIFT)
+
+/* Bitfield definition for register: GPR_CFG0 */
+/*
+ * CLK100_EN (RW)
+ *
+ */
+#define ESC_GPR_CFG0_CLK100_EN_MASK (0x2000U)
+#define ESC_GPR_CFG0_CLK100_EN_SHIFT (13U)
+#define ESC_GPR_CFG0_CLK100_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_CLK100_EN_SHIFT) & ESC_GPR_CFG0_CLK100_EN_MASK)
+#define ESC_GPR_CFG0_CLK100_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_CLK100_EN_MASK) >> ESC_GPR_CFG0_CLK100_EN_SHIFT)
+
+/*
+ * EEPROM_EMU (RW)
+ *
+ * 1 is EEPROM emulation mode (default)
+ */
+#define ESC_GPR_CFG0_EEPROM_EMU_MASK (0x1000U)
+#define ESC_GPR_CFG0_EEPROM_EMU_SHIFT (12U)
+#define ESC_GPR_CFG0_EEPROM_EMU_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_EEPROM_EMU_SHIFT) & ESC_GPR_CFG0_EEPROM_EMU_MASK)
+#define ESC_GPR_CFG0_EEPROM_EMU_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_EEPROM_EMU_MASK) >> ESC_GPR_CFG0_EEPROM_EMU_SHIFT)
+
+/*
+ * I2C_SCLK_EN (RW)
+ *
+ */
+#define ESC_GPR_CFG0_I2C_SCLK_EN_MASK (0x8U)
+#define ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT (3U)
+#define ESC_GPR_CFG0_I2C_SCLK_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT) & ESC_GPR_CFG0_I2C_SCLK_EN_MASK)
+#define ESC_GPR_CFG0_I2C_SCLK_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_I2C_SCLK_EN_MASK) >> ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT)
+
+/*
+ * PROM_SIZE (RW)
+ *
+ * Sets EEPROM size:
+ * 0:up to 16 kbit EEPROM
+ * 1:32 kbit-4Mbit EEPROM
+ */
+#define ESC_GPR_CFG0_PROM_SIZE_MASK (0x1U)
+#define ESC_GPR_CFG0_PROM_SIZE_SHIFT (0U)
+#define ESC_GPR_CFG0_PROM_SIZE_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_PROM_SIZE_SHIFT) & ESC_GPR_CFG0_PROM_SIZE_MASK)
+#define ESC_GPR_CFG0_PROM_SIZE_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_PROM_SIZE_MASK) >> ESC_GPR_CFG0_PROM_SIZE_SHIFT)
+
+/* Bitfield definition for register: GPR_CFG1 */
+/*
+ * SYNC1_IRQ_EN (RW)
+ *
+ */
+#define ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK (0x80000000UL)
+#define ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT (31U)
+#define ESC_GPR_CFG1_SYNC1_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT) & ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK)
+#define ESC_GPR_CFG1_SYNC1_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK) >> ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT)
+
+/*
+ * SYNC0_IRQ_EN (RW)
+ *
+ */
+#define ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK (0x40000000UL)
+#define ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT (30U)
+#define ESC_GPR_CFG1_SYNC0_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT) & ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK)
+#define ESC_GPR_CFG1_SYNC0_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK) >> ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT)
+
+/*
+ * RSTO_IRQ_EN (RW)
+ *
+ */
+#define ESC_GPR_CFG1_RSTO_IRQ_EN_MASK (0x20000000UL)
+#define ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT (29U)
+#define ESC_GPR_CFG1_RSTO_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT) & ESC_GPR_CFG1_RSTO_IRQ_EN_MASK)
+#define ESC_GPR_CFG1_RSTO_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_IRQ_EN_MASK) >> ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT)
+
+/*
+ * SYNC1_DMA_EN (RW)
+ *
+ */
+#define ESC_GPR_CFG1_SYNC1_DMA_EN_MASK (0x2000U)
+#define ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT (13U)
+#define ESC_GPR_CFG1_SYNC1_DMA_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT) & ESC_GPR_CFG1_SYNC1_DMA_EN_MASK)
+#define ESC_GPR_CFG1_SYNC1_DMA_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC1_DMA_EN_MASK) >> ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT)
+
+/*
+ * SYNC0_DMA_EN (RW)
+ *
+ */
+#define ESC_GPR_CFG1_SYNC0_DMA_EN_MASK (0x1000U)
+#define ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT (12U)
+#define ESC_GPR_CFG1_SYNC0_DMA_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT) & ESC_GPR_CFG1_SYNC0_DMA_EN_MASK)
+#define ESC_GPR_CFG1_SYNC0_DMA_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC0_DMA_EN_MASK) >> ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT)
+
+/*
+ * LATCH1_FROM_IO (RW)
+ *
+ * 0:from NTM
+ */
+#define ESC_GPR_CFG1_LATCH1_FROM_IO_MASK (0x200U)
+#define ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT (9U)
+#define ESC_GPR_CFG1_LATCH1_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT) & ESC_GPR_CFG1_LATCH1_FROM_IO_MASK)
+#define ESC_GPR_CFG1_LATCH1_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_LATCH1_FROM_IO_MASK) >> ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT)
+
+/*
+ * LATCH0_FROM_IO (RW)
+ *
+ * 0:from TRIGGER_MUX
+ */
+#define ESC_GPR_CFG1_LATCH0_FROM_IO_MASK (0x100U)
+#define ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT (8U)
+#define ESC_GPR_CFG1_LATCH0_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT) & ESC_GPR_CFG1_LATCH0_FROM_IO_MASK)
+#define ESC_GPR_CFG1_LATCH0_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_LATCH0_FROM_IO_MASK) >> ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT)
+
+/*
+ * RSTO_OVRD (RW)
+ *
+ */
+#define ESC_GPR_CFG1_RSTO_OVRD_MASK (0x80U)
+#define ESC_GPR_CFG1_RSTO_OVRD_SHIFT (7U)
+#define ESC_GPR_CFG1_RSTO_OVRD_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_OVRD_SHIFT) & ESC_GPR_CFG1_RSTO_OVRD_MASK)
+#define ESC_GPR_CFG1_RSTO_OVRD_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_OVRD_MASK) >> ESC_GPR_CFG1_RSTO_OVRD_SHIFT)
+
+/*
+ * RSTO_OVRD_ENJ (RW)
+ *
+ */
+#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK (0x40U)
+#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT (6U)
+#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT) & ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK)
+#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK) >> ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT)
+
+/* Bitfield definition for register: GPR_CFG2 */
+/*
+ * NMII_LINK2_FROM_IO (RW)
+ *
+ */
+#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK (0x20000000UL)
+#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT (29U)
+#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK)
+#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT)
+
+/*
+ * NMII_LINK2_GPR (RW)
+ *
+ */
+#define ESC_GPR_CFG2_NMII_LINK2_GPR_MASK (0x10000000UL)
+#define ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT (28U)
+#define ESC_GPR_CFG2_NMII_LINK2_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK2_GPR_MASK)
+#define ESC_GPR_CFG2_NMII_LINK2_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK2_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT)
+
+/*
+ * NMII_LINK1_FROM_IO (RW)
+ *
+ */
+#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK (0x2000000UL)
+#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT (25U)
+#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK)
+#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT)
+
+/*
+ * NMII_LINK1_GPR (RW)
+ *
+ */
+#define ESC_GPR_CFG2_NMII_LINK1_GPR_MASK (0x1000000UL)
+#define ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT (24U)
+#define ESC_GPR_CFG2_NMII_LINK1_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK1_GPR_MASK)
+#define ESC_GPR_CFG2_NMII_LINK1_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK1_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT)
+
+/*
+ * NMII_LINK0_FROM_IO (RW)
+ *
+ */
+#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK (0x200000UL)
+#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT (21U)
+#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK)
+#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT)
+
+/*
+ * NMII_LINK0_GPR (RW)
+ *
+ */
+#define ESC_GPR_CFG2_NMII_LINK0_GPR_MASK (0x100000UL)
+#define ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT (20U)
+#define ESC_GPR_CFG2_NMII_LINK0_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK0_GPR_MASK)
+#define ESC_GPR_CFG2_NMII_LINK0_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK0_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT)
+
+/* Bitfield definition for register: PHY_CFG0 */
+/*
+ * MAC_SPEED (RW)
+ *
+ * 1:100M
+ */
+#define ESC_PHY_CFG0_MAC_SPEED_MASK (0x40000000UL)
+#define ESC_PHY_CFG0_MAC_SPEED_SHIFT (30U)
+#define ESC_PHY_CFG0_MAC_SPEED_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_MAC_SPEED_SHIFT) & ESC_PHY_CFG0_MAC_SPEED_MASK)
+#define ESC_PHY_CFG0_MAC_SPEED_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_MAC_SPEED_MASK) >> ESC_PHY_CFG0_MAC_SPEED_SHIFT)
+
+/*
+ * PHY_OFFSET_VAL (RW)
+ *
+ */
+#define ESC_PHY_CFG0_PHY_OFFSET_VAL_MASK (0x1F000000UL)
+#define ESC_PHY_CFG0_PHY_OFFSET_VAL_SHIFT (24U)
+#define ESC_PHY_CFG0_PHY_OFFSET_VAL_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PHY_OFFSET_VAL_SHIFT) & ESC_PHY_CFG0_PHY_OFFSET_VAL_MASK)
+#define ESC_PHY_CFG0_PHY_OFFSET_VAL_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PHY_OFFSET_VAL_MASK) >> ESC_PHY_CFG0_PHY_OFFSET_VAL_SHIFT)
+
+/*
+ * PORT2_RMII_EN (RW)
+ *
+ */
+#define ESC_PHY_CFG0_PORT2_RMII_EN_MASK (0x800000UL)
+#define ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT (23U)
+#define ESC_PHY_CFG0_PORT2_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT2_RMII_EN_MASK)
+#define ESC_PHY_CFG0_PORT2_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT2_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT)
+
+/*
+ * PORT1_RMII_EN (RW)
+ *
+ */
+#define ESC_PHY_CFG0_PORT1_RMII_EN_MASK (0x8000U)
+#define ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT (15U)
+#define ESC_PHY_CFG0_PORT1_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT1_RMII_EN_MASK)
+#define ESC_PHY_CFG0_PORT1_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT1_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT)
+
+/*
+ * PORT0_RMII_EN (RW)
+ *
+ */
+#define ESC_PHY_CFG0_PORT0_RMII_EN_MASK (0x80U)
+#define ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT (7U)
+#define ESC_PHY_CFG0_PORT0_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT0_RMII_EN_MASK)
+#define ESC_PHY_CFG0_PORT0_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT0_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT)
+
+/* Bitfield definition for register: PHY_CFG1 */
+/*
+ * RMII_REFCLK_SEL (RW)
+ *
+ * 0:use RXCK as 50M refclk. 1:use TXCK as 50M refclk
+ */
+#define ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK (0x700U)
+#define ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT (8U)
+#define ESC_PHY_CFG1_RMII_REFCLK_SEL_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT) & ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK)
+#define ESC_PHY_CFG1_RMII_REFCLK_SEL_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK) >> ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT)
+
+/*
+ * REFCK_25M_INV (RW)
+ *
+ */
+#define ESC_PHY_CFG1_REFCK_25M_INV_MASK (0x80U)
+#define ESC_PHY_CFG1_REFCK_25M_INV_SHIFT (7U)
+#define ESC_PHY_CFG1_REFCK_25M_INV_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_REFCK_25M_INV_SHIFT) & ESC_PHY_CFG1_REFCK_25M_INV_MASK)
+#define ESC_PHY_CFG1_REFCK_25M_INV_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_REFCK_25M_INV_MASK) >> ESC_PHY_CFG1_REFCK_25M_INV_SHIFT)
+
+/*
+ * RMII_P2_RXCK_REFCLK_OE (RW)
+ *
+ */
+#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK (0x40U)
+#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT (6U)
+#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT)
+
+/*
+ * RMII_P1_RXCK_REFCLK_OE (RW)
+ *
+ */
+#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK (0x20U)
+#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT (5U)
+#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT)
+
+/*
+ * RMII_P0_RXCK_REFCLK_OE (RW)
+ *
+ */
+#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK (0x10U)
+#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT (4U)
+#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT)
+
+/*
+ * REFCK_25M_OE (RW)
+ *
+ */
+#define ESC_PHY_CFG1_REFCK_25M_OE_MASK (0x8U)
+#define ESC_PHY_CFG1_REFCK_25M_OE_SHIFT (3U)
+#define ESC_PHY_CFG1_REFCK_25M_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_REFCK_25M_OE_SHIFT) & ESC_PHY_CFG1_REFCK_25M_OE_MASK)
+#define ESC_PHY_CFG1_REFCK_25M_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_REFCK_25M_OE_MASK) >> ESC_PHY_CFG1_REFCK_25M_OE_SHIFT)
+
+/*
+ * RMII_P2_TXCK_REFCLK_OE (RW)
+ *
+ */
+#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK (0x4U)
+#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT (2U)
+#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT)
+
+/*
+ * RMII_P1_TXCK_REFCLK_OE (RW)
+ *
+ */
+#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK (0x2U)
+#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT (1U)
+#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT)
+
+/*
+ * RMII_P0_TXCK_REFCLK_OE (RW)
+ *
+ */
+#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK (0x1U)
+#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT (0U)
+#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT)
+
+/* Bitfield definition for register: GPIO_CTRL */
+/*
+ * SW_LATCH_GPI (WO)
+ *
+ * if gpi_trig_sel is set to 4'b1001, setting this bit will latch GPI to gpi_reg0/1
+ */
+#define ESC_GPIO_CTRL_SW_LATCH_GPI_MASK (0x80000000UL)
+#define ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT (31U)
+#define ESC_GPIO_CTRL_SW_LATCH_GPI_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT) & ESC_GPIO_CTRL_SW_LATCH_GPI_MASK)
+#define ESC_GPIO_CTRL_SW_LATCH_GPI_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_SW_LATCH_GPI_MASK) >> ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT)
+
+/*
+ * SW_LATCH_GPO (WO)
+ *
+ * if gpo_trig_sel is set to 4'b1001, setting this bit will latch GPO to gpo_reg0/1
+ */
+#define ESC_GPIO_CTRL_SW_LATCH_GPO_MASK (0x40000000UL)
+#define ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT (30U)
+#define ESC_GPIO_CTRL_SW_LATCH_GPO_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT) & ESC_GPIO_CTRL_SW_LATCH_GPO_MASK)
+#define ESC_GPIO_CTRL_SW_LATCH_GPO_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_SW_LATCH_GPO_MASK) >> ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT)
+
+/*
+ * GPI_OVERRIDE_EN (RW)
+ *
+ * set this bit will use GPI from the software register gpi_override0/1
+ * clr to use GPI from pad directly
+ */
+#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK (0x2000U)
+#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT (13U)
+#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT) & ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK)
+#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK) >> ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT)
+
+/*
+ * GPI_TRIG_EN (RW)
+ *
+ * use gpi_trig_sel can select the trigger event to latch GPI signal(from reg or pad)
+ * set to use triggered signal;
+ * clr to use signals direclty(from reg or pad)
+ * assign pdi_gpi = gpi_trig_en ? gpi_reg :
+ *                (gpi_override_en ? gpi_override :pad_di_ecat_gpi);
+ */
+#define ESC_GPIO_CTRL_GPI_TRIG_EN_MASK (0x1000U)
+#define ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT (12U)
+#define ESC_GPIO_CTRL_GPI_TRIG_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT) & ESC_GPIO_CTRL_GPI_TRIG_EN_MASK)
+#define ESC_GPIO_CTRL_GPI_TRIG_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_TRIG_EN_MASK) >> ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT)
+
+/*
+ * GPI_TRIG_SEL (RW)
+ *
+ * select the trigger signal to latch GPI.
+ * 0000: SOF;  0001: EOF;  0010: pos of  SYNC0;  0011: pos of SYNC1;
+ * 0100: pos of LATCH0;   0101: pos of LATCH1;   0110: neg of LATCH0;   0111: neg of LATCH1
+ * 1000: wdog trigger;   1001: sw set gpio_ctrl[31];
+ * others no trigger
+ */
+#define ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK (0xF00U)
+#define ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT (8U)
+#define ESC_GPIO_CTRL_GPI_TRIG_SEL_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT) & ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK)
+#define ESC_GPIO_CTRL_GPI_TRIG_SEL_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK) >> ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT)
+
+/*
+ * GPO_TRIG_EN (RW)
+ *
+ * use gpo_trig_sel can select the trigger event to latch GPO signal(from core)
+ * set to use triggered signal;
+ * clr to use GPO signals direclty(from reg or pad)
+ */
+#define ESC_GPIO_CTRL_GPO_TRIG_EN_MASK (0x10U)
+#define ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT (4U)
+#define ESC_GPIO_CTRL_GPO_TRIG_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT) & ESC_GPIO_CTRL_GPO_TRIG_EN_MASK)
+#define ESC_GPIO_CTRL_GPO_TRIG_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPO_TRIG_EN_MASK) >> ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT)
+
+/*
+ * GPO_TRIG_SEL (RW)
+ *
+ * select the trigger signal to latch GPO.
+ * 0000: SOF;  0001: EOF;  0010: pos of  SYNC0;  0011: pos of SYNC1;
+ * 0100: pos of LATCH0;   0101: pos of LATCH1;   0110: neg of LATCH0;   0111: neg of LATCH1
+ * 1000: wdog trigger;   1001: sw set gpio_ctrl[30];
+ * others no trigger
+ */
+#define ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK (0xFU)
+#define ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT (0U)
+#define ESC_GPIO_CTRL_GPO_TRIG_SEL_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT) & ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK)
+#define ESC_GPIO_CTRL_GPO_TRIG_SEL_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK) >> ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT)
+
+/* Bitfield definition for register: GPI_OVERRIDE0 */
+/*
+ * GPR_OVERRIDE_LOW (RW)
+ *
+ */
+#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK (0xFFFFFFFFUL)
+#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT (0U)
+#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SET(x) (((uint32_t)(x) << ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT) & ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK)
+#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_GET(x) (((uint32_t)(x) & ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK) >> ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT)
+
+/* Bitfield definition for register: GPI_OVERRIDE1 */
+/*
+ * GPR_OVERRIDE_HIGH (RW)
+ *
+ */
+#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK (0xFFFFFFFFUL)
+#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT (0U)
+#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SET(x) (((uint32_t)(x) << ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT) & ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK)
+#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_GET(x) (((uint32_t)(x) & ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK) >> ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT)
+
+/* Bitfield definition for register: GPO_REG0 */
+/*
+ * VALUE (RO)
+ *
+ */
+#define ESC_GPO_REG0_VALUE_MASK (0xFFFFFFFFUL)
+#define ESC_GPO_REG0_VALUE_SHIFT (0U)
+#define ESC_GPO_REG0_VALUE_GET(x) (((uint32_t)(x) & ESC_GPO_REG0_VALUE_MASK) >> ESC_GPO_REG0_VALUE_SHIFT)
+
+/* Bitfield definition for register: GPO_REG1 */
+/*
+ * VALUE (RO)
+ *
+ */
+#define ESC_GPO_REG1_VALUE_MASK (0xFFFFFFFFUL)
+#define ESC_GPO_REG1_VALUE_SHIFT (0U)
+#define ESC_GPO_REG1_VALUE_GET(x) (((uint32_t)(x) & ESC_GPO_REG1_VALUE_MASK) >> ESC_GPO_REG1_VALUE_SHIFT)
+
+/* Bitfield definition for register: GPI_REG0 */
+/*
+ * VALUE (RO)
+ *
+ */
+#define ESC_GPI_REG0_VALUE_MASK (0xFFFFFFFFUL)
+#define ESC_GPI_REG0_VALUE_SHIFT (0U)
+#define ESC_GPI_REG0_VALUE_GET(x) (((uint32_t)(x) & ESC_GPI_REG0_VALUE_MASK) >> ESC_GPI_REG0_VALUE_SHIFT)
+
+/* Bitfield definition for register: GPI_REG1 */
+/*
+ * VALUE (RO)
+ *
+ */
+#define ESC_GPI_REG1_VALUE_MASK (0xFFFFFFFFUL)
+#define ESC_GPI_REG1_VALUE_SHIFT (0U)
+#define ESC_GPI_REG1_VALUE_GET(x) (((uint32_t)(x) & ESC_GPI_REG1_VALUE_MASK) >> ESC_GPI_REG1_VALUE_SHIFT)
+
+/* Bitfield definition for register: GPR_STATUS */
+/*
+ * NLINK2_PADSEL (RO)
+ *
+ */
+#define ESC_GPR_STATUS_NLINK2_PADSEL_MASK (0xF0000000UL)
+#define ESC_GPR_STATUS_NLINK2_PADSEL_SHIFT (28U)
+#define ESC_GPR_STATUS_NLINK2_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK2_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK2_PADSEL_SHIFT)
+
+/*
+ * NLINK1_PADSEL (RO)
+ *
+ */
+#define ESC_GPR_STATUS_NLINK1_PADSEL_MASK (0xF000000UL)
+#define ESC_GPR_STATUS_NLINK1_PADSEL_SHIFT (24U)
+#define ESC_GPR_STATUS_NLINK1_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK1_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK1_PADSEL_SHIFT)
+
+/*
+ * NLINK0_PADSEL (RO)
+ *
+ */
+#define ESC_GPR_STATUS_NLINK0_PADSEL_MASK (0xF00000UL)
+#define ESC_GPR_STATUS_NLINK0_PADSEL_SHIFT (20U)
+#define ESC_GPR_STATUS_NLINK0_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK0_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK0_PADSEL_SHIFT)
+
+/*
+ * PDI_SOF (RO)
+ *
+ */
+#define ESC_GPR_STATUS_PDI_SOF_MASK (0x80000UL)
+#define ESC_GPR_STATUS_PDI_SOF_SHIFT (19U)
+#define ESC_GPR_STATUS_PDI_SOF_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_SOF_MASK) >> ESC_GPR_STATUS_PDI_SOF_SHIFT)
+
+/*
+ * PDI_EOF (RO)
+ *
+ */
+#define ESC_GPR_STATUS_PDI_EOF_MASK (0x40000UL)
+#define ESC_GPR_STATUS_PDI_EOF_SHIFT (18U)
+#define ESC_GPR_STATUS_PDI_EOF_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_EOF_MASK) >> ESC_GPR_STATUS_PDI_EOF_SHIFT)
+
+/*
+ * PDI_WD_TRIGGER (RO)
+ *
+ */
+#define ESC_GPR_STATUS_PDI_WD_TRIGGER_MASK (0x20000UL)
+#define ESC_GPR_STATUS_PDI_WD_TRIGGER_SHIFT (17U)
+#define ESC_GPR_STATUS_PDI_WD_TRIGGER_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_WD_TRIGGER_MASK) >> ESC_GPR_STATUS_PDI_WD_TRIGGER_SHIFT)
+
+/*
+ * PDI_WD_STATE (RO)
+ *
+ */
+#define ESC_GPR_STATUS_PDI_WD_STATE_MASK (0x10000UL)
+#define ESC_GPR_STATUS_PDI_WD_STATE_SHIFT (16U)
+#define ESC_GPR_STATUS_PDI_WD_STATE_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_WD_STATE_MASK) >> ESC_GPR_STATUS_PDI_WD_STATE_SHIFT)
+
+/*
+ * SYNC_OUT1 (RO)
+ *
+ */
+#define ESC_GPR_STATUS_SYNC_OUT1_MASK (0x200U)
+#define ESC_GPR_STATUS_SYNC_OUT1_SHIFT (9U)
+#define ESC_GPR_STATUS_SYNC_OUT1_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_SYNC_OUT1_MASK) >> ESC_GPR_STATUS_SYNC_OUT1_SHIFT)
+
+/*
+ * SYNC_OUT0 (RO)
+ *
+ */
+#define ESC_GPR_STATUS_SYNC_OUT0_MASK (0x100U)
+#define ESC_GPR_STATUS_SYNC_OUT0_SHIFT (8U)
+#define ESC_GPR_STATUS_SYNC_OUT0_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_SYNC_OUT0_MASK) >> ESC_GPR_STATUS_SYNC_OUT0_SHIFT)
+
+/*
+ * LED_STATE_RUN (RO)
+ *
+ */
+#define ESC_GPR_STATUS_LED_STATE_RUN_MASK (0x40U)
+#define ESC_GPR_STATUS_LED_STATE_RUN_SHIFT (6U)
+#define ESC_GPR_STATUS_LED_STATE_RUN_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_STATE_RUN_MASK) >> ESC_GPR_STATUS_LED_STATE_RUN_SHIFT)
+
+/*
+ * LED_ERR (RO)
+ *
+ */
+#define ESC_GPR_STATUS_LED_ERR_MASK (0x20U)
+#define ESC_GPR_STATUS_LED_ERR_SHIFT (5U)
+#define ESC_GPR_STATUS_LED_ERR_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_ERR_MASK) >> ESC_GPR_STATUS_LED_ERR_SHIFT)
+
+/*
+ * LED_RUN (RO)
+ *
+ */
+#define ESC_GPR_STATUS_LED_RUN_MASK (0x10U)
+#define ESC_GPR_STATUS_LED_RUN_SHIFT (4U)
+#define ESC_GPR_STATUS_LED_RUN_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_RUN_MASK) >> ESC_GPR_STATUS_LED_RUN_SHIFT)
+
+/*
+ * DEV_STATE (RO)
+ *
+ */
+#define ESC_GPR_STATUS_DEV_STATE_MASK (0x8U)
+#define ESC_GPR_STATUS_DEV_STATE_SHIFT (3U)
+#define ESC_GPR_STATUS_DEV_STATE_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_DEV_STATE_MASK) >> ESC_GPR_STATUS_DEV_STATE_SHIFT)
+
+/*
+ * LINK_ACT (RO)
+ *
+ */
+#define ESC_GPR_STATUS_LINK_ACT_MASK (0x7U)
+#define ESC_GPR_STATUS_LINK_ACT_SHIFT (0U)
+#define ESC_GPR_STATUS_LINK_ACT_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LINK_ACT_MASK) >> ESC_GPR_STATUS_LINK_ACT_SHIFT)
+
+/* Bitfield definition for register array: IO_CFG */
+/*
+ * INVERT (RW)
+ *
+ * 1:invert the IO
+ */
+#define ESC_IO_CFG_INVERT_MASK (0x10U)
+#define ESC_IO_CFG_INVERT_SHIFT (4U)
+#define ESC_IO_CFG_INVERT_SET(x) (((uint32_t)(x) << ESC_IO_CFG_INVERT_SHIFT) & ESC_IO_CFG_INVERT_MASK)
+#define ESC_IO_CFG_INVERT_GET(x) (((uint32_t)(x) & ESC_IO_CFG_INVERT_MASK) >> ESC_IO_CFG_INVERT_SHIFT)
+
+/*
+ * FUNC_ALT (RW)
+ *
+ * IO usage:
+ * 0:NMII_LINK0
+ * 1:NMII_LINK1
+ * 2:NMII_LINK2
+ * 3:LINK_ACT0
+ * 4:LINK_ACT1
+ * 5:LINK_ACT2
+ * 6:LED_RUN
+ * 7:LED_ERR
+ * 8:RESET_OUT
+ */
+#define ESC_IO_CFG_FUNC_ALT_MASK (0xFU)
+#define ESC_IO_CFG_FUNC_ALT_SHIFT (0U)
+#define ESC_IO_CFG_FUNC_ALT_SET(x) (((uint32_t)(x) << ESC_IO_CFG_FUNC_ALT_SHIFT) & ESC_IO_CFG_FUNC_ALT_MASK)
+#define ESC_IO_CFG_FUNC_ALT_GET(x) (((uint32_t)(x) & ESC_IO_CFG_FUNC_ALT_MASK) >> ESC_IO_CFG_FUNC_ALT_SHIFT)
+
+
+
+/* RX_ERR_CNT register group index macro definition */
+#define ESC_RX_ERR_CNT_PORT0 (0UL)
+#define ESC_RX_ERR_CNT_PORT1 (1UL)
+#define ESC_RX_ERR_CNT_PORT2 (2UL)
+#define ESC_RX_ERR_CNT_PORT3 (3UL)
+
+/* FWD_RX_ERR_CNT register group index macro definition */
+#define ESC_FWD_RX_ERR_CNT_PORT0 (0UL)
+#define ESC_FWD_RX_ERR_CNT_PORT1 (1UL)
+#define ESC_FWD_RX_ERR_CNT_PORT2 (2UL)
+#define ESC_FWD_RX_ERR_CNT_PORT3 (3UL)
+
+/* LOST_LINK_CNT register group index macro definition */
+#define ESC_LOST_LINK_CNT_PORT0 (0UL)
+#define ESC_LOST_LINK_CNT_PORT1 (1UL)
+#define ESC_LOST_LINK_CNT_PORT2 (2UL)
+#define ESC_LOST_LINK_CNT_PORT3 (3UL)
+
+/* PHY_STAT register group index macro definition */
+#define ESC_PHY_STAT_PORT0 (0UL)
+#define ESC_PHY_STAT_PORT1 (1UL)
+#define ESC_PHY_STAT_PORT2 (2UL)
+#define ESC_PHY_STAT_PORT3 (3UL)
+
+/* FMMU register group index macro definition */
+#define ESC_FMMU_0 (0UL)
+#define ESC_FMMU_1 (1UL)
+#define ESC_FMMU_2 (2UL)
+#define ESC_FMMU_3 (3UL)
+#define ESC_FMMU_4 (4UL)
+#define ESC_FMMU_5 (5UL)
+#define ESC_FMMU_6 (6UL)
+#define ESC_FMMU_7 (7UL)
+
+/* SYNCM register group index macro definition */
+#define ESC_SYNCM_0 (0UL)
+#define ESC_SYNCM_1 (1UL)
+#define ESC_SYNCM_2 (2UL)
+#define ESC_SYNCM_3 (3UL)
+#define ESC_SYNCM_4 (4UL)
+#define ESC_SYNCM_5 (5UL)
+#define ESC_SYNCM_6 (6UL)
+#define ESC_SYNCM_7 (7UL)
+
+/* RCV_TIME register group index macro definition */
+#define ESC_RCV_TIME_PORT0 (0UL)
+#define ESC_RCV_TIME_PORT1 (1UL)
+#define ESC_RCV_TIME_PORT2 (2UL)
+#define ESC_RCV_TIME_PORT3 (3UL)
+
+/* IO_CFG register group index macro definition */
+#define ESC_IO_CFG_CTR0 (0UL)
+#define ESC_IO_CFG_CTR1 (1UL)
+#define ESC_IO_CFG_CTR2 (2UL)
+#define ESC_IO_CFG_CTR3 (3UL)
+#define ESC_IO_CFG_CTR4 (4UL)
+#define ESC_IO_CFG_CTR5 (5UL)
+#define ESC_IO_CFG_CTR6 (6UL)
+#define ESC_IO_CFG_CTR7 (7UL)
+#define ESC_IO_CFG_CTR8 (8UL)
+
+
+#endif /* HPM_ESC_H */
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_mii.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_mii.h
new file mode 100644
index 00000000..bd1ee182
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_mii.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef CHRY_MII_H
+#define CHRY_MII_H
+
+/* Generic MII registers. */
+#define MII_BMCR          0x00 /* Basic Mode Control Register */
+#define MII_BMSR          0x01 /* Basic Mode Status Register  */
+#define MII_PHYSID1       0x02 /* PHY Identifier Register #1  */
+#define MII_PHYSID2       0x03 /* PHY Identifier Register #2  */
+#define MII_ANAR          0x04 /* Auto-Negotiation Advertisement Register   */
+#define MII_ANLPAR        0x05 /* Auto-Negotiation Link Partner Ability Register */
+#define MII_ANER          0x06 /* Auto-Negotiate Expansion Register          */
+#define MII_ANNPTR        0x07 /* Auto-Negotiation Next Page Transmit Register */
+#define MII_ANNPRR        0x08 /* Auto-Negotiation Next Page Receive Register  */
+#define MII_GBCR          0x09 /* 1000Base-T Control Register          */
+#define MII_GBSR          0x0a /* 1000Base-T Status Register           */
+#define MII_GBESR         0x0f /* 1000Base-T Extended Status Register  */
+
+/* Basic Mode Control Register. */
+#define BMCR_RESET        (1 << 15) /* Reset to default state      */
+#define BMCR_LOOPBACK     (1 << 14) /* TXD loopback bits           */
+#define BMCR_SPEED100     (1 << 13) /* Select 100Mbps or 10Mbps    */
+#define BMCR_ANENABLE     (1 << 12) /* Enable auto negotiation     */
+#define BMCR_POWERDOWN    (1 << 11) /* Enable low power state      */
+#define BMCR_ISOLATE      (1 << 10) /* Isolate data paths from MII */
+#define BMCR_ANRESTART    (1 << 9)  /* Auto negotiation restart    */
+#define BMCR_FULLDPLX     (1 << 8)  /* Full duplex                 */
+#define BMCR_CTST         (1 << 7)  /* Collision test              */
+#define BMCR_SPEED1000    (1 << 6)  /* MSB of Speed (1000)         */
+#define BMCR_RESV         0x003f    /* Unused...                   */
+
+/* Basic Mode Status Register. */
+#define BMSR_100T4        (1 << 15) /* Enable 100Base-T4 support  */
+#define BMSR_100FULL      (1 << 14) /* Enable 100Base-TX full duplex support  */
+#define BMSR_100HALF      (1 << 13) /* Enable 100Base-TX half duplex support  */
+#define BMSR_10FULL       (1 << 12) /* Enable 10Base-TX full duplex support  */
+#define BMSR_10HALF       (1 << 11) /* Enable 10Base-TX half duplex support  */
+#define BMSR_100HALF2     (1 << 10) /* Can do 100BASE-T2 HDX       */
+#define BMSR_100FULL2     (1 << 9)  /* Can do 100BASE-T2 FDX       */
+#define BMSR_ESTATEN      (1 << 8)  /* Extended Status in R15      */
+#define BMSR_ANEGCOMPLETE (1 << 5)  /* Auto-negotiation complete   */
+#define BMSR_REMOTEFAULT  (1 << 4)  /* Remote fault detected       */
+#define BMSR_ANEGCAPABLE  (1 << 3)  /* Able to do auto-negotiation */
+#define BMSR_LINKSTATUS   (1 << 2)  /* Link status                 */
+#define BMSR_JCD          (1 << 1)  /* Jabber detected             */
+#define BMSR_ERCAP        (1 << 0)  /* Ext-reg capability          */
+
+/* Auto-Negotiation Advertisement Register. */
+#define ANAR_NPAGE        (1 << 15) /* Next page bit               */
+#define ANAR_ACK          (1 << 14) /* Link partner acknowledges reception of local node’s capability data word   */
+#define ANAR_REMOTEFAULT  (1 << 13) /* Link partner is indicating a remote fault    */
+#define ANAR_ASYM_PAUSE   (1 << 11) /* Try for asymetric pause     */
+#define ANAR_PAUSE        (1 << 10) /* Try for pause               */
+#define ANAR_100T4        (1 << 9)  /* 100Base-T4 is supported by local mode  */
+#define ANAR_100FULL      (1 << 8)  /* 100Base-TX full duplex is supported by local mode */
+#define ANAR_100HALF      (1 << 7)  /* 100Base-TX half duplex is supported by local mode */
+#define ANAR_10FULL       (1 << 6)  /* 10Base-TX full duplex is supported by local mode */
+#define ANAR_10HALF       (1 << 5)  /* 10Base-TX half duplex is supported by local mode */
+#define ANAR_SLCT         0x001f    /* Selector bits               */
+#define ANAR_CSMA         0x0001    /* Only selector supported     */
+
+#define ANAR_SPEED_ALL    (ANAR_10HALF | ANAR_10FULL | \
+                        ANAR_100HALF | ANAR_100FULL)
+
+/* Auto-Negotiation Link Partner Ability Register. */
+#define ANLPAR_NPAGE       (1 << 15) /* Next page bit               */
+#define ANLPAR_ACK         (1 << 14) /* Link partner acknowledges reception of local node’s capability data word   */
+#define ANLPAR_REMOTEFAULT (1 << 13) /* Link partner is indicating a remote fault    */
+#define ANLPAR_ASYM_PAUSE  (1 << 11) /* Try for asymetric pause     */
+#define ANLPAR_PAUSE       (1 << 10) /* Try for pause               */
+#define ANLPAR_100T4       (1 << 9)  /* 100Base-T4 is supported by local mode  */
+#define ANLPAR_100FULL     (1 << 8)  /* 100Base-TX full duplex is supported by local mode */
+#define ANLPAR_100HALF     (1 << 7)  /* 100Base-TX half duplex is supported by local mode */
+#define ANLPAR_10FULL      (1 << 6)  /* 10Base-TX full duplex is supported by local mode */
+#define ANLPAR_10HALF      (1 << 5)  /* 10Base-TX half duplex is supported by local mode */
+#define ANLPAR_SLCT        0x001f    /* Selector bits               */
+#define ANLPAR_CSMA        0x0001    /* Only selector supported     */
+
+/* 1000Base-T Control Register          */
+#define GBCR_1000FULL      0x0200 /* Advertise 1000BASE-T full duplex */
+#define GBCR_1000HALF      0x0100 /* Advertise 1000BASE-T half duplex */
+#define GBCR_PREFER_MASTER 0x0400 /* prefer to operate as master */
+#define GBCR_AS_MASTER     0x0800
+#define GBCR_ENABLE_MASTER 0x1000
+
+/* 1000Base-T Status Register           */
+#define GBSR_1000MSFAIL    0x8000 /* Master/Slave resolution failure */
+#define GBSR_1000MSRES     0x4000 /* Master/Slave resolution status */
+#define GBSR_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
+#define GBSR_1000REMRXOK   0x1000 /* Link partner remote receiver status */
+#define GBSR_1000FULL      0x0800 /* Link partner 1000BASE-T full duplex */
+#define GBSR_1000HALF      0x0400 /* Link partner 1000BASE-T half duplex */
+
+/* 1000Base-T Extended Status Register  */
+#define GBESR_1000_XFULL   0x8000 /* Can do 1000BaseX Full       */
+#define GBESR_1000_XHALF   0x4000 /* Can do 1000BaseX Half       */
+#define GBESR_1000_TFULL   0x2000 /* Can do 1000BT Full          */
+#define GBESR_1000_THALF   0x1000 /* Can do 1000BT Half          */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy.h
new file mode 100644
index 00000000..97440c36
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef CHRY_PHY_H
+#define CHRY_PHY_H
+
+#include <stdbool.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "chry_mii.h"
+
+struct chry_phy_config {
+    bool loopback;
+    bool auto_negotiation;
+    bool duplex;
+    uint16_t speed;
+};
+
+struct chry_phy_status {
+    bool link;
+    bool duplex;
+    uint16_t speed;
+};
+
+struct chry_phy_device;
+struct chry_phy_driver {
+    char *phy_name;
+    char *phy_desc;
+    uint32_t phy_id;
+    uint32_t phy_id_mask;
+    void (*phy_init)(struct chry_phy_device *phydev, struct chry_phy_config *config);
+    void (*phy_get_status)(struct chry_phy_device *phydev, struct chry_phy_status *status);
+};
+
+struct chry_phy_support {
+    uint32_t support_100base_t4       : 1;
+    uint32_t support_1000base_tx_full : 1;
+    uint32_t support_1000base_tx_half : 1;
+    uint32_t support_100base_tx_full  : 1;
+    uint32_t support_100base_tx_half  : 1;
+    uint32_t support_10base_tx_full   : 1;
+    uint32_t support_10base_tx_half   : 1;
+    uint32_t support_asym_pause       : 1;
+    uint32_t support_pause            : 1;
+    uint32_t support_autoeng          : 1;
+
+    uint32_t reserved : 22;
+};
+
+struct chry_phy_device {
+    uint16_t phy_addr;
+    uint32_t phy_id;
+    struct chry_phy_support support;
+    const struct chry_phy_driver *driver;
+    void (*mdio_write)(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum, uint16_t val);
+    uint16_t (*mdio_read)(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum);
+    void *user_data;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int chry_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config);
+void chry_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83847.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83847.h
new file mode 100644
index 00000000..0b0078d4
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83847.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "chry_phy.h"
+
+#define DP83847_PHYSTS 0x11 /* PHY Status Register */
+
+#define DP83847_PHYSTS_LINK_STATUS (0x400U)
+/*
+ * SPEED (RO)
+ *
+ * Link Speed.
+ * 11: Reserved  10: 1000Mbps
+ * 01: 100Mbps  00: 10Mbps
+ */
+#define DP83847_PHYSTS_SPEED_STATUS  (0xC000U)
+#define DP83847_PHYSTS_DUPLEX_STATUS (0x2000U)
+
+void dp83847_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+}
+
+void dp83847_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, DP83847_PHYSTS);
+
+    status->link = regval & DP83847_PHYSTS_LINK_STATUS;
+
+    if (status->link) {
+        status->duplex = regval & DP83847_PHYSTS_DUPLEX_STATUS;
+
+        switch ((regval & DP83847_PHYSTS_SPEED_STATUS) >> 14) {
+            case 0:
+                status->speed = 10;
+                break;
+            case 1:
+                status->speed = 100;
+                break;
+            case 2:
+                status->speed = 1000;
+                break;
+
+            default:
+                break;
+        }
+    }
+}
+
+const struct chry_phy_driver dp83847_driver = {
+    .phy_id = 0x2000A230,
+    .phy_id_mask = 0xFFFFFFF0,
+    .phy_name = "DP83847",
+    .phy_desc = "TI DP83847 Ethernet PHY",
+    .phy_init = dp83847_phy_init,
+    .phy_get_status = dp83847_phy_get_status,
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83848.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83848.h
new file mode 100644
index 00000000..ffa4619a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83848.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "chry_phy.h"
+
+#define DP83848_PHYSTS 0x10 /* PHY Status Register */
+
+#define DP83848_PHYSTS_LINK_STATUS (0x0001U)
+/*
+ * SPEED_STATUS (RO)
+ *
+ * Speed10:
+ * This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced
+ * Modes.
+ * 1 = 10 Mb/s mode.
+ * 0 = 100 Mb/s mode.
+ * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid
+ * link or if Auto-Negotiation is disabled and there is a valid link.
+ */
+#define DP83848_PHYSTS_SPEED_STATUS  (0x0002U)
+#define DP83848_PHYSTS_DUPLEX_STATUS (0x0004U)
+
+void dp83848_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+}
+
+void dp83848_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, DP83848_PHYSTS);
+
+    status->link = regval & DP83848_PHYSTS_LINK_STATUS;
+
+    if (status->link) {
+        status->duplex = regval & DP83848_PHYSTS_DUPLEX_STATUS;
+        status->speed = (regval & DP83848_PHYSTS_SPEED_STATUS) ? 10 : 100;
+    }
+}
+
+const struct chry_phy_driver dp83848_driver = {
+    .phy_id = 0x20005C90,
+    .phy_id_mask = 0xFFFFFFF0,
+    .phy_name = "DP83848",
+    .phy_desc = "TI DP83848 Ethernet PHY",
+    .phy_init = dp83848_phy_init,
+    .phy_get_status = dp83848_phy_get_status,
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_jl1111.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_jl1111.h
new file mode 100644
index 00000000..ac9290d6
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_jl1111.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "chry_phy.h"
+
+void jl1111_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+}
+
+void jl1111_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_BMSR);
+    status->link = regval & BMSR_LINKSTATUS;
+
+    if (status->link) {
+        regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_ANAR) & phydev->mdio_read(phydev, phydev->phy_addr, MII_ANLPAR);
+
+        if (regval & ANAR_100HALF) {
+            if (regval & ANAR_100FULL) {
+                status->speed = 100;
+                status->duplex = true;
+            } else {
+                status->speed = 100;
+                status->duplex = false;
+            }
+        } else if (regval & ANAR_10HALF) {
+            if (regval & ANAR_10FULL) {
+                status->speed = 10;
+                status->duplex = true;
+            } else {
+                status->speed = 10;
+                status->duplex = false;
+            }
+        }
+    }
+}
+
+const struct chry_phy_driver jl1111_driver = {
+    .phy_id = 0x937C4020,
+    .phy_id_mask = 0xFFFFFFF0,
+    .phy_name = "JL1111",
+    .phy_desc = "JLSemi JL1111 Ethernet PHY",
+    .phy_init = jl1111_phy_init,
+    .phy_get_status = jl1111_phy_get_status,
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_ksz8081.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_ksz8081.h
new file mode 100644
index 00000000..3f5808c5
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_ksz8081.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "chry_phy.h"
+
+#define KSZ8081_PHY_CONTROL1 0x1EU /*!< The PHY control one register. */
+#define KSZ8081_PHY_CONTROL2 0x1FU /*!< The PHY control two register. */
+
+#define KSZ8081_PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
+
+void ksz8081_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, KSZ8081_PHY_CONTROL2);
+    phydev->mdio_write(phydev, phydev->phy_addr, KSZ8081_PHY_CONTROL2, (regval | KSZ8081_PHY_CTL2_REFCLK_SELECT_MASK));
+}
+
+void ksz8081_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, KSZ8081_PHY_CONTROL1);
+    status->link = regval & (1 << 8);
+
+    if (status->link) {
+        regval &= 0x07;
+
+        switch (regval) {
+            case 0x01:
+                status->speed = 10;
+                status->duplex = false;
+                break;
+            case 0x02:
+                status->speed = 100;
+                status->duplex = false;
+                break;
+            case 0x05:
+                status->speed = 10;
+                status->duplex = true;
+                break;
+            case 0x06:
+                status->speed = 100;
+                status->duplex = true;
+                break;
+
+            default:
+                break;
+        }
+    }
+}
+
+const struct chry_phy_driver ksz8081_driver = {
+    .phy_id = 0x00221560,
+    .phy_id_mask = 0xFFFFFFF0,
+    .phy_name = "KSZ8081",
+    .phy_desc = "MICROCHIP KSZ8081 Ethernet PHY",
+    .phy_init = ksz8081_phy_init,
+    .phy_get_status = ksz8081_phy_get_status,
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_lan8720.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_lan8720.h
new file mode 100644
index 00000000..d98c3818
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_lan8720.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "chry_phy.h"
+
+#define LAN8720_PSCSR 31 /* PHY Special Control/Status Register */
+
+#define LAN8720_PSCSR_DUPLEX_STATUS (0x10U)
+/*
+ * SPEED (RO)
+ *
+ * HCDSPEED value:
+ * 01 = 10BASE-T
+ * 10 = 100BASE-TX
+ */
+#define LAN8720_PSCSR_SPEED_STATUS (0xCU)
+
+void lan8720_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+}
+
+void lan8720_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_BMSR);
+    status->link = regval & BMSR_LINKSTATUS;
+
+    if (status->link) {
+        regval = phydev->mdio_read(phydev, phydev->phy_addr, LAN8720_PSCSR);
+        status->duplex = regval & LAN8720_PSCSR_DUPLEX_STATUS;
+
+        switch ((regval & LAN8720_PSCSR_SPEED_STATUS) >> 2) {
+            case 1:
+                status->speed = 10;
+                break;
+            case 2:
+                status->speed = 100;
+                break;
+
+            default:
+                break;
+        }
+    }
+}
+
+const struct chry_phy_driver lan8720_driver = {
+    .phy_id = 0x0007C0F0,
+    .phy_id_mask = 0xFFFFFFF0,
+    .phy_name = "LAN8720",
+    .phy_desc = "MICROCHIP LAN8720 Ethernet PHY",
+    .phy_init = lan8720_phy_init,
+    .phy_get_status = lan8720_phy_get_status,
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8201.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8201.h
new file mode 100644
index 00000000..00dd4faf
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8201.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "chry_phy.h"
+
+#define RTL8201_RMSR_P7 16 /* RMII Mode Setting Register */
+#define RTL8201_PAGESEL 31 /* Page Select Register */
+
+/*
+ * RG_RMII_CLKDIR (RW)
+ *
+ * This Bit Sets the Type of TXC in RMII Mode.
+ * 0: Output
+ * 1: Input
+ */
+#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK   (0x1000U)
+#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT  (12U)
+#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK)
+#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_GET(x) (((uint16_t)(x)&RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) >> RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT)
+
+void rtl8201_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+    uint16_t regval;
+
+    phydev->mdio_write(phydev, phydev->phy_addr, RTL8201_PAGESEL, 7);
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, RTL8201_RMSR_P7);
+    regval &= ~RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK;
+    regval |= RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(1);
+    phydev->mdio_write(phydev, phydev->phy_addr, RTL8201_RMSR_P7, regval);
+}
+
+void rtl8201_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_BMSR);
+    status->link = regval & BMSR_LINKSTATUS;
+
+    if (status->link) {
+        regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_BMCR);
+        status->speed = regval & BMCR_SPEED100 ? 100 : 10;
+        status->duplex = regval & BMCR_FULLDPLX;
+    }
+}
+
+const struct chry_phy_driver rtl8201_driver = {
+    .phy_id = 0x001CC810,
+    .phy_id_mask = 0xFFFFFFF0,
+    .phy_name = "RTL8201",
+    .phy_desc = "REALTEK RTL8201 Ethernet PHY",
+    .phy_init = rtl8201_phy_init,
+    .phy_get_status = rtl8201_phy_get_status,
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8211.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8211.h
new file mode 100644
index 00000000..27dd44d3
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8211.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "chry_phy.h"
+
+#define RTL8211_PHYSR 17 /* PHY Specific Status Register */
+
+#define RTL8211_PHYSTS_LINK_STATUS (0x400U)
+/*
+ * SPEED (RO)
+ *
+ * Link Speed.
+ * 11: Reserved  10: 1000Mbps
+ * 01: 100Mbps  00: 10Mbps
+ */
+#define RTL8211_PHYSTS_SPEED_STATUS  (0xC000U)
+#define RTL8211_PHYSTS_DUPLEX_STATUS (0x2000U)
+
+void rtl8211_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+}
+
+void rtl8211_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, RTL8211_PHYSR);
+
+    status->link = regval & RTL8211_PHYSTS_LINK_STATUS;
+
+    if (status->link) {
+        status->duplex = regval & RTL8211_PHYSTS_DUPLEX_STATUS;
+
+        switch ((regval & RTL8211_PHYSTS_SPEED_STATUS) >> 14) {
+            case 0:
+                status->speed = 10;
+                break;
+            case 1:
+                status->speed = 100;
+                break;
+            case 2:
+                status->speed = 1000;
+                break;
+
+            default:
+                break;
+        }
+    }
+}
+
+const struct chry_phy_driver rtl8211_driver = {
+    .phy_id = 0x001CC910,
+    .phy_id_mask = 0xFFFFFFF0,
+    .phy_name = "RTL8211",
+    .phy_desc = "REALTEK RTL8211 Ethernet PHY",
+    .phy_init = rtl8211_phy_init,
+    .phy_get_status = rtl8211_phy_get_status,
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_yt8522.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_yt8522.h
new file mode 100644
index 00000000..af66903b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_yt8522.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "chry_phy.h"
+
+#define YT8522_PHYSTS 0x11 /* PHY Status Register */
+
+#define YT8522_PHYSTS_LINK_STATUS (0x400U)
+/*
+ * SPEED (RO)
+ *
+ * Link Speed.
+ * 11: Reserved  10: 1000Mbps
+ * 01: 100Mbps  00: 10Mbps
+ */
+#define YT8522_PHYSTS_SPEED_STATUS  (0xC000U)
+#define YT8522_PHYSTS_DUPLEX_STATUS (0x2000U)
+
+void yt8522_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+}
+
+void yt8522_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    uint16_t regval;
+
+    regval = phydev->mdio_read(phydev, phydev->phy_addr, YT8522_PHYSTS);
+
+    status->link = regval & YT8522_PHYSTS_LINK_STATUS;
+
+    if (status->link) {
+        status->duplex = regval & YT8522_PHYSTS_DUPLEX_STATUS;
+
+        switch ((regval & YT8522_PHYSTS_SPEED_STATUS) >> 14) {
+            case 0:
+                status->speed = 10;
+                break;
+            case 1:
+                status->speed = 100;
+                break;
+            case 2:
+                status->speed = 1000;
+                break;
+
+            default:
+                break;
+        }
+    }
+}
+
+const struct chry_phy_driver yt8522_driver = {
+    .phy_id = 0x4F51E900,
+    .phy_id_mask = 0xFFFFFFC0,
+    .phy_name = "YT8512/YT8522/YT8531",
+    .phy_desc = "MOTOR COMM YT8512/YT8522/YT8531 Ethernet PHY",
+    .phy_init = yt8522_phy_init,
+    .phy_get_status = yt8522_phy_get_status,
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_freertos.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_freertos.c
new file mode 100644
index 00000000..b005fc71
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_freertos.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+#include <FreeRTOS.h>
+#include "semphr.h"
+#include "event_groups.h"
+
+ec_osal_thread_t ec_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, ec_thread_entry_t entry, void *args)
+{
+    TaskHandle_t htask = NULL;
+    stack_size /= sizeof(StackType_t);
+    xTaskCreate(entry, name, stack_size, args, configMAX_PRIORITIES - 1 - prio, &htask);
+    if (htask == NULL) {
+        EC_LOG_ERR("Create thread %s failed\r\n", name);
+        while (1) {
+        }
+    }
+    return (ec_osal_thread_t)htask;
+}
+
+void ec_osal_thread_delete(ec_osal_thread_t thread)
+{
+    vTaskDelete(thread);
+}
+
+void ec_osal_thread_suspend(ec_osal_thread_t thread)
+{
+    vTaskSuspend((TaskHandle_t)thread);
+}
+
+void ec_osal_thread_resume(ec_osal_thread_t thread)
+{
+    vTaskResume((TaskHandle_t)thread);
+}
+
+ec_osal_sem_t ec_osal_sem_create(uint32_t max_count, uint32_t initial_count)
+{
+    ec_osal_sem_t sem = (ec_osal_sem_t)xSemaphoreCreateCounting(max_count, initial_count);
+    if (sem == NULL) {
+        EC_LOG_ERR("Create semaphore failed\r\n");
+        while (1) {
+        }
+    }
+    return sem;
+}
+
+void ec_osal_sem_delete(ec_osal_sem_t sem)
+{
+    vSemaphoreDelete((SemaphoreHandle_t)sem);
+}
+
+int ec_osal_sem_take(ec_osal_sem_t sem, uint32_t timeout)
+{
+    if (timeout == EC_OSAL_WAITING_FOREVER) {
+        return (xSemaphoreTake((SemaphoreHandle_t)sem, portMAX_DELAY) == pdPASS) ? 0 : -EC_ERR_TIMEOUT;
+    } else {
+        return (xSemaphoreTake((SemaphoreHandle_t)sem, pdMS_TO_TICKS(timeout)) == pdPASS) ? 0 : -EC_ERR_TIMEOUT;
+    }
+}
+
+int ec_osal_sem_give(ec_osal_sem_t sem)
+{
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+    int ret;
+
+    if (xPortIsInsideInterrupt()) {
+        ret = xSemaphoreGiveFromISR((SemaphoreHandle_t)sem, &xHigherPriorityTaskWoken);
+        if (ret == pdPASS) {
+            portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+        }
+    } else {
+        ret = xSemaphoreGive((SemaphoreHandle_t)sem);
+    }
+
+    return (ret == pdPASS) ? 0 : -EC_ERR_TIMEOUT;
+}
+
+void ec_osal_sem_reset(ec_osal_sem_t sem)
+{
+    xQueueReset((QueueHandle_t)sem);
+}
+
+ec_osal_mutex_t ec_osal_mutex_create(void)
+{
+    ec_osal_mutex_t mutex = (ec_osal_mutex_t)xSemaphoreCreateMutex();
+    if (mutex == NULL) {
+        EC_LOG_ERR("Create mutex failed\r\n");
+        while (1) {
+        }
+    }
+    return mutex;
+}
+
+void ec_osal_mutex_delete(ec_osal_mutex_t mutex)
+{
+    vSemaphoreDelete((SemaphoreHandle_t)mutex);
+}
+
+int ec_osal_mutex_take(ec_osal_mutex_t mutex)
+{
+    return (xSemaphoreTake((SemaphoreHandle_t)mutex, portMAX_DELAY) == pdPASS) ? 0 : -EC_ERR_TIMEOUT;
+}
+
+int ec_osal_mutex_give(ec_osal_mutex_t mutex)
+{
+    return (xSemaphoreGive((SemaphoreHandle_t)mutex) == pdPASS) ? 0 : -EC_ERR_TIMEOUT;
+}
+
+static void __ec_timeout(TimerHandle_t *handle)
+{
+    struct ec_osal_timer *timer = (struct ec_osal_timer *)pvTimerGetTimerID((TimerHandle_t)handle);
+
+    timer->handler(timer->argument);
+}
+
+struct ec_osal_timer *ec_osal_timer_create(const char *name, uint32_t timeout_ms, ec_timer_handler_t handler, void *argument, bool is_period)
+{
+    struct ec_osal_timer *timer;
+    (void)name;
+
+    timer = pvPortMalloc(sizeof(struct ec_osal_timer));
+
+    if (timer == NULL) {
+        EC_LOG_ERR("Create ec_osal_timer failed\r\n");
+        while (1) {
+        }
+    }
+    memset(timer, 0, sizeof(struct ec_osal_timer));
+
+    timer->handler = handler;
+    timer->argument = argument;
+
+    timer->timer = (void *)xTimerCreate("ec_tim", pdMS_TO_TICKS(timeout_ms), is_period, timer, (TimerCallbackFunction_t)__ec_timeout);
+    if (timer->timer == NULL) {
+        EC_LOG_ERR("Create timer failed\r\n");
+        while (1) {
+        }
+    }
+    return timer;
+}
+
+void ec_osal_timer_delete(struct ec_osal_timer *timer)
+{
+    xTimerStop(timer->timer, 0);
+    xTimerDelete(timer->timer, 0);
+    vPortFree(timer);
+}
+
+void ec_osal_timer_start(struct ec_osal_timer *timer)
+{
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+    int ret;
+
+    if (xPortIsInsideInterrupt()) {
+        ret = xTimerStartFromISR(timer->timer, &xHigherPriorityTaskWoken);
+        if (ret == pdPASS) {
+            portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+        }
+    } else {
+        xTimerStart(timer->timer, 0);
+    }
+}
+
+void ec_osal_timer_stop(struct ec_osal_timer *timer)
+{
+    xTimerStop(timer->timer, 0);
+}
+
+size_t ec_osal_enter_critical_section(void)
+{
+    size_t ret;
+
+    if (xPortIsInsideInterrupt()) {
+        ret = taskENTER_CRITICAL_FROM_ISR();
+    } else {
+        taskENTER_CRITICAL();
+        ret = 1;
+    }
+
+    return ret;
+}
+
+void ec_osal_leave_critical_section(size_t flag)
+{
+    if (xPortIsInsideInterrupt()) {
+        taskEXIT_CRITICAL_FROM_ISR(flag);
+    } else {
+        taskEXIT_CRITICAL();
+    }
+}
+
+void ec_osal_msleep(uint32_t delay)
+{
+    vTaskDelay(pdMS_TO_TICKS(delay));
+}
+
+void *ec_osal_malloc(size_t size)
+{
+    return pvPortMalloc(size);
+}
+
+void ec_osal_free(void *ptr)
+{
+    vPortFree(ptr);
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_rtthread.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_rtthread.c
new file mode 100644
index 00000000..74788d79
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_rtthread.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+#include <rtthread.h>
+#include <rthw.h>
+
+ec_osal_thread_t ec_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, ec_thread_entry_t entry, void *args)
+{
+    rt_thread_t htask;
+    htask = rt_thread_create(name, entry, args, stack_size, prio, 10);
+    if (htask == NULL) {
+        EC_LOG_ERR("Create thread %s failed\r\n", name);
+        while (1) {
+        }
+    }
+    rt_thread_startup(htask);
+    return (ec_osal_thread_t)htask;
+}
+
+void ec_osal_thread_delete(ec_osal_thread_t thread)
+{
+    if (thread == NULL) {
+        rt_thread_t self = rt_thread_self();
+        rt_thread_control(self, RT_THREAD_CTRL_CLOSE, RT_NULL);
+        return;
+    }
+
+    rt_thread_delete(thread);
+}
+
+void ec_osal_thread_suspend(ec_osal_thread_t thread)
+{
+    rt_thread_suspend((rt_thread_t)thread);
+}
+
+void ec_osal_thread_resume(ec_osal_thread_t thread)
+{
+    rt_thread_resume((rt_thread_t)thread);
+}
+
+ec_osal_sem_t ec_osal_sem_create(uint32_t max_count, uint32_t initial_count)
+{
+    ec_osal_sem_t sem = (ec_osal_sem_t)rt_sem_create("ec_sem", initial_count, RT_IPC_FLAG_FIFO);
+    if (sem == NULL) {
+        EC_LOG_ERR("Create semaphore failed\r\n");
+        while (1) {
+        }
+    }
+    return sem;
+}
+
+void ec_osal_sem_delete(ec_osal_sem_t sem)
+{
+    rt_sem_delete((rt_sem_t)sem);
+}
+
+int ec_osal_sem_take(ec_osal_sem_t sem, uint32_t timeout)
+{
+    int ret = 0;
+    rt_err_t result = RT_EOK;
+
+    if (timeout == EC_OSAL_WAITING_FOREVER) {
+        result = rt_sem_take((rt_sem_t)sem, RT_WAITING_FOREVER);
+    } else {
+        result = rt_sem_take((rt_sem_t)sem, rt_tick_from_millisecond(timeout));
+    }
+    if (result == -RT_ETIMEOUT) {
+        ret = -EC_ERR_TIMEOUT;
+    } else if (result == -RT_ERROR) {
+        ret = -EC_ERR_INVAL;
+    } else {
+        ret = 0;
+    }
+
+    return (int)ret;
+}
+
+int ec_osal_sem_give(ec_osal_sem_t sem)
+{
+    return (int)rt_sem_release((rt_sem_t)sem);
+}
+
+void ec_osal_sem_reset(ec_osal_sem_t sem)
+{
+    rt_sem_control((rt_sem_t)sem, RT_IPC_CMD_RESET, (void *)0);
+}
+
+ec_osal_mutex_t ec_osal_mutex_create(void)
+{
+    ec_osal_mutex_t mutex = (ec_osal_mutex_t)rt_mutex_create("ec_mutex", RT_IPC_FLAG_FIFO);
+    if (mutex == NULL) {
+        EC_LOG_ERR("Create mutex failed\r\n");
+        while (1) {
+        }
+    }
+    return mutex;
+}
+
+void ec_osal_mutex_delete(ec_osal_mutex_t mutex)
+{
+    rt_mutex_delete((rt_mutex_t)mutex);
+}
+
+int ec_osal_mutex_take(ec_osal_mutex_t mutex)
+{
+    return (int)rt_mutex_take((rt_mutex_t)mutex, RT_WAITING_FOREVER);
+}
+
+int ec_osal_mutex_give(ec_osal_mutex_t mutex)
+{
+    return (int)rt_mutex_release((rt_mutex_t)mutex);
+}
+
+struct ec_osal_timer *ec_osal_timer_create(const char *name, uint32_t timeout_ms, ec_timer_handler_t handler, void *argument, bool is_period)
+{
+    struct ec_osal_timer *timer;
+
+    timer = rt_malloc(sizeof(struct ec_osal_timer));
+    if (timer == NULL) {
+        EC_LOG_ERR("Create ec_osal_timer failed\r\n");
+        while (1) {
+        }
+    }
+    memset(timer, 0, sizeof(struct ec_osal_timer));
+
+    timer->timer = (void *)rt_timer_create(name, handler, argument, timeout_ms, is_period ? (RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER) : (RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER));
+    if (timer->timer == NULL) {
+        EC_LOG_ERR("Create timer failed\r\n");
+        while (1) {
+        }
+    }
+    return timer;
+}
+
+void ec_osal_timer_delete(struct ec_osal_timer *timer)
+{
+    rt_timer_stop(timer->timer);
+    rt_timer_delete(timer->timer);
+    rt_free(timer);
+}
+
+void ec_osal_timer_start(struct ec_osal_timer *timer)
+{
+    rt_timer_start(timer->timer);
+}
+
+void ec_osal_timer_stop(struct ec_osal_timer *timer)
+{
+    rt_timer_stop(timer->timer);
+}
+
+size_t ec_osal_enter_critical_section(void)
+{
+    return rt_hw_interrupt_disable();
+}
+
+void ec_osal_leave_critical_section(size_t flag)
+{
+    rt_hw_interrupt_enable(flag);
+}
+
+void ec_osal_msleep(uint32_t delay)
+{
+    rt_thread_mdelay(delay);
+}
+
+void *ec_osal_malloc(size_t size)
+{
+    return rt_malloc(size);
+}
+
+void ec_osal_free(void *ptr)
+{
+    rt_free(ptr);
+}
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_threadx.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_threadx.c
new file mode 100644
index 00000000..a45671a4
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_threadx.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+#include "tx_api.h"
+
+/* create bytepool in tx_application_define
+ *
+ * tx_byte_pool_create(&ec_byte_pool, "ec byte pool", memory_area, 65536);
+ */
+
+extern TX_BYTE_POOL ec_byte_pool;
+
+ec_osal_thread_t ec_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, ec_thread_entry_t entry, void *args)
+{
+    CHAR *pointer = TX_NULL;
+    TX_THREAD *thread_ptr = TX_NULL;
+
+    tx_byte_allocate(&ec_byte_pool, (VOID **)&thread_ptr, sizeof(TX_THREAD), TX_NO_WAIT);
+
+    if (thread_ptr == TX_NULL) {
+        EC_LOG_ERR("Create thread %s failed\r\n", name);
+        while (1) {
+        }
+    }
+
+    tx_byte_allocate(&ec_byte_pool, (VOID **)&pointer, stack_size, TX_NO_WAIT);
+    if (pointer == TX_NULL) {
+        EC_LOG_ERR("Create thread %s failed\r\n", name);
+        while (1) {
+        }
+    }
+
+    tx_thread_create(thread_ptr, (CHAR *)name, (VOID(*)(ULONG))entry, (uintptr_t)args,
+                     pointer, stack_size,
+                     prio, prio, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    return (ec_osal_thread_t)thread_ptr;
+}
+
+void ec_osal_thread_delete(ec_osal_thread_t thread)
+{
+    TX_THREAD *thread_ptr = NULL;
+
+    if (thread == NULL) {
+        /* Call the tx_thread_identify to get the control block pointer of the
+        currently executing thread. */
+        thread_ptr = tx_thread_identify();
+
+        /* Check if the current running thread pointer is not NULL */
+        if (thread_ptr != NULL) {
+            /* Call the tx_thread_terminate to terminates the specified application
+            thread regardless of whether the thread is suspended or not. A thread
+            may call this service to terminate itself. */
+            tx_thread_terminate(thread_ptr);
+            tx_byte_release(thread_ptr->tx_thread_stack_start);
+            tx_byte_release(thread_ptr);
+        }
+        return;
+    }
+
+    tx_thread_terminate(thread);
+    tx_byte_release(thread_ptr->tx_thread_stack_start);
+    tx_byte_release(thread);
+}
+
+void ec_osal_thread_suspend(ec_osal_thread_t thread)
+{
+    tx_thread_suspend((TX_THREAD *)thread);
+}
+
+void ec_osal_thread_resume(ec_osal_thread_t thread)
+{
+    tx_thread_resume((TX_THREAD *)thread);
+}
+
+ec_osal_sem_t ec_osal_sem_create(uint32_t max_count, uint32_t initial_count)
+{
+    TX_SEMAPHORE *sem_ptr = TX_NULL;
+
+    tx_byte_allocate(&ec_byte_pool, (VOID **)&sem_ptr, sizeof(TX_SEMAPHORE), TX_NO_WAIT);
+
+    if (sem_ptr == TX_NULL) {
+        EC_LOG_ERR("Create semaphore failed\r\n");
+        while (1) {
+        }
+    }
+
+    tx_semaphore_create(sem_ptr, "ec_sem", initial_count);
+    return (ec_osal_sem_t)sem_ptr;
+}
+
+void ec_osal_sem_delete(ec_osal_sem_t sem)
+{
+    tx_semaphore_delete((TX_SEMAPHORE *)sem);
+    tx_byte_release(sem);
+}
+
+int ec_osal_sem_take(ec_osal_sem_t sem, uint32_t timeout)
+{
+    int ret = 0;
+
+    ret = tx_semaphore_get((TX_SEMAPHORE *)sem, timeout);
+    if (ret == TX_SUCCESS) {
+        ret = 0;
+    } else if ((ret == TX_WAIT_ABORTED) || (ret == TX_NO_INSTANCE)) {
+        ret = -EC_ERR_TIMEOUT;
+    } else {
+        ret = -EC_ERR_INVAL;
+    }
+
+    return (int)ret;
+}
+
+int ec_osal_sem_give(ec_osal_sem_t sem)
+{
+    return (int)tx_semaphore_put((TX_SEMAPHORE *)sem);
+}
+
+void ec_osal_sem_reset(ec_osal_sem_t sem)
+{
+    tx_semaphore_get((TX_SEMAPHORE *)sem, 0);
+}
+
+ec_osal_mutex_t ec_osal_mutex_create(void)
+{
+    TX_MUTEX *mutex_ptr = TX_NULL;
+
+    tx_byte_allocate(&ec_byte_pool, (VOID **)&mutex_ptr, sizeof(TX_MUTEX), TX_NO_WAIT);
+
+    if (mutex_ptr == TX_NULL) {
+        EC_LOG_ERR("Create mutex failed\r\n");
+        while (1) {
+        }
+    }
+
+    tx_mutex_create(mutex_ptr, "ec_mutx", TX_INHERIT);
+    return (ec_osal_mutex_t)mutex_ptr;
+}
+
+void ec_osal_mutex_delete(ec_osal_mutex_t mutex)
+{
+    tx_mutex_delete((TX_MUTEX *)mutex);
+    tx_byte_release(mutex);
+}
+
+int ec_osal_mutex_take(ec_osal_mutex_t mutex)
+{
+    int ret = 0;
+
+    ret = tx_mutex_get((TX_MUTEX *)mutex, TX_WAIT_FOREVER);
+    if (ret == TX_SUCCESS) {
+        ret = 0;
+    } else if ((ret == TX_WAIT_ABORTED) || (ret == TX_NO_INSTANCE)) {
+        ret = -EC_ERR_TIMEOUT;
+    } else {
+        ret = -EC_ERR_INVAL;
+    }
+
+    return (int)ret;
+}
+
+int ec_osal_mutex_give(ec_osal_mutex_t mutex)
+{
+    return (int)(tx_mutex_put((TX_MUTEX *)mutex) == TX_SUCCESS) ? 0 : -EC_ERR_INVAL;
+}
+
+struct ec_osal_timer *ec_osal_timer_create(const char *name, uint32_t timeout_ms, ec_timer_handler_t handler, void *argument, bool is_period)
+{
+    TX_TIMER *timer_ptr = TX_NULL;
+    struct ec_osal_timer *timer;
+
+    tx_byte_allocate(&ec_byte_pool, (VOID **)&timer, sizeof(struct ec_osal_timer), TX_NO_WAIT);
+
+    if (timer == TX_NULL) {
+        EC_LOG_ERR("Create ec_osal_timer failed\r\n");
+        while (1) {
+        }
+    }
+    memset(timer, 0, sizeof(struct ec_osal_timer));
+
+    tx_byte_allocate(&ec_byte_pool, (VOID **)&timer_ptr, sizeof(TX_TIMER), TX_NO_WAIT);
+
+    if (timer_ptr == TX_NULL) {
+        EC_LOG_ERR("Create TX_TIMER failed\r\n");
+        while (1) {
+        }
+    }
+
+    timer->timer = timer_ptr;
+    timer->timeout_ms = timeout_ms;
+    timer->is_period = is_period;
+    if (tx_timer_create(timer_ptr, (CHAR *)name, (void (*)(ULONG))handler, (uintptr_t)argument, 1, is_period ? 1 : 0,
+                        TX_NO_ACTIVATE) != TX_SUCCESS) {
+        return NULL;
+    }
+    return timer;
+}
+
+void ec_osal_timer_delete(struct ec_osal_timer *timer)
+{
+    tx_timer_deactivate((TX_TIMER *)timer->timer);
+    tx_timer_delete((TX_TIMER *)timer->timer);
+    tx_byte_release(timer->timer);
+    tx_byte_release(timer);
+}
+
+void ec_osal_timer_start(struct ec_osal_timer *timer)
+{
+    if (tx_timer_change((TX_TIMER *)timer->timer, timer->timeout_ms, timer->is_period ? timer->timeout_ms : 0) == TX_SUCCESS) {
+        /* Call the tx_timer_activate to activates the specified application
+             timer. The expiration routines of timers that expire at the same
+             time are executed in the order they were activated. */
+        if (tx_timer_activate((TX_TIMER *)timer->timer) == TX_SUCCESS) {
+            /* Return osOK for success */
+        } else {
+            /* Return osErrorResource in case of error */
+        }
+    } else {
+    }
+}
+
+void ec_osal_timer_stop(struct ec_osal_timer *timer)
+{
+    tx_timer_deactivate((TX_TIMER *)timer->timer);
+}
+
+size_t ec_osal_enter_critical_section(void)
+{
+    TX_INTERRUPT_SAVE_AREA
+
+    TX_DISABLE
+
+    return interrupt_save;
+}
+
+void ec_osal_leave_critical_section(size_t flag)
+{
+    int interrupt_save;
+
+    interrupt_save = flag;
+    TX_RESTORE
+}
+
+void ec_osal_msleep(uint32_t delay)
+{
+#if TX_TIMER_TICKS_PER_SECOND != 1000
+#error "TX_TIMER_TICKS_PER_SECOND must be 1000"
+#endif
+    tx_thread_sleep(delay);
+}
+
+void *ec_osal_malloc(size_t size)
+{
+    CHAR *pointer = TX_NULL;
+
+    tx_byte_allocate(&ec_byte_pool, (VOID **)&pointer, size, TX_WAIT_FOREVER);
+
+    return pointer;
+}
+
+void ec_osal_free(void *ptr)
+{
+    tx_byte_release(ptr);
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_hpmicro.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_hpmicro.c
new file mode 100644
index 00000000..93726b5e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_hpmicro.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "hpm_clock_drv.h"
+#include "hpm_enet_drv.h"
+#include "hpm_enet_phy_common.h"
+#include "hpm_otp_drv.h"
+#include "hpm_l1c_drv.h"
+#include "board.h"
+#include "ec_master.h"
+
+#if defined(RGMII) && RGMII
+#define ENET_INF_TYPE enet_inf_rgmii
+#define ENET          BOARD_ENET_RGMII
+#else
+#define ENET_INF_TYPE enet_inf_rmii
+#define ENET          BOARD_ENET_RMII
+#endif
+
+#define __ENABLE_ENET_RECEIVE_INTERRUPT 1
+
+#define MAC_ADDR0 0x00
+#define MAC_ADDR1 0x80
+#define MAC_ADDR2 0xE1
+#define MAC_ADDR3 0x00
+#define MAC_ADDR4 0x00
+#define MAC_ADDR5 0x00
+
+#define ENET_TX_BUFF_COUNT CONFIG_EC_MAX_ENET_TXBUF_COUNT
+#define ENET_RX_BUFF_COUNT CONFIG_EC_MAX_ENET_RXBUF_COUNT
+#define ENET_RX_BUFF_SIZE  ENET_MAX_FRAME_SIZE
+#define ENET_TX_BUFF_SIZE  ENET_MAX_FRAME_SIZE
+
+ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT)
+__RW enet_rx_desc_t dma_rx_desc_tab[ENET_RX_BUFF_COUNT]; /* Ethernet Rx DMA Descriptor */
+
+ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT)
+__RW enet_tx_desc_t dma_tx_desc_tab[ENET_TX_BUFF_COUNT]; /* Ethernet Tx DMA Descriptor */
+
+ATTR_PLACE_AT_FAST_RAM_BSS_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT)
+__RW uint8_t rx_buff[ENET_RX_BUFF_COUNT][ENET_RX_BUFF_SIZE]; /* Ethernet Receive Buffer */
+
+ATTR_PLACE_AT_FAST_RAM_BSS_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT)
+__RW uint8_t tx_buff[ENET_TX_BUFF_COUNT][ENET_TX_BUFF_SIZE]; /* Ethernet Transmit Buffer */
+
+enet_desc_t desc;
+uint8_t mac[ENET_MAC];
+
+ec_netdev_t g_netdev;
+
+ATTR_WEAK void enet_get_mac_address(uint8_t *mac)
+{
+    bool invalid = true;
+
+    uint32_t uuid[(ENET_MAC + (ENET_MAC - 1)) / sizeof(uint32_t)];
+
+    for (int i = 0; i < ARRAY_SIZE(uuid); i++) {
+        uuid[i] = otp_read_from_shadow(OTP_SOC_UUID_IDX + i);
+        if (uuid[i] != 0xFFFFFFFFUL && uuid[i] != 0) {
+            invalid = false;
+        }
+    }
+
+    if (invalid == true) {
+        ec_memcpy(mac, &uuid, ENET_MAC);
+    } else {
+        mac[0] = MAC_ADDR0;
+        mac[1] = MAC_ADDR1;
+        mac[2] = MAC_ADDR2;
+        mac[3] = MAC_ADDR3;
+        mac[4] = MAC_ADDR4;
+        mac[5] = MAC_ADDR5;
+    }
+}
+
+hpm_stat_t enet_init(ENET_Type *ptr)
+{
+    enet_int_config_t int_config = { .int_enable = 0, .int_mask = 0 };
+    enet_mac_config_t enet_config;
+    enet_tx_control_config_t enet_tx_control_config;
+
+#ifdef CONFIG_EC_PHY_CUSTOM
+#if defined(RGMII) && RGMII
+#if defined(__USE_DP83867) && __USE_DP83867
+    dp83867_config_t phy_config;
+#else
+    rtl8211_config_t phy_config;
+#endif
+#else
+#if defined(__USE_DP83848) && __USE_DP83848
+    dp83848_config_t phy_config;
+#else
+    rtl8201_config_t phy_config;
+#endif
+#endif
+#endif
+
+    /* Initialize td, rd and the corresponding buffers */
+    memset((uint8_t *)dma_tx_desc_tab, 0x00, sizeof(dma_tx_desc_tab));
+    memset((uint8_t *)dma_rx_desc_tab, 0x00, sizeof(dma_rx_desc_tab));
+    memset((uint8_t *)rx_buff, 0x00, sizeof(rx_buff));
+    memset((uint8_t *)tx_buff, 0x00, sizeof(tx_buff));
+
+    desc.tx_desc_list_head = (enet_tx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)dma_tx_desc_tab);
+    desc.rx_desc_list_head = (enet_rx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)dma_rx_desc_tab);
+
+    desc.tx_buff_cfg.buffer = core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)tx_buff);
+    desc.tx_buff_cfg.count = ENET_TX_BUFF_COUNT;
+    desc.tx_buff_cfg.size = ENET_TX_BUFF_SIZE;
+
+    desc.rx_buff_cfg.buffer = core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)rx_buff);
+    desc.rx_buff_cfg.count = ENET_RX_BUFF_COUNT;
+    desc.rx_buff_cfg.size = ENET_RX_BUFF_SIZE;
+
+    /*Get a default control config for tx descriptor */
+    enet_get_default_tx_control_config(ENET, &enet_tx_control_config);
+
+    /* Set the control config for tx descriptor */
+    ec_memcpy(&desc.tx_control_config, &enet_tx_control_config, sizeof(enet_tx_control_config_t));
+
+    /* Get MAC address */
+    enet_get_mac_address(mac);
+
+    /* Set MAC0 address */
+    enet_config.mac_addr_high[0] = mac[5] << 8 | mac[4];
+    enet_config.mac_addr_low[0] = mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0];
+    enet_config.valid_max_count = 1;
+
+    /* Set DMA PBL */
+    enet_config.dma_pbl = board_get_enet_dma_pbl(ENET);
+
+    /* Set SARC */
+    enet_config.sarc = enet_sarc_replace_mac0;
+
+#if defined(__ENABLE_ENET_RECEIVE_INTERRUPT) && __ENABLE_ENET_RECEIVE_INTERRUPT
+    /* Enable Enet IRQ */
+    board_enable_enet_irq(ENET);
+
+    /* Get the default interrupt config */
+    enet_get_default_interrupt_config(ENET, &int_config);
+#endif
+
+    /* Initialize enet controller */
+    if (enet_controller_init(ptr, ENET_INF_TYPE, &desc, &enet_config, &int_config) != status_success) {
+        return status_fail;
+    }
+
+#if defined(__ENABLE_ENET_RECEIVE_INTERRUPT) && __ENABLE_ENET_RECEIVE_INTERRUPT
+    /* Disable LPI interrupt */
+    enet_disable_lpi_interrupt(ENET);
+#endif
+
+#ifdef CONFIG_EC_PHY_CUSTOM
+/* Initialize phy */
+#if defined(RGMII) && RGMII
+#if defined(__USE_DP83867) && __USE_DP83867
+    dp83867_reset(ptr);
+#if defined(__DISABLE_AUTO_NEGO) && __DISABLE_AUTO_NEGO
+    dp83867_set_mdi_crossover_mode(ENET, enet_phy_mdi_crossover_manual_mdix);
+#endif
+    dp83867_basic_mode_default_config(ptr, &phy_config);
+    if (dp83867_basic_mode_init(ptr, &phy_config) == true) {
+#else
+    rtl8211_reset(ptr);
+    rtl8211_basic_mode_default_config(ptr, &phy_config);
+    if (rtl8211_basic_mode_init(ptr, &phy_config) == true) {
+#endif
+#else
+#if defined(__USE_DP83848) && __USE_DP83848
+    dp83848_reset(ptr);
+    dp83848_basic_mode_default_config(ptr, &phy_config);
+    if (dp83848_basic_mode_init(ptr, &phy_config) == true) {
+#else
+    rtl8201_reset(ptr);
+    rtl8201_basic_mode_default_config(ptr, &phy_config);
+    if (rtl8201_basic_mode_init(ptr, &phy_config) == true) {
+#endif
+#endif
+        EC_LOG_DBG("Enet phy init passed !\n");
+    } else {
+        EC_LOG_DBG("Enet phy init failed !\n");
+        return status_fail;
+    }
+#endif
+    return status_success;
+}
+
+ec_netdev_t *ec_netdev_low_level_init(uint8_t netdev_index)
+{
+    /* Initialize GPIOs */
+    board_init_enet_pins(ENET);
+
+    /* Reset an enet PHY */
+    board_reset_enet_phy(ENET);
+#if defined(RGMII) && RGMII
+    /* Set RGMII clock delay */
+    board_init_enet_rgmii_clock_delay(ENET);
+#else
+    /* Set RMII reference clock */
+    board_init_enet_rmii_reference_clock(ENET, BOARD_ENET_RMII_INT_REF_CLK);
+    EC_LOG_DBG("Reference Clock: %s\n", BOARD_ENET_RMII_INT_REF_CLK ? "Internal Clock" : "External Clock");
+#endif
+
+    /* Initialize MAC and DMA */
+    if (enet_init(ENET) == 0) {
+    } else {
+        EC_LOG_DBG("Enet initialization fails !!!\n");
+        while (1) {
+        }
+    }
+
+    ec_memcpy(g_netdev.mac_addr, mac, ENET_MAC);
+
+    for (uint32_t i = 0; i < ENET_TX_BUFF_COUNT; i++) {
+        for (uint8_t j = 0; j < 6; j++) { // dst MAC
+            EC_WRITE_U8(&tx_buff[i][j], 0xFF);
+        }
+        for (uint8_t j = 0; j < 6; j++) { // src MAC
+            EC_WRITE_U8(&tx_buff[i][6 + j], mac[j]);
+        }
+        EC_WRITE_U16(&tx_buff[i][12], ec_htons(0x88a4));
+    }
+
+    return &g_netdev;
+}
+
+#ifndef CONFIG_EC_PHY_CUSTOM
+void ec_mdio_low_level_write(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum, uint16_t val)
+{
+    //ec_netdev_t *netdev = (ec_netdev_t *)phydev->user_data;
+    enet_write_phy(ENET, phy_addr, regnum, val);
+}
+
+uint16_t ec_mdio_low_level_read(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum)
+{
+    //ec_netdev_t *netdev = (ec_netdev_t *)phydev->user_data;
+    return enet_read_phy(ENET, phy_addr, regnum);
+}
+
+void ec_netdev_low_level_link_up(ec_netdev_t *netdev, struct chry_phy_status *status)
+{
+    enet_line_speed_t line_speed = enet_line_speed_10mbps;
+
+    switch (status->speed) {
+        case 10:
+            line_speed = enet_line_speed_10mbps;
+            break;
+        case 100:
+            line_speed = enet_line_speed_100mbps;
+            break;
+        case 1000:
+            line_speed = enet_line_speed_1000mbps;
+            break;
+
+        default:
+            break;
+    }
+    if (status->link) {
+        enet_set_line_speed(ENET, line_speed);
+        enet_set_duplex_mode(ENET, status->duplex);
+    } else {
+    }
+}
+#else
+void ec_netdev_low_level_poll_link_state(ec_netdev_t *netdev)
+{
+    static enet_phy_status_t last_status;
+    enet_phy_status_t status = { 0 };
+
+    enet_line_speed_t line_speed[] = { enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps };
+
+#if defined(RGMII) && RGMII
+#if defined(__USE_DP83867) && __USE_DP83867
+    dp83867_get_phy_status(ENET, &status);
+#else
+    rtl8211_get_phy_status(ENET, &status);
+#endif
+#else
+#if defined(__USE_DP83848) && __USE_DP83848
+    dp83848_get_phy_status(ENET, &status);
+#else
+    rtl8201_get_phy_status(ENET, &status);
+#endif
+#endif
+
+    if (memcmp(&last_status, &status, sizeof(enet_phy_status_t)) != 0) {
+        ec_memcpy(&last_status, &status, sizeof(enet_phy_status_t));
+        if (status.enet_phy_link) {
+            enet_set_line_speed(ENET, line_speed[status.enet_phy_speed]);
+            enet_set_duplex_mode(ENET, status.enet_phy_duplex);
+            netdev->link_state = true;
+        } else {
+            netdev->link_state = false;
+        }
+    }
+}
+#endif
+
+EC_FAST_CODE_SECTION uint8_t *ec_netdev_low_level_get_txbuf(ec_netdev_t *netdev)
+{
+    return (uint8_t *)tx_buff[netdev->tx_frame_index];
+}
+
+EC_FAST_CODE_SECTION int ec_netdev_low_level_output(ec_netdev_t *netdev, uint32_t size)
+{
+    __IO enet_tx_desc_t *dma_tx_desc;
+
+    dma_tx_desc = desc.tx_desc_list_cur;
+    if (dma_tx_desc->tdes0_bm.own != 0) {
+        return -1;
+    }
+
+    netdev->tx_frame_index++;
+    netdev->tx_frame_index %= ENET_TX_BUFF_COUNT;
+
+    /* Prepare transmit descriptors to give to DMA*/
+    enet_prepare_transmission_descriptors(ENET, &desc.tx_desc_list_cur, size + 4, desc.tx_buff_cfg.size);
+
+    return 0;
+}
+
+EC_FAST_CODE_SECTION int ec_netdev_low_level_input(ec_netdev_t *netdev)
+{
+    uint32_t len;
+    uint8_t *buffer;
+    enet_frame_t frame = { 0, 0, 0 };
+    enet_rx_desc_t *dma_rx_desc;
+    uint32_t i = 0;
+    int ret = 0;
+
+    /* Check and get a received frame */
+    if (enet_check_received_frame(&desc.rx_desc_list_cur, &desc.rx_frame_info) == 1) {
+        frame = enet_get_received_frame(&desc.rx_desc_list_cur, &desc.rx_frame_info);
+    }
+
+    /* Obtain the size of the packet and put it into the "len" variable. */
+    len = frame.length;
+    buffer = (uint8_t *)sys_address_to_core_local_mem(BOARD_RUNNING_CORE, (uint32_t)frame.buffer);
+
+    if (len > 0) {
+        ec_netdev_receive(netdev, buffer, len);
+        /* Release descriptors to DMA */
+        dma_rx_desc = frame.rx_desc;
+
+        /* Set Own bit in Rx descriptors: gives the buffers back to DMA */
+        for (i = 0; i < desc.rx_frame_info.seg_count; i++) {
+            dma_rx_desc->rdes0_bm.own = 1;
+            dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc);
+        }
+
+        /* Clear Segment_Count */
+        desc.rx_frame_info.seg_count = 0;
+    } else {
+        ret = -1;
+    }
+
+    /* Resume Rx Process */
+    enet_rx_resume(ENET);
+    return ret;
+}
+
+#if defined(__ENABLE_ENET_RECEIVE_INTERRUPT) && __ENABLE_ENET_RECEIVE_INTERRUPT
+void isr_enet(ENET_Type *ptr)
+{
+    uint32_t status;
+    uint32_t rxgbfrmis;
+    uint32_t intr_status;
+
+    status = ptr->DMA_STATUS;
+    rxgbfrmis = ptr->MMC_INTR_RX;
+    intr_status = ptr->INTR_STATUS;
+
+    if (ENET_DMA_STATUS_GLPII_GET(status)) {
+        /* read LPI_CSR to clear interrupt status */
+        ptr->LPI_CSR;
+    }
+
+    if (ENET_INTR_STATUS_RGSMIIIS_GET(intr_status)) {
+        /* read XMII_CSR to clear interrupt status */
+        ptr->XMII_CSR;
+    }
+
+    if (ENET_DMA_STATUS_RI_GET(status)) {
+        ptr->DMA_STATUS |= ENET_DMA_STATUS_RI_MASK;
+        while (ec_netdev_low_level_input(&g_netdev) == 0) {
+        }
+    }
+
+    if (ENET_MMC_INTR_RX_RXCTRLFIS_GET(rxgbfrmis)) {
+        ptr->RXFRAMECOUNT_GB;
+    }
+}
+
+#ifdef HPM_ENET0_BASE
+void isr_enet0(void)
+{
+    isr_enet(ENET);
+}
+SDK_DECLARE_EXT_ISR_M(IRQn_ENET0, isr_enet0)
+#endif
+
+#ifdef HPM_ENET1_BASE
+void isr_enet1(void)
+{
+    isr_enet(ENET);
+}
+SDK_DECLARE_EXT_ISR_M(IRQn_ENET1, isr_enet1)
+#endif
+
+#endif
+
+#include "hpm_gptmr_drv.h"
+
+#define EC_HTIMER          BOARD_GPTMR
+#define EC_HTIMER_CH       BOARD_GPTMR_CHANNEL
+#define EC_HTIMER_IRQ      BOARD_GPTMR_IRQ
+#define EC_HTIMER_CLK_NAME BOARD_GPTMR_CLK_NAME
+
+ec_htimer_cb g_ec_htimer_cb = NULL;
+void *g_ec_htimer_arg = NULL;
+
+void ec_htimer_isr(void)
+{
+    if (gptmr_check_status(EC_HTIMER, GPTMR_CH_RLD_STAT_MASK(EC_HTIMER_CH))) {
+        gptmr_clear_status(EC_HTIMER, GPTMR_CH_RLD_STAT_MASK(EC_HTIMER_CH));
+        g_ec_htimer_cb(g_ec_htimer_arg);
+    }
+}
+SDK_DECLARE_EXT_ISR_M(EC_HTIMER_IRQ, ec_htimer_isr);
+
+void ec_htimer_start(uint32_t us, ec_htimer_cb cb, void *arg)
+{
+    uint32_t gptmr_freq;
+    gptmr_channel_config_t config;
+
+    g_ec_htimer_cb = cb;
+    g_ec_htimer_arg = arg;
+
+    gptmr_channel_get_default_config(EC_HTIMER, &config);
+
+    clock_add_to_group(EC_HTIMER_CLK_NAME, 0);
+    gptmr_freq = clock_get_frequency(EC_HTIMER_CLK_NAME);
+
+    config.reload = gptmr_freq / 1000000 * us;
+    gptmr_stop_counter(EC_HTIMER, EC_HTIMER_CH);
+    gptmr_channel_config(EC_HTIMER, EC_HTIMER_CH, &config, false);
+    gptmr_enable_irq(EC_HTIMER, GPTMR_CH_RLD_IRQ_MASK(EC_HTIMER_CH));
+    intc_m_enable_irq_with_priority(EC_HTIMER_IRQ, 10);
+    gptmr_start_counter(EC_HTIMER, EC_HTIMER_CH);
+}
+
+void ec_htimer_stop(void)
+{
+    gptmr_stop_counter(EC_HTIMER, EC_HTIMER_CH);
+    gptmr_disable_irq(EC_HTIMER, GPTMR_CH_RLD_IRQ_MASK(EC_HTIMER_CH));
+    intc_m_disable_irq(EC_HTIMER_IRQ);
+}
+
+uint32_t ec_get_cpu_frequency(void)
+{
+    return clock_get_frequency(clock_cpu0);
+}
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_renesas.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_renesas.c
new file mode 100644
index 00000000..d5d4945a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_renesas.c
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ * Copyright (c) 2025, yans
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <hal_data.h>
+#include "ec_master.h"
+
+ec_netdev_t g_netdev;
+
+#if defined(BSP_MCU_GROUP_RZT2M) || defined(BSP_MCU_GROUP_RZN2L)
+#define ETHER_BUFFER_PLACE_IN_SECTION BSP_PLACE_IN_SECTION(".noncache_buffer.eth")
+#else
+#define ETHER_BUFFER_PLACE_IN_SECTION
+#endif
+
+__attribute__((__aligned__(32))) uint8_t tx_buffer[CONFIG_EC_MAX_ENET_TXBUF_COUNT][1536] ETHER_BUFFER_PLACE_IN_SECTION;
+
+extern uint32_t SystemCoreClock;
+
+#define PING_PORT_COUNT (3) ///< Count of port
+
+static uint8_t g_link_change = 0; ///< Link change (bit0:port0, bit1:port1, bit2:port2)
+static uint8_t g_link_status = 0; ///< Link status (bit0:port0, bit1:port1, bit2:port2)
+static uint8_t previous_link_status = 0;
+
+static int phy_rtl8211f_led_fixup(ether_phy_instance_ctrl_t *phydev)
+{
+#define RTL_8211F_PAGE_SELECT 0x1F
+#define RTL_8211F_EEELCR_ADDR 0x11
+#define RTL_8211F_LED_PAGE    0xD04
+#define RTL_8211F_LCR_ADDR    0x10
+
+    uint32_t val1, val2 = 0;
+
+    /* switch to led page */
+    R_ETHER_PHY_Write(phydev, RTL_8211F_PAGE_SELECT, RTL_8211F_LED_PAGE);
+
+    /* set led1(green) Link 10/100/1000M, and set led2(yellow) Link 10/100/1000M+Active */
+    R_ETHER_PHY_Read(phydev, RTL_8211F_LCR_ADDR, &val1);
+    val1 |= (1 << 5);
+    val1 |= (1 << 8);
+    val1 &= (~(1 << 9));
+    val1 |= (1 << 10);
+    val1 |= (1 << 11);
+    R_ETHER_PHY_Write(phydev, RTL_8211F_LCR_ADDR, val1);
+
+    /* set led1(green) EEE LED function disabled so it can keep on when linked */
+    R_ETHER_PHY_Read(phydev, RTL_8211F_EEELCR_ADDR, &val2);
+    val2 &= (~(1 << 2));
+    R_ETHER_PHY_Write(phydev, RTL_8211F_EEELCR_ADDR, val2);
+
+    /* switch back to page0 */
+    R_ETHER_PHY_Write(phydev, RTL_8211F_PAGE_SELECT, 0xa42);
+
+    return 0;
+}
+
+void ether_phy_targets_initialize_rtl8211_rgmii(ether_phy_instance_ctrl_t *p_instance_ctrl)
+{
+    ec_osal_msleep(100);
+    phy_rtl8211f_led_fixup(p_instance_ctrl);
+}
+
+ec_netdev_t *ec_netdev_low_level_init(uint8_t netdev_index)
+{
+    fsp_err_t res;
+
+    EC_ASSERT_MSG(g_ether0_cfg.zerocopy == ETHER_ZEROCOPY_ENABLE, "zerocopy must be enabled");
+
+    res = R_GMAC_Open(&g_ether0_ctrl, &g_ether0_cfg);
+    if (res != FSP_SUCCESS)
+        EC_LOG_ERR("R_ETHER_Open failed!, res = %d", res);
+
+    ec_memcpy(g_netdev.mac_addr, g_ether0_cfg.p_mac_address, 6);
+
+    for (uint32_t i = 0; i < g_ether0_cfg.num_tx_descriptors; i++) {
+        for (uint8_t j = 0; j < 6; j++) { // dst MAC
+            EC_WRITE_U8(&tx_buffer[i][j], 0xFF);
+        }
+        for (uint8_t j = 0; j < 6; j++) { // src MAC
+            EC_WRITE_U8(&tx_buffer[i][6 + j], g_ether0_cfg.p_mac_address[j]);
+        }
+        EC_WRITE_U16(&tx_buffer[i][12], ec_htons(0x88a4));
+    }
+
+    return &g_netdev;
+}
+
+void ec_netdev_low_level_poll_link_state(ec_netdev_t *netdev)
+{
+    fsp_err_t res;
+    gmac_link_status_t port_status;
+    uint8_t port = 0;
+    uint8_t port_bit = 0;
+
+    res = R_GMAC_LinkProcess(&g_ether0_ctrl);
+    if (res != FSP_SUCCESS)
+        EC_LOG_ERR("R_ETHER_LinkProcess failed!, res = %d", res);
+
+    if (0 == g_ether0.p_cfg->p_callback) {
+        for (port = 0; port < PING_PORT_COUNT; port++) {
+            res = R_GMAC_GetLinkStatus(&g_ether0_ctrl, port, &port_status);
+            if (FSP_SUCCESS != res) {
+                /* An error has occurred */
+                EC_LOG_ERR("R_GMAC_GetLinkStatus failed!, res = %d", res);
+                break;
+            }
+
+            if (GMAC_LINK_STATUS_DOWN != port_status) {
+                /* Set link up */
+                g_link_status |= (uint8_t)(1U << port);
+            }
+        }
+        if (FSP_SUCCESS == res) {
+            /* Set changed link status */
+            g_link_change = previous_link_status ^ g_link_status;
+        }
+    }
+
+    previous_link_status = g_link_status;
+
+    if (FSP_SUCCESS == res) {
+        for (port = 0; port < PING_PORT_COUNT; port++) {
+            port_bit = (uint8_t)(1U << port);
+
+            if (g_link_change & port_bit) {
+                /* Link status changed */
+                g_link_change &= (uint8_t)(~port_bit); // change bit clear
+
+                if (g_link_status & port_bit) {
+                    /* Changed to Link-up */
+                    netdev->link_state = true;
+                } else {
+                    /* Changed to Link-down */
+                    netdev->link_state = false;
+                }
+            }
+        }
+    }
+}
+
+EC_FAST_CODE_SECTION uint8_t *ec_netdev_low_level_get_txbuf(ec_netdev_t *netdev)
+{
+    return (uint8_t *)tx_buffer[netdev->tx_frame_index];
+}
+
+EC_FAST_CODE_SECTION int ec_netdev_low_level_output(ec_netdev_t *netdev, uint32_t size)
+{
+    fsp_err_t res;
+
+    res = R_GMAC_Write(&g_ether0_ctrl, tx_buffer[netdev->tx_frame_index], size);
+    if (res != FSP_SUCCESS) {
+        return -1;
+    }
+
+    netdev->tx_frame_index++;
+    netdev->tx_frame_index %= g_ether0_cfg.num_tx_descriptors;
+
+    return 0;
+}
+
+EC_FAST_CODE_SECTION int ec_netdev_low_level_input(ec_netdev_t *netdev)
+{
+    fsp_err_t res;
+    uint8_t *buffer;
+    uint32_t len = 0;
+
+    res = R_GMAC_Read(&g_ether0_ctrl, (void *)&buffer, &len);
+    if (res != FSP_SUCCESS) {
+        return -1;
+    }
+
+    ec_netdev_receive(netdev, buffer, len);
+
+    R_GMAC_BufferRelease(&g_ether0_ctrl);
+
+    return 0;
+}
+
+static ec_htimer_cb g_ec_htimer_cb = NULL;
+static void *g_ec_htimer_arg = NULL;
+
+void timer0_esc_callback(timer_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (TIMER_EVENT_CYCLE_END == p_args->event) {
+        if (g_ec_htimer_cb) {
+            g_ec_htimer_cb(g_ec_htimer_arg);
+        }
+    }
+    rt_interrupt_leave();
+}
+
+void ec_htimer_start(uint32_t us, ec_htimer_cb cb, void *arg)
+{
+    fsp_err_t fsp_err = FSP_SUCCESS;
+    uint32_t count = us * (SystemCoreClock / 1000000); // 400MHz, 1us = 400 ticks
+
+    g_ec_htimer_cb = cb;
+    g_ec_htimer_arg = arg;
+
+    fsp_err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
+    fsp_err |= R_GPT_CounterSet(&g_timer0_ctrl, 0);
+    fsp_err |= R_GPT_PeriodSet(&g_timer0_ctrl, count);
+    fsp_err |= R_GPT_Start(&g_timer0_ctrl);
+
+    if (fsp_err != FSP_SUCCESS) {
+        EC_LOG_ERR("R_GPT_Open failed!, res = %d", fsp_err);
+    }
+}
+
+void ec_htimer_stop(void)
+{
+    R_GPT_Stop(&g_timer0_ctrl);
+}
+
+volatile uint64_t mtu3_overflow_count = 0;
+
+void g_mtu3_callback(timer_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (TIMER_EVENT_CYCLE_END == p_args->event) {
+        mtu3_overflow_count++;
+    }
+    rt_interrupt_leave();
+}
+
+uint64_t gpt_get_count(void)
+{
+    mtu3_status_t status;
+    uint64_t high;
+    uint64_t low;
+
+    do {
+        high = mtu3_overflow_count;
+        R_MTU3_StatusGet(&g_mtu3_ctrl, &status);
+        low = status.counter;
+    } while (high != mtu3_overflow_count);
+
+    return (high << 16) | low;
+}
+
+void ec_timestamp_init(void)
+{
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    fsp_err = R_MTU3_Open(&g_mtu3_ctrl, &g_mtu3_cfg);
+    fsp_err |= R_MTU3_Start(&g_mtu3_ctrl);
+
+    if (fsp_err != FSP_SUCCESS) {
+        EC_LOG_ERR("R_GPT_Open failed!, res = %d", fsp_err);
+    }
+}
+
+EC_FAST_CODE_SECTION uint64_t ec_timestamp_get_time_ns(void)
+{
+    return (uint64_t)(gpt_get_count() * 5ULL);
+}
+
+EC_FAST_CODE_SECTION uint64_t ec_timestamp_get_time_us(void)
+{
+    return ec_timestamp_get_time_ns() / 1000ULL;
+}
+
+void user_ether0_callback(ether_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    switch (p_args->event) {
+        case ETHER_EVENT_LINK_ON:                          ///< Link up detection event/
+            g_link_status |= (uint8_t)p_args->status_link; ///< status up
+            g_link_change |= (uint8_t)p_args->status_link; ///< change bit set
+            break;
+
+        case ETHER_EVENT_LINK_OFF:                            ///< Link down detection event
+            g_link_status &= (uint8_t)(~p_args->status_link); ///< status down
+            g_link_change |= (uint8_t)p_args->status_link;    ///< change bit set
+            break;
+
+        case ETHER_EVENT_WAKEON_LAN: ///< Magic packet detection event
+        /* If EDMAC FR (Frame Receive Event) or FDE (Receive Descriptor Empty Event)
+         * interrupt occurs, send rx mailbox. */
+        case ETHER_EVENT_SBD_INTERRUPT: ///< BSD Interrupt event
+        {
+            while (ec_netdev_low_level_input(&g_netdev) == 0) {
+            }
+            break;
+        }
+        case ETHER_EVENT_PMT_INTERRUPT: ///< PMT Interrupt event
+            break;
+
+        default:
+            break;
+    }
+
+    rt_interrupt_leave();
+}
+
+uint32_t ec_get_cpu_frequency(void)
+{
+    return SystemCoreClock;
+}
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ENI.xml b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ENI.xml
new file mode 100644
index 00000000..b85a399e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ENI.xml
@@ -0,0 +1,1094 @@
+<?xml version="1.0"?>
+<EtherCATConfig xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="EtherCATConfig.xsd" Version="1.3">
+	<Config>
+		<Master>
+			<Info>
+				<Name><![CDATA[Device 2 (EtherCAT)]]></Name>
+				<Destination>010105010000</Destination>
+				<Source>2c58b9dca252</Source>
+				<EtherType>a488</EtherType>
+			</Info>
+			<MailboxStates>
+				<StartAddr>150994944</StartAddr>
+				<Count>1</Count>
+			</MailboxStates>
+			<InitCmds>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[read slave count]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>7</Cmd>
+					<Adp>0</Adp>
+					<Ado>304</Ado>
+					<Data>0000</Data>
+					<Retries>0</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[read slave count]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>7</Cmd>
+					<Adp>0</Adp>
+					<Ado>304</Ado>
+					<Data>0000</Data>
+					<Retries>0</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[enable ECAT IRQ]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>512</Ado>
+					<Data>0400</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[clear configured addresses]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>16</Ado>
+					<Data>0000</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[clear crc register]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>768</Ado>
+					<Data>0000000000000000</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>PI</Transition>
+					<Transition>BI</Transition>
+					<Transition>SI</Transition>
+					<Transition>OI</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[clear fmmu]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>1536</Ado>
+					<DataLength>256</DataLength>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[clear sm]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>2048</Ado>
+					<DataLength>256</DataLength>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[clear dc system time]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>2320</Ado>
+					<DataLength>32</DataLength>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[clear dc cycle cfg]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>2433</Ado>
+					<Data>00</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[reset dc speed]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>2352</Ado>
+					<Data>0010</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[configure dc filter]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>2356</Ado>
+					<Data>000c</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<BeforeSlave>true</BeforeSlave>
+					<Comment><![CDATA[en/disable second physical address]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>8</Cmd>
+					<Adp>0</Adp>
+					<Ado>259</Ado>
+					<Data>00</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+			</InitCmds>
+		</Master>
+		<Slave>
+			<Info>
+				<Name><![CDATA[Drive 1 (ECAT_CIA402)]]></Name>
+				<PhysAddr>1001</PhysAddr>
+				<AutoIncAddr>0</AutoIncAddr>
+				<Identification Value="0">
+					<Ado>#x0134</Ado>
+				</Identification>
+				<Physics>YYY</Physics>
+				<VendorId>4739149</VendorId>
+				<ProductCode>3</ProductCode>
+				<RevisionNo>1</RevisionNo>
+				<SerialNo>0</SerialNo>
+			</Info>
+			<ProcessData>
+				<Send>
+					<BitStart>312</BitStart>
+					<BitLength>64</BitLength>
+				</Send>
+				<Recv>
+					<BitStart>312</BitStart>
+					<BitLength>64</BitLength>
+				</Recv>
+				<Sm2>
+					<Type>Outputs</Type>
+					<StartAddress>4352</StartAddress>
+					<ControlByte>100</ControlByte>
+					<Enable>1</Enable>
+					<Pdo>5634</Pdo>
+				</Sm2>
+				<Sm3>
+					<Type>Inputs</Type>
+					<StartAddress>5120</StartAddress>
+					<ControlByte>32</ControlByte>
+					<Enable>1</Enable>
+					<Pdo>6658</Pdo>
+				</Sm3>
+				<TxPdo Fixed="true" Sm="3">
+					<Index DependOnSlot="true">#x1a02</Index>
+					<Name>Inputs</Name>
+					<Entry>
+						<Index DependOnSlot="true">#x6041</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Name>Status Word</Name>
+						<Comment>object 0x6041:0</Comment>
+						<DataType>UINT</DataType>
+					</Entry>
+					<Entry>
+						<Index DependOnSlot="true">#x6064</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>32</BitLen>
+						<Name>ActualPosition</Name>
+						<Comment>object 0x6064:0</Comment>
+						<DataType>DINT</DataType>
+					</Entry>
+					<Entry>
+						<Index>#x0</Index>
+						<BitLen>16</BitLen>
+					</Entry>
+				</TxPdo>
+				<RxPdo Fixed="true" Sm="2">
+					<Index DependOnSlot="true">#x1602</Index>
+					<Name>Outputs</Name>
+					<Entry>
+						<Index DependOnSlot="true">#x6040</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Name>Control Word</Name>
+						<Comment>object 0x6040:0</Comment>
+						<DataType>UINT</DataType>
+					</Entry>
+					<Entry>
+						<Index DependOnSlot="true">#x60ff</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>32</BitLen>
+						<Name>TargetVelocity</Name>
+						<Comment>object 0x60FF:0</Comment>
+						<DataType>DINT</DataType>
+					</Entry>
+					<Entry>
+						<Index>#x0</Index>
+						<BitLen>16</BitLen>
+					</Entry>
+				</RxPdo>
+			</ProcessData>
+			<Mailbox DataLinkLayer="true">
+				<Send>
+					<Start>4096</Start>
+					<Length>128</Length>
+				</Send>
+				<Recv>
+					<Start>4224</Start>
+					<Length>128</Length>
+					<StatusBitAddr>0</StatusBitAddr>
+				</Recv>
+				<Protocol>CoE</Protocol>
+				<CoE>
+					<InitCmds>
+						<InitCmd Fixed="true" CompleteAccess="true">
+							<Transition>PS</Transition>
+							<Comment><![CDATA[download pdo 0x1C12 index]]></Comment>
+							<Timeout>0</Timeout>
+							<Ccs>1</Ccs>
+							<Index>7186</Index>
+							<SubIndex>0</SubIndex>
+							<Data>01000216</Data>
+						</InitCmd>
+						<InitCmd Fixed="true" CompleteAccess="true">
+							<Transition>PS</Transition>
+							<Comment><![CDATA[download pdo 0x1C13 index]]></Comment>
+							<Timeout>0</Timeout>
+							<Ccs>1</Ccs>
+							<Index>7187</Index>
+							<SubIndex>0</SubIndex>
+							<Data>0100021a</Data>
+						</InitCmd>
+						<InitCmd ModuleHandle="0">
+							<Transition>SO</Transition>
+							<Timeout>0</Timeout>
+							<Ccs>1</Ccs>
+							<Index>24672</Index>
+							<SubIndex>0</SubIndex>
+							<Data>09</Data>
+						</InitCmd>
+					</InitCmds>
+					<Profile>
+						<ChannelInfo>
+							<ProfileNo>402</ProfileNo>
+							<AddInfo>2</AddInfo>
+						</ChannelInfo>
+						<ChannelInfo>
+							<ProfileNo>402</ProfileNo>
+							<AddInfo>0</AddInfo>
+						</ChannelInfo>
+					</Profile>
+				</CoE>
+			</Mailbox>
+			<InitCmds>
+				<InitCmd>
+					<Transition>PI</Transition>
+					<Transition>BI</Transition>
+					<Transition>SI</Transition>
+					<Transition>OI</Transition>
+					<Comment><![CDATA[set device state to INIT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>288</Ado>
+					<Data>1100</Data>
+					<Retries>3</Retries>
+					<Timeout>5000</Timeout>
+				</InitCmd>
+				<InitCmd>
+					<Transition>PI</Transition>
+					<Transition>SI</Transition>
+					<Transition>OI</Transition>
+					<Comment><![CDATA[check device state for INIT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>1</Cmd>
+					<Adp>0</Adp>
+					<Ado>304</Ado>
+					<Data>0000</Data>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>0100</Data>
+						<DataMask>0f00</DataMask>
+						<Timeout>5000</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>BI</Transition>
+					<Comment><![CDATA[check device state for INIT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>1</Cmd>
+					<Adp>0</Adp>
+					<Ado>304</Ado>
+					<Data>0000</Data>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>0100</Data>
+						<DataMask>0f00</DataMask>
+						<Timeout>10000</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[set device state to INIT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>288</Ado>
+					<Data>1100</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Timeout>2000</Timeout>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[check device state for INIT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>1</Cmd>
+					<Adp>0</Adp>
+					<Ado>304</Ado>
+					<Data>0000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>0100</Data>
+						<DataMask>0f00</DataMask>
+						<Timeout>2000</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Comment><![CDATA[assign EEPROM to ECAT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>1280</Ado>
+					<Data>00</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Comment><![CDATA[check vendor id]]></Comment>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>1282</Ado>
+					<Data>000108000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Comment><![CDATA[check vendor id]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>1</Cmd>
+					<Adp>0</Adp>
+					<Ado>1288</Ado>
+					<Data>00000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>4d504800</Data>
+						<Timeout>100</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Comment><![CDATA[check product code]]></Comment>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>1282</Ado>
+					<Data>00010a000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Comment><![CDATA[check product code]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>1</Cmd>
+					<Adp>0</Adp>
+					<Ado>1288</Ado>
+					<Data>00000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>03000000</Data>
+						<Timeout>100</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[set physical address]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>16</Ado>
+					<Data>e903</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>IB</Transition>
+					<Transition>PI</Transition>
+					<Transition>SI</Transition>
+					<Transition>OI</Transition>
+					<Comment><![CDATA[clear sm 0/1 (mailbox out/in)]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>2048</Ado>
+					<Data>00000000000000000000000000000000</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>BI</Transition>
+					<Comment><![CDATA[clear sm 0/1 (mailbox out/in)]]></Comment>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>2048</Ado>
+					<Data>00000000000000000000000000000000</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[set sm 0 (mailbox out)]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>2048</Ado>
+					<Data>0010800026000100</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[set sm 1 (mailbox in)]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>2056</Ado>
+					<Data>8010800022000100</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>SP</Transition>
+					<Transition>OP</Transition>
+					<Comment><![CDATA[set device state to PREOP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>288</Ado>
+					<Data>1200</Data>
+					<Retries>300</Retries>
+					<Timeout>200</Timeout>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>SP</Transition>
+					<Transition>SI</Transition>
+					<Transition>OP</Transition>
+					<Transition>OI</Transition>
+					<Comment><![CDATA[clear sms]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>2064</Ado>
+					<Data>00000000000000000000000000000000</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>PS</Transition>
+					<Comment><![CDATA[set sm 2 (outputs)]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>2064</Ado>
+					<Data>0011080064000100</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>PS</Transition>
+					<Comment><![CDATA[set sm 3 (inputs)]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>2072</Ado>
+					<Data>0014080020000100</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>PS</Transition>
+					<Comment><![CDATA[set fmmu 0 (outputs)]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>1536</Ado>
+					<Data>00000001080000070011000201000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>PS</Transition>
+					<Comment><![CDATA[set fmmu 1 (inputs)]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>1552</Ado>
+					<Data>00000001080000070014000101000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[set fmmu 2 (mailbox state)]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>1568</Ado>
+					<Data>00000009010000000d08000101000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>OS</Transition>
+					<Comment><![CDATA[set device state to SAFEOP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>288</Ado>
+					<Data>0400</Data>
+					<Retries>3</Retries>
+					<Timeout>200</Timeout>
+				</InitCmd>
+				<InitCmd>
+					<Transition>SP</Transition>
+					<Transition>SI</Transition>
+					<Transition>OP</Transition>
+					<Transition>OI</Transition>
+					<Comment><![CDATA[clear fmmu 0]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>1536</Ado>
+					<Data>00000000000000000000000000000000</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>SP</Transition>
+					<Transition>SI</Transition>
+					<Transition>OP</Transition>
+					<Transition>OI</Transition>
+					<Comment><![CDATA[clear fmmu 1]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>1552</Ado>
+					<Data>00000000000000000000000000000000</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>PI</Transition>
+					<Transition>BI</Transition>
+					<Transition>SI</Transition>
+					<Transition>OI</Transition>
+					<Comment><![CDATA[clear fmmu 2]]></Comment>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>1568</Ado>
+					<Data>00000000000000000000000000000000</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>SP</Transition>
+					<Transition>OP</Transition>
+					<Comment><![CDATA[check device state for PREOP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>4</Cmd>
+					<Adp>1001</Adp>
+					<Ado>304</Ado>
+					<Data>000000000000</Data>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>020000000000</Data>
+						<DataMask>0f0000000000</DataMask>
+						<Timeout>5000</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[assign EEPROM to PDI]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>1280</Ado>
+					<Data>01</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>II</Transition>
+					<Comment><![CDATA[assign EEPROM back to ECAT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>1280</Ado>
+					<Data>00</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Comment><![CDATA[set device state to PREOP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>288</Ado>
+					<Data>1200</Data>
+					<Cnt>1</Cnt>
+					<Retries>300</Retries>
+					<Timeout>2000</Timeout>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Comment><![CDATA[check device state for PREOP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>4</Cmd>
+					<Adp>1001</Adp>
+					<Ado>304</Ado>
+					<Data>000000000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>020000000000</Data>
+						<DataMask>1f0000000000</DataMask>
+						<Timeout>2000</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IP</Transition>
+					<Transition>BI</Transition>
+					<Comment><![CDATA[assign EEPROM back to ECAT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>2</Cmd>
+					<Adp>0</Adp>
+					<Ado>1280</Ado>
+					<Data>00</Data>
+					<Retries>3</Retries>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[set device state to BOOT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>288</Ado>
+					<Data>1300</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Timeout>2000</Timeout>
+				</InitCmd>
+				<InitCmd>
+					<Transition>IB</Transition>
+					<Comment><![CDATA[check device state for BOOT]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>4</Cmd>
+					<Adp>1001</Adp>
+					<Ado>304</Ado>
+					<Data>000000000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>030000000000</Data>
+						<DataMask>1f0000000000</DataMask>
+						<Timeout>2000</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>PS</Transition>
+					<Comment><![CDATA[set device state to SAFEOP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>288</Ado>
+					<Data>0400</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Timeout>9000</Timeout>
+				</InitCmd>
+				<InitCmd>
+					<Transition>PS</Transition>
+					<Comment><![CDATA[check device state for SAFEOP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>4</Cmd>
+					<Adp>1001</Adp>
+					<Ado>304</Ado>
+					<Data>000000000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>040000000000</Data>
+						<DataMask>1f0000000000</DataMask>
+						<Timeout>9000</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>OS</Transition>
+					<Comment><![CDATA[check device state for SAFEOP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>4</Cmd>
+					<Adp>1001</Adp>
+					<Ado>304</Ado>
+					<Data>000000000000</Data>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>040000000000</Data>
+						<DataMask>0f0000000000</DataMask>
+						<Timeout>200</Timeout>
+					</Validate>
+				</InitCmd>
+				<InitCmd>
+					<Transition>SO</Transition>
+					<Comment><![CDATA[set device state to OP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>5</Cmd>
+					<Adp>1001</Adp>
+					<Ado>288</Ado>
+					<Data>0800</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Timeout>9000</Timeout>
+				</InitCmd>
+				<InitCmd>
+					<Transition>SO</Transition>
+					<Comment><![CDATA[check device state for OP]]></Comment>
+					<Requires>cycle</Requires>
+					<Cmd>4</Cmd>
+					<Adp>1001</Adp>
+					<Ado>304</Ado>
+					<Data>000000000000</Data>
+					<Cnt>1</Cnt>
+					<Retries>3</Retries>
+					<Validate>
+						<Data>080000000000</Data>
+						<DataMask>1f0000000000</DataMask>
+						<Timeout>9000</Timeout>
+					</Validate>
+				</InitCmd>
+			</InitCmds>
+		</Slave>
+		<Cyclic>
+			<Comment><![CDATA[synchronized with task 'NC-Task 1 SAF']]></Comment>
+			<CycleTime>2000</CycleTime>
+			<Priority>4</Priority>
+			<TaskId>1</TaskId>
+			<Frame>
+				<Cmd>
+					<State>PREOP</State>
+					<State>SAFEOP</State>
+					<State>OP</State>
+					<Comment><![CDATA[cyclic cmd]]></Comment>
+					<Cmd>10</Cmd>
+					<Addr>150994944</Addr>
+					<DataLength>1</DataLength>
+					<InputOffs>16</InputOffs>
+					<OutputOffs>16</OutputOffs>
+				</Cmd>
+				<Cmd>
+					<State>SAFEOP</State>
+					<State>OP</State>
+					<Comment><![CDATA[cyclic cmd]]></Comment>
+					<Cmd>12</Cmd>
+					<Addr>16777216</Addr>
+					<DataLength>8</DataLength>
+					<Cnt>3</Cnt>
+					<InputOffs>29</InputOffs>
+					<OutputOffs>29</OutputOffs>
+				</Cmd>
+				<Cmd>
+					<State>PREOP</State>
+					<State>SAFEOP</State>
+					<State>OP</State>
+					<Comment><![CDATA[cyclic cmd]]></Comment>
+					<Cmd>7</Cmd>
+					<Adp>0</Adp>
+					<Ado>304</Ado>
+					<DataLength>2</DataLength>
+					<Cnt>1</Cnt>
+					<InputOffs>49</InputOffs>
+					<OutputOffs>49</OutputOffs>
+				</Cmd>
+			</Frame>
+		</Cyclic>
+		<ProcessImage>
+			<Inputs>
+				<ByteSize>1536</ByteSize>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).Module 1 (csv -  axis).Inputs.Status Word</Name>
+					<Comment><![CDATA[object 0x6041:0]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>312</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).Module 1 (csv -  axis).Inputs.ActualPosition</Name>
+					<Comment><![CDATA[object 0x6064:0]]></Comment>
+					<DataType>DINT</DataType>
+					<BitSize>32</BitSize>
+					<BitOffs>328</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Inputs.Frm0State</Name>
+					<Comment><![CDATA[0x0001 = 1. EtherCAT command not sent (NOP requested)
+0x0002 = 2. EtherCAT command not sent (NOP requested)
+0x0004 = 3. EtherCAT command not sent (NOP requested)
+...
+0x4000 = 15. EtherCAT command not sent (NOP requested)
+0x8000 = complete frame not sent
+]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12160</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Inputs.Frm0WcState</Name>
+					<Comment><![CDATA[0x0001 = wrong working counter of 1. EtherCAT command received
+0x0002 = wrong working counter of 2. EtherCAT command received
+0x0004 = wrong working counter of 3. EtherCAT command received
+...
+0x4000 = wrong working counter of 15. EtherCAT command received
+0x8000 = complete frame missing
+]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12176</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).WcState.WcState</Name>
+					<Comment><![CDATA[0 = Data valid
+1 = Data invalid
+]]></Comment>
+					<DataType>BIT</DataType>
+					<BitSize>1</BitSize>
+					<BitOffs>12177</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Inputs.Frm0InputToggle</Name>
+					<Comment><![CDATA[0x0001 = Toggle Bit: 1. EtherCAT command received new inputs
+0x0002 = Toggle Bit: 2. EtherCAT command received new inputs
+0x0004 = Toggle Bit: 3. EtherCAT command received new inputs
+...
+0x4000 = Toggle Bit: 15. EtherCAT command received new inputs
+0x8000 = Old frame - not from the actual cycle - received
+]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12192</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).WcState.InputToggle</Name>
+					<DataType>BIT</DataType>
+					<BitSize>1</BitSize>
+					<BitOffs>12193</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>SyncUnits.&lt;default&gt;.NC-Task 1 SAF.WcState.WcState</Name>
+					<Comment><![CDATA[0 = Data valid
+1 = Data invalid
+]]></Comment>
+					<DataType>BIT</DataType>
+					<BitSize>1</BitSize>
+					<BitOffs>12208</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Inputs.SlaveCount</Name>
+					<Comment><![CDATA[Actual count of EtherCAT slaves received]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12240</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Inputs.DevState</Name>
+					<Comment><![CDATA[0x0001 = Link error
+0x0002 = I/O locked after link error (I/O reset required)
+0x0004 = Link error (redundancy adapter)
+0x0008 = Missing one frame (redundancy mode)
+0x0010 = Out of send resources (I/O reset required)
+0x0020 = Watchdog triggered
+0x0040 = Ethernet driver (miniport) not found
+0x0080 = I/O reset active
+0x0100 = At least one device in 'INIT' state
+0x0200 = At least one device in 'PRE-OP' state
+0x0400 = At least one device in 'SAFE-OP' state
+0x0800 = At least one device indicates an error state
+0x1000 = DC not in sync
+]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12272</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>InfoData.ChangeCount</Name>
+					<Comment><![CDATA[Info data change counter]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12288</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>InfoData.DevId</Name>
+					<Comment><![CDATA[DeviceId of EtherCAT device]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12304</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>InfoData.AmsNetId</Name>
+					<Comment><![CDATA[AmsNetId of EtherCAT device]]></Comment>
+					<DataType>AMSNETID</DataType>
+					<BitSize>48</BitSize>
+					<BitOffs>12320</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>InfoData.CfgSlaveCount</Name>
+					<Comment><![CDATA[Count of configured EtherCAT slaves]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12368</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).InfoData.State</Name>
+					<Comment><![CDATA[0x___1 = Slave in 'INIT' state
+0x___2 = Slave in 'PREOP' state
+0x___3 = Slave in 'BOOT' state
+0x___4 = Slave in 'SAFEOP' state
+0x___8 = Slave in 'OP' state
+0x001_ = Slave signals error
+0x002_ = Invalid vendorId, productCode... read
+0x004_ = Initialization error occurred
+0x008_ = Slave disabled
+0x010_ = Slave not present
+0x020_ = Slave signals link error
+0x040_ = Slave signals missing link
+0x080_ = Slave signals unexpected link
+0x100_ = Communication port A
+0x200_ = Communication port B
+0x400_ = Communication port C
+0x800_ = Communication port D
+]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12384</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).InfoData.AdsAddr</Name>
+					<Comment><![CDATA[Complete ADS address to access the slave (mailbox)]]></Comment>
+					<DataType>AMSADDR</DataType>
+					<BitSize>64</BitSize>
+					<BitOffs>12400</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).InfoData.Chn0</Name>
+					<Comment><![CDATA[Slave has a channel]]></Comment>
+					<DataType>USINT</DataType>
+					<BitSize>8</BitSize>
+					<BitOffs>12464</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).InfoData.Chn1</Name>
+					<Comment><![CDATA[Slave has a channel]]></Comment>
+					<DataType>USINT</DataType>
+					<BitSize>8</BitSize>
+					<BitOffs>12472</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>SyncUnits.&lt;default&gt;.NC-Task 1 SAF.InfoData.ObjectId</Name>
+					<DataType>OTCID</DataType>
+					<BitSize>32</BitSize>
+					<BitOffs>12480</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>SyncUnits.&lt;default&gt;.NC-Task 1 SAF.InfoData.State</Name>
+					<Comment><![CDATA[0x___1 = At least one slave in 'INIT' state
+0x___2 = At least one slave in 'PREOP' state
+0x___3 = At least one slave in 'BOOT' state
+0x___4 = At least one slave in 'SAFEOP' state
+0x___8 = At least one slave in 'OP' state
+0x001_ = At least one slave signals error
+0x002_ = Invalid vendorId, productCode... read
+0x004_ = Initialization error occurred
+0x008_ = At least one slave disabled
+0x010_ = At least one slave not present
+0x020_ = At least one slave signals link error
+0x040_ = At least one slave signals missing link
+0x080_ = At least one slave signals unexpected link
+]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12512</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>SyncUnits.&lt;default&gt;.NC-Task 1 SAF.InfoData.SlaveCount</Name>
+					<Comment><![CDATA[Info data slave counter]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12528</BitOffs>
+				</Variable>
+			</Inputs>
+			<Outputs>
+				<ByteSize>1536</ByteSize>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).Module 1 (csv -  axis).Outputs.Control Word</Name>
+					<Comment><![CDATA[object 0x6040:0]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>312</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Drive 1 (ECAT_CIA402).Module 1 (csv -  axis).Outputs.TargetVelocity</Name>
+					<Comment><![CDATA[object 0x60FF:0]]></Comment>
+					<DataType>DINT</DataType>
+					<BitSize>32</BitSize>
+					<BitOffs>328</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Outputs.Frm0Ctrl</Name>
+					<Comment><![CDATA[0x0001 = prevent 1. EtherCAT command from sending (request NOP)
+0x0002 = prevent 2. EtherCAT command from sending (request NOP)
+0x0004 = prevent 3. EtherCAT command from sending (request NOP)
+...
+0x4000 = prevent 15. EtherCAT command from sending (request NOP)
+0x8000 = prevent complete frame from sending
+]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12160</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Outputs.Frm0WcCtrl</Name>
+					<Comment><![CDATA[0x0001 = copy data with wrong working counter of 1. EtherCAT command
+0x0002 = copy data with wrong working counter of 2. EtherCAT command
+0x0004 = copy data with wrong working counter of 3. EtherCAT command
+...
+0x4000 = copy data with wrong working counter of 15. EtherCAT command
+]]></Comment>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12176</BitOffs>
+				</Variable>
+				<Variable>
+					<Name>Outputs.DevCtrl</Name>
+					<DataType>UINT</DataType>
+					<BitSize>16</BitSize>
+					<BitOffs>12272</BitOffs>
+				</Variable>
+			</Outputs>
+		</ProcessImage>
+	</Config>
+</EtherCATConfig>
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ESI.xml b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ESI.xml
new file mode 100644
index 00000000..8cd34ea6
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ESI.xml
@@ -0,0 +1,2141 @@
+<?xml version="1.0" encoding="utf-8"?>
+<EtherCATInfo xmlns:xsd="http://www.w3.org/2001/XMLSchema" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="EtherCATInfo.xsd" Version="1.6">
+	<Vendor>
+		<Id>#x0048504D</Id>
+		<Name>HPMicro</Name>
+		<ImageData16x14>424DE6000000000000007600000028000000100000000E000000010004000000000070000000120B0000120B0000100000001000000000000000000080000080000000808000800000008000800080800000C0C0C000808080000000FF0000FF000000FFFF00FF000000FF00FF00FFFF0000FFFFFF009D9DD99DD9DDD9DD9D9D9DD9D9DDD9DD999D9DD9D999D9999D9D9DD9D9DDD9DD9D9DD99DD999D999DDDDDDDDDDDDDDDD88888888888888888888888888888888DDDDDDDDDDDDDDDD999D999DD99DD9D99D9D9DDD9DD9D9D999DD999D9DDDD99D9D9D9DDD9DD9D99D999D999DD99DD9D9</ImageData16x14>
+	</Vendor>
+	<Descriptions>
+		<Groups>
+			<Group>
+				<Type>ECAT_Device</Type>
+				<Name>ECAT_Device</Name>
+				<ImageData16x14>424DD8020000000000003600000028000000100000000E0000000100180000000000A2020000120B0000120B000000000000000000001306E31306E3190CE42B1FE62B1FE61306E31F13E5190CE42519E51306E31306E3190CE42F24E7190CE41306E31306E31306E31306E35F56EC645CED645CED4137E91F13E5473DE95F57EC3227E71306E3473DE95A51EC271BE61306E31306E31409CA524CC68E8AD74F48C1615CC82218D03E36BF716BCE746FCE453DC01307CE3931BA7D78D27671D1150CB21409CA1712801B1D1D1B1D1D1B1D1D1B1D1D120B891B1D1D1B1D1D1B1D1D1B1D1D120B891B1D1D1B1D1D1B1D1D1B1D1D1712801712807F8080D4D5D5D4D5D5383939120B89545656D4D5D5D4D5D5626464130C89292B2BD4D5D5D4D5D56264641915801712804647471B1D1DAAAAAAD4D5D5130E82383939292B2B717272D4D5D5151183D4D5D57F80801B1D1D7172721E1C81191580464747D4D5D5D4D5D51B1D1D19158A292B2BD4D5D5D4D5D5292B2B1B1B8AD4D5D56264641B1D1D1B1D1D2427821E1D81D4D5D54647476264643839391E208BD4D5D57F8080464747545656242A8BD4D5D59B9C9C292B2BAAAAAA2D3683252882464747D4D5D5D4D5D51B1D1D272D85292B2BD4D5D5D4D5D5292B2B2E37861B1D1DD4D5D5D4D5D5464747394484323BB52324812122822426822526824554C0323883292B822A2D83353C84424CBF3238843940842E32834853865D6EBB5262EB3E43E83334E74147E94349E9535FEB4D56EA5662EB484DEA545DEB636FED545AEA5A63EC6671ED8CA0F290A5F2748AEF6B7BEE5D68EC6874ED788AEF8397F17684EF7986EF8C9FF2818FF1818EF08E9DF18A97F18791F19BA9F3B0C0F691A4F291A2F28390F192A1F29CACF3A3B3F498A6F3A4B3F4AEBDF5B0BEF59EA8F3A3ADF4BBC7F7C4D1F8CAD7F8CED9F9B4C4F6B8C8F6ACB8F59AA3F3B6C1F6C5D2F8C2CDF8CCD7F9D2DDF9D5E0FAD2DAF9D5DCF9DFE7FBE2E9FBE5EBFBE8EEFB0000</ImageData16x14>
+			</Group>
+		</Groups>
+		<Devices>
+			<Device Physics="YYY">
+				<Type ProductCode="#x00000003" RevisionNo="#x00000001">ECAT_CIA402</Type>
+				<Name>ECAT_CIA402</Name>
+				<Info>
+					<StateMachine>
+						<Timeout>
+							<PreopTimeout>2000</PreopTimeout>
+							<SafeopOpTimeout>9000</SafeopOpTimeout>
+							<BackToInitTimeout>5000</BackToInitTimeout>
+							<BackToSafeopTimeout>200</BackToSafeopTimeout>
+						</Timeout>
+					</StateMachine>
+					<Mailbox>
+						<Timeout>
+							<RequestTimeout>100</RequestTimeout>
+							<ResponseTimeout>2000</ResponseTimeout>
+						</Timeout>
+					</Mailbox>
+					<EtherCATController>
+						<DpramSize>61440</DpramSize>
+						<SmCount>8</SmCount>
+						<FmmuCount>8</FmmuCount>
+					</EtherCATController>
+					<IdentificationReg134>true</IdentificationReg134>
+				</Info>
+				<GroupType>ECAT_Device</GroupType>
+				<Profile>
+					<ChannelInfo>
+						<ProfileNo>402</ProfileNo>
+						<AddInfo>2</AddInfo>
+					</ChannelInfo>
+					<ChannelInfo>
+						<ProfileNo>402</ProfileNo>
+						<AddInfo>0</AddInfo>
+					</ChannelInfo>
+					<Dictionary>
+						<DataTypes>
+							<DataType>
+								<Name>STRING(3)</Name>
+								<BitSize>24</BitSize>
+							</DataType>
+							<DataType>
+								<Name>STRING(11)</Name>
+								<BitSize>88</BitSize>
+							</DataType>
+							<DataType>
+								<Name>USINT</Name>
+								<BitSize>8</BitSize>
+							</DataType>
+							<DataType>
+								<Name>UDINT</Name>
+								<BitSize>32</BitSize>
+							</DataType>
+							<DataType>
+								<Name>UINT</Name>
+								<BitSize>16</BitSize>
+							</DataType>
+							<DataType>
+								<Name>ULINT</Name>
+								<BitSize>64</BitSize>
+							</DataType>
+							<DataType>
+								<Name>BOOL</Name>
+								<BitSize>1</BitSize>
+							</DataType>
+							<DataType>
+								<Name>DT1018</Name>
+								<BitSize>144</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>1</SubIdx>
+									<Name>Vendor ID</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>2</SubIdx>
+									<Name>Product Code</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>48</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>3</SubIdx>
+									<Name>Revision Number</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>80</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>4</SubIdx>
+									<Name>Serial number</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>112</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT10F1</Name>
+								<BitSize>64</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>1</SubIdx>
+									<Name>Local Error Reaction</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>2</SubIdx>
+									<Name>Sync Error Counter Limit</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>48</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT1C00ARR</Name>
+								<BaseType>USINT</BaseType>
+								<BitSize>32</BitSize>
+								<ArrayInfo>
+									<LBound>1</LBound>
+									<Elements>4</Elements>
+								</ArrayInfo>
+							</DataType>
+							<DataType>
+								<Name>DT1C00</Name>
+								<BitSize>48</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DT1C00ARR</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT1C12ARR</Name>
+								<BaseType>UINT</BaseType>
+								<BitSize>32</BitSize>
+								<ArrayInfo>
+									<LBound>1</LBound>
+									<Elements>2</Elements>
+								</ArrayInfo>
+							</DataType>
+							<DataType>
+								<Name>DT1C12</Name>
+								<BitSize>48</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access WriteRestrictions="PreOP">rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DT1C12ARR</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access WriteRestrictions="PreOP">rw</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT1C13ARR</Name>
+								<BaseType>UINT</BaseType>
+								<BitSize>32</BitSize>
+								<ArrayInfo>
+									<LBound>1</LBound>
+									<Elements>2</Elements>
+								</ArrayInfo>
+							</DataType>
+							<DataType>
+								<Name>DT1C13</Name>
+								<BitSize>48</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access WriteRestrictions="PreOP">rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DT1C13ARR</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access WriteRestrictions="PreOP">rw</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT1C32</Name>
+								<BitSize>488</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>1</SubIdx>
+									<Name>Synchronization Type</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access WriteRestrictions="PreOP">rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>2</SubIdx>
+									<Name>Cycle Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>32</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>4</SubIdx>
+									<Name>Synchronization Types supported</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>96</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>5</SubIdx>
+									<Name>Minimum Cycle Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>112</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>6</SubIdx>
+									<Name>Calc and Copy Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>144</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>8</SubIdx>
+									<Name>Get Cycle Time</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>208</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>9</SubIdx>
+									<Name>Delay Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>224</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>10</SubIdx>
+									<Name>Sync0 Cycle Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>256</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>11</SubIdx>
+									<Name>SM-Event Missed</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>288</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>12</SubIdx>
+									<Name>Cycle Time Too Small</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>304</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>13</SubIdx>
+									<Name>Shift Time Too Short Counter</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>320</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>32</SubIdx>
+									<Name>Sync Error</Name>
+									<Type>BOOL</Type>
+									<BitSize>1</BitSize>
+									<BitOffs>480</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT1C33</Name>
+								<BitSize>488</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>1</SubIdx>
+									<Name>Synchronization Type</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access WriteRestrictions="PreOP">rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>2</SubIdx>
+									<Name>Cycle Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>32</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>4</SubIdx>
+									<Name>Synchronization Types supported</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>96</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>5</SubIdx>
+									<Name>Minimum Cycle Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>112</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>6</SubIdx>
+									<Name>Calc and Copy Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>144</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>8</SubIdx>
+									<Name>Get Cycle Time</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>208</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>9</SubIdx>
+									<Name>Delay Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>224</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>10</SubIdx>
+									<Name>Sync0 Cycle Time</Name>
+									<Type>UDINT</Type>
+									<BitSize>32</BitSize>
+									<BitOffs>256</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>11</SubIdx>
+									<Name>SM-Event Missed</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>288</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>12</SubIdx>
+									<Name>Cycle Time Too Small</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>304</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>13</SubIdx>
+									<Name>Shift Time Too Short Counter</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>320</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>32</SubIdx>
+									<Name>Sync Error</Name>
+									<Type>BOOL</Type>
+									<BitSize>1</BitSize>
+									<BitOffs>480</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DTF000</Name>
+								<BitSize>48</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>1</SubIdx>
+									<Name>Index distance</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>2</SubIdx>
+									<Name>Maximum number of modules</Name>
+									<Type>UINT</Type>
+									<BitSize>16</BitSize>
+									<BitOffs>32</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DTF010ARR</Name>
+								<BaseType>UDINT</BaseType>
+								<BitSize>64</BitSize>
+								<ArrayInfo>
+									<LBound>1</LBound>
+									<Elements>2</Elements>
+								</ArrayInfo>
+							</DataType>
+							<DataType>
+								<Name>DTF010</Name>
+								<BitSize>80</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DTF010ARR</Type>
+									<BitSize>64</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DTF030ARR</Name>
+								<BaseType>UDINT</BaseType>
+								<BitSize>64</BitSize>
+								<ArrayInfo>
+									<LBound>1</LBound>
+									<Elements>2</Elements>
+								</ArrayInfo>
+							</DataType>
+							<DataType>
+								<Name>DTF030</Name>
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+										<Access WriteRestrictions="PreOP">rw</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DTF030ARR</Type>
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+									<Flags>
+										<Access WriteRestrictions="PreOP">rw</Access>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DTF050ARR</Name>
+								<BaseType>UDINT</BaseType>
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+									<Type>USINT</Type>
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+									<Flags>
+										<Access>ro</Access>
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+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DTF050ARR</Type>
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+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
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+						</DataTypes>
+						<Objects>
+							<Object>
+								<Index>#x1000</Index>
+								<Name>Device type</Name>
+								<Type>UDINT</Type>
+								<BitSize>32</BitSize>
+								<Info>
+									<DefaultData>92010000</DefaultData>
+								</Info>
+								<Flags>
+									<Access>ro</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index>#x1001</Index>
+								<Name>Error register</Name>
+								<Type>USINT</Type>
+								<BitSize>8</BitSize>
+								<Info>
+									<DefaultData>00</DefaultData>
+								</Info>
+								<Flags>
+									<Access>ro</Access>
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+							</Object>
+							<Object>
+								<Index>#x1008</Index>
+								<Name>Device name</Name>
+								<Type>STRING(11)</Type>
+								<BitSize>88</BitSize>
+								<Info>
+									<DefaultData>454341545F434941343032</DefaultData>
+								</Info>
+								<Flags>
+									<Access>ro</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index>#x1009</Index>
+								<Name>Manufacturer Hardware version</Name>
+								<Type>STRING(11)</Type>
+								<BitSize>88</BitSize>
+								<Info>
+									<DefaultData>454341545F446576696365</DefaultData>
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+								<Flags>
+									<Access>ro</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index>#x100A</Index>
+								<Name>Manufacturer Software version</Name>
+								<Type>STRING(3)</Type>
+								<BitSize>24</BitSize>
+								<Info>
+									<DefaultData>312E30</DefaultData>
+								</Info>
+								<Flags>
+									<Access>ro</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index>#x1018</Index>
+								<Name>Identity Object</Name>
+								<Type>DT1018</Type>
+								<BitSize>144</BitSize>
+								<Info>
+									<SubItem>
+										<Name>SubIndex 000</Name>
+										<Info>
+											<DefaultData>04</DefaultData>
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+									</SubItem>
+									<SubItem>
+										<Name>Vendor ID</Name>
+										<Info>
+											<DefaultData>4D504800</DefaultData>
+										</Info>
+									</SubItem>
+									<SubItem>
+										<Name>Product Code</Name>
+										<Info>
+											<DefaultData>03000000</DefaultData>
+										</Info>
+									</SubItem>
+									<SubItem>
+										<Name>Revision Number</Name>
+										<Info>
+											<DefaultData>01000000</DefaultData>
+										</Info>
+									</SubItem>
+									<SubItem>
+										<Name>Serial number</Name>
+										<Info>
+											<DefaultData>00000000</DefaultData>
+										</Info>
+									</SubItem>
+								</Info>
+							</Object>
+							<Object>
+								<Index>#x10F1</Index>
+								<Name>Error Settings</Name>
+								<Type>DT10F1</Type>
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+								<Info>
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+										<Name>SubIndex 000</Name>
+										<Info>
+											<DefaultData>02</DefaultData>
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+									<SubItem>
+										<Name>Local Error Reaction</Name>
+										<Info>
+											<DefaultData>01000000</DefaultData>
+										</Info>
+									</SubItem>
+									<SubItem>
+										<Name>Sync Error Counter Limit</Name>
+										<Info>
+											<DefaultData>0400</DefaultData>
+										</Info>
+									</SubItem>
+								</Info>
+							</Object>
+							<Object>
+								<Index>#x10F8</Index>
+								<Name>Timestamp Object</Name>
+								<Type>ULINT</Type>
+								<BitSize>64</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>t</PdoMapping>
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+							<Object>
+								<Index>#x1C00</Index>
+								<Name>Sync manager type</Name>
+								<Type>DT1C00</Type>
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+								<Info>
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+											<DefaultData>04</DefaultData>
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+							<Object>
+								<Index>#x1C12</Index>
+								<Name>RxPDO assign</Name>
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+								<Name>TxPDO assign</Name>
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+										<Name>SubIndex 000</Name>
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+										<Name>Synchronization Type</Name>
+										<Info>
+											<DefaultData>0100</DefaultData>
+										</Info>
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+									<SubItem>
+										<Name>Synchronization Types supported</Name>
+										<Info>
+											<DefaultData>0780</DefaultData>
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+									</SubItem>
+									<SubItem>
+										<Name>Minimum Cycle Time</Name>
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+											<DefaultData>E0790000</DefaultData>
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+								</Info>
+							</Object>
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+								<Name>SM input parameter</Name>
+								<Type>DT1C33</Type>
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+										<Name>Synchronization Type</Name>
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+											<DefaultData>2200</DefaultData>
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+									</SubItem>
+									<SubItem>
+										<Name>Synchronization Types supported</Name>
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+											<DefaultData>0780</DefaultData>
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+									<SubItem>
+										<Name>Minimum Cycle Time</Name>
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+											<DefaultData>E0790000</DefaultData>
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+								</Info>
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+								<Name>Modular Device Profile</Name>
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+											<DefaultData>0080</DefaultData>
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+									<SubItem>
+										<Name>Maximum number of modules</Name>
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+											<DefaultData>0200</DefaultData>
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+								<Name>Module Profile List</Name>
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+								<Name>Configured Module Ident List</Name>
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+								<Name>Module detected list</Name>
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+						</Objects>
+					</Dictionary>
+				</Profile>
+				<Fmmu>Outputs</Fmmu>
+				<Fmmu>Inputs</Fmmu>
+				<Fmmu>MBoxState</Fmmu>
+				<Sm MinSize="#x24" MaxSize="#x10C" DefaultSize="#x80" StartAddress="#x1000" ControlByte="#x26" Enable="1">MBoxOut</Sm>
+				<Sm MinSize="#x24" MaxSize="#x10C" DefaultSize="#x80" StartAddress="#x1080" ControlByte="#x22" Enable="1">MBoxIn</Sm>
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+				<Sm DefaultSize="0" StartAddress="#x1400" ControlByte="#x20" Enable="0">Inputs</Sm>
+				<Mailbox DataLinkLayer="true">
+					<CoE SdoInfo="true" PdoAssign="true" PdoConfig="false" CompleteAccess="true" SegmentedSdo="true" />
+				</Mailbox>
+				<Dc>
+					<OpMode>
+						<Name>Synchron</Name>
+						<Desc>SM-Synchron</Desc>
+						<AssignActivate>#x0</AssignActivate>
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+					<OpMode>
+						<Name>DC</Name>
+						<Desc>DC-Synchron</Desc>
+						<AssignActivate>#x300</AssignActivate>
+						<CycleTimeSync0 Factor="1">0</CycleTimeSync0>
+						<CycleTimeSync1 Factor="1">0</CycleTimeSync1>
+					</OpMode>
+				</Dc>
+				<Slots SlotPdoIncrement="16" SlotIndexIncrement="#x800">
+					<Slot MinInstances="1" MaxInstances="1">
+						<Name>Axis 0</Name>
+						<ModuleIdent Default="0">#x119800</ModuleIdent>
+						<ModuleIdent Default="0">#x219800</ModuleIdent>
+						<ModuleIdent Default="1">#x319800</ModuleIdent>
+					</Slot>
+					<Slot MinInstances="0" MaxInstances="1">
+						<Name>Axis 1</Name>
+						<ModuleIdent Default="0">#x119800</ModuleIdent>
+						<ModuleIdent Default="0">#x219800</ModuleIdent>
+						<ModuleIdent Default="0">#x319800</ModuleIdent>
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+				<Eeprom>
+					<ByteSize>2048</ByteSize>
+					<ConfigData>800C8166000000001234</ConfigData>
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+			</Device>
+		</Devices>
+		<Modules>
+			<Module>
+				<Type ModuleIdent="#x119800">csv,csp - axis</Type>
+				<Name>dynamic switch bewteen csp/csv</Name>
+				<RxPdo Fixed="true" Sm="2">
+					<Index DependOnSlot="true">#x1600</Index>
+					<Name>Outputs</Name>
+					<Entry>
+						<Index DependOnSlot="true">#x6040</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Name>Control Word</Name>
+						<Comment>object 0x6040:0</Comment>
+						<DataType>UINT</DataType>
+					</Entry>
+					<Entry>
+						<Index DependOnSlot="true">#x607A</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>32</BitLen>
+						<Name>TargetPosition</Name>
+						<Comment>object 0x607A:0</Comment>
+						<DataType>DINT</DataType>
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+					<Entry>
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+						<Name>TargetVelocity</Name>
+						<Comment>object 0x60FF:0</Comment>
+						<DataType>DINT</DataType>
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+						<Comment>object 0x6060:0</Comment>
+						<DataType>USINT</DataType>
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+					</Entry>
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+				<TxPdo Fixed="true" Sm="3">
+					<Index DependOnSlot="true">#x1a00</Index>
+					<Name>Inputs</Name>
+					<Entry>
+						<Index DependOnSlot="true">#x6041</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Name>Status Word</Name>
+						<Comment>object 0x6041:0</Comment>
+						<DataType>UINT</DataType>
+					</Entry>
+					<Entry>
+						<Index DependOnSlot="true">#x6064</Index>
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+						<Name>ActualPosition</Name>
+						<Comment>object 0x6064:0</Comment>
+						<DataType>DINT</DataType>
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+					<Entry>
+						<Index DependOnSlot="true">#x606C</Index>
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+						<BitLen>32</BitLen>
+						<Name>ActualVelocity</Name>
+						<Comment>object 0x606C:0</Comment>
+						<DataType>DINT</DataType>
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+					<Entry>
+						<Index DependOnSlot="true">#x6061</Index>
+						<SubIndex>0</SubIndex>
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+						<Name>ModeOfOperationDisplay</Name>
+						<Comment>object 0x6061:0</Comment>
+						<DataType>USINT</DataType>
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+						<Index>0</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>8</BitLen>
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+				</TxPdo>
+				<Profile>
+					<ProfileNo>402</ProfileNo>
+					<AddInfo>2</AddInfo>
+					<Dictionary>
+						<DataTypes>
+							<DataType>
+								<Name>SINT</Name>
+								<BitSize>8</BitSize>
+							</DataType>
+							<DataType>
+								<Name>USINT</Name>
+								<BitSize>8</BitSize>
+							</DataType>
+							<DataType>
+								<Name>UDINT</Name>
+								<BitSize>32</BitSize>
+							</DataType>
+							<DataType>
+								<Name>DINT</Name>
+								<BitSize>32</BitSize>
+							</DataType>
+							<DataType>
+								<Name>INT</Name>
+								<BitSize>16</BitSize>
+							</DataType>
+							<DataType>
+								<Name>UINT</Name>
+								<BitSize>16</BitSize>
+							</DataType>
+							<DataType>
+								<Name>DT607DARR</Name>
+								<BaseType>DINT</BaseType>
+								<BitSize>64</BitSize>
+								<ArrayInfo>
+									<LBound>1</LBound>
+									<Elements>2</Elements>
+								</ArrayInfo>
+							</DataType>
+							<DataType>
+								<Name>DT607D</Name>
+								<BitSize>80</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DT607DARR</Type>
+									<BitSize>64</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT60C2</Name>
+								<BitSize>32</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>1</SubIdx>
+									<Name>Interpolation time period value</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>2</SubIdx>
+									<Name>Interpolation time index</Name>
+									<Type>SINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>24</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+							</DataType>
+						</DataTypes>
+						<Objects>
+							<Object>
+								<Index DependOnSlot="true">#x603F</Index>
+								<Name>Error Code</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6040</Index>
+								<Name>Control Word</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6041</Index>
+								<Name>Status Word</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605A</Index>
+								<Name>Quick stop option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605B</Index>
+								<Name>Shutdown option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605C</Index>
+								<Name>Disable operation option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605E</Index>
+								<Name>Fault reaction option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6060</Index>
+								<Name>Modes of operation</Name>
+								<Type>SINT</Type>
+								<BitSize>8</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6061</Index>
+								<Name>Modes of operation display</Name>
+								<Type>SINT</Type>
+								<BitSize>8</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6064</Index>
+								<Name>Position actual value</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x606C</Index>
+								<Name>Velocity actual value</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6077</Index>
+								<Name>Torque actual value</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x607D</Index>
+								<Name>Software position limit</Name>
+								<Type>DT607D</Type>
+								<BitSize>80</BitSize>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x607A</Index>
+								<Name>Target position</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6085</Index>
+								<Name>Quick stop deceleration</Name>
+								<Type>UDINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x60C2</Index>
+								<Name>Interpolation time period</Name>
+								<Type>DT60C2</Type>
+								<BitSize>32</BitSize>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x60FF</Index>
+								<Name>Target velocity</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6502</Index>
+								<Name>Supported drive modes</Name>
+								<Type>UDINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+						</Objects>
+					</Dictionary>
+				</Profile>
+			</Module>
+			<Module>
+				<Type ModuleIdent="#x219800">csp - axis</Type>
+				<Name>csp</Name>
+				<RxPdo Fixed="true" Sm="2">
+					<Index DependOnSlot="true">#x1601</Index>
+					<Name>Outputs</Name>
+					<Entry>
+						<Index DependOnSlot="true">#x6040</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Name>Control Word</Name>
+						<Comment>object 0x6040:0</Comment>
+						<DataType>UINT</DataType>
+					</Entry>
+					<Entry>
+						<Index DependOnSlot="true">#x607A</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>32</BitLen>
+						<Name>TargetPosition</Name>
+						<Comment>object 0x607A:0</Comment>
+						<DataType>DINT</DataType>
+					</Entry>
+					<Entry>
+						<Index>#x0</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Comment>16bit padding</Comment>
+					</Entry>
+				</RxPdo>
+				<TxPdo Fixed="true" Sm="3">
+					<Index DependOnSlot="true">#x1a01</Index>
+					<Name>Inputs</Name>
+					<Entry>
+						<Index DependOnSlot="true">#x6041</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Name>Status Word</Name>
+						<Comment>object 0x6041:0</Comment>
+						<DataType>UINT</DataType>
+					</Entry>
+					<Entry>
+						<Index DependOnSlot="true">#x6064</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>32</BitLen>
+						<Name>ActualPosition</Name>
+						<Comment>object 0x6064:0</Comment>
+						<DataType>DINT</DataType>
+					</Entry>
+					<Entry>
+						<Index>#x0</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Comment>16bit padding</Comment>
+					</Entry>
+				</TxPdo>
+				<Mailbox>
+					<CoE>
+						<InitCmd>
+							<Transition>SO</Transition>
+							<Index DependOnSlot="true">#x6060</Index>
+							<SubIndex>0</SubIndex>
+							<Data>08</Data>
+						</InitCmd>
+					</CoE>
+				</Mailbox>
+				<Profile>
+					<ProfileNo>402</ProfileNo>
+					<AddInfo>2</AddInfo>
+					<Dictionary>
+						<DataTypes>
+							<DataType>
+								<Name>SINT</Name>
+								<BitSize>8</BitSize>
+							</DataType>
+							<DataType>
+								<Name>USINT</Name>
+								<BitSize>8</BitSize>
+							</DataType>
+							<DataType>
+								<Name>UDINT</Name>
+								<BitSize>32</BitSize>
+							</DataType>
+							<DataType>
+								<Name>DINT</Name>
+								<BitSize>32</BitSize>
+							</DataType>
+							<DataType>
+								<Name>INT</Name>
+								<BitSize>16</BitSize>
+							</DataType>
+							<DataType>
+								<Name>UINT</Name>
+								<BitSize>16</BitSize>
+							</DataType>
+							<DataType>
+								<Name>DT60C2</Name>
+								<BitSize>32</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>1</SubIdx>
+									<Name>Interpolation time period value</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>2</SubIdx>
+									<Name>Interpolation time index</Name>
+									<Type>SINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>24</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT607DARR</Name>
+								<BaseType>DINT</BaseType>
+								<BitSize>64</BitSize>
+								<ArrayInfo>
+									<LBound>1</LBound>
+									<Elements>2</Elements>
+								</ArrayInfo>
+							</DataType>
+							<DataType>
+								<Name>DT607D</Name>
+								<BitSize>80</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DT607DARR</Type>
+									<BitSize>64</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+							</DataType>
+						</DataTypes>
+						<Objects>
+							<Object>
+								<Index DependOnSlot="true">#x603F</Index>
+								<Name>Error Code</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6040</Index>
+								<Name>Control Word</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6041</Index>
+								<Name>Status Word</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605A</Index>
+								<Name>Quick stop option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605B</Index>
+								<Name>Shutdown option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605C</Index>
+								<Name>Disable operation option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605E</Index>
+								<Name>Fault reaction option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6060</Index>
+								<Name>Modes of operation</Name>
+								<Type>SINT</Type>
+								<BitSize>8</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6061</Index>
+								<Name>Modes of operation display</Name>
+								<Type>SINT</Type>
+								<BitSize>8</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6064</Index>
+								<Name>Position actual value</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x606C</Index>
+								<Name>Velocity actual value</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6077</Index>
+								<Name>Torque actual value</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x607D</Index>
+								<Name>Software position limit</Name>
+								<Type>DT607D</Type>
+								<BitSize>80</BitSize>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x607A</Index>
+								<Name>Target position</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6085</Index>
+								<Name>Quick stop deceleration</Name>
+								<Type>UDINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x60C2</Index>
+								<Name>Interpolation time period</Name>
+								<Type>DT60C2</Type>
+								<BitSize>32</BitSize>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x60FF</Index>
+								<Name>Target velocity</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6502</Index>
+								<Name>Supported drive modes</Name>
+								<Type>UDINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+						</Objects>
+					</Dictionary>
+				</Profile>
+			</Module>
+			<Module>
+				<Type ModuleIdent="#x319800">csv -  axis</Type>
+				<Name>csv</Name>
+				<RxPdo Fixed="true" Sm="2">
+					<Index DependOnSlot="true">#x1602</Index>
+					<Name>Outputs</Name>
+					<Entry>
+						<Index DependOnSlot="true">#x6040</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Name>Control Word</Name>
+						<Comment>object 0x6040:0</Comment>
+						<DataType>UINT</DataType>
+					</Entry>
+					<Entry>
+						<Index DependOnSlot="true">#x60FF</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>32</BitLen>
+						<Name>TargetVelocity</Name>
+						<Comment>object 0x60FF:0</Comment>
+						<DataType>DINT</DataType>
+					</Entry>
+					<Entry>
+						<Index>#x0</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Comment>16bit padding</Comment>
+					</Entry>
+				</RxPdo>
+				<TxPdo Fixed="true" Sm="3">
+					<Index DependOnSlot="true">#x1a02</Index>
+					<Name>Inputs</Name>
+					<Entry>
+						<Index DependOnSlot="true">#x6041</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Name>Status Word</Name>
+						<Comment>object 0x6041:0</Comment>
+						<DataType>UINT</DataType>
+					</Entry>
+					<Entry>
+						<Index DependOnSlot="true">#x6064</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>32</BitLen>
+						<Name>ActualPosition</Name>
+						<Comment>object 0x6064:0</Comment>
+						<DataType>DINT</DataType>
+					</Entry>
+					<Entry>
+						<Index>#x0</Index>
+						<SubIndex>0</SubIndex>
+						<BitLen>16</BitLen>
+						<Comment>16bit padding</Comment>
+					</Entry>
+				</TxPdo>
+				<Mailbox>
+					<CoE>
+						<InitCmd>
+							<Transition>SO</Transition>
+							<Index DependOnSlot="true">#x6060</Index>
+							<SubIndex>0</SubIndex>
+							<Data>09</Data>
+						</InitCmd>
+					</CoE>
+				</Mailbox>
+				<Profile>
+					<ProfileNo>402</ProfileNo>
+					<AddInfo>2</AddInfo>
+					<Dictionary>
+						<DataTypes>
+							<DataType>
+								<Name>SINT</Name>
+								<BitSize>8</BitSize>
+							</DataType>
+							<DataType>
+								<Name>USINT</Name>
+								<BitSize>8</BitSize>
+							</DataType>
+							<DataType>
+								<Name>UDINT</Name>
+								<BitSize>32</BitSize>
+							</DataType>
+							<DataType>
+								<Name>DINT</Name>
+								<BitSize>32</BitSize>
+							</DataType>
+							<DataType>
+								<Name>INT</Name>
+								<BitSize>16</BitSize>
+							</DataType>
+							<DataType>
+								<Name>UINT</Name>
+								<BitSize>16</BitSize>
+							</DataType>
+							<DataType>
+								<Name>DT607DARR</Name>
+								<BaseType>DINT</BaseType>
+								<BitSize>64</BitSize>
+								<ArrayInfo>
+									<LBound>1</LBound>
+									<Elements>2</Elements>
+								</ArrayInfo>
+							</DataType>
+							<DataType>
+								<Name>DT607D</Name>
+								<BitSize>80</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<Name>Elements</Name>
+									<Type>DT607DARR</Type>
+									<BitSize>64</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+							</DataType>
+							<DataType>
+								<Name>DT60C2</Name>
+								<BitSize>32</BitSize>
+								<SubItem>
+									<SubIdx>0</SubIdx>
+									<Name>SubIndex 000</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>0</BitOffs>
+									<Flags>
+										<Access>ro</Access>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>1</SubIdx>
+									<Name>Interpolation time period value</Name>
+									<Type>USINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>16</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+								<SubItem>
+									<SubIdx>2</SubIdx>
+									<Name>Interpolation time index</Name>
+									<Type>SINT</Type>
+									<BitSize>8</BitSize>
+									<BitOffs>24</BitOffs>
+									<Flags>
+										<Access>rw</Access>
+										<PdoMapping>r</PdoMapping>
+									</Flags>
+								</SubItem>
+							</DataType>
+						</DataTypes>
+						<Objects>
+							<Object>
+								<Index DependOnSlot="true">#x603F</Index>
+								<Name>Error Code</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6040</Index>
+								<Name>Control Word</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6041</Index>
+								<Name>Status Word</Name>
+								<Type>UINT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605A</Index>
+								<Name>Quick stop option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605B</Index>
+								<Name>Shutdown option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605C</Index>
+								<Name>Disable operation option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x605E</Index>
+								<Name>Fault reaction option code</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>rw</Access>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6060</Index>
+								<Name>Modes of operation</Name>
+								<Type>SINT</Type>
+								<BitSize>8</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6061</Index>
+								<Name>Modes of operation display</Name>
+								<Type>SINT</Type>
+								<BitSize>8</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6064</Index>
+								<Name>Position actual value</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x606C</Index>
+								<Name>Velocity actual value</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6077</Index>
+								<Name>Torque actual value</Name>
+								<Type>INT</Type>
+								<BitSize>16</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x607D</Index>
+								<Name>Software position limit</Name>
+								<Type>DT607D</Type>
+								<BitSize>80</BitSize>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x607A</Index>
+								<Name>Target position</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6085</Index>
+								<Name>Quick stop deceleration</Name>
+								<Type>UDINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x60C2</Index>
+								<Name>Interpolation time period</Name>
+								<Type>DT60C2</Type>
+								<BitSize>32</BitSize>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x60FF</Index>
+								<Name>Target velocity</Name>
+								<Type>DINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>rw</Access>
+									<PdoMapping>r</PdoMapping>
+								</Flags>
+							</Object>
+							<Object>
+								<Index DependOnSlot="true">#x6502</Index>
+								<Name>Supported drive modes</Name>
+								<Type>UDINT</Type>
+								<BitSize>32</BitSize>
+								<Flags>
+									<Access>ro</Access>
+									<PdoMapping>t</PdoMapping>
+								</Flags>
+							</Object>
+						</Objects>
+					</Dictionary>
+				</Profile>
+			</Module>
+		</Modules>
+	</Descriptions>
+</EtherCATInfo>
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.bin b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.bin
new file mode 100644
index 0000000000000000000000000000000000000000..2d1dbc426f55059b05bc79791bcd42c462c1084d
GIT binary patch
literal 2048
zcmd;SXiQ@O0wEIyhQz170Uiv@KprDV2m}Ng7#e^WPJ;!hNystq0&Qag8p*_<4l$S!
zVZ8<e3j-q)$VChcnhX+Pcc?LfT%^RvAjrUw!oVQHz@Pw@$431B&%p416pV(zXb6mk
Pz-S1JhQMeDpoIVc0k0#`

literal 0
HcmV?d00001

diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.h
new file mode 100644
index 00000000..12e2d4d2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.h
@@ -0,0 +1,138 @@
+/*
+The EEPROM data is created based on EtherCAT Slave Information (ESI) XML file.
+Generated 2048 bytes of EEPROM data
+Vendor ID: 0x0048504D
+Product Code: 0x00000003
+Revision: 0x00000001
+Device Name: ECAT_CIA402
+*/
+unsigned char cherryecat_eepromdata[] = {
+0x0C,0x80,0x81,0x66,0x00,0x00,0x00,0x00,0x12,0x34,0x00,0x00,0x61,0xE5,0x4D,0x50,
+0x48,0x00,0x03,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,
+0x80,0x00,0x80,0x10,0x80,0x00,0x00,0x10,0x80,0x00,0x80,0x10,0x80,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0A,0x00,0x0D,0x00,0x02,0x0B,0x45,0x43,0x41,0x54,0x5F,0x44,0x65,0x76,0x69,0x63,
+0x65,0x0B,0x45,0x43,0x41,0x54,0x5F,0x43,0x49,0x41,0x34,0x30,0x32,0x00,0x1E,0x00,
+0x0D,0x00,0x01,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x27,0x00,0x00,0x00,0x00,0x00,
+0x00,0x01,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x00,0x04,0x00,
+0x01,0x02,0x03,0x00,0x00,0x00,0x00,0x00,0x29,0x00,0x18,0x00,0x00,0x10,0x80,0x00,
+0x26,0x01,0x80,0x10,0x80,0x00,0x22,0x01,0x00,0x11,0x00,0x00,0x64,0x00,0x00,0x14,
+0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
+};
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eni_parser.py b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eni_parser.py
new file mode 100644
index 00000000..118635bb
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eni_parser.py
@@ -0,0 +1,381 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+"""
+ENI (EtherCAT Network Information) Parser
+
+Copyright (c) 2025, sakumisu
+
+SPDX-License-Identifier: Apache-2.0
+
+"""
+
+import xml.etree.ElementTree as ET
+import sys
+import os
+from typing import Dict, List, Tuple, Optional
+
+class ENIParser:
+    def __init__(self):
+        self.slaves = []
+
+    def parse_hex_value(self, hex_str: str) -> int:
+        """解析十六进制字符串"""
+        if not hex_str:
+            return 0
+        hex_str = hex_str.strip()
+        if hex_str.startswith('#x'):
+            return int(hex_str[2:], 16)
+        elif hex_str.startswith('0x'):
+            return int(hex_str[2:], 16)
+        else:
+            try:
+                return int(hex_str, 16)
+            except:
+                try:
+                    return int(hex_str, 10)
+                except:
+                    return 0
+
+    def parse_slave_info(self, slave_elem):
+        """解析从站基本信息"""
+        slave_info = {}
+
+        info_elem = slave_elem.find('Info')
+        if info_elem is not None:
+            name_elem = info_elem.find('Name')
+            if name_elem is not None:
+                slave_info['name'] = name_elem.text.strip() if name_elem.text else ""
+
+            vendor_id_elem = info_elem.find('VendorId')
+            if vendor_id_elem is not None:
+                slave_info['vendor_id'] = int(vendor_id_elem.text)
+
+            product_code_elem = info_elem.find('ProductCode')
+            if product_code_elem is not None:
+                slave_info['product_code'] = int(product_code_elem.text)
+
+            revision_no_elem = info_elem.find('RevisionNo')
+            if revision_no_elem is not None:
+                slave_info['revision_no'] = int(revision_no_elem.text)
+
+        return slave_info
+
+    def parse_pdo_entry(self, entry_elem):
+        """解析单个PDO条目"""
+        entry_info = {}
+
+        # 解析Index
+        index_elem = entry_elem.find('Index')
+        if index_elem is not None and index_elem.text:
+            entry_info['index'] = self.parse_hex_value(index_elem.text)
+        else:
+            entry_info['index'] = 0x0000
+
+        # 解析SubIndex
+        subindex_elem = entry_elem.find('SubIndex')
+        if subindex_elem is not None and subindex_elem.text:
+            entry_info['subindex'] = int(subindex_elem.text)
+        else:
+            entry_info['subindex'] = 0x00
+
+        # 解析BitLen
+        bitlen_elem = entry_elem.find('BitLen')
+        if bitlen_elem is not None and bitlen_elem.text:
+            entry_info['bit_length'] = int(bitlen_elem.text)
+        else:
+            entry_info['bit_length'] = 16
+
+        # 解析Name (作为注释)
+        name_elem = entry_elem.find('Name')
+        if name_elem is not None and name_elem.text:
+            entry_info['name'] = name_elem.text.strip()
+        else:
+            # 如果Index是0或#x0，标记为Padding
+            if entry_info['index'] == 0:
+                entry_info['name'] = 'Padding'
+            else:
+                entry_info['name'] = f'Object_{entry_info["index"]:04X}'
+
+        # 解析DataType
+        datatype_elem = entry_elem.find('DataType')
+        if datatype_elem is not None and datatype_elem.text:
+            entry_info['data_type'] = datatype_elem.text.strip()
+        else:
+            entry_info['data_type'] = 'UINT'
+
+        # 解析Comment
+        comment_elem = entry_elem.find('Comment')
+        if comment_elem is not None and comment_elem.text:
+            entry_info['comment'] = comment_elem.text.strip()
+        else:
+            entry_info['comment'] = ''
+
+        return entry_info
+
+    def parse_process_data(self, slave_elem):
+        """解析过程数据配置"""
+        process_data = {
+            'rx_pdos': [],  # 输出PDO (主站->从站)
+            'tx_pdos': [],  # 输入PDO (从站->主站)
+            'syncs': []
+        }
+
+        process_elem = slave_elem.find('ProcessData')
+        if process_elem is None:
+            return process_data
+
+        # 解析RxPDO (输出)
+        for rxpdo_elem in process_elem.findall('RxPdo'):
+            pdo_info = {}
+
+            # 解析PDO Index
+            index_elem = rxpdo_elem.find('Index')
+            if index_elem is not None:
+                pdo_info['index'] = self.parse_hex_value(index_elem.text)
+
+            # 解析PDO Name
+            name_elem = rxpdo_elem.find('Name')
+            if name_elem is not None:
+                pdo_info['name'] = name_elem.text.strip() if name_elem.text else ""
+
+            # 解析所有Entry
+            entries = []
+            for entry_elem in rxpdo_elem.findall('Entry'):
+                entry_info = self.parse_pdo_entry(entry_elem)
+                entries.append(entry_info)
+
+            pdo_info['entries'] = entries
+            process_data['rx_pdos'].append(pdo_info)
+
+        # 解析TxPDO (输入)
+        for txpdo_elem in process_elem.findall('TxPdo'):
+            pdo_info = {}
+
+            # 解析PDO Index
+            index_elem = txpdo_elem.find('Index')
+            if index_elem is not None:
+                pdo_info['index'] = self.parse_hex_value(index_elem.text)
+
+            # 解析PDO Name
+            name_elem = txpdo_elem.find('Name')
+            if name_elem is not None:
+                pdo_info['name'] = name_elem.text.strip() if name_elem.text else ""
+
+            # 解析所有Entry
+            entries = []
+            for entry_elem in txpdo_elem.findall('Entry'):
+                entry_info = self.parse_pdo_entry(entry_elem)
+                entries.append(entry_info)
+
+            pdo_info['entries'] = entries
+            process_data['tx_pdos'].append(pdo_info)
+
+        # 解析同步管理器配置
+        sm2_elem = process_elem.find('Sm2')
+        if sm2_elem is not None:
+            sm_info = {
+                'index': 2,
+                'direction': 'EC_DIR_OUTPUT',
+                'type': sm2_elem.find('Type').text if sm2_elem.find('Type') is not None else 'Outputs'
+            }
+            process_data['syncs'].append(sm_info)
+
+        sm3_elem = process_elem.find('Sm3')
+        if sm3_elem is not None:
+            sm_info = {
+                'index': 3,
+                'direction': 'EC_DIR_INPUT',
+                'type': sm3_elem.find('Type').text if sm3_elem.find('Type') is not None else 'Inputs'
+            }
+            process_data['syncs'].append(sm_info)
+
+        return process_data
+
+    def parse_eni(self, eni_file: str) -> bool:
+        """解析ENI文件"""
+        try:
+            tree = ET.parse(eni_file)
+            root = tree.getroot()
+
+            # 解析从站配置
+            for slave_elem in root.findall('.//Slave'):
+                slave_info = self.parse_slave_info(slave_elem)
+                process_data = self.parse_process_data(slave_elem)
+
+                slave_config = {
+                    'info': slave_info,
+                    'process_data': process_data
+                }
+
+                self.slaves.append(slave_config)
+
+            return True
+
+        except Exception as e:
+            print(f"Error parsing ENI file: {e}")
+            import traceback
+            traceback.print_exc()
+            return False
+
+    def generate_slave_name(self, slave_info):
+        """生成从站名称标识符"""
+        name = slave_info.get('name', 'slave')
+        # 清理名称，只保留字母数字和下划线
+        clean_name = ''.join(c if c.isalnum() or c == '_' else '_' for c in name.lower())
+        clean_name = clean_name.replace('__', '_').strip('_')
+
+        # 根据产品代码生成后缀
+        product_code = slave_info.get('product_code', 0)
+        return f'eni_{product_code:04x}'
+
+    def generate_c_code(self) -> str:
+        """生成C代码"""
+        lines = [
+            "/*",
+            " * Generated CherryECAT PDO configuration from ENI file",
+            " * Auto-generated - do not modify manually",
+            " */",
+            "",
+            "#include \"ec_master.h\"",
+            ""
+        ]
+
+        for slave_idx, slave in enumerate(self.slaves):
+            slave_info = slave['info']
+            process_data = slave['process_data']
+
+            slave_name = self.generate_slave_name(slave_info)
+
+            lines.append(f"// Slave {slave_idx + 1}: {slave_info.get('name', 'Unknown')}")
+            lines.append(f"// Vendor ID: 0x{slave_info.get('vendor_id', 0):08X}")
+            lines.append(f"// Product Code: 0x{slave_info.get('product_code', 0):08X}")
+            lines.append("")
+
+            # 生成RxPDO entries (输出)
+            rx_entries_generated = set()
+            for pdo in process_data['rx_pdos']:
+                pdo_index = pdo.get('index', 0)
+                pdo_hex = f"{pdo_index:04x}"
+                entries_name = f"{slave_name}_{pdo_hex}"
+
+                if entries_name not in rx_entries_generated:
+                    lines.append(f"static ec_pdo_entry_info_t {entries_name}[] = {{")
+
+                    # 生成每个entry
+                    for entry in pdo.get('entries', []):
+                        comment = entry.get('name', 'Padding')
+                        lines.append(f"    {{ 0x{entry['index']:04x}, 0x{entry['subindex']:02x}, 0x{entry['bit_length']:02x} }},  // {comment}")
+
+                    lines.append("};")
+                    lines.append("")
+                    rx_entries_generated.add(entries_name)
+
+            # 生成TxPDO entries (输入)
+            tx_entries_generated = set()
+            for pdo in process_data['tx_pdos']:
+                pdo_index = pdo.get('index', 0)
+                pdo_hex = f"{pdo_index:04x}"
+                entries_name = f"{slave_name}_{pdo_hex}"
+
+                if entries_name not in tx_entries_generated:
+                    lines.append(f"static ec_pdo_entry_info_t {entries_name}[] = {{")
+
+                    # 生成每个entry
+                    for entry in pdo.get('entries', []):
+                        comment = entry.get('name', 'Padding')
+                        lines.append(f"    {{ 0x{entry['index']:04x}, 0x{entry['subindex']:02x}, 0x{entry['bit_length']:02x} }},  // {comment}")
+
+                    lines.append("};")
+                    lines.append("")
+                    tx_entries_generated.add(entries_name)
+
+            # 生成RxPDO info
+            if process_data['rx_pdos']:
+                lines.append(f"static ec_pdo_info_t {slave_name}_rxpdos[] = {{")
+                for pdo in process_data['rx_pdos']:
+                    pdo_index = pdo.get('index', 0)
+                    pdo_hex = f"{pdo_index:04x}"
+                    entries_name = f"{slave_name}_{pdo_hex}"
+                    entry_count = len(pdo.get('entries', []))
+                    lines.append(f"    {{ 0x{pdo_index:04x}, {entry_count}, &{entries_name}[0] }},")
+                lines.append("};")
+                lines.append("")
+
+            # 生成TxPDO info
+            if process_data['tx_pdos']:
+                lines.append(f"static ec_pdo_info_t {slave_name}_txpdos[] = {{")
+                for pdo in process_data['tx_pdos']:
+                    pdo_index = pdo.get('index', 0)
+                    pdo_hex = f"{pdo_index:04x}"
+                    entries_name = f"{slave_name}_{pdo_hex}"
+                    entry_count = len(pdo.get('entries', []))
+                    lines.append(f"    {{ 0x{pdo_index:04x}, {entry_count}, &{entries_name}[0] }},")
+                lines.append("};")
+                lines.append("")
+
+            # 生成同步管理器配置
+            lines.append(f"static ec_sync_info_t {slave_name}_syncs[] = {{")
+
+            # 添加SM2 (输出)
+            if process_data['rx_pdos']:
+                lines.append(f"    {{ 2, EC_DIR_OUTPUT, {len(process_data['rx_pdos'])}, {slave_name}_rxpdos }},")
+
+            # 添加SM3 (输入)
+            if process_data['tx_pdos']:
+                lines.append(f"    {{ 3, EC_DIR_INPUT, {len(process_data['tx_pdos'])}, {slave_name}_txpdos }},")
+
+            lines.append("};")
+            lines.append("")
+
+        return "\n".join(lines)
+
+def main():
+    if len(sys.argv) != 3:
+        print("Usage: python eni_parser.py <input.xml> <output.h>")
+        print("  input.xml  - ENI XML file")
+        print("  output.h   - Output C header file")
+        sys.exit(1)
+
+    input_file = sys.argv[1]
+    output_file = sys.argv[2]
+
+    if not os.path.exists(input_file):
+        print(f"Error: Input file '{input_file}' not found")
+        sys.exit(1)
+
+    # 创建解析器
+    parser = ENIParser()
+
+    # 解析ENI文件
+    print(f"Parsing ENI file: {input_file}")
+    if not parser.parse_eni(input_file):
+        print("Failed to parse ENI file")
+        sys.exit(1)
+
+    # 生成C代码
+    print("Generating C code...")
+    c_code = parser.generate_c_code()
+
+    # 写入输出文件
+    try:
+        with open(output_file, 'w') as f:
+            f.write(c_code)
+
+        print(f"✓ Successfully converted '{input_file}' to '{output_file}'")
+        print(f"✓ Generated C code for {len(parser.slaves)} slave(s)")
+
+        # 显示生成的PDO映射信息
+        for slave_idx, slave in enumerate(parser.slaves):
+            process_data = slave['process_data']
+            print(f"✓ Slave {slave_idx + 1}:")
+            for pdo in process_data['rx_pdos']:
+                print(f"  - RxPDO 0x{pdo.get('index', 0):04X}: {len(pdo.get('entries', []))} entries")
+            for pdo in process_data['tx_pdos']:
+                print(f"  - TxPDO 0x{pdo.get('index', 0):04X}: {len(pdo.get('entries', []))} entries")
+
+    except Exception as e:
+        print(f"Error writing output file: {e}")
+        sys.exit(1)
+
+if __name__ == "__main__":
+    main()
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/esi_parser.py b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/esi_parser.py
new file mode 100644
index 00000000..add2f274
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/esi_parser.py
@@ -0,0 +1,510 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+"""
+ESI(EtherCAT Slave Information) to EEPROM Binary Converter
+
+Copyright (c) 2025, sakumisu
+
+SPDX-License-Identifier: Apache-2.0
+
+"""
+
+import xml.etree.ElementTree as ET
+import struct
+import sys
+import os
+from typing import Dict, List, Tuple, Optional
+
+class EtherCATXMLParser:
+    def __init__(self):
+        # 设备基本信息
+        self.vendor_id = 0x00000000  # 默认厂商ID
+        self.product_code = 0x00000000  # 默认产品代码
+        self.revision_no = 0x00000000  # 默认版本号
+        self.serial_number = 0x00000000  # 序列号
+        self.device_name = ""
+        self.device_type = ""
+
+        # 邮箱配置
+        self.mailbox_protocols = 0x0
+        self.boot_rx_mailbox = {}
+        self.boot_tx_mailbox = {}
+        self.std_rx_mailbox = {}
+        self.std_tx_mailbox = {}
+
+        # 字符串表
+        self.strings = []
+
+        # 类别数据
+        self.categories = []
+
+    def parse_hex_value(self, hex_str: str) -> int:
+        """解析十六进制字符串"""
+        if not hex_str:
+            return 0
+        hex_str = hex_str.strip()
+        if hex_str.startswith('#x'):
+            return int(hex_str[2:], 16)
+        elif hex_str.startswith('0x'):
+            return int(hex_str[2:], 16)
+        else:
+            try:
+                return int(hex_str, 16)
+            except:
+                return int(hex_str, 10)
+
+    def parse_device_info(self, device_elem):
+        """解析设备基本信息"""
+        # 获取产品代码和版本号
+        type_elem = device_elem.find('Type')
+        if type_elem is not None:
+            product_code = type_elem.get('ProductCode')
+            if product_code:
+                self.product_code = self.parse_hex_value(product_code)
+
+            revision_no = type_elem.get('RevisionNo')
+            if revision_no:
+                self.revision_no = self.parse_hex_value(revision_no)
+
+        # 获取设备名称
+        name_elem = device_elem.find('Name')
+        if name_elem is not None and name_elem.text:
+            self.device_name = name_elem.text.strip()
+
+        # 获取设备类型
+        type_name = device_elem.find('Type/Name')
+        if type_name is not None and type_name.text:
+            self.device_type = type_name.text.strip()
+
+    def parse_vendor_info(self, vendor_elem):
+        """解析厂商信息"""
+        vendor_id_elem = vendor_elem.find('Id')
+        if vendor_id_elem is not None and vendor_id_elem.text:
+            self.vendor_id = self.parse_hex_value(vendor_id_elem.text)
+
+    def parse_mailbox_info(self, device_elem):
+        """解析邮箱信息"""
+        mailbox_elem = device_elem.find('.//Mailbox')
+        if mailbox_elem is not None:
+            # 检查支持的协议
+            self.mailbox_protocols = 0
+
+            if mailbox_elem.find('CoE') is not None:
+                self.mailbox_protocols |= 0x04  # CoE
+            if mailbox_elem.find('FoE') is not None:
+                self.mailbox_protocols |= 0x08  # FoE
+            if mailbox_elem.find('EoE') is not None:
+                self.mailbox_protocols |= 0x10  # EoE
+            if mailbox_elem.find('SoE') is not None:
+                self.mailbox_protocols |= 0x20  # SoE
+
+        # 从SM配置中获取邮箱地址和大小
+        sm_elems = device_elem.findall('.//Sm')
+        for i, sm_elem in enumerate(sm_elems):
+            start_addr = self.parse_hex_value(sm_elem.get('StartAddress', '0'))
+            size = self.parse_hex_value(sm_elem.get('DefaultSize', '0'))
+
+            if i == 0:  # MBoxOut (接收)
+                self.boot_rx_mailbox = {"offset": start_addr, "size": size}
+                self.std_rx_mailbox = {"offset": start_addr, "size": size}
+            elif i == 1:  # MBoxIn (发送)
+                self.boot_tx_mailbox = {"offset": start_addr, "size": size}
+                self.std_tx_mailbox = {"offset": start_addr, "size": size}
+
+    def add_string(self, text: str) -> int:
+        """添加字符串到字符串表，返回索引"""
+        if not text:
+            return 0
+
+        # 检查是否已存在
+        for i, existing in enumerate(self.strings):
+            if existing == text:
+                return i + 1
+
+        # 添加新字符串
+        self.strings.append(text)
+        return len(self.strings)
+
+    def create_strings_category(self) -> bytes:
+        """创建字符串类别(Category 10)"""
+        if not self.strings:
+            return b''
+
+        data = bytearray()
+
+        # 字符串数量
+        data.append(len(self.strings))
+
+        # 每个字符串: 长度 + 内容
+        for string in self.strings:
+            string_bytes = string.encode('ascii', errors='replace')
+            data.append(len(string_bytes))
+            data.extend(string_bytes)
+
+        # 填充到偶数长度
+        if len(data) % 2:
+            data.append(0)
+
+        return bytes(data)
+
+    def create_general_category(self) -> bytes:
+        """创建通用类别(Category 30)"""
+        data = bytearray()
+
+        # Group Type String Index (2 bytes)
+        group_idx = self.add_string("ECAT_Device")
+        data.extend(struct.pack('<H', group_idx))
+
+        # Image Name String Index (2 bytes)
+        image_idx = self.add_string("ECAT_CIA402")
+        data.extend(struct.pack('<H', image_idx))
+
+        # Order Number String Index (2 bytes)
+        order_idx = self.add_string("")
+        data.extend(struct.pack('<H', order_idx))
+
+        # Device Name String Index (2 bytes)
+        name_idx = self.add_string(self.device_name)
+        data.extend(struct.pack('<H', name_idx))
+
+        # CoE Details (2 bytes) - 支持SDO, PDO配置
+        coe_details = 0x0027  # Enable SDO, SDO Info, PDO Assign, PDO Config
+        data.extend(struct.pack('<H', coe_details))
+
+        # FoE Details (2 bytes)
+        foe_details = 0x0000
+        data.extend(struct.pack('<H', foe_details))
+
+        # EoE Details (2 bytes)
+        eoe_details = 0x0000
+        data.extend(struct.pack('<H', eoe_details))
+
+        # SoE Channels (1 byte)
+        soe_channels = 0x00
+        data.append(soe_channels)
+
+        # DS402 Channels (1 byte)
+        ds402_channels = 0x01
+        data.append(ds402_channels)
+
+        # SysmanClass (1 byte)
+        sysman_class = 0x00
+        data.append(sysman_class)
+
+        # Flags (1 byte)
+        flags = 0x01  # Enable SafeOp
+        data.append(flags)
+
+        # Current Consumption (2 bytes)
+        current = 0x0000
+        data.extend(struct.pack('<H', current))
+
+        # Group Type and Image Name for 2nd device (if any)
+        data.extend(struct.pack('<H', 0x0000))  # Group Type 2
+        data.extend(struct.pack('<H', 0x0000))  # Image Name 2
+
+        # Physical Memory Address (2 bytes)
+        phys_addr = 0x0000
+        data.extend(struct.pack('<H', phys_addr))
+
+        # 填充到偶数长度
+        if len(data) % 2:
+            data.append(0)
+
+        return bytes(data)
+
+    def create_fmmu_category(self) -> bytes:
+        """创建FMMU类别(Category 40)"""
+        data = bytearray()
+
+        # FMMU配置 - 8个FMMU
+        fmmu_configs = [
+            0x01,  # FMMU0: Outputs
+            0x02,  # FMMU1: Inputs
+            0x03,  # FMMU2: MBox State
+            0x00,  # FMMU3: Unused
+            0x00,  # FMMU4: Unused
+            0x00,  # FMMU5: Unused
+            0x00,  # FMMU6: Unused
+            0x00,  # FMMU7: Unused
+        ]
+
+        for config in fmmu_configs:
+            data.append(config)
+
+        return bytes(data)
+
+    def create_sm_category(self) -> bytes:
+        """创建同步管理器类别(Category 41)"""
+        data = bytearray()
+
+        # SM配置数据结构: StartAddr(2) + Length(2) + ControlByte(1) + Enable(1)
+        sm_configs = [
+            # SM0: MBoxOut (接收邮箱)
+            (self.boot_rx_mailbox["offset"], self.boot_rx_mailbox["size"], 0x26, 0x01),
+            # SM1: MBoxIn (发送邮箱)
+            (self.boot_tx_mailbox["offset"], self.boot_tx_mailbox["size"], 0x22, 0x01),
+            # SM2: Process Data Output
+            (0x1100, 0x0000, 0x64, 0x00),  # 长度为0表示未配置
+            # SM3: Process Data Input
+            (0x1400, 0x0000, 0x20, 0x00),  # 长度为0表示未配置
+            # SM4-7: 未使用
+            (0x0000, 0x0000, 0x00, 0x00),
+            (0x0000, 0x0000, 0x00, 0x00),
+            (0x0000, 0x0000, 0x00, 0x00),
+            (0x0000, 0x0000, 0x00, 0x00),
+        ]
+
+        for start_addr, length, control, enable in sm_configs:
+            data.extend(struct.pack('<H', start_addr))  # Start Address
+            data.extend(struct.pack('<H', length))      # Length
+            data.append(control)                        # Control Byte
+            data.append(enable)                         # Enable
+
+        return bytes(data)
+
+    def create_category(self, category_type: int, data: bytes) -> bytes:
+        """创建类别头部+数据"""
+        header = bytearray()
+
+        # Category Type (2 bytes)
+        header.extend(struct.pack('<H', category_type))
+
+        # Category Size in words (2 bytes)
+        size_words = (len(data) + 1) // 2
+        header.extend(struct.pack('<H', size_words))
+
+        return bytes(header) + data
+
+    def generate_eeprom(self) -> bytes:
+        """生成完整的EEPROM数据，参考eeprom.h的格式"""
+        eeprom_data = bytearray()
+
+        # === EEPROM Header (固定128字节) ===
+
+        # PDI Control (2 bytes) - 0x800C (Digital I/O + SII EEPROM)
+        eeprom_data.extend(struct.pack('<H', 0x800C))
+
+        # PDI Configuration (2 bytes) - 0x6681
+        eeprom_data.extend(struct.pack('<H', 0x6681))
+
+        # Sync Impulse Length (2 bytes)
+        eeprom_data.extend(struct.pack('<H', 0x0000))
+
+        # PDI Configuration 2 (2 bytes)
+        eeprom_data.extend(struct.pack('<H', 0x0000))
+
+        # Station Alias (2 bytes)
+        eeprom_data.extend(struct.pack('<H', 0x3412))
+
+        # Reserved (2 bytes)
+        eeprom_data.extend(struct.pack('<H', 0x0000))
+
+        # Checksum (2 bytes) - 稍后计算
+        checksum_pos = len(eeprom_data)
+        eeprom_data.extend(struct.pack('<H', 0x0077))  # 临时值
+
+        # Vendor ID (4 bytes)
+        eeprom_data.extend(struct.pack('<L', self.vendor_id))
+
+        # Product Code (4 bytes)
+        eeprom_data.extend(struct.pack('<L', self.product_code))
+
+        # Revision Number (4 bytes)
+        eeprom_data.extend(struct.pack('<L', self.revision_no))
+
+        # Serial Number (4 bytes)
+        eeprom_data.extend(struct.pack('<L', self.serial_number))
+
+        # Bootstrap Mailbox Receive Offset (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.boot_rx_mailbox["offset"]))
+
+        # Bootstrap Mailbox Receive Size (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.boot_rx_mailbox["size"]))
+
+        # Bootstrap Mailbox Send Offset (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.boot_tx_mailbox["offset"]))
+
+        # Bootstrap Mailbox Send Size (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.boot_tx_mailbox["size"]))
+
+        # Standard Mailbox Receive Offset (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.std_rx_mailbox["offset"]))
+
+        # Standard Mailbox Receive Size (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.std_rx_mailbox["size"]))
+
+        # Standard Mailbox Send Offset (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.std_tx_mailbox["offset"]))
+
+        # Standard Mailbox Send Size (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.std_tx_mailbox["size"]))
+
+        # Mailbox Protocol (2 bytes)
+        eeprom_data.extend(struct.pack('<H', self.mailbox_protocols))
+
+        # Reserved bytes to reach 128 bytes header
+        current_size = len(eeprom_data)
+        header_size = 128
+        if current_size < header_size:
+            eeprom_data.extend(b'\x00' * (header_size - current_size))
+
+        # === Categories Section ===
+
+        # Category 10: Strings
+        strings_data = self.create_strings_category()
+        if strings_data:
+            eeprom_data.extend(self.create_category(10, strings_data))
+
+        # Category 30: General
+        general_data = self.create_general_category()
+        eeprom_data.extend(self.create_category(30, general_data))
+
+        # Category 40: FMMU
+        fmmu_data = self.create_fmmu_category()
+        eeprom_data.extend(self.create_category(40, fmmu_data))
+
+        # Category 41: SyncM
+        sm_data = self.create_sm_category()
+        eeprom_data.extend(self.create_category(41, sm_data))
+
+        # End of Categories marker
+        eeprom_data.extend(struct.pack('<H', 0xFFFF))
+        eeprom_data.extend(struct.pack('<H', 0x0000))
+
+        # 填充到合适的大小 (通常是2KB)
+        target_size = 2048
+        if len(eeprom_data) < target_size:
+            eeprom_data.extend(b'\xFF' * (target_size - len(eeprom_data)))
+
+        # 重新计算校验和 (SII头部校验和)
+        checksum = 0
+        # 计算前14字节的校验和，跳过校验和字段本身
+        for i in range(0, 14, 2):
+            if i != 12:  # 跳过校验和位置
+                word = struct.unpack('<H', eeprom_data[i:i+2])[0]
+                checksum += word
+
+        checksum = (~checksum + 1) & 0xFFFF  # 2's complement
+
+        # 更新校验和
+        struct.pack_into('<H', eeprom_data, checksum_pos, checksum)
+
+        return bytes(eeprom_data)
+
+    def parse_xml(self, xml_file: str) -> bool:
+        """解析XML文件"""
+        try:
+            tree = ET.parse(xml_file)
+            root = tree.getroot()
+
+            # 查找并解析厂商信息
+            vendor_elem = root.find('.//Vendor')
+            if vendor_elem is not None:
+                self.parse_vendor_info(vendor_elem)
+
+            # 查找并解析设备信息
+            device_elem = root.find('.//Device')
+            if device_elem is not None:
+                self.parse_device_info(device_elem)
+                self.parse_mailbox_info(device_elem)
+
+            print(f"Parsed XML: Vendor=0x{self.vendor_id:08X}, Product=0x{self.product_code:08X}")
+            print(f"Device Name: {self.device_name}")
+            print(f"Mailbox RX: 0x{self.std_rx_mailbox['offset']:04X}({self.std_rx_mailbox['size']})")
+            print(f"Mailbox TX: 0x{self.std_tx_mailbox['offset']:04X}({self.std_tx_mailbox['size']})")
+
+            return True
+
+        except Exception as e:
+            print(f"Error parsing XML file: {e}")
+            import traceback
+            traceback.print_exc()
+            return False
+
+    def generate_c_header(self, array_name: str = "cherryecat_eepromdata") -> str:
+        """生成C语言头文件格式的数组"""
+        eeprom_data = self.generate_eeprom()
+
+        lines = [
+            "/*",
+            f"The EEPROM data is created based on EtherCAT Slave Information (ESI) XML file.",
+            f"Generated {len(eeprom_data)} bytes of EEPROM data",
+            f"Vendor ID: 0x{self.vendor_id:08X}",
+            f"Product Code: 0x{self.product_code:08X}",
+            f"Revision: 0x{self.revision_no:08X}",
+            f"Device Name: {self.device_name}",
+            "*/",
+            f"unsigned char {array_name}[] = {{",
+        ]
+
+        # 按16字节一行格式化数据
+        for i in range(0, len(eeprom_data), 16):
+            chunk = eeprom_data[i:i+16]
+            hex_values = [f"0x{b:02X}" for b in chunk]
+            line = ",".join(hex_values)
+            if i + 16 < len(eeprom_data):
+                line += ","
+            lines.append(line)
+
+        lines.append("};")
+
+        return "\n".join(lines)
+
+def main():
+    if len(sys.argv) < 3:
+        print("Usage: python esi_parse.py <input.xml> <output.bin> [output.h]")
+        print("  input.xml  - EtherCAT ESI XML file")
+        print("  output.bin - Output binary EEPROM file")
+        print("  output.h   - Optional C header file output")
+        sys.exit(1)
+
+    input_file = sys.argv[1]
+    output_file = sys.argv[2]
+    header_file = sys.argv[3] if len(sys.argv) > 3 else None
+
+    if not os.path.exists(input_file):
+        print(f"Error: Input file '{input_file}' not found")
+        sys.exit(1)
+
+    # 创建解析器
+    parser = EtherCATXMLParser()
+
+    # 解析XML
+    print(f"Parsing XML file: {input_file}")
+    if not parser.parse_xml(input_file):
+        print("Failed to parse XML file")
+        sys.exit(1)
+
+    # 生成EEPROM数据
+    print("Generating EEPROM data...")
+    eeprom_data = parser.generate_eeprom()
+
+    # 写入二进制文件
+    try:
+        with open(output_file, 'wb') as f:
+            f.write(eeprom_data)
+
+        print(f"✓ Successfully converted '{input_file}' to '{output_file}'")
+        print(f"✓ Generated {len(eeprom_data)} bytes of EEPROM data")
+        print(f"✓ Vendor ID: 0x{parser.vendor_id:08X}")
+        print(f"✓ Product Code: 0x{parser.product_code:08X}")
+        print(f"✓ Revision: 0x{parser.revision_no:08X}")
+        print(f"✓ Device Name: {parser.device_name}")
+
+    except Exception as e:
+        print(f"Error writing binary file: {e}")
+        sys.exit(1)
+
+    # 生成C头文件(可选)
+    if header_file:
+        try:
+            header_content = parser.generate_c_header()
+            with open(header_file, 'w') as f:
+                f.write(header_content)
+            print(f"✓ Generated C header file: {header_file}")
+        except Exception as e:
+            print(f"Error writing header file: {e}")
+
+if __name__ == "__main__":
+    main()
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/sync_config.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/sync_config.h
new file mode 100644
index 00000000..68152ba1
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/sync_config.h
@@ -0,0 +1,35 @@
+/*
+ * Generated CherryECAT PDO configuration from ENI file
+ * Auto-generated - do not modify manually
+ */
+
+#include "ec_master.h"
+
+// Slave 1: Drive 1 (ECAT_CIA402)
+// Vendor ID: 0x0048504D
+// Product Code: 0x00000003
+
+static ec_pdo_entry_info_t eni_0003_1602[] = {
+    { 0x6040, 0x00, 0x10 },  // Control Word
+    { 0x60ff, 0x00, 0x20 },  // TargetVelocity
+    { 0x0000, 0x00, 0x10 },  // Padding
+};
+
+static ec_pdo_entry_info_t eni_0003_1a02[] = {
+    { 0x6041, 0x00, 0x10 },  // Status Word
+    { 0x6064, 0x00, 0x20 },  // ActualPosition
+    { 0x0000, 0x00, 0x10 },  // Padding
+};
+
+static ec_pdo_info_t eni_0003_rxpdos[] = {
+    { 0x1602, 3, &eni_0003_1602[0] },
+};
+
+static ec_pdo_info_t eni_0003_txpdos[] = {
+    { 0x1a02, 3, &eni_0003_1a02[0] },
+};
+
+static ec_sync_info_t eni_0003_syncs[] = {
+    { 2, EC_DIR_OUTPUT, 1, eni_0003_rxpdos },
+    { 3, EC_DIR_INPUT, 1, eni_0003_txpdos },
+};
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_cmd.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_cmd.c
new file mode 100644
index 00000000..620c2f29
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_cmd.c
@@ -0,0 +1,1059 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+#ifdef CONFIG_EC_CMD_ENABLE
+
+typedef struct {
+    uint32_t slave_count;
+    uint8_t phase;
+    uint8_t active;
+    struct ec_ioctl_device {
+        uint8_t mac_addr[6];
+        uint8_t attached;
+        uint8_t link_state;
+        uint64_t tx_count;
+        uint64_t rx_count;
+        uint64_t tx_bytes;
+        uint64_t rx_bytes;
+        uint64_t tx_errors;
+        int32_t tx_frame_rates[EC_RATE_COUNT];
+        int32_t rx_frame_rates[EC_RATE_COUNT];
+        int32_t tx_byte_rates[EC_RATE_COUNT];
+        int32_t rx_byte_rates[EC_RATE_COUNT];
+    } netdevs[CONFIG_EC_MAX_NETDEVS];
+    uint32_t num_netdevs;
+    uint64_t tx_count;
+    uint64_t rx_count;
+    uint64_t tx_bytes;
+    uint64_t rx_bytes;
+    int32_t tx_frame_rates[EC_RATE_COUNT];
+    int32_t rx_frame_rates[EC_RATE_COUNT];
+    int32_t tx_byte_rates[EC_RATE_COUNT];
+    int32_t rx_byte_rates[EC_RATE_COUNT];
+    int32_t loss_rates[EC_RATE_COUNT];
+    uint64_t app_time;
+    uint64_t dc_ref_time;
+    uint16_t ref_clock;
+} ec_cmd_master_info_t;
+
+typedef struct {
+    uint32_t netdev_idx;
+    uint32_t vendor_id;
+    uint32_t product_code;
+    uint32_t revision_number;
+    uint32_t serial_number;
+    uint16_t alias;
+    uint16_t boot_rx_mailbox_offset;
+    uint16_t boot_rx_mailbox_size;
+    uint16_t boot_tx_mailbox_offset;
+    uint16_t boot_tx_mailbox_size;
+    uint16_t std_rx_mailbox_offset;
+    uint16_t std_rx_mailbox_size;
+    uint16_t std_tx_mailbox_offset;
+    uint16_t std_tx_mailbox_size;
+    uint16_t mailbox_protocols;
+    bool has_general;
+    ec_sii_coe_details_t coe_details;
+    ec_sii_general_flags_t general_flags;
+    int16_t current_on_ebus;
+    struct {
+        ec_slave_port_desc_t desc;
+        ec_slave_port_link_t link;
+        uint32_t receive_time;
+        uint16_t next_slave;
+        uint32_t delay_to_next_dc;
+    } ports[EC_MAX_PORTS];
+    uint8_t base_fmmu_bit_operation;
+    uint8_t base_dc_supported;
+    ec_slave_dc_range_t base_dc_range;
+    uint8_t has_dc_system_time;
+    uint32_t transmission_delay;
+    uint8_t current_state;
+    uint8_t error_flag;
+    uint8_t sync_count;
+    uint16_t sdo_count;
+    uint32_t sii_nwords;
+    char *group;
+    char *image;
+    char *order;
+    char *name;
+} ec_cmd_slave_info_t;
+
+static ec_master_t *global_cmd_master = NULL;
+
+void ec_master_cmd_init(ec_master_t *master)
+{
+    global_cmd_master = master;
+}
+
+static void ec_master_cmd_show_help(void)
+{
+    EC_LOG_RAW("CherryECAT " CHERRYECAT_VERSION_STR " Command Line Tool\n\n");
+    EC_LOG_RAW("Usage: ethercat <command> [options]\n");
+    EC_LOG_RAW("Commands:\n");
+    EC_LOG_RAW("  master                                         Show master information\n");
+    EC_LOG_RAW("  slaves                                         Show slaves overview\n");
+    EC_LOG_RAW("  slaves -v                                      Show detailed information for all slaves\n");
+    EC_LOG_RAW("  slaves -p <idx>                                Show information for slave <idx>\n");
+    EC_LOG_RAW("  slaves -p <idx> -v                             Show detailed information for slave <idx>\n");
+    EC_LOG_RAW("  pdos                                           Show PDOs for all slaves\n");
+    EC_LOG_RAW("  pdos -p <idx>                                  Show PDOs for slave <idx>\n");
+    EC_LOG_RAW("  states <state>                                 Request state for all slaves (hex)\n");
+    EC_LOG_RAW("  states -p <idx> <state>                        Request state for slave <idx> (hex)\n");
+    EC_LOG_RAW("  coe_read -p [idx] [index] [subindex]           Read SDO via CoE\n");
+    EC_LOG_RAW("  coe_write -p [idx] [index] [subindex] [data]   Write SDO via CoE\n");
+    EC_LOG_RAW("  pdo_read                                       Read process data\n");
+    EC_LOG_RAW("  pdo_read -p [idx]                              Read slave <idx> process data\n");
+    EC_LOG_RAW("  pdo_write [offset] [hex low...high]            Write hexarray with offset to pdo\n");
+    EC_LOG_RAW("  pdo_write -p [idx] [offset] [hex low...high]   Write slave <idx> hexarray with offset to pdo\n");
+#ifdef CONFIG_EC_FOE
+    EC_LOG_RAW("  foe_write -p [idx] [filename] [pwd] [hexdata]  Read hexarray via FoE\n");
+    EC_LOG_RAW("  foe_read -p [idx] [filename] [pwd]             Write hexarray via FoE\n");
+#endif
+    EC_LOG_RAW("  sii_read -p [idx]                              Read SII\n");
+    EC_LOG_RAW("  wc                                             Show master working counter\n");
+#ifdef CONFIG_EC_PERF_ENABLE
+    EC_LOG_RAW("  perf -s <time>                                 Start performance test\n");
+    EC_LOG_RAW("  perf -v                                        Show performance statistics\n");
+#endif
+    EC_LOG_RAW("  timediff -s                                    Enable system time diff monitor\n");
+    EC_LOG_RAW("  timediff -d                                    Disable system time diff monitor\n");
+    EC_LOG_RAW("  timediff -v                                    Show system time diff statistics\n");
+    EC_LOG_RAW("  help                                           Show this help\n\n");
+}
+
+static const char *ec_slave_state_string(uint8_t state)
+{
+    switch (state) {
+        case 0x01:
+            return "INIT";
+        case 0x02:
+            return "PREOP";
+        case 0x03:
+            return "BOOT";
+        case 0x04:
+            return "SAFEOP";
+        case 0x08:
+            return "OP";
+        default:
+            return "UNKNOWN";
+    }
+}
+
+static const char *ec_port_desc_string(uint8_t desc)
+{
+    switch (desc) {
+        case 0:
+            return "N/A";
+        case 1:
+            return "N/C";
+        case 2:
+            return "EBUS";
+        case 3:
+            return "MII";
+        default:
+            return "???";
+    }
+}
+
+static void ec_master_get_master_info(ec_master_t *master, ec_cmd_master_info_t *info)
+{
+    unsigned int dev_idx;
+    int j;
+
+    info->slave_count = master->slave_count;
+    info->phase = (uint8_t)master->phase;
+
+    for (dev_idx = EC_NETDEV_MAIN; dev_idx < CONFIG_EC_MAX_NETDEVS; dev_idx++) {
+        ec_netdev_t *device = master->netdev[dev_idx];
+
+        ec_memcpy(info->netdevs[dev_idx].mac_addr, device->mac_addr, ETH_ALEN);
+
+        info->netdevs[dev_idx].attached = master->netdev[dev_idx] ? 1 : 0;
+        info->netdevs[dev_idx].link_state = device->link_state ? 1 : 0;
+        info->netdevs[dev_idx].tx_count = device->tx_count;
+        info->netdevs[dev_idx].rx_count = device->rx_count;
+        info->netdevs[dev_idx].tx_bytes = device->tx_bytes;
+        info->netdevs[dev_idx].rx_bytes = device->rx_bytes;
+        info->netdevs[dev_idx].tx_errors = device->tx_errors;
+        for (j = 0; j < EC_RATE_COUNT; j++) {
+            info->netdevs[dev_idx].tx_frame_rates[j] =
+                device->tx_frame_rates[j];
+            info->netdevs[dev_idx].rx_frame_rates[j] =
+                device->rx_frame_rates[j];
+            info->netdevs[dev_idx].tx_byte_rates[j] =
+                device->tx_byte_rates[j];
+            info->netdevs[dev_idx].rx_byte_rates[j] =
+                device->rx_byte_rates[j];
+        }
+    }
+    info->num_netdevs = CONFIG_EC_MAX_NETDEVS;
+
+    info->tx_count = master->netdev_stats.tx_count;
+    info->rx_count = master->netdev_stats.rx_count;
+    info->tx_bytes = master->netdev_stats.tx_bytes;
+    info->rx_bytes = master->netdev_stats.rx_bytes;
+    for (j = 0; j < EC_RATE_COUNT; j++) {
+        info->tx_frame_rates[j] =
+            master->netdev_stats.tx_frame_rates[j];
+        info->rx_frame_rates[j] =
+            master->netdev_stats.rx_frame_rates[j];
+        info->tx_byte_rates[j] =
+            master->netdev_stats.tx_byte_rates[j];
+        info->rx_byte_rates[j] =
+            master->netdev_stats.rx_byte_rates[j];
+        info->loss_rates[j] =
+            master->netdev_stats.loss_rates[j];
+    }
+
+    // info->app_time = master->app_time;
+    // info->dc_ref_time = master->dc_ref_time;
+    // info->ref_clock = master->dc_ref_clock ? master->dc_ref_clock->autoinc_address : 0xffff;
+}
+
+static void ec_master_get_slave_info(ec_slave_t *slave, ec_cmd_slave_info_t *info)
+{
+    int i;
+
+    info->netdev_idx = slave->netdev_idx;
+    info->vendor_id = slave->sii.vendor_id;
+    info->product_code = slave->sii.product_code;
+    info->revision_number = slave->sii.revision_number;
+    info->serial_number = slave->sii.serial_number;
+    info->alias = slave->effective_alias;
+    info->boot_rx_mailbox_offset = slave->sii.boot_rx_mailbox_offset;
+    info->boot_rx_mailbox_size = slave->sii.boot_rx_mailbox_size;
+    info->boot_tx_mailbox_offset = slave->sii.boot_tx_mailbox_offset;
+    info->boot_tx_mailbox_size = slave->sii.boot_tx_mailbox_size;
+    info->std_rx_mailbox_offset = slave->sii.std_rx_mailbox_offset;
+    info->std_rx_mailbox_size = slave->sii.std_rx_mailbox_size;
+    info->std_tx_mailbox_offset = slave->sii.std_tx_mailbox_offset;
+    info->std_tx_mailbox_size = slave->sii.std_tx_mailbox_size;
+    info->mailbox_protocols = slave->sii.mailbox_protocols;
+    info->has_general = slave->sii.has_general;
+    info->coe_details = slave->sii.general.coe_details;
+    info->general_flags = slave->sii.general.flags;
+    info->current_on_ebus = slave->sii.general.current_on_ebus;
+    for (i = 0; i < EC_MAX_PORTS; i++) {
+        info->ports[i].desc = slave->ports[i].desc;
+        info->ports[i].link.link_up = slave->ports[i].link.link_up;
+        info->ports[i].link.loop_closed = slave->ports[i].link.loop_closed;
+        info->ports[i].link.signal_detected =
+            slave->ports[i].link.signal_detected;
+        info->ports[i].receive_time = slave->ports[i].receive_time;
+        if (slave->ports[i].next_slave) {
+            info->ports[i].next_slave =
+                slave->ports[i].next_slave->autoinc_address;
+        } else {
+            info->ports[i].next_slave = 0xffff;
+        }
+        info->ports[i].delay_to_next_dc = slave->ports[i].delay_to_next_dc;
+    }
+    info->base_fmmu_bit_operation = slave->base_fmmu_bit_operation;
+    info->base_dc_supported = slave->base_dc_supported;
+    info->base_dc_range = slave->base_dc_range;
+    info->has_dc_system_time = slave->has_dc_system_time;
+    info->transmission_delay = slave->transmission_delay;
+    info->current_state = slave->current_state;
+
+    info->group = ec_slave_get_sii_string(slave, slave->sii.general.groupidx);
+    info->image = ec_slave_get_sii_string(slave, slave->sii.general.imgidx);
+    info->order = ec_slave_get_sii_string(slave, slave->sii.general.orderidx);
+    info->name = ec_slave_get_sii_string(slave, slave->sii.general.nameidx);
+}
+
+void ec_master_cmd_master(ec_master_t *master)
+{
+    unsigned int dev_idx, j;
+    uint64_t lost;
+    double perc;
+    int colwidth = 8;
+    ec_cmd_master_info_t data;
+
+    ec_osal_mutex_take(master->scan_lock);
+    ec_master_get_master_info(master, &data);
+    ec_osal_mutex_give(master->scan_lock);
+
+    EC_LOG_RAW("Master%d\n", master->index);
+    EC_LOG_RAW("  Phase: ");
+    switch (data.phase) {
+        case 0:
+            EC_LOG_RAW("Waiting for device(s)...");
+            break;
+        case 1:
+            EC_LOG_RAW("Idle");
+            break;
+        case 2:
+            EC_LOG_RAW("Operation");
+            break;
+        default:
+            EC_LOG_RAW("???");
+    }
+
+    EC_LOG_RAW("\n");
+    EC_LOG_RAW("  Slaves: %u\n", data.slave_count);
+    EC_LOG_RAW("  Ethernet net devices:\n");
+
+    for (dev_idx = EC_NETDEV_MAIN; dev_idx < CONFIG_EC_MAX_NETDEVS; dev_idx++) {
+        EC_LOG_RAW("    %s: ", dev_idx == EC_NETDEV_MAIN ? "Main" : "Backup");
+        EC_LOG_RAW("%02x:%02x:%02x:%02x:%02x:%02x\n",
+                   data.netdevs[dev_idx].mac_addr[0],
+                   data.netdevs[dev_idx].mac_addr[1],
+                   data.netdevs[dev_idx].mac_addr[2],
+                   data.netdevs[dev_idx].mac_addr[3],
+                   data.netdevs[dev_idx].mac_addr[4],
+                   data.netdevs[dev_idx].mac_addr[5]);
+        EC_LOG_RAW("      Link: %s\n", data.netdevs[dev_idx].link_state ? "UP" : "DOWN");
+        EC_LOG_RAW("      Tx frames:   %llu\n", data.netdevs[dev_idx].tx_count);
+        EC_LOG_RAW("      Tx bytes:    %llu\n", data.netdevs[dev_idx].tx_bytes);
+        EC_LOG_RAW("      Rx frames:   %llu\n", data.netdevs[dev_idx].rx_count);
+        EC_LOG_RAW("      Rx bytes:    %llu\n", data.netdevs[dev_idx].rx_bytes);
+        EC_LOG_RAW("      Tx errors:   %llu\n", data.netdevs[dev_idx].tx_errors);
+
+        EC_LOG_RAW("      Tx frame rate [1/s]: ");
+        for (j = 0; j < EC_RATE_COUNT; j++) {
+            EC_LOG_RAW("%*.*f", colwidth, 0, data.netdevs[dev_idx].tx_frame_rates[j] / 1000.0);
+            if (j < EC_RATE_COUNT - 1)
+                EC_LOG_RAW(" ");
+        }
+        EC_LOG_RAW("\n      Tx rate [KByte/s]:   ");
+        for (j = 0; j < EC_RATE_COUNT; j++) {
+            EC_LOG_RAW("%*.*f", colwidth, 1, data.netdevs[dev_idx].tx_byte_rates[j] / 1024.0);
+            if (j < EC_RATE_COUNT - 1)
+                EC_LOG_RAW(" ");
+        }
+        EC_LOG_RAW("\n      Rx frame rate [1/s]: ");
+        for (j = 0; j < EC_RATE_COUNT; j++) {
+            EC_LOG_RAW("%*.*f", colwidth, 0, data.netdevs[dev_idx].rx_frame_rates[j] / 1000.0);
+            if (j < EC_RATE_COUNT - 1)
+                EC_LOG_RAW(" ");
+        }
+        EC_LOG_RAW("\n      Rx rate [KByte/s]:   ");
+        for (j = 0; j < EC_RATE_COUNT; j++) {
+            EC_LOG_RAW("%*.*f", colwidth, 1, data.netdevs[dev_idx].rx_byte_rates[j] / 1024.0);
+            if (j < EC_RATE_COUNT - 1)
+                EC_LOG_RAW(" ");
+        }
+        EC_LOG_RAW("\n");
+    }
+
+    lost = data.tx_count - data.rx_count;
+    if (lost == 1)
+        lost = 0;
+    EC_LOG_RAW("    Common:\n");
+    EC_LOG_RAW("      Tx frames:   %llu\n", data.tx_count);
+    EC_LOG_RAW("      Tx bytes:    %llu\n", data.tx_bytes);
+    EC_LOG_RAW("      Rx frames:   %llu\n", data.rx_count);
+    EC_LOG_RAW("      Rx bytes:    %llu\n", data.rx_bytes);
+    EC_LOG_RAW("      Lost frames: %llu\n", lost);
+
+    EC_LOG_RAW("      Tx frame rate [1/s]: ");
+    for (j = 0; j < EC_RATE_COUNT; j++) {
+        EC_LOG_RAW("%*.*f", colwidth, 0, data.tx_frame_rates[j] / 1000.0);
+        if (j < EC_RATE_COUNT - 1)
+            EC_LOG_RAW(" ");
+    }
+    EC_LOG_RAW("\n      Tx rate [KByte/s]:   ");
+    for (j = 0; j < EC_RATE_COUNT; j++) {
+        EC_LOG_RAW("%*.*f", colwidth, 1, data.tx_byte_rates[j] / 1024.0);
+        if (j < EC_RATE_COUNT - 1)
+            EC_LOG_RAW(" ");
+    }
+    EC_LOG_RAW("\n      Rx frame rate [1/s]: ");
+    for (j = 0; j < EC_RATE_COUNT; j++) {
+        EC_LOG_RAW("%*.*f", colwidth, 0, data.rx_frame_rates[j] / 1000.0);
+        if (j < EC_RATE_COUNT - 1)
+            EC_LOG_RAW(" ");
+    }
+    EC_LOG_RAW("\n      Rx rate [KByte/s]:   ");
+    for (j = 0; j < EC_RATE_COUNT; j++) {
+        EC_LOG_RAW("%*.*f", colwidth, 1, data.rx_byte_rates[j] / 1024.0);
+        if (j < EC_RATE_COUNT - 1)
+            EC_LOG_RAW(" ");
+    }
+    EC_LOG_RAW("\n      Loss rate [1/s]:     ");
+    for (j = 0; j < EC_RATE_COUNT; j++) {
+        EC_LOG_RAW("%*.*f", colwidth, 0, data.loss_rates[j] / 1000.0);
+        if (j < EC_RATE_COUNT - 1)
+            EC_LOG_RAW(" ");
+    }
+    EC_LOG_RAW("\n      Frame loss [%%]:      ");
+    for (j = 0; j < EC_RATE_COUNT; j++) {
+        perc = 0.0;
+        if (data.tx_frame_rates[j])
+            perc = 100.0 * data.loss_rates[j] / data.tx_frame_rates[j];
+        EC_LOG_RAW("%*.*f", colwidth, 1, perc);
+        if (j < EC_RATE_COUNT - 1)
+            EC_LOG_RAW(" ");
+    }
+    EC_LOG_RAW("\n");
+}
+
+static void ec_cmd_show_slave_detail(ec_master_t *master, uint32_t slave_idx)
+{
+    unsigned int port_idx;
+    ec_slave_t *slave;
+    ec_cmd_slave_info_t data;
+
+    if (slave_idx >= master->slave_count) {
+        EC_LOG_RAW("No slaves found\n");
+        return;
+    }
+
+    slave = &master->slaves[slave_idx];
+
+    ec_osal_mutex_take(master->scan_lock);
+    ec_master_get_slave_info(slave, &data);
+    ec_osal_mutex_give(master->scan_lock);
+
+    EC_LOG_RAW("=== Master %d, Slave %d ===\n", master->index, slave_idx);
+
+    if (data.alias != 0) {
+        EC_LOG_RAW("Alias: 0x%04x\n", data.alias);
+    }
+
+    EC_LOG_RAW("Device: %s\n", master->netdev[slave->netdev_idx]->name);
+    EC_LOG_RAW("State: %s\n", ec_slave_state_string(data.current_state));
+
+    EC_LOG_RAW("Identity:\n");
+    EC_LOG_RAW("  Vendor Id:       0x%08x\n", data.vendor_id);
+    EC_LOG_RAW("  Product code:    0x%08x\n", data.product_code);
+    EC_LOG_RAW("  Revision number: 0x%08x\n", data.revision_number);
+    EC_LOG_RAW("  Serial number:   0x%08x\n", data.serial_number);
+
+    EC_LOG_RAW("DL information:\n");
+    EC_LOG_RAW("  FMMU bit operation: %s\n", (data.base_fmmu_bit_operation ? "yes" : "no"));
+    EC_LOG_RAW("  Distributed clocks: ");
+
+    if (data.base_dc_supported) {
+        if (data.has_dc_system_time) {
+            EC_LOG_RAW("yes, ");
+            if (data.base_dc_range) {
+                EC_LOG_RAW("64 bit\n");
+            } else {
+                EC_LOG_RAW("32 bit\n");
+            }
+            EC_LOG_RAW("  DC system time transmission delay: %d ns\n",
+                       data.transmission_delay);
+        } else {
+            EC_LOG_RAW("yes, delay measurement only\n");
+        }
+    } else {
+        EC_LOG_RAW("no\n");
+    }
+
+    EC_LOG_RAW("Port  Type  Link  Loop    Signal  NextSlave");
+    if (data.base_dc_supported) {
+        EC_LOG_RAW("  RxTime [ns]  Diff [ns]   NextDc [ns]");
+    }
+    EC_LOG_RAW("\n");
+
+    for (port_idx = 0; port_idx < EC_MAX_PORTS; port_idx++) {
+        EC_LOG_RAW("   %d  %-4s  %-4s  %-6s  %-6s  ",
+                   port_idx,
+                   ec_port_desc_string(data.ports[port_idx].desc),
+                   (data.ports[port_idx].link.link_up ? "up" : "down"),
+                   (data.ports[port_idx].link.loop_closed ? "closed" : "open"),
+                   (data.ports[port_idx].link.signal_detected ? "yes" : "no"));
+
+        if (data.ports[port_idx].next_slave != 0xffff) {
+            EC_LOG_RAW("%-9d", data.ports[port_idx].next_slave);
+        } else {
+            EC_LOG_RAW("%-9s", "-");
+        }
+
+        if (data.base_dc_supported) {
+            if (!data.ports[port_idx].link.loop_closed) {
+                EC_LOG_RAW("  %11u  %10d  %10d",
+                           data.ports[port_idx].receive_time,
+                           data.ports[port_idx].receive_time - data.ports[0].receive_time,
+                           data.ports[port_idx].delay_to_next_dc);
+            } else {
+                EC_LOG_RAW("  %11s  %10s  %10s", "-", "-", "-");
+            }
+        }
+
+        EC_LOG_RAW("\n");
+    }
+
+    if (data.mailbox_protocols) {
+        EC_LOG_RAW("Mailboxes:\n");
+        EC_LOG_RAW("  Bootstrap RX: 0x%04x/%d, TX: 0x%04x/%d\n",
+                   data.boot_rx_mailbox_offset,
+                   data.boot_rx_mailbox_size,
+                   data.boot_tx_mailbox_offset,
+                   data.boot_tx_mailbox_size);
+        EC_LOG_RAW("  Standard  RX: 0x%04x/%d, TX: 0x%04x/%d\n",
+                   data.std_rx_mailbox_offset,
+                   data.std_rx_mailbox_size,
+                   data.std_tx_mailbox_offset,
+                   data.std_tx_mailbox_size);
+
+        EC_LOG_RAW("  Supported protocols: %s\n", ec_mbox_protocol_string(data.mailbox_protocols));
+    }
+
+    if (data.has_general) {
+        EC_LOG_RAW("General:\n");
+        EC_LOG_RAW("  Group: %s\n", data.group ? data.group : "");
+        EC_LOG_RAW("  Image name: %s\n", data.image ? data.image : "");
+        EC_LOG_RAW("  Order number: %s\n", data.order ? data.order : "");
+        EC_LOG_RAW("  Device name: %s\n", data.name ? data.name : "");
+
+        if (data.mailbox_protocols & EC_MBXPROT_COE) {
+            EC_LOG_RAW("  CoE details:\n");
+            EC_LOG_RAW("    Enable SDO: %s\n",
+                       (data.coe_details.enable_sdo ? "yes" : "no"));
+            EC_LOG_RAW("    Enable SDO Info: %s\n",
+                       (data.coe_details.enable_sdo_info ? "yes" : "no"));
+            EC_LOG_RAW("    Enable PDO Assign: %s\n",
+                       (data.coe_details.enable_pdo_assign ? "yes" : "no"));
+            EC_LOG_RAW("    Enable PDO Configuration: %s\n",
+                       (data.coe_details.enable_pdo_configuration ? "yes" : "no"));
+            EC_LOG_RAW("    Enable Upload at startup: %s\n",
+                       (data.coe_details.enable_upload_at_startup ? "yes" : "no"));
+            EC_LOG_RAW("    Enable SDO complete access: %s\n",
+                       (data.coe_details.enable_sdo_complete_access ? "yes" : "no"));
+        }
+
+        EC_LOG_RAW("  Flags:\n");
+        EC_LOG_RAW("    Enable SafeOp: %s\n",
+                   (data.general_flags.enable_safeop ? "yes" : "no"));
+        EC_LOG_RAW("    Enable notLRW: %s\n",
+                   (data.general_flags.enable_not_lrw ? "yes" : "no"));
+        EC_LOG_RAW("  Current consumption: %d mA\n", data.current_on_ebus);
+    }
+
+    EC_LOG_RAW("\n");
+}
+
+static void ec_cmd_show_slave_simple(ec_master_t *master, uint32_t slave_idx)
+{
+    ec_slave_t *slave;
+    ec_cmd_slave_info_t data;
+
+    if (slave_idx >= master->slave_count) {
+        EC_LOG_RAW("No slaves found\n");
+        return;
+    }
+
+    slave = &master->slaves[slave_idx];
+
+    ec_osal_mutex_take(master->scan_lock);
+    ec_master_get_slave_info(slave, &data);
+    ec_osal_mutex_give(master->scan_lock);
+
+    EC_LOG_RAW("%-3u  %u:%04x   %-13s %s\n",
+               master->index,
+               slave_idx,
+               slave->autoinc_address,
+               ec_state_string(slave->current_state, 0),
+               ec_alstatus_string(slave->alstatus_code));
+}
+
+static void ec_cmd_show_slave_pdos(ec_master_t *master, uint32_t slave_idx)
+{
+    if (slave_idx >= master->slave_count) {
+        EC_LOG_RAW("No slaves found\n");
+        return;
+    }
+
+    EC_LOG_RAW("=== Master %d, Slave %d ===\n", master->index, slave_idx);
+
+    for (uint8_t i = 0; i < master->slaves[slave_idx].sm_count; i++) {
+        EC_LOG_RAW("SM%u: physaddr 0x%04x, length 0x%04x, control 0x%02x, enable %d\r\n",
+                   i,
+                   master->slaves[slave_idx].sm_info[i].physical_start_address,
+                   master->slaves[slave_idx].sm_info[i].length,
+                   master->slaves[slave_idx].sm_info[i].control,
+                   master->slaves[slave_idx].sm_info[i].enable);
+
+        // if sm is process data output, print rxpdo info
+        if (i == EC_SM_INDEX_PROCESS_DATA_OUTPUT) {
+            for (uint16_t j = 0; j < master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.count; j++) {
+                EC_LOG_RAW("\tRxPDO 0x%04x\r\n", master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.entry[j]);
+
+                for (uint16_t k = 0; k < master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_mapping[j].count; k++) {
+                    EC_LOG_RAW("\t\tPDO entry 0x%04x:0x%02x, bitlen 0x%02x\r\n",
+                               master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_mapping[j].entry[k] >> 16 & 0xffff,
+                               master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_mapping[j].entry[k] >> 8 & 0xff,
+                               master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_mapping[j].entry[k] >> 0 & 0xff);
+                }
+            }
+        }
+
+        // if sm is process data input, print txpdo info
+        if (i == EC_SM_INDEX_PROCESS_DATA_INPUT) {
+            for (uint16_t j = 0; j < master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.count; j++) {
+                EC_LOG_RAW("\tTxPDO 0x%04x\r\n", master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.entry[j]);
+
+                for (uint16_t k = 0; k < master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_mapping[j].count; k++) {
+                    EC_LOG_RAW("\t\tPDO entry 0x%04x:0x%02x, bitlen 0x%02x\r\n",
+                               master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_mapping[j].entry[k] >> 16 & 0xffff,
+                               master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_mapping[j].entry[k] >> 8 & 0xff,
+                               master->slaves[slave_idx].sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_mapping[j].entry[k] >> 0 & 0xff);
+                }
+            }
+        }
+    }
+}
+
+static void ec_cmd_slave_state_request(ec_master_t *master, uint32_t slave_idx, ec_slave_state_t state)
+{
+    if (slave_idx >= master->slave_count) {
+        EC_LOG_RAW("No slaves found\n");
+        return;
+    }
+
+    ec_slave_t *slave = &master->slaves[slave_idx];
+    slave->requested_state = state;
+}
+
+static int hex_char_to_num(char c)
+{
+    if (c >= '0' && c <= '9') {
+        return c - '0';
+    } else if (c >= 'a' && c <= 'f') {
+        return c - 'a' + 10;
+    } else if (c >= 'A' && c <= 'F') {
+        return c - 'A' + 10;
+    }
+    return -1;
+}
+
+static int parse_hex_string(const char *hex_str, uint8_t *output, uint32_t max_len)
+{
+    const char *ptr = hex_str;
+    uint32_t byte_count = 0;
+
+    if (strlen(hex_str) >= 2 && hex_str[0] == '0' &&
+        (hex_str[1] == 'x' || hex_str[1] == 'X')) {
+        ptr = hex_str + 2;
+    }
+
+    uint32_t str_len = strlen(ptr);
+    if (str_len % 2) {
+        EC_LOG_RAW("Hex string length must be even\n");
+        return -1;
+    }
+
+    while (*ptr && *(ptr + 1) && byte_count < max_len) {
+        int high = hex_char_to_num(*ptr);
+        int low = hex_char_to_num(*(ptr + 1));
+
+        if (high < 0 || low < 0) {
+            EC_LOG_RAW("Invalid hex character: %c%c\n", *ptr, *(ptr + 1));
+            return -1;
+        }
+
+        output[byte_count++] = (uint8_t)((high << 4) | low);
+        ptr += 2;
+    }
+
+    if (*ptr) {
+        if (byte_count >= max_len) {
+            EC_LOG_RAW("Hex string too long, maximum %u bytes\n", max_len);
+            return -1;
+        }
+        EC_LOG_RAW("Incomplete hex pair at end of string\n");
+        return -1;
+    }
+
+    return byte_count;
+}
+
+int ethercat(int argc, const char **argv)
+{
+    if (global_cmd_master == NULL) {
+        EC_LOG_RAW("No master configured\n");
+        return -1;
+    }
+
+    if (argc < 2) {
+        ec_master_cmd_show_help();
+        return -1;
+    }
+
+    if (strcmp(argv[1], "help") == 0) {
+        ec_master_cmd_show_help();
+        return 0;
+    } else if (strcmp(argv[1], "master") == 0) {
+        ec_master_cmd_master(global_cmd_master);
+        return 0;
+    } else if (strcmp(argv[1], "slaves") == 0) {
+        // ethercat slaves
+        if (argc == 2) {
+            for (uint32_t i = 0; i < global_cmd_master->slave_count; i++) {
+                ec_cmd_show_slave_simple(global_cmd_master, i);
+            }
+            return 0;
+        } else if (argc >= 4 && strcmp(argv[2], "-p") == 0) {
+            // ethercat slaves -p [x] [-v]
+            int show_detail = 0;
+            if (argc == 5) {
+                if (argc == 5 && strcmp(argv[4], "-v") == 0) {
+                    show_detail = 1;
+                }
+            }
+
+            if (show_detail) {
+                ec_cmd_show_slave_detail(global_cmd_master, atoi(argv[3]));
+            } else {
+                ec_cmd_show_slave_simple(global_cmd_master, atoi(argv[3]));
+            }
+
+            return 0;
+        } else if (argc == 3 && strcmp(argv[2], "-v") == 0) {
+            // ethercat slaves -v
+            for (uint32_t i = 0; i < global_cmd_master->slave_count; i++) {
+                ec_cmd_show_slave_detail(global_cmd_master, i);
+            }
+
+            return 0;
+        } else {
+        }
+    } else if (strcmp(argv[1], "pdos") == 0) {
+        // ethercat pdos
+        if (argc == 2) {
+            for (uint32_t i = 0; i < global_cmd_master->slave_count; i++) {
+                ec_cmd_show_slave_pdos(global_cmd_master, i);
+            }
+            return 0;
+        } else if (argc == 4 && strcmp(argv[2], "-p") == 0) {
+            // ethercat pdos -p [x]
+            ec_cmd_show_slave_pdos(global_cmd_master, atoi(argv[3]));
+            return 0;
+        } else {
+        }
+    } else if (argc >= 3 && strcmp(argv[1], "states") == 0) {
+        // ethercat states
+        if (argc == 3) {
+            // ethercat states [state]
+            for (uint32_t i = 0; i < global_cmd_master->slave_count; i++) {
+                ec_cmd_slave_state_request(global_cmd_master, i, strtoul(argv[4], NULL, 16));
+            }
+            return 0;
+        } else if (argc == 5 && strcmp(argv[2], "-p") == 0) {
+            // ethercat states -p [x] [state]
+            ec_cmd_slave_state_request(global_cmd_master, atoi(argv[3]), strtoul(argv[4], NULL, 16));
+            return 0;
+        } else {
+        }
+    } else if (argc >= 2 && strcmp(argv[1], "wc") == 0) {
+        // ethercat wc
+        if (argc == 2) {
+            // ethercat wc
+            EC_LOG_RAW("Master %d working counter(actual/expect): %u/%u\n",
+                       global_cmd_master->index,
+                       global_cmd_master->actual_working_counter,
+                       global_cmd_master->expected_working_counter);
+
+            for (uint32_t i = 0; i < global_cmd_master->slave_count; i++) {
+                EC_LOG_RAW("%-3u  %u:%04x         (actual/expect): %u/%u\n",
+                           global_cmd_master->index,
+                           i,
+                           global_cmd_master->slaves[i].autoinc_address,
+                           global_cmd_master->slaves[i].actual_working_counter,
+                           global_cmd_master->slaves[i].expected_working_counter);
+            }
+            return 0;
+        } else {
+        }
+    } else if (argc >= 5 && strcmp(argv[1], "coe_read") == 0) {
+        // ethercat coe_read -p [slave_idx] [index] [subindex]
+        static ec_datagram_t datagram;
+        static uint8_t output_buffer[512];
+        uint32_t actual_size;
+        int ret;
+
+        uint32_t slave_idx = atoi(argv[3]);
+
+        ec_datagram_init(&datagram, 512);
+        ret = ec_coe_upload(global_cmd_master,
+                            slave_idx,
+                            &datagram,
+                            strtoul(argv[4], NULL, 16),
+                            argc >= 6 ? strtoul(argv[5], NULL, 16) : 0x00,
+                            output_buffer,
+                            sizeof(output_buffer),
+                            &actual_size,
+                            argc >= 6 ? false : true);
+        if (ret < 0) {
+            EC_SLAVE_LOG_ERR("Slave %u coe_read failed: %d\n", slave_idx, ret);
+        } else {
+            ec_hexdump(output_buffer, actual_size);
+        }
+        ec_datagram_clear(&datagram);
+
+        return 0;
+    } else if (argc >= 7 && strcmp(argv[1], "coe_write") == 0) {
+        // ethercat coe_write -p [slave_idx] [index] [subindex] [u32data]
+        static ec_datagram_t datagram;
+        uint32_t u32data;
+        uint32_t size;
+        int ret;
+
+        uint32_t slave_idx = atoi(argv[3]);
+        u32data = strtoul(argv[6], NULL, 16);
+
+        if (u32data < 0xff)
+            size = 1;
+        else if (u32data < 0xffff)
+            size = 2;
+        else
+            size = 4;
+
+        ec_datagram_init(&datagram, 512);
+        ret = ec_coe_download(global_cmd_master,
+                              slave_idx,
+                              &datagram,
+                              strtoul(argv[4], NULL, 16),
+                              strtoul(argv[5], NULL, 16),
+                              &u32data,
+                              size,
+                              false);
+        if (ret < 0) {
+            EC_SLAVE_LOG_ERR("Slave %u coe_write failed: %d\n", slave_idx, ret);
+        } else {
+            EC_LOG_RAW("Slave %u coe write success\n", slave_idx);
+        }
+        ec_datagram_clear(&datagram);
+        return 0;
+    } else if (argc >= 4 && strcmp(argv[1], "sii_read") == 0) {
+        // ethercat sii_read -p [slave_idx]
+        uint32_t slave_idx = atoi(argv[3]);
+        if (slave_idx >= global_cmd_master->slave_count) {
+            EC_LOG_RAW("No slaves found\n");
+            return -1;
+        }
+
+        ec_hexdump(global_cmd_master->slaves[slave_idx].sii_image,
+                   global_cmd_master->slaves[slave_idx].sii_nwords * 2);
+
+        return 0;
+    } else if (argc >= 5 && strcmp(argv[1], "sii_write") == 0) {
+        // ethercat sii_write -p [slave_idx]
+        int ret;
+        static ec_datagram_t datagram;
+        extern unsigned char cherryecat_eepromdata[2048];
+
+        ec_datagram_init(&datagram, 4096);
+
+        uint32_t slave_idx = atoi(argv[3]);
+
+        ec_osal_mutex_take(global_cmd_master->scan_lock);
+        ret = ec_sii_write(global_cmd_master, slave_idx, &datagram, 0x0000, (const uint16_t *)cherryecat_eepromdata, sizeof(cherryecat_eepromdata));
+        ec_osal_mutex_give(global_cmd_master->scan_lock);
+
+        if (ret < 0) {
+            EC_SLAVE_LOG_ERR("Slave %u sii_write failed: %d\n", slave_idx, ret);
+        } else {
+            EC_LOG_RAW("Slave %u sii write success\n", slave_idx);
+        }
+
+        ec_datagram_clear(&datagram);
+        return 0;
+    } else if (argc >= 2 && strcmp(argv[1], "pdo_read") == 0) {
+        // ethercat pdo_read
+        if (argc == 2) {
+            for (uint32_t count = 0; count < 10; count++) {
+                EC_LOG_RAW("\r");
+                for (uint32_t i = 0; i < global_cmd_master->actual_pdo_size; i++) {
+                    EC_LOG_RAW("%02x ", global_cmd_master->pdo_buffer[EC_NETDEV_MAIN][i]);
+                }
+                fflush(stdout);
+                if (count < 9) {
+                    ec_osal_msleep(1000);
+                }
+            }
+            EC_LOG_RAW("\n");
+            return 0;
+        } else if (argc == 4 && strcmp(argv[2], "-p") == 0) {
+            // ethercat pdo_read -p [slave_idx]
+            uint32_t slave_idx = atoi(argv[3]);
+            if (slave_idx >= global_cmd_master->slave_count) {
+                EC_LOG_RAW("No slaves found\n");
+                return -1;
+            }
+            uint8_t *buffer = ec_master_get_slave_domain_input(global_cmd_master, slave_idx);
+            uint32_t data_size = ec_master_get_slave_domain_isize(global_cmd_master, slave_idx);
+
+            for (uint32_t count = 0; count < 10; count++) {
+                EC_LOG_RAW("\r");
+                for (uint32_t i = 0; i < data_size; i++) {
+                    EC_LOG_RAW("%02x ", buffer[i]);
+                }
+                fflush(stdout);
+                if (count < 9) {
+                    ec_osal_msleep(1000);
+                }
+            }
+            EC_LOG_RAW("\n");
+            return 0;
+        } else {
+        }
+    } else if (argc >= 4 && strcmp(argv[1], "pdo_write") == 0) {
+        // ethercat pdo_write -p [slave_idx] [offset] [hexdata]
+        uint8_t hexdata[256];
+        uint32_t offset;
+        int size;
+
+        if (argc >= 6 && strcmp(argv[2], "-p") == 0) {
+            uint32_t slave_idx = atoi(argv[3]);
+            if (slave_idx >= global_cmd_master->slave_count) {
+                EC_LOG_RAW("No slaves found\n");
+                return -1;
+            }
+
+            offset = strtoul(argv[4], NULL, 16);
+
+            size = parse_hex_string(argv[5], hexdata, sizeof(hexdata));
+            if (size < 0) {
+                return -1;
+            }
+
+            uint8_t *buffer = ec_master_get_slave_domain_output(global_cmd_master, slave_idx);
+            if (buffer) {
+                EC_LOG_RAW("Slave %u pdo write offset 0x%04x, size %u\n",
+                           slave_idx, offset, size);
+                ec_memcpy(&buffer[offset], hexdata, size);
+            }
+            return 0;
+        } else {
+            offset = strtoul(argv[2], NULL, 16);
+
+            size = parse_hex_string(argv[3], hexdata, sizeof(hexdata));
+            if (size < 0) {
+                return -1;
+            }
+
+            EC_LOG_RAW("Slaves pdo write offset 0x%04x, size %u\n",
+                       offset, size);
+
+            for (uint32_t slave_idx = 0; slave_idx < global_cmd_master->slave_count; slave_idx++) {
+                uint8_t *buffer = ec_master_get_slave_domain_output(global_cmd_master, slave_idx);
+                if (buffer) {
+                    ec_memcpy(&buffer[offset], hexdata, size);
+                }
+            }
+            return 0;
+        }
+    }
+#ifdef CONFIG_EC_FOE
+    else if (argc >= 7 && strcmp(argv[1], "foe_write") == 0) {
+        // ethercat foe_write -p [slave_idx] [filename] [password] [hexdata]
+        uint8_t hexdata[256];
+        uint32_t size;
+        int ret;
+        uint32_t slave_idx = atoi(argv[3]);
+        const char *filename = argv[4];
+        uint32_t password = strtoul(argv[5], NULL, 16);
+
+        size = parse_hex_string(argv[6], hexdata, sizeof(hexdata));
+        if (size < 0) {
+            return -1;
+        }
+        static ec_datagram_t datagram;
+
+        ec_datagram_init(&datagram, 4096);
+
+        EC_SLAVE_LOG_INFO("Slave %u foe write file %s, password: 0x%08x, size %u\n", slave_idx, filename, password, size);
+
+        ec_osal_mutex_take(global_cmd_master->scan_lock);
+        ret = ec_foe_write(global_cmd_master, slave_idx, &datagram, filename, password, hexdata, size);
+        ec_osal_mutex_give(global_cmd_master->scan_lock);
+
+        if (ret < 0) {
+            EC_SLAVE_LOG_ERR("Slave %u foe_write failed: %d\n", slave_idx, ret);
+        } else {
+            EC_LOG_RAW("Slave %u foe write success\n", slave_idx);
+        }
+
+        ec_datagram_clear(&datagram);
+        return 0;
+    } else if (argc >= 6 && strcmp(argv[1], "foe_read") == 0) {
+        // ethercat foe_read -p [slave_idx] [filename] [password]
+        uint8_t hexdata[256];
+        uint32_t size;
+        int ret;
+        uint32_t slave_idx = atoi(argv[3]);
+        const char *filename = argv[4];
+        uint32_t password = strtoul(argv[5], NULL, 16);
+
+        EC_SLAVE_LOG_INFO("Slave %u foe read file %s, password: 0x%08x\n", slave_idx, filename, password);
+
+        static ec_datagram_t datagram;
+
+        ec_datagram_init(&datagram, 4096);
+
+        ec_osal_mutex_take(global_cmd_master->scan_lock);
+        ret = ec_foe_read(global_cmd_master, slave_idx, &datagram, filename, password, hexdata, sizeof(hexdata), &size);
+        ec_osal_mutex_give(global_cmd_master->scan_lock);
+
+        if (ret < 0) {
+            EC_SLAVE_LOG_ERR("Slave %u foe_read failed: %d\n", slave_idx, ret);
+        } else {
+            ec_hexdump(hexdata, size);
+        }
+
+        ec_datagram_clear(&datagram);
+        return 0;
+    }
+#endif
+    else if (argc >= 3 && strcmp(argv[1], "timediff") == 0) {
+        if (strcmp(argv[2], "-s") == 0) {
+            uintptr_t flags;
+
+            flags = ec_osal_enter_critical_section();
+            global_cmd_master->systime_diff_enable = true;
+            global_cmd_master->curr_systime_diff = 0;
+            global_cmd_master->min_systime_diff = 0xffffffff;
+            global_cmd_master->max_systime_diff = 0;
+            global_cmd_master->systime_diff_count = 0;
+            global_cmd_master->total_systime_diff = 0;
+            ec_osal_leave_critical_section(flags);
+
+        } else if (strcmp(argv[2], "-d") == 0) {
+            uintptr_t flags;
+
+            flags = ec_osal_enter_critical_section();
+            global_cmd_master->systime_diff_enable = false;
+            ec_osal_leave_critical_section(flags);
+        } else if (strcmp(argv[2], "-v") == 0) {
+            for (uint32_t i = 0; i < 10; i++) {
+                EC_LOG_RAW("System Time Diff curr = %d, min = %d, max = %d, avg = %d ns\n",
+                           global_cmd_master->curr_systime_diff,
+                           global_cmd_master->min_systime_diff,
+                           global_cmd_master->max_systime_diff,
+                           global_cmd_master->total_systime_diff / global_cmd_master->systime_diff_count);
+                ec_osal_msleep(1000);
+            }
+        }
+        return 0;
+#ifdef CONFIG_EC_PERF_ENABLE
+    } else if (strcmp(argv[1], "perf") == 0) {
+        if (argc >= 4 && strcmp(argv[2], "-s") == 0) {
+            ec_perf_init(&global_cmd_master->perf, atoi(argv[3]));
+            return 0;
+        } else if (argc >= 3 && strcmp(argv[2], "-v") == 0) {
+            ec_perf_print_statistics(&global_cmd_master->perf);
+            return 0;
+        }
+#endif
+    } else {
+    }
+
+    EC_LOG_RAW("Invalid command: %s\n", argv[1]);
+    ec_master_cmd_show_help();
+    return -1;
+}
+
+#ifdef FINSH_USING_MSH
+#include <finsh.h>
+MSH_CMD_EXPORT(ethercat, cherryecat command line tool);
+#endif
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_coe.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_coe.c
new file mode 100644
index 00000000..c5ec0ec4
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_coe.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+typedef struct __PACKED {
+    ec_coe_header_t coe_header;
+    ec_sdo_header_common_t sdo_header;
+    uint16_t index;
+    uint8_t subindex;
+    uint8_t data[4];
+} ec_coe_download_common_header_t;
+
+typedef struct __PACKED {
+    ec_coe_header_t coe_header;
+    ec_sdo_header_segment_t sdo_header;
+} ec_coe_download_segment_header_t;
+
+typedef ec_coe_download_common_header_t ec_coe_upload_common_header_t;
+typedef ec_coe_download_segment_header_t ec_coe_upload_segment_header_t;
+
+/** CoE download request header size.
+ */
+#define EC_COE_DOWN_REQ_HEADER_SIZE (sizeof(ec_coe_download_common_header_t))
+
+/** CoE upload request header size.
+ */
+#define EC_COE_UP_REQ_HEADER_SIZE (sizeof(ec_coe_upload_common_header_t))
+
+/** CoE download segment request header size.
+ */
+#define EC_COE_DOWN_SEG_REQ_HEADER_SIZE (sizeof(ec_coe_download_segment_header_t))
+
+/** CoE upload segment request header size.
+ */
+#define EC_COE_UP_SEG_REQ_HEADER_SIZE (sizeof(ec_coe_upload_segment_header_t))
+
+/** Minimum size of download segment.
+ */
+#define EC_COE_DOWN_SEG_MIN_DATA_SIZE 7
+
+#define EC_COE_TIMEOUT_US (1000 * 1000) /* 1s */
+
+static int ec_coe_download_expedited(ec_master_t *master,
+                                     uint16_t slave_index,
+                                     ec_datagram_t *datagram,
+                                     uint16_t index,
+                                     uint8_t subindex,
+                                     const void *buf,
+                                     uint32_t size,
+                                     bool complete_access)
+{
+    uint8_t *data;
+    uint8_t mbox_proto;
+    uint32_t recv_size;
+    ec_coe_download_common_header_t *download_common;
+    int ret;
+
+    data = ec_mailbox_fill_send(master, slave_index, datagram, EC_MBOX_TYPE_COE, EC_COE_DOWN_REQ_HEADER_SIZE);
+
+    download_common = (ec_coe_download_common_header_t *)data;
+    download_common->coe_header.number = 0;
+    download_common->coe_header.reserved = 0;
+    download_common->coe_header.service = EC_COE_SERVICE_SDO_REQUEST;
+    download_common->sdo_header.size_indicator = 1;
+    download_common->sdo_header.transfertype = 1; // expedited
+    download_common->sdo_header.data_set_size = 4 - size;
+    download_common->sdo_header.complete_access = complete_access ? 1 : 0;
+    download_common->sdo_header.command = EC_COE_REQUEST_DOWNLOAD;
+
+    download_common->index = index;
+    download_common->subindex = complete_access ? 0x00 : subindex;
+
+    ec_memcpy(download_common->data, buf, size);
+    memset(download_common->data + size, 0x00, 4 - size);
+    ret = ec_mailbox_send(master, slave_index, datagram);
+    if (ret < 0) {
+        return ret;
+    }
+
+    ret = ec_mailbox_receive(master, slave_index, datagram, &mbox_proto, &recv_size, EC_COE_TIMEOUT_US);
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (mbox_proto != EC_MBOX_TYPE_COE) {
+        return -EC_ERR_COE_TYPE;
+    }
+
+    if (recv_size < 6) {
+        return -EC_ERR_COE_SIZE;
+    }
+
+    data = datagram->data + EC_MBOX_HEADER_SIZE;
+
+    if (EC_READ_U16(data) >> 12 == EC_COE_SERVICE_SDO_REQUEST &&
+        EC_READ_U8(data + 2) >> 5 == EC_COE_REQUEST_ABORT) {
+        EC_SLAVE_LOG_ERR("Slave %u SDO abort code: 0x%08x (%s)\n", slave_index, EC_READ_U32(data + 6), ec_sdo_abort_string(EC_READ_U32(data + 6)));
+        return -EC_ERR_COE_ABORT;
+    }
+
+    if (EC_READ_U16(data) >> 12 != EC_COE_SERVICE_SDO_RESPONSE ||
+        EC_READ_U8(data + 2) >> 5 != EC_COE_RESPONSE_DOWNLOAD ||
+        EC_READ_U16(data + 3) != index ||
+        EC_READ_U8(data + 5) != subindex) {
+        return -EC_ERR_COE_REQUEST;
+    }
+
+    return 0;
+}
+
+static int ec_coe_download_common(ec_master_t *master,
+                                  uint16_t slave_index,
+                                  ec_datagram_t *datagram,
+                                  uint16_t index,
+                                  uint8_t subindex,
+                                  const void *buf,
+                                  uint32_t size,
+                                  bool complete_access)
+{
+    uint8_t *data;
+    uint8_t mbox_proto;
+    uint32_t recv_size;
+    ec_coe_download_common_header_t *download_common;
+    int ret;
+
+    data = ec_mailbox_fill_send(master, slave_index, datagram, EC_MBOX_TYPE_COE, size + EC_COE_DOWN_REQ_HEADER_SIZE);
+
+    download_common = (ec_coe_download_common_header_t *)data;
+    download_common->coe_header.number = 0;
+    download_common->coe_header.reserved = 0;
+    download_common->coe_header.service = EC_COE_SERVICE_SDO_REQUEST;
+    download_common->sdo_header.size_indicator = 1;
+    download_common->sdo_header.transfertype = 0; // normal
+    download_common->sdo_header.data_set_size = 0;
+    download_common->sdo_header.complete_access = complete_access ? 1 : 0;
+    download_common->sdo_header.command = EC_COE_REQUEST_DOWNLOAD;
+
+    download_common->index = index;
+    download_common->subindex = complete_access ? 0x00 : subindex;
+
+    ec_memcpy(download_common->data, &size, 4);
+    ec_memcpy(data + EC_COE_DOWN_REQ_HEADER_SIZE, buf, size);
+    ret = ec_mailbox_send(master, slave_index, datagram);
+    if (ret < 0) {
+        return ret;
+    }
+
+    ret = ec_mailbox_receive(master, slave_index, datagram, &mbox_proto, &recv_size, EC_COE_TIMEOUT_US);
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (mbox_proto != EC_MBOX_TYPE_COE) {
+        return -EC_ERR_COE_TYPE;
+    }
+
+    if (recv_size < 6) {
+        return -EC_ERR_COE_SIZE;
+    }
+
+    data = datagram->data + EC_MBOX_HEADER_SIZE;
+
+    if (EC_READ_U16(data) >> 12 == EC_COE_SERVICE_SDO_REQUEST &&
+        EC_READ_U8(data + 2) >> 5 == EC_COE_REQUEST_ABORT) {
+        EC_SLAVE_LOG_ERR("Slave %u SDO abort code: 0x%08x (%s)\n", slave_index, EC_READ_U32(data + 6), ec_sdo_abort_string(EC_READ_U32(data + 6)));
+        return -EC_ERR_COE_ABORT;
+    }
+
+    if (EC_READ_U16(data) >> 12 != EC_COE_SERVICE_SDO_RESPONSE ||
+        EC_READ_U8(data + 2) >> 5 != EC_COE_RESPONSE_DOWNLOAD ||
+        EC_READ_U16(data + 3) != index ||
+        EC_READ_U8(data + 5) != subindex) {
+        return -EC_ERR_COE_REQUEST;
+    }
+
+    return 0;
+}
+
+static int ec_coe_download_segment(ec_master_t *master,
+                                   uint16_t slave_index,
+                                   ec_datagram_t *datagram,
+                                   const void *seg_data,
+                                   uint16_t size,
+                                   bool toggle,
+                                   bool last)
+{
+    uint8_t *data;
+    uint8_t mbox_proto;
+    uint32_t data_size, recv_size;
+    uint32_t seg_size;
+    ec_coe_download_segment_header_t *download_seg;
+    int ret;
+
+    if (size > EC_COE_DOWN_SEG_MIN_DATA_SIZE) {
+        seg_size = 0;
+        data_size = size;
+    } else {
+        seg_size = EC_COE_DOWN_SEG_MIN_DATA_SIZE - size;
+        data_size = EC_COE_DOWN_SEG_MIN_DATA_SIZE;
+    }
+
+    data = ec_mailbox_fill_send(master, slave_index, datagram, EC_MBOX_TYPE_COE, data_size + EC_COE_DOWN_SEG_REQ_HEADER_SIZE);
+
+    download_seg = (ec_coe_download_segment_header_t *)data;
+    download_seg->coe_header.number = 0;
+    download_seg->coe_header.reserved = 0;
+    download_seg->coe_header.service = EC_COE_SERVICE_SDO_REQUEST;
+
+    download_seg->sdo_header.more_follows = last ? 1 : 0;
+    download_seg->sdo_header.toggle = toggle ? 1 : 0;
+    download_seg->sdo_header.command = EC_COE_REQUEST_SEGMENT_DOWNLOAD;
+    download_seg->sdo_header.segdata_size = seg_size;
+
+    ec_memcpy(data + EC_COE_DOWN_SEG_REQ_HEADER_SIZE, seg_data, size);
+    if (size < EC_COE_DOWN_SEG_MIN_DATA_SIZE) {
+        memset(data + EC_COE_DOWN_SEG_REQ_HEADER_SIZE + size, 0x00, EC_COE_DOWN_SEG_MIN_DATA_SIZE - size);
+    }
+
+    ret = ec_mailbox_send(master, slave_index, datagram);
+    if (ret < 0) {
+        return ret;
+    }
+
+    ret = ec_mailbox_receive(master, slave_index, datagram, &mbox_proto, &recv_size, EC_COE_TIMEOUT_US);
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (mbox_proto != EC_MBOX_TYPE_COE) {
+        return -EC_ERR_COE_TYPE;
+    }
+
+    if (recv_size < 6) {
+        return -EC_ERR_COE_SIZE;
+    }
+
+    data = datagram->data + EC_MBOX_HEADER_SIZE;
+
+    if (EC_READ_U16(data) >> 12 == EC_COE_SERVICE_SDO_REQUEST &&
+        EC_READ_U8(data + 2) >> 5 == EC_COE_REQUEST_ABORT) {
+        EC_SLAVE_LOG_ERR("Slave %u SDO abort code: 0x%08x (%s)\n", slave_index, EC_READ_U32(data + 6), ec_sdo_abort_string(EC_READ_U32(data + 6)));
+        return -EC_ERR_COE_ABORT;
+    }
+
+    if (EC_READ_U16(data) >> 12 != EC_COE_SERVICE_SDO_RESPONSE ||
+        EC_READ_U8(data + 2) >> 5 != EC_COE_RESPONSE_SEGMENT_DOWNLOAD) {
+        return -EC_ERR_COE_REQUEST;
+    }
+
+    if (((EC_READ_U8(data + 2) >> 4) & 0x01) != toggle) {
+        return -EC_ERR_COE_TOGGLE;
+    }
+
+    return 0;
+}
+
+int ec_coe_download(ec_master_t *master,
+                    uint16_t slave_index,
+                    ec_datagram_t *datagram,
+                    uint16_t index,
+                    uint8_t subindex,
+                    const void *buf,
+                    uint32_t size,
+                    bool complete_access)
+{
+    ec_slave_t *slave;
+    uint8_t *ptr;
+    uint32_t seg_size, max_data_size;
+    bool toggle;
+    bool last;
+    int ret;
+
+    if (slave_index >= master->slave_count) {
+        return -EC_ERR_INVAL;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    ptr = (uint8_t *)buf;
+
+    if (size <= 4) {
+        return ec_coe_download_expedited(master, slave_index, datagram, index, subindex, ptr, size, complete_access);
+    } else {
+        max_data_size = slave->configured_rx_mailbox_size - EC_MBOX_HEADER_SIZE - EC_COE_DOWN_REQ_HEADER_SIZE;
+        if (size <= max_data_size) {
+            return ec_coe_download_common(master, slave_index, datagram, index, subindex, ptr, size, complete_access);
+        } else {
+            ret = ec_coe_download_common(master, slave_index, datagram, index, subindex, ptr, max_data_size, complete_access);
+            if (ret < 0) {
+                return ret;
+            }
+
+            size -= max_data_size;
+            ptr += max_data_size;
+            toggle = false;
+            last = false;
+            max_data_size += 7;
+
+            while (1) {
+                seg_size = MIN(size, max_data_size);
+                if (size <= max_data_size) {
+                    last = true;
+                }
+                ret = ec_coe_download_segment(master, slave_index, datagram, ptr, seg_size, toggle, last);
+                if (ret < 0) {
+                    return ret;
+                }
+                ptr += seg_size;
+                size -= seg_size;
+                toggle ^= 1;
+                if (size == 0) {
+                    return 0;
+                }
+            }
+        }
+    }
+}
+
+int ec_coe_upload(ec_master_t *master,
+                  uint16_t slave_index,
+                  ec_datagram_t *datagram,
+                  uint16_t index,
+                  uint8_t subindex,
+                  const void *buf,
+                  uint32_t maxsize,
+                  uint32_t *size,
+                  bool complete_access)
+{
+    uint8_t *data;
+    uint8_t *ptr;
+    uint8_t mbox_proto;
+    uint32_t recv_size;
+    uint16_t rec_index;
+    uint8_t rec_subindex;
+    uint32_t data_size, total_size, offset;
+    bool expedited, size_specified;
+    ec_coe_upload_common_header_t *upload_common;
+    ec_coe_upload_segment_header_t *upload_seg;
+    bool toggle;
+    bool last;
+    int ret;
+
+    ptr = (uint8_t *)buf;
+
+    data = ec_mailbox_fill_send(master, slave_index, datagram, EC_MBOX_TYPE_COE, EC_COE_UP_REQ_HEADER_SIZE);
+
+    upload_common = (ec_coe_upload_common_header_t *)data;
+    upload_common->coe_header.number = 0;
+    upload_common->coe_header.reserved = 0;
+    upload_common->coe_header.service = EC_COE_SERVICE_SDO_REQUEST;
+    upload_common->sdo_header.size_indicator = 0;
+    upload_common->sdo_header.transfertype = 0;
+    upload_common->sdo_header.data_set_size = 0;
+    upload_common->sdo_header.complete_access = complete_access ? 1 : 0;
+    upload_common->sdo_header.command = EC_COE_REQUEST_UPLOAD;
+
+    upload_common->index = index;
+    upload_common->subindex = complete_access ? 0x00 : subindex;
+
+    memset(upload_common->data, 0x00, 4);
+    ret = ec_mailbox_send(master, slave_index, datagram);
+    if (ret < 0) {
+        return ret;
+    }
+
+    ret = ec_mailbox_receive(master, slave_index, datagram, &mbox_proto, &recv_size, EC_COE_TIMEOUT_US);
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (mbox_proto != EC_MBOX_TYPE_COE) {
+        return -EC_ERR_COE_TYPE;
+    }
+
+    if (recv_size < 6) {
+        return -EC_ERR_COE_SIZE;
+    }
+
+    data = datagram->data + EC_MBOX_HEADER_SIZE;
+
+    if (EC_READ_U16(data) >> 12 == EC_COE_SERVICE_SDO_REQUEST &&
+        EC_READ_U8(data + 2) >> 5 == EC_COE_REQUEST_ABORT) {
+        EC_SLAVE_LOG_ERR("Slave %u SDO abort code: 0x%08x (%s)\n", slave_index, EC_READ_U32(data + 6), ec_sdo_abort_string(EC_READ_U32(data + 6)));
+        return -EC_ERR_COE_ABORT;
+    }
+
+    if (EC_READ_U16(data) >> 12 != EC_COE_SERVICE_SDO_RESPONSE ||
+        EC_READ_U8(data + 2) >> 5 != EC_COE_RESPONSE_UPLOAD) {
+        return -EC_ERR_COE_REQUEST;
+    }
+
+    rec_index = EC_READ_U16(data + 3);
+    rec_subindex = EC_READ_U8(data + 5);
+
+    if (rec_index != index || rec_subindex != (complete_access ? 0x00 : subindex)) {
+        return -EC_ERR_COE_REQUEST;
+    }
+
+    expedited = EC_READ_U8(data + 2) & 0x02;
+
+    if (expedited) {
+        size_specified = EC_READ_U8(data + 2) & 0x01;
+        if (size_specified) {
+            total_size = 4 - ((EC_READ_U8(data + 2) & 0x0C) >> 2);
+        } else {
+            total_size = 4;
+        }
+
+        if (recv_size < (total_size + 6)) {
+            return -EC_ERR_COE_SIZE;
+        }
+
+        ec_memcpy(ptr, data + 6, total_size);
+
+        if (maxsize < total_size) {
+            return -EC_ERR_COE_SIZE;
+        }
+
+        if (size) {
+            *size = total_size;
+        }
+        return 0;
+    } else { // normal or segment
+        if (recv_size < EC_COE_UP_REQ_HEADER_SIZE) {
+            return -EC_ERR_COE_SIZE;
+        }
+
+        data_size = recv_size - EC_COE_UP_REQ_HEADER_SIZE;
+        total_size = EC_READ_U32(data + 6);
+        offset = 0;
+
+        if (maxsize < total_size) {
+            return -EC_ERR_COE_SIZE;
+        }
+
+        ec_memcpy(ptr, data + EC_COE_UP_REQ_HEADER_SIZE, data_size);
+
+        ptr += data_size;
+        offset += data_size;
+
+        toggle = false;
+
+        if (offset < total_size) {
+            while (1) {
+                data = ec_mailbox_fill_send(master, slave_index, datagram, EC_MBOX_TYPE_COE, EC_COE_UP_REQ_HEADER_SIZE);
+
+                upload_seg = (ec_coe_upload_segment_header_t *)data;
+                upload_seg->coe_header.number = 0;
+                upload_seg->coe_header.reserved = 0;
+                upload_seg->coe_header.service = EC_COE_SERVICE_SDO_REQUEST;
+                upload_seg->sdo_header.more_follows = 0;
+                upload_seg->sdo_header.toggle = toggle ? 1 : 0;
+                upload_seg->sdo_header.command = EC_COE_REQUEST_SEGMENT_UPLOAD;
+                upload_seg->sdo_header.segdata_size = 0;
+                memset(data + EC_COE_DOWN_SEG_REQ_HEADER_SIZE, 0x00, 7);
+                ret = ec_mailbox_send(master, slave_index, datagram);
+                if (ret < 0) {
+                    return ret;
+                }
+
+                ret = ec_mailbox_receive(master, slave_index, datagram, &mbox_proto, &recv_size, EC_COE_TIMEOUT_US);
+                if (ret < 0) {
+                    return ret;
+                }
+
+                if (mbox_proto != EC_MBOX_TYPE_COE) {
+                    return -EC_ERR_COE_TYPE;
+                }
+
+                if (recv_size < EC_COE_UP_REQ_HEADER_SIZE) {
+                    return -EC_ERR_COE_SIZE;
+                }
+
+                data = datagram->data + EC_MBOX_HEADER_SIZE;
+
+                if (EC_READ_U16(data) >> 12 == EC_COE_SERVICE_SDO_REQUEST &&
+                    EC_READ_U8(data + 2) >> 5 == EC_COE_REQUEST_ABORT) {
+                    EC_SLAVE_LOG_ERR("Slave %u SDO abort code: 0x%08x (%s)\n", slave_index, EC_READ_U32(data + 6), ec_sdo_abort_string(EC_READ_U32(data + 6)));
+                    return -EC_ERR_COE_ABORT;
+                }
+
+                if (EC_READ_U16(data) >> 12 != EC_COE_SERVICE_SDO_RESPONSE ||
+                    EC_READ_U8(data + 2) >> 5 != EC_COE_RESPONSE_SEGMENT_UPLOAD) {
+                    return -EC_ERR_COE_REQUEST;
+                }
+
+                data_size = recv_size - EC_COE_UP_SEG_REQ_HEADER_SIZE;
+
+                if (recv_size == EC_COE_UP_REQ_HEADER_SIZE) {
+                    uint8_t seg_size = (EC_READ_U8(data + 2) & 0xE) >> 1;
+                    data_size -= seg_size;
+                }
+
+                if ((offset + data_size) > total_size) {
+                    return -EC_ERR_COE_SIZE;
+                }
+
+                ec_memcpy(ptr, data + EC_COE_UP_SEG_REQ_HEADER_SIZE, data_size);
+                ptr += data_size;
+                offset += data_size;
+                toggle ^= 1;
+
+                last = EC_READ_U8(data + 2) & 0x01;
+
+                if (last) {
+                    if (offset != total_size) {
+                        return -EC_ERR_COE_SIZE;
+                    }
+
+                    if (size) {
+                        *size = total_size;
+                    }
+                    return 0;
+                }
+            }
+        } else {
+            if (size) {
+                *size = total_size;
+            }
+            return 0;
+        }
+    }
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_common.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_common.c
new file mode 100644
index 00000000..7e1bc96b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_common.c
@@ -0,0 +1,381 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+#define ALIGN_UP_DWORD(x) ((uint32_t)(uintptr_t)(x) & (sizeof(uint32_t) - 1))
+
+static inline void dword2array(char *addr, uint32_t w)
+{
+    addr[0] = w;
+    addr[1] = w >> 8;
+    addr[2] = w >> 16;
+    addr[3] = w >> 24;
+}
+
+EC_FAST_CODE_SECTION void *ec_memcpy(void *s1, const void *s2, size_t n)
+{
+    char *b1 = (char *)s1;
+    const char *b2 = (const char *)s2;
+    uint32_t *w1;
+    const uint32_t *w2;
+
+    if (ALIGN_UP_DWORD(b1) == ALIGN_UP_DWORD(b2)) {
+        while (ALIGN_UP_DWORD(b1) != 0 && n > 0) {
+            *b1++ = *b2++;
+            --n;
+        }
+
+        w1 = (uint32_t *)b1;
+        w2 = (const uint32_t *)b2;
+
+        while (n >= 4 * sizeof(uint32_t)) {
+            *w1++ = *w2++;
+            *w1++ = *w2++;
+            *w1++ = *w2++;
+            *w1++ = *w2++;
+            n -= 4 * sizeof(uint32_t);
+        }
+
+        while (n >= sizeof(uint32_t)) {
+            *w1++ = *w2++;
+            n -= sizeof(uint32_t);
+        }
+
+        b1 = (char *)w1;
+        b2 = (const char *)w2;
+
+        while (n--) {
+            *b1++ = *b2++;
+        }
+    } else {
+        while (n > 0 && ALIGN_UP_DWORD(b2) != 0) {
+            *b1++ = *b2++;
+            --n;
+        }
+
+        w2 = (const uint32_t *)b2;
+
+        while (n >= 4 * sizeof(uint32_t)) {
+            dword2array(b1, *w2++);
+            b1 += sizeof(uint32_t);
+            dword2array(b1, *w2++);
+            b1 += sizeof(uint32_t);
+            dword2array(b1, *w2++);
+            b1 += sizeof(uint32_t);
+            dword2array(b1, *w2++);
+            b1 += sizeof(uint32_t);
+            n -= 4 * sizeof(uint32_t);
+        }
+
+        while (n >= sizeof(uint32_t)) {
+            dword2array(b1, *w2++);
+            b1 += sizeof(uint32_t);
+            n -= sizeof(uint32_t);
+        }
+
+        b2 = (const char *)w2;
+
+        while (n--) {
+            *b1++ = *b2++;
+        }
+    }
+    return s1;
+}
+
+EC_FAST_CODE_SECTION void ec_memset(void *s, int c, size_t n)
+{
+    char *b = (char *)s;
+    uint32_t *w;
+
+    while (ALIGN_UP_DWORD(b) != 0 && n > 0) {
+        *b++ = (char)c;
+        --n;
+    }
+
+    w = (uint32_t *)b;
+    c = (c & 0xff) | ((c & 0xff) << 8) | ((c & 0xff) << 16) | ((c & 0xff) << 24);
+
+    while (n >= 4 * sizeof(uint32_t)) {
+        *w++ = c;
+        *w++ = c;
+        *w++ = c;
+        *w++ = c;
+        n -= 4 * sizeof(uint32_t);
+    }
+
+    while (n >= sizeof(uint32_t)) {
+        *w++ = c;
+        n -= sizeof(uint32_t);
+    }
+
+    b = (char *)w;
+
+    while (n--) {
+        *b++ = (char)c;
+    }
+}
+
+typedef struct {
+    uint32_t code;
+    const char *message;
+} ec_code_msg_t;
+
+const char *ec_state_string(uint8_t states, uint8_t multi)
+{
+    uint32_t off = 0;
+    unsigned int first = 1;
+    static char buffer[64];
+
+    memset(buffer, 0, sizeof(buffer));
+
+    if (!states) {
+        off += sprintf(buffer + off, "(unknown)");
+        return buffer;
+    }
+
+    if (multi) { // multiple slaves
+        if (states & EC_SLAVE_STATE_INIT) {
+            off += sprintf(buffer + off, "INIT");
+            first = 0;
+        }
+        if (states & EC_SLAVE_STATE_PREOP) {
+            if (!first)
+                off += sprintf(buffer + off, ", ");
+            off += sprintf(buffer + off, "PREOP");
+            first = 0;
+        }
+        if (states & EC_SLAVE_STATE_SAFEOP) {
+            if (!first)
+                off += sprintf(buffer + off, ", ");
+            off += sprintf(buffer + off, "SAFEOP");
+            first = 0;
+        }
+        if (states & EC_SLAVE_STATE_OP) {
+            if (!first)
+                off += sprintf(buffer + off, ", ");
+            off += sprintf(buffer + off, "OP");
+        }
+    } else { // single slave
+        if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_INIT) {
+            off += sprintf(buffer + off, "INIT");
+        } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_PREOP) {
+            off += sprintf(buffer + off, "PREOP");
+        } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_BOOT) {
+            off += sprintf(buffer + off, "BOOT");
+        } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_SAFEOP) {
+            off += sprintf(buffer + off, "SAFEOP");
+        } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_OP) {
+            off += sprintf(buffer + off, "OP");
+        } else {
+            off += sprintf(buffer + off, "(invalid)");
+        }
+        first = 0;
+    }
+
+    if (states & EC_SLAVE_STATE_ACK_ERR) {
+        if (!first)
+            off += sprintf(buffer + off, " + ");
+        off += sprintf(buffer + off, "ERROR");
+    }
+
+    return buffer;
+}
+
+const ec_code_msg_t ec_mbox_protocol_messages[] = {
+    { EC_MBXPROT_AOE, "AOE" },
+    { EC_MBXPROT_EOE, "EOE" },
+    { EC_MBXPROT_COE, "COE" },
+    { EC_MBXPROT_FOE, "FOE" },
+    { EC_MBXPROT_SOE, "SOE" },
+    { EC_MBXPROT_VOE, "VOE" },
+    { 0, "" }
+};
+
+const char *ec_mbox_protocol_string(uint8_t prot)
+{
+    static char buffer[64];
+
+    memset(buffer, 0, sizeof(buffer));
+
+    int first = 1;
+    for (uint32_t i = 0; ec_mbox_protocol_messages[i].code != 0; i++) {
+        if (prot & ec_mbox_protocol_messages[i].code) {
+            if (!first) {
+                strcat(buffer, "|");
+            }
+            strcat(buffer, ec_mbox_protocol_messages[i].message);
+            first = 0;
+        }
+    }
+    if (first) {
+        return "";
+    }
+    return buffer;
+}
+
+const ec_code_msg_t al_status_messages[] = {
+    { 0x0000, "No error" },
+    { 0x0001, "Unspecified error" },
+    { 0x0002, "No Memory" },
+    { 0x0011, "Invalid requested state change" },
+    { 0x0012, "Unknown requested state" },
+    { 0x0013, "Bootstrap not supported" },
+    { 0x0014, "No valid firmware" },
+    { 0x0015, "Invalid mailbox configuration (BOOT state)" },
+    { 0x0016, "Invalid mailbox configuration (PreOP state)" },
+    { 0x0017, "Invalid sync manager configuration" },
+    { 0x0018, "No valid inputs available" },
+    { 0x0019, "No valid outputs" },
+    { 0x001A, "Synchronization error" },
+    { 0x001B, "Sync manager watchdog" },
+    { 0x001C, "Invalid sync manager types" },
+    { 0x001D, "Invalid output configuration" },
+    { 0x001E, "Invalid input configuration" },
+    { 0x001F, "Invalid watchdog configuration" },
+    { 0x0020, "Slave needs cold start" },
+    { 0x0021, "Slave needs INIT" },
+    { 0x0022, "Slave needs PREOP" },
+    { 0x0023, "Slave needs SAFEOP" },
+    { 0x0024, "Invalid Input Mapping" },
+    { 0x0025, "Invalid Output Mapping" },
+    { 0x0026, "Inconsistent Settings" },
+    { 0x0027, "Freerun not supported" },
+    { 0x0028, "Synchronization not supported" },
+    { 0x0029, "Freerun needs 3 Buffer Mode" },
+    { 0x002A, "Background Watchdog" },
+    { 0x002B, "No Valid Inputs and Outputs" },
+    { 0x002C, "Fatal Sync Error" },
+    { 0x002D, "No Sync Error" },
+    { 0x0030, "Invalid DC SYNCH configuration" },
+    { 0x0031, "Invalid DC latch configuration" },
+    { 0x0032, "PLL error" },
+    { 0x0033, "DC Sync IO Error" },
+    { 0x0034, "DC Sync Timeout Error" },
+    { 0x0035, "DC Invalid Sync Cycle Time" },
+    { 0x0036, "DC Sync0 Cycle Time" },
+    { 0x0037, "DC Sync1 Cycle Time" },
+    { 0x0041, "MBX_AOE" },
+    { 0x0042, "MBX_EOE" },
+    { 0x0043, "MBX_COE" },
+    { 0x0044, "MBX_FOE" },
+    { 0x0045, "MBX_SOE" },
+    { 0x004F, "MBX_VOE" },
+    { 0x0050, "EEPROM No Access" },
+    { 0x0051, "EEPROM Error" },
+    { 0x0060, "Slave Restarted Locally" },
+    { 0xffff }
+};
+
+const char *ec_alstatus_string(uint16_t errorcode)
+{
+    for (uint32_t i = 0; al_status_messages[i].code != 0xffff; i++) {
+        if (al_status_messages[i].code == errorcode) {
+            return al_status_messages[i].message;
+        }
+    }
+    return "Unknown errorcode";
+}
+
+const ec_code_msg_t mbox_error_messages[] = {
+    { 0x00000001, "MBXERR_SYNTAX" },
+    { 0x00000002, "MBXERR_UNSUPPORTEDPROTOCOL" },
+    { 0x00000003, "MBXERR_INVAILDCHANNEL" },
+    { 0x00000004, "MBXERR_SERVICENOTSUPPORTED" },
+    { 0x00000005, "MBXERR_INVALIDHEADER" },
+    { 0x00000006, "MBXERR_SIZETOOSHORT" },
+    { 0x00000007, "MBXERR_NOMOREMEMORY" },
+    { 0x00000008, "MBXERR_INVALIDSIZE" },
+    { 0xffffffff }
+};
+
+const char *ec_mbox_error_string(uint16_t errorcode)
+{
+    for (uint32_t i = 0; mbox_error_messages[i].code != 0xffffffff; i++) {
+        if (mbox_error_messages[i].code == errorcode) {
+            return mbox_error_messages[i].message;
+        }
+    }
+    return "Unknown errorcode";
+}
+
+const ec_code_msg_t sdo_abort_messages[] = {
+    { 0x05030000, "Toggle bit not changed" },
+    { 0x05040000, "SDO protocol timeout" },
+    { 0x05040001, "Client/Server command specifier not valid or unknown" },
+    { 0x05040005, "Out of memory" },
+    { 0x06010000, "Unsupported access to an object" },
+    { 0x06010001, "Attempt to read a write-only object" },
+    { 0x06010002, "Attempt to write a read-only object" },
+    { 0x06020000, "This object does not exist in the object directory" },
+    { 0x06040041, "The object cannot be mapped into the PDO" },
+    { 0x06040042, "The number and length of the objects to be mapped would"
+                  " exceed the PDO length" },
+    { 0x06040043, "General parameter incompatibility reason" },
+    { 0x06040047, "Gerneral internal incompatibility in device" },
+    { 0x06060000, "Access failure due to a hardware error" },
+    { 0x06070010, "Data type does not match, length of service parameter does"
+                  " not match" },
+    { 0x06070012, "Data type does not match, length of service parameter too"
+                  " high" },
+    { 0x06070013, "Data type does not match, length of service parameter too"
+                  " low" },
+    { 0x06090011, "Subindex does not exist" },
+    { 0x06090030, "Value range of parameter exceeded" },
+    { 0x06090031, "Value of parameter written too high" },
+    { 0x06090032, "Value of parameter written too low" },
+    { 0x06090036, "Maximum value is less than minimum value" },
+    { 0x08000000, "General error" },
+    { 0x08000020, "Data cannot be transferred or stored to the application" },
+    { 0x08000021, "Data cannot be transferred or stored to the application"
+                  " because of local control" },
+    { 0x08000022, "Data cannot be transferred or stored to the application"
+                  " because of the present device state" },
+    { 0x08000023, "Object dictionary dynamic generation fails or no object"
+                  " dictionary is present" },
+    { 0xffffffff }
+};
+
+const char *ec_sdo_abort_string(uint32_t errorcode)
+{
+    for (uint32_t i = 0; sdo_abort_messages[i].code != 0xffffffff; i++) {
+        if (sdo_abort_messages[i].code == errorcode) {
+            return sdo_abort_messages[i].message;
+        }
+    }
+    return "Unknown errorcode";
+}
+
+const ec_code_msg_t foe_errcode_messages[] = {
+    { EC_FOE_ERRCODE_NOTDEFINED, "Not defined" },
+    { EC_FOE_ERRCODE_NOTFOUND, "The file requested by an FoE upload service could not be found on the server" },
+    { EC_FOE_ERRCODE_ACCESS, "Read or write access to this file not allowed (e.g. due to local control)" },
+    { EC_FOE_ERRCODE_DISKFULL, "Disk to store file is full or memory allocation exceeded" },
+    { EC_FOE_ERRCODE_ILLEGAL, "Illegal FoE operation, e.g. service identifier invalid" },
+    { EC_FOE_ERRCODE_PACKENO, "FoE packet number invalid" },
+    { EC_FOE_ERRCODE_EXISTS, "The file which is requested to be downloaded does already exist" },
+    { EC_FOE_ERRCODE_NOUSER, "No User" },
+    { EC_FOE_ERRCODE_BOOTSTRAPONLY, "FoE only supported in Bootstrap" },
+    { EC_FOE_ERRCODE_NOTINBOOTSTRAP, "This file may not be accessed in BOOTSTRAP state" },
+    { EC_FOE_ERRCODE_NORIGHTS, "Password invalid" },
+    { EC_FOE_ERRCODE_PROGERROR, "Generic programming error. Should only be returned if  error reason cannot be distinguished" },
+    { EC_FOE_ERRCODE_INVALID_CHECKSUM, "checksum included in the file is invalid" },
+    { EC_FOE_ERRCODE_INVALID_FIRMWARE, "The hardware does not support the downloaded firmware" },
+    { EC_FOE_ERRCODE_NO_FILE, "Do not use (identical with 0x8001)" },
+    { EC_FOE_ERRCODE_NO_FILE_HEADER, "Missing file header of error in file header" },
+    { EC_FOE_ERRCODE_FLASH_ERROR, "Flash cannot be accessed" },
+    { 0xffffffff }
+
+};
+
+const char *foe_errorcode_string(uint16_t errorcode)
+{
+    for (uint32_t i = 0; foe_errcode_messages[i].code != 0xffffffff; i++) {
+        if (foe_errcode_messages[i].code == errorcode) {
+            return foe_errcode_messages[i].message;
+        }
+    }
+    return "Unknown errorcode";
+}
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_datagram.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_datagram.c
new file mode 100644
index 00000000..9ada58a6
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_datagram.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+static const char *type_strings[] = {
+    "?",
+    "APRD",
+    "APWR",
+    "APRW",
+    "FPRD",
+    "FPWR",
+    "FPRW",
+    "BRD",
+    "BWR",
+    "BRW",
+    "LRD",
+    "LWR",
+    "LRW",
+    "ARMW",
+    "FRMW"
+};
+
+void ec_datagram_init(ec_datagram_t *datagram, size_t mem_size)
+{
+    uint8_t *data = NULL;
+
+    data = ec_osal_malloc(mem_size);
+    if (!data) {
+        EC_LOG_ERR("Failed to allocate memory for datagram data\n");
+        return;
+    }
+
+    ec_dlist_init(&datagram->queue);
+    datagram->netdev_idx = EC_NETDEV_MAIN;
+    datagram->type = EC_DATAGRAM_NONE;
+    memset(datagram->address, 0x00, EC_ADDR_LEN);
+    datagram->data = data;
+    datagram->mem_size = mem_size;
+    datagram->data_size = 0;
+    datagram->index = 0x00;
+    datagram->working_counter = 0x0000;
+    datagram->state = EC_DATAGRAM_INIT;
+    datagram->jiffies_sent = 0;
+    datagram->jiffies_received = 0;
+    memset(datagram->name, 0x00, EC_DATAGRAM_NAME_SIZE);
+
+    datagram->waiter = 0;
+    datagram->wait = ec_osal_sem_create(1, 0);
+    if (!datagram->wait) {
+        EC_LOG_ERR("Failed to create semaphore for datagram\n");
+        ec_osal_free(data);
+        datagram->data = NULL;
+        return;
+    }
+}
+
+void ec_datagram_init_static(ec_datagram_t *datagram, uint8_t *data, size_t mem_size)
+{
+    ec_dlist_init(&datagram->queue);
+    datagram->netdev_idx = EC_NETDEV_MAIN;
+    datagram->type = EC_DATAGRAM_NONE;
+    datagram->static_alloc = true;
+    memset(datagram->address, 0x00, EC_ADDR_LEN);
+    datagram->data = data;
+    datagram->mem_size = mem_size;
+    datagram->data_size = 0;
+    datagram->index = 0x00;
+    datagram->working_counter = 0x0000;
+    datagram->state = EC_DATAGRAM_INIT;
+    datagram->jiffies_sent = 0;
+    datagram->jiffies_received = 0;
+    memset(datagram->name, 0x00, EC_DATAGRAM_NAME_SIZE);
+}
+
+void ec_datagram_clear(ec_datagram_t *datagram)
+{
+    ec_datagram_unqueue(datagram);
+
+    if (datagram->data && !datagram->static_alloc) {
+        ec_osal_free(datagram->data);
+        datagram->data = NULL;
+
+        if (datagram->wait) {
+            ec_osal_sem_delete(datagram->wait);
+            datagram->wait = NULL;
+        }
+    }
+}
+
+void ec_datagram_unqueue(ec_datagram_t *datagram)
+{
+    if (!ec_dlist_isempty(&datagram->queue)) {
+        ec_dlist_del_init(&datagram->queue);
+    }
+}
+
+EC_FAST_CODE_SECTION void ec_datagram_zero(ec_datagram_t *datagram)
+{
+    memset(datagram->data, 0x00, datagram->data_size);
+}
+
+void ec_datagram_fill(ec_datagram_t *datagram,
+                      ec_datagram_type_t type,
+                      uint16_t adp,
+                      uint16_t ado,
+                      uint16_t size)
+{
+    datagram->index = 0;
+    datagram->working_counter = 0;
+    datagram->state = EC_DATAGRAM_INIT;
+
+    datagram->type = type;
+    EC_WRITE_U16(datagram->address, adp);
+    EC_WRITE_U16(datagram->address + 2, ado);
+    datagram->data_size = size;
+    datagram->waiter = 0;
+}
+
+void ec_datagram_aprd(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_APRD, autoinc_address, mem_address, data_size);
+}
+
+void ec_datagram_apwr(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_APWR, autoinc_address, mem_address, data_size);
+}
+
+void ec_datagram_aprw(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_APRW, autoinc_address, mem_address, data_size);
+}
+
+void ec_datagram_armw(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_ARMW, autoinc_address, mem_address, data_size);
+}
+
+void ec_datagram_fprd(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_FPRD, configured_address, mem_address, data_size);
+}
+
+void ec_datagram_fpwr(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_FPWR, configured_address, mem_address, data_size);
+}
+
+void ec_datagram_fprw(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_FPRW, configured_address, mem_address, data_size);
+}
+
+void ec_datagram_frmw(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_FRMW, configured_address, mem_address, data_size);
+}
+
+void ec_datagram_brd(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_BRD, 0x0000, mem_address, data_size);
+}
+
+void ec_datagram_bwr(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_BWR, 0x0000, mem_address, data_size);
+}
+
+void ec_datagram_brw(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_BRW, 0x0000, mem_address, data_size);
+}
+
+void ec_datagram_lrd(ec_datagram_t *datagram, uint32_t offset, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_LRD, offset & 0xffff, offset >> 16, data_size);
+}
+
+void ec_datagram_lwr(ec_datagram_t *datagram, uint32_t offset, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_LWR, offset & 0xffff, offset >> 16, data_size);
+}
+
+void ec_datagram_lrw(ec_datagram_t *datagram, uint32_t offset, size_t data_size)
+{
+    ec_datagram_fill(datagram, EC_DATAGRAM_LRW, offset & 0xffff, offset >> 16, data_size);
+}
+
+const char *ec_datagram_type_string(const ec_datagram_t *datagram)
+{
+    return type_strings[datagram->type];
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_foe.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_foe.c
new file mode 100644
index 00000000..e69de29b
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_mailbox.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_mailbox.c
new file mode 100644
index 00000000..2de0e36e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_mailbox.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+#define EC_MBOX_READ_TIMEOUT (100 * 1000)
+
+uint8_t *ec_mailbox_fill_send(ec_master_t *master,
+                              uint16_t slave_index,
+                              ec_datagram_t *datagram,
+                              uint8_t type,
+                              uint16_t size)
+{
+    ec_slave_t *slave;
+
+    EC_ASSERT_MSG(slave_index >= master->slave_count, "Invalid slave index");
+
+    slave = &master->slaves[slave_index];
+
+    EC_ASSERT_MSG((EC_MBOX_HEADER_SIZE + size) <= slave->configured_rx_mailbox_size, "RX Mailbox size overflow");
+
+    EC_WRITE_U16(datagram->data, size);                       // mailbox service data length
+    EC_WRITE_U16(datagram->data + 2, slave->station_address); // station address
+    EC_WRITE_U8(datagram->data + 4, 0x00);                    // channel & priority
+    EC_WRITE_U8(datagram->data + 5, type);                    // protocol type
+
+    return (datagram->data + EC_MBOX_HEADER_SIZE);
+}
+
+int ec_mailbox_send(ec_master_t *master,
+                    uint16_t slave_index,
+                    ec_datagram_t *datagram)
+{
+    ec_slave_t *slave;
+
+    if (slave_index >= master->slave_count) {
+        return -EC_ERR_INVAL;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    ec_datagram_fpwr(datagram, slave->station_address, slave->configured_rx_mailbox_offset, slave->configured_rx_mailbox_size);
+    datagram->netdev_idx = slave->netdev_idx;
+    return ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+}
+
+int ec_mailbox_read_status(ec_master_t *master,
+                           uint16_t slave_index,
+                           ec_datagram_t *datagram,
+                           uint32_t timeout_us)
+{
+    ec_slave_t *slave;
+    uint32_t start_time;
+    int ret;
+
+    if (slave_index >= master->slave_count) {
+        return -EC_ERR_INVAL;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    start_time = jiffies;
+
+check_again:
+    ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->SYNCM[EC_SM_INDEX_MBX_READ]), 8);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (!(EC_READ_U8(datagram->data + 5) & ESC_SYNCM_STATUS_MBX_MODE_MASK)) {
+        if ((jiffies - start_time) > timeout_us) {
+            return -EC_ERR_TIMEOUT;
+        }
+        goto check_again;
+    }
+
+    return 0;
+}
+
+int ec_mailbox_receive(ec_master_t *master,
+                       uint16_t slave_index,
+                       ec_datagram_t *datagram,
+                       uint8_t *type,
+                       uint32_t *size,
+                       uint32_t timeout_us)
+{
+    ec_slave_t *slave;
+    uint16_t code;
+    uint32_t tmp_size;
+    uint8_t tmp_type;
+    int ret;
+
+    if (slave_index >= master->slave_count) {
+        return -EC_ERR_INVAL;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    ret = ec_mailbox_read_status(master, slave_index, datagram, timeout_us);
+    if (ret < 0) {
+        return ret;
+    }
+
+    ec_datagram_fprd(datagram, slave->station_address, slave->configured_tx_mailbox_offset, slave->configured_tx_mailbox_size);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    tmp_size = EC_READ_U16(datagram->data);
+    tmp_type = EC_READ_U8(datagram->data + 5) & 0x0F;
+
+    EC_ASSERT_MSG(tmp_size <= slave->configured_tx_mailbox_size, "TX Mailbox size overflow");
+
+    if (tmp_type == 0x00) {
+        code = EC_READ_U16(datagram->data + 8);
+
+        EC_SLAVE_LOG_ERR("Slave %u mailbox errorcode: 0x%04x (%s)\n", slave->index, code, ec_mbox_error_string(code));
+        return -EC_ERR_MBOX;
+    }
+
+    *type = tmp_type;
+    *size = tmp_size;
+
+    return 0;
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_master.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_master.c
new file mode 100644
index 00000000..08bd4271
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_master.c
@@ -0,0 +1,856 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+#define EC_DATAGRAM_TIMEOUT_US (50 * 1000) // 50ms
+
+static void ec_master_period_process(void *arg);
+
+/** List of intervals for statistics [s].
+ */
+const unsigned int rate_intervals[] = {
+    1, 10, 60
+};
+
+EC_FAST_CODE_SECTION static void ec_master_update_netdev_stats(ec_master_t *master)
+{
+    ec_netdev_stats_t *s = &master->netdev_stats;
+    int32_t tx_frame_rate, rx_frame_rate, tx_byte_rate, rx_byte_rate, loss_rate;
+    uint64_t loss;
+    unsigned int i, netdev_idx;
+
+    // frame statistics
+    if ((jiffies - s->last_jiffies) < 1000000) {
+        return;
+    }
+
+    tx_frame_rate = (s->tx_count - s->last_tx_count) * 1000;
+    rx_frame_rate = (s->rx_count - s->last_rx_count) * 1000;
+    tx_byte_rate = s->tx_bytes - s->last_tx_bytes;
+    rx_byte_rate = s->rx_bytes - s->last_rx_bytes;
+    loss = s->tx_count - s->rx_count;
+    loss_rate = (loss - s->last_loss) * 1000;
+
+    /* Low-pass filter:
+     *      Y_n = y_(n - 1) + T / tau * (x - y_(n - 1))   | T = 1
+     *   -> Y_n += (x - y_(n - 1)) / tau
+     */
+    for (i = 0; i < EC_RATE_COUNT; i++) {
+        int32_t n = rate_intervals[i];
+        s->tx_frame_rates[i] += (tx_frame_rate - s->tx_frame_rates[i]) / n;
+        s->rx_frame_rates[i] += (rx_frame_rate - s->rx_frame_rates[i]) / n;
+        s->tx_byte_rates[i] += (tx_byte_rate - s->tx_byte_rates[i]) / n;
+        s->rx_byte_rates[i] += (rx_byte_rate - s->rx_byte_rates[i]) / n;
+        s->loss_rates[i] += (loss_rate - s->loss_rates[i]) / n;
+    }
+
+    s->last_tx_count = s->tx_count;
+    s->last_rx_count = s->rx_count;
+    s->last_tx_bytes = s->tx_bytes;
+    s->last_rx_bytes = s->rx_bytes;
+    s->last_loss = loss;
+
+    for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS;
+         netdev_idx++) {
+        ec_netdev_update_stats(master->netdev[netdev_idx]);
+    }
+
+    s->last_jiffies = jiffies;
+}
+
+EC_FAST_CODE_SECTION static void ec_master_clear_netdev_stats(ec_master_t *master)
+{
+    unsigned int i;
+
+    // zero frame statistics
+    master->netdev_stats.tx_count = 0;
+    master->netdev_stats.last_tx_count = 0;
+    master->netdev_stats.rx_count = 0;
+    master->netdev_stats.last_rx_count = 0;
+    master->netdev_stats.tx_bytes = 0;
+    master->netdev_stats.last_tx_bytes = 0;
+    master->netdev_stats.rx_bytes = 0;
+    master->netdev_stats.last_rx_bytes = 0;
+    master->netdev_stats.last_loss = 0;
+
+    for (i = 0; i < EC_RATE_COUNT; i++) {
+        master->netdev_stats.tx_frame_rates[i] = 0;
+        master->netdev_stats.rx_frame_rates[i] = 0;
+        master->netdev_stats.tx_byte_rates[i] = 0;
+        master->netdev_stats.rx_byte_rates[i] = 0;
+        master->netdev_stats.loss_rates[i] = 0;
+    }
+
+    master->netdev_stats.last_jiffies = 0;
+}
+
+EC_FAST_CODE_SECTION static void ec_master_queue_datagram(ec_master_t *master, ec_datagram_t *datagram)
+{
+    ec_datagram_t *queued_datagram;
+
+    ec_dlist_for_each_entry(queued_datagram, &master->datagram_queue, queue)
+    {
+        if (queued_datagram == datagram) {
+            datagram->state = EC_DATAGRAM_QUEUED;
+            return;
+        }
+    }
+
+    ec_dlist_add_tail(&master->datagram_queue, &datagram->queue);
+    datagram->state = EC_DATAGRAM_QUEUED;
+}
+
+EC_FAST_CODE_SECTION static void ec_master_unqueue_datagram(ec_master_t *master, ec_datagram_t *datagram)
+{
+    ec_dlist_del_init(&datagram->queue);
+
+    if (datagram->waiter) {
+        datagram->waiter = false;
+        ec_osal_sem_give(datagram->wait);
+    }
+}
+
+EC_FAST_CODE_SECTION static void ec_master_send_datagrams(ec_master_t *master, ec_netdev_index_t netdev_idx)
+{
+    ec_datagram_t *datagram, *next;
+    size_t datagram_size;
+    uint8_t *frame_data, *cur_data = NULL;
+    void *follows_word;
+    uint64_t jiffies_sent;
+    unsigned int datagram_count, more_datagrams_waiting;
+    ec_dlist_t sent_datagrams;
+
+#ifdef CONFIG_EC_CAL_TX_TIME
+    uint64_t cycles_start = jiffies;
+#endif
+    datagram_count = 0;
+    ec_dlist_init(&sent_datagrams);
+
+    do {
+        frame_data = NULL;
+        follows_word = NULL;
+        more_datagrams_waiting = 0;
+
+        // fill current frame with datagrams
+        ec_dlist_for_each_entry(datagram, &master->datagram_queue, queue)
+        {
+            if (datagram->state != EC_DATAGRAM_QUEUED ||
+                datagram->netdev_idx != netdev_idx) {
+                continue;
+            }
+
+            if (!frame_data) {
+                // fetch pointer to transmit socket buffer
+                frame_data =
+                    ec_netdev_get_txbuf(master->netdev[netdev_idx]);
+                cur_data = frame_data + EC_FRAME_HEADER_SIZE;
+            }
+
+            // does the current datagram fit in the frame?
+            datagram_size = EC_DATAGRAM_HEADER_SIZE + datagram->data_size + EC_DATAGRAM_WC_SIZE;
+            if (cur_data - frame_data + datagram_size > ETH_DATA_LEN) {
+                more_datagrams_waiting = 1;
+                break;
+            }
+
+            ec_dlist_add_tail(&sent_datagrams, &datagram->sent);
+            datagram->index = master->datagram_index++;
+
+            EC_LOG_DBG("Adding datagram 0x%02X\n", datagram->index);
+
+            // set "datagram following" flag in previous datagram
+            if (follows_word) {
+                EC_WRITE_U16(follows_word,
+                             EC_READ_U16(follows_word) | 0x8000);
+            }
+
+            // EtherCAT datagram header
+            EC_WRITE_U8(cur_data, datagram->type);
+            EC_WRITE_U8(cur_data + 1, datagram->index);
+            ec_memcpy(cur_data + 2, datagram->address, EC_ADDR_LEN);
+            EC_WRITE_U16(cur_data + 6, datagram->data_size & 0x7FF);
+            EC_WRITE_U16(cur_data + 8, 0x0000); // IRQ
+            follows_word = cur_data + 6;
+            cur_data += EC_DATAGRAM_HEADER_SIZE;
+
+            // EtherCAT datagram data
+            ec_memcpy(cur_data, datagram->data, datagram->data_size);
+            cur_data += datagram->data_size;
+
+            // EtherCAT datagram footer
+            EC_WRITE_U16(cur_data, 0x0000); // reset working counter
+            cur_data += EC_DATAGRAM_WC_SIZE;
+        }
+
+        if (ec_dlist_isempty(&sent_datagrams)) {
+            EC_LOG_DBG("nothing to send.\n");
+            break;
+        }
+
+        // EtherCAT frame header
+        EC_WRITE_U16(frame_data, ((cur_data - frame_data - EC_FRAME_HEADER_SIZE) & 0x7FF) | 0x1000);
+
+        // pad frame
+        while (cur_data - frame_data < ETH_ZLEN - ETH_HLEN)
+            EC_WRITE_U8(cur_data++, 0x00);
+
+        EC_LOG_DBG("frame size: %u\n", cur_data - frame_data);
+
+        // send frame
+        if (ec_netdev_send(master->netdev[netdev_idx], cur_data - frame_data) < 0) {
+            EC_LOG_ERR("ec_netdev_send() failed.\n");
+        }
+
+        jiffies_sent = jiffies;
+
+        // set datagram states and sending timestamps
+        ec_dlist_for_each_entry_safe(datagram, next, &sent_datagrams, sent)
+        {
+            datagram->state = EC_DATAGRAM_SENT;
+            datagram->jiffies_sent = jiffies_sent;
+            ec_dlist_del_init(&datagram->sent); // empty list of sent datagrams
+
+            datagram_count++;
+        }
+    } while (more_datagrams_waiting);
+
+#ifdef CONFIG_EC_CAL_TX_TIME
+    EC_LOG_INFO("Sent %u datagrams in %uus.\n", datagram_count, (unsigned int)(jiffies - cycles_start));
+#endif
+}
+
+EC_FAST_CODE_SECTION void ec_master_receive_datagrams(ec_master_t *master,
+                                                      ec_netdev_index_t netdev_idx,
+                                                      const uint8_t *frame_data,
+                                                      size_t size)
+{
+    size_t frame_size, data_size;
+    uint8_t datagram_type, datagram_index;
+    unsigned int cmd_follows, matched;
+    const uint8_t *cur_data;
+    unsigned int datagram_count;
+    ec_datagram_t *datagram;
+
+    if (size < EC_FRAME_HEADER_SIZE) {
+        EC_LOG_ERR("Corrupted frame received on %s (size %u < %u byte)\n",
+                   master->netdev[netdev_idx]->name, size, EC_FRAME_HEADER_SIZE);
+        master->stats.corrupted++;
+        return;
+    }
+
+    cur_data = frame_data;
+
+    // check length of entire frame
+    frame_size = EC_READ_U16(cur_data) & 0x07FF;
+    cur_data += EC_FRAME_HEADER_SIZE;
+
+    if (frame_size > size) {
+        EC_LOG_ERR("Corrupted frame received on %s (invalid frame size %u > received size %u)\n",
+                   master->netdev[netdev_idx]->name, frame_size, size);
+        master->stats.corrupted++;
+        return;
+    }
+
+#ifdef CONFIG_EC_CAL_RX_TIME
+    uint64_t cycles_start = jiffies;
+#endif
+    datagram_count = 0;
+    cmd_follows = 1;
+    while (cmd_follows) {
+        // process datagram header
+        datagram_type = EC_READ_U8(cur_data);
+        datagram_index = EC_READ_U8(cur_data + 1);
+        data_size = EC_READ_U16(cur_data + 6) & 0x07FF;
+        cmd_follows = EC_READ_U16(cur_data + 6) & 0x8000;
+        cur_data += EC_DATAGRAM_HEADER_SIZE;
+
+        if ((cur_data - frame_data + data_size + EC_DATAGRAM_WC_SIZE) > size) {
+            EC_LOG_ERR("Corrupted frame received on %s (invalid data size %u)\n",
+                       master->netdev[netdev_idx]->name, data_size);
+            master->stats.corrupted++;
+            return;
+        }
+
+        // search for matching datagram in the queue
+        matched = 0;
+        ec_dlist_for_each_entry(datagram, &master->datagram_queue, queue)
+        {
+            if ((datagram->index == datagram_index) &&
+                (datagram->state == EC_DATAGRAM_SENT) &&
+                (datagram->type == datagram_type) &&
+                (datagram->data_size == data_size)) {
+                matched = 1;
+                break;
+            }
+        }
+
+        // no matching datagram was found
+        if (!matched) {
+            EC_LOG_DBG("No matching datagram found for index 0x%02X, type 0x%02X, size %u on %s\n",
+                       datagram_index, datagram_type, data_size,
+                       master->netdev[netdev_idx]->name);
+            master->stats.unmatched++;
+
+            cur_data += data_size + EC_DATAGRAM_WC_SIZE;
+            continue;
+        }
+
+        if (datagram->type != EC_DATAGRAM_APWR &&
+            datagram->type != EC_DATAGRAM_FPWR &&
+            datagram->type != EC_DATAGRAM_BWR &&
+            datagram->type != EC_DATAGRAM_LWR) {
+            // copy received data into the datagram memory, only copy the read part, do not modify the write part
+            if (datagram->type == EC_DATAGRAM_LRW) {
+                ec_memcpy(datagram->data + datagram->lrw_read_offset, cur_data + datagram->lrw_read_offset, datagram->lrw_read_size);
+            } else {
+                ec_memcpy(datagram->data, cur_data, data_size);
+            }
+        }
+        cur_data += data_size;
+
+        // set the datagram's working counter
+        datagram->working_counter = EC_READ_U16(cur_data);
+        cur_data += EC_DATAGRAM_WC_SIZE;
+
+        // dequeue the received datagram
+        datagram->state = EC_DATAGRAM_RECEIVED;
+
+        datagram->jiffies_received = master->netdev[EC_NETDEV_MAIN]->jiffies_poll;
+        ec_master_unqueue_datagram(master, datagram);
+
+        datagram_count++;
+    }
+#ifdef CONFIG_EC_CAL_RX_TIME
+    EC_LOG_INFO("Recv %u datagrams in %uus.\n", datagram_count, (unsigned int)(jiffies - cycles_start));
+#endif
+}
+
+EC_FAST_CODE_SECTION static void ec_master_send(ec_master_t *master)
+{
+    ec_datagram_t *datagram, *n;
+    ec_netdev_index_t netdev_idx;
+
+    // update netdev statistics
+    ec_master_update_netdev_stats(master);
+
+    // dequeue all datagrams that timed out
+    ec_dlist_for_each_entry_safe(datagram, n, &master->datagram_queue, queue)
+    {
+        if (datagram->state != EC_DATAGRAM_SENT)
+            continue;
+
+        if ((jiffies - datagram->jiffies_sent) > EC_DATAGRAM_TIMEOUT_US) {
+            datagram->state = EC_DATAGRAM_TIMED_OUT;
+            ec_master_unqueue_datagram(master, datagram);
+            master->stats.timeouts++;
+        }
+    }
+
+    for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+        if (!master->netdev[netdev_idx]->link_state) {
+            // link is down, no datagram can be sent
+            ec_dlist_for_each_entry_safe(datagram, n, &master->datagram_queue, queue)
+            {
+                if (datagram->netdev_idx == netdev_idx) {
+                    datagram->state = EC_DATAGRAM_ERROR;
+                    ec_master_unqueue_datagram(master, datagram);
+                }
+            }
+
+            if (!master->netdev[netdev_idx]) {
+                continue;
+            }
+
+            // clear frame statistics
+            ec_netdev_clear_stats(master->netdev[netdev_idx]);
+            continue;
+        }
+
+        // send frames
+        ec_master_send_datagrams(master, netdev_idx);
+    }
+}
+
+static void ec_netdev_linkpoll_timer(void *argument)
+{
+    ec_master_t *master = (ec_master_t *)argument;
+    unsigned int netdev_idx;
+
+    for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+        ec_netdev_poll_link_state(master->netdev[netdev_idx]);
+    }
+}
+
+static int ec_master_enter_idle(ec_master_t *master)
+{
+    master->phase = EC_IDLE;
+    master->nonperiod_suspend = false;
+
+    ec_osal_thread_resume(master->nonperiod_thread);
+
+    return 0;
+}
+
+static void ec_master_exit_idle(ec_master_t *master)
+{
+    master->nonperiod_suspend = false;
+    ec_osal_thread_suspend(master->nonperiod_thread);
+}
+
+static void ec_master_nonperiod_thread(void *argument)
+{
+    ec_master_t *master = (ec_master_t *)argument;
+    uintptr_t flags;
+
+    while (1) {
+        ec_osal_sem_take(master->nonperiod_sem, CONFIG_EC_NONPERIOD_INTERVAL_MS);
+        flags = ec_osal_enter_critical_section();
+        ec_master_send(master);
+        ec_osal_leave_critical_section(flags);
+
+        if (master->nonperiod_suspend) {
+            ec_master_exit_idle(master);
+        }
+    }
+}
+
+static void ec_master_scan_thread(void *argument)
+{
+    ec_master_t *master = (ec_master_t *)argument;
+
+    while (1) {
+        ec_slaves_scanning(master);
+        ec_osal_msleep(CONFIG_EC_SCAN_INTERVAL_MS);
+    }
+}
+
+int ec_master_init(ec_master_t *master, uint8_t master_index)
+{
+    unsigned int netdev_idx;
+
+    memset(master, 0, sizeof(ec_master_t));
+    master->index = master_index;
+    master->datagram_index = 1; // start with index 1
+
+    ec_dlist_init(&master->datagram_queue);
+    ec_dlist_init(&master->pdo_datagram_queue);
+
+    ec_timestamp_init();
+
+    for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+        master->netdev[netdev_idx] = ec_netdev_init(netdev_idx);
+        if (!master->netdev[netdev_idx]) {
+            return -1;
+        }
+        master->netdev[netdev_idx]->master = master;
+    }
+
+    ec_master_clear_netdev_stats(master);
+
+    ec_datagram_init(&master->main_datagram, EC_MAX_DATA_SIZE);
+    ec_datagram_init(&master->dc_ref_sync_datagram, 8);
+    ec_datagram_init(&master->dc_all_sync_datagram, 8);
+    ec_datagram_init(&master->systime_diff_mon_datagram, 4);
+
+    ec_datagram_brd(&master->systime_diff_mon_datagram, ESCREG_OF(ESCREG->SYS_TIME_DIFF), 4);
+
+    master->scan_lock = ec_osal_mutex_create();
+    if (!master->scan_lock) {
+        return -1;
+    }
+
+    master->nonperiod_sem = ec_osal_sem_create(CONFIG_EC_NONPERIOD_WAITERS, 0);
+    if (!master->nonperiod_sem) {
+        return -1;
+    }
+
+    master->nonperiod_thread = ec_osal_thread_create("ec_nonperiod", CONFIG_EC_NONPERIOD_STACKSIZE, CONFIG_EC_NONPERIOD_PRIO, ec_master_nonperiod_thread, master);
+    if (!master->nonperiod_thread) {
+        return -1;
+    }
+
+    master->scan_thread = ec_osal_thread_create("ec_scan", CONFIG_EC_SCAN_STACKSIZE, CONFIG_EC_SCAN_PRIO, ec_master_scan_thread, master);
+    if (!master->scan_thread) {
+        return -1;
+    }
+
+    master->linkdetect_timer = ec_osal_timer_create("ec_linkdetect", 1000, ec_netdev_linkpoll_timer, master, true);
+    if (!master->linkdetect_timer) {
+        return -1;
+    }
+
+    ec_osal_timer_start(master->linkdetect_timer);
+
+    ec_master_enter_idle(master);
+
+    return 0;
+}
+
+void ec_master_deinit(ec_master_t *master)
+{
+}
+
+int ec_master_start(ec_master_t *master, uint32_t period_us)
+{
+    ec_slave_t *slave;
+    uint32_t bitlen;
+    bool used[2] = { false, false };
+    unsigned int netdev_idx;
+    uint8_t sm_idx;
+
+    if (master->active) {
+        return 0;
+    }
+
+    while (!master->scan_done) {
+        ec_osal_msleep(10);
+    }
+
+    ec_osal_mutex_take(master->scan_lock);
+
+    master->actual_working_counter = 0;
+    master->expected_working_counter = 0;
+    master->actual_pdo_size = 0;
+    master->phase = EC_OPERATION;
+    master->nonperiod_suspend = true;
+    master->interval = 0;
+    master->systime_diff_enable = false;
+
+    // wait for non-periodic thread to suspend
+    while (master->nonperiod_suspend) {
+        ec_osal_msleep(10);
+    }
+
+    for (uint32_t slave_idx = 0; slave_idx < master->slave_count; slave_idx++) {
+        slave = &master->slaves[slave_idx];
+
+        EC_ASSERT_MSG(slave->config != NULL, "Slave %u has no configuration\n", slave_idx);
+
+        slave->logical_start_address = master->actual_pdo_size;
+        slave->odata_size = 0;
+        slave->idata_size = 0;
+        for (uint8_t i = 0; i < slave->config->sync_count; i++) {
+            bitlen = 0;
+
+            sm_idx = slave->config->sync[i].index;
+            EC_ASSERT_MSG(sm_idx < slave->sm_count, "Slave %u: Invalid sync manager index %u\n",
+                          slave_idx, sm_idx);
+
+            slave->sm_info[sm_idx].pdo_assign.count = slave->config->sync[i].n_pdos;
+
+            for (uint32_t j = 0; j < slave->config->sync[i].n_pdos; j++) {
+                slave->sm_info[sm_idx].pdo_assign.entry[j] = slave->config->sync[i].pdos[j].index;
+
+                slave->sm_info[sm_idx].pdo_mapping[j].count = slave->config->sync[i].pdos[j].n_entries;
+
+                for (uint32_t k = 0; k < slave->config->sync[i].pdos[j].n_entries; k++) {
+                    uint32_t entry = (slave->config->sync[i].pdos[j].entries[k].index << 16) |
+                                     (slave->config->sync[i].pdos[j].entries[k].subindex & 0xFF) << 8 |
+                                     (slave->config->sync[i].pdos[j].entries[k].bit_length & 0xFF);
+                    slave->sm_info[sm_idx].pdo_mapping[j].entry[k] = entry;
+
+                    bitlen += slave->config->sync[i].pdos[j].entries[k].bit_length;
+                }
+            }
+
+            // update SM
+            slave->sm_info[sm_idx].length = (bitlen + 7) / 8;
+            slave->sm_info[sm_idx].enable = true;
+
+            // update FMMU
+            slave->sm_info[sm_idx].fmmu.data_size = (bitlen + 7) / 8;
+            slave->sm_info[sm_idx].fmmu.logical_start_address = master->actual_pdo_size;
+            slave->sm_info[sm_idx].fmmu.dir = slave->config->sync[i].dir;
+            slave->sm_info[sm_idx].fmmu_enable = true;
+            master->actual_pdo_size += (bitlen + 7) / 8;
+
+            if (slave->config->sync[i].dir == EC_DIR_INPUT) {
+                used[EC_DIR_INPUT] = true;
+                slave->idata_size += (bitlen + 7) / 8;
+            }
+            if (slave->config->sync[i].dir == EC_DIR_OUTPUT) {
+                used[EC_DIR_OUTPUT] = true;
+                slave->odata_size += (bitlen + 7) / 8;
+            }
+        }
+
+        ec_pdo_datagram_t *pdo_datagram;
+
+        pdo_datagram = (ec_pdo_datagram_t *)ec_osal_malloc(sizeof(ec_pdo_datagram_t));
+        if (!pdo_datagram) {
+            return -1;
+        }
+        memset(pdo_datagram, 0, sizeof(ec_pdo_datagram_t));
+
+        for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+            ec_datagram_init_static(&pdo_datagram->datagrams[netdev_idx], &master->pdo_buffer[netdev_idx][slave->logical_start_address],
+                                    slave->odata_size + slave->idata_size);
+            pdo_datagram->datagrams[netdev_idx].netdev_idx = netdev_idx;
+
+            if (used[EC_DIR_OUTPUT] && used[EC_DIR_INPUT]) {
+                ec_datagram_lrw(&pdo_datagram->datagrams[netdev_idx], slave->logical_start_address, slave->odata_size + slave->idata_size);
+                pdo_datagram->datagrams[netdev_idx].lrw_read_offset = slave->odata_size;
+                pdo_datagram->datagrams[netdev_idx].lrw_read_size = slave->idata_size;
+                pdo_datagram->expected_working_counter = 3;
+            } else if (used[EC_DIR_INPUT]) {
+                ec_datagram_lrd(&pdo_datagram->datagrams[netdev_idx], slave->logical_start_address, slave->idata_size);
+                pdo_datagram->expected_working_counter = 1;
+            } else if (used[EC_DIR_OUTPUT]) {
+                ec_datagram_lwr(&pdo_datagram->datagrams[netdev_idx], slave->logical_start_address, slave->odata_size);
+                pdo_datagram->expected_working_counter = 1;
+            }
+            ec_datagram_zero(&pdo_datagram->datagrams[netdev_idx]);
+        }
+        slave->expected_working_counter = pdo_datagram->expected_working_counter;
+        master->expected_working_counter += slave->expected_working_counter;
+        pdo_datagram->slave = slave;
+
+        EC_SLAVE_LOG_INFO("Slave %u: Logical address 0x%08x, obyte %u, ibyte %u, expected working counter %u\n",
+                          slave->index,
+                          slave->logical_start_address, slave->odata_size, slave->idata_size,
+                          slave->expected_working_counter);
+
+        ec_dlist_add_tail(&master->pdo_datagram_queue, &pdo_datagram->queue);
+    }
+
+    ec_htimer_start(period_us, ec_master_period_process, master);
+
+    for (uint32_t i = 0; i < master->slave_count; i++) {
+        master->slaves[i].requested_state = EC_SLAVE_STATE_OP;
+        master->slaves[i].alstatus_code = 0;
+        master->slaves[i].force_update = true;
+    }
+    master->active = true;
+
+    ec_osal_mutex_give(master->scan_lock);
+    return 0;
+}
+
+int ec_master_stop(ec_master_t *master)
+{
+    ec_pdo_datagram_t *pdo_datagram, *n;
+    unsigned int netdev_idx;
+
+    if (!master->active) {
+        return 0;
+    }
+
+    ec_osal_mutex_take(master->scan_lock);
+    ec_htimer_stop();
+
+    for (uint32_t i = 0; i < master->slave_count; i++) {
+        master->slaves[i].requested_state = EC_SLAVE_STATE_PREOP;
+        master->slaves[i].alstatus_code = 0;
+        master->slaves[i].force_update = true;
+    }
+
+    ec_dlist_for_each_entry_safe(pdo_datagram, n, &master->pdo_datagram_queue, queue)
+    {
+        for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+            ec_datagram_clear(&pdo_datagram->datagrams[netdev_idx]);
+        }
+        ec_dlist_del_init(&pdo_datagram->queue);
+        ec_osal_free(pdo_datagram);
+    }
+
+    master->active = false;
+
+    ec_master_enter_idle(master);
+
+    ec_osal_mutex_give(master->scan_lock);
+
+    return 0;
+}
+
+int ec_master_queue_ext_datagram(ec_master_t *master, ec_datagram_t *datagram, bool wakep_poll, bool waiter)
+{
+    uintptr_t flags;
+    int ret;
+
+    flags = ec_osal_enter_critical_section();
+    datagram->waiter = waiter;
+    ec_master_queue_datagram(master, datagram);
+
+    if (wakep_poll && master->nonperiod_sem) {
+        ec_osal_sem_give(master->nonperiod_sem);
+    }
+    ec_osal_leave_critical_section(flags);
+
+    if (waiter) {
+        ret = ec_osal_sem_take(datagram->wait, EC_OSAL_WAITING_FOREVER);
+        if (ret < 0) {
+            return ret;
+        }
+
+        if (datagram->state == EC_DATAGRAM_RECEIVED) {
+            if (datagram->working_counter == 0) {
+                return -EC_ERR_WC;
+            }
+            return 0;
+        } else if (datagram->state == EC_DATAGRAM_TIMED_OUT) {
+            return -EC_ERR_TIMEOUT;
+        } else if (datagram->state == EC_DATAGRAM_ERROR) {
+            return -EC_ERR_IO;
+        } else {
+            return -EC_ERR_UNKNOWN;
+        }
+    }
+
+    return 0;
+}
+
+uint8_t *ec_master_get_slave_domain(ec_master_t *master, uint32_t slave_index)
+{
+    ec_slave_t *slave;
+
+    if (slave_index >= master->slave_count) {
+        return NULL;
+    }
+
+    slave = &master->slaves[slave_index];
+    if ((slave->odata_size + slave->idata_size) == 0) {
+        return NULL;
+    }
+
+    return &master->pdo_buffer[EC_NETDEV_MAIN][slave->logical_start_address];
+}
+
+uint8_t *ec_master_get_slave_domain_output(ec_master_t *master, uint32_t slave_index)
+{
+    ec_slave_t *slave;
+
+    if (slave_index >= master->slave_count) {
+        return NULL;
+    }
+
+    slave = &master->slaves[slave_index];
+    if (slave->odata_size == 0) {
+        return NULL;
+    }
+
+    return &master->pdo_buffer[EC_NETDEV_MAIN][slave->logical_start_address];
+}
+
+uint8_t *ec_master_get_slave_domain_input(ec_master_t *master, uint32_t slave_index)
+{
+    ec_slave_t *slave;
+
+    if (slave_index >= master->slave_count) {
+        return NULL;
+    }
+
+    slave = &master->slaves[slave_index];
+    if (slave->idata_size == 0) {
+        return NULL;
+    }
+
+    return &master->pdo_buffer[EC_NETDEV_MAIN][slave->logical_start_address + slave->idata_size];
+}
+
+uint32_t ec_master_get_slave_domain_size(ec_master_t *master, uint32_t slave_index)
+{
+    ec_slave_t *slave;
+
+    if (slave_index >= master->slave_count) {
+        return 0;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    return (slave->odata_size + slave->idata_size);
+}
+
+uint32_t ec_master_get_slave_domain_osize(ec_master_t *master, uint32_t slave_index)
+{
+    ec_slave_t *slave;
+
+    if (slave_index >= master->slave_count) {
+        return 0;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    return slave->odata_size;
+}
+
+uint32_t ec_master_get_slave_domain_isize(ec_master_t *master, uint32_t slave_index)
+{
+    ec_slave_t *slave;
+
+    if (slave_index >= master->slave_count) {
+        return 0;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    return slave->idata_size;
+}
+
+EC_FAST_CODE_SECTION static void ec_master_period_process(void *arg)
+{
+    ec_master_t *master = (ec_master_t *)arg;
+    ec_pdo_datagram_t *pdo_datagram, *n;
+    unsigned int netdev_idx;
+
+    if (master->phase != EC_OPERATION) {
+        return;
+    }
+
+#ifdef CONFIG_EC_PERF_ENABLE
+    ec_perf_polling(&master->perf);
+#endif
+    if (master->systime_diff_enable) {
+        if (master->systime_diff_mon_datagram.state == EC_DATAGRAM_RECEIVED) {
+            master->curr_systime_diff = EC_READ_U32(master->systime_diff_mon_datagram.data) & 0x7fffffff;
+
+            if (master->curr_systime_diff < master->min_systime_diff) {
+                master->min_systime_diff = master->curr_systime_diff;
+            }
+
+            if (master->curr_systime_diff > master->max_systime_diff) {
+                master->max_systime_diff = master->curr_systime_diff;
+            }
+            master->systime_diff_count++;
+            master->total_systime_diff += master->curr_systime_diff;
+        }
+
+        if ((master->interval % 10) == 0) {
+            ec_datagram_zero(&master->systime_diff_mon_datagram);
+            ec_master_queue_datagram(master, &master->systime_diff_mon_datagram);
+        }
+    }
+
+    master->actual_working_counter = 0;
+    ec_dlist_for_each_entry_safe(pdo_datagram, n, &master->pdo_datagram_queue, queue)
+    {
+        for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+            if (pdo_datagram->datagrams[netdev_idx].state == EC_DATAGRAM_RECEIVED) {
+                master->actual_working_counter += pdo_datagram->datagrams[netdev_idx].working_counter;
+                pdo_datagram->slave->actual_working_counter = pdo_datagram->datagrams[netdev_idx].working_counter;
+            }
+        }
+    }
+
+    if (master->dc_ref_clock) {
+        EC_WRITE_U32(master->dc_ref_sync_datagram.data, ec_timestamp_get_time_ns() & 0xffffffff);
+        if (master->dc_ref_clock->base_dc_range == EC_DC_64) {
+            EC_WRITE_U32(master->dc_ref_sync_datagram.data + 4, (uint32_t)(ec_timestamp_get_time_ns() >> 32));
+        }
+        ec_master_queue_datagram(master, &master->dc_ref_sync_datagram);
+
+        ec_datagram_zero(&master->dc_all_sync_datagram);
+        ec_master_queue_datagram(master, &master->dc_all_sync_datagram);
+    }
+
+    ec_dlist_for_each_entry_safe(pdo_datagram, n, &master->pdo_datagram_queue, queue)
+    {
+        ec_master_queue_datagram(master, &pdo_datagram->datagrams[EC_NETDEV_MAIN]);
+    }
+
+    ec_master_send(master);
+
+    master->interval++;
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_netdev.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_netdev.c
new file mode 100644
index 00000000..57d60b31
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_netdev.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+extern void ec_master_receive_datagrams(ec_master_t *master,
+                                        ec_netdev_index_t netdev_index,
+                                        const uint8_t *frame_data,
+                                        size_t size);
+
+/** List of intervals for statistics [s].
+ */
+const unsigned int netdev_rate_intervals[] = {
+    1, 10, 60
+};
+
+EC_FAST_CODE_SECTION void ec_netdev_clear_stats(ec_netdev_t *netdev)
+{
+    unsigned int i;
+
+    // zero frame statistics
+    netdev->tx_count = 0;
+    netdev->last_tx_count = 0;
+    netdev->rx_count = 0;
+    netdev->last_rx_count = 0;
+    netdev->tx_bytes = 0;
+    netdev->last_tx_bytes = 0;
+    netdev->rx_bytes = 0;
+    netdev->last_rx_bytes = 0;
+    netdev->tx_errors = 0;
+
+    for (i = 0; i < EC_RATE_COUNT; i++) {
+        netdev->tx_frame_rates[i] = 0;
+        netdev->rx_frame_rates[i] = 0;
+        netdev->tx_byte_rates[i] = 0;
+        netdev->rx_byte_rates[i] = 0;
+    }
+}
+
+EC_FAST_CODE_SECTION void ec_netdev_update_stats(ec_netdev_t *netdev)
+{
+    unsigned int i;
+
+    int32_t tx_frame_rate = (netdev->tx_count - netdev->last_tx_count) * 1000;
+    int32_t rx_frame_rate = (netdev->rx_count - netdev->last_rx_count) * 1000;
+    int32_t tx_byte_rate = (netdev->tx_bytes - netdev->last_tx_bytes);
+    int32_t rx_byte_rate = (netdev->rx_bytes - netdev->last_rx_bytes);
+
+    /* Low-pass filter:
+     *      Y_n = y_(n - 1) + T / tau * (x - y_(n - 1))   | T = 1
+     *   -> Y_n += (x - y_(n - 1)) / tau
+     */
+    for (i = 0; i < EC_RATE_COUNT; i++) {
+        int32_t n = netdev_rate_intervals[i];
+        netdev->tx_frame_rates[i] +=
+            (tx_frame_rate - netdev->tx_frame_rates[i]) / n;
+        netdev->rx_frame_rates[i] +=
+            (rx_frame_rate - netdev->rx_frame_rates[i]) / n;
+        netdev->tx_byte_rates[i] +=
+            (tx_byte_rate - netdev->tx_byte_rates[i]) / n;
+        netdev->rx_byte_rates[i] +=
+            (rx_byte_rate - netdev->rx_byte_rates[i]) / n;
+    }
+
+    netdev->last_tx_count = netdev->tx_count;
+    netdev->last_rx_count = netdev->rx_count;
+    netdev->last_tx_bytes = netdev->tx_bytes;
+    netdev->last_rx_bytes = netdev->rx_bytes;
+}
+
+ec_netdev_t *ec_netdev_init(uint8_t netdev_index)
+{
+    ec_netdev_t *netdev;
+
+    netdev = ec_netdev_low_level_init(netdev_index);
+    if (netdev) {
+        ec_netdev_clear_stats(netdev);
+        netdev->index = netdev_index;
+        netdev->tx_frame_index = 0;
+        netdev->link_state = false;
+
+        snprintf(netdev->name, sizeof(netdev->name), "ec-netdev%d(%s)", netdev_index, netdev_index == 0 ? "main" : "backup");
+#ifndef CONFIG_EC_PHY_CUSTOM
+        struct chry_phy_config config;
+
+        config.auto_negotiation = true;
+        config.loopback = false;
+        netdev->phydev.mdio_read = ec_mdio_low_level_read;
+        netdev->phydev.mdio_write = ec_mdio_low_level_write;
+        netdev->phydev.user_data = netdev;
+
+        EC_ASSERT_MSG(chry_phy_init(&netdev->phydev, &config) == 0, "PHY init failed for netdev %d\n", netdev_index);
+
+        EC_LOG_INFO("PHY info: \n");
+        EC_LOG_INFO("  ID: 0x%08x\n", netdev->phydev.phy_id);
+        EC_LOG_INFO("  Name: %s\n", netdev->phydev.driver->phy_name);
+        EC_LOG_INFO("  Description: %s\n", netdev->phydev.driver->phy_desc);
+#endif
+    }
+
+    return netdev;
+}
+
+void ec_netdev_poll_link_state(ec_netdev_t *netdev)
+{
+#ifndef CONFIG_EC_PHY_CUSTOM
+    struct chry_phy_status status = { 0 };
+    static struct chry_phy_status current_status = { 0 };
+
+    chry_phy_get_status(&netdev->phydev, &status);
+
+    EC_LOG_DBG("PHY link: %d, speed: %d, duplex: %d\n", status.link, status.speed, status.duplex);
+
+    if (memcmp(&current_status, &status, sizeof(struct chry_phy_status)) != 0) {
+        ec_memcpy(&current_status, &status, sizeof(struct chry_phy_status));
+
+        if (status.link) {
+            netdev->link_state = true;
+            ec_netdev_low_level_link_up(netdev, &status);
+        } else {
+            netdev->link_state = false;
+            ec_netdev_low_level_link_up(netdev, &status);
+        }
+    }
+#else
+    ec_netdev_low_level_poll_link_state(netdev);
+#endif
+}
+
+EC_FAST_CODE_SECTION uint8_t *ec_netdev_get_txbuf(ec_netdev_t *netdev)
+{
+    return (ec_netdev_low_level_get_txbuf(netdev) + ETH_HLEN);
+}
+
+EC_FAST_CODE_SECTION int ec_netdev_send(ec_netdev_t *netdev, uint32_t size)
+{
+    if (ec_netdev_low_level_output(netdev, size + ETH_HLEN) == 0) {
+        netdev->tx_count++;
+        netdev->master->netdev_stats.tx_count++;
+        netdev->tx_bytes += ETH_HLEN + size;
+        netdev->master->netdev_stats.tx_bytes += ETH_HLEN + size;
+
+        return 0;
+    } else {
+        netdev->tx_errors++;
+        return -1;
+    }
+}
+
+EC_FAST_CODE_SECTION void ec_netdev_receive(ec_netdev_t *netdev, uint8_t *frame, uint32_t size)
+{
+    const uint8_t *ec_data = frame + ETH_HLEN;
+    uint32_t ec_size = size - ETH_HLEN;
+
+    netdev->rx_count++;
+    netdev->master->netdev_stats.rx_count++;
+    netdev->rx_bytes += size;
+    netdev->master->netdev_stats.rx_bytes += size;
+
+    ec_master_receive_datagrams(netdev->master, netdev->index, ec_data, ec_size);
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_perf.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_perf.c
new file mode 100644
index 00000000..c404e56e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_perf.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+#ifdef CONFIG_EC_PERF_ENABLE
+void ec_perf_init(ec_perf_t *perf, uint64_t expected_interval_us)
+{
+    memset(perf, 0, sizeof(ec_perf_t));
+
+    perf->enable = true;
+    perf->min_interval = UINT64_MAX;
+    perf->max_interval = 0;
+    perf->min_jitter = INT64_MAX;
+    perf->max_jitter = INT64_MIN;
+    perf->expected_interval = expected_interval_us;
+    perf->ignore_count = 5;
+
+    EC_LOG_RAW("Perf initialized\n");
+    EC_LOG_RAW("Expected interval: %llu us\n", expected_interval_us);
+}
+
+EC_FAST_CODE_SECTION void ec_perf_polling(ec_perf_t *perf)
+{
+    uint64_t current_timestamp = jiffies;
+
+    if (!perf->enable) {
+        return;
+    }
+
+    if (perf->ignore_count > 0) {
+        perf->ignore_count--;
+        perf->last_timestamp = current_timestamp;
+        return;
+    }
+
+    uint64_t interval = current_timestamp - perf->last_timestamp;
+    int64_t jitter = (int64_t)interval - (int64_t)perf->expected_interval;
+
+    if (interval < perf->min_interval)
+        perf->min_interval = interval;
+    if (interval > perf->max_interval)
+        perf->max_interval = interval;
+    if (jitter < perf->min_jitter)
+        perf->min_jitter = jitter;
+    if (jitter > perf->max_jitter)
+        perf->max_jitter = jitter;
+
+    perf->total_interval += interval;
+    perf->total_jitter += jitter;
+
+    perf->count++;
+    perf->last_timestamp = current_timestamp;
+}
+
+void ec_perf_print_statistics(ec_perf_t *perf)
+{
+    if (perf->count == 0)
+        return;
+
+    double avg_interval = (double)perf->total_interval / perf->count;
+    double avg_jitter = (double)perf->total_jitter / perf->count;
+
+    EC_LOG_RAW("\n========= Perf Statistics =========\n");
+    EC_LOG_RAW("Measurements: %lld\n", perf->count);
+    EC_LOG_RAW("\nInterval Statistics (us):\n");
+    EC_LOG_RAW("  Average:    %.2f\n", avg_interval);
+    EC_LOG_RAW("  Minimum:    %llu\n", perf->min_interval);
+    EC_LOG_RAW("  Maximum:    %llu\n", perf->max_interval);
+
+    EC_LOG_RAW("\nJitter Statistics (us):\n");
+    EC_LOG_RAW("  Average:        %.2f\n", avg_jitter);
+    EC_LOG_RAW("  Minimum:        %lld\n", perf->min_jitter);
+    EC_LOG_RAW("  Maximum:        %lld\n", perf->max_jitter);
+
+    EC_LOG_RAW("===================================\n");
+}
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_sii.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_sii.c
new file mode 100644
index 00000000..34f75e71
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_sii.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+#define SII_TIMEOUT_US (200 * 1000) // 200ms
+
+static int ec_sii_assign_master(ec_slave_t *slave, ec_datagram_t *datagram)
+{
+    // assign SII to ECAT
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->EEPROM_CFG), 1);
+    EC_WRITE_U8(datagram->data, 0x00);
+    datagram->netdev_idx = slave->netdev_idx;
+    return ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+}
+
+static int esc_sii_assign_pdi(ec_slave_t *slave, ec_datagram_t *datagram)
+{
+    // assign SII to PDI
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->EEPROM_CFG), 1);
+    EC_WRITE_U8(datagram->data, 0x01);
+    datagram->netdev_idx = slave->netdev_idx;
+    return ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+}
+
+static int ec_sii_read_dword(ec_slave_t *slave, ec_datagram_t *datagram, uint16_t woffset, uint32_t *value)
+{
+    uint32_t start_time;
+    int ret;
+
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->EEPROM_CTRL_STAT), 4);
+    EC_WRITE_U8(datagram->data, 0x80);         // two address bytes
+    EC_WRITE_U8(datagram->data + 1, 0x01);     // read command
+    EC_WRITE_U16(datagram->data + 2, woffset); // word offset
+
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    start_time = jiffies;
+sii_check:
+    // read with 4 bytes
+    ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->EEPROM_CTRL_STAT), 10);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (EC_READ_U16(datagram->data) & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT) {
+        return -EC_ERR_SII;
+    }
+
+    if (EC_READ_U16(datagram->data) & ESC_EEPROM_CTRL_STAT_BUSY_MASK) {
+        if ((jiffies - start_time) > SII_TIMEOUT_US) {
+            return -EC_ERR_TIMEOUT;
+        }
+        goto sii_check;
+    }
+
+    ec_memcpy(value, datagram->data + 6, 4);
+
+    return 0;
+}
+
+static int ec_sii_write_word(ec_slave_t *slave, ec_datagram_t *datagram, uint16_t woffset, uint16_t value)
+{
+    uint32_t start_time;
+    int ret;
+
+    // write with 2 bytes
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->EEPROM_CTRL_STAT), 8);
+    EC_WRITE_U8(datagram->data, 0x81);         // two address bytes + enable write access
+    EC_WRITE_U8(datagram->data + 1, 0x02);     // write command
+    EC_WRITE_U16(datagram->data + 2, woffset); // word offset
+    EC_WRITE_U16(datagram->data + 4, 0x00);
+    EC_WRITE_U16(datagram->data + 6, value);
+
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    start_time = jiffies;
+sii_check:
+    ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->EEPROM_CTRL_STAT), 2);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (EC_READ_U16(datagram->data) & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT) {
+        return -EC_ERR_SII;
+    }
+
+    if (EC_READ_U16(datagram->data) & ESC_EEPROM_CTRL_STAT_BUSY_MASK) {
+        if ((jiffies - start_time) > SII_TIMEOUT_US) {
+            return -EC_ERR_TIMEOUT;
+        }
+        goto sii_check;
+    }
+
+    if (EC_READ_U16(datagram->data) & ESC_EEPROM_CTRL_STAT_ERR_WEN_MASK) {
+        return -EC_ERR_SII;
+    }
+
+    return 0;
+}
+
+int ec_sii_read(ec_master_t *master, uint16_t slave_index, ec_datagram_t *datagram, uint16_t woffset, uint32_t *buf, uint32_t len)
+{
+    ec_slave_t *slave;
+    int ret;
+
+    if (len % 4) {
+        return -EC_ERR_INVAL;
+    }
+
+    if (slave_index >= master->slave_count) {
+        return -EC_ERR_INVAL;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    ret = ec_sii_assign_master(slave, datagram);
+    if (ret < 0) {
+        return ret;
+    }
+
+    for (uint32_t i = 0; i < (len / 4); i++) {
+        ret = ec_sii_read_dword(slave, datagram, woffset + i * 2, &buf[i]);
+        if (ret < 0) {
+            return ret;
+        }
+    }
+
+    return esc_sii_assign_pdi(slave, datagram);
+}
+
+int ec_sii_write(ec_master_t *master, uint16_t slave_index, ec_datagram_t *datagram, uint16_t woffset, const uint16_t *buf, uint32_t len)
+{
+    ec_slave_t *slave;
+    int ret;
+
+    if (len % 2) {
+        return -EC_ERR_INVAL;
+    }
+
+    if (slave_index >= master->slave_count) {
+        return -EC_ERR_INVAL;
+    }
+
+    slave = &master->slaves[slave_index];
+
+    ret = ec_sii_assign_master(slave, datagram);
+    if (ret < 0) {
+        return ret;
+    }
+
+    for (uint32_t i = 0; i < (len / 2); i++) {
+        ret = ec_sii_write_word(slave, datagram, woffset + i, buf[i]);
+        if (ret < 0) {
+            return ret;
+        }
+    }
+
+    return esc_sii_assign_pdi(slave, datagram);
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_slave.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_slave.c
new file mode 100644
index 00000000..ce12c7ea
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_slave.c
@@ -0,0 +1,1360 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+/** Maximum clock difference (in ns) before going to SAFEOP.
+ *
+ * Wait for DC time difference to drop under this absolute value before
+ * requesting SAFEOP.
+ */
+#define EC_DC_MAX_SYNC_DIFF_NS 100
+
+/** Maximum count to wait for clock discipline.
+ */
+#define EC_DC_SYNC_WAIT_COUNT (15000)
+
+/** Time offset (in ns), that is added to cyclic start time.
+ */
+#define EC_DC_START_OFFSET 100000000ULL
+
+static void ec_slave_init(ec_slave_t *slave,
+                          uint32_t slave_index,
+                          ec_master_t *master,
+                          ec_netdev_index_t netdev_idx,
+                          uint16_t autoinc_address,
+                          uint16_t station_address)
+{
+    slave->index = slave_index;
+    slave->master = master;
+    slave->netdev_idx = netdev_idx;
+    slave->autoinc_address = autoinc_address;
+    slave->station_address = station_address;
+
+    slave->requested_state = EC_SLAVE_STATE_PREOP;
+}
+
+static void ec_slave_clear(ec_slave_t *slave)
+{
+    int i;
+
+    if (slave->sii_image) {
+        ec_osal_free(slave->sii_image);
+        slave->sii_image = NULL;
+        slave->sii_nwords = 0;
+    }
+
+    if (slave->sii.strings) {
+        for (i = 0; i < slave->sii.string_count; i++)
+            ec_osal_free(slave->sii.strings[i]);
+        ec_osal_free(slave->sii.strings);
+        slave->sii.strings = NULL;
+    }
+}
+
+static int ec_slave_fetch_sii_strings(ec_slave_t *slave, const uint8_t *data, size_t data_size)
+{
+    int i, ret;
+    uint32_t size;
+    uint32_t offset;
+
+    slave->sii.string_count = data[0];
+
+    if (slave->sii.string_count) {
+        slave->sii.strings = ec_osal_malloc(sizeof(char *) * slave->sii.string_count);
+        if (!slave->sii.strings) {
+            EC_SLAVE_LOG_ERR("Failed to allocate string array memory\n");
+            ret = -EC_ERR_NOMEM;
+            goto errorout1;
+        }
+
+        offset = 1;
+        for (i = 0; i < slave->sii.string_count; i++) {
+            size = data[offset];
+
+            slave->sii.strings[i] = ec_osal_malloc(sizeof(char) * size + 1);
+            if (!slave->sii.strings[i]) {
+                EC_SLAVE_LOG_ERR("Failed to allocate string memory\n");
+                ret = -EC_ERR_NOMEM;
+                goto errorout2;
+            }
+
+            ec_memcpy(slave->sii.strings[i], data + offset + 1, size);
+            slave->sii.strings[i][size] = 0x00;
+            offset += 1 + size;
+        }
+    }
+
+    return 0;
+
+errorout2:
+    for (i = 0; i < slave->sii.string_count; i++) {
+        ec_osal_free(slave->sii.strings[i]);
+    }
+    ec_osal_free(slave->sii.strings);
+    slave->sii.strings = NULL;
+errorout1:
+    slave->sii.string_count = 0;
+    return ret;
+}
+
+/** Get timeout in us.
+ *
+ * For defaults see ETG2000_S_R_V1i0i15 section 5.3.6.2.
+ */
+unsigned int ec_slave_state_change_timeout_us(ec_slave_state_t old_state, ec_slave_state_t requested_state)
+{
+    ec_slave_state_t from = old_state;
+    ec_slave_state_t to = requested_state;
+
+    if (from == EC_SLAVE_STATE_INIT &&
+        (to == EC_SLAVE_STATE_PREOP || to == EC_SLAVE_STATE_BOOT)) {
+        return (3000 * 1000); // PreopTimeout
+    }
+    if ((from == EC_SLAVE_STATE_PREOP && to == EC_SLAVE_STATE_SAFEOP) ||
+        (from == EC_SLAVE_STATE_SAFEOP && to == EC_SLAVE_STATE_OP)) {
+        return (10000 * 1000); // SafeopOpTimeout
+    }
+    if (to == EC_SLAVE_STATE_INIT ||
+        ((from == EC_SLAVE_STATE_OP || from == EC_SLAVE_STATE_SAFEOP) && to == EC_SLAVE_STATE_PREOP)) {
+        return (5000 * 1000); // BackToInitTimeout
+    }
+    if (from == EC_SLAVE_STATE_OP && to == EC_SLAVE_STATE_SAFEOP) {
+        return (200 * 1000); // BackToSafeopTimeout
+    }
+
+    return (10000 * 1000); // default [us]
+}
+
+static uint8_t ec_slave_get_previous_port(const ec_slave_t *slave, uint8_t port_index)
+{
+    static const uint8_t prev_table[EC_MAX_PORTS] = {
+        2, 3, 1, 0
+    };
+
+    do {
+        port_index = prev_table[port_index];
+        if (slave->ports[port_index].next_slave) {
+            return port_index;
+        }
+    } while (port_index);
+
+    return 0;
+}
+
+static uint8_t ec_slave_get_next_port(const ec_slave_t *slave, uint8_t port_index)
+{
+    static const uint8_t next_table[EC_MAX_PORTS] = {
+        3, 2, 0, 1
+    };
+
+    do {
+        port_index = next_table[port_index];
+        if (slave->ports[port_index].next_slave) {
+            return port_index;
+        }
+    } while (port_index);
+
+    return 0;
+}
+
+/** Calculates the sum of round-trip-times of connected ports 1-3.
+ *
+ * \return Round-trip-time in ns.
+ */
+static uint32_t ec_slave_calc_rtt_sum(const ec_slave_t *slave)
+{
+    uint32_t rtt_sum = 0, rtt;
+    uint8_t port_index = ec_slave_get_next_port(slave, 0);
+
+    while (port_index != 0) {
+        uint8_t prev_index =
+            ec_slave_get_previous_port(slave, port_index);
+
+        rtt = slave->ports[port_index].receive_time -
+              slave->ports[prev_index].receive_time;
+        rtt_sum += rtt;
+        port_index = ec_slave_get_next_port(slave, port_index);
+    }
+
+    return rtt_sum;
+}
+
+/** Finds the next slave supporting DC delay measurement.
+ *
+ * \return Next DC slave, or NULL.
+ */
+static ec_slave_t *ec_slave_find_next_dc_slave(ec_slave_t *slave)
+{
+    uint8_t port_index;
+    ec_slave_t *dc_slave = NULL;
+
+    if (slave->base_dc_supported) {
+        dc_slave = slave;
+    } else {
+        port_index = ec_slave_get_next_port(slave, 0);
+
+        while (port_index != 0) {
+            ec_slave_t *next = slave->ports[port_index].next_slave;
+
+            if (next) {
+                dc_slave = ec_slave_find_next_dc_slave(next);
+
+                if (dc_slave) {
+                    break;
+                }
+            }
+            port_index = ec_slave_get_next_port(slave, port_index);
+        }
+    }
+
+    return dc_slave;
+}
+
+void ec_slave_calc_port_delays(ec_slave_t *slave)
+{
+    uint8_t port_index;
+    ec_slave_t *next_slave, *next_dc;
+    uint32_t rtt, next_rtt_sum;
+
+    if (!slave->base_dc_supported)
+        return;
+
+    port_index = ec_slave_get_next_port(slave, 0);
+
+    while (port_index != 0) {
+        next_slave = slave->ports[port_index].next_slave;
+        next_dc = ec_slave_find_next_dc_slave(next_slave);
+
+        if (next_dc) {
+            uint8_t prev_port =
+                ec_slave_get_previous_port(slave, port_index);
+
+            rtt = slave->ports[port_index].receive_time -
+                  slave->ports[prev_port].receive_time;
+            next_rtt_sum = ec_slave_calc_rtt_sum(next_dc);
+
+            slave->ports[port_index].delay_to_next_dc =
+                (rtt - next_rtt_sum) / 2;
+            next_dc->ports[0].delay_to_next_dc =
+                (rtt - next_rtt_sum) / 2;
+        }
+
+        port_index = ec_slave_get_next_port(slave, port_index);
+    }
+}
+
+void ec_slave_calc_transmission_delays(ec_slave_t *slave, uint32_t *delay)
+{
+    unsigned int i;
+    ec_slave_t *next_dc;
+
+    slave->transmission_delay = *delay;
+
+    i = ec_slave_get_next_port(slave, 0);
+
+    while (i != 0) {
+        ec_slave_port_t *port = &slave->ports[i];
+        next_dc = ec_slave_find_next_dc_slave(port->next_slave);
+        if (next_dc) {
+            *delay = *delay + port->delay_to_next_dc;
+
+            ec_slave_calc_transmission_delays(next_dc, delay);
+        }
+
+        i = ec_slave_get_next_port(slave, i);
+    }
+
+    *delay = *delay + slave->ports[0].delay_to_next_dc;
+}
+
+static int ec_slave_state_clear_ack_error(ec_slave_t *slave, ec_slave_state_t requested_state)
+{
+    ec_datagram_t *datagram;
+    int ret;
+    uint64_t start_time;
+    uint32_t status_code;
+
+    datagram = &slave->master->main_datagram;
+
+    start_time = jiffies;
+
+    ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->AL_STAT_CODE), 2);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    status_code = EC_READ_U16(datagram->data);
+
+    slave->alstatus_code = status_code;
+
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->AL_CTRL), 2);
+    EC_WRITE_U16(datagram->data, slave->current_state);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+repeat_check:
+    ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->AL_STAT), 2);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    slave->current_state = EC_READ_U8(datagram->data);
+
+    if (!(slave->current_state & EC_SLAVE_STATE_ACK_ERR)) {
+        if (slave->current_state == slave->requested_state) {
+            return 0;
+        } else {
+            EC_SLAVE_LOG_ERR("Slave %u acked state %s, alstatus code: 0x%04x (%s)\n",
+                             slave->index,
+                             ec_state_string(slave->current_state, 0),
+                             status_code,
+                             ec_alstatus_string(status_code));
+
+            return -EC_ERR_ALERR;
+        }
+    } else {
+        if ((jiffies - start_time) > ec_slave_state_change_timeout_us(slave->current_state, requested_state)) {
+            return -EC_ERR_TIMEOUT;
+        }
+        goto repeat_check;
+    }
+}
+
+/* ec_slave_state_change - change slave state
+ *
+ * 1. write AL control register
+ * 2. read AL status register
+ * 3. if state is changed to correct state, return success
+ * 4. if state is not changed and acknowledge bit is set, read AL status code
+ *    and write AL control register to acknowledge error, then repeat 2
+ * 5. if state is changed to other state, repeat step 2
+*/
+static int ec_slave_state_change(ec_slave_t *slave, ec_slave_state_t requested_state)
+{
+    ec_datagram_t *datagram;
+    int ret;
+    uint32_t start_time;
+    ec_slave_state_t old_state;
+
+    datagram = &slave->master->main_datagram;
+
+    old_state = slave->current_state;
+    start_time = jiffies;
+
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->AL_CTRL), 2);
+    EC_WRITE_U16(datagram->data, requested_state);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+repeat_check:
+    ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->AL_STAT), 2);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    slave->current_state = EC_READ_U8(datagram->data);
+
+    if (slave->current_state == requested_state) {
+        EC_SLAVE_LOG_INFO("Slave %u State changed to %s\n", slave->index, ec_state_string(slave->current_state, 0));
+        return 0;
+    }
+
+    if (slave->current_state != old_state) {
+        if ((slave->current_state & 0x0F) == (old_state & 0x0F)) { // acknowledge bit enable
+            return ec_slave_state_clear_ack_error(slave, requested_state);
+        } else {
+            old_state = slave->current_state;
+            if ((jiffies - start_time) > ec_slave_state_change_timeout_us(slave->current_state, requested_state)) {
+                return -EC_ERR_TIMEOUT;
+            }
+            goto repeat_check;
+        }
+    }
+
+    // still in old state
+    if ((jiffies - start_time) > ec_slave_state_change_timeout_us(slave->current_state, requested_state)) {
+        return -EC_ERR_TIMEOUT;
+    }
+    goto repeat_check;
+}
+
+static inline void ec_slave_sm_config(ec_sm_info_t *sm, uint8_t *data)
+{
+    EC_WRITE_U16(data, sm->physical_start_address);
+    EC_WRITE_U16(data + 2, sm->length);
+    EC_WRITE_U8(data + 4, sm->control);
+    EC_WRITE_U8(data + 5, 0x00); // status byte (read only)
+    EC_WRITE_U16(data + 6, sm->enable);
+}
+
+static inline void ec_slave_fmmu_config(ec_sm_info_t *sm, uint8_t *data)
+{
+    EC_WRITE_U32(data, sm->fmmu.logical_start_address);
+    EC_WRITE_U16(data + 4, sm->fmmu.data_size); // size of fmmu
+    EC_WRITE_U8(data + 6, 0x00);                // logical start bit
+    EC_WRITE_U8(data + 7, 0x07);                // logical end bit
+    EC_WRITE_U16(data + 8, sm->physical_start_address);
+    EC_WRITE_U8(data + 10, 0x00); // physical start bit
+    EC_WRITE_U8(data + 11, sm->fmmu.dir == EC_DIR_INPUT ? 0x01 : 0x02);
+    EC_WRITE_U16(data + 12, 0x0001); // enable
+    EC_WRITE_U16(data + 14, 0x0000); // reserved
+}
+
+static int ec_slave_config_dc_systime_and_delay(ec_slave_t *slave)
+{
+    ec_datagram_t *datagram;
+    uint64_t system_time, old_system_time_offset, new_system_time_offset;
+    uint64_t time_diff;
+    int ret;
+
+    datagram = &slave->master->main_datagram;
+
+    if (slave->base_dc_supported && slave->has_dc_system_time) {
+        ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->SYS_TIME), 24);
+        datagram->netdev_idx = slave->netdev_idx;
+        ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+        if (ret < 0) {
+            return ret;
+        }
+        system_time = EC_READ_U64(datagram->data);
+        old_system_time_offset = EC_READ_U64(datagram->data + 16);
+        time_diff = ec_timestamp_get_time_ns() - system_time;
+
+        if (slave->base_dc_range == EC_DC_32) {
+            system_time = (uint32_t)system_time + datagram->jiffies_sent * 1000;
+            old_system_time_offset = (uint32_t)old_system_time_offset;
+        } else {
+            system_time = system_time + datagram->jiffies_sent * 1000;
+        }
+
+        if (time_diff > 1000000) { // 1ms
+            new_system_time_offset = time_diff + old_system_time_offset;
+        } else {
+            new_system_time_offset = old_system_time_offset;
+        }
+
+        // set DC system time offset and transmission delay
+        ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->SYS_TIME_OFFSET), 12);
+        EC_WRITE_U64(datagram->data, new_system_time_offset);
+        EC_WRITE_U32(datagram->data + 8, slave->transmission_delay);
+        datagram->netdev_idx = slave->netdev_idx;
+        ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+        if (ret < 0) {
+            return ret;
+        }
+    }
+
+    return 0;
+}
+
+static int ec_slave_config(ec_slave_t *slave)
+{
+    ec_datagram_t *datagram;
+    uint64_t start_time;
+    int ret;
+
+    datagram = &slave->master->main_datagram;
+
+    ret = ec_slave_state_change(slave, EC_SLAVE_STATE_INIT);
+    if (ret < 0) {
+        return ret;
+    }
+
+    // clear FMMU configurations
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->FMMU[0]), EC_FMMU_PAGE_SIZE * slave->base_fmmu_count);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    // clear sync manager configurations
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->SYNCM[0]), EC_SYNC_PAGE_SIZE * slave->base_sync_count);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    // Clear the DC assignment
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->CYC_UNIT_CTRL), 2);
+    ec_datagram_zero(datagram);
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    // init state done
+    if (slave->current_state == slave->requested_state) {
+        return 0;
+    }
+
+    if (slave->requested_state == EC_SLAVE_STATE_BOOT) {
+        ec_sm_info_t sm_info[2];
+
+        sm_info[0].physical_start_address = slave->sii.boot_rx_mailbox_offset;
+        sm_info[0].control = 0x26;
+        sm_info[0].length = slave->sii.boot_rx_mailbox_size;
+        sm_info[0].enable = 0x01;
+
+        sm_info[1].physical_start_address = slave->sii.boot_tx_mailbox_offset;
+        sm_info[1].control = 0x22;
+        sm_info[1].length = slave->sii.boot_tx_mailbox_size;
+        sm_info[1].enable = 0x01;
+
+        // Config mailbox sm
+        ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->SYNCM[0]), EC_SYNC_PAGE_SIZE * 2);
+        ec_datagram_zero(datagram);
+        for (uint8_t i = 0; i < 2; i++) {
+            ec_slave_sm_config(&sm_info[i], datagram->data + EC_SYNC_PAGE_SIZE * i);
+        }
+        datagram->netdev_idx = slave->netdev_idx;
+        ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+        if (ret < 0) {
+            return ret;
+        }
+
+        slave->configured_rx_mailbox_offset = slave->sii.boot_rx_mailbox_offset;
+        slave->configured_rx_mailbox_size = slave->sii.boot_rx_mailbox_size;
+        slave->configured_tx_mailbox_offset = slave->sii.boot_tx_mailbox_offset;
+        slave->configured_tx_mailbox_size = slave->sii.boot_tx_mailbox_size;
+
+        ret = ec_slave_state_change(slave, EC_SLAVE_STATE_BOOT);
+        if (ret < 0) {
+            EC_SLAVE_LOG_ERR("Failed to change state to %s on slave %u\n",
+                             ec_state_string(slave->requested_state, 0), slave->index);
+            return ret;
+        }
+
+        return 0;
+    }
+
+    // Config mailbox sm
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->SYNCM[0]), EC_SYNC_PAGE_SIZE * 2);
+    ec_datagram_zero(datagram);
+    for (uint8_t i = 0; i < 2; i++) {
+        ec_slave_sm_config(&slave->sm_info[i], datagram->data + EC_SYNC_PAGE_SIZE * i);
+    }
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    slave->configured_rx_mailbox_offset = slave->sm_info[EC_SM_INDEX_MBX_WRITE].physical_start_address;
+    slave->configured_rx_mailbox_size = slave->sm_info[EC_SM_INDEX_MBX_WRITE].length;
+    slave->configured_tx_mailbox_offset = slave->sm_info[EC_SM_INDEX_MBX_READ].physical_start_address;
+    slave->configured_tx_mailbox_size = slave->sm_info[EC_SM_INDEX_MBX_READ].length;
+
+    ret = ec_slave_state_change(slave, EC_SLAVE_STATE_PREOP);
+    if (ret < 0) {
+        EC_SLAVE_LOG_ERR("Failed to change state to %s on slave %u\n",
+                         ec_state_string(slave->requested_state, 0), slave->index);
+        return ret;
+    }
+
+    if (slave->config && slave->sii.general.coe_details.enable_pdo_assign) {
+        uint32_t data;
+
+        /* Config PDO assignments for 0x1c12, 0x1c13
+         *
+         * Clear existing assignments first
+         * Reassign all entries
+         * Set number of assigned entries
+        */
+        data = 0;
+        ret = ec_coe_download(slave->master, slave->index, datagram, 0x1c12, 0x00, &data, 2, false);
+        if (ret < 0) {
+            return ret;
+        }
+        ret = ec_coe_download(slave->master, slave->index, datagram, 0x1c13, 0x00, &data, 2, false);
+        if (ret < 0) {
+            return ret;
+        }
+        for (uint32_t i = 0; i < slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.count; i++) {
+            data = slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.entry[i];
+            ret = ec_coe_download(slave->master, slave->index, datagram, 0x1c12, 0x01 + i, &data, 2, false);
+            if (ret < 0) {
+                return ret;
+            }
+        }
+        for (uint32_t i = 0; i < slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.count; i++) {
+            data = slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.entry[i];
+            ret = ec_coe_download(slave->master, slave->index, datagram, 0x1c13, 0x01 + i, &data, 2, false);
+            if (ret < 0) {
+                return ret;
+            }
+        }
+        data = slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.count;
+        ret = ec_coe_download(slave->master, slave->index, datagram, 0x1c12, 0x00, &data, 2, false);
+        if (ret < 0) {
+            return ret;
+        }
+        data = slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.count;
+        ret = ec_coe_download(slave->master, slave->index, datagram, 0x1c13, 0x00, &data, 2, false);
+        if (ret < 0) {
+            return ret;
+        }
+
+        /* Config PDO mappings
+         *
+         * Clear existing mappings first
+         * Remap all entries
+         * Set number of mapped entries
+        */
+        if (slave->sii.general.coe_details.enable_pdo_configuration) {
+            for (uint32_t i = 0; i < slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.count; i++) {
+                data = 0;
+                ret = ec_coe_download(slave->master, slave->index, datagram, slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.entry[i], 0x00, &data, 1, false);
+                if (ret < 0) {
+                    return ret;
+                }
+
+                for (uint32_t j = 0; j < slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_mapping[i].count; j++) {
+                    data = slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_mapping[i].entry[j];
+                    ret = ec_coe_download(slave->master, slave->index, datagram, slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.entry[i], 0x01 + j, &data, 4, false);
+                    if (ret < 0) {
+                        return ret;
+                    }
+                }
+
+                data = slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_mapping[i].count;
+                ret = ec_coe_download(slave->master, slave->index, datagram, slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT].pdo_assign.entry[i], 0x00, &data, 1, false);
+                if (ret < 0) {
+                    return ret;
+                }
+            }
+
+            for (uint32_t i = 0; i < slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.count; i++) {
+                data = 0;
+                ret = ec_coe_download(slave->master, slave->index, datagram, slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.entry[i], 0x00, &data, 1, false);
+                if (ret < 0) {
+                    return ret;
+                }
+
+                for (uint32_t j = 0; j < slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_mapping[i].count; j++) {
+                    data = slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_mapping[i].entry[j];
+                    ret = ec_coe_download(slave->master, slave->index, datagram, slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.entry[i], 0x01 + j, &data, 4, false);
+                    if (ret < 0) {
+                        return ret;
+                    }
+                }
+
+                data = slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_mapping[i].count;
+                ret = ec_coe_download(slave->master, slave->index, datagram, slave->sm_info[EC_SM_INDEX_PROCESS_DATA_INPUT].pdo_assign.entry[i], 0x00, &data, 1, false);
+                if (ret < 0) {
+                    return ret;
+                }
+            }
+        }
+    }
+
+    // preop state done
+    if (slave->current_state == slave->requested_state) {
+        return 0;
+    }
+
+    // Config process data sm
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->SYNCM[2]), EC_SYNC_PAGE_SIZE * 2);
+    ec_datagram_zero(datagram);
+    for (uint8_t i = 0; i < 2; i++) {
+        ec_slave_sm_config(&slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT + i], datagram->data + EC_SYNC_PAGE_SIZE * i);
+    }
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->FMMU[0]), EC_FMMU_PAGE_SIZE * 2);
+    ec_datagram_zero(datagram);
+    for (uint8_t i = 0; i < 2; i++) {
+        ec_slave_fmmu_config(&slave->sm_info[EC_SM_INDEX_PROCESS_DATA_OUTPUT + i], datagram->data + EC_FMMU_PAGE_SIZE * i);
+    }
+    datagram->netdev_idx = slave->netdev_idx;
+    ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (slave->config && slave->config->dc_assign_activate) {
+        if (!slave->base_dc_supported) {
+            EC_SLAVE_LOG_WRN("Slave %u does not support DC, but DC is activated in master config\n", slave->index);
+        }
+
+        ec_slave_config_dc_systime_and_delay(slave);
+
+        // set DC cycle times
+        ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->SYNC0_CYC_TIME), 8);
+        EC_WRITE_U32(datagram->data, slave->config->dc_sync[0].cycle_time);
+        EC_WRITE_U32(datagram->data + 4, slave->config->dc_sync[1].cycle_time);
+        datagram->netdev_idx = slave->netdev_idx;
+        ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+        if (ret < 0) {
+            return ret;
+        }
+
+        start_time = 0;
+    read_check:
+        ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->SYS_TIME_DIFF), 4);
+        ec_datagram_zero(datagram);
+        datagram->netdev_idx = slave->netdev_idx;
+        ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+        if (ret < 0) {
+            return ret;
+        }
+
+        uint32_t time_diff = EC_READ_U32(datagram->data) & 0x7fffffff;
+        if (time_diff > EC_DC_MAX_SYNC_DIFF_NS) {
+            start_time++;
+            if (start_time > EC_DC_SYNC_WAIT_COUNT) {
+                EC_SLAVE_LOG_ERR("Slave %u DC time diff sync failed\n",
+                                 slave->index);
+                return -EC_ERR_TIMEOUT;
+            }
+            goto read_check;
+        } else {
+            EC_SLAVE_LOG_INFO("Slave %u DC time diff: %u ns\n", slave->index, time_diff);
+        }
+
+        uint64_t dc_start_time;
+        uint32_t remainder = EC_DC_START_OFFSET / (slave->config->dc_sync[0].cycle_time + slave->config->dc_sync[1].cycle_time);
+
+        dc_start_time = ec_timestamp_get_time_ns() + EC_DC_START_OFFSET +
+                        slave->config->dc_sync[0].cycle_time + slave->config->dc_sync[1].cycle_time - remainder +
+                        slave->config->dc_sync[0].shift_time;
+        ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->START_TIME_CO), 8);
+
+        EC_WRITE_U64(datagram->data, dc_start_time);
+        datagram->netdev_idx = slave->netdev_idx;
+        ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+        if (ret < 0) {
+            return ret;
+        }
+
+        ec_datagram_fpwr(datagram, slave->station_address, ESCREG_OF(ESCREG->CYC_UNIT_CTRL), 2);
+        EC_WRITE_U16(datagram->data, slave->config->dc_assign_activate);
+        datagram->netdev_idx = slave->netdev_idx;
+        ret = ec_master_queue_ext_datagram(slave->master, datagram, true, true);
+        if (ret < 0) {
+            return ret;
+        }
+    }
+
+    ret = ec_slave_state_change(slave, EC_SLAVE_STATE_SAFEOP);
+    if (ret < 0) {
+        EC_SLAVE_LOG_ERR("Failed to change state to %s on slave %u\n",
+                         ec_state_string(slave->requested_state, 0), slave->index);
+        return ret;
+    }
+
+    // safeop state done
+    if (slave->current_state == slave->requested_state) {
+        return 0;
+    }
+
+    ret = ec_slave_state_change(slave, EC_SLAVE_STATE_OP);
+    if (ret < 0) {
+        EC_SLAVE_LOG_ERR("Failed to change state to %s on slave %u\n",
+                         ec_state_string(slave->requested_state, 0), slave->index);
+        return ret;
+    }
+
+    return 0;
+}
+
+static void ec_master_clear_slaves(ec_master_t *master)
+{
+    ec_slave_t *slave;
+
+    if (master->slaves) {
+        for (uint32_t slave_index = 0; slave_index < master->slave_count; slave_index++) {
+            slave = master->slaves + slave_index;
+            ec_slave_clear(slave);
+        }
+
+        ec_osal_free(master->slaves);
+        master->slaves = NULL;
+    }
+
+    master->slave_count = 0;
+}
+
+static int ec_master_calc_topology_rec(ec_master_t *master, ec_slave_t *port0_slave, unsigned int *slave_position)
+{
+    ec_slave_t *slave = master->slaves + *slave_position;
+    unsigned int port_index;
+    int ret;
+
+    static const unsigned int next_table[EC_MAX_PORTS] = {
+        3, 2, 0, 1
+    };
+
+    slave->ports[0].next_slave = port0_slave;
+
+    port_index = 3;
+    while (port_index != 0) {
+        if (!slave->ports[port_index].link.loop_closed) {
+            *slave_position = *slave_position + 1;
+            if (*slave_position < master->slave_count) {
+                slave->ports[port_index].next_slave =
+                    master->slaves + *slave_position;
+                ret = ec_master_calc_topology_rec(master,
+                                                  slave, slave_position);
+                if (ret) {
+                    return ret;
+                }
+            } else {
+                return -1;
+            }
+        }
+
+        port_index = next_table[port_index];
+    }
+
+    return 0;
+}
+
+static void ec_master_find_dc_ref_clock(ec_master_t *master)
+{
+    ec_slave_t *slave, *ref = NULL;
+
+    // Use first slave with DC support as reference clock
+    for (slave = master->slaves;
+         slave < master->slaves + master->slave_count;
+         slave++) {
+        if (slave->base_dc_supported && slave->has_dc_system_time) {
+            ref = slave;
+            break;
+        }
+    }
+
+    master->dc_ref_clock = ref;
+
+    if (ref) {
+        EC_LOG_INFO("Using slave %u as DC reference clock\n", ref->index);
+    } else {
+        EC_LOG_INFO("No DC reference clock found\n");
+    }
+
+    ec_datagram_fpwr(&master->dc_ref_sync_datagram,
+                     ref ? ref->station_address : 0xffff, ESCREG_OF(ESCREG->SYS_TIME), ref->base_dc_range == EC_DC_64 ? 8 : 4);
+    ec_datagram_frmw(&master->dc_all_sync_datagram,
+                     ref ? ref->station_address : 0xffff, ESCREG_OF(ESCREG->SYS_TIME), ref->base_dc_range == EC_DC_64 ? 8 : 4);
+}
+
+static void ec_master_calc_topology(ec_master_t *master)
+{
+    unsigned int slave_position = 0;
+
+    if (master->slave_count == 0)
+        return;
+
+    EC_ASSERT_MSG(ec_master_calc_topology_rec(master, NULL, &slave_position) == 0,
+                  "Failed to calculate bus topology\n");
+}
+
+static void ec_master_calc_transmission_delays(ec_master_t *master)
+{
+    ec_slave_t *slave;
+
+    for (slave = master->slaves;
+         slave < master->slaves + master->slave_count;
+         slave++) {
+        ec_slave_calc_port_delays(slave);
+    }
+
+    if (master->dc_ref_clock) {
+        uint32_t delay = 0;
+        ec_slave_calc_transmission_delays(master->dc_ref_clock, &delay);
+    }
+}
+
+static void ec_master_calc_dc(ec_master_t *master)
+{
+    // find DC reference clock
+    ec_master_find_dc_ref_clock(master);
+
+    // calculate bus topology
+    ec_master_calc_topology(master);
+
+    ec_master_calc_transmission_delays(master);
+}
+
+static void ec_master_scan_slaves_state(ec_master_t *master)
+{
+    ec_datagram_t *datagram;
+    ec_slave_t *slave;
+    uint8_t slave_state;
+    int ret;
+
+    datagram = &master->main_datagram;
+
+    for (uint32_t slave_index = 0; slave_index < master->slave_count; slave_index++) {
+        slave = master->slaves + slave_index;
+
+        ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->AL_STAT), 2);
+        ec_datagram_zero(datagram);
+        datagram->netdev_idx = slave->netdev_idx;
+        ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+        if (ret < 0) {
+            continue;
+        }
+
+        slave_state = EC_READ_U8(datagram->data);
+
+        if (slave->current_state != slave_state) {
+            EC_SLAVE_LOG_WRN("Slave %u state changed to %s\n", slave->index, ec_state_string(slave_state, 0));
+            slave->current_state = slave_state;
+        }
+
+        if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) {
+            ret = ec_slave_state_clear_ack_error(slave, slave->requested_state);
+            if (ret < 0) {
+                continue;
+            }
+        } else {
+            slave->alstatus_code = 0;
+        }
+
+        if (((slave->requested_state != slave->current_state) && (slave->alstatus_code == 0)) || slave->force_update) {
+            ret = ec_slave_config(slave);
+            if (ret < 0) {
+                EC_SLAVE_LOG_ERR("Failed to configure slave %u\n", slave->index);
+            }
+            slave->force_update = false;
+        }
+    }
+}
+
+void ec_slaves_scanning(ec_master_t *master)
+{
+    ec_datagram_t *datagram;
+    ec_slave_t *slave;
+    unsigned int netdev_idx;
+    bool rescan_required = false;
+    unsigned int scan_jiffies;
+    int ret;
+
+    datagram = &master->main_datagram;
+
+    for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+        if (!master->link_state[netdev_idx] && master->netdev[netdev_idx]->link_state) {
+            EC_LOG_INFO("Detect link up on %s\n",
+                        master->netdev[netdev_idx]->name);
+        }
+
+        if (master->link_state[netdev_idx] && !master->netdev[netdev_idx]->link_state) {
+            EC_LOG_INFO("Detect link down on %s\n",
+                        master->netdev[netdev_idx]->name);
+
+            ec_osal_mutex_take(master->scan_lock);
+            ec_master_clear_slaves(master);
+
+            for (uint8_t i = EC_NETDEV_MAIN; i < CONFIG_EC_MAX_NETDEVS; i++) {
+                master->slaves_state[i] = 0x00;
+                master->slaves_responding[i] = 0;
+            }
+            master->scan_done = false;
+            ec_osal_mutex_give(master->scan_lock);
+        }
+        master->link_state[netdev_idx] = master->netdev[netdev_idx]->link_state;
+    }
+
+    for (netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+        ec_datagram_brd(datagram, ESCREG_OF(ESCREG->AL_STAT), 2);
+        ec_datagram_zero(datagram);
+        datagram->netdev_idx = netdev_idx;
+        ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+        if (ret < 0) {
+            return;
+        }
+
+        if (datagram->working_counter != master->slaves_responding[netdev_idx]) {
+            rescan_required = 1;
+            master->slaves_responding[netdev_idx] = datagram->working_counter;
+            EC_LOG_INFO("%u slaves responding on %s device\n",
+                        master->slaves_responding[netdev_idx],
+                        master->netdev[netdev_idx]->name);
+        }
+
+        if (master->slaves_responding[netdev_idx] > 0) {
+            uint8_t states = EC_READ_U8(datagram->data);
+            if (states != master->slaves_state[netdev_idx]) {
+                // slave states changed
+                master->slaves_state[netdev_idx] = states;
+                EC_LOG_INFO("Slaves state on %s device: %s\n",
+                            master->netdev[netdev_idx]->name, ec_state_string(states, 1));
+            }
+        } else {
+            master->slaves_state[netdev_idx] = 0;
+        }
+    }
+
+    if (rescan_required) {
+        uint32_t count = 0, slave_index, autoinc_address;
+
+        rescan_required = 0;
+
+        ec_osal_mutex_take(master->scan_lock);
+
+        master->scan_done = false;
+        EC_LOG_INFO("Rescanning bus...\n");
+
+        ec_master_clear_slaves(master);
+
+        scan_jiffies = jiffies;
+
+        for (uint8_t i = EC_NETDEV_MAIN; i < CONFIG_EC_MAX_NETDEVS; i++) {
+            count += master->slaves_responding[i];
+        }
+
+        if (!count) {
+            goto mutex_unlock;
+        }
+
+        master->slaves = ec_osal_malloc(sizeof(ec_slave_t) * count);
+        if (!master->slaves) {
+            EC_LOG_ERR("Failed to allocate memory for slaves\n");
+            goto mutex_unlock;
+        }
+
+        master->slave_count = count;
+        memset(master->slaves, 0, sizeof(ec_slave_t) * count);
+
+        slave_index = 0;
+        for (uint8_t netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+            autoinc_address = 0;
+            for (uint32_t j = 0; j < master->slaves_responding[netdev_idx]; j++) {
+                slave = master->slaves + slave_index;
+
+                ec_slave_init(slave, slave_index, master, netdev_idx, (int16_t)autoinc_address * (-1), slave_index + 1001);
+
+                slave_index++;
+                autoinc_address++;
+            }
+        }
+        ec_osal_mutex_give(master->scan_lock);
+
+        for (uint8_t netdev_idx = EC_NETDEV_MAIN; netdev_idx < CONFIG_EC_MAX_NETDEVS; netdev_idx++) {
+            if (master->slaves_responding[netdev_idx] == 0) {
+                continue;
+            }
+            // Clear station address
+            ec_datagram_bwr(datagram, ESCREG_OF(ESCREG->STATION_ADDR), 2);
+            ec_datagram_zero(datagram);
+            datagram->netdev_idx = netdev_idx;
+            ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+            if (ret < 0) {
+                EC_LOG_ERR("Failed to clear station address on %s link\n", master->netdev[netdev_idx]->name);
+                goto mutex_unlock;
+            }
+
+            // Clear receive time for dc measure delays
+            ec_datagram_bwr(datagram, ESCREG_OF(ESCREG->RCV_TIME[0]), 4);
+            ec_datagram_zero(datagram);
+            datagram->netdev_idx = netdev_idx;
+            ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+            if (ret < 0) {
+                EC_LOG_ERR("Failed to clear receive time on %s link\n", master->netdev[netdev_idx]->name);
+                goto mutex_unlock;
+            }
+        }
+
+        for (uint32_t slave_index = 0; slave_index < master->slave_count; slave_index++) {
+            slave = master->slaves + slave_index;
+
+            EC_SLAVE_LOG_INFO("Scanning slave %u on %s\n", slave->index, master->netdev[slave->netdev_idx]->name);
+
+            // Set station address
+            ec_datagram_apwr(datagram, slave->autoinc_address, ESCREG_OF(ESCREG->STATION_ADDR), 2);
+            EC_WRITE_U16(datagram->data, slave->station_address);
+            datagram->netdev_idx = slave->netdev_idx;
+            ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+            if (ret < 0) {
+                EC_LOG_ERR("Failed to set station address on slave %u\n", slave->index);
+                goto mutex_unlock;
+            }
+
+            // Read AL state
+            ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->AL_STAT), 2);
+            ec_datagram_zero(datagram);
+            datagram->netdev_idx = slave->netdev_idx;
+            ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+            if (ret < 0) {
+                EC_LOG_ERR("Failed to read AL status on slave %u\n", slave->index);
+                goto mutex_unlock;
+            }
+
+            // Read base information
+            ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->TYPE), 12);
+            ec_datagram_zero(datagram);
+            datagram->netdev_idx = slave->netdev_idx;
+            ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+            if (ret < 0) {
+                EC_SLAVE_LOG_ERR("Failed to read base on slave %u\n", slave->index);
+                goto mutex_unlock;
+            }
+
+            slave->base_type = EC_READ_U8(datagram->data);
+            slave->base_revision = EC_READ_U8(datagram->data + 1);
+            slave->base_build = EC_READ_U16(datagram->data + 2);
+
+            slave->base_fmmu_count = EC_READ_U8(datagram->data + 4);
+            if (slave->base_fmmu_count > EC_MAX_FMMUS) {
+                EC_SLAVE_LOG_WRN("Slave has more FMMUs (%u) than the master can handle (%u)\n",
+                                 slave->base_fmmu_count, EC_MAX_FMMUS);
+                slave->base_fmmu_count = EC_MAX_FMMUS;
+            }
+
+            slave->base_sync_count = EC_READ_U8(datagram->data + 5);
+            if (slave->base_sync_count > EC_MAX_SYNC_MANAGERS) {
+                EC_SLAVE_LOG_WRN("Slave provides more sync managers (%u) than the master can handle (%u)\n",
+                                 slave->base_sync_count, EC_MAX_SYNC_MANAGERS);
+                slave->base_sync_count = EC_MAX_SYNC_MANAGERS;
+            }
+
+            uint8_t data = EC_READ_U8(datagram->data + 7);
+            for (uint8_t i = 0; i < EC_MAX_PORTS; i++) {
+                slave->ports[i].desc = (data >> (2 * i)) & 0x03;
+            }
+
+            data = EC_READ_U8(datagram->data + 8);
+            slave->base_fmmu_bit_operation = data & 0x01;
+            slave->base_dc_supported = (data >> 2) & 0x01;
+            slave->base_dc_range = ((data >> 3) & 0x01) ? EC_DC_64 : EC_DC_32;
+
+            if (slave->base_dc_supported) {
+                // Read DC capabilities
+                ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->SYS_TIME),
+                                 slave->base_dc_range == EC_DC_64 ? 8 : 4);
+                ec_datagram_zero(datagram);
+                datagram->netdev_idx = slave->netdev_idx;
+                ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+                if (ret < 0) {
+                    EC_SLAVE_LOG_ERR("Failed to read DC capabilities on slave %u\n", slave->index);
+                    goto mutex_unlock;
+                }
+
+                if (datagram->working_counter == 1) {
+                    slave->has_dc_system_time = 1;
+                    EC_SLAVE_LOG_DBG("Slave has the System Time register\n");
+                } else {
+                    slave->has_dc_system_time = 0;
+                    EC_SLAVE_LOG_DBG("Slave has no System Time register; delay measurement only\n");
+                }
+
+                // Read DC port receive times
+                ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->RCV_TIME[0]), 16);
+                ec_datagram_zero(datagram);
+                datagram->netdev_idx = slave->netdev_idx;
+                ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+                if (ret < 0) {
+                    EC_SLAVE_LOG_ERR("Failed to read DC receive times on slave %u\n", slave->index);
+                    goto mutex_unlock;
+                }
+
+                for (uint8_t i = 0; i < EC_MAX_PORTS; i++) {
+                    slave->ports[i].receive_time = EC_READ_U32(datagram->data + 4 * i);
+                }
+            } else {
+            }
+
+            // Read data link status
+            ec_datagram_fprd(datagram, slave->station_address, ESCREG_OF(ESCREG->ESC_DL_STAT), 2);
+            ec_datagram_zero(datagram);
+            datagram->netdev_idx = slave->netdev_idx;
+            ret = ec_master_queue_ext_datagram(master, datagram, true, true);
+            if (ret < 0) {
+                EC_SLAVE_LOG_ERR("Failed to read data link status on slave %u\n", slave->index);
+                goto mutex_unlock;
+            }
+
+            uint16_t dl_status = EC_READ_U16(datagram->data);
+            for (uint8_t i = 0; i < EC_MAX_PORTS; i++) {
+                slave->ports[i].link.link_up =
+                    dl_status & (1 << (4 + i)) ? 1 : 0;
+                slave->ports[i].link.loop_closed =
+                    dl_status & (1 << (8 + i * 2)) ? 1 : 0;
+                slave->ports[i].link.signal_detected =
+                    dl_status & (1 << (9 + i * 2)) ? 1 : 0;
+            }
+
+            uint16_t sii_offset = EC_FIRST_SII_CATEGORY_OFFSET;
+            uint16_t cat_type, cat_size;
+            uint32_t sii_data;
+            uint16_t *cat_data;
+
+            // Read SII category headers to determine full SII size
+            do {
+                ret = ec_sii_read(master, slave_index, datagram, sii_offset, &sii_data, 4);
+                if (ret < 0) {
+                    EC_SLAVE_LOG_ERR("Failed to read SII category header on slave %u\n", slave->index);
+                    goto mutex_unlock;
+                }
+
+                cat_type = sii_data & 0xFFFF;
+                cat_size = (sii_data >> 16) & 0xFFFF;
+
+                sii_offset += 2 + cat_size;
+                EC_SLAVE_LOG_DBG("Found category type 0x%04x with size 0x%04x, next offset 0x%04x\n",
+                                 cat_type, cat_size * 2, sii_offset);
+            } while (cat_type != 0xFFFF && (sii_offset < EC_MAX_SII_SIZE));
+
+            slave->sii_nwords = EC_ALIGN_UP(sii_offset + 1, 2);
+
+            slave->sii_image = ec_osal_malloc(slave->sii_nwords * 2);
+            if (!slave->sii_image) {
+                EC_LOG_ERR("Failed to allocate memory for SII on slave %u\n", slave->index);
+                goto mutex_unlock;
+            }
+            memset(slave->sii_image, 0, slave->sii_nwords * 2);
+
+            // Read full SII and parse it
+            ret = ec_sii_read(master, slave_index, datagram, 0x0000, (uint32_t *)slave->sii_image, slave->sii_nwords * 2);
+            if (ret < 0) {
+                EC_SLAVE_LOG_ERR("Failed to read SII category header on slave %u\n", slave->index);
+                goto mutex_unlock;
+            }
+
+            slave->sii.aliasaddr =
+                EC_READ_U16(slave->sii_image + 0x0004);
+            slave->effective_alias = slave->sii.aliasaddr;
+            slave->sii.vendor_id =
+                EC_READ_U32(slave->sii_image + 0x0008);
+            slave->sii.product_code =
+                EC_READ_U32(slave->sii_image + 0x000A);
+            slave->sii.revision_number =
+                EC_READ_U32(slave->sii_image + 0x000C);
+            slave->sii.serial_number =
+                EC_READ_U32(slave->sii_image + 0x000E);
+            slave->sii.boot_rx_mailbox_offset =
+                EC_READ_U16(slave->sii_image + 0x0014);
+            slave->sii.boot_rx_mailbox_size =
+                EC_READ_U16(slave->sii_image + 0x0015);
+            slave->sii.boot_tx_mailbox_offset =
+                EC_READ_U16(slave->sii_image + 0x0016);
+            slave->sii.boot_tx_mailbox_size =
+                EC_READ_U16(slave->sii_image + 0x0017);
+            slave->sii.std_rx_mailbox_offset =
+                EC_READ_U16(slave->sii_image + 0x0018);
+            slave->sii.std_rx_mailbox_size =
+                EC_READ_U16(slave->sii_image + 0x0019);
+            slave->sii.std_tx_mailbox_offset =
+                EC_READ_U16(slave->sii_image + 0x001A);
+            slave->sii.std_tx_mailbox_size =
+                EC_READ_U16(slave->sii_image + 0x001B);
+            slave->sii.mailbox_protocols =
+                EC_READ_U16(slave->sii_image + 0x001C);
+
+            EC_ASSERT_MSG(slave->sii.mailbox_protocols & EC_MBXPROT_COE, "Slave %u must support COE\n", slave->index);
+            EC_SLAVE_LOG_INFO("Slave %u mbxprot support: %s\n", slave->index, ec_mbox_protocol_string(slave->sii.mailbox_protocols));
+
+            cat_data = slave->sii_image + EC_FIRST_SII_CATEGORY_OFFSET;
+
+            while (EC_READ_U16(cat_data) != 0xFFFF) {
+                cat_type = EC_READ_U16(cat_data);     // category type
+                cat_size = EC_READ_U16(cat_data + 1); // category size
+                cat_data += 2;
+
+                EC_SLAVE_LOG_DBG("Parsing category type 0x%04x with size 0x%04x\n",
+                                 cat_type, cat_size * 2);
+
+                switch (cat_type) {
+                    case EC_SII_TYPE_STRINGS:
+                        ret = ec_slave_fetch_sii_strings(slave, (uint8_t *)cat_data, cat_size * 2);
+                        if (ret < 0) {
+                            EC_SLAVE_LOG_ERR("Failed to fetch SII strings on slave %u\n", slave->index);
+                            goto mutex_unlock;
+                        }
+                        break;
+                    case EC_SII_TYPE_GENERAL:
+                        slave->sii.has_general = true;
+                        ec_memcpy(&slave->sii.general, cat_data, sizeof(ec_sii_general_t));
+                        break;
+                    case EC_SII_TYPE_FMMU:
+                        break;
+                    case EC_SII_TYPE_SM:
+                        slave->sm_count = (cat_size * 2) / sizeof(ec_sii_sm_t);
+
+                        EC_ASSERT_MSG(slave->sm_count >= 4, "Slave %u has less than 4 sync managers\n", slave->index);
+
+                        for (uint8_t i = 0; i < slave->sm_count; i++) {
+                            ec_sii_sm_t *sm = (ec_sii_sm_t *)((uint8_t *)cat_data + i * sizeof(ec_sii_sm_t));
+
+                            slave->sm_info[i].physical_start_address = sm->physical_start_address;
+                            slave->sm_info[i].length = sm->length;
+                            slave->sm_info[i].control = sm->control;
+                            slave->sm_info[i].enable = sm->active;
+                        }
+                        break;
+                    case EC_SII_TYPE_TXPDO:
+                        break;
+                    case EC_SII_TYPE_RXPDO:
+                        break;
+                    case EC_SII_TYPE_DC:
+                        break;
+                    default:
+                        EC_SLAVE_LOG_WRN("Unknown SII category type 0x%04x\n", cat_type);
+                        break;
+                }
+
+                cat_data += cat_size;
+            }
+
+            EC_SLAVE_LOG_INFO("Slave %u parse eeprom success\n", slave->index);
+
+            ret = ec_slave_config(slave);
+            if (ret < 0) {
+                EC_SLAVE_LOG_ERR("Failed to configure slave %u\n", slave->index);
+                goto mutex_unlock;
+            }
+        }
+
+        EC_LOG_INFO("Bus scanning completed in %u ms\n", (unsigned int)((jiffies - scan_jiffies) / 1000));
+        master->scan_done = true;
+
+        ec_master_calc_dc(master);
+
+    mutex_unlock:
+        ec_osal_mutex_give(master->scan_lock);
+    }
+
+    if (master->slave_count && master->scan_done) {
+        ec_master_scan_slaves_state(master);
+    }
+}
+
+char *ec_slave_get_sii_string(const ec_slave_t *slave, uint32_t index)
+{
+    if (!index--)
+        return NULL;
+
+    if (index >= slave->sii.string_count) {
+        EC_LOG_ERR("String %u not found\n", index);
+        return NULL;
+    }
+
+    return slave->sii.strings[index];
+}
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_timestamp.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_timestamp.c
new file mode 100644
index 00000000..fba2473f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_timestamp.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_master.h"
+
+#ifndef CONFIG_EC_TIMESTAMP_CUSTOM
+#if defined(__riscv) || defined(__ICCRISCV__)
+
+#define READ_CSR(csr_num) ({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v; })
+
+#define CSR_MCYCLE  (0xB00)
+#define CSR_MCYCLEH (0xB80)
+
+static inline uint64_t riscv_csr_get_core_mcycle(void)
+{
+    uint64_t result;
+    uint32_t resultl_first = READ_CSR(CSR_MCYCLE);
+    uint32_t resulth = READ_CSR(CSR_MCYCLEH);
+    uint32_t resultl_second = READ_CSR(CSR_MCYCLE);
+    if (resultl_first < resultl_second) {
+        result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */
+    } else {
+        resulth = READ_CSR(CSR_MCYCLEH);
+        result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */
+    }
+    return result;
+}
+
+static uint32_t g_clock_time_div;
+
+void ec_timestamp_init(void)
+{
+    g_clock_time_div = ec_get_cpu_frequency() / 1000000;
+
+    uint64_t start_cycle = ec_timestamp_get_time_us();
+    ec_osal_msleep(10);
+
+    EC_ASSERT_MSG((ec_timestamp_get_time_us() - start_cycle) >= 9000, "Timestamp timer not running\n");
+}
+
+EC_FAST_CODE_SECTION uint64_t ec_timestamp_get_time_ns(void)
+{
+    return (riscv_csr_get_core_mcycle() * 1000) / g_clock_time_div;
+}
+
+EC_FAST_CODE_SECTION uint64_t ec_timestamp_get_time_us(void)
+{
+    return riscv_csr_get_core_mcycle() / g_clock_time_div;
+}
+#elif defined(__arm__) || defined(__ICCARM__) || defined(__ARMCC_VERSION)
+
+#define DWT_CR     (*(volatile uint32_t *)0xE0001000)
+#define DWT_CYCCNT (*(volatile uint32_t *)0xE0001004)
+#define DEM_CR     (*(volatile uint32_t *)0xE000EDFC)
+#define ITM_LAR    (*((volatile unsigned int *)0xE0001FB0))
+
+#define DEM_CR_TRCENA    (1 << 24)
+#define DWT_CR_CYCCNTENA (1 << 0)
+
+static volatile uint32_t g_dwt_high = 0;
+static volatile uint32_t g_dwt_last_low = 0;
+static uint32_t g_clock_time_div;
+
+static inline uint64_t arm_dwt_get_cycle_count(void)
+{
+    uint32_t current_low = DWT_CYCCNT;
+
+    if (current_low < g_dwt_last_low) {
+        g_dwt_high++;
+    }
+    g_dwt_last_low = current_low;
+
+    return ((uint64_t)g_dwt_high << 32) | current_low;
+}
+
+void ec_timestamp_init(void)
+{
+    g_clock_time_div = ec_get_cpu_frequency() / 1000000;
+
+    g_dwt_high = 0;
+    g_dwt_last_low = 0;
+
+    DEM_CR |= (uint32_t)DEM_CR_TRCENA;
+    DWT_CYCCNT = (uint32_t)0u;
+    g_dwt_last_low = 0;
+
+    DWT_CR |= (uint32_t)DWT_CR_CYCCNTENA;
+
+    uint64_t start_cycle = ec_timestamp_get_time_us();
+    ec_osal_msleep(10);
+
+    EC_ASSERT_MSG((ec_timestamp_get_time_us() - start_cycle) >= 9000, "Timestamp timer not running\n");
+}
+
+EC_FAST_CODE_SECTION uint64_t ec_timestamp_get_time_ns(void)
+{
+    return (arm_dwt_get_cycle_count() * 1000) / g_clock_time_div;
+}
+
+EC_FAST_CODE_SECTION uint64_t ec_timestamp_get_time_us(void)
+{
+    return arm_dwt_get_cycle_count() / g_clock_time_div;
+}
+
+#else
+#error "Unsupported architecture"
+#endif
+
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/phy/chry_phy.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/phy/chry_phy.c
new file mode 100644
index 00000000..0df4161a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/phy/chry_phy.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "ec_config.h"
+
+#ifndef CONFIG_EC_PHY_CUSTOM
+#include "phy/chry_phy.h"
+
+#include "phy/chry_phy_dp83848.h"
+#include "phy/chry_phy_dp83847.h"
+#include "phy/chry_phy_jl1111.h"
+#include "phy/chry_phy_ksz8081.h"
+#include "phy/chry_phy_lan8720.h"
+#include "phy/chry_phy_rtl8201.h"
+#include "phy/chry_phy_rtl8211.h"
+#include "phy/chry_phy_yt8522.h"
+
+const struct chry_phy_driver *g_phy_driver_table[] = {
+    &dp83848_driver,
+    &dp83847_driver,
+    &jl1111_driver,
+    &ksz8081_driver,
+    &lan8720_driver,
+    &rtl8201_driver,
+    &rtl8211_driver,
+    &yt8522_driver,
+
+};
+
+int chry_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config)
+{
+    const struct chry_phy_driver *phydrv = NULL;
+    uint16_t phy_id1;
+    uint16_t phy_id2;
+    uint16_t regval = 0;
+    uint32_t phy_id;
+    bool extended_status = false;
+    uint16_t phy_addr;
+
+    for (uint16_t i = 0; i < 32; i++) {
+        phy_addr = i;
+        phy_id1 = phydev->mdio_read(phydev, phy_addr, MII_PHYSID1);
+        phy_id2 = phydev->mdio_read(phydev, phy_addr, MII_PHYSID2);
+
+        phy_id = (phy_id1 << 16) | phy_id2;
+        for (uint32_t i = 0; i < sizeof(g_phy_driver_table) / sizeof(g_phy_driver_table[0]); i++) {
+            if (g_phy_driver_table[i]->phy_id == (phy_id & g_phy_driver_table[i]->phy_id_mask)) {
+                phydrv = g_phy_driver_table[i];
+                goto phydrv_found;
+            }
+        }
+    }
+
+    if (phydrv == NULL) {
+        return -1;
+    }
+
+    /* PHY reset */
+    phydev->mdio_write(phydev, phy_addr, MII_BMCR, BMCR_RESET);
+    while (phydev->mdio_read(phydev, phy_addr, MII_BMCR) & BMCR_RESET) {
+    }
+
+phydrv_found:
+    phydev->phy_id = phy_id;
+    phydev->phy_addr = phy_addr;
+    phydev->driver = phydrv;
+
+    regval = phydev->mdio_read(phydev, phy_addr, MII_BMSR);
+
+    phydev->support.support_pause = 1;
+
+    if (regval & BMSR_100T4) {
+        phydev->support.support_100base_t4 = 1;
+    }
+    if (regval & BMSR_100FULL) {
+        phydev->support.support_100base_tx_full = 1;
+    }
+    if (regval & BMSR_100HALF) {
+        phydev->support.support_1000base_tx_half = 1;
+    }
+    if (regval & BMSR_10FULL) {
+        phydev->support.support_10base_tx_full = 1;
+    }
+    if (regval & BMSR_10HALF) {
+        phydev->support.support_10base_tx_half = 1;
+    }
+    if (regval & BMSR_ANEGCAPABLE) {
+        phydev->support.support_autoeng = 1;
+    }
+
+    if (regval & BMSR_ESTATEN) {
+        regval = phydev->mdio_read(phydev, phy_addr, MII_GBESR);
+        if (regval & GBESR_1000_TFULL) {
+            phydev->support.support_1000base_tx_full = 1;
+        }
+        if (regval & GBESR_1000_THALF) {
+            phydev->support.support_1000base_tx_half = 1;
+        }
+        extended_status = true;
+    }
+
+    regval = 0;
+    if (config->loopback) {
+        regval |= BMCR_LOOPBACK;
+    }
+
+    if (config->auto_negotiation) {
+        regval |= BMCR_ANENABLE;
+        regval |= BMCR_ANRESTART;
+    } else {
+        if (config->speed == 100) {
+            regval |= BMCR_SPEED100;
+        } else if (config->speed == 1000) {
+            regval |= BMCR_SPEED100;
+            regval |= BMCR_SPEED1000;
+        } else {
+            regval &= ~BMCR_SPEED100;
+        }
+    }
+    phydev->mdio_write(phydev, phy_addr, MII_BMCR, regval);
+
+    regval = phydev->mdio_read(phydev, phy_addr, MII_ANAR);
+    regval &= ~(ANAR_SPEED_ALL | ANAR_SLCT | ANAR_PAUSE | ANAR_ASYM_PAUSE);
+    regval |= phydev->support.support_100base_t4 ? ANAR_100T4 : 0;
+    regval |= phydev->support.support_100base_tx_full ? ANAR_100FULL : 0;
+    regval |= phydev->support.support_100base_tx_half ? ANAR_100HALF : 0;
+    regval |= phydev->support.support_10base_tx_full ? ANAR_10FULL : 0;
+    regval |= phydev->support.support_10base_tx_half ? ANAR_10HALF : 0;
+    regval |= phydev->support.support_pause ? ANAR_PAUSE : 0;
+    regval |= phydev->support.support_asym_pause ? ANAR_ASYM_PAUSE : 0;
+    regval |= ANAR_CSMA;
+    phydev->mdio_write(phydev, phy_addr, MII_ANAR, regval);
+
+    if (extended_status) {
+        regval = phydev->mdio_read(phydev, phy_addr, MII_GBCR);
+        regval &= ~(GBCR_1000FULL | GBCR_1000HALF);
+        regval |= phydev->support.support_1000base_tx_full ? GBCR_1000FULL : 0;
+        regval |= phydev->support.support_1000base_tx_half ? GBCR_1000HALF : 0;
+        phydev->mdio_write(phydev, phy_addr, MII_GBCR, regval);
+    }
+
+    if (phydev->driver && phydev->driver->phy_init) {
+        phydev->driver->phy_init(phydev, config);
+    }
+    return 0;
+}
+
+void chry_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status)
+{
+    if (phydev->driver && phydev->driver->phy_get_status) {
+        phydev->driver->phy_get_status(phydev, status);
+    }
+}
+#endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/SConscript b/projects/etherkit_ethercat_cherryecat/packages/SConscript
new file mode 100644
index 00000000..ca95be14
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/SConscript
@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
diff --git a/projects/etherkit_ethercat_cherryecat/packages/pkgs.json b/projects/etherkit_ethercat_cherryecat/packages/pkgs.json
new file mode 100644
index 00000000..0637a088
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/pkgs.json
@@ -0,0 +1 @@
+[]
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/packages/pkgs_error.json b/projects/etherkit_ethercat_cherryecat/packages/pkgs_error.json
new file mode 100644
index 00000000..0637a088
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/packages/pkgs_error.json
@@ -0,0 +1 @@
+[]
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/project.ewd b/projects/etherkit_ethercat_cherryecat/project.ewd
new file mode 100644
index 00000000..e970683a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/project.ewd
@@ -0,0 +1,3276 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>4</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>33</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state>$TOOLKIT_DIR$\config\debugger\Renesas\R9A07G084M04.ddf</state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>9.50.2.71646</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>JLINK_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state>9.50.2.71646</state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state>$TOOLKIT_DIR$/config/flashloader/Renesas/FlashRSK_RZN2L.board</state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlavePath</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>C_32_64Device</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AuthSdmSelection</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthSdmManifest</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthSdmExplicitLib</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthEnforce</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>E2_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>E2PowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CE2UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CE2IdCodeEditB</name>
+                    <state>0xFFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF</state>
+                </option>
+                <option>
+                    <name>CE2LogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CE2LogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GPLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVccEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSelectedCoreName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>33</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>9.50.2.71646</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>ARMSIM_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlavePath</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>C_32_64Device</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AuthSdmSelection</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthSdmManifest</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthSdmExplicitLib</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthEnforce</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>E2_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>E2PowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CE2UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CE2IdCodeEditB</name>
+                    <state>0xFFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF</state>
+                </option>
+                <option>
+                    <name>CE2LogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CE2LogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GPLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVccEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSelectedCoreName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>
diff --git a/projects/etherkit_ethercat_cherryecat/project.ewp b/projects/etherkit_ethercat_cherryecat/project.ewp
new file mode 100644
index 00000000..fe882226
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/project.ewp
@@ -0,0 +1,2728 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>4</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>36</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>BrowseInfoPath</name>
+                    <state>Debug\BrowseInfo</state>
+                </option>
+                <option>
+                    <name>OGAarch64Abi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OG_32_64Device</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>BuildFilesPath</name>
+                    <state>Debug\</state>
+                </option>
+                <option>
+                    <name>ExePath</name>
+                    <state>Debug\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>Debug\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>Debug\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state>A complete configuration of the C/C++14 runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>9.20.4.47112</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>9.50.2.71646</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>R9A07G084M04	Renesas R9A07G084M04</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>33</version>
+                    <state>49</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>33</version>
+                    <state>49</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>R9A07G084M04	Renesas R9A07G084M04</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>33</version>
+                    <state>49</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PointerAuthentication</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FPU64</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OG_32_64DeviceCoreSlave</name>
+                    <version>33</version>
+                    <state>49</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>38</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCDefines</name>
+                    <state>_LWIP_ADD_ON_APP=0</state>
+                    <state>ETHERCAT_SSC_PORT_GMAC_MDIO_SUPPORT=1</state>
+                    <state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state>
+                    <state>RT_USING_DLIBC</state>
+                    <state>RT_USING_LIBC</state>
+                    <state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
+                    <state>__RTTHREAD__</state>
+                    <state>__RT_IPC_SOURCE__</state>
+                    <state>__RT_KERNEL_SOURCE__</state>
+                    <state>_RZN_ORDINAL=1</state>
+                    <state>_RZN_CORE=CR52_0</state>
+                    <state>_RENESAS_RZN_</state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>10010100</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</state>
+                    <state>$PROJ_DIR$/rzn/aws/amazon-freertos/freertos_kernel/include</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/api</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/instances</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_ethercat_ssc_port</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_freertos_port/cr</state>
+                    <state>$PROJ_DIR$/rzn_cfg/aws</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</state>
+                    <state>$PROJ_DIR$/rzn_gen</state>
+                    <state>$PROJ_DIR$/src</state>
+                    <state>$PROJ_DIR$</state>
+                    <state>$PROJ_DIR$\src\ethercat\beckhoff\Src</state>
+                    <state>$PROJ_DIR$\src\ethercat\renesas</state>
+                    <state>$PROJ_DIR$\src\tcpip\renesas\module</state>
+                    <state>$PROJ_DIR$\src\tcpip\renesas\module\ether_netif</state>
+                    <state>$PROJ_DIR$\src\tcpip\renesas\module\lwip_port</state>
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+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+                <buildSequence>inputOutputBased</buildSequence>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>27</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IlinkLogCrtRoutineSelection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFragmentInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInlining</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogMerging</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDemangle</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFileEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$/script/fsp_xspi0_boot.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state>--config_search "$PROJ_DIR$"</state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>system_init</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkFpuProcessor</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <buildActions>
+                    <buildAction>
+                        <cmdline>cmd /c ""$PROJ_DIR$\rasc_launcher.bat" "$PROJ_DIR$\rasc_version.txt" -nosplash --launcher.suppressErrors --generate --compiler IAR --devicefamily $RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" 2&gt; "$BUILD_FILES_DIR$\.rasc_stderr.txt" &amp;&amp; echo. &gt; "$BUILD_FILES_DIR$\$TARGET_BNAME$.rasc""</cmdline>
+                        <workingDirectory>$PROJ_DIR$</workingDirectory>
+                        <buildSequence>preCompile</buildSequence>
+                        <outputs>
+                            <file>
+                                <name>$BUILD_FILES_DIR$/$TARGET_BNAME$.rasc</name>
+                            </file>
+                        </outputs>
+                        <dependencies>
+                            <file>
+                                <name>configuration.xml</name>
+                            </file>
+                        </dependencies>
+                    </buildAction>
+                    <buildAction>
+                        <cmdline>cmd /c ""$PROJ_DIR$\rasc_launcher.bat" "$PROJ_DIR$\rasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily $RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2&gt; "$BUILD_FILES_DIR$\.rasc_stderr.txt""</cmdline>
+                        <workingDirectory>$PROJ_DIR$</workingDirectory>
+                        <buildSequence>postLink</buildSequence>
+                        <outputs>
+                            <file>
+                                <name>$TARGET_BPATH$.sbd</name>
+                            </file>
+                        </outputs>
+                        <dependencies>
+                            <file>
+                                <name>$TARGET_PATH$</name>
+                            </file>
+                        </dependencies>
+                    </buildAction>
+                </buildActions>
+            </data>
+        </settings>
+    </configuration>
+    <group>
+        <name>Applications</name>
+        <file>
+            <name>$PROJ_DIR$\src\hal_entry.c</name>
+        </file>
+    </group>
+    <group>
+        <name>CherryECAT</name>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\phy\chry_phy.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_cmd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_coe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_common.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_datagram.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_foe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_mailbox.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_master.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_netdev.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\osal\ec_osal_rtthread.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_perf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_sii.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_slave.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_timestamp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\port\netdev_renesas.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Compiler</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cctype.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cstdlib.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cstring.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\ctime.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cunistd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cwchar.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\environ.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_close.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_lseek.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_mem.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_open.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_read.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_remove.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_write.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscalls.c</name>
+        </file>
+    </group>
+    <group>
+        <name>CPU</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\backtrace.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\context_iar.S</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\cpuport.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\gicv3.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\interrupt.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\stack.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\start_iar.S</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\trap.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\vector_iar.S</name>
+        </file>
+    </group>
+    <group>
+        <name>DeviceDrivers</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\completion.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\condvar.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\dataqueue.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\core\device.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\hwtimer\hwtimer.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\pin\pin.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\pipe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\ringblk_buf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\ringbuffer.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\serial\serial_v2.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\waitqueue.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\workqueue.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Drivers</name>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_common.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_gpio.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_usart_v2.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Finsh</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\cmd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\msh.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\msh_parse.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\shell.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Kernel</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\clock.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\components.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\idle.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\ipc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\irq.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\kservice.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\klibc\kstdio.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\klibc\kstring.c</name>
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diff --git a/projects/etherkit_ethercat_cherryecat/project.ewt b/projects/etherkit_ethercat_cherryecat/project.ewt
new file mode 100644
index 00000000..86115d86
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/project.ewt
@@ -0,0 +1,3304 @@
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+                                <check name="THROW-main" enabled="false" />
+                                <check name="THROW-null" enabled="true" />
+                                <check name="THROW-ptr" enabled="true" />
+                                <check name="THROW-static" enabled="true" />
+                                <check name="THROW-unhandled" enabled="true" />
+                            </group>
+                            <group enabled="true" name="UNION">
+                                <check name="UNION-overlap-assign" enabled="true" />
+                                <check name="UNION-type-punning" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="CERT" enabled="false">
+                            <group enabled="true" name="CERT-ARR">
+                                <check name="CERT-ARR30-C_a" enabled="true" />
+                                <check name="CERT-ARR30-C_b" enabled="true" />
+                                <check name="CERT-ARR30-C_c" enabled="true" />
+                                <check name="CERT-ARR30-C_d" enabled="true" />
+                                <check name="CERT-ARR30-C_e" enabled="true" />
+                                <check name="CERT-ARR30-C_f" enabled="true" />
+                                <check name="CERT-ARR30-C_g" enabled="true" />
+                                <check name="CERT-ARR30-C_h" enabled="true" />
+                                <check name="CERT-ARR30-C_i" enabled="true" />
+                                <check name="CERT-ARR30-C_j" enabled="true" />
+                                <check name="CERT-ARR32-C" enabled="true" />
+                                <check name="CERT-ARR36-C_a" enabled="true" />
+                                <check name="CERT-ARR36-C_b" enabled="true" />
+                                <check name="CERT-ARR37-C" enabled="true" />
+                                <check name="CERT-ARR38-C_a" enabled="true" />
+                                <check name="CERT-ARR38-C_b" enabled="true" />
+                                <check name="CERT-ARR38-C_c" enabled="true" />
+                                <check name="CERT-ARR38-C_d" enabled="true" />
+                                <check name="CERT-ARR38-C_e" enabled="true" />
+                                <check name="CERT-ARR38-C_f" enabled="true" />
+                                <check name="CERT-ARR39-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-DCL">
+                                <check name="CERT-DCL30-C_a" enabled="true" />
+                                <check name="CERT-DCL30-C_b" enabled="true" />
+                                <check name="CERT-DCL30-C_c" enabled="true" />
+                                <check name="CERT-DCL30-C_d" enabled="true" />
+                                <check name="CERT-DCL30-C_e" enabled="true" />
+                                <check name="CERT-DCL31-C" enabled="true" />
+                                <check name="CERT-DCL36-C" enabled="true" />
+                                <check name="CERT-DCL37-C_a" enabled="true" />
+                                <check name="CERT-DCL37-C_b" enabled="true" />
+                                <check name="CERT-DCL37-C_c" enabled="false" />
+                                <check name="CERT-DCL38-C" enabled="true" />
+                                <check name="CERT-DCL39-C" enabled="true" />
+                                <check name="CERT-DCL40-C" enabled="true" />
+                                <check name="CERT-DCL41-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check name="CERT-ENV30-C" enabled="true" />
+                                <check name="CERT-ENV31-C" enabled="true" />
+                                <check name="CERT-ENV32-C" enabled="true" />
+                                <check name="CERT-ENV33-C" enabled="true" />
+                                <check name="CERT-ENV34-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check name="CERT-ERR30-C_a" enabled="true" />
+                                <check name="CERT-ERR30-C_b" enabled="true" />
+                                <check name="CERT-ERR30-C_c" enabled="true" />
+                                <check name="CERT-ERR30-C_d" enabled="true" />
+                                <check name="CERT-ERR30-C_e" enabled="true" />
+                                <check name="CERT-ERR32-C" enabled="true" />
+                                <check name="CERT-ERR33-C_a" enabled="true" />
+                                <check name="CERT-ERR33-C_b" enabled="true" />
+                                <check name="CERT-ERR33-C_c" enabled="true" />
+                                <check name="CERT-ERR33-C_d" enabled="true" />
+                                <check name="CERT-ERR34-C_a" enabled="true" />
+                                <check name="CERT-ERR34-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-EXP">
+                                <check name="CERT-EXP19-C" enabled="true" />
+                                <check name="CERT-EXP30-C_a" enabled="true" />
+                                <check name="CERT-EXP30-C_b" enabled="true" />
+                                <check name="CERT-EXP32-C" enabled="true" />
+                                <check name="CERT-EXP33-C_a" enabled="true" />
+                                <check name="CERT-EXP33-C_b" enabled="true" />
+                                <check name="CERT-EXP33-C_c" enabled="true" />
+                                <check name="CERT-EXP33-C_d" enabled="true" />
+                                <check name="CERT-EXP33-C_e" enabled="true" />
+                                <check name="CERT-EXP33-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_a" enabled="true" />
+                                <check name="CERT-EXP34-C_b" enabled="true" />
+                                <check name="CERT-EXP34-C_c" enabled="true" />
+                                <check name="CERT-EXP34-C_d" enabled="true" />
+                                <check name="CERT-EXP34-C_e" enabled="true" />
+                                <check name="CERT-EXP34-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_g" enabled="true" />
+                                <check name="CERT-EXP35-C" enabled="true" />
+                                <check name="CERT-EXP36-C_a" enabled="true" />
+                                <check name="CERT-EXP36-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_a" enabled="true" />
+                                <check name="CERT-EXP37-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_a" enabled="true" />
+                                <check name="CERT-EXP39-C_b" enabled="true" />
+                                <check name="CERT-EXP39-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_d" enabled="true" />
+                                <check name="CERT-EXP39-C_e" enabled="true" />
+                                <check name="CERT-EXP40-C_a" enabled="true" />
+                                <check name="CERT-EXP40-C_b" enabled="true" />
+                                <check name="CERT-EXP42-C" enabled="true" />
+                                <check name="CERT-EXP43-C_a" enabled="true" />
+                                <check name="CERT-EXP43-C_b" enabled="true" />
+                                <check name="CERT-EXP43-C_c" enabled="true" />
+                                <check name="CERT-EXP43-C_d" enabled="true" />
+                                <check name="CERT-EXP44-C" enabled="true" />
+                                <check name="CERT-EXP45-C" enabled="true" />
+                                <check name="CERT-EXP46-C" enabled="true" />
+                                <check name="CERT-EXP47-C_a" enabled="true" />
+                                <check name="CERT-EXP47-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check name="CERT-FIO30-C" enabled="true" />
+                                <check name="CERT-FIO32-C" enabled="true" />
+                                <check name="CERT-FIO34-C" enabled="true" />
+                                <check name="CERT-FIO37-C" enabled="true" />
+                                <check name="CERT-FIO38-C" enabled="true" />
+                                <check name="CERT-FIO39-C" enabled="true" />
+                                <check name="CERT-FIO40-C" enabled="true" />
+                                <check name="CERT-FIO41-C" enabled="true" />
+                                <check name="CERT-FIO42-C_a" enabled="true" />
+                                <check name="CERT-FIO42-C_b" enabled="false" />
+                                <check name="CERT-FIO44-C" enabled="true" />
+                                <check name="CERT-FIO45-C" enabled="true" />
+                                <check name="CERT-FIO46-C_a" enabled="true" />
+                                <check name="CERT-FIO46-C_b" enabled="true" />
+                                <check name="CERT-FIO46-C_c" enabled="true" />
+                                <check name="CERT-FIO47-C_a" enabled="true" />
+                                <check name="CERT-FIO47-C_b" enabled="true" />
+                                <check name="CERT-FIO47-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check name="CERT-FLP30-C_a" enabled="true" />
+                                <check name="CERT-FLP30-C_b" enabled="true" />
+                                <check name="CERT-FLP32-C_a" enabled="true" />
+                                <check name="CERT-FLP32-C_b" enabled="true" />
+                                <check name="CERT-FLP34-C" enabled="true" />
+                                <check name="CERT-FLP36-C" enabled="true" />
+                                <check name="CERT-FLP37-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check name="CERT-INT30-C_a" enabled="true" />
+                                <check name="CERT-INT30-C_b" enabled="false" />
+                                <check name="CERT-INT31-C_a" enabled="true" />
+                                <check name="CERT-INT31-C_b" enabled="true" />
+                                <check name="CERT-INT31-C_c" enabled="true" />
+                                <check name="CERT-INT32-C_a" enabled="true" />
+                                <check name="CERT-INT32-C_b" enabled="false" />
+                                <check name="CERT-INT33-C_a" enabled="true" />
+                                <check name="CERT-INT33-C_b" enabled="true" />
+                                <check name="CERT-INT33-C_c" enabled="true" />
+                                <check name="CERT-INT33-C_d" enabled="true" />
+                                <check name="CERT-INT33-C_e" enabled="true" />
+                                <check name="CERT-INT33-C_f" enabled="true" />
+                                <check name="CERT-INT33-C_g" enabled="true" />
+                                <check name="CERT-INT33-C_h" enabled="true" />
+                                <check name="CERT-INT33-C_i" enabled="true" />
+                                <check name="CERT-INT34-C_a" enabled="true" />
+                                <check name="CERT-INT34-C_b" enabled="true" />
+                                <check name="CERT-INT34-C_c" enabled="true" />
+                                <check name="CERT-INT35-C" enabled="true" />
+                                <check name="CERT-INT36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check name="CERT-MEM30-C_a" enabled="true" />
+                                <check name="CERT-MEM30-C_b" enabled="true" />
+                                <check name="CERT-MEM30-C_c" enabled="true" />
+                                <check name="CERT-MEM31-C" enabled="true" />
+                                <check name="CERT-MEM33-C_a" enabled="true" />
+                                <check name="CERT-MEM33-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_a" enabled="true" />
+                                <check name="CERT-MEM34-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_c" enabled="true" />
+                                <check name="CERT-MEM35-C_a" enabled="true" />
+                                <check name="CERT-MEM35-C_b" enabled="true" />
+                                <check name="CERT-MEM35-C_c" enabled="true" />
+                                <check name="CERT-MEM36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check name="CERT-MSC30-C" enabled="true" />
+                                <check name="CERT-MSC32-C" enabled="true" />
+                                <check name="CERT-MSC33-C" enabled="false" />
+                                <check name="CERT-MSC37-C" enabled="true" />
+                                <check name="CERT-MSC38-C" enabled="true" />
+                                <check name="CERT-MSC39-C" enabled="true" />
+                                <check name="CERT-MSC40-C_a" enabled="true" />
+                                <check name="CERT-MSC40-C_b" enabled="true" />
+                                <check name="CERT-MSC40-C_c" enabled="true" />
+                                <check name="CERT-MSC40-C_d" enabled="true" />
+                                <check name="CERT-MSC40-C_e" enabled="false" />
+                                <check name="CERT-MSC41-C_a" enabled="true" />
+                                <check name="CERT-MSC41-C_b" enabled="true" />
+                                <check name="CERT-MSC41-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check name="CERT-PRE31-C" enabled="true" />
+                                <check name="CERT-PRE32-C_a" enabled="true" />
+                                <check name="CERT-PRE32-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-SIG">
+                                <check name="CERT-SIG30-C" enabled="true" />
+                                <check name="CERT-SIG31-C" enabled="true" />
+                                <check name="CERT-SIG34-C" enabled="true" />
+                                <check name="CERT-SIG35-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check name="CERT-STR30-C" enabled="true" />
+                                <check name="CERT-STR31-C_a" enabled="true" />
+                                <check name="CERT-STR31-C_b" enabled="true" />
+                                <check name="CERT-STR31-C_c" enabled="true" />
+                                <check name="CERT-STR31-C_d" enabled="true" />
+                                <check name="CERT-STR31-C_e" enabled="true" />
+                                <check name="CERT-STR31-C_f" enabled="true" />
+                                <check name="CERT-STR31-C_g" enabled="true" />
+                                <check name="CERT-STR31-C_h" enabled="true" />
+                                <check name="CERT-STR32-C" enabled="true" />
+                                <check name="CERT-STR34-C" enabled="true" />
+                                <check name="CERT-STR37-C" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="SECURITY" enabled="false">
+                            <group enabled="true" name="SEC-BUFFER">
+                                <check name="SEC-BUFFER-memory-leak-alias" enabled="true" />
+                                <check name="SEC-BUFFER-memory-leak" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-qsort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-qsort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-sprintf-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-std-sort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-std-sort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncmp-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncmp-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-alloc-size" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy-length" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-index" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-offset" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-all" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-DIV-0">
+                                <check name="SEC-DIV-0-compare-after" enabled="true" />
+                                <check name="SEC-DIV-0-compare-before" enabled="true" />
+                                <check name="SEC-DIV-0-tainted" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check name="SEC-FILEOP-open-no-close" enabled="true" />
+                                <check name="SEC-FILEOP-path-traversal" enabled="false" />
+                                <check name="SEC-FILEOP-use-after-close" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check name="SEC-INJECTION-sql" enabled="false" />
+                                <check name="SEC-INJECTION-xpath" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check name="SEC-LOOP-tainted-bound" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check name="SEC-NULL-assignment-fun-pos" enabled="false" />
+                                <check name="SEC-NULL-assignment" enabled="true" />
+                                <check name="SEC-NULL-cmp-aft" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef-fun" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef" enabled="true" />
+                                <check name="SEC-NULL-literal-pos" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check name="SEC-STRING-format-string" enabled="true" />
+                                <check name="SEC-STRING-hard-coded-credentials" enabled="false" />
+                            </group>
+                        </package>
+                        <package name="MISRAC2004" enabled="false">
+                            <group enabled="true" name="MISRAC2004-1">
+                                <check name="MISRAC2004-1.1" enabled="true" />
+                                <check name="MISRAC2004-1.2_a" enabled="true" />
+                                <check name="MISRAC2004-1.2_b" enabled="true" />
+                                <check name="MISRAC2004-1.2_c" enabled="true" />
+                                <check name="MISRAC2004-1.2_d" enabled="true" />
+                                <check name="MISRAC2004-1.2_e" enabled="true" />
+                                <check name="MISRAC2004-1.2_f" enabled="true" />
+                                <check name="MISRAC2004-1.2_g" enabled="true" />
+                                <check name="MISRAC2004-1.2_h" enabled="true" />
+                                <check name="MISRAC2004-1.2_i" enabled="true" />
+                                <check name="MISRAC2004-1.2_j" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-2">
+                                <check name="MISRAC2004-2.1" enabled="true" />
+                                <check name="MISRAC2004-2.2" enabled="true" />
+                                <check name="MISRAC2004-2.3" enabled="true" />
+                                <check name="MISRAC2004-2.4" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-5">
+                                <check name="MISRAC2004-5.1" enabled="true" />
+                                <check name="MISRAC2004-5.2" enabled="true" />
+                                <check name="MISRAC2004-5.3" enabled="true" />
+                                <check name="MISRAC2004-5.4" enabled="true" />
+                                <check name="MISRAC2004-5.5" enabled="false" />
+                                <check name="MISRAC2004-5.6" enabled="false" />
+                                <check name="MISRAC2004-5.7" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-6">
+                                <check name="MISRAC2004-6.1" enabled="true" />
+                                <check name="MISRAC2004-6.2" enabled="true" />
+                                <check name="MISRAC2004-6.3" enabled="false" />
+                                <check name="MISRAC2004-6.4" enabled="true" />
+                                <check name="MISRAC2004-6.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-7">
+                                <check name="MISRAC2004-7.1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-8">
+                                <check name="MISRAC2004-8.1" enabled="true" />
+                                <check name="MISRAC2004-8.2" enabled="true" />
+                                <check name="MISRAC2004-8.3" enabled="true" />
+                                <check name="MISRAC2004-8.5_a" enabled="true" />
+                                <check name="MISRAC2004-8.5_b" enabled="true" />
+                                <check name="MISRAC2004-8.6" enabled="true" />
+                                <check name="MISRAC2004-8.7" enabled="true" />
+                                <check name="MISRAC2004-8.8_a" enabled="true" />
+                                <check name="MISRAC2004-8.8_b" enabled="true" />
+                                <check name="MISRAC2004-8.10" enabled="true" />
+                                <check name="MISRAC2004-8.12" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-9">
+                                <check name="MISRAC2004-9.1_a" enabled="true" />
+                                <check name="MISRAC2004-9.1_b" enabled="true" />
+                                <check name="MISRAC2004-9.1_c" enabled="true" />
+                                <check name="MISRAC2004-9.2" enabled="true" />
+                                <check name="MISRAC2004-9.3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-10">
+                                <check name="MISRAC2004-10.1_a" enabled="true" />
+                                <check name="MISRAC2004-10.1_b" enabled="true" />
+                                <check name="MISRAC2004-10.1_c" enabled="true" />
+                                <check name="MISRAC2004-10.1_d" enabled="true" />
+                                <check name="MISRAC2004-10.2_a" enabled="true" />
+                                <check name="MISRAC2004-10.2_b" enabled="true" />
+                                <check name="MISRAC2004-10.2_c" enabled="true" />
+                                <check name="MISRAC2004-10.2_d" enabled="true" />
+                                <check name="MISRAC2004-10.3" enabled="true" />
+                                <check name="MISRAC2004-10.4" enabled="true" />
+                                <check name="MISRAC2004-10.5" enabled="true" />
+                                <check name="MISRAC2004-10.6" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-11">
+                                <check name="MISRAC2004-11.1" enabled="true" />
+                                <check name="MISRAC2004-11.3" enabled="false" />
+                                <check name="MISRAC2004-11.4" enabled="false" />
+                                <check name="MISRAC2004-11.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-12">
+                                <check name="MISRAC2004-12.1" enabled="false" />
+                                <check name="MISRAC2004-12.2_a" enabled="true" />
+                                <check name="MISRAC2004-12.2_b" enabled="true" />
+                                <check name="MISRAC2004-12.2_c" enabled="true" />
+                                <check name="MISRAC2004-12.3" enabled="true" />
+                                <check name="MISRAC2004-12.4" enabled="true" />
+                                <check name="MISRAC2004-12.5" enabled="true" />
+                                <check name="MISRAC2004-12.6_a" enabled="false" />
+                                <check name="MISRAC2004-12.6_b" enabled="false" />
+                                <check name="MISRAC2004-12.7" enabled="true" />
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+                            <group enabled="true" name="CERT-DCL">
+                                <check name="CERT-DCL30-C_a" enabled="true" />
+                                <check name="CERT-DCL30-C_b" enabled="true" />
+                                <check name="CERT-DCL30-C_c" enabled="true" />
+                                <check name="CERT-DCL30-C_d" enabled="true" />
+                                <check name="CERT-DCL30-C_e" enabled="true" />
+                                <check name="CERT-DCL31-C" enabled="true" />
+                                <check name="CERT-DCL36-C" enabled="true" />
+                                <check name="CERT-DCL37-C_a" enabled="true" />
+                                <check name="CERT-DCL37-C_b" enabled="true" />
+                                <check name="CERT-DCL37-C_c" enabled="false" />
+                                <check name="CERT-DCL38-C" enabled="true" />
+                                <check name="CERT-DCL39-C" enabled="true" />
+                                <check name="CERT-DCL40-C" enabled="true" />
+                                <check name="CERT-DCL41-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check name="CERT-ENV30-C" enabled="true" />
+                                <check name="CERT-ENV31-C" enabled="true" />
+                                <check name="CERT-ENV32-C" enabled="true" />
+                                <check name="CERT-ENV33-C" enabled="true" />
+                                <check name="CERT-ENV34-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check name="CERT-ERR30-C_a" enabled="true" />
+                                <check name="CERT-ERR30-C_b" enabled="true" />
+                                <check name="CERT-ERR30-C_c" enabled="true" />
+                                <check name="CERT-ERR30-C_d" enabled="true" />
+                                <check name="CERT-ERR30-C_e" enabled="true" />
+                                <check name="CERT-ERR32-C" enabled="true" />
+                                <check name="CERT-ERR33-C_a" enabled="true" />
+                                <check name="CERT-ERR33-C_b" enabled="true" />
+                                <check name="CERT-ERR33-C_c" enabled="true" />
+                                <check name="CERT-ERR33-C_d" enabled="true" />
+                                <check name="CERT-ERR34-C_a" enabled="true" />
+                                <check name="CERT-ERR34-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-EXP">
+                                <check name="CERT-EXP19-C" enabled="true" />
+                                <check name="CERT-EXP30-C_a" enabled="true" />
+                                <check name="CERT-EXP30-C_b" enabled="true" />
+                                <check name="CERT-EXP32-C" enabled="true" />
+                                <check name="CERT-EXP33-C_a" enabled="true" />
+                                <check name="CERT-EXP33-C_b" enabled="true" />
+                                <check name="CERT-EXP33-C_c" enabled="true" />
+                                <check name="CERT-EXP33-C_d" enabled="true" />
+                                <check name="CERT-EXP33-C_e" enabled="true" />
+                                <check name="CERT-EXP33-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_a" enabled="true" />
+                                <check name="CERT-EXP34-C_b" enabled="true" />
+                                <check name="CERT-EXP34-C_c" enabled="true" />
+                                <check name="CERT-EXP34-C_d" enabled="true" />
+                                <check name="CERT-EXP34-C_e" enabled="true" />
+                                <check name="CERT-EXP34-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_g" enabled="true" />
+                                <check name="CERT-EXP35-C" enabled="true" />
+                                <check name="CERT-EXP36-C_a" enabled="true" />
+                                <check name="CERT-EXP36-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_a" enabled="true" />
+                                <check name="CERT-EXP37-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_a" enabled="true" />
+                                <check name="CERT-EXP39-C_b" enabled="true" />
+                                <check name="CERT-EXP39-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_d" enabled="true" />
+                                <check name="CERT-EXP39-C_e" enabled="true" />
+                                <check name="CERT-EXP40-C_a" enabled="true" />
+                                <check name="CERT-EXP40-C_b" enabled="true" />
+                                <check name="CERT-EXP42-C" enabled="true" />
+                                <check name="CERT-EXP43-C_a" enabled="true" />
+                                <check name="CERT-EXP43-C_b" enabled="true" />
+                                <check name="CERT-EXP43-C_c" enabled="true" />
+                                <check name="CERT-EXP43-C_d" enabled="true" />
+                                <check name="CERT-EXP44-C" enabled="true" />
+                                <check name="CERT-EXP45-C" enabled="true" />
+                                <check name="CERT-EXP46-C" enabled="true" />
+                                <check name="CERT-EXP47-C_a" enabled="true" />
+                                <check name="CERT-EXP47-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check name="CERT-FIO30-C" enabled="true" />
+                                <check name="CERT-FIO32-C" enabled="true" />
+                                <check name="CERT-FIO34-C" enabled="true" />
+                                <check name="CERT-FIO37-C" enabled="true" />
+                                <check name="CERT-FIO38-C" enabled="true" />
+                                <check name="CERT-FIO39-C" enabled="true" />
+                                <check name="CERT-FIO40-C" enabled="true" />
+                                <check name="CERT-FIO41-C" enabled="true" />
+                                <check name="CERT-FIO42-C_a" enabled="true" />
+                                <check name="CERT-FIO42-C_b" enabled="false" />
+                                <check name="CERT-FIO44-C" enabled="true" />
+                                <check name="CERT-FIO45-C" enabled="true" />
+                                <check name="CERT-FIO46-C_a" enabled="true" />
+                                <check name="CERT-FIO46-C_b" enabled="true" />
+                                <check name="CERT-FIO46-C_c" enabled="true" />
+                                <check name="CERT-FIO47-C_a" enabled="true" />
+                                <check name="CERT-FIO47-C_b" enabled="true" />
+                                <check name="CERT-FIO47-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check name="CERT-FLP30-C_a" enabled="true" />
+                                <check name="CERT-FLP30-C_b" enabled="true" />
+                                <check name="CERT-FLP32-C_a" enabled="true" />
+                                <check name="CERT-FLP32-C_b" enabled="true" />
+                                <check name="CERT-FLP34-C" enabled="true" />
+                                <check name="CERT-FLP36-C" enabled="true" />
+                                <check name="CERT-FLP37-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check name="CERT-INT30-C_a" enabled="true" />
+                                <check name="CERT-INT30-C_b" enabled="false" />
+                                <check name="CERT-INT31-C_a" enabled="true" />
+                                <check name="CERT-INT31-C_b" enabled="true" />
+                                <check name="CERT-INT31-C_c" enabled="true" />
+                                <check name="CERT-INT32-C_a" enabled="true" />
+                                <check name="CERT-INT32-C_b" enabled="false" />
+                                <check name="CERT-INT33-C_a" enabled="true" />
+                                <check name="CERT-INT33-C_b" enabled="true" />
+                                <check name="CERT-INT33-C_c" enabled="true" />
+                                <check name="CERT-INT33-C_d" enabled="true" />
+                                <check name="CERT-INT33-C_e" enabled="true" />
+                                <check name="CERT-INT33-C_f" enabled="true" />
+                                <check name="CERT-INT33-C_g" enabled="true" />
+                                <check name="CERT-INT33-C_h" enabled="true" />
+                                <check name="CERT-INT33-C_i" enabled="true" />
+                                <check name="CERT-INT34-C_a" enabled="true" />
+                                <check name="CERT-INT34-C_b" enabled="true" />
+                                <check name="CERT-INT34-C_c" enabled="true" />
+                                <check name="CERT-INT35-C" enabled="true" />
+                                <check name="CERT-INT36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check name="CERT-MEM30-C_a" enabled="true" />
+                                <check name="CERT-MEM30-C_b" enabled="true" />
+                                <check name="CERT-MEM30-C_c" enabled="true" />
+                                <check name="CERT-MEM31-C" enabled="true" />
+                                <check name="CERT-MEM33-C_a" enabled="true" />
+                                <check name="CERT-MEM33-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_a" enabled="true" />
+                                <check name="CERT-MEM34-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_c" enabled="true" />
+                                <check name="CERT-MEM35-C_a" enabled="true" />
+                                <check name="CERT-MEM35-C_b" enabled="true" />
+                                <check name="CERT-MEM35-C_c" enabled="true" />
+                                <check name="CERT-MEM36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check name="CERT-MSC30-C" enabled="true" />
+                                <check name="CERT-MSC32-C" enabled="true" />
+                                <check name="CERT-MSC33-C" enabled="false" />
+                                <check name="CERT-MSC37-C" enabled="true" />
+                                <check name="CERT-MSC38-C" enabled="true" />
+                                <check name="CERT-MSC39-C" enabled="true" />
+                                <check name="CERT-MSC40-C_a" enabled="true" />
+                                <check name="CERT-MSC40-C_b" enabled="true" />
+                                <check name="CERT-MSC40-C_c" enabled="true" />
+                                <check name="CERT-MSC40-C_d" enabled="true" />
+                                <check name="CERT-MSC40-C_e" enabled="false" />
+                                <check name="CERT-MSC41-C_a" enabled="true" />
+                                <check name="CERT-MSC41-C_b" enabled="true" />
+                                <check name="CERT-MSC41-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check name="CERT-PRE31-C" enabled="true" />
+                                <check name="CERT-PRE32-C_a" enabled="true" />
+                                <check name="CERT-PRE32-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-SIG">
+                                <check name="CERT-SIG30-C" enabled="true" />
+                                <check name="CERT-SIG31-C" enabled="true" />
+                                <check name="CERT-SIG34-C" enabled="true" />
+                                <check name="CERT-SIG35-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check name="CERT-STR30-C" enabled="true" />
+                                <check name="CERT-STR31-C_a" enabled="true" />
+                                <check name="CERT-STR31-C_b" enabled="true" />
+                                <check name="CERT-STR31-C_c" enabled="true" />
+                                <check name="CERT-STR31-C_d" enabled="true" />
+                                <check name="CERT-STR31-C_e" enabled="true" />
+                                <check name="CERT-STR31-C_f" enabled="true" />
+                                <check name="CERT-STR31-C_g" enabled="true" />
+                                <check name="CERT-STR31-C_h" enabled="true" />
+                                <check name="CERT-STR32-C" enabled="true" />
+                                <check name="CERT-STR34-C" enabled="true" />
+                                <check name="CERT-STR37-C" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="SECURITY" enabled="false">
+                            <group enabled="true" name="SEC-BUFFER">
+                                <check name="SEC-BUFFER-memory-leak-alias" enabled="true" />
+                                <check name="SEC-BUFFER-memory-leak" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-qsort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-qsort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-sprintf-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-std-sort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-std-sort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncmp-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncmp-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-alloc-size" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy-length" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-index" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-offset" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-all" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-DIV-0">
+                                <check name="SEC-DIV-0-compare-after" enabled="true" />
+                                <check name="SEC-DIV-0-compare-before" enabled="true" />
+                                <check name="SEC-DIV-0-tainted" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check name="SEC-FILEOP-open-no-close" enabled="true" />
+                                <check name="SEC-FILEOP-path-traversal" enabled="false" />
+                                <check name="SEC-FILEOP-use-after-close" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check name="SEC-INJECTION-sql" enabled="false" />
+                                <check name="SEC-INJECTION-xpath" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check name="SEC-LOOP-tainted-bound" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check name="SEC-NULL-assignment-fun-pos" enabled="false" />
+                                <check name="SEC-NULL-assignment" enabled="true" />
+                                <check name="SEC-NULL-cmp-aft" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef-fun" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef" enabled="true" />
+                                <check name="SEC-NULL-literal-pos" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check name="SEC-STRING-format-string" enabled="true" />
+                                <check name="SEC-STRING-hard-coded-credentials" enabled="false" />
+                            </group>
+                        </package>
+                        <package name="MISRAC2004" enabled="false">
+                            <group enabled="true" name="MISRAC2004-1">
+                                <check name="MISRAC2004-1.1" enabled="true" />
+                                <check name="MISRAC2004-1.2_a" enabled="true" />
+                                <check name="MISRAC2004-1.2_b" enabled="true" />
+                                <check name="MISRAC2004-1.2_c" enabled="true" />
+                                <check name="MISRAC2004-1.2_d" enabled="true" />
+                                <check name="MISRAC2004-1.2_e" enabled="true" />
+                                <check name="MISRAC2004-1.2_f" enabled="true" />
+                                <check name="MISRAC2004-1.2_g" enabled="true" />
+                                <check name="MISRAC2004-1.2_h" enabled="true" />
+                                <check name="MISRAC2004-1.2_i" enabled="true" />
+                                <check name="MISRAC2004-1.2_j" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-2">
+                                <check name="MISRAC2004-2.1" enabled="true" />
+                                <check name="MISRAC2004-2.2" enabled="true" />
+                                <check name="MISRAC2004-2.3" enabled="true" />
+                                <check name="MISRAC2004-2.4" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-5">
+                                <check name="MISRAC2004-5.1" enabled="true" />
+                                <check name="MISRAC2004-5.2" enabled="true" />
+                                <check name="MISRAC2004-5.3" enabled="true" />
+                                <check name="MISRAC2004-5.4" enabled="true" />
+                                <check name="MISRAC2004-5.5" enabled="false" />
+                                <check name="MISRAC2004-5.6" enabled="false" />
+                                <check name="MISRAC2004-5.7" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-6">
+                                <check name="MISRAC2004-6.1" enabled="true" />
+                                <check name="MISRAC2004-6.2" enabled="true" />
+                                <check name="MISRAC2004-6.3" enabled="false" />
+                                <check name="MISRAC2004-6.4" enabled="true" />
+                                <check name="MISRAC2004-6.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-7">
+                                <check name="MISRAC2004-7.1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-8">
+                                <check name="MISRAC2004-8.1" enabled="true" />
+                                <check name="MISRAC2004-8.2" enabled="true" />
+                                <check name="MISRAC2004-8.3" enabled="true" />
+                                <check name="MISRAC2004-8.5_a" enabled="true" />
+                                <check name="MISRAC2004-8.5_b" enabled="true" />
+                                <check name="MISRAC2004-8.6" enabled="true" />
+                                <check name="MISRAC2004-8.7" enabled="true" />
+                                <check name="MISRAC2004-8.8_a" enabled="true" />
+                                <check name="MISRAC2004-8.8_b" enabled="true" />
+                                <check name="MISRAC2004-8.10" enabled="true" />
+                                <check name="MISRAC2004-8.12" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-9">
+                                <check name="MISRAC2004-9.1_a" enabled="true" />
+                                <check name="MISRAC2004-9.1_b" enabled="true" />
+                                <check name="MISRAC2004-9.1_c" enabled="true" />
+                                <check name="MISRAC2004-9.2" enabled="true" />
+                                <check name="MISRAC2004-9.3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-10">
+                                <check name="MISRAC2004-10.1_a" enabled="true" />
+                                <check name="MISRAC2004-10.1_b" enabled="true" />
+                                <check name="MISRAC2004-10.1_c" enabled="true" />
+                                <check name="MISRAC2004-10.1_d" enabled="true" />
+                                <check name="MISRAC2004-10.2_a" enabled="true" />
+                                <check name="MISRAC2004-10.2_b" enabled="true" />
+                                <check name="MISRAC2004-10.2_c" enabled="true" />
+                                <check name="MISRAC2004-10.2_d" enabled="true" />
+                                <check name="MISRAC2004-10.3" enabled="true" />
+                                <check name="MISRAC2004-10.4" enabled="true" />
+                                <check name="MISRAC2004-10.5" enabled="true" />
+                                <check name="MISRAC2004-10.6" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-11">
+                                <check name="MISRAC2004-11.1" enabled="true" />
+                                <check name="MISRAC2004-11.3" enabled="false" />
+                                <check name="MISRAC2004-11.4" enabled="false" />
+                                <check name="MISRAC2004-11.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-12">
+                                <check name="MISRAC2004-12.1" enabled="false" />
+                                <check name="MISRAC2004-12.2_a" enabled="true" />
+                                <check name="MISRAC2004-12.2_b" enabled="true" />
+                                <check name="MISRAC2004-12.2_c" enabled="true" />
+                                <check name="MISRAC2004-12.3" enabled="true" />
+                                <check name="MISRAC2004-12.4" enabled="true" />
+                                <check name="MISRAC2004-12.5" enabled="true" />
+                                <check name="MISRAC2004-12.6_a" enabled="false" />
+                                <check name="MISRAC2004-12.6_b" enabled="false" />
+                                <check name="MISRAC2004-12.7" enabled="true" />
+                                <check name="MISRAC2004-12.8" enabled="true" />
+                                <check name="MISRAC2004-12.9" enabled="true" />
+                                <check name="MISRAC2004-12.10" enabled="true" />
+                                <check name="MISRAC2004-12.11" enabled="false" />
+                                <check name="MISRAC2004-12.12_a" enabled="true" />
+                                <check name="MISRAC2004-12.12_b" enabled="true" />
+                                <check name="MISRAC2004-12.13" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-13">
+                                <check name="MISRAC2004-13.1" enabled="true" />
+                                <check name="MISRAC2004-13.2_a" enabled="false" />
+                                <check name="MISRAC2004-13.2_b" enabled="false" />
+                                <check name="MISRAC2004-13.2_c" enabled="false" />
+                                <check name="MISRAC2004-13.2_d" enabled="false" />
+                                <check name="MISRAC2004-13.2_e" enabled="false" />
+                                <check name="MISRAC2004-13.3" enabled="true" />
+                                <check name="MISRAC2004-13.4" enabled="true" />
+                                <check name="MISRAC2004-13.5" enabled="true" />
+                                <check name="MISRAC2004-13.6" enabled="true" />
+                                <check name="MISRAC2004-13.7_a" enabled="true" />
+                                <check name="MISRAC2004-13.7_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-14">
+                                <check name="MISRAC2004-14.1" enabled="true" />
+                                <check name="MISRAC2004-14.2" enabled="true" />
+                                <check name="MISRAC2004-14.3" enabled="true" />
+                                <check name="MISRAC2004-14.4" enabled="true" />
+                                <check name="MISRAC2004-14.5" enabled="true" />
+                                <check name="MISRAC2004-14.6" enabled="true" />
+                                <check name="MISRAC2004-14.7" enabled="true" />
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+                                <check name="MISRAC++2008-18-0-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-2">
+                                <check name="MISRAC++2008-18-2-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-4">
+                                <check name="MISRAC++2008-18-4-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-7">
+                                <check name="MISRAC++2008-18-7-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-19-3">
+                                <check name="MISRAC++2008-19-3-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-27-0">
+                                <check name="MISRAC++2008-27-0-1" enabled="true" />
+                            </group>
+                        </package>
+                    </checks_tree>
+                </cstat_settings>
+            </data>
+        </settings>
+        <settings>
+            <name>RuntimeChecking</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>GenRtcDebugHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnableBoundsChecking</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrMem</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcTrackPointerBounds</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckAccesses</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcGenerateEntries</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcNrTrackedPointers</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>GenRtcIntOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIncUnsigned</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntConversion</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclExplicit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclUnsignedShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcUnhandledCase</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcDivByZero</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrFunc</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+    </configuration>
+    <group>
+        <name>Applications</name>
+        <file>
+            <name>$PROJ_DIR$\src\hal_entry.c</name>
+        </file>
+    </group>
+    <group>
+        <name>CherryECAT</name>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\phy\chry_phy.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_cmd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_coe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_common.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_datagram.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_foe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_mailbox.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_master.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_netdev.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\osal\ec_osal_rtthread.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_perf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_sii.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_slave.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\src\ec_timestamp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\packages\CherryECAT-latest\port\netdev_renesas.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Compiler</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cctype.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cstdlib.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cstring.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\ctime.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cunistd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\common\cwchar.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\environ.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_close.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_lseek.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_mem.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_open.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_read.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_remove.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_write.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscalls.c</name>
+        </file>
+    </group>
+    <group>
+        <name>CPU</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\backtrace.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\context_iar.S</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\cpuport.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\gicv3.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\interrupt.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\stack.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\start_iar.S</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\trap.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\vector_iar.S</name>
+        </file>
+    </group>
+    <group>
+        <name>DeviceDrivers</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\completion.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\condvar.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\dataqueue.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\core\device.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\hwtimer\hwtimer.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\pin\pin.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\pipe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\ringblk_buf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\ringbuffer.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\serial\serial_v2.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\waitqueue.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\drivers\ipc\workqueue.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Drivers</name>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_common.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_gpio.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\libraries\HAL_Drivers\drv_usart_v2.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Finsh</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\cmd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\msh.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\msh_parse.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\components\finsh\shell.c</name>
+        </file>
+    </group>
+    <group>
+        <name>Kernel</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\clock.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\components.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\idle.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\ipc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\irq.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\kservice.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\klibc\kstdio.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\klibc\kstring.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\mem.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\mempool.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\object.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\scheduler_comm.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\scheduler_up.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\thread.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\src\timer.c</name>
+        </file>
+    </group>
+    <group>
+        <name>libcpu</name>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\common\atomic_arm.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\common\div0.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rt-thread\libcpu\arm\common\showmem.c</name>
+        </file>
+    </group>
+    <group>
+        <name>POSIX</name>
+    </group>
+    <group>
+        <name>RZN</name>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_address_expander.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_cache.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_cache_core.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_clocks.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_common.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_ddr.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_ddr_fw_param.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_delay.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_delay_core.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_io.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_irq.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_irq_core.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_irq_sense.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_loader_param.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_register_protection.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_reset.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_sbrk.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_semaphore.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_slave_stop.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_tzc400.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_ether_phy\r_ether_phy.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_ether_selector\r_ether_selector.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_ethsw\r_ethsw.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_gmac\r_gmac.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_gpt\r_gpt.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_ioport\r_ioport.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_mtu3\r_mtu3.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\r_sci_uart\r_sci_uart.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\startup.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\startup_core.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\system.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\system_core.c</name>
+        </file>
+    </group>
+    <group>
+        <name>RZN_cfg</name>
+    </group>
+    <group>
+        <name>RZN_gen</name>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\common_data.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\hal_data.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\main.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\pin_data.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\rzn_gen\vector_data.c</name>
+        </file>
+    </group>
+    <file>
+        <name>$PROJ_DIR$\buildinfo.ipcf</name>
+    </file>
+</project>
diff --git a/projects/etherkit_ethercat_cherryecat/project.eww b/projects/etherkit_ethercat_cherryecat/project.eww
new file mode 100644
index 00000000..faa93f37
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/project.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
diff --git a/projects/etherkit_ethercat_cherryecat/rtconfig.h b/projects/etherkit_ethercat_cherryecat/rtconfig.h
new file mode 100644
index 00000000..b1a94ea2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rtconfig.h
@@ -0,0 +1,366 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+
+/* kservice optimization */
+
+#define RT_KPRINTF_USING_LONGLONG
+/* end of kservice optimization */
+#define RT_USING_DEBUG
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+/* end of Memory Management */
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 512
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50100
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
+#define RT_USING_HW_ATOMIC
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_R
+#define ARCH_ARM_CORTEX_R52
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+/* end of DFS: device virtual file system */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V2
+#define RT_SERIAL_USING_DMA
+#define RT_USING_PIN
+#define RT_USING_HWTIMER
+
+/* Using USB */
+
+/* end of Using USB */
+/* end of Device Drivers */
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
+
+/* Network */
+
+/* end of Network */
+
+/* Memory protection */
+
+/* end of Memory protection */
+
+/* Utilities */
+
+/* end of Utilities */
+/* end of RT-Thread Components */
+
+/* RT-Thread Utestcases */
+
+/* end of RT-Thread Utestcases */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* end of Marvell WiFi */
+
+/* Wiced WiFi */
+
+/* end of Wiced WiFi */
+
+/* CYW43012 WiFi */
+
+/* end of CYW43012 WiFi */
+
+/* BL808 WiFi */
+
+/* end of BL808 WiFi */
+
+/* CYW43439 WiFi */
+
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
+
+/* IoT Cloud */
+
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
+
+/* security packages */
+
+/* end of security packages */
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+/* XML: Extensible Markup Language */
+
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
+
+/* u8g2: a monochrome graphic library */
+
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
+
+/* tools packages */
+
+/* end of tools packages */
+
+/* system packages */
+
+/* enhanced kernel services */
+
+/* end of enhanced kernel services */
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+/* end of Micrium: Micrium software products porting for RT-Thread */
+#define PKG_USING_CHERRYECAT
+#define PKG_CHERRYECAT_NETDEV_RENESAS
+#define PKG_USING_CHERRYECAT_LATEST_VERSION
+/* end of system packages */
+
+/* peripheral libraries and drivers */
+
+/* HAL & SDK Drivers */
+
+/* STM32 HAL & SDK Drivers */
+
+/* end of STM32 HAL & SDK Drivers */
+
+/* Infineon HAL Packages */
+
+/* end of Infineon HAL Packages */
+
+/* Kendryte SDK */
+
+/* end of Kendryte SDK */
+
+/* WCH HAL & SDK Drivers */
+
+/* end of WCH HAL & SDK Drivers */
+
+/* AT32 HAL & SDK Drivers */
+
+/* end of AT32 HAL & SDK Drivers */
+
+/* HC32 DDL Drivers */
+
+/* end of HC32 DDL Drivers */
+
+/* NXP HAL & SDK Drivers */
+
+/* end of NXP HAL & SDK Drivers */
+
+/* NUVOTON Drivers */
+
+/* end of NUVOTON Drivers */
+
+/* GD32 Drivers */
+
+/* end of GD32 Drivers */
+
+/* HPMicro SDK */
+
+/* end of HPMicro SDK */
+/* end of HAL & SDK Drivers */
+
+/* sensors drivers */
+
+/* end of sensors drivers */
+
+/* touch drivers */
+
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
+
+/* AI packages */
+
+/* end of AI packages */
+
+/* Signal Processing and Control Algorithm Packages */
+
+/* end of Signal Processing and Control Algorithm Packages */
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* end of project laboratory */
+
+/* samples: kernel and components samples */
+
+/* end of samples: kernel and components samples */
+
+/* entertainment: terminal games and other interesting software packages */
+
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+/* end of Projects and Demos */
+
+/* Sensors */
+
+/* end of Sensors */
+
+/* Display */
+
+/* end of Display */
+
+/* Timing */
+
+/* end of Timing */
+
+/* Data Processing */
+
+/* end of Data Processing */
+
+/* Data Storage */
+
+/* Communication */
+
+/* end of Communication */
+
+/* Device Control */
+
+/* end of Device Control */
+
+/* Other */
+
+/* end of Other */
+
+/* Signal IO */
+
+/* end of Signal IO */
+
+/* Uncategorized */
+
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
+#define SOC_FAMILY_RENESAS_RZ
+#define SOC_SERIES_R9A07G0
+
+/* Hardware Drivers Config */
+
+#define SOC_R9A07G084
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_UART0_RX_BUFSIZE 256
+#define BSP_UART0_TX_BUFSIZE 0
+/* end of On-chip Peripheral Drivers */
+
+/* Board extended module Drivers */
+
+/* end of Board extended module Drivers */
+/* end of Hardware Drivers Config */
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rtconfig.py b/projects/etherkit_ethercat_cherryecat/rtconfig.py
new file mode 100644
index 00000000..006bdd85
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rtconfig.py
@@ -0,0 +1,121 @@
+import os
+import sys
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-r52'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armclang'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iccarm'
+    EXEC_PATH   = r'D:/IAR Systems/Embedded Workbench 9.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+# BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    NM = PREFIX + 'nm'
+    DEVICE = ' -mcpu=cortex-r52 -marm -mfloat-abi=hard -mfpu=neon-fp-armv8 -fdiagnostics-parseable-fixits -Og -fmessage-length=0 -fsigned-char -fdata-sections -funwind-tables -ffunction-sections -fno-strict-aliasing -g -gdwarf-4'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_init -lgcc -lrdimon -T script/fsp_xspi0_boot_scons.ld -L script/'
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -Og'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -Os'
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n'
+    # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'iccarm':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-R52'
+    CFLAGS += ' -e'
+    CFLAGS += ' --arm'
+    CFLAGS += ' --float-abi=hard'
+    CFLAGS += ' --fpu=neon-fp-armv8'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-R52'
+    AFLAGS += ' --arm'
+    AFLAGS += ' --float-abi hard'
+    AFLAGS += ' --fpu neon-fp-armv8'
+    # AFLAGS += ' --unaligned-access'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "script/fsp_xspi0_boot.icf"'
+    LFLAGS += ' --entry Reset_Handler'
+
+    CXXFLAGS = CFLAGS
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/SConscript b/projects/etherkit_ethercat_cherryecat/rzn/SConscript
new file mode 100644
index 00000000..ee3d8421
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/SConscript
@@ -0,0 +1,25 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+from gcc import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM():
+    if rtconfig.PLATFORM == 'iccarm' or GetOption('target') != 'mdk5':
+        src += Glob('./fsp/src/bsp/mcu/all/*.c')
+        src += Glob('./fsp/src/bsp/mcu/all/cr/*.c')
+        src += Glob('./fsp/src/bsp/mcu/r*/*.c')
+        src += Glob('./fsp/src/bsp/cmsis/Device/RENESAS/Source/*.c')
+        src += Glob('./fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/*.c')
+        src += Glob('./fsp/src/r_*/*.c')
+        CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core_R/Include',
+                            cwd + '/fsp/inc',
+                            cwd + '/fsp/inc/api',
+                            cwd + '/fsp/inc/instances',]
+
+group = DefineGroup('RZN', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h
new file mode 100644
index 00000000..e1e68604
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h
@@ -0,0 +1,290 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @date     31. August 2021
+ ******************************************************************************/
+/*
+ * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This file is based on the "\CMSIS\Core\Include\cmsis_compliler.h"
+ *
+ * Changes:
+ *    - No Changes.
+ */
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h
new file mode 100644
index 00000000..174b5b8e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h
@@ -0,0 +1,783 @@
+/**************************************************************************//**
+ * @file     cmsis_cp15.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @date     02. February 2024
+ ******************************************************************************/
+/*
+ * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This file is based on the "CMSIS\Core_A\Include\cmsis_cp15.h"
+ *
+ * Changes:
+ * Renesas Electronics Corporation on 2021-08-31
+ *    - Changed to be related to Cortex-R52 by
+ * Renesas Electronics Corporation on 2024-02-02
+ *    - Functions are sorted according to the Arm technical reference.
+ *    - Added some functions to convert BSP into C language.
+ */
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_CP15_H
+#define __CMSIS_CP15_H
+
+/** \brief  Get CTR
+    \return               Cache Type Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CTR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 0, 0, 1);
+  return result;
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 0, 0, 5);
+  return result;
+}
+
+/** \brief  Get CCSIDR
+    \return CCSIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
+{
+  uint32_t result;
+  __get_CP(15, 1, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Get CLIDR
+    \return CLIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
+{
+  uint32_t result;
+  __get_CP(15, 1, result, 0, 0, 1);
+  return result;
+}
+
+/** \brief  Get CSSELR
+    \return CSSELR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
+{
+  uint32_t result;
+  __get_CP(15, 2, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Set CSSELR
+ */
+__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
+{
+  __set_CP(15, 2, value, 0, 0, 0);
+}
+
+/** \brief  Get SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \return               System Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 0);
+  return result;
+}
+
+/** \brief  Set SCTLR
+    \param [in]    value  System Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_SCTLR(uint32_t value)
+{
+  __set_CP(15, 0, value, 1, 0, 0);
+}
+
+
+/** \brief  Get ACTLR
+    \return               Auxiliary Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return(result);
+}
+
+/** \brief  Set ACTLR
+    \param [in]    value  Auxiliary Control value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTLR(uint32_t value)
+{
+  __set_CP(15, 0, value, 1, 0, 1);
+}
+
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 2);
+  return result;
+}
+
+/** \brief  Set CPACR
+    \param [in]    value  Coprocessor Access Control value to set
+ */
+__STATIC_FORCEINLINE void __set_CPACR(uint32_t value)
+{
+  __set_CP(15, 0, value, 1, 0, 2);
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 2, 0, 0);
+  return result;
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    value  Translation Table Base Register 0 value to set
+ */
+__STATIC_FORCEINLINE void __set_TTBR0(uint32_t value)
+{
+  __set_CP(15, 0, value, 2, 0, 0);
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 3, 0, 0);
+  return result;
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    value   Domain Access Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_DACR(uint32_t value)
+{
+  __set_CP(15, 0, value, 3, 0, 0);
+}
+
+/** \brief  Get ICC_PMR
+ */
+__STATIC_FORCEINLINE uint32_t __get_ICC_PMR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 4, 6, 0);
+  return result;
+}
+
+/** \brief  Set ICC_PMR
+ */
+__STATIC_FORCEINLINE void __set_ICC_PMR(uint32_t value)
+{
+  __set_CP(15, 0, value, 4, 6, 0);
+}
+
+/** \brief  Get DFSR
+    \return               Data Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 0);
+  return result;
+}
+
+/** \brief  Set DFSR
+    \param [in]    value  Data Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_DFSR(uint32_t value)
+{
+  __set_CP(15, 0, value, 5, 0, 0);
+}
+
+/** \brief  Get IFSR
+    \return               Instruction Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 1);
+  return result;
+}
+
+/** \brief  Set IFSR
+    \param [in]    value  Instruction Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_IFSR(uint32_t value)
+{
+  __set_CP(15, 0, value, 5, 0, 1);
+}
+
+/** \brief  Set PRSELR
+
+    This function assigns the given value to the Protection Region Selection Register.
+
+    \param [in]    value  Protection Region Selection Register to set
+ */
+__STATIC_FORCEINLINE void __set_PRSELR(uint32_t value)
+{
+  __set_CP(15, 0, value, 6, 2, 1);
+}
+
+/** \brief  Get PRBAR
+
+    This function returns the value of the Protection Region Base Address Register.
+
+    \return               Protection Region Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 6, 3, 0);
+  return result;
+}
+
+/** \brief  Set PRBAR
+
+    This function assigns the given value to the Protection Region Base Address Register.
+
+    \param [in]    value  Protection Region Base Address Register to set
+ */
+__STATIC_FORCEINLINE void __set_PRBAR(uint32_t value)
+{
+  __set_CP(15, 0, value, 6, 3, 0);
+}
+
+/** \brief  Get PRLAR
+
+    This function returns the value of the Protection Region Limit Address Register.
+
+    \return               Protection Region Limit Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRLAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 6, 3, 1);
+  return result;
+}
+
+/** \brief  Set PRLAR
+
+    This function assigns the given value to the Protection Region Limit Address Register.
+
+    \param [in]    value  Protection Region Limit Address Register to set
+ */
+__STATIC_FORCEINLINE void __set_PRLAR(uint32_t value)
+{
+  __set_CP(15, 0, value, 6, 3, 1);
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 0);
+}
+
+/** \brief  Set ICIVAU
+ */
+__STATIC_FORCEINLINE void __set_ICIVAU(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 1);
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 6);
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 6, 1);
+}
+
+/** \brief  Set DCIVAC
+ */
+__STATIC_FORCEINLINE void __set_DCIVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 6, 1);
+}
+
+/** \brief  Set DCISW
+ */
+__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 6, 2);
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 10, 1);
+}
+
+/** \brief  Set DCCVAC
+ */
+__STATIC_FORCEINLINE void __set_DCCVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 10, 1);
+}
+
+/** \brief  Set DCCSW
+ */
+__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 10, 2);
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 14, 1);
+}
+
+/** \brief  Set DCCIVAC
+ */
+__STATIC_FORCEINLINE void __set_DCCIVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 14, 1);
+}
+
+/** \brief  Set DCCISW
+ */
+__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 14, 2);
+}
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 8, 7, 0);
+}
+
+/** \brief  Set MAIR0
+
+    This function assigns the given value to the Memory Attribute Indirection Registers 0.
+
+    \param [in]    value  Memory Attribute Indirection Registers 0 to set
+ */
+__STATIC_FORCEINLINE void __set_MAIR0(uint32_t value)
+{
+  __set_CP(15, 0, value, 10, 2, 0);
+}
+
+/** \brief  Set MAIR1
+
+    This function assigns the given value to the Memory Attribute Indirection Registers 1.
+
+    \param [in]    value  Memory Attribute Indirection Registers 1 to set
+ */
+__STATIC_FORCEINLINE void __set_MAIR1(uint32_t value)
+{
+  __set_CP(15, 0, value, 10, 2, 1);
+}
+
+/** \brief  Get IMP_SLAVEPCTLR
+
+    This function returns the value of the Slave Port Control Register.
+
+    \return                 Slave Port Control Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_IMP_SLAVEPCTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 11, 0, 0);
+  return result;
+}
+
+/** \brief  Set IMP_SLAVEPCTLR
+
+    This function assigns the given value to the Slave Port Control Register.
+
+    \param [in]    value    Slave Port Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_IMP_SLAVEPCTLR(uint32_t value)
+{
+  __set_CP(15, 0, value, 11, 0, 0);
+}
+
+/** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 0);
+  return result;
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    value  Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_VBAR(uint32_t value)
+{
+  __set_CP(15, 0, value, 12, 0, 0);
+}
+
+/** \brief  Get MVBAR
+
+    This function returns the value of the Monitor Vector Base Address Register.
+
+    \return               Monitor Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 1);
+  return result;
+}
+
+/** \brief  Set MVBAR
+
+    This function assigns the given value to the Monitor Vector Base Address Register.
+
+    \param [in]    value  Monitor Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_MVBAR(uint32_t value)
+{
+  __set_CP(15, 0, value, 12, 0, 1);
+}
+
+/** \brief  Get ISR
+    \return               Interrupt Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ISR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 1, 0);
+  return result;
+}
+
+/** \brief  Get ICC_RPR
+ */
+__STATIC_FORCEINLINE uint32_t __get_ICC_RPR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 11, 3);
+  return result;
+}
+
+/** \brief  Get ICC_IAR1
+ */
+__STATIC_FORCEINLINE uint32_t __get_ICC_IAR1(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 12, 0);
+  return result;
+}
+
+/** \brief  Set ICC_EOIR1
+ */
+__STATIC_FORCEINLINE void __set_ICC_EOIR1(uint32_t value)
+{
+  __set_CP(15, 0, value, 12, 12, 0);
+}
+
+/** \brief  Get ICC_HPPIR1
+ */
+__STATIC_FORCEINLINE uint32_t __get_ICC_HPPIR1(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 12, 2);
+  return result;
+}
+
+/** \brief  Get ICC_BPR1
+ */
+__STATIC_FORCEINLINE uint32_t __get_ICC_BPR1(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 12, 3);
+  return result;
+}
+
+/** \brief  Set ICC_BPR1
+ */
+__STATIC_FORCEINLINE void __set_ICC_BPR1(uint32_t value)
+{
+  __set_CP(15, 0, value, 12, 12, 3);
+}
+
+/** \brief  Get ICC_CTLR
+ */
+__STATIC_FORCEINLINE uint32_t __get_ICC_CTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 12, 4);
+  return result;
+}
+
+/** \brief  Set ICC_CTLR
+ */
+__STATIC_FORCEINLINE void __set_ICC_CTLR(uint32_t value)
+{
+  __set_CP(15, 0, value, 12, 12, 4);
+}
+
+/** \brief  Set ICC_IGRPEN1
+ */
+__STATIC_FORCEINLINE void __set_ICC_IGRPEN1(uint32_t value)
+{
+  __set_CP(15, 0, value, 12, 12, 7);
+}
+
+/** \brief  Set CNTFRQ
+
+  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+  \param [in]    value  CNTFRQ Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 0, 0);
+}
+
+/** \brief  Get CNTFRQ
+
+    This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+    \return               CNTFRQ Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 0, 0);
+  return result;
+}
+
+/** \brief  Set CNTKCTL
+
+  This function assigns the given value to Counter-timer Kernel Control Register (CNTKCTL).
+
+  \param [in]    value  CNTKCTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTKCTL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 1, 0);
+}
+
+/** \brief  Get CNTKCTL
+
+    This function returns the value of the Counter-timer kernel Control Register (CNTKCTL).
+
+    \return               CNTFRQ Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTKCTL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 1, 0);
+  return result;
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 0);
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 0);
+  return result;
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 1);
+}
+
+/** \brief  Get CNTP_CTL register
+    \return               CNTP_CTL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 1);
+  return result;
+}
+
+/** \brief  Set CNTV_CTL
+
+  This function assigns the given value to PL1 Virtual Timer Control Register (CNTV_CTL).
+
+  \param [in]    value  CNTV_CTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTV_CTL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 3, 1);
+}
+
+/** \brief  Get CNTV_CTL register
+    \return               CNTV_CTL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTV_CTL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 3, 1);
+  return result;
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 4, result, 15, 0, 0);
+  return result;
+}
+
+/** \brief  Get CNTPCT
+
+    This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
+
+    \return               CNTPCT Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
+{
+  uint64_t result;
+  __get_CP64(15, 0, result, 14);
+  return result;
+}
+
+/** \brief  Set ICC_SGI1R
+ */
+__STATIC_FORCEINLINE void __set_ICC_SGI1R(uint64_t value)
+{
+  __set_CP64(15, 0, value, 12);
+}
+
+/** \brief  Get CNTVCT
+
+    This function returns the value of the 64 bits PL1 Virtual Count Register (CNTVCT).
+
+    \return               CNTVCT Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTVCT(void)
+{
+  uint64_t result;
+  __get_CP64(15, 1, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CVAL
+
+  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+  \param [in]    value  CNTP_CVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
+{
+  __set_CP64(15, 2, value, 14);
+}
+
+/** \brief  Get CNTP_CVAL
+
+    This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+    \return               CNTP_CVAL Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
+{
+  uint64_t result;
+  __get_CP64(15, 2, result, 14);
+  return result;
+}
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h
new file mode 100644
index 00000000..1e6e8bdd
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h
@@ -0,0 +1,2233 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @date     02. February 2024
+ ******************************************************************************/
+/*
+ * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This file is based on the "\CMSIS\Core\Include\cmsis_gcc.h"
+ *
+ * Changes:
+ * Renesas Electronics Corporation on 2021-08-31
+ *    - Add CP15 descriptions by
+ * Renesas Electronics Corporation on 2024-02-02
+ *    - Added functions related to FPEXC registers.
+ */
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+  \brief   Initializes data and bss sections
+  \details This default implementations initialized all data and additional bss
+           sections relying on .copy.table and .zero.table specified properly
+           in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+  extern void _start(void) __NO_RETURN;
+
+  typedef struct {
+    uint32_t const* src;
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __copy_table_t;
+
+  typedef struct {
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __zero_table_t;
+
+  extern const __copy_table_t __copy_table_start__;
+  extern const __copy_table_t __copy_table_end__;
+  extern const __zero_table_t __zero_table_start__;
+  extern const __zero_table_t __zero_table_end__;
+
+  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = pTable->src[i];
+    }
+  }
+
+  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = 0u;
+    }
+  }
+
+  _start();
+}
+
+#define __PROGRAM_START           __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+/**
+ * \brief   Get FPEXC
+ * \details Returns the current value of the Floating Point Exception Control register.
+ * \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC (void)
+{
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+    (defined(__FPU_USED) && (__FPU_USED == 1U)))
+
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpexc" : "=r" (result));
+
+    return result;
+#else
+
+    return 0U;
+#endif
+}
+
+/**
+ * \brief   Set FPEXC
+ * \details Assigns the given value to the Floating Point Exception Control register.
+ * \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC (uint32_t fpexc)
+{
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+    (defined(__FPU_USED) && (__FPU_USED == 1U)))
+
+    __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#else
+    (void) fpexc;
+#endif
+}
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi":::"memory")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe":::"memory")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+
+  return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h
new file mode 100644
index 00000000..a6882cfe
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h
@@ -0,0 +1,958 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @date     02. February 2024
+ ******************************************************************************/
+// ------------------------------------------------------------------------------
+//
+// Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+//
+// This file is based on the "\CMSIS\Core\Include\cmsis_iccarm.h"
+//
+// Changes:
+// Renesas Electronics Corporation on 2021-08-31
+//    - Changed to be related to Cortex-R52 by
+// Renesas Electronics Corporation on 2024-02-02
+//    - Added functions related to FPEXC registers.
+//    - Moved the process of defining compiler macros for CPU architectures to renesas.h.
+//
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+
+    #define __get_FPEXC()             (__arm_rsr("FPEXC"))
+    #define __set_FPEXC(VALUE)        (__arm_wsr("FPEXC", (VALUE)))
+   #else
+    #define __get_FPSCR()             (0)
+    #define __set_FPSCR(VALUE)        ((void) VALUE)
+
+    #define __get_FPEXC()             (0)
+    #define __set_FPEXC(VALUE)        ((void) VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
+    ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
+
+  #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
+    (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
+
+  #define __get_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+
+  #define __set_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+  #include "cmsis_cp15.h"
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+
+    #define __get_FPEXC()       (0)
+    #define __set_FPEXC(VALUE)  ((void) VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h
new file mode 100644
index 00000000..fa9f84c1
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h
@@ -0,0 +1,46 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @date     31. August 2021
+ ******************************************************************************/
+/*
+ * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This file is based on the "\CMSIS\Core\Include\cmsis_version.h"
+ *
+ * Changes:
+ *    - No Changes.
+ */
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h
new file mode 100644
index 00000000..615ae49a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h
@@ -0,0 +1,312 @@
+/**************************************************************************//**
+ * @file     core_cr52.h
+ * @brief    CMSIS Cortex-R52 Core Peripheral Access Layer Header File
+ * @date     31. August 2021
+ ******************************************************************************/
+/*
+ * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This file is based on the "\CMSIS\Core\Include\core_armv8mml.h"
+ *
+ * Changes:
+ * Renesas Electronics Corporation on 2021-08-31
+ *    - Changed to be related to Cortex-R52 by
+ */
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CR52_H_GENERIC
+#define __CORE_CR52_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_R52
+  @{
+ */
+
+#if defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+      #define __FPU_D32        1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+      #ifndef __ARMVFP_D16__
+        #define __FPU_D32      1U
+      #endif
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+#endif
+
+#include "cmsis_version.h"
+
+/* CMSIS CR52 definitions */
+#define __CR52_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CR52_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CR52_CMSIS_VERSION       ((__CR52_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CR52_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_R                 (52U)                                      /*!< Cortex-R Core                    */
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CR52_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CR52_H_DEPENDANT
+#define __CORE_CR52_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_R52 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_GIC  Generic Interrupt Controller (GIC)
+  \brief      Type definitions for the GIC Registers
+  @{
+*/
+
+ /**
+  \brief  Structure type to access the Generic Interrupt Controller (GIC) for GICD.
+ */
+typedef struct
+{
+  __IOM uint32_t GICD_CTLR;                  /*!< Offset: 0x0000 (R/W)  Distributor Control Register */
+  __IM  uint32_t GICD_TYPER;                 /*!< Offset: 0x0004 (R/ )  Interrupt Controller Type Register */
+  __IM  uint32_t GICD_IIDR;                  /*!< Offset: 0x0008 (R/ )  Distributor Implementer Identification Register */
+        uint32_t RESERVED0[30U];
+  __IOM uint32_t GICD_IGROUPR[30U];          /*!< Offset: 0x0084 (R/W)  Interrupt Group Registers 1 - 30 */
+        uint32_t RESERVED1[2U];
+  __IOM uint32_t GICD_ISENABLER[30U];        /*!< Offset: 0x0104 (R/W)  Interrupt Set-Enable Registers 1 - 30 */
+        uint32_t RESERVED2[2U];
+  __IOM uint32_t GICD_ICENABLER[30U];        /*!< Offset: 0x0184 (R/W)  Interrupt Clear-Enable Registers 1 - 30 */
+        uint32_t RESERVED3[2U];
+  __IOM uint32_t GICD_ISPENDR[30U];          /*!< Offset: 0x0204 (R/W)  Interrupt Set-Pending Registers 1 - 30 */
+        uint32_t RESERVED4[2U];
+  __IOM uint32_t GICD_ICPENDR[30U];          /*!< Offset: 0x0284 (R/W)  Interrupt Clear-Pending Registers 1 - 30 */
+        uint32_t RESERVED5[2U];
+  __IOM uint32_t GICD_ISACTIVER[30U];        /*!< Offset: 0x0304 (R/W)  Interrupt Set-Active Registers 1 - 30 */
+        uint32_t RESERVED6[2U];
+  __IOM uint32_t GICD_ICACTIVER[30U];        /*!< Offset: 0x0384 (R/W)  Interrupt Clear-Active Registers 1 - 30 */
+        uint32_t RESERVED7[9U];
+  __IOM uint32_t GICD_IPRIORITYR[240U];      /*!< Offset: 0x0420 (R/W)  Interrupt Priority Registers 8 - 247 */
+        uint32_t RESERVED8[266U];
+  __IOM uint32_t GICD_ICFGR[60U];            /*!< Offset: 0x0C08 (R/W)  Interrupt Configuration Registers 2 - 61 */
+}  GICD_Type;
+
+ /**
+  \brief  Structure type to access the Generic Interrupt Controller (GIC) for GICR for Control target.
+ */
+typedef struct
+{
+  __IM  uint32_t GICR_CTLR;                  /*!< Offset: 0x0000 (R/ )  Redistributor Control Register */
+  __IM  uint32_t GICR_IIDR;                  /*!< Offset: 0x0004 (R/ )  Redistributor Implementer Identification Register */
+  __IM  uint32_t GICR_TYPER[2];              /*!< Offset: 0x0008 (R/ )  Redistributor Type Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t GICR_WAKER;                 /*!< Offset: 0x0014 (R/W)  Redistributor Wake Register */
+}  GICR_CONTROL_TARGET_Type;
+
+ /**
+  \brief  Structure type to access the Generic Interrupt Controller (GIC) for GICR for SGI and PPI.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[32];
+  __IOM uint32_t GICR_IGROUPR0;              /*!< Offset: 0x0080 (R/W)  Interrupt Group Register 0 */
+        uint32_t RESERVED1[31];
+  __IOM uint32_t GICR_ISENABLER0;            /*!< Offset: 0x0100 (R/W)  Interrupt Set-Enable Register 0 */
+        uint32_t RESERVED2[31];
+  __IOM uint32_t GICR_ICENABLER0;            /*!< Offset: 0x0180 (R/W)  Interrupt Clear-Enable Register 0 */
+        uint32_t RESERVED3[31];
+  __IOM uint32_t GICR_ISPENDR0;              /*!< Offset: 0x0200 (R/W)  Interrupt Set-Pending Register 0 */
+        uint32_t RESERVED4[31];
+  __IOM uint32_t GICR_ICPENDR0;              /*!< Offset: 0x0280 (R/W)  Interrupt Clear-Pending Register 0 */
+        uint32_t RESERVED5[31];
+  __IOM uint32_t GICR_ISACTIVER0;            /*!< Offset: 0x0300 (R/W)  Interrupt Set-Active Register 0 */
+        uint32_t RESERVED6[31];
+  __IOM uint32_t GICR_ICACTIVER0;            /*!< Offset: 0x0380 (R/W)  Interrupt Clear-Active Register 0 */
+        uint32_t RESERVED7[31];
+  __IOM uint32_t GICR_IPRIORITYR[8];         /*!< Offset: 0x0400 (R/W)  Interrupt Priority Registers 0 - 7 */
+        uint32_t RESERVED8[504];
+  __IM  uint32_t GICR_ICFGR0;                /*!< Offset: 0x0C00 (R/ )  Interrupt Configuration Register 0 */
+  __IOM uint32_t GICR_ICFGR1;                /*!< Offset: 0x0C04 (R/W)  Interrupt Configuration Register 1 */
+}  GICR_SGI_PPI_Type;
+
+/*@} end of group CMSIS_GIC */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define GIC0_BASE                     (0x94000000UL)              /*!< GIC0 Base Address */
+#define GIC1_BASE                     (0x9C000000UL)              /*!< GIC1 Base Address */
+#define GICR_TARGET0_BASE             (0x00100000UL)              /*!< GICR Base Address (for Control target 0) */
+#define GICR_TARGET0_SGI_PPI_BASE     (0x00110000UL)              /*!< GICR Base Address (for SGI and PPI target 0) */
+
+#define GICD0                         ((GICD_Type *) GIC0_BASE )   /*!< GICD configuration struct */
+#define GICD1                         ((GICD_Type *) GIC1_BASE )   /*!< GICD configuration struct */
+#define GICR0_TARGET0_IFREG           ((GICR_CONTROL_TARGET_Type *) (GIC0_BASE + GICR_TARGET0_BASE) )    /*!< GICR configuration struct for Control target 0 */
+#define GICR1_TARGET0_IFREG           ((GICR_CONTROL_TARGET_Type *) (GIC1_BASE + GICR_TARGET0_BASE) )    /*!< GICR configuration struct for Control target 0 */
+#define GICR0_TARGET0_INTREG          ((GICR_SGI_PPI_Type *) (GIC0_BASE + GICR_TARGET0_SGI_PPI_BASE) )   /*!< GICR configuration struct for SGI and PPI target 0 */
+#define GICR1_TARGET0_INTREG          ((GICR_SGI_PPI_Type *) (GIC1_BASE + GICR_TARGET0_SGI_PPI_BASE) )   /*!< GICR configuration struct for SGI and PPI target 0 */
+
+/*@} */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  Get CPSR Register
+
+    This function returns the content of the CPSR Register.
+
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+
+
+#include <intrinsics.h>
+
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __CORE_CR52_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/LICENSE.txt b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/LICENSE.txt
new file mode 100644
index 00000000..8dada3ed
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/arm/CMSIS_5/LICENSE.txt
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
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+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
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+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
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+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
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+      Work and such Derivative Works in Source or Object form.
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+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
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+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
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+   5. Submission of Contributions. Unless You explicitly state otherwise,
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+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
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diff --git a/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board.h b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board.h
new file mode 100644
index 00000000..4e82a47e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board.h
@@ -0,0 +1,59 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * File Name    : board.h
+ * Description  : Includes and API function available for this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARDS
+ * @defgroup BOARD_RZN2L_RSK
+ * @brief BSP for the RZN2L_RSK Board
+ *
+ * The RZN2L_RSK is a development kit for the Renesas RZN2L microcontroller.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP Board Specific Includes. */
+#include "board_init.h"
+#include "board_leds.h"
+#include "board_ethernet_phy.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BOARD_RZN2L_RSK
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BSP_CONFIG_RZN2L) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_ethernet_phy.h b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_ethernet_phy.h
new file mode 100644
index 00000000..26d27a6e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_ethernet_phy.h
@@ -0,0 +1,46 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_RZN2_RSK
+ * @defgroup BOARD_RZN2_RSK_ETHERNET_PHY Board Ethernet Phy
+ * @brief Ethernet Phy information for this board.
+ *
+ * This is code specific to the RZN2_RSK board.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BSP_ETHERNET_PHY_H
+#define BSP_ETHERNET_PHY_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define ETHER_PHY_CFG_TARGET_VSC8541_ENABLE    (1)
+#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT       ETHER_PHY_LSI_TYPE_VSC8541
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Public Functions
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/** @} (end defgroup BOARD_RZN2_RSK_ETHERNET_PHY) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_init.c b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_init.c
new file mode 100644
index 00000000..00e6c7c8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_init.c
@@ -0,0 +1,53 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * File Name    : board_init.c
+ * Description  : This module calls any initialization code specific to this BSP.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BOARD_RZN2L_RSK_INIT
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+#if defined(BOARD_RZN2L_RSK)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief      Performs any initialization specific to this BSP.
+ *
+ * @param[in]  p_args         Pointer to arguments of the user's choice.
+ **********************************************************************************************************************/
+void bsp_init (void * p_args)
+{
+    FSP_PARAMETER_NOT_USED(p_args);
+}
+
+#endif
+
+/** @} (end addtogroup BOARD_RZN2L_RSK_INIT) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_init.h b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_init.h
new file mode 100644
index 00000000..c1cf0474
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_init.h
@@ -0,0 +1,50 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * File Name    : board_init.h
+ * Description  : This module calls any initialization code specific to this BSP.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_RZN2L_RSK
+ * @defgroup BOARD_RZN2L_RSK_INIT
+ * @brief Board specific code for the RZN2L_RSK Board
+ *
+ * This include file is specific to the RZN2L_RSK board.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_INIT_H
+#define BOARD_INIT_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+void bsp_init(void * p_args);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/** @} (end defgroup BOARD_RZN2L_RSK_INIT) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_leds.c b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_leds.c
new file mode 100644
index 00000000..4721954c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_leds.c
@@ -0,0 +1,63 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * File Name    : board_leds.c
+ * Description  : This module has information about the LEDs on this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BOARD_RZN2L_RSK_LEDS
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#if defined(BOARD_RZN2L_RSK)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/** Array of LED IOPORT pins. */
+static const uint32_t g_bsp_prv_leds[][2] =
+{
+    {(uint32_t) BSP_IO_PORT_18_PIN_2, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED0
+    {(uint32_t) BSP_IO_PORT_22_PIN_3, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED1
+    {(uint32_t) BSP_IO_PORT_04_PIN_1, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED2
+    {(uint32_t) BSP_IO_PORT_17_PIN_3, (uint32_t) BSP_IO_REGION_SAFE}  ///< RLED3
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Structure with LED information for this board. */
+
+const bsp_leds_t g_bsp_leds =
+{
+    .led_count = (uint16_t) (sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0])),
+    .p_leds    = g_bsp_prv_leds
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+#endif
+
+/** @} (end addtogroup BOARD_RZN2L_RSK_LEDS) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_leds.h b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_leds.h
new file mode 100644
index 00000000..62a31db9
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/board/rzn2l_rsk/board_leds.h
@@ -0,0 +1,72 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * File Name    : board_leds.h
+ * Description  : This module has information about the LEDs on this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_RZN2L_RSK
+ * @defgroup BOARD_RZN2L_RSK_LEDS Board LEDs
+ * @brief LED information for this board.
+ *
+ * This is code specific to the RZN2L_RSK board. It includes info on the number of LEDs and which pins are they
+ * are on.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_LEDS_H
+#define BOARD_LEDS_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Information on how many LEDs and what pins they are on. */
+typedef struct st_bsp_leds
+{
+    uint16_t led_count;                ///< The number of LEDs on this board
+    uint32_t const (*p_leds)[2];       ///< Pointer to an array of IOPORT pins for controlling LEDs
+} bsp_leds_t;
+
+/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
+ * found in the bsp_leds_t structure. */
+typedef enum e_bsp_led
+{
+#if defined(BSP_CFG_CORE_CR52)
+ #if (0 == BSP_CFG_CORE_CR52)
+    BSP_LED_RLED0 = 0,                 ///< Green
+    BSP_LED_RLED1 = 1,                 ///< Yellow
+ #elif (1 == BSP_CFG_CORE_CR52)
+    BSP_LED_RLED2 = 2,                 ///< Red
+    BSP_LED_RLED3 = 3,                 ///< Red
+ #endif
+#endif
+} bsp_led_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Public Functions
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/** @} (end defgroup BOARD_RZN2L_RSK_LEDS) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/bsp_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/bsp_api.h
new file mode 100644
index 00000000..e0e39b50
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/bsp_api.h
@@ -0,0 +1,97 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_API_H
+#define BSP_API_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* FSP Common Includes. */
+#include "fsp_common_api.h"
+
+/* Gets MCU configuration information. */
+#include "bsp_cfg.h"
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+
+/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
+ #pragma GCC diagnostic push
+
+/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
+ * We are not modifying these files so we will ignore these warnings temporarily. */
+ #pragma GCC diagnostic ignored "-Wconversion"
+ #pragma GCC diagnostic ignored "-Wsign-conversion"
+#endif
+
+/* Vector information for this project. This is generated by the tooling. */
+#include "../../src/bsp/mcu/all/bsp_exceptions.h"
+#include "vector_data.h"
+
+/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
+#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
+#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+
+/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
+ #pragma GCC diagnostic pop
+#endif
+
+#if defined(BSP_API_OVERRIDE)
+ #include BSP_API_OVERRIDE
+#else
+
+/* BSP Common Includes. */
+ #include "../../src/bsp/mcu/all/bsp_common.h"
+
+/* BSP MCU Specific Includes. */
+ #include "../../src/bsp/mcu/all/bsp_register_protection.h"
+ #include "../../src/bsp/mcu/all/bsp_irq.h"
+ #include "../../src/bsp/mcu/all/bsp_io.h"
+ #include "../../src/bsp/mcu/all/bsp_group_irq.h"
+ #include "../../src/bsp/mcu/all/bsp_clocks.h"
+ #include "../../src/bsp/mcu/all/bsp_module_stop.h"
+ #include "../../src/bsp/mcu/all/bsp_security.h"
+
+/* Factory MCU information. */
+ #include "../../inc/fsp_features.h"
+
+/* BSP Common Includes (Other than bsp_common.h) */
+ #include "../../src/bsp/mcu/all/bsp_delay.h"
+ #include "../../src/bsp/mcu/all/bsp_mcu_api.h"
+
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
+
+/** @} (end addtogroup BSP_MCU) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_api.h
new file mode 100644
index 00000000..2294edfa
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_api.h
@@ -0,0 +1,245 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_NETWORKING_INTERFACES
+ * @defgroup ETHER_API Ethernet Interface
+ * @brief Interface for Ethernet functions.
+ *
+ * @section ETHER_API_Summary Summary
+ * The Ethernet interface provides Ethernet functionality.
+ * The Ethernet interface supports the following features:
+ * - Transmit/receive processing (Blocking and Non-Blocking)
+ * - Callback function with returned event code
+ * - Magic packet detection mode support
+ * - Auto negotiation support
+ * - Flow control support
+ * - Multicast filtering support
+ *
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ETHER_API_H
+#define R_ETHER_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+#include "r_ether_phy_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Wake on LAN */
+typedef enum e_ether_wake_on_lan
+{
+    ETHER_WAKE_ON_LAN_DISABLE = 0,     ///< Disable Wake on LAN
+    ETHER_WAKE_ON_LAN_ENABLE  = 1,     ///< Enable Wake on LAN
+} ether_wake_on_lan_t;
+
+/** Flow control functionality  */
+typedef enum e_ether_flow_control
+{
+    ETHER_FLOW_CONTROL_DISABLE = 0,    ///< Disable flow control functionality
+    ETHER_FLOW_CONTROL_ENABLE  = 1,    ///< Enable flow control functionality with pause frames
+} ether_flow_control_t;
+
+/** Multicast Filter */
+typedef enum e_ether_multicast
+{
+    ETHER_MULTICAST_DISABLE = 0,       ///< Disable reception of multicast frames
+    ETHER_MULTICAST_ENABLE  = 1,       ///< Enable reception of multicast frames
+} ether_multicast_t;
+
+/** Promiscuous Mode */
+typedef enum e_ether_promiscuous
+{
+    ETHER_PROMISCUOUS_DISABLE = 0,     ///< Only receive packets with current MAC address, multicast, and broadcast
+    ETHER_PROMISCUOUS_ENABLE  = 1,     ///< Receive all packets
+} ether_promiscuous_t;
+
+/** Zero copy */
+typedef enum e_ether_zerocopy
+{
+    ETHER_ZEROCOPY_DISABLE = 0,        ///< Disable zero copy in Read/Write function
+    ETHER_ZEROCOPY_ENABLE  = 1,        ///< Enable zero copy in Read/Write function
+} ether_zerocopy_t;
+
+typedef enum e_ether_padding
+{
+    ETHER_PADDING_DISABLE = 0,
+    ETHER_PADDING_1BYTE   = 1,
+    ETHER_PADDING_2BYTE   = 2,
+    ETHER_PADDING_3BYTE   = 3,
+} ether_padding_t;
+
+#ifndef BSP_OVERRIDE_ETHER_EVENT_T
+
+/** Event code of callback function */
+typedef enum e_ether_event
+{
+    ETHER_EVENT_WAKEON_LAN,            ///< Magic packet detection event
+    ETHER_EVENT_LINK_ON,               ///< Link up detection event
+    ETHER_EVENT_LINK_OFF,              ///< Link down detection event
+    ETHER_EVENT_INTERRUPT,             ///< Interrupt event
+} ether_event_t;
+#endif
+
+#ifndef BSP_OVERRIDE_ETHER_CALLBACK_ARGS_T
+
+/** Callback function parameter data */
+typedef struct st_ether_callback_args
+{
+    uint32_t      channel;             ///< Device channel number
+    ether_event_t event;               ///< Event code
+    uint32_t      status_ecsr;         ///< ETHERC status register for interrupt handler
+    uint32_t      status_eesr;         ///< ETHERC/EDMAC status register for interrupt handler
+
+    void const * p_context;            ///< Placeholder for user data.  Set in @ref ether_api_t::open function in @ref ether_cfg_t.
+} ether_callback_args_t;
+#endif
+
+/** Control block.  Allocate an instance specific control block to pass into the API calls.
+ */
+typedef void ether_ctrl_t;
+
+/** Configuration parameters. */
+typedef struct st_ether_cfg
+{
+    uint8_t              channel;                        ///< Channel
+    ether_zerocopy_t     zerocopy;                       ///< Zero copy enable or disable in Read/Write function
+    ether_multicast_t    multicast;                      ///< Multicast enable or disable
+    ether_promiscuous_t  promiscuous;                    ///< Promiscuous mode enable or disable
+    ether_flow_control_t flow_control;                   ///< Flow control functionally enable or disable
+    ether_padding_t      padding;                        ///< Padding length inserted into the received Ethernet frame.
+    uint32_t             padding_offset;                 ///< Offset of the padding inserted into the received Ethernet frame.
+    uint32_t             broadcast_filter;               ///< Limit of the number of broadcast frames received continuously
+    uint8_t            * p_mac_address;                  ///< Pointer of MAC address
+
+    uint8_t num_tx_descriptors;                          ///< Number of transmission descriptor
+    uint8_t num_rx_descriptors;                          ///< Number of receive descriptor
+
+    uint8_t ** pp_ether_buffers;                         ///< Transmit and receive buffer
+
+    uint32_t ether_buffer_size;                          ///< Size of transmit and receive buffer
+
+    IRQn_Type irq;                                       ///< Interrupt number
+    uint32_t  interrupt_priority;                        ///< Interrupt priority
+
+    void (* p_callback)(ether_callback_args_t * p_args); ///< Callback provided when an ISR occurs.
+
+    ether_phy_instance_t const * p_ether_phy_instance;   ///< Pointer to ETHER_PHY instance
+
+    /** Placeholder for user data.  Passed to the user callback in ether_callback_args_t. */
+    void const * p_context;                              ///< Placeholder for user data.
+    void const * p_extend;                               ///< Placeholder for user extension.
+} ether_cfg_t;
+
+/** Functions implemented at the HAL layer will follow this API. */
+typedef struct st_ether_api
+{
+    /** Open driver.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to pin configuration structure.
+     */
+    fsp_err_t (* open)(ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p_cfg);
+
+    /** Close driver.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* close)(ether_ctrl_t * const p_ctrl);
+
+    /** Read packet if data is available.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_buffer     Pointer to where to store read data.
+     * @param[in]  length_bytes Number of bytes in buffer
+     */
+    fsp_err_t (* read)(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t * const length_bytes);
+
+    /** Release rx buffer from buffer pool process in zero-copy read operation.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* bufferRelease)(ether_ctrl_t * const p_ctrl);
+
+    /** Update the buffer pointer in the current receive descriptor.
+     *
+     * @param[in]  p_ctrl           Pointer to control structure.
+     * @param[in]  p_buffer         New address to write into the rx buffer descriptor.
+     */
+    fsp_err_t (* rxBufferUpdate)(ether_ctrl_t * const p_ctrl, void * const p_buffer);
+
+    /** Write packet.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_buffer     Pointer to data to write.
+     * @param[in]  frame_length Send ethernet frame size (without 4 bytes of CRC data size).
+     */
+    fsp_err_t (* write)(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length);
+
+    /** Process link.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* linkProcess)(ether_ctrl_t * const p_ctrl);
+
+    /** Enable magic packet detection.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* wakeOnLANEnable)(ether_ctrl_t * const p_ctrl);
+
+    /** Get the address of the most recently sent buffer.
+     *
+     * @param[in]   p_ctrl             Pointer to control structure.
+     * @param[out]  p_buffer_address   Pointer to the address of the most recently sent buffer.
+     */
+    fsp_err_t (* txStatusGet)(ether_ctrl_t * const p_ctrl, void * const p_buffer_address);
+
+    /**
+     * Specify callback function and optional context pointer and working memory pointer.
+     *
+     * @param[in]   p_ctrl                   Pointer to the ETHER control block.
+     * @param[in]   p_callback               Callback function
+     * @param[in]   p_context                Pointer to send to callback function
+     * @param[in]   p_working_memory         Pointer to volatile memory where callback structure can be allocated.
+     *                                       Callback arguments allocated here are only valid during the callback.
+     */
+    fsp_err_t (* callbackSet)(ether_ctrl_t * const p_ctrl, void (* p_callback)(ether_callback_args_t *),
+                              void const * const p_context, ether_callback_args_t * const p_callback_memory);
+} ether_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_ether_instance
+{
+    ether_ctrl_t      * p_ctrl;        ///< Pointer to the control structure for this instance
+    ether_cfg_t const * p_cfg;         ///< Pointer to the configuration structure for this instance
+    ether_api_t const * p_api;         ///< Pointer to the API structure for this instance
+} ether_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup ETHER_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 /* R_ETHERNET_API_H */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_phy_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_phy_api.h
new file mode 100644
index 00000000..84abde14
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_phy_api.h
@@ -0,0 +1,187 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_NETWORKING_INTERFACES
+ * @defgroup ETHER_PHY_API Ethernet PHY Interface
+ * @brief Interface for Ethernet PHY functions.
+ *
+ * @section ETHER_PHY_API_Summary Summary
+ * The Ethernet PHY module (r_ether_phy) provides an API for standard Ethernet PHY communications applications that use
+ * the ETHERC peripheral.
+ *
+ * The Ethernet PHY interface supports the following features:
+ * - Auto negotiation support
+ * - Flow control support
+ * - Link status check support
+ *
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ETHER_PHY_API_H
+#define R_ETHER_PHY_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+#ifndef BSP_OVERRIDE_ETHER_PHY_LSI_TYPE_T
+
+/** Phy LSI */
+typedef enum e_ether_phy_lsi_type
+{
+    ETHER_PHY_LSI_TYPE_DEFAULT    = 0,     ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option.
+    ETHER_PHY_LSI_TYPE_KSZ8091RNB = 1,     ///< Select configuration for KSZ8091RNB.
+    ETHER_PHY_LSI_TYPE_KSZ8041    = 2,     ///< Select configuration for KSZ8041.
+    ETHER_PHY_LSI_TYPE_DP83620    = 3,     ///< Select configuration for DP83620.
+    ETHER_PHY_LSI_TYPE_ICS1894    = 4,     ///< Select configuration for ICS1894.
+    ETHER_PHY_LSI_TYPE_CUSTOM     = 0xFFU, ///< Select configuration for User custom.
+} ether_phy_lsi_type_t;
+#endif
+
+/** Flow control functionality  */
+typedef enum e_ether_phy_flow_control
+{
+    ETHER_PHY_FLOW_CONTROL_DISABLE = 0, ///< Disable flow control functionality
+    ETHER_PHY_FLOW_CONTROL_ENABLE  = 1, ///< Enable flow control functionality with pause frames
+} ether_phy_flow_control_t;
+
+/** Link speed  */
+typedef enum e_ether_phy_link_speed
+{
+    ETHER_PHY_LINK_SPEED_NO_LINK = 0,  ///< Link is not established
+    ETHER_PHY_LINK_SPEED_10H     = 1,  ///< Link status is 10Mbit/s and half duplex
+    ETHER_PHY_LINK_SPEED_10F     = 2,  ///< Link status is 10Mbit/s and full duplex
+    ETHER_PHY_LINK_SPEED_100H    = 3,  ///< Link status is 100Mbit/s and half duplex
+    ETHER_PHY_LINK_SPEED_100F    = 4,  ///< Link status is 100Mbit/s and full duplex
+    ETHER_PHY_LINK_SPEED_1000H   = 5,  ///< Link status is 1000Mbit/s and half duplex
+    ETHER_PHY_LINK_SPEED_1000F   = 6   ///< Link status is 1000Mbit/s and full duplex
+} ether_phy_link_speed_t;
+
+/** Media-independent interface */
+typedef enum e_ether_phy_mii_type
+{
+    ETHER_PHY_MII_TYPE_MII   = 0,      ///< MII
+    ETHER_PHY_MII_TYPE_RMII  = 1,      ///< RMII
+    ETHER_PHY_MII_TYPE_GMII  = 2,      ///< GMII
+    ETHER_PHY_MII_TYPE_RGMII = 3       ///< RGMII
+} ether_phy_mii_type_t;
+
+/** Control block.  Allocate an instance specific control block to pass into the API calls.
+ */
+typedef void ether_phy_ctrl_t;
+
+/** Configuration parameters. */
+typedef struct st_ether_phy_cfg
+{
+    uint8_t channel;                               ///< Channel
+    uint8_t phy_lsi_address;                       ///< Address of PHY-LSI
+
+    uint32_t             phy_reset_wait_time;      ///< Wait time for PHY-LSI reboot
+    int32_t              mii_bit_access_wait_time; ///< Wait time for MII/RMII access
+    ether_phy_lsi_type_t phy_lsi_type;             ///< Phy LSI type
+
+    ether_phy_flow_control_t flow_control;         ///< Flow control functionally enable or disable
+    ether_phy_mii_type_t     mii_type;             ///< Interface type is MII or RMII
+
+    /** Placeholder for user data.  Passed to the user callback in ether_phy_callback_args_t. */
+    void const * p_context;
+    void const * p_extend;                         ///< Placeholder for user extension.
+} ether_phy_cfg_t;
+
+/** Functions implemented at the HAL layer will follow this API. */
+typedef struct st_ether_phy_api
+{
+    /** Open driver.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to pin configuration structure.
+     */
+    fsp_err_t (* open)(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg);
+
+    /** Close driver.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* close)(ether_phy_ctrl_t * const p_ctrl);
+
+    /** Initialize PHY-LSI.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to pin configuration structure.
+     */
+    fsp_err_t (* chipInit)(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg);
+
+    /** Read register value of PHY-LSI.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  reg_addr     Register address.
+     * @param[out] p_data       Pointer to the location to store read data.
+     */
+    fsp_err_t (* read)(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data);
+
+    /** Write data to register of PHY-LSI.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  reg_addr     Register address.
+     * @param[in]  data         Data written to register.
+     */
+    fsp_err_t (* write)(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data);
+
+    /** Start auto negotiation.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* startAutoNegotiate)(ether_phy_ctrl_t * const p_ctrl);
+
+    /** Get the partner ability.
+     *
+     * @param[in]  p_ctrl                     Pointer to control structure.
+     * @param[out] p_line_speed_duplex        Pointer to the location of both the line speed and the duplex.
+     * @param[out] p_local_pause              Pointer to the location to store the local pause bits.
+     * @param[out] p_partner_pause            Pointer to the location to store the partner pause bits.
+     */
+    fsp_err_t (* linkPartnerAbilityGet)(ether_phy_ctrl_t * const p_ctrl, uint32_t * const p_line_speed_duplex,
+                                        uint32_t * const p_local_pause, uint32_t * const p_partner_pause);
+
+    /** Get Link status from PHY-LSI interface.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* linkStatusGet)(ether_phy_ctrl_t * const p_ctrl);
+} ether_phy_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_ether_phy_instance
+{
+    ether_phy_ctrl_t      * p_ctrl;    ///< Pointer to the control structure for this instance
+    ether_phy_cfg_t const * p_cfg;     ///< Pointer to the configuration structure for this instance
+    ether_phy_api_t const * p_api;     ///< Pointer to the API structure for this instance
+} ether_phy_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup ETHER_PHY_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 /* R_ETHER_PHY_API_H */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_selector_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_selector_api.h
new file mode 100644
index 00000000..de97783a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_selector_api.h
@@ -0,0 +1,141 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_NETWORKING_INTERFACES
+ * @defgroup ETHER_SELECTOR_API Ethernet Selector Interface
+ * @brief Interface for Ethernet Selector functions.
+ *
+ * @section ETHER_SELECTOR_API_Summary Summary
+ * The Ethernet Selector module (r_ether_selector) provides an API for standard Ethernet Selector communications applications that use
+ * the Ethernet Subsystem peripheral.
+ *
+ * The Ethernet Selector interface supports the following features:
+ * - Ethernet port select support
+ * - Selector control support
+ * - PHY link signal polarity control support
+ *
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ETHER_SELECTOR_API_H
+#define R_ETHER_SELECTOR_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** PHY link signal polarity */
+typedef enum e_ether_selector_phylink_polarity
+{
+    ETHER_SELECTOR_PHYLINK_POLARITY_LOW  = 0, ///< Active-Low link signal
+    ETHER_SELECTOR_PHYLINK_POLARITY_HIGH = 1, ///< Active-High link signal
+} ether_selector_phylink_polarity_t;
+
+/** Selector mode */
+typedef enum e_ether_selector_interface
+{
+    ETHER_SELECTOR_INTERFACE_MII   = 0, ///< MII
+    ETHER_SELECTOR_INTERFACE_RMII  = 1, ///< RMII
+    ETHER_SELECTOR_INTERFACE_GMII  = 2, ///< GMII
+    ETHER_SELECTOR_INTERFACE_RGMII = 3, ///< RGMII
+} ether_selector_interface_t;
+
+/** Selector speed */
+typedef enum e_ether_selector_speed
+{
+    ETHER_SELECTOR_SPEED_10_MBPS   = 0, ///< 10Mbit/s
+    ETHER_SELECTOR_SPEED_100_MBPS  = 1, ///< 100Mbit/s
+    ETHER_SELECTOR_SPEED_1000_MBPS = 2, ///< 1000Mbit/s
+} ether_selector_speed_t;
+
+/** Selector duplex */
+typedef enum e_ether_selector_duplex
+{
+    ETHER_SELECTOR_DUPLEX_HALF = 0,    ///< Half-Duplex
+    ETHER_SELECTOR_DUPLEX_FULL = 1,    ///< Full-Duplex
+} ether_selector_duplex_t;
+
+/** Selector reference clock */
+typedef enum e_ether_selector_ref_clock
+{
+    ETHER_SELECTOR_REF_CLOCK_INPUT  = 0, ///< REF_CLK input
+    ETHER_SELECTOR_REF_CLOCK_OUTPUT = 1, ///< REF_CLK output
+} ether_selector_ref_clock_t;
+
+/** Control block.  Allocate an instance specific control block to pass into the API calls. */
+typedef void ether_selector_ctrl_t;
+
+/** Configuration parameters. */
+typedef struct st_ether_selector_cfg
+{
+    uint8_t channel;                           ///< Channel number
+    ether_selector_phylink_polarity_t phylink; ///< PHY link signal polarity
+
+    ether_selector_interface_t interface;      ///< Interface mode
+    ether_selector_speed_t     speed;          ///< Interface speed
+    ether_selector_duplex_t    duplex;         ///< Interface duplex
+    ether_selector_ref_clock_t ref_clock;      ///< Interface REF_CLK
+    void const               * p_extend;       ///< Placeholder for user extension.
+} ether_selector_cfg_t;
+
+/** Functions implemented at the HAL layer will follow this API. */
+typedef struct st_ether_selector_api
+{
+    /** Open driver. Set Ethernet mode such as Ethernet MAC or Ethernet Switch or EtherCAT for each port.
+     *
+     * @param[in]  p_api_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg            Pointer to selector configuration structure.
+     */
+    fsp_err_t (* open)(ether_selector_ctrl_t * const p_api_ctrl, ether_selector_cfg_t const * const p_cfg);
+
+    /** Close driver.
+     *
+     * @param[in]  p_api_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* close)(ether_selector_ctrl_t * const p_api_ctrl);
+
+    /** Set the Converter speed and duplex in runtime.
+     *
+     * @param[in]  p_api_ctrl       Pointer to control structure.
+     * @param[in]  speed            Converter speed.
+     * @param[in]  duplex           Converter duplex mode.
+     */
+    fsp_err_t (* converterSet)(ether_selector_ctrl_t * const p_api_ctrl, ether_selector_speed_t speed,
+                               ether_selector_duplex_t duplex);
+} ether_selector_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_ether_selector_instance
+{
+    ether_selector_ctrl_t      * p_ctrl; ///< Pointer to the control structure for this instance
+    ether_selector_cfg_t const * p_cfg;  ///< Pointer to the configuration structure for this instance
+    ether_selector_api_t const * p_api;  ///< Pointer to the API structure for this instance
+} ether_selector_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ETHER_SELECTOR_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 /* R_ETHER_SELECTOR_API_H */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_switch_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_switch_api.h
new file mode 100644
index 00000000..ba120a83
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ether_switch_api.h
@@ -0,0 +1,102 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_NETWORKING_INTERFACES
+ * @defgroup ETHER_SWITCH_API Ethernet Switch Interface
+ * @brief Interface for Ethernet Switch functions.
+ *
+ * @section ETHER_SWITCH_API_Summary Summary
+ * The Ether Switch module provides an API for ethernet switch peripheral.
+ * And the general ethernet switch peripheral have forwarding functionality.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ETHER_SWITCH_API_H
+#define R_ETHER_SWITCH_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+#ifndef BSP_OVERRIDE_ETHER_SWITCH_CALLBACK_ARGS_T
+
+/** Callback function parameter data */
+typedef struct st_ether_switch_callback_args
+{
+    uint32_t channel;                  ///< Device channel number
+
+    void const * p_context;            ///< Placeholder for user data.  Set in @ref ether_switch_api_t::open function in @ref ether_switch_cfg_t.
+} ether_switch_callback_args_t;
+#endif
+
+/** Control block.  Allocate an instance specific control block to pass into the API calls.
+ */
+typedef void ether_switch_ctrl_t;
+
+/** Configuration parameters. */
+typedef struct st_ether_switch_cfg
+{
+    uint8_t channel;                                            ///< Channel
+
+    IRQn_Type irq;                                              ///< MCU interrupt number
+    uint8_t   ipl;                                              ///< MCU interrupt priority
+
+    void (* p_callback)(ether_switch_callback_args_t * p_args); ///< Callback provided when an ISR occurs.
+
+    /** Placeholder for user data.  Passed to the user callback in ether_switch_callback_args_t. */
+    void const * p_context;
+    void const * p_extend;                                      ///< Placeholder for user extension.
+} ether_switch_cfg_t;
+
+/** Functions implemented at the HAL layer will follow this API. */
+typedef struct st_ether_switch_api
+{
+    /** Open driver.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to pin configuration structure.
+     */
+    fsp_err_t (* open)(ether_switch_ctrl_t * const p_ctrl, ether_switch_cfg_t const * const p_cfg);
+
+    /** Close driver.
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* close)(ether_switch_ctrl_t * const p_ctrl);
+} ether_switch_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_ether_switch_instance
+{
+    ether_switch_ctrl_t      * p_ctrl; ///< Pointer to the control structure for this instance
+    ether_switch_cfg_t const * p_cfg;  ///< Pointer to the configuration structure for this instance
+    ether_switch_api_t const * p_api;  ///< Pointer to the API structure for this instance
+} ether_switch_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup ETHER_SWITCH_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 /* R_ETHER_SWITCH_API_H */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ioport_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ioport_api.h
new file mode 100644
index 00000000..dcb104b0
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_ioport_api.h
@@ -0,0 +1,192 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_SYSTEM_INTERFACES
+ * @defgroup IOPORT_API I/O Port Interface
+ * @brief Interface  for accessing I/O ports and configuring I/O functionality.
+ *
+ * @section IOPORT_API_SUMMARY Summary
+ * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
+ * Port and pin direction can be changed.
+ *
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_IOPORT_API_H
+#define R_IOPORT_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Common error codes and definitions. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+#ifndef BSP_OVERRIDE_IOPORT_SIZE_T
+
+/** IO port type used with ports */
+typedef uint16_t ioport_size_t;        ///< IO port size
+#endif
+
+/** Pin identifier and pin configuration value */
+typedef struct st_ioport_pin_cfg
+{
+    uint32_t          pin_cfg;         ///< Pin configuration - Use ioport_cfg_options_t parameters to configure
+    bsp_io_port_pin_t pin;             ///< Pin identifier
+} ioport_pin_cfg_t;
+
+/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */
+typedef struct st_ioport_cfg
+{
+    uint16_t                 number_of_pins; ///< Number of pins for which there is configuration data
+    ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
+    const void             * p_extend;       ///< Pointer to hardware extend configuration
+} ioport_cfg_t;
+
+/** IOPORT control block.  Allocate an instance specific control block to pass into the IOPORT API calls.
+ */
+typedef void ioport_ctrl_t;
+
+/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
+typedef struct st_ioport_api
+{
+    /** Initialize internal driver data and initial pin configurations.  Called during startup.  Do
+     * not call this API during runtime.  Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
+     * multiple pins.
+     *
+     * @param[in]      p_ctrl     Pointer to control structure. Must be declared by user. Elements set here.
+     * @param[in]      p_cfg      Pointer to pin configuration data array.
+     */
+    fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
+
+    /** Close the API.
+     *
+     * @param[in]   p_ctrl  Pointer to control structure.
+     **/
+    fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
+
+    /** Configure multiple pins.
+     *
+     * @param[in]  p_ctrl     Pointer to control structure.
+     * @param[in]  p_cfg      Pointer to pin configuration data array.
+     */
+    fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
+
+    /** Configure settings for an individual pin.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  pin                  Pin to be read.
+     * @param[in]  cfg                  Configuration options for the pin.
+     */
+    fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
+
+    /** Read the event input data of the specified pin and return the level.
+     *
+     * @param[in]  p_ctrl              Pointer to control structure.
+     * @param[in]  pin                 Pin to be read.
+     * @param[in]  p_pin_event         Pointer to return the event data.
+     */
+    fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
+
+    /** Write pin event data.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  pin                  Pin event data is to be written to.
+     * @param[in]  pin_value            Level to be written to pin output event.
+     */
+    fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
+
+    /** Read level of a pin.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  pin                  Pin to be read.
+     * @param[in]  p_pin_value          Pointer to return the pin level.
+     */
+    fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
+
+    /** Write specified level to a pin.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  pin                  Pin to be written to.
+     * @param[in]  level                State to be written to the pin.
+     */
+    fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
+
+    /** Set the direction of one or more pins on a port.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  port                 Port being configured.
+     * @param[in]  direction_values     Value controlling direction of pins on port.
+     * @param[in]  mask                 Mask controlling which pins on the port are to be configured.
+     */
+    fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
+                                   ioport_size_t mask);
+
+    /** Read captured event data for a port.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  port                 Port to be read.
+     * @param[in]  p_event_data         Pointer to return the event data.
+     */
+    fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
+
+    /** Write event output data for a port.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  port                 Port event data will be written to.
+     * @param[in]  event_data           Data to be written as event data to specified port.
+     * @param[in]  mask_value           Each bit set to 1 in the mask corresponds to that bit's value in event data.
+     * being written to port.
+     */
+    fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
+                                       ioport_size_t mask_value);
+
+    /** Read states of pins on the specified port.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  port                 Port to be read.
+     * @param[in]  p_port_value         Pointer to return the port value.
+     */
+    fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
+
+    /** Write to multiple pins on a port.
+     *
+     * @param[in]  p_ctrl               Pointer to control structure.
+     * @param[in]  port                 Port to be written to.
+     * @param[in]  value                Value to be written to the port.
+     * @param[in]  mask                 Mask controlling which pins on the port are written to.
+     */
+    fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
+} ioport_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_ioport_instance
+{
+    ioport_ctrl_t      * p_ctrl;       ///< Pointer to the control structure for this instance
+    ioport_cfg_t const * p_cfg;        ///< Pointer to the configuration structure for this instance
+    ioport_api_t const * p_api;        ///< Pointer to the API structure for this instance
+} ioport_instance_t;
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup IOPORT_API)
+ **********************************************************************************************************************/
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_timer_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_timer_api.h
new file mode 100644
index 00000000..b972f63e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_timer_api.h
@@ -0,0 +1,291 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef R_TIMER_API_H
+#define R_TIMER_API_H
+
+/*******************************************************************************************************************//**
+ * @defgroup TIMER_API Timer Interface
+ * @ingroup RENESAS_TIMERS_INTERFACES
+ * @brief Interface for timer functions.
+ *
+ * @section TIMER_API_SUMMARY Summary
+ * The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output,
+ * and free-running timer mode.  After each timer cycle (overflow or underflow), an interrupt can be triggered.
+ *
+ * If an instance supports output compare mode, it is provided in the extension configuration
+ * timer_on_<instance>_cfg_t defined in r_<instance>.h.
+ *
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+#ifndef BSP_OVERRIDE_TIMER_EVENT_T
+
+/** Events that can trigger a callback function */
+typedef enum e_timer_event
+{
+    TIMER_EVENT_CYCLE_END,                     ///< Requested timer delay has expired or timer has wrapped around
+    TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only)
+    TIMER_EVENT_CAPTURE_A,                     ///< A capture has occurred on signal A
+    TIMER_EVENT_CAPTURE_B,                     ///< A capture has occurred on signal B
+    TIMER_EVENT_TROUGH,                        ///< Timer trough event (counter is 0, triangle-wave PWM only
+    TIMER_EVENT_COMPARE_A,                     ///< A compare has occurred on signal A
+    TIMER_EVENT_COMPARE_B,                     ///< A compare has occurred on signal B
+    TIMER_EVENT_COMPARE_C,                     ///< A compare has occurred on signal C
+    TIMER_EVENT_COMPARE_D,                     ///< A compare has occurred on signal D
+    TIMER_EVENT_COMPARE_E,                     ///< A compare has occurred on signal E
+    TIMER_EVENT_COMPARE_F,                     ///< A compare has occurred on signal F
+    TIMER_EVENT_DEAD_TIME                      ///< Dead time event
+} timer_event_t;
+#endif
+
+/** Timer variant types. */
+typedef enum e_timer_variant
+{
+    TIMER_VARIANT_32_BIT,              ///< 32-bit timer
+    TIMER_VARIANT_16_BIT               ///< 16-bit timer
+} timer_variant_t;
+
+/** Callback function parameter data */
+typedef struct st_timer_callback_args
+{
+    /** Placeholder for user data.  Set in @ref timer_api_t::open function in @ref timer_cfg_t. */
+    void const  * p_context;
+    timer_event_t event;               ///< The event can be used to identify what caused the callback.
+
+    /** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */
+    uint32_t capture;
+} timer_callback_args_t;
+
+/** Timer control block.  Allocate an instance specific control block to pass into the timer API calls.
+ */
+typedef void timer_ctrl_t;
+
+/** Possible status values returned by @ref timer_api_t::statusGet. */
+typedef enum e_timer_state
+{
+    TIMER_STATE_STOPPED  = 0,          ///< Timer is stopped
+    TIMER_STATE_COUNTING = 1           ///< Timer is running
+} timer_state_t;
+#ifndef BSP_OVERRIDE_TIMER_MODE_T
+
+/** Timer operational modes */
+typedef enum e_timer_mode
+{
+    TIMER_MODE_PERIODIC,                          ///< Timer restarts after period elapses.
+    TIMER_MODE_ONE_SHOT,                          ///< Timer stops after period elapses.
+    TIMER_MODE_PWM,                               ///< Timer generates saw-wave PWM output.
+    TIMER_MODE_ONE_SHOT_PULSE,                    ///< Saw-wave one-shot pulse mode (fixed buffer operation).
+    TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM  = 4U, ///< Timer generates symmetric triangle-wave PWM output.
+    TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output.
+
+    /**
+     * Timer generates Asymmetric Triangle-wave PWM output. In PWM mode 3, the duty cycle does
+     * not need to be updated at each tough/crest interrupt. Instead, the trough and crest duty cycle values can be
+     * set once and only need to be updated when the application needs to change the duty cycle.
+     */
+    TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 = 6U
+} timer_mode_t;
+
+#endif
+
+/** Direction of timer count */
+typedef enum e_timer_direction
+{
+    TIMER_DIRECTION_DOWN = 0,          ///< Timer count goes up
+    TIMER_DIRECTION_UP   = 1           ///< Timer count goes down
+} timer_direction_t;
+
+#ifndef BSP_OVERRIDE_TIMER_SOURCE_DIV_T
+
+/** Clock source divisors */
+typedef enum e_timer_source_div
+{
+    TIMER_SOURCE_DIV_1    = 0,         ///< Timer clock source divided by 1
+    TIMER_SOURCE_DIV_2    = 1,         ///< Timer clock source divided by 2
+    TIMER_SOURCE_DIV_4    = 2,         ///< Timer clock source divided by 4
+    TIMER_SOURCE_DIV_8    = 3,         ///< Timer clock source divided by 8
+    TIMER_SOURCE_DIV_16   = 4,         ///< Timer clock source divided by 16
+    TIMER_SOURCE_DIV_32   = 5,         ///< Timer clock source divided by 32
+    TIMER_SOURCE_DIV_64   = 6,         ///< Timer clock source divided by 64
+    TIMER_SOURCE_DIV_128  = 7,         ///< Timer clock source divided by 128
+    TIMER_SOURCE_DIV_256  = 8,         ///< Timer clock source divided by 256
+    TIMER_SOURCE_DIV_512  = 9,         ///< Timer clock source divided by 512
+    TIMER_SOURCE_DIV_1024 = 10,        ///< Timer clock source divided by 1024
+} timer_source_div_t;
+#endif
+
+/** Timer information structure to store various information for a timer resource */
+typedef struct st_timer_info
+{
+    timer_direction_t count_direction; ///< Clock counting direction of the timer.
+    uint32_t          clock_frequency; ///< Clock frequency of the timer counter.
+
+    /** Period in raw timer counts.
+     * @note For triangle wave PWM modes, the full period is double this value.
+     */
+    uint32_t period_counts;
+} timer_info_t;
+
+/** Current timer status. */
+typedef struct st_timer_status
+{
+    uint32_t      counter;             ///< Current counter value
+    timer_state_t state;               ///< Current timer state (running or stopped)
+} timer_status_t;
+
+/** User configuration structure, used in open function */
+typedef struct st_timer_cfg
+{
+    timer_mode_t mode;                    ///< Select enumerated value from @ref timer_mode_t
+
+    /* Period in raw timer counts.
+     * @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period.
+     */
+    uint32_t           period_counts;     ///< Period in raw timer counts
+    timer_source_div_t source_div;        ///< Source clock divider
+    uint32_t           duty_cycle_counts; ///< Duty cycle in counts
+
+    /** Select a channel corresponding to the channel number of the hardware. */
+    uint8_t   channel;
+    uint8_t   cycle_end_ipl;              ///< Cycle end interrupt priority
+    IRQn_Type cycle_end_irq;              ///< Cycle end interrupt
+
+    /** Callback provided when a timer ISR occurs.  Set to NULL for no CPU interrupt. */
+    void (* p_callback)(timer_callback_args_t * p_args);
+
+    /** Placeholder for user data.  Passed to the user callback in @ref timer_callback_args_t. */
+    void const * p_context;
+    void const * p_extend;             ///< Extension parameter for hardware specific settings.
+} timer_cfg_t;
+
+/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */
+typedef struct st_timer_api
+{
+    /** Initial configuration.
+     *
+     * @param[in]   p_ctrl     Pointer to control block. Must be declared by user. Elements set here.
+     * @param[in]   p_cfg      Pointer to configuration structure. All elements of this structure must be set by user.
+     */
+    fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
+
+    /** Start the counter.
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* start)(timer_ctrl_t * const p_ctrl);
+
+    /** Stop the counter.
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl);
+
+    /** Reset the counter to the initial value.
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl);
+
+    /** Enables input capture.
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl);
+
+    /** Disables input capture.
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl);
+
+    /** Set the time until the timer expires.  See implementation for details of period update timing.
+     *
+     *
+     * @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in
+     * @ref timer_api_t::open.
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     * @param[in]   period     Time until timer should expire.
+     */
+    fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period);
+
+    /** Sets the number of counts for the pin level to be high.  If the timer is counting, the updated duty cycle is
+     * reflected after the next timer expiration.
+     *
+     *
+     * @param[in]   p_ctrl             Control block set in @ref timer_api_t::open call for this timer.
+     * @param[in]   duty_cycle_counts  Time until duty cycle should expire.
+     * @param[in]   pin                Which output pin to update.  See implementation for details.
+     */
+    fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
+
+    /** Stores timer information in p_info.
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     * @param[out]  p_info     Collection of information for this timer.
+     */
+    fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
+
+    /** Get the current counter value and timer state and store it in p_status.
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     * @param[out]  p_status   Current status of this timer.
+     */
+    fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
+
+    /** Specify callback function and optional context pointer and working memory pointer.
+     *
+     * @param[in]   p_ctrl                   Control block set in @ref timer_api_t::open call for this timer.
+     * @param[in]   p_callback               Callback function to register
+     * @param[in]   p_context                Pointer to send to callback function
+     * @param[in]   p_working_memory         Pointer to volatile memory where callback structure can be allocated.
+     *                                       Callback arguments allocated here are only valid during the callback.
+     */
+    fsp_err_t (* callbackSet)(timer_ctrl_t * const p_ctrl, void (* p_callback)(timer_callback_args_t *),
+                              void const * const p_context, timer_callback_args_t * const p_callback_memory);
+
+    /** Allows driver to be reconfigured and may reduce power consumption.
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* close)(timer_ctrl_t * const p_ctrl);
+} timer_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_timer_instance
+{
+    timer_ctrl_t      * p_ctrl;        ///< Pointer to the control structure for this instance
+    timer_cfg_t const * p_cfg;         ///< Pointer to the configuration structure for this instance
+    timer_api_t const * p_api;         ///< Pointer to the API structure for this instance
+} timer_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup TIMER_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_transfer_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_transfer_api.h
new file mode 100644
index 00000000..841e6929
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_transfer_api.h
@@ -0,0 +1,388 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_TRANSFER_INTERFACES
+ * @defgroup TRANSFER_API Transfer Interface
+ *
+ * @brief Interface for data transfer functions.
+ *
+ * @section TRANSFER_API_SUMMARY Summary
+ * The transfer interface supports background data transfer (no CPU intervention).
+ *
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_TRANSFER_API_H
+#define R_TRANSFER_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Common error codes and definitions. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+#define TRANSFER_SETTINGS_MODE_BITS           (30U)
+#define TRANSFER_SETTINGS_SIZE_BITS           (28U)
+#define TRANSFER_SETTINGS_SRC_ADDR_BITS       (26U)
+#define TRANSFER_SETTINGS_CHAIN_MODE_BITS     (22U)
+#define TRANSFER_SETTINGS_IRQ_BITS            (21U)
+#define TRANSFER_SETTINGS_REPEAT_AREA_BITS    (20U)
+#define TRANSFER_SETTINGS_DEST_ADDR_BITS      (18U)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Transfer control block.  Allocate an instance specific control block to pass into the transfer API calls.
+ */
+typedef void transfer_ctrl_t;
+
+#ifndef BSP_OVERRIDE_TRANSFER_MODE_T
+
+/** Transfer mode describes what will happen when a transfer request occurs. */
+typedef enum e_transfer_mode
+{
+    /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
+     *  the destination pointer.  The transfer length is decremented and the source and address pointers are
+     *  updated according to @ref transfer_addr_mode_t.  After the transfer length reaches 0, transfer requests
+     *  will not cause any further transfers. */
+    TRANSFER_MODE_NORMAL = 0,
+
+    /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
+     *  repeat area and the transfer length will be reset to their initial values.  If DMAC is used, the
+     *  transfer repeats only transfer_info_t::num_blocks times.  After the transfer repeats
+     *  transfer_info_t::num_blocks times, transfer requests will not cause any further transfers.  If DTC is
+     *  used, the transfer repeats continuously (no limit to the number of repeat transfers). */
+    TRANSFER_MODE_REPEAT = 1,
+
+    /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
+     *  After each individual transfer, the source and destination pointers are updated according to
+     *  @ref transfer_addr_mode_t.  After the block transfer is complete, transfer_info_t::num_blocks is
+     *  decremented.  After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
+     *  further transfers. */
+    TRANSFER_MODE_BLOCK = 2,
+
+    /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets
+     *  within a block (to split blocks into arrays of their first data, second data, etc.) */
+    TRANSFER_MODE_REPEAT_BLOCK = 3
+} transfer_mode_t;
+
+#endif
+
+#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T
+
+/** Transfer size specifies the size of each individual transfer.
+ *  Total transfer length = transfer_size_t * transfer_length_t
+ */
+typedef enum e_transfer_size
+{
+    TRANSFER_SIZE_1_BYTE = 0,          ///< Each transfer transfers a 8-bit value
+    TRANSFER_SIZE_2_BYTE = 1,          ///< Each transfer transfers a 16-bit value
+    TRANSFER_SIZE_4_BYTE = 2           ///< Each transfer transfers a 32-bit value
+} transfer_size_t;
+
+#endif
+
+#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T
+
+/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
+typedef enum e_transfer_addr_mode
+{
+    /** Address pointer remains fixed after each transfer. */
+    TRANSFER_ADDR_MODE_FIXED = 0,
+
+    /** Offset is added to the address pointer after each transfer. */
+    TRANSFER_ADDR_MODE_OFFSET = 1,
+
+    /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
+    TRANSFER_ADDR_MODE_INCREMENTED = 2,
+
+    /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
+    TRANSFER_ADDR_MODE_DECREMENTED = 3
+} transfer_addr_mode_t;
+
+#endif
+
+#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T
+
+/** Repeat area options (source or destination).  In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
+ *  original value after transfer_info_t::length transfers.  In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK,
+ *  the selected pointer returns to its original value after each transfer. */
+typedef enum e_transfer_repeat_area
+{
+    /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
+    TRANSFER_REPEAT_AREA_DESTINATION = 0,
+
+    /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
+    TRANSFER_REPEAT_AREA_SOURCE = 1
+} transfer_repeat_area_t;
+
+#endif
+
+#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T
+
+/** Chain transfer mode options.
+ *  @note Only applies for DTC. */
+typedef enum e_transfer_chain_mode
+{
+    /** Chain mode not used. */
+    TRANSFER_CHAIN_MODE_DISABLED = 0,
+
+    /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
+    TRANSFER_CHAIN_MODE_EACH = 2,
+
+    /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
+    TRANSFER_CHAIN_MODE_END = 3
+} transfer_chain_mode_t;
+
+#endif
+
+#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T
+
+/** Interrupt options. */
+typedef enum e_transfer_irq
+{
+    /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
+     *  the interrupt will occur only after subsequent chained transfer(s) are complete.
+     *  @warning  DTC triggers the interrupt of the activation source.  Choosing TRANSFER_IRQ_END with DTC will
+     *            prevent activation source interrupts until the transfer is complete. */
+    TRANSFER_IRQ_END = 0,
+
+    /** Interrupt occurs after each transfer.
+     *  @note     Not available in all HAL drivers.  See HAL driver for details. */
+    TRANSFER_IRQ_EACH = 1
+} transfer_irq_t;
+
+#endif
+
+#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T
+
+/** Callback function parameter data. */
+typedef struct st_transfer_callback_args_t
+{
+    void const * p_context;            ///< Placeholder for user data.  Set in @ref transfer_api_t::open function in ::transfer_cfg_t.
+} transfer_callback_args_t;
+
+#endif
+
+/** Driver specific information. */
+typedef struct st_transfer_properties
+{
+    uint32_t block_count_max;           ///< Maximum number of blocks
+    uint32_t block_count_remaining;     ///< Number of blocks remaining
+    uint32_t transfer_length_max;       ///< Maximum number of transfers
+    uint32_t transfer_length_remaining; ///< Number of transfers remaining
+} transfer_properties_t;
+
+#ifndef BSP_OVERRIDE_TRANSFER_INFO_T
+
+/** This structure specifies the properties of the transfer.
+ *  @warning  When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
+ *            The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
+ *  @warning  When using DTC, do NOT reuse this structure to configure multiple transfers.  Each transfer must
+ *            have a unique transfer_info_t.
+ *  @warning  When using DTC, this structure must not be allocated in a temporary location.  Any instance of this
+ *            structure must remain in scope until the transfer it is used for is closed.
+ *  @note     When using DTC, consider placing instances of this structure in a protected section of memory. */
+typedef struct st_transfer_info
+{
+    union
+    {
+        struct
+        {
+            uint32_t : 16;
+            uint32_t : 2;
+
+            /** Select what happens to destination pointer after each transfer. */
+            transfer_addr_mode_t dest_addr_mode : 2;
+
+            /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
+            transfer_repeat_area_t repeat_area : 1;
+
+            /** Select if interrupts should occur after each individual transfer or after the completion of all planned
+             *  transfers. */
+            transfer_irq_t irq : 1;
+
+            /** Select when the chain transfer ends. */
+            transfer_chain_mode_t chain_mode : 2;
+
+            uint32_t : 2;
+
+            /** Select what happens to source pointer after each transfer. */
+            transfer_addr_mode_t src_addr_mode : 2;
+
+            /** Select number of bytes to transfer at once. @see transfer_info_t::length. */
+            transfer_size_t size : 2;
+
+            /** Select mode from @ref transfer_mode_t. */
+            transfer_mode_t mode : 2;
+        } transfer_settings_word_b;
+
+        uint32_t transfer_settings_word;
+    };
+
+    void const * volatile p_src;       ///< Source pointer
+    void * volatile       p_dest;      ///< Destination pointer
+
+    /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or
+     * @ref TRANSFER_MODE_REPEAT (DMAC only) or
+     * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */
+    volatile uint16_t num_blocks;
+
+    /** Length of each transfer.  Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT,
+     *  and @ref TRANSFER_MODE_REPEAT_BLOCK
+     *  see HAL driver for details. */
+    volatile uint16_t length;
+} transfer_info_t;
+
+#endif
+
+/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
+ *  initialized. */
+typedef struct st_transfer_cfg
+{
+    /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
+     *  an array of chained transfers that will be completed in order. */
+    transfer_info_t * p_info;
+
+    void const * p_extend;             ///< Extension parameter for hardware specific settings.
+} transfer_cfg_t;
+
+/** Select whether to start single or repeated transfer with software start. */
+typedef enum e_transfer_start_mode
+{
+    TRANSFER_START_MODE_SINGLE = 0,    ///< Software start triggers single transfer.
+    TRANSFER_START_MODE_REPEAT = 1     ///< Software start transfer continues until transfer is complete.
+} transfer_start_mode_t;
+
+/** Transfer functions implemented at the HAL layer will follow this API. */
+typedef struct st_transfer_api
+{
+    /** Initial configuration.
+     *
+     * @param[in,out] p_ctrl   Pointer to control block. Must be declared by user. Elements set here.
+     * @param[in]     p_cfg    Pointer to configuration structure. All elements of this structure
+     *                                               must be set by user.
+     */
+    fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
+
+    /** Reconfigure the transfer.
+     * Enable the transfer if p_info is valid.
+     *
+     * @param[in,out] p_ctrl   Pointer to control block. Must be declared by user. Elements set here.
+     * @param[in]     p_info   Pointer to a new transfer info structure.
+     */
+    fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
+
+    /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
+     * Enable the transfer if p_src, p_dest, and length are valid.
+     *
+     * @param[in]     p_ctrl         Control block set in @ref transfer_api_t::open call for this transfer.
+     * @param[in]     p_src          Pointer to source. Set to NULL if source pointer should not change.
+     * @param[in]     p_dest         Pointer to destination. Set to NULL if destination pointer should not change.
+     * @param[in]     num_transfers  Transfer length in normal mode or number of blocks in block mode.  In DMAC only,
+     *                               resets number of repeats (initially stored in transfer_info_t::num_blocks) in
+     *                               repeat mode.  Not used in repeat mode for DTC.
+     */
+    fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
+                        uint16_t const num_transfers);
+
+    /** Enable transfer. Transfers occur after the activation source event (or when
+     * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source).
+     *
+     * @param[in]     p_ctrl   Control block set in @ref transfer_api_t::open call for this transfer.
+     */
+    fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
+
+    /** Disable transfer. Transfers do not occur after the activation source event (or when
+     * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source).
+     * @note If a transfer is in progress, it will be completed.  Subsequent transfer requests do not cause a
+     * transfer.
+     *
+     * @param[in]     p_ctrl   Control block set in @ref transfer_api_t::open call for this transfer.
+     */
+    fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
+
+    /** Start transfer in software.
+     * @warning Only works if no peripheral event is chosen as the DMAC activation source.
+     * @note Not supported for DTC.
+     *
+     * @param[in]     p_ctrl   Control block set in @ref transfer_api_t::open call for this transfer.
+     * @param[in]     mode     Select mode from @ref transfer_start_mode_t.
+     */
+    fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
+
+    /** Stop transfer in software. The transfer will stop after completion of the current transfer.
+     * @note Not supported for DTC.
+     * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
+     * @warning Only works if no peripheral event is chosen as the DMAC activation source.
+     *
+     * @param[in]     p_ctrl   Control block set in @ref transfer_api_t::open call for this transfer.
+     */
+    fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
+
+    /** Provides information about this transfer.
+     *
+     * @param[in]     p_ctrl         Control block set in @ref transfer_api_t::open call for this transfer.
+     * @param[out]    p_properties   Driver specific information.
+     */
+    fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
+
+    /** Releases hardware lock.  This allows a transfer to be reconfigured using @ref transfer_api_t::open.
+     *
+     * @param[in]     p_ctrl    Control block set in @ref transfer_api_t::open call for this transfer.
+     */
+    fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
+
+    /** To update next transfer information without interruption during transfer.
+     *  Allow further transfer continuation.
+     *
+     * @param[in]     p_ctrl         Control block set in @ref transfer_api_t::open call for this transfer.
+     * @param[in]     p_src          Pointer to source. Set to NULL if source pointer should not change.
+     * @param[in]     p_dest         Pointer to destination. Set to NULL if destination pointer should not change.
+     * @param[in]     num_transfers  Transfer length in normal mode or block mode.
+     */
+    fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
+                         uint32_t const num_transfers);
+
+    /** Specify callback function and optional context pointer and working memory pointer.
+     *
+     * @param[in]   p_ctrl                   Control block set in @ref transfer_api_t::open call for this transfer.
+     * @param[in]   p_callback               Callback function to register
+     * @param[in]   p_context                Pointer to send to callback function
+     * @param[in]   p_callback_memory        Pointer to volatile memory where callback structure can be allocated.
+     *                                       Callback arguments allocated here are only valid during the callback.
+     */
+    fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *),
+                              void const * const p_context, transfer_callback_args_t * const p_callback_memory);
+} transfer_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_transfer_instance
+{
+    transfer_ctrl_t      * p_ctrl;     ///< Pointer to the control structure for this instance
+    transfer_cfg_t const * p_cfg;      ///< Pointer to the configuration structure for this instance
+    transfer_api_t const * p_api;      ///< Pointer to the API structure for this instance
+} transfer_instance_t;
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup TRANSFER_API)
+ **********************************************************************************************************************/
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_uart_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_uart_api.h
new file mode 100644
index 00000000..e9f81a92
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/api/r_uart_api.h
@@ -0,0 +1,254 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_CONNECTIVITY_INTERFACES
+ * @defgroup UART_API UART Interface
+ * @brief Interface for UART communications.
+ *
+ * @section UART_INTERFACE_SUMMARY Summary
+ * The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
+ * - Full-duplex UART communication
+ * - Interrupt driven transmit/receive processing
+ * - Callback function with returned event code
+ * - Runtime baud-rate change
+ * - Hardware resource locking during a transaction
+ * - CTS/RTS hardware flow control support (with an associated IOPORT pin)
+ *
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_UART_API_H
+#define R_UART_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+#include "r_transfer_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** UART Event codes */
+#ifndef BSP_OVERRIDE_UART_EVENT_T
+typedef enum e_sf_event
+{
+    UART_EVENT_RX_COMPLETE   = (1UL << 0), ///< Receive complete event
+    UART_EVENT_TX_COMPLETE   = (1UL << 1), ///< Transmit complete event
+    UART_EVENT_RX_CHAR       = (1UL << 2), ///< Character received
+    UART_EVENT_ERR_PARITY    = (1UL << 3), ///< Parity error event
+    UART_EVENT_ERR_FRAMING   = (1UL << 4), ///< Mode fault error event
+    UART_EVENT_ERR_OVERFLOW  = (1UL << 5), ///< FIFO Overflow error event
+    UART_EVENT_BREAK_DETECT  = (1UL << 6), ///< Break detect error event
+    UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data
+} uart_event_t;
+#endif
+#ifndef BSP_OVERRIDE_UART_DATA_BITS_T
+
+/** UART Data bit length definition */
+typedef enum e_uart_data_bits
+{
+    UART_DATA_BITS_9 = 0U,             ///< Data bits 9-bit
+    UART_DATA_BITS_8 = 2U,             ///< Data bits 8-bit
+    UART_DATA_BITS_7 = 3U,             ///< Data bits 7-bit
+} uart_data_bits_t;
+#endif
+#ifndef BSP_OVERRIDE_UART_PARITY_T
+
+/** UART Parity definition */
+typedef enum e_uart_parity
+{
+    UART_PARITY_OFF  = 0U,             ///< No parity
+    UART_PARITY_ZERO = 1U,             ///< Zero parity
+    UART_PARITY_EVEN = 2U,             ///< Even parity
+    UART_PARITY_ODD  = 3U,             ///< Odd parity
+} uart_parity_t;
+#endif
+
+/** UART Stop bits definition */
+typedef enum e_uart_stop_bits
+{
+    UART_STOP_BITS_1 = 0U,             ///< Stop bit 1-bit
+    UART_STOP_BITS_2 = 1U,             ///< Stop bits 2-bit
+} uart_stop_bits_t;
+
+/** UART transaction definition */
+typedef enum e_uart_dir
+{
+    UART_DIR_RX_TX = 3U,               ///< Both RX and TX
+    UART_DIR_RX    = 1U,               ///< Only RX
+    UART_DIR_TX    = 2U,               ///< Only TX
+} uart_dir_t;
+
+/** UART driver specific information */
+typedef struct st_uart_info
+{
+    /** Maximum bytes that can be written at this time.  Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
+    uint32_t write_bytes_max;
+
+    /** Maximum bytes that are available to read at one time.  Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
+    uint32_t read_bytes_max;
+} uart_info_t;
+
+/** UART Callback parameter definition */
+typedef struct st_uart_callback_arg
+{
+    uint32_t     channel;              ///< Device channel number
+    uart_event_t event;                ///< Event code
+
+    /** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
+     * UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW.  Otherwise unused. */
+    uint32_t     data;
+    void const * p_context;            ///< Context provided to user during callback
+} uart_callback_args_t;
+
+/** UART Configuration */
+typedef struct st_uart_cfg
+{
+    /* UART generic configuration */
+    uint8_t          channel;          ///< Select a channel corresponding to the channel number of the hardware.
+    uart_data_bits_t data_bits;        ///< Data bit length (8 or 7 or 9)
+    uart_parity_t    parity;           ///< Parity type (none or odd or even)
+    uart_stop_bits_t stop_bits;        ///< Stop bit length (1 or 2)
+    uint8_t          rxi_ipl;          ///< Receive interrupt priority
+    IRQn_Type        rxi_irq;          ///< Receive interrupt IRQ number
+    uint8_t          txi_ipl;          ///< Transmit interrupt priority
+    IRQn_Type        txi_irq;          ///< Transmit interrupt IRQ number
+    uint8_t          tei_ipl;          ///< Transmit end interrupt priority
+    IRQn_Type        tei_irq;          ///< Transmit end interrupt IRQ number
+    uint8_t          eri_ipl;          ///< Error interrupt priority
+    IRQn_Type        eri_irq;          ///< Error interrupt IRQ number
+
+    /** Optional transfer instance used to receive multiple bytes without interrupts.  Set to NULL if unused.
+     * If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
+    transfer_instance_t const * p_transfer_rx;
+
+    /** Optional transfer instance used to send multiple bytes without interrupts.  Set to NULL if unused.
+     * If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
+    transfer_instance_t const * p_transfer_tx;
+
+    /* Configuration for UART Event processing */
+    void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function
+    void const * p_context;                             ///< User defined context passed into callback function
+
+    /* Pointer to UART peripheral specific configuration */
+    void const * p_extend;                              ///< UART hardware dependent configuration
+} uart_cfg_t;
+
+/** UART control block.  Allocate an instance specific control block to pass into the UART API calls.
+ */
+typedef void uart_ctrl_t;
+
+/** Shared Interface definition for UART */
+typedef struct st_uart_api
+{
+    /** Open  UART device.
+     *
+     * @param[in,out]  p_ctrl     Pointer to the UART control block. Must be declared by user. Value set here.
+     * @param[in]      uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
+     *                            user.
+     */
+    fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
+
+    /** Read from UART device.  The read buffer is used until the read is complete.  When a transfer is complete, the
+     * callback is called with event UART_EVENT_RX_COMPLETE.  Bytes received outside an active transfer are received in
+     * the callback function with event UART_EVENT_RX_CHAR.
+     * The maximum transfer size is reported by infoGet().
+     *
+     * @param[in]   p_ctrl     Pointer to the UART control block for the channel.
+     * @param[in]   p_dest     Destination address to read data from.
+     * @param[in]   bytes      Read data length.
+     */
+    fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
+
+    /** Write to UART device.  The write buffer is used until write is complete.  Do not overwrite write buffer
+     * contents until the write is finished.  When the write is complete (all bytes are fully transmitted on the wire),
+     * the callback called with event UART_EVENT_TX_COMPLETE.
+     * The maximum transfer size is reported by infoGet().
+     *
+     * @param[in]   p_ctrl     Pointer to the UART control block.
+     * @param[in]   p_src      Source address  to write data to.
+     * @param[in]   bytes      Write data length.
+     */
+    fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
+
+    /** Change baud rate.
+     * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
+     * settings have been applied.
+     *
+     *
+     * @param[in]   p_ctrl          Pointer to the UART control block.
+     * @param[in]   p_baudrate_info Pointer to module specific information for configuring baud rate.
+     */
+    fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
+
+    /** Get the driver specific information.
+     *
+     * @param[in]   p_ctrl     Pointer to the UART control block.
+     * @param[in]   baudrate   Baud rate in bps.
+     */
+    fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
+
+    /**
+     * Abort ongoing transfer.
+     *
+     * @param[in]   p_ctrl                   Pointer to the UART control block.
+     * @param[in]   communication_to_abort   Type of abort request.
+     */
+    fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
+
+    /**
+     * Specify callback function and optional context pointer and working memory pointer.
+     *
+     * @param[in]   p_ctrl                   Pointer to the UART control block.
+     * @param[in]   p_callback               Callback function
+     * @param[in]   p_context                Pointer to send to callback function
+     * @param[in]   p_working_memory         Pointer to volatile memory where callback structure can be allocated.
+     *                                       Callback arguments allocated here are only valid during the callback.
+     */
+    fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *),
+                              void const * const p_context, uart_callback_args_t * const p_callback_memory);
+
+    /** Close UART device.
+     *
+     * @param[in]   p_ctrl     Pointer to the UART control block.
+     */
+    fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
+
+    /** Stop ongoing read and return the number of bytes remaining in the read.
+     *
+     * @param[in]      p_ctrl                Pointer to the UART control block.
+     * @param[in,out]  remaining_bytes       Pointer to location to store remaining bytes for read.
+     */
+    fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
+} uart_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_uart_instance
+{
+    uart_ctrl_t      * p_ctrl;         ///< Pointer to the control structure for this instance
+    uart_cfg_t const * p_cfg;          ///< Pointer to the configuration structure for this instance
+    uart_api_t const * p_api;          ///< Pointer to the API structure for this instance
+} uart_instance_t;
+
+/** @} (end defgroup UART_API) */
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_common_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_common_api.h
new file mode 100644
index 00000000..194336c3
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_common_api.h
@@ -0,0 +1,380 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef FSP_COMMON_API_H
+#define FSP_COMMON_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include <assert.h>
+#include <stdint.h>
+
+/* Includes FSP version macros. */
+#include "fsp_version.h"
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_COMMON
+ * @defgroup RENESAS_ERROR_CODES Common Error Codes
+ * All FSP modules share these common error codes.
+ * @{
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
+ * about using this implementation is that it does not take any extra RAM or ROM. */
+
+#define FSP_PARAMETER_NOT_USED(p)    (void) ((p))
+
+/** Determine if a C++ compiler is being used.
+ * If so, ensure that standard C is used to process the API information.  */
+#if defined(__cplusplus)
+ #define FSP_CPP_HEADER    extern "C" {
+ #define FSP_CPP_FOOTER    }
+#else
+ #define FSP_CPP_HEADER
+ #define FSP_CPP_FOOTER
+#endif
+
+/** FSP Header and Footer definitions */
+#define FSP_HEADER    FSP_CPP_HEADER
+#define FSP_FOOTER    FSP_CPP_FOOTER
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
+ *  defined on the Secure side. */
+#define FSP_SECURE_ARGUMENT    (NULL)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Common error codes */
+typedef enum e_fsp_err
+{
+    FSP_SUCCESS = 0,
+
+    FSP_ERR_ASSERTION             = 1,                      ///< A critical assertion has failed
+    FSP_ERR_INVALID_POINTER       = 2,                      ///< Pointer points to invalid memory location
+    FSP_ERR_INVALID_ARGUMENT      = 3,                      ///< Invalid input parameter
+    FSP_ERR_INVALID_CHANNEL       = 4,                      ///< Selected channel does not exist
+    FSP_ERR_INVALID_MODE          = 5,                      ///< Unsupported or incorrect mode
+    FSP_ERR_UNSUPPORTED           = 6,                      ///< Selected mode not supported by this API
+    FSP_ERR_NOT_OPEN              = 7,                      ///< Requested channel is not configured or API not open
+    FSP_ERR_IN_USE                = 8,                      ///< Channel/peripheral is running/busy
+    FSP_ERR_OUT_OF_MEMORY         = 9,                      ///< Allocate more memory in the driver's cfg.h
+    FSP_ERR_HW_LOCKED             = 10,                     ///< Hardware is locked
+    FSP_ERR_IRQ_BSP_DISABLED      = 11,                     ///< IRQ not enabled in BSP
+    FSP_ERR_OVERFLOW              = 12,                     ///< Hardware overflow
+    FSP_ERR_UNDERFLOW             = 13,                     ///< Hardware underflow
+    FSP_ERR_ALREADY_OPEN          = 14,                     ///< Requested channel is already open in a different configuration
+    FSP_ERR_APPROXIMATION         = 15,                     ///< Could not set value to exact result
+    FSP_ERR_CLAMPED               = 16,                     ///< Value had to be limited for some reason
+    FSP_ERR_INVALID_RATE          = 17,                     ///< Selected rate could not be met
+    FSP_ERR_ABORTED               = 18,                     ///< An operation was aborted
+    FSP_ERR_NOT_ENABLED           = 19,                     ///< Requested operation is not enabled
+    FSP_ERR_TIMEOUT               = 20,                     ///< Timeout error
+    FSP_ERR_INVALID_BLOCKS        = 21,                     ///< Invalid number of blocks supplied
+    FSP_ERR_INVALID_ADDRESS       = 22,                     ///< Invalid address supplied
+    FSP_ERR_INVALID_SIZE          = 23,                     ///< Invalid size/length supplied for operation
+    FSP_ERR_WRITE_FAILED          = 24,                     ///< Write operation failed
+    FSP_ERR_ERASE_FAILED          = 25,                     ///< Erase operation failed
+    FSP_ERR_INVALID_CALL          = 26,                     ///< Invalid function call is made
+    FSP_ERR_INVALID_HW_CONDITION  = 27,                     ///< Detected hardware is in invalid condition
+    FSP_ERR_INVALID_FACTORY_FLASH = 28,                     ///< Factory flash is not available on this MCU
+    FSP_ERR_INVALID_STATE         = 30,                     ///< API or command not valid in the current state
+    FSP_ERR_NOT_ERASED            = 31,                     ///< Erase verification failed
+    FSP_ERR_SECTOR_RELEASE_FAILED = 32,                     ///< Sector release failed
+    FSP_ERR_NOT_INITIALIZED       = 33,                     ///< Required initialization not complete
+    FSP_ERR_NOT_FOUND             = 34,                     ///< The requested item could not be found
+    FSP_ERR_NO_CALLBACK_MEMORY    = 35,                     ///< Non-secure callback memory not provided for non-secure callback
+    FSP_ERR_BUFFER_EMPTY          = 36,                     ///< No data available in buffer
+    FSP_ERR_INVALID_DATA          = 37,                     ///< Accuracy of data is not guaranteed
+
+    /* Start of RTOS only error codes */
+    FSP_ERR_INTERNAL     = 100,                             ///< Internal error
+    FSP_ERR_WAIT_ABORTED = 101,                             ///< Wait aborted
+
+    /* Start of UART specific */
+    FSP_ERR_FRAMING            = 200,                       ///< Framing error occurs
+    FSP_ERR_BREAK_DETECT       = 201,                       ///< Break signal detects
+    FSP_ERR_PARITY             = 202,                       ///< Parity error occurs
+    FSP_ERR_RXBUF_OVERFLOW     = 203,                       ///< Receive queue overflow
+    FSP_ERR_QUEUE_UNAVAILABLE  = 204,                       ///< Can't open s/w queue
+    FSP_ERR_INSUFFICIENT_SPACE = 205,                       ///< Not enough space in transmission circular buffer
+    FSP_ERR_INSUFFICIENT_DATA  = 206,                       ///< Not enough data in receive circular buffer
+
+    /* Start of SPI specific */
+    FSP_ERR_TRANSFER_ABORTED = 300,                         ///< The data transfer was aborted.
+    FSP_ERR_MODE_FAULT       = 301,                         ///< Mode fault error.
+    FSP_ERR_READ_OVERFLOW    = 302,                         ///< Read overflow.
+    FSP_ERR_SPI_PARITY       = 303,                         ///< Parity error.
+    FSP_ERR_OVERRUN          = 304,                         ///< Overrun error.
+
+    /* Start of CGC Specific */
+    FSP_ERR_CLOCK_INACTIVE        = 400,                    ///< Inactive clock specified as system clock.
+    FSP_ERR_CLOCK_ACTIVE          = 401,                    ///< Active clock source cannot be modified without stopping first.
+    FSP_ERR_NOT_STABILIZED        = 403,                    ///< Clock has not stabilized after its been turned on/off
+    FSP_ERR_PLL_SRC_INACTIVE      = 404,                    ///< PLL initialization attempted when PLL source is turned off
+    FSP_ERR_OSC_STOP_DET_ENABLED  = 405,                    ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
+    FSP_ERR_OSC_STOP_DETECTED     = 406,                    ///< The Oscillation stop detection status flag is set
+    FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407,                    ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
+    FSP_ERR_CLKOUT_EXCEEDED       = 408,                    ///< Output on target output clock pin exceeds maximum supported limit
+    FSP_ERR_USB_MODULE_ENABLED    = 409,                    ///< USB clock configure request with USB Module enabled
+    FSP_ERR_HARDWARE_TIMEOUT      = 410,                    ///< A register read or write timed out
+    FSP_ERR_LOW_VOLTAGE_MODE      = 411,                    ///< Invalid clock setting attempted in low voltage mode
+
+    /* Start of FLASH Specific */
+    FSP_ERR_PE_FAILURE             = 500,                   ///< Unable to enter Programming mode.
+    FSP_ERR_CMD_LOCKED             = 501,                   ///< Peripheral in command locked state
+    FSP_ERR_FCLK                   = 502,                   ///< FCLK must be >= 4 MHz
+    FSP_ERR_INVALID_LINKED_ADDRESS = 503,                   ///< Function or data are linked at an invalid region of memory
+    FSP_ERR_BLANK_CHECK_FAILED     = 504,                   ///< Blank check operation failed
+
+    /* Start of CAC Specific */
+    FSP_ERR_INVALID_CAC_REF_CLOCK = 600,                    ///< Measured clock rate < reference clock rate
+
+    /* Start of IIRFA Specific */
+    FSP_ERR_INVALID_RESULT = 700,                           ///< The result of one or more calculations was +/- infinity.
+
+    /* Start of GLCD Specific */
+    FSP_ERR_CLOCK_GENERATION           = 1000,              ///< Clock cannot be specified as system clock
+    FSP_ERR_INVALID_TIMING_SETTING     = 1001,              ///< Invalid timing parameter
+    FSP_ERR_INVALID_LAYER_SETTING      = 1002,              ///< Invalid layer parameter
+    FSP_ERR_INVALID_ALIGNMENT          = 1003,              ///< Invalid memory alignment found
+    FSP_ERR_INVALID_GAMMA_SETTING      = 1004,              ///< Invalid gamma correction parameter
+    FSP_ERR_INVALID_LAYER_FORMAT       = 1005,              ///< Invalid color format in layer
+    FSP_ERR_INVALID_UPDATE_TIMING      = 1006,              ///< Invalid timing for register update
+    FSP_ERR_INVALID_CLUT_ACCESS        = 1007,              ///< Invalid access to CLUT entry
+    FSP_ERR_INVALID_FADE_SETTING       = 1008,              ///< Invalid fade-in/fade-out setting
+    FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009,              ///< Invalid gamma correction parameter
+
+    /* Start of JPEG Specific */
+    FSP_ERR_JPEG_ERR                                = 1100, ///< JPEG error
+    FSP_ERR_JPEG_SOI_NOT_DETECTED                   = 1101, ///< SOI not detected until EOI detected.
+    FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED              = 1102, ///< SOF1 to SOFF detected.
+    FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT           = 1103, ///< Unprovided pixel format detected.
+    FSP_ERR_JPEG_SOF_ACCURACY_ERROR                 = 1104, ///< SOF accuracy error: other than 8 detected.
+    FSP_ERR_JPEG_DQT_ACCURACY_ERROR                 = 1105, ///< DQT accuracy error: other than 0 detected.
+    FSP_ERR_JPEG_COMPONENT_ERROR1                   = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
+    FSP_ERR_JPEG_COMPONENT_ERROR2                   = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
+    FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED          = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
+    FSP_ERR_JPEG_SOS_NOT_DETECTED                   = 1109, ///< SOS not detected: SOS not detected until EOI detected.
+    FSP_ERR_JPEG_EOI_NOT_DETECTED                   = 1110, ///< EOI not detected (default)
+    FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
+    FSP_ERR_JPEG_IMAGE_SIZE_ERROR                   = 1112, ///< Image size error detected.
+    FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR         = 1113, ///< Last MCU data number error detected.
+    FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR            = 1114, ///< Block data number error detected.
+    FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH              = 1115, ///< User provided buffer size not enough
+    FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE             = 1116, ///< JPEG Image size is not aligned with MCU
+
+    /* Start of touch panel framework specific */
+    FSP_ERR_CALIBRATE_FAILED = 1200,                        ///< Calibration failed
+
+    /* Start of IIRFA specific */
+    FSP_ERR_IIRFA_ECC_1BIT = 1300,                          ///< 1-bit ECC error detected
+    FSP_ERR_IIRFA_ECC_2BIT = 1301,                          ///< 2-bit ECC error detected
+
+    /* Start of IP specific */
+    FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400,                 ///< Requested IP does not exist on this device
+    FSP_ERR_IP_UNIT_NOT_PRESENT     = 1401,                 ///< Requested unit does not exist on this device
+    FSP_ERR_IP_CHANNEL_NOT_PRESENT  = 1402,                 ///< Requested channel does not exist on this device
+
+    /* Start of USB specific */
+    FSP_ERR_USB_FAILED      = 1500,
+    FSP_ERR_USB_BUSY        = 1501,
+    FSP_ERR_USB_SIZE_SHORT  = 1502,
+    FSP_ERR_USB_SIZE_OVER   = 1503,
+    FSP_ERR_USB_NOT_OPEN    = 1504,
+    FSP_ERR_USB_NOT_SUSPEND = 1505,
+    FSP_ERR_USB_PARAMETER   = 1506,
+
+    /* Start of Message framework specific */
+    FSP_ERR_NO_MORE_BUFFER           = 2000,         ///< No more buffer found in the memory block pool
+    FSP_ERR_ILLEGAL_BUFFER_ADDRESS   = 2001,         ///< Buffer address is out of block memory pool
+    FSP_ERR_INVALID_WORKBUFFER_SIZE  = 2002,         ///< Work buffer size is invalid
+    FSP_ERR_INVALID_MSG_BUFFER_SIZE  = 2003,         ///< Message buffer size is invalid
+    FSP_ERR_TOO_MANY_BUFFERS         = 2004,         ///< Number of buffer is too many
+    FSP_ERR_NO_SUBSCRIBER_FOUND      = 2005,         ///< No message subscriber found
+    FSP_ERR_MESSAGE_QUEUE_EMPTY      = 2006,         ///< No message found in the message queue
+    FSP_ERR_MESSAGE_QUEUE_FULL       = 2007,         ///< No room for new message in the message queue
+    FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008,         ///< Message subscriber lists is illegal
+    FSP_ERR_BUFFER_RELEASED          = 2009,         ///< Buffer has been released
+
+    /* Start of 2DG Driver specific */
+    FSP_ERR_D2D_ERROR_INIT      = 3000,              ///< D/AVE 2D has an error in the initialization
+    FSP_ERR_D2D_ERROR_DEINIT    = 3001,              ///< D/AVE 2D has an error in the initialization
+    FSP_ERR_D2D_ERROR_RENDERING = 3002,              ///< D/AVE 2D has an error in the rendering
+    FSP_ERR_D2D_ERROR_SIZE      = 3003,              ///< D/AVE 2D has an error in the rendering
+
+    /* Start of ETHER Driver specific */
+    FSP_ERR_ETHER_ERROR_NO_DATA              = 4000, ///< No Data in Receive buffer.
+    FSP_ERR_ETHER_ERROR_LINK                 = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
+    FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE    = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
+    FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
+    FSP_ERR_ETHER_ERROR_FILTERING            = 4004, ///< Detect multicast frame when multicast frame filtering enable
+    FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION    = 4005, ///< ETHERC/EDMAC has an error in the phy communication
+    FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE      = 4006, ///< Receive buffer is active.
+
+    /* Start of ETHER_PHY Driver specific */
+    FSP_ERR_ETHER_PHY_ERROR_LINK = 5000,             ///< PHY is not link up.
+    FSP_ERR_ETHER_PHY_NOT_READY  = 5001,             ///< PHY has an error in the Auto-negotiation
+
+    /* Start of BYTEQ library specific */
+    FSP_ERR_QUEUE_FULL  = 10000,                     ///< Queue is full, cannot queue another data
+    FSP_ERR_QUEUE_EMPTY = 10001,                     ///< Queue is empty, no data to dequeue
+
+    /* Start of CTSU Driver specific */
+    FSP_ERR_CTSU_SCANNING              = 6000,       ///< Scanning.
+    FSP_ERR_CTSU_NOT_GET_DATA          = 6001,       ///< Not processed previous scan data.
+    FSP_ERR_CTSU_INCOMPLETE_TUNING     = 6002,       ///< Incomplete initial offset tuning.
+    FSP_ERR_CTSU_DIAG_NOT_YET          = 6003,       ///< Diagnosis of data collected no yet.
+    FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004,       ///< Diagnosis of LDO over voltage failed.
+    FSP_ERR_CTSU_DIAG_CCO_HIGH         = 6005,       ///< Diagnosis of CCO into 19.2uA failed.
+    FSP_ERR_CTSU_DIAG_CCO_LOW          = 6006,       ///< Diagnosis of CCO into 2.4uA failed.
+    FSP_ERR_CTSU_DIAG_SSCG             = 6007,       ///< Diagnosis of SSCG frequency failed.
+    FSP_ERR_CTSU_DIAG_DAC              = 6008,       ///< Diagnosis of non-touch count value failed.
+    FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE   = 6009,       ///< Diagnosis of LDO output voltage failed.
+    FSP_ERR_CTSU_DIAG_OVER_VOLTAGE     = 6010,       ///< Diagnosis of over voltage detection circuit failed.
+    FSP_ERR_CTSU_DIAG_OVER_CURRENT     = 6011,       ///< Diagnosis of over current detection circuit failed.
+    FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE  = 6012,       ///< Diagnosis of LDO internal resistance value failed.
+    FSP_ERR_CTSU_DIAG_CURRENT_SOURCE   = 6013,       ///< Diagnosis of Current source value failed.
+    FSP_ERR_CTSU_DIAG_SENSCLK_GAIN     = 6014,       ///< Diagnosis of SENSCLK frequency gain failed.
+    FSP_ERR_CTSU_DIAG_SUCLK_GAIN       = 6015,       ///< Diagnosis of SUCLK frequency gain failed.
+    FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY   = 6016,       ///< Diagnosis of SUCLK clock recovery function failed.
+    FSP_ERR_CTSU_DIAG_CFC_GAIN         = 6017,       ///< Diagnosis of CFC oscillator gain failed.
+
+    /* Start of SDMMC specific */
+    FSP_ERR_CARD_INIT_FAILED     = 40000,            ///< SD card or eMMC device failed to initialize.
+    FSP_ERR_CARD_NOT_INSERTED    = 40001,            ///< SD card not installed.
+    FSP_ERR_DEVICE_BUSY          = 40002,            ///< Device is holding DAT0 low or another operation is ongoing.
+    FSP_ERR_CARD_NOT_INITIALIZED = 40004,            ///< SD card was removed.
+    FSP_ERR_CARD_WRITE_PROTECTED = 40005,            ///< Media is write protected.
+    FSP_ERR_TRANSFER_BUSY        = 40006,            ///< Transfer in progress.
+    FSP_ERR_RESPONSE             = 40007,            ///< Card did not respond or responded with an error.
+
+    /* Start of FX_IO specific */
+    FSP_ERR_MEDIA_FORMAT_FAILED = 50000,             ///< Media format failed.
+    FSP_ERR_MEDIA_OPEN_FAILED   = 50001,             ///< Media open failed.
+
+    /* Start of CAN specific */
+    FSP_ERR_CAN_DATA_UNAVAILABLE   = 60000,          ///< No data available.
+    FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001,          ///< Switching operation modes failed.
+    FSP_ERR_CAN_INIT_FAILED        = 60002,          ///< Hardware initialization failed.
+    FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003,          ///< Transmit in progress.
+    FSP_ERR_CAN_RECEIVE_MAILBOX    = 60004,          ///< Mailbox is setup as a receive mailbox.
+    FSP_ERR_CAN_TRANSMIT_MAILBOX   = 60005,          ///< Mailbox is setup as a transmit mailbox.
+    FSP_ERR_CAN_MESSAGE_LOST       = 60006,          ///< Receive message has been overwritten or overrun.
+    FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007,          ///< Transmit FIFO is full.
+
+    /* Start of SF_WIFI Specific */
+    FSP_ERR_WIFI_CONFIG_FAILED    = 70000,           ///< WiFi module Configuration failed.
+    FSP_ERR_WIFI_INIT_FAILED      = 70001,           ///< WiFi module initialization failed.
+    FSP_ERR_WIFI_TRANSMIT_FAILED  = 70002,           ///< Transmission failed
+    FSP_ERR_WIFI_INVALID_MODE     = 70003,           ///< API called when provisioned in client mode
+    FSP_ERR_WIFI_FAILED           = 70004,           ///< WiFi Failed.
+    FSP_ERR_WIFI_SCAN_COMPLETE    = 70005,           ///< Wifi scan has completed.
+    FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006,           ///< WiFi module is not connected to access point
+    FSP_ERR_WIFI_UNKNOWN_AT_CMD   = 70007,           ///< DA16200 Unknown AT command Error
+    FSP_ERR_WIFI_INSUF_PARAM      = 70008,           ///< DA16200 Insufficient parameter
+    FSP_ERR_WIFI_TOO_MANY_PARAMS  = 70009,           ///< DA16200 Too many parameters
+    FSP_ERR_WIFI_INV_PARAM_VAL    = 70010,           ///< DA16200 Wrong parameter value
+    FSP_ERR_WIFI_NO_RESULT        = 70011,           ///< DA16200 No result
+    FSP_ERR_WIFI_RSP_BUF_OVFLW    = 70012,           ///< DA16200 Response buffer overflow
+    FSP_ERR_WIFI_FUNC_NOT_CONFIG  = 70013,           ///< DA16200 Function is not configured
+    FSP_ERR_WIFI_NVRAM_WR_FAIL    = 70014,           ///< DA16200 NVRAM write failure
+    FSP_ERR_WIFI_RET_MEM_WR_FAIL  = 70015,           ///< DA16200 Retention memory write failure
+    FSP_ERR_WIFI_UNKNOWN_ERR      = 70016,           ///< DA16200 unknown error
+
+    /* Start of SF_CELLULAR Specific */
+    FSP_ERR_CELLULAR_CONFIG_FAILED       = 80000,    ///< Cellular module Configuration failed.
+    FSP_ERR_CELLULAR_INIT_FAILED         = 80001,    ///< Cellular module initialization failed.
+    FSP_ERR_CELLULAR_TRANSMIT_FAILED     = 80002,    ///< Transmission failed
+    FSP_ERR_CELLULAR_FW_UPTODATE         = 80003,    ///< Firmware is uptodate
+    FSP_ERR_CELLULAR_FW_UPGRADE_FAILED   = 80004,    ///< Firmware upgrade failed
+    FSP_ERR_CELLULAR_FAILED              = 80005,    ///< Cellular Failed.
+    FSP_ERR_CELLULAR_INVALID_STATE       = 80006,    ///< API Called in invalid state.
+    FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007,    ///< Cellular Network registration failed
+
+    /* Start of SF_BLE specific */
+    FSP_ERR_BLE_FAILED              = 90001,         ///< BLE operation failed
+    FSP_ERR_BLE_INIT_FAILED         = 90002,         ///< BLE device initialization failed
+    FSP_ERR_BLE_CONFIG_FAILED       = 90003,         ///< BLE device configuration failed
+    FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004,         ///< BLE device Profile already enabled
+    FSP_ERR_BLE_PRF_NOT_ENABLED     = 90005,         ///< BLE device not enabled
+
+    /* Start of SF_BLE_ABS specific */
+    FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001,       ///< Invalid operation is executed.
+    FSP_ERR_BLE_ABS_NOT_FOUND         = 91002,       ///< Valid data or free space is not found.
+
+    /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
+    FSP_ERR_CRYPTO_CONTINUE              = 0x10000,  ///< Continue executing function
+    FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001,  ///< Hardware resource busy
+    FSP_ERR_CRYPTO_SCE_FAIL              = 0x10002,  ///< Internal I/O buffer is not empty
+    FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003,  ///< Invalid index
+    FSP_ERR_CRYPTO_SCE_RETRY             = 0x10004,  ///< Retry
+    FSP_ERR_CRYPTO_SCE_VERIFY_FAIL       = 0x10005,  ///< Verify is failed
+    FSP_ERR_CRYPTO_SCE_ALREADY_OPEN      = 0x10006,  ///< HW SCE module is already opened
+    FSP_ERR_CRYPTO_NOT_OPEN              = 0x10007,  ///< Hardware module is not initialized
+    FSP_ERR_CRYPTO_UNKNOWN               = 0x10008,  ///< Some unknown error occurred
+    FSP_ERR_CRYPTO_NULL_POINTER          = 0x10009,  ///< Null pointer input as a parameter
+    FSP_ERR_CRYPTO_NOT_IMPLEMENTED       = 0x1000a,  ///< Algorithm/size not implemented
+    FSP_ERR_CRYPTO_RNG_INVALID_PARAM     = 0x1000b,  ///< An invalid parameter is specified
+    FSP_ERR_CRYPTO_RNG_FATAL_ERROR       = 0x1000c,  ///< A fatal error occurred
+    FSP_ERR_CRYPTO_INVALID_SIZE          = 0x1000d,  ///< Size specified is invalid
+    FSP_ERR_CRYPTO_INVALID_STATE         = 0x1000e,  ///< Function used in an valid state
+    FSP_ERR_CRYPTO_ALREADY_OPEN          = 0x1000f,  ///< control block is already opened
+    FSP_ERR_CRYPTO_INSTALL_KEY_FAILED    = 0x10010,  ///< Specified input key is invalid.
+    FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011,  ///< Authentication failed
+    FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL      = 0x10012,  ///< Failure to Init Cipher
+    FSP_ERR_CRYPTO_SCE_AUTHENTICATION    = 0x10013,  ///< Authentication failed
+    FSP_ERR_CRYPTO_SCE_PARAMETER         = 0x10014,  ///< Input date is illegal.
+    FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015,  ///< An invalid function call occurred.
+
+    /* Start of Crypto RSIP specific (0x10100) */
+    FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy
+    FSP_ERR_CRYPTO_RSIP_FATAL             = 0x10101, ///< Hardware fatal error or unexpected return
+    FSP_ERR_CRYPTO_RSIP_FAIL              = 0x10102, ///< Internal error
+    FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL      = 0x10103, ///< Input key type is illegal
+    FSP_ERR_CRYPTO_RSIP_AUTHENTICATION    = 0x10104, ///< Authentication failed
+
+    /* Start of SF_CRYPTO specific */
+    FSP_ERR_CRYPTO_COMMON_NOT_OPENED      = 0x20000, ///< Crypto Framework Common is not opened
+    FSP_ERR_CRYPTO_HAL_ERROR              = 0x20001, ///< Cryoto HAL module returned an error
+    FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH     = 0x20002, ///< Key buffer size is not enough to generate a key
+    FSP_ERR_CRYPTO_BUF_OVERFLOW           = 0x20003, ///< Attempt to write data larger than what the buffer can hold
+    FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
+    FSP_ERR_MESSAGE_TOO_LONG              = 0x20005, ///< Message for RSA encryption is too long.
+    FSP_ERR_RSA_DECRYPTION_ERROR          = 0x20006, ///< RSA Decryption error.
+
+    /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
+     *        Refer to sf_cryoto_err.h for Crypto error codes.
+     */
+
+    /* Start of Sensor specific */
+    FSP_ERR_SENSOR_INVALID_DATA             = 0x30000, ///< Data is invalid.
+    FSP_ERR_SENSOR_IN_STABILIZATION         = 0x30001, ///< Sensor is stabilizing.
+    FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished.
+
+    /* Start of COMMS specific */
+    FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000,              ///< Bus is not open.
+} fsp_err_t;
+
+/** @} */
+
+/***********************************************************************************************************************
+ * Function prototypes
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_features.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_features.h
new file mode 100644
index 00000000..f5bc4d35
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_features.h
@@ -0,0 +1,564 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef FSP_FEATURES_H
+#define FSP_FEATURES_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* C99 includes. */
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <assert.h>
+
+/* Different compiler support. */
+#include "fsp_common_api.h"
+#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Available modules. */
+typedef enum e_fsp_ip
+{
+    FSP_IP_CGC        = 1,             ///< Clock Generation Circuit
+    FSP_IP_CLMA       = 2,             ///< Clock Monitor Circuit
+    FSP_IP_MSTP       = 3,             ///< Module Stop
+    FSP_IP_ICU        = 4,             ///< Interrupt Control Unit
+    FSP_IP_BSC        = 5,             ///< Bus State Contoller
+    FSP_IP_CKIO       = 6,             ///< CKIO
+    FSP_IP_DMAC       = 7,             ///< DMA Controller
+    FSP_IP_ELC        = 8,             ///< Event Link Controller
+    FSP_IP_IOPORT     = 9,             ///< I/O Ports
+    FSP_IP_MTU3       = 10,            ///< Multi-Function Timer Pulse Unit
+    FSP_IP_POE3       = 11,            ///< Port Output Enable for MTU3
+    FSP_IP_GPT        = 12,            ///< General PWM Timer
+    FSP_IP_POEG       = 13,            ///< Port Output Enable for GPT
+    FSP_IP_TFU        = 14,            ///< Arithmetic Unit for Trigonometric Functions
+    FSP_IP_CMT        = 15,            ///< Compare Match Timer
+    FSP_IP_CMTW       = 16,            ///< Compare Match Timer W
+    FSP_IP_WDT        = 17,            ///< Watch Dog Timer
+    FSP_IP_RTC        = 18,            ///< Real Time Clock
+    FSP_IP_ETHSS      = 19,            ///< Ethernet Subsystem
+    FSP_IP_GMAC       = 20,            ///< Ethernet MAC
+    FSP_IP_ETHSW      = 21,            ///< Ethernet Switch
+    FSP_IP_ESC        = 22,            ///< EtherCAT Slave Controller
+    FSP_IP_USBHS      = 23,            ///< USB High Speed
+    FSP_IP_SCI        = 24,            ///< Serial Communications Interface
+    FSP_IP_IIC        = 25,            ///< I2C Bus Interface
+    FSP_IP_CANFD      = 26,            ///< Controller Area Network with Flexible Data Rate
+    FSP_IP_SPI        = 27,            ///< Serial Peripheral Interface
+    FSP_IP_XSPI       = 28,            ///< expanded Serial Peripheral Interface
+    FSP_IP_CRC        = 29,            ///< Cyclic Redundancy Check Calculator
+    FSP_IP_BSCAN      = 30,            ///< Boundary Scan
+    FSP_IP_DSMIF      = 31,            ///< Delta Sigma Interface
+    FSP_IP_ADC12      = 32,            ///< 12-Bit A/D Converter
+    FSP_IP_TSU        = 33,            ///< Temperature Sensor
+    FSP_IP_DOC        = 34,            ///< Data Operation Circuit
+    FSP_IP_SYSRAM     = 35,            ///< System SRAM
+    FSP_IP_ENCIF      = 36,            ///< Encoder Interface
+    FSP_IP_SHOSTIF    = 37,            ///< Serial Host Interface
+    FSP_IP_PHOSTIF    = 38,            ///< Parallel Host Interface
+    FSP_IP_SCIE       = 39,            ///< Serial Communications Interface for encoder interface
+    FSP_IP_TRACECLOCK = 40,            ///< Trace Clock
+    FSP_IP_ENCOUT     = 41,            ///< Encoder Divided-Output
+    FSP_IP_DDRSS      = 42,            ///< LPDDR4 SDRAM Subsystem
+    FSP_IP_LCDC       = 43,            ///< LCD Controller
+    FSP_IP_PCIE       = 44,            ///< PCI Express 3.0 Interface
+    FSP_IP_SDHI       = 45,            ///< SDMMC Host Interface
+    FSP_IP_CPU1       = 46,            ///< CPU1 Module Stop
+    FSP_IP_CR52       = 47,            ///< Cortex-R52 CPUn Module Stop
+    FSP_IP_CA55       = 48             ///< Cortex-A55 CPUn Module Stop
+} fsp_ip_t;
+
+/** Signals that can be mapped to an interrupt. */
+typedef enum e_fsp_signal
+{
+    FSP_SIGNAL_INTCPU0        = (0),   ///< Software interrupt 0
+    FSP_SIGNAL_INTCPU1        = (1),   ///< Software interrupt 1
+    FSP_SIGNAL_INTCPU2        = (2),   ///< Software interrupt 2
+    FSP_SIGNAL_INTCPU3        = (3),   ///< Software interrupt 3
+    FSP_SIGNAL_INTCPU4        = (4),   ///< Software interrupt 4
+    FSP_SIGNAL_INTCPU5        = (5),   ///< Software interrupt 5
+    FSP_SIGNAL_IRQ0           = (6),   ///< External pin interrupt 0
+    FSP_SIGNAL_IRQ1           = (7),   ///< External pin interrupt 1
+    FSP_SIGNAL_IRQ2           = (8),   ///< External pin interrupt 2
+    FSP_SIGNAL_IRQ3           = (9),   ///< External pin interrupt 3
+    FSP_SIGNAL_IRQ4           = (10),  ///< External pin interrupt 4
+    FSP_SIGNAL_IRQ5           = (11),  ///< External pin interrupt 5
+    FSP_SIGNAL_IRQ6           = (12),  ///< External pin interrupt 6
+    FSP_SIGNAL_IRQ7           = (13),  ///< External pin interrupt 7
+    FSP_SIGNAL_IRQ8           = (14),  ///< External pin interrupt 8
+    FSP_SIGNAL_IRQ9           = (15),  ///< External pin interrupt 9
+    FSP_SIGNAL_IRQ10          = (16),  ///< External pin interrupt 10
+    FSP_SIGNAL_IRQ11          = (17),  ///< External pin interrupt 11
+    FSP_SIGNAL_IRQ12          = (18),  ///< External pin interrupt 12
+    FSP_SIGNAL_IRQ13          = (19),  ///< External pin interrupt 13
+    FSP_SIGNAL_BSC_CMI        = (20),  ///< Refresh compare match interrupt
+    FSP_SIGNAL_DMAC0_INT0     = (21),  ///< DMAC0 transfer completion 0
+    FSP_SIGNAL_DMAC0_INT1     = (22),  ///< DMAC0 transfer completion 1
+    FSP_SIGNAL_DMAC0_INT2     = (23),  ///< DMAC0 transfer completion 2
+    FSP_SIGNAL_DMAC0_INT3     = (24),  ///< DMAC0 transfer completion 3
+    FSP_SIGNAL_DMAC0_INT4     = (25),  ///< DMAC0 transfer completion 4
+    FSP_SIGNAL_DMAC0_INT5     = (26),  ///< DMAC0 transfer completion 5
+    FSP_SIGNAL_DMAC0_INT6     = (27),  ///< DMAC0 transfer completion 6
+    FSP_SIGNAL_DMAC0_INT7     = (28),  ///< DMAC0 transfer completion 7
+    FSP_SIGNAL_DMAC1_INT0     = (37),  ///< DMAC1 transfer completion 0
+    FSP_SIGNAL_DMAC1_INT1     = (38),  ///< DMAC1 transfer completion 1
+    FSP_SIGNAL_DMAC1_INT2     = (39),  ///< DMAC1 transfer completion 2
+    FSP_SIGNAL_DMAC1_INT3     = (40),  ///< DMAC1 transfer completion 3
+    FSP_SIGNAL_DMAC1_INT4     = (41),  ///< DMAC1 transfer completion 4
+    FSP_SIGNAL_DMAC1_INT5     = (42),  ///< DMAC1 transfer completion 5
+    FSP_SIGNAL_DMAC1_INT6     = (43),  ///< DMAC1 transfer completion 6
+    FSP_SIGNAL_DMAC1_INT7     = (44),  ///< DMAC1 transfer completion 7
+    FSP_SIGNAL_CMT0_CMI       = (53),  ///< CMT0 Compare match
+    FSP_SIGNAL_CMT1_CMI       = (54),  ///< CMT1 Compare match
+    FSP_SIGNAL_CMT2_CMI       = (55),  ///< CMT2 Compare match
+    FSP_SIGNAL_CMT3_CMI       = (56),  ///< CMT3 Compare match
+    FSP_SIGNAL_CMT4_CMI       = (57),  ///< CMT4 Compare match
+    FSP_SIGNAL_CMT5_CMI       = (58),  ///< CMT5 Compare match
+    FSP_SIGNAL_CMTW0_CMWI     = (59),  ///< CMTW0 Compare match
+    FSP_SIGNAL_CMTW0_IC0I     = (60),  ///< CMTW0 Input capture of register 0
+    FSP_SIGNAL_CMTW0_IC1I     = (61),  ///< CMTW0 Input capture of register 1
+    FSP_SIGNAL_CMTW0_OC0I     = (62),  ///< CMTW0 Output compare of register 0
+    FSP_SIGNAL_CMTW0_OC1I     = (63),  ///< CMTW0 Output compare of register 1
+    FSP_SIGNAL_CMTW1_CMWI     = (64),  ///< CMTW1 Compare match
+    FSP_SIGNAL_CMTW1_IC0I     = (65),  ///< CMTW1 Input capture of register 0
+    FSP_SIGNAL_CMTW1_IC1I     = (66),  ///< CMTW1 Input capture of register 1
+    FSP_SIGNAL_CMTW1_OC0I     = (67),  ///< CMTW1 Output compare of register 0
+    FSP_SIGNAL_CMTW1_OC1I     = (68),  ///< CMTW1 Output compare of register 1
+    FSP_SIGNAL_TGIA0          = (69),  ///< MTU0.TGRA input capture/compare match
+    FSP_SIGNAL_TGIB0          = (70),  ///< MTU0.TGRB input capture/compare match
+    FSP_SIGNAL_TGIC0          = (71),  ///< MTU0.TGRC input capture/compare match
+    FSP_SIGNAL_TGID0          = (72),  ///< MTU0.TGRD input capture/compare match
+    FSP_SIGNAL_TCIV0          = (73),  ///< MTU0.TCNT overflow
+    FSP_SIGNAL_TGIE0          = (74),  ///< MTU0.TGRE compare match
+    FSP_SIGNAL_TGIF0          = (75),  ///< MTU0.TGRF compare match
+    FSP_SIGNAL_TGIA1          = (76),  ///< MTU1.TGRA input capture/compare match
+    FSP_SIGNAL_TGIB1          = (77),  ///< MTU1.TGRB input capture/compare match
+    FSP_SIGNAL_TCIV1          = (78),  ///< MTU1.TCNT overflow
+    FSP_SIGNAL_TCIU1          = (79),  ///< MTU1.TCNT underflow
+    FSP_SIGNAL_TGIA2          = (80),  ///< MTU2.TGRA input capture/compare match
+    FSP_SIGNAL_TGIB2          = (81),  ///< MTU2.TGRB input capture/compare match
+    FSP_SIGNAL_TCIV2          = (82),  ///< MTU2.TCNT overflow
+    FSP_SIGNAL_TCIU2          = (83),  ///< MTU2.TCNT underflow
+    FSP_SIGNAL_TGIA3          = (84),  ///< MTU3.TGRA input capture/compare match
+    FSP_SIGNAL_TGIB3          = (85),  ///< MTU3.TGRB input capture/compare match
+    FSP_SIGNAL_TGIC3          = (86),  ///< MTU3.TGRC input capture/compare match
+    FSP_SIGNAL_TGID3          = (87),  ///< MTU3.TGRD input capture/compare match
+    FSP_SIGNAL_TCIV3          = (88),  ///< MTU3.TCNT overflow
+    FSP_SIGNAL_TGIA4          = (89),  ///< MTU4.TGRA input capture/compare match
+    FSP_SIGNAL_TGIB4          = (90),  ///< MTU4.TGRB input capture/compare match
+    FSP_SIGNAL_TGIC4          = (91),  ///< MTU4.TGRC input capture/compare match
+    FSP_SIGNAL_TGID4          = (92),  ///< MTU4.TGRD input capture/compare match
+    FSP_SIGNAL_TCIV4          = (93),  ///< MTU4.TCNT overflow/underflow
+    FSP_SIGNAL_TGIU5          = (94),  ///< MTU5.TGRU input capture/compare match
+    FSP_SIGNAL_TGIV5          = (95),  ///< MTU5.TGRV input capture/compare match
+    FSP_SIGNAL_TGIW5          = (96),  ///< MTU5.TGRW input capture/compare match
+    FSP_SIGNAL_TGIA6          = (97),  ///< MTU6.TGRA input capture/compare match
+    FSP_SIGNAL_TGIB6          = (98),  ///< MTU6.TGRB input capture/compare match
+    FSP_SIGNAL_TGIC6          = (99),  ///< MTU6.TGRC input capture/compare match
+    FSP_SIGNAL_TGID6          = (100), ///< MTU6.TGRD input capture/compare match
+    FSP_SIGNAL_TCIV6          = (101), ///< MTU6.TCNT overflow
+    FSP_SIGNAL_TGIA7          = (102), ///< MTU7.TGRA input capture/compare match
+    FSP_SIGNAL_TGIB7          = (103), ///< MTU7.TGRB input capture/compare match
+    FSP_SIGNAL_TGIC7          = (104), ///< MTU7.TGRC input capture/compare match
+    FSP_SIGNAL_TGID7          = (105), ///< MTU7.TGRD input capture/compare match
+    FSP_SIGNAL_TCIV7          = (106), ///< MTU7.TCNT overflow/underflow
+    FSP_SIGNAL_TGIA8          = (107), ///< MTU8.TGRA input capture/compare match
+    FSP_SIGNAL_TGIB8          = (108), ///< MTU8.TGRB input capture/compare match
+    FSP_SIGNAL_TGIC8          = (109), ///< MTU8.TGRC input capture/compare match
+    FSP_SIGNAL_TGID8          = (110), ///< MTU8.TGRD input capture/compare match
+    FSP_SIGNAL_TCIV8          = (111), ///< MTU8.TCNT overflow
+    FSP_SIGNAL_OEI1           = (112), ///< Output enable interrupt 1
+    FSP_SIGNAL_OEI2           = (113), ///< Output enable interrupt 2
+    FSP_SIGNAL_OEI3           = (114), ///< Output enable interrupt 3
+    FSP_SIGNAL_OEI4           = (115), ///< Output enable interrupt 4
+    FSP_SIGNAL_GPT0_CCMPA     = (116), ///< GPT0 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT0_CCMPB     = (117), ///< GPT0 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT0_CMPC      = (118), ///< GPT0 GTCCRC compare match
+    FSP_SIGNAL_GPT0_CMPD      = (119), ///< GPT0 GTCCRD compare match
+    FSP_SIGNAL_GPT0_CMPE      = (120), ///< GPT0 GTCCRE compare match
+    FSP_SIGNAL_GPT0_CMPF      = (121), ///< GPT0 GTCCRF compare match
+    FSP_SIGNAL_GPT0_OVF       = (122), ///< GPT0 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT0_UDF       = (123), ///< GPT0 GTCNT underflow
+    FSP_SIGNAL_GPT0_DTE       = (124), ///< GPT0 Dead time error
+    FSP_SIGNAL_GPT1_CCMPA     = (125), ///< GPT1 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT1_CCMPB     = (126), ///< GPT1 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT1_CMPC      = (127), ///< GPT1 GTCCRC compare match
+    FSP_SIGNAL_GPT1_CMPD      = (128), ///< GPT1 GTCCRD compare match
+    FSP_SIGNAL_GPT1_CMPE      = (129), ///< GPT1 GTCCRE compare match
+    FSP_SIGNAL_GPT1_CMPF      = (130), ///< GPT1 GTCCRF compare match
+    FSP_SIGNAL_GPT1_OVF       = (131), ///< GPT1 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT1_UDF       = (132), ///< GPT1 GTCNT underflow
+    FSP_SIGNAL_GPT1_DTE       = (133), ///< GPT1 Dead time error
+    FSP_SIGNAL_GPT2_CCMPA     = (134), ///< GPT2 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT2_CCMPB     = (135), ///< GPT2 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT2_CMPC      = (136), ///< GPT2 GTCCRC compare match
+    FSP_SIGNAL_GPT2_CMPD      = (137), ///< GPT2 GTCCRD compare match
+    FSP_SIGNAL_GPT2_CMPE      = (138), ///< GPT2 GTCCRE compare match
+    FSP_SIGNAL_GPT2_CMPF      = (139), ///< GPT2 GTCCRF compare match
+    FSP_SIGNAL_GPT2_OVF       = (140), ///< GPT2 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT2_UDF       = (141), ///< GPT2 GTCNT underflow
+    FSP_SIGNAL_GPT2_DTE       = (142), ///< GPT2 Dead time error
+    FSP_SIGNAL_GPT3_CCMPA     = (143), ///< GPT3 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT3_CCMPB     = (144), ///< GPT3 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT3_CMPC      = (145), ///< GPT3 GTCCRC compare match
+    FSP_SIGNAL_GPT3_CMPD      = (146), ///< GPT3 GTCCRD compare match
+    FSP_SIGNAL_GPT3_CMPE      = (147), ///< GPT3 GTCCRE compare match
+    FSP_SIGNAL_GPT3_CMPF      = (148), ///< GPT3 GTCCRF compare match
+    FSP_SIGNAL_GPT3_OVF       = (149), ///< GPT3 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT3_UDF       = (150), ///< GPT3 GTCNT underflow
+    FSP_SIGNAL_GPT3_DTE       = (151), ///< GPT3 Dead time error
+    FSP_SIGNAL_GPT4_CCMPA     = (152), ///< GPT4 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT4_CCMPB     = (153), ///< GPT4 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT4_CMPC      = (154), ///< GPT4 GTCCRC compare match
+    FSP_SIGNAL_GPT4_CMPD      = (155), ///< GPT4 GTCCRD compare match
+    FSP_SIGNAL_GPT4_CMPE      = (156), ///< GPT4 GTCCRE compare match
+    FSP_SIGNAL_GPT4_CMPF      = (157), ///< GPT4 GTCCRF compare match
+    FSP_SIGNAL_GPT4_OVF       = (158), ///< GPT4 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT4_UDF       = (159), ///< GPT4 GTCNT underflow
+    FSP_SIGNAL_GPT4_DTE       = (160), ///< GPT4 Dead time error
+    FSP_SIGNAL_GPT5_CCMPA     = (161), ///< GPT5 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT5_CCMPB     = (162), ///< GPT5 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT5_CMPC      = (163), ///< GPT5 GTCCRC compare match
+    FSP_SIGNAL_GPT5_CMPD      = (164), ///< GPT5 GTCCRD compare match
+    FSP_SIGNAL_GPT5_CMPE      = (165), ///< GPT5 GTCCRE compare match
+    FSP_SIGNAL_GPT5_CMPF      = (166), ///< GPT5 GTCCRF compare match
+    FSP_SIGNAL_GPT5_OVF       = (167), ///< GPT5 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT5_UDF       = (168), ///< GPT5 GTCNT underflow
+    FSP_SIGNAL_GPT5_DTE       = (169), ///< GPT5 Dead time error
+    FSP_SIGNAL_GPT6_CCMPA     = (170), ///< GPT6 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT6_CCMPB     = (171), ///< GPT6 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT6_CMPC      = (172), ///< GPT6 GTCCRC compare match
+    FSP_SIGNAL_GPT6_CMPD      = (173), ///< GPT6 GTCCRD compare match
+    FSP_SIGNAL_GPT6_CMPE      = (174), ///< GPT6 GTCCRE compare match
+    FSP_SIGNAL_GPT6_CMPF      = (175), ///< GPT6 GTCCRF compare match
+    FSP_SIGNAL_GPT6_OVF       = (176), ///< GPT6 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT6_UDF       = (177), ///< GPT6 GTCNT underflow
+    FSP_SIGNAL_GPT6_DTE       = (178), ///< GPT6 Dead time error
+    FSP_SIGNAL_GPT7_CCMPA     = (179), ///< GPT7 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT7_CCMPB     = (180), ///< GPT7 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT7_CMPC      = (181), ///< GPT7 GTCCRC compare match
+    FSP_SIGNAL_GPT7_CMPD      = (182), ///< GPT7 GTCCRD compare match
+    FSP_SIGNAL_GPT7_CMPE      = (183), ///< GPT7 GTCCRE compare match
+    FSP_SIGNAL_GPT7_CMPF      = (184), ///< GPT7 GTCCRF compare match
+    FSP_SIGNAL_GPT7_OVF       = (185), ///< GPT7 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT7_UDF       = (186), ///< GPT7 GTCNT underflow
+    FSP_SIGNAL_GPT7_DTE       = (187), ///< GPT7 Dead time error
+    FSP_SIGNAL_GPT8_CCMPA     = (188), ///< GPT8 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT8_CCMPB     = (189), ///< GPT8 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT8_CMPC      = (190), ///< GPT8 GTCCRC compare match
+    FSP_SIGNAL_GPT8_CMPD      = (191), ///< GPT8 GTCCRD compare match
+    FSP_SIGNAL_GPT8_CMPE      = (192), ///< GPT8 GTCCRE compare match
+    FSP_SIGNAL_GPT8_CMPF      = (193), ///< GPT8 GTCCRF compare match
+    FSP_SIGNAL_GPT8_OVF       = (194), ///< GPT8 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT8_UDF       = (195), ///< GPT8 GTCNT underflow
+    FSP_SIGNAL_GPT8_DTE       = (196), ///< GPT8 Dead time error
+    FSP_SIGNAL_GPT9_CCMPA     = (197), ///< GPT9 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT9_CCMPB     = (198), ///< GPT9 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT9_CMPC      = (199), ///< GPT9 GTCCRC compare match
+    FSP_SIGNAL_GPT9_CMPD      = (200), ///< GPT9 GTCCRD compare match
+    FSP_SIGNAL_GPT9_CMPE      = (201), ///< GPT9 GTCCRE compare match
+    FSP_SIGNAL_GPT9_CMPF      = (202), ///< GPT9 GTCCRF compare match
+    FSP_SIGNAL_GPT9_OVF       = (203), ///< GPT9 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT9_UDF       = (204), ///< GPT9 GTCNT underflow
+    FSP_SIGNAL_GPT9_DTE       = (205), ///< GPT9 Dead time error
+    FSP_SIGNAL_GPT10_CCMPA    = (206), ///< GPT10 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT10_CCMPB    = (207), ///< GPT10 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT10_CMPC     = (208), ///< GPT10 GTCCRC compare match
+    FSP_SIGNAL_GPT10_CMPD     = (209), ///< GPT10 GTCCRD compare match
+    FSP_SIGNAL_GPT10_CMPE     = (210), ///< GPT10 GTCCRE compare match
+    FSP_SIGNAL_GPT10_CMPF     = (211), ///< GPT10 GTCCRF compare match
+    FSP_SIGNAL_GPT10_OVF      = (212), ///< GPT10 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT10_UDF      = (213), ///< GPT10 GTCNT underflow
+    FSP_SIGNAL_GPT10_DTE      = (214), ///< GPT10 Dead time error
+    FSP_SIGNAL_GPT11_CCMPA    = (215), ///< GPT11 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT11_CCMPB    = (216), ///< GPT11 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT11_CMPC     = (217), ///< GPT11 GTCCRC compare match
+    FSP_SIGNAL_GPT11_CMPD     = (218), ///< GPT11 GTCCRD compare match
+    FSP_SIGNAL_GPT11_CMPE     = (219), ///< GPT11 GTCCRE compare match
+    FSP_SIGNAL_GPT11_CMPF     = (220), ///< GPT11 GTCCRF compare match
+    FSP_SIGNAL_GPT11_OVF      = (221), ///< GPT11 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT11_UDF      = (222), ///< GPT11 GTCNT underflow
+    FSP_SIGNAL_GPT11_DTE      = (223), ///< GPT11 Dead time error
+    FSP_SIGNAL_GPT12_CCMPA    = (224), ///< GPT12 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT12_CCMPB    = (225), ///< GPT12 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT12_CMPC     = (226), ///< GPT12 GTCCRC compare match
+    FSP_SIGNAL_GPT12_CMPD     = (227), ///< GPT12 GTCCRD compare match
+    FSP_SIGNAL_GPT12_CMPE     = (228), ///< GPT12 GTCCRE compare match
+    FSP_SIGNAL_GPT12_CMPF     = (229), ///< GPT12 GTCCRF compare match
+    FSP_SIGNAL_GPT12_OVF      = (230), ///< GPT12 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT12_UDF      = (231), ///< GPT12 GTCNT underflow
+    FSP_SIGNAL_GPT12_DTE      = (232), ///< GPT12 Dead time error
+    FSP_SIGNAL_GPT13_CCMPA    = (233), ///< GPT13 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT13_CCMPB    = (234), ///< GPT13 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT13_CMPC     = (235), ///< GPT13 GTCCRC compare match
+    FSP_SIGNAL_GPT13_CMPD     = (236), ///< GPT13 GTCCRD compare match
+    FSP_SIGNAL_GPT13_CMPE     = (237), ///< GPT13 GTCCRE compare match
+    FSP_SIGNAL_GPT13_CMPF     = (238), ///< GPT13 GTCCRF compare match
+    FSP_SIGNAL_GPT13_OVF      = (239), ///< GPT13 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT13_UDF      = (240), ///< GPT13 GTCNT underflow
+    FSP_SIGNAL_GPT13_DTE      = (241), ///< GPT13 Dead time error
+    FSP_SIGNAL_POEG0_GROUP0   = (242), ///< POEG group A interrupt for channels in LLPP
+    FSP_SIGNAL_POEG0_GROUP1   = (243), ///< POEG group B interrupt for channels in LLPP
+    FSP_SIGNAL_POEG0_GROUP2   = (244), ///< POEG group C interrupt for channels in LLPP
+    FSP_SIGNAL_POEG0_GROUP3   = (245), ///< POEG group D interrupt for channels in LLPP
+    FSP_SIGNAL_POEG1_GROUP0   = (246), ///< POEG group A interrupt for channels in NONSAFETY
+    FSP_SIGNAL_POEG1_GROUP1   = (247), ///< POEG group B interrupt for channels in NONSAFETY
+    FSP_SIGNAL_POEG1_GROUP2   = (248), ///< POEG group C interrupt for channels in NONSAFETY
+    FSP_SIGNAL_POEG1_GROUP3   = (249), ///< POEG group D interrupt for channels in NONSAFETY
+    FSP_SIGNAL_GMAC_LPI       = (250), ///< GMAC1 energy efficient
+    FSP_SIGNAL_GMAC_PMT       = (251), ///< GMAC1 power management
+    FSP_SIGNAL_GMAC_SBD       = (252), ///< GMAC1 general interrupt
+    FSP_SIGNAL_ETHSW_INTR     = (253), ///< Ethernet Switch interrupt
+    FSP_SIGNAL_ETHSW_DLR      = (254), ///< Ethernet Switch DLR interrupt
+    FSP_SIGNAL_ETHSW_PRP      = (255), ///< Ethernet Switch PRP interrupt
+    FSP_SIGNAL_ETHSW_IHUB     = (256), ///< Ethernet Switch Integrated Hub interrupt
+    FSP_SIGNAL_ETHSW_PTRN0    = (257), ///< Ethernet Switch RX Pattern Matcher interrupt 0
+    FSP_SIGNAL_ETHSW_PTRN1    = (258), ///< Ethernet Switch RX Pattern Matcher interrupt 1
+    FSP_SIGNAL_ETHSW_PTRN2    = (259), ///< Ethernet Switch RX Pattern Matcher interrupt 2
+    FSP_SIGNAL_ETHSW_PTRN3    = (260), ///< Ethernet Switch RX Pattern Matcher interrupt 3
+    FSP_SIGNAL_ETHSW_PTRN4    = (261), ///< Ethernet Switch RX Pattern Matcher interrupt 4
+    FSP_SIGNAL_ETHSW_PTRN5    = (262), ///< Ethernet Switch RX Pattern Matcher interrupt 5
+    FSP_SIGNAL_ETHSW_PTRN6    = (263), ///< Ethernet Switch RX Pattern Matcher interrupt 6
+    FSP_SIGNAL_ETHSW_PTRN7    = (264), ///< Ethernet Switch RX Pattern Matcher interrupt 7
+    FSP_SIGNAL_ETHSW_PTRN8    = (265), ///< Ethernet Switch RX Pattern Matcher interrupt 8
+    FSP_SIGNAL_ETHSW_PTRN9    = (266), ///< Ethernet Switch RX Pattern Matcher interrupt 9
+    FSP_SIGNAL_ETHSW_PTRN10   = (267), ///< Ethernet Switch RX Pattern Matcher interrupt 10
+    FSP_SIGNAL_ETHSW_PTRN11   = (268), ///< Ethernet Switch RX Pattern Matcher interrupt 11
+    FSP_SIGNAL_ETHSW_PTPOUT0  = (269), ///< Ethernet switch timer pulse output 0
+    FSP_SIGNAL_ETHSW_PTPOUT1  = (270), ///< Ethernet switch timer pulse output 1
+    FSP_SIGNAL_ETHSW_PTPOUT2  = (271), ///< Ethernet switch timer pulse output 2
+    FSP_SIGNAL_ETHSW_PTPOUT3  = (272), ///< Ethernet switch timer pulse output 3
+    FSP_SIGNAL_ETHSW_TDMAOUT0 = (273), ///< Ethernet Switch TDMA timer output 0
+    FSP_SIGNAL_ETHSW_TDMAOUT1 = (274), ///< Ethernet Switch TDMA timer output 1
+    FSP_SIGNAL_ETHSW_TDMAOUT2 = (275), ///< Ethernet Switch TDMA timer output 2
+    FSP_SIGNAL_ETHSW_TDMAOUT3 = (276), ///< Ethernet Switch TDMA timer output 3
+    FSP_SIGNAL_ESC_SYNC0      = (277), ///< EtherCAT Sync0 interrupt
+    FSP_SIGNAL_ESC_SYNC1      = (278), ///< EtherCAT Sync1 interrupt
+    FSP_SIGNAL_ESC_CAT        = (279), ///< EtherCAT interrupt
+    FSP_SIGNAL_ESC_SOF        = (280), ///< EtherCAT SOF interrupt
+    FSP_SIGNAL_ESC_EOF        = (281), ///< EtherCAT EOF interrupt
+    FSP_SIGNAL_ESC_WDT        = (282), ///< EtherCAT WDT interrupt
+    FSP_SIGNAL_ESC_RST        = (283), ///< EtherCAT RESET interrupt
+    FSP_SIGNAL_USB_HI         = (284), ///< USB (Host) interrupt
+    FSP_SIGNAL_USB_FI         = (285), ///< USB (Function) interrupt
+    FSP_SIGNAL_USB_FDMA0      = (286), ///< USB (Function) DMA 0 transmit completion
+    FSP_SIGNAL_USB_FDMA1      = (287), ///< USB (Function) DMA 1 transmit completion
+    FSP_SIGNAL_SCI0_ERI       = (288), ///< SCI0 Receive error
+    FSP_SIGNAL_SCI0_RXI       = (289), ///< SCI0 Receive data full
+    FSP_SIGNAL_SCI0_TXI       = (290), ///< SCI0 Transmit data empty
+    FSP_SIGNAL_SCI0_TEI       = (291), ///< SCI0 Transmit end
+    FSP_SIGNAL_SCI1_ERI       = (292), ///< SCI1 Receive error
+    FSP_SIGNAL_SCI1_RXI       = (293), ///< SCI1 Receive data full
+    FSP_SIGNAL_SCI1_TXI       = (294), ///< SCI1 Transmit data empty
+    FSP_SIGNAL_SCI1_TEI       = (295), ///< SCI1 Transmit end
+    FSP_SIGNAL_SCI2_ERI       = (296), ///< SCI2 Receive error
+    FSP_SIGNAL_SCI2_RXI       = (297), ///< SCI2 Receive data full
+    FSP_SIGNAL_SCI2_TXI       = (298), ///< SCI2 Transmit data empty
+    FSP_SIGNAL_SCI2_TEI       = (299), ///< SCI2 Transmit end
+    FSP_SIGNAL_SCI3_ERI       = (300), ///< SCI3 Receive error
+    FSP_SIGNAL_SCI3_RXI       = (301), ///< SCI3 Receive data full
+    FSP_SIGNAL_SCI3_TXI       = (302), ///< SCI3 Transmit data empty
+    FSP_SIGNAL_SCI3_TEI       = (303), ///< SCI3 Transmit end
+    FSP_SIGNAL_SCI4_ERI       = (304), ///< SCI4 Receive error
+    FSP_SIGNAL_SCI4_RXI       = (305), ///< SCI4 Receive data full
+    FSP_SIGNAL_SCI4_TXI       = (306), ///< SCI4 Transmit data empty
+    FSP_SIGNAL_SCI4_TEI       = (307), ///< SCI4 Transmit end
+    FSP_SIGNAL_IIC0_EEI       = (308), ///< IIC0 Transfer error or event generation
+    FSP_SIGNAL_IIC0_RXI       = (309), ///< IIC0 Receive data full
+    FSP_SIGNAL_IIC0_TXI       = (310), ///< IIC0 Transmit data empty
+    FSP_SIGNAL_IIC0_TEI       = (311), ///< IIC0 Transmit end
+    FSP_SIGNAL_IIC1_EEI       = (312), ///< IIC1 Transfer error or event generation
+    FSP_SIGNAL_IIC1_RXI       = (313), ///< IIC1 Receive data full
+    FSP_SIGNAL_IIC1_TXI       = (314), ///< IIC1 Transmit data empty
+    FSP_SIGNAL_IIC1_TEI       = (315), ///< IIC1 Transmit end
+    FSP_SIGNAL_CAN_RXF        = (316), ///< CANFD RX FIFO interrupt
+    FSP_SIGNAL_CAN_GLERR      = (317), ///< CANFD Global error interrupt
+    FSP_SIGNAL_CAN0_TX        = (318), ///< CAFND0 Channel TX interrupt
+    FSP_SIGNAL_CAN0_CHERR     = (319), ///< CAFND0 Channel CAN error interrupt
+    FSP_SIGNAL_CAN0_COMFRX    = (320), ///< CAFND0 Common RX FIFO or TXQ interrupt
+    FSP_SIGNAL_CAN1_TX        = (321), ///< CAFND1 Channel TX interrupt
+    FSP_SIGNAL_CAN1_CHERR     = (322), ///< CAFND1 Channel CAN error interrupt
+    FSP_SIGNAL_CAN1_COMFRX    = (323), ///< CAFND1 Common RX FIFO or TXQ interrupt
+    FSP_SIGNAL_SPI0_SPRI      = (324), ///< SPI0 Reception buffer full
+    FSP_SIGNAL_SPI0_SPTI      = (325), ///< SPI0 Transmit buffer empty
+    FSP_SIGNAL_SPI0_SPII      = (326), ///< SPI0 SPI idle
+    FSP_SIGNAL_SPI0_SPEI      = (327), ///< SPI0 errors
+    FSP_SIGNAL_SPI0_SPCEND    = (328), ///< SPI0 Communication complete
+    FSP_SIGNAL_SPI1_SPRI      = (329), ///< SPI1 Reception buffer full
+    FSP_SIGNAL_SPI1_SPTI      = (330), ///< SPI1 Transmit buffer empty
+    FSP_SIGNAL_SPI1_SPII      = (331), ///< SPI1 SPI idle
+    FSP_SIGNAL_SPI1_SPEI      = (332), ///< SPI1 errors
+    FSP_SIGNAL_SPI1_SPCEND    = (333), ///< SPI1 Communication complete
+    FSP_SIGNAL_SPI2_SPRI      = (334), ///< SPI2 Reception buffer full
+    FSP_SIGNAL_SPI2_SPTI      = (335), ///< SPI2 Transmit buffer empty
+    FSP_SIGNAL_SPI2_SPII      = (336), ///< SPI2 SPI idle
+    FSP_SIGNAL_SPI2_SPEI      = (337), ///< SPI2 errors
+    FSP_SIGNAL_SPI2_SPCEND    = (338), ///< SPI2 Communication complete
+    FSP_SIGNAL_XSPI0_INT      = (339), ///< xSPI0 Interrupt
+    FSP_SIGNAL_XSPI0_INTERR   = (340), ///< xSPI0 Error interrupt
+    FSP_SIGNAL_XSPI1_INT      = (341), ///< xSPI1 Interrupt
+    FSP_SIGNAL_XSPI1_INTERR   = (342), ///< xSPI1 Error interrupt
+    FSP_SIGNAL_DSMIF0_CDRUI   = (343), ///< DSMIF0 current data register update (ORed ch0 to ch2)
+    FSP_SIGNAL_DSMIF1_CDRUI   = (344), ///< DSMIF1 current data register update (ORed ch3 to ch5)
+    FSP_SIGNAL_ADC0_ADI       = (345), ///< ADC0 A/D scan end interrupt
+    FSP_SIGNAL_ADC0_GBADI     = (346), ///< ADC0 A/D scan end interrupt for Group B
+    FSP_SIGNAL_ADC0_GCADI     = (347), ///< ADC0 A/D scan end interrupt for Group C
+    FSP_SIGNAL_ADC0_CMPAI     = (348), ///< ADC0 Window A compare match
+    FSP_SIGNAL_ADC0_CMPBI     = (349), ///< ADC0 Window B compare match
+    FSP_SIGNAL_ADC1_ADI       = (350), ///< ADC1 A/D scan end interrupt
+    FSP_SIGNAL_ADC1_GBADI     = (351), ///< ADC1 A/D scan end interrupt for Group B
+    FSP_SIGNAL_ADC1_GCADI     = (352), ///< ADC1 A/D scan end interrupt for Group C
+    FSP_SIGNAL_ADC1_CMPAI     = (353), ///< ADC1 Window A compare match
+    FSP_SIGNAL_ADC1_CMPBI     = (354), ///< ADC1 Window B compare match
+    FSP_SIGNAL_MBX_INT0       = (372), ///< Mailbox (Host CPU to Cortex-R52) interrupt 0
+    FSP_SIGNAL_MBX_INT1       = (373), ///< Mailbox (Host CPU to Cortex-R52) interrupt 1
+    FSP_SIGNAL_MBX_INT2       = (374), ///< Mailbox (Host CPU to Cortex-R52) interrupt 2
+    FSP_SIGNAL_MBX_INT3       = (375), ///< Mailbox (Host CPU to Cortex-R52) interrupt 3
+    FSP_SIGNAL_CPU0_ERR0      = (384), ///< Cortex-R52 CPU0 error event 0
+    FSP_SIGNAL_CPU0_ERR1      = (385), ///< Cortex-R52 CPU0 error event 1
+    FSP_SIGNAL_PERI_ERR0      = (388), ///< Peripherals error event 0
+    FSP_SIGNAL_PERI_ERR1      = (389), ///< Peripherals error event 1
+    FSP_SIGNAL_SHOST_INT      = (390), ///< SHOSTIF interrupt
+    FSP_SIGNAL_PHOST_INT      = (391), ///< PHOSTIF interrupt
+    FSP_SIGNAL_INTCPU6        = (392), ///< Software interrupt 6
+    FSP_SIGNAL_INTCPU7        = (393), ///< Software interrupt 7
+    FSP_SIGNAL_IRQ14          = (394), ///< External pin interrupt 14
+    FSP_SIGNAL_IRQ15          = (395), ///< External pin interrupt 15
+    FSP_SIGNAL_GPT14_CCMPA    = (396), ///< GPT14 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT14_CCMPB    = (397), ///< GPT14 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT14_CMPC     = (398), ///< GPT14 GTCCRC compare match
+    FSP_SIGNAL_GPT14_CMPD     = (399), ///< GPT14 GTCCRD compare match
+    FSP_SIGNAL_GPT14_CMPE     = (400), ///< GPT14 GTCCRE compare match
+    FSP_SIGNAL_GPT14_CMPF     = (401), ///< GPT14 GTCCRF compare match
+    FSP_SIGNAL_GPT14_OVF      = (402), ///< GPT14 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT14_UDF      = (403), ///< GPT14 GTCNT underflow
+    FSP_SIGNAL_GPT15_CCMPA    = (404), ///< GPT15 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT15_CCMPB    = (405), ///< GPT15 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT15_CMPC     = (406), ///< GPT15 GTCCRC compare match
+    FSP_SIGNAL_GPT15_CMPD     = (407), ///< GPT15 GTCCRD compare match
+    FSP_SIGNAL_GPT15_CMPE     = (408), ///< GPT15 GTCCRE compare match
+    FSP_SIGNAL_GPT15_CMPF     = (409), ///< GPT15 GTCCRF compare match
+    FSP_SIGNAL_GPT15_OVF      = (410), ///< GPT15 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT15_UDF      = (411), ///< GPT15 GTCNT underflow
+    FSP_SIGNAL_GPT16_CCMPA    = (412), ///< GPT16 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT16_CCMPB    = (413), ///< GPT16 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT16_CMPC     = (414), ///< GPT16 GTCCRC compare match
+    FSP_SIGNAL_GPT16_CMPD     = (415), ///< GPT16 GTCCRD compare match
+    FSP_SIGNAL_GPT16_CMPE     = (416), ///< GPT16 GTCCRE compare match
+    FSP_SIGNAL_GPT16_CMPF     = (417), ///< GPT16 GTCCRF compare match
+    FSP_SIGNAL_GPT16_OVF      = (418), ///< GPT16 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT16_UDF      = (419), ///< GPT16 GTCNT underflow
+    FSP_SIGNAL_GPT17_CCMPA    = (420), ///< GPT17 GTCCRA input capture/compare match
+    FSP_SIGNAL_GPT17_CCMPB    = (421), ///< GPT17 GTCCRB input capture/compare match
+    FSP_SIGNAL_GPT17_CMPC     = (422), ///< GPT17 GTCCRC compare match
+    FSP_SIGNAL_GPT17_CMPD     = (423), ///< GPT17 GTCCRD compare match
+    FSP_SIGNAL_GPT17_CMPE     = (424), ///< GPT17 GTCCRE compare match
+    FSP_SIGNAL_GPT17_CMPF     = (425), ///< GPT17 GTCCRF compare match
+    FSP_SIGNAL_GPT17_OVF      = (426), ///< GPT17 GTCNT overflow (GTPR compare match)
+    FSP_SIGNAL_GPT17_UDF      = (427), ///< GPT17 GTCNT underflow
+    FSP_SIGNAL_POEG2_GROUP0   = (428), ///< POEG group A interrupt for channels in SAFETY
+    FSP_SIGNAL_POEG2_GROUP1   = (429), ///< POEG group B interrupt for channels in SAFETY
+    FSP_SIGNAL_POEG2_GROUP2   = (430), ///< POEG group C interrupt for channels in SAFETY
+    FSP_SIGNAL_POEG2_GROUP3   = (431), ///< POEG group D interrupt for channels in SAFETY
+    FSP_SIGNAL_RTC_ALM        = (432), ///< Alarm interrupt
+    FSP_SIGNAL_RTC_1S         = (433), ///< 1 second interrupt
+    FSP_SIGNAL_RTC_PRD        = (434), ///< Fixed interval interrupt
+    FSP_SIGNAL_SCI5_ERI       = (435), ///< SCI5 Receive error
+    FSP_SIGNAL_SCI5_RXI       = (436), ///< SCI5 Receive data full
+    FSP_SIGNAL_SCI5_TXI       = (437), ///< SCI5 Transmit data empty
+    FSP_SIGNAL_SCI5_TEI       = (438), ///< SCI5 Transmit end
+    FSP_SIGNAL_IIC2_EEI       = (439), ///< IIC2 Transfer error or event generation
+    FSP_SIGNAL_IIC2_RXI       = (440), ///< IIC2 Receive data full
+    FSP_SIGNAL_IIC2_TXI       = (441), ///< IIC2 Transmit data empty
+    FSP_SIGNAL_IIC2_TEI       = (442), ///< IIC2 Transmit end
+    FSP_SIGNAL_SPI3_SPRI      = (443), ///< SPI3 Reception buffer full
+    FSP_SIGNAL_SPI3_SPTI      = (444), ///< SPI3 Transmit buffer empty
+    FSP_SIGNAL_SPI3_SPII      = (445), ///< SPI3 SPI idle
+    FSP_SIGNAL_SPI3_SPEI      = (446), ///< SPI3 errors
+    FSP_SIGNAL_SPI3_SPCEND    = (447), ///< SPI3 Communication complete
+    FSP_SIGNAL_DREQ           = (448), ///< External DMA request
+    FSP_SIGNAL_CAN_RF_DMAREQ0 = (449), ///< CAFND RX FIFO 0 DMA request
+    FSP_SIGNAL_CAN_RF_DMAREQ1 = (450), ///< CAFND RX FIFO 1 DMA request
+    FSP_SIGNAL_CAN_RF_DMAREQ2 = (451), ///< CAFND RX FIFO 2 DMA request
+    FSP_SIGNAL_CAN_RF_DMAREQ3 = (452), ///< CAFND RX FIFO 3 DMA request
+    FSP_SIGNAL_CAN_RF_DMAREQ4 = (453), ///< CAFND RX FIFO 4 DMA request
+    FSP_SIGNAL_CAN_RF_DMAREQ5 = (454), ///< CAFND RX FIFO 5 DMA request
+    FSP_SIGNAL_CAN_RF_DMAREQ6 = (455), ///< CAFND RX FIFO 6 DMA request
+    FSP_SIGNAL_CAN_RF_DMAREQ7 = (456), ///< CAFND RX FIFO 7 DMA request
+    FSP_SIGNAL_CAN0_CF_DMAREQ = (457), ///< CAFND0 First common FIFO DMA request
+    FSP_SIGNAL_CAN1_CF_DMAREQ = (458), ///< CAFND1 First common FIFO DMA request
+    FSP_SIGNAL_ADC0_WCMPM     = (459), ///< ADC0 compare match
+    FSP_SIGNAL_ADC0_WCMPUM    = (460), ///< ADC0 compare mismatch
+    FSP_SIGNAL_ADC1_WCMPM     = (461), ///< ADC1 compare match
+    FSP_SIGNAL_ADC1_WCMPUM    = (462), ///< ADC1 compare mismatch
+    FSP_SIGNAL_TCIV4_OF       = (463), ///< MTU4.TCNT overflow
+    FSP_SIGNAL_TCIV4_UF       = (464), ///< MTU4.TCNT underflow
+    FSP_SIGNAL_TCIV7_OF       = (465), ///< MTU7.TCNT overflow
+    FSP_SIGNAL_TCIV7_UF       = (466), ///< MTU7.TCNT underflow
+    FSP_SIGNAL_IOPORT_GROUP1  = (467), ///< Input edge detection of input port group 1
+    FSP_SIGNAL_IOPORT_GROUP2  = (468), ///< Input edge detection of input port group 2
+    FSP_SIGNAL_IOPORT_SINGLE0 = (469), ///< Input edge detection of single input port 0
+    FSP_SIGNAL_IOPORT_SINGLE1 = (470), ///< Input edge detection of single input port 1
+    FSP_SIGNAL_IOPORT_SINGLE2 = (471), ///< Input edge detection of single input port 2
+    FSP_SIGNAL_IOPORT_SINGLE3 = (472), ///< Input edge detection of single input port 3
+    FSP_SIGNAL_GPT0_ADTRGA    = (473), ///< GPT0 GTADTRA compare match
+    FSP_SIGNAL_GPT0_ADTRGB    = (474), ///< GPT0 GTADTRB compare match
+    FSP_SIGNAL_GPT1_ADTRGA    = (475), ///< GPT1 GTADTRA compare match
+    FSP_SIGNAL_GPT1_ADTRGB    = (476), ///< GPT1 GTADTRB compare match
+    FSP_SIGNAL_GPT2_ADTRGA    = (477), ///< GPT2 GTADTRA compare match
+    FSP_SIGNAL_GPT2_ADTRGB    = (478), ///< GPT2 GTADTRB compare match
+    FSP_SIGNAL_GPT3_ADTRGA    = (479), ///< GPT3 GTADTRA compare match
+    FSP_SIGNAL_GPT3_ADTRGB    = (480), ///< GPT3 GTADTRB compare match
+    FSP_SIGNAL_GPT4_ADTRGA    = (481), ///< GPT4 GTADTRA compare match
+    FSP_SIGNAL_GPT4_ADTRGB    = (482), ///< GPT4 GTADTRB compare match
+    FSP_SIGNAL_GPT5_ADTRGA    = (483), ///< GPT5 GTADTRA compare match
+    FSP_SIGNAL_GPT5_ADTRGB    = (484), ///< GPT5 GTADTRB compare match
+    FSP_SIGNAL_GPT6_ADTRGA    = (485), ///< GPT6 GTADTRA compare match
+    FSP_SIGNAL_GPT6_ADTRGB    = (486), ///< GPT6 GTADTRB compare match
+    FSP_SIGNAL_GPT7_ADTRGA    = (487), ///< GPT7 GTADTRA compare match
+    FSP_SIGNAL_GPT7_ADTRGB    = (488), ///< GPT7 GTADTRB compare match
+    FSP_SIGNAL_GPT8_ADTRGA    = (489), ///< GPT8 GTADTRA compare match
+    FSP_SIGNAL_GPT8_ADTRGB    = (490), ///< GPT8 GTADTRB compare match
+    FSP_SIGNAL_GPT9_ADTRGA    = (491), ///< GPT9 GTADTRA compare match
+    FSP_SIGNAL_GPT9_ADTRGB    = (492), ///< GPT9 GTADTRB compare match
+    FSP_SIGNAL_GPT10_ADTRGA   = (493), ///< GPT10 GTADTRA compare match
+    FSP_SIGNAL_GPT10_ADTRGB   = (494), ///< GPT10 GTADTRB compare match
+    FSP_SIGNAL_GPT11_ADTRGA   = (495), ///< GPT11 GTADTRA compare match
+    FSP_SIGNAL_GPT11_ADTRGB   = (496), ///< GPT11 GTADTRB compare match
+    FSP_SIGNAL_GPT12_ADTRGA   = (497), ///< GPT12 GTADTRA compare match
+    FSP_SIGNAL_GPT12_ADTRGB   = (498), ///< GPT12 GTADTRB compare match
+    FSP_SIGNAL_GPT13_ADTRGA   = (499), ///< GPT13 GTADTRA compare match
+    FSP_SIGNAL_GPT13_ADTRGB   = (500), ///< GPT13 GTADTRB compare match
+    FSP_SIGNAL_NONE
+} fsp_signal_t;
+
+typedef void (* fsp_vector_t)(void);
+
+/** @} (end addtogroup BSP_MCU) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_version.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_version.h
new file mode 100644
index 00000000..ced83aed
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/fsp_version.h
@@ -0,0 +1,66 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef FSP_VERSION_H
+#define FSP_VERSION_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+
+/*******************************************************************************************************************//**
+ * @addtogroup RENESAS_COMMON
+ * @{
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** FSP pack major version. */
+#define FSP_VERSION_MAJOR           (2U)
+
+/** FSP pack minor version. */
+#define FSP_VERSION_MINOR (2U)
+
+/** FSP pack patch version. */
+#define FSP_VERSION_PATCH (0U)
+
+/** FSP pack version build number (currently unused). */
+#define FSP_VERSION_BUILD           (0U)
+
+/** Public FSP version name. */
+#define FSP_VERSION_STRING          ("2.2.0")
+
+/** Unique FSP version ID. */
+#define FSP_VERSION_BUILD_STRING    ("Built with RZ/N Flexible Software Package version 2.2.0")
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** FSP Pack version structure */
+typedef union st_fsp_pack_version
+{
+    /** Version id */
+    uint32_t version_id;
+
+    /** Code version parameters, little endian order. */
+    struct version_id_b_s
+    {
+        uint8_t build;                 ///< Build version of FSP Pack
+        uint8_t patch;                 ///< Patch version of FSP Pack
+        uint8_t minor;                 ///< Minor version of FSP Pack
+        uint8_t major;                 ///< Major version of FSP Pack
+    } version_id_b;
+} fsp_pack_version_t;
+
+/** @} */
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ether_phy.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ether_phy.h
new file mode 100644
index 00000000..c76e3b4d
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ether_phy.h
@@ -0,0 +1,154 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @addtogroup ETHER_PHY
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ETHER_PHY_H
+#define R_ETHER_PHY_H
+
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_ether_phy_cfg.h"
+#include "r_ether_phy_api.h"
+#include "r_ether_selector.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** ETHER PHY control block. DO NOT INITIALIZE.  Initialization occurs when @ref ether_phy_api_t::open is called. */
+typedef struct st_ether_phy_instance_ctrl
+{
+    uint32_t open;                           ///< Used to determine if the channel is configured
+
+    /* Configuration of Ethernet PHY-LSI module. */
+    ether_phy_cfg_t const * p_ether_phy_cfg; ///< Pointer to initial configurations.
+
+    /* Interface for PHY-LSI chip. */
+    volatile uint32_t * p_reg_etherc;        ///< Pointer to ETHERC peripheral registers.
+
+    /* The capabilities of the local link as PHY data */
+    uint32_t local_advertise;                ///< Capabilities bitmap for local advertising.
+} ether_phy_instance_ctrl_t;
+
+/** Identify Ethernet and EtherCAT */
+typedef enum e_ether_phy_port_type
+{
+    ETHER_PHY_PORT_TYPE_ETHERNET  = 0, ///< Ethernet
+    ETHER_PHY_PORT_TYPE_ETHER_CAT = 1, ///< EtherCAT
+} ether_phy_port_type_t;
+
+/** Identify the access interface of the PHY register */
+typedef enum e_ether_phy_mdio
+{
+    ETHER_PHY_MDIO_GMAC  = 0,          ///< GMAC
+    ETHER_PHY_MDIO_ETHSW = 1,          ///< Ether switch
+    ETHER_PHY_MDIO_ESC   = 2,          ///< EtherCAT
+#if defined(BSP_MCU_GROUP_RZN2H)
+    ETHER_PHY_MDIO_GMAC1 = 3,          ///< GMAC1
+    ETHER_PHY_MDIO_GMAC2 = 4           ///< GMAC2
+#endif
+} ether_phy_mdio_t;
+
+/** PHY Speed for setting */
+typedef enum e_ether_phy_speed
+{
+    ETHER_PHY_SPEED_10_100  = 0,       ///< 100/10Mbps      (Note:Can be specified when auto-negotiation is ON)
+    ETHER_PHY_SPEED_10_1000 = 1,       ///< 1000/100/10Mbps (Note:Can be specified when auto-negotiation is ON)
+    ETHER_PHY_SPEED_10      = 2,       ///< 10Mbps
+    ETHER_PHY_SPEED_100     = 3,       ///< 100Mbps
+    ETHER_PHY_SPEED_1000    = 4,       ///< 1000Mbps
+} ether_phy_speed_t;
+
+/** PHY Duplex for setting */
+typedef enum e_ether_phy_duplex
+{
+    ETHER_PHY_DUPLEX_HALF = 0,         ///< Half duplex
+    ETHER_PHY_DUPLEX_FULL = 1,         ///< Full duplex
+} ether_phy_duplex_t;
+
+/** PHY Auto Negotiation for setting */
+typedef enum e_ether_phy_auto_negotiation
+{
+    ETHER_PHY_AUTO_NEGOTIATION_OFF = 0, ///< Auto Negotiation is ON
+    ETHER_PHY_AUTO_NEGOTIATION_ON  = 1, ///< Auto Negotiation is OFF
+} ether_phy_auto_negotiation_t;
+
+/** Extended configuration */
+typedef struct s_ether_phy_extend_cfg
+{
+    ether_phy_port_type_t port_type;                                     ///< Port type
+    ether_phy_mdio_t      mdio_type;                                     ///< MDIO type
+
+    ether_phy_speed_t            bps;                                    ///< PHY Speed
+    ether_phy_duplex_t           duplex;                                 ///< PHY Duplex
+    ether_phy_auto_negotiation_t auto_negotiation;                       ///< Auto Negotiation ON/OFF
+
+    bsp_io_port_pin_t phy_reset_pin;                                     ///< PHY reset pin
+    uint32_t          phy_reset_time;                                    ///< PHY reset assert time in millsecond
+
+    ether_selector_instance_t * p_selector_instance;                     ///< Instance of selector driver
+
+    void (* p_target_init)(ether_phy_instance_ctrl_t * p_instance_ctrl); ///< Pointer to callback that is called to initialize the target.
+} ether_phy_extend_cfg_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const ether_phy_api_t g_ether_phy_on_ether_phy;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Public Function Prototypes
+ **********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_Open(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg);
+
+fsp_err_t R_ETHER_PHY_Close(ether_phy_ctrl_t * const p_ctrl);
+
+fsp_err_t R_ETHER_PHY_ChipInit(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg);
+
+fsp_err_t R_ETHER_PHY_Read(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data);
+
+fsp_err_t R_ETHER_PHY_Write(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data);
+
+fsp_err_t R_ETHER_PHY_StartAutoNegotiate(ether_phy_ctrl_t * const p_ctrl);
+
+fsp_err_t R_ETHER_PHY_LinkPartnerAbilityGet(ether_phy_ctrl_t * const p_ctrl,
+                                            uint32_t * const         p_line_speed_duplex,
+                                            uint32_t * const         p_local_pause,
+                                            uint32_t * const         p_partner_pause);
+
+fsp_err_t R_ETHER_PHY_LinkStatusGet(ether_phy_ctrl_t * const p_ctrl);
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ETHER_PHY)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // R_ETHER_PHY_H
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ether_selector.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ether_selector.h
new file mode 100644
index 00000000..a2c3a2d6
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ether_selector.h
@@ -0,0 +1,78 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @addtogroup ETHER_SELECTOR
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ETHER_SELECTOR_H
+#define R_ETHER_SELECTOR_H
+
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_ether_selector_cfg.h"
+#include "r_ether_selector_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** ETHER SELECTOR control block. DO NOT INITIALIZE.  Initialization occurs when @ref ether_selector_api_t::open is called. */
+typedef struct st_ether_selector_instance_ctrl
+{
+    uint32_t open;                      ///< Used to determine if the channel is configured
+
+    /* Configuration of Ethernet Selector module. */
+    ether_selector_cfg_t const * p_cfg; ///< Pointer to initial configurations.
+
+    /* Interface for Ethernet Selector */
+    R_ETHSS_Type * p_reg;               ///< Pointer to Ethernet Subsystem peripheral registers.
+} ether_selector_instance_ctrl_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const ether_selector_api_t g_ether_selector_on_ether_selector;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Public Function Prototypes
+ **********************************************************************************************************************/
+fsp_err_t R_ETHER_SELECTOR_Open(ether_selector_ctrl_t * const p_ctrl, ether_selector_cfg_t const * const p_cfg);
+
+fsp_err_t R_ETHER_SELECTOR_Close(ether_selector_ctrl_t * const p_ctrl);
+
+fsp_err_t R_ETHER_SELECTOR_ConverterSet(ether_selector_ctrl_t * const p_ctrl,
+                                        ether_selector_speed_t        speed,
+                                        ether_selector_duplex_t       duplex);
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ETHER_SELECTOR)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // R_ETHER_SELECTOR_H
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ethsw.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ethsw.h
new file mode 100644
index 00000000..b1918048
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ethsw.h
@@ -0,0 +1,1242 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @addtogroup ETHER_SWITCH
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ETHSW_H
+#define R_ETHSW_H
+
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_ether_switch_cfg.h"
+#include "r_ether_switch_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define ETHSW_MAC_ADDR_LENGTH    (6U)
+
+/** Ethernet port macros */
+#define ETHSW_PORT_MGMT          (3U)  ///< Management port number
+#define ETHSW_PORT_BIT(x)    (1U << (x))
+
+/* RZN2L have the EFP feture, RZT2M don't have it. */
+#ifdef R_ETHSW_P0_QSTMACU0_MACA_Pos
+ #define ETHSW_EFP_FEATURE_SUPPORTED
+#endif                                       // R_ETHSW_P0_QSTMACU0_MACA_Pos
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+ #define ETHSW_VLAN_VID_LEN             (2U)
+#endif                                       /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+#define ETHER_SWITCH_TDMA_GPIO_COUNT    (8U) ///< Noumber of TDMA_GPIO
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+ #define ETHSW_EFP_SID_COUNT            (8U) ///< Number of Active Stream Identification table entry in EFP
+ #define ETHSW_EFP_MEATER_COUNT         (8U) ///< Number of Meater in EFP
+#endif                                       /* ETHSW_EFP_FEATURE_SUPPORTED */
+#define ETHSW_QUEUE_COUNT               (8U) ///< Number of queues ETHSW has
+#define ETHSW_QUEUE_COUNT               (8U) ///< Number of queues ETHSW has
+#define ETHSW_TDMA_GPIO_COUNT           (8U) ///< Number of TDMA_GPIO
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** ETHER SWITCH control block. DO NOT INITIALIZE.  Initialization occurs when @ref ether_switch_api_t::open is called. */
+typedef struct st_ethsw_instance_ctrl
+{
+    uint32_t open;                           ///< Used to determine if the channel is configured
+
+    /* Configuration of Ethernet SWITCH-LSI module. */
+    ether_switch_cfg_t const * p_switch_cfg; ///< Pointer to initial configurations.
+
+    /* Interface for Ethernet Swith */
+    R_ETHSW_Type     * p_reg_switch;         ///< Pointer to Ethernet Switch peripheral registers.
+    R_ETHSS_Type     * p_reg_ethss;          ///< Pointer to Ethernet Subsystem peripheral registers.
+    R_ETHSW_PTP_Type * p_reg_ethsw_ptp;      ///< Pointer to PTP Timer Pulse Control Registers.
+} ethsw_instance_ctrl_t;
+
+/** Enable/Disable Management Port Specific Frame Tagging */
+typedef enum e_ethsw_specific_tag
+{
+    ETHSW_SPECIFIC_TAG_DISABLE = 0,    ///< Disable
+    ETHSW_SPECIFIC_TAG_ENABLE  = 1     ///< Enable
+} ethsw_specific_tag_t;
+
+/** Enable/Disable PHYLINK Change Interrupt */
+typedef enum e_ethsw_phylink
+{
+    ETHSW_PHYLINK_DISABLE = 0,         ///< Disable
+    ETHSW_PHYLINK_ENABLE  = 1          ///< Enable
+} ethsw_phylink_t;
+
+/** Extend Configuration parameters. */
+typedef struct st_ethsw_extend_cfg
+{
+    /* Management port specific frmame tag */
+    ethsw_specific_tag_t specific_tag;    ///< Enable or Disable Management port specific frmame tag
+    uint16_t             specific_tag_id; ///< Management port specific frmame tag ID, when specific_tag is enable
+
+    /* Enable or disable link status change by PHYLINK. Call callback function when enable */
+    ethsw_phylink_t phylink;
+} ethsw_extend_cfg_t;
+
+/** Speed and duplex of the port */
+typedef enum e_ethsw_link_speed
+{
+    ETHSW_LINK_SPEED_NO_LINK = 0,      ///< Link is not established
+    ETHSW_LINK_SPEED_10H     = 1,      ///< Link status is 10Mbit/s and half duplex
+    ETHSW_LINK_SPEED_10F     = 2,      ///< Link status is 10Mbit/s and full duplex
+    ETHSW_LINK_SPEED_100H    = 3,      ///< Link status is 100Mbit/s and half duplex
+    ETHSW_LINK_SPEED_100F    = 4,      ///< Link status is 100Mbit/s and full duplex
+    ETHSW_LINK_SPEED_1000H   = 5,      ///< Link status is 1000Mbit/s and half duplex
+    ETHSW_LINK_SPEED_1000F   = 6       ///< Link status is 1000Mbit/s and full duplex
+} ethsw_link_speed_t;
+
+/** Port mask */
+typedef struct  st_ethsw_port_mask
+{
+    uint32_t mask : 4;                 ///< [3.. 0] Port Mask: bit0=Port0, bit1=Port1, bit2=Port2, bit3=Port3(Management Port)
+    uint32_t      : 28;                ///< [4..31]
+} ethsw_port_mask_t;
+
+/** MAC address */
+typedef uint8_t ethsw_mac_addr_t[ETHSW_MAC_ADDR_LENGTH];
+
+/** Address in MAC table entry */
+typedef struct st_ethsw_mac_table_entry_addr
+{
+    ethsw_mac_addr_t * mac_addr;       ///< MAC address pointer
+    uint16_t           vlan_id;        ///< VLAN ID
+} ethsw_mac_table_entry_addr_t;
+
+/** Information in MAC table entry */
+typedef struct st_ethsw_mac_table_entry_info
+{
+    ethsw_port_mask_t port_mask;       ///< port mask
+    uint32_t          priority;        ///< switching priority
+} ethsw_mac_table_entry_info_t;
+
+/** MAC table config */
+typedef struct st_ethsw_mac_table_config
+{
+    bool learning;                     ///< Enable/disable MAC learning
+    bool aging;                        ///< Enable/disable address aging
+    bool migration;                    ///< Enable/disable the migration of devices from one port to another
+    bool independent_vlan;             ///< Enable/disable independent VLAN learning
+    bool discard_unknown;              ///< Enable/disable discarding of unknown destination frames
+} ethsw_mac_table_config_t;
+
+/** MAC table clear modes */
+typedef enum e_ethsw_mac_table_clear_mode
+{
+    ETHSW_MAC_TABLE_CLEAR_STATIC  = 0, ///< Static MAC table entries
+    ETHSW_MAC_TABLE_CLEAR_DYNAMIC = 1, ///< Learned MAC table entries
+    ETHSW_MAC_TABLE_CLEAR_ALL     = 2, ///< Static and learn entries
+} ethsw_mac_table_clear_mode_t;
+
+/** Flood domain configuration for unknown frames */
+typedef struct st_ethsw_flood_unknown_config
+{
+    ethsw_port_mask_t port_mask_bcast; ///< flood domain port mask for broadcasts with unkown destination
+    ethsw_port_mask_t port_mask_mcast; ///< flood domain port mask for multicasts with unkown destination
+    ethsw_port_mask_t port_mask_ucast; ///< flood domain port mask for unicasts with unkown destination
+} ethsw_flood_unknown_config_t;
+
+/** Link status */
+typedef enum e_ethsw_link_status
+{
+    ETHSW_LINK_STATE_DOWN = 0,         ///< Link Down
+    ETHSW_LINK_STATE_UP   = 1,         ///< Link Up
+} ethsw_link_status_t;
+
+/** DLR events for the DLR State Machine */
+typedef enum e_ethsw_dlr_event
+{
+    ETHSW_DLR_EVENT_LINKLOST      = 0, ///< Link was lost
+    ETHSW_DLR_EVENT_OWNFRAME      = 1, ///< the device received its own frame
+    ETHSW_DLR_EVENT_LINKRESTORED  = 2, ///< Link is restored
+    ETHSW_DLR_EVENT_BEACONFRAME   = 3, ///< Beacon Frame received
+    ETHSW_DLR_EVENT_BEACONTIMEOUT = 4, ///< Beacon Timer timed out
+    ETHSW_DLR_EVENT_NEWSUPERVISOR = 5, ///< a new Ring Supervisor was detected
+    ETHSW_DLR_EVENT_NEWSTATE      = 6, ///< Beacon Hardware detected new state
+} ethsw_dlr_event_t;
+
+/** DLR initilize */
+typedef struct st_ethsw_dlr_init
+{
+    ethsw_mac_addr_t * p_host_addr;    ///< host MAC address pointer
+    void (* p_dlr_callback)(           ///< callback function pointer
+        ethsw_dlr_event_t event,
+        uint32_t          port);
+} ethsw_dlr_init_t;
+
+/** DLR beacon frame receive status */
+typedef enum e_ethsw_dlr_beacon_state
+{
+    ETHSW_DLR_BEACON_INVALID = 0,      ///< Not receiving the valid beacon frmae
+    ETHSW_DLR_BEACON_VALID   = 1,      ///< Receiving the valid beacon frmae
+} ethsw_dlr_beacon_state_t;
+
+/** DLR node status */
+typedef enum e_ethsw_dlr_node_state
+{
+    ETHSW_DLR_NODE_IDLE   = 0,         ///< Idole State
+    ETHSW_DLR_NODE_NORMAL = 1,         ///< Normal State
+    ETHSW_DLR_NODE_FAULT  = 2,         ///< Fault State
+} ethsw_dlr_node_state_t;
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+
+/** VLAN ID of an entry of the Active Stream Identification */
+typedef uint8_t ethsw_vlan_vid_t[ETHSW_VLAN_VID_LEN];
+
+/** The parameter for active steam Id table settings **/
+typedef struct
+{
+    uint8_t dmaci[6];                  ///< DMACI/VIDI are the DMAC and VID of the incoming frame,
+    uint8_t vidi[2];                   ///< which are matched to this table entry. A full match is required.
+    uint8_t dmaco[6];                  ///< If a frame matches this entry,
+    uint8_t vido[2];                   ///< its DMAC, VID, and PCP are replaced by these values.
+    uint8_t pcpo;                      ///< The DEI bit keeps its value.
+    uint8_t sid;                       ///< This is the frame handle assigned to the matched frame.
+    ///< In case of this implementation, it directly refers
+    ///< to a filter entry in the filter table.
+    bool     fs;                       ///< If set, the filter referenced by SID is applied. If cleared, no filtering is applied.
+    bool     ev;                       ///< If set, this table entry is valid. If cleared, this table entry shall be ignored.
+    uint32_t port;
+} ethsw_efp_asi_t;
+
+/** The parameter for vlan input verification mode settings **/
+typedef enum e_ethsw_vlan_input_verification_mode
+{
+    ETHSW_VICM_ALL_FRAMES_PASS = 0U,                          ///< Disabled, all frames pass
+    ETHSW_VICM_MODE_ADMIT_ONLY_VLAN_TAGGED_FRAMES,            ///< Admit Only VLAN-tagged frames
+    ETHSW_VICM_ADMIT_ONLY_UNTAGGED_OR_PRIORITY_TAGGED_FRAMES, ///< Admit Only Untagged or Priority-tagged frames
+    ETHSW_VICM_DROP_ALL_FRAMES,                               ///< Do not use (drop all frames)
+} ethsw_vlan_input_verification_mode_t;
+
+/** The parameter for priority regeneration settings **/
+typedef enum e_ethsw_vlan_input_tagging_mode
+{
+    ETHSW_VITM_VLAN_TAG_IS_NEITHER_ADDED_NOR_OVERWRITTEN = 0, ///< Disabled, VLAN tag is neither added nor overwritten.
+    ETHSW_VITM_SINGLE_TAGGING_WITH_PASSTHROUGH,               ///< Single Tagging with Passthrough / VLAN ID (VID) Overwrite.
+    ETHSW_VITM_SINGLE_TAGGING_WITH_REPLACE,                   ///< Single Tagging with Replace
+    ETHSW_VITM_TAG_ALWAYS,                                    ///< Tag always
+} ethsw_vlan_input_tagging_mode_t;
+
+typedef struct
+{
+    uint8_t vid[2];                       ///< Port Domain VID
+    uint8_t dei;                          ///< Port Drop Eligible Indicator
+    uint8_t pcp;                          ///< Port Priority Code Point
+    uint8_t tpid[2];                      ///< Port Tag Protocol Identifier
+    ethsw_vlan_input_tagging_mode_t vitm; ///< VLAN input verification mode
+    uint8_t pcp_remap[8];                 ///< VLAN Priority Code Point (PCP) Remap
+} ethsw_efp_priority_regeneration_t;
+
+/** The parameter for filtering function settings **/
+typedef enum e_ethsw_vlan_tag_mode
+{
+    ETHSW_VLAN_TAG_MODE_UN_TAGGED = 0,             ///< Un Tagged (the frame must be untagged to match to this filter)
+    ETHSW_VLAN_TAG_MODE_C_TAGGED,                  ///< C-Tagged (the frame must be C-Tagged to match to this filter)
+    ///< ( 10 : Reserved)
+    ETHSW_VLAN_TAG_MODE_DO_NOT_CHECK_VLAN_TAG = 3, ///< Do not check VLAN Tag (VLAN Tag check is skipped. All frames either untagged
+    ///< or tagged with any VLAN/PCP/DEI may match this filter.)
+} ethsw_vlan_tag_mode_t;
+
+/** The parameter for EFP interrupt source id **/
+typedef enum e_ethsw_efp_event
+{
+    ETHSW_EFP_INT_SRC_GATE_ERROR_DROP = 0, ///< Qci stream gate error interrupt (gating error drop)
+    ETHSW_EFP_INT_SRC_SDU_OVER_DROP,       ///< Qci stream filter error interrupt (max SDU over drop)
+    ETHSW_EFP_INT_SRC_FLOW_METER_DROP,     ///< Qci meter error interrupt (flow meter drop)
+    ETHSW_EFP_INT_SRC_RUNTIME_ERROR        ///< Frame parser error interrupt (runtime error)
+} ethsw_efp_event_t;
+
+typedef struct
+{
+    uint8_t               qdasa;       ///< MAC address (MACA) select
+    uint8_t               qmac[6];     ///< Qci stream filter table MAC address
+    uint8_t               qmam[6];     ///< Qci stream filter table MAC address bit mask
+    ethsw_vlan_tag_mode_t tagmd;       ///< Qci stream filter table VLAN Tag Mode
+    uint8_t               vlanid[2];   ///< Qci stream filter table VLAN ID[11:0]
+    uint8_t               dei;         ///< Qci stream filter table VLAN DEI
+    uint8_t               pcp;         ///< Qci stream filter table VLAN PCP[2:0]
+    uint8_t               vlanidm[2];  ///< Qci stream filter table VLAN ID[11:0] bit mask
+    uint8_t               deim;        ///< Qci stream filter table VLAN DEI bit mask
+    uint8_t               pcpm;        ///< Qci stream filter table VLAN PCP[2:0] bit mask
+} ethsw_efp_qci_stream_filter_t;
+
+/** The parameter for gating check settings **/
+typedef struct
+{
+    bool    gaidv;                     ///< Qci stream filter Gating check enable
+    uint8_t gaid;                      ///< Qci filter table gate ID
+    bool    qgmod;                     ///< Flow gate mode
+} ethsw_efp_gating_check_t;
+
+/** The parameter for sdu max verification settings **/
+typedef struct
+{
+    bool     msdue;                    ///< Qci stream filter table max SDU size Check enable
+    uint16_t msdu;                     ///< Qci stream filter table max SDU size
+    bool     qsmsm;                    ///< Qci stream MSDU mode
+} ethsw_efp_sdu_max_verification_t;
+
+/** The parameter for flow meter settings **/
+typedef struct
+{
+    bool     meidv;                    ///< Qci stream filter table Meter ID Valid
+    uint8_t  meid;                     ///< Qci stream filter table Meter ID
+    bool     cf;                       ///< Coupling flag for meter
+    bool     mm;                       ///< Flow meter mode
+    bool     rfd;                      ///< Red frame drop
+    uint32_t cbs;                      ///< CBS (Committed Burst Size)
+    uint32_t cir;                      ///< CIR (Committed Information Rate)
+    bool     me;                       ///< Enable meter
+} ethsw_efp_flow_metering_t;
+
+/** The parameter for configuration of interrupt source **/
+typedef struct
+{
+    uint8_t qsmoi;                     ///< Qci Stream Filter Error Interrupt Enable/Disable
+    uint8_t qgmoi;                     ///< Qci Gate Error Interrupt Enable/Disable
+    uint8_t qrfi;                      ///< Qci Meter Error Interrupt Enable/Disable
+    uint8_t errmask;                   ///< Frame Parser Runtime Error Mask
+} ethsw_efp_interrupt_source_t;
+
+/** The parameter for getting statistics information of EFP **/
+typedef struct
+{
+    uint32_t qsmois;                   ///< Qci Stream Filter Error Interrupt Status (SDU Oversize)
+    uint32_t qgmois;                   ///< Qci Gate Error Interrupt Status
+    uint32_t qrfis;                    ///< Qci Meter Error Interrupt Status
+    uint32_t error_status;             ///< Frame Parser Runtime Error Status
+} ethsw_efp_status_t;
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+/** Operating mode of RX Pattern Matcher */
+typedef enum e_ethsw_rx_pattern_mode
+{
+    ETHSW_RX_PATTER_MODE_FIXED = 0,       ///< Mode1: Fixed 12-byte match
+    ETHSW_RX_PATTER_MODE_LOOKUP,          ///< Mode2: 2-byte lookup mode
+    ETHSW_RX_PATTER_MODE_RANGE_MATCH,     ///< Mode3: 2-byte range match at set offset
+    ETHSW_RX_PATTER_MODE_RANGE_NOT_MATCH, ///< Mode4: 2-byte range not-match at set offset
+} ethsw_rx_pattern_mode_t;
+
+/** RX Pattern Matcher Function Control */
+typedef struct st_ethsw_rx_pattern_ctrl
+{
+    bool match_not;                    ///< The functions of this control are executed if the pattern does not match.
+    bool mgmt_fwd;                     ///< The frame is forwarded to the management port only
+    bool discard;                      ///< The frame is discarded.
+    bool set_prio;                     ///< Set frame priority, overriding normal classification.
+
+    ethsw_rx_pattern_mode_t mode;      ///< Operating mode
+
+    bool    timer_sel_ovr;             ///< Overrides the default timer to use by timestamp operations.
+    bool    force_forward;             ///< The frame is forwarded to the ports indicated in PORTMASK,
+    bool    hub_trigger;               ///< The port defined in the PORTMASK setting is allowed for transmitting one frame. Usable for Hub mode only.
+    bool    match_red;                 ///< Enable the pattern matcher only when the TDMA indicates that this is the RED period.
+    bool    match_not_red;             ///< Enable the pattern matcher only when the TDMA indicates that this is not the RED period.
+    bool    vlan_skip;                 ///< Skips VLAN tag (4 bytes)
+    uint8_t priority;                  ///< Priority of the frame used when SET_PRIO is set.
+    bool    learning_dis;              ///< The hardware learning function is not executed.
+
+    ethsw_port_mask_t port_mask;       ///< A port mask used depending on the control bits (for example, HUBTRIGGER).
+
+    bool    imc_trigger;               ///< The ports defined in the PORTMASK setting are allowed for transmitting one frame from the queues indicated by QUEUESEL.
+    bool    imc_trigger_dely;          ///< The ports defined in the PORTMASK setting are allowed for transmitting one frame from the queues indicated by QUEUESEL. Delayed by the value programmed in MMCTL_DLY_QTRIGGER_CTRL.
+    bool    swap_bytes;                ///< The byte order is swapped from the order received by the frame.
+    bool    match_lt;                  ///< The Length/Type field in the frame is compared against the value in length_type in the compare register.
+    uint8_t timer_sel;                 ///< Override value to use when TIMER_SEL_OVR is set to 1 for selecting the timer for this frame.
+    uint8_t queue_sel;                 ///< A queue selector for the HUBTRIGGER function.
+} ethsw_rx_pattern_ctrl_t;
+
+/** RX Pattern Matcher Function Data */
+typedef union st_ethsw_rx_pattern_data
+{
+    /* Mode1: Fixed 12-byte match */
+    struct
+    {
+        uint8_t cmp[12];               ///< Compare value 0 .. 12
+        uint8_t msk[12];               ///< Masks bits 0 .. 12
+    } fixed_mode;
+
+    /* Mode2: 2-byte lookup mode */
+    struct
+    {
+        uint16_t cmp0;                 ///< Compare value 0
+        uint16_t cmp1;                 ///< Compare value 1
+        uint16_t cmp2;                 ///< Compare value2
+        uint16_t cmp3;                 ///< Compare value 3
+        uint16_t cmp4;                 ///< Compare value 4
+        uint16_t cmp5;                 ///< Compare value 5
+        uint16_t mask;                 ///< Masks bits
+        uint16_t length_type;          ///< Value to compare against the frame's Length/Type when MATCH_LT is set in the config register.
+        uint8_t  offset;               ///< Byte offset to do the match after the MAC source address of the frame.
+        uint8_t  reserve;
+        uint16_t and_mask;             ///< Indicates that this pattern matcher matches if its own matching conditions match AND the pattern matchers which have their bits set to 1 in and_mask also match.
+        uint16_t cmp6;                 ///< Compare value 6
+        uint16_t cmp7;                 ///< Compare value 7
+    } lookup_mode;
+
+    /* Mode3: 2-byte range match at set offset */
+    /* Mode4: 2-byte range not-match at set offset */
+    struct
+    {
+        uint16_t min;                  ///< Minimum length to compare the 2 bytes at the offset.
+        uint16_t max;                  ///< Maximum length to compare the 2 bytes at the offset.
+        uint16_t reserve_1;
+        uint16_t reserve_2;
+        uint16_t reserve_3;
+        uint16_t reserve_4;
+        uint16_t mask;                 ///< Masks bits
+        uint16_t length_type;          ///< Value to compare against the frame's Length/Type when MATCH_LT is set in the config register.
+        uint8_t  offset;               ///< Byte offset to do the match after the MAC source address of the frame.
+        uint8_t  reserve_5;
+        uint16_t and_mask;             ///< Indicates that this pattern matcher matches if its own matching conditions match AND the pattern matchers which have their bits set to 1 in and_mask also match.
+        uint16_t reserve_6;
+        uint16_t reserve_7;
+    } range_mode;
+
+    /* register */
+    struct
+    {
+        uint32_t cmp_30;               ///< Value to set in PTRN_CMP_30
+        uint32_t cmp_74;               ///< Value to set in PTRN_CMP_74
+        uint32_t cmp_118;              ///< Value to set in PTRN_CMP_118
+        uint32_t msk_30;               ///< Value to set in PTRN_MSK_30
+        uint32_t msk_74;               ///< Value to set in PTRN_MSK_74
+        uint32_t msk_118;              ///< Value to set in PTRN_MSK_118
+    } reg;
+} ethsw_rx_pattern_data_t;
+
+/** The parameter for set/get the Rx pattern matcher function */
+typedef struct st_ethsw_rx_pattern_matcher
+{
+    uint16_t          pattern_sel;            ///< Pattern matcher number (0..11)
+    ethsw_port_mask_t pattern_port_mask;      ///< Port mask
+    bool              pattern_int;            ///< When true, called back from ISR
+
+    ethsw_rx_pattern_ctrl_t * p_pattern_ctrl; ///< RX Pattern Matcher Function Control
+    ethsw_rx_pattern_data_t * p_pattern_data; ///< RX Pattern Matcher Function Data
+} ethsw_rx_pattern_matcher_t;
+
+/** Callback event of the Rx pattern matcher */
+typedef enum e_ethsw_rx_pattern_event
+{
+    ETHSW_RX_PATTERN_MATCHER,          ///< Rx pattern matcher event
+} ethsw_rx_pattern_event_t;
+
+/** Callback parameter of the Rx pattern matcher */
+typedef struct st_ethsw_rx_pattern_event_data
+{
+    uint16_t match_int;                ///< Pattern mask to indicate pattern match
+    uint16_t error_int;                ///< Error for each port
+} ethsw_rx_pattern_event_data_t;
+
+/** The parameter for set preemptable queue */
+typedef struct
+{
+    union
+    {
+        uint8_t preempt_queues;        ///< Per-queue enable bit to configure which queues are used for preemptable traffic. Set to 1 the corresponding bit to configure a queue to be preemptable. The express queues always have priority over preemptable queues.
+        struct
+        {
+            uint8_t q0 : 1;            ///< queue0
+            uint8_t q1 : 1;            ///< queue1
+            uint8_t q2 : 1;            ///< queue2
+            uint8_t q3 : 1;            ///< queue3
+            uint8_t q4 : 1;            ///< queue4
+            uint8_t q5 : 1;            ///< queue5
+            uint8_t q6 : 1;            ///< queue6
+            uint8_t q7 : 1;            ///< queue7
+        } preempt_queues_b;
+    };
+    union
+    {
+        uint8_t preempt_on_qclose;     ///< Per-queue configuration bit to enable preempting a frame when the queue goes from OPENto CLOSED. When the corresponding bit is set to 1 and the queue is configured as preemptable in PREEMPT_ENA, a queue close event causes the current frame to be preempted, if preemption is operational.
+        struct
+        {
+            uint8_t q0 : 1;            ///< queue0
+            uint8_t q1 : 1;            ///< queue1
+            uint8_t q2 : 1;            ///< queue2
+            uint8_t q3 : 1;            ///< queue3
+            uint8_t q4 : 1;            ///< queue4
+            uint8_t q5 : 1;            ///< queue5
+            uint8_t q6 : 1;            ///< queue6
+            uint8_t q7 : 1;            ///< queue7
+        } preempt_on_qclose_b;
+    };
+} ethsw_preempt_queue_t;
+
+/** The parameter for set frame configuration of frame preemption for each ports */
+typedef struct
+{
+    bool    verify_dis;                ///< When set to 1, disables the verify process required for preemption operation. When PREEMPT_ENA is set to 1, preemption is not operational until the verify process validates that the peer port is also capable of performing frame preemption. Setting VERIFY_DIS disables this process and allows frame preemption without running the verify process.
+    bool    response_dis;              ///< When set to 1 prevents the MAC from responding to "verify" frames. "verify" frames are always replied to unless PREEMPT_ENA is set to 0 and RESPONSE_DIS is set to 1. This bit must be kept at 0 to be compliant with 802.3br.
+    uint8_t addfragsize;               ///< Minimum fragment size in increments of 64 bytes. Sets the minimum mPacket size when preempting a Preemptable frame. The default value of 0 corresponds to 64 bytes, a value of 1 corresponds to 128 bytes, and so on.
+    uint8_t tx_verify_time;            ///< Preemption verification timeout in milliseconds. When preemption is enabled and verification is running, this is the timeout to wait for a RESPONSE frame after sending a VERIFY frames +/? 1 ms. VERIFY frames are sent after the timeout up to two more times. Default value is 10 ms. When the value is set to less than 5 ms, it does not meet the 20% precision required by the 802.3br, so it is recommended to use larger times.
+    bool    rx_strict_pre;             ///< When set to 1, the preamble is checked so all bytes except the SFD are 0x55. When set to 0, only the last 2 bytes of the preamble are checked (SFD/SMD and FRAG_COUNT). It is recommended to set this bit to 1 to comply with the 802.3br specification. This bit must be set to 0 if only non-802.3br traffic is expected (for example, normal Ethernet traffic) and if custom preamble is used.
+    bool    rx_br_smd_dis;             ///< When set to 1, the receiver does not decode the 802.3br SMDs and assumes all frames areexpress frames. This bit must be set to 0 for correct operation with 802.3br, and can be set to 1 when 802.3br is not enabled to avoid false detection of SMDs. Setting this bit to 1 also causes any preempted frame to be aborted, bringing the re- assembly state machine to IDLE.
+    bool    rx_strict_br_ctl;          ///< When set to 1, strict checking of VERIFY and RESPONSE frames is enabled. When set to 1, the frame contents and frame length checks are also performed on these frames. The mCRC is always checked regardless of the value of this register. This bit must be set to 0 to be compliant with the functionality described in IEEE 802.3br.
+    bool    tx_mcrc_inv;               ///< When set to 1, the 32-bit XOR mask used to calculate the mCRC for transmitted frames is inverted. This bit must always be written to 0 and only used for debugging.
+    bool    rx_mcrc_inv;               ///< When set to 1, the 32-bit XOR mask used to calculate the mCRC for received frames is inverted. This bit must always be written to 0 and only used for debugging.
+} ethsw_preempt_port_ctrl_config_t;
+
+/** Port status of verification for frame preemption */
+typedef enum
+{
+    ETHSW_PREEMPT_VERIFY_STATUS_UNKNOWN = 0, ///< Unknown (during reset)
+    ETHSW_PREEMPT_VERIFY_STATUS_INITIAL,     ///< Initial (when preemption is disabled)
+    ETHSW_PREEMPT_VERIFY_STATUS_VERIFYING,   ///< Verifying
+    ETHSW_PREEMPT_VERIFY_STATUS_SUCCEEDED,   ///< Succeeded
+    ETHSW_PREEMPT_VERIFY_STATUS_FAILED,      ///< Failed
+    ETHSW_PREEMPT_VERIFY_STATUS_DISABLED     ///< Disabled (if preempt verification is disabled)
+} ethsw_preempt_verify_status_t;
+
+/** The parameter for get preemption status */
+typedef struct
+{
+    ethsw_preempt_verify_status_t verify_status;
+    bool    preempt_state;             ///< A per-port bit that indicates if a port is in a preempted state. This is a real-time indication meant for debugging.
+    bool    hold_req_state;            ///< A per-port bit that indicates if a port is preempted using MM_CTL.request (hold_req). This isa real-time indication meant for debugging.
+    uint8_t min_pfrm_adj;              ///< Adjust the minimum mPacket length, in increments of 4 bytes.
+    uint8_t last_pfrm_adj;             ///< Adjust the preemptable threshold when reaching the end of the frame, in increments of 4 bytes. Incrementing this value increments the length of the last mPacket.
+} ethsw_preempt_status_t;
+
+/** queue gate action */
+typedef enum e_ethsw_mmctl_qgate_action
+{
+    ETHSW_MMCTL_QGATE_NOT_CHANGE = 0,
+    ETHSW_MMCTL_QGATE_TOGGLE     = 1,
+    ETHSW_MMCTL_QGATE_CLOSE      = 2,
+    ETHSW_MMCTL_QGATE_OPEN       = 3,
+} ethsw_mmctl_qgate_action_t;
+
+/** queue gate */
+typedef struct st_ethsw_mmctl_qgate
+{
+    ethsw_port_mask_t          port_mask;                 ///< Per-port bit mask
+    ethsw_mmctl_qgate_action_t action[ETHSW_QUEUE_COUNT]; ///< Gate action for queue number 0..7
+} ethsw_mmclt_qgate_t;
+
+/** MMCTL pool ID. */
+typedef enum e_ethsw_mmctl_pool_id
+{
+    ETHSW_MMCTL_POOL_ID_0      = 0,    ///< Pool 0
+    ETHSW_MMCTL_POOL_ID_1      = 1,    ///< Pool 1
+    ETHSW_MMCTL_POOL_ID_GLOBAL = 8,    ///< Global Pool
+} ethsw_mmctl_pool_id_t;
+
+/** The parameter for set/get memory pool size function  */
+typedef struct st_ethsw_mmctl_pool_size
+{
+    ethsw_mmctl_pool_id_t pool_id;     ///< MMCTL pool ID.
+    uint16_t              cells;       ///< Memory pool size, in sells.
+} ethsw_mmctl_pool_size_t;
+
+/** The parameter for function that assins a memory pool for a queue. */
+typedef struct st_ethsw_mmctl_queue_assign
+{
+    uint8_t               queue_num;   ///< Queue number
+    ethsw_mmctl_pool_id_t pool_id;     ///< MMCTL pool ID.
+} ethsw_mmctl_queue_assign_t;
+
+/** The parameter for set / get length in bytes of the YELLOW period. */
+typedef struct st_ethsw_yellow_length
+{
+    bool     enable;                   ///< When true, length is valid.
+    uint16_t length;                   ///< Specify the byte length of the YELLOW period in units of 4 bytes.
+} ethsw_yellow_length_t;
+
+/** The action of queue flush event. */
+typedef enum e_ethsw_queu_flush_action
+{
+    ETHSW_QUEUE_FLUSH_DISABLE = 0,           ///< Disable flush
+    ETHSW_QUEUE_FLUSH_WHEN_QUEUE_IS_CLOSING, ///< Flush when queue is closed, discarding any new frames
+    ETHSW_QUEUE_FLUSH_WHEN_QUEUE_CLOSE,      ///< Flush on queue close until empty, then stops flushing
+    ETHSW_QUEUE_FLUSH_TRIGGER,               ///< TRIGGER flush until empty, then return to current flush mode
+} ethsw_queu_flush_action_t;
+
+/** The parameter for set / get queue flush event. */
+typedef struct st_ethsw_queue_flush_event
+{
+    ethsw_port_mask_t         port_mask;  ///< Per-port bit mask
+    uint8_t                   queue_mask; ///< 1 bit per queue indicating for which queues of the ports indicated by port_mask the flush state is changed as indicated in action.
+    ethsw_queu_flush_action_t action;     ///< Selects the flush state for the queues indicated by queue_mask in the ports indicated by port_mask.
+} ethsw_queue_flush_event_t;
+
+/** The parameter for QclosedNonempty status */
+typedef uint8_t ethsw_mmctl_qclosed_nonempty_t[4];
+
+/* Switch Base Statistics counter */
+typedef struct st_ethsw_statistic_switch_base
+{
+    uint32_t total_disc;               ///< Discarded Frame Total Number
+    uint32_t total_byt_disc;           ///< Discarded Frame Total Bytes
+    uint32_t total_frame;              ///< Processed Frame Total Number
+    uint32_t total_byt_frame;          ///< Processed Frame Total Bytes
+} ethsw_statistics_switch_base_t;
+
+/* MAC Statistics counter */
+typedef struct st_ethsw_statistic_mac
+{
+    uint64_t a_frames_transmitted_ok;              ///< MAC Transmitted Valid Frame Count
+    uint64_t a_frames_received_ok;                 ///< MAC Received Valid Frame Count
+    uint64_t a_frame_check_sequence_errors;        ///< MAC FCS Error Frame Count
+    uint64_t a_alignment_errors;                   ///< MAC Alignment Error Frame Count
+    uint64_t a_octets_transmitted_ok;              ///< MAC Transmitted Valid Frame Octets Count
+    uint64_t a_octets_received_ok;                 ///< MAC Received Valid Frame Octets Count
+    uint64_t a_tx_pause_mac_ctrl_frames;           ///< MAC Transmitted Pause Frame Count
+    uint64_t a_rx_pause_mac_ctrl_frames;           ///< MAC Received Pause Frame Count
+    uint64_t if_in_errors;                         ///< MAC Input Error Count
+    uint64_t if_out_errors;                        ///< MAC Output Error Count
+    uint64_t if_in_ucast_pkts;                     ///< MAC Received Unicast Frame Count
+    uint64_t if_in_multicast_pkts;                 ///< MAC Received Multicast Frame Count
+    uint64_t if_in_broadcast_pkts;                 ///< MAC Received Broadcast Frame Count
+    uint64_t if_out_discards;                      ///< MAC Discarded Outbound Frame Count
+    uint64_t if_out_ucast_pkts;                    ///< MAC Transmitted Unicast Frame Count
+    uint64_t if_out_multicast_pkts;                ///< MAC Transmitted Multicast Frame Count
+    uint64_t if_out_broadcast_pkts;                ///< MAC Transmitted Broadcast Frame Count
+    uint64_t ether_stats_drop_events;              ///< MAC Dropped Frame Count
+    uint64_t ether_stats_octets;                   ///< MAC All Frame Octets Count
+    uint64_t ether_stats_pkts;                     ///< MAC All Frame Count
+    uint64_t ether_stats_undersize_pkts;           ///< MAC Too Short Frame Count
+    uint64_t ether_stats_oversize_pkts;            ///< MAC Too Long Frame Count
+    uint64_t ether_stats_pkts_64_octets;           ///< MAC 64 Octets Frame Count
+    uint64_t ether_stats_pkts_65_to_127_octets;    ///< MAC 65 to 127 Octets Frame Count
+    uint64_t ether_stats_pkts_128_to_255_octets;   ///< MAC 128 to 255 Octets Frame Count
+    uint64_t ether_stats_pkts_256_to_511_octets;   ///< MAC 256 to 511 Octets Frame Count
+    uint64_t ether_stats_pkts_512_to_1023_octets;  ///< MAC 512 to 1023 Octets Frame Count
+    uint64_t ether_stats_pkts_1024_to_1518_octets; ///< MAC 1024 to 1518 Octets Frame Count
+    uint64_t ether_stats_pkts_1519_to_x_octets;    ///< MAC Over 1519 Octets Frame Count
+    uint64_t ether_stats_jabbers;                  ///< MAC Jabbers Frame Count
+    uint64_t ether_stats_fragments;                ///< MAC Fragment Frame Count
+    uint64_t vlan_received_ok;                     ///< MAC Received VLAN Tagged Frame Count
+    uint64_t vlan_transmitted_ok;                  ///< MAC Transmitted VLAN Tagged Frame Count
+    uint64_t frames_retransmitted;                 ///< MAC Retransmitted Frame Count
+    uint64_t a_deferred;                           ///< MAC Deferred Count
+    uint64_t a_multiple_collisions;                ///< MAC Multiple Collision Count
+    uint64_t a_single_collisions;                  ///< MAC Single Collision Count
+    uint64_t a_late_collisions;                    ///< MAC Late Collision Count
+    uint64_t a_excessive_collisions;               ///< MAC Excessive Collision Count
+    uint64_t a_carriersense_errors;                ///< MAC Carrier Sense Error Count
+} ethsw_statistics_mac_t;
+
+#ifdef ETHSW_EFP_FEATURE_SUPPORTED
+
+/* EFP Statistics counter */
+typedef struct st_ethsw_statistics_efp
+{
+    uint32_t qci_stream_match_pkts[ETHSW_EFP_SID_COUNT];   ///< Qci Stream Match Packet Count (sid 0-7)
+    uint32_t qci_msdu_passed_pkts[ETHSW_EFP_SID_COUNT];    ///< Qci MSDU Passed Packet Count (sid 0-7)
+    uint32_t qci_msdu_reject_pkts[ETHSW_EFP_SID_COUNT];    ///< Qci MSDU Reject Packet Count (sid 0-7)
+    uint32_t qci_gate_passed_pkts;                         ///< Qci Gate (All) Passed Packet Count
+    uint32_t qci_gate_dropped_pkts[ETHSW_TDMA_GPIO_COUNT]; ///< Qci Gate g Dropped Packet Count (gid 0-7)
+    uint32_t qci_mater_green_pkts[ETHSW_EFP_MEATER_COUNT]; ///< Qci Meter Green Packet Count (mid 0-7)
+    uint32_t qci_mater_red_pkts[ETHSW_EFP_MEATER_COUNT];   ///< Qci Meter Red Packet Count (mid 0-7)
+    uint32_t vlan_in_drop;                                 ///< VLAN Ingress Check Drop Frame Counter
+    uint32_t lookup_hit;                                   ///< DST Address Lookup Hit Counter
+} ethsw_statistics_efp_t;
+
+#endif                                                     /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+/* Global Discard and 802.3br Statistics counter */
+typedef struct st_ethsw_statistics_8023br
+{
+    uint32_t out_disc;                 ///< Discarded Outgoing Frame Count
+    uint32_t in_disc_vlan;             ///< Discarded Incoming VLAN Tagged Frame Count
+    uint32_t in_disc_untagged;         ///< Discarded Incoming VLAN Untagged Frame Count
+    uint32_t in_disc_blocked;          ///< Discarded Incoming Blocked Frame Count
+    uint32_t in_disc_any;              ///< Discarded Any Frame Count
+    uint32_t in_disc_src_filter;       ///< Discarded Address Source Count
+
+    uint32_t tx_hold_req;              ///< TX Hold Request Count
+    uint32_t tx_frag;                  ///< TX for Preemption Count
+    uint32_t rx_frag;                  ///< RX Continuation Count
+    uint32_t rx_assy_ok;               ///< RX Preempted Frame Success Count
+
+    uint16_t rx_assy_err;              ///< RX Preempted Frame Incorrect Count
+    uint16_t rx_smd_err;               ///< RX SMD Frame Count
+
+    uint8_t tx_verify_ok;              ///< TX VERIFY Frame Count
+    uint8_t tx_response_ok;            ///< TX RESPONSE Frame Count
+    uint8_t rx_verify_ok;              ///< RX VERIFY Frame Count
+    uint8_t rx_response_ok;            ///< RX RESPONSE Frame Count
+    uint8_t rx_verify_bad;             ///< RX Error VERIFY Frame Count
+    uint8_t rx_response_bad;           ///< RX Error RESPONSE Count
+} ethsw_statistics_8023br_t;
+
+/* DLR Statistics counter */
+typedef struct st_ethsw_statistics_dlr
+{
+    uint32_t rx_beacon_ok0;            ///< In port 0, Beacon Frames Received count
+    uint32_t rx_beacon_err0;           ///< In port 0, Beacon Frames Received count with CRC Error
+    uint32_t rx_disc_lf0;              ///< In port 0, Discarded frames count due to loop filtering
+    uint32_t rx_beacon_ok1;            ///< In port 1, Beacon Frames Received count
+    uint32_t rx_beacon_err1;           ///< In port 1, Beacon Frames Received count with CRC Error
+    uint32_t rx_disc_lf1;              ///< In port 1, Discarded frames count due to loop filtering
+} ethsw_statistics_dlr_t;
+
+/** The parameter for set CQF enable configuration */
+typedef struct
+{
+    union
+    {
+        uint8_t cqf_enable_priority;   ///< A per-queue enable to select which ingress priorities are queued in the two CQF queues.
+        struct
+        {
+            uint8_t p0 : 1;            ///< priority0
+            uint8_t p1 : 1;            ///< priority1
+            uint8_t p2 : 1;            ///< priority2
+            uint8_t p3 : 1;            ///< priority3
+            uint8_t p4 : 1;            ///< priority4
+            uint8_t p5 : 1;            ///< priority5
+            uint8_t p6 : 1;            ///< priority6
+            uint8_t p7 : 1;            ///< priority7
+        } cqf_enable_priority_b;
+    };
+    uint8_t cqf_queue;                 ///< Select which two physical queues are used for CQF. The queues used are QUEUE_SEL0 and QUEUE_SEL0 + 1. Frames are written into QUEUE_SEL0 when the gate control selected with GATE_SEL0 is 0, and into QUEUE_SEL0 + 1 when the gate control is 1.
+    uint8_t cqf_gate_sel;              ///< Select which gate control signal is used for selecting the output queue (these signals are the same as the ETHSW_TDMAOUT pins).
+    bool    use_sop;                   ///< When set to 1, the CFQ queue is determined when the SOP is received at the frame writerin the memory controller. When set to 0, the queue is determined when the EOP is received at the frame writer.
+    bool    cqf_gate_ref_sel;          ///< Select whether the gate control signal used for the CQF group is based on the egress port when set to 0, or the ingress port when set to 1.
+} ethsw_cqf_enable_t;
+
+/* Snoop offset type */
+typedef enum e_ethsw_snoop_offset_type
+{
+    ETHSW_SNOOP_OFFS_ETHER1 = 0,       ///< The offset starts counting from the first byte of the MAC destination address.
+    ETHSW_SNOOP_OFFS_ETHER2,           ///< The offset can either be specified starting after the MAC source address.
+    ETHSW_SNOOP_OFFS_VLAN,             ///< The offset can either be specified starting starting after any optional VLAN tags.
+    ETHSW_SNOOP_OFFS_IPDATA,           ///< The offset can either be specified starting starting after an IP header.
+    ETHSW_SNOOP_OFFS_IPPROT,           ///< The offset is ignored. The compare value is compared with the protocol field located within the IP.
+} ethsw_snoop_offset_type_t;
+
+/* Snoop comparison type */
+typedef enum e_ethsw_snoop_comp_type
+{
+    ETHSW_SNOOP_COMP_8 = 0,            ///< Applies a bitmask (AND) and compare single byte value.
+    ETHSW_SNOOP_COMP_8OR,              ///< Compare two different single byte value.
+    ETHSW_SNOOP_COMP_16,               ///< Compare a 16-bit value.
+    ETHSW_SNOOP_COMP_16PLUS,           ///< Repeats the 16-bit comparison at offset + 2, if the 16-bit comparison at offset failed.
+} ethsw_snoop_comp_type_t;
+
+/** Snoop parser config */
+typedef struct st_ethsw_snoop_parser_config
+{
+    uint8_t arith_block;                 ///< Arithmetic blkoc ID (0..1).
+    uint8_t parser_id;                   ///< Parser ID (0..3).
+    bool    enable;                      ///< true:enble, false:disable.
+    ethsw_snoop_offset_type_t offs_type; ///< Snooping mode.
+    ethsw_snoop_comp_type_t   comp_type; ///< How to handle matched frames.
+    uint8_t offset;                      ///< An offset in bytes to locate the data for comparison within the frame.
+    uint8_t comp_value;                  ///< The value to compare the frame data with at the given offset.
+    uint8_t mask_value2;                 ///< When ETHSW_SNOOP_COMP_8, bitmask for single byte compares. When ETHSW_SNOOP_COMP_8OR, 2nd compare value. When ETHSW_SNOOP_COMP_16 or ETHSW_SNOOP_COMP_16PLUS, least significant bits of a 16-bit compare value.
+} ethsw_snoop_parser_config_t;
+
+/** Snooping actions */
+typedef enum e_ethsw_snoop_action
+{
+    ETHSW_SNOOP_ACTION_DISABLE   = 0,  ///< Disabled, no snooping occurs (forward normally).
+    ETHSW_SNOOP_ACTION_ONLY_MGMT = 1,  ///< Forward to management port only.
+    ETHSW_SNOOP_ACTION_COPY_MGMT = 2,  ///< Forward normally and copy to management port.
+    ETHSW_SNOOP_ACTION_DISCARD   = 3   ///< Discard the frame
+} ethsw_snoop_action_t;
+
+/* Operation of paraser result */
+typedef enum e_ethsw_snoop_operat
+{
+    ETHSW_SNOOP_OPERAT_AND = 0,        ///< AND all selected inputs
+    ETHSW_SNOOP_OPERAT_OR  = 1         ///< OR all selected inputs
+} ethsw_snoop_operat_t;
+
+/** Snoop arithmetic config */
+typedef struct st_ethsw_snoop_arith_config
+{
+    uint8_t              arith_block;  ///< Arithmetic blkoc ID (0..1).
+    ethsw_snoop_operat_t operat;       ///< Operation of paraser result
+    ethsw_snoop_action_t action;       ///< Arithmetic action.
+} ethsw_snoop_arith_config_t;
+
+/** EEE */
+typedef struct st_ethsw_eee
+{
+    bool     enable;                   ///< State of EEE auto mode (true:enabled/false:disabled)
+    uint32_t idle_time;                ///< Idle time of EEE
+    uint32_t wakeup_time;              ///< Wakeup time of EEE
+} ethsw_eee_t;
+
+/** QoS mode */
+typedef struct st_ethsw_qos_mode
+{
+    bool    vlan_enable;               ///< VLAN Priority Enable
+    bool    ip_enable;                 ///< IP Priority Enable
+    bool    mac_enable;                ///< MAC Based Priority Enable
+    bool    type_enable;               ///< TYPE Based Priority Enable
+    uint8_t default_pri;               ///< Default Priority Enable Setting
+} ethsw_qos_mode_t;
+
+typedef struct st_ethsw_qos_prio_vlan
+{
+    uint32_t priority0 : 3;            ///< Priority 0 Setting
+    uint32_t priority1 : 3;            ///< Priority 1 Setting
+    uint32_t priority2 : 3;            ///< Priority 2 Setting
+    uint32_t priority3 : 3;            ///< Priority 3 Setting
+    uint32_t priority4 : 3;            ///< Priority 4 Setting
+    uint32_t priority5 : 3;            ///< Priority 5 Setting
+    uint32_t priority6 : 3;            ///< Priority 6 Setting
+    uint32_t priority7 : 3;            ///< Priority 7 Setting
+    uint32_t           : 8;            ///< Reserved
+} ethsw_qos_prio_vlan_t;
+
+/** QoS IP priority */
+typedef struct st_ethsw_qos_prio_ip
+{
+    uint8_t diffserv;                  ///< The DiffServ field of the IP packet
+    uint8_t priority;                  ///< The priority to assign.
+} ethsw_qos_prio_ip_t;
+
+/** QoS Ethertype priority */
+typedef struct st_ethsw_qos_prio_type
+{
+    uint16_t type1;                    ///< The first type to match against. A value of 0 disables that match.
+    uint8_t  prio1;                    ///< The priority to be assigned for the first match.
+    uint16_t type2;                    ///< The second type to match against. A value of 0 disables that match.
+    uint8_t  prio2;                    ///< The priority to be assigned for the second match.
+} ethsw_qos_prio_type_t;
+
+/** port mirroring modes */
+typedef enum e_ethsw_mirr_mode
+{
+    ETHSW_MIRR_MODE_DISABLE,           ///< Disable
+    ETHSW_MIRR_MODE_EGRESS_DA,         ///< Enable, Egress DA match
+    ETHSW_MIRR_MODE_EGRESS_SA,         ///< Enable, Egress SA match
+    ETHSW_MIRR_MODE_INGRESS_DA,        ///< Enable, Ingress DA match
+    ETHSW_MIRR_MODE_INGRESS_SA,        ///< Enable, Ingress SA match
+    ETHSW_MIRR_MODE_INGRESS_PORT,      ///< Enable, Ingress port match
+    ETHSW_MIRR_MODE_EGRESS_PORT        ///< Enable, Egress port match
+} ethsw_mirr_mode_t;
+
+/** mirror port config */
+typedef struct st_ethsw_mirror_conf
+{
+    uint32_t           mirror_port;    ///< The port id that will received all mirrored frames.
+    ethsw_mirr_mode_t  mirror_mode;    ///< The mode of mirroring to configure.
+    ethsw_port_mask_t  port_map;       ///< The port map to which the mirror configuration will be applied to.
+    ethsw_mac_addr_t * mac_addr;       ///< MAC address pointer
+} ethsw_mirror_conf_t;
+
+/** The parameter for set/get pulse generator. */
+typedef struct
+{
+    uint8_t  pulse_num;                ///< Pulse generator number (0..3)
+    bool     enable;                   ///< When true, enable
+    uint32_t start_sec;                ///< Pulse start second
+    uint32_t start_ns;                 ///< Pulse start nanosecond
+    uint16_t wide;                     ///< Pulse width
+    uint32_t period_sec;               ///< Pulse period second
+    uint32_t period_ns;                ///< Pulse period anosecond
+} ethsw_ts_pulse_generator_t;
+
+/** VLAN input processing modes */
+typedef enum e_ethsw_vlan_in_mode
+{
+    ETHSW_VLANIN_PASSTHROUGH_OVERRIDE, ///< Single Tagging with Passthrough/VID Overwrite
+    ETHSW_VLANIN_REPLACE,              ///< Single Tagging with Replace
+    ETHSW_VLANIN_TAG_ALWAYS,           ///< Tag always
+    ETHSW_VLANIN_DISABLE = 0xFF        ///< Disable VLAN
+} ethsw_vlan_in_mode_t;
+
+/** VLAN output processing mode */
+typedef enum e_ethsw_vlan_out_mode
+{
+    ETHSW_VLANOUT_DISABLE,             ///< No manipulation
+    ETHSW_VLANOUT_STRIP,               ///< Strip mode
+    ETHSW_VLANOUT_TAGTHROUGH,          ///< Tag Thru mode
+    ETHSW_VLANOUT_DOMAINTRANSP         ///< Domain / Transparent mode
+} ethsw_vlan_out_mode_t;
+
+/** tdma callback event */
+typedef enum e_ethsw_tdma_event
+{
+    ETHSW_TDMA_CALLBACK_TCV_INT      = 0x100, ///< Active event of TCV sequence entry
+    ETHSW_TDMA_CALLBACK_COUNTER1_INT = 0x101, ///< Active event of TDMA count1
+} ethsw_tdma_event_t;
+
+/** tdma callback data */
+typedef union
+{
+    uint16_t tcv_s_idx;                ///< index of TCV sequence entry (valu of TDMA_IRQ_STAT_ACK_b.TCV_IDX_ACK)
+} ethsw_tdma_callback_data_t;
+
+/** tdma enable parameter */
+typedef struct st_ethsw_tdma_enable
+{
+    bool              enable;          ///< True is enable, false:disabel.
+    uint8_t           time_num;        ///< Timer number to use as TDMA time source.
+    ethsw_port_mask_t port_mask;       ///< Port mask that TDMA operat.
+    uint32_t          tdma_start;      ///< Start nano time for the first cycle of TDMA
+    uint32_t          tdma_modulo;     ///< System timer modulo for 1 second.
+    uint32_t          tdma_cycle;      ///< Periodic cycle time for TDMA scheduler
+
+    void (* p_tdma_callback)(          ///< Pointer of callback function
+        ethsw_tdma_event_t           event,
+        ethsw_tdma_callback_data_t * p_tdma_data);
+} ethsw_tdma_enable_t;
+
+/** TDMA schedule entry parameter */
+typedef struct st_ethsw_tdma_schedule_entry
+{
+    uint32_t          time_offset;     ///< Time offset from the TDMA Cycle Start
+    ethsw_port_mask_t port_mask;       ///< Bit mask (one per output port) that controls which queues of the ports are gated, triggered, hold request generation, and which ports change their Cut-Through mode setting.
+    uint8_t           gate_state;      ///< Bit mask, gate state of queue 0 to 7 (bit0:queue0, bit1:queue1, .., bit7:queue7). Value 0 is close, value 1 is open.
+    uint8_t           gpio_mask;       ///< Generic bits that control the output pins ETHSW_TDMAOUT0..3.
+    bool              interrupt;       ///< Indicates this entry generates an interrupt to the CPU when activated.
+    bool              hold_req;        ///< Preemption hold request. Generates a hold request to ports enabled in port_mask.
+    bool              gate_mode;       ///< Gate mode enable when set to 1.
+    bool              trigger_mode;    ///< Trigger mode enable when set to 1. GATE_MODE must be 0, otherwise, GATE_MODE has precedence.
+    bool              in_ct_ena;       ///< Input Cut-Through Enable.
+    bool              out_ct_ena;      ///< Output Cut-Through Enable.
+    bool              red_period;      ///< Period Color Control (for Profinet IRT)
+    bool              inc_crt1;        ///< Increment Control for Counter 1.
+    bool              inc_crt0;        ///< Increment Control for Counter 0.
+} ethsw_tdma_schedule_entry_t;
+
+/** TDMA GPIO operating mode */
+typedef enum e_ethsw_tdma_gpio_mode
+{
+    ETHSW_TDMA_GPIO_MODE_LEVEL  = 0,   ///< level mode
+    ETHSW_TDMA_GPIO_MODE_STROBE = 1,   ///< strobe mode
+    ETHSW_TDMA_GPIO_MODE_TOGGLE = 2,   ///< toggle mode
+} ethsw_tdma_gpio_mode_t;
+
+/** The parameter for set/get TDMA counter 1 function */
+typedef struct st_ethsw_tdma_counter1
+{
+    bool    write_value;               ///< When true, set value to counter 1
+    uint8_t value;                     ///< Setted counter 1 value
+    uint8_t max_value;                 ///< Maximum value of counter 1
+    bool    int_enable;                ///< When true, enable counter 1 interrupt
+    uint8_t int_value;                 ///< Counter 1 value when the interrupt occurred
+} ethsw_tdma_counter1_t;
+
+/** Timer enable/disable parameter */
+typedef struct st_ethsw_time_enable
+{
+    uint8_t time_num;                  ///< Timer number (range is 0..1).
+    bool    enable;                    ///< Enables/disables the timer specified by time_num. (true is enable, false is disable)
+    uint8_t clock_period;              ///< Clock period (specify 8).
+} ethsw_time_enable_t;
+
+/** Timer callback event */
+typedef enum e_ethsw_time_event
+{
+    ETHSW_TIME_CALLBACK_TIMESTAMP = 0x10,
+} ethsw_time_event_t;
+
+/** Timestamp parameter */
+typedef struct st_ethsw_timestamp
+{
+    uint8_t  time_num;                 ///< Timer number
+    uint32_t time_sec;                 ///< Second
+    uint32_t time_nsec;                ///< Nanosecond
+    uint32_t timestamp_id;             ///< Timeatamp ID
+} ethsw_timestamp_t;
+
+/** Transmit timestamp parameter */
+typedef struct st_ethsw_time_transmit
+{
+    ethsw_port_mask_t port_mask;          ///< Per Port Transmit Timestamp Capture Interrupt Enable.
+    ///< (Bit0=Port0, Bit1=Port1, Bit2=Port2)
+    void (* p_time_callback)(             ///< Pointer to the callback function that receives the
+        ethsw_time_event_t  event,        ///< Callback event
+        uint32_t            port,         ///< Port number
+        ethsw_timestamp_t * p_timestamp); ///< Pointer to the timestamp parameter.
+} ethsw_time_transmit_t;
+
+/** Peer delay info */
+typedef struct st_ethsw_time_peerdelay
+{
+    uint8_t  time_num;                 ///< Timer number
+    uint32_t peerdelay;                ///< Peer delay value
+} ethsw_time_peerdelay_t;
+
+/** offset correction parameter */
+typedef struct st_ethsw_time_offset_correction
+{
+    uint8_t  time_num;                 ///< Timer number (0 or 1)
+    uint8_t  offs_inc;                 ///< Offset correction increment
+    uint32_t offs_corr;                ///< Offset correction counter
+    uint32_t offset;                   ///< Offset correction value
+} ethsw_time_offset_correction_t;
+
+/** Rate correction parameter */
+typedef struct st_ethsw_time_rate_correction
+{
+    uint8_t time_num;                  ///< timer number (0 or 1)
+    int32_t rate;                      ///< Correction rate
+} ethsw_time_rate_correction_t;
+
+/* Domain parameter */
+typedef struct st_ethsw_time_domain
+{
+    uint8_t time_num;                  ///< Timer number
+    uint8_t domain_num;                ///< Domain number
+} ethsw_time_domain_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const ether_switch_api_t g_ether_switch_on_ethsw;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Public Function Prototypes
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_Open(ether_switch_ctrl_t * const p_ctrl, ether_switch_cfg_t const * const p_cfg);
+fsp_err_t R_ETHSW_Close(ether_switch_ctrl_t * const p_ctrl);
+
+fsp_err_t R_ETHSW_SpeedCfg(ether_switch_ctrl_t * const p_ctrl, uint32_t const port, ethsw_link_speed_t const speed);
+
+/* Forwarding extension API function */
+fsp_err_t R_ETHSW_MacTableSet(ether_switch_ctrl_t * const    p_ctrl,
+                              ethsw_mac_table_entry_addr_t * p_mac_entry_addr,
+                              ethsw_mac_table_entry_info_t * p_mac_entry_info);
+fsp_err_t R_ETHSW_MacTableGet(ether_switch_ctrl_t * const    p_ctrl,
+                              ethsw_mac_table_entry_addr_t * p_mac_entry_addr,
+                              ethsw_mac_table_entry_info_t * p_mac_entry_info);
+fsp_err_t R_ETHSW_MacTableConfigSet(ether_switch_ctrl_t * const p_ctrl, ethsw_mac_table_config_t * p_mac_table_config);
+fsp_err_t R_ETHSW_MacTableClear(ether_switch_ctrl_t * const p_ctrl, ethsw_mac_table_clear_mode_t * p_mac_table_clear);
+fsp_err_t R_ETHSW_LearningSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool enable);
+fsp_err_t R_ETHSW_PortForwardAdd(ether_switch_ctrl_t * const p_ctrl, uint32_t port);
+fsp_err_t R_ETHSW_PortForwardDel(ether_switch_ctrl_t * const p_ctrl, uint32_t port);
+fsp_err_t R_ETHSW_FloodUnknownSet(ether_switch_ctrl_t * const p_ctrl, ethsw_flood_unknown_config_t * p_flood_config);
+
+/* MAC extension API function */
+fsp_err_t R_ETHSW_LinkStateGet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_link_status_t * p_state_link);
+fsp_err_t R_ETHSW_FrameSizeMaxSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint32_t frame_size_max);
+
+/* DLR extension API function */
+fsp_err_t R_ETHSW_DlrInitSet(ether_switch_ctrl_t * const p_ctrl, ethsw_dlr_init_t * p_dlr_init);
+fsp_err_t R_ETHSW_DlrUninitSet(ether_switch_ctrl_t * const p_ctrl);
+fsp_err_t R_ETHSW_DlrEnableSet(ether_switch_ctrl_t * const p_ctrl);
+fsp_err_t R_ETHSW_DlrDisableSet(ether_switch_ctrl_t * const p_ctrl);
+fsp_err_t R_ETHSW_DlrBeaconStateGet(ether_switch_ctrl_t * const p_ctrl,
+                                    uint32_t                    port,
+                                    ethsw_dlr_beacon_state_t  * p_beacon_state);
+fsp_err_t R_ETHSW_DlrNodeStateGet(ether_switch_ctrl_t * const p_ctrl, ethsw_dlr_node_state_t * p_node_state);
+fsp_err_t R_ETHSW_DlrSvIpGet(ether_switch_ctrl_t * const p_ctrl, uint32_t * p_ip_addr);
+fsp_err_t R_ETHSW_DlrSvPriorityGet(ether_switch_ctrl_t * const p_ctrl, uint8_t * p_priority);
+fsp_err_t R_ETHSW_DlrVlanGet(ether_switch_ctrl_t * const p_ctrl, uint16_t * p_vlan_info);
+fsp_err_t R_ETHSW_DlrSvMacGet(ether_switch_ctrl_t * const p_ctrl, ethsw_mac_addr_t * p_addr_mac);
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+
+/* Extended Frame Parser (EFP) extension API function */
+fsp_err_t R_ETHSW_EfpInitilizeAsiTable(ether_switch_ctrl_t * const p_ctrl, ethsw_port_mask_t port_mask);
+fsp_err_t R_ETHSW_EfpAsiTableSet(ether_switch_ctrl_t * const p_ctrl, ethsw_efp_asi_t * p_efp_asi_entry);
+fsp_err_t R_ETHSW_EfpAsiTableDelete(ether_switch_ctrl_t * const p_ctrl,
+                                    uint32_t                    port,
+                                    ethsw_mac_addr_t          * dmaci,
+                                    ethsw_vlan_vid_t          * vidi);
+fsp_err_t R_ETHSW_EfpVlanVerificationModeSet(ether_switch_ctrl_t * const          p_ctrl,
+                                             uint32_t                             port,
+                                             ethsw_vlan_input_verification_mode_t vicm);
+fsp_err_t R_ETHSW_EfpPriorityRegenerationSet(ether_switch_ctrl_t * const         p_ctrl,
+                                             uint32_t                            port,
+                                             ethsw_efp_priority_regeneration_t * p_pri_regen);
+fsp_err_t R_ETHSW_EfpFilterTableSet(ether_switch_ctrl_t * const     p_ctrl,
+                                    uint32_t                        port,
+                                    uint32_t                        sid,
+                                    ethsw_efp_qci_stream_filter_t * p_flt_entry);
+fsp_err_t R_ETHSW_EfpQsfTableEnable(ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint32_t sid, bool qste);
+fsp_err_t R_ETHSW_EfpGatingCheckSet(ether_switch_ctrl_t * const p_ctrl,
+                                    uint32_t                    port,
+                                    uint32_t                    sid,
+                                    ethsw_efp_gating_check_t  * p_gt_chk);
+fsp_err_t R_ETHSW_EfpSDUmaxVerificationSet(ether_switch_ctrl_t * const        p_ctrl,
+                                           uint32_t                           port,
+                                           uint32_t                           sid,
+                                           ethsw_efp_sdu_max_verification_t * p_sdumax);
+fsp_err_t R_ETHSW_EfpFlowMeteringSet(ether_switch_ctrl_t * const p_ctrl,
+                                     uint32_t                    port,
+                                     uint32_t                    sid,
+                                     ethsw_efp_flow_metering_t * p_meter);
+fsp_err_t R_ETHSW_EfpInterruptEnable(ether_switch_ctrl_t * const    p_ctrl,
+                                     uint32_t                       port,
+                                     ethsw_efp_interrupt_source_t * p_conf,
+                                     void (                       * p_efp_callback_func)(uint32_t,
+                                                                                         ethsw_efp_event_t));
+fsp_err_t R_ETHSW_EfpStatusGet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_efp_status_t * p_info);
+fsp_err_t R_ETHSW_EfpChannelEnable(ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool enable);
+
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+/* Rx Pattern Matcher extension API function */
+fsp_err_t R_ETHSW_RxPatternMatcherSet(ether_switch_ctrl_t * const  p_ctrl,
+                                      ethsw_rx_pattern_matcher_t * p_rx_pattern_matcher);
+fsp_err_t R_ETHSW_RxPatternMatcherCallback(
+    ether_switch_ctrl_t * const         p_ctrl,
+    void (                            * p_rx_pattern_callback_func)(
+        ethsw_rx_pattern_event_t        event,
+        ethsw_rx_pattern_event_data_t * p_data));
+
+/* Frame Preemption extension API function */
+fsp_err_t R_ETHSW_PreemptQueueSet(ether_switch_ctrl_t * const p_ctrl, ethsw_preempt_queue_t * p_preempt_queue);
+fsp_err_t R_ETHSW_PreemptPortControlConfigSet(ether_switch_ctrl_t * const        p_ctrl,
+                                              uint32_t                           port,
+                                              ethsw_preempt_port_ctrl_config_t * p_preempt_port_ctrl);
+fsp_err_t R_ETHSW_PreemptPortControlEnableSet(ether_switch_ctrl_t * const p_ctrl,
+                                              uint32_t                    port,
+                                              bool                        frame_preempt_enable);
+fsp_err_t R_ETHSW_PreemptHoldReqForceSet(ether_switch_ctrl_t * const p_ctrl,
+                                         ethsw_port_mask_t           holdreq_request_port_mask);
+fsp_err_t R_ETHSW_PreemptHoldReqReleaseSet(ether_switch_ctrl_t * const p_ctrl,
+                                           ethsw_port_mask_t           holdreq_release_port_mask);
+fsp_err_t R_ETHSW_PreemptStatusGet(ether_switch_ctrl_t * const p_ctrl,
+                                   uint32_t                    port,
+                                   ethsw_preempt_status_t    * p_preempt_status);
+
+/* MMCTL extension API function */
+fsp_err_t R_ETHSW_MmctlQgateSet(ether_switch_ctrl_t * const p_ctrl, ethsw_mmclt_qgate_t * p_mmctl_qgate);
+fsp_err_t R_ETHSW_MmctlPoolSizeSet(ether_switch_ctrl_t * const p_ctrl, ethsw_mmctl_pool_size_t * p_pool_size);
+fsp_err_t R_ETHSW_MmctlQueueAssignSet(ether_switch_ctrl_t * const p_ctrl, ethsw_mmctl_queue_assign_t * p_queue_assign);
+fsp_err_t R_ETHSW_MmctlYellowLengthSet(ether_switch_ctrl_t * const p_ctrl,
+                                       uint32_t                    port,
+                                       ethsw_yellow_length_t     * p_yellow_length);
+fsp_err_t R_ETHSW_QueueFlushEventSet(ether_switch_ctrl_t * const p_ctrl,
+                                     ethsw_queue_flush_event_t * p_queue_flush_event);
+fsp_err_t R_ETHSW_MmctlQueueClosedNonemptyStatusGet(ether_switch_ctrl_t * const      p_ctrl,
+                                                    ethsw_mmctl_qclosed_nonempty_t * p_qclosed_nonempty);
+
+/* Statistics extension API function */
+fsp_err_t R_ETHSW_StatisticsSwitchGet(ether_switch_ctrl_t * const      p_ctrl,
+                                      bool                             clear,
+                                      ethsw_statistics_switch_base_t * p_statistics_switch);
+fsp_err_t R_ETHSW_StatisticsMacGet(ether_switch_ctrl_t * const p_ctrl,
+                                   uint32_t                    port,
+                                   ethsw_statistics_mac_t    * p_statistics_mac);
+fsp_err_t R_ETHSW_StatisticsMacClear(ether_switch_ctrl_t * const p_ctrl);
+
+#ifdef ETHSW_EFP_FEATURE_SUPPORTED
+fsp_err_t R_ETHSW_StatisticsEfpGet(ether_switch_ctrl_t * const p_ctrl,
+                                   uint32_t                    port,
+                                   ethsw_statistics_efp_t    * p_statistics_efp);
+
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+fsp_err_t R_ETHSW_Statistics8023brGet(ether_switch_ctrl_t * const p_ctrl,
+                                      uint32_t                    port,
+                                      bool                        clear,
+                                      ethsw_statistics_8023br_t * p_statistics_8023br);
+fsp_err_t R_ETHSW_StatisticsDlrGet(ether_switch_ctrl_t * const p_ctrl, ethsw_statistics_dlr_t * p_statistics_dlr);
+
+/* CQF extension API function */
+fsp_err_t R_ETHSW_CqfEnableSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_cqf_enable_t * p_cqf_enable);
+
+/* Snooping extension API function */
+fsp_err_t R_ETHSW_SnoopParserSet(ether_switch_ctrl_t * const p_ctrl, ethsw_snoop_parser_config_t * p_parser_cnf);
+fsp_err_t R_ETHSW_SnoopArithSet(ether_switch_ctrl_t * const p_ctrl, ethsw_snoop_arith_config_t * p_arith_cnf);
+
+/* EEE extension API function */
+fsp_err_t R_ETHSW_EeeSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_eee_t * p_cnf_eee);
+
+/* Storm protection extension API function */
+fsp_err_t R_ETHSW_StormTimeSet(ether_switch_ctrl_t * const p_ctrl, uint16_t storm_time);
+fsp_err_t R_ETHSW_BcastLimitSet(ether_switch_ctrl_t * const p_ctrl, uint16_t storm_frames);
+fsp_err_t R_ETHSW_McastLimitSet(ether_switch_ctrl_t * const p_ctrl, uint16_t storm_frames);
+fsp_err_t R_ETHSW_TxRateSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, float rate);
+
+/* QoS extension API function */
+fsp_err_t R_ETHSW_QosModeSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_qos_mode_t * p_qos_mode);
+fsp_err_t R_ETHSW_QosPrioValnSet(ether_switch_ctrl_t * const p_ctrl,
+                                 uint32_t                    port,
+                                 ethsw_qos_prio_vlan_t     * p_qos_prio_vlan);
+fsp_err_t R_ETHSW_QosPrioIpSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_qos_prio_ip_t * p_qos_prio_ip);
+fsp_err_t R_ETHSW_QosPrioTypeSet(ether_switch_ctrl_t * const p_ctrl, ethsw_qos_prio_type_t * p_qos_prio_ethtype);
+
+/* Mirroring extension API function */
+fsp_err_t R_ETHSW_MirrorSet(ether_switch_ctrl_t * const p_ctrl, ethsw_mirror_conf_t * p_mirror_conf);
+
+/* Cut Through extension API function */
+fsp_err_t R_ETHSW_CtEnableSet(ether_switch_ctrl_t * const p_ctrl, ethsw_port_mask_t port_mask);
+fsp_err_t R_ETHSW_CtDelaySet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint32_t ct_delay);
+
+/* Pulse Generator extension API function */
+fsp_err_t R_ETHSW_PulseGeneratorInit(ether_switch_ctrl_t * const p_ctrl, uint32_t time_num);
+fsp_err_t R_ETHSW_PulseGeneratorSet(ether_switch_ctrl_t * const p_ctrl, ethsw_ts_pulse_generator_t * p_pulse);
+
+/* Bridge management extension API function */
+fsp_err_t R_ETHSW_PortAuthSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool auth_state);
+fsp_err_t R_ETHSW_PortCtrlDirSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool dir_state);
+fsp_err_t R_ETHSW_PortEapolSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool eapol_state);
+fsp_err_t R_ETHSW_BpduSet(ether_switch_ctrl_t * const p_ctrl, bool bpdu_state);
+
+/* VLAN management extension API function */
+fsp_err_t R_ETHSW_VlanDefaultSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint16_t vlan_id);
+fsp_err_t R_ETHSW_VlanPortAdd(ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint16_t vlan_id);
+fsp_err_t R_ETHSW_VlanPortRemove(ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint16_t vlan_id);
+fsp_err_t R_ETHSW_VlanInModeSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_vlan_in_mode_t vlan_in_mode);
+fsp_err_t R_ETHSW_VlanOutModeSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port,
+                                 ethsw_vlan_out_mode_t vlan_out_mode);
+fsp_err_t R_ETHSW_VlanVerifySet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool enable);
+fsp_err_t R_ETHSW_VlanDiscardUnknownSet(ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool enable);
+
+/* TDMA extension API function */
+fsp_err_t R_ETHSW_TdmaEnableSet(ether_switch_ctrl_t * const p_ctrl, ethsw_tdma_enable_t * p_tdma_enable);
+fsp_err_t R_ETHSW_TdmaScheduleSet(ether_switch_ctrl_t * const   p_ctrl,
+                                  ethsw_tdma_schedule_entry_t * p_tdma_schedule_entry,
+                                  uint16_t                      tdma_schedule_entry_count);
+fsp_err_t R_ETHSW_TdmaGpioModeSet(ether_switch_ctrl_t * const p_ctrl, uint8_t gpio_num,
+                                  ethsw_tdma_gpio_mode_t gpio_mode);
+fsp_err_t R_ETHSW_TdmaCounter0Set(ether_switch_ctrl_t * const p_ctrl, uint32_t tdma_counter0);
+fsp_err_t R_ETHSW_TdmaCounter0Get(ether_switch_ctrl_t * const p_ctrl, uint32_t * p_tdma_counter0);
+fsp_err_t R_ETHSW_TdmaCounter1Set(ether_switch_ctrl_t * const p_ctrl, ethsw_tdma_counter1_t * p_tdma_counter1);
+fsp_err_t R_ETHSW_TdmaCounter1Get(ether_switch_ctrl_t * const p_ctrl, ethsw_tdma_counter1_t * p_tdma_counter1);
+fsp_err_t R_ETHSW_TdmaHoldReqClear(ether_switch_ctrl_t * const p_ctrl);
+
+/* Timestamp extension API function */
+fsp_err_t R_ETHSW_TimeEnableSet(ether_switch_ctrl_t * const p_ctrl, ethsw_time_enable_t * p_time_enable);
+fsp_err_t R_ETHSW_TimeTransmitTimestampSet(ether_switch_ctrl_t * const p_ctrl, ethsw_time_transmit_t * p_time_transmit);
+fsp_err_t R_ETHSW_TimeValueSet(ether_switch_ctrl_t * const p_ctrl, ethsw_timestamp_t * p_timestamp);
+fsp_err_t R_ETHSW_TimeValueGet(ether_switch_ctrl_t * const p_ctrl, ethsw_timestamp_t * p_timestamp);
+fsp_err_t R_ETHSW_TimeValueGetAll(ether_switch_ctrl_t * const p_ctrl,
+                                  ethsw_timestamp_t         * p_timer0,
+                                  ethsw_timestamp_t         * p_timer1);
+fsp_err_t R_ETHSW_TimePeerDelaySet(ether_switch_ctrl_t * const p_ctrl,
+                                   uint32_t                    port,
+                                   ethsw_time_peerdelay_t    * p_peerdelay);
+fsp_err_t R_ETHSW_TimeOffsetSet(ether_switch_ctrl_t * const p_ctrl, ethsw_time_offset_correction_t * p_offset);
+fsp_err_t R_ETHSW_TimeRateSet(ether_switch_ctrl_t * const p_ctrl, ethsw_time_rate_correction_t * p_rate);
+fsp_err_t R_ETHSW_TimeDomainSet(ether_switch_ctrl_t * const p_ctrl, ethsw_time_domain_t * p_domain);
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ETHSW)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // R_ETHSW_H
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_gmac.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_gmac.h
new file mode 100644
index 00000000..6b34afbc
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_gmac.h
@@ -0,0 +1,235 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @addtogroup ETHER
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ETHER_H
+#define R_ETHER_H
+
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_ether_cfg.h"
+#include "r_ether_api.h"
+#ifdef GMAC_IMPLEMENT_ETHSW
+ #include "r_ethsw.h"
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef enum e_gmac_port_mask
+{
+    GMAC_PORT_MASK_0   = (1U << 0),
+    GMAC_PORT_MASK_1   = (1U << 1),
+    GMAC_PORT_MASK_2   = (1U << 2),
+    GMAC_PORT_MASK_ALL = (GMAC_PORT_MASK_0 | GMAC_PORT_MASK_1 | GMAC_PORT_MASK_2)
+} gmac_port_mask_t;
+
+typedef enum e_gmac_link_change
+{
+    GMAC_LINK_CHANGE_NO_CHANGE = 0,    ///< Link status is no change
+    GMAC_LINK_CHANGE_LINK_DOWN = 1,    ///< Link status changes to down
+    GMAC_LINK_CHANGE_LINK_UP   = 2,    ///< Link status changes to up
+} gmac_link_change_t;
+
+typedef enum e_gmac_magic_packet
+{
+    GMAC_MAGIC_PACKET_NOT_DETECTED = 0, ///< Magic packet is not detected
+    GMAC_MAGIC_PACKET_DETECTING    = 1, ///< Magic packet is detecting
+    GMAC_MAGIC_PACKET_DETECTED     = 2, ///< Magic packet is detected
+} gmac_magic_packet_t;
+
+/** GMAC descriptor as defined in the hardware manual. */
+typedef struct st_gmac_instance_descriptor
+{
+    volatile uint32_t des0;            ///< TDES0/RDES0
+    volatile uint32_t des1;            ///< TDES1/RDES1
+    volatile uint32_t des2;            ///< TDES2/RDES2
+    volatile uint32_t des3;            ///< TDES3/RDES3
+} gmac_instance_descriptor_t;
+
+typedef enum e_gmac_phylink
+{
+    GMAC_PHYLINK_DISABLE = 0,          ///< Disable
+    GMAC_PHYLINK_ENABLE  = 1           ///< Enable
+} gmac_phylink_t;
+
+typedef struct st_gmac_extend_cfg
+{
+    gmac_instance_descriptor_t * p_rx_descriptors;                              ///< Receive descriptor buffer pool
+    gmac_instance_descriptor_t * p_tx_descriptors;                              ///< Transmit descriptor buffer pool
+
+    gmac_phylink_t phylink;                                                     ///< Enable or disable link status change by PHYLINK
+
+    IRQn_Type pmt_irq;                                                          ///< PMT_interrupt number
+    uint32_t  pmt_interrupt_priority;                                           ///< PMT_interrupt priority
+
+    ether_phy_instance_t const *(*pp_phy_instance)[BSP_FEATURE_GMAC_MAX_PORTS]; ///< Pointer to ETHER_PHY instance
+#ifdef GMAC_IMPLEMENT_ETHSW
+    ether_switch_instance_t const * p_ethsw_instance;                           ///< Pointer to ETHER_SWITCH instance
+#endif // GMAC_IMPLEMENT_ETHSW
+
+    uint8_t * p_mac_address1;                                                   ///< Pointer of MAC address 1
+    uint8_t * p_mac_address2;                                                   ///< Pointer of MAC address 2
+} gmac_extend_cfg_t;
+
+/** ETHER control block. DO NOT INITIALIZE.  Initialization occurs when @ref ether_api_t::open is called. */
+typedef struct st_gmac_instance_ctrl
+{
+    uint32_t open;                                ///< Used to determine if the channel is configured
+
+    /* Configuration of ethernet module. */
+    ether_cfg_t const * p_gmac_cfg;               ///< Pointer to initial configurations.
+
+    /* Buffer of ethernet module. */
+    gmac_instance_descriptor_t * p_rx_descriptor; ///< Pointer to the currently referenced transmit descriptor
+    gmac_instance_descriptor_t * p_tx_descriptor; ///< Pointer to the currently referenced receive descriptor
+
+    /* Interface for PHY-LSI chip. */
+    void * p_reg_gmac;                            ///< Base register of ethernet controller for this channel
+
+    /* Link status */
+    gmac_port_mask_t link_status;                 ///< link status by callback from ethsw (bit0:port0, bit1:port1,..)
+
+    /* Status of ethernet driver. */
+    gmac_port_mask_t previous_link_status;        ///< Previous link status (bit0:port0, bit1:port1,..)
+
+    uint32_t link_speed_duplex;                   ///< Link speed & duplex
+
+    gmac_magic_packet_t magic_packet;             ///< status of magic packet detection
+
+    gmac_port_mask_t link_establish_status;       ///< Current Link status (bit0:port0, bit1:port1,..)
+
+    uint32_t local_pause_bits;                    ///< Local pause bits got from PHY.
+    uint32_t partner_pause_bits;                  ///< Partner pause bits got from PHY.
+
+    /* Pointer to callback and optional working memory */
+    void (* p_callback)(ether_callback_args_t *);
+    ether_callback_args_t * p_callback_memory;
+
+    /* Pointer to context to be passed into callback function */
+    void const * p_context;
+} gmac_instance_ctrl_t;
+
+/*
+ * PauseMaskE, PauseValE and pause_resolutionS are use to create
+ * PAUSE resolution Table 28B-3 in IEEE 802.3-2008 standard.
+ */
+typedef enum e_gmac_pause_mask
+{
+    GMAC_PAUSE_MASK0,
+    GMAC_PAUSE_MASK1,
+    GMAC_PAUSE_MASK2,
+    GMAC_PAUSE_MASK3,
+    GMAC_PAUSE_MASK4,
+    GMAC_PAUSE_MASK5,
+    GMAC_PAUSE_MASK6,
+    GMAC_PAUSE_MASK7,
+    GMAC_PAUSE_MASK8,
+    GMAC_PAUSE_MASK9,
+    GMAC_PAUSE_MASKA,
+    GMAC_PAUSE_MASKB,
+    GMAC_PAUSE_MASKC,
+    GMAC_PAUSE_MASKD,
+    GMAC_PAUSE_MASKE,
+    GMAC_PAUSE_MASKF
+} gmac_pause_mask_t;
+
+typedef enum e_gmac_pause_val
+{
+    GMAC_PAUSE_VAL0,
+    GMAC_PAUSE_VAL1,
+    GMAC_PAUSE_VAL2,
+    GMAC_PAUSE_VAL3,
+    GMAC_PAUSE_VAL4,
+    GMAC_PAUSE_VAL5,
+    GMAC_PAUSE_VAL6,
+    GMAC_PAUSE_VAL7,
+    GMAC_PAUSE_VAL8,
+    GMAC_PAUSE_VAL9,
+    GMAC_PAUSE_VALA,
+    GMAC_PAUSE_VALB,
+    GMAC_PAUSE_VALC,
+    GMAC_PAUSE_VALD,
+    GMAC_PAUSE_VALE,
+    GMAC_PAUSE_VALF
+} gmac_pause_val_t;
+
+typedef struct st_gmac_pause_resolution
+{
+    gmac_pause_mask_t mask;
+    gmac_pause_val_t  value;
+    uint8_t           transmit;
+    uint8_t           receive;
+} gmac_pause_resolution_t;
+
+/** Link status of each port */
+typedef enum e_gmac_link_status
+{
+    GMAC_LINK_STATUS_DOWN  = 0,        ///< Link down
+    GMAC_LINK_STATUS_UP    = 1,        ///< Link up
+    GMAC_LINK_STATUS_READY = 2,        ///< Link establishment
+} gmac_link_status_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const ether_api_t g_ether_on_gmac;
+
+/** @endcond */
+
+/**********************************************************************************************************************
+ * Public Function Prototypes
+ **********************************************************************************************************************/
+fsp_err_t R_GMAC_Open(ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p_cfg);
+
+fsp_err_t R_GMAC_Close(ether_ctrl_t * const p_ctrl);
+
+fsp_err_t R_GMAC_Read(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t * const length_bytes);
+
+fsp_err_t R_GMAC_BufferRelease(ether_ctrl_t * const p_ctrl);
+
+fsp_err_t R_GMAC_RxBufferUpdate(ether_ctrl_t * const p_ctrl, void * const p_buffer);
+
+fsp_err_t R_GMAC_Write(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length);
+
+fsp_err_t R_GMAC_LinkProcess(ether_ctrl_t * const p_ctrl);
+
+fsp_err_t R_GMAC_GetLinkStatus(ether_ctrl_t * const p_ctrl, uint8_t port, gmac_link_status_t * p_status);
+
+fsp_err_t R_GMAC_WakeOnLANEnable(ether_ctrl_t * const p_ctrl);
+
+fsp_err_t R_GMAC_TxStatusGet(ether_ctrl_t * const p_ctrl, void * const p_buffer_address);
+
+fsp_err_t R_GMAC_CallbackSet(ether_ctrl_t * const          p_ctrl,
+                             void (                      * p_callback)(ether_callback_args_t *),
+                             void const * const            p_context,
+                             ether_callback_args_t * const p_callback_memory);
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ETHER)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // R_ETHER_H
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_gpt.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_gpt.h
new file mode 100644
index 00000000..bbec8468
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_gpt.h
@@ -0,0 +1,520 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef R_GPT_H
+#define R_GPT_H
+
+/*******************************************************************************************************************//**
+ * @addtogroup GPT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_timer_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Values to assign to GTUPSR, GTDNSR registers to determine phase counting mode. */
+#define GPT_PHASE_COUNTING_MODE_1_UP      (0x00006900U)
+#define GPT_PHASE_COUNTING_MODE_1_DN      (0x00009600U)
+#define GPT_PHASE_COUNTING_MODE_200_UP    (0x00000800U)
+#define GPT_PHASE_COUNTING_MODE_200_DN    (0x00000400U)
+#define GPT_PHASE_COUNTING_MODE_201_UP    (0x00000200U)
+#define GPT_PHASE_COUNTING_MODE_201_DN    (0x00000100U)
+#define GPT_PHASE_COUNTING_MODE_210_UP    (0x00000A00U)
+#define GPT_PHASE_COUNTING_MODE_210_DN    (0x00000500U)
+#define GPT_PHASE_COUNTING_MODE_300_UP    (0x00000800U)
+#define GPT_PHASE_COUNTING_MODE_300_DN    (0x00008000U)
+#define GPT_PHASE_COUNTING_MODE_301_UP    (0x00000200U)
+#define GPT_PHASE_COUNTING_MODE_301_DN    (0x00002000U)
+#define GPT_PHASE_COUNTING_MODE_310_UP    (0x00000A00U)
+#define GPT_PHASE_COUNTING_MODE_310_DN    (0x0000A000U)
+#define GPT_PHASE_COUNTING_MODE_4_UP      (0x00006000U)
+#define GPT_PHASE_COUNTING_MODE_4_DN      (0x00009000U)
+#define GPT_PHASE_COUNTING_MODE_50_UP     (0x00000C00U)
+#define GPT_PHASE_COUNTING_MODE_50_DN     (0x00000000U)
+#define GPT_PHASE_COUNTING_MODE_51_UP     (0x0000C000U)
+#define GPT_PHASE_COUNTING_MODE_51_DN     (0x00000000U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */
+typedef enum e_gpt_io_pin
+{
+    GPT_IO_PIN_GTIOCA            = 0,  ///< GTIOCA
+    GPT_IO_PIN_GTIOCB            = 1,  ///< GTIOCB
+    GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2,  ///< GTIOCA and GTIOCB
+} gpt_io_pin_t;
+
+/** Level of GPT pin */
+typedef enum e_gpt_pin_level
+{
+    GPT_PIN_LEVEL_LOW  = 0,            ///< Pin level low
+    GPT_PIN_LEVEL_HIGH = 1,            ///< Pin level high
+} gpt_pin_level_t;
+
+#if 18U == BSP_FEATURE_GPT_CHANNEL
+typedef enum e_gpt_channel
+{
+    GPT_CHANNEL_UNIT0_0 = 0,           ///< Unit0 channel0
+    GPT_CHANNEL_UNIT0_1 = 1,           ///< Unit0 channel1
+    GPT_CHANNEL_UNIT0_2 = 2,           ///< Unit0 channel2
+    GPT_CHANNEL_UNIT0_3 = 3,           ///< Unit0 channel3
+    GPT_CHANNEL_UNIT0_4 = 4,           ///< Unit0 channel4
+    GPT_CHANNEL_UNIT0_5 = 5,           ///< Unit0 channel5
+    GPT_CHANNEL_UNIT0_6 = 6,           ///< Unit0 channel6
+    GPT_CHANNEL_UNIT1_0 = 7,           ///< Unit1 channel0
+    GPT_CHANNEL_UNIT1_1 = 8,           ///< Unit1 channel1
+    GPT_CHANNEL_UNIT1_2 = 9,           ///< Unit1 channel2
+    GPT_CHANNEL_UNIT1_3 = 10,          ///< Unit1 channel3
+    GPT_CHANNEL_UNIT1_4 = 11,          ///< Unit1 channel4
+    GPT_CHANNEL_UNIT1_5 = 12,          ///< Unit1 channel5
+    GPT_CHANNEL_UNIT1_6 = 13,          ///< Unit1 channel6
+    GPT_CHANNEL_UNIT2_0 = 14,          ///< Unit2 channel0
+    GPT_CHANNEL_UNIT2_1 = 15,          ///< Unit2 channel1
+    GPT_CHANNEL_UNIT2_2 = 16,          ///< Unit2 channel2
+    GPT_CHANNEL_UNIT2_3 = 17,          ///< Unit2 channel3
+} gpt_channel_t;
+#elif 56U == BSP_FEATURE_GPT_CHANNEL
+typedef enum e_gpt_channel
+{
+    GPT_CHANNEL_UNIT0_0  = 0,          ///< Unit0 channel0
+    GPT_CHANNEL_UNIT0_1  = 1,          ///< Unit0 channel1
+    GPT_CHANNEL_UNIT0_2  = 2,          ///< Unit0 channel2
+    GPT_CHANNEL_UNIT0_3  = 3,          ///< Unit0 channel3
+    GPT_CHANNEL_UNIT0_4  = 4,          ///< Unit0 channel4
+    GPT_CHANNEL_UNIT1_0  = 5,          ///< Unit1 channel0
+    GPT_CHANNEL_UNIT1_1  = 6,          ///< Unit1 channel1
+    GPT_CHANNEL_UNIT1_2  = 7,          ///< Unit1 channel2
+    GPT_CHANNEL_UNIT1_3  = 8,          ///< Unit1 channel3
+    GPT_CHANNEL_UNIT1_4  = 9,          ///< Unit1 channel4
+    GPT_CHANNEL_UNIT2_0  = 10,         ///< Unit2 channel0
+    GPT_CHANNEL_UNIT2_1  = 11,         ///< Unit2 channel1
+    GPT_CHANNEL_UNIT2_2  = 12,         ///< Unit2 channel2
+    GPT_CHANNEL_UNIT2_3  = 13,         ///< Unit2 channel3
+    GPT_CHANNEL_UNIT2_4  = 14,         ///< Unit2 channel4
+    GPT_CHANNEL_UNIT3_0  = 15,         ///< Unit3 channel0
+    GPT_CHANNEL_UNIT3_1  = 16,         ///< Unit3 channel1
+    GPT_CHANNEL_UNIT3_2  = 17,         ///< Unit3 channel2
+    GPT_CHANNEL_UNIT3_3  = 18,         ///< Unit3 channel3
+    GPT_CHANNEL_UNIT3_4  = 19,         ///< Unit3 channel4
+    GPT_CHANNEL_UNIT4_0  = 20,         ///< Unit4 channel0
+    GPT_CHANNEL_UNIT4_1  = 21,         ///< Unit4 channel1
+    GPT_CHANNEL_UNIT4_2  = 22,         ///< Unit4 channel2
+    GPT_CHANNEL_UNIT4_3  = 23,         ///< Unit4 channel3
+    GPT_CHANNEL_UNIT4_4  = 24,         ///< Unit4 channel4
+    GPT_CHANNEL_UNIT5_0  = 25,         ///< Unit5 channel0
+    GPT_CHANNEL_UNIT5_1  = 26,         ///< Unit5 channel1
+    GPT_CHANNEL_UNIT5_2  = 27,         ///< Unit5 channel2
+    GPT_CHANNEL_UNIT5_3  = 28,         ///< Unit5 channel3
+    GPT_CHANNEL_UNIT5_4  = 29,         ///< Unit5 channel4
+    GPT_CHANNEL_UNIT6_0  = 30,         ///< Unit6 channel0
+    GPT_CHANNEL_UNIT6_1  = 31,         ///< Unit6 channel1
+    GPT_CHANNEL_UNIT6_2  = 32,         ///< Unit6 channel2
+    GPT_CHANNEL_UNIT6_3  = 33,         ///< Unit6 channel3
+    GPT_CHANNEL_UNIT6_4  = 34,         ///< Unit6 channel4
+    GPT_CHANNEL_UNIT7_0  = 35,         ///< Unit7 channel0
+    GPT_CHANNEL_UNIT7_1  = 36,         ///< Unit7 channel1
+    GPT_CHANNEL_UNIT7_2  = 37,         ///< Unit7 channel2
+    GPT_CHANNEL_UNIT7_3  = 38,         ///< Unit7 channel3
+    GPT_CHANNEL_UNIT7_4  = 39,         ///< Unit7 channel4
+    GPT_CHANNEL_UNIT8_0  = 40,         ///< Unit8 channel0
+    GPT_CHANNEL_UNIT8_1  = 41,         ///< Unit8 channel1
+    GPT_CHANNEL_UNIT8_2  = 42,         ///< Unit8 channel2
+    GPT_CHANNEL_UNIT8_3  = 43,         ///< Unit8 channel3
+    GPT_CHANNEL_UNIT8_4  = 44,         ///< Unit8 channel4
+    GPT_CHANNEL_UNIT9_0  = 45,         ///< Unit9 channel0
+    GPT_CHANNEL_UNIT9_1  = 46,         ///< Unit9 channel1
+    GPT_CHANNEL_UNIT9_2  = 47,         ///< Unit9 channel2
+    GPT_CHANNEL_UNIT9_3  = 48,         ///< Unit9 channel3
+    GPT_CHANNEL_UNIT9_4  = 49,         ///< Unit9 channel4
+    GPT_CHANNEL_UNIT9_5  = 50,         ///< Unit9 channel5
+    GPT_CHANNEL_UNIT9_6  = 51,         ///< Unit9 channel6
+    GPT_CHANNEL_UNIT10_0 = 52,         ///< Unit10 channel0
+    GPT_CHANNEL_UNIT10_1 = 53,         ///< Unit10 channel1
+    GPT_CHANNEL_UNIT10_2 = 54,         ///< Unit10 channel2
+    GPT_CHANNEL_UNIT10_3 = 55,         ///< Unit10 channel3
+} gpt_channel_t;
+#endif
+
+/** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent
+ * a bitmask. Multiple sources can be ORed together. */
+typedef enum e_gpt_source
+{
+    /** No active event sources. */
+    GPT_SOURCE_NONE = 0U,
+
+    /** Action performed on GTETRGA rising edge. **/
+    GPT_SOURCE_GTETRGA_RISING = (1U << 0),
+
+    /** Action performed on GTETRGA falling edge. **/
+    GPT_SOURCE_GTETRGA_FALLING = (1U << 1),
+
+    /** Action performed on GTETRGB rising edge. **/
+    GPT_SOURCE_GTETRGB_RISING = (1U << 2),
+
+    /** Action performed on GTETRGB falling edge. **/
+    GPT_SOURCE_GTETRGB_FALLING = (1U << 3),
+
+    /** Action performed on GTETRGC rising edge. **/
+    GPT_SOURCE_GTETRGC_RISING = (1U << 4),
+
+    /** Action performed on GTETRGC falling edge. **/
+    GPT_SOURCE_GTETRGC_FALLING = (1U << 5),
+
+    /** Action performed on GTETRGB rising edge. **/
+    GPT_SOURCE_GTETRGD_RISING = (1U << 6),
+
+    /** Action performed on GTETRGB falling edge. **/
+    GPT_SOURCE_GTETRGD_FALLING = (1U << 7),
+
+    /** Action performed when GTIOCA input rises while GTIOCB is low. **/
+    GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8),
+
+    /** Action performed when GTIOCA input rises while GTIOCB is high. **/
+    GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9),
+
+    /** Action performed when GTIOCA input falls while GTIOCB is low. **/
+    GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10),
+
+    /** Action performed when GTIOCA input falls while GTIOCB is high. **/
+    GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11),
+
+    /** Action performed when GTIOCB input rises while GTIOCA is low. **/
+    GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12),
+
+    /** Action performed when GTIOCB input rises while GTIOCA is high. **/
+    GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13),
+
+    /** Action performed when GTIOCB input falls while GTIOCA is low. **/
+    GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14),
+
+    /** Action performed when GTIOCB input falls while GTIOCA is high. **/
+    GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15),
+
+    /** Action performed on ELC GPTA event. **/
+    GPT_SOURCE_GPT_A = (1U << 16),
+
+    /** Action performed on ELC GPTB event. **/
+    GPT_SOURCE_GPT_B = (1U << 17),
+
+    /** Action performed on ELC GPTC event. **/
+    GPT_SOURCE_GPT_C = (1U << 18),
+
+    /** Action performed on ELC GPTD event. **/
+    GPT_SOURCE_GPT_D = (1U << 19),
+
+    /** Action performed on ELC GPTE event. **/
+    GPT_SOURCE_GPT_E = (1U << 20),
+
+    /** Action performed on ELC GPTF event. **/
+    GPT_SOURCE_GPT_F = (1U << 21),
+
+    /** Action performed on ELC GPTG event. **/
+    GPT_SOURCE_GPT_G = (1U << 22),
+
+    /** Action performed on ELC GPTH event. **/
+    GPT_SOURCE_GPT_H = (1U << 23),
+} gpt_source_t;
+
+/** Configurations for output pins. */
+typedef struct s_gpt_output_pin
+{
+    bool            output_enabled;    ///< Set to true to enable output, false to disable output
+    gpt_pin_level_t stop_level;        ///< Select a stop level from ::gpt_pin_level_t
+} gpt_output_pin_t;
+
+/** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB.
+ *   The noise filter samples the external signal at intervals of the PCLK divided by one of the values.
+ *   When 3 consecutive samples are at the same level (high or low), then that level is passed on as
+ *   the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section.
+ */
+typedef enum e_gpt_capture_filter
+{
+    GPT_CAPTURE_FILTER_NONE         = 0U, ///< None - no filtering
+    GPT_CAPTURE_FILTER_PCLKD_DIV_1  = 1U, ///< PCLK/1 - fast sampling
+    GPT_CAPTURE_FILTER_PCLKD_DIV_4  = 3U, ///< PCLK/4
+    GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16
+    GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling
+} gpt_capture_filter_t;
+
+/** Trigger options to start A/D conversion. */
+typedef enum e_gpt_adc_trigger
+{
+    GPT_ADC_TRIGGER_NONE                   = 0U,      ///< None - no output disable request
+    GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A   = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match
+    GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match
+    GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B   = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match
+    GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match
+} gpt_adc_trigger_t;
+
+/** POEG channel to link to this channel. */
+typedef enum e_gpt_poeg_link
+{
+    GPT_POEG_LINK_POEG0 = 0U,          ///< Link this GPT channel to POEG channel 0 (GTETRGA)
+    GPT_POEG_LINK_POEG1 = 1U,          ///< Link this GPT channel to POEG channel 1 (GTETRGB)
+    GPT_POEG_LINK_POEG2 = 2U,          ///< Link this GPT channel to POEG channel 2 (GTETRGC)
+    GPT_POEG_LINK_POEG3 = 3U,          ///< Link this GPT channel to POEG channel 3 (GTETRGD)
+} gpt_poeg_link_t;
+
+/** Select trigger to send output disable request to POEG. */
+typedef enum e_gpt_output_disable
+{
+    GPT_OUTPUT_DISABLE_NONE               = 0U,      ///< None - no output disable request
+    GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR    = 1U << 0, ///< Request output disable if a dead time error occurs
+    GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time
+    GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW  = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time
+} gpt_output_disable_t;
+
+/** Disable level options for GTIOC pins. */
+typedef enum e_gpt_gtioc_disable
+{
+    GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable
+    GPT_GTIOC_DISABLE_SET_HI_Z   = 1U, ///< Set GTIOC to high impedance when output is disabled
+    GPT_GTIOC_DISABLE_LEVEL_LOW  = 2U, ///< Set GTIOC level low when output is disabled
+    GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled
+} gpt_gtioc_disable_t;
+
+/** Trigger options to start A/D conversion. */
+typedef enum e_gpt_adc_compare_match
+{
+    GPT_ADC_COMPARE_MATCH_ADC_A = 0U,  ///< Set A/D conversion start request value for GPT A/D converter start request A
+    GPT_ADC_COMPARE_MATCH_ADC_B = 3U,  ///< Set A/D conversion start request value for GPT A/D converter start request B
+} gpt_adc_compare_match_t;
+
+/** Interrupt skipping modes */
+typedef enum e_gpt_interrupt_skip_source
+{
+    GPT_INTERRUPT_SKIP_SOURCE_NONE               = 0U, ///< Do not skip interrupts
+    GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts
+
+    /** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in
+     *  @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest
+     * interrupt. */
+    GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U,
+
+    /** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in
+     *  @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough
+     *  interrupt. */
+    GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U,
+} gpt_interrupt_skip_source_t;
+
+/** Number of interrupts to skip between events */
+typedef enum e_gpt_interrupt_skip_count
+{
+    GPT_INTERRUPT_SKIP_COUNT_0 = 0U,   ///< Do not skip interrupts
+    GPT_INTERRUPT_SKIP_COUNT_1,        ///< Skip one interrupt
+    GPT_INTERRUPT_SKIP_COUNT_2,        ///< Skip two interrupts
+    GPT_INTERRUPT_SKIP_COUNT_3,        ///< Skip three interrupts
+    GPT_INTERRUPT_SKIP_COUNT_4,        ///< Skip four interrupts
+    GPT_INTERRUPT_SKIP_COUNT_5,        ///< Skip five interrupts
+    GPT_INTERRUPT_SKIP_COUNT_6,        ///< Skip six interrupts
+    GPT_INTERRUPT_SKIP_COUNT_7,        ///< Skip seven interrupts
+
+    /** When setting GTIEITC */
+    GPT_INTERRUPT_SKIP_COUNT_8,        ///< Skip eight interrupts
+    GPT_INTERRUPT_SKIP_COUNT_9,        ///< Skip nine interrupts
+    GPT_INTERRUPT_SKIP_COUNT_10,       ///< Skip ten interrupts
+    GPT_INTERRUPT_SKIP_COUNT_11,       ///< Skip eleven interrupts
+    GPT_INTERRUPT_SKIP_COUNT_12,       ///< Skip twelve interrupts
+    GPT_INTERRUPT_SKIP_COUNT_13,       ///< Skip thiertenn interrupts
+    GPT_INTERRUPT_SKIP_COUNT_14,       ///< Skip fourteen interrupts
+    GPT_INTERRUPT_SKIP_COUNT_15,       ///< Skip fifteen interrupts
+} gpt_interrupt_skip_count_t;
+
+/** ADC events to skip during interrupt skipping */
+typedef enum e_gpt_interrupt_skip_adc
+{
+    GPT_INTERRUPT_SKIP_ADC_NONE    = 0U, ///< Do not skip ADC events
+    GPT_INTERRUPT_SKIP_ADC_A       = 1U, ///< Skip ADC A events
+    GPT_INTERRUPT_SKIP_ADC_B       = 4U, ///< Skip ADC B events
+    GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events
+} gpt_interrupt_skip_adc_t;
+
+/** extended interrupt skipping */
+typedef enum e_gpt_interrupt_skip_select
+{
+    GPT_INTERRUPT_SKIP_SELECT_NONE      = 0U, ///< Do not perform an extended interrupt skipping
+    GPT_INTERRUPT_SKIP_SELECT_EITCNT1   = 1U, ///< An interrupt is output in the period of EITCNT1[3:0] bits = 0000b.
+    GPT_INTERRUPT_SKIP_SELECT_EITCNT2   = 2U, ///< An interrupt is output in the period of EITCNT2[3:0] bits = 0000b.
+    GPT_INTERRUPT_SKIP_SELECT_EITCNT1_2 = 3U, ///< An interrupt is output in the period of EITCNT1[3:0] bits = 0000b and EITCNT2[3:0] bits = 0000b.
+
+    GPT_INTERRUPT_SKIP_SELECT_EITVTT1   = 5U, ///< An interrupt is output in the period of EITCNT1[3:0] bits = EIVTT1[3:0] bits.
+    GPT_INTERRUPT_SKIP_SELECT_EITVTT2   = 6U, ///< An interrupt is output in the period of EITCNT2[3:0] bits = EIVTT2[3:0] bits.
+    GPT_INTERRUPT_SKIP_SELECT_EITVTT1_2 = 7U, ///< An interrupt is output in the period of EITCNT1[3:0] bits = EIVTT1[3:0] bits and EITCNT2[3:0] bits = EIVTT2[3:0] bits.
+} gpt_interrupt_skip_select_t;
+
+#if 1U == BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE
+
+/** Input Capture Signal Select  */
+
+typedef enum e_gpt_input_signal_select
+{
+    GPT_INPUT_SIGNAL_SELECT_GTIOC00_4A_4B = (0U << 0U), ///< GTIOC00_4A / GTIOC00_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC00_3A_3B = (1U << 0U), ///< GTIOC00_3A / GTIOC00_3B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC01_4A_4B = (0U << 1U), ///< GTIOC01_4A / GTIOC01_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC01_3A_3B = (1U << 1U), ///< GTIOC01_3A / GTIOC01_3B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC02_4A_4B = (0U << 2U), ///< GTIOC02_4A / GTIOC02_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC02_3A_3B = (1U << 2U), ///< GTIOC02_3A / GTIOC02_3B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC03_4A_4B = (0U << 3U), ///< GTIOC03_4A / GTIOC03_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC03_3A_3B = (1U << 3U), ///< GTIOC03_3A / GTIOC03_3B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC04_4A_4B = (0U << 4U), ///< GTIOC04_4A / GTIOC04_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC04_3A_3B = (1U << 4U), ///< GTIOC04_3A / GTIOC04_3B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC05_4A_4B = (0U << 5U), ///< GTIOC05_4A / GTIOC05_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC05_3A_3B = (1U << 5U), ///< GTIOC05_3A / GTIOC05_3B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC06_4A_4B = (0U << 6U), ///< GTIOC06_4A / GTIOC06_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC06_3A_3B = (1U << 6U), ///< GTIOC06_3A / GTIOC06_3B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC07_4A_4B = (0U << 7U), ///< GTIOC07_4A / GTIOC07_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC07_3A_3B = (1U << 7U), ///< GTIOC07_3A / GTIOC07_3B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC08_4A_4B = (0U << 8U), ///< GTIOC08_4A / GTIOC08_4B input signals are selected
+    GPT_INPUT_SIGNAL_SELECT_GTIOC08_3A_3B = (1U << 8U), ///< GTIOC08_3A / GTIOC08_3B input signals are selected
+} gpt_input_signal_select_t;
+#endif
+
+/** Channel control block. DO NOT INITIALIZE.  Initialization occurs when @ref timer_api_t::open is called. */
+typedef struct st_gpt_instance_ctrl
+{
+    uint32_t            open;                     // Whether or not channel is open
+    const timer_cfg_t * p_cfg;                    // Pointer to initial configurations
+#if (1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE)
+    R_GPT0_Type * p_reg;                          // Base register for this channel
+#elif (2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE)
+    R_GPT00_0_Type * p_reg;                       // Base register for this channel
+#endif
+#if 1U == BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE
+    R_GPT_IC_Type * p_reg_com;                    // Base register for this channel(common ch)
+#endif
+    uint32_t        channel_mask;                 // Channel bitmask
+    timer_variant_t variant;                      // Timer variant
+
+    void (* p_callback)(timer_callback_args_t *); // Pointer to callback
+    timer_callback_args_t * p_callback_memory;    // Pointer to optional callback argument memory
+    void const            * p_context;            // Pointer to context to be passed into callback function
+} gpt_instance_ctrl_t;
+
+/** GPT extension for advanced PWM features. */
+typedef struct st_gpt_extended_pwm_cfg
+{
+    uint8_t                     trough_ipl;                 ///< Trough interrupt priority
+    IRQn_Type                   trough_irq;                 ///< Trough interrupt
+    gpt_poeg_link_t             poeg_link;                  ///< Select which POEG channel controls output disable for this GPT channel
+    gpt_output_disable_t        output_disable;             ///< Select which trigger sources request output disable from POEG
+    gpt_adc_trigger_t           adc_trigger;                ///< Select trigger sources to start A/D conversion
+    uint32_t                    dead_time_count_up;         ///< Set a dead time value for counting up
+    uint32_t                    dead_time_count_down;       ///< Set a dead time value for counting down
+    uint32_t                    adc_a_compare_match;        ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_A
+    uint32_t                    adc_b_compare_match;        ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_B
+    gpt_interrupt_skip_source_t interrupt_skip_source;      ///< Interrupt source to count for interrupt skipping
+    gpt_interrupt_skip_count_t  interrupt_skip_count;       ///< Number of interrupts to skip between events
+    gpt_interrupt_skip_adc_t    interrupt_skip_adc;         ///< ADC events to skip when interrupt skipping is enabled
+    gpt_interrupt_skip_source_t interrupt_skip_source_ext1; ///< Interrupt source to count for interrupt skipping(GTEITC.EIVTC1)
+    gpt_interrupt_skip_count_t  interrupt_skip_count_ext1;  ///< Number of interrupts to skip between events(GTEITC.EIVTT1)
+    gpt_interrupt_skip_source_t interrupt_skip_source_ext2; ///< Interrupt source to count for interrupt skipping(GTEITC.EIVTC2)
+    gpt_interrupt_skip_count_t  interrupt_skip_count_ext2;  ///< Number of interrupts to skip between events(GTEITC.EIVTT2)
+    gpt_interrupt_skip_select_t interrupt_skip_func_ovf;    ///< Extended Skipping Function Select(GTEITL1.EITVL)
+    gpt_interrupt_skip_select_t interrupt_skip_func_unf;    ///< Extended Skipping Function Select(GTEITL1.EITUL)
+    gpt_interrupt_skip_select_t interrupt_skip_func_adc_a;  ///< Extended Skipping Function Select(GTEITL2.EADTAL)
+    gpt_interrupt_skip_select_t interrupt_skip_func_adc_b;  ///< Extended Skipping Function Select(GTEITL2.EADTBL)
+    gpt_gtioc_disable_t         gtioca_disable_setting;     ///< Select how to configure GTIOCA when output is disabled
+    gpt_gtioc_disable_t         gtiocb_disable_setting;     ///< Select how to configure GTIOCB when output is disabled
+} gpt_extended_pwm_cfg_t;
+
+/** GPT extension configures the output pins for GPT. */
+typedef struct st_gpt_extended_cfg
+{
+    gpt_output_pin_t gtioca;           ///< Configuration for GPT I/O pin A
+    gpt_output_pin_t gtiocb;           ///< Configuration for GPT I/O pin B
+    gpt_source_t     start_source;     ///< Event sources that trigger the timer to start
+    gpt_source_t     stop_source;      ///< Event sources that trigger the timer to stop
+    gpt_source_t     clear_source;     ///< Event sources that trigger the timer to clear
+    gpt_source_t     capture_a_source; ///< Event sources that trigger capture of GTIOCA
+    gpt_source_t     capture_b_source; ///< Event sources that trigger capture of GTIOCB
+
+    /** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source
+     * and count_down_source, then the timer count source is PCLK.  */
+    gpt_source_t count_up_source;
+
+    /** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source
+     * and count_down_source, then the timer count source is PCLK.  */
+    gpt_source_t count_down_source;
+
+    gpt_capture_filter_t capture_filter_gtioca; ///< Debounce filter for GTIOCxA input signal pin.
+
+    gpt_capture_filter_t capture_filter_gtiocb; ///< Debounce filter for GTIOCxB input signal pin.
+
+    uint8_t capture_a_ipl;                      ///< Capture A interrupt priority
+    uint8_t capture_b_ipl;                      ///< Capture B interrupt priority
+    uint8_t dead_time_ipl;                      ///< Dead time error interrupt priority
+
+    uint8_t icds;                               ///< Input Capture Operation Select at Count Stop
+#if 1U == BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE
+    gpt_input_signal_select_t gtioc_isel;       ///< Input Capture Signal Select
+#endif
+    IRQn_Type capture_a_irq;                    ///< Capture A interrupt
+    IRQn_Type capture_b_irq;                    ///< Capture B interrupt
+    IRQn_Type dead_time_irq;                    ///< Dead time error interrupt
+
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg;   ///< Advanced PWM features, optional
+    uint8_t capture_a_source_select;            ///< Capture A interrupt source select
+    uint8_t capture_b_source_select;            ///< Capture B interrupt source select
+    uint8_t cycle_end_source_select;            ///< Cycle end interrupt source select
+    uint8_t dead_time_error_source_select;      ///< Dead time error interrupt source select
+    uint8_t trough_source_select;               ///< Trough interrupt source select
+} gpt_extended_cfg_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const timer_api_t g_timer_on_gpt;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Public APIs
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
+fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
+fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
+fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
+fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
+fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter);
+fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin);
+fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin);
+fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const    p_ctrl,
+                              gpt_adc_compare_match_t which_compare_match,
+                              uint32_t                compare_match_value);
+fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const          p_ctrl,
+                            void (                      * p_callback)(timer_callback_args_t *),
+                            void const * const            p_context,
+                            timer_callback_args_t * const p_callback_memory);
+fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl);
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup GPT)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ioport.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ioport.h
new file mode 100644
index 00000000..c593ac4f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_ioport.h
@@ -0,0 +1,198 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @addtogroup IOPORT
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_IOPORT_H
+#define R_IOPORT_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#include "r_ioport_api.h"
+#include "r_ioport_cfg.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define IOPORT_SINGLE_PORT_NUM    (4)
+#define IOPORT_PORT_GROUP_NUM     (2)
+#define IOPORT_PORT_GROUP_1       (0)
+#define IOPORT_PORT_GROUP_2       (1)
+#define IOPORT_SINGLE_PORT_0      (0)
+#define IOPORT_SINGLE_PORT_1      (1)
+#define IOPORT_SINGLE_PORT_2      (2)
+#define IOPORT_SINGLE_PORT_3      (3)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Pin selection for port group
+ *  @note Event link must be configured by the ELC
+ */
+typedef enum e_ioport_event_pin_selection
+{
+    IOPORT_EVENT_PIN_SELECTION_NONE  = 0x00, ///< No pin selection for port group
+    IOPORT_EVENT_PIN_SELECTION_PIN_0 = 0x01, ///< Select pin 0 to port group
+    IOPORT_EVENT_PIN_SELECTION_PIN_1 = 0x02, ///< Select pin 1 to port group
+    IOPORT_EVENT_PIN_SELECTION_PIN_2 = 0x04, ///< Select pin 2 to port group
+    IOPORT_EVENT_PIN_SELECTION_PIN_3 = 0x08, ///< Select pin 3 to port group
+    IOPORT_EVENT_PIN_SELECTION_PIN_4 = 0x10, ///< Select pin 4 to port group
+    IOPORT_EVENT_PIN_SELECTION_PIN_5 = 0x20, ///< Select pin 5 to port group
+    IOPORT_EVENT_PIN_SELECTION_PIN_6 = 0x40, ///< Select pin 6 to port group
+    IOPORT_EVENT_PIN_SELECTION_PIN_7 = 0x80, ///< Select pin 7 to port group
+} ioport_event_pin_selection_t;
+
+/** Port group operation
+ *  @note Event link must be configured by the ELC
+ */
+typedef enum e_ioport_event_output_operation
+{
+    IOPORT_EVENT_OUTPUT_OPERATION_LOW    = 0x0, ///< Set Low output to output operation
+    IOPORT_EVENT_OUTPUT_OPERATION_HIGH   = 0x1, ///< Set High output to output operation
+    IOPORT_EVENT_OUTPUT_OPERATION_TOGGLE = 0x2, ///< Set toggle output to output operation
+    IOPORT_EVENT_OUTPUT_OPERATION_BUFFER = 0x3, ///< Set buffer value output to output operation
+} ioport_event_output_operation_t;
+
+/** Input port group event control
+ *  @note Event link must be configured by the ELC
+ */
+typedef enum e_ioport_event_control
+{
+    IOPORT_EVENT_CONTROL_DISABLE = 0x0, ///< Disable function related with event link
+    IOPORT_EVENT_CONTROL_ENABLE  = 0x1, ///< Enable function related with event link
+} ioport_event_control_t;
+
+/** Single port event direction
+ *  @note Event link must be configured by the ELC
+ */
+typedef enum e_ioport_event_direction
+{
+    IOPORT_EVENT_DIRECTION_OUTPUT = 0x0, ///< Set output direction to single port
+    IOPORT_EVENT_DIRECTION_INPUT  = 0x1, ///< Set input direction to single port
+} ioport_event_direction_t;
+
+/** Input event edge detection
+ *  @note Event link must be configured by the ELC
+ */
+typedef enum e_ioport_event_detection
+{
+    IOPORT_EVENT_DETECTION_RISING_EDGE  = 0x0, ///< Set rising edge to event detection for input event
+    IOPORT_EVENT_DETECTION_FALLING_EDGE = 0x1, ///< Set falling edge to event detection for input event
+    IOPORT_EVENT_DETECTION_BOTH_EGDE    = 0x2, ///< Set both edges to event detection for input event
+} ioport_event_detection_t;
+
+/** Initial value for buffer register
+ *  @note Event link must be configured by the ELC
+ */
+typedef enum e_ioport_event_initial_buffer_value
+{
+    IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW  = 0U, ///< Set low input to initial value of buffer register for input port group
+    IOPORT_EVENT_INITIAL_BUFFER_VALUE_HIGH = 1U, ///< Set high input to initial value of buffer register for input port group
+} ioport_event_initial_buffer_value_t;
+
+/** Single port configuration
+ *  @note Event link must be configured by the ELC
+ */
+typedef struct st_ioport_event_single
+{
+    ioport_event_control_t          event_control;  ///< Event link control for single port
+    ioport_event_direction_t        direction;      ///< Event direction for single port
+    uint16_t                        port_num;       ///< Port number specified to single port
+    ioport_event_output_operation_t operation;      ///< Single port operation select
+    ioport_event_detection_t        edge_detection; ///< Edge detection select
+} ioport_event_single_t;
+
+/** Output port group configuration
+ *  @note Event link must be configured by the ELC
+ */
+typedef struct st_ioport_event_group_output
+{
+    uint8_t pin_select;                        ///< Port number specified to output port group
+    ioport_event_output_operation_t operation; ///< Port group operation select
+} ioport_event_group_output_t;
+
+/** Input port group configuration
+ *  @note Event link must be configured by the ELC
+ */
+typedef struct st_ioport_event_group_input
+{
+    ioport_event_control_t   event_control;     ///< Event link control for input port group
+    ioport_event_detection_t edge_detection;    ///< Edge detection select
+    ioport_event_control_t   overwrite_control; ///< Buffer register overwrite control
+    uint8_t pin_select;                         ///< Port number specified to input port group
+    uint8_t buffer_init_value;                  ///< Buffer register initial value
+} ioport_event_group_input_t;
+
+/** IOPORT extended configuration for event link function
+ *  @note Event link must be configured by the ELC
+ */
+typedef struct  st_ioport_extend_cfg
+{
+    ioport_event_group_output_t port_group_output_cfg[IOPORT_PORT_GROUP_NUM]; ///< Output port group configuration
+    ioport_event_group_input_t  port_group_input_cfg[IOPORT_PORT_GROUP_NUM];  ///< Input port group configuration
+    ioport_event_single_t       single_port_cfg[IOPORT_SINGLE_PORT_NUM];      ///< Single input port configuration
+} ioport_extend_cfg_t;
+
+/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
+typedef struct st_ioport_instance_ctrl
+{
+    uint32_t             open;         // Whether or not ioport is open
+    void const         * p_context;    // Pointer to context to be passed into callback
+    ioport_cfg_t const * p_cfg;        // Pointer to the configuration block
+} ioport_instance_ctrl_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const ioport_api_t g_ioport_on_ioport;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Public APIs
+ **********************************************************************************************************************/
+
+fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
+fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
+fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
+fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
+fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
+fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
+fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
+fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
+fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
+                                    bsp_io_port_t         port,
+                                    ioport_size_t         direction_values,
+                                    ioport_size_t         mask);
+fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
+fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
+                                        bsp_io_port_t         port,
+                                        ioport_size_t         event_data,
+                                        ioport_size_t         mask_value);
+fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
+fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup IOPORT)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // R_IOPORT_H
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_mtu3.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_mtu3.h
new file mode 100644
index 00000000..ec2f4469
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_mtu3.h
@@ -0,0 +1,455 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef R_MTU3_H
+#define R_MTU3_H
+
+/*******************************************************************************************************************//**
+ * @addtogroup MTU3
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_timer_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** I/O Level Select */
+typedef enum e_mtu3_io_pin_level
+{
+    /* Output */
+    MTU3_IO_PIN_LEVEL_NO_OUTPUT                   = 0,    ///< Output prohibited
+    MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_LOW     = 1,    ///< Initial output is low. Low output at compare match.
+    MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_HIGH    = 2,    ///< Initial output is low. High output at compare match.
+    MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_TOGGLE  = 3,    ///< Initial output is low. Toggle output at compare match.
+    MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_LOW    = 5,    ///< Initial output is high. Low output at compare match.
+    MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_HIGH   = 6,    ///< Initial output is high. High output at compare match.
+    MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_TOGGLE = 7,    ///< Initial output is high. Toggle output at compare match.
+
+    /* Input(Common to A and B) */
+    MTU3_IO_PIN_LEVEL_INPUT_RISING_EDGE  = 8,             ///< Input capture at rising edge.
+    MTU3_IO_PIN_LEVEL_INPUT_FALLING_EDGE = 9,             ///< Input capture at falling edge.
+    MTU3_IO_PIN_LEVEL_INPUT_BOTH_EDGE    = 10,            ///< Input capture at both edge.
+
+    /* Input A(IOA) */
+    MTU3_IO_PIN_LEVEL_INPUT_A_MTU1_TCNT_CH0         = 12, ///< Capture input source is the clock source for counting in MTU1. (ch0)
+    MTU3_IO_PIN_LEVEL_INPUT_A_MTU0_TGRA_COMPARE_CH1 = 12, ///< Input capture at generation of MTU0.TGRA compare match/input capture. (ch1)
+
+    /* Input B(IOB) */
+    MTU3_IO_PIN_LEVEL_INPUT_B_MTU1_TCNT_CH0_8 = 12,       ///< Capture input source is the clock source for counting in MTU1. (ch0, 8)
+} mtu3_io_pin_level_t;
+
+/** I/O Level Select(MTU5) */
+typedef enum e_mtu3_io_pin_level_uvw
+{
+    MTU3_IO_PIN_LEVEL_UVW_NO_FUNC                    = 0x0,  ///< No function
+    MTU3_IO_PIN_LEVEL_UVW_INPUT_RISING_EDGE          = 0x11, ///< Input capture at rising edge.
+    MTU3_IO_PIN_LEVEL_UVW_INPUT_FALLING_EDGE         = 0x12, ///< Input capture at falling edge.
+    MTU3_IO_PIN_LEVEL_UVW_INPUT_BOTH_EDGE            = 0x13, ///< Input capture at both edges.
+    MTU3_IO_PIN_LEVEL_UVW_INPUT_MTU8_TGRC_COMPARE    = 0x14, ///< Input capture on generation of compare match with MTU8.TGRC
+    MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_LOW_TROUGH        = 0x19, ///< Measurement of low pulse width of external input signal.Capture at trough in complementary PWM mode.
+    MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_LOW_CREST         = 0x1A, ///< Measurement of low pulse width of external input signal.Capture at crest of complementary PWM mode.
+    MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_LOW_CREST_TROUGH  = 0x1B, ///< Measurement of low pulse width of external input signal.Capture at crest and trough of complementary PWM mode.
+    MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_HIGH_TROUGH       = 0x1D, ///< Measurement of high pulse width of external input signal.Capture at trough in complementary PWM mode.
+    MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_HIGH_CREST        = 0x1E, ///< Measurement of high pulse width of external input signal.Capture at crest of complementary PWM mode.
+    MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_HIGH_CREST_TROUGH = 0x1F, ///< Measurement of high pulse width of external input signal.Capture at crest and trough of complementary PWM mode.
+} mtu3_io_pin_level_uvw_t;
+
+/** Clock Edge Select */
+typedef enum e_mtu3_clock_edge
+{
+    MTU3_CLOCK_EDGE_RISING  = 0x0,     ///< Count at rising edge
+    MTU3_CLOCK_EDGE_FALLING = 0x1,     ///< Count at falling edge
+    MTU3_CLOCK_EDGE_BOTH    = 0x2,     ///< Count at both edges
+} mtu3_clock_edge_t;
+
+/** Time Prescaler Select */
+typedef enum e_mtu3_div
+{
+    MTU3_DIV_PCLKH_1  = 0x0,                ///< PCLKH divided by 1  (common ch)
+    MTU3_DIV_PCLKH_4  = 0x1,                ///< PCLKH divided by 4  (common ch)
+    MTU3_DIV_PCLKH_16 = 0x2,                ///< PCLKH divided by 16 (common ch)
+    MTU3_DIV_PCLKH_64 = 0x3,                ///< PCLKH divided by 64 (common ch)
+    MTU3_DIV_PCLKH_2  = 0x8,                ///< PCLKH divided by 2 (common ch)
+    MTU3_DIV_PCLKH_8  = 0x10,               ///< PCLKH divided by 8 (common ch)
+    MTU3_DIV_PCLKH_32 = 0x18,               ///< PCLKH divided by 32 (common ch)
+
+    MTU3_DIV_MTCLKA_CH_0     = 0x4,         ///< External clock: counts on MTCLKA pin input (ch0)
+    MTU3_DIV_MTCLKB_CH_0     = 0x5,         ///< External clock: counts on MTCLKB pin input (ch0)
+    MTU3_DIV_MTCLKC_CH_0     = 0x6,         ///< External clock: counts on MTCLKC pin input (ch0)
+    MTU3_DIV_MTCLKD_CH_0     = 0x7,         ///< External clock: counts on MTCLKD pin input (ch0)
+    MTU3_DIV_PCLKH_256_CH_0  = 0x20,        ///< PCLKH divided by 256 (ch0)
+    MTU3_DIV_PCLKH_1024_CH_0 = 0x28,        ///< PCLKH divided by 1024 (ch0)
+    MTU3_DIV_MTIOC1A_CH_0    = 0x38,        ///< External clock: counts on MTIOC1A pin input (ch0)
+
+    MTU3_DIV_MTCLKA_CH_1     = 0x4,         ///< External clock: counts on MTCLKA pin input (ch1)
+    MTU3_DIV_MTCLKB_CH_1     = 0x5,         ///< External clock: counts on MTCLKB pin input (ch1)
+    MTU3_DIV_PCLKH_256_CH_1  = 0x6,         ///< PCLKH divided by 256 (ch1)
+    MTU3_DIV_TCNT_CH1        = 0x7,         ///< Overflow/underflow of MTU2.TCNT
+    MTU3_DIV_PCLKH_1024_CH_1 = 0x20,        ///< PCLKH divided by 1024 (ch1)
+
+    MTU3_DIV_MTCLKA_CH_2     = 0x4,         ///< External clock: counts on MTCLKA pin input (ch2)
+    MTU3_DIV_MTCLKB_CH_2     = 0x5,         ///< External clock: counts on MTCLKB pin input (ch2)
+    MTU3_DIV_MTCLKC_CH_2     = 0x6,         ///< External clock: counts on MTCLKC pin input (ch2)
+    MTU3_DIV_PCLKH_1024_CH_2 = 0x7,         ///< PCLKH divided by 1024 (ch2)
+    MTU3_DIV_PCLKH_256_CH_2  = 0x20,        ///< PCLKH divided by 256 (ch2)
+
+    MTU3_DIV_PCLKH_256_CH_3_4_6_7_8  = 0x4, ///< PCLKH divided by 256 (ch3-4, 6-8)
+    MTU3_DIV_PCLKH_1024_CH_3_4_6_7_8 = 0x5, ///< PCLKH divided by 1024 (ch3-4, 6-8)
+    MTU3_DIV_MTCLKA_CH_3_4_6_7_8     = 0x6, ///< External clock: counts on MTCLKA pin input (ch3-4, 6-8)
+    MTU3_DIV_MTCLKB_CH_3_4_6_7_8     = 0x7, ///< External clock: counts on MTCLKB pin input (ch3-4, 6-8)
+} mtu3_div_t;
+
+/** Time Prescaler Select(MTU5) */
+typedef enum e_mtu3_div_uvw
+{
+    MTU3_DIV_UVW_PCLKH_1              = 0x0,  ///< PCLKH divided by 1
+    MTU3_DIV_UVW_PCLKH_4              = 0x1,  ///< PCLKH divided by 4
+    MTU3_DIV_UVW_PCLKH_16             = 0x2,  ///< PCLKH divided by 16
+    MTU3_DIV_UVW_PCLKH_64             = 0x3,  ///< PCLKH divided by 64
+    MTU3_DIV_UVW_PCLKH_2              = 0x4,  ///< PCLKH divided by 2
+    MTU3_DIV_UVW_PCLKH_8              = 0x8,  ///< PCLKH divided by 8
+    MTU3_DIV_UVW_PCLKH_32             = 0xC,  ///< PCLKH divided by 32
+    MTU3_DIV_UVW_PCLKH_256            = 0x10, ///< PCLKH divided by 256
+    MTU3_DIV_UVW_PCLKH_1024           = 0x14, ///< PCLKH divided by 1024
+    MTU3_DIV_UVW_MTIOC1A_RISING_EDGE  = 0x1C, ///< External clock: Counts at the rising edge on MTIOC1A pin input
+    MTU3_DIV_UVW_MTIOC1A_FALLING_EDGE = 0x3C, ///< External clock: Counts at the falling edge on MTIOC1A pin input
+    MTU3_DIV_UVW_MTIOC1A_BOTH_EDGE    = 0x5C, ///< External clock: Counts at the both edges on MTIOC1A pin input
+} mtu3_div_uvw_t;
+
+/** Counter Clear Source Select */
+typedef enum e_mtu3_tcnt_clear
+{
+    MTU3_TCNT_CLEAR_DISABLE = 0x0,     ///< TCNT clearing disabled
+    MTU3_TCNT_CLEAR_TGRA    = 0x1,     ///< TCNT cleared by TGRA compare match/input capture
+    MTU3_TCNT_CLEAR_TGRB    = 0x2,     ///< TCNT cleared by TGRB compare match/input capture
+} mtu3_tcnt_clear_t;
+
+/** Level of MTU3 pin */
+typedef enum e_mtu3_io_pin
+{
+    MTU3_IO_PIN_MTIOCA            = 0, ///< MTIOCA
+    MTU3_IO_PIN_MTIOCB            = 1, ///< MTIOCB
+    MTU3_IO_PIN_MTIOCA_AND_MTIOCB = 2, ///< MTIOCA and MTIOCB
+} mtu3_io_pin_t;
+
+/** MTU3 event group operation
+ *  @note Event link must be configured by the ELC
+ */
+typedef enum e_mtu3_elc_operation_option
+{
+    MTU3_EVENT_OPERATION_SELECT_COUNT_START   = 0x0, ///< The MTU event operation is set to start counting
+    MTU3_EVENT_OPERATION_SELECT_COUNT_RESTART = 0x1, ///< The MTU event operation is set to restart counting
+    MTU3_EVENT_OPERATION_SELECT_INPUT_CAPTURE = 0x2, ///< The MTU event operation is set to input capture
+    MTU3_EVENT_OPERATION_SELECT_DISABLE       = 0x3, ///< The MTU event operation is set to disable
+} mtu3_elc_operation_option_t;
+
+/** Configurations for output pins. */
+typedef struct st_mtu3_output_pin
+{
+    mtu3_io_pin_level_t output_pin_level_a; ///< I/O Control A
+    mtu3_io_pin_level_t output_pin_level_b; ///< I/O Control B
+} mtu3_output_pin_t;
+
+/** Disables or enables the noise filter for input from the MTIOCnA pin */
+typedef enum e_mtu3_noise_filter
+{
+    MTU3_NOISE_FILTER_DISABLE  = 0U,   ///< The noise filter for the MTIOC pin is disabled
+    MTU3_NOISE_FILTER_A_ENABLE = 1U,   ///< The noise filter for the MTIOCA pin is enabled
+    MTU3_NOISE_FILTER_B_ENABLE = 2U,   ///< The noise filter for the MTIOCB pin is enabled
+} mtu3_noise_filter_setting_t;
+
+/** Disables or enables the noise filter for the external clock input pins of the MTU */
+typedef enum e_mtu3_noise_filter_external
+{
+    MTU3_NOISE_FILTER_EXTERNAL_DISABLE  = 0U, ///< The noise filter for the MTCLK pin is disabled
+    MTU3_NOISE_FILTER_EXTERNAL_A_ENABLE = 1U, ///< The noise filter for the MTCLKA pin is enabled.
+    MTU3_NOISE_FILTER_EXTERNAL_B_ENABLE = 2U, ///< The noise filter for the MTCLKB pin is enabled.
+    MTU3_NOISE_FILTER_EXTERNAL_C_ENABLE = 4U, ///< The noise filter for the MTCLKC pin is enabled.
+    MTU3_NOISE_FILTER_EXTERNAL_D_ENABLE = 8U, ///< The noise filter for the MTCLKD pin is enabled.
+} mtu3_noise_filter_mtclk_setting_t;
+
+/** Disables or enables the noise filter for input from the MTIC5U, MTIC5V, MTIC5W pin */
+typedef enum e_mtu3_noise_filter_uvw
+{
+    MTU3_NOISE_FILTER_UVW_DISABLE  = 0U, ///< The noise filter for the MTIOC pin is disabled
+    MTU3_NOISE_FILTER_UVW_U_ENABLE = 1U, ///< The noise filter for the MTIC5U pin is enabled
+    MTU3_NOISE_FILTER_UVW_V_ENABLE = 2U, ///< The noise filter for the MTIC5V pin is enabled
+    MTU3_NOISE_FILTER_UVW_W_ENABLE = 4U, ///< The noise filter for the MTIC5W pin is enabled
+} mtu3_noise_filter_setting_uvw_t;
+
+typedef enum e_mtu3_noise_filter_clock
+{
+    MTU3_NOISE_FILTER_CLOCK_PCLKH_DIV_1  = 0U, ///< PCLK/1 - fast sampling
+    MTU3_NOISE_FILTER_CLOCK_PCLKH_DIV_8  = 1U, ///< PCLK/8
+    MTU3_NOISE_FILTER_CLOCK_PCLKH_DIV_32 = 2U, ///< PCLK/32 - slow sampling
+    MTU3_NOISE_FILTER_CLOCK_SOURCE       = 3U, ///< Clock source for counting
+} mtu3_noise_filter_clock_t;
+
+typedef enum e_mtu3_noise_filter_external_clock
+{
+    MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_1  = 0U, ///< PCLK/1 - fast sampling
+    MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_2  = 1U, ///< PCLK/2
+    MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_8  = 2U, ///< PCLK/8
+    MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_32 = 3U, ///< PCLK/32 - slow sampling
+} mtu3_noise_filter_external_clock_t;
+
+/** Interrupt Skipping Function Select */
+typedef enum e_mtu3_interrupt_skip_mode
+{
+    MTU3_INTERRUPT_SKIP_MODE_1 = 0U,   ///< Setting the TITCR1A or TITCR1B register enables
+    MTU3_INTERRUPT_SKIP_MODE_2 = 1U,   ///< Setting the TITCR2A or TITCR2B register enables
+} mtu3_interrupt_skip_mode_t;
+
+/** Number of interrupts to skip between events */
+typedef enum e_mtu3_interrupt_skip_count
+{
+    MTU3_INTERRUPT_SKIP_COUNT_0 = 0U,  ///< Do not skip interrupts
+    MTU3_INTERRUPT_SKIP_COUNT_1,       ///< Skip one interrupt
+    MTU3_INTERRUPT_SKIP_COUNT_2,       ///< Skip two interrupts
+    MTU3_INTERRUPT_SKIP_COUNT_3,       ///< Skip three interrupts
+    MTU3_INTERRUPT_SKIP_COUNT_4,       ///< Skip four interrupts
+    MTU3_INTERRUPT_SKIP_COUNT_5,       ///< Skip five interrupts
+    MTU3_INTERRUPT_SKIP_COUNT_6,       ///< Skip six interrupts
+    MTU3_INTERRUPT_SKIP_COUNT_7,       ///< Skip seven interrupts
+} mtu3_interrupt_skip_count_t;
+
+/** Trigger options to start A/D conversion. */
+typedef enum e_mtu3_adc_compare_match
+{
+    MTU3_ADC_COMPARE_MATCH_ADC_A = 0x1U, ///< Set A/D conversion start request value for MTU3 A/D converter start request A
+    MTU3_ADC_COMPARE_MATCH_ADC_B = 0x2U, ///< Set A/D conversion start request value for MTU3 A/D converter start request B
+} mtu3_adc_compare_match_t;
+
+/** Current timer status. */
+typedef struct st_mtu3_status
+{
+    uint32_t counter;                  ///< Current counter value
+
+    /* MTU3 ch5 specific parameters */
+    uint32_t tgru_counter;             ///< Current counter value(TGRU)
+    uint32_t tgrv_counter;             ///< Current counter value(TGRV)
+    uint32_t tgrw_counter;             ///< Current counter value(TGRW)
+
+    timer_state_t state;               ///< Current timer state (running or stopped)
+} mtu3_status_t;
+
+/** MTU3 configuration for event link function*/
+typedef struct st_mtu3_elc_operation
+{
+    mtu3_elc_operation_option_t mtu0_elc_operation; ///< MTU0 operation select
+    mtu3_elc_operation_option_t mtu3_elc_operation; ///< MTU3 operation select
+    mtu3_elc_operation_option_t mtu4_elc_operation; ///< MTU4 operation select
+} mtu3_elc_operation_t;
+
+/** MTU3 set counter. */
+typedef struct st_mtu3_counter
+{
+    uint32_t tgra_counts;              ///< Counter value(TGRA)
+    uint32_t tgrb_counts;              ///< Counter value(TGRB)
+
+    /* MTU3 ch5 specific parameters */
+    uint32_t tgru_counts;              ///< Counter value(TGRU)
+    uint32_t tgrv_counts;              ///< Counter value(TGRV)
+    uint32_t tgrw_counts;              ///< Counter value(TGRW)
+} mtu3_counter_t;
+
+/** MTU3 information structure to store various information for a timer resource */
+typedef struct st_mtu3_info
+{
+    timer_direction_t count_direction;    ///< Clock counting direction of the timer.
+    uint32_t          clock_frequency[3]; ///< Clock frequency of the timer counter.(For ch5, use clock_frequency[0]-[2].)
+
+    mtu3_counter_t count_param;
+} mtu3_info_t;
+
+/** Channel control block. DO NOT INITIALIZE.  Initialization occurs when @ref timer_api_t::open is called. */
+typedef struct st_mtu3_instance_ctrl
+{
+    uint32_t            open;                     ///< Whether or not channel is open
+    const timer_cfg_t * p_cfg;                    ///< Pointer to initial configurations
+    void              * p_reg;                    ///< Base register for this channel
+    R_MTU_Type        * p_reg_com;                ///< Base register for this channel(common ch)
+    void              * p_reg_nf;                 ///< Base register for this channel(noise fileter)
+    uint32_t            channel_mask;             ///< Channel bitmask
+
+    void (* p_callback)(timer_callback_args_t *); ///< Pointer to callback
+    timer_callback_args_t * p_callback_memory;    ///< Pointer to optional callback argument memory
+    void const            * p_context;            ///< Pointer to context to be passed into callback function
+} mtu3_instance_ctrl_t;
+
+/** MTU3 extension for advanced PWM features. */
+typedef struct st_mtu3_extended_pwm_cfg
+{
+    mtu3_interrupt_skip_mode_t interrupt_skip_mode_a;           ///< Selects interrupt skipping function 1 or 2(TIMTRA)
+    mtu3_interrupt_skip_mode_t interrupt_skip_mode_b;           ///< Selects interrupt skipping function 1 or 2(TIMTRB)
+    uint16_t adc_a_compare_match;                               ///< Timer A/D Converter Start Request Cycle A (MTU4 or MTU7)
+    uint16_t adc_b_compare_match;                               ///< Timer A/D Converter Start Request Cycle B (MTU4 or MTU7)
+    mtu3_interrupt_skip_count_t interrupt_skip_count_tciv4;     ///< TCIV4 Interrupt Skipping Count Setting(TITCR1A)
+    mtu3_interrupt_skip_count_t interrupt_skip_count_tgia3;     ///< TGIA3 Interrupt Skipping Count Setting(TITCR1A)
+    mtu3_interrupt_skip_count_t interrupt_skip_count_tciv7;     ///< TCIV7 Interrupt Skipping Count Setting(TITCR1B)
+    mtu3_interrupt_skip_count_t interrupt_skip_count_tgia6;     ///< TGIA6 Interrupt Skipping Count Setting(TITCR1B)
+    mtu3_interrupt_skip_count_t interrupt_skip_count_tgr4an_bn; ///< TRG4AN/TRG4BN Interrupt Skipping Count Setting(TITCR2A)
+    mtu3_interrupt_skip_count_t interrupt_skip_count_tgr7an_bn; ///< TRG7AN/TRG7BN Interrupt Skipping Count Setting(TITCR2B)
+} mtu3_extended_pwm_cfg_t;
+
+/** MTU3 extension for ch5. */
+typedef struct st_mtu3_extended_uvw_cfg
+{
+    /* Used only with MTU5(TGRU5, TGRV5, TGRW5) */
+    uint16_t tgru_val;                          ///< Capture/Compare match U register
+    uint16_t tgrv_val;                          ///< Capture/Compare match V register
+    uint16_t tgrw_val;                          ///< Capture/Compare match W register
+
+    mtu3_div_uvw_t mtu3_clk_div_u;              ///< Time Prescaler Select U register
+    mtu3_div_uvw_t mtu3_clk_div_v;              ///< Time Prescaler Select V register
+    mtu3_div_uvw_t mtu3_clk_div_w;              ///< Time Prescaler Select W register
+
+    mtu3_io_pin_level_uvw_t output_pin_level_u; ///< I/O Control U register
+    mtu3_io_pin_level_uvw_t output_pin_level_v; ///< I/O Control V register
+    mtu3_io_pin_level_uvw_t output_pin_level_w; ///< I/O Control W register
+
+    /* Debounce filter for MTIC5U, MTIC5V or MTIC5W input signal pin. */
+    mtu3_noise_filter_setting_uvw_t noise_filter_mtioc_setting_uvw;
+    mtu3_noise_filter_clock_t       noise_filter_mtioc_clk_uvw;
+
+    uint8_t   capture_u_ipl;                             ///< Capture/Compare match U interrupt priority
+    uint8_t   capture_v_ipl;                             ///< Capture/Compare match V interrupt priority
+    uint8_t   capture_w_ipl;                             ///< Capture/Compare match W interrupt priority
+    IRQn_Type capture_u_irq;                             ///< Capture/Compare match U interrupt
+    IRQn_Type capture_v_irq;                             ///< Capture/Compare match V interrupt
+    IRQn_Type capture_w_irq;                             ///< Capture/Compare match W interrupt
+
+    bsp_irq_gpt_selected_event_t capture_u_select_event; ///< Selected capture u event
+    bsp_irq_gpt_selected_event_t capture_v_select_event; ///< Selected capture v event
+    bsp_irq_gpt_selected_event_t capture_w_select_event; ///< Selected capture w event
+} mtu3_extended_uvw_cfg_t;
+
+typedef enum e_mtu3_phase_counting_mode
+{
+    MTU3_PHASE_COUNTING_MODE_NONE,     ///< Disable Counting Mode
+    MTU3_PHASE_COUNTING_MODE_1,        ///< Mode 1
+    MTU3_PHASE_COUNTING_MODE_200,      ///< Mode 2 (00)
+    MTU3_PHASE_COUNTING_MODE_201,      ///< Mode 2 (01)
+    MTU3_PHASE_COUNTING_MODE_210,      ///< Mode 2 (1x)
+    MTU3_PHASE_COUNTING_MODE_300,      ///< Mode 3 (00)
+    MTU3_PHASE_COUNTING_MODE_301,      ///< Mode 3 (01)
+    MTU3_PHASE_COUNTING_MODE_310,      ///< Mode 3 (1x)
+    MTU3_PHASE_COUNTING_MODE_4,        ///< Mode 4
+    MTU3_PHASE_COUNTING_MODE_50,       ///< Mode 5 (0x)
+    MTU3_PHASE_COUNTING_MODE_51,       ///< Mode 5 (10)
+} mtu3_phase_counting_mode_t;
+
+typedef enum e_mtu3_bit_mode
+{
+    MTU3_BIT_MODE_NORMAL_16BIT,        ///< normal mode(16bit mode)
+    MTU3_BIT_MODE_NORMAL_32BIT,        ///< normal mode(32bit mode)
+} mtu3_bit_mode_t;
+
+typedef enum e_mtu3_external_clock
+{
+    MTU3_EXTERNAL_CLOCK_MTCLKA_B = 0x0, ///< MTCLKA, MTCLKB
+    MTU3_EXTERNAL_CLOCK_MTCLKC_D = 0x1, ///< MTCLKC, MTCLKD
+} mtu3_external_clock_t;
+
+/** The MTU3 extension constitutes a unique feature of MTU3. */
+typedef struct st_mtu3_extended_cfg
+{
+    uint32_t          tgra_val;           ///< Capture/Compare match A register
+    uint32_t          tgrb_val;           ///< Capture/Compare match B register
+    uint32_t          tgrc_val;           ///< Capture/Compare match C register (Does not exist in MTU ch1-2)
+    uint32_t          tgrd_val;           ///< Capture/Compare match D register (Does not exist in MTU ch1-2)
+    mtu3_div_t        mtu3_clk_div;       ///< Time Prescaler Select
+    mtu3_clock_edge_t clk_edge;           ///< Clock Edge Select
+    mtu3_tcnt_clear_t mtu3_clear;         ///< Counter Clear Source Select
+    mtu3_output_pin_t mtioc_ctrl_setting; ///< I/O Control A, B
+
+    /* Debounce filter for MTIOCxA or MTIOCxB input signal pin. */
+    mtu3_noise_filter_setting_t noise_filter_mtioc_setting;
+    mtu3_noise_filter_clock_t   noise_filter_mtioc_clk;
+
+    /* Debounce filter for MTCLKx input signal pin. */
+    mtu3_noise_filter_mtclk_setting_t  noise_filter_mtclk_setting;
+    mtu3_noise_filter_external_clock_t noise_filter_mtclk_clk;
+
+    bool adc_request_enable;                             ///< A/D Converter Start Request Enable(ch5 and ch8 are excluded)
+
+    mtu3_elc_operation_t mtu3_elc_event_operation;       ///< MTU3 event link operation
+
+    /* Used for other than MTU5 */
+
+    uint8_t   capture_a_ipl;                             ///< Capture/Compare match A interrupt priority
+    uint8_t   capture_b_ipl;                             ///< Capture/Compare match B interrupt priority
+    IRQn_Type capture_a_irq;                             ///< Capture/Compare match A interrupt
+    IRQn_Type capture_b_irq;                             ///< Capture/Compare match B interrupt
+
+    mtu3_extended_uvw_cfg_t const * p_uvw_cfg;           ///< Advanced MTU ch5 features, optional
+    mtu3_extended_pwm_cfg_t const * p_pwm_cfg;           ///< Advanced PWM features, optional
+    mtu3_phase_counting_mode_t      counting_mode;       ///< Select the counting mode.
+    mtu3_bit_mode_t                 bit_mode;            ///< Select bit mode
+    mtu3_external_clock_t           external_clock;      ///< Select External Clock Input Pins
+
+    uint8_t capture_a_source_select;                     ///< Identify the GPT_INT for capture a
+    uint8_t capture_b_source_select;                     ///< Identify the GPT_INT for capture b
+    uint8_t cycle_end_source_select;                     ///< Identify the GPT_INT for capture overflow/underflow
+
+    bsp_irq_gpt_selected_event_t capture_a_select_event; ///< Selected capture a event
+    bsp_irq_gpt_selected_event_t capture_b_select_event; ///< Selected capture b event
+    bsp_irq_gpt_selected_event_t cycle_end_select_event; ///< Selected cycle end event
+} mtu3_extended_cfg_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const timer_api_t g_timer_on_mtu3;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Public APIs
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
+fsp_err_t R_MTU3_Stop(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_MTU3_Start(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_MTU3_Reset(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_MTU3_PeriodSet(timer_ctrl_t * const p_ctrl, mtu3_counter_t * const p_counter);
+fsp_err_t R_MTU3_InfoGet(timer_ctrl_t * const p_ctrl, mtu3_info_t * const p_info);
+fsp_err_t R_MTU3_StatusGet(timer_ctrl_t * const p_ctrl, mtu3_status_t * const p_status);
+fsp_err_t R_MTU3_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter);
+fsp_err_t R_MTU3_OutputEnable(timer_ctrl_t * const p_ctrl, mtu3_output_pin_t pin_level);
+fsp_err_t R_MTU3_OutputDisable(timer_ctrl_t * const p_ctrl, mtu3_io_pin_t pin);
+fsp_err_t R_MTU3_AdcTriggerSet(timer_ctrl_t * const     p_ctrl,
+                               mtu3_adc_compare_match_t which_compare_match,
+                               uint16_t                 compare_match_value);
+fsp_err_t R_MTU3_CallbackSet(timer_ctrl_t * const          p_ctrl,
+                             void (                      * p_callback)(timer_callback_args_t *),
+                             void const * const            p_context,
+                             timer_callback_args_t * const p_callback_memory);
+fsp_err_t R_MTU3_Close(timer_ctrl_t * const p_ctrl);
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup MTU3)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_sci_uart.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_sci_uart.h
new file mode 100644
index 00000000..50f4513c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/inc/instances/r_sci_uart.h
@@ -0,0 +1,245 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef R_SCI_UART_H
+#define R_SCI_UART_H
+
+/*******************************************************************************************************************//**
+ * @addtogroup SCI_UART
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_uart_api.h"
+#include "r_sci_uart_cfg.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Enumeration for SCI clock source */
+typedef enum e_sci_uart_clock
+{
+    SCI_UART_CLOCK_INT,                      ///< Use internal clock for baud generation
+    SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
+    SCI_UART_CLOCK_EXT8X,                    ///< Use external clock 8x baud rate
+    SCI_UART_CLOCK_EXT16X                    ///< Use external clock 16x baud rate
+} sci_uart_clock_t;
+
+/** UART flow control mode definition */
+typedef enum e_sci_uart_flow_control
+{
+    SCI_UART_FLOW_CONTROL_RTS             = 0U, ///< Use CTSn_RTSn pin for RTS
+    SCI_UART_FLOW_CONTROL_CTS             = 1U, ///< Use CTSn_RTSn pin for CTS
+    SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS
+    SCI_UART_FLOW_CONTROL_CTSRTS          = 5U, ///< Use SCI pin for CTS, external pin for RTS
+} sci_uart_flow_control_t;
+
+/** UART instance control block. */
+typedef struct st_sci_uart_instance_ctrl
+{
+    /* Parameters to control UART peripheral device */
+    uint8_t  fifo_depth;               // FIFO depth of the UART channel
+    uint8_t  rx_transfer_in_progress;  // Set to 1 if a receive transfer is in progress, 0 otherwise
+    uint8_t  data_bytes         : 2;   // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data
+    uint8_t  bitrate_modulation : 1;   // 1 if bit rate modulation is enabled, 0 otherwise
+    uint32_t open;                     // Used to determine if the channel is configured
+
+    bsp_io_port_pin_t flow_pin;
+
+    /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
+    uint8_t const * p_tx_src;
+
+    /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
+    uint32_t tx_src_bytes;
+
+    /* Destination buffer pointer used for receiving data. */
+    uint8_t const * p_rx_dest;
+
+    /* Size of destination buffer pointer used for receiving data. */
+    uint32_t rx_dest_bytes;
+
+    /* Pointer to the configuration block. */
+    uart_cfg_t const * p_cfg;
+
+    /* Base register for this channel */
+    R_SCI0_Type * p_reg;
+
+    void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs.
+    uart_callback_args_t * p_callback_memory;    // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
+
+    /* Pointer to context to be passed into callback function */
+    void const * p_context;
+} sci_uart_instance_ctrl_t;
+
+/** Receive FIFO trigger configuration. */
+typedef enum e_sci_uart_rx_fifo_trigger
+{
+    SCI_UART_RX_FIFO_TRIGGER_1   = 0x1, ///< Callback after each byte is received without buffering
+    SCI_UART_RX_FIFO_TRIGGER_2   = 0x2, ///< Callback when FIFO having 2 bytes
+    SCI_UART_RX_FIFO_TRIGGER_3   = 0x3, ///< Callback when FIFO having 3 bytes
+    SCI_UART_RX_FIFO_TRIGGER_4   = 0x4, ///< Callback when FIFO having 4 bytes
+    SCI_UART_RX_FIFO_TRIGGER_5   = 0x5, ///< Callback when FIFO having 5 bytes
+    SCI_UART_RX_FIFO_TRIGGER_6   = 0x6, ///< Callback when FIFO having 6 bytes
+    SCI_UART_RX_FIFO_TRIGGER_7   = 0x7, ///< Callback when FIFO having 7 bytes
+    SCI_UART_RX_FIFO_TRIGGER_8   = 0x8, ///< Callback when FIFO having 8 bytes
+    SCI_UART_RX_FIFO_TRIGGER_9   = 0x9, ///< Callback when FIFO having 9 bytes
+    SCI_UART_RX_FIFO_TRIGGER_10  = 0xA, ///< Callback when FIFO having 10 bytes
+    SCI_UART_RX_FIFO_TRIGGER_11  = 0xB, ///< Callback when FIFO having 11 bytes
+    SCI_UART_RX_FIFO_TRIGGER_12  = 0xC, ///< Callback when FIFO having 12 bytes
+    SCI_UART_RX_FIFO_TRIGGER_13  = 0xD, ///< Callback when FIFO having 13 bytes
+    SCI_UART_RX_FIFO_TRIGGER_14  = 0xE, ///< Callback when FIFO having 14 bytes
+    SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts)
+} sci_uart_rx_fifo_trigger_t;
+
+/** Asynchronous Start Bit Edge Detection configuration. */
+typedef enum e_sci_uart_start_bit
+{
+    SCI_UART_START_BIT_LOW_LEVEL    = 0x0, ///< Detect low level on RXDn pin as start bit
+    SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
+} sci_uart_start_bit_t;
+
+/** Noise cancellation configuration. */
+typedef enum e_sci_uart_noise_cancellation
+{
+    SCI_UART_NOISE_CANCELLATION_DISABLE                 = 0x0, ///< Disable noise cancellation
+    SCI_UART_NOISE_CANCELLATION_ENABLE                  = 0x1, ///< Enable noise cancellation, The base clock signal divided by 1
+    SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_1 = 0x2, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 1
+    SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_2 = 0x3, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 2
+    SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_4 = 0x4, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 4
+    SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_8 = 0x5, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 8
+} sci_uart_noise_cancellation_t;
+
+/** RS-485 Enable/Disable. */
+typedef enum e_sci_uart_rs485_enable
+{
+    SCI_UART_RS485_DISABLE = 0,        ///< RS-485 disabled.
+    SCI_UART_RS485_ENABLE  = 1,        ///< RS-485 enabled.
+} sci_uart_rs485_enable_t;
+
+/** The polarity of the RS-485 DE signal. */
+typedef enum e_sci_uart_rs485_de_polarity
+{
+    SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress.
+    SCI_UART_RS485_DE_POLARITY_LOW  = 1, ///< The DE signal is low when a write transfer is in progress.
+} sci_uart_rs485_de_polarity_t;
+
+/** Source clock selection options for SCI. */
+typedef enum e_sci_uart_clock_source
+{
+    SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0,
+    SCI_UART_CLOCK_SOURCE_SCI1ASYNCCLK = 1,
+    SCI_UART_CLOCK_SOURCE_SCI2ASYNCCLK = 2,
+    SCI_UART_CLOCK_SOURCE_SCI3ASYNCCLK = 3,
+    SCI_UART_CLOCK_SOURCE_SCI4ASYNCCLK = 4,
+    SCI_UART_CLOCK_SOURCE_SCI5ASYNCCLK = 5,
+    SCI_UART_CLOCK_SOURCE_PCLKM        = 6,
+} sci_uart_clock_source_t;
+
+/** Baudrate calculation configuration. */
+typedef struct st_sci_uart_baud_calculation
+{
+    uint32_t baudrate;                 ///< Target baudrate
+    bool     bitrate_modulation;       ///< Whether bitrate modulation use or not
+    uint32_t baud_rate_error_x_1000;   ///< Max baudrate percent error
+} sci_uart_baud_calculation_t;
+
+/** Register settings to achieve a desired baud rate and modulation duty. */
+typedef struct st_sci_baud_setting_t
+{
+    union
+    {
+        uint32_t baudrate_bits;
+
+        struct
+        {
+            uint32_t       : 4;
+            uint32_t bgdm  : 1;        ///< Baud Rate Generator Double-Speed Mode Select
+            uint32_t abcs  : 1;        ///< Asynchronous Mode Base Clock Select
+            uint32_t abcse : 1;        ///< Asynchronous Mode Extended Base Clock Select 1
+            uint32_t       : 1;
+            uint32_t brr   : 8;        ///< Bit Rate Register setting
+            uint32_t brme  : 1;        ///< Bit Rate Modulation Enable
+            uint32_t       : 3;
+            uint32_t cks   : 2;        ///< CKS  value to get divisor (CKS = N)
+            uint32_t       : 2;
+            uint32_t mddr  : 8;        ///< Modulation Duty Register setting
+        } baudrate_bits_b;
+    };
+} sci_baud_setting_t;
+
+/** Configuration settings for controlling the DE signal for RS-485. */
+typedef struct st_sci_uart_rs485_setting
+{
+    sci_uart_rs485_enable_t      enable;   ///< Enable the DE signal.
+    sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity.
+    uint8_t assertion_time : 5;            ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer.
+    uint8_t negation_time  : 5;            ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated.
+} sci_uart_rs485_setting_t;
+
+/** UART on SCI device Configuration */
+typedef struct st_sci_uart_extended_cfg
+{
+    sci_uart_clock_t              clock;         ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
+    sci_uart_start_bit_t          rx_edge_start; ///< Start reception on falling edge
+    sci_uart_noise_cancellation_t noise_cancel;  ///< Noise cancellation setting
+
+    sci_baud_setting_t * p_baud_setting;         ///< Register settings for a desired baud rate.
+
+    sci_uart_rx_fifo_trigger_t rx_fifo_trigger;  ///< Receive FIFO trigger level, unused if channel has no FIFO or if DMAC is used.
+
+    bsp_io_port_pin_t        flow_control_pin;   ///< UART Driver Enable pin
+    sci_uart_flow_control_t  flow_control;       ///< CTS/RTS function
+    sci_uart_rs485_setting_t rs485_setting;      ///< RS-485 settings.
+
+    /** Clock source to generate SCK can either be selected as PCLKM or SCInASYNCCLK. */
+    sci_uart_clock_source_t clock_source;
+} sci_uart_extended_cfg_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const uart_api_t g_uart_on_sci;
+
+/** @endcond */
+
+fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
+fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
+fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
+fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_ctrl, void const * const p_baud_setting);
+fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
+fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_ctrl);
+fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
+fsp_err_t R_SCI_UART_BaudCalculate(sci_uart_baud_calculation_t const * const p_baud_target,
+                                   sci_uart_clock_source_t                   clock_source,
+                                   sci_baud_setting_t * const                p_baud_setting);
+fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const          p_ctrl,
+                                 void (                     * p_callback)(uart_callback_args_t *),
+                                 void const * const           p_context,
+                                 uart_callback_args_t * const p_callback_memory);
+fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup SCI_UART)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h
new file mode 100644
index 00000000..b96a2e99
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h
@@ -0,0 +1,46264 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/** @addtogroup Renesas Electronics Corporation
+ * @{
+ */
+
+/** @addtogroup R9A07G084
+ * @{
+ */
+
+#ifndef R9A07G084_H
+ #define R9A07G084_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */
+ #ifdef RENESAS_CORTEX_M4
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
+  #include "core_cm4.h"                /*!< Cortex-M4 processor and core peripherals                              */
+ #elif defined(RENESAS_CORTEX_M0PLUS)
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
+  #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
+  #include "core_cm0plus.h"            /*!< Cortex-M0 processor and core peripherals                              */
+ #elif defined(RENESAS_CORTEX_M23)
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
+  #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
+  #include "core_cm23.h"               /*!< Cortex-M23 processor and core peripherals                             */
+ #elif defined(RENESAS_CORTEX_M33)
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
+  #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
+  #define __DSP_PRESENT             1  /*!< DSP present or not                                                    */
+  #include "core_cm33.h"               /*!< Cortex-M33 processor and core peripherals                             */
+ #elif defined(RENESAS_CORTEX_R52)
+  #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
+  #include "core_cr52.h"               /*!< Cortex-R52 processor and core peripherals                              */
+ #endif
+
+ #include "system.h"                   /*!< System                                                                */
+
+ #ifndef __IM                          /*!< Fallback for older CMSIS versions                                         */
+  #define __IM     __I
+ #endif
+ #ifndef __OM                          /*!< Fallback for older CMSIS versions                                         */
+  #define __OM     __O
+ #endif
+ #ifndef __IOM                         /*!< Fallback for older CMSIS versions                                         */
+  #define __IOM    __IO
+ #endif
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+ #if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+ #elif defined(__ICCARM__)
+  #pragma language=extended
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+  #pragma clang diagnostic ignored "-Wnested-anon-types"
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning 586
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #else
+  #warning Not supported compiler type
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                              Device Specific Cluster Section                              ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+/**
+ * @brief R_CANFD_CFDC [CFDC] (CANFD Channel [0..1] Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel n Nominal Bit Rate Configuration Register          */
+
+        struct
+        {
+            __IOM uint32_t NBRP   : 10; /*!< [9..0] Nominal Bit Rate Prescaler                                         */
+            __IOM uint32_t NSJW   : 7;  /*!< [16..10] Nominal Bit Rate Resynchronization Jump Width Control            */
+            __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Nominal Bit Rate Time Segment 1 Control                          */
+            __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Nominal Bit Rate Time Segment 2 Control                          */
+        } NCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel n Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t CHMDC   : 2; /*!< [1..0] Mode Select                                                        */
+            __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Stop Mode                                                  */
+            __IOM uint32_t RTBO    : 1; /*!< [3..3] Forcible Return from Bus-Off                                       */
+            uint32_t               : 4;
+            __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
+            __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
+            __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
+            __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
+            __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
+            __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
+            __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
+            __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
+            __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission Abort Interrupt Enable                              */
+            __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error Occurrence Counter Overflow Interrupt Enable               */
+            __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt Enable          */
+            __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
+                                         *   Enable                                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t BOM  : 2;    /*!< [22..21] Bus-Off Recovery Mode Select                                     */
+            __IOM uint32_t ERRD : 1;    /*!< [23..23] Error Display Mode Select                                        */
+            __IOM uint32_t CTME : 1;    /*!< [24..24] Communication Test Mode Enable                                   */
+            __IOM uint32_t CTMS : 2;    /*!< [26..25] Communication Test Mode Select                                   */
+            uint32_t            : 3;
+            __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test Enable                                            */
+            __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode Enable                                 */
+        } CTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel n Status Register                                  */
+
+        struct
+        {
+            __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel Reset Status Flag                                          */
+            __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel Halt Status Flag                                           */
+            __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel Stop Status Flag                                           */
+            __IM uint32_t  EPSTS   : 1; /*!< [3..3] Error Passive Status Flag                                          */
+            __IM uint32_t  BOSTS   : 1; /*!< [4..4] Bus-Off Status Flag                                                */
+            __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Transmit Status Flag                                               */
+            __IM uint32_t  RECSTS  : 1; /*!< [6..6] Receive Status Flag                                                */
+            __IM uint32_t  COMSTS  : 1; /*!< [7..7] Communication Status Flag                                          */
+            __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
+            uint32_t               : 7;
+            __IM uint32_t REC      : 8; /*!< [23..16] Reception Error Count                                            */
+            __IM uint32_t TEC      : 8; /*!< [31..24] Transmission Error Count                                         */
+        } STS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel n Error Flag Register                              */
+
+        struct
+        {
+            __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
+            __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
+            __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
+            __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
+            __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
+            __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
+            __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
+            __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
+            __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error Flag                                                   */
+            __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error Flag                                                    */
+            __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error Flag                                           */
+            __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error Flag                                                   */
+            __IOM uint32_t B1ERR : 1;  /*!< [12..12] Recessive Bit Error Flag                                         */
+            __IOM uint32_t B0ERR : 1;  /*!< [13..13] Dominant Bit Error Flag                                          */
+            __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error Flag                                 */
+            uint32_t             : 1;
+            __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Calculation Data (CRC length: 15 bits)                       */
+            uint32_t             : 1;
+        } ERFL_b;
+    };
+} R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bit Rate Configuration Register               */
+
+        struct
+        {
+            __IOM uint32_t DBRP   : 8; /*!< [7..0] Data Bit Rate Prescaler Division Ratio Setting                     */
+            __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Data Bit Rate Time Segment 1 Control                              */
+            uint32_t              : 3;
+            __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Data Bit Rate Time Segment 2 Control                             */
+            uint32_t              : 4;
+            __IOM uint32_t DSJW   : 4; /*!< [27..24] Data Bit Rate Resynchronization Jump Width Control               */
+            uint32_t              : 4;
+        } DCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel n CAN-FD Configuration Register                    */
+
+        struct
+        {
+            __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
+            uint32_t              : 5;
+            __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transmitter Delay Compensation Offset Configuration                */
+            __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
+            __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
+            uint32_t              : 5;
+            __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
+            __IOM uint32_t GWEN   : 1; /*!< [24..24] CAN2.0, CAN-FD Multi Gateway Enable                              */
+            __IOM uint32_t GWFDF  : 1; /*!< [25..25] Gateway FDF Configuration Bit                                    */
+            __IOM uint32_t GWBRS  : 1; /*!< [26..26] Gateway BRS Configuration Bit                                    */
+            uint32_t              : 1;
+            __IOM uint32_t FDOE   : 1; /*!< [28..28] FD-Only Enable                                                   */
+            __IOM uint32_t REFE   : 1; /*!< [29..29] RX Edge Filter Enable                                            */
+            __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN-Only Enable                                        */
+            __IOM uint32_t CFDTE  : 1; /*!< [31..31] CAN-FD Frame Distinction Enable                                  */
+        } FDCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel n CAN-FD Control Register                          */
+
+        struct
+        {
+            __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
+            __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
+            uint32_t              : 30;
+        } FDCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel n CAN-FD Status Register                           */
+
+        struct
+        {
+            __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
+            __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error Occurrence Counter Overflow Flag                             */
+            __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful Occurrence Counter Overflow Flag                        */
+            uint32_t             : 5;
+            __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
+            __IM uint32_t  EOC   : 8;  /*!< [23..16] Error Occurrence Counter                                         */
+            __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful Occurrence Counter                                    */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t FDCRC;           /*!< (@ 0x00000010) Channel n CAN-FD CRC Register                              */
+
+        struct
+        {
+            __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register Value                                                */
+            uint32_t             : 4;
+            __IM uint32_t SCNT   : 4;  /*!< [28..25] Stuff Bit Count                                                  */
+            uint32_t             : 3;
+        } FDCRC_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t BLCT;           /*!< (@ 0x00000018) Channel n Bus Load Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t BLCE : 1;   /*!< [0..0] Bus Load Counter Enable                                            */
+            uint32_t            : 7;
+            __OM uint32_t BLCLD : 1;   /*!< [8..8] Bus Load Counter Load                                              */
+            uint32_t            : 23;
+        } BLCT_b;
+    };
+
+    union
+    {
+        __IM uint32_t BLSTS;           /*!< (@ 0x0000001C) Channel n Bus Load Status Register                         */
+
+        struct
+        {
+            uint32_t          : 3;
+            __IM uint32_t BLC : 29;    /*!< [31..3] Bus Load Counter Status                                           */
+        } BLSTS_b;
+    };
+} R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
+
+/**
+ * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Register n                */
+
+        struct
+        {
+            __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
+            __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
+            __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
+            __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Register n              */
+
+        struct
+        {
+            __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
+            __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
+            __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
+            __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
+        } M_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Register
+                                          *                  n                                                          */
+
+        struct
+        {
+            __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
+            __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing Destination
+                                          *   0                                                                         */
+            __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing Destination
+                                          *   1                                                                         */
+            __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing Destination
+                                          *   2                                                                         */
+            __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
+            __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
+                                          *   Pointer                                                                   */
+            uint32_t               : 2;
+            __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
+            __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer                            */
+        } P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1;               /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Register
+                                          *                  n                                                          */
+
+        struct
+        {
+            __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer              */
+            uint32_t               : 18;
+        } P1_b;
+    };
+} R_CANFD_CFDGAFL_Type;                  /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
+
+        struct
+        {
+            __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
+            uint32_t            : 1;
+            __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Bit                                        */
+            __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
+
+        struct
+        {
+            __IOM uint32_t RMTS  : 16; /*!< [15..0] RX Message Buffer Timestamp Field                                 */
+            uint32_t             : 12;
+            __IOM uint32_t RMDLC : 4;  /*!< [31..28] RX Message Buffer DLC Field                                      */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
+
+        struct
+        {
+            __IOM uint32_t RMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t RMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t RMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t RMIFL : 2;  /*!< [9..8] RX Message Buffer Information Label Field                          */
+            uint32_t             : 6;
+            __IOM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field                                  */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p
+                                            *                  = 0 to 15, n = 0 to 31)                                    */
+
+            struct
+            {
+                __IM uint32_t RMDB_LL : 8; /*!< [7..0] RX Message Buffer Data Byte (4 * p)                               */
+                __IM uint32_t RMDB_LH : 8; /*!< [15..8] RX Message Buffer Data Byte (4 * p + 1)                          */
+                __IM uint32_t RMDB_HL : 8; /*!< [23..16] RX Message Buffer Data Byte (4 * p + 2)                         */
+                __IM uint32_t RMDB_HH : 8; /*!< [31..24] RX Message Buffer Data Byte (4 * p + 3)                         */
+            } DF_WD_b[16];
+        };
+
+        union
+        {
+            __IM uint8_t DF[64];       /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p
+                                        *                  = 0 to 63, n = 0 to 31)                                    */
+
+            struct
+            {
+                __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte                                        */
+            } DF_b[64];
+        };
+    };
+    __IM uint32_t RESERVED[13];
+} R_CANFD_CFDRM_Type;                  /*!< Size = 128 (0x80)                                                         */
+
+/**
+ * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register n                               */
+
+        struct
+        {
+            __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
+            uint32_t            : 1;
+            __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR bit                                           */
+            __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE bit                                           */
+        } ID_b;
+    };
+
+    union
+    {
+        __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register n                          */
+
+        struct
+        {
+            __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Value                                           */
+            uint32_t            : 12;
+            __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FDSTS;             /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register n                    */
+
+        struct
+        {
+            __IM uint32_t RFESI    : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IM uint32_t RFBRS    : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IM uint32_t RFFDF    : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t               : 5;
+            __IM uint32_t RFIFL    : 2;  /*!< [9..8] RX FIFO Buffer Information Label Field                             */
+            uint32_t               : 6;
+            __IM uint32_t CFDRFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0
+                                            *                  to 15, n = 0 to 7)                                         */
+
+            struct
+            {
+                __IM uint32_t RFDB_LL : 8; /*!< [7..0] RX FIFO Buffer Data Byte (4 * p)                                  */
+                __IM uint32_t RFDB_LH : 8; /*!< [15..8] RX FIFO Buffer Data Byte (4 * p + 1)                             */
+                __IM uint32_t RFDB_HL : 8; /*!< [23..16] RX FIFO Buffer Data Byte (4 * p + 2)                            */
+                __IM uint32_t RFDB_HH : 8; /*!< [31..24] RX FIFO Buffer Data Byte (4 * p + 3)                            */
+            } DF_WD_b[16];
+        };
+
+        union
+        {
+            __IM uint8_t DF[64];       /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0
+                                        *                  to 63, n = 0 to 7)                                         */
+
+            struct
+            {
+                __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte                                           */
+            } DF_b[64];
+        };
+    };
+    __IM uint32_t RESERVED[13];
+} R_CANFD_CFDRF_Type;                  /*!< Size = 128 (0x80)                                                         */
+
+/**
+ * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
+
+        struct
+        {
+            __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
+            __IOM uint32_t THLEN : 1;  /*!< [29..29] THL Entry Enable                                                 */
+            __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR bit                                       */
+            __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE bit                                       */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register n                      */
+
+        struct
+        {
+            __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Value                                       */
+            uint32_t             : 12;
+            __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCSTS;         /*!< (@ 0x00000008) Common FIFO Access CAN-FD Control/Status Register
+                                        *                  n                                                          */
+
+        struct
+        {
+            __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t CFIFL : 2;  /*!< [9..8] COMMON FIFO Buffer Information Label Field                         */
+            uint32_t             : 6;
+            __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
+        } FDCSTS_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p
+                                             *                  = 0 to 15, n = 0 to 5)                                     */
+
+            struct
+            {
+                __IOM uint32_t CFDB_LL : 8; /*!< [7..0] Common FIFO Buffer Data Bytes (4 * p)                             */
+                __IOM uint32_t CFDB_LH : 8; /*!< [15..8] Common FIFO Buffer Data Bytes (4 * p + 1)                        */
+                __IOM uint32_t CFDB_HL : 8; /*!< [23..16] Common FIFO Buffer Data Bytes (4 * p + 2)                       */
+                __IOM uint32_t CFDB_HH : 8; /*!< [31..24] Common FIFO Buffer Data Bytes (4 * p + 3)                       */
+            } DF_WD_b[16];
+        };
+
+        union
+        {
+            __IOM uint8_t DF[64];       /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p
+                                         *                  = 0 to 63, n = 0 to 5)                                     */
+
+            struct
+            {
+                __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Bytes                                      */
+            } DF_b[64];
+        };
+    };
+    __IM uint32_t RESERVED[13];
+} R_CANFD_CFDCF_Type;                  /*!< Size = 128 (0x80)                                                         */
+
+/**
+ * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
+
+        struct
+        {
+            __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
+            __IM uint32_t BN   : 7;    /*!< [9..3] Buffer Number                                                      */
+            uint32_t           : 5;
+            __IM uint32_t TGW  : 1;    /*!< [15..15] Transmit Gateway Buffer Indication                               */
+            __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
+        } ACC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACC1;            /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
+
+        struct
+        {
+            __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
+            __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
+            uint32_t           : 14;
+        } ACC1_b;
+    };
+} R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register n (n = 0 to 127)             */
+
+        struct
+        {
+            __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
+            __IOM uint32_t THLEN : 1;  /*!< [29..29] Tx History List Entry                                            */
+            __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR bit                                        */
+            __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE bit                                        */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register n (n = 0 to
+                                        *                  127)                                                       */
+
+        struct
+        {
+            uint32_t             : 28;
+            __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register n (n
+                                        *                  = 0 to 127)                                                */
+
+        struct
+        {
+            __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
+            uint32_t             : 6;
+            __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
+        } FDCTR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p
+                                             *                  = 0 to 15, n = 0 to 127)                                   */
+
+            struct
+            {
+                __IOM uint32_t TMDB_LL : 8; /*!< [7..0] TX Message Buffer Data Byte (4 * p)                               */
+                __IOM uint32_t TMDB_LH : 8; /*!< [15..8] TX Message Buffer Data Byte (4 * p + 1)                          */
+                __IOM uint32_t TMDB_HL : 8; /*!< [23..16] TX Message Buffer Data Byte (4 * p + 2)                         */
+                __IOM uint32_t TMDB_HH : 8; /*!< [31..24] TX Message Buffer Data Byte (4 * p + 3)                         */
+            } DF_WD_b[16];
+        };
+
+        union
+        {
+            __IOM uint8_t DF[64];       /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p
+                                         *                  = 0 to 63, n = 0 to 5)                                     */
+
+            struct
+            {
+                __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Bytes                                       */
+            } DF_b[64];
+        };
+    };
+    __IM uint32_t RESERVED[13];
+} R_CANFD_CFDTM_Type;                  /*!< Size = 128 (0x80)                                                         */
+
+/**
+ * @brief R_CMT_UNT_CM [CM] (2 Timer Start Register Pairs)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CR;             /*!< (@ 0x00000000) Compare Match Timer Control Register                       */
+
+        struct
+        {
+            __IOM uint16_t CKS  : 2;   /*!< [1..0] Clock Select                                                       */
+            uint16_t            : 4;
+            __IOM uint16_t CMIE : 1;   /*!< [6..6] Compare Match Interrupt Enable                                     */
+            uint16_t            : 9;
+        } CR_b;
+    };
+    __IOM uint16_t CNT;                /*!< (@ 0x00000002) Compare Match Timer Counter Register                       */
+    __IOM uint16_t COR;                /*!< (@ 0x00000004) Compare Match Timer Constant Register                      */
+} R_CMT_UNT_CM_Type;                   /*!< Size = 6 (0x6)                                                            */
+
+/**
+ * @brief R_CMT_UNT [UNT] (3 Timer Start Register Units)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CMSTR0;         /*!< (@ 0x00000000) Compare Match Timer Start Register                         */
+
+        struct
+        {
+            __IOM uint16_t STR0 : 1;   /*!< [0..0] CMT Channel n Count Start                                          */
+            __IOM uint16_t STR1 : 1;   /*!< [1..1] CMT Channel n+1 Count Start                                        */
+            uint16_t            : 14;
+        } CMSTR0_b;
+    };
+    __IOM R_CMT_UNT_CM_Type CM[2];     /*!< (@ 0x00000002) 2 Timer Start Register Pairs                               */
+    __IM uint16_t           RESERVED[505];
+} R_CMT_UNT_Type;                      /*!< Size = 1024 (0x400)                                                       */
+
+/**
+ * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L y (y = 0 to 2)                    */
+
+        struct
+        {
+            __IOM uint8_t SVA0 : 1;    /*!< [0..0] 10-bit Address LSB                                                 */
+            __IOM uint8_t SVA  : 7;    /*!< [7..1] 7-bit Address/10-bit Address Lower Bits                            */
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U y (y = 0 to 2)                    */
+
+        struct
+        {
+            __IOM uint8_t FS  : 1;     /*!< [0..0] 7-bit/10-bit Address Format Select                                 */
+            __IOM uint8_t SVA : 2;     /*!< [2..1] 10-bit Address Upper Bits                                          */
+            uint8_t           : 5;
+        } U_b;
+    };
+} R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_DMAC0_GRP_CH_N [N] (DMAC Address Registers [0..1])
+ */
+typedef struct
+{
+    __IOM uint32_t SA;                 /*!< (@ 0x00000000) Nextm0 Source Address Register n (m = 0, 1) (n
+                                        *                  = 0 to 7)                                                  */
+    __IOM uint32_t DA;                 /*!< (@ 0x00000004) Nextm0 Destination Address Register n (m = 0,
+                                        *                  1) (n = 0 to 7)                                            */
+    __IOM uint32_t TB;                 /*!< (@ 0x00000008) Nextm0 Transaction Byte Register n (m = 0, 1)
+                                        *                  (n = 0 to 7)                                               */
+} R_DMAC0_GRP_CH_N_Type;               /*!< Size = 12 (0xc)                                                           */
+
+/**
+ * @brief R_DMAC0_GRP_CH [CH] (DMAC channel Control Register [0..7])
+ */
+typedef struct
+{
+    __IOM R_DMAC0_GRP_CH_N_Type N[2];  /*!< (@ 0x00000000) DMAC Address Registers [0..1]                              */
+    __IM uint32_t               CRSA;  /*!< (@ 0x00000018) Current Source Address Register n (n = 0 to 7)             */
+    __IM uint32_t               CRDA;  /*!< (@ 0x0000001C) Current Destination Address Register n (n = 0
+                                        *                  to 7)                                                      */
+    __IM uint32_t CRTB;                /*!< (@ 0x00000020) Current Transaction Byte Register n (n = 0 to
+                                        *                  7)                                                         */
+
+    union
+    {
+        __IM uint32_t CHSTAT;          /*!< (@ 0x00000024) Channel Status Register n (n = 0 to 7)                     */
+
+        struct
+        {
+            __IM uint32_t EN   : 1;    /*!< [0..0] DMA Activation Enable                                              */
+            __IM uint32_t RQST : 1;    /*!< [1..1] DMA Transfer Request                                               */
+            __IM uint32_t TACT : 1;    /*!< [2..2] DMAC Operating Status                                              */
+            __IM uint32_t SUS  : 1;    /*!< [3..3] Suspend                                                            */
+            __IM uint32_t ER   : 1;    /*!< [4..4] DMA Error                                                          */
+            __IM uint32_t END  : 1;    /*!< [5..5] DMA Transfer Completion Interrupt                                  */
+            __IM uint32_t TC   : 1;    /*!< [6..6] DMA Transfer Completion (total number of data bytes for
+                                        *   transaction)                                                              */
+            __IM uint32_t SR   : 1;    /*!< [7..7] Next Register Select                                               */
+            __IM uint32_t DL   : 1;    /*!< [8..8] Descriptor Load                                                    */
+            __IM uint32_t DW   : 1;    /*!< [9..9] Descriptor Write Back                                              */
+            __IM uint32_t DER  : 1;    /*!< [10..10] Descriptor Error                                                 */
+            __IM uint32_t MODE : 1;    /*!< [11..11] DMA Mode                                                         */
+            uint32_t           : 4;
+            __IM uint32_t INTM : 1;    /*!< [16..16] DMA Transfer Completion Interrupt Request Mask                   */
+            uint32_t           : 15;
+        } CHSTAT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHCTRL;          /*!< (@ 0x00000028) Channel Control Register n (n = 0 to 7)                    */
+
+        struct
+        {
+            __IOM uint32_t SETEN   : 1; /*!< [0..0] DMA Activation Enable                                              */
+            __IOM uint32_t CLREN   : 1; /*!< [1..1] DMA Activation Enable Clear                                        */
+            __IOM uint32_t STG     : 1; /*!< [2..2] Software Trigger                                                   */
+            __IOM uint32_t SWRST   : 1; /*!< [3..3] Software Reset                                                     */
+            __IOM uint32_t CLRRQ   : 1; /*!< [4..4] DMA Transfer Request Clear                                         */
+            __IOM uint32_t CLREND  : 1; /*!< [5..5] END Clear                                                          */
+            __IOM uint32_t CLRTC   : 1; /*!< [6..6] TC Clear                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t SETSUS  : 1; /*!< [8..8] Suspend Request                                                    */
+            __IOM uint32_t CLRSUS  : 1; /*!< [9..9] Suspend Clear                                                      */
+            uint32_t               : 6;
+            __IOM uint32_t SETINTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask                   */
+            __IOM uint32_t CLRINTM : 1; /*!< [17..17] DMA Transfer Completion Interrupt Request Mask Clear             */
+            uint32_t               : 14;
+        } CHCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHCFG;          /*!< (@ 0x0000002C) Channel Configuration Register n (n = 0 to 7)              */
+
+        struct
+        {
+            __IOM uint32_t SEL  : 3;   /*!< [2..0] Pin Select                                                         */
+            __IOM uint32_t REQD : 1;   /*!< [3..3] DMA Activation Request Source Select                               */
+            __IOM uint32_t LOEN : 1;   /*!< [4..4] L Detection Enable                                                 */
+            __IOM uint32_t HIEN : 1;   /*!< [5..5] H Detection Enable                                                 */
+            __IOM uint32_t LVL  : 1;   /*!< [6..6] Level Detection Enable                                             */
+            uint32_t            : 1;
+            __IOM uint32_t AM   : 3;   /*!< [10..8] ACK Mode                                                          */
+            uint32_t            : 1;
+            __IOM uint32_t SDS  : 4;   /*!< [15..12] Source Data Size                                                 */
+            __IOM uint32_t DDS  : 4;   /*!< [19..16] Destination Data Size                                            */
+            __IOM uint32_t SAD  : 1;   /*!< [20..20] Source Address Count Direction                                   */
+            __IOM uint32_t DAD  : 1;   /*!< [21..21] Destination Address Count Direction                              */
+            __IOM uint32_t TM   : 1;   /*!< [22..22] Transfer Mode                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t DEM  : 1;   /*!< [24..24] DMA Transfer Completion Interrupt Mask                           */
+            __IOM uint32_t TCM  : 1;   /*!< [25..25] TEND Mask                                                        */
+            uint32_t            : 1;
+            __IOM uint32_t SBE  : 1;   /*!< [27..27] Buffer Flush Enable                                              */
+            __IOM uint32_t RSEL : 1;   /*!< [28..28] Next Register Select                                             */
+            __IOM uint32_t RSW  : 1;   /*!< [29..29] RSEL Reverse                                                     */
+            __IOM uint32_t REN  : 1;   /*!< [30..30] Register Set Enable                                              */
+            __IOM uint32_t DMS  : 1;   /*!< [31..31] DMA Mode Select                                                  */
+        } CHCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHITVL;         /*!< (@ 0x00000030) Channel Interval Register n (n = 0 to 7)                   */
+
+        struct
+        {
+            __IOM uint32_t ITVL : 16;  /*!< [15..0] Interval                                                          */
+            uint32_t            : 16;
+        } CHITVL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHEXT;          /*!< (@ 0x00000034) Channel Extension Register n (n = 0 to 7)                  */
+
+        struct
+        {
+            __IOM uint32_t SPR : 3;    /*!< [2..0] Source PROT                                                        */
+            uint32_t           : 1;
+            __IOM uint32_t SCA : 4;    /*!< [7..4] Source CACHE                                                       */
+            __IOM uint32_t DPR : 3;    /*!< [10..8] Destination PROT                                                  */
+            uint32_t           : 1;
+            __IOM uint32_t DCA : 4;    /*!< [15..12] Destination CACHE                                                */
+            uint32_t           : 16;
+        } CHEXT_b;
+    };
+    __IOM uint32_t NXLA;               /*!< (@ 0x00000038) Next Link Address Register n (n = 0 to 7)                  */
+    __IM uint32_t  CRLA;               /*!< (@ 0x0000003C) Current Link Address Register n (n = 0 to 7)               */
+} R_DMAC0_GRP_CH_Type;                 /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_DMAC0_GRP [GRP] (8 channel Registers)
+ */
+typedef struct
+{
+    __IOM R_DMAC0_GRP_CH_Type CH[8];   /*!< (@ 0x00000000) DMAC channel Control Register [0..7]                       */
+    __IM uint32_t             RESERVED[64];
+
+    union
+    {
+        __IOM uint32_t DCTRL;          /*!< (@ 0x00000300) DMA Control Register A                                     */
+
+        struct
+        {
+            __IOM uint32_t PR    : 1;  /*!< [0..0] Priority Control Select                                            */
+            __IOM uint32_t LVINT : 1;  /*!< [1..1] Sets the interrupt output mode.                                    */
+            uint32_t             : 30;
+        } DCTRL_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IM uint32_t DSTAT_EN;        /*!< (@ 0x00000310) DMA Status EN Register A                                   */
+
+        struct
+        {
+            __IM uint32_t EN00 : 1;    /*!< [0..0] Channel 0 EN                                                       */
+            __IM uint32_t EN01 : 1;    /*!< [1..1] Channel 1 EN                                                       */
+            __IM uint32_t EN02 : 1;    /*!< [2..2] Channel 2 EN                                                       */
+            __IM uint32_t EN03 : 1;    /*!< [3..3] Channel 3 EN                                                       */
+            __IM uint32_t EN04 : 1;    /*!< [4..4] Channel 4 EN                                                       */
+            __IM uint32_t EN05 : 1;    /*!< [5..5] Channel 5 EN                                                       */
+            __IM uint32_t EN06 : 1;    /*!< [6..6] Channel 6 EN                                                       */
+            __IM uint32_t EN07 : 1;    /*!< [7..7] Channel 7 EN                                                       */
+            uint32_t           : 24;
+        } DSTAT_EN_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_ER;        /*!< (@ 0x00000314) DMA Status ER Register A                                   */
+
+        struct
+        {
+            __IM uint32_t ER00 : 1;    /*!< [0..0] Channel 0 ER                                                       */
+            __IM uint32_t ER01 : 1;    /*!< [1..1] Channel 1 ER                                                       */
+            __IM uint32_t ER02 : 1;    /*!< [2..2] Channel 2 ER                                                       */
+            __IM uint32_t ER03 : 1;    /*!< [3..3] Channel 3 ER                                                       */
+            __IM uint32_t ER04 : 1;    /*!< [4..4] Channel 4 ER                                                       */
+            __IM uint32_t ER05 : 1;    /*!< [5..5] Channel 5 ER                                                       */
+            __IM uint32_t ER06 : 1;    /*!< [6..6] Channel 6 ER                                                       */
+            __IM uint32_t ER07 : 1;    /*!< [7..7] Channel 7 ER                                                       */
+            uint32_t           : 24;
+        } DSTAT_ER_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_END;       /*!< (@ 0x00000318) DMA Status END Register A                                  */
+
+        struct
+        {
+            __IM uint32_t END00 : 1;   /*!< [0..0] Channel 0 END                                                      */
+            __IM uint32_t END01 : 1;   /*!< [1..1] Channel 1 END                                                      */
+            __IM uint32_t END02 : 1;   /*!< [2..2] Channel 2 END                                                      */
+            __IM uint32_t END03 : 1;   /*!< [3..3] Channel 3 END                                                      */
+            __IM uint32_t END04 : 1;   /*!< [4..4] Channel 4 END                                                      */
+            __IM uint32_t END05 : 1;   /*!< [5..5] Channel 5 END                                                      */
+            __IM uint32_t END06 : 1;   /*!< [6..6] Channel 6 END                                                      */
+            __IM uint32_t END07 : 1;   /*!< [7..7] Channel 7 END                                                      */
+            uint32_t            : 24;
+        } DSTAT_END_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IM uint32_t DSTAT_SUS;       /*!< (@ 0x00000320) DMA Status SUS Register A                                  */
+
+        struct
+        {
+            __IM uint32_t SUS00 : 1;   /*!< [0..0] Channel 0 SUS                                                      */
+            __IM uint32_t SUS01 : 1;   /*!< [1..1] Channel 1 SUS                                                      */
+            __IM uint32_t SUS02 : 1;   /*!< [2..2] Channel 2 SUS                                                      */
+            __IM uint32_t SUS03 : 1;   /*!< [3..3] Channel 3 SUS                                                      */
+            __IM uint32_t SUS04 : 1;   /*!< [4..4] Channel 4 SUS                                                      */
+            __IM uint32_t SUS05 : 1;   /*!< [5..5] Channel 5 SUS                                                      */
+            __IM uint32_t SUS06 : 1;   /*!< [6..6] Channel 6 SUS                                                      */
+            __IM uint32_t SUS07 : 1;   /*!< [7..7] Channel 7 SUS                                                      */
+            uint32_t            : 24;
+        } DSTAT_SUS_b;
+    };
+} R_DMAC0_GRP_Type;                    /*!< Size = 804 (0x324)                                                        */
+
+/**
+ * @brief R_PORT_DRCTL [DRCTL] (I/O Buffer [0..24] Function Switching Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t L;              /*!< (@ 0x00000000) I/O Buffer m Function Switching Register 0-3               */
+
+        struct
+        {
+            __IOM uint32_t DRV0 : 2;   /*!< [1..0] Pm_0 Driving Ability Control                                       */
+            __IOM uint32_t PUD0 : 2;   /*!< [3..2] Pm_0 Pull-Up/Down Control                                          */
+            __IOM uint32_t SMT0 : 1;   /*!< [4..4] Pm_0 Schmitt Trigger Control                                       */
+            __IOM uint32_t SR0  : 1;   /*!< [5..5] Pm_0 Slew Rate Control                                             */
+            uint32_t            : 2;
+            __IOM uint32_t DRV1 : 2;   /*!< [9..8] Pm_1 Driving Ability Control                                       */
+            __IOM uint32_t PUD1 : 2;   /*!< [11..10] Pm_1 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT1 : 1;   /*!< [12..12] Pm_1 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR1  : 1;   /*!< [13..13] Pm_1 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV2 : 2;   /*!< [17..16] Pm_2 Driving Ability Control                                     */
+            __IOM uint32_t PUD2 : 2;   /*!< [19..18] Pm_2 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT2 : 1;   /*!< [20..20] Pm_2 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR2  : 1;   /*!< [21..21] Pm_2 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV3 : 2;   /*!< [25..24] Pm_3 Driving Ability Control                                     */
+            __IOM uint32_t PUD3 : 2;   /*!< [27..26] Pm_3 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT3 : 1;   /*!< [28..28] Pm_3 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR3  : 1;   /*!< [29..29] Pm_3 Slew Rate Control                                           */
+            uint32_t            : 2;
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t H;              /*!< (@ 0x00000004) I/O Buffer m Function Switching Register 4-7               */
+
+        struct
+        {
+            __IOM uint32_t DRV4 : 2;   /*!< [1..0] Pm_4 Driving Ability Control                                       */
+            __IOM uint32_t PUD4 : 2;   /*!< [3..2] Pm_4 Pull-Up/Down Control                                          */
+            __IOM uint32_t SMT4 : 1;   /*!< [4..4] Pm_4 Schmitt Trigger Control                                       */
+            __IOM uint32_t SR4  : 1;   /*!< [5..5] Pm_4 Slew Rate Control                                             */
+            uint32_t            : 2;
+            __IOM uint32_t DRV5 : 2;   /*!< [9..8] Pm_5 Driving Ability Control                                       */
+            __IOM uint32_t PUD5 : 2;   /*!< [11..10] Pm_5 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT5 : 1;   /*!< [12..12] Pm_5 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR5  : 1;   /*!< [13..13] Pm_5 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV6 : 2;   /*!< [17..16] Pm_6 Driving Ability Control                                     */
+            __IOM uint32_t PUD6 : 2;   /*!< [19..18] Pm_6 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT6 : 1;   /*!< [20..20] Pm_6 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR6  : 1;   /*!< [21..21] Pm_6 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV7 : 2;   /*!< [25..24] Pm_7 Driving Ability Control                                     */
+            __IOM uint32_t PUD7 : 2;   /*!< [27..26] Pm_7 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT7 : 1;   /*!< [28..28] Pm_7 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR7  : 1;   /*!< [29..29] Pm_7 Slew Rate Control                                           */
+            uint32_t            : 2;
+        } H_b;
+    };
+} R_PORT_DRCTL_Type;                   /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_PORT_NSR_ELC_PDBF [ELC_PDBF] (ELC Port Buffer Register [0..1])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t BY;              /*!< (@ 0x00000000) ELC Port Buffer Register n                                 */
+
+        struct
+        {
+            __IOM uint8_t PB0 : 1;     /*!< [0..0] Port Buffer 0                                                      */
+            __IOM uint8_t PB1 : 1;     /*!< [1..1] Port Buffer 1                                                      */
+            __IOM uint8_t PB2 : 1;     /*!< [2..2] Port Buffer 2                                                      */
+            __IOM uint8_t PB3 : 1;     /*!< [3..3] Port Buffer 3                                                      */
+            __IOM uint8_t PB4 : 1;     /*!< [4..4] Port Buffer 4                                                      */
+            __IOM uint8_t PB5 : 1;     /*!< [5..5] Port Buffer 5                                                      */
+            __IOM uint8_t PB6 : 1;     /*!< [6..6] Port Buffer 6                                                      */
+            __IOM uint8_t PB7 : 1;     /*!< [7..7] Port Buffer 7                                                      */
+        } BY_b;
+    };
+    __IM uint8_t RESERVED[3];
+} R_PORT_NSR_ELC_PDBF_Type;            /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_ETHSW_PTP_SWTM [SWTM] (Ethernet Switch Timer output pins 0-3 Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t EN;             /*!< (@ 0x00000000) PTP Timer Pulse Output Enable n Register                   */
+
+        struct
+        {
+            __IOM uint32_t OUTEN : 1;  /*!< [0..0] Enable ETHSW_PTPOUTn Signal Output                                 */
+            uint32_t             : 31;
+        } EN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STSEC;          /*!< (@ 0x00000004) PTP Timer Pulse Start Second n Register                    */
+
+        struct
+        {
+            __IOM uint32_t STSEC : 32; /*!< [31..0] STSEC                                                             */
+        } STSEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STNS;           /*!< (@ 0x00000008) PTP Timer Pulse Start Nanosecond n Register                */
+
+        struct
+        {
+            __IOM uint32_t STNS : 32;  /*!< [31..0] Start Time by Nanosecond                                          */
+        } STNS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PSEC;           /*!< (@ 0x0000000C) PTP Timer Pulse Period Second n Register                   */
+
+        struct
+        {
+            __IOM uint32_t PSEC : 32;  /*!< [31..0] PSEC                                                              */
+        } PSEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PNS;            /*!< (@ 0x00000010) PTP Timer Pulse Period Nanosecond n Register               */
+
+        struct
+        {
+            __IOM uint32_t PNS : 32;   /*!< [31..0] Period by Nanosecond                                              */
+        } PNS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WTH;            /*!< (@ 0x00000014) PTP Timer Pulse Width n Register                           */
+
+        struct
+        {
+            __IOM uint32_t WIDTH : 16; /*!< [15..0] Set the Pulse Width of ETHSW_PTPOUTn in the cycle number
+                                        *   of ts_clk (8 ns).                                                         */
+            uint32_t : 16;
+        } WTH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAXP;           /*!< (@ 0x00000018) PTP Timer Pulse Max Second n Register                      */
+
+        struct
+        {
+            __IOM uint32_t MAXP : 32;  /*!< [31..0] Sets the boundary value in nanoseconds to carry from
+                                        *   the nanosecond field to the second field. The same value
+                                        *   as ATIME_EVT_PERIOD register must be set.                                 */
+        } MAXP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LATSEC;          /*!< (@ 0x0000001C) PTP Timer Pulse Latch Second n Register                    */
+
+        struct
+        {
+            __IOM uint32_t LATSEC : 32; /*!< [31..0] LATSEC                                                            */
+        } LATSEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LATNS;          /*!< (@ 0x00000020) PTP Timer Pulse Latch Nanosecond n Register                */
+
+        struct
+        {
+            __IOM uint32_t LATNS : 32; /*!< [31..0] LATNS                                                             */
+        } LATNS_b;
+    };
+    __IM uint32_t RESERVED[55];
+} R_ETHSW_PTP_SWTM_Type;               /*!< Size = 256 (0x100)                                                        */
+
+/**
+ * @brief R_ETHSW_MGMT_ADDR [MGMT_ADDR] (MAC Address [0..3] for Bridge Protocol Frame Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t lo;                /*!< (@ 0x00000000) Lower MAC Address                                          */
+
+        struct
+        {
+            __IOM uint32_t BPDU_DST : 32; /*!< [31..0] Additional MAC address defining a Bridge Protocol Frame
+                                           *   (BPDU) in addition to the commonly-known addresses                        */
+        } lo_b;
+    };
+
+    union
+    {
+        __IOM uint32_t hi;                /*!< (@ 0x00000004) Higher MAC Address                                         */
+
+        struct
+        {
+            __IOM uint32_t BPDU_DST : 16; /*!< [15..0] Bits [7:0] is 5th byte, bits [15:8] is 6th (last) byte            */
+            __IOM uint32_t MASK     : 8;  /*!< [23..16] 8-bit mask for comparing the last byte of the MAC address.       */
+            uint32_t                : 8;
+        } hi_b;
+    };
+} R_ETHSW_MGMT_ADDR_Type;                 /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_ESC_FMMU [FMMU] (FMMU [0..7] Registers (n = 0 to 7))
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t L_START_ADR;      /*!< (@ 0x00000000) FMMU Logical Start Address n Register (n = 0
+                                         *                  to 7)                                                      */
+
+        struct
+        {
+            __IM uint32_t LSTAADR : 32; /*!< [31..0] Logical Start Address Setting                                     */
+        } L_START_ADR_b;
+    };
+
+    union
+    {
+        __IM uint16_t LEN;              /*!< (@ 0x00000004) FMMU Length n Register (n = 0 to 7)                        */
+
+        struct
+        {
+            __IM uint16_t FMMULEN : 16; /*!< [15..0] Area Size Specification                                           */
+        } LEN_b;
+    };
+
+    union
+    {
+        __IM uint8_t L_START_BIT;      /*!< (@ 0x00000006) FMMU Logical Start Bit n Register (n = 0 to 7)             */
+
+        struct
+        {
+            __IM uint8_t LSTABIT : 3;  /*!< [2..0] Start Bit Setting                                                  */
+            uint8_t              : 5;
+        } L_START_BIT_b;
+    };
+
+    union
+    {
+        __IM uint8_t L_STOP_BIT;       /*!< (@ 0x00000007) FMMU Logical Stop Bit n Register (n = 0 to 7)              */
+
+        struct
+        {
+            __IM uint8_t LSTPBIT : 3;  /*!< [2..0] Last Bit Setting                                                   */
+            uint8_t              : 5;
+        } L_STOP_BIT_b;
+    };
+
+    union
+    {
+        __IM uint16_t P_START_ADR;        /*!< (@ 0x00000008) FMMU Physical Start Address n Register (n = 0
+                                           *                  to 7)                                                      */
+
+        struct
+        {
+            __IM uint16_t PHYSTAADR : 16; /*!< [15..0] Physical Start Address Setting                                    */
+        } P_START_ADR_b;
+    };
+
+    union
+    {
+        __IM uint8_t P_START_BIT;       /*!< (@ 0x0000000A) FMMU Physical Start Bit n Register (n = 0 to
+                                         *                  7)                                                         */
+
+        struct
+        {
+            __IM uint8_t PHYSTABIT : 3; /*!< [2..0] Physical Start Bit Setting                                         */
+            uint8_t                : 5;
+        } P_START_BIT_b;
+    };
+
+    union
+    {
+        __IM uint8_t TYPE;             /*!< (@ 0x0000000B) FMMU Type n Register (n = 0 to 7)                          */
+
+        struct
+        {
+            __IM uint8_t READ  : 1;    /*!< [0..0] Read Access Mapping Setting                                        */
+            __IM uint8_t WRITE : 1;    /*!< [1..1] Write Access Mapping Setting                                       */
+            uint8_t            : 6;
+        } TYPE_b;
+    };
+
+    union
+    {
+        __IM uint8_t ACT;              /*!< (@ 0x0000000C) FMMU Activate n Register (n = 0 to 7)                      */
+
+        struct
+        {
+            __IM uint8_t ACTIVATE : 1; /*!< [0..0] FMMU Enable/Disable                                                */
+            uint8_t               : 7;
+        } ACT_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+} R_ESC_FMMU_Type;                     /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_ESC_SM [SM] (SyncManager [0..7] Registers (n = 0 to 7))
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint16_t P_START_ADR;        /*!< (@ 0x00000000) SyncManager Physical Start Address n Register
+                                           *                  (n = 0 to 7)                                               */
+
+        struct
+        {
+            __IM uint16_t SMSTAADDR : 16; /*!< [15..0] Physical Start Address Setting                                    */
+        } P_START_ADR_b;
+    };
+
+    union
+    {
+        __IM uint16_t LEN;             /*!< (@ 0x00000002) SyncManager Length n Register (n = 0 to 7)                 */
+
+        struct
+        {
+            __IM uint16_t SMLEN : 16;  /*!< [15..0] Area Size Setting                                                 */
+        } LEN_b;
+    };
+
+    union
+    {
+        __IM uint8_t CONTROL;          /*!< (@ 0x00000004) SyncManager Control n Register (n = 0 to 7)                */
+
+        struct
+        {
+            __IM uint8_t OPEMODE : 2;  /*!< [1..0] Operating Mode Setting                                             */
+            __IM uint8_t DIR     : 2;  /*!< [3..2] Transfer Direction Setting                                         */
+            __IM uint8_t IRQECAT : 1;  /*!< [4..4] ECAT Event Interrupt Setting                                       */
+            __IM uint8_t IRQPDI  : 1;  /*!< [5..5] AL Event Interrupt Setting                                         */
+            __IM uint8_t WDTRGEN : 1;  /*!< [6..6] Watchdog Trigger Setting                                           */
+            uint8_t              : 1;
+        } CONTROL_b;
+    };
+
+    union
+    {
+        __IM uint8_t STATUS;           /*!< (@ 0x00000005) SyncManager Status n Register (n = 0 to 7)                 */
+
+        struct
+        {
+            __IM uint8_t INTWR    : 1; /*!< [0..0] Write Complete Interrupt State Indication                          */
+            __IM uint8_t INTRD    : 1; /*!< [1..1] Read Complete Interrupt State Indication                           */
+            uint8_t               : 1;
+            __IM uint8_t MAILBOX  : 1; /*!< [3..3] Mailbox Status Indication                                          */
+            __IM uint8_t BUFFERED : 2; /*!< [5..4] Buffer Status Indication                                           */
+            __IM uint8_t RDBUF    : 1; /*!< [6..6] Read State Indication                                              */
+            __IM uint8_t WRBUF    : 1; /*!< [7..7] Write State Indication                                             */
+        } STATUS_b;
+    };
+
+    union
+    {
+        __IM uint8_t ACT;               /*!< (@ 0x00000006) SyncManager Activate n Register (n = 0 to 7)               */
+
+        struct
+        {
+            __IM uint8_t SMEN      : 1; /*!< [0..0] SyncManager Enable/Disable                                         */
+            __IM uint8_t REPEATREQ : 1; /*!< [1..1] Repeat Request                                                     */
+            uint8_t                : 4;
+            __IM uint8_t LATCHECAT : 1; /*!< [6..6] ECAT Latch Event Specification                                     */
+            __IM uint8_t LATCHPDI  : 1; /*!< [7..7] PDI Latch Event Specification                                      */
+        } ACT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PDI_CONT;          /*!< (@ 0x00000007) SyncManager PDI Control n Register (n = 0 to
+                                          *                  7)                                                         */
+
+        struct
+        {
+            __IOM uint8_t DEACTIVE  : 1; /*!< [0..0] SyncManager Operation Indication/Setting                           */
+            __IOM uint8_t REPEATACK : 1; /*!< [1..1] Repeat Acknowledge                                                 */
+            uint8_t                 : 6;
+        } PDI_CONT_b;
+    };
+} R_ESC_SM_Type;                         /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_USBF_PIPE_TR [PIPE_TR] (PIPEn Transaction Counter Registers (n=1-5))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t E;              /*!< (@ 0x00000000) PIPEn Transaction Counter Enable Register                  */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
+            __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
+            uint16_t             : 6;
+        } E_b;
+    };
+
+    union
+    {
+        __IOM uint16_t N;               /*!< (@ 0x00000002) PIPEn Transaction Counter Register                         */
+
+        struct
+        {
+            __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
+        } N_b;
+    };
+} R_USBF_PIPE_TR_Type;                  /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_USBF_CHa_N [N] (Address Registers n (n=0-1))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t SA;             /*!< (@ 0x00000000) Next Source Address Register                               */
+
+        struct
+        {
+            __IOM uint32_t SAWD : 32;  /*!< [31..0] Source Address or Write Data                                      */
+        } SA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DA;             /*!< (@ 0x00000004) Next Destination Address Register                          */
+
+        struct
+        {
+            __IOM uint32_t DA : 32;    /*!< [31..0] Destination Address                                               */
+        } DA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TB;             /*!< (@ 0x00000008) Next Transaction Byte Register                             */
+
+        struct
+        {
+            __IOM uint32_t TB : 32;    /*!< [31..0] Transaction Byte                                                  */
+        } TB_b;
+    };
+} R_USBF_CHa_N_Type;                   /*!< Size = 12 (0xc)                                                           */
+
+/**
+ * @brief R_USBF_CHa [CHa] (Next Register Set)
+ */
+typedef struct
+{
+    __IOM R_USBF_CHa_N_Type N[2];      /*!< (@ 0x00000000) Address Registers n (n=0-1)                                */
+
+    union
+    {
+        __IM uint32_t CRSA;            /*!< (@ 0x00000018) Current Source Address Register                            */
+
+        struct
+        {
+            __IM uint32_t CRSA : 32;   /*!< [31..0] Source Address                                                    */
+        } CRSA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CRDA;            /*!< (@ 0x0000001C) Current Destination Address Register                       */
+
+        struct
+        {
+            __IM uint32_t CRDA : 32;   /*!< [31..0] Destination Address                                               */
+        } CRDA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CRTB;            /*!< (@ 0x00000020) Current Transaction Byte Register                          */
+
+        struct
+        {
+            __IM uint32_t CRTB : 32;   /*!< [31..0] Transaction Byte                                                  */
+        } CRTB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CHSTAT;          /*!< (@ 0x00000024) Channel Status Register                                    */
+
+        struct
+        {
+            __IM uint32_t EN     : 1;  /*!< [0..0] Enable                                                             */
+            __IM uint32_t RQST   : 1;  /*!< [1..1] Request                                                            */
+            __IM uint32_t TACT   : 1;  /*!< [2..2] Transaction Active                                                 */
+            __IM uint32_t SUS    : 1;  /*!< [3..3] Suspend                                                            */
+            __IM uint32_t ER     : 1;  /*!< [4..4] Error                                                              */
+            __IM uint32_t END    : 1;  /*!< [5..5] USB_FDMAn Interrupted                                              */
+            __IM uint32_t TC     : 1;  /*!< [6..6] Terminal Count                                                     */
+            __IM uint32_t SR     : 1;  /*!< [7..7] Selected Register Set                                              */
+            __IM uint32_t DL     : 1;  /*!< [8..8] Descriptor Load                                                    */
+            __IM uint32_t DW     : 1;  /*!< [9..9] Descriptor WriteBack                                               */
+            __IM uint32_t DER    : 1;  /*!< [10..10] Descriptor Error                                                 */
+            __IM uint32_t MODE   : 1;  /*!< [11..11] DMA Mode                                                         */
+            uint32_t             : 4;
+            __IM uint32_t INTM   : 1;  /*!< [16..16] Interrupt Mask                                                   */
+            __IM uint32_t DMARQM : 1;  /*!< [17..17] DMAREQ Mask                                                      */
+            __IM uint32_t SWPRQ  : 1;  /*!< [18..18] Sweep Request                                                    */
+            uint32_t             : 5;
+            __IM uint32_t DNUM   : 8;  /*!< [31..24] Data Number                                                      */
+        } CHSTAT_b;
+    };
+
+    union
+    {
+        __OM uint32_t CHCTRL;            /*!< (@ 0x00000028) Channel Control Register                                   */
+
+        struct
+        {
+            __OM uint32_t SETEN     : 1; /*!< [0..0] Set Enable                                                         */
+            __OM uint32_t CLREN     : 1; /*!< [1..1] Clear Enable                                                       */
+            __OM uint32_t STG       : 1; /*!< [2..2] Software Trigger                                                   */
+            __OM uint32_t SWRST     : 1; /*!< [3..3] Software Reset                                                     */
+            __OM uint32_t CLRRQ     : 1; /*!< [4..4] Clear Request                                                      */
+            __OM uint32_t CLREND    : 1; /*!< [5..5] Clear End                                                          */
+            __OM uint32_t CLRTC     : 1; /*!< [6..6] Clear TC                                                           */
+            __OM uint32_t CLRDER    : 1; /*!< [7..7] Clear DER                                                          */
+            __OM uint32_t SETSUS    : 1; /*!< [8..8] Set Suspend                                                        */
+            __OM uint32_t CLRSUS    : 1; /*!< [9..9] Clear Suspend                                                      */
+            uint32_t                : 2;
+            __OM uint32_t SETREN    : 1; /*!< [12..12] Set Register Set Enable                                          */
+            uint32_t                : 1;
+            __OM uint32_t SETSSWPRQ : 1; /*!< [14..14] Set Software Sweep Request                                       */
+            uint32_t                : 1;
+            __OM uint32_t SETINTM   : 1; /*!< [16..16] Set Interrupt Mask                                               */
+            __OM uint32_t CLRINTM   : 1; /*!< [17..17] Clear Interrupt Mask                                             */
+            __OM uint32_t SETDMARQM : 1; /*!< [18..18] SET DMAREQ Mask                                                  */
+            __OM uint32_t CLRDMARQM : 1; /*!< [19..19] Clear DMAREQ Mask                                                */
+            uint32_t                : 12;
+        } CHCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHCFG;          /*!< (@ 0x0000002C) Channel Configuration Register                             */
+
+        struct
+        {
+            __IOM uint32_t SEL  : 1;   /*!< [0..0] Terminal Select                                                    */
+            uint32_t            : 2;
+            __IOM uint32_t REQD : 1;   /*!< [3..3] Request Direction                                                  */
+            __IOM uint32_t LOEN : 1;   /*!< [4..4] Sets the transfer request signal between the USB control
+                                        *   and the DMAC.                                                             */
+            __IOM uint32_t HIEN : 1;   /*!< [5..5] Sets the transfer request signal between the USB control
+                                        *   and the DMAC.                                                             */
+            __IOM uint32_t LVL : 1;    /*!< [6..6] Sets the transfer request signal between the USB control
+                                        *   and the DMAC.                                                             */
+            uint32_t          : 1;
+            __IOM uint32_t AM : 3;     /*!< [10..8] These bits set the transfer request signal between the
+                                        *   USB control and the DMAC.                                                 */
+            __IOM uint32_t DRRP : 1;   /*!< [11..11] Descriptor Read Repeat                                           */
+            __IOM uint32_t SDS  : 4;   /*!< [15..12] Source Data Size                                                 */
+            __IOM uint32_t DDS  : 4;   /*!< [19..16] Destination Data Size                                            */
+            __IOM uint32_t SAD  : 1;   /*!< [20..20] Source Address Direction                                         */
+            __IOM uint32_t DAD  : 1;   /*!< [21..21] Destination Address Direction                                    */
+            __IOM uint32_t TM   : 1;   /*!< [22..22] Sets the transfer request signal between the USB control
+                                        *   and the DMAC.                                                             */
+            __IOM uint32_t WONLY : 1;  /*!< [23..23] Write Only Mode                                                  */
+            __IOM uint32_t DEM   : 1;  /*!< [24..24] USB_FDMAn Mask                                                   */
+            uint32_t             : 1;
+            __IOM uint32_t DIM   : 1;  /*!< [26..26] Descriptor Interrupt Mask                                        */
+            __IOM uint32_t SBE   : 1;  /*!< [27..27] Sweep Buffer Enable                                              */
+            __IOM uint32_t RSEL  : 1;  /*!< [28..28] Register Set Select                                              */
+            __IOM uint32_t RSW   : 1;  /*!< [29..29] Register Select Switch                                           */
+            __IOM uint32_t REN   : 1;  /*!< [30..30] Register Set Enable                                              */
+            __IOM uint32_t DMS   : 1;  /*!< [31..31] DMA Mode Select                                                  */
+        } CHCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHITVL;         /*!< (@ 0x00000030) Channel Interval Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ITVL : 16;  /*!< [15..0] Interval                                                          */
+            uint32_t            : 16;
+        } CHITVL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHEXT;          /*!< (@ 0x00000034) Channel Extension Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SPR : 4;    /*!< [3..0] Source PROT                                                        */
+            uint32_t           : 4;
+            __IOM uint32_t DPR : 4;    /*!< [11..8] Destination PROT                                                  */
+            uint32_t           : 20;
+        } CHEXT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NXLA;           /*!< (@ 0x00000038) Next Link Address Register                                 */
+
+        struct
+        {
+            __IOM uint32_t NXLA : 32;  /*!< [31..0] Next Link Address                                                 */
+        } NXLA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CRLA;            /*!< (@ 0x0000003C) Current Link Address Register                              */
+
+        struct
+        {
+            __IM uint32_t CRLA : 32;   /*!< [31..0] Current Link Address                                              */
+        } CRLA_b;
+    };
+} R_USBF_CHa_Type;                     /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_USBF_CHb [CHb] (Skip Register Set)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t SCNT;           /*!< (@ 0x00000000) Source Continuous Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SCNT : 32;  /*!< [31..0] Source Continuous                                                 */
+        } SCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSKP;           /*!< (@ 0x00000004) Source Skip Register                                       */
+
+        struct
+        {
+            __IOM uint32_t SSKP : 32;  /*!< [31..0] Source Skip                                                       */
+        } SSKP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DCNT;           /*!< (@ 0x00000008) Destination Continuous Register                            */
+
+        struct
+        {
+            __IOM uint32_t DCNT : 32;  /*!< [31..0] Destination Continuous                                            */
+        } DCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSKP;           /*!< (@ 0x0000000C) Destination Skip Register                                  */
+
+        struct
+        {
+            __IOM uint32_t DSKP : 32;  /*!< [31..0] Destination Skip                                                  */
+        } DSKP_b;
+    };
+    __IM uint32_t RESERVED[4];
+} R_USBF_CHb_Type;                     /*!< Size = 32 (0x20)                                                          */
+
+/**
+ * @brief R_XSPI0_CSa [CSa] (xSPI Command Map Configuration Register [0..1])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t CMCFG0;          /*!< (@ 0x00000000) xSPI Command Map Configuration Register 0 CSn              */
+
+        struct
+        {
+            __IOM uint32_t FFMT    : 2; /*!< [1..0] Frame format                                                       */
+            __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size                                                       */
+            uint32_t               : 12;
+            __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable                                           */
+            __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code                                             */
+        } CMCFG0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMCFG1;          /*!< (@ 0x00000004) xSPI Command Map Configuration Register 1 CSn              */
+
+        struct
+        {
+            __IOM uint32_t RDCMD  : 16; /*!< [15..0] Read command                                                      */
+            __IOM uint32_t RDLATE : 5;  /*!< [20..16] Read latency cycle                                               */
+            uint32_t              : 11;
+        } CMCFG1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMCFG2;          /*!< (@ 0x00000008) xSPI Command Map Configuration Register 2 CSn              */
+
+        struct
+        {
+            __IOM uint32_t WRCMD  : 16; /*!< [15..0] Write command                                                     */
+            __IOM uint32_t WRLATE : 5;  /*!< [20..16] Write latency cycle                                              */
+            uint32_t              : 11;
+        } CMCFG2_b;
+    };
+    __IM uint32_t RESERVED;
+} R_XSPI0_CSa_Type;                    /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_XSPI0_BUF [BUF] (xSPI Command Manual Buf [0..3])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t CDT;               /*!< (@ 0x00000000) xSPI Command Manual Type Buf                               */
+
+        struct
+        {
+            __IOM uint32_t CMDSIZE  : 2;  /*!< [1..0] Command Size                                                       */
+            __IOM uint32_t ADDSIZE  : 3;  /*!< [4..2] Address size                                                       */
+            __IOM uint32_t DATASIZE : 4;  /*!< [8..5] Write/Read Data Size                                               */
+            __IOM uint32_t LATE     : 5;  /*!< [13..9] Latency cycle                                                     */
+            uint32_t                : 1;
+            __IOM uint32_t TRTYPE   : 1;  /*!< [15..15] Transaction Type                                                 */
+            __IOM uint32_t CMD      : 16; /*!< [31..16] Command (1-2 bytes)                                              */
+        } CDT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDA;            /*!< (@ 0x00000004) xSPI Command Manual Address Buf                            */
+
+        struct
+        {
+            __IOM uint32_t ADD : 32;   /*!< [31..0] Address                                                           */
+        } CDA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDD0;           /*!< (@ 0x00000008) xSPI Command Manual Data 0 Buf                             */
+
+        struct
+        {
+            __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
+        } CDD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDD1;           /*!< (@ 0x0000000C) xSPI Command Manual Data 1 Buf                             */
+
+        struct
+        {
+            __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
+        } CDD1_b;
+    };
+} R_XSPI0_BUF_Type;                    /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_XSPI0_CSb [CSb] (xSPI Command Calibration Control register [0..1])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t CCCTL0;           /*!< (@ 0x00000000) xSPI Command Calibration Control Register 0 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CAEN     : 1; /*!< [0..0] Automatic Calibration Enable                                       */
+            __IOM uint32_t CANOWR   : 1; /*!< [1..1] Calibration no write mode                                          */
+            uint32_t                : 6;
+            __IOM uint32_t CAITV    : 5; /*!< [12..8] Calibration interval                                              */
+            uint32_t                : 3;
+            __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value                                 */
+            uint32_t                : 3;
+            __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value                                   */
+            uint32_t                : 3;
+        } CCCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL1;             /*!< (@ 0x00000004) xSPI Command Calibration Control Register 1 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CACMDSIZE  : 2; /*!< [1..0] Command Size                                                       */
+            __IOM uint32_t CAADDSIZE  : 3; /*!< [4..2] Address size                                                       */
+            __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size                                               */
+            uint32_t                  : 7;
+            __IOM uint32_t CAWRLATE   : 5; /*!< [20..16] Write Latency cycle                                              */
+            uint32_t                  : 3;
+            __IOM uint32_t CARDLATE   : 5; /*!< [28..24] Read Latency cycle                                               */
+            uint32_t                  : 3;
+        } CCCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL2;           /*!< (@ 0x00000008) xSPI Command Calibration Control Register 2 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command                                 */
+            __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command                                 */
+        } CCCTL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL3;         /*!< (@ 0x0000000C) xSPI Command Calibration Control Register 3 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address                                       */
+        } CCCTL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL4;          /*!< (@ 0x00000010) xSPI Command Calibration Control Register 4 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
+        } CCCTL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL5;          /*!< (@ 0x00000014) xSPI Command Calibration Control Register 5 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
+        } CCCTL5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL6;          /*!< (@ 0x00000018) xSPI Command Calibration Control Register 6 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
+        } CCCTL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL7;          /*!< (@ 0x0000001C) xSPI Command Calibration Control Register 7 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
+        } CCCTL7_b;
+    };
+} R_XSPI0_CSb_Type;                     /*!< Size = 32 (0x20)                                                          */
+
+/**
+ * @brief R_SYSRAM0_W [W] (System SRAM Wn Registers (n = 0 to 3))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t EC710CTL;        /*!< (@ 0x00000000) ECC Control Register                                       */
+
+        struct
+        {
+            __IM uint32_t  ECEMF   : 1; /*!< [0..0] ECC Error Indicate Flag                                            */
+            __IM uint32_t  ECER1F  : 1; /*!< [1..1] 1-Bit ECC Error Detection/Correction Flag                          */
+            __IM uint32_t  ECER2F  : 1; /*!< [2..2] 2-Bit ECC Error Detection Flag                                     */
+            __IOM uint32_t EC1EDIC : 1; /*!< [3..3] 1-Bit ECC Error Detection Interrupt Control                        */
+            __IOM uint32_t EC2EDIC : 1; /*!< [4..4] 2-Bit ECC Error Detection Interrupt Control                        */
+            __IOM uint32_t EC1ECP  : 1; /*!< [5..5] 1-Bit ECC Error Correction Enable                                  */
+            __IOM uint32_t ECERVF  : 1; /*!< [6..6] ECC Error Determination Enable                                     */
+            __IOM uint32_t ECTHM   : 1; /*!< [7..7] ECC Function Through Mode Enable                                   */
+            uint32_t               : 1;
+            __IOM uint32_t ECER1C  : 1; /*!< [9..9] 1-Bit ECC Error Detection Clear                                    */
+            __IOM uint32_t ECER2C  : 1; /*!< [10..10] 2-Bit ECC Error Detection Clear                                  */
+            __IM uint32_t  ECOVFF  : 1; /*!< [11..11] ECC Error Address Capture Overflow Flag                          */
+            uint32_t               : 2;
+            __IOM uint32_t EMCA    : 2; /*!< [15..14] Access Control to ECC Mode Selection                             */
+            __IM uint32_t  ECEDF0  : 2; /*!< [17..16] ECC Error Address Capture Flag m (m = 0)                         */
+            __IM uint32_t  ECEDF1  : 2; /*!< [19..18] ECC Error Address Capture Flag m (m = 1)                         */
+            __IM uint32_t  ECEDF2  : 2; /*!< [21..20] ECC Error Address Capture Flag m (m = 2)                         */
+            __IM uint32_t  ECEDF3  : 2; /*!< [23..22] ECC Error Address Capture Flag m (m = 3)                         */
+            __IM uint32_t  ECEDF4  : 2; /*!< [25..24] ECC Error Address Capture Flag m (m = 4)                         */
+            __IM uint32_t  ECEDF5  : 2; /*!< [27..26] ECC Error Address Capture Flag m (m = 5)                         */
+            __IM uint32_t  ECEDF6  : 2; /*!< [29..28] ECC Error Address Capture Flag m (m = 6)                         */
+            __IM uint32_t  ECEDF7  : 2; /*!< [31..30] ECC Error Address Capture Flag m (m = 7)                         */
+        } EC710CTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EC710TMC;       /*!< (@ 0x00000004) ECC Test Mode Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t ECREIS : 1; /*!< [0..0] ECC Redundancy Bit Input Data Select                               */
+            __IOM uint32_t ECDCS  : 1; /*!< [1..1] ECC Decode Input Select                                            */
+            __IOM uint32_t ECENS  : 1; /*!< [2..2] ECC Encode Input Select                                            */
+            __IOM uint32_t ECREOS : 1; /*!< [3..3] ECC Redundancy Bit Output Data Select                              */
+            __IOM uint32_t ECTRRS : 1; /*!< [4..4] RAM Read Test Mode Select                                          */
+            uint32_t              : 2;
+            __IOM uint32_t ECTMCE : 1; /*!< [7..7] Test Mode Enable                                                   */
+            uint32_t              : 6;
+            __IOM uint32_t ETMA   : 2; /*!< [15..14] ECTMCE Write Enable                                              */
+            uint32_t              : 16;
+        } EC710TMC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EC710TRC;       /*!< (@ 0x00000008) ECC Redundancy Bit Data Control Test Register              */
+
+        struct
+        {
+            __IOM uint32_t ECERDB : 7; /*!< [6..0] ECC Redundancy Bit Input/Output Substitute Buffer Register         */
+            uint32_t              : 1;
+            __IM uint32_t ECECRD  : 7; /*!< [14..8] ECC Encode Test Register                                          */
+            uint32_t              : 1;
+            __IM uint32_t ECHORD  : 7; /*!< [22..16] ECC 7-Redundancy-Bit Data Retain Test Register                   */
+            uint32_t              : 1;
+            __IM uint32_t ECSYND  : 7; /*!< [30..24] ECC Decode Syndrome Register                                     */
+            uint32_t              : 1;
+        } EC710TRC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EC710TED;       /*!< (@ 0x0000000C) ECC Encode/Decode Input/Output Switchover Test
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t ECEDB : 32; /*!< [31..0] 32-Bit Data Test Register for ECC Encode/Decode                   */
+        } EC710TED_b;
+    };
+
+    union
+    {
+        __IM uint32_t EC710EAD[8];     /*!< (@ 0x00000010) ECC Error Address [0..7] Register 0                        */
+
+        struct
+        {
+            __IM uint32_t ECEAD : 15;  /*!< [14..0] Bit Error Address                                                 */
+            uint32_t            : 17;
+        } EC710EAD_b[8];
+    };
+    __IM uint32_t RESERVED[4];
+} R_SYSRAM0_W_Type;                    /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_MPU0_RGN [RGN] (Master MPU Safety Region Start Address Register [0..7])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t STADD;           /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register            */
+
+        struct
+        {
+            __IOM uint32_t RDPR   : 1;  /*!< [0..0] Enable read protection for region m of master MPU                  */
+            __IOM uint32_t WRPR   : 1;  /*!< [1..1] Enable write protection for region m of master MPU                 */
+            uint32_t              : 8;
+            __IOM uint32_t STADDR : 22; /*!< [31..10] Start address for MPU region                                     */
+        } STADD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDADD;         /*!< (@ 0x00000004) Master MPU Safety Region End Address Register              */
+
+        struct
+        {
+            uint32_t               : 10;
+            __IOM uint32_t ENDADDR : 22; /*!< [31..10] End address for MPU region                                       */
+        } ENDADD_b;
+    };
+    __IM uint32_t RESERVED[2];
+} R_MPU0_RGN_Type;                       /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_DSMIF0_CH [CH] (Channel Registers [0..2])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t DSICR;          /*!< (@ 0x00000000) Interrupt Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t IOEL : 1;   /*!< [0..0] Overcurrent lower limit detection interrupt enable                 */
+            __IOM uint32_t IOEH : 1;   /*!< [1..1] Overcurrent upper limit exceeded output interrupt enable           */
+            __IOM uint32_t ISE  : 1;   /*!< [2..2] Short circuit detection error interrupt enable                     */
+            __IOM uint32_t IUE  : 1;   /*!< [3..3] Current data register update interrupt enable                      */
+            uint32_t            : 28;
+        } DSICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCMCCR;        /*!< (@ 0x00000004) Current Measurement Clock Control Register                 */
+
+        struct
+        {
+            __IOM uint32_t CKDIR : 1;  /*!< [0..0] A/D conversion clock master/slave switching                        */
+            uint32_t             : 6;
+            __IOM uint32_t SEDGE : 1;  /*!< [7..7] Sampling edge selection                                            */
+            __IOM uint32_t CKDIV : 6;  /*!< [13..8] A/D conversion clock division ratio                               */
+            uint32_t             : 18;
+        } DSCMCCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCMFCR;        /*!< (@ 0x00000008) Current Measurement Filter Control Register                */
+
+        struct
+        {
+            __IOM uint32_t CMSINC : 2; /*!< [1..0] Current measurement filter order setting                           */
+            uint32_t              : 6;
+            __IOM uint32_t CMDEC  : 8; /*!< [15..8] Decimation ratio selection for current measurement                */
+            __IOM uint32_t CMSH   : 5; /*!< [20..16] Data shift setting for current measurement                       */
+            uint32_t              : 11;
+        } DSCMFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCMCTCR;       /*!< (@ 0x0000000C) Current Measurement Capture Trigger Control Register       */
+
+        struct
+        {
+            __IOM uint32_t CTSELA : 3; /*!< [2..0] Current capture trigger A selection bit                            */
+            uint32_t              : 5;
+            __IOM uint32_t CTSELB : 3; /*!< [10..8] Current capture trigger B selection bit                           */
+            uint32_t              : 5;
+            __IOM uint32_t DITSEL : 2; /*!< [17..16] Current measurement filter initialization trigger selection
+                                        *   bit for frequency division counter for decimation.                        */
+            uint32_t             : 5;
+            __IOM uint32_t DEDGE : 1;  /*!< [23..23] Current measurement filter initialization trigger for
+                                        *   division counter for decimation edge selection bit. The
+                                        *   trigger from ELC is usually used positive edge. Change
+                                        *   from the initial value if necessary.                                      */
+            uint32_t : 8;
+        } DSCMCTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSEDCR;         /*!< (@ 0x00000010) Error Detect Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t SDE : 1;    /*!< [0..0] Short circuit detection enable bit                                 */
+            uint32_t           : 31;
+        } DSEDCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSOCFCR;        /*!< (@ 0x00000014) Overcurrent Detect Filter Control Register                 */
+
+        struct
+        {
+            __IOM uint32_t OCSINC : 2; /*!< [1..0] Overcurrent detection filter order setting                         */
+            uint32_t              : 6;
+            __IOM uint32_t OCDEC  : 8; /*!< [15..8] Decimation ratio selection for overcurrent detection              */
+            __IOM uint32_t OCSH   : 5; /*!< [20..16] Data shift setting for overcurrent detection                     */
+            uint32_t              : 11;
+        } DSOCFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSOCLTR;          /*!< (@ 0x00000018) Overcurrent Low Threshold Register                         */
+
+        struct
+        {
+            __IOM uint32_t OCMPTBL : 16; /*!< [15..0] Overcurrent detection lower limit                                 */
+            uint32_t               : 16;
+        } DSOCLTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSOCHTR;          /*!< (@ 0x0000001C) Overcurrent High Threshold Register                        */
+
+        struct
+        {
+            __IOM uint32_t OCMPTBH : 16; /*!< [15..0] Overcurrent detection upper limit                                 */
+            uint32_t               : 16;
+        } DSOCHTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSCTSR;        /*!< (@ 0x00000020) Short Circuit Threshold Setting Register                   */
+
+        struct
+        {
+            __IOM uint32_t SCNTL : 13; /*!< [12..0] Short circuit detection low continuous detection count            */
+            uint32_t             : 3;
+            __IOM uint32_t SCNTH : 13; /*!< [28..16] Short circuit detection high continuous detection count          */
+            uint32_t             : 3;
+        } DSSCTSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSODCR;         /*!< (@ 0x00000024) Overcurrent Detect Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t ODEL : 1;   /*!< [0..0] Overcurrent lower limit detection enable bit                       */
+            __IOM uint32_t ODEH : 1;   /*!< [1..1] Overcurrent upper limit exceeded detection enable bit              */
+            uint32_t            : 30;
+        } DSODCR_b;
+    };
+    __IM uint32_t RESERVED[6];
+
+    union
+    {
+        __IOM uint32_t DSCSTRTR;       /*!< (@ 0x00000040) Software Start Trigger Register                            */
+
+        struct
+        {
+            __IOM uint32_t STRTRG : 1; /*!< [0..0] Channel start trigger                                              */
+            uint32_t              : 31;
+        } DSCSTRTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCSTPTR;       /*!< (@ 0x00000044) Software Stop Trigger Register                             */
+
+        struct
+        {
+            __IOM uint32_t STPTRG : 1; /*!< [0..0] Channel stop trigger                                               */
+            uint32_t              : 31;
+        } DSCSTPTR_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IM uint32_t DSCDR;           /*!< (@ 0x00000050) Current Data Register                                      */
+
+        struct
+        {
+            __IM uint32_t ADDR : 16;   /*!< [15..0] Current data                                                      */
+            uint32_t           : 16;
+        } DSCDR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCCDRA;         /*!< (@ 0x00000054) Capture Current Data Register A                            */
+
+        struct
+        {
+            __IM uint32_t CDRA : 16;   /*!< [15..0] Capture current data A                                            */
+            uint32_t           : 16;
+        } DSCCDRA_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCCDRB;         /*!< (@ 0x00000058) Capture Current Data Register B                            */
+
+        struct
+        {
+            __IM uint32_t CDRB : 16;   /*!< [15..0] Capture current data B                                            */
+            uint32_t           : 16;
+        } DSCCDRB_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSOCDR;          /*!< (@ 0x0000005C) Overcurrent Data Register                                  */
+
+        struct
+        {
+            __IM uint32_t ODR : 16;    /*!< [15..0] Overcurrent data                                                  */
+            uint32_t          : 16;
+        } DSOCDR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCOCDR;         /*!< (@ 0x00000060) Capture Overcurrent Data Register                          */
+
+        struct
+        {
+            __IM uint32_t CODR : 16;   /*!< [15..0] Capture Overcurrent data when overcurrent detected                */
+            uint32_t           : 16;
+        } DSCOCDR_b;
+    };
+    __IM uint32_t RESERVED2[7];
+
+    union
+    {
+        __IM uint32_t DSCSR;           /*!< (@ 0x00000080) Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t DUF     : 1; /*!< [0..0] Channel n data update flag                                         */
+            __IM uint32_t OCFL    : 1; /*!< [1..1] Channel n overcurrent lower limit detection flag                   */
+            __IM uint32_t OCFH    : 1; /*!< [2..2] Channel n overcurrent upper limit exceeded flag                    */
+            __IM uint32_t SCF     : 1; /*!< [3..3] Channel n short circuit detection flag                             */
+            uint32_t              : 12;
+            __IM uint32_t CHSTATE : 1; /*!< [16..16] Channel n state                                                  */
+            uint32_t              : 15;
+        } DSCSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCSCR;          /*!< (@ 0x00000084) Status Clear Register                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRDUF  : 1; /*!< [0..0] Channel n data update flag clear                                   */
+            __IOM uint32_t CLROCFL : 1; /*!< [1..1] Channel n overcurrent lower limit detection flag clear             */
+            __IOM uint32_t CLROCFH : 1; /*!< [2..2] Channel n overcurrent upper limit exceeded flag clear              */
+            __IOM uint32_t CLRSCF  : 1; /*!< [3..3] Channel n short circuit detection flag clear                       */
+            uint32_t               : 28;
+        } DSCSCR_b;
+    };
+    __IM uint32_t RESERVED3[2];
+} R_DSMIF0_CH_Type;                    /*!< Size = 144 (0x90)                                                         */
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GPT7                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief General PWM Timer 7 (R_GPT7)
+ */
+
+typedef struct                         /*!< (@ 0x80000000) R_GPT7 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
+
+        struct
+        {
+            __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disabled                                            */
+            __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disabled                                     */
+            __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disabled                                     */
+            __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disabled                                      */
+            __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
+            uint32_t             : 3;
+            __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
+            uint32_t             : 16;
+        } GTWP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTR;          /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
+
+        struct
+        {
+            __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel 0 Count Start                                              */
+            __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel 1 Count Start                                              */
+            __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel 2 Count Start                                              */
+            __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel 3 Count Start                                              */
+            __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel 4 Count Start                                              */
+            __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel 5 Count Start                                              */
+            __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel 6 Count Start                                              */
+            uint32_t              : 25;
+        } GTSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTP;          /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
+
+        struct
+        {
+            __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel 0 Count Stop                                               */
+            __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel 1 Count Stop                                               */
+            __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel 2 Count Stop                                               */
+            __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel 3 Count Stop                                               */
+            __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel 4 Count Stop                                               */
+            __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel 5 Count Stop                                               */
+            __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel 6 Count Stop                                               */
+            uint32_t              : 25;
+        } GTSTP_b;
+    };
+
+    union
+    {
+        __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
+
+        struct
+        {
+            __OM uint32_t CCLR0 : 1;   /*!< [0..0] Channel 0 Count Clear                                              */
+            __OM uint32_t CCLR1 : 1;   /*!< [1..1] Channel 1 Count Clear                                              */
+            __OM uint32_t CCLR2 : 1;   /*!< [2..2] Channel 2 Count Clear                                              */
+            __OM uint32_t CCLR3 : 1;   /*!< [3..3] Channel 3 Count Clear                                              */
+            __OM uint32_t CCLR4 : 1;   /*!< [4..4] Channel 4 Count Clear                                              */
+            __OM uint32_t CCLR5 : 1;   /*!< [5..5] Channel 5 Count Clear                                              */
+            __OM uint32_t CCLR6 : 1;   /*!< [6..6] Channel 6 Count Clear                                              */
+            uint32_t            : 25;
+        } GTCLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSSR;             /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t SSGTRGAFR : 2; /*!< [1..0] SSGTRGAFR                                                          */
+            __IOM uint32_t SSGTRGBFR : 2; /*!< [3..2] SSGTRGBFR                                                          */
+            __IOM uint32_t SSGTRGCFR : 2; /*!< [5..4] SSGTRGCFR                                                          */
+            __IOM uint32_t SSGTRGDFR : 2; /*!< [7..6] SSGTRGDFR                                                          */
+            __IOM uint32_t SSCARBHL  : 2; /*!< [9..8] SSCARBHL                                                           */
+            __IOM uint32_t SSCAFBHL  : 2; /*!< [11..10] SSCAFBHL                                                         */
+            __IOM uint32_t SSCBRAHL  : 2; /*!< [13..12] SSCBRAHL                                                         */
+            __IOM uint32_t SSCBFAHL  : 2; /*!< [15..14] SSCBFAHL                                                         */
+            __IOM uint32_t SSELCA    : 1; /*!< [16..16] SSELCA                                                           */
+            __IOM uint32_t SSELCB    : 1; /*!< [17..17] SSELCB                                                           */
+            __IOM uint32_t SSELCC    : 1; /*!< [18..18] SSELCC                                                           */
+            __IOM uint32_t SSELCD    : 1; /*!< [19..19] SSELCD                                                           */
+            __IOM uint32_t SSELCE    : 1; /*!< [20..20] SSELCE                                                           */
+            __IOM uint32_t SSELCF    : 1; /*!< [21..21] SSELCF                                                           */
+            __IOM uint32_t SSELCG    : 1; /*!< [22..22] SSELCG                                                           */
+            __IOM uint32_t SSELCH    : 1; /*!< [23..23] SSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CSTRT     : 1; /*!< [31..31] Software Source Count Start Enable                               */
+        } GTSSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPSR;             /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
+
+        struct
+        {
+            __IOM uint32_t PSGTRGAFR : 2; /*!< [1..0] PSGTRGAFR                                                          */
+            __IOM uint32_t PSGTRGBFR : 2; /*!< [3..2] PSGTRGBFR                                                          */
+            __IOM uint32_t PSGTRGCFR : 2; /*!< [5..4] PSGTRGCFR                                                          */
+            __IOM uint32_t PSGTRGDFR : 2; /*!< [7..6] PSGTRGDFR                                                          */
+            __IOM uint32_t PSCARBHL  : 2; /*!< [9..8] PSCARBHL                                                           */
+            __IOM uint32_t PSCAFBHL  : 2; /*!< [11..10] PSCAFBHL                                                         */
+            __IOM uint32_t PSCBRAHL  : 2; /*!< [13..12] PSCBRAHL                                                         */
+            __IOM uint32_t PSCBFAHL  : 2; /*!< [15..14] PSCBFAHL                                                         */
+            __IOM uint32_t PSELCA    : 1; /*!< [16..16] PSELCA                                                           */
+            __IOM uint32_t PSELCB    : 1; /*!< [17..17] PSELCB                                                           */
+            __IOM uint32_t PSELCC    : 1; /*!< [18..18] PSELCC                                                           */
+            __IOM uint32_t PSELCD    : 1; /*!< [19..19] PSELCD                                                           */
+            __IOM uint32_t PSELCE    : 1; /*!< [20..20] PSELCE                                                           */
+            __IOM uint32_t PSELCF    : 1; /*!< [21..21] PSELCF                                                           */
+            __IOM uint32_t PSELCG    : 1; /*!< [22..22] PSELCG                                                           */
+            __IOM uint32_t PSELCH    : 1; /*!< [23..23] PSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CSTOP     : 1; /*!< [31..31] CSTOP                                                            */
+        } GTPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCSR;             /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t CSGTRGAFR : 2; /*!< [1..0] CSGTRGAFR                                                          */
+            __IOM uint32_t CSGTRGBFR : 2; /*!< [3..2] CSGTRGBFR                                                          */
+            __IOM uint32_t CSGTRGCFR : 2; /*!< [5..4] CSGTRGCFR                                                          */
+            __IOM uint32_t CSGTRGDFR : 2; /*!< [7..6] CSGTRGDFR                                                          */
+            __IOM uint32_t CSCARBHL  : 2; /*!< [9..8] CSCARBHL                                                           */
+            __IOM uint32_t CSCAFBHL  : 2; /*!< [11..10] CSCAFBHL                                                         */
+            __IOM uint32_t CSCBRAHL  : 2; /*!< [13..12] CSCBRAHL                                                         */
+            __IOM uint32_t CSCBFAHL  : 2; /*!< [15..14] CSCBFAHL                                                         */
+            __IOM uint32_t CSELCA    : 1; /*!< [16..16] CSELCA                                                           */
+            __IOM uint32_t CSELCB    : 1; /*!< [17..17] CSELCB                                                           */
+            __IOM uint32_t CSELCC    : 1; /*!< [18..18] CSELCC                                                           */
+            __IOM uint32_t CSELCD    : 1; /*!< [19..19] CSELCD                                                           */
+            __IOM uint32_t CSELCE    : 1; /*!< [20..20] CSELCE                                                           */
+            __IOM uint32_t CSELCF    : 1; /*!< [21..21] CSELCF                                                           */
+            __IOM uint32_t CSELCG    : 1; /*!< [22..22] CSELCG                                                           */
+            __IOM uint32_t CSELCH    : 1; /*!< [23..23] CSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CCLR      : 1; /*!< [31..31] CCLR                                                             */
+        } GTCSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUPSR;            /*!< (@ 0x0000001C) General PWM Timer Count-Up Source Select Register          */
+
+        struct
+        {
+            __IOM uint32_t USGTRGAFR : 2; /*!< [1..0] USGTRGAFR                                                          */
+            __IOM uint32_t USGTRGBFR : 2; /*!< [3..2] USGTRGBFR                                                          */
+            __IOM uint32_t USGTRGCFR : 2; /*!< [5..4] USGTRGCFR                                                          */
+            __IOM uint32_t USGTRGDFR : 2; /*!< [7..6] USGTRGDFR                                                          */
+            __IOM uint32_t USCARBHL  : 2; /*!< [9..8] USCARBHL                                                           */
+            __IOM uint32_t USCAFBHL  : 2; /*!< [11..10] USCAFBHL                                                         */
+            __IOM uint32_t USCBRAHL  : 2; /*!< [13..12] USCBRAHL                                                         */
+            __IOM uint32_t USCBFAHL  : 2; /*!< [15..14] USCBFAHL                                                         */
+            __IOM uint32_t USELCA    : 1; /*!< [16..16] USELCA                                                           */
+            __IOM uint32_t USELCB    : 1; /*!< [17..17] USELCB                                                           */
+            __IOM uint32_t USELCC    : 1; /*!< [18..18] USELCC                                                           */
+            __IOM uint32_t USELCD    : 1; /*!< [19..19] USELCD                                                           */
+            __IOM uint32_t USELCE    : 1; /*!< [20..20] USELCE                                                           */
+            __IOM uint32_t USELCF    : 1; /*!< [21..21] USELCF                                                           */
+            __IOM uint32_t USELCG    : 1; /*!< [22..22] USELCG                                                           */
+            __IOM uint32_t USELCH    : 1; /*!< [23..23] USELCH                                                           */
+            uint32_t                 : 8;
+        } GTUPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDNSR;            /*!< (@ 0x00000020) General PWM Timer Count-Down Source Select Register        */
+
+        struct
+        {
+            __IOM uint32_t DSGTRGAFR : 2; /*!< [1..0] DSGTRGAFR                                                          */
+            __IOM uint32_t DSGTRGBFR : 2; /*!< [3..2] DSGTRGBFR                                                          */
+            __IOM uint32_t DSGTRGCFR : 2; /*!< [5..4] DSGTRGCFR                                                          */
+            __IOM uint32_t DSGTRGDFR : 2; /*!< [7..6] DSGTRGDFR                                                          */
+            __IOM uint32_t DSCARBHL  : 2; /*!< [9..8] DSCARBHL                                                           */
+            __IOM uint32_t DSCAFBHL  : 2; /*!< [11..10] DSCAFBHL                                                         */
+            __IOM uint32_t DSCBRAHL  : 2; /*!< [13..12] DSCBRAHL                                                         */
+            __IOM uint32_t DSCBFAHL  : 2; /*!< [15..14] DSCBFAHL                                                         */
+            __IOM uint32_t DSELCA    : 1; /*!< [16..16] DSELCA                                                           */
+            __IOM uint32_t DSELCB    : 1; /*!< [17..17] DSELCB                                                           */
+            __IOM uint32_t DSELCC    : 1; /*!< [18..18] DSELCC                                                           */
+            __IOM uint32_t DSELCD    : 1; /*!< [19..19] DSELCD                                                           */
+            __IOM uint32_t DSELCE    : 1; /*!< [20..20] DSELCE                                                           */
+            __IOM uint32_t DSELCF    : 1; /*!< [21..21] DSELCF                                                           */
+            __IOM uint32_t DSELCG    : 1; /*!< [22..22] DSELCG                                                           */
+            __IOM uint32_t DSELCH    : 1; /*!< [23..23] DSELCH                                                           */
+            uint32_t                 : 8;
+        } GTDNSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICASR;           /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
+                                           *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t ASGTRGAFR : 2; /*!< [1..0] ASGTRGAFR                                                          */
+            __IOM uint32_t ASGTRGBFR : 2; /*!< [3..2] ASGTRGBFR                                                          */
+            __IOM uint32_t ASGTRGCFR : 2; /*!< [5..4] ASGTRGCFR                                                          */
+            __IOM uint32_t ASGTRGDFR : 2; /*!< [7..6] ASGTRGDFR                                                          */
+            __IOM uint32_t ASCARBHL  : 2; /*!< [9..8] ASCARBHL                                                           */
+            __IOM uint32_t ASCAFBHL  : 2; /*!< [11..10] ASCAFBHL                                                         */
+            __IOM uint32_t ASCBRAHL  : 2; /*!< [13..12] ASCBRAHL                                                         */
+            __IOM uint32_t ASCBFAHL  : 2; /*!< [15..14] ASCBFAHL                                                         */
+            __IOM uint32_t ASELCA    : 1; /*!< [16..16] ASELCA                                                           */
+            __IOM uint32_t ASELCB    : 1; /*!< [17..17] ASELCB                                                           */
+            __IOM uint32_t ASELCC    : 1; /*!< [18..18] ASELCC                                                           */
+            __IOM uint32_t ASELCD    : 1; /*!< [19..19] ASELCD                                                           */
+            __IOM uint32_t ASELCE    : 1; /*!< [20..20] ASELCE                                                           */
+            __IOM uint32_t ASELCF    : 1; /*!< [21..21] ASELCF                                                           */
+            __IOM uint32_t ASELCG    : 1; /*!< [22..22] ASELCG                                                           */
+            __IOM uint32_t ASELCH    : 1; /*!< [23..23] ASELCH                                                           */
+            uint32_t                 : 8;
+        } GTICASR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICBSR;           /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
+                                           *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t BSGTRGAFR : 2; /*!< [1..0] BSGTRGAFR                                                          */
+            __IOM uint32_t BSGTRGBFR : 2; /*!< [3..2] BSGTRGBFR                                                          */
+            __IOM uint32_t BSGTRGCFR : 2; /*!< [5..4] BSGTRGCFR                                                          */
+            __IOM uint32_t BSGTRGDFR : 2; /*!< [7..6] BSGTRGDFR                                                          */
+            __IOM uint32_t BSCARBHL  : 2; /*!< [9..8] BSCARBHL                                                           */
+            __IOM uint32_t BSCAFBHL  : 2; /*!< [11..10] BSCAFBHL                                                         */
+            __IOM uint32_t BSCBRAHL  : 2; /*!< [13..12] BSCBRAHL                                                         */
+            __IOM uint32_t BSCBFAHL  : 2; /*!< [15..14] BSCBFAHL                                                         */
+            __IOM uint32_t BSELCA    : 1; /*!< [16..16] BSELCA                                                           */
+            __IOM uint32_t BSELCB    : 1; /*!< [17..17] BSELCB                                                           */
+            __IOM uint32_t BSELCC    : 1; /*!< [18..18] BSELCC                                                           */
+            __IOM uint32_t BSELCD    : 1; /*!< [19..19] BSELCD                                                           */
+            __IOM uint32_t BSELCE    : 1; /*!< [20..20] BSELCE                                                           */
+            __IOM uint32_t BSELCF    : 1; /*!< [21..21] BSELCF                                                           */
+            __IOM uint32_t BSELCG    : 1; /*!< [22..22] BSELCG                                                           */
+            __IOM uint32_t BSELCH    : 1; /*!< [23..23] BSELCH                                                           */
+            uint32_t                 : 8;
+        } GTICBSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
+            uint32_t            : 7;
+            __IOM uint32_t ICDS : 1;   /*!< [8..8] Input Capture Operation Select at Count Stop                       */
+            uint32_t            : 7;
+            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
+            uint32_t            : 4;
+            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
+            uint32_t            : 2;
+            __IOM uint32_t SWMD : 3;   /*!< [31..29] Switch Mode Select                                               */
+        } GTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
+            __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
+            uint32_t              : 14;
+            __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCnA Pin Output Duty Setting                                  */
+            __IOM uint32_t OADTYF : 1; /*!< [18..18] GTIOCnA Pin Output Duty Forced Setting                           */
+            __IOM uint32_t OADTYR : 1; /*!< [19..19] Output after Release of GTIOCnA Pin Output 0%/100%
+                                        *   Duty Cycle Settings                                                       */
+            uint32_t              : 4;
+            __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCnB Pin Output Duty Setting                                  */
+            __IOM uint32_t OBDTYF : 1; /*!< [26..26] GTIOCnB Pin Output Duty Forced Setting                           */
+            __IOM uint32_t OBDTYR : 1; /*!< [27..27] Output after Release of GTIOCnB Pin Output 0%/100%
+                                        *   Duty Cycle Settings                                                       */
+            uint32_t : 4;
+        } GTUDDTYC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCnA Pin Function Select                                        */
+            uint32_t              : 1;
+            __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCnA Pin Output Value Setting at the Count Stop                 */
+            __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCnA Pin Output Retention at the Start/Stop Count               */
+            __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCnA Pin Output Enable                                          */
+            __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCnA Pin Negate Value Setting                                  */
+            uint32_t              : 2;
+            __IOM uint32_t NFAEN  : 1; /*!< [13..13] GTIOCnA Pin Input Noise Filter Enable                            */
+            __IOM uint32_t NFCSA  : 2; /*!< [15..14] GTIOCnA Pin Input Noise Filter Sampling Clock Select             */
+            __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCnB Pin Function Select                                      */
+            uint32_t              : 1;
+            __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCnB Pin Output Value Setting at the Count Stop               */
+            __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCnB Pin Output Retention at the Start/Stop Count             */
+            __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCnB Pin Output Enable                                        */
+            __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCnB Pin Negate Value Setting                                 */
+            uint32_t              : 2;
+            __IOM uint32_t NFBEN  : 1; /*!< [29..29] GTIOCnB Pin Input Noise Filter Enable                            */
+            __IOM uint32_t NFCSB  : 2; /*!< [31..30] GTIOCnB Pin Input Noise Filter Sampling Clock Select             */
+        } GTIOR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTINTAD;          /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
+
+        struct
+        {
+            __IOM uint32_t GTINTA   : 1; /*!< [0..0] GTINTA                                                             */
+            __IOM uint32_t GTINTB   : 1; /*!< [1..1] GTINTB                                                             */
+            __IOM uint32_t GTINTC   : 1; /*!< [2..2] GTINTC                                                             */
+            __IOM uint32_t GTINTD   : 1; /*!< [3..3] GTINTD                                                             */
+            __IOM uint32_t GTINTE   : 1; /*!< [4..4] GTINTE                                                             */
+            __IOM uint32_t GTINTF   : 1; /*!< [5..5] GTINTF                                                             */
+            __IOM uint32_t GTINTPR  : 2; /*!< [7..6] GTINTPR                                                            */
+            uint32_t                : 8;
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] ADTRAUEN                                                         */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] ADTRADEN                                                         */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] ADTRBUEN                                                         */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] ADTRBDEN                                                         */
+            uint32_t                : 4;
+            __IOM uint32_t GRP      : 2; /*!< [25..24] Select the group to detect disabling of output (dead-time
+                                          *   error or simultaneous driving of outputs to the high or
+                                          *   low level) to POEG and to request of disabling of output
+                                          *   from POEG.                                                                */
+            uint32_t              : 2;
+            __IOM uint32_t GRPDTE : 1;   /*!< [28..28] GRPDTE                                                           */
+            __IOM uint32_t GRPABH : 1;   /*!< [29..29] (GTIOCnA pin and GTIOCnB output)                                 */
+            __IOM uint32_t GRPABL : 1;   /*!< [30..30] (GTIOCnA pin and GTIOCnB output)                                 */
+            uint32_t              : 1;
+        } GTINTAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTST;           /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IM uint32_t ITCNT    : 3; /*!< [10..8] GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter                */
+            uint32_t               : 4;
+            __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
+            __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Register Compare Match (Up-Counting) A/D Converter
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Register Compare Match (Down-Counting) A/D
+                                         *   Converter Start Request Flag                                              */
+            __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Register Compare Match (Up-Counting) A/D Converter
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Register Compare Match (Down-Counting) A/D
+                                         *   Converter Start Request Flag                                              */
+            uint32_t            : 4;
+            __IM uint32_t ODF   : 1;    /*!< [24..24] Output Stop Request Flag                                         */
+            uint32_t            : 3;
+            __IM uint32_t DTEF  : 1;    /*!< [28..28] Dead Time Error Flag                                             */
+            __IM uint32_t OABHF : 1;    /*!< [29..29] Simultaneous High Output Flag                                    */
+            __IM uint32_t OABLF : 1;    /*!< [30..30] Simultaneous Low Output Flag                                     */
+            uint32_t            : 1;
+        } GTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+
+        struct
+        {
+            __IOM uint32_t BD0     : 1; /*!< [0..0] GTCCRA/GTCCRB Registers Buffer Operation Disable                   */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] GTPR Register Buffer Operation Disable                             */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] GTADTRA/GTADTRB Registers Buffer Operation Disable                 */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] GTDVU/GTDVD Registers Buffer Operation Disable                     */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRA Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRB Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Register Buffer Operation                                 */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Register Buffer Operation                                 */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Register Buffer Operation                                   */
+            __IOM uint32_t CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Registers Forcible Buffer Operation            */
+            uint32_t               : 1;
+            __IOM uint32_t ADTTA   : 2; /*!< [25..24] GTADTRA Register Buffer Transfer Timing Select                   */
+            __IOM uint32_t ADTDA   : 1; /*!< [26..26] GTADTRA Register Double Buffer Operation                         */
+            uint32_t               : 1;
+            __IOM uint32_t ADTTB   : 2; /*!< [29..28] GTADTRB Register Buffer Transfer Timing Select                   */
+            __IOM uint32_t ADTDB   : 1; /*!< [30..30] GTADTRB Register Double Buffer Operation                         */
+            uint32_t               : 1;
+        } GTBER_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
+                                        *                  Start Request Skipping Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t ITLA  : 1;  /*!< [0..0] ITLA                                                               */
+            __IOM uint32_t ITLB  : 1;  /*!< [1..1] ITLB                                                               */
+            __IOM uint32_t ITLC  : 1;  /*!< [2..2] ITLC                                                               */
+            __IOM uint32_t ITLD  : 1;  /*!< [3..3] ITLD                                                               */
+            __IOM uint32_t ITLE  : 1;  /*!< [4..4] ITLE                                                               */
+            __IOM uint32_t ITLF  : 1;  /*!< [5..5] ITLF                                                               */
+            __IOM uint32_t IVTC  : 2;  /*!< [7..6] IVTC                                                               */
+            __IOM uint32_t IVTT  : 3;  /*!< [10..8] IVTT                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t ADTAL : 1;  /*!< [12..12] ADTAL                                                            */
+            uint32_t             : 1;
+            __IOM uint32_t ADTBL : 1;  /*!< [14..14] ADTBL                                                            */
+            uint32_t             : 17;
+        } GTITC_b;
+    };
+    __IOM uint32_t GTCNT;              /*!< (@ 0x00000048) General PWM Timer Counter                                  */
+    __IOM uint32_t GTCCR[6];           /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register m
+                                        *                  (m = A to F)                                               */
+    __IOM uint32_t GTPR;               /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
+    __IOM uint32_t GTPBR;              /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
+    __IOM uint32_t GTPDBR;             /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
+                                        *                  Register                                                   */
+    __IOM uint32_t GTADTRA;            /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A
+                                        *                  (m = A, B)                                                 */
+    __IOM uint32_t GTADTBRA;           /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
+                                        *                  A (m = A, B)                                               */
+    __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
+                                        *                  Register A                                                 */
+    __IOM uint32_t GTADTRB;            /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B
+                                        *                  (m = A, B)                                                 */
+    __IOM uint32_t GTADTBRB;           /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
+                                        *                  B (m = A, B)                                               */
+    __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
+                                        *                  Register B                                                 */
+
+    union
+    {
+        __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
+
+        struct
+        {
+            __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
+            uint32_t             : 3;
+            __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Register Buffer Operation Enable                             */
+            __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Register Buffer Operation Enable                             */
+            uint32_t             : 2;
+            __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Register Setting                                             */
+            uint32_t             : 23;
+        } GTDTCR_b;
+    };
+    __IOM uint32_t GTDVU;              /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U
+                                        *                  (m = U, D)                                                 */
+    __IOM uint32_t GTDVD;              /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D
+                                        *                  (m = U, D)                                                 */
+    __IOM uint32_t GTDBU;              /*!< (@ 0x00000094) General PWM Timer Dead Time Value Buffer Register
+                                        *                  U (m = U, D)                                               */
+    __IOM uint32_t GTDBD;              /*!< (@ 0x00000098) General PWM Timer Dead Time Value Buffer Register
+                                        *                  D (m = U, D)                                               */
+
+    union
+    {
+        __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
+                                        *                  Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
+            uint32_t          : 30;
+        } GTSOS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
+                                        *                  Temporary Release Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
+            uint32_t            : 31;
+        } GTSOTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   Select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA A/D Converter Start Request Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB A/D Converter Start Request Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
+    __IM uint32_t RESERVED[6];
+
+    union
+    {
+        __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
+                                         *                  Control Channel Select Register                            */
+
+        struct
+        {
+            __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            uint32_t : 25;
+        } GTSECSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
+            __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
+            __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
+            __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 20;
+        } GTSECR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSWSR;          /*!< (@ 0x000000D8) General PWM Timer Switch Source Select Register            */
+
+        struct
+        {
+            __IOM uint32_t WSGTRGA : 2; /*!< [1..0] GTETRGA Signal Edge Select to Switch Counter (GTETRGSA
+                                         *   Signal for SAFTY)                                                         */
+            __IOM uint32_t WSGTRGB : 2; /*!< [3..2] GTETRGB Signal Edge Select to Switch Counter (GTETRGSB
+                                         *   Signal for SAFTY)                                                         */
+            __IOM uint32_t WSGTRGC : 2; /*!< [5..4] GTETRGC Signal Edge Select to Switch Counter (GTETRGSC
+                                         *   Signal for SAFTY)                                                         */
+            __IOM uint32_t WSGTRGD : 2; /*!< [7..6] GTETRGD Signal Edge Select to Switch Counter (GTETRGSD
+                                         *   Signal for SAFTY)                                                         */
+            uint32_t              : 8;
+            __IOM uint32_t WSELCA : 1;  /*!< [16..16] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCB : 1;  /*!< [17..17] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCC : 1;  /*!< [18..18] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCD : 1;  /*!< [19..19] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCE : 1;  /*!< [20..20] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCF : 1;  /*!< [21..21] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCG : 1;  /*!< [22..22] Event Source Counter Switch Enable                               */
+            __IOM uint32_t CSELCH : 1;  /*!< [23..23] Event Source Counter Switch Enable                               */
+            uint32_t              : 8;
+        } GTSWSR_b;
+    };
+    __IOM uint32_t GTSWOS;              /*!< (@ 0x000000DC) General PWM Timer Switch Offset Setting Register           */
+} R_GPT0_Type;                          /*!< Size = 224 (0xe0)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Communication Interface 0 (R_SCI0)
+ */
+
+typedef struct                         /*!< (@ 0x80001000) R_SCI0 Structure                                           */
+{
+    union
+    {
+        __IM uint32_t RDR;             /*!< (@ 0x00000000) Receive Data Register                                      */
+
+        struct
+        {
+            __IM uint32_t RDAT : 9;    /*!< [8..0] Serial receive data                                                */
+            __IM uint32_t MPB  : 1;    /*!< [9..9] Multi-processor flag                                               */
+            __IM uint32_t DR   : 1;    /*!< [10..10] Receive data ready flag                                          */
+            __IM uint32_t FPER : 1;    /*!< [11..11] FIFO parity error flag                                           */
+            __IM uint32_t FFER : 1;    /*!< [12..12] FIFO framing error flag                                          */
+            uint32_t           : 11;
+            __IM uint32_t ORER : 1;    /*!< [24..24] Overrun Error flag                                               */
+            uint32_t           : 2;
+            __IM uint32_t PER  : 1;    /*!< [27..27] Parity error flag                                                */
+            __IM uint32_t FER  : 1;    /*!< [28..28] Framing error flag                                               */
+            uint32_t           : 3;
+        } RDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDR;            /*!< (@ 0x00000004) Transmit Data Register                                     */
+
+        struct
+        {
+            __IOM uint32_t TDAT : 9;   /*!< [8..0] Serial transmit data                                               */
+            __IOM uint32_t MPBT : 1;   /*!< [9..9] Multi-processor transfer bit flag                                  */
+            uint32_t            : 22;
+        } TDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR0;           /*!< (@ 0x00000008) Common Control Register 0                                  */
+
+        struct
+        {
+            __IOM uint32_t RE    : 1;  /*!< [0..0] Receive Enable                                                     */
+            uint32_t             : 3;
+            __IOM uint32_t TE    : 1;  /*!< [4..4] Transmit Enable                                                    */
+            uint32_t             : 3;
+            __IOM uint32_t MPIE  : 1;  /*!< [8..8] Multi-Processor Interrupt Enable                                   */
+            __IOM uint32_t DCME  : 1;  /*!< [9..9] Data Compare Match Enable                                          */
+            __IOM uint32_t IDSEL : 1;  /*!< [10..10] ID frame select                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t RIE   : 1;  /*!< [16..16] Receive Interrupt Enable                                         */
+            uint32_t             : 3;
+            __IOM uint32_t TIE   : 1;  /*!< [20..20] Transmit Interrupt Enable                                        */
+            __IOM uint32_t TEIE  : 1;  /*!< [21..21] Transmit End Interrupt Enable                                    */
+            uint32_t             : 2;
+            __IOM uint32_t SSE   : 1;  /*!< [24..24] SSn# Pin Function Enable                                         */
+            uint32_t             : 7;
+        } CCR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR1;           /*!< (@ 0x0000000C) Common Control Register 1                                  */
+
+        struct
+        {
+            __IOM uint32_t CTSE   : 1; /*!< [0..0] CTS Enable                                                         */
+            __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable                                            */
+            uint32_t              : 2;
+            __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select                                      */
+            __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O                                              */
+            uint32_t              : 2;
+            __IOM uint32_t PE     : 1; /*!< [8..8] Parity Enable                                                      */
+            __IOM uint32_t PM     : 1; /*!< [9..9] Parity Mode                                                        */
+            uint32_t              : 2;
+            __IOM uint32_t TINV   : 1; /*!< [12..12] TXD invert                                                       */
+            __IOM uint32_t RINV   : 1; /*!< [13..13] RXD invert                                                       */
+            uint32_t              : 2;
+            __IOM uint32_t SPLP   : 1; /*!< [16..16] Loopback Control                                                 */
+            uint32_t              : 3;
+            __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select                                 */
+            uint32_t              : 3;
+            __IOM uint32_t NFCS   : 3; /*!< [26..24] Noise Filter Clock Select                                        */
+            uint32_t              : 1;
+            __IOM uint32_t NFEN   : 1; /*!< [28..28] Digital Noise Filter Function Enable                             */
+            uint32_t              : 3;
+        } CCR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR2;           /*!< (@ 0x00000010) Common Control Register 2                                  */
+
+        struct
+        {
+            __IOM uint32_t BCP   : 3;  /*!< [2..0] Base Clock Pulse                                                   */
+            uint32_t             : 1;
+            __IOM uint32_t BGDM  : 1;  /*!< [4..4] Baud Rate Generator Double-Speed Mode Select                       */
+            __IOM uint32_t ABCS  : 1;  /*!< [5..5] Asynchronous Mode Base Clock Select                                */
+            __IOM uint32_t ABCSE : 1;  /*!< [6..6] Asynchronous Mode Extended Base Clock Select                       */
+            uint32_t             : 1;
+            __IOM uint32_t BRR   : 8;  /*!< [15..8] Bit rate setting                                                  */
+            __IOM uint32_t BRME  : 1;  /*!< [16..16] BRME                                                             */
+            uint32_t             : 3;
+            __IOM uint32_t CKS   : 2;  /*!< [21..20] Clock Select                                                     */
+            uint32_t             : 2;
+            __IOM uint32_t MDDR  : 8;  /*!< [31..24] Modulation Duty setting                                          */
+        } CCR2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR3;            /*!< (@ 0x00000014) Common Control Register 3                                  */
+
+        struct
+        {
+            __IOM uint32_t CPHA    : 1; /*!< [0..0] Clock Phase Select                                                 */
+            __IOM uint32_t CPOL    : 1; /*!< [1..1] Clock Polarity Select                                              */
+            uint32_t               : 5;
+            __IOM uint32_t BPEN    : 1; /*!< [7..7] Synchronizer bypass enable                                         */
+            __IOM uint32_t CHR     : 2; /*!< [9..8] Character Length                                                   */
+            uint32_t               : 2;
+            __IOM uint32_t LSBF    : 1; /*!< [12..12] LSB First select                                                 */
+            __IOM uint32_t SINV    : 1; /*!< [13..13] Transmitted/Received Data Invert                                 */
+            __IOM uint32_t STP     : 1; /*!< [14..14] Stop Bit Length                                                  */
+            __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select                     */
+            __IOM uint32_t MOD     : 3; /*!< [18..16] Communication mode select                                        */
+            __IOM uint32_t MP      : 1; /*!< [19..19] Multi-Processor Mode                                             */
+            __IOM uint32_t FM      : 1; /*!< [20..20] FIFO Mode select                                                 */
+            __IOM uint32_t DEN     : 1; /*!< [21..21] Driver enable                                                    */
+            uint32_t               : 2;
+            __IOM uint32_t CKE     : 2; /*!< [25..24] Clock enable                                                     */
+            uint32_t               : 2;
+            __IOM uint32_t GM      : 1; /*!< [28..28] GSM Mode                                                         */
+            __IOM uint32_t BLK     : 1; /*!< [29..29] Block Transfer Mode                                              */
+            uint32_t               : 2;
+        } CCR3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR4;           /*!< (@ 0x00000018) Common Control Register 4                                  */
+
+        struct
+        {
+            __IOM uint32_t CMPD : 9;   /*!< [8..0] Compare Match Data                                                 */
+            uint32_t            : 7;
+            __IOM uint32_t ASEN : 1;   /*!< [16..16] Adjust receive sampling timing enable                            */
+            __IOM uint32_t ATEN : 1;   /*!< [17..17] Adjust transmit timing enable                                    */
+            uint32_t            : 6;
+            __IOM uint32_t AST  : 3;   /*!< [26..24] Adjustment value for receive Sampling Timing                     */
+            __IOM uint32_t AJD  : 1;   /*!< [27..27] Adjustment Direction for receive sampling timing                 */
+            __IOM uint32_t ATT  : 3;   /*!< [30..28] Adjustment value for Transmit timing                             */
+            __IOM uint32_t AET  : 1;   /*!< [31..31] Adjustment edge for transmit timing                              */
+        } CCR4_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t ICR;                /*!< (@ 0x00000020) Simple I2C Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t IICDL      : 5; /*!< [4..0] SDA Delay Output Select                                            */
+            uint32_t                  : 3;
+            __IOM uint32_t IICINTM    : 1; /*!< [8..8] IICINTM                                                            */
+            __IOM uint32_t IICCSC     : 1; /*!< [9..9] IICCSC                                                             */
+            uint32_t                  : 3;
+            __IOM uint32_t IICACKT    : 1; /*!< [13..13] IICACKT                                                          */
+            uint32_t                  : 2;
+            __IOM uint32_t IICSTAREQ  : 1; /*!< [16..16] IICSTAREQ                                                        */
+            __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] IICRSTAREQ                                                       */
+            __IOM uint32_t IICSTPREQ  : 1; /*!< [18..18] IICSTPREQ                                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t IICSDAS    : 2; /*!< [21..20] IICSDAS                                                          */
+            __IOM uint32_t IICSCLS    : 2; /*!< [23..22] IICSCLS                                                          */
+            uint32_t                  : 8;
+        } ICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FCR;            /*!< (@ 0x00000024) FIFO Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t DRES  : 1;  /*!< [0..0] Receive data ready error select                                    */
+            uint32_t             : 7;
+            __IOM uint32_t TTRG  : 5;  /*!< [12..8] Transmit FIFO data trigger number                                 */
+            uint32_t             : 2;
+            __OM uint32_t  TFRST : 1;  /*!< [15..15] Transmit FIFO Data Register Reset                                */
+            __IOM uint32_t RTRG  : 5;  /*!< [20..16] Receive FIFO data trigger number                                 */
+            uint32_t             : 2;
+            __OM uint32_t  RFRST : 1;  /*!< [23..23] Receive FIFO Data Register Reset                                 */
+            __IOM uint32_t RSTRG : 5;  /*!< [28..24] RTS# Output Active Trigger Number Select                         */
+            uint32_t             : 3;
+        } FCR_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t DCR;            /*!< (@ 0x00000030) Driver Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t DEPOL : 1;  /*!< [0..0] Driver effective polarity select                                   */
+            uint32_t             : 7;
+            __IOM uint32_t DEAST : 5;  /*!< [12..8] Driver Assertion Time                                             */
+            uint32_t             : 3;
+            __IOM uint32_t DENGT : 5;  /*!< [20..16] Driver negate time                                               */
+            uint32_t             : 11;
+        } DCR_b;
+    };
+    __IM uint32_t RESERVED2[5];
+
+    union
+    {
+        __IM uint32_t CSR;             /*!< (@ 0x00000048) Common Status Register                                     */
+
+        struct
+        {
+            uint32_t             : 4;
+            __IM uint32_t ERS    : 1;  /*!< [4..4] Error Signal Status Flag                                           */
+            uint32_t             : 10;
+            __IM uint32_t RXDMON : 1;  /*!< [15..15] Serial input data monitor                                        */
+            __IM uint32_t DCMF   : 1;  /*!< [16..16] Data Compare Match Flag                                          */
+            __IM uint32_t DPER   : 1;  /*!< [17..17] Data Compare Match Parity Error Flag                             */
+            __IM uint32_t DFER   : 1;  /*!< [18..18] Data Compare Match Framing Error Flag                            */
+            uint32_t             : 5;
+            __IM uint32_t ORER   : 1;  /*!< [24..24] ORER                                                             */
+            uint32_t             : 1;
+            __IM uint32_t MFF    : 1;  /*!< [26..26] Mode Fault Error Flag                                            */
+            __IM uint32_t PER    : 1;  /*!< [27..27] PER                                                              */
+            __IM uint32_t FER    : 1;  /*!< [28..28] FER                                                              */
+            __IM uint32_t TDRE   : 1;  /*!< [29..29] Transmit Data Empty Flag                                         */
+            __IM uint32_t TEND   : 1;  /*!< [30..30] TEND                                                             */
+            __IM uint32_t RDRF   : 1;  /*!< [31..31] RDRF                                                             */
+        } CSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ISR;             /*!< (@ 0x0000004C) Simple I2C Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag                                            */
+            uint32_t              : 2;
+            __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
+                                        *   Flag                                                                      */
+            uint32_t : 28;
+        } ISR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRSR;            /*!< (@ 0x00000050) FIFO Receive Status Register                               */
+
+        struct
+        {
+            __IM uint32_t DR   : 1;    /*!< [0..0] DR                                                                 */
+            uint32_t           : 7;
+            __IM uint32_t R    : 6;    /*!< [13..8] Receive FIFO Data Count                                           */
+            uint32_t           : 2;
+            __IM uint32_t PNUM : 6;    /*!< [21..16] Parity Error Count                                               */
+            uint32_t           : 2;
+            __IM uint32_t FNUM : 6;    /*!< [29..24] Framing Error Count                                              */
+            uint32_t           : 2;
+        } FRSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FTSR;            /*!< (@ 0x00000054) FIFO Transmit Status Register                              */
+
+        struct
+        {
+            __IM uint32_t T : 6;       /*!< [5..0] Transmit FIFO Data Count                                           */
+            uint32_t        : 26;
+        } FTSR_b;
+    };
+    __IM uint32_t RESERVED3[4];
+
+    union
+    {
+        __OM uint32_t CFCLR;           /*!< (@ 0x00000068) Common Flag Clear Register                                 */
+
+        struct
+        {
+            uint32_t            : 4;
+            __OM uint32_t ERSC  : 1;   /*!< [4..4] ERSC                                                               */
+            uint32_t            : 11;
+            __OM uint32_t DCMFC : 1;   /*!< [16..16] DCMFC                                                            */
+            __OM uint32_t DPERC : 1;   /*!< [17..17] DPERC                                                            */
+            __OM uint32_t DFERC : 1;   /*!< [18..18] DFERC                                                            */
+            uint32_t            : 5;
+            __OM uint32_t ORERC : 1;   /*!< [24..24] ORERC                                                            */
+            uint32_t            : 1;
+            __OM uint32_t MFFC  : 1;   /*!< [26..26] MFFC                                                             */
+            __OM uint32_t PERC  : 1;   /*!< [27..27] PERC                                                             */
+            __OM uint32_t FERC  : 1;   /*!< [28..28] FERC                                                             */
+            __OM uint32_t TDREC : 1;   /*!< [29..29] TDREC                                                            */
+            uint32_t            : 1;
+            __OM uint32_t RDRFC : 1;   /*!< [31..31] RDRFC                                                            */
+        } CFCLR_b;
+    };
+
+    union
+    {
+        __OM uint32_t ICFCLR;          /*!< (@ 0x0000006C) Simple I2C Flag Clear Register                             */
+
+        struct
+        {
+            uint32_t               : 3;
+            __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIFC                                                           */
+            uint32_t               : 28;
+        } ICFCLR_b;
+    };
+
+    union
+    {
+        __OM uint32_t FFCLR;           /*!< (@ 0x00000070) FIFO Flag Clear Register                                   */
+
+        struct
+        {
+            __OM uint32_t DRC : 1;     /*!< [0..0] DRC                                                                */
+            uint32_t          : 31;
+        } FFCLR_b;
+    };
+} R_SCI0_Type;                         /*!< Size = 116 (0x74)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Peripheral Interface 0 (R_SPI0)
+ */
+
+typedef struct                         /*!< (@ 0x80003000) R_SPI0 Structure                                           */
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t SPDR;         /*!< (@ 0x00000000) SPI Data Register                                          */
+
+            struct
+            {
+                __IOM uint32_t SPD : 32; /*!< [31..0] The SPI data register (SPDR) is used to store SPI's
+                                          *   transmit data and receive data. Transmit buffers and receive
+                                          *   buffers independently function.                                           */
+            } SPDR_b;
+        };
+        __IOM uint16_t SPDR_HA;          /*!< (@ 0x00000000) SPI Data Register                                          */
+        __IOM uint8_t  SPDR_BY;          /*!< (@ 0x00000000) SPI Data Register                                          */
+    };
+
+    union
+    {
+        __IOM uint8_t SPCKD;           /*!< (@ 0x00000004) SPI Clock Delay Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
+            uint8_t             : 5;
+        } SPCKD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLND;           /*!< (@ 0x00000005) SPI Slave Select Negation Delay Register                   */
+
+        struct
+        {
+            __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Bits                                            */
+            uint8_t             : 5;
+        } SSLND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPND;            /*!< (@ 0x00000006) SPI Next-Access Delay Register                             */
+
+        struct
+        {
+            __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Bits                                         */
+            uint8_t             : 5;
+        } SPND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MRCKD;           /*!< (@ 0x00000007) SPI ClocK Digital control Register for Master
+                                        *                  Receive                                                    */
+
+        struct
+        {
+            __IOM uint8_t ARST : 3;    /*!< [2..0] Receive Sampling Timing Adjustment Bits                            */
+            uint8_t            : 5;
+        } MRCKD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SPCR;             /*!< (@ 0x00000008) SPI Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t SPE      : 1; /*!< [0..0] SPI Function Enable                                                */
+            uint32_t                : 6;
+            __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] SPI Master Receive Clock Select                                    */
+            __IOM uint32_t SPPE     : 1; /*!< [8..8] Parity Enable                                                      */
+            __IOM uint32_t SPOE     : 1; /*!< [9..9] Parity Mode                                                        */
+            uint32_t                : 1;
+            __IOM uint32_t PTE      : 1; /*!< [11..11] Parity Self-Diagnosis Enable                                     */
+            __IOM uint32_t SCKASE   : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable                                  */
+            __IOM uint32_t BFDS     : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select                       */
+            __IOM uint32_t MODFEN   : 1; /*!< [14..14] Mode Fault Error Detection Enable                                */
+            uint32_t                : 1;
+            __IOM uint32_t SPEIE    : 1; /*!< [16..16] SPI Error Interrupt Enable                                       */
+            __IOM uint32_t SPRIE    : 1; /*!< [17..17] SPI Receive Buffer Full Interrupt Enable                         */
+            __IOM uint32_t SPIIE    : 1; /*!< [18..18] SPI Idle Interrupt Enable                                        */
+            __IOM uint32_t SPDRES   : 1; /*!< [19..19] SPI Receive Data Ready Error Select                              */
+            __IOM uint32_t SPTIE    : 1; /*!< [20..20] SPI Transmit Buffer Empty Interrupt Enable                       */
+            __IOM uint32_t CENDIE   : 1; /*!< [21..21] SPI Communication End Interrupt Enable                           */
+            uint32_t                : 2;
+            __IOM uint32_t SPMS     : 1; /*!< [24..24] SPI Function Enable                                              */
+            __IOM uint32_t SPFRF    : 1; /*!< [25..25] SPI Frame Format Select                                          */
+            uint32_t                : 2;
+            __IOM uint32_t TXMD     : 2; /*!< [29..28] Communication Mode Select                                        */
+            __IOM uint32_t MSTR     : 1; /*!< [30..30] SPI Master/Slave Mode Select                                     */
+            __IOM uint32_t BPEN     : 1; /*!< [31..31] Synchronization Circuit Bypass Enable                            */
+        } SPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCRRM;          /*!< (@ 0x0000000C) SPI Control Register for Master Receive only               */
+
+        struct
+        {
+            __IOM uint8_t RMFM  : 5;   /*!< [4..0] Frame processing count setting in Master Receive only              */
+            uint8_t             : 1;
+            __OM uint8_t RMEDTG : 1;   /*!< [6..6] Reading value is always 0.                                         */
+            __OM uint8_t RMSTTG : 1;   /*!< [7..7] Reading value is always 0.                                         */
+        } SPCRRM_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPDRCR;          /*!< (@ 0x0000000D) SPI Control Register for Received Data Ready
+                                        *                  Detection                                                  */
+
+        struct
+        {
+            __IOM uint8_t SPDRC : 8;   /*!< [7..0] SPDRC                                                              */
+        } SPDRCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPPCR;           /*!< (@ 0x0000000E) SPI Pin Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
+            __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
+            __IOM uint8_t SPOM  : 1;   /*!< [2..2] SPI Output Pin Mode                                                */
+            uint8_t             : 1;
+            __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
+            __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
+            uint8_t             : 2;
+        } SPPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t SPSCKDL : 3; /*!< [2..0] SPI Master Receive Clock Analog Delay                              */
+            uint8_t               : 5;
+        } SPCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLP;            /*!< (@ 0x00000010) SPI Slave Select Polarity Register                         */
+
+        struct
+        {
+            __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
+            uint8_t             : 4;
+        } SSLP_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPBR;            /*!< (@ 0x00000011) SPI Bit Rate Register                                      */
+
+        struct
+        {
+            __IOM uint8_t SPR : 8;     /*!< [7..0] The SPBR register is used to set the bit rate in master
+                                        *   mode. If SPBR is modified while SPCR.MSTR = 1 and SPCR.SPE
+                                        *   = 1, subsequent operation is not guaranteed.                              */
+        } SPBR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t SPSCR;           /*!< (@ 0x00000013) SPI Sequence Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t SPSLN : 3;   /*!< [2..0] SPI Sequence Length Specification                                  */
+            uint8_t             : 5;
+        } SPSCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SPCMD[8];       /*!< (@ 0x00000014) SPI Command Register [0..7] (m = 0 to 7)                   */
+
+        struct
+        {
+            __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
+            __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
+            __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
+            uint32_t              : 3;
+            __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
+            uint32_t              : 4;
+            __IOM uint32_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
+            __IOM uint32_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
+            __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
+            __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
+            __IOM uint32_t SPB    : 5; /*!< [20..16] SPI Data Length                                                  */
+            uint32_t              : 3;
+            __IOM uint32_t SSLA   : 2; /*!< [25..24] SSL Signal Assertion                                             */
+            uint32_t              : 6;
+        } SPCMD_b[8];
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint16_t SPDCR;          /*!< (@ 0x00000040) SPI Data Control Register                                  */
+
+        struct
+        {
+            __IOM uint16_t BYSW   : 1; /*!< [0..0] Byte Swap Operating Mode Select                                    */
+            __IOM uint16_t SLSEL  : 2; /*!< [2..1] SSL Pin Output Select                                              */
+            __IOM uint16_t SPRDTD : 1; /*!< [3..3] SPI Receive Data or Transmit Data Selection                        */
+            __IOM uint16_t SINV   : 1; /*!< [4..4] Serial data invert                                                 */
+            uint16_t              : 3;
+            __IOM uint16_t SPFC   : 2; /*!< [9..8] Frame Count                                                        */
+            uint16_t              : 6;
+        } SPDCR_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint16_t SPDCR2;         /*!< (@ 0x00000044) SPI Data Control Register 2                                */
+
+        struct
+        {
+            __IOM uint16_t RTRG : 2;   /*!< [1..0] Receive FIFO threshold setting                                     */
+            uint16_t            : 6;
+            __IOM uint16_t TTRG : 2;   /*!< [9..8] Transmission FIFO threshold setting                                */
+            uint16_t            : 6;
+        } SPDCR2_b;
+    };
+    __IM uint16_t RESERVED3;
+    __IM uint32_t RESERVED4[2];
+    __IM uint8_t  RESERVED5;
+
+    union
+    {
+        __IM uint8_t SPSSR;            /*!< (@ 0x00000051) SPI Sequence Status Register                               */
+
+        struct
+        {
+            __IM uint8_t SPCP  : 3;    /*!< [2..0] SPI Command Pointer                                                */
+            uint8_t            : 1;
+            __IM uint8_t SPECM : 3;    /*!< [6..4] SPI Error Command                                                  */
+            uint8_t            : 1;
+        } SPSSR_b;
+    };
+
+    union
+    {
+        __IM uint16_t SPSR;            /*!< (@ 0x00000052) SPI Status Register                                        */
+
+        struct
+        {
+            uint16_t            : 7;
+            __IM uint16_t SPDRF : 1;   /*!< [7..7] SPI Receive Data Ready Flag                                        */
+            __IM uint16_t OVRF  : 1;   /*!< [8..8] Overrun Error Flag                                                 */
+            __IM uint16_t IDLNF : 1;   /*!< [9..9] SPI Idle Flag                                                      */
+            __IM uint16_t MODF  : 1;   /*!< [10..10] Mode Fault Error Flag                                            */
+            __IM uint16_t PERF  : 1;   /*!< [11..11] Parity Error Flag                                                */
+            __IM uint16_t UDRF  : 1;   /*!< [12..12] Underrun Error Flag                                              */
+            __IM uint16_t SPTEF : 1;   /*!< [13..13] SPI Transmit Buffer Empty Flag                                   */
+            __IM uint16_t CENDF : 1;   /*!< [14..14] Communication End Flag                                           */
+            __IM uint16_t SPRF  : 1;   /*!< [15..15] SPI Receive Buffer Full Flag                                     */
+        } SPSR_b;
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IM uint8_t SPTFSR;           /*!< (@ 0x00000058) SPI Transfer FIFO Status Register                          */
+
+        struct
+        {
+            __IM uint8_t TFDN : 3;     /*!< [2..0] Transmit FIFO data empty stage number                              */
+            uint8_t           : 5;
+        } SPTFSR_b;
+    };
+    __IM uint8_t  RESERVED7;
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IM uint8_t SPRFSR;           /*!< (@ 0x0000005C) SPI Receive FIFO Status Register                           */
+
+        struct
+        {
+            __IM uint8_t RFDN : 3;     /*!< [2..0] Receive FIFO data store stage number                               */
+            uint8_t           : 5;
+        } SPRFSR_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IM uint32_t SPPSR;           /*!< (@ 0x00000060) SPI Poling Register                                        */
+
+        struct
+        {
+            __IM uint32_t SPEPS : 1;   /*!< [0..0] SPI Polling Status                                                 */
+            uint32_t            : 31;
+        } SPPSR_b;
+    };
+    __IM uint32_t RESERVED11;
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t SPSRC;          /*!< (@ 0x0000006A) SPI Status Clear Register                                  */
+
+        struct
+        {
+            uint16_t             : 7;
+            __OM uint16_t SPDRFC : 1;  /*!< [7..7] SPI Receive Data Ready Flag Clear                                  */
+            __OM uint16_t OVRFC  : 1;  /*!< [8..8] Overrun Error Flag Clear                                           */
+            uint16_t             : 1;
+            __OM uint16_t MODFC  : 1;  /*!< [10..10] Mode Fault Error Flag Clear                                      */
+            __OM uint16_t PERFC  : 1;  /*!< [11..11] Parity Error Flag Clear                                          */
+            __OM uint16_t UDRFC  : 1;  /*!< [12..12] Underrun Error Flag Clear                                        */
+            __OM uint16_t SPTEFC : 1;  /*!< [13..13] SPI Transmit Buffer Empty Flag Clear                             */
+            __OM uint16_t CENDFC : 1;  /*!< [14..14] Communication End Flag Clear                                     */
+            __OM uint16_t SPRFC  : 1;  /*!< [15..15] SPI Receive Buffer Full Flag Clear                               */
+        } SPSRC_b;
+    };
+
+    union
+    {
+        __OM uint8_t SPFCR;            /*!< (@ 0x0000006C) SPI FIFO Clear Register                                    */
+
+        struct
+        {
+            __OM uint8_t SPFRST : 1;   /*!< [0..0] SPI FIFO clear                                                     */
+            uint8_t             : 7;
+        } SPFCR_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+} R_SPI0_Type;                         /*!< Size = 112 (0x70)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CRC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CRC Unit 0 (R_CRC0)
+ */
+
+typedef struct                         /*!< (@ 0x80004000) R_CRC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register 0                                     */
+
+        struct
+        {
+            __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
+            uint8_t              : 3;
+            __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
+            __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
+        } CRCCR0_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t CRCDIR;         /*!< (@ 0x00000004) CRC Data Input Register                                    */
+        __IOM uint8_t  CRCDIR_BY;      /*!< (@ 0x00000004) CRC Data Input Register                                    */
+    };
+
+    union
+    {
+        __IOM uint32_t CRCDOR;         /*!< (@ 0x00000008) CRC Data Output Register                                   */
+        __IOM uint16_t CRCDOR_HA;      /*!< (@ 0x00000008) CRC Data Output Register                                   */
+        __IOM uint8_t  CRCDOR_BY;      /*!< (@ 0x00000008) CRC Data Output Register                                   */
+    };
+} R_CRC0_Type;                         /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CANFD                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CAN-FD (R_CANFD)
+ */
+
+typedef struct                         /*!< (@ 0x80020000) R_CANFD Structure                                          */
+{
+    __IOM R_CANFD_CFDC_Type CFDC[2];   /*!< (@ 0x00000000) CANFD Channel [0..1] Registers                             */
+    __IM uint32_t           RESERVED[24];
+
+    union
+    {
+        __IM uint32_t CFDGIPV;         /*!< (@ 0x00000080) Global IP Version Register                                 */
+
+        struct
+        {
+            __IM uint32_t IPV : 8;     /*!< [7..0] IP Version                                                         */
+            __IM uint32_t IPT : 2;     /*!< [9..8] IP Type                                                            */
+            uint32_t          : 6;
+            __IM uint32_t PSI : 14;    /*!< [29..16] Parameter Status Information                                     */
+            uint32_t          : 2;
+        } CFDGIPV_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGCFG;         /*!< (@ 0x00000084) Global Configuration Register                              */
+
+        struct
+        {
+            __IOM uint32_t TPRI   : 1;  /*!< [0..0] Transmission Priority                                              */
+            __IOM uint32_t DCE    : 1;  /*!< [1..1] DLC Check Enable                                                   */
+            __IOM uint32_t DRE    : 1;  /*!< [2..2] DLC Replacement Enable                                             */
+            __IOM uint32_t MME    : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
+            __IOM uint32_t DCS    : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
+            __IOM uint32_t CMPOC  : 1;  /*!< [5..5] CAN-FD Message Payload Overflow Configuration                      */
+            uint32_t              : 2;
+            __IOM uint32_t TSP    : 4;  /*!< [11..8] Timestamp Prescaler                                               */
+            __IOM uint32_t TSSS   : 1;  /*!< [12..12] Timestamp Source Select                                          */
+            __IOM uint32_t TSBTCS : 3;  /*!< [15..13] Timestamp Bit Time Channel Select                                */
+            __IOM uint32_t ITRCP  : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
+        } CFDGCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000088) Global Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
+            __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
+            uint32_t               : 5;
+            __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC Check Interrupt Enable                                         */
+            __IOM uint32_t MEIE    : 1; /*!< [9..9] Message Lost Error Interrupt Enable                                */
+            __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
+            __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD Message Payload Overflow Flag Interrupt Enable            */
+            __IOM uint32_t QOWEIE  : 1; /*!< [12..12] TXQ Message Overwrite Error Interrupt Enable                     */
+            uint32_t               : 1;
+            __IOM uint32_t QMEIE   : 1; /*!< [14..14] TXQ Message Lost Error Interrupt Enable                          */
+            __IOM uint32_t MOWEIE  : 1; /*!< [15..15] Message Lost Error Interrupt Enable                              */
+            __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
+            uint32_t               : 15;
+        } CFDGCTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDGSTS;          /*!< (@ 0x0000008C) Global Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
+            __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
+            __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
+            __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialization                                          */
+            uint32_t               : 28;
+        } CFDGSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000090) Global Error Flag Register                                 */
+
+        struct
+        {
+            __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
+            __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
+            __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
+            __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD Message Payload Overflow Flag                               */
+            __IM uint32_t  QOWES : 1;  /*!< [4..4] TXQ Message Overwrite Error Status                                 */
+            uint32_t             : 1;
+            __IM uint32_t QMES   : 1;  /*!< [6..6] TXQ Message Lost Error Status                                      */
+            __IM uint32_t MOWES  : 1;  /*!< [7..7] Message Overwrite Error Status                                     */
+            uint32_t             : 8;
+            __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
+            __IOM uint32_t EEF1  : 1;  /*!< [17..17] ECC Error Flag for Channel 1                                     */
+            uint32_t             : 14;
+        } CFDGERFL_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDGTSC;         /*!< (@ 0x00000094) Global Timestamp Counter Register                          */
+
+        struct
+        {
+            __IM uint32_t TS : 16;     /*!< [15..0] Timestamp value                                                   */
+            uint32_t         : 16;
+        } CFDGTSC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register       */
+
+        struct
+        {
+            __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
+            uint32_t              : 4;
+            __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
+            uint32_t              : 23;
+        } CFDGAFLECTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register
+                                        *                  0                                                          */
+
+        struct
+        {
+            __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
+            uint32_t            : 7;
+            __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
+            uint32_t            : 7;
+        } CFDGAFLCFG0_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint32_t CFDRMNB;        /*!< (@ 0x000000AC) RX Message Buffer Number Register                          */
+
+        struct
+        {
+            __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
+            __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
+            uint32_t             : 21;
+        } CFDRMNB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRMND0;       /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t RMNS : 32;  /*!< [31..0] RX Message Buffer New Data Status                                 */
+        } CFDRMND0_b;
+    };
+    __IM uint32_t RESERVED2[3];
+
+    union
+    {
+        __IOM uint32_t CFDRFCC[8];     /*!< (@ 0x000000C0) RX FIFO Configuration/Control Register [0..7]              */
+
+        struct
+        {
+            __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
+            __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
+            uint32_t              : 2;
+            __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size Configuration                            */
+            uint32_t              : 1;
+            __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
+            uint32_t              : 1;
+            __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
+            __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
+            __IOM uint32_t RFFIE  : 1; /*!< [16..16] RX FIFO Full Interrupt Enable                                    */
+            uint32_t              : 15;
+        } CFDRFCC_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFSTS[8];    /*!< (@ 0x000000E0) RX FIFO Status Register [0..7]                             */
+
+        struct
+        {
+            __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
+            __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
+            __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
+            __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
+            uint32_t             : 4;
+            __IM uint32_t  RFMC  : 8;  /*!< [15..8] RX FIFO Message Count                                             */
+            __IOM uint32_t RFFIF : 1;  /*!< [16..16] RX FIFO Full Interrupt Flag                                      */
+            uint32_t             : 15;
+        } CFDRFSTS_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFPCTR[8];   /*!< (@ 0x00000100) RX FIFO Pointer Control Register [0..7]                    */
+
+        struct
+        {
+            __IOM uint32_t RFPC : 8;   /*!< [7..0] RX FIFO Pointer Control                                            */
+            uint32_t            : 24;
+        } CFDRFPCTR_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCFCC[6];     /*!< (@ 0x00000120) Common FIFO Configuration/Control Register [0..5]          */
+
+        struct
+        {
+            __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
+            __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
+            __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data Size Configuration                        */
+            uint32_t              : 1;
+            __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
+            __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
+            __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
+            __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
+            __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
+            __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
+            __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
+            __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
+        } CFDCFCC_b[6];
+    };
+    __IM uint32_t RESERVED3[18];
+
+    union
+    {
+        __IOM uint32_t CFDCFCCE[6];      /*!< (@ 0x00000180) Common FIFO Configuration/Control Enhancement
+                                          *                  Register [0..5]                                            */
+
+        struct
+        {
+            __IOM uint32_t CFFIE    : 1; /*!< [0..0] Common FIFO Full Interrupt Enable                                  */
+            __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable                   */
+            __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable                */
+            uint32_t                : 5;
+            __IOM uint32_t CFMOWM   : 1; /*!< [8..8] Common FIFO Message Overwrite Mode                                 */
+            uint32_t                : 7;
+            __IOM uint32_t CFBME    : 1; /*!< [16..16] Common FIFO Buffering Mode Enable                                */
+            uint32_t                : 15;
+        } CFDCFCCE_b[6];
+    };
+    __IM uint32_t RESERVED4[18];
+
+    union
+    {
+        __IOM uint32_t CFDCFSTS[6];      /*!< (@ 0x000001E0) Common FIFO Status Register [0..5]                         */
+
+        struct
+        {
+            __IM uint32_t  CFEMP    : 1; /*!< [0..0] Common FIFO Empty                                                  */
+            __IM uint32_t  CFFLL    : 1; /*!< [1..1] Common FIFO Full                                                   */
+            __IOM uint32_t CFMLT    : 1; /*!< [2..2] Common FIFO Message Lost                                           */
+            __IOM uint32_t CFRXIF   : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
+            __IOM uint32_t CFTXIF   : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
+            uint32_t                : 3;
+            __IM uint32_t  CFMC     : 8; /*!< [15..8] Common FIFO Message Count                                         */
+            __IOM uint32_t CFFIF    : 1; /*!< [16..16] Common FIFO Full Interrupt Flag                                  */
+            __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag                   */
+            __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag                */
+            uint32_t                : 5;
+            __IOM uint32_t CFMOW    : 1; /*!< [24..24] Common FIFO Message Overwrite                                    */
+            uint32_t                : 7;
+        } CFDCFSTS_b[6];
+    };
+    __IM uint32_t RESERVED5[18];
+
+    union
+    {
+        __OM uint32_t CFDCFPCTR[6];    /*!< (@ 0x00000240) Common FIFO Pointer Control Register [0..5]                */
+
+        struct
+        {
+            __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
+            uint32_t           : 24;
+        } CFDCFPCTR_b[6];
+    };
+    __IM uint32_t RESERVED6[18];
+
+    union
+    {
+        __IM uint32_t CFDFESTS;        /*!< (@ 0x000002A0) FIFO Empty Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t RFXEMP : 8;  /*!< [7..0] RX FIFO Empty Status                                               */
+            __IM uint32_t CFXEMP : 6;  /*!< [13..8] Common FIFO Empty Status                                          */
+            uint32_t             : 18;
+        } CFDFESTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFFSTS;        /*!< (@ 0x000002A4) FIFO Full Status Register                                  */
+
+        struct
+        {
+            __IM uint32_t RFXFLL : 8;  /*!< [7..0] RX FIFO Full Status                                                */
+            __IM uint32_t CFXFLL : 6;  /*!< [13..8] Common FIFO Full Status                                           */
+            uint32_t             : 18;
+        } CFDFFSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFMSTS;        /*!< (@ 0x000002A8) FIFO Message Lost Status Register                          */
+
+        struct
+        {
+            __IM uint32_t RFXMLT : 8;  /*!< [7..0] RX FIFO Message Lost Status                                        */
+            __IM uint32_t CFXMLT : 6;  /*!< [13..8] Common FIFO Message Lost Status                                   */
+            uint32_t             : 18;
+        } CFDFMSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDRFISTS;       /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register                     */
+
+        struct
+        {
+            __IM uint32_t RFXIF   : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status                                   */
+            uint32_t              : 8;
+            __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status                            */
+            uint32_t              : 8;
+        } CFDRFISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFRISTS;      /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register              */
+
+        struct
+        {
+            __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO RX Interrupt Flag Status                               */
+            uint32_t              : 26;
+        } CFDCFRISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFTISTS;      /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register              */
+
+        struct
+        {
+            __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO TX Interrupt Flag Status                               */
+            uint32_t              : 26;
+        } CFDCFTISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFOFRISTS;      /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO One Frame RX Interrupt Flag Status                     */
+            uint32_t                : 26;
+        } CFDCFOFRISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFOFTISTS;      /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO One Frame TX Interrupt Flag Status                     */
+            uint32_t                : 26;
+        } CFDCFOFTISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFMOWSTS;     /*!< (@ 0x000002C0) Common FIFO Message Overwrite Status Register              */
+
+        struct
+        {
+            __IM uint32_t CFXMOW : 6;  /*!< [5..0] Common FIFO Massage Overwrite Status                               */
+            uint32_t             : 26;
+        } CFDCFMOWSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFFFSTS;       /*!< (@ 0x000002C4) FIFO FDC Full Status Register                              */
+
+        struct
+        {
+            __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC Level Full Status                                      */
+            __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC Level Full Status                                 */
+            uint32_t              : 18;
+        } CFDFFFSTS_b;
+    };
+    __IM uint32_t RESERVED7[2];
+
+    union
+    {
+        __IOM uint8_t CFDTMC[128];     /*!< (@ 0x000002D0) TX Message Buffer Control Register [0..127]                */
+
+        struct
+        {
+            __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
+            __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission Abort Request                       */
+            __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
+            uint8_t             : 5;
+        } CFDTMC_b[128];
+    };
+    __IM uint32_t RESERVED8[288];
+
+    union
+    {
+        __IOM uint8_t CFDTMSTS[128];   /*!< (@ 0x000007D0) TX Message Buffer Status Register [0..127]                 */
+
+        struct
+        {
+            __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
+            __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
+            __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
+            __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission Abort Request Mirrored              */
+            uint8_t              : 3;
+        } CFDTMSTS_b[128];
+    };
+    __IM uint32_t RESERVED9[288];
+
+    union
+    {
+        __IM uint32_t CFDTMTRSTS[4];    /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status
+                                         *                  Register [0..3]                                            */
+
+        struct
+        {
+            __IM uint32_t TMTRSTS : 16; /*!< [15..0] TX Message Buffer Transmission Request Status                     */
+            uint32_t              : 16;
+        } CFDTMTRSTS_b[4];
+    };
+    __IM uint32_t RESERVED10[36];
+
+    union
+    {
+        __IM uint32_t CFDTMTARSTS[4];    /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request
+                                          *                  Status Register [0..3]                                     */
+
+        struct
+        {
+            __IM uint32_t TMTARSTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Request Status               */
+            uint32_t               : 16;
+        } CFDTMTARSTS_b[4];
+    };
+    __IM uint32_t RESERVED11[36];
+
+    union
+    {
+        __IM uint32_t CFDTMTCSTS[4];    /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status
+                                         *                  Register [0..3]                                            */
+
+        struct
+        {
+            __IM uint32_t TMTCSTS : 16; /*!< [15..0] TX Message Buffer Transmission Completion Status                  */
+            uint32_t              : 16;
+        } CFDTMTCSTS_b[4];
+    };
+    __IM uint32_t RESERVED12[36];
+
+    union
+    {
+        __IM uint32_t CFDTMTASTS[4];    /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register
+                                         *                  [0..3]                                                     */
+
+        struct
+        {
+            __IM uint32_t TMTASTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Status                       */
+            uint32_t              : 16;
+        } CFDTMTASTS_b[4];
+    };
+    __IM uint32_t RESERVED13[36];
+
+    union
+    {
+        __IOM uint32_t CFDTMIEC[4];    /*!< (@ 0x00000F50) TX Message Buffer Transmission Interrupt Enable
+                                        *                  Register [0..3]                                            */
+
+        struct
+        {
+            __IOM uint32_t TMIE : 16;  /*!< [15..0] TX Message Buffer Interrupt Enable                                */
+            uint32_t            : 16;
+        } CFDTMIEC_b[4];
+    };
+    __IM uint32_t RESERVED14[40];
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC0[2];      /*!< (@ 0x00001000) TX Queue Configuration/Control Register 0[0..1]            */
+
+        struct
+        {
+            __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
+            __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
+            __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
+            uint32_t                 : 3;
+            __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
+            __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
+            __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
+            uint32_t                 : 13;
+        } CFDTXQCC0_b[2];
+    };
+    __IM uint32_t RESERVED15[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS0[2];     /*!< (@ 0x00001020) TX Queue Status Register 0[0..1]                           */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t                 : 5;
+            __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
+            __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
+            __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
+            __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
+            __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
+            uint32_t                 : 11;
+        } CFDTXQSTS0_b[2];
+    };
+    __IM uint32_t RESERVED16[6];
+
+    union
+    {
+        __OM uint32_t CFDTXQPCTR0[2];  /*!< (@ 0x00001040) TX Queue Pointer Control Register 0[0..1]                  */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR0_b[2];
+    };
+    __IM uint32_t RESERVED17[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC1[2];      /*!< (@ 0x00001060) TX Queue Configuration/Control Register 1[0..1]            */
+
+        struct
+        {
+            __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
+            __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
+            __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
+            uint32_t                 : 3;
+            __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
+            __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
+            __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
+            uint32_t                 : 13;
+        } CFDTXQCC1_b[2];
+    };
+    __IM uint32_t RESERVED18[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS1[2];     /*!< (@ 0x00001080) TX Queue Status Register 1[0..1]                           */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t                 : 5;
+            __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
+            __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
+            __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
+            __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
+            __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
+            uint32_t                 : 11;
+        } CFDTXQSTS1_b[2];
+    };
+    __IM uint32_t RESERVED19[6];
+
+    union
+    {
+        __OM uint32_t CFDTXQPCTR1[2];  /*!< (@ 0x000010A0) TX Queue Pointer Control Register 1[0..1]                  */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR1_b[2];
+    };
+    __IM uint32_t RESERVED20[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC2[2];      /*!< (@ 0x000010C0) TX Queue Configuration/Control Register 2[0..1]            */
+
+        struct
+        {
+            __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
+            __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
+            __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
+            uint32_t                 : 3;
+            __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
+            __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
+            __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
+            uint32_t                 : 13;
+        } CFDTXQCC2_b[2];
+    };
+    __IM uint32_t RESERVED21[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS2[2];     /*!< (@ 0x000010E0) TX Queue Status Register 2[0..1]                           */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t                 : 5;
+            __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
+            __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
+            __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
+            __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
+            __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
+            uint32_t                 : 11;
+        } CFDTXQSTS2_b[2];
+    };
+    __IM uint32_t RESERVED22[6];
+
+    union
+    {
+        __OM uint32_t CFDTXQPCTR2[2];  /*!< (@ 0x00001100) TX Queue Pointer Control Register 2[0..1]                  */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR2_b[2];
+    };
+    __IM uint32_t RESERVED23[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC3[2];      /*!< (@ 0x00001120) TX Queue Configuration/Control Register 3[0..1]            */
+
+        struct
+        {
+            __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
+            uint32_t                 : 5;
+            __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
+            uint32_t                 : 13;
+        } CFDTXQCC3_b[2];
+    };
+    __IM uint32_t RESERVED24[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS3[2];     /*!< (@ 0x00001140) TX Queue Status Register 3[0..1]                           */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t                 : 5;
+            __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t                 : 4;
+            __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
+            uint32_t                 : 11;
+        } CFDTXQSTS3_b[2];
+    };
+    __IM uint32_t RESERVED25[6];
+
+    union
+    {
+        __OM uint32_t CFDTXQPCTR3[2];  /*!< (@ 0x00001160) TX Queue Pointer Control Register 3[0..1]                  */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR3_b[2];
+    };
+    __IM uint32_t RESERVED26[6];
+
+    union
+    {
+        __IM uint32_t CFDTXQESTS;      /*!< (@ 0x00001180) TX Queue Empty Status Register                             */
+
+        struct
+        {
+            __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ Empty Status                                                   */
+            uint32_t              : 24;
+        } CFDTXQESTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQFISTS;      /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register                    */
+
+        struct
+        {
+            __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status Flag for Channel 0                       */
+            uint32_t               : 1;
+            __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status Flag for Channel 1                       */
+            uint32_t               : 25;
+        } CFDTXQFISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQMSTS;      /*!< (@ 0x00001188) TX Queue Message Lost Status Register                      */
+
+        struct
+        {
+            __IM uint32_t TXQ0ML : 3;  /*!< [2..0] TXQ Message Lost Status Flag for Channel 0                         */
+            uint32_t             : 1;
+            __IM uint32_t TXQ1ML : 3;  /*!< [6..4] TXQ Message Lost Status Flag for Channel 1                         */
+            uint32_t             : 25;
+        } CFDTXQMSTS_b;
+    };
+    __IM uint32_t RESERVED27;
+
+    union
+    {
+        __IM uint32_t CFDTXQISTS;      /*!< (@ 0x00001190) TX Queue Interrupt Status Register                         */
+
+        struct
+        {
+            __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for Channel 0                            */
+            __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for Channel 1                            */
+            uint32_t              : 24;
+        } CFDTXQISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQOFTISTS;      /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register            */
+
+        struct
+        {
+            __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for Channel 0               */
+            __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for Channel 1               */
+            uint32_t                 : 24;
+        } CFDTXQOFTISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQOFRISTS;      /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register            */
+
+        struct
+        {
+            __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag for Channel 0               */
+            uint32_t                 : 1;
+            __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag for Channel 1               */
+            uint32_t                 : 25;
+        } CFDTXQOFRISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQFSTS;      /*!< (@ 0x0000119C) TX Queue Full Status Register                              */
+
+        struct
+        {
+            __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for Channel 0                                 */
+            __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for Channel 1                                 */
+            uint32_t              : 24;
+        } CFDTXQFSTS_b;
+    };
+    __IM uint32_t RESERVED28[24];
+
+    union
+    {
+        __IOM uint32_t CFDTHLCC[2];    /*!< (@ 0x00001200) TX History List Configuration/Control Register
+                                        *                  [0..1]                                                     */
+
+        struct
+        {
+            __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
+            uint32_t              : 7;
+            __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
+            __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
+            __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
+            __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated Gateway Enable                         */
+            uint32_t              : 20;
+        } CFDTHLCC_b[2];
+    };
+    __IM uint32_t RESERVED29[6];
+
+    union
+    {
+        __IOM uint32_t CFDTHLSTS[2];   /*!< (@ 0x00001220) TX History List Status Register [0..1]                     */
+
+        struct
+        {
+            __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
+            __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
+            __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
+            __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
+            uint32_t              : 4;
+            __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
+            uint32_t              : 18;
+        } CFDTHLSTS_b[2];
+    };
+    __IM uint32_t RESERVED30[6];
+
+    union
+    {
+        __OM uint32_t CFDTHLPCTR[2];   /*!< (@ 0x00001240) TX History List Pointer Control Register [0..1]            */
+
+        struct
+        {
+            __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
+            uint32_t            : 24;
+        } CFDTHLPCTR_b[2];
+    };
+    __IM uint32_t RESERVED31[46];
+
+    union
+    {
+        __IM uint32_t CFDGTINTSTS0;    /*!< (@ 0x00001300) Global TX Interrupt Status Register 0                      */
+
+        struct
+        {
+            __IM uint32_t TSIF0   : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
+            __IM uint32_t TAIF0   : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
+            __IM uint32_t TQIF0   : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
+            __IM uint32_t CFTIF0  : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
+            __IM uint32_t THIF0   : 1; /*!< [4..4] TX History List Interrupt Channel 0                                */
+            __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel
+                                        *   0                                                                         */
+            __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel
+                                        *   0                                                                         */
+            uint32_t              : 1;
+            __IM uint32_t TSIF1   : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1                             */
+            __IM uint32_t TAIF1   : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1                                  */
+            __IM uint32_t TQIF1   : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1                                */
+            __IM uint32_t CFTIF1  : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1                     */
+            __IM uint32_t THIF1   : 1; /*!< [12..12] TX History List Interrupt Channel 1                              */
+            __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel
+                                        *   1                                                                         */
+            __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel
+                                        *   1                                                                         */
+            uint32_t : 17;
+        } CFDGTINTSTS0_b;
+    };
+    __IM uint32_t RESERVED32;
+
+    union
+    {
+        __IOM uint32_t CFDGTSTCFG;       /*!< (@ 0x00001308) Global Test Configuration Register                         */
+
+        struct
+        {
+            __IOM uint32_t C0ICBCE : 1;  /*!< [0..0] Channel 0 Internal CAN Bus Communication Test Mode Enable          */
+            __IOM uint32_t C1ICBCE : 1;  /*!< [1..1] Channel 1 Internal CAN Bus Communication Test Mode Enable          */
+            uint32_t               : 14;
+            __IOM uint32_t RTMPS   : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
+            uint32_t               : 6;
+        } CFDGTSTCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTSTCTR;      /*!< (@ 0x0000130C) Global Test Control Register                               */
+
+        struct
+        {
+            __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable                    */
+            uint32_t               : 1;
+            __IOM uint32_t RTME    : 1; /*!< [2..2] RAM Test Mode Enable                                               */
+            uint32_t               : 29;
+        } CFDGTSTCTR_b;
+    };
+    __IM uint32_t RESERVED33;
+
+    union
+    {
+        __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x00001314) Global FD Configuration Register                           */
+
+        struct
+        {
+            __IOM uint32_t RPED   : 1; /*!< [0..0] RES Bit Protocol Exception Disable                                 */
+            uint32_t              : 7;
+            __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp Capture Configuration                                    */
+            uint32_t              : 22;
+        } CFDGFDCFG_b;
+    };
+    __IM uint32_t RESERVED34;
+
+    union
+    {
+        __OM uint32_t CFDGLOCKK;       /*!< (@ 0x0000131C) Global Lock Key Register                                   */
+
+        struct
+        {
+            __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
+            uint32_t           : 16;
+        } CFDGLOCKK_b;
+    };
+    __IM uint32_t RESERVED35[4];
+
+    union
+    {
+        __IOM uint32_t CFDCDTCT;        /*!< (@ 0x00001330) DMA Transfer Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RX FIFO 0                                  */
+            __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RX FIFO 1                                  */
+            __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RX FIFO 2                                  */
+            __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RX FIFO 3                                  */
+            __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RX FIFO 4                                  */
+            __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RX FIFO 5                                  */
+            __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RX FIFO 6                                  */
+            __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RX FIFO 7                                  */
+            __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of Channel 0                 */
+            __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of Channel 1                 */
+            uint32_t               : 22;
+        } CFDCDTCT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCDTSTS;         /*!< (@ 0x00001334) DMA Transfer Status Register                               */
+
+        struct
+        {
+            __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
+            __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
+            __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2                                  */
+            __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3                                  */
+            __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4                                  */
+            __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5                                  */
+            __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6                                  */
+            __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7                                  */
+            __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of Channel
+                                          *   0                                                                         */
+            __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of Channel
+                                          *   1                                                                         */
+            uint32_t : 22;
+        } CFDCDTSTS_b;
+    };
+    __IM uint32_t RESERVED36[2];
+
+    union
+    {
+        __IOM uint32_t CFDCDTTCT;        /*!< (@ 0x00001340) DMA TX Transfer Control Register                           */
+
+        struct
+        {
+            __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of Channel 0                      */
+            __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of Channel 1                      */
+            uint32_t                : 6;
+            __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of Channel 0                      */
+            __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of Channel 1                      */
+            uint32_t                : 6;
+            __IOM uint32_t CFDMAE0  : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of Channel
+                                          *   0                                                                         */
+            __IOM uint32_t CFDMAE1 : 1;  /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of Channel
+                                          *   1                                                                         */
+            uint32_t : 14;
+        } CFDCDTTCT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCDTTSTS;         /*!< (@ 0x00001344) DMA TX Transfer Status Register                            */
+
+        struct
+        {
+            __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of Channel 0                       */
+            __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of Channel 1                       */
+            uint32_t                 : 6;
+            __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of Channel 0                       */
+            __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of Channel 1                       */
+            uint32_t                 : 6;
+            __IM uint32_t CFDMASTS0  : 1; /*!< [16..16] DMA TX Transfer Status for Common FIFO 2 of Channel
+                                           *   0                                                                         */
+            __IM uint32_t CFDMASTS1 : 1;  /*!< [17..17] DMA TX Transfer Status for Common FIFO 2 of Channel
+                                           *   1                                                                         */
+            uint32_t : 14;
+        } CFDCDTTSTS_b;
+    };
+    __IM uint32_t RESERVED37[2];
+
+    union
+    {
+        __IM uint32_t CFDGRINTSTS[2];  /*!< (@ 0x00001350) Global RX Interrupt Status Register [0..1]                 */
+
+        struct
+        {
+            __IM uint32_t QFIF    : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n (n = 0, 1)                       */
+            uint32_t              : 1;
+            __IM uint32_t BQFIF   : 2; /*!< [5..4] Borrowed TXQ Full Interrupt Flag Channel n (n = 0, 1)              */
+            uint32_t              : 2;
+            __IM uint32_t QOFRIF  : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n (n = 0, 1)              */
+            uint32_t              : 1;
+            __IM uint32_t BQOFRIF : 2; /*!< [13..12] Borrowed TXQ One Frame RX Interrupt Flag Channel n
+                                        *   (n = 0, 1)                                                                */
+            uint32_t             : 2;
+            __IM uint32_t CFRIF  : 3;  /*!< [18..16] Common FIFO RX Interrupt Flag Channel n (n = 0, 1)               */
+            uint32_t             : 5;
+            __IM uint32_t CFRFIF : 3;  /*!< [26..24] Common FIFO FDC Level Full Interrupt Flag Channel n
+                                        *   (n = 0, 1)                                                                */
+            uint32_t              : 1;
+            __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n (n
+                                        *   = 0, 1)                                                                   */
+            uint32_t : 1;
+        } CFDGRINTSTS_b[2];
+    };
+    __IM uint32_t RESERVED38[10];
+
+    union
+    {
+        __IOM uint32_t CFDGRSTC;       /*!< (@ 0x00001380) Global Reset Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t SRST : 1;   /*!< [0..0] Software Reset                                                     */
+            uint32_t            : 7;
+            __OM uint32_t KEY   : 8;   /*!< [15..8] Key Code                                                          */
+            uint32_t            : 16;
+        } CFDGRSTC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGFCMC;       /*!< (@ 0x00001384) Global Flexible CAN Mode Configuration Register            */
+
+        struct
+        {
+            __IOM uint32_t FLXC0 : 1;  /*!< [0..0] Flexible CAN Mode between Channel 0 and Channel 1                  */
+            uint32_t             : 31;
+        } CFDGFCMC_b;
+    };
+    __IM uint32_t RESERVED39;
+
+    union
+    {
+        __IOM uint32_t CFDGFTBAC;      /*!< (@ 0x0000138C) Global Flexible Transmission Buffer Assignment
+                                        *                  Configuration Register                                     */
+
+        struct
+        {
+            __IOM uint32_t FLXMB0 : 4; /*!< [3..0] Flexible Transmission Buffer Assignment between Channel
+                                        *   0 and Channel 1                                                           */
+            uint32_t : 28;
+        } CFDGFTBAC_b;
+    };
+    __IM uint32_t              RESERVED40[28];
+    __IOM R_CANFD_CFDC2_Type   CFDC2[2];    /*!< (@ 0x00001400) Channel Configuration Registers                            */
+    __IM uint32_t              RESERVED41[240];
+    __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers                    */
+    __IM uint32_t              RESERVED42[448];
+    __IOM R_CANFD_CFDRM_Type   CFDRM[32];   /*!< (@ 0x00002000) RX Message Buffer Access Registers                         */
+    __IM uint32_t              RESERVED43[3072];
+    __IOM R_CANFD_CFDRF_Type   CFDRF[8];    /*!< (@ 0x00006000) RX FIFO Access Registers                                   */
+    __IOM R_CANFD_CFDCF_Type   CFDCF[6];    /*!< (@ 0x00006400) Common FIFO Access Registers                               */
+    __IM uint32_t              RESERVED44[1600];
+    __IOM R_CANFD_CFDTHL_Type  CFDTHL[2];   /*!< (@ 0x00008000) Channel TX History List                                    */
+    __IM uint32_t              RESERVED45[252];
+
+    union
+    {
+        __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00008400) RAM Test Page Access Register [0..63]                      */
+
+        struct
+        {
+            __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
+        } CFDRPGACC_b[64];
+    };
+    __IM uint32_t            RESERVED46[7872];
+    __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Registers                                */
+} R_CANFD_Type;                          /*!< Size = 81920 (0x14000)                                                    */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CMT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Compare Match Timer Control (R_CMT)
+ */
+
+typedef struct                         /*!< (@ 0x80040000) R_CMT Structure                                            */
+{
+    __IOM R_CMT_UNT_Type UNT[3];       /*!< (@ 0x00000000) 3 Timer Start Register Units                               */
+} R_CMT_Type;                          /*!< Size = 3072 (0xc00)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CMTW0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Compare Match Timer W (R_CMTW0)
+ */
+
+typedef struct                         /*!< (@ 0x80041000) R_CMTW0 Structure                                          */
+{
+    union
+    {
+        __IOM uint16_t CMWSTR;         /*!< (@ 0x00000000) Timer Start Register                                       */
+
+        struct
+        {
+            __IOM uint16_t STR : 1;    /*!< [0..0] Counter Start                                                      */
+            uint16_t           : 15;
+        } CMWSTR_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CMWCR;          /*!< (@ 0x00000004) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint16_t CKS   : 2;  /*!< [1..0] Clock Select                                                       */
+            uint16_t             : 1;
+            __IOM uint16_t CMWIE : 1;  /*!< [3..3] Compare Match Interrupt Enable                                     */
+            __IOM uint16_t IC0IE : 1;  /*!< [4..4] Input Capture 0 Interrupt Enable                                   */
+            __IOM uint16_t IC1IE : 1;  /*!< [5..5] Input Capture 1 Interrupt Enable                                   */
+            __IOM uint16_t OC0IE : 1;  /*!< [6..6] Output Compare 0 Interrupt Enable                                  */
+            __IOM uint16_t OC1IE : 1;  /*!< [7..7] Output Compare 1 Interrupt Enable                                  */
+            uint16_t             : 1;
+            __IOM uint16_t CMS   : 1;  /*!< [9..9] Timer Counter Size                                                 */
+            uint16_t             : 3;
+            __IOM uint16_t CCLR  : 3;  /*!< [15..13] Counter Clear                                                    */
+        } CMWCR_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t CMWIOR;         /*!< (@ 0x00000008) Timer I/O Control Register                                 */
+
+        struct
+        {
+            __IOM uint16_t IC0  : 2;   /*!< [1..0] Input Capture Control 0                                            */
+            __IOM uint16_t IC1  : 2;   /*!< [3..2] Input Capture Control 1                                            */
+            __IOM uint16_t IC0E : 1;   /*!< [4..4] Input Capture Enable 0                                             */
+            __IOM uint16_t IC1E : 1;   /*!< [5..5] Input Capture Enable 1                                             */
+            uint16_t            : 2;
+            __IOM uint16_t OC0  : 2;   /*!< [9..8] Output Compare Control 0                                           */
+            __IOM uint16_t OC1  : 2;   /*!< [11..10] Output Compare Control 1                                         */
+            __IOM uint16_t OC0E : 1;   /*!< [12..12] Compare Match Enable 0                                           */
+            __IOM uint16_t OC1E : 1;   /*!< [13..13] Compare Match Enable 1                                           */
+            uint16_t            : 1;
+            __IOM uint16_t CMWE : 1;   /*!< [15..15] Compare Match Enable                                             */
+        } CMWIOR_b;
+    };
+    __IM uint16_t  RESERVED2;
+    __IM uint32_t  RESERVED3;
+    __IOM uint32_t CMWCNT;             /*!< (@ 0x00000010) Timer Counter                                              */
+    __IOM uint32_t CMWCOR;             /*!< (@ 0x00000014) Compare Match Constant Register                            */
+    __IM uint32_t  CMWICR0;            /*!< (@ 0x00000018) Input Capture Registers                                    */
+    __IM uint32_t  CMWICR1;            /*!< (@ 0x0000001C) Input Capture Registers                                    */
+    __IOM uint32_t CMWOCR0;            /*!< (@ 0x00000020) Output Compare Registers                                   */
+    __IOM uint32_t CMWOCR1;            /*!< (@ 0x00000024) Output Compare Registers                                   */
+} R_CMTW0_Type;                        /*!< Size = 40 (0x28)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_WDT0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Watchdog Timer 0 (R_WDT0)
+ */
+
+typedef struct                         /*!< (@ 0x80042000) R_WDT0 Structure                                           */
+{
+    __IOM uint8_t WDTRR;               /*!< (@ 0x00000000) WDT Refresh Register                                       */
+    __IM uint8_t  RESERVED;
+
+    union
+    {
+        __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
+            uint16_t            : 2;
+            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
+            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
+            uint16_t            : 2;
+            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
+            uint16_t            : 2;
+        } WDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
+            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
+            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
+        } WDTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
+
+        struct
+        {
+            uint8_t               : 7;
+            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
+        } WDTRCR_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+} R_WDT0_Type;                         /*!< Size = 10 (0xa)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I2C Bus Interface 0 (R_IIC0)
+ */
+
+typedef struct                         /*!< (@ 0x80043000) R_IIC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
+
+        struct
+        {
+            __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
+            __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
+            __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
+            __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
+            __OM uint8_t  SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
+            __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
+            __IOM uint8_t IICRST : 1;  /*!< [6..6] IIC-Bus Interface Internal Reset                                   */
+            __IOM uint8_t ICE    : 1;  /*!< [7..7] IIC-Bus Interface Enable                                           */
+        } ICCR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
+
+        struct
+        {
+            uint8_t            : 1;
+            __IOM uint8_t ST   : 1;    /*!< [1..1] Start Condition Issuance Request                                   */
+            __IOM uint8_t RS   : 1;    /*!< [2..2] Restart Condition Issuance Request                                 */
+            __IOM uint8_t SP   : 1;    /*!< [3..3] Stop Condition Issuance Request                                    */
+            uint8_t            : 1;
+            __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
+            __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
+            __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
+        } ICCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
+
+        struct
+        {
+            __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
+            __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect                                                   */
+            __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock Select                                    */
+            __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
+        } ICMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
+
+        struct
+        {
+            __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
+            __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
+            __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
+            uint8_t            : 1;
+            __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
+            __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
+        } ICMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
+
+        struct
+        {
+            __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Select                                          */
+            __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
+            __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
+            __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
+            __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Select                                        */
+            __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAIT                                                               */
+            __IOM uint8_t SMBS  : 1;   /*!< [7..7] SMBus/IIC-Bus Select                                               */
+        } ICMR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
+
+        struct
+        {
+            __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
+            __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
+            __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
+            __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
+            __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
+            __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
+            __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
+            uint8_t             : 1;
+        } ICFER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
+
+        struct
+        {
+            __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
+            __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
+            __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
+            __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
+            uint8_t             : 1;
+            __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device ID Address Detection Enable                                 */
+            uint8_t             : 1;
+            __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
+        } ICSER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
+
+        struct
+        {
+            __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
+            __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
+            __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
+            __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
+            __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
+            __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
+            __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
+            __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
+        } ICIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
+
+        struct
+        {
+            __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
+            __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
+            __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
+            __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
+            uint8_t            : 1;
+            __IOM uint8_t DID  : 1;    /*!< [5..5] Device ID Address Detection Flag                                   */
+            uint8_t            : 1;
+            __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
+        } ICSR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
+
+        struct
+        {
+            __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
+            __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
+            __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
+            __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
+            __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
+            __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
+            __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
+            __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
+        } ICSR2_b;
+    };
+    __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
+
+    union
+    {
+        __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
+
+        struct
+        {
+            __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period                                          */
+            uint8_t           : 3;
+        } ICBRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
+
+        struct
+        {
+            __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period                                         */
+            uint8_t           : 3;
+        } ICBRH_b;
+    };
+    __IOM uint8_t ICDRT;               /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
+    __IM uint8_t  ICDRR;               /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
+} R_IIC0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Operation Circuit (R_DOC)
+ */
+
+typedef struct                         /*!< (@ 0x80044000) R_DOC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
+            __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
+            uint8_t               : 1;
+            __IOM uint8_t DOPCIE  : 1; /*!< [4..4] Data Operation Circuit Interrupt Enable                            */
+            __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
+            __OM uint8_t  DOPCFCL : 1; /*!< [6..6] DOPCF Flag Clear                                                   */
+            uint8_t               : 1;
+        } DOCR_b;
+    };
+    __IM uint8_t   RESERVED;
+    __IOM uint16_t DODIR;              /*!< (@ 0x00000002) DOC Data Input Register                                    */
+    __IOM uint16_t DODSR;              /*!< (@ 0x00000004) DOC Data Setting Register                                  */
+} R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ADC121                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief 12-Bit A/D converter (R_ADC121)
+ */
+
+typedef struct                         /*!< (@ 0x80045000) R_ADC121 Structure                                         */
+{
+    union
+    {
+        __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel Select                                      */
+            uint16_t              : 1;
+            __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
+            __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
+            __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
+            __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
+            uint16_t              : 2;
+            __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
+            __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
+            __IOM uint16_t ADST   : 1; /*!< [15..15] A/D conversion Start                                             */
+        } ADCSR_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t ADANSA0;        /*!< (@ 0x00000004) A/D Channel Select Register A0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSA0 : 8;  /*!< [7..0] A/D conversion Analog input Channel Select                         */
+            uint16_t             : 8;
+        } ADANSA0_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t ADADS0;         /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Function
+                                        *                  Channel Select Register 0                                  */
+
+        struct
+        {
+            __IOM uint16_t ADS0 : 8;   /*!< [7..0] A/D-Converted Value Addition/Average Channel Select                */
+            uint16_t            : 8;
+        } ADADS0_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t ADC  : 3;    /*!< [2..0] Addition Count Select                                              */
+            uint8_t            : 4;
+            __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable                                                */
+        } ADADC_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
+
+        struct
+        {
+            uint16_t              : 1;
+            __IOM uint16_t ADPRC  : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
+            uint16_t              : 2;
+            __IOM uint16_t ACE    : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
+            uint16_t              : 9;
+            __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select                                  */
+        } ADCER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
+
+        struct
+        {
+            __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group B                    */
+            uint16_t            : 2;
+            __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger Select                               */
+            uint16_t            : 2;
+        } ADSTRGR_b;
+    };
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint16_t ADANSB0;        /*!< (@ 0x00000014) A/D Channel Select Register B0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSB0 : 8;  /*!< [7..0] A/D Conversion Analog Input Channel Select                         */
+            uint16_t             : 8;
+        } ADANSB0_b;
+    };
+    __IM uint16_t RESERVED5;
+
+    union
+    {
+        __IM uint16_t ADDBLDR;         /*!< (@ 0x00000018) A/D Data Duplication Register                              */
+
+        struct
+        {
+            __IM uint16_t DBLDR : 16;  /*!< [15..0] The result of A/D conversion in response to the second
+                                        *   trigger in double trigger mode.                                           */
+        } ADDBLDR_b;
+    };
+    __IM uint16_t RESERVED6[3];
+
+    union
+    {
+        __IM uint16_t ADDR[8];         /*!< (@ 0x00000020) A/D Data Register n (n = 0 to 3 for unit 0, n
+                                        *                  = 0 to 7 for unit1)                                        */
+
+        struct
+        {
+            __IM uint16_t DR : 16;     /*!< [15..0] The result of A/D conversion (n: Number of channel)               */
+        } ADDR_b[8];
+    };
+    __IM uint16_t RESERVED7[27];
+
+    union
+    {
+        __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Control Register                       */
+
+        struct
+        {
+            __IOM uint16_t SSTSH : 8;  /*!< [7..0] Sample and hold period setting                                     */
+            __IOM uint16_t SHANS : 3;  /*!< [10..8] Sample and hold use or bypass select for ch0-2                    */
+            uint16_t             : 5;
+        } ADSHCR_b;
+    };
+    __IM uint16_t RESERVED8[10];
+    __IM uint8_t  RESERVED9;
+
+    union
+    {
+        __IOM uint8_t ADELCCR;         /*!< (@ 0x0000007D) A/D Event Link Control Register                            */
+
+        struct
+        {
+            __IOM uint8_t ELCC  : 2;   /*!< [1..0] Event link control bits                                            */
+            __IOM uint8_t GCELC : 1;   /*!< [2..2] Event control bit for Group C                                      */
+            uint8_t             : 5;
+        } ADELCCR_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t ADGSPCR;        /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
+
+        struct
+        {
+            __IOM uint16_t PGS    : 1; /*!< [0..0] Group Priority Control Setting                                     */
+            __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting                                            */
+            uint16_t              : 12;
+            __IOM uint16_t LGRRS  : 1; /*!< [14..14] Restart Channel Select                                           */
+            __IOM uint16_t GBRP   : 1; /*!< [15..15] Group B Single Scan Continuous Start                             */
+        } ADGSPCR_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IM uint16_t ADDBLDRA;        /*!< (@ 0x00000084) A/D Data Duplication Register A                            */
+
+        struct
+        {
+            __IM uint16_t DBLDRA : 16; /*!< [15..0] The result of A/D conversion during extended operation
+                                        *   in double trigger mode                                                    */
+        } ADDBLDRA_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDRB;        /*!< (@ 0x00000086) A/D Data Duplication Register B                            */
+
+        struct
+        {
+            __IM uint16_t DBLDRB : 16; /*!< [15..0] The result of A/D conversion during extended operation
+                                        *   in double trigger mode                                                    */
+        } ADDBLDRB_b;
+    };
+    __IM uint16_t RESERVED12[2];
+
+    union
+    {
+        __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitoring
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitor                                         */
+            uint8_t              : 3;
+            __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparing result monitor for window A                              */
+            __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparing result monitor for window B                              */
+            uint8_t              : 2;
+        } ADWINMON_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t CMPAB  : 2; /*!< [1..0] Window A/B combination condition setting                           */
+            uint16_t              : 7;
+            __IOM uint16_t CMPBE  : 1; /*!< [9..9] Window B operation permission                                      */
+            uint16_t              : 1;
+            __IOM uint16_t CMPAE  : 1; /*!< [11..11] Window A operation permission                                    */
+            uint16_t              : 1;
+            __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare window B Interrupt Enable                                */
+            __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function enable                                           */
+            __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare window A Interrupt Enable                                */
+        } ADCMPCR_b;
+    };
+    __IM uint16_t RESERVED15;
+
+    union
+    {
+        __IOM uint16_t ADCMPANSR0;      /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
+                                         *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t CMPCHA0 : 8; /*!< [7..0] Window A Channel Select                                            */
+            uint16_t               : 8;
+        } ADCMPANSR0_b;
+    };
+    __IM uint16_t RESERVED16;
+
+    union
+    {
+        __IOM uint16_t ADCMPLR0;         /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
+                                          *                  Setting Register 0                                         */
+
+        struct
+        {
+            __IOM uint16_t CMPLCHA0 : 8; /*!< [7..0] Window A comparison condition for target channel (ch0-7)
+                                          *   setting                                                                   */
+            uint16_t : 8;
+        } ADCMPLR0_b;
+    };
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint16_t ADCMPDR0;        /*!< (@ 0x0000009C) A/D Comparison Function Window A Lower Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLLA : 16; /*!< [15..0] Reference data setting when using the compare function
+                                         *   window A                                                                  */
+        } ADCMPDR0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR1;        /*!< (@ 0x0000009E) AD Comparison Function Window A Upper Level Setting
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPULA : 16; /*!< [15..0] Reference data setting when using the compare function
+                                         *   window A                                                                  */
+        } ADCMPDR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPSR0;          /*!< (@ 0x000000A0) A/D Comparison Function Window A Channel Status
+                                           *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t CMPSTCHA0 : 8; /*!< [7..0] Window A Status Flag                                               */
+            uint16_t                 : 8;
+        } ADCMPSR0_b;
+    };
+    __IM uint16_t RESERVED18[2];
+
+    union
+    {
+        __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Window B Channel Select                                            */
+            uint8_t              : 1;
+            __IOM uint8_t CMPLB  : 1;  /*!< [7..7] Window B Comparison Condition Setting                              */
+        } ADCMPBNSR_b;
+    };
+    __IM uint8_t RESERVED19;
+
+    union
+    {
+        __IOM uint16_t ADWINLLB;        /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLLB : 16; /*!< [15..0] Reference lower data setting when using the compare
+                                         *   function window B                                                         */
+        } ADWINLLB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADWINULB;        /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPULB : 16; /*!< [15..0] Reference upper data setting when using the compare
+                                         *   function window B                                                         */
+        } ADWINULB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
+
+        struct
+        {
+            __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Window B Flag                                                      */
+            uint8_t              : 7;
+        } ADCMPBSR_b;
+    };
+    __IM uint8_t  RESERVED20;
+    __IM uint16_t RESERVED21[19];
+
+    union
+    {
+        __IOM uint16_t ADANSC0;        /*!< (@ 0x000000D4) A/D Channel Select Register C0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSC0 : 8;  /*!< [7..0] A/D-Converted Channel Select for Group C in Group Scan
+                                        *   Mode                                                                      */
+            uint16_t : 8;
+        } ADANSC0_b;
+    };
+    __IM uint16_t RESERVED22;
+    __IM uint8_t  RESERVED23;
+
+    union
+    {
+        __IOM uint8_t ADGCTRGR;        /*!< (@ 0x000000D9) A/D Group C Trigger Select Register                        */
+
+        struct
+        {
+            __IOM uint8_t TRSC   : 6;  /*!< [5..0] Group C A/D Conversion Start Trigger Select                        */
+            __IOM uint8_t GCADIE : 1;  /*!< [6..6] Group C Scan Completion Interrupt Enable                           */
+            __IOM uint8_t GRCE   : 1;  /*!< [7..7] Group C A/D Conversion Enable                                      */
+        } ADGCTRGR_b;
+    };
+    __IM uint16_t RESERVED24[3];
+
+    union
+    {
+        __IOM uint8_t ADSSTR[8];       /*!< (@ 0x000000E0) A/D Sampling State Register n (n = 0 to 3 for
+                                        *                  unit 0, n = 0 to 7 for unit1)                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting                                              */
+        } ADSSTR_b[8];
+    };
+} R_ADC121_Type;                       /*!< Size = 232 (0xe8)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TSU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor Unit (R_TSU)
+ */
+
+typedef struct                         /*!< (@ 0x80046000) R_TSU Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t TSUSM;          /*!< (@ 0x00000000) Sensor Mode Register                                       */
+
+        struct
+        {
+            __IOM uint32_t TSEN  : 1;  /*!< [0..0] Temperature Sensor Enable                                          */
+            __IOM uint32_t ADCEN : 1;  /*!< [1..1] ADC Enable                                                         */
+            uint32_t             : 30;
+        } TSUSM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TSUST;          /*!< (@ 0x00000004) Sensor Trigger Register                                    */
+
+        struct
+        {
+            __IOM uint32_t START : 1;  /*!< [0..0] A/D Conversion Control                                             */
+            uint32_t             : 31;
+        } TSUST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TSUSCS;         /*!< (@ 0x00000008) Sensor Configuration Setting Register                      */
+
+        struct
+        {
+            uint32_t             : 3;
+            __IOM uint32_t CKDIV : 1;  /*!< [3..3] Divider Value for PCLKL                                            */
+            uint32_t             : 28;
+        } TSUSCS_b;
+    };
+
+    union
+    {
+        __IM uint32_t TSUSAD;          /*!< (@ 0x0000000C) Sensor ADC Data Register                                   */
+
+        struct
+        {
+            __IM uint32_t DOUT : 12;   /*!< [11..0] Temperature Sensor Data Output                                    */
+            uint32_t           : 20;
+        } TSUSAD_b;
+    };
+
+    union
+    {
+        __IM uint32_t TSUSS;           /*!< (@ 0x00000010) Sensor Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t CONV : 1;    /*!< [0..0] A/D Conversion Status                                              */
+            uint32_t           : 31;
+        } TSUSS_b;
+    };
+} R_TSU_Type;                          /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG1                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief GPT Port Output Enable 1 (R_POEG1)
+ */
+
+typedef struct                         /*!< (@ 0x80047000) R_POEG1 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t POEG1GA;        /*!< (@ 0x00000000) POEG1 Group A Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG1GA_b;
+    };
+    __IM uint32_t RESERVED[255];
+
+    union
+    {
+        __IOM uint32_t POEG1GB;        /*!< (@ 0x00000400) POEG1 Group B Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG1GB_b;
+    };
+    __IM uint32_t RESERVED1[255];
+
+    union
+    {
+        __IOM uint32_t POEG1GC;        /*!< (@ 0x00000800) POEG1 Group C Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG1GC_b;
+    };
+    __IM uint32_t RESERVED2[255];
+
+    union
+    {
+        __IOM uint32_t POEG1GD;        /*!< (@ 0x00000C00) POEG1 Group D Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG1GD_b;
+    };
+} R_POEG1_Type;                        /*!< Size = 3076 (0xc04)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller 0 (R_DMAC0)
+ */
+
+typedef struct                         /*!< (@ 0x80080000) R_DMAC0 Structure                                          */
+{
+    __IOM R_DMAC0_GRP_Type GRP[1];     /*!< (@ 0x00000000) 8 channel Registers                                        */
+} R_DMAC0_Type;                        /*!< Size = 804 (0x324)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ICU_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Controller in Non Safety Domain (R_ICU_NS)
+ */
+
+typedef struct                         /*!< (@ 0x80090000) R_ICU_NS Structure                                         */
+{
+    union
+    {
+        __OM uint32_t NS_SWINT;        /*!< (@ 0x00000000) Software Interrupt Register                                */
+
+        struct
+        {
+            __OM uint32_t IC0 : 1;     /*!< [0..0] Software Interrupt register                                        */
+            __OM uint32_t IC1 : 1;     /*!< [1..1] Software Interrupt register                                        */
+            __OM uint32_t IC2 : 1;     /*!< [2..2] Software Interrupt register                                        */
+            __OM uint32_t IC3 : 1;     /*!< [3..3] Software Interrupt register                                        */
+            __OM uint32_t IC4 : 1;     /*!< [4..4] Software Interrupt register                                        */
+            __OM uint32_t IC5 : 1;     /*!< [5..5] Software Interrupt register                                        */
+            uint32_t          : 26;
+        } NS_SWINT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NS_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register                     */
+
+        struct
+        {
+            __IOM uint32_t FLT0   : 1;   /*!< [0..0] Noise filter enable for IRQ0                                       */
+            __IOM uint32_t FLT1   : 1;   /*!< [1..1] Noise filter enable for IRQ1                                       */
+            __IOM uint32_t FLT2   : 1;   /*!< [2..2] Noise filter enable for IRQ2                                       */
+            __IOM uint32_t FLT3   : 1;   /*!< [3..3] Noise filter enable for IRQ3                                       */
+            __IOM uint32_t FLT4   : 1;   /*!< [4..4] Noise filter enable for IRQ4                                       */
+            __IOM uint32_t FLT5   : 1;   /*!< [5..5] Noise filter enable for IRQ5                                       */
+            __IOM uint32_t FLT6   : 1;   /*!< [6..6] Noise filter enable for IRQ6                                       */
+            __IOM uint32_t FLT7   : 1;   /*!< [7..7] Noise filter enable for IRQ7                                       */
+            __IOM uint32_t FLT8   : 1;   /*!< [8..8] Noise filter enable for IRQ8                                       */
+            __IOM uint32_t FLT9   : 1;   /*!< [9..9] Noise filter enable for IRQ9                                       */
+            __IOM uint32_t FLT10  : 1;   /*!< [10..10] Noise filter enable for IRQ10                                    */
+            __IOM uint32_t FLT11  : 1;   /*!< [11..11] Noise filter enable for IRQ11                                    */
+            __IOM uint32_t FLT12  : 1;   /*!< [12..12] Noise filter enable for IRQ12                                    */
+            __IOM uint32_t FLT13  : 1;   /*!< [13..13] Noise filter enable for IRQ13                                    */
+            __IOM uint32_t FLTDRQ : 1;   /*!< [14..14] Noise filter enable for External DMA request (DREQ)              */
+            uint32_t              : 17;
+        } NS_PORTNF_FLTSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NS_PORTNF_CLKSEL;  /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t CKSEL0    : 2; /*!< [1..0] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL1    : 2; /*!< [3..2] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL2    : 2; /*!< [5..4] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL3    : 2; /*!< [7..6] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL4    : 2; /*!< [9..8] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL5    : 2; /*!< [11..10] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL6    : 2; /*!< [13..12] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL7    : 2; /*!< [15..14] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL8    : 2; /*!< [17..16] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL9    : 2; /*!< [19..18] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL10   : 2; /*!< [21..20] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL11   : 2; /*!< [23..22] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL12   : 2; /*!< [25..24] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL13   : 2; /*!< [27..26] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSELDREQ : 2; /*!< [29..28] Noise filter sampling clock selector                             */
+            uint32_t                 : 2;
+        } NS_PORTNF_CLKSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NS_PORTNF_MD;   /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register                  */
+
+        struct
+        {
+            __IOM uint32_t MD0   : 2;  /*!< [1..0] Select detection mode for IRQ0                                     */
+            __IOM uint32_t MD1   : 2;  /*!< [3..2] Select detection mode for IRQ1                                     */
+            __IOM uint32_t MD2   : 2;  /*!< [5..4] Select detection mode for IRQ2                                     */
+            __IOM uint32_t MD3   : 2;  /*!< [7..6] Select detection mode for IRQ3                                     */
+            __IOM uint32_t MD4   : 2;  /*!< [9..8] Select detection mode for IRQ4                                     */
+            __IOM uint32_t MD5   : 2;  /*!< [11..10] Select detection mode for IRQ5                                   */
+            __IOM uint32_t MD6   : 2;  /*!< [13..12] Select detection mode for IRQ6                                   */
+            __IOM uint32_t MD7   : 2;  /*!< [15..14] Select detection mode for IRQ7                                   */
+            __IOM uint32_t MD8   : 2;  /*!< [17..16] Select detection mode for IRQ8                                   */
+            __IOM uint32_t MD9   : 2;  /*!< [19..18] Select detection mode for IRQ9                                   */
+            __IOM uint32_t MD10  : 2;  /*!< [21..20] Select detection mode for IRQ10                                  */
+            __IOM uint32_t MD11  : 2;  /*!< [23..22] Select detection mode for IRQ11                                  */
+            __IOM uint32_t MD12  : 2;  /*!< [25..24] Select detection mode for IRQ12                                  */
+            __IOM uint32_t MD13  : 2;  /*!< [27..26] Select detection mode for IRQ13                                  */
+            __IOM uint32_t MDDRQ : 2;  /*!< [29..28] Select detection mode for DREQ of DMAC                           */
+            uint32_t             : 2;
+        } NS_PORTNF_MD_b;
+    };
+} R_ICU_NS_Type;                       /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Evnet Link Controller (R_ELC)
+ */
+
+typedef struct                            /*!< (@ 0x80090010) R_ELC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t ELC_SSEL[19];      /*!< (@ 0x00000000) ELC Event Source Select Register [0..18]                   */
+
+        struct
+        {
+            __IOM uint32_t ELC_SEL0 : 10; /*!< [9..0] Set the number for ELC event source to be linked to the
+                                           *   ELC destination.                                                          */
+            __IOM uint32_t ELC_SEL1 : 10; /*!< [19..10] Set the number for ELC event source to be linked to
+                                           *   the ELC destination.                                                      */
+            __IOM uint32_t ELC_SEL2 : 10; /*!< [29..20] Set the number for ELC event source to be linked to
+                                           *   the ELC destination.                                                      */
+            uint32_t : 2;
+        } ELC_SSEL_b[19];
+    };
+} R_ELC_Type;                             /*!< Size = 76 (0x4c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMAC Configuration (R_DMA)
+ */
+
+typedef struct                         /*!< (@ 0x80090060) R_DMA Structure                                            */
+{
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t DMAC0_RSSEL[3];   /*!< (@ 0x0000000C) DMAC Unit 0 Resource Select Register [0..2]                */
+
+        struct
+        {
+            __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n                                  */
+            uint32_t                : 1;
+            __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1                            */
+            uint32_t                : 1;
+            __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2                            */
+            uint32_t                : 3;
+        } DMAC0_RSSEL_b[3];
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint32_t DMAC1_RSSEL[3];   /*!< (@ 0x00000024) DMAC Unit 1 Resource Select Register [0..2]                */
+
+        struct
+        {
+            __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n                                  */
+            uint32_t                : 1;
+            __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1                            */
+            uint32_t                : 1;
+            __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2                            */
+            uint32_t                : 3;
+        } DMAC1_RSSEL_b[3];
+    };
+} R_DMA_Type;                            /*!< Size = 48 (0x30)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PORT_NSR                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports (Non safety region) (R_PORT_NSR)
+ */
+
+typedef struct                         /*!< (@ 0x800A0000) R_PORT_NSR Structure                                       */
+{
+    union
+    {
+        __IOM uint8_t P[25];           /*!< (@ 0x00000000) Port [0..24] Register                                      */
+
+        struct
+        {
+            __IOM uint8_t POUT_0 : 1;  /*!< [0..0] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_1 : 1;  /*!< [1..1] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_2 : 1;  /*!< [2..2] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_3 : 1;  /*!< [3..3] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_4 : 1;  /*!< [4..4] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_5 : 1;  /*!< [5..5] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_6 : 1;  /*!< [6..6] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_7 : 1;  /*!< [7..7] Pm_n Output Data Store (n: bit position)                           */
+        } P_b[25];
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[121];
+
+    union
+    {
+        __IOM uint16_t PM[25];         /*!< (@ 0x00000200) Port 0 Mode Register                                       */
+
+        struct
+        {
+            __IOM uint16_t PM0 : 2;    /*!< [1..0] Pm_0 I/O Select                                                    */
+            __IOM uint16_t PM1 : 2;    /*!< [3..2] Pm_1 I/O Select                                                    */
+            __IOM uint16_t PM2 : 2;    /*!< [5..4] Pm_2 I/O Select                                                    */
+            __IOM uint16_t PM3 : 2;    /*!< [7..6] Pm_3 I/O Select                                                    */
+            __IOM uint16_t PM4 : 2;    /*!< [9..8] Pm_4 I/O Select                                                    */
+            __IOM uint16_t PM5 : 2;    /*!< [11..10] Pm_5 I/O Select                                                  */
+            __IOM uint16_t PM6 : 2;    /*!< [13..12] Pm_6 I/O Select                                                  */
+            __IOM uint16_t PM7 : 2;    /*!< [15..14] Pm_7 I/O Select                                                  */
+        } PM_b[25];
+    };
+    __IM uint16_t RESERVED3;
+    __IM uint32_t RESERVED4[115];
+
+    union
+    {
+        __IOM uint8_t PMC[25];         /*!< (@ 0x00000400) Port [0..24] Mode Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t PMC0 : 1;    /*!< [0..0] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC1 : 1;    /*!< [1..1] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC2 : 1;    /*!< [2..2] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC3 : 1;    /*!< [3..3] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC4 : 1;    /*!< [4..4] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC5 : 1;    /*!< [5..5] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC6 : 1;    /*!< [6..6] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC7 : 1;    /*!< [7..7] Pm_n Pin Mode Control (n: bit position)                            */
+        } PMC_b[25];
+    };
+    __IM uint8_t  RESERVED5;
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[121];
+
+    union
+    {
+        __IOM uint32_t PFC[25];        /*!< (@ 0x00000600) Port [0..24] Function Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t PFC0 : 4;   /*!< [3..0] Pm_0 Pin function Select                                           */
+            __IOM uint32_t PFC1 : 4;   /*!< [7..4] Pm_1 Pin function Select                                           */
+            __IOM uint32_t PFC2 : 4;   /*!< [11..8] Pm_2 Pin function Select                                          */
+            __IOM uint32_t PFC3 : 4;   /*!< [15..12] Pm_3 Pin function Select                                         */
+            __IOM uint32_t PFC4 : 4;   /*!< [19..16] Pm_4 Pin function Select                                         */
+            __IOM uint32_t PFC5 : 4;   /*!< [23..20] Pm_5 Pin function Select                                         */
+            __IOM uint32_t PFC6 : 4;   /*!< [27..24] Pm_6 Pin function Select                                         */
+            __IOM uint32_t PFC7 : 4;   /*!< [31..28] Pm_7 Pin function Select                                         */
+        } PFC_b[25];
+    };
+    __IM uint32_t RESERVED8[103];
+
+    union
+    {
+        __IM uint8_t PIN[25];          /*!< (@ 0x00000800) Port [0..24] Input Register                                */
+
+        struct
+        {
+            __IM uint8_t PIN0 : 1;     /*!< [0..0] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN1 : 1;     /*!< [1..1] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN2 : 1;     /*!< [2..2] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN3 : 1;     /*!< [3..3] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN4 : 1;     /*!< [4..4] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN5 : 1;     /*!< [5..5] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN6 : 1;     /*!< [6..6] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN7 : 1;     /*!< [7..7] Pm_n Pin Input (n: bit position)                                   */
+        } PIN_b[25];
+    };
+    __IM uint8_t            RESERVED9;
+    __IM uint16_t           RESERVED10;
+    __IM uint32_t           RESERVED11[121];
+    __IOM R_PORT_DRCTL_Type DRCTL[25]; /*!< (@ 0x00000A00) I/O Buffer [0..24] Function Switching Register             */
+    __IM uint32_t           RESERVED12[206];
+
+    union
+    {
+        __IOM uint8_t ELC_PGR[2];      /*!< (@ 0x00000E00) ELC Port Group Setting Register [0..1]                     */
+
+        struct
+        {
+            __IOM uint8_t PG0 : 1;     /*!< [0..0] Port Group Setting                                                 */
+            __IOM uint8_t PG1 : 1;     /*!< [1..1] Port Group Setting                                                 */
+            __IOM uint8_t PG2 : 1;     /*!< [2..2] Port Group Setting                                                 */
+            __IOM uint8_t PG3 : 1;     /*!< [3..3] Port Group Setting                                                 */
+            __IOM uint8_t PG4 : 1;     /*!< [4..4] Port Group Setting                                                 */
+            __IOM uint8_t PG5 : 1;     /*!< [5..5] Port Group Setting                                                 */
+            __IOM uint8_t PG6 : 1;     /*!< [6..6] Port Group Setting                                                 */
+            __IOM uint8_t PG7 : 1;     /*!< [7..7] Port Group Setting                                                 */
+        } ELC_PGR_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t ELC_PGC[2];               /*!< (@ 0x00000E02) ELC Port Group Control Register [0..1]                     */
+
+        struct
+        {
+            __IOM uint8_t PGCI   : 2;           /*!< [1..0] Event Output Edge Select                                           */
+            __IOM uint8_t PGCOVE : 1;           /*!< [2..2] PDBF Overwrite                                                     */
+            uint8_t              : 1;
+            __IOM uint8_t PGCO   : 3;           /*!< [6..4] Port Group Operation Select                                        */
+            uint8_t              : 1;
+        } ELC_PGC_b[2];
+    };
+    __IOM R_PORT_NSR_ELC_PDBF_Type ELC_PDBF[2]; /*!< (@ 0x00000E04) ELC Port Buffer Register [0..1]                            */
+
+    union
+    {
+        __IOM uint8_t ELC_PEL[4];               /*!< (@ 0x00000E0C) ELC Port Setting Register [0..3]                           */
+
+        struct
+        {
+            __IOM uint8_t PSB : 3;              /*!< [2..0] Bit Number Specification                                           */
+            __IOM uint8_t PSP : 2;              /*!< [4..3] Port Number Specification                                          */
+            __IOM uint8_t PSM : 2;              /*!< [6..5] Event Link Specification                                           */
+            uint8_t           : 1;
+        } ELC_PEL_b[4];
+    };
+
+    union
+    {
+        __IOM uint8_t ELC_DPTC;        /*!< (@ 0x00000E10) ELC Edge Detection Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t PTC0 : 1;    /*!< [0..0] Single Input Port n Edge Detection                                 */
+            __IOM uint8_t PTC1 : 1;    /*!< [1..1] Single Input Port n Edge Detection                                 */
+            __IOM uint8_t PTC2 : 1;    /*!< [2..2] Single Input Port n Edge Detection                                 */
+            __IOM uint8_t PTC3 : 1;    /*!< [3..3] Single Input Port n Edge Detection                                 */
+            uint8_t            : 4;
+        } ELC_DPTC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ELC_ELSR2;       /*!< (@ 0x00000E11) ELC Port Event Control Register                            */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t PEG1 : 1;    /*!< [2..2] ELC Port Buffer Register (ELC_PDBFn) write access control.
+                                        *   When set to 1, writing to the ELC_PDBFn register via Internal
+                                        *   peripheral bus is disabled, preventing overwriting.                       */
+            __IOM uint8_t PEG2 : 1;    /*!< [3..3] ELC Port Buffer Register (ELC_PDBFn) write access control.
+                                        *   When set to 1, writing to the ELC_PDBFn register via Internal
+                                        *   peripheral bus is disabled, preventing overwriting.                       */
+            __IOM uint8_t PES0 : 1;    /*!< [4..4] Single Port n Event Link Function Enable                           */
+            __IOM uint8_t PES1 : 1;    /*!< [5..5] Single Port n Event Link Function Enable                           */
+            __IOM uint8_t PES2 : 1;    /*!< [6..6] Single Port n Event Link Function Enable                           */
+            __IOM uint8_t PES3 : 1;    /*!< [7..7] Single Port n Event Link Function Enable                           */
+        } ELC_ELSR2_b;
+    };
+    __IM uint16_t RESERVED13;
+} R_PORT_COMMON_Type;                  /*!< Size = 3604 (0xe14)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GMAC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet MAC (R_GMAC)
+ */
+
+typedef struct                            /*!< (@ 0x80100000) R_GMAC Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t MAC_Configuration; /*!< (@ 0x00000000) MAC Configuration Register                                 */
+
+        struct
+        {
+            __IOM uint32_t PRELEN : 2;    /*!< [1..0] Preamble Length for Transmit Frames                                */
+            __IOM uint32_t RE     : 1;    /*!< [2..2] Receiver Enable                                                    */
+            __IOM uint32_t TE     : 1;    /*!< [3..3] Transmitter Enable                                                 */
+            __IOM uint32_t DC     : 1;    /*!< [4..4] Deferral Check                                                     */
+            __IOM uint32_t BL     : 2;    /*!< [6..5] Back-Off Limit                                                     */
+            __IOM uint32_t ACS    : 1;    /*!< [7..7] Automatic Pad or CRC Stripping                                     */
+            uint32_t              : 1;
+            __IOM uint32_t DR     : 1;    /*!< [9..9] Disable Retry                                                      */
+            __IOM uint32_t IPC    : 1;    /*!< [10..10] Checksum Offload                                                 */
+            __IOM uint32_t DM     : 1;    /*!< [11..11] Duplex Mode                                                      */
+            __IOM uint32_t LM     : 1;    /*!< [12..12] Loopback Mode                                                    */
+            __IOM uint32_t DO     : 1;    /*!< [13..13] Disable Receive Own                                              */
+            __IOM uint32_t FES    : 1;    /*!< [14..14] Speed                                                            */
+            __IOM uint32_t PS     : 1;    /*!< [15..15] Port Select                                                      */
+            __IOM uint32_t DCRS   : 1;    /*!< [16..16] Disable Carrier Sense During Transmission                        */
+            __IOM uint32_t IFG    : 3;    /*!< [19..17] Inter-Frame Gap                                                  */
+            __IOM uint32_t JE     : 1;    /*!< [20..20] Jumbo Frame Enable                                               */
+            __IOM uint32_t BE     : 1;    /*!< [21..21] Frame Burst Enable                                               */
+            __IOM uint32_t JD     : 1;    /*!< [22..22] Jabber Disable                                                   */
+            __IOM uint32_t WD     : 1;    /*!< [23..23] Watchdog Disable                                                 */
+            uint32_t              : 1;
+            __IOM uint32_t CST    : 1;    /*!< [25..25] CRC Stripping for Type Frames                                    */
+            uint32_t              : 1;
+            __IOM uint32_t TWOKPE : 1;    /*!< [27..27] IEEE 802.3 as Support for 2 K Packets                            */
+            uint32_t              : 4;
+        } MAC_Configuration_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Frame_Filter; /*!< (@ 0x00000004) MAC Frame Filter Register                                  */
+
+        struct
+        {
+            __IOM uint32_t PR   : 1;     /*!< [0..0] Promiscuous Mode                                                   */
+            __IOM uint32_t HUC  : 1;     /*!< [1..1] Hash Unicast                                                       */
+            __IOM uint32_t HMC  : 1;     /*!< [2..2] Hash Multicast                                                     */
+            __IOM uint32_t DAIF : 1;     /*!< [3..3] DA Inverse Filtering                                               */
+            __IOM uint32_t PM   : 1;     /*!< [4..4] Pass All Multicast                                                 */
+            __IOM uint32_t DBF  : 1;     /*!< [5..5] Disable Broadcast Frames                                           */
+            __IOM uint32_t PCF  : 2;     /*!< [7..6] Pass Control Frames                                                */
+            __IOM uint32_t SAIF : 1;     /*!< [8..8] SA Inverse Filtering                                               */
+            __IOM uint32_t SAF  : 1;     /*!< [9..9] Source Address Filter Enable                                       */
+            __IOM uint32_t HPF  : 1;     /*!< [10..10] Hash or Perfect Filter                                           */
+            uint32_t            : 5;
+            __IOM uint32_t VTFE : 1;     /*!< [16..16] VLAN Tag Filter Enable                                           */
+            uint32_t            : 14;
+            __IOM uint32_t RA   : 1;     /*!< [31..31] Receive All                                                      */
+        } MAC_Frame_Filter_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t GMII_Address;   /*!< (@ 0x00000010) GMII Address Register                                      */
+
+        struct
+        {
+            __IOM uint32_t GB : 1;     /*!< [0..0] GMII Busy                                                          */
+            __IOM uint32_t GW : 1;     /*!< [1..1] GMII Write                                                         */
+            __IOM uint32_t CR : 4;     /*!< [5..2] CSR Clock Range                                                    */
+            __IOM uint32_t GR : 5;     /*!< [10..6] GMII Register                                                     */
+            __IOM uint32_t PA : 5;     /*!< [15..11] Physical Layer Address                                           */
+            uint32_t          : 16;
+        } GMII_Address_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GMII_Data;      /*!< (@ 0x00000014) GMII Data Register                                         */
+
+        struct
+        {
+            __IOM uint32_t GD : 16;    /*!< [15..0] GMII Data                                                         */
+            uint32_t          : 16;
+        } GMII_Data_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Flow_Control;     /*!< (@ 0x00000018) Flow Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t FCA_BPA : 1;  /*!< [0..0] Flow Control Busy or Backpressure Activate                         */
+            __IOM uint32_t TFE     : 1;  /*!< [1..1] Transmit Flow Control Enable                                       */
+            __IOM uint32_t RFE     : 1;  /*!< [2..2] Receive Flow Control Enable                                        */
+            __IOM uint32_t UP      : 1;  /*!< [3..3] Unicast Pause Frame Detect                                         */
+            __IOM uint32_t PLT     : 2;  /*!< [5..4] Pause Low Threshold                                                */
+            uint32_t               : 1;
+            __IOM uint32_t DZPQ    : 1;  /*!< [7..7] Disable Zero-Quanta Pause                                          */
+            uint32_t               : 8;
+            __IOM uint32_t PT      : 16; /*!< [31..16] Pause Time                                                       */
+        } Flow_Control_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_Tag;       /*!< (@ 0x0000001C) VLAN Tag Register                                          */
+
+        struct
+        {
+            __IOM uint32_t VL   : 16;  /*!< [15..0] VLAN Tag Identifier for Receive Frames                            */
+            __IOM uint32_t ETV  : 1;   /*!< [16..16] Enable 12-Bit VLAN Tag Comparison                                */
+            __IOM uint32_t VTIM : 1;   /*!< [17..17] VLAN Tag Inverse Match Enable                                    */
+            __IOM uint32_t ESVL : 1;   /*!< [18..18] Enable S-VLAN                                                    */
+            __IOM uint32_t VTHM : 1;   /*!< [19..19] VLAN Tag Hash Table Match Enable                                 */
+            uint32_t            : 12;
+        } VLAN_Tag_b;
+    };
+
+    union
+    {
+        __IM uint32_t Version;         /*!< (@ 0x00000020) Version Register                                           */
+
+        struct
+        {
+            __IM uint32_t VER : 16;    /*!< [15..0] Version (GMAC: 0x3037)                                            */
+            uint32_t          : 16;
+        } Version_b;
+    };
+
+    union
+    {
+        __IM uint32_t Debug;             /*!< (@ 0x00000024) Debug Register                                             */
+
+        struct
+        {
+            __IM uint32_t RPESTS    : 1; /*!< [0..0] GMAC GMII or MII Receive Protocol Engine Status                    */
+            __IM uint32_t RFCFCSTS  : 2; /*!< [2..1] GMAC Receive Frame Controller FIFO Status                          */
+            uint32_t                : 1;
+            __IM uint32_t RWCSTS    : 1; /*!< [4..4] MTL RX FIFO Write Controller Active Status                         */
+            __IM uint32_t RRCSTS    : 2; /*!< [6..5] MTL RX FIFO Read Controller State                                  */
+            uint32_t                : 1;
+            __IM uint32_t RXFSTS    : 2; /*!< [9..8] MTL RX FIFO Fill-level Status                                      */
+            uint32_t                : 6;
+            __IM uint32_t TPESTS    : 1; /*!< [16..16] GMAC GMII or MII Transmit Protocol Engine Status                 */
+            __IM uint32_t TFCSTS    : 2; /*!< [18..17] GMAC Transmit Frame Controller Status                            */
+            __IM uint32_t TXPAUSED  : 1; /*!< [19..19] GMAC transmitter in PAUSE                                        */
+            __IM uint32_t TRCSTS    : 2; /*!< [21..20] MTL TX FIFO Read Controller Status                               */
+            __IM uint32_t TWCSTS    : 1; /*!< [22..22] MTL TX FIFO Write Controller Active Status                       */
+            uint32_t                : 1;
+            __IM uint32_t TXFSTS    : 1; /*!< [24..24] MTL TX FIFO Not Empty Status                                     */
+            __IM uint32_t TXSTSFSTS : 1; /*!< [25..25] MTL TX Status FIFO Full Status                                   */
+            uint32_t                : 6;
+        } Debug_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Remote_Wake_Up_Frame_Filter; /*!< (@ 0x00000028) Remote Wake-Up Frame Filter Register                       */
+
+        struct
+        {
+            __IOM uint32_t WKUPFRMFTR : 32;         /*!< [31..0] Remote Wake-Up Frame Filter                                       */
+        } Remote_Wake_Up_Frame_Filter_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PMT_Control_Status; /*!< (@ 0x0000002C) PMT Control and Status Register                            */
+
+        struct
+        {
+            __IOM uint32_t PWRDWN     : 1; /*!< [0..0] Power Down                                                         */
+            __IOM uint32_t MGKPKTEN   : 1; /*!< [1..1] Magic Packet Enable                                                */
+            __IOM uint32_t RWKPKTEN   : 1; /*!< [2..2] Wake-Up Frame Enable                                               */
+            uint32_t                  : 2;
+            __IM uint32_t MGKPRCVD    : 1; /*!< [5..5] Magic Packet Received                                              */
+            __IM uint32_t RWKPRCVD    : 1; /*!< [6..6] Wake-Up Frame Received                                             */
+            uint32_t                  : 2;
+            __IOM uint32_t GLBLUCAST  : 1; /*!< [9..9] Global Unicast                                                     */
+            uint32_t                  : 14;
+            __IM uint32_t RWKPTR      : 3; /*!< [26..24] Remote Wake-Up FIFO Pointer                                      */
+            uint32_t                  : 4;
+            __IOM uint32_t RWKFILTRST : 1; /*!< [31..31] Wake-Up Frame Filter Register Pointer Reset                      */
+        } PMT_Control_Status_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LPI_Control_Status; /*!< (@ 0x00000030) LPI Control and Status Register                            */
+
+        struct
+        {
+            __IM uint32_t TLPIEN  : 1;     /*!< [0..0] Transmit LPI Entry                                                 */
+            __IM uint32_t TLPIEX  : 1;     /*!< [1..1] Transmit LPI Exit                                                  */
+            __IM uint32_t RLPIEN  : 1;     /*!< [2..2] Receive LPI Entry                                                  */
+            __IM uint32_t RLPIEX  : 1;     /*!< [3..3] Receive LPI Exit                                                   */
+            uint32_t              : 4;
+            __IM uint32_t TLPIST  : 1;     /*!< [8..8] Transmit LPI State                                                 */
+            __IM uint32_t RLPIST  : 1;     /*!< [9..9] Receive LPI State                                                  */
+            uint32_t              : 6;
+            __IOM uint32_t LPIEN  : 1;     /*!< [16..16] LPI Enable                                                       */
+            __IOM uint32_t PLS    : 1;     /*!< [17..17] PHY Link Status                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t LPITXA : 1;     /*!< [19..19] LPI TX Automate                                                  */
+            uint32_t              : 12;
+        } LPI_Control_Status_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LPI_Timers_Control; /*!< (@ 0x00000034) LPI Timers Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t TWT : 16;       /*!< [15..0] LPI TW Timer                                                      */
+            __IOM uint32_t LST : 10;       /*!< [25..16] LPI LS Timer                                                     */
+            uint32_t           : 6;
+        } LPI_Timers_Control_b;
+    };
+
+    union
+    {
+        __IM uint32_t Interrupt_Status; /*!< (@ 0x00000038) Interrupt Status Register                                  */
+
+        struct
+        {
+            uint32_t                : 3;
+            __IM uint32_t PMTIS     : 1; /*!< [3..3] PMT Interrupt Status                                               */
+            __IM uint32_t MMCIS     : 1; /*!< [4..4] MMC Interrupt Status                                               */
+            __IM uint32_t MMCRXIS   : 1; /*!< [5..5] MMC Receive Interrupt Status                                       */
+            __IM uint32_t MMCTXIS   : 1; /*!< [6..6] MMC Transmit Interrupt Status                                      */
+            __IM uint32_t MMCRXIPIS : 1; /*!< [7..7] MMC Receive Checksum Offload Interrupt Status                      */
+            uint32_t                : 1;
+            __IM uint32_t TSIS      : 1; /*!< [9..9] Timestamp Interrupt Status                                         */
+            __IM uint32_t LPIIS     : 1; /*!< [10..10] LPI Interrupt Status                                             */
+            uint32_t                : 21;
+        } Interrupt_Status_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Interrupt_Mask; /*!< (@ 0x0000003C) Interrupt Mask Register                                    */
+
+        struct
+        {
+            uint32_t             : 3;
+            __IOM uint32_t PMTIM : 1;  /*!< [3..3] PMT Interrupt Mask                                                 */
+            uint32_t             : 5;
+            __IOM uint32_t TSIM  : 1;  /*!< [9..9] Timestamp Interrupt Mask                                           */
+            __IOM uint32_t LPIIM : 1;  /*!< [10..10] LPI Interrupt Mask                                               */
+            uint32_t             : 21;
+        } Interrupt_Mask_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR0_H;          /*!< (@ 0x00000040) MAC Address 0 High Register                                */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address0[47:32]                                               */
+            uint32_t              : 15;
+            __IM uint32_t AE      : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR0_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR0_L;          /*!< (@ 0x00000044) MAC Address 0 Low Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address0[31:0]                                                */
+        } MAR0_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR1_H;          /*!< (@ 0x00000048) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR1_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR1_L;          /*!< (@ 0x0000004C) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR1_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR2_H;          /*!< (@ 0x00000050) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR2_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR2_L;          /*!< (@ 0x00000054) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR2_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR3_H;          /*!< (@ 0x00000058) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR3_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR3_L;          /*!< (@ 0x0000005C) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR3_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR4_H;          /*!< (@ 0x00000060) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR4_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR4_L;          /*!< (@ 0x00000064) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR4_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR5_H;          /*!< (@ 0x00000068) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR5_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR5_L;          /*!< (@ 0x0000006C) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR5_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR6_H;          /*!< (@ 0x00000070) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR6_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR6_L;          /*!< (@ 0x00000074) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR6_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR7_H;          /*!< (@ 0x00000078) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR7_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR7_L;          /*!< (@ 0x0000007C) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR7_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR8_H;          /*!< (@ 0x00000080) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR8_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR8_L;          /*!< (@ 0x00000084) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR8_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR9_H;          /*!< (@ 0x00000088) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR9_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR9_L;          /*!< (@ 0x0000008C) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR9_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR10_H;         /*!< (@ 0x00000090) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR10_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR10_L;         /*!< (@ 0x00000094) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR10_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR11_H;         /*!< (@ 0x00000098) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR11_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR11_L;         /*!< (@ 0x0000009C) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR11_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR12_H;         /*!< (@ 0x000000A0) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR12_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR12_L;         /*!< (@ 0x000000A4) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR12_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR13_H;         /*!< (@ 0x000000A8) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR13_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR13_L;         /*!< (@ 0x000000AC) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR13_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR14_H;         /*!< (@ 0x000000B0) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR14_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR14_L;         /*!< (@ 0x000000B4) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR14_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR15_H;         /*!< (@ 0x000000B8) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR15_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR15_L;         /*!< (@ 0x000000BC) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR15_L_b;
+    };
+    __IM uint32_t RESERVED1[7];
+
+    union
+    {
+        __IOM uint32_t WDog_Timeout;   /*!< (@ 0x000000DC) Watchdog Timeout Register                                  */
+
+        struct
+        {
+            __IOM uint32_t WTO : 14;   /*!< [13..0] Watchdog Timeout                                                  */
+            uint32_t           : 2;
+            __IOM uint32_t PWE : 1;    /*!< [16..16] Programmable Watchdog Enable                                     */
+            uint32_t           : 15;
+        } WDog_Timeout_b;
+    };
+    __IM uint32_t RESERVED2[8];
+
+    union
+    {
+        __IOM uint32_t MMC_Control;        /*!< (@ 0x00000100) MMC Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t CNTRST     : 1; /*!< [0..0] Counters Reset                                                     */
+            __IOM uint32_t CNTSTOPRO  : 1; /*!< [1..1] Counters Stop Rollover                                             */
+            __IOM uint32_t RSTONRD    : 1; /*!< [2..2] Reset on Read                                                      */
+            __IOM uint32_t CNTFREEZ   : 1; /*!< [3..3] MMC Counter Freeze                                                 */
+            __IOM uint32_t CNTPRST    : 1; /*!< [4..4] Counters Preset                                                    */
+            __IOM uint32_t CNTPRSTLVL : 1; /*!< [5..5] Full-Half Preset                                                   */
+            uint32_t                  : 2;
+            __IOM uint32_t UCDBC      : 1; /*!< [8..8] Update MMC Counters for Dropped Broadcast Frames                   */
+            uint32_t                  : 23;
+        } MMC_Control_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Receive_Interrupt;      /*!< (@ 0x00000104) MMC Receive Interrupt Register                             */
+
+        struct
+        {
+            __IM uint32_t RXGBFRMIS    : 1;       /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Status                */
+            __IM uint32_t RXGBOCTIS    : 1;       /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Status                */
+            __IM uint32_t RXGOCTIS     : 1;       /*!< [2..2] MMC Receive Good Octet Counter Interrupt Status                    */
+            __IM uint32_t RXBCGFIS     : 1;       /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Status          */
+            __IM uint32_t RXMCGFIS     : 1;       /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Status          */
+            __IM uint32_t RXCRCERFIS   : 1;       /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Status               */
+            __IM uint32_t RXALGNERFIS  : 1;       /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Status         */
+            __IM uint32_t RXRUNTFIS    : 1;       /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Status                    */
+            __IM uint32_t RXJABERFIS   : 1;       /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Status            */
+            __IM uint32_t RXUSIZEGFIS  : 1;       /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Status          */
+            __IM uint32_t RXOSIZEGFIS  : 1;       /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Status         */
+            __IM uint32_t RX64OCTGBFIS : 1;       /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t RX65T127OCTGBFIS : 1;   /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t RX128T255OCTGBFIS : 1;  /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t RX256T511OCTGBFIS : 1;  /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t RX512T1023OCTGBFIS : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t RX1024TMAXOCTGBFIS : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t RXUCGFIS    : 1;        /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Status          */
+            __IM uint32_t RXLENERFIS  : 1;        /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Status          */
+            __IM uint32_t RXORANGEFIS : 1;        /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t RXPAUSFIS   : 1;        /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Status                 */
+            __IM uint32_t RXFOVFIS    : 1;        /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Status         */
+            __IM uint32_t RXVLANGBFIS : 1;        /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Status         */
+            __IM uint32_t RXWDOGFIS   : 1;        /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t RXRCVERRFIS : 1;        /*!< [24..24] MMC Receive Error Frame Counter Interrupt Status                 */
+            __IM uint32_t RXCTRLFIS   : 1;        /*!< [25..25] MMC Receive Control Frame Counter Interrupt Status               */
+            uint32_t                  : 6;
+        } MMC_Receive_Interrupt_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Transmit_Interrupt;     /*!< (@ 0x00000108) MMC Transmit Interrupt Register                            */
+
+        struct
+        {
+            __IM uint32_t TXGBOCTIS    : 1;       /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Status               */
+            __IM uint32_t TXGBFRMIS    : 1;       /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Status               */
+            __IM uint32_t TXBCGFIS     : 1;       /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Status         */
+            __IM uint32_t TXMCGFIS     : 1;       /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Status         */
+            __IM uint32_t TX64OCTGBFIS : 1;       /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TX65T127OCTGBFIS : 1;   /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TX128T255OCTGBFIS : 1;  /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t TX256T511OCTGBFIS : 1;  /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t TX512T1023OCTGBFIS : 1; /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t TX1024TMAXOCTGBFIS : 1; /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t TXUCGBFIS : 1;          /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXMCGBFIS : 1;          /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXBCGBFIS : 1;          /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXUFLOWERFIS : 1;       /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXSCOLGFIS : 1;         /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXMCOLGFIS : 1;         /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter
+                                                   *   Interrupt Status                                                          */
+            __IM uint32_t TXDEFFIS    : 1;        /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Status             */
+            __IM uint32_t TXLATCOLFIS : 1;        /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXEXCOLFIS : 1;         /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXCARERFIS : 1;         /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXGOCTIS   : 1;         /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Status                 */
+            __IM uint32_t TXGFRMIS   : 1;         /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Status                 */
+            __IM uint32_t TXEXDEFFIS : 1;         /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            __IM uint32_t TXPAUSFIS   : 1;        /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Status                */
+            __IM uint32_t TXVLANGFIS  : 1;        /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Status            */
+            __IM uint32_t TXOSIZEGFIS : 1;        /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt
+                                                   *   Status                                                                    */
+            uint32_t : 6;
+        } MMC_Transmit_Interrupt_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMC_Receive_Interrupt_Mask; /*!< (@ 0x0000010C) MMC Receive Interrupt Mask Register                        */
+
+        struct
+        {
+            __IOM uint32_t RXGBFRMIM    : 1;       /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Mask                  */
+            __IOM uint32_t RXGBOCTIM    : 1;       /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Mask                  */
+            __IOM uint32_t RXGOCTIM     : 1;       /*!< [2..2] MMC Receive Good Octet Counter Interrupt Mask                      */
+            __IOM uint32_t RXBCGFIM     : 1;       /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Mask            */
+            __IOM uint32_t RXMCGFIM     : 1;       /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Mask            */
+            __IOM uint32_t RXCRCERFIM   : 1;       /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Mask                 */
+            __IOM uint32_t RXALGNERFIM  : 1;       /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Mask           */
+            __IOM uint32_t RXRUNTFIM    : 1;       /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Mask                      */
+            __IOM uint32_t RXJABERFIM   : 1;       /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Mask              */
+            __IOM uint32_t RXUSIZEGFIM  : 1;       /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Mask            */
+            __IOM uint32_t RXOSIZEGFIM  : 1;       /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Mask           */
+            __IOM uint32_t RX64OCTGBFIM : 1;       /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt
+                                                    *   Mask                                                                      */
+            __IOM uint32_t RX65T127OCTGBFIM : 1;   /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter
+                                                    *   Interrupt Mask                                                            */
+            __IOM uint32_t RX128T255OCTGBFIM : 1;  /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter
+                                                    *   Interrupt Mask                                                            */
+            __IOM uint32_t RX256T511OCTGBFIM : 1;  /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter
+                                                    *   Interrupt Mask                                                            */
+            __IOM uint32_t RX512T1023OCTGBFIM : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter
+                                                    *   Interrupt Mask                                                            */
+            __IOM uint32_t RX1024TMAXOCTGBFIM : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter
+                                                    *   Interrupt Mask                                                            */
+            __IOM uint32_t RXUCGFIM    : 1;        /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Mask            */
+            __IOM uint32_t RXLENERFIM  : 1;        /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Mask            */
+            __IOM uint32_t RXORANGEFIM : 1;        /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt
+                                                    *   Mask                                                                      */
+            __IOM uint32_t RXPAUSFIM   : 1;        /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Mask                   */
+            __IOM uint32_t RXFOVFIM    : 1;        /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Mask           */
+            __IOM uint32_t RXVLANGBFIM : 1;        /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Mask           */
+            __IOM uint32_t RXWDOGFIM   : 1;        /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt
+                                                    *   Mask                                                                      */
+            __IOM uint32_t RXRCVERRFIM : 1;        /*!< [24..24] MMC Receive Error Frame Counter Interrupt Mask                   */
+            __IOM uint32_t RXCTRLFIM   : 1;        /*!< [25..25] MMC Receive Control Frame Counter Interrupt Mask                 */
+            uint32_t                   : 6;
+        } MMC_Receive_Interrupt_Mask_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMC_Transmit_Interrupt_Mask; /*!< (@ 0x00000110) MMC Transmit Interrupt Mask Register                       */
+
+        struct
+        {
+            __IOM uint32_t TXGBOCTIM    : 1;        /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Mask                 */
+            __IOM uint32_t TXGBFRMIM    : 1;        /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Mask                 */
+            __IOM uint32_t TXBCGFIM     : 1;        /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Mask           */
+            __IOM uint32_t TXMCGFIM     : 1;        /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Mask           */
+            __IOM uint32_t TX64OCTGBFIM : 1;        /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TX65T127OCTGBFIM : 1;    /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TX128T255OCTGBFIM : 1;   /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter
+                                                     *   Interrupt Mask                                                            */
+            __IOM uint32_t TX256T511OCTGBFIM : 1;   /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter
+                                                     *   Interrupt Mask                                                            */
+            __IOM uint32_t TX512T1023OCTGBFIM : 1;  /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter
+                                                     *   Interrupt Mask                                                            */
+            __IOM uint32_t TX1024TMAXOCTGBFIM : 1;  /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter
+                                                     *   Interrupt Mask                                                            */
+            __IOM uint32_t TXUCGBFIM : 1;           /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXMCGBFIM : 1;           /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXBCGBFIM : 1;           /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXUFLOWERFIM : 1;        /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXSCOLGFIM : 1;          /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXMCOLGFIM : 1;          /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter
+                                                     *   Interrupt Mask                                                            */
+            __IOM uint32_t TXDEFFIM    : 1;         /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Mask               */
+            __IOM uint32_t TXLATCOLFIM : 1;         /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXEXCOLFIM : 1;          /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXCARERFIM : 1;          /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXGOCTIM   : 1;          /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Mask                   */
+            __IOM uint32_t TXGFRMIM   : 1;          /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Mask                   */
+            __IOM uint32_t TXEXDEFFIM : 1;          /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            __IOM uint32_t TXPAUSFIM   : 1;         /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Mask                  */
+            __IOM uint32_t TXVLANGFIM  : 1;         /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Mask              */
+            __IOM uint32_t TXOSIZEGFIM : 1;         /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt
+                                                     *   Mask                                                                      */
+            uint32_t : 6;
+        } MMC_Transmit_Interrupt_Mask_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Octet_Count_Good_Bad; /*!< (@ 0x00000114) Transmit Octet Count for Good and Bad Frames               */
+
+        struct
+        {
+            __IM uint32_t TXOCTGB : 32;        /*!< [31..0] This field indicates the number of bytes transmitted
+                                                *   in good and bad frames exclusive of preamble and retried
+                                                *   bytes.                                                                    */
+        } Tx_Octet_Count_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Frame_Count_Good_Bad; /*!< (@ 0x00000118) Transmit Frame Count for Good and Bad Frames               */
+
+        struct
+        {
+            __IM uint32_t TXFRMGB : 32;        /*!< [31..0] This field indicates the number of good and bad frames
+                                                *   transmitted, exclusive of retried frames.                                 */
+        } Tx_Frame_Count_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Broadcast_Frames_Good; /*!< (@ 0x0000011C) Transmit Frame Count for Good Broadcast Frames             */
+
+        struct
+        {
+            __IM uint32_t TXBCASTG : 32;        /*!< [31..0] This field indicates the number of transmitted good
+                                                 *   broadcast frames.                                                         */
+        } Tx_Broadcast_Frames_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Multicast_Frames_Good; /*!< (@ 0x00000120) Transmit Frame Count for Good Multicast Frames             */
+
+        struct
+        {
+            __IM uint32_t TXMCASTG : 32;        /*!< [31..0] This field indicates the number of transmitted good
+                                                 *   multicast frames.                                                         */
+        } Tx_Multicast_Frames_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_64Octets_Frames_Good_Bad; /*!< (@ 0x00000124) Transmit Octet Count for Good and Bad 64 Byte
+                                                    *                  Frames                                                     */
+
+        struct
+        {
+            __IM uint32_t TX64OCTGB : 32;          /*!< [31..0] This field indicates the number of transmitted good
+                                                    *   and bad frames with length of 64 bytes, exclusive of preamble
+                                                    *   and retried frames.                                                       */
+        } Tx_64Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x00000128) Transmit Octet Count for Good and Bad 65 to 127
+                                                         *              Bytes Frames                                               */
+
+        struct
+        {
+            __IM uint32_t TX65_127OCTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
+                                                         *   and bad frames with length between 65 and 127 (inclusive)
+                                                         *   bytes, exclusive of preamble and retried frames.                          */
+        } Tx_65To127Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x0000012C) Transmit Octet Count for Good and Bad 128 to
+                                                          *             255 Bytes Frames                                           */
+
+        struct
+        {
+            __IM uint32_t TX128_255OCTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
+                                                          *   and bad frames with length between 128 and 255 (inclusive)
+                                                          *   bytes, exclusive of preamble and retried frames.                          */
+        } Tx_128To255Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x00000130) Transmit Octet Count for Good and Bad 256 to
+                                                          *             511 Bytes Frames                                           */
+
+        struct
+        {
+            __IM uint32_t TX256_511OCTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
+                                                          *   and bad frames with length between 256 and 511 (inclusive)
+                                                          *   bytes, exclusive of preamble and retried frames.                          */
+        } Tx_256To511Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x00000134) Transmit Octet Count for Good and Bad 512 to
+                                                           *            1023 Bytes Frames                                          */
+
+        struct
+        {
+            __IM uint32_t TX512_1023OCTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
+                                                           *   and bad frames with length between 512 and 1,023 (inclusive)
+                                                           *   bytes, exclusive of preamble and retried frames.                          */
+        } Tx_512To1023Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x00000138) Transmit Octet Count for Good and Bad 1024 to
+                                                           *            Maxsize Bytes Frames                                       */
+
+        struct
+        {
+            __IM uint32_t TX1024_MAXOCTGB : 32;           /*!< [31..0] This field indicates the number of good and bad frames
+                                                           *   transmitted with length between 1,024 and maxsize (inclusive)
+                                                           *   bytes, exclusive of preamble and retried frames.                          */
+        } Tx_1024ToMaxOctets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Unicast_Frames_Good_Bad; /*!< (@ 0x0000013C) Transmit Frame Count for Good and Bad Unicast
+                                                   *                  Frames                                                     */
+
+        struct
+        {
+            __IM uint32_t TXUCASTGB : 32;         /*!< [31..0] This field indicates the number of transmitted good
+                                                   *   and bad unicast frames.                                                   */
+        } Tx_Unicast_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Multicast_Frames_Good_Bad; /*!< (@ 0x00000140) Transmit Frame Count for Good and Bad Multicast
+                                                     *                  Frames                                                     */
+
+        struct
+        {
+            __IM uint32_t TXMCASTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
+                                                     *   and bad multicast frames.                                                 */
+        } Tx_Multicast_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Broadcast_Frames_Good_Bad; /*!< (@ 0x00000144) Transmit Frame Count for Good and Bad Broadcast
+                                                     *                  Frames                                                     */
+
+        struct
+        {
+            __IM uint32_t TXBCASTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
+                                                     *   and bad broadcast frames.                                                 */
+        } Tx_Broadcast_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Underflow_Error_Frames; /*!< (@ 0x00000148) Transmit Frame Count for Underflow Error Frames            */
+
+        struct
+        {
+            __IM uint32_t TXUNDRFLW : 16;        /*!< [15..0] This field indicates the number of frames aborted because
+                                                  *   of frame underflow error.                                                 */
+            uint32_t : 16;
+        } Tx_Underflow_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Single_Collision_Good_Frames; /*!< (@ 0x0000014C) Transmit Frame Count for Frames Transmitted after
+                                                        *               Single Collision                                           */
+
+        struct
+        {
+            __IM uint32_t TXSNGLCOLG : 16;             /*!< [15..0] This field indicates the number of successfully transmitted
+                                                        *   frames after a single collision in the half-duplex mode.                  */
+            uint32_t : 16;
+        } Tx_Single_Collision_Good_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Multiple_Collision_Good_Frames; /*!< (@ 0x00000150) Transmit Frame Count for Frames Transmitted after
+                                                          *             Multiple Collision                                         */
+
+        struct
+        {
+            __IM uint32_t TXMULTCOLG : 16;               /*!< [15..0] This field indicates the number of successfully transmitted
+                                                          *   frames after multiple collisions in the half-duplex mode.                 */
+            uint32_t : 16;
+        } Tx_Multiple_Collision_Good_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Deferred_Frames; /*!< (@ 0x00000154) Transmit Frame Count for Deferred Frames                   */
+
+        struct
+        {
+            __IM uint32_t TXDEFRD : 16;   /*!< [15..0] This field indicates the number of successfully transmitted
+                                           *   frames after a deferral in the half-duplex mode.                          */
+            uint32_t : 16;
+        } Tx_Deferred_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Late_Collision_Frames; /*!< (@ 0x00000158) Transmit Frame Count for Late Collision Error
+                                                 *                  Frames                                                     */
+
+        struct
+        {
+            __IM uint32_t TXLATECOL : 16;       /*!< [15..0] This field indicates the number of frames aborted because
+                                                 *   of late collision error.                                                  */
+            uint32_t : 16;
+        } Tx_Late_Collision_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Excessive_Collision_Frames; /*!< (@ 0x0000015C) Transmit Frame Count for Excessive Collision
+                                                      *                 Error Frames                                               */
+
+        struct
+        {
+            __IM uint32_t TXEXSCOL : 16;             /*!< [15..0] This field indicates the number of frames aborted because
+                                                      *   of excessive (16) collision error.                                        */
+            uint32_t : 16;
+        } Tx_Excessive_Collision_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Carrier_Error_Frames; /*!< (@ 0x00000160) Transmit Frame Count for Carrier Sense Error
+                                                *                  Frames                                                     */
+
+        struct
+        {
+            __IM uint32_t TXCARR : 16;         /*!< [15..0] This field indicates the number of frames aborted because
+                                                *   of carrier sense error (no carrier or loss of carrier).                   */
+            uint32_t : 16;
+        } Tx_Carrier_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Octet_Count_Good; /*!< (@ 0x00000164) Transmit Octet Count for Good Frames                       */
+
+        struct
+        {
+            __IM uint32_t TXOCTG : 32;     /*!< [31..0] TXOCTG                                                            */
+        } Tx_Octet_Count_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Frame_Count_Good; /*!< (@ 0x00000168) Transmit Frame Count for Good Frames                       */
+
+        struct
+        {
+            __IM uint32_t TXFRMG : 32;     /*!< [31..0] This field indicates the number of transmitted good
+                                            *   frames, exclusive of preamble.                                            */
+        } Tx_Frame_Count_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Excessive_Deferral_Error; /*!< (@ 0x0000016C) Transmit Frame Count for Excessive Deferral Error
+                                                    *                  Frames                                                     */
+
+        struct
+        {
+            __IM uint32_t TXEXSDEF : 16;           /*!< [15..0] This field indicates the number of frames aborted because
+                                                    *   of excessive deferral error, that is, frames deferred for
+                                                    *   more than two max sized frame times.                                      */
+            uint32_t : 16;
+        } Tx_Excessive_Deferral_Error_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Pause_Frames;  /*!< (@ 0x00000170) Transmit Frame Count for Good PAUSE Frames                 */
+
+        struct
+        {
+            __IM uint32_t TXPAUSE : 16; /*!< [15..0] This field indicates the number of transmitted good
+                                         *   PAUSE frames.                                                             */
+            uint32_t : 16;
+        } Tx_Pause_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_VLAN_Frames_Good; /*!< (@ 0x00000174) Transmit Frame Count for Good VLAN Frames                  */
+
+        struct
+        {
+            __IM uint32_t TXVLANG : 32;    /*!< [31..0] This register maintains the number of transmitted good
+                                            *   VLAN frames, exclusive of retried frames.                                 */
+        } Tx_VLAN_Frames_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_OSize_Frames_Good; /*!< (@ 0x00000178) Transmit Frame Count for Good Oversize Frames              */
+
+        struct
+        {
+            __IM uint32_t TXOSIZG : 16;     /*!< [15..0] This field indicates the number of frames transmitted
+                                             *   without errors and with length greater than the maxsize
+                                             *   (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes
+                                             *   if enabled in bit [27] of MAC Configuration Register (MAC_Configuration))
+                                             */
+            uint32_t : 16;
+        } Tx_OSize_Frames_Good_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IM uint32_t Rx_Frames_Count_Good_Bad; /*!< (@ 0x00000180) Receive Frame Count for Good and Bad Frames                */
+
+        struct
+        {
+            __IM uint32_t RXFRMGB : 32;         /*!< [31..0] This field indicates the number of received good and
+                                                 *   bad frames.                                                               */
+        } Rx_Frames_Count_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Octet_Count_Good_Bad; /*!< (@ 0x00000184) Receive Octet Count for Good and Bad Frames                */
+
+        struct
+        {
+            __IM uint32_t RXOCTGB : 32;        /*!< [31..0] This field indicates the number of bytes received, exclusive
+                                                *   of preamble, in good and bad frames.                                      */
+        } Rx_Octet_Count_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Octet_Count_Good; /*!< (@ 0x00000188) Receive Octet Count for Good Frames                        */
+
+        struct
+        {
+            __IM uint32_t RXOCTG : 32;     /*!< [31..0] This field indicates the number of bytes received, exclusive
+                                            *   of preamble, only in good frames.                                         */
+        } Rx_Octet_Count_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Broadcast_Frames_Good; /*!< (@ 0x0000018C) Receive Frame Count for Good Broadcast Frames              */
+
+        struct
+        {
+            __IM uint32_t RXBCASTG : 32;        /*!< [31..0] This field indicates the number of received good broadcast
+                                                 *   frames.                                                                   */
+        } Rx_Broadcast_Frames_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Multicast_Frames_Good; /*!< (@ 0x00000190) Receive Frame Count for Good Multicast Frames              */
+
+        struct
+        {
+            __IM uint32_t RXMCASTG : 32;        /*!< [31..0] This field indicates the number of received good multicast
+                                                 *   frames.                                                                   */
+        } Rx_Multicast_Frames_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_CRC_Error_Frames; /*!< (@ 0x00000194) Receive Frame Count for CRC Error Frames                   */
+
+        struct
+        {
+            __IM uint32_t RXCRCERR : 16;   /*!< [15..0] This field indicates the number of frames received with
+                                            *   CRC error.                                                                */
+            uint32_t : 16;
+        } Rx_CRC_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Alignment_Error_Frames; /*!< (@ 0x00000198) Receive Frame Count for Alignment Error Frames             */
+
+        struct
+        {
+            __IM uint32_t RXALGNERR : 16;        /*!< [15..0] This field indicates the number of frames received with
+                                                  *   alignment (dribble) error. This field is valid only in
+                                                  *   the 10 or 100 Mbps mode.                                                  */
+            uint32_t : 16;
+        } Rx_Alignment_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Runt_Error_Frames; /*!< (@ 0x0000019C) Receive Frame Count for Runt Error Frames                  */
+
+        struct
+        {
+            __IM uint32_t RXRUNTERR : 16;   /*!< [15..0] This field indicates the number of frames received with
+                                             *   runt error (< 64 bytes and CRC error).                                    */
+            uint32_t : 16;
+        } Rx_Runt_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Jabber_Error_Frames; /*!< (@ 0x000001A0) Receive Frame Count for Jabber Error Frames                */
+
+        struct
+        {
+            __IM uint32_t RXJABERR : 16;      /*!< [15..0] This field indicates the number of giant frames received
+                                               *   with length (including CRC) greater than 1,518 bytes (1,522
+                                               *   bytes for VLAN tagged) and with CRC error. If Jumbo Frame
+                                               *   mode is enabled, then frames of length greater than 9,018
+                                               *   bytes (9,022 for VLAN tagged) are considered as giant frames.             */
+            uint32_t : 16;
+        } Rx_Jabber_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Undersize_Frames_Good; /*!< (@ 0x000001A4) Receive Frame Count for Undersize Frames                   */
+
+        struct
+        {
+            __IM uint32_t RXUNDERSZG : 16;      /*!< [15..0] This field indicates the number of frames received with
+                                                 *   length less than 64 bytes and without errors.                             */
+            uint32_t : 16;
+        } Rx_Undersize_Frames_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Oversize_Frames_Good; /*!< (@ 0x000001A8) Receive Frame Count for Oversize Frames                    */
+
+        struct
+        {
+            __IM uint32_t RXOVERSZG : 16;      /*!< [15..0] This field indicates the number of frames received without
+                                                *   errors, with length greater than the maxsize (1,518 or
+                                                *   1,522 for VLAN tagged frames; 2,000 bytes if enabled in
+                                                *   bit [27] of MAC Configuration Register (MAC_Configuration)).              */
+            uint32_t : 16;
+        } Rx_Oversize_Frames_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_64Octets_Frames_Good_Bad; /*!< (@ 0x000001AC) Receive Frame Count for Good and Bad 64 Byte
+                                                    *                  Frames                                                     */
+
+        struct
+        {
+            __IM uint32_t RX64OCTGB : 32;          /*!< [31..0] This field indicates the number of received good and
+                                                    *   bad frames with length 64 bytes, exclusive of preamble.                   */
+        } Rx_64Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x000001B0) Receive Frame Count for Good and Bad 65 to 127
+                                                         *              Bytes Frames                                               */
+
+        struct
+        {
+            __IM uint32_t RX65_127OCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
+                                                         *   bad frames received with length between 65 and 127 (inclusive)
+                                                         *   bytes, exclusive of preamble.                                             */
+        } Rx_65To127Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x000001B4) Receive Frame Count for Good and Bad 128 to 255
+                                                          *             Bytes Frames                                               */
+
+        struct
+        {
+            __IM uint32_t RX128_255OCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
+                                                          *   bad frames with length between 128 and 255 (inclusive)
+                                                          *   bytes, exclusive of preamble.                                             */
+        } Rx_128To255Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x000001B8) Receive Frame Count for Good and Bad 256 to 511
+                                                          *             Bytes Frames                                               */
+
+        struct
+        {
+            __IM uint32_t RX256_511OCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
+                                                          *   bad frames with length between 256 and 511 (inclusive)
+                                                          *   bytes, exclusive of preamble.                                             */
+        } Rx_256To511Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x000001BC) Receive Frame Count for Good and Bad 512 to 1,023
+                                                           *            Bytes Frames                                               */
+
+        struct
+        {
+            __IM uint32_t RX512_1023OCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
+                                                           *   bad frames with length between 512 and 1,023 (inclusive)
+                                                           *   bytes, exclusive of preamble.                                             */
+        } Rx_512To1023Octets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x000001C0) Receive Frame Count for Good and Bad 1,024 to
+                                                           *            Maxsize Bytes Frames                                       */
+
+        struct
+        {
+            __IM uint32_t RX1024_MAXOCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
+                                                           *   bad frames with length between 1,024 and maxsize (inclusive)
+                                                           *   bytes, exclusive of preamble and retried frames.                          */
+        } Rx_1024ToMaxOctets_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Unicast_Frames_Good; /*!< (@ 0x000001C4) Receive Frame Count for Good Unicast Frames                */
+
+        struct
+        {
+            __IM uint32_t RXUCASTG : 32;      /*!< [31..0] This field indicates the number of received good unicast
+                                               *   frames.                                                                   */
+        } Rx_Unicast_Frames_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Length_Error_Frames; /*!< (@ 0x000001C8) Receive Frame Count for Length Error Frames                */
+
+        struct
+        {
+            __IM uint32_t RXLENERR : 16;      /*!< [15..0] RXLENERR                                                          */
+            uint32_t               : 16;
+        } Rx_Length_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Out_Of_Range_Type_Frames; /*!< (@ 0x000001CC) Receive Frame Count for Out of Range Frames                */
+
+        struct
+        {
+            __IM uint32_t RXOUTOFRNG : 16;         /*!< [15..0] This field indicates the number of received frames with
+                                                    *   length field not equal to the valid frame size (greater
+                                                    *   than 1,500 but less than 1,536).                                          */
+            uint32_t : 16;
+        } Rx_Out_Of_Range_Type_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Pause_Frames;     /*!< (@ 0x000001D0) Receive Frame Count for PAUSE Frames                       */
+
+        struct
+        {
+            __IM uint32_t RXPAUSEFRM : 16; /*!< [15..0] This field indicates the number of received good and
+                                            *   valid PAUSE frames.                                                       */
+            uint32_t : 16;
+        } Rx_Pause_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_FIFO_Overflow_Frames; /*!< (@ 0x000001D4) Receive Frame Count for FIFO Overflow Frames               */
+
+        struct
+        {
+            __IM uint32_t RXFIFOOVFL : 16;     /*!< [15..0] This field indicates the number of received frames missed
+                                                *   because of FIFO overflow.                                                 */
+            uint32_t : 16;
+        } Rx_FIFO_Overflow_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_VLAN_Frames_Good_Bad; /*!< (@ 0x000001D8) Receive Frame Count for Good and Bad VLAN Frames           */
+
+        struct
+        {
+            __IM uint32_t RXVLANFRGB : 32;     /*!< [31..0] This field indicates the number of received good and
+                                                *   bad VLAN frames.                                                          */
+        } Rx_VLAN_Frames_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Watchdog_Error_Frames; /*!< (@ 0x000001DC) Receive Frame Count for Watchdog Error Frames              */
+
+        struct
+        {
+            __IM uint32_t RXWDGERR : 16;        /*!< [15..0] This field indicates the number of frames received with
+                                                 *   error because of the watchdog timeout error (frames with
+                                                 *   more than 2,048 bytes or value programmed in Watchdog Timeout
+                                                 *   Register (WDog_Timeout)).                                                 */
+            uint32_t : 16;
+        } Rx_Watchdog_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Receive_Error_Frames; /*!< (@ 0x000001E0) Receive Frame Count for Receive Error Frames               */
+
+        struct
+        {
+            __IM uint32_t RXRCVERR : 16;       /*!< [15..0] This field indicates the number of frames received with
+                                                *   error because of the GMII/MII RXER error or Frame Extension
+                                                *   error on GMII.                                                            */
+            uint32_t : 16;
+        } Rx_Receive_Error_Frames_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Control_Frames_Good; /*!< (@ 0x000001E4) Receive Frame Count for Good Control Frames                */
+
+        struct
+        {
+            __IM uint32_t RXCTRLG : 32;       /*!< [31..0] This field indicates the number of good control frames
+                                               *   received.                                                                 */
+        } Rx_Control_Frames_Good_b;
+    };
+    __IM uint32_t RESERVED4[134];
+
+    union
+    {
+        __IOM uint32_t GMACTRGSEL;     /*!< (@ 0x00000400) GMAC PTP Trigger Select Register                           */
+
+        struct
+        {
+            __IOM uint32_t TRGSEL : 2; /*!< [1..0] Select PTP Timestamp Trigger for GMAC IP                           */
+            uint32_t              : 30;
+        } GMACTRGSEL_b;
+    };
+    __IM uint32_t RESERVED5[63];
+
+    union
+    {
+        __IOM uint32_t HASH_TABLE_REG[8]; /*!< (@ 0x00000500) Hash Table Register [0..7] (n = 0 to 7)                    */
+
+        struct
+        {
+            __IOM uint32_t HT : 32;       /*!< [31..0] This field contains the nth 32 bits [31:0] of the Hash
+                                           *   table.                                                                    */
+        } HASH_TABLE_REG_b[8];
+    };
+    __IM uint32_t RESERVED6[26];
+
+    union
+    {
+        __IOM uint32_t VLAN_Hash_Table_Reg; /*!< (@ 0x00000588) VLAN Hash Table Register                                   */
+
+        struct
+        {
+            __IOM uint32_t VLHT : 16;       /*!< [15..0] VLAN Hash Table                                                   */
+            uint32_t            : 16;
+        } VLAN_Hash_Table_Reg_b;
+    };
+    __IM uint32_t RESERVED7[93];
+
+    union
+    {
+        __IOM uint32_t Timestamp_Control;   /*!< (@ 0x00000700) Timestamp Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t TSENA       : 1; /*!< [0..0] Timestamp Enable                                                   */
+            uint32_t                   : 7;
+            __IOM uint32_t TSENALL     : 1; /*!< [8..8] Enable Timestamp for all Frames                                    */
+            __IOM uint32_t TSCTRLSSR   : 1; /*!< [9..9] Timestamp Digital or Binary Rollover Control                       */
+            __IOM uint32_t TSVER2ENA   : 1; /*!< [10..10] Enable PTP packet Processing for Version 2 Format                */
+            __IOM uint32_t TSIPENA     : 1; /*!< [11..11] Enable Processing of PTP over Ethernet Frames                    */
+            __IOM uint32_t TSIPV6ENA   : 1; /*!< [12..12] Enable Processing of PTP Frames Sent Over IPv6 UDP               */
+            __IOM uint32_t TSIPV4ENA   : 1; /*!< [13..13] Enable Processing of PTP Frames Sent over IPv4 UDP               */
+            __IOM uint32_t TSEVNTENA   : 1; /*!< [14..14] Enable Timestamp Snapshot for Event Messages                     */
+            __IOM uint32_t TSMSTRENA   : 1; /*!< [15..15] Enable Snapshot for Messages Relevant to Master                  */
+            __IOM uint32_t SNAPTYPSEL  : 2; /*!< [17..16] Select PTP packets for Taking Snapshots                          */
+            __IOM uint32_t TSENMACADDR : 1; /*!< [18..18] Enable MAC address for PTP Frame Filtering                       */
+            uint32_t                   : 5;
+            __IOM uint32_t ATSFC       : 1; /*!< [24..24] Auxiliary Snapshot FIFO Clear                                    */
+            __IOM uint32_t ATSEN0      : 1; /*!< [25..25] Auxiliary Snapshot 0 Enable                                      */
+            __IOM uint32_t ATSEN1      : 1; /*!< [26..26] Auxiliary Snapshot 1 Enable                                      */
+            uint32_t                   : 5;
+        } Timestamp_Control_b;
+    };
+    __IM uint32_t RESERVED8[9];
+
+    union
+    {
+        __IM uint32_t Timestamp_Status; /*!< (@ 0x00000728) Timestamp Status Register                                  */
+
+        struct
+        {
+            uint32_t                : 2;
+            __IM uint32_t AUXTSTRIG : 1; /*!< [2..2] Auxiliary Timestamp Trigger Snapshot                               */
+            uint32_t                : 13;
+            __IM uint32_t ATSSTN    : 4; /*!< [19..16] Auxiliary Timestamp Snapshot Trigger Identifier                  */
+            uint32_t                : 4;
+            __IM uint32_t ATSSTM    : 1; /*!< [24..24] Auxiliary Timestamp Snapshot Trigger Missed                      */
+            __IM uint32_t ATSNS     : 5; /*!< [29..25] Number of Auxiliary Timestamp Snapshots                          */
+            uint32_t                : 2;
+        } Timestamp_Status_b;
+    };
+    __IM uint32_t RESERVED9;
+
+    union
+    {
+        __IM uint32_t Auxiliary_Timestamp_Nanoseconds; /*!< (@ 0x00000730) Auxiliary Timestamp - Nanoseconds Register            */
+
+        struct
+        {
+            __IM uint32_t AUXTSLO : 31;                /*!< [30..0] Contains the lower 32 bits (nanoseconds field) of the
+                                                        *   auxiliary timestamp.                                                      */
+            uint32_t : 1;
+        } Auxiliary_Timestamp_Nanoseconds_b;
+    };
+
+    union
+    {
+        __IM uint32_t Auxiliary_Timestamp_Seconds; /*!< (@ 0x00000734) Auxiliary Timestamp - Seconds Register                     */
+
+        struct
+        {
+            __IM uint32_t AUXTSHI : 32;            /*!< [31..0] Contains the upper 32 bits (Seconds field) of the auxiliary
+                                                    *   timestamp.                                                                */
+        } Auxiliary_Timestamp_Seconds_b;
+    };
+    __IM uint32_t RESERVED10[50];
+
+    union
+    {
+        __IOM uint32_t MAR16_H;         /*!< (@ 0x00000800) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR16_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR16_L;         /*!< (@ 0x00000804) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR16_L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR17_H;         /*!< (@ 0x00000808) MAC ADDRESS High Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
+            uint32_t              : 8;
+            __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
+            __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
+            __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
+        } MAR17_H_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAR17_L;         /*!< (@ 0x0000080C) MAC ADDRESS Low Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
+        } MAR17_L_b;
+    };
+    __IM uint32_t RESERVED11[508];
+
+    union
+    {
+        __IOM uint32_t Bus_Mode;       /*!< (@ 0x00001000) Bus Mode Register                                          */
+
+        struct
+        {
+            __IOM uint32_t SWR   : 1;  /*!< [0..0] Software Reset                                                     */
+            __IM uint32_t  DA    : 1;  /*!< [1..1] DMA Arbitration Scheme                                             */
+            __IOM uint32_t DSL   : 5;  /*!< [6..2] Descriptor Skip Length                                             */
+            __IOM uint32_t ATDS  : 1;  /*!< [7..7] Enhanced Descriptor Size                                           */
+            __IOM uint32_t PBL   : 6;  /*!< [13..8] Programmable Burst Length                                         */
+            __IM uint32_t  PR    : 2;  /*!< [15..14] Priority Ratio                                                   */
+            __IOM uint32_t FB    : 1;  /*!< [16..16] Fixed Burst                                                      */
+            __IOM uint32_t RPBL  : 6;  /*!< [22..17] RX DMA PBL                                                       */
+            __IOM uint32_t USP   : 1;  /*!< [23..23] Use Separate PBL                                                 */
+            __IOM uint32_t PBLx8 : 1;  /*!< [24..24] PBLx8 Mode                                                       */
+            __IOM uint32_t AAL   : 1;  /*!< [25..25] Address Aligned Beats                                            */
+            __IM uint32_t  MB    : 1;  /*!< [26..26] Mixed Burst                                                      */
+            __IM uint32_t  TXPR  : 1;  /*!< [27..27] Transmit Priority                                                */
+            __IM uint32_t  PRWG  : 2;  /*!< [29..28] Channel Priority Weights                                         */
+            uint32_t             : 1;
+            __IM uint32_t RIB    : 1;  /*!< [31..31] Rebuild INCRx Burst                                              */
+        } Bus_Mode_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Transmit_Poll_Demand; /*!< (@ 0x00001004) Transmit Poll Demand Register                              */
+
+        struct
+        {
+            __IOM uint32_t TPD : 32;         /*!< [31..0] Transmit Poll Demand                                              */
+        } Transmit_Poll_Demand_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Receive_Poll_Demand; /*!< (@ 0x00001008) Receive Poll Demand Register                               */
+
+        struct
+        {
+            __IOM uint32_t RPD : 32;        /*!< [31..0] Receive Poll Demand                                               */
+        } Receive_Poll_Demand_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Receive_Descriptor_List_Address; /*!< (@ 0x0000100C) Receive Descriptor List Address Register                */
+
+        struct
+        {
+            uint32_t                    : 2;
+            __IOM uint32_t RDESLA_32bit : 30; /*!< [31..2] Start of Receive List                                             */
+        } Receive_Descriptor_List_Address_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Transmit_Descriptor_List_Address; /*!< (@ 0x00001010) Transmit Descriptor List Address Register              */
+
+        struct
+        {
+            uint32_t                    : 2;
+            __IOM uint32_t TDESLA_32bit : 30; /*!< [31..2] Start of Transmit List                                            */
+        } Transmit_Descriptor_List_Address_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Status;         /*!< (@ 0x00001014) Status Register                                            */
+
+        struct
+        {
+            __IOM uint32_t TI   : 1;   /*!< [0..0] Transmit Interrupt                                                 */
+            __IOM uint32_t TPS  : 1;   /*!< [1..1] Transmit Process Stopped                                           */
+            __IOM uint32_t TU   : 1;   /*!< [2..2] Transmit Buffer Unavailable                                        */
+            __IOM uint32_t TJT  : 1;   /*!< [3..3] Transmit Jabber Timeout                                            */
+            __IOM uint32_t OVF  : 1;   /*!< [4..4] Receive Overflow                                                   */
+            __IOM uint32_t UNF  : 1;   /*!< [5..5] Transmit Underflow                                                 */
+            __IOM uint32_t RI   : 1;   /*!< [6..6] Receive Interrupt                                                  */
+            __IOM uint32_t RU   : 1;   /*!< [7..7] Receive Buffer Unavailable                                         */
+            __IOM uint32_t RPS  : 1;   /*!< [8..8] Receive Process Stopped                                            */
+            __IOM uint32_t RWT  : 1;   /*!< [9..9] Receive Watchdog Timeout                                           */
+            __IOM uint32_t ETI  : 1;   /*!< [10..10] Early Transmit Interrupt                                         */
+            uint32_t            : 2;
+            __IOM uint32_t FBI  : 1;   /*!< [13..13] Fatal Bus Error Interrupt                                        */
+            __IOM uint32_t ERI  : 1;   /*!< [14..14] Early Receive Interrupt                                          */
+            __IOM uint32_t AIS  : 1;   /*!< [15..15] Abnormal Interrupt Summary                                       */
+            __IOM uint32_t NIS  : 1;   /*!< [16..16] Normal Interrupt Summary                                         */
+            __IM uint32_t  RS   : 3;   /*!< [19..17] Received Process State                                           */
+            __IM uint32_t  TS   : 3;   /*!< [22..20] Transmit Process State                                           */
+            __IM uint32_t  EB   : 3;   /*!< [25..23] Error Bits                                                       */
+            uint32_t            : 1;
+            __IM uint32_t GMI   : 1;   /*!< [27..27] GMAC MMC Interrupt                                               */
+            __IM uint32_t GPI   : 1;   /*!< [28..28] GMAC PMT Interrupt                                               */
+            __IM uint32_t TTI   : 1;   /*!< [29..29] Timestamp Trigger Interrupt                                      */
+            __IM uint32_t GLPII : 1;   /*!< [30..30] GMAC LPI Interrupt                                               */
+            uint32_t            : 1;
+        } Status_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Operation_Mode; /*!< (@ 0x00001018) Operation Mode Register                                    */
+
+        struct
+        {
+            uint32_t           : 1;
+            __IOM uint32_t SR  : 1;    /*!< [1..1] Start or Stop Receive                                              */
+            __IOM uint32_t OSF : 1;    /*!< [2..2] Operate on Second Frame                                            */
+            __IOM uint32_t RTC : 2;    /*!< [4..3] Receive Threshold Control                                          */
+            __IOM uint32_t DGF : 1;    /*!< [5..5] Drop Giant Frames                                                  */
+            __IOM uint32_t FUF : 1;    /*!< [6..6] Forward Undersized Good Frames                                     */
+            __IOM uint32_t FEF : 1;    /*!< [7..7] Forward Error Frames                                               */
+            __IOM uint32_t EFC : 1;    /*!< [8..8] Enable HW Flow Control                                             */
+            __IOM uint32_t RFA : 2;    /*!< [10..9] Threshold for Activating Flow Control (in half-duplex
+                                        *   and full-duplex)                                                          */
+            __IOM uint32_t RFD : 2;    /*!< [12..11] Threshold for Deactivating Flow Control (in half-duplex
+                                        *   and full-duplex)                                                          */
+            __IOM uint32_t ST  : 1;    /*!< [13..13] Start or Stop Transmission Command                               */
+            __IOM uint32_t TTC : 3;    /*!< [16..14] Transmit Threshold Control                                       */
+            uint32_t           : 3;
+            __IOM uint32_t FTF : 1;    /*!< [20..20] Flush Transmit FIFO                                              */
+            __IOM uint32_t TSF : 1;    /*!< [21..21] Transmit Store and Forward                                       */
+            uint32_t           : 3;
+            __IOM uint32_t RSF : 1;    /*!< [25..25] Receive Store and Forward                                        */
+            __IOM uint32_t DT  : 1;    /*!< [26..26] Disable Dropping of TCP/IP Checksum Error Frames                 */
+            uint32_t           : 5;
+        } Operation_Mode_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Interrupt_Enable; /*!< (@ 0x0000101C) Interrupt Enable Register                                  */
+
+        struct
+        {
+            __IOM uint32_t TIE : 1;      /*!< [0..0] Transmit Interrupt Enable                                          */
+            __IOM uint32_t TSE : 1;      /*!< [1..1] Transmit Stopped Enable                                            */
+            __IOM uint32_t TUE : 1;      /*!< [2..2] Transmit Buffer Unavailable Enable                                 */
+            __IOM uint32_t TJE : 1;      /*!< [3..3] Transmit Jabber Timeout Enable                                     */
+            __IOM uint32_t OVE : 1;      /*!< [4..4] Overflow Interrupt Enable                                          */
+            __IOM uint32_t UNE : 1;      /*!< [5..5] Underflow Interrupt Enable                                         */
+            __IOM uint32_t RIE : 1;      /*!< [6..6] Receive Interrupt Enable                                           */
+            __IOM uint32_t RUE : 1;      /*!< [7..7] Receive Buffer Unavailable Enable                                  */
+            __IOM uint32_t RSE : 1;      /*!< [8..8] Receive Stopped Enable                                             */
+            __IOM uint32_t RWE : 1;      /*!< [9..9] Receive Watchdog Timeout Enable                                    */
+            __IOM uint32_t ETE : 1;      /*!< [10..10] Early Transmit Interrupt Enable                                  */
+            uint32_t           : 2;
+            __IOM uint32_t FBE : 1;      /*!< [13..13] Fatal Bus Error Enable                                           */
+            __IOM uint32_t ERE : 1;      /*!< [14..14] Early Receive Interrupt Enable                                   */
+            __IOM uint32_t AIE : 1;      /*!< [15..15] Abnormal Interrupt Summary Enable                                */
+            __IOM uint32_t NIE : 1;      /*!< [16..16] Normal Interrupt Summary Enable                                  */
+            uint32_t           : 15;
+        } Interrupt_Enable_b;
+    };
+
+    union
+    {
+        __IM uint32_t Missed_Frame_And_Buffer_Overflow_Counter; /*!< (@ 0x00001020) Missed Frame and Buffer Overflow Counter Register */
+
+        struct
+        {
+            __IM uint32_t MISFRMCNT : 16;                       /*!< [15..0] Missed Frame Counter                                              */
+            __IM uint32_t MISCNTOVF : 1;                        /*!< [16..16] Overflow Bit for Missed Frame Counter                            */
+            __IM uint32_t OVFFRMCNT : 11;                       /*!< [27..17] Overflow Frame Counter                                           */
+            __IM uint32_t OVFCNTOVF : 1;                        /*!< [28..28] Overflow Bit for FIFO Overflow Counter                           */
+            uint32_t                : 3;
+        } Missed_Frame_And_Buffer_Overflow_Counter_b;
+    };
+
+    union
+    {
+        __IOM uint32_t Receive_Interrupt_Watchdog_Timer; /*!< (@ 0x00001024) Receive Interrupt Watchdog Timer Register              */
+
+        struct
+        {
+            __IOM uint32_t RIWT : 8;                     /*!< [7..0] RI Watchdog Timer Count                                            */
+            uint32_t            : 24;
+        } Receive_Interrupt_Watchdog_Timer_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AXI_Bus_Mode;        /*!< (@ 0x00001028) AXI Bus Mode Register                                      */
+
+        struct
+        {
+            __IM uint32_t  UNDEF       : 1; /*!< [0..0] AXI Undefined Burst Length                                         */
+            __IOM uint32_t BLEN4       : 1; /*!< [1..1] AXI Burst Length 4                                                 */
+            __IOM uint32_t BLEN8       : 1; /*!< [2..2] AXI Burst Length 8                                                 */
+            __IOM uint32_t BLEN16      : 1; /*!< [3..3] AXI Burst Length 16                                                */
+            uint32_t                   : 8;
+            __IM uint32_t  AXI_AAL     : 1; /*!< [12..12] Address-Aligned Beats                                            */
+            __IOM uint32_t ONEKBBE     : 1; /*!< [13..13] 1 KB Boundary Crossing Enable for the GMAC-AXI Master            */
+            uint32_t                   : 2;
+            __IOM uint32_t RD_OSR_LMT  : 2; /*!< [17..16] AXI Maximum Read OutStanding Request Limit                       */
+            uint32_t                   : 2;
+            __IOM uint32_t WR_OSR_LMT  : 2; /*!< [21..20] AXI Maximum Write OutStanding Request Limit                      */
+            uint32_t                   : 8;
+            __IOM uint32_t LPI_XIT_FRM : 1; /*!< [30..30] Unlock on Magic Packet or Remote Wake-Up Frame                   */
+            __IOM uint32_t EN_LPI      : 1; /*!< [31..31] Enable Low Power Interface (LPI)                                 */
+        } AXI_Bus_Mode_b;
+    };
+
+    union
+    {
+        __IM uint32_t AXI_Status;       /*!< (@ 0x0000102C) AXI Status Register                                        */
+
+        struct
+        {
+            __IM uint32_t AXWHSTS  : 1; /*!< [0..0] AXI Master Write Channel                                           */
+            __IM uint32_t AXIRDSTS : 1; /*!< [1..1] AXI Master Read Channel Status                                     */
+            uint32_t               : 30;
+        } AXI_Status_b;
+    };
+    __IM uint32_t RESERVED12[6];
+
+    union
+    {
+        __IM uint32_t Current_Host_Transmit_Descriptor; /*!< (@ 0x00001048) Current Host Transmit Descriptor Register              */
+
+        struct
+        {
+            __IM uint32_t CURTDESAPTR : 32;             /*!< [31..0] Host Transmit Descriptor Address Pointer                          */
+        } Current_Host_Transmit_Descriptor_b;
+    };
+
+    union
+    {
+        __IM uint32_t Current_Host_Receive_Descriptor; /*!< (@ 0x0000104C) Current Host Receive Descriptor Register                */
+
+        struct
+        {
+            __IM uint32_t CURRDESAPTR : 32;            /*!< [31..0] Host Receive Descriptor Address Pointer                           */
+        } Current_Host_Receive_Descriptor_b;
+    };
+
+    union
+    {
+        __IM uint32_t Current_Host_Transmit_Buffer_Address; /*!< (@ 0x00001050) Current Host Transmit Buffer Address Register      */
+
+        struct
+        {
+            __IM uint32_t CURTBUFAPTR : 32;                 /*!< [31..0] Host Transmit Buffer Address Pointer                              */
+        } Current_Host_Transmit_Buffer_Address_b;
+    };
+
+    union
+    {
+        __IM uint32_t Current_Host_Receive_Buffer_Address; /*!< (@ 0x00001054) Current Host Receive Buffer Address Register        */
+
+        struct
+        {
+            __IM uint32_t CURRBUFAPTR : 32;                /*!< [31..0] Host Receive Buffer Address Pointer                               */
+        } Current_Host_Receive_Buffer_Address_b;
+    };
+
+    union
+    {
+        __IM uint32_t HW_Feature;           /*!< (@ 0x00001058) HW Feature Register                                        */
+
+        struct
+        {
+            __IM uint32_t MIISEL       : 1; /*!< [0..0] 10 or 100 Mbps support                                             */
+            __IM uint32_t GMIISEL      : 1; /*!< [1..1] 1000 Mbps support                                                  */
+            __IM uint32_t HDSEL        : 1; /*!< [2..2] Half-Duplex support                                                */
+            __IM uint32_t EXTHASHEN    : 1; /*!< [3..3] Expanded DA Hash Filter                                            */
+            __IM uint32_t HASHSEL      : 1; /*!< [4..4] HASH Filter                                                        */
+            __IM uint32_t ADDMACADRSEL : 1; /*!< [5..5] Multiple MAC Address Registers                                     */
+            uint32_t                   : 1;
+            __IM uint32_t L3L4FLTREN   : 1; /*!< [7..7] Layer 3 and Layer 4 Filter Feature                                 */
+            __IM uint32_t SMASEL       : 1; /*!< [8..8] SMA (MDIO) Interface                                               */
+            __IM uint32_t RWKSEL       : 1; /*!< [9..9] PMT Remote wakeup                                                  */
+            __IM uint32_t MGKSEL       : 1; /*!< [10..10] PMT Magic Packet                                                 */
+            __IM uint32_t MMCSEL       : 1; /*!< [11..11] RMON Module                                                      */
+            __IM uint32_t TSVER1SEL    : 1; /*!< [12..12] Only IEEE 1588-2002 Timestamp                                    */
+            __IM uint32_t TSVER2SEL    : 1; /*!< [13..13] IEEE 1588-2008 Advanced Timestamp                                */
+            __IM uint32_t EEESEL       : 1; /*!< [14..14] Energy Efficient Ethernet                                        */
+            __IM uint32_t AVSEL        : 1; /*!< [15..15] AV Feature                                                       */
+            __IM uint32_t TXCOESEL     : 1; /*!< [16..16] Checksum Offload in TX                                           */
+            __IM uint32_t RXTYP1COE    : 1; /*!< [17..17] IP Checksum Offload (Type 1) in RX                               */
+            __IM uint32_t RXTYP2COE    : 1; /*!< [18..18] IP Checksum Offload (Type 2) in RX                               */
+            __IM uint32_t RXFIFOSIZE   : 1; /*!< [19..19] RX FIFO > 2,048 Bytes                                            */
+            __IM uint32_t RXCHCNT      : 2; /*!< [21..20] Number of additional RX channels                                 */
+            __IM uint32_t TXCHCNT      : 2; /*!< [23..22] Number of additional TX channels                                 */
+            __IM uint32_t ENHDESSEL    : 1; /*!< [24..24] Enhanced Descriptor                                              */
+            __IM uint32_t INTTSEN      : 1; /*!< [25..25] Timestamping with Internal System Time                           */
+            __IM uint32_t FLEXIPPSEN   : 1; /*!< [26..26] Flexible Pulse-Per-Second Output (GMAC: 0)                       */
+            __IM uint32_t SAVLANINS    : 1; /*!< [27..27] Source Address or VLAN Insertion                                 */
+            __IM uint32_t ACTPHYIF     : 3; /*!< [30..28] Active or Selected PHY interface                                 */
+            uint32_t                   : 1;
+        } HW_Feature_b;
+    };
+} R_GMAC_Type;                              /*!< Size = 4188 (0x105c)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ETHSS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet Subsystem (R_ETHSS)
+ */
+
+typedef struct                         /*!< (@ 0x80110000) R_ETHSS Structure                                          */
+{
+    __IOM uint32_t PRCMD;              /*!< (@ 0x00000000) Ethernet Protect Register                                  */
+    __IM uint32_t  RESERVED;
+
+    union
+    {
+        __IOM uint32_t MODCTRL;         /*!< (@ 0x00000008) Mode Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t SW_MODE : 3; /*!< [2..0] Media I/F connectionSW_MODE[2:0]Media I/FPort 0Port 1Port
+                                         *   2000bETHSW Port 0ETHSW Port 1ETHSW Port 2001bESC Port 0ESC
+                                         *   Port 1GMAC Port010bESC Port 0ESC Port 1ETHSW Port 2011bESC
+                                         *   Port 0ESC Port 1ESC Port 2100bETHSW Port 0ESC Port 1ESC
+                                         *   Port 2101bETHSW Port 0ESC Port 1ETHSW Port 2110b-ETHSW
+                                         *   Port 1ETHSW Port 0111b-ESC Port 1ESC Port 0                             */
+            uint32_t : 29;
+        } MODCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPMCTRL;             /*!< (@ 0x0000000C) PTP Mode Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t PTP_MODE : 1;     /*!< [0..0] Select the unit number of PTP Timer for GMAC and Pulse
+                                              *   Generator (unit 0 - 3)                                                    */
+            uint32_t                    : 15;
+            __IOM uint32_t PTP_PLS_RSTn : 1; /*!< [16..16] Reset control for Pulse Generator (unit 0 - 3)                   */
+            uint32_t                    : 15;
+        } PTPMCTRL_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t PHYLNK;         /*!< (@ 0x00000014) Ethernet PHY Link Mode Register                            */
+
+        struct
+        {
+            __IOM uint32_t SWLINK : 3; /*!< [2..0] Specify the active level of the ETHSW_PHYLINKn signal
+                                        *   using the Ethernet switch interface                                       */
+            uint32_t              : 1;
+            __IOM uint32_t CATLNK : 3; /*!< [6..4] Specify the active level of the ESC_PHYLINKn signal using
+                                        *   the EtherCAT interface                                                    */
+            uint32_t : 25;
+        } PHYLNK_b;
+    };
+    __IM uint32_t RESERVED2[58];
+
+    union
+    {
+        __IOM uint32_t CONVCTRL[3];           /*!< (@ 0x00000100) RGMII/RMII Converter [0..2] Control Register               */
+
+        struct
+        {
+            __IOM uint32_t CONV_MODE     : 5; /*!< [4..0] Converter operation mode                                           */
+            uint32_t                     : 3;
+            __IOM uint32_t FULLD         : 1; /*!< [8..8] FULLD                                                              */
+            __IOM uint32_t RMII_RX_ER_EN : 1; /*!< [9..9] RMII_RX_ER_EN                                                      */
+            __IOM uint32_t RMII_CRS_MODE : 1; /*!< [10..10] RMII_CRS_MODE                                                    */
+            uint32_t                     : 1;
+            __IM uint32_t RGMII_LINK     : 1; /*!< [12..12] RGMII_LINK                                                       */
+            __IM uint32_t RGMII_DUPLEX   : 1; /*!< [13..13] RGMII_DUPLEX                                                     */
+            __IM uint32_t RGMII_SPEED    : 2; /*!< [15..14] RGMII_SPEED                                                      */
+            uint32_t                     : 16;
+        } CONVCTRL_b[3];
+    };
+    __IM uint32_t RESERVED3[2];
+
+    union
+    {
+        __IOM uint32_t CONVRST;        /*!< (@ 0x00000114) RGMII/RMII Converter Reset Control Register                */
+
+        struct
+        {
+            __IOM uint32_t PHYIR : 3;  /*!< [2..0] PHYIR                                                              */
+            uint32_t             : 29;
+        } CONVRST_b;
+    };
+    __IM uint32_t RESERVED4[123];
+
+    union
+    {
+        __IOM uint32_t SWCTRL;                /*!< (@ 0x00000304) Switch Core Control Register                               */
+
+        struct
+        {
+            __IOM uint32_t SET10 : 3;         /*!< [2..0] Port control to select use of 10 Mbps. Bit 0 = port 0,
+                                               *   bit 1 = port 1, bit 2 = port 2.                                           */
+            uint32_t               : 1;
+            __IOM uint32_t SET1000 : 3;       /*!< [6..4] Port control to select use of 1000 Mbps. Bit 0 = port
+                                               *   0, bit 1 = port 1, bit 2 = port 2.                                        */
+            uint32_t                    : 9;
+            __IOM uint32_t STRAP_SX_ENB : 1;  /*!< [16..16] Initialize switch after reset (set during module reset
+                                               *   of ETHSW)                                                                 */
+            __IOM uint32_t STRAP_HUB_ENB : 1; /*!< [17..17] Initialize switch port 0 and 1 (set during module reset
+                                               *   of ETHSW)                                                                 */
+            uint32_t : 14;
+        } SWCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWDUPC;             /*!< (@ 0x00000308) Switch Core Duplex Mode Register                           */
+
+        struct
+        {
+            __IOM uint32_t PHY_DUPLEX : 3; /*!< [2..0] Configure the MAC of each port for full-duplex or half-duplex
+                                            *   operation. Bit 0 = port 0, bit 1 = port 1, bit 2 = port
+                                            *   2.                                                                        */
+            uint32_t : 29;
+        } SWDUPC_b;
+    };
+    __IM uint32_t RESERVED5[573];
+
+    union
+    {
+        __IOM uint32_t CDCR;             /*!< (@ 0x00000C00) RGMII Clock Delay Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t RXDLYEN  : 1; /*!< [0..0] Enable delay for ETH2_RXCLK                                        */
+            __IOM uint32_t TXDLYEN  : 1; /*!< [1..1] Enable delay for ETH2_TXCLK                                        */
+            __IOM uint32_t OSCCLKEN : 1; /*!< [2..2] Enable Oscillation mode for calibration                            */
+            __IOM uint32_t CLKINEN  : 1; /*!< [3..3] Enable Phase shift mode for normal operation                       */
+            uint32_t                : 28;
+        } CDCR_b;
+    };
+    __IM uint32_t RESERVED6[3];
+
+    union
+    {
+        __IM uint32_t RXFCNT;          /*!< (@ 0x00000C10) RGMII RX OSC Frequency Measurement Counter Register        */
+
+        struct
+        {
+            __IM uint32_t RXFCNT : 16; /*!< [15..0] Oscillation frequency measurement counter for ETH2_RXCLK
+                                        *   delay                                                                     */
+            uint32_t : 16;
+        } RXFCNT_b;
+    };
+
+    union
+    {
+        __IM uint32_t TXFCNT;          /*!< (@ 0x00000C14) RGMII TX OSC Frequency Measurement Counter Register        */
+
+        struct
+        {
+            __IM uint32_t TXFCNT : 16; /*!< [15..0] Oscillation frequency measurement counter for ETH2_TXCLK
+                                        *   delay                                                                     */
+            uint32_t : 16;
+        } TXFCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RXTAPSEL;         /*!< (@ 0x00000C18) RGMII RX TAP Selection Register                            */
+
+        struct
+        {
+            __IOM uint32_t RXTAPSEL : 7; /*!< [6..0] TAP selection for ETH2_RXCLK delay (number of taps for
+                                          *   90 degree phase shift)                                                    */
+            uint32_t : 25;
+        } RXTAPSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TXTAPSEL;         /*!< (@ 0x00000C1C) RGMII TX TAP Selection Register                            */
+
+        struct
+        {
+            __IOM uint32_t TXTAPSEL : 7; /*!< [6..0] TAP selection for ETH2_TXCLK delay (Number of taps for
+                                          *   90 degree phase shift)                                                    */
+            uint32_t : 25;
+        } TXTAPSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIIMCR;           /*!< (@ 0x00000C20) MII Mode Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t MIIM2MEN : 1; /*!< [0..0] Enable MAC-to-MAC MII Mode                                         */
+            uint32_t                : 31;
+        } MIIMCR_b;
+    };
+} R_ETHSS_Type;                          /*!< Size = 3108 (0xc24)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ESC_INI                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Initial Configuration 1 for EtherCAT Slave Controller (R_ESC_INI)
+ */
+
+typedef struct                         /*!< (@ 0x80110200) R_ESC_INI Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t ECATOFFADR;     /*!< (@ 0x00000000) EtherCAT PHY Offset Address Setting Register               */
+
+        struct
+        {
+            __IOM uint32_t OADD : 5;   /*!< [4..0] PHY Offset Address Setting                                         */
+            uint32_t            : 27;
+        } ECATOFFADR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ECATOPMOD;          /*!< (@ 0x00000004) EtherCAT Operation Mode Register                           */
+
+        struct
+        {
+            __IOM uint32_t EEPROMSIZE : 1; /*!< [0..0] EEPROM Memory Size Specification                                   */
+            uint32_t                  : 31;
+        } ECATOPMOD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ECATDBGC;       /*!< (@ 0x00000008) EtherCAT Debug Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t TXSFT0 : 2; /*!< [1..0] Set the delay time for ETH0_TXEN and ETH0_TXDn of the
+                                        *   EtherCAT                                                                  */
+            __IOM uint32_t TXSFT1 : 2; /*!< [3..2] Set the delay time for ETH1_TXEN and ETH1_TXDn of the
+                                        *   EtherCAT                                                                  */
+            __IOM uint32_t TXSFT2 : 2; /*!< [5..4] Set the delay time for ETH2_TXEN and ETH2_TXDn of the
+                                        *   EtherCAT                                                                  */
+            uint32_t : 26;
+        } ECATDBGC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ECATTRGSEL;      /*!< (@ 0x0000000C) EtherCAT DC Latch Trigger Select Register                  */
+
+        struct
+        {
+            __IOM uint32_t TRGSEL0 : 1; /*!< [0..0] Select DC Latch Trigger 0 for ESC                                  */
+            __IOM uint32_t TRGSEL1 : 1; /*!< [1..1] Select DC Latch Trigger 1 for ESC                                  */
+            uint32_t               : 30;
+        } ECATTRGSEL_b;
+    };
+} R_ESC_INI_Type;                       /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_ETHSW_PTP                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet Switch for PTP (R_ETHSW_PTP)
+ */
+
+typedef struct                         /*!< (@ 0x80110400) R_ETHSW_PTP Structure                                      */
+{
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t SWPTPOUTSEL;     /*!< (@ 0x00000004) ETHSW_PTPOUT Select Register                               */
+
+        struct
+        {
+            __IOM uint32_t IOSEL0  : 1; /*!< [0..0] Select the source of the ETHSW_PTPOUT0 output signal               */
+            __IOM uint32_t IOSEL1  : 1; /*!< [1..1] Select the source of the ETHSW_PTPOUT1 output signal               */
+            __IOM uint32_t IOSEL2  : 1; /*!< [2..2] Select the source of the ETHSW_PTPOUT2 output signal               */
+            __IOM uint32_t IOSEL3  : 1; /*!< [3..3] Select the source of the ETHSW_PTPOUT3 output signal               */
+            __IOM uint32_t EVTSEL0 : 1; /*!< [4..4] Select the source of the ETHSW_PTPOUT0 event for GIC,
+                                         *   DMAC, and ELC                                                             */
+            __IOM uint32_t EVTSEL1 : 1; /*!< [5..5] Select the source of the ETHSW_PTPOUT1 event for GIC,
+                                         *   DMAC, and ELC                                                             */
+            __IOM uint32_t EVTSEL2 : 1; /*!< [6..6] Select the source of the ETHSW_PTPOUT2 event for GIC,
+                                         *   DMAC, and ELC                                                             */
+            __IOM uint32_t EVTSEL3 : 1; /*!< [7..7] Select the source of the ETHSW_PTPOUT3 event for GIC,
+                                         *   DMAC, and ELC                                                             */
+            uint32_t : 24;
+        } SWPTPOUTSEL_b;
+    };
+    __IM uint32_t               RESERVED1[254];
+    __IOM R_ETHSW_PTP_SWTM_Type SWTM[4]; /*!< (@ 0x00000400) Ethernet Switch Timer output pins 0-3 Registers            */
+} R_ETHSW_PTP_Type;                      /*!< Size = 2048 (0x800)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ETHSW                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet Switch (R_ETHSW)
+ */
+
+typedef struct                         /*!< (@ 0x80120000) R_ETHSW Structure                                          */
+{
+    union
+    {
+        __IM uint32_t REVISION;        /*!< (@ 0x00000000) Switch Core Version Register                               */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] Revision                                                          */
+        } REVISION_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCRATCH;          /*!< (@ 0x00000004) Scratch Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SCRATCH : 32; /*!< [31..0] The Scratch Register provides a memory location to test
+                                          *   the register access.                                                      */
+        } SCRATCH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PORT_ENA;       /*!< (@ 0x00000008) Port Enable Register                                       */
+
+        struct
+        {
+            __IOM uint32_t TXENA : 4;  /*!< [3..0] Transmit Enable Mask                                               */
+            uint32_t             : 12;
+            __IOM uint32_t RXENA : 4;  /*!< [19..16] Receive Enable Mask                                              */
+            uint32_t             : 12;
+        } PORT_ENA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t UCAST_DEFAULT_MASK0; /*!< (@ 0x0000000C) Unicast Default Mask Register 0                            */
+
+        struct
+        {
+            __IOM uint32_t UCASTDM : 4;     /*!< [3..0] Default Unicast Resolution                                         */
+            uint32_t               : 28;
+        } UCAST_DEFAULT_MASK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_VERIFY;      /*!< (@ 0x00000010) Verify VLAN Domain Register                                */
+
+        struct
+        {
+            __IOM uint32_t VLANVERI : 4; /*!< [3..0] Verify VLAN Domain                                                 */
+            uint32_t                : 12;
+            __IOM uint32_t VLANDISC : 4; /*!< [19..16] Discard Unknown                                                  */
+            uint32_t                : 12;
+        } VLAN_VERIFY_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCAST_DEFAULT_MASK0; /*!< (@ 0x00000014) Broadcast Default Mask Register 0                          */
+
+        struct
+        {
+            __IOM uint32_t BCASTDM : 4;     /*!< [3..0] Default Broadcast Resolution                                       */
+            uint32_t               : 28;
+        } BCAST_DEFAULT_MASK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MCAST_DEFAULT_MASK0; /*!< (@ 0x00000018) Multicast Default Mask Register 0                          */
+
+        struct
+        {
+            __IOM uint32_t MCASTDM : 4;     /*!< [3..0] Default Multicast Resolution                                       */
+            uint32_t               : 28;
+        } MCAST_DEFAULT_MASK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INPUT_LEARN_BLOCK; /*!< (@ 0x0000001C) Input Learning Block Register                              */
+
+        struct
+        {
+            __IOM uint32_t BLOCKEN  : 4;  /*!< [3..0] Blocking Enable                                                    */
+            uint32_t                : 12;
+            __IOM uint32_t LEARNDIS : 4;  /*!< [19..16] Learning Disable                                                 */
+            uint32_t                : 12;
+        } INPUT_LEARN_BLOCK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MGMT_CONFIG;       /*!< (@ 0x00000020) Management Configuration Register                          */
+
+        struct
+        {
+            __IOM uint32_t PORT : 4;      /*!< [3..0] The Port number of the port that should act as a management
+                                           *   port. Keep the initial value.                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t MSG_TRANS : 1; /*!< [5..5] Set (latched) when a BPDU message is transmitted from
+                                           *   the management port to any output port. This bit can be
+                                           *   used for handshaking to indicate that the port mask bits
+                                           *   are used and can now be changed again by setting it to
+                                           *   0.                                                                        */
+            __IOM uint32_t ENABLE : 1;    /*!< [6..6] If set, all Bridge Protocol Frames (BPDU) are forwarded
+                                           *   exclusively to the management port specified in bits [3:0].               */
+            __IOM uint32_t DISCARD : 1;   /*!< [7..7] If set, BPDU frames are discarded always.                          */
+            __IOM uint32_t MGMT_EN : 1;   /*!< [8..8] If set, BPDU frames received at the management port are
+                                           *   forwarded to the ports given in the portmask given in this
+                                           *   register, bypassing the normal forwarding decisions (except
+                                           *   forced forwarding).                                                       */
+            __IOM uint32_t MGMT_DISC : 1; /*!< [9..9] This bit is the same as DISCARD (bit 7) but for the management
+                                           *   port.                                                                     */
+            uint32_t                : 3;
+            __IOM uint32_t PRIORITY : 3;  /*!< [15..13] Priority to use for transmitted BPDU frames if non-zero.         */
+            __IOM uint32_t PORTMASK : 4;  /*!< [19..16] Portmask for transmission of management frames. When
+                                           *   the management port transmits a frame to the switch, it
+                                           *   is forwarded to all ports in this portmask (bit 16 = port
+                                           *   0, bit 17 = port 1, ..., bit 19 = port 3).                                */
+            uint32_t : 12;
+        } MGMT_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MODE_CONFIG;    /*!< (@ 0x00000024) Mode Configuration Register                                */
+
+        struct
+        {
+            uint32_t                   : 8;
+            __IOM uint32_t CUT_THRU_EN : 4; /*!< [11..8] Port Cut through Support Enable                                   */
+            uint32_t                   : 19;
+            __IOM uint32_t STATSRESET  : 1; /*!< [31..31] Reset Statistics Counters Command.                               */
+        } MODE_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_IN_MODE;       /*!< (@ 0x00000028) VLAN Input Manipulation Mode Register                      */
+
+        struct
+        {
+            __IOM uint32_t P0VLANINMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Input Manipulation Function         */
+            __IOM uint32_t P1VLANINMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Input Manipulation Function         */
+            __IOM uint32_t P2VLANINMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Input Manipulation Function         */
+            __IOM uint32_t P3VLANINMD : 2; /*!< [7..6] Port3 Define Behavior of VLAN Input Manipulation Function          */
+            uint32_t                  : 24;
+        } VLAN_IN_MODE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_OUT_MODE;       /*!< (@ 0x0000002C) VLAN Output Manipulation Mode Register                     */
+
+        struct
+        {
+            __IOM uint32_t P0VLANOUTMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Output Manipulation Function        */
+            __IOM uint32_t P1VLANOUTMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Output Manipulation Function        */
+            __IOM uint32_t P2VLANOUTMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Output Manipulation Function        */
+            __IOM uint32_t P3VLANOUTMD : 2; /*!< [7..6] Port 3 Define Behavior of VLAN Output Manipulation Function        */
+            uint32_t                   : 24;
+        } VLAN_OUT_MODE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_IN_MODE_ENA;   /*!< (@ 0x00000030) VLAN Input Mode Enable Register                            */
+
+        struct
+        {
+            __IOM uint32_t VLANINMDEN : 4; /*!< [3..0] Enable the input processing according to the VLAN_IN_MODE
+                                            *   for a port (1 bit per port).                                              */
+            uint32_t : 28;
+        } VLAN_IN_MODE_ENA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_TAG_ID;        /*!< (@ 0x00000034) VLAN Tag ID Register                                       */
+
+        struct
+        {
+            __IOM uint32_t VLANTAGID : 16; /*!< [15..0] The VLAN type field (TPID) value to expect to identify
+                                            *   a VLAN tagged frame.                                                      */
+            uint32_t : 16;
+        } VLAN_TAG_ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCAST_STORM_LIMIT;   /*!< (@ 0x00000038) Broadcast Storm Protection Register                        */
+
+        struct
+        {
+            __IOM uint32_t TMOUT      : 16; /*!< [15..0] Timeout in steps of 65535 switch operating clock cycles.          */
+            __IOM uint32_t BCASTLIMIT : 16; /*!< [31..16] Number of broadcast frames (-1) that can be accepted
+                                             *   on a port during a timeout period. If more are received,
+                                             *   they are discarded. The counter is implemented per port
+                                             *   independently. However, the limit is used for all ports.                  */
+        } BCAST_STORM_LIMIT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MCAST_STORM_LIMIT; /*!< (@ 0x0000003C) Multicast Storm Protection Register                        */
+
+        struct
+        {
+            uint32_t                  : 16;
+            __IOM uint32_t MCASTLIMIT : 16; /*!< [31..16] Number of multicast frames (-1) that can be accepted
+                                             *   on a port during a timeout period. If more are received,
+                                             *   they are discarded. The counter is implemented per port
+                                             *   independently. However, the limit is used for all ports.                  */
+        } MCAST_STORM_LIMIT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_CONTROL;       /*!< (@ 0x00000040) Port Mirroring Configuration Register                      */
+
+        struct
+        {
+            __IOM uint32_t PORT : 2;         /*!< [1..0] The port number of the port that acts as the mirror port
+                                              *   and receives all mirrored frames. Valid setting range is
+                                              *   0 to 3.                                                                   */
+            uint32_t                    : 2;
+            __IOM uint32_t MIRROR_EN    : 1; /*!< [4..4] MIRROR_EN                                                          */
+            __IOM uint32_t ING_MAP_EN   : 1; /*!< [5..5] If set, the ingress map is enabled (MIRROR_ING_MAP).               */
+            __IOM uint32_t EG_MAP_EN    : 1; /*!< [6..6] If set, the egress map is enabled (MIRROR_EG_MAP).                 */
+            __IOM uint32_t ING_SA_MATCH : 1; /*!< [7..7] If set, only frames received on an ingress port with
+                                              *   a source address matching the value programmed in MIRROR_ISRC
+                                              *   registers are mirrored. Other frames are not mirrored.                    */
+            __IOM uint32_t ING_DA_MATCH : 1; /*!< [8..8] If set, only frames received on an ingress port with
+                                              *   a destination address matching the value programmed in
+                                              *   MIRROR_IDST registers are mirrored. Other frames are not
+                                              *   mirrored.                                                                 */
+            __IOM uint32_t EG_SA_MATCH : 1;  /*!< [9..9] If set, only frames transmitted on an egress port with
+                                              *   a source address matching the value programmed in MIRROR_ESRC
+                                              *   registers are mirrored. Other frames are not mirrored.                    */
+            __IOM uint32_t EG_DA_MATCH : 1;  /*!< [10..10] If set, only frames transmitted on an egress port with
+                                              *   a destination address matching the value programmed in
+                                              *   MIRROR_EDST registers are mirrored. Other frames are not
+                                              *   mirrored.                                                                 */
+            uint32_t : 21;
+        } MIRROR_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_EG_MAP;  /*!< (@ 0x00000044) Port Mirroring Egress Port Definition Register             */
+
+        struct
+        {
+            __IOM uint32_t EMAP : 4;   /*!< [3..0] Port Mirroring Egress Port Definitions                             */
+            uint32_t            : 28;
+        } MIRROR_EG_MAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ING_MAP; /*!< (@ 0x00000048) Port Mirroring Ingress Port Definition Register            */
+
+        struct
+        {
+            __IOM uint32_t IMAP : 4;   /*!< [3..0] Port Mirroring Ingress Port Definitions                            */
+            uint32_t            : 28;
+        } MIRROR_ING_MAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ISRC_0;  /*!< (@ 0x0000004C) Ingress Source MAC Address for Mirror Filtering
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t ISRC : 32;  /*!< [31..0] Ingress Source MAC Address for Mirror Filtering                   */
+        } MIRROR_ISRC_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ISRC_1;  /*!< (@ 0x00000050) Ingress Source MAC Address for Mirror Filtering
+                                        *                  Register 1                                                 */
+
+        struct
+        {
+            __IOM uint32_t ISRC : 16;  /*!< [15..0] Ingress Source MAC Address for Mirror Filtering                   */
+            uint32_t            : 16;
+        } MIRROR_ISRC_1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_IDST_0;  /*!< (@ 0x00000054) Ingress Destination MAC Address for Mirror Filtering
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t IDST : 32;  /*!< [31..0] Ingress Destination MAC Address for Mirror Filtering              */
+        } MIRROR_IDST_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_IDST_1;  /*!< (@ 0x00000058) Ingress Destination MAC Address for Mirror Filtering
+                                        *                  Register 1                                                 */
+
+        struct
+        {
+            __IOM uint32_t IDST : 16;  /*!< [15..0] Ingress Destination MAC Address for Mirror Filtering              */
+            uint32_t            : 16;
+        } MIRROR_IDST_1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ESRC_0;  /*!< (@ 0x0000005C) Egress Source MAC Address for Mirror Filtering
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t ESRC : 32;  /*!< [31..0] Egress Source MAC Address for Mirror Filtering                    */
+        } MIRROR_ESRC_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ESRC_1;  /*!< (@ 0x00000060) Egress Source MAC Address for Mirror Filtering
+                                        *                  Register 1                                                 */
+
+        struct
+        {
+            __IOM uint32_t ESRC : 16;  /*!< [15..0] Egress Source MAC Address for Mirror Filtering                    */
+            uint32_t            : 16;
+        } MIRROR_ESRC_1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_EDST_0;  /*!< (@ 0x00000064) Egress Destination MAC Address for Mirror Filtering
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t EDST : 32;  /*!< [31..0] Egress Destination MAC Address for Mirror Filtering               */
+        } MIRROR_EDST_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_EDST_1;  /*!< (@ 0x00000068) Egress Destination MAC Address for Mirror Filtering
+                                        *                  Register 1                                                 */
+
+        struct
+        {
+            __IOM uint32_t EDST : 16;  /*!< [15..0] Egress Destination MAC Address for Mirror Filtering               */
+            uint32_t            : 16;
+        } MIRROR_EDST_1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_CNT;     /*!< (@ 0x0000006C) Mirror Filtering Count Value Register                      */
+
+        struct
+        {
+            __IOM uint32_t CNT : 8;    /*!< [7..0] Count Value for Mirror Filtering                                   */
+            uint32_t           : 24;
+        } MIRROR_CNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t UCAST_DEFAULT_MASK1; /*!< (@ 0x00000070) Unicast Default Mask Register 1                            */
+
+        struct
+        {
+            __IOM uint32_t UCASTDM1 : 4;    /*!< [3..0] Default Unicast Resolution Mask 1                                  */
+            uint32_t                : 28;
+        } UCAST_DEFAULT_MASK1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCAST_DEFAULT_MASK1; /*!< (@ 0x00000074) Broadcast Default Mask Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t BCASTDM1 : 4;    /*!< [3..0] Default Broadcast Resolution Mask 1                                */
+            uint32_t                : 28;
+        } BCAST_DEFAULT_MASK1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MCAST_DEFAULT_MASK1; /*!< (@ 0x00000078) Multicast Default Mask Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t MCASTDM1 : 4;    /*!< [3..0] Default Multicast Resolution Mask 1                                */
+            uint32_t                : 28;
+        } MCAST_DEFAULT_MASK1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PORT_XCAST_MASK_SEL; /*!< (@ 0x0000007C) Port Mask Select Register                                  */
+
+        struct
+        {
+            __IOM uint32_t MSEL : 4;        /*!< [3..0] Mask Select                                                        */
+            uint32_t            : 28;
+        } PORT_XCAST_MASK_SEL_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t QMGR_ST_MINCELLS;    /*!< (@ 0x00000088) Minimum Memory Cell Statistics Register                    */
+
+        struct
+        {
+            __IOM uint32_t STMINCELLS : 11; /*!< [10..0] Minimum Free Cell Indication                                      */
+            uint32_t                  : 21;
+        } QMGR_ST_MINCELLS_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t QMGR_RED_MIN4;          /*!< (@ 0x00000094) RED Minimum Threshold Register                             */
+
+        struct
+        {
+            __IOM uint32_t CFGRED_MINTH4 : 32; /*!< [31..0] Random Early Detection (RED) Minimum Threshold for Queues
+                                                *   0 to 3                                                                    */
+        } QMGR_RED_MIN4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t QMGR_RED_MAX4;          /*!< (@ 0x00000098) RED Maximum Threshold Register                             */
+
+        struct
+        {
+            __IOM uint32_t CFGRED_MAXTH4 : 32; /*!< [31..0] Random Early Detection (RED) Maximum Threshold for Queues
+                                                *   0 to 3                                                                    */
+        } QMGR_RED_MAX4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t QMGR_RED_CONFIG;      /*!< (@ 0x0000009C) RED Configuration Register                                 */
+
+        struct
+        {
+            __IOM uint32_t QUEUE_RED_EN : 4; /*!< [3..0] Enable Random Early Detection (RED) (when this bit is
+                                              *   1) or Tail Drop (when this bit is 0) congestion management
+                                              *   for a queue.                                                              */
+            uint32_t                    : 4;
+            __IOM uint32_t GACTIVITY_EN : 1; /*!< [8..8] Enable Averaging on Global Switch Activity (when this
+                                              *   bit is 1) or on port local activity (when this bit is 0)
+                                              *   only.                                                                     */
+            uint32_t : 23;
+        } QMGR_RED_CONFIG_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_STATUS;               /*!< (@ 0x000000A0) Input Memory Controller Status Register                    */
+
+        struct
+        {
+            __IM uint32_t CELLS_AVAILABLE : 24; /*!< [23..0] Total number of memory cells (128-byte units) available
+                                                 *   in the shared memory (real time).                                         */
+            __IM uint32_t CF_ERR  : 1;          /*!< [24..24] Cell Factory Empty Error                                         */
+            __IM uint32_t DE_ERR  : 1;          /*!< [25..25] Deallocation Error                                               */
+            __IM uint32_t DE_INIT : 1;          /*!< [26..26] Asserts during Memory Initialization (deallocation
+                                                 *   module)                                                                   */
+            __IM uint32_t MEM_FULL : 1;         /*!< [27..27] Latched Indication that Memory is or was Full                    */
+            uint32_t               : 4;
+        } IMC_STATUS_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_ERR_FULL;          /*!< (@ 0x000000A4) Input Port Memory Full and Truncation Indicator
+                                              *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IPC_ERR_FULL  : 4; /*!< [3..0] Memory was full at start of a frame reception.                     */
+            uint32_t                    : 12;
+            __IM uint32_t IPC_ERR_TRUNC : 4; /*!< [19..16] Memory became full while a frame was received and was
+                                              *   partly written into memory.                                               */
+            uint32_t : 12;
+        } IMC_ERR_FULL_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_ERR_IFACE;         /*!< (@ 0x000000A8) Input Port Memory Error Indicator Register                 */
+
+        struct
+        {
+            __IM uint32_t IPC_ERR_IFACE : 4; /*!< [3..0] Error indication on memory input (receive from MAC) that
+                                              *   a frame has been truncated and discarded.                                 */
+            uint32_t               : 12;
+            __IM uint32_t WBUF_OVF : 4;      /*!< [19..16] Error indicating an overflow in the input write buffer
+                                              *   to the memory controller (a small decoupling FIFO at every
+                                              *   MAC RX).                                                                  */
+            uint32_t : 12;
+        } IMC_ERR_IFACE_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_ERR_QOFLOW;  /*!< (@ 0x000000AC) Output Port Queue Overflow Indicator Register              */
+
+        struct
+        {
+            __IM uint32_t OP_ERR : 4;  /*!< [3..0] A frame cannot be stored in an output queue of the port
+                                        *   as the queue FIFO overflowed (write occurred into full
+                                        *   fifo). The frame is ignored but stays stored in memory.
+                                        *   This should not occur during normal operation. This is
+                                        *   a fatal error as the memory allocated by that frame is
+                                        *   not freed, and resulting in memory leakage.                               */
+            uint32_t : 28;
+        } IMC_ERR_QOFLOW_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IMC_CONFIG;              /*!< (@ 0x000000B0) Input Memory Controller Configuration Register             */
+
+        struct
+        {
+            __IOM uint32_t WFQ_EN : 1;          /*!< [0..0] Enable weighted fair queuing (when this bit is 1) or
+                                                 *   strict priority (when this bit is 0, default) output queue
+                                                 *   scheduling.                                                               */
+            __IOM uint32_t RSV_ENA         : 1; /*!< [1..1] Enable Memory Reservations to Operate                              */
+            __IOM uint32_t SPEED_HIPRI_THR : 3; /*!< [4..2] High-Priority Speed Threshold                                      */
+            __IOM uint32_t CTFL_EMPTY_MD   : 1; /*!< [5..5] When this bit is set to 0, a frame received in Cut-Through
+                                                 *   mode that cannot allocate an entry in the CTFL is forwarded
+                                                 *   as store and forward.                                                     */
+            uint32_t : 26;
+        } IMC_CONFIG_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_ERR_ALLOC;     /*!< (@ 0x000000B4) Input Port Error Indicator Register                        */
+
+        struct
+        {
+            __IM uint32_t DISC_FULL : 4; /*!< [3..0] Per port discard indication due to memory pool going
+                                          *   empty. Per port indication that one of the queues was full
+                                          *   and a frame was discarded.                                                */
+            uint32_t                : 12;
+            __IM uint32_t DISC_LATE : 4; /*!< [19..16] Per port discard indication due to lateness in the
+                                          *   priority resolution. The priority resolution can be delayed
+                                          *   by the pattern matchers. If it arrives too late (after
+                                          *   approximately 100 bytes into the frame), the frame is discarded.          */
+            uint32_t : 12;
+        } IMC_ERR_ALLOC_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t GPARSER0;             /*!< (@ 0x000000C0) [n + 1]th Parser of 1st Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask will be compared with the data in the frame.
+                                              *   All bits having a 0 will be 0 for the compare, however
+                                              *   this requires the compare value to have those bits also
+                                              *   set to 0.                                                                 */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type/length field of the frame, that
+                                              *   is, 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see IPDATA). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field found within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored.                                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
+                                              *   the given offset and MASK_VAL2[7:0] represent the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields. For example, setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames. No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
+                                              *   When set, the parser reports a match if the byte at given
+                                              *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
+            uint32_t : 1;
+        } GPARSER0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER1;             /*!< (@ 0x000000C4) [n + 1]th Parser of 1st Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask will be compared with the data in the frame.
+                                              *   All bits having a 0 will be 0 for the compare, however
+                                              *   this requires the compare value to have those bits also
+                                              *   set to 0.                                                                 */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type/length field of the frame, that
+                                              *   is, 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see IPDATA). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field found within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored.                                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
+                                              *   the given offset and MASK_VAL2[7:0] represent the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields. For example, setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames. No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
+                                              *   When set, the parser reports a match if the byte at given
+                                              *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
+            uint32_t : 1;
+        } GPARSER1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER2;             /*!< (@ 0x000000C8) [n + 1]th Parser of 1st Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask will be compared with the data in the frame.
+                                              *   All bits having a 0 will be 0 for the compare, however
+                                              *   this requires the compare value to have those bits also
+                                              *   set to 0.                                                                 */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type/length field of the frame, that
+                                              *   is, 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see IPDATA). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field found within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored.                                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
+                                              *   the given offset and MASK_VAL2[7:0] represent the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields. For example, setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames. No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
+                                              *   When set, the parser reports a match if the byte at given
+                                              *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
+            uint32_t : 1;
+        } GPARSER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER3;             /*!< (@ 0x000000CC) [n + 1]th Parser of 1st Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask will be compared with the data in the frame.
+                                              *   All bits having a 0 will be 0 for the compare, however
+                                              *   this requires the compare value to have those bits also
+                                              *   set to 0.                                                                 */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type/length field of the frame, that
+                                              *   is, 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see IPDATA). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field found within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored.                                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
+                                              *   the given offset and MASK_VAL2[7:0] represent the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields. For example, setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames. No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
+                                              *   When set, the parser reports a match if the byte at given
+                                              *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
+            uint32_t : 1;
+        } GPARSER3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH0;            /*!< (@ 0x000000D0) Snoop Configuration for Arithmetic [n + 1]th
+                                            *                  Stage of 1st Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH1;            /*!< (@ 0x000000D4) Snoop Configuration for Arithmetic [n + 1]th
+                                            *                  Stage of 1st Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH2;            /*!< (@ 0x000000D8) Snoop Configuration for Arithmetic [n + 1]th
+                                            *                  Stage of 1st Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH3;            /*!< (@ 0x000000DC) Snoop Configuration for Arithmetic [n + 1]th
+                                            *                  Stage of 1st Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER4;             /*!< (@ 0x000000E0) [n - 3]th Parser of 2nd Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask are compared with the data in the frame. All
+                                              *   bits having a 0 will be 0 for the compare, however this
+                                              *   requires the compare value to have those bits also set
+                                              *   to 0.                                                                     */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type or length field of the frame, for
+                                              *   example 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see bit 26). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field located within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored. If the bit is set, but the frame is not
+                                              *   an IPv4/v6 frame the parser reports a no match and does
+                                              *   not continue to inspect the frame. When cleared, the offset
+                                              *   is used normally on all frames.                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
+                                              *   at the given offset and MASK_VAL2[7:0] represents the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields, (for example setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames). No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
+                                              *   set, the parser reports a match if the byte at given offset
+                                              *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
+            uint32_t : 1;
+        } GPARSER4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER5;             /*!< (@ 0x000000E4) [n - 3]th Parser of 2nd Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask are compared with the data in the frame. All
+                                              *   bits having a 0 will be 0 for the compare, however this
+                                              *   requires the compare value to have those bits also set
+                                              *   to 0.                                                                     */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type or length field of the frame, for
+                                              *   example 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see bit 26). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field located within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored. If the bit is set, but the frame is not
+                                              *   an IPv4/v6 frame the parser reports a no match and does
+                                              *   not continue to inspect the frame. When cleared, the offset
+                                              *   is used normally on all frames.                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
+                                              *   at the given offset and MASK_VAL2[7:0] represents the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields, (for example setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames). No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
+                                              *   set, the parser reports a match if the byte at given offset
+                                              *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
+            uint32_t : 1;
+        } GPARSER5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER6;             /*!< (@ 0x000000E8) [n - 3]th Parser of 2nd Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask are compared with the data in the frame. All
+                                              *   bits having a 0 will be 0 for the compare, however this
+                                              *   requires the compare value to have those bits also set
+                                              *   to 0.                                                                     */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type or length field of the frame, for
+                                              *   example 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see bit 26). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field located within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored. If the bit is set, but the frame is not
+                                              *   an IPv4/v6 frame the parser reports a no match and does
+                                              *   not continue to inspect the frame. When cleared, the offset
+                                              *   is used normally on all frames.                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
+                                              *   at the given offset and MASK_VAL2[7:0] represents the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields, (for example setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames). No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
+                                              *   set, the parser reports a match if the byte at given offset
+                                              *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
+            uint32_t : 1;
+        } GPARSER6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER7;             /*!< (@ 0x000000EC) [n - 3]th Parser of 2nd Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask are compared with the data in the frame. All
+                                              *   bits having a 0 will be 0 for the compare, however this
+                                              *   requires the compare value to have those bits also set
+                                              *   to 0.                                                                     */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type or length field of the frame, for
+                                              *   example 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see bit 26). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field located within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored. If the bit is set, but the frame is not
+                                              *   an IPv4/v6 frame the parser reports a no match and does
+                                              *   not continue to inspect the frame. When cleared, the offset
+                                              *   is used normally on all frames.                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
+                                              *   at the given offset and MASK_VAL2[7:0] represents the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields, (for example setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames). No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
+                                              *   set, the parser reports a match if the byte at given offset
+                                              *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
+            uint32_t : 1;
+        } GPARSER7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH4;            /*!< (@ 0x000000F0) Snoop Configuration for Arithmetic [n - 3]th
+                                            *                  Stage of 2nd Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH5;            /*!< (@ 0x000000F4) Snoop Configuration for Arithmetic [n - 3]th
+                                            *                  Stage of 2nd Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH6;            /*!< (@ 0x000000F8) Snoop Configuration for Arithmetic [n - 3]th
+                                            *                  Stage of 2nd Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH7;            /*!< (@ 0x000000FC) Snoop Configuration for Arithmetic [n - 3]th
+                                            *                  Stage of 2nd Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_PRIORITY[4];  /*!< (@ 0x00000100) VLAN Priority Register [0..3]                              */
+
+        struct
+        {
+            __IOM uint32_t PRIORITY0 : 3; /*!< [2..0] Priority 0 Setting                                                 */
+            __IOM uint32_t PRIORITY1 : 3; /*!< [5..3] Priority 1 Setting                                                 */
+            __IOM uint32_t PRIORITY2 : 3; /*!< [8..6] Priority 2 Setting                                                 */
+            __IOM uint32_t PRIORITY3 : 3; /*!< [11..9] Priority 3 Setting                                                */
+            __IOM uint32_t PRIORITY4 : 3; /*!< [14..12] Priority 4 Setting                                               */
+            __IOM uint32_t PRIORITY5 : 3; /*!< [17..15] Priority 5 Setting                                               */
+            __IOM uint32_t PRIORITY6 : 3; /*!< [20..18] Priority 6 Setting                                               */
+            __IOM uint32_t PRIORITY7 : 3; /*!< [23..21] Priority 7 Setting                                               */
+            uint32_t                 : 8;
+        } VLAN_PRIORITY_b[4];
+    };
+    __IM uint32_t RESERVED3[12];
+
+    union
+    {
+        __IOM uint32_t IP_PRIORITY[4];     /*!< (@ 0x00000140) IP Priority Register [0..3]                                */
+
+        struct
+        {
+            __IOM uint32_t ADDRESS    : 8; /*!< [7..0] COS Table Address Specifying                                       */
+            __IOM uint32_t IPV6SELECT : 1; /*!< [8..8] IPv6 COS Table Selection                                           */
+            __IOM uint32_t PRIORITY   : 3; /*!< [11..9] COS Table Priority                                                */
+            uint32_t                  : 19;
+            __IOM uint32_t READ       : 1; /*!< [31..31] COS Table Operation Switching                                    */
+        } IP_PRIORITY_b[4];
+    };
+    __IM uint32_t RESERVED4[12];
+
+    union
+    {
+        __IOM uint32_t PRIORITY_CFG[4];        /*!< (@ 0x00000180) Priority Configuration Register [0..3]                     */
+
+        struct
+        {
+            __IOM uint32_t VLANEN        : 1;  /*!< [0..0] VLAN Priority Enable                                               */
+            __IOM uint32_t IPEN          : 1;  /*!< [1..1] IP Priority Enable                                                 */
+            __IOM uint32_t MACEN         : 1;  /*!< [2..2] MAC Based Priority Enable                                          */
+            __IOM uint32_t TYPE_EN       : 1;  /*!< [3..3] TYPE Based Priority Enable                                         */
+            __IOM uint32_t DEFAULTPRI    : 3;  /*!< [6..4] Default Priority Enable Setting                                    */
+            __IOM uint32_t PCP_REMAP_DIS : 1;  /*!< [7..7] Disables PCP remapping when set to 1.                              */
+            __IOM uint32_t PCP_REMAP     : 24; /*!< [31..8] PCP Remapping function                                            */
+        } PRIORITY_CFG_b[4];
+    };
+    __IM uint32_t RESERVED5[10];
+
+    union
+    {
+        __IOM uint32_t PRIORITY_TYPE1;    /*!< (@ 0x000001B8) Priority Type Register 1                                   */
+
+        struct
+        {
+            __IOM uint32_t TYPEVAL  : 16; /*!< [15..0] Type Priority                                                     */
+            __IOM uint32_t VALID    : 1;  /*!< [16..16] If set indicates, this register contains valid data.             */
+            __IOM uint32_t PRIORITY : 3;  /*!< [19..17] The priority value to use if a match occurs.                     */
+            uint32_t                : 12;
+        } PRIORITY_TYPE1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRIORITY_TYPE2;         /*!< (@ 0x000001BC) Priority Type Register 2                                   */
+
+        struct
+        {
+            __IOM uint32_t TYPEVAL  : 16;      /*!< [15..0] Type Priority                                                     */
+            __IOM uint32_t VALID    : 1;       /*!< [16..16] If set indicates, this register contains valid data.             */
+            __IOM uint32_t PRIORITY : 3;       /*!< [19..17] The priority value to use if a match occurs.                     */
+            uint32_t                : 12;
+        } PRIORITY_TYPE2_b;
+    };
+    __IOM R_ETHSW_MGMT_ADDR_Type MGMT_ADDR[4]; /*!< (@ 0x000001C0) MAC Address [0..3] for Bridge Protocol Frame
+                                                *                  Register                                                   */
+
+    union
+    {
+        __IOM uint32_t SRCFLT_ENA;             /*!< (@ 0x000001E0) MAC Source Address Filtering Enable Register               */
+
+        struct
+        {
+            __IOM uint32_t SRCENA : 3;         /*!< [2..0] Per-Source Port Enable                                             */
+            uint32_t              : 13;
+            __IOM uint32_t DSTENA : 4;         /*!< [19..16] Per-Destination Port Enable                                      */
+            uint32_t              : 12;
+        } SRCFLT_ENA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SRCFLT_CONTROL;         /*!< (@ 0x000001E4) MAC Source Address Filtering Control Register              */
+
+        struct
+        {
+            __IOM uint32_t MGMT_FWD      : 1;  /*!< [0..0] Management Forward Enable                                          */
+            __IOM uint32_t WATCHDOG_ENA  : 1;  /*!< [1..1] When set to 1, a watchdog is enabled.                              */
+            uint32_t                     : 14;
+            __IOM uint32_t WATCHDOG_TIME : 16; /*!< [31..16] Defines the watchdog expire time in milliseconds. The
+                                                *   default is 2000 milliseconds.                                             */
+        } SRCFLT_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SRCFLT_MACADDR_LO;       /*!< (@ 0x000001E8) Lower MAC Filtering Address Register                       */
+
+        struct
+        {
+            __IOM uint32_t SRCFLT_MACADDR : 32; /*!< [31..0] MAC address to use in source filtering                            */
+        } SRCFLT_MACADDR_LO_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SRCFLT_MACADDR_HI;       /*!< (@ 0x000001EC) Higher MAC Filtering Address Register                      */
+
+        struct
+        {
+            __IOM uint32_t SRCFLT_MACADDR : 16; /*!< [15..0] MAC address to use in source filtering                            */
+            __IOM uint32_t MASK           : 16; /*!< [31..16] The mask to apply to the last 16 bits of the MAC address         */
+        } SRCFLT_MACADDR_HI_b;
+    };
+    __IM uint32_t RESERVED6[3];
+
+    union
+    {
+        __IOM uint32_t PHY_FILTER_CFG;          /*!< (@ 0x000001FC) Debounce Filter Configuration Register                     */
+
+        struct
+        {
+            __IOM uint32_t FILTER_DURATION : 9; /*!< [8..0] This is the amount of time to wait after the last phy_link
+                                                 *   (ETHSW_PHYLINKn: n = port) transition from 0 to 1 to acknowledge
+                                                 *   the link-up condition.                                                    */
+            uint32_t              : 7;
+            __IOM uint32_t FLT_EN : 3;          /*!< [18..16] Per-port Enable Mask                                             */
+            uint32_t              : 13;
+        } PHY_FILTER_CFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYSTEM_TAGINFO[4];    /*!< (@ 0x00000200) One VLAN ID Field [0..3] for VLAN Input Manipulation       */
+
+        struct
+        {
+            __IOM uint32_t SYSVLANINFO : 16; /*!< [15..0] System VLAN Info (prio/cfi/vid) for Port n                        */
+            uint32_t                   : 16;
+        } SYSTEM_TAGINFO_b[4];
+    };
+    __IM uint32_t RESERVED7[12];
+
+    union
+    {
+        __IOM uint32_t AUTH_PORT[4];        /*!< (@ 0x00000240) Port [0..3] Authentication Control and Configuration       */
+
+        struct
+        {
+            __IOM uint32_t AUTH        : 1; /*!< [0..0] Authorized                                                         */
+            __IOM uint32_t CTRL_BOTH   : 1; /*!< [1..1] Controlled Both                                                    */
+            __IOM uint32_t EAPOL_EN    : 1; /*!< [2..2] EAPOL Enable                                                       */
+            __IOM uint32_t GUEST_EN    : 1; /*!< [3..3] Guest Enable                                                       */
+            __IOM uint32_t BPDU_EN     : 1; /*!< [4..4] BPDU Enable                                                        */
+            __IOM uint32_t EAPOL_UC_EN : 1; /*!< [5..5] EAPOL Unicast Enable                                               */
+            uint32_t                   : 5;
+            __IOM uint32_t ACHG_UNAUTH : 1; /*!< [11..11] Automatic Port Change to Unauthorized                            */
+            __IOM uint32_t EAPOL_PNUM  : 4; /*!< [15..12] EAPOL Port Number                                                */
+            __IOM uint32_t GUEST_MASK  : 4; /*!< [19..16] Destination port mask with all ports that are allowed
+                                             *   to receive non-EAPOL frames from this port while it is
+                                             *   unauthorized and guest (GUEST_EN) is enabled.                             */
+            uint32_t : 12;
+        } AUTH_PORT_b[4];
+    };
+    __IM uint32_t RESERVED8[12];
+
+    union
+    {
+        __IOM uint32_t VLAN_RES_TABLE[32]; /*!< (@ 0x00000280) 32 VLAN Domain Entries                                     */
+
+        struct
+        {
+            __IOM uint32_t PORTMASK : 4;   /*!< [3..0] When this bit is set to 1, it defines a port as a member
+                                            *   of the VLAN. When bit [28] or bit [29] is set, the tagged
+                                            *   bit mask is read/written instead of port mask.                            */
+            __IOM uint32_t VLANID    : 12; /*!< [15..4] The 12-bit VLAN identifier (VLAN ID) of the entry.                */
+            uint32_t                 : 12;
+            __IOM uint32_t RD_TAGMSK : 1;  /*!< [28..28] Read TAG Mask                                                    */
+            __IOM uint32_t WT_TAGMSK : 1;  /*!< [29..29] Write TAG Mask                                                   */
+            __IOM uint32_t WT_PRTMSK : 1;  /*!< [30..30] Write Port Mask                                                  */
+            uint32_t                 : 1;
+        } VLAN_RES_TABLE_b[32];
+    };
+
+    union
+    {
+        __IM uint32_t TOTAL_DISC;          /*!< (@ 0x00000300) Discarded Frame Total Number Register                      */
+
+        struct
+        {
+            __IM uint32_t TOTAL_DISC : 32; /*!< [31..0] Total number of incoming frames accepted by MAC RX but
+                                            *   discarded in the switch                                                   */
+        } TOTAL_DISC_b;
+    };
+
+    union
+    {
+        __IM uint32_t TOTAL_BYT_DISC;          /*!< (@ 0x00000304) Discarded Frame Total Bytes Register                       */
+
+        struct
+        {
+            __IM uint32_t TOTAL_BYT_DISC : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_DISC                      */
+        } TOTAL_BYT_DISC_b;
+    };
+
+    union
+    {
+        __IM uint32_t TOTAL_FRM;          /*!< (@ 0x00000308) Processed Frame Total Number Register                      */
+
+        struct
+        {
+            __IM uint32_t TOTAL_FRM : 32; /*!< [31..0] Total number of incoming frames processed by the switch           */
+        } TOTAL_FRM_b;
+    };
+
+    union
+    {
+        __IM uint32_t TOTAL_BYT_FRM;          /*!< (@ 0x0000030C) Processed Frame Total Bytes Register                       */
+
+        struct
+        {
+            __IM uint32_t TOTAL_BYT_FRM : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_FRM                       */
+        } TOTAL_BYT_FRM_b;
+    };
+    __IM uint32_t RESERVED9[12];
+
+    union
+    {
+        __IOM uint32_t IALK_CONTROL;        /*!< (@ 0x00000340) IA Lookup Function Enable Register                         */
+
+        struct
+        {
+            __IOM uint32_t IA_LKUP_ENA : 4; /*!< [3..0] Per-port Enable to the IA Lookup Table                             */
+            uint32_t                   : 12;
+            __IOM uint32_t CT_ENA      : 4; /*!< [19..16] Per-port Cut-Through Mode Enable                                 */
+            uint32_t                   : 12;
+        } IALK_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_OUI;          /*!< (@ 0x00000344) IA Frames MAC Address OUI Register                         */
+
+        struct
+        {
+            __IOM uint32_t IALK_OUI : 24; /*!< [23..0] IA Frames MAC Address OUI                                         */
+            uint32_t                : 8;
+        } IALK_OUI_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_ID_MIN;          /*!< (@ 0x00000348) Minimum Value ID MAC Address Register                      */
+
+        struct
+        {
+            __IOM uint32_t IALK_ID_MIN : 24; /*!< [23..0] Minimum value for the 24-bit ID in the MAC address                */
+            uint32_t                   : 8;
+        } IALK_ID_MIN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_ID_MAX;          /*!< (@ 0x0000034C) Maximum Value ID MAC Address Register                      */
+
+        struct
+        {
+            __IOM uint32_t IALK_ID_MAX : 24; /*!< [23..0] Maximum value for the 24-bit ID in the MAC address                */
+            uint32_t                   : 8;
+        } IALK_ID_MAX_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_ID_SUB;          /*!< (@ 0x00000350) Offset Value ID MAC Address Register                       */
+
+        struct
+        {
+            __IOM uint32_t IALK_ID_SUB : 24; /*!< [23..0] Offset value to subtract from the 24-bit ID in the MAC
+                                              *   address                                                                   */
+            uint32_t : 8;
+        } IALK_ID_SUB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_ID_CONFIG;              /*!< (@ 0x00000354) Configures Lookup Response Unknown IDs Register            */
+
+        struct
+        {
+            __IOM uint32_t INVLD_ID_FLOOD : 1;      /*!< [0..0] Setting this bit to 1 causes the IA table to return a
+                                                     *   found response for frames whose ID lies outside the ID
+                                                     *   range defined by [IA_LK_MAX:IA_LK_MIN] using INVLD_ID_FLOOD_MASK[3:0]
+                                                     *   bits.                                                                     */
+            __IOM uint32_t INVLD_ID_LRN_ENA : 1;    /*!< [1..1] Setting this bit to 1 allows automatic learning into
+                                                     *   the L2 FDB for frames with unknown IDs. When 0, learning
+                                                     *   is inhibited. This bit is only valid when INVLD_ID_FLOOD
+                                                     *   bit is set to 1.                                                          */
+            uint32_t                     : 2;
+            __IOM uint32_t INVLD_ID_PRIO : 3;       /*!< [6..4] Priority to use for found responses of an invalid ID.
+                                                     *   This bit is only valid when INVLD_ID_FLOOD bit is set to
+                                                     *   1.                                                                        */
+            __IOM uint32_t INVLD_ID_PRIO_VLD : 1;   /*!< [7..7] Indicates if the priority in INVLD_ID_PRIO is valid.
+                                                     *   This bit is valid only when INVLD_ID_FLOOD bit is set to
+                                                     *   1.                                                                        */
+            uint32_t                           : 8;
+            __IOM uint32_t INVLD_ID_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames whose ID is invalid.
+                                                     *   This bit is only valid when INVLD_ID_FLOOD bit is set to
+                                                     *   1. Setting this mask to 0 causes the frame to be dropped.                 */
+            uint32_t : 12;
+        } IALK_ID_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_VLAN_CONFIG;              /*!< (@ 0x00000358) Configure Lookup Response Unknown VLAN Register            */
+
+        struct
+        {
+            __IOM uint32_t UNKWN_VLAN_FLOOD : 1;      /*!< [0..0] When this bit is set to 1, a frame matching the OUI and
+                                                       *   with a valid ID but having a VLAN ID not matching any of
+                                                       *   the enabled values in IALK_VLANIDn causes the IA table
+                                                       *   to return a found response using the forwarding mask in
+                                                       *   UNKWN_VLAN_FLOOD_MASK[3:0].                                               */
+            __IOM uint32_t UNKWN_VLAN_LRN_ENA : 1;    /*!< [1..1] Setting this bit to 1 allows automatic learning into
+                                                       *   the L2 FDB for frames with unknown VLANs. When 0, learning
+                                                       *   is inhibited. This bit is only valid when UNKWN_VLAN_FLOOD
+                                                       *   bit is set to 1.                                                          */
+            uint32_t                       : 2;
+            __IOM uint32_t UNKWN_VLAN_PRIO : 3;       /*!< [6..4] Priority to use for found responses for an unknown VLAN.
+                                                       *   This bit is only valid when UNKWN_VLAN_FLOOD bit is set
+                                                       *   to 1.                                                                     */
+            __IOM uint32_t UNKWN_VLAN_PRIO_VLD : 1;   /*!< [7..7] Indicates if the priority in UNKWN_VLAN_PRIO[2:0] is
+                                                       *   valid. This bit is only valid when UNKWN_VLAN_FLOOD bit
+                                                       *   is set to 1.                                                              */
+            __IOM uint32_t VLANS_ENABLED : 3;         /*!< [10..8] Configures the logical geometry of the IA table by specifying
+                                                       *   the number of distinct VLAN IDs enabled. When set to 0,
+                                                       *   no VLANs are supported and the VLAN ID for the frames is
+                                                       *   ignored.                                                                  */
+            uint32_t                             : 5;
+            __IOM uint32_t UNKWN_VLAN_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames with an unknown VLAN
+                                                       *   ID.                                                                       */
+            uint32_t : 12;
+        } IALK_VLAN_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_TBL_ADDR;  /*!< (@ 0x0000035C) IA Lookup Database Address Register                        */
+
+        struct
+        {
+            __IOM uint32_t ADDR : 13;  /*!< [12..0] Defines the address to write to or read from the IA
+                                        *   Lookup table                                                              */
+            uint32_t            : 15;
+            __IOM uint32_t AINC : 4;   /*!< [31..28] Auto-Increment Control                                           */
+        } IALK_TBL_ADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_TBL_DATA;    /*!< (@ 0x00000360) IA Lookup Database Data Register                           */
+
+        struct
+        {
+            __IOM uint32_t VALID : 1;    /*!< [0..0] Indicates whether the entry indicated by ADDR is valid
+                                          *   or not.                                                                   */
+            __IOM uint32_t FWD_MASK : 4; /*!< [4..1] Forwarding mask used for lookups that hit the entry and
+                                          *   when VALID is set to 1.                                                   */
+            uint32_t : 27;
+        } IALK_TBL_DATA_b;
+    };
+    __IM uint32_t RESERVED10[7];
+
+    union
+    {
+        __IOM uint32_t IALK_VLANID[4];            /*!< (@ 0x00000380) IA Lookup VLANIDn Register                                 */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12;           /*!< [11..0] Configure the VLAN ID to be used for VLAN n (n: IALK_VLAN_CONFIG.VLANS
+                                                   *   ENABLED). This bit is only valid when VLANID_ENA bit is
+                                                   *   set to 1. A value of 0 matches any VLAN ID.                               */
+            __IOM uint32_t VLANID_ENA : 1;        /*!< [12..12] Enables this VLAN ID. When set to 1, the VLAN ID of
+                                                   *   the frame is compared against VLANID[11:0].                               */
+            __IOM uint32_t VLANID_LRN_ENA : 1;    /*!< [13..13] Configures whether automatic learning in the L2 FDB
+                                                   *   is allowed for frames matching VLAN ID. This also includes
+                                                   *   frames that match the VLAN ID and that the entry in the
+                                                   *   IA table is invalid.                                                      */
+            uint32_t                         : 2;
+            __IOM uint32_t VLANID_FLOOD_MASK : 4; /*!< [19..16] Flooding mask to be used for frames matching this VLAN
+                                                   *   ID but with an invalid entry in the IA table.                             */
+            uint32_t                       : 8;
+            __IOM uint32_t VLANID_PRIO     : 3;   /*!< [30..28] Priority to use for found responses.                             */
+            __IOM uint32_t VLANID_PRIO_VLD : 1;   /*!< [31..31] Indicates if the priority in VLANID_PRIO[2:0] is valid.          */
+        } IALK_VLANID_b[4];
+    };
+    __IM uint32_t RESERVED11[12];
+
+    union
+    {
+        __IM uint32_t IMC_QLEVEL_P[4]; /*!< (@ 0x000003C0) Port [0..3] Queued Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t QUEUE0 : 4;  /*!< [3..0] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 0                                                         */
+            __IM uint32_t QUEUE1 : 4;  /*!< [7..4] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 1                                                         */
+            __IM uint32_t QUEUE2 : 4;  /*!< [11..8] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 2                                                         */
+            __IM uint32_t QUEUE3 : 4;  /*!< [15..12] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 3                                                         */
+            __IM uint32_t QUEUE4 : 4;  /*!< [19..16] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 4                                                         */
+            __IM uint32_t QUEUE5 : 4;  /*!< [23..20] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 5                                                         */
+            __IM uint32_t QUEUE6 : 4;  /*!< [27..24] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 6                                                         */
+            __IM uint32_t QUEUE7 : 4;  /*!< [31..28] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 7                                                         */
+        } IMC_QLEVEL_P_b[4];
+    };
+    __IM uint32_t RESERVED12[12];
+
+    union
+    {
+        __IOM uint32_t LK_CTRL;               /*!< (@ 0x00000400) Learning/Lookup Function Global Configuration
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t LKUP_EN       : 1; /*!< [0..0] Lookup Controller Enable                                           */
+            __IOM uint32_t LEARN_EN      : 1; /*!< [1..1] Learning Enable                                                    */
+            __IOM uint32_t AGING_EN      : 1; /*!< [2..2] Aging Enable                                                       */
+            __IOM uint32_t ALW_MGRT      : 1; /*!< [3..3] Allow Migration                                                    */
+            __IOM uint32_t DISC_UNK_DEST : 1; /*!< [4..4] Discard Unknown Destination                                        */
+            uint32_t                     : 1;
+            __IOM uint32_t CLRTBL        : 1; /*!< [6..6] Clear Table                                                        */
+            __IOM uint32_t IND_VLAN      : 1; /*!< [7..7] Enable Independent VLAN Learning                                   */
+            uint32_t                     : 8;
+            __IOM uint32_t DISC_UNK_SRC  : 4; /*!< [19..16] Discard Unknown Source                                           */
+            uint32_t                     : 12;
+        } LK_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_STATUS;       /*!< (@ 0x00000404) Status Bits and Table Overflow Counter Register            */
+
+        struct
+        {
+            __IM uint32_t AGEADDR : 16; /*!< [15..0] Address the aging process will inspect when the aging
+                                         *   timer expires next time.                                                  */
+            __IOM uint32_t OVRF : 14;   /*!< [29..16] Counts number of table overflows that occurred (a new
+                                         *   address was learned but the table had no storage and an
+                                         *   older entry was deleted). The counter is cleared by writing
+                                         *   into the register and having bit 16 set to 1.                             */
+            uint32_t               : 1;
+            __IOM uint32_t LRNEVNT : 1; /*!< [31..31] Learn Event                                                      */
+        } LK_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_ADDR_CTRL;        /*!< (@ 0x00000408) Address Table Transaction Control and Read/Write
+                                             *                  Address                                                    */
+
+        struct
+        {
+            __IOM uint32_t ADDR_MSK : 12;   /*!< [11..0] Memory address for read and write transactions. This
+                                             *   is the address of a 69-bit entry. For the DEL_PORT bit,
+                                             *   a port mask can be provided in these bits instead of the
+                                             *   address. Bit 0 represents port 0, bit 1 port 1, and so
+                                             *   on.                                                                       */
+            uint32_t                   : 10;
+            __IOM uint32_t CLR_DYNAMIC : 1; /*!< [22..22] When set to 1, scans the complete table for valid dynamic
+                                             *   entries and deletes them (writes entry with all 0s). This
+                                             *   bit is cleared when the function has completed.                           */
+            __IOM uint32_t CLR_STATIC : 1;  /*!< [23..23] When set to 1, scans the complete table for valid static
+                                             *   entries and deletes them (writes entry with all 0s). This
+                                             *   bit is cleared when the function has completed.                           */
+            __IOM uint32_t GETLASTNEW : 1;  /*!< [24..24] When set to 1, retrieves the last source address that
+                                             *   was not found in the table and places it into LK_DATA_LO/HI/HI2.
+                                             *   The valid bit of the entry (bit LK_DATA_HI[16]) indicates
+                                             *   if the address is new (when valid bit is 1) or not (when
+                                             *   valid bit is 0) since the command was last issued.                        */
+            __IOM uint32_t WRITE     : 1;   /*!< [25..25] When set to 1, perform a single write transaction.               */
+            __IOM uint32_t READ      : 1;   /*!< [26..26] When set to 1, perform a single read transaction.                */
+            __IOM uint32_t WAIT_COMP : 1;   /*!< [27..27] When set to 1, instructs to stall the processor bus
+                                             *   until the transaction is completed. This allows performing
+                                             *   of consecutive writes into this register with varying commands
+                                             *   without the need for polling the BUSY bit.                                */
+            __IM uint32_t LOOKUP : 1;       /*!< [28..28] When set to 1, perform a lookup of the MAC address
+                                             *   given in LK_DATA_LO/HI/HI2.                                               */
+            __IOM uint32_t CLEAR : 1;       /*!< [29..29] When set to 1, writes all 0s to the entry selected
+                                             *   by the given address set in ADDR_MSK[11:0]. If this bit
+                                             *   is set together with the LOOKUP bit, first a lookup is
+                                             *   performed and if the lookup succeeds, the entry is then
+                                             *   deleted. The registers LK_DATA_LO/HI/HI2 are also cleared.
+                                             *   The memory address in this register is set from the lookup
+                                             *   result. If the lookup failed, the clear command is ignored
+                                             *   and memory address is arbitrary.                                          */
+            __IOM uint32_t DEL_PORT : 1;    /*!< [30..30] When set to 1, scans the complete table for valid dynamic
+                                             *   entries that contain the given ports in their destination
+                                             *   port mask and deletes the ports or the complete entry.
+                                             *   The port mask is provided in the ADDR_MSK[3:0] when writing
+                                             *   this register (1 bit per port, bit 0 = port 0, bit 1 =
+                                             *   port 1, and so on).                                                       */
+            __IM uint32_t BUSY : 1;         /*!< [31..31] Transaction Busy Indication                                      */
+        } LK_ADDR_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_DATA_LO;       /*!< (@ 0x0000040C) Lower 32-Bit Data of Lookup Memory Entry                   */
+
+        struct
+        {
+            __IOM uint32_t MEMDATA : 32; /*!< [31..0] Memory Data [31:0]                                                */
+        } LK_DATA_LO_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_DATA_HI;       /*!< (@ 0x00000410) Higher 25-Bit Data of Lookup Memory Entry                  */
+
+        struct
+        {
+            __IOM uint32_t MEMDATA : 25; /*!< [24..0] Memory Data [56:32]                                               */
+            uint32_t               : 7;
+        } LK_DATA_HI_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_DATA_HI2;    /*!< (@ 0x00000414) Higher2 12-Bit Data of Lookup Memory Entry                 */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IOM uint32_t MEMDATA : 12; /*!< [19..8] Memory Data [68:57]                                               */
+            uint32_t               : 12;
+        } LK_DATA_HI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_LEARNCOUNT;       /*!< (@ 0x00000418) Learned Address Count Register                             */
+
+        struct
+        {
+            __IOM uint32_t LEARNCOUNT : 13; /*!< [12..0] Number of Learned Addresses                                       */
+            uint32_t                  : 17;
+            __IOM uint32_t WRITE_MD   : 2;  /*!< [31..30] These bits define how the LEARNCOUNT value is modified
+                                             *   when writing into the register:                                           */
+        } LK_LEARNCOUNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_AGETIME;       /*!< (@ 0x0000041C) Period of the Aging Timer                                  */
+
+        struct
+        {
+            __IOM uint32_t AGETIME : 24; /*!< [23..0] 24-bit Timer Value                                                */
+            uint32_t               : 8;
+        } LK_AGETIME_b;
+    };
+    __IM uint32_t RESERVED13[24];
+
+    union
+    {
+        __IOM uint32_t MGMT_TAG_CONFIG;   /*!< (@ 0x00000480) Management Tag Configuration Register                      */
+
+        struct
+        {
+            __IOM uint32_t ENABLE    : 1; /*!< [0..0] Enable Management Tag Insertion Module                             */
+            __IOM uint32_t AL_FRAMES : 1; /*!< [1..1] Enable Tag Insertion for All Frames                                */
+            uint32_t                 : 2;
+            __IOM uint32_t TYPE1_EN  : 1; /*!< [4..4] When set, frames with a Type field that match the value
+                                           *   in PRIORITY_TYPE1.TYPEVAL[15:0] have management tag inserted.
+                                           *   This is in addition to BPDU frames which always have tag
+                                           *   inserted.                                                                 */
+            __IOM uint32_t TYPE2_EN : 1;  /*!< [5..5] When set, frames with a Type field that match the value
+                                           *   in PRIORITY_TYPE2.TYPEVAL[15:0] have management tag inserted.
+                                           *   This is in addition to BPDU frames which always have tag
+                                           *   inserted.                                                                 */
+            uint32_t                : 10;
+            __IOM uint32_t TAGFIELD : 16; /*!< [31..16] The value of the tag that is found in the first Type/Length
+                                           *   field of the frame to identify that the control information
+                                           *   is present within a frame. For example, [31:24] = first
+                                           *   octet, [23:16] = 2nd octet.                                               */
+        } MGMT_TAG_CONFIG_b;
+    };
+    __IM uint32_t RESERVED14[32];
+
+    union
+    {
+        __IOM uint32_t TSM_CONFIG;             /*!< (@ 0x00000504) Timestamping Control Module Configuration Register         */
+
+        struct
+        {
+            __IOM uint32_t IRQ_EN         : 1; /*!< [0..0] Final Interrupt enable                                             */
+            __IOM uint32_t IRQ_TEST       : 1; /*!< [1..1] Software controlled interrupt for testing purposes                 */
+            __IOM uint32_t IRQ_TSFIFO_OVR : 1; /*!< [2..2] Trigger interrupt enable for Transmit Timestamp Capture
+                                                *   Overflow event                                                            */
+            uint32_t                      : 1;
+            __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Trigger interrupt enable for the timer offset
+                                                *   event                                                                     */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Trigger interrupt enable for the timer periodical
+                                                *   event                                                                     */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Trigger interrupt enable for the timer wrap
+                                                *   (reached its maximum)                                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t IRQ_TX_EN : 4;      /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt Enable             */
+            uint32_t                 : 12;
+        } TSM_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TSM_IRQ_STAT_ACK;       /*!< (@ 0x00000508) Interrupt Status/Acknowledge Register                      */
+
+        struct
+        {
+            __IM uint32_t  IRQ_STAT       : 1; /*!< [0..0] Interrupt Pending Status                                           */
+            __IOM uint32_t IRQ_TEST       : 1; /*!< [1..1] Test Interrupt Pending Status                                      */
+            __IM uint32_t  IRQ_TSFIFO_OVR : 1; /*!< [2..2] Transmit Timestamp Capture Overflow Interrupt Pending
+                                                *   Status                                                                    */
+            uint32_t                      : 1;
+            __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Offset Interrupt Pending Status                          */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Periodical Interrupt Pending Status                      */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Overflow Interrupt Pending Status                      */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_TX         : 4; /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt                    */
+            uint32_t                      : 12;
+        } TSM_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTP_DOMAIN;      /*!< (@ 0x0000050C) Domain Number of PTP Frame                                 */
+
+        struct
+        {
+            __IOM uint32_t DOMAIN0 : 8; /*!< [7..0] DomainNumber to Match Against for Timer 0                          */
+            __IOM uint32_t DOMAIN1 : 8; /*!< [15..8] DomainNumber to Match Against for Timer 1                         */
+            uint32_t               : 16;
+        } PTP_DOMAIN_b;
+    };
+    __IM uint32_t RESERVED15[12];
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P0_T0;    /*!< (@ 0x00000540) Port 0 Peer Delay Value for Timer 0 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   0                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P0_T0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P0_T1;    /*!< (@ 0x00000544) Port 0 Peer Delay Value for Timer 1 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   1                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P0_T1_b;
+    };
+    __IM uint32_t RESERVED16[2];
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P1_T0;    /*!< (@ 0x00000550) Port 1 Peer Delay Value for Timer 0 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   0                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P1_T0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P1_T1;    /*!< (@ 0x00000554) Port 1 Peer Delay Value for Timer 1 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   1                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P1_T1_b;
+    };
+    __IM uint32_t RESERVED17[2];
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P2_T0;    /*!< (@ 0x00000560) Port 2 Peer Delay Value for Timer 0 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   0                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P2_T0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P2_T1;    /*!< (@ 0x00000564) Port 2 Peer Delay Value for Timer 1 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   1                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P2_T1_b;
+    };
+    __IM uint32_t RESERVED18[2];
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P3_T0;    /*!< (@ 0x00000570) Port 3 Peer Delay Value for Timer 0 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   0                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P3_T0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P3_T1;    /*!< (@ 0x00000574) Port 3 Peer Delay Value for Timer 1 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   1                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P3_T1_b;
+    };
+    __IM uint32_t RESERVED19[18];
+
+    union
+    {
+        __IOM uint32_t TS_FIFO_STATUS;  /*!< (@ 0x000005C0) Transmit Timestamp FIFO Status Register                    */
+
+        struct
+        {
+            __IM uint32_t FF_VALID : 4; /*!< [3..0] Per-port indication that a valid timestamp is available
+                                         *   in the corresponding FIFO of the port                                     */
+            uint32_t              : 12;
+            __IOM uint32_t FF_OVR : 4;  /*!< [19..16] Per-port indication that a timestamp cannot be written
+                                         *   to the FIFO because of the FIFO being full.                               */
+            uint32_t : 12;
+        } TS_FIFO_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TS_FIFO_READ_CTRL; /*!< (@ 0x000005C4) Transmit Timestamp FIFO Read Control Register              */
+
+        struct
+        {
+            __IOM uint32_t PORT_NUM : 2;  /*!< [1..0] Port Number to Read from                                           */
+            uint32_t                : 2;
+            __IM uint32_t TS_VALID  : 1;  /*!< [4..4] When reading from this register, this bit is 1 if the
+                                           *   FIFO indicated by PORT_NUM contained valid data.                          */
+            uint32_t             : 1;
+            __IM uint32_t TS_SEL : 1;     /*!< [6..6] When TS_VALID is 1, TS_SEL indicates the timer used for
+                                           *   the read timestamp.                                                       */
+            uint32_t            : 1;
+            __IM uint32_t TS_ID : 7;      /*!< [14..8] When TS_VALID is 1, TS_ID indicates the ID specified
+                                           *   by the application through the management tag control information,
+                                           *   if present.                                                               */
+            uint32_t : 17;
+        } TS_FIFO_READ_CTRL_b;
+    };
+
+    union
+    {
+        __IM uint32_t TS_FIFO_READ_TIMESTAMP; /*!< (@ 0x000005C8) 32-bit Timestamp Value Read from FIFO                      */
+
+        struct
+        {
+            __IM uint32_t TIMESTAMP : 32;     /*!< [31..0] 32-bit timestamp value read from the FIFO                         */
+        } TS_FIFO_READ_TIMESTAMP_b;
+    };
+    __IM uint32_t RESERVED20[13];
+
+    union
+    {
+        __IOM uint32_t INT_CONFIG;            /*!< (@ 0x00000600) Interrupt Enable Configuration Register                    */
+
+        struct
+        {
+            __IOM uint32_t IRQ_EN     : 1;    /*!< [0..0] Interrupt Global Enable                                            */
+            __IOM uint32_t MDIO1      : 1;    /*!< [1..1] Enable Interrupt on Transaction Complete from MDIO Controller      */
+            uint32_t                  : 1;
+            __IOM uint32_t LK_NEW_SRC : 1;    /*!< [3..3] Enable Interrupt for New Source Address                            */
+            __IOM uint32_t IRQ_TEST   : 1;    /*!< [4..4] When set, an interrupt is triggered immediately. Can
+                                               *   be used to cause a software controlled interrupt for testing
+                                               *   purposes.                                                                 */
+            __IOM uint32_t DLR_INT       : 1; /*!< [5..5] Enable Interrupt for DLR                                           */
+            __IOM uint32_t PRP_INT       : 1; /*!< [6..6] Enable Interrupt for PRP                                           */
+            __IOM uint32_t HUB_INT       : 1; /*!< [7..7] Enable Interrupt for HUB                                           */
+            __IOM uint32_t IRQ_LINK      : 3; /*!< [10..8] Per Line Port Phy Link Change Interrupt Enable                    */
+            uint32_t                     : 5;
+            __IOM uint32_t IRQ_MAC_EEE   : 3; /*!< [18..16] Per Line Port MAC interrupt                                      */
+            uint32_t                     : 8;
+            __IOM uint32_t EFP_INT       : 1; /*!< [27..27] Enable Interrupt for Extended Frame Parser                       */
+            __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] MAC Address Source Filtering Watchdog                            */
+            __IOM uint32_t TSM_INT       : 1; /*!< [29..29] Enable Interrupt for TSM (Timer, Timestamping)                   */
+            __IOM uint32_t TDMA_INT      : 1; /*!< [30..30] Enable Interrupt for TDMA scheduler                              */
+            __IOM uint32_t PATTERN_INT   : 1; /*!< [31..31] Enable Interrupt for RX Pattern Matcher                          */
+        } INT_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INT_STAT_ACK;          /*!< (@ 0x00000604) Interrupt Status/ACK Register                              */
+
+        struct
+        {
+            __IM uint32_t  IRQ_PEND      : 1; /*!< [0..0] Interrupt Pending Status                                           */
+            __IOM uint32_t MDIO1         : 1; /*!< [1..1] Latched Interrupt Status for MDIO1                                 */
+            uint32_t                     : 1;
+            __IOM uint32_t LK_NEW_SRC    : 1; /*!< [3..3] Latched Interrupt Status for LK_NEW_SRC                            */
+            __IM uint32_t  IRQ_TEST      : 1; /*!< [4..4] Interrupt Status for IRQ_TEST                                      */
+            __IM uint32_t  DLR_INT       : 1; /*!< [5..5] Interrupt Pending Status from DLR Module                           */
+            __IM uint32_t  PRP_INT       : 1; /*!< [6..6] Interrupt Pending Status from PRP Module                           */
+            __IM uint32_t  HUB_INT       : 1; /*!< [7..7] Interrupt Pending Status from Hub Module                           */
+            __IOM uint32_t IRQ_LINK      : 3; /*!< [10..8] Interrupt Pending per Line Port Phy Link Change Interrupt         */
+            uint32_t                     : 5;
+            __IOM uint32_t IRQ_MAC_EEE   : 3; /*!< [18..16] Interrupt Pending Status per Line Port MAC Interrupt             */
+            uint32_t                     : 8;
+            __IOM uint32_t EFP_INT       : 1; /*!< [27..27] Interrupt from Extended Frame Parser                             */
+            __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] Interrupt Pending Status for MAC Source Filtering Watchdog       */
+            __IM uint32_t  TSM_INT       : 1; /*!< [29..29] Interrupt Pending Interrupt Indication from TSM (Timestamping)
+                                               *   module                                                                    */
+            __IM uint32_t TDMA_INT    : 1;    /*!< [30..30] Interrupt Pending Status from TDMA Scheduler                     */
+            __IM uint32_t PATTERN_INT : 1;    /*!< [31..31] Interrupt Pending Status from RX Pattern Matcher Module          */
+        } INT_STAT_ACK_b;
+    };
+    __IM uint32_t RESERVED21[30];
+
+    union
+    {
+        __IOM uint32_t ATIME_CTRL0;            /*!< (@ 0x00000680) Timer 0 Control Register (n = 0, 1)                        */
+
+        struct
+        {
+            __IOM uint32_t ENABLE   : 1;       /*!< [0..0] ENABLE                                                             */
+            __IOM uint32_t ONE_SHOT : 1;       /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum.
+                                                *   An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs
+                                                *   (if enabled) when the maximum is reached.                                 */
+            __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event                                                */
+            uint32_t                      : 1;
+            __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event                                            */
+            __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event                                    */
+            uint32_t                      : 3;
+            __IOM uint32_t RESTART        : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit)                             */
+            uint32_t                      : 1;
+            __IOM uint32_t CAPTURE        : 1; /*!< [11..11] Capture Time Value (Command Bit)                                 */
+            __IOM uint32_t CAPTURE_ALL    : 1; /*!< [12..12] Capture All Timers Value (Command Bit)                           */
+            uint32_t                      : 19;
+        } ATIME_CTRL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME0;             /*!< (@ 0x00000684) Timer 0 Count Register (n = 0, 1)                          */
+
+        struct
+        {
+            __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value                                                       */
+        } ATIME0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_OFFSET0;   /*!< (@ 0x00000688) Timer 0 Offset Register (n = 0, 1)                         */
+
+        struct
+        {
+            __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without
+                                         *   changing the drift correction                                             */
+        } ATIME_OFFSET0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_EVT_PERIOD0; /*!< (@ 0x0000068C) Timer 0 Periodic Event Register (n = 0, 1)                 */
+
+        struct
+        {
+            __IOM uint32_t PERIOD : 32;   /*!< [31..0] Value for generating periodic events                              */
+        } ATIME_EVT_PERIOD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_CORR0;          /*!< (@ 0x00000690) Timer 0 Correction Period Register (n = 0, 1)              */
+
+        struct
+        {
+            __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period                                                 */
+            uint32_t                   : 1;
+        } ATIME_CORR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_INC0;            /*!< (@ 0x00000694) Timer 0 Increment Register (n = 0, 1)                      */
+
+        struct
+        {
+            __IOM uint32_t CLK_PERIOD    : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds    */
+            uint32_t                     : 1;
+            __IOM uint32_t CORR_INC      : 7; /*!< [14..8] Correction Increment Value                                        */
+            uint32_t                     : 1;
+            __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value                                */
+            uint32_t                     : 9;
+        } ATIME_INC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_SEC0;        /*!< (@ 0x00000698) Timer 0 Seconds Time Register (n = 0, 1)                   */
+
+        struct
+        {
+            __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value                                                */
+        } ATIME_SEC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_OFFS_CORR0;       /*!< (@ 0x0000069C) Timer 0 Offset Correction Counter Register (n
+                                                *                  = 0, 1)                                                    */
+
+        struct
+        {
+            __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter                                         */
+        } ATIME_OFFS_CORR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_CTRL1;            /*!< (@ 0x000006A0) Timer 1 Control Register (n = 0, 1)                        */
+
+        struct
+        {
+            __IOM uint32_t ENABLE   : 1;       /*!< [0..0] ENABLE                                                             */
+            __IOM uint32_t ONE_SHOT : 1;       /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum.
+                                                *   An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs
+                                                *   (if enabled) when the maximum is reached.                                 */
+            __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event                                                */
+            uint32_t                      : 1;
+            __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event                                            */
+            __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event                                    */
+            uint32_t                      : 3;
+            __IOM uint32_t RESTART        : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit)                             */
+            uint32_t                      : 1;
+            __IOM uint32_t CAPTURE        : 1; /*!< [11..11] Capture Time Value (Command Bit)                                 */
+            __IOM uint32_t CAPTURE_ALL    : 1; /*!< [12..12] Capture All Timers Value (Command Bit)                           */
+            uint32_t                      : 19;
+        } ATIME_CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME1;             /*!< (@ 0x000006A4) Timer 1 Count Register (n = 0, 1)                          */
+
+        struct
+        {
+            __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value                                                       */
+        } ATIME1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_OFFSET1;   /*!< (@ 0x000006A8) Timer 1 Offset Register (n = 0, 1)                         */
+
+        struct
+        {
+            __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without
+                                         *   changing the drift correction                                             */
+        } ATIME_OFFSET1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_EVT_PERIOD1; /*!< (@ 0x000006AC) Timer 1 Periodic Event Register (n = 0, 1)                 */
+
+        struct
+        {
+            __IOM uint32_t PERIOD : 32;   /*!< [31..0] Value for generating periodic events                              */
+        } ATIME_EVT_PERIOD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_CORR1;          /*!< (@ 0x000006B0) Timer 1 Correction Period Register (n = 0, 1)              */
+
+        struct
+        {
+            __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period                                                 */
+            uint32_t                   : 1;
+        } ATIME_CORR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_INC1;            /*!< (@ 0x000006B4) Timer 1 Increment Register (n = 0, 1)                      */
+
+        struct
+        {
+            __IOM uint32_t CLK_PERIOD    : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds    */
+            uint32_t                     : 1;
+            __IOM uint32_t CORR_INC      : 7; /*!< [14..8] Correction Increment Value                                        */
+            uint32_t                     : 1;
+            __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value                                */
+            uint32_t                     : 9;
+        } ATIME_INC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_SEC1;        /*!< (@ 0x000006B8) Timer 1 Seconds Time Register (n = 0, 1)                   */
+
+        struct
+        {
+            __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value                                                */
+        } ATIME_SEC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_OFFS_CORR1;       /*!< (@ 0x000006BC) Timer 1 Offset Correction Counter Register (n
+                                                *                  = 0, 1)                                                    */
+
+        struct
+        {
+            __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter                                         */
+        } ATIME_OFFS_CORR1_b;
+    };
+    __IM uint32_t RESERVED22[16];
+
+    union
+    {
+        __IOM uint32_t MDIO_CFG_STATUS;  /*!< (@ 0x00000700) MDIO Configuration and Status Register                     */
+
+        struct
+        {
+            __IM uint32_t  BUSY     : 1; /*!< [0..0] MDIO Busy                                                          */
+            __IM uint32_t  READERR  : 1; /*!< [1..1] MDIO Read Error                                                    */
+            __IOM uint32_t HOLD     : 3; /*!< [4..2] MDIO Hold Time Setting                                             */
+            __IOM uint32_t DISPREAM : 1; /*!< [5..5] Disable Preamble                                                   */
+            uint32_t                : 1;
+            __IOM uint32_t CLKDIV   : 9; /*!< [15..7] MDIO Clock Divisor                                                */
+            uint32_t                : 16;
+        } MDIO_CFG_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MDIO_COMMAND;     /*!< (@ 0x00000704) MDIO PHY Command Register                                  */
+
+        struct
+        {
+            __IOM uint32_t REGADDR  : 5; /*!< [4..0] Register Address                                                   */
+            __IOM uint32_t PHYADDR  : 5; /*!< [9..5] PHY Address                                                        */
+            uint32_t                : 5;
+            __IOM uint32_t TRANINIT : 1; /*!< [15..15] If set to 1, a read transaction is initiated.                    */
+            uint32_t                : 16;
+        } MDIO_COMMAND_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MDIO_DATA;          /*!< (@ 0x00000708) MDIO Data Register                                         */
+
+        struct
+        {
+            __IOM uint32_t MDIO_DATA : 16; /*!< [15..0] MDIO_DATA                                                         */
+            uint32_t                 : 16;
+        } MDIO_DATA_b;
+    };
+    __IM uint32_t RESERVED23[61];
+
+    union
+    {
+        __IM uint32_t REV_P0;          /*!< (@ 0x00000800) Port 0 MAC Core Revision (n = 0 to 3)                      */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
+        } REV_P0_b;
+    };
+    __IM uint32_t RESERVED24;
+
+    union
+    {
+        __IOM uint32_t COMMAND_CONFIG_P0;       /*!< (@ 0x00000808) Port 0 Command Configuration Register (n = 0
+                                                 *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
+            __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
+            __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
+                                                 *   the IMC until the current frame is completed. This can
+                                                 *   cause the IPG between frames to be more than the value
+                                                 *   in TX_IPG_LENGTH.                                                         */
+            __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
+            __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
+            __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
+            uint32_t                    : 1;
+            __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
+            __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
+            __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
+            __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
+                                                 *   full-duplex only (set to 0).                                              */
+            __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
+            uint32_t                     : 1;
+            __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
+            uint32_t                     : 9;
+            __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
+            __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
+            __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
+                                                 *   register.                                                                 */
+            __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
+            __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
+            uint32_t                   : 2;
+            __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
+                                                 *   on transmit and on receive. The value is used when not
+                                                 *   overridden by the PTP auto-response function, pattern matchers
+                                                 *   or force forwarding information in a management tag.                      */
+            uint32_t : 1;
+        } COMMAND_CONFIG_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_0_P0;     /*!< (@ 0x0000080C) Port 0 MAC Address Register 0 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
+                                           *   byte is bits [7:0]. The MAC address is used on locally
+                                           *   generated frames such as pause frames, peer-delay response.               */
+        } MAC_ADDR_0_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_1_P0;     /*!< (@ 0x00000810) Port 0 MAC Address Register 1 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
+                                           *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
+            uint32_t : 16;
+        } MAC_ADDR_1_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRM_LENGTH_P0;       /*!< (@ 0x00000814) Port 0 Maximum Frame Length Register (n = 0 to
+                                             *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
+            uint32_t                  : 18;
+        } FRM_LENGTH_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t PAUSE_QUANT_P0;       /*!< (@ 0x00000818) Port 0 MAC Pause Quanta (n = 0 to 3)                       */
+
+        struct
+        {
+            __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
+            uint32_t                  : 16;
+        } PAUSE_QUANT_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_LINK_QTRIG_P0;  /*!< (@ 0x0000081C) Port 0 Trigger Event Configuration Register (n
+                                            *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
+            uint32_t                  : 12;
+            __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
+                                            *   is transmitted from the ports indicated by PORT_MASK. A
+                                            *   single frame is transmitted per indicated port in PORT_MASK
+                                            *   among the queues indicated by QUEUE_MASK.                                 */
+            uint32_t                 : 4;
+            __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
+                                            *   a frame was transmitted. When MODE is set to 0, TRIGGERED
+                                            *   is always 0. This flag clears when the register is written.               */
+            __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
+                                            *   set to 1, the Link Queue Trigger occurs only if the DLR
+                                            *   state machine is in the NORMAL or FAULT state.                            */
+            __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
+                                            *   This is to prevent sending multiple frames due to link
+                                            *   flapping.                                                                 */
+            __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
+                                            *   When the link status (phy_link) transitions from 1 ->
+                                            *   0, a trigger event is generated to the memory controller
+                                            *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
+        } MAC_LINK_QTRIG_P0_b;
+    };
+    __IM uint32_t RESERVED25[4];
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY1_P0;  /*!< (@ 0x00000830) Port 0 PTP Clock Identity 1 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
+            __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
+            __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
+            __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
+        } PTPCLOCKIDENTITY1_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY2_P0;  /*!< (@ 0x00000834) Port 0 PTP Clock Identity 2 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
+            __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
+            __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
+            __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
+        } PTPCLOCKIDENTITY2_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPAUTORESPONSE_P0; /*!< (@ 0x00000838) Port 0 PTP Auto Response Register (n = 0 to 2)             */
+
+        struct
+        {
+            __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
+            __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
+            uint32_t                : 14;
+            __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
+            __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
+        } PTPAUTORESPONSE_P0_b;
+    };
+    __IM uint32_t RESERVED26;
+
+    union
+    {
+        __IOM uint32_t STATUS_P0;          /*!< (@ 0x00000840) Port 0 Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
+            __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
+            __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
+            __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
+                                            *   never occur during normal operation.                                      */
+            __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
+                                            *   to complete in time before the next frame was received
+                                            *   at the port. This should never occur under normal operation.
+                                            *   The cause could be from IPG violations in the received
+                                            *   frames.                                                                   */
+            __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
+                                            *   to clause 30.14.1.2 of the 802.3br specification                          */
+            uint32_t : 23;
+        } STATUS_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TX_IPG_LENGTH_P0;      /*!< (@ 0x00000844) Port 0 Transmit IPG Length Register (n = 0 to
+                                               *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
+                                               *   are in the range of 8 to 31.                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
+            uint32_t                  : 11;
+        } TX_IPG_LENGTH_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_CTL_STAT_P0;        /*!< (@ 0x00000848) Port 0 MAC EEE Functions Control and Status (n
+                                                *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
+            __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
+            __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
+            uint32_t                    : 5;
+            __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
+            __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
+            __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
+            __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
+                                                *   available for transmission.                                               */
+            __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
+            uint32_t                      : 3;
+            __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
+            __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
+                                                *   MAC                                                                       */
+            __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
+            uint32_t                   : 1;
+            __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
+            uint32_t                   : 11;
+        } EEE_CTL_STAT_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_IDLE_TIME_P0;       /*!< (@ 0x0000084C) Port 0 EEE Idle Time Register (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
+                                                *   of LPI begins. A 32-bit value in steps of 32 switch operating
+                                                *   clock cycles. A value of 0 disables the timer. The value
+                                                *   must be set to 1 less count.                                              */
+        } EEE_IDLE_TIME_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_TWSYS_TIME_P0;      /*!< (@ 0x00000850) Port 0 EEE Wake Up Time Register (n = 0 to 2)              */
+
+        struct
+        {
+            __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
+                                                *   to begin transmitting the first frame again. A 32-bit value
+                                                *   in steps of switch operating clock cycles. A value of 0
+                                                *   disables the timer. The value must be set to 1 less count.                */
+        } EEE_TWSYS_TIME_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IDLE_SLOPE_P0;       /*!< (@ 0x00000854) Port 0 MAC Traffic Shaper Bandwidth Control                */
+
+        struct
+        {
+            __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
+            uint32_t                  : 21;
+        } IDLE_SLOPE_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CT_DELAY_P0;      /*!< (@ 0x00000858) Port 0 Cut-Through Delay Indication Register               */
+
+        struct
+        {
+            __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
+                                          *   of the MII PHY interface)                                                 */
+            uint32_t : 23;
+        } CT_DELAY_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BR_CONTROL_P0;            /*!< (@ 0x0000085C) Port 0 802.3br Frame Configuration Register                */
+
+        struct
+        {
+            __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
+            __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
+                                                  *   preemption operation.                                                     */
+            __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
+                                                  *   frames.                                                                   */
+            uint32_t                      : 1;
+            __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
+            uint32_t                      : 2;
+            __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
+            uint32_t                      : 1;
+            __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
+                                                  *   except the SFD are 0x55. When set to 0, only the last 2
+                                                  *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
+                                                  *   It is recommended to set this bit to 1 to comply with the
+                                                  *   802.3br specification. This bit must be set to 0 if only
+                                                  *   non-802.3br traffic is expected (for example, normal Ethernet
+                                                  *   traffic) and if custom preamble is used.                                  */
+            __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
+                                                  *   SMDs and assumes all frames are express frames. This bit
+                                                  *   must be set to 0 for correct operation with 802.3br, and
+                                                  *   can be set to 1 when 802.3br is not enabled to avoid false
+                                                  *   detection of SMDs.                                                        */
+            __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
+                                                  *   frames is enabled. When set to 1, the frame contents and
+                                                  *   frame length checks are also performed on these frames.
+                                                  *   The mCRC is always checked regardless of the value of this
+                                                  *   register. This bit must be set to 0 to be compliant with
+                                                  *   the functionality described in IEEE 802.3br.                              */
+            __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for transmitted frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for received frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            uint32_t : 11;
+        } BR_CONTROL_P0_b;
+    };
+    __IM uint32_t RESERVED27[2];
+
+    union
+    {
+        __IM uint32_t AFRAMESTRANSMITTEDOK_P0; /*!< (@ 0x00000868) Port 0 MAC Transmitted Valid Frame Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                *   Transmitted, including pause.                                             */
+        } AFRAMESTRANSMITTEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMESRECEIVEDOK_P0;  /*!< (@ 0x0000086C) Port 0 MAC Received Valid Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                              *   Received, including pause.                                                */
+        } AFRAMESRECEIVEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P0; /*!< (@ 0x00000870) Port 0 MAC FCS Error Frame Count Register (n
+                                                     *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                     *   Length but CRC error.                                                     */
+        } AFRAMECHECKSEQUENCEERRORS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AALIGNMENTERRORS_P0;   /*!< (@ 0x00000874) Port 0 MAC Alignment Error Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
+                                              *   of Nibbles (MII) Received.                                                */
+        } AALIGNMENTERRORS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSTRANSMITTEDOK_P0; /*!< (@ 0x00000878) Port 0 MAC Transmitted Valid Frame Octets Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                                *   only) of MAC Valid Transmitted.                                           */
+        } AOCTETSTRANSMITTEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSRECEIVEDOK_P0;   /*!< (@ 0x0000087C) Port 0 MAC Received Valid Frame Octets Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                               *   only) of MAC Valid Received.                                              */
+        } AOCTETSRECEIVEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ATXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000880) Port 0 MAC Transmitted Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Transmitted.                                                        */
+        } ATXPAUSEMACCTRLFRAMES_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ARXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000884) Port 0 MAC Received Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Received.                                                           */
+        } ARXPAUSEMACCTRLFRAMES_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINERRORS_P0;       /*!< (@ 0x00000888) Port 0 MAC Input Error Count Register (n = 0
+                                            *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
+                                            *   During Reception such as CRC, Length, PHY Error, RX FIFO
+                                            *   Overflow.                                                                 */
+        } IFINERRORS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTERRORS_P0;       /*!< (@ 0x0000088C) Port 0 MAC Output Error Count Register (n = 0
+                                             *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
+                                             *   Transmitted with PHY error.                                               */
+        } IFOUTERRORS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINUCASTPKTS_P0;      /*!< (@ 0x00000890) Port 0 MAC Received Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINUCASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINMULTICASTPKTS_P0;  /*!< (@ 0x00000894) Port 0 MAC Received Multicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINMULTICASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINBROADCASTPKTS_P0;  /*!< (@ 0x00000898) Port 0 MAC Received Broadcast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Received.                                                     */
+        } IFINBROADCASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTDISCARDS_P0;     /*!< (@ 0x0000089C) Port 0 MAC Discarded Outbound Frame Count Register
+                                             *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
+        } IFOUTDISCARDS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTUCASTPKTS_P0;     /*!< (@ 0x000008A0) Port 0 MAC Transmitted Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTUCASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTMULTICASTPKTS_P0; /*!< (@ 0x000008A4) Port 0 MAC Transmitted Multicast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTMULTICASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTBROADCASTPKTS_P0; /*!< (@ 0x000008A8) Port 0 MAC Transmitted Broadcast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTBROADCASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSDROPEVENTS_P0; /*!< (@ 0x000008AC) Port 0 MAC Dropped Frame Count Register (n =
+                                                *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
+                                                *   Full at frame start.                                                      */
+        } ETHERSTATSDROPEVENTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOCTETS_P0; /*!< (@ 0x000008B0) Port 0 MAC All Frame Octets Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
+        } ETHERSTATSOCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS_P0; /*!< (@ 0x000008B4) Port 0 MAC All Frame Count Register (n = 0 to
+                                          *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
+        } ETHERSTATSPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P0; /*!< (@ 0x000008B8) Port 0 MAC Too Short Frame Count Register (n
+                                                   *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                                   *   Good CRC.                                                                 */
+        } ETHERSTATSUNDERSIZEPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOVERSIZEPKTS_P0; /*!< (@ 0x000008BC) Port 0 MAC Too Long Frame Count Register (n =
+                                                  *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                                  *   Good CRC.                                                                 */
+        } ETHERSTATSOVERSIZEPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS64OCTETS_P0; /*!< (@ 0x000008C0) Port 0 MAC 64 Octets Frame Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                  *   Good and Bad (Packet Size: 64 bytes).                                     */
+        } ETHERSTATSPKTS64OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P0; /*!< (@ 0x000008C4) Port 0 MAC 65 to 127 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                       *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
+        } ETHERSTATSPKTS65TO127OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P0; /*!< (@ 0x000008C8) Port 0 MAC 128 to 255 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
+        } ETHERSTATSPKTS128TO255OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P0; /*!< (@ 0x000008CC) Port 0 MAC 256 to 511 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
+        } ETHERSTATSPKTS256TO511OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P0; /*!< (@ 0x000008D0) Port 0 MAC 512 to 1023 Octets Frame Count Register
+                                                         *              (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                         *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
+        } ETHERSTATSPKTS512TO1023OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P0; /*!< (@ 0x000008D4) Port 0 MAC 1024 to 1518 Octets Frame Count Register
+                                                          *             (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                          *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
+        } ETHERSTATSPKTS1024TO1518OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P0; /*!< (@ 0x000008D8) Port 0 MAC Over 1519 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
+                                                       *   Good and Bad (Packet Size: over 1519 bytes).                              */
+        } ETHERSTATSPKTS1519TOXOCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSJABBERS_P0; /*!< (@ 0x000008DC) Port 0 MAC Jabbers Frame Count Register (n =
+                                             *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                             *   Bad CRC.                                                                  */
+        } ETHERSTATSJABBERS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSFRAGMENTS_P0; /*!< (@ 0x000008E0) Port 0 MAC Fragment Frame Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                               *   Bad CRC.                                                                  */
+        } ETHERSTATSFRAGMENTS_P0_b;
+    };
+    __IM uint32_t RESERVED28;
+
+    union
+    {
+        __IM uint32_t VLANRECEIVEDOK_P0;     /*!< (@ 0x000008E8) Port 0 MAC Received VLAN Tagged Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Received.                                                   */
+        } VLANRECEIVEDOK_P0_b;
+    };
+    __IM uint32_t RESERVED29[2];
+
+    union
+    {
+        __IM uint32_t VLANTRANSMITTEDOK_P0;  /*!< (@ 0x000008F4) Port 0 MAC Transmitted VLAN Tagged Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Transmitted.                                                */
+        } VLANTRANSMITTEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRAMESRETRANSMITTED_P0; /*!< (@ 0x000008F8) Port 0 MAC Retransmitted Frame Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
+                                               *   Frames that experienced a collision and were retransmitted.               */
+        } FRAMESRETRANSMITTED_P0_b;
+    };
+    __IM uint32_t RESERVED30;
+
+    union
+    {
+        __IM uint32_t STATS_HIWORD_P0;       /*!< (@ 0x00000900) Port 0 MAC Statistics Counter High Word Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
+                                              *   Counter Last Read                                                         */
+        } STATS_HIWORD_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CTRL_P0;   /*!< (@ 0x00000904) Port 0 MAC Statistics Control Register (n = 0
+                                         *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
+            __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
+            uint32_t               : 30;
+        } STATS_CTRL_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUELO_P0;       /*!< (@ 0x00000908) Port 0 MAC Statistics Clear Value Lower Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUELO_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUEHI_P0;       /*!< (@ 0x0000090C) Port 0 MAC Statistics Clear Value Higher Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUEHI_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADEFERRED_P0;        /*!< (@ 0x00000910) Port 0 MAC Deferred Count Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
+                                            *   without collision but was deferred at begin.                              */
+        } ADEFERRED_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AMULTIPLECOLLISIONS_P0;   /*!< (@ 0x00000914) Port 0 MAC Multiple Collision Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                 *   Transmit after multiple collisions.                                       */
+        } AMULTIPLECOLLISIONS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASINGLECOLLISIONS_P0;      /*!< (@ 0x00000918) Port 0 MAC Single Collision Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                  *   Transmit after single collision.                                          */
+        } ASINGLECOLLISIONS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ALATECOLLISIONS_P0;     /*!< (@ 0x0000091C) Port 0 MAC Late Collision Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
+                                               *   Collision. Frame was aborted and not retransmitted.                       */
+        } ALATECOLLISIONS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AEXCESSIVECOLLISIONS_P0; /*!< (@ 0x00000920) Port 0 MAC Excessive Collision Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
+                                                *   due to 16 consecutive collisions.                                         */
+        } AEXCESSIVECOLLISIONS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACARRIERSENSEERRORS_P0; /*!< (@ 0x00000924) Port 0 MAC Carrier Sense Error Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
+                                               *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
+                                               *   asserted.                                                                 */
+        } ACARRIERSENSEERRORS_P0_b;
+    };
+    __IM uint32_t RESERVED31[182];
+
+    union
+    {
+        __IM uint32_t REV_P1;          /*!< (@ 0x00000C00) Port 1 MAC Core Revision (n = 0 to 3)                      */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
+        } REV_P1_b;
+    };
+    __IM uint32_t RESERVED32;
+
+    union
+    {
+        __IOM uint32_t COMMAND_CONFIG_P1;       /*!< (@ 0x00000C08) Port 1 Command Configuration Register (n = 0
+                                                 *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
+            __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
+            __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
+                                                 *   the IMC until the current frame is completed. This can
+                                                 *   cause the IPG between frames to be more than the value
+                                                 *   in TX_IPG_LENGTH.                                                         */
+            __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
+            __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
+            __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
+            uint32_t                    : 1;
+            __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
+            __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
+            __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
+            __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
+                                                 *   full-duplex only (set to 0).                                              */
+            __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
+            uint32_t                     : 1;
+            __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
+            uint32_t                     : 9;
+            __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
+            __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
+            __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
+                                                 *   register.                                                                 */
+            __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
+            __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
+            uint32_t                   : 2;
+            __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
+                                                 *   on transmit and on receive. The value is used when not
+                                                 *   overridden by the PTP auto-response function, pattern matchers
+                                                 *   or force forwarding information in a management tag.                      */
+            uint32_t : 1;
+        } COMMAND_CONFIG_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_0_P1;     /*!< (@ 0x00000C0C) Port 1 MAC Address Register 0 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
+                                           *   byte is bits [7:0]. The MAC address is used on locally
+                                           *   generated frames such as pause frames, peer-delay response.               */
+        } MAC_ADDR_0_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_1_P1;     /*!< (@ 0x00000C10) Port 1 MAC Address Register 1 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
+                                           *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
+            uint32_t : 16;
+        } MAC_ADDR_1_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRM_LENGTH_P1;       /*!< (@ 0x00000C14) Port 1 Maximum Frame Length Register (n = 0 to
+                                             *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
+            uint32_t                  : 18;
+        } FRM_LENGTH_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t PAUSE_QUANT_P1;       /*!< (@ 0x00000C18) Port 1 MAC Pause Quanta (n = 0 to 3)                       */
+
+        struct
+        {
+            __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
+            uint32_t                  : 16;
+        } PAUSE_QUANT_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_LINK_QTRIG_P1;  /*!< (@ 0x00000C1C) Port 1 Trigger Event Configuration Register (n
+                                            *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
+            uint32_t                  : 12;
+            __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
+                                            *   is transmitted from the ports indicated by PORT_MASK. A
+                                            *   single frame is transmitted per indicated port in PORT_MASK
+                                            *   among the queues indicated by QUEUE_MASK.                                 */
+            uint32_t                 : 4;
+            __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
+                                            *   a frame was transmitted. When MODE is set to 0, TRIGGERED
+                                            *   is always 0. This flag clears when the register is written.               */
+            __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
+                                            *   set to 1, the Link Queue Trigger occurs only if the DLR
+                                            *   state machine is in the NORMAL or FAULT state.                            */
+            __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
+                                            *   This is to prevent sending multiple frames due to link
+                                            *   flapping.                                                                 */
+            __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
+                                            *   When the link status (phy_link) transitions from 1 ->
+                                            *   0, a trigger event is generated to the memory controller
+                                            *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
+        } MAC_LINK_QTRIG_P1_b;
+    };
+    __IM uint32_t RESERVED33[4];
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY1_P1;  /*!< (@ 0x00000C30) Port 1 PTP Clock Identity 1 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
+            __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
+            __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
+            __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
+        } PTPCLOCKIDENTITY1_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY2_P1;  /*!< (@ 0x00000C34) Port 1 PTP Clock Identity 2 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
+            __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
+            __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
+            __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
+        } PTPCLOCKIDENTITY2_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPAUTORESPONSE_P1; /*!< (@ 0x00000C38) Port 1 PTP Auto Response Register (n = 0 to 2)             */
+
+        struct
+        {
+            __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
+            __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
+            uint32_t                : 14;
+            __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
+            __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
+        } PTPAUTORESPONSE_P1_b;
+    };
+    __IM uint32_t RESERVED34;
+
+    union
+    {
+        __IOM uint32_t STATUS_P1;          /*!< (@ 0x00000C40) Port 1 Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
+            __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
+            __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
+            __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
+                                            *   never occur during normal operation.                                      */
+            __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
+                                            *   to complete in time before the next frame was received
+                                            *   at the port. This should never occur under normal operation.
+                                            *   The cause could be from IPG violations in the received
+                                            *   frames.                                                                   */
+            __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
+                                            *   to clause 30.14.1.2 of the 802.3br specification                          */
+            uint32_t : 23;
+        } STATUS_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TX_IPG_LENGTH_P1;      /*!< (@ 0x00000C44) Port 1 Transmit IPG Length Register (n = 0 to
+                                               *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
+                                               *   are in the range of 8 to 31.                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
+            uint32_t                  : 11;
+        } TX_IPG_LENGTH_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_CTL_STAT_P1;        /*!< (@ 0x00000C48) Port 1 MAC EEE Functions Control and Status (n
+                                                *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
+            __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
+            __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
+            uint32_t                    : 5;
+            __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
+            __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
+            __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
+            __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
+                                                *   available for transmission.                                               */
+            __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
+            uint32_t                      : 3;
+            __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
+            __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
+                                                *   MAC                                                                       */
+            __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
+            uint32_t                   : 1;
+            __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
+            uint32_t                   : 11;
+        } EEE_CTL_STAT_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_IDLE_TIME_P1;       /*!< (@ 0x00000C4C) Port 1 EEE Idle Time Register (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
+                                                *   of LPI begins. A 32-bit value in steps of 32 switch operating
+                                                *   clock cycles. A value of 0 disables the timer. The value
+                                                *   must be set to 1 less count.                                              */
+        } EEE_IDLE_TIME_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_TWSYS_TIME_P1;      /*!< (@ 0x00000C50) Port 1 EEE Wake Up Time Register (n = 0 to 2)              */
+
+        struct
+        {
+            __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
+                                                *   to begin transmitting the first frame again. A 32-bit value
+                                                *   in steps of switch operating clock cycles. A value of 0
+                                                *   disables the timer. The value must be set to 1 less count.                */
+        } EEE_TWSYS_TIME_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IDLE_SLOPE_P1;       /*!< (@ 0x00000C54) Port 1 MAC Traffic Shaper Bandwidth Control                */
+
+        struct
+        {
+            __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
+            uint32_t                  : 21;
+        } IDLE_SLOPE_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CT_DELAY_P1;      /*!< (@ 0x00000C58) Port 1 Cut-Through Delay Indication Register               */
+
+        struct
+        {
+            __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
+                                          *   of the MII PHY interface)                                                 */
+            uint32_t : 23;
+        } CT_DELAY_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BR_CONTROL_P1;            /*!< (@ 0x00000C5C) Port 1 802.3br Frame Configuration Register                */
+
+        struct
+        {
+            __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
+            __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
+                                                  *   preemption operation.                                                     */
+            __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
+                                                  *   frames.                                                                   */
+            uint32_t                      : 1;
+            __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
+            uint32_t                      : 2;
+            __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
+            uint32_t                      : 1;
+            __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
+                                                  *   except the SFD are 0x55. When set to 0, only the last 2
+                                                  *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
+                                                  *   It is recommended to set this bit to 1 to comply with the
+                                                  *   802.3br specification. This bit must be set to 0 if only
+                                                  *   non-802.3br traffic is expected (for example, normal Ethernet
+                                                  *   traffic) and if custom preamble is used.                                  */
+            __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
+                                                  *   SMDs and assumes all frames are express frames. This bit
+                                                  *   must be set to 0 for correct operation with 802.3br, and
+                                                  *   can be set to 1 when 802.3br is not enabled to avoid false
+                                                  *   detection of SMDs.                                                        */
+            __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
+                                                  *   frames is enabled. When set to 1, the frame contents and
+                                                  *   frame length checks are also performed on these frames.
+                                                  *   The mCRC is always checked regardless of the value of this
+                                                  *   register. This bit must be set to 0 to be compliant with
+                                                  *   the functionality described in IEEE 802.3br.                              */
+            __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for transmitted frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for received frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            uint32_t : 11;
+        } BR_CONTROL_P1_b;
+    };
+    __IM uint32_t RESERVED35[2];
+
+    union
+    {
+        __IM uint32_t AFRAMESTRANSMITTEDOK_P1; /*!< (@ 0x00000C68) Port 1 MAC Transmitted Valid Frame Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                *   Transmitted, including pause.                                             */
+        } AFRAMESTRANSMITTEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMESRECEIVEDOK_P1;  /*!< (@ 0x00000C6C) Port 1 MAC Received Valid Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                              *   Received, including pause.                                                */
+        } AFRAMESRECEIVEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P1; /*!< (@ 0x00000C70) Port 1 MAC FCS Error Frame Count Register (n
+                                                     *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                     *   Length but CRC error.                                                     */
+        } AFRAMECHECKSEQUENCEERRORS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AALIGNMENTERRORS_P1;   /*!< (@ 0x00000C74) Port 1 MAC Alignment Error Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
+                                              *   of Nibbles (MII) Received.                                                */
+        } AALIGNMENTERRORS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSTRANSMITTEDOK_P1; /*!< (@ 0x00000C78) Port 1 MAC Transmitted Valid Frame Octets Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                                *   only) of MAC Valid Transmitted.                                           */
+        } AOCTETSTRANSMITTEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSRECEIVEDOK_P1;   /*!< (@ 0x00000C7C) Port 1 MAC Received Valid Frame Octets Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                               *   only) of MAC Valid Received.                                              */
+        } AOCTETSRECEIVEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ATXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C80) Port 1 MAC Transmitted Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Transmitted.                                                        */
+        } ATXPAUSEMACCTRLFRAMES_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ARXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C84) Port 1 MAC Received Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Received.                                                           */
+        } ARXPAUSEMACCTRLFRAMES_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINERRORS_P1;       /*!< (@ 0x00000C88) Port 1 MAC Input Error Count Register (n = 0
+                                            *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
+                                            *   During Reception such as CRC, Length, PHY Error, RX FIFO
+                                            *   Overflow.                                                                 */
+        } IFINERRORS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTERRORS_P1;       /*!< (@ 0x00000C8C) Port 1 MAC Output Error Count Register (n = 0
+                                             *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
+                                             *   Transmitted with PHY error.                                               */
+        } IFOUTERRORS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINUCASTPKTS_P1;      /*!< (@ 0x00000C90) Port 1 MAC Received Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINUCASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINMULTICASTPKTS_P1;  /*!< (@ 0x00000C94) Port 1 MAC Received Multicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINMULTICASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINBROADCASTPKTS_P1;  /*!< (@ 0x00000C98) Port 1 MAC Received Broadcast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Received.                                                     */
+        } IFINBROADCASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTDISCARDS_P1;     /*!< (@ 0x00000C9C) Port 1 MAC Discarded Outbound Frame Count Register
+                                             *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
+        } IFOUTDISCARDS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTUCASTPKTS_P1;     /*!< (@ 0x00000CA0) Port 1 MAC Transmitted Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTUCASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTMULTICASTPKTS_P1; /*!< (@ 0x00000CA4) Port 1 MAC Transmitted Multicast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTMULTICASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTBROADCASTPKTS_P1; /*!< (@ 0x00000CA8) Port 1 MAC Transmitted Broadcast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTBROADCASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSDROPEVENTS_P1; /*!< (@ 0x00000CAC) Port 1 MAC Dropped Frame Count Register (n =
+                                                *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
+                                                *   Full at frame start.                                                      */
+        } ETHERSTATSDROPEVENTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOCTETS_P1; /*!< (@ 0x00000CB0) Port 1 MAC All Frame Octets Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
+        } ETHERSTATSOCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS_P1; /*!< (@ 0x00000CB4) Port 1 MAC All Frame Count Register (n = 0 to
+                                          *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
+        } ETHERSTATSPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P1; /*!< (@ 0x00000CB8) Port 1 MAC Too Short Frame Count Register (n
+                                                   *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                                   *   Good CRC.                                                                 */
+        } ETHERSTATSUNDERSIZEPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOVERSIZEPKTS_P1; /*!< (@ 0x00000CBC) Port 1 MAC Too Long Frame Count Register (n =
+                                                  *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                                  *   Good CRC.                                                                 */
+        } ETHERSTATSOVERSIZEPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS64OCTETS_P1; /*!< (@ 0x00000CC0) Port 1 MAC 64 Octets Frame Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                  *   Good and Bad (Packet Size: 64 bytes).                                     */
+        } ETHERSTATSPKTS64OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P1; /*!< (@ 0x00000CC4) Port 1 MAC 65 to 127 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                       *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
+        } ETHERSTATSPKTS65TO127OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P1; /*!< (@ 0x00000CC8) Port 1 MAC 128 to 255 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
+        } ETHERSTATSPKTS128TO255OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P1; /*!< (@ 0x00000CCC) Port 1 MAC 256 to 511 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
+        } ETHERSTATSPKTS256TO511OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P1; /*!< (@ 0x00000CD0) Port 1 MAC 512 to 1023 Octets Frame Count Register
+                                                         *              (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                         *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
+        } ETHERSTATSPKTS512TO1023OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P1; /*!< (@ 0x00000CD4) Port 1 MAC 1024 to 1518 Octets Frame Count Register
+                                                          *             (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                          *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
+        } ETHERSTATSPKTS1024TO1518OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P1; /*!< (@ 0x00000CD8) Port 1 MAC Over 1519 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
+                                                       *   Good and Bad (Packet Size: over 1519 bytes).                              */
+        } ETHERSTATSPKTS1519TOXOCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSJABBERS_P1; /*!< (@ 0x00000CDC) Port 1 MAC Jabbers Frame Count Register (n =
+                                             *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                             *   Bad CRC.                                                                  */
+        } ETHERSTATSJABBERS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSFRAGMENTS_P1; /*!< (@ 0x00000CE0) Port 1 MAC Fragment Frame Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                               *   Bad CRC.                                                                  */
+        } ETHERSTATSFRAGMENTS_P1_b;
+    };
+    __IM uint32_t RESERVED36;
+
+    union
+    {
+        __IM uint32_t VLANRECEIVEDOK_P1;     /*!< (@ 0x00000CE8) Port 1 MAC Received VLAN Tagged Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Received.                                                   */
+        } VLANRECEIVEDOK_P1_b;
+    };
+    __IM uint32_t RESERVED37[2];
+
+    union
+    {
+        __IM uint32_t VLANTRANSMITTEDOK_P1;  /*!< (@ 0x00000CF4) Port 1 MAC Transmitted VLAN Tagged Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Transmitted.                                                */
+        } VLANTRANSMITTEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRAMESRETRANSMITTED_P1; /*!< (@ 0x00000CF8) Port 1 MAC Retransmitted Frame Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
+                                               *   Frames that experienced a collision and were retransmitted.               */
+        } FRAMESRETRANSMITTED_P1_b;
+    };
+    __IM uint32_t RESERVED38;
+
+    union
+    {
+        __IM uint32_t STATS_HIWORD_P1;       /*!< (@ 0x00000D00) Port 1 MAC Statistics Counter High Word Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
+                                              *   Counter Last Read                                                         */
+        } STATS_HIWORD_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CTRL_P1;   /*!< (@ 0x00000D04) Port 1 MAC Statistics Control Register (n = 0
+                                         *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
+            __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
+            uint32_t               : 30;
+        } STATS_CTRL_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUELO_P1;       /*!< (@ 0x00000D08) Port 1 MAC Statistics Clear Value Lower Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUELO_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUEHI_P1;       /*!< (@ 0x00000D0C) Port 1 MAC Statistics Clear Value Higher Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUEHI_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADEFERRED_P1;        /*!< (@ 0x00000D10) Port 1 MAC Deferred Count Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
+                                            *   without collision but was deferred at begin.                              */
+        } ADEFERRED_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AMULTIPLECOLLISIONS_P1;   /*!< (@ 0x00000D14) Port 1 MAC Multiple Collision Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                 *   Transmit after multiple collisions.                                       */
+        } AMULTIPLECOLLISIONS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASINGLECOLLISIONS_P1;      /*!< (@ 0x00000D18) Port 1 MAC Single Collision Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                  *   Transmit after single collision.                                          */
+        } ASINGLECOLLISIONS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ALATECOLLISIONS_P1;     /*!< (@ 0x00000D1C) Port 1 MAC Late Collision Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
+                                               *   Collision. Frame was aborted and not retransmitted.                       */
+        } ALATECOLLISIONS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AEXCESSIVECOLLISIONS_P1; /*!< (@ 0x00000D20) Port 1 MAC Excessive Collision Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
+                                                *   due to 16 consecutive collisions.                                         */
+        } AEXCESSIVECOLLISIONS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACARRIERSENSEERRORS_P1; /*!< (@ 0x00000D24) Port 1 MAC Carrier Sense Error Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
+                                               *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
+                                               *   asserted.                                                                 */
+        } ACARRIERSENSEERRORS_P1_b;
+    };
+    __IM uint32_t RESERVED39[182];
+
+    union
+    {
+        __IM uint32_t REV_P2;          /*!< (@ 0x00001000) Port 2 MAC Core Revision (n = 0 to 3)                      */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
+        } REV_P2_b;
+    };
+    __IM uint32_t RESERVED40;
+
+    union
+    {
+        __IOM uint32_t COMMAND_CONFIG_P2;       /*!< (@ 0x00001008) Port 2 Command Configuration Register (n = 0
+                                                 *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
+            __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
+            __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
+                                                 *   the IMC until the current frame is completed. This can
+                                                 *   cause the IPG between frames to be more than the value
+                                                 *   in TX_IPG_LENGTH.                                                         */
+            __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
+            __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
+            __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
+            uint32_t                    : 1;
+            __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
+            __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
+            __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
+            __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
+                                                 *   full-duplex only (set to 0).                                              */
+            __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
+            uint32_t                     : 1;
+            __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
+            uint32_t                     : 9;
+            __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
+            __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
+            __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
+                                                 *   register.                                                                 */
+            __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
+            __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
+            uint32_t                   : 2;
+            __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
+                                                 *   on transmit and on receive. The value is used when not
+                                                 *   overridden by the PTP auto-response function, pattern matchers
+                                                 *   or force forwarding information in a management tag.                      */
+            uint32_t : 1;
+        } COMMAND_CONFIG_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_0_P2;     /*!< (@ 0x0000100C) Port 2 MAC Address Register 0 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
+                                           *   byte is bits [7:0]. The MAC address is used on locally
+                                           *   generated frames such as pause frames, peer-delay response.               */
+        } MAC_ADDR_0_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_1_P2;     /*!< (@ 0x00001010) Port 2 MAC Address Register 1 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
+                                           *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
+            uint32_t : 16;
+        } MAC_ADDR_1_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRM_LENGTH_P2;       /*!< (@ 0x00001014) Port 2 Maximum Frame Length Register (n = 0 to
+                                             *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
+            uint32_t                  : 18;
+        } FRM_LENGTH_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t PAUSE_QUANT_P2;       /*!< (@ 0x00001018) Port 2 MAC Pause Quanta (n = 0 to 3)                       */
+
+        struct
+        {
+            __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
+            uint32_t                  : 16;
+        } PAUSE_QUANT_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_LINK_QTRIG_P2;  /*!< (@ 0x0000101C) Port 2 Trigger Event Configuration Register (n
+                                            *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
+            uint32_t                  : 12;
+            __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
+                                            *   is transmitted from the ports indicated by PORT_MASK. A
+                                            *   single frame is transmitted per indicated port in PORT_MASK
+                                            *   among the queues indicated by QUEUE_MASK.                                 */
+            uint32_t                 : 4;
+            __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
+                                            *   a frame was transmitted. When MODE is set to 0, TRIGGERED
+                                            *   is always 0. This flag clears when the register is written.               */
+            __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
+                                            *   set to 1, the Link Queue Trigger occurs only if the DLR
+                                            *   state machine is in the NORMAL or FAULT state.                            */
+            __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
+                                            *   This is to prevent sending multiple frames due to link
+                                            *   flapping.                                                                 */
+            __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
+                                            *   When the link status (phy_link) transitions from 1 ->
+                                            *   0, a trigger event is generated to the memory controller
+                                            *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
+        } MAC_LINK_QTRIG_P2_b;
+    };
+    __IM uint32_t RESERVED41[4];
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY1_P2;  /*!< (@ 0x00001030) Port 2 PTP Clock Identity 1 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
+            __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
+            __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
+            __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
+        } PTPCLOCKIDENTITY1_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY2_P2;  /*!< (@ 0x00001034) Port 2 PTP Clock Identity 2 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
+            __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
+            __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
+            __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
+        } PTPCLOCKIDENTITY2_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPAUTORESPONSE_P2; /*!< (@ 0x00001038) Port 2 PTP Auto Response Register (n = 0 to 2)             */
+
+        struct
+        {
+            __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
+            __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
+            uint32_t                : 14;
+            __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
+            __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
+        } PTPAUTORESPONSE_P2_b;
+    };
+    __IM uint32_t RESERVED42;
+
+    union
+    {
+        __IOM uint32_t STATUS_P2;          /*!< (@ 0x00001040) Port 2 Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
+            __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
+            __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
+            __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
+                                            *   never occur during normal operation.                                      */
+            __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
+                                            *   to complete in time before the next frame was received
+                                            *   at the port. This should never occur under normal operation.
+                                            *   The cause could be from IPG violations in the received
+                                            *   frames.                                                                   */
+            __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
+                                            *   to clause 30.14.1.2 of the 802.3br specification                          */
+            uint32_t : 23;
+        } STATUS_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TX_IPG_LENGTH_P2;      /*!< (@ 0x00001044) Port 2 Transmit IPG Length Register (n = 0 to
+                                               *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
+                                               *   are in the range of 8 to 31.                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
+            uint32_t                  : 11;
+        } TX_IPG_LENGTH_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_CTL_STAT_P2;        /*!< (@ 0x00001048) Port 2 MAC EEE Functions Control and Status (n
+                                                *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
+            __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
+            __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
+            uint32_t                    : 5;
+            __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
+            __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
+            __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
+            __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
+                                                *   available for transmission.                                               */
+            __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
+            uint32_t                      : 3;
+            __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
+            __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
+                                                *   MAC                                                                       */
+            __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
+            uint32_t                   : 1;
+            __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
+            uint32_t                   : 11;
+        } EEE_CTL_STAT_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_IDLE_TIME_P2;       /*!< (@ 0x0000104C) Port 2 EEE Idle Time Register (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
+                                                *   of LPI begins. A 32-bit value in steps of 32 switch operating
+                                                *   clock cycles. A value of 0 disables the timer. The value
+                                                *   must be set to 1 less count.                                              */
+        } EEE_IDLE_TIME_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_TWSYS_TIME_P2;      /*!< (@ 0x00001050) Port 2 EEE Wake Up Time Register (n = 0 to 2)              */
+
+        struct
+        {
+            __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
+                                                *   to begin transmitting the first frame again. A 32-bit value
+                                                *   in steps of switch operating clock cycles. A value of 0
+                                                *   disables the timer. The value must be set to 1 less count.                */
+        } EEE_TWSYS_TIME_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IDLE_SLOPE_P2;       /*!< (@ 0x00001054) Port 2 MAC Traffic Shaper Bandwidth Control                */
+
+        struct
+        {
+            __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
+            uint32_t                  : 21;
+        } IDLE_SLOPE_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CT_DELAY_P2;      /*!< (@ 0x00001058) Port 2 Cut-Through Delay Indication Register               */
+
+        struct
+        {
+            __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
+                                          *   of the MII PHY interface)                                                 */
+            uint32_t : 23;
+        } CT_DELAY_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BR_CONTROL_P2;            /*!< (@ 0x0000105C) Port 2 802.3br Frame Configuration Register                */
+
+        struct
+        {
+            __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
+            __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
+                                                  *   preemption operation.                                                     */
+            __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
+                                                  *   frames.                                                                   */
+            uint32_t                      : 1;
+            __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
+            uint32_t                      : 2;
+            __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
+            uint32_t                      : 1;
+            __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
+                                                  *   except the SFD are 0x55. When set to 0, only the last 2
+                                                  *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
+                                                  *   It is recommended to set this bit to 1 to comply with the
+                                                  *   802.3br specification. This bit must be set to 0 if only
+                                                  *   non-802.3br traffic is expected (for example, normal Ethernet
+                                                  *   traffic) and if custom preamble is used.                                  */
+            __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
+                                                  *   SMDs and assumes all frames are express frames. This bit
+                                                  *   must be set to 0 for correct operation with 802.3br, and
+                                                  *   can be set to 1 when 802.3br is not enabled to avoid false
+                                                  *   detection of SMDs.                                                        */
+            __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
+                                                  *   frames is enabled. When set to 1, the frame contents and
+                                                  *   frame length checks are also performed on these frames.
+                                                  *   The mCRC is always checked regardless of the value of this
+                                                  *   register. This bit must be set to 0 to be compliant with
+                                                  *   the functionality described in IEEE 802.3br.                              */
+            __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for transmitted frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for received frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            uint32_t : 11;
+        } BR_CONTROL_P2_b;
+    };
+    __IM uint32_t RESERVED43[2];
+
+    union
+    {
+        __IM uint32_t AFRAMESTRANSMITTEDOK_P2; /*!< (@ 0x00001068) Port 2 MAC Transmitted Valid Frame Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                *   Transmitted, including pause.                                             */
+        } AFRAMESTRANSMITTEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMESRECEIVEDOK_P2;  /*!< (@ 0x0000106C) Port 2 MAC Received Valid Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                              *   Received, including pause.                                                */
+        } AFRAMESRECEIVEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P2; /*!< (@ 0x00001070) Port 2 MAC FCS Error Frame Count Register (n
+                                                     *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                     *   Length but CRC error.                                                     */
+        } AFRAMECHECKSEQUENCEERRORS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AALIGNMENTERRORS_P2;   /*!< (@ 0x00001074) Port 2 MAC Alignment Error Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
+                                              *   of Nibbles (MII) Received.                                                */
+        } AALIGNMENTERRORS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSTRANSMITTEDOK_P2; /*!< (@ 0x00001078) Port 2 MAC Transmitted Valid Frame Octets Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                                *   only) of MAC Valid Transmitted.                                           */
+        } AOCTETSTRANSMITTEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSRECEIVEDOK_P2;   /*!< (@ 0x0000107C) Port 2 MAC Received Valid Frame Octets Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                               *   only) of MAC Valid Received.                                              */
+        } AOCTETSRECEIVEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ATXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001080) Port 2 MAC Transmitted Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Transmitted.                                                        */
+        } ATXPAUSEMACCTRLFRAMES_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ARXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001084) Port 2 MAC Received Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Received.                                                           */
+        } ARXPAUSEMACCTRLFRAMES_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINERRORS_P2;       /*!< (@ 0x00001088) Port 2 MAC Input Error Count Register (n = 0
+                                            *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
+                                            *   During Reception such as CRC, Length, PHY Error, RX FIFO
+                                            *   Overflow.                                                                 */
+        } IFINERRORS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTERRORS_P2;       /*!< (@ 0x0000108C) Port 2 MAC Output Error Count Register (n = 0
+                                             *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
+                                             *   Transmitted with PHY error.                                               */
+        } IFOUTERRORS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINUCASTPKTS_P2;      /*!< (@ 0x00001090) Port 2 MAC Received Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINUCASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINMULTICASTPKTS_P2;  /*!< (@ 0x00001094) Port 2 MAC Received Multicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINMULTICASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINBROADCASTPKTS_P2;  /*!< (@ 0x00001098) Port 2 MAC Received Broadcast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Received.                                                     */
+        } IFINBROADCASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTDISCARDS_P2;     /*!< (@ 0x0000109C) Port 2 MAC Discarded Outbound Frame Count Register
+                                             *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
+        } IFOUTDISCARDS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTUCASTPKTS_P2;     /*!< (@ 0x000010A0) Port 2 MAC Transmitted Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTUCASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTMULTICASTPKTS_P2; /*!< (@ 0x000010A4) Port 2 MAC Transmitted Multicast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTMULTICASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTBROADCASTPKTS_P2; /*!< (@ 0x000010A8) Port 2 MAC Transmitted Broadcast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTBROADCASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSDROPEVENTS_P2; /*!< (@ 0x000010AC) Port 2 MAC Dropped Frame Count Register (n =
+                                                *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
+                                                *   Full at frame start.                                                      */
+        } ETHERSTATSDROPEVENTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOCTETS_P2; /*!< (@ 0x000010B0) Port 2 MAC All Frame Octets Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
+        } ETHERSTATSOCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS_P2; /*!< (@ 0x000010B4) Port 2 MAC All Frame Count Register (n = 0 to
+                                          *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
+        } ETHERSTATSPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P2; /*!< (@ 0x000010B8) Port 2 MAC Too Short Frame Count Register (n
+                                                   *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                                   *   Good CRC.                                                                 */
+        } ETHERSTATSUNDERSIZEPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOVERSIZEPKTS_P2; /*!< (@ 0x000010BC) Port 2 MAC Too Long Frame Count Register (n =
+                                                  *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                                  *   Good CRC.                                                                 */
+        } ETHERSTATSOVERSIZEPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS64OCTETS_P2; /*!< (@ 0x000010C0) Port 2 MAC 64 Octets Frame Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                  *   Good and Bad (Packet Size: 64 bytes).                                     */
+        } ETHERSTATSPKTS64OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P2; /*!< (@ 0x000010C4) Port 2 MAC 65 to 127 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                       *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
+        } ETHERSTATSPKTS65TO127OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P2; /*!< (@ 0x000010C8) Port 2 MAC 128 to 255 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
+        } ETHERSTATSPKTS128TO255OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P2; /*!< (@ 0x000010CC) Port 2 MAC 256 to 511 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
+        } ETHERSTATSPKTS256TO511OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P2; /*!< (@ 0x000010D0) Port 2 MAC 512 to 1023 Octets Frame Count Register
+                                                         *              (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                         *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
+        } ETHERSTATSPKTS512TO1023OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P2; /*!< (@ 0x000010D4) Port 2 MAC 1024 to 1518 Octets Frame Count Register
+                                                          *             (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                          *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
+        } ETHERSTATSPKTS1024TO1518OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P2; /*!< (@ 0x000010D8) Port 2 MAC Over 1519 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
+                                                       *   Good and Bad (Packet Size: over 1519 bytes).                              */
+        } ETHERSTATSPKTS1519TOXOCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSJABBERS_P2; /*!< (@ 0x000010DC) Port 2 MAC Jabbers Frame Count Register (n =
+                                             *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                             *   Bad CRC.                                                                  */
+        } ETHERSTATSJABBERS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSFRAGMENTS_P2; /*!< (@ 0x000010E0) Port 2 MAC Fragment Frame Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                               *   Bad CRC.                                                                  */
+        } ETHERSTATSFRAGMENTS_P2_b;
+    };
+    __IM uint32_t RESERVED44;
+
+    union
+    {
+        __IM uint32_t VLANRECEIVEDOK_P2;     /*!< (@ 0x000010E8) Port 2 MAC Received VLAN Tagged Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Received.                                                   */
+        } VLANRECEIVEDOK_P2_b;
+    };
+    __IM uint32_t RESERVED45[2];
+
+    union
+    {
+        __IM uint32_t VLANTRANSMITTEDOK_P2;  /*!< (@ 0x000010F4) Port 2 MAC Transmitted VLAN Tagged Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Transmitted.                                                */
+        } VLANTRANSMITTEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRAMESRETRANSMITTED_P2; /*!< (@ 0x000010F8) Port 2 MAC Retransmitted Frame Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
+                                               *   Frames that experienced a collision and were retransmitted.               */
+        } FRAMESRETRANSMITTED_P2_b;
+    };
+    __IM uint32_t RESERVED46;
+
+    union
+    {
+        __IM uint32_t STATS_HIWORD_P2;       /*!< (@ 0x00001100) Port 2 MAC Statistics Counter High Word Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
+                                              *   Counter Last Read                                                         */
+        } STATS_HIWORD_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CTRL_P2;   /*!< (@ 0x00001104) Port 2 MAC Statistics Control Register (n = 0
+                                         *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
+            __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
+            uint32_t               : 30;
+        } STATS_CTRL_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUELO_P2;       /*!< (@ 0x00001108) Port 2 MAC Statistics Clear Value Lower Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUELO_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUEHI_P2;       /*!< (@ 0x0000110C) Port 2 MAC Statistics Clear Value Higher Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUEHI_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADEFERRED_P2;        /*!< (@ 0x00001110) Port 2 MAC Deferred Count Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
+                                            *   without collision but was deferred at begin.                              */
+        } ADEFERRED_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AMULTIPLECOLLISIONS_P2;   /*!< (@ 0x00001114) Port 2 MAC Multiple Collision Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                 *   Transmit after multiple collisions.                                       */
+        } AMULTIPLECOLLISIONS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASINGLECOLLISIONS_P2;      /*!< (@ 0x00001118) Port 2 MAC Single Collision Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                  *   Transmit after single collision.                                          */
+        } ASINGLECOLLISIONS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ALATECOLLISIONS_P2;     /*!< (@ 0x0000111C) Port 2 MAC Late Collision Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
+                                               *   Collision. Frame was aborted and not retransmitted.                       */
+        } ALATECOLLISIONS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AEXCESSIVECOLLISIONS_P2; /*!< (@ 0x00001120) Port 2 MAC Excessive Collision Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
+                                                *   due to 16 consecutive collisions.                                         */
+        } AEXCESSIVECOLLISIONS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACARRIERSENSEERRORS_P2; /*!< (@ 0x00001124) Port 2 MAC Carrier Sense Error Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
+                                               *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
+                                               *   asserted.                                                                 */
+        } ACARRIERSENSEERRORS_P2_b;
+    };
+    __IM uint32_t RESERVED47[182];
+
+    union
+    {
+        __IM uint32_t REV_P3;          /*!< (@ 0x00001400) Port 3 MAC Core Revision (n = 0 to 3)                      */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
+        } REV_P3_b;
+    };
+    __IM uint32_t RESERVED48;
+
+    union
+    {
+        __IOM uint32_t COMMAND_CONFIG_P3;       /*!< (@ 0x00001408) Port 3 Command Configuration Register (n = 0
+                                                 *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
+            __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
+            __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
+                                                 *   the IMC until the current frame is completed. This can
+                                                 *   cause the IPG between frames to be more than the value
+                                                 *   in TX_IPG_LENGTH.                                                         */
+            __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
+            __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
+            __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
+            uint32_t                    : 1;
+            __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
+            __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
+            __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
+            __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
+                                                 *   full-duplex only (set to 0).                                              */
+            __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
+            uint32_t                     : 1;
+            __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
+            uint32_t                     : 9;
+            __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
+            __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
+            __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
+                                                 *   register.                                                                 */
+            __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
+            __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
+            uint32_t                   : 2;
+            __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
+                                                 *   on transmit and on receive. The value is used when not
+                                                 *   overridden by the PTP auto-response function, pattern matchers
+                                                 *   or force forwarding information in a management tag.                      */
+            uint32_t : 1;
+        } COMMAND_CONFIG_P3_b;
+    };
+    __IM uint32_t RESERVED49[2];
+
+    union
+    {
+        __IOM uint32_t FRM_LENGTH_P3;       /*!< (@ 0x00001414) Port 3 Maximum Frame Length Register (n = 0 to
+                                             *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
+            uint32_t                  : 18;
+        } FRM_LENGTH_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t PAUSE_QUANT_P3;       /*!< (@ 0x00001418) Port 3 MAC Pause Quanta (n = 0 to 3)                       */
+
+        struct
+        {
+            __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
+            uint32_t                  : 16;
+        } PAUSE_QUANT_P3_b;
+    };
+    __IM uint32_t RESERVED50[9];
+
+    union
+    {
+        __IOM uint32_t STATUS_P3;          /*!< (@ 0x00001440) Port 3 Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
+            __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
+            __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
+            __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
+                                            *   never occur during normal operation.                                      */
+            __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
+                                            *   to complete in time before the next frame was received
+                                            *   at the port. This should never occur under normal operation.
+                                            *   The cause could be from IPG violations in the received
+                                            *   frames.                                                                   */
+            __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
+                                            *   to clause 30.14.1.2 of the 802.3br specification                          */
+            uint32_t : 23;
+        } STATUS_P3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TX_IPG_LENGTH_P3;      /*!< (@ 0x00001444) Port 3 Transmit IPG Length Register (n = 0 to
+                                               *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
+                                               *   are in the range of 8 to 31.                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
+            uint32_t                  : 11;
+        } TX_IPG_LENGTH_P3_b;
+    };
+    __IM uint32_t RESERVED51[3];
+
+    union
+    {
+        __IOM uint32_t IDLE_SLOPE_P3;       /*!< (@ 0x00001454) Port 3 MAC Traffic Shaper Bandwidth Control                */
+
+        struct
+        {
+            __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
+            uint32_t                  : 21;
+        } IDLE_SLOPE_P3_b;
+    };
+    __IM uint32_t RESERVED52[4];
+
+    union
+    {
+        __IM uint32_t AFRAMESTRANSMITTEDOK_P3; /*!< (@ 0x00001468) Port 3 MAC Transmitted Valid Frame Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                *   Transmitted, including pause.                                             */
+        } AFRAMESTRANSMITTEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMESRECEIVEDOK_P3;  /*!< (@ 0x0000146C) Port 3 MAC Received Valid Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                              *   Received, including pause.                                                */
+        } AFRAMESRECEIVEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P3; /*!< (@ 0x00001470) Port 3 MAC FCS Error Frame Count Register (n
+                                                     *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                     *   Length but CRC error.                                                     */
+        } AFRAMECHECKSEQUENCEERRORS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AALIGNMENTERRORS_P3;   /*!< (@ 0x00001474) Port 3 MAC Alignment Error Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
+                                              *   of Nibbles (MII) Received.                                                */
+        } AALIGNMENTERRORS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSTRANSMITTEDOK_P3; /*!< (@ 0x00001478) Port 3 MAC Transmitted Valid Frame Octets Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                                *   only) of MAC Valid Transmitted.                                           */
+        } AOCTETSTRANSMITTEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSRECEIVEDOK_P3;   /*!< (@ 0x0000147C) Port 3 MAC Received Valid Frame Octets Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                               *   only) of MAC Valid Received.                                              */
+        } AOCTETSRECEIVEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ATXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001480) Port 3 MAC Transmitted Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Transmitted.                                                        */
+        } ATXPAUSEMACCTRLFRAMES_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ARXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001484) Port 3 MAC Received Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Received.                                                           */
+        } ARXPAUSEMACCTRLFRAMES_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINERRORS_P3;       /*!< (@ 0x00001488) Port 3 MAC Input Error Count Register (n = 0
+                                            *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
+                                            *   During Reception such as CRC, Length, PHY Error, RX FIFO
+                                            *   Overflow.                                                                 */
+        } IFINERRORS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTERRORS_P3;       /*!< (@ 0x0000148C) Port 3 MAC Output Error Count Register (n = 0
+                                             *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
+                                             *   Transmitted with PHY error.                                               */
+        } IFOUTERRORS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINUCASTPKTS_P3;      /*!< (@ 0x00001490) Port 3 MAC Received Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINUCASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINMULTICASTPKTS_P3;  /*!< (@ 0x00001494) Port 3 MAC Received Multicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINMULTICASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINBROADCASTPKTS_P3;  /*!< (@ 0x00001498) Port 3 MAC Received Broadcast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Received.                                                     */
+        } IFINBROADCASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTDISCARDS_P3;     /*!< (@ 0x0000149C) Port 3 MAC Discarded Outbound Frame Count Register
+                                             *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
+        } IFOUTDISCARDS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTUCASTPKTS_P3;     /*!< (@ 0x000014A0) Port 3 MAC Transmitted Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTUCASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTMULTICASTPKTS_P3; /*!< (@ 0x000014A4) Port 3 MAC Transmitted Multicast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTMULTICASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTBROADCASTPKTS_P3; /*!< (@ 0x000014A8) Port 3 MAC Transmitted Broadcast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTBROADCASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSDROPEVENTS_P3; /*!< (@ 0x000014AC) Port 3 MAC Dropped Frame Count Register (n =
+                                                *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
+                                                *   Full at frame start.                                                      */
+        } ETHERSTATSDROPEVENTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOCTETS_P3; /*!< (@ 0x000014B0) Port 3 MAC All Frame Octets Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
+        } ETHERSTATSOCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS_P3; /*!< (@ 0x000014B4) Port 3 MAC All Frame Count Register (n = 0 to
+                                          *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
+        } ETHERSTATSPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P3; /*!< (@ 0x000014B8) Port 3 MAC Too Short Frame Count Register (n
+                                                   *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                                   *   Good CRC.                                                                 */
+        } ETHERSTATSUNDERSIZEPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOVERSIZEPKTS_P3; /*!< (@ 0x000014BC) Port 3 MAC Too Long Frame Count Register (n =
+                                                  *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                                  *   Good CRC.                                                                 */
+        } ETHERSTATSOVERSIZEPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS64OCTETS_P3; /*!< (@ 0x000014C0) Port 3 MAC 64 Octets Frame Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                  *   Good and Bad (Packet Size: 64 bytes).                                     */
+        } ETHERSTATSPKTS64OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P3; /*!< (@ 0x000014C4) Port 3 MAC 65 to 127 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                       *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
+        } ETHERSTATSPKTS65TO127OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P3; /*!< (@ 0x000014C8) Port 3 MAC 128 to 255 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
+        } ETHERSTATSPKTS128TO255OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P3; /*!< (@ 0x000014CC) Port 3 MAC 256 to 511 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
+        } ETHERSTATSPKTS256TO511OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P3; /*!< (@ 0x000014D0) Port 3 MAC 512 to 1023 Octets Frame Count Register
+                                                         *              (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                         *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
+        } ETHERSTATSPKTS512TO1023OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P3; /*!< (@ 0x000014D4) Port 3 MAC 1024 to 1518 Octets Frame Count Register
+                                                          *             (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                          *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
+        } ETHERSTATSPKTS1024TO1518OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P3; /*!< (@ 0x000014D8) Port 3 MAC Over 1519 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
+                                                       *   Good and Bad (Packet Size: over 1519 bytes).                              */
+        } ETHERSTATSPKTS1519TOXOCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSJABBERS_P3; /*!< (@ 0x000014DC) Port 3 MAC Jabbers Frame Count Register (n =
+                                             *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                             *   Bad CRC.                                                                  */
+        } ETHERSTATSJABBERS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSFRAGMENTS_P3; /*!< (@ 0x000014E0) Port 3 MAC Fragment Frame Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                               *   Bad CRC.                                                                  */
+        } ETHERSTATSFRAGMENTS_P3_b;
+    };
+    __IM uint32_t RESERVED53;
+
+    union
+    {
+        __IM uint32_t VLANRECEIVEDOK_P3;     /*!< (@ 0x000014E8) Port 3 MAC Received VLAN Tagged Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Received.                                                   */
+        } VLANRECEIVEDOK_P3_b;
+    };
+    __IM uint32_t RESERVED54[2];
+
+    union
+    {
+        __IM uint32_t VLANTRANSMITTEDOK_P3;  /*!< (@ 0x000014F4) Port 3 MAC Transmitted VLAN Tagged Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Transmitted.                                                */
+        } VLANTRANSMITTEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRAMESRETRANSMITTED_P3; /*!< (@ 0x000014F8) Port 3 MAC Retransmitted Frame Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
+                                               *   Frames that experienced a collision and were retransmitted.               */
+        } FRAMESRETRANSMITTED_P3_b;
+    };
+    __IM uint32_t RESERVED55;
+
+    union
+    {
+        __IM uint32_t STATS_HIWORD_P3;       /*!< (@ 0x00001500) Port 3 MAC Statistics Counter High Word Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
+                                              *   Counter Last Read                                                         */
+        } STATS_HIWORD_P3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CTRL_P3;   /*!< (@ 0x00001504) Port 3 MAC Statistics Control Register (n = 0
+                                         *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
+            __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
+            uint32_t               : 30;
+        } STATS_CTRL_P3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUELO_P3;       /*!< (@ 0x00001508) Port 3 MAC Statistics Clear Value Lower Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUELO_P3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUEHI_P3;       /*!< (@ 0x0000150C) Port 3 MAC Statistics Clear Value Higher Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUEHI_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADEFERRED_P3;        /*!< (@ 0x00001510) Port 3 MAC Deferred Count Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
+                                            *   without collision but was deferred at begin.                              */
+        } ADEFERRED_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AMULTIPLECOLLISIONS_P3;   /*!< (@ 0x00001514) Port 3 MAC Multiple Collision Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                 *   Transmit after multiple collisions.                                       */
+        } AMULTIPLECOLLISIONS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASINGLECOLLISIONS_P3;      /*!< (@ 0x00001518) Port 3 MAC Single Collision Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                  *   Transmit after single collision.                                          */
+        } ASINGLECOLLISIONS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ALATECOLLISIONS_P3;     /*!< (@ 0x0000151C) Port 3 MAC Late Collision Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
+                                               *   Collision. Frame was aborted and not retransmitted.                       */
+        } ALATECOLLISIONS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AEXCESSIVECOLLISIONS_P3; /*!< (@ 0x00001520) Port 3 MAC Excessive Collision Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
+                                                *   due to 16 consecutive collisions.                                         */
+        } AEXCESSIVECOLLISIONS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACARRIERSENSEERRORS_P3; /*!< (@ 0x00001524) Port 3 MAC Carrier Sense Error Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
+                                               *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
+                                               *   asserted.                                                                 */
+        } ACARRIERSENSEERRORS_P3_b;
+    };
+    __IM uint32_t RESERVED56[694];
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU0;    /*!< (@ 0x00002000) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD0;    /*!< (@ 0x00002004) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU0;    /*!< (@ 0x00002008) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD0;    /*!< (@ 0x0000200C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL0;      /*!< (@ 0x00002010) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM0;      /*!< (@ 0x00002014) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL0;     /*!< (@ 0x00002018) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC0;       /*!< (@ 0x0000201C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC0;      /*!< (@ 0x00002020) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC0;      /*!< (@ 0x00002024) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU1;    /*!< (@ 0x00002028) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD1;    /*!< (@ 0x0000202C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU1;    /*!< (@ 0x00002030) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD1;    /*!< (@ 0x00002034) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL1;      /*!< (@ 0x00002038) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM1;      /*!< (@ 0x0000203C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL1;     /*!< (@ 0x00002040) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC1;       /*!< (@ 0x00002044) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC1;      /*!< (@ 0x00002048) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC1;      /*!< (@ 0x0000204C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU2;    /*!< (@ 0x00002050) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD2;    /*!< (@ 0x00002054) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU2;    /*!< (@ 0x00002058) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD2;    /*!< (@ 0x0000205C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL2;      /*!< (@ 0x00002060) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM2;      /*!< (@ 0x00002064) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL2;     /*!< (@ 0x00002068) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC2;       /*!< (@ 0x0000206C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC2;      /*!< (@ 0x00002070) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC2;      /*!< (@ 0x00002074) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU3;    /*!< (@ 0x00002078) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD3;    /*!< (@ 0x0000207C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU3;    /*!< (@ 0x00002080) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD3;    /*!< (@ 0x00002084) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL3;      /*!< (@ 0x00002088) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM3;      /*!< (@ 0x0000208C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL3;     /*!< (@ 0x00002090) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC3;       /*!< (@ 0x00002094) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC3;      /*!< (@ 0x00002098) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC3;      /*!< (@ 0x0000209C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU4;    /*!< (@ 0x000020A0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD4;    /*!< (@ 0x000020A4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU4;    /*!< (@ 0x000020A8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD4;    /*!< (@ 0x000020AC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL4;      /*!< (@ 0x000020B0) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM4;      /*!< (@ 0x000020B4) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL4;     /*!< (@ 0x000020B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC4;       /*!< (@ 0x000020BC) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC4;      /*!< (@ 0x000020C0) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC4;      /*!< (@ 0x000020C4) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU5;    /*!< (@ 0x000020C8) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD5;    /*!< (@ 0x000020CC) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU5;    /*!< (@ 0x000020D0) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD5;    /*!< (@ 0x000020D4) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL5;      /*!< (@ 0x000020D8) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM5;      /*!< (@ 0x000020DC) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL5;     /*!< (@ 0x000020E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC5;       /*!< (@ 0x000020E4) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC5;      /*!< (@ 0x000020E8) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC5;      /*!< (@ 0x000020EC) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU6;    /*!< (@ 0x000020F0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD6;    /*!< (@ 0x000020F4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU6;    /*!< (@ 0x000020F8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD6;    /*!< (@ 0x000020FC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL6;      /*!< (@ 0x00002100) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM6;      /*!< (@ 0x00002104) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL6;     /*!< (@ 0x00002108) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC6;       /*!< (@ 0x0000210C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC6;      /*!< (@ 0x00002110) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC6;      /*!< (@ 0x00002114) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU7;    /*!< (@ 0x00002118) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD7;    /*!< (@ 0x0000211C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU7;    /*!< (@ 0x00002120) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD7;    /*!< (@ 0x00002124) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL7;      /*!< (@ 0x00002128) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM7;      /*!< (@ 0x0000212C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL7;     /*!< (@ 0x00002130) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC7;       /*!< (@ 0x00002134) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC7;      /*!< (@ 0x00002138) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC7;      /*!< (@ 0x0000213C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC7_b;
+    };
+    __IM uint32_t RESERVED57[42];
+
+    union
+    {
+        __IOM uint32_t P0_QSEIS;       /*!< (@ 0x000021E8) Qci Stream Filter Error Interrupt Status (SDU
+                                        *                  Oversize)                                                  */
+
+        struct
+        {
+            __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
+            uint32_t              : 24;
+        } P0_QSEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSEIE;       /*!< (@ 0x000021EC) Qci Stream Filter Error Interrupt Enable                   */
+
+        struct
+        {
+            __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
+            uint32_t              : 24;
+        } P0_QSEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P0_QSEID;        /*!< (@ 0x000021F0) Qci Stream Filter Error Interrupt Disable                  */
+
+        struct
+        {
+            __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
+            uint32_t             : 24;
+        } P0_QSEID_b;
+    };
+    __IM uint32_t RESERVED58[3];
+
+    union
+    {
+        __IOM uint32_t P0_QGMOD;       /*!< (@ 0x00002200) Qci Gate Mode Register                                     */
+
+        struct
+        {
+            __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
+            uint32_t             : 24;
+        } P0_QGMOD_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QGPPC;        /*!< (@ 0x00002204) Qci Gate (All) Passed Packet Count Port 0                  */
+
+        struct
+        {
+            __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
+            uint32_t            : 16;
+        } P0_QGPPC_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QGDPC0;       /*!< (@ 0x00002208) Qci Gate 0 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC0_b;
+    };
+    __IM uint32_t RESERVED59;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC1;       /*!< (@ 0x00002210) Qci Gate 1 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC1_b;
+    };
+    __IM uint32_t RESERVED60;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC2;       /*!< (@ 0x00002218) Qci Gate 2 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC2_b;
+    };
+    __IM uint32_t RESERVED61;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC3;       /*!< (@ 0x00002220) Qci Gate 3 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC3_b;
+    };
+    __IM uint32_t RESERVED62;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC4;       /*!< (@ 0x00002228) Qci Gate 4 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC4_b;
+    };
+    __IM uint32_t RESERVED63;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC5;       /*!< (@ 0x00002230) Qci Gate 5 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC5_b;
+    };
+    __IM uint32_t RESERVED64;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC6;       /*!< (@ 0x00002238) Qci Gate 6 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC6_b;
+    };
+    __IM uint32_t RESERVED65;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC7;       /*!< (@ 0x00002240) Qci Gate 7 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QGEIS;       /*!< (@ 0x00002244) Qci Gate Error Interrupt Status                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
+            uint32_t              : 24;
+        } P0_QGEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QGEIE;       /*!< (@ 0x00002248) Qci Gate Error Interrupt Enable                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
+            uint32_t              : 24;
+        } P0_QGEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P0_QGEID;        /*!< (@ 0x0000224C) Qci Gate Error Interrupt Disable                           */
+
+        struct
+        {
+            __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
+            uint32_t             : 24;
+        } P0_QGEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC0;     /*!< (@ 0x00002250) Qci Port n Flow Meter 0 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC0;     /*!< (@ 0x00002254) Qci Meter CBS Configuration Port n, Meter 0                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC0;     /*!< (@ 0x00002258) Qci Meter CIR Configuration n 0                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC0;       /*!< (@ 0x0000225C) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC0;       /*!< (@ 0x00002260) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC1;     /*!< (@ 0x00002264) Qci Port n Flow Meter 1 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC1;     /*!< (@ 0x00002268) Qci Meter CBS Configuration Port n, Meter 1                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC1;     /*!< (@ 0x0000226C) Qci Meter CIR Configuration n 1                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC1;       /*!< (@ 0x00002270) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC1;       /*!< (@ 0x00002274) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC2;     /*!< (@ 0x00002278) Qci Port n Flow Meter 2 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC2;     /*!< (@ 0x0000227C) Qci Meter CBS Configuration Port n, Meter 2                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC2;     /*!< (@ 0x00002280) Qci Meter CIR Configuration n 2                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC2;       /*!< (@ 0x00002284) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC2;       /*!< (@ 0x00002288) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC3;     /*!< (@ 0x0000228C) Qci Port n Flow Meter 3 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC3;     /*!< (@ 0x00002290) Qci Meter CBS Configuration Port n, Meter 3                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC3;     /*!< (@ 0x00002294) Qci Meter CIR Configuration n 3                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC3;       /*!< (@ 0x00002298) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC3;       /*!< (@ 0x0000229C) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC4;     /*!< (@ 0x000022A0) Qci Port n Flow Meter 4 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC4;     /*!< (@ 0x000022A4) Qci Meter CBS Configuration Port n, Meter 4                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC4;     /*!< (@ 0x000022A8) Qci Meter CIR Configuration n 4                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC4;       /*!< (@ 0x000022AC) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC4;       /*!< (@ 0x000022B0) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC5;     /*!< (@ 0x000022B4) Qci Port n Flow Meter 5 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC5;     /*!< (@ 0x000022B8) Qci Meter CBS Configuration Port n, Meter 5                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC5;     /*!< (@ 0x000022BC) Qci Meter CIR Configuration n 5                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC5;       /*!< (@ 0x000022C0) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC5;       /*!< (@ 0x000022C4) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC6;     /*!< (@ 0x000022C8) Qci Port n Flow Meter 6 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC6;     /*!< (@ 0x000022CC) Qci Meter CBS Configuration Port n, Meter 6                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC6;     /*!< (@ 0x000022D0) Qci Meter CIR Configuration n 6                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC6;       /*!< (@ 0x000022D4) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC6;       /*!< (@ 0x000022D8) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC7;     /*!< (@ 0x000022DC) Qci Port n Flow Meter 7 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC7;     /*!< (@ 0x000022E0) Qci Meter CBS Configuration Port n, Meter 7                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC7;     /*!< (@ 0x000022E4) Qci Meter CIR Configuration n 7                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC7;       /*!< (@ 0x000022E8) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC7;       /*!< (@ 0x000022EC) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMEC;        /*!< (@ 0x000022F0) Qci Meter Enable Configuration                             */
+
+        struct
+        {
+            __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
+            uint32_t          : 24;
+        } P0_QMEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMEIS;       /*!< (@ 0x000022F4) Qci Meter Error Interrupt Status                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
+            uint32_t             : 24;
+        } P0_QMEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMEIE;       /*!< (@ 0x000022F8) Qci Meter Error Interrupt Enable                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
+            uint32_t             : 24;
+        } P0_QMEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P0_QMEID;        /*!< (@ 0x000022FC) Qci Meter Error Interrupt Disable                          */
+
+        struct
+        {
+            __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
+            uint32_t            : 24;
+        } P0_QMEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_PCP_REMAP;       /*!< (@ 0x00002300) Port 0 VLAN Priority Code Point (PCP) Remap                */
+
+        struct
+        {
+            __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
+            __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
+            __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
+            __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
+            __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
+            __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
+            __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
+            __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
+            uint32_t                  : 8;
+        } P0_PCP_REMAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_VLAN_TAG;    /*!< (@ 0x00002304) Port 0 VLAN TAG Information for Priority Regeneration      */
+
+        struct
+        {
+            __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
+            __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
+        } P0_VLAN_TAG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_VLAN_MODE;   /*!< (@ 0x00002308) Port 0 VLAN Mode                                           */
+
+        struct
+        {
+            __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
+            __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
+            uint32_t            : 28;
+        } P0_VLAN_MODE_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_VIC_DROP_CNT;       /*!< (@ 0x0000230C) Port 0 VLAN Ingress Check Drop Frame Counter               */
+
+        struct
+        {
+            __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
+            uint32_t                   : 16;
+        } P0_VIC_DROP_CNT_b;
+    };
+    __IM uint32_t RESERVED66[6];
+
+    union
+    {
+        __IM uint32_t P0_LOOKUP_HIT_CNT;       /*!< (@ 0x00002328) Port 0 DST Address Lookup Hit Counter                      */
+
+        struct
+        {
+            __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
+            uint32_t                     : 8;
+        } P0_LOOKUP_HIT_CNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_ERROR_STATUS; /*!< (@ 0x0000232C) Port 0 Frame Parser Runtime Error Status                   */
+
+        struct
+        {
+            __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
+            __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
+                                         *   parser                                                                    */
+            __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
+            __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
+            __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
+            uint32_t              : 27;
+        } P0_ERROR_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_ERROR_MASK;   /*!< (@ 0x00002330) Port 0 Frame Parser Runtime Error Mask                     */
+
+        struct
+        {
+            __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
+            __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
+            __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
+            __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
+            __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
+            uint32_t               : 27;
+        } P0_ERROR_MASK_b;
+    };
+    __IM uint32_t RESERVED67[35];
+
+    union
+    {
+        __IM uint32_t CHANNEL_STATE;   /*!< (@ 0x000023C0) Enable/Disable State of Ingress Channels                   */
+
+        struct
+        {
+            __IM uint32_t CH0ACT : 1;  /*!< [0..0] CH0ACT                                                             */
+            __IM uint32_t CH1ACT : 1;  /*!< [1..1] CH1ACT                                                             */
+            __IM uint32_t CH2ACT : 1;  /*!< [2..2] CH2ACT                                                             */
+            uint32_t             : 29;
+        } CHANNEL_STATE_b;
+    };
+
+    union
+    {
+        __OM uint32_t CHANNEL_ENABLE;  /*!< (@ 0x000023C4) Enable Operation of Channel                                */
+
+        struct
+        {
+            __OM uint32_t CH0ENA : 1;  /*!< [0..0] CH0ENA                                                             */
+            __OM uint32_t CH1ENA : 1;  /*!< [1..1] CH1ENA                                                             */
+            __OM uint32_t CH2ENA : 1;  /*!< [2..2] CH2ENA                                                             */
+            uint32_t             : 29;
+        } CHANNEL_ENABLE_b;
+    };
+
+    union
+    {
+        __OM uint32_t CHANNEL_DISABLE; /*!< (@ 0x000023C8) Disable and Reset Operation of Channel                     */
+
+        struct
+        {
+            __OM uint32_t CH0DIS : 1;  /*!< [0..0] CH0DIS                                                             */
+            __OM uint32_t CH1DIS : 1;  /*!< [1..1] CH1DIS                                                             */
+            __OM uint32_t CH2DIS : 1;  /*!< [2..2] CH2DIS                                                             */
+            uint32_t             : 29;
+        } CHANNEL_DISABLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ASI_MEM_WDATA[4]; /*!< (@ 0x000023CC) Memory Write Data Word [0..3]                              */
+
+        struct
+        {
+            __IOM uint32_t WDATA : 32;   /*!< [31..0] Destination MAC address regeneration write data                   */
+        } ASI_MEM_WDATA_b[4];
+    };
+
+    union
+    {
+        __IOM uint32_t ASI_MEM_ADDR;    /*!< (@ 0x000023DC) Memory Address and R/W Control                             */
+
+        struct
+        {
+            __IOM uint32_t ADDR    : 7; /*!< [6..0] Memory access address                                              */
+            __IOM uint32_t MEM_WEN : 1; /*!< [7..7] MEM_WEN                                                            */
+            __IOM uint32_t MEM_REQ : 3; /*!< [10..8] Memory access request                                             */
+            uint32_t               : 21;
+        } ASI_MEM_ADDR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASI_MEM_RDATA[4]; /*!< (@ 0x000023E0) Memory Read Data Word [0..3]                               */
+
+        struct
+        {
+            __IM uint32_t RDATA : 32;   /*!< [31..0] Destination MAC address regeneration read data                    */
+        } ASI_MEM_RDATA_b[4];
+    };
+    __IM uint32_t RESERVED68[4];
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU0;    /*!< (@ 0x00002400) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD0;    /*!< (@ 0x00002404) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU0;    /*!< (@ 0x00002408) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD0;    /*!< (@ 0x0000240C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL0;      /*!< (@ 0x00002410) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM0;      /*!< (@ 0x00002414) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL0;     /*!< (@ 0x00002418) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC0;       /*!< (@ 0x0000241C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC0;      /*!< (@ 0x00002420) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC0;      /*!< (@ 0x00002424) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU1;    /*!< (@ 0x00002428) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD1;    /*!< (@ 0x0000242C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU1;    /*!< (@ 0x00002430) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD1;    /*!< (@ 0x00002434) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL1;      /*!< (@ 0x00002438) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM1;      /*!< (@ 0x0000243C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL1;     /*!< (@ 0x00002440) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC1;       /*!< (@ 0x00002444) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC1;      /*!< (@ 0x00002448) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC1;      /*!< (@ 0x0000244C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU2;    /*!< (@ 0x00002450) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD2;    /*!< (@ 0x00002454) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU2;    /*!< (@ 0x00002458) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD2;    /*!< (@ 0x0000245C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL2;      /*!< (@ 0x00002460) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM2;      /*!< (@ 0x00002464) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL2;     /*!< (@ 0x00002468) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC2;       /*!< (@ 0x0000246C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC2;      /*!< (@ 0x00002470) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC2;      /*!< (@ 0x00002474) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU3;    /*!< (@ 0x00002478) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD3;    /*!< (@ 0x0000247C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU3;    /*!< (@ 0x00002480) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD3;    /*!< (@ 0x00002484) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL3;      /*!< (@ 0x00002488) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM3;      /*!< (@ 0x0000248C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL3;     /*!< (@ 0x00002490) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC3;       /*!< (@ 0x00002494) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC3;      /*!< (@ 0x00002498) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC3;      /*!< (@ 0x0000249C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU4;    /*!< (@ 0x000024A0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD4;    /*!< (@ 0x000024A4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU4;    /*!< (@ 0x000024A8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD4;    /*!< (@ 0x000024AC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL4;      /*!< (@ 0x000024B0) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM4;      /*!< (@ 0x000024B4) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL4;     /*!< (@ 0x000024B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC4;       /*!< (@ 0x000024BC) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC4;      /*!< (@ 0x000024C0) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC4;      /*!< (@ 0x000024C4) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU5;    /*!< (@ 0x000024C8) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD5;    /*!< (@ 0x000024CC) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU5;    /*!< (@ 0x000024D0) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD5;    /*!< (@ 0x000024D4) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL5;      /*!< (@ 0x000024D8) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM5;      /*!< (@ 0x000024DC) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL5;     /*!< (@ 0x000024E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC5;       /*!< (@ 0x000024E4) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC5;      /*!< (@ 0x000024E8) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC5;      /*!< (@ 0x000024EC) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU6;    /*!< (@ 0x000024F0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD6;    /*!< (@ 0x000024F4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU6;    /*!< (@ 0x000024F8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD6;    /*!< (@ 0x000024FC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL6;      /*!< (@ 0x00002500) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM6;      /*!< (@ 0x00002504) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL6;     /*!< (@ 0x00002508) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC6;       /*!< (@ 0x0000250C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC6;      /*!< (@ 0x00002510) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC6;      /*!< (@ 0x00002514) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU7;    /*!< (@ 0x00002518) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD7;    /*!< (@ 0x0000251C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU7;    /*!< (@ 0x00002520) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD7;    /*!< (@ 0x00002524) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL7;      /*!< (@ 0x00002528) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM7;      /*!< (@ 0x0000252C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL7;     /*!< (@ 0x00002530) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC7;       /*!< (@ 0x00002534) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC7;      /*!< (@ 0x00002538) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC7;      /*!< (@ 0x0000253C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC7_b;
+    };
+    __IM uint32_t RESERVED69[42];
+
+    union
+    {
+        __IOM uint32_t P1_QSEIS;       /*!< (@ 0x000025E8) Qci Stream Filter Error Interrupt Status (SDU
+                                        *                  Oversize)                                                  */
+
+        struct
+        {
+            __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
+            uint32_t              : 24;
+        } P1_QSEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSEIE;       /*!< (@ 0x000025EC) Qci Stream Filter Error Interrupt Enable                   */
+
+        struct
+        {
+            __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
+            uint32_t              : 24;
+        } P1_QSEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P1_QSEID;        /*!< (@ 0x000025F0) Qci Stream Filter Error Interrupt Disable                  */
+
+        struct
+        {
+            __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
+            uint32_t             : 24;
+        } P1_QSEID_b;
+    };
+    __IM uint32_t RESERVED70[3];
+
+    union
+    {
+        __IOM uint32_t P1_QGMOD;       /*!< (@ 0x00002600) Qci Gate Mode Register                                     */
+
+        struct
+        {
+            __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
+            uint32_t             : 24;
+        } P1_QGMOD_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QGPPC;        /*!< (@ 0x00002604) Qci Gate (All) Passed Packet Count Port 1                  */
+
+        struct
+        {
+            __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
+            uint32_t            : 16;
+        } P1_QGPPC_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QGDPC0;       /*!< (@ 0x00002608) Qci Gate 0 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC0_b;
+    };
+    __IM uint32_t RESERVED71;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC1;       /*!< (@ 0x00002610) Qci Gate 1 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC1_b;
+    };
+    __IM uint32_t RESERVED72;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC2;       /*!< (@ 0x00002618) Qci Gate 2 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC2_b;
+    };
+    __IM uint32_t RESERVED73;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC3;       /*!< (@ 0x00002620) Qci Gate 3 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC3_b;
+    };
+    __IM uint32_t RESERVED74;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC4;       /*!< (@ 0x00002628) Qci Gate 4 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC4_b;
+    };
+    __IM uint32_t RESERVED75;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC5;       /*!< (@ 0x00002630) Qci Gate 5 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC5_b;
+    };
+    __IM uint32_t RESERVED76;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC6;       /*!< (@ 0x00002638) Qci Gate 6 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC6_b;
+    };
+    __IM uint32_t RESERVED77;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC7;       /*!< (@ 0x00002640) Qci Gate 7 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QGEIS;       /*!< (@ 0x00002644) Qci Gate Error Interrupt Status                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
+            uint32_t              : 24;
+        } P1_QGEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QGEIE;       /*!< (@ 0x00002648) Qci Gate Error Interrupt Enable                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
+            uint32_t              : 24;
+        } P1_QGEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P1_QGEID;        /*!< (@ 0x0000264C) Qci Gate Error Interrupt Disable                           */
+
+        struct
+        {
+            __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
+            uint32_t             : 24;
+        } P1_QGEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC0;     /*!< (@ 0x00002650) Qci Port n Flow Meter 0 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC0;     /*!< (@ 0x00002654) Qci Meter CBS Configuration Port n, Meter 0                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC0;     /*!< (@ 0x00002658) Qci Meter CIR Configuration n 0                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC0;       /*!< (@ 0x0000265C) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC0;       /*!< (@ 0x00002660) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC1;     /*!< (@ 0x00002664) Qci Port n Flow Meter 1 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC1;     /*!< (@ 0x00002668) Qci Meter CBS Configuration Port n, Meter 1                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC1;     /*!< (@ 0x0000266C) Qci Meter CIR Configuration n 1                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC1;       /*!< (@ 0x00002670) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC1;       /*!< (@ 0x00002674) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC2;     /*!< (@ 0x00002678) Qci Port n Flow Meter 2 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC2;     /*!< (@ 0x0000267C) Qci Meter CBS Configuration Port n, Meter 2                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC2;     /*!< (@ 0x00002680) Qci Meter CIR Configuration n 2                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC2;       /*!< (@ 0x00002684) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC2;       /*!< (@ 0x00002688) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC3;     /*!< (@ 0x0000268C) Qci Port n Flow Meter 3 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC3;     /*!< (@ 0x00002690) Qci Meter CBS Configuration Port n, Meter 3                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC3;     /*!< (@ 0x00002694) Qci Meter CIR Configuration n 3                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC3;       /*!< (@ 0x00002698) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC3;       /*!< (@ 0x0000269C) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC4;     /*!< (@ 0x000026A0) Qci Port n Flow Meter 4 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC4;     /*!< (@ 0x000026A4) Qci Meter CBS Configuration Port n, Meter 4                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC4;     /*!< (@ 0x000026A8) Qci Meter CIR Configuration n 4                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC4;       /*!< (@ 0x000026AC) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC4;       /*!< (@ 0x000026B0) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC5;     /*!< (@ 0x000026B4) Qci Port n Flow Meter 5 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC5;     /*!< (@ 0x000026B8) Qci Meter CBS Configuration Port n, Meter 5                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC5;     /*!< (@ 0x000026BC) Qci Meter CIR Configuration n 5                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC5;       /*!< (@ 0x000026C0) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC5;       /*!< (@ 0x000026C4) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC6;     /*!< (@ 0x000026C8) Qci Port n Flow Meter 6 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC6;     /*!< (@ 0x000026CC) Qci Meter CBS Configuration Port n, Meter 6                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC6;     /*!< (@ 0x000026D0) Qci Meter CIR Configuration n 6                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC6;       /*!< (@ 0x000026D4) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC6;       /*!< (@ 0x000026D8) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC7;     /*!< (@ 0x000026DC) Qci Port n Flow Meter 7 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC7;     /*!< (@ 0x000026E0) Qci Meter CBS Configuration Port n, Meter 7                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC7;     /*!< (@ 0x000026E4) Qci Meter CIR Configuration n 7                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC7;       /*!< (@ 0x000026E8) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC7;       /*!< (@ 0x000026EC) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMEC;        /*!< (@ 0x000026F0) Qci Meter Enable Configuration                             */
+
+        struct
+        {
+            __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
+            uint32_t          : 24;
+        } P1_QMEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMEIS;       /*!< (@ 0x000026F4) Qci Meter Error Interrupt Status                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
+            uint32_t             : 24;
+        } P1_QMEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMEIE;       /*!< (@ 0x000026F8) Qci Meter Error Interrupt Enable                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
+            uint32_t             : 24;
+        } P1_QMEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P1_QMEID;        /*!< (@ 0x000026FC) Qci Meter Error Interrupt Disable                          */
+
+        struct
+        {
+            __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
+            uint32_t            : 24;
+        } P1_QMEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_PCP_REMAP;       /*!< (@ 0x00002700) Port 1 VLAN Priority Code Point (PCP) Remap                */
+
+        struct
+        {
+            __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
+            __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
+            __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
+            __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
+            __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
+            __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
+            __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
+            __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
+            uint32_t                  : 8;
+        } P1_PCP_REMAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_VLAN_TAG;    /*!< (@ 0x00002704) Port 1 VLAN TAG Information for Priority Regeneration      */
+
+        struct
+        {
+            __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
+            __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
+        } P1_VLAN_TAG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_VLAN_MODE;   /*!< (@ 0x00002708) Port 1 VLAN Mode                                           */
+
+        struct
+        {
+            __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
+            __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
+            uint32_t            : 28;
+        } P1_VLAN_MODE_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_VIC_DROP_CNT;       /*!< (@ 0x0000270C) Port 1 VLAN Ingress Check Drop Frame Counter               */
+
+        struct
+        {
+            __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
+            uint32_t                   : 16;
+        } P1_VIC_DROP_CNT_b;
+    };
+    __IM uint32_t RESERVED78[6];
+
+    union
+    {
+        __IM uint32_t P1_LOOKUP_HIT_CNT;       /*!< (@ 0x00002728) Port 1 DST Address Lookup Hit Counter                      */
+
+        struct
+        {
+            __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
+            uint32_t                     : 8;
+        } P1_LOOKUP_HIT_CNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_ERROR_STATUS; /*!< (@ 0x0000272C) Port 1 Frame Parser Runtime Error Status                   */
+
+        struct
+        {
+            __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
+            __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
+                                         *   parser                                                                    */
+            __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
+            __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
+            __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
+            uint32_t              : 27;
+        } P1_ERROR_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_ERROR_MASK;   /*!< (@ 0x00002730) Port 1 Frame Parser Runtime Error Mask                     */
+
+        struct
+        {
+            __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
+            __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
+            __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
+            __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
+            __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
+            uint32_t               : 27;
+        } P1_ERROR_MASK_b;
+    };
+    __IM uint32_t RESERVED79[51];
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU0;    /*!< (@ 0x00002800) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD0;    /*!< (@ 0x00002804) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU0;    /*!< (@ 0x00002808) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD0;    /*!< (@ 0x0000280C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL0;      /*!< (@ 0x00002810) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM0;      /*!< (@ 0x00002814) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL0;     /*!< (@ 0x00002818) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC0;       /*!< (@ 0x0000281C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC0;      /*!< (@ 0x00002820) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC0;      /*!< (@ 0x00002824) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU1;    /*!< (@ 0x00002828) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD1;    /*!< (@ 0x0000282C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU1;    /*!< (@ 0x00002830) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD1;    /*!< (@ 0x00002834) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL1;      /*!< (@ 0x00002838) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM1;      /*!< (@ 0x0000283C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL1;     /*!< (@ 0x00002840) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC1;       /*!< (@ 0x00002844) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC1;      /*!< (@ 0x00002848) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC1;      /*!< (@ 0x0000284C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU2;    /*!< (@ 0x00002850) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD2;    /*!< (@ 0x00002854) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU2;    /*!< (@ 0x00002858) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD2;    /*!< (@ 0x0000285C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL2;      /*!< (@ 0x00002860) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM2;      /*!< (@ 0x00002864) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL2;     /*!< (@ 0x00002868) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC2;       /*!< (@ 0x0000286C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC2;      /*!< (@ 0x00002870) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC2;      /*!< (@ 0x00002874) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU3;    /*!< (@ 0x00002878) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD3;    /*!< (@ 0x0000287C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU3;    /*!< (@ 0x00002880) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD3;    /*!< (@ 0x00002884) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL3;      /*!< (@ 0x00002888) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM3;      /*!< (@ 0x0000288C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL3;     /*!< (@ 0x00002890) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC3;       /*!< (@ 0x00002894) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC3;      /*!< (@ 0x00002898) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC3;      /*!< (@ 0x0000289C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU4;    /*!< (@ 0x000028A0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD4;    /*!< (@ 0x000028A4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU4;    /*!< (@ 0x000028A8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD4;    /*!< (@ 0x000028AC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL4;      /*!< (@ 0x000028B0) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM4;      /*!< (@ 0x000028B4) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL4;     /*!< (@ 0x000028B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC4;       /*!< (@ 0x000028BC) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC4;      /*!< (@ 0x000028C0) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC4;      /*!< (@ 0x000028C4) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU5;    /*!< (@ 0x000028C8) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD5;    /*!< (@ 0x000028CC) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU5;    /*!< (@ 0x000028D0) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD5;    /*!< (@ 0x000028D4) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL5;      /*!< (@ 0x000028D8) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM5;      /*!< (@ 0x000028DC) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL5;     /*!< (@ 0x000028E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC5;       /*!< (@ 0x000028E4) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC5;      /*!< (@ 0x000028E8) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC5;      /*!< (@ 0x000028EC) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU6;    /*!< (@ 0x000028F0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD6;    /*!< (@ 0x000028F4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU6;    /*!< (@ 0x000028F8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD6;    /*!< (@ 0x000028FC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL6;      /*!< (@ 0x00002900) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM6;      /*!< (@ 0x00002904) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL6;     /*!< (@ 0x00002908) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC6;       /*!< (@ 0x0000290C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC6;      /*!< (@ 0x00002910) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC6;      /*!< (@ 0x00002914) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU7;    /*!< (@ 0x00002918) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD7;    /*!< (@ 0x0000291C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU7;    /*!< (@ 0x00002920) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD7;    /*!< (@ 0x00002924) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL7;      /*!< (@ 0x00002928) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM7;      /*!< (@ 0x0000292C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL7;     /*!< (@ 0x00002930) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC7;       /*!< (@ 0x00002934) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC7;      /*!< (@ 0x00002938) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC7;      /*!< (@ 0x0000293C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC7_b;
+    };
+    __IM uint32_t RESERVED80[42];
+
+    union
+    {
+        __IOM uint32_t P2_QSEIS;       /*!< (@ 0x000029E8) Qci Stream Filter Error Interrupt Status (SDU
+                                        *                  Oversize)                                                  */
+
+        struct
+        {
+            __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
+            uint32_t              : 24;
+        } P2_QSEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSEIE;       /*!< (@ 0x000029EC) Qci Stream Filter Error Interrupt Enable                   */
+
+        struct
+        {
+            __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
+            uint32_t              : 24;
+        } P2_QSEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P2_QSEID;        /*!< (@ 0x000029F0) Qci Stream Filter Error Interrupt Disable                  */
+
+        struct
+        {
+            __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
+            uint32_t             : 24;
+        } P2_QSEID_b;
+    };
+    __IM uint32_t RESERVED81[3];
+
+    union
+    {
+        __IOM uint32_t P2_QGMOD;       /*!< (@ 0x00002A00) Qci Gate Mode Register                                     */
+
+        struct
+        {
+            __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
+            uint32_t             : 24;
+        } P2_QGMOD_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QGPPC;        /*!< (@ 0x00002A04) Qci Gate (All) Passed Packet Count Port 2                  */
+
+        struct
+        {
+            __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
+            uint32_t            : 16;
+        } P2_QGPPC_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QGDPC0;       /*!< (@ 0x00002A08) Qci Gate 0 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC0_b;
+    };
+    __IM uint32_t RESERVED82;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC1;       /*!< (@ 0x00002A10) Qci Gate 1 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC1_b;
+    };
+    __IM uint32_t RESERVED83;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC2;       /*!< (@ 0x00002A18) Qci Gate 2 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC2_b;
+    };
+    __IM uint32_t RESERVED84;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC3;       /*!< (@ 0x00002A20) Qci Gate 3 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC3_b;
+    };
+    __IM uint32_t RESERVED85;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC4;       /*!< (@ 0x00002A28) Qci Gate 4 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC4_b;
+    };
+    __IM uint32_t RESERVED86;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC5;       /*!< (@ 0x00002A30) Qci Gate 5 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC5_b;
+    };
+    __IM uint32_t RESERVED87;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC6;       /*!< (@ 0x00002A38) Qci Gate 6 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC6_b;
+    };
+    __IM uint32_t RESERVED88;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC7;       /*!< (@ 0x00002A40) Qci Gate 7 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QGEIS;       /*!< (@ 0x00002A44) Qci Gate Error Interrupt Status                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
+            uint32_t              : 24;
+        } P2_QGEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QGEIE;       /*!< (@ 0x00002A48) Qci Gate Error Interrupt Enable                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
+            uint32_t              : 24;
+        } P2_QGEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P2_QGEID;        /*!< (@ 0x00002A4C) Qci Gate Error Interrupt Disable                           */
+
+        struct
+        {
+            __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
+            uint32_t             : 24;
+        } P2_QGEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC0;     /*!< (@ 0x00002A50) Qci Port n Flow Meter 0 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC0;     /*!< (@ 0x00002A54) Qci Meter CBS Configuration Port n, Meter 0                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC0;     /*!< (@ 0x00002A58) Qci Meter CIR Configuration n 0                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC0;       /*!< (@ 0x00002A5C) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC0;       /*!< (@ 0x00002A60) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC1;     /*!< (@ 0x00002A64) Qci Port n Flow Meter 1 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC1;     /*!< (@ 0x00002A68) Qci Meter CBS Configuration Port n, Meter 1                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC1;     /*!< (@ 0x00002A6C) Qci Meter CIR Configuration n 1                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC1;       /*!< (@ 0x00002A70) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC1;       /*!< (@ 0x00002A74) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC2;     /*!< (@ 0x00002A78) Qci Port n Flow Meter 2 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC2;     /*!< (@ 0x00002A7C) Qci Meter CBS Configuration Port n, Meter 2                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC2;     /*!< (@ 0x00002A80) Qci Meter CIR Configuration n 2                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC2;       /*!< (@ 0x00002A84) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC2;       /*!< (@ 0x00002A88) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC3;     /*!< (@ 0x00002A8C) Qci Port n Flow Meter 3 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC3;     /*!< (@ 0x00002A90) Qci Meter CBS Configuration Port n, Meter 3                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC3;     /*!< (@ 0x00002A94) Qci Meter CIR Configuration n 3                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC3;       /*!< (@ 0x00002A98) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC3;       /*!< (@ 0x00002A9C) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC4;     /*!< (@ 0x00002AA0) Qci Port n Flow Meter 4 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC4;     /*!< (@ 0x00002AA4) Qci Meter CBS Configuration Port n, Meter 4                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC4;     /*!< (@ 0x00002AA8) Qci Meter CIR Configuration n 4                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC4;       /*!< (@ 0x00002AAC) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC4;       /*!< (@ 0x00002AB0) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC5;     /*!< (@ 0x00002AB4) Qci Port n Flow Meter 5 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC5;     /*!< (@ 0x00002AB8) Qci Meter CBS Configuration Port n, Meter 5                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC5;     /*!< (@ 0x00002ABC) Qci Meter CIR Configuration n 5                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC5;       /*!< (@ 0x00002AC0) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC5;       /*!< (@ 0x00002AC4) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC6;     /*!< (@ 0x00002AC8) Qci Port n Flow Meter 6 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC6;     /*!< (@ 0x00002ACC) Qci Meter CBS Configuration Port n, Meter 6                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC6;     /*!< (@ 0x00002AD0) Qci Meter CIR Configuration n 6                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC6;       /*!< (@ 0x00002AD4) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC6;       /*!< (@ 0x00002AD8) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC7;     /*!< (@ 0x00002ADC) Qci Port n Flow Meter 7 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC7;     /*!< (@ 0x00002AE0) Qci Meter CBS Configuration Port n, Meter 7                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC7;     /*!< (@ 0x00002AE4) Qci Meter CIR Configuration n 7                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC7;       /*!< (@ 0x00002AE8) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC7;       /*!< (@ 0x00002AEC) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMEC;        /*!< (@ 0x00002AF0) Qci Meter Enable Configuration                             */
+
+        struct
+        {
+            __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
+            uint32_t          : 24;
+        } P2_QMEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMEIS;       /*!< (@ 0x00002AF4) Qci Meter Error Interrupt Status                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
+            uint32_t             : 24;
+        } P2_QMEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMEIE;       /*!< (@ 0x00002AF8) Qci Meter Error Interrupt Enable                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
+            uint32_t             : 24;
+        } P2_QMEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P2_QMEID;        /*!< (@ 0x00002AFC) Qci Meter Error Interrupt Disable                          */
+
+        struct
+        {
+            __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
+            uint32_t            : 24;
+        } P2_QMEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_PCP_REMAP;       /*!< (@ 0x00002B00) Port 2 VLAN Priority Code Point (PCP) Remap                */
+
+        struct
+        {
+            __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
+            __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
+            __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
+            __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
+            __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
+            __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
+            __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
+            __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
+            uint32_t                  : 8;
+        } P2_PCP_REMAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_VLAN_TAG;    /*!< (@ 0x00002B04) Port 2 VLAN TAG Information for Priority Regeneration      */
+
+        struct
+        {
+            __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
+            __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
+        } P2_VLAN_TAG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_VLAN_MODE;   /*!< (@ 0x00002B08) Port 2 VLAN Mode                                           */
+
+        struct
+        {
+            __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
+            __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
+            uint32_t            : 28;
+        } P2_VLAN_MODE_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_VIC_DROP_CNT;       /*!< (@ 0x00002B0C) Port 2 VLAN Ingress Check Drop Frame Counter               */
+
+        struct
+        {
+            __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
+            uint32_t                   : 16;
+        } P2_VIC_DROP_CNT_b;
+    };
+    __IM uint32_t RESERVED89[6];
+
+    union
+    {
+        __IM uint32_t P2_LOOKUP_HIT_CNT;       /*!< (@ 0x00002B28) Port 2 DST Address Lookup Hit Counter                      */
+
+        struct
+        {
+            __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
+            uint32_t                     : 8;
+        } P2_LOOKUP_HIT_CNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_ERROR_STATUS; /*!< (@ 0x00002B2C) Port 2 Frame Parser Runtime Error Status                   */
+
+        struct
+        {
+            __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
+            __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
+                                         *   parser                                                                    */
+            __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
+            __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
+            __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
+            uint32_t              : 27;
+        } P2_ERROR_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_ERROR_MASK;   /*!< (@ 0x00002B30) Port 2 Frame Parser Runtime Error Mask                     */
+
+        struct
+        {
+            __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
+            __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
+            __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
+            __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
+            __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
+            uint32_t               : 27;
+        } P2_ERROR_MASK_b;
+    };
+    __IM uint32_t RESERVED90[564];
+
+    union
+    {
+        __IM uint32_t STATN_STATUS;    /*!< (@ 0x00003404) Statistics Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t BUSY : 1;    /*!< [0..0] Statistics module is busy                                          */
+            uint32_t           : 31;
+        } STATN_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATN_CONFIG;   /*!< (@ 0x00003408) Statistics Configure Register                              */
+
+        struct
+        {
+            uint32_t                     : 1;
+            __IOM uint32_t CLEAR_ON_READ : 1; /*!< [1..1] When set to 1, a read to a counter resets it to 0. When
+                                               *   set to 0 (default), counters are not affected by read.                    */
+            uint32_t             : 29;
+            __IOM uint32_t RESET : 1;         /*!< [31..31] When set to 1, all internal functions are aborted and
+                                               *   return to a stable state (flushes prescalers). It also
+                                               *   triggers a clear of all counter memory (all ports are cleared)
+                                               *   by setting STATN_CONTROL.CMD_CLEAR with all mask bits.
+                                               *   Capture memory is not reset.                                              */
+        } STATN_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATN_CONTROL;     /*!< (@ 0x0000340C) Statistics Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t CHANMASK : 4;  /*!< [3..0] One bit per port. Bit 0 = port 0, bit 1 = port 1, and
+                                           *   so on.                                                                    */
+            uint32_t                 : 25;
+            __IOM uint32_t CLEAR_PRE : 1; /*!< [29..29] Clear the internal pre-scaler counters of ports when
+                                           *   a clear occurs. This bit can be used together with the
+                                           *   CMD_CLEAR command to clear the internal pre-scaler counters
+                                           *   of the ports.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t CMD_CLEAR : 1; /*!< [31..31] Clear Channel Counters Command                                   */
+        } STATN_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATN_CLEARVALUE_LO;          /*!< (@ 0x00003410) Statistics Clear Value Lower Register                      */
+
+        struct
+        {
+            __IOM uint32_t STATN_CLEARVALUE_LO : 32; /*!< [31..0] 32-bit value written into statistics memory when a clear
+                                                      *   command (STATN_CONTROL.CMD_CLEAR) is triggered (see ),
+                                                      *   or when a clear-after-read is used.                                       */
+        } STATN_CLEARVALUE_LO_b;
+    };
+    __IM uint32_t RESERVED91[21];
+
+    union
+    {
+        __IM uint32_t ODISC0;          /*!< (@ 0x00003468) Port 0 Discarded Outgoing Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
+                                        *   congestion.                                                               */
+        } ODISC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_VLAN0;         /*!< (@ 0x0000346C) Port 0 Discarded Incoming VLAN Tagged Frame Count
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
+                                            *   or missing VLAN ID while VLAN verification was enabled.                   */
+        } IDISC_VLAN0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_UNTAGGED0;         /*!< (@ 0x00003470) Port 0 Discarded Incoming VLAN Untagged Frame
+                                                *                  Count Register                                             */
+
+        struct
+        {
+            __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
+                                                *   tag.                                                                      */
+        } IDISC_UNTAGGED0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_BLOCKED0;         /*!< (@ 0x00003474) Port 0 Discarded Incoming Blocked Frame Count
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
+                                               *   the port is configured in blocking mode.                                  */
+        } IDISC_BLOCKED0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_ANY0;         /*!< (@ 0x00003478) Port 0 Discarded Any Frame Count Register (n
+                                           *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
+                                           *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
+        } IDISC_ANY0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_SRCFLT0;         /*!< (@ 0x0000347C) Port 0 Discarded Address Source Count Register             */
+
+        struct
+        {
+            __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
+                                              *   due to the MAC address source filter.                                     */
+        } IDISC_SRCFLT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_HOLD_REQ_CNT0;         /*!< (@ 0x00003480) Port 0 TX Hold Request Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
+        } TX_HOLD_REQ_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_FRAG_CNT0;         /*!< (@ 0x00003484) Port 0 TX for Preemption Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
+                                             *   due to preemption.                                                        */
+        } TX_FRAG_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_FRAG_CNT0;         /*!< (@ 0x00003488) Port 0 RX Continuation Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
+        } RX_FRAG_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_OK_CNT0;         /*!< (@ 0x0000348C) Port 0 RX Preempted Frame Success Count Register           */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
+                                                *   assembled.                                                                */
+        } RX_ASSY_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_ERR_CNT0;         /*!< (@ 0x00003490) Port 0 RX Preempted Frame Incorrect Count Register         */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
+                                                 *   assembled.                                                                */
+            uint32_t : 16;
+        } RX_ASSY_ERR_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_SMD_ERR_CNT0;         /*!< (@ 0x00003494) Port 0 RX SMD Frame Count Register                         */
+
+        struct
+        {
+            __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
+                                                *   and no assembly is in progress.                                           */
+            uint32_t : 16;
+        } RX_SMD_ERR_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_VERIFY_OK_CNT0;        /*!< (@ 0x00003498) Port 0 TX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
+            uint32_t                       : 24;
+        } TX_VERIFY_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_RESPONSE_OK_CNT0;        /*!< (@ 0x0000349C) Port 0 TX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
+            uint32_t                         : 24;
+        } TX_RESPONSE_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_OK_CNT0;        /*!< (@ 0x000034A0) Port 0 RX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
+            uint32_t                       : 24;
+        } RX_VERIFY_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_OK_CNT0;        /*!< (@ 0x000034A4) Port 0 RX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
+            uint32_t                         : 24;
+        } RX_RESPONSE_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_BAD_CNT0;        /*!< (@ 0x000034A8) Port 0 RX Error VERIFY Frame Count Register                */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
+            uint32_t                        : 24;
+        } RX_VERIFY_BAD_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_BAD_CNT0;        /*!< (@ 0x000034AC) Port 0 RX Error RESPONSE Frame Count Register              */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
+            uint32_t                          : 24;
+        } RX_RESPONSE_BAD_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ODISC1;          /*!< (@ 0x000034B0) Port 1 Discarded Outgoing Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
+                                        *   congestion.                                                               */
+        } ODISC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_VLAN1;         /*!< (@ 0x000034B4) Port 1 Discarded Incoming VLAN Tagged Frame Count
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
+                                            *   or missing VLAN ID while VLAN verification was enabled.                   */
+        } IDISC_VLAN1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_UNTAGGED1;         /*!< (@ 0x000034B8) Port 1 Discarded Incoming VLAN Untagged Frame
+                                                *                  Count Register                                             */
+
+        struct
+        {
+            __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
+                                                *   tag.                                                                      */
+        } IDISC_UNTAGGED1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_BLOCKED1;         /*!< (@ 0x000034BC) Port 1 Discarded Incoming Blocked Frame Count
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
+                                               *   the port is configured in blocking mode.                                  */
+        } IDISC_BLOCKED1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_ANY1;         /*!< (@ 0x000034C0) Port 1 Discarded Any Frame Count Register (n
+                                           *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
+                                           *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
+        } IDISC_ANY1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_SRCFLT1;         /*!< (@ 0x000034C4) Port 1 Discarded Address Source Count Register             */
+
+        struct
+        {
+            __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
+                                              *   due to the MAC address source filter.                                     */
+        } IDISC_SRCFLT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_HOLD_REQ_CNT1;         /*!< (@ 0x000034C8) Port 1 TX Hold Request Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
+        } TX_HOLD_REQ_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_FRAG_CNT1;         /*!< (@ 0x000034CC) Port 1 TX for Preemption Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
+                                             *   due to preemption.                                                        */
+        } TX_FRAG_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_FRAG_CNT1;         /*!< (@ 0x000034D0) Port 1 RX Continuation Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
+        } RX_FRAG_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_OK_CNT1;         /*!< (@ 0x000034D4) Port 1 RX Preempted Frame Success Count Register           */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
+                                                *   assembled.                                                                */
+        } RX_ASSY_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_ERR_CNT1;         /*!< (@ 0x000034D8) Port 1 RX Preempted Frame Incorrect Count Register         */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
+                                                 *   assembled.                                                                */
+            uint32_t : 16;
+        } RX_ASSY_ERR_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_SMD_ERR_CNT1;         /*!< (@ 0x000034DC) Port 1 RX SMD Frame Count Register                         */
+
+        struct
+        {
+            __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
+                                                *   and no assembly is in progress.                                           */
+            uint32_t : 16;
+        } RX_SMD_ERR_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_VERIFY_OK_CNT1;        /*!< (@ 0x000034E0) Port 1 TX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
+            uint32_t                       : 24;
+        } TX_VERIFY_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_RESPONSE_OK_CNT1;        /*!< (@ 0x000034E4) Port 1 TX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
+            uint32_t                         : 24;
+        } TX_RESPONSE_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_OK_CNT1;        /*!< (@ 0x000034E8) Port 1 RX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
+            uint32_t                       : 24;
+        } RX_VERIFY_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_OK_CNT1;        /*!< (@ 0x000034EC) Port 1 RX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
+            uint32_t                         : 24;
+        } RX_RESPONSE_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_BAD_CNT1;        /*!< (@ 0x000034F0) Port 1 RX Error VERIFY Frame Count Register                */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
+            uint32_t                        : 24;
+        } RX_VERIFY_BAD_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_BAD_CNT1;        /*!< (@ 0x000034F4) Port 1 RX Error RESPONSE Frame Count Register              */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
+            uint32_t                          : 24;
+        } RX_RESPONSE_BAD_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ODISC2;          /*!< (@ 0x000034F8) Port 2 Discarded Outgoing Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
+                                        *   congestion.                                                               */
+        } ODISC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_VLAN2;         /*!< (@ 0x000034FC) Port 2 Discarded Incoming VLAN Tagged Frame Count
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
+                                            *   or missing VLAN ID while VLAN verification was enabled.                   */
+        } IDISC_VLAN2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_UNTAGGED2;         /*!< (@ 0x00003500) Port 2 Discarded Incoming VLAN Untagged Frame
+                                                *                  Count Register                                             */
+
+        struct
+        {
+            __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
+                                                *   tag.                                                                      */
+        } IDISC_UNTAGGED2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_BLOCKED2;         /*!< (@ 0x00003504) Port 2 Discarded Incoming Blocked Frame Count
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
+                                               *   the port is configured in blocking mode.                                  */
+        } IDISC_BLOCKED2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_ANY2;         /*!< (@ 0x00003508) Port 2 Discarded Any Frame Count Register (n
+                                           *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
+                                           *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
+        } IDISC_ANY2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_SRCFLT2;         /*!< (@ 0x0000350C) Port 2 Discarded Address Source Count Register             */
+
+        struct
+        {
+            __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
+                                              *   due to the MAC address source filter.                                     */
+        } IDISC_SRCFLT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_HOLD_REQ_CNT2;         /*!< (@ 0x00003510) Port 2 TX Hold Request Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
+        } TX_HOLD_REQ_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_FRAG_CNT2;         /*!< (@ 0x00003514) Port 2 TX for Preemption Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
+                                             *   due to preemption.                                                        */
+        } TX_FRAG_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_FRAG_CNT2;         /*!< (@ 0x00003518) Port 2 RX Continuation Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
+        } RX_FRAG_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_OK_CNT2;         /*!< (@ 0x0000351C) Port 2 RX Preempted Frame Success Count Register           */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
+                                                *   assembled.                                                                */
+        } RX_ASSY_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_ERR_CNT2;         /*!< (@ 0x00003520) Port 2 RX Preempted Frame Incorrect Count Register         */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
+                                                 *   assembled.                                                                */
+            uint32_t : 16;
+        } RX_ASSY_ERR_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_SMD_ERR_CNT2;         /*!< (@ 0x00003524) Port 2 RX SMD Frame Count Register                         */
+
+        struct
+        {
+            __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
+                                                *   and no assembly is in progress.                                           */
+            uint32_t : 16;
+        } RX_SMD_ERR_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_VERIFY_OK_CNT2;        /*!< (@ 0x00003528) Port 2 TX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
+            uint32_t                       : 24;
+        } TX_VERIFY_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_RESPONSE_OK_CNT2;        /*!< (@ 0x0000352C) Port 2 TX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
+            uint32_t                         : 24;
+        } TX_RESPONSE_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_OK_CNT2;        /*!< (@ 0x00003530) Port 2 RX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
+            uint32_t                       : 24;
+        } RX_VERIFY_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_OK_CNT2;        /*!< (@ 0x00003534) Port 2 RX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
+            uint32_t                         : 24;
+        } RX_RESPONSE_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_BAD_CNT2;        /*!< (@ 0x00003538) Port 2 RX Error VERIFY Frame Count Register                */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
+            uint32_t                        : 24;
+        } RX_VERIFY_BAD_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_BAD_CNT2;        /*!< (@ 0x0000353C) Port 2 RX Error RESPONSE Frame Count Register              */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
+            uint32_t                          : 24;
+        } RX_RESPONSE_BAD_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ODISC3;          /*!< (@ 0x00003540) Port 3 Discarded Outgoing Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
+                                        *   congestion.                                                               */
+        } ODISC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_VLAN3;         /*!< (@ 0x00003544) Port 3 Discarded Incoming VLAN Tagged Frame Count
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
+                                            *   or missing VLAN ID while VLAN verification was enabled.                   */
+        } IDISC_VLAN3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_UNTAGGED3;         /*!< (@ 0x00003548) Port 3 Discarded Incoming VLAN Untagged Frame
+                                                *                  Count Register                                             */
+
+        struct
+        {
+            __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
+                                                *   tag.                                                                      */
+        } IDISC_UNTAGGED3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_BLOCKED3;         /*!< (@ 0x0000354C) Port 3 Discarded Incoming Blocked Frame Count
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
+                                               *   the port is configured in blocking mode.                                  */
+        } IDISC_BLOCKED3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_ANY3;         /*!< (@ 0x00003550) Port 3 Discarded Any Frame Count Register (n
+                                           *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
+                                           *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
+        } IDISC_ANY3_b;
+    };
+    __IM uint32_t RESERVED92[363];
+
+    union
+    {
+        __IOM uint32_t MMCTL_OUT_CT;       /*!< (@ 0x00003B00) Cut-Through Register                                       */
+
+        struct
+        {
+            __IOM uint32_t CT_OVR_ENA : 3; /*!< [2..0] Per-port bit mask to enable overriding the Cut-Through
+                                            *   (CT) behavior of the output ports with CT_OVR. When set
+                                            *   to 0, the frames are transmitted CT if the CT flag of the
+                                            *   frame context is set.                                                     */
+            uint32_t              : 13;
+            __IOM uint32_t CT_OVR : 3;     /*!< [18..16] 1 bit per-port value to set the Cut Through behavior
+                                            *   of the output ports. When set to 0, all frames are sent
+                                            *   as Store & Forward (SF) frames. When set to 1, frames with
+                                            *   the CT flag set in the frame context are started as soon
+                                            *   as the frame context information is available.                            */
+            uint32_t : 13;
+        } MMCTL_OUT_CT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_CTFL_P0_3_ENA; /*!< (@ 0x00003B04) Cut-Through Frame Length Enable Register                   */
+
+        struct
+        {
+            __IOM uint32_t CTFL_P0_ENA : 8; /*!< [7..0] Port 0 bit mask of n bits, where n is the number of queues
+                                             *   per port indicating whether the CTFL is used for Cut-Through
+                                             *   (CT) frames. When set to 1, a CT frame requires a CTFL
+                                             *   entry to be written as a CT frame in the output memory.                   */
+            __IOM uint32_t CTFL_P1_ENA : 8; /*!< [15..8] Port 1 bit mask of n bits, where n is the number of
+                                             *   queues per port indicating whether the CTFL is used for
+                                             *   Cut-Through (CT) frames. When set to 1, a CT frame requires
+                                             *   a CTFL entry to be written as a CT frame in the output
+                                             *   memory.                                                                   */
+            __IOM uint32_t CTFL_P2_ENA : 8; /*!< [23..16] Port 2 bit mask of n bits, where n is the number of
+                                             *   queues per port indicating whether the CTFL is used for
+                                             *   Cut-Through (CT) frames. When set to 1, a CT frame requires
+                                             *   a CTFL entry to be written as a CT frame in the output
+                                             *   memory.                                                                   */
+            uint32_t : 8;
+        } MMCTL_CTFL_P0_3_ENA_b;
+    };
+    __IM uint32_t RESERVED93[6];
+
+    union
+    {
+        __IOM uint32_t MMCTL_YELLOW_BYTE_LENGTH_P[3]; /*!< (@ 0x00003B20) Port [0..2] Yellow Period Byte Length Register            */
+
+        struct
+        {
+            uint32_t                  : 2;
+            __IOM uint32_t YELLOW_LEN : 14; /*!< [15..2] Length in bytes of the YELLOW period for port n. Determines
+                                             *   whether a frame can be transmitted before the YELLOW period
+                                             *   expires. The value is programmed in increments of 4 bytes
+                                             *   excluding the MAC overhead (IPG, Preamble and FCS if appended)
+                                             *   of the frame.                                                             */
+            __IOM uint32_t YLEN_EN : 1;     /*!< [16..16] When set to 1, enables transmission when OUT_CT_ENA
+                                             *   is low only if the frame length is less than YELLOW_LEN.
+                                             *   If cleared, YELLOW_LEN is ignored and frames are always
+                                             *   transmitted in SF mode when OUT_CT_ENA is 0.                              */
+            uint32_t : 15;
+        } MMCTL_YELLOW_BYTE_LENGTH_P_b[3];
+    };
+    __IM uint32_t RESERVED94[5];
+
+    union
+    {
+        __IOM uint32_t MMCTL_POOL0_CTR; /*!< (@ 0x00003B40) Memory Pool Counter (n = 0 to 1)                           */
+
+        struct
+        {
+            __IOM uint32_t CELLS : 10;  /*!< [9..0] Memory pool configuration for pool n. Configures, in
+                                         *   cells, the size of each memory pool.                                      */
+            uint32_t           : 6;
+            __IM uint32_t USED : 10;    /*!< [25..16] Reports the current available number of used cells
+                                         *   for this memory pool. The used number of free cells can
+                                         *   be calculated as CELLS - USED.                                          */
+            uint32_t : 6;
+        } MMCTL_POOL0_CTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_POOL1_CTR; /*!< (@ 0x00003B44) Memory Pool Counter (n = 0 to 1)                           */
+
+        struct
+        {
+            __IOM uint32_t CELLS : 10;  /*!< [9..0] Memory pool configuration for pool n. Configures, in
+                                         *   cells, the size of each memory pool.                                      */
+            uint32_t           : 6;
+            __IM uint32_t USED : 10;    /*!< [25..16] Reports the current available number of used cells
+                                         *   for this memory pool. The used number of free cells can
+                                         *   be calculated as CELLS - USED.                                          */
+            uint32_t : 6;
+        } MMCTL_POOL1_CTR_b;
+    };
+    __IM uint32_t RESERVED95[6];
+
+    union
+    {
+        __IOM uint32_t MMCTL_POOL_GLOBAL; /*!< (@ 0x00003B60) Memory Pool Configuration Register                         */
+
+        struct
+        {
+            __IOM uint32_t CELLS : 10;    /*!< [9..0] Memory pool configuration for the global pool. Configures,
+                                           *   in cells, the size of the global shared pool.                             */
+            uint32_t           : 6;
+            __IM uint32_t USED : 10;      /*!< [25..16] Reports the current number of used cells for the global
+                                           *   shared pool. The used number of free cells can be calculated
+                                           *   as CELLS - USED.                                                        */
+            uint32_t : 6;
+        } MMCTL_POOL_GLOBAL_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMCTL_POOL_STATUS;  /*!< (@ 0x00003B64) Memory Pool Status Register                                */
+
+        struct
+        {
+            __IM uint32_t QUEUE_FULL : 8; /*!< [7..0] Per-queue pool full indication. Indicates for each queue
+                                           *   whether all the blocks in the corresponding pool and global
+                                           *   pool are allocated.                                                       */
+            uint32_t : 24;
+        } MMCTL_POOL_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_POOL_QMAP; /*!< (@ 0x00003B68) Queue MAP Register                                         */
+
+        struct
+        {
+            __IOM uint32_t Q0_MAP : 1;  /*!< [0..0] Queue 0 Memory Pool                                                */
+            uint32_t              : 2;
+            __IOM uint32_t Q0_ENA : 1;  /*!< [3..3] Queue 0 Memory Pool Enabled                                        */
+            __IOM uint32_t Q1_MAP : 1;  /*!< [4..4] Queue 1 Memory Pool                                                */
+            uint32_t              : 2;
+            __IOM uint32_t Q1_ENA : 1;  /*!< [7..7] Queue 1 Memory Pool Enabled                                        */
+            __IOM uint32_t Q2_MAP : 1;  /*!< [8..8] Queue 2 Memory Pool                                                */
+            uint32_t              : 2;
+            __IOM uint32_t Q2_ENA : 1;  /*!< [11..11] Queue 2 Memory Pool Enabled                                      */
+            __IOM uint32_t Q3_MAP : 1;  /*!< [12..12] Queue 3 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q3_ENA : 1;  /*!< [15..15] Queue 3 Memory Pool Enabled                                      */
+            __IOM uint32_t Q4_MAP : 1;  /*!< [16..16] Queue 4 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q4_ENA : 1;  /*!< [19..19] Queue 4 Memory Pool Enabled                                      */
+            __IOM uint32_t Q5_MAP : 1;  /*!< [20..20] Queue 5 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q5_ENA : 1;  /*!< [23..23] Queue 5 Memory Pool Enabled                                      */
+            __IOM uint32_t Q6_MAP : 1;  /*!< [24..24] Queue 6 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q6_ENA : 1;  /*!< [27..27] Queue 6 Memory Pool Enabled                                      */
+            __IOM uint32_t Q7_MAP : 1;  /*!< [28..28] Queue 7 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q7_ENA : 1;  /*!< [31..31] Queue 7 Memory Pool Enabled                                      */
+        } MMCTL_POOL_QMAP_b;
+    };
+
+    union
+    {
+        __OM uint32_t MMCTL_QGATE;         /*!< (@ 0x00003B6C) Queue Gate State Register                                  */
+
+        struct
+        {
+            __OM uint32_t PORT_MASK : 4;   /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue
+                                            *   gate state is changed for that port as indicated by QUEUE_GATE.           */
+            uint32_t                 : 12;
+            __OM uint32_t QUEUE_GATE : 16; /*!< [31..16] 2-bit per queue indicating the action to be performed
+                                            *   on each queue of the ports indicated by PORT_MASK.                        */
+        } MMCTL_QGATE_b;
+    };
+
+    union
+    {
+        __OM uint32_t MMCTL_QTRIG;        /*!< (@ 0x00003B70) Queue Trigger Register                                     */
+
+        struct
+        {
+            __OM uint32_t PORT_MASK : 4;  /*!< [3..0] Per-port bit mask. When set to 1 for a port, a frame
+                                           *   is triggered from the closed queues indicated by QUEUE_TRIG.              */
+            uint32_t                 : 12;
+            __OM uint32_t QUEUE_TRIG : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
+                                           *   is to be transmitted from the ports indicated by PORT_MASK.
+                                           *   When set to 1, a single frame is transmitted per indicated
+                                           *   port in PORT_MASK among the queues indicated by QUEUE_TRIG.               */
+            uint32_t : 8;
+        } MMCTL_QTRIG_b;
+    };
+
+    union
+    {
+        __OM uint32_t MMCTL_QFLUSH;       /*!< (@ 0x00003B74) Flush Event Select Register                                */
+
+        struct
+        {
+            __OM uint32_t PORT_MASK : 4;  /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue
+                                           *   flush status is changed for that port for the queues indicated
+                                           *   in QUEUE_MASK.                                                            */
+            uint32_t                 : 12;
+            __OM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1 bit per queue indicating for which queues of the
+                                           *   ports indicated by PORT_MASK the flush state is changed
+                                           *   as indicated in ACTION.                                                   */
+            __OM uint32_t ACTION : 2;     /*!< [25..24] Selects the flush state for the queues indicated by
+                                           *   QUEUE_MASK in the ports indicated by PORT_MASK. Possible
+                                           *   actions are:                                                              */
+            uint32_t : 6;
+        } MMCTL_QFLUSH_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMCTL_QCLOSED_STATUS_P0_3; /*!< (@ 0x00003B78) Queue Closed Status Register                               */
+
+        struct
+        {
+            __IM uint32_t P0_STATUS : 8;         /*!< [7..0] Per-queue closed status of Port 0 (1-bit per queue).
+                                                  *   A 0 indicates that the queue is open (enabled), and a 1
+                                                  *   indicates that the queue is closed (disabled).                            */
+            __IM uint32_t P1_STATUS : 8;         /*!< [15..8] Per-queue closed status of Port 1 (1-bit per queue).
+                                                  *   A 0 indicates that the queue is open (enabled), and a 1
+                                                  *   indicates that the queue is closed (disabled).                            */
+            __IM uint32_t P2_STATUS : 8;         /*!< [23..16] Per-queue closed status of Port 2 (1-bit per queue).
+                                                  *   A 0 indicates that the queue is open (enabled), and a 1
+                                                  *   indicates that the queue is closed (disabled).                            */
+            uint32_t : 8;
+        } MMCTL_QCLOSED_STATUS_P0_3_b;
+    };
+    __IM uint32_t RESERVED96;
+
+    union
+    {
+        __IOM uint32_t MMCTL_1FRAME_MODE_P[3]; /*!< (@ 0x00003B80) Port [0..2] 1-Frame Mode Configuration Register            */
+
+        struct
+        {
+            __IOM uint32_t Q_1FRAME_ENA : 8;   /*!< [7..0] 1 bit per queue. Setting a bit to 1 enables the 1-frame
+                                                *   mode for that queue for port n. In this mode, only one
+                                                *   frame is allowed in the queue. If a new frame is received,
+                                                *   the old frame is discarded.                                               */
+            uint32_t                 : 8;
+            __IOM uint32_t Q_BUF_ENA : 8;      /*!< [23..16] 1 bit per queue. Setting a bit to 1 enables the buffer
+                                                *   mode behavior for that queue for port n. This mode requires
+                                                *   also that Q_1FRAME_ENA is set to 1.                                       */
+            uint32_t : 8;
+        } MMCTL_1FRAME_MODE_P_b[3];
+    };
+    __IM uint32_t RESERVED97[5];
+
+    union
+    {
+        __IM uint32_t MMCTL_P0_3_QUEUE_STATUS; /*!< (@ 0x00003BA0) Queue Status Indicator                                     */
+
+        struct
+        {
+            __IM uint32_t P0_Q_STATUS : 8;     /*!< [7..0] Port 0 Per-Queue Bit Indication                                    */
+            __IM uint32_t P1_Q_STATUS : 8;     /*!< [15..8] Port 1 Per-Queue Bit Indication                                   */
+            __IM uint32_t P2_Q_STATUS : 8;     /*!< [23..16] Port 2 Per-Queue Bit Indication                                  */
+            uint32_t                  : 8;
+        } MMCTL_P0_3_QUEUE_STATUS_b;
+    };
+    __IM uint32_t RESERVED98;
+
+    union
+    {
+        __IM uint32_t MMCTL_P0_3_FLUSH_STATUS; /*!< (@ 0x00003BA8) Queue Flush Status Indicator                               */
+
+        struct
+        {
+            __IM uint32_t P0_F_STATUS : 8;     /*!< [7..0] Port 0 per-Queue Bit Indication on whether the queue
+                                                *   is flushing frames (read 1) or not (read 0).                              */
+            __IM uint32_t P1_F_STATUS : 8;     /*!< [15..8] Port 1 per-Queue Bit Indication on whether the queue
+                                                *   is flushing frames (read 1) or not (read 0).                              */
+            __IM uint32_t P2_F_STATUS : 8;     /*!< [23..16] Port 2 per-Queue Bit Indication on whether the queue
+                                                *   is flushing frames (read 1) or not (read 0).                              */
+            uint32_t : 8;
+        } MMCTL_P0_3_FLUSH_STATUS_b;
+    };
+    __IM uint32_t RESERVED99;
+
+    union
+    {
+        __IOM uint32_t MMCTL_DLY_QTRIGGER_CTRL; /*!< (@ 0x00003BB0) Delayed Queue Trigger Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t DELAY_TIME : 30;     /*!< [29..0] 30-bit time in nanoseconds indicates the time after
+                                                 *   the trigger request from the pattern matchers to generate
+                                                 *   the event.                                                                */
+            __IOM uint32_t TIMER_SEL : 1;       /*!< [30..30] Select the source timer to use for calculating the
+                                                 *   time.                                                                     */
+            uint32_t : 1;
+        } MMCTL_DLY_QTRIGGER_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_PREEMPT_QUEUES;      /*!< (@ 0x00003BB4) Preemptable Queues Configures Register                     */
+
+        struct
+        {
+            __IOM uint32_t PREEMPT_ENA : 8;       /*!< [7..0] Per-queue enable bit to configure which queues are used
+                                                   *   for preemptable traffic. Set to 1 the corresponding bit
+                                                   *   to configure a queue to be preemptable.                                   */
+            __IOM uint32_t PREEMPT_ON_QCLOSE : 8; /*!< [15..8] Per-queue configuration bit to enable preempting a frame
+                                                   *   when the queue goes from OPEN to CLOSED. When the corresponding
+                                                   *   bit is set to 1 and the queue is configured as preemptable
+                                                   *   in PREEMPT_ENA, a queue close event causes the current
+                                                   *   frame to be preempted, if preemption is operational.                      */
+            uint32_t : 16;
+        } MMCTL_PREEMPT_QUEUES_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_HOLD_CONTROL;         /*!< (@ 0x00003BB8) Request Preemption Register                                */
+
+        struct
+        {
+            __IOM uint32_t Q_HOLD_REQ_FORCE : 3;   /*!< [2..0] A per-port bit that forces a preempt request using MM_CTL.request
+                                                    *   (hold_req). When this bit is set to 1, it overrides other
+                                                    *   sources of hold request, including the TDMA controller.                   */
+            uint32_t                          : 13;
+            __IOM uint32_t Q_HOLD_REQ_RELEASE : 3; /*!< [18..16] A per-port bit that forces a release of preemption
+                                                    *   request using MM_CTL.request (hold_req). When this bit
+                                                    *   is set to 1, it overrides other sources of hold request,
+                                                    *   including the TDMA controller and Q_HOLD_REQ_FORCE[2:0].                  */
+            uint32_t : 13;
+        } MMCTL_HOLD_CONTROL_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMCTL_PREEMPT_STATUS;   /*!< (@ 0x00003BBC) Preemption State Register                                  */
+
+        struct
+        {
+            __IM uint32_t PREEMPT_STATE : 3;  /*!< [2..0] A per-port bit that indicates if a port is in a preempted
+                                               *   state. This is a real-time indication meant for debugging.                */
+            uint32_t                     : 13;
+            __IM uint32_t HOLD_REQ_STATE : 3; /*!< [18..16] A per-port bit that indicates if a port is preempted
+                                               *   using MM_CTL.request (hold_req). This is a real-time indication
+                                               *   meant for debugging.                                                      */
+            uint32_t : 13;
+        } MMCTL_PREEMPT_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_CQF_CTRL_P[4];  /*!< (@ 0x00003BC0) Port [0..3] Cyclic Queuing and Forwarding Control
+                                              *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t PRIO_ENABLE0 : 8; /*!< [7..0] A per-queue enable to select which ingress priorities
+                                              *   are queued in the two CQF queues.                                         */
+            __IOM uint32_t QUEUE_SEL0 : 3;   /*!< [10..8] Select which two physical queues are used for CQF. The
+                                              *   queues used are QUEUE_SEL0 and QUEUE_SEL0 + 1. Frames are
+                                              *   written into QUEUE_SEL0 when the gate control selected
+                                              *   with GATE_SEL0 is 0, and into QUEUE_SEL0 + 1 when the gate
+                                              *   control is 1.                                                             */
+            __IOM uint32_t GATE_SEL0 : 3;    /*!< [13..11] Select which gate control signal is used for selecting
+                                              *   the output queue (these signals are the same as the ETHSW_TDMAOUT
+                                              *   pins).                                                                    */
+            __IOM uint32_t USE_SOP0 : 1;     /*!< [14..14] When set to 1, the CFQ queue is determined when the
+                                              *   SOP is received at the frame writer in the memory controller.
+                                              *   When set to 0, the queue is determined when the EOP is
+                                              *   received at the frame writer.                                             */
+            __IOM uint32_t REF_SEL0 : 1;     /*!< [15..15] Select whether the gate control signal used for the
+                                              *   CQF group is based on the egress port when set to 0, or
+                                              *   the ingress port when set to 1.                                           */
+            uint32_t : 16;
+        } MMCTL_CQF_CTRL_P_b[4];
+    };
+    __IM uint32_t RESERVED100[4];
+
+    union
+    {
+        __IM uint32_t MMCTL_P0_3_QCLOSED_NONEMPTY; /*!< (@ 0x00003BE0) Port Queue Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t P0_Q_STATUS : 8;         /*!< [7..0] Port 0 per-queue bit indication on whether the queue
+                                                    *   transitioned from open to closed state while frames were
+                                                    *   still queued.                                                             */
+            __IM uint32_t P1_Q_STATUS : 8;         /*!< [15..8] Port 1 per-queue bit indication on whether the queue
+                                                    *   transitioned from open to closed state while frames were
+                                                    *   still queued.                                                             */
+            __IM uint32_t P2_Q_STATUS : 8;         /*!< [23..16] Port 2 per-queue bit indication on whether the queue
+                                                    *   transitioned from open to closed state while frames were
+                                                    *   still queued.                                                             */
+            __IM uint32_t P3_Q_STATUS : 8;         /*!< [31..24] Port 3 per-queue bit indication on whether the queue
+                                                    *   transitioned from open to closed state while frames were
+                                                    *   still queued.                                                             */
+        } MMCTL_P0_3_QCLOSED_NONEMPTY_b;
+    };
+    __IM uint32_t RESERVED101;
+
+    union
+    {
+        __IOM uint32_t MMCTL_PREEMPT_EXTRA;   /*!< (@ 0x00003BE8) Frame Preemption Extra Configuration Register              */
+
+        struct
+        {
+            __IOM uint32_t MIN_PFRM_ADJ : 4;  /*!< [3..0] Adjust the minimum mPacket length, in increments of 4
+                                               *   bytes.                                                                    */
+            __IOM uint32_t LAST_PFRM_ADJ : 4; /*!< [7..4] Adjust the preemptable threshold when reaching the end
+                                               *   of the frame, in increments of 4 bytes. Incrementing this
+                                               *   value increments the length of the last mPacket.                          */
+            uint32_t : 24;
+        } MMCTL_PREEMPT_EXTRA_b;
+    };
+    __IM uint32_t RESERVED102[5];
+
+    union
+    {
+        __IOM uint32_t DLR_CONTROL;             /*!< (@ 0x00003C00) DLR Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t ENABLE : 1;          /*!< [0..0] Enable DLR extension module. When set, the DLR module
+                                                 *   becomes active. When DLR is enabled, the LOOP_FILTER_ENA
+                                                 *   must also be enabled for proper DLR operation.                            */
+            __IOM uint32_t AUTOFLUSH : 1;       /*!< [1..1] Enable automatic flushing of unicast entries in address
+                                                 *   table if ring reconfiguration occurs (see also DLR interrupt
+                                                 *   IRQ_flush_macaddr_ena in DLR_IRQ_CONTROL).                                */
+            __IOM uint32_t LOOP_FILTER_ENA : 1; /*!< [2..2] Enable the loop filter function. When set to 1, the ingress
+                                                 *   loop filter is enabled. This can be enabled regardless
+                                                 *   of the DLR ENABLE state, allowing the loop filter function
+                                                 *   to operate when DLR is not used.                                          */
+            uint32_t                    : 1;
+            __IOM uint32_t IGNORE_INVTM : 1;    /*!< [4..4] Enable ignore beacon frames with invalid timeout timer.
+                                                 *   When enabled (set to 1) frames with timeout timer value
+                                                 *   not within a range of 200 microseconds to 500 milliseconds
+                                                 *   are ignored and parameters are not locally stored or considered
+                                                 *   for state transitions. The invalid timeout timer value
+                                                 *   is always stored within the DLR_INV_TMOUT register irrespective
+                                                 *   of the value of this bit. Ignored frames are forwarded
+                                                 *   normally.                                                                 */
+            uint32_t               : 3;
+            __IOM uint32_t US_TIME : 12;        /*!< [19..8] Number of clock cycles required for 1 microsecond for
+                                                 *   the switch operating clock. This LSI operates at 200 MHz,
+                                                 *   therefore this register must be set to 0xC8. The value
+                                                 *   after reset must be changed.                                              */
+            uint32_t : 12;
+        } DLR_CONTROL_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_STATUS;             /*!< (@ 0x00003C04) DLR Status Register                                        */
+
+        struct
+        {
+            __IM uint32_t LastBcnRcvPort : 2; /*!< [1..0] Last Beacon Receive Port                                           */
+            uint32_t                     : 6;
+            __IM uint32_t NODE_STATE     : 8; /*!< [15..8] Local Node Current State                                          */
+            __IM uint32_t LINK_STATUS    : 2; /*!< [17..16] Link Status                                                      */
+            uint32_t                     : 6;
+            __IM uint32_t TOPOLOGY       : 8; /*!< [31..24] Current Network Topology                                         */
+        } DLR_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_ETH_TYP;          /*!< (@ 0x00003C08) DLR Ethernet Type Register                                 */
+
+        struct
+        {
+            __IOM uint32_t DLR_ETH_TYP : 16; /*!< [15..0] Ethernet type to compare for DLR frame detection (initial
+                                              *   value is 0x80E1)                                                          */
+            uint32_t : 16;
+        } DLR_ETH_TYP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_IRQ_CONTROL;               /*!< (@ 0x00003C0C) DLR Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t IRQ_state_chng_ena    : 1; /*!< [0..0] Enable Interrupt for State Change                                  */
+            __IOM uint32_t IRQ_flush_macaddr_ena : 1; /*!< [1..1] Enable Flush Local MAC Address Table Interrupt.                    */
+            __IOM uint32_t IRQ_stop_nbchk0_ena   : 1; /*!< [2..2] Enable Stop Request Neighbor Check Timeout Timer Interrupt
+                                                       *   for Port 0.                                                               */
+            __IOM uint32_t IRQ_stop_nbchk1_ena : 1;   /*!< [3..3] Enable Stop Request Neighbor Check Timeout Timer Interrupt
+                                                       *   for Port 1.                                                               */
+            __IOM uint32_t IRQ_bec_tmr0_exp_ena : 1;  /*!< [4..4] IRQ_bec_tmr0_exp_ena                                               */
+            __IOM uint32_t IRQ_bec_tmr1_exp_ena : 1;  /*!< [5..5] Enable Interrupt on Beacon Timeout Timer Expire for Port
+                                                       *   1.                                                                        */
+            __IOM uint32_t IRQ_supr_chng_ena  : 1;    /*!< [6..6] Enable Interrupt on Ring Supervisor Change.                        */
+            __IOM uint32_t IRQ_link_chng0_ena : 1;    /*!< [7..7] Enable Link Status Change Interrupt Event for Port 0.              */
+            __IOM uint32_t IRQ_link_chng1_ena : 1;    /*!< [8..8] Enable Link Status Change Interrupt Event for Port 1.              */
+            __IOM uint32_t IRQ_sup_ignord_ena : 1;    /*!< [9..9] Enable interrupt on beacon frame detection from a supervisor
+                                                       *   with lower precedence than the current ring supervisor
+                                                       *   or lower numeric value for MAC address when precedence
+                                                       *   is same.                                                                  */
+            __IOM uint32_t IRQ_ip_addr_chng_ena : 1;  /*!< [10..10] Enable interrupt on IP address change detection within
+                                                       *   beacon frame from ring supervisor.                                        */
+            __IOM uint32_t IRQ_invalid_tmr_ena : 1;   /*!< [11..11] Enable interrupt on invalid range for beacon timeout
+                                                       *   timer value detection.                                                    */
+            __IOM uint32_t IRQ_bec_rcv0_ena : 1;      /*!< [12..12] Enable interrupt on beacon frame detection on port
+                                                       *   0.                                                                        */
+            __IOM uint32_t IRQ_bec_rcv1_ena : 1;      /*!< [13..13] Enable interrupt on beacon frame detection on port
+                                                       *   1.                                                                        */
+            __IOM uint32_t IRQ_frm_dscrd0 : 1;        /*!< [14..14] Enable interrupt on frame discard due to source address
+                                                       *   match with the local address on port 0.                                   */
+            __IOM uint32_t IRQ_frm_dscrd1 : 1;        /*!< [15..15] Enable Interrupt on Frame discard due to source address
+                                                       *   match with the local address on port 1.                                   */
+            uint32_t                  : 13;
+            __IOM uint32_t low_int_en : 1;            /*!< [29..29] Enable active-low interrupt. Asserted to use active-low
+                                                       *   interrupt signal instead of active-high interrupt signal.                 */
+            __OM uint32_t atomic_OR : 1;              /*!< [30..30] When set during a register-write, the enable bits are
+                                                       *   ORed into the current setting of the register. By writing
+                                                       *   this bit at the same time, only the target bit can be set
+                                                       *   to 1.                                                                     */
+            __OM uint32_t atomic_AND : 1;             /*!< [31..31] When set during a register-write, the enable bits are
+                                                       *   ANDed with the current setting of the register. By writing
+                                                       *   this bit at the same time, only the target bit can be set
+                                                       *   to 0.                                                                     */
+        } DLR_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_IRQ_STAT_ACK;                /*!< (@ 0x00003C10) DLR Interrupt Status/ACK Register                          */
+
+        struct
+        {
+            __IOM uint32_t state_chng_IRQ_pending : 1;  /*!< [0..0] Latched State Change Event                                         */
+            __IOM uint32_t flush_IRQ_pending      : 1;  /*!< [1..1] Latched Flush Event for MAC Address Learning Table                 */
+            __IOM uint32_t nbchk0_IRQ_pending     : 1;  /*!< [2..2] Stop Request Event for Neighbor Check Timeout Timer for
+                                                         *   Port 0                                                                    */
+            __IOM uint32_t nbchk1_IRQ_pending : 1;      /*!< [3..3] Stop Request Event for Neighbor Check Timeout Timer for
+                                                         *   Port 1                                                                    */
+            __IOM uint32_t bec_tmr0_IRQ_pending   : 1;  /*!< [4..4] Beacon Timeout Timer Expire Event for Port 0                       */
+            __IOM uint32_t bec_tmr1_IRQ_pending   : 1;  /*!< [5..5] Beacon Timeout Timer Expire Event for Port 1                       */
+            __IOM uint32_t supr_chng_IRQ_pending  : 1;  /*!< [6..6] Latched Supervisor Change Event                                    */
+            __IOM uint32_t Link0_IRQ_pending      : 1;  /*!< [7..7] Latched Link Status Change Event for Port 0                        */
+            __IOM uint32_t Link1_IRQ_pending      : 1;  /*!< [8..8] Latched Link Status Change Event for Port 1                        */
+            __IOM uint32_t sup_ignord_IRQ_pending : 1;  /*!< [9..9] Latched Event for Beacon Frame Detection from Ignored
+                                                         *   Supervisor                                                                */
+            __IOM uint32_t ip_chng_IRQ_pending     : 1; /*!< [10..10] Latched IP Address Change Event                                  */
+            __IOM uint32_t invalid_tmr_IRQ_pending : 1; /*!< [11..11] Latched Event on Invalid Beacon Timeout Timer Value
+                                                         *  Detection Within Beacon Frame on Port 0 or Port 1                         */
+            __IOM uint32_t bec_rcv0_IRQ_pending   : 1;  /*!< [12..12] Latched Event on Beacon Frame Detection on Port 0                */
+            __IOM uint32_t bec_rcv1_IRQ_pending   : 1;  /*!< [13..13] Latched Event on Beacon Frame Detection on Port 1                */
+            __IOM uint32_t frm_dscrd0_IRQ_pending : 1;  /*!< [14..14] Latched Event on Frame Discard Due to Source Address
+                                                         *   Match with the Local Address on Port 0 (Loop Filter)                      */
+            __IOM uint32_t frm_dscrd1_IRQ_pending : 1;  /*!< [15..15] Latched Event on Frame Discard Due to Source Address
+                                                         *   Match with the Local Address on Port 1 (Loop Filter)                      */
+            uint32_t : 16;
+        } DLR_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_LOC_MAClo;    /*!< (@ 0x00003C14) DLR Local MAC Address Low Register                         */
+
+        struct
+        {
+            __IOM uint32_t LOC_MAC : 32; /*!< [31..0] First 4 octets of the Local MAC address for loop filter           */
+        } DLR_LOC_MAClo_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_LOC_MAChi;    /*!< (@ 0x00003C18) DLR Local MAC Address High Register                        */
+
+        struct
+        {
+            __IOM uint32_t LOC_MAC : 16; /*!< [15..0] Last 2 octets of local MAC address for loop filter                */
+            uint32_t               : 16;
+        } DLR_LOC_MAChi_b;
+    };
+    __IM uint32_t RESERVED103;
+
+    union
+    {
+        __IM uint32_t DLR_SUPR_MAClo;    /*!< (@ 0x00003C20) DLR Supervisor MAC Address Low Register                    */
+
+        struct
+        {
+            __IM uint32_t SUPR_MAC : 32; /*!< [31..0] First 4 octets of the active ring supervisor of the
+                                          *   MAC address extracted from the Source Address field of
+                                          *   the beacon frame.                                                         */
+        } DLR_SUPR_MAClo_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_SUPR_MAChi;    /*!< (@ 0x00003C24) DLR Supervisor MAC Address High Register                   */
+
+        struct
+        {
+            __IM uint32_t SUPR_MAC : 16; /*!< [15..0] Last 2 octets of the active ring supervisor of the MAC
+                                          *   address extracted from the Source Address field of the
+                                          *   beacon frame.                                                             */
+            __IM uint32_t PRECE : 8;     /*!< [23..16] Precedence value of the ring supervisor extracted from
+                                          *   the Supervisor precedence field of the beacon frame.                      */
+            uint32_t : 8;
+        } DLR_SUPR_MAChi_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_STATE_VLAN;     /*!< (@ 0x00003C28) DLR Ring Status/VLAN Register                              */
+
+        struct
+        {
+            __IM uint32_t RINGSTAT : 8;   /*!< [7..0] DLR ring state extracted from the Ring State field of
+                                           *   the beacon frame.                                                         */
+            __IM uint32_t VLANVALID : 1;  /*!< [8..8] VLAN Valid                                                         */
+            uint32_t                : 7;
+            __IM uint32_t VLANINFO  : 16; /*!< [31..16] IEEE 802.1Q VLAN Tag control field extracted from the
+                                           *   VLAN info field of the beacon frame.                                      */
+        } DLR_STATE_VLAN_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_BEC_TMOUT;      /*!< (@ 0x00003C2C) DLR Beacon Timeout Register                                */
+
+        struct
+        {
+            __IM uint32_t BEC_TMOUT : 32; /*!< [31..0] Beacon timeout timer value extracted from the Beacon
+                                           *   Timeout in microseconds field of the beacon frame.                        */
+        } DLR_BEC_TMOUT_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_BEC_INTRVL;      /*!< (@ 0x00003C30) DLR Beacon Interval Register                               */
+
+        struct
+        {
+            __IM uint32_t BEC_INTRVL : 32; /*!< [31..0] Beacon interval extracted from the Beacon Interval field
+                                            *   of the beacon frame                                                       */
+        } DLR_BEC_INTRVL_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_SUPR_IPADR;      /*!< (@ 0x00003C34) DLR Supervisor IP Address Register                         */
+
+        struct
+        {
+            __IM uint32_t SUPR_IPADR : 32; /*!< [31..0] IP address of the ring supervisor extracted from the
+                                            *   Source IP address field of the beacon frame. A value of
+                                            *   0x0 can be received when supervisor has no IP address.                    */
+        } DLR_SUPR_IPADR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_ETH_STYP_VER; /*!< (@ 0x00003C38) DLR Sub Type/Protocol Version Register                     */
+
+        struct
+        {
+            __IM uint32_t SUBTYPE : 8;  /*!< [7..0] DLR Ring Ether Sub Type extracted from the Ring Sub Type
+                                         *   field of the beacon frame.                                                */
+            __IM uint32_t PROTVER : 8;  /*!< [15..8] DLR Ring Protocol Version extracted from the Ring Protocol
+                                         *   Version field of the beacon frame.                                        */
+            __IM uint32_t SPORT : 8;    /*!< [23..16] Source port extracted from the Source Port field of
+                                         *   the beacon frame.                                                         */
+            uint32_t : 8;
+        } DLR_ETH_STYP_VER_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_INV_TMOUT;      /*!< (@ 0x00003C3C) DLR Beacon Timeout Timer Register                          */
+
+        struct
+        {
+            __IM uint32_t INV_TMOUT : 32; /*!< [31..0] Last out of range Beacon timeout timer value extracted
+                                           *   from beacon frame on any of the port.                                     */
+        } DLR_INV_TMOUT_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_SEQ_ID;      /*!< (@ 0x00003C40) DLR Sequence ID Register                                   */
+
+        struct
+        {
+            __IM uint32_t SEQ_ID : 32; /*!< [31..0] Sequence ID of the last beacon frame extracted from
+                                        *   the Sequence ID field of the beacon frame on port 0 or
+                                        *   port 1. Sequence ID of the ignored frames is not stored.                  */
+        } DLR_SEQ_ID_b;
+    };
+    __IM uint32_t RESERVED104[5];
+
+    union
+    {
+        __IOM uint32_t DLR_DSTlo;        /*!< (@ 0x00003C58) DLR Beacon Destination Address Low Register                */
+
+        struct
+        {
+            __IOM uint32_t DLR_DST : 32; /*!< [31..0] First 4 octets of the beacon frame destination multicast
+                                          *   address (01-21-6C-00-00-01).                                              */
+        } DLR_DSTlo_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_DSThi;        /*!< (@ 0x00003C5C) DLR Beacon Destination Address High Register               */
+
+        struct
+        {
+            __IOM uint32_t DLR_DST : 16; /*!< [15..0] Last 2 octets of the beacon frame destination multicast
+                                          *   address (01-21-6C-00-00-01).                                              */
+            uint32_t : 16;
+        } DLR_DSThi_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_RX_STAT0;      /*!< (@ 0x00003C60) DLR Received Frame Statistic Register 0                    */
+
+        struct
+        {
+            __IM uint32_t RX_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 0                        */
+        } DLR_RX_STAT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_RX_ERR_STAT0;      /*!< (@ 0x00003C64) DLR Received Frame Error Statistic Register 0              */
+
+        struct
+        {
+            __IM uint32_t RX_ERR_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port
+                                              *   0                                                                         */
+        } DLR_RX_ERR_STAT0_b;
+    };
+    __IM uint32_t RESERVED105;
+
+    union
+    {
+        __IOM uint32_t DLR_RX_LF_STAT0;     /*!< (@ 0x00003C6C) DLR Received Frame Loop Filter Statistic Register
+                                             *                  0                                                          */
+
+        struct
+        {
+            __IOM uint32_t RX_LF_STAT0 : 8; /*!< [7..0] Number of discarded frames in port 0 due to loop filtering
+                                             *   when LOOP_FILTER_ENA is set to 1. Saturates at 255.                       */
+            uint32_t : 24;
+        } DLR_RX_LF_STAT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_RX_STAT1;      /*!< (@ 0x00003C70) DLR Received Frame Statistic Register 1                    */
+
+        struct
+        {
+            __IM uint32_t RX_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 1                        */
+        } DLR_RX_STAT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_RX_ERR_STAT1;      /*!< (@ 0x00003C74) DLR Received Frame Error Statistic Register 1              */
+
+        struct
+        {
+            __IM uint32_t RX_ERR_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port
+                                              *   1                                                                         */
+        } DLR_RX_ERR_STAT1_b;
+    };
+    __IM uint32_t RESERVED106;
+
+    union
+    {
+        __IOM uint32_t DLR_RX_LF_STAT1;     /*!< (@ 0x00003C7C) DLR Received Frame Loop Filter Statistic Register
+                                             *                  1                                                          */
+
+        struct
+        {
+            __IOM uint32_t RX_LF_STAT1 : 8; /*!< [7..0] Number of discarded frames in port 1 due to loop filtering
+                                             *   when LOOP_FILTER_ENA is set to 1. Saturates at 255.                       */
+            uint32_t : 24;
+        } DLR_RX_LF_STAT1_b;
+    };
+    __IM uint32_t RESERVED107[32];
+
+    union
+    {
+        __IOM uint32_t PRP_CONFIG;               /*!< (@ 0x00003D00) PRP Configuration Register                                 */
+
+        struct
+        {
+            __IOM uint32_t PRP_ENA       : 1;    /*!< [0..0] Enable PRP Operation                                               */
+            __IOM uint32_t RX_DUP_ACCEPT : 1;    /*!< [1..1] Enable Duplicate Accept Mode of Operation at Receive               */
+            __IOM uint32_t RX_REMOVE_RCT : 1;    /*!< [2..2] Allow PRP Port RX to Remove the RCT                                */
+            __IOM uint32_t TX_RCT_MODE   : 2;    /*!< [4..3] Control Appending the RCT to Transmitted Frames on the
+                                                  *   Redundant Ports                                                           */
+            __IOM uint32_t TX_RCT_BROADCAST : 1; /*!< [5..5] Should be 1 normally.                                              */
+            __IOM uint32_t TX_RCT_MULTICAST : 1; /*!< [6..6] Should be 1 normally.                                              */
+            __IOM uint32_t TX_RCT_UNKNOWN   : 1; /*!< [7..7] Should be 1 normally.                                              */
+            __IOM uint32_t TX_RCT_1588      : 1; /*!< [8..8] Setting this bit affects IEEE 1588 frames that are forwarded
+                                                  *   through the switch (for example, when used as RedBox) to
+                                                  *   both PRP_GROUP ports. Locally generated IEEE 1588 frames
+                                                  *   (peer-delay request/response) are not affected by this
+                                                  *   setting.                                                                  */
+            __IOM uint32_t RCT_LEN_CHK_DIS : 1;  /*!< [9..9] When set to 1, disables the RCT length field checking
+                                                  *   against the actual frame length.                                          */
+            uint32_t                   : 6;
+            __IOM uint32_t PRP_AGE_ENA : 1;      /*!< [16..16] Enable History Memory Aging Timer                                */
+            uint32_t                   : 15;
+        } PRP_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_GROUP;         /*!< (@ 0x00003D04) PRP Port Group Register                                    */
+
+        struct
+        {
+            __IOM uint32_t PRP_GROUP : 3; /*!< [2..0] Defines which two ports should be treated as redundant
+                                           *   ports for PRP.                                                            */
+            uint32_t                 : 13;
+            __IOM uint32_t LANB_MASK : 3; /*!< [18..16] Defines which of the ports is considered the LAN B
+                                           *   port.                                                                     */
+            uint32_t : 13;
+        } PRP_GROUP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_SUFFIX;          /*!< (@ 0x00003D08) PRP RCT Suffix                                             */
+
+        struct
+        {
+            __IOM uint32_t PRP_SUFFIX : 16; /*!< [15..0] The Redundancy Control Trailer (RCT) suffix (initial
+                                             *   value is 0x88FB)                                                          */
+            uint32_t : 16;
+        } PRP_SUFFIX_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_LANID;      /*!< (@ 0x00003D0C) PRP LAN Identifier                                         */
+
+        struct
+        {
+            __IOM uint32_t LANAID : 4; /*!< [3..0] LAN A Identifier                                                   */
+            __IOM uint32_t LANBID : 4; /*!< [7..4] LAN B Identifier                                                   */
+            uint32_t              : 24;
+        } PRP_LANID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DUP_W;          /*!< (@ 0x00003D10) PRP Max Duplicate Detection Window Size                    */
+
+        struct
+        {
+            __IOM uint32_t DUP_W : 8;  /*!< [7..0] Maximum Duplicate Detect Window Size                               */
+            uint32_t             : 24;
+        } DUP_W_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_AGETIME;          /*!< (@ 0x00003D14) PRP Aging Time Define Register                             */
+
+        struct
+        {
+            __IOM uint32_t PRP_AGETIME : 24; /*!< [23..0] Timeout in steps of 32 switch operating clock cycles
+                                              *   to control aging of duplicate history data.                               */
+            uint32_t : 8;
+        } PRP_AGETIME_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_IRQ_CONTROL;    /*!< (@ 0x00003D18) PRP Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Enable Interrupt for Memory Error Indications.                     */
+            __IOM uint32_t WRONGLAN   : 1; /*!< [1..1] Enable interrupt for frames received at a redundant port
+                                            *   with an invalid LAN identifier in its redundancy trailer.                 */
+            __IOM uint32_t OUTOFSEQ : 1;   /*!< [2..2] Enable interrupt for frames received and accepted but
+                                            *   have an unexpected sequence number.                                       */
+            __IOM uint32_t SEQMISSING : 1; /*!< [3..3] Enable interrupt for frames received and accepted that
+                                            *   caused the history to skip a sequence number that was never
+                                            *   received (for example, a missing sequence number is being
+                                            *   ignored and is now treated as a candidate for dropping).                  */
+            uint32_t : 28;
+        } PRP_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_IRQ_STAT_ACK;   /*!< (@ 0x00003D1C) PRP Interrupt Status/ACK Register                          */
+
+        struct
+        {
+            __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Interrupt Pending Indication                                       */
+            __IOM uint32_t WRONGLAN   : 1; /*!< [1..1] This bit functions the same as MEMTOOLATE bit.                     */
+            __IOM uint32_t OUTOFSEQ   : 1; /*!< [2..2] This bit functions the same as MEMTOOLATE bit.                     */
+            __IOM uint32_t SEQMISSING : 1; /*!< [3..3] This bit functions the same as MEMTOOLATE bit.                     */
+            uint32_t                  : 28;
+        } PRP_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RM_ADDR_CTRL;           /*!< (@ 0x00003D20) PRP History Memory Transactions Control Register           */
+
+        struct
+        {
+            __IOM uint32_t address       : 12; /*!< [11..0] Memory Address for Read and Write Transactions                    */
+            uint32_t                     : 10;
+            __IOM uint32_t CLEAR_DYNAMIC : 1;  /*!< [22..22] When set to 1, scan the complete table for valid dynamic
+                                                *   history entries and deletes them (writes entry with all
+                                                *   0s).                                                                      */
+            __IOM uint32_t CLEAR_MEMORY : 1;   /*!< [23..23] When set to 1, write all memory locations with 0.                */
+            uint32_t                    : 1;
+            __IOM uint32_t WRITE        : 1;   /*!< [25..25] When set to 1, perform a Single Write Transaction.               */
+            __IOM uint32_t READ         : 1;   /*!< [26..26] When set to 1, perform Single Read Transaction.                  */
+            uint32_t                    : 2;
+            __IOM uint32_t CLEAR        : 1;   /*!< [29..29] When set to 1, write all 0s to the entry selected by
+                                                *   the given address.                                                        */
+            uint32_t           : 1;
+            __IM uint32_t BUSY : 1;            /*!< [31..31] Transaction Busy Indication                                      */
+        } RM_ADDR_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RM_DATA;          /*!< (@ 0x00003D24) PRP Memory Data Register                                   */
+
+        struct
+        {
+            __IOM uint32_t RM_DATA : 32; /*!< [31..0] Memory data register for read/write transactions controlled
+                                          *   by RM_ADDR_CTRL.                                                          */
+        } RM_DATA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RM_DATA_HI;          /*!< (@ 0x00003D28) PRP Memory Data Higher Register                            */
+
+        struct
+        {
+            __IOM uint32_t RM_DATA_HI : 32; /*!< [31..0] A Second Data Register                                            */
+        } RM_DATA_HI_b;
+    };
+
+    union
+    {
+        __IM uint32_t RM_STATUS;           /*!< (@ 0x00003D2C) PRP Memory Controller Status Indication                    */
+
+        struct
+        {
+            __IM uint32_t ageaddress : 12; /*!< [11..0] Address of an entry which the aging process inspects
+                                            *   when the aging timer expires next time.                                   */
+            uint32_t : 20;
+        } RM_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TxSeqTooLate;         /*!< (@ 0x00003D30) PRP Frame Transmission Retrieval of Failed Sequence        */
+
+        struct
+        {
+            __IOM uint32_t TxSeqTooLate : 4; /*!< [3..0] Retrieval of a Sequence Number Failed                              */
+            uint32_t                    : 28;
+        } TxSeqTooLate_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntErrWrongLanA;          /*!< (@ 0x00003D34) PRP Wrong ID LAN-A Count Register                          */
+
+        struct
+        {
+            __IM uint32_t CntErrWrongLanA : 32; /*!< [31..0] Valid frames received on LAN A which have an RCT (valid
+                                                 *   length + suffix) but LAN ID is not matching LAN A.                        */
+        } CntErrWrongLanA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntErrWrongLanB;          /*!< (@ 0x00003D38) PRP Wrong ID LAN-B Count Register                          */
+
+        struct
+        {
+            __IM uint32_t CntErrWrongLanB : 32; /*!< [31..0] Valid frames received on LAN B which have an RCT (valid
+                                                 *   length + suffix) but LAN ID is not matching LAN B.                        */
+        } CntErrWrongLanB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntDupLanA;          /*!< (@ 0x00003D3C) PRP Duplicate LAN-A Count Register                         */
+
+        struct
+        {
+            __IM uint32_t CntDupLanA : 32; /*!< [31..0] Valid frames received on LAN A that were dropped by
+                                            *   duplicate detection.                                                      */
+        } CntDupLanA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntDupLanB;          /*!< (@ 0x00003D40) PRP Duplicate LAN-B Count Register                         */
+
+        struct
+        {
+            __IM uint32_t CntDupLanB : 32; /*!< [31..0] Valid frames received on LAN B that were dropped by
+                                            *   duplicate detection.                                                      */
+        } CntDupLanB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntOutOfSeqLowA;          /*!< (@ 0x00003D44) PRP Sequence Error Low LAN-A Count Register                */
+
+        struct
+        {
+            __IM uint32_t CntOutOfSeqLowA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with a sequence
+                                                 *   number less than last window (DUP_W).                                     */
+        } CntOutOfSeqLowA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntOutOfSeqLowB;          /*!< (@ 0x00003D48) PRP Sequence Error Low LAN-B Count Register                */
+
+        struct
+        {
+            __IM uint32_t CntOutOfSeqLowB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with a sequence
+                                                 *   number less than last window (DUP_W).                                     */
+        } CntOutOfSeqLowB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntOutOfSeqA;          /*!< (@ 0x00003D4C) PRP Sequence Error LAN-A Count Register                    */
+
+        struct
+        {
+            __IM uint32_t CntOutOfSeqA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with an
+                                              *   unexpected sequence number.                                               */
+        } CntOutOfSeqA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntOutOfSeqB;          /*!< (@ 0x00003D50) PRP Sequence Error LAN-B Count Register                    */
+
+        struct
+        {
+            __IM uint32_t CntOutOfSeqB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with an
+                                              *   unexpected sequence number.                                               */
+        } CntOutOfSeqB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntAcceptA;          /*!< (@ 0x00003D54) PRP Valid Frame LAN-A Count Register                       */
+
+        struct
+        {
+            __IM uint32_t CntAcceptA : 32; /*!< [31..0] Valid frames received on LAN A which had a valid sequence
+                                            *   number in the expected range.                                             */
+        } CntAcceptA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntAcceptB;          /*!< (@ 0x00003D58) PRP Valid Frame LAN-B Count Register                       */
+
+        struct
+        {
+            __IM uint32_t CntAcceptB : 32; /*!< [31..0] Valid frames received on LAN B which had a valid sequence
+                                            *   number in the expected range.                                             */
+        } CntAcceptB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntMissing;          /*!< (@ 0x00003D5C) PRP Drop History Adjustment Count                          */
+
+        struct
+        {
+            __IM uint32_t CntMissing : 32; /*!< [31..0] Indicates adjustment of the drop history as a frame
+                                            *   was received with a sequence number of expected + history
+                                            + 1. This occurs if the same frame was dropped in both
+                                            +   LAN segments (one sequence number is missing) and the history
+                                            +   is now extended beyond that sequence number (causing it
+                                            +   to be treated as drop allowed).                                           */
+        } CntMissing_b;
+    };
+    __IM uint32_t RESERVED108[40];
+
+    union
+    {
+        __IOM uint32_t HUB_CONFIG;             /*!< (@ 0x00003E00) HUB Configuration Register                                 */
+
+        struct
+        {
+            __IOM uint32_t HUB_ENA        : 1; /*!< [0..0] Enable Integrated HUB Operation                                    */
+            __IOM uint32_t RETRANSMIT_ENA : 1; /*!< [1..1] Enable Hub Retransmit Capability                                   */
+            __IOM uint32_t TRIGGER_MODE   : 1; /*!< [2..2] Enable Single Frame Trigger Mode                                   */
+            __IOM uint32_t HUB_ISOLATE    : 1; /*!< [3..3] Isolate all hub ports from the other ports of the switch
+                                                *   and allow communication with management port only. It is
+                                                *   then up to the application of the management port to implement
+                                                *   some bridging functionality to other ports as required.                   */
+            __IOM uint32_t TIMER_SEL     : 1;  /*!< [4..4] Select the timer to use for timed triggers                         */
+            uint32_t                     : 1;
+            __IOM uint32_t IPG_WAIT      : 3;  /*!< [8..6] IPG_WAIT                                                           */
+            __IOM uint32_t CRS_GEN       : 1;  /*!< [9..9] CRS_GEN                                                            */
+            __IOM uint32_t PRMB_GEN_DIS  : 1;  /*!< [10..10] PRMB_GEN_DIS                                                     */
+            __IOM uint32_t JAM_WAIT_IDLE : 1;  /*!< [11..11] JAM_WAIT_IDLE                                                    */
+            uint32_t                     : 20;
+        } HUB_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_GROUP;         /*!< (@ 0x00003E04) HUB Port Group Register                                    */
+
+        struct
+        {
+            __IOM uint32_t HUB_GROUP : 3; /*!< [2..0] Define all ports that should be combined to a Hub Group.           */
+            uint32_t                 : 29;
+        } HUB_GROUP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_DEFPORT;         /*!< (@ 0x00003E08) HUB Default Port Selection Register                        */
+
+        struct
+        {
+            __IOM uint32_t HUB_DEFPORT : 3; /*!< [2..0] The default port within the Hub Group where all traffic
+                                             *   from a port outside the group is forwarded to port (bit
+                                             *   0 = port 0, bit 1 = port 1, and bit 2 = port 2). If a frame
+                                             *   should be forwarded to any of the hub ports, the frame
+                                             *   is sent to this port only. The copy function of the hub
+                                             *   copies it to all PHY interfaces of the group eventually.                  */
+            uint32_t : 29;
+        } HUB_DEFPORT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_TRIGGER_IMMEDIATE;         /*!< (@ 0x00003E0C) HUB Transmission Trigger Immediate Register                */
+
+        struct
+        {
+            __IOM uint32_t HUB_TRIGGER_IMMEDIATE : 3; /*!< [2..0] Trigger immediate transmission of a single frame from
+                                                       *   given port within the hub group (bit 0 = port 0, bit 1
+                                                       *   = port 1, and bit 2 = port 2).                                            */
+            uint32_t : 29;
+        } HUB_TRIGGER_IMMEDIATE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_TRIGGER_AT;         /*!< (@ 0x00003E10) HUB Transmission Trigger At Register                       */
+
+        struct
+        {
+            __IOM uint32_t HUB_TRIGGER_AT : 3; /*!< [2..0] Trigger Transmission of a Single Frame at a Specific
+                                                *   Time (bit 0 = port 0, bit 1 = port 1, and bit 2 = port
+                                                *   2).                                                                       */
+            uint32_t : 29;
+        } HUB_TRIGGER_AT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_TTIME;          /*!< (@ 0x00003E14) HUB Transmission Time Define Register                      */
+
+        struct
+        {
+            __IOM uint32_t HUB_TTIME : 32; /*!< [31..0] Define the Time Value when a Trigger Should Occur                 */
+        } HUB_TTIME_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_IRQ_CONTROL;           /*!< (@ 0x00003E18) HUB Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t RX_TRIGGER : 3;        /*!< [2..0] Enable Interrupt on Receive Pattern Match Trigger Function         */
+            __IOM uint32_t CHANGE_DET : 1;        /*!< [3..3] Enable interrupt for hub TX state machine port state
+                                                   *   change request detection                                                  */
+            __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] Enable interrupt when hub transmit started after writing
+                                                   *   the HUB_TRIGGER_IMMEDIATE register                                        */
+            __IOM uint32_t TRIGGER_TIMER : 1;     /*!< [5..5] Enable interrupt when hub transmit started after writing
+                                                   *   the HUB_TRIGGER_TIME register and the timeout value is
+                                                   *   reached (register HUB_TTIME).                                             */
+            uint32_t : 26;
+        } HUB_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_IRQ_STAT_ACK;          /*!< (@ 0x00003E1C) HUB Interrupt Status/ACK Register                          */
+
+        struct
+        {
+            __IOM uint32_t RX_TRIGGER        : 3; /*!< [2..0] Interrupt Pending Indication                                       */
+            __IOM uint32_t CHANGE_DET        : 1; /*!< [3..3] This bit functions the same as RX_TRIGGER bit.                     */
+            __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] This bit functions the same as RX_TRIGGER bit.                     */
+            __IOM uint32_t TRIGGER_TIMER     : 1; /*!< [5..5] This bit functions the same as RX_TRIGGER bit.                     */
+            uint32_t                         : 26;
+        } HUB_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IM uint32_t HUB_STATUS;                /*!< (@ 0x00003E20) HUB Status Register                                        */
+
+        struct
+        {
+            __IM uint32_t PORTS_ACTIVE : 3;      /*!< [2..0] When this bit is 1, it shows the currently active ports
+                                                  *   of the Hub group which are allowed for transmit.                          */
+            uint32_t                : 6;
+            __IM uint32_t TX_ACTIVE : 1;         /*!< [9..9] When this bit is 1, the hub global transmit state machine
+                                                  *   has successfully entered Hub mode and is now controlling
+                                                  *   the hub group.                                                            */
+            __IM uint32_t TX_BUSY : 1;           /*!< [10..10] When this bit is 1, the local device currently transmits
+                                                  *   data to all ports within the hub group.                                   */
+            __IM uint32_t Speed_OK : 1;          /*!< [11..11] When this bit is 1, it indicates that the port speed
+                                                  *   of all group ports match.                                                 */
+            __IM uint32_t TX_Change_Pending : 1; /*!< [12..12] Indicate a pending change request in the hub transmitter
+                                                  *   that is unsolved and cause the hub to stop operation (no
+                                                  *   longer performing any transmissions).                                     */
+            uint32_t : 19;
+        } HUB_STATUS_b;
+    };
+
+    union
+    {
+        __IM uint32_t HUB_OPORT_STATUS;         /*!< (@ 0x00003E24) HUB Output Port Status Register                            */
+
+        struct
+        {
+            __IM uint32_t HUB_OPORT_STATUS : 3; /*!< [2..0] Per Output Port Data Available Status                              */
+            uint32_t                       : 29;
+        } HUB_OPORT_STATUS_b;
+    };
+    __IM uint32_t RESERVED109[22];
+
+    union
+    {
+        __IOM uint32_t TDMA_CONFIG;             /*!< (@ 0x00003E80) TDMA Configuration Register                                */
+
+        struct
+        {
+            __IOM uint32_t TDMA_ENA   : 1;      /*!< [0..0] Enable TDMA Scheduler                                              */
+            __IM uint32_t  WAIT_START : 1;      /*!< [1..1] Status bit which is set as long as the scheduler is enabled
+                                                 *   but has not yet reached the time given in register TDMA_START.            */
+            __IOM uint32_t TIMER_SEL : 1;       /*!< [2..2] Select which timer to use as the time source for the
+                                                 *   scheduler                                                                 */
+            uint32_t                    : 1;
+            __IM uint32_t  RED_PERIOD   : 1;    /*!< [4..4] Read only bit indicating the current period for Profinet           */
+            __IOM uint32_t RED_OVRD_ENA : 1;    /*!< [5..5] Enables overriding the RED period status, regardless
+                                                 *   of the indication by the TCV.                                             */
+            __IOM uint32_t RED_OVRD     : 1;    /*!< [6..6] Override Value for the RED Period                                  */
+            __OM uint32_t  IN_CT_WREN   : 1;    /*!< [7..7] IN_CT_WREN                                                         */
+            __OM uint32_t  OUT_CT_WREN  : 1;    /*!< [8..8] Enable writing the OUT_CT_ENA control to the egress ports.         */
+            __OM uint32_t  HOLD_REQ_CLR : 1;    /*!< [9..9] Writing 1 to this register clears the state of TDMA hold
+                                                 *   request.                                                                  */
+            uint32_t                       : 2;
+            __IM uint32_t TIMER_SEL_ACTIVE : 1; /*!< [12..12] Return the current timer being used for the TDMA Scheduler       */
+            uint32_t                       : 3;
+            __IOM uint32_t IN_CT_ENA       : 4; /*!< [19..16] On read, return the current status of the ingress Cut-Through
+                                                 *   enable indicated by the TDMA scheduler. On write, override
+                                                 *   the ingress Cut-Through enable if IN_CT_WREN is also 1.                   */
+            uint32_t                  : 4;
+            __IOM uint32_t OUT_CT_ENA : 4;      /*!< [27..24] On read, return the current status of the egress Cut-Through
+                                                 *   enable indicated by the TDMA scheduler. On write, override
+                                                 *   the egress Cut-Through enable if OUT_CT_WREN is also 1.                   */
+            uint32_t : 4;
+        } TDMA_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_ENA_CTRL;     /*!< (@ 0x00003E84) TDMA Scheduling Enable Control Register                    */
+
+        struct
+        {
+            __IOM uint32_t PORT_ENA : 4;  /*!< [3..0] Set to 1 to indicate that a port is operating in TDMA
+                                           *   mode. When set to 1 for a port, the port does not prefetch
+                                           *   another frame until the current frame in progress is done
+                                           *   and if TDMA_PREBUF_DIS in COMMAND_CONFIG is set to 1. This
+                                           *   helps adding precision to the queue gating operations indicated
+                                           *   by the TDMA at the expense of loss of line rate.                          */
+            uint32_t                 : 12;
+            __IOM uint32_t QGATE_DIS : 8; /*!< [23..16] One bit per output queue. When a bit is set to 1, the
+                                           *   TDMA scheduler gating commands do not affect the queue
+                                           *   even if the queue mask in the TCV control data is set to
+                                           *   1.                                                                        */
+            __IOM uint32_t QTRIG_DIS : 8; /*!< [31..24] One bit per output queue. When a bit is set to 1, the
+                                           *   TDMA scheduler triggering commands do not affect the queue
+                                           *   even if the queue mask in the TCV control data is set to
+                                           *   1.                                                                        */
+        } TDMA_ENA_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_START;          /*!< (@ 0x00003E88) TDMA Start Time Set Register                               */
+
+        struct
+        {
+            __IOM uint32_t TDMA_START : 32; /*!< [31..0] Set the start time for the very first cycle after system
+                                             *   initialization has completed. The value is compared with
+                                             *   the system time (selected in TDMA_CONFIG.TIMER_SEL) and
+                                             *   when it is reached (crossed), the scheduler begins with
+                                             *   its first cycle. The 2nd cycle is then at TDMA_START +
+                                             *   TDMA_CYCLE.                                                               */
+        } TDMA_START_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_MODULO;          /*!< (@ 0x00003E8C) TDMA System Timer Modulo                                   */
+
+        struct
+        {
+            __IOM uint32_t TDMA_MODULO : 32; /*!< [31..0] The System Timer Modulo                                           */
+        } TDMA_MODULO_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_CYCLE;          /*!< (@ 0x00003E90) TDMA Periodic Cycle Set Register                           */
+
+        struct
+        {
+            __IOM uint32_t TDMA_CYCLE : 32; /*!< [31..0] The periodic cycle time for the scheduler given in system
+                                             *   timer time.                                                               */
+        } TDMA_CYCLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_SEQ_ADDR;        /*!< (@ 0x00003E94) TCV Sequence Address Register                              */
+
+        struct
+        {
+            __IOM uint32_t TCV_S_ADDR : 12; /*!< [11..0] Address to write to or read from in the TCV sequence
+                                             *   table.                                                                    */
+            uint32_t                 : 19;
+            __IOM uint32_t ADDR_AINC : 1;   /*!< [31..31] When set to 1, read and write operations performed
+                                             *   using TCV_SEQ_CTRL causes the address in TCV_S_ADDR to
+                                             *   auto-increment after the operation.                                       */
+        } TCV_SEQ_ADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_SEQ_CTRL;      /*!< (@ 0x00003E98) TCV Sequence Table Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t START : 1;     /*!< [0..0] Indicate this TCV must be executed after the next cycle
+                                           *   start                                                                     */
+            __IOM uint32_t INT : 1;       /*!< [1..1] Indicates this TCV generates an interrupt to the CPU
+                                           *   when activated                                                            */
+            __IOM uint32_t TCV_D_IDX : 9; /*!< [10..2] Index to the TCV Data Entry                                       */
+            uint32_t                 : 11;
+            __IOM uint32_t GPIO      : 8; /*!< [29..22] Generic bits that control the output pins ETHSW_TDMAOUTn
+                                           *   (n = 0 to 7)                                                              */
+            uint32_t                 : 1;
+            __IOM uint32_t READ_MODE : 1; /*!< [31..31] When set to 1, a read operation is performed instead
+                                           *   of writing to the TCV sequence table. The read data (START,
+                                           *   INT, TCV_D_IDX[8:0], and GPIO) can be obtained by reading
+                                           *   this register afterwards. On read, this field always returns
+                                           *   0.                                                                        */
+        } TCV_SEQ_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_SEQ_LAST;   /*!< (@ 0x00003E9C) TCV Sequence Last Entry                                    */
+
+        struct
+        {
+            __IOM uint32_t LAST : 12;  /*!< [11..0] Defines the last entry to read from the TCV sequence
+                                        *   table when the TDMA scheduler is operating.                               */
+            uint32_t             : 4;
+            __IM uint32_t ACTIVE : 12; /*!< [27..16] Return the active TCV sequence entry.                            */
+            uint32_t             : 4;
+        } TCV_SEQ_LAST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_D_ADDR;          /*!< (@ 0x00003EA0) TCV Data Address Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDR        : 9; /*!< [8..0] Address to read from/write to in the TCV data table                */
+            uint32_t                   : 22;
+            __IOM uint32_t AINC_WR_ENA : 1; /*!< [31..31] Auto-Increment Enable                                            */
+        } TCV_D_ADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_D_OFFSET;          /*!< (@ 0x00003EA4) TCV Data Offset Register                                   */
+
+        struct
+        {
+            __IOM uint32_t TCV_D_OFFSET : 32; /*!< [31..0] 32-bit time offset for the TCV data entry indicated
+                                               *   by TCV_D_ADDR. When accessing the table, TCV_D_OFFSET must
+                                               *   be read or written before TCV_D_CTRL.                                     */
+        } TCV_D_OFFSET_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_D_CTRL;           /*!< (@ 0x00003EA8) TCV Data Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t INC_CTR0     : 1; /*!< [0..0] Increment Control for Counter 0                                    */
+            __IOM uint32_t INC_CTR1     : 1; /*!< [1..1] Increment Control for Counter 1                                    */
+            __IOM uint32_t RED_PERIOD   : 1; /*!< [2..2] Period Color Control (for Profinet IRT)                            */
+            __IOM uint32_t OUT_CT_ENA   : 1; /*!< [3..3] Output Cut-Through Enable                                          */
+            __IOM uint32_t IN_CT_ENA    : 1; /*!< [4..4] Input Cut-Through Enable                                           */
+            __IOM uint32_t TRIGGER_MODE : 1; /*!< [5..5] Trigger mode enable when set to 1. GATE_MODE must be
+                                              *   0, otherwise, GATE_MODE has precedence.                                   */
+            __IOM uint32_t GATE_MODE : 1;    /*!< [6..6] Gate mode enable when set to 1.                                    */
+            __IOM uint32_t HOLD_REQ  : 1;    /*!< [7..7] Preemption hold request. Generates a hold request to
+                                              *   ports enabled in PMASK.                                                   */
+            __IOM uint32_t QGATE : 8;        /*!< [15..8] Bits mask, one per output queue                                   */
+            __IOM uint32_t PMASK : 4;        /*!< [19..16] Bits mask, one per output port                                   */
+            uint32_t             : 12;
+        } TCV_D_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_CTR0;          /*!< (@ 0x00003EAC) TDMA Counter 0                                             */
+
+        struct
+        {
+            __IOM uint32_t TDMA_CTR0 : 32; /*!< [31..0] 32-bit counter that is incremented when the TCV field
+                                            *   INC_CTR0 is set to 1.                                                     */
+        } TDMA_CTR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_CTR1;         /*!< (@ 0x00003EB0) TDMA Counter 1                                             */
+
+        struct
+        {
+            __IOM uint32_t VALUE     : 8; /*!< [7..0] Current Counter Value                                              */
+            __OM uint32_t  WRITE_ENA : 1; /*!< [8..8] Write Enable for VALUE                                             */
+            uint32_t                 : 7;
+            __IOM uint32_t MAX       : 8; /*!< [23..16] Counter Maximum Value                                            */
+            __IOM uint32_t INT_VALUE : 8; /*!< [31..24] Interrupt Value                                                  */
+        } TDMA_CTR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_TCV_START;          /*!< (@ 0x00003EB4) TDMA TCV Sequence Entry Start                              */
+
+        struct
+        {
+            __IOM uint32_t TDMA_TCV_START : 12; /*!< [11..0] Define the TCV_SEQ entry to start from.                           */
+            uint32_t                      : 20;
+        } TDMA_TCV_START_b;
+    };
+
+    union
+    {
+        __IM uint32_t TIME_LOAD_NEXT;          /*!< (@ 0x00003EB8) TDMA Calculated Next Loading Time                          */
+
+        struct
+        {
+            __IM uint32_t TIME_LOAD_NEXT : 32; /*!< [31..0] Status giving the calculated time the scheduler loads
+                                                *   into its internal compare register after the current running
+                                                *   slot end is reached (not the end of the current slot).                    */
+        } TIME_LOAD_NEXT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_IRQ_CONTROL;    /*!< (@ 0x00003EBC) TDMA IRQ Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t TCV_INT_EN  : 1; /*!< [0..0] Enable Interrupts Generated by the TCV                             */
+            uint32_t                   : 12;
+            __IOM uint32_t CTR1_INT_EN : 1; /*!< [13..13] Enable Interrupts Generated from Counter 1                       */
+            uint32_t                   : 18;
+        } TDMA_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_IRQ_STAT_ACK; /*!< (@ 0x00003EC0) TDMA IRQ Status/ACK Register                               */
+
+        struct
+        {
+            __IOM uint32_t TCV_ACK  : 1;  /*!< [0..0] TCV Execution Event                                                */
+            uint32_t                : 12;
+            __IOM uint32_t CTR1_ACK : 1;  /*!< [13..13] Counter 1 Event                                                  */
+            uint32_t                : 18;
+        } TDMA_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_GPIO;           /*!< (@ 0x00003EC4) TDMA GPIO Register                                         */
+
+        struct
+        {
+            __IM uint32_t GPIO_STATUS : 8;  /*!< [7..0] Status of the GPIO Output Pins                                     */
+            uint32_t                  : 8;
+            __IOM uint32_t GPIO_MODE  : 16; /*!< [31..16] 2 bits per GPIO pin to configure its operating mode              */
+        } TDMA_GPIO_b;
+    };
+    __IM uint32_t RESERVED110[14];
+
+    union
+    {
+        __IOM uint32_t RXMATCH_CONFIG[4];   /*!< (@ 0x00003F00) RX Pattern Matcher Configuration for Port [0..3]           */
+
+        struct
+        {
+            __IOM uint32_t PATTERN_EN : 12; /*!< [11..0] Enable Patterns on the Port (RX)                                  */
+            uint32_t                  : 20;
+        } RXMATCH_CONFIG_b[4];
+    };
+    __IM uint32_t RESERVED111[12];
+
+    union
+    {
+        __IOM uint32_t PATTERN_CTRL[12];        /*!< (@ 0x00003F40) RX Pattern Matcher Function Control for Pattern
+                                                 *                  [0..11]                                                    */
+
+        struct
+        {
+            __IOM uint32_t MATCH_NOT : 1;       /*!< [0..0] When set, a match is reported and the functions of this
+                                                 *   control are executed if the pattern does not match.                       */
+            __IOM uint32_t MGMTFWD : 1;         /*!< [1..1] When set, the frame is forwarded to the management port
+                                                 *   only (suppressing destination address lookup).                            */
+            __IOM uint32_t DISCARD       : 1;   /*!< [2..2] When set, the frame is discarded.                                  */
+            __IOM uint32_t SET_PRIO      : 1;   /*!< [3..3] Set frame priority, overriding normal classification.              */
+            __IOM uint32_t MODE          : 2;   /*!< [5..4] Selects the operating mode                                         */
+            __IOM uint32_t TIMER_SEL_OVR : 1;   /*!< [6..6] Overrides the default timer to use by timestamp operations
+                                                 *   when set to 1, using instead the value in TIMER_SEL.                      */
+            __IOM uint32_t FORCE_FORWARD : 1;   /*!< [7..7] When set, the frame is forwarded to the ports indicated
+                                                 *   in PORTMASK, ignoring the result from L2 lookups.                         */
+            __IOM uint32_t HUBTRIGGER : 1;      /*!< [8..8] When set, the port defined in the PORTMASK setting is
+                                                 *   allowed for transmitting one frame.                                       */
+            __IOM uint32_t MATCH_RED : 1;       /*!< [9..9] Enable the pattern matcher only when the TDMA indicates
+                                                 *   that this is the RED period.                                              */
+            __IOM uint32_t MATCH_NOT_RED : 1;   /*!< [10..10] Enable the pattern matcher only when the TDMA indicates
+                                                 *   that this is not the RED period.                                          */
+            __IOM uint32_t VLAN_SKIP : 1;       /*!< [11..11] When set to 1, for operating modes 1, 2, and 3. The
+                                                 *   first Length/Type after the MAC source address is compared
+                                                 *   against 0x8100. If it matches, a VLAN tag is assumed and
+                                                 *   4 bytes are skipped.                                                      */
+            __IOM uint32_t PRIORITY : 3;        /*!< [14..12] Priority of the frame used when SET_PRIO is set. The
+                                                 *   priority is used to forward the frame into the corresponding
+                                                 *   output queue of a port.                                                   */
+            __IOM uint32_t LEARNING_DIS : 1;    /*!< [15..15] When set to 1, the hardware learning function is not
+                                                 *   executed.                                                                 */
+            __IOM uint32_t PORTMASK : 4;        /*!< [19..16] A port mask used depending on the control bits (for
+                                                 *   example, HUBTRIGGER).                                                     */
+            uint32_t                   : 2;
+            __IOM uint32_t IMC_TRIGGER : 1;     /*!< [22..22] When set, the ports defined in the PORTMASK setting
+                                                 *   are allowed for transmitting one frame from the queues
+                                                 *   indicated by QUEUESEL. The trigger request is sent to the
+                                                 *   integrated memory controller.                                             */
+            __IOM uint32_t IMC_TRIGGER_DLY : 1; /*!< [23..23] When set, the ports defined in the PORTMASK setting
+                                                 *   are allowed for transmitting one frame from the queues
+                                                 *   indicated by QUEUESEL. The trigger request is sent to the
+                                                 *   integrated memory controller and the event is delayed by
+                                                 *   the value programmed in MMCTL_DLY_QTRIGGER_CTRL.                          */
+            __IOM uint32_t SWAP_BYTES : 1;      /*!< [24..24] Applicable only for operating modes 1, 2, and 3. When
+                                                 *   set to 1, the byte order is swapped from the order received
+                                                 *   by the frame. When set to 0, the first byte received by
+                                                 *   the frame is set into position 0 for comparison. When set
+                                                 *   to 1, the first byte received is set into position 3 (for
+                                                 *   mode 1) or position 2 (for mode 2 and 3) for comparison.                  */
+            __IOM uint32_t MATCH_LT : 1;        /*!< [25..25] For operating modes 1, 2, and 3. When set to 1, the
+                                                 *   Length/Type field in the frame after the MAC source address
+                                                 *   is compared against the value in length_type in the compare
+                                                 *   register. If VLAN_SKIP is set and the frame has a VLAN
+                                                 *   tag with Length/Type of 0x8100 then the comparison is performed
+                                                 *   in the Length/Type following the VLAN tag.                                */
+            __IOM uint32_t TIMER_SEL : 1;       /*!< [26..26] Override value to use when TIMER_SEL_OVR is set to
+                                                 *   1 for selecting the timer for this frame.                                 */
+            uint32_t                : 1;
+            __IOM uint32_t QUEUESEL : 4;        /*!< [31..28] A queue selector for the HUBTRIGGER function. Selects
+                                                 *   the queue to trigger a frame, or sets from 0x8 to 0xF to
+                                                 *   select one among all queues.                                              */
+        } PATTERN_CTRL_b[12];
+    };
+    __IM uint32_t RESERVED112[4];
+
+    union
+    {
+        __IOM uint32_t PATTERN_IRQ_CONTROL; /*!< (@ 0x00003F80) RX Pattern Matcher Interrupt Control Register              */
+
+        struct
+        {
+            __IOM uint32_t MATCHINT  : 12;  /*!< [11..0] Enable Interrupt on Receive Pattern Match                         */
+            uint32_t                 : 4;
+            __IOM uint32_t ERROR_INT : 4;   /*!< [19..16] Enable Interrupt on Internal Pattern Matcher Error               */
+            uint32_t                 : 12;
+        } PATTERN_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PATTERN_IRQ_STAT_ACK; /*!< (@ 0x00003F84) RX Pattern Matcher Interrupt Status/ACK Register           */
+
+        struct
+        {
+            __IOM uint32_t MATCHINT : 12;    /*!< [11..0] Interrupt pending indication for the corresponding pattern
+                                              *   match events (see ).                                                      */
+            uint32_t                 : 4;
+            __IOM uint32_t ERROR_INT : 4;    /*!< [19..16] Interrupt pending indication for a pattern matcher
+                                              *   error, per port.                                                          */
+            uint32_t : 12;
+        } PATTERN_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_VLANID;          /*!< (@ 0x00003F88) Custom VLAN ID Register                                    */
+
+        struct
+        {
+            __IOM uint32_t PTRN_VLANID : 16; /*!< [15..0] Custom VLAN ID to use. The default VLAN ID 0x8100 is
+                                              *   always considered by the hardware. This value can be changed
+                                              *   to detect other VLANs like 0x8808.                                        */
+            uint32_t : 16;
+        } PTRN_VLANID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PATTERN_SEL;         /*!< (@ 0x00003F8C) RX Pattern Number Selection Register                       */
+
+        struct
+        {
+            __IOM uint32_t PATTERN_SEL : 4; /*!< [3..0] Define the pattern number which is selected for read/write
+                                             *   through the PTRN_CMP_* and PTRN_MSK_* registers.                          */
+            uint32_t : 28;
+        } PATTERN_SEL_b;
+    };
+    __IM uint32_t RESERVED113[12];
+
+    union
+    {
+        __IOM uint32_t PTRN_CMP_30;          /*!< (@ 0x00003FC0) Pattern Compare Value Bytes 3 .. 0                         */
+
+        struct
+        {
+            __IOM uint32_t PTRN_CMP_30 : 32; /*!< [31..0] Pattern Compare Value Bytes 3 .. 0                                */
+        } PTRN_CMP_30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_CMP_74;          /*!< (@ 0x00003FC4) Pattern Compare Value Bytes 7 .. 4                         */
+
+        struct
+        {
+            __IOM uint32_t PTRN_CMP_74 : 32; /*!< [31..0] Pattern Compare Value Bytes 7 .. 4                                */
+        } PTRN_CMP_74_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_CMP_118;          /*!< (@ 0x00003FC8) Pattern Compare Value Bytes 11 .. 8                        */
+
+        struct
+        {
+            __IOM uint32_t PTRN_CMP_118 : 32; /*!< [31..0] Pattern Compare Value Bytes 11 .. 8                               */
+        } PTRN_CMP_118_b;
+    };
+    __IM uint32_t RESERVED114;
+
+    union
+    {
+        __IOM uint32_t PTRN_MSK_30;          /*!< (@ 0x00003FD0) Pattern Mask for Bytes 3 .. 0                              */
+
+        struct
+        {
+            __IOM uint32_t PTRN_MSK_30 : 32; /*!< [31..0] PTRN_MSK_30                                                       */
+        } PTRN_MSK_30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_MSK_74;          /*!< (@ 0x00003FD4) Pattern Mask for Bytes 7 .. 4                              */
+
+        struct
+        {
+            __IOM uint32_t PTRN_MSK_74 : 32; /*!< [31..0] PTRN_MSK_74                                                       */
+        } PTRN_MSK_74_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_MSK_118;          /*!< (@ 0x00003FD8) Pattern Mask for Bytes 11 .. 8                             */
+
+        struct
+        {
+            __IOM uint32_t PTRN_MSK_118 : 32; /*!< [31..0] PTRN_MSK_118                                                      */
+        } PTRN_MSK_118_b;
+    };
+} R_ETHSW_Type;                               /*!< Size = 16348 (0x3fdc)                                                     */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ESC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief EtherCAT Slave Controller (R_ESC)
+ */
+
+typedef struct                         /*!< (@ 0x80130000) R_ESC Structure                                            */
+{
+    union
+    {
+        __IM uint8_t TYPE;             /*!< (@ 0x00000000) Type Register                                              */
+
+        struct
+        {
+            __IM uint8_t TYPE : 8;     /*!< [7..0] Type of the EtherCAT slave controller                              */
+        } TYPE_b;
+    };
+
+    union
+    {
+        __IM uint8_t REVISION;         /*!< (@ 0x00000001) Revision Register                                          */
+
+        struct
+        {
+            __IM uint8_t REV : 8;      /*!< [7..0] Revision of the EtherCAT slave controller                          */
+        } REVISION_b;
+    };
+
+    union
+    {
+        __IM uint8_t BUILD;            /*!< (@ 0x00000002) Build Register                                             */
+
+        struct
+        {
+            __IM uint8_t BUILD : 8;    /*!< [7..0] Build number of the EtherCAT slave controller                      */
+        } BUILD_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IM uint8_t FMMU_NUM;         /*!< (@ 0x00000004) FMMU Supported Register                                    */
+
+        struct
+        {
+            __IM uint8_t NUMFMMU : 8;  /*!< [7..0] Number of FMMU channels supported in the EtherCAT slave
+                                        *   controller                                                                */
+        } FMMU_NUM_b;
+    };
+
+    union
+    {
+        __IM uint8_t SYNC_MANAGER;     /*!< (@ 0x00000005) SyncManager Supported Register                             */
+
+        struct
+        {
+            __IM uint8_t NUMSYNC : 8;  /*!< [7..0] Number of SyncManager channels supported in the EtherCAT
+                                        *   slave controller                                                          */
+        } SYNC_MANAGER_b;
+    };
+
+    union
+    {
+        __IM uint8_t RAM_SIZE;         /*!< (@ 0x00000006) RAM Size Register                                          */
+
+        struct
+        {
+            __IM uint8_t RAMSIZE : 8;  /*!< [7..0] Process data RAM size supported in the EtherCAT slave
+                                        *   controller (unit: KB)                                                     */
+        } RAM_SIZE_b;
+    };
+
+    union
+    {
+        __IM uint8_t PORT_DESC;        /*!< (@ 0x00000007) Port Descriptor Register                                   */
+
+        struct
+        {
+            __IM uint8_t P0 : 2;       /*!< [1..0] Port 0 configuration                                               */
+            __IM uint8_t P1 : 2;       /*!< [3..2] Port 1 configuration                                               */
+            __IM uint8_t P2 : 2;       /*!< [5..4] Port 2 configuration                                               */
+            __IM uint8_t P3 : 2;       /*!< [7..6] Port 3 configuration                                               */
+        } PORT_DESC_b;
+    };
+
+    union
+    {
+        __IM uint16_t FEATURE;            /*!< (@ 0x00000008) ESC Features Supported Register                            */
+
+        struct
+        {
+            __IM uint16_t FMMU       : 1; /*!< [0..0] FMMU Operation                                                     */
+            uint16_t                 : 1;
+            __IM uint16_t DC         : 1; /*!< [2..2] Distributed Clock                                                  */
+            __IM uint16_t DCWID      : 1; /*!< [3..3] Distributed Clock Width                                            */
+            uint16_t                 : 2;
+            __IM uint16_t LINKDECMII : 1; /*!< [6..6] Enhanced Link Detection in MII                                     */
+            __IM uint16_t FCS        : 1; /*!< [7..7] Separate handling of FCS errors                                    */
+            __IM uint16_t DCSYNC     : 1; /*!< [8..8] Enhanced DC SYNC activation                                        */
+            __IM uint16_t LRW        : 1; /*!< [9..9] EtherCAT LRW command support                                       */
+            __IM uint16_t RWSUPP     : 1; /*!< [10..10] EtherCAT read/write command support (BRW, APRW, FPRW)            */
+            __IM uint16_t FSCONFIG   : 1; /*!< [11..11] Fixed FMMU/SyncManager configuration                             */
+            uint16_t                 : 4;
+        } FEATURE_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IM uint16_t STATION_ADR;      /*!< (@ 0x00000010) Configured Station Address Register                        */
+
+        struct
+        {
+            __IM uint16_t NODADDR : 16; /*!< [15..0] Node Addressing Address Indication                                */
+        } STATION_ADR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATION_ALIAS;       /*!< (@ 0x00000012) Configured Station Alias Register                          */
+
+        struct
+        {
+            __IOM uint16_t NODALIADDR : 16; /*!< [15..0] Alias Address Indication                                          */
+        } STATION_ALIAS_b;
+    };
+    __IM uint32_t RESERVED3[3];
+
+    union
+    {
+        __IM uint8_t WR_REG_ENABLE;    /*!< (@ 0x00000020) Write Register Enable Register                             */
+
+        struct
+        {
+            __IM uint8_t ENABLE : 1;   /*!< [0..0] Register Write Protection Unlock                                   */
+            uint8_t             : 7;
+        } WR_REG_ENABLE_b;
+    };
+
+    union
+    {
+        __IM uint8_t WR_REG_PROTECT;   /*!< (@ 0x00000021) Write Register Protection Register                         */
+
+        struct
+        {
+            __IM uint8_t PROTECT : 1;  /*!< [0..0] Register Write Protection Specification                            */
+            uint8_t              : 7;
+        } WR_REG_PROTECT_b;
+    };
+    __IM uint16_t RESERVED4;
+    __IM uint32_t RESERVED5[3];
+
+    union
+    {
+        __IM uint8_t ESC_WR_ENABLE;    /*!< (@ 0x00000030) ESC Write Enable Register                                  */
+
+        struct
+        {
+            __IM uint8_t ENABLE : 1;   /*!< [0..0] Register/Memory Write Protection Unlock                            */
+            uint8_t             : 7;
+        } ESC_WR_ENABLE_b;
+    };
+
+    union
+    {
+        __IM uint8_t ESC_WR_PROTECT;   /*!< (@ 0x00000031) ESC Write Protection Register                              */
+
+        struct
+        {
+            __IM uint8_t PROTECT : 1;  /*!< [0..0] Register/Memory Write Protection Specification                     */
+            uint8_t              : 7;
+        } ESC_WR_PROTECT_b;
+    };
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        union
+        {
+            __IM uint8_t ESC_RESET_ECAT_R;   /*!< (@ 0x00000040) ESC Reset ECAT Register for read                           */
+
+            struct
+            {
+                __IM uint8_t RESET_ECAT : 2; /*!< [1..0] Reset Progress Status                                              */
+                uint8_t                 : 6;
+            } ESC_RESET_ECAT_R_b;
+        };
+
+        union
+        {
+            __IM uint8_t ESC_RESET_ECAT_W;   /*!< (@ 0x00000040) ESC Reset ECAT Register for write                          */
+
+            struct
+            {
+                __IM uint8_t RESET_ECAT : 8; /*!< [7..0] Software Reset Setting                                             */
+            } ESC_RESET_ECAT_W_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t ESC_RESET_PDI_R;   /*!< (@ 0x00000041) ESC Reset PDI Register for read                            */
+
+            struct
+            {
+                __IOM uint8_t RESET_PDI : 2; /*!< [1..0] Reset Progress Status                                              */
+                uint8_t                 : 6;
+            } ESC_RESET_PDI_R_b;
+        };
+
+        union
+        {
+            __IOM uint8_t ESC_RESET_PDI_W;   /*!< (@ 0x00000041) ESC Reset PDI Register for write                           */
+
+            struct
+            {
+                __IOM uint8_t RESET_PDI : 8; /*!< [7..0] Software Reset Setting                                             */
+            } ESC_RESET_PDI_W_b;
+        };
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9[47];
+
+    union
+    {
+        __IM uint32_t ESC_DL_CONTROL;   /*!< (@ 0x00000100) ESC DL Control Register                                    */
+
+        struct
+        {
+            __IM uint32_t FWDRULE  : 1; /*!< [0..0] Forwarding Rule                                                    */
+            __IM uint32_t TEMPUSE  : 1; /*!< [1..1] Temporary Use of Bits 15 to 8 Settings                             */
+            uint32_t               : 6;
+            __IM uint32_t LP0      : 2; /*!< [9..8] Loop Port 0 Configuration                                          */
+            __IM uint32_t LP1      : 2; /*!< [11..10] Loop Port 1 Configuration                                        */
+            __IM uint32_t LP2      : 2; /*!< [13..12] Loop Port 2 Configuration                                        */
+            __IM uint32_t LP3      : 2; /*!< [15..14] Loop Port 3 Configuration                                        */
+            __IM uint32_t RXFIFO   : 3; /*!< [18..16] RX FIFO Size                                                     */
+            uint32_t               : 5;
+            __IM uint32_t STAALIAS : 1; /*!< [24..24] Station Alias Status                                             */
+            uint32_t               : 7;
+        } ESC_DL_CONTROL_b;
+    };
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IM uint16_t PHYSICAL_RW_OFFSET; /*!< (@ 0x00000108) Physical Read/Write Offset Register                        */
+
+        struct
+        {
+            __IM uint16_t RWOFFSET : 16;  /*!< [15..0] Offset between Read and Write Addresses                           */
+        } PHYSICAL_RW_OFFSET_b;
+    };
+    __IM uint16_t RESERVED11;
+    __IM uint32_t RESERVED12;
+
+    union
+    {
+        __IM uint16_t ESC_DL_STATUS;    /*!< (@ 0x00000110) ESC DL Status Register                                     */
+
+        struct
+        {
+            __IM uint16_t PDIOPE   : 1; /*!< [0..0] PDI/EEPROM Load State Indication                                   */
+            __IM uint16_t PDIWDST  : 1; /*!< [1..1] PDI Watchdog Timer Status                                          */
+            __IM uint16_t ENHLINKD : 1; /*!< [2..2] Enhanced Link Detection Indication                                 */
+            uint16_t               : 1;
+            __IM uint16_t PHYP0    : 1; /*!< [4..4] Port 0 Link State Indication                                       */
+            __IM uint16_t PHYP1    : 1; /*!< [5..5] Port 1 Link State Indication                                       */
+            __IM uint16_t PHYP2    : 1; /*!< [6..6] Port 2 Link State Indication                                       */
+            __IM uint16_t PHYP3    : 1; /*!< [7..7] Port 3 Link State Indication                                       */
+            __IM uint16_t LP0      : 1; /*!< [8..8] Loop Port 0 State Indication                                       */
+            __IM uint16_t COMP0    : 1; /*!< [9..9] Port 0 Communication State Indication                              */
+            __IM uint16_t LP1      : 1; /*!< [10..10] Loop Port 1 State Indication                                     */
+            __IM uint16_t COMP1    : 1; /*!< [11..11] Port 1 Communication State Indication                            */
+            __IM uint16_t LP2      : 1; /*!< [12..12] Loop Port 2 State Indication                                     */
+            __IM uint16_t COMP2    : 1; /*!< [13..13] Port 2 Communication State Indication                            */
+            __IM uint16_t LP3      : 1; /*!< [14..14] Loop Port 3 State Indication                                     */
+            __IM uint16_t COMP3    : 1; /*!< [15..15] Port 3 Communication State Indication                            */
+        } ESC_DL_STATUS_b;
+    };
+    __IM uint16_t RESERVED13;
+    __IM uint32_t RESERVED14[3];
+
+    union
+    {
+        __IM uint16_t AL_CONTROL;        /*!< (@ 0x00000120) AL Control Register                                        */
+
+        struct
+        {
+            __IM uint16_t INISTATE  : 4; /*!< [3..0] Change the state transition of the device state machine.           */
+            __IM uint16_t ERRINDACK : 1; /*!< [4..4] Error Indication Acknowledge (Response)                            */
+            __IM uint16_t DEVICEID  : 1; /*!< [5..5] Device ID Request                                                  */
+            uint16_t                : 10;
+        } AL_CONTROL_b;
+    };
+    __IM uint16_t RESERVED15;
+    __IM uint32_t RESERVED16[3];
+
+    union
+    {
+        __IOM uint16_t AL_STATUS;        /*!< (@ 0x00000130) AL Status Register                                         */
+
+        struct
+        {
+            __IOM uint16_t ACTSTATE : 4; /*!< [3..0] State Machine State Indication                                     */
+            __IOM uint16_t ERR      : 1; /*!< [4..4] Error State Indication                                             */
+            __IOM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Load State Indication                                    */
+            uint16_t                : 10;
+        } AL_STATUS_b;
+    };
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint16_t AL_STATUS_CODE;      /*!< (@ 0x00000134) AL Status Code Register                                    */
+
+        struct
+        {
+            __IOM uint16_t STATUSCODE : 16; /*!< [15..0] AL status code                                                    */
+        } AL_STATUS_CODE_b;
+    };
+    __IM uint16_t RESERVED18;
+
+    union
+    {
+        __IOM uint8_t RUN_LED_OVERRIDE;   /*!< (@ 0x00000138) RUN LED Override Register                                  */
+
+        struct
+        {
+            __IOM uint8_t LEDCODE : 4;    /*!< [3..0] LED Code Indication (FSM state: Bits [3:0] of the AL
+                                           *   Status register, AL_STATUS)                                               */
+            __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting                                                   */
+            uint8_t                  : 3;
+        } RUN_LED_OVERRIDE_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ERR_LED_OVERRIDE;   /*!< (@ 0x00000139) ERR LED Override Register                                  */
+
+        struct
+        {
+            __IOM uint8_t LEDCODE    : 4; /*!< [3..0] LED Code Indication                                                */
+            __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting                                                   */
+            uint8_t                  : 3;
+        } ERR_LED_OVERRIDE_b;
+    };
+    __IM uint16_t RESERVED19;
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        __IM uint8_t PDI_CONTROL;      /*!< (@ 0x00000140) PDI Control Register                                       */
+
+        struct
+        {
+            __IM uint8_t PDI : 8;      /*!< [7..0] Process Data Interface. In this LSI, the following value
+                                        *   is indicated.                                                             */
+        } PDI_CONTROL_b;
+    };
+
+    union
+    {
+        __IM uint8_t ESC_CONFIG;       /*!< (@ 0x00000141) ESC Configuration Register                                 */
+
+        struct
+        {
+            __IM uint8_t DEVEMU  : 1;  /*!< [0..0] Device emulation (control of AL status)                            */
+            __IM uint8_t ENLALLP : 1;  /*!< [1..1] Sets enhanced link detection for all ports                         */
+            __IM uint8_t DCSYNC  : 1;  /*!< [2..2] Sets the SYNC output unit for distributed clocks (fixed
+                                        *   to 1 in this LSI)                                                         */
+            __IM uint8_t DCLATCH : 1;  /*!< [3..3] Sets the latch input unit for distributed clocks                   */
+            __IM uint8_t ENLP0   : 1;  /*!< [4..4] Port 0 Enhanced Link Detection Setting                             */
+            __IM uint8_t ENLP1   : 1;  /*!< [5..5] Port 1 Enhanced Link Detection Setting                             */
+            __IM uint8_t ENLP2   : 1;  /*!< [6..6] Port 2 Enhanced Link Detection Setting                             */
+            __IM uint8_t ENLP3   : 1;  /*!< [7..7] Port 3 Enhanced Link Detection Setting                             */
+        } ESC_CONFIG_b;
+    };
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
+
+    union
+    {
+        __IM uint8_t PDI_CONFIG;           /*!< (@ 0x00000150) PDI Configuration Register                                 */
+
+        struct
+        {
+            __IM uint8_t ONCHIPBUSCLK : 5; /*!< [4..0] On-Chip Bus Clock Indication                                       */
+            __IM uint8_t ONCHIPBUS    : 3; /*!< [7..5] On-Chip Bus Type Indication                                        */
+        } PDI_CONFIG_b;
+    };
+
+    union
+    {
+        __IM uint8_t SYNC_LATCH_CONFIG; /*!< (@ 0x00000151) SYNC/LATCH PDI Configuration Register                      */
+
+        struct
+        {
+            __IM uint8_t SYNC0OUT : 2;  /*!< [1..0] SYNC0 Output Driver and Polarity Indication                        */
+            __IM uint8_t SYNCLAT0 : 1;  /*!< [2..2] SYNC0/LATCH0 Indication                                            */
+            __IM uint8_t SYNC0MAP : 1;  /*!< [3..3] SYNC0 State Mapping Indication                                     */
+            __IM uint8_t SYNC1OUT : 2;  /*!< [5..4] SYNC1 Output Driver and Polarity Indication                        */
+            __IM uint8_t SYNCLAT1 : 1;  /*!< [6..6] SYNC1/LATCH1 Indication                                            */
+            __IM uint8_t SYNC1MAP : 1;  /*!< [7..7] SYNC1 State Mapping Indication                                     */
+        } SYNC_LATCH_CONFIG_b;
+    };
+
+    union
+    {
+        __IM uint16_t EXT_PDI_CONFIG;     /*!< (@ 0x00000152) Extended PDI Configuration Register                        */
+
+        struct
+        {
+            __IM uint16_t DATABUSWID : 2; /*!< [1..0] PDI Data Bus Width Indication                                      */
+            uint16_t                 : 14;
+        } EXT_PDI_CONFIG_b;
+    };
+    __IM uint32_t RESERVED23[43];
+
+    union
+    {
+        __IM uint16_t ECAT_EVENT_MASK;     /*!< (@ 0x00000200) ECAT Event Mask Register                                   */
+
+        struct
+        {
+            __IM uint16_t ECATEVMASK : 16; /*!< [15..0] Event Request Mask Setting                                        */
+        } ECAT_EVENT_MASK_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint32_t AL_EVENT_MASK;     /*!< (@ 0x00000204) AL Event Mask Register                                     */
+
+        struct
+        {
+            __IOM uint32_t ALEVMASK : 32; /*!< [31..0] Event Request Mask Setting                                        */
+        } AL_EVENT_MASK_b;
+    };
+    __IM uint32_t RESERVED25[2];
+
+    union
+    {
+        __IM uint16_t ECAT_EVENT_REQ;  /*!< (@ 0x00000210) ECAT Event Request Register                                */
+
+        struct
+        {
+            __IM uint16_t DCLATCH : 1; /*!< [0..0] DC Latch Event State Indication                                    */
+            uint16_t              : 1;
+            __IM uint16_t DLSTA   : 1; /*!< [2..2] DL Status Event State Indication                                   */
+            __IM uint16_t ALSTA   : 1; /*!< [3..3] AL Status Event State Indication                                   */
+            __IM uint16_t SMSTA0  : 1; /*!< [4..4] Mirror value of SyncManager 0 Status Indication                    */
+            __IM uint16_t SMSTA1  : 1; /*!< [5..5] Mirror value of SyncManager 1 Status Indication                    */
+            __IM uint16_t SMSTA2  : 1; /*!< [6..6] Mirror value of SyncManager 2 Status Indication                    */
+            __IM uint16_t SMSTA3  : 1; /*!< [7..7] Mirror value of SyncManager 3 Status Indication                    */
+            __IM uint16_t SMSTA4  : 1; /*!< [8..8] Mirror value of SyncManager 4 Status Indication                    */
+            __IM uint16_t SMSTA5  : 1; /*!< [9..9] Mirror value of SyncManager 5 Status Indication                    */
+            __IM uint16_t SMSTA6  : 1; /*!< [10..10] Mirror value of SyncManager 6 Status Indication                  */
+            __IM uint16_t SMSTA7  : 1; /*!< [11..11] Mirror value of SyncManager 7 Status Indication                  */
+            uint16_t              : 4;
+        } ECAT_EVENT_REQ_b;
+    };
+    __IM uint16_t RESERVED26;
+    __IM uint32_t RESERVED27[3];
+
+    union
+    {
+        __IM uint32_t AL_EVENT_REQ;       /*!< (@ 0x00000220) AL Event Request Register                                  */
+
+        struct
+        {
+            __IM uint32_t ALCTRL     : 1; /*!< [0..0] AL Control Event State Indication                                  */
+            __IM uint32_t DCLATCH    : 1; /*!< [1..1] DC Latch Event State Indication                                    */
+            __IM uint32_t DCSYNC0STA : 1; /*!< [2..2] DC SYNC0 State Indication                                          */
+            __IM uint32_t DCSYNC1STA : 1; /*!< [3..3] DC SYNC1 State Indication                                          */
+            __IM uint32_t SYNCACT    : 1; /*!< [4..4] SyncManager Activation Indication                                  */
+            uint32_t                 : 1;
+            __IM uint32_t WDPD       : 1; /*!< [6..6] Watchdog Process Data Indication                                   */
+            uint32_t                 : 1;
+            __IM uint32_t SMINT0     : 1; /*!< [8..8] SyncManager 0 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x0805))                                                 */
+            __IM uint32_t SMINT1 : 1;     /*!< [9..9] SyncManager 1 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x080D))                                                 */
+            __IM uint32_t SMINT2 : 1;     /*!< [10..10] SyncManager 2 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x0815))                                                 */
+            __IM uint32_t SMINT3 : 1;     /*!< [11..11] SyncManager 3 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x081D))                                                 */
+            __IM uint32_t SMINT4 : 1;     /*!< [12..12] SyncManager 4 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x0825))                                                 */
+            __IM uint32_t SMINT5 : 1;     /*!< [13..13] SyncManager 5 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x082D))                                                 */
+            __IM uint32_t SMINT6 : 1;     /*!< [14..14] SyncManager 6 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x0835))                                                 */
+            __IM uint32_t SMINT7 : 1;     /*!< [15..15] SyncManager 7 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x083D))                                                 */
+            uint32_t : 16;
+        } AL_EVENT_REQ_b;
+    };
+    __IM uint32_t RESERVED28[55];
+
+    union
+    {
+        __IM uint16_t RX_ERR_COUNT[3];   /*!< (@ 0x00000300) RX Error Counter [0..2] Register (n = 0 to 2)              */
+
+        struct
+        {
+            __IM uint16_t INVFRMCNT : 8; /*!< [7..0] Invalid Frame Counter Value Indication                             */
+            __IM uint16_t RXERRCNT  : 8; /*!< [15..8] RX Frame Error Counter Value Indication                           */
+        } RX_ERR_COUNT_b[3];
+    };
+    __IM uint16_t RESERVED29;
+
+    union
+    {
+        __IM uint8_t FWD_RX_ERR_COUNT[3]; /*!< (@ 0x00000308) Forwarded RX Error Counter [0..2] Register (n
+                                           *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IM uint8_t FWDERRCNT : 8;   /*!< [7..0] Forwarded Error Counter Value Indication                           */
+        } FWD_RX_ERR_COUNT_b[3];
+    };
+    __IM uint8_t RESERVED30;
+
+    union
+    {
+        __IM uint8_t ECAT_PROC_ERR_COUNT; /*!< (@ 0x0000030C) ECAT Processing Unit Error Counter Register                */
+
+        struct
+        {
+            __IM uint8_t EPUERRCNT : 8;   /*!< [7..0] Processing Unit Error Counter Value Indication                     */
+        } ECAT_PROC_ERR_COUNT_b;
+    };
+
+    union
+    {
+        __IM uint8_t PDI_ERR_COUNT;     /*!< (@ 0x0000030D) PDI Error Counter Register                                 */
+
+        struct
+        {
+            __IM uint8_t PDIERRCNT : 8; /*!< [7..0] PDI Error Counter Value Indication                                 */
+        } PDI_ERR_COUNT_b;
+    };
+    __IM uint16_t RESERVED31;
+
+    union
+    {
+        __IM uint8_t LOST_LINK_COUNT[3];  /*!< (@ 0x00000310) Lost Link Counter [0..2] Register (n = 0 to 2)             */
+
+        struct
+        {
+            __IM uint8_t LOSTLINKCNT : 8; /*!< [7..0] Lost Link Counter Value Indication                                 */
+        } LOST_LINK_COUNT_b[3];
+    };
+    __IM uint8_t  RESERVED32;
+    __IM uint32_t RESERVED33[59];
+
+    union
+    {
+        __IM uint16_t WD_DIVIDE;       /*!< (@ 0x00000400) Watchdog Divider Register                                  */
+
+        struct
+        {
+            __IM uint16_t WDDIV : 16;  /*!< [15..0] Watchdog Clock Frequency Divisor Setting                          */
+        } WD_DIVIDE_b;
+    };
+    __IM uint16_t RESERVED34;
+    __IM uint32_t RESERVED35[3];
+
+    union
+    {
+        __IM uint16_t WDT_PDI;           /*!< (@ 0x00000410) Watchdog Time PDI Register                                 */
+
+        struct
+        {
+            __IM uint16_t WDTIMPDI : 16; /*!< [15..0] Watchdog Overflow Time Setting                                    */
+        } WDT_PDI_b;
+    };
+    __IM uint16_t RESERVED36;
+    __IM uint32_t RESERVED37[3];
+
+    union
+    {
+        __IM uint16_t WDT_DATA;         /*!< (@ 0x00000420) Watchdog Time Process Data Register                        */
+
+        struct
+        {
+            __IM uint16_t WDTIMPD : 16; /*!< [15..0] Watchdog Overflow Time Setting                                    */
+        } WDT_DATA_b;
+    };
+    __IM uint16_t RESERVED38;
+    __IM uint32_t RESERVED39[7];
+
+    union
+    {
+        __IM uint16_t WDS_DATA;        /*!< (@ 0x00000440) Watchdog Status Process Data Register                      */
+
+        struct
+        {
+            __IM uint16_t WDSTAPD : 1; /*!< [0..0] Watchdog State Indication                                          */
+            uint16_t              : 15;
+        } WDS_DATA_b;
+    };
+
+    union
+    {
+        __IM uint8_t WDC_DATA;         /*!< (@ 0x00000442) Watchdog Counter Process Data Register                     */
+
+        struct
+        {
+            __IM uint8_t WDCNTPD : 8;  /*!< [7..0] Watchdog Counter Value Indication                                  */
+        } WDC_DATA_b;
+    };
+
+    union
+    {
+        __IM uint8_t WDC_PDI;          /*!< (@ 0x00000443) Watchdog Counter PDI Register                              */
+
+        struct
+        {
+            __IM uint8_t WDCNTPDI : 8; /*!< [7..0] Watchdog Counter Value Indication                                  */
+        } WDC_PDI_b;
+    };
+    __IM uint32_t RESERVED40[47];
+
+    union
+    {
+        __IM uint8_t EEP_CONF;          /*!< (@ 0x00000500) EEPROM Configuration Register                              */
+
+        struct
+        {
+            __IM uint8_t CTRLPDI   : 1; /*!< [0..0] PDI EEPROM Control                                                 */
+            __IM uint8_t FORCEECAT : 1; /*!< [1..1] EEPROM Access Right Change                                         */
+            uint8_t                : 6;
+        } EEP_CONF_b;
+    };
+
+    union
+    {
+        __IOM uint8_t EEP_STATE;         /*!< (@ 0x00000501) EEPROM PDI Access State Register                           */
+
+        struct
+        {
+            __IOM uint8_t PDIACCESS : 1; /*!< [0..0] EEPROM Access Right Setting                                        */
+            uint8_t                 : 7;
+        } EEP_STATE_b;
+    };
+
+    union
+    {
+        __IOM uint16_t EEP_CONT_STAT;     /*!< (@ 0x00000502) EEPROM Control/Status Register                             */
+
+        struct
+        {
+            __IM uint16_t ECATWREN   : 1; /*!< [0..0] ECAT Write Enable                                                  */
+            uint16_t                 : 5;
+            __IM uint16_t  READBYTE  : 1; /*!< [6..6] EEPROM Read Byte Indication                                        */
+            __IM uint16_t  PROMSIZE  : 1; /*!< [7..7] EEPROM Algorithm Indication                                        */
+            __IOM uint16_t COMMAND   : 3; /*!< [10..8] Command                                                           */
+            __IM uint16_t  CKSUMERR  : 1; /*!< [11..11] Checksum Error Indication                                        */
+            __IM uint16_t  LOADSTA   : 1; /*!< [12..12] EEPROM Loading Status Indication                                 */
+            __IM uint16_t  ACKCMDERR : 1; /*!< [13..13] Acknowledge/Command Error Indication                             */
+            __IM uint16_t  WRENERR   : 1; /*!< [14..14] Write Enable Error Indication                                    */
+            __IM uint16_t  BUSY      : 1; /*!< [15..15] EEPROM Interface State Indication                                */
+        } EEP_CONT_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEP_ADR;          /*!< (@ 0x00000504) EEPROM Address Register                                    */
+
+        struct
+        {
+            __IOM uint32_t ADDRESS : 32; /*!< [31..0] EEPROM Address Setting                                            */
+        } EEP_ADR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEP_DATA;        /*!< (@ 0x00000508) EEPROM Data Register                                       */
+
+        struct
+        {
+            __IOM uint32_t LODATA : 16; /*!< [15..0] Data to be written to the EEPROM or data read from the
+                                         *   EEPROM (lower 2 bytes)                                                    */
+            __IM uint32_t HIDATA : 16;  /*!< [31..16] Data read from the EEPROM (upper 2 bytes)                        */
+        } EEP_DATA_b;
+    };
+    __IM uint32_t RESERVED41;
+
+    union
+    {
+        __IOM uint16_t MII_CONT_STAT;     /*!< (@ 0x00000510) MII Management Control/Status Register                     */
+
+        struct
+        {
+            __IM uint16_t  WREN      : 1; /*!< [0..0] Write Enable                                                       */
+            __IM uint16_t  PDICTRL   : 1; /*!< [1..1] PDI Control Indication                                             */
+            __IM uint16_t  MILINK    : 1; /*!< [2..2] MI Link Detection                                                  */
+            __IM uint16_t  PHYOFFSET : 5; /*!< [7..3] PHY Address Offset Indication                                      */
+            __IOM uint16_t COMMAND   : 2; /*!< [9..8] Command                                                            */
+            uint16_t                 : 3;
+            __IOM uint16_t READERR   : 1; /*!< [13..13] Read Error Indication                                            */
+            __IM uint16_t  CMDERR    : 1; /*!< [14..14] Command Error Indication                                         */
+            __IM uint16_t  BUSY      : 1; /*!< [15..15] MII Management State Indication                                  */
+        } MII_CONT_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PHY_ADR;         /*!< (@ 0x00000512) PHY Address Register                                       */
+
+        struct
+        {
+            __IOM uint8_t PHYADDR : 5; /*!< [4..0] PHY Address Setting                                                */
+            uint8_t               : 3;
+        } PHY_ADR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PHY_REG_ADR;        /*!< (@ 0x00000513) PHY Register Address Register                              */
+
+        struct
+        {
+            __IOM uint8_t PHYREGADDR : 5; /*!< [4..0] Address of PHY register                                            */
+            uint8_t                  : 3;
+        } PHY_REG_ADR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PHY_DATA;            /*!< (@ 0x00000514) PHY Data Register                                          */
+
+        struct
+        {
+            __IOM uint16_t PHYREGDATA : 16; /*!< [15..0] PHY Register Data Indication/Setting                              */
+        } PHY_DATA_b;
+    };
+
+    union
+    {
+        __IM uint8_t MII_ECAT_ACS_STAT; /*!< (@ 0x00000516) MII Management ECAT Access State Register                  */
+
+        struct
+        {
+            __IM uint8_t ACSMII : 1;    /*!< [0..0] MII Management Interface Access Right Setting                      */
+            uint8_t             : 7;
+        } MII_ECAT_ACS_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MII_PDI_ACS_STAT; /*!< (@ 0x00000517) MII Management PDI Access State Register                   */
+
+        struct
+        {
+            __IOM uint8_t ACSMII : 1;   /*!< [0..0] Right of access to the MII management interface                    */
+            __IM uint8_t  FORPDI : 1;   /*!< [1..1] Forced change of access by the PDI (forced change of
+                                         *   bit 0)                                                                    */
+            uint8_t : 6;
+        } MII_PDI_ACS_STAT_b;
+    };
+    __IM uint32_t         RESERVED42[58];
+    __IOM R_ESC_FMMU_Type FMMU[8];     /*!< (@ 0x00000600) FMMU [0..7] Registers (n = 0 to 7)                         */
+    __IM uint32_t         RESERVED43[96];
+    __IOM R_ESC_SM_Type   SM[8];       /*!< (@ 0x00000800) SyncManager [0..7] Registers (n = 0 to 7)                  */
+    __IM uint32_t         RESERVED44[48];
+
+    union
+    {
+        __IM uint32_t DC_RCV_TIME_PORT[3]; /*!< (@ 0x00000900) Receive Time Port [0..2] Register                          */
+
+        struct
+        {
+            __IM uint32_t RCVTIME0 : 32;   /*!< [31..0] Receive Time Indication/Latch                                     */
+        } DC_RCV_TIME_PORT_b[3];
+    };
+    __IM uint32_t RESERVED45;
+    __IM uint32_t DC_SYS_TIME_L;           /*!< (@ 0x00000910) System Time Register L                                     */
+    __IM uint32_t DC_SYS_TIME_H;           /*!< (@ 0x00000914) System Time Register H                                     */
+    __IM uint32_t DC_RCV_TIME_UNIT_L;      /*!< (@ 0x00000918) Receive Time ECAT Processing Unit Register L               */
+    __IM uint32_t DC_RCV_TIME_UNIT_H;      /*!< (@ 0x0000091C) Receive Time ECAT Processing Unit Register H               */
+    __IM uint32_t DC_SYS_TIME_OFFSET_L;    /*!< (@ 0x00000920) System Time Offset Register L                              */
+    __IM uint32_t DC_SYS_TIME_OFFSET_H;    /*!< (@ 0x00000924) System Time Offset Register H                              */
+
+    union
+    {
+        __IM uint32_t DC_SYS_TIME_DELAY;   /*!< (@ 0x00000928) System Time Delay Register                                 */
+
+        struct
+        {
+            __IM uint32_t SYSTIMDLY : 32;  /*!< [31..0] Propagation Delay Indication                                      */
+        } DC_SYS_TIME_DELAY_b;
+    };
+
+    union
+    {
+        __IM uint32_t DC_SYS_TIME_DIFF; /*!< (@ 0x0000092C) System Time Difference Register                            */
+
+        struct
+        {
+            __IM uint32_t DIFF : 31;    /*!< [30..0] System Time Mean Difference Indication                            */
+            __IM uint32_t LCP  : 1;     /*!< [31..31] System Time Greater/Less Indication                              */
+        } DC_SYS_TIME_DIFF_b;
+    };
+
+    union
+    {
+        __IM uint16_t DC_SPEED_COUNT_START; /*!< (@ 0x00000930) Speed Counter Start Register                               */
+
+        struct
+        {
+            __IM uint16_t SPDCNTSTRT : 15;  /*!< [14..0] Drift Correction Bandwidth Setting                                */
+            uint16_t                 : 1;
+        } DC_SPEED_COUNT_START_b;
+    };
+
+    union
+    {
+        __IM uint16_t DC_SPEED_COUNT_DIFF; /*!< (@ 0x00000932) Speed Counter Difference Register                          */
+
+        struct
+        {
+            __IM uint16_t SPDCNTDIFF : 16; /*!< [15..0] Clock Period Deviation Indication                                 */
+        } DC_SPEED_COUNT_DIFF_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_SYS_TIME_DIFF_FIL_DEPTH; /*!< (@ 0x00000934) System Time Difference Filter Depth Register               */
+
+        struct
+        {
+            __IM uint8_t SYSTIMDEP : 4;          /*!< [3..0] Filter Depth Setting                                               */
+            uint8_t                : 4;
+        } DC_SYS_TIME_DIFF_FIL_DEPTH_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_SPEED_COUNT_FIL_DEPTH; /*!< (@ 0x00000935) Speed Counter Filter Depth Register                        */
+
+        struct
+        {
+            __IM uint8_t CLKPERDEP : 4;        /*!< [3..0] Filter Depth Setting                                               */
+            uint8_t                : 4;
+        } DC_SPEED_COUNT_FIL_DEPTH_b;
+    };
+    __IM uint16_t RESERVED46;
+    __IM uint32_t RESERVED47[18];
+
+    union
+    {
+        __IM uint8_t DC_CYC_CONT;      /*!< (@ 0x00000980) Cyclic Unit Control Register                               */
+
+        struct
+        {
+            __IM uint8_t SYNCOUT : 1;  /*!< [0..0] SYNC Output Unit Control Setting                                   */
+            uint8_t              : 3;
+            __IM uint8_t LATCH0  : 1;  /*!< [4..4] Latch Input Unit 0 Control Setting                                 */
+            __IM uint8_t LATCH1  : 1;  /*!< [5..5] Latch Input Unit 1 Control Setting                                 */
+            uint8_t              : 2;
+        } DC_CYC_CONT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DC_ACT;               /*!< (@ 0x00000981) Activation Register                                        */
+
+        struct
+        {
+            __IOM uint8_t SYNCACT      : 1; /*!< [0..0] Sync Output Unit Activation                                        */
+            __IOM uint8_t SYNC0        : 1; /*!< [1..1] SYNC0 Output Setting                                               */
+            __IOM uint8_t SYNC1        : 1; /*!< [2..2] SYNC1 Output Setting                                               */
+            __IOM uint8_t AUTOACT      : 1; /*!< [3..3] SYNC Output Unit Activation                                        */
+            __IOM uint8_t EXTSTARTTIME : 1; /*!< [4..4] Start Time Cyclic Operation Extension                              */
+            __IOM uint8_t STARTTIME    : 1; /*!< [5..5] Start Time Plausibility                                            */
+            __IOM uint8_t NEARFUTURE   : 1; /*!< [6..6] Near Future Range Setting                                          */
+            __IOM uint8_t DBGPULSE     : 1; /*!< [7..7] Debug Pulse Setting                                                */
+        } DC_ACT_b;
+    };
+
+    union
+    {
+        __IM uint16_t DC_PULSE_LEN;      /*!< (@ 0x00000982) SYNC Signal Pulse Length Register                          */
+
+        struct
+        {
+            __IM uint16_t PULSELEN : 16; /*!< [15..0] SYNC Signal Pulse Length Indication                               */
+        } DC_PULSE_LEN_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_ACT_STAT;       /*!< (@ 0x00000984) Activation Status Register                                 */
+
+        struct
+        {
+            __IM uint8_t SYNC0ACT  : 1; /*!< [0..0] SYNC0 Status Indication                                            */
+            __IM uint8_t SYNC1ACT  : 1; /*!< [1..1] SYNC1 Status Indication                                            */
+            __IM uint8_t STARTTIME : 1; /*!< [2..2] Plausibility Result Indication                                     */
+            uint8_t                : 5;
+        } DC_ACT_STAT_b;
+    };
+    __IM uint8_t  RESERVED48;
+    __IM uint16_t RESERVED49;
+    __IM uint32_t RESERVED50;
+    __IM uint16_t RESERVED51;
+
+    union
+    {
+        __IM uint8_t DC_SYNC0_STAT;    /*!< (@ 0x0000098E) SYNC0 Status Register                                      */
+
+        struct
+        {
+            __IM uint8_t SYNC0STA : 1; /*!< [0..0] SYNC0 State Indication                                             */
+            uint8_t               : 7;
+        } DC_SYNC0_STAT_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_SYNC1_STAT;       /*!< (@ 0x0000098F) SYNC1 Status Register                                      */
+
+        struct
+        {
+            __IM uint8_t SYNC1STA : 1;    /*!< [0..0] SYNC1 State Indication                                             */
+            uint8_t               : 7;
+        } DC_SYNC1_STAT_b;
+    };
+    __IOM uint32_t DC_CYC_START_TIME_L;   /*!< (@ 0x00000990) Start Time Cyclic Operation/Next SYNC0 Pulse
+                                           *                  Register L                                                 */
+    __IOM uint32_t DC_CYC_START_TIME_H;   /*!< (@ 0x00000994) Start Time Cyclic Operation/Next SYNC0 Pulse
+                                           *                  Register H                                                 */
+    __IM uint32_t DC_NEXT_SYNC1_PULSE_L;  /*!< (@ 0x00000998) Next SYNC1 Pulse Register L                                */
+    __IM uint32_t DC_NEXT_SYNC1_PULSE_H;  /*!< (@ 0x0000099C) Next SYNC1 Pulse Register H                                */
+
+    union
+    {
+        __IOM uint32_t DC_SYNC0_CYC_TIME; /*!< (@ 0x000009A0) SYNC0 Cycle Time Register                                  */
+
+        struct
+        {
+            __IOM uint32_t SYNC0CYC : 32; /*!< [31..0] Time Between Consecutive SYNC0 Pulses                             */
+        } DC_SYNC0_CYC_TIME_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DC_SYNC1_CYC_TIME; /*!< (@ 0x000009A4) SYNC1 Cycle Time Register                                  */
+
+        struct
+        {
+            __IOM uint32_t SYNC1CYC : 32; /*!< [31..0] Time between SYNC1 and SYNC0 Pulses                               */
+        } DC_SYNC1_CYC_TIME_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DC_LATCH0_CONT;  /*!< (@ 0x000009A8) Latch 0 Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 0 Positive Edge Function Setting                             */
+            __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 0 Negative Edge Function Setting                             */
+            uint8_t               : 6;
+        } DC_LATCH0_CONT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DC_LATCH1_CONT;  /*!< (@ 0x000009A9) Latch 1 Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 1 Positive Edge Function Setting                             */
+            __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 1 Negative Edge Function Setting                             */
+            uint8_t               : 6;
+        } DC_LATCH1_CONT_b;
+    };
+    __IM uint16_t RESERVED52[2];
+
+    union
+    {
+        __IM uint8_t DC_LATCH0_STAT;   /*!< (@ 0x000009AE) Latch 0 Status Register                                    */
+
+        struct
+        {
+            __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 0 Positive Edge Event Indication                             */
+            __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 0 Negative Edge Event Indication                             */
+            __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 0 Input Pin State Indication                                 */
+            uint8_t               : 5;
+        } DC_LATCH0_STAT_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_LATCH1_STAT;    /*!< (@ 0x000009AF) Latch 1 Status Register                                    */
+
+        struct
+        {
+            __IM uint8_t EVENTPOS : 1;  /*!< [0..0] Latch 1 Positive Edge Event Indication                             */
+            __IM uint8_t EVENTNEG : 1;  /*!< [1..1] Latch 1 Negative Edge Event Indication                             */
+            __IM uint8_t PINSTATE : 1;  /*!< [2..2] Latch 1 Input Pin State Indication                                 */
+            uint8_t               : 5;
+        } DC_LATCH1_STAT_b;
+    };
+    __IM uint32_t DC_LATCH0_TIME_POS_L; /*!< (@ 0x000009B0) Latch 0 Time Positive Edge Register L                      */
+    __IM uint32_t DC_LATCH0_TIME_POS_H; /*!< (@ 0x000009B4) Latch 0 Time Positive Edge Register H                      */
+    __IM uint32_t DC_LATCH0_TIME_NEG_L; /*!< (@ 0x000009B8) Latch 0 Time Negative Edge Register L                      */
+    __IM uint32_t DC_LATCH0_TIME_NEG_H; /*!< (@ 0x000009BC) Latch 0 Time Negative Edge Register H                      */
+    __IM uint32_t DC_LATCH1_TIME_POS_L; /*!< (@ 0x000009C0) Latch 1 Time Positive Edge Register L                      */
+    __IM uint32_t DC_LATCH1_TIME_POS_H; /*!< (@ 0x000009C4) Latch 1 Time Positive Edge Register H                      */
+    __IM uint32_t DC_LATCH1_TIME_NEG_L; /*!< (@ 0x000009C8) Latch 1 Time Negative Edge Register L                      */
+    __IM uint32_t DC_LATCH1_TIME_NEG_H; /*!< (@ 0x000009CC) Latch 1 Time Negative Edge Register H                      */
+    __IM uint32_t RESERVED53[8];
+
+    union
+    {
+        __IM uint32_t DC_ECAT_CNG_EV_TIME; /*!< (@ 0x000009F0) Buffer Change Event Time Register                          */
+
+        struct
+        {
+            __IM uint32_t ECATCHANGE : 32; /*!< [31..0] Local Time Indication                                             */
+        } DC_ECAT_CNG_EV_TIME_b;
+    };
+    __IM uint32_t RESERVED54;
+
+    union
+    {
+        __IM uint32_t DC_PDI_START_EV_TIME; /*!< (@ 0x000009F8) PDI Buffer Start Event Time Register                       */
+
+        struct
+        {
+            __IM uint32_t PDISTART : 32;    /*!< [31..0] Local Time Indication                                             */
+        } DC_PDI_START_EV_TIME_b;
+    };
+
+    union
+    {
+        __IM uint32_t DC_PDI_CNG_EV_TIME; /*!< (@ 0x000009FC) PDI Buffer Change Event Time Register                      */
+
+        struct
+        {
+            __IM uint32_t PDICHANGE : 32; /*!< [31..0] Local Time Indication                                             */
+        } DC_PDI_CNG_EV_TIME_b;
+    };
+    __IM uint32_t RESERVED55[256];
+    __IM uint32_t PRODUCT_ID_L;           /*!< (@ 0x00000E00) Product ID Register L                                      */
+    __IM uint32_t PRODUCT_ID_H;           /*!< (@ 0x00000E04) Product ID Register H                                      */
+
+    union
+    {
+        __IM uint32_t VENDOR_ID_L;        /*!< (@ 0x00000E08) Vendor ID Register L                                       */
+
+        struct
+        {
+            __IM uint32_t VENDORID : 32;  /*!< [31..0] Vendor ID Indication                                              */
+        } VENDOR_ID_L_b;
+    };
+} R_ESC_Type;                             /*!< Size = 3596 (0xe0c)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USBHC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 HS Host Module (R_USBHC)
+ */
+
+typedef struct                         /*!< (@ 0x80200000) R_USBHC Structure                                          */
+{
+    union
+    {
+        __IM uint32_t HCREVISION;      /*!< (@ 0x00000000) HcRevision Register                                        */
+
+        struct
+        {
+            __IM uint32_t REV : 8;     /*!< [7..0] HCI revision                                                       */
+            uint32_t          : 24;
+        } HCREVISION_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCCONTROL;      /*!< (@ 0x00000004) HcControl Register                                         */
+
+        struct
+        {
+            __IOM uint32_t CBSR : 2;   /*!< [1..0] Control/bulk transfer service ratio (ControlBulkServiceRatio)      */
+            __IOM uint32_t PLE  : 1;   /*!< [2..2] Periodic list setting (PeriodicListEnable)                         */
+            __IOM uint32_t IE   : 1;   /*!< [3..3] Isochronous ED processing setting (IsochronousEnable)              */
+            __IOM uint32_t CLE  : 1;   /*!< [4..4] Control list processing setting (ControlListEnable)                */
+            __IOM uint32_t BLE  : 1;   /*!< [5..5] Bulk list processing setting (BulkListEnable)                      */
+            __IOM uint32_t HCFS : 2;   /*!< [7..6] Host logic operation status (Host Controller FunctionalState)      */
+            __IOM uint32_t IR   : 1;   /*!< [8..8] HcInterruptStatus interrupt path setting (InterruptRouting)        */
+            __IOM uint32_t RWC  : 1;   /*!< [9..9] Remote Wakeup support setting (RemoteWakeUpConnect)                */
+            __IOM uint32_t RWE  : 1;   /*!< [10..10] PME assertion control (RemoteWakeUpEnable)                       */
+            uint32_t            : 21;
+        } HCCONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCCOMMANDSTATUS; /*!< (@ 0x00000008) HcCommandStatus Register                                   */
+
+        struct
+        {
+            __OM uint32_t  HCR : 1;     /*!< [0..0] Host logic software reset start (HostController Reset)             */
+            __IOM uint32_t CLF : 1;     /*!< [1..1] Control list TD (ControlList Filled)                               */
+            __IOM uint32_t BLF : 1;     /*!< [2..2] Bulk list TD (BulkListFilled)                                      */
+            __OM uint32_t  OCR : 1;     /*!< [3..3] Host logic control right change (OwnershipChangeRequest)           */
+            uint32_t           : 12;
+            __IM uint32_t SOC  : 2;     /*!< [17..16] Schedule overrun count (Scheduling OverrunCount)                 */
+            uint32_t           : 14;
+        } HCCOMMANDSTATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCINTERRUPTSTATUS; /*!< (@ 0x0000000C) HcInterruptStatus Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SO  : 1;       /*!< [0..0] USB schedule overrun (Scheduling Overrun)                          */
+            __IOM uint32_t WDH : 1;       /*!< [1..1] Host logic HccaDoneHead update (Writeback Done Head)               */
+            __IOM uint32_t SF  : 1;       /*!< [2..2] HccaFrameNumber update (StartOfFrame)                              */
+            __IOM uint32_t RD  : 1;       /*!< [3..3] Resume detection (Resume Detected)                                 */
+            __IOM uint32_t UE  : 1;       /*!< [4..4] USB non-related system error detection (Unrecoverable
+                                           *   Error)                                                                    */
+            __IOM uint32_t FNO  : 1;      /*!< [5..5] FrameNumber bit MSB change (Frame Number Overflow)                 */
+            __IOM uint32_t RHSC : 1;      /*!< [6..6] HcRhStatus/HcRhPortStatus register status (RootHubStatus
+                                           *   Change)                                                                   */
+            uint32_t          : 23;
+            __IOM uint32_t OC : 1;        /*!< [30..30] Host logic control right change (OwnershipChange)                */
+            uint32_t          : 1;
+        } HCINTERRUPTSTATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCINTERRUPTENABLE; /*!< (@ 0x00000010) HcInterruptEnable Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SOE   : 1;     /*!< [0..0] SO interrupt source enable (Scheduling OverrunEnable)              */
+            __IOM uint32_t WDHE  : 1;     /*!< [1..1] WDH interrupt source enable (WritebackDone HeadEnable)             */
+            __IOM uint32_t SFE   : 1;     /*!< [2..2] SF interrupt source enable (StartOfFrame)                          */
+            __IOM uint32_t RDE   : 1;     /*!< [3..3] RD interrupt source enable (Resume DetectedEnable)                 */
+            __IOM uint32_t UEE   : 1;     /*!< [4..4] UE interrupt source enable (Unrecoverable ErrorEnable)             */
+            __IOM uint32_t FNOE  : 1;     /*!< [5..5] FNO interrupt source enable (FrameNumber OverflowEnable)           */
+            __IOM uint32_t RHSCE : 1;     /*!< [6..6] RHSC interrupt source enable (RootHubStatus ChangeEnable)          */
+            uint32_t             : 23;
+            __IOM uint32_t OCE   : 1;     /*!< [30..30] OC interrupt source enable (OwnershipChangeEnable)               */
+            __IOM uint32_t MIE   : 1;     /*!< [31..31] Interrupt 8 source enable (MasterInterrupt Enable)               */
+        } HCINTERRUPTENABLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCINTERRUPTDISABLE; /*!< (@ 0x00000014) HcInterruptDisable Register                                */
+
+        struct
+        {
+            __IOM uint32_t SOD   : 1;      /*!< [0..0] SO interrupt source disable (Scheduling Overrun Disable)           */
+            __IOM uint32_t WDHD  : 1;      /*!< [1..1] WDH interrupt source disable (Writeback DoneHead Disable)          */
+            __IOM uint32_t SFD   : 1;      /*!< [2..2] SF interrupt source disable (StartOfFrame Disable)                 */
+            __IOM uint32_t RDD   : 1;      /*!< [3..3] RD interrupt source disable (Resume Detected Disable)              */
+            __IOM uint32_t UED   : 1;      /*!< [4..4] UE interrupt source disable (Unrecoverable ErrorDisable)           */
+            __IOM uint32_t FNOD  : 1;      /*!< [5..5] FNO interrupt source disable (FrameNumberOverflow Disable)         */
+            __IOM uint32_t RHSCD : 1;      /*!< [6..6] RHSC interrupt source disable (RootHub StatusChange Disable)       */
+            uint32_t             : 23;
+            __IOM uint32_t OCD   : 1;      /*!< [30..30] OC interrupt source disable (OwnershipChangeDisable)             */
+            __IOM uint32_t MID   : 1;      /*!< [31..31] Interrupt 8 source disable (Master Interrupt Disable)            */
+        } HCINTERRUPTDISABLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCHCCA;         /*!< (@ 0x00000018) HcHCCA Register                                            */
+
+        struct
+        {
+            uint32_t             : 8;
+            __IOM uint32_t RAMBA : 24; /*!< [31..8] RAM base address setting                                          */
+        } HCHCCA_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCPERIODCCURRENTIED; /*!< (@ 0x0000001C) HcPeriodicCurrentED Register                               */
+
+        struct
+        {
+            uint32_t           : 4;
+            __IM uint32_t PCED : 28;   /*!< [31..4] ED physical address (PeriodicCurrentED)                           */
+        } HCPERIODCCURRENTIED_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCCONTROLHEADED; /*!< (@ 0x00000020) HcControlHeadED Register                                   */
+
+        struct
+        {
+            uint32_t            : 4;
+            __IOM uint32_t CHED : 28;  /*!< [31..4] Start ED physical address (ControlHeadED)                         */
+        } HCCONTROLHEADED_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCCONTROLCURRENTED; /*!< (@ 0x00000024) HcControlCurrentED Register                                */
+
+        struct
+        {
+            uint32_t            : 4;
+            __IOM uint32_t CCED : 28;  /*!< [31..4] ED physical address (ControlCurrentED)                            */
+        } HCCONTROLCURRENTED_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCBULKHEADED;   /*!< (@ 0x00000028) HcBulkHeadED Register                                      */
+
+        struct
+        {
+            uint32_t            : 4;
+            __IOM uint32_t BHED : 28;  /*!< [31..4] Start ED physical address (BulkHeadED)                            */
+        } HCBULKHEADED_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCBULKCURRENTED; /*!< (@ 0x0000002C) HcBulkCurrentED Register                                   */
+
+        struct
+        {
+            uint32_t            : 4;
+            __IOM uint32_t BCED : 28;  /*!< [31..4] ED physical address (BulkCurrentED)                               */
+        } HCBULKCURRENTED_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCDONEHEAD;      /*!< (@ 0x00000030) HcDoneHead Register                                        */
+
+        struct
+        {
+            uint32_t         : 4;
+            __IM uint32_t DH : 28;     /*!< [31..4] HcDoneHead physical address (DoneHead)                            */
+        } HCDONEHEAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCFMINTERVAL;   /*!< (@ 0x00000034) HcFmInterval Register                                      */
+
+        struct
+        {
+            __IOM uint32_t FI    : 14; /*!< [13..0] Frame interval setting (FrameInterval)                            */
+            uint32_t             : 2;
+            __IOM uint32_t FSMPS : 15; /*!< [30..16] FS transfer packet maximum size setting (FSLagest DataPacket)    */
+            __IOM uint32_t FIT   : 1;  /*!< [31..31] Frame synchronization (FrameInterval Toggle)                     */
+        } HCFMINTERVAL_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCFNREMAINING;   /*!< (@ 0x00000038) HcFmRemaining Register                                     */
+
+        struct
+        {
+            __IM uint32_t FR  : 14;    /*!< [13..0] Down counter frame (FrameRemaining)                               */
+            uint32_t          : 17;
+            __IM uint32_t FRT : 1;     /*!< [31..31] Frame synchronization (FrameRemainingToggle)                     */
+        } HCFNREMAINING_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCFMNUMBER;      /*!< (@ 0x0000003C) HcFmNumber Register                                        */
+
+        struct
+        {
+            __IM uint32_t FN : 16;     /*!< [15..0] Elapsed frame number (FrameNumber)                                */
+            uint32_t         : 16;
+        } HCFMNUMBER_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCPERIODSTART;  /*!< (@ 0x00000040) HcPeriodicStart Register                                   */
+
+        struct
+        {
+            __IOM uint32_t PS : 14;    /*!< [13..0] Periodic list processing start time (PeriodicStart)               */
+            uint32_t          : 18;
+        } HCPERIODSTART_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCLSTHRESHOLD;  /*!< (@ 0x00000044) HcLSThreshold Register                                     */
+
+        struct
+        {
+            __IOM uint32_t LS : 12;    /*!< [11..0] Transferrable threshold (LSThreshold)                             */
+            uint32_t          : 20;
+        } HCLSTHRESHOLD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCRHDESCRIPTORA; /*!< (@ 0x00000048) HcRhDescriptorA Register                                   */
+
+        struct
+        {
+            __IM uint32_t  NDP  : 8;    /*!< [7..0] Downstream port number (NumberDownstreamPorts)                     */
+            __IOM uint32_t PSM  : 1;    /*!< [8..8] Power switch control (PowerSwitchingMode)                          */
+            __IOM uint32_t NPS  : 1;    /*!< [9..9] Power control (NoPower Switching)                                  */
+            __IM uint32_t  DT   : 1;    /*!< [10..10] Device type (DeviceType)                                         */
+            __IOM uint32_t OCPM : 1;    /*!< [11..11] Overcurrent state reporting (OverCurrentProtection
+                                         *   Mode)                                                                     */
+            __IOM uint32_t NOCP   : 1;  /*!< [12..12] Overcurrent function support (NoOver Current Protection)         */
+            uint32_t              : 11;
+            __IOM uint32_t POTPGT : 8;  /*!< [31..24] Wait time (PowerOnToPowerGood Time)                              */
+        } HCRHDESCRIPTORA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCRHDESCRIPTORB; /*!< (@ 0x0000004C) HcRhDescriptorB Register                                   */
+
+        struct
+        {
+            __IOM uint32_t DR   : 16;   /*!< [15..0] Device Removable                                                  */
+            __IOM uint32_t PPCM : 16;   /*!< [31..16] Port Power Control Mask                                          */
+        } HCRHDESCRIPTORB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCRHSTATUS;     /*!< (@ 0x00000050) HcRhStatus Register                                        */
+
+        struct
+        {
+            __IOM uint32_t LPS  : 1;   /*!< [0..0] Local power status (LocalPowerStatus)                              */
+            __IM uint32_t  OCI  : 1;   /*!< [1..1] Overcurrent indicator (OverCurrent Indicator)                      */
+            uint32_t            : 13;
+            __IOM uint32_t DRWE : 1;   /*!< [15..15] Device remote start enable (DeviceRemoteWakeupEnable)            */
+            __IOM uint32_t LPSC : 1;   /*!< [16..16] Local power status change (LocalPowerStatusChange)               */
+            __IOM uint32_t OCIC : 1;   /*!< [17..17] OCI bit change report (OverCurrent Indicate Change)              */
+            uint32_t            : 13;
+            __OM uint32_t CRWE  : 1;   /*!< [31..31] DRWE bit clear (Clear Remote Wakeup Enable)                      */
+        } HCRHSTATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCRHPORTSTATUS1; /*!< (@ 0x00000054) HcRhPortStatus1 Register                                   */
+
+        struct
+        {
+            __IOM uint32_t CCS  : 1;    /*!< [0..0] Connection status indication (CurrentConnectStatus)                */
+            __IOM uint32_t PES  : 1;    /*!< [1..1] Port enable status (PortEnableStatus)                              */
+            __IOM uint32_t PSS  : 1;    /*!< [2..2] Suspend/Resume status (PortSuspendStatus)                          */
+            __IM uint32_t  POCI : 1;    /*!< [3..3] Downstream port overcurrent detection (PortOverCurrentIndicator)   */
+            __IOM uint32_t PRS  : 1;    /*!< [4..4] Port reset status (PortResetStatus)                                */
+            uint32_t            : 3;
+            __IOM uint32_t PPS  : 1;    /*!< [8..8] Power status (PortPowerStatus)                                     */
+            __IOM uint32_t LSDA : 1;    /*!< [9..9] Device speed (LowSpeedDeviceAttached)                              */
+            uint32_t            : 6;
+            __IOM uint32_t CSC  : 1;    /*!< [16..16] CCS bit status (ConnectStatus Change)                            */
+            __IOM uint32_t PESC : 1;    /*!< [17..17] PES bit status (PortEnable StatusChange)                         */
+            __IOM uint32_t PSSC : 1;    /*!< [18..18] RESUME sequence complete (PortSuspend StatusChange)              */
+            __IOM uint32_t OCIC : 1;    /*!< [19..19] Overcurrent state detection (OverCurrent IndicateChange)         */
+            __IOM uint32_t PRSC : 1;    /*!< [20..20] Port reset complete (PortReset StatusChange)                     */
+            uint32_t            : 11;
+        } HCRHPORTSTATUS1_b;
+    };
+    __IM uint32_t RESERVED[42];
+
+    union
+    {
+        __IM uint32_t CAPL_VERSION;    /*!< (@ 0x00000100) Capability Registers Length and EHCI Version
+                                        *                  Number Register                                            */
+
+        struct
+        {
+            __IM uint32_t CRL   : 8;   /*!< [7..0] Capability Registers Length                                        */
+            uint32_t            : 8;
+            __IM uint32_t HCIVN : 16;  /*!< [31..16] EHCI Version Number                                              */
+        } CAPL_VERSION_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCSPARAMS;           /*!< (@ 0x00000104) Structural Parameters Register                             */
+
+        struct
+        {
+            __IM uint32_t N_PORTS     : 4; /*!< [3..0] Number of downstream ports (Number of Ports)                       */
+            __IM uint32_t PPC         : 1; /*!< [4..4] Port power control (Port Power Control)                            */
+            uint32_t                  : 2;
+            __IM uint32_t PTRR        : 1; /*!< [7..7] Port routing rules                                                 */
+            __IM uint32_t N_PCC       : 4; /*!< [11..8] Number of ports (Number of Ports per Companion Controller)        */
+            __IM uint32_t N_CC        : 4; /*!< [15..12] Number of OHCI host logic (Number of Companion Controller)       */
+            __IM uint32_t P_INDICATOR : 1; /*!< [16..16] Port indicator control support                                   */
+            uint32_t                  : 3;
+            __IM uint32_t DBGPTNUM    : 4; /*!< [23..20] Debug port number                                                */
+            uint32_t                  : 8;
+        } HCSPARAMS_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCCPARAMS;       /*!< (@ 0x00000108) Capability Parameters Register                             */
+
+        struct
+        {
+            __IM uint32_t AC64 : 1;    /*!< [0..0] Memory pointer selection                                           */
+            __IM uint32_t PFLF : 1;    /*!< [1..1] Programming frame list flag                                        */
+            __IM uint32_t ASPC : 1;    /*!< [2..2] Asynchronous schedule park support capability                      */
+            uint32_t           : 1;
+            __IM uint32_t IST  : 4;    /*!< [7..4] Isochronous data structure threshold                               */
+            __IM uint32_t EECP : 8;    /*!< [15..8] Offset address (EHCI Extend Capabilities Pointer)                 */
+            __IM uint32_t HP   : 1;    /*!< [16..16] Hardware prefetch capability                                     */
+            __IM uint32_t LPMC : 1;    /*!< [17..17] Link power management capability                                 */
+            __IM uint32_t PCEC : 1;    /*!< [18..18] Per-port change event capability                                 */
+            __IM uint32_t PL32 : 1;    /*!< [19..19] 32-frame periodic list capability                                */
+            uint32_t           : 12;
+        } HCCPARAMS_b;
+    };
+    __IM uint32_t HCSP_PORTROUTE;      /*!< (@ 0x0000010C) Companion Port Route Description Register                  */
+    __IM uint32_t RESERVED1[4];
+
+    union
+    {
+        __IOM uint32_t USBCMD;          /*!< (@ 0x00000120) USB Command Register                                       */
+
+        struct
+        {
+            __IOM uint32_t RS      : 1; /*!< [0..0] EHCI host logic run/stop (Run/Stop)                                */
+            __IOM uint32_t HCRESET : 1; /*!< [1..1] Host logic initialization (Host Controller Reset)                  */
+            __IOM uint32_t FLS     : 2; /*!< [3..2] Frame list size                                                    */
+            __IOM uint32_t PSE     : 1; /*!< [4..4] Periodic schedule enable                                           */
+            __IOM uint32_t ASYNSE  : 1; /*!< [5..5] Asynchronous schedule enable                                       */
+            __IOM uint32_t IAAD    : 1; /*!< [6..6] Interrupt on Async Advance Doorbell                                */
+            __IM uint32_t  LHCR    : 1; /*!< [7..7] Light host controller reset execution status                       */
+            __IOM uint32_t ASPMC   : 2; /*!< [9..8] Asynchronous schedule park mode count                              */
+            uint32_t               : 1;
+            __IOM uint32_t ASPME   : 1; /*!< [11..11] Asynchronous schedule park mode enable                           */
+            uint32_t               : 3;
+            __IOM uint32_t PPCEE   : 1; /*!< [15..15] Per-port change event enable                                     */
+            __IOM uint32_t ITC     : 8; /*!< [23..16] Host logic interrupt generation maximum rate (Interrupt
+                                         *   Threshold Control)                                                        */
+            __IOM uint32_t HIRD : 4;    /*!< [27..24] Host-Initiated Resume Duration (Minimum K-state drive
+                                         *   time)                                                                     */
+            uint32_t : 4;
+        } USBCMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t USBSTS;             /*!< (@ 0x00000124) USB Status Register                                        */
+
+        struct
+        {
+            __IOM uint32_t USBINT    : 1;  /*!< [0..0] USB transfer complete (USB Interrupt)                              */
+            __IOM uint32_t USBERRINT : 1;  /*!< [1..1] USB transaction status (USB Error Interrupt)                       */
+            __IOM uint32_t PTCGDET   : 1;  /*!< [2..2] Port state change detection                                        */
+            __IOM uint32_t FLROV     : 1;  /*!< [3..3] Frame list rollover                                                */
+            __IOM uint32_t HSYSE     : 1;  /*!< [4..4] Host system error                                                  */
+            __IOM uint32_t IAAIS     : 1;  /*!< [5..5] Async advance interrupt status                                     */
+            uint32_t                 : 6;
+            __IM uint32_t  EHCSTS    : 1;  /*!< [12..12] EHCI host logic status (HCHalted)                                */
+            __IM uint32_t  RECLAM    : 1;  /*!< [13..13] Empty asynchronous schedule detection (Reclamation)              */
+            __IM uint32_t  PSCHSTS   : 1;  /*!< [14..14] Periodic schedule status                                         */
+            __IM uint32_t  ASS       : 1;  /*!< [15..15] Asynchronous schedule status                                     */
+            __IOM uint32_t PTCGDETC  : 16; /*!< [31..16] Port-n Change Detect                                             */
+        } USBSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t USBINTR;           /*!< (@ 0x00000128) USB Interrupt Enable Register                              */
+
+        struct
+        {
+            __IOM uint32_t USBIE    : 1;  /*!< [0..0] USB interrupt enable                                               */
+            __IOM uint32_t USBEIE   : 1;  /*!< [1..1] USB error interrupt enable                                         */
+            __IOM uint32_t PTCGIE   : 1;  /*!< [2..2] Port change interrupt enable                                       */
+            __IOM uint32_t FMLSTROE : 1;  /*!< [3..3] Frame list rollover enable                                         */
+            __IOM uint32_t HSEE     : 1;  /*!< [4..4] Host system error enable                                           */
+            __IOM uint32_t INTAADVE : 1;  /*!< [5..5] Interrupt on async advance enable                                  */
+            uint32_t                : 10;
+            __IOM uint32_t PCGIE    : 16; /*!< [31..16] Port-n Change Interrupt Enable                                   */
+        } USBINTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRINDEX;             /*!< (@ 0x0000012C) USB Frame Index Register                                   */
+
+        struct
+        {
+            __IOM uint32_t FRAMEINDEX : 14; /*!< [13..0] Frame index                                                       */
+            uint32_t                  : 18;
+        } FRINDEX_b;
+    };
+    __IM uint32_t CTRLDSSEGMENT;            /*!< (@ 0x00000130) Control Data Structure Segment Register                    */
+
+    union
+    {
+        __IOM uint32_t PERIODICLISTBASE;    /*!< (@ 0x00000134) Periodic Frame List Base Address Register                  */
+
+        struct
+        {
+            uint32_t             : 12;
+            __IOM uint32_t PFLSA : 20; /*!< [31..12] Periodic frame list start address                                */
+        } PERIODICLISTBASE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ASYNCLISTADDR;  /*!< (@ 0x00000138) Next Asynchronous List Address Register                    */
+
+        struct
+        {
+            uint32_t           : 5;
+            __IOM uint32_t LPL : 27;   /*!< [31..5] Asynchronous Queue Head link pointer address (Link Pointer
+                                        *   Low)                                                                      */
+        } ASYNCLISTADDR_b;
+    };
+    __IM uint32_t RESERVED2[9];
+
+    union
+    {
+        __IOM uint32_t CONFIGFLAG;     /*!< (@ 0x00000160) Configure Flag Register                                    */
+
+        struct
+        {
+            __IOM uint32_t CF : 1;     /*!< [0..0] Port routing control circuit configuration flag (Configure
+                                        *   Flag)                                                                     */
+            uint32_t : 31;
+        } CONFIGFLAG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PORTSC1;            /*!< (@ 0x00000164) Port 1 Status and Control Register                         */
+
+        struct
+        {
+            __IM uint32_t  CCSTS    : 1;   /*!< [0..0] Port connection status                                             */
+            __IOM uint32_t CSC      : 1;   /*!< [1..1] Connect status change                                              */
+            __IOM uint32_t PTE      : 1;   /*!< [2..2] Port enable/disable status                                         */
+            __IOM uint32_t PTESC    : 1;   /*!< [3..3] Port enable/disable status change                                  */
+            __IM uint32_t  OVCACT   : 1;   /*!< [4..4] Port overcurrent status                                            */
+            __IOM uint32_t OVCC     : 1;   /*!< [5..5] Over-current Change                                                */
+            __IOM uint32_t FRCPTRSM : 1;   /*!< [6..6] Force Port Resume (Port resume detection flag)                     */
+            __IOM uint32_t SUSPEND  : 1;   /*!< [7..7] Port suspend                                                       */
+            __IOM uint32_t PTRST    : 1;   /*!< [8..8] Port reset status                                                  */
+            __IOM uint32_t LPMCTL   : 1;   /*!< [9..9] LPM control                                                        */
+            __IM uint32_t  LINESTS  : 2;   /*!< [11..10] D+/D- logic level                                              */
+            __IOM uint32_t PP       : 1;   /*!< [12..12] Port Power Supply Control (Port Power)                           */
+            __IOM uint32_t PTOWNR   : 1;   /*!< [13..13] Port ownership                                                   */
+            __IM uint32_t  PTINDCTL : 2;   /*!< [15..14] As the host logic does not support the port indicator
+                                            *   control function, these bits are set to 00b.                              */
+            __IOM uint32_t PTTST    : 4;   /*!< [19..16] Pin test control                                                 */
+            __IOM uint32_t WKCNNT_E : 1;   /*!< [20..20] Device connection detection enable (Wake on Connect
+                                            *   Enable)                                                                   */
+            __IOM uint32_t WKDSCNNT_E : 1; /*!< [21..21] Device disconnection detection enable (Wake on Disconnect
+                                            *   Enable)                                                                   */
+            __IOM uint32_t WKOC_E : 1;     /*!< [22..22] Overcurrent state detection enable (Wake on Over-current
+                                            *   Enable)                                                                   */
+            __IOM uint32_t SUSPSTS : 2;    /*!< [24..23] Suspend status                                                   */
+            __IOM uint32_t DVADDR  : 7;    /*!< [31..25] USB device address                                               */
+        } PORTSC1_b;
+    };
+    __IM uint32_t RESERVED3[38];
+
+    union
+    {
+        __IOM uint32_t INTENABLE;            /*!< (@ 0x00000200) INT_ENABLE Register                                        */
+
+        struct
+        {
+            __IOM uint32_t AHB_INTEN    : 1; /*!< [0..0] AHB_INT bit control                                                */
+            __IOM uint32_t USBH_INTAEN  : 1; /*!< [1..1] USBH_INTA bit control                                              */
+            __IOM uint32_t USBH_INTBEN  : 1; /*!< [2..2] USBH_INTB bit control                                              */
+            __IOM uint32_t UCOM_INTEN   : 1; /*!< [3..3] UCOM_INT bit control                                               */
+            __IOM uint32_t WAKEON_INTEN : 1; /*!< [4..4] WAKEON_INT bit control                                             */
+            uint32_t                    : 27;
+        } INTENABLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INTSTATUS;          /*!< (@ 0x00000204) INT_STATUS Register                                        */
+
+        struct
+        {
+            __IOM uint32_t AHB_INT    : 1; /*!< [0..0] AHB bus error indication                                           */
+            __IM uint32_t  USBH_INTA  : 1; /*!< [1..1] OHCI interrupt status                                              */
+            __IM uint32_t  USBH_INTB  : 1; /*!< [2..2] USBH_INTB EHCI interrupt status                                    */
+            __IM uint32_t  UCOM_INT   : 1; /*!< [3..3] UCOM register interrupt status                                     */
+            __IOM uint32_t WAKEON_INT : 1; /*!< [4..4] WAKEON interrupt status                                            */
+            uint32_t                  : 27;
+        } INTSTATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AHBBUSCTR;             /*!< (@ 0x00000208) AHB_BUS_CTR Register                                       */
+
+        struct
+        {
+            __IOM uint32_t MAX_BURST_LEN : 2; /*!< [1..0] Maximum burst length                                               */
+            uint32_t                     : 2;
+            __IOM uint32_t ALIGN_ADDRESS : 2; /*!< [5..4] Address boundary setting                                           */
+            uint32_t                     : 2;
+            __IOM uint32_t PROT_MODE     : 1; /*!< [8..8] This bit selects the MHPROT[3:0] mode when the AHB master
+                                               *   interface initiates a transfer.                                           */
+            uint32_t                 : 3;
+            __IOM uint32_t PROT_TYPE : 4;     /*!< [15..12] These bits set MHPROT[3:0] when the AHB master interface
+                                               *   initiates a transfer.                                                     */
+            uint32_t : 16;
+        } AHBBUSCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t USBCTR;           /*!< (@ 0x0000020C) USBCTR Register                                            */
+
+        struct
+        {
+            __OM uint32_t  USBH_RST : 1; /*!< [0..0] Software reset for the core                                        */
+            __IOM uint32_t PLL_RST  : 1; /*!< [1..1] Reset of USB PHY PLL                                               */
+            __IOM uint32_t DIRPD    : 1; /*!< [2..2] Direct transition to power-down state                              */
+            uint32_t                : 29;
+        } USBCTR_b;
+    };
+    __IM uint32_t RESERVED4[60];
+
+    union
+    {
+        __IM uint32_t REVID;           /*!< (@ 0x00000300) Revision and Core ID Register                              */
+
+        struct
+        {
+            __IM uint32_t MINV   : 8;  /*!< [7..0] Minor Version                                                      */
+            __IM uint32_t MAJV   : 8;  /*!< [15..8] Major Version                                                     */
+            uint32_t             : 8;
+            __IM uint32_t COREID : 8;  /*!< [31..24] Core ID                                                          */
+        } REVID_b;
+    };
+    __IM uint32_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint32_t OCSLPTIMSET;          /*!< (@ 0x00000310) Overcurrent Detection/Sleep Timer Setting Register         */
+
+        struct
+        {
+            __IOM uint32_t TIMER_OC    : 20; /*!< [19..0] Overcurrent Timer setting                                         */
+            __IOM uint32_t TIMER_SLEEP : 9;  /*!< [28..20] Detection/Sleep Timer Setting                                    */
+            uint32_t                   : 3;
+        } OCSLPTIMSET_b;
+    };
+    __IM uint32_t RESERVED6[315];
+
+    union
+    {
+        __IOM uint32_t COMMCTRL;       /*!< (@ 0x00000800) Common Control Register                                    */
+
+        struct
+        {
+            uint32_t            : 31;
+            __IOM uint32_t PERI : 1;   /*!< [31..31] USB mode setting                                                 */
+        } COMMCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OBINTSTA;             /*!< (@ 0x00000804) OTG-BC Interrupt Status Register                           */
+
+        struct
+        {
+            __IOM uint32_t IDCHG_STA    : 1; /*!< [0..0] USB_OTGID change status                                            */
+            __IOM uint32_t OCINT_STA    : 1; /*!< [1..1] USB_OVRCUR assertion status                                        */
+            __IOM uint32_t VBSTACHG_STA : 1; /*!< [2..2] VBSTA[3:0] change status                                           */
+            __IOM uint32_t VBSTAINT_STA : 1; /*!< [3..3] VBUS voltage status interrupt                                      */
+            uint32_t                    : 12;
+            __IOM uint32_t DMMONCHG_STA : 1; /*!< [16..16] DMMON change status                                              */
+            __IOM uint32_t DPMONCHG_STA : 1; /*!< [17..17] DPMON change status                                              */
+            uint32_t                    : 14;
+        } OBINTSTA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OBINTEN;             /*!< (@ 0x00000808) OTG-BC Interrupt Enable Register                           */
+
+        struct
+        {
+            __IOM uint32_t IDCHG_EN    : 1; /*!< [0..0] IDCHG_STA Interrupt enable                                         */
+            __IOM uint32_t OCINT_EN    : 1; /*!< [1..1] OCINT_STA interrupt enable                                         */
+            __IOM uint32_t VBSTACHG_EN : 1; /*!< [2..2] VBSTACHG_STA interrupt enable                                      */
+            __IOM uint32_t VBSTAINT_EN : 1; /*!< [3..3] VBSTAINT_STA interrupt enable                                      */
+            uint32_t                   : 12;
+            __IOM uint32_t DMMONCHG_EN : 1; /*!< [16..16] DMMONCHG_STA interrupt enable                                    */
+            __IOM uint32_t DPMONCHG_EN : 1; /*!< [17..17] DPMONCHG_STA interrupt enable                                    */
+            uint32_t                   : 14;
+        } OBINTEN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VBCTRL;            /*!< (@ 0x0000080C) VBUS Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t VBOUT     : 1; /*!< [0..0] VBUS drive control (USB_VBUSEN pin)                                */
+            __IOM uint32_t VBUSENSEL : 1; /*!< [1..1] USB_VBUSEN pin control                                             */
+            uint32_t                 : 2;
+            __IOM uint32_t VGPUO     : 1; /*!< [4..4] USB_EXICEN pin control                                             */
+            uint32_t                 : 11;
+            __IOM uint32_t OCCLRIEN  : 1; /*!< [16..16] USB_VBUSEN pin control at occurrence of overcurrent              */
+            __IOM uint32_t OCISEL    : 1; /*!< [17..17] Overcurrent detection                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t VBLVL     : 4; /*!< [23..20] VBUS level detection                                             */
+            uint32_t                 : 4;
+            __IM uint32_t VBSTA      : 4; /*!< [31..28] VBUS indication                                                  */
+        } VBCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LINECTRL1;        /*!< (@ 0x00000810) Line Control Port 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t IDMON   : 1;   /*!< [0..0] Indicates a value of USB_OTGID input pin.                          */
+            uint32_t              : 1;
+            __IM uint32_t DMMON   : 1;   /*!< [2..2] Indicates a value of USB bus DM.                                   */
+            __IM uint32_t DPMON   : 1;   /*!< [3..3] Indicates a value of USB bus DP.                                   */
+            uint32_t              : 12;
+            __IOM uint32_t DM_RPD : 1;   /*!< [16..16] Controls USB bus (DM) 15 kOhm pulldown resistor when
+                                          *   DMPPD_EN = 1.                                                             */
+            __IOM uint32_t DMRPD_EN : 1; /*!< [17..17] Enables DM_RPD to control USB bus (DM) 15 kOhm pulldown
+                                          *   resistor.                                                                 */
+            __IOM uint32_t DP_RPD : 1;   /*!< [18..18] Controls USB bus (DP) 15 kOhm pulldown resistor when
+                                          *   DRPPD_EN = 1.                                                             */
+            __IOM uint32_t DPRPD_EN : 1; /*!< [19..19] Enables DP_RPD to control USB bus (DP) 15 kOhm pulldown
+                                          *   resistor.                                                                 */
+            uint32_t : 12;
+        } LINECTRL1_b;
+    };
+} R_USBHC_Type;                          /*!< Size = 2068 (0x814)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USBF                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 Host and Function Module (R_USBF)
+ */
+
+typedef struct                         /*!< (@ 0x80201000) R_USBF Structure                                           */
+{
+    union
+    {
+        __IOM uint16_t SYSCFG0;        /*!< (@ 0x00000000) System Configuration Control Register 0                    */
+
+        struct
+        {
+            __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Block Operation Enable                                         */
+            uint16_t             : 3;
+            __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
+            __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                      */
+            uint16_t             : 1;
+            __IOM uint16_t HSE   : 1;  /*!< [7..7] High-Speed Operation Enable                                        */
+            __IOM uint16_t CNEN  : 1;  /*!< [8..8] Single-End Receiver Operation Enable                               */
+            uint16_t             : 7;
+        } SYSCFG0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SYSCFG1;        /*!< (@ 0x00000002) System Configuration Control Register 1                    */
+
+        struct
+        {
+            __IOM uint16_t BWAIT : 6;  /*!< [5..0] CPU Bus Access Wait Specification                                  */
+            uint16_t             : 2;
+            __IOM uint16_t AWAIT : 6;  /*!< [13..8] AHB-DMA Bridge Bus Access Wait Specification                      */
+            uint16_t             : 2;
+        } SYSCFG1_b;
+    };
+
+    union
+    {
+        __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register                       */
+
+        struct
+        {
+            __IM uint16_t LNST : 2;    /*!< [1..0] USB Data Line Status Monitor                                       */
+            uint16_t           : 14;
+        } SYSSTS0_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t DVSTCTR0;       /*!< (@ 0x00000008) Device State Control Register 0                            */
+
+        struct
+        {
+            __IM uint16_t RHST  : 3;   /*!< [2..0] Reset Handshake                                                    */
+            uint16_t            : 5;
+            __IOM uint16_t WKUP : 1;   /*!< [8..8] Wakeup Output                                                      */
+            uint16_t            : 7;
+        } DVSTCTR0_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
+
+        struct
+        {
+            __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
+            uint16_t            : 12;
+        } TESTMODE_b;
+    };
+    __IM uint16_t RESERVED2;
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CFIFO;             /*!< (@ 0x00000014) FIFO Port Register                                         */
+
+            struct
+            {
+                __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
+            } CFIFO_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) FIFO Port Register                                         */
+                __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) FIFO Port Register                                         */
+            };
+
+            union
+            {
+                union
+                {
+                    __IOM uint16_t CFIFOH;            /*!< (@ 0x00000016) FIFO Port Register                                         */
+
+                    struct
+                    {
+                        __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
+                    } CFIFOH_b;
+                };
+
+                struct
+                {
+                    __IM uint8_t RESERVED4;
+
+                    union
+                    {
+                        __IOM uint8_t CFIFOHH;          /*!< (@ 0x00000017) FIFO Port Register                                         */
+
+                        struct
+                        {
+                            __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
+                        } CFIFOHH_b;
+                    };
+                };
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t D0FIFO;            /*!< (@ 0x00000018) FIFO Port Register                                         */
+
+            struct
+            {
+                __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
+            } D0FIFO_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) FIFO Port Register                                         */
+                __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) FIFO Port Register                                         */
+            };
+
+            union
+            {
+                union
+                {
+                    __IOM uint16_t D0FIFOH;           /*!< (@ 0x0000001A) FIFO Port Register                                         */
+
+                    struct
+                    {
+                        __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
+                    } D0FIFOH_b;
+                };
+
+                struct
+                {
+                    __IM uint8_t RESERVED5;
+
+                    union
+                    {
+                        __IOM uint8_t D0FIFOHH;         /*!< (@ 0x0000001B) FIFO Port Register                                         */
+
+                        struct
+                        {
+                            __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
+                        } D0FIFOHH_b;
+                    };
+                };
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t D1FIFO;            /*!< (@ 0x0000001C) FIFO Port Register                                         */
+
+            struct
+            {
+                __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
+            } D1FIFO_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) FIFO Port Register                                         */
+                __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) FIFO Port Register                                         */
+            };
+
+            union
+            {
+                union
+                {
+                    __IOM uint16_t D1FIFOH;           /*!< (@ 0x0000001E) FIFO Port Register                                         */
+
+                    struct
+                    {
+                        __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
+                    } D1FIFOH_b;
+                };
+
+                struct
+                {
+                    __IM uint8_t RESERVED6;
+
+                    union
+                    {
+                        __IOM uint8_t D1FIFOHH;         /*!< (@ 0x0000001F) FIFO Port Register                                         */
+
+                        struct
+                        {
+                            __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
+                        } D1FIFOHH_b;
+                    };
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 1;
+            __IOM uint16_t ISEL    : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected                    */
+            uint16_t               : 2;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
+            uint16_t               : 2;
+            __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
+        } CFIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) FIFO Port Control Register                                 */
+
+        struct
+        {
+            __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } CFIFOCTR_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA Request Enable                                               */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe
+                                         *   Data is Read                                                              */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D0FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) FIFO Port Control Register                                 */
+
+        struct
+        {
+            __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D0FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA Request Enable                                               */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe
+                                         *   Data is Read                                                              */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D1FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) FIFO Port Control Register                                 */
+
+        struct
+        {
+            __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D1FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
+            __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
+            __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
+            __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
+            __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
+            __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
+            __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
+            __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
+        } INTENB0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB1;           /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINTE : 1; /*!< [0..0] PDDETINT Detection Interrupt Enable                                */
+            uint16_t                 : 15;
+        } INTENB1_b;
+    };
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe                                */
+            uint16_t                 : 6;
+        } BRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe                                */
+            uint16_t                 : 6;
+        } NRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe                                */
+            uint16_t                 : 6;
+        } BEMPENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Pin Configuration Register                             */
+
+        struct
+        {
+            uint16_t               : 4;
+            __IM uint16_t  EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status                                   */
+            __IOM uint16_t INTL    : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
+            __IOM uint16_t BRDYM   : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing                             */
+            uint16_t               : 9;
+        } SOFCFG_b;
+    };
+    __IM uint16_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
+
+        struct
+        {
+            __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
+            __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
+            __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
+            __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
+            __IM uint16_t  BRDY  : 1;  /*!< [8..8] BRDY Interrupt Status                                              */
+            __IM uint16_t  NRDY  : 1;  /*!< [9..9] NRDY Interrupt Status                                              */
+            __IM uint16_t  BEMP  : 1;  /*!< [10..10] BEMP Interrupt Status                                            */
+            __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
+            __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
+            __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Update Interrupt Status                             */
+            __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
+            __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Change Detect Interrupt Status                              */
+        } INTSTS0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS1;          /*!< (@ 0x00000042) Interrupt Status Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINT : 1; /*!< [0..0] PDDET Detection Interrupt Status                                   */
+            uint16_t                : 15;
+        } INTSTS1_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe                                */
+            uint16_t                : 6;
+        } BRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe                                */
+            uint16_t                : 6;
+        } NRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe                                */
+            uint16_t                : 6;
+        } BEMPSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
+
+        struct
+        {
+            __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame Number                                                      */
+            uint16_t            : 3;
+            __IOM uint16_t CRCE : 1;   /*!< [14..14] CRC Error Detection Status                                       */
+            __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
+        } FRMNUM_b;
+    };
+
+    union
+    {
+        __IM uint16_t UFRMNUM;         /*!< (@ 0x0000004E) Frame Number Register                                      */
+
+        struct
+        {
+            __IM uint16_t UFRNM : 3;   /*!< [2..0] Microframe Number                                                  */
+            uint16_t            : 13;
+        } UFRMNUM_b;
+    };
+
+    union
+    {
+        __IM uint16_t USBADDR;         /*!< (@ 0x00000050) USB Address Register                                       */
+
+        struct
+        {
+            __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address                                                        */
+            uint16_t              : 9;
+        } USBADDR_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
+
+        struct
+        {
+            __IM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request Type                                                       */
+            __IM uint16_t BREQUEST      : 8; /*!< [15..8] Request                                                           */
+        } USBREQ_b;
+    };
+
+    union
+    {
+        __IM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
+
+        struct
+        {
+            __IM uint16_t WVALUE : 16; /*!< [15..0] Value                                                             */
+        } USBVAL_b;
+    };
+
+    union
+    {
+        __IM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
+
+        struct
+        {
+            __IM uint16_t WINDEX : 16; /*!< [15..0] Index                                                             */
+        } USBINDX_b;
+    };
+
+    union
+    {
+        __IM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
+
+        struct
+        {
+            __IM uint16_t WLENGTH : 16; /*!< [15..0] Length                                                            */
+        } USBLENG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
+
+        struct
+        {
+            uint16_t              : 7;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Disabling PIPE at the End of Transfer                              */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
+            uint16_t              : 7;
+        } DCPCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet Size                                                */
+            uint16_t            : 9;
+        } DCPMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCTR;         /*!< (@ 0x00000060) DCP Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t PID   : 2;  /*!< [1..0] Response PID                                                       */
+            __IOM uint16_t CCPL  : 1;  /*!< [2..2] Control Transfer End Enable                                        */
+            uint16_t             : 2;
+            __IM uint16_t  PBUSY : 1;  /*!< [5..5] PIPE Busy                                                          */
+            __IM uint16_t  SQMON : 1;  /*!< [6..6] Sequence Toggle Bit Monitor                                        */
+            __IOM uint16_t SQSET : 1;  /*!< [7..7] Toggle Bit Set                                                     */
+            __IOM uint16_t SQCLR : 1;  /*!< [8..8] Toggle Bit Clear                                                   */
+            uint16_t             : 6;
+            __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
+        } DCPCTR_b;
+    };
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
+            uint16_t               : 12;
+        } PIPESEL_b;
+    };
+    __IM uint16_t RESERVED13;
+
+    union
+    {
+        __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
+
+        struct
+        {
+            __IOM uint16_t EPNUM  : 4; /*!< [3..0] Endpoint Number                                                    */
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disable at the End of Transfer                                */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
+            __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
+            __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
+            uint16_t              : 3;
+            __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
+        } PIPECFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Specification Register                         */
+
+        struct
+        {
+            __IOM uint16_t BUFNMB  : 8; /*!< [7..0] Buffer number                                                      */
+            uint16_t               : 2;
+            __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer size                                                      */
+            uint16_t               : 1;
+        } PIPEBUF_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 11;  /*!< [10..0] Maximum Packet Size                                               */
+            uint16_t            : 5;
+        } PIPEMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Timing Control Register                               */
+
+        struct
+        {
+            __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection Spacing                                   */
+            uint16_t            : 9;
+            __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
+            uint16_t            : 3;
+        } PIPEPERI_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) PIPE[0..8] Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
+            uint16_t              : 3;
+            __IM uint16_t  PBUSY  : 1; /*!< [5..5] PIPE Busy                                                          */
+            __IM uint16_t  SQMON  : 1; /*!< [6..6] Toggle Bit Confirm                                                 */
+            __IOM uint16_t SQSET  : 1; /*!< [7..7] Toggle Bit Set                                                     */
+            __IOM uint16_t SQCLR  : 1; /*!< [8..8] Toggle Bit Clear                                                   */
+            __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
+            __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
+            uint16_t              : 3;
+            __IM uint16_t INBUFM  : 1; /*!< [14..14] Transfer Buffer Monitor                                          */
+            __IM uint16_t BSTS    : 1; /*!< [15..15] Buffer Status                                                    */
+        } PIPE_CTR_b[9];
+    };
+    __IM uint16_t             RESERVED14;
+    __IM uint32_t             RESERVED15[3];
+    __IOM R_USBF_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) PIPEn Transaction Counter Registers (n=1-5)                */
+    __IM uint32_t             RESERVED16[23];
+    __IM uint16_t             RESERVED17;
+
+    union
+    {
+        __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
+
+        struct
+        {
+            uint16_t             : 14;
+            __IOM uint16_t SUSPM : 1;  /*!< [14..14] UTMI SuspendM Control                                            */
+            uint16_t             : 1;
+        } LPSTS_b;
+    };
+    __IM uint32_t         RESERVED18[191];
+    __IOM R_USBF_CHa_Type CHa[2];      /*!< (@ 0x00000400) Next Register Set                                          */
+    __IM uint32_t         RESERVED19[96];
+    __IOM R_USBF_CHb_Type CHb[2];      /*!< (@ 0x00000600) Skip Register Set                                          */
+    __IM uint32_t         RESERVED20[48];
+
+    union
+    {
+        __IOM uint32_t DCTRL;          /*!< (@ 0x00000700) DMA Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t PR   : 1;   /*!< [0..0] Priority                                                           */
+            uint32_t            : 15;
+            __IOM uint32_t LDPR : 4;   /*!< [19..16] Link Descriptor PROT                                             */
+            uint32_t            : 4;
+            __IOM uint32_t LWPR : 4;   /*!< [27..24] Link WriteBack PROT                                              */
+            uint32_t            : 4;
+        } DCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCITVL;        /*!< (@ 0x00000704) Descriptor Interval Register                               */
+
+        struct
+        {
+            uint32_t             : 8;
+            __IOM uint32_t DITVL : 8;  /*!< [15..8] Descriptor Interval                                               */
+            uint32_t             : 16;
+        } DSCITVL_b;
+    };
+    __IM uint32_t RESERVED21[2];
+
+    union
+    {
+        __IM uint32_t DSTAT_EN;        /*!< (@ 0x00000710) DMA Status EN Register                                     */
+
+        struct
+        {
+            __IM uint32_t EN0 : 1;     /*!< [0..0] Channel 0 EN                                                       */
+            __IM uint32_t EN1 : 1;     /*!< [1..1] Channel 1 EN                                                       */
+            uint32_t          : 30;
+        } DSTAT_EN_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_ER;        /*!< (@ 0x00000714) DMA Status ER Register                                     */
+
+        struct
+        {
+            __IM uint32_t ER0 : 1;     /*!< [0..0] Channel 0 ER                                                       */
+            __IM uint32_t ER1 : 1;     /*!< [1..1] Channel 1 ER                                                       */
+            uint32_t          : 30;
+        } DSTAT_ER_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_END;       /*!< (@ 0x00000718) DMA Status END Register                                    */
+
+        struct
+        {
+            __IM uint32_t END0 : 1;    /*!< [0..0] Channel 0 END                                                      */
+            __IM uint32_t END1 : 1;    /*!< [1..1] Channel 1 END                                                      */
+            uint32_t           : 30;
+        } DSTAT_END_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_TC;        /*!< (@ 0x0000071C) DMA Status TC Register                                     */
+
+        struct
+        {
+            __IM uint32_t TC0 : 1;     /*!< [0..0] Channel 0 TC                                                       */
+            __IM uint32_t TC1 : 1;     /*!< [1..1] Channel 1 TC                                                       */
+            uint32_t          : 30;
+        } DSTAT_TC_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_SUS;       /*!< (@ 0x00000720) DMA Status SUS Register                                    */
+
+        struct
+        {
+            __IM uint32_t SUS0 : 1;    /*!< [0..0] Channel 0 SUS                                                      */
+            __IM uint32_t SUS1 : 1;    /*!< [1..1] Channel 1 SUS                                                      */
+            uint32_t           : 30;
+        } DSTAT_SUS_b;
+    };
+} R_USBF_Type;                         /*!< Size = 1828 (0x724)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BSC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus State Controller (R_BSC)
+ */
+
+typedef struct                         /*!< (@ 0x80210000) R_BSC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t CMNCR;          /*!< (@ 0x00000000) Common Control Register                                    */
+
+        struct
+        {
+            uint32_t             : 9;
+            __IOM uint32_t DPRTY : 2;  /*!< [10..9] DMA Burst Transfer Priority                                       */
+            uint32_t             : 13;
+            __IOM uint32_t AL    : 1;  /*!< [24..24] Acknowledge Level                                                */
+            uint32_t             : 3;
+            __IOM uint32_t TL    : 1;  /*!< [28..28] Transfer End Level                                               */
+            uint32_t             : 3;
+        } CMNCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CSnBCR[6];      /*!< (@ 0x00000004) CS[0..5] Space Bus Control Register                        */
+
+        struct
+        {
+            uint32_t             : 9;
+            __IOM uint32_t BSZ   : 2;  /*!< [10..9] Data Bus Width Specification                                      */
+            uint32_t             : 1;
+            __IOM uint32_t TYPE  : 3;  /*!< [14..12] Memory Connected to a Space                                      */
+            uint32_t             : 1;
+            __IOM uint32_t IWRRS : 3;  /*!< [18..16] Idle State Insertion between Read-Read Cycles in the
+                                        *   Same CS Space                                                             */
+            __IOM uint32_t IWRRD : 3;  /*!< [21..19] Idle State Insertion between Read-Read Cycles in Different
+                                        *   CS Spaces                                                                 */
+            __IOM uint32_t IWRWS : 3;  /*!< [24..22] Idle State Insertion between Read-Write Cycles in the
+                                        *   Same CS Space                                                             */
+            __IOM uint32_t IWRWD : 3;  /*!< [27..25] Idle State Insertion between Read-Write Cycles in Different
+                                        *   CS Spaces                                                                 */
+            __IOM uint32_t IWW : 3;    /*!< [30..28] Idle Cycles between Write-Read Cycles and Write-Write
+                                        *   Cycles                                                                    */
+            uint32_t : 1;
+        } CSnBCR_b[6];
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CS0WCR_0;    /*!< (@ 0x00000028) CS0 Space Wait Control Register for Normal Space,
+                                         *                  SRAM with Byte Selection                                   */
+
+            struct
+            {
+                __IOM uint32_t HW : 2;  /*!< [1..0] Delay States from RD#, WEn# Negation to Address, CS0#
+                                         *   Negation                                                                  */
+                uint32_t          : 4;
+                __IOM uint32_t WM : 1;  /*!< [6..6] External Wait Mask Specification                                   */
+                __IOM uint32_t WR : 4;  /*!< [10..7] Number of Access Waits                                            */
+                __IOM uint32_t SW : 2;  /*!< [12..11] Number of Delay Cycles from Address, CSn# Assertion
+                                         *   to RD#, WEn# Assertion                                                    */
+                uint32_t           : 7;
+                __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
+                uint32_t           : 11;
+            } CS0WCR_0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t CS0WCR_1;   /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM
+                                        *                  with Clocked Asynchronous                                  */
+
+            struct
+            {
+                uint32_t           : 6;
+                __IOM uint32_t WM  : 1; /*!< [6..6] External Wait Mask Specification                                   */
+                __IOM uint32_t W   : 4; /*!< [10..7] Number of Access Waits                                            */
+                uint32_t           : 5;
+                __IOM uint32_t BW  : 2; /*!< [17..16] Number of Waits during Burst Access                              */
+                uint32_t           : 2;
+                __IOM uint32_t BST : 2; /*!< [21..20] Burst Count Specification                                        */
+                uint32_t           : 10;
+            } CS0WCR_1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t CS0WCR_2;   /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM
+                                        *                  with Clocked Synchronous                                   */
+
+            struct
+            {
+                uint32_t          : 6;
+                __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification                                   */
+                __IOM uint32_t W  : 4; /*!< [10..7] Number of Access Waits                                            */
+                uint32_t          : 5;
+                __IOM uint32_t BW : 2; /*!< [17..16] Number of Burst Wait Cycles                                      */
+                uint32_t          : 14;
+            } CS0WCR_2_b;
+        };
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CS2WCR_0;   /*!< (@ 0x00000030) CS2 Space Wait Control Register for Normal Space,
+                                        *                  SRAM with Byte Selection                                   */
+
+            struct
+            {
+                uint32_t           : 6;
+                __IOM uint32_t WM  : 1; /*!< [6..6] External Wait Mask Specification                                   */
+                __IOM uint32_t WR  : 4; /*!< [10..7] Number of Access Waits                                            */
+                uint32_t           : 9;
+                __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
+                uint32_t           : 11;
+            } CS2WCR_0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t CS2WCR_1;   /*!< (@ 0x00000030) CS2 Space Wait Control Register for SDRAM                  */
+
+            struct
+            {
+                uint32_t            : 7;
+                __IOM uint32_t A2CL : 2; /*!< [8..7] CAS Latency for Area 2                                             */
+                uint32_t            : 23;
+            } CS2WCR_1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CS3WCR_0;   /*!< (@ 0x00000034) CS3 Space Wait Control Register for Normal Space,
+                                        *                  SRAM with Byte Selection                                   */
+
+            struct
+            {
+                uint32_t           : 6;
+                __IOM uint32_t WM  : 1; /*!< [6..6] External Wait Mask Specification                                   */
+                __IOM uint32_t WR  : 4; /*!< [10..7] Number of Access Waits                                            */
+                uint32_t           : 9;
+                __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
+                uint32_t           : 11;
+            } CS3WCR_0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t CS3WCR_1;      /*!< (@ 0x00000034) CS3 Space Wait Control Register for SDRAM                  */
+
+            struct
+            {
+                __IOM uint32_t WTRC : 2;  /*!< [1..0] Number of Idle States from REF Command/Self-Refresh Release
+                                           *   to ACTV/REF/MRS Command                                                   */
+                uint32_t             : 1;
+                __IOM uint32_t TRWL  : 2; /*!< [4..3] Number of Auto-Precharge Startup Wait Cycles                       */
+                uint32_t             : 2;
+                __IOM uint32_t A3CL  : 2; /*!< [8..7] CAS Latency for Area 3                                             */
+                uint32_t             : 1;
+                __IOM uint32_t WTRCD : 2; /*!< [11..10] Number of Waits between ACTV Command and READ(A)/WRIT(A)
+                                           *   Command                                                                   */
+                uint32_t            : 1;
+                __IOM uint32_t WTRP : 2;  /*!< [14..13] Number of Auto-Precharge Completion Wait States                  */
+                uint32_t            : 17;
+            } CS3WCR_1_b;
+        };
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t CS5WCR;           /*!< (@ 0x0000003C) CS5 Space Wait Control Register for Normal Space,
+                                          *                  SRAM with Byte Selection, and MPX-I/O                      */
+
+        struct
+        {
+            __IOM uint32_t HW : 2;       /*!< [1..0] Delay Cycles from RD#, WEn# to Address, CS5#                       */
+            uint32_t          : 4;
+            __IOM uint32_t WM : 1;       /*!< [6..6] External Wait Mask Specification                                   */
+            __IOM uint32_t WR : 4;       /*!< [10..7] Number of Read Access Waits                                       */
+            __IOM uint32_t SW : 2;       /*!< [12..11] Number of Delay Cycles from Address, CS5# Assertion
+                                          *   to RD#, WEn# Assertion                                                    */
+            uint32_t                : 3;
+            __IOM uint32_t WW       : 3; /*!< [18..16] Number of Write Access Waits                                     */
+            uint32_t                : 1;
+            __IOM uint32_t MPXWSBAS : 1; /*!< [20..20] MPX-I/O Interface Address Cycle Wait and SRAM with
+                                          *   Byte Selection Byte Access Select                                         */
+            __IOM uint32_t SZSEL : 1;    /*!< [21..21] MPX-I/O Interface Bus Width Specification                        */
+            uint32_t             : 10;
+        } CS5WCR_b;
+    };
+    __IM uint32_t RESERVED3[3];
+
+    union
+    {
+        __IOM uint32_t SDCR;           /*!< (@ 0x0000004C) SDRAM Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t A3COL : 2;  /*!< [1..0] Number of Bits of Column Address for Area 3                        */
+            uint32_t             : 1;
+            __IOM uint32_t A3ROW : 2;  /*!< [4..3] Number of Bits of Row Address for Area 3                           */
+            uint32_t             : 3;
+            __IOM uint32_t BACTV : 1;  /*!< [8..8] Bank Active Mode                                                   */
+            __IOM uint32_t PDOWN : 1;  /*!< [9..9] Power-Down Mode                                                    */
+            __IOM uint32_t RMODE : 1;  /*!< [10..10] Refresh Mode                                                     */
+            __IOM uint32_t RFSH  : 1;  /*!< [11..11] Refresh Control                                                  */
+            uint32_t             : 1;
+            __IOM uint32_t DEEP  : 1;  /*!< [13..13] Deep Power-Down Mode                                             */
+            uint32_t             : 2;
+            __IOM uint32_t A2COL : 2;  /*!< [17..16] Number of Bits of Column Address for Area 2                      */
+            uint32_t             : 1;
+            __IOM uint32_t A2ROW : 2;  /*!< [20..19] Number of Bits of Row Address for Area 2                         */
+            uint32_t             : 11;
+        } SDCR_b;
+    };
+    __IOM uint32_t RTCSR;              /*!< (@ 0x00000050) Refresh Timer Control/Status Register                      */
+    __IOM uint32_t RTCNT;              /*!< (@ 0x00000054) Refresh Timer Counter                                      */
+    __IOM uint32_t RTCOR;              /*!< (@ 0x00000058) Refresh Time Constant Register                             */
+    __IM uint32_t  RESERVED4;
+
+    union
+    {
+        __IOM uint32_t TOSCOR[6];       /*!< (@ 0x00000060) Timeout Cycle Constant Register [0..5]                     */
+
+        struct
+        {
+            __IOM uint32_t TOCNUM : 16; /*!< [15..0] Timeout Cycle Number                                              */
+            uint32_t              : 16;
+        } TOSCOR_b[6];
+    };
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        __IOM uint32_t TOSTR;            /*!< (@ 0x00000080) Timeout Status Register                                    */
+
+        struct
+        {
+            __IOM uint32_t CS0TOSTF : 1; /*!< [0..0] CS0 Space Timeout Status Flag                                      */
+            uint32_t                : 1;
+            __IOM uint32_t CS2TOSTF : 1; /*!< [2..2] CS2 Space Timeout Status Flag                                      */
+            __IOM uint32_t CS3TOSTF : 1; /*!< [3..3] CS3 Space Timeout Status Flag                                      */
+            uint32_t                : 1;
+            __IOM uint32_t CS5TOSTF : 1; /*!< [5..5] CS5 Space Timeout Status Flag                                      */
+            uint32_t                : 26;
+        } TOSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TOENR;           /*!< (@ 0x00000084) Timeout Enable Register                                    */
+
+        struct
+        {
+            __IOM uint32_t CS0TOEN : 1; /*!< [0..0] CS0 Space Timeout Detection Enable                                 */
+            uint32_t               : 1;
+            __IOM uint32_t CS2TOEN : 1; /*!< [2..2] CS2 Space Timeout Detection Enable                                 */
+            __IOM uint32_t CS3TOEN : 1; /*!< [3..3] CS3 Space Timeout Detection Enable                                 */
+            uint32_t               : 1;
+            __IOM uint32_t CS5TOEN : 1; /*!< [5..5] CS5 Space Timeout Detection Enable                                 */
+            uint32_t               : 26;
+        } TOENR_b;
+    };
+} R_BSC_Type;                           /*!< Size = 136 (0x88)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_XSPI0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief xSPI (R_XSPI0)
+ */
+
+typedef struct                         /*!< (@ 0x80220000) R_XSPI0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t WRAPCFG;        /*!< (@ 0x00000000) xSPI Wrapper Configuration Register                        */
+
+        struct
+        {
+            uint32_t                : 8;
+            __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0                                               */
+            uint32_t                : 11;
+            __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1                                              */
+            uint32_t                : 3;
+        } WRAPCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t COMCFG;         /*!< (@ 0x00000004) xSPI Common Configuration Register                         */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension                                */
+            __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension                                 */
+            uint32_t               : 14;
+        } COMCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BMCFG;           /*!< (@ 0x00000008) xSPI Bridge Map Configuration Register                     */
+
+        struct
+        {
+            __IOM uint32_t WRMD    : 1; /*!< [0..0] AHB Write Response mode                                            */
+            uint32_t               : 6;
+            __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode                                      */
+            __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size                                                 */
+            __IOM uint32_t PREEN   : 1; /*!< [16..16] Prefetch enable                                                  */
+            uint32_t               : 15;
+        } BMCFG_b;
+    };
+    __IM uint32_t          RESERVED;
+    __IOM R_XSPI0_CSa_Type CSa[2];     /*!< (@ 0x00000010) xSPI Command Map Configuration Register [0..1]             */
+    __IM uint32_t          RESERVED1[8];
+
+    union
+    {
+        __IOM uint32_t LIOCFGCS[2];        /*!< (@ 0x00000050) xSPI Link I/O Configuration Register CSn                   */
+
+        struct
+        {
+            __IOM uint32_t PRTMD     : 10; /*!< [9..0] Protocol mode                                                      */
+            __IOM uint32_t LATEMD    : 1;  /*!< [10..10] Latency mode                                                     */
+            __IOM uint32_t WRMSKMD   : 1;  /*!< [11..11] Write mask mode                                                  */
+            uint32_t                 : 4;
+            __IOM uint32_t CSMIN     : 4;  /*!< [19..16] CS minimum idle term                                             */
+            __IOM uint32_t CSASTEX   : 1;  /*!< [20..20] CS asserting extension                                           */
+            __IOM uint32_t CSNEGEX   : 1;  /*!< [21..21] CS negating extension                                            */
+            __IOM uint32_t SDRDRV    : 1;  /*!< [22..22] SDR driving timing                                               */
+            __IOM uint32_t SDRSMPMD  : 1;  /*!< [23..23] SDR Sampling mode                                                */
+            __IOM uint32_t SDRSMPSFT : 4;  /*!< [27..24] SDR Sampling window shift                                        */
+            __IOM uint32_t DDRSMPEX  : 4;  /*!< [31..28] DDR sampling window extend                                       */
+        } LIOCFGCS_b[2];
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t BMCTL0;         /*!< (@ 0x00000060) xSPI Bridge Map Control Register 0                         */
+
+        struct
+        {
+            __IOM uint32_t CS0ACC : 2; /*!< [1..0] AHB channel to slave0 memory area access enable                    */
+            __IOM uint32_t CS1ACC : 2; /*!< [3..2] AHB channel to slave1 memory area access enable                    */
+            uint32_t              : 28;
+        } BMCTL0_b;
+    };
+
+    union
+    {
+        __OM uint32_t BMCTL1;          /*!< (@ 0x00000064) xSPI Bridge Map Control Register 1                         */
+
+        struct
+        {
+            uint32_t              : 8;
+            __OM uint32_t MWRPUSH : 1; /*!< [8..8] Memory Write Data Push                                             */
+            uint32_t              : 1;
+            __OM uint32_t PBUFCLR : 1; /*!< [10..10] Prefetch Buffer clear                                            */
+            uint32_t              : 21;
+        } BMCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMCTL;             /*!< (@ 0x00000068) xSPI Command Map Control Register                          */
+
+        struct
+        {
+            __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code                                                */
+            __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code                                                */
+            __IOM uint32_t XIPEN     : 1; /*!< [16..16] XiP mode enable                                                  */
+            uint32_t                 : 15;
+        } CMCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CSSCTL;          /*!< (@ 0x0000006C) xSPI CS Size Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t CS0SIZE : 6; /*!< [5..0] CS0 (slave0) size                                                  */
+            uint32_t               : 2;
+            __IOM uint32_t CS1SIZE : 6; /*!< [13..8] CS1 (slave1) size                                                 */
+            uint32_t               : 18;
+        } CSSCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDCTL0;         /*!< (@ 0x00000070) xSPI Command Manual Control Register 0                     */
+
+        struct
+        {
+            __IOM uint32_t TRREQ  : 1; /*!< [0..0] Transaction request                                                */
+            __IOM uint32_t PERMD  : 1; /*!< [1..1] Periodic mode                                                      */
+            uint32_t              : 1;
+            __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
+            __IOM uint32_t TRNUM  : 2; /*!< [5..4] Transaction number                                                 */
+            uint32_t              : 10;
+            __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval                                    */
+            uint32_t              : 3;
+            __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat                                      */
+            uint32_t              : 4;
+        } CDCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDCTL1;          /*!< (@ 0x00000074) xSPI Command Manual Control Register 1                     */
+
+        struct
+        {
+            __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value                               */
+        } CDCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDCTL2;          /*!< (@ 0x00000078) xSPI Command Manual Control Register 2                     */
+
+        struct
+        {
+            __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value                                 */
+        } CDCTL2_b;
+    };
+    __IM uint32_t          RESERVED3;
+    __IOM R_XSPI0_BUF_Type BUF[4];      /*!< (@ 0x00000080) xSPI Command Manual Buf [0..3]                             */
+    __IM uint32_t          RESERVED4[16];
+
+    union
+    {
+        __IOM uint32_t LPCTL0;         /*!< (@ 0x00000100) xSPI Link Pattern Control Register 0                       */
+
+        struct
+        {
+            __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request                                                    */
+            uint32_t              : 2;
+            __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
+            __IOM uint32_t XDPIN  : 2; /*!< [5..4] XiP Disable pattern pin                                            */
+            uint32_t              : 10;
+            __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length                             */
+            uint32_t              : 2;
+            __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value                              */
+            __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length                             */
+            uint32_t              : 2;
+            __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value                              */
+        } LPCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LPCTL1;         /*!< (@ 0x00000104) xSPI Link Pattern Control Register 1                       */
+
+        struct
+        {
+            __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
+            __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat                                               */
+            uint32_t              : 2;
+            __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width                                               */
+            uint32_t              : 1;
+            __IOM uint32_t RSTSU  : 3; /*!< [14..12] Reset pattern data output setup time                             */
+            uint32_t              : 17;
+        } LPCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LIOCTL;         /*!< (@ 0x00000108) xSPI Link I/O Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t WPCS0  : 1; /*!< [0..0] WP drive for slave0                                                */
+            __IOM uint32_t WPCS1  : 1; /*!< [1..1] WP drive for slave1                                                */
+            uint32_t              : 14;
+            __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave0                                           */
+            __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave1                                           */
+            uint32_t              : 14;
+        } LIOCTL_b;
+    };
+    __IM uint32_t          RESERVED5[9];
+    __IOM R_XSPI0_CSb_Type CSb[2];     /*!< (@ 0x00000130) xSPI Command Calibration Control register [0..1]           */
+    __IM uint32_t          RESERVED6[4];
+
+    union
+    {
+        __IM uint32_t VERSTT;          /*!< (@ 0x00000180) xSPI Version Register                                      */
+
+        struct
+        {
+            __IM uint32_t VER : 32;    /*!< [31..0] Version                                                           */
+        } VERSTT_b;
+    };
+
+    union
+    {
+        __IM uint32_t COMSTT;          /*!< (@ 0x00000184) xSPI Common Status Register                                */
+
+        struct
+        {
+            __IM uint32_t MEMACC  : 1; /*!< [0..0] Memory access ongoing                                              */
+            uint32_t              : 3;
+            __IM uint32_t PBUFNE  : 1; /*!< [4..4] Prefetch Buffer Not Empty                                          */
+            uint32_t              : 1;
+            __IM uint32_t WRBUFNE : 1; /*!< [6..6] Write Buffer Not Empty                                             */
+            uint32_t              : 9;
+            __IM uint32_t ECSCS0  : 1; /*!< [16..16] ECS monitor for slave0                                           */
+            __IM uint32_t INTCS0  : 1; /*!< [17..17] INT monitor for slave0                                           */
+            __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0                                          */
+            uint32_t              : 1;
+            __IM uint32_t ECSCS1  : 1; /*!< [20..20] ECS monitor for slave1                                           */
+            __IM uint32_t INTCS1  : 1; /*!< [21..21] INT monitor for slave1                                           */
+            __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1                                          */
+            uint32_t              : 9;
+        } COMSTT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CASTTCS[2];      /*!< (@ 0x00000188) xSPI Calibration Status Register CSn                       */
+
+        struct
+        {
+            __IM uint32_t CASUC : 32;  /*!< [31..0] Calibration Success                                               */
+        } CASTTCS_b[2];
+    };
+
+    union
+    {
+        __IM uint32_t INTS;              /*!< (@ 0x00000190) xSPI Interrupt Status Register                             */
+
+        struct
+        {
+            __IM uint32_t CMDCMP    : 1; /*!< [0..0] Command Completed                                                  */
+            __IM uint32_t PATCMP    : 1; /*!< [1..1] Pattern Completed                                                  */
+            __IM uint32_t INICMP    : 1; /*!< [2..2] Initial Sequence Completed                                         */
+            __IM uint32_t PERTO     : 1; /*!< [3..3] Periodic transaction timeout                                       */
+            __IM uint32_t DSTOCS0   : 1; /*!< [4..4] DS timeout for slave0                                              */
+            __IM uint32_t DSTOCS1   : 1; /*!< [5..5] DS timeout for slave1                                              */
+            uint32_t                : 2;
+            __IM uint32_t ECSCS0    : 1; /*!< [8..8] ECC error detection for slave0                                     */
+            __IM uint32_t ECSCS1    : 1; /*!< [9..9] ECC error detection for slave1                                     */
+            uint32_t                : 2;
+            __IM uint32_t INTCS0    : 1; /*!< [12..12] Interrupt detection for slave0                                   */
+            __IM uint32_t INTCS1    : 1; /*!< [13..13] Interrupt detection for slave1                                   */
+            uint32_t                : 2;
+            __IM uint32_t BRGOF     : 1; /*!< [16..16] Bridge Buffer overflow                                           */
+            uint32_t                : 1;
+            __IM uint32_t BRGUF     : 1; /*!< [18..18] Bridge Buffer underflow                                          */
+            uint32_t                : 1;
+            __IM uint32_t BUSERR    : 1; /*!< [20..20] AHB bus error                                                    */
+            uint32_t                : 7;
+            __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0                                    */
+            __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1                                    */
+            __IM uint32_t CASUCCS0  : 1; /*!< [30..30] Calibration success for slave0                                   */
+            __IM uint32_t CASUCCS1  : 1; /*!< [31..31] Calibration success for slave1                                   */
+        } INTS_b;
+    };
+
+    union
+    {
+        __OM uint32_t INTC;               /*!< (@ 0x00000194) xSPI Interrupt Clear Register                              */
+
+        struct
+        {
+            __OM uint32_t CMDCMPC    : 1; /*!< [0..0] Command Completed interrupt clear                                  */
+            __OM uint32_t PATCMPC    : 1; /*!< [1..1] Pattern Completed interrupt clear                                  */
+            __OM uint32_t INICMPC    : 1; /*!< [2..2] Initial Sequence Completed interrupt clear                         */
+            __OM uint32_t PERTOC     : 1; /*!< [3..3] Periodic transaction timeout interrupt clear                       */
+            __OM uint32_t DSTOCS0C   : 1; /*!< [4..4] DS timeout for slave0 interrupt clear                              */
+            __OM uint32_t DSTOCS1C   : 1; /*!< [5..5] DS timeout for slave1 interrupt clear                              */
+            uint32_t                 : 2;
+            __OM uint32_t ECSCS0C    : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear                     */
+            __OM uint32_t ECSCS1C    : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear                     */
+            uint32_t                 : 2;
+            __OM uint32_t INTCS0C    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear                   */
+            __OM uint32_t INTCS1C    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear                   */
+            uint32_t                 : 2;
+            __OM uint32_t BRGOFC     : 1; /*!< [16..16] Bridge Buffer overflow interrupt clear                           */
+            uint32_t                 : 1;
+            __OM uint32_t BRGUFC     : 1; /*!< [18..18] Bridge Buffer underflow interrupt clear                          */
+            uint32_t                 : 1;
+            __OM uint32_t BUSERRC    : 1; /*!< [20..20] AHB bus error interrupt clear                                    */
+            uint32_t                 : 7;
+            __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear                    */
+            __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear                    */
+            __OM uint32_t CASUCCS0C  : 1; /*!< [30..30] Calibration success for slave0 interrupt clear                   */
+            __OM uint32_t CASUCCS1C  : 1; /*!< [31..31] Calibration success for slave1 interrupt clear                   */
+        } INTC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INTE;               /*!< (@ 0x00000198) xSPI Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint32_t CMDCMPE    : 1; /*!< [0..0] Command Completed interrupt enable                                 */
+            __IOM uint32_t PATCMPE    : 1; /*!< [1..1] Pattern Completed interrupt enable                                 */
+            __IOM uint32_t INICMPE    : 1; /*!< [2..2] Initial Sequence Completed interrupt enable                        */
+            __IOM uint32_t PERTOE     : 1; /*!< [3..3] Periodic transaction timeout interrupt enable                      */
+            __IOM uint32_t DSTOCS0E   : 1; /*!< [4..4] DS timeout for slave0 interrupt enable                             */
+            __IOM uint32_t DSTOCS1E   : 1; /*!< [5..5] DS timeout for slave1 interrupt enable                             */
+            uint32_t                  : 2;
+            __IOM uint32_t ECSCS0E    : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable                    */
+            __IOM uint32_t ECSCS1E    : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable                    */
+            uint32_t                  : 2;
+            __IOM uint32_t INTCS0E    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable                  */
+            __IOM uint32_t INTCS1E    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable                  */
+            uint32_t                  : 2;
+            __IOM uint32_t BRGOFE     : 1; /*!< [16..16] Bridge Buffer overflow interrupt enable                          */
+            uint32_t                  : 1;
+            __IOM uint32_t BRGUFE     : 1; /*!< [18..18] Bridge Buffer underflow interrupt enable                         */
+            uint32_t                  : 1;
+            __IOM uint32_t BUSERRE    : 1; /*!< [20..20] AHB bus error interrupt enable                                   */
+            uint32_t                  : 7;
+            __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable                   */
+            __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable                   */
+            __IOM uint32_t CASUCCS0E  : 1; /*!< [30..30] Calibration success for slave0 interrupt enable                  */
+            __IOM uint32_t CASUCCS1E  : 1; /*!< [31..31] Calibration success for slave1 interrupt enable                  */
+        } INTE_b;
+    };
+} R_XSPI0_Type;                            /*!< Size = 412 (0x19c)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MBXSEM                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Mailbox and Semaphore (R_MBXSEM)
+ */
+
+typedef struct                         /*!< (@ 0x80240000) R_MBXSEM Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t SEM[8];         /*!< (@ 0x00000000) Semaphore Register [0..7]                                  */
+
+        struct
+        {
+            __IOM uint32_t SEM : 1;    /*!< [0..0] Semaphore bit                                                      */
+            uint32_t           : 31;
+        } SEM_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t SEMRCEN;          /*!< (@ 0x00000020) Semaphore Read Clear Enable Register                       */
+
+        struct
+        {
+            __IOM uint32_t SEMRCEN0 : 1; /*!< [0..0] SEMRCEN0                                                           */
+            __IOM uint32_t SEMRCEN1 : 1; /*!< [1..1] SEMRCEN1                                                           */
+            __IOM uint32_t SEMRCEN2 : 1; /*!< [2..2] SEMRCEN2                                                           */
+            __IOM uint32_t SEMRCEN3 : 1; /*!< [3..3] SEMRCEN3                                                           */
+            __IOM uint32_t SEMRCEN4 : 1; /*!< [4..4] SEMRCEN4                                                           */
+            __IOM uint32_t SEMRCEN5 : 1; /*!< [5..5] SEMRCEN5                                                           */
+            __IOM uint32_t SEMRCEN6 : 1; /*!< [6..6] SEMRCEN6                                                           */
+            __IOM uint32_t SEMRCEN7 : 1; /*!< [7..7] SEMRCEN7                                                           */
+            uint32_t                : 24;
+        } SEMRCEN_b;
+    };
+    __IM uint32_t RESERVED[7];
+
+    union
+    {
+        __IM uint32_t MBXH2C[4];       /*!< (@ 0x00000040) Host to CR52 Mailbox Register [0..3]                       */
+
+        struct
+        {
+            __IM uint32_t MBX : 32;    /*!< [31..0] MBX                                                               */
+        } MBXH2C_b[4];
+    };
+
+    union
+    {
+        __IM uint32_t MBXISETH2C;        /*!< (@ 0x00000050) Host to CR52 Mailbox Interrupt Set Register                */
+
+        struct
+        {
+            __IM uint32_t MBX_INT0S : 1; /*!< [0..0] Generates or indicates MBX_INT0 interrupt of mailbox
+                                          *   from external host CPU to internal Cortex-R52.                            */
+            __IM uint32_t MBX_INT1S : 1; /*!< [1..1] Generates or indicates MBX_INT1 interrupt of mailbox
+                                          *   from external host CPU to internal Cortex-R52.                            */
+            __IM uint32_t MBX_INT2S : 1; /*!< [2..2] Generates or indicates MBX_INT2 interrupt of mailbox
+                                          *   from external host CPU to internal Cortex-R52.                            */
+            __IM uint32_t MBX_INT3S : 1; /*!< [3..3] Generates or indicates MBX_INT3 interrupt of mailbox
+                                          *   from external host CPU to internal Cortex-R52.                            */
+            uint32_t : 28;
+        } MBXISETH2C_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRH2C;        /*!< (@ 0x00000054) Host to CR52 Mailbox Interrupt Clear Register              */
+
+        struct
+        {
+            __IOM uint32_t MBX_INT0C : 1; /*!< [0..0] Clears or indicates MBX_INT0 interrupt of mailbox from
+                                           *   external host CPU to internal Cortex-R52.                                 */
+            __IOM uint32_t MBX_INT1C : 1; /*!< [1..1] Clears or indicates MBX_INT1 interrupt of mailbox from
+                                           *   external host CPU to internal Cortex-R52.                                 */
+            __IOM uint32_t MBX_INT2C : 1; /*!< [2..2] Clears or indicates MBX_INT2 interrupt of mailbox from
+                                           *   external host CPU to internal Cortex-R52.                                 */
+            __IOM uint32_t MBX_INT3C : 1; /*!< [3..3] Clears or indicates MBX_INT3 interrupt of mailbox from
+                                           *   external host CPU to internal Cortex-R52.                                 */
+            uint32_t : 28;
+        } MBXICLRH2C_b;
+    };
+    __IM uint32_t RESERVED1[10];
+
+    union
+    {
+        __IOM uint32_t MBXC2H[4];      /*!< (@ 0x00000080) CR52 to Host Mailbox Register [0..3]                       */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXC2H_b[4];
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETC2H;         /*!< (@ 0x00000090) CR52 to Host Mailbox Interrupt Set Register                */
+
+        struct
+        {
+            __IOM uint32_t MBX_HINT0S : 1; /*!< [0..0] Generates or indicates MBX_HINT0 interrupt of mailbox
+                                            *   from internal Cortex-R52 to external host CPU.                            */
+            __IOM uint32_t MBX_HINT1S : 1; /*!< [1..1] Generates or indicates MBX_HINT1 interrupt of mailbox
+                                            *   from internal Cortex-R52 to external host CPU.                            */
+            __IOM uint32_t MBX_HINT2S : 1; /*!< [2..2] Generates or indicates MBX_HINT2 interrupt of mailbox
+                                            *   from internal Cortex-R52 to external host CPU.                            */
+            __IOM uint32_t MBX_HINT3S : 1; /*!< [3..3] Generates or indicates MBX_HINT3 interrupt of mailbox
+                                            *   from internal Cortex-R52 to external host CPU.                            */
+            uint32_t : 28;
+        } MBXISETC2H_b;
+    };
+
+    union
+    {
+        __IM uint32_t MBXICLRC2H;         /*!< (@ 0x00000094) CR52 to Host Mailbox Interrupt Clear Register              */
+
+        struct
+        {
+            __IM uint32_t MBX_HINT0C : 1; /*!< [0..0] Clears or indicates MBX_HINT0 interrupt of mailbox from
+                                           *   internal Cortex-R52 to external host CPU.                                 */
+            __IM uint32_t MBX_HINT1C : 1; /*!< [1..1] Clears or indicates MBX_HINT1 interrupt of mailbox from
+                                           *   internal Cortex-R52 to external host CPU.                                 */
+            __IM uint32_t MBX_HINT2C : 1; /*!< [2..2] Clears or indicates MBX_HINT2 interrupt of mailbox from
+                                           *   internal Cortex-R52 to external host CPU.                                 */
+            __IM uint32_t MBX_HINT3C : 1; /*!< [3..3] Clears or indicates MBX_HINT3 interrupt of mailbox from
+                                           *   internal Cortex-R52 to external host CPU.                                 */
+            uint32_t : 28;
+        } MBXICLRC2H_b;
+    };
+} R_MBXSEM_Type;                          /*!< Size = 152 (0x98)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SHOSTIF                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Host Interface (R_SHOSTIF)
+ */
+
+typedef struct                         /*!< (@ 0x80241000) R_SHOSTIF Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t CTRLR0;         /*!< (@ 0x00000000) Control Register 0                                         */
+
+        struct
+        {
+            uint32_t             : 8;
+            __IOM uint32_t SCPH  : 1;  /*!< [8..8] Serial Clock Phase                                                 */
+            __IOM uint32_t SCPOL : 1;  /*!< [9..9] Serial Clock Polarity                                              */
+            uint32_t             : 22;
+        } CTRLR0_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t ENR;            /*!< (@ 0x00000008) Enable Register                                            */
+
+        struct
+        {
+            __IOM uint32_t ENABLE : 1; /*!< [0..0] SHOSTIF Enable                                                     */
+            uint32_t              : 31;
+        } ENR_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t RXFBTR;         /*!< (@ 0x00000014) Receive FIFO Burst Threshold Register                      */
+
+        struct
+        {
+            __IOM uint32_t RXFBTL : 6; /*!< [5..0] Receive FIFO Burst Threshold                                       */
+            uint32_t              : 26;
+        } RXFBTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TXFTLR;         /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register                     */
+
+        struct
+        {
+            __IOM uint32_t TFT : 6;    /*!< [5..0] Transmit FIFO Threshold                                            */
+            uint32_t           : 26;
+        } TXFTLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RXFTLR;         /*!< (@ 0x0000001C) Receive FIFO Threshold Level Register                      */
+
+        struct
+        {
+            __IOM uint32_t RFT : 6;    /*!< [5..0] Receive FIFO Threshold                                             */
+            uint32_t           : 26;
+        } RXFTLR_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IM uint32_t SR;              /*!< (@ 0x00000028) Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t BUSY : 1;    /*!< [0..0] Busy Flag                                                          */
+            uint32_t           : 31;
+        } SR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IMR;            /*!< (@ 0x0000002C) Interrupt Mask Register                                    */
+
+        struct
+        {
+            __IOM uint32_t TXEIM  : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask                                 */
+            uint32_t              : 2;
+            __IOM uint32_t RXOIM  : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask                               */
+            __IOM uint32_t RXFIM  : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask                                   */
+            uint32_t              : 2;
+            __IOM uint32_t TXUIM  : 1; /*!< [7..7] Transmit FIFO Underflow Mask                                       */
+            __IOM uint32_t AHBEM  : 1; /*!< [8..8] AHB Error Interrupt Mask                                           */
+            __IOM uint32_t SPIMEM : 1; /*!< [9..9] SPI Master Error Interrupt Mask                                    */
+            uint32_t              : 22;
+        } IMR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ISR;             /*!< (@ 0x00000030) Interrupt Status Register                                  */
+
+        struct
+        {
+            __IM uint32_t TXEIS  : 1;  /*!< [0..0] Transmit FIFO Empty Interrupt Status                               */
+            uint32_t             : 2;
+            __IM uint32_t RXOIS  : 1;  /*!< [3..3] Receive FIFO Overflow Interrupt Status                             */
+            __IM uint32_t RXFIS  : 1;  /*!< [4..4] Receive FIFO Full Interrupt Status                                 */
+            uint32_t             : 2;
+            __IM uint32_t TXUIS  : 1;  /*!< [7..7] Transmit FIFO Underflow Status                                     */
+            __IM uint32_t AHBES  : 1;  /*!< [8..8] AHB Error Interrupt Status                                         */
+            __IM uint32_t SPIMES : 1;  /*!< [9..9] SPI Master Error Interrupt Status                                  */
+            uint32_t             : 22;
+        } ISR_b;
+    };
+
+    union
+    {
+        __IM uint32_t RISR;            /*!< (@ 0x00000034) Raw Interrupt Status Register                              */
+
+        struct
+        {
+            __IM uint32_t TXEIR  : 1;  /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status                           */
+            uint32_t             : 2;
+            __IM uint32_t RXOIR  : 1;  /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status                         */
+            __IM uint32_t RXFIR  : 1;  /*!< [4..4] Receive FIFO Full Raw Interrupt Status                             */
+            uint32_t             : 2;
+            __IM uint32_t TXUIR  : 1;  /*!< [7..7] Transmit FIFO Underflow Raw Interrupt Status                       */
+            __IM uint32_t AHBER  : 1;  /*!< [8..8] AHB Error Raw Interrupt Status                                     */
+            __IM uint32_t SPIMER : 1;  /*!< [9..9] SPI Master Error Raw Interrupt Status                              */
+            uint32_t             : 22;
+        } RISR_b;
+    };
+
+    union
+    {
+        __IM uint32_t TXUICR;          /*!< (@ 0x00000038) Transmit FIFO Underflow Interrupt Clear Register           */
+
+        struct
+        {
+            __IM uint32_t TXUICR : 1;  /*!< [0..0] Clear Transmit FIFO Underflow Interrupt                            */
+            uint32_t             : 31;
+        } TXUICR_b;
+    };
+
+    union
+    {
+        __IM uint32_t RXOICR;          /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register             */
+
+        struct
+        {
+            __IM uint32_t RXOICR : 1;  /*!< [0..0] Clear Receive FIFO Overflow Interrupt                              */
+            uint32_t             : 31;
+        } RXOICR_b;
+    };
+
+    union
+    {
+        __IM uint32_t SPIMECR;         /*!< (@ 0x00000040) SPI Master Interrupt Clear Register                        */
+
+        struct
+        {
+            __IM uint32_t SPIMECR : 1; /*!< [0..0] Clear SPI Master Error interrupt                                   */
+            uint32_t              : 31;
+        } SPIMECR_b;
+    };
+
+    union
+    {
+        __IM uint32_t AHBECR;          /*!< (@ 0x00000044) AHB Error Clear Register                                   */
+
+        struct
+        {
+            __IM uint32_t AHBECR : 1;  /*!< [0..0] Clear AHB Error Interrupt                                          */
+            uint32_t             : 31;
+        } AHBECR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ICR;             /*!< (@ 0x00000048) Interrupt Clear Register                                   */
+
+        struct
+        {
+            __IM uint32_t ICR : 1;     /*!< [0..0] Clear Interrupts                                                   */
+            uint32_t          : 31;
+        } ICR_b;
+    };
+} R_SHOSTIF_Type;                      /*!< Size = 76 (0x4c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_PHOSTIF                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Parallel Host Interface (R_PHOSTIF)
+ */
+
+typedef struct                          /*!< (@ 0x80242000) R_PHOSTIF Structure                                        */
+{
+    union
+    {
+        __IOM uint16_t HIFBCC;          /*!< (@ 0x00000000) HOSTIF Bus Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t RBUFON0 : 1; /*!< [0..0] RBUFON0                                                            */
+            __IOM uint16_t RBUFON1 : 1; /*!< [1..1] RBUFON1                                                            */
+            __IOM uint16_t RBUFON2 : 1; /*!< [2..2] RBUFON2                                                            */
+            __IOM uint16_t RBUFON3 : 1; /*!< [3..3] RBUFON3                                                            */
+            __IOM uint16_t RBUFON4 : 1; /*!< [4..4] RBUFON4                                                            */
+            __IOM uint16_t RBUFON5 : 1; /*!< [5..5] RBUFON5                                                            */
+            uint16_t               : 2;
+            __IOM uint16_t RBUFONX : 1; /*!< [8..8] RBUFONX                                                            */
+            uint16_t               : 3;
+            __IOM uint16_t BSTON   : 1; /*!< [12..12] BSTON                                                            */
+            __IOM uint16_t WRPON   : 1; /*!< [13..13] WRPON                                                            */
+            uint16_t               : 2;
+        } HIFBCC_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t HIFBTC;         /*!< (@ 0x00000004) HOSTIF Timing Control Register                             */
+
+        struct
+        {
+            __IOM uint16_t WRSTD : 3;  /*!< [2..0] Specifies the timing for detecting the start of write
+                                        *   operation by the HWRSTB# signal.                                          */
+            uint16_t             : 1;
+            __IOM uint16_t RDSTD : 2;  /*!< [5..4] Specifies the timing for detecting the start of read
+                                        *   operation by the HRD# signal.                                             */
+            uint16_t             : 2;
+            __IOM uint16_t PASTD : 3;  /*!< [10..8] PASTD                                                             */
+            uint16_t             : 1;
+            __IOM uint16_t RDDTS : 2;  /*!< [13..12] RDDTS                                                            */
+            uint16_t             : 2;
+        } HIFBTC_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t HIFPRC;          /*!< (@ 0x00000008) HOSTIF Page ROM Control Register                           */
+
+        struct
+        {
+            __IOM uint16_t PAGEON0 : 1; /*!< [0..0] PAGEON0                                                            */
+            __IOM uint16_t PAGEON1 : 1; /*!< [1..1] PAGEON1                                                            */
+            __IOM uint16_t PAGEON2 : 1; /*!< [2..2] PAGEON2                                                            */
+            __IOM uint16_t PAGEON3 : 1; /*!< [3..3] PAGEON3                                                            */
+            __IOM uint16_t PAGEON4 : 1; /*!< [4..4] PAGEON4                                                            */
+            __IOM uint16_t PAGEON5 : 1; /*!< [5..5] PAGEON5                                                            */
+            uint16_t               : 2;
+            __IOM uint16_t PAGEONX : 1; /*!< [8..8] PAGEONX                                                            */
+            uint16_t               : 3;
+            __IOM uint16_t PAGESZ  : 1; /*!< [12..12] PAGESZ                                                           */
+            uint16_t               : 3;
+        } HIFPRC_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint16_t HIFIRC;         /*!< (@ 0x0000000C) HOSTIF Interrupt Request Control Register                  */
+
+        struct
+        {
+            __IOM uint16_t ERRRSP : 1; /*!< [0..0] This bit is set to 1 on reception of an error response
+                                        *   from internal slave modules.                                              */
+            uint16_t : 15;
+        } HIFIRC_b;
+    };
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IM uint32_t HIFECR0;          /*!< (@ 0x00000010) HOSTIF Error Source Register 0                             */
+
+        struct
+        {
+            __IM uint32_t ERRADDR : 32; /*!< [31..0] ERRADDR                                                           */
+        } HIFECR0_b;
+    };
+
+    union
+    {
+        __IM uint16_t HIFECR1;         /*!< (@ 0x00000014) HOSTIF Error Source Register 1                             */
+
+        struct
+        {
+            __IM uint16_t ERRSZ : 3;   /*!< [2..0] ERRSZ                                                              */
+            __IM uint16_t ERRWR : 1;   /*!< [3..3] ERRWR                                                              */
+            uint16_t            : 12;
+        } HIFECR1_b;
+    };
+    __IM uint16_t RESERVED4;
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        __IOM uint16_t HIFMON1;        /*!< (@ 0x00000020) HOSTIF Monitor Register 1                                  */
+
+        struct
+        {
+            __IOM uint16_t HIFRDY : 1; /*!< [0..0] HIFRDY                                                             */
+            __IM uint16_t  BUSSEL : 1; /*!< [1..1] BUSSEL                                                             */
+            uint16_t              : 1;
+            __IM uint16_t HIFSYNC : 1; /*!< [3..3] HIFSYNC                                                            */
+            uint16_t              : 12;
+        } HIFMON1_b;
+    };
+    __IM uint16_t RESERVED6;
+
+    union
+    {
+        __IM uint16_t HIFMON2;         /*!< (@ 0x00000024) HOSTIF Monitor Register 2                                  */
+
+        struct
+        {
+            __IM uint16_t HIFBCC : 1;  /*!< [0..0] HIFBCC                                                             */
+            __IM uint16_t HIFBTC : 1;  /*!< [1..1] HIFBTC                                                             */
+            __IM uint16_t HIFPRC : 1;  /*!< [2..2] HIFPRC                                                             */
+            __IM uint16_t HIFIRC : 1;  /*!< [3..3] HIFIRC                                                             */
+            __IM uint16_t HIFXAL : 1;  /*!< [4..4] HIFXAL                                                             */
+            __IM uint16_t HIFXAH : 1;  /*!< [5..5] HIFXAH                                                             */
+            uint16_t             : 10;
+        } HIFMON2_b;
+    };
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IM uint16_t HIFMON3;         /*!< (@ 0x00000028) HOSTIF Monitor Register 3                                  */
+
+        struct
+        {
+            __IM uint16_t HIFEXT0 : 1; /*!< [0..0] HIFEXT0                                                            */
+            __IM uint16_t HIFEXT1 : 1; /*!< [1..1] HIFEXT1                                                            */
+            uint16_t              : 14;
+        } HIFMON3_b;
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t HIFXAL;         /*!< (@ 0x00000030) HOSTIF Specified Area Lower-limit Register                 */
+
+        struct
+        {
+            __IOM uint16_t XADDRL : 9; /*!< [8..0] Specifies the lower-limit address of the specified area
+                                        *   to be set in the external bus address space.                              */
+            uint16_t : 7;
+        } HIFXAL_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t HIFXAH;         /*!< (@ 0x00000034) HOSTIF Specified Area Upper-limit Register                 */
+
+        struct
+        {
+            __IOM uint16_t XADDRH : 9; /*!< [8..0] Specifies the upper-limit address of the specified area
+                                        *   to be set in the external bus address space.                              */
+            uint16_t : 7;
+        } HIFXAH_b;
+    };
+    __IM uint16_t RESERVED11;
+    __IM uint32_t RESERVED12[18];
+
+    union
+    {
+        __IOM uint16_t HIFEXT0;        /*!< (@ 0x00000080) HOSTIF Synchronous Burst Transfer Control Register
+                                        *                  0                                                          */
+
+        struct
+        {
+            __IOM uint16_t KESSBI : 1; /*!< [0..0] KESSBI                                                             */
+            uint16_t              : 1;
+            __IOM uint16_t KESDTI : 1; /*!< [2..2] KESDTI                                                             */
+            __IOM uint16_t KESAVI : 1; /*!< [3..3] KESAVI                                                             */
+            __IOM uint16_t KESDTO : 1; /*!< [4..4] KESDTO                                                             */
+            __IOM uint16_t KESWTO : 1; /*!< [5..5] KESWTO                                                             */
+            uint16_t              : 3;
+            __IOM uint16_t CNDWEO : 1; /*!< [9..9] CNDWEO                                                             */
+            uint16_t              : 5;
+            __IOM uint16_t MODTRN : 1; /*!< [15..15] MODTRN                                                           */
+        } HIFEXT0_b;
+    };
+    __IM uint16_t RESERVED13;
+
+    union
+    {
+        __IOM uint16_t HIFEXT1;        /*!< (@ 0x00000084) HOSTIF Synchronous Burst Transfer Control Register
+                                        *                  1                                                          */
+
+        struct
+        {
+            __IOM uint16_t DLYWA : 4;  /*!< [3..0] Minimum time from the last input of the Low level on
+                                        *   the HBS# pin to the point where write data is received.
+                                        *   (twc)DLYWA[3:0]CNDWEO = 0CNDWEO = 0HWRSTB# = 0HWRSTB# =
+                                        *   1HWRSTB# = 0HWRSTB# = 10x034450x134450x234450x344450x455550x566660x677770
+                                        *   788880x899990x9101010100xA111111110xB121212120xC131313130xD141414140xE151
+                                        *   15150xF16161616                                                           */
+            uint16_t             : 4;
+            __IOM uint16_t DLYRA : 4;  /*!< [11..8] Minimum time from the last input of the Low level on
+                                        *   the HBS# pin to the point where read data can be acquired.
+                                        *   (trc)DLYRA[3:0]CNDWEO = 0CNDWEO = 10x0450x1450x2550x3660x4770x5880x6990x7
+                                        *   0100x811110x912120xA13130xB14140xC15150xD16160xE17170xF1818               */
+            uint16_t : 4;
+        } HIFEXT1_b;
+    };
+    __IM uint16_t RESERVED14;
+} R_PHOSTIF_Type;                      /*!< Size = 136 (0x88)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSC_NS                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System Control for Non-safety region (R_SYSC_NS)
+ */
+
+typedef struct                               /*!< (@ 0x80280000) R_SYSC_NS Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t SCKCR;                /*!< (@ 0x00000000) System Clock Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t FSELXSPI0 : 3;    /*!< [2..0] Set the frequency of the clock provided to xSPI Unit
+                                              *   0 in combination with bit 6 (DIVSELXSPI0). The combination
+                                              *   is shown below.                                                           */
+            uint32_t                   : 3;
+            __IOM uint32_t DIVSELXSPI0 : 1;  /*!< [6..6] Select the base clock to generate serial clock for xSPI
+                                              *   Unit 0                                                                    */
+            uint32_t                 : 1;
+            __IOM uint32_t FSELXSPI1 : 3;    /*!< [10..8] Set the frequency of the clock provided to xSPI Unit
+                                              *   1 in combination with bit 14 (DIVSELXSPI1).                               */
+            uint32_t                   : 3;
+            __IOM uint32_t DIVSELXSPI1 : 1;  /*!< [14..14] Select the base clock to generate serial clock for
+                                              *   xSPI Unit 1                                                               */
+            uint32_t            : 1;
+            __IOM uint32_t CKIO : 3;         /*!< [18..16] Set the frequency of the external bus clock (CKIO)
+                                              *   and the clock supplied to BSC in combination with the DIVSELSUB
+                                              *   in the SCKCR2 register. The combination is shown below.                   */
+            uint32_t                 : 1;
+            __IOM uint32_t FSELCANFD : 1;    /*!< [20..20] Select the frequency of the clock supplied to CANFD              */
+            __IOM uint32_t PHYSEL    : 1;    /*!< [21..21] Select the Ethernet PHY reference clock output (ETHn_REFCLK,
+                                              *   n = 0 to 2)                                                               */
+            __IOM uint32_t CLMASEL : 1;      /*!< [22..22] Select alternative clock when main clock abnormal oscillation
+                                              *   is detected in CLMA3                                                      */
+            uint32_t                    : 1;
+            __IOM uint32_t SPI0ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SPI0                                                       */
+            __IOM uint32_t SPI1ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SPI1                                                       */
+            __IOM uint32_t SPI2ASYNCSEL : 1; /*!< [26..26] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SPI2                                                       */
+            __IOM uint32_t SCI0ASYNCSEL : 1; /*!< [27..27] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SCI0                                                       */
+            __IOM uint32_t SCI1ASYNCSEL : 1; /*!< [28..28] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SCI1                                                       */
+            __IOM uint32_t SCI2ASYNCSEL : 1; /*!< [29..29] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SCI2                                                       */
+            __IOM uint32_t SCI3ASYNCSEL : 1; /*!< [30..30] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SCI3                                                       */
+            __IOM uint32_t SCI4ASYNCSEL : 1; /*!< [31..31] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SCI4                                                       */
+        } SCKCR_b;
+    };
+    __IM uint32_t RESERVED[127];
+
+    union
+    {
+        __IOM uint32_t RSTSR0;         /*!< (@ 0x00000200) Reset Status Register 0                                    */
+
+        struct
+        {
+            uint32_t             : 1;
+            __IOM uint32_t TRF   : 1;  /*!< [1..1] RES# Pin Reset Detect Flag                                         */
+            __IOM uint32_t ERRF  : 1;  /*!< [2..2] Error Reset Detect Flag                                            */
+            __IOM uint32_t SWRSF : 1;  /*!< [3..3] System Software Reset Detect Flag                                  */
+            __IOM uint32_t SWR0F : 1;  /*!< [4..4] CPU0 Software Reset Detect Flag                                    */
+            uint32_t             : 27;
+        } RSTSR0_b;
+    };
+    __IM uint32_t RESERVED1[15];
+
+    union
+    {
+        __IOM uint32_t MRCTLA;         /*!< (@ 0x00000240) Module Reset Control Register A                            */
+
+        struct
+        {
+            uint32_t                : 4;
+            __IOM uint32_t MRCTLA04 : 1; /*!< [4..4] xSPI Unit 0 Reset Control                                          */
+            __IOM uint32_t MRCTLA05 : 1; /*!< [5..5] xSPI Unit 1 Reset Control                                          */
+            uint32_t                : 26;
+        } MRCTLA_b;
+    };
+    __IM uint32_t RESERVED2[3];
+
+    union
+    {
+        __IOM uint32_t MRCTLE;           /*!< (@ 0x00000250) Module Reset Control Register E                            */
+
+        struct
+        {
+            __IOM uint32_t MRCTLE00 : 1; /*!< [0..0] GMAC (PCLKH clock domain) Reset Control                            */
+            __IOM uint32_t MRCTLE01 : 1; /*!< [1..1] GMAC (PCLKM clock domain) Reset Control                            */
+            __IOM uint32_t MRCTLE02 : 1; /*!< [2..2] ETHSW Reset Control                                                */
+            __IOM uint32_t MRCTLE03 : 1; /*!< [3..3] ESC (Bus clock domain) Reset Control                               */
+            __IOM uint32_t MRCTLE04 : 1; /*!< [4..4] ESC (IP clock domain) Reset Control                                */
+            __IOM uint32_t MRCTLE05 : 1; /*!< [5..5] Ethernet Subsystem Register Reset Control                          */
+            __IOM uint32_t MRCTLE06 : 1; /*!< [6..6] MII Converter Reset Control                                        */
+            uint32_t                : 25;
+        } MRCTLE_b;
+    };
+    __IM uint32_t RESERVED3[43];
+
+    union
+    {
+        __IOM uint32_t MSTPCRA;           /*!< (@ 0x00000300) Module Stop Control Register A                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRA00 : 1; /*!< [0..0] BSC Module Stop                                                    */
+            uint32_t                 : 3;
+            __IOM uint32_t MSTPCRA04 : 1; /*!< [4..4] xSPI Unit 0 Module Stop                                            */
+            __IOM uint32_t MSTPCRA05 : 1; /*!< [5..5] xSPI Unit 1 Module Stop                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t MSTPCRA08 : 1; /*!< [8..8] SCI Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRA09 : 1; /*!< [9..9] SCI Unit 1 Module Stop                                             */
+            __IOM uint32_t MSTPCRA10 : 1; /*!< [10..10] SCI Unit 2 Module Stop                                           */
+            __IOM uint32_t MSTPCRA11 : 1; /*!< [11..11] SCI Unit 3 Module Stop                                           */
+            __IOM uint32_t MSTPCRA12 : 1; /*!< [12..12] SCI Unit 4 Module Stop                                           */
+            uint32_t                 : 19;
+        } MSTPCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRB;           /*!< (@ 0x00000304) Module Stop Control Register B                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRB00 : 1; /*!< [0..0] IIC Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRB01 : 1; /*!< [1..1] IIC Unit 1 Module Stop                                             */
+            uint32_t                 : 2;
+            __IOM uint32_t MSTPCRB04 : 1; /*!< [4..4] SPI Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRB05 : 1; /*!< [5..5] SPI Unit 1 Module Stop                                             */
+            __IOM uint32_t MSTPCRB06 : 1; /*!< [6..6] SPI Unit 2 Module Stop                                             */
+            uint32_t                 : 25;
+        } MSTPCRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRC;           /*!< (@ 0x00000308) Module Stop Control Register C                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRC00 : 1; /*!< [0..0] MTU3 Module Stop                                                   */
+            __IOM uint32_t MSTPCRC01 : 1; /*!< [1..1] GPT Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRC02 : 1; /*!< [2..2] GPT Unit 1 Module Stop                                             */
+            uint32_t                 : 2;
+            __IOM uint32_t MSTPCRC05 : 1; /*!< [5..5] TFU Module Stop                                                    */
+            __IOM uint32_t MSTPCRC06 : 1; /*!< [6..6] ADC12 Unit 0 Module Stop                                           */
+            __IOM uint32_t MSTPCRC07 : 1; /*!< [7..7] ADC12 Unit 1 Module Stop                                           */
+            uint32_t                 : 24;
+        } MSTPCRC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRD;           /*!< (@ 0x0000030C) Module Stop Control Register D                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRD00 : 1; /*!< [0..0] DSMIF Unit 0 Module Stop                                           */
+            __IOM uint32_t MSTPCRD01 : 1; /*!< [1..1] DSMIF Unit 1 Module Stop                                           */
+            __IOM uint32_t MSTPCRD02 : 1; /*!< [2..2] CMT Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRD03 : 1; /*!< [3..3] CMT Unit 1 Module Stop                                             */
+            __IOM uint32_t MSTPCRD04 : 1; /*!< [4..4] CMT Unit 2 Module Stop                                             */
+            __IOM uint32_t MSTPCRD05 : 1; /*!< [5..5] CMTW Unit 0 Module Stop                                            */
+            __IOM uint32_t MSTPCRD06 : 1; /*!< [6..6] CMTW Unit 1 Module Stop                                            */
+            __IOM uint32_t MSTPCRD07 : 1; /*!< [7..7] TSU Module Stop                                                    */
+            __IOM uint32_t MSTPCRD08 : 1; /*!< [8..8] DOC Module Stop                                                    */
+            __IOM uint32_t MSTPCRD09 : 1; /*!< [9..9] CRC Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRD10 : 1; /*!< [10..10] CANFD Module Stop                                                */
+            __IOM uint32_t MSTPCRD11 : 1; /*!< [11..11] CKIO Module Stop                                                 */
+            uint32_t                 : 20;
+        } MSTPCRD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRE;           /*!< (@ 0x00000310) Module Stop Control Register E                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRE00 : 1; /*!< [0..0] GMAC Module Stop                                                   */
+            __IOM uint32_t MSTPCRE01 : 1; /*!< [1..1] ETHSW Module Stop                                                  */
+            __IOM uint32_t MSTPCRE02 : 1; /*!< [2..2] ESC Module Stop                                                    */
+            __IOM uint32_t MSTPCRE03 : 1; /*!< [3..3] Ethernet Subsystem Register Module Stop                            */
+            uint32_t                 : 4;
+            __IOM uint32_t MSTPCRE08 : 1; /*!< [8..8] USB Module Stop                                                    */
+            uint32_t                 : 23;
+        } MSTPCRE_b;
+    };
+    __IM uint32_t RESERVED4[891];
+
+    union
+    {
+        __IM uint32_t MD_MON;          /*!< (@ 0x00001100) Operating Mode Monitor Register                            */
+
+        struct
+        {
+            __IM uint32_t MDDMON  : 1; /*!< [0..0] MDD status flag                                                    */
+            uint32_t              : 7;
+            __IM uint32_t MDP     : 1; /*!< [8..8] Package type                                                       */
+            uint32_t              : 3;
+            __IM uint32_t MD0MON  : 1; /*!< [12..12] MD0 pin status flag                                              */
+            __IM uint32_t MD1MON  : 1; /*!< [13..13] MD1 pin status flag                                              */
+            __IM uint32_t MD2MON  : 1; /*!< [14..14] MD2 pin status flag                                              */
+            uint32_t              : 1;
+            __IM uint32_t MDV0MON : 1; /*!< [16..16] MDV0 status flag (ETH0 domain)                                   */
+            __IM uint32_t MDV1MON : 1; /*!< [17..17] MDV1 status flag (ETH1 domain)                                   */
+            __IM uint32_t MDV2MON : 1; /*!< [18..18] MDV2 status flag (ETH2 domain)                                   */
+            __IM uint32_t MDV3MON : 1; /*!< [19..19] MDV3 status flag (xSPI0 domain)                                  */
+            __IM uint32_t MDV4MON : 1; /*!< [20..20] MDV4 status flag (xSPI1 domain)                                  */
+            uint32_t              : 11;
+        } MD_MON_b;
+    };
+} R_SYSC_NS_Type;                      /*!< Size = 4356 (0x1104)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELO                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Evnet Link Option Setting (R_ELO)
+ */
+
+typedef struct                         /*!< (@ 0x80281200) R_ELO Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t ELOPA;          /*!< (@ 0x00000000) Event Link Option Setting Register A                       */
+
+        struct
+        {
+            __IOM uint32_t MTU0MD : 2; /*!< [1..0] MTU0 Operation Select                                              */
+            uint32_t              : 4;
+            __IOM uint32_t MTU3MD : 2; /*!< [7..6] MTU3 Operation Select                                              */
+            uint32_t              : 24;
+        } ELOPA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ELOPB;          /*!< (@ 0x00000004) Event Link Option Setting Register B                       */
+
+        struct
+        {
+            __IOM uint32_t MTU4MD : 2; /*!< [1..0] MTU4 Operation Select                                              */
+            uint32_t              : 30;
+        } ELOPB_b;
+    };
+} R_ELO_Type;                          /*!< Size = 8 (0x8)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_RWP_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Register Write Protection for Non-safety Area (R_RWP_NS)
+ */
+
+typedef struct                         /*!< (@ 0x80281A10) R_RWP_NS Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t PRCRN;          /*!< (@ 0x00000000) Non_Safety Area Protect Register                           */
+
+        struct
+        {
+            __IOM uint32_t PRC0 : 1;   /*!< [0..0] Protect 0                                                          */
+            __IOM uint32_t PRC1 : 1;   /*!< [1..1] Protect 1                                                          */
+            __IOM uint32_t PRC2 : 1;   /*!< [2..2] Protect 2                                                          */
+            uint32_t            : 5;
+            __OM uint32_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
+            uint32_t            : 16;
+        } PRCRN_b;
+    };
+} R_RWP_NS_Type;                       /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Real Time Clock (R_RTC)
+ */
+
+typedef struct                         /*!< (@ 0x81009000) R_RTC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t RTCA0CTL0;      /*!< (@ 0x00000000) RTC Control Register 0                                     */
+
+        struct
+        {
+            uint32_t                 : 4;
+            __IOM uint32_t RTCA0SLSB : 1; /*!< [4..4] RTCA0SCMP enable/disable setting                                   */
+            __IOM uint32_t RTCA0AMPM : 1; /*!< [5..5] RTCA0HOUR, RTCA0ALH display format selection bit                   */
+            __IM uint32_t  RTCA0CEST : 1; /*!< [6..6] RTC Controller Enable Status                                       */
+            __IOM uint32_t RTCA0CE   : 1; /*!< [7..7] RTC Controller Enable Bit                                          */
+            uint32_t                 : 24;
+        } RTCA0CTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0CTL1;         /*!< (@ 0x00000004) RTC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint32_t RTCA0CT   : 3; /*!< [2..0] Fixed interval interrupt (RTC_PRD) output setting bit              */
+            __IOM uint32_t RTCA01SE  : 1; /*!< [3..3] 1 second interrupt (RTC_1S) output enable bit                      */
+            __IOM uint32_t RTCA0ALME : 1; /*!< [4..4] Alarm interrupt (RTC_ALM) output enable bit                        */
+            __IOM uint32_t RTCA01HZE : 1; /*!< [5..5] This bit enables/disables 1 Hz pulse output (RTCAT1HZ).            */
+            uint32_t                 : 26;
+        } RTCA0CTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0CTL2;         /*!< (@ 0x00000008) RTC Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint32_t RTCA0WAIT : 1; /*!< [0..0] RTC Controller Counter Wait Control                                */
+            __IM uint32_t  RTCA0WST  : 1; /*!< [1..1] RTC Controller Counter Wait Status                                 */
+            __IOM uint32_t RTCA0RSUB : 1; /*!< [2..2] RTCA0SUBC Data Transfer Control                                    */
+            __IM uint32_t  RTCA0RSST : 1; /*!< [3..3] RTCA0SRBU Transfer Status                                          */
+            __IM uint32_t  RTCA0WSST : 1; /*!< [4..4] RTCA0SCMP Write Status                                             */
+            uint32_t                 : 27;
+        } RTCA0CTL2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0SUBC;          /*!< (@ 0x0000000C) RTC Sub Count Register                                     */
+
+        struct
+        {
+            __IM uint32_t RTCA0SUBC : 22; /*!< [21..0] Register that counts the 1 second reference time                  */
+            uint32_t                : 10;
+        } RTCA0SUBC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0SRBU;          /*!< (@ 0x00000010) RTC Sub Count Register Read Buffer                         */
+
+        struct
+        {
+            __IM uint32_t RTCA0SRBU : 22; /*!< [21..0] Read buffer register of RTCA0SUBC                                 */
+            uint32_t                : 10;
+        } RTCA0SRBU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0SEC;         /*!< (@ 0x00000014) RTC Sec Count Buffer Register                              */
+
+        struct
+        {
+            __IOM uint32_t RTCA0SEC : 7; /*!< [6..0] Buffer register to read/write RTC Second Count register
+                                          *   (RTCA0SECC).                                                              */
+            uint32_t : 25;
+        } RTCA0SEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0MIN;         /*!< (@ 0x00000018) RTC Min Count Buffer Register                              */
+
+        struct
+        {
+            __IOM uint32_t RTCA0MIN : 7; /*!< [6..0] Buffer register to read/write RTC Minute Count register
+                                          *   (RTCA0MINC).                                                              */
+            uint32_t : 25;
+        } RTCA0MIN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0HOUR;         /*!< (@ 0x0000001C) RTC Hour Count Buffer Register                             */
+
+        struct
+        {
+            __IOM uint32_t RTCA0HOUR : 6; /*!< [5..0] Buffer register to read/write RTC Hour Count register
+                                           *   (RTCA0HOURC).                                                             */
+            uint32_t : 26;
+        } RTCA0HOUR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0WEEK;         /*!< (@ 0x00000020) RTC Week Count Buffer Register                             */
+
+        struct
+        {
+            __IOM uint32_t RTCA0WEEK : 3; /*!< [2..0] Buffer register to read/write RTC Week Count register
+                                           *   (RTCA0WEEKC).                                                             */
+            uint32_t : 29;
+        } RTCA0WEEK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0DAY;         /*!< (@ 0x00000024) RTC Day Count Buffer Register                              */
+
+        struct
+        {
+            __IOM uint32_t RTCA0DAY : 6; /*!< [5..0] Buffer register to read/write RTC Day Count register
+                                          *   (RTCA0DAYC).                                                              */
+            uint32_t : 26;
+        } RTCA0DAY_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0MONTH;         /*!< (@ 0x00000028) RTC Month Count Buffer Register                            */
+
+        struct
+        {
+            __IOM uint32_t RTCA0MONTH : 5; /*!< [4..0] Buffer register to read/write RTC Month Count register
+                                            *   (RTCA0MONC).                                                              */
+            uint32_t : 27;
+        } RTCA0MONTH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0YEAR;         /*!< (@ 0x0000002C) RTC Year Count Buffer Register                             */
+
+        struct
+        {
+            __IOM uint32_t RTCA0YEAR : 8; /*!< [7..0] Buffer register to read/write RTC Year Count register
+                                           *   (RTCA0YEARC).                                                             */
+            uint32_t : 24;
+        } RTCA0YEAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0TIME;         /*!< (@ 0x00000030) RTC Time Set Register                                      */
+
+        struct
+        {
+            __IOM uint32_t RTCA0SEC  : 8; /*!< [7..0] See RTCA0SEC register                                              */
+            __IOM uint32_t RTCA0MIN  : 8; /*!< [15..8] See RTCA0MIN register                                             */
+            __IOM uint32_t RTCA0HOUR : 8; /*!< [23..16] See RTCA0HOUR register                                           */
+            uint32_t                 : 8;
+        } RTCA0TIME_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0CAL;           /*!< (@ 0x00000034) RTC Calendar Set Register                                  */
+
+        struct
+        {
+            __IOM uint32_t RTCA0WEEK  : 8; /*!< [7..0] See RTCA0WEEK register                                             */
+            __IOM uint32_t RTCA0DAY   : 8; /*!< [15..8] See RTCA0DAY register                                             */
+            __IOM uint32_t RTCA0MONTH : 8; /*!< [23..16] See RTCA0MONTH register                                          */
+            __IOM uint32_t RTCA0YEAR  : 8; /*!< [31..24] See RTCA0YEAR register                                           */
+        } RTCA0CAL_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t RTCA0SCMP;          /*!< (@ 0x0000003C) RTC Sub Count Compare Register                             */
+
+        struct
+        {
+            __IOM uint32_t RTCA0SCMP : 22; /*!< [21..0] Register that sets the compare value of RTCA0SUBC (sub-counter).  */
+            uint32_t                 : 10;
+        } RTCA0SCMP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0ALM;         /*!< (@ 0x00000040) RTC Alarm Min Set Register                                 */
+
+        struct
+        {
+            __IOM uint32_t RTCA0ALM : 7; /*!< [6..0] RTCA0ALM is a register that performs the minute setting
+                                          *   for the alarm interrupt.                                                  */
+            uint32_t : 25;
+        } RTCA0ALM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0ALH;         /*!< (@ 0x00000044) RTC Alarm Hour Set Register                                */
+
+        struct
+        {
+            __IOM uint32_t RTCA0ALH : 6; /*!< [5..0] RTCA0ALH is a register that performs the hour setting
+                                          *   for the alarm interrupt.                                                  */
+            uint32_t : 26;
+        } RTCA0ALH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0ALW;          /*!< (@ 0x00000048) RTC Alarm Week Set Register                                */
+
+        struct
+        {
+            __IOM uint32_t RTCA0ALW0 : 1; /*!< [0..0] Alarm interrupt day of the week setting bit 0                      */
+            __IOM uint32_t RTCA0ALW1 : 1; /*!< [1..1] Alarm interrupt day of the week setting bit 1                      */
+            __IOM uint32_t RTCA0ALW2 : 1; /*!< [2..2] Alarm interrupt day of the week setting bit 2                      */
+            __IOM uint32_t RTCA0ALW3 : 1; /*!< [3..3] Alarm interrupt day of the week setting bit 3                      */
+            __IOM uint32_t RTCA0ALW4 : 1; /*!< [4..4] Alarm interrupt day of the week setting bit 4                      */
+            __IOM uint32_t RTCA0ALW5 : 1; /*!< [5..5] Alarm interrupt day of the week setting bit 5                      */
+            __IOM uint32_t RTCA0ALW6 : 1; /*!< [6..6] Alarm interrupt day of the week setting bit 6                      */
+            uint32_t                 : 25;
+        } RTCA0ALW_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0SECC;         /*!< (@ 0x0000004C) RTC Second Count Register                                  */
+
+        struct
+        {
+            __IM uint32_t RTCA0SECC : 7; /*!< [6..0] Counts up the seconds                                              */
+            uint32_t                : 25;
+        } RTCA0SECC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0MINC;         /*!< (@ 0x00000050) RTC Minute Count Register                                  */
+
+        struct
+        {
+            __IM uint32_t RTCA0MINC : 7; /*!< [6..0] Counts up the minutes                                              */
+            uint32_t                : 25;
+        } RTCA0MINC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0HOURC;         /*!< (@ 0x00000054) RTC Hour Count Register                                    */
+
+        struct
+        {
+            __IM uint32_t RTCA0HOURC : 6; /*!< [5..0] Counts up the hours                                                */
+            uint32_t                 : 26;
+        } RTCA0HOURC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0WEEKC;         /*!< (@ 0x00000058) RTC Week Count Register                                    */
+
+        struct
+        {
+            __IM uint32_t RTCA0WEEKC : 3; /*!< [2..0] Counts up the weeks                                                */
+            uint32_t                 : 29;
+        } RTCA0WEEKC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0DAYC;         /*!< (@ 0x0000005C) RTC Day Count Register                                     */
+
+        struct
+        {
+            __IM uint32_t RTCA0DAYC : 6; /*!< [5..0] Counts up the days                                                 */
+            uint32_t                : 26;
+        } RTCA0DAYC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0MONC;         /*!< (@ 0x00000060) RTC Month Count Register                                   */
+
+        struct
+        {
+            __IM uint32_t RTCA0MONC : 5; /*!< [4..0] Counts up the months                                               */
+            uint32_t                : 27;
+        } RTCA0MONC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0YEARC;         /*!< (@ 0x00000064) RTC Year Count Register                                    */
+
+        struct
+        {
+            __IM uint32_t RTCA0YEARC : 8; /*!< [7..0] Counts up the years                                                */
+            uint32_t                 : 24;
+        } RTCA0YEARC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0TIMEC;         /*!< (@ 0x00000068) RTC Time Count Register                                    */
+
+        struct
+        {
+            __IM uint32_t RTCA0SECC  : 8; /*!< [7..0] See RTCA0SECC register                                             */
+            __IM uint32_t RTCA0MINC  : 8; /*!< [15..8] See RTCA0MINC register                                            */
+            __IM uint32_t RTCA0HOURC : 8; /*!< [23..16] See RTCA0HOURC register                                          */
+            uint32_t                 : 8;
+        } RTCA0TIMEC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0CALC;          /*!< (@ 0x0000006C) RTC Calendar Count Register                                */
+
+        struct
+        {
+            __IM uint32_t RTCA0WEEKC : 8; /*!< [7..0] See RTCA0WEEKC register                                            */
+            __IM uint32_t RTCA0DAYC  : 8; /*!< [15..8] See RTCA0DAYC register                                            */
+            __IM uint32_t RTCA0MONC  : 8; /*!< [23..16] See RTCA0MONC register                                           */
+            __IM uint32_t RTCA0YEARC : 8; /*!< [31..24] See RTCA0YEARC register                                          */
+        } RTCA0CALC_b;
+    };
+} R_RTC_Type;                             /*!< Size = 112 (0x70)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG2                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief GPT Port Output Enable 2 (R_POEG2)
+ */
+
+typedef struct                         /*!< (@ 0x8100A000) R_POEG2 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t POEG2GA;        /*!< (@ 0x00000000) POEG2 Group A Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG2GA_b;
+    };
+    __IM uint32_t RESERVED[255];
+
+    union
+    {
+        __IOM uint32_t POEG2GB;        /*!< (@ 0x00000400) POEG2 Group B Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG2GB_b;
+    };
+    __IM uint32_t RESERVED1[255];
+
+    union
+    {
+        __IOM uint32_t POEG2GC;        /*!< (@ 0x00000800) POEG2 Group C Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG2GC_b;
+    };
+    __IM uint32_t RESERVED2[255];
+
+    union
+    {
+        __IOM uint32_t POEG2GD;        /*!< (@ 0x00000C00) POEG2 Group D Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG2GD_b;
+    };
+} R_POEG2_Type;                        /*!< Size = 3076 (0xc04)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_OTP                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief One-Time Programmable Memory (R_OTP)
+ */
+
+typedef struct                         /*!< (@ 0x81028000) R_OTP Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t OTPPWR;         /*!< (@ 0x00000000) OTP Power Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t PWR  : 1;   /*!< [0..0] OTP power on/off setting                                           */
+            uint32_t            : 3;
+            __IOM uint32_t ACCL : 1;   /*!< [4..4] Selects OTP access I/F                                             */
+            uint32_t            : 27;
+        } OTPPWR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPSTR;             /*!< (@ 0x00000004) OTP Access Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t CMD_RDY : 1;     /*!< [0..0] Indicates whether OTP controller is ready to receive
+                                            *   command or not.                                                           */
+            __IM uint32_t ERR_WR      : 2; /*!< [2..1] OTP write status                                                   */
+            __IM uint32_t ERR_WP      : 1; /*!< [3..3] Write protection error                                             */
+            __IM uint32_t ERR_RP      : 1; /*!< [4..4] Read protection error                                              */
+            uint32_t                  : 3;
+            __IOM uint32_t ERR_RDY_WR : 1; /*!< [8..8] OTP write command ready error                                      */
+            __IOM uint32_t ERR_RDY_RD : 1; /*!< [9..9] OTP read command ready error                                       */
+            uint32_t                  : 5;
+            __IM uint32_t CNT_ST_IDLE : 1; /*!< [15..15] Indicates status of OTP controller                               */
+            uint32_t                  : 16;
+        } OTPSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPSTAWR;       /*!< (@ 0x00000008) OTP Write Command Register                                 */
+
+        struct
+        {
+            __IOM uint32_t STAWR : 1;  /*!< [0..0] OTP write start                                                    */
+            uint32_t             : 31;
+        } OTPSTAWR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPADRWR;       /*!< (@ 0x0000000C) OTP Write Address Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADRWR : 9;  /*!< [8..0] OTP write address                                                  */
+            uint32_t             : 23;
+        } OTPADRWR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPDATAWR;       /*!< (@ 0x00000010) OTP Write Data Register                                    */
+
+        struct
+        {
+            __IOM uint32_t DATAWR : 16; /*!< [15..0] OTP write data                                                    */
+            uint32_t              : 16;
+        } OTPDATAWR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPADRRD;       /*!< (@ 0x00000014) OTP Read Address Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADRRD : 9;  /*!< [8..0] OTP read address                                                   */
+            uint32_t             : 23;
+        } OTPADRRD_b;
+    };
+
+    union
+    {
+        __IM uint32_t OTPDATARD;       /*!< (@ 0x00000018) OTP Read Data Register                                     */
+
+        struct
+        {
+            __IM uint32_t DATARD : 16; /*!< [15..0] OTP read data                                                     */
+            uint32_t             : 16;
+        } OTPDATARD_b;
+    };
+} R_OTP_Type;                          /*!< Size = 28 (0x1c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PTADR                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Port Address Selection (R_PTADR)
+ */
+
+typedef struct                         /*!< (@ 0x81030C00) R_PTADR Structure                                          */
+{
+    union
+    {
+        __IOM uint8_t RSELP[25];       /*!< (@ 0x00000000) Port [0..24] Region Select Register                        */
+
+        struct
+        {
+            __IOM uint8_t RS0 : 1;     /*!< [0..0] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS1 : 1;     /*!< [1..1] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS2 : 1;     /*!< [2..2] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS3 : 1;     /*!< [3..3] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS4 : 1;     /*!< [4..4] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS5 : 1;     /*!< [5..5] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS6 : 1;     /*!< [6..6] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS7 : 1;     /*!< [7..7] Pm_n pin I/O port registers Region Select (n = bit position)       */
+        } RSELP_b[25];
+    };
+} R_PTADR_Type;                        /*!< Size = 25 (0x19)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSRAM0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System SRAM 0 (R_SYSRAM0)
+ */
+
+typedef struct                         /*!< (@ 0x81040000) R_SYSRAM0 Structure                                        */
+{
+    __IOM R_SYSRAM0_W_Type W[4];       /*!< (@ 0x00000000) System SRAM Wn Registers (n = 0 to 3)                      */
+} R_SYSRAM0_Type;                      /*!< Size = 256 (0x100)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ICU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Controller (R_ICU)
+ */
+
+typedef struct                         /*!< (@ 0x81048000) R_ICU Structure                                            */
+{
+    union
+    {
+        __OM uint32_t S_SWINT;         /*!< (@ 0x00000000) Software Interrupt Register for Safety Register            */
+
+        struct
+        {
+            __OM uint32_t IC6 : 1;     /*!< [0..0] Software Interrupt register                                        */
+            __OM uint32_t IC7 : 1;     /*!< [1..1] Software Interrupt register                                        */
+            uint32_t          : 30;
+        } S_SWINT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t S_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register for Safety
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t FLT14  : 1;  /*!< [0..0] Noise filter enable for IRQ14                                      */
+            __IOM uint32_t FLT15  : 1;  /*!< [1..1] Noise filter enable for IRQ15                                      */
+            __IOM uint32_t FLTNMI : 1;  /*!< [2..2] Noise filter enable for NMI                                        */
+            uint32_t              : 29;
+        } S_PORTNF_FLTSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t S_PORTNF_CLKSEL;  /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register for Safety
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t CKSEL14 : 2;  /*!< [1..0] Select noise filter sampling frequency dividend rate
+                                          *   for IRQ14.                                                                */
+            __IOM uint32_t CKSEL15 : 2;  /*!< [3..2] Select noise filter sampling frequency dividend rate
+                                          *   for IRQ15.                                                                */
+            __IOM uint32_t CKSELNMI : 2; /*!< [5..4] Select noise filter sampling frequency dividend rate
+                                          *   for NMI.                                                                  */
+            uint32_t : 26;
+        } S_PORTNF_CLKSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t S_PORTNF_MD;    /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register for
+                                        *                  Safety Register                                            */
+
+        struct
+        {
+            __IOM uint32_t MD14  : 2;  /*!< [1..0] Select detection mode for IRQ14                                    */
+            __IOM uint32_t MD15  : 2;  /*!< [3..2] Select detection mode for IRQ15                                    */
+            __IOM uint32_t MDNMI : 2;  /*!< [5..4] Select detection mode for NMI                                      */
+            uint32_t             : 26;
+        } S_PORTNF_MD_b;
+    };
+    __IM uint32_t RESERVED[20];
+
+    union
+    {
+        __IM uint32_t CPU0ERR_STAT;    /*!< (@ 0x00000060) CPU0 Error Event Status Register                           */
+
+        struct
+        {
+            __IM uint32_t ER_ST0  : 1; /*!< [0..0] Indicate captured error status for CPU0_ERREVENT0                  */
+            __IM uint32_t ER_ST1  : 1; /*!< [1..1] Indicate captured error status for CPU0_ERREVENT1                  */
+            __IM uint32_t ER_ST2  : 1; /*!< [2..2] Indicate captured error status for CPU0_ERREVENT2                  */
+            __IM uint32_t ER_ST3  : 1; /*!< [3..3] Indicate captured error status for CPU0_ERREVENT3                  */
+            __IM uint32_t ER_ST4  : 1; /*!< [4..4] Indicate captured error status for CPU0_ERREVENT4                  */
+            __IM uint32_t ER_ST5  : 1; /*!< [5..5] Indicate captured error status for CPU0_ERREVENT5                  */
+            __IM uint32_t ER_ST6  : 1; /*!< [6..6] Indicate captured error status for CPU0_ERREVENT6                  */
+            __IM uint32_t ER_ST7  : 1; /*!< [7..7] Indicate captured error status for CPU0_ERREVENT7                  */
+            __IM uint32_t ER_ST8  : 1; /*!< [8..8] Indicate captured error status for CPU0_ERREVENT8                  */
+            __IM uint32_t ER_ST9  : 1; /*!< [9..9] Indicate captured error status for CPU0_ERREVENT9                  */
+            __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for CPU0_ERREVENT10               */
+            __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for CPU0_ERREVENT11               */
+            __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for CPU0_ERREVENT12               */
+            __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for CPU0_ERREVENT13               */
+            __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for CPU0_ERREVENT14               */
+            __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for CPU0_ERREVENT15               */
+            __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for CPU0_ERREVENT16               */
+            __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for CPU0_ERREVENT17               */
+            __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for CPU0_ERREVENT18               */
+            __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for CPU0_ERREVENT19               */
+            __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for CPU0_ERREVENT20               */
+            __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for CPU0_ERREVENT21               */
+            __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for CPU0_ERREVENT22               */
+            __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for CPU0_ERREVENT23               */
+            __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for CPU0_ERREVENT24               */
+            __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for CPU0_ERREVENT25               */
+            uint32_t              : 6;
+        } CPU0ERR_STAT_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IM uint32_t PERIERR_STAT0;   /*!< (@ 0x00000068) Peripheral Error Event Status Register 0                   */
+
+        struct
+        {
+            __IM uint32_t ER_ST0  : 1; /*!< [0..0] Indicate captured error status for CLMA3_INT                       */
+            __IM uint32_t ER_ST1  : 1; /*!< [1..1] Indicate captured error status for CLMA0_INT                       */
+            __IM uint32_t ER_ST2  : 1; /*!< [2..2] Indicate captured error status for CLMA1_INT                       */
+            __IM uint32_t ER_ST3  : 1; /*!< [3..3] Indicate captured error status for CLMA2_INT                       */
+            __IM uint32_t ER_ST4  : 1; /*!< [4..4] Indicate captured error status for BSC_WTO                         */
+            __IM uint32_t ER_ST5  : 1; /*!< [5..5] Indicate captured error status for DMAC0_ERR                       */
+            __IM uint32_t ER_ST6  : 1; /*!< [6..6] Indicate captured error status for DMAC1_ERR                       */
+            __IM uint32_t ER_ST7  : 1; /*!< [7..7] Indicate captured error status for WDT_NMIUNDF0                    */
+            uint32_t              : 1;
+            __IM uint32_t ER_ST9  : 1; /*!< [9..9] Indicate captured error status for USB_FDMAERR                     */
+            __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for DSMIF0_LTCSE                  */
+            __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for DSMIF0_UTCSE                  */
+            __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for DSMIF0_LTODE0                 */
+            __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for DSMIF0_LTODE1                 */
+            __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for DSMIF0_LTODE2                 */
+            __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for DSMIF0_UTODE0                 */
+            __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for DSMIF0_UTODE1                 */
+            __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for DSMIF0_UTODE2                 */
+            __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for DSMIF0_SCDE0                  */
+            __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for DSMIF0_SCDE1                  */
+            __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for DSMIF0_SCDE2                  */
+            __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for DSMIF1_LTCSE                  */
+            __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for DSMIF1_UTCSE                  */
+            __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for DSMIF1_LTODE0                 */
+            __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for DSMIF1_LTODE1                 */
+            __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for DSMIF1_LTODE2                 */
+            __IM uint32_t ER_ST26 : 1; /*!< [26..26] Indicate captured error status for DSMIF1_UTODE0                 */
+            __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for DSMIF1_UTODE1                 */
+            __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for DSMIF1_UTODE2                 */
+            __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate captured error status for DSMIF1_SCDE0                  */
+            __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate captured error status for DSMIF1_SCDE1                  */
+            __IM uint32_t ER_ST31 : 1; /*!< [31..31] Indicate captured error status for DSMIF1_SCDE2                  */
+        } PERIERR_STAT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t PERIERR_STAT1;   /*!< (@ 0x0000006C) Peripheral Error Event Status Register 1                   */
+
+        struct
+        {
+            __IM uint32_t ER_ST0  : 1; /*!< [0..0] Indicate captured error status for DOC_DOPCI                       */
+            __IM uint32_t ER_ST1  : 1; /*!< [1..1] Indicate captured error status for SRAM0_IE1                       */
+            __IM uint32_t ER_ST2  : 1; /*!< [2..2] Indicate captured error status for SRAM0_IE2                       */
+            __IM uint32_t ER_ST3  : 1; /*!< [3..3] Indicate captured error status for SRAM0_OVF                       */
+            __IM uint32_t ER_ST4  : 1; /*!< [4..4] Indicate captured error status for SRAM1_IE1                       */
+            __IM uint32_t ER_ST5  : 1; /*!< [5..5] Indicate captured error status for SRAM1_IE2                       */
+            __IM uint32_t ER_ST6  : 1; /*!< [6..6] Indicate captured error status for SRAM1_OVF                       */
+            __IM uint32_t ER_ST7  : 1; /*!< [7..7] Indicate captured error status for SRAM2_IE1                       */
+            __IM uint32_t ER_ST8  : 1; /*!< [8..8] Indicate captured error status for SRAM2_IE2                       */
+            __IM uint32_t ER_ST9  : 1; /*!< [9..9] Indicate captured error status for SRAM2_OVF                       */
+            uint32_t              : 3;
+            __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for BUS_ERRINT                    */
+            uint32_t              : 1;
+            __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for MPU_SHOSTIF                   */
+            __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for MPU_PHOSTIF                   */
+            __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for MPU_DMACR0                    */
+            __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for MPU_DMACW0                    */
+            __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for MPU_DMACR1                    */
+            __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for MPU_DMACW1                    */
+            __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for MPU_GMACR                     */
+            __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for MPU_GMACW                     */
+            __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for MPU_USBH                      */
+            __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for MPU_USBF                      */
+            uint32_t              : 2;
+            __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for MPU_DBGR                      */
+            __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for MPU_DBGW                      */
+            uint32_t              : 3;
+        } PERIERR_STAT1_b;
+    };
+
+    union
+    {
+        __OM uint32_t CPU0ERR_CLR;     /*!< (@ 0x00000070) CPU0 Error Event Status Clear Register                     */
+
+        struct
+        {
+            __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL8 : 1;  /*!< [8..8] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for CPU0ERR_STAT register
+                                        *   by writing 1                                                              */
+            uint32_t : 6;
+        } CPU0ERR_CLR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __OM uint32_t PERIERR_CLR0;    /*!< (@ 0x00000078) Peripheral Error Event Status Clear Register
+                                        *                  0                                                          */
+
+        struct
+        {
+            __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            uint32_t             : 1;
+            __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL26 : 1; /*!< [26..26] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL29 : 1; /*!< [29..29] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL30 : 1; /*!< [30..30] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL31 : 1; /*!< [31..31] Clear captured error status for PERIERR_STAT0 register
+                                        *   by writing 1                                                              */
+        } PERIERR_CLR0_b;
+    };
+
+    union
+    {
+        __OM uint32_t PERIERR_CLR1;    /*!< (@ 0x0000007C) Peripheral Error Event Status Clear Register
+                                        *                  1                                                          */
+
+        struct
+        {
+            __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL8 : 1;  /*!< [8..8] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            uint32_t              : 3;
+            __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            uint32_t              : 1;
+            __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            uint32_t              : 2;
+            __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT1 register
+                                        *   by writing 1                                                              */
+            uint32_t : 3;
+        } PERIERR_CLR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CPU0ERR_RSTMSK;  /*!< (@ 0x00000080) CPU0 Error Event Reset Mask Register                       */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1; /*!< [0..0] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK1  : 1; /*!< [1..1] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK2  : 1; /*!< [2..2] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK3  : 1; /*!< [3..3] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK4  : 1; /*!< [4..4] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK5  : 1; /*!< [5..5] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK6  : 1; /*!< [6..6] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK7  : 1; /*!< [7..7] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK8  : 1; /*!< [8..8] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK9  : 1; /*!< [9..9] Mask captured error status as a reset event for CPU0ERR_STAT       */
+            __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for CPU0ERR_STAT     */
+            uint32_t               : 6;
+        } CPU0ERR_RSTMSK_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t PERIERR_RSTMSK0; /*!< (@ 0x00000088) Peripheral Error Event Reset Mask Register 0               */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT0      */
+            __IOM uint32_t RS_MK1  : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT0      */
+            __IOM uint32_t RS_MK2  : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT0      */
+            __IOM uint32_t RS_MK3  : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT0      */
+            __IOM uint32_t RS_MK4  : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT0      */
+            __IOM uint32_t RS_MK5  : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT0      */
+            __IOM uint32_t RS_MK6  : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT0      */
+            __IOM uint32_t RS_MK7  : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT0      */
+            uint32_t               : 1;
+            __IOM uint32_t RS_MK9  : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT0      */
+            __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK26 : 1; /*!< [26..26] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK29 : 1; /*!< [29..29] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK30 : 1; /*!< [30..30] Mask captured error status as a reset event for PERIERR_STAT0    */
+            __IOM uint32_t RS_MK31 : 1; /*!< [31..31] Mask captured error status as a reset event for PERIERR_STAT0    */
+        } PERIERR_RSTMSK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PERIERR_RSTMSK1; /*!< (@ 0x0000008C) Peripheral Error Event Reset Mask Register 1               */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK1  : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK2  : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK3  : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK4  : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK5  : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK6  : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK7  : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK8  : 1; /*!< [8..8] Mask captured error status as a reset event for PERIERR_STAT1      */
+            __IOM uint32_t RS_MK9  : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT1      */
+            uint32_t               : 3;
+            __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT1    */
+            uint32_t               : 1;
+            __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT1    */
+            uint32_t               : 2;
+            __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT1    */
+            __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT1    */
+            uint32_t               : 3;
+        } PERIERR_RSTMSK1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CPU0ERR_E0MSK;   /*!< (@ 0x00000090) CPU0 E0 Error Event Mask Register                          */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0 : 1;  /*!< [0..0] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK1 : 1;  /*!< [1..1] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK2 : 1;  /*!< [2..2] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK3 : 1;  /*!< [3..3] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK4 : 1;  /*!< [4..4] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK5 : 1;  /*!< [5..5] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK6 : 1;  /*!< [6..6] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK7 : 1;  /*!< [7..7] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK8 : 1;  /*!< [8..8] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK9 : 1;  /*!< [9..9] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU0_ERR0 event for
+                                         *   CPU0ERR_STAT                                                              */
+            uint32_t : 6;
+        } CPU0ERR_E0MSK_b;
+    };
+    __IM uint32_t RESERVED4;
+
+    union
+    {
+        __IOM uint32_t PERIERR_E0MSK0;  /*!< (@ 0x00000098) Peripheral E0 Error Event Mask Register 0                  */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0 : 1;  /*!< [0..0] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK1 : 1;  /*!< [1..1] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK2 : 1;  /*!< [2..2] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK3 : 1;  /*!< [3..3] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK4 : 1;  /*!< [4..4] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK5 : 1;  /*!< [5..5] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK6 : 1;  /*!< [6..6] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK7 : 1;  /*!< [7..7] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            uint32_t              : 1;
+            __IOM uint32_t E0_MK9 : 1;  /*!< [9..9] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK26 : 1; /*!< [26..26] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK29 : 1; /*!< [29..29] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK30 : 1; /*!< [30..30] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E0_MK31 : 1; /*!< [31..31] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT0                                                             */
+        } PERIERR_E0MSK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PERIERR_E0MSK1;  /*!< (@ 0x0000009C) Peripheral E0 Error Event Mask Register 1                  */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0 : 1;  /*!< [0..0] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK1 : 1;  /*!< [1..1] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK2 : 1;  /*!< [2..2] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK3 : 1;  /*!< [3..3] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK4 : 1;  /*!< [4..4] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK5 : 1;  /*!< [5..5] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK6 : 1;  /*!< [6..6] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK7 : 1;  /*!< [7..7] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK8 : 1;  /*!< [8..8] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK9 : 1;  /*!< [9..9] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            uint32_t               : 3;
+            __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            uint32_t               : 1;
+            __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            uint32_t               : 2;
+            __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR0 event for
+                                         *   PERIERR_STAT1                                                             */
+            uint32_t : 3;
+        } PERIERR_E0MSK1_b;
+    };
+    __IM uint32_t RESERVED5[24];
+
+    union
+    {
+        __IOM uint32_t CPU0ERR_E1MSK;   /*!< (@ 0x00000100) CPU0 E1 Error Event Mask Register                          */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0 : 1;  /*!< [0..0] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK1 : 1;  /*!< [1..1] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK2 : 1;  /*!< [2..2] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK3 : 1;  /*!< [3..3] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK4 : 1;  /*!< [4..4] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK5 : 1;  /*!< [5..5] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK6 : 1;  /*!< [6..6] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK7 : 1;  /*!< [7..7] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK8 : 1;  /*!< [8..8] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK9 : 1;  /*!< [9..9] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU0_ERR1 event for
+                                         *   CPU0ERR_STAT                                                              */
+            uint32_t : 6;
+        } CPU0ERR_E1MSK_b;
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IOM uint32_t PERIERR_E1MSK0;  /*!< (@ 0x00000108) Peripheral E1 Error Event Mask Register 0                  */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0 : 1;  /*!< [0..0] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK1 : 1;  /*!< [1..1] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK2 : 1;  /*!< [2..2] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK3 : 1;  /*!< [3..3] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK4 : 1;  /*!< [4..4] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK5 : 1;  /*!< [5..5] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK6 : 1;  /*!< [6..6] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK7 : 1;  /*!< [7..7] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            uint32_t              : 1;
+            __IOM uint32_t E1_MK9 : 1;  /*!< [9..9] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK26 : 1; /*!< [26..26] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK29 : 1; /*!< [29..29] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK30 : 1; /*!< [30..30] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+            __IOM uint32_t E1_MK31 : 1; /*!< [31..31] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT0                                                             */
+        } PERIERR_E1MSK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PERIERR_E1MSK1;  /*!< (@ 0x0000010C) Peripheral E1 Error Event Mask Register 1                  */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0 : 1;  /*!< [0..0] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK1 : 1;  /*!< [1..1] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK2 : 1;  /*!< [2..2] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK3 : 1;  /*!< [3..3] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK4 : 1;  /*!< [4..4] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK5 : 1;  /*!< [5..5] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK6 : 1;  /*!< [6..6] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK7 : 1;  /*!< [7..7] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK8 : 1;  /*!< [8..8] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK9 : 1;  /*!< [9..9] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            uint32_t               : 3;
+            __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            uint32_t               : 1;
+            __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            uint32_t               : 2;
+            __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR1 event for
+                                         *   PERIERR_STAT1                                                             */
+            uint32_t : 3;
+        } PERIERR_E1MSK1_b;
+    };
+} R_ICU_Type;                           /*!< Size = 272 (0x110)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSC_S                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Register Write Protection for Safety Area (R_SYSC_S)
+ */
+
+typedef struct                         /*!< (@ 0x81280000) R_SYSC_S Structure                                         */
+{
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t SCKCR2;               /*!< (@ 0x00000004) System Clock Control Register 2                            */
+
+        struct
+        {
+            __IOM uint32_t FSELCPU0 : 1;     /*!< [0..0] Set the frequency of the clock provided to Coretex-R52
+                                              *   CPU0 in combination with bit 5 (DIVSELSUB). The combination
+                                              *   is shown below.                                                           */
+            uint32_t                    : 4;
+            __IOM uint32_t DIVSELSUB    : 1; /*!< [5..5] Select the base clock frequency for peripheral module.             */
+            uint32_t                    : 18;
+            __IOM uint32_t SPI3ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SPI3                                                       */
+            __IOM uint32_t SCI5ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock
+                                              *   is selected in SCI5                                                       */
+            uint32_t : 6;
+        } SCKCR2_b;
+    };
+    __IM uint32_t RESERVED1[6];
+
+    union
+    {
+        __IM uint32_t PLL0MON;         /*!< (@ 0x00000020) PLL0 Monitor Register                                      */
+
+        struct
+        {
+            __IM uint32_t PLL0MON : 1; /*!< [0..0] PLL0 Lock State Monitor                                            */
+            uint32_t              : 31;
+        } PLL0MON_b;
+    };
+    __IM uint32_t RESERVED2[7];
+
+    union
+    {
+        __IM uint32_t PLL1MON;         /*!< (@ 0x00000040) PLL1 Monitor Register                                      */
+
+        struct
+        {
+            __IM uint32_t PLL1MON : 1; /*!< [0..0] PLL1 Lock State Monitor                                            */
+            uint32_t              : 31;
+        } PLL1MON_b;
+    };
+    __IM uint32_t RESERVED3[3];
+
+    union
+    {
+        __IOM uint32_t PLL1EN;         /*!< (@ 0x00000050) PLL1 Enable Register                                       */
+
+        struct
+        {
+            __IOM uint32_t PLL1EN : 1; /*!< [0..0] PLL1 Enable                                                        */
+            uint32_t              : 31;
+        } PLL1EN_b;
+    };
+    __IM uint32_t RESERVED4[7];
+
+    union
+    {
+        __IOM uint32_t LOCOCR;         /*!< (@ 0x00000070) Low-Speed On-Chip Oscillator Control Register              */
+
+        struct
+        {
+            __IOM uint32_t LCSTP : 1;  /*!< [0..0] LOCO Stop                                                          */
+            uint32_t             : 31;
+        } LOCOCR_b;
+    };
+    __IM uint32_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint32_t HIZCTRLEN;         /*!< (@ 0x00000080) High-Impedance Control Enable Register                     */
+
+        struct
+        {
+            __IOM uint32_t CLMA3MASK : 1; /*!< [0..0] CLMA3 error mask to POE3 and POEG                                  */
+            __IOM uint32_t CLMA0MASK : 1; /*!< [1..1] CLMA0 error mask to POE3 and POEG                                  */
+            __IOM uint32_t CLMA1MASK : 1; /*!< [2..2] CLMA1 error mask to POE3 and POEG                                  */
+            uint32_t                 : 29;
+        } HIZCTRLEN_b;
+    };
+    __IM uint32_t RESERVED6[99];
+
+    union
+    {
+        __OM uint32_t SWRSYS;          /*!< (@ 0x00000210) System Software Reset Register                             */
+
+        struct
+        {
+            __OM uint32_t SWR : 32;    /*!< [31..0] System Software Reset                                             */
+        } SWRSYS_b;
+    };
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        __IOM uint32_t SWRCPU0;        /*!< (@ 0x00000220) CPU0 Software Reset Register                               */
+
+        struct
+        {
+            __IOM uint32_t SWR : 32;   /*!< [31..0] CPU0 Software Reset                                               */
+        } SWRCPU0_b;
+    };
+    __IM uint32_t RESERVED8[15];
+
+    union
+    {
+        __IOM uint32_t MRCTLI;           /*!< (@ 0x00000260) Module Reset Control Register I                            */
+
+        struct
+        {
+            __IOM uint32_t MRCTLI00 : 1; /*!< [0..0] PHOSTIF Reset Control                                              */
+            __IOM uint32_t MRCTLI01 : 1; /*!< [1..1] SHOSTIF (Master bus clock domain) Reset Control                    */
+            __IOM uint32_t MRCTLI02 : 1; /*!< [2..2] SHOSTIF (Slave bus clock domain) Reset Control                     */
+            __IOM uint32_t MRCTLI03 : 1; /*!< [3..3] SHOSTIF (IP clock domain) Reset Control                            */
+            uint32_t                : 28;
+        } MRCTLI_b;
+    };
+    __IM uint32_t RESERVED9[44];
+
+    union
+    {
+        __IOM uint32_t MSTPCRF;           /*!< (@ 0x00000314) Module Stop Control Register F                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRF00 : 1; /*!< [0..0] Trace Clock for Debugging Interface Module Stop                    */
+            uint32_t                 : 31;
+        } MSTPCRF_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRG;           /*!< (@ 0x00000318) Module Stop Control Register G                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRG00 : 1; /*!< [0..0] SCI Unit 5 Module Stop                                             */
+            __IOM uint32_t MSTPCRG01 : 1; /*!< [1..1] IIC Unit 2 Module Stop                                             */
+            __IOM uint32_t MSTPCRG02 : 1; /*!< [2..2] SPI Unit 3 Module Stop                                             */
+            __IOM uint32_t MSTPCRG03 : 1; /*!< [3..3] GPT Unit 2 Module Stop                                             */
+            __IOM uint32_t MSTPCRG04 : 1; /*!< [4..4] CRC Unit 1 Module Stop                                             */
+            __IOM uint32_t MSTPCRG05 : 1; /*!< [5..5] RTC Module Stop                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t MSTPCRG08 : 1; /*!< [8..8] CLMA3 Module Stop                                                  */
+            __IOM uint32_t MSTPCRG09 : 1; /*!< [9..9] CLMA0 Module Stop                                                  */
+            __IOM uint32_t MSTPCRG10 : 1; /*!< [10..10] CLMA1 Module Stop                                                */
+            __IOM uint32_t MSTPCRG11 : 1; /*!< [11..11] CLMA2 Module Stop                                                */
+            uint32_t                 : 20;
+        } MSTPCRG_b;
+    };
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IOM uint32_t MSTPCRI;           /*!< (@ 0x00000320) Module Stop Control Register I                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRI00 : 1; /*!< [0..0] PHOSTIF Module Stop                                                */
+            __IOM uint32_t MSTPCRI01 : 1; /*!< [1..1] SHOSTIF Module Stop                                                */
+            uint32_t                 : 30;
+        } MSTPCRI_b;
+    };
+} R_SYSC_S_Type;                          /*!< Size = 804 (0x324)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CLMA0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Clock Monitor Circuit 0 (R_CLMA0)
+ */
+
+typedef struct                         /*!< (@ 0x81280800) R_CLMA0 Structure                                          */
+{
+    union
+    {
+        __IOM uint8_t CTL0;            /*!< (@ 0x00000000) CLMA Control Register 0                                    */
+
+        struct
+        {
+            __IOM uint8_t CLME : 1;    /*!< [0..0] Clock Monitor m Enable (m = 0 to 3)                                */
+            uint8_t            : 7;
+        } CTL0_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint16_t CMPL;           /*!< (@ 0x00000008) CLMA Compare Register L                                    */
+
+        struct
+        {
+            __IOM uint16_t CMPL : 12;  /*!< [11..0] Clock Monitor m Compare L (m = 0 to 3)                            */
+            uint16_t            : 4;
+        } CMPL_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint16_t CMPH;           /*!< (@ 0x0000000C) CLMA Compare Register H                                    */
+
+        struct
+        {
+            __IOM uint16_t CMPH : 12;  /*!< [11..0] Clock Monitor m Compare H (m = 0 to 3)                            */
+            uint16_t            : 4;
+        } CMPH_b;
+    };
+    __IM uint16_t RESERVED3;
+    __OM uint8_t  PCMD;                /*!< (@ 0x00000010) CLMA Command Register                                      */
+    __IM uint8_t  RESERVED4;
+    __IM uint16_t RESERVED5;
+
+    union
+    {
+        __IM uint8_t PROTSR;           /*!< (@ 0x00000014) CLMA Protection Status Register                            */
+
+        struct
+        {
+            __IM uint8_t PRERR : 1;    /*!< [0..0] CLMAm Error (m = 0 to 3)                                           */
+            uint8_t            : 7;
+        } PROTSR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+} R_CLMA0_Type;                        /*!< Size = 24 (0x18)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MPU0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Master MPU 0 (R_MPU0)
+ */
+
+typedef struct                           /*!< (@ 0x81281100) R_MPU0 Structure                                           */
+{
+    __IOM R_MPU0_RGN_Type RGN[8];        /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register
+                                          *                  [0..7]                                                     */
+
+    union
+    {
+        __IOM uint32_t ERRINF_R;         /*!< (@ 0x00000080) Master MPU Error Information Register for AXI
+                                          *                  type                                                       */
+
+        struct
+        {
+            __IOM uint32_t VALID   : 1;  /*!< [0..0] Validity of access error information                               */
+            __IM uint32_t  RW      : 1;  /*!< [1..1] Access error type                                                  */
+            __IM uint32_t  ERRADDR : 30; /*!< [31..2] Access error address                                              */
+        } ERRINF_R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ERRINF_W;         /*!< (@ 0x00000084) Master MPU Error Information Register for AXI
+                                          *                  type                                                       */
+
+        struct
+        {
+            __IOM uint32_t VALID   : 1;  /*!< [0..0] Validity of access error information                               */
+            __IM uint32_t  RW      : 1;  /*!< [1..1] Access error type                                                  */
+            __IM uint32_t  ERRADDR : 30; /*!< [31..2] Access error address                                              */
+        } ERRINF_W_b;
+    };
+} R_MPU0_Type;                           /*!< Size = 136 (0x88)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MPU3                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Master MPU 3 (R_MPU3)
+ */
+
+typedef struct                           /*!< (@ 0x81281400) R_MPU3 Structure                                           */
+{
+    __IOM R_MPU0_RGN_Type RGN[8];        /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register
+                                          *                  [0..7]                                                     */
+
+    union
+    {
+        __IOM uint32_t ERRINF;           /*!< (@ 0x00000080) Master MPU Error Information Register for AHB
+                                          *                  type                                                       */
+
+        struct
+        {
+            __IOM uint32_t VALID   : 1;  /*!< [0..0] Validity of Access Error Information                               */
+            __IM uint32_t  RW      : 1;  /*!< [1..1] Access error type                                                  */
+            __IM uint32_t  ERRADDR : 30; /*!< [31..2] Access Error Address                                              */
+        } ERRINF_b;
+    };
+} R_MPU3_Type;                           /*!< Size = 132 (0x84)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                       R_SYSRAM_CTL                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System SRAM Control (R_SYSRAM_CTL)
+ */
+
+typedef struct                              /*!< (@ 0x81281800) R_SYSRAM_CTL Structure                                     */
+{
+    union
+    {
+        __IOM uint32_t SYSRAM_CTRL0;        /*!< (@ 0x00000000) System SRAM Control Register 0                             */
+
+        struct
+        {
+            __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
+            uint32_t                   : 15;
+            __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
+            __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
+            __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
+            uint32_t                   : 2;
+            __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
+            uint32_t                   : 7;
+        } SYSRAM_CTRL0_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t SYSRAM_CTRL1;        /*!< (@ 0x00000010) System SRAM Control Register 1                             */
+
+        struct
+        {
+            __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
+            uint32_t                   : 15;
+            __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
+            __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
+            __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
+            uint32_t                   : 2;
+            __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
+            uint32_t                   : 7;
+        } SYSRAM_CTRL1_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint32_t SYSRAM_CTRL2;        /*!< (@ 0x00000020) System SRAM Control Register 2                             */
+
+        struct
+        {
+            __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
+            uint32_t                   : 15;
+            __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
+            __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
+            __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
+            uint32_t                   : 2;
+            __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
+            uint32_t                   : 7;
+        } SYSRAM_CTRL2_b;
+    };
+} R_SYSRAM_CTL_Type;                        /*!< Size = 36 (0x24)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                       R_SHOSTIF_CFG                                       ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Host Interface Configuration (R_SHOSTIF_CFG)
+ */
+
+typedef struct                             /*!< (@ 0x81281920) R_SHOSTIF_CFG Structure                                    */
+{
+    union
+    {
+        __IOM uint32_t SHCFG;              /*!< (@ 0x00000000) SHOSTIF Configuration Register                             */
+
+        struct
+        {
+            __IOM uint32_t SPIMODE    : 2; /*!< [1..0] SPI Frame Format Select                                            */
+            __IOM uint32_t BYTESWAP   : 1; /*!< [2..2] Byte Swap Mode                                                     */
+            __IOM uint32_t ADDRESSING : 1; /*!< [3..3] Addressing Mode                                                    */
+            __IM uint32_t  SLEEP      : 1; /*!< [4..4] SHOSTIF Enable Flag Monitor                                        */
+            uint32_t                  : 11;
+            __IOM uint32_t INTMASKI   : 6; /*!< [21..16] Interrupt Mask Enable for Internal Interrupt (SHOST_INT)         */
+            uint32_t                  : 2;
+            __IOM uint32_t INTMASKE   : 6; /*!< [29..24] Interrupt Mask Enable for External Interrupt (HSPI_INT#
+                                            *   signal)                                                                   */
+            uint32_t : 2;
+        } SHCFG_b;
+    };
+} R_SHOSTIF_CFG_Type;                      /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                       R_PHOSTIF_CFG                                       ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Parallel Host Interface Configuration (R_PHOSTIF_CFG)
+ */
+
+typedef struct                            /*!< (@ 0x81281930) R_PHOSTIF_CFG Structure                                    */
+{
+    union
+    {
+        __IOM uint32_t PHCFG;             /*!< (@ 0x00000000) PHOSTIF Configureation Register                            */
+
+        struct
+        {
+            __IOM uint32_t MEMIFSEL  : 1; /*!< [0..0] MEMIFSEL                                                           */
+            uint32_t                 : 3;
+            __IOM uint32_t BUSSSEL   : 1; /*!< [4..4] BUSSSEL                                                            */
+            uint32_t                 : 3;
+            __IOM uint32_t HIFSYNC   : 1; /*!< [8..8] HIFSYNC                                                            */
+            uint32_t                 : 3;
+            __IOM uint32_t MEMCSEL   : 1; /*!< [12..12] MEMCSEL                                                          */
+            uint32_t                 : 3;
+            __IOM uint32_t HWRZSEL   : 1; /*!< [16..16] HWRZSEL                                                          */
+            uint32_t                 : 3;
+            __IOM uint32_t ADMUXMODE : 1; /*!< [20..20] ADMUXMODE                                                        */
+            uint32_t                 : 11;
+        } PHCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PHACC;              /*!< (@ 0x00000004) PHOSTIF Register Access Control Register                   */
+
+        struct
+        {
+            __IOM uint32_t HIFRDYSEL  : 1; /*!< [0..0] HIFRDYSEL                                                          */
+            uint32_t                  : 7;
+            __IOM uint32_t HIFBCCSEL  : 1; /*!< [8..8] HIFBCCSEL                                                          */
+            __IOM uint32_t HIFBTCSEL  : 1; /*!< [9..9] HIFBTCSEL                                                          */
+            __IOM uint32_t HIFPRCSEL  : 1; /*!< [10..10] HIFPRCSEL                                                        */
+            __IOM uint32_t HIFIRCSEL  : 1; /*!< [11..11] HIFIRCSEL                                                        */
+            __IOM uint32_t HIFXALSEL  : 1; /*!< [12..12] HIFXALSEL                                                        */
+            __IOM uint32_t HIFXAHSEL  : 1; /*!< [13..13] HIFXAHSEL                                                        */
+            __IOM uint32_t HIFEXT0SEL : 1; /*!< [14..14] HIFEXT0SEL                                                       */
+            __IOM uint32_t HIFEXT1SEL : 1; /*!< [15..15] HIFEXT1SEL                                                       */
+            __IOM uint32_t CSSWAP     : 1; /*!< [16..16] CSSWAP                                                           */
+            __IOM uint32_t BSCADMUX   : 1; /*!< [17..17] BSCADMUX                                                         */
+            uint32_t                  : 14;
+        } PHACC_b;
+    };
+} R_PHOSTIF_CFG_Type;                      /*!< Size = 8 (0x8)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_RWP_S                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Register Write Protection for Safety Area (R_RWP_S)
+ */
+
+typedef struct                         /*!< (@ 0x81281A00) R_RWP_S Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t PRCRS;          /*!< (@ 0x00000000) Safety Area Protect Register                               */
+
+        struct
+        {
+            __IOM uint32_t PRC0 : 1;   /*!< [0..0] Protect 0                                                          */
+            __IOM uint32_t PRC1 : 1;   /*!< [1..1] Protect 1                                                          */
+            __IOM uint32_t PRC2 : 1;   /*!< [2..2] Protect 2                                                          */
+            __IOM uint32_t PRC3 : 1;   /*!< [3..3] Protect 3                                                          */
+            uint32_t            : 4;
+            __OM uint32_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
+            uint32_t            : 16;
+        } PRCRS_b;
+    };
+} R_RWP_S_Type;                        /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_MTU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit (R_MTU)
+ */
+
+typedef struct                         /*!< (@ 0x90001000) R_MTU Structure                                            */
+{
+    __IM uint16_t RESERVED[261];
+
+    union
+    {
+        __IOM uint8_t TOERA;           /*!< (@ 0x0000020A) Timer Output Master Enable Register A                      */
+
+        struct
+        {
+            __IOM uint8_t OE3B : 1;    /*!< [0..0] Master Enable MTIOC3B                                              */
+            __IOM uint8_t OE4A : 1;    /*!< [1..1] Master Enable MTIOC4A                                              */
+            __IOM uint8_t OE4B : 1;    /*!< [2..2] Master Enable MTIOC4B                                              */
+            __IOM uint8_t OE3D : 1;    /*!< [3..3] Master Enable MTIOC3D                                              */
+            __IOM uint8_t OE4C : 1;    /*!< [4..4] Master Enable MTIOC4C                                              */
+            __IOM uint8_t OE4D : 1;    /*!< [5..5] Master Enable MTIOC4D                                              */
+            uint8_t            : 2;
+        } TOERA_b;
+    };
+    __IM uint8_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint8_t TGCRA;           /*!< (@ 0x0000020D) Timer Gate Control Register A                              */
+
+        struct
+        {
+            __IOM uint8_t UF  : 1;     /*!< [0..0] Output Phase Switch                                                */
+            __IOM uint8_t VF  : 1;     /*!< [1..1] Output Phase Switch                                                */
+            __IOM uint8_t WF  : 1;     /*!< [2..2] Output Phase Switch                                                */
+            __IOM uint8_t FB  : 1;     /*!< [3..3] External Feedback Signal Enable                                    */
+            __IOM uint8_t P   : 1;     /*!< [4..4] Positive-Phase Output (P) Control                                  */
+            __IOM uint8_t N   : 1;     /*!< [5..5] Negative-Phase Output (N) Control                                  */
+            __IOM uint8_t BDC : 1;     /*!< [6..6] Brushless DC Motor                                                 */
+            uint8_t           : 1;
+        } TGCRA_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TOCR1A;          /*!< (@ 0x0000020E) Timer Output Control Register 1A                           */
+
+        struct
+        {
+            __IOM uint8_t OLSP : 1;    /*!< [0..0] Output Level Select P                                              */
+            __IOM uint8_t OLSN : 1;    /*!< [1..1] Output Level Select N                                              */
+            __IOM uint8_t TOCS : 1;    /*!< [2..2] TOC Select                                                         */
+            __IOM uint8_t TOCL : 1;    /*!< [3..3] TOC Register Write Protection                                      */
+            uint8_t            : 2;
+            __IOM uint8_t PSYE : 1;    /*!< [6..6] PWM Synchronous Output Enable                                      */
+            uint8_t            : 1;
+        } TOCR1A_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TOCR2A;          /*!< (@ 0x0000020F) Timer Output Control Register 2A                           */
+
+        struct
+        {
+            __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
+            __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
+            __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
+            __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
+            __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
+            __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
+            __IOM uint8_t BF    : 2;   /*!< [7..6] TOLBR Buffer Transfer Timing Select                                */
+        } TOCR2A_b;
+    };
+    __IM uint16_t  RESERVED2[2];
+    __IOM uint16_t TCDRA;              /*!< (@ 0x00000214) Timer Cycle Data Register A                                */
+    __IOM uint16_t TDDRA;              /*!< (@ 0x00000216) Timer Dead Time Data Register A                            */
+    __IM uint16_t  RESERVED3[4];
+    __IM uint16_t  TCNTSA;             /*!< (@ 0x00000220) Timer Subcounter A                                         */
+    __IOM uint16_t TCBRA;              /*!< (@ 0x00000222) Timer Cycle Buffer Register A                              */
+    __IM uint16_t  RESERVED4[6];
+
+    union
+    {
+        __IOM uint8_t TITCR1A;         /*!< (@ 0x00000230) Timer Interrupt Skipping Set Register 1A                   */
+
+        struct
+        {
+            __IOM uint8_t T4VCOR : 3;  /*!< [2..0] TCIV4 Interrupt Skipping Count Setting                             */
+            __IOM uint8_t T4VEN  : 1;  /*!< [3..3] TCIV4 Interrupt Skipping Enable                                    */
+            __IOM uint8_t T3ACOR : 3;  /*!< [6..4] TGIA3 Interrupt Skipping Count Setting                             */
+            __IOM uint8_t T3AEN  : 1;  /*!< [7..7] TGIA3 Interrupt Skipping Enable                                    */
+        } TITCR1A_b;
+    };
+
+    union
+    {
+        __IM uint8_t TITCNT1A;         /*!< (@ 0x00000231) Timer Interrupt Skipping Counter 1A                        */
+
+        struct
+        {
+            __IM uint8_t T4VCNT : 3;   /*!< [2..0] TCIV4 Interrupt Counter                                            */
+            uint8_t             : 1;
+            __IM uint8_t T3ACNT : 3;   /*!< [6..4] TGIA3 Interrupt Counter                                            */
+            uint8_t             : 1;
+        } TITCNT1A_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TBTERA;          /*!< (@ 0x00000232) Timer Buffer Transfer Set Register A                       */
+
+        struct
+        {
+            __IOM uint8_t BTE : 2;     /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting        */
+            uint8_t           : 6;
+        } TBTERA_b;
+    };
+    __IM uint8_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t TDERA;           /*!< (@ 0x00000234) Timer Dead Time Enable Register A                          */
+
+        struct
+        {
+            __IOM uint8_t TDER : 1;    /*!< [0..0] Dead Time Enable                                                   */
+            uint8_t            : 7;
+        } TDERA_b;
+    };
+    __IM uint8_t RESERVED6;
+
+    union
+    {
+        __IOM uint8_t TOLBRA;          /*!< (@ 0x00000236) Timer Output Level Buffer Register A                       */
+
+        struct
+        {
+            __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
+            __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
+            __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
+            __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
+            __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
+            __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
+            uint8_t             : 2;
+        } TOLBRA_b;
+    };
+    __IM uint8_t  RESERVED7;
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IOM uint8_t TITMRA;          /*!< (@ 0x0000023A) Timer Interrupt Skipping Mode Register A                   */
+
+        struct
+        {
+            __IOM uint8_t TITM : 1;    /*!< [0..0] Interrupt Skipping Function Select                                 */
+            uint8_t            : 7;
+        } TITMRA_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TITCR2A;         /*!< (@ 0x0000023B) Timer Interrupt Skipping Set Register 2A                   */
+
+        struct
+        {
+            __IOM uint8_t TRG4COR : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Skipping Count Setting                     */
+            uint8_t               : 5;
+        } TITCR2A_b;
+    };
+
+    union
+    {
+        __IM uint8_t TITCNT2A;         /*!< (@ 0x0000023C) Timer Interrupt Skipping Counter 2A                        */
+
+        struct
+        {
+            __IM uint8_t TRG4CNT : 3;  /*!< [2..0] TRG4AN/TRG4BN Interrupt Counter                                    */
+            uint8_t              : 5;
+        } TITCNT2A_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10[17];
+
+    union
+    {
+        __IOM uint8_t TWCRA;           /*!< (@ 0x00000260) Timer Waveform Control Register A                          */
+
+        struct
+        {
+            __IOM uint8_t WRE : 1;     /*!< [0..0] Waveform Retain Enable                                             */
+            __IOM uint8_t SCC : 1;     /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB)                 */
+            uint8_t           : 5;
+            __IOM uint8_t CCE : 1;     /*!< [7..7] Compare Match Clear Enable                                         */
+        } TWCRA_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12[7];
+
+    union
+    {
+        __IOM uint8_t TMDR2A;          /*!< (@ 0x00000270) Timer Mode Register 2A                                     */
+
+        struct
+        {
+            __IOM uint8_t DRS : 1;     /*!< [0..0] Double Buffer Select                                               */
+            uint8_t           : 7;
+        } TMDR2A_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14[7];
+
+    union
+    {
+        __IOM uint8_t TSTRA;           /*!< (@ 0x00000280) Timer Start Register A                                     */
+
+        struct
+        {
+            __IOM uint8_t CST0 : 1;    /*!< [0..0] Counter Start 0                                                    */
+            __IOM uint8_t CST1 : 1;    /*!< [1..1] Counter Start 1                                                    */
+            __IOM uint8_t CST2 : 1;    /*!< [2..2] Counter Start 2                                                    */
+            __IOM uint8_t CST8 : 1;    /*!< [3..3] Counter Start 8                                                    */
+            uint8_t            : 2;
+            __IOM uint8_t CST3 : 1;    /*!< [6..6] Counter Start 3                                                    */
+            __IOM uint8_t CST4 : 1;    /*!< [7..7] Counter Start 4                                                    */
+        } TSTRA_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TSYRA;           /*!< (@ 0x00000281) Timer Synchronous Register A                               */
+
+        struct
+        {
+            __IOM uint8_t SYNC0 : 1;   /*!< [0..0] Timer Synchronous Operation 0                                      */
+            __IOM uint8_t SYNC1 : 1;   /*!< [1..1] Timer Synchronous Operation 1                                      */
+            __IOM uint8_t SYNC2 : 1;   /*!< [2..2] Timer Synchronous Operation 2                                      */
+            uint8_t             : 3;
+            __IOM uint8_t SYNC3 : 1;   /*!< [6..6] Timer Synchronous Operation 3                                      */
+            __IOM uint8_t SYNC4 : 1;   /*!< [7..7] Timer Synchronous Operation 4                                      */
+        } TSYRA_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCSYSTR;         /*!< (@ 0x00000282) Timer Counter Synchronous Start Register                   */
+
+        struct
+        {
+            __IOM uint8_t SCH7 : 1;    /*!< [0..0] Synchronous Start 7                                                */
+            __IOM uint8_t SCH6 : 1;    /*!< [1..1] Synchronous Start 6                                                */
+            uint8_t            : 1;
+            __IOM uint8_t SCH4 : 1;    /*!< [3..3] Synchronous Start 4                                                */
+            __IOM uint8_t SCH3 : 1;    /*!< [4..4] Synchronous Start 3                                                */
+            __IOM uint8_t SCH2 : 1;    /*!< [5..5] Synchronous Start 2                                                */
+            __IOM uint8_t SCH1 : 1;    /*!< [6..6] Synchronous Start 1                                                */
+            __IOM uint8_t SCH0 : 1;    /*!< [7..7] Synchronous Start 0                                                */
+        } TCSYSTR_b;
+    };
+    __IM uint8_t RESERVED15;
+
+    union
+    {
+        __IOM uint8_t TRWERA;          /*!< (@ 0x00000284) Timer Read/Write Enable Register A                         */
+
+        struct
+        {
+            __IOM uint8_t RWE : 1;     /*!< [0..0] Read/Write Enable                                                  */
+            uint8_t           : 7;
+        } TRWERA_b;
+    };
+    __IM uint8_t  RESERVED16;
+    __IM uint16_t RESERVED17[962];
+
+    union
+    {
+        __IOM uint8_t TOERB;           /*!< (@ 0x00000A0A) Timer Output Master Enable Register B                      */
+
+        struct
+        {
+            __IOM uint8_t OE6B : 1;    /*!< [0..0] Master Enable MTIOC6B                                              */
+            __IOM uint8_t OE7A : 1;    /*!< [1..1] Master Enable MTIOC7A                                              */
+            __IOM uint8_t OE7B : 1;    /*!< [2..2] Master Enable MTIOC7B                                              */
+            __IOM uint8_t OE6D : 1;    /*!< [3..3] Master Enable MTIOC6D                                              */
+            __IOM uint8_t OE7C : 1;    /*!< [4..4] Master Enable MTIOC7C                                              */
+            __IOM uint8_t OE7D : 1;    /*!< [5..5] Master Enable MTIOC7D                                              */
+            uint8_t            : 2;
+        } TOERB_b;
+    };
+    __IM uint8_t  RESERVED18;
+    __IM uint16_t RESERVED19;
+
+    union
+    {
+        __IOM uint8_t TOCR1B;          /*!< (@ 0x00000A0E) Timer Output Control Register 1B                           */
+
+        struct
+        {
+            __IOM uint8_t OLSP : 1;    /*!< [0..0] Output Level Select P                                              */
+            __IOM uint8_t OLSN : 1;    /*!< [1..1] Output Level Select N                                              */
+            __IOM uint8_t TOCS : 1;    /*!< [2..2] TOC Select                                                         */
+            __IOM uint8_t TOCL : 1;    /*!< [3..3] TOC Register Write Protection                                      */
+            uint8_t            : 2;
+            __IOM uint8_t PSYE : 1;    /*!< [6..6] PWM Synchronous Output Enable                                      */
+            uint8_t            : 1;
+        } TOCR1B_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TOCR2B;          /*!< (@ 0x00000A0F) Timer Output Control Register 2B                           */
+
+        struct
+        {
+            __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
+            __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
+            __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
+            __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
+            __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
+            __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
+            __IOM uint8_t BF    : 2;   /*!< [7..6] TOLBR Buffer Transfer Timing Select                                */
+        } TOCR2B_b;
+    };
+    __IM uint16_t  RESERVED20[2];
+    __IOM uint16_t TCDRB;              /*!< (@ 0x00000A14) Timer Cycle Data Register B                                */
+    __IOM uint16_t TDDRB;              /*!< (@ 0x00000A16) Timer Dead Time Data Register B                            */
+    __IM uint16_t  RESERVED21[4];
+    __IM uint16_t  TCNTSB;             /*!< (@ 0x00000A20) Timer Subcounter B                                         */
+    __IOM uint16_t TCBRB;              /*!< (@ 0x00000A22) Timer Cycle Buffer Register B                              */
+    __IM uint16_t  RESERVED22[6];
+
+    union
+    {
+        __IOM uint8_t TITCR1B;         /*!< (@ 0x00000A30) Timer Interrupt Skipping Set Register 1B                   */
+
+        struct
+        {
+            __IOM uint8_t T7VCOR : 3;  /*!< [2..0] TCIV7 Interrupt Skipping Count Setting                             */
+            __IOM uint8_t T7VEN  : 1;  /*!< [3..3] TCIV7 Interrupt Skipping Enable                                    */
+            __IOM uint8_t T6ACOR : 3;  /*!< [6..4] TGIA6 Interrupt Skipping Count Setting                             */
+            __IOM uint8_t T6AEN  : 1;  /*!< [7..7] TGIA6 Interrupt Skipping Enable                                    */
+        } TITCR1B_b;
+    };
+
+    union
+    {
+        __IM uint8_t TITCNT1B;         /*!< (@ 0x00000A31) Timer Interrupt Skipping Counter 1B                        */
+
+        struct
+        {
+            __IM uint8_t T7VCNT : 3;   /*!< [2..0] TCIV7 Interrupt Counter                                            */
+            uint8_t             : 1;
+            __IM uint8_t T6ACNT : 3;   /*!< [6..4] TGIA6 Interrupt Counter                                            */
+            uint8_t             : 1;
+        } TITCNT1B_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TBTERB;          /*!< (@ 0x00000A32) Timer Buffer Transfer Set Register B                       */
+
+        struct
+        {
+            __IOM uint8_t BTE : 2;     /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting        */
+            uint8_t           : 6;
+        } TBTERB_b;
+    };
+    __IM uint8_t RESERVED23;
+
+    union
+    {
+        __IOM uint8_t TDERB;           /*!< (@ 0x00000A34) Timer Dead Time Enable Register B                          */
+
+        struct
+        {
+            __IOM uint8_t TDER : 1;    /*!< [0..0] Dead Time Enable                                                   */
+            uint8_t            : 7;
+        } TDERB_b;
+    };
+    __IM uint8_t RESERVED24;
+
+    union
+    {
+        __IOM uint8_t TOLBRB;          /*!< (@ 0x00000A36) Timer Output Level Buffer Register B                       */
+
+        struct
+        {
+            __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
+            __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
+            __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
+            __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
+            __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
+            __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
+            uint8_t             : 2;
+        } TOLBRB_b;
+    };
+    __IM uint8_t  RESERVED25;
+    __IM uint16_t RESERVED26;
+
+    union
+    {
+        __IOM uint8_t TITMRB;          /*!< (@ 0x00000A3A) Timer Interrupt Skipping Mode Register B                   */
+
+        struct
+        {
+            __IOM uint8_t TITM : 1;    /*!< [0..0] Interrupt Skipping Function Select                                 */
+            uint8_t            : 7;
+        } TITMRB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TITCR2B;         /*!< (@ 0x00000A3B) Timer Interrupt Skipping Set Register 2B                   */
+
+        struct
+        {
+            __IOM uint8_t TRG7COR : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Skipping Count Setting                     */
+            uint8_t               : 5;
+        } TITCR2B_b;
+    };
+
+    union
+    {
+        __IM uint8_t TITCNT2B;         /*!< (@ 0x00000A3C) Timer Interrupt Skipping Counter 2B                        */
+
+        struct
+        {
+            __IM uint8_t TRG7CNT : 3;  /*!< [2..0] TRG7AN/TRG7BN Interrupt Counter                                    */
+            uint8_t              : 5;
+        } TITCNT2B_b;
+    };
+    __IM uint8_t  RESERVED27;
+    __IM uint16_t RESERVED28[17];
+
+    union
+    {
+        __IOM uint8_t TWCRB;           /*!< (@ 0x00000A60) Timer Waveform Control Register B                          */
+
+        struct
+        {
+            __IOM uint8_t WRE : 1;     /*!< [0..0] Waveform Retain Enable                                             */
+            __IOM uint8_t SCC : 1;     /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB)                 */
+            uint8_t           : 5;
+            __IOM uint8_t CCE : 1;     /*!< [7..7] Compare Match Clear Enable                                         */
+        } TWCRB_b;
+    };
+    __IM uint8_t  RESERVED29;
+    __IM uint16_t RESERVED30[7];
+
+    union
+    {
+        __IOM uint8_t TMDR2B;          /*!< (@ 0x00000A70) Timer Mode Register 2B                                     */
+
+        struct
+        {
+            __IOM uint8_t DRS : 1;     /*!< [0..0] Double Buffer Select                                               */
+            uint8_t           : 7;
+        } TMDR2B_b;
+    };
+    __IM uint8_t  RESERVED31;
+    __IM uint16_t RESERVED32[7];
+
+    union
+    {
+        __IOM uint8_t TSTRB;           /*!< (@ 0x00000A80) Timer Start Register B                                     */
+
+        struct
+        {
+            uint8_t            : 6;
+            __IOM uint8_t CST6 : 1;    /*!< [6..6] Counter Start 6                                                    */
+            __IOM uint8_t CST7 : 1;    /*!< [7..7] Counter Start 7                                                    */
+        } TSTRB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TSYRB;           /*!< (@ 0x00000A81) Timer Synchronous Register B                               */
+
+        struct
+        {
+            uint8_t             : 6;
+            __IOM uint8_t SYNC6 : 1;   /*!< [6..6] Timer Synchronous Operation 6                                      */
+            __IOM uint8_t SYNC7 : 1;   /*!< [7..7] Timer Synchronous Operation 7                                      */
+        } TSYRB_b;
+    };
+    __IM uint16_t RESERVED33;
+
+    union
+    {
+        __IOM uint8_t TRWERB;          /*!< (@ 0x00000A84) Timer Read/Write Enable Register B                         */
+
+        struct
+        {
+            __IOM uint8_t RWE : 1;     /*!< [0..0] Read/Write Enable                                                  */
+            uint8_t           : 7;
+        } TRWERB_b;
+    };
+    __IM uint8_t  RESERVED34;
+    __IM uint16_t RESERVED35;
+} R_MTU_Type;                          /*!< Size = 2696 (0xa88)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU3                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 3 (R_MTU3)
+ */
+
+typedef struct                         /*!< (@ 0x90001100) R_MTU3 Structure                                           */
+{
+    __IM uint16_t RESERVED[128];
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000100) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000102) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000104) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000105) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000108) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 2;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint8_t   RESERVED4;
+    __IM uint16_t  RESERVED5[3];
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000110) Timer Counter                                              */
+    __IM uint16_t  RESERVED6[3];
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000118) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000011A) Timer General Register B                                   */
+    __IM uint16_t  RESERVED7[4];
+    __IOM uint16_t TGRC;               /*!< (@ 0x00000124) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x00000126) Timer General Register D                                   */
+    __IM uint16_t  RESERVED8[2];
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x0000012C) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10[5];
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            uint8_t            : 6;
+        } TBTM_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12[9];
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000014C) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint8_t   RESERVED13;
+    __IM uint16_t  RESERVED14[18];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000172) Timer General Register E                                   */
+} R_MTU3_Type;                         /*!< Size = 372 (0x174)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU4                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 4 (R_MTU4)
+ */
+
+typedef struct                         /*!< (@ 0x90001200) R_MTU4 Structure                                           */
+{
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000001) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000003) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000006) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000007) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000009) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 1;
+            __IOM uint8_t TTGE2 : 1;   /*!< [6..6] A/D Converter Start Request Enable 2                               */
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint16_t  RESERVED4[4];
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000012) Timer Counter                                              */
+    __IM uint16_t  RESERVED5[4];
+    __IOM uint16_t TGRA;               /*!< (@ 0x0000001C) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000001E) Timer General Register B                                   */
+    __IM uint16_t  RESERVED6[4];
+    __IOM uint16_t TGRC;               /*!< (@ 0x00000028) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x0000002A) Timer General Register D                                   */
+    __IM uint8_t   RESERVED7;
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x0000002D) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IM uint16_t RESERVED8[5];
+    __IM uint8_t  RESERVED9;
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            uint8_t            : 6;
+        } TBTM_b;
+    };
+    __IM uint16_t RESERVED10[3];
+
+    union
+    {
+        __IOM uint16_t TADCR;          /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register         */
+
+        struct
+        {
+            __IOM uint16_t ITB4VE : 1; /*!< [0..0] TCIV4 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITB3AE : 1; /*!< [1..1] TGIA3 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITA4VE : 1; /*!< [2..2] TCIV4 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITA3AE : 1; /*!< [3..3] TGIA3 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t DT4BE  : 1; /*!< [4..4] Down-Count TRG4BN Enable                                           */
+            __IOM uint16_t UT4BE  : 1; /*!< [5..5] Up-Count TRG4BN Enable                                             */
+            __IOM uint16_t DT4AE  : 1; /*!< [6..6] Down-Count TRG4AN Enable                                           */
+            __IOM uint16_t UT4AE  : 1; /*!< [7..7] Up-Count TRG4AN Enable                                             */
+            uint16_t              : 6;
+            __IOM uint16_t BF     : 2; /*!< [15..14] MTU4.TADCOBRA/TADCOBRB Transfer Timing Select                    */
+        } TADCR_b;
+    };
+    __IM uint16_t  RESERVED11;
+    __IOM uint16_t TADCORA;            /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register
+                                        *                  A                                                          */
+    __IOM uint16_t TADCORB;            /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register
+                                        *                  B                                                          */
+    __IOM uint16_t TADCOBRA;           /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer
+                                        *                  Register A                                                 */
+    __IOM uint16_t TADCOBRB;           /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer
+                                        *                  Register B                                                 */
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000004D) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint16_t  RESERVED13[19];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000074) Timer General Register E                                   */
+    __IOM uint16_t TGRF;               /*!< (@ 0x00000076) Timer General Register F                                   */
+} R_MTU4_Type;                         /*!< Size = 120 (0x78)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MTU_NF                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Noise Filter (R_MTU_NF)
+ */
+
+typedef struct                         /*!< (@ 0x90001290) R_MTU_NF Structure                                         */
+{
+    union
+    {
+        __IOM uint8_t NFCR0;           /*!< (@ 0x00000000) Noise Filter Control Register 0                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR1;           /*!< (@ 0x00000001) Noise Filter Control Register 1                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            uint8_t             : 2;
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR2;           /*!< (@ 0x00000002) Noise Filter Control Register 2                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            uint8_t             : 2;
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR3;           /*!< (@ 0x00000003) Noise Filter Control Register 3                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR4;           /*!< (@ 0x00000004) Noise Filter Control Register 4                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR4_b;
+    };
+    __IM uint8_t RESERVED[3];
+
+    union
+    {
+        __IOM uint8_t NFCR8;           /*!< (@ 0x00000008) Noise Filter Control Register 8                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR8_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCRC;           /*!< (@ 0x00000009) Noise Filter Control Register C                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCRC_b;
+    };
+    __IM uint8_t RESERVED1[2041];
+
+    union
+    {
+        __IOM uint8_t NFCR6;           /*!< (@ 0x00000803) Noise Filter Control Register 6                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR6_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR7;           /*!< (@ 0x00000804) Noise Filter Control Register 7                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR7_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR5;           /*!< (@ 0x00000805) Noise Filter Control Register 5                            */
+
+        struct
+        {
+            __IOM uint8_t NFUEN : 1;   /*!< [0..0] Noise Filter U Enable                                              */
+            __IOM uint8_t NFVEN : 1;   /*!< [1..1] Noise Filter V Enable                                              */
+            __IOM uint8_t NFWEN : 1;   /*!< [2..2] Noise Filter W Enable                                              */
+            uint8_t             : 1;
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR5_b;
+    };
+} R_MTU_NF_Type;                       /*!< Size = 2054 (0x806)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 0 (R_MTU0)
+ */
+
+typedef struct                         /*!< (@ 0x90001300) R_MTU0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            __IOM uint8_t BFE : 1;     /*!< [6..6] Buffer Operation E                                                 */
+            uint8_t           : 1;
+        } TMDR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000002) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000003) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 2;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint8_t   RESERVED;
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
+    __IOM uint16_t TGRC;               /*!< (@ 0x0000000C) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x0000000E) Timer General Register D                                   */
+    __IM uint16_t  RESERVED1[8];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000020) Timer General Register E                                   */
+    __IOM uint16_t TGRF;               /*!< (@ 0x00000022) Timer General Register F                                   */
+
+    union
+    {
+        __IOM uint8_t TIER2;           /*!< (@ 0x00000024) Timer Interrupt Enable Register 2                          */
+
+        struct
+        {
+            __IOM uint8_t TGIEE : 1;   /*!< [0..0] TGR Interrupt Enable E                                             */
+            __IOM uint8_t TGIEF : 1;   /*!< [1..1] TGR Interrupt Enable F                                             */
+            uint8_t             : 5;
+            __IOM uint8_t TTGE2 : 1;   /*!< [7..7] A/D Converter Start Request Enable 2                               */
+        } TIER2_b;
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000026) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            __IOM uint8_t TTSE : 1;    /*!< [2..2] Timing Select E                                                    */
+            uint8_t            : 5;
+        } TBTM_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x00000028) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint8_t  RESERVED4;
+    __IM uint16_t RESERVED5;
+} R_MTU0_Type;                         /*!< Size = 44 (0x2c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU1                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 1 (R_MTU1)
+ */
+
+typedef struct                         /*!< (@ 0x90001380) R_MTU1 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD : 4;      /*!< [3..0] Mode Select                                                        */
+            uint8_t          : 4;
+        } TMDR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIOR;            /*!< (@ 0x00000002) Timer I/O Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIOR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            uint8_t             : 2;
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            __IOM uint8_t TCIEU : 1;   /*!< [5..5] Underflow Interrupt Enable                                         */
+            uint8_t             : 1;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x00000005) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
+    __IM uint32_t  RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TICCR;           /*!< (@ 0x00000010) Timer Input Capture Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t I1AE : 1;    /*!< [0..0] Input Capture Enable                                               */
+            __IOM uint8_t I1BE : 1;    /*!< [1..1] Input Capture Enable                                               */
+            __IOM uint8_t I2AE : 1;    /*!< [2..2] Input Capture Enable                                               */
+            __IOM uint8_t I2BE : 1;    /*!< [3..3] Input Capture Enable                                               */
+            uint8_t            : 4;
+        } TICCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR3;           /*!< (@ 0x00000011) Timer Mode Register 3                                      */
+
+        struct
+        {
+            __IOM uint8_t LWA     : 1; /*!< [0..0] MTU1/MTU2 Combination Longword Access Control                      */
+            __IOM uint8_t PHCKSEL : 1; /*!< [1..1] External Input Phase Clock Select                                  */
+            uint8_t               : 6;
+        } TMDR3_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x00000014) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t PCB   : 2;   /*!< [4..3] Functional Expansion Control for Phase Counting Modes
+                                        *   2, 3, and 5                                                               */
+            uint8_t : 3;
+        } TCR2_b;
+    };
+    __IM uint8_t   RESERVED3;
+    __IM uint16_t  RESERVED4;
+    __IM uint32_t  RESERVED5[2];
+    __IOM uint32_t TCNTLW;             /*!< (@ 0x00000020) Timer Longword Counter                                     */
+    __IOM uint32_t TGRALW;             /*!< (@ 0x00000024) Timer Longword General Register A                          */
+    __IOM uint32_t TGRBLW;             /*!< (@ 0x00000028) Timer Longword General Register B                          */
+} R_MTU1_Type;                         /*!< Size = 44 (0x2c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU2                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 2 (R_MTU2)
+ */
+
+typedef struct                         /*!< (@ 0x90001400) R_MTU2 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD : 4;      /*!< [3..0] Mode Select                                                        */
+            uint8_t          : 4;
+        } TMDR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIOR;            /*!< (@ 0x00000002) Timer I/O Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIOR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            uint8_t             : 2;
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            __IOM uint8_t TCIEU : 1;   /*!< [5..5] Underflow Interrupt Enable                                         */
+            uint8_t             : 1;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x00000005) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000000C) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t PCB   : 2;   /*!< [4..3] Functional Expansion Control for Phase Counting Modes
+                                        *   2, 3, and 5                                                               */
+            uint8_t : 3;
+        } TCR2_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+} R_MTU2_Type;                         /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU8                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 8 (R_MTU8)
+ */
+
+typedef struct                         /*!< (@ 0x90001600) R_MTU8 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000002) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000003) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 3;
+        } TIER_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x00000006) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint8_t   RESERVED1;
+    __IOM uint32_t TCNT;               /*!< (@ 0x00000008) Timer Counter                                              */
+    __IOM uint32_t TGRA;               /*!< (@ 0x0000000C) Timer General Register A                                   */
+    __IOM uint32_t TGRB;               /*!< (@ 0x00000010) Timer General Register B                                   */
+    __IOM uint32_t TGRC;               /*!< (@ 0x00000014) Timer General Register C                                   */
+    __IOM uint32_t TGRD;               /*!< (@ 0x00000018) Timer General Register D                                   */
+} R_MTU8_Type;                         /*!< Size = 28 (0x1c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU6                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 6 (R_MTU6)
+ */
+
+typedef struct                         /*!< (@ 0x90001900) R_MTU6 Structure                                           */
+{
+    __IM uint16_t RESERVED[128];
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000100) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000102) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000104) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000105) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000108) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 2;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint8_t   RESERVED4;
+    __IM uint16_t  RESERVED5[3];
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000110) Timer Counter                                              */
+    __IM uint16_t  RESERVED6[3];
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000118) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000011A) Timer General Register B                                   */
+    __IM uint16_t  RESERVED7[4];
+    __IOM uint16_t TGRC;               /*!< (@ 0x00000124) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x00000126) Timer General Register D                                   */
+    __IM uint16_t  RESERVED8[2];
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x0000012C) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10[5];
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            uint8_t            : 6;
+        } TBTM_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12[9];
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000014C) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t TSYCR;           /*!< (@ 0x00000150) Timer Synchronous Clear Register                           */
+
+        struct
+        {
+            __IOM uint8_t CE2B : 1;    /*!< [0..0] Clear Enable 2B                                                    */
+            __IOM uint8_t CE2A : 1;    /*!< [1..1] Clear Enable 2A                                                    */
+            __IOM uint8_t CE1B : 1;    /*!< [2..2] Clear Enable 1B                                                    */
+            __IOM uint8_t CE1A : 1;    /*!< [3..3] Clear Enable 1A                                                    */
+            __IOM uint8_t CE0D : 1;    /*!< [4..4] Clear Enable 0D                                                    */
+            __IOM uint8_t CE0C : 1;    /*!< [5..5] Clear Enable 0C                                                    */
+            __IOM uint8_t CE0B : 1;    /*!< [6..6] Clear Enable 0B                                                    */
+            __IOM uint8_t CE0A : 1;    /*!< [7..7] Clear Enable 0A                                                    */
+        } TSYCR_b;
+    };
+    __IM uint8_t   RESERVED15;
+    __IM uint16_t  RESERVED16[16];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000172) Timer General Register E                                   */
+} R_MTU6_Type;                         /*!< Size = 372 (0x174)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU7                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 7 (R_MTU7)
+ */
+
+typedef struct                         /*!< (@ 0x90001A00) R_MTU7 Structure                                           */
+{
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000001) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000003) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000006) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000007) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000009) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 1;
+            __IOM uint8_t TTGE2 : 1;   /*!< [6..6] A/D Converter Start Request Enable 2                               */
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint16_t  RESERVED4[4];
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000012) Timer Counter                                              */
+    __IM uint16_t  RESERVED5[4];
+    __IOM uint16_t TGRA;               /*!< (@ 0x0000001C) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000001E) Timer General Register B                                   */
+    __IM uint16_t  RESERVED6[4];
+    __IOM uint16_t TGRC;               /*!< (@ 0x00000028) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x0000002A) Timer General Register D                                   */
+    __IM uint8_t   RESERVED7;
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x0000002D) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IM uint16_t RESERVED8[5];
+    __IM uint8_t  RESERVED9;
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            uint8_t            : 6;
+        } TBTM_b;
+    };
+    __IM uint16_t RESERVED10[3];
+
+    union
+    {
+        __IOM uint16_t TADCR;          /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register         */
+
+        struct
+        {
+            __IOM uint16_t ITB7VE : 1; /*!< [0..0] TCIV7 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITB6AE : 1; /*!< [1..1] TGIA6 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITA7VE : 1; /*!< [2..2] TCIV7 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITA6AE : 1; /*!< [3..3] TGIA6 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t DT7BE  : 1; /*!< [4..4] Down-Count TRG7BN Enable                                           */
+            __IOM uint16_t UT7BE  : 1; /*!< [5..5] Up-Count TRG7BN Enable                                             */
+            __IOM uint16_t DT7AE  : 1; /*!< [6..6] Down-Count TRG7AN Enable                                           */
+            __IOM uint16_t UT7AE  : 1; /*!< [7..7] Up-Count TRG7AN Enable                                             */
+            uint16_t              : 6;
+            __IOM uint16_t BF     : 2; /*!< [15..14] MTU7.TADCOBRA/TADCOBRB Transfer Timing Select                    */
+        } TADCR_b;
+    };
+    __IM uint16_t  RESERVED11;
+    __IOM uint16_t TADCORA;            /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register
+                                        *                  A                                                          */
+    __IOM uint16_t TADCORB;            /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register
+                                        *                  B                                                          */
+    __IOM uint16_t TADCOBRA;           /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer
+                                        *                  Register A                                                 */
+    __IOM uint16_t TADCOBRB;           /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer
+                                        *                  Register B                                                 */
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000004D) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint16_t  RESERVED13[19];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000074) Timer General Register E                                   */
+    __IOM uint16_t TGRF;               /*!< (@ 0x00000076) Timer General Register F                                   */
+} R_MTU7_Type;                         /*!< Size = 120 (0x78)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU5                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 5 (R_MTU5)
+ */
+
+typedef struct                         /*!< (@ 0x90001C00) R_MTU5 Structure                                           */
+{
+    __IM uint16_t  RESERVED[64];
+    __IOM uint16_t TCNTU;              /*!< (@ 0x00000080) Timer Counter U                                            */
+    __IOM uint16_t TGRU;               /*!< (@ 0x00000082) Timer General Register U                                   */
+
+    union
+    {
+        __IOM uint8_t TCRU;            /*!< (@ 0x00000084) Timer Control Register U                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
+            uint8_t            : 6;
+        } TCRU_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCR2U;           /*!< (@ 0x00000085) Timer Control Register 2U                                  */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
+            uint8_t             : 3;
+        } TCR2U_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORU;           /*!< (@ 0x00000086) Timer I/O Control Register U                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
+            uint8_t           : 3;
+        } TIORU_b;
+    };
+    __IM uint8_t   RESERVED1;
+    __IM uint16_t  RESERVED2[4];
+    __IOM uint16_t TCNTV;              /*!< (@ 0x00000090) Timer Counter V                                            */
+    __IOM uint16_t TGRV;               /*!< (@ 0x00000092) Timer General Register V                                   */
+
+    union
+    {
+        __IOM uint8_t TCRV;            /*!< (@ 0x00000094) Timer Control Register V                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
+            uint8_t            : 6;
+        } TCRV_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCR2V;           /*!< (@ 0x00000095) Timer Control Register 2V                                  */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
+            uint8_t             : 3;
+        } TCR2V_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORV;           /*!< (@ 0x00000096) Timer I/O Control Register V                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
+            uint8_t           : 3;
+        } TIORV_b;
+    };
+    __IM uint8_t   RESERVED3;
+    __IM uint16_t  RESERVED4[4];
+    __IOM uint16_t TCNTW;              /*!< (@ 0x000000A0) Timer Counter W                                            */
+    __IOM uint16_t TGRW;               /*!< (@ 0x000000A2) Timer General Register W                                   */
+
+    union
+    {
+        __IOM uint8_t TCRW;            /*!< (@ 0x000000A4) Timer Control Register W                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
+            uint8_t            : 6;
+        } TCRW_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCR2W;           /*!< (@ 0x000000A5) Timer Control Register 2W                                  */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
+            uint8_t             : 3;
+        } TCR2W_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORW;           /*!< (@ 0x000000A6) Timer I/O Control Register W                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
+            uint8_t           : 3;
+        } TIORW_b;
+    };
+    __IM uint8_t  RESERVED5;
+    __IM uint16_t RESERVED6[5];
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x000000B2) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIE5W : 1;  /*!< [0..0] TGR Interrupt Enable 5W                                            */
+            __IOM uint8_t TGIE5V : 1;  /*!< [1..1] TGR Interrupt Enable 5V                                            */
+            __IOM uint8_t TGIE5U : 1;  /*!< [2..2] TGR Interrupt Enable 5U                                            */
+            uint8_t              : 5;
+        } TIER_b;
+    };
+    __IM uint8_t RESERVED7;
+
+    union
+    {
+        __IOM uint8_t TSTR;            /*!< (@ 0x000000B4) Timer Start Register                                       */
+
+        struct
+        {
+            __IOM uint8_t CSTW5 : 1;   /*!< [0..0] Counter Start W5                                                   */
+            __IOM uint8_t CSTV5 : 1;   /*!< [1..1] Counter Start V5                                                   */
+            __IOM uint8_t CSTU5 : 1;   /*!< [2..2] Counter Start U5                                                   */
+            uint8_t             : 5;
+        } TSTR_b;
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        __IOM uint8_t TCNTCMPCLR;       /*!< (@ 0x000000B6) Timer Compare Match Clear Register                         */
+
+        struct
+        {
+            __IOM uint8_t CMPCLR5W : 1; /*!< [0..0] TCNT Compare Clear 5W                                              */
+            __IOM uint8_t CMPCLR5V : 1; /*!< [1..1] TCNT Compare Clear 5V                                              */
+            __IOM uint8_t CMPCLR5U : 1; /*!< [2..2] TCNT Compare Clear 5U                                              */
+            uint8_t                : 5;
+        } TCNTCMPCLR_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10;
+} R_MTU5_Type;                         /*!< Size = 186 (0xba)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TFU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Trigonometric Function Unit (R_TFU)
+ */
+
+typedef struct                         /*!< (@ 0x90003000) R_TFU Structure                                            */
+{
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IM uint8_t TRGSTS;           /*!< (@ 0x00000008) Trigonometric Status Register                              */
+
+        struct
+        {
+            __IM uint8_t BSYF : 1;     /*!< [0..0] Calculation in progress flag                                       */
+            __IM uint8_t ERRF : 1;     /*!< [1..1] Input error flag                                                   */
+            uint8_t           : 6;
+        } TRGSTS_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM float SCDT0;             /*!< (@ 0x00000010) Sine Cosine Data Register 0                                */
+
+        struct
+        {
+            __IOM uint32_t SCDT0 : 32; /*!< [31..0] Sine Cosine Data Register 0 (single-precision floating-point)     */
+        } SCDT0_b;
+    };
+
+    union
+    {
+        __IOM float SCDT1;             /*!< (@ 0x00000014) Sine Cosine Data Register 1                                */
+
+        struct
+        {
+            __IOM uint32_t SCDT1 : 32; /*!< [31..0] Sine Cosine Data Register 1 (single-precision floating-point)     */
+        } SCDT1_b;
+    };
+
+    union
+    {
+        __IOM float ATDT0;             /*!< (@ 0x00000018) Arctangent Data Register 0                                 */
+
+        struct
+        {
+            __IOM uint32_t ATDT0 : 32; /*!< [31..0] Arctangent Data Register 0 (single-precision floating-point)      */
+        } ATDT0_b;
+    };
+
+    union
+    {
+        __IOM float ATDT1;             /*!< (@ 0x0000001C) Arctangent Data Register 1                                 */
+
+        struct
+        {
+            __IOM uint32_t ATDT1 : 32; /*!< [31..0] Arctangent Data Register 1 (single-precision floating-point)      */
+        } ATDT1_b;
+    };
+} R_TFU_Type;                          /*!< Size = 32 (0x20)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POE3                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Port Output Enable 3 (R_POE3)
+ */
+
+typedef struct                         /*!< (@ 0x90005000) R_POE3 Structure                                           */
+{
+    union
+    {
+        __IOM uint16_t ICSR1;          /*!< (@ 0x00000000) Input Level Control/Status Register 1                      */
+
+        struct
+        {
+            __IOM uint16_t POE0M : 2;  /*!< [1..0] POE0 Mode Select                                                   */
+            uint16_t             : 6;
+            __IOM uint16_t PIE1  : 1;  /*!< [8..8] Port Interrupt Enable 1                                            */
+            uint16_t             : 3;
+            __IOM uint16_t POE0F : 1;  /*!< [12..12] POE0 Flag                                                        */
+            uint16_t             : 3;
+        } ICSR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t OCSR1;          /*!< (@ 0x00000002) Output Level Control/Status Register 1                     */
+
+        struct
+        {
+            uint16_t            : 8;
+            __IOM uint16_t OIE1 : 1;   /*!< [8..8] Output Short Circuit Interrupt Enable 1                            */
+            __IOM uint16_t OCE1 : 1;   /*!< [9..9] Output Short Circuit High-Impedance Enable 1                       */
+            uint16_t            : 5;
+            __IOM uint16_t OSF1 : 1;   /*!< [15..15] Output Short Circuit Flag 1                                      */
+        } OCSR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR2;          /*!< (@ 0x00000004) Input Level Control/Status Register 2                      */
+
+        struct
+        {
+            __IOM uint16_t POE4M : 2;  /*!< [1..0] POE4 Mode Select                                                   */
+            uint16_t             : 6;
+            __IOM uint16_t PIE2  : 1;  /*!< [8..8] Port Interrupt Enable 2                                            */
+            uint16_t             : 3;
+            __IOM uint16_t POE4F : 1;  /*!< [12..12] POE4 Flag                                                        */
+            uint16_t             : 3;
+        } ICSR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t OCSR2;          /*!< (@ 0x00000006) Output Level Control/Status Register 2                     */
+
+        struct
+        {
+            uint16_t            : 8;
+            __IOM uint16_t OIE2 : 1;   /*!< [8..8] Output Short Circuit Interrupt Enable 2                            */
+            __IOM uint16_t OCE2 : 1;   /*!< [9..9] Output Short Circuit High-Impedance Enable 2                       */
+            uint16_t            : 5;
+            __IOM uint16_t OSF2 : 1;   /*!< [15..15] Output Short Circuit Flag 2                                      */
+        } OCSR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR3;          /*!< (@ 0x00000008) Input Level Control/Status Register 3                      */
+
+        struct
+        {
+            __IOM uint16_t POE8M : 2;  /*!< [1..0] POE8 Mode Select                                                   */
+            uint16_t             : 6;
+            __IOM uint16_t PIE3  : 1;  /*!< [8..8] Port Interrupt Enable 3                                            */
+            __IOM uint16_t POE8E : 1;  /*!< [9..9] POE8 High-Impedance Enable                                         */
+            uint16_t             : 2;
+            __IOM uint16_t POE8F : 1;  /*!< [12..12] POE8 Flag                                                        */
+            uint16_t             : 3;
+        } ICSR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPOER;              /*!< (@ 0x0000000A) Software Port Output Enable Register                       */
+
+        struct
+        {
+            __IOM uint8_t MTUCH34HIZ : 1; /*!< [0..0] MTU3 and MTU4 Output High-Impedance Enable                         */
+            __IOM uint8_t MTUCH67HIZ : 1; /*!< [1..1] MTU6 and MTU7 Output High-Impedance Enable                         */
+            __IOM uint8_t MTUCH0HIZ  : 1; /*!< [2..2] MTU0 Pin High-Impedance Enable                                     */
+            uint8_t                  : 5;
+        } SPOER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t POECR1;          /*!< (@ 0x0000000B) Port Output Enable Control Register 1                      */
+
+        struct
+        {
+            __IOM uint8_t MTU0AZE : 1; /*!< [0..0] MTIOC0A High-Impedance Enable                                      */
+            __IOM uint8_t MTU0BZE : 1; /*!< [1..1] MTIOC0B High-Impedance Enable                                      */
+            __IOM uint8_t MTU0CZE : 1; /*!< [2..2] MTIOC0C High-Impedance Enable                                      */
+            __IOM uint8_t MTU0DZE : 1; /*!< [3..3] MTIOC0D High-Impedance Enable                                      */
+            uint8_t               : 4;
+        } POECR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR2;           /*!< (@ 0x0000000C) Port Output Enable Control Register 2                      */
+
+        struct
+        {
+            __IOM uint16_t MTU7BDZE : 1; /*!< [0..0] MTIOC7B/MTIOC7D High-Impedance Enable                              */
+            __IOM uint16_t MTU7ACZE : 1; /*!< [1..1] MTIOC7A/MTIOC7C High-Impedance Enable                              */
+            __IOM uint16_t MTU6BDZE : 1; /*!< [2..2] MTIOC6B/MTIOC6D High-Impedance Enable                              */
+            uint16_t                : 5;
+            __IOM uint16_t MTU4BDZE : 1; /*!< [8..8] MTIOC4B/MTIOC4D High-Impedance Enable                              */
+            __IOM uint16_t MTU4ACZE : 1; /*!< [9..9] MTIOC4A/MTIOC4C High-Impedance Enable                              */
+            __IOM uint16_t MTU3BDZE : 1; /*!< [10..10] MTIOC3B/MTIOC3D High-Impedance Enable                            */
+            uint16_t                : 5;
+        } POECR2_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t POECR4;         /*!< (@ 0x00000010) Port Output Enable Control Register 4                      */
+
+        struct
+        {
+            uint16_t                    : 2;
+            __IOM uint16_t IC2ADDMT34ZE : 1; /*!< [2..2] MTU3 and MTU4 High-Impedance POE4F Add                             */
+            __IOM uint16_t IC3ADDMT34ZE : 1; /*!< [3..3] MTU3 and MTU4 High-Impedance POE8F Add                             */
+            __IOM uint16_t IC4ADDMT34ZE : 1; /*!< [4..4] MTU3 and MTU4 High-Impedance POE10F Add                            */
+            __IOM uint16_t IC5ADDMT34ZE : 1; /*!< [5..5] MTU3 and MTU4 High-Impedance POE11F Add                            */
+            __IOM uint16_t DE0ADDMT34ZE : 1; /*!< [6..6] MTU3 and MTU4 High-Impedance DERR0ST Add                           */
+            __IOM uint16_t DE1ADDMT34ZE : 1; /*!< [7..7] MTU3 and MTU4 High-Impedance DERR1ST Add                           */
+            uint16_t                    : 1;
+            __IOM uint16_t IC1ADDMT67ZE : 1; /*!< [9..9] MTU6 and MTU7 High-Impedance POE0F Add                             */
+            uint16_t                    : 1;
+            __IOM uint16_t IC3ADDMT67ZE : 1; /*!< [11..11] MTU6 and MTU7 High-Impedance POE8F Add                           */
+            __IOM uint16_t IC4ADDMT67ZE : 1; /*!< [12..12] MTU6 and MTU7 High-Impedance POE10F Add                          */
+            __IOM uint16_t IC5ADDMT67ZE : 1; /*!< [13..13] MTU6 and MTU7 High-Impedance POE11F Add                          */
+            __IOM uint16_t DE0ADDMT67ZE : 1; /*!< [14..14] MTU6 and MTU7 High-Impedance DERR0ST Add                         */
+            __IOM uint16_t DE1ADDMT67ZE : 1; /*!< [15..15] MTU6 and MTU7 High-Impedance DERR1ST Add                         */
+        } POECR4_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR5;         /*!< (@ 0x00000012) Port Output Enable Control Register 5                      */
+
+        struct
+        {
+            uint16_t                   : 1;
+            __IOM uint16_t IC1ADDMT0ZE : 1; /*!< [1..1] MTU0 High-Impedance POE0F Add                                      */
+            __IOM uint16_t IC2ADDMT0ZE : 1; /*!< [2..2] MTU0 High-Impedance POE4F Add                                      */
+            uint16_t                   : 1;
+            __IOM uint16_t IC4ADDMT0ZE : 1; /*!< [4..4] MTU0 High-Impedance POE10F Add                                     */
+            __IOM uint16_t IC5ADDMT0ZE : 1; /*!< [5..5] MTU0 High-Impedance POE11F Add                                     */
+            __IOM uint16_t DE0ADDMT0ZE : 1; /*!< [6..6] MTU0 High-Impedance DERR0ST Add                                    */
+            __IOM uint16_t DE1ADDMT0ZE : 1; /*!< [7..7] MTU0 High-Impedance DERR1ST Add                                    */
+            uint16_t                   : 8;
+        } POECR5_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t ICSR4;          /*!< (@ 0x00000016) Input Level Control/Status Register 4                      */
+
+        struct
+        {
+            __IOM uint16_t POE10M : 2; /*!< [1..0] POE10 Mode Select                                                  */
+            uint16_t              : 6;
+            __IOM uint16_t PIE4   : 1; /*!< [8..8] Port Interrupt Enable 4                                            */
+            __IOM uint16_t POE10E : 1; /*!< [9..9] POE10 High-Impedance Enable                                        */
+            uint16_t              : 2;
+            __IOM uint16_t POE10F : 1; /*!< [12..12] POE10 Flag                                                       */
+            uint16_t              : 3;
+        } ICSR4_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR5;          /*!< (@ 0x00000018) Input Level Control/Status Register 5                      */
+
+        struct
+        {
+            __IOM uint16_t POE11M : 2; /*!< [1..0] POE11 Mode Select                                                  */
+            uint16_t              : 6;
+            __IOM uint16_t PIE5   : 1; /*!< [8..8] Port Interrupt Enable 5                                            */
+            __IOM uint16_t POE11E : 1; /*!< [9..9] POE11 High-Impedance Enable                                        */
+            uint16_t              : 2;
+            __IOM uint16_t POE11F : 1; /*!< [12..12] POE11 Flag                                                       */
+            uint16_t              : 3;
+        } ICSR5_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ALR1;           /*!< (@ 0x0000001A) Active Level Setting Register 1                            */
+
+        struct
+        {
+            __IOM uint16_t OLSG0A : 1; /*!< [0..0] MTIOC3B Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG0B : 1; /*!< [1..1] MTIOC3D Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG1A : 1; /*!< [2..2] MTIOC4A Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG1B : 1; /*!< [3..3] MTIOC4C Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG2A : 1; /*!< [4..4] MTIOC4B Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG2B : 1; /*!< [5..5] MTIOC4D Pin Active Level Setting                                   */
+            uint16_t              : 1;
+            __IOM uint16_t OLSEN  : 1; /*!< [7..7] Active Level Setting Enable                                        */
+            uint16_t              : 8;
+        } ALR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR6;          /*!< (@ 0x0000001C) Input Level Control/Status Register 6                      */
+
+        struct
+        {
+            uint16_t              : 9;
+            __IOM uint16_t OSTSTE : 1; /*!< [9..9] Oscillation Stop High-Impedance Enable                             */
+            uint16_t              : 2;
+            __IOM uint16_t OSTSTF : 1; /*!< [12..12] Oscillation Stop High-Impedance Flag                             */
+            uint16_t              : 3;
+        } ICSR6_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR7;          /*!< (@ 0x0000001E) Input Level Control/Status Register 7                      */
+
+        struct
+        {
+            uint16_t               : 6;
+            __IOM uint16_t DERR0IE : 1; /*!< [6..6] DSMIF0 Error Interrupt Enable                                      */
+            __IOM uint16_t DERR1IE : 1; /*!< [7..7] DSMIF1 Error Interrupt Enable                                      */
+            uint16_t               : 5;
+            __IM uint16_t DERR0ST  : 1; /*!< [13..13] DSMIF0 Error Status                                              */
+            __IM uint16_t DERR1ST  : 1; /*!< [14..14] DSMIF1 Error Status                                              */
+            uint16_t               : 1;
+        } ICSR7_b;
+    };
+    __IM uint16_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint8_t M0SELR1;         /*!< (@ 0x00000024) MTU0 Pin Select Register 1                                 */
+
+        struct
+        {
+            __IOM uint8_t M0ASEL : 4;  /*!< [3..0] MTU0-A (MTIOC0A) Pin Select                                        */
+            __IOM uint8_t M0BSEL : 4;  /*!< [7..4] MTU0-B (MTIOC0B) Pin Select                                        */
+        } M0SELR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M0SELR2;         /*!< (@ 0x00000025) MTU0 Pin Select Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t M0CSEL : 4;  /*!< [3..0] MTU0-C (MTIOC0C) Pin Select                                        */
+            __IOM uint8_t M0DSEL : 4;  /*!< [7..4] MTU0-D (MTIOC0D) Pin Select                                        */
+        } M0SELR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M3SELR;          /*!< (@ 0x00000026) MTU3 Pin Select Register                                   */
+
+        struct
+        {
+            __IOM uint8_t M3BSEL : 4;  /*!< [3..0] MTU3-B (MTIOC3B) Pin Select                                        */
+            __IOM uint8_t M3DSEL : 4;  /*!< [7..4] MTU3-D (MTIOC3D) Pin Select                                        */
+        } M3SELR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M4SELR1;         /*!< (@ 0x00000027) MTU4 Pin Select Register 1                                 */
+
+        struct
+        {
+            __IOM uint8_t M4ASEL : 4;  /*!< [3..0] MTU4-A (MTIOC4A) Pin Select                                        */
+            __IOM uint8_t M4CSEL : 4;  /*!< [7..4] MTU4-C (MTIOC4C) Pin Select                                        */
+        } M4SELR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M4SELR2;         /*!< (@ 0x00000028) MTU4 Pin Select Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t M4BSEL : 4;  /*!< [3..0] MTU4-B (MTIOC4B) Pin Select                                        */
+            __IOM uint8_t M4DSEL : 4;  /*!< [7..4] MTU4-D (MTIOC4D) Pin Select                                        */
+        } M4SELR2_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t M6SELR;          /*!< (@ 0x0000002A) MTU6 Pin Select Register                                   */
+
+        struct
+        {
+            __IOM uint8_t M6BSEL : 4;  /*!< [3..0] MTU6-B (MTIOC6B) Pin Select                                        */
+            __IOM uint8_t M6DSEL : 4;  /*!< [7..4] MTU6-D (MTIOC6D) Pin Select                                        */
+        } M6SELR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M7SELR1;         /*!< (@ 0x0000002B) MTU7 Pin Select Register 1                                 */
+
+        struct
+        {
+            __IOM uint8_t M7ASEL : 4;  /*!< [3..0] MTU7-A (MTIOC7A) Pin Select                                        */
+            __IOM uint8_t M7CSEL : 4;  /*!< [7..4] MTU7-C (MTIOC7C) Pin Select                                        */
+        } M7SELR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M7SELR2;         /*!< (@ 0x0000002C) MTU7 Pin Select Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t M7BSEL : 4;  /*!< [3..0] MTU7-B (MTIOC7B) Pin Select                                        */
+            __IOM uint8_t M7DSEL : 4;  /*!< [7..4] MTU7-D (MTIOC7D) Pin Select                                        */
+        } M7SELR2_b;
+    };
+    __IM uint8_t  RESERVED4;
+    __IM uint16_t RESERVED5;
+} R_POE3_Type;                         /*!< Size = 48 (0x30)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief GPT Port Output Enable 0 (R_POEG0)
+ */
+
+typedef struct                          /*!< (@ 0x90006000) R_POEG0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t POEG0GA;         /*!< (@ 0x00000000) POEG0 Group A Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF    : 1; /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF    : 1; /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF   : 1; /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF     : 1; /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE    : 1; /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE    : 1; /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE   : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t               : 9;
+            __IM uint32_t ST       : 1; /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t               : 7;
+            __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status                                              */
+            __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status                                              */
+            __IOM uint32_t DERR0E  : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection                 */
+            __IOM uint32_t DERR1E  : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection                 */
+            __IOM uint32_t INV     : 1; /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG0GA_b;
+    };
+    __IM uint32_t RESERVED[255];
+
+    union
+    {
+        __IOM uint32_t POEG0GB;         /*!< (@ 0x00000400) POEG0 Group B Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF    : 1; /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF    : 1; /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF   : 1; /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF     : 1; /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE    : 1; /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE    : 1; /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE   : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t               : 9;
+            __IM uint32_t ST       : 1; /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t               : 7;
+            __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status                                              */
+            __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status                                              */
+            __IOM uint32_t DERR0E  : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection                 */
+            __IOM uint32_t DERR1E  : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection                 */
+            __IOM uint32_t INV     : 1; /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG0GB_b;
+    };
+    __IM uint32_t RESERVED1[255];
+
+    union
+    {
+        __IOM uint32_t POEG0GC;         /*!< (@ 0x00000800) POEG0 Group C Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF    : 1; /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF    : 1; /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF   : 1; /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF     : 1; /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE    : 1; /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE    : 1; /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE   : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t               : 9;
+            __IM uint32_t ST       : 1; /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t               : 7;
+            __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status                                              */
+            __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status                                              */
+            __IOM uint32_t DERR0E  : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection                 */
+            __IOM uint32_t DERR1E  : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection                 */
+            __IOM uint32_t INV     : 1; /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG0GC_b;
+    };
+    __IM uint32_t RESERVED2[255];
+
+    union
+    {
+        __IOM uint32_t POEG0GD;         /*!< (@ 0x00000C00) POEG0 Group D Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PIDF    : 1; /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF    : 1; /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF   : 1; /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF     : 1; /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE    : 1; /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE    : 1; /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE   : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t               : 9;
+            __IM uint32_t ST       : 1; /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t               : 7;
+            __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status                                              */
+            __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status                                              */
+            __IOM uint32_t DERR0E  : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection                 */
+            __IOM uint32_t DERR1E  : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection                 */
+            __IOM uint32_t INV     : 1; /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG0GD_b;
+    };
+} R_POEG0_Type;                         /*!< Size = 3076 (0xc04)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_DSMIF0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Delta-sigma Interface 0 (R_DSMIF0)
+ */
+
+typedef struct                         /*!< (@ 0x90008000) R_DSMIF0 Structure                                         */
+{
+    __IM uint32_t RESERVED[16];
+
+    union
+    {
+        __IOM uint32_t DSSEICR;        /*!< (@ 0x00000040) Overcurrent Sum Error Detect Interrupt Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t ISEL : 1;   /*!< [0..0] Overcurrent sum error lower limit detection interrupt
+                                        *   enable bit                                                                */
+            __IOM uint32_t ISEH : 1;   /*!< [1..1] Overcurrent sum error upper limit detection interrupt
+                                        *   enable bit                                                                */
+            uint32_t : 30;
+        } DSSEICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSECSR;        /*!< (@ 0x00000044) Overcurrent Sum Error Detect Channel Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t SEDM : 3;   /*!< [2..0] Overcurrent sum error detect mode setting bit                      */
+            uint32_t            : 29;
+        } DSSECSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSELTR;          /*!< (@ 0x00000048) Overcurrent Sum Error Detect Low Threshold Register        */
+
+        struct
+        {
+            __IOM uint32_t SCMPTBL : 18; /*!< [17..0] Overcurrent sum error detect lower limit                          */
+            uint32_t               : 14;
+        } DSSELTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSEHTR;          /*!< (@ 0x0000004C) Overcurrent Sum Error Detect High Threshold Register       */
+
+        struct
+        {
+            __IOM uint32_t SCMPTBH : 18; /*!< [17..0] Overcurrent sum error detect upper limit                          */
+            uint32_t               : 14;
+        } DSSEHTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSECR;         /*!< (@ 0x00000050) Overcurrent Sum Error Detect Control Register              */
+
+        struct
+        {
+            __IOM uint32_t SEEL : 1;   /*!< [0..0] Overcurrent sum error lower limit detection enable bit             */
+            __IOM uint32_t SEEH : 1;   /*!< [1..1] Overcurrent sum error upper limit detection enable bit             */
+            uint32_t            : 30;
+        } DSSECR_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint32_t DSSECDR[3];     /*!< (@ 0x00000060) Overcurrent Sum Error Detect Capture Data Register
+                                        *                  [0..2]                                                     */
+
+        struct
+        {
+            __IOM uint32_t SECDR : 16; /*!< [15..0] Overcurrent sum error detect capture data n                       */
+            uint32_t             : 16;
+        } DSSECDR_b[3];
+    };
+    __IM uint32_t RESERVED2[37];
+
+    union
+    {
+        __IOM uint32_t DSCSTRTR;        /*!< (@ 0x00000100) Channel Software Start Trigger Register                    */
+
+        struct
+        {
+            __IOM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger                                            */
+            __IOM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger                                            */
+            __IOM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger                                            */
+            uint32_t               : 29;
+        } DSCSTRTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCSTPTR;        /*!< (@ 0x00000104) Channel Software Stop Trigger Register                     */
+
+        struct
+        {
+            __IOM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger                                             */
+            __IOM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger                                             */
+            __IOM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger                                             */
+            uint32_t               : 29;
+        } DSCSTPTR_b;
+    };
+    __IM uint32_t RESERVED3[2];
+
+    union
+    {
+        __IM uint32_t DSCESR;          /*!< (@ 0x00000110) Channel Error Status Register                              */
+
+        struct
+        {
+            __IM uint32_t OCFL0   : 1; /*!< [0..0] Channel 0 overcurrent lower limit detection flag                   */
+            __IM uint32_t OCFL1   : 1; /*!< [1..1] Channel 1 overcurrent lower limit detection flag                   */
+            __IM uint32_t OCFL2   : 1; /*!< [2..2] Channel 2 overcurrent lower limit detection flag                   */
+            uint32_t              : 1;
+            __IM uint32_t OCFH0   : 1; /*!< [4..4] Channel 0 overcurrent upper limit detection flag                   */
+            __IM uint32_t OCFH1   : 1; /*!< [5..5] Channel 1 overcurrent upper limit detection flag                   */
+            __IM uint32_t OCFH2   : 1; /*!< [6..6] Channel 2 overcurrent upper limit detection flag                   */
+            uint32_t              : 1;
+            __IM uint32_t SCF0    : 1; /*!< [8..8] Channel 0 short circuit detection flag                             */
+            __IM uint32_t SCF1    : 1; /*!< [9..9] Channel 1 short circuit detection flag                             */
+            __IM uint32_t SCF2    : 1; /*!< [10..10] Channel 2 short circuit detection flag                           */
+            uint32_t              : 5;
+            __IM uint32_t SUMERRL : 1; /*!< [16..16] Overcurrent sum error lower limit detection flag                 */
+            __IM uint32_t SUMERRH : 1; /*!< [17..17] Overcurrent sum error upper limit detection flag                 */
+            uint32_t              : 14;
+        } DSCESR_b;
+    };
+    __IM uint32_t RESERVED4;
+
+    union
+    {
+        __IM uint32_t DSCSR;           /*!< (@ 0x00000118) Channel Status Register                                    */
+
+        struct
+        {
+            __IM uint32_t DUF0 : 1;    /*!< [0..0] Channel 0 Data Update flag                                         */
+            __IM uint32_t DUF1 : 1;    /*!< [1..1] Channel 1 Data Update flag                                         */
+            __IM uint32_t DUF2 : 1;    /*!< [2..2] Channel 2 Data Update flag                                         */
+            uint32_t           : 29;
+        } DSCSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCSSR;           /*!< (@ 0x0000011C) Channel State Status Register                              */
+
+        struct
+        {
+            __IM uint32_t CHSTATE0 : 1; /*!< [0..0] Channel 0 state                                                    */
+            uint32_t               : 3;
+            __IM uint32_t CHSTATE1 : 1; /*!< [4..4] Channel 1 state                                                    */
+            uint32_t               : 3;
+            __IM uint32_t CHSTATE2 : 1; /*!< [8..8] Channel 2 state                                                    */
+            uint32_t               : 23;
+        } DSCSSR_b;
+    };
+
+    union
+    {
+        __OM uint32_t DSCESCR;            /*!< (@ 0x00000120) Channel Error Status Clear Register                        */
+
+        struct
+        {
+            __OM uint32_t CLROCFL0   : 1; /*!< [0..0] Channel 0 Overcurrent Lower Limit Detection Flag Clear             */
+            __OM uint32_t CLROCFL1   : 1; /*!< [1..1] Channel 1 Overcurrent Lower Limit Detection Flag Clear             */
+            __OM uint32_t CLROCFL2   : 1; /*!< [2..2] Channel 2 Overcurrent Lower Limit Detection Flag Clear             */
+            uint32_t                 : 1;
+            __OM uint32_t CLROCFH0   : 1; /*!< [4..4] Channel 0 Overcurrent Upper Limit Detection Flag Clear             */
+            __OM uint32_t CLROCFH1   : 1; /*!< [5..5] Channel 1 Overcurrent Upper Limit Detection Flag Clear             */
+            __OM uint32_t CLROCFH2   : 1; /*!< [6..6] Channel 2 Overcurrent Upper Limit Detection Flag Clear             */
+            uint32_t                 : 1;
+            __OM uint32_t CLRSCF0    : 1; /*!< [8..8] Channel 0 Short Circuit Detection Flag Clear                       */
+            __OM uint32_t CLRSCF1    : 1; /*!< [9..9] Channel 1 Short Circuit Detection Flag Clear                       */
+            __OM uint32_t CLRSCF2    : 1; /*!< [10..10] Channel 2 Short Circuit Detection Flag Clear                     */
+            uint32_t                 : 5;
+            __OM uint32_t CLRSUMERRL : 1; /*!< [16..16] Overcurrent Sum Error Lower Limit Detection Flag Clear           */
+            __OM uint32_t CLRSUMERRH : 1; /*!< [17..17] Overcurrent Sum Error Upper Limit Detection Flag Clear           */
+            uint32_t                 : 14;
+        } DSCESCR_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __OM uint32_t DSCSCR;          /*!< (@ 0x00000128) Channel Status Clear Register                              */
+
+        struct
+        {
+            __OM uint32_t CLRDUF0 : 1; /*!< [0..0] Channel 0 Data Update Flag Clear                                   */
+            __OM uint32_t CLRDUF1 : 1; /*!< [1..1] Channel 1 Data Update Flag Clear                                   */
+            __OM uint32_t CLRDUF2 : 1; /*!< [2..2] Channel 2 Data Update Flag Clear                                   */
+            uint32_t              : 29;
+        } DSCSCR_b;
+    };
+    __IM uint32_t          RESERVED6[21];
+    __IOM R_DSMIF0_CH_Type CH[3];      /*!< (@ 0x00000180) Channel Registers [0..2]                                   */
+} R_DSMIF0_Type;                       /*!< Size = 816 (0x330)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_GSC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Global System Counter (R_GSC)
+ */
+
+typedef struct                         /*!< (@ 0xC0060000) R_GSC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t CNTCR;          /*!< (@ 0x00000000) Global System Counter Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t EN   : 1;   /*!< [0..0] Counter Enable                                                     */
+            __IOM uint32_t HDBG : 1;   /*!< [1..1] Halt on Debug                                                      */
+            uint32_t            : 30;
+        } CNTCR_b;
+    };
+
+    union
+    {
+        __IM uint32_t CNTSR;           /*!< (@ 0x00000004) Global System Counter Status Register                      */
+
+        struct
+        {
+            uint32_t           : 1;
+            __IM uint32_t DBGH : 1;    /*!< [1..1] Debug Halted                                                       */
+            uint32_t           : 30;
+        } CNTSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CNTCVL;               /*!< (@ 0x00000008) Global System Counter Current Value Lower Register         */
+
+        struct
+        {
+            __IOM uint32_t CNTCVL_L_32 : 32; /*!< [31..0] Current value of the counter, lower 32 bits                       */
+        } CNTCVL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CNTCVU;               /*!< (@ 0x0000000C) Global System Counter Current Value Upper Register         */
+
+        struct
+        {
+            __IOM uint32_t CNTCVU_U_32 : 32; /*!< [31..0] Current value of the counter, upper 32 bits                       */
+        } CNTCVU_b;
+    };
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint32_t CNTFID0;        /*!< (@ 0x00000020) Global System Counter Base Frequency ID Register           */
+
+        struct
+        {
+            __IOM uint32_t FREQ : 32;  /*!< [31..0] Frequency in number of ticks per second                           */
+        } CNTFID0_b;
+    };
+} R_GSC_Type;                          /*!< Size = 36 (0x24)                                                          */
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+ #define R_GPT7_BASE           0x80000000UL
+ #define R_GPT8_BASE           0x80000100UL
+ #define R_GPT9_BASE           0x80000200UL
+ #define R_GPT10_BASE          0x80000300UL
+ #define R_GPT11_BASE          0x80000400UL
+ #define R_GPT12_BASE          0x80000500UL
+ #define R_GPT13_BASE          0x80000600UL
+ #define R_SCI0_BASE           0x80001000UL
+ #define R_SCI1_BASE           0x80001400UL
+ #define R_SCI2_BASE           0x80001800UL
+ #define R_SCI3_BASE           0x80001C00UL
+ #define R_SCI4_BASE           0x80002000UL
+ #define R_SPI0_BASE           0x80003000UL
+ #define R_SPI1_BASE           0x80003400UL
+ #define R_SPI2_BASE           0x80003800UL
+ #define R_CRC0_BASE           0x80004000UL
+ #define R_CANFD_BASE          0x80020000UL
+ #define R_CMT_BASE            0x80040000UL
+ #define R_CMTW0_BASE          0x80041000UL
+ #define R_CMTW1_BASE          0x80041400UL
+ #define R_WDT0_BASE           0x80042000UL
+ #define R_IIC0_BASE           0x80043000UL
+ #define R_IIC1_BASE           0x80043400UL
+ #define R_DOC_BASE            0x80044000UL
+ #define R_ADC121_BASE         0x80045000UL
+ #define R_TSU_BASE            0x80046000UL
+ #define R_POEG1_BASE          0x80047000UL
+ #define R_DMAC0_BASE          0x80080000UL
+ #define R_DMAC1_BASE          0x80081000UL
+ #define R_ICU_NS_BASE         0x80090000UL
+ #define R_ELC_BASE            0x80090010UL
+ #define R_DMA_BASE            0x80090060UL
+ #define R_PORT_NSR_BASE       0x800A0000UL
+ #define R_GMAC_BASE           0x80100000UL
+ #define R_ETHSS_BASE          0x80110000UL
+ #define R_ESC_INI_BASE        0x80110200UL
+ #define R_ETHSW_PTP_BASE      0x80110400UL
+ #define R_ETHSW_BASE          0x80120000UL
+ #define R_ESC_BASE            0x80130000UL
+ #define R_USBHC_BASE          0x80200000UL
+ #define R_USBF_BASE           0x80201000UL
+ #define R_BSC_BASE            0x80210000UL
+ #define R_XSPI0_BASE          0x80220000UL
+ #define R_XSPI1_BASE          0x80221000UL
+ #define R_MBXSEM_BASE         0x80240000UL
+ #define R_SHOSTIF_BASE        0x80241000UL
+ #define R_PHOSTIF_BASE        0x80242000UL
+ #define R_SYSC_NS_BASE        0x80280000UL
+ #define R_ELO_BASE            0x80281200UL
+ #define R_RWP_NS_BASE         0x80281A10UL
+ #define R_GPT14_BASE          0x81000000UL
+ #define R_GPT15_BASE          0x81000100UL
+ #define R_GPT16_BASE          0x81000200UL
+ #define R_GPT17_BASE          0x81000300UL
+ #define R_SCI5_BASE           0x81001000UL
+ #define R_SPI3_BASE           0x81002000UL
+ #define R_CRC1_BASE           0x81003000UL
+ #define R_IIC2_BASE           0x81008000UL
+ #define R_RTC_BASE            0x81009000UL
+ #define R_POEG2_BASE          0x8100A000UL
+ #define R_OTP_BASE            0x81028000UL
+ #define R_PORT_SR_BASE        0x81030000UL
+ #define R_PTADR_BASE          0x81030C00UL
+ #define R_SYSRAM0_BASE        0x81040000UL
+ #define R_SYSRAM1_BASE        0x81041000UL
+ #define R_SYSRAM2_BASE        0x81042000UL
+ #define R_ICU_BASE            0x81048000UL
+ #define R_SYSC_S_BASE         0x81280000UL
+ #define R_CLMA0_BASE          0x81280800UL
+ #define R_CLMA1_BASE          0x81280820UL
+ #define R_CLMA2_BASE          0x81280840UL
+ #define R_CLMA3_BASE          0x81280860UL
+ #define R_MPU0_BASE           0x81281100UL
+ #define R_MPU1_BASE           0x81281200UL
+ #define R_MPU2_BASE           0x81281300UL
+ #define R_MPU3_BASE           0x81281400UL
+ #define R_MPU4_BASE           0x81281500UL
+ #define R_MPU6_BASE           0x81281700UL
+ #define R_SYSRAM_CTL_BASE     0x81281800UL
+ #define R_SHOSTIF_CFG_BASE    0x81281920UL
+ #define R_PHOSTIF_CFG_BASE    0x81281930UL
+ #define R_RWP_S_BASE          0x81281A00UL
+ #define R_MPU7_BASE           0x81281C00UL
+ #define R_MPU8_BASE           0x81281D00UL
+ #define R_MTU_BASE            0x90001000UL
+ #define R_MTU3_BASE           0x90001100UL
+ #define R_MTU4_BASE           0x90001200UL
+ #define R_MTU_NF_BASE         0x90001290UL
+ #define R_MTU0_BASE           0x90001300UL
+ #define R_MTU1_BASE           0x90001380UL
+ #define R_MTU2_BASE           0x90001400UL
+ #define R_MTU8_BASE           0x90001600UL
+ #define R_MTU6_BASE           0x90001900UL
+ #define R_MTU7_BASE           0x90001A00UL
+ #define R_MTU5_BASE           0x90001C00UL
+ #define R_GPT0_BASE           0x90002000UL
+ #define R_GPT1_BASE           0x90002100UL
+ #define R_GPT2_BASE           0x90002200UL
+ #define R_GPT3_BASE           0x90002300UL
+ #define R_GPT4_BASE           0x90002400UL
+ #define R_GPT5_BASE           0x90002500UL
+ #define R_GPT6_BASE           0x90002600UL
+ #define R_TFU_BASE            0x90003000UL
+ #define R_ADC120_BASE         0x90004000UL
+ #define R_POE3_BASE           0x90005000UL
+ #define R_POEG0_BASE          0x90006000UL
+ #define R_DSMIF0_BASE         0x90008000UL
+ #define R_DSMIF1_BASE         0x90008400UL
+ #define R_GSC_BASE            0xC0060000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+ #define R_GPT7           ((R_GPT0_Type *) R_GPT7_BASE)
+ #define R_GPT8           ((R_GPT0_Type *) R_GPT8_BASE)
+ #define R_GPT9           ((R_GPT0_Type *) R_GPT9_BASE)
+ #define R_GPT10          ((R_GPT0_Type *) R_GPT10_BASE)
+ #define R_GPT11          ((R_GPT0_Type *) R_GPT11_BASE)
+ #define R_GPT12          ((R_GPT0_Type *) R_GPT12_BASE)
+ #define R_GPT13          ((R_GPT0_Type *) R_GPT13_BASE)
+ #define R_SCI0           ((R_SCI0_Type *) R_SCI0_BASE)
+ #define R_SCI1           ((R_SCI0_Type *) R_SCI1_BASE)
+ #define R_SCI2           ((R_SCI0_Type *) R_SCI2_BASE)
+ #define R_SCI3           ((R_SCI0_Type *) R_SCI3_BASE)
+ #define R_SCI4           ((R_SCI0_Type *) R_SCI4_BASE)
+ #define R_SPI0           ((R_SPI0_Type *) R_SPI0_BASE)
+ #define R_SPI1           ((R_SPI0_Type *) R_SPI1_BASE)
+ #define R_SPI2           ((R_SPI0_Type *) R_SPI2_BASE)
+ #define R_CRC0           ((R_CRC0_Type *) R_CRC0_BASE)
+ #define R_CANFD          ((R_CANFD_Type *) R_CANFD_BASE)
+ #define R_CMT            ((R_CMT_Type *) R_CMT_BASE)
+ #define R_CMTW0          ((R_CMTW0_Type *) R_CMTW0_BASE)
+ #define R_CMTW1          ((R_CMTW0_Type *) R_CMTW1_BASE)
+ #define R_WDT0           ((R_WDT0_Type *) R_WDT0_BASE)
+ #define R_IIC0           ((R_IIC0_Type *) R_IIC0_BASE)
+ #define R_IIC1           ((R_IIC0_Type *) R_IIC1_BASE)
+ #define R_DOC            ((R_DOC_Type *) R_DOC_BASE)
+ #define R_ADC121         ((R_ADC121_Type *) R_ADC121_BASE)
+ #define R_TSU            ((R_TSU_Type *) R_TSU_BASE)
+ #define R_POEG1          ((R_POEG1_Type *) R_POEG1_BASE)
+ #define R_DMAC0          ((R_DMAC0_Type *) R_DMAC0_BASE)
+ #define R_DMAC1          ((R_DMAC0_Type *) R_DMAC1_BASE)
+ #define R_ICU_NS         ((R_ICU_NS_Type *) R_ICU_NS_BASE)
+ #define R_ELC            ((R_ELC_Type *) R_ELC_BASE)
+ #define R_DMA            ((R_DMA_Type *) R_DMA_BASE)
+ #define R_PORT_NSR       ((R_PORT_COMMON_Type *) R_PORT_NSR_BASE)
+ #define R_GMAC           ((R_GMAC_Type *) R_GMAC_BASE)
+ #define R_ETHSS          ((R_ETHSS_Type *) R_ETHSS_BASE)
+ #define R_ESC_INI        ((R_ESC_INI_Type *) R_ESC_INI_BASE)
+ #define R_ETHSW_PTP      ((R_ETHSW_PTP_Type *) R_ETHSW_PTP_BASE)
+ #define R_ETHSW          ((R_ETHSW_Type *) R_ETHSW_BASE)
+ #define R_ESC            ((R_ESC_Type *) R_ESC_BASE)
+ #define R_USBHC          ((R_USBHC_Type *) R_USBHC_BASE)
+ #define R_USBF           ((R_USBF_Type *) R_USBF_BASE)
+ #define R_BSC            ((R_BSC_Type *) R_BSC_BASE)
+ #define R_XSPI0          ((R_XSPI0_Type *) R_XSPI0_BASE)
+ #define R_XSPI1          ((R_XSPI0_Type *) R_XSPI1_BASE)
+ #define R_MBXSEM         ((R_MBXSEM_Type *) R_MBXSEM_BASE)
+ #define R_SHOSTIF        ((R_SHOSTIF_Type *) R_SHOSTIF_BASE)
+ #define R_PHOSTIF        ((R_PHOSTIF_Type *) R_PHOSTIF_BASE)
+ #define R_SYSC_NS        ((R_SYSC_NS_Type *) R_SYSC_NS_BASE)
+ #define R_ELO            ((R_ELO_Type *) R_ELO_BASE)
+ #define R_RWP_NS         ((R_RWP_NS_Type *) R_RWP_NS_BASE)
+ #define R_GPT14          ((R_GPT0_Type *) R_GPT14_BASE)
+ #define R_GPT15          ((R_GPT0_Type *) R_GPT15_BASE)
+ #define R_GPT16          ((R_GPT0_Type *) R_GPT16_BASE)
+ #define R_GPT17          ((R_GPT0_Type *) R_GPT17_BASE)
+ #define R_SCI5           ((R_SCI0_Type *) R_SCI5_BASE)
+ #define R_SPI3           ((R_SPI0_Type *) R_SPI3_BASE)
+ #define R_CRC1           ((R_CRC0_Type *) R_CRC1_BASE)
+ #define R_IIC2           ((R_IIC0_Type *) R_IIC2_BASE)
+ #define R_RTC            ((R_RTC_Type *) R_RTC_BASE)
+ #define R_POEG2          ((R_POEG2_Type *) R_POEG2_BASE)
+ #define R_OTP            ((R_OTP_Type *) R_OTP_BASE)
+ #define R_PORT_SR        ((R_PORT_COMMON_Type *) R_PORT_SR_BASE)
+ #define R_PTADR          ((R_PTADR_Type *) R_PTADR_BASE)
+ #define R_SYSRAM0        ((R_SYSRAM0_Type *) R_SYSRAM0_BASE)
+ #define R_SYSRAM1        ((R_SYSRAM0_Type *) R_SYSRAM1_BASE)
+ #define R_SYSRAM2        ((R_SYSRAM0_Type *) R_SYSRAM2_BASE)
+ #define R_ICU            ((R_ICU_Type *) R_ICU_BASE)
+ #define R_SYSC_S         ((R_SYSC_S_Type *) R_SYSC_S_BASE)
+ #define R_CLMA0          ((R_CLMA0_Type *) R_CLMA0_BASE)
+ #define R_CLMA1          ((R_CLMA0_Type *) R_CLMA1_BASE)
+ #define R_CLMA2          ((R_CLMA0_Type *) R_CLMA2_BASE)
+ #define R_CLMA3          ((R_CLMA0_Type *) R_CLMA3_BASE)
+ #define R_MPU0           ((R_MPU0_Type *) R_MPU0_BASE)
+ #define R_MPU1           ((R_MPU0_Type *) R_MPU1_BASE)
+ #define R_MPU2           ((R_MPU0_Type *) R_MPU2_BASE)
+ #define R_MPU3           ((R_MPU3_Type *) R_MPU3_BASE)
+ #define R_MPU4           ((R_MPU3_Type *) R_MPU4_BASE)
+ #define R_MPU6           ((R_MPU0_Type *) R_MPU6_BASE)
+ #define R_SYSRAM_CTL     ((R_SYSRAM_CTL_Type *) R_SYSRAM_CTL_BASE)
+ #define R_SHOSTIF_CFG    ((R_SHOSTIF_CFG_Type *) R_SHOSTIF_CFG_BASE)
+ #define R_PHOSTIF_CFG    ((R_PHOSTIF_CFG_Type *) R_PHOSTIF_CFG_BASE)
+ #define R_RWP_S          ((R_RWP_S_Type *) R_RWP_S_BASE)
+ #define R_MPU7           ((R_MPU3_Type *) R_MPU7_BASE)
+ #define R_MPU8           ((R_MPU3_Type *) R_MPU8_BASE)
+ #define R_MTU            ((R_MTU_Type *) R_MTU_BASE)
+ #define R_MTU3           ((R_MTU3_Type *) R_MTU3_BASE)
+ #define R_MTU4           ((R_MTU4_Type *) R_MTU4_BASE)
+ #define R_MTU_NF         ((R_MTU_NF_Type *) R_MTU_NF_BASE)
+ #define R_MTU0           ((R_MTU0_Type *) R_MTU0_BASE)
+ #define R_MTU1           ((R_MTU1_Type *) R_MTU1_BASE)
+ #define R_MTU2           ((R_MTU2_Type *) R_MTU2_BASE)
+ #define R_MTU8           ((R_MTU8_Type *) R_MTU8_BASE)
+ #define R_MTU6           ((R_MTU6_Type *) R_MTU6_BASE)
+ #define R_MTU7           ((R_MTU7_Type *) R_MTU7_BASE)
+ #define R_MTU5           ((R_MTU5_Type *) R_MTU5_BASE)
+ #define R_GPT0           ((R_GPT0_Type *) R_GPT0_BASE)
+ #define R_GPT1           ((R_GPT0_Type *) R_GPT1_BASE)
+ #define R_GPT2           ((R_GPT0_Type *) R_GPT2_BASE)
+ #define R_GPT3           ((R_GPT0_Type *) R_GPT3_BASE)
+ #define R_GPT4           ((R_GPT0_Type *) R_GPT4_BASE)
+ #define R_GPT5           ((R_GPT0_Type *) R_GPT5_BASE)
+ #define R_GPT6           ((R_GPT0_Type *) R_GPT6_BASE)
+ #define R_TFU            ((R_TFU_Type *) R_TFU_BASE)
+ #define R_ADC120         ((R_ADC121_Type *) R_ADC120_BASE)
+ #define R_POE3           ((R_POE3_Type *) R_POE3_BASE)
+ #define R_POEG0          ((R_POEG0_Type *) R_POEG0_BASE)
+ #define R_DSMIF0         ((R_DSMIF0_Type *) R_DSMIF0_BASE)
+ #define R_DSMIF1         ((R_DSMIF0_Type *) R_DSMIF1_BASE)
+ #define R_GSC            ((R_GSC_Type *) R_GSC_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+ #if defined(__CC_ARM)
+  #pragma pop
+ #elif defined(__ICCARM__)
+
+/* leave anonymous unions enabled */
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning restore
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                                 Pos/Mask Cluster Section                                  ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_clusters
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDC                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  NCFG  ========================================================== */
+ #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
+ #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
+ #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
+ #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
+/* ==========================================================  CTR  ========================================================== */
+ #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
+ #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
+ #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
+ #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
+ #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
+ #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
+ #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
+ #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
+ #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
+ #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
+ #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
+ #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
+ #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
+ #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
+ #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
+ #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
+ #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
+ #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
+ #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
+ #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  STS  ========================================================== */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
+ #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
+ #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
+ #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
+ #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
+ #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
+ #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
+ #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
+ #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
+/* =========================================================  ERFL  ========================================================== */
+ #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
+ #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
+ #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
+ #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
+ #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
+ #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
+ #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
+ #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
+ #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
+ #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
+ #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
+ #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
+ #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
+ #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDC2                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DCFG  ========================================================== */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  FDCFG  ========================================================= */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_FDCFG_GWEN_Pos      (24UL)         /*!< GWEN (Bit 24)                                         */
+ #define R_CANFD_CFDC2_FDCFG_GWEN_Msk      (0x1000000UL)  /*!< GWEN (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos     (25UL)         /*!< GWFDF (Bit 25)                                        */
+ #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk     (0x2000000UL)  /*!< GWFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos     (26UL)         /*!< GWBRS (Bit 26)                                        */
+ #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk     (0x4000000UL)  /*!< GWBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos     (31UL)         /*!< CFDTE (Bit 31)                                        */
+ #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk     (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FDCTR  ========================================================= */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
+/* =========================================================  FDCRC  ========================================================= */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (25UL)         /*!< SCNT (Bit 25)                                         */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0x1e000000UL) /*!< SCNT (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BLCT  ========================================================== */
+ #define R_CANFD_CFDC2_BLCT_BLCE_Pos       (0UL)          /*!< BLCE (Bit 0)                                          */
+ #define R_CANFD_CFDC2_BLCT_BLCE_Msk       (0x1UL)        /*!< BLCE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_BLCT_BLCLD_Pos      (8UL)          /*!< BLCLD (Bit 8)                                         */
+ #define R_CANFD_CFDC2_BLCT_BLCLD_Msk      (0x100UL)      /*!< BLCLD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  BLSTS  ========================================================= */
+ #define R_CANFD_CFDC2_BLSTS_BLC_Pos       (3UL)          /*!< BLC (Bit 3)                                           */
+ #define R_CANFD_CFDC2_BLSTS_BLC_Msk       (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          CFDGAFL                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
+/* ===========================================================  M  =========================================================== */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
+/* ==========================================================  P0  =========================================================== */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos    (4UL)          /*!< GAFLSRD0 (Bit 4)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk    (0x10UL)       /*!< GAFLSRD0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos    (5UL)          /*!< GAFLSRD1 (Bit 5)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk    (0x20UL)       /*!< GAFLSRD1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos    (6UL)          /*!< GAFLSRD2 (Bit 6)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk    (0x40UL)       /*!< GAFLSRD2 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
+/* ==========================================================  P1  =========================================================== */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x3fffUL)     /*!< GAFLFDP (Bitfield-Mask: 0x3fff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDRM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDRM_ID_RMID_Pos          (0UL)          /*!< RMID (Bit 0)                                          */
+ #define R_CANFD_CFDRM_ID_RMID_Msk          (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDRM_ID_RMRTR_Pos         (30UL)         /*!< RMRTR (Bit 30)                                        */
+ #define R_CANFD_CFDRM_ID_RMRTR_Msk         (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_ID_RMIDE_Pos         (31UL)         /*!< RMIDE (Bit 31)                                        */
+ #define R_CANFD_CFDRM_ID_RMIDE_Msk         (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDRM_PTR_RMTS_Pos         (0UL)          /*!< RMTS (Bit 0)                                          */
+ #define R_CANFD_CFDRM_PTR_RMTS_Msk         (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDRM_PTR_RMDLC_Pos        (28UL)         /*!< RMDLC (Bit 28)                                        */
+ #define R_CANFD_CFDRM_PTR_RMDLC_Msk        (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDRM_FDSTS_RMESI_Pos      (0UL)          /*!< RMESI (Bit 0)                                         */
+ #define R_CANFD_CFDRM_FDSTS_RMESI_Msk      (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos      (1UL)          /*!< RMBRS (Bit 1)                                         */
+ #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk      (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos      (2UL)          /*!< RMFDF (Bit 2)                                         */
+ #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk      (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos      (8UL)          /*!< RMIFL (Bit 8)                                         */
+ #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk      (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos      (16UL)         /*!< RMPTR (Bit 16)                                        */
+ #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk      (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DF_WD  ========================================================= */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Pos    (0UL)          /*!< RMDB_LL (Bit 0)                                       */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Msk    (0xffUL)       /*!< RMDB_LL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Pos    (8UL)          /*!< RMDB_LH (Bit 8)                                       */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Msk    (0xff00UL)     /*!< RMDB_LH (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Pos    (16UL)         /*!< RMDB_HL (Bit 16)                                      */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Msk    (0xff0000UL)   /*!< RMDB_HL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Pos    (24UL)         /*!< RMDB_HH (Bit 24)                                      */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Msk    (0xff000000UL) /*!< RMDB_HH (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDRM_DF_RMDB_Pos          (0UL)          /*!< RMDB (Bit 0)                                          */
+ #define R_CANFD_CFDRM_DF_RMDB_Msk          (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDRF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDRF_ID_RFID_Pos           (0UL)          /*!< RFID (Bit 0)                                          */
+ #define R_CANFD_CFDRF_ID_RFID_Msk           (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDRF_ID_RFRTR_Pos          (30UL)         /*!< RFRTR (Bit 30)                                        */
+ #define R_CANFD_CFDRF_ID_RFRTR_Msk          (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_ID_RFIDE_Pos          (31UL)         /*!< RFIDE (Bit 31)                                        */
+ #define R_CANFD_CFDRF_ID_RFIDE_Msk          (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDRF_PTR_RFTS_Pos          (0UL)          /*!< RFTS (Bit 0)                                          */
+ #define R_CANFD_CFDRF_PTR_RFTS_Msk          (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Pos         (28UL)         /*!< RFDLC (Bit 28)                                        */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Msk         (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Pos       (0UL)          /*!< RFESI (Bit 0)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Msk       (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos       (1UL)          /*!< RFBRS (Bit 1)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk       (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos       (2UL)          /*!< RFFDF (Bit 2)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk       (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos       (8UL)          /*!< RFIFL (Bit 8)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk       (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Pos    (16UL)         /*!< CFDRFPTR (Bit 16)                                     */
+ #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Msk    (0xffff0000UL) /*!< CFDRFPTR (Bitfield-Mask: 0xffff)                      */
+/* =========================================================  DF_WD  ========================================================= */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Pos     (0UL)          /*!< RFDB_LL (Bit 0)                                       */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Msk     (0xffUL)       /*!< RFDB_LL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Pos     (8UL)          /*!< RFDB_LH (Bit 8)                                       */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Msk     (0xff00UL)     /*!< RFDB_LH (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Pos     (16UL)         /*!< RFDB_HL (Bit 16)                                      */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Msk     (0xff0000UL)   /*!< RFDB_HL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Pos     (24UL)         /*!< RFDB_HH (Bit 24)                                      */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Msk     (0xff000000UL) /*!< RFDB_HH (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDRF_DF_RFDB_Pos           (0UL)          /*!< RFDB (Bit 0)                                          */
+ #define R_CANFD_CFDRF_DF_RFDB_Msk           (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDCF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDCF_ID_CFID_Pos          (0UL)          /*!< CFID (Bit 0)                                          */
+ #define R_CANFD_CFDCF_ID_CFID_Msk          (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDCF_ID_THLEN_Pos         (29UL)         /*!< THLEN (Bit 29)                                        */
+ #define R_CANFD_CFDCF_ID_THLEN_Msk         (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_ID_CFRTR_Pos         (30UL)         /*!< CFRTR (Bit 30)                                        */
+ #define R_CANFD_CFDCF_ID_CFRTR_Msk         (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_ID_CFIDE_Pos         (31UL)         /*!< CFIDE (Bit 31)                                        */
+ #define R_CANFD_CFDCF_ID_CFIDE_Msk         (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDCF_PTR_CFTS_Pos         (0UL)          /*!< CFTS (Bit 0)                                          */
+ #define R_CANFD_CFDCF_PTR_CFTS_Msk         (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Pos        (28UL)         /*!< CFDLC (Bit 28)                                        */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Msk        (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  FDCSTS  ========================================================= */
+ #define R_CANFD_CFDCF_FDCSTS_CFESI_Pos     (0UL)          /*!< CFESI (Bit 0)                                         */
+ #define R_CANFD_CFDCF_FDCSTS_CFESI_Msk     (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDCSTS_CFBRS_Pos     (1UL)          /*!< CFBRS (Bit 1)                                         */
+ #define R_CANFD_CFDCF_FDCSTS_CFBRS_Msk     (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDCSTS_CFFDF_Pos     (2UL)          /*!< CFFDF (Bit 2)                                         */
+ #define R_CANFD_CFDCF_FDCSTS_CFFDF_Msk     (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDCSTS_CFIFL_Pos     (8UL)          /*!< CFIFL (Bit 8)                                         */
+ #define R_CANFD_CFDCF_FDCSTS_CFIFL_Msk     (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDCF_FDCSTS_CFPTR_Pos     (16UL)         /*!< CFPTR (Bit 16)                                        */
+ #define R_CANFD_CFDCF_FDCSTS_CFPTR_Msk     (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DF_WD  ========================================================= */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Pos    (0UL)          /*!< CFDB_LL (Bit 0)                                       */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Msk    (0xffUL)       /*!< CFDB_LL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Pos    (8UL)          /*!< CFDB_LH (Bit 8)                                       */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Msk    (0xff00UL)     /*!< CFDB_LH (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Pos    (16UL)         /*!< CFDB_HL (Bit 16)                                      */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Msk    (0xff0000UL)   /*!< CFDB_HL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Pos    (24UL)         /*!< CFDB_HH (Bit 24)                                      */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Msk    (0xff000000UL) /*!< CFDB_HH (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDCF_DF_CFDB_Pos          (0UL)          /*!< CFDB (Bit 0)                                          */
+ #define R_CANFD_CFDCF_DF_CFDB_Msk          (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          CFDTHL                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ACC0  ========================================================== */
+ #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
+ #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
+ #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
+ #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
+ #define R_CANFD_CFDTHL_ACC0_TGW_Pos     (15UL)         /*!< TGW (Bit 15)                                          */
+ #define R_CANFD_CFDTHL_ACC0_TGW_Msk     (0x8000UL)     /*!< TGW (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  ACC1  ========================================================== */
+ #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
+ #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDTM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDTM_ID_TMID_Pos          (0UL)          /*!< TMID (Bit 0)                                          */
+ #define R_CANFD_CFDTM_ID_TMID_Msk          (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDTM_ID_THLEN_Pos         (29UL)         /*!< THLEN (Bit 29)                                        */
+ #define R_CANFD_CFDTM_ID_THLEN_Msk         (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_ID_TMRTR_Pos         (30UL)         /*!< TMRTR (Bit 30)                                        */
+ #define R_CANFD_CFDTM_ID_TMRTR_Msk         (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_ID_TMIDE_Pos         (31UL)         /*!< TMIDE (Bit 31)                                        */
+ #define R_CANFD_CFDTM_ID_TMIDE_Msk         (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Pos        (28UL)         /*!< TMDLC (Bit 28)                                        */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Msk        (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDCTR  ========================================================= */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Pos      (0UL)          /*!< TMESI (Bit 0)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Msk      (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos      (1UL)          /*!< TMBRS (Bit 1)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk      (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos      (2UL)          /*!< TMFDF (Bit 2)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk      (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos      (8UL)          /*!< TMIFL (Bit 8)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk      (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos      (16UL)         /*!< TMPTR (Bit 16)                                        */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk      (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DF_WD  ========================================================= */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Pos    (0UL)          /*!< TMDB_LL (Bit 0)                                       */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Msk    (0xffUL)       /*!< TMDB_LL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Pos    (8UL)          /*!< TMDB_LH (Bit 8)                                       */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Msk    (0xff00UL)     /*!< TMDB_LH (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Pos    (16UL)         /*!< TMDB_HL (Bit 16)                                      */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Msk    (0xff0000UL)   /*!< TMDB_HL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Pos    (24UL)         /*!< TMDB_HH (Bit 24)                                      */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Msk    (0xff000000UL) /*!< TMDB_HH (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDTM_DF_TMDB_Pos          (0UL)          /*!< TMDB (Bit 0)                                          */
+ #define R_CANFD_CFDTM_DF_TMDB_Msk          (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            CM                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+ #define R_CMT_UNT_CM_CR_CKS_Pos     (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_CMT_UNT_CM_CR_CKS_Msk     (0x3UL)  /*!< CKS (Bitfield-Mask: 0x03)                             */
+ #define R_CMT_UNT_CM_CR_CMIE_Pos    (6UL)    /*!< CMIE (Bit 6)                                          */
+ #define R_CMT_UNT_CM_CR_CMIE_Msk    (0x40UL) /*!< CMIE (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CNT  ========================================================== */
+/* ==========================================================  COR  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                            UNT                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CMSTR0  ========================================================= */
+ #define R_CMT_UNT_CMSTR0_STR0_Pos    (0UL)   /*!< STR0 (Bit 0)                                          */
+ #define R_CMT_UNT_CMSTR0_STR0_Msk    (0x1UL) /*!< STR0 (Bitfield-Mask: 0x01)                            */
+ #define R_CMT_UNT_CMSTR0_STR1_Pos    (1UL)   /*!< STR1 (Bit 1)                                          */
+ #define R_CMT_UNT_CMSTR0_STR1_Msk    (0x2UL) /*!< STR1 (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            SAR                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_IIC0_SAR_L_SVA0_Pos    (0UL)    /*!< SVA0 (Bit 0)                                          */
+ #define R_IIC0_SAR_L_SVA0_Msk    (0x1UL)  /*!< SVA0 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_SAR_L_SVA_Pos     (1UL)    /*!< SVA (Bit 1)                                           */
+ #define R_IIC0_SAR_L_SVA_Msk     (0xfeUL) /*!< SVA (Bitfield-Mask: 0x7f)                             */
+/* ===========================================================  U  =========================================================== */
+ #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
+ #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_SAR_U_SVA_Pos     (1UL)    /*!< SVA (Bit 1)                                           */
+ #define R_IIC0_SAR_U_SVA_Msk     (0x6UL)  /*!< SVA (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                             N                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SA  =========================================================== */
+/* ==========================================================  DA  =========================================================== */
+/* ==========================================================  TB  =========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                            CH                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CRSA  ========================================================== */
+/* =========================================================  CRDA  ========================================================== */
+/* =========================================================  CRTB  ========================================================== */
+/* ========================================================  CHSTAT  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHSTAT_EN_Pos         (0UL)          /*!< EN (Bit 0)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_EN_Msk         (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_RQST_Pos       (1UL)          /*!< RQST (Bit 1)                                          */
+ #define R_DMAC0_GRP_CH_CHSTAT_RQST_Msk       (0x2UL)        /*!< RQST (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_TACT_Pos       (2UL)          /*!< TACT (Bit 2)                                          */
+ #define R_DMAC0_GRP_CH_CHSTAT_TACT_Msk       (0x4UL)        /*!< TACT (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_SUS_Pos        (3UL)          /*!< SUS (Bit 3)                                           */
+ #define R_DMAC0_GRP_CH_CHSTAT_SUS_Msk        (0x8UL)        /*!< SUS (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHSTAT_ER_Pos         (4UL)          /*!< ER (Bit 4)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_ER_Msk         (0x10UL)       /*!< ER (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_END_Pos        (5UL)          /*!< END (Bit 5)                                           */
+ #define R_DMAC0_GRP_CH_CHSTAT_END_Msk        (0x20UL)       /*!< END (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHSTAT_TC_Pos         (6UL)          /*!< TC (Bit 6)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_TC_Msk         (0x40UL)       /*!< TC (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_SR_Pos         (7UL)          /*!< SR (Bit 7)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_SR_Msk         (0x80UL)       /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_DL_Pos         (8UL)          /*!< DL (Bit 8)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_DL_Msk         (0x100UL)      /*!< DL (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_DW_Pos         (9UL)          /*!< DW (Bit 9)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_DW_Msk         (0x200UL)      /*!< DW (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_DER_Pos        (10UL)         /*!< DER (Bit 10)                                          */
+ #define R_DMAC0_GRP_CH_CHSTAT_DER_Msk        (0x400UL)      /*!< DER (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHSTAT_MODE_Pos       (11UL)         /*!< MODE (Bit 11)                                         */
+ #define R_DMAC0_GRP_CH_CHSTAT_MODE_Msk       (0x800UL)      /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_INTM_Pos       (16UL)         /*!< INTM (Bit 16)                                         */
+ #define R_DMAC0_GRP_CH_CHSTAT_INTM_Msk       (0x10000UL)    /*!< INTM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CHCTRL  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Pos      (0UL)          /*!< SETEN (Bit 0)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Msk      (0x1UL)        /*!< SETEN (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Pos      (1UL)          /*!< CLREN (Bit 1)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Msk      (0x2UL)        /*!< CLREN (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_STG_Pos        (2UL)          /*!< STG (Bit 2)                                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_STG_Msk        (0x4UL)        /*!< STG (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Pos      (3UL)          /*!< SWRST (Bit 3)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Msk      (0x8UL)        /*!< SWRST (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Pos      (4UL)          /*!< CLRRQ (Bit 4)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Msk      (0x10UL)       /*!< CLRRQ (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Pos     (5UL)          /*!< CLREND (Bit 5)                                        */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Msk     (0x20UL)       /*!< CLREND (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Pos      (6UL)          /*!< CLRTC (Bit 6)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Msk      (0x40UL)       /*!< CLRTC (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Pos     (8UL)          /*!< SETSUS (Bit 8)                                        */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Msk     (0x100UL)      /*!< SETSUS (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Pos     (9UL)          /*!< CLRSUS (Bit 9)                                        */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Msk     (0x200UL)      /*!< CLRSUS (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Pos    (16UL)         /*!< SETINTM (Bit 16)                                      */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Msk    (0x10000UL)    /*!< SETINTM (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Pos    (17UL)         /*!< CLRINTM (Bit 17)                                      */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Msk    (0x20000UL)    /*!< CLRINTM (Bitfield-Mask: 0x01)                         */
+/* =========================================================  CHCFG  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHCFG_SEL_Pos         (0UL)          /*!< SEL (Bit 0)                                           */
+ #define R_DMAC0_GRP_CH_CHCFG_SEL_Msk         (0x7UL)        /*!< SEL (Bitfield-Mask: 0x07)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_REQD_Pos        (3UL)          /*!< REQD (Bit 3)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_REQD_Msk        (0x8UL)        /*!< REQD (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHCFG_LOEN_Pos        (4UL)          /*!< LOEN (Bit 4)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_LOEN_Msk        (0x10UL)       /*!< LOEN (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHCFG_HIEN_Pos        (5UL)          /*!< HIEN (Bit 5)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_HIEN_Msk        (0x20UL)       /*!< HIEN (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHCFG_LVL_Pos         (6UL)          /*!< LVL (Bit 6)                                           */
+ #define R_DMAC0_GRP_CH_CHCFG_LVL_Msk         (0x40UL)       /*!< LVL (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_AM_Pos          (8UL)          /*!< AM (Bit 8)                                            */
+ #define R_DMAC0_GRP_CH_CHCFG_AM_Msk          (0x700UL)      /*!< AM (Bitfield-Mask: 0x07)                              */
+ #define R_DMAC0_GRP_CH_CHCFG_SDS_Pos         (12UL)         /*!< SDS (Bit 12)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_SDS_Msk         (0xf000UL)     /*!< SDS (Bitfield-Mask: 0x0f)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_DDS_Pos         (16UL)         /*!< DDS (Bit 16)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_DDS_Msk         (0xf0000UL)    /*!< DDS (Bitfield-Mask: 0x0f)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_SAD_Pos         (20UL)         /*!< SAD (Bit 20)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_SAD_Msk         (0x100000UL)   /*!< SAD (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_DAD_Pos         (21UL)         /*!< DAD (Bit 21)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_DAD_Msk         (0x200000UL)   /*!< DAD (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_TM_Pos          (22UL)         /*!< TM (Bit 22)                                           */
+ #define R_DMAC0_GRP_CH_CHCFG_TM_Msk          (0x400000UL)   /*!< TM (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHCFG_DEM_Pos         (24UL)         /*!< DEM (Bit 24)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_DEM_Msk         (0x1000000UL)  /*!< DEM (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_TCM_Pos         (25UL)         /*!< TCM (Bit 25)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_TCM_Msk         (0x2000000UL)  /*!< TCM (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_SBE_Pos         (27UL)         /*!< SBE (Bit 27)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_SBE_Msk         (0x8000000UL)  /*!< SBE (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_RSEL_Pos        (28UL)         /*!< RSEL (Bit 28)                                         */
+ #define R_DMAC0_GRP_CH_CHCFG_RSEL_Msk        (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHCFG_RSW_Pos         (29UL)         /*!< RSW (Bit 29)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_RSW_Msk         (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_REN_Pos         (30UL)         /*!< REN (Bit 30)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_REN_Msk         (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_DMS_Pos         (31UL)         /*!< DMS (Bit 31)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_DMS_Msk         (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CHITVL  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHITVL_ITVL_Pos       (0UL)          /*!< ITVL (Bit 0)                                          */
+ #define R_DMAC0_GRP_CH_CHITVL_ITVL_Msk       (0xffffUL)     /*!< ITVL (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  CHEXT  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHEXT_SPR_Pos         (0UL)          /*!< SPR (Bit 0)                                           */
+ #define R_DMAC0_GRP_CH_CHEXT_SPR_Msk         (0x7UL)        /*!< SPR (Bitfield-Mask: 0x07)                             */
+ #define R_DMAC0_GRP_CH_CHEXT_SCA_Pos         (4UL)          /*!< SCA (Bit 4)                                           */
+ #define R_DMAC0_GRP_CH_CHEXT_SCA_Msk         (0xf0UL)       /*!< SCA (Bitfield-Mask: 0x0f)                             */
+ #define R_DMAC0_GRP_CH_CHEXT_DPR_Pos         (8UL)          /*!< DPR (Bit 8)                                           */
+ #define R_DMAC0_GRP_CH_CHEXT_DPR_Msk         (0x700UL)      /*!< DPR (Bitfield-Mask: 0x07)                             */
+ #define R_DMAC0_GRP_CH_CHEXT_DCA_Pos         (12UL)         /*!< DCA (Bit 12)                                          */
+ #define R_DMAC0_GRP_CH_CHEXT_DCA_Msk         (0xf000UL)     /*!< DCA (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  NXLA  ========================================================== */
+/* =========================================================  CRLA  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                            GRP                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DCTRL  ========================================================= */
+ #define R_DMAC0_GRP_DCTRL_PR_Pos           (0UL)    /*!< PR (Bit 0)                                            */
+ #define R_DMAC0_GRP_DCTRL_PR_Msk           (0x1UL)  /*!< PR (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_DCTRL_LVINT_Pos        (1UL)    /*!< LVINT (Bit 1)                                         */
+ #define R_DMAC0_GRP_DCTRL_LVINT_Msk        (0x2UL)  /*!< LVINT (Bitfield-Mask: 0x01)                           */
+/* =======================================================  DSTAT_EN  ======================================================== */
+ #define R_DMAC0_GRP_DSTAT_EN_EN00_Pos      (0UL)    /*!< EN00 (Bit 0)                                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN00_Msk      (0x1UL)  /*!< EN00 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_EN_EN01_Pos      (1UL)    /*!< EN01 (Bit 1)                                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN01_Msk      (0x2UL)  /*!< EN01 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_EN_EN02_Pos      (2UL)    /*!< EN02 (Bit 2)                                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN02_Msk      (0x4UL)  /*!< EN02 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_EN_EN03_Pos      (3UL)    /*!< EN03 (Bit 3)                                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN03_Msk      (0x8UL)  /*!< EN03 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_EN_EN04_Pos      (4UL)    /*!< EN04 (Bit 4)                                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN04_Msk      (0x10UL) /*!< EN04 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_EN_EN05_Pos      (5UL)    /*!< EN05 (Bit 5)                                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN05_Msk      (0x20UL) /*!< EN05 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_EN_EN06_Pos      (6UL)    /*!< EN06 (Bit 6)                                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN06_Msk      (0x40UL) /*!< EN06 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_EN_EN07_Pos      (7UL)    /*!< EN07 (Bit 7)                                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN07_Msk      (0x80UL) /*!< EN07 (Bitfield-Mask: 0x01)                            */
+/* =======================================================  DSTAT_ER  ======================================================== */
+ #define R_DMAC0_GRP_DSTAT_ER_ER00_Pos      (0UL)    /*!< ER00 (Bit 0)                                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER00_Msk      (0x1UL)  /*!< ER00 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_ER_ER01_Pos      (1UL)    /*!< ER01 (Bit 1)                                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER01_Msk      (0x2UL)  /*!< ER01 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_ER_ER02_Pos      (2UL)    /*!< ER02 (Bit 2)                                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER02_Msk      (0x4UL)  /*!< ER02 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_ER_ER03_Pos      (3UL)    /*!< ER03 (Bit 3)                                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER03_Msk      (0x8UL)  /*!< ER03 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_ER_ER04_Pos      (4UL)    /*!< ER04 (Bit 4)                                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER04_Msk      (0x10UL) /*!< ER04 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_ER_ER05_Pos      (5UL)    /*!< ER05 (Bit 5)                                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER05_Msk      (0x20UL) /*!< ER05 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_ER_ER06_Pos      (6UL)    /*!< ER06 (Bit 6)                                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER06_Msk      (0x40UL) /*!< ER06 (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_DSTAT_ER_ER07_Pos      (7UL)    /*!< ER07 (Bit 7)                                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER07_Msk      (0x80UL) /*!< ER07 (Bitfield-Mask: 0x01)                            */
+/* =======================================================  DSTAT_END  ======================================================= */
+ #define R_DMAC0_GRP_DSTAT_END_END00_Pos    (0UL)    /*!< END00 (Bit 0)                                         */
+ #define R_DMAC0_GRP_DSTAT_END_END00_Msk    (0x1UL)  /*!< END00 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_END_END01_Pos    (1UL)    /*!< END01 (Bit 1)                                         */
+ #define R_DMAC0_GRP_DSTAT_END_END01_Msk    (0x2UL)  /*!< END01 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_END_END02_Pos    (2UL)    /*!< END02 (Bit 2)                                         */
+ #define R_DMAC0_GRP_DSTAT_END_END02_Msk    (0x4UL)  /*!< END02 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_END_END03_Pos    (3UL)    /*!< END03 (Bit 3)                                         */
+ #define R_DMAC0_GRP_DSTAT_END_END03_Msk    (0x8UL)  /*!< END03 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_END_END04_Pos    (4UL)    /*!< END04 (Bit 4)                                         */
+ #define R_DMAC0_GRP_DSTAT_END_END04_Msk    (0x10UL) /*!< END04 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_END_END05_Pos    (5UL)    /*!< END05 (Bit 5)                                         */
+ #define R_DMAC0_GRP_DSTAT_END_END05_Msk    (0x20UL) /*!< END05 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_END_END06_Pos    (6UL)    /*!< END06 (Bit 6)                                         */
+ #define R_DMAC0_GRP_DSTAT_END_END06_Msk    (0x40UL) /*!< END06 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_END_END07_Pos    (7UL)    /*!< END07 (Bit 7)                                         */
+ #define R_DMAC0_GRP_DSTAT_END_END07_Msk    (0x80UL) /*!< END07 (Bitfield-Mask: 0x01)                           */
+/* =======================================================  DSTAT_SUS  ======================================================= */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS00_Pos    (0UL)    /*!< SUS00 (Bit 0)                                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS00_Msk    (0x1UL)  /*!< SUS00 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS01_Pos    (1UL)    /*!< SUS01 (Bit 1)                                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS01_Msk    (0x2UL)  /*!< SUS01 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS02_Pos    (2UL)    /*!< SUS02 (Bit 2)                                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS02_Msk    (0x4UL)  /*!< SUS02 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS03_Pos    (3UL)    /*!< SUS03 (Bit 3)                                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS03_Msk    (0x8UL)  /*!< SUS03 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS04_Pos    (4UL)    /*!< SUS04 (Bit 4)                                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS04_Msk    (0x10UL) /*!< SUS04 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS05_Pos    (5UL)    /*!< SUS05 (Bit 5)                                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS05_Msk    (0x20UL) /*!< SUS05 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS06_Pos    (6UL)    /*!< SUS06 (Bit 6)                                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS06_Msk    (0x40UL) /*!< SUS06 (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS07_Pos    (7UL)    /*!< SUS07 (Bit 7)                                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS07_Msk    (0x80UL) /*!< SUS07 (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           DRCTL                                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_PORT_NSR_DRCTL_L_DRV0_Pos    (0UL)          /*!< DRV0 (Bit 0)                                          */
+ #define R_PORT_NSR_DRCTL_L_DRV0_Msk    (0x3UL)        /*!< DRV0 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_PUD0_Pos    (2UL)          /*!< PUD0 (Bit 2)                                          */
+ #define R_PORT_NSR_DRCTL_L_PUD0_Msk    (0xcUL)        /*!< PUD0 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_SMT0_Pos    (4UL)          /*!< SMT0 (Bit 4)                                          */
+ #define R_PORT_NSR_DRCTL_L_SMT0_Msk    (0x10UL)       /*!< SMT0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_L_SR0_Pos     (5UL)          /*!< SR0 (Bit 5)                                           */
+ #define R_PORT_NSR_DRCTL_L_SR0_Msk     (0x20UL)       /*!< SR0 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_L_DRV1_Pos    (8UL)          /*!< DRV1 (Bit 8)                                          */
+ #define R_PORT_NSR_DRCTL_L_DRV1_Msk    (0x300UL)      /*!< DRV1 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_PUD1_Pos    (10UL)         /*!< PUD1 (Bit 10)                                         */
+ #define R_PORT_NSR_DRCTL_L_PUD1_Msk    (0xc00UL)      /*!< PUD1 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_SMT1_Pos    (12UL)         /*!< SMT1 (Bit 12)                                         */
+ #define R_PORT_NSR_DRCTL_L_SMT1_Msk    (0x1000UL)     /*!< SMT1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_L_SR1_Pos     (13UL)         /*!< SR1 (Bit 13)                                          */
+ #define R_PORT_NSR_DRCTL_L_SR1_Msk     (0x2000UL)     /*!< SR1 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_L_DRV2_Pos    (16UL)         /*!< DRV2 (Bit 16)                                         */
+ #define R_PORT_NSR_DRCTL_L_DRV2_Msk    (0x30000UL)    /*!< DRV2 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_PUD2_Pos    (18UL)         /*!< PUD2 (Bit 18)                                         */
+ #define R_PORT_NSR_DRCTL_L_PUD2_Msk    (0xc0000UL)    /*!< PUD2 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_SMT2_Pos    (20UL)         /*!< SMT2 (Bit 20)                                         */
+ #define R_PORT_NSR_DRCTL_L_SMT2_Msk    (0x100000UL)   /*!< SMT2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_L_SR2_Pos     (21UL)         /*!< SR2 (Bit 21)                                          */
+ #define R_PORT_NSR_DRCTL_L_SR2_Msk     (0x200000UL)   /*!< SR2 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_L_DRV3_Pos    (24UL)         /*!< DRV3 (Bit 24)                                         */
+ #define R_PORT_NSR_DRCTL_L_DRV3_Msk    (0x3000000UL)  /*!< DRV3 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_PUD3_Pos    (26UL)         /*!< PUD3 (Bit 26)                                         */
+ #define R_PORT_NSR_DRCTL_L_PUD3_Msk    (0xc000000UL)  /*!< PUD3 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_SMT3_Pos    (28UL)         /*!< SMT3 (Bit 28)                                         */
+ #define R_PORT_NSR_DRCTL_L_SMT3_Msk    (0x10000000UL) /*!< SMT3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_L_SR3_Pos     (29UL)         /*!< SR3 (Bit 29)                                          */
+ #define R_PORT_NSR_DRCTL_L_SR3_Msk     (0x20000000UL) /*!< SR3 (Bitfield-Mask: 0x01)                             */
+/* ===========================================================  H  =========================================================== */
+ #define R_PORT_NSR_DRCTL_H_DRV4_Pos    (0UL)          /*!< DRV4 (Bit 0)                                          */
+ #define R_PORT_NSR_DRCTL_H_DRV4_Msk    (0x3UL)        /*!< DRV4 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_PUD4_Pos    (2UL)          /*!< PUD4 (Bit 2)                                          */
+ #define R_PORT_NSR_DRCTL_H_PUD4_Msk    (0xcUL)        /*!< PUD4 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_SMT4_Pos    (4UL)          /*!< SMT4 (Bit 4)                                          */
+ #define R_PORT_NSR_DRCTL_H_SMT4_Msk    (0x10UL)       /*!< SMT4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_H_SR4_Pos     (5UL)          /*!< SR4 (Bit 5)                                           */
+ #define R_PORT_NSR_DRCTL_H_SR4_Msk     (0x20UL)       /*!< SR4 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_H_DRV5_Pos    (8UL)          /*!< DRV5 (Bit 8)                                          */
+ #define R_PORT_NSR_DRCTL_H_DRV5_Msk    (0x300UL)      /*!< DRV5 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_PUD5_Pos    (10UL)         /*!< PUD5 (Bit 10)                                         */
+ #define R_PORT_NSR_DRCTL_H_PUD5_Msk    (0xc00UL)      /*!< PUD5 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_SMT5_Pos    (12UL)         /*!< SMT5 (Bit 12)                                         */
+ #define R_PORT_NSR_DRCTL_H_SMT5_Msk    (0x1000UL)     /*!< SMT5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_H_SR5_Pos     (13UL)         /*!< SR5 (Bit 13)                                          */
+ #define R_PORT_NSR_DRCTL_H_SR5_Msk     (0x2000UL)     /*!< SR5 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_H_DRV6_Pos    (16UL)         /*!< DRV6 (Bit 16)                                         */
+ #define R_PORT_NSR_DRCTL_H_DRV6_Msk    (0x30000UL)    /*!< DRV6 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_PUD6_Pos    (18UL)         /*!< PUD6 (Bit 18)                                         */
+ #define R_PORT_NSR_DRCTL_H_PUD6_Msk    (0xc0000UL)    /*!< PUD6 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_SMT6_Pos    (20UL)         /*!< SMT6 (Bit 20)                                         */
+ #define R_PORT_NSR_DRCTL_H_SMT6_Msk    (0x100000UL)   /*!< SMT6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_H_SR6_Pos     (21UL)         /*!< SR6 (Bit 21)                                          */
+ #define R_PORT_NSR_DRCTL_H_SR6_Msk     (0x200000UL)   /*!< SR6 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_H_DRV7_Pos    (24UL)         /*!< DRV7 (Bit 24)                                         */
+ #define R_PORT_NSR_DRCTL_H_DRV7_Msk    (0x3000000UL)  /*!< DRV7 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_PUD7_Pos    (26UL)         /*!< PUD7 (Bit 26)                                         */
+ #define R_PORT_NSR_DRCTL_H_PUD7_Msk    (0xc000000UL)  /*!< PUD7 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_SMT7_Pos    (28UL)         /*!< SMT7 (Bit 28)                                         */
+ #define R_PORT_NSR_DRCTL_H_SMT7_Msk    (0x10000000UL) /*!< SMT7 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_H_SR7_Pos     (29UL)         /*!< SR7 (Bit 29)                                          */
+ #define R_PORT_NSR_DRCTL_H_SR7_Msk     (0x20000000UL) /*!< SR7 (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                         ELC_PDBF                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  BY  =========================================================== */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB0_Pos    (0UL)    /*!< PB0 (Bit 0)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB0_Msk    (0x1UL)  /*!< PB0 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB1_Pos    (1UL)    /*!< PB1 (Bit 1)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB1_Msk    (0x2UL)  /*!< PB1 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB2_Pos    (2UL)    /*!< PB2 (Bit 2)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB2_Msk    (0x4UL)  /*!< PB2 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB3_Pos    (3UL)    /*!< PB3 (Bit 3)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB3_Msk    (0x8UL)  /*!< PB3 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB4_Pos    (4UL)    /*!< PB4 (Bit 4)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB4_Msk    (0x10UL) /*!< PB4 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB5_Pos    (5UL)    /*!< PB5 (Bit 5)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB5_Msk    (0x20UL) /*!< PB5 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB6_Pos    (6UL)    /*!< PB6 (Bit 6)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB6_Msk    (0x40UL) /*!< PB6 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB7_Pos    (7UL)    /*!< PB7 (Bit 7)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB7_Msk    (0x80UL) /*!< PB7 (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           SWTM                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  EN  =========================================================== */
+ #define R_ETHSW_PTP_SWTM_EN_OUTEN_Pos         (0UL)          /*!< OUTEN (Bit 0)                                         */
+ #define R_ETHSW_PTP_SWTM_EN_OUTEN_Msk         (0x1UL)        /*!< OUTEN (Bitfield-Mask: 0x01)                           */
+/* =========================================================  STSEC  ========================================================= */
+ #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Pos      (0UL)          /*!< STSEC (Bit 0)                                         */
+ #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Msk      (0xffffffffUL) /*!< STSEC (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  STNS  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_STNS_STNS_Pos        (0UL)          /*!< STNS (Bit 0)                                          */
+ #define R_ETHSW_PTP_SWTM_STNS_STNS_Msk        (0xffffffffUL) /*!< STNS (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  PSEC  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Pos        (0UL)          /*!< PSEC (Bit 0)                                          */
+ #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Msk        (0xffffffffUL) /*!< PSEC (Bitfield-Mask: 0xffffffff)                      */
+/* ==========================================================  PNS  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_PNS_PNS_Pos          (0UL)          /*!< PNS (Bit 0)                                           */
+ #define R_ETHSW_PTP_SWTM_PNS_PNS_Msk          (0xffffffffUL) /*!< PNS (Bitfield-Mask: 0xffffffff)                       */
+/* ==========================================================  WTH  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Pos        (0UL)          /*!< WIDTH (Bit 0)                                         */
+ #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Msk        (0xffffUL)     /*!< WIDTH (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  MAXP  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Pos        (0UL)          /*!< MAXP (Bit 0)                                          */
+ #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Msk        (0xffffffffUL) /*!< MAXP (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  LATSEC  ========================================================= */
+ #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Pos    (0UL)          /*!< LATSEC (Bit 0)                                        */
+ #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Msk    (0xffffffffUL) /*!< LATSEC (Bitfield-Mask: 0xffffffff)                    */
+/* =========================================================  LATNS  ========================================================= */
+ #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Pos      (0UL)          /*!< LATNS (Bit 0)                                         */
+ #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Msk      (0xffffffffUL) /*!< LATNS (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                         MGMT_ADDR                                         ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  lo  =========================================================== */
+ #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Pos    (0UL)          /*!< BPDU_DST (Bit 0)                                      */
+ #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Msk    (0xffffffffUL) /*!< BPDU_DST (Bitfield-Mask: 0xffffffff)                  */
+/* ==========================================================  hi  =========================================================== */
+ #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Pos    (0UL)          /*!< BPDU_DST (Bit 0)                                      */
+ #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Msk    (0xffffUL)     /*!< BPDU_DST (Bitfield-Mask: 0xffff)                      */
+ #define R_ETHSW_MGMT_ADDR_hi_MASK_Pos        (16UL)         /*!< MASK (Bit 16)                                         */
+ #define R_ETHSW_MGMT_ADDR_hi_MASK_Msk        (0xff0000UL)   /*!< MASK (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           FMMU                                            ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  L_START_ADR  ====================================================== */
+ #define R_ESC_FMMU_L_START_ADR_LSTAADR_Pos      (0UL)          /*!< LSTAADR (Bit 0)                                       */
+ #define R_ESC_FMMU_L_START_ADR_LSTAADR_Msk      (0xffffffffUL) /*!< LSTAADR (Bitfield-Mask: 0xffffffff)                   */
+/* ==========================================================  LEN  ========================================================== */
+ #define R_ESC_FMMU_LEN_FMMULEN_Pos              (0UL)          /*!< FMMULEN (Bit 0)                                       */
+ #define R_ESC_FMMU_LEN_FMMULEN_Msk              (0xffffUL)     /*!< FMMULEN (Bitfield-Mask: 0xffff)                       */
+/* ======================================================  L_START_BIT  ====================================================== */
+ #define R_ESC_FMMU_L_START_BIT_LSTABIT_Pos      (0UL)          /*!< LSTABIT (Bit 0)                                       */
+ #define R_ESC_FMMU_L_START_BIT_LSTABIT_Msk      (0x7UL)        /*!< LSTABIT (Bitfield-Mask: 0x07)                         */
+/* ======================================================  L_STOP_BIT  ======================================================= */
+ #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Pos       (0UL)          /*!< LSTPBIT (Bit 0)                                       */
+ #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Msk       (0x7UL)        /*!< LSTPBIT (Bitfield-Mask: 0x07)                         */
+/* ======================================================  P_START_ADR  ====================================================== */
+ #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Pos    (0UL)          /*!< PHYSTAADR (Bit 0)                                     */
+ #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Msk    (0xffffUL)     /*!< PHYSTAADR (Bitfield-Mask: 0xffff)                     */
+/* ======================================================  P_START_BIT  ====================================================== */
+ #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Pos    (0UL)          /*!< PHYSTABIT (Bit 0)                                     */
+ #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Msk    (0x7UL)        /*!< PHYSTABIT (Bitfield-Mask: 0x07)                       */
+/* =========================================================  TYPE  ========================================================== */
+ #define R_ESC_FMMU_TYPE_READ_Pos                (0UL)          /*!< READ (Bit 0)                                          */
+ #define R_ESC_FMMU_TYPE_READ_Msk                (0x1UL)        /*!< READ (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_FMMU_TYPE_WRITE_Pos               (1UL)          /*!< WRITE (Bit 1)                                         */
+ #define R_ESC_FMMU_TYPE_WRITE_Msk               (0x2UL)        /*!< WRITE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  ACT  ========================================================== */
+ #define R_ESC_FMMU_ACT_ACTIVATE_Pos             (0UL)          /*!< ACTIVATE (Bit 0)                                      */
+ #define R_ESC_FMMU_ACT_ACTIVATE_Msk             (0x1UL)        /*!< ACTIVATE (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                            SM                                             ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  P_START_ADR  ====================================================== */
+ #define R_ESC_SM_P_START_ADR_SMSTAADDR_Pos    (0UL)      /*!< SMSTAADDR (Bit 0)                                     */
+ #define R_ESC_SM_P_START_ADR_SMSTAADDR_Msk    (0xffffUL) /*!< SMSTAADDR (Bitfield-Mask: 0xffff)                     */
+/* ==========================================================  LEN  ========================================================== */
+ #define R_ESC_SM_LEN_SMLEN_Pos                (0UL)      /*!< SMLEN (Bit 0)                                         */
+ #define R_ESC_SM_LEN_SMLEN_Msk                (0xffffUL) /*!< SMLEN (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  CONTROL  ======================================================== */
+ #define R_ESC_SM_CONTROL_OPEMODE_Pos          (0UL)      /*!< OPEMODE (Bit 0)                                       */
+ #define R_ESC_SM_CONTROL_OPEMODE_Msk          (0x3UL)    /*!< OPEMODE (Bitfield-Mask: 0x03)                         */
+ #define R_ESC_SM_CONTROL_DIR_Pos              (2UL)      /*!< DIR (Bit 2)                                           */
+ #define R_ESC_SM_CONTROL_DIR_Msk              (0xcUL)    /*!< DIR (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_SM_CONTROL_IRQECAT_Pos          (4UL)      /*!< IRQECAT (Bit 4)                                       */
+ #define R_ESC_SM_CONTROL_IRQECAT_Msk          (0x10UL)   /*!< IRQECAT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_SM_CONTROL_IRQPDI_Pos           (5UL)      /*!< IRQPDI (Bit 5)                                        */
+ #define R_ESC_SM_CONTROL_IRQPDI_Msk           (0x20UL)   /*!< IRQPDI (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_SM_CONTROL_WDTRGEN_Pos          (6UL)      /*!< WDTRGEN (Bit 6)                                       */
+ #define R_ESC_SM_CONTROL_WDTRGEN_Msk          (0x40UL)   /*!< WDTRGEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  STATUS  ========================================================= */
+ #define R_ESC_SM_STATUS_INTWR_Pos             (0UL)      /*!< INTWR (Bit 0)                                         */
+ #define R_ESC_SM_STATUS_INTWR_Msk             (0x1UL)    /*!< INTWR (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_SM_STATUS_INTRD_Pos             (1UL)      /*!< INTRD (Bit 1)                                         */
+ #define R_ESC_SM_STATUS_INTRD_Msk             (0x2UL)    /*!< INTRD (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_SM_STATUS_MAILBOX_Pos           (3UL)      /*!< MAILBOX (Bit 3)                                       */
+ #define R_ESC_SM_STATUS_MAILBOX_Msk           (0x8UL)    /*!< MAILBOX (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_SM_STATUS_BUFFERED_Pos          (4UL)      /*!< BUFFERED (Bit 4)                                      */
+ #define R_ESC_SM_STATUS_BUFFERED_Msk          (0x30UL)   /*!< BUFFERED (Bitfield-Mask: 0x03)                        */
+ #define R_ESC_SM_STATUS_RDBUF_Pos             (6UL)      /*!< RDBUF (Bit 6)                                         */
+ #define R_ESC_SM_STATUS_RDBUF_Msk             (0x40UL)   /*!< RDBUF (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_SM_STATUS_WRBUF_Pos             (7UL)      /*!< WRBUF (Bit 7)                                         */
+ #define R_ESC_SM_STATUS_WRBUF_Msk             (0x80UL)   /*!< WRBUF (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  ACT  ========================================================== */
+ #define R_ESC_SM_ACT_SMEN_Pos                 (0UL)      /*!< SMEN (Bit 0)                                          */
+ #define R_ESC_SM_ACT_SMEN_Msk                 (0x1UL)    /*!< SMEN (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_SM_ACT_REPEATREQ_Pos            (1UL)      /*!< REPEATREQ (Bit 1)                                     */
+ #define R_ESC_SM_ACT_REPEATREQ_Msk            (0x2UL)    /*!< REPEATREQ (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_SM_ACT_LATCHECAT_Pos            (6UL)      /*!< LATCHECAT (Bit 6)                                     */
+ #define R_ESC_SM_ACT_LATCHECAT_Msk            (0x40UL)   /*!< LATCHECAT (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_SM_ACT_LATCHPDI_Pos             (7UL)      /*!< LATCHPDI (Bit 7)                                      */
+ #define R_ESC_SM_ACT_LATCHPDI_Msk             (0x80UL)   /*!< LATCHPDI (Bitfield-Mask: 0x01)                        */
+/* =======================================================  PDI_CONT  ======================================================== */
+ #define R_ESC_SM_PDI_CONT_DEACTIVE_Pos        (0UL)      /*!< DEACTIVE (Bit 0)                                      */
+ #define R_ESC_SM_PDI_CONT_DEACTIVE_Msk        (0x1UL)    /*!< DEACTIVE (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_SM_PDI_CONT_REPEATACK_Pos       (1UL)      /*!< REPEATACK (Bit 1)                                     */
+ #define R_ESC_SM_PDI_CONT_REPEATACK_Msk       (0x2UL)    /*!< REPEATACK (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          PIPE_TR                                          ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  E  =========================================================== */
+ #define R_USBF_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
+ #define R_USBF_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
+ #define R_USBF_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
+/* ===========================================================  N  =========================================================== */
+ #define R_USBF_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
+ #define R_USBF_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                             N                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SA  =========================================================== */
+ #define R_USBF_CHa_N_SA_SAWD_Pos    (0UL)          /*!< SAWD (Bit 0)                                          */
+ #define R_USBF_CHa_N_SA_SAWD_Msk    (0xffffffffUL) /*!< SAWD (Bitfield-Mask: 0xffffffff)                      */
+/* ==========================================================  DA  =========================================================== */
+ #define R_USBF_CHa_N_DA_DA_Pos      (0UL)          /*!< DA (Bit 0)                                            */
+ #define R_USBF_CHa_N_DA_DA_Msk      (0xffffffffUL) /*!< DA (Bitfield-Mask: 0xffffffff)                        */
+/* ==========================================================  TB  =========================================================== */
+ #define R_USBF_CHa_N_TB_TB_Pos      (0UL)          /*!< TB (Bit 0)                                            */
+ #define R_USBF_CHa_N_TB_TB_Msk      (0xffffffffUL) /*!< TB (Bitfield-Mask: 0xffffffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                            CHa                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CRSA  ========================================================== */
+ #define R_USBF_CHa_CRSA_CRSA_Pos           (0UL)          /*!< CRSA (Bit 0)                                          */
+ #define R_USBF_CHa_CRSA_CRSA_Msk           (0xffffffffUL) /*!< CRSA (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CRDA  ========================================================== */
+ #define R_USBF_CHa_CRDA_CRDA_Pos           (0UL)          /*!< CRDA (Bit 0)                                          */
+ #define R_USBF_CHa_CRDA_CRDA_Msk           (0xffffffffUL) /*!< CRDA (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CRTB  ========================================================== */
+ #define R_USBF_CHa_CRTB_CRTB_Pos           (0UL)          /*!< CRTB (Bit 0)                                          */
+ #define R_USBF_CHa_CRTB_CRTB_Msk           (0xffffffffUL) /*!< CRTB (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  CHSTAT  ========================================================= */
+ #define R_USBF_CHa_CHSTAT_EN_Pos           (0UL)          /*!< EN (Bit 0)                                            */
+ #define R_USBF_CHa_CHSTAT_EN_Msk           (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_RQST_Pos         (1UL)          /*!< RQST (Bit 1)                                          */
+ #define R_USBF_CHa_CHSTAT_RQST_Msk         (0x2UL)        /*!< RQST (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHSTAT_TACT_Pos         (2UL)          /*!< TACT (Bit 2)                                          */
+ #define R_USBF_CHa_CHSTAT_TACT_Msk         (0x4UL)        /*!< TACT (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHSTAT_SUS_Pos          (3UL)          /*!< SUS (Bit 3)                                           */
+ #define R_USBF_CHa_CHSTAT_SUS_Msk          (0x8UL)        /*!< SUS (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHSTAT_ER_Pos           (4UL)          /*!< ER (Bit 4)                                            */
+ #define R_USBF_CHa_CHSTAT_ER_Msk           (0x10UL)       /*!< ER (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_END_Pos          (5UL)          /*!< END (Bit 5)                                           */
+ #define R_USBF_CHa_CHSTAT_END_Msk          (0x20UL)       /*!< END (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHSTAT_TC_Pos           (6UL)          /*!< TC (Bit 6)                                            */
+ #define R_USBF_CHa_CHSTAT_TC_Msk           (0x40UL)       /*!< TC (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_SR_Pos           (7UL)          /*!< SR (Bit 7)                                            */
+ #define R_USBF_CHa_CHSTAT_SR_Msk           (0x80UL)       /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_DL_Pos           (8UL)          /*!< DL (Bit 8)                                            */
+ #define R_USBF_CHa_CHSTAT_DL_Msk           (0x100UL)      /*!< DL (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_DW_Pos           (9UL)          /*!< DW (Bit 9)                                            */
+ #define R_USBF_CHa_CHSTAT_DW_Msk           (0x200UL)      /*!< DW (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_DER_Pos          (10UL)         /*!< DER (Bit 10)                                          */
+ #define R_USBF_CHa_CHSTAT_DER_Msk          (0x400UL)      /*!< DER (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHSTAT_MODE_Pos         (11UL)         /*!< MODE (Bit 11)                                         */
+ #define R_USBF_CHa_CHSTAT_MODE_Msk         (0x800UL)      /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHSTAT_INTM_Pos         (16UL)         /*!< INTM (Bit 16)                                         */
+ #define R_USBF_CHa_CHSTAT_INTM_Msk         (0x10000UL)    /*!< INTM (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHSTAT_DMARQM_Pos       (17UL)         /*!< DMARQM (Bit 17)                                       */
+ #define R_USBF_CHa_CHSTAT_DMARQM_Msk       (0x20000UL)    /*!< DMARQM (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHSTAT_SWPRQ_Pos        (18UL)         /*!< SWPRQ (Bit 18)                                        */
+ #define R_USBF_CHa_CHSTAT_SWPRQ_Msk        (0x40000UL)    /*!< SWPRQ (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHSTAT_DNUM_Pos         (24UL)         /*!< DNUM (Bit 24)                                         */
+ #define R_USBF_CHa_CHSTAT_DNUM_Msk         (0xff000000UL) /*!< DNUM (Bitfield-Mask: 0xff)                            */
+/* ========================================================  CHCTRL  ========================================================= */
+ #define R_USBF_CHa_CHCTRL_SETEN_Pos        (0UL)          /*!< SETEN (Bit 0)                                         */
+ #define R_USBF_CHa_CHCTRL_SETEN_Msk        (0x1UL)        /*!< SETEN (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_CLREN_Pos        (1UL)          /*!< CLREN (Bit 1)                                         */
+ #define R_USBF_CHa_CHCTRL_CLREN_Msk        (0x2UL)        /*!< CLREN (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_STG_Pos          (2UL)          /*!< STG (Bit 2)                                           */
+ #define R_USBF_CHa_CHCTRL_STG_Msk          (0x4UL)        /*!< STG (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCTRL_SWRST_Pos        (3UL)          /*!< SWRST (Bit 3)                                         */
+ #define R_USBF_CHa_CHCTRL_SWRST_Msk        (0x8UL)        /*!< SWRST (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_CLRRQ_Pos        (4UL)          /*!< CLRRQ (Bit 4)                                         */
+ #define R_USBF_CHa_CHCTRL_CLRRQ_Msk        (0x10UL)       /*!< CLRRQ (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_CLREND_Pos       (5UL)          /*!< CLREND (Bit 5)                                        */
+ #define R_USBF_CHa_CHCTRL_CLREND_Msk       (0x20UL)       /*!< CLREND (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_CLRTC_Pos        (6UL)          /*!< CLRTC (Bit 6)                                         */
+ #define R_USBF_CHa_CHCTRL_CLRTC_Msk        (0x40UL)       /*!< CLRTC (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_CLRDER_Pos       (7UL)          /*!< CLRDER (Bit 7)                                        */
+ #define R_USBF_CHa_CHCTRL_CLRDER_Msk       (0x80UL)       /*!< CLRDER (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_SETSUS_Pos       (8UL)          /*!< SETSUS (Bit 8)                                        */
+ #define R_USBF_CHa_CHCTRL_SETSUS_Msk       (0x100UL)      /*!< SETSUS (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_CLRSUS_Pos       (9UL)          /*!< CLRSUS (Bit 9)                                        */
+ #define R_USBF_CHa_CHCTRL_CLRSUS_Msk       (0x200UL)      /*!< CLRSUS (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_SETREN_Pos       (12UL)         /*!< SETREN (Bit 12)                                       */
+ #define R_USBF_CHa_CHCTRL_SETREN_Msk       (0x1000UL)     /*!< SETREN (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Pos    (14UL)         /*!< SETSSWPRQ (Bit 14)                                    */
+ #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Msk    (0x4000UL)     /*!< SETSSWPRQ (Bitfield-Mask: 0x01)                       */
+ #define R_USBF_CHa_CHCTRL_SETINTM_Pos      (16UL)         /*!< SETINTM (Bit 16)                                      */
+ #define R_USBF_CHa_CHCTRL_SETINTM_Msk      (0x10000UL)    /*!< SETINTM (Bitfield-Mask: 0x01)                         */
+ #define R_USBF_CHa_CHCTRL_CLRINTM_Pos      (17UL)         /*!< CLRINTM (Bit 17)                                      */
+ #define R_USBF_CHa_CHCTRL_CLRINTM_Msk      (0x20000UL)    /*!< CLRINTM (Bitfield-Mask: 0x01)                         */
+ #define R_USBF_CHa_CHCTRL_SETDMARQM_Pos    (18UL)         /*!< SETDMARQM (Bit 18)                                    */
+ #define R_USBF_CHa_CHCTRL_SETDMARQM_Msk    (0x40000UL)    /*!< SETDMARQM (Bitfield-Mask: 0x01)                       */
+ #define R_USBF_CHa_CHCTRL_CLRDMARQM_Pos    (19UL)         /*!< CLRDMARQM (Bit 19)                                    */
+ #define R_USBF_CHa_CHCTRL_CLRDMARQM_Msk    (0x80000UL)    /*!< CLRDMARQM (Bitfield-Mask: 0x01)                       */
+/* =========================================================  CHCFG  ========================================================= */
+ #define R_USBF_CHa_CHCFG_SEL_Pos           (0UL)          /*!< SEL (Bit 0)                                           */
+ #define R_USBF_CHa_CHCFG_SEL_Msk           (0x1UL)        /*!< SEL (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_REQD_Pos          (3UL)          /*!< REQD (Bit 3)                                          */
+ #define R_USBF_CHa_CHCFG_REQD_Msk          (0x8UL)        /*!< REQD (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_LOEN_Pos          (4UL)          /*!< LOEN (Bit 4)                                          */
+ #define R_USBF_CHa_CHCFG_LOEN_Msk          (0x10UL)       /*!< LOEN (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_HIEN_Pos          (5UL)          /*!< HIEN (Bit 5)                                          */
+ #define R_USBF_CHa_CHCFG_HIEN_Msk          (0x20UL)       /*!< HIEN (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_LVL_Pos           (6UL)          /*!< LVL (Bit 6)                                           */
+ #define R_USBF_CHa_CHCFG_LVL_Msk           (0x40UL)       /*!< LVL (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_AM_Pos            (8UL)          /*!< AM (Bit 8)                                            */
+ #define R_USBF_CHa_CHCFG_AM_Msk            (0x700UL)      /*!< AM (Bitfield-Mask: 0x07)                              */
+ #define R_USBF_CHa_CHCFG_DRRP_Pos          (11UL)         /*!< DRRP (Bit 11)                                         */
+ #define R_USBF_CHa_CHCFG_DRRP_Msk          (0x800UL)      /*!< DRRP (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_SDS_Pos           (12UL)         /*!< SDS (Bit 12)                                          */
+ #define R_USBF_CHa_CHCFG_SDS_Msk           (0xf000UL)     /*!< SDS (Bitfield-Mask: 0x0f)                             */
+ #define R_USBF_CHa_CHCFG_DDS_Pos           (16UL)         /*!< DDS (Bit 16)                                          */
+ #define R_USBF_CHa_CHCFG_DDS_Msk           (0xf0000UL)    /*!< DDS (Bitfield-Mask: 0x0f)                             */
+ #define R_USBF_CHa_CHCFG_SAD_Pos           (20UL)         /*!< SAD (Bit 20)                                          */
+ #define R_USBF_CHa_CHCFG_SAD_Msk           (0x100000UL)   /*!< SAD (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_DAD_Pos           (21UL)         /*!< DAD (Bit 21)                                          */
+ #define R_USBF_CHa_CHCFG_DAD_Msk           (0x200000UL)   /*!< DAD (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_TM_Pos            (22UL)         /*!< TM (Bit 22)                                           */
+ #define R_USBF_CHa_CHCFG_TM_Msk            (0x400000UL)   /*!< TM (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHCFG_WONLY_Pos         (23UL)         /*!< WONLY (Bit 23)                                        */
+ #define R_USBF_CHa_CHCFG_WONLY_Msk         (0x800000UL)   /*!< WONLY (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCFG_DEM_Pos           (24UL)         /*!< DEM (Bit 24)                                          */
+ #define R_USBF_CHa_CHCFG_DEM_Msk           (0x1000000UL)  /*!< DEM (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_DIM_Pos           (26UL)         /*!< DIM (Bit 26)                                          */
+ #define R_USBF_CHa_CHCFG_DIM_Msk           (0x4000000UL)  /*!< DIM (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_SBE_Pos           (27UL)         /*!< SBE (Bit 27)                                          */
+ #define R_USBF_CHa_CHCFG_SBE_Msk           (0x8000000UL)  /*!< SBE (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_RSEL_Pos          (28UL)         /*!< RSEL (Bit 28)                                         */
+ #define R_USBF_CHa_CHCFG_RSEL_Msk          (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_RSW_Pos           (29UL)         /*!< RSW (Bit 29)                                          */
+ #define R_USBF_CHa_CHCFG_RSW_Msk           (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_REN_Pos           (30UL)         /*!< REN (Bit 30)                                          */
+ #define R_USBF_CHa_CHCFG_REN_Msk           (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_DMS_Pos           (31UL)         /*!< DMS (Bit 31)                                          */
+ #define R_USBF_CHa_CHCFG_DMS_Msk           (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CHITVL  ========================================================= */
+ #define R_USBF_CHa_CHITVL_ITVL_Pos         (0UL)          /*!< ITVL (Bit 0)                                          */
+ #define R_USBF_CHa_CHITVL_ITVL_Msk         (0xffffUL)     /*!< ITVL (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  CHEXT  ========================================================= */
+ #define R_USBF_CHa_CHEXT_SPR_Pos           (0UL)          /*!< SPR (Bit 0)                                           */
+ #define R_USBF_CHa_CHEXT_SPR_Msk           (0xfUL)        /*!< SPR (Bitfield-Mask: 0x0f)                             */
+ #define R_USBF_CHa_CHEXT_DPR_Pos           (8UL)          /*!< DPR (Bit 8)                                           */
+ #define R_USBF_CHa_CHEXT_DPR_Msk           (0xf00UL)      /*!< DPR (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  NXLA  ========================================================== */
+ #define R_USBF_CHa_NXLA_NXLA_Pos           (0UL)          /*!< NXLA (Bit 0)                                          */
+ #define R_USBF_CHa_NXLA_NXLA_Msk           (0xffffffffUL) /*!< NXLA (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CRLA  ========================================================== */
+ #define R_USBF_CHa_CRLA_CRLA_Pos           (0UL)          /*!< CRLA (Bit 0)                                          */
+ #define R_USBF_CHa_CRLA_CRLA_Msk           (0xffffffffUL) /*!< CRLA (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                            CHb                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SCNT  ========================================================== */
+ #define R_USBF_CHb_SCNT_SCNT_Pos    (0UL)          /*!< SCNT (Bit 0)                                          */
+ #define R_USBF_CHb_SCNT_SCNT_Msk    (0xffffffffUL) /*!< SCNT (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  SSKP  ========================================================== */
+ #define R_USBF_CHb_SSKP_SSKP_Pos    (0UL)          /*!< SSKP (Bit 0)                                          */
+ #define R_USBF_CHb_SSKP_SSKP_Msk    (0xffffffffUL) /*!< SSKP (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  DCNT  ========================================================== */
+ #define R_USBF_CHb_DCNT_DCNT_Pos    (0UL)          /*!< DCNT (Bit 0)                                          */
+ #define R_USBF_CHb_DCNT_DCNT_Msk    (0xffffffffUL) /*!< DCNT (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  DSKP  ========================================================== */
+ #define R_USBF_CHb_DSKP_DSKP_Pos    (0UL)          /*!< DSKP (Bit 0)                                          */
+ #define R_USBF_CHb_DSKP_DSKP_Msk    (0xffffffffUL) /*!< DSKP (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                            CSa                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CMCFG0  ========================================================= */
+ #define R_XSPI0_CSa_CMCFG0_FFMT_Pos       (0UL)          /*!< FFMT (Bit 0)                                          */
+ #define R_XSPI0_CSa_CMCFG0_FFMT_Msk       (0x3UL)        /*!< FFMT (Bitfield-Mask: 0x03)                            */
+ #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Pos    (2UL)          /*!< ADDSIZE (Bit 2)                                       */
+ #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Msk    (0xcUL)        /*!< ADDSIZE (Bitfield-Mask: 0x03)                         */
+ #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Pos    (16UL)         /*!< ADDRPEN (Bit 16)                                      */
+ #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Msk    (0xff0000UL)   /*!< ADDRPEN (Bitfield-Mask: 0xff)                         */
+ #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Pos    (24UL)         /*!< ADDRPCD (Bit 24)                                      */
+ #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Msk    (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff)                         */
+/* ========================================================  CMCFG1  ========================================================= */
+ #define R_XSPI0_CSa_CMCFG1_RDCMD_Pos      (0UL)          /*!< RDCMD (Bit 0)                                         */
+ #define R_XSPI0_CSa_CMCFG1_RDCMD_Msk      (0xffffUL)     /*!< RDCMD (Bitfield-Mask: 0xffff)                         */
+ #define R_XSPI0_CSa_CMCFG1_RDLATE_Pos     (16UL)         /*!< RDLATE (Bit 16)                                       */
+ #define R_XSPI0_CSa_CMCFG1_RDLATE_Msk     (0x1f0000UL)   /*!< RDLATE (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  CMCFG2  ========================================================= */
+ #define R_XSPI0_CSa_CMCFG2_WRCMD_Pos      (0UL)          /*!< WRCMD (Bit 0)                                         */
+ #define R_XSPI0_CSa_CMCFG2_WRCMD_Msk      (0xffffUL)     /*!< WRCMD (Bitfield-Mask: 0xffff)                         */
+ #define R_XSPI0_CSa_CMCFG2_WRLATE_Pos     (16UL)         /*!< WRLATE (Bit 16)                                       */
+ #define R_XSPI0_CSa_CMCFG2_WRLATE_Msk     (0x1f0000UL)   /*!< WRLATE (Bitfield-Mask: 0x1f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                            BUF                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CDT  ========================================================== */
+ #define R_XSPI0_BUF_CDT_CMDSIZE_Pos     (0UL)          /*!< CMDSIZE (Bit 0)                                       */
+ #define R_XSPI0_BUF_CDT_CMDSIZE_Msk     (0x3UL)        /*!< CMDSIZE (Bitfield-Mask: 0x03)                         */
+ #define R_XSPI0_BUF_CDT_ADDSIZE_Pos     (2UL)          /*!< ADDSIZE (Bit 2)                                       */
+ #define R_XSPI0_BUF_CDT_ADDSIZE_Msk     (0x1cUL)       /*!< ADDSIZE (Bitfield-Mask: 0x07)                         */
+ #define R_XSPI0_BUF_CDT_DATASIZE_Pos    (5UL)          /*!< DATASIZE (Bit 5)                                      */
+ #define R_XSPI0_BUF_CDT_DATASIZE_Msk    (0x1e0UL)      /*!< DATASIZE (Bitfield-Mask: 0x0f)                        */
+ #define R_XSPI0_BUF_CDT_LATE_Pos        (9UL)          /*!< LATE (Bit 9)                                          */
+ #define R_XSPI0_BUF_CDT_LATE_Msk        (0x3e00UL)     /*!< LATE (Bitfield-Mask: 0x1f)                            */
+ #define R_XSPI0_BUF_CDT_TRTYPE_Pos      (15UL)         /*!< TRTYPE (Bit 15)                                       */
+ #define R_XSPI0_BUF_CDT_TRTYPE_Msk      (0x8000UL)     /*!< TRTYPE (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_BUF_CDT_CMD_Pos         (16UL)         /*!< CMD (Bit 16)                                          */
+ #define R_XSPI0_BUF_CDT_CMD_Msk         (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff)                           */
+/* ==========================================================  CDA  ========================================================== */
+ #define R_XSPI0_BUF_CDA_ADD_Pos         (0UL)          /*!< ADD (Bit 0)                                           */
+ #define R_XSPI0_BUF_CDA_ADD_Msk         (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff)                       */
+/* =========================================================  CDD0  ========================================================== */
+ #define R_XSPI0_BUF_CDD0_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_XSPI0_BUF_CDD0_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CDD1  ========================================================== */
+ #define R_XSPI0_BUF_CDD1_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_XSPI0_BUF_CDD1_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                            CSb                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CCCTL0  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL0_CAEN_Pos          (0UL)          /*!< CAEN (Bit 0)                                          */
+ #define R_XSPI0_CSb_CCCTL0_CAEN_Msk          (0x1UL)        /*!< CAEN (Bitfield-Mask: 0x01)                            */
+ #define R_XSPI0_CSb_CCCTL0_CANOWR_Pos        (1UL)          /*!< CANOWR (Bit 1)                                        */
+ #define R_XSPI0_CSb_CCCTL0_CANOWR_Msk        (0x2UL)        /*!< CANOWR (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_CSb_CCCTL0_CAITV_Pos         (8UL)          /*!< CAITV (Bit 8)                                         */
+ #define R_XSPI0_CSb_CCCTL0_CAITV_Msk         (0x1f00UL)     /*!< CAITV (Bitfield-Mask: 0x1f)                           */
+ #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Pos      (16UL)         /*!< CASFTSTA (Bit 16)                                     */
+ #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Msk      (0x1f0000UL)   /*!< CASFTSTA (Bitfield-Mask: 0x1f)                        */
+ #define R_XSPI0_CSb_CCCTL0_CASFTEND_Pos      (24UL)         /*!< CASFTEND (Bit 24)                                     */
+ #define R_XSPI0_CSb_CCCTL0_CASFTEND_Msk      (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f)                        */
+/* ========================================================  CCCTL1  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Pos     (0UL)          /*!< CACMDSIZE (Bit 0)                                     */
+ #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Msk     (0x3UL)        /*!< CACMDSIZE (Bitfield-Mask: 0x03)                       */
+ #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Pos     (2UL)          /*!< CAADDSIZE (Bit 2)                                     */
+ #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Msk     (0x1cUL)       /*!< CAADDSIZE (Bitfield-Mask: 0x07)                       */
+ #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Pos    (5UL)          /*!< CADATASIZE (Bit 5)                                    */
+ #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Msk    (0x1e0UL)      /*!< CADATASIZE (Bitfield-Mask: 0x0f)                      */
+ #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Pos      (16UL)         /*!< CAWRLATE (Bit 16)                                     */
+ #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Msk      (0x1f0000UL)   /*!< CAWRLATE (Bitfield-Mask: 0x1f)                        */
+ #define R_XSPI0_CSb_CCCTL1_CARDLATE_Pos      (24UL)         /*!< CARDLATE (Bit 24)                                     */
+ #define R_XSPI0_CSb_CCCTL1_CARDLATE_Msk      (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f)                        */
+/* ========================================================  CCCTL2  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Pos       (0UL)          /*!< CAWRCMD (Bit 0)                                       */
+ #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Msk       (0xffffUL)     /*!< CAWRCMD (Bitfield-Mask: 0xffff)                       */
+ #define R_XSPI0_CSb_CCCTL2_CARDCMD_Pos       (16UL)         /*!< CARDCMD (Bit 16)                                      */
+ #define R_XSPI0_CSb_CCCTL2_CARDCMD_Msk       (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  CCCTL3  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL3_CAADD_Pos         (0UL)          /*!< CAADD (Bit 0)                                         */
+ #define R_XSPI0_CSb_CCCTL3_CAADD_Msk         (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  CCCTL4  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL4_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
+ #define R_XSPI0_CSb_CCCTL4_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CCCTL5  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL5_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
+ #define R_XSPI0_CSb_CCCTL5_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CCCTL6  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL6_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
+ #define R_XSPI0_CSb_CCCTL6_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CCCTL7  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL7_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
+ #define R_XSPI0_CSb_CCCTL7_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
+
+/* =========================================================================================================================== */
+/* ================                                             W                                             ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  EC710CTL  ======================================================== */
+ #define R_SYSRAM0_W_EC710CTL_ECEMF_Pos      (0UL)          /*!< ECEMF (Bit 0)                                         */
+ #define R_SYSRAM0_W_EC710CTL_ECEMF_Msk      (0x1UL)        /*!< ECEMF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM0_W_EC710CTL_ECER1F_Pos     (1UL)          /*!< ECER1F (Bit 1)                                        */
+ #define R_SYSRAM0_W_EC710CTL_ECER1F_Msk     (0x2UL)        /*!< ECER1F (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECER2F_Pos     (2UL)          /*!< ECER2F (Bit 2)                                        */
+ #define R_SYSRAM0_W_EC710CTL_ECER2F_Msk     (0x4UL)        /*!< ECER2F (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Pos    (3UL)          /*!< EC1EDIC (Bit 3)                                       */
+ #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Msk    (0x8UL)        /*!< EC1EDIC (Bitfield-Mask: 0x01)                         */
+ #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Pos    (4UL)          /*!< EC2EDIC (Bit 4)                                       */
+ #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Msk    (0x10UL)       /*!< EC2EDIC (Bitfield-Mask: 0x01)                         */
+ #define R_SYSRAM0_W_EC710CTL_EC1ECP_Pos     (5UL)          /*!< EC1ECP (Bit 5)                                        */
+ #define R_SYSRAM0_W_EC710CTL_EC1ECP_Msk     (0x20UL)       /*!< EC1ECP (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECERVF_Pos     (6UL)          /*!< ECERVF (Bit 6)                                        */
+ #define R_SYSRAM0_W_EC710CTL_ECERVF_Msk     (0x40UL)       /*!< ECERVF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECTHM_Pos      (7UL)          /*!< ECTHM (Bit 7)                                         */
+ #define R_SYSRAM0_W_EC710CTL_ECTHM_Msk      (0x80UL)       /*!< ECTHM (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM0_W_EC710CTL_ECER1C_Pos     (9UL)          /*!< ECER1C (Bit 9)                                        */
+ #define R_SYSRAM0_W_EC710CTL_ECER1C_Msk     (0x200UL)      /*!< ECER1C (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECER2C_Pos     (10UL)         /*!< ECER2C (Bit 10)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECER2C_Msk     (0x400UL)      /*!< ECER2C (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECOVFF_Pos     (11UL)         /*!< ECOVFF (Bit 11)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECOVFF_Msk     (0x800UL)      /*!< ECOVFF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_EMCA_Pos       (14UL)         /*!< EMCA (Bit 14)                                         */
+ #define R_SYSRAM0_W_EC710CTL_EMCA_Msk       (0xc000UL)     /*!< EMCA (Bitfield-Mask: 0x03)                            */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF0_Pos     (16UL)         /*!< ECEDF0 (Bit 16)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF0_Msk     (0x30000UL)    /*!< ECEDF0 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF1_Pos     (18UL)         /*!< ECEDF1 (Bit 18)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF1_Msk     (0xc0000UL)    /*!< ECEDF1 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF2_Pos     (20UL)         /*!< ECEDF2 (Bit 20)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF2_Msk     (0x300000UL)   /*!< ECEDF2 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF3_Pos     (22UL)         /*!< ECEDF3 (Bit 22)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF3_Msk     (0xc00000UL)   /*!< ECEDF3 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF4_Pos     (24UL)         /*!< ECEDF4 (Bit 24)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF4_Msk     (0x3000000UL)  /*!< ECEDF4 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF5_Pos     (26UL)         /*!< ECEDF5 (Bit 26)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF5_Msk     (0xc000000UL)  /*!< ECEDF5 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF6_Pos     (28UL)         /*!< ECEDF6 (Bit 28)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF6_Msk     (0x30000000UL) /*!< ECEDF6 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF7_Pos     (30UL)         /*!< ECEDF7 (Bit 30)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF7_Msk     (0xc0000000UL) /*!< ECEDF7 (Bitfield-Mask: 0x03)                          */
+/* =======================================================  EC710TMC  ======================================================== */
+ #define R_SYSRAM0_W_EC710TMC_ECREIS_Pos     (0UL)          /*!< ECREIS (Bit 0)                                        */
+ #define R_SYSRAM0_W_EC710TMC_ECREIS_Msk     (0x1UL)        /*!< ECREIS (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710TMC_ECDCS_Pos      (1UL)          /*!< ECDCS (Bit 1)                                         */
+ #define R_SYSRAM0_W_EC710TMC_ECDCS_Msk      (0x2UL)        /*!< ECDCS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM0_W_EC710TMC_ECENS_Pos      (2UL)          /*!< ECENS (Bit 2)                                         */
+ #define R_SYSRAM0_W_EC710TMC_ECENS_Msk      (0x4UL)        /*!< ECENS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM0_W_EC710TMC_ECREOS_Pos     (3UL)          /*!< ECREOS (Bit 3)                                        */
+ #define R_SYSRAM0_W_EC710TMC_ECREOS_Msk     (0x8UL)        /*!< ECREOS (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710TMC_ECTRRS_Pos     (4UL)          /*!< ECTRRS (Bit 4)                                        */
+ #define R_SYSRAM0_W_EC710TMC_ECTRRS_Msk     (0x10UL)       /*!< ECTRRS (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710TMC_ECTMCE_Pos     (7UL)          /*!< ECTMCE (Bit 7)                                        */
+ #define R_SYSRAM0_W_EC710TMC_ECTMCE_Msk     (0x80UL)       /*!< ECTMCE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710TMC_ETMA_Pos       (14UL)         /*!< ETMA (Bit 14)                                         */
+ #define R_SYSRAM0_W_EC710TMC_ETMA_Msk       (0xc000UL)     /*!< ETMA (Bitfield-Mask: 0x03)                            */
+/* =======================================================  EC710TRC  ======================================================== */
+ #define R_SYSRAM0_W_EC710TRC_ECERDB_Pos     (0UL)          /*!< ECERDB (Bit 0)                                        */
+ #define R_SYSRAM0_W_EC710TRC_ECERDB_Msk     (0x7fUL)       /*!< ECERDB (Bitfield-Mask: 0x7f)                          */
+ #define R_SYSRAM0_W_EC710TRC_ECECRD_Pos     (8UL)          /*!< ECECRD (Bit 8)                                        */
+ #define R_SYSRAM0_W_EC710TRC_ECECRD_Msk     (0x7f00UL)     /*!< ECECRD (Bitfield-Mask: 0x7f)                          */
+ #define R_SYSRAM0_W_EC710TRC_ECHORD_Pos     (16UL)         /*!< ECHORD (Bit 16)                                       */
+ #define R_SYSRAM0_W_EC710TRC_ECHORD_Msk     (0x7f0000UL)   /*!< ECHORD (Bitfield-Mask: 0x7f)                          */
+ #define R_SYSRAM0_W_EC710TRC_ECSYND_Pos     (24UL)         /*!< ECSYND (Bit 24)                                       */
+ #define R_SYSRAM0_W_EC710TRC_ECSYND_Msk     (0x7f000000UL) /*!< ECSYND (Bitfield-Mask: 0x7f)                          */
+/* =======================================================  EC710TED  ======================================================== */
+ #define R_SYSRAM0_W_EC710TED_ECEDB_Pos      (0UL)          /*!< ECEDB (Bit 0)                                         */
+ #define R_SYSRAM0_W_EC710TED_ECEDB_Msk      (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff)                     */
+/* =======================================================  EC710EAD  ======================================================== */
+ #define R_SYSRAM0_W_EC710EAD_ECEAD_Pos      (0UL)          /*!< ECEAD (Bit 0)                                         */
+ #define R_SYSRAM0_W_EC710EAD_ECEAD_Msk      (0x7fffUL)     /*!< ECEAD (Bitfield-Mask: 0x7fff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                            RGN                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  STADD  ========================================================= */
+ #define R_MPU0_RGN_STADD_RDPR_Pos        (0UL)          /*!< RDPR (Bit 0)                                          */
+ #define R_MPU0_RGN_STADD_RDPR_Msk        (0x1UL)        /*!< RDPR (Bitfield-Mask: 0x01)                            */
+ #define R_MPU0_RGN_STADD_WRPR_Pos        (1UL)          /*!< WRPR (Bit 1)                                          */
+ #define R_MPU0_RGN_STADD_WRPR_Msk        (0x2UL)        /*!< WRPR (Bitfield-Mask: 0x01)                            */
+ #define R_MPU0_RGN_STADD_STADDR_Pos      (10UL)         /*!< STADDR (Bit 10)                                       */
+ #define R_MPU0_RGN_STADD_STADDR_Msk      (0xfffffc00UL) /*!< STADDR (Bitfield-Mask: 0x3fffff)                      */
+/* ========================================================  ENDADD  ========================================================= */
+ #define R_MPU0_RGN_ENDADD_ENDADDR_Pos    (10UL)         /*!< ENDADDR (Bit 10)                                      */
+ #define R_MPU0_RGN_ENDADD_ENDADDR_Msk    (0xfffffc00UL) /*!< ENDADDR (Bitfield-Mask: 0x3fffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                            CH                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DSICR  ========================================================= */
+ #define R_DSMIF0_CH_DSICR_IOEL_Pos         (0UL)          /*!< IOEL (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSICR_IOEL_Msk         (0x1UL)        /*!< IOEL (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSICR_IOEH_Pos         (1UL)          /*!< IOEH (Bit 1)                                          */
+ #define R_DSMIF0_CH_DSICR_IOEH_Msk         (0x2UL)        /*!< IOEH (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSICR_ISE_Pos          (2UL)          /*!< ISE (Bit 2)                                           */
+ #define R_DSMIF0_CH_DSICR_ISE_Msk          (0x4UL)        /*!< ISE (Bitfield-Mask: 0x01)                             */
+ #define R_DSMIF0_CH_DSICR_IUE_Pos          (3UL)          /*!< IUE (Bit 3)                                           */
+ #define R_DSMIF0_CH_DSICR_IUE_Msk          (0x8UL)        /*!< IUE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DSCMCCR  ======================================================== */
+ #define R_DSMIF0_CH_DSCMCCR_CKDIR_Pos      (0UL)          /*!< CKDIR (Bit 0)                                         */
+ #define R_DSMIF0_CH_DSCMCCR_CKDIR_Msk      (0x1UL)        /*!< CKDIR (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCMCCR_SEDGE_Pos      (7UL)          /*!< SEDGE (Bit 7)                                         */
+ #define R_DSMIF0_CH_DSCMCCR_SEDGE_Msk      (0x80UL)       /*!< SEDGE (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCMCCR_CKDIV_Pos      (8UL)          /*!< CKDIV (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSCMCCR_CKDIV_Msk      (0x3f00UL)     /*!< CKDIV (Bitfield-Mask: 0x3f)                           */
+/* ========================================================  DSCMFCR  ======================================================== */
+ #define R_DSMIF0_CH_DSCMFCR_CMSINC_Pos     (0UL)          /*!< CMSINC (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCMFCR_CMSINC_Msk     (0x3UL)        /*!< CMSINC (Bitfield-Mask: 0x03)                          */
+ #define R_DSMIF0_CH_DSCMFCR_CMDEC_Pos      (8UL)          /*!< CMDEC (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSCMFCR_CMDEC_Msk      (0xff00UL)     /*!< CMDEC (Bitfield-Mask: 0xff)                           */
+ #define R_DSMIF0_CH_DSCMFCR_CMSH_Pos       (16UL)         /*!< CMSH (Bit 16)                                         */
+ #define R_DSMIF0_CH_DSCMFCR_CMSH_Msk       (0x1f0000UL)   /*!< CMSH (Bitfield-Mask: 0x1f)                            */
+/* =======================================================  DSCMCTCR  ======================================================== */
+ #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Pos    (0UL)          /*!< CTSELA (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Msk    (0x7UL)        /*!< CTSELA (Bitfield-Mask: 0x07)                          */
+ #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Pos    (8UL)          /*!< CTSELB (Bit 8)                                        */
+ #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Msk    (0x700UL)      /*!< CTSELB (Bitfield-Mask: 0x07)                          */
+ #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Pos    (16UL)         /*!< DITSEL (Bit 16)                                       */
+ #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Msk    (0x30000UL)    /*!< DITSEL (Bitfield-Mask: 0x03)                          */
+ #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Pos     (23UL)         /*!< DEDGE (Bit 23)                                        */
+ #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Msk     (0x800000UL)   /*!< DEDGE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DSEDCR  ========================================================= */
+ #define R_DSMIF0_CH_DSEDCR_SDE_Pos         (0UL)          /*!< SDE (Bit 0)                                           */
+ #define R_DSMIF0_CH_DSEDCR_SDE_Msk         (0x1UL)        /*!< SDE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DSOCFCR  ======================================================== */
+ #define R_DSMIF0_CH_DSOCFCR_OCSINC_Pos     (0UL)          /*!< OCSINC (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSOCFCR_OCSINC_Msk     (0x3UL)        /*!< OCSINC (Bitfield-Mask: 0x03)                          */
+ #define R_DSMIF0_CH_DSOCFCR_OCDEC_Pos      (8UL)          /*!< OCDEC (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSOCFCR_OCDEC_Msk      (0xff00UL)     /*!< OCDEC (Bitfield-Mask: 0xff)                           */
+ #define R_DSMIF0_CH_DSOCFCR_OCSH_Pos       (16UL)         /*!< OCSH (Bit 16)                                         */
+ #define R_DSMIF0_CH_DSOCFCR_OCSH_Msk       (0x1f0000UL)   /*!< OCSH (Bitfield-Mask: 0x1f)                            */
+/* ========================================================  DSOCLTR  ======================================================== */
+ #define R_DSMIF0_CH_DSOCLTR_OCMPTBL_Pos    (0UL)          /*!< OCMPTBL (Bit 0)                                       */
+ #define R_DSMIF0_CH_DSOCLTR_OCMPTBL_Msk    (0xffffUL)     /*!< OCMPTBL (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  DSOCHTR  ======================================================== */
+ #define R_DSMIF0_CH_DSOCHTR_OCMPTBH_Pos    (0UL)          /*!< OCMPTBH (Bit 0)                                       */
+ #define R_DSMIF0_CH_DSOCHTR_OCMPTBH_Msk    (0xffffUL)     /*!< OCMPTBH (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  DSSCTSR  ======================================================== */
+ #define R_DSMIF0_CH_DSSCTSR_SCNTL_Pos      (0UL)          /*!< SCNTL (Bit 0)                                         */
+ #define R_DSMIF0_CH_DSSCTSR_SCNTL_Msk      (0x1fffUL)     /*!< SCNTL (Bitfield-Mask: 0x1fff)                         */
+ #define R_DSMIF0_CH_DSSCTSR_SCNTH_Pos      (16UL)         /*!< SCNTH (Bit 16)                                        */
+ #define R_DSMIF0_CH_DSSCTSR_SCNTH_Msk      (0x1fff0000UL) /*!< SCNTH (Bitfield-Mask: 0x1fff)                         */
+/* ========================================================  DSODCR  ========================================================= */
+ #define R_DSMIF0_CH_DSODCR_ODEL_Pos        (0UL)          /*!< ODEL (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSODCR_ODEL_Msk        (0x1UL)        /*!< ODEL (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSODCR_ODEH_Pos        (1UL)          /*!< ODEH (Bit 1)                                          */
+ #define R_DSMIF0_CH_DSODCR_ODEH_Msk        (0x2UL)        /*!< ODEH (Bitfield-Mask: 0x01)                            */
+/* =======================================================  DSCSTRTR  ======================================================== */
+ #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Pos    (0UL)          /*!< STRTRG (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Msk    (0x1UL)        /*!< STRTRG (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DSCSTPTR  ======================================================== */
+ #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Pos    (0UL)          /*!< STPTRG (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Msk    (0x1UL)        /*!< STPTRG (Bitfield-Mask: 0x01)                          */
+/* =========================================================  DSCDR  ========================================================= */
+ #define R_DSMIF0_CH_DSCDR_ADDR_Pos         (0UL)          /*!< ADDR (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSCDR_ADDR_Msk         (0xffffUL)     /*!< ADDR (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  DSCCDRA  ======================================================== */
+ #define R_DSMIF0_CH_DSCCDRA_CDRA_Pos       (0UL)          /*!< CDRA (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSCCDRA_CDRA_Msk       (0xffffUL)     /*!< CDRA (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  DSCCDRB  ======================================================== */
+ #define R_DSMIF0_CH_DSCCDRB_CDRB_Pos       (0UL)          /*!< CDRB (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSCCDRB_CDRB_Msk       (0xffffUL)     /*!< CDRB (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  DSOCDR  ========================================================= */
+ #define R_DSMIF0_CH_DSOCDR_ODR_Pos         (0UL)          /*!< ODR (Bit 0)                                           */
+ #define R_DSMIF0_CH_DSOCDR_ODR_Msk         (0xffffUL)     /*!< ODR (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  DSCOCDR  ======================================================== */
+ #define R_DSMIF0_CH_DSCOCDR_CODR_Pos       (0UL)          /*!< CODR (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSCOCDR_CODR_Msk       (0xffffUL)     /*!< CODR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  DSCSR  ========================================================= */
+ #define R_DSMIF0_CH_DSCSR_DUF_Pos          (0UL)          /*!< DUF (Bit 0)                                           */
+ #define R_DSMIF0_CH_DSCSR_DUF_Msk          (0x1UL)        /*!< DUF (Bitfield-Mask: 0x01)                             */
+ #define R_DSMIF0_CH_DSCSR_OCFL_Pos         (1UL)          /*!< OCFL (Bit 1)                                          */
+ #define R_DSMIF0_CH_DSCSR_OCFL_Msk         (0x2UL)        /*!< OCFL (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSCSR_OCFH_Pos         (2UL)          /*!< OCFH (Bit 2)                                          */
+ #define R_DSMIF0_CH_DSCSR_OCFH_Msk         (0x4UL)        /*!< OCFH (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSCSR_SCF_Pos          (3UL)          /*!< SCF (Bit 3)                                           */
+ #define R_DSMIF0_CH_DSCSR_SCF_Msk          (0x8UL)        /*!< SCF (Bitfield-Mask: 0x01)                             */
+ #define R_DSMIF0_CH_DSCSR_CHSTATE_Pos      (16UL)         /*!< CHSTATE (Bit 16)                                      */
+ #define R_DSMIF0_CH_DSCSR_CHSTATE_Msk      (0x10000UL)    /*!< CHSTATE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DSCSCR  ========================================================= */
+ #define R_DSMIF0_CH_DSCSCR_CLRDUF_Pos      (0UL)          /*!< CLRDUF (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCSCR_CLRDUF_Msk      (0x1UL)        /*!< CLRDUF (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_CH_DSCSCR_CLROCFL_Pos     (1UL)          /*!< CLROCFL (Bit 1)                                       */
+ #define R_DSMIF0_CH_DSCSCR_CLROCFL_Msk     (0x2UL)        /*!< CLROCFL (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSCR_CLROCFH_Pos     (2UL)          /*!< CLROCFH (Bit 2)                                       */
+ #define R_DSMIF0_CH_DSCSCR_CLROCFH_Msk     (0x4UL)        /*!< CLROCFH (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSCR_CLRSCF_Pos      (3UL)          /*!< CLRSCF (Bit 3)                                        */
+ #define R_DSMIF0_CH_DSCSCR_CLRSCF_Msk      (0x8UL)        /*!< CLRSCF (Bitfield-Mask: 0x01)                          */
+
+/** @} */ /* End of group PosMask_clusters */
+
+/* =========================================================================================================================== */
+/* ================                                Pos/Mask Peripheral Section                                ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GPT0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  GTWP  ========================================================== */
+ #define R_GPT7_GTWP_WP_Pos              (0UL)          /*!< WP (Bit 0)                                            */
+ #define R_GPT7_GTWP_WP_Msk              (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
+ #define R_GPT7_GTWP_STRWP_Pos           (1UL)          /*!< STRWP (Bit 1)                                         */
+ #define R_GPT7_GTWP_STRWP_Msk           (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTWP_STPWP_Pos           (2UL)          /*!< STPWP (Bit 2)                                         */
+ #define R_GPT7_GTWP_STPWP_Msk           (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTWP_CLRWP_Pos           (3UL)          /*!< CLRWP (Bit 3)                                         */
+ #define R_GPT7_GTWP_CLRWP_Msk           (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTWP_CMNWP_Pos           (4UL)          /*!< CMNWP (Bit 4)                                         */
+ #define R_GPT7_GTWP_CMNWP_Msk           (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTWP_PRKEY_Pos           (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_GPT7_GTWP_PRKEY_Msk           (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+/* =========================================================  GTSTR  ========================================================= */
+ #define R_GPT7_GTSTR_CSTRT0_Pos         (0UL)          /*!< CSTRT0 (Bit 0)                                        */
+ #define R_GPT7_GTSTR_CSTRT0_Msk         (0x1UL)        /*!< CSTRT0 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTR_CSTRT1_Pos         (1UL)          /*!< CSTRT1 (Bit 1)                                        */
+ #define R_GPT7_GTSTR_CSTRT1_Msk         (0x2UL)        /*!< CSTRT1 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTR_CSTRT2_Pos         (2UL)          /*!< CSTRT2 (Bit 2)                                        */
+ #define R_GPT7_GTSTR_CSTRT2_Msk         (0x4UL)        /*!< CSTRT2 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTR_CSTRT3_Pos         (3UL)          /*!< CSTRT3 (Bit 3)                                        */
+ #define R_GPT7_GTSTR_CSTRT3_Msk         (0x8UL)        /*!< CSTRT3 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTR_CSTRT4_Pos         (4UL)          /*!< CSTRT4 (Bit 4)                                        */
+ #define R_GPT7_GTSTR_CSTRT4_Msk         (0x10UL)       /*!< CSTRT4 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTR_CSTRT5_Pos         (5UL)          /*!< CSTRT5 (Bit 5)                                        */
+ #define R_GPT7_GTSTR_CSTRT5_Msk         (0x20UL)       /*!< CSTRT5 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTR_CSTRT6_Pos         (6UL)          /*!< CSTRT6 (Bit 6)                                        */
+ #define R_GPT7_GTSTR_CSTRT6_Msk         (0x40UL)       /*!< CSTRT6 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTSTP  ========================================================= */
+ #define R_GPT7_GTSTP_CSTOP0_Pos         (0UL)          /*!< CSTOP0 (Bit 0)                                        */
+ #define R_GPT7_GTSTP_CSTOP0_Msk         (0x1UL)        /*!< CSTOP0 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTP_CSTOP1_Pos         (1UL)          /*!< CSTOP1 (Bit 1)                                        */
+ #define R_GPT7_GTSTP_CSTOP1_Msk         (0x2UL)        /*!< CSTOP1 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTP_CSTOP2_Pos         (2UL)          /*!< CSTOP2 (Bit 2)                                        */
+ #define R_GPT7_GTSTP_CSTOP2_Msk         (0x4UL)        /*!< CSTOP2 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTP_CSTOP3_Pos         (3UL)          /*!< CSTOP3 (Bit 3)                                        */
+ #define R_GPT7_GTSTP_CSTOP3_Msk         (0x8UL)        /*!< CSTOP3 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTP_CSTOP4_Pos         (4UL)          /*!< CSTOP4 (Bit 4)                                        */
+ #define R_GPT7_GTSTP_CSTOP4_Msk         (0x10UL)       /*!< CSTOP4 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTP_CSTOP5_Pos         (5UL)          /*!< CSTOP5 (Bit 5)                                        */
+ #define R_GPT7_GTSTP_CSTOP5_Msk         (0x20UL)       /*!< CSTOP5 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSTP_CSTOP6_Pos         (6UL)          /*!< CSTOP6 (Bit 6)                                        */
+ #define R_GPT7_GTSTP_CSTOP6_Msk         (0x40UL)       /*!< CSTOP6 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTCLR  ========================================================= */
+ #define R_GPT7_GTCLR_CCLR0_Pos          (0UL)          /*!< CCLR0 (Bit 0)                                         */
+ #define R_GPT7_GTCLR_CCLR0_Msk          (0x1UL)        /*!< CCLR0 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTCLR_CCLR1_Pos          (1UL)          /*!< CCLR1 (Bit 1)                                         */
+ #define R_GPT7_GTCLR_CCLR1_Msk          (0x2UL)        /*!< CCLR1 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTCLR_CCLR2_Pos          (2UL)          /*!< CCLR2 (Bit 2)                                         */
+ #define R_GPT7_GTCLR_CCLR2_Msk          (0x4UL)        /*!< CCLR2 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTCLR_CCLR3_Pos          (3UL)          /*!< CCLR3 (Bit 3)                                         */
+ #define R_GPT7_GTCLR_CCLR3_Msk          (0x8UL)        /*!< CCLR3 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTCLR_CCLR4_Pos          (4UL)          /*!< CCLR4 (Bit 4)                                         */
+ #define R_GPT7_GTCLR_CCLR4_Msk          (0x10UL)       /*!< CCLR4 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTCLR_CCLR5_Pos          (5UL)          /*!< CCLR5 (Bit 5)                                         */
+ #define R_GPT7_GTCLR_CCLR5_Msk          (0x20UL)       /*!< CCLR5 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTCLR_CCLR6_Pos          (6UL)          /*!< CCLR6 (Bit 6)                                         */
+ #define R_GPT7_GTCLR_CCLR6_Msk          (0x40UL)       /*!< CCLR6 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTSSR  ========================================================= */
+ #define R_GPT7_GTSSR_SSGTRGAFR_Pos      (0UL)          /*!< SSGTRGAFR (Bit 0)                                     */
+ #define R_GPT7_GTSSR_SSGTRGAFR_Msk      (0x3UL)        /*!< SSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTSSR_SSGTRGBFR_Pos      (2UL)          /*!< SSGTRGBFR (Bit 2)                                     */
+ #define R_GPT7_GTSSR_SSGTRGBFR_Msk      (0xcUL)        /*!< SSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTSSR_SSGTRGCFR_Pos      (4UL)          /*!< SSGTRGCFR (Bit 4)                                     */
+ #define R_GPT7_GTSSR_SSGTRGCFR_Msk      (0x30UL)       /*!< SSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTSSR_SSGTRGDFR_Pos      (6UL)          /*!< SSGTRGDFR (Bit 6)                                     */
+ #define R_GPT7_GTSSR_SSGTRGDFR_Msk      (0xc0UL)       /*!< SSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTSSR_SSCARBHL_Pos       (8UL)          /*!< SSCARBHL (Bit 8)                                      */
+ #define R_GPT7_GTSSR_SSCARBHL_Msk       (0x300UL)      /*!< SSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTSSR_SSCAFBHL_Pos       (10UL)         /*!< SSCAFBHL (Bit 10)                                     */
+ #define R_GPT7_GTSSR_SSCAFBHL_Msk       (0xc00UL)      /*!< SSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTSSR_SSCBRAHL_Pos       (12UL)         /*!< SSCBRAHL (Bit 12)                                     */
+ #define R_GPT7_GTSSR_SSCBRAHL_Msk       (0x3000UL)     /*!< SSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTSSR_SSCBFAHL_Pos       (14UL)         /*!< SSCBFAHL (Bit 14)                                     */
+ #define R_GPT7_GTSSR_SSCBFAHL_Msk       (0xc000UL)     /*!< SSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTSSR_SSELCA_Pos         (16UL)         /*!< SSELCA (Bit 16)                                       */
+ #define R_GPT7_GTSSR_SSELCA_Msk         (0x10000UL)    /*!< SSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSSR_SSELCB_Pos         (17UL)         /*!< SSELCB (Bit 17)                                       */
+ #define R_GPT7_GTSSR_SSELCB_Msk         (0x20000UL)    /*!< SSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSSR_SSELCC_Pos         (18UL)         /*!< SSELCC (Bit 18)                                       */
+ #define R_GPT7_GTSSR_SSELCC_Msk         (0x40000UL)    /*!< SSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSSR_SSELCD_Pos         (19UL)         /*!< SSELCD (Bit 19)                                       */
+ #define R_GPT7_GTSSR_SSELCD_Msk         (0x80000UL)    /*!< SSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSSR_SSELCE_Pos         (20UL)         /*!< SSELCE (Bit 20)                                       */
+ #define R_GPT7_GTSSR_SSELCE_Msk         (0x100000UL)   /*!< SSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSSR_SSELCF_Pos         (21UL)         /*!< SSELCF (Bit 21)                                       */
+ #define R_GPT7_GTSSR_SSELCF_Msk         (0x200000UL)   /*!< SSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSSR_SSELCG_Pos         (22UL)         /*!< SSELCG (Bit 22)                                       */
+ #define R_GPT7_GTSSR_SSELCG_Msk         (0x400000UL)   /*!< SSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSSR_SSELCH_Pos         (23UL)         /*!< SSELCH (Bit 23)                                       */
+ #define R_GPT7_GTSSR_SSELCH_Msk         (0x800000UL)   /*!< SSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSSR_CSTRT_Pos          (31UL)         /*!< CSTRT (Bit 31)                                        */
+ #define R_GPT7_GTSSR_CSTRT_Msk          (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTPSR  ========================================================= */
+ #define R_GPT7_GTPSR_PSGTRGAFR_Pos      (0UL)          /*!< PSGTRGAFR (Bit 0)                                     */
+ #define R_GPT7_GTPSR_PSGTRGAFR_Msk      (0x3UL)        /*!< PSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTPSR_PSGTRGBFR_Pos      (2UL)          /*!< PSGTRGBFR (Bit 2)                                     */
+ #define R_GPT7_GTPSR_PSGTRGBFR_Msk      (0xcUL)        /*!< PSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTPSR_PSGTRGCFR_Pos      (4UL)          /*!< PSGTRGCFR (Bit 4)                                     */
+ #define R_GPT7_GTPSR_PSGTRGCFR_Msk      (0x30UL)       /*!< PSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTPSR_PSGTRGDFR_Pos      (6UL)          /*!< PSGTRGDFR (Bit 6)                                     */
+ #define R_GPT7_GTPSR_PSGTRGDFR_Msk      (0xc0UL)       /*!< PSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTPSR_PSCARBHL_Pos       (8UL)          /*!< PSCARBHL (Bit 8)                                      */
+ #define R_GPT7_GTPSR_PSCARBHL_Msk       (0x300UL)      /*!< PSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTPSR_PSCAFBHL_Pos       (10UL)         /*!< PSCAFBHL (Bit 10)                                     */
+ #define R_GPT7_GTPSR_PSCAFBHL_Msk       (0xc00UL)      /*!< PSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTPSR_PSCBRAHL_Pos       (12UL)         /*!< PSCBRAHL (Bit 12)                                     */
+ #define R_GPT7_GTPSR_PSCBRAHL_Msk       (0x3000UL)     /*!< PSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTPSR_PSCBFAHL_Pos       (14UL)         /*!< PSCBFAHL (Bit 14)                                     */
+ #define R_GPT7_GTPSR_PSCBFAHL_Msk       (0xc000UL)     /*!< PSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTPSR_PSELCA_Pos         (16UL)         /*!< PSELCA (Bit 16)                                       */
+ #define R_GPT7_GTPSR_PSELCA_Msk         (0x10000UL)    /*!< PSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTPSR_PSELCB_Pos         (17UL)         /*!< PSELCB (Bit 17)                                       */
+ #define R_GPT7_GTPSR_PSELCB_Msk         (0x20000UL)    /*!< PSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTPSR_PSELCC_Pos         (18UL)         /*!< PSELCC (Bit 18)                                       */
+ #define R_GPT7_GTPSR_PSELCC_Msk         (0x40000UL)    /*!< PSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTPSR_PSELCD_Pos         (19UL)         /*!< PSELCD (Bit 19)                                       */
+ #define R_GPT7_GTPSR_PSELCD_Msk         (0x80000UL)    /*!< PSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTPSR_PSELCE_Pos         (20UL)         /*!< PSELCE (Bit 20)                                       */
+ #define R_GPT7_GTPSR_PSELCE_Msk         (0x100000UL)   /*!< PSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTPSR_PSELCF_Pos         (21UL)         /*!< PSELCF (Bit 21)                                       */
+ #define R_GPT7_GTPSR_PSELCF_Msk         (0x200000UL)   /*!< PSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTPSR_PSELCG_Pos         (22UL)         /*!< PSELCG (Bit 22)                                       */
+ #define R_GPT7_GTPSR_PSELCG_Msk         (0x400000UL)   /*!< PSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTPSR_PSELCH_Pos         (23UL)         /*!< PSELCH (Bit 23)                                       */
+ #define R_GPT7_GTPSR_PSELCH_Msk         (0x800000UL)   /*!< PSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTPSR_CSTOP_Pos          (31UL)         /*!< CSTOP (Bit 31)                                        */
+ #define R_GPT7_GTPSR_CSTOP_Msk          (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCSR  ========================================================= */
+ #define R_GPT7_GTCSR_CSGTRGAFR_Pos      (0UL)          /*!< CSGTRGAFR (Bit 0)                                     */
+ #define R_GPT7_GTCSR_CSGTRGAFR_Msk      (0x3UL)        /*!< CSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTCSR_CSGTRGBFR_Pos      (2UL)          /*!< CSGTRGBFR (Bit 2)                                     */
+ #define R_GPT7_GTCSR_CSGTRGBFR_Msk      (0xcUL)        /*!< CSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTCSR_CSGTRGCFR_Pos      (4UL)          /*!< CSGTRGCFR (Bit 4)                                     */
+ #define R_GPT7_GTCSR_CSGTRGCFR_Msk      (0x30UL)       /*!< CSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTCSR_CSGTRGDFR_Pos      (6UL)          /*!< CSGTRGDFR (Bit 6)                                     */
+ #define R_GPT7_GTCSR_CSGTRGDFR_Msk      (0xc0UL)       /*!< CSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTCSR_CSCARBHL_Pos       (8UL)          /*!< CSCARBHL (Bit 8)                                      */
+ #define R_GPT7_GTCSR_CSCARBHL_Msk       (0x300UL)      /*!< CSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTCSR_CSCAFBHL_Pos       (10UL)         /*!< CSCAFBHL (Bit 10)                                     */
+ #define R_GPT7_GTCSR_CSCAFBHL_Msk       (0xc00UL)      /*!< CSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTCSR_CSCBRAHL_Pos       (12UL)         /*!< CSCBRAHL (Bit 12)                                     */
+ #define R_GPT7_GTCSR_CSCBRAHL_Msk       (0x3000UL)     /*!< CSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTCSR_CSCBFAHL_Pos       (14UL)         /*!< CSCBFAHL (Bit 14)                                     */
+ #define R_GPT7_GTCSR_CSCBFAHL_Msk       (0xc000UL)     /*!< CSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTCSR_CSELCA_Pos         (16UL)         /*!< CSELCA (Bit 16)                                       */
+ #define R_GPT7_GTCSR_CSELCA_Msk         (0x10000UL)    /*!< CSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTCSR_CSELCB_Pos         (17UL)         /*!< CSELCB (Bit 17)                                       */
+ #define R_GPT7_GTCSR_CSELCB_Msk         (0x20000UL)    /*!< CSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTCSR_CSELCC_Pos         (18UL)         /*!< CSELCC (Bit 18)                                       */
+ #define R_GPT7_GTCSR_CSELCC_Msk         (0x40000UL)    /*!< CSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTCSR_CSELCD_Pos         (19UL)         /*!< CSELCD (Bit 19)                                       */
+ #define R_GPT7_GTCSR_CSELCD_Msk         (0x80000UL)    /*!< CSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTCSR_CSELCE_Pos         (20UL)         /*!< CSELCE (Bit 20)                                       */
+ #define R_GPT7_GTCSR_CSELCE_Msk         (0x100000UL)   /*!< CSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTCSR_CSELCF_Pos         (21UL)         /*!< CSELCF (Bit 21)                                       */
+ #define R_GPT7_GTCSR_CSELCF_Msk         (0x200000UL)   /*!< CSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTCSR_CSELCG_Pos         (22UL)         /*!< CSELCG (Bit 22)                                       */
+ #define R_GPT7_GTCSR_CSELCG_Msk         (0x400000UL)   /*!< CSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTCSR_CSELCH_Pos         (23UL)         /*!< CSELCH (Bit 23)                                       */
+ #define R_GPT7_GTCSR_CSELCH_Msk         (0x800000UL)   /*!< CSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTCSR_CCLR_Pos           (31UL)         /*!< CCLR (Bit 31)                                         */
+ #define R_GPT7_GTCSR_CCLR_Msk           (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTUPSR  ========================================================= */
+ #define R_GPT7_GTUPSR_USGTRGAFR_Pos     (0UL)          /*!< USGTRGAFR (Bit 0)                                     */
+ #define R_GPT7_GTUPSR_USGTRGAFR_Msk     (0x3UL)        /*!< USGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTUPSR_USGTRGBFR_Pos     (2UL)          /*!< USGTRGBFR (Bit 2)                                     */
+ #define R_GPT7_GTUPSR_USGTRGBFR_Msk     (0xcUL)        /*!< USGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTUPSR_USGTRGCFR_Pos     (4UL)          /*!< USGTRGCFR (Bit 4)                                     */
+ #define R_GPT7_GTUPSR_USGTRGCFR_Msk     (0x30UL)       /*!< USGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTUPSR_USGTRGDFR_Pos     (6UL)          /*!< USGTRGDFR (Bit 6)                                     */
+ #define R_GPT7_GTUPSR_USGTRGDFR_Msk     (0xc0UL)       /*!< USGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTUPSR_USCARBHL_Pos      (8UL)          /*!< USCARBHL (Bit 8)                                      */
+ #define R_GPT7_GTUPSR_USCARBHL_Msk      (0x300UL)      /*!< USCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTUPSR_USCAFBHL_Pos      (10UL)         /*!< USCAFBHL (Bit 10)                                     */
+ #define R_GPT7_GTUPSR_USCAFBHL_Msk      (0xc00UL)      /*!< USCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTUPSR_USCBRAHL_Pos      (12UL)         /*!< USCBRAHL (Bit 12)                                     */
+ #define R_GPT7_GTUPSR_USCBRAHL_Msk      (0x3000UL)     /*!< USCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTUPSR_USCBFAHL_Pos      (14UL)         /*!< USCBFAHL (Bit 14)                                     */
+ #define R_GPT7_GTUPSR_USCBFAHL_Msk      (0xc000UL)     /*!< USCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTUPSR_USELCA_Pos        (16UL)         /*!< USELCA (Bit 16)                                       */
+ #define R_GPT7_GTUPSR_USELCA_Msk        (0x10000UL)    /*!< USELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUPSR_USELCB_Pos        (17UL)         /*!< USELCB (Bit 17)                                       */
+ #define R_GPT7_GTUPSR_USELCB_Msk        (0x20000UL)    /*!< USELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUPSR_USELCC_Pos        (18UL)         /*!< USELCC (Bit 18)                                       */
+ #define R_GPT7_GTUPSR_USELCC_Msk        (0x40000UL)    /*!< USELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUPSR_USELCD_Pos        (19UL)         /*!< USELCD (Bit 19)                                       */
+ #define R_GPT7_GTUPSR_USELCD_Msk        (0x80000UL)    /*!< USELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUPSR_USELCE_Pos        (20UL)         /*!< USELCE (Bit 20)                                       */
+ #define R_GPT7_GTUPSR_USELCE_Msk        (0x100000UL)   /*!< USELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUPSR_USELCF_Pos        (21UL)         /*!< USELCF (Bit 21)                                       */
+ #define R_GPT7_GTUPSR_USELCF_Msk        (0x200000UL)   /*!< USELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUPSR_USELCG_Pos        (22UL)         /*!< USELCG (Bit 22)                                       */
+ #define R_GPT7_GTUPSR_USELCG_Msk        (0x400000UL)   /*!< USELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUPSR_USELCH_Pos        (23UL)         /*!< USELCH (Bit 23)                                       */
+ #define R_GPT7_GTUPSR_USELCH_Msk        (0x800000UL)   /*!< USELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTDNSR  ========================================================= */
+ #define R_GPT7_GTDNSR_DSGTRGAFR_Pos     (0UL)          /*!< DSGTRGAFR (Bit 0)                                     */
+ #define R_GPT7_GTDNSR_DSGTRGAFR_Msk     (0x3UL)        /*!< DSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTDNSR_DSGTRGBFR_Pos     (2UL)          /*!< DSGTRGBFR (Bit 2)                                     */
+ #define R_GPT7_GTDNSR_DSGTRGBFR_Msk     (0xcUL)        /*!< DSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTDNSR_DSGTRGCFR_Pos     (4UL)          /*!< DSGTRGCFR (Bit 4)                                     */
+ #define R_GPT7_GTDNSR_DSGTRGCFR_Msk     (0x30UL)       /*!< DSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTDNSR_DSGTRGDFR_Pos     (6UL)          /*!< DSGTRGDFR (Bit 6)                                     */
+ #define R_GPT7_GTDNSR_DSGTRGDFR_Msk     (0xc0UL)       /*!< DSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTDNSR_DSCARBHL_Pos      (8UL)          /*!< DSCARBHL (Bit 8)                                      */
+ #define R_GPT7_GTDNSR_DSCARBHL_Msk      (0x300UL)      /*!< DSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTDNSR_DSCAFBHL_Pos      (10UL)         /*!< DSCAFBHL (Bit 10)                                     */
+ #define R_GPT7_GTDNSR_DSCAFBHL_Msk      (0xc00UL)      /*!< DSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTDNSR_DSCBRAHL_Pos      (12UL)         /*!< DSCBRAHL (Bit 12)                                     */
+ #define R_GPT7_GTDNSR_DSCBRAHL_Msk      (0x3000UL)     /*!< DSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTDNSR_DSCBFAHL_Pos      (14UL)         /*!< DSCBFAHL (Bit 14)                                     */
+ #define R_GPT7_GTDNSR_DSCBFAHL_Msk      (0xc000UL)     /*!< DSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTDNSR_DSELCA_Pos        (16UL)         /*!< DSELCA (Bit 16)                                       */
+ #define R_GPT7_GTDNSR_DSELCA_Msk        (0x10000UL)    /*!< DSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTDNSR_DSELCB_Pos        (17UL)         /*!< DSELCB (Bit 17)                                       */
+ #define R_GPT7_GTDNSR_DSELCB_Msk        (0x20000UL)    /*!< DSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTDNSR_DSELCC_Pos        (18UL)         /*!< DSELCC (Bit 18)                                       */
+ #define R_GPT7_GTDNSR_DSELCC_Msk        (0x40000UL)    /*!< DSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTDNSR_DSELCD_Pos        (19UL)         /*!< DSELCD (Bit 19)                                       */
+ #define R_GPT7_GTDNSR_DSELCD_Msk        (0x80000UL)    /*!< DSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTDNSR_DSELCE_Pos        (20UL)         /*!< DSELCE (Bit 20)                                       */
+ #define R_GPT7_GTDNSR_DSELCE_Msk        (0x100000UL)   /*!< DSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTDNSR_DSELCF_Pos        (21UL)         /*!< DSELCF (Bit 21)                                       */
+ #define R_GPT7_GTDNSR_DSELCF_Msk        (0x200000UL)   /*!< DSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTDNSR_DSELCG_Pos        (22UL)         /*!< DSELCG (Bit 22)                                       */
+ #define R_GPT7_GTDNSR_DSELCG_Msk        (0x400000UL)   /*!< DSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTDNSR_DSELCH_Pos        (23UL)         /*!< DSELCH (Bit 23)                                       */
+ #define R_GPT7_GTDNSR_DSELCH_Msk        (0x800000UL)   /*!< DSELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTICASR  ======================================================== */
+ #define R_GPT7_GTICASR_ASGTRGAFR_Pos    (0UL)          /*!< ASGTRGAFR (Bit 0)                                     */
+ #define R_GPT7_GTICASR_ASGTRGAFR_Msk    (0x3UL)        /*!< ASGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTICASR_ASGTRGBFR_Pos    (2UL)          /*!< ASGTRGBFR (Bit 2)                                     */
+ #define R_GPT7_GTICASR_ASGTRGBFR_Msk    (0xcUL)        /*!< ASGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTICASR_ASGTRGCFR_Pos    (4UL)          /*!< ASGTRGCFR (Bit 4)                                     */
+ #define R_GPT7_GTICASR_ASGTRGCFR_Msk    (0x30UL)       /*!< ASGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTICASR_ASGTRGDFR_Pos    (6UL)          /*!< ASGTRGDFR (Bit 6)                                     */
+ #define R_GPT7_GTICASR_ASGTRGDFR_Msk    (0xc0UL)       /*!< ASGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTICASR_ASCARBHL_Pos     (8UL)          /*!< ASCARBHL (Bit 8)                                      */
+ #define R_GPT7_GTICASR_ASCARBHL_Msk     (0x300UL)      /*!< ASCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTICASR_ASCAFBHL_Pos     (10UL)         /*!< ASCAFBHL (Bit 10)                                     */
+ #define R_GPT7_GTICASR_ASCAFBHL_Msk     (0xc00UL)      /*!< ASCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTICASR_ASCBRAHL_Pos     (12UL)         /*!< ASCBRAHL (Bit 12)                                     */
+ #define R_GPT7_GTICASR_ASCBRAHL_Msk     (0x3000UL)     /*!< ASCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTICASR_ASCBFAHL_Pos     (14UL)         /*!< ASCBFAHL (Bit 14)                                     */
+ #define R_GPT7_GTICASR_ASCBFAHL_Msk     (0xc000UL)     /*!< ASCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTICASR_ASELCA_Pos       (16UL)         /*!< ASELCA (Bit 16)                                       */
+ #define R_GPT7_GTICASR_ASELCA_Msk       (0x10000UL)    /*!< ASELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICASR_ASELCB_Pos       (17UL)         /*!< ASELCB (Bit 17)                                       */
+ #define R_GPT7_GTICASR_ASELCB_Msk       (0x20000UL)    /*!< ASELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICASR_ASELCC_Pos       (18UL)         /*!< ASELCC (Bit 18)                                       */
+ #define R_GPT7_GTICASR_ASELCC_Msk       (0x40000UL)    /*!< ASELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICASR_ASELCD_Pos       (19UL)         /*!< ASELCD (Bit 19)                                       */
+ #define R_GPT7_GTICASR_ASELCD_Msk       (0x80000UL)    /*!< ASELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICASR_ASELCE_Pos       (20UL)         /*!< ASELCE (Bit 20)                                       */
+ #define R_GPT7_GTICASR_ASELCE_Msk       (0x100000UL)   /*!< ASELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICASR_ASELCF_Pos       (21UL)         /*!< ASELCF (Bit 21)                                       */
+ #define R_GPT7_GTICASR_ASELCF_Msk       (0x200000UL)   /*!< ASELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICASR_ASELCG_Pos       (22UL)         /*!< ASELCG (Bit 22)                                       */
+ #define R_GPT7_GTICASR_ASELCG_Msk       (0x400000UL)   /*!< ASELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICASR_ASELCH_Pos       (23UL)         /*!< ASELCH (Bit 23)                                       */
+ #define R_GPT7_GTICASR_ASELCH_Msk       (0x800000UL)   /*!< ASELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTICBSR  ======================================================== */
+ #define R_GPT7_GTICBSR_BSGTRGAFR_Pos    (0UL)          /*!< BSGTRGAFR (Bit 0)                                     */
+ #define R_GPT7_GTICBSR_BSGTRGAFR_Msk    (0x3UL)        /*!< BSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTICBSR_BSGTRGBFR_Pos    (2UL)          /*!< BSGTRGBFR (Bit 2)                                     */
+ #define R_GPT7_GTICBSR_BSGTRGBFR_Msk    (0xcUL)        /*!< BSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTICBSR_BSGTRGCFR_Pos    (4UL)          /*!< BSGTRGCFR (Bit 4)                                     */
+ #define R_GPT7_GTICBSR_BSGTRGCFR_Msk    (0x30UL)       /*!< BSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTICBSR_BSGTRGDFR_Pos    (6UL)          /*!< BSGTRGDFR (Bit 6)                                     */
+ #define R_GPT7_GTICBSR_BSGTRGDFR_Msk    (0xc0UL)       /*!< BSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT7_GTICBSR_BSCARBHL_Pos     (8UL)          /*!< BSCARBHL (Bit 8)                                      */
+ #define R_GPT7_GTICBSR_BSCARBHL_Msk     (0x300UL)      /*!< BSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTICBSR_BSCAFBHL_Pos     (10UL)         /*!< BSCAFBHL (Bit 10)                                     */
+ #define R_GPT7_GTICBSR_BSCAFBHL_Msk     (0xc00UL)      /*!< BSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTICBSR_BSCBRAHL_Pos     (12UL)         /*!< BSCBRAHL (Bit 12)                                     */
+ #define R_GPT7_GTICBSR_BSCBRAHL_Msk     (0x3000UL)     /*!< BSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTICBSR_BSCBFAHL_Pos     (14UL)         /*!< BSCBFAHL (Bit 14)                                     */
+ #define R_GPT7_GTICBSR_BSCBFAHL_Msk     (0xc000UL)     /*!< BSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT7_GTICBSR_BSELCA_Pos       (16UL)         /*!< BSELCA (Bit 16)                                       */
+ #define R_GPT7_GTICBSR_BSELCA_Msk       (0x10000UL)    /*!< BSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICBSR_BSELCB_Pos       (17UL)         /*!< BSELCB (Bit 17)                                       */
+ #define R_GPT7_GTICBSR_BSELCB_Msk       (0x20000UL)    /*!< BSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICBSR_BSELCC_Pos       (18UL)         /*!< BSELCC (Bit 18)                                       */
+ #define R_GPT7_GTICBSR_BSELCC_Msk       (0x40000UL)    /*!< BSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICBSR_BSELCD_Pos       (19UL)         /*!< BSELCD (Bit 19)                                       */
+ #define R_GPT7_GTICBSR_BSELCD_Msk       (0x80000UL)    /*!< BSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICBSR_BSELCE_Pos       (20UL)         /*!< BSELCE (Bit 20)                                       */
+ #define R_GPT7_GTICBSR_BSELCE_Msk       (0x100000UL)   /*!< BSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICBSR_BSELCF_Pos       (21UL)         /*!< BSELCF (Bit 21)                                       */
+ #define R_GPT7_GTICBSR_BSELCF_Msk       (0x200000UL)   /*!< BSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICBSR_BSELCG_Pos       (22UL)         /*!< BSELCG (Bit 22)                                       */
+ #define R_GPT7_GTICBSR_BSELCG_Msk       (0x400000UL)   /*!< BSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTICBSR_BSELCH_Pos       (23UL)         /*!< BSELCH (Bit 23)                                       */
+ #define R_GPT7_GTICBSR_BSELCH_Msk       (0x800000UL)   /*!< BSELCH (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTCR  ========================================================== */
+ #define R_GPT7_GTCR_CST_Pos             (0UL)          /*!< CST (Bit 0)                                           */
+ #define R_GPT7_GTCR_CST_Msk             (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTCR_ICDS_Pos            (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT7_GTCR_ICDS_Msk            (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTCR_MD_Pos              (16UL)         /*!< MD (Bit 16)                                           */
+ #define R_GPT7_GTCR_MD_Msk              (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT7_GTCR_TPCS_Pos            (23UL)         /*!< TPCS (Bit 23)                                         */
+ #define R_GPT7_GTCR_TPCS_Msk            (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
+ #define R_GPT7_GTCR_SWMD_Pos            (29UL)         /*!< SWMD (Bit 29)                                         */
+ #define R_GPT7_GTCR_SWMD_Msk            (0xe0000000UL) /*!< SWMD (Bitfield-Mask: 0x07)                            */
+/* =======================================================  GTUDDTYC  ======================================================== */
+ #define R_GPT7_GTUDDTYC_UD_Pos          (0UL)          /*!< UD (Bit 0)                                            */
+ #define R_GPT7_GTUDDTYC_UD_Msk          (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
+ #define R_GPT7_GTUDDTYC_UDF_Pos         (1UL)          /*!< UDF (Bit 1)                                           */
+ #define R_GPT7_GTUDDTYC_UDF_Msk         (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTUDDTYC_OADTY_Pos       (16UL)         /*!< OADTY (Bit 16)                                        */
+ #define R_GPT7_GTUDDTYC_OADTY_Msk       (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT7_GTUDDTYC_OADTYF_Pos      (18UL)         /*!< OADTYF (Bit 18)                                       */
+ #define R_GPT7_GTUDDTYC_OADTYF_Msk      (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUDDTYC_OADTYR_Pos      (19UL)         /*!< OADTYR (Bit 19)                                       */
+ #define R_GPT7_GTUDDTYC_OADTYR_Msk      (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUDDTYC_OBDTY_Pos       (24UL)         /*!< OBDTY (Bit 24)                                        */
+ #define R_GPT7_GTUDDTYC_OBDTY_Msk       (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT7_GTUDDTYC_OBDTYF_Pos      (26UL)         /*!< OBDTYF (Bit 26)                                       */
+ #define R_GPT7_GTUDDTYC_OBDTYF_Msk      (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTUDDTYC_OBDTYR_Pos      (27UL)         /*!< OBDTYR (Bit 27)                                       */
+ #define R_GPT7_GTUDDTYC_OBDTYR_Msk      (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTIOR  ========================================================= */
+ #define R_GPT7_GTIOR_GTIOA_Pos          (0UL)          /*!< GTIOA (Bit 0)                                         */
+ #define R_GPT7_GTIOR_GTIOA_Msk          (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT7_GTIOR_OADFLT_Pos         (6UL)          /*!< OADFLT (Bit 6)                                        */
+ #define R_GPT7_GTIOR_OADFLT_Msk         (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTIOR_OAHLD_Pos          (7UL)          /*!< OAHLD (Bit 7)                                         */
+ #define R_GPT7_GTIOR_OAHLD_Msk          (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTIOR_OAE_Pos            (8UL)          /*!< OAE (Bit 8)                                           */
+ #define R_GPT7_GTIOR_OAE_Msk            (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTIOR_OADF_Pos           (9UL)          /*!< OADF (Bit 9)                                          */
+ #define R_GPT7_GTIOR_OADF_Msk           (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT7_GTIOR_NFAEN_Pos          (13UL)         /*!< NFAEN (Bit 13)                                        */
+ #define R_GPT7_GTIOR_NFAEN_Msk          (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTIOR_NFCSA_Pos          (14UL)         /*!< NFCSA (Bit 14)                                        */
+ #define R_GPT7_GTIOR_NFCSA_Msk          (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT7_GTIOR_GTIOB_Pos          (16UL)         /*!< GTIOB (Bit 16)                                        */
+ #define R_GPT7_GTIOR_GTIOB_Msk          (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT7_GTIOR_OBDFLT_Pos         (22UL)         /*!< OBDFLT (Bit 22)                                       */
+ #define R_GPT7_GTIOR_OBDFLT_Msk         (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTIOR_OBHLD_Pos          (23UL)         /*!< OBHLD (Bit 23)                                        */
+ #define R_GPT7_GTIOR_OBHLD_Msk          (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTIOR_OBE_Pos            (24UL)         /*!< OBE (Bit 24)                                          */
+ #define R_GPT7_GTIOR_OBE_Msk            (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTIOR_OBDF_Pos           (25UL)         /*!< OBDF (Bit 25)                                         */
+ #define R_GPT7_GTIOR_OBDF_Msk           (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT7_GTIOR_NFBEN_Pos          (29UL)         /*!< NFBEN (Bit 29)                                        */
+ #define R_GPT7_GTIOR_NFBEN_Msk          (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTIOR_NFCSB_Pos          (30UL)         /*!< NFCSB (Bit 30)                                        */
+ #define R_GPT7_GTIOR_NFCSB_Msk          (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT7_GTINTAD_GTINTA_Pos       (0UL)          /*!< GTINTA (Bit 0)                                        */
+ #define R_GPT7_GTINTAD_GTINTA_Msk       (0x1UL)        /*!< GTINTA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTINTAD_GTINTB_Pos       (1UL)          /*!< GTINTB (Bit 1)                                        */
+ #define R_GPT7_GTINTAD_GTINTB_Msk       (0x2UL)        /*!< GTINTB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTINTAD_GTINTC_Pos       (2UL)          /*!< GTINTC (Bit 2)                                        */
+ #define R_GPT7_GTINTAD_GTINTC_Msk       (0x4UL)        /*!< GTINTC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTINTAD_GTINTD_Pos       (3UL)          /*!< GTINTD (Bit 3)                                        */
+ #define R_GPT7_GTINTAD_GTINTD_Msk       (0x8UL)        /*!< GTINTD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTINTAD_GTINTE_Pos       (4UL)          /*!< GTINTE (Bit 4)                                        */
+ #define R_GPT7_GTINTAD_GTINTE_Msk       (0x10UL)       /*!< GTINTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTINTAD_GTINTF_Pos       (5UL)          /*!< GTINTF (Bit 5)                                        */
+ #define R_GPT7_GTINTAD_GTINTF_Msk       (0x20UL)       /*!< GTINTF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTINTAD_GTINTPR_Pos      (6UL)          /*!< GTINTPR (Bit 6)                                       */
+ #define R_GPT7_GTINTAD_GTINTPR_Msk      (0xc0UL)       /*!< GTINTPR (Bitfield-Mask: 0x03)                         */
+ #define R_GPT7_GTINTAD_ADTRAUEN_Pos     (16UL)         /*!< ADTRAUEN (Bit 16)                                     */
+ #define R_GPT7_GTINTAD_ADTRAUEN_Msk     (0x10000UL)    /*!< ADTRAUEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT7_GTINTAD_ADTRADEN_Pos     (17UL)         /*!< ADTRADEN (Bit 17)                                     */
+ #define R_GPT7_GTINTAD_ADTRADEN_Msk     (0x20000UL)    /*!< ADTRADEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT7_GTINTAD_ADTRBUEN_Pos     (18UL)         /*!< ADTRBUEN (Bit 18)                                     */
+ #define R_GPT7_GTINTAD_ADTRBUEN_Msk     (0x40000UL)    /*!< ADTRBUEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT7_GTINTAD_ADTRBDEN_Pos     (19UL)         /*!< ADTRBDEN (Bit 19)                                     */
+ #define R_GPT7_GTINTAD_ADTRBDEN_Msk     (0x80000UL)    /*!< ADTRBDEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT7_GTINTAD_GRP_Pos          (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT7_GTINTAD_GRP_Msk          (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+ #define R_GPT7_GTINTAD_GRPDTE_Pos       (28UL)         /*!< GRPDTE (Bit 28)                                       */
+ #define R_GPT7_GTINTAD_GRPDTE_Msk       (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTINTAD_GRPABH_Pos       (29UL)         /*!< GRPABH (Bit 29)                                       */
+ #define R_GPT7_GTINTAD_GRPABH_Msk       (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTINTAD_GRPABL_Pos       (30UL)         /*!< GRPABL (Bit 30)                                       */
+ #define R_GPT7_GTINTAD_GRPABL_Msk       (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTST  ========================================================== */
+ #define R_GPT7_GTST_ITCNT_Pos           (8UL)          /*!< ITCNT (Bit 8)                                         */
+ #define R_GPT7_GTST_ITCNT_Msk           (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
+ #define R_GPT7_GTST_TUCF_Pos            (15UL)         /*!< TUCF (Bit 15)                                         */
+ #define R_GPT7_GTST_TUCF_Msk            (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTST_ADTRAUF_Pos         (16UL)         /*!< ADTRAUF (Bit 16)                                      */
+ #define R_GPT7_GTST_ADTRAUF_Msk         (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTST_ADTRADF_Pos         (17UL)         /*!< ADTRADF (Bit 17)                                      */
+ #define R_GPT7_GTST_ADTRADF_Msk         (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTST_ADTRBUF_Pos         (18UL)         /*!< ADTRBUF (Bit 18)                                      */
+ #define R_GPT7_GTST_ADTRBUF_Msk         (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTST_ADTRBDF_Pos         (19UL)         /*!< ADTRBDF (Bit 19)                                      */
+ #define R_GPT7_GTST_ADTRBDF_Msk         (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTST_ODF_Pos             (24UL)         /*!< ODF (Bit 24)                                          */
+ #define R_GPT7_GTST_ODF_Msk             (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTST_DTEF_Pos            (28UL)         /*!< DTEF (Bit 28)                                         */
+ #define R_GPT7_GTST_DTEF_Msk            (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTST_OABHF_Pos           (29UL)         /*!< OABHF (Bit 29)                                        */
+ #define R_GPT7_GTST_OABHF_Msk           (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTST_OABLF_Pos           (30UL)         /*!< OABLF (Bit 30)                                        */
+ #define R_GPT7_GTST_OABLF_Msk           (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTBER  ========================================================= */
+ #define R_GPT7_GTBER_BD0_Pos            (0UL)          /*!< BD0 (Bit 0)                                           */
+ #define R_GPT7_GTBER_BD0_Msk            (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTBER_BD1_Pos            (1UL)          /*!< BD1 (Bit 1)                                           */
+ #define R_GPT7_GTBER_BD1_Msk            (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTBER_BD2_Pos            (2UL)          /*!< BD2 (Bit 2)                                           */
+ #define R_GPT7_GTBER_BD2_Msk            (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTBER_BD3_Pos            (3UL)          /*!< BD3 (Bit 3)                                           */
+ #define R_GPT7_GTBER_BD3_Msk            (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTBER_DBRTECA_Pos        (8UL)          /*!< DBRTECA (Bit 8)                                       */
+ #define R_GPT7_GTBER_DBRTECA_Msk        (0x100UL)      /*!< DBRTECA (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTBER_DBRTECB_Pos        (10UL)         /*!< DBRTECB (Bit 10)                                      */
+ #define R_GPT7_GTBER_DBRTECB_Msk        (0x400UL)      /*!< DBRTECB (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTBER_CCRA_Pos           (16UL)         /*!< CCRA (Bit 16)                                         */
+ #define R_GPT7_GTBER_CCRA_Msk           (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT7_GTBER_CCRB_Pos           (18UL)         /*!< CCRB (Bit 18)                                         */
+ #define R_GPT7_GTBER_CCRB_Msk           (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
+ #define R_GPT7_GTBER_PR_Pos             (20UL)         /*!< PR (Bit 20)                                           */
+ #define R_GPT7_GTBER_PR_Msk             (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
+ #define R_GPT7_GTBER_CCRSWT_Pos         (22UL)         /*!< CCRSWT (Bit 22)                                       */
+ #define R_GPT7_GTBER_CCRSWT_Msk         (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTBER_ADTTA_Pos          (24UL)         /*!< ADTTA (Bit 24)                                        */
+ #define R_GPT7_GTBER_ADTTA_Msk          (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT7_GTBER_ADTDA_Pos          (26UL)         /*!< ADTDA (Bit 26)                                        */
+ #define R_GPT7_GTBER_ADTDA_Msk          (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTBER_ADTTB_Pos          (28UL)         /*!< ADTTB (Bit 28)                                        */
+ #define R_GPT7_GTBER_ADTTB_Msk          (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT7_GTBER_ADTDB_Pos          (30UL)         /*!< ADTDB (Bit 30)                                        */
+ #define R_GPT7_GTBER_ADTDB_Msk          (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTITC  ========================================================= */
+ #define R_GPT7_GTITC_ITLA_Pos           (0UL)          /*!< ITLA (Bit 0)                                          */
+ #define R_GPT7_GTITC_ITLA_Msk           (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTITC_ITLB_Pos           (1UL)          /*!< ITLB (Bit 1)                                          */
+ #define R_GPT7_GTITC_ITLB_Msk           (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTITC_ITLC_Pos           (2UL)          /*!< ITLC (Bit 2)                                          */
+ #define R_GPT7_GTITC_ITLC_Msk           (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTITC_ITLD_Pos           (3UL)          /*!< ITLD (Bit 3)                                          */
+ #define R_GPT7_GTITC_ITLD_Msk           (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTITC_ITLE_Pos           (4UL)          /*!< ITLE (Bit 4)                                          */
+ #define R_GPT7_GTITC_ITLE_Msk           (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTITC_ITLF_Pos           (5UL)          /*!< ITLF (Bit 5)                                          */
+ #define R_GPT7_GTITC_ITLF_Msk           (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT7_GTITC_IVTC_Pos           (6UL)          /*!< IVTC (Bit 6)                                          */
+ #define R_GPT7_GTITC_IVTC_Msk           (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
+ #define R_GPT7_GTITC_IVTT_Pos           (8UL)          /*!< IVTT (Bit 8)                                          */
+ #define R_GPT7_GTITC_IVTT_Msk           (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
+ #define R_GPT7_GTITC_ADTAL_Pos          (12UL)         /*!< ADTAL (Bit 12)                                        */
+ #define R_GPT7_GTITC_ADTAL_Msk          (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTITC_ADTBL_Pos          (14UL)         /*!< ADTBL (Bit 14)                                        */
+ #define R_GPT7_GTITC_ADTBL_Msk          (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCNT  ========================================================= */
+/* =========================================================  GTCCR  ========================================================= */
+/* =========================================================  GTPR  ========================================================== */
+/* =========================================================  GTPBR  ========================================================= */
+/* ========================================================  GTPDBR  ========================================================= */
+/* ========================================================  GTADTRA  ======================================================== */
+/* =======================================================  GTADTBRA  ======================================================== */
+/* =======================================================  GTADTDBRA  ======================================================= */
+/* ========================================================  GTADTRB  ======================================================== */
+/* =======================================================  GTADTBRB  ======================================================== */
+/* =======================================================  GTADTDBRB  ======================================================= */
+/* ========================================================  GTDTCR  ========================================================= */
+ #define R_GPT7_GTDTCR_TDE_Pos      (0UL)     /*!< TDE (Bit 0)                                           */
+ #define R_GPT7_GTDTCR_TDE_Msk      (0x1UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT7_GTDTCR_TDBUE_Pos    (4UL)     /*!< TDBUE (Bit 4)                                         */
+ #define R_GPT7_GTDTCR_TDBUE_Msk    (0x10UL)  /*!< TDBUE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTDTCR_TDBDE_Pos    (5UL)     /*!< TDBDE (Bit 5)                                         */
+ #define R_GPT7_GTDTCR_TDBDE_Msk    (0x20UL)  /*!< TDBDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTDTCR_TDFER_Pos    (8UL)     /*!< TDFER (Bit 8)                                         */
+ #define R_GPT7_GTDTCR_TDFER_Msk    (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTDVU  ========================================================= */
+/* =========================================================  GTDVD  ========================================================= */
+/* =========================================================  GTDBU  ========================================================= */
+/* =========================================================  GTDBD  ========================================================= */
+/* =========================================================  GTSOS  ========================================================= */
+ #define R_GPT7_GTSOS_SOS_Pos           (0UL)          /*!< SOS (Bit 0)                                           */
+ #define R_GPT7_GTSOS_SOS_Msk           (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
+/* ========================================================  GTSOTR  ========================================================= */
+ #define R_GPT7_GTSOTR_SOTR_Pos         (0UL)          /*!< SOTR (Bit 0)                                          */
+ #define R_GPT7_GTSOTR_SOTR_Msk         (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT7_GTADSMR_ADSMS0_Pos      (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT7_GTADSMR_ADSMS0_Msk      (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT7_GTADSMR_ADSMEN0_Pos     (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT7_GTADSMR_ADSMEN0_Msk     (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTADSMR_ADSMS1_Pos      (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT7_GTADSMR_ADSMS1_Msk      (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT7_GTADSMR_ADSMEN1_Pos     (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT7_GTADSMR_ADSMEN1_Msk     (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT7_GTEITC_EIVTC1_Pos       (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT7_GTEITC_EIVTC1_Msk       (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT7_GTEITC_EIVTT1_Pos       (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT7_GTEITC_EIVTT1_Msk       (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT7_GTEITC_EITCNT1_Pos      (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT7_GTEITC_EITCNT1_Msk      (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT7_GTEITC_EIVTC2_Pos       (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT7_GTEITC_EIVTC2_Msk       (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT7_GTEITC_EIVTT2_Pos       (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT7_GTEITC_EIVTT2_Msk       (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT7_GTEITC_EITCNT2IV_Pos    (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT7_GTEITC_EITCNT2IV_Msk    (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT7_GTEITC_EITCNT2_Pos      (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT7_GTEITC_EITCNT2_Msk      (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT7_GTEITLI1_EITLA_Pos      (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT7_GTEITLI1_EITLA_Msk      (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT7_GTEITLI1_EITLB_Pos      (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT7_GTEITLI1_EITLB_Msk      (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT7_GTEITLI1_EITLC_Pos      (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT7_GTEITLI1_EITLC_Msk      (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT7_GTEITLI1_EITLD_Pos      (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT7_GTEITLI1_EITLD_Msk      (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT7_GTEITLI1_EITLE_Pos      (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT7_GTEITLI1_EITLE_Msk      (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT7_GTEITLI1_EITLF_Pos      (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT7_GTEITLI1_EITLF_Msk      (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT7_GTEITLI1_EITLV_Pos      (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT7_GTEITLI1_EITLV_Msk      (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT7_GTEITLI1_EITLU_Pos      (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT7_GTEITLI1_EITLU_Msk      (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT7_GTEITLI2_EADTAL_Pos     (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT7_GTEITLI2_EADTAL_Msk     (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT7_GTEITLI2_EADTBL_Pos     (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT7_GTEITLI2_EADTBL_Msk     (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT7_GTEITLB_EBTLCA_Pos      (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT7_GTEITLB_EBTLCA_Msk      (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT7_GTEITLB_EBTLCB_Pos      (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT7_GTEITLB_EBTLCB_Msk      (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT7_GTEITLB_EBTLPR_Pos      (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT7_GTEITLB_EBTLPR_Msk      (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT7_GTEITLB_EBTLADA_Pos     (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT7_GTEITLB_EBTLADA_Msk     (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT7_GTEITLB_EBTLADB_Pos     (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT7_GTEITLB_EBTLADB_Msk     (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT7_GTEITLB_EBTLDVU_Pos     (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT7_GTEITLB_EBTLDVU_Msk     (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT7_GTEITLB_EBTLDVD_Pos     (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT7_GTEITLB_EBTLDVD_Msk     (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
+/* ========================================================  GTSECSR  ======================================================== */
+ #define R_GPT7_GTSECSR_SECSEL0_Pos     (0UL)          /*!< SECSEL0 (Bit 0)                                       */
+ #define R_GPT7_GTSECSR_SECSEL0_Msk     (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTSECSR_SECSEL1_Pos     (1UL)          /*!< SECSEL1 (Bit 1)                                       */
+ #define R_GPT7_GTSECSR_SECSEL1_Msk     (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTSECSR_SECSEL2_Pos     (2UL)          /*!< SECSEL2 (Bit 2)                                       */
+ #define R_GPT7_GTSECSR_SECSEL2_Msk     (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTSECSR_SECSEL3_Pos     (3UL)          /*!< SECSEL3 (Bit 3)                                       */
+ #define R_GPT7_GTSECSR_SECSEL3_Msk     (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTSECSR_SECSEL4_Pos     (4UL)          /*!< SECSEL4 (Bit 4)                                       */
+ #define R_GPT7_GTSECSR_SECSEL4_Msk     (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTSECSR_SECSEL5_Pos     (5UL)          /*!< SECSEL5 (Bit 5)                                       */
+ #define R_GPT7_GTSECSR_SECSEL5_Msk     (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT7_GTSECSR_SECSEL6_Pos     (6UL)          /*!< SECSEL6 (Bit 6)                                       */
+ #define R_GPT7_GTSECSR_SECSEL6_Msk     (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTSECR  ========================================================= */
+ #define R_GPT7_GTSECR_SBDCE_Pos        (0UL)          /*!< SBDCE (Bit 0)                                         */
+ #define R_GPT7_GTSECR_SBDCE_Msk        (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTSECR_SBDPE_Pos        (1UL)          /*!< SBDPE (Bit 1)                                         */
+ #define R_GPT7_GTSECR_SBDPE_Msk        (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTSECR_SBDAE_Pos        (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT7_GTSECR_SBDAE_Msk        (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTSECR_SBDDE_Pos        (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT7_GTSECR_SBDDE_Msk        (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTSECR_SBDCD_Pos        (8UL)          /*!< SBDCD (Bit 8)                                         */
+ #define R_GPT7_GTSECR_SBDCD_Msk        (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTSECR_SBDPD_Pos        (9UL)          /*!< SBDPD (Bit 9)                                         */
+ #define R_GPT7_GTSECR_SBDPD_Msk        (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTSECR_SBDAD_Pos        (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT7_GTSECR_SBDAD_Msk        (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT7_GTSECR_SBDDD_Pos        (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT7_GTSECR_SBDDD_Msk        (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  GTSWSR  ========================================================= */
+ #define R_GPT7_GTSWSR_WSGTRGA_Pos      (0UL)          /*!< WSGTRGA (Bit 0)                                       */
+ #define R_GPT7_GTSWSR_WSGTRGA_Msk      (0x3UL)        /*!< WSGTRGA (Bitfield-Mask: 0x03)                         */
+ #define R_GPT7_GTSWSR_WSGTRGB_Pos      (2UL)          /*!< WSGTRGB (Bit 2)                                       */
+ #define R_GPT7_GTSWSR_WSGTRGB_Msk      (0xcUL)        /*!< WSGTRGB (Bitfield-Mask: 0x03)                         */
+ #define R_GPT7_GTSWSR_WSGTRGC_Pos      (4UL)          /*!< WSGTRGC (Bit 4)                                       */
+ #define R_GPT7_GTSWSR_WSGTRGC_Msk      (0x30UL)       /*!< WSGTRGC (Bitfield-Mask: 0x03)                         */
+ #define R_GPT7_GTSWSR_WSGTRGD_Pos      (6UL)          /*!< WSGTRGD (Bit 6)                                       */
+ #define R_GPT7_GTSWSR_WSGTRGD_Msk      (0xc0UL)       /*!< WSGTRGD (Bitfield-Mask: 0x03)                         */
+ #define R_GPT7_GTSWSR_WSELCA_Pos       (16UL)         /*!< WSELCA (Bit 16)                                       */
+ #define R_GPT7_GTSWSR_WSELCA_Msk       (0x10000UL)    /*!< WSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSWSR_WSELCB_Pos       (17UL)         /*!< WSELCB (Bit 17)                                       */
+ #define R_GPT7_GTSWSR_WSELCB_Msk       (0x20000UL)    /*!< WSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSWSR_WSELCC_Pos       (18UL)         /*!< WSELCC (Bit 18)                                       */
+ #define R_GPT7_GTSWSR_WSELCC_Msk       (0x40000UL)    /*!< WSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSWSR_WSELCD_Pos       (19UL)         /*!< WSELCD (Bit 19)                                       */
+ #define R_GPT7_GTSWSR_WSELCD_Msk       (0x80000UL)    /*!< WSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSWSR_WSELCE_Pos       (20UL)         /*!< WSELCE (Bit 20)                                       */
+ #define R_GPT7_GTSWSR_WSELCE_Msk       (0x100000UL)   /*!< WSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSWSR_WSELCF_Pos       (21UL)         /*!< WSELCF (Bit 21)                                       */
+ #define R_GPT7_GTSWSR_WSELCF_Msk       (0x200000UL)   /*!< WSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSWSR_WSELCG_Pos       (22UL)         /*!< WSELCG (Bit 22)                                       */
+ #define R_GPT7_GTSWSR_WSELCG_Msk       (0x400000UL)   /*!< WSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT7_GTSWSR_CSELCH_Pos       (23UL)         /*!< CSELCH (Bit 23)                                       */
+ #define R_GPT7_GTSWSR_CSELCH_Msk       (0x800000UL)   /*!< CSELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTSWOS  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  RDR  ========================================================== */
+ #define R_SCI0_RDR_RDAT_Pos           (0UL)          /*!< RDAT (Bit 0)                                          */
+ #define R_SCI0_RDR_RDAT_Msk           (0x1ffUL)      /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
+ #define R_SCI0_RDR_MPB_Pos            (9UL)          /*!< MPB (Bit 9)                                           */
+ #define R_SCI0_RDR_MPB_Msk            (0x200UL)      /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_RDR_DR_Pos             (10UL)         /*!< DR (Bit 10)                                           */
+ #define R_SCI0_RDR_DR_Msk             (0x400UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_RDR_FPER_Pos           (11UL)         /*!< FPER (Bit 11)                                         */
+ #define R_SCI0_RDR_FPER_Msk           (0x800UL)      /*!< FPER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_RDR_FFER_Pos           (12UL)         /*!< FFER (Bit 12)                                         */
+ #define R_SCI0_RDR_FFER_Msk           (0x1000UL)     /*!< FFER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_RDR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
+ #define R_SCI0_RDR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_RDR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
+ #define R_SCI0_RDR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_RDR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
+ #define R_SCI0_RDR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  TDR  ========================================================== */
+ #define R_SCI0_TDR_TDAT_Pos           (0UL)          /*!< TDAT (Bit 0)                                          */
+ #define R_SCI0_TDR_TDAT_Msk           (0x1ffUL)      /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
+ #define R_SCI0_TDR_MPBT_Pos           (9UL)          /*!< MPBT (Bit 9)                                          */
+ #define R_SCI0_TDR_MPBT_Msk           (0x200UL)      /*!< MPBT (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CCR0  ========================================================== */
+ #define R_SCI0_CCR0_RE_Pos            (0UL)          /*!< RE (Bit 0)                                            */
+ #define R_SCI0_CCR0_RE_Msk            (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR0_TE_Pos            (4UL)          /*!< TE (Bit 4)                                            */
+ #define R_SCI0_CCR0_TE_Msk            (0x10UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR0_MPIE_Pos          (8UL)          /*!< MPIE (Bit 8)                                          */
+ #define R_SCI0_CCR0_MPIE_Msk          (0x100UL)      /*!< MPIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR0_DCME_Pos          (9UL)          /*!< DCME (Bit 9)                                          */
+ #define R_SCI0_CCR0_DCME_Msk          (0x200UL)      /*!< DCME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR0_IDSEL_Pos         (10UL)         /*!< IDSEL (Bit 10)                                        */
+ #define R_SCI0_CCR0_IDSEL_Msk         (0x400UL)      /*!< IDSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CCR0_RIE_Pos           (16UL)         /*!< RIE (Bit 16)                                          */
+ #define R_SCI0_CCR0_RIE_Msk           (0x10000UL)    /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR0_TIE_Pos           (20UL)         /*!< TIE (Bit 20)                                          */
+ #define R_SCI0_CCR0_TIE_Msk           (0x100000UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR0_TEIE_Pos          (21UL)         /*!< TEIE (Bit 21)                                         */
+ #define R_SCI0_CCR0_TEIE_Msk          (0x200000UL)   /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR0_SSE_Pos           (24UL)         /*!< SSE (Bit 24)                                          */
+ #define R_SCI0_CCR0_SSE_Msk           (0x1000000UL)  /*!< SSE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CCR1  ========================================================== */
+ #define R_SCI0_CCR1_CTSE_Pos          (0UL)          /*!< CTSE (Bit 0)                                          */
+ #define R_SCI0_CCR1_CTSE_Msk          (0x1UL)        /*!< CTSE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR1_CTSPEN_Pos        (1UL)          /*!< CTSPEN (Bit 1)                                        */
+ #define R_SCI0_CCR1_CTSPEN_Msk        (0x2UL)        /*!< CTSPEN (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CCR1_SPB2DT_Pos        (4UL)          /*!< SPB2DT (Bit 4)                                        */
+ #define R_SCI0_CCR1_SPB2DT_Msk        (0x10UL)       /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CCR1_SPB2IO_Pos        (5UL)          /*!< SPB2IO (Bit 5)                                        */
+ #define R_SCI0_CCR1_SPB2IO_Msk        (0x20UL)       /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CCR1_PE_Pos            (8UL)          /*!< PE (Bit 8)                                            */
+ #define R_SCI0_CCR1_PE_Msk            (0x100UL)      /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR1_PM_Pos            (9UL)          /*!< PM (Bit 9)                                            */
+ #define R_SCI0_CCR1_PM_Msk            (0x200UL)      /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR1_TINV_Pos          (12UL)         /*!< TINV (Bit 12)                                         */
+ #define R_SCI0_CCR1_TINV_Msk          (0x1000UL)     /*!< TINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR1_RINV_Pos          (13UL)         /*!< RINV (Bit 13)                                         */
+ #define R_SCI0_CCR1_RINV_Msk          (0x2000UL)     /*!< RINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR1_SPLP_Pos          (16UL)         /*!< SPLP (Bit 16)                                         */
+ #define R_SCI0_CCR1_SPLP_Msk          (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR1_SHARPS_Pos        (20UL)         /*!< SHARPS (Bit 20)                                       */
+ #define R_SCI0_CCR1_SHARPS_Msk        (0x100000UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CCR1_NFCS_Pos          (24UL)         /*!< NFCS (Bit 24)                                         */
+ #define R_SCI0_CCR1_NFCS_Msk          (0x7000000UL)  /*!< NFCS (Bitfield-Mask: 0x07)                            */
+ #define R_SCI0_CCR1_NFEN_Pos          (28UL)         /*!< NFEN (Bit 28)                                         */
+ #define R_SCI0_CCR1_NFEN_Msk          (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CCR2  ========================================================== */
+ #define R_SCI0_CCR2_BCP_Pos           (0UL)          /*!< BCP (Bit 0)                                           */
+ #define R_SCI0_CCR2_BCP_Msk           (0x7UL)        /*!< BCP (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_CCR2_BGDM_Pos          (4UL)          /*!< BGDM (Bit 4)                                          */
+ #define R_SCI0_CCR2_BGDM_Msk          (0x10UL)       /*!< BGDM (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR2_ABCS_Pos          (5UL)          /*!< ABCS (Bit 5)                                          */
+ #define R_SCI0_CCR2_ABCS_Msk          (0x20UL)       /*!< ABCS (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR2_ABCSE_Pos         (6UL)          /*!< ABCSE (Bit 6)                                         */
+ #define R_SCI0_CCR2_ABCSE_Msk         (0x40UL)       /*!< ABCSE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CCR2_BRR_Pos           (8UL)          /*!< BRR (Bit 8)                                           */
+ #define R_SCI0_CCR2_BRR_Msk           (0xff00UL)     /*!< BRR (Bitfield-Mask: 0xff)                             */
+ #define R_SCI0_CCR2_BRME_Pos          (16UL)         /*!< BRME (Bit 16)                                         */
+ #define R_SCI0_CCR2_BRME_Msk          (0x10000UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR2_CKS_Pos           (20UL)         /*!< CKS (Bit 20)                                          */
+ #define R_SCI0_CCR2_CKS_Msk           (0x300000UL)   /*!< CKS (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_CCR2_MDDR_Pos          (24UL)         /*!< MDDR (Bit 24)                                         */
+ #define R_SCI0_CCR2_MDDR_Msk          (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff)                            */
+/* =========================================================  CCR3  ========================================================== */
+ #define R_SCI0_CCR3_CPHA_Pos          (0UL)          /*!< CPHA (Bit 0)                                          */
+ #define R_SCI0_CCR3_CPHA_Msk          (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_CPOL_Pos          (1UL)          /*!< CPOL (Bit 1)                                          */
+ #define R_SCI0_CCR3_CPOL_Msk          (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_BPEN_Pos          (7UL)          /*!< BPEN (Bit 7)                                          */
+ #define R_SCI0_CCR3_BPEN_Msk          (0x80UL)       /*!< BPEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_CHR_Pos           (8UL)          /*!< CHR (Bit 8)                                           */
+ #define R_SCI0_CCR3_CHR_Msk           (0x300UL)      /*!< CHR (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_CCR3_LSBF_Pos          (12UL)         /*!< LSBF (Bit 12)                                         */
+ #define R_SCI0_CCR3_LSBF_Msk          (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_SINV_Pos          (13UL)         /*!< SINV (Bit 13)                                         */
+ #define R_SCI0_CCR3_SINV_Msk          (0x2000UL)     /*!< SINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_STP_Pos           (14UL)         /*!< STP (Bit 14)                                          */
+ #define R_SCI0_CCR3_STP_Msk           (0x4000UL)     /*!< STP (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR3_RXDESEL_Pos       (15UL)         /*!< RXDESEL (Bit 15)                                      */
+ #define R_SCI0_CCR3_RXDESEL_Msk       (0x8000UL)     /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_CCR3_MOD_Pos           (16UL)         /*!< MOD (Bit 16)                                          */
+ #define R_SCI0_CCR3_MOD_Msk           (0x70000UL)    /*!< MOD (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_CCR3_MP_Pos            (19UL)         /*!< MP (Bit 19)                                           */
+ #define R_SCI0_CCR3_MP_Msk            (0x80000UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR3_FM_Pos            (20UL)         /*!< FM (Bit 20)                                           */
+ #define R_SCI0_CCR3_FM_Msk            (0x100000UL)   /*!< FM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR3_DEN_Pos           (21UL)         /*!< DEN (Bit 21)                                          */
+ #define R_SCI0_CCR3_DEN_Msk           (0x200000UL)   /*!< DEN (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR3_CKE_Pos           (24UL)         /*!< CKE (Bit 24)                                          */
+ #define R_SCI0_CCR3_CKE_Msk           (0x3000000UL)  /*!< CKE (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_CCR3_GM_Pos            (28UL)         /*!< GM (Bit 28)                                           */
+ #define R_SCI0_CCR3_GM_Msk            (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR3_BLK_Pos           (29UL)         /*!< BLK (Bit 29)                                          */
+ #define R_SCI0_CCR3_BLK_Msk           (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CCR4  ========================================================== */
+ #define R_SCI0_CCR4_CMPD_Pos          (0UL)          /*!< CMPD (Bit 0)                                          */
+ #define R_SCI0_CCR4_CMPD_Msk          (0x1ffUL)      /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
+ #define R_SCI0_CCR4_ASEN_Pos          (16UL)         /*!< ASEN (Bit 16)                                         */
+ #define R_SCI0_CCR4_ASEN_Msk          (0x10000UL)    /*!< ASEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR4_ATEN_Pos          (17UL)         /*!< ATEN (Bit 17)                                         */
+ #define R_SCI0_CCR4_ATEN_Msk          (0x20000UL)    /*!< ATEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR4_AST_Pos           (24UL)         /*!< AST (Bit 24)                                          */
+ #define R_SCI0_CCR4_AST_Msk           (0x7000000UL)  /*!< AST (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_CCR4_AJD_Pos           (27UL)         /*!< AJD (Bit 27)                                          */
+ #define R_SCI0_CCR4_AJD_Msk           (0x8000000UL)  /*!< AJD (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR4_ATT_Pos           (28UL)         /*!< ATT (Bit 28)                                          */
+ #define R_SCI0_CCR4_ATT_Msk           (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_CCR4_AET_Pos           (31UL)         /*!< AET (Bit 31)                                          */
+ #define R_SCI0_CCR4_AET_Msk           (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  ICR  ========================================================== */
+ #define R_SCI0_ICR_IICDL_Pos          (0UL)          /*!< IICDL (Bit 0)                                         */
+ #define R_SCI0_ICR_IICDL_Msk          (0x1fUL)       /*!< IICDL (Bitfield-Mask: 0x1f)                           */
+ #define R_SCI0_ICR_IICINTM_Pos        (8UL)          /*!< IICINTM (Bit 8)                                       */
+ #define R_SCI0_ICR_IICINTM_Msk        (0x100UL)      /*!< IICINTM (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_ICR_IICCSC_Pos         (9UL)          /*!< IICCSC (Bit 9)                                        */
+ #define R_SCI0_ICR_IICCSC_Msk         (0x200UL)      /*!< IICCSC (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_ICR_IICACKT_Pos        (13UL)         /*!< IICACKT (Bit 13)                                      */
+ #define R_SCI0_ICR_IICACKT_Msk        (0x2000UL)     /*!< IICACKT (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_ICR_IICSTAREQ_Pos      (16UL)         /*!< IICSTAREQ (Bit 16)                                    */
+ #define R_SCI0_ICR_IICSTAREQ_Msk      (0x10000UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SCI0_ICR_IICRSTAREQ_Pos     (17UL)         /*!< IICRSTAREQ (Bit 17)                                   */
+ #define R_SCI0_ICR_IICRSTAREQ_Msk     (0x20000UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
+ #define R_SCI0_ICR_IICSTPREQ_Pos      (18UL)         /*!< IICSTPREQ (Bit 18)                                    */
+ #define R_SCI0_ICR_IICSTPREQ_Msk      (0x40000UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SCI0_ICR_IICSDAS_Pos        (20UL)         /*!< IICSDAS (Bit 20)                                      */
+ #define R_SCI0_ICR_IICSDAS_Msk        (0x300000UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
+ #define R_SCI0_ICR_IICSCLS_Pos        (22UL)         /*!< IICSCLS (Bit 22)                                      */
+ #define R_SCI0_ICR_IICSCLS_Msk        (0xc00000UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
+/* ==========================================================  FCR  ========================================================== */
+ #define R_SCI0_FCR_DRES_Pos           (0UL)          /*!< DRES (Bit 0)                                          */
+ #define R_SCI0_FCR_DRES_Msk           (0x1UL)        /*!< DRES (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FCR_TTRG_Pos           (8UL)          /*!< TTRG (Bit 8)                                          */
+ #define R_SCI0_FCR_TTRG_Msk           (0x1f00UL)     /*!< TTRG (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_FCR_TFRST_Pos          (15UL)         /*!< TFRST (Bit 15)                                        */
+ #define R_SCI0_FCR_TFRST_Msk          (0x8000UL)     /*!< TFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_RTRG_Pos           (16UL)         /*!< RTRG (Bit 16)                                         */
+ #define R_SCI0_FCR_RTRG_Msk           (0x1f0000UL)   /*!< RTRG (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_FCR_RFRST_Pos          (23UL)         /*!< RFRST (Bit 23)                                        */
+ #define R_SCI0_FCR_RFRST_Msk          (0x800000UL)   /*!< RFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_RSTRG_Pos          (24UL)         /*!< RSTRG (Bit 24)                                        */
+ #define R_SCI0_FCR_RSTRG_Msk          (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f)                           */
+/* ==========================================================  DCR  ========================================================== */
+ #define R_SCI0_DCR_DEPOL_Pos          (0UL)          /*!< DEPOL (Bit 0)                                         */
+ #define R_SCI0_DCR_DEPOL_Msk          (0x1UL)        /*!< DEPOL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_DCR_DEAST_Pos          (8UL)          /*!< DEAST (Bit 8)                                         */
+ #define R_SCI0_DCR_DEAST_Msk          (0x1f00UL)     /*!< DEAST (Bitfield-Mask: 0x1f)                           */
+ #define R_SCI0_DCR_DENGT_Pos          (16UL)         /*!< DENGT (Bit 16)                                        */
+ #define R_SCI0_DCR_DENGT_Msk          (0x1f0000UL)   /*!< DENGT (Bitfield-Mask: 0x1f)                           */
+/* ==========================================================  CSR  ========================================================== */
+ #define R_SCI0_CSR_ERS_Pos            (4UL)          /*!< ERS (Bit 4)                                           */
+ #define R_SCI0_CSR_ERS_Msk            (0x10UL)       /*!< ERS (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CSR_RXDMON_Pos         (15UL)         /*!< RXDMON (Bit 15)                                       */
+ #define R_SCI0_CSR_RXDMON_Msk         (0x8000UL)     /*!< RXDMON (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CSR_DCMF_Pos           (16UL)         /*!< DCMF (Bit 16)                                         */
+ #define R_SCI0_CSR_DCMF_Msk           (0x10000UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_DPER_Pos           (17UL)         /*!< DPER (Bit 17)                                         */
+ #define R_SCI0_CSR_DPER_Msk           (0x20000UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_DFER_Pos           (18UL)         /*!< DFER (Bit 18)                                         */
+ #define R_SCI0_CSR_DFER_Msk           (0x40000UL)    /*!< DFER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
+ #define R_SCI0_CSR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_MFF_Pos            (26UL)         /*!< MFF (Bit 26)                                          */
+ #define R_SCI0_CSR_MFF_Msk            (0x4000000UL)  /*!< MFF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CSR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
+ #define R_SCI0_CSR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CSR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
+ #define R_SCI0_CSR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CSR_TDRE_Pos           (29UL)         /*!< TDRE (Bit 29)                                         */
+ #define R_SCI0_CSR_TDRE_Msk           (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_TEND_Pos           (30UL)         /*!< TEND (Bit 30)                                         */
+ #define R_SCI0_CSR_TEND_Msk           (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_RDRF_Pos           (31UL)         /*!< RDRF (Bit 31)                                         */
+ #define R_SCI0_CSR_RDRF_Msk           (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  ISR  ========================================================== */
+ #define R_SCI0_ISR_IICACKR_Pos        (0UL)          /*!< IICACKR (Bit 0)                                       */
+ #define R_SCI0_ISR_IICACKR_Msk        (0x1UL)        /*!< IICACKR (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_ISR_IICSTIF_Pos        (3UL)          /*!< IICSTIF (Bit 3)                                       */
+ #define R_SCI0_ISR_IICSTIF_Msk        (0x8UL)        /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
+/* =========================================================  FRSR  ========================================================== */
+ #define R_SCI0_FRSR_DR_Pos            (0UL)          /*!< DR (Bit 0)                                            */
+ #define R_SCI0_FRSR_DR_Msk            (0x1UL)        /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_FRSR_R_Pos             (8UL)          /*!< R (Bit 8)                                             */
+ #define R_SCI0_FRSR_R_Msk             (0x3f00UL)     /*!< R (Bitfield-Mask: 0x3f)                               */
+ #define R_SCI0_FRSR_PNUM_Pos          (16UL)         /*!< PNUM (Bit 16)                                         */
+ #define R_SCI0_FRSR_PNUM_Msk          (0x3f0000UL)   /*!< PNUM (Bitfield-Mask: 0x3f)                            */
+ #define R_SCI0_FRSR_FNUM_Pos          (24UL)         /*!< FNUM (Bit 24)                                         */
+ #define R_SCI0_FRSR_FNUM_Msk          (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f)                            */
+/* =========================================================  FTSR  ========================================================== */
+ #define R_SCI0_FTSR_T_Pos             (0UL)          /*!< T (Bit 0)                                             */
+ #define R_SCI0_FTSR_T_Msk             (0x3fUL)       /*!< T (Bitfield-Mask: 0x3f)                               */
+/* =========================================================  CFCLR  ========================================================= */
+ #define R_SCI0_CFCLR_ERSC_Pos         (4UL)          /*!< ERSC (Bit 4)                                          */
+ #define R_SCI0_CFCLR_ERSC_Msk         (0x10UL)       /*!< ERSC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CFCLR_DCMFC_Pos        (16UL)         /*!< DCMFC (Bit 16)                                        */
+ #define R_SCI0_CFCLR_DCMFC_Msk        (0x10000UL)    /*!< DCMFC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_DPERC_Pos        (17UL)         /*!< DPERC (Bit 17)                                        */
+ #define R_SCI0_CFCLR_DPERC_Msk        (0x20000UL)    /*!< DPERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_DFERC_Pos        (18UL)         /*!< DFERC (Bit 18)                                        */
+ #define R_SCI0_CFCLR_DFERC_Msk        (0x40000UL)    /*!< DFERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_ORERC_Pos        (24UL)         /*!< ORERC (Bit 24)                                        */
+ #define R_SCI0_CFCLR_ORERC_Msk        (0x1000000UL)  /*!< ORERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_MFFC_Pos         (26UL)         /*!< MFFC (Bit 26)                                         */
+ #define R_SCI0_CFCLR_MFFC_Msk         (0x4000000UL)  /*!< MFFC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CFCLR_PERC_Pos         (27UL)         /*!< PERC (Bit 27)                                         */
+ #define R_SCI0_CFCLR_PERC_Msk         (0x8000000UL)  /*!< PERC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CFCLR_FERC_Pos         (28UL)         /*!< FERC (Bit 28)                                         */
+ #define R_SCI0_CFCLR_FERC_Msk         (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CFCLR_TDREC_Pos        (29UL)         /*!< TDREC (Bit 29)                                        */
+ #define R_SCI0_CFCLR_TDREC_Msk        (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_RDRFC_Pos        (31UL)         /*!< RDRFC (Bit 31)                                        */
+ #define R_SCI0_CFCLR_RDRFC_Msk        (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ICFCLR  ========================================================= */
+ #define R_SCI0_ICFCLR_IICSTIFC_Pos    (3UL)          /*!< IICSTIFC (Bit 3)                                      */
+ #define R_SCI0_ICFCLR_IICSTIFC_Msk    (0x8UL)        /*!< IICSTIFC (Bitfield-Mask: 0x01)                        */
+/* =========================================================  FFCLR  ========================================================= */
+ #define R_SCI0_FFCLR_DRC_Pos          (0UL)          /*!< DRC (Bit 0)                                           */
+ #define R_SCI0_FFCLR_DRC_Msk          (0x1UL)        /*!< DRC (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SPDR  ========================================================== */
+ #define R_SPI0_SPDR_SPD_Pos         (0UL)          /*!< SPD (Bit 0)                                           */
+ #define R_SPI0_SPDR_SPD_Msk         (0xffffffffUL) /*!< SPD (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SPDR_HA  ======================================================== */
+/* ========================================================  SPDR_BY  ======================================================== */
+/* =========================================================  SPCKD  ========================================================= */
+ #define R_SPI0_SPCKD_SCKDL_Pos      (0UL)          /*!< SCKDL (Bit 0)                                         */
+ #define R_SPI0_SPCKD_SCKDL_Msk      (0x7UL)        /*!< SCKDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SSLND  ========================================================= */
+ #define R_SPI0_SSLND_SLNDL_Pos      (0UL)          /*!< SLNDL (Bit 0)                                         */
+ #define R_SPI0_SSLND_SLNDL_Msk      (0x7UL)        /*!< SLNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPND  ========================================================== */
+ #define R_SPI0_SPND_SPNDL_Pos       (0UL)          /*!< SPNDL (Bit 0)                                         */
+ #define R_SPI0_SPND_SPNDL_Msk       (0x7UL)        /*!< SPNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  MRCKD  ========================================================= */
+ #define R_SPI0_MRCKD_ARST_Pos       (0UL)          /*!< ARST (Bit 0)                                          */
+ #define R_SPI0_MRCKD_ARST_Msk       (0x7UL)        /*!< ARST (Bitfield-Mask: 0x07)                            */
+/* =========================================================  SPCR  ========================================================== */
+ #define R_SPI0_SPCR_SPE_Pos         (0UL)          /*!< SPE (Bit 0)                                           */
+ #define R_SPI0_SPCR_SPE_Msk         (0x1UL)        /*!< SPE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR_SPSCKSEL_Pos    (7UL)          /*!< SPSCKSEL (Bit 7)                                      */
+ #define R_SPI0_SPCR_SPSCKSEL_Msk    (0x80UL)       /*!< SPSCKSEL (Bitfield-Mask: 0x01)                        */
+ #define R_SPI0_SPCR_SPPE_Pos        (8UL)          /*!< SPPE (Bit 8)                                          */
+ #define R_SPI0_SPCR_SPPE_Msk        (0x100UL)      /*!< SPPE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_SPOE_Pos        (9UL)          /*!< SPOE (Bit 9)                                          */
+ #define R_SPI0_SPCR_SPOE_Msk        (0x200UL)      /*!< SPOE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_PTE_Pos         (11UL)         /*!< PTE (Bit 11)                                          */
+ #define R_SPI0_SPCR_PTE_Msk         (0x800UL)      /*!< PTE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR_SCKASE_Pos      (12UL)         /*!< SCKASE (Bit 12)                                       */
+ #define R_SPI0_SPCR_SCKASE_Msk      (0x1000UL)     /*!< SCKASE (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_BFDS_Pos        (13UL)         /*!< BFDS (Bit 13)                                         */
+ #define R_SPI0_SPCR_BFDS_Msk        (0x2000UL)     /*!< BFDS (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_MODFEN_Pos      (14UL)         /*!< MODFEN (Bit 14)                                       */
+ #define R_SPI0_SPCR_MODFEN_Msk      (0x4000UL)     /*!< MODFEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_SPEIE_Pos       (16UL)         /*!< SPEIE (Bit 16)                                        */
+ #define R_SPI0_SPCR_SPEIE_Msk       (0x10000UL)    /*!< SPEIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPRIE_Pos       (17UL)         /*!< SPRIE (Bit 17)                                        */
+ #define R_SPI0_SPCR_SPRIE_Msk       (0x20000UL)    /*!< SPRIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPIIE_Pos       (18UL)         /*!< SPIIE (Bit 18)                                        */
+ #define R_SPI0_SPCR_SPIIE_Msk       (0x40000UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPDRES_Pos      (19UL)         /*!< SPDRES (Bit 19)                                       */
+ #define R_SPI0_SPCR_SPDRES_Msk      (0x80000UL)    /*!< SPDRES (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_SPTIE_Pos       (20UL)         /*!< SPTIE (Bit 20)                                        */
+ #define R_SPI0_SPCR_SPTIE_Msk       (0x100000UL)   /*!< SPTIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_CENDIE_Pos      (21UL)         /*!< CENDIE (Bit 21)                                       */
+ #define R_SPI0_SPCR_CENDIE_Msk      (0x200000UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_SPMS_Pos        (24UL)         /*!< SPMS (Bit 24)                                         */
+ #define R_SPI0_SPCR_SPMS_Msk        (0x1000000UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_SPFRF_Pos       (25UL)         /*!< SPFRF (Bit 25)                                        */
+ #define R_SPI0_SPCR_SPFRF_Msk       (0x2000000UL)  /*!< SPFRF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_TXMD_Pos        (28UL)         /*!< TXMD (Bit 28)                                         */
+ #define R_SPI0_SPCR_TXMD_Msk        (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPCR_MSTR_Pos        (30UL)         /*!< MSTR (Bit 30)                                         */
+ #define R_SPI0_SPCR_MSTR_Msk        (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_BPEN_Pos        (31UL)         /*!< BPEN (Bit 31)                                         */
+ #define R_SPI0_SPCR_BPEN_Msk        (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SPCRRM  ========================================================= */
+ #define R_SPI0_SPCRRM_RMFM_Pos      (0UL)          /*!< RMFM (Bit 0)                                          */
+ #define R_SPI0_SPCRRM_RMFM_Msk      (0x1fUL)       /*!< RMFM (Bitfield-Mask: 0x1f)                            */
+ #define R_SPI0_SPCRRM_RMEDTG_Pos    (6UL)          /*!< RMEDTG (Bit 6)                                        */
+ #define R_SPI0_SPCRRM_RMEDTG_Msk    (0x40UL)       /*!< RMEDTG (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCRRM_RMSTTG_Pos    (7UL)          /*!< RMSTTG (Bit 7)                                        */
+ #define R_SPI0_SPCRRM_RMSTTG_Msk    (0x80UL)       /*!< RMSTTG (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SPDRCR  ========================================================= */
+ #define R_SPI0_SPDRCR_SPDRC_Pos     (0UL)          /*!< SPDRC (Bit 0)                                         */
+ #define R_SPI0_SPDRCR_SPDRC_Msk     (0xffUL)       /*!< SPDRC (Bitfield-Mask: 0xff)                           */
+/* =========================================================  SPPCR  ========================================================= */
+ #define R_SPI0_SPPCR_SPLP_Pos       (0UL)          /*!< SPLP (Bit 0)                                          */
+ #define R_SPI0_SPPCR_SPLP_Msk       (0x1UL)        /*!< SPLP (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPPCR_SPLP2_Pos      (1UL)          /*!< SPLP2 (Bit 1)                                         */
+ #define R_SPI0_SPPCR_SPLP2_Msk      (0x2UL)        /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_SPOM_Pos       (2UL)          /*!< SPOM (Bit 2)                                          */
+ #define R_SPI0_SPPCR_SPOM_Msk       (0x4UL)        /*!< SPOM (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPPCR_MOIFV_Pos      (4UL)          /*!< MOIFV (Bit 4)                                         */
+ #define R_SPI0_SPPCR_MOIFV_Msk      (0x10UL)       /*!< MOIFV (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_MOIFE_Pos      (5UL)          /*!< MOIFE (Bit 5)                                         */
+ #define R_SPI0_SPPCR_MOIFE_Msk      (0x20UL)       /*!< MOIFE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPCR2  ========================================================= */
+ #define R_SPI0_SPCR2_SPSCKDL_Pos    (0UL)          /*!< SPSCKDL (Bit 0)                                       */
+ #define R_SPI0_SPCR2_SPSCKDL_Msk    (0x7UL)        /*!< SPSCKDL (Bitfield-Mask: 0x07)                         */
+/* =========================================================  SSLP  ========================================================== */
+ #define R_SPI0_SSLP_SSL0P_Pos       (0UL)          /*!< SSL0P (Bit 0)                                         */
+ #define R_SPI0_SSLP_SSL0P_Msk       (0x1UL)        /*!< SSL0P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL1P_Pos       (1UL)          /*!< SSL1P (Bit 1)                                         */
+ #define R_SPI0_SSLP_SSL1P_Msk       (0x2UL)        /*!< SSL1P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL2P_Pos       (2UL)          /*!< SSL2P (Bit 2)                                         */
+ #define R_SPI0_SSLP_SSL2P_Msk       (0x4UL)        /*!< SSL2P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL3P_Pos       (3UL)          /*!< SSL3P (Bit 3)                                         */
+ #define R_SPI0_SSLP_SSL3P_Msk       (0x8UL)        /*!< SSL3P (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPBR  ========================================================== */
+ #define R_SPI0_SPBR_SPR_Pos         (0UL)          /*!< SPR (Bit 0)                                           */
+ #define R_SPI0_SPBR_SPR_Msk         (0xffUL)       /*!< SPR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  SPSCR  ========================================================= */
+ #define R_SPI0_SPSCR_SPSLN_Pos      (0UL)          /*!< SPSLN (Bit 0)                                         */
+ #define R_SPI0_SPSCR_SPSLN_Msk      (0x7UL)        /*!< SPSLN (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPCMD  ========================================================= */
+ #define R_SPI0_SPCMD_CPHA_Pos       (0UL)          /*!< CPHA (Bit 0)                                          */
+ #define R_SPI0_SPCMD_CPHA_Msk       (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_CPOL_Pos       (1UL)          /*!< CPOL (Bit 1)                                          */
+ #define R_SPI0_SPCMD_CPOL_Msk       (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_BRDV_Pos       (2UL)          /*!< BRDV (Bit 2)                                          */
+ #define R_SPI0_SPCMD_BRDV_Msk       (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPCMD_SSLKP_Pos      (7UL)          /*!< SSLKP (Bit 7)                                         */
+ #define R_SPI0_SPCMD_SSLKP_Msk      (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCMD_LSBF_Pos       (12UL)         /*!< LSBF (Bit 12)                                         */
+ #define R_SPI0_SPCMD_LSBF_Msk       (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_SPNDEN_Pos     (13UL)         /*!< SPNDEN (Bit 13)                                       */
+ #define R_SPI0_SPCMD_SPNDEN_Msk     (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SLNDEN_Pos     (14UL)         /*!< SLNDEN (Bit 14)                                       */
+ #define R_SPI0_SPCMD_SLNDEN_Msk     (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SCKDEN_Pos     (15UL)         /*!< SCKDEN (Bit 15)                                       */
+ #define R_SPI0_SPCMD_SCKDEN_Msk     (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SPB_Pos        (16UL)         /*!< SPB (Bit 16)                                          */
+ #define R_SPI0_SPCMD_SPB_Msk        (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
+ #define R_SPI0_SPCMD_SSLA_Pos       (24UL)         /*!< SSLA (Bit 24)                                         */
+ #define R_SPI0_SPCMD_SSLA_Msk       (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x03)                            */
+/* =========================================================  SPDCR  ========================================================= */
+ #define R_SPI0_SPDCR_BYSW_Pos       (0UL)          /*!< BYSW (Bit 0)                                          */
+ #define R_SPI0_SPDCR_BYSW_Msk       (0x1UL)        /*!< BYSW (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR_SLSEL_Pos      (1UL)          /*!< SLSEL (Bit 1)                                         */
+ #define R_SPI0_SPDCR_SLSEL_Msk      (0x6UL)        /*!< SLSEL (Bitfield-Mask: 0x03)                           */
+ #define R_SPI0_SPDCR_SPRDTD_Pos     (3UL)          /*!< SPRDTD (Bit 3)                                        */
+ #define R_SPI0_SPDCR_SPRDTD_Msk     (0x8UL)        /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPDCR_SINV_Pos       (4UL)          /*!< SINV (Bit 4)                                          */
+ #define R_SPI0_SPDCR_SINV_Msk       (0x10UL)       /*!< SINV (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR_SPFC_Pos       (8UL)          /*!< SPFC (Bit 8)                                          */
+ #define R_SPI0_SPDCR_SPFC_Msk       (0x300UL)      /*!< SPFC (Bitfield-Mask: 0x03)                            */
+/* ========================================================  SPDCR2  ========================================================= */
+ #define R_SPI0_SPDCR2_RTRG_Pos      (0UL)          /*!< RTRG (Bit 0)                                          */
+ #define R_SPI0_SPDCR2_RTRG_Msk      (0x3UL)        /*!< RTRG (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPDCR2_TTRG_Pos      (8UL)          /*!< TTRG (Bit 8)                                          */
+ #define R_SPI0_SPDCR2_TTRG_Msk      (0x300UL)      /*!< TTRG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  SPSSR  ========================================================= */
+ #define R_SPI0_SPSSR_SPCP_Pos       (0UL)          /*!< SPCP (Bit 0)                                          */
+ #define R_SPI0_SPSSR_SPCP_Msk       (0x7UL)        /*!< SPCP (Bitfield-Mask: 0x07)                            */
+ #define R_SPI0_SPSSR_SPECM_Pos      (4UL)          /*!< SPECM (Bit 4)                                         */
+ #define R_SPI0_SPSSR_SPECM_Msk      (0x70UL)       /*!< SPECM (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPSR  ========================================================== */
+ #define R_SPI0_SPSR_SPDRF_Pos       (7UL)          /*!< SPDRF (Bit 7)                                         */
+ #define R_SPI0_SPSR_SPDRF_Msk       (0x80UL)       /*!< SPDRF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_OVRF_Pos        (8UL)          /*!< OVRF (Bit 8)                                          */
+ #define R_SPI0_SPSR_OVRF_Msk        (0x100UL)      /*!< OVRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_IDLNF_Pos       (9UL)          /*!< IDLNF (Bit 9)                                         */
+ #define R_SPI0_SPSR_IDLNF_Msk       (0x200UL)      /*!< IDLNF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_MODF_Pos        (10UL)         /*!< MODF (Bit 10)                                         */
+ #define R_SPI0_SPSR_MODF_Msk        (0x400UL)      /*!< MODF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_PERF_Pos        (11UL)         /*!< PERF (Bit 11)                                         */
+ #define R_SPI0_SPSR_PERF_Msk        (0x800UL)      /*!< PERF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_UDRF_Pos        (12UL)         /*!< UDRF (Bit 12)                                         */
+ #define R_SPI0_SPSR_UDRF_Msk        (0x1000UL)     /*!< UDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_SPTEF_Pos       (13UL)         /*!< SPTEF (Bit 13)                                        */
+ #define R_SPI0_SPSR_SPTEF_Msk       (0x2000UL)     /*!< SPTEF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_CENDF_Pos       (14UL)         /*!< CENDF (Bit 14)                                        */
+ #define R_SPI0_SPSR_CENDF_Msk       (0x4000UL)     /*!< CENDF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_SPRF_Pos        (15UL)         /*!< SPRF (Bit 15)                                         */
+ #define R_SPI0_SPSR_SPRF_Msk        (0x8000UL)     /*!< SPRF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SPTFSR  ========================================================= */
+ #define R_SPI0_SPTFSR_TFDN_Pos      (0UL)          /*!< TFDN (Bit 0)                                          */
+ #define R_SPI0_SPTFSR_TFDN_Msk      (0x7UL)        /*!< TFDN (Bitfield-Mask: 0x07)                            */
+/* ========================================================  SPRFSR  ========================================================= */
+ #define R_SPI0_SPRFSR_RFDN_Pos      (0UL)          /*!< RFDN (Bit 0)                                          */
+ #define R_SPI0_SPRFSR_RFDN_Msk      (0x7UL)        /*!< RFDN (Bitfield-Mask: 0x07)                            */
+/* =========================================================  SPPSR  ========================================================= */
+ #define R_SPI0_SPPSR_SPEPS_Pos      (0UL)          /*!< SPEPS (Bit 0)                                         */
+ #define R_SPI0_SPPSR_SPEPS_Msk      (0x1UL)        /*!< SPEPS (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPSRC  ========================================================= */
+ #define R_SPI0_SPSRC_SPDRFC_Pos     (7UL)          /*!< SPDRFC (Bit 7)                                        */
+ #define R_SPI0_SPSRC_SPDRFC_Msk     (0x80UL)       /*!< SPDRFC (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPSRC_OVRFC_Pos      (8UL)          /*!< OVRFC (Bit 8)                                         */
+ #define R_SPI0_SPSRC_OVRFC_Msk      (0x100UL)      /*!< OVRFC (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSRC_MODFC_Pos      (10UL)         /*!< MODFC (Bit 10)                                        */
+ #define R_SPI0_SPSRC_MODFC_Msk      (0x400UL)      /*!< MODFC (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSRC_PERFC_Pos      (11UL)         /*!< PERFC (Bit 11)                                        */
+ #define R_SPI0_SPSRC_PERFC_Msk      (0x800UL)      /*!< PERFC (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSRC_UDRFC_Pos      (12UL)         /*!< UDRFC (Bit 12)                                        */
+ #define R_SPI0_SPSRC_UDRFC_Msk      (0x1000UL)     /*!< UDRFC (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSRC_SPTEFC_Pos     (13UL)         /*!< SPTEFC (Bit 13)                                       */
+ #define R_SPI0_SPSRC_SPTEFC_Msk     (0x2000UL)     /*!< SPTEFC (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPSRC_CENDFC_Pos     (14UL)         /*!< CENDFC (Bit 14)                                       */
+ #define R_SPI0_SPSRC_CENDFC_Msk     (0x4000UL)     /*!< CENDFC (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPSRC_SPRFC_Pos      (15UL)         /*!< SPRFC (Bit 15)                                        */
+ #define R_SPI0_SPSRC_SPRFC_Msk      (0x8000UL)     /*!< SPRFC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPFCR  ========================================================= */
+ #define R_SPI0_SPFCR_SPFRST_Pos     (0UL)          /*!< SPFRST (Bit 0)                                        */
+ #define R_SPI0_SPFCR_SPFRST_Msk     (0x1UL)        /*!< SPFRST (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CRC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CRCCR0  ========================================================= */
+ #define R_CRC0_CRCCR0_GPS_Pos       (0UL)    /*!< GPS (Bit 0)                                           */
+ #define R_CRC0_CRCCR0_GPS_Msk       (0x7UL)  /*!< GPS (Bitfield-Mask: 0x07)                             */
+ #define R_CRC0_CRCCR0_LMS_Pos       (6UL)    /*!< LMS (Bit 6)                                           */
+ #define R_CRC0_CRCCR0_LMS_Msk       (0x40UL) /*!< LMS (Bitfield-Mask: 0x01)                             */
+ #define R_CRC0_CRCCR0_DORCLR_Pos    (7UL)    /*!< DORCLR (Bit 7)                                        */
+ #define R_CRC0_CRCCR0_DORCLR_Msk    (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CRCDIR  ========================================================= */
+/* =======================================================  CRCDIR_BY  ======================================================= */
+/* ========================================================  CRCDOR  ========================================================= */
+/* =======================================================  CRCDOR_HA  ======================================================= */
+/* =======================================================  CRCDOR_BY  ======================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CANFD                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CFDGIPV  ======================================================== */
+ #define R_CANFD_CFDGIPV_IPV_Pos                 (0UL)          /*!< IPV (Bit 0)                                           */
+ #define R_CANFD_CFDGIPV_IPV_Msk                 (0xffUL)       /*!< IPV (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDGIPV_IPT_Pos                 (8UL)          /*!< IPT (Bit 8)                                           */
+ #define R_CANFD_CFDGIPV_IPT_Msk                 (0x300UL)      /*!< IPT (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDGIPV_PSI_Pos                 (16UL)         /*!< PSI (Bit 16)                                          */
+ #define R_CANFD_CFDGIPV_PSI_Msk                 (0x3fff0000UL) /*!< PSI (Bitfield-Mask: 0x3fff)                           */
+/* ========================================================  CFDGCFG  ======================================================== */
+ #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
+ #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
+ #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
+ #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
+ #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
+ #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
+ #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
+ #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
+ #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
+ #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCFG_TSBTCS_Pos              (13UL)         /*!< TSBTCS (Bit 13)                                       */
+ #define R_CANFD_CFDGCFG_TSBTCS_Msk              (0xe000UL)     /*!< TSBTCS (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
+ #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  CFDGCTR  ======================================================== */
+ #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
+ #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
+ #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
+ #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
+ #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
+ #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
+ #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGCTR_QOWEIE_Pos              (12UL)         /*!< QOWEIE (Bit 12)                                       */
+ #define R_CANFD_CFDGCTR_QOWEIE_Msk              (0x1000UL)     /*!< QOWEIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGCTR_QMEIE_Pos               (14UL)         /*!< QMEIE (Bit 14)                                        */
+ #define R_CANFD_CFDGCTR_QMEIE_Msk               (0x4000UL)     /*!< QMEIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCTR_MOWEIE_Pos              (15UL)         /*!< MOWEIE (Bit 15)                                       */
+ #define R_CANFD_CFDGCTR_MOWEIE_Msk              (0x8000UL)     /*!< MOWEIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
+ #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CFDGSTS  ======================================================== */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
+/* =======================================================  CFDGERFL  ======================================================== */
+ #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
+ #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
+ #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
+ #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
+ #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_QOWES_Pos              (4UL)          /*!< QOWES (Bit 4)                                         */
+ #define R_CANFD_CFDGERFL_QOWES_Msk              (0x10UL)       /*!< QOWES (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_QMES_Pos               (6UL)          /*!< QMES (Bit 6)                                          */
+ #define R_CANFD_CFDGERFL_QMES_Msk               (0x40UL)       /*!< QMES (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGERFL_MOWES_Pos              (7UL)          /*!< MOWES (Bit 7)                                         */
+ #define R_CANFD_CFDGERFL_MOWES_Msk              (0x80UL)       /*!< MOWES (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
+ #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGERFL_EEF1_Pos               (17UL)         /*!< EEF1 (Bit 17)                                         */
+ #define R_CANFD_CFDGERFL_EEF1_Msk               (0x20000UL)    /*!< EEF1 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CFDGTSC  ======================================================== */
+ #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
+ #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
+/* ======================================================  CFDGAFLECTR  ====================================================== */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDGAFLCFG0  ====================================================== */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  CFDRMNB  ======================================================== */
+ #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
+ #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
+ #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
+ #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
+/* =======================================================  CFDRMND0  ======================================================== */
+ #define R_CANFD_CFDRMND0_RMNS_Pos               (0UL)          /*!< RMNS (Bit 0)                                          */
+ #define R_CANFD_CFDRMND0_RMNS_Msk               (0xffffffffUL) /*!< RMNS (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  CFDRFCC  ======================================================== */
+ #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
+ #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
+ #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
+ #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
+ #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
+ #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
+ #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDRFCC_RFFIE_Pos               (16UL)         /*!< RFFIE (Bit 16)                                        */
+ #define R_CANFD_CFDRFCC_RFFIE_Msk               (0x10000UL)    /*!< RFFIE (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDRFSTS  ======================================================== */
+ #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
+ #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
+ #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
+ #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
+ #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
+ #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDRFSTS_RFFIF_Pos              (16UL)         /*!< RFFIF (Bit 16)                                        */
+ #define R_CANFD_CFDRFSTS_RFFIF_Msk              (0x10000UL)    /*!< RFFIF (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDRFPCTR  ======================================================= */
+ #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
+ #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
+/* ========================================================  CFDCFCC  ======================================================== */
+ #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
+ #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
+ #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
+ #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
+ #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
+ #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
+ #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
+ #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
+ #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
+ #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
+ #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
+ #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
+ #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDCFCCE  ======================================================== */
+ #define R_CANFD_CFDCFCCE_CFFIE_Pos              (0UL)          /*!< CFFIE (Bit 0)                                         */
+ #define R_CANFD_CFDCFCCE_CFFIE_Msk              (0x1UL)        /*!< CFFIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos           (1UL)          /*!< CFOFRXIE (Bit 1)                                      */
+ #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk           (0x2UL)        /*!< CFOFRXIE (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos           (2UL)          /*!< CFOFTXIE (Bit 2)                                      */
+ #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk           (0x4UL)        /*!< CFOFTXIE (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCFCCE_CFMOWM_Pos             (8UL)          /*!< CFMOWM (Bit 8)                                        */
+ #define R_CANFD_CFDCFCCE_CFMOWM_Msk             (0x100UL)      /*!< CFMOWM (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCCE_CFBME_Pos              (16UL)         /*!< CFBME (Bit 16)                                        */
+ #define R_CANFD_CFDCFCCE_CFBME_Msk              (0x10000UL)    /*!< CFBME (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDCFSTS  ======================================================== */
+ #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
+ #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
+ #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
+ #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
+ #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDCFSTS_CFFIF_Pos              (16UL)         /*!< CFFIF (Bit 16)                                        */
+ #define R_CANFD_CFDCFSTS_CFFIF_Msk              (0x10000UL)    /*!< CFFIF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos           (17UL)         /*!< CFOFRXIF (Bit 17)                                     */
+ #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk           (0x20000UL)    /*!< CFOFRXIF (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos           (18UL)         /*!< CFOFTXIF (Bit 18)                                     */
+ #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk           (0x40000UL)    /*!< CFOFTXIF (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCFSTS_CFMOW_Pos              (24UL)         /*!< CFMOW (Bit 24)                                        */
+ #define R_CANFD_CFDCFSTS_CFMOW_Msk              (0x1000000UL)  /*!< CFMOW (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDCFPCTR  ======================================================= */
+ #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
+ #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
+/* =======================================================  CFDFESTS  ======================================================== */
+ #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
+ #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0xffUL)       /*!< RFXEMP (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
+ #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x3f00UL)     /*!< CFXEMP (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CFDFFSTS  ======================================================== */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0xffUL)       /*!< RFXFLL (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x3f00UL)     /*!< CFXFLL (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CFDFMSTS  ======================================================== */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0xffUL)       /*!< RFXMLT (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x3f00UL)     /*!< CFXMLT (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CFDRFISTS  ======================================================= */
+ #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
+ #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0xffUL)       /*!< RFXIF (Bitfield-Mask: 0xff)                           */
+ #define R_CANFD_CFDRFISTS_RFXFFLL_Pos           (16UL)         /*!< RFXFFLL (Bit 16)                                      */
+ #define R_CANFD_CFDRFISTS_RFXFFLL_Msk           (0xff0000UL)   /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
+/* ======================================================  CFDCFRISTS  ======================================================= */
+ #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos          (0UL)          /*!< CFXRXIF (Bit 0)                                       */
+ #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk          (0x3fUL)       /*!< CFXRXIF (Bitfield-Mask: 0x3f)                         */
+/* ======================================================  CFDCFTISTS  ======================================================= */
+ #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos          (0UL)          /*!< CFXTXIF (Bit 0)                                       */
+ #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk          (0x3fUL)       /*!< CFXTXIF (Bitfield-Mask: 0x3f)                         */
+/* =====================================================  CFDCFOFRISTS  ====================================================== */
+ #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos      (0UL)          /*!< CFXOFRXIF (Bit 0)                                     */
+ #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk      (0x3fUL)       /*!< CFXOFRXIF (Bitfield-Mask: 0x3f)                       */
+/* =====================================================  CFDCFOFTISTS  ====================================================== */
+ #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos      (0UL)          /*!< CFXOFTXIF (Bit 0)                                     */
+ #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk      (0x3fUL)       /*!< CFXOFTXIF (Bitfield-Mask: 0x3f)                       */
+/* ======================================================  CFDCFMOWSTS  ====================================================== */
+ #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos          (0UL)          /*!< CFXMOW (Bit 0)                                        */
+ #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk          (0x3fUL)       /*!< CFXMOW (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CFDFFFSTS  ======================================================= */
+ #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos           (0UL)          /*!< RFXFFLL (Bit 0)                                       */
+ #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk           (0xffUL)       /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos           (8UL)          /*!< CFXFFLL (Bit 8)                                       */
+ #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk           (0x3f00UL)     /*!< CFXFFLL (Bitfield-Mask: 0x3f)                         */
+/* ========================================================  CFDTMC  ========================================================= */
+ #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
+ #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
+ #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
+ #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFDTMSTS  ======================================================== */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
+ #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
+ #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
+ #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTMTRSTS  ======================================================= */
+ #define R_CANFD_CFDTMTRSTS_TMTRSTS_Pos          (0UL)          /*!< TMTRSTS (Bit 0)                                       */
+ #define R_CANFD_CFDTMTRSTS_TMTRSTS_Msk          (0xffffUL)     /*!< TMTRSTS (Bitfield-Mask: 0xffff)                       */
+/* ======================================================  CFDTMTARSTS  ====================================================== */
+ #define R_CANFD_CFDTMTARSTS_TMTARSTS_Pos        (0UL)          /*!< TMTARSTS (Bit 0)                                      */
+ #define R_CANFD_CFDTMTARSTS_TMTARSTS_Msk        (0xffffUL)     /*!< TMTARSTS (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  CFDTMTCSTS  ======================================================= */
+ #define R_CANFD_CFDTMTCSTS_TMTCSTS_Pos          (0UL)          /*!< TMTCSTS (Bit 0)                                       */
+ #define R_CANFD_CFDTMTCSTS_TMTCSTS_Msk          (0xffffUL)     /*!< TMTCSTS (Bitfield-Mask: 0xffff)                       */
+/* ======================================================  CFDTMTASTS  ======================================================= */
+ #define R_CANFD_CFDTMTASTS_TMTASTS_Pos          (0UL)          /*!< TMTASTS (Bit 0)                                       */
+ #define R_CANFD_CFDTMTASTS_TMTASTS_Msk          (0xffffUL)     /*!< TMTASTS (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  CFDTMIEC  ======================================================== */
+ #define R_CANFD_CFDTMIEC_TMIE_Pos               (0UL)          /*!< TMIE (Bit 0)                                          */
+ #define R_CANFD_CFDTMIEC_TMIE_Msk               (0xffffUL)     /*!< TMIE (Bitfield-Mask: 0xffff)                          */
+/* =======================================================  CFDTXQCC0  ======================================================= */
+ #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC0_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
+ #define R_CANFD_CFDTXQCC0_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC0_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
+ #define R_CANFD_CFDTXQCC0_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDTXQCC0_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
+ #define R_CANFD_CFDTXQCC0_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
+ #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
+ #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDTXQSTS0  ======================================================= */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+ #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
+ #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
+ #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTXQPCTR0  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDTXQCC1  ======================================================= */
+ #define R_CANFD_CFDTXQCC1_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC1_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC1_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
+ #define R_CANFD_CFDTXQCC1_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC1_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
+ #define R_CANFD_CFDTXQCC1_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC1_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC1_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC1_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC1_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDTXQCC1_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
+ #define R_CANFD_CFDTXQCC1_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
+ #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
+ #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDTXQSTS1  ======================================================= */
+ #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS1_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS1_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+ #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
+ #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
+ #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
+ #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
+ #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS1_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
+ #define R_CANFD_CFDTXQSTS1_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTXQPCTR1  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDTXQCC2  ======================================================= */
+ #define R_CANFD_CFDTXQCC2_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC2_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC2_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
+ #define R_CANFD_CFDTXQCC2_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC2_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
+ #define R_CANFD_CFDTXQCC2_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC2_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC2_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC2_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC2_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDTXQCC2_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
+ #define R_CANFD_CFDTXQCC2_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
+ #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
+ #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDTXQSTS2  ======================================================= */
+ #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS2_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS2_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+ #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
+ #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
+ #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
+ #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
+ #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS2_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
+ #define R_CANFD_CFDTXQSTS2_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTXQPCTR2  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDTXQCC3  ======================================================= */
+ #define R_CANFD_CFDTXQCC3_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC3_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC3_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
+ #define R_CANFD_CFDTXQCC3_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC3_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC3_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC3_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC3_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
+ #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDTXQSTS3  ======================================================= */
+ #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS3_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS3_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+ #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
+ #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS3_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
+ #define R_CANFD_CFDTXQSTS3_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTXQPCTR3  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* ======================================================  CFDTXQESTS  ======================================================= */
+ #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos          (0UL)          /*!< TXQxEMP (Bit 0)                                       */
+ #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk          (0xffUL)       /*!< TXQxEMP (Bitfield-Mask: 0xff)                         */
+/* ======================================================  CFDTXQFISTS  ====================================================== */
+ #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos        (0UL)          /*!< TXQ0FULL (Bit 0)                                      */
+ #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk        (0x7UL)        /*!< TXQ0FULL (Bitfield-Mask: 0x07)                        */
+ #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos        (4UL)          /*!< TXQ1FULL (Bit 4)                                      */
+ #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk        (0x70UL)       /*!< TXQ1FULL (Bitfield-Mask: 0x07)                        */
+/* ======================================================  CFDTXQMSTS  ======================================================= */
+ #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos           (0UL)          /*!< TXQ0ML (Bit 0)                                        */
+ #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk           (0x7UL)        /*!< TXQ0ML (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos           (4UL)          /*!< TXQ1ML (Bit 4)                                        */
+ #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk           (0x70UL)       /*!< TXQ1ML (Bitfield-Mask: 0x07)                          */
+/* ======================================================  CFDTXQISTS  ======================================================= */
+ #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos          (0UL)          /*!< TXQ0ISF (Bit 0)                                       */
+ #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk          (0xfUL)        /*!< TXQ0ISF (Bitfield-Mask: 0x0f)                         */
+ #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos          (4UL)          /*!< TXQ1ISF (Bit 4)                                       */
+ #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk          (0xf0UL)       /*!< TXQ1ISF (Bitfield-Mask: 0x0f)                         */
+/* =====================================================  CFDTXQOFTISTS  ===================================================== */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos    (0UL)          /*!< TXQ0OFTISF (Bit 0)                                    */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk    (0xfUL)        /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f)                      */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos    (4UL)          /*!< TXQ1OFTISF (Bit 4)                                    */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk    (0xf0UL)       /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  CFDTXQOFRISTS  ===================================================== */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos    (0UL)          /*!< TXQ0OFRISF (Bit 0)                                    */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk    (0x7UL)        /*!< TXQ0OFRISF (Bitfield-Mask: 0x07)                      */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos    (4UL)          /*!< TXQ1OFRISF (Bit 4)                                    */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk    (0x70UL)       /*!< TXQ1OFRISF (Bitfield-Mask: 0x07)                      */
+/* ======================================================  CFDTXQFSTS  ======================================================= */
+ #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos          (0UL)          /*!< TXQ0FSF (Bit 0)                                       */
+ #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk          (0xfUL)        /*!< TXQ0FSF (Bitfield-Mask: 0x0f)                         */
+ #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos          (4UL)          /*!< TXQ1FSF (Bit 4)                                       */
+ #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk          (0xf0UL)       /*!< TXQ1FSF (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  CFDTHLCC  ======================================================== */
+ #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
+ #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
+ #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
+ #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
+ #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLCC_THLDGE_Pos             (11UL)         /*!< THLDGE (Bit 11)                                       */
+ #define R_CANFD_CFDTHLCC_THLDGE_Msk             (0x800UL)      /*!< THLDGE (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDTHLSTS  ======================================================= */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
+ #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
+ #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
+ #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
+/* ======================================================  CFDTHLPCTR  ======================================================= */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
+/* =====================================================  CFDGTINTSTS0  ====================================================== */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos        (5UL)          /*!< TQOFIF0 (Bit 5)                                       */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk        (0x20UL)       /*!< TQOFIF0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos        (6UL)          /*!< CFOTIF0 (Bit 6)                                       */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk        (0x40UL)       /*!< CFOTIF0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos          (8UL)          /*!< TSIF1 (Bit 8)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk          (0x100UL)      /*!< TSIF1 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos          (9UL)          /*!< TAIF1 (Bit 9)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk          (0x200UL)      /*!< TAIF1 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos          (10UL)         /*!< TQIF1 (Bit 10)                                        */
+ #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk          (0x400UL)      /*!< TQIF1 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos         (11UL)         /*!< CFTIF1 (Bit 11)                                       */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk         (0x800UL)      /*!< CFTIF1 (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGTINTSTS0_THIF1_Pos          (12UL)         /*!< THIF1 (Bit 12)                                        */
+ #define R_CANFD_CFDGTINTSTS0_THIF1_Msk          (0x1000UL)     /*!< THIF1 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos        (13UL)         /*!< TQOFIF1 (Bit 13)                                      */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk        (0x2000UL)     /*!< TQOFIF1 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos        (14UL)         /*!< CFOTIF1 (Bit 14)                                      */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk        (0x4000UL)     /*!< CFOTIF1 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  CFDGTSTCFG  ======================================================= */
+ #define R_CANFD_CFDGTSTCFG_C0ICBCE_Pos          (0UL)          /*!< C0ICBCE (Bit 0)                                       */
+ #define R_CANFD_CFDGTSTCFG_C0ICBCE_Msk          (0x1UL)        /*!< C0ICBCE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTSTCFG_C1ICBCE_Pos          (1UL)          /*!< C1ICBCE (Bit 1)                                       */
+ #define R_CANFD_CFDGTSTCFG_C1ICBCE_Msk          (0x2UL)        /*!< C1ICBCE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
+/* ======================================================  CFDGTSTCTR  ======================================================= */
+ #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos          (0UL)          /*!< ICBCTME (Bit 0)                                       */
+ #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk          (0x1UL)        /*!< ICBCTME (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
+ #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFDGFDCFG  ======================================================= */
+ #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
+ #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
+/* =======================================================  CFDGLOCKK  ======================================================= */
+ #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
+ #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
+/* =======================================================  CFDCDTCT  ======================================================== */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE2_Pos            (2UL)          /*!< RFDMAE2 (Bit 2)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE2_Msk            (0x4UL)        /*!< RFDMAE2 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE3_Pos            (3UL)          /*!< RFDMAE3 (Bit 3)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE3_Msk            (0x8UL)        /*!< RFDMAE3 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE4_Pos            (4UL)          /*!< RFDMAE4 (Bit 4)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE4_Msk            (0x10UL)       /*!< RFDMAE4 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE5_Pos            (5UL)          /*!< RFDMAE5 (Bit 5)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE5_Msk            (0x20UL)       /*!< RFDMAE5 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE6_Pos            (6UL)          /*!< RFDMAE6 (Bit 6)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE6_Msk            (0x40UL)       /*!< RFDMAE6 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE7_Pos            (7UL)          /*!< RFDMAE7 (Bit 7)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE7_Msk            (0x80UL)       /*!< RFDMAE7 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_CFDMAE1_Pos            (9UL)          /*!< CFDMAE1 (Bit 9)                                       */
+ #define R_CANFD_CFDCDTCT_CFDMAE1_Msk            (0x200UL)      /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  CFDCDTSTS  ======================================================= */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos         (2UL)          /*!< RFDMASTS2 (Bit 2)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk         (0x4UL)        /*!< RFDMASTS2 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos         (3UL)          /*!< RFDMASTS3 (Bit 3)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk         (0x8UL)        /*!< RFDMASTS3 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos         (4UL)          /*!< RFDMASTS4 (Bit 4)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk         (0x10UL)       /*!< RFDMASTS4 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos         (5UL)          /*!< RFDMASTS5 (Bit 5)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk         (0x20UL)       /*!< RFDMASTS5 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos         (6UL)          /*!< RFDMASTS6 (Bit 6)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk         (0x40UL)       /*!< RFDMASTS6 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos         (7UL)          /*!< RFDMASTS7 (Bit 7)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk         (0x80UL)       /*!< RFDMASTS7 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos         (9UL)          /*!< CFDMASTS1 (Bit 9)                                     */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk         (0x200UL)      /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  CFDCDTTCT  ======================================================= */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos          (0UL)          /*!< TQ0DMAE0 (Bit 0)                                      */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk          (0x1UL)        /*!< TQ0DMAE0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos          (1UL)          /*!< TQ0DMAE1 (Bit 1)                                      */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk          (0x2UL)        /*!< TQ0DMAE1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos          (8UL)          /*!< TQ3DMAE0 (Bit 8)                                      */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk          (0x100UL)      /*!< TQ3DMAE0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos          (9UL)          /*!< TQ3DMAE1 (Bit 9)                                      */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk          (0x200UL)      /*!< TQ3DMAE1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos           (16UL)         /*!< CFDMAE0 (Bit 16)                                      */
+ #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk           (0x10000UL)    /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos           (17UL)         /*!< CFDMAE1 (Bit 17)                                      */
+ #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk           (0x20000UL)    /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  CFDCDTTSTS  ======================================================= */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos       (0UL)          /*!< TQ0DMASTS0 (Bit 0)                                    */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk       (0x1UL)        /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01)                      */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos       (1UL)          /*!< TQ0DMASTS1 (Bit 1)                                    */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk       (0x2UL)        /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01)                      */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos       (8UL)          /*!< TQ3DMASTS0 (Bit 8)                                    */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk       (0x100UL)      /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01)                      */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos       (9UL)          /*!< TQ3DMASTS1 (Bit 9)                                    */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk       (0x200UL)      /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01)                      */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos        (16UL)         /*!< CFDMASTS0 (Bit 16)                                    */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk        (0x10000UL)    /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos        (17UL)         /*!< CFDMASTS1 (Bit 17)                                    */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk        (0x20000UL)    /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDGRINTSTS  ====================================================== */
+ #define R_CANFD_CFDGRINTSTS_QFIF_Pos            (0UL)          /*!< QFIF (Bit 0)                                          */
+ #define R_CANFD_CFDGRINTSTS_QFIF_Msk            (0x7UL)        /*!< QFIF (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDGRINTSTS_BQFIF_Pos           (4UL)          /*!< BQFIF (Bit 4)                                         */
+ #define R_CANFD_CFDGRINTSTS_BQFIF_Msk           (0x30UL)       /*!< BQFIF (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos          (8UL)          /*!< QOFRIF (Bit 8)                                        */
+ #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk          (0x700UL)      /*!< QOFRIF (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDGRINTSTS_BQOFRIF_Pos         (12UL)         /*!< BQOFRIF (Bit 12)                                      */
+ #define R_CANFD_CFDGRINTSTS_BQOFRIF_Msk         (0x3000UL)     /*!< BQOFRIF (Bitfield-Mask: 0x03)                         */
+ #define R_CANFD_CFDGRINTSTS_CFRIF_Pos           (16UL)         /*!< CFRIF (Bit 16)                                        */
+ #define R_CANFD_CFDGRINTSTS_CFRIF_Msk           (0x70000UL)    /*!< CFRIF (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos          (24UL)         /*!< CFRFIF (Bit 24)                                       */
+ #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk          (0x7000000UL)  /*!< CFRFIF (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos         (28UL)         /*!< CFOFRIF (Bit 28)                                      */
+ #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk         (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07)                         */
+/* =======================================================  CFDGRSTC  ======================================================== */
+ #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
+ #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* =======================================================  CFDGFCMC  ======================================================== */
+ #define R_CANFD_CFDGFCMC_FLXC0_Pos              (0UL)          /*!< FLXC0 (Bit 0)                                         */
+ #define R_CANFD_CFDGFCMC_FLXC0_Msk              (0x1UL)        /*!< FLXC0 (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDGFTBAC  ======================================================= */
+ #define R_CANFD_CFDGFTBAC_FLXMB0_Pos            (0UL)          /*!< FLXMB0 (Bit 0)                                        */
+ #define R_CANFD_CFDGFTBAC_FLXMB0_Msk            (0xfUL)        /*!< FLXMB0 (Bitfield-Mask: 0x0f)                          */
+/* =======================================================  CFDRPGACC  ======================================================= */
+ #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
+ #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CMT                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CMTW0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CMWSTR  ========================================================= */
+ #define R_CMTW0_CMWSTR_STR_Pos     (0UL)      /*!< STR (Bit 0)                                           */
+ #define R_CMTW0_CMWSTR_STR_Msk     (0x1UL)    /*!< STR (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CMWCR  ========================================================= */
+ #define R_CMTW0_CMWCR_CKS_Pos      (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_CMTW0_CMWCR_CKS_Msk      (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWCR_CMWIE_Pos    (3UL)      /*!< CMWIE (Bit 3)                                         */
+ #define R_CMTW0_CMWCR_CMWIE_Msk    (0x8UL)    /*!< CMWIE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_IC0IE_Pos    (4UL)      /*!< IC0IE (Bit 4)                                         */
+ #define R_CMTW0_CMWCR_IC0IE_Msk    (0x10UL)   /*!< IC0IE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_IC1IE_Pos    (5UL)      /*!< IC1IE (Bit 5)                                         */
+ #define R_CMTW0_CMWCR_IC1IE_Msk    (0x20UL)   /*!< IC1IE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_OC0IE_Pos    (6UL)      /*!< OC0IE (Bit 6)                                         */
+ #define R_CMTW0_CMWCR_OC0IE_Msk    (0x40UL)   /*!< OC0IE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_OC1IE_Pos    (7UL)      /*!< OC1IE (Bit 7)                                         */
+ #define R_CMTW0_CMWCR_OC1IE_Msk    (0x80UL)   /*!< OC1IE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_CMS_Pos      (9UL)      /*!< CMS (Bit 9)                                           */
+ #define R_CMTW0_CMWCR_CMS_Msk      (0x200UL)  /*!< CMS (Bitfield-Mask: 0x01)                             */
+ #define R_CMTW0_CMWCR_CCLR_Pos     (13UL)     /*!< CCLR (Bit 13)                                         */
+ #define R_CMTW0_CMWCR_CCLR_Msk     (0xe000UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* ========================================================  CMWIOR  ========================================================= */
+ #define R_CMTW0_CMWIOR_IC0_Pos     (0UL)      /*!< IC0 (Bit 0)                                           */
+ #define R_CMTW0_CMWIOR_IC0_Msk     (0x3UL)    /*!< IC0 (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWIOR_IC1_Pos     (2UL)      /*!< IC1 (Bit 2)                                           */
+ #define R_CMTW0_CMWIOR_IC1_Msk     (0xcUL)    /*!< IC1 (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWIOR_IC0E_Pos    (4UL)      /*!< IC0E (Bit 4)                                          */
+ #define R_CMTW0_CMWIOR_IC0E_Msk    (0x10UL)   /*!< IC0E (Bitfield-Mask: 0x01)                            */
+ #define R_CMTW0_CMWIOR_IC1E_Pos    (5UL)      /*!< IC1E (Bit 5)                                          */
+ #define R_CMTW0_CMWIOR_IC1E_Msk    (0x20UL)   /*!< IC1E (Bitfield-Mask: 0x01)                            */
+ #define R_CMTW0_CMWIOR_OC0_Pos     (8UL)      /*!< OC0 (Bit 8)                                           */
+ #define R_CMTW0_CMWIOR_OC0_Msk     (0x300UL)  /*!< OC0 (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWIOR_OC1_Pos     (10UL)     /*!< OC1 (Bit 10)                                          */
+ #define R_CMTW0_CMWIOR_OC1_Msk     (0xc00UL)  /*!< OC1 (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWIOR_OC0E_Pos    (12UL)     /*!< OC0E (Bit 12)                                         */
+ #define R_CMTW0_CMWIOR_OC0E_Msk    (0x1000UL) /*!< OC0E (Bitfield-Mask: 0x01)                            */
+ #define R_CMTW0_CMWIOR_OC1E_Pos    (13UL)     /*!< OC1E (Bit 13)                                         */
+ #define R_CMTW0_CMWIOR_OC1E_Msk    (0x2000UL) /*!< OC1E (Bitfield-Mask: 0x01)                            */
+ #define R_CMTW0_CMWIOR_CMWE_Pos    (15UL)     /*!< CMWE (Bit 15)                                         */
+ #define R_CMTW0_CMWIOR_CMWE_Msk    (0x8000UL) /*!< CMWE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CMWCNT  ========================================================= */
+/* ========================================================  CMWCOR  ========================================================= */
+/* ========================================================  CMWICR0  ======================================================== */
+/* ========================================================  CMWICR1  ======================================================== */
+/* ========================================================  CMWOCR0  ======================================================== */
+/* ========================================================  CMWOCR1  ======================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_WDT0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  WDTRR  ========================================================= */
+/* =========================================================  WDTCR  ========================================================= */
+ #define R_WDT0_WDTCR_TOPS_Pos        (0UL)      /*!< TOPS (Bit 0)                                          */
+ #define R_WDT0_WDTCR_TOPS_Msk        (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
+ #define R_WDT0_WDTCR_CKS_Pos         (4UL)      /*!< CKS (Bit 4)                                           */
+ #define R_WDT0_WDTCR_CKS_Msk         (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
+ #define R_WDT0_WDTCR_RPES_Pos        (8UL)      /*!< RPES (Bit 8)                                          */
+ #define R_WDT0_WDTCR_RPES_Msk        (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
+ #define R_WDT0_WDTCR_RPSS_Pos        (12UL)     /*!< RPSS (Bit 12)                                         */
+ #define R_WDT0_WDTCR_RPSS_Msk        (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  WDTSR  ========================================================= */
+ #define R_WDT0_WDTSR_CNTVAL_Pos      (0UL)      /*!< CNTVAL (Bit 0)                                        */
+ #define R_WDT0_WDTSR_CNTVAL_Msk      (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
+ #define R_WDT0_WDTSR_UNDFF_Pos       (14UL)     /*!< UNDFF (Bit 14)                                        */
+ #define R_WDT0_WDTSR_UNDFF_Msk       (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
+ #define R_WDT0_WDTSR_REFEF_Pos       (15UL)     /*!< REFEF (Bit 15)                                        */
+ #define R_WDT0_WDTSR_REFEF_Msk       (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  WDTRCR  ========================================================= */
+ #define R_WDT0_WDTRCR_RSTIRQS_Pos    (7UL)      /*!< RSTIRQS (Bit 7)                                       */
+ #define R_WDT0_WDTRCR_RSTIRQS_Msk    (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ICCR1  ========================================================= */
+ #define R_IIC0_ICCR1_SDAI_Pos      (0UL)    /*!< SDAI (Bit 0)                                          */
+ #define R_IIC0_ICCR1_SDAI_Msk      (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLI_Pos      (1UL)    /*!< SCLI (Bit 1)                                          */
+ #define R_IIC0_ICCR1_SCLI_Msk      (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SDAO_Pos      (2UL)    /*!< SDAO (Bit 2)                                          */
+ #define R_IIC0_ICCR1_SDAO_Msk      (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLO_Pos      (3UL)    /*!< SCLO (Bit 3)                                          */
+ #define R_IIC0_ICCR1_SCLO_Msk      (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SOWP_Pos      (4UL)    /*!< SOWP (Bit 4)                                          */
+ #define R_IIC0_ICCR1_SOWP_Msk      (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_CLO_Pos       (5UL)    /*!< CLO (Bit 5)                                           */
+ #define R_IIC0_ICCR1_CLO_Msk       (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR1_IICRST_Pos    (6UL)    /*!< IICRST (Bit 6)                                        */
+ #define R_IIC0_ICCR1_IICRST_Msk    (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
+ #define R_IIC0_ICCR1_ICE_Pos       (7UL)    /*!< ICE (Bit 7)                                           */
+ #define R_IIC0_ICCR1_ICE_Msk       (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ICCR2  ========================================================= */
+ #define R_IIC0_ICCR2_ST_Pos        (1UL)    /*!< ST (Bit 1)                                            */
+ #define R_IIC0_ICCR2_ST_Msk        (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_RS_Pos        (2UL)    /*!< RS (Bit 2)                                            */
+ #define R_IIC0_ICCR2_RS_Msk        (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_SP_Pos        (3UL)    /*!< SP (Bit 3)                                            */
+ #define R_IIC0_ICCR2_SP_Msk        (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_TRS_Pos       (5UL)    /*!< TRS (Bit 5)                                           */
+ #define R_IIC0_ICCR2_TRS_Msk       (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_MST_Pos       (6UL)    /*!< MST (Bit 6)                                           */
+ #define R_IIC0_ICCR2_MST_Msk       (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_BBSY_Pos      (7UL)    /*!< BBSY (Bit 7)                                          */
+ #define R_IIC0_ICCR2_BBSY_Msk      (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR1  ========================================================= */
+ #define R_IIC0_ICMR1_BC_Pos        (0UL)    /*!< BC (Bit 0)                                            */
+ #define R_IIC0_ICMR1_BC_Msk        (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
+ #define R_IIC0_ICMR1_BCWP_Pos      (3UL)    /*!< BCWP (Bit 3)                                          */
+ #define R_IIC0_ICMR1_BCWP_Msk      (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR1_CKS_Pos       (4UL)    /*!< CKS (Bit 4)                                           */
+ #define R_IIC0_ICMR1_CKS_Msk       (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
+ #define R_IIC0_ICMR1_MTWP_Pos      (7UL)    /*!< MTWP (Bit 7)                                          */
+ #define R_IIC0_ICMR1_MTWP_Msk      (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR2  ========================================================= */
+ #define R_IIC0_ICMR2_TMOS_Pos      (0UL)    /*!< TMOS (Bit 0)                                          */
+ #define R_IIC0_ICMR2_TMOS_Msk      (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOL_Pos      (1UL)    /*!< TMOL (Bit 1)                                          */
+ #define R_IIC0_ICMR2_TMOL_Msk      (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOH_Pos      (2UL)    /*!< TMOH (Bit 2)                                          */
+ #define R_IIC0_ICMR2_TMOH_Msk      (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_SDDL_Pos      (4UL)    /*!< SDDL (Bit 4)                                          */
+ #define R_IIC0_ICMR2_SDDL_Msk      (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
+ #define R_IIC0_ICMR2_DLCS_Pos      (7UL)    /*!< DLCS (Bit 7)                                          */
+ #define R_IIC0_ICMR2_DLCS_Msk      (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR3  ========================================================= */
+ #define R_IIC0_ICMR3_NF_Pos        (0UL)    /*!< NF (Bit 0)                                            */
+ #define R_IIC0_ICMR3_NF_Msk        (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
+ #define R_IIC0_ICMR3_ACKBR_Pos     (2UL)    /*!< ACKBR (Bit 2)                                         */
+ #define R_IIC0_ICMR3_ACKBR_Msk     (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKBT_Pos     (3UL)    /*!< ACKBT (Bit 3)                                         */
+ #define R_IIC0_ICMR3_ACKBT_Msk     (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKWP_Pos     (4UL)    /*!< ACKWP (Bit 4)                                         */
+ #define R_IIC0_ICMR3_ACKWP_Msk     (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_RDRFS_Pos     (5UL)    /*!< RDRFS (Bit 5)                                         */
+ #define R_IIC0_ICMR3_RDRFS_Msk     (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_WAIT_Pos      (6UL)    /*!< WAIT (Bit 6)                                          */
+ #define R_IIC0_ICMR3_WAIT_Msk      (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR3_SMBS_Pos      (7UL)    /*!< SMBS (Bit 7)                                          */
+ #define R_IIC0_ICMR3_SMBS_Msk      (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICFER  ========================================================= */
+ #define R_IIC0_ICFER_TMOE_Pos      (0UL)    /*!< TMOE (Bit 0)                                          */
+ #define R_IIC0_ICFER_TMOE_Msk      (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_MALE_Pos      (1UL)    /*!< MALE (Bit 1)                                          */
+ #define R_IIC0_ICFER_MALE_Msk      (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NALE_Pos      (2UL)    /*!< NALE (Bit 2)                                          */
+ #define R_IIC0_ICFER_NALE_Msk      (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_SALE_Pos      (3UL)    /*!< SALE (Bit 3)                                          */
+ #define R_IIC0_ICFER_SALE_Msk      (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NACKE_Pos     (4UL)    /*!< NACKE (Bit 4)                                         */
+ #define R_IIC0_ICFER_NACKE_Msk     (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICFER_NFE_Pos       (5UL)    /*!< NFE (Bit 5)                                           */
+ #define R_IIC0_ICFER_NFE_Msk       (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICFER_SCLE_Pos      (6UL)    /*!< SCLE (Bit 6)                                          */
+ #define R_IIC0_ICFER_SCLE_Msk      (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSER  ========================================================= */
+ #define R_IIC0_ICSER_SAR0E_Pos     (0UL)    /*!< SAR0E (Bit 0)                                         */
+ #define R_IIC0_ICSER_SAR0E_Msk     (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR1E_Pos     (1UL)    /*!< SAR1E (Bit 1)                                         */
+ #define R_IIC0_ICSER_SAR1E_Msk     (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR2E_Pos     (2UL)    /*!< SAR2E (Bit 2)                                         */
+ #define R_IIC0_ICSER_SAR2E_Msk     (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_GCAE_Pos      (3UL)    /*!< GCAE (Bit 3)                                          */
+ #define R_IIC0_ICSER_GCAE_Msk      (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_DIDE_Pos      (5UL)    /*!< DIDE (Bit 5)                                          */
+ #define R_IIC0_ICSER_DIDE_Msk      (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_HOAE_Pos      (7UL)    /*!< HOAE (Bit 7)                                          */
+ #define R_IIC0_ICSER_HOAE_Msk      (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICIER  ========================================================= */
+ #define R_IIC0_ICIER_TMOIE_Pos     (0UL)    /*!< TMOIE (Bit 0)                                         */
+ #define R_IIC0_ICIER_TMOIE_Msk     (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICIER_ALIE_Pos      (1UL)    /*!< ALIE (Bit 1)                                          */
+ #define R_IIC0_ICIER_ALIE_Msk      (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_STIE_Pos      (2UL)    /*!< STIE (Bit 2)                                          */
+ #define R_IIC0_ICIER_STIE_Msk      (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_SPIE_Pos      (3UL)    /*!< SPIE (Bit 3)                                          */
+ #define R_IIC0_ICIER_SPIE_Msk      (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_NAKIE_Pos     (4UL)    /*!< NAKIE (Bit 4)                                         */
+ #define R_IIC0_ICIER_NAKIE_Msk     (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICIER_RIE_Pos       (5UL)    /*!< RIE (Bit 5)                                           */
+ #define R_IIC0_ICIER_RIE_Msk       (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICIER_TEIE_Pos      (6UL)    /*!< TEIE (Bit 6)                                          */
+ #define R_IIC0_ICIER_TEIE_Msk      (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_TIE_Pos       (7UL)    /*!< TIE (Bit 7)                                           */
+ #define R_IIC0_ICIER_TIE_Msk       (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ICSR1  ========================================================= */
+ #define R_IIC0_ICSR1_AAS0_Pos      (0UL)    /*!< AAS0 (Bit 0)                                          */
+ #define R_IIC0_ICSR1_AAS0_Msk      (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS1_Pos      (1UL)    /*!< AAS1 (Bit 1)                                          */
+ #define R_IIC0_ICSR1_AAS1_Msk      (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS2_Pos      (2UL)    /*!< AAS2 (Bit 2)                                          */
+ #define R_IIC0_ICSR1_AAS2_Msk      (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_GCA_Pos       (3UL)    /*!< GCA (Bit 3)                                           */
+ #define R_IIC0_ICSR1_GCA_Msk       (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_DID_Pos       (5UL)    /*!< DID (Bit 5)                                           */
+ #define R_IIC0_ICSR1_DID_Msk       (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_HOA_Pos       (7UL)    /*!< HOA (Bit 7)                                           */
+ #define R_IIC0_ICSR1_HOA_Msk       (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ICSR2  ========================================================= */
+ #define R_IIC0_ICSR2_TMOF_Pos      (0UL)    /*!< TMOF (Bit 0)                                          */
+ #define R_IIC0_ICSR2_TMOF_Msk      (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_AL_Pos        (1UL)    /*!< AL (Bit 1)                                            */
+ #define R_IIC0_ICSR2_AL_Msk        (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICSR2_START_Pos     (2UL)    /*!< START (Bit 2)                                         */
+ #define R_IIC0_ICSR2_START_Msk     (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_STOP_Pos      (3UL)    /*!< STOP (Bit 3)                                          */
+ #define R_IIC0_ICSR2_STOP_Msk      (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_NACKF_Pos     (4UL)    /*!< NACKF (Bit 4)                                         */
+ #define R_IIC0_ICSR2_NACKF_Msk     (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_RDRF_Pos      (5UL)    /*!< RDRF (Bit 5)                                          */
+ #define R_IIC0_ICSR2_RDRF_Msk      (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_TEND_Pos      (6UL)    /*!< TEND (Bit 6)                                          */
+ #define R_IIC0_ICSR2_TEND_Msk      (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_TDRE_Pos      (7UL)    /*!< TDRE (Bit 7)                                          */
+ #define R_IIC0_ICSR2_TDRE_Msk      (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICBRL  ========================================================= */
+ #define R_IIC0_ICBRL_BRL_Pos       (0UL)    /*!< BRL (Bit 0)                                           */
+ #define R_IIC0_ICBRL_BRL_Msk       (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICBRH  ========================================================= */
+ #define R_IIC0_ICBRH_BRH_Pos       (0UL)    /*!< BRH (Bit 0)                                           */
+ #define R_IIC0_ICBRH_BRH_Msk       (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICDRT  ========================================================= */
+/* =========================================================  ICDRR  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DOCR  ========================================================== */
+ #define R_DOC_DOCR_OMS_Pos        (0UL)    /*!< OMS (Bit 0)                                           */
+ #define R_DOC_DOCR_OMS_Msk        (0x3UL)  /*!< OMS (Bitfield-Mask: 0x03)                             */
+ #define R_DOC_DOCR_DCSEL_Pos      (2UL)    /*!< DCSEL (Bit 2)                                         */
+ #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)  /*!< DCSEL (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_DOPCIE_Pos     (4UL)    /*!< DOPCIE (Bit 4)                                        */
+ #define R_DOC_DOCR_DOPCIE_Msk     (0x10UL) /*!< DOPCIE (Bitfield-Mask: 0x01)                          */
+ #define R_DOC_DOCR_DOPCF_Pos      (5UL)    /*!< DOPCF (Bit 5)                                         */
+ #define R_DOC_DOCR_DOPCF_Msk      (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)    /*!< DOPCFCL (Bit 6)                                       */
+ #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
+/* =========================================================  DODIR  ========================================================= */
+/* =========================================================  DODSR  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ADC121                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ADCSR  ========================================================= */
+ #define R_ADC121_ADCSR_DBLANS_Pos          (0UL)      /*!< DBLANS (Bit 0)                                        */
+ #define R_ADC121_ADCSR_DBLANS_Msk          (0x1fUL)   /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
+ #define R_ADC121_ADCSR_GBADIE_Pos          (6UL)      /*!< GBADIE (Bit 6)                                        */
+ #define R_ADC121_ADCSR_GBADIE_Msk          (0x40UL)   /*!< GBADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC121_ADCSR_DBLE_Pos            (7UL)      /*!< DBLE (Bit 7)                                          */
+ #define R_ADC121_ADCSR_DBLE_Msk            (0x80UL)   /*!< DBLE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC121_ADCSR_EXTRG_Pos           (8UL)      /*!< EXTRG (Bit 8)                                         */
+ #define R_ADC121_ADCSR_EXTRG_Msk           (0x100UL)  /*!< EXTRG (Bitfield-Mask: 0x01)                           */
+ #define R_ADC121_ADCSR_TRGE_Pos            (9UL)      /*!< TRGE (Bit 9)                                          */
+ #define R_ADC121_ADCSR_TRGE_Msk            (0x200UL)  /*!< TRGE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC121_ADCSR_ADIE_Pos            (12UL)     /*!< ADIE (Bit 12)                                         */
+ #define R_ADC121_ADCSR_ADIE_Msk            (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC121_ADCSR_ADCS_Pos            (13UL)     /*!< ADCS (Bit 13)                                         */
+ #define R_ADC121_ADCSR_ADCS_Msk            (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03)                            */
+ #define R_ADC121_ADCSR_ADST_Pos            (15UL)     /*!< ADST (Bit 15)                                         */
+ #define R_ADC121_ADCSR_ADST_Msk            (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADANSA0  ======================================================== */
+ #define R_ADC121_ADANSA0_ANSA0_Pos         (0UL)      /*!< ANSA0 (Bit 0)                                         */
+ #define R_ADC121_ADANSA0_ANSA0_Msk         (0xffUL)   /*!< ANSA0 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ADADS0  ========================================================= */
+ #define R_ADC121_ADADS0_ADS0_Pos           (0UL)      /*!< ADS0 (Bit 0)                                          */
+ #define R_ADC121_ADADS0_ADS0_Msk           (0xffUL)   /*!< ADS0 (Bitfield-Mask: 0xff)                            */
+/* =========================================================  ADADC  ========================================================= */
+ #define R_ADC121_ADADC_ADC_Pos             (0UL)      /*!< ADC (Bit 0)                                           */
+ #define R_ADC121_ADADC_ADC_Msk             (0x7UL)    /*!< ADC (Bitfield-Mask: 0x07)                             */
+ #define R_ADC121_ADADC_AVEE_Pos            (7UL)      /*!< AVEE (Bit 7)                                          */
+ #define R_ADC121_ADADC_AVEE_Msk            (0x80UL)   /*!< AVEE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADCER  ========================================================= */
+ #define R_ADC121_ADCER_ADPRC_Pos           (1UL)      /*!< ADPRC (Bit 1)                                         */
+ #define R_ADC121_ADCER_ADPRC_Msk           (0x6UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
+ #define R_ADC121_ADCER_ACE_Pos             (5UL)      /*!< ACE (Bit 5)                                           */
+ #define R_ADC121_ADCER_ACE_Msk             (0x20UL)   /*!< ACE (Bitfield-Mask: 0x01)                             */
+ #define R_ADC121_ADCER_ADRFMT_Pos          (15UL)     /*!< ADRFMT (Bit 15)                                       */
+ #define R_ADC121_ADCER_ADRFMT_Msk          (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADSTRGR  ======================================================== */
+ #define R_ADC121_ADSTRGR_TRSB_Pos          (0UL)      /*!< TRSB (Bit 0)                                          */
+ #define R_ADC121_ADSTRGR_TRSB_Msk          (0x3fUL)   /*!< TRSB (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC121_ADSTRGR_TRSA_Pos          (8UL)      /*!< TRSA (Bit 8)                                          */
+ #define R_ADC121_ADSTRGR_TRSA_Msk          (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f)                            */
+/* ========================================================  ADANSB0  ======================================================== */
+ #define R_ADC121_ADANSB0_ANSB0_Pos         (0UL)      /*!< ANSB0 (Bit 0)                                         */
+ #define R_ADC121_ADANSB0_ANSB0_Msk         (0xffUL)   /*!< ANSB0 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ADDBLDR  ======================================================== */
+ #define R_ADC121_ADDBLDR_DBLDR_Pos         (0UL)      /*!< DBLDR (Bit 0)                                         */
+ #define R_ADC121_ADDBLDR_DBLDR_Msk         (0xffffUL) /*!< DBLDR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  ADDR  ========================================================== */
+ #define R_ADC121_ADDR_DR_Pos               (0UL)      /*!< DR (Bit 0)                                            */
+ #define R_ADC121_ADDR_DR_Msk               (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff)                            */
+/* ========================================================  ADSHCR  ========================================================= */
+ #define R_ADC121_ADSHCR_SSTSH_Pos          (0UL)      /*!< SSTSH (Bit 0)                                         */
+ #define R_ADC121_ADSHCR_SSTSH_Msk          (0xffUL)   /*!< SSTSH (Bitfield-Mask: 0xff)                           */
+ #define R_ADC121_ADSHCR_SHANS_Pos          (8UL)      /*!< SHANS (Bit 8)                                         */
+ #define R_ADC121_ADSHCR_SHANS_Msk          (0x700UL)  /*!< SHANS (Bitfield-Mask: 0x07)                           */
+/* ========================================================  ADELCCR  ======================================================== */
+ #define R_ADC121_ADELCCR_ELCC_Pos          (0UL)      /*!< ELCC (Bit 0)                                          */
+ #define R_ADC121_ADELCCR_ELCC_Msk          (0x3UL)    /*!< ELCC (Bitfield-Mask: 0x03)                            */
+ #define R_ADC121_ADELCCR_GCELC_Pos         (2UL)      /*!< GCELC (Bit 2)                                         */
+ #define R_ADC121_ADELCCR_GCELC_Msk         (0x4UL)    /*!< GCELC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADGSPCR  ======================================================== */
+ #define R_ADC121_ADGSPCR_PGS_Pos           (0UL)      /*!< PGS (Bit 0)                                           */
+ #define R_ADC121_ADGSPCR_PGS_Msk           (0x1UL)    /*!< PGS (Bitfield-Mask: 0x01)                             */
+ #define R_ADC121_ADGSPCR_GBRSCN_Pos        (1UL)      /*!< GBRSCN (Bit 1)                                        */
+ #define R_ADC121_ADGSPCR_GBRSCN_Msk        (0x2UL)    /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
+ #define R_ADC121_ADGSPCR_LGRRS_Pos         (14UL)     /*!< LGRRS (Bit 14)                                        */
+ #define R_ADC121_ADGSPCR_LGRRS_Msk         (0x4000UL) /*!< LGRRS (Bitfield-Mask: 0x01)                           */
+ #define R_ADC121_ADGSPCR_GBRP_Pos          (15UL)     /*!< GBRP (Bit 15)                                         */
+ #define R_ADC121_ADGSPCR_GBRP_Msk          (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADDBLDRA  ======================================================== */
+ #define R_ADC121_ADDBLDRA_DBLDRA_Pos       (0UL)      /*!< DBLDRA (Bit 0)                                        */
+ #define R_ADC121_ADDBLDRA_DBLDRA_Msk       (0xffffUL) /*!< DBLDRA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADDBLDRB  ======================================================== */
+ #define R_ADC121_ADDBLDRB_DBLDRB_Pos       (0UL)      /*!< DBLDRB (Bit 0)                                        */
+ #define R_ADC121_ADDBLDRB_DBLDRB_Msk       (0xffffUL) /*!< DBLDRB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADWINMON  ======================================================== */
+ #define R_ADC121_ADWINMON_MONCOMB_Pos      (0UL)      /*!< MONCOMB (Bit 0)                                       */
+ #define R_ADC121_ADWINMON_MONCOMB_Msk      (0x1UL)    /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
+ #define R_ADC121_ADWINMON_MONCMPA_Pos      (4UL)      /*!< MONCMPA (Bit 4)                                       */
+ #define R_ADC121_ADWINMON_MONCMPA_Msk      (0x10UL)   /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC121_ADWINMON_MONCMPB_Pos      (5UL)      /*!< MONCMPB (Bit 5)                                       */
+ #define R_ADC121_ADWINMON_MONCMPB_Msk      (0x20UL)   /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADCMPCR  ======================================================== */
+ #define R_ADC121_ADCMPCR_CMPAB_Pos         (0UL)      /*!< CMPAB (Bit 0)                                         */
+ #define R_ADC121_ADCMPCR_CMPAB_Msk         (0x3UL)    /*!< CMPAB (Bitfield-Mask: 0x03)                           */
+ #define R_ADC121_ADCMPCR_CMPBE_Pos         (9UL)      /*!< CMPBE (Bit 9)                                         */
+ #define R_ADC121_ADCMPCR_CMPBE_Msk         (0x200UL)  /*!< CMPBE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC121_ADCMPCR_CMPAE_Pos         (11UL)     /*!< CMPAE (Bit 11)                                        */
+ #define R_ADC121_ADCMPCR_CMPAE_Msk         (0x800UL)  /*!< CMPAE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC121_ADCMPCR_CMPBIE_Pos        (13UL)     /*!< CMPBIE (Bit 13)                                       */
+ #define R_ADC121_ADCMPCR_CMPBIE_Msk        (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC121_ADCMPCR_WCMPE_Pos         (14UL)     /*!< WCMPE (Bit 14)                                        */
+ #define R_ADC121_ADCMPCR_WCMPE_Msk         (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC121_ADCMPCR_CMPAIE_Pos        (15UL)     /*!< CMPAIE (Bit 15)                                       */
+ #define R_ADC121_ADCMPCR_CMPAIE_Msk        (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
+/* ======================================================  ADCMPANSR0  ======================================================= */
+ #define R_ADC121_ADCMPANSR0_CMPCHA0_Pos    (0UL)      /*!< CMPCHA0 (Bit 0)                                       */
+ #define R_ADC121_ADCMPANSR0_CMPCHA0_Msk    (0xffUL)   /*!< CMPCHA0 (Bitfield-Mask: 0xff)                         */
+/* =======================================================  ADCMPLR0  ======================================================== */
+ #define R_ADC121_ADCMPLR0_CMPLCHA0_Pos     (0UL)      /*!< CMPLCHA0 (Bit 0)                                      */
+ #define R_ADC121_ADCMPLR0_CMPLCHA0_Msk     (0xffUL)   /*!< CMPLCHA0 (Bitfield-Mask: 0xff)                        */
+/* =======================================================  ADCMPDR0  ======================================================== */
+ #define R_ADC121_ADCMPDR0_CMPLLA_Pos       (0UL)      /*!< CMPLLA (Bit 0)                                        */
+ #define R_ADC121_ADCMPDR0_CMPLLA_Msk       (0xffffUL) /*!< CMPLLA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPDR1  ======================================================== */
+ #define R_ADC121_ADCMPDR1_CMPULA_Pos       (0UL)      /*!< CMPULA (Bit 0)                                        */
+ #define R_ADC121_ADCMPDR1_CMPULA_Msk       (0xffffUL) /*!< CMPULA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPSR0  ======================================================== */
+ #define R_ADC121_ADCMPSR0_CMPSTCHA0_Pos    (0UL)      /*!< CMPSTCHA0 (Bit 0)                                     */
+ #define R_ADC121_ADCMPSR0_CMPSTCHA0_Msk    (0xffUL)   /*!< CMPSTCHA0 (Bitfield-Mask: 0xff)                       */
+/* =======================================================  ADCMPBNSR  ======================================================= */
+ #define R_ADC121_ADCMPBNSR_CMPCHB_Pos      (0UL)      /*!< CMPCHB (Bit 0)                                        */
+ #define R_ADC121_ADCMPBNSR_CMPCHB_Msk      (0x3fUL)   /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
+ #define R_ADC121_ADCMPBNSR_CMPLB_Pos       (7UL)      /*!< CMPLB (Bit 7)                                         */
+ #define R_ADC121_ADCMPBNSR_CMPLB_Msk       (0x80UL)   /*!< CMPLB (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADWINLLB  ======================================================== */
+ #define R_ADC121_ADWINLLB_CMPLLB_Pos       (0UL)      /*!< CMPLLB (Bit 0)                                        */
+ #define R_ADC121_ADWINLLB_CMPLLB_Msk       (0xffffUL) /*!< CMPLLB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADWINULB  ======================================================== */
+ #define R_ADC121_ADWINULB_CMPULB_Pos       (0UL)      /*!< CMPULB (Bit 0)                                        */
+ #define R_ADC121_ADWINULB_CMPULB_Msk       (0xffffUL) /*!< CMPULB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPBSR  ======================================================== */
+ #define R_ADC121_ADCMPBSR_CMPSTB_Pos       (0UL)      /*!< CMPSTB (Bit 0)                                        */
+ #define R_ADC121_ADCMPBSR_CMPSTB_Msk       (0x1UL)    /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADANSC0  ======================================================== */
+ #define R_ADC121_ADANSC0_ANSC0_Pos         (0UL)      /*!< ANSC0 (Bit 0)                                         */
+ #define R_ADC121_ADANSC0_ANSC0_Msk         (0xffUL)   /*!< ANSC0 (Bitfield-Mask: 0xff)                           */
+/* =======================================================  ADGCTRGR  ======================================================== */
+ #define R_ADC121_ADGCTRGR_TRSC_Pos         (0UL)      /*!< TRSC (Bit 0)                                          */
+ #define R_ADC121_ADGCTRGR_TRSC_Msk         (0x3fUL)   /*!< TRSC (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC121_ADGCTRGR_GCADIE_Pos       (6UL)      /*!< GCADIE (Bit 6)                                        */
+ #define R_ADC121_ADGCTRGR_GCADIE_Msk       (0x40UL)   /*!< GCADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC121_ADGCTRGR_GRCE_Pos         (7UL)      /*!< GRCE (Bit 7)                                          */
+ #define R_ADC121_ADGCTRGR_GRCE_Msk         (0x80UL)   /*!< GRCE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADSSTR  ========================================================= */
+ #define R_ADC121_ADSSTR_SST_Pos            (0UL)      /*!< SST (Bit 0)                                           */
+ #define R_ADC121_ADSSTR_SST_Msk            (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TSU                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TSUSM  ========================================================= */
+ #define R_TSU_TSUSM_TSEN_Pos      (0UL)     /*!< TSEN (Bit 0)                                          */
+ #define R_TSU_TSUSM_TSEN_Msk      (0x1UL)   /*!< TSEN (Bitfield-Mask: 0x01)                            */
+ #define R_TSU_TSUSM_ADCEN_Pos     (1UL)     /*!< ADCEN (Bit 1)                                         */
+ #define R_TSU_TSUSM_ADCEN_Msk     (0x2UL)   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
+/* =========================================================  TSUST  ========================================================= */
+ #define R_TSU_TSUST_START_Pos     (0UL)     /*!< START (Bit 0)                                         */
+ #define R_TSU_TSUST_START_Msk     (0x1UL)   /*!< START (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TSUSCS  ========================================================= */
+ #define R_TSU_TSUSCS_CKDIV_Pos    (3UL)     /*!< CKDIV (Bit 3)                                         */
+ #define R_TSU_TSUSCS_CKDIV_Msk    (0x8UL)   /*!< CKDIV (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TSUSAD  ========================================================= */
+ #define R_TSU_TSUSAD_DOUT_Pos     (0UL)     /*!< DOUT (Bit 0)                                          */
+ #define R_TSU_TSUSAD_DOUT_Msk     (0xfffUL) /*!< DOUT (Bitfield-Mask: 0xfff)                           */
+/* =========================================================  TSUSS  ========================================================= */
+ #define R_TSU_TSUSS_CONV_Pos      (0UL)     /*!< CONV (Bit 0)                                          */
+ #define R_TSU_TSUSS_CONV_Msk      (0x1UL)   /*!< CONV (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG1                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  POEG1GA  ======================================================== */
+ #define R_POEG1_POEG1GA_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG1_POEG1GA_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG1_POEG1GA_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG1_POEG1GA_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GA_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG1_POEG1GA_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GA_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG1_POEG1GA_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG1_POEG1GA_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG1_POEG1GA_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GA_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG1_POEG1GA_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG1_POEG1GA_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG1_POEG1GA_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GA_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG1_POEG1GA_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG1_POEG1GA_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG1GB  ======================================================== */
+ #define R_POEG1_POEG1GB_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG1_POEG1GB_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG1_POEG1GB_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG1_POEG1GB_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GB_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG1_POEG1GB_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GB_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG1_POEG1GB_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG1_POEG1GB_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG1_POEG1GB_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GB_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG1_POEG1GB_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG1_POEG1GB_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG1_POEG1GB_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GB_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG1_POEG1GB_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG1_POEG1GB_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG1GC  ======================================================== */
+ #define R_POEG1_POEG1GC_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG1_POEG1GC_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG1_POEG1GC_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG1_POEG1GC_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GC_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG1_POEG1GC_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GC_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG1_POEG1GC_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG1_POEG1GC_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG1_POEG1GC_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GC_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG1_POEG1GC_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG1_POEG1GC_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG1_POEG1GC_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GC_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG1_POEG1GC_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG1_POEG1GC_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG1GD  ======================================================== */
+ #define R_POEG1_POEG1GD_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG1_POEG1GD_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG1_POEG1GD_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG1_POEG1GD_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GD_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG1_POEG1GD_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GD_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG1_POEG1GD_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG1_POEG1GD_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG1_POEG1GD_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GD_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG1_POEG1GD_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG1_POEG1GD_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG1_POEG1GD_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GD_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG1_POEG1GD_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG1_POEG1GD_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ICU_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  NS_SWINT  ======================================================== */
+ #define R_ICU_NS_NS_SWINT_IC0_Pos                  (0UL)          /*!< IC0 (Bit 0)                                           */
+ #define R_ICU_NS_NS_SWINT_IC0_Msk                  (0x1UL)        /*!< IC0 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC1_Pos                  (1UL)          /*!< IC1 (Bit 1)                                           */
+ #define R_ICU_NS_NS_SWINT_IC1_Msk                  (0x2UL)        /*!< IC1 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC2_Pos                  (2UL)          /*!< IC2 (Bit 2)                                           */
+ #define R_ICU_NS_NS_SWINT_IC2_Msk                  (0x4UL)        /*!< IC2 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC3_Pos                  (3UL)          /*!< IC3 (Bit 3)                                           */
+ #define R_ICU_NS_NS_SWINT_IC3_Msk                  (0x8UL)        /*!< IC3 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC4_Pos                  (4UL)          /*!< IC4 (Bit 4)                                           */
+ #define R_ICU_NS_NS_SWINT_IC4_Msk                  (0x10UL)       /*!< IC4 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC5_Pos                  (5UL)          /*!< IC5 (Bit 5)                                           */
+ #define R_ICU_NS_NS_SWINT_IC5_Msk                  (0x20UL)       /*!< IC5 (Bitfield-Mask: 0x01)                             */
+/* ===================================================  NS_PORTNF_FLTSEL  ==================================================== */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Pos         (0UL)          /*!< FLT0 (Bit 0)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Msk         (0x1UL)        /*!< FLT0 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Pos         (1UL)          /*!< FLT1 (Bit 1)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Msk         (0x2UL)        /*!< FLT1 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Pos         (2UL)          /*!< FLT2 (Bit 2)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Msk         (0x4UL)        /*!< FLT2 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Pos         (3UL)          /*!< FLT3 (Bit 3)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Msk         (0x8UL)        /*!< FLT3 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Pos         (4UL)          /*!< FLT4 (Bit 4)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Msk         (0x10UL)       /*!< FLT4 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Pos         (5UL)          /*!< FLT5 (Bit 5)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Msk         (0x20UL)       /*!< FLT5 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Pos         (6UL)          /*!< FLT6 (Bit 6)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Msk         (0x40UL)       /*!< FLT6 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Pos         (7UL)          /*!< FLT7 (Bit 7)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Msk         (0x80UL)       /*!< FLT7 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Pos         (8UL)          /*!< FLT8 (Bit 8)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Msk         (0x100UL)      /*!< FLT8 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Pos         (9UL)          /*!< FLT9 (Bit 9)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Msk         (0x200UL)      /*!< FLT9 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Pos        (10UL)         /*!< FLT10 (Bit 10)                                        */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Msk        (0x400UL)      /*!< FLT10 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Pos        (11UL)         /*!< FLT11 (Bit 11)                                        */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Msk        (0x800UL)      /*!< FLT11 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Pos        (12UL)         /*!< FLT12 (Bit 12)                                        */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Msk        (0x1000UL)     /*!< FLT12 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Pos        (13UL)         /*!< FLT13 (Bit 13)                                        */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Msk        (0x2000UL)     /*!< FLT13 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Pos       (14UL)         /*!< FLTDRQ (Bit 14)                                       */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Msk       (0x4000UL)     /*!< FLTDRQ (Bitfield-Mask: 0x01)                          */
+/* ===================================================  NS_PORTNF_CLKSEL  ==================================================== */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Pos       (0UL)          /*!< CKSEL0 (Bit 0)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Msk       (0x3UL)        /*!< CKSEL0 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Pos       (2UL)          /*!< CKSEL1 (Bit 2)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Msk       (0xcUL)        /*!< CKSEL1 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Pos       (4UL)          /*!< CKSEL2 (Bit 4)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Msk       (0x30UL)       /*!< CKSEL2 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Pos       (6UL)          /*!< CKSEL3 (Bit 6)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Msk       (0xc0UL)       /*!< CKSEL3 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Pos       (8UL)          /*!< CKSEL4 (Bit 8)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Msk       (0x300UL)      /*!< CKSEL4 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Pos       (10UL)         /*!< CKSEL5 (Bit 10)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Msk       (0xc00UL)      /*!< CKSEL5 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Pos       (12UL)         /*!< CKSEL6 (Bit 12)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Msk       (0x3000UL)     /*!< CKSEL6 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Pos       (14UL)         /*!< CKSEL7 (Bit 14)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Msk       (0xc000UL)     /*!< CKSEL7 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Pos       (16UL)         /*!< CKSEL8 (Bit 16)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Msk       (0x30000UL)    /*!< CKSEL8 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Pos       (18UL)         /*!< CKSEL9 (Bit 18)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Msk       (0xc0000UL)    /*!< CKSEL9 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Pos      (20UL)         /*!< CKSEL10 (Bit 20)                                      */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Msk      (0x300000UL)   /*!< CKSEL10 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Pos      (22UL)         /*!< CKSEL11 (Bit 22)                                      */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Msk      (0xc00000UL)   /*!< CKSEL11 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Pos      (24UL)         /*!< CKSEL12 (Bit 24)                                      */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Msk      (0x3000000UL)  /*!< CKSEL12 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Pos      (26UL)         /*!< CKSEL13 (Bit 26)                                      */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Msk      (0xc000000UL)  /*!< CKSEL13 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Pos    (28UL)         /*!< CKSELDREQ (Bit 28)                                    */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Msk    (0x30000000UL) /*!< CKSELDREQ (Bitfield-Mask: 0x03)                       */
+/* =====================================================  NS_PORTNF_MD  ====================================================== */
+ #define R_ICU_NS_NS_PORTNF_MD_MD0_Pos              (0UL)          /*!< MD0 (Bit 0)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD0_Msk              (0x3UL)        /*!< MD0 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD1_Pos              (2UL)          /*!< MD1 (Bit 2)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD1_Msk              (0xcUL)        /*!< MD1 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD2_Pos              (4UL)          /*!< MD2 (Bit 4)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD2_Msk              (0x30UL)       /*!< MD2 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD3_Pos              (6UL)          /*!< MD3 (Bit 6)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD3_Msk              (0xc0UL)       /*!< MD3 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD4_Pos              (8UL)          /*!< MD4 (Bit 8)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD4_Msk              (0x300UL)      /*!< MD4 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD5_Pos              (10UL)         /*!< MD5 (Bit 10)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD5_Msk              (0xc00UL)      /*!< MD5 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD6_Pos              (12UL)         /*!< MD6 (Bit 12)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD6_Msk              (0x3000UL)     /*!< MD6 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD7_Pos              (14UL)         /*!< MD7 (Bit 14)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD7_Msk              (0xc000UL)     /*!< MD7 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD8_Pos              (16UL)         /*!< MD8 (Bit 16)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD8_Msk              (0x30000UL)    /*!< MD8 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD9_Pos              (18UL)         /*!< MD9 (Bit 18)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD9_Msk              (0xc0000UL)    /*!< MD9 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD10_Pos             (20UL)         /*!< MD10 (Bit 20)                                         */
+ #define R_ICU_NS_NS_PORTNF_MD_MD10_Msk             (0x300000UL)   /*!< MD10 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_NS_NS_PORTNF_MD_MD11_Pos             (22UL)         /*!< MD11 (Bit 22)                                         */
+ #define R_ICU_NS_NS_PORTNF_MD_MD11_Msk             (0xc00000UL)   /*!< MD11 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_NS_NS_PORTNF_MD_MD12_Pos             (24UL)         /*!< MD12 (Bit 24)                                         */
+ #define R_ICU_NS_NS_PORTNF_MD_MD12_Msk             (0x3000000UL)  /*!< MD12 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_NS_NS_PORTNF_MD_MD13_Pos             (26UL)         /*!< MD13 (Bit 26)                                         */
+ #define R_ICU_NS_NS_PORTNF_MD_MD13_Msk             (0xc000000UL)  /*!< MD13 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Pos            (28UL)         /*!< MDDRQ (Bit 28)                                        */
+ #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Msk            (0x30000000UL) /*!< MDDRQ (Bitfield-Mask: 0x03)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  ELC_SSEL  ======================================================== */
+ #define R_ELC_ELC_SSEL_ELC_SEL0_Pos    (0UL)          /*!< ELC_SEL0 (Bit 0)                                      */
+ #define R_ELC_ELC_SSEL_ELC_SEL0_Msk    (0x3ffUL)      /*!< ELC_SEL0 (Bitfield-Mask: 0x3ff)                       */
+ #define R_ELC_ELC_SSEL_ELC_SEL1_Pos    (10UL)         /*!< ELC_SEL1 (Bit 10)                                     */
+ #define R_ELC_ELC_SSEL_ELC_SEL1_Msk    (0xffc00UL)    /*!< ELC_SEL1 (Bitfield-Mask: 0x3ff)                       */
+ #define R_ELC_ELC_SSEL_ELC_SEL2_Pos    (20UL)         /*!< ELC_SEL2 (Bit 20)                                     */
+ #define R_ELC_ELC_SSEL_ELC_SEL2_Msk    (0x3ff00000UL) /*!< ELC_SEL2 (Bitfield-Mask: 0x3ff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  DMAC0_RSSEL  ====================================================== */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELA_Pos    (0UL)          /*!< REQ_SELA (Bit 0)                                      */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELA_Msk    (0x1ffUL)      /*!< REQ_SELA (Bitfield-Mask: 0x1ff)                       */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELB_Pos    (10UL)         /*!< REQ_SELB (Bit 10)                                     */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELB_Msk    (0x7fc00UL)    /*!< REQ_SELB (Bitfield-Mask: 0x1ff)                       */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELC_Pos    (20UL)         /*!< REQ_SELC (Bit 20)                                     */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELC_Msk    (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff)                       */
+/* ======================================================  DMAC1_RSSEL  ====================================================== */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELA_Pos    (0UL)          /*!< REQ_SELA (Bit 0)                                      */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELA_Msk    (0x1ffUL)      /*!< REQ_SELA (Bitfield-Mask: 0x1ff)                       */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELB_Pos    (10UL)         /*!< REQ_SELB (Bit 10)                                     */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELB_Msk    (0x7fc00UL)    /*!< REQ_SELB (Bitfield-Mask: 0x1ff)                       */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELC_Pos    (20UL)         /*!< REQ_SELC (Bit 20)                                     */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELC_Msk    (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                       R_PORT_COMMON                                       ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  P  =========================================================== */
+ #define R_PORT_NSR_P_POUT_0_Pos          (0UL)          /*!< POUT_0 (Bit 0)                                        */
+ #define R_PORT_NSR_P_POUT_0_Msk          (0x1UL)        /*!< POUT_0 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_1_Pos          (1UL)          /*!< POUT_1 (Bit 1)                                        */
+ #define R_PORT_NSR_P_POUT_1_Msk          (0x2UL)        /*!< POUT_1 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_2_Pos          (2UL)          /*!< POUT_2 (Bit 2)                                        */
+ #define R_PORT_NSR_P_POUT_2_Msk          (0x4UL)        /*!< POUT_2 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_3_Pos          (3UL)          /*!< POUT_3 (Bit 3)                                        */
+ #define R_PORT_NSR_P_POUT_3_Msk          (0x8UL)        /*!< POUT_3 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_4_Pos          (4UL)          /*!< POUT_4 (Bit 4)                                        */
+ #define R_PORT_NSR_P_POUT_4_Msk          (0x10UL)       /*!< POUT_4 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_5_Pos          (5UL)          /*!< POUT_5 (Bit 5)                                        */
+ #define R_PORT_NSR_P_POUT_5_Msk          (0x20UL)       /*!< POUT_5 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_6_Pos          (6UL)          /*!< POUT_6 (Bit 6)                                        */
+ #define R_PORT_NSR_P_POUT_6_Msk          (0x40UL)       /*!< POUT_6 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_7_Pos          (7UL)          /*!< POUT_7 (Bit 7)                                        */
+ #define R_PORT_NSR_P_POUT_7_Msk          (0x80UL)       /*!< POUT_7 (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  PM  =========================================================== */
+ #define R_PORT_NSR_PM_PM0_Pos            (0UL)          /*!< PM0 (Bit 0)                                           */
+ #define R_PORT_NSR_PM_PM0_Msk            (0x3UL)        /*!< PM0 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM1_Pos            (2UL)          /*!< PM1 (Bit 2)                                           */
+ #define R_PORT_NSR_PM_PM1_Msk            (0xcUL)        /*!< PM1 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM2_Pos            (4UL)          /*!< PM2 (Bit 4)                                           */
+ #define R_PORT_NSR_PM_PM2_Msk            (0x30UL)       /*!< PM2 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM3_Pos            (6UL)          /*!< PM3 (Bit 6)                                           */
+ #define R_PORT_NSR_PM_PM3_Msk            (0xc0UL)       /*!< PM3 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM4_Pos            (8UL)          /*!< PM4 (Bit 8)                                           */
+ #define R_PORT_NSR_PM_PM4_Msk            (0x300UL)      /*!< PM4 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM5_Pos            (10UL)         /*!< PM5 (Bit 10)                                          */
+ #define R_PORT_NSR_PM_PM5_Msk            (0xc00UL)      /*!< PM5 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM6_Pos            (12UL)         /*!< PM6 (Bit 12)                                          */
+ #define R_PORT_NSR_PM_PM6_Msk            (0x3000UL)     /*!< PM6 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM7_Pos            (14UL)         /*!< PM7 (Bit 14)                                          */
+ #define R_PORT_NSR_PM_PM7_Msk            (0xc000UL)     /*!< PM7 (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  PMC  ========================================================== */
+ #define R_PORT_NSR_PMC_PMC0_Pos          (0UL)          /*!< PMC0 (Bit 0)                                          */
+ #define R_PORT_NSR_PMC_PMC0_Msk          (0x1UL)        /*!< PMC0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC1_Pos          (1UL)          /*!< PMC1 (Bit 1)                                          */
+ #define R_PORT_NSR_PMC_PMC1_Msk          (0x2UL)        /*!< PMC1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC2_Pos          (2UL)          /*!< PMC2 (Bit 2)                                          */
+ #define R_PORT_NSR_PMC_PMC2_Msk          (0x4UL)        /*!< PMC2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC3_Pos          (3UL)          /*!< PMC3 (Bit 3)                                          */
+ #define R_PORT_NSR_PMC_PMC3_Msk          (0x8UL)        /*!< PMC3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC4_Pos          (4UL)          /*!< PMC4 (Bit 4)                                          */
+ #define R_PORT_NSR_PMC_PMC4_Msk          (0x10UL)       /*!< PMC4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC5_Pos          (5UL)          /*!< PMC5 (Bit 5)                                          */
+ #define R_PORT_NSR_PMC_PMC5_Msk          (0x20UL)       /*!< PMC5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC6_Pos          (6UL)          /*!< PMC6 (Bit 6)                                          */
+ #define R_PORT_NSR_PMC_PMC6_Msk          (0x40UL)       /*!< PMC6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC7_Pos          (7UL)          /*!< PMC7 (Bit 7)                                          */
+ #define R_PORT_NSR_PMC_PMC7_Msk          (0x80UL)       /*!< PMC7 (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  PFC  ========================================================== */
+ #define R_PORT_NSR_PFC_PFC0_Pos          (0UL)          /*!< PFC0 (Bit 0)                                          */
+ #define R_PORT_NSR_PFC_PFC0_Msk          (0xfUL)        /*!< PFC0 (Bitfield-Mask: 0x0f)                            */
+ #define R_PORT_NSR_PFC_PFC1_Pos          (4UL)          /*!< PFC1 (Bit 4)                                          */
+ #define R_PORT_NSR_PFC_PFC1_Msk          (0xf0UL)       /*!< PFC1 (Bitfield-Mask: 0x0f)                            */
+ #define R_PORT_NSR_PFC_PFC2_Pos          (8UL)          /*!< PFC2 (Bit 8)                                          */
+ #define R_PORT_NSR_PFC_PFC2_Msk          (0xf00UL)      /*!< PFC2 (Bitfield-Mask: 0x0f)                            */
+ #define R_PORT_NSR_PFC_PFC3_Pos          (12UL)         /*!< PFC3 (Bit 12)                                         */
+ #define R_PORT_NSR_PFC_PFC3_Msk          (0xf000UL)     /*!< PFC3 (Bitfield-Mask: 0x0f)                            */
+ #define R_PORT_NSR_PFC_PFC4_Pos          (16UL)         /*!< PFC4 (Bit 16)                                         */
+ #define R_PORT_NSR_PFC_PFC4_Msk          (0xf0000UL)    /*!< PFC4 (Bitfield-Mask: 0x0f)                            */
+ #define R_PORT_NSR_PFC_PFC5_Pos          (20UL)         /*!< PFC5 (Bit 20)                                         */
+ #define R_PORT_NSR_PFC_PFC5_Msk          (0xf00000UL)   /*!< PFC5 (Bitfield-Mask: 0x0f)                            */
+ #define R_PORT_NSR_PFC_PFC6_Pos          (24UL)         /*!< PFC6 (Bit 24)                                         */
+ #define R_PORT_NSR_PFC_PFC6_Msk          (0xf000000UL)  /*!< PFC6 (Bitfield-Mask: 0x0f)                            */
+ #define R_PORT_NSR_PFC_PFC7_Pos          (28UL)         /*!< PFC7 (Bit 28)                                         */
+ #define R_PORT_NSR_PFC_PFC7_Msk          (0xf0000000UL) /*!< PFC7 (Bitfield-Mask: 0x0f)                            */
+/* ==========================================================  PIN  ========================================================== */
+ #define R_PORT_NSR_PIN_PIN0_Pos          (0UL)          /*!< PIN0 (Bit 0)                                          */
+ #define R_PORT_NSR_PIN_PIN0_Msk          (0x1UL)        /*!< PIN0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN1_Pos          (1UL)          /*!< PIN1 (Bit 1)                                          */
+ #define R_PORT_NSR_PIN_PIN1_Msk          (0x2UL)        /*!< PIN1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN2_Pos          (2UL)          /*!< PIN2 (Bit 2)                                          */
+ #define R_PORT_NSR_PIN_PIN2_Msk          (0x4UL)        /*!< PIN2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN3_Pos          (3UL)          /*!< PIN3 (Bit 3)                                          */
+ #define R_PORT_NSR_PIN_PIN3_Msk          (0x8UL)        /*!< PIN3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN4_Pos          (4UL)          /*!< PIN4 (Bit 4)                                          */
+ #define R_PORT_NSR_PIN_PIN4_Msk          (0x10UL)       /*!< PIN4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN5_Pos          (5UL)          /*!< PIN5 (Bit 5)                                          */
+ #define R_PORT_NSR_PIN_PIN5_Msk          (0x20UL)       /*!< PIN5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN6_Pos          (6UL)          /*!< PIN6 (Bit 6)                                          */
+ #define R_PORT_NSR_PIN_PIN6_Msk          (0x40UL)       /*!< PIN6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN7_Pos          (7UL)          /*!< PIN7 (Bit 7)                                          */
+ #define R_PORT_NSR_PIN_PIN7_Msk          (0x80UL)       /*!< PIN7 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ELC_PGR  ======================================================== */
+ #define R_PORT_NSR_ELC_PGR_PG0_Pos       (0UL)          /*!< PG0 (Bit 0)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG0_Msk       (0x1UL)        /*!< PG0 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG1_Pos       (1UL)          /*!< PG1 (Bit 1)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG1_Msk       (0x2UL)        /*!< PG1 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG2_Pos       (2UL)          /*!< PG2 (Bit 2)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG2_Msk       (0x4UL)        /*!< PG2 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG3_Pos       (3UL)          /*!< PG3 (Bit 3)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG3_Msk       (0x8UL)        /*!< PG3 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG4_Pos       (4UL)          /*!< PG4 (Bit 4)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG4_Msk       (0x10UL)       /*!< PG4 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG5_Pos       (5UL)          /*!< PG5 (Bit 5)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG5_Msk       (0x20UL)       /*!< PG5 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG6_Pos       (6UL)          /*!< PG6 (Bit 6)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG6_Msk       (0x40UL)       /*!< PG6 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG7_Pos       (7UL)          /*!< PG7 (Bit 7)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG7_Msk       (0x80UL)       /*!< PG7 (Bitfield-Mask: 0x01)                             */
+/* ========================================================  ELC_PGC  ======================================================== */
+ #define R_PORT_NSR_ELC_PGC_PGCI_Pos      (0UL)          /*!< PGCI (Bit 0)                                          */
+ #define R_PORT_NSR_ELC_PGC_PGCI_Msk      (0x3UL)        /*!< PGCI (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_ELC_PGC_PGCOVE_Pos    (2UL)          /*!< PGCOVE (Bit 2)                                        */
+ #define R_PORT_NSR_ELC_PGC_PGCOVE_Msk    (0x4UL)        /*!< PGCOVE (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_ELC_PGC_PGCO_Pos      (4UL)          /*!< PGCO (Bit 4)                                          */
+ #define R_PORT_NSR_ELC_PGC_PGCO_Msk      (0x70UL)       /*!< PGCO (Bitfield-Mask: 0x07)                            */
+/* ========================================================  ELC_PEL  ======================================================== */
+ #define R_PORT_NSR_ELC_PEL_PSB_Pos       (0UL)          /*!< PSB (Bit 0)                                           */
+ #define R_PORT_NSR_ELC_PEL_PSB_Msk       (0x7UL)        /*!< PSB (Bitfield-Mask: 0x07)                             */
+ #define R_PORT_NSR_ELC_PEL_PSP_Pos       (3UL)          /*!< PSP (Bit 3)                                           */
+ #define R_PORT_NSR_ELC_PEL_PSP_Msk       (0x18UL)       /*!< PSP (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_ELC_PEL_PSM_Pos       (5UL)          /*!< PSM (Bit 5)                                           */
+ #define R_PORT_NSR_ELC_PEL_PSM_Msk       (0x60UL)       /*!< PSM (Bitfield-Mask: 0x03)                             */
+/* =======================================================  ELC_DPTC  ======================================================== */
+ #define R_PORT_NSR_ELC_DPTC_PTC0_Pos     (0UL)          /*!< PTC0 (Bit 0)                                          */
+ #define R_PORT_NSR_ELC_DPTC_PTC0_Msk     (0x1UL)        /*!< PTC0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_DPTC_PTC1_Pos     (1UL)          /*!< PTC1 (Bit 1)                                          */
+ #define R_PORT_NSR_ELC_DPTC_PTC1_Msk     (0x2UL)        /*!< PTC1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_DPTC_PTC2_Pos     (2UL)          /*!< PTC2 (Bit 2)                                          */
+ #define R_PORT_NSR_ELC_DPTC_PTC2_Msk     (0x4UL)        /*!< PTC2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_DPTC_PTC3_Pos     (3UL)          /*!< PTC3 (Bit 3)                                          */
+ #define R_PORT_NSR_ELC_DPTC_PTC3_Msk     (0x8UL)        /*!< PTC3 (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ELC_ELSR2  ======================================================= */
+ #define R_PORT_NSR_ELC_ELSR2_PEG1_Pos    (2UL)          /*!< PEG1 (Bit 2)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PEG1_Msk    (0x4UL)        /*!< PEG1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PEG2_Pos    (3UL)          /*!< PEG2 (Bit 3)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PEG2_Msk    (0x8UL)        /*!< PEG2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PES0_Pos    (4UL)          /*!< PES0 (Bit 4)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PES0_Msk    (0x10UL)       /*!< PES0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PES1_Pos    (5UL)          /*!< PES1 (Bit 5)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PES1_Msk    (0x20UL)       /*!< PES1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PES2_Pos    (6UL)          /*!< PES2 (Bit 6)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PES2_Msk    (0x40UL)       /*!< PES2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PES3_Pos    (7UL)          /*!< PES3 (Bit 7)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PES3_Msk    (0x80UL)       /*!< PES3 (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GMAC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================  MAC_Configuration  =================================================== */
+ #define R_GMAC_MAC_Configuration_PRELEN_Pos                              (0UL)          /*!< PRELEN (Bit 0)                                        */
+ #define R_GMAC_MAC_Configuration_PRELEN_Msk                              (0x3UL)        /*!< PRELEN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC_MAC_Configuration_RE_Pos                                  (2UL)          /*!< RE (Bit 2)                                            */
+ #define R_GMAC_MAC_Configuration_RE_Msk                                  (0x4UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_TE_Pos                                  (3UL)          /*!< TE (Bit 3)                                            */
+ #define R_GMAC_MAC_Configuration_TE_Msk                                  (0x8UL)        /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_DC_Pos                                  (4UL)          /*!< DC (Bit 4)                                            */
+ #define R_GMAC_MAC_Configuration_DC_Msk                                  (0x10UL)       /*!< DC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_BL_Pos                                  (5UL)          /*!< BL (Bit 5)                                            */
+ #define R_GMAC_MAC_Configuration_BL_Msk                                  (0x60UL)       /*!< BL (Bitfield-Mask: 0x03)                              */
+ #define R_GMAC_MAC_Configuration_ACS_Pos                                 (7UL)          /*!< ACS (Bit 7)                                           */
+ #define R_GMAC_MAC_Configuration_ACS_Msk                                 (0x80UL)       /*!< ACS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Configuration_DR_Pos                                  (9UL)          /*!< DR (Bit 9)                                            */
+ #define R_GMAC_MAC_Configuration_DR_Msk                                  (0x200UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_IPC_Pos                                 (10UL)         /*!< IPC (Bit 10)                                          */
+ #define R_GMAC_MAC_Configuration_IPC_Msk                                 (0x400UL)      /*!< IPC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Configuration_DM_Pos                                  (11UL)         /*!< DM (Bit 11)                                           */
+ #define R_GMAC_MAC_Configuration_DM_Msk                                  (0x800UL)      /*!< DM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_LM_Pos                                  (12UL)         /*!< LM (Bit 12)                                           */
+ #define R_GMAC_MAC_Configuration_LM_Msk                                  (0x1000UL)     /*!< LM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_DO_Pos                                  (13UL)         /*!< DO (Bit 13)                                           */
+ #define R_GMAC_MAC_Configuration_DO_Msk                                  (0x2000UL)     /*!< DO (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_FES_Pos                                 (14UL)         /*!< FES (Bit 14)                                          */
+ #define R_GMAC_MAC_Configuration_FES_Msk                                 (0x4000UL)     /*!< FES (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Configuration_PS_Pos                                  (15UL)         /*!< PS (Bit 15)                                           */
+ #define R_GMAC_MAC_Configuration_PS_Msk                                  (0x8000UL)     /*!< PS (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_DCRS_Pos                                (16UL)         /*!< DCRS (Bit 16)                                         */
+ #define R_GMAC_MAC_Configuration_DCRS_Msk                                (0x10000UL)    /*!< DCRS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_MAC_Configuration_IFG_Pos                                 (17UL)         /*!< IFG (Bit 17)                                          */
+ #define R_GMAC_MAC_Configuration_IFG_Msk                                 (0xe0000UL)    /*!< IFG (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC_MAC_Configuration_JE_Pos                                  (20UL)         /*!< JE (Bit 20)                                           */
+ #define R_GMAC_MAC_Configuration_JE_Msk                                  (0x100000UL)   /*!< JE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_BE_Pos                                  (21UL)         /*!< BE (Bit 21)                                           */
+ #define R_GMAC_MAC_Configuration_BE_Msk                                  (0x200000UL)   /*!< BE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_JD_Pos                                  (22UL)         /*!< JD (Bit 22)                                           */
+ #define R_GMAC_MAC_Configuration_JD_Msk                                  (0x400000UL)   /*!< JD (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_WD_Pos                                  (23UL)         /*!< WD (Bit 23)                                           */
+ #define R_GMAC_MAC_Configuration_WD_Msk                                  (0x800000UL)   /*!< WD (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Configuration_CST_Pos                                 (25UL)         /*!< CST (Bit 25)                                          */
+ #define R_GMAC_MAC_Configuration_CST_Msk                                 (0x2000000UL)  /*!< CST (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Configuration_TWOKPE_Pos                              (27UL)         /*!< TWOKPE (Bit 27)                                       */
+ #define R_GMAC_MAC_Configuration_TWOKPE_Msk                              (0x8000000UL)  /*!< TWOKPE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_Frame_Filter  ==================================================== */
+ #define R_GMAC_MAC_Frame_Filter_PR_Pos                                   (0UL)          /*!< PR (Bit 0)                                            */
+ #define R_GMAC_MAC_Frame_Filter_PR_Msk                                   (0x1UL)        /*!< PR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Frame_Filter_HUC_Pos                                  (1UL)          /*!< HUC (Bit 1)                                           */
+ #define R_GMAC_MAC_Frame_Filter_HUC_Msk                                  (0x2UL)        /*!< HUC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Frame_Filter_HMC_Pos                                  (2UL)          /*!< HMC (Bit 2)                                           */
+ #define R_GMAC_MAC_Frame_Filter_HMC_Msk                                  (0x4UL)        /*!< HMC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Frame_Filter_DAIF_Pos                                 (3UL)          /*!< DAIF (Bit 3)                                          */
+ #define R_GMAC_MAC_Frame_Filter_DAIF_Msk                                 (0x8UL)        /*!< DAIF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_MAC_Frame_Filter_PM_Pos                                   (4UL)          /*!< PM (Bit 4)                                            */
+ #define R_GMAC_MAC_Frame_Filter_PM_Msk                                   (0x10UL)       /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAC_Frame_Filter_DBF_Pos                                  (5UL)          /*!< DBF (Bit 5)                                           */
+ #define R_GMAC_MAC_Frame_Filter_DBF_Msk                                  (0x20UL)       /*!< DBF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Frame_Filter_PCF_Pos                                  (6UL)          /*!< PCF (Bit 6)                                           */
+ #define R_GMAC_MAC_Frame_Filter_PCF_Msk                                  (0xc0UL)       /*!< PCF (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC_MAC_Frame_Filter_SAIF_Pos                                 (8UL)          /*!< SAIF (Bit 8)                                          */
+ #define R_GMAC_MAC_Frame_Filter_SAIF_Msk                                 (0x100UL)      /*!< SAIF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_MAC_Frame_Filter_SAF_Pos                                  (9UL)          /*!< SAF (Bit 9)                                           */
+ #define R_GMAC_MAC_Frame_Filter_SAF_Msk                                  (0x200UL)      /*!< SAF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Frame_Filter_HPF_Pos                                  (10UL)         /*!< HPF (Bit 10)                                          */
+ #define R_GMAC_MAC_Frame_Filter_HPF_Msk                                  (0x400UL)      /*!< HPF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_MAC_Frame_Filter_VTFE_Pos                                 (16UL)         /*!< VTFE (Bit 16)                                         */
+ #define R_GMAC_MAC_Frame_Filter_VTFE_Msk                                 (0x10000UL)    /*!< VTFE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_MAC_Frame_Filter_RA_Pos                                   (31UL)         /*!< RA (Bit 31)                                           */
+ #define R_GMAC_MAC_Frame_Filter_RA_Msk                                   (0x80000000UL) /*!< RA (Bitfield-Mask: 0x01)                              */
+/* =====================================================  GMII_Address  ====================================================== */
+ #define R_GMAC_GMII_Address_GB_Pos                                       (0UL)          /*!< GB (Bit 0)                                            */
+ #define R_GMAC_GMII_Address_GB_Msk                                       (0x1UL)        /*!< GB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_GMII_Address_GW_Pos                                       (1UL)          /*!< GW (Bit 1)                                            */
+ #define R_GMAC_GMII_Address_GW_Msk                                       (0x2UL)        /*!< GW (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_GMII_Address_CR_Pos                                       (2UL)          /*!< CR (Bit 2)                                            */
+ #define R_GMAC_GMII_Address_CR_Msk                                       (0x3cUL)       /*!< CR (Bitfield-Mask: 0x0f)                              */
+ #define R_GMAC_GMII_Address_GR_Pos                                       (6UL)          /*!< GR (Bit 6)                                            */
+ #define R_GMAC_GMII_Address_GR_Msk                                       (0x7c0UL)      /*!< GR (Bitfield-Mask: 0x1f)                              */
+ #define R_GMAC_GMII_Address_PA_Pos                                       (11UL)         /*!< PA (Bit 11)                                           */
+ #define R_GMAC_GMII_Address_PA_Msk                                       (0xf800UL)     /*!< PA (Bitfield-Mask: 0x1f)                              */
+/* =======================================================  GMII_Data  ======================================================= */
+ #define R_GMAC_GMII_Data_GD_Pos                                          (0UL)          /*!< GD (Bit 0)                                            */
+ #define R_GMAC_GMII_Data_GD_Msk                                          (0xffffUL)     /*!< GD (Bitfield-Mask: 0xffff)                            */
+/* =====================================================  Flow_Control  ====================================================== */
+ #define R_GMAC_Flow_Control_FCA_BPA_Pos                                  (0UL)          /*!< FCA_BPA (Bit 0)                                       */
+ #define R_GMAC_Flow_Control_FCA_BPA_Msk                                  (0x1UL)        /*!< FCA_BPA (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_Flow_Control_TFE_Pos                                      (1UL)          /*!< TFE (Bit 1)                                           */
+ #define R_GMAC_Flow_Control_TFE_Msk                                      (0x2UL)        /*!< TFE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Flow_Control_RFE_Pos                                      (2UL)          /*!< RFE (Bit 2)                                           */
+ #define R_GMAC_Flow_Control_RFE_Msk                                      (0x4UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Flow_Control_UP_Pos                                       (3UL)          /*!< UP (Bit 3)                                            */
+ #define R_GMAC_Flow_Control_UP_Msk                                       (0x8UL)        /*!< UP (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Flow_Control_PLT_Pos                                      (4UL)          /*!< PLT (Bit 4)                                           */
+ #define R_GMAC_Flow_Control_PLT_Msk                                      (0x30UL)       /*!< PLT (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC_Flow_Control_DZPQ_Pos                                     (7UL)          /*!< DZPQ (Bit 7)                                          */
+ #define R_GMAC_Flow_Control_DZPQ_Msk                                     (0x80UL)       /*!< DZPQ (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_Flow_Control_PT_Pos                                       (16UL)         /*!< PT (Bit 16)                                           */
+ #define R_GMAC_Flow_Control_PT_Msk                                       (0xffff0000UL) /*!< PT (Bitfield-Mask: 0xffff)                            */
+/* =======================================================  VLAN_Tag  ======================================================== */
+ #define R_GMAC_VLAN_Tag_VL_Pos                                           (0UL)          /*!< VL (Bit 0)                                            */
+ #define R_GMAC_VLAN_Tag_VL_Msk                                           (0xffffUL)     /*!< VL (Bitfield-Mask: 0xffff)                            */
+ #define R_GMAC_VLAN_Tag_ETV_Pos                                          (16UL)         /*!< ETV (Bit 16)                                          */
+ #define R_GMAC_VLAN_Tag_ETV_Msk                                          (0x10000UL)    /*!< ETV (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_VLAN_Tag_VTIM_Pos                                         (17UL)         /*!< VTIM (Bit 17)                                         */
+ #define R_GMAC_VLAN_Tag_VTIM_Msk                                         (0x20000UL)    /*!< VTIM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_VLAN_Tag_ESVL_Pos                                         (18UL)         /*!< ESVL (Bit 18)                                         */
+ #define R_GMAC_VLAN_Tag_ESVL_Msk                                         (0x40000UL)    /*!< ESVL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_VLAN_Tag_VTHM_Pos                                         (19UL)         /*!< VTHM (Bit 19)                                         */
+ #define R_GMAC_VLAN_Tag_VTHM_Msk                                         (0x80000UL)    /*!< VTHM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  Version  ======================================================== */
+ #define R_GMAC_Version_VER_Pos                                           (0UL)          /*!< VER (Bit 0)                                           */
+ #define R_GMAC_Version_VER_Msk                                           (0xffffUL)     /*!< VER (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  Debug  ========================================================= */
+ #define R_GMAC_Debug_RPESTS_Pos                                          (0UL)          /*!< RPESTS (Bit 0)                                        */
+ #define R_GMAC_Debug_RPESTS_Msk                                          (0x1UL)        /*!< RPESTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_Debug_RFCFCSTS_Pos                                        (1UL)          /*!< RFCFCSTS (Bit 1)                                      */
+ #define R_GMAC_Debug_RFCFCSTS_Msk                                        (0x6UL)        /*!< RFCFCSTS (Bitfield-Mask: 0x03)                        */
+ #define R_GMAC_Debug_RWCSTS_Pos                                          (4UL)          /*!< RWCSTS (Bit 4)                                        */
+ #define R_GMAC_Debug_RWCSTS_Msk                                          (0x10UL)       /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_Debug_RRCSTS_Pos                                          (5UL)          /*!< RRCSTS (Bit 5)                                        */
+ #define R_GMAC_Debug_RRCSTS_Msk                                          (0x60UL)       /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC_Debug_RXFSTS_Pos                                          (8UL)          /*!< RXFSTS (Bit 8)                                        */
+ #define R_GMAC_Debug_RXFSTS_Msk                                          (0x300UL)      /*!< RXFSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC_Debug_TPESTS_Pos                                          (16UL)         /*!< TPESTS (Bit 16)                                       */
+ #define R_GMAC_Debug_TPESTS_Msk                                          (0x10000UL)    /*!< TPESTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_Debug_TFCSTS_Pos                                          (17UL)         /*!< TFCSTS (Bit 17)                                       */
+ #define R_GMAC_Debug_TFCSTS_Msk                                          (0x60000UL)    /*!< TFCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC_Debug_TXPAUSED_Pos                                        (19UL)         /*!< TXPAUSED (Bit 19)                                     */
+ #define R_GMAC_Debug_TXPAUSED_Msk                                        (0x80000UL)    /*!< TXPAUSED (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_Debug_TRCSTS_Pos                                          (20UL)         /*!< TRCSTS (Bit 20)                                       */
+ #define R_GMAC_Debug_TRCSTS_Msk                                          (0x300000UL)   /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC_Debug_TWCSTS_Pos                                          (22UL)         /*!< TWCSTS (Bit 22)                                       */
+ #define R_GMAC_Debug_TWCSTS_Msk                                          (0x400000UL)   /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_Debug_TXFSTS_Pos                                          (24UL)         /*!< TXFSTS (Bit 24)                                       */
+ #define R_GMAC_Debug_TXFSTS_Msk                                          (0x1000000UL)  /*!< TXFSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_Debug_TXSTSFSTS_Pos                                       (25UL)         /*!< TXSTSFSTS (Bit 25)                                    */
+ #define R_GMAC_Debug_TXSTSFSTS_Msk                                       (0x2000000UL)  /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+/* ==============================================  Remote_Wake_Up_Frame_Filter  ============================================== */
+ #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Pos                (0UL)          /*!< WKUPFRMFTR (Bit 0)                                    */
+ #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Msk                (0xffffffffUL) /*!< WKUPFRMFTR (Bitfield-Mask: 0xffffffff)           */
+/* ==================================================  PMT_Control_Status  =================================================== */
+ #define R_GMAC_PMT_Control_Status_PWRDWN_Pos                             (0UL)          /*!< PWRDWN (Bit 0)                                        */
+ #define R_GMAC_PMT_Control_Status_PWRDWN_Msk                             (0x1UL)        /*!< PWRDWN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_PMT_Control_Status_MGKPKTEN_Pos                           (1UL)          /*!< MGKPKTEN (Bit 1)                                      */
+ #define R_GMAC_PMT_Control_Status_MGKPKTEN_Msk                           (0x2UL)        /*!< MGKPKTEN (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_PMT_Control_Status_RWKPKTEN_Pos                           (2UL)          /*!< RWKPKTEN (Bit 2)                                      */
+ #define R_GMAC_PMT_Control_Status_RWKPKTEN_Msk                           (0x4UL)        /*!< RWKPKTEN (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_PMT_Control_Status_MGKPRCVD_Pos                           (5UL)          /*!< MGKPRCVD (Bit 5)                                      */
+ #define R_GMAC_PMT_Control_Status_MGKPRCVD_Msk                           (0x20UL)       /*!< MGKPRCVD (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_PMT_Control_Status_RWKPRCVD_Pos                           (6UL)          /*!< RWKPRCVD (Bit 6)                                      */
+ #define R_GMAC_PMT_Control_Status_RWKPRCVD_Msk                           (0x40UL)       /*!< RWKPRCVD (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_PMT_Control_Status_GLBLUCAST_Pos                          (9UL)          /*!< GLBLUCAST (Bit 9)                                     */
+ #define R_GMAC_PMT_Control_Status_GLBLUCAST_Msk                          (0x200UL)      /*!< GLBLUCAST (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_PMT_Control_Status_RWKPTR_Pos                             (24UL)         /*!< RWKPTR (Bit 24)                                       */
+ #define R_GMAC_PMT_Control_Status_RWKPTR_Msk                             (0x7000000UL)  /*!< RWKPTR (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC_PMT_Control_Status_RWKFILTRST_Pos                         (31UL)         /*!< RWKFILTRST (Bit 31)                                   */
+ #define R_GMAC_PMT_Control_Status_RWKFILTRST_Msk                         (0x80000000UL) /*!< RWKFILTRST (Bitfield-Mask: 0x01)                      */
+/* ==================================================  LPI_Control_Status  =================================================== */
+ #define R_GMAC_LPI_Control_Status_TLPIEN_Pos                             (0UL)          /*!< TLPIEN (Bit 0)                                        */
+ #define R_GMAC_LPI_Control_Status_TLPIEN_Msk                             (0x1UL)        /*!< TLPIEN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_LPI_Control_Status_TLPIEX_Pos                             (1UL)          /*!< TLPIEX (Bit 1)                                        */
+ #define R_GMAC_LPI_Control_Status_TLPIEX_Msk                             (0x2UL)        /*!< TLPIEX (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_LPI_Control_Status_RLPIEN_Pos                             (2UL)          /*!< RLPIEN (Bit 2)                                        */
+ #define R_GMAC_LPI_Control_Status_RLPIEN_Msk                             (0x4UL)        /*!< RLPIEN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_LPI_Control_Status_RLPIEX_Pos                             (3UL)          /*!< RLPIEX (Bit 3)                                        */
+ #define R_GMAC_LPI_Control_Status_RLPIEX_Msk                             (0x8UL)        /*!< RLPIEX (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_LPI_Control_Status_TLPIST_Pos                             (8UL)          /*!< TLPIST (Bit 8)                                        */
+ #define R_GMAC_LPI_Control_Status_TLPIST_Msk                             (0x100UL)      /*!< TLPIST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_LPI_Control_Status_RLPIST_Pos                             (9UL)          /*!< RLPIST (Bit 9)                                        */
+ #define R_GMAC_LPI_Control_Status_RLPIST_Msk                             (0x200UL)      /*!< RLPIST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_LPI_Control_Status_LPIEN_Pos                              (16UL)         /*!< LPIEN (Bit 16)                                        */
+ #define R_GMAC_LPI_Control_Status_LPIEN_Msk                              (0x10000UL)    /*!< LPIEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_LPI_Control_Status_PLS_Pos                                (17UL)         /*!< PLS (Bit 17)                                          */
+ #define R_GMAC_LPI_Control_Status_PLS_Msk                                (0x20000UL)    /*!< PLS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_LPI_Control_Status_LPITXA_Pos                             (19UL)         /*!< LPITXA (Bit 19)                                       */
+ #define R_GMAC_LPI_Control_Status_LPITXA_Msk                             (0x80000UL)    /*!< LPITXA (Bitfield-Mask: 0x01)                          */
+/* ==================================================  LPI_Timers_Control  =================================================== */
+ #define R_GMAC_LPI_Timers_Control_TWT_Pos                                (0UL)          /*!< TWT (Bit 0)                                           */
+ #define R_GMAC_LPI_Timers_Control_TWT_Msk                                (0xffffUL)     /*!< TWT (Bitfield-Mask: 0xffff)                           */
+ #define R_GMAC_LPI_Timers_Control_LST_Pos                                (16UL)         /*!< LST (Bit 16)                                          */
+ #define R_GMAC_LPI_Timers_Control_LST_Msk                                (0x3ff0000UL)  /*!< LST (Bitfield-Mask: 0x3ff)                            */
+/* ===================================================  Interrupt_Status  ==================================================== */
+ #define R_GMAC_Interrupt_Status_PMTIS_Pos                                (3UL)          /*!< PMTIS (Bit 3)                                         */
+ #define R_GMAC_Interrupt_Status_PMTIS_Msk                                (0x8UL)        /*!< PMTIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_Interrupt_Status_MMCIS_Pos                                (4UL)          /*!< MMCIS (Bit 4)                                         */
+ #define R_GMAC_Interrupt_Status_MMCIS_Msk                                (0x10UL)       /*!< MMCIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_Interrupt_Status_MMCRXIS_Pos                              (5UL)          /*!< MMCRXIS (Bit 5)                                       */
+ #define R_GMAC_Interrupt_Status_MMCRXIS_Msk                              (0x20UL)       /*!< MMCRXIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_Interrupt_Status_MMCTXIS_Pos                              (6UL)          /*!< MMCTXIS (Bit 6)                                       */
+ #define R_GMAC_Interrupt_Status_MMCTXIS_Msk                              (0x40UL)       /*!< MMCTXIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_Interrupt_Status_MMCRXIPIS_Pos                            (7UL)          /*!< MMCRXIPIS (Bit 7)                                     */
+ #define R_GMAC_Interrupt_Status_MMCRXIPIS_Msk                            (0x80UL)       /*!< MMCRXIPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_Interrupt_Status_TSIS_Pos                                 (9UL)          /*!< TSIS (Bit 9)                                          */
+ #define R_GMAC_Interrupt_Status_TSIS_Msk                                 (0x200UL)      /*!< TSIS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_Interrupt_Status_LPIIS_Pos                                (10UL)         /*!< LPIIS (Bit 10)                                        */
+ #define R_GMAC_Interrupt_Status_LPIIS_Msk                                (0x400UL)      /*!< LPIIS (Bitfield-Mask: 0x01)                           */
+/* ====================================================  Interrupt_Mask  ===================================================== */
+ #define R_GMAC_Interrupt_Mask_PMTIM_Pos                                  (3UL)          /*!< PMTIM (Bit 3)                                         */
+ #define R_GMAC_Interrupt_Mask_PMTIM_Msk                                  (0x8UL)        /*!< PMTIM (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_Interrupt_Mask_TSIM_Pos                                   (9UL)          /*!< TSIM (Bit 9)                                          */
+ #define R_GMAC_Interrupt_Mask_TSIM_Msk                                   (0x200UL)      /*!< TSIM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_Interrupt_Mask_LPIIM_Pos                                  (10UL)         /*!< LPIIM (Bit 10)                                        */
+ #define R_GMAC_Interrupt_Mask_LPIIM_Msk                                  (0x400UL)      /*!< LPIIM (Bitfield-Mask: 0x01)                           */
+/* ========================================================  MAR0_H  ========================================================= */
+ #define R_GMAC_MAR0_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR0_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR0_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR0_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR0_L  ========================================================= */
+ #define R_GMAC_MAR0_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR0_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR1_H  ========================================================= */
+ #define R_GMAC_MAR1_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR1_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR1_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR1_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR1_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR1_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR1_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR1_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR2_H  ========================================================= */
+ #define R_GMAC_MAR2_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR2_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR2_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR2_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR2_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR2_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR2_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR2_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR3_H  ========================================================= */
+ #define R_GMAC_MAR3_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR3_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR3_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR3_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR3_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR3_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR3_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR3_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR4_H  ========================================================= */
+ #define R_GMAC_MAR4_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR4_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR4_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR4_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR4_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR4_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR4_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR4_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR5_H  ========================================================= */
+ #define R_GMAC_MAR5_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR5_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR5_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR5_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR5_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR5_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR5_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR5_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR6_H  ========================================================= */
+ #define R_GMAC_MAR6_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR6_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR6_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR6_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR6_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR6_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR6_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR6_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR7_H  ========================================================= */
+ #define R_GMAC_MAR7_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR7_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR7_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR7_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR7_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR7_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR7_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR7_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR8_H  ========================================================= */
+ #define R_GMAC_MAR8_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR8_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR8_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR8_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR8_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR8_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR8_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR8_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR9_H  ========================================================= */
+ #define R_GMAC_MAR9_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR9_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR9_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR9_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR9_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR9_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR9_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR9_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR10_H  ======================================================== */
+ #define R_GMAC_MAR10_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR10_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR10_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR10_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR10_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR10_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR10_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR10_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR11_H  ======================================================== */
+ #define R_GMAC_MAR11_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR11_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR11_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR11_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR11_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR11_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR11_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR11_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR12_H  ======================================================== */
+ #define R_GMAC_MAR12_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR12_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR12_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR12_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR12_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR12_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR12_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR12_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR13_H  ======================================================== */
+ #define R_GMAC_MAR13_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR13_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR13_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR13_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR13_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR13_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR13_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR13_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR14_H  ======================================================== */
+ #define R_GMAC_MAR14_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR14_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR14_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR14_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR14_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR14_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR14_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR14_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR15_H  ======================================================== */
+ #define R_GMAC_MAR15_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR15_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR15_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR15_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR15_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR15_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR15_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR15_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR1_L  ========================================================= */
+ #define R_GMAC_MAR1_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR1_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR2_L  ========================================================= */
+ #define R_GMAC_MAR2_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR2_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR3_L  ========================================================= */
+ #define R_GMAC_MAR3_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR3_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR4_L  ========================================================= */
+ #define R_GMAC_MAR4_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR4_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR5_L  ========================================================= */
+ #define R_GMAC_MAR5_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR5_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR6_L  ========================================================= */
+ #define R_GMAC_MAR6_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR6_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR7_L  ========================================================= */
+ #define R_GMAC_MAR7_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR7_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR8_L  ========================================================= */
+ #define R_GMAC_MAR8_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR8_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR9_L  ========================================================= */
+ #define R_GMAC_MAR9_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR9_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR10_L  ======================================================== */
+ #define R_GMAC_MAR10_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR10_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR11_L  ======================================================== */
+ #define R_GMAC_MAR11_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR11_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR12_L  ======================================================== */
+ #define R_GMAC_MAR12_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR12_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR13_L  ======================================================== */
+ #define R_GMAC_MAR13_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR13_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR14_L  ======================================================== */
+ #define R_GMAC_MAR14_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR14_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR15_L  ======================================================== */
+ #define R_GMAC_MAR15_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR15_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  WDog_Timeout  ====================================================== */
+ #define R_GMAC_WDog_Timeout_WTO_Pos                                      (0UL)          /*!< WTO (Bit 0)                                           */
+ #define R_GMAC_WDog_Timeout_WTO_Msk                                      (0x3fffUL)     /*!< WTO (Bitfield-Mask: 0x3fff)                           */
+ #define R_GMAC_WDog_Timeout_PWE_Pos                                      (16UL)         /*!< PWE (Bit 16)                                          */
+ #define R_GMAC_WDog_Timeout_PWE_Msk                                      (0x10000UL)    /*!< PWE (Bitfield-Mask: 0x01)                             */
+/* ======================================================  MMC_Control  ====================================================== */
+ #define R_GMAC_MMC_Control_CNTRST_Pos                                    (0UL)          /*!< CNTRST (Bit 0)                                        */
+ #define R_GMAC_MMC_Control_CNTRST_Msk                                    (0x1UL)        /*!< CNTRST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_MMC_Control_CNTSTOPRO_Pos                                 (1UL)          /*!< CNTSTOPRO (Bit 1)                                     */
+ #define R_GMAC_MMC_Control_CNTSTOPRO_Msk                                 (0x2UL)        /*!< CNTSTOPRO (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Control_RSTONRD_Pos                                   (2UL)          /*!< RSTONRD (Bit 2)                                       */
+ #define R_GMAC_MMC_Control_RSTONRD_Msk                                   (0x4UL)        /*!< RSTONRD (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_MMC_Control_CNTFREEZ_Pos                                  (3UL)          /*!< CNTFREEZ (Bit 3)                                      */
+ #define R_GMAC_MMC_Control_CNTFREEZ_Msk                                  (0x8UL)        /*!< CNTFREEZ (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Control_CNTPRST_Pos                                   (4UL)          /*!< CNTPRST (Bit 4)                                       */
+ #define R_GMAC_MMC_Control_CNTPRST_Msk                                   (0x10UL)       /*!< CNTPRST (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_MMC_Control_CNTPRSTLVL_Pos                                (5UL)          /*!< CNTPRSTLVL (Bit 5)                                    */
+ #define R_GMAC_MMC_Control_CNTPRSTLVL_Msk                                (0x20UL)       /*!< CNTPRSTLVL (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Control_UCDBC_Pos                                     (8UL)          /*!< UCDBC (Bit 8)                                         */
+ #define R_GMAC_MMC_Control_UCDBC_Msk                                     (0x100UL)      /*!< UCDBC (Bitfield-Mask: 0x01)                           */
+/* =================================================  MMC_Receive_Interrupt  ================================================= */
+ #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Pos                       (0UL)          /*!< RXGBFRMIS (Bit 0)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Msk                       (0x1UL)        /*!< RXGBFRMIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Pos                       (1UL)          /*!< RXGBOCTIS (Bit 1)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Msk                       (0x2UL)        /*!< RXGBOCTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Pos                        (2UL)          /*!< RXGOCTIS (Bit 2)                                      */
+ #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Msk                        (0x4UL)        /*!< RXGOCTIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Pos                        (3UL)          /*!< RXBCGFIS (Bit 3)                                      */
+ #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Msk                        (0x8UL)        /*!< RXBCGFIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Pos                        (4UL)          /*!< RXMCGFIS (Bit 4)                                      */
+ #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Msk                        (0x10UL)       /*!< RXMCGFIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Pos                      (5UL)          /*!< RXCRCERFIS (Bit 5)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Msk                      (0x20UL)       /*!< RXCRCERFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Pos                     (6UL)          /*!< RXALGNERFIS (Bit 6)                                   */
+ #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Msk                     (0x40UL)       /*!< RXALGNERFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Pos                       (7UL)          /*!< RXRUNTFIS (Bit 7)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Msk                       (0x80UL)       /*!< RXRUNTFIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Pos                      (8UL)          /*!< RXJABERFIS (Bit 8)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Msk                      (0x100UL)      /*!< RXJABERFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Pos                     (9UL)          /*!< RXUSIZEGFIS (Bit 9)                                   */
+ #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Msk                     (0x200UL)      /*!< RXUSIZEGFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Pos                     (10UL)         /*!< RXOSIZEGFIS (Bit 10)                                  */
+ #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Msk                     (0x400UL)      /*!< RXOSIZEGFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Pos                    (11UL)         /*!< RX64OCTGBFIS (Bit 11)                                 */
+ #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Msk                    (0x800UL)      /*!< RX64OCTGBFIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Pos                (12UL)         /*!< RX65T127OCTGBFIS (Bit 12)                             */
+ #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Msk                (0x1000UL)     /*!< RX65T127OCTGBFIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Pos               (13UL)         /*!< RX128T255OCTGBFIS (Bit 13)                            */
+ #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Msk               (0x2000UL)     /*!< RX128T255OCTGBFIS (Bitfield-Mask: 0x01)             */
+ #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Pos               (14UL)         /*!< RX256T511OCTGBFIS (Bit 14)                            */
+ #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Msk               (0x4000UL)     /*!< RX256T511OCTGBFIS (Bitfield-Mask: 0x01)             */
+ #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Pos              (15UL)         /*!< RX512T1023OCTGBFIS (Bit 15)                           */
+ #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Msk              (0x8000UL)     /*!< RX512T1023OCTGBFIS (Bitfield-Mask: 0x01)           */
+ #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Pos              (16UL)         /*!< RX1024TMAXOCTGBFIS (Bit 16)                           */
+ #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Msk              (0x10000UL)    /*!< RX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01)          */
+ #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Pos                        (17UL)         /*!< RXUCGFIS (Bit 17)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Msk                        (0x20000UL)    /*!< RXUCGFIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Pos                      (18UL)         /*!< RXLENERFIS (Bit 18)                                   */
+ #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Msk                      (0x40000UL)    /*!< RXLENERFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Pos                     (19UL)         /*!< RXORANGEFIS (Bit 19)                                  */
+ #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Msk                     (0x80000UL)    /*!< RXORANGEFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Pos                       (20UL)         /*!< RXPAUSFIS (Bit 20)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Msk                       (0x100000UL)   /*!< RXPAUSFIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Pos                        (21UL)         /*!< RXFOVFIS (Bit 21)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Msk                        (0x200000UL)   /*!< RXFOVFIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Pos                     (22UL)         /*!< RXVLANGBFIS (Bit 22)                                  */
+ #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Msk                     (0x400000UL)   /*!< RXVLANGBFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Pos                       (23UL)         /*!< RXWDOGFIS (Bit 23)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Msk                       (0x800000UL)   /*!< RXWDOGFIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Pos                     (24UL)         /*!< RXRCVERRFIS (Bit 24)                                  */
+ #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Msk                     (0x1000000UL)  /*!< RXRCVERRFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Pos                       (25UL)         /*!< RXCTRLFIS (Bit 25)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Msk                       (0x2000000UL)  /*!< RXCTRLFIS (Bitfield-Mask: 0x01)                       */
+/* ================================================  MMC_Transmit_Interrupt  ================================================= */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Pos                      (0UL)          /*!< TXGBOCTIS (Bit 0)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Msk                      (0x1UL)        /*!< TXGBOCTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Pos                      (1UL)          /*!< TXGBFRMIS (Bit 1)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Msk                      (0x2UL)        /*!< TXGBFRMIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Pos                       (2UL)          /*!< TXBCGFIS (Bit 2)                                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Msk                       (0x4UL)        /*!< TXBCGFIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Pos                       (3UL)          /*!< TXMCGFIS (Bit 3)                                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Msk                       (0x8UL)        /*!< TXMCGFIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Pos                   (4UL)          /*!< TX64OCTGBFIS (Bit 4)                                  */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Msk                   (0x10UL)       /*!< TX64OCTGBFIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Pos               (5UL)          /*!< TX65T127OCTGBFIS (Bit 5)                              */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Msk               (0x20UL)       /*!< TX65T127OCTGBFIS (Bitfield-Mask: 0x01)                */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Pos              (6UL)          /*!< TX128T255OCTGBFIS (Bit 6)                             */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Msk              (0x40UL)       /*!< TX128T255OCTGBFIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Pos              (7UL)          /*!< TX256T511OCTGBFIS (Bit 7)                             */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Msk              (0x80UL)       /*!< TX256T511OCTGBFIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Pos             (8UL)          /*!< TX512T1023OCTGBFIS (Bit 8)                            */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Msk             (0x100UL)      /*!< TX512T1023OCTGBFIS (Bitfield-Mask: 0x01)           */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Pos             (9UL)          /*!< TX1024TMAXOCTGBFIS (Bit 9)                            */
+ #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Msk             (0x200UL)      /*!< TX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01)           */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Pos                      (10UL)         /*!< TXUCGBFIS (Bit 10)                                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Msk                      (0x400UL)      /*!< TXUCGBFIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Pos                      (11UL)         /*!< TXMCGBFIS (Bit 11)                                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Msk                      (0x800UL)      /*!< TXMCGBFIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Pos                      (12UL)         /*!< TXBCGBFIS (Bit 12)                                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Msk                      (0x1000UL)     /*!< TXBCGBFIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Pos                   (13UL)         /*!< TXUFLOWERFIS (Bit 13)                                 */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Msk                   (0x2000UL)     /*!< TXUFLOWERFIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Pos                     (14UL)         /*!< TXSCOLGFIS (Bit 14)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Msk                     (0x4000UL)     /*!< TXSCOLGFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Pos                     (15UL)         /*!< TXMCOLGFIS (Bit 15)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Msk                     (0x8000UL)     /*!< TXMCOLGFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Pos                       (16UL)         /*!< TXDEFFIS (Bit 16)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Msk                       (0x10000UL)    /*!< TXDEFFIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Pos                    (17UL)         /*!< TXLATCOLFIS (Bit 17)                                  */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Msk                    (0x20000UL)    /*!< TXLATCOLFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Pos                     (18UL)         /*!< TXEXCOLFIS (Bit 18)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Msk                     (0x40000UL)    /*!< TXEXCOLFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Pos                     (19UL)         /*!< TXCARERFIS (Bit 19)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Msk                     (0x80000UL)    /*!< TXCARERFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Pos                       (20UL)         /*!< TXGOCTIS (Bit 20)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Msk                       (0x100000UL)   /*!< TXGOCTIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Pos                       (21UL)         /*!< TXGFRMIS (Bit 21)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Msk                       (0x200000UL)   /*!< TXGFRMIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Pos                     (22UL)         /*!< TXEXDEFFIS (Bit 22)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Msk                     (0x400000UL)   /*!< TXEXDEFFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Pos                      (23UL)         /*!< TXPAUSFIS (Bit 23)                                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Msk                      (0x800000UL)   /*!< TXPAUSFIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Pos                     (24UL)         /*!< TXVLANGFIS (Bit 24)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Msk                     (0x1000000UL)  /*!< TXVLANGFIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Pos                    (25UL)         /*!< TXOSIZEGFIS (Bit 25)                                  */
+ #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Msk                    (0x2000000UL)  /*!< TXOSIZEGFIS (Bitfield-Mask: 0x01)                     */
+/* ==============================================  MMC_Receive_Interrupt_Mask  =============================================== */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Pos                  (0UL)          /*!< RXGBFRMIM (Bit 0)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Msk                  (0x1UL)        /*!< RXGBFRMIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Pos                  (1UL)          /*!< RXGBOCTIM (Bit 1)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Msk                  (0x2UL)        /*!< RXGBOCTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Pos                   (2UL)          /*!< RXGOCTIM (Bit 2)                                      */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Msk                   (0x4UL)        /*!< RXGOCTIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Pos                   (3UL)          /*!< RXBCGFIM (Bit 3)                                      */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Msk                   (0x8UL)        /*!< RXBCGFIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Pos                   (4UL)          /*!< RXMCGFIM (Bit 4)                                      */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Msk                   (0x10UL)       /*!< RXMCGFIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Pos                 (5UL)          /*!< RXCRCERFIM (Bit 5)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Msk                 (0x20UL)       /*!< RXCRCERFIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Pos                (6UL)          /*!< RXALGNERFIM (Bit 6)                                   */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Msk                (0x40UL)       /*!< RXALGNERFIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Pos                  (7UL)          /*!< RXRUNTFIM (Bit 7)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Msk                  (0x80UL)       /*!< RXRUNTFIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Pos                 (8UL)          /*!< RXJABERFIM (Bit 8)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Msk                 (0x100UL)      /*!< RXJABERFIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Pos                (9UL)          /*!< RXUSIZEGFIM (Bit 9)                                   */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Msk                (0x200UL)      /*!< RXUSIZEGFIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Pos                (10UL)         /*!< RXOSIZEGFIM (Bit 10)                                  */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Msk                (0x400UL)      /*!< RXOSIZEGFIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Pos               (11UL)         /*!< RX64OCTGBFIM (Bit 11)                                 */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Msk               (0x800UL)      /*!< RX64OCTGBFIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Pos           (12UL)         /*!< RX65T127OCTGBFIM (Bit 12)                           */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Msk           (0x1000UL)     /*!< RX65T127OCTGBFIM (Bitfield-Mask: 0x01)          */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Pos          (13UL)         /*!< RX128T255OCTGBFIM (Bit 13)                         */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Msk          (0x2000UL)     /*!< RX128T255OCTGBFIM (Bitfield-Mask: 0x01)        */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Pos          (14UL)         /*!< RX256T511OCTGBFIM (Bit 14)                         */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Msk          (0x4000UL)     /*!< RX256T511OCTGBFIM (Bitfield-Mask: 0x01)        */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Pos         (15UL)         /*!< RX512T1023OCTGBFIM (Bit 15)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Msk         (0x8000UL)     /*!< RX512T1023OCTGBFIM (Bitfield-Mask: 0x01)      */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Pos         (16UL)         /*!< RX1024TMAXOCTGBFIM (Bit 16)                       */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Msk         (0x10000UL)    /*!< RX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01)     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Pos                   (17UL)         /*!< RXUCGFIM (Bit 17)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Msk                   (0x20000UL)    /*!< RXUCGFIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Pos                 (18UL)         /*!< RXLENERFIM (Bit 18)                                   */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Msk                 (0x40000UL)    /*!< RXLENERFIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Pos                (19UL)         /*!< RXORANGEFIM (Bit 19)                                  */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Msk                (0x80000UL)    /*!< RXORANGEFIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Pos                  (20UL)         /*!< RXPAUSFIM (Bit 20)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Msk                  (0x100000UL)   /*!< RXPAUSFIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Pos                   (21UL)         /*!< RXFOVFIM (Bit 21)                                     */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Msk                   (0x200000UL)   /*!< RXFOVFIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Pos                (22UL)         /*!< RXVLANGBFIM (Bit 22)                                  */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Msk                (0x400000UL)   /*!< RXVLANGBFIM (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Pos                  (23UL)         /*!< RXWDOGFIM (Bit 23)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Msk                  (0x800000UL)   /*!< RXWDOGFIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Pos                (24UL)         /*!< RXRCVERRFIM (Bit 24)                                  */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Msk                (0x1000000UL)  /*!< RXRCVERRFIM (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Pos                  (25UL)         /*!< RXCTRLFIM (Bit 25)                                    */
+ #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Msk                  (0x2000000UL)  /*!< RXCTRLFIM (Bitfield-Mask: 0x01)                     */
+/* ==============================================  MMC_Transmit_Interrupt_Mask  ============================================== */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Pos                 (0UL)          /*!< TXGBOCTIM (Bit 0)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Msk                 (0x1UL)        /*!< TXGBOCTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Pos                 (1UL)          /*!< TXGBFRMIM (Bit 1)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Msk                 (0x2UL)        /*!< TXGBFRMIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Pos                  (2UL)          /*!< TXBCGFIM (Bit 2)                                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Msk                  (0x4UL)        /*!< TXBCGFIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Pos                  (3UL)          /*!< TXMCGFIM (Bit 3)                                      */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Msk                  (0x8UL)        /*!< TXMCGFIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Pos              (4UL)          /*!< TX64OCTGBFIM (Bit 4)                                  */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Msk              (0x10UL)       /*!< TX64OCTGBFIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Pos          (5UL)          /*!< TX65T127OCTGBFIM (Bit 5)                            */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Msk          (0x20UL)       /*!< TX65T127OCTGBFIM (Bitfield-Mask: 0x01)           */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Pos         (6UL)          /*!< TX128T255OCTGBFIM (Bit 6)                          */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Msk         (0x40UL)       /*!< TX128T255OCTGBFIM (Bitfield-Mask: 0x01)         */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Pos         (7UL)          /*!< TX256T511OCTGBFIM (Bit 7)                          */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Msk         (0x80UL)       /*!< TX256T511OCTGBFIM (Bitfield-Mask: 0x01)         */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Pos        (8UL)          /*!< TX512T1023OCTGBFIM (Bit 8)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Msk        (0x100UL)      /*!< TX512T1023OCTGBFIM (Bitfield-Mask: 0x01)      */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Pos        (9UL)          /*!< TX1024TMAXOCTGBFIM (Bit 9)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Msk        (0x200UL)      /*!< TX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01)      */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Pos                 (10UL)         /*!< TXUCGBFIM (Bit 10)                                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Msk                 (0x400UL)      /*!< TXUCGBFIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Pos                 (11UL)         /*!< TXMCGBFIM (Bit 11)                                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Msk                 (0x800UL)      /*!< TXMCGBFIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Pos                 (12UL)         /*!< TXBCGBFIM (Bit 12)                                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Msk                 (0x1000UL)     /*!< TXBCGBFIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Pos              (13UL)         /*!< TXUFLOWERFIM (Bit 13)                                 */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Msk              (0x2000UL)     /*!< TXUFLOWERFIM (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Pos                (14UL)         /*!< TXSCOLGFIM (Bit 14)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Msk                (0x4000UL)     /*!< TXSCOLGFIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Pos                (15UL)         /*!< TXMCOLGFIM (Bit 15)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Msk                (0x8000UL)     /*!< TXMCOLGFIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Pos                  (16UL)         /*!< TXDEFFIM (Bit 16)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Msk                  (0x10000UL)    /*!< TXDEFFIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Pos               (17UL)         /*!< TXLATCOLFIM (Bit 17)                                  */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Msk               (0x20000UL)    /*!< TXLATCOLFIM (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Pos                (18UL)         /*!< TXEXCOLFIM (Bit 18)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Msk                (0x40000UL)    /*!< TXEXCOLFIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Pos                (19UL)         /*!< TXCARERFIM (Bit 19)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Msk                (0x80000UL)    /*!< TXCARERFIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Pos                  (20UL)         /*!< TXGOCTIM (Bit 20)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Msk                  (0x100000UL)   /*!< TXGOCTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Pos                  (21UL)         /*!< TXGFRMIM (Bit 21)                                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Msk                  (0x200000UL)   /*!< TXGFRMIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Pos                (22UL)         /*!< TXEXDEFFIM (Bit 22)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Msk                (0x400000UL)   /*!< TXEXDEFFIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Pos                 (23UL)         /*!< TXPAUSFIM (Bit 23)                                    */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Msk                 (0x800000UL)   /*!< TXPAUSFIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Pos                (24UL)         /*!< TXVLANGFIM (Bit 24)                                   */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Msk                (0x1000000UL)  /*!< TXVLANGFIM (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Pos               (25UL)         /*!< TXOSIZEGFIM (Bit 25)                                  */
+ #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Msk               (0x2000000UL)  /*!< TXOSIZEGFIM (Bitfield-Mask: 0x01)                */
+/* ================================================  Tx_Octet_Count_Good_Bad  ================================================ */
+ #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Pos                       (0UL)          /*!< TXOCTGB (Bit 0)                                       */
+ #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Msk                       (0xffffffffUL) /*!< TXOCTGB (Bitfield-Mask: 0xffffffff)                   */
+/* ================================================  Tx_Frame_Count_Good_Bad  ================================================ */
+ #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Pos                       (0UL)          /*!< TXFRMGB (Bit 0)                                       */
+ #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Msk                       (0xffffffffUL) /*!< TXFRMGB (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Tx_Broadcast_Frames_Good  ================================================ */
+ #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Pos                     (0UL)          /*!< TXBCASTG (Bit 0)                                      */
+ #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Msk                     (0xffffffffUL) /*!< TXBCASTG (Bitfield-Mask: 0xffffffff)                  */
+/* ===============================================  Tx_Multicast_Frames_Good  ================================================ */
+ #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Pos                     (0UL)          /*!< TXMCASTG (Bit 0)                                      */
+ #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Msk                     (0xffffffffUL) /*!< TXMCASTG (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  Tx_64Octets_Frames_Good_Bad  ============================================== */
+ #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Pos                 (0UL)          /*!< TX64OCTGB (Bit 0)                                     */
+ #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Msk                 (0xffffffffUL) /*!< TX64OCTGB (Bitfield-Mask: 0xffffffff)             */
+/* ===========================================  Tx_65To127Octets_Frames_Good_Bad  ============================================ */
+ #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Pos        (0UL)          /*!< TX65_127OCTGB (Bit 0)                             */
+ #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Msk        (0xffffffffUL) /*!< TX65_127OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  Tx_128To255Octets_Frames_Good_Bad  =========================================== */
+ #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Pos      (0UL)          /*!< TX128_255OCTGB (Bit 0)                          */
+ #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Msk      (0xffffffffUL) /*!< TX128_255OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  Tx_256To511Octets_Frames_Good_Bad  =========================================== */
+ #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Pos      (0UL)          /*!< TX256_511OCTGB (Bit 0)                          */
+ #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Msk      (0xffffffffUL) /*!< TX256_511OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_512To1023Octets_Frames_Good_Bad  =========================================== */
+ #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Pos    (0UL)          /*!< TX512_1023OCTGB (Bit 0)                       */
+ #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Msk    (0xffffffffUL) /*!< TX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_1024ToMaxOctets_Frames_Good_Bad  =========================================== */
+ #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Pos    (0UL)          /*!< TX1024_MAXOCTGB (Bit 0)                       */
+ #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Msk    (0xffffffffUL) /*!< TX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==============================================  Tx_Unicast_Frames_Good_Bad  =============================================== */
+ #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Pos                  (0UL)          /*!< TXUCASTGB (Bit 0)                                     */
+ #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Msk                  (0xffffffffUL) /*!< TXUCASTGB (Bitfield-Mask: 0xffffffff)              */
+/* =============================================  Tx_Multicast_Frames_Good_Bad  ============================================== */
+ #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Pos                (0UL)          /*!< TXMCASTGB (Bit 0)                                     */
+ #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Msk                (0xffffffffUL) /*!< TXMCASTGB (Bitfield-Mask: 0xffffffff)            */
+/* =============================================  Tx_Broadcast_Frames_Good_Bad  ============================================== */
+ #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Pos                (0UL)          /*!< TXBCASTGB (Bit 0)                                     */
+ #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Msk                (0xffffffffUL) /*!< TXBCASTGB (Bitfield-Mask: 0xffffffff)            */
+/* ===============================================  Tx_Underflow_Error_Frames  =============================================== */
+ #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Pos                   (0UL)          /*!< TXUNDRFLW (Bit 0)                                     */
+ #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Msk                   (0xffffUL)     /*!< TXUNDRFLW (Bitfield-Mask: 0xffff)                     */
+/* ============================================  Tx_Single_Collision_Good_Frames  ============================================ */
+ #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Pos            (0UL)          /*!< TXSNGLCOLG (Bit 0)                                    */
+ #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Msk            (0xffffUL)     /*!< TXSNGLCOLG (Bitfield-Mask: 0xffff)               */
+/* ===========================================  Tx_Multiple_Collision_Good_Frames  =========================================== */
+ #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Pos          (0UL)          /*!< TXMULTCOLG (Bit 0)                                  */
+ #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Msk          (0xffffUL)     /*!< TXMULTCOLG (Bitfield-Mask: 0xffff)             */
+/* ==================================================  Tx_Deferred_Frames  =================================================== */
+ #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Pos                            (0UL)          /*!< TXDEFRD (Bit 0)                                       */
+ #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Msk                            (0xffffUL)     /*!< TXDEFRD (Bitfield-Mask: 0xffff)                       */
+/* ===============================================  Tx_Late_Collision_Frames  ================================================ */
+ #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Pos                    (0UL)          /*!< TXLATECOL (Bit 0)                                     */
+ #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Msk                    (0xffffUL)     /*!< TXLATECOL (Bitfield-Mask: 0xffff)                     */
+/* =============================================  Tx_Excessive_Collision_Frames  ============================================= */
+ #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Pos                (0UL)          /*!< TXEXSCOL (Bit 0)                                      */
+ #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Msk                (0xffffUL)     /*!< TXEXSCOL (Bitfield-Mask: 0xffff)                     */
+/* ================================================  Tx_Carrier_Error_Frames  ================================================ */
+ #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Pos                        (0UL)          /*!< TXCARR (Bit 0)                                        */
+ #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Msk                        (0xffffUL)     /*!< TXCARR (Bitfield-Mask: 0xffff)                        */
+/* ==================================================  Tx_Octet_Count_Good  ================================================== */
+ #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Pos                            (0UL)          /*!< TXOCTG (Bit 0)                                        */
+ #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Msk                            (0xffffffffUL) /*!< TXOCTG (Bitfield-Mask: 0xffffffff)                    */
+/* ==================================================  Tx_Frame_Count_Good  ================================================== */
+ #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Pos                            (0UL)          /*!< TXFRMG (Bit 0)                                        */
+ #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Msk                            (0xffffffffUL) /*!< TXFRMG (Bitfield-Mask: 0xffffffff)                    */
+/* ==============================================  Tx_Excessive_Deferral_Error  ============================================== */
+ #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Pos                  (0UL)          /*!< TXEXSDEF (Bit 0)                                      */
+ #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Msk                  (0xffffUL)     /*!< TXEXSDEF (Bitfield-Mask: 0xffff)                      */
+/* ====================================================  Tx_Pause_Frames  ==================================================== */
+ #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Pos                               (0UL)          /*!< TXPAUSE (Bit 0)                                       */
+ #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Msk                               (0xffffUL)     /*!< TXPAUSE (Bitfield-Mask: 0xffff)                       */
+/* ==================================================  Tx_VLAN_Frames_Good  ================================================== */
+ #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Pos                           (0UL)          /*!< TXVLANG (Bit 0)                                       */
+ #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Msk                           (0xffffffffUL) /*!< TXVLANG (Bitfield-Mask: 0xffffffff)                   */
+/* =================================================  Tx_OSize_Frames_Good  ================================================== */
+ #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Pos                          (0UL)          /*!< TXOSIZG (Bit 0)                                       */
+ #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Msk                          (0xffffUL)     /*!< TXOSIZG (Bitfield-Mask: 0xffff)                       */
+/* ===============================================  Rx_Frames_Count_Good_Bad  ================================================ */
+ #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Pos                      (0UL)          /*!< RXFRMGB (Bit 0)                                       */
+ #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Msk                      (0xffffffffUL) /*!< RXFRMGB (Bitfield-Mask: 0xffffffff)                   */
+/* ================================================  Rx_Octet_Count_Good_Bad  ================================================ */
+ #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Pos                       (0UL)          /*!< RXOCTGB (Bit 0)                                       */
+ #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Msk                       (0xffffffffUL) /*!< RXOCTGB (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  Rx_Octet_Count_Good  ================================================== */
+ #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Pos                            (0UL)          /*!< RXOCTG (Bit 0)                                        */
+ #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Msk                            (0xffffffffUL) /*!< RXOCTG (Bitfield-Mask: 0xffffffff)                    */
+/* ===============================================  Rx_Broadcast_Frames_Good  ================================================ */
+ #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Pos                     (0UL)          /*!< RXBCASTG (Bit 0)                                      */
+ #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Msk                     (0xffffffffUL) /*!< RXBCASTG (Bitfield-Mask: 0xffffffff)                  */
+/* ===============================================  Rx_Multicast_Frames_Good  ================================================ */
+ #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Pos                     (0UL)          /*!< RXMCASTG (Bit 0)                                      */
+ #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Msk                     (0xffffffffUL) /*!< RXMCASTG (Bitfield-Mask: 0xffffffff)                  */
+/* ==================================================  Rx_CRC_Error_Frames  ================================================== */
+ #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Pos                          (0UL)          /*!< RXCRCERR (Bit 0)                                      */
+ #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Msk                          (0xffffUL)     /*!< RXCRCERR (Bitfield-Mask: 0xffff)                      */
+/* ===============================================  Rx_Alignment_Error_Frames  =============================================== */
+ #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Pos                   (0UL)          /*!< RXALGNERR (Bit 0)                                     */
+ #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Msk                   (0xffffUL)     /*!< RXALGNERR (Bitfield-Mask: 0xffff)                     */
+/* =================================================  Rx_Runt_Error_Frames  ================================================== */
+ #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Pos                        (0UL)          /*!< RXRUNTERR (Bit 0)                                     */
+ #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Msk                        (0xffffUL)     /*!< RXRUNTERR (Bitfield-Mask: 0xffff)                     */
+/* ================================================  Rx_Jabber_Error_Frames  ================================================= */
+ #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Pos                       (0UL)          /*!< RXJABERR (Bit 0)                                      */
+ #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Msk                       (0xffffUL)     /*!< RXJABERR (Bitfield-Mask: 0xffff)                      */
+/* ===============================================  Rx_Undersize_Frames_Good  ================================================ */
+ #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Pos                   (0UL)          /*!< RXUNDERSZG (Bit 0)                                    */
+ #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Msk                   (0xffffUL)     /*!< RXUNDERSZG (Bitfield-Mask: 0xffff)                    */
+/* ================================================  Rx_Oversize_Frames_Good  ================================================ */
+ #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Pos                     (0UL)          /*!< RXOVERSZG (Bit 0)                                     */
+ #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Msk                     (0xffffUL)     /*!< RXOVERSZG (Bitfield-Mask: 0xffff)                     */
+/* ==============================================  Rx_64Octets_Frames_Good_Bad  ============================================== */
+ #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Pos                 (0UL)          /*!< RX64OCTGB (Bit 0)                                     */
+ #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Msk                 (0xffffffffUL) /*!< RX64OCTGB (Bitfield-Mask: 0xffffffff)             */
+/* ===========================================  Rx_65To127Octets_Frames_Good_Bad  ============================================ */
+ #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Pos        (0UL)          /*!< RX65_127OCTGB (Bit 0)                             */
+ #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Msk        (0xffffffffUL) /*!< RX65_127OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  Rx_128To255Octets_Frames_Good_Bad  =========================================== */
+ #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Pos      (0UL)          /*!< RX128_255OCTGB (Bit 0)                          */
+ #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Msk      (0xffffffffUL) /*!< RX128_255OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  Rx_256To511Octets_Frames_Good_Bad  =========================================== */
+ #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Pos      (0UL)          /*!< RX256_511OCTGB (Bit 0)                          */
+ #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Msk      (0xffffffffUL) /*!< RX256_511OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_512To1023Octets_Frames_Good_Bad  =========================================== */
+ #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Pos    (0UL)          /*!< RX512_1023OCTGB (Bit 0)                       */
+ #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Msk    (0xffffffffUL) /*!< RX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_1024ToMaxOctets_Frames_Good_Bad  =========================================== */
+ #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Pos    (0UL)          /*!< RX1024_MAXOCTGB (Bit 0)                       */
+ #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Msk    (0xffffffffUL) /*!< RX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */
+/* ================================================  Rx_Unicast_Frames_Good  ================================================= */
+ #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Pos                       (0UL)          /*!< RXUCASTG (Bit 0)                                      */
+ #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Msk                       (0xffffffffUL) /*!< RXUCASTG (Bitfield-Mask: 0xffffffff)                  */
+/* ================================================  Rx_Length_Error_Frames  ================================================= */
+ #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Pos                       (0UL)          /*!< RXLENERR (Bit 0)                                      */
+ #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Msk                       (0xffffUL)     /*!< RXLENERR (Bitfield-Mask: 0xffff)                      */
+/* ==============================================  Rx_Out_Of_Range_Type_Frames  ============================================== */
+ #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Pos                (0UL)          /*!< RXOUTOFRNG (Bit 0)                                    */
+ #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Msk                (0xffffUL)     /*!< RXOUTOFRNG (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  Rx_Pause_Frames  ==================================================== */
+ #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Pos                            (0UL)          /*!< RXPAUSEFRM (Bit 0)                                    */
+ #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Msk                            (0xffffUL)     /*!< RXPAUSEFRM (Bitfield-Mask: 0xffff)                    */
+/* ================================================  Rx_FIFO_Overflow_Frames  ================================================ */
+ #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Pos                    (0UL)          /*!< RXFIFOOVFL (Bit 0)                                    */
+ #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Msk                    (0xffffUL)     /*!< RXFIFOOVFL (Bitfield-Mask: 0xffff)                    */
+/* ================================================  Rx_VLAN_Frames_Good_Bad  ================================================ */
+ #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Pos                    (0UL)          /*!< RXVLANFRGB (Bit 0)                                    */
+ #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Msk                    (0xffffffffUL) /*!< RXVLANFRGB (Bitfield-Mask: 0xffffffff)               */
+/* ===============================================  Rx_Watchdog_Error_Frames  ================================================ */
+ #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Pos                     (0UL)          /*!< RXWDGERR (Bit 0)                                      */
+ #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Msk                     (0xffffUL)     /*!< RXWDGERR (Bitfield-Mask: 0xffff)                      */
+/* ================================================  Rx_Receive_Error_Frames  ================================================ */
+ #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Pos                      (0UL)          /*!< RXRCVERR (Bit 0)                                      */
+ #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Msk                      (0xffffUL)     /*!< RXRCVERR (Bitfield-Mask: 0xffff)                      */
+/* ================================================  Rx_Control_Frames_Good  ================================================= */
+ #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Pos                        (0UL)          /*!< RXCTRLG (Bit 0)                                       */
+ #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Msk                        (0xffffffffUL) /*!< RXCTRLG (Bitfield-Mask: 0xffffffff)                   */
+/* ======================================================  GMACTRGSEL  ======================================================= */
+ #define R_GMAC_GMACTRGSEL_TRGSEL_Pos                                     (0UL)          /*!< TRGSEL (Bit 0)                                        */
+ #define R_GMAC_GMACTRGSEL_TRGSEL_Msk                                     (0x3UL)        /*!< TRGSEL (Bitfield-Mask: 0x03)                          */
+/* ====================================================  HASH_TABLE_REG  ===================================================== */
+ #define R_GMAC_HASH_TABLE_REG_HT_Pos                                     (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC_HASH_TABLE_REG_HT_Msk                                     (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  VLAN_Hash_Table_Reg  ================================================== */
+ #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Pos                              (0UL)          /*!< VLHT (Bit 0)                                          */
+ #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Msk                              (0xffffUL)     /*!< VLHT (Bitfield-Mask: 0xffff)                          */
+/* ===================================================  Timestamp_Control  =================================================== */
+ #define R_GMAC_Timestamp_Control_TSENA_Pos                               (0UL)          /*!< TSENA (Bit 0)                                         */
+ #define R_GMAC_Timestamp_Control_TSENA_Msk                               (0x1UL)        /*!< TSENA (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_Timestamp_Control_TSENALL_Pos                             (8UL)          /*!< TSENALL (Bit 8)                                       */
+ #define R_GMAC_Timestamp_Control_TSENALL_Msk                             (0x100UL)      /*!< TSENALL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_Timestamp_Control_TSCTRLSSR_Pos                           (9UL)          /*!< TSCTRLSSR (Bit 9)                                     */
+ #define R_GMAC_Timestamp_Control_TSCTRLSSR_Msk                           (0x200UL)      /*!< TSCTRLSSR (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_Timestamp_Control_TSVER2ENA_Pos                           (10UL)         /*!< TSVER2ENA (Bit 10)                                    */
+ #define R_GMAC_Timestamp_Control_TSVER2ENA_Msk                           (0x400UL)      /*!< TSVER2ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_Timestamp_Control_TSIPENA_Pos                             (11UL)         /*!< TSIPENA (Bit 11)                                      */
+ #define R_GMAC_Timestamp_Control_TSIPENA_Msk                             (0x800UL)      /*!< TSIPENA (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_Timestamp_Control_TSIPV6ENA_Pos                           (12UL)         /*!< TSIPV6ENA (Bit 12)                                    */
+ #define R_GMAC_Timestamp_Control_TSIPV6ENA_Msk                           (0x1000UL)     /*!< TSIPV6ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_Timestamp_Control_TSIPV4ENA_Pos                           (13UL)         /*!< TSIPV4ENA (Bit 13)                                    */
+ #define R_GMAC_Timestamp_Control_TSIPV4ENA_Msk                           (0x2000UL)     /*!< TSIPV4ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_Timestamp_Control_TSEVNTENA_Pos                           (14UL)         /*!< TSEVNTENA (Bit 14)                                    */
+ #define R_GMAC_Timestamp_Control_TSEVNTENA_Msk                           (0x4000UL)     /*!< TSEVNTENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_Timestamp_Control_TSMSTRENA_Pos                           (15UL)         /*!< TSMSTRENA (Bit 15)                                    */
+ #define R_GMAC_Timestamp_Control_TSMSTRENA_Msk                           (0x8000UL)     /*!< TSMSTRENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Pos                          (16UL)         /*!< SNAPTYPSEL (Bit 16)                                   */
+ #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Msk                          (0x30000UL)    /*!< SNAPTYPSEL (Bitfield-Mask: 0x03)                      */
+ #define R_GMAC_Timestamp_Control_TSENMACADDR_Pos                         (18UL)         /*!< TSENMACADDR (Bit 18)                                  */
+ #define R_GMAC_Timestamp_Control_TSENMACADDR_Msk                         (0x40000UL)    /*!< TSENMACADDR (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_Timestamp_Control_ATSFC_Pos                               (24UL)         /*!< ATSFC (Bit 24)                                        */
+ #define R_GMAC_Timestamp_Control_ATSFC_Msk                               (0x1000000UL)  /*!< ATSFC (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_Timestamp_Control_ATSEN0_Pos                              (25UL)         /*!< ATSEN0 (Bit 25)                                       */
+ #define R_GMAC_Timestamp_Control_ATSEN0_Msk                              (0x2000000UL)  /*!< ATSEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_Timestamp_Control_ATSEN1_Pos                              (26UL)         /*!< ATSEN1 (Bit 26)                                       */
+ #define R_GMAC_Timestamp_Control_ATSEN1_Msk                              (0x4000000UL)  /*!< ATSEN1 (Bitfield-Mask: 0x01)                          */
+/* ===================================================  Timestamp_Status  ==================================================== */
+ #define R_GMAC_Timestamp_Status_AUXTSTRIG_Pos                            (2UL)          /*!< AUXTSTRIG (Bit 2)                                     */
+ #define R_GMAC_Timestamp_Status_AUXTSTRIG_Msk                            (0x4UL)        /*!< AUXTSTRIG (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_Timestamp_Status_ATSSTN_Pos                               (16UL)         /*!< ATSSTN (Bit 16)                                       */
+ #define R_GMAC_Timestamp_Status_ATSSTN_Msk                               (0xf0000UL)    /*!< ATSSTN (Bitfield-Mask: 0x0f)                          */
+ #define R_GMAC_Timestamp_Status_ATSSTM_Pos                               (24UL)         /*!< ATSSTM (Bit 24)                                       */
+ #define R_GMAC_Timestamp_Status_ATSSTM_Msk                               (0x1000000UL)  /*!< ATSSTM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_Timestamp_Status_ATSNS_Pos                                (25UL)         /*!< ATSNS (Bit 25)                                        */
+ #define R_GMAC_Timestamp_Status_ATSNS_Msk                                (0x3e000000UL) /*!< ATSNS (Bitfield-Mask: 0x1f)                           */
+/* ============================================  Auxiliary_Timestamp_Nanoseconds  ============================================ */
+ #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Pos               (0UL)          /*!< AUXTSLO (Bit 0)                                       */
+ #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Msk               (0x7fffffffUL) /*!< AUXTSLO (Bitfield-Mask: 0x7fffffff)             */
+/* ==============================================  Auxiliary_Timestamp_Seconds  ============================================== */
+ #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Pos                   (0UL)          /*!< AUXTSHI (Bit 0)                                       */
+ #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Msk                   (0xffffffffUL) /*!< AUXTSHI (Bitfield-Mask: 0xffffffff)                 */
+/* ========================================================  MAR16_H  ======================================================== */
+ #define R_GMAC_MAR16_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR16_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR16_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR16_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR16_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR16_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR16_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR16_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR16_L  ======================================================== */
+ #define R_GMAC_MAR16_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR16_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MAR17_H  ======================================================== */
+ #define R_GMAC_MAR17_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC_MAR17_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC_MAR17_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC_MAR17_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_MAR17_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC_MAR17_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_MAR17_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC_MAR17_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MAR17_L  ======================================================== */
+ #define R_GMAC_MAR17_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC_MAR17_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  Bus_Mode  ======================================================== */
+ #define R_GMAC_Bus_Mode_SWR_Pos                                          (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_GMAC_Bus_Mode_SWR_Msk                                          (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Bus_Mode_DA_Pos                                           (1UL)          /*!< DA (Bit 1)                                            */
+ #define R_GMAC_Bus_Mode_DA_Msk                                           (0x2UL)        /*!< DA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Bus_Mode_DSL_Pos                                          (2UL)          /*!< DSL (Bit 2)                                           */
+ #define R_GMAC_Bus_Mode_DSL_Msk                                          (0x7cUL)       /*!< DSL (Bitfield-Mask: 0x1f)                             */
+ #define R_GMAC_Bus_Mode_ATDS_Pos                                         (7UL)          /*!< ATDS (Bit 7)                                          */
+ #define R_GMAC_Bus_Mode_ATDS_Msk                                         (0x80UL)       /*!< ATDS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_Bus_Mode_PBL_Pos                                          (8UL)          /*!< PBL (Bit 8)                                           */
+ #define R_GMAC_Bus_Mode_PBL_Msk                                          (0x3f00UL)     /*!< PBL (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC_Bus_Mode_PR_Pos                                           (14UL)         /*!< PR (Bit 14)                                           */
+ #define R_GMAC_Bus_Mode_PR_Msk                                           (0xc000UL)     /*!< PR (Bitfield-Mask: 0x03)                              */
+ #define R_GMAC_Bus_Mode_FB_Pos                                           (16UL)         /*!< FB (Bit 16)                                           */
+ #define R_GMAC_Bus_Mode_FB_Msk                                           (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Bus_Mode_RPBL_Pos                                         (17UL)         /*!< RPBL (Bit 17)                                         */
+ #define R_GMAC_Bus_Mode_RPBL_Msk                                         (0x7e0000UL)   /*!< RPBL (Bitfield-Mask: 0x3f)                            */
+ #define R_GMAC_Bus_Mode_USP_Pos                                          (23UL)         /*!< USP (Bit 23)                                          */
+ #define R_GMAC_Bus_Mode_USP_Msk                                          (0x800000UL)   /*!< USP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Bus_Mode_PBLx8_Pos                                        (24UL)         /*!< PBLx8 (Bit 24)                                        */
+ #define R_GMAC_Bus_Mode_PBLx8_Msk                                        (0x1000000UL)  /*!< PBLx8 (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_Bus_Mode_AAL_Pos                                          (25UL)         /*!< AAL (Bit 25)                                          */
+ #define R_GMAC_Bus_Mode_AAL_Msk                                          (0x2000000UL)  /*!< AAL (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Bus_Mode_MB_Pos                                           (26UL)         /*!< MB (Bit 26)                                           */
+ #define R_GMAC_Bus_Mode_MB_Msk                                           (0x4000000UL)  /*!< MB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Bus_Mode_TXPR_Pos                                         (27UL)         /*!< TXPR (Bit 27)                                         */
+ #define R_GMAC_Bus_Mode_TXPR_Msk                                         (0x8000000UL)  /*!< TXPR (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC_Bus_Mode_PRWG_Pos                                         (28UL)         /*!< PRWG (Bit 28)                                         */
+ #define R_GMAC_Bus_Mode_PRWG_Msk                                         (0x30000000UL) /*!< PRWG (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC_Bus_Mode_RIB_Pos                                          (31UL)         /*!< RIB (Bit 31)                                          */
+ #define R_GMAC_Bus_Mode_RIB_Msk                                          (0x80000000UL) /*!< RIB (Bitfield-Mask: 0x01)                             */
+/* =================================================  Transmit_Poll_Demand  ================================================== */
+ #define R_GMAC_Transmit_Poll_Demand_TPD_Pos                              (0UL)          /*!< TPD (Bit 0)                                           */
+ #define R_GMAC_Transmit_Poll_Demand_TPD_Msk                              (0xffffffffUL) /*!< TPD (Bitfield-Mask: 0xffffffff)                       */
+/* ==================================================  Receive_Poll_Demand  ================================================== */
+ #define R_GMAC_Receive_Poll_Demand_RPD_Pos                               (0UL)          /*!< RPD (Bit 0)                                           */
+ #define R_GMAC_Receive_Poll_Demand_RPD_Msk                               (0xffffffffUL) /*!< RPD (Bitfield-Mask: 0xffffffff)                       */
+/* ============================================  Receive_Descriptor_List_Address  ============================================ */
+ #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Pos          (2UL)          /*!< RDESLA_32bit (Bit 2)                                */
+ #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Msk          (0xfffffffcUL) /*!< RDESLA_32bit (Bitfield-Mask: 0x3fffffff)   */
+/* ===========================================  Transmit_Descriptor_List_Address  ============================================ */
+ #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Pos         (2UL)          /*!< TDESLA_32bit (Bit 2)                               */
+ #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Msk         (0xfffffffcUL) /*!< TDESLA_32bit (Bitfield-Mask: 0x3fffffff)  */
+/* ========================================================  Status  ========================================================= */
+ #define R_GMAC_Status_TI_Pos                                             (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC_Status_TI_Msk                                             (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Status_TPS_Pos                                            (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC_Status_TPS_Msk                                            (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_TU_Pos                                             (2UL)          /*!< TU (Bit 2)                                            */
+ #define R_GMAC_Status_TU_Msk                                             (0x4UL)        /*!< TU (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Status_TJT_Pos                                            (3UL)          /*!< TJT (Bit 3)                                           */
+ #define R_GMAC_Status_TJT_Msk                                            (0x8UL)        /*!< TJT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_OVF_Pos                                            (4UL)          /*!< OVF (Bit 4)                                           */
+ #define R_GMAC_Status_OVF_Msk                                            (0x10UL)       /*!< OVF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_UNF_Pos                                            (5UL)          /*!< UNF (Bit 5)                                           */
+ #define R_GMAC_Status_UNF_Msk                                            (0x20UL)       /*!< UNF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_RI_Pos                                             (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC_Status_RI_Msk                                             (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Status_RU_Pos                                             (7UL)          /*!< RU (Bit 7)                                            */
+ #define R_GMAC_Status_RU_Msk                                             (0x80UL)       /*!< RU (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Status_RPS_Pos                                            (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC_Status_RPS_Msk                                            (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_RWT_Pos                                            (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC_Status_RWT_Msk                                            (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_ETI_Pos                                            (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC_Status_ETI_Msk                                            (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_FBI_Pos                                            (13UL)         /*!< FBI (Bit 13)                                          */
+ #define R_GMAC_Status_FBI_Msk                                            (0x2000UL)     /*!< FBI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_ERI_Pos                                            (14UL)         /*!< ERI (Bit 14)                                          */
+ #define R_GMAC_Status_ERI_Msk                                            (0x4000UL)     /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_AIS_Pos                                            (15UL)         /*!< AIS (Bit 15)                                          */
+ #define R_GMAC_Status_AIS_Msk                                            (0x8000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_NIS_Pos                                            (16UL)         /*!< NIS (Bit 16)                                          */
+ #define R_GMAC_Status_NIS_Msk                                            (0x10000UL)    /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_RS_Pos                                             (17UL)         /*!< RS (Bit 17)                                           */
+ #define R_GMAC_Status_RS_Msk                                             (0xe0000UL)    /*!< RS (Bitfield-Mask: 0x07)                              */
+ #define R_GMAC_Status_TS_Pos                                             (20UL)         /*!< TS (Bit 20)                                           */
+ #define R_GMAC_Status_TS_Msk                                             (0x700000UL)   /*!< TS (Bitfield-Mask: 0x07)                              */
+ #define R_GMAC_Status_EB_Pos                                             (23UL)         /*!< EB (Bit 23)                                           */
+ #define R_GMAC_Status_EB_Msk                                             (0x3800000UL)  /*!< EB (Bitfield-Mask: 0x07)                              */
+ #define R_GMAC_Status_GMI_Pos                                            (27UL)         /*!< GMI (Bit 27)                                          */
+ #define R_GMAC_Status_GMI_Msk                                            (0x8000000UL)  /*!< GMI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_GPI_Pos                                            (28UL)         /*!< GPI (Bit 28)                                          */
+ #define R_GMAC_Status_GPI_Msk                                            (0x10000000UL) /*!< GPI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_TTI_Pos                                            (29UL)         /*!< TTI (Bit 29)                                          */
+ #define R_GMAC_Status_TTI_Msk                                            (0x20000000UL) /*!< TTI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Status_GLPII_Pos                                          (30UL)         /*!< GLPII (Bit 30)                                        */
+ #define R_GMAC_Status_GLPII_Msk                                          (0x40000000UL) /*!< GLPII (Bitfield-Mask: 0x01)                           */
+/* ====================================================  Operation_Mode  ===================================================== */
+ #define R_GMAC_Operation_Mode_SR_Pos                                     (1UL)          /*!< SR (Bit 1)                                            */
+ #define R_GMAC_Operation_Mode_SR_Msk                                     (0x2UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Operation_Mode_OSF_Pos                                    (2UL)          /*!< OSF (Bit 2)                                           */
+ #define R_GMAC_Operation_Mode_OSF_Msk                                    (0x4UL)        /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Operation_Mode_RTC_Pos                                    (3UL)          /*!< RTC (Bit 3)                                           */
+ #define R_GMAC_Operation_Mode_RTC_Msk                                    (0x18UL)       /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC_Operation_Mode_DGF_Pos                                    (5UL)          /*!< DGF (Bit 5)                                           */
+ #define R_GMAC_Operation_Mode_DGF_Msk                                    (0x20UL)       /*!< DGF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Operation_Mode_FUF_Pos                                    (6UL)          /*!< FUF (Bit 6)                                           */
+ #define R_GMAC_Operation_Mode_FUF_Msk                                    (0x40UL)       /*!< FUF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Operation_Mode_FEF_Pos                                    (7UL)          /*!< FEF (Bit 7)                                           */
+ #define R_GMAC_Operation_Mode_FEF_Msk                                    (0x80UL)       /*!< FEF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Operation_Mode_EFC_Pos                                    (8UL)          /*!< EFC (Bit 8)                                           */
+ #define R_GMAC_Operation_Mode_EFC_Msk                                    (0x100UL)      /*!< EFC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Operation_Mode_RFA_Pos                                    (9UL)          /*!< RFA (Bit 9)                                           */
+ #define R_GMAC_Operation_Mode_RFA_Msk                                    (0x600UL)      /*!< RFA (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC_Operation_Mode_RFD_Pos                                    (11UL)         /*!< RFD (Bit 11)                                          */
+ #define R_GMAC_Operation_Mode_RFD_Msk                                    (0x1800UL)     /*!< RFD (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC_Operation_Mode_ST_Pos                                     (13UL)         /*!< ST (Bit 13)                                           */
+ #define R_GMAC_Operation_Mode_ST_Msk                                     (0x2000UL)     /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC_Operation_Mode_TTC_Pos                                    (14UL)         /*!< TTC (Bit 14)                                          */
+ #define R_GMAC_Operation_Mode_TTC_Msk                                    (0x1c000UL)    /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC_Operation_Mode_FTF_Pos                                    (20UL)         /*!< FTF (Bit 20)                                          */
+ #define R_GMAC_Operation_Mode_FTF_Msk                                    (0x100000UL)   /*!< FTF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Operation_Mode_TSF_Pos                                    (21UL)         /*!< TSF (Bit 21)                                          */
+ #define R_GMAC_Operation_Mode_TSF_Msk                                    (0x200000UL)   /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Operation_Mode_RSF_Pos                                    (25UL)         /*!< RSF (Bit 25)                                          */
+ #define R_GMAC_Operation_Mode_RSF_Msk                                    (0x2000000UL)  /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Operation_Mode_DT_Pos                                     (26UL)         /*!< DT (Bit 26)                                           */
+ #define R_GMAC_Operation_Mode_DT_Msk                                     (0x4000000UL)  /*!< DT (Bitfield-Mask: 0x01)                              */
+/* ===================================================  Interrupt_Enable  ==================================================== */
+ #define R_GMAC_Interrupt_Enable_TIE_Pos                                  (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC_Interrupt_Enable_TIE_Msk                                  (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_TSE_Pos                                  (1UL)          /*!< TSE (Bit 1)                                           */
+ #define R_GMAC_Interrupt_Enable_TSE_Msk                                  (0x2UL)        /*!< TSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_TUE_Pos                                  (2UL)          /*!< TUE (Bit 2)                                           */
+ #define R_GMAC_Interrupt_Enable_TUE_Msk                                  (0x4UL)        /*!< TUE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_TJE_Pos                                  (3UL)          /*!< TJE (Bit 3)                                           */
+ #define R_GMAC_Interrupt_Enable_TJE_Msk                                  (0x8UL)        /*!< TJE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_OVE_Pos                                  (4UL)          /*!< OVE (Bit 4)                                           */
+ #define R_GMAC_Interrupt_Enable_OVE_Msk                                  (0x10UL)       /*!< OVE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_UNE_Pos                                  (5UL)          /*!< UNE (Bit 5)                                           */
+ #define R_GMAC_Interrupt_Enable_UNE_Msk                                  (0x20UL)       /*!< UNE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_RIE_Pos                                  (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC_Interrupt_Enable_RIE_Msk                                  (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_RUE_Pos                                  (7UL)          /*!< RUE (Bit 7)                                           */
+ #define R_GMAC_Interrupt_Enable_RUE_Msk                                  (0x80UL)       /*!< RUE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_RSE_Pos                                  (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC_Interrupt_Enable_RSE_Msk                                  (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_RWE_Pos                                  (9UL)          /*!< RWE (Bit 9)                                           */
+ #define R_GMAC_Interrupt_Enable_RWE_Msk                                  (0x200UL)      /*!< RWE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_ETE_Pos                                  (10UL)         /*!< ETE (Bit 10)                                          */
+ #define R_GMAC_Interrupt_Enable_ETE_Msk                                  (0x400UL)      /*!< ETE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_FBE_Pos                                  (13UL)         /*!< FBE (Bit 13)                                          */
+ #define R_GMAC_Interrupt_Enable_FBE_Msk                                  (0x2000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_ERE_Pos                                  (14UL)         /*!< ERE (Bit 14)                                          */
+ #define R_GMAC_Interrupt_Enable_ERE_Msk                                  (0x4000UL)     /*!< ERE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_AIE_Pos                                  (15UL)         /*!< AIE (Bit 15)                                          */
+ #define R_GMAC_Interrupt_Enable_AIE_Msk                                  (0x8000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC_Interrupt_Enable_NIE_Pos                                  (16UL)         /*!< NIE (Bit 16)                                          */
+ #define R_GMAC_Interrupt_Enable_NIE_Msk                                  (0x10000UL)    /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* =======================================  Missed_Frame_And_Buffer_Overflow_Counter  ======================================== */
+ #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Pos    (0UL)          /*!< MISFRMCNT (Bit 0)                             */
+ #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Msk    (0xffffUL)     /*!< MISFRMCNT (Bitfield-Mask: 0xffff)        */
+ #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Pos    (16UL)         /*!< MISCNTOVF (Bit 16)                           */
+ #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Msk    (0x10000UL)    /*!< MISCNTOVF (Bitfield-Mask: 0x01)         */
+ #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Pos    (17UL)         /*!< OVFFRMCNT (Bit 17)                           */
+ #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Msk    (0xffe0000UL)  /*!< OVFFRMCNT (Bitfield-Mask: 0x7ff)      */
+ #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Pos    (28UL)         /*!< OVFCNTOVF (Bit 28)                           */
+ #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Msk    (0x10000000UL) /*!< OVFCNTOVF (Bitfield-Mask: 0x01)      */
+/* ===========================================  Receive_Interrupt_Watchdog_Timer  ============================================ */
+ #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Pos                 (0UL)          /*!< RIWT (Bit 0)                                          */
+ #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Msk                 (0xffUL)       /*!< RIWT (Bitfield-Mask: 0xff)                            */
+/* =====================================================  AXI_Bus_Mode  ====================================================== */
+ #define R_GMAC_AXI_Bus_Mode_UNDEF_Pos                                    (0UL)          /*!< UNDEF (Bit 0)                                         */
+ #define R_GMAC_AXI_Bus_Mode_UNDEF_Msk                                    (0x1UL)        /*!< UNDEF (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_AXI_Bus_Mode_BLEN4_Pos                                    (1UL)          /*!< BLEN4 (Bit 1)                                         */
+ #define R_GMAC_AXI_Bus_Mode_BLEN4_Msk                                    (0x2UL)        /*!< BLEN4 (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_AXI_Bus_Mode_BLEN8_Pos                                    (2UL)          /*!< BLEN8 (Bit 2)                                         */
+ #define R_GMAC_AXI_Bus_Mode_BLEN8_Msk                                    (0x4UL)        /*!< BLEN8 (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_AXI_Bus_Mode_BLEN16_Pos                                   (3UL)          /*!< BLEN16 (Bit 3)                                        */
+ #define R_GMAC_AXI_Bus_Mode_BLEN16_Msk                                   (0x8UL)        /*!< BLEN16 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Pos                                  (12UL)         /*!< AXI_AAL (Bit 12)                                      */
+ #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Msk                                  (0x1000UL)     /*!< AXI_AAL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Pos                                  (13UL)         /*!< ONEKBBE (Bit 13)                                      */
+ #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Msk                                  (0x2000UL)     /*!< ONEKBBE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Pos                               (16UL)         /*!< RD_OSR_LMT (Bit 16)                                   */
+ #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Msk                               (0x30000UL)    /*!< RD_OSR_LMT (Bitfield-Mask: 0x03)                      */
+ #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Pos                               (20UL)         /*!< WR_OSR_LMT (Bit 20)                                   */
+ #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Msk                               (0x300000UL)   /*!< WR_OSR_LMT (Bitfield-Mask: 0x03)                      */
+ #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Pos                              (30UL)         /*!< LPI_XIT_FRM (Bit 30)                                  */
+ #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Msk                              (0x40000000UL) /*!< LPI_XIT_FRM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC_AXI_Bus_Mode_EN_LPI_Pos                                   (31UL)         /*!< EN_LPI (Bit 31)                                       */
+ #define R_GMAC_AXI_Bus_Mode_EN_LPI_Msk                                   (0x80000000UL) /*!< EN_LPI (Bitfield-Mask: 0x01)                          */
+/* ======================================================  AXI_Status  ======================================================= */
+ #define R_GMAC_AXI_Status_AXWHSTS_Pos                                    (0UL)          /*!< AXWHSTS (Bit 0)                                       */
+ #define R_GMAC_AXI_Status_AXWHSTS_Msk                                    (0x1UL)        /*!< AXWHSTS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_AXI_Status_AXIRDSTS_Pos                                   (1UL)          /*!< AXIRDSTS (Bit 1)                                      */
+ #define R_GMAC_AXI_Status_AXIRDSTS_Msk                                   (0x2UL)        /*!< AXIRDSTS (Bitfield-Mask: 0x01)                        */
+/* ===========================================  Current_Host_Transmit_Descriptor  ============================================ */
+ #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Pos          (0UL)          /*!< CURTDESAPTR (Bit 0)                                 */
+ #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Msk          (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)    */
+/* ============================================  Current_Host_Receive_Descriptor  ============================================ */
+ #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Pos           (0UL)          /*!< CURRDESAPTR (Bit 0)                                  */
+ #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Msk           (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)     */
+/* =========================================  Current_Host_Transmit_Buffer_Address  ========================================== */
+ #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Pos      (0UL)          /*!< CURTBUFAPTR (Bit 0)                             */
+ #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Msk      (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Current_Host_Receive_Buffer_Address  ========================================== */
+ #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Pos       (0UL)          /*!< CURRBUFAPTR (Bit 0)                              */
+ #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Msk       (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================  HW_Feature  ======================================================= */
+ #define R_GMAC_HW_Feature_MIISEL_Pos                                     (0UL)          /*!< MIISEL (Bit 0)                                        */
+ #define R_GMAC_HW_Feature_MIISEL_Msk                                     (0x1UL)        /*!< MIISEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_HW_Feature_GMIISEL_Pos                                    (1UL)          /*!< GMIISEL (Bit 1)                                       */
+ #define R_GMAC_HW_Feature_GMIISEL_Msk                                    (0x2UL)        /*!< GMIISEL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_HW_Feature_HDSEL_Pos                                      (2UL)          /*!< HDSEL (Bit 2)                                         */
+ #define R_GMAC_HW_Feature_HDSEL_Msk                                      (0x4UL)        /*!< HDSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_HW_Feature_EXTHASHEN_Pos                                  (3UL)          /*!< EXTHASHEN (Bit 3)                                     */
+ #define R_GMAC_HW_Feature_EXTHASHEN_Msk                                  (0x8UL)        /*!< EXTHASHEN (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_HW_Feature_HASHSEL_Pos                                    (4UL)          /*!< HASHSEL (Bit 4)                                       */
+ #define R_GMAC_HW_Feature_HASHSEL_Msk                                    (0x10UL)       /*!< HASHSEL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_HW_Feature_ADDMACADRSEL_Pos                               (5UL)          /*!< ADDMACADRSEL (Bit 5)                                  */
+ #define R_GMAC_HW_Feature_ADDMACADRSEL_Msk                               (0x20UL)       /*!< ADDMACADRSEL (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC_HW_Feature_L3L4FLTREN_Pos                                 (7UL)          /*!< L3L4FLTREN (Bit 7)                                    */
+ #define R_GMAC_HW_Feature_L3L4FLTREN_Msk                                 (0x80UL)       /*!< L3L4FLTREN (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_HW_Feature_SMASEL_Pos                                     (8UL)          /*!< SMASEL (Bit 8)                                        */
+ #define R_GMAC_HW_Feature_SMASEL_Msk                                     (0x100UL)      /*!< SMASEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_HW_Feature_RWKSEL_Pos                                     (9UL)          /*!< RWKSEL (Bit 9)                                        */
+ #define R_GMAC_HW_Feature_RWKSEL_Msk                                     (0x200UL)      /*!< RWKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_HW_Feature_MGKSEL_Pos                                     (10UL)         /*!< MGKSEL (Bit 10)                                       */
+ #define R_GMAC_HW_Feature_MGKSEL_Msk                                     (0x400UL)      /*!< MGKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_HW_Feature_MMCSEL_Pos                                     (11UL)         /*!< MMCSEL (Bit 11)                                       */
+ #define R_GMAC_HW_Feature_MMCSEL_Msk                                     (0x800UL)      /*!< MMCSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_HW_Feature_TSVER1SEL_Pos                                  (12UL)         /*!< TSVER1SEL (Bit 12)                                    */
+ #define R_GMAC_HW_Feature_TSVER1SEL_Msk                                  (0x1000UL)     /*!< TSVER1SEL (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_HW_Feature_TSVER2SEL_Pos                                  (13UL)         /*!< TSVER2SEL (Bit 13)                                    */
+ #define R_GMAC_HW_Feature_TSVER2SEL_Msk                                  (0x2000UL)     /*!< TSVER2SEL (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_HW_Feature_EEESEL_Pos                                     (14UL)         /*!< EEESEL (Bit 14)                                       */
+ #define R_GMAC_HW_Feature_EEESEL_Msk                                     (0x4000UL)     /*!< EEESEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC_HW_Feature_AVSEL_Pos                                      (15UL)         /*!< AVSEL (Bit 15)                                        */
+ #define R_GMAC_HW_Feature_AVSEL_Msk                                      (0x8000UL)     /*!< AVSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC_HW_Feature_TXCOESEL_Pos                                   (16UL)         /*!< TXCOESEL (Bit 16)                                     */
+ #define R_GMAC_HW_Feature_TXCOESEL_Msk                                   (0x10000UL)    /*!< TXCOESEL (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC_HW_Feature_RXTYP1COE_Pos                                  (17UL)         /*!< RXTYP1COE (Bit 17)                                    */
+ #define R_GMAC_HW_Feature_RXTYP1COE_Msk                                  (0x20000UL)    /*!< RXTYP1COE (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_HW_Feature_RXTYP2COE_Pos                                  (18UL)         /*!< RXTYP2COE (Bit 18)                                    */
+ #define R_GMAC_HW_Feature_RXTYP2COE_Msk                                  (0x40000UL)    /*!< RXTYP2COE (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_HW_Feature_RXFIFOSIZE_Pos                                 (19UL)         /*!< RXFIFOSIZE (Bit 19)                                   */
+ #define R_GMAC_HW_Feature_RXFIFOSIZE_Msk                                 (0x80000UL)    /*!< RXFIFOSIZE (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_HW_Feature_RXCHCNT_Pos                                    (20UL)         /*!< RXCHCNT (Bit 20)                                      */
+ #define R_GMAC_HW_Feature_RXCHCNT_Msk                                    (0x300000UL)   /*!< RXCHCNT (Bitfield-Mask: 0x03)                         */
+ #define R_GMAC_HW_Feature_TXCHCNT_Pos                                    (22UL)         /*!< TXCHCNT (Bit 22)                                      */
+ #define R_GMAC_HW_Feature_TXCHCNT_Msk                                    (0xc00000UL)   /*!< TXCHCNT (Bitfield-Mask: 0x03)                         */
+ #define R_GMAC_HW_Feature_ENHDESSEL_Pos                                  (24UL)         /*!< ENHDESSEL (Bit 24)                                    */
+ #define R_GMAC_HW_Feature_ENHDESSEL_Msk                                  (0x1000000UL)  /*!< ENHDESSEL (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_HW_Feature_INTTSEN_Pos                                    (25UL)         /*!< INTTSEN (Bit 25)                                      */
+ #define R_GMAC_HW_Feature_INTTSEN_Msk                                    (0x2000000UL)  /*!< INTTSEN (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC_HW_Feature_FLEXIPPSEN_Pos                                 (26UL)         /*!< FLEXIPPSEN (Bit 26)                                   */
+ #define R_GMAC_HW_Feature_FLEXIPPSEN_Msk                                 (0x4000000UL)  /*!< FLEXIPPSEN (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC_HW_Feature_SAVLANINS_Pos                                  (27UL)         /*!< SAVLANINS (Bit 27)                                    */
+ #define R_GMAC_HW_Feature_SAVLANINS_Msk                                  (0x8000000UL)  /*!< SAVLANINS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC_HW_Feature_ACTPHYIF_Pos                                   (28UL)         /*!< ACTPHYIF (Bit 28)                                     */
+ #define R_GMAC_HW_Feature_ACTPHYIF_Msk                                   (0x70000000UL) /*!< ACTPHYIF (Bitfield-Mask: 0x07)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ETHSS                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PRCMD  ========================================================= */
+/* ========================================================  MODCTRL  ======================================================== */
+ #define R_ETHSS_MODCTRL_SW_MODE_Pos           (0UL)       /*!< SW_MODE (Bit 0)                                       */
+ #define R_ETHSS_MODCTRL_SW_MODE_Msk           (0x7UL)     /*!< SW_MODE (Bitfield-Mask: 0x07)                         */
+/* =======================================================  PTPMCTRL  ======================================================== */
+ #define R_ETHSS_PTPMCTRL_PTP_MODE_Pos         (0UL)       /*!< PTP_MODE (Bit 0)                                      */
+ #define R_ETHSS_PTPMCTRL_PTP_MODE_Msk         (0x1UL)     /*!< PTP_MODE (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Pos     (16UL)      /*!< PTP_PLS_RSTn (Bit 16)                                 */
+ #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Msk     (0x10000UL) /*!< PTP_PLS_RSTn (Bitfield-Mask: 0x01)                    */
+/* ========================================================  PHYLNK  ========================================================= */
+ #define R_ETHSS_PHYLNK_SWLINK_Pos             (0UL)       /*!< SWLINK (Bit 0)                                        */
+ #define R_ETHSS_PHYLNK_SWLINK_Msk             (0x7UL)     /*!< SWLINK (Bitfield-Mask: 0x07)                          */
+ #define R_ETHSS_PHYLNK_CATLNK_Pos             (4UL)       /*!< CATLNK (Bit 4)                                        */
+ #define R_ETHSS_PHYLNK_CATLNK_Msk             (0x70UL)    /*!< CATLNK (Bitfield-Mask: 0x07)                          */
+/* =======================================================  CONVCTRL  ======================================================== */
+ #define R_ETHSS_CONVCTRL_CONV_MODE_Pos        (0UL)       /*!< CONV_MODE (Bit 0)                                     */
+ #define R_ETHSS_CONVCTRL_CONV_MODE_Msk        (0x1fUL)    /*!< CONV_MODE (Bitfield-Mask: 0x1f)                       */
+ #define R_ETHSS_CONVCTRL_FULLD_Pos            (8UL)       /*!< FULLD (Bit 8)                                         */
+ #define R_ETHSS_CONVCTRL_FULLD_Msk            (0x100UL)   /*!< FULLD (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Pos    (9UL)       /*!< RMII_RX_ER_EN (Bit 9)                                 */
+ #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Msk    (0x200UL)   /*!< RMII_RX_ER_EN (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Pos    (10UL)      /*!< RMII_CRS_MODE (Bit 10)                                */
+ #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Msk    (0x400UL)   /*!< RMII_CRS_MODE (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSS_CONVCTRL_RGMII_LINK_Pos       (12UL)      /*!< RGMII_LINK (Bit 12)                                   */
+ #define R_ETHSS_CONVCTRL_RGMII_LINK_Msk       (0x1000UL)  /*!< RGMII_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Pos     (13UL)      /*!< RGMII_DUPLEX (Bit 13)                                 */
+ #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Msk     (0x2000UL)  /*!< RGMII_DUPLEX (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSS_CONVCTRL_RGMII_SPEED_Pos      (14UL)      /*!< RGMII_SPEED (Bit 14)                                  */
+ #define R_ETHSS_CONVCTRL_RGMII_SPEED_Msk      (0xc000UL)  /*!< RGMII_SPEED (Bitfield-Mask: 0x03)                     */
+/* ========================================================  CONVRST  ======================================================== */
+ #define R_ETHSS_CONVRST_PHYIR_Pos             (0UL)       /*!< PHYIR (Bit 0)                                         */
+ #define R_ETHSS_CONVRST_PHYIR_Msk             (0x7UL)     /*!< PHYIR (Bitfield-Mask: 0x07)                           */
+/* ========================================================  SWCTRL  ========================================================= */
+ #define R_ETHSS_SWCTRL_SET10_Pos              (0UL)       /*!< SET10 (Bit 0)                                         */
+ #define R_ETHSS_SWCTRL_SET10_Msk              (0x7UL)     /*!< SET10 (Bitfield-Mask: 0x07)                           */
+ #define R_ETHSS_SWCTRL_SET1000_Pos            (4UL)       /*!< SET1000 (Bit 4)                                       */
+ #define R_ETHSS_SWCTRL_SET1000_Msk            (0x70UL)    /*!< SET1000 (Bitfield-Mask: 0x07)                         */
+ #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Pos       (16UL)      /*!< STRAP_SX_ENB (Bit 16)                                 */
+ #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Msk       (0x10000UL) /*!< STRAP_SX_ENB (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Pos      (17UL)      /*!< STRAP_HUB_ENB (Bit 17)                                */
+ #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Msk      (0x20000UL) /*!< STRAP_HUB_ENB (Bitfield-Mask: 0x01)                   */
+/* ========================================================  SWDUPC  ========================================================= */
+ #define R_ETHSS_SWDUPC_PHY_DUPLEX_Pos         (0UL)       /*!< PHY_DUPLEX (Bit 0)                                    */
+ #define R_ETHSS_SWDUPC_PHY_DUPLEX_Msk         (0x7UL)     /*!< PHY_DUPLEX (Bitfield-Mask: 0x07)                      */
+/* =========================================================  CDCR  ========================================================== */
+ #define R_ETHSS_CDCR_RXDLYEN_Pos              (0UL)       /*!< RXDLYEN (Bit 0)                                       */
+ #define R_ETHSS_CDCR_RXDLYEN_Msk              (0x1UL)     /*!< RXDLYEN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSS_CDCR_TXDLYEN_Pos              (1UL)       /*!< TXDLYEN (Bit 1)                                       */
+ #define R_ETHSS_CDCR_TXDLYEN_Msk              (0x2UL)     /*!< TXDLYEN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSS_CDCR_OSCCLKEN_Pos             (2UL)       /*!< OSCCLKEN (Bit 2)                                      */
+ #define R_ETHSS_CDCR_OSCCLKEN_Msk             (0x4UL)     /*!< OSCCLKEN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSS_CDCR_CLKINEN_Pos              (3UL)       /*!< CLKINEN (Bit 3)                                       */
+ #define R_ETHSS_CDCR_CLKINEN_Msk              (0x8UL)     /*!< CLKINEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  RXFCNT  ========================================================= */
+ #define R_ETHSS_RXFCNT_RXFCNT_Pos             (0UL)       /*!< RXFCNT (Bit 0)                                        */
+ #define R_ETHSS_RXFCNT_RXFCNT_Msk             (0xffffUL)  /*!< RXFCNT (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  TXFCNT  ========================================================= */
+ #define R_ETHSS_TXFCNT_TXFCNT_Pos             (0UL)       /*!< TXFCNT (Bit 0)                                        */
+ #define R_ETHSS_TXFCNT_TXFCNT_Msk             (0xffffUL)  /*!< TXFCNT (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  RXTAPSEL  ======================================================== */
+ #define R_ETHSS_RXTAPSEL_RXTAPSEL_Pos         (0UL)       /*!< RXTAPSEL (Bit 0)                                      */
+ #define R_ETHSS_RXTAPSEL_RXTAPSEL_Msk         (0x7fUL)    /*!< RXTAPSEL (Bitfield-Mask: 0x7f)                        */
+/* =======================================================  TXTAPSEL  ======================================================== */
+ #define R_ETHSS_TXTAPSEL_TXTAPSEL_Pos         (0UL)       /*!< TXTAPSEL (Bit 0)                                      */
+ #define R_ETHSS_TXTAPSEL_TXTAPSEL_Msk         (0x7fUL)    /*!< TXTAPSEL (Bitfield-Mask: 0x7f)                        */
+/* ========================================================  MIIMCR  ========================================================= */
+ #define R_ETHSS_MIIMCR_MIIM2MEN_Pos           (0UL)       /*!< MIIM2MEN (Bit 0)                                      */
+ #define R_ETHSS_MIIMCR_MIIM2MEN_Msk           (0x1UL)     /*!< MIIM2MEN (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ESC_INI                                         ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  ECATOFFADR  ======================================================= */
+ #define R_ESC_INI_ECATOFFADR_OADD_Pos         (0UL)    /*!< OADD (Bit 0)                                          */
+ #define R_ESC_INI_ECATOFFADR_OADD_Msk         (0x1fUL) /*!< OADD (Bitfield-Mask: 0x1f)                            */
+/* =======================================================  ECATOPMOD  ======================================================= */
+ #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Pos    (0UL)    /*!< EEPROMSIZE (Bit 0)                                    */
+ #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Msk    (0x1UL)  /*!< EEPROMSIZE (Bitfield-Mask: 0x01)                      */
+/* =======================================================  ECATDBGC  ======================================================== */
+ #define R_ESC_INI_ECATDBGC_TXSFT0_Pos         (0UL)    /*!< TXSFT0 (Bit 0)                                        */
+ #define R_ESC_INI_ECATDBGC_TXSFT0_Msk         (0x3UL)  /*!< TXSFT0 (Bitfield-Mask: 0x03)                          */
+ #define R_ESC_INI_ECATDBGC_TXSFT1_Pos         (2UL)    /*!< TXSFT1 (Bit 2)                                        */
+ #define R_ESC_INI_ECATDBGC_TXSFT1_Msk         (0xcUL)  /*!< TXSFT1 (Bitfield-Mask: 0x03)                          */
+ #define R_ESC_INI_ECATDBGC_TXSFT2_Pos         (4UL)    /*!< TXSFT2 (Bit 4)                                        */
+ #define R_ESC_INI_ECATDBGC_TXSFT2_Msk         (0x30UL) /*!< TXSFT2 (Bitfield-Mask: 0x03)                          */
+/* ======================================================  ECATTRGSEL  ======================================================= */
+ #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Pos      (0UL)    /*!< TRGSEL0 (Bit 0)                                       */
+ #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Msk      (0x1UL)  /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Pos      (1UL)    /*!< TRGSEL1 (Bit 1)                                       */
+ #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Msk      (0x2UL)  /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                        R_ETHSW_PTP                                        ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  SWPTPOUTSEL  ====================================================== */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Pos     (0UL)    /*!< IOSEL0 (Bit 0)                                        */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Msk     (0x1UL)  /*!< IOSEL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Pos     (1UL)    /*!< IOSEL1 (Bit 1)                                        */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Msk     (0x2UL)  /*!< IOSEL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Pos     (2UL)    /*!< IOSEL2 (Bit 2)                                        */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Msk     (0x4UL)  /*!< IOSEL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Pos     (3UL)    /*!< IOSEL3 (Bit 3)                                        */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Msk     (0x8UL)  /*!< IOSEL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Pos    (4UL)    /*!< EVTSEL0 (Bit 4)                                       */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Msk    (0x10UL) /*!< EVTSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Pos    (5UL)    /*!< EVTSEL1 (Bit 5)                                       */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Msk    (0x20UL) /*!< EVTSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Pos    (6UL)    /*!< EVTSEL2 (Bit 6)                                       */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Msk    (0x40UL) /*!< EVTSEL2 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Pos    (7UL)    /*!< EVTSEL3 (Bit 7)                                       */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Msk    (0x80UL) /*!< EVTSEL3 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ETHSW                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  REVISION  ======================================================== */
+ #define R_ETHSW_REVISION_REV_Pos                                         (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REVISION_REV_Msk                                         (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SCRATCH  ======================================================== */
+ #define R_ETHSW_SCRATCH_SCRATCH_Pos                                      (0UL)          /*!< SCRATCH (Bit 0)                                       */
+ #define R_ETHSW_SCRATCH_SCRATCH_Msk                                      (0xffffffffUL) /*!< SCRATCH (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  PORT_ENA  ======================================================== */
+ #define R_ETHSW_PORT_ENA_TXENA_Pos                                       (0UL)          /*!< TXENA (Bit 0)                                         */
+ #define R_ETHSW_PORT_ENA_TXENA_Msk                                       (0xfUL)        /*!< TXENA (Bitfield-Mask: 0x0f)                           */
+ #define R_ETHSW_PORT_ENA_RXENA_Pos                                       (16UL)         /*!< RXENA (Bit 16)                                        */
+ #define R_ETHSW_PORT_ENA_RXENA_Msk                                       (0xf0000UL)    /*!< RXENA (Bitfield-Mask: 0x0f)                           */
+/* ==================================================  UCAST_DEFAULT_MASK0  ================================================== */
+ #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Pos                          (0UL)          /*!< UCASTDM (Bit 0)                                       */
+ #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Msk                          (0xfUL)        /*!< UCASTDM (Bitfield-Mask: 0x0f)                         */
+/* ======================================================  VLAN_VERIFY  ====================================================== */
+ #define R_ETHSW_VLAN_VERIFY_VLANVERI_Pos                                 (0UL)          /*!< VLANVERI (Bit 0)                                      */
+ #define R_ETHSW_VLAN_VERIFY_VLANVERI_Msk                                 (0xfUL)        /*!< VLANVERI (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_VLAN_VERIFY_VLANDISC_Pos                                 (16UL)         /*!< VLANDISC (Bit 16)                                     */
+ #define R_ETHSW_VLAN_VERIFY_VLANDISC_Msk                                 (0xf0000UL)    /*!< VLANDISC (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  BCAST_DEFAULT_MASK0  ================================================== */
+ #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Pos                          (0UL)          /*!< BCASTDM (Bit 0)                                       */
+ #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Msk                          (0xfUL)        /*!< BCASTDM (Bitfield-Mask: 0x0f)                         */
+/* ==================================================  MCAST_DEFAULT_MASK0  ================================================== */
+ #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Pos                          (0UL)          /*!< MCASTDM (Bit 0)                                       */
+ #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Msk                          (0xfUL)        /*!< MCASTDM (Bitfield-Mask: 0x0f)                         */
+/* ===================================================  INPUT_LEARN_BLOCK  =================================================== */
+ #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Pos                            (0UL)          /*!< BLOCKEN (Bit 0)                                       */
+ #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Msk                            (0xfUL)        /*!< BLOCKEN (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Pos                           (16UL)         /*!< LEARNDIS (Bit 16)                                     */
+ #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Msk                           (0xf0000UL)    /*!< LEARNDIS (Bitfield-Mask: 0x0f)                        */
+/* ======================================================  MGMT_CONFIG  ====================================================== */
+ #define R_ETHSW_MGMT_CONFIG_PORT_Pos                                     (0UL)          /*!< PORT (Bit 0)                                          */
+ #define R_ETHSW_MGMT_CONFIG_PORT_Msk                                     (0xfUL)        /*!< PORT (Bitfield-Mask: 0x0f)                            */
+ #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Pos                                (5UL)          /*!< MSG_TRANS (Bit 5)                                     */
+ #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Msk                                (0x20UL)       /*!< MSG_TRANS (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MGMT_CONFIG_ENABLE_Pos                                   (6UL)          /*!< ENABLE (Bit 6)                                        */
+ #define R_ETHSW_MGMT_CONFIG_ENABLE_Msk                                   (0x40UL)       /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MGMT_CONFIG_DISCARD_Pos                                  (7UL)          /*!< DISCARD (Bit 7)                                       */
+ #define R_ETHSW_MGMT_CONFIG_DISCARD_Msk                                  (0x80UL)       /*!< DISCARD (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Pos                                  (8UL)          /*!< MGMT_EN (Bit 8)                                       */
+ #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Msk                                  (0x100UL)      /*!< MGMT_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Pos                                (9UL)          /*!< MGMT_DISC (Bit 9)                                     */
+ #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Msk                                (0x200UL)      /*!< MGMT_DISC (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MGMT_CONFIG_PRIORITY_Pos                                 (13UL)         /*!< PRIORITY (Bit 13)                                     */
+ #define R_ETHSW_MGMT_CONFIG_PRIORITY_Msk                                 (0xe000UL)     /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_MGMT_CONFIG_PORTMASK_Pos                                 (16UL)         /*!< PORTMASK (Bit 16)                                     */
+ #define R_ETHSW_MGMT_CONFIG_PORTMASK_Msk                                 (0xf0000UL)    /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
+/* ======================================================  MODE_CONFIG  ====================================================== */
+ #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Pos                              (8UL)          /*!< CUT_THRU_EN (Bit 8)                                   */
+ #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Msk                              (0xf00UL)      /*!< CUT_THRU_EN (Bitfield-Mask: 0x0f)                     */
+ #define R_ETHSW_MODE_CONFIG_STATSRESET_Pos                               (31UL)         /*!< STATSRESET (Bit 31)                                   */
+ #define R_ETHSW_MODE_CONFIG_STATSRESET_Msk                               (0x80000000UL) /*!< STATSRESET (Bitfield-Mask: 0x01)                      */
+/* =====================================================  VLAN_IN_MODE  ====================================================== */
+ #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Pos                              (0UL)          /*!< P0VLANINMD (Bit 0)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Msk                              (0x3UL)        /*!< P0VLANINMD (Bitfield-Mask: 0x03)                      */
+ #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Pos                              (2UL)          /*!< P1VLANINMD (Bit 2)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Msk                              (0xcUL)        /*!< P1VLANINMD (Bitfield-Mask: 0x03)                      */
+ #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Pos                              (4UL)          /*!< P2VLANINMD (Bit 4)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Msk                              (0x30UL)       /*!< P2VLANINMD (Bitfield-Mask: 0x03)                      */
+ #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Pos                              (6UL)          /*!< P3VLANINMD (Bit 6)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Msk                              (0xc0UL)       /*!< P3VLANINMD (Bitfield-Mask: 0x03)                      */
+/* =====================================================  VLAN_OUT_MODE  ===================================================== */
+ #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Pos                            (0UL)          /*!< P0VLANOUTMD (Bit 0)                                   */
+ #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Msk                            (0x3UL)        /*!< P0VLANOUTMD (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Pos                            (2UL)          /*!< P1VLANOUTMD (Bit 2)                                   */
+ #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Msk                            (0xcUL)        /*!< P1VLANOUTMD (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Pos                            (4UL)          /*!< P2VLANOUTMD (Bit 4)                                   */
+ #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Msk                            (0x30UL)       /*!< P2VLANOUTMD (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Pos                            (6UL)          /*!< P3VLANOUTMD (Bit 6)                                   */
+ #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Msk                            (0xc0UL)       /*!< P3VLANOUTMD (Bitfield-Mask: 0x03)                     */
+/* ===================================================  VLAN_IN_MODE_ENA  ==================================================== */
+ #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Pos                          (0UL)          /*!< VLANINMDEN (Bit 0)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Msk                          (0xfUL)        /*!< VLANINMDEN (Bitfield-Mask: 0x0f)                      */
+/* ======================================================  VLAN_TAG_ID  ====================================================== */
+ #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Pos                                (0UL)          /*!< VLANTAGID (Bit 0)                                     */
+ #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Msk                                (0xffffUL)     /*!< VLANTAGID (Bitfield-Mask: 0xffff)                     */
+/* ===================================================  BCAST_STORM_LIMIT  =================================================== */
+ #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Pos                              (0UL)          /*!< TMOUT (Bit 0)                                         */
+ #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Msk                              (0xffffUL)     /*!< TMOUT (Bitfield-Mask: 0xffff)                         */
+ #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Pos                         (16UL)         /*!< BCASTLIMIT (Bit 16)                                   */
+ #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Msk                         (0xffff0000UL) /*!< BCASTLIMIT (Bitfield-Mask: 0xffff)                    */
+/* ===================================================  MCAST_STORM_LIMIT  =================================================== */
+ #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Pos                         (16UL)         /*!< MCASTLIMIT (Bit 16)                                   */
+ #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Msk                         (0xffff0000UL) /*!< MCASTLIMIT (Bitfield-Mask: 0xffff)                    */
+/* ====================================================  MIRROR_CONTROL  ===================================================== */
+ #define R_ETHSW_MIRROR_CONTROL_PORT_Pos                                  (0UL)          /*!< PORT (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_CONTROL_PORT_Msk                                  (0x3UL)        /*!< PORT (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Pos                             (4UL)          /*!< MIRROR_EN (Bit 4)                                     */
+ #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Msk                             (0x10UL)       /*!< MIRROR_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Pos                            (5UL)          /*!< ING_MAP_EN (Bit 5)                                    */
+ #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Msk                            (0x20UL)       /*!< ING_MAP_EN (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Pos                             (6UL)          /*!< EG_MAP_EN (Bit 6)                                     */
+ #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Msk                             (0x40UL)       /*!< EG_MAP_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Pos                          (7UL)          /*!< ING_SA_MATCH (Bit 7)                                  */
+ #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Msk                          (0x80UL)       /*!< ING_SA_MATCH (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Pos                          (8UL)          /*!< ING_DA_MATCH (Bit 8)                                  */
+ #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Msk                          (0x100UL)      /*!< ING_DA_MATCH (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Pos                           (9UL)          /*!< EG_SA_MATCH (Bit 9)                                   */
+ #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Msk                           (0x200UL)      /*!< EG_SA_MATCH (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Pos                           (10UL)         /*!< EG_DA_MATCH (Bit 10)                                  */
+ #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Msk                           (0x400UL)      /*!< EG_DA_MATCH (Bitfield-Mask: 0x01)                     */
+/* =====================================================  MIRROR_EG_MAP  ===================================================== */
+ #define R_ETHSW_MIRROR_EG_MAP_EMAP_Pos                                   (0UL)          /*!< EMAP (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_EG_MAP_EMAP_Msk                                   (0xfUL)        /*!< EMAP (Bitfield-Mask: 0x0f)                            */
+/* ====================================================  MIRROR_ING_MAP  ===================================================== */
+ #define R_ETHSW_MIRROR_ING_MAP_IMAP_Pos                                  (0UL)          /*!< IMAP (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ING_MAP_IMAP_Msk                                  (0xfUL)        /*!< IMAP (Bitfield-Mask: 0x0f)                            */
+/* =====================================================  MIRROR_ISRC_0  ===================================================== */
+ #define R_ETHSW_MIRROR_ISRC_0_ISRC_Pos                                   (0UL)          /*!< ISRC (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ISRC_0_ISRC_Msk                                   (0xffffffffUL) /*!< ISRC (Bitfield-Mask: 0xffffffff)                      */
+/* =====================================================  MIRROR_ISRC_1  ===================================================== */
+ #define R_ETHSW_MIRROR_ISRC_1_ISRC_Pos                                   (0UL)          /*!< ISRC (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ISRC_1_ISRC_Msk                                   (0xffffUL)     /*!< ISRC (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  MIRROR_IDST_0  ===================================================== */
+ #define R_ETHSW_MIRROR_IDST_0_IDST_Pos                                   (0UL)          /*!< IDST (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_IDST_0_IDST_Msk                                   (0xffffffffUL) /*!< IDST (Bitfield-Mask: 0xffffffff)                      */
+/* =====================================================  MIRROR_IDST_1  ===================================================== */
+ #define R_ETHSW_MIRROR_IDST_1_IDST_Pos                                   (0UL)          /*!< IDST (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_IDST_1_IDST_Msk                                   (0xffffUL)     /*!< IDST (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  MIRROR_ESRC_0  ===================================================== */
+ #define R_ETHSW_MIRROR_ESRC_0_ESRC_Pos                                   (0UL)          /*!< ESRC (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ESRC_0_ESRC_Msk                                   (0xffffffffUL) /*!< ESRC (Bitfield-Mask: 0xffffffff)                      */
+/* =====================================================  MIRROR_ESRC_1  ===================================================== */
+ #define R_ETHSW_MIRROR_ESRC_1_ESRC_Pos                                   (0UL)          /*!< ESRC (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ESRC_1_ESRC_Msk                                   (0xffffUL)     /*!< ESRC (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  MIRROR_EDST_0  ===================================================== */
+ #define R_ETHSW_MIRROR_EDST_0_EDST_Pos                                   (0UL)          /*!< EDST (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_EDST_0_EDST_Msk                                   (0xffffffffUL) /*!< EDST (Bitfield-Mask: 0xffffffff)                      */
+/* =====================================================  MIRROR_EDST_1  ===================================================== */
+ #define R_ETHSW_MIRROR_EDST_1_EDST_Pos                                   (0UL)          /*!< EDST (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_EDST_1_EDST_Msk                                   (0xffffUL)     /*!< EDST (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  MIRROR_CNT  ======================================================= */
+ #define R_ETHSW_MIRROR_CNT_CNT_Pos                                       (0UL)          /*!< CNT (Bit 0)                                           */
+ #define R_ETHSW_MIRROR_CNT_CNT_Msk                                       (0xffUL)       /*!< CNT (Bitfield-Mask: 0xff)                             */
+/* ==================================================  UCAST_DEFAULT_MASK1  ================================================== */
+ #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Pos                         (0UL)          /*!< UCASTDM1 (Bit 0)                                      */
+ #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Msk                         (0xfUL)        /*!< UCASTDM1 (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  BCAST_DEFAULT_MASK1  ================================================== */
+ #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Pos                         (0UL)          /*!< BCASTDM1 (Bit 0)                                      */
+ #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Msk                         (0xfUL)        /*!< BCASTDM1 (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  MCAST_DEFAULT_MASK1  ================================================== */
+ #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Pos                         (0UL)          /*!< MCASTDM1 (Bit 0)                                      */
+ #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Msk                         (0xfUL)        /*!< MCASTDM1 (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  PORT_XCAST_MASK_SEL  ================================================== */
+ #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Pos                             (0UL)          /*!< MSEL (Bit 0)                                          */
+ #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Msk                             (0xfUL)        /*!< MSEL (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  QMGR_ST_MINCELLS  ==================================================== */
+ #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Pos                          (0UL)          /*!< STMINCELLS (Bit 0)                                    */
+ #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Msk                          (0x7ffUL)      /*!< STMINCELLS (Bitfield-Mask: 0x7ff)                     */
+/* =====================================================  QMGR_RED_MIN4  ===================================================== */
+ #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Pos                          (0UL)          /*!< CFGRED_MINTH4 (Bit 0)                                 */
+ #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Msk                          (0xffffffffUL) /*!< CFGRED_MINTH4 (Bitfield-Mask: 0xffffffff)             */
+/* =====================================================  QMGR_RED_MAX4  ===================================================== */
+ #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Pos                          (0UL)          /*!< CFGRED_MAXTH4 (Bit 0)                                 */
+ #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Msk                          (0xffffffffUL) /*!< CFGRED_MAXTH4 (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  QMGR_RED_CONFIG  ==================================================== */
+ #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Pos                         (0UL)          /*!< QUEUE_RED_EN (Bit 0)                                  */
+ #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Msk                         (0xfUL)        /*!< QUEUE_RED_EN (Bitfield-Mask: 0x0f)                    */
+ #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Pos                         (8UL)          /*!< GACTIVITY_EN (Bit 8)                                  */
+ #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Msk                         (0x100UL)      /*!< GACTIVITY_EN (Bitfield-Mask: 0x01)                    */
+/* ======================================================  IMC_STATUS  ======================================================= */
+ #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Pos                           (0UL)          /*!< CELLS_AVAILABLE (Bit 0)                               */
+ #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Msk                           (0xffffffUL)   /*!< CELLS_AVAILABLE (Bitfield-Mask: 0xffffff)             */
+ #define R_ETHSW_IMC_STATUS_CF_ERR_Pos                                    (24UL)         /*!< CF_ERR (Bit 24)                                       */
+ #define R_ETHSW_IMC_STATUS_CF_ERR_Msk                                    (0x1000000UL)  /*!< CF_ERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_IMC_STATUS_DE_ERR_Pos                                    (25UL)         /*!< DE_ERR (Bit 25)                                       */
+ #define R_ETHSW_IMC_STATUS_DE_ERR_Msk                                    (0x2000000UL)  /*!< DE_ERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_IMC_STATUS_DE_INIT_Pos                                   (26UL)         /*!< DE_INIT (Bit 26)                                      */
+ #define R_ETHSW_IMC_STATUS_DE_INIT_Msk                                   (0x4000000UL)  /*!< DE_INIT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_IMC_STATUS_MEM_FULL_Pos                                  (27UL)         /*!< MEM_FULL (Bit 27)                                     */
+ #define R_ETHSW_IMC_STATUS_MEM_FULL_Msk                                  (0x8000000UL)  /*!< MEM_FULL (Bitfield-Mask: 0x01)                        */
+/* =====================================================  IMC_ERR_FULL  ====================================================== */
+ #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Pos                            (0UL)          /*!< IPC_ERR_FULL (Bit 0)                                  */
+ #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Msk                            (0xfUL)        /*!< IPC_ERR_FULL (Bitfield-Mask: 0x0f)                    */
+ #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Pos                           (16UL)         /*!< IPC_ERR_TRUNC (Bit 16)                                */
+ #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Msk                           (0xf0000UL)    /*!< IPC_ERR_TRUNC (Bitfield-Mask: 0x0f)                   */
+/* =====================================================  IMC_ERR_IFACE  ===================================================== */
+ #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Pos                          (0UL)          /*!< IPC_ERR_IFACE (Bit 0)                                 */
+ #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Msk                          (0xfUL)        /*!< IPC_ERR_IFACE (Bitfield-Mask: 0x0f)                   */
+ #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Pos                               (16UL)         /*!< WBUF_OVF (Bit 16)                                     */
+ #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Msk                               (0xf0000UL)    /*!< WBUF_OVF (Bitfield-Mask: 0x0f)                        */
+/* ====================================================  IMC_ERR_QOFLOW  ===================================================== */
+ #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Pos                                (0UL)          /*!< OP_ERR (Bit 0)                                        */
+ #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Msk                                (0xfUL)        /*!< OP_ERR (Bitfield-Mask: 0x0f)                          */
+/* ======================================================  IMC_CONFIG  ======================================================= */
+ #define R_ETHSW_IMC_CONFIG_WFQ_EN_Pos                                    (0UL)          /*!< WFQ_EN (Bit 0)                                        */
+ #define R_ETHSW_IMC_CONFIG_WFQ_EN_Msk                                    (0x1UL)        /*!< WFQ_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_IMC_CONFIG_RSV_ENA_Pos                                   (1UL)          /*!< RSV_ENA (Bit 1)                                       */
+ #define R_ETHSW_IMC_CONFIG_RSV_ENA_Msk                                   (0x2UL)        /*!< RSV_ENA (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Pos                           (2UL)          /*!< SPEED_HIPRI_THR (Bit 2)                               */
+ #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Msk                           (0x1cUL)       /*!< SPEED_HIPRI_THR (Bitfield-Mask: 0x07)                 */
+ #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Pos                             (5UL)          /*!< CTFL_EMPTY_MD (Bit 5)                                 */
+ #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Msk                             (0x20UL)       /*!< CTFL_EMPTY_MD (Bitfield-Mask: 0x01)                   */
+/* =====================================================  IMC_ERR_ALLOC  ===================================================== */
+ #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Pos                              (0UL)          /*!< DISC_FULL (Bit 0)                                     */
+ #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Msk                              (0xfUL)        /*!< DISC_FULL (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Pos                              (16UL)         /*!< DISC_LATE (Bit 16)                                    */
+ #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Msk                              (0xf0000UL)    /*!< DISC_LATE (Bitfield-Mask: 0x0f)                       */
+/* =======================================================  GPARSER0  ======================================================== */
+ #define R_ETHSW_GPARSER0_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER0_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER0_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER0_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER0_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER0_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER0_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER0_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER0_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER0_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER0_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER0_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER0_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER0_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER0_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER0_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER0_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER0_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER0_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER0_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER1  ======================================================== */
+ #define R_ETHSW_GPARSER1_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER1_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER1_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER1_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER1_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER1_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER1_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER1_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER1_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER1_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER1_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER1_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER1_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER1_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER1_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER1_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER1_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER1_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER1_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER1_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER2  ======================================================== */
+ #define R_ETHSW_GPARSER2_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER2_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER2_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER2_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER2_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER2_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER2_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER2_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER2_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER2_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER2_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER2_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER2_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER2_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER2_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER2_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER2_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER2_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER2_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER2_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER3  ======================================================== */
+ #define R_ETHSW_GPARSER3_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER3_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER3_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER3_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER3_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER3_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER3_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER3_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER3_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER3_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER3_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER3_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER3_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER3_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER3_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER3_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER3_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER3_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER3_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER3_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* ========================================================  GARITH0  ======================================================== */
+ #define R_ETHSW_GARITH0_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH0_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH0_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH0_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH0_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH0_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH0_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH0_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH0_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH0_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH0_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH0_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH0_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH0_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH0_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH0_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH1  ======================================================== */
+ #define R_ETHSW_GARITH1_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH1_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH1_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH1_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH1_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH1_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH1_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH1_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH1_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH1_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH1_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH1_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH1_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH1_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH1_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH1_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH2  ======================================================== */
+ #define R_ETHSW_GARITH2_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH2_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH2_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH2_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH2_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH2_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH2_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH2_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH2_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH2_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH2_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH2_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH2_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH2_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH2_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH2_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH3  ======================================================== */
+ #define R_ETHSW_GARITH3_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH3_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH3_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH3_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH3_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH3_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH3_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH3_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH3_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH3_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH3_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH3_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH3_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH3_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH3_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH3_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* =======================================================  GPARSER4  ======================================================== */
+ #define R_ETHSW_GPARSER4_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER4_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER4_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER4_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER4_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER4_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER4_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER4_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER4_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER4_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER4_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER4_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER4_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER4_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER4_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER4_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER4_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER4_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER4_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER4_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER5  ======================================================== */
+ #define R_ETHSW_GPARSER5_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER5_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER5_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER5_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER5_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER5_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER5_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER5_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER5_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER5_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER5_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER5_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER5_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER5_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER5_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER5_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER5_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER5_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER5_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER5_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER6  ======================================================== */
+ #define R_ETHSW_GPARSER6_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER6_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER6_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER6_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER6_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER6_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER6_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER6_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER6_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER6_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER6_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER6_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER6_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER6_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER6_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER6_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER6_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER6_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER6_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER6_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER7  ======================================================== */
+ #define R_ETHSW_GPARSER7_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER7_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER7_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER7_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER7_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER7_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER7_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER7_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER7_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER7_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER7_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER7_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER7_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER7_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER7_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER7_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER7_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER7_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER7_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER7_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* ========================================================  GARITH4  ======================================================== */
+ #define R_ETHSW_GARITH4_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH4_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH4_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH4_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH4_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH4_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH4_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH4_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH4_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH4_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH4_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH4_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH4_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH4_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH4_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH4_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH5  ======================================================== */
+ #define R_ETHSW_GARITH5_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH5_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH5_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH5_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH5_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH5_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH5_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH5_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH5_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH5_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH5_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH5_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH5_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH5_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH5_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH5_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH6  ======================================================== */
+ #define R_ETHSW_GARITH6_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH6_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH6_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH6_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH6_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH6_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH6_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH6_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH6_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH6_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH6_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH6_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH6_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH6_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH6_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH6_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH7  ======================================================== */
+ #define R_ETHSW_GARITH7_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH7_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH7_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH7_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH7_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH7_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH7_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH7_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH7_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH7_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH7_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH7_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH7_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH7_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH7_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH7_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* =====================================================  VLAN_PRIORITY  ===================================================== */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Pos                              (0UL)          /*!< PRIORITY0 (Bit 0)                                     */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Msk                              (0x7UL)        /*!< PRIORITY0 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Pos                              (3UL)          /*!< PRIORITY1 (Bit 3)                                     */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Msk                              (0x38UL)       /*!< PRIORITY1 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Pos                              (6UL)          /*!< PRIORITY2 (Bit 6)                                     */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Msk                              (0x1c0UL)      /*!< PRIORITY2 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Pos                              (9UL)          /*!< PRIORITY3 (Bit 9)                                     */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Msk                              (0xe00UL)      /*!< PRIORITY3 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Pos                              (12UL)         /*!< PRIORITY4 (Bit 12)                                    */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Msk                              (0x7000UL)     /*!< PRIORITY4 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Pos                              (15UL)         /*!< PRIORITY5 (Bit 15)                                    */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Msk                              (0x38000UL)    /*!< PRIORITY5 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Pos                              (18UL)         /*!< PRIORITY6 (Bit 18)                                    */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Msk                              (0x1c0000UL)   /*!< PRIORITY6 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Pos                              (21UL)         /*!< PRIORITY7 (Bit 21)                                    */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Msk                              (0xe00000UL)   /*!< PRIORITY7 (Bitfield-Mask: 0x07)                       */
+/* ======================================================  IP_PRIORITY  ====================================================== */
+ #define R_ETHSW_IP_PRIORITY_ADDRESS_Pos                                  (0UL)          /*!< ADDRESS (Bit 0)                                       */
+ #define R_ETHSW_IP_PRIORITY_ADDRESS_Msk                                  (0xffUL)       /*!< ADDRESS (Bitfield-Mask: 0xff)                         */
+ #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Pos                               (8UL)          /*!< IPV6SELECT (Bit 8)                                    */
+ #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Msk                               (0x100UL)      /*!< IPV6SELECT (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_IP_PRIORITY_PRIORITY_Pos                                 (9UL)          /*!< PRIORITY (Bit 9)                                      */
+ #define R_ETHSW_IP_PRIORITY_PRIORITY_Msk                                 (0xe00UL)      /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_IP_PRIORITY_READ_Pos                                     (31UL)         /*!< READ (Bit 31)                                         */
+ #define R_ETHSW_IP_PRIORITY_READ_Msk                                     (0x80000000UL) /*!< READ (Bitfield-Mask: 0x01)                            */
+/* =====================================================  PRIORITY_CFG  ====================================================== */
+ #define R_ETHSW_PRIORITY_CFG_VLANEN_Pos                                  (0UL)          /*!< VLANEN (Bit 0)                                        */
+ #define R_ETHSW_PRIORITY_CFG_VLANEN_Msk                                  (0x1UL)        /*!< VLANEN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PRIORITY_CFG_IPEN_Pos                                    (1UL)          /*!< IPEN (Bit 1)                                          */
+ #define R_ETHSW_PRIORITY_CFG_IPEN_Msk                                    (0x2UL)        /*!< IPEN (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_PRIORITY_CFG_MACEN_Pos                                   (2UL)          /*!< MACEN (Bit 2)                                         */
+ #define R_ETHSW_PRIORITY_CFG_MACEN_Msk                                   (0x4UL)        /*!< MACEN (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Pos                                 (3UL)          /*!< TYPE_EN (Bit 3)                                       */
+ #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Msk                                 (0x8UL)        /*!< TYPE_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Pos                              (4UL)          /*!< DEFAULTPRI (Bit 4)                                    */
+ #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Msk                              (0x70UL)       /*!< DEFAULTPRI (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_DIS_Pos                           (7UL)          /*!< PCP_REMAP_DIS (Bit 7)                                 */
+ #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_DIS_Msk                           (0x80UL)       /*!< PCP_REMAP_DIS (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_Pos                               (8UL)          /*!< PCP_REMAP (Bit 8)                                     */
+ #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_Msk                               (0xffffff00UL) /*!< PCP_REMAP (Bitfield-Mask: 0xffffff)                   */
+/* ====================================================  PRIORITY_TYPE1  ===================================================== */
+ #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Pos                               (0UL)          /*!< TYPEVAL (Bit 0)                                       */
+ #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Msk                               (0xffffUL)     /*!< TYPEVAL (Bitfield-Mask: 0xffff)                       */
+ #define R_ETHSW_PRIORITY_TYPE1_VALID_Pos                                 (16UL)         /*!< VALID (Bit 16)                                        */
+ #define R_ETHSW_PRIORITY_TYPE1_VALID_Msk                                 (0x10000UL)    /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Pos                              (17UL)         /*!< PRIORITY (Bit 17)                                     */
+ #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Msk                              (0xe0000UL)    /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+/* ====================================================  PRIORITY_TYPE2  ===================================================== */
+ #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Pos                               (0UL)          /*!< TYPEVAL (Bit 0)                                       */
+ #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Msk                               (0xffffUL)     /*!< TYPEVAL (Bitfield-Mask: 0xffff)                       */
+ #define R_ETHSW_PRIORITY_TYPE2_VALID_Pos                                 (16UL)         /*!< VALID (Bit 16)                                        */
+ #define R_ETHSW_PRIORITY_TYPE2_VALID_Msk                                 (0x10000UL)    /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Pos                              (17UL)         /*!< PRIORITY (Bit 17)                                     */
+ #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Msk                              (0xe0000UL)    /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+/* ======================================================  SRCFLT_ENA  ======================================================= */
+ #define R_ETHSW_SRCFLT_ENA_SRCENA_Pos                                    (0UL)          /*!< SRCENA (Bit 0)                                        */
+ #define R_ETHSW_SRCFLT_ENA_SRCENA_Msk                                    (0x7UL)        /*!< SRCENA (Bitfield-Mask: 0x07)                          */
+ #define R_ETHSW_SRCFLT_ENA_DSTENA_Pos                                    (16UL)         /*!< DSTENA (Bit 16)                                       */
+ #define R_ETHSW_SRCFLT_ENA_DSTENA_Msk                                    (0xf0000UL)    /*!< DSTENA (Bitfield-Mask: 0x0f)                          */
+/* ====================================================  SRCFLT_CONTROL  ===================================================== */
+ #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Pos                              (0UL)          /*!< MGMT_FWD (Bit 0)                                      */
+ #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Msk                              (0x1UL)        /*!< MGMT_FWD (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Pos                          (1UL)          /*!< WATCHDOG_ENA (Bit 1)                                  */
+ #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Msk                          (0x2UL)        /*!< WATCHDOG_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Pos                         (16UL)         /*!< WATCHDOG_TIME (Bit 16)                                */
+ #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Msk                         (0xffff0000UL) /*!< WATCHDOG_TIME (Bitfield-Mask: 0xffff)                 */
+/* ===================================================  SRCFLT_MACADDR_LO  =================================================== */
+ #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Pos                     (0UL)          /*!< SRCFLT_MACADDR (Bit 0)                                */
+ #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Msk                     (0xffffffffUL) /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  SRCFLT_MACADDR_HI  =================================================== */
+ #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Pos                     (0UL)          /*!< SRCFLT_MACADDR (Bit 0)                                */
+ #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Msk                     (0xffffUL)     /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffff)                */
+ #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Pos                               (16UL)         /*!< MASK (Bit 16)                                         */
+ #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Msk                               (0xffff0000UL) /*!< MASK (Bitfield-Mask: 0xffff)                          */
+/* ====================================================  PHY_FILTER_CFG  ===================================================== */
+ #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Pos                       (0UL)          /*!< FILTER_DURATION (Bit 0)                               */
+ #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Msk                       (0x1ffUL)      /*!< FILTER_DURATION (Bitfield-Mask: 0x1ff)                */
+ #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Pos                                (16UL)         /*!< FLT_EN (Bit 16)                                       */
+ #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Msk                                (0x70000UL)    /*!< FLT_EN (Bitfield-Mask: 0x07)                          */
+/* ====================================================  SYSTEM_TAGINFO  ===================================================== */
+ #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Pos                           (0UL)          /*!< SYSVLANINFO (Bit 0)                                   */
+ #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Msk                           (0xffffUL)     /*!< SYSVLANINFO (Bitfield-Mask: 0xffff)                   */
+/* =======================================================  AUTH_PORT  ======================================================= */
+ #define R_ETHSW_AUTH_PORT_AUTH_Pos                                       (0UL)          /*!< AUTH (Bit 0)                                          */
+ #define R_ETHSW_AUTH_PORT_AUTH_Msk                                       (0x1UL)        /*!< AUTH (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Pos                                  (1UL)          /*!< CTRL_BOTH (Bit 1)                                     */
+ #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Msk                                  (0x2UL)        /*!< CTRL_BOTH (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_AUTH_PORT_EAPOL_EN_Pos                                   (2UL)          /*!< EAPOL_EN (Bit 2)                                      */
+ #define R_ETHSW_AUTH_PORT_EAPOL_EN_Msk                                   (0x4UL)        /*!< EAPOL_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_AUTH_PORT_GUEST_EN_Pos                                   (3UL)          /*!< GUEST_EN (Bit 3)                                      */
+ #define R_ETHSW_AUTH_PORT_GUEST_EN_Msk                                   (0x8UL)        /*!< GUEST_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_AUTH_PORT_BPDU_EN_Pos                                    (4UL)          /*!< BPDU_EN (Bit 4)                                       */
+ #define R_ETHSW_AUTH_PORT_BPDU_EN_Msk                                    (0x10UL)       /*!< BPDU_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Pos                                (5UL)          /*!< EAPOL_UC_EN (Bit 5)                                   */
+ #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Msk                                (0x20UL)       /*!< EAPOL_UC_EN (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Pos                                (11UL)         /*!< ACHG_UNAUTH (Bit 11)                                  */
+ #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Msk                                (0x800UL)      /*!< ACHG_UNAUTH (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Pos                                 (12UL)         /*!< EAPOL_PNUM (Bit 12)                                   */
+ #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Msk                                 (0xf000UL)     /*!< EAPOL_PNUM (Bitfield-Mask: 0x0f)                      */
+ #define R_ETHSW_AUTH_PORT_GUEST_MASK_Pos                                 (16UL)         /*!< GUEST_MASK (Bit 16)                                   */
+ #define R_ETHSW_AUTH_PORT_GUEST_MASK_Msk                                 (0xf0000UL)    /*!< GUEST_MASK (Bitfield-Mask: 0x0f)                      */
+/* ====================================================  VLAN_RES_TABLE  ===================================================== */
+ #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos                              (0UL)          /*!< PORTMASK (Bit 0)                                      */
+ #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk                              (0xfUL)        /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_VLAN_RES_TABLE_VLANID_Pos                                (4UL)          /*!< VLANID (Bit 4)                                        */
+ #define R_ETHSW_VLAN_RES_TABLE_VLANID_Msk                                (0xfff0UL)     /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Pos                             (28UL)         /*!< RD_TAGMSK (Bit 28)                                    */
+ #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Msk                             (0x10000000UL) /*!< RD_TAGMSK (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Pos                             (29UL)         /*!< WT_TAGMSK (Bit 29)                                    */
+ #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Msk                             (0x20000000UL) /*!< WT_TAGMSK (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Pos                             (30UL)         /*!< WT_PRTMSK (Bit 30)                                    */
+ #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Msk                             (0x40000000UL) /*!< WT_PRTMSK (Bitfield-Mask: 0x01)                       */
+/* ======================================================  TOTAL_DISC  ======================================================= */
+ #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Pos                                (0UL)          /*!< TOTAL_DISC (Bit 0)                                    */
+ #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Msk                                (0xffffffffUL) /*!< TOTAL_DISC (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  TOTAL_BYT_DISC  ===================================================== */
+ #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Pos                        (0UL)          /*!< TOTAL_BYT_DISC (Bit 0)                                */
+ #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Msk                        (0xffffffffUL) /*!< TOTAL_BYT_DISC (Bitfield-Mask: 0xffffffff)            */
+/* =======================================================  TOTAL_FRM  ======================================================= */
+ #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Pos                                  (0UL)          /*!< TOTAL_FRM (Bit 0)                                     */
+ #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Msk                                  (0xffffffffUL) /*!< TOTAL_FRM (Bitfield-Mask: 0xffffffff)                 */
+/* =====================================================  TOTAL_BYT_FRM  ===================================================== */
+ #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Pos                          (0UL)          /*!< TOTAL_BYT_FRM (Bit 0)                                 */
+ #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Msk                          (0xffffffffUL) /*!< TOTAL_BYT_FRM (Bitfield-Mask: 0xffffffff)             */
+/* =====================================================  IALK_CONTROL  ====================================================== */
+ #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Pos                             (0UL)          /*!< IA_LKUP_ENA (Bit 0)                                   */
+ #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Msk                             (0xfUL)        /*!< IA_LKUP_ENA (Bitfield-Mask: 0x0f)                     */
+ #define R_ETHSW_IALK_CONTROL_CT_ENA_Pos                                  (16UL)         /*!< CT_ENA (Bit 16)                                       */
+ #define R_ETHSW_IALK_CONTROL_CT_ENA_Msk                                  (0xf0000UL)    /*!< CT_ENA (Bitfield-Mask: 0x0f)                          */
+/* =======================================================  IALK_OUI  ======================================================== */
+ #define R_ETHSW_IALK_OUI_IALK_OUI_Pos                                    (0UL)          /*!< IALK_OUI (Bit 0)                                      */
+ #define R_ETHSW_IALK_OUI_IALK_OUI_Msk                                    (0xffffffUL)   /*!< IALK_OUI (Bitfield-Mask: 0xffffff)                    */
+/* ======================================================  IALK_ID_MIN  ====================================================== */
+ #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Pos                              (0UL)          /*!< IALK_ID_MIN (Bit 0)                                   */
+ #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Msk                              (0xffffffUL)   /*!< IALK_ID_MIN (Bitfield-Mask: 0xffffff)                 */
+/* ======================================================  IALK_ID_MAX  ====================================================== */
+ #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Pos                              (0UL)          /*!< IALK_ID_MAX (Bit 0)                                   */
+ #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Msk                              (0xffffffUL)   /*!< IALK_ID_MAX (Bitfield-Mask: 0xffffff)                 */
+/* ======================================================  IALK_ID_SUB  ====================================================== */
+ #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Pos                              (0UL)          /*!< IALK_ID_SUB (Bit 0)                                   */
+ #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Msk                              (0xffffffUL)   /*!< IALK_ID_SUB (Bitfield-Mask: 0xffffff)                 */
+/* ====================================================  IALK_ID_CONFIG  ===================================================== */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Pos                        (0UL)          /*!< INVLD_ID_FLOOD (Bit 0)                                */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Msk                        (0x1UL)        /*!< INVLD_ID_FLOOD (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Pos                      (1UL)          /*!< INVLD_ID_LRN_ENA (Bit 1)                              */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Msk                      (0x2UL)        /*!< INVLD_ID_LRN_ENA (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Pos                         (4UL)          /*!< INVLD_ID_PRIO (Bit 4)                                 */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Msk                         (0x70UL)       /*!< INVLD_ID_PRIO (Bitfield-Mask: 0x07)                   */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Pos                     (7UL)          /*!< INVLD_ID_PRIO_VLD (Bit 7)                             */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Msk                     (0x80UL)       /*!< INVLD_ID_PRIO_VLD (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Pos                   (16UL)         /*!< INVLD_ID_FLOOD_MASK (Bit 16)                          */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Msk                   (0xf0000UL)    /*!< INVLD_ID_FLOOD_MASK (Bitfield-Mask: 0x0f)             */
+/* ===================================================  IALK_VLAN_CONFIG  ==================================================== */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Pos                    (0UL)          /*!< UNKWN_VLAN_FLOOD (Bit 0)                              */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Msk                    (0x1UL)        /*!< UNKWN_VLAN_FLOOD (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Pos                  (1UL)          /*!< UNKWN_VLAN_LRN_ENA (Bit 1)                            */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Msk                  (0x2UL)        /*!< UNKWN_VLAN_LRN_ENA (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Pos                     (4UL)          /*!< UNKWN_VLAN_PRIO (Bit 4)                               */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Msk                     (0x70UL)       /*!< UNKWN_VLAN_PRIO (Bitfield-Mask: 0x07)                 */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Pos                 (7UL)          /*!< UNKWN_VLAN_PRIO_VLD (Bit 7)                           */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Msk                 (0x80UL)       /*!< UNKWN_VLAN_PRIO_VLD (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Pos                       (8UL)          /*!< VLANS_ENABLED (Bit 8)                                 */
+ #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Msk                       (0x700UL)      /*!< VLANS_ENABLED (Bitfield-Mask: 0x07)                   */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Pos               (16UL)         /*!< UNKWN_VLAN_FLOOD_MASK (Bit 16)                        */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Msk               (0xf0000UL)    /*!< UNKWN_VLAN_FLOOD_MASK (Bitfield-Mask: 0x0f)        */
+/* =====================================================  IALK_TBL_ADDR  ===================================================== */
+ #define R_ETHSW_IALK_TBL_ADDR_ADDR_Pos                                   (0UL)          /*!< ADDR (Bit 0)                                          */
+ #define R_ETHSW_IALK_TBL_ADDR_ADDR_Msk                                   (0x1fffUL)     /*!< ADDR (Bitfield-Mask: 0x1fff)                          */
+ #define R_ETHSW_IALK_TBL_ADDR_AINC_Pos                                   (28UL)         /*!< AINC (Bit 28)                                         */
+ #define R_ETHSW_IALK_TBL_ADDR_AINC_Msk                                   (0xf0000000UL) /*!< AINC (Bitfield-Mask: 0x0f)                            */
+/* =====================================================  IALK_TBL_DATA  ===================================================== */
+ #define R_ETHSW_IALK_TBL_DATA_VALID_Pos                                  (0UL)          /*!< VALID (Bit 0)                                         */
+ #define R_ETHSW_IALK_TBL_DATA_VALID_Msk                                  (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Pos                               (1UL)          /*!< FWD_MASK (Bit 1)                                      */
+ #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Msk                               (0x1eUL)       /*!< FWD_MASK (Bitfield-Mask: 0x0f)                        */
+/* ======================================================  IALK_VLANID  ====================================================== */
+ #define R_ETHSW_IALK_VLANID_VLANID_Pos                                   (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_IALK_VLANID_VLANID_Msk                                   (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_IALK_VLANID_VLANID_ENA_Pos                               (12UL)         /*!< VLANID_ENA (Bit 12)                                   */
+ #define R_ETHSW_IALK_VLANID_VLANID_ENA_Msk                               (0x1000UL)     /*!< VLANID_ENA (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Pos                           (13UL)         /*!< VLANID_LRN_ENA (Bit 13)                               */
+ #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Msk                           (0x2000UL)     /*!< VLANID_LRN_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Pos                        (16UL)         /*!< VLANID_FLOOD_MASK (Bit 16)                            */
+ #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Msk                        (0xf0000UL)    /*!< VLANID_FLOOD_MASK (Bitfield-Mask: 0x0f)               */
+ #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Pos                              (28UL)         /*!< VLANID_PRIO (Bit 28)                                  */
+ #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Msk                              (0x70000000UL) /*!< VLANID_PRIO (Bitfield-Mask: 0x07)                     */
+ #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Pos                          (31UL)         /*!< VLANID_PRIO_VLD (Bit 31)                              */
+ #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Msk                          (0x80000000UL) /*!< VLANID_PRIO_VLD (Bitfield-Mask: 0x01)                 */
+/* =====================================================  IMC_QLEVEL_P  ====================================================== */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Pos                                  (0UL)          /*!< QUEUE0 (Bit 0)                                        */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Msk                                  (0xfUL)        /*!< QUEUE0 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Pos                                  (4UL)          /*!< QUEUE1 (Bit 4)                                        */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Msk                                  (0xf0UL)       /*!< QUEUE1 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Pos                                  (8UL)          /*!< QUEUE2 (Bit 8)                                        */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Msk                                  (0xf00UL)      /*!< QUEUE2 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Pos                                  (12UL)         /*!< QUEUE3 (Bit 12)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Msk                                  (0xf000UL)     /*!< QUEUE3 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Pos                                  (16UL)         /*!< QUEUE4 (Bit 16)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Msk                                  (0xf0000UL)    /*!< QUEUE4 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Pos                                  (20UL)         /*!< QUEUE5 (Bit 20)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Msk                                  (0xf00000UL)   /*!< QUEUE5 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Pos                                  (24UL)         /*!< QUEUE6 (Bit 24)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Msk                                  (0xf000000UL)  /*!< QUEUE6 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Pos                                  (28UL)         /*!< QUEUE7 (Bit 28)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Msk                                  (0xf0000000UL) /*!< QUEUE7 (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  LK_CTRL  ======================================================== */
+ #define R_ETHSW_LK_CTRL_LKUP_EN_Pos                                      (0UL)          /*!< LKUP_EN (Bit 0)                                       */
+ #define R_ETHSW_LK_CTRL_LKUP_EN_Msk                                      (0x1UL)        /*!< LKUP_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_LK_CTRL_LEARN_EN_Pos                                     (1UL)          /*!< LEARN_EN (Bit 1)                                      */
+ #define R_ETHSW_LK_CTRL_LEARN_EN_Msk                                     (0x2UL)        /*!< LEARN_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_CTRL_AGING_EN_Pos                                     (2UL)          /*!< AGING_EN (Bit 2)                                      */
+ #define R_ETHSW_LK_CTRL_AGING_EN_Msk                                     (0x4UL)        /*!< AGING_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_CTRL_ALW_MGRT_Pos                                     (3UL)          /*!< ALW_MGRT (Bit 3)                                      */
+ #define R_ETHSW_LK_CTRL_ALW_MGRT_Msk                                     (0x8UL)        /*!< ALW_MGRT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Pos                                (4UL)          /*!< DISC_UNK_DEST (Bit 4)                                 */
+ #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Msk                                (0x10UL)       /*!< DISC_UNK_DEST (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_LK_CTRL_CLRTBL_Pos                                       (6UL)          /*!< CLRTBL (Bit 6)                                        */
+ #define R_ETHSW_LK_CTRL_CLRTBL_Msk                                       (0x40UL)       /*!< CLRTBL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_LK_CTRL_IND_VLAN_Pos                                     (7UL)          /*!< IND_VLAN (Bit 7)                                      */
+ #define R_ETHSW_LK_CTRL_IND_VLAN_Msk                                     (0x80UL)       /*!< IND_VLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Pos                                 (16UL)         /*!< DISC_UNK_SRC (Bit 16)                                 */
+ #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Msk                                 (0xf0000UL)    /*!< DISC_UNK_SRC (Bitfield-Mask: 0x0f)                    */
+/* =======================================================  LK_STATUS  ======================================================= */
+ #define R_ETHSW_LK_STATUS_AGEADDR_Pos                                    (0UL)          /*!< AGEADDR (Bit 0)                                       */
+ #define R_ETHSW_LK_STATUS_AGEADDR_Msk                                    (0xffffUL)     /*!< AGEADDR (Bitfield-Mask: 0xffff)                       */
+ #define R_ETHSW_LK_STATUS_OVRF_Pos                                       (16UL)         /*!< OVRF (Bit 16)                                         */
+ #define R_ETHSW_LK_STATUS_OVRF_Msk                                       (0x3fff0000UL) /*!< OVRF (Bitfield-Mask: 0x3fff)                          */
+ #define R_ETHSW_LK_STATUS_LRNEVNT_Pos                                    (31UL)         /*!< LRNEVNT (Bit 31)                                      */
+ #define R_ETHSW_LK_STATUS_LRNEVNT_Msk                                    (0x80000000UL) /*!< LRNEVNT (Bitfield-Mask: 0x01)                         */
+/* =====================================================  LK_ADDR_CTRL  ====================================================== */
+ #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Pos                                (0UL)          /*!< ADDR_MSK (Bit 0)                                      */
+ #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Msk                                (0xfffUL)      /*!< ADDR_MSK (Bitfield-Mask: 0xfff)                       */
+ #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Pos                             (22UL)         /*!< CLR_DYNAMIC (Bit 22)                                  */
+ #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Msk                             (0x400000UL)   /*!< CLR_DYNAMIC (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Pos                              (23UL)         /*!< CLR_STATIC (Bit 23)                                   */
+ #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Msk                              (0x800000UL)   /*!< CLR_STATIC (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Pos                              (24UL)         /*!< GETLASTNEW (Bit 24)                                   */
+ #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Msk                              (0x1000000UL)  /*!< GETLASTNEW (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_LK_ADDR_CTRL_WRITE_Pos                                   (25UL)         /*!< WRITE (Bit 25)                                        */
+ #define R_ETHSW_LK_ADDR_CTRL_WRITE_Msk                                   (0x2000000UL)  /*!< WRITE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_LK_ADDR_CTRL_READ_Pos                                    (26UL)         /*!< READ (Bit 26)                                         */
+ #define R_ETHSW_LK_ADDR_CTRL_READ_Msk                                    (0x4000000UL)  /*!< READ (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Pos                               (27UL)         /*!< WAIT_COMP (Bit 27)                                    */
+ #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Msk                               (0x8000000UL)  /*!< WAIT_COMP (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Pos                                  (28UL)         /*!< LOOKUP (Bit 28)                                       */
+ #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Msk                                  (0x10000000UL) /*!< LOOKUP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Pos                                   (29UL)         /*!< CLEAR (Bit 29)                                        */
+ #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Msk                                   (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Pos                                (30UL)         /*!< DEL_PORT (Bit 30)                                     */
+ #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Msk                                (0x40000000UL) /*!< DEL_PORT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_ADDR_CTRL_BUSY_Pos                                    (31UL)         /*!< BUSY (Bit 31)                                         */
+ #define R_ETHSW_LK_ADDR_CTRL_BUSY_Msk                                    (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ======================================================  LK_DATA_LO  ======================================================= */
+ #define R_ETHSW_LK_DATA_LO_MEMDATA_Pos                                   (0UL)          /*!< MEMDATA (Bit 0)                                       */
+ #define R_ETHSW_LK_DATA_LO_MEMDATA_Msk                                   (0xffffffffUL) /*!< MEMDATA (Bitfield-Mask: 0xffffffff)                   */
+/* ======================================================  LK_DATA_HI  ======================================================= */
+ #define R_ETHSW_LK_DATA_HI_MEMDATA_Pos                                   (0UL)          /*!< MEMDATA (Bit 0)                                       */
+ #define R_ETHSW_LK_DATA_HI_MEMDATA_Msk                                   (0x1ffffffUL)  /*!< MEMDATA (Bitfield-Mask: 0x1ffffff)                    */
+/* ======================================================  LK_DATA_HI2  ====================================================== */
+ #define R_ETHSW_LK_DATA_HI2_MEMDATA_Pos                                  (8UL)          /*!< MEMDATA (Bit 8)                                       */
+ #define R_ETHSW_LK_DATA_HI2_MEMDATA_Msk                                  (0xfff00UL)    /*!< MEMDATA (Bitfield-Mask: 0xfff)                        */
+/* =====================================================  LK_LEARNCOUNT  ===================================================== */
+ #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Pos                             (0UL)          /*!< LEARNCOUNT (Bit 0)                                    */
+ #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Msk                             (0x1fffUL)     /*!< LEARNCOUNT (Bitfield-Mask: 0x1fff)                    */
+ #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Pos                               (30UL)         /*!< WRITE_MD (Bit 30)                                     */
+ #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Msk                               (0xc0000000UL) /*!< WRITE_MD (Bitfield-Mask: 0x03)                        */
+/* ======================================================  LK_AGETIME  ======================================================= */
+ #define R_ETHSW_LK_AGETIME_AGETIME_Pos                                   (0UL)          /*!< AGETIME (Bit 0)                                       */
+ #define R_ETHSW_LK_AGETIME_AGETIME_Msk                                   (0xffffffUL)   /*!< AGETIME (Bitfield-Mask: 0xffffff)                     */
+/* ====================================================  MGMT_TAG_CONFIG  ==================================================== */
+ #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Pos                               (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Msk                               (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Pos                            (1UL)          /*!< AL_FRAMES (Bit 1)                                     */
+ #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Msk                            (0x2UL)        /*!< AL_FRAMES (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Pos                             (4UL)          /*!< TYPE1_EN (Bit 4)                                      */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Msk                             (0x10UL)       /*!< TYPE1_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Pos                             (5UL)          /*!< TYPE2_EN (Bit 5)                                      */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Msk                             (0x20UL)       /*!< TYPE2_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Pos                             (16UL)         /*!< TAGFIELD (Bit 16)                                     */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Msk                             (0xffff0000UL) /*!< TAGFIELD (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  TSM_CONFIG  ======================================================= */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EN_Pos                                    (0UL)          /*!< IRQ_EN (Bit 0)                                        */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EN_Msk                                    (0x1UL)        /*!< IRQ_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Pos                                  (1UL)          /*!< IRQ_TEST (Bit 1)                                      */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Msk                                  (0x2UL)        /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Pos                            (2UL)          /*!< IRQ_TSFIFO_OVR (Bit 2)                                */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Msk                            (0x4UL)        /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Pos                            (4UL)          /*!< IRQ_EVT_OFFSET (Bit 4)                                */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Msk                            (0x30UL)       /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Pos                            (8UL)          /*!< IRQ_EVT_PERIOD (Bit 8)                                */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Msk                            (0x300UL)      /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Pos                            (12UL)         /*!< IRQ_ATIME_OVER (Bit 12)                               */
+ #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Msk                            (0x3000UL)     /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Pos                                 (16UL)         /*!< IRQ_TX_EN (Bit 16)                                    */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Msk                                 (0xf0000UL)    /*!< IRQ_TX_EN (Bitfield-Mask: 0x0f)                       */
+/* ===================================================  TSM_IRQ_STAT_ACK  ==================================================== */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Pos                            (0UL)          /*!< IRQ_STAT (Bit 0)                                      */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Msk                            (0x1UL)        /*!< IRQ_STAT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Pos                            (1UL)          /*!< IRQ_TEST (Bit 1)                                      */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Msk                            (0x2UL)        /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Pos                      (2UL)          /*!< IRQ_TSFIFO_OVR (Bit 2)                                */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Msk                      (0x4UL)        /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Pos                      (4UL)          /*!< IRQ_EVT_OFFSET (Bit 4)                                */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Msk                      (0x30UL)       /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Pos                      (8UL)          /*!< IRQ_EVT_PERIOD (Bit 8)                                */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Msk                      (0x300UL)      /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Pos                      (12UL)         /*!< IRQ_ATIME_OVER (Bit 12)                               */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Msk                      (0x3000UL)     /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Pos                              (16UL)         /*!< IRQ_TX (Bit 16)                                       */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Msk                              (0xf0000UL)    /*!< IRQ_TX (Bitfield-Mask: 0x0f)                          */
+/* ======================================================  PTP_DOMAIN  ======================================================= */
+ #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Pos                                   (0UL)          /*!< DOMAIN0 (Bit 0)                                       */
+ #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Msk                                   (0xffUL)       /*!< DOMAIN0 (Bitfield-Mask: 0xff)                         */
+ #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Pos                                   (8UL)          /*!< DOMAIN1 (Bit 8)                                       */
+ #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Msk                                   (0xff00UL)     /*!< DOMAIN1 (Bitfield-Mask: 0xff)                         */
+/* ====================================================  PEERDELAY_P0_T0  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P1_T0  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P2_T0  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P3_T0  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P0_T1  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P1_T1  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P2_T1  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P3_T1  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  TS_FIFO_STATUS  ===================================================== */
+ #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Pos                              (0UL)          /*!< FF_VALID (Bit 0)                                      */
+ #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Msk                              (0xfUL)        /*!< FF_VALID (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Pos                                (16UL)         /*!< FF_OVR (Bit 16)                                       */
+ #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Msk                                (0xf0000UL)    /*!< FF_OVR (Bitfield-Mask: 0x0f)                          */
+/* ===================================================  TS_FIFO_READ_CTRL  =================================================== */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Pos                           (0UL)          /*!< PORT_NUM (Bit 0)                                      */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Msk                           (0x3UL)        /*!< PORT_NUM (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Pos                           (4UL)          /*!< TS_VALID (Bit 4)                                      */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Msk                           (0x10UL)       /*!< TS_VALID (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Pos                             (6UL)          /*!< TS_SEL (Bit 6)                                        */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Msk                             (0x40UL)       /*!< TS_SEL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Pos                              (8UL)          /*!< TS_ID (Bit 8)                                         */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Msk                              (0x7f00UL)     /*!< TS_ID (Bitfield-Mask: 0x7f)                           */
+/* ================================================  TS_FIFO_READ_TIMESTAMP  ================================================= */
+ #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Pos                     (0UL)          /*!< TIMESTAMP (Bit 0)                                     */
+ #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Msk                     (0xffffffffUL) /*!< TIMESTAMP (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  INT_CONFIG  ======================================================= */
+ #define R_ETHSW_INT_CONFIG_IRQ_EN_Pos                                    (0UL)          /*!< IRQ_EN (Bit 0)                                        */
+ #define R_ETHSW_INT_CONFIG_IRQ_EN_Msk                                    (0x1UL)        /*!< IRQ_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_INT_CONFIG_MDIO1_Pos                                     (1UL)          /*!< MDIO1 (Bit 1)                                         */
+ #define R_ETHSW_INT_CONFIG_MDIO1_Msk                                     (0x2UL)        /*!< MDIO1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Pos                                (3UL)          /*!< LK_NEW_SRC (Bit 3)                                    */
+ #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Msk                                (0x8UL)        /*!< LK_NEW_SRC (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_INT_CONFIG_IRQ_TEST_Pos                                  (4UL)          /*!< IRQ_TEST (Bit 4)                                      */
+ #define R_ETHSW_INT_CONFIG_IRQ_TEST_Msk                                  (0x10UL)       /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_CONFIG_DLR_INT_Pos                                   (5UL)          /*!< DLR_INT (Bit 5)                                       */
+ #define R_ETHSW_INT_CONFIG_DLR_INT_Msk                                   (0x20UL)       /*!< DLR_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_PRP_INT_Pos                                   (6UL)          /*!< PRP_INT (Bit 6)                                       */
+ #define R_ETHSW_INT_CONFIG_PRP_INT_Msk                                   (0x40UL)       /*!< PRP_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_HUB_INT_Pos                                   (7UL)          /*!< HUB_INT (Bit 7)                                       */
+ #define R_ETHSW_INT_CONFIG_HUB_INT_Msk                                   (0x80UL)       /*!< HUB_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_IRQ_LINK_Pos                                  (8UL)          /*!< IRQ_LINK (Bit 8)                                      */
+ #define R_ETHSW_INT_CONFIG_IRQ_LINK_Msk                                  (0x700UL)      /*!< IRQ_LINK (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Pos                               (16UL)         /*!< IRQ_MAC_EEE (Bit 16)                                  */
+ #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Msk                               (0x70000UL)    /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07)                     */
+ #define R_ETHSW_INT_CONFIG_EFP_INT_Pos                                   (27UL)         /*!< EFP_INT (Bit 27)                                      */
+ #define R_ETHSW_INT_CONFIG_EFP_INT_Msk                                   (0x8000000UL)  /*!< EFP_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Pos                             (28UL)         /*!< SRCFLT_WD_INT (Bit 28)                                */
+ #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Msk                             (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_INT_CONFIG_TSM_INT_Pos                                   (29UL)         /*!< TSM_INT (Bit 29)                                      */
+ #define R_ETHSW_INT_CONFIG_TSM_INT_Msk                                   (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_TDMA_INT_Pos                                  (30UL)         /*!< TDMA_INT (Bit 30)                                     */
+ #define R_ETHSW_INT_CONFIG_TDMA_INT_Msk                                  (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_CONFIG_PATTERN_INT_Pos                               (31UL)         /*!< PATTERN_INT (Bit 31)                                  */
+ #define R_ETHSW_INT_CONFIG_PATTERN_INT_Msk                               (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01)                     */
+/* =====================================================  INT_STAT_ACK  ====================================================== */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Pos                                (0UL)          /*!< IRQ_PEND (Bit 0)                                      */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Msk                                (0x1UL)        /*!< IRQ_PEND (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_STAT_ACK_MDIO1_Pos                                   (1UL)          /*!< MDIO1 (Bit 1)                                         */
+ #define R_ETHSW_INT_STAT_ACK_MDIO1_Msk                                   (0x2UL)        /*!< MDIO1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Pos                              (3UL)          /*!< LK_NEW_SRC (Bit 3)                                    */
+ #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Msk                              (0x8UL)        /*!< LK_NEW_SRC (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Pos                                (4UL)          /*!< IRQ_TEST (Bit 4)                                      */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Msk                                (0x10UL)       /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_STAT_ACK_DLR_INT_Pos                                 (5UL)          /*!< DLR_INT (Bit 5)                                       */
+ #define R_ETHSW_INT_STAT_ACK_DLR_INT_Msk                                 (0x20UL)       /*!< DLR_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_PRP_INT_Pos                                 (6UL)          /*!< PRP_INT (Bit 6)                                       */
+ #define R_ETHSW_INT_STAT_ACK_PRP_INT_Msk                                 (0x40UL)       /*!< PRP_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_HUB_INT_Pos                                 (7UL)          /*!< HUB_INT (Bit 7)                                       */
+ #define R_ETHSW_INT_STAT_ACK_HUB_INT_Msk                                 (0x80UL)       /*!< HUB_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Pos                                (8UL)          /*!< IRQ_LINK (Bit 8)                                      */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Msk                                (0x700UL)      /*!< IRQ_LINK (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Pos                             (16UL)         /*!< IRQ_MAC_EEE (Bit 16)                                  */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Msk                             (0x70000UL)    /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07)                     */
+ #define R_ETHSW_INT_STAT_ACK_EFP_INT_Pos                                 (27UL)         /*!< EFP_INT (Bit 27)                                      */
+ #define R_ETHSW_INT_STAT_ACK_EFP_INT_Msk                                 (0x8000000UL)  /*!< EFP_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Pos                           (28UL)         /*!< SRCFLT_WD_INT (Bit 28)                                */
+ #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Msk                           (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_INT_STAT_ACK_TSM_INT_Pos                                 (29UL)         /*!< TSM_INT (Bit 29)                                      */
+ #define R_ETHSW_INT_STAT_ACK_TSM_INT_Msk                                 (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Pos                                (30UL)         /*!< TDMA_INT (Bit 30)                                     */
+ #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Msk                                (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Pos                             (31UL)         /*!< PATTERN_INT (Bit 31)                                  */
+ #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Msk                             (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  ATIME_CTRL0  ====================================================== */
+ #define R_ETHSW_ATIME_CTRL0_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ETHSW_ATIME_CTRL0_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Pos                                 (1UL)          /*!< ONE_SHOT (Bit 1)                                      */
+ #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Msk                                 (0x2UL)        /*!< ONE_SHOT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Pos                           (2UL)          /*!< EVT_OFFSET_ENA (Bit 2)                                */
+ #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Msk                           (0x4UL)        /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Pos                           (4UL)          /*!< EVT_PERIOD_ENA (Bit 4)                                */
+ #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Msk                           (0x10UL)       /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Pos                           (5UL)          /*!< EVT_PERIOD_RST (Bit 5)                                */
+ #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Msk                           (0x20UL)       /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL0_RESTART_Pos                                  (9UL)          /*!< RESTART (Bit 9)                                       */
+ #define R_ETHSW_ATIME_CTRL0_RESTART_Msk                                  (0x200UL)      /*!< RESTART (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ATIME_CTRL0_CAPTURE_Pos                                  (11UL)         /*!< CAPTURE (Bit 11)                                      */
+ #define R_ETHSW_ATIME_CTRL0_CAPTURE_Msk                                  (0x800UL)      /*!< CAPTURE (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Pos                              (12UL)         /*!< CAPTURE_ALL (Bit 12)                                  */
+ #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Msk                              (0x1000UL)     /*!< CAPTURE_ALL (Bitfield-Mask: 0x01)                     */
+/* ======================================================  ATIME_CTRL1  ====================================================== */
+ #define R_ETHSW_ATIME_CTRL1_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ETHSW_ATIME_CTRL1_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Pos                                 (1UL)          /*!< ONE_SHOT (Bit 1)                                      */
+ #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Msk                                 (0x2UL)        /*!< ONE_SHOT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Pos                           (2UL)          /*!< EVT_OFFSET_ENA (Bit 2)                                */
+ #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Msk                           (0x4UL)        /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Pos                           (4UL)          /*!< EVT_PERIOD_ENA (Bit 4)                                */
+ #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Msk                           (0x10UL)       /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Pos                           (5UL)          /*!< EVT_PERIOD_RST (Bit 5)                                */
+ #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Msk                           (0x20UL)       /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL1_RESTART_Pos                                  (9UL)          /*!< RESTART (Bit 9)                                       */
+ #define R_ETHSW_ATIME_CTRL1_RESTART_Msk                                  (0x200UL)      /*!< RESTART (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ATIME_CTRL1_CAPTURE_Pos                                  (11UL)         /*!< CAPTURE (Bit 11)                                      */
+ #define R_ETHSW_ATIME_CTRL1_CAPTURE_Msk                                  (0x800UL)      /*!< CAPTURE (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Pos                              (12UL)         /*!< CAPTURE_ALL (Bit 12)                                  */
+ #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Msk                              (0x1000UL)     /*!< CAPTURE_ALL (Bitfield-Mask: 0x01)                     */
+/* ========================================================  ATIME0  ========================================================= */
+ #define R_ETHSW_ATIME0_TIMER_VAL_Pos                                     (0UL)          /*!< TIMER_VAL (Bit 0)                                     */
+ #define R_ETHSW_ATIME0_TIMER_VAL_Msk                                     (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff)                 */
+/* ========================================================  ATIME1  ========================================================= */
+ #define R_ETHSW_ATIME1_TIMER_VAL_Pos                                     (0UL)          /*!< TIMER_VAL (Bit 0)                                     */
+ #define R_ETHSW_ATIME1_TIMER_VAL_Msk                                     (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff)                 */
+/* =====================================================  ATIME_OFFSET0  ===================================================== */
+ #define R_ETHSW_ATIME_OFFSET0_OFFSET_Pos                                 (0UL)          /*!< OFFSET (Bit 0)                                        */
+ #define R_ETHSW_ATIME_OFFSET0_OFFSET_Msk                                 (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  ATIME_OFFSET1  ===================================================== */
+ #define R_ETHSW_ATIME_OFFSET1_OFFSET_Pos                                 (0UL)          /*!< OFFSET (Bit 0)                                        */
+ #define R_ETHSW_ATIME_OFFSET1_OFFSET_Msk                                 (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  ATIME_EVT_PERIOD0  =================================================== */
+ #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Pos                             (0UL)          /*!< PERIOD (Bit 0)                                        */
+ #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Msk                             (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  ATIME_EVT_PERIOD1  =================================================== */
+ #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Pos                             (0UL)          /*!< PERIOD (Bit 0)                                        */
+ #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Msk                             (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff)                    */
+/* ======================================================  ATIME_CORR0  ====================================================== */
+ #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Pos                              (0UL)          /*!< CORR_PERIOD (Bit 0)                                   */
+ #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Msk                              (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff)               */
+/* ======================================================  ATIME_CORR1  ====================================================== */
+ #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Pos                              (0UL)          /*!< CORR_PERIOD (Bit 0)                                   */
+ #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Msk                              (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff)               */
+/* ======================================================  ATIME_INC0  ======================================================= */
+ #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Pos                                (0UL)          /*!< CLK_PERIOD (Bit 0)                                    */
+ #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Msk                                (0x7fUL)       /*!< CLK_PERIOD (Bitfield-Mask: 0x7f)                      */
+ #define R_ETHSW_ATIME_INC0_CORR_INC_Pos                                  (8UL)          /*!< CORR_INC (Bit 8)                                      */
+ #define R_ETHSW_ATIME_INC0_CORR_INC_Msk                                  (0x7f00UL)     /*!< CORR_INC (Bitfield-Mask: 0x7f)                        */
+ #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Pos                             (16UL)         /*!< OFFS_CORR_INC (Bit 16)                                */
+ #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Msk                             (0x7f0000UL)   /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f)                   */
+/* ======================================================  ATIME_INC1  ======================================================= */
+ #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Pos                                (0UL)          /*!< CLK_PERIOD (Bit 0)                                    */
+ #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Msk                                (0x7fUL)       /*!< CLK_PERIOD (Bitfield-Mask: 0x7f)                      */
+ #define R_ETHSW_ATIME_INC1_CORR_INC_Pos                                  (8UL)          /*!< CORR_INC (Bit 8)                                      */
+ #define R_ETHSW_ATIME_INC1_CORR_INC_Msk                                  (0x7f00UL)     /*!< CORR_INC (Bitfield-Mask: 0x7f)                        */
+ #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Pos                             (16UL)         /*!< OFFS_CORR_INC (Bit 16)                                */
+ #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Msk                             (0x7f0000UL)   /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f)                   */
+/* ======================================================  ATIME_SEC0  ======================================================= */
+ #define R_ETHSW_ATIME_SEC0_SEC_TIME_Pos                                  (0UL)          /*!< SEC_TIME (Bit 0)                                      */
+ #define R_ETHSW_ATIME_SEC0_SEC_TIME_Msk                                  (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff)                  */
+/* ======================================================  ATIME_SEC1  ======================================================= */
+ #define R_ETHSW_ATIME_SEC1_SEC_TIME_Pos                                  (0UL)          /*!< SEC_TIME (Bit 0)                                      */
+ #define R_ETHSW_ATIME_SEC1_SEC_TIME_Msk                                  (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  ATIME_OFFS_CORR0  ==================================================== */
+ #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Pos                       (0UL)          /*!< OFFS_CORR_CNT (Bit 0)                                 */
+ #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Msk                       (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  ATIME_OFFS_CORR1  ==================================================== */
+ #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Pos                       (0UL)          /*!< OFFS_CORR_CNT (Bit 0)                                 */
+ #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Msk                       (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  MDIO_CFG_STATUS  ==================================================== */
+ #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Pos                                 (0UL)          /*!< BUSY (Bit 0)                                          */
+ #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Msk                                 (0x1UL)        /*!< BUSY (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_MDIO_CFG_STATUS_READERR_Pos                              (1UL)          /*!< READERR (Bit 1)                                       */
+ #define R_ETHSW_MDIO_CFG_STATUS_READERR_Msk                              (0x2UL)        /*!< READERR (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Pos                                 (2UL)          /*!< HOLD (Bit 2)                                          */
+ #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Msk                                 (0x1cUL)       /*!< HOLD (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Pos                             (5UL)          /*!< DISPREAM (Bit 5)                                      */
+ #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Msk                             (0x20UL)       /*!< DISPREAM (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Pos                               (7UL)          /*!< CLKDIV (Bit 7)                                        */
+ #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Msk                               (0xff80UL)     /*!< CLKDIV (Bitfield-Mask: 0x1ff)                         */
+/* =====================================================  MDIO_COMMAND  ====================================================== */
+ #define R_ETHSW_MDIO_COMMAND_REGADDR_Pos                                 (0UL)          /*!< REGADDR (Bit 0)                                       */
+ #define R_ETHSW_MDIO_COMMAND_REGADDR_Msk                                 (0x1fUL)       /*!< REGADDR (Bitfield-Mask: 0x1f)                         */
+ #define R_ETHSW_MDIO_COMMAND_PHYADDR_Pos                                 (5UL)          /*!< PHYADDR (Bit 5)                                       */
+ #define R_ETHSW_MDIO_COMMAND_PHYADDR_Msk                                 (0x3e0UL)      /*!< PHYADDR (Bitfield-Mask: 0x1f)                         */
+ #define R_ETHSW_MDIO_COMMAND_TRANINIT_Pos                                (15UL)         /*!< TRANINIT (Bit 15)                                     */
+ #define R_ETHSW_MDIO_COMMAND_TRANINIT_Msk                                (0x8000UL)     /*!< TRANINIT (Bitfield-Mask: 0x01)                        */
+/* =======================================================  MDIO_DATA  ======================================================= */
+ #define R_ETHSW_MDIO_DATA_MDIO_DATA_Pos                                  (0UL)          /*!< MDIO_DATA (Bit 0)                                     */
+ #define R_ETHSW_MDIO_DATA_MDIO_DATA_Msk                                  (0xffffUL)     /*!< MDIO_DATA (Bitfield-Mask: 0xffff)                     */
+/* ========================================================  REV_P0  ========================================================= */
+ #define R_ETHSW_REV_P0_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REV_P0_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  REV_P1  ========================================================= */
+ #define R_ETHSW_REV_P1_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REV_P1_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  REV_P2  ========================================================= */
+ #define R_ETHSW_REV_P2_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REV_P2_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  REV_P3  ========================================================= */
+ #define R_ETHSW_REV_P3_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REV_P3_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ===================================================  COMMAND_CONFIG_P0  =================================================== */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
+ #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+/* ===================================================  COMMAND_CONFIG_P1  =================================================== */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
+ #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P1_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+/* ===================================================  COMMAND_CONFIG_P2  =================================================== */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
+ #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P2_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+/* ===================================================  COMMAND_CONFIG_P3  =================================================== */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
+ #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P3_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+/* =====================================================  MAC_ADDR_0_P0  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  MAC_ADDR_0_P1  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  MAC_ADDR_0_P2  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  MAC_ADDR_1_P0  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  MAC_ADDR_1_P1  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  MAC_ADDR_1_P2  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  FRM_LENGTH_P0  ===================================================== */
+ #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
+ #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
+/* =====================================================  FRM_LENGTH_P1  ===================================================== */
+ #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
+ #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
+/* =====================================================  FRM_LENGTH_P2  ===================================================== */
+ #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
+ #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
+/* =====================================================  FRM_LENGTH_P3  ===================================================== */
+ #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
+ #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
+/* ====================================================  PAUSE_QUANT_P0  ===================================================== */
+ #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
+ #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  PAUSE_QUANT_P1  ===================================================== */
+ #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
+ #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  PAUSE_QUANT_P2  ===================================================== */
+ #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
+ #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  PAUSE_QUANT_P3  ===================================================== */
+ #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
+ #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
+/* ===================================================  MAC_LINK_QTRIG_P0  =================================================== */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_LINK_QTRIG_P1  =================================================== */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_LINK_QTRIG_P2  =================================================== */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* =================================================  PTPCLOCKIDENTITY1_P0  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY1_P1  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY1_P2  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY2_P0  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY2_P1  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY2_P2  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
+/* ==================================================  PTPAUTORESPONSE_P0  =================================================== */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
+/* ==================================================  PTPAUTORESPONSE_P1  =================================================== */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
+/* ==================================================  PTPAUTORESPONSE_P2  =================================================== */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
+/* =======================================================  STATUS_P0  ======================================================= */
+ #define R_ETHSW_STATUS_P0_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
+ #define R_ETHSW_STATUS_P0_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_STATUS_P0_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
+ #define R_ETHSW_STATUS_P0_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_STATUS_P0_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
+ #define R_ETHSW_STATUS_P0_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P0_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
+ #define R_ETHSW_STATUS_P0_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P0_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
+ #define R_ETHSW_STATUS_P0_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
+ #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
+/* =======================================================  STATUS_P1  ======================================================= */
+ #define R_ETHSW_STATUS_P1_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
+ #define R_ETHSW_STATUS_P1_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_STATUS_P1_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
+ #define R_ETHSW_STATUS_P1_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_STATUS_P1_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
+ #define R_ETHSW_STATUS_P1_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P1_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
+ #define R_ETHSW_STATUS_P1_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P1_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
+ #define R_ETHSW_STATUS_P1_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
+ #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
+/* =======================================================  STATUS_P2  ======================================================= */
+ #define R_ETHSW_STATUS_P2_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
+ #define R_ETHSW_STATUS_P2_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_STATUS_P2_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
+ #define R_ETHSW_STATUS_P2_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_STATUS_P2_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
+ #define R_ETHSW_STATUS_P2_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P2_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
+ #define R_ETHSW_STATUS_P2_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P2_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
+ #define R_ETHSW_STATUS_P2_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
+ #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
+/* =======================================================  STATUS_P3  ======================================================= */
+ #define R_ETHSW_STATUS_P3_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
+ #define R_ETHSW_STATUS_P3_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_STATUS_P3_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
+ #define R_ETHSW_STATUS_P3_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_STATUS_P3_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
+ #define R_ETHSW_STATUS_P3_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P3_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
+ #define R_ETHSW_STATUS_P3_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P3_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
+ #define R_ETHSW_STATUS_P3_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
+ #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
+/* ===================================================  TX_IPG_LENGTH_P0  ==================================================== */
+ #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
+ #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
+/* ===================================================  TX_IPG_LENGTH_P1  ==================================================== */
+ #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
+ #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
+/* ===================================================  TX_IPG_LENGTH_P2  ==================================================== */
+ #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
+ #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
+/* ===================================================  TX_IPG_LENGTH_P3  ==================================================== */
+ #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
+ #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
+/* ====================================================  EEE_CTL_STAT_P0  ==================================================== */
+ #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
+ #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
+/* ====================================================  EEE_CTL_STAT_P1  ==================================================== */
+ #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
+ #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
+/* ====================================================  EEE_CTL_STAT_P2  ==================================================== */
+ #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
+ #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
+/* ===================================================  EEE_IDLE_TIME_P0  ==================================================== */
+ #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_IDLE_TIME_P1  ==================================================== */
+ #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_IDLE_TIME_P2  ==================================================== */
+ #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_TWSYS_TIME_P0  =================================================== */
+ #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_TWSYS_TIME_P1  =================================================== */
+ #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_TWSYS_TIME_P2  =================================================== */
+ #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
+/* =====================================================  IDLE_SLOPE_P0  ===================================================== */
+ #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
+ #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
+/* =====================================================  IDLE_SLOPE_P1  ===================================================== */
+ #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
+ #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
+/* =====================================================  IDLE_SLOPE_P2  ===================================================== */
+ #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
+ #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
+/* =====================================================  IDLE_SLOPE_P3  ===================================================== */
+ #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
+ #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
+/* ======================================================  CT_DELAY_P0  ====================================================== */
+ #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
+ #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
+/* ======================================================  CT_DELAY_P1  ====================================================== */
+ #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
+ #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
+/* ======================================================  CT_DELAY_P2  ====================================================== */
+ #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
+ #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
+/* =====================================================  BR_CONTROL_P0  ===================================================== */
+ #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
+ #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
+ #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
+ #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
+ #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
+ #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
+ #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
+ #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
+ #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
+ #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
+ #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
+ #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+/* =====================================================  BR_CONTROL_P1  ===================================================== */
+ #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
+ #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
+ #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
+ #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
+ #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
+ #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
+ #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
+ #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
+ #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
+ #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
+ #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
+ #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+/* =====================================================  BR_CONTROL_P2  ===================================================== */
+ #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
+ #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
+ #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
+ #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
+ #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
+ #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
+ #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
+ #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
+ #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
+ #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
+ #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
+ #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+/* ================================================  AFRAMESTRANSMITTEDOK_P0  ================================================ */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AFRAMESTRANSMITTEDOK_P1  ================================================ */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AFRAMESTRANSMITTEDOK_P2  ================================================ */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AFRAMESTRANSMITTEDOK_P3  ================================================ */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* =================================================  AFRAMESRECEIVEDOK_P0  ================================================== */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  AFRAMESRECEIVEDOK_P1  ================================================== */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  AFRAMESRECEIVEDOK_P2  ================================================== */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  AFRAMESRECEIVEDOK_P3  ================================================== */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =============================================  AFRAMECHECKSEQUENCEERRORS_P0  ============================================== */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  AFRAMECHECKSEQUENCEERRORS_P1  ============================================== */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  AFRAMECHECKSEQUENCEERRORS_P2  ============================================== */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  AFRAMECHECKSEQUENCEERRORS_P3  ============================================== */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ==================================================  AALIGNMENTERRORS_P0  ================================================== */
+ #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ==================================================  AALIGNMENTERRORS_P1  ================================================== */
+ #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ==================================================  AALIGNMENTERRORS_P2  ================================================== */
+ #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ==================================================  AALIGNMENTERRORS_P3  ================================================== */
+ #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ================================================  AOCTETSTRANSMITTEDOK_P0  ================================================ */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
+/* ================================================  AOCTETSTRANSMITTEDOK_P1  ================================================ */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
+/* ================================================  AOCTETSTRANSMITTEDOK_P2  ================================================ */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
+/* ================================================  AOCTETSTRANSMITTEDOK_P3  ================================================ */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
+/* =================================================  AOCTETSRECEIVEDOK_P0  ================================================== */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
+/* =================================================  AOCTETSRECEIVEDOK_P1  ================================================== */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
+/* =================================================  AOCTETSRECEIVEDOK_P2  ================================================== */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
+/* =================================================  AOCTETSRECEIVEDOK_P3  ================================================== */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
+/* ===============================================  ATXPAUSEMACCTRLFRAMES_P0  ================================================ */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ATXPAUSEMACCTRLFRAMES_P1  ================================================ */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ATXPAUSEMACCTRLFRAMES_P2  ================================================ */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ATXPAUSEMACCTRLFRAMES_P3  ================================================ */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ARXPAUSEMACCTRLFRAMES_P0  ================================================ */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ARXPAUSEMACCTRLFRAMES_P1  ================================================ */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ARXPAUSEMACCTRLFRAMES_P2  ================================================ */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ARXPAUSEMACCTRLFRAMES_P3  ================================================ */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* =====================================================  IFINERRORS_P0  ===================================================== */
+ #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  IFINERRORS_P1  ===================================================== */
+ #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  IFINERRORS_P2  ===================================================== */
+ #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  IFINERRORS_P3  ===================================================== */
+ #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  IFOUTERRORS_P0  ===================================================== */
+ #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ====================================================  IFOUTERRORS_P1  ===================================================== */
+ #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ====================================================  IFOUTERRORS_P2  ===================================================== */
+ #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ====================================================  IFOUTERRORS_P3  ===================================================== */
+ #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFINUCASTPKTS_P0  ==================================================== */
+ #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFINUCASTPKTS_P1  ==================================================== */
+ #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFINUCASTPKTS_P2  ==================================================== */
+ #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFINUCASTPKTS_P3  ==================================================== */
+ #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* =================================================  IFINMULTICASTPKTS_P0  ================================================== */
+ #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINMULTICASTPKTS_P1  ================================================== */
+ #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINMULTICASTPKTS_P2  ================================================== */
+ #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINMULTICASTPKTS_P3  ================================================== */
+ #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINBROADCASTPKTS_P0  ================================================== */
+ #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINBROADCASTPKTS_P1  ================================================== */
+ #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINBROADCASTPKTS_P2  ================================================== */
+ #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINBROADCASTPKTS_P3  ================================================== */
+ #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  IFOUTDISCARDS_P0  ==================================================== */
+ #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFOUTDISCARDS_P1  ==================================================== */
+ #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFOUTDISCARDS_P2  ==================================================== */
+ #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFOUTDISCARDS_P3  ==================================================== */
+ #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFOUTUCASTPKTS_P0  =================================================== */
+ #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFOUTUCASTPKTS_P1  =================================================== */
+ #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFOUTUCASTPKTS_P2  =================================================== */
+ #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFOUTUCASTPKTS_P3  =================================================== */
+ #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* =================================================  IFOUTMULTICASTPKTS_P0  ================================================= */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTMULTICASTPKTS_P1  ================================================= */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTMULTICASTPKTS_P2  ================================================= */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTMULTICASTPKTS_P3  ================================================= */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTBROADCASTPKTS_P0  ================================================= */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTBROADCASTPKTS_P1  ================================================= */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTBROADCASTPKTS_P2  ================================================= */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTBROADCASTPKTS_P3  ================================================= */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* ================================================  ETHERSTATSDROPEVENTS_P0  ================================================ */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  ETHERSTATSDROPEVENTS_P1  ================================================ */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  ETHERSTATSDROPEVENTS_P2  ================================================ */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  ETHERSTATSDROPEVENTS_P3  ================================================ */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  ETHERSTATSOCTETS_P0  ================================================== */
+ #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
+/* ==================================================  ETHERSTATSOCTETS_P1  ================================================== */
+ #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
+/* ==================================================  ETHERSTATSOCTETS_P2  ================================================== */
+ #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
+/* ==================================================  ETHERSTATSOCTETS_P3  ================================================== */
+ #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
+/* ===================================================  ETHERSTATSPKTS_P0  =================================================== */
+ #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  ETHERSTATSPKTS_P1  =================================================== */
+ #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  ETHERSTATSPKTS_P2  =================================================== */
+ #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  ETHERSTATSPKTS_P3  =================================================== */
+ #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  ETHERSTATSUNDERSIZEPKTS_P0  =============================================== */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ==============================================  ETHERSTATSUNDERSIZEPKTS_P1  =============================================== */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ==============================================  ETHERSTATSUNDERSIZEPKTS_P2  =============================================== */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ==============================================  ETHERSTATSUNDERSIZEPKTS_P3  =============================================== */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ===============================================  ETHERSTATSOVERSIZEPKTS_P0  =============================================== */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
+/* ===============================================  ETHERSTATSOVERSIZEPKTS_P1  =============================================== */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
+/* ===============================================  ETHERSTATSOVERSIZEPKTS_P2  =============================================== */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
+/* ===============================================  ETHERSTATSOVERSIZEPKTS_P3  =============================================== */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
+/* ===============================================  ETHERSTATSPKTS64OCTETS_P0  =============================================== */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  ETHERSTATSPKTS64OCTETS_P1  =============================================== */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  ETHERSTATSPKTS64OCTETS_P2  =============================================== */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  ETHERSTATSPKTS64OCTETS_P3  =============================================== */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
+/* ============================================  ETHERSTATSPKTS65TO127OCTETS_P0  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS65TO127OCTETS_P1  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS65TO127OCTETS_P2  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS65TO127OCTETS_P3  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS128TO255OCTETS_P0  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS128TO255OCTETS_P1  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS128TO255OCTETS_P2  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS128TO255OCTETS_P3  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS256TO511OCTETS_P0  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS256TO511OCTETS_P1  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS256TO511OCTETS_P2  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS256TO511OCTETS_P3  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P0  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P1  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P2  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P3  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P0  =========================================== */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P1  =========================================== */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P2  =========================================== */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P3  =========================================== */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P0  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P1  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P2  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P3  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
+/* =================================================  ETHERSTATSJABBERS_P0  ================================================== */
+ #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
+ #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  ETHERSTATSJABBERS_P1  ================================================== */
+ #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
+ #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  ETHERSTATSJABBERS_P2  ================================================== */
+ #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
+ #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  ETHERSTATSJABBERS_P3  ================================================== */
+ #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
+ #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ================================================  ETHERSTATSFRAGMENTS_P0  ================================================= */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  ETHERSTATSFRAGMENTS_P1  ================================================= */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  ETHERSTATSFRAGMENTS_P2  ================================================= */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  ETHERSTATSFRAGMENTS_P3  ================================================= */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ===================================================  VLANRECEIVEDOK_P0  =================================================== */
+ #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  VLANRECEIVEDOK_P1  =================================================== */
+ #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  VLANRECEIVEDOK_P2  =================================================== */
+ #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  VLANRECEIVEDOK_P3  =================================================== */
+ #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
+/* =================================================  VLANTRANSMITTEDOK_P0  ================================================== */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VLANTRANSMITTEDOK_P1  ================================================== */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VLANTRANSMITTEDOK_P2  ================================================== */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VLANTRANSMITTEDOK_P3  ================================================== */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
+/* ================================================  FRAMESRETRANSMITTED_P0  ================================================= */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  FRAMESRETRANSMITTED_P1  ================================================= */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  FRAMESRETRANSMITTED_P2  ================================================= */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  FRAMESRETRANSMITTED_P3  ================================================= */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ====================================================  STATS_HIWORD_P0  ==================================================== */
+ #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
+ #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  STATS_HIWORD_P1  ==================================================== */
+ #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
+ #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  STATS_HIWORD_P2  ==================================================== */
+ #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
+ #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  STATS_HIWORD_P3  ==================================================== */
+ #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
+ #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
+/* =====================================================  STATS_CTRL_P0  ===================================================== */
+ #define R_ETHSW_STATS_CTRL_P0_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
+ #define R_ETHSW_STATS_CTRL_P0_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
+ #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
+/* =====================================================  STATS_CTRL_P1  ===================================================== */
+ #define R_ETHSW_STATS_CTRL_P1_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
+ #define R_ETHSW_STATS_CTRL_P1_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
+ #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
+/* =====================================================  STATS_CTRL_P2  ===================================================== */
+ #define R_ETHSW_STATS_CTRL_P2_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
+ #define R_ETHSW_STATS_CTRL_P2_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
+ #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
+/* =====================================================  STATS_CTRL_P3  ===================================================== */
+ #define R_ETHSW_STATS_CTRL_P3_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
+ #define R_ETHSW_STATS_CTRL_P3_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
+ #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
+/* ================================================  STATS_CLEAR_VALUELO_P0  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUELO_P1  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUELO_P2  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUELO_P3  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUEHI_P0  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUEHI_P1  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUEHI_P2  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUEHI_P3  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
+/* =====================================================  ADEFERRED_P0  ====================================================== */
+ #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  ADEFERRED_P1  ====================================================== */
+ #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  ADEFERRED_P2  ====================================================== */
+ #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  ADEFERRED_P3  ====================================================== */
+ #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  AMULTIPLECOLLISIONS_P0  ================================================= */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
+/* ================================================  AMULTIPLECOLLISIONS_P1  ================================================= */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
+/* ================================================  AMULTIPLECOLLISIONS_P2  ================================================= */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
+/* ================================================  AMULTIPLECOLLISIONS_P3  ================================================= */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
+/* =================================================  ASINGLECOLLISIONS_P0  ================================================== */
+ #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
+ #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
+/* =================================================  ASINGLECOLLISIONS_P1  ================================================== */
+ #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
+ #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
+/* =================================================  ASINGLECOLLISIONS_P2  ================================================== */
+ #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
+ #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
+/* =================================================  ASINGLECOLLISIONS_P3  ================================================== */
+ #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
+ #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
+/* ==================================================  ALATECOLLISIONS_P0  =================================================== */
+ #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
+ #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  ALATECOLLISIONS_P1  =================================================== */
+ #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
+ #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  ALATECOLLISIONS_P2  =================================================== */
+ #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
+ #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  ALATECOLLISIONS_P3  =================================================== */
+ #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
+ #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ================================================  AEXCESSIVECOLLISIONS_P0  ================================================ */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AEXCESSIVECOLLISIONS_P1  ================================================ */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AEXCESSIVECOLLISIONS_P2  ================================================ */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AEXCESSIVECOLLISIONS_P3  ================================================ */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  ACARRIERSENSEERRORS_P0  ================================================= */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ================================================  ACARRIERSENSEERRORS_P1  ================================================= */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ================================================  ACARRIERSENSEERRORS_P2  ================================================= */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ================================================  ACARRIERSENSEERRORS_P3  ================================================= */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  P0_QSTMACU0  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU1  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU2  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU3  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU4  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU5  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU6  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU7  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACD0  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD1  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD2  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD3  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD4  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD5  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD6  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD7  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMAMU0  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU1  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU2  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU3  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU4  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU5  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU6  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU7  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMD0  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD1  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD2  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD3  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD4  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD5  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD6  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD7  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSFTVL0  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL1  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL2  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL3  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL4  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL5  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL6  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL7  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVLM0  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM1  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM2  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM3  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM4  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM5  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM6  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM7  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTBL0  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL1  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL2  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL3  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL4  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL5  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL6  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL7  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  P0_QSMFC0  ======================================================= */
+ #define R_ETHSW_P0_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC1  ======================================================= */
+ #define R_ETHSW_P0_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC2  ======================================================= */
+ #define R_ETHSW_P0_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC3  ======================================================= */
+ #define R_ETHSW_P0_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC4  ======================================================= */
+ #define R_ETHSW_P0_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC5  ======================================================= */
+ #define R_ETHSW_P0_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC6  ======================================================= */
+ #define R_ETHSW_P0_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC7  ======================================================= */
+ #define R_ETHSW_P0_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QMSPPC0  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC1  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC2  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC3  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC4  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC5  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC6  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC7  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC0  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC1  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC2  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC3  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC4  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC5  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC6  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC7  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  P0_QSEIS  ======================================================== */
+ #define R_ETHSW_P0_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
+ #define R_ETHSW_P0_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QSEIS  ======================================================== */
+ #define R_ETHSW_P1_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
+ #define R_ETHSW_P1_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QSEIS  ======================================================== */
+ #define R_ETHSW_P2_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
+ #define R_ETHSW_P2_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QSEIE  ======================================================== */
+ #define R_ETHSW_P0_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
+ #define R_ETHSW_P0_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QSEIE  ======================================================== */
+ #define R_ETHSW_P1_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
+ #define R_ETHSW_P1_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QSEIE  ======================================================== */
+ #define R_ETHSW_P2_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
+ #define R_ETHSW_P2_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QSEID  ======================================================== */
+ #define R_ETHSW_P0_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QSEID  ======================================================== */
+ #define R_ETHSW_P1_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QSEID  ======================================================== */
+ #define R_ETHSW_P2_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QGMOD  ======================================================== */
+ #define R_ETHSW_P0_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
+ #define R_ETHSW_P0_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P1_QGMOD  ======================================================== */
+ #define R_ETHSW_P1_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
+ #define R_ETHSW_P1_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P2_QGMOD  ======================================================== */
+ #define R_ETHSW_P2_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
+ #define R_ETHSW_P2_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P0_QGPPC  ======================================================== */
+ #define R_ETHSW_P0_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGPPC  ======================================================== */
+ #define R_ETHSW_P1_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGPPC  ======================================================== */
+ #define R_ETHSW_P2_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC0  ======================================================= */
+ #define R_ETHSW_P0_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC1  ======================================================= */
+ #define R_ETHSW_P0_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC2  ======================================================= */
+ #define R_ETHSW_P0_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC3  ======================================================= */
+ #define R_ETHSW_P0_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC4  ======================================================= */
+ #define R_ETHSW_P0_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC5  ======================================================= */
+ #define R_ETHSW_P0_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC6  ======================================================= */
+ #define R_ETHSW_P0_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC7  ======================================================= */
+ #define R_ETHSW_P0_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGEIS  ======================================================== */
+ #define R_ETHSW_P0_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
+ #define R_ETHSW_P0_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QGEIS  ======================================================== */
+ #define R_ETHSW_P1_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
+ #define R_ETHSW_P1_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QGEIS  ======================================================== */
+ #define R_ETHSW_P2_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
+ #define R_ETHSW_P2_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QGEIE  ======================================================== */
+ #define R_ETHSW_P0_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
+ #define R_ETHSW_P0_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QGEIE  ======================================================== */
+ #define R_ETHSW_P1_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
+ #define R_ETHSW_P1_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QGEIE  ======================================================== */
+ #define R_ETHSW_P2_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
+ #define R_ETHSW_P2_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QGEID  ======================================================== */
+ #define R_ETHSW_P0_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
+ #define R_ETHSW_P0_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QGEID  ======================================================== */
+ #define R_ETHSW_P1_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
+ #define R_ETHSW_P1_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QGEID  ======================================================== */
+ #define R_ETHSW_P2_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
+ #define R_ETHSW_P2_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
+/* ======================================================  P0_QMDESC0  ======================================================= */
+ #define R_ETHSW_P0_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC1  ======================================================= */
+ #define R_ETHSW_P0_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC2  ======================================================= */
+ #define R_ETHSW_P0_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC3  ======================================================= */
+ #define R_ETHSW_P0_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC4  ======================================================= */
+ #define R_ETHSW_P0_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC5  ======================================================= */
+ #define R_ETHSW_P0_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC6  ======================================================= */
+ #define R_ETHSW_P0_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC7  ======================================================= */
+ #define R_ETHSW_P0_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMCBSC0  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC1  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC2  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC3  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC4  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC5  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC6  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC7  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCIRC0  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC1  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC2  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC3  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC4  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC5  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC6  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC7  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* =======================================================  P0_QMGPC0  ======================================================= */
+ #define R_ETHSW_P0_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC1  ======================================================= */
+ #define R_ETHSW_P0_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC2  ======================================================= */
+ #define R_ETHSW_P0_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC3  ======================================================= */
+ #define R_ETHSW_P0_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC4  ======================================================= */
+ #define R_ETHSW_P0_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC5  ======================================================= */
+ #define R_ETHSW_P0_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC6  ======================================================= */
+ #define R_ETHSW_P0_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC7  ======================================================= */
+ #define R_ETHSW_P0_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC0  ======================================================= */
+ #define R_ETHSW_P0_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC1  ======================================================= */
+ #define R_ETHSW_P0_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC2  ======================================================= */
+ #define R_ETHSW_P0_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC3  ======================================================= */
+ #define R_ETHSW_P0_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC4  ======================================================= */
+ #define R_ETHSW_P0_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC5  ======================================================= */
+ #define R_ETHSW_P0_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC6  ======================================================= */
+ #define R_ETHSW_P0_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC7  ======================================================= */
+ #define R_ETHSW_P0_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  P0_QMEC  ======================================================== */
+ #define R_ETHSW_P0_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
+ #define R_ETHSW_P0_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
+/* ========================================================  P1_QMEC  ======================================================== */
+ #define R_ETHSW_P1_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
+ #define R_ETHSW_P1_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
+/* ========================================================  P2_QMEC  ======================================================== */
+ #define R_ETHSW_P2_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
+ #define R_ETHSW_P2_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
+/* =======================================================  P0_QMEIS  ======================================================== */
+ #define R_ETHSW_P0_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
+ #define R_ETHSW_P0_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P1_QMEIS  ======================================================== */
+ #define R_ETHSW_P1_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
+ #define R_ETHSW_P1_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P2_QMEIS  ======================================================== */
+ #define R_ETHSW_P2_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
+ #define R_ETHSW_P2_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P0_QMEIE  ======================================================== */
+ #define R_ETHSW_P0_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
+ #define R_ETHSW_P0_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P1_QMEIE  ======================================================== */
+ #define R_ETHSW_P1_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
+ #define R_ETHSW_P1_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P2_QMEIE  ======================================================== */
+ #define R_ETHSW_P2_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
+ #define R_ETHSW_P2_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P0_QMEID  ======================================================== */
+ #define R_ETHSW_P0_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
+ #define R_ETHSW_P0_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P1_QMEID  ======================================================== */
+ #define R_ETHSW_P1_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
+ #define R_ETHSW_P1_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P2_QMEID  ======================================================== */
+ #define R_ETHSW_P2_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
+ #define R_ETHSW_P2_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
+/* =====================================================  P0_PCP_REMAP  ====================================================== */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
+/* =====================================================  P1_PCP_REMAP  ====================================================== */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
+/* =====================================================  P2_PCP_REMAP  ====================================================== */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
+/* ======================================================  P0_VLAN_TAG  ====================================================== */
+ #define R_ETHSW_P0_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_ETHSW_P0_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
+ #define R_ETHSW_P0_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
+ #define R_ETHSW_P0_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  P1_VLAN_TAG  ====================================================== */
+ #define R_ETHSW_P1_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_ETHSW_P1_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
+ #define R_ETHSW_P1_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
+ #define R_ETHSW_P1_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  P2_VLAN_TAG  ====================================================== */
+ #define R_ETHSW_P2_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_ETHSW_P2_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
+ #define R_ETHSW_P2_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
+ #define R_ETHSW_P2_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  P0_VLAN_MODE  ====================================================== */
+ #define R_ETHSW_P0_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
+ #define R_ETHSW_P0_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_P0_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
+ #define R_ETHSW_P0_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
+/* =====================================================  P1_VLAN_MODE  ====================================================== */
+ #define R_ETHSW_P1_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
+ #define R_ETHSW_P1_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_P1_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
+ #define R_ETHSW_P1_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
+/* =====================================================  P2_VLAN_MODE  ====================================================== */
+ #define R_ETHSW_P2_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
+ #define R_ETHSW_P2_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_P2_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
+ #define R_ETHSW_P2_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
+/* ====================================================  P0_VIC_DROP_CNT  ==================================================== */
+ #define R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
+ #define R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
+/* ====================================================  P1_VIC_DROP_CNT  ==================================================== */
+ #define R_ETHSW_P1_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
+ #define R_ETHSW_P1_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
+/* ====================================================  P2_VIC_DROP_CNT  ==================================================== */
+ #define R_ETHSW_P2_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
+ #define R_ETHSW_P2_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
+/* ===================================================  P0_LOOKUP_HIT_CNT  =================================================== */
+ #define R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
+ #define R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
+/* ===================================================  P1_LOOKUP_HIT_CNT  =================================================== */
+ #define R_ETHSW_P1_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
+ #define R_ETHSW_P1_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
+/* ===================================================  P2_LOOKUP_HIT_CNT  =================================================== */
+ #define R_ETHSW_P2_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
+ #define R_ETHSW_P2_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
+/* ====================================================  P0_ERROR_STATUS  ==================================================== */
+ #define R_ETHSW_P0_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P0_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
+/* ====================================================  P1_ERROR_STATUS  ==================================================== */
+ #define R_ETHSW_P1_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P1_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P1_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P1_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P1_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
+/* ====================================================  P2_ERROR_STATUS  ==================================================== */
+ #define R_ETHSW_P2_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P2_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P2_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P2_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P2_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
+/* =====================================================  P0_ERROR_MASK  ===================================================== */
+ #define R_ETHSW_P0_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
+/* =====================================================  P1_ERROR_MASK  ===================================================== */
+ #define R_ETHSW_P1_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P1_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P1_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P1_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P1_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
+/* =====================================================  P2_ERROR_MASK  ===================================================== */
+ #define R_ETHSW_P2_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P2_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P2_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P2_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P2_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CHANNEL_STATE  ===================================================== */
+ #define R_ETHSW_CHANNEL_STATE_CH0ACT_Pos                                 (0UL)          /*!< CH0ACT (Bit 0)                                        */
+ #define R_ETHSW_CHANNEL_STATE_CH0ACT_Msk                                 (0x1UL)        /*!< CH0ACT (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_STATE_CH1ACT_Pos                                 (1UL)          /*!< CH1ACT (Bit 1)                                        */
+ #define R_ETHSW_CHANNEL_STATE_CH1ACT_Msk                                 (0x2UL)        /*!< CH1ACT (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_STATE_CH2ACT_Pos                                 (2UL)          /*!< CH2ACT (Bit 2)                                        */
+ #define R_ETHSW_CHANNEL_STATE_CH2ACT_Msk                                 (0x4UL)        /*!< CH2ACT (Bitfield-Mask: 0x01)                          */
+/* ====================================================  CHANNEL_ENABLE  ===================================================== */
+ #define R_ETHSW_CHANNEL_ENABLE_CH0ENA_Pos                                (0UL)          /*!< CH0ENA (Bit 0)                                        */
+ #define R_ETHSW_CHANNEL_ENABLE_CH0ENA_Msk                                (0x1UL)        /*!< CH0ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_ENABLE_CH1ENA_Pos                                (1UL)          /*!< CH1ENA (Bit 1)                                        */
+ #define R_ETHSW_CHANNEL_ENABLE_CH1ENA_Msk                                (0x2UL)        /*!< CH1ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_ENABLE_CH2ENA_Pos                                (2UL)          /*!< CH2ENA (Bit 2)                                        */
+ #define R_ETHSW_CHANNEL_ENABLE_CH2ENA_Msk                                (0x4UL)        /*!< CH2ENA (Bitfield-Mask: 0x01)                          */
+/* ====================================================  CHANNEL_DISABLE  ==================================================== */
+ #define R_ETHSW_CHANNEL_DISABLE_CH0DIS_Pos                               (0UL)          /*!< CH0DIS (Bit 0)                                        */
+ #define R_ETHSW_CHANNEL_DISABLE_CH0DIS_Msk                               (0x1UL)        /*!< CH0DIS (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_DISABLE_CH1DIS_Pos                               (1UL)          /*!< CH1DIS (Bit 1)                                        */
+ #define R_ETHSW_CHANNEL_DISABLE_CH1DIS_Msk                               (0x2UL)        /*!< CH1DIS (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_DISABLE_CH2DIS_Pos                               (2UL)          /*!< CH2DIS (Bit 2)                                        */
+ #define R_ETHSW_CHANNEL_DISABLE_CH2DIS_Msk                               (0x4UL)        /*!< CH2DIS (Bitfield-Mask: 0x01)                          */
+/* =====================================================  ASI_MEM_WDATA  ===================================================== */
+ #define R_ETHSW_ASI_MEM_WDATA_WDATA_Pos                                  (0UL)          /*!< WDATA (Bit 0)                                         */
+ #define R_ETHSW_ASI_MEM_WDATA_WDATA_Msk                                  (0xffffffffUL) /*!< WDATA (Bitfield-Mask: 0xffffffff)                     */
+/* =====================================================  ASI_MEM_ADDR  ====================================================== */
+ #define R_ETHSW_ASI_MEM_ADDR_ADDR_Pos                                    (0UL)          /*!< ADDR (Bit 0)                                          */
+ #define R_ETHSW_ASI_MEM_ADDR_ADDR_Msk                                    (0x7fUL)       /*!< ADDR (Bitfield-Mask: 0x7f)                            */
+ #define R_ETHSW_ASI_MEM_ADDR_MEM_WEN_Pos                                 (7UL)          /*!< MEM_WEN (Bit 7)                                       */
+ #define R_ETHSW_ASI_MEM_ADDR_MEM_WEN_Msk                                 (0x80UL)       /*!< MEM_WEN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos                                 (8UL)          /*!< MEM_REQ (Bit 8)                                       */
+ #define R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk                                 (0x700UL)      /*!< MEM_REQ (Bitfield-Mask: 0x07)                         */
+/* =====================================================  ASI_MEM_RDATA  ===================================================== */
+ #define R_ETHSW_ASI_MEM_RDATA_RDATA_Pos                                  (0UL)          /*!< RDATA (Bit 0)                                         */
+ #define R_ETHSW_ASI_MEM_RDATA_RDATA_Msk                                  (0xffffffffUL) /*!< RDATA (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMACU0  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU1  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU2  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU3  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU4  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU5  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU6  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU7  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACD0  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD1  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD2  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD3  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD4  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD5  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD6  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD7  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMAMU0  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU1  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU2  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU3  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU4  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU5  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU6  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU7  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMD0  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD1  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD2  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD3  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD4  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD5  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD6  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD7  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSFTVL0  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL1  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL2  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL3  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL4  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL5  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL6  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL7  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVLM0  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM1  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM2  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM3  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM4  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM5  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM6  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM7  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTBL0  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL1  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL2  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL3  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL4  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL5  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL6  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL7  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  P1_QSMFC0  ======================================================= */
+ #define R_ETHSW_P1_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC1  ======================================================= */
+ #define R_ETHSW_P1_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC2  ======================================================= */
+ #define R_ETHSW_P1_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC3  ======================================================= */
+ #define R_ETHSW_P1_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC4  ======================================================= */
+ #define R_ETHSW_P1_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC5  ======================================================= */
+ #define R_ETHSW_P1_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC6  ======================================================= */
+ #define R_ETHSW_P1_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC7  ======================================================= */
+ #define R_ETHSW_P1_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QMSPPC0  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC1  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC2  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC3  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC4  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC5  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC6  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC7  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC0  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC1  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC2  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC3  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC4  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC5  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC6  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC7  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  P1_QGDPC0  ======================================================= */
+ #define R_ETHSW_P1_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC1  ======================================================= */
+ #define R_ETHSW_P1_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC2  ======================================================= */
+ #define R_ETHSW_P1_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC3  ======================================================= */
+ #define R_ETHSW_P1_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC4  ======================================================= */
+ #define R_ETHSW_P1_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC5  ======================================================= */
+ #define R_ETHSW_P1_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC6  ======================================================= */
+ #define R_ETHSW_P1_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC7  ======================================================= */
+ #define R_ETHSW_P1_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QMDESC0  ======================================================= */
+ #define R_ETHSW_P1_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC1  ======================================================= */
+ #define R_ETHSW_P1_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC2  ======================================================= */
+ #define R_ETHSW_P1_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC3  ======================================================= */
+ #define R_ETHSW_P1_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC4  ======================================================= */
+ #define R_ETHSW_P1_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC5  ======================================================= */
+ #define R_ETHSW_P1_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC6  ======================================================= */
+ #define R_ETHSW_P1_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC7  ======================================================= */
+ #define R_ETHSW_P1_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMCBSC0  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC1  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC2  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC3  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC4  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC5  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC6  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC7  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCIRC0  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC1  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC2  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC3  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC4  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC5  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC6  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC7  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* =======================================================  P1_QMGPC0  ======================================================= */
+ #define R_ETHSW_P1_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC1  ======================================================= */
+ #define R_ETHSW_P1_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC2  ======================================================= */
+ #define R_ETHSW_P1_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC3  ======================================================= */
+ #define R_ETHSW_P1_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC4  ======================================================= */
+ #define R_ETHSW_P1_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC5  ======================================================= */
+ #define R_ETHSW_P1_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC6  ======================================================= */
+ #define R_ETHSW_P1_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC7  ======================================================= */
+ #define R_ETHSW_P1_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC0  ======================================================= */
+ #define R_ETHSW_P1_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC1  ======================================================= */
+ #define R_ETHSW_P1_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC2  ======================================================= */
+ #define R_ETHSW_P1_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC3  ======================================================= */
+ #define R_ETHSW_P1_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC4  ======================================================= */
+ #define R_ETHSW_P1_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC5  ======================================================= */
+ #define R_ETHSW_P1_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC6  ======================================================= */
+ #define R_ETHSW_P1_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC7  ======================================================= */
+ #define R_ETHSW_P1_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMACU0  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU1  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU2  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU3  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU4  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU5  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU6  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU7  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACD0  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD1  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD2  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD3  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD4  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD5  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD6  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD7  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMAMU0  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU1  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU2  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU3  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU4  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU5  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU6  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU7  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMD0  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD1  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD2  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD3  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD4  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD5  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD6  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD7  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSFTVL0  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL1  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL2  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL3  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL4  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL5  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL6  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL7  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVLM0  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM1  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM2  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM3  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM4  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM5  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM6  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM7  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTBL0  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL1  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL2  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL3  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL4  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL5  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL6  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL7  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  P2_QSMFC0  ======================================================= */
+ #define R_ETHSW_P2_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC1  ======================================================= */
+ #define R_ETHSW_P2_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC2  ======================================================= */
+ #define R_ETHSW_P2_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC3  ======================================================= */
+ #define R_ETHSW_P2_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC4  ======================================================= */
+ #define R_ETHSW_P2_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC5  ======================================================= */
+ #define R_ETHSW_P2_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC6  ======================================================= */
+ #define R_ETHSW_P2_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC7  ======================================================= */
+ #define R_ETHSW_P2_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QMSPPC0  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC1  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC2  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC3  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC4  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC5  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC6  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC7  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC0  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC1  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC2  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC3  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC4  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC5  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC6  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC7  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  P2_QGDPC0  ======================================================= */
+ #define R_ETHSW_P2_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC1  ======================================================= */
+ #define R_ETHSW_P2_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC2  ======================================================= */
+ #define R_ETHSW_P2_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC3  ======================================================= */
+ #define R_ETHSW_P2_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC4  ======================================================= */
+ #define R_ETHSW_P2_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC5  ======================================================= */
+ #define R_ETHSW_P2_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC6  ======================================================= */
+ #define R_ETHSW_P2_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC7  ======================================================= */
+ #define R_ETHSW_P2_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QMDESC0  ======================================================= */
+ #define R_ETHSW_P2_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC1  ======================================================= */
+ #define R_ETHSW_P2_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC2  ======================================================= */
+ #define R_ETHSW_P2_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC3  ======================================================= */
+ #define R_ETHSW_P2_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC4  ======================================================= */
+ #define R_ETHSW_P2_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC5  ======================================================= */
+ #define R_ETHSW_P2_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC6  ======================================================= */
+ #define R_ETHSW_P2_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC7  ======================================================= */
+ #define R_ETHSW_P2_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMCBSC0  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC1  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC2  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC3  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC4  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC5  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC6  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC7  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCIRC0  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC1  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC2  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC3  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC4  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC5  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC6  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC7  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* =======================================================  P2_QMGPC0  ======================================================= */
+ #define R_ETHSW_P2_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC1  ======================================================= */
+ #define R_ETHSW_P2_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC2  ======================================================= */
+ #define R_ETHSW_P2_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC3  ======================================================= */
+ #define R_ETHSW_P2_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC4  ======================================================= */
+ #define R_ETHSW_P2_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC5  ======================================================= */
+ #define R_ETHSW_P2_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC6  ======================================================= */
+ #define R_ETHSW_P2_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC7  ======================================================= */
+ #define R_ETHSW_P2_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC0  ======================================================= */
+ #define R_ETHSW_P2_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC1  ======================================================= */
+ #define R_ETHSW_P2_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC2  ======================================================= */
+ #define R_ETHSW_P2_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC3  ======================================================= */
+ #define R_ETHSW_P2_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC4  ======================================================= */
+ #define R_ETHSW_P2_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC5  ======================================================= */
+ #define R_ETHSW_P2_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC6  ======================================================= */
+ #define R_ETHSW_P2_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC7  ======================================================= */
+ #define R_ETHSW_P2_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =====================================================  STATN_STATUS  ====================================================== */
+ #define R_ETHSW_STATN_STATUS_BUSY_Pos                                    (0UL)          /*!< BUSY (Bit 0)                                          */
+ #define R_ETHSW_STATN_STATUS_BUSY_Msk                                    (0x1UL)        /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* =====================================================  STATN_CONFIG  ====================================================== */
+ #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Pos                           (1UL)          /*!< CLEAR_ON_READ (Bit 1)                                 */
+ #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Msk                           (0x2UL)        /*!< CLEAR_ON_READ (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_STATN_CONFIG_RESET_Pos                                   (31UL)         /*!< RESET (Bit 31)                                        */
+ #define R_ETHSW_STATN_CONFIG_RESET_Msk                                   (0x80000000UL) /*!< RESET (Bitfield-Mask: 0x01)                           */
+/* =====================================================  STATN_CONTROL  ===================================================== */
+ #define R_ETHSW_STATN_CONTROL_CHANMASK_Pos                               (0UL)          /*!< CHANMASK (Bit 0)                                      */
+ #define R_ETHSW_STATN_CONTROL_CHANMASK_Msk                               (0xfUL)        /*!< CHANMASK (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Pos                              (29UL)         /*!< CLEAR_PRE (Bit 29)                                    */
+ #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Msk                              (0x20000000UL) /*!< CLEAR_PRE (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Pos                              (31UL)         /*!< CMD_CLEAR (Bit 31)                                    */
+ #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Msk                              (0x80000000UL) /*!< CMD_CLEAR (Bitfield-Mask: 0x01)                       */
+/* ==================================================  STATN_CLEARVALUE_LO  ================================================== */
+ #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Pos              (0UL)          /*!< STATN_CLEARVALUE_LO (Bit 0)                           */
+ #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Msk              (0xffffffffUL) /*!< STATN_CLEARVALUE_LO (Bitfield-Mask: 0xffffffff) */
+/* ========================================================  ODISC0  ========================================================= */
+ #define R_ETHSW_ODISC0_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
+ #define R_ETHSW_ODISC0_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  ODISC1  ========================================================= */
+ #define R_ETHSW_ODISC1_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
+ #define R_ETHSW_ODISC1_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  ODISC2  ========================================================= */
+ #define R_ETHSW_ODISC2_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
+ #define R_ETHSW_ODISC2_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  ODISC3  ========================================================= */
+ #define R_ETHSW_ODISC3_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
+ #define R_ETHSW_ODISC3_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  IDISC_VLAN0  ====================================================== */
+ #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
+ #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  IDISC_VLAN1  ====================================================== */
+ #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
+ #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  IDISC_VLAN2  ====================================================== */
+ #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
+ #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  IDISC_VLAN3  ====================================================== */
+ #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
+ #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  IDISC_UNTAGGED0  ==================================================== */
+ #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
+ #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  IDISC_UNTAGGED1  ==================================================== */
+ #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
+ #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  IDISC_UNTAGGED2  ==================================================== */
+ #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
+ #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  IDISC_UNTAGGED3  ==================================================== */
+ #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
+ #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  IDISC_BLOCKED0  ===================================================== */
+ #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
+ #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  IDISC_BLOCKED1  ===================================================== */
+ #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
+ #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  IDISC_BLOCKED2  ===================================================== */
+ #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
+ #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  IDISC_BLOCKED3  ===================================================== */
+ #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
+ #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
+/* ======================================================  IDISC_ANY0  ======================================================= */
+ #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
+ #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  IDISC_ANY1  ======================================================= */
+ #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
+ #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  IDISC_ANY2  ======================================================= */
+ #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
+ #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  IDISC_ANY3  ======================================================= */
+ #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
+ #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
+/* =====================================================  IDISC_SRCFLT0  ===================================================== */
+ #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
+ #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
+/* =====================================================  IDISC_SRCFLT1  ===================================================== */
+ #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
+ #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
+/* =====================================================  IDISC_SRCFLT2  ===================================================== */
+ #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
+ #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  TX_HOLD_REQ_CNT0  ==================================================== */
+ #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
+ #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
+/* ===================================================  TX_HOLD_REQ_CNT1  ==================================================== */
+ #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
+ #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
+/* ===================================================  TX_HOLD_REQ_CNT2  ==================================================== */
+ #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
+ #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
+/* =====================================================  TX_FRAG_CNT0  ====================================================== */
+ #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  TX_FRAG_CNT1  ====================================================== */
+ #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  TX_FRAG_CNT2  ====================================================== */
+ #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  RX_FRAG_CNT0  ====================================================== */
+ #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  RX_FRAG_CNT1  ====================================================== */
+ #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  RX_FRAG_CNT2  ====================================================== */
+ #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* ====================================================  RX_ASSY_OK_CNT0  ==================================================== */
+ #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  RX_ASSY_OK_CNT1  ==================================================== */
+ #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  RX_ASSY_OK_CNT2  ==================================================== */
+ #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  RX_ASSY_ERR_CNT0  ==================================================== */
+ #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
+ #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
+/* ===================================================  RX_ASSY_ERR_CNT1  ==================================================== */
+ #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
+ #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
+/* ===================================================  RX_ASSY_ERR_CNT2  ==================================================== */
+ #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
+ #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
+/* ====================================================  RX_SMD_ERR_CNT0  ==================================================== */
+ #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
+/* ====================================================  RX_SMD_ERR_CNT1  ==================================================== */
+ #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
+/* ====================================================  RX_SMD_ERR_CNT2  ==================================================== */
+ #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
+/* ===================================================  TX_VERIFY_OK_CNT0  =================================================== */
+ #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ===================================================  TX_VERIFY_OK_CNT1  =================================================== */
+ #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ===================================================  TX_VERIFY_OK_CNT2  =================================================== */
+ #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ==================================================  TX_RESPONSE_OK_CNT0  ================================================== */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  TX_RESPONSE_OK_CNT1  ================================================== */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  TX_RESPONSE_OK_CNT2  ================================================== */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ===================================================  RX_VERIFY_OK_CNT0  =================================================== */
+ #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ===================================================  RX_VERIFY_OK_CNT1  =================================================== */
+ #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ===================================================  RX_VERIFY_OK_CNT2  =================================================== */
+ #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ==================================================  RX_RESPONSE_OK_CNT0  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  RX_RESPONSE_OK_CNT1  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  RX_RESPONSE_OK_CNT2  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  RX_VERIFY_BAD_CNT0  =================================================== */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
+/* ==================================================  RX_VERIFY_BAD_CNT1  =================================================== */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
+/* ==================================================  RX_VERIFY_BAD_CNT2  =================================================== */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
+/* =================================================  RX_RESPONSE_BAD_CNT0  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
+/* =================================================  RX_RESPONSE_BAD_CNT1  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
+/* =================================================  RX_RESPONSE_BAD_CNT2  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
+/* =====================================================  MMCTL_OUT_CT  ====================================================== */
+ #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Pos                              (0UL)          /*!< CT_OVR_ENA (Bit 0)                                    */
+ #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Msk                              (0x7UL)        /*!< CT_OVR_ENA (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Pos                                  (16UL)         /*!< CT_OVR (Bit 16)                                       */
+ #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Msk                                  (0x70000UL)    /*!< CT_OVR (Bitfield-Mask: 0x07)                          */
+/* ==================================================  MMCTL_CTFL_P0_3_ENA  ================================================== */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Pos                      (0UL)          /*!< CTFL_P0_ENA (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Msk                      (0xffUL)       /*!< CTFL_P0_ENA (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Pos                      (8UL)          /*!< CTFL_P1_ENA (Bit 8)                                   */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Msk                      (0xff00UL)     /*!< CTFL_P1_ENA (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Pos                      (16UL)         /*!< CTFL_P2_ENA (Bit 16)                                  */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Msk                      (0xff0000UL)   /*!< CTFL_P2_ENA (Bitfield-Mask: 0xff)                     */
+/* ==============================================  MMCTL_YELLOW_BYTE_LENGTH_P  =============================================== */
+ #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Pos                (2UL)          /*!< YELLOW_LEN (Bit 2)                                    */
+ #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Msk                (0xfffcUL)     /*!< YELLOW_LEN (Bitfield-Mask: 0x3fff)                   */
+ #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Pos                   (16UL)         /*!< YLEN_EN (Bit 16)                                      */
+ #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Msk                   (0x10000UL)    /*!< YLEN_EN (Bitfield-Mask: 0x01)                         */
+/* ====================================================  MMCTL_POOL0_CTR  ==================================================== */
+ #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Pos                                (0UL)          /*!< CELLS (Bit 0)                                         */
+ #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Msk                                (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
+ #define R_ETHSW_MMCTL_POOL0_CTR_USED_Pos                                 (16UL)         /*!< USED (Bit 16)                                         */
+ #define R_ETHSW_MMCTL_POOL0_CTR_USED_Msk                                 (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
+/* ====================================================  MMCTL_POOL1_CTR  ==================================================== */
+ #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Pos                                (0UL)          /*!< CELLS (Bit 0)                                         */
+ #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Msk                                (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
+ #define R_ETHSW_MMCTL_POOL1_CTR_USED_Pos                                 (16UL)         /*!< USED (Bit 16)                                         */
+ #define R_ETHSW_MMCTL_POOL1_CTR_USED_Msk                                 (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
+/* ===================================================  MMCTL_POOL_GLOBAL  =================================================== */
+ #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Pos                              (0UL)          /*!< CELLS (Bit 0)                                         */
+ #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Msk                              (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
+ #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Pos                               (16UL)         /*!< USED (Bit 16)                                         */
+ #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Msk                               (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
+/* ===================================================  MMCTL_POOL_STATUS  =================================================== */
+ #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Pos                         (0UL)          /*!< QUEUE_FULL (Bit 0)                                    */
+ #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Msk                         (0xffUL)       /*!< QUEUE_FULL (Bitfield-Mask: 0xff)                      */
+/* ====================================================  MMCTL_POOL_QMAP  ==================================================== */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Pos                               (0UL)          /*!< Q0_MAP (Bit 0)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Msk                               (0x1UL)        /*!< Q0_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Pos                               (3UL)          /*!< Q0_ENA (Bit 3)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Msk                               (0x8UL)        /*!< Q0_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Pos                               (4UL)          /*!< Q1_MAP (Bit 4)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Msk                               (0x10UL)       /*!< Q1_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Pos                               (7UL)          /*!< Q1_ENA (Bit 7)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Msk                               (0x80UL)       /*!< Q1_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Pos                               (8UL)          /*!< Q2_MAP (Bit 8)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Msk                               (0x100UL)      /*!< Q2_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Pos                               (11UL)         /*!< Q2_ENA (Bit 11)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Msk                               (0x800UL)      /*!< Q2_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Pos                               (12UL)         /*!< Q3_MAP (Bit 12)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Msk                               (0x1000UL)     /*!< Q3_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Pos                               (15UL)         /*!< Q3_ENA (Bit 15)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Msk                               (0x8000UL)     /*!< Q3_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Pos                               (16UL)         /*!< Q4_MAP (Bit 16)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Msk                               (0x10000UL)    /*!< Q4_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Pos                               (19UL)         /*!< Q4_ENA (Bit 19)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Msk                               (0x80000UL)    /*!< Q4_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Pos                               (20UL)         /*!< Q5_MAP (Bit 20)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Msk                               (0x100000UL)   /*!< Q5_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Pos                               (23UL)         /*!< Q5_ENA (Bit 23)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Msk                               (0x800000UL)   /*!< Q5_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Pos                               (24UL)         /*!< Q6_MAP (Bit 24)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Msk                               (0x1000000UL)  /*!< Q6_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Pos                               (27UL)         /*!< Q6_ENA (Bit 27)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Msk                               (0x8000000UL)  /*!< Q6_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Pos                               (28UL)         /*!< Q7_MAP (Bit 28)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Msk                               (0x10000000UL) /*!< Q7_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Pos                               (31UL)         /*!< Q7_ENA (Bit 31)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Msk                               (0x80000000UL) /*!< Q7_ENA (Bitfield-Mask: 0x01)                          */
+/* ======================================================  MMCTL_QGATE  ====================================================== */
+ #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Pos                                (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Msk                                (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Pos                               (16UL)         /*!< QUEUE_GATE (Bit 16)                                   */
+ #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Msk                               (0xffff0000UL) /*!< QUEUE_GATE (Bitfield-Mask: 0xffff)                    */
+/* ======================================================  MMCTL_QTRIG  ====================================================== */
+ #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Pos                                (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Msk                                (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Pos                               (16UL)         /*!< QUEUE_TRIG (Bit 16)                                   */
+ #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Msk                               (0xff0000UL)   /*!< QUEUE_TRIG (Bitfield-Mask: 0xff)                      */
+/* =====================================================  MMCTL_QFLUSH  ====================================================== */
+ #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Pos                               (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Msk                               (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Pos                              (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
+ #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Msk                              (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_MMCTL_QFLUSH_ACTION_Pos                                  (24UL)         /*!< ACTION (Bit 24)                                       */
+ #define R_ETHSW_MMCTL_QFLUSH_ACTION_Msk                                  (0x3000000UL)  /*!< ACTION (Bitfield-Mask: 0x03)                          */
+/* ===============================================  MMCTL_QCLOSED_STATUS_P0_3  =============================================== */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Pos                  (0UL)          /*!< P0_STATUS (Bit 0)                                     */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Msk                  (0xffUL)       /*!< P0_STATUS (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Pos                  (8UL)          /*!< P1_STATUS (Bit 8)                                     */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Msk                  (0xff00UL)     /*!< P1_STATUS (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Pos                  (16UL)         /*!< P2_STATUS (Bit 16)                                    */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Msk                  (0xff0000UL)   /*!< P2_STATUS (Bitfield-Mask: 0xff)                      */
+/* ==================================================  MMCTL_1FRAME_MODE_P  ================================================== */
+ #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Pos                     (0UL)          /*!< Q_1FRAME_ENA (Bit 0)                                  */
+ #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Msk                     (0xffUL)       /*!< Q_1FRAME_ENA (Bitfield-Mask: 0xff)                    */
+ #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Pos                        (16UL)         /*!< Q_BUF_ENA (Bit 16)                                    */
+ #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Msk                        (0xff0000UL)   /*!< Q_BUF_ENA (Bitfield-Mask: 0xff)                       */
+/* ================================================  MMCTL_P0_3_QUEUE_STATUS  ================================================ */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Pos                  (0UL)          /*!< P0_Q_STATUS (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Msk                  (0xffUL)       /*!< P0_Q_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Pos                  (8UL)          /*!< P1_Q_STATUS (Bit 8)                                   */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Msk                  (0xff00UL)     /*!< P1_Q_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Pos                  (16UL)         /*!< P2_Q_STATUS (Bit 16)                                  */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Msk                  (0xff0000UL)   /*!< P2_Q_STATUS (Bitfield-Mask: 0xff)                    */
+/* ================================================  MMCTL_P0_3_FLUSH_STATUS  ================================================ */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Pos                  (0UL)          /*!< P0_F_STATUS (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Msk                  (0xffUL)       /*!< P0_F_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Pos                  (8UL)          /*!< P1_F_STATUS (Bit 8)                                   */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Msk                  (0xff00UL)     /*!< P1_F_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Pos                  (16UL)         /*!< P2_F_STATUS (Bit 16)                                  */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Msk                  (0xff0000UL)   /*!< P2_F_STATUS (Bitfield-Mask: 0xff)                    */
+/* ================================================  MMCTL_DLY_QTRIGGER_CTRL  ================================================ */
+ #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Pos                   (0UL)          /*!< DELAY_TIME (Bit 0)                                    */
+ #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Msk                   (0x3fffffffUL) /*!< DELAY_TIME (Bitfield-Mask: 0x3fffffff)              */
+ #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Pos                    (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Msk                    (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                      */
+/* =================================================  MMCTL_PREEMPT_QUEUES  ================================================== */
+ #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Pos                     (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Msk                     (0xffUL)       /*!< PREEMPT_ENA (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Pos               (8UL)          /*!< PREEMPT_ON_QCLOSE (Bit 8)                             */
+ #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Msk               (0xff00UL)     /*!< PREEMPT_ON_QCLOSE (Bitfield-Mask: 0xff)             */
+/* ==================================================  MMCTL_HOLD_CONTROL  =================================================== */
+ #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Pos                  (0UL)          /*!< Q_HOLD_REQ_FORCE (Bit 0)                              */
+ #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Msk                  (0x7UL)        /*!< Q_HOLD_REQ_FORCE (Bitfield-Mask: 0x07)                */
+ #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Pos                (16UL)         /*!< Q_HOLD_REQ_RELEASE (Bit 16)                           */
+ #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Msk                (0x70000UL)    /*!< Q_HOLD_REQ_RELEASE (Bitfield-Mask: 0x07)            */
+/* =================================================  MMCTL_PREEMPT_STATUS  ================================================== */
+ #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Pos                   (0UL)          /*!< PREEMPT_STATE (Bit 0)                                 */
+ #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Msk                   (0x7UL)        /*!< PREEMPT_STATE (Bitfield-Mask: 0x07)                   */
+ #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Pos                  (16UL)         /*!< HOLD_REQ_STATE (Bit 16)                               */
+ #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Msk                  (0x70000UL)    /*!< HOLD_REQ_STATE (Bitfield-Mask: 0x07)                  */
+/* ===================================================  MMCTL_CQF_CTRL_P  ==================================================== */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Pos                        (0UL)          /*!< PRIO_ENABLE0 (Bit 0)                                  */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Msk                        (0xffUL)       /*!< PRIO_ENABLE0 (Bitfield-Mask: 0xff)                    */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Pos                          (8UL)          /*!< QUEUE_SEL0 (Bit 8)                                    */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Msk                          (0x700UL)      /*!< QUEUE_SEL0 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Pos                           (11UL)         /*!< GATE_SEL0 (Bit 11)                                    */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Msk                           (0x3800UL)     /*!< GATE_SEL0 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Pos                            (14UL)         /*!< USE_SOP0 (Bit 14)                                     */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Msk                            (0x4000UL)     /*!< USE_SOP0 (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Pos                            (15UL)         /*!< REF_SEL0 (Bit 15)                                     */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Msk                            (0x8000UL)     /*!< REF_SEL0 (Bitfield-Mask: 0x01)                        */
+/* ==============================================  MMCTL_P0_3_QCLOSED_NONEMPTY  ============================================== */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Pos              (0UL)          /*!< P0_Q_STATUS (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Msk              (0xffUL)       /*!< P0_Q_STATUS (Bitfield-Mask: 0xff)                    */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Pos              (8UL)          /*!< P1_Q_STATUS (Bit 8)                                   */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Msk              (0xff00UL)     /*!< P1_Q_STATUS (Bitfield-Mask: 0xff)                  */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Pos              (16UL)         /*!< P2_Q_STATUS (Bit 16)                                  */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Msk              (0xff0000UL)   /*!< P2_Q_STATUS (Bitfield-Mask: 0xff)                */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Pos              (24UL)         /*!< P3_Q_STATUS (Bit 24)                                  */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Msk              (0xff000000UL) /*!< P3_Q_STATUS (Bitfield-Mask: 0xff)              */
+/* ==================================================  MMCTL_PREEMPT_EXTRA  ================================================== */
+ #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Pos                     (0UL)          /*!< MIN_PFRM_ADJ (Bit 0)                                  */
+ #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Msk                     (0xfUL)        /*!< MIN_PFRM_ADJ (Bitfield-Mask: 0x0f)                    */
+ #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Pos                    (4UL)          /*!< LAST_PFRM_ADJ (Bit 4)                                 */
+ #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Msk                    (0xf0UL)       /*!< LAST_PFRM_ADJ (Bitfield-Mask: 0x0f)                   */
+/* ======================================================  DLR_CONTROL  ====================================================== */
+ #define R_ETHSW_DLR_CONTROL_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ETHSW_DLR_CONTROL_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Pos                                (1UL)          /*!< AUTOFLUSH (Bit 1)                                     */
+ #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Msk                                (0x2UL)        /*!< AUTOFLUSH (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Pos                          (2UL)          /*!< LOOP_FILTER_ENA (Bit 2)                               */
+ #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Msk                          (0x4UL)        /*!< LOOP_FILTER_ENA (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Pos                             (4UL)          /*!< IGNORE_INVTM (Bit 4)                                  */
+ #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Msk                             (0x10UL)       /*!< IGNORE_INVTM (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_DLR_CONTROL_US_TIME_Pos                                  (8UL)          /*!< US_TIME (Bit 8)                                       */
+ #define R_ETHSW_DLR_CONTROL_US_TIME_Msk                                  (0xfff00UL)    /*!< US_TIME (Bitfield-Mask: 0xfff)                        */
+/* ======================================================  DLR_STATUS  ======================================================= */
+ #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Pos                            (0UL)          /*!< LastBcnRcvPort (Bit 0)                                */
+ #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Msk                            (0x3UL)        /*!< LastBcnRcvPort (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_DLR_STATUS_NODE_STATE_Pos                                (8UL)          /*!< NODE_STATE (Bit 8)                                    */
+ #define R_ETHSW_DLR_STATUS_NODE_STATE_Msk                                (0xff00UL)     /*!< NODE_STATE (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_DLR_STATUS_LINK_STATUS_Pos                               (16UL)         /*!< LINK_STATUS (Bit 16)                                  */
+ #define R_ETHSW_DLR_STATUS_LINK_STATUS_Msk                               (0x30000UL)    /*!< LINK_STATUS (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_DLR_STATUS_TOPOLOGY_Pos                                  (24UL)         /*!< TOPOLOGY (Bit 24)                                     */
+ #define R_ETHSW_DLR_STATUS_TOPOLOGY_Msk                                  (0xff000000UL) /*!< TOPOLOGY (Bitfield-Mask: 0xff)                        */
+/* ======================================================  DLR_ETH_TYP  ====================================================== */
+ #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Pos                              (0UL)          /*!< DLR_ETH_TYP (Bit 0)                                   */
+ #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Msk                              (0xffffUL)     /*!< DLR_ETH_TYP (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  DLR_IRQ_CONTROL  ==================================================== */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Pos                   (0UL)          /*!< IRQ_state_chng_ena (Bit 0)                            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Msk                   (0x1UL)        /*!< IRQ_state_chng_ena (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Pos                (1UL)          /*!< IRQ_flush_macaddr_ena (Bit 1)                         */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Msk                (0x2UL)        /*!< IRQ_flush_macaddr_ena (Bitfield-Mask: 0x01)           */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Pos                  (2UL)          /*!< IRQ_stop_nbchk0_ena (Bit 2)                           */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Msk                  (0x4UL)        /*!< IRQ_stop_nbchk0_ena (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Pos                  (3UL)          /*!< IRQ_stop_nbchk1_ena (Bit 3)                           */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Msk                  (0x8UL)        /*!< IRQ_stop_nbchk1_ena (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Pos                 (4UL)          /*!< IRQ_bec_tmr0_exp_ena (Bit 4)                          */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Msk                 (0x10UL)       /*!< IRQ_bec_tmr0_exp_ena (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Pos                 (5UL)          /*!< IRQ_bec_tmr1_exp_ena (Bit 5)                          */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Msk                 (0x20UL)       /*!< IRQ_bec_tmr1_exp_ena (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Pos                    (6UL)          /*!< IRQ_supr_chng_ena (Bit 6)                             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Msk                    (0x40UL)       /*!< IRQ_supr_chng_ena (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Pos                   (7UL)          /*!< IRQ_link_chng0_ena (Bit 7)                            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Msk                   (0x80UL)       /*!< IRQ_link_chng0_ena (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Pos                   (8UL)          /*!< IRQ_link_chng1_ena (Bit 8)                            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Msk                   (0x100UL)      /*!< IRQ_link_chng1_ena (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Pos                   (9UL)          /*!< IRQ_sup_ignord_ena (Bit 9)                            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Msk                   (0x200UL)      /*!< IRQ_sup_ignord_ena (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Pos                 (10UL)         /*!< IRQ_ip_addr_chng_ena (Bit 10)                         */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Msk                 (0x400UL)      /*!< IRQ_ip_addr_chng_ena (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Pos                  (11UL)         /*!< IRQ_invalid_tmr_ena (Bit 11)                          */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Msk                  (0x800UL)      /*!< IRQ_invalid_tmr_ena (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Pos                     (12UL)         /*!< IRQ_bec_rcv0_ena (Bit 12)                             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Msk                     (0x1000UL)     /*!< IRQ_bec_rcv0_ena (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Pos                     (13UL)         /*!< IRQ_bec_rcv1_ena (Bit 13)                             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Msk                     (0x2000UL)     /*!< IRQ_bec_rcv1_ena (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Pos                       (14UL)         /*!< IRQ_frm_dscrd0 (Bit 14)                               */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Msk                       (0x4000UL)     /*!< IRQ_frm_dscrd0 (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Pos                       (15UL)         /*!< IRQ_frm_dscrd1 (Bit 15)                               */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Msk                       (0x8000UL)     /*!< IRQ_frm_dscrd1 (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Pos                           (29UL)         /*!< low_int_en (Bit 29)                                   */
+ #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Msk                           (0x20000000UL) /*!< low_int_en (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Pos                            (30UL)         /*!< atomic_OR (Bit 30)                                    */
+ #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Msk                            (0x40000000UL) /*!< atomic_OR (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Pos                           (31UL)         /*!< atomic_AND (Bit 31)                                   */
+ #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Msk                           (0x80000000UL) /*!< atomic_AND (Bitfield-Mask: 0x01)                      */
+/* ===================================================  DLR_IRQ_STAT_ACK  ==================================================== */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Pos              (0UL)          /*!< state_chng_IRQ_pending (Bit 0)                        */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Msk              (0x1UL)        /*!< state_chng_IRQ_pending (Bitfield-Mask: 0x01)          */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Pos                   (1UL)          /*!< flush_IRQ_pending (Bit 1)                             */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Msk                   (0x2UL)        /*!< flush_IRQ_pending (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Pos                  (2UL)          /*!< nbchk0_IRQ_pending (Bit 2)                            */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Msk                  (0x4UL)        /*!< nbchk0_IRQ_pending (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Pos                  (3UL)          /*!< nbchk1_IRQ_pending (Bit 3)                            */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Msk                  (0x8UL)        /*!< nbchk1_IRQ_pending (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Pos                (4UL)          /*!< bec_tmr0_IRQ_pending (Bit 4)                          */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Msk                (0x10UL)       /*!< bec_tmr0_IRQ_pending (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Pos                (5UL)          /*!< bec_tmr1_IRQ_pending (Bit 5)                          */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Msk                (0x20UL)       /*!< bec_tmr1_IRQ_pending (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Pos               (6UL)          /*!< supr_chng_IRQ_pending (Bit 6)                         */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Msk               (0x40UL)       /*!< supr_chng_IRQ_pending (Bitfield-Mask: 0x01)           */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Pos                   (7UL)          /*!< Link0_IRQ_pending (Bit 7)                             */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Msk                   (0x80UL)       /*!< Link0_IRQ_pending (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Pos                   (8UL)          /*!< Link1_IRQ_pending (Bit 8)                             */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Msk                   (0x100UL)      /*!< Link1_IRQ_pending (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Pos              (9UL)          /*!< sup_ignord_IRQ_pending (Bit 9)                        */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Msk              (0x200UL)      /*!< sup_ignord_IRQ_pending (Bitfield-Mask: 0x01)        */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Pos                 (10UL)         /*!< ip_chng_IRQ_pending (Bit 10)                          */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Msk                 (0x400UL)      /*!< ip_chng_IRQ_pending (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Pos             (11UL)         /*!< invalid_tmr_IRQ_pending (Bit 11)                      */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Msk             (0x800UL)      /*!< invalid_tmr_IRQ_pending (Bitfield-Mask: 0x01)      */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Pos                (12UL)         /*!< bec_rcv0_IRQ_pending (Bit 12)                         */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Msk                (0x1000UL)     /*!< bec_rcv0_IRQ_pending (Bitfield-Mask: 0x01)           */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Pos                (13UL)         /*!< bec_rcv1_IRQ_pending (Bit 13)                         */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Msk                (0x2000UL)     /*!< bec_rcv1_IRQ_pending (Bitfield-Mask: 0x01)           */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Pos              (14UL)         /*!< frm_dscrd0_IRQ_pending (Bit 14)                       */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Msk              (0x4000UL)     /*!< frm_dscrd0_IRQ_pending (Bitfield-Mask: 0x01)       */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Pos              (15UL)         /*!< frm_dscrd1_IRQ_pending (Bit 15)                       */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Msk              (0x8000UL)     /*!< frm_dscrd1_IRQ_pending (Bitfield-Mask: 0x01)       */
+/* =====================================================  DLR_LOC_MAClo  ===================================================== */
+ #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Pos                                (0UL)          /*!< LOC_MAC (Bit 0)                                       */
+ #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Msk                                (0xffffffffUL) /*!< LOC_MAC (Bitfield-Mask: 0xffffffff)                   */
+/* =====================================================  DLR_LOC_MAChi  ===================================================== */
+ #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Pos                                (0UL)          /*!< LOC_MAC (Bit 0)                                       */
+ #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Msk                                (0xffffUL)     /*!< LOC_MAC (Bitfield-Mask: 0xffff)                       */
+/* ====================================================  DLR_SUPR_MAClo  ===================================================== */
+ #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Pos                              (0UL)          /*!< SUPR_MAC (Bit 0)                                      */
+ #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Msk                              (0xffffffffUL) /*!< SUPR_MAC (Bitfield-Mask: 0xffffffff)                  */
+/* ====================================================  DLR_SUPR_MAChi  ===================================================== */
+ #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Pos                              (0UL)          /*!< SUPR_MAC (Bit 0)                                      */
+ #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Msk                              (0xffffUL)     /*!< SUPR_MAC (Bitfield-Mask: 0xffff)                      */
+ #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Pos                                 (16UL)         /*!< PRECE (Bit 16)                                        */
+ #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Msk                                 (0xff0000UL)   /*!< PRECE (Bitfield-Mask: 0xff)                           */
+/* ====================================================  DLR_STATE_VLAN  ===================================================== */
+ #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Pos                              (0UL)          /*!< RINGSTAT (Bit 0)                                      */
+ #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Msk                              (0xffUL)       /*!< RINGSTAT (Bitfield-Mask: 0xff)                        */
+ #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Pos                             (8UL)          /*!< VLANVALID (Bit 8)                                     */
+ #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Msk                             (0x100UL)      /*!< VLANVALID (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Pos                              (16UL)         /*!< VLANINFO (Bit 16)                                     */
+ #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Msk                              (0xffff0000UL) /*!< VLANINFO (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  DLR_BEC_TMOUT  ===================================================== */
+ #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Pos                              (0UL)          /*!< BEC_TMOUT (Bit 0)                                     */
+ #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Msk                              (0xffffffffUL) /*!< BEC_TMOUT (Bitfield-Mask: 0xffffffff)                 */
+/* ====================================================  DLR_BEC_INTRVL  ===================================================== */
+ #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Pos                            (0UL)          /*!< BEC_INTRVL (Bit 0)                                    */
+ #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Msk                            (0xffffffffUL) /*!< BEC_INTRVL (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  DLR_SUPR_IPADR  ===================================================== */
+ #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Pos                            (0UL)          /*!< SUPR_IPADR (Bit 0)                                    */
+ #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Msk                            (0xffffffffUL) /*!< SUPR_IPADR (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  DLR_ETH_STYP_VER  ==================================================== */
+ #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Pos                             (0UL)          /*!< SUBTYPE (Bit 0)                                       */
+ #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Msk                             (0xffUL)       /*!< SUBTYPE (Bitfield-Mask: 0xff)                         */
+ #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Pos                             (8UL)          /*!< PROTVER (Bit 8)                                       */
+ #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Msk                             (0xff00UL)     /*!< PROTVER (Bitfield-Mask: 0xff)                         */
+ #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Pos                               (16UL)         /*!< SPORT (Bit 16)                                        */
+ #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Msk                               (0xff0000UL)   /*!< SPORT (Bitfield-Mask: 0xff)                           */
+/* =====================================================  DLR_INV_TMOUT  ===================================================== */
+ #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Pos                              (0UL)          /*!< INV_TMOUT (Bit 0)                                     */
+ #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Msk                              (0xffffffffUL) /*!< INV_TMOUT (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  DLR_SEQ_ID  ======================================================= */
+ #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Pos                                    (0UL)          /*!< SEQ_ID (Bit 0)                                        */
+ #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Msk                                    (0xffffffffUL) /*!< SEQ_ID (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  DLR_DSTlo  ======================================================= */
+ #define R_ETHSW_DLR_DSTlo_DLR_DST_Pos                                    (0UL)          /*!< DLR_DST (Bit 0)                                       */
+ #define R_ETHSW_DLR_DSTlo_DLR_DST_Msk                                    (0xffffffffUL) /*!< DLR_DST (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  DLR_DSThi  ======================================================= */
+ #define R_ETHSW_DLR_DSThi_DLR_DST_Pos                                    (0UL)          /*!< DLR_DST (Bit 0)                                       */
+ #define R_ETHSW_DLR_DSThi_DLR_DST_Msk                                    (0xffffUL)     /*!< DLR_DST (Bitfield-Mask: 0xffff)                       */
+/* =====================================================  DLR_RX_STAT0  ====================================================== */
+ #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Pos                                (0UL)          /*!< RX_STAT0 (Bit 0)                                      */
+ #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Msk                                (0xffffffffUL) /*!< RX_STAT0 (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  DLR_RX_ERR_STAT0  ==================================================== */
+ #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Pos                        (0UL)          /*!< RX_ERR_STAT0 (Bit 0)                                  */
+ #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Msk                        (0xffffffffUL) /*!< RX_ERR_STAT0 (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  DLR_RX_LF_STAT0  ==================================================== */
+ #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Pos                          (0UL)          /*!< RX_LF_STAT0 (Bit 0)                                   */
+ #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Msk                          (0xffUL)       /*!< RX_LF_STAT0 (Bitfield-Mask: 0xff)                     */
+/* =====================================================  DLR_RX_STAT1  ====================================================== */
+ #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Pos                                (0UL)          /*!< RX_STAT1 (Bit 0)                                      */
+ #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Msk                                (0xffffffffUL) /*!< RX_STAT1 (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  DLR_RX_ERR_STAT1  ==================================================== */
+ #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Pos                        (0UL)          /*!< RX_ERR_STAT1 (Bit 0)                                  */
+ #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Msk                        (0xffffffffUL) /*!< RX_ERR_STAT1 (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  DLR_RX_LF_STAT1  ==================================================== */
+ #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Pos                          (0UL)          /*!< RX_LF_STAT1 (Bit 0)                                   */
+ #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Msk                          (0xffUL)       /*!< RX_LF_STAT1 (Bitfield-Mask: 0xff)                     */
+/* ======================================================  PRP_CONFIG  ======================================================= */
+ #define R_ETHSW_PRP_CONFIG_PRP_ENA_Pos                                   (0UL)          /*!< PRP_ENA (Bit 0)                                       */
+ #define R_ETHSW_PRP_CONFIG_PRP_ENA_Msk                                   (0x1UL)        /*!< PRP_ENA (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Pos                             (1UL)          /*!< RX_DUP_ACCEPT (Bit 1)                                 */
+ #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Msk                             (0x2UL)        /*!< RX_DUP_ACCEPT (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Pos                             (2UL)          /*!< RX_REMOVE_RCT (Bit 2)                                 */
+ #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Msk                             (0x4UL)        /*!< RX_REMOVE_RCT (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Pos                               (3UL)          /*!< TX_RCT_MODE (Bit 3)                                   */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Msk                               (0x18UL)       /*!< TX_RCT_MODE (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Pos                          (5UL)          /*!< TX_RCT_BROADCAST (Bit 5)                              */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Msk                          (0x20UL)       /*!< TX_RCT_BROADCAST (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Pos                          (6UL)          /*!< TX_RCT_MULTICAST (Bit 6)                              */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Msk                          (0x40UL)       /*!< TX_RCT_MULTICAST (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Pos                            (7UL)          /*!< TX_RCT_UNKNOWN (Bit 7)                                */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Msk                            (0x80UL)       /*!< TX_RCT_UNKNOWN (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Pos                               (8UL)          /*!< TX_RCT_1588 (Bit 8)                                   */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Msk                               (0x100UL)      /*!< TX_RCT_1588 (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Pos                           (9UL)          /*!< RCT_LEN_CHK_DIS (Bit 9)                               */
+ #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Msk                           (0x200UL)      /*!< RCT_LEN_CHK_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Pos                               (16UL)         /*!< PRP_AGE_ENA (Bit 16)                                  */
+ #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Msk                               (0x10000UL)    /*!< PRP_AGE_ENA (Bitfield-Mask: 0x01)                     */
+/* =======================================================  PRP_GROUP  ======================================================= */
+ #define R_ETHSW_PRP_GROUP_PRP_GROUP_Pos                                  (0UL)          /*!< PRP_GROUP (Bit 0)                                     */
+ #define R_ETHSW_PRP_GROUP_PRP_GROUP_Msk                                  (0x7UL)        /*!< PRP_GROUP (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_PRP_GROUP_LANB_MASK_Pos                                  (16UL)         /*!< LANB_MASK (Bit 16)                                    */
+ #define R_ETHSW_PRP_GROUP_LANB_MASK_Msk                                  (0x70000UL)    /*!< LANB_MASK (Bitfield-Mask: 0x07)                       */
+/* ======================================================  PRP_SUFFIX  ======================================================= */
+ #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Pos                                (0UL)          /*!< PRP_SUFFIX (Bit 0)                                    */
+ #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Msk                                (0xffffUL)     /*!< PRP_SUFFIX (Bitfield-Mask: 0xffff)                    */
+/* =======================================================  PRP_LANID  ======================================================= */
+ #define R_ETHSW_PRP_LANID_LANAID_Pos                                     (0UL)          /*!< LANAID (Bit 0)                                        */
+ #define R_ETHSW_PRP_LANID_LANAID_Msk                                     (0xfUL)        /*!< LANAID (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_PRP_LANID_LANBID_Pos                                     (4UL)          /*!< LANBID (Bit 4)                                        */
+ #define R_ETHSW_PRP_LANID_LANBID_Msk                                     (0xf0UL)       /*!< LANBID (Bitfield-Mask: 0x0f)                          */
+/* =========================================================  DUP_W  ========================================================= */
+ #define R_ETHSW_DUP_W_DUP_W_Pos                                          (0UL)          /*!< DUP_W (Bit 0)                                         */
+ #define R_ETHSW_DUP_W_DUP_W_Msk                                          (0xffUL)       /*!< DUP_W (Bitfield-Mask: 0xff)                           */
+/* ======================================================  PRP_AGETIME  ====================================================== */
+ #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Pos                              (0UL)          /*!< PRP_AGETIME (Bit 0)                                   */
+ #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Msk                              (0xffffffUL)   /*!< PRP_AGETIME (Bitfield-Mask: 0xffffff)                 */
+/* ====================================================  PRP_IRQ_CONTROL  ==================================================== */
+ #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Pos                           (0UL)          /*!< MEMTOOLATE (Bit 0)                                    */
+ #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Msk                           (0x1UL)        /*!< MEMTOOLATE (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Pos                             (1UL)          /*!< WRONGLAN (Bit 1)                                      */
+ #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Msk                             (0x2UL)        /*!< WRONGLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Pos                             (2UL)          /*!< OUTOFSEQ (Bit 2)                                      */
+ #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Msk                             (0x4UL)        /*!< OUTOFSEQ (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Pos                           (3UL)          /*!< SEQMISSING (Bit 3)                                    */
+ #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Msk                           (0x8UL)        /*!< SEQMISSING (Bitfield-Mask: 0x01)                      */
+/* ===================================================  PRP_IRQ_STAT_ACK  ==================================================== */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Pos                          (0UL)          /*!< MEMTOOLATE (Bit 0)                                    */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Msk                          (0x1UL)        /*!< MEMTOOLATE (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Pos                            (1UL)          /*!< WRONGLAN (Bit 1)                                      */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Msk                            (0x2UL)        /*!< WRONGLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Pos                            (2UL)          /*!< OUTOFSEQ (Bit 2)                                      */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Msk                            (0x4UL)        /*!< OUTOFSEQ (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Pos                          (3UL)          /*!< SEQMISSING (Bit 3)                                    */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Msk                          (0x8UL)        /*!< SEQMISSING (Bitfield-Mask: 0x01)                      */
+/* =====================================================  RM_ADDR_CTRL  ====================================================== */
+ #define R_ETHSW_RM_ADDR_CTRL_address_Pos                                 (0UL)          /*!< address (Bit 0)                                       */
+ #define R_ETHSW_RM_ADDR_CTRL_address_Msk                                 (0xfffUL)      /*!< address (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Pos                           (22UL)         /*!< CLEAR_DYNAMIC (Bit 22)                                */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Msk                           (0x400000UL)   /*!< CLEAR_DYNAMIC (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Pos                            (23UL)         /*!< CLEAR_MEMORY (Bit 23)                                 */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Msk                            (0x800000UL)   /*!< CLEAR_MEMORY (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_RM_ADDR_CTRL_WRITE_Pos                                   (25UL)         /*!< WRITE (Bit 25)                                        */
+ #define R_ETHSW_RM_ADDR_CTRL_WRITE_Msk                                   (0x2000000UL)  /*!< WRITE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_RM_ADDR_CTRL_READ_Pos                                    (26UL)         /*!< READ (Bit 26)                                         */
+ #define R_ETHSW_RM_ADDR_CTRL_READ_Msk                                    (0x4000000UL)  /*!< READ (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Pos                                   (29UL)         /*!< CLEAR (Bit 29)                                        */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Msk                                   (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_RM_ADDR_CTRL_BUSY_Pos                                    (31UL)         /*!< BUSY (Bit 31)                                         */
+ #define R_ETHSW_RM_ADDR_CTRL_BUSY_Msk                                    (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ========================================================  RM_DATA  ======================================================== */
+ #define R_ETHSW_RM_DATA_RM_DATA_Pos                                      (0UL)          /*!< RM_DATA (Bit 0)                                       */
+ #define R_ETHSW_RM_DATA_RM_DATA_Msk                                      (0xffffffffUL) /*!< RM_DATA (Bitfield-Mask: 0xffffffff)                   */
+/* ======================================================  RM_DATA_HI  ======================================================= */
+ #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Pos                                (0UL)          /*!< RM_DATA_HI (Bit 0)                                    */
+ #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Msk                                (0xffffffffUL) /*!< RM_DATA_HI (Bitfield-Mask: 0xffffffff)                */
+/* =======================================================  RM_STATUS  ======================================================= */
+ #define R_ETHSW_RM_STATUS_ageaddress_Pos                                 (0UL)          /*!< ageaddress (Bit 0)                                    */
+ #define R_ETHSW_RM_STATUS_ageaddress_Msk                                 (0xfffUL)      /*!< ageaddress (Bitfield-Mask: 0xfff)                     */
+/* =====================================================  TxSeqTooLate  ====================================================== */
+ #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Pos                            (0UL)          /*!< TxSeqTooLate (Bit 0)                                  */
+ #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Msk                            (0xfUL)        /*!< TxSeqTooLate (Bitfield-Mask: 0x0f)                    */
+/* ====================================================  CntErrWrongLanA  ==================================================== */
+ #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Pos                      (0UL)          /*!< CntErrWrongLanA (Bit 0)                               */
+ #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Msk                      (0xffffffffUL) /*!< CntErrWrongLanA (Bitfield-Mask: 0xffffffff)           */
+/* ====================================================  CntErrWrongLanB  ==================================================== */
+ #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Pos                      (0UL)          /*!< CntErrWrongLanB (Bit 0)                               */
+ #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Msk                      (0xffffffffUL) /*!< CntErrWrongLanB (Bitfield-Mask: 0xffffffff)           */
+/* ======================================================  CntDupLanA  ======================================================= */
+ #define R_ETHSW_CntDupLanA_CntDupLanA_Pos                                (0UL)          /*!< CntDupLanA (Bit 0)                                    */
+ #define R_ETHSW_CntDupLanA_CntDupLanA_Msk                                (0xffffffffUL) /*!< CntDupLanA (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  CntDupLanB  ======================================================= */
+ #define R_ETHSW_CntDupLanB_CntDupLanB_Pos                                (0UL)          /*!< CntDupLanB (Bit 0)                                    */
+ #define R_ETHSW_CntDupLanB_CntDupLanB_Msk                                (0xffffffffUL) /*!< CntDupLanB (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  CntOutOfSeqLowA  ==================================================== */
+ #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Pos                      (0UL)          /*!< CntOutOfSeqLowA (Bit 0)                               */
+ #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Msk                      (0xffffffffUL) /*!< CntOutOfSeqLowA (Bitfield-Mask: 0xffffffff)           */
+/* ====================================================  CntOutOfSeqLowB  ==================================================== */
+ #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Pos                      (0UL)          /*!< CntOutOfSeqLowB (Bit 0)                               */
+ #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Msk                      (0xffffffffUL) /*!< CntOutOfSeqLowB (Bitfield-Mask: 0xffffffff)           */
+/* =====================================================  CntOutOfSeqA  ====================================================== */
+ #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Pos                            (0UL)          /*!< CntOutOfSeqA (Bit 0)                                  */
+ #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Msk                            (0xffffffffUL) /*!< CntOutOfSeqA (Bitfield-Mask: 0xffffffff)              */
+/* =====================================================  CntOutOfSeqB  ====================================================== */
+ #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Pos                            (0UL)          /*!< CntOutOfSeqB (Bit 0)                                  */
+ #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Msk                            (0xffffffffUL) /*!< CntOutOfSeqB (Bitfield-Mask: 0xffffffff)              */
+/* ======================================================  CntAcceptA  ======================================================= */
+ #define R_ETHSW_CntAcceptA_CntAcceptA_Pos                                (0UL)          /*!< CntAcceptA (Bit 0)                                    */
+ #define R_ETHSW_CntAcceptA_CntAcceptA_Msk                                (0xffffffffUL) /*!< CntAcceptA (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  CntAcceptB  ======================================================= */
+ #define R_ETHSW_CntAcceptB_CntAcceptB_Pos                                (0UL)          /*!< CntAcceptB (Bit 0)                                    */
+ #define R_ETHSW_CntAcceptB_CntAcceptB_Msk                                (0xffffffffUL) /*!< CntAcceptB (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  CntMissing  ======================================================= */
+ #define R_ETHSW_CntMissing_CntMissing_Pos                                (0UL)          /*!< CntMissing (Bit 0)                                    */
+ #define R_ETHSW_CntMissing_CntMissing_Msk                                (0xffffffffUL) /*!< CntMissing (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  HUB_CONFIG  ======================================================= */
+ #define R_ETHSW_HUB_CONFIG_HUB_ENA_Pos                                   (0UL)          /*!< HUB_ENA (Bit 0)                                       */
+ #define R_ETHSW_HUB_CONFIG_HUB_ENA_Msk                                   (0x1UL)        /*!< HUB_ENA (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Pos                            (1UL)          /*!< RETRANSMIT_ENA (Bit 1)                                */
+ #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Msk                            (0x2UL)        /*!< RETRANSMIT_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Pos                              (2UL)          /*!< TRIGGER_MODE (Bit 2)                                  */
+ #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Msk                              (0x4UL)        /*!< TRIGGER_MODE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Pos                               (3UL)          /*!< HUB_ISOLATE (Bit 3)                                   */
+ #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Msk                               (0x8UL)        /*!< HUB_ISOLATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Pos                                 (4UL)          /*!< TIMER_SEL (Bit 4)                                     */
+ #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Msk                                 (0x10UL)       /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Pos                                  (6UL)          /*!< IPG_WAIT (Bit 6)                                      */
+ #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Msk                                  (0x1c0UL)      /*!< IPG_WAIT (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_HUB_CONFIG_CRS_GEN_Pos                                   (9UL)          /*!< CRS_GEN (Bit 9)                                       */
+ #define R_ETHSW_HUB_CONFIG_CRS_GEN_Msk                                   (0x200UL)      /*!< CRS_GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Pos                              (10UL)         /*!< PRMB_GEN_DIS (Bit 10)                                 */
+ #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Msk                              (0x400UL)      /*!< PRMB_GEN_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Pos                             (11UL)         /*!< JAM_WAIT_IDLE (Bit 11)                                */
+ #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Msk                             (0x800UL)      /*!< JAM_WAIT_IDLE (Bitfield-Mask: 0x01)                   */
+/* =======================================================  HUB_GROUP  ======================================================= */
+ #define R_ETHSW_HUB_GROUP_HUB_GROUP_Pos                                  (0UL)          /*!< HUB_GROUP (Bit 0)                                     */
+ #define R_ETHSW_HUB_GROUP_HUB_GROUP_Msk                                  (0x7UL)        /*!< HUB_GROUP (Bitfield-Mask: 0x07)                       */
+/* ======================================================  HUB_DEFPORT  ====================================================== */
+ #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Pos                              (0UL)          /*!< HUB_DEFPORT (Bit 0)                                   */
+ #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Msk                              (0x7UL)        /*!< HUB_DEFPORT (Bitfield-Mask: 0x07)                     */
+/* =================================================  HUB_TRIGGER_IMMEDIATE  ================================================= */
+ #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Pos          (0UL)          /*!< HUB_TRIGGER_IMMEDIATE (Bit 0)                       */
+ #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Msk          (0x7UL)        /*!< HUB_TRIGGER_IMMEDIATE (Bitfield-Mask: 0x07)       */
+/* ====================================================  HUB_TRIGGER_AT  ===================================================== */
+ #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Pos                        (0UL)          /*!< HUB_TRIGGER_AT (Bit 0)                                */
+ #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Msk                        (0x7UL)        /*!< HUB_TRIGGER_AT (Bitfield-Mask: 0x07)                  */
+/* =======================================================  HUB_TTIME  ======================================================= */
+ #define R_ETHSW_HUB_TTIME_HUB_TTIME_Pos                                  (0UL)          /*!< HUB_TTIME (Bit 0)                                     */
+ #define R_ETHSW_HUB_TTIME_HUB_TTIME_Msk                                  (0xffffffffUL) /*!< HUB_TTIME (Bitfield-Mask: 0xffffffff)                 */
+/* ====================================================  HUB_IRQ_CONTROL  ==================================================== */
+ #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Pos                           (0UL)          /*!< RX_TRIGGER (Bit 0)                                    */
+ #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Msk                           (0x7UL)        /*!< RX_TRIGGER (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Pos                           (3UL)          /*!< CHANGE_DET (Bit 3)                                    */
+ #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Msk                           (0x8UL)        /*!< CHANGE_DET (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Pos                    (4UL)          /*!< TRIGGER_IMMEDIATE (Bit 4)                             */
+ #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Msk                    (0x10UL)       /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Pos                        (5UL)          /*!< TRIGGER_TIMER (Bit 5)                                 */
+ #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Msk                        (0x20UL)       /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01)                   */
+/* ===================================================  HUB_IRQ_STAT_ACK  ==================================================== */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Pos                          (0UL)          /*!< RX_TRIGGER (Bit 0)                                    */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Msk                          (0x7UL)        /*!< RX_TRIGGER (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Pos                          (3UL)          /*!< CHANGE_DET (Bit 3)                                    */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Msk                          (0x8UL)        /*!< CHANGE_DET (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Pos                   (4UL)          /*!< TRIGGER_IMMEDIATE (Bit 4)                             */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Msk                   (0x10UL)       /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Pos                       (5UL)          /*!< TRIGGER_TIMER (Bit 5)                                 */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Msk                       (0x20UL)       /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01)                   */
+/* ======================================================  HUB_STATUS  ======================================================= */
+ #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Pos                              (0UL)          /*!< PORTS_ACTIVE (Bit 0)                                  */
+ #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Msk                              (0x7UL)        /*!< PORTS_ACTIVE (Bitfield-Mask: 0x07)                    */
+ #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Pos                                 (9UL)          /*!< TX_ACTIVE (Bit 9)                                     */
+ #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Msk                                 (0x200UL)      /*!< TX_ACTIVE (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_HUB_STATUS_TX_BUSY_Pos                                   (10UL)         /*!< TX_BUSY (Bit 10)                                      */
+ #define R_ETHSW_HUB_STATUS_TX_BUSY_Msk                                   (0x400UL)      /*!< TX_BUSY (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_HUB_STATUS_Speed_OK_Pos                                  (11UL)         /*!< Speed_OK (Bit 11)                                     */
+ #define R_ETHSW_HUB_STATUS_Speed_OK_Msk                                  (0x800UL)      /*!< Speed_OK (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Pos                         (12UL)         /*!< TX_Change_Pending (Bit 12)                            */
+ #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Msk                         (0x1000UL)     /*!< TX_Change_Pending (Bitfield-Mask: 0x01)               */
+/* ===================================================  HUB_OPORT_STATUS  ==================================================== */
+ #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Pos                    (0UL)          /*!< HUB_OPORT_STATUS (Bit 0)                              */
+ #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Msk                    (0x7UL)        /*!< HUB_OPORT_STATUS (Bitfield-Mask: 0x07)                */
+/* ======================================================  TDMA_CONFIG  ====================================================== */
+ #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Pos                                 (0UL)          /*!< TDMA_ENA (Bit 0)                                      */
+ #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Msk                                 (0x1UL)        /*!< TDMA_ENA (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TDMA_CONFIG_WAIT_START_Pos                               (1UL)          /*!< WAIT_START (Bit 1)                                    */
+ #define R_ETHSW_TDMA_CONFIG_WAIT_START_Msk                               (0x2UL)        /*!< WAIT_START (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Pos                                (2UL)          /*!< TIMER_SEL (Bit 2)                                     */
+ #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Msk                                (0x4UL)        /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Pos                               (4UL)          /*!< RED_PERIOD (Bit 4)                                    */
+ #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Msk                               (0x10UL)       /*!< RED_PERIOD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Pos                             (5UL)          /*!< RED_OVRD_ENA (Bit 5)                                  */
+ #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Msk                             (0x20UL)       /*!< RED_OVRD_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Pos                                 (6UL)          /*!< RED_OVRD (Bit 6)                                      */
+ #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Msk                                 (0x40UL)       /*!< RED_OVRD (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Pos                               (7UL)          /*!< IN_CT_WREN (Bit 7)                                    */
+ #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Msk                               (0x80UL)       /*!< IN_CT_WREN (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Pos                              (8UL)          /*!< OUT_CT_WREN (Bit 8)                                   */
+ #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Msk                              (0x100UL)      /*!< OUT_CT_WREN (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Pos                             (9UL)          /*!< HOLD_REQ_CLR (Bit 9)                                  */
+ #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Msk                             (0x200UL)      /*!< HOLD_REQ_CLR (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Pos                         (12UL)         /*!< TIMER_SEL_ACTIVE (Bit 12)                             */
+ #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Msk                         (0x1000UL)     /*!< TIMER_SEL_ACTIVE (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Pos                                (16UL)         /*!< IN_CT_ENA (Bit 16)                                    */
+ #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Msk                                (0xf0000UL)    /*!< IN_CT_ENA (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Pos                               (24UL)         /*!< OUT_CT_ENA (Bit 24)                                   */
+ #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Msk                               (0xf000000UL)  /*!< OUT_CT_ENA (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  TDMA_ENA_CTRL  ===================================================== */
+ #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Pos                               (0UL)          /*!< PORT_ENA (Bit 0)                                      */
+ #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Msk                               (0xfUL)        /*!< PORT_ENA (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Pos                              (16UL)         /*!< QGATE_DIS (Bit 16)                                    */
+ #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Msk                              (0xff0000UL)   /*!< QGATE_DIS (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Pos                              (24UL)         /*!< QTRIG_DIS (Bit 24)                                    */
+ #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Msk                              (0xff000000UL) /*!< QTRIG_DIS (Bitfield-Mask: 0xff)                       */
+/* ======================================================  TDMA_START  ======================================================= */
+ #define R_ETHSW_TDMA_START_TDMA_START_Pos                                (0UL)          /*!< TDMA_START (Bit 0)                                    */
+ #define R_ETHSW_TDMA_START_TDMA_START_Msk                                (0xffffffffUL) /*!< TDMA_START (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  TDMA_MODULO  ====================================================== */
+ #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Pos                              (0UL)          /*!< TDMA_MODULO (Bit 0)                                   */
+ #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Msk                              (0xffffffffUL) /*!< TDMA_MODULO (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  TDMA_CYCLE  ======================================================= */
+ #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Pos                                (0UL)          /*!< TDMA_CYCLE (Bit 0)                                    */
+ #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Msk                                (0xffffffffUL) /*!< TDMA_CYCLE (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  TCV_SEQ_ADDR  ====================================================== */
+ #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Pos                              (0UL)          /*!< TCV_S_ADDR (Bit 0)                                    */
+ #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Msk                              (0xfffUL)      /*!< TCV_S_ADDR (Bitfield-Mask: 0xfff)                     */
+ #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Pos                               (31UL)         /*!< ADDR_AINC (Bit 31)                                    */
+ #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Msk                               (0x80000000UL) /*!< ADDR_AINC (Bitfield-Mask: 0x01)                       */
+/* =====================================================  TCV_SEQ_CTRL  ====================================================== */
+ #define R_ETHSW_TCV_SEQ_CTRL_START_Pos                                   (0UL)          /*!< START (Bit 0)                                         */
+ #define R_ETHSW_TCV_SEQ_CTRL_START_Msk                                   (0x1UL)        /*!< START (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_TCV_SEQ_CTRL_INT_Pos                                     (1UL)          /*!< INT (Bit 1)                                           */
+ #define R_ETHSW_TCV_SEQ_CTRL_INT_Msk                                     (0x2UL)        /*!< INT (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Pos                               (2UL)          /*!< TCV_D_IDX (Bit 2)                                     */
+ #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Msk                               (0x7fcUL)      /*!< TCV_D_IDX (Bitfield-Mask: 0x1ff)                      */
+ #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Pos                                    (22UL)         /*!< GPIO (Bit 22)                                         */
+ #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Msk                                    (0x3fc00000UL) /*!< GPIO (Bitfield-Mask: 0xff)                            */
+ #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Pos                               (31UL)         /*!< READ_MODE (Bit 31)                                    */
+ #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Msk                               (0x80000000UL) /*!< READ_MODE (Bitfield-Mask: 0x01)                       */
+/* =====================================================  TCV_SEQ_LAST  ====================================================== */
+ #define R_ETHSW_TCV_SEQ_LAST_LAST_Pos                                    (0UL)          /*!< LAST (Bit 0)                                          */
+ #define R_ETHSW_TCV_SEQ_LAST_LAST_Msk                                    (0xfffUL)      /*!< LAST (Bitfield-Mask: 0xfff)                           */
+ #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Pos                                  (16UL)         /*!< ACTIVE (Bit 16)                                       */
+ #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Msk                                  (0xfff0000UL)  /*!< ACTIVE (Bitfield-Mask: 0xfff)                         */
+/* ======================================================  TCV_D_ADDR  ======================================================= */
+ #define R_ETHSW_TCV_D_ADDR_ADDR_Pos                                      (0UL)          /*!< ADDR (Bit 0)                                          */
+ #define R_ETHSW_TCV_D_ADDR_ADDR_Msk                                      (0x1ffUL)      /*!< ADDR (Bitfield-Mask: 0x1ff)                           */
+ #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Pos                               (31UL)         /*!< AINC_WR_ENA (Bit 31)                                  */
+ #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Msk                               (0x80000000UL) /*!< AINC_WR_ENA (Bitfield-Mask: 0x01)                     */
+/* =====================================================  TCV_D_OFFSET  ====================================================== */
+ #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Pos                            (0UL)          /*!< TCV_D_OFFSET (Bit 0)                                  */
+ #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Msk                            (0xffffffffUL) /*!< TCV_D_OFFSET (Bitfield-Mask: 0xffffffff)              */
+/* ======================================================  TCV_D_CTRL  ======================================================= */
+ #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Pos                                  (0UL)          /*!< INC_CTR0 (Bit 0)                                      */
+ #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Msk                                  (0x1UL)        /*!< INC_CTR0 (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Pos                                  (1UL)          /*!< INC_CTR1 (Bit 1)                                      */
+ #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Msk                                  (0x2UL)        /*!< INC_CTR1 (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Pos                                (2UL)          /*!< RED_PERIOD (Bit 2)                                    */
+ #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Msk                                (0x4UL)        /*!< RED_PERIOD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Pos                                (3UL)          /*!< OUT_CT_ENA (Bit 3)                                    */
+ #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Msk                                (0x8UL)        /*!< OUT_CT_ENA (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Pos                                 (4UL)          /*!< IN_CT_ENA (Bit 4)                                     */
+ #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Msk                                 (0x10UL)       /*!< IN_CT_ENA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Pos                              (5UL)          /*!< TRIGGER_MODE (Bit 5)                                  */
+ #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Msk                              (0x20UL)       /*!< TRIGGER_MODE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Pos                                 (6UL)          /*!< GATE_MODE (Bit 6)                                     */
+ #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Msk                                 (0x40UL)       /*!< GATE_MODE (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Pos                                  (7UL)          /*!< HOLD_REQ (Bit 7)                                      */
+ #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Msk                                  (0x80UL)       /*!< HOLD_REQ (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TCV_D_CTRL_QGATE_Pos                                     (8UL)          /*!< QGATE (Bit 8)                                         */
+ #define R_ETHSW_TCV_D_CTRL_QGATE_Msk                                     (0xff00UL)     /*!< QGATE (Bitfield-Mask: 0xff)                           */
+ #define R_ETHSW_TCV_D_CTRL_PMASK_Pos                                     (16UL)         /*!< PMASK (Bit 16)                                        */
+ #define R_ETHSW_TCV_D_CTRL_PMASK_Msk                                     (0xf0000UL)    /*!< PMASK (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  TDMA_CTR0  ======================================================= */
+ #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Pos                                  (0UL)          /*!< TDMA_CTR0 (Bit 0)                                     */
+ #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Msk                                  (0xffffffffUL) /*!< TDMA_CTR0 (Bitfield-Mask: 0xffffffff)                 */
+/* =======================================================  TDMA_CTR1  ======================================================= */
+ #define R_ETHSW_TDMA_CTR1_VALUE_Pos                                      (0UL)          /*!< VALUE (Bit 0)                                         */
+ #define R_ETHSW_TDMA_CTR1_VALUE_Msk                                      (0xffUL)       /*!< VALUE (Bitfield-Mask: 0xff)                           */
+ #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Pos                                  (8UL)          /*!< WRITE_ENA (Bit 8)                                     */
+ #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Msk                                  (0x100UL)      /*!< WRITE_ENA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_TDMA_CTR1_MAX_Pos                                        (16UL)         /*!< MAX (Bit 16)                                          */
+ #define R_ETHSW_TDMA_CTR1_MAX_Msk                                        (0xff0000UL)   /*!< MAX (Bitfield-Mask: 0xff)                             */
+ #define R_ETHSW_TDMA_CTR1_INT_VALUE_Pos                                  (24UL)         /*!< INT_VALUE (Bit 24)                                    */
+ #define R_ETHSW_TDMA_CTR1_INT_VALUE_Msk                                  (0xff000000UL) /*!< INT_VALUE (Bitfield-Mask: 0xff)                       */
+/* ====================================================  TDMA_TCV_START  ===================================================== */
+ #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Pos                        (0UL)          /*!< TDMA_TCV_START (Bit 0)                                */
+ #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Msk                        (0xfffUL)      /*!< TDMA_TCV_START (Bitfield-Mask: 0xfff)                 */
+/* ====================================================  TIME_LOAD_NEXT  ===================================================== */
+ #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Pos                        (0UL)          /*!< TIME_LOAD_NEXT (Bit 0)                                */
+ #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Msk                        (0xffffffffUL) /*!< TIME_LOAD_NEXT (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  TDMA_IRQ_CONTROL  ==================================================== */
+ #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Pos                          (0UL)          /*!< TCV_INT_EN (Bit 0)                                    */
+ #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Msk                          (0x1UL)        /*!< TCV_INT_EN (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Pos                         (13UL)         /*!< CTR1_INT_EN (Bit 13)                                  */
+ #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Msk                         (0x2000UL)     /*!< CTR1_INT_EN (Bitfield-Mask: 0x01)                     */
+/* ===================================================  TDMA_IRQ_STAT_ACK  =================================================== */
+ #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Pos                            (0UL)          /*!< TCV_ACK (Bit 0)                                       */
+ #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Msk                            (0x1UL)        /*!< TCV_ACK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Pos                           (13UL)         /*!< CTR1_ACK (Bit 13)                                     */
+ #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Msk                           (0x2000UL)     /*!< CTR1_ACK (Bitfield-Mask: 0x01)                        */
+/* =======================================================  TDMA_GPIO  ======================================================= */
+ #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Pos                                (0UL)          /*!< GPIO_STATUS (Bit 0)                                   */
+ #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Msk                                (0xffUL)       /*!< GPIO_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Pos                                  (16UL)         /*!< GPIO_MODE (Bit 16)                                    */
+ #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Msk                                  (0xffff0000UL) /*!< GPIO_MODE (Bitfield-Mask: 0xffff)                     */
+/* ====================================================  RXMATCH_CONFIG  ===================================================== */
+ #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Pos                            (0UL)          /*!< PATTERN_EN (Bit 0)                                    */
+ #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk                            (0xfffUL)      /*!< PATTERN_EN (Bitfield-Mask: 0xfff)                     */
+/* =====================================================  PATTERN_CTRL  ====================================================== */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Pos                               (0UL)          /*!< MATCH_NOT (Bit 0)                                     */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Msk                               (0x1UL)        /*!< MATCH_NOT (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Pos                                 (1UL)          /*!< MGMTFWD (Bit 1)                                       */
+ #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Msk                                 (0x2UL)        /*!< MGMTFWD (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PATTERN_CTRL_DISCARD_Pos                                 (2UL)          /*!< DISCARD (Bit 2)                                       */
+ #define R_ETHSW_PATTERN_CTRL_DISCARD_Msk                                 (0x4UL)        /*!< DISCARD (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Pos                                (3UL)          /*!< SET_PRIO (Bit 3)                                      */
+ #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Msk                                (0x8UL)        /*!< SET_PRIO (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PATTERN_CTRL_MODE_Pos                                    (4UL)          /*!< MODE (Bit 4)                                          */
+ #define R_ETHSW_PATTERN_CTRL_MODE_Msk                                    (0x30UL)       /*!< MODE (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Pos                           (6UL)          /*!< TIMER_SEL_OVR (Bit 6)                                 */
+ #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Msk                           (0x40UL)       /*!< TIMER_SEL_OVR (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Pos                           (7UL)          /*!< FORCE_FORWARD (Bit 7)                                 */
+ #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Msk                           (0x80UL)       /*!< FORCE_FORWARD (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Pos                              (8UL)          /*!< HUBTRIGGER (Bit 8)                                    */
+ #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Msk                              (0x100UL)      /*!< HUBTRIGGER (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Pos                               (9UL)          /*!< MATCH_RED (Bit 9)                                     */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Msk                               (0x200UL)      /*!< MATCH_RED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Pos                           (10UL)         /*!< MATCH_NOT_RED (Bit 10)                                */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Msk                           (0x400UL)      /*!< MATCH_NOT_RED (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Pos                               (11UL)         /*!< VLAN_SKIP (Bit 11)                                    */
+ #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Msk                               (0x800UL)      /*!< VLAN_SKIP (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_PATTERN_CTRL_PRIORITY_Pos                                (12UL)         /*!< PRIORITY (Bit 12)                                     */
+ #define R_ETHSW_PATTERN_CTRL_PRIORITY_Msk                                (0x7000UL)     /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Pos                            (15UL)         /*!< LEARNING_DIS (Bit 15)                                 */
+ #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Msk                            (0x8000UL)     /*!< LEARNING_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_PATTERN_CTRL_PORTMASK_Pos                                (16UL)         /*!< PORTMASK (Bit 16)                                     */
+ #define R_ETHSW_PATTERN_CTRL_PORTMASK_Msk                                (0xf0000UL)    /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Pos                             (22UL)         /*!< IMC_TRIGGER (Bit 22)                                  */
+ #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Msk                             (0x400000UL)   /*!< IMC_TRIGGER (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Pos                         (23UL)         /*!< IMC_TRIGGER_DLY (Bit 23)                              */
+ #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Msk                         (0x800000UL)   /*!< IMC_TRIGGER_DLY (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Pos                              (24UL)         /*!< SWAP_BYTES (Bit 24)                                   */
+ #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Msk                              (0x1000000UL)  /*!< SWAP_BYTES (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Pos                                (25UL)         /*!< MATCH_LT (Bit 25)                                     */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Msk                                (0x2000000UL)  /*!< MATCH_LT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Pos                               (26UL)         /*!< TIMER_SEL (Bit 26)                                    */
+ #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Msk                               (0x4000000UL)  /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Pos                                (28UL)         /*!< QUEUESEL (Bit 28)                                     */
+ #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Msk                                (0xf0000000UL) /*!< QUEUESEL (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  PATTERN_IRQ_CONTROL  ================================================== */
+ #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Pos                         (0UL)          /*!< MATCHINT (Bit 0)                                      */
+ #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Msk                         (0xfffUL)      /*!< MATCHINT (Bitfield-Mask: 0xfff)                       */
+ #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Pos                        (16UL)         /*!< ERROR_INT (Bit 16)                                    */
+ #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Msk                        (0xf0000UL)    /*!< ERROR_INT (Bitfield-Mask: 0x0f)                       */
+/* =================================================  PATTERN_IRQ_STAT_ACK  ================================================== */
+ #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Pos                        (0UL)          /*!< MATCHINT (Bit 0)                                      */
+ #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Msk                        (0xfffUL)      /*!< MATCHINT (Bitfield-Mask: 0xfff)                       */
+ #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Pos                       (16UL)         /*!< ERROR_INT (Bit 16)                                    */
+ #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Msk                       (0xf0000UL)    /*!< ERROR_INT (Bitfield-Mask: 0x0f)                       */
+/* ======================================================  PTRN_VLANID  ====================================================== */
+ #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Pos                              (0UL)          /*!< PTRN_VLANID (Bit 0)                                   */
+ #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Msk                              (0xffffUL)     /*!< PTRN_VLANID (Bitfield-Mask: 0xffff)                   */
+/* ======================================================  PATTERN_SEL  ====================================================== */
+ #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Pos                              (0UL)          /*!< PATTERN_SEL (Bit 0)                                   */
+ #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Msk                              (0xfUL)        /*!< PATTERN_SEL (Bitfield-Mask: 0x0f)                     */
+/* ======================================================  PTRN_CMP_30  ====================================================== */
+ #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Pos                              (0UL)          /*!< PTRN_CMP_30 (Bit 0)                                   */
+ #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Msk                              (0xffffffffUL) /*!< PTRN_CMP_30 (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  PTRN_CMP_74  ====================================================== */
+ #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Pos                              (0UL)          /*!< PTRN_CMP_74 (Bit 0)                                   */
+ #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Msk                              (0xffffffffUL) /*!< PTRN_CMP_74 (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  PTRN_CMP_118  ====================================================== */
+ #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Pos                            (0UL)          /*!< PTRN_CMP_118 (Bit 0)                                  */
+ #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Msk                            (0xffffffffUL) /*!< PTRN_CMP_118 (Bitfield-Mask: 0xffffffff)              */
+/* ======================================================  PTRN_MSK_30  ====================================================== */
+ #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Pos                              (0UL)          /*!< PTRN_MSK_30 (Bit 0)                                   */
+ #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Msk                              (0xffffffffUL) /*!< PTRN_MSK_30 (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  PTRN_MSK_74  ====================================================== */
+ #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Pos                              (0UL)          /*!< PTRN_MSK_74 (Bit 0)                                   */
+ #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Msk                              (0xffffffffUL) /*!< PTRN_MSK_74 (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  PTRN_MSK_118  ====================================================== */
+ #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Pos                            (0UL)          /*!< PTRN_MSK_118 (Bit 0)                                  */
+ #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Msk                            (0xffffffffUL) /*!< PTRN_MSK_118 (Bitfield-Mask: 0xffffffff)              */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ESC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TYPE  ========================================================== */
+ #define R_ESC_TYPE_TYPE_Pos                        (0UL)          /*!< TYPE (Bit 0)                                          */
+ #define R_ESC_TYPE_TYPE_Msk                        (0xffUL)       /*!< TYPE (Bitfield-Mask: 0xff)                            */
+/* =======================================================  REVISION  ======================================================== */
+ #define R_ESC_REVISION_REV_Pos                     (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ESC_REVISION_REV_Msk                     (0xffUL)       /*!< REV (Bitfield-Mask: 0xff)                             */
+/* =========================================================  BUILD  ========================================================= */
+ #define R_ESC_BUILD_BUILD_Pos                      (0UL)          /*!< BUILD (Bit 0)                                         */
+ #define R_ESC_BUILD_BUILD_Msk                      (0xffUL)       /*!< BUILD (Bitfield-Mask: 0xff)                           */
+/* =======================================================  FMMU_NUM  ======================================================== */
+ #define R_ESC_FMMU_NUM_NUMFMMU_Pos                 (0UL)          /*!< NUMFMMU (Bit 0)                                       */
+ #define R_ESC_FMMU_NUM_NUMFMMU_Msk                 (0xffUL)       /*!< NUMFMMU (Bitfield-Mask: 0xff)                         */
+/* =====================================================  SYNC_MANAGER  ====================================================== */
+ #define R_ESC_SYNC_MANAGER_NUMSYNC_Pos             (0UL)          /*!< NUMSYNC (Bit 0)                                       */
+ #define R_ESC_SYNC_MANAGER_NUMSYNC_Msk             (0xffUL)       /*!< NUMSYNC (Bitfield-Mask: 0xff)                         */
+/* =======================================================  RAM_SIZE  ======================================================== */
+ #define R_ESC_RAM_SIZE_RAMSIZE_Pos                 (0UL)          /*!< RAMSIZE (Bit 0)                                       */
+ #define R_ESC_RAM_SIZE_RAMSIZE_Msk                 (0xffUL)       /*!< RAMSIZE (Bitfield-Mask: 0xff)                         */
+/* =======================================================  PORT_DESC  ======================================================= */
+ #define R_ESC_PORT_DESC_P0_Pos                     (0UL)          /*!< P0 (Bit 0)                                            */
+ #define R_ESC_PORT_DESC_P0_Msk                     (0x3UL)        /*!< P0 (Bitfield-Mask: 0x03)                              */
+ #define R_ESC_PORT_DESC_P1_Pos                     (2UL)          /*!< P1 (Bit 2)                                            */
+ #define R_ESC_PORT_DESC_P1_Msk                     (0xcUL)        /*!< P1 (Bitfield-Mask: 0x03)                              */
+ #define R_ESC_PORT_DESC_P2_Pos                     (4UL)          /*!< P2 (Bit 4)                                            */
+ #define R_ESC_PORT_DESC_P2_Msk                     (0x30UL)       /*!< P2 (Bitfield-Mask: 0x03)                              */
+ #define R_ESC_PORT_DESC_P3_Pos                     (6UL)          /*!< P3 (Bit 6)                                            */
+ #define R_ESC_PORT_DESC_P3_Msk                     (0xc0UL)       /*!< P3 (Bitfield-Mask: 0x03)                              */
+/* ========================================================  FEATURE  ======================================================== */
+ #define R_ESC_FEATURE_FMMU_Pos                     (0UL)          /*!< FMMU (Bit 0)                                          */
+ #define R_ESC_FEATURE_FMMU_Msk                     (0x1UL)        /*!< FMMU (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_FEATURE_DC_Pos                       (2UL)          /*!< DC (Bit 2)                                            */
+ #define R_ESC_FEATURE_DC_Msk                       (0x4UL)        /*!< DC (Bitfield-Mask: 0x01)                              */
+ #define R_ESC_FEATURE_DCWID_Pos                    (3UL)          /*!< DCWID (Bit 3)                                         */
+ #define R_ESC_FEATURE_DCWID_Msk                    (0x8UL)        /*!< DCWID (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_FEATURE_LINKDECMII_Pos               (6UL)          /*!< LINKDECMII (Bit 6)                                    */
+ #define R_ESC_FEATURE_LINKDECMII_Msk               (0x40UL)       /*!< LINKDECMII (Bitfield-Mask: 0x01)                      */
+ #define R_ESC_FEATURE_FCS_Pos                      (7UL)          /*!< FCS (Bit 7)                                           */
+ #define R_ESC_FEATURE_FCS_Msk                      (0x80UL)       /*!< FCS (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_FEATURE_DCSYNC_Pos                   (8UL)          /*!< DCSYNC (Bit 8)                                        */
+ #define R_ESC_FEATURE_DCSYNC_Msk                   (0x100UL)      /*!< DCSYNC (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_FEATURE_LRW_Pos                      (9UL)          /*!< LRW (Bit 9)                                           */
+ #define R_ESC_FEATURE_LRW_Msk                      (0x200UL)      /*!< LRW (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_FEATURE_RWSUPP_Pos                   (10UL)         /*!< RWSUPP (Bit 10)                                       */
+ #define R_ESC_FEATURE_RWSUPP_Msk                   (0x400UL)      /*!< RWSUPP (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_FEATURE_FSCONFIG_Pos                 (11UL)         /*!< FSCONFIG (Bit 11)                                     */
+ #define R_ESC_FEATURE_FSCONFIG_Msk                 (0x800UL)      /*!< FSCONFIG (Bitfield-Mask: 0x01)                        */
+/* ======================================================  STATION_ADR  ====================================================== */
+ #define R_ESC_STATION_ADR_NODADDR_Pos              (0UL)          /*!< NODADDR (Bit 0)                                       */
+ #define R_ESC_STATION_ADR_NODADDR_Msk              (0xffffUL)     /*!< NODADDR (Bitfield-Mask: 0xffff)                       */
+/* =====================================================  STATION_ALIAS  ===================================================== */
+ #define R_ESC_STATION_ALIAS_NODALIADDR_Pos         (0UL)          /*!< NODALIADDR (Bit 0)                                    */
+ #define R_ESC_STATION_ALIAS_NODALIADDR_Msk         (0xffffUL)     /*!< NODALIADDR (Bitfield-Mask: 0xffff)                    */
+/* =====================================================  WR_REG_ENABLE  ===================================================== */
+ #define R_ESC_WR_REG_ENABLE_ENABLE_Pos             (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ESC_WR_REG_ENABLE_ENABLE_Msk             (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ====================================================  WR_REG_PROTECT  ===================================================== */
+ #define R_ESC_WR_REG_PROTECT_PROTECT_Pos           (0UL)          /*!< PROTECT (Bit 0)                                       */
+ #define R_ESC_WR_REG_PROTECT_PROTECT_Msk           (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+/* =====================================================  ESC_WR_ENABLE  ===================================================== */
+ #define R_ESC_ESC_WR_ENABLE_ENABLE_Pos             (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ESC_ESC_WR_ENABLE_ENABLE_Msk             (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ====================================================  ESC_WR_PROTECT  ===================================================== */
+ #define R_ESC_ESC_WR_PROTECT_PROTECT_Pos           (0UL)          /*!< PROTECT (Bit 0)                                       */
+ #define R_ESC_ESC_WR_PROTECT_PROTECT_Msk           (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+/* ===================================================  ESC_RESET_ECAT_R  ==================================================== */
+ #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Pos      (0UL)          /*!< RESET_ECAT (Bit 0)                                    */
+ #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Msk      (0x3UL)        /*!< RESET_ECAT (Bitfield-Mask: 0x03)                      */
+/* ===================================================  ESC_RESET_ECAT_W  ==================================================== */
+ #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Pos      (0UL)          /*!< RESET_ECAT (Bit 0)                                    */
+ #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Msk      (0xffUL)       /*!< RESET_ECAT (Bitfield-Mask: 0xff)                      */
+/* ====================================================  ESC_RESET_PDI_R  ==================================================== */
+ #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Pos        (0UL)          /*!< RESET_PDI (Bit 0)                                     */
+ #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Msk        (0x3UL)        /*!< RESET_PDI (Bitfield-Mask: 0x03)                       */
+/* ====================================================  ESC_RESET_PDI_W  ==================================================== */
+ #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Pos        (0UL)          /*!< RESET_PDI (Bit 0)                                     */
+ #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Msk        (0xffUL)       /*!< RESET_PDI (Bitfield-Mask: 0xff)                       */
+/* ====================================================  ESC_DL_CONTROL  ===================================================== */
+ #define R_ESC_ESC_DL_CONTROL_FWDRULE_Pos           (0UL)          /*!< FWDRULE (Bit 0)                                       */
+ #define R_ESC_ESC_DL_CONTROL_FWDRULE_Msk           (0x1UL)        /*!< FWDRULE (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Pos           (1UL)          /*!< TEMPUSE (Bit 1)                                       */
+ #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Msk           (0x2UL)        /*!< TEMPUSE (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_DL_CONTROL_LP0_Pos               (8UL)          /*!< LP0 (Bit 8)                                           */
+ #define R_ESC_ESC_DL_CONTROL_LP0_Msk               (0x300UL)      /*!< LP0 (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_ESC_DL_CONTROL_LP1_Pos               (10UL)         /*!< LP1 (Bit 10)                                          */
+ #define R_ESC_ESC_DL_CONTROL_LP1_Msk               (0xc00UL)      /*!< LP1 (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_ESC_DL_CONTROL_LP2_Pos               (12UL)         /*!< LP2 (Bit 12)                                          */
+ #define R_ESC_ESC_DL_CONTROL_LP2_Msk               (0x3000UL)     /*!< LP2 (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_ESC_DL_CONTROL_LP3_Pos               (14UL)         /*!< LP3 (Bit 14)                                          */
+ #define R_ESC_ESC_DL_CONTROL_LP3_Msk               (0xc000UL)     /*!< LP3 (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_ESC_DL_CONTROL_RXFIFO_Pos            (16UL)         /*!< RXFIFO (Bit 16)                                       */
+ #define R_ESC_ESC_DL_CONTROL_RXFIFO_Msk            (0x70000UL)    /*!< RXFIFO (Bitfield-Mask: 0x07)                          */
+ #define R_ESC_ESC_DL_CONTROL_STAALIAS_Pos          (24UL)         /*!< STAALIAS (Bit 24)                                     */
+ #define R_ESC_ESC_DL_CONTROL_STAALIAS_Msk          (0x1000000UL)  /*!< STAALIAS (Bitfield-Mask: 0x01)                        */
+/* ==================================================  PHYSICAL_RW_OFFSET  =================================================== */
+ #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Pos      (0UL)          /*!< RWOFFSET (Bit 0)                                      */
+ #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Msk      (0xffffUL)     /*!< RWOFFSET (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  ESC_DL_STATUS  ===================================================== */
+ #define R_ESC_ESC_DL_STATUS_PDIOPE_Pos             (0UL)          /*!< PDIOPE (Bit 0)                                        */
+ #define R_ESC_ESC_DL_STATUS_PDIOPE_Msk             (0x1UL)        /*!< PDIOPE (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ESC_DL_STATUS_PDIWDST_Pos            (1UL)          /*!< PDIWDST (Bit 1)                                       */
+ #define R_ESC_ESC_DL_STATUS_PDIWDST_Msk            (0x2UL)        /*!< PDIWDST (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_DL_STATUS_ENHLINKD_Pos           (2UL)          /*!< ENHLINKD (Bit 2)                                      */
+ #define R_ESC_ESC_DL_STATUS_ENHLINKD_Msk           (0x4UL)        /*!< ENHLINKD (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_ESC_DL_STATUS_PHYP0_Pos              (4UL)          /*!< PHYP0 (Bit 4)                                         */
+ #define R_ESC_ESC_DL_STATUS_PHYP0_Msk              (0x10UL)       /*!< PHYP0 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_PHYP1_Pos              (5UL)          /*!< PHYP1 (Bit 5)                                         */
+ #define R_ESC_ESC_DL_STATUS_PHYP1_Msk              (0x20UL)       /*!< PHYP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_PHYP2_Pos              (6UL)          /*!< PHYP2 (Bit 6)                                         */
+ #define R_ESC_ESC_DL_STATUS_PHYP2_Msk              (0x40UL)       /*!< PHYP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_PHYP3_Pos              (7UL)          /*!< PHYP3 (Bit 7)                                         */
+ #define R_ESC_ESC_DL_STATUS_PHYP3_Msk              (0x80UL)       /*!< PHYP3 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_LP0_Pos                (8UL)          /*!< LP0 (Bit 8)                                           */
+ #define R_ESC_ESC_DL_STATUS_LP0_Msk                (0x100UL)      /*!< LP0 (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_ESC_DL_STATUS_COMP0_Pos              (9UL)          /*!< COMP0 (Bit 9)                                         */
+ #define R_ESC_ESC_DL_STATUS_COMP0_Msk              (0x200UL)      /*!< COMP0 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_LP1_Pos                (10UL)         /*!< LP1 (Bit 10)                                          */
+ #define R_ESC_ESC_DL_STATUS_LP1_Msk                (0x400UL)      /*!< LP1 (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_ESC_DL_STATUS_COMP1_Pos              (11UL)         /*!< COMP1 (Bit 11)                                        */
+ #define R_ESC_ESC_DL_STATUS_COMP1_Msk              (0x800UL)      /*!< COMP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_LP2_Pos                (12UL)         /*!< LP2 (Bit 12)                                          */
+ #define R_ESC_ESC_DL_STATUS_LP2_Msk                (0x1000UL)     /*!< LP2 (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_ESC_DL_STATUS_COMP2_Pos              (13UL)         /*!< COMP2 (Bit 13)                                        */
+ #define R_ESC_ESC_DL_STATUS_COMP2_Msk              (0x2000UL)     /*!< COMP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_LP3_Pos                (14UL)         /*!< LP3 (Bit 14)                                          */
+ #define R_ESC_ESC_DL_STATUS_LP3_Msk                (0x4000UL)     /*!< LP3 (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_ESC_DL_STATUS_COMP3_Pos              (15UL)         /*!< COMP3 (Bit 15)                                        */
+ #define R_ESC_ESC_DL_STATUS_COMP3_Msk              (0x8000UL)     /*!< COMP3 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  AL_CONTROL  ======================================================= */
+ #define R_ESC_AL_CONTROL_INISTATE_Pos              (0UL)          /*!< INISTATE (Bit 0)                                      */
+ #define R_ESC_AL_CONTROL_INISTATE_Msk              (0xfUL)        /*!< INISTATE (Bitfield-Mask: 0x0f)                        */
+ #define R_ESC_AL_CONTROL_ERRINDACK_Pos             (4UL)          /*!< ERRINDACK (Bit 4)                                     */
+ #define R_ESC_AL_CONTROL_ERRINDACK_Msk             (0x10UL)       /*!< ERRINDACK (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_AL_CONTROL_DEVICEID_Pos              (5UL)          /*!< DEVICEID (Bit 5)                                      */
+ #define R_ESC_AL_CONTROL_DEVICEID_Msk              (0x20UL)       /*!< DEVICEID (Bitfield-Mask: 0x01)                        */
+/* =======================================================  AL_STATUS  ======================================================= */
+ #define R_ESC_AL_STATUS_ACTSTATE_Pos               (0UL)          /*!< ACTSTATE (Bit 0)                                      */
+ #define R_ESC_AL_STATUS_ACTSTATE_Msk               (0xfUL)        /*!< ACTSTATE (Bitfield-Mask: 0x0f)                        */
+ #define R_ESC_AL_STATUS_ERR_Pos                    (4UL)          /*!< ERR (Bit 4)                                           */
+ #define R_ESC_AL_STATUS_ERR_Msk                    (0x10UL)       /*!< ERR (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_AL_STATUS_DEVICEID_Pos               (5UL)          /*!< DEVICEID (Bit 5)                                      */
+ #define R_ESC_AL_STATUS_DEVICEID_Msk               (0x20UL)       /*!< DEVICEID (Bitfield-Mask: 0x01)                        */
+/* ====================================================  AL_STATUS_CODE  ===================================================== */
+ #define R_ESC_AL_STATUS_CODE_STATUSCODE_Pos        (0UL)          /*!< STATUSCODE (Bit 0)                                    */
+ #define R_ESC_AL_STATUS_CODE_STATUSCODE_Msk        (0xffffUL)     /*!< STATUSCODE (Bitfield-Mask: 0xffff)                    */
+/* ===================================================  RUN_LED_OVERRIDE  ==================================================== */
+ #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Pos         (0UL)          /*!< LEDCODE (Bit 0)                                       */
+ #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Msk         (0xfUL)        /*!< LEDCODE (Bitfield-Mask: 0x0f)                         */
+ #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Pos      (4UL)          /*!< OVERRIDEEN (Bit 4)                                    */
+ #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Msk      (0x10UL)       /*!< OVERRIDEEN (Bitfield-Mask: 0x01)                      */
+/* ===================================================  ERR_LED_OVERRIDE  ==================================================== */
+ #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Pos         (0UL)          /*!< LEDCODE (Bit 0)                                       */
+ #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Msk         (0xfUL)        /*!< LEDCODE (Bitfield-Mask: 0x0f)                         */
+ #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Pos      (4UL)          /*!< OVERRIDEEN (Bit 4)                                    */
+ #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Msk      (0x10UL)       /*!< OVERRIDEEN (Bitfield-Mask: 0x01)                      */
+/* ======================================================  PDI_CONTROL  ====================================================== */
+ #define R_ESC_PDI_CONTROL_PDI_Pos                  (0UL)          /*!< PDI (Bit 0)                                           */
+ #define R_ESC_PDI_CONTROL_PDI_Msk                  (0xffUL)       /*!< PDI (Bitfield-Mask: 0xff)                             */
+/* ======================================================  ESC_CONFIG  ======================================================= */
+ #define R_ESC_ESC_CONFIG_DEVEMU_Pos                (0UL)          /*!< DEVEMU (Bit 0)                                        */
+ #define R_ESC_ESC_CONFIG_DEVEMU_Msk                (0x1UL)        /*!< DEVEMU (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ESC_CONFIG_ENLALLP_Pos               (1UL)          /*!< ENLALLP (Bit 1)                                       */
+ #define R_ESC_ESC_CONFIG_ENLALLP_Msk               (0x2UL)        /*!< ENLALLP (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_CONFIG_DCSYNC_Pos                (2UL)          /*!< DCSYNC (Bit 2)                                        */
+ #define R_ESC_ESC_CONFIG_DCSYNC_Msk                (0x4UL)        /*!< DCSYNC (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ESC_CONFIG_DCLATCH_Pos               (3UL)          /*!< DCLATCH (Bit 3)                                       */
+ #define R_ESC_ESC_CONFIG_DCLATCH_Msk               (0x8UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_CONFIG_ENLP0_Pos                 (4UL)          /*!< ENLP0 (Bit 4)                                         */
+ #define R_ESC_ESC_CONFIG_ENLP0_Msk                 (0x10UL)       /*!< ENLP0 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_CONFIG_ENLP1_Pos                 (5UL)          /*!< ENLP1 (Bit 5)                                         */
+ #define R_ESC_ESC_CONFIG_ENLP1_Msk                 (0x20UL)       /*!< ENLP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_CONFIG_ENLP2_Pos                 (6UL)          /*!< ENLP2 (Bit 6)                                         */
+ #define R_ESC_ESC_CONFIG_ENLP2_Msk                 (0x40UL)       /*!< ENLP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_CONFIG_ENLP3_Pos                 (7UL)          /*!< ENLP3 (Bit 7)                                         */
+ #define R_ESC_ESC_CONFIG_ENLP3_Msk                 (0x80UL)       /*!< ENLP3 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  PDI_CONFIG  ======================================================= */
+ #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Pos          (0UL)          /*!< ONCHIPBUSCLK (Bit 0)                                  */
+ #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Msk          (0x1fUL)       /*!< ONCHIPBUSCLK (Bitfield-Mask: 0x1f)                    */
+ #define R_ESC_PDI_CONFIG_ONCHIPBUS_Pos             (5UL)          /*!< ONCHIPBUS (Bit 5)                                     */
+ #define R_ESC_PDI_CONFIG_ONCHIPBUS_Msk             (0xe0UL)       /*!< ONCHIPBUS (Bitfield-Mask: 0x07)                       */
+/* ===================================================  SYNC_LATCH_CONFIG  =================================================== */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Pos       (0UL)          /*!< SYNC0OUT (Bit 0)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Msk       (0x3UL)        /*!< SYNC0OUT (Bitfield-Mask: 0x03)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Pos       (2UL)          /*!< SYNCLAT0 (Bit 2)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Msk       (0x4UL)        /*!< SYNCLAT0 (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Pos       (3UL)          /*!< SYNC0MAP (Bit 3)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Msk       (0x8UL)        /*!< SYNC0MAP (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Pos       (4UL)          /*!< SYNC1OUT (Bit 4)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Msk       (0x30UL)       /*!< SYNC1OUT (Bitfield-Mask: 0x03)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Pos       (6UL)          /*!< SYNCLAT1 (Bit 6)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Msk       (0x40UL)       /*!< SYNCLAT1 (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Pos       (7UL)          /*!< SYNC1MAP (Bit 7)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Msk       (0x80UL)       /*!< SYNC1MAP (Bitfield-Mask: 0x01)                        */
+/* ====================================================  EXT_PDI_CONFIG  ===================================================== */
+ #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Pos        (0UL)          /*!< DATABUSWID (Bit 0)                                    */
+ #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Msk        (0x3UL)        /*!< DATABUSWID (Bitfield-Mask: 0x03)                      */
+/* ====================================================  ECAT_EVENT_MASK  ==================================================== */
+ #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Pos       (0UL)          /*!< ECATEVMASK (Bit 0)                                    */
+ #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Msk       (0xffffUL)     /*!< ECATEVMASK (Bitfield-Mask: 0xffff)                    */
+/* =====================================================  AL_EVENT_MASK  ===================================================== */
+ #define R_ESC_AL_EVENT_MASK_ALEVMASK_Pos           (0UL)          /*!< ALEVMASK (Bit 0)                                      */
+ #define R_ESC_AL_EVENT_MASK_ALEVMASK_Msk           (0xffffffffUL) /*!< ALEVMASK (Bitfield-Mask: 0xffffffff)                  */
+/* ====================================================  ECAT_EVENT_REQ  ===================================================== */
+ #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Pos           (0UL)          /*!< DCLATCH (Bit 0)                                       */
+ #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Msk           (0x1UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ECAT_EVENT_REQ_DLSTA_Pos             (2UL)          /*!< DLSTA (Bit 2)                                         */
+ #define R_ESC_ECAT_EVENT_REQ_DLSTA_Msk             (0x4UL)        /*!< DLSTA (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ECAT_EVENT_REQ_ALSTA_Pos             (3UL)          /*!< ALSTA (Bit 3)                                         */
+ #define R_ESC_ECAT_EVENT_REQ_ALSTA_Msk             (0x8UL)        /*!< ALSTA (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Pos            (4UL)          /*!< SMSTA0 (Bit 4)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Msk            (0x10UL)       /*!< SMSTA0 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Pos            (5UL)          /*!< SMSTA1 (Bit 5)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Msk            (0x20UL)       /*!< SMSTA1 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Pos            (6UL)          /*!< SMSTA2 (Bit 6)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Msk            (0x40UL)       /*!< SMSTA2 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Pos            (7UL)          /*!< SMSTA3 (Bit 7)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Msk            (0x80UL)       /*!< SMSTA3 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Pos            (8UL)          /*!< SMSTA4 (Bit 8)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Msk            (0x100UL)      /*!< SMSTA4 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Pos            (9UL)          /*!< SMSTA5 (Bit 9)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Msk            (0x200UL)      /*!< SMSTA5 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Pos            (10UL)         /*!< SMSTA6 (Bit 10)                                       */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Msk            (0x400UL)      /*!< SMSTA6 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Pos            (11UL)         /*!< SMSTA7 (Bit 11)                                       */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Msk            (0x800UL)      /*!< SMSTA7 (Bitfield-Mask: 0x01)                          */
+/* =====================================================  AL_EVENT_REQ  ====================================================== */
+ #define R_ESC_AL_EVENT_REQ_ALCTRL_Pos              (0UL)          /*!< ALCTRL (Bit 0)                                        */
+ #define R_ESC_AL_EVENT_REQ_ALCTRL_Msk              (0x1UL)        /*!< ALCTRL (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_DCLATCH_Pos             (1UL)          /*!< DCLATCH (Bit 1)                                       */
+ #define R_ESC_AL_EVENT_REQ_DCLATCH_Msk             (0x2UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Pos          (2UL)          /*!< DCSYNC0STA (Bit 2)                                    */
+ #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Msk          (0x4UL)        /*!< DCSYNC0STA (Bitfield-Mask: 0x01)                      */
+ #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Pos          (3UL)          /*!< DCSYNC1STA (Bit 3)                                    */
+ #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Msk          (0x8UL)        /*!< DCSYNC1STA (Bitfield-Mask: 0x01)                      */
+ #define R_ESC_AL_EVENT_REQ_SYNCACT_Pos             (4UL)          /*!< SYNCACT (Bit 4)                                       */
+ #define R_ESC_AL_EVENT_REQ_SYNCACT_Msk             (0x10UL)       /*!< SYNCACT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_AL_EVENT_REQ_WDPD_Pos                (6UL)          /*!< WDPD (Bit 6)                                          */
+ #define R_ESC_AL_EVENT_REQ_WDPD_Msk                (0x40UL)       /*!< WDPD (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_AL_EVENT_REQ_SMINT0_Pos              (8UL)          /*!< SMINT0 (Bit 8)                                        */
+ #define R_ESC_AL_EVENT_REQ_SMINT0_Msk              (0x100UL)      /*!< SMINT0 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT1_Pos              (9UL)          /*!< SMINT1 (Bit 9)                                        */
+ #define R_ESC_AL_EVENT_REQ_SMINT1_Msk              (0x200UL)      /*!< SMINT1 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT2_Pos              (10UL)         /*!< SMINT2 (Bit 10)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT2_Msk              (0x400UL)      /*!< SMINT2 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT3_Pos              (11UL)         /*!< SMINT3 (Bit 11)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT3_Msk              (0x800UL)      /*!< SMINT3 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT4_Pos              (12UL)         /*!< SMINT4 (Bit 12)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT4_Msk              (0x1000UL)     /*!< SMINT4 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT5_Pos              (13UL)         /*!< SMINT5 (Bit 13)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT5_Msk              (0x2000UL)     /*!< SMINT5 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT6_Pos              (14UL)         /*!< SMINT6 (Bit 14)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT6_Msk              (0x4000UL)     /*!< SMINT6 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT7_Pos              (15UL)         /*!< SMINT7 (Bit 15)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT7_Msk              (0x8000UL)     /*!< SMINT7 (Bitfield-Mask: 0x01)                          */
+/* =====================================================  RX_ERR_COUNT  ====================================================== */
+ #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Pos           (0UL)          /*!< INVFRMCNT (Bit 0)                                     */
+ #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Msk           (0xffUL)       /*!< INVFRMCNT (Bitfield-Mask: 0xff)                       */
+ #define R_ESC_RX_ERR_COUNT_RXERRCNT_Pos            (8UL)          /*!< RXERRCNT (Bit 8)                                      */
+ #define R_ESC_RX_ERR_COUNT_RXERRCNT_Msk            (0xff00UL)     /*!< RXERRCNT (Bitfield-Mask: 0xff)                        */
+/* ===================================================  FWD_RX_ERR_COUNT  ==================================================== */
+ #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Pos       (0UL)          /*!< FWDERRCNT (Bit 0)                                     */
+ #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Msk       (0xffUL)       /*!< FWDERRCNT (Bitfield-Mask: 0xff)                       */
+/* ==================================================  ECAT_PROC_ERR_COUNT  ================================================== */
+ #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Pos    (0UL)          /*!< EPUERRCNT (Bit 0)                                     */
+ #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Msk    (0xffUL)       /*!< EPUERRCNT (Bitfield-Mask: 0xff)                       */
+/* =====================================================  PDI_ERR_COUNT  ===================================================== */
+ #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Pos          (0UL)          /*!< PDIERRCNT (Bit 0)                                     */
+ #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Msk          (0xffUL)       /*!< PDIERRCNT (Bitfield-Mask: 0xff)                       */
+/* ====================================================  LOST_LINK_COUNT  ==================================================== */
+ #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Pos      (0UL)          /*!< LOSTLINKCNT (Bit 0)                                   */
+ #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Msk      (0xffUL)       /*!< LOSTLINKCNT (Bitfield-Mask: 0xff)                     */
+/* =======================================================  WD_DIVIDE  ======================================================= */
+ #define R_ESC_WD_DIVIDE_WDDIV_Pos                  (0UL)          /*!< WDDIV (Bit 0)                                         */
+ #define R_ESC_WD_DIVIDE_WDDIV_Msk                  (0xffffUL)     /*!< WDDIV (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  WDT_PDI  ======================================================== */
+ #define R_ESC_WDT_PDI_WDTIMPDI_Pos                 (0UL)          /*!< WDTIMPDI (Bit 0)                                      */
+ #define R_ESC_WDT_PDI_WDTIMPDI_Msk                 (0xffffUL)     /*!< WDTIMPDI (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  WDT_DATA  ======================================================== */
+ #define R_ESC_WDT_DATA_WDTIMPD_Pos                 (0UL)          /*!< WDTIMPD (Bit 0)                                       */
+ #define R_ESC_WDT_DATA_WDTIMPD_Msk                 (0xffffUL)     /*!< WDTIMPD (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  WDS_DATA  ======================================================== */
+ #define R_ESC_WDS_DATA_WDSTAPD_Pos                 (0UL)          /*!< WDSTAPD (Bit 0)                                       */
+ #define R_ESC_WDS_DATA_WDSTAPD_Msk                 (0x1UL)        /*!< WDSTAPD (Bitfield-Mask: 0x01)                         */
+/* =======================================================  WDC_DATA  ======================================================== */
+ #define R_ESC_WDC_DATA_WDCNTPD_Pos                 (0UL)          /*!< WDCNTPD (Bit 0)                                       */
+ #define R_ESC_WDC_DATA_WDCNTPD_Msk                 (0xffUL)       /*!< WDCNTPD (Bitfield-Mask: 0xff)                         */
+/* ========================================================  WDC_PDI  ======================================================== */
+ #define R_ESC_WDC_PDI_WDCNTPDI_Pos                 (0UL)          /*!< WDCNTPDI (Bit 0)                                      */
+ #define R_ESC_WDC_PDI_WDCNTPDI_Msk                 (0xffUL)       /*!< WDCNTPDI (Bitfield-Mask: 0xff)                        */
+/* =======================================================  EEP_CONF  ======================================================== */
+ #define R_ESC_EEP_CONF_CTRLPDI_Pos                 (0UL)          /*!< CTRLPDI (Bit 0)                                       */
+ #define R_ESC_EEP_CONF_CTRLPDI_Msk                 (0x1UL)        /*!< CTRLPDI (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_EEP_CONF_FORCEECAT_Pos               (1UL)          /*!< FORCEECAT (Bit 1)                                     */
+ #define R_ESC_EEP_CONF_FORCEECAT_Msk               (0x2UL)        /*!< FORCEECAT (Bitfield-Mask: 0x01)                       */
+/* =======================================================  EEP_STATE  ======================================================= */
+ #define R_ESC_EEP_STATE_PDIACCESS_Pos              (0UL)          /*!< PDIACCESS (Bit 0)                                     */
+ #define R_ESC_EEP_STATE_PDIACCESS_Msk              (0x1UL)        /*!< PDIACCESS (Bitfield-Mask: 0x01)                       */
+/* =====================================================  EEP_CONT_STAT  ===================================================== */
+ #define R_ESC_EEP_CONT_STAT_ECATWREN_Pos           (0UL)          /*!< ECATWREN (Bit 0)                                      */
+ #define R_ESC_EEP_CONT_STAT_ECATWREN_Msk           (0x1UL)        /*!< ECATWREN (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_EEP_CONT_STAT_READBYTE_Pos           (6UL)          /*!< READBYTE (Bit 6)                                      */
+ #define R_ESC_EEP_CONT_STAT_READBYTE_Msk           (0x40UL)       /*!< READBYTE (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_EEP_CONT_STAT_PROMSIZE_Pos           (7UL)          /*!< PROMSIZE (Bit 7)                                      */
+ #define R_ESC_EEP_CONT_STAT_PROMSIZE_Msk           (0x80UL)       /*!< PROMSIZE (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_EEP_CONT_STAT_COMMAND_Pos            (8UL)          /*!< COMMAND (Bit 8)                                       */
+ #define R_ESC_EEP_CONT_STAT_COMMAND_Msk            (0x700UL)      /*!< COMMAND (Bitfield-Mask: 0x07)                         */
+ #define R_ESC_EEP_CONT_STAT_CKSUMERR_Pos           (11UL)         /*!< CKSUMERR (Bit 11)                                     */
+ #define R_ESC_EEP_CONT_STAT_CKSUMERR_Msk           (0x800UL)      /*!< CKSUMERR (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_EEP_CONT_STAT_LOADSTA_Pos            (12UL)         /*!< LOADSTA (Bit 12)                                      */
+ #define R_ESC_EEP_CONT_STAT_LOADSTA_Msk            (0x1000UL)     /*!< LOADSTA (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Pos          (13UL)         /*!< ACKCMDERR (Bit 13)                                    */
+ #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Msk          (0x2000UL)     /*!< ACKCMDERR (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_EEP_CONT_STAT_WRENERR_Pos            (14UL)         /*!< WRENERR (Bit 14)                                      */
+ #define R_ESC_EEP_CONT_STAT_WRENERR_Msk            (0x4000UL)     /*!< WRENERR (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_EEP_CONT_STAT_BUSY_Pos               (15UL)         /*!< BUSY (Bit 15)                                         */
+ #define R_ESC_EEP_CONT_STAT_BUSY_Msk               (0x8000UL)     /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ========================================================  EEP_ADR  ======================================================== */
+ #define R_ESC_EEP_ADR_ADDRESS_Pos                  (0UL)          /*!< ADDRESS (Bit 0)                                       */
+ #define R_ESC_EEP_ADR_ADDRESS_Msk                  (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  EEP_DATA  ======================================================== */
+ #define R_ESC_EEP_DATA_LODATA_Pos                  (0UL)          /*!< LODATA (Bit 0)                                        */
+ #define R_ESC_EEP_DATA_LODATA_Msk                  (0xffffUL)     /*!< LODATA (Bitfield-Mask: 0xffff)                        */
+ #define R_ESC_EEP_DATA_HIDATA_Pos                  (16UL)         /*!< HIDATA (Bit 16)                                       */
+ #define R_ESC_EEP_DATA_HIDATA_Msk                  (0xffff0000UL) /*!< HIDATA (Bitfield-Mask: 0xffff)                        */
+/* =====================================================  MII_CONT_STAT  ===================================================== */
+ #define R_ESC_MII_CONT_STAT_WREN_Pos               (0UL)          /*!< WREN (Bit 0)                                          */
+ #define R_ESC_MII_CONT_STAT_WREN_Msk               (0x1UL)        /*!< WREN (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_MII_CONT_STAT_PDICTRL_Pos            (1UL)          /*!< PDICTRL (Bit 1)                                       */
+ #define R_ESC_MII_CONT_STAT_PDICTRL_Msk            (0x2UL)        /*!< PDICTRL (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_MII_CONT_STAT_MILINK_Pos             (2UL)          /*!< MILINK (Bit 2)                                        */
+ #define R_ESC_MII_CONT_STAT_MILINK_Msk             (0x4UL)        /*!< MILINK (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_MII_CONT_STAT_PHYOFFSET_Pos          (3UL)          /*!< PHYOFFSET (Bit 3)                                     */
+ #define R_ESC_MII_CONT_STAT_PHYOFFSET_Msk          (0xf8UL)       /*!< PHYOFFSET (Bitfield-Mask: 0x1f)                       */
+ #define R_ESC_MII_CONT_STAT_COMMAND_Pos            (8UL)          /*!< COMMAND (Bit 8)                                       */
+ #define R_ESC_MII_CONT_STAT_COMMAND_Msk            (0x300UL)      /*!< COMMAND (Bitfield-Mask: 0x03)                         */
+ #define R_ESC_MII_CONT_STAT_READERR_Pos            (13UL)         /*!< READERR (Bit 13)                                      */
+ #define R_ESC_MII_CONT_STAT_READERR_Msk            (0x2000UL)     /*!< READERR (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_MII_CONT_STAT_CMDERR_Pos             (14UL)         /*!< CMDERR (Bit 14)                                       */
+ #define R_ESC_MII_CONT_STAT_CMDERR_Msk             (0x4000UL)     /*!< CMDERR (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_MII_CONT_STAT_BUSY_Pos               (15UL)         /*!< BUSY (Bit 15)                                         */
+ #define R_ESC_MII_CONT_STAT_BUSY_Msk               (0x8000UL)     /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PHY_ADR  ======================================================== */
+ #define R_ESC_PHY_ADR_PHYADDR_Pos                  (0UL)          /*!< PHYADDR (Bit 0)                                       */
+ #define R_ESC_PHY_ADR_PHYADDR_Msk                  (0x1fUL)       /*!< PHYADDR (Bitfield-Mask: 0x1f)                         */
+/* ======================================================  PHY_REG_ADR  ====================================================== */
+ #define R_ESC_PHY_REG_ADR_PHYREGADDR_Pos           (0UL)          /*!< PHYREGADDR (Bit 0)                                    */
+ #define R_ESC_PHY_REG_ADR_PHYREGADDR_Msk           (0x1fUL)       /*!< PHYREGADDR (Bitfield-Mask: 0x1f)                      */
+/* =======================================================  PHY_DATA  ======================================================== */
+ #define R_ESC_PHY_DATA_PHYREGDATA_Pos              (0UL)          /*!< PHYREGDATA (Bit 0)                                    */
+ #define R_ESC_PHY_DATA_PHYREGDATA_Msk              (0xffffUL)     /*!< PHYREGDATA (Bitfield-Mask: 0xffff)                    */
+/* ===================================================  MII_ECAT_ACS_STAT  =================================================== */
+ #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Pos         (0UL)          /*!< ACSMII (Bit 0)                                        */
+ #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Msk         (0x1UL)        /*!< ACSMII (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MII_PDI_ACS_STAT  ==================================================== */
+ #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Pos          (0UL)          /*!< ACSMII (Bit 0)                                        */
+ #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Msk          (0x1UL)        /*!< ACSMII (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Pos          (1UL)          /*!< FORPDI (Bit 1)                                        */
+ #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Msk          (0x2UL)        /*!< FORPDI (Bitfield-Mask: 0x01)                          */
+/* ===================================================  DC_RCV_TIME_PORT  ==================================================== */
+ #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Pos        (0UL)          /*!< RCVTIME0 (Bit 0)                                      */
+ #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Msk        (0xffffffffUL) /*!< RCVTIME0 (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  DC_SYS_TIME_L  ===================================================== */
+/* =====================================================  DC_SYS_TIME_H  ===================================================== */
+/* ==================================================  DC_RCV_TIME_UNIT_L  =================================================== */
+/* ==================================================  DC_RCV_TIME_UNIT_H  =================================================== */
+/* =================================================  DC_SYS_TIME_OFFSET_L  ================================================== */
+/* =================================================  DC_SYS_TIME_OFFSET_H  ================================================== */
+/* ===================================================  DC_SYS_TIME_DELAY  =================================================== */
+ #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Pos             (0UL)          /*!< SYSTIMDLY (Bit 0)                                     */
+ #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Msk             (0xffffffffUL) /*!< SYSTIMDLY (Bitfield-Mask: 0xffffffff)                 */
+/* ===================================================  DC_SYS_TIME_DIFF  ==================================================== */
+ #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Pos                   (0UL)          /*!< DIFF (Bit 0)                                          */
+ #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Msk                   (0x7fffffffUL) /*!< DIFF (Bitfield-Mask: 0x7fffffff)                      */
+ #define R_ESC_DC_SYS_TIME_DIFF_LCP_Pos                    (31UL)         /*!< LCP (Bit 31)                                          */
+ #define R_ESC_DC_SYS_TIME_DIFF_LCP_Msk                    (0x80000000UL) /*!< LCP (Bitfield-Mask: 0x01)                             */
+/* =================================================  DC_SPEED_COUNT_START  ================================================== */
+ #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Pos         (0UL)          /*!< SPDCNTSTRT (Bit 0)                                    */
+ #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Msk         (0x7fffUL)     /*!< SPDCNTSTRT (Bitfield-Mask: 0x7fff)                    */
+/* ==================================================  DC_SPEED_COUNT_DIFF  ================================================== */
+ #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Pos          (0UL)          /*!< SPDCNTDIFF (Bit 0)                                    */
+ #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Msk          (0xffffUL)     /*!< SPDCNTDIFF (Bitfield-Mask: 0xffff)                    */
+/* ==============================================  DC_SYS_TIME_DIFF_FIL_DEPTH  =============================================== */
+ #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Pos    (0UL)          /*!< SYSTIMDEP (Bit 0)                                     */
+ #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Msk    (0xfUL)        /*!< SYSTIMDEP (Bitfield-Mask: 0x0f)                       */
+/* ===============================================  DC_SPEED_COUNT_FIL_DEPTH  ================================================ */
+ #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Pos      (0UL)          /*!< CLKPERDEP (Bit 0)                                     */
+ #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Msk      (0xfUL)        /*!< CLKPERDEP (Bitfield-Mask: 0x0f)                       */
+/* ======================================================  DC_CYC_CONT  ====================================================== */
+ #define R_ESC_DC_CYC_CONT_SYNCOUT_Pos                     (0UL)          /*!< SYNCOUT (Bit 0)                                       */
+ #define R_ESC_DC_CYC_CONT_SYNCOUT_Msk                     (0x1UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_CYC_CONT_LATCH0_Pos                      (4UL)          /*!< LATCH0 (Bit 4)                                        */
+ #define R_ESC_DC_CYC_CONT_LATCH0_Msk                      (0x10UL)       /*!< LATCH0 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_DC_CYC_CONT_LATCH1_Pos                      (5UL)          /*!< LATCH1 (Bit 5)                                        */
+ #define R_ESC_DC_CYC_CONT_LATCH1_Msk                      (0x20UL)       /*!< LATCH1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DC_ACT  ========================================================= */
+ #define R_ESC_DC_ACT_SYNCACT_Pos                          (0UL)          /*!< SYNCACT (Bit 0)                                       */
+ #define R_ESC_DC_ACT_SYNCACT_Msk                          (0x1UL)        /*!< SYNCACT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_ACT_SYNC0_Pos                            (1UL)          /*!< SYNC0 (Bit 1)                                         */
+ #define R_ESC_DC_ACT_SYNC0_Msk                            (0x2UL)        /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_DC_ACT_SYNC1_Pos                            (2UL)          /*!< SYNC1 (Bit 2)                                         */
+ #define R_ESC_DC_ACT_SYNC1_Msk                            (0x4UL)        /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_DC_ACT_AUTOACT_Pos                          (3UL)          /*!< AUTOACT (Bit 3)                                       */
+ #define R_ESC_DC_ACT_AUTOACT_Msk                          (0x8UL)        /*!< AUTOACT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_ACT_EXTSTARTTIME_Pos                     (4UL)          /*!< EXTSTARTTIME (Bit 4)                                  */
+ #define R_ESC_DC_ACT_EXTSTARTTIME_Msk                     (0x10UL)       /*!< EXTSTARTTIME (Bitfield-Mask: 0x01)                    */
+ #define R_ESC_DC_ACT_STARTTIME_Pos                        (5UL)          /*!< STARTTIME (Bit 5)                                     */
+ #define R_ESC_DC_ACT_STARTTIME_Msk                        (0x20UL)       /*!< STARTTIME (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_DC_ACT_NEARFUTURE_Pos                       (6UL)          /*!< NEARFUTURE (Bit 6)                                    */
+ #define R_ESC_DC_ACT_NEARFUTURE_Msk                       (0x40UL)       /*!< NEARFUTURE (Bitfield-Mask: 0x01)                      */
+ #define R_ESC_DC_ACT_DBGPULSE_Pos                         (7UL)          /*!< DBGPULSE (Bit 7)                                      */
+ #define R_ESC_DC_ACT_DBGPULSE_Msk                         (0x80UL)       /*!< DBGPULSE (Bitfield-Mask: 0x01)                        */
+/* =====================================================  DC_PULSE_LEN  ====================================================== */
+ #define R_ESC_DC_PULSE_LEN_PULSELEN_Pos                   (0UL)          /*!< PULSELEN (Bit 0)                                      */
+ #define R_ESC_DC_PULSE_LEN_PULSELEN_Msk                   (0xffffUL)     /*!< PULSELEN (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  DC_ACT_STAT  ====================================================== */
+ #define R_ESC_DC_ACT_STAT_SYNC0ACT_Pos                    (0UL)          /*!< SYNC0ACT (Bit 0)                                      */
+ #define R_ESC_DC_ACT_STAT_SYNC0ACT_Msk                    (0x1UL)        /*!< SYNC0ACT (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_ACT_STAT_SYNC1ACT_Pos                    (1UL)          /*!< SYNC1ACT (Bit 1)                                      */
+ #define R_ESC_DC_ACT_STAT_SYNC1ACT_Msk                    (0x2UL)        /*!< SYNC1ACT (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_ACT_STAT_STARTTIME_Pos                   (2UL)          /*!< STARTTIME (Bit 2)                                     */
+ #define R_ESC_DC_ACT_STAT_STARTTIME_Msk                   (0x4UL)        /*!< STARTTIME (Bitfield-Mask: 0x01)                       */
+/* =====================================================  DC_SYNC0_STAT  ===================================================== */
+ #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Pos                  (0UL)          /*!< SYNC0STA (Bit 0)                                      */
+ #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Msk                  (0x1UL)        /*!< SYNC0STA (Bitfield-Mask: 0x01)                        */
+/* =====================================================  DC_SYNC1_STAT  ===================================================== */
+ #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Pos                  (0UL)          /*!< SYNC1STA (Bit 0)                                      */
+ #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Msk                  (0x1UL)        /*!< SYNC1STA (Bitfield-Mask: 0x01)                        */
+/* ==================================================  DC_CYC_START_TIME_L  ================================================== */
+/* ==================================================  DC_CYC_START_TIME_H  ================================================== */
+/* =================================================  DC_NEXT_SYNC1_PULSE_L  ================================================= */
+/* =================================================  DC_NEXT_SYNC1_PULSE_H  ================================================= */
+/* ===================================================  DC_SYNC0_CYC_TIME  =================================================== */
+ #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Pos    (0UL)          /*!< SYNC0CYC (Bit 0)                                      */
+ #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Msk    (0xffffffffUL) /*!< SYNC0CYC (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  DC_SYNC1_CYC_TIME  =================================================== */
+ #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Pos    (0UL)          /*!< SYNC1CYC (Bit 0)                                      */
+ #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Msk    (0xffffffffUL) /*!< SYNC1CYC (Bitfield-Mask: 0xffffffff)                  */
+/* ====================================================  DC_LATCH0_CONT  ===================================================== */
+ #define R_ESC_DC_LATCH0_CONT_POSEDGE_Pos        (0UL)          /*!< POSEDGE (Bit 0)                                       */
+ #define R_ESC_DC_LATCH0_CONT_POSEDGE_Msk        (0x1UL)        /*!< POSEDGE (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Pos        (1UL)          /*!< NEGEDGE (Bit 1)                                       */
+ #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Msk        (0x2UL)        /*!< NEGEDGE (Bitfield-Mask: 0x01)                         */
+/* ====================================================  DC_LATCH1_CONT  ===================================================== */
+ #define R_ESC_DC_LATCH1_CONT_POSEDGE_Pos        (0UL)          /*!< POSEDGE (Bit 0)                                       */
+ #define R_ESC_DC_LATCH1_CONT_POSEDGE_Msk        (0x1UL)        /*!< POSEDGE (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Pos        (1UL)          /*!< NEGEDGE (Bit 1)                                       */
+ #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Msk        (0x2UL)        /*!< NEGEDGE (Bitfield-Mask: 0x01)                         */
+/* ====================================================  DC_LATCH0_STAT  ===================================================== */
+ #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Pos       (0UL)          /*!< EVENTPOS (Bit 0)                                      */
+ #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Msk       (0x1UL)        /*!< EVENTPOS (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Pos       (1UL)          /*!< EVENTNEG (Bit 1)                                      */
+ #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Msk       (0x2UL)        /*!< EVENTNEG (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_LATCH0_STAT_PINSTATE_Pos       (2UL)          /*!< PINSTATE (Bit 2)                                      */
+ #define R_ESC_DC_LATCH0_STAT_PINSTATE_Msk       (0x4UL)        /*!< PINSTATE (Bitfield-Mask: 0x01)                        */
+/* ====================================================  DC_LATCH1_STAT  ===================================================== */
+ #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Pos       (0UL)          /*!< EVENTPOS (Bit 0)                                      */
+ #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Msk       (0x1UL)        /*!< EVENTPOS (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Pos       (1UL)          /*!< EVENTNEG (Bit 1)                                      */
+ #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Msk       (0x2UL)        /*!< EVENTNEG (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_LATCH1_STAT_PINSTATE_Pos       (2UL)          /*!< PINSTATE (Bit 2)                                      */
+ #define R_ESC_DC_LATCH1_STAT_PINSTATE_Msk       (0x4UL)        /*!< PINSTATE (Bitfield-Mask: 0x01)                        */
+/* =================================================  DC_LATCH0_TIME_POS_L  ================================================== */
+/* =================================================  DC_LATCH0_TIME_POS_H  ================================================== */
+/* =================================================  DC_LATCH0_TIME_NEG_L  ================================================== */
+/* =================================================  DC_LATCH0_TIME_NEG_H  ================================================== */
+/* =================================================  DC_LATCH1_TIME_POS_L  ================================================== */
+/* =================================================  DC_LATCH1_TIME_POS_H  ================================================== */
+/* =================================================  DC_LATCH1_TIME_NEG_L  ================================================== */
+/* =================================================  DC_LATCH1_TIME_NEG_H  ================================================== */
+/* ==================================================  DC_ECAT_CNG_EV_TIME  ================================================== */
+ #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Pos    (0UL)          /*!< ECATCHANGE (Bit 0)                                    */
+ #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Msk    (0xffffffffUL) /*!< ECATCHANGE (Bitfield-Mask: 0xffffffff)                */
+/* =================================================  DC_PDI_START_EV_TIME  ================================================== */
+ #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Pos     (0UL)          /*!< PDISTART (Bit 0)                                      */
+ #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Msk     (0xffffffffUL) /*!< PDISTART (Bitfield-Mask: 0xffffffff)                  */
+/* ==================================================  DC_PDI_CNG_EV_TIME  =================================================== */
+ #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Pos      (0UL)          /*!< PDICHANGE (Bit 0)                                     */
+ #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Msk      (0xffffffffUL) /*!< PDICHANGE (Bitfield-Mask: 0xffffffff)                 */
+/* =====================================================  PRODUCT_ID_L  ====================================================== */
+/* =====================================================  PRODUCT_ID_H  ====================================================== */
+/* ======================================================  VENDOR_ID_L  ====================================================== */
+ #define R_ESC_VENDOR_ID_L_VENDORID_Pos              (0UL)          /*!< VENDORID (Bit 0)                                      */
+ #define R_ESC_VENDOR_ID_L_VENDORID_Msk              (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff)                  */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USBHC                                          ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  HCREVISION  ======================================================= */
+ #define R_USBHC_HCREVISION_REV_Pos              (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_USBHC_HCREVISION_REV_Msk              (0xffUL)       /*!< REV (Bitfield-Mask: 0xff)                             */
+/* =======================================================  HCCONTROL  ======================================================= */
+ #define R_USBHC_HCCONTROL_CBSR_Pos              (0UL)          /*!< CBSR (Bit 0)                                          */
+ #define R_USBHC_HCCONTROL_CBSR_Msk              (0x3UL)        /*!< CBSR (Bitfield-Mask: 0x03)                            */
+ #define R_USBHC_HCCONTROL_PLE_Pos               (2UL)          /*!< PLE (Bit 2)                                           */
+ #define R_USBHC_HCCONTROL_PLE_Msk               (0x4UL)        /*!< PLE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCONTROL_IE_Pos                (3UL)          /*!< IE (Bit 3)                                            */
+ #define R_USBHC_HCCONTROL_IE_Msk                (0x8UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCCONTROL_CLE_Pos               (4UL)          /*!< CLE (Bit 4)                                           */
+ #define R_USBHC_HCCONTROL_CLE_Msk               (0x10UL)       /*!< CLE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCONTROL_BLE_Pos               (5UL)          /*!< BLE (Bit 5)                                           */
+ #define R_USBHC_HCCONTROL_BLE_Msk               (0x20UL)       /*!< BLE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCONTROL_HCFS_Pos              (6UL)          /*!< HCFS (Bit 6)                                          */
+ #define R_USBHC_HCCONTROL_HCFS_Msk              (0xc0UL)       /*!< HCFS (Bitfield-Mask: 0x03)                            */
+ #define R_USBHC_HCCONTROL_IR_Pos                (8UL)          /*!< IR (Bit 8)                                            */
+ #define R_USBHC_HCCONTROL_IR_Msk                (0x100UL)      /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCCONTROL_RWC_Pos               (9UL)          /*!< RWC (Bit 9)                                           */
+ #define R_USBHC_HCCONTROL_RWC_Msk               (0x200UL)      /*!< RWC (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCONTROL_RWE_Pos               (10UL)         /*!< RWE (Bit 10)                                          */
+ #define R_USBHC_HCCONTROL_RWE_Msk               (0x400UL)      /*!< RWE (Bitfield-Mask: 0x01)                             */
+/* ====================================================  HCCOMMANDSTATUS  ==================================================== */
+ #define R_USBHC_HCCOMMANDSTATUS_HCR_Pos         (0UL)          /*!< HCR (Bit 0)                                           */
+ #define R_USBHC_HCCOMMANDSTATUS_HCR_Msk         (0x1UL)        /*!< HCR (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCOMMANDSTATUS_CLF_Pos         (1UL)          /*!< CLF (Bit 1)                                           */
+ #define R_USBHC_HCCOMMANDSTATUS_CLF_Msk         (0x2UL)        /*!< CLF (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCOMMANDSTATUS_BLF_Pos         (2UL)          /*!< BLF (Bit 2)                                           */
+ #define R_USBHC_HCCOMMANDSTATUS_BLF_Msk         (0x4UL)        /*!< BLF (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCOMMANDSTATUS_OCR_Pos         (3UL)          /*!< OCR (Bit 3)                                           */
+ #define R_USBHC_HCCOMMANDSTATUS_OCR_Msk         (0x8UL)        /*!< OCR (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCOMMANDSTATUS_SOC_Pos         (16UL)         /*!< SOC (Bit 16)                                          */
+ #define R_USBHC_HCCOMMANDSTATUS_SOC_Msk         (0x30000UL)    /*!< SOC (Bitfield-Mask: 0x03)                             */
+/* ===================================================  HCINTERRUPTSTATUS  =================================================== */
+ #define R_USBHC_HCINTERRUPTSTATUS_SO_Pos        (0UL)          /*!< SO (Bit 0)                                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_SO_Msk        (0x1UL)        /*!< SO (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCINTERRUPTSTATUS_WDH_Pos       (1UL)          /*!< WDH (Bit 1)                                           */
+ #define R_USBHC_HCINTERRUPTSTATUS_WDH_Msk       (0x2UL)        /*!< WDH (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTSTATUS_SF_Pos        (2UL)          /*!< SF (Bit 2)                                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_SF_Msk        (0x4UL)        /*!< SF (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCINTERRUPTSTATUS_RD_Pos        (3UL)          /*!< RD (Bit 3)                                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_RD_Msk        (0x8UL)        /*!< RD (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCINTERRUPTSTATUS_UE_Pos        (4UL)          /*!< UE (Bit 4)                                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_UE_Msk        (0x10UL)       /*!< UE (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCINTERRUPTSTATUS_FNO_Pos       (5UL)          /*!< FNO (Bit 5)                                           */
+ #define R_USBHC_HCINTERRUPTSTATUS_FNO_Msk       (0x20UL)       /*!< FNO (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Pos      (6UL)          /*!< RHSC (Bit 6)                                          */
+ #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Msk      (0x40UL)       /*!< RHSC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_OC_Pos        (30UL)         /*!< OC (Bit 30)                                           */
+ #define R_USBHC_HCINTERRUPTSTATUS_OC_Msk        (0x40000000UL) /*!< OC (Bitfield-Mask: 0x01)                              */
+/* ===================================================  HCINTERRUPTENABLE  =================================================== */
+ #define R_USBHC_HCINTERRUPTENABLE_SOE_Pos       (0UL)          /*!< SOE (Bit 0)                                           */
+ #define R_USBHC_HCINTERRUPTENABLE_SOE_Msk       (0x1UL)        /*!< SOE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_WDHE_Pos      (1UL)          /*!< WDHE (Bit 1)                                          */
+ #define R_USBHC_HCINTERRUPTENABLE_WDHE_Msk      (0x2UL)        /*!< WDHE (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTENABLE_SFE_Pos       (2UL)          /*!< SFE (Bit 2)                                           */
+ #define R_USBHC_HCINTERRUPTENABLE_SFE_Msk       (0x4UL)        /*!< SFE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_RDE_Pos       (3UL)          /*!< RDE (Bit 3)                                           */
+ #define R_USBHC_HCINTERRUPTENABLE_RDE_Msk       (0x8UL)        /*!< RDE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_UEE_Pos       (4UL)          /*!< UEE (Bit 4)                                           */
+ #define R_USBHC_HCINTERRUPTENABLE_UEE_Msk       (0x10UL)       /*!< UEE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_FNOE_Pos      (5UL)          /*!< FNOE (Bit 5)                                          */
+ #define R_USBHC_HCINTERRUPTENABLE_FNOE_Msk      (0x20UL)       /*!< FNOE (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Pos     (6UL)          /*!< RHSCE (Bit 6)                                         */
+ #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Msk     (0x40UL)       /*!< RHSCE (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_HCINTERRUPTENABLE_OCE_Pos       (30UL)         /*!< OCE (Bit 30)                                          */
+ #define R_USBHC_HCINTERRUPTENABLE_OCE_Msk       (0x40000000UL) /*!< OCE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_MIE_Pos       (31UL)         /*!< MIE (Bit 31)                                          */
+ #define R_USBHC_HCINTERRUPTENABLE_MIE_Msk       (0x80000000UL) /*!< MIE (Bitfield-Mask: 0x01)                             */
+/* ==================================================  HCINTERRUPTDISABLE  =================================================== */
+ #define R_USBHC_HCINTERRUPTDISABLE_SOD_Pos      (0UL)          /*!< SOD (Bit 0)                                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_SOD_Msk      (0x1UL)        /*!< SOD (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Pos     (1UL)          /*!< WDHD (Bit 1)                                          */
+ #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Msk     (0x2UL)        /*!< WDHD (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTDISABLE_SFD_Pos      (2UL)          /*!< SFD (Bit 2)                                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_SFD_Msk      (0x4UL)        /*!< SFD (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_RDD_Pos      (3UL)          /*!< RDD (Bit 3)                                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_RDD_Msk      (0x8UL)        /*!< RDD (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_UED_Pos      (4UL)          /*!< UED (Bit 4)                                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_UED_Msk      (0x10UL)       /*!< UED (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Pos     (5UL)          /*!< FNOD (Bit 5)                                          */
+ #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Msk     (0x20UL)       /*!< FNOD (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Pos    (6UL)          /*!< RHSCD (Bit 6)                                         */
+ #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Msk    (0x40UL)       /*!< RHSCD (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_OCD_Pos      (30UL)         /*!< OCD (Bit 30)                                          */
+ #define R_USBHC_HCINTERRUPTDISABLE_OCD_Msk      (0x40000000UL) /*!< OCD (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_MID_Pos      (31UL)         /*!< MID (Bit 31)                                          */
+ #define R_USBHC_HCINTERRUPTDISABLE_MID_Msk      (0x80000000UL) /*!< MID (Bitfield-Mask: 0x01)                             */
+/* ========================================================  HCHCCA  ========================================================= */
+ #define R_USBHC_HCHCCA_RAMBA_Pos                (8UL)          /*!< RAMBA (Bit 8)                                         */
+ #define R_USBHC_HCHCCA_RAMBA_Msk                (0xffffff00UL) /*!< RAMBA (Bitfield-Mask: 0xffffff)                       */
+/* ==================================================  HCPERIODCCURRENTIED  ================================================== */
+ #define R_USBHC_HCPERIODCCURRENTIED_PCED_Pos    (4UL)          /*!< PCED (Bit 4)                                          */
+ #define R_USBHC_HCPERIODCCURRENTIED_PCED_Msk    (0xfffffff0UL) /*!< PCED (Bitfield-Mask: 0xfffffff)                       */
+/* ====================================================  HCCONTROLHEADED  ==================================================== */
+ #define R_USBHC_HCCONTROLHEADED_CHED_Pos        (4UL)          /*!< CHED (Bit 4)                                          */
+ #define R_USBHC_HCCONTROLHEADED_CHED_Msk        (0xfffffff0UL) /*!< CHED (Bitfield-Mask: 0xfffffff)                       */
+/* ==================================================  HCCONTROLCURRENTED  =================================================== */
+ #define R_USBHC_HCCONTROLCURRENTED_CCED_Pos     (4UL)          /*!< CCED (Bit 4)                                          */
+ #define R_USBHC_HCCONTROLCURRENTED_CCED_Msk     (0xfffffff0UL) /*!< CCED (Bitfield-Mask: 0xfffffff)                       */
+/* =====================================================  HCBULKHEADED  ====================================================== */
+ #define R_USBHC_HCBULKHEADED_BHED_Pos           (4UL)          /*!< BHED (Bit 4)                                          */
+ #define R_USBHC_HCBULKHEADED_BHED_Msk           (0xfffffff0UL) /*!< BHED (Bitfield-Mask: 0xfffffff)                       */
+/* ====================================================  HCBULKCURRENTED  ==================================================== */
+ #define R_USBHC_HCBULKCURRENTED_BCED_Pos        (4UL)          /*!< BCED (Bit 4)                                          */
+ #define R_USBHC_HCBULKCURRENTED_BCED_Msk        (0xfffffff0UL) /*!< BCED (Bitfield-Mask: 0xfffffff)                       */
+/* ======================================================  HCDONEHEAD  ======================================================= */
+ #define R_USBHC_HCDONEHEAD_DH_Pos               (4UL)          /*!< DH (Bit 4)                                            */
+ #define R_USBHC_HCDONEHEAD_DH_Msk               (0xfffffff0UL) /*!< DH (Bitfield-Mask: 0xfffffff)                         */
+/* =====================================================  HCFMINTERVAL  ====================================================== */
+ #define R_USBHC_HCFMINTERVAL_FI_Pos             (0UL)          /*!< FI (Bit 0)                                            */
+ #define R_USBHC_HCFMINTERVAL_FI_Msk             (0x3fffUL)     /*!< FI (Bitfield-Mask: 0x3fff)                            */
+ #define R_USBHC_HCFMINTERVAL_FSMPS_Pos          (16UL)         /*!< FSMPS (Bit 16)                                        */
+ #define R_USBHC_HCFMINTERVAL_FSMPS_Msk          (0x7fff0000UL) /*!< FSMPS (Bitfield-Mask: 0x7fff)                         */
+ #define R_USBHC_HCFMINTERVAL_FIT_Pos            (31UL)         /*!< FIT (Bit 31)                                          */
+ #define R_USBHC_HCFMINTERVAL_FIT_Msk            (0x80000000UL) /*!< FIT (Bitfield-Mask: 0x01)                             */
+/* =====================================================  HCFNREMAINING  ===================================================== */
+ #define R_USBHC_HCFNREMAINING_FR_Pos            (0UL)          /*!< FR (Bit 0)                                            */
+ #define R_USBHC_HCFNREMAINING_FR_Msk            (0x3fffUL)     /*!< FR (Bitfield-Mask: 0x3fff)                            */
+ #define R_USBHC_HCFNREMAINING_FRT_Pos           (31UL)         /*!< FRT (Bit 31)                                          */
+ #define R_USBHC_HCFNREMAINING_FRT_Msk           (0x80000000UL) /*!< FRT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HCFMNUMBER  ======================================================= */
+ #define R_USBHC_HCFMNUMBER_FN_Pos               (0UL)          /*!< FN (Bit 0)                                            */
+ #define R_USBHC_HCFMNUMBER_FN_Msk               (0xffffUL)     /*!< FN (Bitfield-Mask: 0xffff)                            */
+/* =====================================================  HCPERIODSTART  ===================================================== */
+ #define R_USBHC_HCPERIODSTART_PS_Pos            (0UL)          /*!< PS (Bit 0)                                            */
+ #define R_USBHC_HCPERIODSTART_PS_Msk            (0x3fffUL)     /*!< PS (Bitfield-Mask: 0x3fff)                            */
+/* =====================================================  HCLSTHRESHOLD  ===================================================== */
+ #define R_USBHC_HCLSTHRESHOLD_LS_Pos            (0UL)          /*!< LS (Bit 0)                                            */
+ #define R_USBHC_HCLSTHRESHOLD_LS_Msk            (0xfffUL)      /*!< LS (Bitfield-Mask: 0xfff)                             */
+/* ====================================================  HCRHDESCRIPTORA  ==================================================== */
+ #define R_USBHC_HCRHDESCRIPTORA_NDP_Pos         (0UL)          /*!< NDP (Bit 0)                                           */
+ #define R_USBHC_HCRHDESCRIPTORA_NDP_Msk         (0xffUL)       /*!< NDP (Bitfield-Mask: 0xff)                             */
+ #define R_USBHC_HCRHDESCRIPTORA_PSM_Pos         (8UL)          /*!< PSM (Bit 8)                                           */
+ #define R_USBHC_HCRHDESCRIPTORA_PSM_Msk         (0x100UL)      /*!< PSM (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHDESCRIPTORA_NPS_Pos         (9UL)          /*!< NPS (Bit 9)                                           */
+ #define R_USBHC_HCRHDESCRIPTORA_NPS_Msk         (0x200UL)      /*!< NPS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHDESCRIPTORA_DT_Pos          (10UL)         /*!< DT (Bit 10)                                           */
+ #define R_USBHC_HCRHDESCRIPTORA_DT_Msk          (0x400UL)      /*!< DT (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCRHDESCRIPTORA_OCPM_Pos        (11UL)         /*!< OCPM (Bit 11)                                         */
+ #define R_USBHC_HCRHDESCRIPTORA_OCPM_Msk        (0x800UL)      /*!< OCPM (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHDESCRIPTORA_NOCP_Pos        (12UL)         /*!< NOCP (Bit 12)                                         */
+ #define R_USBHC_HCRHDESCRIPTORA_NOCP_Msk        (0x1000UL)     /*!< NOCP (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Pos      (24UL)         /*!< POTPGT (Bit 24)                                       */
+ #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Msk      (0xff000000UL) /*!< POTPGT (Bitfield-Mask: 0xff)                          */
+/* ====================================================  HCRHDESCRIPTORB  ==================================================== */
+ #define R_USBHC_HCRHDESCRIPTORB_DR_Pos          (0UL)          /*!< DR (Bit 0)                                            */
+ #define R_USBHC_HCRHDESCRIPTORB_DR_Msk          (0xffffUL)     /*!< DR (Bitfield-Mask: 0xffff)                            */
+ #define R_USBHC_HCRHDESCRIPTORB_PPCM_Pos        (16UL)         /*!< PPCM (Bit 16)                                         */
+ #define R_USBHC_HCRHDESCRIPTORB_PPCM_Msk        (0xffff0000UL) /*!< PPCM (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  HCRHSTATUS  ======================================================= */
+ #define R_USBHC_HCRHSTATUS_LPS_Pos              (0UL)          /*!< LPS (Bit 0)                                           */
+ #define R_USBHC_HCRHSTATUS_LPS_Msk              (0x1UL)        /*!< LPS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHSTATUS_OCI_Pos              (1UL)          /*!< OCI (Bit 1)                                           */
+ #define R_USBHC_HCRHSTATUS_OCI_Msk              (0x2UL)        /*!< OCI (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHSTATUS_DRWE_Pos             (15UL)         /*!< DRWE (Bit 15)                                         */
+ #define R_USBHC_HCRHSTATUS_DRWE_Msk             (0x8000UL)     /*!< DRWE (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHSTATUS_LPSC_Pos             (16UL)         /*!< LPSC (Bit 16)                                         */
+ #define R_USBHC_HCRHSTATUS_LPSC_Msk             (0x10000UL)    /*!< LPSC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHSTATUS_OCIC_Pos             (17UL)         /*!< OCIC (Bit 17)                                         */
+ #define R_USBHC_HCRHSTATUS_OCIC_Msk             (0x20000UL)    /*!< OCIC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHSTATUS_CRWE_Pos             (31UL)         /*!< CRWE (Bit 31)                                         */
+ #define R_USBHC_HCRHSTATUS_CRWE_Msk             (0x80000000UL) /*!< CRWE (Bitfield-Mask: 0x01)                            */
+/* ====================================================  HCRHPORTSTATUS1  ==================================================== */
+ #define R_USBHC_HCRHPORTSTATUS1_CCS_Pos         (0UL)          /*!< CCS (Bit 0)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_CCS_Msk         (0x1UL)        /*!< CCS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_PES_Pos         (1UL)          /*!< PES (Bit 1)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_PES_Msk         (0x2UL)        /*!< PES (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_PSS_Pos         (2UL)          /*!< PSS (Bit 2)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_PSS_Msk         (0x4UL)        /*!< PSS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_POCI_Pos        (3UL)          /*!< POCI (Bit 3)                                          */
+ #define R_USBHC_HCRHPORTSTATUS1_POCI_Msk        (0x8UL)        /*!< POCI (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_PRS_Pos         (4UL)          /*!< PRS (Bit 4)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_PRS_Msk         (0x10UL)       /*!< PRS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_PPS_Pos         (8UL)          /*!< PPS (Bit 8)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_PPS_Msk         (0x100UL)      /*!< PPS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_LSDA_Pos        (9UL)          /*!< LSDA (Bit 9)                                          */
+ #define R_USBHC_HCRHPORTSTATUS1_LSDA_Msk        (0x200UL)      /*!< LSDA (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_CSC_Pos         (16UL)         /*!< CSC (Bit 16)                                          */
+ #define R_USBHC_HCRHPORTSTATUS1_CSC_Msk         (0x10000UL)    /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_PESC_Pos        (17UL)         /*!< PESC (Bit 17)                                         */
+ #define R_USBHC_HCRHPORTSTATUS1_PESC_Msk        (0x20000UL)    /*!< PESC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_PSSC_Pos        (18UL)         /*!< PSSC (Bit 18)                                         */
+ #define R_USBHC_HCRHPORTSTATUS1_PSSC_Msk        (0x40000UL)    /*!< PSSC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_OCIC_Pos        (19UL)         /*!< OCIC (Bit 19)                                         */
+ #define R_USBHC_HCRHPORTSTATUS1_OCIC_Msk        (0x80000UL)    /*!< OCIC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_PRSC_Pos        (20UL)         /*!< PRSC (Bit 20)                                         */
+ #define R_USBHC_HCRHPORTSTATUS1_PRSC_Msk        (0x100000UL)   /*!< PRSC (Bitfield-Mask: 0x01)                            */
+/* =====================================================  CAPL_VERSION  ====================================================== */
+ #define R_USBHC_CAPL_VERSION_CRL_Pos            (0UL)          /*!< CRL (Bit 0)                                           */
+ #define R_USBHC_CAPL_VERSION_CRL_Msk            (0xffUL)       /*!< CRL (Bitfield-Mask: 0xff)                             */
+ #define R_USBHC_CAPL_VERSION_HCIVN_Pos          (16UL)         /*!< HCIVN (Bit 16)                                        */
+ #define R_USBHC_CAPL_VERSION_HCIVN_Msk          (0xffff0000UL) /*!< HCIVN (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  HCSPARAMS  ======================================================= */
+ #define R_USBHC_HCSPARAMS_N_PORTS_Pos           (0UL)          /*!< N_PORTS (Bit 0)                                       */
+ #define R_USBHC_HCSPARAMS_N_PORTS_Msk           (0xfUL)        /*!< N_PORTS (Bitfield-Mask: 0x0f)                         */
+ #define R_USBHC_HCSPARAMS_PPC_Pos               (4UL)          /*!< PPC (Bit 4)                                           */
+ #define R_USBHC_HCSPARAMS_PPC_Msk               (0x10UL)       /*!< PPC (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCSPARAMS_PTRR_Pos              (7UL)          /*!< PTRR (Bit 7)                                          */
+ #define R_USBHC_HCSPARAMS_PTRR_Msk              (0x80UL)       /*!< PTRR (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCSPARAMS_N_PCC_Pos             (8UL)          /*!< N_PCC (Bit 8)                                         */
+ #define R_USBHC_HCSPARAMS_N_PCC_Msk             (0xf00UL)      /*!< N_PCC (Bitfield-Mask: 0x0f)                           */
+ #define R_USBHC_HCSPARAMS_N_CC_Pos              (12UL)         /*!< N_CC (Bit 12)                                         */
+ #define R_USBHC_HCSPARAMS_N_CC_Msk              (0xf000UL)     /*!< N_CC (Bitfield-Mask: 0x0f)                            */
+ #define R_USBHC_HCSPARAMS_P_INDICATOR_Pos       (16UL)         /*!< P_INDICATOR (Bit 16)                                  */
+ #define R_USBHC_HCSPARAMS_P_INDICATOR_Msk       (0x10000UL)    /*!< P_INDICATOR (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_HCSPARAMS_DBGPTNUM_Pos          (20UL)         /*!< DBGPTNUM (Bit 20)                                     */
+ #define R_USBHC_HCSPARAMS_DBGPTNUM_Msk          (0xf00000UL)   /*!< DBGPTNUM (Bitfield-Mask: 0x0f)                        */
+/* =======================================================  HCCPARAMS  ======================================================= */
+ #define R_USBHC_HCCPARAMS_AC64_Pos              (0UL)          /*!< AC64 (Bit 0)                                          */
+ #define R_USBHC_HCCPARAMS_AC64_Msk              (0x1UL)        /*!< AC64 (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_PFLF_Pos              (1UL)          /*!< PFLF (Bit 1)                                          */
+ #define R_USBHC_HCCPARAMS_PFLF_Msk              (0x2UL)        /*!< PFLF (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_ASPC_Pos              (2UL)          /*!< ASPC (Bit 2)                                          */
+ #define R_USBHC_HCCPARAMS_ASPC_Msk              (0x4UL)        /*!< ASPC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_IST_Pos               (4UL)          /*!< IST (Bit 4)                                           */
+ #define R_USBHC_HCCPARAMS_IST_Msk               (0xf0UL)       /*!< IST (Bitfield-Mask: 0x0f)                             */
+ #define R_USBHC_HCCPARAMS_EECP_Pos              (8UL)          /*!< EECP (Bit 8)                                          */
+ #define R_USBHC_HCCPARAMS_EECP_Msk              (0xff00UL)     /*!< EECP (Bitfield-Mask: 0xff)                            */
+ #define R_USBHC_HCCPARAMS_HP_Pos                (16UL)         /*!< HP (Bit 16)                                           */
+ #define R_USBHC_HCCPARAMS_HP_Msk                (0x10000UL)    /*!< HP (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCCPARAMS_LPMC_Pos              (17UL)         /*!< LPMC (Bit 17)                                         */
+ #define R_USBHC_HCCPARAMS_LPMC_Msk              (0x20000UL)    /*!< LPMC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_PCEC_Pos              (18UL)         /*!< PCEC (Bit 18)                                         */
+ #define R_USBHC_HCCPARAMS_PCEC_Msk              (0x40000UL)    /*!< PCEC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_PL32_Pos              (19UL)         /*!< PL32 (Bit 19)                                         */
+ #define R_USBHC_HCCPARAMS_PL32_Msk              (0x80000UL)    /*!< PL32 (Bitfield-Mask: 0x01)                            */
+/* ====================================================  HCSP_PORTROUTE  ===================================================== */
+/* ========================================================  USBCMD  ========================================================= */
+ #define R_USBHC_USBCMD_RS_Pos                   (0UL)          /*!< RS (Bit 0)                                            */
+ #define R_USBHC_USBCMD_RS_Msk                   (0x1UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_USBCMD_HCRESET_Pos              (1UL)          /*!< HCRESET (Bit 1)                                       */
+ #define R_USBHC_USBCMD_HCRESET_Msk              (0x2UL)        /*!< HCRESET (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_USBCMD_FLS_Pos                  (2UL)          /*!< FLS (Bit 2)                                           */
+ #define R_USBHC_USBCMD_FLS_Msk                  (0xcUL)        /*!< FLS (Bitfield-Mask: 0x03)                             */
+ #define R_USBHC_USBCMD_PSE_Pos                  (4UL)          /*!< PSE (Bit 4)                                           */
+ #define R_USBHC_USBCMD_PSE_Msk                  (0x10UL)       /*!< PSE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_USBCMD_ASYNSE_Pos               (5UL)          /*!< ASYNSE (Bit 5)                                        */
+ #define R_USBHC_USBCMD_ASYNSE_Msk               (0x20UL)       /*!< ASYNSE (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBCMD_IAAD_Pos                 (6UL)          /*!< IAAD (Bit 6)                                          */
+ #define R_USBHC_USBCMD_IAAD_Msk                 (0x40UL)       /*!< IAAD (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_USBCMD_LHCR_Pos                 (7UL)          /*!< LHCR (Bit 7)                                          */
+ #define R_USBHC_USBCMD_LHCR_Msk                 (0x80UL)       /*!< LHCR (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_USBCMD_ASPMC_Pos                (8UL)          /*!< ASPMC (Bit 8)                                         */
+ #define R_USBHC_USBCMD_ASPMC_Msk                (0x300UL)      /*!< ASPMC (Bitfield-Mask: 0x03)                           */
+ #define R_USBHC_USBCMD_ASPME_Pos                (11UL)         /*!< ASPME (Bit 11)                                        */
+ #define R_USBHC_USBCMD_ASPME_Msk                (0x800UL)      /*!< ASPME (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBCMD_PPCEE_Pos                (15UL)         /*!< PPCEE (Bit 15)                                        */
+ #define R_USBHC_USBCMD_PPCEE_Msk                (0x8000UL)     /*!< PPCEE (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBCMD_ITC_Pos                  (16UL)         /*!< ITC (Bit 16)                                          */
+ #define R_USBHC_USBCMD_ITC_Msk                  (0xff0000UL)   /*!< ITC (Bitfield-Mask: 0xff)                             */
+ #define R_USBHC_USBCMD_HIRD_Pos                 (24UL)         /*!< HIRD (Bit 24)                                         */
+ #define R_USBHC_USBCMD_HIRD_Msk                 (0xf000000UL)  /*!< HIRD (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  USBSTS  ========================================================= */
+ #define R_USBHC_USBSTS_USBINT_Pos               (0UL)          /*!< USBINT (Bit 0)                                        */
+ #define R_USBHC_USBSTS_USBINT_Msk               (0x1UL)        /*!< USBINT (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBSTS_USBERRINT_Pos            (1UL)          /*!< USBERRINT (Bit 1)                                     */
+ #define R_USBHC_USBSTS_USBERRINT_Msk            (0x2UL)        /*!< USBERRINT (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_USBSTS_PTCGDET_Pos              (2UL)          /*!< PTCGDET (Bit 2)                                       */
+ #define R_USBHC_USBSTS_PTCGDET_Msk              (0x4UL)        /*!< PTCGDET (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_USBSTS_FLROV_Pos                (3UL)          /*!< FLROV (Bit 3)                                         */
+ #define R_USBHC_USBSTS_FLROV_Msk                (0x8UL)        /*!< FLROV (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBSTS_HSYSE_Pos                (4UL)          /*!< HSYSE (Bit 4)                                         */
+ #define R_USBHC_USBSTS_HSYSE_Msk                (0x10UL)       /*!< HSYSE (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBSTS_IAAIS_Pos                (5UL)          /*!< IAAIS (Bit 5)                                         */
+ #define R_USBHC_USBSTS_IAAIS_Msk                (0x20UL)       /*!< IAAIS (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBSTS_EHCSTS_Pos               (12UL)         /*!< EHCSTS (Bit 12)                                       */
+ #define R_USBHC_USBSTS_EHCSTS_Msk               (0x1000UL)     /*!< EHCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBSTS_RECLAM_Pos               (13UL)         /*!< RECLAM (Bit 13)                                       */
+ #define R_USBHC_USBSTS_RECLAM_Msk               (0x2000UL)     /*!< RECLAM (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBSTS_PSCHSTS_Pos              (14UL)         /*!< PSCHSTS (Bit 14)                                      */
+ #define R_USBHC_USBSTS_PSCHSTS_Msk              (0x4000UL)     /*!< PSCHSTS (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_USBSTS_ASS_Pos                  (15UL)         /*!< ASS (Bit 15)                                          */
+ #define R_USBHC_USBSTS_ASS_Msk                  (0x8000UL)     /*!< ASS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_USBSTS_PTCGDETC_Pos             (16UL)         /*!< PTCGDETC (Bit 16)                                     */
+ #define R_USBHC_USBSTS_PTCGDETC_Msk             (0xffff0000UL) /*!< PTCGDETC (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  USBINTR  ======================================================== */
+ #define R_USBHC_USBINTR_USBIE_Pos               (0UL)          /*!< USBIE (Bit 0)                                         */
+ #define R_USBHC_USBINTR_USBIE_Msk               (0x1UL)        /*!< USBIE (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBINTR_USBEIE_Pos              (1UL)          /*!< USBEIE (Bit 1)                                        */
+ #define R_USBHC_USBINTR_USBEIE_Msk              (0x2UL)        /*!< USBEIE (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBINTR_PTCGIE_Pos              (2UL)          /*!< PTCGIE (Bit 2)                                        */
+ #define R_USBHC_USBINTR_PTCGIE_Msk              (0x4UL)        /*!< PTCGIE (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBINTR_FMLSTROE_Pos            (3UL)          /*!< FMLSTROE (Bit 3)                                      */
+ #define R_USBHC_USBINTR_FMLSTROE_Msk            (0x8UL)        /*!< FMLSTROE (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_USBINTR_HSEE_Pos                (4UL)          /*!< HSEE (Bit 4)                                          */
+ #define R_USBHC_USBINTR_HSEE_Msk                (0x10UL)       /*!< HSEE (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_USBINTR_INTAADVE_Pos            (5UL)          /*!< INTAADVE (Bit 5)                                      */
+ #define R_USBHC_USBINTR_INTAADVE_Msk            (0x20UL)       /*!< INTAADVE (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_USBINTR_PCGIE_Pos               (16UL)         /*!< PCGIE (Bit 16)                                        */
+ #define R_USBHC_USBINTR_PCGIE_Msk               (0xffff0000UL) /*!< PCGIE (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  FRINDEX  ======================================================== */
+ #define R_USBHC_FRINDEX_FRAMEINDEX_Pos          (0UL)          /*!< FRAMEINDEX (Bit 0)                                    */
+ #define R_USBHC_FRINDEX_FRAMEINDEX_Msk          (0x3fffUL)     /*!< FRAMEINDEX (Bitfield-Mask: 0x3fff)                    */
+/* =====================================================  CTRLDSSEGMENT  ===================================================== */
+/* ===================================================  PERIODICLISTBASE  ==================================================== */
+ #define R_USBHC_PERIODICLISTBASE_PFLSA_Pos      (12UL)         /*!< PFLSA (Bit 12)                                        */
+ #define R_USBHC_PERIODICLISTBASE_PFLSA_Msk      (0xfffff000UL) /*!< PFLSA (Bitfield-Mask: 0xfffff)                        */
+/* =====================================================  ASYNCLISTADDR  ===================================================== */
+ #define R_USBHC_ASYNCLISTADDR_LPL_Pos           (5UL)          /*!< LPL (Bit 5)                                           */
+ #define R_USBHC_ASYNCLISTADDR_LPL_Msk           (0xffffffe0UL) /*!< LPL (Bitfield-Mask: 0x7ffffff)                        */
+/* ======================================================  CONFIGFLAG  ======================================================= */
+ #define R_USBHC_CONFIGFLAG_CF_Pos               (0UL)          /*!< CF (Bit 0)                                            */
+ #define R_USBHC_CONFIGFLAG_CF_Msk               (0x1UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ========================================================  PORTSC1  ======================================================== */
+ #define R_USBHC_PORTSC1_CCSTS_Pos               (0UL)          /*!< CCSTS (Bit 0)                                         */
+ #define R_USBHC_PORTSC1_CCSTS_Msk               (0x1UL)        /*!< CCSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_PORTSC1_CSC_Pos                 (1UL)          /*!< CSC (Bit 1)                                           */
+ #define R_USBHC_PORTSC1_CSC_Msk                 (0x2UL)        /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_PORTSC1_PTE_Pos                 (2UL)          /*!< PTE (Bit 2)                                           */
+ #define R_USBHC_PORTSC1_PTE_Msk                 (0x4UL)        /*!< PTE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_PORTSC1_PTESC_Pos               (3UL)          /*!< PTESC (Bit 3)                                         */
+ #define R_USBHC_PORTSC1_PTESC_Msk               (0x8UL)        /*!< PTESC (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_PORTSC1_OVCACT_Pos              (4UL)          /*!< OVCACT (Bit 4)                                        */
+ #define R_USBHC_PORTSC1_OVCACT_Msk              (0x10UL)       /*!< OVCACT (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PORTSC1_OVCC_Pos                (5UL)          /*!< OVCC (Bit 5)                                          */
+ #define R_USBHC_PORTSC1_OVCC_Msk                (0x20UL)       /*!< OVCC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_PORTSC1_FRCPTRSM_Pos            (6UL)          /*!< FRCPTRSM (Bit 6)                                      */
+ #define R_USBHC_PORTSC1_FRCPTRSM_Msk            (0x40UL)       /*!< FRCPTRSM (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_PORTSC1_SUSPEND_Pos             (7UL)          /*!< SUSPEND (Bit 7)                                       */
+ #define R_USBHC_PORTSC1_SUSPEND_Msk             (0x80UL)       /*!< SUSPEND (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_PORTSC1_PTRST_Pos               (8UL)          /*!< PTRST (Bit 8)                                         */
+ #define R_USBHC_PORTSC1_PTRST_Msk               (0x100UL)      /*!< PTRST (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_PORTSC1_LPMCTL_Pos              (9UL)          /*!< LPMCTL (Bit 9)                                        */
+ #define R_USBHC_PORTSC1_LPMCTL_Msk              (0x200UL)      /*!< LPMCTL (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PORTSC1_LINESTS_Pos             (10UL)         /*!< LINESTS (Bit 10)                                      */
+ #define R_USBHC_PORTSC1_LINESTS_Msk             (0xc00UL)      /*!< LINESTS (Bitfield-Mask: 0x03)                         */
+ #define R_USBHC_PORTSC1_PP_Pos                  (12UL)         /*!< PP (Bit 12)                                           */
+ #define R_USBHC_PORTSC1_PP_Msk                  (0x1000UL)     /*!< PP (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_PORTSC1_PTOWNR_Pos              (13UL)         /*!< PTOWNR (Bit 13)                                       */
+ #define R_USBHC_PORTSC1_PTOWNR_Msk              (0x2000UL)     /*!< PTOWNR (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PORTSC1_PTINDCTL_Pos            (14UL)         /*!< PTINDCTL (Bit 14)                                     */
+ #define R_USBHC_PORTSC1_PTINDCTL_Msk            (0xc000UL)     /*!< PTINDCTL (Bitfield-Mask: 0x03)                        */
+ #define R_USBHC_PORTSC1_PTTST_Pos               (16UL)         /*!< PTTST (Bit 16)                                        */
+ #define R_USBHC_PORTSC1_PTTST_Msk               (0xf0000UL)    /*!< PTTST (Bitfield-Mask: 0x0f)                           */
+ #define R_USBHC_PORTSC1_WKCNNT_E_Pos            (20UL)         /*!< WKCNNT_E (Bit 20)                                     */
+ #define R_USBHC_PORTSC1_WKCNNT_E_Msk            (0x100000UL)   /*!< WKCNNT_E (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_PORTSC1_WKDSCNNT_E_Pos          (21UL)         /*!< WKDSCNNT_E (Bit 21)                                   */
+ #define R_USBHC_PORTSC1_WKDSCNNT_E_Msk          (0x200000UL)   /*!< WKDSCNNT_E (Bitfield-Mask: 0x01)                      */
+ #define R_USBHC_PORTSC1_WKOC_E_Pos              (22UL)         /*!< WKOC_E (Bit 22)                                       */
+ #define R_USBHC_PORTSC1_WKOC_E_Msk              (0x400000UL)   /*!< WKOC_E (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PORTSC1_SUSPSTS_Pos             (23UL)         /*!< SUSPSTS (Bit 23)                                      */
+ #define R_USBHC_PORTSC1_SUSPSTS_Msk             (0x1800000UL)  /*!< SUSPSTS (Bitfield-Mask: 0x03)                         */
+ #define R_USBHC_PORTSC1_DVADDR_Pos              (25UL)         /*!< DVADDR (Bit 25)                                       */
+ #define R_USBHC_PORTSC1_DVADDR_Msk              (0xfe000000UL) /*!< DVADDR (Bitfield-Mask: 0x7f)                          */
+/* =======================================================  INTENABLE  ======================================================= */
+ #define R_USBHC_INTENABLE_AHB_INTEN_Pos         (0UL)          /*!< AHB_INTEN (Bit 0)                                     */
+ #define R_USBHC_INTENABLE_AHB_INTEN_Msk         (0x1UL)        /*!< AHB_INTEN (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_INTENABLE_USBH_INTAEN_Pos       (1UL)          /*!< USBH_INTAEN (Bit 1)                                   */
+ #define R_USBHC_INTENABLE_USBH_INTAEN_Msk       (0x2UL)        /*!< USBH_INTAEN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_INTENABLE_USBH_INTBEN_Pos       (2UL)          /*!< USBH_INTBEN (Bit 2)                                   */
+ #define R_USBHC_INTENABLE_USBH_INTBEN_Msk       (0x4UL)        /*!< USBH_INTBEN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_INTENABLE_UCOM_INTEN_Pos        (3UL)          /*!< UCOM_INTEN (Bit 3)                                    */
+ #define R_USBHC_INTENABLE_UCOM_INTEN_Msk        (0x8UL)        /*!< UCOM_INTEN (Bitfield-Mask: 0x01)                      */
+ #define R_USBHC_INTENABLE_WAKEON_INTEN_Pos      (4UL)          /*!< WAKEON_INTEN (Bit 4)                                  */
+ #define R_USBHC_INTENABLE_WAKEON_INTEN_Msk      (0x10UL)       /*!< WAKEON_INTEN (Bitfield-Mask: 0x01)                    */
+/* =======================================================  INTSTATUS  ======================================================= */
+ #define R_USBHC_INTSTATUS_AHB_INT_Pos           (0UL)          /*!< AHB_INT (Bit 0)                                       */
+ #define R_USBHC_INTSTATUS_AHB_INT_Msk           (0x1UL)        /*!< AHB_INT (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_INTSTATUS_USBH_INTA_Pos         (1UL)          /*!< USBH_INTA (Bit 1)                                     */
+ #define R_USBHC_INTSTATUS_USBH_INTA_Msk         (0x2UL)        /*!< USBH_INTA (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_INTSTATUS_USBH_INTB_Pos         (2UL)          /*!< USBH_INTB (Bit 2)                                     */
+ #define R_USBHC_INTSTATUS_USBH_INTB_Msk         (0x4UL)        /*!< USBH_INTB (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_INTSTATUS_UCOM_INT_Pos          (3UL)          /*!< UCOM_INT (Bit 3)                                      */
+ #define R_USBHC_INTSTATUS_UCOM_INT_Msk          (0x8UL)        /*!< UCOM_INT (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_INTSTATUS_WAKEON_INT_Pos        (4UL)          /*!< WAKEON_INT (Bit 4)                                    */
+ #define R_USBHC_INTSTATUS_WAKEON_INT_Msk        (0x10UL)       /*!< WAKEON_INT (Bitfield-Mask: 0x01)                      */
+/* =======================================================  AHBBUSCTR  ======================================================= */
+ #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Pos     (0UL)          /*!< MAX_BURST_LEN (Bit 0)                                 */
+ #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Msk     (0x3UL)        /*!< MAX_BURST_LEN (Bitfield-Mask: 0x03)                   */
+ #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Pos     (4UL)          /*!< ALIGN_ADDRESS (Bit 4)                                 */
+ #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Msk     (0x30UL)       /*!< ALIGN_ADDRESS (Bitfield-Mask: 0x03)                   */
+ #define R_USBHC_AHBBUSCTR_PROT_MODE_Pos         (8UL)          /*!< PROT_MODE (Bit 8)                                     */
+ #define R_USBHC_AHBBUSCTR_PROT_MODE_Msk         (0x100UL)      /*!< PROT_MODE (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_AHBBUSCTR_PROT_TYPE_Pos         (12UL)         /*!< PROT_TYPE (Bit 12)                                    */
+ #define R_USBHC_AHBBUSCTR_PROT_TYPE_Msk         (0xf000UL)     /*!< PROT_TYPE (Bitfield-Mask: 0x0f)                       */
+/* ========================================================  USBCTR  ========================================================= */
+ #define R_USBHC_USBCTR_USBH_RST_Pos             (0UL)          /*!< USBH_RST (Bit 0)                                      */
+ #define R_USBHC_USBCTR_USBH_RST_Msk             (0x1UL)        /*!< USBH_RST (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_USBCTR_PLL_RST_Pos              (1UL)          /*!< PLL_RST (Bit 1)                                       */
+ #define R_USBHC_USBCTR_PLL_RST_Msk              (0x2UL)        /*!< PLL_RST (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_USBCTR_DIRPD_Pos                (2UL)          /*!< DIRPD (Bit 2)                                         */
+ #define R_USBHC_USBCTR_DIRPD_Msk                (0x4UL)        /*!< DIRPD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  REVID  ========================================================= */
+ #define R_USBHC_REVID_MINV_Pos                  (0UL)          /*!< MINV (Bit 0)                                          */
+ #define R_USBHC_REVID_MINV_Msk                  (0xffUL)       /*!< MINV (Bitfield-Mask: 0xff)                            */
+ #define R_USBHC_REVID_MAJV_Pos                  (8UL)          /*!< MAJV (Bit 8)                                          */
+ #define R_USBHC_REVID_MAJV_Msk                  (0xff00UL)     /*!< MAJV (Bitfield-Mask: 0xff)                            */
+ #define R_USBHC_REVID_COREID_Pos                (24UL)         /*!< COREID (Bit 24)                                       */
+ #define R_USBHC_REVID_COREID_Msk                (0xff000000UL) /*!< COREID (Bitfield-Mask: 0xff)                          */
+/* ======================================================  OCSLPTIMSET  ====================================================== */
+ #define R_USBHC_OCSLPTIMSET_TIMER_OC_Pos        (0UL)          /*!< TIMER_OC (Bit 0)                                      */
+ #define R_USBHC_OCSLPTIMSET_TIMER_OC_Msk        (0xfffffUL)    /*!< TIMER_OC (Bitfield-Mask: 0xfffff)                     */
+ #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Pos     (20UL)         /*!< TIMER_SLEEP (Bit 20)                                  */
+ #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Msk     (0x1ff00000UL) /*!< TIMER_SLEEP (Bitfield-Mask: 0x1ff)                    */
+/* =======================================================  COMMCTRL  ======================================================== */
+ #define R_USBHC_COMMCTRL_PERI_Pos               (31UL)         /*!< PERI (Bit 31)                                         */
+ #define R_USBHC_COMMCTRL_PERI_Msk               (0x80000000UL) /*!< PERI (Bitfield-Mask: 0x01)                            */
+/* =======================================================  OBINTSTA  ======================================================== */
+ #define R_USBHC_OBINTSTA_IDCHG_STA_Pos          (0UL)          /*!< IDCHG_STA (Bit 0)                                     */
+ #define R_USBHC_OBINTSTA_IDCHG_STA_Msk          (0x1UL)        /*!< IDCHG_STA (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_OBINTSTA_OCINT_STA_Pos          (1UL)          /*!< OCINT_STA (Bit 1)                                     */
+ #define R_USBHC_OBINTSTA_OCINT_STA_Msk          (0x2UL)        /*!< OCINT_STA (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_OBINTSTA_VBSTACHG_STA_Pos       (2UL)          /*!< VBSTACHG_STA (Bit 2)                                  */
+ #define R_USBHC_OBINTSTA_VBSTACHG_STA_Msk       (0x4UL)        /*!< VBSTACHG_STA (Bitfield-Mask: 0x01)                    */
+ #define R_USBHC_OBINTSTA_VBSTAINT_STA_Pos       (3UL)          /*!< VBSTAINT_STA (Bit 3)                                  */
+ #define R_USBHC_OBINTSTA_VBSTAINT_STA_Msk       (0x8UL)        /*!< VBSTAINT_STA (Bitfield-Mask: 0x01)                    */
+ #define R_USBHC_OBINTSTA_DMMONCHG_STA_Pos       (16UL)         /*!< DMMONCHG_STA (Bit 16)                                 */
+ #define R_USBHC_OBINTSTA_DMMONCHG_STA_Msk       (0x10000UL)    /*!< DMMONCHG_STA (Bitfield-Mask: 0x01)                    */
+ #define R_USBHC_OBINTSTA_DPMONCHG_STA_Pos       (17UL)         /*!< DPMONCHG_STA (Bit 17)                                 */
+ #define R_USBHC_OBINTSTA_DPMONCHG_STA_Msk       (0x20000UL)    /*!< DPMONCHG_STA (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OBINTEN  ======================================================== */
+ #define R_USBHC_OBINTEN_IDCHG_EN_Pos            (0UL)          /*!< IDCHG_EN (Bit 0)                                      */
+ #define R_USBHC_OBINTEN_IDCHG_EN_Msk            (0x1UL)        /*!< IDCHG_EN (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_OBINTEN_OCINT_EN_Pos            (1UL)          /*!< OCINT_EN (Bit 1)                                      */
+ #define R_USBHC_OBINTEN_OCINT_EN_Msk            (0x2UL)        /*!< OCINT_EN (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_OBINTEN_VBSTACHG_EN_Pos         (2UL)          /*!< VBSTACHG_EN (Bit 2)                                   */
+ #define R_USBHC_OBINTEN_VBSTACHG_EN_Msk         (0x4UL)        /*!< VBSTACHG_EN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_OBINTEN_VBSTAINT_EN_Pos         (3UL)          /*!< VBSTAINT_EN (Bit 3)                                   */
+ #define R_USBHC_OBINTEN_VBSTAINT_EN_Msk         (0x8UL)        /*!< VBSTAINT_EN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_OBINTEN_DMMONCHG_EN_Pos         (16UL)         /*!< DMMONCHG_EN (Bit 16)                                  */
+ #define R_USBHC_OBINTEN_DMMONCHG_EN_Msk         (0x10000UL)    /*!< DMMONCHG_EN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_OBINTEN_DPMONCHG_EN_Pos         (17UL)         /*!< DPMONCHG_EN (Bit 17)                                  */
+ #define R_USBHC_OBINTEN_DPMONCHG_EN_Msk         (0x20000UL)    /*!< DPMONCHG_EN (Bitfield-Mask: 0x01)                     */
+/* ========================================================  VBCTRL  ========================================================= */
+ #define R_USBHC_VBCTRL_VBOUT_Pos                (0UL)          /*!< VBOUT (Bit 0)                                         */
+ #define R_USBHC_VBCTRL_VBOUT_Msk                (0x1UL)        /*!< VBOUT (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_VBCTRL_VBUSENSEL_Pos            (1UL)          /*!< VBUSENSEL (Bit 1)                                     */
+ #define R_USBHC_VBCTRL_VBUSENSEL_Msk            (0x2UL)        /*!< VBUSENSEL (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_VBCTRL_VGPUO_Pos                (4UL)          /*!< VGPUO (Bit 4)                                         */
+ #define R_USBHC_VBCTRL_VGPUO_Msk                (0x10UL)       /*!< VGPUO (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_VBCTRL_OCCLRIEN_Pos             (16UL)         /*!< OCCLRIEN (Bit 16)                                     */
+ #define R_USBHC_VBCTRL_OCCLRIEN_Msk             (0x10000UL)    /*!< OCCLRIEN (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_VBCTRL_OCISEL_Pos               (17UL)         /*!< OCISEL (Bit 17)                                       */
+ #define R_USBHC_VBCTRL_OCISEL_Msk               (0x20000UL)    /*!< OCISEL (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_VBCTRL_VBLVL_Pos                (20UL)         /*!< VBLVL (Bit 20)                                        */
+ #define R_USBHC_VBCTRL_VBLVL_Msk                (0xf00000UL)   /*!< VBLVL (Bitfield-Mask: 0x0f)                           */
+ #define R_USBHC_VBCTRL_VBSTA_Pos                (28UL)         /*!< VBSTA (Bit 28)                                        */
+ #define R_USBHC_VBCTRL_VBSTA_Msk                (0xf0000000UL) /*!< VBSTA (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  LINECTRL1  ======================================================= */
+ #define R_USBHC_LINECTRL1_IDMON_Pos             (0UL)          /*!< IDMON (Bit 0)                                         */
+ #define R_USBHC_LINECTRL1_IDMON_Msk             (0x1UL)        /*!< IDMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_LINECTRL1_DMMON_Pos             (2UL)          /*!< DMMON (Bit 2)                                         */
+ #define R_USBHC_LINECTRL1_DMMON_Msk             (0x4UL)        /*!< DMMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_LINECTRL1_DPMON_Pos             (3UL)          /*!< DPMON (Bit 3)                                         */
+ #define R_USBHC_LINECTRL1_DPMON_Msk             (0x8UL)        /*!< DPMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_LINECTRL1_DM_RPD_Pos            (16UL)         /*!< DM_RPD (Bit 16)                                       */
+ #define R_USBHC_LINECTRL1_DM_RPD_Msk            (0x10000UL)    /*!< DM_RPD (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_LINECTRL1_DMRPD_EN_Pos          (17UL)         /*!< DMRPD_EN (Bit 17)                                     */
+ #define R_USBHC_LINECTRL1_DMRPD_EN_Msk          (0x20000UL)    /*!< DMRPD_EN (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_LINECTRL1_DP_RPD_Pos            (18UL)         /*!< DP_RPD (Bit 18)                                       */
+ #define R_USBHC_LINECTRL1_DP_RPD_Msk            (0x40000UL)    /*!< DP_RPD (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_LINECTRL1_DPRPD_EN_Pos          (19UL)         /*!< DPRPD_EN (Bit 19)                                     */
+ #define R_USBHC_LINECTRL1_DPRPD_EN_Msk          (0x80000UL)    /*!< DPRPD_EN (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USBF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SYSCFG0  ======================================================== */
+ #define R_USBF_SYSCFG0_USBE_Pos            (0UL)          /*!< USBE (Bit 0)                                          */
+ #define R_USBF_SYSCFG0_USBE_Msk            (0x1UL)        /*!< USBE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_SYSCFG0_DPRPU_Pos           (4UL)          /*!< DPRPU (Bit 4)                                         */
+ #define R_USBF_SYSCFG0_DPRPU_Msk           (0x10UL)       /*!< DPRPU (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_SYSCFG0_DRPD_Pos            (5UL)          /*!< DRPD (Bit 5)                                          */
+ #define R_USBF_SYSCFG0_DRPD_Msk            (0x20UL)       /*!< DRPD (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_SYSCFG0_HSE_Pos             (7UL)          /*!< HSE (Bit 7)                                           */
+ #define R_USBF_SYSCFG0_HSE_Msk             (0x80UL)       /*!< HSE (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_SYSCFG0_CNEN_Pos            (8UL)          /*!< CNEN (Bit 8)                                          */
+ #define R_USBF_SYSCFG0_CNEN_Msk            (0x100UL)      /*!< CNEN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SYSCFG1  ======================================================== */
+ #define R_USBF_SYSCFG1_BWAIT_Pos           (0UL)          /*!< BWAIT (Bit 0)                                         */
+ #define R_USBF_SYSCFG1_BWAIT_Msk           (0x3fUL)       /*!< BWAIT (Bitfield-Mask: 0x3f)                           */
+ #define R_USBF_SYSCFG1_AWAIT_Pos           (8UL)          /*!< AWAIT (Bit 8)                                         */
+ #define R_USBF_SYSCFG1_AWAIT_Msk           (0x3f00UL)     /*!< AWAIT (Bitfield-Mask: 0x3f)                           */
+/* ========================================================  SYSSTS0  ======================================================== */
+ #define R_USBF_SYSSTS0_LNST_Pos            (0UL)          /*!< LNST (Bit 0)                                          */
+ #define R_USBF_SYSSTS0_LNST_Msk            (0x3UL)        /*!< LNST (Bitfield-Mask: 0x03)                            */
+/* =======================================================  DVSTCTR0  ======================================================== */
+ #define R_USBF_DVSTCTR0_RHST_Pos           (0UL)          /*!< RHST (Bit 0)                                          */
+ #define R_USBF_DVSTCTR0_RHST_Msk           (0x7UL)        /*!< RHST (Bitfield-Mask: 0x07)                            */
+ #define R_USBF_DVSTCTR0_WKUP_Pos           (8UL)          /*!< WKUP (Bit 8)                                          */
+ #define R_USBF_DVSTCTR0_WKUP_Msk           (0x100UL)      /*!< WKUP (Bitfield-Mask: 0x01)                            */
+/* =======================================================  TESTMODE  ======================================================== */
+ #define R_USBF_TESTMODE_UTST_Pos           (0UL)          /*!< UTST (Bit 0)                                          */
+ #define R_USBF_TESTMODE_UTST_Msk           (0xfUL)        /*!< UTST (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  CFIFO  ========================================================= */
+ #define R_USBF_CFIFO_FIFOPORT_Pos          (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_CFIFO_FIFOPORT_Msk          (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  CFIFOL  ========================================================= */
+/* ========================================================  CFIFOLL  ======================================================== */
+/* ========================================================  CFIFOH  ========================================================= */
+ #define R_USBF_CFIFOH_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_CFIFOH_FIFOPORT_Msk         (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  CFIFOHH  ======================================================== */
+ #define R_USBF_CFIFOHH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_CFIFOHH_FIFOPORT_Msk        (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
+/* ========================================================  D0FIFO  ========================================================= */
+ #define R_USBF_D0FIFO_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D0FIFO_FIFOPORT_Msk         (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  D0FIFOL  ======================================================== */
+/* =======================================================  D0FIFOLL  ======================================================== */
+/* ========================================================  D0FIFOH  ======================================================== */
+ #define R_USBF_D0FIFOH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D0FIFOH_FIFOPORT_Msk        (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  D0FIFOHH  ======================================================== */
+ #define R_USBF_D0FIFOHH_FIFOPORT_Pos       (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D0FIFOHH_FIFOPORT_Msk       (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
+/* ========================================================  D1FIFO  ========================================================= */
+ #define R_USBF_D1FIFO_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D1FIFO_FIFOPORT_Msk         (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  D1FIFOL  ======================================================== */
+/* =======================================================  D1FIFOLL  ======================================================== */
+/* ========================================================  D1FIFOH  ======================================================== */
+ #define R_USBF_D1FIFOH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D1FIFOH_FIFOPORT_Msk        (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  D1FIFOHH  ======================================================== */
+ #define R_USBF_D1FIFOHH_FIFOPORT_Pos       (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D1FIFOHH_FIFOPORT_Msk       (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
+/* =======================================================  CFIFOSEL  ======================================================== */
+ #define R_USBF_CFIFOSEL_CURPIPE_Pos        (0UL)          /*!< CURPIPE (Bit 0)                                       */
+ #define R_USBF_CFIFOSEL_CURPIPE_Msk        (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+ #define R_USBF_CFIFOSEL_ISEL_Pos           (5UL)          /*!< ISEL (Bit 5)                                          */
+ #define R_USBF_CFIFOSEL_ISEL_Msk           (0x20UL)       /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CFIFOSEL_BIGEND_Pos         (8UL)          /*!< BIGEND (Bit 8)                                        */
+ #define R_USBF_CFIFOSEL_BIGEND_Msk         (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CFIFOSEL_MBW_Pos            (10UL)         /*!< MBW (Bit 10)                                          */
+ #define R_USBF_CFIFOSEL_MBW_Msk            (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_CFIFOSEL_REW_Pos            (14UL)         /*!< REW (Bit 14)                                          */
+ #define R_USBF_CFIFOSEL_REW_Msk            (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CFIFOSEL_RCNT_Pos           (15UL)         /*!< RCNT (Bit 15)                                         */
+ #define R_USBF_CFIFOSEL_RCNT_Msk           (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFIFOCTR  ======================================================== */
+ #define R_USBF_CFIFOCTR_DTLN_Pos           (0UL)          /*!< DTLN (Bit 0)                                          */
+ #define R_USBF_CFIFOCTR_DTLN_Msk           (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+ #define R_USBF_CFIFOCTR_FRDY_Pos           (13UL)         /*!< FRDY (Bit 13)                                         */
+ #define R_USBF_CFIFOCTR_FRDY_Msk           (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CFIFOCTR_BCLR_Pos           (14UL)         /*!< BCLR (Bit 14)                                         */
+ #define R_USBF_CFIFOCTR_BCLR_Msk           (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CFIFOCTR_BVAL_Pos           (15UL)         /*!< BVAL (Bit 15)                                         */
+ #define R_USBF_CFIFOCTR_BVAL_Msk           (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
+/* =======================================================  D0FIFOSEL  ======================================================= */
+ #define R_USBF_D0FIFOSEL_CURPIPE_Pos       (0UL)          /*!< CURPIPE (Bit 0)                                       */
+ #define R_USBF_D0FIFOSEL_CURPIPE_Msk       (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+ #define R_USBF_D0FIFOSEL_BIGEND_Pos        (8UL)          /*!< BIGEND (Bit 8)                                        */
+ #define R_USBF_D0FIFOSEL_BIGEND_Msk        (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_D0FIFOSEL_MBW_Pos           (10UL)         /*!< MBW (Bit 10)                                          */
+ #define R_USBF_D0FIFOSEL_MBW_Msk           (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_D0FIFOSEL_DREQE_Pos         (12UL)         /*!< DREQE (Bit 12)                                        */
+ #define R_USBF_D0FIFOSEL_DREQE_Msk         (0x1000UL)     /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_D0FIFOSEL_DCLRM_Pos         (13UL)         /*!< DCLRM (Bit 13)                                        */
+ #define R_USBF_D0FIFOSEL_DCLRM_Msk         (0x2000UL)     /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_D0FIFOSEL_REW_Pos           (14UL)         /*!< REW (Bit 14)                                          */
+ #define R_USBF_D0FIFOSEL_REW_Msk           (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_D0FIFOSEL_RCNT_Pos          (15UL)         /*!< RCNT (Bit 15)                                         */
+ #define R_USBF_D0FIFOSEL_RCNT_Msk          (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  D1FIFOSEL  ======================================================= */
+ #define R_USBF_D1FIFOSEL_CURPIPE_Pos       (0UL)          /*!< CURPIPE (Bit 0)                                       */
+ #define R_USBF_D1FIFOSEL_CURPIPE_Msk       (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+ #define R_USBF_D1FIFOSEL_BIGEND_Pos        (8UL)          /*!< BIGEND (Bit 8)                                        */
+ #define R_USBF_D1FIFOSEL_BIGEND_Msk        (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_D1FIFOSEL_MBW_Pos           (10UL)         /*!< MBW (Bit 10)                                          */
+ #define R_USBF_D1FIFOSEL_MBW_Msk           (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_D1FIFOSEL_DREQE_Pos         (12UL)         /*!< DREQE (Bit 12)                                        */
+ #define R_USBF_D1FIFOSEL_DREQE_Msk         (0x1000UL)     /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_D1FIFOSEL_DCLRM_Pos         (13UL)         /*!< DCLRM (Bit 13)                                        */
+ #define R_USBF_D1FIFOSEL_DCLRM_Msk         (0x2000UL)     /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_D1FIFOSEL_REW_Pos           (14UL)         /*!< REW (Bit 14)                                          */
+ #define R_USBF_D1FIFOSEL_REW_Msk           (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_D1FIFOSEL_RCNT_Pos          (15UL)         /*!< RCNT (Bit 15)                                         */
+ #define R_USBF_D1FIFOSEL_RCNT_Msk          (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  D0FIFOCTR  ======================================================= */
+ #define R_USBF_D0FIFOCTR_DTLN_Pos          (0UL)          /*!< DTLN (Bit 0)                                          */
+ #define R_USBF_D0FIFOCTR_DTLN_Msk          (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+ #define R_USBF_D0FIFOCTR_FRDY_Pos          (13UL)         /*!< FRDY (Bit 13)                                         */
+ #define R_USBF_D0FIFOCTR_FRDY_Msk          (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_D0FIFOCTR_BCLR_Pos          (14UL)         /*!< BCLR (Bit 14)                                         */
+ #define R_USBF_D0FIFOCTR_BCLR_Msk          (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_D0FIFOCTR_BVAL_Pos          (15UL)         /*!< BVAL (Bit 15)                                         */
+ #define R_USBF_D0FIFOCTR_BVAL_Msk          (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
+/* =======================================================  D1FIFOCTR  ======================================================= */
+ #define R_USBF_D1FIFOCTR_DTLN_Pos          (0UL)          /*!< DTLN (Bit 0)                                          */
+ #define R_USBF_D1FIFOCTR_DTLN_Msk          (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+ #define R_USBF_D1FIFOCTR_FRDY_Pos          (13UL)         /*!< FRDY (Bit 13)                                         */
+ #define R_USBF_D1FIFOCTR_FRDY_Msk          (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_D1FIFOCTR_BCLR_Pos          (14UL)         /*!< BCLR (Bit 14)                                         */
+ #define R_USBF_D1FIFOCTR_BCLR_Msk          (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_D1FIFOCTR_BVAL_Pos          (15UL)         /*!< BVAL (Bit 15)                                         */
+ #define R_USBF_D1FIFOCTR_BVAL_Msk          (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
+/* ========================================================  INTENB0  ======================================================== */
+ #define R_USBF_INTENB0_BRDYE_Pos           (8UL)          /*!< BRDYE (Bit 8)                                         */
+ #define R_USBF_INTENB0_BRDYE_Msk           (0x100UL)      /*!< BRDYE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTENB0_NRDYE_Pos           (9UL)          /*!< NRDYE (Bit 9)                                         */
+ #define R_USBF_INTENB0_NRDYE_Msk           (0x200UL)      /*!< NRDYE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTENB0_BEMPE_Pos           (10UL)         /*!< BEMPE (Bit 10)                                        */
+ #define R_USBF_INTENB0_BEMPE_Msk           (0x400UL)      /*!< BEMPE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTENB0_CTRE_Pos            (11UL)         /*!< CTRE (Bit 11)                                         */
+ #define R_USBF_INTENB0_CTRE_Msk            (0x800UL)      /*!< CTRE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTENB0_DVSE_Pos            (12UL)         /*!< DVSE (Bit 12)                                         */
+ #define R_USBF_INTENB0_DVSE_Msk            (0x1000UL)     /*!< DVSE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTENB0_SOFE_Pos            (13UL)         /*!< SOFE (Bit 13)                                         */
+ #define R_USBF_INTENB0_SOFE_Msk            (0x2000UL)     /*!< SOFE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTENB0_RSME_Pos            (14UL)         /*!< RSME (Bit 14)                                         */
+ #define R_USBF_INTENB0_RSME_Msk            (0x4000UL)     /*!< RSME (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTENB0_VBSE_Pos            (15UL)         /*!< VBSE (Bit 15)                                         */
+ #define R_USBF_INTENB0_VBSE_Msk            (0x8000UL)     /*!< VBSE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  INTENB1  ======================================================== */
+ #define R_USBF_INTENB1_PDDETINTE_Pos       (0UL)          /*!< PDDETINTE (Bit 0)                                     */
+ #define R_USBF_INTENB1_PDDETINTE_Msk       (0x1UL)        /*!< PDDETINTE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  BRDYENB  ======================================================== */
+ #define R_USBF_BRDYENB_PIPEBRDYE_Pos       (0UL)          /*!< PIPEBRDYE (Bit 0)                                     */
+ #define R_USBF_BRDYENB_PIPEBRDYE_Msk       (0x3ffUL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff)                      */
+/* ========================================================  NRDYENB  ======================================================== */
+ #define R_USBF_NRDYENB_PIPENRDYE_Pos       (0UL)          /*!< PIPENRDYE (Bit 0)                                     */
+ #define R_USBF_NRDYENB_PIPENRDYE_Msk       (0x3ffUL)      /*!< PIPENRDYE (Bitfield-Mask: 0x3ff)                      */
+/* ========================================================  BEMPENB  ======================================================== */
+ #define R_USBF_BEMPENB_PIPEBEMPE_Pos       (0UL)          /*!< PIPEBEMPE (Bit 0)                                     */
+ #define R_USBF_BEMPENB_PIPEBEMPE_Msk       (0x3ffUL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff)                      */
+/* ========================================================  SOFCFG  ========================================================= */
+ #define R_USBF_SOFCFG_EDGESTS_Pos          (4UL)          /*!< EDGESTS (Bit 4)                                       */
+ #define R_USBF_SOFCFG_EDGESTS_Msk          (0x10UL)       /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
+ #define R_USBF_SOFCFG_INTL_Pos             (5UL)          /*!< INTL (Bit 5)                                          */
+ #define R_USBF_SOFCFG_INTL_Msk             (0x20UL)       /*!< INTL (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_SOFCFG_BRDYM_Pos            (6UL)          /*!< BRDYM (Bit 6)                                         */
+ #define R_USBF_SOFCFG_BRDYM_Msk            (0x40UL)       /*!< BRDYM (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTSTS0  ======================================================== */
+ #define R_USBF_INTSTS0_CTSQ_Pos            (0UL)          /*!< CTSQ (Bit 0)                                          */
+ #define R_USBF_INTSTS0_CTSQ_Msk            (0x7UL)        /*!< CTSQ (Bitfield-Mask: 0x07)                            */
+ #define R_USBF_INTSTS0_VALID_Pos           (3UL)          /*!< VALID (Bit 3)                                         */
+ #define R_USBF_INTSTS0_VALID_Msk           (0x8UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTSTS0_DVSQ_Pos            (4UL)          /*!< DVSQ (Bit 4)                                          */
+ #define R_USBF_INTSTS0_DVSQ_Msk            (0x70UL)       /*!< DVSQ (Bitfield-Mask: 0x07)                            */
+ #define R_USBF_INTSTS0_VBSTS_Pos           (7UL)          /*!< VBSTS (Bit 7)                                         */
+ #define R_USBF_INTSTS0_VBSTS_Msk           (0x80UL)       /*!< VBSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTSTS0_BRDY_Pos            (8UL)          /*!< BRDY (Bit 8)                                          */
+ #define R_USBF_INTSTS0_BRDY_Msk            (0x100UL)      /*!< BRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_NRDY_Pos            (9UL)          /*!< NRDY (Bit 9)                                          */
+ #define R_USBF_INTSTS0_NRDY_Msk            (0x200UL)      /*!< NRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_BEMP_Pos            (10UL)         /*!< BEMP (Bit 10)                                         */
+ #define R_USBF_INTSTS0_BEMP_Msk            (0x400UL)      /*!< BEMP (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_CTRT_Pos            (11UL)         /*!< CTRT (Bit 11)                                         */
+ #define R_USBF_INTSTS0_CTRT_Msk            (0x800UL)      /*!< CTRT (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_DVST_Pos            (12UL)         /*!< DVST (Bit 12)                                         */
+ #define R_USBF_INTSTS0_DVST_Msk            (0x1000UL)     /*!< DVST (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_SOFR_Pos            (13UL)         /*!< SOFR (Bit 13)                                         */
+ #define R_USBF_INTSTS0_SOFR_Msk            (0x2000UL)     /*!< SOFR (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_RESM_Pos            (14UL)         /*!< RESM (Bit 14)                                         */
+ #define R_USBF_INTSTS0_RESM_Msk            (0x4000UL)     /*!< RESM (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_VBINT_Pos           (15UL)         /*!< VBINT (Bit 15)                                        */
+ #define R_USBF_INTSTS0_VBINT_Msk           (0x8000UL)     /*!< VBINT (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTSTS1  ======================================================== */
+ #define R_USBF_INTSTS1_PDDETINT_Pos        (0UL)          /*!< PDDETINT (Bit 0)                                      */
+ #define R_USBF_INTSTS1_PDDETINT_Msk        (0x1UL)        /*!< PDDETINT (Bitfield-Mask: 0x01)                        */
+/* ========================================================  BRDYSTS  ======================================================== */
+ #define R_USBF_BRDYSTS_PIPEBRDY_Pos        (0UL)          /*!< PIPEBRDY (Bit 0)                                      */
+ #define R_USBF_BRDYSTS_PIPEBRDY_Msk        (0x3ffUL)      /*!< PIPEBRDY (Bitfield-Mask: 0x3ff)                       */
+/* ========================================================  NRDYSTS  ======================================================== */
+ #define R_USBF_NRDYSTS_PIPENRDY_Pos        (0UL)          /*!< PIPENRDY (Bit 0)                                      */
+ #define R_USBF_NRDYSTS_PIPENRDY_Msk        (0x3ffUL)      /*!< PIPENRDY (Bitfield-Mask: 0x3ff)                       */
+/* ========================================================  BEMPSTS  ======================================================== */
+ #define R_USBF_BEMPSTS_PIPEBEMP_Pos        (0UL)          /*!< PIPEBEMP (Bit 0)                                      */
+ #define R_USBF_BEMPSTS_PIPEBEMP_Msk        (0x3ffUL)      /*!< PIPEBEMP (Bitfield-Mask: 0x3ff)                       */
+/* ========================================================  FRMNUM  ========================================================= */
+ #define R_USBF_FRMNUM_FRNM_Pos             (0UL)          /*!< FRNM (Bit 0)                                          */
+ #define R_USBF_FRMNUM_FRNM_Msk             (0x7ffUL)      /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
+ #define R_USBF_FRMNUM_CRCE_Pos             (14UL)         /*!< CRCE (Bit 14)                                         */
+ #define R_USBF_FRMNUM_CRCE_Msk             (0x4000UL)     /*!< CRCE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_FRMNUM_OVRN_Pos             (15UL)         /*!< OVRN (Bit 15)                                         */
+ #define R_USBF_FRMNUM_OVRN_Msk             (0x8000UL)     /*!< OVRN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  UFRMNUM  ======================================================== */
+ #define R_USBF_UFRMNUM_UFRNM_Pos           (0UL)          /*!< UFRNM (Bit 0)                                         */
+ #define R_USBF_UFRMNUM_UFRNM_Msk           (0x7UL)        /*!< UFRNM (Bitfield-Mask: 0x07)                           */
+/* ========================================================  USBADDR  ======================================================== */
+ #define R_USBF_USBADDR_USBADDR_Pos         (0UL)          /*!< USBADDR (Bit 0)                                       */
+ #define R_USBF_USBADDR_USBADDR_Msk         (0x7fUL)       /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
+/* ========================================================  USBREQ  ========================================================= */
+ #define R_USBF_USBREQ_BMREQUESTTYPE_Pos    (0UL)          /*!< BMREQUESTTYPE (Bit 0)                                 */
+ #define R_USBF_USBREQ_BMREQUESTTYPE_Msk    (0xffUL)       /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
+ #define R_USBF_USBREQ_BREQUEST_Pos         (8UL)          /*!< BREQUEST (Bit 8)                                      */
+ #define R_USBF_USBREQ_BREQUEST_Msk         (0xff00UL)     /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
+/* ========================================================  USBVAL  ========================================================= */
+ #define R_USBF_USBVAL_WVALUE_Pos           (0UL)          /*!< WVALUE (Bit 0)                                        */
+ #define R_USBF_USBVAL_WVALUE_Msk           (0xffffUL)     /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBINDX  ======================================================== */
+ #define R_USBF_USBINDX_WINDEX_Pos          (0UL)          /*!< WINDEX (Bit 0)                                        */
+ #define R_USBF_USBINDX_WINDEX_Msk          (0xffffUL)     /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBLENG  ======================================================== */
+ #define R_USBF_USBLENG_WLENGTH_Pos         (0UL)          /*!< WLENGTH (Bit 0)                                       */
+ #define R_USBF_USBLENG_WLENGTH_Msk         (0xffffUL)     /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  DCPCFG  ========================================================= */
+ #define R_USBF_DCPCFG_SHTNAK_Pos           (7UL)          /*!< SHTNAK (Bit 7)                                        */
+ #define R_USBF_DCPCFG_SHTNAK_Msk           (0x80UL)       /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_DCPCFG_CNTMD_Pos            (8UL)          /*!< CNTMD (Bit 8)                                         */
+ #define R_USBF_DCPCFG_CNTMD_Msk            (0x100UL)      /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DCPMAXP  ======================================================== */
+ #define R_USBF_DCPMAXP_MXPS_Pos            (0UL)          /*!< MXPS (Bit 0)                                          */
+ #define R_USBF_DCPMAXP_MXPS_Msk            (0x7fUL)       /*!< MXPS (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  DCPCTR  ========================================================= */
+ #define R_USBF_DCPCTR_PID_Pos              (0UL)          /*!< PID (Bit 0)                                           */
+ #define R_USBF_DCPCTR_PID_Msk              (0x3UL)        /*!< PID (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_DCPCTR_CCPL_Pos             (2UL)          /*!< CCPL (Bit 2)                                          */
+ #define R_USBF_DCPCTR_CCPL_Msk             (0x4UL)        /*!< CCPL (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_DCPCTR_PBUSY_Pos            (5UL)          /*!< PBUSY (Bit 5)                                         */
+ #define R_USBF_DCPCTR_PBUSY_Msk            (0x20UL)       /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_DCPCTR_SQMON_Pos            (6UL)          /*!< SQMON (Bit 6)                                         */
+ #define R_USBF_DCPCTR_SQMON_Msk            (0x40UL)       /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_DCPCTR_SQSET_Pos            (7UL)          /*!< SQSET (Bit 7)                                         */
+ #define R_USBF_DCPCTR_SQSET_Msk            (0x80UL)       /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_DCPCTR_SQCLR_Pos            (8UL)          /*!< SQCLR (Bit 8)                                         */
+ #define R_USBF_DCPCTR_SQCLR_Msk            (0x100UL)      /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_DCPCTR_BSTS_Pos             (15UL)         /*!< BSTS (Bit 15)                                         */
+ #define R_USBF_DCPCTR_BSTS_Msk             (0x8000UL)     /*!< BSTS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PIPESEL  ======================================================== */
+ #define R_USBF_PIPESEL_PIPESEL_Pos         (0UL)          /*!< PIPESEL (Bit 0)                                       */
+ #define R_USBF_PIPESEL_PIPESEL_Msk         (0xfUL)        /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
+/* ========================================================  PIPECFG  ======================================================== */
+ #define R_USBF_PIPECFG_EPNUM_Pos           (0UL)          /*!< EPNUM (Bit 0)                                         */
+ #define R_USBF_PIPECFG_EPNUM_Msk           (0xfUL)        /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
+ #define R_USBF_PIPECFG_DIR_Pos             (4UL)          /*!< DIR (Bit 4)                                           */
+ #define R_USBF_PIPECFG_DIR_Msk             (0x10UL)       /*!< DIR (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_PIPECFG_SHTNAK_Pos          (7UL)          /*!< SHTNAK (Bit 7)                                        */
+ #define R_USBF_PIPECFG_SHTNAK_Msk          (0x80UL)       /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_PIPECFG_CNTMD_Pos           (8UL)          /*!< CNTMD (Bit 8)                                         */
+ #define R_USBF_PIPECFG_CNTMD_Msk           (0x100UL)      /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPECFG_DBLB_Pos            (9UL)          /*!< DBLB (Bit 9)                                          */
+ #define R_USBF_PIPECFG_DBLB_Msk            (0x200UL)      /*!< DBLB (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_PIPECFG_BFRE_Pos            (10UL)         /*!< BFRE (Bit 10)                                         */
+ #define R_USBF_PIPECFG_BFRE_Msk            (0x400UL)      /*!< BFRE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_PIPECFG_TYPE_Pos            (14UL)         /*!< TYPE (Bit 14)                                         */
+ #define R_USBF_PIPECFG_TYPE_Msk            (0xc000UL)     /*!< TYPE (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PIPEBUF  ======================================================== */
+ #define R_USBF_PIPEBUF_BUFNMB_Pos          (0UL)          /*!< BUFNMB (Bit 0)                                        */
+ #define R_USBF_PIPEBUF_BUFNMB_Msk          (0xffUL)       /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
+ #define R_USBF_PIPEBUF_BUFSIZE_Pos         (10UL)         /*!< BUFSIZE (Bit 10)                                      */
+ #define R_USBF_PIPEBUF_BUFSIZE_Msk         (0x7c00UL)     /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  PIPEMAXP  ======================================================== */
+ #define R_USBF_PIPEMAXP_MXPS_Pos           (0UL)          /*!< MXPS (Bit 0)                                          */
+ #define R_USBF_PIPEMAXP_MXPS_Msk           (0x7ffUL)      /*!< MXPS (Bitfield-Mask: 0x7ff)                           */
+/* =======================================================  PIPEPERI  ======================================================== */
+ #define R_USBF_PIPEPERI_IITV_Pos           (0UL)          /*!< IITV (Bit 0)                                          */
+ #define R_USBF_PIPEPERI_IITV_Msk           (0x7UL)        /*!< IITV (Bitfield-Mask: 0x07)                            */
+ #define R_USBF_PIPEPERI_IFIS_Pos           (12UL)         /*!< IFIS (Bit 12)                                         */
+ #define R_USBF_PIPEPERI_IFIS_Msk           (0x1000UL)     /*!< IFIS (Bitfield-Mask: 0x01)                            */
+/* =======================================================  PIPE_CTR  ======================================================== */
+ #define R_USBF_PIPE_CTR_PID_Pos            (0UL)          /*!< PID (Bit 0)                                           */
+ #define R_USBF_PIPE_CTR_PID_Msk            (0x3UL)        /*!< PID (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_PIPE_CTR_PBUSY_Pos          (5UL)          /*!< PBUSY (Bit 5)                                         */
+ #define R_USBF_PIPE_CTR_PBUSY_Msk          (0x20UL)       /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_SQMON_Pos          (6UL)          /*!< SQMON (Bit 6)                                         */
+ #define R_USBF_PIPE_CTR_SQMON_Msk          (0x40UL)       /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_SQSET_Pos          (7UL)          /*!< SQSET (Bit 7)                                         */
+ #define R_USBF_PIPE_CTR_SQSET_Msk          (0x80UL)       /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_SQCLR_Pos          (8UL)          /*!< SQCLR (Bit 8)                                         */
+ #define R_USBF_PIPE_CTR_SQCLR_Msk          (0x100UL)      /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_ACLRM_Pos          (9UL)          /*!< ACLRM (Bit 9)                                         */
+ #define R_USBF_PIPE_CTR_ACLRM_Msk          (0x200UL)      /*!< ACLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_ATREPM_Pos         (10UL)         /*!< ATREPM (Bit 10)                                       */
+ #define R_USBF_PIPE_CTR_ATREPM_Msk         (0x400UL)      /*!< ATREPM (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_PIPE_CTR_INBUFM_Pos         (14UL)         /*!< INBUFM (Bit 14)                                       */
+ #define R_USBF_PIPE_CTR_INBUFM_Msk         (0x4000UL)     /*!< INBUFM (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_PIPE_CTR_BSTS_Pos           (15UL)         /*!< BSTS (Bit 15)                                         */
+ #define R_USBF_PIPE_CTR_BSTS_Msk           (0x8000UL)     /*!< BSTS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  LPSTS  ========================================================= */
+ #define R_USBF_LPSTS_SUSPM_Pos             (14UL)         /*!< SUSPM (Bit 14)                                        */
+ #define R_USBF_LPSTS_SUSPM_Msk             (0x4000UL)     /*!< SUSPM (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DCTRL  ========================================================= */
+ #define R_USBF_DCTRL_PR_Pos                (0UL)          /*!< PR (Bit 0)                                            */
+ #define R_USBF_DCTRL_PR_Msk                (0x1UL)        /*!< PR (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_DCTRL_LDPR_Pos              (16UL)         /*!< LDPR (Bit 16)                                         */
+ #define R_USBF_DCTRL_LDPR_Msk              (0xf0000UL)    /*!< LDPR (Bitfield-Mask: 0x0f)                            */
+ #define R_USBF_DCTRL_LWPR_Pos              (24UL)         /*!< LWPR (Bit 24)                                         */
+ #define R_USBF_DCTRL_LWPR_Msk              (0xf000000UL)  /*!< LWPR (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  DSCITVL  ======================================================== */
+ #define R_USBF_DSCITVL_DITVL_Pos           (8UL)          /*!< DITVL (Bit 8)                                         */
+ #define R_USBF_DSCITVL_DITVL_Msk           (0xff00UL)     /*!< DITVL (Bitfield-Mask: 0xff)                           */
+/* =======================================================  DSTAT_EN  ======================================================== */
+ #define R_USBF_DSTAT_EN_EN0_Pos            (0UL)          /*!< EN0 (Bit 0)                                           */
+ #define R_USBF_DSTAT_EN_EN0_Msk            (0x1UL)        /*!< EN0 (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_DSTAT_EN_EN1_Pos            (1UL)          /*!< EN1 (Bit 1)                                           */
+ #define R_USBF_DSTAT_EN_EN1_Msk            (0x2UL)        /*!< EN1 (Bitfield-Mask: 0x01)                             */
+/* =======================================================  DSTAT_ER  ======================================================== */
+ #define R_USBF_DSTAT_ER_ER0_Pos            (0UL)          /*!< ER0 (Bit 0)                                           */
+ #define R_USBF_DSTAT_ER_ER0_Msk            (0x1UL)        /*!< ER0 (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_DSTAT_ER_ER1_Pos            (1UL)          /*!< ER1 (Bit 1)                                           */
+ #define R_USBF_DSTAT_ER_ER1_Msk            (0x2UL)        /*!< ER1 (Bitfield-Mask: 0x01)                             */
+/* =======================================================  DSTAT_END  ======================================================= */
+ #define R_USBF_DSTAT_END_END0_Pos          (0UL)          /*!< END0 (Bit 0)                                          */
+ #define R_USBF_DSTAT_END_END0_Msk          (0x1UL)        /*!< END0 (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_DSTAT_END_END1_Pos          (1UL)          /*!< END1 (Bit 1)                                          */
+ #define R_USBF_DSTAT_END_END1_Msk          (0x2UL)        /*!< END1 (Bitfield-Mask: 0x01)                            */
+/* =======================================================  DSTAT_TC  ======================================================== */
+ #define R_USBF_DSTAT_TC_TC0_Pos            (0UL)          /*!< TC0 (Bit 0)                                           */
+ #define R_USBF_DSTAT_TC_TC0_Msk            (0x1UL)        /*!< TC0 (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_DSTAT_TC_TC1_Pos            (1UL)          /*!< TC1 (Bit 1)                                           */
+ #define R_USBF_DSTAT_TC_TC1_Msk            (0x2UL)        /*!< TC1 (Bitfield-Mask: 0x01)                             */
+/* =======================================================  DSTAT_SUS  ======================================================= */
+ #define R_USBF_DSTAT_SUS_SUS0_Pos          (0UL)          /*!< SUS0 (Bit 0)                                          */
+ #define R_USBF_DSTAT_SUS_SUS0_Msk          (0x1UL)        /*!< SUS0 (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_DSTAT_SUS_SUS1_Pos          (1UL)          /*!< SUS1 (Bit 1)                                          */
+ #define R_USBF_DSTAT_SUS_SUS1_Msk          (0x2UL)        /*!< SUS1 (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BSC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CMNCR  ========================================================= */
+ #define R_BSC_CMNCR_DPRTY_Pos        (9UL)          /*!< DPRTY (Bit 9)                                         */
+ #define R_BSC_CMNCR_DPRTY_Msk        (0x600UL)      /*!< DPRTY (Bitfield-Mask: 0x03)                           */
+ #define R_BSC_CMNCR_AL_Pos           (24UL)         /*!< AL (Bit 24)                                           */
+ #define R_BSC_CMNCR_AL_Msk           (0x1000000UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CMNCR_TL_Pos           (28UL)         /*!< TL (Bit 28)                                           */
+ #define R_BSC_CMNCR_TL_Msk           (0x10000000UL) /*!< TL (Bitfield-Mask: 0x01)                              */
+/* ========================================================  CSnBCR  ========================================================= */
+ #define R_BSC_CSnBCR_BSZ_Pos         (9UL)          /*!< BSZ (Bit 9)                                           */
+ #define R_BSC_CSnBCR_BSZ_Msk         (0x600UL)      /*!< BSZ (Bitfield-Mask: 0x03)                             */
+ #define R_BSC_CSnBCR_TYPE_Pos        (12UL)         /*!< TYPE (Bit 12)                                         */
+ #define R_BSC_CSnBCR_TYPE_Msk        (0x7000UL)     /*!< TYPE (Bitfield-Mask: 0x07)                            */
+ #define R_BSC_CSnBCR_IWRRS_Pos       (16UL)         /*!< IWRRS (Bit 16)                                        */
+ #define R_BSC_CSnBCR_IWRRS_Msk       (0x70000UL)    /*!< IWRRS (Bitfield-Mask: 0x07)                           */
+ #define R_BSC_CSnBCR_IWRRD_Pos       (19UL)         /*!< IWRRD (Bit 19)                                        */
+ #define R_BSC_CSnBCR_IWRRD_Msk       (0x380000UL)   /*!< IWRRD (Bitfield-Mask: 0x07)                           */
+ #define R_BSC_CSnBCR_IWRWS_Pos       (22UL)         /*!< IWRWS (Bit 22)                                        */
+ #define R_BSC_CSnBCR_IWRWS_Msk       (0x1c00000UL)  /*!< IWRWS (Bitfield-Mask: 0x07)                           */
+ #define R_BSC_CSnBCR_IWRWD_Pos       (25UL)         /*!< IWRWD (Bit 25)                                        */
+ #define R_BSC_CSnBCR_IWRWD_Msk       (0xe000000UL)  /*!< IWRWD (Bitfield-Mask: 0x07)                           */
+ #define R_BSC_CSnBCR_IWW_Pos         (28UL)         /*!< IWW (Bit 28)                                          */
+ #define R_BSC_CSnBCR_IWW_Msk         (0x70000000UL) /*!< IWW (Bitfield-Mask: 0x07)                             */
+/* =======================================================  CS0WCR_0  ======================================================== */
+ #define R_BSC_CS0WCR_0_HW_Pos        (0UL)          /*!< HW (Bit 0)                                            */
+ #define R_BSC_CS0WCR_0_HW_Msk        (0x3UL)        /*!< HW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS0WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS0WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS0WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
+ #define R_BSC_CS0WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
+ #define R_BSC_CS0WCR_0_SW_Pos        (11UL)         /*!< SW (Bit 11)                                           */
+ #define R_BSC_CS0WCR_0_SW_Msk        (0x1800UL)     /*!< SW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS0WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
+ #define R_BSC_CS0WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
+/* =======================================================  CS0WCR_1  ======================================================== */
+ #define R_BSC_CS0WCR_1_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS0WCR_1_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS0WCR_1_W_Pos         (7UL)          /*!< W (Bit 7)                                             */
+ #define R_BSC_CS0WCR_1_W_Msk         (0x780UL)      /*!< W (Bitfield-Mask: 0x0f)                               */
+ #define R_BSC_CS0WCR_1_BW_Pos        (16UL)         /*!< BW (Bit 16)                                           */
+ #define R_BSC_CS0WCR_1_BW_Msk        (0x30000UL)    /*!< BW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS0WCR_1_BST_Pos       (20UL)         /*!< BST (Bit 20)                                          */
+ #define R_BSC_CS0WCR_1_BST_Msk       (0x300000UL)   /*!< BST (Bitfield-Mask: 0x03)                             */
+/* =======================================================  CS0WCR_2  ======================================================== */
+ #define R_BSC_CS0WCR_2_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS0WCR_2_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS0WCR_2_W_Pos         (7UL)          /*!< W (Bit 7)                                             */
+ #define R_BSC_CS0WCR_2_W_Msk         (0x780UL)      /*!< W (Bitfield-Mask: 0x0f)                               */
+ #define R_BSC_CS0WCR_2_BW_Pos        (16UL)         /*!< BW (Bit 16)                                           */
+ #define R_BSC_CS0WCR_2_BW_Msk        (0x30000UL)    /*!< BW (Bitfield-Mask: 0x03)                              */
+/* =======================================================  CS2WCR_0  ======================================================== */
+ #define R_BSC_CS2WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS2WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS2WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
+ #define R_BSC_CS2WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
+ #define R_BSC_CS2WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
+ #define R_BSC_CS2WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
+/* =======================================================  CS2WCR_1  ======================================================== */
+ #define R_BSC_CS2WCR_1_A2CL_Pos      (7UL)          /*!< A2CL (Bit 7)                                          */
+ #define R_BSC_CS2WCR_1_A2CL_Msk      (0x180UL)      /*!< A2CL (Bitfield-Mask: 0x03)                            */
+/* =======================================================  CS3WCR_0  ======================================================== */
+ #define R_BSC_CS3WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS3WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS3WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
+ #define R_BSC_CS3WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
+ #define R_BSC_CS3WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
+ #define R_BSC_CS3WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
+/* =======================================================  CS3WCR_1  ======================================================== */
+ #define R_BSC_CS3WCR_1_WTRC_Pos      (0UL)          /*!< WTRC (Bit 0)                                          */
+ #define R_BSC_CS3WCR_1_WTRC_Msk      (0x3UL)        /*!< WTRC (Bitfield-Mask: 0x03)                            */
+ #define R_BSC_CS3WCR_1_TRWL_Pos      (3UL)          /*!< TRWL (Bit 3)                                          */
+ #define R_BSC_CS3WCR_1_TRWL_Msk      (0x18UL)       /*!< TRWL (Bitfield-Mask: 0x03)                            */
+ #define R_BSC_CS3WCR_1_A3CL_Pos      (7UL)          /*!< A3CL (Bit 7)                                          */
+ #define R_BSC_CS3WCR_1_A3CL_Msk      (0x180UL)      /*!< A3CL (Bitfield-Mask: 0x03)                            */
+ #define R_BSC_CS3WCR_1_WTRCD_Pos     (10UL)         /*!< WTRCD (Bit 10)                                        */
+ #define R_BSC_CS3WCR_1_WTRCD_Msk     (0xc00UL)      /*!< WTRCD (Bitfield-Mask: 0x03)                           */
+ #define R_BSC_CS3WCR_1_WTRP_Pos      (13UL)         /*!< WTRP (Bit 13)                                         */
+ #define R_BSC_CS3WCR_1_WTRP_Msk      (0x6000UL)     /*!< WTRP (Bitfield-Mask: 0x03)                            */
+/* ========================================================  CS5WCR  ========================================================= */
+ #define R_BSC_CS5WCR_HW_Pos          (0UL)          /*!< HW (Bit 0)                                            */
+ #define R_BSC_CS5WCR_HW_Msk          (0x3UL)        /*!< HW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS5WCR_WM_Pos          (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS5WCR_WM_Msk          (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS5WCR_WR_Pos          (7UL)          /*!< WR (Bit 7)                                            */
+ #define R_BSC_CS5WCR_WR_Msk          (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
+ #define R_BSC_CS5WCR_SW_Pos          (11UL)         /*!< SW (Bit 11)                                           */
+ #define R_BSC_CS5WCR_SW_Msk          (0x1800UL)     /*!< SW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS5WCR_WW_Pos          (16UL)         /*!< WW (Bit 16)                                           */
+ #define R_BSC_CS5WCR_WW_Msk          (0x70000UL)    /*!< WW (Bitfield-Mask: 0x07)                              */
+ #define R_BSC_CS5WCR_MPXWSBAS_Pos    (20UL)         /*!< MPXWSBAS (Bit 20)                                     */
+ #define R_BSC_CS5WCR_MPXWSBAS_Msk    (0x100000UL)   /*!< MPXWSBAS (Bitfield-Mask: 0x01)                        */
+ #define R_BSC_CS5WCR_SZSEL_Pos       (21UL)         /*!< SZSEL (Bit 21)                                        */
+ #define R_BSC_CS5WCR_SZSEL_Msk       (0x200000UL)   /*!< SZSEL (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SDCR  ========================================================== */
+ #define R_BSC_SDCR_A3COL_Pos         (0UL)          /*!< A3COL (Bit 0)                                         */
+ #define R_BSC_SDCR_A3COL_Msk         (0x3UL)        /*!< A3COL (Bitfield-Mask: 0x03)                           */
+ #define R_BSC_SDCR_A3ROW_Pos         (3UL)          /*!< A3ROW (Bit 3)                                         */
+ #define R_BSC_SDCR_A3ROW_Msk         (0x18UL)       /*!< A3ROW (Bitfield-Mask: 0x03)                           */
+ #define R_BSC_SDCR_BACTV_Pos         (8UL)          /*!< BACTV (Bit 8)                                         */
+ #define R_BSC_SDCR_BACTV_Msk         (0x100UL)      /*!< BACTV (Bitfield-Mask: 0x01)                           */
+ #define R_BSC_SDCR_PDOWN_Pos         (9UL)          /*!< PDOWN (Bit 9)                                         */
+ #define R_BSC_SDCR_PDOWN_Msk         (0x200UL)      /*!< PDOWN (Bitfield-Mask: 0x01)                           */
+ #define R_BSC_SDCR_RMODE_Pos         (10UL)         /*!< RMODE (Bit 10)                                        */
+ #define R_BSC_SDCR_RMODE_Msk         (0x400UL)      /*!< RMODE (Bitfield-Mask: 0x01)                           */
+ #define R_BSC_SDCR_RFSH_Pos          (11UL)         /*!< RFSH (Bit 11)                                         */
+ #define R_BSC_SDCR_RFSH_Msk          (0x800UL)      /*!< RFSH (Bitfield-Mask: 0x01)                            */
+ #define R_BSC_SDCR_DEEP_Pos          (13UL)         /*!< DEEP (Bit 13)                                         */
+ #define R_BSC_SDCR_DEEP_Msk          (0x2000UL)     /*!< DEEP (Bitfield-Mask: 0x01)                            */
+ #define R_BSC_SDCR_A2COL_Pos         (16UL)         /*!< A2COL (Bit 16)                                        */
+ #define R_BSC_SDCR_A2COL_Msk         (0x30000UL)    /*!< A2COL (Bitfield-Mask: 0x03)                           */
+ #define R_BSC_SDCR_A2ROW_Pos         (19UL)         /*!< A2ROW (Bit 19)                                        */
+ #define R_BSC_SDCR_A2ROW_Msk         (0x180000UL)   /*!< A2ROW (Bitfield-Mask: 0x03)                           */
+/* =========================================================  RTCSR  ========================================================= */
+/* =========================================================  RTCNT  ========================================================= */
+/* =========================================================  RTCOR  ========================================================= */
+/* ========================================================  TOSCOR  ========================================================= */
+ #define R_BSC_TOSCOR_TOCNUM_Pos      (0UL)      /*!< TOCNUM (Bit 0)                                        */
+ #define R_BSC_TOSCOR_TOCNUM_Msk      (0xffffUL) /*!< TOCNUM (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  TOSTR  ========================================================= */
+ #define R_BSC_TOSTR_CS0TOSTF_Pos     (0UL)      /*!< CS0TOSTF (Bit 0)                                      */
+ #define R_BSC_TOSTR_CS0TOSTF_Msk     (0x1UL)    /*!< CS0TOSTF (Bitfield-Mask: 0x01)                        */
+ #define R_BSC_TOSTR_CS2TOSTF_Pos     (2UL)      /*!< CS2TOSTF (Bit 2)                                      */
+ #define R_BSC_TOSTR_CS2TOSTF_Msk     (0x4UL)    /*!< CS2TOSTF (Bitfield-Mask: 0x01)                        */
+ #define R_BSC_TOSTR_CS3TOSTF_Pos     (3UL)      /*!< CS3TOSTF (Bit 3)                                      */
+ #define R_BSC_TOSTR_CS3TOSTF_Msk     (0x8UL)    /*!< CS3TOSTF (Bitfield-Mask: 0x01)                        */
+ #define R_BSC_TOSTR_CS5TOSTF_Pos     (5UL)      /*!< CS5TOSTF (Bit 5)                                      */
+ #define R_BSC_TOSTR_CS5TOSTF_Msk     (0x20UL)   /*!< CS5TOSTF (Bitfield-Mask: 0x01)                        */
+/* =========================================================  TOENR  ========================================================= */
+ #define R_BSC_TOENR_CS0TOEN_Pos      (0UL)      /*!< CS0TOEN (Bit 0)                                       */
+ #define R_BSC_TOENR_CS0TOEN_Msk      (0x1UL)    /*!< CS0TOEN (Bitfield-Mask: 0x01)                         */
+ #define R_BSC_TOENR_CS2TOEN_Pos      (2UL)      /*!< CS2TOEN (Bit 2)                                       */
+ #define R_BSC_TOENR_CS2TOEN_Msk      (0x4UL)    /*!< CS2TOEN (Bitfield-Mask: 0x01)                         */
+ #define R_BSC_TOENR_CS3TOEN_Pos      (3UL)      /*!< CS3TOEN (Bit 3)                                       */
+ #define R_BSC_TOENR_CS3TOEN_Msk      (0x8UL)    /*!< CS3TOEN (Bitfield-Mask: 0x01)                         */
+ #define R_BSC_TOENR_CS5TOEN_Pos      (5UL)      /*!< CS5TOEN (Bit 5)                                       */
+ #define R_BSC_TOENR_CS5TOEN_Msk      (0x20UL)   /*!< CS5TOEN (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_XSPI0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  WRAPCFG  ======================================================== */
+ #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos      (8UL)          /*!< DSSFTCS0 (Bit 8)                                      */
+ #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk      (0x1f00UL)     /*!< DSSFTCS0 (Bitfield-Mask: 0x1f)                        */
+ #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos      (24UL)         /*!< DSSFTCS1 (Bit 24)                                     */
+ #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk      (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f)                        */
+/* ========================================================  COMCFG  ========================================================= */
+ #define R_XSPI0_COMCFG_OEASTEX_Pos        (16UL)         /*!< OEASTEX (Bit 16)                                      */
+ #define R_XSPI0_COMCFG_OEASTEX_Msk        (0x10000UL)    /*!< OEASTEX (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_COMCFG_OENEGEX_Pos        (17UL)         /*!< OENEGEX (Bit 17)                                      */
+ #define R_XSPI0_COMCFG_OENEGEX_Msk        (0x20000UL)    /*!< OENEGEX (Bitfield-Mask: 0x01)                         */
+/* =========================================================  BMCFG  ========================================================= */
+ #define R_XSPI0_BMCFG_WRMD_Pos            (0UL)          /*!< WRMD (Bit 0)                                          */
+ #define R_XSPI0_BMCFG_WRMD_Msk            (0x1UL)        /*!< WRMD (Bitfield-Mask: 0x01)                            */
+ #define R_XSPI0_BMCFG_MWRCOMB_Pos         (7UL)          /*!< MWRCOMB (Bit 7)                                       */
+ #define R_XSPI0_BMCFG_MWRCOMB_Msk         (0x80UL)       /*!< MWRCOMB (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_BMCFG_MWRSIZE_Pos         (8UL)          /*!< MWRSIZE (Bit 8)                                       */
+ #define R_XSPI0_BMCFG_MWRSIZE_Msk         (0xff00UL)     /*!< MWRSIZE (Bitfield-Mask: 0xff)                         */
+ #define R_XSPI0_BMCFG_PREEN_Pos           (16UL)         /*!< PREEN (Bit 16)                                        */
+ #define R_XSPI0_BMCFG_PREEN_Msk           (0x10000UL)    /*!< PREEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  LIOCFGCS  ======================================================== */
+ #define R_XSPI0_LIOCFGCS_PRTMD_Pos        (0UL)          /*!< PRTMD (Bit 0)                                         */
+ #define R_XSPI0_LIOCFGCS_PRTMD_Msk        (0x3ffUL)      /*!< PRTMD (Bitfield-Mask: 0x3ff)                          */
+ #define R_XSPI0_LIOCFGCS_LATEMD_Pos       (10UL)         /*!< LATEMD (Bit 10)                                       */
+ #define R_XSPI0_LIOCFGCS_LATEMD_Msk       (0x400UL)      /*!< LATEMD (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos      (11UL)         /*!< WRMSKMD (Bit 11)                                      */
+ #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk      (0x800UL)      /*!< WRMSKMD (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_LIOCFGCS_CSMIN_Pos        (16UL)         /*!< CSMIN (Bit 16)                                        */
+ #define R_XSPI0_LIOCFGCS_CSMIN_Msk        (0xf0000UL)    /*!< CSMIN (Bitfield-Mask: 0x0f)                           */
+ #define R_XSPI0_LIOCFGCS_CSASTEX_Pos      (20UL)         /*!< CSASTEX (Bit 20)                                      */
+ #define R_XSPI0_LIOCFGCS_CSASTEX_Msk      (0x100000UL)   /*!< CSASTEX (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos      (21UL)         /*!< CSNEGEX (Bit 21)                                      */
+ #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk      (0x200000UL)   /*!< CSNEGEX (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_LIOCFGCS_SDRDRV_Pos       (22UL)         /*!< SDRDRV (Bit 22)                                       */
+ #define R_XSPI0_LIOCFGCS_SDRDRV_Msk       (0x400000UL)   /*!< SDRDRV (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos     (23UL)         /*!< SDRSMPMD (Bit 23)                                     */
+ #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk     (0x800000UL)   /*!< SDRSMPMD (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos    (24UL)         /*!< SDRSMPSFT (Bit 24)                                    */
+ #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk    (0xf000000UL)  /*!< SDRSMPSFT (Bitfield-Mask: 0x0f)                       */
+ #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos     (28UL)         /*!< DDRSMPEX (Bit 28)                                     */
+ #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk     (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f)                        */
+/* ========================================================  BMCTL0  ========================================================= */
+ #define R_XSPI0_BMCTL0_CS0ACC_Pos         (0UL)          /*!< CS0ACC (Bit 0)                                        */
+ #define R_XSPI0_BMCTL0_CS0ACC_Msk         (0x3UL)        /*!< CS0ACC (Bitfield-Mask: 0x03)                          */
+ #define R_XSPI0_BMCTL0_CS1ACC_Pos         (2UL)          /*!< CS1ACC (Bit 2)                                        */
+ #define R_XSPI0_BMCTL0_CS1ACC_Msk         (0xcUL)        /*!< CS1ACC (Bitfield-Mask: 0x03)                          */
+/* ========================================================  BMCTL1  ========================================================= */
+ #define R_XSPI0_BMCTL1_MWRPUSH_Pos        (8UL)          /*!< MWRPUSH (Bit 8)                                       */
+ #define R_XSPI0_BMCTL1_MWRPUSH_Msk        (0x100UL)      /*!< MWRPUSH (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_BMCTL1_PBUFCLR_Pos        (10UL)         /*!< PBUFCLR (Bit 10)                                      */
+ #define R_XSPI0_BMCTL1_PBUFCLR_Msk        (0x400UL)      /*!< PBUFCLR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  CMCTL  ========================================================= */
+ #define R_XSPI0_CMCTL_XIPENCODE_Pos       (0UL)          /*!< XIPENCODE (Bit 0)                                     */
+ #define R_XSPI0_CMCTL_XIPENCODE_Msk       (0xffUL)       /*!< XIPENCODE (Bitfield-Mask: 0xff)                       */
+ #define R_XSPI0_CMCTL_XIPEXCODE_Pos       (8UL)          /*!< XIPEXCODE (Bit 8)                                     */
+ #define R_XSPI0_CMCTL_XIPEXCODE_Msk       (0xff00UL)     /*!< XIPEXCODE (Bitfield-Mask: 0xff)                       */
+ #define R_XSPI0_CMCTL_XIPEN_Pos           (16UL)         /*!< XIPEN (Bit 16)                                        */
+ #define R_XSPI0_CMCTL_XIPEN_Msk           (0x10000UL)    /*!< XIPEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CSSCTL  ========================================================= */
+ #define R_XSPI0_CSSCTL_CS0SIZE_Pos        (0UL)          /*!< CS0SIZE (Bit 0)                                       */
+ #define R_XSPI0_CSSCTL_CS0SIZE_Msk        (0x3fUL)       /*!< CS0SIZE (Bitfield-Mask: 0x3f)                         */
+ #define R_XSPI0_CSSCTL_CS1SIZE_Pos        (8UL)          /*!< CS1SIZE (Bit 8)                                       */
+ #define R_XSPI0_CSSCTL_CS1SIZE_Msk        (0x3f00UL)     /*!< CS1SIZE (Bitfield-Mask: 0x3f)                         */
+/* ========================================================  CDCTL0  ========================================================= */
+ #define R_XSPI0_CDCTL0_TRREQ_Pos          (0UL)          /*!< TRREQ (Bit 0)                                         */
+ #define R_XSPI0_CDCTL0_TRREQ_Msk          (0x1UL)        /*!< TRREQ (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_CDCTL0_PERMD_Pos          (1UL)          /*!< PERMD (Bit 1)                                         */
+ #define R_XSPI0_CDCTL0_PERMD_Msk          (0x2UL)        /*!< PERMD (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_CDCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
+ #define R_XSPI0_CDCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_CDCTL0_TRNUM_Pos          (4UL)          /*!< TRNUM (Bit 4)                                         */
+ #define R_XSPI0_CDCTL0_TRNUM_Msk          (0x30UL)       /*!< TRNUM (Bitfield-Mask: 0x03)                           */
+ #define R_XSPI0_CDCTL0_PERITV_Pos         (16UL)         /*!< PERITV (Bit 16)                                       */
+ #define R_XSPI0_CDCTL0_PERITV_Msk         (0x1f0000UL)   /*!< PERITV (Bitfield-Mask: 0x1f)                          */
+ #define R_XSPI0_CDCTL0_PERREP_Pos         (24UL)         /*!< PERREP (Bit 24)                                       */
+ #define R_XSPI0_CDCTL0_PERREP_Msk         (0xf000000UL)  /*!< PERREP (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  CDCTL1  ========================================================= */
+ #define R_XSPI0_CDCTL1_PEREXP_Pos         (0UL)          /*!< PEREXP (Bit 0)                                        */
+ #define R_XSPI0_CDCTL1_PEREXP_Msk         (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CDCTL2  ========================================================= */
+ #define R_XSPI0_CDCTL2_PERMSK_Pos         (0UL)          /*!< PERMSK (Bit 0)                                        */
+ #define R_XSPI0_CDCTL2_PERMSK_Msk         (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  LPCTL0  ========================================================= */
+ #define R_XSPI0_LPCTL0_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
+ #define R_XSPI0_LPCTL0_PATREQ_Msk         (0x1UL)        /*!< PATREQ (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LPCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
+ #define R_XSPI0_LPCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_LPCTL0_XDPIN_Pos          (4UL)          /*!< XDPIN (Bit 4)                                         */
+ #define R_XSPI0_LPCTL0_XDPIN_Msk          (0x30UL)       /*!< XDPIN (Bitfield-Mask: 0x03)                           */
+ #define R_XSPI0_LPCTL0_XD1LEN_Pos         (16UL)         /*!< XD1LEN (Bit 16)                                       */
+ #define R_XSPI0_LPCTL0_XD1LEN_Msk         (0x1f0000UL)   /*!< XD1LEN (Bitfield-Mask: 0x1f)                          */
+ #define R_XSPI0_LPCTL0_XD1VAL_Pos         (23UL)         /*!< XD1VAL (Bit 23)                                       */
+ #define R_XSPI0_LPCTL0_XD1VAL_Msk         (0x800000UL)   /*!< XD1VAL (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LPCTL0_XD2LEN_Pos         (24UL)         /*!< XD2LEN (Bit 24)                                       */
+ #define R_XSPI0_LPCTL0_XD2LEN_Msk         (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f)                          */
+ #define R_XSPI0_LPCTL0_XD2VAL_Pos         (31UL)         /*!< XD2VAL (Bit 31)                                       */
+ #define R_XSPI0_LPCTL0_XD2VAL_Msk         (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01)                          */
+/* ========================================================  LPCTL1  ========================================================= */
+ #define R_XSPI0_LPCTL1_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
+ #define R_XSPI0_LPCTL1_PATREQ_Msk         (0x3UL)        /*!< PATREQ (Bitfield-Mask: 0x03)                          */
+ #define R_XSPI0_LPCTL1_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
+ #define R_XSPI0_LPCTL1_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_LPCTL1_RSTREP_Pos         (4UL)          /*!< RSTREP (Bit 4)                                        */
+ #define R_XSPI0_LPCTL1_RSTREP_Msk         (0x30UL)       /*!< RSTREP (Bitfield-Mask: 0x03)                          */
+ #define R_XSPI0_LPCTL1_RSTWID_Pos         (8UL)          /*!< RSTWID (Bit 8)                                        */
+ #define R_XSPI0_LPCTL1_RSTWID_Msk         (0x700UL)      /*!< RSTWID (Bitfield-Mask: 0x07)                          */
+ #define R_XSPI0_LPCTL1_RSTSU_Pos          (12UL)         /*!< RSTSU (Bit 12)                                        */
+ #define R_XSPI0_LPCTL1_RSTSU_Msk          (0x7000UL)     /*!< RSTSU (Bitfield-Mask: 0x07)                           */
+/* ========================================================  LIOCTL  ========================================================= */
+ #define R_XSPI0_LIOCTL_WPCS0_Pos          (0UL)          /*!< WPCS0 (Bit 0)                                         */
+ #define R_XSPI0_LIOCTL_WPCS0_Msk          (0x1UL)        /*!< WPCS0 (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_LIOCTL_WPCS1_Pos          (1UL)          /*!< WPCS1 (Bit 1)                                         */
+ #define R_XSPI0_LIOCTL_WPCS1_Msk          (0x2UL)        /*!< WPCS1 (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_LIOCTL_RSTCS0_Pos         (16UL)         /*!< RSTCS0 (Bit 16)                                       */
+ #define R_XSPI0_LIOCTL_RSTCS0_Msk         (0x10000UL)    /*!< RSTCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LIOCTL_RSTCS1_Pos         (17UL)         /*!< RSTCS1 (Bit 17)                                       */
+ #define R_XSPI0_LIOCTL_RSTCS1_Msk         (0x20000UL)    /*!< RSTCS1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  VERSTT  ========================================================= */
+ #define R_XSPI0_VERSTT_VER_Pos            (0UL)          /*!< VER (Bit 0)                                           */
+ #define R_XSPI0_VERSTT_VER_Msk            (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  COMSTT  ========================================================= */
+ #define R_XSPI0_COMSTT_MEMACC_Pos         (0UL)          /*!< MEMACC (Bit 0)                                        */
+ #define R_XSPI0_COMSTT_MEMACC_Msk         (0x1UL)        /*!< MEMACC (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_PBUFNE_Pos         (4UL)          /*!< PBUFNE (Bit 4)                                        */
+ #define R_XSPI0_COMSTT_PBUFNE_Msk         (0x10UL)       /*!< PBUFNE (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_WRBUFNE_Pos        (6UL)          /*!< WRBUFNE (Bit 6)                                       */
+ #define R_XSPI0_COMSTT_WRBUFNE_Msk        (0x40UL)       /*!< WRBUFNE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_COMSTT_ECSCS0_Pos         (16UL)         /*!< ECSCS0 (Bit 16)                                       */
+ #define R_XSPI0_COMSTT_ECSCS0_Msk         (0x10000UL)    /*!< ECSCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_INTCS0_Pos         (17UL)         /*!< INTCS0 (Bit 17)                                       */
+ #define R_XSPI0_COMSTT_INTCS0_Msk         (0x20000UL)    /*!< INTCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_RSTOCS0_Pos        (18UL)         /*!< RSTOCS0 (Bit 18)                                      */
+ #define R_XSPI0_COMSTT_RSTOCS0_Msk        (0x40000UL)    /*!< RSTOCS0 (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_COMSTT_ECSCS1_Pos         (20UL)         /*!< ECSCS1 (Bit 20)                                       */
+ #define R_XSPI0_COMSTT_ECSCS1_Msk         (0x100000UL)   /*!< ECSCS1 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_INTCS1_Pos         (21UL)         /*!< INTCS1 (Bit 21)                                       */
+ #define R_XSPI0_COMSTT_INTCS1_Msk         (0x200000UL)   /*!< INTCS1 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_RSTOCS1_Pos        (22UL)         /*!< RSTOCS1 (Bit 22)                                      */
+ #define R_XSPI0_COMSTT_RSTOCS1_Msk        (0x400000UL)   /*!< RSTOCS1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  CASTTCS  ======================================================== */
+ #define R_XSPI0_CASTTCS_CASUC_Pos         (0UL)          /*!< CASUC (Bit 0)                                         */
+ #define R_XSPI0_CASTTCS_CASUC_Msk         (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  INTS  ========================================================== */
+ #define R_XSPI0_INTS_CMDCMP_Pos           (0UL)          /*!< CMDCMP (Bit 0)                                        */
+ #define R_XSPI0_INTS_CMDCMP_Msk           (0x1UL)        /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_PATCMP_Pos           (1UL)          /*!< PATCMP (Bit 1)                                        */
+ #define R_XSPI0_INTS_PATCMP_Msk           (0x2UL)        /*!< PATCMP (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_INICMP_Pos           (2UL)          /*!< INICMP (Bit 2)                                        */
+ #define R_XSPI0_INTS_INICMP_Msk           (0x4UL)        /*!< INICMP (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_PERTO_Pos            (3UL)          /*!< PERTO (Bit 3)                                         */
+ #define R_XSPI0_INTS_PERTO_Msk            (0x8UL)        /*!< PERTO (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_INTS_DSTOCS0_Pos          (4UL)          /*!< DSTOCS0 (Bit 4)                                       */
+ #define R_XSPI0_INTS_DSTOCS0_Msk          (0x10UL)       /*!< DSTOCS0 (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTS_DSTOCS1_Pos          (5UL)          /*!< DSTOCS1 (Bit 5)                                       */
+ #define R_XSPI0_INTS_DSTOCS1_Msk          (0x20UL)       /*!< DSTOCS1 (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTS_ECSCS0_Pos           (8UL)          /*!< ECSCS0 (Bit 8)                                        */
+ #define R_XSPI0_INTS_ECSCS0_Msk           (0x100UL)      /*!< ECSCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_ECSCS1_Pos           (9UL)          /*!< ECSCS1 (Bit 9)                                        */
+ #define R_XSPI0_INTS_ECSCS1_Msk           (0x200UL)      /*!< ECSCS1 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_INTCS0_Pos           (12UL)         /*!< INTCS0 (Bit 12)                                       */
+ #define R_XSPI0_INTS_INTCS0_Msk           (0x1000UL)     /*!< INTCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_INTCS1_Pos           (13UL)         /*!< INTCS1 (Bit 13)                                       */
+ #define R_XSPI0_INTS_INTCS1_Msk           (0x2000UL)     /*!< INTCS1 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_BRGOF_Pos            (16UL)         /*!< BRGOF (Bit 16)                                        */
+ #define R_XSPI0_INTS_BRGOF_Msk            (0x10000UL)    /*!< BRGOF (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_INTS_BRGUF_Pos            (18UL)         /*!< BRGUF (Bit 18)                                        */
+ #define R_XSPI0_INTS_BRGUF_Msk            (0x40000UL)    /*!< BRGUF (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_INTS_BUSERR_Pos           (20UL)         /*!< BUSERR (Bit 20)                                       */
+ #define R_XSPI0_INTS_BUSERR_Msk           (0x100000UL)   /*!< BUSERR (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_CAFAILCS0_Pos        (28UL)         /*!< CAFAILCS0 (Bit 28)                                    */
+ #define R_XSPI0_INTS_CAFAILCS0_Msk        (0x10000000UL) /*!< CAFAILCS0 (Bitfield-Mask: 0x01)                       */
+ #define R_XSPI0_INTS_CAFAILCS1_Pos        (29UL)         /*!< CAFAILCS1 (Bit 29)                                    */
+ #define R_XSPI0_INTS_CAFAILCS1_Msk        (0x20000000UL) /*!< CAFAILCS1 (Bitfield-Mask: 0x01)                       */
+ #define R_XSPI0_INTS_CASUCCS0_Pos         (30UL)         /*!< CASUCCS0 (Bit 30)                                     */
+ #define R_XSPI0_INTS_CASUCCS0_Msk         (0x40000000UL) /*!< CASUCCS0 (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTS_CASUCCS1_Pos         (31UL)         /*!< CASUCCS1 (Bit 31)                                     */
+ #define R_XSPI0_INTS_CASUCCS1_Msk         (0x80000000UL) /*!< CASUCCS1 (Bitfield-Mask: 0x01)                        */
+/* =========================================================  INTC  ========================================================== */
+ #define R_XSPI0_INTC_CMDCMPC_Pos          (0UL)          /*!< CMDCMPC (Bit 0)                                       */
+ #define R_XSPI0_INTC_CMDCMPC_Msk          (0x1UL)        /*!< CMDCMPC (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_PATCMPC_Pos          (1UL)          /*!< PATCMPC (Bit 1)                                       */
+ #define R_XSPI0_INTC_PATCMPC_Msk          (0x2UL)        /*!< PATCMPC (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_INICMPC_Pos          (2UL)          /*!< INICMPC (Bit 2)                                       */
+ #define R_XSPI0_INTC_INICMPC_Msk          (0x4UL)        /*!< INICMPC (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_PERTOC_Pos           (3UL)          /*!< PERTOC (Bit 3)                                        */
+ #define R_XSPI0_INTC_PERTOC_Msk           (0x8UL)        /*!< PERTOC (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTC_DSTOCS0C_Pos         (4UL)          /*!< DSTOCS0C (Bit 4)                                      */
+ #define R_XSPI0_INTC_DSTOCS0C_Msk         (0x10UL)       /*!< DSTOCS0C (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTC_DSTOCS1C_Pos         (5UL)          /*!< DSTOCS1C (Bit 5)                                      */
+ #define R_XSPI0_INTC_DSTOCS1C_Msk         (0x20UL)       /*!< DSTOCS1C (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTC_ECSCS0C_Pos          (8UL)          /*!< ECSCS0C (Bit 8)                                       */
+ #define R_XSPI0_INTC_ECSCS0C_Msk          (0x100UL)      /*!< ECSCS0C (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_ECSCS1C_Pos          (9UL)          /*!< ECSCS1C (Bit 9)                                       */
+ #define R_XSPI0_INTC_ECSCS1C_Msk          (0x200UL)      /*!< ECSCS1C (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_INTCS0C_Pos          (12UL)         /*!< INTCS0C (Bit 12)                                      */
+ #define R_XSPI0_INTC_INTCS0C_Msk          (0x1000UL)     /*!< INTCS0C (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_INTCS1C_Pos          (13UL)         /*!< INTCS1C (Bit 13)                                      */
+ #define R_XSPI0_INTC_INTCS1C_Msk          (0x2000UL)     /*!< INTCS1C (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_BRGOFC_Pos           (16UL)         /*!< BRGOFC (Bit 16)                                       */
+ #define R_XSPI0_INTC_BRGOFC_Msk           (0x10000UL)    /*!< BRGOFC (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTC_BRGUFC_Pos           (18UL)         /*!< BRGUFC (Bit 18)                                       */
+ #define R_XSPI0_INTC_BRGUFC_Msk           (0x40000UL)    /*!< BRGUFC (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTC_BUSERRC_Pos          (20UL)         /*!< BUSERRC (Bit 20)                                      */
+ #define R_XSPI0_INTC_BUSERRC_Msk          (0x100000UL)   /*!< BUSERRC (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_CAFAILCS0C_Pos       (28UL)         /*!< CAFAILCS0C (Bit 28)                                   */
+ #define R_XSPI0_INTC_CAFAILCS0C_Msk       (0x10000000UL) /*!< CAFAILCS0C (Bitfield-Mask: 0x01)                      */
+ #define R_XSPI0_INTC_CAFAILCS1C_Pos       (29UL)         /*!< CAFAILCS1C (Bit 29)                                   */
+ #define R_XSPI0_INTC_CAFAILCS1C_Msk       (0x20000000UL) /*!< CAFAILCS1C (Bitfield-Mask: 0x01)                      */
+ #define R_XSPI0_INTC_CASUCCS0C_Pos        (30UL)         /*!< CASUCCS0C (Bit 30)                                    */
+ #define R_XSPI0_INTC_CASUCCS0C_Msk        (0x40000000UL) /*!< CASUCCS0C (Bitfield-Mask: 0x01)                       */
+ #define R_XSPI0_INTC_CASUCCS1C_Pos        (31UL)         /*!< CASUCCS1C (Bit 31)                                    */
+ #define R_XSPI0_INTC_CASUCCS1C_Msk        (0x80000000UL) /*!< CASUCCS1C (Bitfield-Mask: 0x01)                       */
+/* =========================================================  INTE  ========================================================== */
+ #define R_XSPI0_INTE_CMDCMPE_Pos          (0UL)          /*!< CMDCMPE (Bit 0)                                       */
+ #define R_XSPI0_INTE_CMDCMPE_Msk          (0x1UL)        /*!< CMDCMPE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_PATCMPE_Pos          (1UL)          /*!< PATCMPE (Bit 1)                                       */
+ #define R_XSPI0_INTE_PATCMPE_Msk          (0x2UL)        /*!< PATCMPE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_INICMPE_Pos          (2UL)          /*!< INICMPE (Bit 2)                                       */
+ #define R_XSPI0_INTE_INICMPE_Msk          (0x4UL)        /*!< INICMPE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_PERTOE_Pos           (3UL)          /*!< PERTOE (Bit 3)                                        */
+ #define R_XSPI0_INTE_PERTOE_Msk           (0x8UL)        /*!< PERTOE (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTE_DSTOCS0E_Pos         (4UL)          /*!< DSTOCS0E (Bit 4)                                      */
+ #define R_XSPI0_INTE_DSTOCS0E_Msk         (0x10UL)       /*!< DSTOCS0E (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTE_DSTOCS1E_Pos         (5UL)          /*!< DSTOCS1E (Bit 5)                                      */
+ #define R_XSPI0_INTE_DSTOCS1E_Msk         (0x20UL)       /*!< DSTOCS1E (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTE_ECSCS0E_Pos          (8UL)          /*!< ECSCS0E (Bit 8)                                       */
+ #define R_XSPI0_INTE_ECSCS0E_Msk          (0x100UL)      /*!< ECSCS0E (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_ECSCS1E_Pos          (9UL)          /*!< ECSCS1E (Bit 9)                                       */
+ #define R_XSPI0_INTE_ECSCS1E_Msk          (0x200UL)      /*!< ECSCS1E (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_INTCS0E_Pos          (12UL)         /*!< INTCS0E (Bit 12)                                      */
+ #define R_XSPI0_INTE_INTCS0E_Msk          (0x1000UL)     /*!< INTCS0E (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_INTCS1E_Pos          (13UL)         /*!< INTCS1E (Bit 13)                                      */
+ #define R_XSPI0_INTE_INTCS1E_Msk          (0x2000UL)     /*!< INTCS1E (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_BRGOFE_Pos           (16UL)         /*!< BRGOFE (Bit 16)                                       */
+ #define R_XSPI0_INTE_BRGOFE_Msk           (0x10000UL)    /*!< BRGOFE (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTE_BRGUFE_Pos           (18UL)         /*!< BRGUFE (Bit 18)                                       */
+ #define R_XSPI0_INTE_BRGUFE_Msk           (0x40000UL)    /*!< BRGUFE (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTE_BUSERRE_Pos          (20UL)         /*!< BUSERRE (Bit 20)                                      */
+ #define R_XSPI0_INTE_BUSERRE_Msk          (0x100000UL)   /*!< BUSERRE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_CAFAILCS0E_Pos       (28UL)         /*!< CAFAILCS0E (Bit 28)                                   */
+ #define R_XSPI0_INTE_CAFAILCS0E_Msk       (0x10000000UL) /*!< CAFAILCS0E (Bitfield-Mask: 0x01)                      */
+ #define R_XSPI0_INTE_CAFAILCS1E_Pos       (29UL)         /*!< CAFAILCS1E (Bit 29)                                   */
+ #define R_XSPI0_INTE_CAFAILCS1E_Msk       (0x20000000UL) /*!< CAFAILCS1E (Bitfield-Mask: 0x01)                      */
+ #define R_XSPI0_INTE_CASUCCS0E_Pos        (30UL)         /*!< CASUCCS0E (Bit 30)                                    */
+ #define R_XSPI0_INTE_CASUCCS0E_Msk        (0x40000000UL) /*!< CASUCCS0E (Bitfield-Mask: 0x01)                       */
+ #define R_XSPI0_INTE_CASUCCS1E_Pos        (31UL)         /*!< CASUCCS1E (Bit 31)                                    */
+ #define R_XSPI0_INTE_CASUCCS1E_Msk        (0x80000000UL) /*!< CASUCCS1E (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MBXSEM                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SEM  ========================================================== */
+ #define R_MBXSEM_SEM_SEM_Pos                  (0UL)          /*!< SEM (Bit 0)                                           */
+ #define R_MBXSEM_SEM_SEM_Msk                  (0x1UL)        /*!< SEM (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SEMRCEN  ======================================================== */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN0_Pos         (0UL)          /*!< SEMRCEN0 (Bit 0)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN0_Msk         (0x1UL)        /*!< SEMRCEN0 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN1_Pos         (1UL)          /*!< SEMRCEN1 (Bit 1)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN1_Msk         (0x2UL)        /*!< SEMRCEN1 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN2_Pos         (2UL)          /*!< SEMRCEN2 (Bit 2)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN2_Msk         (0x4UL)        /*!< SEMRCEN2 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN3_Pos         (3UL)          /*!< SEMRCEN3 (Bit 3)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN3_Msk         (0x8UL)        /*!< SEMRCEN3 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN4_Pos         (4UL)          /*!< SEMRCEN4 (Bit 4)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN4_Msk         (0x10UL)       /*!< SEMRCEN4 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN5_Pos         (5UL)          /*!< SEMRCEN5 (Bit 5)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN5_Msk         (0x20UL)       /*!< SEMRCEN5 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN6_Pos         (6UL)          /*!< SEMRCEN6 (Bit 6)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN6_Msk         (0x40UL)       /*!< SEMRCEN6 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN7_Pos         (7UL)          /*!< SEMRCEN7 (Bit 7)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN7_Msk         (0x80UL)       /*!< SEMRCEN7 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MBXH2C  ========================================================= */
+ #define R_MBXSEM_MBXH2C_MBX_Pos               (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXH2C_MBX_Msk               (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETH2C  ======================================================= */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Pos     (0UL)          /*!< MBX_INT0S (Bit 0)                                     */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Msk     (0x1UL)        /*!< MBX_INT0S (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Pos     (1UL)          /*!< MBX_INT1S (Bit 1)                                     */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Msk     (0x2UL)        /*!< MBX_INT1S (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Pos     (2UL)          /*!< MBX_INT2S (Bit 2)                                     */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Msk     (0x4UL)        /*!< MBX_INT2S (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Pos     (3UL)          /*!< MBX_INT3S (Bit 3)                                     */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Msk     (0x8UL)        /*!< MBX_INT3S (Bitfield-Mask: 0x01)                       */
+/* ======================================================  MBXICLRH2C  ======================================================= */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Pos     (0UL)          /*!< MBX_INT0C (Bit 0)                                     */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Msk     (0x1UL)        /*!< MBX_INT0C (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Pos     (1UL)          /*!< MBX_INT1C (Bit 1)                                     */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Msk     (0x2UL)        /*!< MBX_INT1C (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Pos     (2UL)          /*!< MBX_INT2C (Bit 2)                                     */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Msk     (0x4UL)        /*!< MBX_INT2C (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Pos     (3UL)          /*!< MBX_INT3C (Bit 3)                                     */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Msk     (0x8UL)        /*!< MBX_INT3C (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MBXC2H  ========================================================= */
+ #define R_MBXSEM_MBXC2H_MBX_Pos               (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXC2H_MBX_Msk               (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETC2H  ======================================================= */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Pos    (0UL)          /*!< MBX_HINT0S (Bit 0)                                    */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Msk    (0x1UL)        /*!< MBX_HINT0S (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Pos    (1UL)          /*!< MBX_HINT1S (Bit 1)                                    */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Msk    (0x2UL)        /*!< MBX_HINT1S (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Pos    (2UL)          /*!< MBX_HINT2S (Bit 2)                                    */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Msk    (0x4UL)        /*!< MBX_HINT2S (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Pos    (3UL)          /*!< MBX_HINT3S (Bit 3)                                    */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Msk    (0x8UL)        /*!< MBX_HINT3S (Bitfield-Mask: 0x01)                      */
+/* ======================================================  MBXICLRC2H  ======================================================= */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Pos    (0UL)          /*!< MBX_HINT0C (Bit 0)                                    */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Msk    (0x1UL)        /*!< MBX_HINT0C (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Pos    (1UL)          /*!< MBX_HINT1C (Bit 1)                                    */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Msk    (0x2UL)        /*!< MBX_HINT1C (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Pos    (2UL)          /*!< MBX_HINT2C (Bit 2)                                    */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Msk    (0x4UL)        /*!< MBX_HINT2C (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Pos    (3UL)          /*!< MBX_HINT3C (Bit 3)                                    */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Msk    (0x8UL)        /*!< MBX_HINT3C (Bitfield-Mask: 0x01)                      */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SHOSTIF                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CTRLR0  ========================================================= */
+ #define R_SHOSTIF_CTRLR0_SCPH_Pos        (8UL)     /*!< SCPH (Bit 8)                                          */
+ #define R_SHOSTIF_CTRLR0_SCPH_Msk        (0x100UL) /*!< SCPH (Bitfield-Mask: 0x01)                            */
+ #define R_SHOSTIF_CTRLR0_SCPOL_Pos       (9UL)     /*!< SCPOL (Bit 9)                                         */
+ #define R_SHOSTIF_CTRLR0_SCPOL_Msk       (0x200UL) /*!< SCPOL (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  ENR  ========================================================== */
+ #define R_SHOSTIF_ENR_ENABLE_Pos         (0UL)     /*!< ENABLE (Bit 0)                                        */
+ #define R_SHOSTIF_ENR_ENABLE_Msk         (0x1UL)   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RXFBTR  ========================================================= */
+ #define R_SHOSTIF_RXFBTR_RXFBTL_Pos      (0UL)     /*!< RXFBTL (Bit 0)                                        */
+ #define R_SHOSTIF_RXFBTR_RXFBTL_Msk      (0x3fUL)  /*!< RXFBTL (Bitfield-Mask: 0x3f)                          */
+/* ========================================================  TXFTLR  ========================================================= */
+ #define R_SHOSTIF_TXFTLR_TFT_Pos         (0UL)     /*!< TFT (Bit 0)                                           */
+ #define R_SHOSTIF_TXFTLR_TFT_Msk         (0x3fUL)  /*!< TFT (Bitfield-Mask: 0x3f)                             */
+/* ========================================================  RXFTLR  ========================================================= */
+ #define R_SHOSTIF_RXFTLR_RFT_Pos         (0UL)     /*!< RFT (Bit 0)                                           */
+ #define R_SHOSTIF_RXFTLR_RFT_Msk         (0x3fUL)  /*!< RFT (Bitfield-Mask: 0x3f)                             */
+/* ==========================================================  SR  =========================================================== */
+ #define R_SHOSTIF_SR_BUSY_Pos            (0UL)     /*!< BUSY (Bit 0)                                          */
+ #define R_SHOSTIF_SR_BUSY_Msk            (0x1UL)   /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  IMR  ========================================================== */
+ #define R_SHOSTIF_IMR_TXEIM_Pos          (0UL)     /*!< TXEIM (Bit 0)                                         */
+ #define R_SHOSTIF_IMR_TXEIM_Msk          (0x1UL)   /*!< TXEIM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_RXOIM_Pos          (3UL)     /*!< RXOIM (Bit 3)                                         */
+ #define R_SHOSTIF_IMR_RXOIM_Msk          (0x8UL)   /*!< RXOIM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_RXFIM_Pos          (4UL)     /*!< RXFIM (Bit 4)                                         */
+ #define R_SHOSTIF_IMR_RXFIM_Msk          (0x10UL)  /*!< RXFIM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_TXUIM_Pos          (7UL)     /*!< TXUIM (Bit 7)                                         */
+ #define R_SHOSTIF_IMR_TXUIM_Msk          (0x80UL)  /*!< TXUIM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_AHBEM_Pos          (8UL)     /*!< AHBEM (Bit 8)                                         */
+ #define R_SHOSTIF_IMR_AHBEM_Msk          (0x100UL) /*!< AHBEM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_SPIMEM_Pos         (9UL)     /*!< SPIMEM (Bit 9)                                        */
+ #define R_SHOSTIF_IMR_SPIMEM_Msk         (0x200UL) /*!< SPIMEM (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  ISR  ========================================================== */
+ #define R_SHOSTIF_ISR_TXEIS_Pos          (0UL)     /*!< TXEIS (Bit 0)                                         */
+ #define R_SHOSTIF_ISR_TXEIS_Msk          (0x1UL)   /*!< TXEIS (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_RXOIS_Pos          (3UL)     /*!< RXOIS (Bit 3)                                         */
+ #define R_SHOSTIF_ISR_RXOIS_Msk          (0x8UL)   /*!< RXOIS (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_RXFIS_Pos          (4UL)     /*!< RXFIS (Bit 4)                                         */
+ #define R_SHOSTIF_ISR_RXFIS_Msk          (0x10UL)  /*!< RXFIS (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_TXUIS_Pos          (7UL)     /*!< TXUIS (Bit 7)                                         */
+ #define R_SHOSTIF_ISR_TXUIS_Msk          (0x80UL)  /*!< TXUIS (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_AHBES_Pos          (8UL)     /*!< AHBES (Bit 8)                                         */
+ #define R_SHOSTIF_ISR_AHBES_Msk          (0x100UL) /*!< AHBES (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_SPIMES_Pos         (9UL)     /*!< SPIMES (Bit 9)                                        */
+ #define R_SHOSTIF_ISR_SPIMES_Msk         (0x200UL) /*!< SPIMES (Bitfield-Mask: 0x01)                          */
+/* =========================================================  RISR  ========================================================== */
+ #define R_SHOSTIF_RISR_TXEIR_Pos         (0UL)     /*!< TXEIR (Bit 0)                                         */
+ #define R_SHOSTIF_RISR_TXEIR_Msk         (0x1UL)   /*!< TXEIR (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_RXOIR_Pos         (3UL)     /*!< RXOIR (Bit 3)                                         */
+ #define R_SHOSTIF_RISR_RXOIR_Msk         (0x8UL)   /*!< RXOIR (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_RXFIR_Pos         (4UL)     /*!< RXFIR (Bit 4)                                         */
+ #define R_SHOSTIF_RISR_RXFIR_Msk         (0x10UL)  /*!< RXFIR (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_TXUIR_Pos         (7UL)     /*!< TXUIR (Bit 7)                                         */
+ #define R_SHOSTIF_RISR_TXUIR_Msk         (0x80UL)  /*!< TXUIR (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_AHBER_Pos         (8UL)     /*!< AHBER (Bit 8)                                         */
+ #define R_SHOSTIF_RISR_AHBER_Msk         (0x100UL) /*!< AHBER (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_SPIMER_Pos        (9UL)     /*!< SPIMER (Bit 9)                                        */
+ #define R_SHOSTIF_RISR_SPIMER_Msk        (0x200UL) /*!< SPIMER (Bitfield-Mask: 0x01)                          */
+/* ========================================================  TXUICR  ========================================================= */
+ #define R_SHOSTIF_TXUICR_TXUICR_Pos      (0UL)     /*!< TXUICR (Bit 0)                                        */
+ #define R_SHOSTIF_TXUICR_TXUICR_Msk      (0x1UL)   /*!< TXUICR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RXOICR  ========================================================= */
+ #define R_SHOSTIF_RXOICR_RXOICR_Pos      (0UL)     /*!< RXOICR (Bit 0)                                        */
+ #define R_SHOSTIF_RXOICR_RXOICR_Msk      (0x1UL)   /*!< RXOICR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SPIMECR  ======================================================== */
+ #define R_SHOSTIF_SPIMECR_SPIMECR_Pos    (0UL)     /*!< SPIMECR (Bit 0)                                       */
+ #define R_SHOSTIF_SPIMECR_SPIMECR_Msk    (0x1UL)   /*!< SPIMECR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AHBECR  ========================================================= */
+ #define R_SHOSTIF_AHBECR_AHBECR_Pos      (0UL)     /*!< AHBECR (Bit 0)                                        */
+ #define R_SHOSTIF_AHBECR_AHBECR_Msk      (0x1UL)   /*!< AHBECR (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  ICR  ========================================================== */
+ #define R_SHOSTIF_ICR_ICR_Pos            (0UL)     /*!< ICR (Bit 0)                                           */
+ #define R_SHOSTIF_ICR_ICR_Msk            (0x1UL)   /*!< ICR (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                         R_PHOSTIF                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  HIFBCC  ========================================================= */
+ #define R_PHOSTIF_HIFBCC_RBUFON0_Pos     (0UL)          /*!< RBUFON0 (Bit 0)                                       */
+ #define R_PHOSTIF_HIFBCC_RBUFON0_Msk     (0x1UL)        /*!< RBUFON0 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFBCC_RBUFON1_Pos     (1UL)          /*!< RBUFON1 (Bit 1)                                       */
+ #define R_PHOSTIF_HIFBCC_RBUFON1_Msk     (0x2UL)        /*!< RBUFON1 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFBCC_RBUFON2_Pos     (2UL)          /*!< RBUFON2 (Bit 2)                                       */
+ #define R_PHOSTIF_HIFBCC_RBUFON2_Msk     (0x4UL)        /*!< RBUFON2 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFBCC_RBUFON3_Pos     (3UL)          /*!< RBUFON3 (Bit 3)                                       */
+ #define R_PHOSTIF_HIFBCC_RBUFON3_Msk     (0x8UL)        /*!< RBUFON3 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFBCC_RBUFON4_Pos     (4UL)          /*!< RBUFON4 (Bit 4)                                       */
+ #define R_PHOSTIF_HIFBCC_RBUFON4_Msk     (0x10UL)       /*!< RBUFON4 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFBCC_RBUFON5_Pos     (5UL)          /*!< RBUFON5 (Bit 5)                                       */
+ #define R_PHOSTIF_HIFBCC_RBUFON5_Msk     (0x20UL)       /*!< RBUFON5 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFBCC_RBUFONX_Pos     (8UL)          /*!< RBUFONX (Bit 8)                                       */
+ #define R_PHOSTIF_HIFBCC_RBUFONX_Msk     (0x100UL)      /*!< RBUFONX (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFBCC_BSTON_Pos       (12UL)         /*!< BSTON (Bit 12)                                        */
+ #define R_PHOSTIF_HIFBCC_BSTON_Msk       (0x1000UL)     /*!< BSTON (Bitfield-Mask: 0x01)                           */
+ #define R_PHOSTIF_HIFBCC_WRPON_Pos       (13UL)         /*!< WRPON (Bit 13)                                        */
+ #define R_PHOSTIF_HIFBCC_WRPON_Msk       (0x2000UL)     /*!< WRPON (Bitfield-Mask: 0x01)                           */
+/* ========================================================  HIFBTC  ========================================================= */
+ #define R_PHOSTIF_HIFBTC_WRSTD_Pos       (0UL)          /*!< WRSTD (Bit 0)                                         */
+ #define R_PHOSTIF_HIFBTC_WRSTD_Msk       (0x7UL)        /*!< WRSTD (Bitfield-Mask: 0x07)                           */
+ #define R_PHOSTIF_HIFBTC_RDSTD_Pos       (4UL)          /*!< RDSTD (Bit 4)                                         */
+ #define R_PHOSTIF_HIFBTC_RDSTD_Msk       (0x30UL)       /*!< RDSTD (Bitfield-Mask: 0x03)                           */
+ #define R_PHOSTIF_HIFBTC_PASTD_Pos       (8UL)          /*!< PASTD (Bit 8)                                         */
+ #define R_PHOSTIF_HIFBTC_PASTD_Msk       (0x700UL)      /*!< PASTD (Bitfield-Mask: 0x07)                           */
+ #define R_PHOSTIF_HIFBTC_RDDTS_Pos       (12UL)         /*!< RDDTS (Bit 12)                                        */
+ #define R_PHOSTIF_HIFBTC_RDDTS_Msk       (0x3000UL)     /*!< RDDTS (Bitfield-Mask: 0x03)                           */
+/* ========================================================  HIFPRC  ========================================================= */
+ #define R_PHOSTIF_HIFPRC_PAGEON0_Pos     (0UL)          /*!< PAGEON0 (Bit 0)                                       */
+ #define R_PHOSTIF_HIFPRC_PAGEON0_Msk     (0x1UL)        /*!< PAGEON0 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFPRC_PAGEON1_Pos     (1UL)          /*!< PAGEON1 (Bit 1)                                       */
+ #define R_PHOSTIF_HIFPRC_PAGEON1_Msk     (0x2UL)        /*!< PAGEON1 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFPRC_PAGEON2_Pos     (2UL)          /*!< PAGEON2 (Bit 2)                                       */
+ #define R_PHOSTIF_HIFPRC_PAGEON2_Msk     (0x4UL)        /*!< PAGEON2 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFPRC_PAGEON3_Pos     (3UL)          /*!< PAGEON3 (Bit 3)                                       */
+ #define R_PHOSTIF_HIFPRC_PAGEON3_Msk     (0x8UL)        /*!< PAGEON3 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFPRC_PAGEON4_Pos     (4UL)          /*!< PAGEON4 (Bit 4)                                       */
+ #define R_PHOSTIF_HIFPRC_PAGEON4_Msk     (0x10UL)       /*!< PAGEON4 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFPRC_PAGEON5_Pos     (5UL)          /*!< PAGEON5 (Bit 5)                                       */
+ #define R_PHOSTIF_HIFPRC_PAGEON5_Msk     (0x20UL)       /*!< PAGEON5 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFPRC_PAGEONX_Pos     (8UL)          /*!< PAGEONX (Bit 8)                                       */
+ #define R_PHOSTIF_HIFPRC_PAGEONX_Msk     (0x100UL)      /*!< PAGEONX (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFPRC_PAGESZ_Pos      (12UL)         /*!< PAGESZ (Bit 12)                                       */
+ #define R_PHOSTIF_HIFPRC_PAGESZ_Msk      (0x1000UL)     /*!< PAGESZ (Bitfield-Mask: 0x01)                          */
+/* ========================================================  HIFIRC  ========================================================= */
+ #define R_PHOSTIF_HIFIRC_ERRRSP_Pos      (0UL)          /*!< ERRRSP (Bit 0)                                        */
+ #define R_PHOSTIF_HIFIRC_ERRRSP_Msk      (0x1UL)        /*!< ERRRSP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  HIFECR0  ======================================================== */
+ #define R_PHOSTIF_HIFECR0_ERRADDR_Pos    (0UL)          /*!< ERRADDR (Bit 0)                                       */
+ #define R_PHOSTIF_HIFECR0_ERRADDR_Msk    (0xffffffffUL) /*!< ERRADDR (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  HIFECR1  ======================================================== */
+ #define R_PHOSTIF_HIFECR1_ERRSZ_Pos      (0UL)          /*!< ERRSZ (Bit 0)                                         */
+ #define R_PHOSTIF_HIFECR1_ERRSZ_Msk      (0x7UL)        /*!< ERRSZ (Bitfield-Mask: 0x07)                           */
+ #define R_PHOSTIF_HIFECR1_ERRWR_Pos      (3UL)          /*!< ERRWR (Bit 3)                                         */
+ #define R_PHOSTIF_HIFECR1_ERRWR_Msk      (0x8UL)        /*!< ERRWR (Bitfield-Mask: 0x01)                           */
+/* ========================================================  HIFMON1  ======================================================== */
+ #define R_PHOSTIF_HIFMON1_HIFRDY_Pos     (0UL)          /*!< HIFRDY (Bit 0)                                        */
+ #define R_PHOSTIF_HIFMON1_HIFRDY_Msk     (0x1UL)        /*!< HIFRDY (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFMON1_BUSSEL_Pos     (1UL)          /*!< BUSSEL (Bit 1)                                        */
+ #define R_PHOSTIF_HIFMON1_BUSSEL_Msk     (0x2UL)        /*!< BUSSEL (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFMON1_HIFSYNC_Pos    (3UL)          /*!< HIFSYNC (Bit 3)                                       */
+ #define R_PHOSTIF_HIFMON1_HIFSYNC_Msk    (0x8UL)        /*!< HIFSYNC (Bitfield-Mask: 0x01)                         */
+/* ========================================================  HIFMON2  ======================================================== */
+ #define R_PHOSTIF_HIFMON2_HIFBCC_Pos     (0UL)          /*!< HIFBCC (Bit 0)                                        */
+ #define R_PHOSTIF_HIFMON2_HIFBCC_Msk     (0x1UL)        /*!< HIFBCC (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFMON2_HIFBTC_Pos     (1UL)          /*!< HIFBTC (Bit 1)                                        */
+ #define R_PHOSTIF_HIFMON2_HIFBTC_Msk     (0x2UL)        /*!< HIFBTC (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFMON2_HIFPRC_Pos     (2UL)          /*!< HIFPRC (Bit 2)                                        */
+ #define R_PHOSTIF_HIFMON2_HIFPRC_Msk     (0x4UL)        /*!< HIFPRC (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFMON2_HIFIRC_Pos     (3UL)          /*!< HIFIRC (Bit 3)                                        */
+ #define R_PHOSTIF_HIFMON2_HIFIRC_Msk     (0x8UL)        /*!< HIFIRC (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFMON2_HIFXAL_Pos     (4UL)          /*!< HIFXAL (Bit 4)                                        */
+ #define R_PHOSTIF_HIFMON2_HIFXAL_Msk     (0x10UL)       /*!< HIFXAL (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFMON2_HIFXAH_Pos     (5UL)          /*!< HIFXAH (Bit 5)                                        */
+ #define R_PHOSTIF_HIFMON2_HIFXAH_Msk     (0x20UL)       /*!< HIFXAH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  HIFMON3  ======================================================== */
+ #define R_PHOSTIF_HIFMON3_HIFEXT0_Pos    (0UL)          /*!< HIFEXT0 (Bit 0)                                       */
+ #define R_PHOSTIF_HIFMON3_HIFEXT0_Msk    (0x1UL)        /*!< HIFEXT0 (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_HIFMON3_HIFEXT1_Pos    (1UL)          /*!< HIFEXT1 (Bit 1)                                       */
+ #define R_PHOSTIF_HIFMON3_HIFEXT1_Msk    (0x2UL)        /*!< HIFEXT1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  HIFXAL  ========================================================= */
+ #define R_PHOSTIF_HIFXAL_XADDRL_Pos      (0UL)          /*!< XADDRL (Bit 0)                                        */
+ #define R_PHOSTIF_HIFXAL_XADDRL_Msk      (0x1ffUL)      /*!< XADDRL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  HIFXAH  ========================================================= */
+ #define R_PHOSTIF_HIFXAH_XADDRH_Pos      (0UL)          /*!< XADDRH (Bit 0)                                        */
+ #define R_PHOSTIF_HIFXAH_XADDRH_Msk      (0x1ffUL)      /*!< XADDRH (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  HIFEXT0  ======================================================== */
+ #define R_PHOSTIF_HIFEXT0_KESSBI_Pos     (0UL)          /*!< KESSBI (Bit 0)                                        */
+ #define R_PHOSTIF_HIFEXT0_KESSBI_Msk     (0x1UL)        /*!< KESSBI (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFEXT0_KESDTI_Pos     (2UL)          /*!< KESDTI (Bit 2)                                        */
+ #define R_PHOSTIF_HIFEXT0_KESDTI_Msk     (0x4UL)        /*!< KESDTI (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFEXT0_KESAVI_Pos     (3UL)          /*!< KESAVI (Bit 3)                                        */
+ #define R_PHOSTIF_HIFEXT0_KESAVI_Msk     (0x8UL)        /*!< KESAVI (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFEXT0_KESDTO_Pos     (4UL)          /*!< KESDTO (Bit 4)                                        */
+ #define R_PHOSTIF_HIFEXT0_KESDTO_Msk     (0x10UL)       /*!< KESDTO (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFEXT0_KESWTO_Pos     (5UL)          /*!< KESWTO (Bit 5)                                        */
+ #define R_PHOSTIF_HIFEXT0_KESWTO_Msk     (0x20UL)       /*!< KESWTO (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFEXT0_CNDWEO_Pos     (9UL)          /*!< CNDWEO (Bit 9)                                        */
+ #define R_PHOSTIF_HIFEXT0_CNDWEO_Msk     (0x200UL)      /*!< CNDWEO (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_HIFEXT0_MODTRN_Pos     (15UL)         /*!< MODTRN (Bit 15)                                       */
+ #define R_PHOSTIF_HIFEXT0_MODTRN_Msk     (0x8000UL)     /*!< MODTRN (Bitfield-Mask: 0x01)                          */
+/* ========================================================  HIFEXT1  ======================================================== */
+ #define R_PHOSTIF_HIFEXT1_DLYWA_Pos      (0UL)          /*!< DLYWA (Bit 0)                                         */
+ #define R_PHOSTIF_HIFEXT1_DLYWA_Msk      (0xfUL)        /*!< DLYWA (Bitfield-Mask: 0x0f)                           */
+ #define R_PHOSTIF_HIFEXT1_DLYRA_Pos      (8UL)          /*!< DLYRA (Bit 8)                                         */
+ #define R_PHOSTIF_HIFEXT1_DLYRA_Msk      (0xf00UL)      /*!< DLYRA (Bitfield-Mask: 0x0f)                           */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSC_NS                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SCKCR  ========================================================= */
+ #define R_SYSC_NS_SCKCR_FSELXSPI0_Pos       (0UL)          /*!< FSELXSPI0 (Bit 0)                                     */
+ #define R_SYSC_NS_SCKCR_FSELXSPI0_Msk       (0x7UL)        /*!< FSELXSPI0 (Bitfield-Mask: 0x07)                       */
+ #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Pos     (6UL)          /*!< DIVSELXSPI0 (Bit 6)                                   */
+ #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Msk     (0x40UL)       /*!< DIVSELXSPI0 (Bitfield-Mask: 0x01)                     */
+ #define R_SYSC_NS_SCKCR_FSELXSPI1_Pos       (8UL)          /*!< FSELXSPI1 (Bit 8)                                     */
+ #define R_SYSC_NS_SCKCR_FSELXSPI1_Msk       (0x700UL)      /*!< FSELXSPI1 (Bitfield-Mask: 0x07)                       */
+ #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Pos     (14UL)         /*!< DIVSELXSPI1 (Bit 14)                                  */
+ #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Msk     (0x4000UL)     /*!< DIVSELXSPI1 (Bitfield-Mask: 0x01)                     */
+ #define R_SYSC_NS_SCKCR_CKIO_Pos            (16UL)         /*!< CKIO (Bit 16)                                         */
+ #define R_SYSC_NS_SCKCR_CKIO_Msk            (0x70000UL)    /*!< CKIO (Bitfield-Mask: 0x07)                            */
+ #define R_SYSC_NS_SCKCR_FSELCANFD_Pos       (20UL)         /*!< FSELCANFD (Bit 20)                                    */
+ #define R_SYSC_NS_SCKCR_FSELCANFD_Msk       (0x100000UL)   /*!< FSELCANFD (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_SCKCR_PHYSEL_Pos          (21UL)         /*!< PHYSEL (Bit 21)                                       */
+ #define R_SYSC_NS_SCKCR_PHYSEL_Msk          (0x200000UL)   /*!< PHYSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_SCKCR_CLMASEL_Pos         (22UL)         /*!< CLMASEL (Bit 22)                                      */
+ #define R_SYSC_NS_SCKCR_CLMASEL_Msk         (0x400000UL)   /*!< CLMASEL (Bitfield-Mask: 0x01)                         */
+ #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Pos    (24UL)         /*!< SPI0ASYNCSEL (Bit 24)                                 */
+ #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Msk    (0x1000000UL)  /*!< SPI0ASYNCSEL (Bitfield-Mask: 0x01)                    */
+ #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Pos    (25UL)         /*!< SPI1ASYNCSEL (Bit 25)                                 */
+ #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Msk    (0x2000000UL)  /*!< SPI1ASYNCSEL (Bitfield-Mask: 0x01)                    */
+ #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Pos    (26UL)         /*!< SPI2ASYNCSEL (Bit 26)                                 */
+ #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Msk    (0x4000000UL)  /*!< SPI2ASYNCSEL (Bitfield-Mask: 0x01)                    */
+ #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Pos    (27UL)         /*!< SCI0ASYNCSEL (Bit 27)                                 */
+ #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Msk    (0x8000000UL)  /*!< SCI0ASYNCSEL (Bitfield-Mask: 0x01)                    */
+ #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Pos    (28UL)         /*!< SCI1ASYNCSEL (Bit 28)                                 */
+ #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Msk    (0x10000000UL) /*!< SCI1ASYNCSEL (Bitfield-Mask: 0x01)                    */
+ #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Pos    (29UL)         /*!< SCI2ASYNCSEL (Bit 29)                                 */
+ #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Msk    (0x20000000UL) /*!< SCI2ASYNCSEL (Bitfield-Mask: 0x01)                    */
+ #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Pos    (30UL)         /*!< SCI3ASYNCSEL (Bit 30)                                 */
+ #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Msk    (0x40000000UL) /*!< SCI3ASYNCSEL (Bitfield-Mask: 0x01)                    */
+ #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Pos    (31UL)         /*!< SCI4ASYNCSEL (Bit 31)                                 */
+ #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Msk    (0x80000000UL) /*!< SCI4ASYNCSEL (Bitfield-Mask: 0x01)                    */
+/* ========================================================  RSTSR0  ========================================================= */
+ #define R_SYSC_NS_RSTSR0_TRF_Pos            (1UL)          /*!< TRF (Bit 1)                                           */
+ #define R_SYSC_NS_RSTSR0_TRF_Msk            (0x2UL)        /*!< TRF (Bitfield-Mask: 0x01)                             */
+ #define R_SYSC_NS_RSTSR0_ERRF_Pos           (2UL)          /*!< ERRF (Bit 2)                                          */
+ #define R_SYSC_NS_RSTSR0_ERRF_Msk           (0x4UL)        /*!< ERRF (Bitfield-Mask: 0x01)                            */
+ #define R_SYSC_NS_RSTSR0_SWRSF_Pos          (3UL)          /*!< SWRSF (Bit 3)                                         */
+ #define R_SYSC_NS_RSTSR0_SWRSF_Msk          (0x8UL)        /*!< SWRSF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSC_NS_RSTSR0_SWR0F_Pos          (4UL)          /*!< SWR0F (Bit 4)                                         */
+ #define R_SYSC_NS_RSTSR0_SWR0F_Msk          (0x10UL)       /*!< SWR0F (Bitfield-Mask: 0x01)                           */
+/* ========================================================  MRCTLA  ========================================================= */
+ #define R_SYSC_NS_MRCTLA_MRCTLA04_Pos       (4UL)          /*!< MRCTLA04 (Bit 4)                                      */
+ #define R_SYSC_NS_MRCTLA_MRCTLA04_Msk       (0x10UL)       /*!< MRCTLA04 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLA_MRCTLA05_Pos       (5UL)          /*!< MRCTLA05 (Bit 5)                                      */
+ #define R_SYSC_NS_MRCTLA_MRCTLA05_Msk       (0x20UL)       /*!< MRCTLA05 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MRCTLE  ========================================================= */
+ #define R_SYSC_NS_MRCTLE_MRCTLE00_Pos       (0UL)          /*!< MRCTLE00 (Bit 0)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE00_Msk       (0x1UL)        /*!< MRCTLE00 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE01_Pos       (1UL)          /*!< MRCTLE01 (Bit 1)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE01_Msk       (0x2UL)        /*!< MRCTLE01 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE02_Pos       (2UL)          /*!< MRCTLE02 (Bit 2)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE02_Msk       (0x4UL)        /*!< MRCTLE02 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE03_Pos       (3UL)          /*!< MRCTLE03 (Bit 3)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE03_Msk       (0x8UL)        /*!< MRCTLE03 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE04_Pos       (4UL)          /*!< MRCTLE04 (Bit 4)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE04_Msk       (0x10UL)       /*!< MRCTLE04 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE05_Pos       (5UL)          /*!< MRCTLE05 (Bit 5)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE05_Msk       (0x20UL)       /*!< MRCTLE05 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE06_Pos       (6UL)          /*!< MRCTLE06 (Bit 6)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE06_Msk       (0x40UL)       /*!< MRCTLE06 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MSTPCRA  ======================================================== */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Pos     (0UL)          /*!< MSTPCRA00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Msk     (0x1UL)        /*!< MSTPCRA00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Pos     (4UL)          /*!< MSTPCRA04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Msk     (0x10UL)       /*!< MSTPCRA04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Pos     (5UL)          /*!< MSTPCRA05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Msk     (0x20UL)       /*!< MSTPCRA05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Pos     (8UL)          /*!< MSTPCRA08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Msk     (0x100UL)      /*!< MSTPCRA08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Pos     (9UL)          /*!< MSTPCRA09 (Bit 9)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Msk     (0x200UL)      /*!< MSTPCRA09 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Pos     (10UL)         /*!< MSTPCRA10 (Bit 10)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Msk     (0x400UL)      /*!< MSTPCRA10 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Pos     (11UL)         /*!< MSTPCRA11 (Bit 11)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Msk     (0x800UL)      /*!< MSTPCRA11 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Pos     (12UL)         /*!< MSTPCRA12 (Bit 12)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Msk     (0x1000UL)     /*!< MSTPCRA12 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRB  ======================================================== */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Pos     (0UL)          /*!< MSTPCRB00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Msk     (0x1UL)        /*!< MSTPCRB00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Pos     (1UL)          /*!< MSTPCRB01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Msk     (0x2UL)        /*!< MSTPCRB01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Pos     (4UL)          /*!< MSTPCRB04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Msk     (0x10UL)       /*!< MSTPCRB04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Pos     (5UL)          /*!< MSTPCRB05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Msk     (0x20UL)       /*!< MSTPCRB05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Pos     (6UL)          /*!< MSTPCRB06 (Bit 6)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Msk     (0x40UL)       /*!< MSTPCRB06 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRC  ======================================================== */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Pos     (0UL)          /*!< MSTPCRC00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Msk     (0x1UL)        /*!< MSTPCRC00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Pos     (1UL)          /*!< MSTPCRC01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Msk     (0x2UL)        /*!< MSTPCRC01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Pos     (2UL)          /*!< MSTPCRC02 (Bit 2)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Msk     (0x4UL)        /*!< MSTPCRC02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Pos     (5UL)          /*!< MSTPCRC05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Msk     (0x20UL)       /*!< MSTPCRC05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Pos     (6UL)          /*!< MSTPCRC06 (Bit 6)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Msk     (0x40UL)       /*!< MSTPCRC06 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Pos     (7UL)          /*!< MSTPCRC07 (Bit 7)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Msk     (0x80UL)       /*!< MSTPCRC07 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRD  ======================================================== */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Pos     (0UL)          /*!< MSTPCRD00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Msk     (0x1UL)        /*!< MSTPCRD00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Pos     (1UL)          /*!< MSTPCRD01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Msk     (0x2UL)        /*!< MSTPCRD01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Pos     (2UL)          /*!< MSTPCRD02 (Bit 2)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Msk     (0x4UL)        /*!< MSTPCRD02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Pos     (3UL)          /*!< MSTPCRD03 (Bit 3)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Msk     (0x8UL)        /*!< MSTPCRD03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Pos     (4UL)          /*!< MSTPCRD04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Msk     (0x10UL)       /*!< MSTPCRD04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Pos     (5UL)          /*!< MSTPCRD05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Msk     (0x20UL)       /*!< MSTPCRD05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Pos     (6UL)          /*!< MSTPCRD06 (Bit 6)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Msk     (0x40UL)       /*!< MSTPCRD06 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Pos     (7UL)          /*!< MSTPCRD07 (Bit 7)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Msk     (0x80UL)       /*!< MSTPCRD07 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Pos     (8UL)          /*!< MSTPCRD08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Msk     (0x100UL)      /*!< MSTPCRD08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Pos     (9UL)          /*!< MSTPCRD09 (Bit 9)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Msk     (0x200UL)      /*!< MSTPCRD09 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Pos     (10UL)         /*!< MSTPCRD10 (Bit 10)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Msk     (0x400UL)      /*!< MSTPCRD10 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Pos     (11UL)         /*!< MSTPCRD11 (Bit 11)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Msk     (0x800UL)      /*!< MSTPCRD11 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRE  ======================================================== */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Pos     (0UL)          /*!< MSTPCRE00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Msk     (0x1UL)        /*!< MSTPCRE00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Pos     (1UL)          /*!< MSTPCRE01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Msk     (0x2UL)        /*!< MSTPCRE01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Pos     (2UL)          /*!< MSTPCRE02 (Bit 2)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Msk     (0x4UL)        /*!< MSTPCRE02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Pos     (3UL)          /*!< MSTPCRE03 (Bit 3)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Msk     (0x8UL)        /*!< MSTPCRE03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Pos     (8UL)          /*!< MSTPCRE08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Msk     (0x100UL)      /*!< MSTPCRE08 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MD_MON  ========================================================= */
+ #define R_SYSC_NS_MD_MON_MDDMON_Pos         (0UL)          /*!< MDDMON (Bit 0)                                        */
+ #define R_SYSC_NS_MD_MON_MDDMON_Msk         (0x1UL)        /*!< MDDMON (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_MD_MON_MDP_Pos            (8UL)          /*!< MDP (Bit 8)                                           */
+ #define R_SYSC_NS_MD_MON_MDP_Msk            (0x100UL)      /*!< MDP (Bitfield-Mask: 0x01)                             */
+ #define R_SYSC_NS_MD_MON_MD0MON_Pos         (12UL)         /*!< MD0MON (Bit 12)                                       */
+ #define R_SYSC_NS_MD_MON_MD0MON_Msk         (0x1000UL)     /*!< MD0MON (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_MD_MON_MD1MON_Pos         (13UL)         /*!< MD1MON (Bit 13)                                       */
+ #define R_SYSC_NS_MD_MON_MD1MON_Msk         (0x2000UL)     /*!< MD1MON (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_MD_MON_MD2MON_Pos         (14UL)         /*!< MD2MON (Bit 14)                                       */
+ #define R_SYSC_NS_MD_MON_MD2MON_Msk         (0x4000UL)     /*!< MD2MON (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_MD_MON_MDV0MON_Pos        (16UL)         /*!< MDV0MON (Bit 16)                                      */
+ #define R_SYSC_NS_MD_MON_MDV0MON_Msk        (0x10000UL)    /*!< MDV0MON (Bitfield-Mask: 0x01)                         */
+ #define R_SYSC_NS_MD_MON_MDV1MON_Pos        (17UL)         /*!< MDV1MON (Bit 17)                                      */
+ #define R_SYSC_NS_MD_MON_MDV1MON_Msk        (0x20000UL)    /*!< MDV1MON (Bitfield-Mask: 0x01)                         */
+ #define R_SYSC_NS_MD_MON_MDV2MON_Pos        (18UL)         /*!< MDV2MON (Bit 18)                                      */
+ #define R_SYSC_NS_MD_MON_MDV2MON_Msk        (0x40000UL)    /*!< MDV2MON (Bitfield-Mask: 0x01)                         */
+ #define R_SYSC_NS_MD_MON_MDV3MON_Pos        (19UL)         /*!< MDV3MON (Bit 19)                                      */
+ #define R_SYSC_NS_MD_MON_MDV3MON_Msk        (0x80000UL)    /*!< MDV3MON (Bitfield-Mask: 0x01)                         */
+ #define R_SYSC_NS_MD_MON_MDV4MON_Pos        (20UL)         /*!< MDV4MON (Bit 20)                                      */
+ #define R_SYSC_NS_MD_MON_MDV4MON_Msk        (0x100000UL)   /*!< MDV4MON (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELO                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ELOPA  ========================================================= */
+ #define R_ELO_ELOPA_MTU0MD_Pos    (0UL)    /*!< MTU0MD (Bit 0)                                        */
+ #define R_ELO_ELOPA_MTU0MD_Msk    (0x3UL)  /*!< MTU0MD (Bitfield-Mask: 0x03)                          */
+ #define R_ELO_ELOPA_MTU3MD_Pos    (6UL)    /*!< MTU3MD (Bit 6)                                        */
+ #define R_ELO_ELOPA_MTU3MD_Msk    (0xc0UL) /*!< MTU3MD (Bitfield-Mask: 0x03)                          */
+/* =========================================================  ELOPB  ========================================================= */
+ #define R_ELO_ELOPB_MTU4MD_Pos    (0UL)    /*!< MTU4MD (Bit 0)                                        */
+ #define R_ELO_ELOPB_MTU4MD_Msk    (0x3UL)  /*!< MTU4MD (Bitfield-Mask: 0x03)                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_RWP_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PRCRN  ========================================================= */
+ #define R_RWP_NS_PRCRN_PRC0_Pos     (0UL)      /*!< PRC0 (Bit 0)                                          */
+ #define R_RWP_NS_PRCRN_PRC0_Msk     (0x1UL)    /*!< PRC0 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_NS_PRCRN_PRC1_Pos     (1UL)      /*!< PRC1 (Bit 1)                                          */
+ #define R_RWP_NS_PRCRN_PRC1_Msk     (0x2UL)    /*!< PRC1 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_NS_PRCRN_PRC2_Pos     (2UL)      /*!< PRC2 (Bit 2)                                          */
+ #define R_RWP_NS_PRCRN_PRC2_Msk     (0x4UL)    /*!< PRC2 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_NS_PRCRN_PRKEY_Pos    (8UL)      /*!< PRKEY (Bit 8)                                         */
+ #define R_RWP_NS_PRCRN_PRKEY_Msk    (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  RTCA0CTL0  ======================================================= */
+ #define R_RTC_RTCA0CTL0_RTCA0SLSB_Pos      (4UL)          /*!< RTCA0SLSB (Bit 4)                                     */
+ #define R_RTC_RTCA0CTL0_RTCA0SLSB_Msk      (0x10UL)       /*!< RTCA0SLSB (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL0_RTCA0AMPM_Pos      (5UL)          /*!< RTCA0AMPM (Bit 5)                                     */
+ #define R_RTC_RTCA0CTL0_RTCA0AMPM_Msk      (0x20UL)       /*!< RTCA0AMPM (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL0_RTCA0CEST_Pos      (6UL)          /*!< RTCA0CEST (Bit 6)                                     */
+ #define R_RTC_RTCA0CTL0_RTCA0CEST_Msk      (0x40UL)       /*!< RTCA0CEST (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL0_RTCA0CE_Pos        (7UL)          /*!< RTCA0CE (Bit 7)                                       */
+ #define R_RTC_RTCA0CTL0_RTCA0CE_Msk        (0x80UL)       /*!< RTCA0CE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  RTCA0CTL1  ======================================================= */
+ #define R_RTC_RTCA0CTL1_RTCA0CT_Pos        (0UL)          /*!< RTCA0CT (Bit 0)                                       */
+ #define R_RTC_RTCA0CTL1_RTCA0CT_Msk        (0x7UL)        /*!< RTCA0CT (Bitfield-Mask: 0x07)                         */
+ #define R_RTC_RTCA0CTL1_RTCA01SE_Pos       (3UL)          /*!< RTCA01SE (Bit 3)                                      */
+ #define R_RTC_RTCA0CTL1_RTCA01SE_Msk       (0x8UL)        /*!< RTCA01SE (Bitfield-Mask: 0x01)                        */
+ #define R_RTC_RTCA0CTL1_RTCA0ALME_Pos      (4UL)          /*!< RTCA0ALME (Bit 4)                                     */
+ #define R_RTC_RTCA0CTL1_RTCA0ALME_Msk      (0x10UL)       /*!< RTCA0ALME (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL1_RTCA01HZE_Pos      (5UL)          /*!< RTCA01HZE (Bit 5)                                     */
+ #define R_RTC_RTCA0CTL1_RTCA01HZE_Msk      (0x20UL)       /*!< RTCA01HZE (Bitfield-Mask: 0x01)                       */
+/* =======================================================  RTCA0CTL2  ======================================================= */
+ #define R_RTC_RTCA0CTL2_RTCA0WAIT_Pos      (0UL)          /*!< RTCA0WAIT (Bit 0)                                     */
+ #define R_RTC_RTCA0CTL2_RTCA0WAIT_Msk      (0x1UL)        /*!< RTCA0WAIT (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL2_RTCA0WST_Pos       (1UL)          /*!< RTCA0WST (Bit 1)                                      */
+ #define R_RTC_RTCA0CTL2_RTCA0WST_Msk       (0x2UL)        /*!< RTCA0WST (Bitfield-Mask: 0x01)                        */
+ #define R_RTC_RTCA0CTL2_RTCA0RSUB_Pos      (2UL)          /*!< RTCA0RSUB (Bit 2)                                     */
+ #define R_RTC_RTCA0CTL2_RTCA0RSUB_Msk      (0x4UL)        /*!< RTCA0RSUB (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL2_RTCA0RSST_Pos      (3UL)          /*!< RTCA0RSST (Bit 3)                                     */
+ #define R_RTC_RTCA0CTL2_RTCA0RSST_Msk      (0x8UL)        /*!< RTCA0RSST (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL2_RTCA0WSST_Pos      (4UL)          /*!< RTCA0WSST (Bit 4)                                     */
+ #define R_RTC_RTCA0CTL2_RTCA0WSST_Msk      (0x10UL)       /*!< RTCA0WSST (Bitfield-Mask: 0x01)                       */
+/* =======================================================  RTCA0SUBC  ======================================================= */
+ #define R_RTC_RTCA0SUBC_RTCA0SUBC_Pos      (0UL)          /*!< RTCA0SUBC (Bit 0)                                     */
+ #define R_RTC_RTCA0SUBC_RTCA0SUBC_Msk      (0x3fffffUL)   /*!< RTCA0SUBC (Bitfield-Mask: 0x3fffff)                   */
+/* =======================================================  RTCA0SRBU  ======================================================= */
+ #define R_RTC_RTCA0SRBU_RTCA0SRBU_Pos      (0UL)          /*!< RTCA0SRBU (Bit 0)                                     */
+ #define R_RTC_RTCA0SRBU_RTCA0SRBU_Msk      (0x3fffffUL)   /*!< RTCA0SRBU (Bitfield-Mask: 0x3fffff)                   */
+/* =======================================================  RTCA0SEC  ======================================================== */
+ #define R_RTC_RTCA0SEC_RTCA0SEC_Pos        (0UL)          /*!< RTCA0SEC (Bit 0)                                      */
+ #define R_RTC_RTCA0SEC_RTCA0SEC_Msk        (0x7fUL)       /*!< RTCA0SEC (Bitfield-Mask: 0x7f)                        */
+/* =======================================================  RTCA0MIN  ======================================================== */
+ #define R_RTC_RTCA0MIN_RTCA0MIN_Pos        (0UL)          /*!< RTCA0MIN (Bit 0)                                      */
+ #define R_RTC_RTCA0MIN_RTCA0MIN_Msk        (0x7fUL)       /*!< RTCA0MIN (Bitfield-Mask: 0x7f)                        */
+/* =======================================================  RTCA0HOUR  ======================================================= */
+ #define R_RTC_RTCA0HOUR_RTCA0HOUR_Pos      (0UL)          /*!< RTCA0HOUR (Bit 0)                                     */
+ #define R_RTC_RTCA0HOUR_RTCA0HOUR_Msk      (0x3fUL)       /*!< RTCA0HOUR (Bitfield-Mask: 0x3f)                       */
+/* =======================================================  RTCA0WEEK  ======================================================= */
+ #define R_RTC_RTCA0WEEK_RTCA0WEEK_Pos      (0UL)          /*!< RTCA0WEEK (Bit 0)                                     */
+ #define R_RTC_RTCA0WEEK_RTCA0WEEK_Msk      (0x7UL)        /*!< RTCA0WEEK (Bitfield-Mask: 0x07)                       */
+/* =======================================================  RTCA0DAY  ======================================================== */
+ #define R_RTC_RTCA0DAY_RTCA0DAY_Pos        (0UL)          /*!< RTCA0DAY (Bit 0)                                      */
+ #define R_RTC_RTCA0DAY_RTCA0DAY_Msk        (0x3fUL)       /*!< RTCA0DAY (Bitfield-Mask: 0x3f)                        */
+/* ======================================================  RTCA0MONTH  ======================================================= */
+ #define R_RTC_RTCA0MONTH_RTCA0MONTH_Pos    (0UL)          /*!< RTCA0MONTH (Bit 0)                                    */
+ #define R_RTC_RTCA0MONTH_RTCA0MONTH_Msk    (0x1fUL)       /*!< RTCA0MONTH (Bitfield-Mask: 0x1f)                      */
+/* =======================================================  RTCA0YEAR  ======================================================= */
+ #define R_RTC_RTCA0YEAR_RTCA0YEAR_Pos      (0UL)          /*!< RTCA0YEAR (Bit 0)                                     */
+ #define R_RTC_RTCA0YEAR_RTCA0YEAR_Msk      (0xffUL)       /*!< RTCA0YEAR (Bitfield-Mask: 0xff)                       */
+/* =======================================================  RTCA0TIME  ======================================================= */
+ #define R_RTC_RTCA0TIME_RTCA0SEC_Pos       (0UL)          /*!< RTCA0SEC (Bit 0)                                      */
+ #define R_RTC_RTCA0TIME_RTCA0SEC_Msk       (0xffUL)       /*!< RTCA0SEC (Bitfield-Mask: 0xff)                        */
+ #define R_RTC_RTCA0TIME_RTCA0MIN_Pos       (8UL)          /*!< RTCA0MIN (Bit 8)                                      */
+ #define R_RTC_RTCA0TIME_RTCA0MIN_Msk       (0xff00UL)     /*!< RTCA0MIN (Bitfield-Mask: 0xff)                        */
+ #define R_RTC_RTCA0TIME_RTCA0HOUR_Pos      (16UL)         /*!< RTCA0HOUR (Bit 16)                                    */
+ #define R_RTC_RTCA0TIME_RTCA0HOUR_Msk      (0xff0000UL)   /*!< RTCA0HOUR (Bitfield-Mask: 0xff)                       */
+/* =======================================================  RTCA0CAL  ======================================================== */
+ #define R_RTC_RTCA0CAL_RTCA0WEEK_Pos       (0UL)          /*!< RTCA0WEEK (Bit 0)                                     */
+ #define R_RTC_RTCA0CAL_RTCA0WEEK_Msk       (0xffUL)       /*!< RTCA0WEEK (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0CAL_RTCA0DAY_Pos        (8UL)          /*!< RTCA0DAY (Bit 8)                                      */
+ #define R_RTC_RTCA0CAL_RTCA0DAY_Msk        (0xff00UL)     /*!< RTCA0DAY (Bitfield-Mask: 0xff)                        */
+ #define R_RTC_RTCA0CAL_RTCA0MONTH_Pos      (16UL)         /*!< RTCA0MONTH (Bit 16)                                   */
+ #define R_RTC_RTCA0CAL_RTCA0MONTH_Msk      (0xff0000UL)   /*!< RTCA0MONTH (Bitfield-Mask: 0xff)                      */
+ #define R_RTC_RTCA0CAL_RTCA0YEAR_Pos       (24UL)         /*!< RTCA0YEAR (Bit 24)                                    */
+ #define R_RTC_RTCA0CAL_RTCA0YEAR_Msk       (0xff000000UL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff)                       */
+/* =======================================================  RTCA0SCMP  ======================================================= */
+ #define R_RTC_RTCA0SCMP_RTCA0SCMP_Pos      (0UL)          /*!< RTCA0SCMP (Bit 0)                                     */
+ #define R_RTC_RTCA0SCMP_RTCA0SCMP_Msk      (0x3fffffUL)   /*!< RTCA0SCMP (Bitfield-Mask: 0x3fffff)                   */
+/* =======================================================  RTCA0ALM  ======================================================== */
+ #define R_RTC_RTCA0ALM_RTCA0ALM_Pos        (0UL)          /*!< RTCA0ALM (Bit 0)                                      */
+ #define R_RTC_RTCA0ALM_RTCA0ALM_Msk        (0x7fUL)       /*!< RTCA0ALM (Bitfield-Mask: 0x7f)                        */
+/* =======================================================  RTCA0ALH  ======================================================== */
+ #define R_RTC_RTCA0ALH_RTCA0ALH_Pos        (0UL)          /*!< RTCA0ALH (Bit 0)                                      */
+ #define R_RTC_RTCA0ALH_RTCA0ALH_Msk        (0x3fUL)       /*!< RTCA0ALH (Bitfield-Mask: 0x3f)                        */
+/* =======================================================  RTCA0ALW  ======================================================== */
+ #define R_RTC_RTCA0ALW_RTCA0ALW0_Pos       (0UL)          /*!< RTCA0ALW0 (Bit 0)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW0_Msk       (0x1UL)        /*!< RTCA0ALW0 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW1_Pos       (1UL)          /*!< RTCA0ALW1 (Bit 1)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW1_Msk       (0x2UL)        /*!< RTCA0ALW1 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW2_Pos       (2UL)          /*!< RTCA0ALW2 (Bit 2)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW2_Msk       (0x4UL)        /*!< RTCA0ALW2 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW3_Pos       (3UL)          /*!< RTCA0ALW3 (Bit 3)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW3_Msk       (0x8UL)        /*!< RTCA0ALW3 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW4_Pos       (4UL)          /*!< RTCA0ALW4 (Bit 4)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW4_Msk       (0x10UL)       /*!< RTCA0ALW4 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW5_Pos       (5UL)          /*!< RTCA0ALW5 (Bit 5)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW5_Msk       (0x20UL)       /*!< RTCA0ALW5 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW6_Pos       (6UL)          /*!< RTCA0ALW6 (Bit 6)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW6_Msk       (0x40UL)       /*!< RTCA0ALW6 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  RTCA0SECC  ======================================================= */
+ #define R_RTC_RTCA0SECC_RTCA0SECC_Pos      (0UL)          /*!< RTCA0SECC (Bit 0)                                     */
+ #define R_RTC_RTCA0SECC_RTCA0SECC_Msk      (0x7fUL)       /*!< RTCA0SECC (Bitfield-Mask: 0x7f)                       */
+/* =======================================================  RTCA0MINC  ======================================================= */
+ #define R_RTC_RTCA0MINC_RTCA0MINC_Pos      (0UL)          /*!< RTCA0MINC (Bit 0)                                     */
+ #define R_RTC_RTCA0MINC_RTCA0MINC_Msk      (0x7fUL)       /*!< RTCA0MINC (Bitfield-Mask: 0x7f)                       */
+/* ======================================================  RTCA0HOURC  ======================================================= */
+ #define R_RTC_RTCA0HOURC_RTCA0HOURC_Pos    (0UL)          /*!< RTCA0HOURC (Bit 0)                                    */
+ #define R_RTC_RTCA0HOURC_RTCA0HOURC_Msk    (0x3fUL)       /*!< RTCA0HOURC (Bitfield-Mask: 0x3f)                      */
+/* ======================================================  RTCA0WEEKC  ======================================================= */
+ #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Pos    (0UL)          /*!< RTCA0WEEKC (Bit 0)                                    */
+ #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Msk    (0x7UL)        /*!< RTCA0WEEKC (Bitfield-Mask: 0x07)                      */
+/* =======================================================  RTCA0DAYC  ======================================================= */
+ #define R_RTC_RTCA0DAYC_RTCA0DAYC_Pos      (0UL)          /*!< RTCA0DAYC (Bit 0)                                     */
+ #define R_RTC_RTCA0DAYC_RTCA0DAYC_Msk      (0x3fUL)       /*!< RTCA0DAYC (Bitfield-Mask: 0x3f)                       */
+/* =======================================================  RTCA0MONC  ======================================================= */
+ #define R_RTC_RTCA0MONC_RTCA0MONC_Pos      (0UL)          /*!< RTCA0MONC (Bit 0)                                     */
+ #define R_RTC_RTCA0MONC_RTCA0MONC_Msk      (0x1fUL)       /*!< RTCA0MONC (Bitfield-Mask: 0x1f)                       */
+/* ======================================================  RTCA0YEARC  ======================================================= */
+ #define R_RTC_RTCA0YEARC_RTCA0YEARC_Pos    (0UL)          /*!< RTCA0YEARC (Bit 0)                                    */
+ #define R_RTC_RTCA0YEARC_RTCA0YEARC_Msk    (0xffUL)       /*!< RTCA0YEARC (Bitfield-Mask: 0xff)                      */
+/* ======================================================  RTCA0TIMEC  ======================================================= */
+ #define R_RTC_RTCA0TIMEC_RTCA0SECC_Pos     (0UL)          /*!< RTCA0SECC (Bit 0)                                     */
+ #define R_RTC_RTCA0TIMEC_RTCA0SECC_Msk     (0xffUL)       /*!< RTCA0SECC (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0TIMEC_RTCA0MINC_Pos     (8UL)          /*!< RTCA0MINC (Bit 8)                                     */
+ #define R_RTC_RTCA0TIMEC_RTCA0MINC_Msk     (0xff00UL)     /*!< RTCA0MINC (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Pos    (16UL)         /*!< RTCA0HOURC (Bit 16)                                   */
+ #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Msk    (0xff0000UL)   /*!< RTCA0HOURC (Bitfield-Mask: 0xff)                      */
+/* =======================================================  RTCA0CALC  ======================================================= */
+ #define R_RTC_RTCA0CALC_RTCA0WEEKC_Pos     (0UL)          /*!< RTCA0WEEKC (Bit 0)                                    */
+ #define R_RTC_RTCA0CALC_RTCA0WEEKC_Msk     (0xffUL)       /*!< RTCA0WEEKC (Bitfield-Mask: 0xff)                      */
+ #define R_RTC_RTCA0CALC_RTCA0DAYC_Pos      (8UL)          /*!< RTCA0DAYC (Bit 8)                                     */
+ #define R_RTC_RTCA0CALC_RTCA0DAYC_Msk      (0xff00UL)     /*!< RTCA0DAYC (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0CALC_RTCA0MONC_Pos      (16UL)         /*!< RTCA0MONC (Bit 16)                                    */
+ #define R_RTC_RTCA0CALC_RTCA0MONC_Msk      (0xff0000UL)   /*!< RTCA0MONC (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0CALC_RTCA0YEARC_Pos     (24UL)         /*!< RTCA0YEARC (Bit 24)                                   */
+ #define R_RTC_RTCA0CALC_RTCA0YEARC_Msk     (0xff000000UL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG2                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  POEG2GA  ======================================================== */
+ #define R_POEG2_POEG2GA_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG2_POEG2GA_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG2_POEG2GA_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG2_POEG2GA_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GA_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG2_POEG2GA_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GA_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG2_POEG2GA_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG2_POEG2GA_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG2_POEG2GA_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GA_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG2_POEG2GA_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG2_POEG2GA_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG2_POEG2GA_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GA_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG2_POEG2GA_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG2_POEG2GA_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG2GB  ======================================================== */
+ #define R_POEG2_POEG2GB_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG2_POEG2GB_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG2_POEG2GB_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG2_POEG2GB_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GB_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG2_POEG2GB_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GB_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG2_POEG2GB_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG2_POEG2GB_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG2_POEG2GB_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GB_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG2_POEG2GB_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG2_POEG2GB_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG2_POEG2GB_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GB_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG2_POEG2GB_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG2_POEG2GB_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG2GC  ======================================================== */
+ #define R_POEG2_POEG2GC_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG2_POEG2GC_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG2_POEG2GC_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG2_POEG2GC_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GC_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG2_POEG2GC_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GC_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG2_POEG2GC_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG2_POEG2GC_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG2_POEG2GC_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GC_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG2_POEG2GC_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG2_POEG2GC_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG2_POEG2GC_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GC_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG2_POEG2GC_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG2_POEG2GC_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG2GD  ======================================================== */
+ #define R_POEG2_POEG2GD_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG2_POEG2GD_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG2_POEG2GD_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG2_POEG2GD_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GD_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG2_POEG2GD_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GD_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG2_POEG2GD_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG2_POEG2GD_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG2_POEG2GD_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GD_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG2_POEG2GD_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG2_POEG2GD_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG2_POEG2GD_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GD_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG2_POEG2GD_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG2_POEG2GD_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_OTP                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  OTPPWR  ========================================================= */
+ #define R_OTP_OTPPWR_PWR_Pos            (0UL)      /*!< PWR (Bit 0)                                           */
+ #define R_OTP_OTPPWR_PWR_Msk            (0x1UL)    /*!< PWR (Bitfield-Mask: 0x01)                             */
+ #define R_OTP_OTPPWR_ACCL_Pos           (4UL)      /*!< ACCL (Bit 4)                                          */
+ #define R_OTP_OTPPWR_ACCL_Msk           (0x10UL)   /*!< ACCL (Bitfield-Mask: 0x01)                            */
+/* ========================================================  OTPSTR  ========================================================= */
+ #define R_OTP_OTPSTR_CMD_RDY_Pos        (0UL)      /*!< CMD_RDY (Bit 0)                                       */
+ #define R_OTP_OTPSTR_CMD_RDY_Msk        (0x1UL)    /*!< CMD_RDY (Bitfield-Mask: 0x01)                         */
+ #define R_OTP_OTPSTR_ERR_WR_Pos         (1UL)      /*!< ERR_WR (Bit 1)                                        */
+ #define R_OTP_OTPSTR_ERR_WR_Msk         (0x6UL)    /*!< ERR_WR (Bitfield-Mask: 0x03)                          */
+ #define R_OTP_OTPSTR_ERR_WP_Pos         (3UL)      /*!< ERR_WP (Bit 3)                                        */
+ #define R_OTP_OTPSTR_ERR_WP_Msk         (0x8UL)    /*!< ERR_WP (Bitfield-Mask: 0x01)                          */
+ #define R_OTP_OTPSTR_ERR_RP_Pos         (4UL)      /*!< ERR_RP (Bit 4)                                        */
+ #define R_OTP_OTPSTR_ERR_RP_Msk         (0x10UL)   /*!< ERR_RP (Bitfield-Mask: 0x01)                          */
+ #define R_OTP_OTPSTR_ERR_RDY_WR_Pos     (8UL)      /*!< ERR_RDY_WR (Bit 8)                                    */
+ #define R_OTP_OTPSTR_ERR_RDY_WR_Msk     (0x100UL)  /*!< ERR_RDY_WR (Bitfield-Mask: 0x01)                      */
+ #define R_OTP_OTPSTR_ERR_RDY_RD_Pos     (9UL)      /*!< ERR_RDY_RD (Bit 9)                                    */
+ #define R_OTP_OTPSTR_ERR_RDY_RD_Msk     (0x200UL)  /*!< ERR_RDY_RD (Bitfield-Mask: 0x01)                      */
+ #define R_OTP_OTPSTR_CNT_ST_IDLE_Pos    (15UL)     /*!< CNT_ST_IDLE (Bit 15)                                  */
+ #define R_OTP_OTPSTR_CNT_ST_IDLE_Msk    (0x8000UL) /*!< CNT_ST_IDLE (Bitfield-Mask: 0x01)                     */
+/* =======================================================  OTPSTAWR  ======================================================== */
+ #define R_OTP_OTPSTAWR_STAWR_Pos        (0UL)      /*!< STAWR (Bit 0)                                         */
+ #define R_OTP_OTPSTAWR_STAWR_Msk        (0x1UL)    /*!< STAWR (Bitfield-Mask: 0x01)                           */
+/* =======================================================  OTPADRWR  ======================================================== */
+ #define R_OTP_OTPADRWR_ADRWR_Pos        (0UL)      /*!< ADRWR (Bit 0)                                         */
+ #define R_OTP_OTPADRWR_ADRWR_Msk        (0x1ffUL)  /*!< ADRWR (Bitfield-Mask: 0x1ff)                          */
+/* =======================================================  OTPDATAWR  ======================================================= */
+ #define R_OTP_OTPDATAWR_DATAWR_Pos      (0UL)      /*!< DATAWR (Bit 0)                                        */
+ #define R_OTP_OTPDATAWR_DATAWR_Msk      (0xffffUL) /*!< DATAWR (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  OTPADRRD  ======================================================== */
+ #define R_OTP_OTPADRRD_ADRRD_Pos        (0UL)      /*!< ADRRD (Bit 0)                                         */
+ #define R_OTP_OTPADRRD_ADRRD_Msk        (0x1ffUL)  /*!< ADRRD (Bitfield-Mask: 0x1ff)                          */
+/* =======================================================  OTPDATARD  ======================================================= */
+ #define R_OTP_OTPDATARD_DATARD_Pos      (0UL)      /*!< DATARD (Bit 0)                                        */
+ #define R_OTP_OTPDATARD_DATARD_Msk      (0xffffUL) /*!< DATARD (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PTADR                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  RSELP  ========================================================= */
+ #define R_PTADR_RSELP_RS0_Pos    (0UL)    /*!< RS0 (Bit 0)                                           */
+ #define R_PTADR_RSELP_RS0_Msk    (0x1UL)  /*!< RS0 (Bitfield-Mask: 0x01)                             */
+ #define R_PTADR_RSELP_RS1_Pos    (1UL)    /*!< RS1 (Bit 1)                                           */
+ #define R_PTADR_RSELP_RS1_Msk    (0x2UL)  /*!< RS1 (Bitfield-Mask: 0x01)                             */
+ #define R_PTADR_RSELP_RS2_Pos    (2UL)    /*!< RS2 (Bit 2)                                           */
+ #define R_PTADR_RSELP_RS2_Msk    (0x4UL)  /*!< RS2 (Bitfield-Mask: 0x01)                             */
+ #define R_PTADR_RSELP_RS3_Pos    (3UL)    /*!< RS3 (Bit 3)                                           */
+ #define R_PTADR_RSELP_RS3_Msk    (0x8UL)  /*!< RS3 (Bitfield-Mask: 0x01)                             */
+ #define R_PTADR_RSELP_RS4_Pos    (4UL)    /*!< RS4 (Bit 4)                                           */
+ #define R_PTADR_RSELP_RS4_Msk    (0x10UL) /*!< RS4 (Bitfield-Mask: 0x01)                             */
+ #define R_PTADR_RSELP_RS5_Pos    (5UL)    /*!< RS5 (Bit 5)                                           */
+ #define R_PTADR_RSELP_RS5_Msk    (0x20UL) /*!< RS5 (Bitfield-Mask: 0x01)                             */
+ #define R_PTADR_RSELP_RS6_Pos    (6UL)    /*!< RS6 (Bit 6)                                           */
+ #define R_PTADR_RSELP_RS6_Msk    (0x40UL) /*!< RS6 (Bitfield-Mask: 0x01)                             */
+ #define R_PTADR_RSELP_RS7_Pos    (7UL)    /*!< RS7 (Bit 7)                                           */
+ #define R_PTADR_RSELP_RS7_Msk    (0x80UL) /*!< RS7 (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSRAM0                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ICU                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  S_SWINT  ======================================================== */
+ #define R_ICU_S_SWINT_IC6_Pos                 (0UL)          /*!< IC6 (Bit 0)                                           */
+ #define R_ICU_S_SWINT_IC6_Msk                 (0x1UL)        /*!< IC6 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_S_SWINT_IC7_Pos                 (1UL)          /*!< IC7 (Bit 1)                                           */
+ #define R_ICU_S_SWINT_IC7_Msk                 (0x2UL)        /*!< IC7 (Bitfield-Mask: 0x01)                             */
+/* ====================================================  S_PORTNF_FLTSEL  ==================================================== */
+ #define R_ICU_S_PORTNF_FLTSEL_FLT14_Pos       (0UL)          /*!< FLT14 (Bit 0)                                         */
+ #define R_ICU_S_PORTNF_FLTSEL_FLT14_Msk       (0x1UL)        /*!< FLT14 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_S_PORTNF_FLTSEL_FLT15_Pos       (1UL)          /*!< FLT15 (Bit 1)                                         */
+ #define R_ICU_S_PORTNF_FLTSEL_FLT15_Msk       (0x2UL)        /*!< FLT15 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Pos      (2UL)          /*!< FLTNMI (Bit 2)                                        */
+ #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Msk      (0x4UL)        /*!< FLTNMI (Bitfield-Mask: 0x01)                          */
+/* ====================================================  S_PORTNF_CLKSEL  ==================================================== */
+ #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Pos     (0UL)          /*!< CKSEL14 (Bit 0)                                       */
+ #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Msk     (0x3UL)        /*!< CKSEL14 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Pos     (2UL)          /*!< CKSEL15 (Bit 2)                                       */
+ #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Msk     (0xcUL)        /*!< CKSEL15 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Pos    (4UL)          /*!< CKSELNMI (Bit 4)                                      */
+ #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Msk    (0x30UL)       /*!< CKSELNMI (Bitfield-Mask: 0x03)                        */
+/* ======================================================  S_PORTNF_MD  ====================================================== */
+ #define R_ICU_S_PORTNF_MD_MD14_Pos            (0UL)          /*!< MD14 (Bit 0)                                          */
+ #define R_ICU_S_PORTNF_MD_MD14_Msk            (0x3UL)        /*!< MD14 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_S_PORTNF_MD_MD15_Pos            (2UL)          /*!< MD15 (Bit 2)                                          */
+ #define R_ICU_S_PORTNF_MD_MD15_Msk            (0xcUL)        /*!< MD15 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_S_PORTNF_MD_MDNMI_Pos           (4UL)          /*!< MDNMI (Bit 4)                                         */
+ #define R_ICU_S_PORTNF_MD_MDNMI_Msk           (0x30UL)       /*!< MDNMI (Bitfield-Mask: 0x03)                           */
+/* =====================================================  CPU0ERR_STAT  ====================================================== */
+ #define R_ICU_CPU0ERR_STAT_ER_ST0_Pos         (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST0_Msk         (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST1_Pos         (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST1_Msk         (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST2_Pos         (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST2_Msk         (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST3_Pos         (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST3_Msk         (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST4_Pos         (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST4_Msk         (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST5_Pos         (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST5_Msk         (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST6_Pos         (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST6_Msk         (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST7_Pos         (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST7_Msk         (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST8_Pos         (8UL)          /*!< ER_ST8 (Bit 8)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST8_Msk         (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST9_Pos         (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_CPU0ERR_STAT_ER_ST9_Msk         (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_STAT_ER_ST10_Pos        (10UL)         /*!< ER_ST10 (Bit 10)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST10_Msk        (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST11_Pos        (11UL)         /*!< ER_ST11 (Bit 11)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST11_Msk        (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST12_Pos        (12UL)         /*!< ER_ST12 (Bit 12)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST12_Msk        (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST13_Pos        (13UL)         /*!< ER_ST13 (Bit 13)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST13_Msk        (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST14_Pos        (14UL)         /*!< ER_ST14 (Bit 14)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST14_Msk        (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST15_Pos        (15UL)         /*!< ER_ST15 (Bit 15)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST15_Msk        (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST16_Pos        (16UL)         /*!< ER_ST16 (Bit 16)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST16_Msk        (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST17_Pos        (17UL)         /*!< ER_ST17 (Bit 17)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST17_Msk        (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST18_Pos        (18UL)         /*!< ER_ST18 (Bit 18)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST18_Msk        (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST19_Pos        (19UL)         /*!< ER_ST19 (Bit 19)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST19_Msk        (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST20_Pos        (20UL)         /*!< ER_ST20 (Bit 20)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST20_Msk        (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST21_Pos        (21UL)         /*!< ER_ST21 (Bit 21)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST21_Msk        (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST22_Pos        (22UL)         /*!< ER_ST22 (Bit 22)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST22_Msk        (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST23_Pos        (23UL)         /*!< ER_ST23 (Bit 23)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST23_Msk        (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST24_Pos        (24UL)         /*!< ER_ST24 (Bit 24)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST24_Msk        (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_STAT_ER_ST25_Pos        (25UL)         /*!< ER_ST25 (Bit 25)                                      */
+ #define R_ICU_CPU0ERR_STAT_ER_ST25_Msk        (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  PERIERR_STAT0  ===================================================== */
+ #define R_ICU_PERIERR_STAT0_ER_ST0_Pos        (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST0_Msk        (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST1_Pos        (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST1_Msk        (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST2_Pos        (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST2_Msk        (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST3_Pos        (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST3_Msk        (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST4_Pos        (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST4_Msk        (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST5_Pos        (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST5_Msk        (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST6_Pos        (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST6_Msk        (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST7_Pos        (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST7_Msk        (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST9_Pos        (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_STAT0_ER_ST9_Msk        (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT0_ER_ST10_Pos       (10UL)         /*!< ER_ST10 (Bit 10)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST10_Msk       (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST11_Pos       (11UL)         /*!< ER_ST11 (Bit 11)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST11_Msk       (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST12_Pos       (12UL)         /*!< ER_ST12 (Bit 12)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST12_Msk       (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST13_Pos       (13UL)         /*!< ER_ST13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST13_Msk       (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST14_Pos       (14UL)         /*!< ER_ST14 (Bit 14)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST14_Msk       (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST15_Pos       (15UL)         /*!< ER_ST15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST15_Msk       (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST16_Pos       (16UL)         /*!< ER_ST16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST16_Msk       (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST17_Pos       (17UL)         /*!< ER_ST17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST17_Msk       (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST18_Pos       (18UL)         /*!< ER_ST18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST18_Msk       (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST19_Pos       (19UL)         /*!< ER_ST19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST19_Msk       (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST20_Pos       (20UL)         /*!< ER_ST20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST20_Msk       (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST21_Pos       (21UL)         /*!< ER_ST21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST21_Msk       (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST22_Pos       (22UL)         /*!< ER_ST22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST22_Msk       (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST23_Pos       (23UL)         /*!< ER_ST23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST23_Msk       (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST24_Pos       (24UL)         /*!< ER_ST24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST24_Msk       (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST25_Pos       (25UL)         /*!< ER_ST25 (Bit 25)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST25_Msk       (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST26_Pos       (26UL)         /*!< ER_ST26 (Bit 26)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST26_Msk       (0x4000000UL)  /*!< ER_ST26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST27_Pos       (27UL)         /*!< ER_ST27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST27_Msk       (0x8000000UL)  /*!< ER_ST27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST28_Pos       (28UL)         /*!< ER_ST28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST28_Msk       (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST29_Pos       (29UL)         /*!< ER_ST29 (Bit 29)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST29_Msk       (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST30_Pos       (30UL)         /*!< ER_ST30 (Bit 30)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST30_Msk       (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT0_ER_ST31_Pos       (31UL)         /*!< ER_ST31 (Bit 31)                                      */
+ #define R_ICU_PERIERR_STAT0_ER_ST31_Msk       (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  PERIERR_STAT1  ===================================================== */
+ #define R_ICU_PERIERR_STAT1_ER_ST0_Pos        (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST0_Msk        (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST1_Pos        (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST1_Msk        (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST2_Pos        (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST2_Msk        (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST3_Pos        (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST3_Msk        (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST4_Pos        (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST4_Msk        (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST5_Pos        (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST5_Msk        (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST6_Pos        (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST6_Msk        (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST7_Pos        (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST7_Msk        (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST8_Pos        (8UL)          /*!< ER_ST8 (Bit 8)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST8_Msk        (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST9_Pos        (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_STAT1_ER_ST9_Msk        (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_STAT1_ER_ST13_Pos       (13UL)         /*!< ER_ST13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST13_Msk       (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST15_Pos       (15UL)         /*!< ER_ST15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST15_Msk       (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST16_Pos       (16UL)         /*!< ER_ST16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST16_Msk       (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST17_Pos       (17UL)         /*!< ER_ST17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST17_Msk       (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST18_Pos       (18UL)         /*!< ER_ST18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST18_Msk       (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST19_Pos       (19UL)         /*!< ER_ST19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST19_Msk       (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST20_Pos       (20UL)         /*!< ER_ST20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST20_Msk       (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST21_Pos       (21UL)         /*!< ER_ST21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST21_Msk       (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST22_Pos       (22UL)         /*!< ER_ST22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST22_Msk       (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST23_Pos       (23UL)         /*!< ER_ST23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST23_Msk       (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST24_Pos       (24UL)         /*!< ER_ST24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST24_Msk       (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST27_Pos       (27UL)         /*!< ER_ST27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST27_Msk       (0x8000000UL)  /*!< ER_ST27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_STAT1_ER_ST28_Pos       (28UL)         /*!< ER_ST28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_STAT1_ER_ST28_Msk       (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  CPU0ERR_CLR  ====================================================== */
+ #define R_ICU_CPU0ERR_CLR_ER_CL0_Pos          (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL0_Msk          (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL1_Pos          (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL1_Msk          (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL2_Pos          (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL2_Msk          (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL3_Pos          (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL3_Msk          (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL4_Pos          (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL4_Msk          (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL5_Pos          (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL5_Msk          (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL6_Pos          (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL6_Msk          (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL7_Pos          (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL7_Msk          (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL8_Pos          (8UL)          /*!< ER_CL8 (Bit 8)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL8_Msk          (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL9_Pos          (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_CPU0ERR_CLR_ER_CL9_Msk          (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_CLR_ER_CL10_Pos         (10UL)         /*!< ER_CL10 (Bit 10)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL10_Msk         (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL11_Pos         (11UL)         /*!< ER_CL11 (Bit 11)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL11_Msk         (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL12_Pos         (12UL)         /*!< ER_CL12 (Bit 12)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL12_Msk         (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL13_Pos         (13UL)         /*!< ER_CL13 (Bit 13)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL13_Msk         (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL14_Pos         (14UL)         /*!< ER_CL14 (Bit 14)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL14_Msk         (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL15_Pos         (15UL)         /*!< ER_CL15 (Bit 15)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL15_Msk         (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL16_Pos         (16UL)         /*!< ER_CL16 (Bit 16)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL16_Msk         (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL17_Pos         (17UL)         /*!< ER_CL17 (Bit 17)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL17_Msk         (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL18_Pos         (18UL)         /*!< ER_CL18 (Bit 18)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL18_Msk         (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL19_Pos         (19UL)         /*!< ER_CL19 (Bit 19)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL19_Msk         (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL20_Pos         (20UL)         /*!< ER_CL20 (Bit 20)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL20_Msk         (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL21_Pos         (21UL)         /*!< ER_CL21 (Bit 21)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL21_Msk         (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL22_Pos         (22UL)         /*!< ER_CL22 (Bit 22)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL22_Msk         (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL23_Pos         (23UL)         /*!< ER_CL23 (Bit 23)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL23_Msk         (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL24_Pos         (24UL)         /*!< ER_CL24 (Bit 24)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL24_Msk         (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_CLR_ER_CL25_Pos         (25UL)         /*!< ER_CL25 (Bit 25)                                      */
+ #define R_ICU_CPU0ERR_CLR_ER_CL25_Msk         (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  PERIERR_CLR0  ====================================================== */
+ #define R_ICU_PERIERR_CLR0_ER_CL0_Pos         (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL0_Msk         (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL1_Pos         (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL1_Msk         (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL2_Pos         (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL2_Msk         (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL3_Pos         (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL3_Msk         (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL4_Pos         (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL4_Msk         (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL5_Pos         (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL5_Msk         (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL6_Pos         (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL6_Msk         (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL7_Pos         (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL7_Msk         (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL9_Pos         (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_CLR0_ER_CL9_Msk         (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR0_ER_CL10_Pos        (10UL)         /*!< ER_CL10 (Bit 10)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL10_Msk        (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL11_Pos        (11UL)         /*!< ER_CL11 (Bit 11)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL11_Msk        (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL12_Pos        (12UL)         /*!< ER_CL12 (Bit 12)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL12_Msk        (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL13_Pos        (13UL)         /*!< ER_CL13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL13_Msk        (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL14_Pos        (14UL)         /*!< ER_CL14 (Bit 14)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL14_Msk        (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL15_Pos        (15UL)         /*!< ER_CL15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL15_Msk        (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL16_Pos        (16UL)         /*!< ER_CL16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL16_Msk        (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL17_Pos        (17UL)         /*!< ER_CL17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL17_Msk        (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL18_Pos        (18UL)         /*!< ER_CL18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL18_Msk        (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL19_Pos        (19UL)         /*!< ER_CL19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL19_Msk        (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL20_Pos        (20UL)         /*!< ER_CL20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL20_Msk        (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL21_Pos        (21UL)         /*!< ER_CL21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL21_Msk        (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL22_Pos        (22UL)         /*!< ER_CL22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL22_Msk        (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL23_Pos        (23UL)         /*!< ER_CL23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL23_Msk        (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL24_Pos        (24UL)         /*!< ER_CL24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL24_Msk        (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL25_Pos        (25UL)         /*!< ER_CL25 (Bit 25)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL25_Msk        (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL26_Pos        (26UL)         /*!< ER_CL26 (Bit 26)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL26_Msk        (0x4000000UL)  /*!< ER_CL26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL27_Pos        (27UL)         /*!< ER_CL27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL27_Msk        (0x8000000UL)  /*!< ER_CL27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL28_Pos        (28UL)         /*!< ER_CL28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL28_Msk        (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL29_Pos        (29UL)         /*!< ER_CL29 (Bit 29)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL29_Msk        (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL30_Pos        (30UL)         /*!< ER_CL30 (Bit 30)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL30_Msk        (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR0_ER_CL31_Pos        (31UL)         /*!< ER_CL31 (Bit 31)                                      */
+ #define R_ICU_PERIERR_CLR0_ER_CL31_Msk        (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  PERIERR_CLR1  ====================================================== */
+ #define R_ICU_PERIERR_CLR1_ER_CL0_Pos         (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL0_Msk         (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL1_Pos         (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL1_Msk         (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL2_Pos         (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL2_Msk         (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL3_Pos         (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL3_Msk         (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL4_Pos         (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL4_Msk         (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL5_Pos         (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL5_Msk         (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL6_Pos         (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL6_Msk         (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL7_Pos         (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL7_Msk         (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL8_Pos         (8UL)          /*!< ER_CL8 (Bit 8)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL8_Msk         (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL9_Pos         (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_CLR1_ER_CL9_Msk         (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_CLR1_ER_CL13_Pos        (13UL)         /*!< ER_CL13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL13_Msk        (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL15_Pos        (15UL)         /*!< ER_CL15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL15_Msk        (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL16_Pos        (16UL)         /*!< ER_CL16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL16_Msk        (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL17_Pos        (17UL)         /*!< ER_CL17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL17_Msk        (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL18_Pos        (18UL)         /*!< ER_CL18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL18_Msk        (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL19_Pos        (19UL)         /*!< ER_CL19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL19_Msk        (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL20_Pos        (20UL)         /*!< ER_CL20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL20_Msk        (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL21_Pos        (21UL)         /*!< ER_CL21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL21_Msk        (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL22_Pos        (22UL)         /*!< ER_CL22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL22_Msk        (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL23_Pos        (23UL)         /*!< ER_CL23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL23_Msk        (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL24_Pos        (24UL)         /*!< ER_CL24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL24_Msk        (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL27_Pos        (27UL)         /*!< ER_CL27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL27_Msk        (0x8000000UL)  /*!< ER_CL27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_CLR1_ER_CL28_Pos        (28UL)         /*!< ER_CL28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_CLR1_ER_CL28_Msk        (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  CPU0ERR_RSTMSK  ===================================================== */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Pos       (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Msk       (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Pos       (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Msk       (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Pos       (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Msk       (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Pos       (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Msk       (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Pos       (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Msk       (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Pos       (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Msk       (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Pos       (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Msk       (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Pos       (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Msk       (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Pos       (8UL)          /*!< RS_MK8 (Bit 8)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Msk       (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Pos       (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Msk       (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Pos      (10UL)         /*!< RS_MK10 (Bit 10)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Msk      (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Pos      (11UL)         /*!< RS_MK11 (Bit 11)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Msk      (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Pos      (12UL)         /*!< RS_MK12 (Bit 12)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Msk      (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Pos      (13UL)         /*!< RS_MK13 (Bit 13)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Msk      (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Pos      (14UL)         /*!< RS_MK14 (Bit 14)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Msk      (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Pos      (15UL)         /*!< RS_MK15 (Bit 15)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Msk      (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Pos      (16UL)         /*!< RS_MK16 (Bit 16)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Msk      (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Pos      (17UL)         /*!< RS_MK17 (Bit 17)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Msk      (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Pos      (18UL)         /*!< RS_MK18 (Bit 18)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Msk      (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Pos      (19UL)         /*!< RS_MK19 (Bit 19)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Msk      (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Pos      (20UL)         /*!< RS_MK20 (Bit 20)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Msk      (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Pos      (21UL)         /*!< RS_MK21 (Bit 21)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Msk      (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Pos      (22UL)         /*!< RS_MK22 (Bit 22)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Msk      (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Pos      (23UL)         /*!< RS_MK23 (Bit 23)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Msk      (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Pos      (24UL)         /*!< RS_MK24 (Bit 24)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Msk      (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Pos      (25UL)         /*!< RS_MK25 (Bit 25)                                      */
+ #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Msk      (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PERIERR_RSTMSK0  ==================================================== */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Pos      (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Msk      (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Pos      (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Msk      (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Pos      (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Msk      (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Pos      (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Msk      (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Pos      (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Msk      (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Pos      (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Msk      (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Pos      (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Msk      (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Pos      (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Msk      (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Pos      (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Msk      (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Pos     (10UL)         /*!< RS_MK10 (Bit 10)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Msk     (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Pos     (11UL)         /*!< RS_MK11 (Bit 11)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Msk     (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Pos     (12UL)         /*!< RS_MK12 (Bit 12)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Msk     (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Pos     (13UL)         /*!< RS_MK13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Msk     (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Pos     (14UL)         /*!< RS_MK14 (Bit 14)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Msk     (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Pos     (15UL)         /*!< RS_MK15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Msk     (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Pos     (16UL)         /*!< RS_MK16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Msk     (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Pos     (17UL)         /*!< RS_MK17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Msk     (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Pos     (18UL)         /*!< RS_MK18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Msk     (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Pos     (19UL)         /*!< RS_MK19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Msk     (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Pos     (20UL)         /*!< RS_MK20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Msk     (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Pos     (21UL)         /*!< RS_MK21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Msk     (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Pos     (22UL)         /*!< RS_MK22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Msk     (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Pos     (23UL)         /*!< RS_MK23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Msk     (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Pos     (24UL)         /*!< RS_MK24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Msk     (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Pos     (25UL)         /*!< RS_MK25 (Bit 25)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Msk     (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Pos     (26UL)         /*!< RS_MK26 (Bit 26)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Msk     (0x4000000UL)  /*!< RS_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Pos     (27UL)         /*!< RS_MK27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Msk     (0x8000000UL)  /*!< RS_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Pos     (28UL)         /*!< RS_MK28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Msk     (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Pos     (29UL)         /*!< RS_MK29 (Bit 29)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Msk     (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Pos     (30UL)         /*!< RS_MK30 (Bit 30)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Msk     (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Pos     (31UL)         /*!< RS_MK31 (Bit 31)                                      */
+ #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Msk     (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PERIERR_RSTMSK1  ==================================================== */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Pos      (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Msk      (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Pos      (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Msk      (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Pos      (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Msk      (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Pos      (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Msk      (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Pos      (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Msk      (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Pos      (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Msk      (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Pos      (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Msk      (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK7_Pos      (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK7_Msk      (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK8_Pos      (8UL)          /*!< RS_MK8 (Bit 8)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK8_Msk      (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK9_Pos      (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK9_Msk      (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Pos     (13UL)         /*!< RS_MK13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Msk     (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Pos     (15UL)         /*!< RS_MK15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Msk     (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK16_Pos     (16UL)         /*!< RS_MK16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK16_Msk     (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Pos     (17UL)         /*!< RS_MK17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Msk     (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Pos     (18UL)         /*!< RS_MK18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Msk     (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Pos     (19UL)         /*!< RS_MK19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Msk     (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Pos     (20UL)         /*!< RS_MK20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Msk     (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Pos     (21UL)         /*!< RS_MK21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Msk     (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Pos     (22UL)         /*!< RS_MK22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Msk     (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Pos     (23UL)         /*!< RS_MK23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Msk     (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Pos     (24UL)         /*!< RS_MK24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Msk     (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Pos     (27UL)         /*!< RS_MK27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Msk     (0x8000000UL)  /*!< RS_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Pos     (28UL)         /*!< RS_MK28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Msk     (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CPU0ERR_E0MSK  ===================================================== */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Pos        (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Msk        (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Pos        (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Msk        (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Pos        (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Msk        (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Pos        (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Msk        (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Pos        (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Msk        (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Pos        (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Msk        (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Pos        (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Msk        (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Pos        (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Msk        (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Pos        (8UL)          /*!< E0_MK8 (Bit 8)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Msk        (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Pos        (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Msk        (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Pos       (10UL)         /*!< E0_MK10 (Bit 10)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Msk       (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Pos       (11UL)         /*!< E0_MK11 (Bit 11)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Msk       (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Pos       (12UL)         /*!< E0_MK12 (Bit 12)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Msk       (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Pos       (13UL)         /*!< E0_MK13 (Bit 13)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Msk       (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Pos       (14UL)         /*!< E0_MK14 (Bit 14)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Msk       (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Pos       (15UL)         /*!< E0_MK15 (Bit 15)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Msk       (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Pos       (16UL)         /*!< E0_MK16 (Bit 16)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Msk       (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Pos       (17UL)         /*!< E0_MK17 (Bit 17)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Msk       (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Pos       (18UL)         /*!< E0_MK18 (Bit 18)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Msk       (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Pos       (19UL)         /*!< E0_MK19 (Bit 19)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Msk       (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Pos       (20UL)         /*!< E0_MK20 (Bit 20)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Msk       (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Pos       (21UL)         /*!< E0_MK21 (Bit 21)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Msk       (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Pos       (22UL)         /*!< E0_MK22 (Bit 22)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Msk       (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Pos       (23UL)         /*!< E0_MK23 (Bit 23)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Msk       (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Pos       (24UL)         /*!< E0_MK24 (Bit 24)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Msk       (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Pos       (25UL)         /*!< E0_MK25 (Bit 25)                                      */
+ #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Msk       (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PERIERR_E0MSK0  ===================================================== */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK0_Pos       (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK0_Msk       (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK1_Pos       (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK1_Msk       (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK2_Pos       (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK2_Msk       (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK3_Pos       (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK3_Msk       (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK4_Pos       (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK4_Msk       (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK5_Pos       (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK5_Msk       (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK6_Pos       (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK6_Msk       (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK7_Pos       (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK7_Msk       (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK9_Pos       (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK9_Msk       (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK10_Pos      (10UL)         /*!< E0_MK10 (Bit 10)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK10_Msk      (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK11_Pos      (11UL)         /*!< E0_MK11 (Bit 11)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK11_Msk      (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK12_Pos      (12UL)         /*!< E0_MK12 (Bit 12)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK12_Msk      (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK13_Pos      (13UL)         /*!< E0_MK13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK13_Msk      (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK14_Pos      (14UL)         /*!< E0_MK14 (Bit 14)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK14_Msk      (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK15_Pos      (15UL)         /*!< E0_MK15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK15_Msk      (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK16_Pos      (16UL)         /*!< E0_MK16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK16_Msk      (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK17_Pos      (17UL)         /*!< E0_MK17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK17_Msk      (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK18_Pos      (18UL)         /*!< E0_MK18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK18_Msk      (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK19_Pos      (19UL)         /*!< E0_MK19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK19_Msk      (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK20_Pos      (20UL)         /*!< E0_MK20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK20_Msk      (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK21_Pos      (21UL)         /*!< E0_MK21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK21_Msk      (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK22_Pos      (22UL)         /*!< E0_MK22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK22_Msk      (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK23_Pos      (23UL)         /*!< E0_MK23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK23_Msk      (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK24_Pos      (24UL)         /*!< E0_MK24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK24_Msk      (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK25_Pos      (25UL)         /*!< E0_MK25 (Bit 25)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK25_Msk      (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK26_Pos      (26UL)         /*!< E0_MK26 (Bit 26)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK26_Msk      (0x4000000UL)  /*!< E0_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK27_Pos      (27UL)         /*!< E0_MK27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK27_Msk      (0x8000000UL)  /*!< E0_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK28_Pos      (28UL)         /*!< E0_MK28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK28_Msk      (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK29_Pos      (29UL)         /*!< E0_MK29 (Bit 29)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK29_Msk      (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK30_Pos      (30UL)         /*!< E0_MK30 (Bit 30)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK30_Msk      (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK31_Pos      (31UL)         /*!< E0_MK31 (Bit 31)                                      */
+ #define R_ICU_PERIERR_E0MSK0_E0_MK31_Msk      (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PERIERR_E0MSK1  ===================================================== */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK0_Pos       (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK0_Msk       (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK1_Pos       (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK1_Msk       (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK2_Pos       (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK2_Msk       (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK3_Pos       (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK3_Msk       (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK4_Pos       (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK4_Msk       (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK5_Pos       (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK5_Msk       (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK6_Pos       (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK6_Msk       (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK7_Pos       (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK7_Msk       (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK8_Pos       (8UL)          /*!< E0_MK8 (Bit 8)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK8_Msk       (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK9_Pos       (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK9_Msk       (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK13_Pos      (13UL)         /*!< E0_MK13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK13_Msk      (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK15_Pos      (15UL)         /*!< E0_MK15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK15_Msk      (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK16_Pos      (16UL)         /*!< E0_MK16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK16_Msk      (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK17_Pos      (17UL)         /*!< E0_MK17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK17_Msk      (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK18_Pos      (18UL)         /*!< E0_MK18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK18_Msk      (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK19_Pos      (19UL)         /*!< E0_MK19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK19_Msk      (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK20_Pos      (20UL)         /*!< E0_MK20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK20_Msk      (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK21_Pos      (21UL)         /*!< E0_MK21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK21_Msk      (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK22_Pos      (22UL)         /*!< E0_MK22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK22_Msk      (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK23_Pos      (23UL)         /*!< E0_MK23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK23_Msk      (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK24_Pos      (24UL)         /*!< E0_MK24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK24_Msk      (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK27_Pos      (27UL)         /*!< E0_MK27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK27_Msk      (0x8000000UL)  /*!< E0_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK28_Pos      (28UL)         /*!< E0_MK28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_E0MSK1_E0_MK28_Msk      (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CPU0ERR_E1MSK  ===================================================== */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Pos        (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Msk        (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Pos        (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Msk        (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Pos        (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Msk        (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Pos        (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Msk        (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Pos        (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Msk        (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Pos        (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Msk        (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Pos        (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Msk        (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Pos        (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Msk        (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Pos        (8UL)          /*!< E1_MK8 (Bit 8)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Msk        (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Pos        (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Msk        (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Pos       (10UL)         /*!< E1_MK10 (Bit 10)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Msk       (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Pos       (11UL)         /*!< E1_MK11 (Bit 11)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Msk       (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Pos       (12UL)         /*!< E1_MK12 (Bit 12)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Msk       (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Pos       (13UL)         /*!< E1_MK13 (Bit 13)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Msk       (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Pos       (14UL)         /*!< E1_MK14 (Bit 14)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Msk       (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Pos       (15UL)         /*!< E1_MK15 (Bit 15)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Msk       (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Pos       (16UL)         /*!< E1_MK16 (Bit 16)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Msk       (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Pos       (17UL)         /*!< E1_MK17 (Bit 17)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Msk       (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Pos       (18UL)         /*!< E1_MK18 (Bit 18)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Msk       (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Pos       (19UL)         /*!< E1_MK19 (Bit 19)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Msk       (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Pos       (20UL)         /*!< E1_MK20 (Bit 20)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Msk       (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Pos       (21UL)         /*!< E1_MK21 (Bit 21)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Msk       (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Pos       (22UL)         /*!< E1_MK22 (Bit 22)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Msk       (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Pos       (23UL)         /*!< E1_MK23 (Bit 23)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Msk       (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Pos       (24UL)         /*!< E1_MK24 (Bit 24)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Msk       (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Pos       (25UL)         /*!< E1_MK25 (Bit 25)                                      */
+ #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Msk       (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PERIERR_E1MSK0  ===================================================== */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK0_Pos       (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK0_Msk       (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK1_Pos       (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK1_Msk       (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK2_Pos       (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK2_Msk       (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK3_Pos       (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK3_Msk       (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK4_Pos       (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK4_Msk       (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK5_Pos       (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK5_Msk       (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK6_Pos       (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK6_Msk       (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK7_Pos       (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK7_Msk       (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK9_Pos       (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK9_Msk       (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK10_Pos      (10UL)         /*!< E1_MK10 (Bit 10)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK10_Msk      (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK11_Pos      (11UL)         /*!< E1_MK11 (Bit 11)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK11_Msk      (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK12_Pos      (12UL)         /*!< E1_MK12 (Bit 12)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK12_Msk      (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK13_Pos      (13UL)         /*!< E1_MK13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK13_Msk      (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK14_Pos      (14UL)         /*!< E1_MK14 (Bit 14)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK14_Msk      (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK15_Pos      (15UL)         /*!< E1_MK15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK15_Msk      (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK16_Pos      (16UL)         /*!< E1_MK16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK16_Msk      (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK17_Pos      (17UL)         /*!< E1_MK17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK17_Msk      (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK18_Pos      (18UL)         /*!< E1_MK18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK18_Msk      (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK19_Pos      (19UL)         /*!< E1_MK19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK19_Msk      (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK20_Pos      (20UL)         /*!< E1_MK20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK20_Msk      (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK21_Pos      (21UL)         /*!< E1_MK21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK21_Msk      (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK22_Pos      (22UL)         /*!< E1_MK22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK22_Msk      (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK23_Pos      (23UL)         /*!< E1_MK23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK23_Msk      (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK24_Pos      (24UL)         /*!< E1_MK24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK24_Msk      (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK25_Pos      (25UL)         /*!< E1_MK25 (Bit 25)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK25_Msk      (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK26_Pos      (26UL)         /*!< E1_MK26 (Bit 26)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK26_Msk      (0x4000000UL)  /*!< E1_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK27_Pos      (27UL)         /*!< E1_MK27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK27_Msk      (0x8000000UL)  /*!< E1_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK28_Pos      (28UL)         /*!< E1_MK28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK28_Msk      (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK29_Pos      (29UL)         /*!< E1_MK29 (Bit 29)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK29_Msk      (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK30_Pos      (30UL)         /*!< E1_MK30 (Bit 30)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK30_Msk      (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK31_Pos      (31UL)         /*!< E1_MK31 (Bit 31)                                      */
+ #define R_ICU_PERIERR_E1MSK0_E1_MK31_Msk      (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PERIERR_E1MSK1  ===================================================== */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK0_Pos       (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK0_Msk       (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK1_Pos       (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK1_Msk       (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK2_Pos       (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK2_Msk       (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK3_Pos       (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK3_Msk       (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK4_Pos       (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK4_Msk       (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK5_Pos       (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK5_Msk       (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK6_Pos       (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK6_Msk       (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK7_Pos       (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK7_Msk       (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK8_Pos       (8UL)          /*!< E1_MK8 (Bit 8)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK8_Msk       (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK9_Pos       (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK9_Msk       (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK13_Pos      (13UL)         /*!< E1_MK13 (Bit 13)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK13_Msk      (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK15_Pos      (15UL)         /*!< E1_MK15 (Bit 15)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK15_Msk      (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK16_Pos      (16UL)         /*!< E1_MK16 (Bit 16)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK16_Msk      (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK17_Pos      (17UL)         /*!< E1_MK17 (Bit 17)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK17_Msk      (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK18_Pos      (18UL)         /*!< E1_MK18 (Bit 18)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK18_Msk      (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK19_Pos      (19UL)         /*!< E1_MK19 (Bit 19)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK19_Msk      (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK20_Pos      (20UL)         /*!< E1_MK20 (Bit 20)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK20_Msk      (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK21_Pos      (21UL)         /*!< E1_MK21 (Bit 21)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK21_Msk      (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK22_Pos      (22UL)         /*!< E1_MK22 (Bit 22)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK22_Msk      (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK23_Pos      (23UL)         /*!< E1_MK23 (Bit 23)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK23_Msk      (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK24_Pos      (24UL)         /*!< E1_MK24 (Bit 24)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK24_Msk      (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK27_Pos      (27UL)         /*!< E1_MK27 (Bit 27)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK27_Msk      (0x8000000UL)  /*!< E1_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK28_Pos      (28UL)         /*!< E1_MK28 (Bit 28)                                      */
+ #define R_ICU_PERIERR_E1MSK1_E1_MK28_Msk      (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSC_S                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SCKCR2  ========================================================= */
+ #define R_SYSC_S_SCKCR2_FSELCPU0_Pos        (0UL)          /*!< FSELCPU0 (Bit 0)                                      */
+ #define R_SYSC_S_SCKCR2_FSELCPU0_Msk        (0x1UL)        /*!< FSELCPU0 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_S_SCKCR2_DIVSELSUB_Pos       (5UL)          /*!< DIVSELSUB (Bit 5)                                     */
+ #define R_SYSC_S_SCKCR2_DIVSELSUB_Msk       (0x20UL)       /*!< DIVSELSUB (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Pos    (24UL)         /*!< SPI3ASYNCSEL (Bit 24)                                 */
+ #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Msk    (0x1000000UL)  /*!< SPI3ASYNCSEL (Bitfield-Mask: 0x01)                    */
+ #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Pos    (25UL)         /*!< SCI5ASYNCSEL (Bit 25)                                 */
+ #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Msk    (0x2000000UL)  /*!< SCI5ASYNCSEL (Bitfield-Mask: 0x01)                    */
+/* ========================================================  PLL0MON  ======================================================== */
+ #define R_SYSC_S_PLL0MON_PLL0MON_Pos        (0UL)          /*!< PLL0MON (Bit 0)                                       */
+ #define R_SYSC_S_PLL0MON_PLL0MON_Msk        (0x1UL)        /*!< PLL0MON (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PLL1MON  ======================================================== */
+ #define R_SYSC_S_PLL1MON_PLL1MON_Pos        (0UL)          /*!< PLL1MON (Bit 0)                                       */
+ #define R_SYSC_S_PLL1MON_PLL1MON_Msk        (0x1UL)        /*!< PLL1MON (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PLL1EN  ========================================================= */
+ #define R_SYSC_S_PLL1EN_PLL1EN_Pos          (0UL)          /*!< PLL1EN (Bit 0)                                        */
+ #define R_SYSC_S_PLL1EN_PLL1EN_Msk          (0x1UL)        /*!< PLL1EN (Bitfield-Mask: 0x01)                          */
+/* ========================================================  LOCOCR  ========================================================= */
+ #define R_SYSC_S_LOCOCR_LCSTP_Pos           (0UL)          /*!< LCSTP (Bit 0)                                         */
+ #define R_SYSC_S_LOCOCR_LCSTP_Msk           (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  HIZCTRLEN  ======================================================= */
+ #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Pos    (0UL)          /*!< CLMA3MASK (Bit 0)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Msk    (0x1UL)        /*!< CLMA3MASK (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Pos    (1UL)          /*!< CLMA0MASK (Bit 1)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Msk    (0x2UL)        /*!< CLMA0MASK (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Pos    (2UL)          /*!< CLMA1MASK (Bit 2)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Msk    (0x4UL)        /*!< CLMA1MASK (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SWRSYS  ========================================================= */
+ #define R_SYSC_S_SWRSYS_SWR_Pos             (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWRSYS_SWR_Msk             (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SWRCPU0  ======================================================== */
+ #define R_SYSC_S_SWRCPU0_SWR_Pos            (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWRCPU0_SWR_Msk            (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  MRCTLI  ========================================================= */
+ #define R_SYSC_S_MRCTLI_MRCTLI00_Pos        (0UL)          /*!< MRCTLI00 (Bit 0)                                      */
+ #define R_SYSC_S_MRCTLI_MRCTLI00_Msk        (0x1UL)        /*!< MRCTLI00 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_S_MRCTLI_MRCTLI01_Pos        (1UL)          /*!< MRCTLI01 (Bit 1)                                      */
+ #define R_SYSC_S_MRCTLI_MRCTLI01_Msk        (0x2UL)        /*!< MRCTLI01 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_S_MRCTLI_MRCTLI02_Pos        (2UL)          /*!< MRCTLI02 (Bit 2)                                      */
+ #define R_SYSC_S_MRCTLI_MRCTLI02_Msk        (0x4UL)        /*!< MRCTLI02 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_S_MRCTLI_MRCTLI03_Pos        (3UL)          /*!< MRCTLI03 (Bit 3)                                      */
+ #define R_SYSC_S_MRCTLI_MRCTLI03_Msk        (0x8UL)        /*!< MRCTLI03 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MSTPCRF  ======================================================== */
+ #define R_SYSC_S_MSTPCRF_MSTPCRF00_Pos      (0UL)          /*!< MSTPCRF00 (Bit 0)                                     */
+ #define R_SYSC_S_MSTPCRF_MSTPCRF00_Msk      (0x1UL)        /*!< MSTPCRF00 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRG  ======================================================== */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG00_Pos      (0UL)          /*!< MSTPCRG00 (Bit 0)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG00_Msk      (0x1UL)        /*!< MSTPCRG00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG01_Pos      (1UL)          /*!< MSTPCRG01 (Bit 1)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG01_Msk      (0x2UL)        /*!< MSTPCRG01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG02_Pos      (2UL)          /*!< MSTPCRG02 (Bit 2)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG02_Msk      (0x4UL)        /*!< MSTPCRG02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG03_Pos      (3UL)          /*!< MSTPCRG03 (Bit 3)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG03_Msk      (0x8UL)        /*!< MSTPCRG03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG04_Pos      (4UL)          /*!< MSTPCRG04 (Bit 4)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG04_Msk      (0x10UL)       /*!< MSTPCRG04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG05_Pos      (5UL)          /*!< MSTPCRG05 (Bit 5)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG05_Msk      (0x20UL)       /*!< MSTPCRG05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG08_Pos      (8UL)          /*!< MSTPCRG08 (Bit 8)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG08_Msk      (0x100UL)      /*!< MSTPCRG08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG09_Pos      (9UL)          /*!< MSTPCRG09 (Bit 9)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG09_Msk      (0x200UL)      /*!< MSTPCRG09 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG10_Pos      (10UL)         /*!< MSTPCRG10 (Bit 10)                                    */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG10_Msk      (0x400UL)      /*!< MSTPCRG10 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG11_Pos      (11UL)         /*!< MSTPCRG11 (Bit 11)                                    */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG11_Msk      (0x800UL)      /*!< MSTPCRG11 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRI  ======================================================== */
+ #define R_SYSC_S_MSTPCRI_MSTPCRI00_Pos      (0UL)          /*!< MSTPCRI00 (Bit 0)                                     */
+ #define R_SYSC_S_MSTPCRI_MSTPCRI00_Msk      (0x1UL)        /*!< MSTPCRI00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRI_MSTPCRI01_Pos      (1UL)          /*!< MSTPCRI01 (Bit 1)                                     */
+ #define R_SYSC_S_MSTPCRI_MSTPCRI01_Msk      (0x2UL)        /*!< MSTPCRI01 (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CLMA0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CTL0  ========================================================== */
+ #define R_CLMA0_CTL0_CLME_Pos       (0UL)     /*!< CLME (Bit 0)                                          */
+ #define R_CLMA0_CTL0_CLME_Msk       (0x1UL)   /*!< CLME (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CMPL  ========================================================== */
+ #define R_CLMA0_CMPL_CMPL_Pos       (0UL)     /*!< CMPL (Bit 0)                                          */
+ #define R_CLMA0_CMPL_CMPL_Msk       (0xfffUL) /*!< CMPL (Bitfield-Mask: 0xfff)                           */
+/* =========================================================  CMPH  ========================================================== */
+ #define R_CLMA0_CMPH_CMPH_Pos       (0UL)     /*!< CMPH (Bit 0)                                          */
+ #define R_CLMA0_CMPH_CMPH_Msk       (0xfffUL) /*!< CMPH (Bitfield-Mask: 0xfff)                           */
+/* =========================================================  PCMD  ========================================================== */
+/* ========================================================  PROTSR  ========================================================= */
+ #define R_CLMA0_PROTSR_PRERR_Pos    (0UL)     /*!< PRERR (Bit 0)                                         */
+ #define R_CLMA0_PROTSR_PRERR_Msk    (0x1UL)   /*!< PRERR (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MPU0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  ERRINF_R  ======================================================== */
+ #define R_MPU0_ERRINF_R_VALID_Pos      (0UL)          /*!< VALID (Bit 0)                                         */
+ #define R_MPU0_ERRINF_R_VALID_Msk      (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_MPU0_ERRINF_R_RW_Pos         (1UL)          /*!< RW (Bit 1)                                            */
+ #define R_MPU0_ERRINF_R_RW_Msk         (0x2UL)        /*!< RW (Bitfield-Mask: 0x01)                              */
+ #define R_MPU0_ERRINF_R_ERRADDR_Pos    (2UL)          /*!< ERRADDR (Bit 2)                                       */
+ #define R_MPU0_ERRINF_R_ERRADDR_Msk    (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff)                   */
+/* =======================================================  ERRINF_W  ======================================================== */
+ #define R_MPU0_ERRINF_W_VALID_Pos      (0UL)          /*!< VALID (Bit 0)                                         */
+ #define R_MPU0_ERRINF_W_VALID_Msk      (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_MPU0_ERRINF_W_RW_Pos         (1UL)          /*!< RW (Bit 1)                                            */
+ #define R_MPU0_ERRINF_W_RW_Msk         (0x2UL)        /*!< RW (Bitfield-Mask: 0x01)                              */
+ #define R_MPU0_ERRINF_W_ERRADDR_Pos    (2UL)          /*!< ERRADDR (Bit 2)                                       */
+ #define R_MPU0_ERRINF_W_ERRADDR_Msk    (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff)                   */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MPU3                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  ERRINF  ========================================================= */
+ #define R_MPU3_ERRINF_VALID_Pos      (0UL)          /*!< VALID (Bit 0)                                         */
+ #define R_MPU3_ERRINF_VALID_Msk      (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_MPU3_ERRINF_RW_Pos         (1UL)          /*!< RW (Bit 1)                                            */
+ #define R_MPU3_ERRINF_RW_Msk         (0x2UL)        /*!< RW (Bitfield-Mask: 0x01)                              */
+ #define R_MPU3_ERRINF_ERRADDR_Pos    (2UL)          /*!< ERRADDR (Bit 2)                                       */
+ #define R_MPU3_ERRINF_ERRADDR_Msk    (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff)                   */
+
+/* =========================================================================================================================== */
+/* ================                                       R_SYSRAM_CTL                                        ================ */
+/* =========================================================================================================================== */
+
+/* =====================================================  SYSRAM_CTRL0  ====================================================== */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
+/* =====================================================  SYSRAM_CTRL1  ====================================================== */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
+/* =====================================================  SYSRAM_CTRL2  ====================================================== */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
+
+/* =========================================================================================================================== */
+/* ================                                       R_SHOSTIF_CFG                                       ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SHCFG  ========================================================= */
+ #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Pos       (0UL)          /*!< SPIMODE (Bit 0)                                       */
+ #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Msk       (0x3UL)        /*!< SPIMODE (Bitfield-Mask: 0x03)                         */
+ #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Pos      (2UL)          /*!< BYTESWAP (Bit 2)                                      */
+ #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Msk      (0x4UL)        /*!< BYTESWAP (Bitfield-Mask: 0x01)                        */
+ #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Pos    (3UL)          /*!< ADDRESSING (Bit 3)                                    */
+ #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Msk    (0x8UL)        /*!< ADDRESSING (Bitfield-Mask: 0x01)                      */
+ #define R_SHOSTIF_CFG_SHCFG_SLEEP_Pos         (4UL)          /*!< SLEEP (Bit 4)                                         */
+ #define R_SHOSTIF_CFG_SHCFG_SLEEP_Msk         (0x10UL)       /*!< SLEEP (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Pos      (16UL)         /*!< INTMASKI (Bit 16)                                     */
+ #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Msk      (0x3f0000UL)   /*!< INTMASKI (Bitfield-Mask: 0x3f)                        */
+ #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Pos      (24UL)         /*!< INTMASKE (Bit 24)                                     */
+ #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Msk      (0x3f000000UL) /*!< INTMASKE (Bitfield-Mask: 0x3f)                        */
+
+/* =========================================================================================================================== */
+/* ================                                       R_PHOSTIF_CFG                                       ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PHCFG  ========================================================= */
+ #define R_PHOSTIF_CFG_PHCFG_MEMIFSEL_Pos      (0UL)        /*!< MEMIFSEL (Bit 0)                                      */
+ #define R_PHOSTIF_CFG_PHCFG_MEMIFSEL_Msk      (0x1UL)      /*!< MEMIFSEL (Bitfield-Mask: 0x01)                        */
+ #define R_PHOSTIF_CFG_PHCFG_BUSSSEL_Pos       (4UL)        /*!< BUSSSEL (Bit 4)                                       */
+ #define R_PHOSTIF_CFG_PHCFG_BUSSSEL_Msk       (0x10UL)     /*!< BUSSSEL (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_CFG_PHCFG_HIFSYNC_Pos       (8UL)        /*!< HIFSYNC (Bit 8)                                       */
+ #define R_PHOSTIF_CFG_PHCFG_HIFSYNC_Msk       (0x100UL)    /*!< HIFSYNC (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_CFG_PHCFG_MEMCSEL_Pos       (12UL)       /*!< MEMCSEL (Bit 12)                                      */
+ #define R_PHOSTIF_CFG_PHCFG_MEMCSEL_Msk       (0x1000UL)   /*!< MEMCSEL (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_CFG_PHCFG_HWRZSEL_Pos       (16UL)       /*!< HWRZSEL (Bit 16)                                      */
+ #define R_PHOSTIF_CFG_PHCFG_HWRZSEL_Msk       (0x10000UL)  /*!< HWRZSEL (Bitfield-Mask: 0x01)                         */
+ #define R_PHOSTIF_CFG_PHCFG_ADMUXMODE_Pos     (20UL)       /*!< ADMUXMODE (Bit 20)                                    */
+ #define R_PHOSTIF_CFG_PHCFG_ADMUXMODE_Msk     (0x100000UL) /*!< ADMUXMODE (Bitfield-Mask: 0x01)                       */
+/* =========================================================  PHACC  ========================================================= */
+ #define R_PHOSTIF_CFG_PHACC_HIFRDYSEL_Pos     (0UL)        /*!< HIFRDYSEL (Bit 0)                                     */
+ #define R_PHOSTIF_CFG_PHACC_HIFRDYSEL_Msk     (0x1UL)      /*!< HIFRDYSEL (Bitfield-Mask: 0x01)                       */
+ #define R_PHOSTIF_CFG_PHACC_HIFBCCSEL_Pos     (8UL)        /*!< HIFBCCSEL (Bit 8)                                     */
+ #define R_PHOSTIF_CFG_PHACC_HIFBCCSEL_Msk     (0x100UL)    /*!< HIFBCCSEL (Bitfield-Mask: 0x01)                       */
+ #define R_PHOSTIF_CFG_PHACC_HIFBTCSEL_Pos     (9UL)        /*!< HIFBTCSEL (Bit 9)                                     */
+ #define R_PHOSTIF_CFG_PHACC_HIFBTCSEL_Msk     (0x200UL)    /*!< HIFBTCSEL (Bitfield-Mask: 0x01)                       */
+ #define R_PHOSTIF_CFG_PHACC_HIFPRCSEL_Pos     (10UL)       /*!< HIFPRCSEL (Bit 10)                                    */
+ #define R_PHOSTIF_CFG_PHACC_HIFPRCSEL_Msk     (0x400UL)    /*!< HIFPRCSEL (Bitfield-Mask: 0x01)                       */
+ #define R_PHOSTIF_CFG_PHACC_HIFIRCSEL_Pos     (11UL)       /*!< HIFIRCSEL (Bit 11)                                    */
+ #define R_PHOSTIF_CFG_PHACC_HIFIRCSEL_Msk     (0x800UL)    /*!< HIFIRCSEL (Bitfield-Mask: 0x01)                       */
+ #define R_PHOSTIF_CFG_PHACC_HIFXALSEL_Pos     (12UL)       /*!< HIFXALSEL (Bit 12)                                    */
+ #define R_PHOSTIF_CFG_PHACC_HIFXALSEL_Msk     (0x1000UL)   /*!< HIFXALSEL (Bitfield-Mask: 0x01)                       */
+ #define R_PHOSTIF_CFG_PHACC_HIFXAHSEL_Pos     (13UL)       /*!< HIFXAHSEL (Bit 13)                                    */
+ #define R_PHOSTIF_CFG_PHACC_HIFXAHSEL_Msk     (0x2000UL)   /*!< HIFXAHSEL (Bitfield-Mask: 0x01)                       */
+ #define R_PHOSTIF_CFG_PHACC_HIFEXT0SEL_Pos    (14UL)       /*!< HIFEXT0SEL (Bit 14)                                   */
+ #define R_PHOSTIF_CFG_PHACC_HIFEXT0SEL_Msk    (0x4000UL)   /*!< HIFEXT0SEL (Bitfield-Mask: 0x01)                      */
+ #define R_PHOSTIF_CFG_PHACC_HIFEXT1SEL_Pos    (15UL)       /*!< HIFEXT1SEL (Bit 15)                                   */
+ #define R_PHOSTIF_CFG_PHACC_HIFEXT1SEL_Msk    (0x8000UL)   /*!< HIFEXT1SEL (Bitfield-Mask: 0x01)                      */
+ #define R_PHOSTIF_CFG_PHACC_CSSWAP_Pos        (16UL)       /*!< CSSWAP (Bit 16)                                       */
+ #define R_PHOSTIF_CFG_PHACC_CSSWAP_Msk        (0x10000UL)  /*!< CSSWAP (Bitfield-Mask: 0x01)                          */
+ #define R_PHOSTIF_CFG_PHACC_BSCADMUX_Pos      (17UL)       /*!< BSCADMUX (Bit 17)                                     */
+ #define R_PHOSTIF_CFG_PHACC_BSCADMUX_Msk      (0x20000UL)  /*!< BSCADMUX (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_RWP_S                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PRCRS  ========================================================= */
+ #define R_RWP_S_PRCRS_PRC0_Pos     (0UL)      /*!< PRC0 (Bit 0)                                          */
+ #define R_RWP_S_PRCRS_PRC0_Msk     (0x1UL)    /*!< PRC0 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_S_PRCRS_PRC1_Pos     (1UL)      /*!< PRC1 (Bit 1)                                          */
+ #define R_RWP_S_PRCRS_PRC1_Msk     (0x2UL)    /*!< PRC1 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_S_PRCRS_PRC2_Pos     (2UL)      /*!< PRC2 (Bit 2)                                          */
+ #define R_RWP_S_PRCRS_PRC2_Msk     (0x4UL)    /*!< PRC2 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_S_PRCRS_PRC3_Pos     (3UL)      /*!< PRC3 (Bit 3)                                          */
+ #define R_RWP_S_PRCRS_PRC3_Msk     (0x8UL)    /*!< PRC3 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_S_PRCRS_PRKEY_Pos    (8UL)      /*!< PRKEY (Bit 8)                                         */
+ #define R_RWP_S_PRCRS_PRKEY_Msk    (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_MTU                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TOERA  ========================================================= */
+ #define R_MTU_TOERA_OE3B_Pos      (0UL)    /*!< OE3B (Bit 0)                                          */
+ #define R_MTU_TOERA_OE3B_Msk      (0x1UL)  /*!< OE3B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE4A_Pos      (1UL)    /*!< OE4A (Bit 1)                                          */
+ #define R_MTU_TOERA_OE4A_Msk      (0x2UL)  /*!< OE4A (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE4B_Pos      (2UL)    /*!< OE4B (Bit 2)                                          */
+ #define R_MTU_TOERA_OE4B_Msk      (0x4UL)  /*!< OE4B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE3D_Pos      (3UL)    /*!< OE3D (Bit 3)                                          */
+ #define R_MTU_TOERA_OE3D_Msk      (0x8UL)  /*!< OE3D (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE4C_Pos      (4UL)    /*!< OE4C (Bit 4)                                          */
+ #define R_MTU_TOERA_OE4C_Msk      (0x10UL) /*!< OE4C (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE4D_Pos      (5UL)    /*!< OE4D (Bit 5)                                          */
+ #define R_MTU_TOERA_OE4D_Msk      (0x20UL) /*!< OE4D (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TGCRA  ========================================================= */
+ #define R_MTU_TGCRA_UF_Pos        (0UL)    /*!< UF (Bit 0)                                            */
+ #define R_MTU_TGCRA_UF_Msk        (0x1UL)  /*!< UF (Bitfield-Mask: 0x01)                              */
+ #define R_MTU_TGCRA_VF_Pos        (1UL)    /*!< VF (Bit 1)                                            */
+ #define R_MTU_TGCRA_VF_Msk        (0x2UL)  /*!< VF (Bitfield-Mask: 0x01)                              */
+ #define R_MTU_TGCRA_WF_Pos        (2UL)    /*!< WF (Bit 2)                                            */
+ #define R_MTU_TGCRA_WF_Msk        (0x4UL)  /*!< WF (Bitfield-Mask: 0x01)                              */
+ #define R_MTU_TGCRA_FB_Pos        (3UL)    /*!< FB (Bit 3)                                            */
+ #define R_MTU_TGCRA_FB_Msk        (0x8UL)  /*!< FB (Bitfield-Mask: 0x01)                              */
+ #define R_MTU_TGCRA_P_Pos         (4UL)    /*!< P (Bit 4)                                             */
+ #define R_MTU_TGCRA_P_Msk         (0x10UL) /*!< P (Bitfield-Mask: 0x01)                               */
+ #define R_MTU_TGCRA_N_Pos         (5UL)    /*!< N (Bit 5)                                             */
+ #define R_MTU_TGCRA_N_Msk         (0x20UL) /*!< N (Bitfield-Mask: 0x01)                               */
+ #define R_MTU_TGCRA_BDC_Pos       (6UL)    /*!< BDC (Bit 6)                                           */
+ #define R_MTU_TGCRA_BDC_Msk       (0x40UL) /*!< BDC (Bitfield-Mask: 0x01)                             */
+/* ========================================================  TOCR1A  ========================================================= */
+ #define R_MTU_TOCR1A_OLSP_Pos     (0UL)    /*!< OLSP (Bit 0)                                          */
+ #define R_MTU_TOCR1A_OLSP_Msk     (0x1UL)  /*!< OLSP (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1A_OLSN_Pos     (1UL)    /*!< OLSN (Bit 1)                                          */
+ #define R_MTU_TOCR1A_OLSN_Msk     (0x2UL)  /*!< OLSN (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1A_TOCS_Pos     (2UL)    /*!< TOCS (Bit 2)                                          */
+ #define R_MTU_TOCR1A_TOCS_Msk     (0x4UL)  /*!< TOCS (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1A_TOCL_Pos     (3UL)    /*!< TOCL (Bit 3)                                          */
+ #define R_MTU_TOCR1A_TOCL_Msk     (0x8UL)  /*!< TOCL (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1A_PSYE_Pos     (6UL)    /*!< PSYE (Bit 6)                                          */
+ #define R_MTU_TOCR1A_PSYE_Msk     (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOCR2A  ========================================================= */
+ #define R_MTU_TOCR2A_OLS1P_Pos    (0UL)    /*!< OLS1P (Bit 0)                                         */
+ #define R_MTU_TOCR2A_OLS1P_Msk    (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS1N_Pos    (1UL)    /*!< OLS1N (Bit 1)                                         */
+ #define R_MTU_TOCR2A_OLS1N_Msk    (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS2P_Pos    (2UL)    /*!< OLS2P (Bit 2)                                         */
+ #define R_MTU_TOCR2A_OLS2P_Msk    (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS2N_Pos    (3UL)    /*!< OLS2N (Bit 3)                                         */
+ #define R_MTU_TOCR2A_OLS2N_Msk    (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS3P_Pos    (4UL)    /*!< OLS3P (Bit 4)                                         */
+ #define R_MTU_TOCR2A_OLS3P_Msk    (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS3N_Pos    (5UL)    /*!< OLS3N (Bit 5)                                         */
+ #define R_MTU_TOCR2A_OLS3N_Msk    (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_BF_Pos       (6UL)    /*!< BF (Bit 6)                                            */
+ #define R_MTU_TOCR2A_BF_Msk       (0xc0UL) /*!< BF (Bitfield-Mask: 0x03)                              */
+/* =========================================================  TCDRA  ========================================================= */
+/* =========================================================  TDDRA  ========================================================= */
+/* ========================================================  TCNTSA  ========================================================= */
+/* =========================================================  TCBRA  ========================================================= */
+/* ========================================================  TITCR1A  ======================================================== */
+ #define R_MTU_TITCR1A_T4VCOR_Pos      (0UL)    /*!< T4VCOR (Bit 0)                                        */
+ #define R_MTU_TITCR1A_T4VCOR_Msk      (0x7UL)  /*!< T4VCOR (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCR1A_T4VEN_Pos       (3UL)    /*!< T4VEN (Bit 3)                                         */
+ #define R_MTU_TITCR1A_T4VEN_Msk       (0x8UL)  /*!< T4VEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TITCR1A_T3ACOR_Pos      (4UL)    /*!< T3ACOR (Bit 4)                                        */
+ #define R_MTU_TITCR1A_T3ACOR_Msk      (0x70UL) /*!< T3ACOR (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCR1A_T3AEN_Pos       (7UL)    /*!< T3AEN (Bit 7)                                         */
+ #define R_MTU_TITCR1A_T3AEN_Msk       (0x80UL) /*!< T3AEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  TITCNT1A  ======================================================== */
+ #define R_MTU_TITCNT1A_T4VCNT_Pos     (0UL)    /*!< T4VCNT (Bit 0)                                        */
+ #define R_MTU_TITCNT1A_T4VCNT_Msk     (0x7UL)  /*!< T4VCNT (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCNT1A_T3ACNT_Pos     (4UL)    /*!< T3ACNT (Bit 4)                                        */
+ #define R_MTU_TITCNT1A_T3ACNT_Msk     (0x70UL) /*!< T3ACNT (Bitfield-Mask: 0x07)                          */
+/* ========================================================  TBTERA  ========================================================= */
+ #define R_MTU_TBTERA_BTE_Pos          (0UL)    /*!< BTE (Bit 0)                                           */
+ #define R_MTU_TBTERA_BTE_Msk          (0x3UL)  /*!< BTE (Bitfield-Mask: 0x03)                             */
+/* =========================================================  TDERA  ========================================================= */
+ #define R_MTU_TDERA_TDER_Pos          (0UL)    /*!< TDER (Bit 0)                                          */
+ #define R_MTU_TDERA_TDER_Msk          (0x1UL)  /*!< TDER (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOLBRA  ========================================================= */
+ #define R_MTU_TOLBRA_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
+ #define R_MTU_TOLBRA_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
+ #define R_MTU_TOLBRA_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
+ #define R_MTU_TOLBRA_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
+ #define R_MTU_TOLBRA_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
+ #define R_MTU_TOLBRA_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
+ #define R_MTU_TOLBRA_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TITMRA  ========================================================= */
+ #define R_MTU_TITMRA_TITM_Pos         (0UL)    /*!< TITM (Bit 0)                                          */
+ #define R_MTU_TITMRA_TITM_Msk         (0x1UL)  /*!< TITM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TITCR2A  ======================================================== */
+ #define R_MTU_TITCR2A_TRG4COR_Pos     (0UL)    /*!< TRG4COR (Bit 0)                                       */
+ #define R_MTU_TITCR2A_TRG4COR_Msk     (0x7UL)  /*!< TRG4COR (Bitfield-Mask: 0x07)                         */
+/* =======================================================  TITCNT2A  ======================================================== */
+ #define R_MTU_TITCNT2A_TRG4CNT_Pos    (0UL)    /*!< TRG4CNT (Bit 0)                                       */
+ #define R_MTU_TITCNT2A_TRG4CNT_Msk    (0x7UL)  /*!< TRG4CNT (Bitfield-Mask: 0x07)                         */
+/* =========================================================  TWCRA  ========================================================= */
+ #define R_MTU_TWCRA_WRE_Pos           (0UL)    /*!< WRE (Bit 0)                                           */
+ #define R_MTU_TWCRA_WRE_Msk           (0x1UL)  /*!< WRE (Bitfield-Mask: 0x01)                             */
+ #define R_MTU_TWCRA_SCC_Pos           (1UL)    /*!< SCC (Bit 1)                                           */
+ #define R_MTU_TWCRA_SCC_Msk           (0x2UL)  /*!< SCC (Bitfield-Mask: 0x01)                             */
+ #define R_MTU_TWCRA_CCE_Pos           (7UL)    /*!< CCE (Bit 7)                                           */
+ #define R_MTU_TWCRA_CCE_Msk           (0x80UL) /*!< CCE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  TMDR2A  ========================================================= */
+ #define R_MTU_TMDR2A_DRS_Pos          (0UL)    /*!< DRS (Bit 0)                                           */
+ #define R_MTU_TMDR2A_DRS_Msk          (0x1UL)  /*!< DRS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TSTRA  ========================================================= */
+ #define R_MTU_TSTRA_CST0_Pos          (0UL)    /*!< CST0 (Bit 0)                                          */
+ #define R_MTU_TSTRA_CST0_Msk          (0x1UL)  /*!< CST0 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST1_Pos          (1UL)    /*!< CST1 (Bit 1)                                          */
+ #define R_MTU_TSTRA_CST1_Msk          (0x2UL)  /*!< CST1 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST2_Pos          (2UL)    /*!< CST2 (Bit 2)                                          */
+ #define R_MTU_TSTRA_CST2_Msk          (0x4UL)  /*!< CST2 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST8_Pos          (3UL)    /*!< CST8 (Bit 3)                                          */
+ #define R_MTU_TSTRA_CST8_Msk          (0x8UL)  /*!< CST8 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST3_Pos          (6UL)    /*!< CST3 (Bit 6)                                          */
+ #define R_MTU_TSTRA_CST3_Msk          (0x40UL) /*!< CST3 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST4_Pos          (7UL)    /*!< CST4 (Bit 7)                                          */
+ #define R_MTU_TSTRA_CST4_Msk          (0x80UL) /*!< CST4 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TSYRA  ========================================================= */
+ #define R_MTU_TSYRA_SYNC0_Pos         (0UL)    /*!< SYNC0 (Bit 0)                                         */
+ #define R_MTU_TSYRA_SYNC0_Msk         (0x1UL)  /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRA_SYNC1_Pos         (1UL)    /*!< SYNC1 (Bit 1)                                         */
+ #define R_MTU_TSYRA_SYNC1_Msk         (0x2UL)  /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRA_SYNC2_Pos         (2UL)    /*!< SYNC2 (Bit 2)                                         */
+ #define R_MTU_TSYRA_SYNC2_Msk         (0x4UL)  /*!< SYNC2 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRA_SYNC3_Pos         (6UL)    /*!< SYNC3 (Bit 6)                                         */
+ #define R_MTU_TSYRA_SYNC3_Msk         (0x40UL) /*!< SYNC3 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRA_SYNC4_Pos         (7UL)    /*!< SYNC4 (Bit 7)                                         */
+ #define R_MTU_TSYRA_SYNC4_Msk         (0x80UL) /*!< SYNC4 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TCSYSTR  ======================================================== */
+ #define R_MTU_TCSYSTR_SCH7_Pos        (0UL)    /*!< SCH7 (Bit 0)                                          */
+ #define R_MTU_TCSYSTR_SCH7_Msk        (0x1UL)  /*!< SCH7 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH6_Pos        (1UL)    /*!< SCH6 (Bit 1)                                          */
+ #define R_MTU_TCSYSTR_SCH6_Msk        (0x2UL)  /*!< SCH6 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH4_Pos        (3UL)    /*!< SCH4 (Bit 3)                                          */
+ #define R_MTU_TCSYSTR_SCH4_Msk        (0x8UL)  /*!< SCH4 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH3_Pos        (4UL)    /*!< SCH3 (Bit 4)                                          */
+ #define R_MTU_TCSYSTR_SCH3_Msk        (0x10UL) /*!< SCH3 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH2_Pos        (5UL)    /*!< SCH2 (Bit 5)                                          */
+ #define R_MTU_TCSYSTR_SCH2_Msk        (0x20UL) /*!< SCH2 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH1_Pos        (6UL)    /*!< SCH1 (Bit 6)                                          */
+ #define R_MTU_TCSYSTR_SCH1_Msk        (0x40UL) /*!< SCH1 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH0_Pos        (7UL)    /*!< SCH0 (Bit 7)                                          */
+ #define R_MTU_TCSYSTR_SCH0_Msk        (0x80UL) /*!< SCH0 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TRWERA  ========================================================= */
+ #define R_MTU_TRWERA_RWE_Pos          (0UL)    /*!< RWE (Bit 0)                                           */
+ #define R_MTU_TRWERA_RWE_Msk          (0x1UL)  /*!< RWE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TOERB  ========================================================= */
+ #define R_MTU_TOERB_OE6B_Pos          (0UL)    /*!< OE6B (Bit 0)                                          */
+ #define R_MTU_TOERB_OE6B_Msk          (0x1UL)  /*!< OE6B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE7A_Pos          (1UL)    /*!< OE7A (Bit 1)                                          */
+ #define R_MTU_TOERB_OE7A_Msk          (0x2UL)  /*!< OE7A (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE7B_Pos          (2UL)    /*!< OE7B (Bit 2)                                          */
+ #define R_MTU_TOERB_OE7B_Msk          (0x4UL)  /*!< OE7B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE6D_Pos          (3UL)    /*!< OE6D (Bit 3)                                          */
+ #define R_MTU_TOERB_OE6D_Msk          (0x8UL)  /*!< OE6D (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE7C_Pos          (4UL)    /*!< OE7C (Bit 4)                                          */
+ #define R_MTU_TOERB_OE7C_Msk          (0x10UL) /*!< OE7C (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE7D_Pos          (5UL)    /*!< OE7D (Bit 5)                                          */
+ #define R_MTU_TOERB_OE7D_Msk          (0x20UL) /*!< OE7D (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOCR1B  ========================================================= */
+ #define R_MTU_TOCR1B_OLSP_Pos         (0UL)    /*!< OLSP (Bit 0)                                          */
+ #define R_MTU_TOCR1B_OLSP_Msk         (0x1UL)  /*!< OLSP (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1B_OLSN_Pos         (1UL)    /*!< OLSN (Bit 1)                                          */
+ #define R_MTU_TOCR1B_OLSN_Msk         (0x2UL)  /*!< OLSN (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1B_TOCS_Pos         (2UL)    /*!< TOCS (Bit 2)                                          */
+ #define R_MTU_TOCR1B_TOCS_Msk         (0x4UL)  /*!< TOCS (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1B_TOCL_Pos         (3UL)    /*!< TOCL (Bit 3)                                          */
+ #define R_MTU_TOCR1B_TOCL_Msk         (0x8UL)  /*!< TOCL (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1B_PSYE_Pos         (6UL)    /*!< PSYE (Bit 6)                                          */
+ #define R_MTU_TOCR1B_PSYE_Msk         (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOCR2B  ========================================================= */
+ #define R_MTU_TOCR2B_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
+ #define R_MTU_TOCR2B_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
+ #define R_MTU_TOCR2B_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
+ #define R_MTU_TOCR2B_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
+ #define R_MTU_TOCR2B_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
+ #define R_MTU_TOCR2B_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
+ #define R_MTU_TOCR2B_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_BF_Pos           (6UL)    /*!< BF (Bit 6)                                            */
+ #define R_MTU_TOCR2B_BF_Msk           (0xc0UL) /*!< BF (Bitfield-Mask: 0x03)                              */
+/* =========================================================  TCDRB  ========================================================= */
+/* =========================================================  TDDRB  ========================================================= */
+/* ========================================================  TCNTSB  ========================================================= */
+/* =========================================================  TCBRB  ========================================================= */
+/* ========================================================  TITCR1B  ======================================================== */
+ #define R_MTU_TITCR1B_T7VCOR_Pos      (0UL)    /*!< T7VCOR (Bit 0)                                        */
+ #define R_MTU_TITCR1B_T7VCOR_Msk      (0x7UL)  /*!< T7VCOR (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCR1B_T7VEN_Pos       (3UL)    /*!< T7VEN (Bit 3)                                         */
+ #define R_MTU_TITCR1B_T7VEN_Msk       (0x8UL)  /*!< T7VEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TITCR1B_T6ACOR_Pos      (4UL)    /*!< T6ACOR (Bit 4)                                        */
+ #define R_MTU_TITCR1B_T6ACOR_Msk      (0x70UL) /*!< T6ACOR (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCR1B_T6AEN_Pos       (7UL)    /*!< T6AEN (Bit 7)                                         */
+ #define R_MTU_TITCR1B_T6AEN_Msk       (0x80UL) /*!< T6AEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  TITCNT1B  ======================================================== */
+ #define R_MTU_TITCNT1B_T7VCNT_Pos     (0UL)    /*!< T7VCNT (Bit 0)                                        */
+ #define R_MTU_TITCNT1B_T7VCNT_Msk     (0x7UL)  /*!< T7VCNT (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCNT1B_T6ACNT_Pos     (4UL)    /*!< T6ACNT (Bit 4)                                        */
+ #define R_MTU_TITCNT1B_T6ACNT_Msk     (0x70UL) /*!< T6ACNT (Bitfield-Mask: 0x07)                          */
+/* ========================================================  TBTERB  ========================================================= */
+ #define R_MTU_TBTERB_BTE_Pos          (0UL)    /*!< BTE (Bit 0)                                           */
+ #define R_MTU_TBTERB_BTE_Msk          (0x3UL)  /*!< BTE (Bitfield-Mask: 0x03)                             */
+/* =========================================================  TDERB  ========================================================= */
+ #define R_MTU_TDERB_TDER_Pos          (0UL)    /*!< TDER (Bit 0)                                          */
+ #define R_MTU_TDERB_TDER_Msk          (0x1UL)  /*!< TDER (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOLBRB  ========================================================= */
+ #define R_MTU_TOLBRB_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
+ #define R_MTU_TOLBRB_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
+ #define R_MTU_TOLBRB_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
+ #define R_MTU_TOLBRB_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
+ #define R_MTU_TOLBRB_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
+ #define R_MTU_TOLBRB_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
+ #define R_MTU_TOLBRB_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TITMRB  ========================================================= */
+ #define R_MTU_TITMRB_TITM_Pos         (0UL)    /*!< TITM (Bit 0)                                          */
+ #define R_MTU_TITMRB_TITM_Msk         (0x1UL)  /*!< TITM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TITCR2B  ======================================================== */
+ #define R_MTU_TITCR2B_TRG7COR_Pos     (0UL)    /*!< TRG7COR (Bit 0)                                       */
+ #define R_MTU_TITCR2B_TRG7COR_Msk     (0x7UL)  /*!< TRG7COR (Bitfield-Mask: 0x07)                         */
+/* =======================================================  TITCNT2B  ======================================================== */
+ #define R_MTU_TITCNT2B_TRG7CNT_Pos    (0UL)    /*!< TRG7CNT (Bit 0)                                       */
+ #define R_MTU_TITCNT2B_TRG7CNT_Msk    (0x7UL)  /*!< TRG7CNT (Bitfield-Mask: 0x07)                         */
+/* =========================================================  TWCRB  ========================================================= */
+ #define R_MTU_TWCRB_WRE_Pos           (0UL)    /*!< WRE (Bit 0)                                           */
+ #define R_MTU_TWCRB_WRE_Msk           (0x1UL)  /*!< WRE (Bitfield-Mask: 0x01)                             */
+ #define R_MTU_TWCRB_SCC_Pos           (1UL)    /*!< SCC (Bit 1)                                           */
+ #define R_MTU_TWCRB_SCC_Msk           (0x2UL)  /*!< SCC (Bitfield-Mask: 0x01)                             */
+ #define R_MTU_TWCRB_CCE_Pos           (7UL)    /*!< CCE (Bit 7)                                           */
+ #define R_MTU_TWCRB_CCE_Msk           (0x80UL) /*!< CCE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  TMDR2B  ========================================================= */
+ #define R_MTU_TMDR2B_DRS_Pos          (0UL)    /*!< DRS (Bit 0)                                           */
+ #define R_MTU_TMDR2B_DRS_Msk          (0x1UL)  /*!< DRS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TSTRB  ========================================================= */
+ #define R_MTU_TSTRB_CST6_Pos          (6UL)    /*!< CST6 (Bit 6)                                          */
+ #define R_MTU_TSTRB_CST6_Msk          (0x40UL) /*!< CST6 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRB_CST7_Pos          (7UL)    /*!< CST7 (Bit 7)                                          */
+ #define R_MTU_TSTRB_CST7_Msk          (0x80UL) /*!< CST7 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TSYRB  ========================================================= */
+ #define R_MTU_TSYRB_SYNC6_Pos         (6UL)    /*!< SYNC6 (Bit 6)                                         */
+ #define R_MTU_TSYRB_SYNC6_Msk         (0x40UL) /*!< SYNC6 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRB_SYNC7_Pos         (7UL)    /*!< SYNC7 (Bit 7)                                         */
+ #define R_MTU_TSYRB_SYNC7_Msk         (0x80UL) /*!< SYNC7 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TRWERB  ========================================================= */
+ #define R_MTU_TRWERB_RWE_Pos          (0UL)    /*!< RWE (Bit 0)                                           */
+ #define R_MTU_TRWERB_RWE_Msk          (0x1UL)  /*!< RWE (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU3                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU3_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU3_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU3_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU3_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU3_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU3_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU3_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU3_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU3_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU3_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU3_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU3_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU3_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU3_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU3_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU3_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU3_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU3_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU3_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU3_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU3_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU3_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU3_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU3_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU3_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU3_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU3_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU3_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
+ #define R_MTU3_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
+ #define R_MTU3_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
+ #define R_MTU3_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
+ #define R_MTU3_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
+ #define R_MTU3_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
+ #define R_MTU3_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
+ #define R_MTU3_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU3_TBTM_TTSA_Pos     (0UL)    /*!< TTSA (Bit 0)                                          */
+ #define R_MTU3_TBTM_TTSA_Msk     (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TBTM_TTSB_Pos     (1UL)    /*!< TTSB (Bit 1)                                          */
+ #define R_MTU3_TBTM_TTSB_Msk     (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU3_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU3_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TGRE  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU4                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU4_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU4_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU4_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU4_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU4_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU4_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU4_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU4_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU4_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU4_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU4_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU4_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU4_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU4_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU4_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU4_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU4_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU4_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU4_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU4_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU4_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU4_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU4_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU4_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU4_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU4_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TTGE2_Pos    (6UL)    /*!< TTGE2 (Bit 6)                                         */
+ #define R_MTU4_TIER_TTGE2_Msk    (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU4_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU4_TSR_TGFA_Pos        (0UL)      /*!< TGFA (Bit 0)                                          */
+ #define R_MTU4_TSR_TGFA_Msk        (0x1UL)    /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TGFB_Pos        (1UL)      /*!< TGFB (Bit 1)                                          */
+ #define R_MTU4_TSR_TGFB_Msk        (0x2UL)    /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TGFC_Pos        (2UL)      /*!< TGFC (Bit 2)                                          */
+ #define R_MTU4_TSR_TGFC_Msk        (0x4UL)    /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TGFD_Pos        (3UL)      /*!< TGFD (Bit 3)                                          */
+ #define R_MTU4_TSR_TGFD_Msk        (0x8UL)    /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TCFV_Pos        (4UL)      /*!< TCFV (Bit 4)                                          */
+ #define R_MTU4_TSR_TCFV_Msk        (0x10UL)   /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TCFU_Pos        (5UL)      /*!< TCFU (Bit 5)                                          */
+ #define R_MTU4_TSR_TCFU_Msk        (0x20UL)   /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TCFD_Pos        (7UL)      /*!< TCFD (Bit 7)                                          */
+ #define R_MTU4_TSR_TCFD_Msk        (0x80UL)   /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU4_TBTM_TTSA_Pos       (0UL)      /*!< TTSA (Bit 0)                                          */
+ #define R_MTU4_TBTM_TTSA_Msk       (0x1UL)    /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TBTM_TTSB_Pos       (1UL)      /*!< TTSB (Bit 1)                                          */
+ #define R_MTU4_TBTM_TTSB_Msk       (0x2UL)    /*!< TTSB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TADCR  ========================================================= */
+ #define R_MTU4_TADCR_ITB4VE_Pos    (0UL)      /*!< ITB4VE (Bit 0)                                        */
+ #define R_MTU4_TADCR_ITB4VE_Msk    (0x1UL)    /*!< ITB4VE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU4_TADCR_ITB3AE_Pos    (1UL)      /*!< ITB3AE (Bit 1)                                        */
+ #define R_MTU4_TADCR_ITB3AE_Msk    (0x2UL)    /*!< ITB3AE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU4_TADCR_ITA4VE_Pos    (2UL)      /*!< ITA4VE (Bit 2)                                        */
+ #define R_MTU4_TADCR_ITA4VE_Msk    (0x4UL)    /*!< ITA4VE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU4_TADCR_ITA3AE_Pos    (3UL)      /*!< ITA3AE (Bit 3)                                        */
+ #define R_MTU4_TADCR_ITA3AE_Msk    (0x8UL)    /*!< ITA3AE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU4_TADCR_DT4BE_Pos     (4UL)      /*!< DT4BE (Bit 4)                                         */
+ #define R_MTU4_TADCR_DT4BE_Msk     (0x10UL)   /*!< DT4BE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TADCR_UT4BE_Pos     (5UL)      /*!< UT4BE (Bit 5)                                         */
+ #define R_MTU4_TADCR_UT4BE_Msk     (0x20UL)   /*!< UT4BE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TADCR_DT4AE_Pos     (6UL)      /*!< DT4AE (Bit 6)                                         */
+ #define R_MTU4_TADCR_DT4AE_Msk     (0x40UL)   /*!< DT4AE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TADCR_UT4AE_Pos     (7UL)      /*!< UT4AE (Bit 7)                                         */
+ #define R_MTU4_TADCR_UT4AE_Msk     (0x80UL)   /*!< UT4AE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TADCR_BF_Pos        (14UL)     /*!< BF (Bit 14)                                           */
+ #define R_MTU4_TADCR_BF_Msk        (0xc000UL) /*!< BF (Bitfield-Mask: 0x03)                              */
+/* ========================================================  TADCORA  ======================================================== */
+/* ========================================================  TADCORB  ======================================================== */
+/* =======================================================  TADCOBRA  ======================================================== */
+/* =======================================================  TADCOBRB  ======================================================== */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU4_TCR2_TPSC2_Pos    (0UL)   /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU4_TCR2_TPSC2_Msk    (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TGRE  ========================================================== */
+/* =========================================================  TGRF  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MTU_NF                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  NFCR0  ========================================================= */
+ #define R_MTU_NF_NFCR0_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR0_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR0_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR0_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR0_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR0_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR0_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR0_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR0_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR0_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR1  ========================================================= */
+ #define R_MTU_NF_NFCR1_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR1_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR1_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR1_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR1_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR1_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR2  ========================================================= */
+ #define R_MTU_NF_NFCR2_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR2_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR2_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR2_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR2_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR2_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR3  ========================================================= */
+ #define R_MTU_NF_NFCR3_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR3_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR3_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR3_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR3_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR3_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR3_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR3_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR3_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR3_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR4  ========================================================= */
+ #define R_MTU_NF_NFCR4_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR4_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR4_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR4_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR4_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR4_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR4_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR4_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR4_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR4_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR8  ========================================================= */
+ #define R_MTU_NF_NFCR8_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR8_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR8_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR8_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR8_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR8_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR8_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR8_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR8_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR8_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCRC  ========================================================= */
+ #define R_MTU_NF_NFCRC_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCRC_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCRC_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCRC_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCRC_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCRC_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCRC_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCRC_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCRC_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCRC_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR6  ========================================================= */
+ #define R_MTU_NF_NFCR6_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR6_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR6_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR6_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR6_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR6_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR6_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR6_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR6_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR6_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR7  ========================================================= */
+ #define R_MTU_NF_NFCR7_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR7_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR7_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR7_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR7_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR7_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR7_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR7_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR7_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR7_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR5  ========================================================= */
+ #define R_MTU_NF_NFCR5_NFUEN_Pos    (0UL)    /*!< NFUEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR5_NFUEN_Msk    (0x1UL)  /*!< NFUEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR5_NFVEN_Pos    (1UL)    /*!< NFVEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR5_NFVEN_Msk    (0x2UL)  /*!< NFVEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR5_NFWEN_Pos    (2UL)    /*!< NFWEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR5_NFWEN_Msk    (0x4UL)  /*!< NFWEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR5_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR5_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU0_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU0_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU0_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU0_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU0_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU0_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU0_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU0_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU0_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU0_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU0_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU0_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+ #define R_MTU0_TMDR1_BFE_Pos     (6UL)    /*!< BFE (Bit 6)                                           */
+ #define R_MTU0_TMDR1_BFE_Msk     (0x40UL) /*!< BFE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU0_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU0_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU0_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU0_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU0_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU0_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU0_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU0_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU0_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU0_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU0_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU0_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU0_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU0_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU0_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* =========================================================  TGRE  ========================================================== */
+/* =========================================================  TGRF  ========================================================== */
+/* =========================================================  TIER2  ========================================================= */
+ #define R_MTU0_TIER2_TGIEE_Pos    (0UL)    /*!< TGIEE (Bit 0)                                         */
+ #define R_MTU0_TIER2_TGIEE_Msk    (0x1UL)  /*!< TGIEE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER2_TGIEF_Pos    (1UL)    /*!< TGIEF (Bit 1)                                         */
+ #define R_MTU0_TIER2_TGIEF_Msk    (0x2UL)  /*!< TGIEF (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER2_TTGE2_Pos    (7UL)    /*!< TTGE2 (Bit 7)                                         */
+ #define R_MTU0_TIER2_TTGE2_Msk    (0x80UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU0_TBTM_TTSA_Pos      (0UL)    /*!< TTSA (Bit 0)                                          */
+ #define R_MTU0_TBTM_TTSA_Msk      (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU0_TBTM_TTSB_Pos      (1UL)    /*!< TTSB (Bit 1)                                          */
+ #define R_MTU0_TBTM_TTSB_Msk      (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU0_TBTM_TTSE_Pos      (2UL)    /*!< TTSE (Bit 2)                                          */
+ #define R_MTU0_TBTM_TTSE_Msk      (0x4UL)  /*!< TTSE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU0_TCR2_TPSC2_Pos     (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU0_TCR2_TPSC2_Msk     (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU1                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU1_TCR_TPSC_Pos         (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU1_TCR_TPSC_Msk         (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU1_TCR_CKEG_Pos         (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU1_TCR_CKEG_Msk         (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU1_TCR_CCLR_Pos         (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU1_TCR_CCLR_Msk         (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU1_TMDR1_MD_Pos         (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU1_TMDR1_MD_Msk         (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+/* =========================================================  TIOR  ========================================================== */
+ #define R_MTU1_TIOR_IOA_Pos         (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU1_TIOR_IOA_Msk         (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU1_TIOR_IOB_Pos         (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU1_TIOR_IOB_Msk         (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU1_TIER_TGIEA_Pos       (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU1_TIER_TGIEA_Msk       (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU1_TIER_TGIEB_Pos       (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU1_TIER_TGIEB_Msk       (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU1_TIER_TCIEV_Pos       (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU1_TIER_TCIEV_Msk       (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU1_TIER_TCIEU_Pos       (5UL)    /*!< TCIEU (Bit 5)                                         */
+ #define R_MTU1_TIER_TCIEU_Msk       (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01)                           */
+ #define R_MTU1_TIER_TTGE_Pos        (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU1_TIER_TTGE_Msk        (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU1_TSR_TGFA_Pos         (0UL)    /*!< TGFA (Bit 0)                                          */
+ #define R_MTU1_TSR_TGFA_Msk         (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TGFB_Pos         (1UL)    /*!< TGFB (Bit 1)                                          */
+ #define R_MTU1_TSR_TGFB_Msk         (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TGFC_Pos         (2UL)    /*!< TGFC (Bit 2)                                          */
+ #define R_MTU1_TSR_TGFC_Msk         (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TGFD_Pos         (3UL)    /*!< TGFD (Bit 3)                                          */
+ #define R_MTU1_TSR_TGFD_Msk         (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TCFV_Pos         (4UL)    /*!< TCFV (Bit 4)                                          */
+ #define R_MTU1_TSR_TCFV_Msk         (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TCFU_Pos         (5UL)    /*!< TCFU (Bit 5)                                          */
+ #define R_MTU1_TSR_TCFU_Msk         (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TCFD_Pos         (7UL)    /*!< TCFD (Bit 7)                                          */
+ #define R_MTU1_TSR_TCFD_Msk         (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TICCR  ========================================================= */
+ #define R_MTU1_TICCR_I1AE_Pos       (0UL)    /*!< I1AE (Bit 0)                                          */
+ #define R_MTU1_TICCR_I1AE_Msk       (0x1UL)  /*!< I1AE (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TICCR_I1BE_Pos       (1UL)    /*!< I1BE (Bit 1)                                          */
+ #define R_MTU1_TICCR_I1BE_Msk       (0x2UL)  /*!< I1BE (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TICCR_I2AE_Pos       (2UL)    /*!< I2AE (Bit 2)                                          */
+ #define R_MTU1_TICCR_I2AE_Msk       (0x4UL)  /*!< I2AE (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TICCR_I2BE_Pos       (3UL)    /*!< I2BE (Bit 3)                                          */
+ #define R_MTU1_TICCR_I2BE_Msk       (0x8UL)  /*!< I2BE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TMDR3  ========================================================= */
+ #define R_MTU1_TMDR3_LWA_Pos        (0UL)    /*!< LWA (Bit 0)                                           */
+ #define R_MTU1_TMDR3_LWA_Msk        (0x1UL)  /*!< LWA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU1_TMDR3_PHCKSEL_Pos    (1UL)    /*!< PHCKSEL (Bit 1)                                       */
+ #define R_MTU1_TMDR3_PHCKSEL_Msk    (0x2UL)  /*!< PHCKSEL (Bitfield-Mask: 0x01)                         */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU1_TCR2_TPSC2_Pos       (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU1_TCR2_TPSC2_Msk       (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU1_TCR2_PCB_Pos         (3UL)    /*!< PCB (Bit 3)                                           */
+ #define R_MTU1_TCR2_PCB_Msk         (0x18UL) /*!< PCB (Bitfield-Mask: 0x03)                             */
+/* ========================================================  TCNTLW  ========================================================= */
+/* ========================================================  TGRALW  ========================================================= */
+/* ========================================================  TGRBLW  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU2                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU2_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU2_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU2_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU2_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU2_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU2_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU2_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU2_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+/* =========================================================  TIOR  ========================================================== */
+ #define R_MTU2_TIOR_IOA_Pos      (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU2_TIOR_IOA_Msk      (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU2_TIOR_IOB_Pos      (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU2_TIOR_IOB_Msk      (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU2_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU2_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU2_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU2_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU2_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU2_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU2_TIER_TCIEU_Pos    (5UL)    /*!< TCIEU (Bit 5)                                         */
+ #define R_MTU2_TIER_TCIEU_Msk    (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01)                           */
+ #define R_MTU2_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU2_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU2_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
+ #define R_MTU2_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
+ #define R_MTU2_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
+ #define R_MTU2_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
+ #define R_MTU2_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
+ #define R_MTU2_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
+ #define R_MTU2_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
+ #define R_MTU2_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU2_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU2_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU2_TCR2_PCB_Pos      (3UL)    /*!< PCB (Bit 3)                                           */
+ #define R_MTU2_TCR2_PCB_Msk      (0x18UL) /*!< PCB (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU8                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU8_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU8_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU8_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU8_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU8_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU8_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU8_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU8_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU8_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU8_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU8_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU8_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU8_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU8_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU8_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU8_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU8_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU8_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU8_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU8_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU8_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU8_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU8_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU8_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU8_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU8_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU8_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU8_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU8_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU8_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU8_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU8_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU6                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU6_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU6_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU6_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU6_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU6_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU6_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU6_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU6_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU6_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU6_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU6_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU6_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU6_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU6_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU6_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU6_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU6_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU6_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU6_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU6_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU6_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU6_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU6_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU6_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU6_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU6_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU6_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU6_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
+ #define R_MTU6_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
+ #define R_MTU6_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
+ #define R_MTU6_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
+ #define R_MTU6_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
+ #define R_MTU6_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
+ #define R_MTU6_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
+ #define R_MTU6_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU6_TBTM_TTSA_Pos     (0UL)    /*!< TTSA (Bit 0)                                          */
+ #define R_MTU6_TBTM_TTSA_Msk     (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TBTM_TTSB_Pos     (1UL)    /*!< TTSB (Bit 1)                                          */
+ #define R_MTU6_TBTM_TTSB_Msk     (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU6_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU6_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TSYCR  ========================================================= */
+ #define R_MTU6_TSYCR_CE2B_Pos    (0UL)    /*!< CE2B (Bit 0)                                          */
+ #define R_MTU6_TSYCR_CE2B_Msk    (0x1UL)  /*!< CE2B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE2A_Pos    (1UL)    /*!< CE2A (Bit 1)                                          */
+ #define R_MTU6_TSYCR_CE2A_Msk    (0x2UL)  /*!< CE2A (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE1B_Pos    (2UL)    /*!< CE1B (Bit 2)                                          */
+ #define R_MTU6_TSYCR_CE1B_Msk    (0x4UL)  /*!< CE1B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE1A_Pos    (3UL)    /*!< CE1A (Bit 3)                                          */
+ #define R_MTU6_TSYCR_CE1A_Msk    (0x8UL)  /*!< CE1A (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE0D_Pos    (4UL)    /*!< CE0D (Bit 4)                                          */
+ #define R_MTU6_TSYCR_CE0D_Msk    (0x10UL) /*!< CE0D (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE0C_Pos    (5UL)    /*!< CE0C (Bit 5)                                          */
+ #define R_MTU6_TSYCR_CE0C_Msk    (0x20UL) /*!< CE0C (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE0B_Pos    (6UL)    /*!< CE0B (Bit 6)                                          */
+ #define R_MTU6_TSYCR_CE0B_Msk    (0x40UL) /*!< CE0B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE0A_Pos    (7UL)    /*!< CE0A (Bit 7)                                          */
+ #define R_MTU6_TSYCR_CE0A_Msk    (0x80UL) /*!< CE0A (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TGRE  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU7                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU7_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU7_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU7_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU7_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU7_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU7_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU7_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU7_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU7_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU7_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU7_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU7_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU7_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU7_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU7_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU7_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU7_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU7_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU7_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU7_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU7_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU7_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU7_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU7_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU7_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU7_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TTGE2_Pos    (6UL)    /*!< TTGE2 (Bit 6)                                         */
+ #define R_MTU7_TIER_TTGE2_Msk    (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU7_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU7_TSR_TGFA_Pos        (0UL)      /*!< TGFA (Bit 0)                                          */
+ #define R_MTU7_TSR_TGFA_Msk        (0x1UL)    /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TGFB_Pos        (1UL)      /*!< TGFB (Bit 1)                                          */
+ #define R_MTU7_TSR_TGFB_Msk        (0x2UL)    /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TGFC_Pos        (2UL)      /*!< TGFC (Bit 2)                                          */
+ #define R_MTU7_TSR_TGFC_Msk        (0x4UL)    /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TGFD_Pos        (3UL)      /*!< TGFD (Bit 3)                                          */
+ #define R_MTU7_TSR_TGFD_Msk        (0x8UL)    /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TCFV_Pos        (4UL)      /*!< TCFV (Bit 4)                                          */
+ #define R_MTU7_TSR_TCFV_Msk        (0x10UL)   /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TCFU_Pos        (5UL)      /*!< TCFU (Bit 5)                                          */
+ #define R_MTU7_TSR_TCFU_Msk        (0x20UL)   /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TCFD_Pos        (7UL)      /*!< TCFD (Bit 7)                                          */
+ #define R_MTU7_TSR_TCFD_Msk        (0x80UL)   /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU7_TBTM_TTSA_Pos       (0UL)      /*!< TTSA (Bit 0)                                          */
+ #define R_MTU7_TBTM_TTSA_Msk       (0x1UL)    /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TBTM_TTSB_Pos       (1UL)      /*!< TTSB (Bit 1)                                          */
+ #define R_MTU7_TBTM_TTSB_Msk       (0x2UL)    /*!< TTSB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TADCR  ========================================================= */
+ #define R_MTU7_TADCR_ITB7VE_Pos    (0UL)      /*!< ITB7VE (Bit 0)                                        */
+ #define R_MTU7_TADCR_ITB7VE_Msk    (0x1UL)    /*!< ITB7VE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU7_TADCR_ITB6AE_Pos    (1UL)      /*!< ITB6AE (Bit 1)                                        */
+ #define R_MTU7_TADCR_ITB6AE_Msk    (0x2UL)    /*!< ITB6AE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU7_TADCR_ITA7VE_Pos    (2UL)      /*!< ITA7VE (Bit 2)                                        */
+ #define R_MTU7_TADCR_ITA7VE_Msk    (0x4UL)    /*!< ITA7VE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU7_TADCR_ITA6AE_Pos    (3UL)      /*!< ITA6AE (Bit 3)                                        */
+ #define R_MTU7_TADCR_ITA6AE_Msk    (0x8UL)    /*!< ITA6AE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU7_TADCR_DT7BE_Pos     (4UL)      /*!< DT7BE (Bit 4)                                         */
+ #define R_MTU7_TADCR_DT7BE_Msk     (0x10UL)   /*!< DT7BE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TADCR_UT7BE_Pos     (5UL)      /*!< UT7BE (Bit 5)                                         */
+ #define R_MTU7_TADCR_UT7BE_Msk     (0x20UL)   /*!< UT7BE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TADCR_DT7AE_Pos     (6UL)      /*!< DT7AE (Bit 6)                                         */
+ #define R_MTU7_TADCR_DT7AE_Msk     (0x40UL)   /*!< DT7AE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TADCR_UT7AE_Pos     (7UL)      /*!< UT7AE (Bit 7)                                         */
+ #define R_MTU7_TADCR_UT7AE_Msk     (0x80UL)   /*!< UT7AE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TADCR_BF_Pos        (14UL)     /*!< BF (Bit 14)                                           */
+ #define R_MTU7_TADCR_BF_Msk        (0xc000UL) /*!< BF (Bitfield-Mask: 0x03)                              */
+/* ========================================================  TADCORA  ======================================================== */
+/* ========================================================  TADCORB  ======================================================== */
+/* =======================================================  TADCOBRA  ======================================================== */
+/* =======================================================  TADCOBRB  ======================================================== */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU7_TCR2_TPSC2_Pos    (0UL)   /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU7_TCR2_TPSC2_Msk    (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TGRE  ========================================================== */
+/* =========================================================  TGRF  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU5                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TCNTU  ========================================================= */
+/* =========================================================  TGRU  ========================================================== */
+/* =========================================================  TCRU  ========================================================== */
+ #define R_MTU5_TCRU_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU5_TCRU_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TCR2U  ========================================================= */
+ #define R_MTU5_TCR2U_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU5_TCR2U_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU5_TCR2U_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU5_TCR2U_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TIORU  ========================================================= */
+ #define R_MTU5_TIORU_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU5_TIORU_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  TCNTV  ========================================================= */
+/* =========================================================  TGRV  ========================================================== */
+/* =========================================================  TCRV  ========================================================== */
+ #define R_MTU5_TCRV_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU5_TCRV_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TCR2V  ========================================================= */
+ #define R_MTU5_TCR2V_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU5_TCR2V_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU5_TCR2V_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU5_TCR2V_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TIORV  ========================================================= */
+ #define R_MTU5_TIORV_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU5_TIORV_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  TCNTW  ========================================================= */
+/* =========================================================  TGRW  ========================================================== */
+/* =========================================================  TCRW  ========================================================== */
+ #define R_MTU5_TCRW_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU5_TCRW_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TCR2W  ========================================================= */
+ #define R_MTU5_TCR2W_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU5_TCR2W_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU5_TCR2W_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU5_TCR2W_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TIORW  ========================================================= */
+ #define R_MTU5_TIORW_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU5_TIORW_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU5_TIER_TGIE5W_Pos            (0UL)    /*!< TGIE5W (Bit 0)                                        */
+ #define R_MTU5_TIER_TGIE5W_Msk            (0x1UL)  /*!< TGIE5W (Bitfield-Mask: 0x01)                          */
+ #define R_MTU5_TIER_TGIE5V_Pos            (1UL)    /*!< TGIE5V (Bit 1)                                        */
+ #define R_MTU5_TIER_TGIE5V_Msk            (0x2UL)  /*!< TGIE5V (Bitfield-Mask: 0x01)                          */
+ #define R_MTU5_TIER_TGIE5U_Pos            (2UL)    /*!< TGIE5U (Bit 2)                                        */
+ #define R_MTU5_TIER_TGIE5U_Msk            (0x4UL)  /*!< TGIE5U (Bitfield-Mask: 0x01)                          */
+/* =========================================================  TSTR  ========================================================== */
+ #define R_MTU5_TSTR_CSTW5_Pos             (0UL)    /*!< CSTW5 (Bit 0)                                         */
+ #define R_MTU5_TSTR_CSTW5_Msk             (0x1UL)  /*!< CSTW5 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU5_TSTR_CSTV5_Pos             (1UL)    /*!< CSTV5 (Bit 1)                                         */
+ #define R_MTU5_TSTR_CSTV5_Msk             (0x2UL)  /*!< CSTV5 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU5_TSTR_CSTU5_Pos             (2UL)    /*!< CSTU5 (Bit 2)                                         */
+ #define R_MTU5_TSTR_CSTU5_Msk             (0x4UL)  /*!< CSTU5 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  TCNTCMPCLR  ======================================================= */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Pos    (0UL)    /*!< CMPCLR5W (Bit 0)                                      */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Msk    (0x1UL)  /*!< CMPCLR5W (Bitfield-Mask: 0x01)                        */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Pos    (1UL)    /*!< CMPCLR5V (Bit 1)                                      */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Msk    (0x2UL)  /*!< CMPCLR5V (Bitfield-Mask: 0x01)                        */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Pos    (2UL)    /*!< CMPCLR5U (Bit 2)                                      */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Msk    (0x4UL)  /*!< CMPCLR5U (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TFU                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  TRGSTS  ========================================================= */
+ #define R_TFU_TRGSTS_BSYF_Pos    (0UL)          /*!< BSYF (Bit 0)                                          */
+ #define R_TFU_TRGSTS_BSYF_Msk    (0x1UL)        /*!< BSYF (Bitfield-Mask: 0x01)                            */
+ #define R_TFU_TRGSTS_ERRF_Pos    (1UL)          /*!< ERRF (Bit 1)                                          */
+ #define R_TFU_TRGSTS_ERRF_Msk    (0x2UL)        /*!< ERRF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SCDT0  ========================================================= */
+ #define R_TFU_SCDT0_SCDT0_Pos    (0UL)          /*!< SCDT0 (Bit 0)                                         */
+ #define R_TFU_SCDT0_SCDT0_Msk    (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  SCDT1  ========================================================= */
+ #define R_TFU_SCDT1_SCDT1_Pos    (0UL)          /*!< SCDT1 (Bit 0)                                         */
+ #define R_TFU_SCDT1_SCDT1_Msk    (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  ATDT0  ========================================================= */
+ #define R_TFU_ATDT0_ATDT0_Pos    (0UL)          /*!< ATDT0 (Bit 0)                                         */
+ #define R_TFU_ATDT0_ATDT0_Msk    (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  ATDT1  ========================================================= */
+ #define R_TFU_ATDT1_ATDT1_Pos    (0UL)          /*!< ATDT1 (Bit 0)                                         */
+ #define R_TFU_ATDT1_ATDT1_Msk    (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POE3                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ICSR1  ========================================================= */
+ #define R_POE3_ICSR1_POE0M_Pos            (0UL)      /*!< POE0M (Bit 0)                                         */
+ #define R_POE3_ICSR1_POE0M_Msk            (0x3UL)    /*!< POE0M (Bitfield-Mask: 0x03)                           */
+ #define R_POE3_ICSR1_PIE1_Pos             (8UL)      /*!< PIE1 (Bit 8)                                          */
+ #define R_POE3_ICSR1_PIE1_Msk             (0x100UL)  /*!< PIE1 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR1_POE0F_Pos            (12UL)     /*!< POE0F (Bit 12)                                        */
+ #define R_POE3_ICSR1_POE0F_Msk            (0x1000UL) /*!< POE0F (Bitfield-Mask: 0x01)                           */
+/* =========================================================  OCSR1  ========================================================= */
+ #define R_POE3_OCSR1_OIE1_Pos             (8UL)      /*!< OIE1 (Bit 8)                                          */
+ #define R_POE3_OCSR1_OIE1_Msk             (0x100UL)  /*!< OIE1 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_OCSR1_OCE1_Pos             (9UL)      /*!< OCE1 (Bit 9)                                          */
+ #define R_POE3_OCSR1_OCE1_Msk             (0x200UL)  /*!< OCE1 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_OCSR1_OSF1_Pos             (15UL)     /*!< OSF1 (Bit 15)                                         */
+ #define R_POE3_OCSR1_OSF1_Msk             (0x8000UL) /*!< OSF1 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSR2  ========================================================= */
+ #define R_POE3_ICSR2_POE4M_Pos            (0UL)      /*!< POE4M (Bit 0)                                         */
+ #define R_POE3_ICSR2_POE4M_Msk            (0x3UL)    /*!< POE4M (Bitfield-Mask: 0x03)                           */
+ #define R_POE3_ICSR2_PIE2_Pos             (8UL)      /*!< PIE2 (Bit 8)                                          */
+ #define R_POE3_ICSR2_PIE2_Msk             (0x100UL)  /*!< PIE2 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR2_POE4F_Pos            (12UL)     /*!< POE4F (Bit 12)                                        */
+ #define R_POE3_ICSR2_POE4F_Msk            (0x1000UL) /*!< POE4F (Bitfield-Mask: 0x01)                           */
+/* =========================================================  OCSR2  ========================================================= */
+ #define R_POE3_OCSR2_OIE2_Pos             (8UL)      /*!< OIE2 (Bit 8)                                          */
+ #define R_POE3_OCSR2_OIE2_Msk             (0x100UL)  /*!< OIE2 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_OCSR2_OCE2_Pos             (9UL)      /*!< OCE2 (Bit 9)                                          */
+ #define R_POE3_OCSR2_OCE2_Msk             (0x200UL)  /*!< OCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_OCSR2_OSF2_Pos             (15UL)     /*!< OSF2 (Bit 15)                                         */
+ #define R_POE3_OCSR2_OSF2_Msk             (0x8000UL) /*!< OSF2 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSR3  ========================================================= */
+ #define R_POE3_ICSR3_POE8M_Pos            (0UL)      /*!< POE8M (Bit 0)                                         */
+ #define R_POE3_ICSR3_POE8M_Msk            (0x3UL)    /*!< POE8M (Bitfield-Mask: 0x03)                           */
+ #define R_POE3_ICSR3_PIE3_Pos             (8UL)      /*!< PIE3 (Bit 8)                                          */
+ #define R_POE3_ICSR3_PIE3_Msk             (0x100UL)  /*!< PIE3 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR3_POE8E_Pos            (9UL)      /*!< POE8E (Bit 9)                                         */
+ #define R_POE3_ICSR3_POE8E_Msk            (0x200UL)  /*!< POE8E (Bitfield-Mask: 0x01)                           */
+ #define R_POE3_ICSR3_POE8F_Pos            (12UL)     /*!< POE8F (Bit 12)                                        */
+ #define R_POE3_ICSR3_POE8F_Msk            (0x1000UL) /*!< POE8F (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPOER  ========================================================= */
+ #define R_POE3_SPOER_MTUCH34HIZ_Pos       (0UL)      /*!< MTUCH34HIZ (Bit 0)                                    */
+ #define R_POE3_SPOER_MTUCH34HIZ_Msk       (0x1UL)    /*!< MTUCH34HIZ (Bitfield-Mask: 0x01)                      */
+ #define R_POE3_SPOER_MTUCH67HIZ_Pos       (1UL)      /*!< MTUCH67HIZ (Bit 1)                                    */
+ #define R_POE3_SPOER_MTUCH67HIZ_Msk       (0x2UL)    /*!< MTUCH67HIZ (Bitfield-Mask: 0x01)                      */
+ #define R_POE3_SPOER_MTUCH0HIZ_Pos        (2UL)      /*!< MTUCH0HIZ (Bit 2)                                     */
+ #define R_POE3_SPOER_MTUCH0HIZ_Msk        (0x4UL)    /*!< MTUCH0HIZ (Bitfield-Mask: 0x01)                       */
+/* ========================================================  POECR1  ========================================================= */
+ #define R_POE3_POECR1_MTU0AZE_Pos         (0UL)      /*!< MTU0AZE (Bit 0)                                       */
+ #define R_POE3_POECR1_MTU0AZE_Msk         (0x1UL)    /*!< MTU0AZE (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_POECR1_MTU0BZE_Pos         (1UL)      /*!< MTU0BZE (Bit 1)                                       */
+ #define R_POE3_POECR1_MTU0BZE_Msk         (0x2UL)    /*!< MTU0BZE (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_POECR1_MTU0CZE_Pos         (2UL)      /*!< MTU0CZE (Bit 2)                                       */
+ #define R_POE3_POECR1_MTU0CZE_Msk         (0x4UL)    /*!< MTU0CZE (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_POECR1_MTU0DZE_Pos         (3UL)      /*!< MTU0DZE (Bit 3)                                       */
+ #define R_POE3_POECR1_MTU0DZE_Msk         (0x8UL)    /*!< MTU0DZE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  POECR2  ========================================================= */
+ #define R_POE3_POECR2_MTU7BDZE_Pos        (0UL)      /*!< MTU7BDZE (Bit 0)                                      */
+ #define R_POE3_POECR2_MTU7BDZE_Msk        (0x1UL)    /*!< MTU7BDZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU7ACZE_Pos        (1UL)      /*!< MTU7ACZE (Bit 1)                                      */
+ #define R_POE3_POECR2_MTU7ACZE_Msk        (0x2UL)    /*!< MTU7ACZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU6BDZE_Pos        (2UL)      /*!< MTU6BDZE (Bit 2)                                      */
+ #define R_POE3_POECR2_MTU6BDZE_Msk        (0x4UL)    /*!< MTU6BDZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU4BDZE_Pos        (8UL)      /*!< MTU4BDZE (Bit 8)                                      */
+ #define R_POE3_POECR2_MTU4BDZE_Msk        (0x100UL)  /*!< MTU4BDZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU4ACZE_Pos        (9UL)      /*!< MTU4ACZE (Bit 9)                                      */
+ #define R_POE3_POECR2_MTU4ACZE_Msk        (0x200UL)  /*!< MTU4ACZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU3BDZE_Pos        (10UL)     /*!< MTU3BDZE (Bit 10)                                     */
+ #define R_POE3_POECR2_MTU3BDZE_Msk        (0x400UL)  /*!< MTU3BDZE (Bitfield-Mask: 0x01)                        */
+/* ========================================================  POECR4  ========================================================= */
+ #define R_POE3_POECR4_IC2ADDMT34ZE_Pos    (2UL)      /*!< IC2ADDMT34ZE (Bit 2)                                  */
+ #define R_POE3_POECR4_IC2ADDMT34ZE_Msk    (0x4UL)    /*!< IC2ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC3ADDMT34ZE_Pos    (3UL)      /*!< IC3ADDMT34ZE (Bit 3)                                  */
+ #define R_POE3_POECR4_IC3ADDMT34ZE_Msk    (0x8UL)    /*!< IC3ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC4ADDMT34ZE_Pos    (4UL)      /*!< IC4ADDMT34ZE (Bit 4)                                  */
+ #define R_POE3_POECR4_IC4ADDMT34ZE_Msk    (0x10UL)   /*!< IC4ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC5ADDMT34ZE_Pos    (5UL)      /*!< IC5ADDMT34ZE (Bit 5)                                  */
+ #define R_POE3_POECR4_IC5ADDMT34ZE_Msk    (0x20UL)   /*!< IC5ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_DE0ADDMT34ZE_Pos    (6UL)      /*!< DE0ADDMT34ZE (Bit 6)                                  */
+ #define R_POE3_POECR4_DE0ADDMT34ZE_Msk    (0x40UL)   /*!< DE0ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_DE1ADDMT34ZE_Pos    (7UL)      /*!< DE1ADDMT34ZE (Bit 7)                                  */
+ #define R_POE3_POECR4_DE1ADDMT34ZE_Msk    (0x80UL)   /*!< DE1ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC1ADDMT67ZE_Pos    (9UL)      /*!< IC1ADDMT67ZE (Bit 9)                                  */
+ #define R_POE3_POECR4_IC1ADDMT67ZE_Msk    (0x200UL)  /*!< IC1ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC3ADDMT67ZE_Pos    (11UL)     /*!< IC3ADDMT67ZE (Bit 11)                                 */
+ #define R_POE3_POECR4_IC3ADDMT67ZE_Msk    (0x800UL)  /*!< IC3ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC4ADDMT67ZE_Pos    (12UL)     /*!< IC4ADDMT67ZE (Bit 12)                                 */
+ #define R_POE3_POECR4_IC4ADDMT67ZE_Msk    (0x1000UL) /*!< IC4ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC5ADDMT67ZE_Pos    (13UL)     /*!< IC5ADDMT67ZE (Bit 13)                                 */
+ #define R_POE3_POECR4_IC5ADDMT67ZE_Msk    (0x2000UL) /*!< IC5ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_DE0ADDMT67ZE_Pos    (14UL)     /*!< DE0ADDMT67ZE (Bit 14)                                 */
+ #define R_POE3_POECR4_DE0ADDMT67ZE_Msk    (0x4000UL) /*!< DE0ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_DE1ADDMT67ZE_Pos    (15UL)     /*!< DE1ADDMT67ZE (Bit 15)                                 */
+ #define R_POE3_POECR4_DE1ADDMT67ZE_Msk    (0x8000UL) /*!< DE1ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+/* ========================================================  POECR5  ========================================================= */
+ #define R_POE3_POECR5_IC1ADDMT0ZE_Pos     (1UL)      /*!< IC1ADDMT0ZE (Bit 1)                                   */
+ #define R_POE3_POECR5_IC1ADDMT0ZE_Msk     (0x2UL)    /*!< IC1ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+ #define R_POE3_POECR5_IC2ADDMT0ZE_Pos     (2UL)      /*!< IC2ADDMT0ZE (Bit 2)                                   */
+ #define R_POE3_POECR5_IC2ADDMT0ZE_Msk     (0x4UL)    /*!< IC2ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+ #define R_POE3_POECR5_IC4ADDMT0ZE_Pos     (4UL)      /*!< IC4ADDMT0ZE (Bit 4)                                   */
+ #define R_POE3_POECR5_IC4ADDMT0ZE_Msk     (0x10UL)   /*!< IC4ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+ #define R_POE3_POECR5_IC5ADDMT0ZE_Pos     (5UL)      /*!< IC5ADDMT0ZE (Bit 5)                                   */
+ #define R_POE3_POECR5_IC5ADDMT0ZE_Msk     (0x20UL)   /*!< IC5ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+ #define R_POE3_POECR5_DE0ADDMT0ZE_Pos     (6UL)      /*!< DE0ADDMT0ZE (Bit 6)                                   */
+ #define R_POE3_POECR5_DE0ADDMT0ZE_Msk     (0x40UL)   /*!< DE0ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+ #define R_POE3_POECR5_DE1ADDMT0ZE_Pos     (7UL)      /*!< DE1ADDMT0ZE (Bit 7)                                   */
+ #define R_POE3_POECR5_DE1ADDMT0ZE_Msk     (0x80UL)   /*!< DE1ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+/* =========================================================  ICSR4  ========================================================= */
+ #define R_POE3_ICSR4_POE10M_Pos           (0UL)      /*!< POE10M (Bit 0)                                        */
+ #define R_POE3_ICSR4_POE10M_Msk           (0x3UL)    /*!< POE10M (Bitfield-Mask: 0x03)                          */
+ #define R_POE3_ICSR4_PIE4_Pos             (8UL)      /*!< PIE4 (Bit 8)                                          */
+ #define R_POE3_ICSR4_PIE4_Msk             (0x100UL)  /*!< PIE4 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR4_POE10E_Pos           (9UL)      /*!< POE10E (Bit 9)                                        */
+ #define R_POE3_ICSR4_POE10E_Msk           (0x200UL)  /*!< POE10E (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ICSR4_POE10F_Pos           (12UL)     /*!< POE10F (Bit 12)                                       */
+ #define R_POE3_ICSR4_POE10F_Msk           (0x1000UL) /*!< POE10F (Bitfield-Mask: 0x01)                          */
+/* =========================================================  ICSR5  ========================================================= */
+ #define R_POE3_ICSR5_POE11M_Pos           (0UL)      /*!< POE11M (Bit 0)                                        */
+ #define R_POE3_ICSR5_POE11M_Msk           (0x3UL)    /*!< POE11M (Bitfield-Mask: 0x03)                          */
+ #define R_POE3_ICSR5_PIE5_Pos             (8UL)      /*!< PIE5 (Bit 8)                                          */
+ #define R_POE3_ICSR5_PIE5_Msk             (0x100UL)  /*!< PIE5 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR5_POE11E_Pos           (9UL)      /*!< POE11E (Bit 9)                                        */
+ #define R_POE3_ICSR5_POE11E_Msk           (0x200UL)  /*!< POE11E (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ICSR5_POE11F_Pos           (12UL)     /*!< POE11F (Bit 12)                                       */
+ #define R_POE3_ICSR5_POE11F_Msk           (0x1000UL) /*!< POE11F (Bitfield-Mask: 0x01)                          */
+/* =========================================================  ALR1  ========================================================== */
+ #define R_POE3_ALR1_OLSG0A_Pos            (0UL)      /*!< OLSG0A (Bit 0)                                        */
+ #define R_POE3_ALR1_OLSG0A_Msk            (0x1UL)    /*!< OLSG0A (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG0B_Pos            (1UL)      /*!< OLSG0B (Bit 1)                                        */
+ #define R_POE3_ALR1_OLSG0B_Msk            (0x2UL)    /*!< OLSG0B (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG1A_Pos            (2UL)      /*!< OLSG1A (Bit 2)                                        */
+ #define R_POE3_ALR1_OLSG1A_Msk            (0x4UL)    /*!< OLSG1A (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG1B_Pos            (3UL)      /*!< OLSG1B (Bit 3)                                        */
+ #define R_POE3_ALR1_OLSG1B_Msk            (0x8UL)    /*!< OLSG1B (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG2A_Pos            (4UL)      /*!< OLSG2A (Bit 4)                                        */
+ #define R_POE3_ALR1_OLSG2A_Msk            (0x10UL)   /*!< OLSG2A (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG2B_Pos            (5UL)      /*!< OLSG2B (Bit 5)                                        */
+ #define R_POE3_ALR1_OLSG2B_Msk            (0x20UL)   /*!< OLSG2B (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSEN_Pos             (7UL)      /*!< OLSEN (Bit 7)                                         */
+ #define R_POE3_ALR1_OLSEN_Msk             (0x80UL)   /*!< OLSEN (Bitfield-Mask: 0x01)                           */
+/* =========================================================  ICSR6  ========================================================= */
+ #define R_POE3_ICSR6_OSTSTE_Pos           (9UL)      /*!< OSTSTE (Bit 9)                                        */
+ #define R_POE3_ICSR6_OSTSTE_Msk           (0x200UL)  /*!< OSTSTE (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ICSR6_OSTSTF_Pos           (12UL)     /*!< OSTSTF (Bit 12)                                       */
+ #define R_POE3_ICSR6_OSTSTF_Msk           (0x1000UL) /*!< OSTSTF (Bitfield-Mask: 0x01)                          */
+/* =========================================================  ICSR7  ========================================================= */
+ #define R_POE3_ICSR7_DERR0IE_Pos          (6UL)      /*!< DERR0IE (Bit 6)                                       */
+ #define R_POE3_ICSR7_DERR0IE_Msk          (0x40UL)   /*!< DERR0IE (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_ICSR7_DERR1IE_Pos          (7UL)      /*!< DERR1IE (Bit 7)                                       */
+ #define R_POE3_ICSR7_DERR1IE_Msk          (0x80UL)   /*!< DERR1IE (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_ICSR7_DERR0ST_Pos          (13UL)     /*!< DERR0ST (Bit 13)                                      */
+ #define R_POE3_ICSR7_DERR0ST_Msk          (0x2000UL) /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_ICSR7_DERR1ST_Pos          (14UL)     /*!< DERR1ST (Bit 14)                                      */
+ #define R_POE3_ICSR7_DERR1ST_Msk          (0x4000UL) /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
+/* ========================================================  M0SELR1  ======================================================== */
+ #define R_POE3_M0SELR1_M0ASEL_Pos         (0UL)      /*!< M0ASEL (Bit 0)                                        */
+ #define R_POE3_M0SELR1_M0ASEL_Msk         (0xfUL)    /*!< M0ASEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M0SELR1_M0BSEL_Pos         (4UL)      /*!< M0BSEL (Bit 4)                                        */
+ #define R_POE3_M0SELR1_M0BSEL_Msk         (0xf0UL)   /*!< M0BSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M0SELR2  ======================================================== */
+ #define R_POE3_M0SELR2_M0CSEL_Pos         (0UL)      /*!< M0CSEL (Bit 0)                                        */
+ #define R_POE3_M0SELR2_M0CSEL_Msk         (0xfUL)    /*!< M0CSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M0SELR2_M0DSEL_Pos         (4UL)      /*!< M0DSEL (Bit 4)                                        */
+ #define R_POE3_M0SELR2_M0DSEL_Msk         (0xf0UL)   /*!< M0DSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M3SELR  ========================================================= */
+ #define R_POE3_M3SELR_M3BSEL_Pos          (0UL)      /*!< M3BSEL (Bit 0)                                        */
+ #define R_POE3_M3SELR_M3BSEL_Msk          (0xfUL)    /*!< M3BSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M3SELR_M3DSEL_Pos          (4UL)      /*!< M3DSEL (Bit 4)                                        */
+ #define R_POE3_M3SELR_M3DSEL_Msk          (0xf0UL)   /*!< M3DSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M4SELR1  ======================================================== */
+ #define R_POE3_M4SELR1_M4ASEL_Pos         (0UL)      /*!< M4ASEL (Bit 0)                                        */
+ #define R_POE3_M4SELR1_M4ASEL_Msk         (0xfUL)    /*!< M4ASEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M4SELR1_M4CSEL_Pos         (4UL)      /*!< M4CSEL (Bit 4)                                        */
+ #define R_POE3_M4SELR1_M4CSEL_Msk         (0xf0UL)   /*!< M4CSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M4SELR2  ======================================================== */
+ #define R_POE3_M4SELR2_M4BSEL_Pos         (0UL)      /*!< M4BSEL (Bit 0)                                        */
+ #define R_POE3_M4SELR2_M4BSEL_Msk         (0xfUL)    /*!< M4BSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M4SELR2_M4DSEL_Pos         (4UL)      /*!< M4DSEL (Bit 4)                                        */
+ #define R_POE3_M4SELR2_M4DSEL_Msk         (0xf0UL)   /*!< M4DSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M6SELR  ========================================================= */
+ #define R_POE3_M6SELR_M6BSEL_Pos          (0UL)      /*!< M6BSEL (Bit 0)                                        */
+ #define R_POE3_M6SELR_M6BSEL_Msk          (0xfUL)    /*!< M6BSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M6SELR_M6DSEL_Pos          (4UL)      /*!< M6DSEL (Bit 4)                                        */
+ #define R_POE3_M6SELR_M6DSEL_Msk          (0xf0UL)   /*!< M6DSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M7SELR1  ======================================================== */
+ #define R_POE3_M7SELR1_M7ASEL_Pos         (0UL)      /*!< M7ASEL (Bit 0)                                        */
+ #define R_POE3_M7SELR1_M7ASEL_Msk         (0xfUL)    /*!< M7ASEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M7SELR1_M7CSEL_Pos         (4UL)      /*!< M7CSEL (Bit 4)                                        */
+ #define R_POE3_M7SELR1_M7CSEL_Msk         (0xf0UL)   /*!< M7CSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M7SELR2  ======================================================== */
+ #define R_POE3_M7SELR2_M7BSEL_Pos         (0UL)      /*!< M7BSEL (Bit 0)                                        */
+ #define R_POE3_M7SELR2_M7BSEL_Msk         (0xfUL)    /*!< M7BSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M7SELR2_M7DSEL_Pos         (4UL)      /*!< M7DSEL (Bit 4)                                        */
+ #define R_POE3_M7SELR2_M7DSEL_Msk         (0xf0UL)   /*!< M7DSEL (Bitfield-Mask: 0x0f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  POEG0GA  ======================================================== */
+ #define R_POEG0_POEG0GA_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG0_POEG0GA_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG0_POEG0GA_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG0_POEG0GA_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GA_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG0_POEG0GA_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GA_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG0_POEG0GA_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG0_POEG0GA_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG0_POEG0GA_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GA_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG0_POEG0GA_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG0_POEG0GA_DERR0ST_Pos    (24UL)         /*!< DERR0ST (Bit 24)                                      */
+ #define R_POEG0_POEG0GA_DERR0ST_Msk    (0x1000000UL)  /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA_DERR1ST_Pos    (25UL)         /*!< DERR1ST (Bit 25)                                      */
+ #define R_POEG0_POEG0GA_DERR1ST_Msk    (0x2000000UL)  /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA_DERR0E_Pos     (26UL)         /*!< DERR0E (Bit 26)                                       */
+ #define R_POEG0_POEG0GA_DERR0E_Msk     (0x4000000UL)  /*!< DERR0E (Bitfield-Mask: 0x01)                          */
+ #define R_POEG0_POEG0GA_DERR1E_Pos     (27UL)         /*!< DERR1E (Bit 27)                                       */
+ #define R_POEG0_POEG0GA_DERR1E_Msk     (0x8000000UL)  /*!< DERR1E (Bitfield-Mask: 0x01)                          */
+ #define R_POEG0_POEG0GA_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG0_POEG0GA_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GA_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG0_POEG0GA_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG0_POEG0GA_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG0GB  ======================================================== */
+ #define R_POEG0_POEG0GB_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG0_POEG0GB_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG0_POEG0GB_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG0_POEG0GB_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GB_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG0_POEG0GB_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GB_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG0_POEG0GB_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG0_POEG0GB_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG0_POEG0GB_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GB_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG0_POEG0GB_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG0_POEG0GB_DERR0ST_Pos    (24UL)         /*!< DERR0ST (Bit 24)                                      */
+ #define R_POEG0_POEG0GB_DERR0ST_Msk    (0x1000000UL)  /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB_DERR1ST_Pos    (25UL)         /*!< DERR1ST (Bit 25)                                      */
+ #define R_POEG0_POEG0GB_DERR1ST_Msk    (0x2000000UL)  /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB_DERR0E_Pos     (26UL)         /*!< DERR0E (Bit 26)                                       */
+ #define R_POEG0_POEG0GB_DERR0E_Msk     (0x4000000UL)  /*!< DERR0E (Bitfield-Mask: 0x01)                          */
+ #define R_POEG0_POEG0GB_DERR1E_Pos     (27UL)         /*!< DERR1E (Bit 27)                                       */
+ #define R_POEG0_POEG0GB_DERR1E_Msk     (0x8000000UL)  /*!< DERR1E (Bitfield-Mask: 0x01)                          */
+ #define R_POEG0_POEG0GB_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG0_POEG0GB_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GB_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG0_POEG0GB_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG0_POEG0GB_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG0GC  ======================================================== */
+ #define R_POEG0_POEG0GC_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG0_POEG0GC_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG0_POEG0GC_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG0_POEG0GC_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GC_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG0_POEG0GC_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GC_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG0_POEG0GC_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG0_POEG0GC_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG0_POEG0GC_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GC_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG0_POEG0GC_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG0_POEG0GC_DERR0ST_Pos    (24UL)         /*!< DERR0ST (Bit 24)                                      */
+ #define R_POEG0_POEG0GC_DERR0ST_Msk    (0x1000000UL)  /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC_DERR1ST_Pos    (25UL)         /*!< DERR1ST (Bit 25)                                      */
+ #define R_POEG0_POEG0GC_DERR1ST_Msk    (0x2000000UL)  /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC_DERR0E_Pos     (26UL)         /*!< DERR0E (Bit 26)                                       */
+ #define R_POEG0_POEG0GC_DERR0E_Msk     (0x4000000UL)  /*!< DERR0E (Bitfield-Mask: 0x01)                          */
+ #define R_POEG0_POEG0GC_DERR1E_Pos     (27UL)         /*!< DERR1E (Bit 27)                                       */
+ #define R_POEG0_POEG0GC_DERR1E_Msk     (0x8000000UL)  /*!< DERR1E (Bitfield-Mask: 0x01)                          */
+ #define R_POEG0_POEG0GC_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG0_POEG0GC_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GC_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG0_POEG0GC_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG0_POEG0GC_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  POEG0GD  ======================================================== */
+ #define R_POEG0_POEG0GD_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG0_POEG0GD_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG0_POEG0GD_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG0_POEG0GD_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GD_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG0_POEG0GD_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GD_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG0_POEG0GD_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG0_POEG0GD_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG0_POEG0GD_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GD_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG0_POEG0GD_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG0_POEG0GD_DERR0ST_Pos    (24UL)         /*!< DERR0ST (Bit 24)                                      */
+ #define R_POEG0_POEG0GD_DERR0ST_Msk    (0x1000000UL)  /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD_DERR1ST_Pos    (25UL)         /*!< DERR1ST (Bit 25)                                      */
+ #define R_POEG0_POEG0GD_DERR1ST_Msk    (0x2000000UL)  /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD_DERR0E_Pos     (26UL)         /*!< DERR0E (Bit 26)                                       */
+ #define R_POEG0_POEG0GD_DERR0E_Msk     (0x4000000UL)  /*!< DERR0E (Bitfield-Mask: 0x01)                          */
+ #define R_POEG0_POEG0GD_DERR1E_Pos     (27UL)         /*!< DERR1E (Bit 27)                                       */
+ #define R_POEG0_POEG0GD_DERR1E_Msk     (0x8000000UL)  /*!< DERR1E (Bitfield-Mask: 0x01)                          */
+ #define R_POEG0_POEG0GD_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG0_POEG0GD_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GD_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG0_POEG0GD_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG0_POEG0GD_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_DSMIF0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  DSSEICR  ======================================================== */
+ #define R_DSMIF0_DSSEICR_ISEL_Pos          (0UL)       /*!< ISEL (Bit 0)                                          */
+ #define R_DSMIF0_DSSEICR_ISEL_Msk          (0x1UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSSEICR_ISEH_Pos          (1UL)       /*!< ISEH (Bit 1)                                          */
+ #define R_DSMIF0_DSSEICR_ISEH_Msk          (0x2UL)     /*!< ISEH (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DSSECSR  ======================================================== */
+ #define R_DSMIF0_DSSECSR_SEDM_Pos          (0UL)       /*!< SEDM (Bit 0)                                          */
+ #define R_DSMIF0_DSSECSR_SEDM_Msk          (0x7UL)     /*!< SEDM (Bitfield-Mask: 0x07)                            */
+/* ========================================================  DSSELTR  ======================================================== */
+ #define R_DSMIF0_DSSELTR_SCMPTBL_Pos       (0UL)       /*!< SCMPTBL (Bit 0)                                       */
+ #define R_DSMIF0_DSSELTR_SCMPTBL_Msk       (0x3ffffUL) /*!< SCMPTBL (Bitfield-Mask: 0x3ffff)                      */
+/* ========================================================  DSSEHTR  ======================================================== */
+ #define R_DSMIF0_DSSEHTR_SCMPTBH_Pos       (0UL)       /*!< SCMPTBH (Bit 0)                                       */
+ #define R_DSMIF0_DSSEHTR_SCMPTBH_Msk       (0x3ffffUL) /*!< SCMPTBH (Bitfield-Mask: 0x3ffff)                      */
+/* ========================================================  DSSECR  ========================================================= */
+ #define R_DSMIF0_DSSECR_SEEL_Pos           (0UL)       /*!< SEEL (Bit 0)                                          */
+ #define R_DSMIF0_DSSECR_SEEL_Msk           (0x1UL)     /*!< SEEL (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSSECR_SEEH_Pos           (1UL)       /*!< SEEH (Bit 1)                                          */
+ #define R_DSMIF0_DSSECR_SEEH_Msk           (0x2UL)     /*!< SEEH (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DSSECDR  ======================================================== */
+ #define R_DSMIF0_DSSECDR_SECDR_Pos         (0UL)       /*!< SECDR (Bit 0)                                         */
+ #define R_DSMIF0_DSSECDR_SECDR_Msk         (0xffffUL)  /*!< SECDR (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  DSCSTRTR  ======================================================== */
+ #define R_DSMIF0_DSCSTRTR_STRTRG0_Pos      (0UL)       /*!< STRTRG0 (Bit 0)                                       */
+ #define R_DSMIF0_DSCSTRTR_STRTRG0_Msk      (0x1UL)     /*!< STRTRG0 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSTRTR_STRTRG1_Pos      (1UL)       /*!< STRTRG1 (Bit 1)                                       */
+ #define R_DSMIF0_DSCSTRTR_STRTRG1_Msk      (0x2UL)     /*!< STRTRG1 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSTRTR_STRTRG2_Pos      (2UL)       /*!< STRTRG2 (Bit 2)                                       */
+ #define R_DSMIF0_DSCSTRTR_STRTRG2_Msk      (0x4UL)     /*!< STRTRG2 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DSCSTPTR  ======================================================== */
+ #define R_DSMIF0_DSCSTPTR_STPTRG0_Pos      (0UL)       /*!< STPTRG0 (Bit 0)                                       */
+ #define R_DSMIF0_DSCSTPTR_STPTRG0_Msk      (0x1UL)     /*!< STPTRG0 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSTPTR_STPTRG1_Pos      (1UL)       /*!< STPTRG1 (Bit 1)                                       */
+ #define R_DSMIF0_DSCSTPTR_STPTRG1_Msk      (0x2UL)     /*!< STPTRG1 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSTPTR_STPTRG2_Pos      (2UL)       /*!< STPTRG2 (Bit 2)                                       */
+ #define R_DSMIF0_DSCSTPTR_STPTRG2_Msk      (0x4UL)     /*!< STPTRG2 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DSCESR  ========================================================= */
+ #define R_DSMIF0_DSCESR_OCFL0_Pos          (0UL)       /*!< OCFL0 (Bit 0)                                         */
+ #define R_DSMIF0_DSCESR_OCFL0_Msk          (0x1UL)     /*!< OCFL0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCESR_OCFL1_Pos          (1UL)       /*!< OCFL1 (Bit 1)                                         */
+ #define R_DSMIF0_DSCESR_OCFL1_Msk          (0x2UL)     /*!< OCFL1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCESR_OCFL2_Pos          (2UL)       /*!< OCFL2 (Bit 2)                                         */
+ #define R_DSMIF0_DSCESR_OCFL2_Msk          (0x4UL)     /*!< OCFL2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCESR_OCFH0_Pos          (4UL)       /*!< OCFH0 (Bit 4)                                         */
+ #define R_DSMIF0_DSCESR_OCFH0_Msk          (0x10UL)    /*!< OCFH0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCESR_OCFH1_Pos          (5UL)       /*!< OCFH1 (Bit 5)                                         */
+ #define R_DSMIF0_DSCESR_OCFH1_Msk          (0x20UL)    /*!< OCFH1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCESR_OCFH2_Pos          (6UL)       /*!< OCFH2 (Bit 6)                                         */
+ #define R_DSMIF0_DSCESR_OCFH2_Msk          (0x40UL)    /*!< OCFH2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCESR_SCF0_Pos           (8UL)       /*!< SCF0 (Bit 8)                                          */
+ #define R_DSMIF0_DSCESR_SCF0_Msk           (0x100UL)   /*!< SCF0 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCESR_SCF1_Pos           (9UL)       /*!< SCF1 (Bit 9)                                          */
+ #define R_DSMIF0_DSCESR_SCF1_Msk           (0x200UL)   /*!< SCF1 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCESR_SCF2_Pos           (10UL)      /*!< SCF2 (Bit 10)                                         */
+ #define R_DSMIF0_DSCESR_SCF2_Msk           (0x400UL)   /*!< SCF2 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCESR_SUMERRL_Pos        (16UL)      /*!< SUMERRL (Bit 16)                                      */
+ #define R_DSMIF0_DSCESR_SUMERRL_Msk        (0x10000UL) /*!< SUMERRL (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCESR_SUMERRH_Pos        (17UL)      /*!< SUMERRH (Bit 17)                                      */
+ #define R_DSMIF0_DSCESR_SUMERRH_Msk        (0x20000UL) /*!< SUMERRH (Bitfield-Mask: 0x01)                         */
+/* =========================================================  DSCSR  ========================================================= */
+ #define R_DSMIF0_DSCSR_DUF0_Pos            (0UL)       /*!< DUF0 (Bit 0)                                          */
+ #define R_DSMIF0_DSCSR_DUF0_Msk            (0x1UL)     /*!< DUF0 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCSR_DUF1_Pos            (1UL)       /*!< DUF1 (Bit 1)                                          */
+ #define R_DSMIF0_DSCSR_DUF1_Msk            (0x2UL)     /*!< DUF1 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCSR_DUF2_Pos            (2UL)       /*!< DUF2 (Bit 2)                                          */
+ #define R_DSMIF0_DSCSR_DUF2_Msk            (0x4UL)     /*!< DUF2 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DSCSSR  ========================================================= */
+ #define R_DSMIF0_DSCSSR_CHSTATE0_Pos       (0UL)       /*!< CHSTATE0 (Bit 0)                                      */
+ #define R_DSMIF0_DSCSSR_CHSTATE0_Msk       (0x1UL)     /*!< CHSTATE0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSSR_CHSTATE1_Pos       (4UL)       /*!< CHSTATE1 (Bit 4)                                      */
+ #define R_DSMIF0_DSCSSR_CHSTATE1_Msk       (0x10UL)    /*!< CHSTATE1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSSR_CHSTATE2_Pos       (8UL)       /*!< CHSTATE2 (Bit 8)                                      */
+ #define R_DSMIF0_DSCSSR_CHSTATE2_Msk       (0x100UL)   /*!< CHSTATE2 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DSCESCR  ======================================================== */
+ #define R_DSMIF0_DSCESCR_CLROCFL0_Pos      (0UL)       /*!< CLROCFL0 (Bit 0)                                      */
+ #define R_DSMIF0_DSCESCR_CLROCFL0_Msk      (0x1UL)     /*!< CLROCFL0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCESCR_CLROCFL1_Pos      (1UL)       /*!< CLROCFL1 (Bit 1)                                      */
+ #define R_DSMIF0_DSCESCR_CLROCFL1_Msk      (0x2UL)     /*!< CLROCFL1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCESCR_CLROCFL2_Pos      (2UL)       /*!< CLROCFL2 (Bit 2)                                      */
+ #define R_DSMIF0_DSCESCR_CLROCFL2_Msk      (0x4UL)     /*!< CLROCFL2 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCESCR_CLROCFH0_Pos      (4UL)       /*!< CLROCFH0 (Bit 4)                                      */
+ #define R_DSMIF0_DSCESCR_CLROCFH0_Msk      (0x10UL)    /*!< CLROCFH0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCESCR_CLROCFH1_Pos      (5UL)       /*!< CLROCFH1 (Bit 5)                                      */
+ #define R_DSMIF0_DSCESCR_CLROCFH1_Msk      (0x20UL)    /*!< CLROCFH1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCESCR_CLROCFH2_Pos      (6UL)       /*!< CLROCFH2 (Bit 6)                                      */
+ #define R_DSMIF0_DSCESCR_CLROCFH2_Msk      (0x40UL)    /*!< CLROCFH2 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCESCR_CLRSCF0_Pos       (8UL)       /*!< CLRSCF0 (Bit 8)                                       */
+ #define R_DSMIF0_DSCESCR_CLRSCF0_Msk       (0x100UL)   /*!< CLRSCF0 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCESCR_CLRSCF1_Pos       (9UL)       /*!< CLRSCF1 (Bit 9)                                       */
+ #define R_DSMIF0_DSCESCR_CLRSCF1_Msk       (0x200UL)   /*!< CLRSCF1 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCESCR_CLRSCF2_Pos       (10UL)      /*!< CLRSCF2 (Bit 10)                                      */
+ #define R_DSMIF0_DSCESCR_CLRSCF2_Msk       (0x400UL)   /*!< CLRSCF2 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCESCR_CLRSUMERRL_Pos    (16UL)      /*!< CLRSUMERRL (Bit 16)                                   */
+ #define R_DSMIF0_DSCESCR_CLRSUMERRL_Msk    (0x10000UL) /*!< CLRSUMERRL (Bitfield-Mask: 0x01)                      */
+ #define R_DSMIF0_DSCESCR_CLRSUMERRH_Pos    (17UL)      /*!< CLRSUMERRH (Bit 17)                                   */
+ #define R_DSMIF0_DSCESCR_CLRSUMERRH_Msk    (0x20000UL) /*!< CLRSUMERRH (Bitfield-Mask: 0x01)                      */
+/* ========================================================  DSCSCR  ========================================================= */
+ #define R_DSMIF0_DSCSCR_CLRDUF0_Pos        (0UL)       /*!< CLRDUF0 (Bit 0)                                       */
+ #define R_DSMIF0_DSCSCR_CLRDUF0_Msk        (0x1UL)     /*!< CLRDUF0 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSCR_CLRDUF1_Pos        (1UL)       /*!< CLRDUF1 (Bit 1)                                       */
+ #define R_DSMIF0_DSCSCR_CLRDUF1_Msk        (0x2UL)     /*!< CLRDUF1 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSCR_CLRDUF2_Pos        (2UL)       /*!< CLRDUF2 (Bit 2)                                       */
+ #define R_DSMIF0_DSCSCR_CLRDUF2_Msk        (0x4UL)     /*!< CLRDUF2 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_GSC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CNTCR  ========================================================= */
+ #define R_GSC_CNTCR_EN_Pos              (0UL)          /*!< EN (Bit 0)                                            */
+ #define R_GSC_CNTCR_EN_Msk              (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_GSC_CNTCR_HDBG_Pos            (1UL)          /*!< HDBG (Bit 1)                                          */
+ #define R_GSC_CNTCR_HDBG_Msk            (0x2UL)        /*!< HDBG (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CNTSR  ========================================================= */
+ #define R_GSC_CNTSR_DBGH_Pos            (1UL)          /*!< DBGH (Bit 1)                                          */
+ #define R_GSC_CNTSR_DBGH_Msk            (0x2UL)        /*!< DBGH (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CNTCVL  ========================================================= */
+ #define R_GSC_CNTCVL_CNTCVL_L_32_Pos    (0UL)          /*!< CNTCVL_L_32 (Bit 0)                                   */
+ #define R_GSC_CNTCVL_CNTCVL_L_32_Msk    (0xffffffffUL) /*!< CNTCVL_L_32 (Bitfield-Mask: 0xffffffff)               */
+/* ========================================================  CNTCVU  ========================================================= */
+ #define R_GSC_CNTCVU_CNTCVU_U_32_Pos    (0UL)          /*!< CNTCVU_U_32 (Bit 0)                                   */
+ #define R_GSC_CNTCVU_CNTCVU_U_32_Msk    (0xffffffffUL) /*!< CNTCVU_U_32 (Bitfield-Mask: 0xffffffff)               */
+/* ========================================================  CNTFID0  ======================================================== */
+ #define R_GSC_CNTFID0_FREQ_Pos          (0UL)          /*!< FREQ (Bit 0)                                          */
+ #define R_GSC_CNTFID0_FREQ_Msk          (0xffffffffUL) /*!< FREQ (Bitfield-Mask: 0xffffffff)                      */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif                                 /* R9A07G084_H */
+
+/** @} */ /* End of group R9A07G084 */
+
+/** @} */ /* End of group Renesas Electronics Corporation */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A09G087.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A09G087.h
new file mode 100644
index 00000000..a24f2cff
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A09G087.h
@@ -0,0 +1,101834 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/** @addtogroup Renesas Electronics Corporation
+ * @{
+ */
+
+/** @addtogroup R9A09G087
+ * @{
+ */
+
+#ifndef R9A09G087_H
+ #define R9A09G087_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */
+ #ifdef RENESAS_CORTEX_M4
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
+  #include "core_cm4.h"                /*!< Cortex-M4 processor and core peripherals                              */
+ #elif defined(RENESAS_CORTEX_M0PLUS)
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
+  #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
+  #include "core_cm0plus.h"            /*!< Cortex-M0 processor and core peripherals                              */
+ #elif defined(RENESAS_CORTEX_M23)
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
+  #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
+  #include "core_cm23.h"               /*!< Cortex-M23 processor and core peripherals                             */
+ #elif defined(RENESAS_CORTEX_M33)
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
+  #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
+  #define __DSP_PRESENT             1  /*!< DSP present or not                                                    */
+  #include "core_cm33.h"               /*!< Cortex-M33 processor and core peripherals                             */
+ #elif defined(RENESAS_CORTEX_R52)
+  #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
+  #include "core_cr52.h"               /*!< Cortex-R52 processor and core peripherals                              */
+ #elif defined(RENESAS_CORTEX_A55)
+  #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
+  #include "core_ca55.h"               /*!< Cortex-A55 processor and core peripherals                             */
+  #if (1 == BSP_LP64_SUPPORT)
+   #include "core_ca_64bit.h"          /*!< Cortex-A processor 64bit and core peripherals                         */
+  #else
+   #include "core_ca.h"                /*!< Cortex-A processor 32bit and core peripherals                         */
+  #endif
+ #endif
+
+ #include "system.h"                   /*!< System                                                                */
+
+ #ifndef __IM                          /*!< Fallback for older CMSIS versions                                         */
+  #define __IM     __I
+ #endif
+ #ifndef __OM                          /*!< Fallback for older CMSIS versions                                         */
+  #define __OM     __O
+ #endif
+ #ifndef __IOM                         /*!< Fallback for older CMSIS versions                                         */
+  #define __IOM    __IO
+ #endif
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+ #if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+ #elif defined(__ICCARM__)
+  #pragma language=extended
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+  #pragma clang diagnostic ignored "-Wnested-anon-types"
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning 586
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #else
+  #warning Not supported compiler type
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                              Device Specific Cluster Section                              ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+/**
+ * @brief R_CANFD_CFDC [CFDC] (CANFD Channel [0..1] Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel n Nominal Bit Rate Configuration Register          */
+
+        struct
+        {
+            __IOM uint32_t NBRP   : 10; /*!< [9..0] Nominal Bit Rate Prescaler                                         */
+            __IOM uint32_t NSJW   : 7;  /*!< [16..10] Nominal Bit Rate Resynchronization Jump Width Control            */
+            __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Nominal Bit Rate Time Segment 1 Control                          */
+            __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Nominal Bit Rate Time Segment 2 Control                          */
+        } NCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel n Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t CHMDC   : 2; /*!< [1..0] Mode Select                                                        */
+            __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Stop Mode                                                  */
+            __IOM uint32_t RTBO    : 1; /*!< [3..3] Forcible Return from Bus-Off                                       */
+            uint32_t               : 4;
+            __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
+            __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
+            __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
+            __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
+            __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
+            __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
+            __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
+            __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
+            __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission Abort Interrupt Enable                              */
+            __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error Occurrence Counter Overflow Interrupt Enable               */
+            __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt Enable          */
+            __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
+                                         *   Enable                                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t BOM  : 2;    /*!< [22..21] Bus-Off Recovery Mode Select                                     */
+            __IOM uint32_t ERRD : 1;    /*!< [23..23] Error Display Mode Select                                        */
+            __IOM uint32_t CTME : 1;    /*!< [24..24] Communication Test Mode Enable                                   */
+            __IOM uint32_t CTMS : 2;    /*!< [26..25] Communication Test Mode Select                                   */
+            uint32_t            : 3;
+            __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test Enable                                            */
+            __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode Enable                                 */
+        } CTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel n Status Register                                  */
+
+        struct
+        {
+            __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel Reset Status Flag                                          */
+            __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel Halt Status Flag                                           */
+            __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel Stop Status Flag                                           */
+            __IM uint32_t  EPSTS   : 1; /*!< [3..3] Error Passive Status Flag                                          */
+            __IM uint32_t  BOSTS   : 1; /*!< [4..4] Bus-Off Status Flag                                                */
+            __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Transmit Status Flag                                               */
+            __IM uint32_t  RECSTS  : 1; /*!< [6..6] Receive Status Flag                                                */
+            __IM uint32_t  COMSTS  : 1; /*!< [7..7] Communication Status Flag                                          */
+            __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
+            uint32_t               : 7;
+            __IM uint32_t REC      : 8; /*!< [23..16] Reception Error Count                                            */
+            __IM uint32_t TEC      : 8; /*!< [31..24] Transmission Error Count                                         */
+        } STS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel n Error Flag Register                              */
+
+        struct
+        {
+            __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
+            __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
+            __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
+            __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
+            __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
+            __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
+            __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
+            __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
+            __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error Flag                                                   */
+            __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error Flag                                                    */
+            __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error Flag                                           */
+            __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error Flag                                                   */
+            __IOM uint32_t B1ERR : 1;  /*!< [12..12] Recessive Bit Error Flag                                         */
+            __IOM uint32_t B0ERR : 1;  /*!< [13..13] Dominant Bit Error Flag                                          */
+            __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error Flag                                 */
+            uint32_t             : 1;
+            __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Calculation Data (CRC length: 15 bits)                       */
+            uint32_t             : 1;
+        } ERFL_b;
+    };
+} R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bit Rate Configuration Register               */
+
+        struct
+        {
+            __IOM uint32_t DBRP   : 8; /*!< [7..0] Data Bit Rate Prescaler Division Ratio Setting                     */
+            __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Data Bit Rate Time Segment 1 Control                              */
+            uint32_t              : 3;
+            __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Data Bit Rate Time Segment 2 Control                             */
+            uint32_t              : 4;
+            __IOM uint32_t DSJW   : 4; /*!< [27..24] Data Bit Rate Resynchronization Jump Width Control               */
+            uint32_t              : 4;
+        } DCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel n CAN-FD Configuration Register                    */
+
+        struct
+        {
+            __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
+            uint32_t              : 5;
+            __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transmitter Delay Compensation Offset Configuration                */
+            __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
+            __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
+            uint32_t              : 5;
+            __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
+            __IOM uint32_t GWEN   : 1; /*!< [24..24] CAN2.0, CAN-FD Multi Gateway Enable                              */
+            __IOM uint32_t GWFDF  : 1; /*!< [25..25] Gateway FDF Configuration Bit                                    */
+            __IOM uint32_t GWBRS  : 1; /*!< [26..26] Gateway BRS Configuration Bit                                    */
+            uint32_t              : 1;
+            __IOM uint32_t FDOE   : 1; /*!< [28..28] FD-Only Enable                                                   */
+            __IOM uint32_t REFE   : 1; /*!< [29..29] RX Edge Filter Enable                                            */
+            __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN-Only Enable                                        */
+            __IOM uint32_t CFDTE  : 1; /*!< [31..31] CAN-FD Frame Distinction Enable                                  */
+        } FDCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel n CAN-FD Control Register                          */
+
+        struct
+        {
+            __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
+            __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
+            uint32_t              : 30;
+        } FDCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel n CAN-FD Status Register                           */
+
+        struct
+        {
+            __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
+            __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error Occurrence Counter Overflow Flag                             */
+            __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful Occurrence Counter Overflow Flag                        */
+            uint32_t             : 5;
+            __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
+            __IM uint32_t  EOC   : 8;  /*!< [23..16] Error Occurrence Counter                                         */
+            __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful Occurrence Counter                                    */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t FDCRC;           /*!< (@ 0x00000010) Channel n CAN-FD CRC Register                              */
+
+        struct
+        {
+            __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register Value                                                */
+            uint32_t             : 4;
+            __IM uint32_t SCNT   : 4;  /*!< [28..25] Stuff Bit Count                                                  */
+            uint32_t             : 3;
+        } FDCRC_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t BLCT;           /*!< (@ 0x00000018) Channel n Bus Load Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t BLCE : 1;   /*!< [0..0] Bus Load Counter Enable                                            */
+            uint32_t            : 7;
+            __OM uint32_t BLCLD : 1;   /*!< [8..8] Bus Load Counter Load                                              */
+            uint32_t            : 23;
+        } BLCT_b;
+    };
+
+    union
+    {
+        __IM uint32_t BLSTS;           /*!< (@ 0x0000001C) Channel n Bus Load Status Register                         */
+
+        struct
+        {
+            uint32_t          : 3;
+            __IM uint32_t BLC : 29;    /*!< [31..3] Bus Load Counter Status                                           */
+        } BLSTS_b;
+    };
+} R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
+
+/**
+ * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Register n                */
+
+        struct
+        {
+            __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
+            __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
+            __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
+            __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Register n              */
+
+        struct
+        {
+            __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
+            __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
+            __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
+            __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
+        } M_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Register
+                                          *                  n                                                          */
+
+        struct
+        {
+            __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
+            __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing Destination
+                                          *   0                                                                         */
+            __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing Destination
+                                          *   1                                                                         */
+            __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing Destination
+                                          *   2                                                                         */
+            __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
+            __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
+                                          *   Pointer                                                                   */
+            uint32_t               : 2;
+            __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
+            __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer                            */
+        } P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1;               /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Register
+                                          *                  n                                                          */
+
+        struct
+        {
+            __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer              */
+            uint32_t               : 18;
+        } P1_b;
+    };
+} R_CANFD_CFDGAFL_Type;                  /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
+
+        struct
+        {
+            __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
+            uint32_t            : 1;
+            __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Bit                                        */
+            __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
+
+        struct
+        {
+            __IOM uint32_t RMTS  : 16; /*!< [15..0] RX Message Buffer Timestamp Field                                 */
+            uint32_t             : 12;
+            __IOM uint32_t RMDLC : 4;  /*!< [31..28] RX Message Buffer DLC Field                                      */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
+
+        struct
+        {
+            __IOM uint32_t RMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t RMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t RMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t RMIFL : 2;  /*!< [9..8] RX Message Buffer Information Label Field                          */
+            uint32_t             : 6;
+            __IOM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field                                  */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p
+                                            *                  = 0 to 15, n = 0 to 31)                                    */
+
+            struct
+            {
+                __IM uint32_t RMDB_LL : 8; /*!< [7..0] RX Message Buffer Data Byte (4 * p)                               */
+                __IM uint32_t RMDB_LH : 8; /*!< [15..8] RX Message Buffer Data Byte (4 * p + 1)                          */
+                __IM uint32_t RMDB_HL : 8; /*!< [23..16] RX Message Buffer Data Byte (4 * p + 2)                         */
+                __IM uint32_t RMDB_HH : 8; /*!< [31..24] RX Message Buffer Data Byte (4 * p + 3)                         */
+            } DF_WD_b[16];
+        };
+
+        union
+        {
+            __IM uint8_t DF[64];       /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p
+                                        *                  = 0 to 63, n = 0 to 31)                                    */
+
+            struct
+            {
+                __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte                                        */
+            } DF_b[64];
+        };
+    };
+    __IM uint32_t RESERVED[13];
+} R_CANFD_CFDRM_Type;                  /*!< Size = 128 (0x80)                                                         */
+
+/**
+ * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register n                               */
+
+        struct
+        {
+            __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
+            uint32_t            : 1;
+            __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR bit                                           */
+            __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE bit                                           */
+        } ID_b;
+    };
+
+    union
+    {
+        __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register n                          */
+
+        struct
+        {
+            __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Value                                           */
+            uint32_t            : 12;
+            __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FDSTS;             /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register n                    */
+
+        struct
+        {
+            __IM uint32_t RFESI    : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IM uint32_t RFBRS    : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IM uint32_t RFFDF    : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t               : 5;
+            __IM uint32_t RFIFL    : 2;  /*!< [9..8] RX FIFO Buffer Information Label Field                             */
+            uint32_t               : 6;
+            __IM uint32_t CFDRFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0
+                                            *                  to 15, n = 0 to 7)                                         */
+
+            struct
+            {
+                __IM uint32_t RFDB_LL : 8; /*!< [7..0] RX FIFO Buffer Data Byte (4 * p)                                  */
+                __IM uint32_t RFDB_LH : 8; /*!< [15..8] RX FIFO Buffer Data Byte (4 * p + 1)                             */
+                __IM uint32_t RFDB_HL : 8; /*!< [23..16] RX FIFO Buffer Data Byte (4 * p + 2)                            */
+                __IM uint32_t RFDB_HH : 8; /*!< [31..24] RX FIFO Buffer Data Byte (4 * p + 3)                            */
+            } DF_WD_b[16];
+        };
+
+        union
+        {
+            __IM uint8_t DF[64];       /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0
+                                        *                  to 63, n = 0 to 7)                                         */
+
+            struct
+            {
+                __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte                                           */
+            } DF_b[64];
+        };
+    };
+    __IM uint32_t RESERVED[13];
+} R_CANFD_CFDRF_Type;                  /*!< Size = 128 (0x80)                                                         */
+
+/**
+ * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
+
+        struct
+        {
+            __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
+            __IOM uint32_t THLEN : 1;  /*!< [29..29] THL Entry Enable                                                 */
+            __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR bit                                       */
+            __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE bit                                       */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register n                      */
+
+        struct
+        {
+            __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Value                                       */
+            uint32_t             : 12;
+            __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCSTS;         /*!< (@ 0x00000008) Common FIFO Access CAN-FD Control/Status Register
+                                        *                  n                                                          */
+
+        struct
+        {
+            __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t CFIFL : 2;  /*!< [9..8] COMMON FIFO Buffer Information Label Field                         */
+            uint32_t             : 6;
+            __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
+        } FDCSTS_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p
+                                             *                  = 0 to 15, n = 0 to 5)                                     */
+
+            struct
+            {
+                __IOM uint32_t CFDB_LL : 8; /*!< [7..0] Common FIFO Buffer Data Bytes (4 * p)                             */
+                __IOM uint32_t CFDB_LH : 8; /*!< [15..8] Common FIFO Buffer Data Bytes (4 * p + 1)                        */
+                __IOM uint32_t CFDB_HL : 8; /*!< [23..16] Common FIFO Buffer Data Bytes (4 * p + 2)                       */
+                __IOM uint32_t CFDB_HH : 8; /*!< [31..24] Common FIFO Buffer Data Bytes (4 * p + 3)                       */
+            } DF_WD_b[16];
+        };
+
+        union
+        {
+            __IOM uint8_t DF[64];       /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p
+                                         *                  = 0 to 63, n = 0 to 5)                                     */
+
+            struct
+            {
+                __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Bytes                                      */
+            } DF_b[64];
+        };
+    };
+    __IM uint32_t RESERVED[13];
+} R_CANFD_CFDCF_Type;                  /*!< Size = 128 (0x80)                                                         */
+
+/**
+ * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
+
+        struct
+        {
+            __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
+            __IM uint32_t BN   : 7;    /*!< [9..3] Buffer Number                                                      */
+            uint32_t           : 5;
+            __IM uint32_t TGW  : 1;    /*!< [15..15] Transmit Gateway Buffer Indication                               */
+            __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
+        } ACC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACC1;            /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
+
+        struct
+        {
+            __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
+            __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
+            uint32_t           : 14;
+        } ACC1_b;
+    };
+} R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register n (n = 0 to 127)             */
+
+        struct
+        {
+            __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
+            __IOM uint32_t THLEN : 1;  /*!< [29..29] Tx History List Entry                                            */
+            __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR bit                                        */
+            __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE bit                                        */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register n (n = 0 to
+                                        *                  127)                                                       */
+
+        struct
+        {
+            uint32_t             : 28;
+            __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register n (n
+                                        *                  = 0 to 127)                                                */
+
+        struct
+        {
+            __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
+            uint32_t             : 6;
+            __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
+        } FDCTR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p
+                                             *                  = 0 to 15, n = 0 to 127)                                   */
+
+            struct
+            {
+                __IOM uint32_t TMDB_LL : 8; /*!< [7..0] TX Message Buffer Data Byte (4 * p)                               */
+                __IOM uint32_t TMDB_LH : 8; /*!< [15..8] TX Message Buffer Data Byte (4 * p + 1)                          */
+                __IOM uint32_t TMDB_HL : 8; /*!< [23..16] TX Message Buffer Data Byte (4 * p + 2)                         */
+                __IOM uint32_t TMDB_HH : 8; /*!< [31..24] TX Message Buffer Data Byte (4 * p + 3)                         */
+            } DF_WD_b[16];
+        };
+
+        union
+        {
+            __IOM uint8_t DF[64];       /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p
+                                         *                  = 0 to 63, n = 0 to 5)                                     */
+
+            struct
+            {
+                __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Bytes                                       */
+            } DF_b[64];
+        };
+    };
+    __IM uint32_t RESERVED[13];
+} R_CANFD_CFDTM_Type;                  /*!< Size = 128 (0x80)                                                         */
+
+/**
+ * @brief R_CMT_UNT_CM [CM] (2 Timer Start Register Pairs)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CR;             /*!< (@ 0x00000000) Compare Match Timer Control Register                       */
+
+        struct
+        {
+            __IOM uint16_t CKS  : 2;   /*!< [1..0] Clock Select                                                       */
+            uint16_t            : 4;
+            __IOM uint16_t CMIE : 1;   /*!< [6..6] Compare Match Interrupt Enable                                     */
+            uint16_t            : 9;
+        } CR_b;
+    };
+    __IOM uint16_t CNT;                /*!< (@ 0x00000002) Compare Match Timer Counter Register                       */
+    __IOM uint16_t COR;                /*!< (@ 0x00000004) Compare Match Timer Constant Register                      */
+} R_CMT_UNT_CM_Type;                   /*!< Size = 6 (0x6)                                                            */
+
+/**
+ * @brief R_CMT_UNT [UNT] (3 Timer Start Register Units)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CMSTR0;         /*!< (@ 0x00000000) Compare Match Timer Start Register                         */
+
+        struct
+        {
+            __IOM uint16_t STR0 : 1;   /*!< [0..0] CMT Channel n Count Start                                          */
+            __IOM uint16_t STR1 : 1;   /*!< [1..1] CMT Channel n+1 Count Start                                        */
+            uint16_t            : 14;
+        } CMSTR0_b;
+    };
+    __IOM R_CMT_UNT_CM_Type CM[2];     /*!< (@ 0x00000002) 2 Timer Start Register Pairs                               */
+    __IM uint16_t           RESERVED[505];
+} R_CMT_UNT_Type;                      /*!< Size = 1024 (0x400)                                                       */
+
+/**
+ * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L y (y = 0 to 2)                    */
+
+        struct
+        {
+            __IOM uint8_t SVA0 : 1;    /*!< [0..0] 10-bit Address LSB                                                 */
+            __IOM uint8_t SVA  : 7;    /*!< [7..1] 7-bit Address/10-bit Address Lower Bits                            */
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U y (y = 0 to 2)                    */
+
+        struct
+        {
+            __IOM uint8_t FS  : 1;     /*!< [0..0] 7-bit/10-bit Address Format Select                                 */
+            __IOM uint8_t SVA : 2;     /*!< [2..1] 10-bit Address Upper Bits                                          */
+            uint8_t           : 5;
+        } U_b;
+    };
+} R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_DMAC0_GRP_CH_N [N] (DMAC Address Registers [0..1])
+ */
+typedef struct
+{
+    __IOM uint32_t SA;                 /*!< (@ 0x00000000) Nextm0 Source Address Register n                           */
+    __IOM uint32_t DA;                 /*!< (@ 0x00000004) Nextm0 Destination Address Register n (m = 0,
+                                        *                  1) (n = 0 to 15)                                           */
+    __IOM uint32_t TB;                 /*!< (@ 0x00000008) Nextm0 Transaction Byte Register n (m = 0, 1)
+                                        *                  (n = 0 to 15)                                              */
+} R_DMAC0_GRP_CH_N_Type;               /*!< Size = 12 (0xc)                                                           */
+
+/**
+ * @brief R_DMAC0_GRP_CH [CH] (DMAC channel Control Register [0..7])
+ */
+typedef struct
+{
+    __IOM R_DMAC0_GRP_CH_N_Type N[2];  /*!< (@ 0x00000000) DMAC Address Registers [0..1]                              */
+    __IM uint32_t               CRSA;  /*!< (@ 0x00000018) Current Source Address Register n (n = 0 to 15)            */
+    __IM uint32_t               CRDA;  /*!< (@ 0x0000001C) Current Destination Address Register n (n = 0
+                                        *                  to 15)                                                     */
+    __IM uint32_t CRTB;                /*!< (@ 0x00000020) Current Transaction Byte Register n                        */
+
+    union
+    {
+        __IM uint32_t CHSTAT;          /*!< (@ 0x00000024) Channel Status Register n                                  */
+
+        struct
+        {
+            __IM uint32_t EN   : 1;    /*!< [0..0] DMA Activation Enable                                              */
+            __IM uint32_t RQST : 1;    /*!< [1..1] DMA Transfer Request                                               */
+            __IM uint32_t TACT : 1;    /*!< [2..2] DMAC Operating Status                                              */
+            __IM uint32_t SUS  : 1;    /*!< [3..3] Suspend                                                            */
+            __IM uint32_t ER   : 1;    /*!< [4..4] DMA Error                                                          */
+            __IM uint32_t END  : 1;    /*!< [5..5] DMA Transfer Completion Interrupt                                  */
+            __IM uint32_t TC   : 1;    /*!< [6..6] DMA Transfer Completion (total number of data bytes for
+                                        *   transaction)                                                              */
+            __IM uint32_t SR   : 1;    /*!< [7..7] Next Register Select                                               */
+            __IM uint32_t DL   : 1;    /*!< [8..8] Descriptor Load                                                    */
+            __IM uint32_t DW   : 1;    /*!< [9..9] Descriptor Write Back                                              */
+            __IM uint32_t DER  : 1;    /*!< [10..10] Descriptor Error                                                 */
+            __IM uint32_t MODE : 1;    /*!< [11..11] DMA Mode                                                         */
+            uint32_t           : 4;
+            __IM uint32_t INTM : 1;    /*!< [16..16] DMA Transfer Completion Interrupt Request Mask                   */
+            uint32_t           : 15;
+        } CHSTAT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHCTRL;          /*!< (@ 0x00000028) Channel Control Register n                                 */
+
+        struct
+        {
+            __IOM uint32_t SETEN   : 1; /*!< [0..0] DMA Activation Enable                                              */
+            __IOM uint32_t CLREN   : 1; /*!< [1..1] DMA Activation Enable Clear                                        */
+            __IOM uint32_t STG     : 1; /*!< [2..2] Software Trigger                                                   */
+            __IOM uint32_t SWRST   : 1; /*!< [3..3] Software Reset                                                     */
+            __IOM uint32_t CLRRQ   : 1; /*!< [4..4] DMA Transfer Request Clear                                         */
+            __IOM uint32_t CLREND  : 1; /*!< [5..5] END Clear                                                          */
+            __IOM uint32_t CLRTC   : 1; /*!< [6..6] TC Clear                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t SETSUS  : 1; /*!< [8..8] Suspend Request                                                    */
+            __IOM uint32_t CLRSUS  : 1; /*!< [9..9] Suspend Clear                                                      */
+            uint32_t               : 6;
+            __IOM uint32_t SETINTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask                   */
+            __IOM uint32_t CLRINTM : 1; /*!< [17..17] DMA Transfer Completion Interrupt Request Mask Clear             */
+            uint32_t               : 14;
+        } CHCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHCFG;          /*!< (@ 0x0000002C) Channel Configuration Register n                           */
+
+        struct
+        {
+            __IOM uint32_t SEL  : 3;   /*!< [2..0] Pin Select                                                         */
+            __IOM uint32_t REQD : 1;   /*!< [3..3] DMA Activation Request Source Select                               */
+            __IOM uint32_t LOEN : 1;   /*!< [4..4] L Detection Enable                                                 */
+            __IOM uint32_t HIEN : 1;   /*!< [5..5] H Detection Enable                                                 */
+            __IOM uint32_t LVL  : 1;   /*!< [6..6] Level Detection Enable                                             */
+            uint32_t            : 1;
+            __IOM uint32_t AM   : 3;   /*!< [10..8] ACK Mode                                                          */
+            uint32_t            : 1;
+            __IOM uint32_t SDS  : 4;   /*!< [15..12] Source Data Size                                                 */
+            __IOM uint32_t DDS  : 4;   /*!< [19..16] Destination Data Size                                            */
+            __IOM uint32_t SAD  : 1;   /*!< [20..20] Source Address Count Direction                                   */
+            __IOM uint32_t DAD  : 1;   /*!< [21..21] Destination Address Count Direction                              */
+            __IOM uint32_t TM   : 1;   /*!< [22..22] Transfer Mode                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t DEM  : 1;   /*!< [24..24] DMA Transfer Completion Interrupt Mask                           */
+            __IOM uint32_t TCM  : 1;   /*!< [25..25] TEND Mask                                                        */
+            uint32_t            : 1;
+            __IOM uint32_t SBE  : 1;   /*!< [27..27] Buffer Flush Enable                                              */
+            __IOM uint32_t RSEL : 1;   /*!< [28..28] Next Register Select                                             */
+            __IOM uint32_t RSW  : 1;   /*!< [29..29] RSEL Reverse                                                     */
+            __IOM uint32_t REN  : 1;   /*!< [30..30] Register Set Enable                                              */
+            __IOM uint32_t DMS  : 1;   /*!< [31..31] DMA Mode Select                                                  */
+        } CHCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHITVL;         /*!< (@ 0x00000030) Channel Interval Register n                                */
+
+        struct
+        {
+            __IOM uint32_t ITVL : 16;  /*!< [15..0] Interval                                                          */
+            uint32_t            : 16;
+        } CHITVL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHEXT;          /*!< (@ 0x00000034) Channel Extension Register n                               */
+
+        struct
+        {
+            __IOM uint32_t SPR : 3;    /*!< [2..0] Source PROT                                                        */
+            uint32_t           : 1;
+            __IOM uint32_t SCA : 4;    /*!< [7..4] Source CACHE                                                       */
+            __IOM uint32_t DPR : 3;    /*!< [10..8] Destination PROT                                                  */
+            uint32_t           : 1;
+            __IOM uint32_t DCA : 4;    /*!< [15..12] Destination CACHE                                                */
+            uint32_t           : 16;
+        } CHEXT_b;
+    };
+    __IOM uint32_t NXLA;               /*!< (@ 0x00000038) DMA Destination Address Register                           */
+    __IM uint32_t  CRLA;               /*!< (@ 0x0000003C) Current Link Address Register n                            */
+} R_DMAC0_GRP_CH_Type;                 /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_DMAC0_GRP [GRP] (8 channel Registers)
+ */
+typedef struct
+{
+    __IOM R_DMAC0_GRP_CH_Type CH[8];   /*!< (@ 0x00000000) DMAC channel Control Register [0..7]                       */
+    __IM uint32_t             RESERVED[64];
+
+    union
+    {
+        __IOM uint32_t DCTRL;          /*!< (@ 0x00000300) DMA Control Register A/B                                   */
+
+        struct
+        {
+            __IOM uint32_t PR    : 1;  /*!< [0..0] Priority Control Select                                            */
+            __IOM uint32_t LVINT : 1;  /*!< [1..1] DMA Interrupt Output Select                                        */
+            uint32_t             : 30;
+        } DCTRL_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IM uint32_t DSTAT_EN;        /*!< (@ 0x00000310) DMA Status EN Register A/B                                 */
+
+        struct
+        {
+            __IM uint32_t EN0008 : 1;  /*!< [0..0] Channel 0/8 EN                                                     */
+            __IM uint32_t EN0109 : 1;  /*!< [1..1] Channel 1/9 EN                                                     */
+            __IM uint32_t EN0210 : 1;  /*!< [2..2] Channel 2/10 EN                                                    */
+            __IM uint32_t EN0311 : 1;  /*!< [3..3] Channel 3/11 EN                                                    */
+            __IM uint32_t EN0412 : 1;  /*!< [4..4] Channel 4/12 EN                                                    */
+            __IM uint32_t EN0513 : 1;  /*!< [5..5] Channel 5/13 EN                                                    */
+            __IM uint32_t EN0614 : 1;  /*!< [6..6] Channel 6/14 EN                                                    */
+            __IM uint32_t EN0715 : 1;  /*!< [7..7] Channel 7/15 EN                                                    */
+            uint32_t             : 24;
+        } DSTAT_EN_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_ER;        /*!< (@ 0x00000314) DMA Status ER Register A/B                                 */
+
+        struct
+        {
+            __IM uint32_t ER0008 : 1;  /*!< [0..0] Channel 0/8 ER                                                     */
+            __IM uint32_t ER0109 : 1;  /*!< [1..1] Channel 1/9 ER                                                     */
+            __IM uint32_t ER0210 : 1;  /*!< [2..2] Channel 2/10 ER                                                    */
+            __IM uint32_t ER0311 : 1;  /*!< [3..3] Channel 3/11 ER                                                    */
+            __IM uint32_t ER0412 : 1;  /*!< [4..4] Channel 4/12 ER                                                    */
+            __IM uint32_t ER0513 : 1;  /*!< [5..5] Channel 5/13 ER                                                    */
+            __IM uint32_t ER0614 : 1;  /*!< [6..6] Channel 6/14 ER                                                    */
+            __IM uint32_t ER0715 : 1;  /*!< [7..7] Channel 7/15 ER                                                    */
+            uint32_t             : 24;
+        } DSTAT_ER_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_END;       /*!< (@ 0x00000318) DMA Status END Register A/B                                */
+
+        struct
+        {
+            __IM uint32_t END0008 : 1; /*!< [0..0] Channel 0/8 END                                                    */
+            __IM uint32_t END0109 : 1; /*!< [1..1] Channel 1/9 END                                                    */
+            __IM uint32_t END0210 : 1; /*!< [2..2] Channel 2/10 END                                                   */
+            __IM uint32_t END0311 : 1; /*!< [3..3] Channel 3/11 END                                                   */
+            __IM uint32_t END0412 : 1; /*!< [4..4] Channel 4/12 END                                                   */
+            __IM uint32_t END0513 : 1; /*!< [5..5] Channel 5/13 END                                                   */
+            __IM uint32_t END0614 : 1; /*!< [6..6] Channel 6/14 END                                                   */
+            __IM uint32_t END0715 : 1; /*!< [7..7] Channel 7/15 END                                                   */
+            uint32_t              : 24;
+        } DSTAT_END_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IM uint32_t DSTAT_SUS;       /*!< (@ 0x00000320) DMA Status SUS Register A/B                                */
+
+        struct
+        {
+            __IM uint32_t SUS0008 : 1; /*!< [0..0] Channel 0/8 SUS                                                    */
+            __IM uint32_t SUS0109 : 1; /*!< [1..1] Channel 1/9 SUS                                                    */
+            __IM uint32_t SUS0210 : 1; /*!< [2..2] Channel 2/10 SUS                                                   */
+            __IM uint32_t SUS0311 : 1; /*!< [3..3] Channel 3/11 SUS                                                   */
+            __IM uint32_t SUS0412 : 1; /*!< [4..4] Channel 4/12 SUS                                                   */
+            __IM uint32_t SUS0513 : 1; /*!< [5..5] Channel 5/13 SUS                                                   */
+            __IM uint32_t SUS0614 : 1; /*!< [6..6] Channel 6/14 SUS                                                   */
+            __IM uint32_t SUS0715 : 1; /*!< [7..7] Channel 7/15 SUS                                                   */
+            uint32_t              : 24;
+        } DSTAT_SUS_b;
+    };
+    __IM uint32_t RESERVED3[55];
+} R_DMAC0_GRP_Type;                    /*!< Size = 1024 (0x400)                                                       */
+
+/**
+ * @brief R_ETHSW_PTP_SWTM [SWTM] (Ethernet Switch Timer output pins 0-3 Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t EN;             /*!< (@ 0x00000000) PTP Timer Pulse Output Enable n Register                   */
+
+        struct
+        {
+            __IOM uint32_t OUTEN : 1;  /*!< [0..0] Enable ETHSW_PTPOUTn Signal Output                                 */
+            uint32_t             : 31;
+        } EN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STSEC;          /*!< (@ 0x00000004) PTP Timer Pulse Start Second n Register                    */
+
+        struct
+        {
+            __IOM uint32_t STSEC : 32; /*!< [31..0] STSEC                                                             */
+        } STSEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STNS;           /*!< (@ 0x00000008) PTP Timer Pulse Start Nanosecond n Register                */
+
+        struct
+        {
+            __IOM uint32_t STNS : 32;  /*!< [31..0] Start Time by Nanosecond                                          */
+        } STNS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PSEC;           /*!< (@ 0x0000000C) PTP Timer Pulse Period Second n Register                   */
+
+        struct
+        {
+            __IOM uint32_t PSEC : 32;  /*!< [31..0] PSEC                                                              */
+        } PSEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PNS;            /*!< (@ 0x00000010) PTP Timer Pulse Period Nanosecond n Register               */
+
+        struct
+        {
+            __IOM uint32_t PNS : 32;   /*!< [31..0] Period by Nanosecond                                              */
+        } PNS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WTH;            /*!< (@ 0x00000014) PTP Timer Pulse Width n Register                           */
+
+        struct
+        {
+            __IOM uint32_t WIDTH : 16; /*!< [15..0] Set the Pulse Width of ETHSW_PTPOUTn in the cycle number
+                                        *   of ts_clk (8 ns).                                                         */
+            uint32_t : 16;
+        } WTH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAXP;           /*!< (@ 0x00000018) PTP Timer Pulse Max Second n Register                      */
+
+        struct
+        {
+            __IOM uint32_t MAXP : 32;  /*!< [31..0] Sets the boundary value in nanoseconds to carry from
+                                        *   the nanosecond field to the second field. The same value
+                                        *   as ATIME_EVT_PERIOD register must be set.                                 */
+        } MAXP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LATSEC;          /*!< (@ 0x0000001C) PTP Timer Pulse Latch Second n Register                    */
+
+        struct
+        {
+            __IOM uint32_t LATSEC : 32; /*!< [31..0] LATSEC                                                            */
+        } LATSEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LATNS;          /*!< (@ 0x00000020) PTP Timer Pulse Latch Nanosecond n Register                */
+
+        struct
+        {
+            __IOM uint32_t LATNS : 32; /*!< [31..0] LATNS                                                             */
+        } LATNS_b;
+    };
+    __IM uint32_t RESERVED[55];
+} R_ETHSW_PTP_SWTM_Type;               /*!< Size = 256 (0x100)                                                        */
+
+/**
+ * @brief R_ETHSW_MGMT_ADDR [MGMT_ADDR] (MAC Address [0..3] for Bridge Protocol Frame Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t lo;                /*!< (@ 0x00000000) Lower MAC Address                                          */
+
+        struct
+        {
+            __IOM uint32_t BPDU_DST : 32; /*!< [31..0] Additional MAC address defining a Bridge Protocol Frame
+                                           *   (BPDU) in addition to the commonly-known addresses                        */
+        } lo_b;
+    };
+
+    union
+    {
+        __IOM uint32_t hi;                /*!< (@ 0x00000004) Higher MAC Address                                         */
+
+        struct
+        {
+            __IOM uint32_t BPDU_DST : 16; /*!< [15..0] Bits [7:0] is 5th byte, bits [15:8] is 6th (last) byte            */
+            __IOM uint32_t MASK     : 8;  /*!< [23..16] 8-bit mask for comparing the last byte of the MAC address.       */
+            uint32_t                : 8;
+        } hi_b;
+    };
+} R_ETHSW_MGMT_ADDR_Type;                 /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_ESC_FMMU [FMMU] (FMMU [0..7] Registers (n = 0 to 7))
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t L_START_ADR;      /*!< (@ 0x00000000) FMMU Logical Start Address n Register (n = 0
+                                         *                  to 7)                                                      */
+
+        struct
+        {
+            __IM uint32_t LSTAADR : 32; /*!< [31..0] Logical Start Address Setting                                     */
+        } L_START_ADR_b;
+    };
+
+    union
+    {
+        __IM uint16_t LEN;              /*!< (@ 0x00000004) FMMU Length n Register (n = 0 to 7)                        */
+
+        struct
+        {
+            __IM uint16_t FMMULEN : 16; /*!< [15..0] Area Size Specification                                           */
+        } LEN_b;
+    };
+
+    union
+    {
+        __IM uint8_t L_START_BIT;      /*!< (@ 0x00000006) FMMU Logical Start Bit n Register (n = 0 to 7)             */
+
+        struct
+        {
+            __IM uint8_t LSTABIT : 3;  /*!< [2..0] Start Bit Setting                                                  */
+            uint8_t              : 5;
+        } L_START_BIT_b;
+    };
+
+    union
+    {
+        __IM uint8_t L_STOP_BIT;       /*!< (@ 0x00000007) FMMU Logical Stop Bit n Register (n = 0 to 7)              */
+
+        struct
+        {
+            __IM uint8_t LSTPBIT : 3;  /*!< [2..0] Last Bit Setting                                                   */
+            uint8_t              : 5;
+        } L_STOP_BIT_b;
+    };
+
+    union
+    {
+        __IM uint16_t P_START_ADR;        /*!< (@ 0x00000008) FMMU Physical Start Address n Register (n = 0
+                                           *                  to 7)                                                      */
+
+        struct
+        {
+            __IM uint16_t PHYSTAADR : 16; /*!< [15..0] Physical Start Address Setting                                    */
+        } P_START_ADR_b;
+    };
+
+    union
+    {
+        __IM uint8_t P_START_BIT;       /*!< (@ 0x0000000A) FMMU Physical Start Bit n Register (n = 0 to
+                                         *                  7)                                                         */
+
+        struct
+        {
+            __IM uint8_t PHYSTABIT : 3; /*!< [2..0] Physical Start Bit Setting                                         */
+            uint8_t                : 5;
+        } P_START_BIT_b;
+    };
+
+    union
+    {
+        __IM uint8_t TYPE;             /*!< (@ 0x0000000B) FMMU Type n Register (n = 0 to 7)                          */
+
+        struct
+        {
+            __IM uint8_t READ  : 1;    /*!< [0..0] Read Access Mapping Setting                                        */
+            __IM uint8_t WRITE : 1;    /*!< [1..1] Write Access Mapping Setting                                       */
+            uint8_t            : 6;
+        } TYPE_b;
+    };
+
+    union
+    {
+        __IM uint8_t ACT;              /*!< (@ 0x0000000C) FMMU Activate n Register (n = 0 to 7)                      */
+
+        struct
+        {
+            __IM uint8_t ACTIVATE : 1; /*!< [0..0] FMMU Enable/Disable                                                */
+            uint8_t               : 7;
+        } ACT_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+} R_ESC_FMMU_Type;                     /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_ESC_SM [SM] (SyncManager [0..7] Registers (n = 0 to 7))
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint16_t P_START_ADR;        /*!< (@ 0x00000000) SyncManager Physical Start Address n Register
+                                           *                  (n = 0 to 7)                                               */
+
+        struct
+        {
+            __IM uint16_t SMSTAADDR : 16; /*!< [15..0] Physical Start Address Setting                                    */
+        } P_START_ADR_b;
+    };
+
+    union
+    {
+        __IM uint16_t LEN;             /*!< (@ 0x00000002) SyncManager Length n Register (n = 0 to 7)                 */
+
+        struct
+        {
+            __IM uint16_t SMLEN : 16;  /*!< [15..0] Area Size Setting                                                 */
+        } LEN_b;
+    };
+
+    union
+    {
+        __IM uint8_t CONTROL;          /*!< (@ 0x00000004) SyncManager Control n Register (n = 0 to 7)                */
+
+        struct
+        {
+            __IM uint8_t OPEMODE : 2;  /*!< [1..0] Operating Mode Setting                                             */
+            __IM uint8_t DIR     : 2;  /*!< [3..2] Transfer Direction Setting                                         */
+            __IM uint8_t IRQECAT : 1;  /*!< [4..4] ECAT Event Interrupt Setting                                       */
+            __IM uint8_t IRQPDI  : 1;  /*!< [5..5] AL Event Interrupt Setting                                         */
+            __IM uint8_t WDTRGEN : 1;  /*!< [6..6] Watchdog Trigger Setting                                           */
+            uint8_t              : 1;
+        } CONTROL_b;
+    };
+
+    union
+    {
+        __IM uint8_t STATUS;           /*!< (@ 0x00000005) SyncManager Status n Register (n = 0 to 7)                 */
+
+        struct
+        {
+            __IM uint8_t INTWR    : 1; /*!< [0..0] Write Complete Interrupt State Indication                          */
+            __IM uint8_t INTRD    : 1; /*!< [1..1] Read Complete Interrupt State Indication                           */
+            uint8_t               : 1;
+            __IM uint8_t MAILBOX  : 1; /*!< [3..3] Mailbox Status Indication                                          */
+            __IM uint8_t BUFFERED : 2; /*!< [5..4] Buffer Status Indication                                           */
+            __IM uint8_t RDBUF    : 1; /*!< [6..6] Read State Indication                                              */
+            __IM uint8_t WRBUF    : 1; /*!< [7..7] Write State Indication                                             */
+        } STATUS_b;
+    };
+
+    union
+    {
+        __IM uint8_t ACT;               /*!< (@ 0x00000006) SyncManager Activate n Register (n = 0 to 7)               */
+
+        struct
+        {
+            __IM uint8_t SMEN      : 1; /*!< [0..0] SyncManager Enable/Disable                                         */
+            __IM uint8_t REPEATREQ : 1; /*!< [1..1] Repeat Request                                                     */
+            uint8_t                : 4;
+            __IM uint8_t LATCHECAT : 1; /*!< [6..6] ECAT Latch Event Specification                                     */
+            __IM uint8_t LATCHPDI  : 1; /*!< [7..7] PDI Latch Event Specification                                      */
+        } ACT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PDI_CONT;          /*!< (@ 0x00000007) SyncManager PDI Control n Register (n = 0 to
+                                          *                  7)                                                         */
+
+        struct
+        {
+            __IOM uint8_t DEACTIVE  : 1; /*!< [0..0] SyncManager Operation Indication/Setting                           */
+            __IOM uint8_t REPEATACK : 1; /*!< [1..1] Repeat Acknowledge                                                 */
+            uint8_t                 : 6;
+        } PDI_CONT_b;
+    };
+} R_ESC_SM_Type;                         /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_XSPI0_CSa [CSa] (xSPI Command Map Configuration Register [0..1])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t CMCFG0;          /*!< (@ 0x00000000) xSPI Command Map Configuration Register 0 CSn              */
+
+        struct
+        {
+            __IOM uint32_t FFMT    : 2; /*!< [1..0] Frame format                                                       */
+            __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size                                                       */
+            __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode                                                */
+            __IOM uint32_t ARYAMD  : 1; /*!< [5..5] Array address mode                                                 */
+            uint32_t               : 10;
+            __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable                                           */
+            __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code                                             */
+        } CMCFG0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMCFG1;          /*!< (@ 0x00000004) xSPI Command Map Configuration Register 1 CSn              */
+
+        struct
+        {
+            __IOM uint32_t RDCMD  : 16; /*!< [15..0] Read command                                                      */
+            __IOM uint32_t RDLATE : 5;  /*!< [20..16] Read latency cycle                                               */
+            uint32_t              : 11;
+        } CMCFG1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMCFG2;          /*!< (@ 0x00000008) xSPI Command Map Configuration Register 2 CSn              */
+
+        struct
+        {
+            __IOM uint32_t WRCMD  : 16; /*!< [15..0] Write command                                                     */
+            __IOM uint32_t WRLATE : 5;  /*!< [20..16] Write latency cycle                                              */
+            uint32_t              : 11;
+        } CMCFG2_b;
+    };
+    __IM uint32_t RESERVED;
+} R_XSPI0_CSa_Type;                    /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_XSPI0_BUF [BUF] (xSPI Command Manual Buf [0..3])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t CDT;               /*!< (@ 0x00000000) xSPI Command Manual Type Buf                               */
+
+        struct
+        {
+            __IOM uint32_t CMDSIZE  : 2;  /*!< [1..0] Command Size                                                       */
+            __IOM uint32_t ADDSIZE  : 3;  /*!< [4..2] Address size                                                       */
+            __IOM uint32_t DATASIZE : 4;  /*!< [8..5] Write/Read Data Size                                               */
+            __IOM uint32_t LATE     : 5;  /*!< [13..9] Latency cycle                                                     */
+            uint32_t                : 1;
+            __IOM uint32_t TRTYPE   : 1;  /*!< [15..15] Transaction Type                                                 */
+            __IOM uint32_t CMD      : 16; /*!< [31..16] Command (1-2 bytes)                                              */
+        } CDT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDA;            /*!< (@ 0x00000004) xSPI Command Manual Address Buf                            */
+
+        struct
+        {
+            __IOM uint32_t ADD : 32;   /*!< [31..0] Address                                                           */
+        } CDA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDD0;           /*!< (@ 0x00000008) xSPI Command Manual Data 0 Buf                             */
+
+        struct
+        {
+            __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
+        } CDD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDD1;           /*!< (@ 0x0000000C) xSPI Command Manual Data 1 Buf                             */
+
+        struct
+        {
+            __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
+        } CDD1_b;
+    };
+} R_XSPI0_BUF_Type;                    /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_XSPI0_CSb [CSb] (xSPI Command Calibration Control register [0..1])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t CCCTL0;           /*!< (@ 0x00000000) xSPI Command Calibration Control Register 0 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CAEN     : 1; /*!< [0..0] Automatic Calibration Enable                                       */
+            __IOM uint32_t CANOWR   : 1; /*!< [1..1] Calibration no write mode                                          */
+            uint32_t                : 6;
+            __IOM uint32_t CAITV    : 5; /*!< [12..8] Calibration interval                                              */
+            uint32_t                : 3;
+            __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value                                 */
+            uint32_t                : 3;
+            __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value                                   */
+            uint32_t                : 3;
+        } CCCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL1;             /*!< (@ 0x00000004) xSPI Command Calibration Control Register 1 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CACMDSIZE  : 2; /*!< [1..0] Command Size                                                       */
+            __IOM uint32_t CAADDSIZE  : 3; /*!< [4..2] Address size                                                       */
+            __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size                                               */
+            uint32_t                  : 7;
+            __IOM uint32_t CAWRLATE   : 5; /*!< [20..16] Write Latency cycle                                              */
+            uint32_t                  : 3;
+            __IOM uint32_t CARDLATE   : 5; /*!< [28..24] Read Latency cycle                                               */
+            uint32_t                  : 3;
+        } CCCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL2;           /*!< (@ 0x00000008) xSPI Command Calibration Control Register 2 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command                                 */
+            __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command                                 */
+        } CCCTL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL3;         /*!< (@ 0x0000000C) xSPI Command Calibration Control Register 3 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address                                       */
+        } CCCTL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL4;          /*!< (@ 0x00000010) xSPI Command Calibration Control Register 4 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
+        } CCCTL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL5;          /*!< (@ 0x00000014) xSPI Command Calibration Control Register 5 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
+        } CCCTL5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL6;          /*!< (@ 0x00000018) xSPI Command Calibration Control Register 6 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
+        } CCCTL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCCTL7;          /*!< (@ 0x0000001C) xSPI Command Calibration Control Register 7 CSn            */
+
+        struct
+        {
+            __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
+        } CCCTL7_b;
+    };
+} R_XSPI0_CSb_Type;                     /*!< Size = 32 (0x20)                                                          */
+
+/**
+ * @brief R_PORT_PFC [PFC] (Port [0..12] Function Control Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t L;              /*!< (@ 0x00000000) Port m Function Control Register 0-3                       */
+
+        struct
+        {
+            __IOM uint32_t PFC0 : 6;   /*!< [5..0] Pm_0 Pin function Select                                           */
+            uint32_t            : 2;
+            __IOM uint32_t PFC1 : 6;   /*!< [13..8] Pm_1 Pin function Select                                          */
+            uint32_t            : 2;
+            __IOM uint32_t PFC2 : 6;   /*!< [21..16] Pm_2 Pin function Select                                         */
+            uint32_t            : 2;
+            __IOM uint32_t PFC3 : 6;   /*!< [29..24] Pm_3 Pin function Select                                         */
+            uint32_t            : 2;
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t H;              /*!< (@ 0x00000004) Port m Function Control Register 4-7                       */
+
+        struct
+        {
+            __IOM uint32_t PFC4 : 6;   /*!< [5..0] Pm_4 Pin function Select                                           */
+            uint32_t            : 2;
+            __IOM uint32_t PFC5 : 6;   /*!< [13..8] Pm_5 Pin function Select                                          */
+            uint32_t            : 2;
+            __IOM uint32_t PFC6 : 6;   /*!< [21..16] Pm_6 Pin function Select                                         */
+            uint32_t            : 2;
+            __IOM uint32_t PFC7 : 6;   /*!< [29..24] Pm_7 Pin function Select                                         */
+            uint32_t            : 2;
+        } H_b;
+    };
+} R_PORT_PFC_Type;                     /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_PORT_DRCTL [DRCTL] (I/O Buffer [0..12] Function Switching Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t L;              /*!< (@ 0x00000000) I/O Buffer m Function Switching Register 0-3               */
+
+        struct
+        {
+            __IOM uint32_t DRV0 : 2;   /*!< [1..0] Pm_0 Driving Ability Control                                       */
+            __IOM uint32_t PUD0 : 2;   /*!< [3..2] Pm_0 Pull-Up/Down Control                                          */
+            __IOM uint32_t SMT0 : 1;   /*!< [4..4] Pm_0 Schmitt Trigger Control                                       */
+            __IOM uint32_t SR0  : 1;   /*!< [5..5] Pm_0 Slew Rate Control                                             */
+            uint32_t            : 2;
+            __IOM uint32_t DRV1 : 2;   /*!< [9..8] Pm_1 Driving Ability Control                                       */
+            __IOM uint32_t PUD1 : 2;   /*!< [11..10] Pm_1 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT1 : 1;   /*!< [12..12] Pm_1 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR1  : 1;   /*!< [13..13] Pm_1 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV2 : 2;   /*!< [17..16] Pm_2 Driving Ability Control                                     */
+            __IOM uint32_t PUD2 : 2;   /*!< [19..18] Pm_2 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT2 : 1;   /*!< [20..20] Pm_2 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR2  : 1;   /*!< [21..21] Pm_2 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV3 : 2;   /*!< [25..24] Pm_3 Driving Ability Control                                     */
+            __IOM uint32_t PUD3 : 2;   /*!< [27..26] Pm_3 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT3 : 1;   /*!< [28..28] Pm_3 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR3  : 1;   /*!< [29..29] Pm_3 Slew Rate Control                                           */
+            uint32_t            : 2;
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t H;              /*!< (@ 0x00000004) I/O Buffer m Function Switching Register 4-7               */
+
+        struct
+        {
+            __IOM uint32_t DRV4 : 2;   /*!< [1..0] Pm_4 Driving Ability Control                                       */
+            __IOM uint32_t PUD4 : 2;   /*!< [3..2] Pm_4 Pull-Up/Down Control                                          */
+            __IOM uint32_t SMT4 : 1;   /*!< [4..4] Pm_4 Schmitt Trigger Control                                       */
+            __IOM uint32_t SR4  : 1;   /*!< [5..5] Pm_4 Slew Rate Control                                             */
+            uint32_t            : 2;
+            __IOM uint32_t DRV5 : 2;   /*!< [9..8] Pm_5 Driving Ability Control                                       */
+            __IOM uint32_t PUD5 : 2;   /*!< [11..10] Pm_5 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT5 : 1;   /*!< [12..12] Pm_5 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR5  : 1;   /*!< [13..13] Pm_5 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV6 : 2;   /*!< [17..16] Pm_6 Driving Ability Control                                     */
+            __IOM uint32_t PUD6 : 2;   /*!< [19..18] Pm_6 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT6 : 1;   /*!< [20..20] Pm_6 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR6  : 1;   /*!< [21..21] Pm_6 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV7 : 2;   /*!< [25..24] Pm_7 Driving Ability Control                                     */
+            __IOM uint32_t PUD7 : 2;   /*!< [27..26] Pm_7 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT7 : 1;   /*!< [28..28] Pm_7 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR7  : 1;   /*!< [29..29] Pm_7 Slew Rate Control                                           */
+            uint32_t            : 2;
+        } H_b;
+    };
+} R_PORT_DRCTL_Type;                   /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_PORT_NS_PFC [PFC] (Port [0..35] Function Control Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t L;              /*!< (@ 0x00000000) Port m Function Control Register 0-3                       */
+
+        struct
+        {
+            __IOM uint32_t PFC0 : 6;   /*!< [5..0] Pm_0 Pin function Select                                           */
+            uint32_t            : 2;
+            __IOM uint32_t PFC1 : 6;   /*!< [13..8] Pm_1 Pin function Select                                          */
+            uint32_t            : 2;
+            __IOM uint32_t PFC2 : 6;   /*!< [21..16] Pm_2 Pin function Select                                         */
+            uint32_t            : 2;
+            __IOM uint32_t PFC3 : 6;   /*!< [29..24] Pm_3 Pin function Select                                         */
+            uint32_t            : 2;
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t H;              /*!< (@ 0x00000004) Port m Function Control Register 4-7                       */
+
+        struct
+        {
+            __IOM uint32_t PFC4 : 6;   /*!< [5..0] Pm_4 Pin function Select                                           */
+            uint32_t            : 2;
+            __IOM uint32_t PFC5 : 6;   /*!< [13..8] Pm_5 Pin function Select                                          */
+            uint32_t            : 2;
+            __IOM uint32_t PFC6 : 6;   /*!< [21..16] Pm_6 Pin function Select                                         */
+            uint32_t            : 2;
+            __IOM uint32_t PFC7 : 6;   /*!< [29..24] Pm_7 Pin function Select                                         */
+            uint32_t            : 2;
+        } H_b;
+    };
+} R_PORT_NS_PFC_Type;                  /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_PORT_NS_DRCTL [DRCTL] (I/O Buffer [0..35] Function Switching Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t L;              /*!< (@ 0x00000000) I/O Buffer m Function Switching Register 0-3               */
+
+        struct
+        {
+            __IOM uint32_t DRV0 : 2;   /*!< [1..0] Pm_0 Driving Ability Control                                       */
+            __IOM uint32_t PUD0 : 2;   /*!< [3..2] Pm_0 Pull-Up/Down Control                                          */
+            __IOM uint32_t SMT0 : 1;   /*!< [4..4] Pm_0 Schmitt Trigger Control                                       */
+            __IOM uint32_t SR0  : 1;   /*!< [5..5] Pm_0 Slew Rate Control                                             */
+            uint32_t            : 2;
+            __IOM uint32_t DRV1 : 2;   /*!< [9..8] Pm_1 Driving Ability Control                                       */
+            __IOM uint32_t PUD1 : 2;   /*!< [11..10] Pm_1 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT1 : 1;   /*!< [12..12] Pm_1 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR1  : 1;   /*!< [13..13] Pm_1 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV2 : 2;   /*!< [17..16] Pm_2 Driving Ability Control                                     */
+            __IOM uint32_t PUD2 : 2;   /*!< [19..18] Pm_2 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT2 : 1;   /*!< [20..20] Pm_2 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR2  : 1;   /*!< [21..21] Pm_2 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV3 : 2;   /*!< [25..24] Pm_3 Driving Ability Control                                     */
+            __IOM uint32_t PUD3 : 2;   /*!< [27..26] Pm_3 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT3 : 1;   /*!< [28..28] Pm_3 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR3  : 1;   /*!< [29..29] Pm_3 Slew Rate Control                                           */
+            uint32_t            : 2;
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t H;              /*!< (@ 0x00000004) I/O Buffer m Function Switching Register 4-7               */
+
+        struct
+        {
+            __IOM uint32_t DRV4 : 2;   /*!< [1..0] Pm_4 Driving Ability Control                                       */
+            __IOM uint32_t PUD4 : 2;   /*!< [3..2] Pm_4 Pull-Up/Down Control                                          */
+            __IOM uint32_t SMT4 : 1;   /*!< [4..4] Pm_4 Schmitt Trigger Control                                       */
+            __IOM uint32_t SR4  : 1;   /*!< [5..5] Pm_4 Slew Rate Control                                             */
+            uint32_t            : 2;
+            __IOM uint32_t DRV5 : 2;   /*!< [9..8] Pm_5 Driving Ability Control                                       */
+            __IOM uint32_t PUD5 : 2;   /*!< [11..10] Pm_5 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT5 : 1;   /*!< [12..12] Pm_5 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR5  : 1;   /*!< [13..13] Pm_5 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV6 : 2;   /*!< [17..16] Pm_6 Driving Ability Control                                     */
+            __IOM uint32_t PUD6 : 2;   /*!< [19..18] Pm_6 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT6 : 1;   /*!< [20..20] Pm_6 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR6  : 1;   /*!< [21..21] Pm_6 Slew Rate Control                                           */
+            uint32_t            : 2;
+            __IOM uint32_t DRV7 : 2;   /*!< [25..24] Pm_7 Driving Ability Control                                     */
+            __IOM uint32_t PUD7 : 2;   /*!< [27..26] Pm_7 Pull-Up/Down Control                                        */
+            __IOM uint32_t SMT7 : 1;   /*!< [28..28] Pm_7 Schmitt Trigger Control                                     */
+            __IOM uint32_t SR7  : 1;   /*!< [29..29] Pm_7 Slew Rate Control                                           */
+            uint32_t            : 2;
+        } H_b;
+    };
+} R_PORT_NS_DRCTL_Type;                /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_PORT_NSR_ELC_PDBF [ELC_PDBF] (ELC Port Buffer Register [0..1])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t BY;              /*!< (@ 0x00000000) ELC Port Buffer Register n                                 */
+
+        struct
+        {
+            __IOM uint8_t PB0 : 1;     /*!< [0..0] Port Buffer 0                                                      */
+            __IOM uint8_t PB1 : 1;     /*!< [1..1] Port Buffer 1                                                      */
+            __IOM uint8_t PB2 : 1;     /*!< [2..2] Port Buffer 2                                                      */
+            __IOM uint8_t PB3 : 1;     /*!< [3..3] Port Buffer 3                                                      */
+            __IOM uint8_t PB4 : 1;     /*!< [4..4] Port Buffer 4                                                      */
+            __IOM uint8_t PB5 : 1;     /*!< [5..5] Port Buffer 5                                                      */
+            __IOM uint8_t PB6 : 1;     /*!< [6..6] Port Buffer 6                                                      */
+            __IOM uint8_t PB7 : 1;     /*!< [7..7] Port Buffer 7                                                      */
+        } BY_b;
+    };
+    __IM uint8_t RESERVED[3];
+} R_PORT_NSR_ELC_PDBF_Type;            /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_SYSRAM0_W [W] (System SRAM Wn Registers (n = 0 to 3))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t EC710CTL;        /*!< (@ 0x00000000) ECC Control Register                                       */
+
+        struct
+        {
+            __IM uint32_t  ECEMF   : 1; /*!< [0..0] ECC Error Indicate Flag                                            */
+            __IM uint32_t  ECER1F  : 1; /*!< [1..1] 1-Bit ECC Error Detection/Correction Flag                          */
+            __IM uint32_t  ECER2F  : 1; /*!< [2..2] 2-Bit ECC Error Detection Flag                                     */
+            __IOM uint32_t EC1EDIC : 1; /*!< [3..3] 1-Bit ECC Error Detection Interrupt Control                        */
+            __IOM uint32_t EC2EDIC : 1; /*!< [4..4] 2-Bit ECC Error Detection Interrupt Control                        */
+            __IOM uint32_t EC1ECP  : 1; /*!< [5..5] 1-Bit ECC Error Correction Enable                                  */
+            __IOM uint32_t ECERVF  : 1; /*!< [6..6] ECC Error Determination Enable                                     */
+            __IOM uint32_t ECTHM   : 1; /*!< [7..7] ECC Function Through Mode Enable                                   */
+            uint32_t               : 1;
+            __IOM uint32_t ECER1C  : 1; /*!< [9..9] 1-Bit ECC Error Detection Clear                                    */
+            __IOM uint32_t ECER2C  : 1; /*!< [10..10] 2-Bit ECC Error Detection Clear                                  */
+            __IM uint32_t  ECOVFF  : 1; /*!< [11..11] ECC Error Address Capture Overflow Flag                          */
+            uint32_t               : 2;
+            __IOM uint32_t EMCA    : 2; /*!< [15..14] Access Control to ECC Mode Selection                             */
+            __IM uint32_t  ECEDF0  : 2; /*!< [17..16] ECC Error Address Capture Flag m (m = 0)                         */
+            __IM uint32_t  ECEDF1  : 2; /*!< [19..18] ECC Error Address Capture Flag m (m = 1)                         */
+            __IM uint32_t  ECEDF2  : 2; /*!< [21..20] ECC Error Address Capture Flag m (m = 2)                         */
+            __IM uint32_t  ECEDF3  : 2; /*!< [23..22] ECC Error Address Capture Flag m (m = 3)                         */
+            __IM uint32_t  ECEDF4  : 2; /*!< [25..24] ECC Error Address Capture Flag m (m = 4)                         */
+            __IM uint32_t  ECEDF5  : 2; /*!< [27..26] ECC Error Address Capture Flag m (m = 5)                         */
+            __IM uint32_t  ECEDF6  : 2; /*!< [29..28] ECC Error Address Capture Flag m (m = 6)                         */
+            __IM uint32_t  ECEDF7  : 2; /*!< [31..30] ECC Error Address Capture Flag m (m = 7)                         */
+        } EC710CTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EC710TMC;       /*!< (@ 0x00000004) ECC Test Mode Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t ECREIS : 1; /*!< [0..0] ECC Redundancy Bit Input Data Select                               */
+            __IOM uint32_t ECDCS  : 1; /*!< [1..1] ECC Decode Input Select                                            */
+            __IOM uint32_t ECENS  : 1; /*!< [2..2] ECC Encode Input Select                                            */
+            __IOM uint32_t ECREOS : 1; /*!< [3..3] ECC Redundancy Bit Output Data Select                              */
+            __IOM uint32_t ECTRRS : 1; /*!< [4..4] RAM Read Test Mode Select                                          */
+            uint32_t              : 2;
+            __IOM uint32_t ECTMCE : 1; /*!< [7..7] Test Mode Enable                                                   */
+            uint32_t              : 6;
+            __IOM uint32_t ETMA   : 2; /*!< [15..14] ECTMCE Write Enable                                              */
+            uint32_t              : 16;
+        } EC710TMC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EC710TRC;       /*!< (@ 0x00000008) ECC Redundancy Bit Data Control Test Register              */
+
+        struct
+        {
+            __IOM uint32_t ECERDB : 7; /*!< [6..0] ECC Redundancy Bit Input/Output Substitute Buffer Register         */
+            uint32_t              : 1;
+            __IM uint32_t ECECRD  : 7; /*!< [14..8] ECC Encode Test Register                                          */
+            uint32_t              : 1;
+            __IM uint32_t ECHORD  : 7; /*!< [22..16] ECC 7-Redundancy-Bit Data Retain Test Register                   */
+            uint32_t              : 1;
+            __IM uint32_t ECSYND  : 7; /*!< [30..24] ECC Decode Syndrome Register                                     */
+            uint32_t              : 1;
+        } EC710TRC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EC710TED;       /*!< (@ 0x0000000C) ECC Encode/Decode Input/Output Switchover Test
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t ECEDB : 32; /*!< [31..0] 32-Bit Data Test Register for ECC Encode/Decode                   */
+        } EC710TED_b;
+    };
+
+    union
+    {
+        __IM uint32_t EC710EAD[8];     /*!< (@ 0x00000010) ECC Error Address [0..7] Register 0                        */
+
+        struct
+        {
+            __IM uint32_t ECEAD : 15;  /*!< [14..0] Bit Error Address                                                 */
+            uint32_t            : 17;
+        } EC710EAD_b[8];
+    };
+    __IM uint32_t RESERVED[4];
+} R_SYSRAM0_W_Type;                    /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_MPU10_RGN [RGN] (Master MPU Safety Region Start Address Register [0..15])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t STADD;            /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register            */
+
+        struct
+        {
+            __IOM uint32_t RDPR    : 1;  /*!< [0..0] RDPR                                                               */
+            __IOM uint32_t WRPR    : 1;  /*!< [1..1] WRPR                                                               */
+            uint32_t               : 2;
+            __IOM uint32_t STADDR2 : 3;  /*!< [6..4] Start address for MPU region                                       */
+            uint32_t               : 3;
+            __IOM uint32_t STADDR  : 22; /*!< [31..10] Start address for MPU region                                     */
+        } STADD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDADD;         /*!< (@ 0x00000004) Master MPU Safety Region End Address Register              */
+
+        struct
+        {
+            uint32_t                : 4;
+            __IOM uint32_t ENDADDR2 : 3;  /*!< [6..4] End address for MPU region                                         */
+            uint32_t                : 3;
+            __IOM uint32_t ENDADDR  : 22; /*!< [31..10] End address for MPU region                                       */
+        } ENDADD_b;
+    };
+} R_MPU10_RGN_Type;                       /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_CA55_RVBA [RVBA] (CA55 Core [0..3] Reset Vector Address Configuration Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t L;              /*!< (@ 0x00000000) Cortex-A55 Core n Reset Vector Address Low                 */
+
+        struct
+        {
+            uint32_t                  : 2;
+            __IOM uint32_t RVBARADDRL : 30; /*!< [31..2] Cortex-A55 Core n Reset Vector Address Low                        */
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint32_t H;                  /*!< (@ 0x00000004) Cortex-A55 Core n Reset Vector Address High                */
+
+        struct
+        {
+            __IOM uint32_t RVBARADDRH : 8; /*!< [7..0] Cortex-A55 Core n Reset Vector Address High                        */
+            uint32_t                  : 24;
+        } H_b;
+    };
+} R_CA55_RVBA_Type;                        /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_DSMIF0_CH_TR [TR] (Overcurrent Threshold Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t DSOCL;             /*!< (@ 0x00000000) Overcurrent Low Threshold Register                         */
+
+        struct
+        {
+            __IOM uint32_t OCMPTBL0 : 16; /*!< [15..0] Overcurrent detection lower limit 0                               */
+            uint32_t                : 16;
+        } DSOCL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSOCH;             /*!< (@ 0x00000004) Overcurrent High Threshold Register                        */
+
+        struct
+        {
+            __IOM uint32_t OCMPTBH0 : 16; /*!< [15..0] Overcurrent detection upper limit 0                               */
+            uint32_t                : 16;
+        } DSOCH_b;
+    };
+} R_DSMIF0_CH_TR_Type;                    /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_DSMIF0_CH_DR [DR] (Overcurrent Threshold Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t DSCOC;           /*!< (@ 0x00000000) Capture Overcurrent Data Register                          */
+
+        struct
+        {
+            __IM uint32_t CODR0 : 16;  /*!< [15..0] Capture overcurrent data 0                                        */
+            uint32_t            : 16;
+        } DSCOC_b;
+    };
+} R_DSMIF0_CH_DR_Type;                 /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_DSMIF0_CH [CH] (Channel Registers [0..2])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t DSICR;          /*!< (@ 0x00000000) Interrupt Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t IUE   : 1;  /*!< [0..0] Current data register update interrupt enable                      */
+            __IOM uint32_t IAUE  : 1;  /*!< [1..1] Capture current data register A update interrupt enable            */
+            __IOM uint32_t IBUE  : 1;  /*!< [2..2] Capture current data register B update interrupt enable            */
+            __IOM uint32_t ISE   : 1;  /*!< [3..3] Short circuit detection error interrupt enable bit                 */
+            uint32_t             : 4;
+            __IOM uint32_t IOEL0 : 1;  /*!< [8..8] Overcurrent lower limit detection interrupt 0                      */
+            __IOM uint32_t IOEH0 : 1;  /*!< [9..9] Overcurrent upper limit exceeded detection interrupt
+                                        *   0                                                                         */
+            __IOM uint32_t IOEL1 : 1;  /*!< [10..10] Overcurrent lower limit detection interrupt 1                    */
+            __IOM uint32_t IOEH1 : 1;  /*!< [11..11] Overcurrent upper limit exceeded detection interrupt
+                                        *   1                                                                         */
+            __IOM uint32_t IOEL2 : 1;  /*!< [12..12] Overcurrent lower limit detection interrupt 2                    */
+            __IOM uint32_t IOEH2 : 1;  /*!< [13..13] Overcurrent upper limit exceeded detection interrupt
+                                        *   2                                                                         */
+            uint32_t             : 2;
+            __IOM uint32_t OWNE0 : 1;  /*!< [16..16] Overcurrent detection window notification 0 output
+                                        *   enable                                                                    */
+            __IOM uint32_t OWNE1 : 1;  /*!< [17..17] Overcurrent detection window notification 1 output
+                                        *   enable                                                                    */
+            __IOM uint32_t OWNE2 : 1;  /*!< [18..18] Overcurrent detection window notification 2 output
+                                        *   enable                                                                    */
+            __IOM uint32_t OWNE3 : 1;  /*!< [19..19] Overcurrent detection window notification 3 output
+                                        *   enable                                                                    */
+            uint32_t : 12;
+        } DSICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCMCCR;        /*!< (@ 0x00000004) Current Measurement Clock Control Register                 */
+
+        struct
+        {
+            __IOM uint32_t CKDIR : 1;  /*!< [0..0] A/D conversion clock master/slave switching                        */
+            uint32_t             : 6;
+            __IOM uint32_t SEDGE : 1;  /*!< [7..7] Sampling edge selection                                            */
+            __IOM uint32_t CKDIV : 6;  /*!< [13..8] A/D conversion clock division ratio                               */
+            uint32_t             : 18;
+        } DSCMCCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCMFCR;        /*!< (@ 0x00000008) Current Measurement Filter Control Register                */
+
+        struct
+        {
+            __IOM uint32_t CMSINC : 2; /*!< [1..0] Current measurement filter order setting                           */
+            uint32_t              : 6;
+            __IOM uint32_t CMDEC  : 8; /*!< [15..8] Decimation ratio selection for current measurement                */
+            __IOM uint32_t CMSH   : 5; /*!< [20..16] Data shift setting for current measurement                       */
+            uint32_t              : 11;
+        } DSCMFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCMCTCR;       /*!< (@ 0x0000000C) Current Measurement Capture Trigger Control Register       */
+
+        struct
+        {
+            __IOM uint32_t CTSELA : 3; /*!< [2..0] Current capture trigger A selection bit                            */
+            uint32_t              : 5;
+            __IOM uint32_t CTSELB : 3; /*!< [10..8] Current capture trigger B selection bit                           */
+            uint32_t              : 5;
+            __IOM uint32_t DITSEL : 2; /*!< [17..16] Current measurement filter initialization trigger selection
+                                        *   bit for frequency division counter for decimation.                        */
+            uint32_t             : 5;
+            __IOM uint32_t DEDGE : 1;  /*!< [23..23] Current measurement filter initialization trigger for
+                                        *   division counter for decimation edge selection bit. The
+                                        *   trigger from ELC is usually used positive edge. Change
+                                        *   from the initial value if necessary.                                      */
+            uint32_t : 8;
+        } DSCMCTCR_b;
+    };
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint32_t DSEDCR;         /*!< (@ 0x00000020) Error Detect Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t SDE : 1;    /*!< [0..0] Short circuit detection enable bit                                 */
+            uint32_t           : 31;
+        } DSEDCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSCTSR;        /*!< (@ 0x00000024) Short Circuit Threshold Setting Register                   */
+
+        struct
+        {
+            __IOM uint32_t SCNTL : 13; /*!< [12..0] Short circuit detection low continuous detection count            */
+            uint32_t             : 3;
+            __IOM uint32_t SCNTH : 13; /*!< [28..16] Short circuit detection high continuous detection count          */
+            uint32_t             : 3;
+        } DSSCTSR_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t DSOCFCR;        /*!< (@ 0x00000030) Overcurrent Detect Filter Control Register                 */
+
+        struct
+        {
+            __IOM uint32_t OCSINC : 2; /*!< [1..0] Overcurrent detection filter order setting                         */
+            uint32_t              : 6;
+            __IOM uint32_t OCDEC  : 8; /*!< [15..8] Decimation ratio selection for overcurrent detection              */
+            __IOM uint32_t OCSH   : 5; /*!< [20..16] Data shift setting for overcurrent detection                     */
+            uint32_t              : 11;
+        } DSOCFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSODCR;         /*!< (@ 0x00000034) Overcurrent Detect Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t ODEL0 : 1;  /*!< [0..0] Overcurrent lower limit detection 0 enable                         */
+            __IOM uint32_t ODEH0 : 1;  /*!< [1..1] Overcurrent upper limit exceeded detection 0 enable                */
+            __IOM uint32_t ODEL1 : 1;  /*!< [2..2] Overcurrent lower limit detection 1 enable                         */
+            __IOM uint32_t ODEH1 : 1;  /*!< [3..3] Overcurrent upper limit exceeded detection 1 enable                */
+            __IOM uint32_t ODEL2 : 1;  /*!< [4..4] Overcurrent lower limit detection 2 enable                         */
+            __IOM uint32_t ODEH2 : 1;  /*!< [5..5] Overcurrent upper limit exceeded detection 2 enable                */
+            uint32_t             : 2;
+            __IOM uint32_t OWFE0 : 1;  /*!< [8..8] Overcurrent lower limit detection interrupt 0                      */
+            __IOM uint32_t OWFE1 : 1;  /*!< [9..9] Overcurrent detection window function 0 enable                     */
+            __IOM uint32_t OWFE2 : 1;  /*!< [10..10] Overcurrent detection window function 1 enable                   */
+            __IOM uint32_t OWFE3 : 1;  /*!< [11..11] Overcurrent detection window function 2 enable                   */
+            uint32_t             : 20;
+        } DSODCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSODWCR;        /*!< (@ 0x00000038) Overcurrent Detect Window Control Register                 */
+
+        struct
+        {
+            __IOM uint32_t OWNM0 : 1;  /*!< [0..0] Channel n overcurrent detection window notification 0
+                                        *   mode select                                                               */
+            __IOM uint32_t OWNM1 : 1;  /*!< [1..1] Channel n overcurrent detection window notification 1
+                                        *   mode select                                                               */
+            __IOM uint32_t OWNM2 : 1;  /*!< [2..2] Channel n overcurrent detection window notification 2
+                                        *   mode select                                                               */
+            __IOM uint32_t OWNM3 : 4;  /*!< [6..3] Channel n overcurrent detection window notification 3
+                                        *   mode select                                                               */
+            uint32_t : 25;
+        } DSODWCR_b;
+    };
+    __IM uint32_t             RESERVED2[25];
+    __IOM R_DSMIF0_CH_TR_Type TR[3];   /*!< (@ 0x000000A0) Overcurrent Threshold Registers                            */
+    __IM uint32_t             RESERVED3[10];
+
+    union
+    {
+        __IOM uint32_t DSCSTRTR;       /*!< (@ 0x000000E0) Software Start Trigger Register                            */
+
+        struct
+        {
+            __IOM uint32_t STRTRG : 1; /*!< [0..0] Channel start trigger                                              */
+            uint32_t              : 31;
+        } DSCSTRTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCSTPTR;       /*!< (@ 0x000000E4) Software Stop Trigger Register                             */
+
+        struct
+        {
+            __IOM uint32_t STPTRG : 1; /*!< [0..0] Channel stop trigger                                               */
+            uint32_t              : 31;
+        } DSCSTPTR_b;
+    };
+    __IM uint32_t RESERVED4[2];
+
+    union
+    {
+        __IM uint32_t DSCDR;           /*!< (@ 0x000000F0) Current Data Register                                      */
+
+        struct
+        {
+            __IM uint32_t ADDR : 16;   /*!< [15..0] Current data                                                      */
+            uint32_t           : 16;
+        } DSCDR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCCDRA;         /*!< (@ 0x000000F4) Capture Current Data Register A                            */
+
+        struct
+        {
+            __IM uint32_t CDRA : 16;   /*!< [15..0] Capture current data A                                            */
+            uint32_t           : 16;
+        } DSCCDRA_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCCDRB;         /*!< (@ 0x000000F8) Capture Current Data Register B                            */
+
+        struct
+        {
+            __IM uint32_t CDRB : 16;   /*!< [15..0] Capture current data B                                            */
+            uint32_t           : 16;
+        } DSCCDRB_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSOCDR;          /*!< (@ 0x000000FC) Overcurrent Data Register                                  */
+
+        struct
+        {
+            __IM uint32_t ODR : 16;    /*!< [15..0] Overcurrent data                                                  */
+            uint32_t          : 16;
+        } DSOCDR_b;
+    };
+    __IOM R_DSMIF0_CH_DR_Type DR[3];   /*!< (@ 0x00000100) Overcurrent Threshold Registers                            */
+    __IM uint32_t             RESERVED5[5];
+
+    union
+    {
+        __IM uint32_t DSCSR;           /*!< (@ 0x00000120) Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t DUF     : 1; /*!< [0..0] Channel n data update flag                                         */
+            __IM uint32_t CAUF    : 1; /*!< [1..1] Channel n capture data A update flag                               */
+            __IM uint32_t CBUF    : 1; /*!< [2..2] Channel n capture data B update flag                               */
+            __IM uint32_t SCF     : 1; /*!< [3..3] Channel n short circuit detection flag                             */
+            uint32_t              : 3;
+            __IM uint32_t CHSTATE : 1; /*!< [7..7] Channel n state                                                    */
+            __IM uint32_t OC0FL   : 1; /*!< [8..8] Channel n overcurrent lower limit detection 0 flag                 */
+            __IM uint32_t OC0FH   : 1; /*!< [9..9] Channel n overcurrent upper limit exceeded 0 flag                  */
+            __IM uint32_t OC1FL   : 1; /*!< [10..10] Channel n overcurrent lower limit detection 1 flag               */
+            __IM uint32_t OC1FH   : 1; /*!< [11..11] Channel n overcurrent upper limit exceeded 1 flag                */
+            __IM uint32_t OC2FL   : 1; /*!< [12..12] Channel n overcurrent lower limit detection 2 flag               */
+            __IM uint32_t OC2FH   : 1; /*!< [13..13] Channel n overcurrent upper limit exceeded 2 flag                */
+            uint32_t              : 2;
+            __IM uint32_t OWD0N   : 1; /*!< [16..16] Channel n overcurrent detection window notification
+                                        *   0                                                                         */
+            __IM uint32_t OWD1N : 1;   /*!< [17..17] Channel n overcurrent detection window notification
+                                        *   1                                                                         */
+            __IM uint32_t OWD2N : 1;   /*!< [18..18] Channel n overcurrent detection window notification
+                                        *   2                                                                         */
+            __IM uint32_t OWD3N : 1;   /*!< [19..19] Channel n overcurrent detection window notification
+                                        *   3                                                                         */
+            uint32_t              : 4;
+            __IM uint32_t OC0CMPL : 1; /*!< [24..24] Channel n overcurrent detect 0 lower limit compare
+                                        *   result                                                                    */
+            __IM uint32_t OC0CMPH : 1; /*!< [25..25] Channel n overcurrent detect 0 upper limit compare
+                                        *   result                                                                    */
+            __IM uint32_t OC1CMPL : 1; /*!< [26..26] Channel n overcurrent detect 1 lower limit compare
+                                        *   result                                                                    */
+            __IM uint32_t OC1CMPH : 1; /*!< [27..27] Channel n overcurrent detect 1 upper limit compare
+                                        *   result                                                                    */
+            __IM uint32_t OC2CMPL : 1; /*!< [28..28] Channel n overcurrent detect 2 lower limit compare
+                                        *   result                                                                    */
+            __IM uint32_t OC2CMPH : 1; /*!< [29..29] Channel n overcurrent detect 2 upper limit compare
+                                        *   result                                                                    */
+            uint32_t : 2;
+        } DSCSR_b;
+    };
+    __IM uint32_t RESERVED6[3];
+
+    union
+    {
+        __OM uint32_t DSCSCR;           /*!< (@ 0x00000130) Status Clear Register                                      */
+
+        struct
+        {
+            __OM uint32_t CLRDUF   : 1; /*!< [0..0] Channel n data update flag clear                                   */
+            __OM uint32_t CLRCAUF  : 1; /*!< [1..1] Channel n capture data A update flag clear                         */
+            __OM uint32_t CLRCBUF  : 1; /*!< [2..2] Channel n capture data B update flag clear                         */
+            __OM uint32_t CLRSCF   : 1; /*!< [3..3] Channel n short circuit detection flag clear                       */
+            uint32_t               : 4;
+            __OM uint32_t CLROC0FL : 1; /*!< [8..8] Channel n overcurrent lower limit detection flag 0 clear           */
+            __OM uint32_t CLROC0FH : 1; /*!< [9..9] Channel n overcurrent upper limit exceeded flag 0 clear            */
+            __OM uint32_t CLROC1FL : 1; /*!< [10..10] Channel n overcurrent lower limit detection flag 1
+                                         *   clear                                                                     */
+            __OM uint32_t CLROC1FH : 1; /*!< [11..11] Channel n overcurrent upper limit exceeded flag 1 clear          */
+            __OM uint32_t CLROC2FL : 1; /*!< [12..12] Channel n overcurrent lower limit detection flag 2
+                                         *   clear                                                                     */
+            __OM uint32_t CLROC2FH : 1; /*!< [13..13] Channel n overcurrent upper limit exceeded flag 2 clear          */
+            uint32_t               : 2;
+            __OM uint32_t CLROWD0N : 1; /*!< [16..16] Channel n overcurrent detection window notification
+                                         *   0 flag clear                                                              */
+            __OM uint32_t CLROWD1N : 1; /*!< [17..17] Channel n overcurrent detection window notification
+                                         *   1 flag clear                                                              */
+            __OM uint32_t CLROWD2N : 1; /*!< [18..18] Channel n overcurrent detection window notification
+                                         *   2 flag clear                                                              */
+            __OM uint32_t CLROWD3N : 1; /*!< [19..19] Channel n overcurrent detection window notification
+                                         *   3 flag clear                                                              */
+            uint32_t : 12;
+        } DSCSCR_b;
+    };
+    __IM uint32_t RESERVED7[3];
+} R_DSMIF0_CH_Type;                    /*!< Size = 320 (0x140)                                                        */
+
+/**
+ * @brief R_BISS0_SCDATA [SCDATA] (Sensor Data [0..7])
+ */
+typedef struct
+{
+    __IOM uint32_t L;                  /*!< (@ 0x00000000) Sensor Data L                                              */
+    __IOM uint32_t H;                  /*!< (@ 0x00000004) Sensor Data H                                              */
+} R_BISS0_SCDATA_Type;                 /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_USBF_PIPE_TR [PIPE_TR] (PIPEn Transaction Counter Registers (n=1-5))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t E;              /*!< (@ 0x00000000) PIPEn Transaction Counter Enable Register                  */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
+            __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
+            uint16_t             : 6;
+        } E_b;
+    };
+
+    union
+    {
+        __IOM uint16_t N;               /*!< (@ 0x00000002) PIPEn Transaction Counter Register                         */
+
+        struct
+        {
+            __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
+        } N_b;
+    };
+} R_USBF_PIPE_TR_Type;                  /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_USBF_CHa_N [N] (Address Registers n (n=0-1))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t SA;             /*!< (@ 0x00000000) Next Source Address Register                               */
+
+        struct
+        {
+            __IOM uint32_t SAWD : 32;  /*!< [31..0] Source Address or Write Data                                      */
+        } SA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DA;             /*!< (@ 0x00000004) Next Destination Address Register                          */
+
+        struct
+        {
+            __IOM uint32_t DA : 32;    /*!< [31..0] Destination Address                                               */
+        } DA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TB;             /*!< (@ 0x00000008) Next Transaction Byte Register                             */
+
+        struct
+        {
+            __IOM uint32_t TB : 32;    /*!< [31..0] Transaction Byte                                                  */
+        } TB_b;
+    };
+} R_USBF_CHa_N_Type;                   /*!< Size = 12 (0xc)                                                           */
+
+/**
+ * @brief R_USBF_CHa [CHa] (Next Register Set)
+ */
+typedef struct
+{
+    __IOM R_USBF_CHa_N_Type N[2];      /*!< (@ 0x00000000) Address Registers n (n=0-1)                                */
+
+    union
+    {
+        __IM uint32_t CRSA;            /*!< (@ 0x00000018) Current Source Address Register                            */
+
+        struct
+        {
+            __IM uint32_t CRSA : 32;   /*!< [31..0] Source Address                                                    */
+        } CRSA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CRDA;            /*!< (@ 0x0000001C) Current Destination Address Register                       */
+
+        struct
+        {
+            __IM uint32_t CRDA : 32;   /*!< [31..0] Destination Address                                               */
+        } CRDA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CRTB;            /*!< (@ 0x00000020) Current Transaction Byte Register                          */
+
+        struct
+        {
+            __IM uint32_t CRTB : 32;   /*!< [31..0] Transaction Byte                                                  */
+        } CRTB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CHSTAT;          /*!< (@ 0x00000024) Channel Status Register                                    */
+
+        struct
+        {
+            __IM uint32_t EN     : 1;  /*!< [0..0] Enable                                                             */
+            __IM uint32_t RQST   : 1;  /*!< [1..1] Request                                                            */
+            __IM uint32_t TACT   : 1;  /*!< [2..2] Transaction Active                                                 */
+            __IM uint32_t SUS    : 1;  /*!< [3..3] Suspend                                                            */
+            __IM uint32_t ER     : 1;  /*!< [4..4] Error                                                              */
+            __IM uint32_t END    : 1;  /*!< [5..5] USB_FDMAn Interrupted                                              */
+            __IM uint32_t TC     : 1;  /*!< [6..6] Terminal Count                                                     */
+            __IM uint32_t SR     : 1;  /*!< [7..7] Selected Register Set                                              */
+            __IM uint32_t DL     : 1;  /*!< [8..8] Descriptor Load                                                    */
+            __IM uint32_t DW     : 1;  /*!< [9..9] Descriptor WriteBack                                               */
+            __IM uint32_t DER    : 1;  /*!< [10..10] Descriptor Error                                                 */
+            __IM uint32_t MODE   : 1;  /*!< [11..11] DMA Mode                                                         */
+            uint32_t             : 4;
+            __IM uint32_t INTM   : 1;  /*!< [16..16] Interrupt Mask                                                   */
+            __IM uint32_t DMARQM : 1;  /*!< [17..17] DMAREQ Mask                                                      */
+            __IM uint32_t SWPRQ  : 1;  /*!< [18..18] Sweep Request                                                    */
+            uint32_t             : 5;
+            __IM uint32_t DNUM   : 8;  /*!< [31..24] Data Number                                                      */
+        } CHSTAT_b;
+    };
+
+    union
+    {
+        __OM uint32_t CHCTRL;            /*!< (@ 0x00000028) Channel Control Register                                   */
+
+        struct
+        {
+            __OM uint32_t SETEN     : 1; /*!< [0..0] Set Enable                                                         */
+            __OM uint32_t CLREN     : 1; /*!< [1..1] Clear Enable                                                       */
+            __OM uint32_t STG       : 1; /*!< [2..2] Software Trigger                                                   */
+            __OM uint32_t SWRST     : 1; /*!< [3..3] Software Reset                                                     */
+            __OM uint32_t CLRRQ     : 1; /*!< [4..4] Clear Request                                                      */
+            __OM uint32_t CLREND    : 1; /*!< [5..5] Clear End                                                          */
+            __OM uint32_t CLRTC     : 1; /*!< [6..6] Clear TC                                                           */
+            __OM uint32_t CLRDER    : 1; /*!< [7..7] Clear DER                                                          */
+            __OM uint32_t SETSUS    : 1; /*!< [8..8] Set Suspend                                                        */
+            __OM uint32_t CLRSUS    : 1; /*!< [9..9] Clear Suspend                                                      */
+            uint32_t                : 2;
+            __OM uint32_t SETREN    : 1; /*!< [12..12] Set Register Set Enable                                          */
+            uint32_t                : 1;
+            __OM uint32_t SETSSWPRQ : 1; /*!< [14..14] Set Software Sweep Request                                       */
+            uint32_t                : 1;
+            __OM uint32_t SETINTM   : 1; /*!< [16..16] Set Interrupt Mask                                               */
+            __OM uint32_t CLRINTM   : 1; /*!< [17..17] Clear Interrupt Mask                                             */
+            __OM uint32_t SETDMARQM : 1; /*!< [18..18] SET DMAREQ Mask                                                  */
+            __OM uint32_t CLRDMARQM : 1; /*!< [19..19] Clear DMAREQ Mask                                                */
+            uint32_t                : 12;
+        } CHCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHCFG;          /*!< (@ 0x0000002C) Channel Configuration Register                             */
+
+        struct
+        {
+            __IOM uint32_t SEL  : 1;   /*!< [0..0] Terminal Select                                                    */
+            uint32_t            : 2;
+            __IOM uint32_t REQD : 1;   /*!< [3..3] Request Direction                                                  */
+            __IOM uint32_t LOEN : 1;   /*!< [4..4] Sets the transfer request signal between the USB control
+                                        *   and the DMAC.                                                             */
+            __IOM uint32_t HIEN : 1;   /*!< [5..5] Sets the transfer request signal between the USB control
+                                        *   and the DMAC.                                                             */
+            __IOM uint32_t LVL : 1;    /*!< [6..6] Sets the transfer request signal between the USB control
+                                        *   and the DMAC.                                                             */
+            uint32_t          : 1;
+            __IOM uint32_t AM : 3;     /*!< [10..8] These bits set the transfer request signal between the
+                                        *   USB control and the DMAC.                                                 */
+            __IOM uint32_t DRRP : 1;   /*!< [11..11] Descriptor Read Repeat                                           */
+            __IOM uint32_t SDS  : 4;   /*!< [15..12] Source Data Size                                                 */
+            __IOM uint32_t DDS  : 4;   /*!< [19..16] Destination Data Size                                            */
+            __IOM uint32_t SAD  : 1;   /*!< [20..20] Source Address Direction                                         */
+            __IOM uint32_t DAD  : 1;   /*!< [21..21] Destination Address Direction                                    */
+            __IOM uint32_t TM   : 1;   /*!< [22..22] Sets the transfer request signal between the USB control
+                                        *   and the DMAC.                                                             */
+            __IOM uint32_t WONLY : 1;  /*!< [23..23] Write Only Mode                                                  */
+            __IOM uint32_t DEM   : 1;  /*!< [24..24] USB_FDMAn Mask                                                   */
+            uint32_t             : 1;
+            __IOM uint32_t DIM   : 1;  /*!< [26..26] Descriptor Interrupt Mask                                        */
+            __IOM uint32_t SBE   : 1;  /*!< [27..27] Sweep Buffer Enable                                              */
+            __IOM uint32_t RSEL  : 1;  /*!< [28..28] Register Set Select                                              */
+            __IOM uint32_t RSW   : 1;  /*!< [29..29] Register Select Switch                                           */
+            __IOM uint32_t REN   : 1;  /*!< [30..30] Register Set Enable                                              */
+            __IOM uint32_t DMS   : 1;  /*!< [31..31] DMA Mode Select                                                  */
+        } CHCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHITVL;         /*!< (@ 0x00000030) Channel Interval Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ITVL : 16;  /*!< [15..0] Interval                                                          */
+            uint32_t            : 16;
+        } CHITVL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHEXT;          /*!< (@ 0x00000034) Channel Extension Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SPR : 4;    /*!< [3..0] Source PROT                                                        */
+            uint32_t           : 4;
+            __IOM uint32_t DPR : 4;    /*!< [11..8] Destination PROT                                                  */
+            uint32_t           : 20;
+        } CHEXT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NXLA;           /*!< (@ 0x00000038) Next Link Address Register                                 */
+
+        struct
+        {
+            __IOM uint32_t NXLA : 32;  /*!< [31..0] Next Link Address                                                 */
+        } NXLA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CRLA;            /*!< (@ 0x0000003C) Current Link Address Register                              */
+
+        struct
+        {
+            __IM uint32_t CRLA : 32;   /*!< [31..0] Current Link Address                                              */
+        } CRLA_b;
+    };
+} R_USBF_CHa_Type;                     /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_USBF_CHb [CHb] (Skip Register Set)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t SCNT;           /*!< (@ 0x00000000) Source Continuous Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SCNT : 32;  /*!< [31..0] Source Continuous                                                 */
+        } SCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSKP;           /*!< (@ 0x00000004) Source Skip Register                                       */
+
+        struct
+        {
+            __IOM uint32_t SSKP : 32;  /*!< [31..0] Source Skip                                                       */
+        } SSKP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DCNT;           /*!< (@ 0x00000008) Destination Continuous Register                            */
+
+        struct
+        {
+            __IOM uint32_t DCNT : 32;  /*!< [31..0] Destination Continuous                                            */
+        } DCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSKP;           /*!< (@ 0x0000000C) Destination Skip Register                                  */
+
+        struct
+        {
+            __IOM uint32_t DSKP : 32;  /*!< [31..0] Destination Skip                                                  */
+        } DSKP_b;
+    };
+    __IM uint32_t RESERVED[4];
+} R_USBF_CHb_Type;                     /*!< Size = 32 (0x20)                                                          */
+
+/**
+ * @brief R_PCIE0_PCI_REQDATA [PCI_REQDATA] ([0..2])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t EP;             /*!< (@ 0x00000000) Request Data Register n (n = 0 to 2)                       */
+        __IOM uint32_t RC;             /*!< (@ 0x00000000) Request Data Register n (n = 0 to 2)                       */
+    };
+} R_PCIE0_PCI_REQDATA_Type;            /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_PCIE0_PCI_RC_MSIRCV [PCI_RC_MSIRCV] ([0..15])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t E;              /*!< (@ 0x00000000) MSI Receive Enable Register n (n = 0 to 15)                */
+
+        struct
+        {
+            __IOM uint32_t E : 1;      /*!< [0..0] Enable                                                             */
+            uint32_t         : 31;
+        } E_b;
+    };
+    __IOM uint32_t MSGDATA;            /*!< (@ 0x00000004) MSI Receive Message Data Register n (n = 0 to
+                                        *                  15)                                                        */
+    __IOM uint32_t MSK;                /*!< (@ 0x00000008) MSI Receive Mask Register n (n = 0 to 15)                  */
+    __IOM uint32_t STAT;               /*!< (@ 0x0000000C) MSI Receive Status Register n (n = 0 to 15)                */
+} R_PCIE0_PCI_RC_MSIRCV_Type;          /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_PCIE_PHY_PCI_PHY_XCFGD [PCI_PHY_XCFGD] (XCFGD Setting Register n (n = 0 to 26))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t XCFGD;          /*!< (@ 0x00000000) XCFGD Setting Register                                     */
+
+        struct
+        {
+            __IOM uint32_t XCFGD : 32; /*!< [31..0] Sets each bit of the PHY setting pin XCFGD.                       */
+        } XCFGD_b;
+    };
+    __IM uint32_t RESERVED[3];
+} R_PCIE_PHY_PCI_PHY_XCFGD_Type;       /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_PCIE_PHY_PCI_PHY_XCFGA_CMN [PCI_PHY_XCFGA_CMN] (XCFGA_CMN Setting Register n (n = 0 to 15))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t XCFGA_CMN;          /*!< (@ 0x00000000) XCFGA_CMN Setting Register                                 */
+
+        struct
+        {
+            __IOM uint32_t XCFGA_CMN : 32; /*!< [31..0] Sets each bit of the PHY setting pin XCFGA_CMN.                   */
+        } XCFGA_CMN_b;
+    };
+    __IM uint32_t RESERVED[3];
+} R_PCIE_PHY_PCI_PHY_XCFGA_CMN_Type;       /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_PCIE_PHY_PCI_PHY_XCFGA_L0 [PCI_PHY_XCFGA_L0] (XCFGA_LN0 Setting Register n (n = 0 to 5))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t XCFGA_LN0;          /*!< (@ 0x00000000) XCFGA_LN0 Setting Register                                 */
+
+        struct
+        {
+            __IOM uint32_t XCFGA_LN0 : 32; /*!< [31..0] Sets each bit of the PHY setting pin XCFGA_LN0.                   */
+        } XCFGA_LN0_b;
+    };
+    __IM uint32_t RESERVED[3];
+} R_PCIE_PHY_PCI_PHY_XCFGA_L0_Type;        /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_PCIE_PHY_PCI_PHY_XCFGA_L1 [PCI_PHY_XCFGA_L1] (XCFGA_LN1 Setting Register n (n = 0 to 5))
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t XCFGA_LN1;          /*!< (@ 0x00000000) XCFGA_LN1 Setting Register                                 */
+
+        struct
+        {
+            __IOM uint32_t XCFGA_LN1 : 32; /*!< [31..0] Sets each bit of the PHY setting pin XCFGA_LN1.                   */
+        } XCFGA_LN1_b;
+    };
+    __IM uint32_t RESERVED[3];
+} R_PCIE_PHY_PCI_PHY_XCFGA_L1_Type;        /*!< Size = 16 (0x10)                                                          */
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT09_0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief General PWM Timer 09 (R_GPT09_0)
+ */
+
+typedef struct                         /*!< (@ 0x80000000) R_GPT09_0 Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
+
+        struct
+        {
+            __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disabled                                            */
+            __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disabled                                     */
+            __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disabled                                     */
+            __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disabled                                      */
+            __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
+            uint32_t             : 3;
+            __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
+            uint32_t             : 16;
+        } GTWP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTR;          /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
+
+        struct
+        {
+            __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel 0 Count Start                                              */
+            __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel 1 Count Start                                              */
+            __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel 2 Count Start                                              */
+            __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel 3 Count Start                                              */
+            __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel 4 Count Start                                              */
+            __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel 5 Count Start                                              */
+            __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel 6 Count Start                                              */
+            uint32_t              : 25;
+        } GTSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTP;          /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
+
+        struct
+        {
+            __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel 0 Count Stop                                               */
+            __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel 1 Count Stop                                               */
+            __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel 2 Count Stop                                               */
+            __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel 3 Count Stop                                               */
+            __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel 4 Count Stop                                               */
+            __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel 5 Count Stop                                               */
+            __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel 6 Count Stop                                               */
+            uint32_t              : 25;
+        } GTSTP_b;
+    };
+
+    union
+    {
+        __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
+
+        struct
+        {
+            __OM uint32_t CCLR0 : 1;   /*!< [0..0] Channel 0 Count Clear                                              */
+            __OM uint32_t CCLR1 : 1;   /*!< [1..1] Channel 1 Count Clear                                              */
+            __OM uint32_t CCLR2 : 1;   /*!< [2..2] Channel 2 Count Clear                                              */
+            __OM uint32_t CCLR3 : 1;   /*!< [3..3] Channel 3 Count Clear                                              */
+            __OM uint32_t CCLR4 : 1;   /*!< [4..4] Channel 4 Count Clear                                              */
+            __OM uint32_t CCLR5 : 1;   /*!< [5..5] Channel 5 Count Clear                                              */
+            __OM uint32_t CCLR6 : 1;   /*!< [6..6] Channel 6 Count Clear                                              */
+            uint32_t            : 25;
+        } GTCLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSSR;             /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t SSGTRGAFR : 2; /*!< [1..0] SSGTRGAFR                                                          */
+            __IOM uint32_t SSGTRGBFR : 2; /*!< [3..2] SSGTRGBFR                                                          */
+            __IOM uint32_t SSGTRGCFR : 2; /*!< [5..4] SSGTRGCFR                                                          */
+            __IOM uint32_t SSGTRGDFR : 2; /*!< [7..6] SSGTRGDFR                                                          */
+            __IOM uint32_t SSCARBHL  : 2; /*!< [9..8] SSCARBHL                                                           */
+            __IOM uint32_t SSCAFBHL  : 2; /*!< [11..10] SSCAFBHL                                                         */
+            __IOM uint32_t SSCBRAHL  : 2; /*!< [13..12] SSCBRAHL                                                         */
+            __IOM uint32_t SSCBFAHL  : 2; /*!< [15..14] SSCBFAHL                                                         */
+            __IOM uint32_t SSELCA    : 1; /*!< [16..16] SSELCA                                                           */
+            __IOM uint32_t SSELCB    : 1; /*!< [17..17] SSELCB                                                           */
+            __IOM uint32_t SSELCC    : 1; /*!< [18..18] SSELCC                                                           */
+            __IOM uint32_t SSELCD    : 1; /*!< [19..19] SSELCD                                                           */
+            __IOM uint32_t SSELCE    : 1; /*!< [20..20] SSELCE                                                           */
+            __IOM uint32_t SSELCF    : 1; /*!< [21..21] SSELCF                                                           */
+            __IOM uint32_t SSELCG    : 1; /*!< [22..22] SSELCG                                                           */
+            __IOM uint32_t SSELCH    : 1; /*!< [23..23] SSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CSTRT     : 1; /*!< [31..31] Software Source Count Start Enable                               */
+        } GTSSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPSR;             /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
+
+        struct
+        {
+            __IOM uint32_t PSGTRGAFR : 2; /*!< [1..0] PSGTRGAFR                                                          */
+            __IOM uint32_t PSGTRGBFR : 2; /*!< [3..2] PSGTRGBFR                                                          */
+            __IOM uint32_t PSGTRGCFR : 2; /*!< [5..4] PSGTRGCFR                                                          */
+            __IOM uint32_t PSGTRGDFR : 2; /*!< [7..6] PSGTRGDFR                                                          */
+            __IOM uint32_t PSCARBHL  : 2; /*!< [9..8] PSCARBHL                                                           */
+            __IOM uint32_t PSCAFBHL  : 2; /*!< [11..10] PSCAFBHL                                                         */
+            __IOM uint32_t PSCBRAHL  : 2; /*!< [13..12] PSCBRAHL                                                         */
+            __IOM uint32_t PSCBFAHL  : 2; /*!< [15..14] PSCBFAHL                                                         */
+            __IOM uint32_t PSELCA    : 1; /*!< [16..16] PSELCA                                                           */
+            __IOM uint32_t PSELCB    : 1; /*!< [17..17] PSELCB                                                           */
+            __IOM uint32_t PSELCC    : 1; /*!< [18..18] PSELCC                                                           */
+            __IOM uint32_t PSELCD    : 1; /*!< [19..19] PSELCD                                                           */
+            __IOM uint32_t PSELCE    : 1; /*!< [20..20] PSELCE                                                           */
+            __IOM uint32_t PSELCF    : 1; /*!< [21..21] PSELCF                                                           */
+            __IOM uint32_t PSELCG    : 1; /*!< [22..22] PSELCG                                                           */
+            __IOM uint32_t PSELCH    : 1; /*!< [23..23] PSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CSTOP     : 1; /*!< [31..31] CSTOP                                                            */
+        } GTPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCSR;             /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t CSGTRGAFR : 2; /*!< [1..0] CSGTRGAFR                                                          */
+            __IOM uint32_t CSGTRGBFR : 2; /*!< [3..2] CSGTRGBFR                                                          */
+            __IOM uint32_t CSGTRGCFR : 2; /*!< [5..4] CSGTRGCFR                                                          */
+            __IOM uint32_t CSGTRGDFR : 2; /*!< [7..6] CSGTRGDFR                                                          */
+            __IOM uint32_t CSCARBHL  : 2; /*!< [9..8] CSCARBHL                                                           */
+            __IOM uint32_t CSCAFBHL  : 2; /*!< [11..10] CSCAFBHL                                                         */
+            __IOM uint32_t CSCBRAHL  : 2; /*!< [13..12] CSCBRAHL                                                         */
+            __IOM uint32_t CSCBFAHL  : 2; /*!< [15..14] CSCBFAHL                                                         */
+            __IOM uint32_t CSELCA    : 1; /*!< [16..16] CSELCA                                                           */
+            __IOM uint32_t CSELCB    : 1; /*!< [17..17] CSELCB                                                           */
+            __IOM uint32_t CSELCC    : 1; /*!< [18..18] CSELCC                                                           */
+            __IOM uint32_t CSELCD    : 1; /*!< [19..19] CSELCD                                                           */
+            __IOM uint32_t CSELCE    : 1; /*!< [20..20] CSELCE                                                           */
+            __IOM uint32_t CSELCF    : 1; /*!< [21..21] CSELCF                                                           */
+            __IOM uint32_t CSELCG    : 1; /*!< [22..22] CSELCG                                                           */
+            __IOM uint32_t CSELCH    : 1; /*!< [23..23] CSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CCLR      : 1; /*!< [31..31] CCLR                                                             */
+        } GTCSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUPSR;            /*!< (@ 0x0000001C) General PWM Timer Count-Up Source Select Register          */
+
+        struct
+        {
+            __IOM uint32_t USGTRGAFR : 2; /*!< [1..0] USGTRGAFR                                                          */
+            __IOM uint32_t USGTRGBFR : 2; /*!< [3..2] USGTRGBFR                                                          */
+            __IOM uint32_t USGTRGCFR : 2; /*!< [5..4] USGTRGCFR                                                          */
+            __IOM uint32_t USGTRGDFR : 2; /*!< [7..6] USGTRGDFR                                                          */
+            __IOM uint32_t USCARBHL  : 2; /*!< [9..8] USCARBHL                                                           */
+            __IOM uint32_t USCAFBHL  : 2; /*!< [11..10] USCAFBHL                                                         */
+            __IOM uint32_t USCBRAHL  : 2; /*!< [13..12] USCBRAHL                                                         */
+            __IOM uint32_t USCBFAHL  : 2; /*!< [15..14] USCBFAHL                                                         */
+            __IOM uint32_t USELCA    : 1; /*!< [16..16] USELCA                                                           */
+            __IOM uint32_t USELCB    : 1; /*!< [17..17] USELCB                                                           */
+            __IOM uint32_t USELCC    : 1; /*!< [18..18] USELCC                                                           */
+            __IOM uint32_t USELCD    : 1; /*!< [19..19] USELCD                                                           */
+            __IOM uint32_t USELCE    : 1; /*!< [20..20] USELCE                                                           */
+            __IOM uint32_t USELCF    : 1; /*!< [21..21] USELCF                                                           */
+            __IOM uint32_t USELCG    : 1; /*!< [22..22] USELCG                                                           */
+            __IOM uint32_t USELCH    : 1; /*!< [23..23] USELCH                                                           */
+            uint32_t                 : 8;
+        } GTUPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDNSR;            /*!< (@ 0x00000020) General PWM Timer Count-Down Source Select Register        */
+
+        struct
+        {
+            __IOM uint32_t DSGTRGAFR : 2; /*!< [1..0] DSGTRGAFR                                                          */
+            __IOM uint32_t DSGTRGBFR : 2; /*!< [3..2] DSGTRGBFR                                                          */
+            __IOM uint32_t DSGTRGCFR : 2; /*!< [5..4] DSGTRGCFR                                                          */
+            __IOM uint32_t DSGTRGDFR : 2; /*!< [7..6] DSGTRGDFR                                                          */
+            __IOM uint32_t DSCARBHL  : 2; /*!< [9..8] DSCARBHL                                                           */
+            __IOM uint32_t DSCAFBHL  : 2; /*!< [11..10] DSCAFBHL                                                         */
+            __IOM uint32_t DSCBRAHL  : 2; /*!< [13..12] DSCBRAHL                                                         */
+            __IOM uint32_t DSCBFAHL  : 2; /*!< [15..14] DSCBFAHL                                                         */
+            __IOM uint32_t DSELCA    : 1; /*!< [16..16] DSELCA                                                           */
+            __IOM uint32_t DSELCB    : 1; /*!< [17..17] DSELCB                                                           */
+            __IOM uint32_t DSELCC    : 1; /*!< [18..18] DSELCC                                                           */
+            __IOM uint32_t DSELCD    : 1; /*!< [19..19] DSELCD                                                           */
+            __IOM uint32_t DSELCE    : 1; /*!< [20..20] DSELCE                                                           */
+            __IOM uint32_t DSELCF    : 1; /*!< [21..21] DSELCF                                                           */
+            __IOM uint32_t DSELCG    : 1; /*!< [22..22] DSELCG                                                           */
+            __IOM uint32_t DSELCH    : 1; /*!< [23..23] DSELCH                                                           */
+            uint32_t                 : 8;
+        } GTDNSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICASR;           /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
+                                           *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t ASGTRGAFR : 2; /*!< [1..0] ASGTRGAFR                                                          */
+            __IOM uint32_t ASGTRGBFR : 2; /*!< [3..2] ASGTRGBFR                                                          */
+            __IOM uint32_t ASGTRGCFR : 2; /*!< [5..4] ASGTRGCFR                                                          */
+            __IOM uint32_t ASGTRGDFR : 2; /*!< [7..6] ASGTRGDFR                                                          */
+            __IOM uint32_t ASCARBHL  : 2; /*!< [9..8] ASCARBHL                                                           */
+            __IOM uint32_t ASCAFBHL  : 2; /*!< [11..10] ASCAFBHL                                                         */
+            __IOM uint32_t ASCBRAHL  : 2; /*!< [13..12] ASCBRAHL                                                         */
+            __IOM uint32_t ASCBFAHL  : 2; /*!< [15..14] ASCBFAHL                                                         */
+            __IOM uint32_t ASELCA    : 1; /*!< [16..16] ASELCA                                                           */
+            __IOM uint32_t ASELCB    : 1; /*!< [17..17] ASELCB                                                           */
+            __IOM uint32_t ASELCC    : 1; /*!< [18..18] ASELCC                                                           */
+            __IOM uint32_t ASELCD    : 1; /*!< [19..19] ASELCD                                                           */
+            __IOM uint32_t ASELCE    : 1; /*!< [20..20] ASELCE                                                           */
+            __IOM uint32_t ASELCF    : 1; /*!< [21..21] ASELCF                                                           */
+            __IOM uint32_t ASELCG    : 1; /*!< [22..22] ASELCG                                                           */
+            __IOM uint32_t ASELCH    : 1; /*!< [23..23] ASELCH                                                           */
+            uint32_t                 : 8;
+        } GTICASR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICBSR;           /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
+                                           *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t BSGTRGAFR : 2; /*!< [1..0] BSGTRGAFR                                                          */
+            __IOM uint32_t BSGTRGBFR : 2; /*!< [3..2] BSGTRGBFR                                                          */
+            __IOM uint32_t BSGTRGCFR : 2; /*!< [5..4] BSGTRGCFR                                                          */
+            __IOM uint32_t BSGTRGDFR : 2; /*!< [7..6] BSGTRGDFR                                                          */
+            __IOM uint32_t BSCARBHL  : 2; /*!< [9..8] BSCARBHL                                                           */
+            __IOM uint32_t BSCAFBHL  : 2; /*!< [11..10] BSCAFBHL                                                         */
+            __IOM uint32_t BSCBRAHL  : 2; /*!< [13..12] BSCBRAHL                                                         */
+            __IOM uint32_t BSCBFAHL  : 2; /*!< [15..14] BSCBFAHL                                                         */
+            __IOM uint32_t BSELCA    : 1; /*!< [16..16] BSELCA                                                           */
+            __IOM uint32_t BSELCB    : 1; /*!< [17..17] BSELCB                                                           */
+            __IOM uint32_t BSELCC    : 1; /*!< [18..18] BSELCC                                                           */
+            __IOM uint32_t BSELCD    : 1; /*!< [19..19] BSELCD                                                           */
+            __IOM uint32_t BSELCE    : 1; /*!< [20..20] BSELCE                                                           */
+            __IOM uint32_t BSELCF    : 1; /*!< [21..21] BSELCF                                                           */
+            __IOM uint32_t BSELCG    : 1; /*!< [22..22] BSELCG                                                           */
+            __IOM uint32_t BSELCH    : 1; /*!< [23..23] BSELCH                                                           */
+            uint32_t                 : 8;
+        } GTICBSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
+            uint32_t            : 7;
+            __IOM uint32_t ICDS : 1;   /*!< [8..8] Input Capture Operation Select at Count Stop                       */
+            uint32_t            : 7;
+            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
+            uint32_t            : 4;
+            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
+            uint32_t            : 2;
+            __IOM uint32_t SWMD : 3;   /*!< [31..29] Switch Mode Select                                               */
+        } GTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUDDTYC;        /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t UD     : 1;  /*!< [0..0] Count Direction Setting                                            */
+            __IOM uint32_t UDF    : 1;  /*!< [1..1] Forcible Count Direction Setting                                   */
+            uint32_t              : 14;
+            __IOM uint32_t OADTY  : 2;  /*!< [17..16] GTIOCm_nA Pin Output Duty Setting                                */
+            __IOM uint32_t OADTYF : 1;  /*!< [18..18] GTIOCm_nA Pin Output Duty Forced Setting                         */
+            __IOM uint32_t OADTYR : 1;  /*!< [19..19] Output after Release of GTIOCm_nA Pin Output 0%/100%
+                                         *   Duty Cycle Settings                                                       */
+            uint32_t              : 4;
+            __IOM uint32_t OBDTY  : 2;  /*!< [25..24] GTIOCm_nB Pin Output Duty Setting                                */
+            __IOM uint32_t OBDTYF : 1;  /*!< [26..26] GTIOCm_nB Pin Output Duty Forced Setting                         */
+            __IOM uint32_t OBDTYR : 1;  /*!< [27..27] Output after Release of GTIOCm_nB Pin Output 0%/100%
+                                         *   Duty Cycle Settings                                                       */
+            __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTUDDTYC.OADTY[1:0] and GTUDDTYC.OBDTY[1:0] reflect
+                                         *   timing setting in the triangle-wave mode                                  */
+            uint32_t : 3;
+        } GTUDDTYC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCm_nA Pin Function Select                                      */
+            uint32_t              : 1;
+            __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCm_nA Pin Output Value Setting at the Count Stop               */
+            __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCm_nA Pin Output Retention at the Start/Stop Count             */
+            __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCm_nA Pin Output Enable                                        */
+            __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCm_nA Pin Negate Value Setting                                */
+            uint32_t              : 2;
+            __IOM uint32_t NFAEN  : 1; /*!< [13..13] GTIOCm_nA Pin Input Noise Filter Enable                          */
+            __IOM uint32_t NFCSA  : 2; /*!< [15..14] GTIOCm_nA Pin Input Noise Filter Sampling Clock Select           */
+            __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCm_nB Pin Function Select                                    */
+            uint32_t              : 1;
+            __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCm_nB Pin Output Value Setting at the Count Stop             */
+            __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCm_nB Pin Output Retention at the Start/Stop Count           */
+            __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCm_nB Pin Output Enable                                      */
+            __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCm_nB Pin Negate Value Setting                               */
+            uint32_t              : 2;
+            __IOM uint32_t NFBEN  : 1; /*!< [29..29] GTIOCm_nB Pin Input Noise Filter Enable                          */
+            __IOM uint32_t NFCSB  : 2; /*!< [31..30] GTIOCm_nB Pin Input Noise Filter Sampling Clock Select           */
+        } GTIOR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTINTAD;          /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
+
+        struct
+        {
+            __IOM uint32_t GTINTA   : 1; /*!< [0..0] GTINTA                                                             */
+            __IOM uint32_t GTINTB   : 1; /*!< [1..1] GTINTB                                                             */
+            __IOM uint32_t GTINTC   : 1; /*!< [2..2] GTINTC                                                             */
+            __IOM uint32_t GTINTD   : 1; /*!< [3..3] GTINTD                                                             */
+            __IOM uint32_t GTINTE   : 1; /*!< [4..4] GTINTE                                                             */
+            __IOM uint32_t GTINTF   : 1; /*!< [5..5] GTINTF                                                             */
+            __IOM uint32_t GTINTPR  : 2; /*!< [7..6] GTINTPR                                                            */
+            uint32_t                : 8;
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] ADTRAUEN                                                         */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] ADTRADEN                                                         */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] ADTRBUEN                                                         */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] ADTRBDEN                                                         */
+            uint32_t                : 4;
+            __IOM uint32_t GRP      : 2; /*!< [25..24] Select the group to detect disabling of output (dead-time
+                                          *   error or simultaneous driving of outputs to the high or
+                                          *   low level) to POEG and to request of disabling of output
+                                          *   from POEG.                                                                */
+            uint32_t              : 2;
+            __IOM uint32_t GRPDTE : 1;   /*!< [28..28] GRPDTE                                                           */
+            __IOM uint32_t GRPABH : 1;   /*!< [29..29] (GTIOCm_nA pin and GTIOCm_nB output)                             */
+            __IOM uint32_t GRPABL : 1;   /*!< [30..30] (GTIOCm_nA pin and GTIOCm_nB output)                             */
+            uint32_t              : 1;
+        } GTINTAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTST;           /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IM uint32_t ITCNT    : 3; /*!< [10..8] GPTm_n_OVF/GPTm_n_UDF Interrupt Skipping Count Counter            */
+            uint32_t               : 4;
+            __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
+            __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Register Compare Match (Up-Counting) A/D Converter
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Register Compare Match (Down-Counting) A/D
+                                         *   Converter Start Request Flag                                              */
+            __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Register Compare Match (Up-Counting) A/D Converter
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Register Compare Match (Down-Counting) A/D
+                                         *   Converter Start Request Flag                                              */
+            uint32_t            : 4;
+            __IM uint32_t ODF   : 1;    /*!< [24..24] Output Stop Request Flag                                         */
+            uint32_t            : 3;
+            __IM uint32_t DTEF  : 1;    /*!< [28..28] Dead Time Error Flag                                             */
+            __IM uint32_t OABHF : 1;    /*!< [29..29] Simultaneous High Output Flag                                    */
+            __IM uint32_t OABLF : 1;    /*!< [30..30] Simultaneous Low Output Flag                                     */
+            uint32_t            : 1;
+        } GTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+
+        struct
+        {
+            __IOM uint32_t BD0     : 1; /*!< [0..0] GTCCRA/GTCCRB Registers Buffer Operation Disable                   */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] GTPR Register Buffer Operation Disable                             */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] GTADTRA/GTADTRB Registers Buffer Operation Disable                 */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] GTDVU/GTDVD Registers Buffer Operation Disable                     */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRA Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRB Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Register Buffer Operation                                 */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Register Buffer Operation                                 */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Register Buffer Operation                                   */
+            __IOM uint32_t CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Registers Forcible Buffer Operation            */
+            uint32_t               : 1;
+            __IOM uint32_t ADTTA   : 2; /*!< [25..24] GTADTRA Register Buffer Transfer Timing Select                   */
+            __IOM uint32_t ADTDA   : 1; /*!< [26..26] GTADTRA Register Double Buffer Operation                         */
+            uint32_t               : 1;
+            __IOM uint32_t ADTTB   : 2; /*!< [29..28] GTADTRB Register Buffer Transfer Timing Select                   */
+            __IOM uint32_t ADTDB   : 1; /*!< [30..30] GTADTRB Register Double Buffer Operation                         */
+            uint32_t               : 1;
+        } GTBER_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
+                                        *                  Start Request Skipping Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t ITLA  : 1;  /*!< [0..0] ITLA                                                               */
+            __IOM uint32_t ITLB  : 1;  /*!< [1..1] ITLB                                                               */
+            __IOM uint32_t ITLC  : 1;  /*!< [2..2] ITLC                                                               */
+            __IOM uint32_t ITLD  : 1;  /*!< [3..3] ITLD                                                               */
+            __IOM uint32_t ITLE  : 1;  /*!< [4..4] ITLE                                                               */
+            __IOM uint32_t ITLF  : 1;  /*!< [5..5] ITLF                                                               */
+            __IOM uint32_t IVTC  : 2;  /*!< [7..6] IVTC                                                               */
+            __IOM uint32_t IVTT  : 3;  /*!< [10..8] IVTT                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t ADTAL : 1;  /*!< [12..12] ADTAL                                                            */
+            uint32_t             : 1;
+            __IOM uint32_t ADTBL : 1;  /*!< [14..14] ADTBL                                                            */
+            uint32_t             : 17;
+        } GTITC_b;
+    };
+    __IOM uint32_t GTCNT;              /*!< (@ 0x00000048) General PWM Timer Counter                                  */
+    __IOM uint32_t GTCCR[6];           /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register m
+                                        *                  (m = A,B,C,E,D,F)                                          */
+    __IOM uint32_t GTPR;               /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
+    __IOM uint32_t GTPBR;              /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
+    __IOM uint32_t GTPDBR;             /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
+                                        *                  Register                                                   */
+    __IOM uint32_t GTADTRA;            /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A
+                                        *                  (m = A, B)                                                 */
+    __IOM uint32_t GTADTBRA;           /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
+                                        *                  A (m = A, B)                                               */
+    __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
+                                        *                  Register A                                                 */
+    __IOM uint32_t GTADTRB;            /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B
+                                        *                  (m = A, B)                                                 */
+    __IOM uint32_t GTADTBRB;           /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
+                                        *                  B (m = A, B)                                               */
+    __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
+                                        *                  Register B                                                 */
+
+    union
+    {
+        __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
+
+        struct
+        {
+            __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
+            uint32_t             : 3;
+            __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Register Buffer Operation Enable                             */
+            __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Register Buffer Operation Enable                             */
+            uint32_t             : 2;
+            __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Register Setting                                             */
+            uint32_t             : 23;
+        } GTDTCR_b;
+    };
+    __IOM uint32_t GTDVU;              /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U
+                                        *                  (m = U, D)                                                 */
+    __IOM uint32_t GTDVD;              /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D
+                                        *                  (m = U, D)                                                 */
+    __IOM uint32_t GTDBU;              /*!< (@ 0x00000094) General PWM Timer Dead Time Value Buffer Register
+                                        *                  U (m = U, D)                                               */
+    __IOM uint32_t GTDBD;              /*!< (@ 0x00000098) General PWM Timer Dead Time Value Buffer Register
+                                        *                  D (m = U, D)                                               */
+
+    union
+    {
+        __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
+                                        *                  Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
+            uint32_t          : 30;
+        } GTSOS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
+                                        *                  Temporary Release Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
+            uint32_t            : 31;
+        } GTSOTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   Select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA A/D Converter Start Request Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB A/D Converter Start Request Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
+    __IM uint32_t RESERVED[6];
+
+    union
+    {
+        __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
+                                         *                  Control Channel Select Register                            */
+
+        struct
+        {
+            __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            uint32_t : 25;
+        } GTSECSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
+            __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
+            __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
+            __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 20;
+        } GTSECR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSWSR;          /*!< (@ 0x000000D8) General PWM Timer Switch Source Select Register            */
+
+        struct
+        {
+            __IOM uint32_t WSGTRGA : 2; /*!< [1..0] GTETRGA Signal Edge Select to Switch Counter (GTETRGSA
+                                         *   Signal for SAFTY)                                                         */
+            __IOM uint32_t WSGTRGB : 2; /*!< [3..2] GTETRGB Signal Edge Select to Switch Counter (GTETRGSB
+                                         *   Signal for SAFTY)                                                         */
+            __IOM uint32_t WSGTRGC : 2; /*!< [5..4] GTETRGC Signal Edge Select to Switch Counter (GTIOC10_0A
+                                         *   output Signal for SAFTY)                                                  */
+            __IOM uint32_t WSGTRGD : 2; /*!< [7..6] GTETRGD Signal Edge Select to Switch Counter (GTIOC10_1A
+                                         *   output Signal for SAFTY)                                                  */
+            uint32_t              : 8;
+            __IOM uint32_t WSELCA : 1;  /*!< [16..16] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCB : 1;  /*!< [17..17] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCC : 1;  /*!< [18..18] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCD : 1;  /*!< [19..19] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCE : 1;  /*!< [20..20] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCF : 1;  /*!< [21..21] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCG : 1;  /*!< [22..22] Event Source Counter Switch Enable                               */
+            __IOM uint32_t CSELCH : 1;  /*!< [23..23] Event Source Counter Switch Enable                               */
+            uint32_t              : 8;
+        } GTSWSR_b;
+    };
+    __IOM uint32_t GTSWOS;              /*!< (@ 0x000000DC) General PWM Timer Switch Offset Setting Register           */
+} R_GPT00_0_Type;                       /*!< Size = 224 (0xe0)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CRC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CRC Unit 0 (R_CRC0)
+ */
+
+typedef struct                         /*!< (@ 0x80004000) R_CRC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register 0                                     */
+
+        struct
+        {
+            __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
+            uint8_t              : 3;
+            __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
+            __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
+        } CRCCR0_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t CRCDIR;         /*!< (@ 0x00000004) CRC Data Input Register                                    */
+        __IOM uint8_t  CRCDIR_BY;      /*!< (@ 0x00000004) CRC Data Input Register                                    */
+    };
+
+    union
+    {
+        __IOM uint32_t CRCDOR;         /*!< (@ 0x00000008) CRC Data Output Register                                   */
+        __IOM uint16_t CRCDOR_HA;      /*!< (@ 0x00000008) CRC Data Output Register                                   */
+        __IOM uint8_t  CRCDOR_BY;      /*!< (@ 0x00000008) CRC Data Output Register                                   */
+    };
+} R_CRC0_Type;                         /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Communication Interface 0 (R_SCI0)
+ */
+
+typedef struct                         /*!< (@ 0x80005000) R_SCI0 Structure                                           */
+{
+    union
+    {
+        __IM uint32_t RDR;             /*!< (@ 0x00000000) Receive Data Register                                      */
+
+        struct
+        {
+            __IM uint32_t RDAT : 9;    /*!< [8..0] Serial receive data                                                */
+            __IM uint32_t MPB  : 1;    /*!< [9..9] Multi-processor flag                                               */
+            __IM uint32_t DR   : 1;    /*!< [10..10] Receive data ready flag                                          */
+            __IM uint32_t FPER : 1;    /*!< [11..11] FIFO parity error flag                                           */
+            __IM uint32_t FFER : 1;    /*!< [12..12] FIFO framing error flag                                          */
+            uint32_t           : 11;
+            __IM uint32_t ORER : 1;    /*!< [24..24] Overrun Error flag                                               */
+            uint32_t           : 2;
+            __IM uint32_t PER  : 1;    /*!< [27..27] Parity error flag                                                */
+            __IM uint32_t FER  : 1;    /*!< [28..28] Framing error flag                                               */
+            uint32_t           : 3;
+        } RDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDR;            /*!< (@ 0x00000004) Transmit Data Register                                     */
+
+        struct
+        {
+            __IOM uint32_t TDAT  : 9;  /*!< [8..0] Serial transmit data                                               */
+            __IOM uint32_t MPBT  : 1;  /*!< [9..9] Multi-processor transfer bit flag                                  */
+            uint32_t             : 2;
+            __IOM uint32_t TSYNC : 1;  /*!< [12..12] Transmit SYNC Data Bit                                           */
+            uint32_t             : 19;
+        } TDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR0;           /*!< (@ 0x00000008) Common Control Register 0                                  */
+
+        struct
+        {
+            __IOM uint32_t RE    : 1;  /*!< [0..0] Receive Enable                                                     */
+            uint32_t             : 3;
+            __IOM uint32_t TE    : 1;  /*!< [4..4] Transmit Enable                                                    */
+            uint32_t             : 3;
+            __IOM uint32_t MPIE  : 1;  /*!< [8..8] Multi-Processor Interrupt Enable                                   */
+            __IOM uint32_t DCME  : 1;  /*!< [9..9] Data Compare Match Enable                                          */
+            __IOM uint32_t IDSEL : 1;  /*!< [10..10] ID frame select                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t RIE   : 1;  /*!< [16..16] Receive Interrupt Enable                                         */
+            uint32_t             : 3;
+            __IOM uint32_t TIE   : 1;  /*!< [20..20] Transmit Interrupt Enable                                        */
+            __IOM uint32_t TEIE  : 1;  /*!< [21..21] Transmit End Interrupt Enable                                    */
+            uint32_t             : 2;
+            __IOM uint32_t SSE   : 1;  /*!< [24..24] SSn# Pin Function Enable                                         */
+            uint32_t             : 7;
+        } CCR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR1;           /*!< (@ 0x0000000C) Common Control Register 1                                  */
+
+        struct
+        {
+            __IOM uint32_t CTSE   : 1; /*!< [0..0] CTS Enable                                                         */
+            __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable                                            */
+            uint32_t              : 2;
+            __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select                                      */
+            __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O                                              */
+            uint32_t              : 2;
+            __IOM uint32_t PE     : 1; /*!< [8..8] Parity Enable                                                      */
+            __IOM uint32_t PM     : 1; /*!< [9..9] Parity Mode                                                        */
+            uint32_t              : 2;
+            __IOM uint32_t TINV   : 1; /*!< [12..12] TXD invert                                                       */
+            __IOM uint32_t RINV   : 1; /*!< [13..13] RXD invert                                                       */
+            uint32_t              : 2;
+            __IOM uint32_t SPLP   : 1; /*!< [16..16] Loopback Control                                                 */
+            uint32_t              : 3;
+            __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select                                 */
+            uint32_t              : 3;
+            __IOM uint32_t NFCS   : 3; /*!< [26..24] Noise Filter Clock Select                                        */
+            uint32_t              : 1;
+            __IOM uint32_t NFEN   : 1; /*!< [28..28] Digital Noise Filter Function Enable                             */
+            uint32_t              : 3;
+        } CCR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR2;           /*!< (@ 0x00000010) Common Control Register 2                                  */
+
+        struct
+        {
+            __IOM uint32_t BCP   : 3;  /*!< [2..0] Base Clock Pulse                                                   */
+            uint32_t             : 1;
+            __IOM uint32_t BGDM  : 1;  /*!< [4..4] Baud Rate Generator Double-Speed Mode Select                       */
+            __IOM uint32_t ABCS  : 1;  /*!< [5..5] Asynchronous Mode Base Clock Select                                */
+            __IOM uint32_t ABCSE : 1;  /*!< [6..6] Asynchronous Mode Extended Base Clock Select                       */
+            uint32_t             : 1;
+            __IOM uint32_t BRR   : 8;  /*!< [15..8] Bit rate setting                                                  */
+            __IOM uint32_t BRME  : 1;  /*!< [16..16] BRME                                                             */
+            uint32_t             : 3;
+            __IOM uint32_t CKS   : 2;  /*!< [21..20] Clock Select                                                     */
+            uint32_t             : 2;
+            __IOM uint32_t MDDR  : 8;  /*!< [31..24] Modulation Duty setting                                          */
+        } CCR2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR3;            /*!< (@ 0x00000014) Common Control Register 3                                  */
+
+        struct
+        {
+            __IOM uint32_t CPHA    : 1; /*!< [0..0] Clock Phase Select                                                 */
+            __IOM uint32_t CPOL    : 1; /*!< [1..1] Clock Polarity Select                                              */
+            uint32_t               : 5;
+            __IOM uint32_t BPEN    : 1; /*!< [7..7] Synchronizer bypass enable                                         */
+            __IOM uint32_t CHR     : 2; /*!< [9..8] Character Length                                                   */
+            uint32_t               : 2;
+            __IOM uint32_t LSBF    : 1; /*!< [12..12] LSB First select                                                 */
+            __IOM uint32_t SINV    : 1; /*!< [13..13] Transmitted/Received Data Invert                                 */
+            __IOM uint32_t STP     : 1; /*!< [14..14] Stop Bit Length                                                  */
+            __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select                     */
+            __IOM uint32_t MOD     : 3; /*!< [18..16] Communication mode select                                        */
+            __IOM uint32_t MP      : 1; /*!< [19..19] Multi-Processor Mode                                             */
+            __IOM uint32_t FM      : 1; /*!< [20..20] FIFO Mode select                                                 */
+            __IOM uint32_t DEN     : 1; /*!< [21..21] Driver enable                                                    */
+            uint32_t               : 2;
+            __IOM uint32_t CKE     : 2; /*!< [25..24] Clock enable                                                     */
+            uint32_t               : 2;
+            __IOM uint32_t GM      : 1; /*!< [28..28] GSM Mode                                                         */
+            __IOM uint32_t BLK     : 1; /*!< [29..29] Block Transfer Mode                                              */
+            uint32_t               : 2;
+        } CCR3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCR4;           /*!< (@ 0x00000018) Common Control Register 4                                  */
+
+        struct
+        {
+            __IOM uint32_t CMPD : 9;   /*!< [8..0] Compare Match Data                                                 */
+            uint32_t            : 7;
+            __IOM uint32_t ASEN : 1;   /*!< [16..16] Adjust receive sampling timing enable                            */
+            __IOM uint32_t ATEN : 1;   /*!< [17..17] Adjust transmit timing enable                                    */
+            uint32_t            : 6;
+            __IOM uint32_t AST  : 3;   /*!< [26..24] Adjustment value for receive Sampling Timing                     */
+            __IOM uint32_t AJD  : 1;   /*!< [27..27] Adjustment Direction for receive sampling timing                 */
+            __IOM uint32_t ATT  : 3;   /*!< [30..28] Adjustment value for Transmit timing                             */
+            __IOM uint32_t AET  : 1;   /*!< [31..31] Adjustment edge for transmit timing                              */
+        } CCR4_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t ICR;                /*!< (@ 0x00000020) Simple I2C Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t IICDL      : 5; /*!< [4..0] SDA Delay Output Select                                            */
+            uint32_t                  : 3;
+            __IOM uint32_t IICINTM    : 1; /*!< [8..8] IICINTM                                                            */
+            __IOM uint32_t IICCSC     : 1; /*!< [9..9] IICCSC                                                             */
+            uint32_t                  : 3;
+            __IOM uint32_t IICACKT    : 1; /*!< [13..13] IICACKT                                                          */
+            uint32_t                  : 2;
+            __IOM uint32_t IICSTAREQ  : 1; /*!< [16..16] IICSTAREQ                                                        */
+            __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] IICRSTAREQ                                                       */
+            __IOM uint32_t IICSTPREQ  : 1; /*!< [18..18] IICSTPREQ                                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t IICSDAS    : 2; /*!< [21..20] IICSDAS                                                          */
+            __IOM uint32_t IICSCLS    : 2; /*!< [23..22] IICSCLS                                                          */
+            uint32_t                  : 8;
+        } ICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FCR;            /*!< (@ 0x00000024) FIFO Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t DRES  : 1;  /*!< [0..0] Receive data ready error select                                    */
+            uint32_t             : 7;
+            __IOM uint32_t TTRG  : 5;  /*!< [12..8] Transmit FIFO data trigger number                                 */
+            uint32_t             : 2;
+            __OM uint32_t  TFRST : 1;  /*!< [15..15] Transmit FIFO Data Register Reset                                */
+            __IOM uint32_t RTRG  : 5;  /*!< [20..16] Receive FIFO data trigger number                                 */
+            uint32_t             : 2;
+            __OM uint32_t  RFRST : 1;  /*!< [23..23] Receive FIFO Data Register Reset                                 */
+            __IOM uint32_t RSTRG : 5;  /*!< [28..24] RTS# Output Active Trigger Number Select                         */
+            uint32_t             : 3;
+        } FCR_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t MCR;            /*!< (@ 0x0000002C) Manchester Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t RMPOL  : 1; /*!< [0..0] Polarity of Received Manchester Code                               */
+            __IOM uint32_t TMPOL  : 1; /*!< [1..1] Polarity of Transmit Manchester Code                               */
+            __IOM uint32_t ERTEN  : 1; /*!< [2..2] Manchester Edge Retiming Enable                                    */
+            uint32_t              : 1;
+            __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting                                                 */
+            __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNSEL                                                             */
+            __IOM uint32_t SBSEL  : 1; /*!< [6..6] SBSEL                                                              */
+            uint32_t              : 1;
+            __IOM uint32_t TPLEN  : 4; /*!< [11..8] Transmit preface length                                           */
+            __IOM uint32_t TPPAT  : 2; /*!< [13..12] Transmit preface pattern                                         */
+            uint32_t              : 2;
+            __IOM uint32_t RPLEN  : 4; /*!< [19..16] Receive Preface Length                                           */
+            __IOM uint32_t RPPAT  : 2; /*!< [21..20] Receive Preface Pattern                                          */
+            uint32_t              : 2;
+            __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable                                             */
+            __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable                                        */
+            __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable                                           */
+            uint32_t              : 5;
+        } MCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DCR;            /*!< (@ 0x00000030) Driver Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t DEPOL : 1;  /*!< [0..0] Driver effective polarity select                                   */
+            uint32_t             : 7;
+            __IOM uint32_t DEAST : 5;  /*!< [12..8] Driver Assertion Time                                             */
+            uint32_t             : 3;
+            __IOM uint32_t DENGT : 5;  /*!< [20..16] Driver negate time                                               */
+            uint32_t             : 11;
+        } DCR_b;
+    };
+    __IM uint32_t RESERVED2[5];
+
+    union
+    {
+        __IM uint32_t CSR;             /*!< (@ 0x00000048) Common Status Register                                     */
+
+        struct
+        {
+            uint32_t             : 4;
+            __IM uint32_t ERS    : 1;  /*!< [4..4] Error Signal Status Flag                                           */
+            uint32_t             : 10;
+            __IM uint32_t RXDMON : 1;  /*!< [15..15] Serial input data monitor                                        */
+            __IM uint32_t DCMF   : 1;  /*!< [16..16] Data Compare Match Flag                                          */
+            __IM uint32_t DPER   : 1;  /*!< [17..17] Data Compare Match Parity Error Flag                             */
+            __IM uint32_t DFER   : 1;  /*!< [18..18] Data Compare Match Framing Error Flag                            */
+            uint32_t             : 5;
+            __IM uint32_t ORER   : 1;  /*!< [24..24] ORER                                                             */
+            uint32_t             : 1;
+            __IM uint32_t MFF    : 1;  /*!< [26..26] Mode Fault Error Flag                                            */
+            __IM uint32_t PER    : 1;  /*!< [27..27] PER                                                              */
+            __IM uint32_t FER    : 1;  /*!< [28..28] FER                                                              */
+            __IM uint32_t TDRE   : 1;  /*!< [29..29] Transmit Data Empty Flag                                         */
+            __IM uint32_t TEND   : 1;  /*!< [30..30] TEND                                                             */
+            __IM uint32_t RDRF   : 1;  /*!< [31..31] RDRF                                                             */
+        } CSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ISR;             /*!< (@ 0x0000004C) Simple I2C Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag                                            */
+            uint32_t              : 2;
+            __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
+                                        *   Flag                                                                      */
+            uint32_t : 28;
+        } ISR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRSR;            /*!< (@ 0x00000050) FIFO Receive Status Register                               */
+
+        struct
+        {
+            __IM uint32_t DR   : 1;    /*!< [0..0] DR                                                                 */
+            uint32_t           : 7;
+            __IM uint32_t R    : 6;    /*!< [13..8] Receive FIFO Data Count                                           */
+            uint32_t           : 2;
+            __IM uint32_t PNUM : 6;    /*!< [21..16] Parity Error Count                                               */
+            uint32_t           : 2;
+            __IM uint32_t FNUM : 6;    /*!< [29..24] Framing Error Count                                              */
+            uint32_t           : 2;
+        } FRSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FTSR;            /*!< (@ 0x00000054) FIFO Transmit Status Register                              */
+
+        struct
+        {
+            __IM uint32_t T : 6;       /*!< [5..0] Transmit FIFO Data Count                                           */
+            uint32_t        : 26;
+        } FTSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t MSR;             /*!< (@ 0x00000058) Manchester Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t PFER  : 1;   /*!< [0..0] Preface Error flag                                                 */
+            __IM uint32_t SYER  : 1;   /*!< [1..1] SYNC Error flag                                                    */
+            __IM uint32_t SBER  : 1;   /*!< [2..2] Start Bit Error flag                                               */
+            uint32_t            : 1;
+            __IM uint32_t MER   : 1;   /*!< [4..4] Manchester Error Flag                                              */
+            uint32_t            : 1;
+            __IM uint32_t RSYNC : 1;   /*!< [6..6] Receive SYNC data bit                                              */
+            uint32_t            : 25;
+        } MSR_b;
+    };
+    __IM uint32_t RESERVED3[3];
+
+    union
+    {
+        __OM uint32_t CFCLR;           /*!< (@ 0x00000068) Common Flag Clear Register                                 */
+
+        struct
+        {
+            uint32_t            : 4;
+            __OM uint32_t ERSC  : 1;   /*!< [4..4] ERSC                                                               */
+            uint32_t            : 11;
+            __OM uint32_t DCMFC : 1;   /*!< [16..16] DCMFC                                                            */
+            __OM uint32_t DPERC : 1;   /*!< [17..17] DPERC                                                            */
+            __OM uint32_t DFERC : 1;   /*!< [18..18] DFERC                                                            */
+            uint32_t            : 5;
+            __OM uint32_t ORERC : 1;   /*!< [24..24] ORERC                                                            */
+            uint32_t            : 1;
+            __OM uint32_t MFFC  : 1;   /*!< [26..26] MFFC                                                             */
+            __OM uint32_t PERC  : 1;   /*!< [27..27] PERC                                                             */
+            __OM uint32_t FERC  : 1;   /*!< [28..28] FERC                                                             */
+            __OM uint32_t TDREC : 1;   /*!< [29..29] TDREC                                                            */
+            uint32_t            : 1;
+            __OM uint32_t RDRFC : 1;   /*!< [31..31] RDRFC                                                            */
+        } CFCLR_b;
+    };
+
+    union
+    {
+        __OM uint32_t ICFCLR;          /*!< (@ 0x0000006C) Simple I2C Flag Clear Register                             */
+
+        struct
+        {
+            uint32_t               : 3;
+            __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIFC                                                           */
+            uint32_t               : 28;
+        } ICFCLR_b;
+    };
+
+    union
+    {
+        __OM uint32_t FFCLR;           /*!< (@ 0x00000070) FIFO Flag Clear Register                                   */
+
+        struct
+        {
+            __OM uint32_t DRC : 1;     /*!< [0..0] DRC                                                                */
+            uint32_t          : 31;
+        } FFCLR_b;
+    };
+
+    union
+    {
+        __OM uint32_t MFCLR;           /*!< (@ 0x00000074) Manchester Flag Clear Register                             */
+
+        struct
+        {
+            __OM uint32_t PFERC : 1;   /*!< [0..0] PFER clear bit                                                     */
+            __OM uint32_t SYERC : 1;   /*!< [1..1] SYER clear bit                                                     */
+            __OM uint32_t SBERC : 1;   /*!< [2..2] SBER clear bit                                                     */
+            uint32_t            : 1;
+            __OM uint32_t MERC  : 1;   /*!< [4..4] MER clear bit                                                      */
+            uint32_t            : 27;
+        } MFCLR_b;
+    };
+} R_SCI0_Type;                         /*!< Size = 120 (0x78)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Peripheral Interface 0 (R_SPI0)
+ */
+
+typedef struct                         /*!< (@ 0x80007000) R_SPI0 Structure                                           */
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t SPDR;         /*!< (@ 0x00000000) SPI Data Register                                          */
+
+            struct
+            {
+                __IOM uint32_t SPD : 32; /*!< [31..0] The SPI data register (SPDR) is used to store SPI's
+                                          *   transmit data and receive data. Transmit buffers and receive
+                                          *   buffers independently function.                                           */
+            } SPDR_b;
+        };
+        __IOM uint16_t SPDR_HA;          /*!< (@ 0x00000000) SPI Data Register                                          */
+        __IOM uint8_t  SPDR_BY;          /*!< (@ 0x00000000) SPI Data Register                                          */
+    };
+
+    union
+    {
+        __IOM uint8_t SPCKD;           /*!< (@ 0x00000004) SPI Clock Delay Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
+            uint8_t             : 5;
+        } SPCKD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLND;           /*!< (@ 0x00000005) SPI Slave Select Negation Delay Register                   */
+
+        struct
+        {
+            __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Bits                                            */
+            uint8_t             : 5;
+        } SSLND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPND;            /*!< (@ 0x00000006) SPI Next-Access Delay Register                             */
+
+        struct
+        {
+            __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Bits                                         */
+            uint8_t             : 5;
+        } SPND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MRCKD;           /*!< (@ 0x00000007) SPI ClocK Digital control Register for Master
+                                        *                  Receive                                                    */
+
+        struct
+        {
+            __IOM uint8_t ARST : 3;    /*!< [2..0] Receive Sampling Timing Adjustment Bits                            */
+            uint8_t            : 5;
+        } MRCKD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SPCR;             /*!< (@ 0x00000008) SPI Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t SPE      : 1; /*!< [0..0] SPI Function Enable                                                */
+            uint32_t                : 6;
+            __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] SPI Master Receive Clock Select                                    */
+            __IOM uint32_t SPPE     : 1; /*!< [8..8] Parity Enable                                                      */
+            __IOM uint32_t SPOE     : 1; /*!< [9..9] Parity Mode                                                        */
+            uint32_t                : 1;
+            __IOM uint32_t PTE      : 1; /*!< [11..11] Parity Self-Diagnosis Enable                                     */
+            __IOM uint32_t SCKASE   : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable                                  */
+            __IOM uint32_t BFDS     : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select                       */
+            __IOM uint32_t MODFEN   : 1; /*!< [14..14] Mode Fault Error Detection Enable                                */
+            uint32_t                : 1;
+            __IOM uint32_t SPEIE    : 1; /*!< [16..16] SPI Error Interrupt Enable                                       */
+            __IOM uint32_t SPRIE    : 1; /*!< [17..17] SPI Receive Buffer Full Interrupt Enable                         */
+            __IOM uint32_t SPIIE    : 1; /*!< [18..18] SPI Idle Interrupt Enable                                        */
+            __IOM uint32_t SPDRES   : 1; /*!< [19..19] SPI Receive Data Ready Error Select                              */
+            __IOM uint32_t SPTIE    : 1; /*!< [20..20] SPI Transmit Buffer Empty Interrupt Enable                       */
+            __IOM uint32_t CENDIE   : 1; /*!< [21..21] SPI Communication End Interrupt Enable                           */
+            uint32_t                : 2;
+            __IOM uint32_t SPMS     : 1; /*!< [24..24] SPI Function Enable                                              */
+            __IOM uint32_t SPFRF    : 1; /*!< [25..25] SPI Frame Format Select                                          */
+            uint32_t                : 2;
+            __IOM uint32_t TXMD     : 2; /*!< [29..28] Communication Mode Select                                        */
+            __IOM uint32_t MSTR     : 1; /*!< [30..30] SPI Master/Slave Mode Select                                     */
+            __IOM uint32_t BPEN     : 1; /*!< [31..31] Synchronization Circuit Bypass Enable                            */
+        } SPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCRRM;          /*!< (@ 0x0000000C) SPI Control Register for Master Receive only               */
+
+        struct
+        {
+            __IOM uint8_t RMFM  : 5;   /*!< [4..0] Frame processing count setting in Master Receive only              */
+            uint8_t             : 1;
+            __OM uint8_t RMEDTG : 1;   /*!< [6..6] Reading value is always 0.                                         */
+            __OM uint8_t RMSTTG : 1;   /*!< [7..7] Reading value is always 0.                                         */
+        } SPCRRM_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPDRCR;          /*!< (@ 0x0000000D) SPI Control Register for Received Data Ready
+                                        *                  Detection                                                  */
+
+        struct
+        {
+            __IOM uint8_t SPDRC : 8;   /*!< [7..0] SPDRC                                                              */
+        } SPDRCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPPCR;           /*!< (@ 0x0000000E) SPI Pin Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
+            __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
+            __IOM uint8_t SPOM  : 1;   /*!< [2..2] SPI Output Pin Mode                                                */
+            uint8_t             : 1;
+            __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
+            __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
+            uint8_t             : 2;
+        } SPPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t SPSCKDL : 3; /*!< [2..0] SPI Master Receive Clock Analog Delay                              */
+            uint8_t               : 5;
+        } SPCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLP;            /*!< (@ 0x00000010) SPI Slave Select Polarity Register                         */
+
+        struct
+        {
+            __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
+            uint8_t             : 4;
+        } SSLP_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPBR;            /*!< (@ 0x00000011) SPI Bit Rate Register                                      */
+
+        struct
+        {
+            __IOM uint8_t SPR : 8;     /*!< [7..0] The SPBR register is used to set the bit rate in master
+                                        *   mode. If SPBR is modified while SPCR.MSTR = 1 and SPCR.SPE
+                                        *   = 1, subsequent operation is not guaranteed.                              */
+        } SPBR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t SPSCR;           /*!< (@ 0x00000013) SPI Sequence Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t SPSLN : 3;   /*!< [2..0] SPI Sequence Length Specification                                  */
+            uint8_t             : 5;
+        } SPSCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SPCMD[8];       /*!< (@ 0x00000014) SPI Command Register [0..7] (m = 0 to 7)                   */
+
+        struct
+        {
+            __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
+            __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
+            __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
+            uint32_t              : 3;
+            __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
+            uint32_t              : 4;
+            __IOM uint32_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
+            __IOM uint32_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
+            __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
+            __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
+            __IOM uint32_t SPB    : 5; /*!< [20..16] SPI Data Length                                                  */
+            uint32_t              : 3;
+            __IOM uint32_t SSLA   : 2; /*!< [25..24] SSL Signal Assertion                                             */
+            uint32_t              : 6;
+        } SPCMD_b[8];
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint16_t SPDCR;          /*!< (@ 0x00000040) SPI Data Control Register                                  */
+
+        struct
+        {
+            __IOM uint16_t BYSW   : 1; /*!< [0..0] Byte Swap Operating Mode Select                                    */
+            __IOM uint16_t SLSEL  : 2; /*!< [2..1] SSL Pin Output Select                                              */
+            __IOM uint16_t SPRDTD : 1; /*!< [3..3] SPI Receive Data or Transmit Data Selection                        */
+            __IOM uint16_t SINV   : 1; /*!< [4..4] Serial data invert                                                 */
+            uint16_t              : 3;
+            __IOM uint16_t SPFC   : 2; /*!< [9..8] Frame Count                                                        */
+            uint16_t              : 6;
+        } SPDCR_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint16_t SPDCR2;         /*!< (@ 0x00000044) SPI Data Control Register 2                                */
+
+        struct
+        {
+            __IOM uint16_t RTRG : 2;   /*!< [1..0] Receive FIFO threshold setting                                     */
+            uint16_t            : 6;
+            __IOM uint16_t TTRG : 2;   /*!< [9..8] Transmission FIFO threshold setting                                */
+            uint16_t            : 6;
+        } SPDCR2_b;
+    };
+    __IM uint16_t RESERVED3;
+    __IM uint32_t RESERVED4[2];
+    __IM uint8_t  RESERVED5;
+
+    union
+    {
+        __IM uint8_t SPSSR;            /*!< (@ 0x00000051) SPI Sequence Status Register                               */
+
+        struct
+        {
+            __IM uint8_t SPCP  : 3;    /*!< [2..0] SPI Command Pointer                                                */
+            uint8_t            : 1;
+            __IM uint8_t SPECM : 3;    /*!< [6..4] SPI Error Command                                                  */
+            uint8_t            : 1;
+        } SPSSR_b;
+    };
+
+    union
+    {
+        __IM uint16_t SPSR;            /*!< (@ 0x00000052) SPI Status Register                                        */
+
+        struct
+        {
+            uint16_t            : 7;
+            __IM uint16_t SPDRF : 1;   /*!< [7..7] SPI Receive Data Ready Flag                                        */
+            __IM uint16_t OVRF  : 1;   /*!< [8..8] Overrun Error Flag                                                 */
+            __IM uint16_t IDLNF : 1;   /*!< [9..9] SPI Idle Flag                                                      */
+            __IM uint16_t MODF  : 1;   /*!< [10..10] Mode Fault Error Flag                                            */
+            __IM uint16_t PERF  : 1;   /*!< [11..11] Parity Error Flag                                                */
+            __IM uint16_t UDRF  : 1;   /*!< [12..12] Underrun Error Flag                                              */
+            __IM uint16_t SPTEF : 1;   /*!< [13..13] SPI Transmit Buffer Empty Flag                                   */
+            __IM uint16_t CENDF : 1;   /*!< [14..14] Communication End Flag                                           */
+            __IM uint16_t SPRF  : 1;   /*!< [15..15] SPI Receive Buffer Full Flag                                     */
+        } SPSR_b;
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IM uint8_t SPTFSR;           /*!< (@ 0x00000058) SPI Transfer FIFO Status Register                          */
+
+        struct
+        {
+            __IM uint8_t TFDN : 3;     /*!< [2..0] Transmit FIFO data empty stage number                              */
+            uint8_t           : 5;
+        } SPTFSR_b;
+    };
+    __IM uint8_t  RESERVED7;
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IM uint8_t SPRFSR;           /*!< (@ 0x0000005C) SPI Receive FIFO Status Register                           */
+
+        struct
+        {
+            __IM uint8_t RFDN : 3;     /*!< [2..0] Receive FIFO data store stage number                               */
+            uint8_t           : 5;
+        } SPRFSR_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IM uint32_t SPPSR;           /*!< (@ 0x00000060) SPI Poling Register                                        */
+
+        struct
+        {
+            __IM uint32_t SPEPS : 1;   /*!< [0..0] SPI Polling Status                                                 */
+            uint32_t            : 31;
+        } SPPSR_b;
+    };
+    __IM uint32_t RESERVED11;
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t SPSRC;          /*!< (@ 0x0000006A) SPI Status Clear Register                                  */
+
+        struct
+        {
+            uint16_t             : 7;
+            __OM uint16_t SPDRFC : 1;  /*!< [7..7] SPI Receive Data Ready Flag Clear                                  */
+            __OM uint16_t OVRFC  : 1;  /*!< [8..8] Overrun Error Flag Clear                                           */
+            uint16_t             : 1;
+            __OM uint16_t MODFC  : 1;  /*!< [10..10] Mode Fault Error Flag Clear                                      */
+            __OM uint16_t PERFC  : 1;  /*!< [11..11] Parity Error Flag Clear                                          */
+            __OM uint16_t UDRFC  : 1;  /*!< [12..12] Underrun Error Flag Clear                                        */
+            __OM uint16_t SPTEFC : 1;  /*!< [13..13] SPI Transmit Buffer Empty Flag Clear                             */
+            __OM uint16_t CENDFC : 1;  /*!< [14..14] Communication End Flag Clear                                     */
+            __OM uint16_t SPRFC  : 1;  /*!< [15..15] SPI Receive Buffer Full Flag Clear                               */
+        } SPSRC_b;
+    };
+
+    union
+    {
+        __OM uint8_t SPFCR;            /*!< (@ 0x0000006C) SPI FIFO Clear Register                                    */
+
+        struct
+        {
+            __OM uint8_t SPFRST : 1;   /*!< [0..0] SPI FIFO clear                                                     */
+            uint8_t             : 7;
+        } SPFCR_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+} R_SPI0_Type;                         /*!< Size = 112 (0x70)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ADC122                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief 12-Bit A/D converter 2 (R_ADC122)
+ */
+
+typedef struct                         /*!< (@ 0x80008000) R_ADC122 Structure                                         */
+{
+    union
+    {
+        __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel Select                                      */
+            uint16_t              : 1;
+            __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
+            __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
+            __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
+            __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
+            uint16_t              : 2;
+            __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
+            __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
+            __IOM uint16_t ADST   : 1; /*!< [15..15] A/D conversion Start                                             */
+        } ADCSR_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t ADANSA0;        /*!< (@ 0x00000004) A/D Channel Select Register A0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSA0 : 16; /*!< [15..0] A/D conversion Analog input Channel Select                        */
+        } ADANSA0_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t ADADS0;         /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Function
+                                        *                  Channel Select Register 0                                  */
+
+        struct
+        {
+            __IOM uint16_t ADS0 : 16;  /*!< [15..0] A/D-Converted Value Addition/Average Channel Select               */
+        } ADADS0_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t ADC  : 3;    /*!< [2..0] Addition Count Select                                              */
+            uint8_t            : 4;
+            __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable                                                */
+        } ADADC_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
+
+        struct
+        {
+            uint16_t              : 1;
+            __IOM uint16_t ADPRC  : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
+            uint16_t              : 2;
+            __IOM uint16_t ACE    : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
+            uint16_t              : 9;
+            __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select                                  */
+        } ADCER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
+
+        struct
+        {
+            __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group B                    */
+            uint16_t            : 2;
+            __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger Select                               */
+            uint16_t            : 2;
+        } ADSTRGR_b;
+    };
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint16_t ADANSB0;        /*!< (@ 0x00000014) A/D Channel Select Register B0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSB0 : 16; /*!< [15..0] A/D Conversion Analog Input Channel Select                        */
+        } ADANSB0_b;
+    };
+    __IM uint16_t RESERVED5;
+
+    union
+    {
+        __IM uint16_t ADDBLDR;         /*!< (@ 0x00000018) A/D Data Duplication Register                              */
+
+        struct
+        {
+            __IM uint16_t DBLDR : 16;  /*!< [15..0] The result of A/D conversion in response to the second
+                                        *   trigger in double trigger mode.                                           */
+        } ADDBLDR_b;
+    };
+    __IM uint16_t RESERVED6[3];
+
+    union
+    {
+        __IM uint16_t ADDR[15];        /*!< (@ 0x00000020) A/D Data Register n (n = 0 to 14)                          */
+
+        struct
+        {
+            __IM uint16_t DR : 16;     /*!< [15..0] The result of A/D conversion (n: Number of channel)               */
+        } ADDR_b[15];
+    };
+    __IM uint16_t RESERVED7[20];
+
+    union
+    {
+        __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Control Register                       */
+
+        struct
+        {
+            __IOM uint16_t SSTSH : 8;  /*!< [7..0] Sample and hold period setting                                     */
+            __IOM uint16_t SHANS : 3;  /*!< [10..8] Sample and hold use or bypass select for ch0-2                    */
+            uint16_t             : 5;
+        } ADSHCR_b;
+    };
+    __IM uint16_t RESERVED8[10];
+    __IM uint8_t  RESERVED9;
+
+    union
+    {
+        __IOM uint8_t ADELCCR;         /*!< (@ 0x0000007D) A/D Event Link Control Register                            */
+
+        struct
+        {
+            __IOM uint8_t ELCC  : 2;   /*!< [1..0] Event link control bits                                            */
+            __IOM uint8_t GCELC : 1;   /*!< [2..2] Event control bit for Group C                                      */
+            uint8_t             : 5;
+        } ADELCCR_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t ADGSPCR;        /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
+
+        struct
+        {
+            __IOM uint16_t PGS    : 1; /*!< [0..0] Group Priority Control Setting                                     */
+            __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting                                            */
+            uint16_t              : 12;
+            __IOM uint16_t LGRRS  : 1; /*!< [14..14] Restart Channel Select                                           */
+            __IOM uint16_t GBRP   : 1; /*!< [15..15] Group B Single Scan Continuous Start                             */
+        } ADGSPCR_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IM uint16_t ADDBLDRA;        /*!< (@ 0x00000084) A/D Data Duplication Register A                            */
+
+        struct
+        {
+            __IM uint16_t DBLDRA : 16; /*!< [15..0] The result of A/D conversion during extended operation
+                                        *   in double trigger mode                                                    */
+        } ADDBLDRA_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDRB;        /*!< (@ 0x00000086) A/D Data Duplication Register B                            */
+
+        struct
+        {
+            __IM uint16_t DBLDRB : 16; /*!< [15..0] The result of A/D conversion during extended operation
+                                        *   in double trigger mode                                                    */
+        } ADDBLDRB_b;
+    };
+    __IM uint16_t RESERVED12[2];
+
+    union
+    {
+        __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitoring
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitor                                         */
+            uint8_t              : 3;
+            __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparing result monitor for window A                              */
+            __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparing result monitor for window B                              */
+            uint8_t              : 2;
+        } ADWINMON_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t CMPAB  : 2; /*!< [1..0] Window A/B combination condition setting                           */
+            uint16_t              : 7;
+            __IOM uint16_t CMPBE  : 1; /*!< [9..9] Window B operation permission                                      */
+            uint16_t              : 1;
+            __IOM uint16_t CMPAE  : 1; /*!< [11..11] Window A operation permission                                    */
+            uint16_t              : 1;
+            __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare window B Interrupt Enable                                */
+            __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function enable                                           */
+            __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare window A Interrupt Enable                                */
+        } ADCMPCR_b;
+    };
+    __IM uint16_t RESERVED15;
+
+    union
+    {
+        __IOM uint16_t ADCMPANSR0;       /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
+                                          *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t CMPCHA0 : 16; /*!< [15..0] Window A Channel Select                                           */
+        } ADCMPANSR0_b;
+    };
+    __IM uint16_t RESERVED16;
+
+    union
+    {
+        __IOM uint16_t ADCMPLR0;          /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
+                                           *                  Setting Register 0                                         */
+
+        struct
+        {
+            __IOM uint16_t CMPLCHA0 : 16; /*!< [15..0] Window A comparison condition for target channel (ch0-15)
+                                           *   setting                                                                   */
+        } ADCMPLR0_b;
+    };
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint16_t ADCMPDR0;        /*!< (@ 0x0000009C) A/D Comparison Function Window A Lower Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLLA : 16; /*!< [15..0] Reference data setting when using the compare function
+                                         *   window A                                                                  */
+        } ADCMPDR0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR1;        /*!< (@ 0x0000009E) AD Comparison Function Window A Upper Level Setting
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPULA : 16; /*!< [15..0] Reference data setting when using the compare function
+                                         *   window A                                                                  */
+        } ADCMPDR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPSR0;           /*!< (@ 0x000000A0) A/D Comparison Function Window A Channel Status
+                                            *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t CMPSTCHA0 : 16; /*!< [15..0] Window A Status Flag                                              */
+        } ADCMPSR0_b;
+    };
+    __IM uint16_t RESERVED18[2];
+
+    union
+    {
+        __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Window B Channel Select                                            */
+            uint8_t              : 1;
+            __IOM uint8_t CMPLB  : 1;  /*!< [7..7] Window B Comparison Condition Setting                              */
+        } ADCMPBNSR_b;
+    };
+    __IM uint8_t RESERVED19;
+
+    union
+    {
+        __IOM uint16_t ADWINLLB;        /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLLB : 16; /*!< [15..0] Reference lower data setting when using the compare
+                                         *   function window B                                                         */
+        } ADWINLLB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADWINULB;        /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPULB : 16; /*!< [15..0] Reference upper data setting when using the compare
+                                         *   function window B                                                         */
+        } ADWINULB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
+
+        struct
+        {
+            __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Window B Flag                                                      */
+            uint8_t              : 7;
+        } ADCMPBSR_b;
+    };
+    __IM uint8_t  RESERVED20;
+    __IM uint16_t RESERVED21[19];
+
+    union
+    {
+        __IOM uint16_t ADANSC0;        /*!< (@ 0x000000D4) A/D Channel Select Register C0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSC0 : 16; /*!< [15..0] A/D-Converted Channel Select for Group C in Group Scan
+                                        *   Mode                                                                      */
+        } ADANSC0_b;
+    };
+    __IM uint16_t RESERVED22;
+    __IM uint8_t  RESERVED23;
+
+    union
+    {
+        __IOM uint8_t ADGCTRGR;        /*!< (@ 0x000000D9) A/D Group C Trigger Select Register                        */
+
+        struct
+        {
+            __IOM uint8_t TRSC   : 6;  /*!< [5..0] Group C A/D Conversion Start Trigger Select                        */
+            __IOM uint8_t GCADIE : 1;  /*!< [6..6] Group C Scan Completion Interrupt Enable                           */
+            __IOM uint8_t GRCE   : 1;  /*!< [7..7] Group C A/D Conversion Enable                                      */
+        } ADGCTRGR_b;
+    };
+    __IM uint16_t RESERVED24[3];
+
+    union
+    {
+        __IOM uint8_t ADSSTR[15];      /*!< (@ 0x000000E0) A/D Sampling State Register n (n = 0 to 14)                */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting                                              */
+        } ADSSTR_b[15];
+    };
+    __IM uint8_t  RESERVED25;
+    __IM uint16_t RESERVED26[128];
+
+    union
+    {
+        __IOM uint16_t ADCALCTL;        /*!< (@ 0x000001F0) A/D Calibration Control Register                           */
+
+        struct
+        {
+            __IOM uint16_t CAL     : 1; /*!< [0..0] Calibration Start                                                  */
+            __IM uint16_t  CAL_RDY : 1; /*!< [1..1] Calibration Status                                                 */
+            __IM uint16_t  CAL_ERR : 1; /*!< [2..2] Calibration Result                                                 */
+            uint16_t               : 13;
+        } ADCALCTL_b;
+    };
+} R_ADC122_Type;                        /*!< Size = 498 (0x1f2)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CANFD                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CAN-FD (R_CANFD)
+ */
+
+typedef struct                         /*!< (@ 0x80040000) R_CANFD Structure                                          */
+{
+    __IOM R_CANFD_CFDC_Type CFDC[2];   /*!< (@ 0x00000000) CANFD Channel [0..1] Registers                             */
+    __IM uint32_t           RESERVED[24];
+
+    union
+    {
+        __IM uint32_t CFDGIPV;         /*!< (@ 0x00000080) Global IP Version Register                                 */
+
+        struct
+        {
+            __IM uint32_t IPV : 8;     /*!< [7..0] IP Version                                                         */
+            __IM uint32_t IPT : 2;     /*!< [9..8] IP Type                                                            */
+            uint32_t          : 6;
+            __IM uint32_t PSI : 14;    /*!< [29..16] Parameter Status Information                                     */
+            uint32_t          : 2;
+        } CFDGIPV_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGCFG;         /*!< (@ 0x00000084) Global Configuration Register                              */
+
+        struct
+        {
+            __IOM uint32_t TPRI   : 1;  /*!< [0..0] Transmission Priority                                              */
+            __IOM uint32_t DCE    : 1;  /*!< [1..1] DLC Check Enable                                                   */
+            __IOM uint32_t DRE    : 1;  /*!< [2..2] DLC Replacement Enable                                             */
+            __IOM uint32_t MME    : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
+            __IOM uint32_t DCS    : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
+            __IOM uint32_t CMPOC  : 1;  /*!< [5..5] CAN-FD Message Payload Overflow Configuration                      */
+            uint32_t              : 2;
+            __IOM uint32_t TSP    : 4;  /*!< [11..8] Timestamp Prescaler                                               */
+            __IOM uint32_t TSSS   : 1;  /*!< [12..12] Timestamp Source Select                                          */
+            __IOM uint32_t TSBTCS : 3;  /*!< [15..13] Timestamp Bit Time Channel Select                                */
+            __IOM uint32_t ITRCP  : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
+        } CFDGCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000088) Global Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
+            __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
+            uint32_t               : 5;
+            __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC Check Interrupt Enable                                         */
+            __IOM uint32_t MEIE    : 1; /*!< [9..9] Message Lost Error Interrupt Enable                                */
+            __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
+            __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD Message Payload Overflow Flag Interrupt Enable            */
+            __IOM uint32_t QOWEIE  : 1; /*!< [12..12] TXQ Message Overwrite Error Interrupt Enable                     */
+            uint32_t               : 1;
+            __IOM uint32_t QMEIE   : 1; /*!< [14..14] TXQ Message Lost Error Interrupt Enable                          */
+            __IOM uint32_t MOWEIE  : 1; /*!< [15..15] Message Lost Error Interrupt Enable                              */
+            __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
+            uint32_t               : 15;
+        } CFDGCTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDGSTS;          /*!< (@ 0x0000008C) Global Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
+            __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
+            __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
+            __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialization                                          */
+            uint32_t               : 28;
+        } CFDGSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000090) Global Error Flag Register                                 */
+
+        struct
+        {
+            __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
+            __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
+            __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
+            __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD Message Payload Overflow Flag                               */
+            __IM uint32_t  QOWES : 1;  /*!< [4..4] TXQ Message Overwrite Error Status                                 */
+            uint32_t             : 1;
+            __IM uint32_t QMES   : 1;  /*!< [6..6] TXQ Message Lost Error Status                                      */
+            __IM uint32_t MOWES  : 1;  /*!< [7..7] Message Overwrite Error Status                                     */
+            uint32_t             : 24;
+        } CFDGERFL_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDGTSC;         /*!< (@ 0x00000094) Global Timestamp Counter Register                          */
+
+        struct
+        {
+            __IM uint32_t TS : 16;     /*!< [15..0] Timestamp value                                                   */
+            uint32_t         : 16;
+        } CFDGTSC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register       */
+
+        struct
+        {
+            __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
+            uint32_t              : 4;
+            __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
+            uint32_t              : 23;
+        } CFDGAFLECTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register
+                                        *                  0                                                          */
+
+        struct
+        {
+            __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
+            uint32_t            : 7;
+            __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
+            uint32_t            : 7;
+        } CFDGAFLCFG0_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint32_t CFDRMNB;        /*!< (@ 0x000000AC) RX Message Buffer Number Register                          */
+
+        struct
+        {
+            __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
+            __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
+            uint32_t             : 21;
+        } CFDRMNB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRMND0;       /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t RMNS : 32;  /*!< [31..0] RX Message Buffer New Data Status                                 */
+        } CFDRMND0_b;
+    };
+    __IM uint32_t RESERVED2[3];
+
+    union
+    {
+        __IOM uint32_t CFDRFCC[8];     /*!< (@ 0x000000C0) RX FIFO Configuration/Control Register [0..7]              */
+
+        struct
+        {
+            __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
+            __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
+            uint32_t              : 2;
+            __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size Configuration                            */
+            uint32_t              : 1;
+            __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
+            uint32_t              : 1;
+            __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
+            __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
+            __IOM uint32_t RFFIE  : 1; /*!< [16..16] RX FIFO Full Interrupt Enable                                    */
+            uint32_t              : 15;
+        } CFDRFCC_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFSTS[8];    /*!< (@ 0x000000E0) RX FIFO Status Register [0..7]                             */
+
+        struct
+        {
+            __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
+            __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
+            __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
+            __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
+            uint32_t             : 4;
+            __IM uint32_t  RFMC  : 8;  /*!< [15..8] RX FIFO Message Count                                             */
+            __IOM uint32_t RFFIF : 1;  /*!< [16..16] RX FIFO Full Interrupt Flag                                      */
+            uint32_t             : 15;
+        } CFDRFSTS_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFPCTR[8];   /*!< (@ 0x00000100) RX FIFO Pointer Control Register [0..7]                    */
+
+        struct
+        {
+            __IOM uint32_t RFPC : 8;   /*!< [7..0] RX FIFO Pointer Control                                            */
+            uint32_t            : 24;
+        } CFDRFPCTR_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCFCC[6];     /*!< (@ 0x00000120) Common FIFO Configuration/Control Register [0..5]          */
+
+        struct
+        {
+            __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
+            __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
+            __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data Size Configuration                        */
+            uint32_t              : 1;
+            __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
+            __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
+            __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
+            __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
+            __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
+            __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
+            __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
+            __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
+        } CFDCFCC_b[6];
+    };
+    __IM uint32_t RESERVED3[18];
+
+    union
+    {
+        __IOM uint32_t CFDCFCCE[6];      /*!< (@ 0x00000180) Common FIFO Configuration/Control Enhancement
+                                          *                  Register [0..5]                                            */
+
+        struct
+        {
+            __IOM uint32_t CFFIE    : 1; /*!< [0..0] Common FIFO Full Interrupt Enable                                  */
+            __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable                   */
+            __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable                */
+            uint32_t                : 5;
+            __IOM uint32_t CFMOWM   : 1; /*!< [8..8] Common FIFO Message Overwrite Mode                                 */
+            uint32_t                : 7;
+            __IOM uint32_t CFBME    : 1; /*!< [16..16] Common FIFO Buffering Mode Enable                                */
+            uint32_t                : 15;
+        } CFDCFCCE_b[6];
+    };
+    __IM uint32_t RESERVED4[18];
+
+    union
+    {
+        __IOM uint32_t CFDCFSTS[6];      /*!< (@ 0x000001E0) Common FIFO Status Register [0..5]                         */
+
+        struct
+        {
+            __IM uint32_t  CFEMP    : 1; /*!< [0..0] Common FIFO Empty                                                  */
+            __IM uint32_t  CFFLL    : 1; /*!< [1..1] Common FIFO Full                                                   */
+            __IOM uint32_t CFMLT    : 1; /*!< [2..2] Common FIFO Message Lost                                           */
+            __IOM uint32_t CFRXIF   : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
+            __IOM uint32_t CFTXIF   : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
+            uint32_t                : 3;
+            __IM uint32_t  CFMC     : 8; /*!< [15..8] Common FIFO Message Count                                         */
+            __IOM uint32_t CFFIF    : 1; /*!< [16..16] Common FIFO Full Interrupt Flag                                  */
+            __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag                   */
+            __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag                */
+            uint32_t                : 5;
+            __IOM uint32_t CFMOW    : 1; /*!< [24..24] Common FIFO Message Overwrite                                    */
+            uint32_t                : 7;
+        } CFDCFSTS_b[6];
+    };
+    __IM uint32_t RESERVED5[18];
+
+    union
+    {
+        __OM uint32_t CFDCFPCTR[6];    /*!< (@ 0x00000240) Common FIFO Pointer Control Register [0..5]                */
+
+        struct
+        {
+            __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
+            uint32_t           : 24;
+        } CFDCFPCTR_b[6];
+    };
+    __IM uint32_t RESERVED6[18];
+
+    union
+    {
+        __IM uint32_t CFDFESTS;        /*!< (@ 0x000002A0) FIFO Empty Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t RFXEMP : 8;  /*!< [7..0] RX FIFO Empty Status                                               */
+            __IM uint32_t CFXEMP : 6;  /*!< [13..8] Common FIFO Empty Status                                          */
+            uint32_t             : 18;
+        } CFDFESTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFFSTS;        /*!< (@ 0x000002A4) FIFO Full Status Register                                  */
+
+        struct
+        {
+            __IM uint32_t RFXFLL : 8;  /*!< [7..0] RX FIFO Full Status                                                */
+            __IM uint32_t CFXFLL : 6;  /*!< [13..8] Common FIFO Full Status                                           */
+            uint32_t             : 18;
+        } CFDFFSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFMSTS;        /*!< (@ 0x000002A8) FIFO Message Lost Status Register                          */
+
+        struct
+        {
+            __IM uint32_t RFXMLT : 8;  /*!< [7..0] RX FIFO Message Lost Status                                        */
+            __IM uint32_t CFXMLT : 6;  /*!< [13..8] Common FIFO Message Lost Status                                   */
+            uint32_t             : 18;
+        } CFDFMSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDRFISTS;       /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register                     */
+
+        struct
+        {
+            __IM uint32_t RFXIF   : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status                                   */
+            uint32_t              : 8;
+            __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status                            */
+            uint32_t              : 8;
+        } CFDRFISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFRISTS;      /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register              */
+
+        struct
+        {
+            __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO RX Interrupt Flag Status                               */
+            uint32_t              : 26;
+        } CFDCFRISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFTISTS;      /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register              */
+
+        struct
+        {
+            __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO TX Interrupt Flag Status                               */
+            uint32_t              : 26;
+        } CFDCFTISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFOFRISTS;      /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO One Frame RX Interrupt Flag Status                     */
+            uint32_t                : 26;
+        } CFDCFOFRISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFOFTISTS;      /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO One Frame TX Interrupt Flag Status                     */
+            uint32_t                : 26;
+        } CFDCFOFTISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCFMOWSTS;     /*!< (@ 0x000002C0) Common FIFO Message Overwrite Status Register              */
+
+        struct
+        {
+            __IM uint32_t CFXMOW : 6;  /*!< [5..0] Common FIFO Massage Overwrite Status                               */
+            uint32_t             : 26;
+        } CFDCFMOWSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFFFSTS;       /*!< (@ 0x000002C4) FIFO FDC Full Status Register                              */
+
+        struct
+        {
+            __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC Level Full Status                                      */
+            __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC Level Full Status                                 */
+            uint32_t              : 18;
+        } CFDFFFSTS_b;
+    };
+    __IM uint32_t RESERVED7[2];
+
+    union
+    {
+        __IOM uint8_t CFDTMC[128];     /*!< (@ 0x000002D0) TX Message Buffer Control Register [0..127]                */
+
+        struct
+        {
+            __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
+            __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission Abort Request                       */
+            __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
+            uint8_t             : 5;
+        } CFDTMC_b[128];
+    };
+    __IM uint32_t RESERVED8[288];
+
+    union
+    {
+        __IOM uint8_t CFDTMSTS[128];   /*!< (@ 0x000007D0) TX Message Buffer Status Register [0..127]                 */
+
+        struct
+        {
+            __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
+            __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
+            __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
+            __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission Abort Request Mirrored              */
+            uint8_t              : 3;
+        } CFDTMSTS_b[128];
+    };
+    __IM uint32_t RESERVED9[288];
+
+    union
+    {
+        __IM uint32_t CFDTMTRSTS[4];    /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status
+                                         *                  Register [0..3]                                            */
+
+        struct
+        {
+            __IM uint32_t TMTRSTS : 16; /*!< [15..0] TX Message Buffer Transmission Request Status                     */
+            uint32_t              : 16;
+        } CFDTMTRSTS_b[4];
+    };
+    __IM uint32_t RESERVED10[36];
+
+    union
+    {
+        __IM uint32_t CFDTMTARSTS[4];    /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request
+                                          *                  Status Register [0..3]                                     */
+
+        struct
+        {
+            __IM uint32_t TMTARSTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Request Status               */
+            uint32_t               : 16;
+        } CFDTMTARSTS_b[4];
+    };
+    __IM uint32_t RESERVED11[36];
+
+    union
+    {
+        __IM uint32_t CFDTMTCSTS[4];    /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status
+                                         *                  Register [0..3]                                            */
+
+        struct
+        {
+            __IM uint32_t TMTCSTS : 16; /*!< [15..0] TX Message Buffer Transmission Completion Status                  */
+            uint32_t              : 16;
+        } CFDTMTCSTS_b[4];
+    };
+    __IM uint32_t RESERVED12[36];
+
+    union
+    {
+        __IM uint32_t CFDTMTASTS[4];    /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register
+                                         *                  [0..3]                                                     */
+
+        struct
+        {
+            __IM uint32_t TMTASTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Status                       */
+            uint32_t              : 16;
+        } CFDTMTASTS_b[4];
+    };
+    __IM uint32_t RESERVED13[36];
+
+    union
+    {
+        __IOM uint32_t CFDTMIEC[4];    /*!< (@ 0x00000F50) TX Message Buffer Transmission Interrupt Enable
+                                        *                  Register [0..3]                                            */
+
+        struct
+        {
+            __IOM uint32_t TMIE : 16;  /*!< [15..0] TX Message Buffer Interrupt Enable                                */
+            uint32_t            : 16;
+        } CFDTMIEC_b[4];
+    };
+    __IM uint32_t RESERVED14[40];
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC0[2];      /*!< (@ 0x00001000) TX Queue Configuration/Control Register 0[0..1]            */
+
+        struct
+        {
+            __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
+            __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
+            __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
+            uint32_t                 : 3;
+            __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
+            __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
+            __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
+            uint32_t                 : 13;
+        } CFDTXQCC0_b[2];
+    };
+    __IM uint32_t RESERVED15[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS0[2];     /*!< (@ 0x00001020) TX Queue Status Register 0[0..1]                           */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t                 : 5;
+            __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
+            __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
+            __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
+            __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
+            __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
+            uint32_t                 : 11;
+        } CFDTXQSTS0_b[2];
+    };
+    __IM uint32_t RESERVED16[6];
+
+    union
+    {
+        __OM uint32_t CFDTXQPCTR0[2];  /*!< (@ 0x00001040) TX Queue Pointer Control Register 0[0..1]                  */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR0_b[2];
+    };
+    __IM uint32_t RESERVED17[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC1[2];      /*!< (@ 0x00001060) TX Queue Configuration/Control Register 1[0..1]            */
+
+        struct
+        {
+            __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
+            __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
+            __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
+            uint32_t                 : 3;
+            __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
+            __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
+            __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
+            uint32_t                 : 13;
+        } CFDTXQCC1_b[2];
+    };
+    __IM uint32_t RESERVED18[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS1[2];     /*!< (@ 0x00001080) TX Queue Status Register 1[0..1]                           */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t                 : 5;
+            __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
+            __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
+            __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
+            __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
+            __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
+            uint32_t                 : 11;
+        } CFDTXQSTS1_b[2];
+    };
+    __IM uint32_t RESERVED19[6];
+
+    union
+    {
+        __OM uint32_t CFDTXQPCTR1[2];  /*!< (@ 0x000010A0) TX Queue Pointer Control Register 1[0..1]                  */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR1_b[2];
+    };
+    __IM uint32_t RESERVED20[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC2[2];      /*!< (@ 0x000010C0) TX Queue Configuration/Control Register 2[0..1]            */
+
+        struct
+        {
+            __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
+            __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
+            __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
+            uint32_t                 : 3;
+            __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
+            __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
+            __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
+            uint32_t                 : 13;
+        } CFDTXQCC2_b[2];
+    };
+    __IM uint32_t RESERVED21[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS2[2];     /*!< (@ 0x000010E0) TX Queue Status Register 2[0..1]                           */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t                 : 5;
+            __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
+            __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
+            __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
+            __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
+            __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
+            uint32_t                 : 11;
+        } CFDTXQSTS2_b[2];
+    };
+    __IM uint32_t RESERVED22[6];
+
+    union
+    {
+        __OM uint32_t CFDTXQPCTR2[2];  /*!< (@ 0x00001100) TX Queue Pointer Control Register 2[0..1]                  */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR2_b[2];
+    };
+    __IM uint32_t RESERVED23[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC3[2];      /*!< (@ 0x00001120) TX Queue Configuration/Control Register 3[0..1]            */
+
+        struct
+        {
+            __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
+            uint32_t                 : 5;
+            __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
+            uint32_t                 : 13;
+        } CFDTXQCC3_b[2];
+    };
+    __IM uint32_t RESERVED24[6];
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS3[2];     /*!< (@ 0x00001140) TX Queue Status Register 3[0..1]                           */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t                 : 5;
+            __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t                 : 4;
+            __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
+            uint32_t                 : 1;
+            __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
+            uint32_t                 : 11;
+        } CFDTXQSTS3_b[2];
+    };
+    __IM uint32_t RESERVED25[6];
+
+    union
+    {
+        __OM uint32_t CFDTXQPCTR3[2];  /*!< (@ 0x00001160) TX Queue Pointer Control Register 3[0..1]                  */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR3_b[2];
+    };
+    __IM uint32_t RESERVED26[6];
+
+    union
+    {
+        __IM uint32_t CFDTXQESTS;      /*!< (@ 0x00001180) TX Queue Empty Status Register                             */
+
+        struct
+        {
+            __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ Empty Status                                                   */
+            uint32_t              : 24;
+        } CFDTXQESTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQFISTS;      /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register                    */
+
+        struct
+        {
+            __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status Flag for Channel 0                       */
+            uint32_t               : 1;
+            __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status Flag for Channel 1                       */
+            uint32_t               : 25;
+        } CFDTXQFISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQMSTS;      /*!< (@ 0x00001188) TX Queue Message Lost Status Register                      */
+
+        struct
+        {
+            __IM uint32_t TXQ0ML : 3;  /*!< [2..0] TXQ Message Lost Status Flag for Channel 0                         */
+            uint32_t             : 1;
+            __IM uint32_t TXQ1ML : 3;  /*!< [6..4] TXQ Message Lost Status Flag for Channel 1                         */
+            uint32_t             : 25;
+        } CFDTXQMSTS_b;
+    };
+    __IM uint32_t RESERVED27;
+
+    union
+    {
+        __IM uint32_t CFDTXQISTS;      /*!< (@ 0x00001190) TX Queue Interrupt Status Register                         */
+
+        struct
+        {
+            __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for Channel 0                            */
+            __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for Channel 1                            */
+            uint32_t              : 24;
+        } CFDTXQISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQOFTISTS;      /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register            */
+
+        struct
+        {
+            __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for Channel 0               */
+            __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for Channel 1               */
+            uint32_t                 : 24;
+        } CFDTXQOFTISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQOFRISTS;      /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register            */
+
+        struct
+        {
+            __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag for Channel 0               */
+            uint32_t                 : 1;
+            __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag for Channel 1               */
+            uint32_t                 : 25;
+        } CFDTXQOFRISTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDTXQFSTS;      /*!< (@ 0x0000119C) TX Queue Full Status Register                              */
+
+        struct
+        {
+            __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for Channel 0                                 */
+            __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for Channel 1                                 */
+            uint32_t              : 24;
+        } CFDTXQFSTS_b;
+    };
+    __IM uint32_t RESERVED28[24];
+
+    union
+    {
+        __IOM uint32_t CFDTHLCC[2];    /*!< (@ 0x00001200) TX History List Configuration/Control Register
+                                        *                  [0..1]                                                     */
+
+        struct
+        {
+            __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
+            uint32_t              : 7;
+            __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
+            __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
+            __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
+            __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated Gateway Enable                         */
+            uint32_t              : 20;
+        } CFDTHLCC_b[2];
+    };
+    __IM uint32_t RESERVED29[6];
+
+    union
+    {
+        __IOM uint32_t CFDTHLSTS[2];   /*!< (@ 0x00001220) TX History List Status Register [0..1]                     */
+
+        struct
+        {
+            __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
+            __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
+            __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
+            __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
+            uint32_t              : 4;
+            __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
+            uint32_t              : 18;
+        } CFDTHLSTS_b[2];
+    };
+    __IM uint32_t RESERVED30[6];
+
+    union
+    {
+        __OM uint32_t CFDTHLPCTR[2];   /*!< (@ 0x00001240) TX History List Pointer Control Register [0..1]            */
+
+        struct
+        {
+            __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
+            uint32_t            : 24;
+        } CFDTHLPCTR_b[2];
+    };
+    __IM uint32_t RESERVED31[46];
+
+    union
+    {
+        __IM uint32_t CFDGTINTSTS0;    /*!< (@ 0x00001300) Global TX Interrupt Status Register 0                      */
+
+        struct
+        {
+            __IM uint32_t TSIF0   : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
+            __IM uint32_t TAIF0   : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
+            __IM uint32_t TQIF0   : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
+            __IM uint32_t CFTIF0  : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
+            __IM uint32_t THIF0   : 1; /*!< [4..4] TX History List Interrupt Channel 0                                */
+            __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel
+                                        *   0                                                                         */
+            __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel
+                                        *   0                                                                         */
+            uint32_t              : 1;
+            __IM uint32_t TSIF1   : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1                             */
+            __IM uint32_t TAIF1   : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1                                  */
+            __IM uint32_t TQIF1   : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1                                */
+            __IM uint32_t CFTIF1  : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1                     */
+            __IM uint32_t THIF1   : 1; /*!< [12..12] TX History List Interrupt Channel 1                              */
+            __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel
+                                        *   1                                                                         */
+            __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel
+                                        *   1                                                                         */
+            uint32_t : 17;
+        } CFDGTINTSTS0_b;
+    };
+    __IM uint32_t RESERVED32;
+
+    union
+    {
+        __IOM uint32_t CFDGTSTCFG;       /*!< (@ 0x00001308) Global Test Configuration Register                         */
+
+        struct
+        {
+            __IOM uint32_t C0ICBCE : 1;  /*!< [0..0] Channel 0 Internal CAN Bus Communication Test Mode Enable          */
+            __IOM uint32_t C1ICBCE : 1;  /*!< [1..1] Channel 1 Internal CAN Bus Communication Test Mode Enable          */
+            uint32_t               : 14;
+            __IOM uint32_t RTMPS   : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
+            uint32_t               : 6;
+        } CFDGTSTCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTSTCTR;      /*!< (@ 0x0000130C) Global Test Control Register                               */
+
+        struct
+        {
+            __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable                    */
+            uint32_t               : 1;
+            __IOM uint32_t RTME    : 1; /*!< [2..2] RAM Test Mode Enable                                               */
+            uint32_t               : 29;
+        } CFDGTSTCTR_b;
+    };
+    __IM uint32_t RESERVED33;
+
+    union
+    {
+        __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x00001314) Global FD Configuration Register                           */
+
+        struct
+        {
+            __IOM uint32_t RPED   : 1; /*!< [0..0] RES Bit Protocol Exception Disable                                 */
+            uint32_t              : 7;
+            __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp Capture Configuration                                    */
+            uint32_t              : 22;
+        } CFDGFDCFG_b;
+    };
+    __IM uint32_t RESERVED34;
+
+    union
+    {
+        __OM uint32_t CFDGLOCKK;       /*!< (@ 0x0000131C) Global Lock Key Register                                   */
+
+        struct
+        {
+            __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
+            uint32_t           : 16;
+        } CFDGLOCKK_b;
+    };
+    __IM uint32_t RESERVED35[4];
+
+    union
+    {
+        __IOM uint32_t CFDCDTCT;        /*!< (@ 0x00001330) DMA Transfer Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RX FIFO 0                                  */
+            __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RX FIFO 1                                  */
+            __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RX FIFO 2                                  */
+            __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RX FIFO 3                                  */
+            __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RX FIFO 4                                  */
+            __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RX FIFO 5                                  */
+            __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RX FIFO 6                                  */
+            __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RX FIFO 7                                  */
+            __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of Channel 0                 */
+            __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of Channel 1                 */
+            uint32_t               : 22;
+        } CFDCDTCT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCDTSTS;         /*!< (@ 0x00001334) DMA Transfer Status Register                               */
+
+        struct
+        {
+            __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
+            __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
+            __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2                                  */
+            __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3                                  */
+            __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4                                  */
+            __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5                                  */
+            __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6                                  */
+            __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7                                  */
+            __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of Channel
+                                          *   0                                                                         */
+            __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of Channel
+                                          *   1                                                                         */
+            uint32_t : 22;
+        } CFDCDTSTS_b;
+    };
+    __IM uint32_t RESERVED36[2];
+
+    union
+    {
+        __IOM uint32_t CFDCDTTCT;        /*!< (@ 0x00001340) DMA TX Transfer Control Register                           */
+
+        struct
+        {
+            __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of Channel 0                      */
+            __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of Channel 1                      */
+            uint32_t                : 6;
+            __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of Channel 0                      */
+            __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of Channel 1                      */
+            uint32_t                : 6;
+            __IOM uint32_t CFDMAE0  : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of Channel
+                                          *   0                                                                         */
+            __IOM uint32_t CFDMAE1 : 1;  /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of Channel
+                                          *   1                                                                         */
+            uint32_t : 14;
+        } CFDCDTTCT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCDTTSTS;         /*!< (@ 0x00001344) DMA TX Transfer Status Register                            */
+
+        struct
+        {
+            __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of Channel 0                       */
+            __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of Channel 1                       */
+            uint32_t                 : 6;
+            __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of Channel 0                       */
+            __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of Channel 1                       */
+            uint32_t                 : 6;
+            __IM uint32_t CFDMASTS0  : 1; /*!< [16..16] DMA TX Transfer Status for Common FIFO 2 of Channel
+                                           *   0                                                                         */
+            __IM uint32_t CFDMASTS1 : 1;  /*!< [17..17] DMA TX Transfer Status for Common FIFO 2 of Channel
+                                           *   1                                                                         */
+            uint32_t : 14;
+        } CFDCDTTSTS_b;
+    };
+    __IM uint32_t RESERVED37[2];
+
+    union
+    {
+        __IM uint32_t CFDGRINTSTS[2];  /*!< (@ 0x00001350) Global RX Interrupt Status Register [0..1]                 */
+
+        struct
+        {
+            __IM uint32_t QFIF    : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n (n = 0, 1)                       */
+            uint32_t              : 1;
+            __IM uint32_t BQFIF   : 2; /*!< [5..4] Borrowed TXQ Full Interrupt Flag Channel n (n = 0, 1)              */
+            uint32_t              : 2;
+            __IM uint32_t QOFRIF  : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n (n = 0, 1)              */
+            uint32_t              : 1;
+            __IM uint32_t BQOFRIF : 2; /*!< [13..12] Borrowed TXQ One Frame RX Interrupt Flag Channel n
+                                        *   (n = 0, 1)                                                                */
+            uint32_t             : 2;
+            __IM uint32_t CFRIF  : 3;  /*!< [18..16] Common FIFO RX Interrupt Flag Channel n (n = 0, 1)               */
+            uint32_t             : 5;
+            __IM uint32_t CFRFIF : 3;  /*!< [26..24] Common FIFO FDC Level Full Interrupt Flag Channel n
+                                        *   (n = 0, 1)                                                                */
+            uint32_t              : 1;
+            __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n (n
+                                        *   = 0, 1)                                                                   */
+            uint32_t : 1;
+        } CFDGRINTSTS_b[2];
+    };
+    __IM uint32_t RESERVED38[10];
+
+    union
+    {
+        __IOM uint32_t CFDGRSTC;       /*!< (@ 0x00001380) Global Reset Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t SRST : 1;   /*!< [0..0] Software Reset                                                     */
+            uint32_t            : 7;
+            __OM uint32_t KEY   : 8;   /*!< [15..8] Key Code                                                          */
+            uint32_t            : 16;
+        } CFDGRSTC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGFCMC;       /*!< (@ 0x00001384) Global Flexible CAN Mode Configuration Register            */
+
+        struct
+        {
+            __IOM uint32_t FLXC0 : 1;  /*!< [0..0] Flexible CAN Mode between Channel 0 and Channel 1                  */
+            uint32_t             : 31;
+        } CFDGFCMC_b;
+    };
+    __IM uint32_t RESERVED39;
+
+    union
+    {
+        __IOM uint32_t CFDGFTBAC;      /*!< (@ 0x0000138C) Global Flexible Transmission Buffer Assignment
+                                        *                  Configuration Register                                     */
+
+        struct
+        {
+            __IOM uint32_t FLXMB0 : 4; /*!< [3..0] Flexible Transmission Buffer Assignment between Channel
+                                        *   0 and Channel 1                                                           */
+            uint32_t : 28;
+        } CFDGFTBAC_b;
+    };
+    __IM uint32_t              RESERVED40[28];
+    __IOM R_CANFD_CFDC2_Type   CFDC2[2];    /*!< (@ 0x00001400) Channel Configuration Registers                            */
+    __IM uint32_t              RESERVED41[240];
+    __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers                    */
+    __IM uint32_t              RESERVED42[448];
+    __IOM R_CANFD_CFDRM_Type   CFDRM[32];   /*!< (@ 0x00002000) RX Message Buffer Access Registers                         */
+    __IM uint32_t              RESERVED43[3072];
+    __IOM R_CANFD_CFDRF_Type   CFDRF[8];    /*!< (@ 0x00006000) RX FIFO Access Registers                                   */
+    __IOM R_CANFD_CFDCF_Type   CFDCF[6];    /*!< (@ 0x00006400) Common FIFO Access Registers                               */
+    __IM uint32_t              RESERVED44[1600];
+    __IOM R_CANFD_CFDTHL_Type  CFDTHL[2];   /*!< (@ 0x00008000) Channel TX History List                                    */
+    __IM uint32_t              RESERVED45[252];
+
+    union
+    {
+        __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00008400) RAM Test Page Access Register [0..63]                      */
+
+        struct
+        {
+            __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
+        } CFDRPGACC_b[64];
+    };
+    __IM uint32_t            RESERVED46[7872];
+    __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Registers                                */
+} R_CANFD_Type;                          /*!< Size = 81920 (0x14000)                                                    */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CMT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Compare Match Timer Control (R_CMT)
+ */
+
+typedef struct                         /*!< (@ 0x80080000) R_CMT Structure                                            */
+{
+    __IOM R_CMT_UNT_Type UNT[3];       /*!< (@ 0x00000000) 3 Timer Start Register Units                               */
+} R_CMT_Type;                          /*!< Size = 3072 (0xc00)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CMTW0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Compare Match Timer W (R_CMTW0)
+ */
+
+typedef struct                         /*!< (@ 0x80081000) R_CMTW0 Structure                                          */
+{
+    union
+    {
+        __IOM uint16_t CMWSTR;         /*!< (@ 0x00000000) Timer Start Register                                       */
+
+        struct
+        {
+            __IOM uint16_t STR : 1;    /*!< [0..0] Counter Start                                                      */
+            uint16_t           : 15;
+        } CMWSTR_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CMWCR;          /*!< (@ 0x00000004) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint16_t CKS   : 2;  /*!< [1..0] Clock Select                                                       */
+            uint16_t             : 1;
+            __IOM uint16_t CMWIE : 1;  /*!< [3..3] Compare Match Interrupt Enable                                     */
+            __IOM uint16_t IC0IE : 1;  /*!< [4..4] Input Capture 0 Interrupt Enable                                   */
+            __IOM uint16_t IC1IE : 1;  /*!< [5..5] Input Capture 1 Interrupt Enable                                   */
+            __IOM uint16_t OC0IE : 1;  /*!< [6..6] Output Compare 0 Interrupt Enable                                  */
+            __IOM uint16_t OC1IE : 1;  /*!< [7..7] Output Compare 1 Interrupt Enable                                  */
+            uint16_t             : 1;
+            __IOM uint16_t CMS   : 1;  /*!< [9..9] Timer Counter Size                                                 */
+            uint16_t             : 3;
+            __IOM uint16_t CCLR  : 3;  /*!< [15..13] Counter Clear                                                    */
+        } CMWCR_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t CMWIOR;         /*!< (@ 0x00000008) Timer I/O Control Register                                 */
+
+        struct
+        {
+            __IOM uint16_t IC0  : 2;   /*!< [1..0] Input Capture Control 0                                            */
+            __IOM uint16_t IC1  : 2;   /*!< [3..2] Input Capture Control 1                                            */
+            __IOM uint16_t IC0E : 1;   /*!< [4..4] Input Capture Enable 0                                             */
+            __IOM uint16_t IC1E : 1;   /*!< [5..5] Input Capture Enable 1                                             */
+            uint16_t            : 2;
+            __IOM uint16_t OC0  : 2;   /*!< [9..8] Output Compare Control 0                                           */
+            __IOM uint16_t OC1  : 2;   /*!< [11..10] Output Compare Control 1                                         */
+            __IOM uint16_t OC0E : 1;   /*!< [12..12] Compare Match Enable 0                                           */
+            __IOM uint16_t OC1E : 1;   /*!< [13..13] Compare Match Enable 1                                           */
+            uint16_t            : 1;
+            __IOM uint16_t CMWE : 1;   /*!< [15..15] Compare Match Enable                                             */
+        } CMWIOR_b;
+    };
+    __IM uint16_t  RESERVED2;
+    __IM uint32_t  RESERVED3;
+    __IOM uint32_t CMWCNT;             /*!< (@ 0x00000010) Timer Counter                                              */
+    __IOM uint32_t CMWCOR;             /*!< (@ 0x00000014) Compare Match Constant Register                            */
+    __IM uint32_t  CMWICR0;            /*!< (@ 0x00000018) Input Capture Registers                                    */
+    __IM uint32_t  CMWICR1;            /*!< (@ 0x0000001C) Input Capture Registers                                    */
+    __IOM uint32_t CMWOCR0;            /*!< (@ 0x00000020) Output Compare Registers                                   */
+    __IOM uint32_t CMWOCR1;            /*!< (@ 0x00000024) Output Compare Registers                                   */
+} R_CMTW0_Type;                        /*!< Size = 40 (0x28)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_WDT0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Watchdog Timer 0 (R_WDT0)
+ */
+
+typedef struct                         /*!< (@ 0x80082000) R_WDT0 Structure                                           */
+{
+    __IOM uint8_t WDTRR;               /*!< (@ 0x00000000) WDT Refresh Register                                       */
+    __IM uint8_t  RESERVED;
+
+    union
+    {
+        __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
+            uint16_t            : 2;
+            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
+            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
+            uint16_t            : 2;
+            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
+            uint16_t            : 2;
+        } WDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
+            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
+            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
+        } WDTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
+
+        struct
+        {
+            uint8_t               : 7;
+            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
+        } WDTRCR_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+} R_WDT0_Type;                         /*!< Size = 10 (0xa)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Operation Circuit (R_DOC)
+ */
+
+typedef struct                         /*!< (@ 0x80084000) R_DOC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
+            __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
+            uint8_t               : 1;
+            __IOM uint8_t DOPCIE  : 1; /*!< [4..4] Data Operation Circuit Interrupt Enable                            */
+            __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
+            __OM uint8_t  DOPCFCL : 1; /*!< [6..6] DOPCF Flag Clear                                                   */
+            uint8_t               : 1;
+        } DOCR_b;
+    };
+    __IM uint8_t   RESERVED;
+    __IOM uint16_t DODIR;              /*!< (@ 0x00000002) DOC Data Input Register                                    */
+    __IOM uint16_t DODSR;              /*!< (@ 0x00000004) DOC Data Setting Register                                  */
+} R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_TSU_B0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor Unit (R_TSU_B0)
+ */
+
+typedef struct                            /*!< (@ 0x80086000) R_TSU_B0 Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t SSUSR;             /*!< (@ 0x00000000) Sensor Suspend Register                                    */
+
+        struct
+        {
+            __IOM uint32_t EN_TS     : 1; /*!< [0..0] EN_TS                                                              */
+            __IOM uint32_t ADC_PD    : 1; /*!< [1..1] ADC_PD                                                             */
+            __IOM uint32_t SOC_TS_EN : 1; /*!< [2..2] SOC_TS_EN                                                          */
+            uint32_t                 : 29;
+        } SSUSR_b;
+    };
+
+    union
+    {
+        __OM uint32_t STRGR;           /*!< (@ 0x00000004) Sensor Trigger Register                                    */
+
+        struct
+        {
+            __OM uint32_t ADST  : 1;   /*!< [0..0] ADST                                                               */
+            __OM uint32_t ADEND : 1;   /*!< [1..1] ADEND                                                              */
+            uint32_t            : 30;
+        } STRGR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SOSR1;          /*!< (@ 0x00000008) Sensor Operation Setting 1 Register                        */
+
+        struct
+        {
+            __IOM uint32_t ADCT  : 2;  /*!< [1..0] ADCT                                                               */
+            uint32_t             : 2;
+            __IOM uint32_t ADCS  : 1;  /*!< [4..4] ADCS                                                               */
+            uint32_t             : 4;
+            __IM uint32_t OUTSEL : 1;  /*!< [9..9] OUTSEL                                                             */
+            uint32_t             : 22;
+        } SOSR1_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IM uint32_t SCRR;                 /*!< (@ 0x00000010) Sensor Code Read Register                                  */
+
+        struct
+        {
+            __IM uint32_t OUT12BIT_TS : 12; /*!< [11..0] OUT12BIT_TS                                                       */
+            uint32_t                  : 20;
+        } SCRR_b;
+    };
+
+    union
+    {
+        __IM uint32_t SSR;             /*!< (@ 0x00000014) Sensor Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t CONV : 1;    /*!< [0..0] CONV                                                               */
+            uint32_t           : 31;
+        } SSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMSR;            /*!< (@ 0x00000018) Compare Mode Setting Register                              */
+
+        struct
+        {
+            __IOM uint32_t CMPEN   : 1; /*!< [0..0] CMPEN                                                              */
+            __IOM uint32_t CMPCOND : 1; /*!< [1..1] CMPCOND                                                            */
+            uint32_t               : 30;
+        } CMSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LLSR;           /*!< (@ 0x0000001C) Lower Limit Setting Register                               */
+
+        struct
+        {
+            __IOM uint32_t LLIM : 12;  /*!< [11..0] LLIM                                                              */
+            uint32_t            : 20;
+        } LLSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ULSR;           /*!< (@ 0x00000020) Upper Limit Setting Register                               */
+
+        struct
+        {
+            __IOM uint32_t ULIM : 12;  /*!< [11..0] ULIM                                                              */
+            uint32_t            : 20;
+        } ULSR_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IM uint32_t SISR;            /*!< (@ 0x00000030) Sensor Interrupt Status Register                           */
+
+        struct
+        {
+            __IM uint32_t ADF  : 1;    /*!< [0..0] AD Conversion Complete Flag                                        */
+            __IM uint32_t CMPF : 1;    /*!< [1..1] Compare Result Flag                                                */
+            uint32_t           : 30;
+        } SISR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SIER;           /*!< (@ 0x00000034) Sensor Interrupt Enable Register                           */
+
+        struct
+        {
+            __IOM uint32_t ADIE  : 1;  /*!< [0..0] ADIE                                                               */
+            __IOM uint32_t CMPIE : 1;  /*!< [1..1] CMPIE                                                              */
+            uint32_t             : 30;
+        } SIER_b;
+    };
+
+    union
+    {
+        __OM uint32_t SICR;            /*!< (@ 0x00000038) Sensor Interrupt Clear Register                            */
+
+        struct
+        {
+            __OM uint32_t ADCLR  : 1;  /*!< [0..0] ADCLR                                                              */
+            __OM uint32_t CMPCLR : 1;  /*!< [1..1] CMPCLR                                                             */
+            uint32_t             : 30;
+        } SICR_b;
+    };
+} R_TSU_B0_Type;                       /*!< Size = 60 (0x3c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG1                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief GPT Port Output Enable 1 (R_POEG1)
+ */
+
+typedef struct                         /*!< (@ 0x80087000) R_POEG1 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t POEG1GA0;       /*!< (@ 0x00000000) POEG1 Group A Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG1GA0_b;
+    };
+    __IM uint32_t RESERVED[255];
+
+    union
+    {
+        __IOM uint32_t POEG1GB0;       /*!< (@ 0x00000400) POEG1 Group B Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG1GB0_b;
+    };
+    __IM uint32_t RESERVED1[255];
+
+    union
+    {
+        __IOM uint32_t POEG1GC0;       /*!< (@ 0x00000800) POEG1 Group C Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG1GC0_b;
+    };
+    __IM uint32_t RESERVED2[255];
+
+    union
+    {
+        __IOM uint32_t POEG1GD0;       /*!< (@ 0x00000C00) POEG1 Group D Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG1GD0_b;
+    };
+} R_POEG1_Type;                        /*!< Size = 3076 (0xc04)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I2C Bus Interface 0 (R_IIC0)
+ */
+
+typedef struct                         /*!< (@ 0x80088000) R_IIC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
+
+        struct
+        {
+            __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
+            __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
+            __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
+            __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
+            __OM uint8_t  SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
+            __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
+            __IOM uint8_t IICRST : 1;  /*!< [6..6] IIC-Bus Interface Internal Reset                                   */
+            __IOM uint8_t ICE    : 1;  /*!< [7..7] IIC-Bus Interface Enable                                           */
+        } ICCR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
+
+        struct
+        {
+            uint8_t            : 1;
+            __IOM uint8_t ST   : 1;    /*!< [1..1] Start Condition Issuance Request                                   */
+            __IOM uint8_t RS   : 1;    /*!< [2..2] Restart Condition Issuance Request                                 */
+            __IOM uint8_t SP   : 1;    /*!< [3..3] Stop Condition Issuance Request                                    */
+            uint8_t            : 1;
+            __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
+            __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
+            __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
+        } ICCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
+
+        struct
+        {
+            __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
+            __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect                                                   */
+            __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock Select                                    */
+            __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
+        } ICMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
+
+        struct
+        {
+            __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
+            __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
+            __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
+            uint8_t            : 1;
+            __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
+            __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
+        } ICMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
+
+        struct
+        {
+            __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Select                                          */
+            __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
+            __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
+            __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
+            __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Select                                        */
+            __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAIT                                                               */
+            __IOM uint8_t SMBS  : 1;   /*!< [7..7] SMBus/IIC-Bus Select                                               */
+        } ICMR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
+
+        struct
+        {
+            __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
+            __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
+            __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
+            __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
+            __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
+            __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
+            __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
+            uint8_t             : 1;
+        } ICFER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
+
+        struct
+        {
+            __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
+            __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
+            __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
+            __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
+            uint8_t             : 1;
+            __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device ID Address Detection Enable                                 */
+            uint8_t             : 1;
+            __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
+        } ICSER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
+
+        struct
+        {
+            __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
+            __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
+            __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
+            __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
+            __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
+            __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
+            __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
+            __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
+        } ICIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
+
+        struct
+        {
+            __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
+            __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
+            __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
+            __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
+            uint8_t            : 1;
+            __IOM uint8_t DID  : 1;    /*!< [5..5] Device ID Address Detection Flag                                   */
+            uint8_t            : 1;
+            __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
+        } ICSR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
+
+        struct
+        {
+            __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
+            __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
+            __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
+            __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
+            __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
+            __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
+            __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
+            __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
+        } ICSR2_b;
+    };
+    __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
+
+    union
+    {
+        __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
+
+        struct
+        {
+            __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period                                          */
+            uint8_t           : 3;
+        } ICBRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
+
+        struct
+        {
+            __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period                                         */
+            uint8_t           : 3;
+        } ICBRH_b;
+    };
+    __IOM uint8_t ICDRT;               /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
+    __IM uint8_t  ICDRR;               /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
+} R_IIC0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller 0 (R_DMAC0)
+ */
+
+typedef struct                         /*!< (@ 0x800C0000) R_DMAC0 Structure                                          */
+{
+    __IOM R_DMAC0_GRP_Type GRP[2];     /*!< (@ 0x00000000) 8 channel Registers                                        */
+} R_DMAC0_Type;                        /*!< Size = 2048 (0x800)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_GMAC0 (R_GMAC0)
+ */
+
+typedef struct                            /*!< (@ 0x80100000) R_GMAC0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t MAC_Configuration; /*!< (@ 0x00000000) MAC_Configuration                                          */
+
+        struct
+        {
+            __IOM uint32_t RE     : 1;    /*!< [0..0] RE                                                                 */
+            __IOM uint32_t TE     : 1;    /*!< [1..1] TE                                                                 */
+            __IOM uint32_t PRELEN : 2;    /*!< [3..2] PRELEN                                                             */
+            __IOM uint32_t DC     : 1;    /*!< [4..4] DC                                                                 */
+            __IOM uint32_t BL     : 2;    /*!< [6..5] BL                                                                 */
+            uint32_t              : 1;
+            __IOM uint32_t DR     : 1;    /*!< [8..8] DR                                                                 */
+            __IOM uint32_t DCRS   : 1;    /*!< [9..9] DCRS                                                               */
+            __IOM uint32_t DO     : 1;    /*!< [10..10] DO                                                               */
+            __IOM uint32_t ECRSFD : 1;    /*!< [11..11] ECRSFD                                                           */
+            __IOM uint32_t LM     : 1;    /*!< [12..12] LM                                                               */
+            __IOM uint32_t DM     : 1;    /*!< [13..13] DM                                                               */
+            __IOM uint32_t FES    : 1;    /*!< [14..14] FES                                                              */
+            __IOM uint32_t PS     : 1;    /*!< [15..15] PS                                                               */
+            __IOM uint32_t JE     : 1;    /*!< [16..16] JE                                                               */
+            __IOM uint32_t JD     : 1;    /*!< [17..17] JD                                                               */
+            __IOM uint32_t BE     : 1;    /*!< [18..18] BE                                                               */
+            __IOM uint32_t WD     : 1;    /*!< [19..19] WD                                                               */
+            __IOM uint32_t ACS    : 1;    /*!< [20..20] ACS                                                              */
+            __IOM uint32_t CST    : 1;    /*!< [21..21] CST                                                              */
+            __IOM uint32_t S2KP   : 1;    /*!< [22..22] S2KP                                                             */
+            __IOM uint32_t GPSLCE : 1;    /*!< [23..23] GPSLCE                                                           */
+            __IOM uint32_t IPG    : 3;    /*!< [26..24] IPG                                                              */
+            __IOM uint32_t IPC    : 1;    /*!< [27..27] IPC                                                              */
+            uint32_t              : 3;
+            __IOM uint32_t ARPEN  : 1;    /*!< [31..31] ARPEN                                                            */
+        } MAC_Configuration_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Ext_Configuration; /*!< (@ 0x00000004) MAC_Ext_Configuration                                      */
+
+        struct
+        {
+            __IOM uint32_t GPSL   : 14;       /*!< [13..0] GPSL                                                              */
+            uint32_t              : 2;
+            __IOM uint32_t DCRCC  : 1;        /*!< [16..16] DCRCC                                                            */
+            __IOM uint32_t SPEN   : 1;        /*!< [17..17] SPEN                                                             */
+            __IOM uint32_t USP    : 1;        /*!< [18..18] USP                                                              */
+            __IOM uint32_t PDC    : 1;        /*!< [19..19] PDC                                                              */
+            __IOM uint32_t HDSMS  : 3;        /*!< [22..20] HDSMS                                                            */
+            uint32_t              : 1;
+            __IOM uint32_t EIPGEN : 1;        /*!< [24..24] EIPGEN                                                           */
+            __IOM uint32_t EIPG   : 5;        /*!< [29..25] EIPG                                                             */
+            __IOM uint32_t APDIM  : 1;        /*!< [30..30] APDIM                                                            */
+            uint32_t              : 1;
+        } MAC_Ext_Configuration_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Packet_Filter; /*!< (@ 0x00000008) MAC_Packet_Filter                                          */
+
+        struct
+        {
+            __IOM uint32_t PR   : 1;      /*!< [0..0] PR                                                                 */
+            __IOM uint32_t HUC  : 1;      /*!< [1..1] HUC                                                                */
+            __IOM uint32_t HMC  : 1;      /*!< [2..2] HMC                                                                */
+            __IOM uint32_t DAIF : 1;      /*!< [3..3] DAIF                                                               */
+            __IOM uint32_t PM   : 1;      /*!< [4..4] PM                                                                 */
+            __IOM uint32_t DBF  : 1;      /*!< [5..5] DBF                                                                */
+            __IOM uint32_t PCF  : 2;      /*!< [7..6] PCF                                                                */
+            __IOM uint32_t SAIF : 1;      /*!< [8..8] SAIF                                                               */
+            __IOM uint32_t SAF  : 1;      /*!< [9..9] SAF                                                                */
+            __IOM uint32_t HPF  : 1;      /*!< [10..10] HPF                                                              */
+            uint32_t            : 5;
+            __IOM uint32_t VTFE : 1;      /*!< [16..16] VTFE                                                             */
+            uint32_t            : 3;
+            __IOM uint32_t IPFE : 1;      /*!< [20..20] IPFE                                                             */
+            __IOM uint32_t DNTU : 1;      /*!< [21..21] DNTU                                                             */
+            uint32_t            : 9;
+            __IOM uint32_t RA   : 1;      /*!< [31..31] RA                                                               */
+        } MAC_Packet_Filter_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Watchdog_Timeout; /*!< (@ 0x0000000C) MAC_Watchdog_Timeout                                       */
+
+        struct
+        {
+            __IOM uint32_t WTO : 4;          /*!< [3..0] WTO                                                                */
+            uint32_t           : 4;
+            __IOM uint32_t PWE : 1;          /*!< [8..8] PWE                                                                */
+            uint32_t           : 23;
+        } MAC_Watchdog_Timeout_b;
+    };
+
+    struct
+    {
+        union
+        {
+            __IOM uint32_t MAC_HASH_TABLE_REG; /*!< (@ 0x00000010) 0                                                    */
+
+            struct
+            {
+                __IOM uint32_t HT : 32;        /*!< [31..0] HT                                                          */
+            } MAC_HASH_TABLE_REG_b;
+        };
+    }             MAC_HASH_TABLE_REG[8];
+    __IM uint32_t RESERVED[8];
+
+    union
+    {
+        __IOM uint32_t MAC_VLAN_Tag_Ctrl; /*!< (@ 0x00000050) MAC_VLAN_Tag_Ctrl                                          */
+
+        struct
+        {
+            __IOM uint32_t OB      : 1;   /*!< [0..0] OB                                                                 */
+            __IOM uint32_t CT      : 1;   /*!< [1..1] CT                                                                 */
+            __IOM uint32_t OFS     : 4;   /*!< [5..2] OFS                                                                */
+            uint32_t               : 10;
+            __IOM uint32_t ETV     : 1;   /*!< [16..16] ETV                                                              */
+            __IOM uint32_t VTIM    : 1;   /*!< [17..17] VTIM                                                             */
+            __IOM uint32_t ESVL    : 1;   /*!< [18..18] ESVL                                                             */
+            __IOM uint32_t ERSVLM  : 1;   /*!< [19..19] ERSVLM                                                           */
+            __IOM uint32_t DOVLTC  : 1;   /*!< [20..20] DOVLTC                                                           */
+            __IOM uint32_t EVLS    : 2;   /*!< [22..21] EVLS                                                             */
+            uint32_t               : 1;
+            __IOM uint32_t EVLRXS  : 1;   /*!< [24..24] EVLRXS                                                           */
+            __IOM uint32_t VTHM    : 1;   /*!< [25..25] VTHM                                                             */
+            __IOM uint32_t EDVLP   : 1;   /*!< [26..26] EDVLP                                                            */
+            __IOM uint32_t ERIVLT  : 1;   /*!< [27..27] ERIVLT                                                           */
+            __IOM uint32_t EIVLS   : 2;   /*!< [29..28] EIVLS                                                            */
+            uint32_t               : 1;
+            __IOM uint32_t EIVLRXS : 1;   /*!< [31..31] EIVLRXS                                                          */
+        } MAC_VLAN_Tag_Ctrl_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_VLAN_Tag_Data; /*!< (@ 0x00000054) MAC_VLAN_Tag_Data                                          */
+
+        struct
+        {
+            __IOM uint32_t VID     : 16;  /*!< [15..0] VID                                                               */
+            __IOM uint32_t VEN     : 1;   /*!< [16..16] VEN                                                              */
+            __IOM uint32_t ETV     : 1;   /*!< [17..17] ETV                                                              */
+            __IOM uint32_t DOVLTC  : 1;   /*!< [18..18] DOVLTC                                                           */
+            __IOM uint32_t ERSVLM  : 1;   /*!< [19..19] ERSVLM                                                           */
+            __IOM uint32_t RIVLT   : 1;   /*!< [20..20] RIVLT                                                            */
+            uint32_t               : 3;
+            __IOM uint32_t DMACHEN : 1;   /*!< [24..24] DMACHEN                                                          */
+            __IOM uint32_t DMACHN  : 3;   /*!< [27..25] DMACHN                                                           */
+            uint32_t               : 4;
+        } MAC_VLAN_Tag_Data_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_VLAN_Hash_Table; /*!< (@ 0x00000058) MAC_VLAN_Hash_Table                                        */
+
+        struct
+        {
+            __IOM uint32_t VLHT : 16;       /*!< [15..0] VLHT                                                              */
+            uint32_t            : 16;
+        } MAC_VLAN_Hash_Table_b;
+    };
+    __IM uint32_t RESERVED1[5];
+
+    union
+    {
+        __IOM uint32_t MAC_Q0_Tx_Flow_Ctrl; /*!< (@ 0x00000070) MAC_Q0_Tx_Flow_Ctrl                                        */
+
+        struct
+        {
+            __IOM uint32_t FCB_BPA : 1;     /*!< [0..0] FCB_BPA                                                            */
+            __IOM uint32_t TFE     : 1;     /*!< [1..1] TFE                                                                */
+            uint32_t               : 2;
+            __IOM uint32_t PLT     : 3;     /*!< [6..4] PLT                                                                */
+            __IOM uint32_t DZPQ    : 1;     /*!< [7..7] DZPQ                                                               */
+            uint32_t               : 8;
+            __IOM uint32_t PT      : 16;    /*!< [31..16] PT                                                               */
+        } MAC_Q0_Tx_Flow_Ctrl_b;
+    };
+    __IM uint32_t RESERVED2[7];
+
+    union
+    {
+        __IOM uint32_t MAC_Rx_Flow_Ctrl; /*!< (@ 0x00000090) MAC_Rx_Flow_Ctrl                                           */
+
+        struct
+        {
+            __IOM uint32_t RFE : 1;      /*!< [0..0] RFE                                                                */
+            __IOM uint32_t UP  : 1;      /*!< [1..1] UP                                                                 */
+            uint32_t           : 30;
+        } MAC_Rx_Flow_Ctrl_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_RxQ_Ctrl4;  /*!< (@ 0x00000094) MAC_RxQ_Ctrl4                                              */
+
+        struct
+        {
+            __IOM uint32_t UFFQE : 1;  /*!< [0..0] UFFQE                                                              */
+            __IOM uint32_t UFFQ  : 3;  /*!< [3..1] UFFQ                                                               */
+            uint32_t             : 4;
+            __IOM uint32_t MFFQE : 1;  /*!< [8..8] MFFQE                                                              */
+            __IOM uint32_t MFFQ  : 3;  /*!< [11..9] MFFQ                                                              */
+            uint32_t             : 4;
+            __IOM uint32_t VFFQE : 1;  /*!< [16..16] VFFQE                                                            */
+            __IOM uint32_t VFFQ  : 3;  /*!< [19..17] VFFQ                                                             */
+            uint32_t             : 12;
+        } MAC_RxQ_Ctrl4_b;
+    };
+    __IM uint32_t RESERVED3[2];
+
+    union
+    {
+        __IOM uint32_t MAC_RxQ_Ctrl0;  /*!< (@ 0x000000A0) MAC_RxQ_Ctrl0                                              */
+
+        struct
+        {
+            __IOM uint32_t RXQ0EN : 2; /*!< [1..0] RXQ0EN                                                             */
+            __IOM uint32_t RXQ1EN : 2; /*!< [3..2] RXQ1EN                                                             */
+            __IOM uint32_t RXQ2EN : 2; /*!< [5..4] RXQ2EN                                                             */
+            __IOM uint32_t RXQ3EN : 2; /*!< [7..6] RXQ3EN                                                             */
+            __IOM uint32_t RXQ4EN : 2; /*!< [9..8] RXQ4EN                                                             */
+            __IOM uint32_t RXQ5EN : 2; /*!< [11..10] RXQ5EN                                                           */
+            __IOM uint32_t RXQ6EN : 2; /*!< [13..12] RXQ6EN                                                           */
+            __IOM uint32_t RXQ7EN : 2; /*!< [15..14] RXQ7EN                                                           */
+            uint32_t              : 16;
+        } MAC_RxQ_Ctrl0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_RxQ_Ctrl1;   /*!< (@ 0x000000A4) MAC_RxQ_Ctrl1                                              */
+
+        struct
+        {
+            __IOM uint32_t AVCPQ   : 3; /*!< [2..0] AVCPQ                                                              */
+            uint32_t               : 1;
+            __IOM uint32_t PTPQ    : 3; /*!< [6..4] PTPQ                                                               */
+            uint32_t               : 5;
+            __IOM uint32_t UPQ     : 3; /*!< [14..12] UPQ                                                              */
+            uint32_t               : 1;
+            __IOM uint32_t MCBCQ   : 3; /*!< [18..16] MCBCQ                                                            */
+            uint32_t               : 1;
+            __IOM uint32_t MCBCQEN : 1; /*!< [20..20] MCBCQEN                                                          */
+            __IOM uint32_t TACPQE  : 1; /*!< [21..21] TACPQE                                                           */
+            __IOM uint32_t TPQC    : 2; /*!< [23..22] TPQC                                                             */
+            __IOM uint32_t FPRQ    : 3; /*!< [26..24] FPRQ                                                             */
+            uint32_t               : 1;
+            __IOM uint32_t OMCBCQ  : 1; /*!< [28..28] OMCBCQ                                                           */
+            __IOM uint32_t TBRQE   : 1; /*!< [29..29] TBRQE                                                            */
+            uint32_t               : 2;
+        } MAC_RxQ_Ctrl1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_RxQ_Ctrl2;  /*!< (@ 0x000000A8) MAC_RxQ_Ctrl2                                              */
+
+        struct
+        {
+            __IOM uint32_t PSRQ0 : 8;  /*!< [7..0] PSRQ0                                                              */
+            __IOM uint32_t PSRQ1 : 8;  /*!< [15..8] PSRQ1                                                             */
+            __IOM uint32_t PSRQ2 : 8;  /*!< [23..16] PSRQ2                                                            */
+            __IOM uint32_t PSRQ3 : 8;  /*!< [31..24] PSRQ3                                                            */
+        } MAC_RxQ_Ctrl2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_RxQ_Ctrl3;  /*!< (@ 0x000000AC) MAC_RxQ_Ctrl3                                              */
+
+        struct
+        {
+            __IOM uint32_t PSRQ4 : 8;  /*!< [7..0] PSRQ4                                                              */
+            __IOM uint32_t PSRQ5 : 8;  /*!< [15..8] PSRQ5                                                             */
+            __IOM uint32_t PSRQ6 : 8;  /*!< [23..16] PSRQ6                                                            */
+            __IOM uint32_t PSRQ7 : 8;  /*!< [31..24] PSRQ7                                                            */
+        } MAC_RxQ_Ctrl3_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_Interrupt_Status; /*!< (@ 0x000000B0) MAC_Interrupt_Status                                       */
+
+        struct
+        {
+            uint32_t                : 4;
+            __IM uint32_t PMTIS     : 1; /*!< [4..4] PMTIS                                                              */
+            __IM uint32_t LPIIS     : 1; /*!< [5..5] LPIIS                                                              */
+            uint32_t                : 2;
+            __IM uint32_t MMCIS     : 1; /*!< [8..8] MMCIS                                                              */
+            __IM uint32_t MMCRXIS   : 1; /*!< [9..9] MMCRXIS                                                            */
+            __IM uint32_t MMCTXIS   : 1; /*!< [10..10] MMCTXIS                                                          */
+            __IM uint32_t MMCRXIPIS : 1; /*!< [11..11] MMCRXIPIS                                                        */
+            __IM uint32_t TSIS      : 1; /*!< [12..12] TSIS                                                             */
+            __IM uint32_t TXSTSIS   : 1; /*!< [13..13] TXSTSIS                                                          */
+            __IM uint32_t RXSTSIS   : 1; /*!< [14..14] RXSTSIS                                                          */
+            uint32_t                : 2;
+            __IM uint32_t FPEIS     : 1; /*!< [17..17] FPEIS                                                            */
+            __IM uint32_t MDIOIS    : 1; /*!< [18..18] MDIOIS                                                           */
+            __IM uint32_t MFTIS     : 1; /*!< [19..19] MFTIS                                                            */
+            __IM uint32_t MFRIS     : 1; /*!< [20..20] MFRIS                                                            */
+            uint32_t                : 11;
+        } MAC_Interrupt_Status_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Interrupt_Enable; /*!< (@ 0x000000B4) MAC_Interrupt_Enable                                       */
+
+        struct
+        {
+            uint32_t               : 3;
+            __IOM uint32_t PHYIE   : 1; /*!< [3..3] PHYIE                                                              */
+            __IOM uint32_t PMTIE   : 1; /*!< [4..4] PMTIE                                                              */
+            __IOM uint32_t LPIIE   : 1; /*!< [5..5] LPIIE                                                              */
+            uint32_t               : 6;
+            __IOM uint32_t TSIE    : 1; /*!< [12..12] TSIE                                                             */
+            __IOM uint32_t TXSTSIE : 1; /*!< [13..13] TXSTSIE                                                          */
+            __IOM uint32_t RXSTSIE : 1; /*!< [14..14] RXSTSIE                                                          */
+            uint32_t               : 2;
+            __IOM uint32_t FPEIE   : 1; /*!< [17..17] FPEIE                                                            */
+            __IOM uint32_t MDIOIE  : 1; /*!< [18..18] MDIOIE                                                           */
+            uint32_t               : 13;
+        } MAC_Interrupt_Enable_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_Rx_Tx_Status; /*!< (@ 0x000000B8) MAC_Rx_Tx_Status                                           */
+
+        struct
+        {
+            __IM uint32_t TJT   : 1;    /*!< [0..0] TJT                                                                */
+            __IM uint32_t NCARR : 1;    /*!< [1..1] NCARR                                                              */
+            __IM uint32_t LCARR : 1;    /*!< [2..2] LCARR                                                              */
+            __IM uint32_t EXDEF : 1;    /*!< [3..3] EXDEF                                                              */
+            __IM uint32_t LCOL  : 1;    /*!< [4..4] LCOL                                                               */
+            __IM uint32_t EXCOL : 1;    /*!< [5..5] EXCOL                                                              */
+            uint32_t            : 2;
+            __IM uint32_t RWT   : 1;    /*!< [8..8] RWT                                                                */
+            uint32_t            : 23;
+        } MAC_Rx_Tx_Status_b;
+    };
+    __IM uint32_t RESERVED4;
+
+    union
+    {
+        __IOM uint32_t MAC_PMT_Control_Status; /*!< (@ 0x000000C0) MAC_PMT_Control_Status                                     */
+
+        struct
+        {
+            __IOM uint32_t PWRDWN     : 1;     /*!< [0..0] PWRDWN                                                             */
+            __IOM uint32_t MGKPKTEN   : 1;     /*!< [1..1] MGKPKTEN                                                           */
+            __IOM uint32_t RWKPKTEN   : 1;     /*!< [2..2] RWKPKTEN                                                           */
+            uint32_t                  : 2;
+            __IM uint32_t MGKPRCVD    : 1;     /*!< [5..5] MGKPRCVD                                                           */
+            __IM uint32_t RWKPRCVD    : 1;     /*!< [6..6] RWKPRCVD                                                           */
+            uint32_t                  : 2;
+            __IOM uint32_t GLBLUCAST  : 1;     /*!< [9..9] GLBLUCAST                                                          */
+            __IOM uint32_t RWKPFE     : 1;     /*!< [10..10] RWKPFE                                                           */
+            uint32_t                  : 13;
+            __IM uint32_t RWKPTR      : 5;     /*!< [28..24] RWKPTR                                                           */
+            uint32_t                  : 2;
+            __IOM uint32_t RWKFILTRST : 1;     /*!< [31..31] RWKFILTRST                                                       */
+        } MAC_PMT_Control_Status_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_RWK_Packet_Filter; /*!< (@ 0x000000C4) MAC_RWK_Packet_Filter                                      */
+
+        struct
+        {
+            __IOM uint32_t WKUPFRMFTR : 32;   /*!< [31..0] WKUPFRMFTR                                                        */
+        } MAC_RWK_Packet_Filter_b;
+    };
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        __IOM uint32_t MAC_LPI_Control_Status; /*!< (@ 0x000000D0) MAC_LPI_Control_Status                                     */
+
+        struct
+        {
+            __IM uint32_t TLPIEN  : 1;         /*!< [0..0] TLPIEN                                                             */
+            __IM uint32_t TLPIEX  : 1;         /*!< [1..1] TLPIEX                                                             */
+            __IM uint32_t RLPIEN  : 1;         /*!< [2..2] RLPIEN                                                             */
+            __IM uint32_t RLPIEX  : 1;         /*!< [3..3] RLPIEX                                                             */
+            uint32_t              : 4;
+            __IM uint32_t TLPIST  : 1;         /*!< [8..8] TLPIST                                                             */
+            __IM uint32_t RLPIST  : 1;         /*!< [9..9] RLPIST                                                             */
+            uint32_t              : 6;
+            __IOM uint32_t LPIEN  : 1;         /*!< [16..16] LPIEN                                                            */
+            __IOM uint32_t PLS    : 1;         /*!< [17..17] PLS                                                              */
+            uint32_t              : 1;
+            __IOM uint32_t LPITXA : 1;         /*!< [19..19] LPITXA                                                           */
+            __IOM uint32_t LPIATE : 1;         /*!< [20..20] LPIATE                                                           */
+            uint32_t              : 11;
+        } MAC_LPI_Control_Status_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_LPI_Timers_Control; /*!< (@ 0x000000D4) MAC_LPI_Timers_Control                                     */
+
+        struct
+        {
+            __IOM uint32_t TWT : 16;           /*!< [15..0] TWT                                                               */
+            __IOM uint32_t LST : 10;           /*!< [25..16] LST                                                              */
+            uint32_t           : 6;
+        } MAC_LPI_Timers_Control_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_LPI_Entry_Timer; /*!< (@ 0x000000D8) MAC_LPI_Entry_Timer                                        */
+
+        struct
+        {
+            uint32_t             : 3;
+            __IOM uint32_t LPIET : 17; /*!< [19..3] LPIET                                                             */
+            uint32_t             : 12;
+        } MAC_LPI_Entry_Timer_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_1US_Tic_Counter;   /*!< (@ 0x000000DC) MAC_1US_Tic_Counter                                        */
+
+        struct
+        {
+            __IOM uint32_t TIC_1US_CNTR : 12; /*!< [11..0] TIC_1US_CNTR                                                      */
+            uint32_t                    : 20;
+        } MAC_1US_Tic_Counter_b;
+    };
+    __IM uint32_t RESERVED6[12];
+
+    union
+    {
+        __IM uint32_t MAC_Version;     /*!< (@ 0x00000110) MAC_Version                                                */
+
+        struct
+        {
+            __IM uint32_t VER : 16;    /*!< [15..0] VER                                                               */
+            uint32_t          : 16;
+        } MAC_Version_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_Debug;        /*!< (@ 0x00000114) MAC_Debug                                                  */
+
+        struct
+        {
+            __IM uint32_t RPESTS   : 1; /*!< [0..0] RPESTS                                                             */
+            __IM uint32_t RFCFCSTS : 2; /*!< [2..1] RFCFCSTS                                                           */
+            uint32_t               : 13;
+            __IM uint32_t TPESTS   : 1; /*!< [16..16] TPESTS                                                           */
+            __IM uint32_t TFCSTS   : 2; /*!< [18..17] TFCSTS                                                           */
+            uint32_t               : 13;
+        } MAC_Debug_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IM uint32_t MAC_HW_Feature0;      /*!< (@ 0x0000011C) MAC_HW_Feature0                                            */
+
+        struct
+        {
+            __IM uint32_t MIISEL       : 1; /*!< [0..0] MIISEL                                                             */
+            __IM uint32_t GMIISEL      : 1; /*!< [1..1] GMIISEL                                                            */
+            __IM uint32_t HDSEL        : 1; /*!< [2..2] HDSEL                                                              */
+            uint32_t                   : 1;
+            __IM uint32_t VLHASH       : 1; /*!< [4..4] VLHASH                                                             */
+            __IM uint32_t SMASEL       : 1; /*!< [5..5] SMASEL                                                             */
+            __IM uint32_t RWKSEL       : 1; /*!< [6..6] RWKSEL                                                             */
+            __IM uint32_t MGKSEL       : 1; /*!< [7..7] MGKSEL                                                             */
+            __IM uint32_t MMCSEL       : 1; /*!< [8..8] MMCSEL                                                             */
+            __IM uint32_t ARPOFFSEL    : 1; /*!< [9..9] ARPOFFSEL                                                          */
+            uint32_t                   : 2;
+            __IM uint32_t TSSEL        : 1; /*!< [12..12] TSSEL                                                            */
+            __IM uint32_t EEESEL       : 1; /*!< [13..13] EEESEL                                                           */
+            __IM uint32_t TXCOESEL     : 1; /*!< [14..14] TXCOESEL                                                         */
+            uint32_t                   : 1;
+            __IM uint32_t RXCOESEL     : 1; /*!< [16..16] RXCOESEL                                                         */
+            uint32_t                   : 1;
+            __IM uint32_t ADDMACADRSEL : 5; /*!< [22..18] ADDMACADRSEL                                                     */
+            uint32_t                   : 2;
+            __IM uint32_t TSSTSSEL     : 2; /*!< [26..25] TSSTSSEL                                                         */
+            uint32_t                   : 5;
+        } MAC_HW_Feature0_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_HW_Feature1;    /*!< (@ 0x00000120) MAC_HW_Feature1                                            */
+
+        struct
+        {
+            __IM uint32_t RXFIFOSIZE : 5; /*!< [4..0] RXFIFOSIZE                                                         */
+            uint32_t                 : 1;
+            __IM uint32_t TXFIFOSIZE : 5; /*!< [10..6] TXFIFOSIZE                                                        */
+            __IM uint32_t OSTEN      : 1; /*!< [11..11] OSTEN                                                            */
+            __IM uint32_t PTOEN      : 1; /*!< [12..12] PTOEN                                                            */
+            uint32_t                 : 1;
+            __IM uint32_t ADDR64     : 2; /*!< [15..14] ADDR64                                                           */
+            uint32_t                 : 1;
+            __IM uint32_t SPHEN      : 1; /*!< [17..17] SPHEN                                                            */
+            uint32_t                 : 2;
+            __IM uint32_t AVSEL      : 1; /*!< [20..20] AVSEL                                                            */
+            uint32_t                 : 2;
+            __IM uint32_t POUOST     : 1; /*!< [23..23] POUOST                                                           */
+            __IM uint32_t HASHTBLSZ  : 2; /*!< [25..24] HASHTBLSZ                                                        */
+            uint32_t                 : 1;
+            __IM uint32_t L3L4FNUM   : 4; /*!< [30..27] L3L4FNUM                                                         */
+            uint32_t                 : 1;
+        } MAC_HW_Feature1_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_HW_Feature2;    /*!< (@ 0x00000124) MAC_HW_Feature2                                            */
+
+        struct
+        {
+            __IM uint32_t RXQCNT     : 4; /*!< [3..0] RXQCNT                                                             */
+            uint32_t                 : 2;
+            __IM uint32_t TXQCNT     : 4; /*!< [9..6] TXQCNT                                                             */
+            uint32_t                 : 2;
+            __IM uint32_t RXCHCNT    : 4; /*!< [15..12] RXCHCNT                                                          */
+            uint32_t                 : 2;
+            __IM uint32_t TXCHCNT    : 4; /*!< [21..18] TXCHCNT                                                          */
+            uint32_t                 : 6;
+            __IM uint32_t AUXSNAPNUM : 3; /*!< [30..28] AUXSNAPNUM                                                       */
+            uint32_t                 : 1;
+        } MAC_HW_Feature2_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_HW_Feature3; /*!< (@ 0x00000128) MAC_HW_Feature3                                            */
+
+        struct
+        {
+            __IM uint32_t NRVF    : 3; /*!< [2..0] NRVF                                                               */
+            uint32_t              : 2;
+            __IM uint32_t DVLAN   : 1; /*!< [5..5] DVLAN                                                              */
+            uint32_t              : 3;
+            __IM uint32_t PDUPSEL : 1; /*!< [9..9] PDUPSEL                                                            */
+            uint32_t              : 6;
+            __IM uint32_t ESTSEL  : 1; /*!< [16..16] ESTSEL                                                           */
+            __IM uint32_t ESTDEP  : 3; /*!< [19..17] ESTDEP                                                           */
+            __IM uint32_t ESTWID  : 2; /*!< [21..20] ESTWID                                                           */
+            uint32_t              : 4;
+            __IM uint32_t FPESEL  : 1; /*!< [26..26] FPESEL                                                           */
+            __IM uint32_t TBSSEL  : 1; /*!< [27..27] TBSSEL                                                           */
+            uint32_t              : 4;
+        } MAC_HW_Feature3_b;
+    };
+    __IM uint32_t RESERVED8[53];
+
+    union
+    {
+        __IOM uint32_t MAC_MDIO_Address; /*!< (@ 0x00000200) MAC_MDIO_Address                                           */
+
+        struct
+        {
+            __IOM uint32_t GB   : 1;     /*!< [0..0] GB                                                                 */
+            __IOM uint32_t C45E : 1;     /*!< [1..1] C45E                                                               */
+            __IOM uint32_t GOC  : 2;     /*!< [3..2] GOC                                                                */
+            __IOM uint32_t SKAP : 1;     /*!< [4..4] SKAP                                                               */
+            uint32_t            : 3;
+            __IOM uint32_t CR   : 4;     /*!< [11..8] CR                                                                */
+            __IOM uint32_t NTC  : 3;     /*!< [14..12] NTC                                                              */
+            uint32_t            : 1;
+            __IOM uint32_t RDA  : 5;     /*!< [20..16] RDA                                                              */
+            __IOM uint32_t PA   : 5;     /*!< [25..21] PA                                                               */
+            __IOM uint32_t BTB  : 1;     /*!< [26..26] BTB                                                              */
+            __IOM uint32_t PSE  : 1;     /*!< [27..27] PSE                                                              */
+            uint32_t            : 4;
+        } MAC_MDIO_Address_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_MDIO_Data;  /*!< (@ 0x00000204) MAC_MDIO_Data                                              */
+
+        struct
+        {
+            __IOM uint32_t GD : 16;    /*!< [15..0] GD                                                                */
+            __IOM uint32_t RA : 16;    /*!< [31..16] RA                                                               */
+        } MAC_MDIO_Data_b;
+    };
+    __IM uint32_t RESERVED9[2];
+
+    union
+    {
+        __IOM uint32_t MAC_ARP_Address; /*!< (@ 0x00000210) MAC_ARP_Address                                            */
+
+        struct
+        {
+            __IOM uint32_t ARPPA : 32;  /*!< [31..0] ARPPA                                                             */
+        } MAC_ARP_Address_b;
+    };
+    __IM uint32_t RESERVED10[7];
+
+    union
+    {
+        __IOM uint32_t MAC_CSR_SW_Ctrl; /*!< (@ 0x00000230) MAC_CSR_SW_Ctrl                                            */
+
+        struct
+        {
+            __IOM uint32_t RCWE : 1;    /*!< [0..0] RCWE                                                               */
+            uint32_t            : 7;
+            __IOM uint32_t SEEN : 1;    /*!< [8..8] SEEN                                                               */
+            uint32_t            : 23;
+        } MAC_CSR_SW_Ctrl_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_FPE_CTRL_STS; /*!< (@ 0x00000234) MAC_FPE_CTRL_STS                                           */
+
+        struct
+        {
+            __IOM uint32_t EFPE     : 1; /*!< [0..0] EFPE                                                               */
+            __IOM uint32_t SVER     : 1; /*!< [1..1] SVER                                                               */
+            __IOM uint32_t SRSP     : 1; /*!< [2..2] SRSP                                                               */
+            __IOM uint32_t S1_SET_0 : 1; /*!< [3..3] S1_SET_0                                                           */
+            uint32_t                : 12;
+            __IOM uint32_t RVER     : 1; /*!< [16..16] RVER                                                             */
+            __IOM uint32_t RRSP     : 1; /*!< [17..17] RRSP                                                             */
+            __IOM uint32_t TVER     : 1; /*!< [18..18] TVER                                                             */
+            __IOM uint32_t TRSP     : 1; /*!< [19..19] TRSP                                                             */
+            uint32_t                : 12;
+        } MAC_FPE_CTRL_STS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Ext_Cfg1;    /*!< (@ 0x00000238) MAC_Ext_Cfg1                                               */
+
+        struct
+        {
+            __IOM uint32_t SPLOFST : 7; /*!< [6..0] SPLOFST                                                            */
+            uint32_t               : 1;
+            __IOM uint32_t SPLM    : 2; /*!< [9..8] SPLM                                                               */
+            uint32_t               : 6;
+            __IOM uint32_t SAVO    : 7; /*!< [22..16] SAVO                                                             */
+            uint32_t               : 1;
+            __IOM uint32_t SAVE    : 1; /*!< [24..24] SAVE                                                             */
+            uint32_t               : 7;
+        } MAC_Ext_Cfg1_b;
+    };
+    __IM uint32_t RESERVED11[49];
+
+    struct
+    {
+        union
+        {
+            __IOM uint32_t MAC_ADDRESS_HIGH; /*!< (@ 0x00000300) MAC_ADDRESS_HIGH                                   */
+
+            struct
+            {
+                __IOM uint32_t ADDRHI : 16;  /*!< [15..0] ADDRHI                                                    */
+                __IOM uint32_t DCS    : 8;   /*!< [23..16] DCS                                                      */
+                __IOM uint32_t MBC    : 6;   /*!< [29..24] MBC                                                      */
+                __IOM uint32_t SA     : 1;   /*!< [30..30] SA                                                       */
+                __IOM uint32_t AE     : 1;   /*!< [31..31] AE                                                       */
+            } MAC_ADDRESS_HIGH_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MAC_ADDRESS_LOW; /*!< (@ 0x00000304) MAC_ADDRESS_LOW                                    */
+
+            struct
+            {
+                __IOM uint32_t ADDRL : 32;  /*!< [31..0] ADDRL                                                     */
+            } MAC_ADDRESS_LOW_b;
+        };
+    }             MAC_Addr[32];
+    __IM uint32_t RESERVED12[192];
+
+    union
+    {
+        __IOM uint32_t MMC_Control;        /*!< (@ 0x00000700) MMC_Control                                                */
+
+        struct
+        {
+            __IOM uint32_t CNTRST     : 1; /*!< [0..0] CNTRST                                                             */
+            __IOM uint32_t CNTSTOPRO  : 1; /*!< [1..1] CNTSTOPRO                                                          */
+            __IOM uint32_t RSTONRD    : 1; /*!< [2..2] RSTONRD                                                            */
+            __IOM uint32_t CNTFREEZ   : 1; /*!< [3..3] CNTFREEZ                                                           */
+            __IOM uint32_t CNTPRST    : 1; /*!< [4..4] CNTPRST                                                            */
+            __IOM uint32_t CNTPRSTLVL : 1; /*!< [5..5] CNTPRSTLVL                                                         */
+            uint32_t                  : 2;
+            __IOM uint32_t UCDBC      : 1; /*!< [8..8] UCDBC                                                              */
+            uint32_t                  : 23;
+        } MMC_Control_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Rx_Interrupt;           /*!< (@ 0x00000704) MMC_Rx_Interrupt                                           */
+
+        struct
+        {
+            __IM uint32_t RXGBPKTIS          : 1; /*!< [0..0] RXGBPKTIS                                                          */
+            __IM uint32_t RXGBOCTIS          : 1; /*!< [1..1] RXGBOCTIS                                                          */
+            __IM uint32_t RXGOCTIS           : 1; /*!< [2..2] RXGOCTIS                                                           */
+            __IM uint32_t RXBCGPIS           : 1; /*!< [3..3] RXBCGPIS                                                           */
+            __IM uint32_t RXMCGPIS           : 1; /*!< [4..4] RXMCGPIS                                                           */
+            __IM uint32_t RXCRCERPIS         : 1; /*!< [5..5] RXCRCERPIS                                                         */
+            __IM uint32_t RXALGNERPIS        : 1; /*!< [6..6] RXALGNERPIS                                                        */
+            __IM uint32_t RXRUNTPIS          : 1; /*!< [7..7] RXRUNTPIS                                                          */
+            __IM uint32_t RXJABERPIS         : 1; /*!< [8..8] RXJABERPIS                                                         */
+            __IM uint32_t RXUSIZEGPIS        : 1; /*!< [9..9] RXUSIZEGPIS                                                        */
+            __IM uint32_t RXOSIZEGPIS        : 1; /*!< [10..10] RXOSIZEGPIS                                                      */
+            __IM uint32_t RX64OCTGBPIS       : 1; /*!< [11..11] RX64OCTGBPIS                                                     */
+            __IM uint32_t RX65T127OCTGBPIS   : 1; /*!< [12..12] RX65T127OCTGBPIS                                                 */
+            __IM uint32_t RX128T255OCTGBPIS  : 1; /*!< [13..13] RX128T255OCTGBPIS                                                */
+            __IM uint32_t RX256T511OCTGBPIS  : 1; /*!< [14..14] RX256T511OCTGBPIS                                                */
+            __IM uint32_t RX512T1023OCTGBPIS : 1; /*!< [15..15] RX512T1023OCTGBPIS                                               */
+            __IM uint32_t RX1024TMAXOCTGBPIS : 1; /*!< [16..16] RX1024TMAXOCTGBPIS                                               */
+            __IM uint32_t RXUCGPIS           : 1; /*!< [17..17] RXUCGPIS                                                         */
+            __IM uint32_t RXLENERPIS         : 1; /*!< [18..18] RXLENERPIS                                                       */
+            __IM uint32_t RXORANGEPIS        : 1; /*!< [19..19] RXORANGEPIS                                                      */
+            __IM uint32_t RXPAUSPIS          : 1; /*!< [20..20] RXPAUSPIS                                                        */
+            __IM uint32_t RXFOVPIS           : 1; /*!< [21..21] RXFOVPIS                                                         */
+            __IM uint32_t RXVLANGBPIS        : 1; /*!< [22..22] RXVLANGBPIS                                                      */
+            __IM uint32_t RXWDOGPIS          : 1; /*!< [23..23] RXWDOGPIS                                                        */
+            __IM uint32_t RXRCVERRPIS        : 1; /*!< [24..24] RXRCVERRPIS                                                      */
+            __IM uint32_t RXCTRLPIS          : 1; /*!< [25..25] RXCTRLPIS                                                        */
+            __IM uint32_t RXLPIUSCIS         : 1; /*!< [26..26] RXLPIUSCIS                                                       */
+            __IM uint32_t RXLPITRCIS         : 1; /*!< [27..27] RXLPITRCIS                                                       */
+            uint32_t                         : 4;
+        } MMC_Rx_Interrupt_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Tx_Interrupt;           /*!< (@ 0x00000708) MMC_Tx_Interrupt                                           */
+
+        struct
+        {
+            __IM uint32_t TXGBOCTIS          : 1; /*!< [0..0] TXGBOCTIS                                                          */
+            __IM uint32_t TXGBPKTIS          : 1; /*!< [1..1] TXGBPKTIS                                                          */
+            __IM uint32_t TXBCGPIS           : 1; /*!< [2..2] TXBCGPIS                                                           */
+            __IM uint32_t TXMCGPIS           : 1; /*!< [3..3] TXMCGPIS                                                           */
+            __IM uint32_t TX64OCTGBPIS       : 1; /*!< [4..4] TX64OCTGBPIS                                                       */
+            __IM uint32_t TX65T127OCTGBPIS   : 1; /*!< [5..5] TX65T127OCTGBPIS                                                   */
+            __IM uint32_t TX128T255OCTGBPIS  : 1; /*!< [6..6] TX128T255OCTGBPIS                                                  */
+            __IM uint32_t TX256T511OCTGBPIS  : 1; /*!< [7..7] TX256T511OCTGBPIS                                                  */
+            __IM uint32_t TX512T1023OCTGBPIS : 1; /*!< [8..8] TX512T1023OCTGBPIS                                                 */
+            __IM uint32_t TX1024TMAXOCTGBPIS : 1; /*!< [9..9] TX1024TMAXOCTGBPIS                                                 */
+            __IM uint32_t TXUCGBPIS          : 1; /*!< [10..10] TXUCGBPIS                                                        */
+            __IM uint32_t TXMCGBPIS          : 1; /*!< [11..11] TXMCGBPIS                                                        */
+            __IM uint32_t TXBCGBPIS          : 1; /*!< [12..12] TXBCGBPIS                                                        */
+            __IM uint32_t TXUFLOWERPIS       : 1; /*!< [13..13] TXUFLOWERPIS                                                     */
+            __IM uint32_t TXSCOLGPIS         : 1; /*!< [14..14] TXSCOLGPIS                                                       */
+            __IM uint32_t TXMCOLGPIS         : 1; /*!< [15..15] TXMCOLGPIS                                                       */
+            __IM uint32_t TXDEFPIS           : 1; /*!< [16..16] TXDEFPIS                                                         */
+            __IM uint32_t TXLATCOLPIS        : 1; /*!< [17..17] TXLATCOLPIS                                                      */
+            __IM uint32_t TXEXCOLPIS         : 1; /*!< [18..18] TXEXCOLPIS                                                       */
+            __IM uint32_t TXCARERPIS         : 1; /*!< [19..19] TXCARERPIS                                                       */
+            __IM uint32_t TXGOCTIS           : 1; /*!< [20..20] TXGOCTIS                                                         */
+            __IM uint32_t TXGPKTIS           : 1; /*!< [21..21] TXGPKTIS                                                         */
+            __IM uint32_t TXEXDEFPIS         : 1; /*!< [22..22] TXEXDEFPIS                                                       */
+            __IM uint32_t TXPAUSPIS          : 1; /*!< [23..23] TXPAUSPIS                                                        */
+            __IM uint32_t TXVLANGPIS         : 1; /*!< [24..24] TXVLANGPIS                                                       */
+            __IM uint32_t TXOSIZEGPIS        : 1; /*!< [25..25] TXOSIZEGPIS                                                      */
+            __IM uint32_t TXLPIUSCIS         : 1; /*!< [26..26] TXLPIUSCIS                                                       */
+            __IM uint32_t TXLPITRCIS         : 1; /*!< [27..27] TXLPITRCIS                                                       */
+            uint32_t                         : 4;
+        } MMC_Tx_Interrupt_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMC_Rx_Interrupt_Mask;      /*!< (@ 0x0000070C) MMC_Rx_Interrupt_Mask                                      */
+
+        struct
+        {
+            __IOM uint32_t RXGBPKTIM          : 1; /*!< [0..0] RXGBPKTIM                                                          */
+            __IOM uint32_t RXGBOCTIM          : 1; /*!< [1..1] RXGBOCTIM                                                          */
+            __IOM uint32_t RXGOCTIM           : 1; /*!< [2..2] RXGOCTIM                                                           */
+            __IOM uint32_t RXBCGPIM           : 1; /*!< [3..3] RXBCGPIM                                                           */
+            __IOM uint32_t RXMCGPIM           : 1; /*!< [4..4] RXMCGPIM                                                           */
+            __IOM uint32_t RXCRCERPIM         : 1; /*!< [5..5] RXCRCERPIM                                                         */
+            __IOM uint32_t RXALGNERPIM        : 1; /*!< [6..6] RXALGNERPIM                                                        */
+            __IOM uint32_t RXRUNTPIM          : 1; /*!< [7..7] RXRUNTPIM                                                          */
+            __IOM uint32_t RXJABERPIM         : 1; /*!< [8..8] RXJABERPIM                                                         */
+            __IOM uint32_t RXUSIZEGPIM        : 1; /*!< [9..9] RXUSIZEGPIM                                                        */
+            __IOM uint32_t RXOSIZEGPIM        : 1; /*!< [10..10] RXOSIZEGPIM                                                      */
+            __IOM uint32_t RX64OCTGBPIM       : 1; /*!< [11..11] RX64OCTGBPIM                                                     */
+            __IOM uint32_t RX65T127OCTGBPIM   : 1; /*!< [12..12] RX65T127OCTGBPIM                                                 */
+            __IOM uint32_t RX128T255OCTGBPIM  : 1; /*!< [13..13] RX128T255OCTGBPIM                                                */
+            __IOM uint32_t RX256T511OCTGBPIM  : 1; /*!< [14..14] RX256T511OCTGBPIM                                                */
+            __IOM uint32_t RX512T1023OCTGBPIM : 1; /*!< [15..15] RX512T1023OCTGBPIM                                               */
+            __IOM uint32_t RX1024TMAXOCTGBPIM : 1; /*!< [16..16] RX1024TMAXOCTGBPIM                                               */
+            __IOM uint32_t RXUCGPIM           : 1; /*!< [17..17] RXUCGPIM                                                         */
+            __IOM uint32_t RXLENERPIM         : 1; /*!< [18..18] RXLENERPIM                                                       */
+            __IOM uint32_t RXORANGEPIM        : 1; /*!< [19..19] RXORANGEPIM                                                      */
+            __IOM uint32_t RXPAUSPIM          : 1; /*!< [20..20] RXPAUSPIM                                                        */
+            __IOM uint32_t RXFOVPIM           : 1; /*!< [21..21] RXFOVPIM                                                         */
+            __IOM uint32_t RXVLANGBPIM        : 1; /*!< [22..22] RXVLANGBPIM                                                      */
+            __IOM uint32_t RXWDOGPIM          : 1; /*!< [23..23] RXWDOGPIM                                                        */
+            __IOM uint32_t RXRCVERRPIM        : 1; /*!< [24..24] RXRCVERRPIM                                                      */
+            __IOM uint32_t RXCTRLPIM          : 1; /*!< [25..25] RXCTRLPIM                                                        */
+            __IOM uint32_t RXLPIUSCIM         : 1; /*!< [26..26] RXLPIUSCIM                                                       */
+            __IOM uint32_t RXLPITRCIM         : 1; /*!< [27..27] RXLPITRCIM                                                       */
+            uint32_t                          : 4;
+        } MMC_Rx_Interrupt_Mask_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMC_Tx_Interrupt_Mask;      /*!< (@ 0x00000710) MMC_Tx_Interrupt_Mask                                      */
+
+        struct
+        {
+            __IOM uint32_t TXGBOCTIM          : 1; /*!< [0..0] TXGBOCTIM                                                          */
+            __IOM uint32_t TXGBPKTIM          : 1; /*!< [1..1] TXGBPKTIM                                                          */
+            __IOM uint32_t TXBCGPIM           : 1; /*!< [2..2] TXBCGPIM                                                           */
+            __IOM uint32_t TXMCGPIM           : 1; /*!< [3..3] TXMCGPIM                                                           */
+            __IOM uint32_t TX64OCTGBPIM       : 1; /*!< [4..4] TX64OCTGBPIM                                                       */
+            __IOM uint32_t TX65T127OCTGBPIM   : 1; /*!< [5..5] TX65T127OCTGBPIM                                                   */
+            __IOM uint32_t TX128T255OCTGBPIM  : 1; /*!< [6..6] TX128T255OCTGBPIM                                                  */
+            __IOM uint32_t TX256T511OCTGBPIM  : 1; /*!< [7..7] TX256T511OCTGBPIM                                                  */
+            __IOM uint32_t TX512T1023OCTGBPIM : 1; /*!< [8..8] TX512T1023OCTGBPIM                                                 */
+            __IOM uint32_t TX1024TMAXOCTGBPIM : 1; /*!< [9..9] TX1024TMAXOCTGBPIM                                                 */
+            __IOM uint32_t TXUCGBPIM          : 1; /*!< [10..10] TXUCGBPIM                                                        */
+            __IOM uint32_t TXMCGBPIM          : 1; /*!< [11..11] TXMCGBPIM                                                        */
+            __IOM uint32_t TXBCGBPIM          : 1; /*!< [12..12] TXBCGBPIM                                                        */
+            __IOM uint32_t TXUFLOWERPIM       : 1; /*!< [13..13] TXUFLOWERPIM                                                     */
+            __IOM uint32_t TXSCOLGPIM         : 1; /*!< [14..14] TXSCOLGPIM                                                       */
+            __IOM uint32_t TXMCOLGPIM         : 1; /*!< [15..15] TXMCOLGPIM                                                       */
+            __IOM uint32_t TXDEFPIM           : 1; /*!< [16..16] TXDEFPIM                                                         */
+            __IOM uint32_t TXLATCOLPIM        : 1; /*!< [17..17] TXLATCOLPIM                                                      */
+            __IOM uint32_t TXEXCOLPIM         : 1; /*!< [18..18] TXEXCOLPIM                                                       */
+            __IOM uint32_t TXCARERPIM         : 1; /*!< [19..19] TXCARERPIM                                                       */
+            __IOM uint32_t TXGOCTIM           : 1; /*!< [20..20] TXGOCTIM                                                         */
+            __IOM uint32_t TXGPKTIM           : 1; /*!< [21..21] TXGPKTIM                                                         */
+            __IOM uint32_t TXEXDEFPIM         : 1; /*!< [22..22] TXEXDEFPIM                                                       */
+            __IOM uint32_t TXPAUSPIM          : 1; /*!< [23..23] TXPAUSPIM                                                        */
+            __IOM uint32_t TXVLANGPIM         : 1; /*!< [24..24] TXVLANGPIM                                                       */
+            __IOM uint32_t TXOSIZEGPIM        : 1; /*!< [25..25] TXOSIZEGPIM                                                      */
+            __IOM uint32_t TXLPIUSCIM         : 1; /*!< [26..26] TXLPIUSCIM                                                       */
+            __IOM uint32_t TXLPITRCIM         : 1; /*!< [27..27] TXLPITRCIM                                                       */
+            uint32_t                          : 4;
+        } MMC_Tx_Interrupt_Mask_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Octet_Count_Good_Bad; /*!< (@ 0x00000714) Tx_Octet_Count_Good_Bad                                    */
+
+        struct
+        {
+            __IM uint32_t TXOCTGB : 32;        /*!< [31..0] TXOCTGB                                                           */
+        } Tx_Octet_Count_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Packet_Count_Good_Bad; /*!< (@ 0x00000718) Tx_Packet_Count_Good_Bad                                   */
+
+        struct
+        {
+            __IM uint32_t TXPKTGB : 32;         /*!< [31..0] TXPKTGB                                                           */
+        } Tx_Packet_Count_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Broadcast_Packets_Good; /*!< (@ 0x0000071C) Tx_Broadcast_Packets_Good                                  */
+
+        struct
+        {
+            __IM uint32_t TXBCASTG : 32;         /*!< [31..0] TXBCASTG                                                          */
+        } Tx_Broadcast_Packets_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Multicast_Packets_Good; /*!< (@ 0x00000720) Tx_Multicast_Packets_Good                                  */
+
+        struct
+        {
+            __IM uint32_t TXMCASTG : 32;         /*!< [31..0] TXMCASTG                                                          */
+        } Tx_Multicast_Packets_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_64Octets_Packets_Good_Bad; /*!< (@ 0x00000724) Tx_64Octets_Packets_Good_Bad                               */
+
+        struct
+        {
+            __IM uint32_t TX64OCTGB : 32;           /*!< [31..0] TX64OCTGB                                                         */
+        } Tx_64Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_65To127Octets_Packets_Good_Bad; /*!< (@ 0x00000728) Tx_65To127Octets_Packets_Good_Bad                     */
+
+        struct
+        {
+            __IM uint32_t TX65_127OCTGB : 32;            /*!< [31..0] TX65_127OCTGB                                                     */
+        } Tx_65To127Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_128To255Octets_Packets_Good_Bad; /*!< (@ 0x0000072C) Tx_128To255Octets_Packets_Good_Bad                   */
+
+        struct
+        {
+            __IM uint32_t TX128_255OCTGB : 32;            /*!< [31..0] TX128_255OCTGB                                                    */
+        } Tx_128To255Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_256To511Octets_Packets_Good_Bad; /*!< (@ 0x00000730) Tx_256To511Octets_Packets_Good_Bad                   */
+
+        struct
+        {
+            __IM uint32_t TX256_511OCTGB : 32;            /*!< [31..0] TX256_511OCTGB                                                    */
+        } Tx_256To511Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_512To1023Octets_Packets_Good_Bad; /*!< (@ 0x00000734) Tx_512To1023Octets_Packets_Good_Bad                 */
+
+        struct
+        {
+            __IM uint32_t TX512_1023OCTGB : 32;            /*!< [31..0] TX512_1023OCTGB                                                   */
+        } Tx_512To1023Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_1024ToMaxOctets_Packets_Good_Bad; /*!< (@ 0x00000738) Tx_1024ToMaxOctets_Packets_Good_Bad                 */
+
+        struct
+        {
+            __IM uint32_t TX1024_MAXOCTGB : 32;            /*!< [31..0] TX1024_MAXOCTGB                                                   */
+        } Tx_1024ToMaxOctets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Unicast_Packets_Good_Bad; /*!< (@ 0x0000073C) Tx_Unicast_Packets_Good_Bad                                */
+
+        struct
+        {
+            __IM uint32_t TXUCASTGB : 32;          /*!< [31..0] TXUCASTGB                                                         */
+        } Tx_Unicast_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Multicast_Packets_Good_Bad; /*!< (@ 0x00000740) Tx_Multicast_Packets_Good_Bad                             */
+
+        struct
+        {
+            __IM uint32_t TXMCASTGB : 32;            /*!< [31..0] TXMCASTGB                                                         */
+        } Tx_Multicast_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Broadcast_Packets_Good_Bad; /*!< (@ 0x00000744) Tx_Broadcast_Packets_Good_Bad                             */
+
+        struct
+        {
+            __IM uint32_t TXBCASTGB : 32;            /*!< [31..0] TXBCASTGB                                                         */
+        } Tx_Broadcast_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Underflow_Error_Packets; /*!< (@ 0x00000748) Tx_Underflow_Error_Packets                                 */
+
+        struct
+        {
+            __IM uint32_t TXUNDRFLW : 32;         /*!< [31..0] TXUNDRFLW                                                         */
+        } Tx_Underflow_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Single_Collision_Good_Packets; /*!< (@ 0x0000074C) Tx_Single_Collision_Good_Packets                       */
+
+        struct
+        {
+            __IM uint32_t TXSNGLCOLG : 32;              /*!< [31..0] TXSNGLCOLG                                                        */
+        } Tx_Single_Collision_Good_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Multiple_Collision_Good_Packets; /*!< (@ 0x00000750) Tx_Multiple_Collision_Good_Packets                   */
+
+        struct
+        {
+            __IM uint32_t TXMULTCOLG : 32;                /*!< [31..0] TXMULTCOLG                                                        */
+        } Tx_Multiple_Collision_Good_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Deferred_Packets; /*!< (@ 0x00000754) Tx_Deferred_Packets                                        */
+
+        struct
+        {
+            __IM uint32_t TXDEFRD : 32;    /*!< [31..0] TXDEFRD                                                           */
+        } Tx_Deferred_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Late_Collision_Packets; /*!< (@ 0x00000758) Tx_Late_Collision_Packets                                  */
+
+        struct
+        {
+            __IM uint32_t TXLATECOL : 32;        /*!< [31..0] TXLATECOL                                                         */
+        } Tx_Late_Collision_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Excessive_Collision_Packets; /*!< (@ 0x0000075C) Tx_Excessive_Collision_Packets                           */
+
+        struct
+        {
+            __IM uint32_t TXEXSCOL : 32;              /*!< [31..0] TXEXSCOL                                                          */
+        } Tx_Excessive_Collision_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Carrier_Error_Packets; /*!< (@ 0x00000760) Tx_Carrier_Error_Packets                                   */
+
+        struct
+        {
+            __IM uint32_t TXCARR : 32;          /*!< [31..0] TXCARR                                                            */
+        } Tx_Carrier_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Octet_Count_Good; /*!< (@ 0x00000764) Tx_Octet_Count_Good                                        */
+
+        struct
+        {
+            __IM uint32_t TXOCTG : 32;     /*!< [31..0] TXOCTG                                                            */
+        } Tx_Octet_Count_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Packet_Count_Good; /*!< (@ 0x00000768) Tx_Packet_Count_Good                                       */
+
+        struct
+        {
+            __IM uint32_t TXPKTG : 32;      /*!< [31..0] TXPKTG                                                            */
+        } Tx_Packet_Count_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Excessive_Deferral_Error; /*!< (@ 0x0000076C) Tx_Excessive_Deferral_Error                                */
+
+        struct
+        {
+            __IM uint32_t TXEXSDEF : 32;           /*!< [31..0] TXEXSDEF                                                          */
+        } Tx_Excessive_Deferral_Error_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_Pause_Packets; /*!< (@ 0x00000770) Tx_Pause_Packets                                           */
+
+        struct
+        {
+            __IM uint32_t TXPAUSE : 32; /*!< [31..0] TXPAUSE                                                           */
+        } Tx_Pause_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_VLAN_Packets_Good; /*!< (@ 0x00000774) Tx_VLAN_Packets_Good                                       */
+
+        struct
+        {
+            __IM uint32_t TXVLANG : 32;     /*!< [31..0] TXVLANG                                                           */
+        } Tx_VLAN_Packets_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_OSize_Packets_Good; /*!< (@ 0x00000778) Tx_OSize_Packets_Good                                      */
+
+        struct
+        {
+            __IM uint32_t TXOSIZG : 32;      /*!< [31..0] TXOSIZG                                                           */
+        } Tx_OSize_Packets_Good_b;
+    };
+    __IM uint32_t RESERVED13;
+
+    union
+    {
+        __IM uint32_t Rx_Packets_Count_Good_Bad; /*!< (@ 0x00000780) Rx_Packets_Count_Good_Bad                                  */
+
+        struct
+        {
+            __IM uint32_t RXPKTGB : 32;          /*!< [31..0] RXPKTGB                                                           */
+        } Rx_Packets_Count_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Octet_Count_Good_Bad; /*!< (@ 0x00000784) Rx_Octet_Count_Good_Bad                                    */
+
+        struct
+        {
+            __IM uint32_t RXOCTGB : 32;        /*!< [31..0] RXOCTGB                                                           */
+        } Rx_Octet_Count_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Octet_Count_Good; /*!< (@ 0x00000788) Rx_Octet_Count_Good                                        */
+
+        struct
+        {
+            __IM uint32_t RXOCTG : 32;     /*!< [31..0] RXOCTG                                                            */
+        } Rx_Octet_Count_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Broadcast_Packets_Good; /*!< (@ 0x0000078C) Rx_Broadcast_Packets_Good                                  */
+
+        struct
+        {
+            __IM uint32_t RXBCASTG : 32;         /*!< [31..0] RXBCASTG                                                          */
+        } Rx_Broadcast_Packets_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Multicast_Packets_Good; /*!< (@ 0x00000790) Rx_Multicast_Packets_Good                                  */
+
+        struct
+        {
+            __IM uint32_t RXMCASTG : 32;         /*!< [31..0] RXMCASTG                                                          */
+        } Rx_Multicast_Packets_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_CRC_Error_Packets; /*!< (@ 0x00000794) Rx_CRC_Error_Packets                                       */
+
+        struct
+        {
+            __IM uint32_t RXCRCERR : 32;    /*!< [31..0] RXCRCERR                                                          */
+        } Rx_CRC_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Alignment_Error_Packets; /*!< (@ 0x00000798) Rx_Alignment_Error_Packets                                 */
+
+        struct
+        {
+            __IM uint32_t RXALGNERR : 32;         /*!< [31..0] RXALGNERR                                                         */
+        } Rx_Alignment_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Runt_Error_Packets; /*!< (@ 0x0000079C) Rx_Runt_Error_Packets                                      */
+
+        struct
+        {
+            __IM uint32_t RXRUNTERR : 32;    /*!< [31..0] RXRUNTERR                                                         */
+        } Rx_Runt_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Jabber_Error_Packets; /*!< (@ 0x000007A0) Rx_Jabber_Error_Packets                                    */
+
+        struct
+        {
+            __IM uint32_t RXJABERR : 32;       /*!< [31..0] RXJABERR                                                          */
+        } Rx_Jabber_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Undersize_Packets_Good; /*!< (@ 0x000007A4) Rx_Undersize_Packets_Good                                  */
+
+        struct
+        {
+            __IM uint32_t RXUNDERSZG : 32;       /*!< [31..0] RXUNDERSZG                                                        */
+        } Rx_Undersize_Packets_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Oversize_Packets_Good; /*!< (@ 0x000007A8) Rx_Oversize_Packets_Good                                   */
+
+        struct
+        {
+            __IM uint32_t RXOVERSZG : 32;       /*!< [31..0] RXOVERSZG                                                         */
+        } Rx_Oversize_Packets_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_64Octets_Packets_Good_Bad; /*!< (@ 0x000007AC) Rx_64Octets_Packets_Good_Bad                               */
+
+        struct
+        {
+            __IM uint32_t RX64OCTGB : 32;           /*!< [31..0] RX64OCTGB                                                         */
+        } Rx_64Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_65To127Octets_Packets_Good_Bad; /*!< (@ 0x000007B0) Rx_65To127Octets_Packets_Good_Bad                     */
+
+        struct
+        {
+            __IM uint32_t RX65_127OCTGB : 32;            /*!< [31..0] RX65_127OCTGB                                                     */
+        } Rx_65To127Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_128To255Octets_Packets_Good_Bad; /*!< (@ 0x000007B4) Rx_128To255Octets_Packets_Good_Bad                   */
+
+        struct
+        {
+            __IM uint32_t RX128_255OCTGB : 32;            /*!< [31..0] RX128_255OCTGB                                                    */
+        } Rx_128To255Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_256To511Octets_Packets_Good_Bad; /*!< (@ 0x000007B8) Rx_256To511Octets_Packets_Good_Bad                   */
+
+        struct
+        {
+            __IM uint32_t RX256_511OCTGB : 32;            /*!< [31..0] RX256_511OCTGB                                                    */
+        } Rx_256To511Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_512To1023Octets_Packets_Good_Bad; /*!< (@ 0x000007BC) Rx_512To1023Octets_Packets_Good_Bad                 */
+
+        struct
+        {
+            __IM uint32_t RX512_1023OCTGB : 32;            /*!< [31..0] RX512_1023OCTGB                                                   */
+        } Rx_512To1023Octets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_1024ToMaxOctets_Packets_Good_Bad; /*!< (@ 0x000007C0) Rx_1024ToMaxOctets_Packets_Good_Bad                 */
+
+        struct
+        {
+            __IM uint32_t RX1024_MAXOCTGB : 32;            /*!< [31..0] RX1024_MAXOCTGB                                                   */
+        } Rx_1024ToMaxOctets_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Unicast_Packets_Good; /*!< (@ 0x000007C4) Rx_Unicast_Packets_Good                                    */
+
+        struct
+        {
+            __IM uint32_t RXUCASTG : 32;       /*!< [31..0] RXUCASTG                                                          */
+        } Rx_Unicast_Packets_Good_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Length_Error_Packets; /*!< (@ 0x000007C8) Rx_Length_Error_Packets                                    */
+
+        struct
+        {
+            __IM uint32_t RXLENERR : 32;       /*!< [31..0] RXLENERR                                                          */
+        } Rx_Length_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Out_Of_Range_Type_Packets; /*!< (@ 0x000007CC) Rx_Out_Of_Range_Type_Packets                               */
+
+        struct
+        {
+            __IM uint32_t RXOUTOFRNG : 32;          /*!< [31..0] RXOUTOFRNG                                                        */
+        } Rx_Out_Of_Range_Type_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Pause_Packets;    /*!< (@ 0x000007D0) Rx_Pause_Packets                                           */
+
+        struct
+        {
+            __IM uint32_t RXPAUSEPKT : 32; /*!< [31..0] RXPAUSEPKT                                                        */
+        } Rx_Pause_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_FIFO_Overflow_Packets; /*!< (@ 0x000007D4) Rx_FIFO_Overflow_Packets                                   */
+
+        struct
+        {
+            __IM uint32_t RXFIFOOVFL : 32;      /*!< [31..0] RXFIFOOVFL                                                        */
+        } Rx_FIFO_Overflow_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_VLAN_Packets_Good_Bad; /*!< (@ 0x000007D8) Rx_VLAN_Packets_Good_Bad                                   */
+
+        struct
+        {
+            __IM uint32_t RXVLANPKTGB : 32;     /*!< [31..0] RXVLANPKTGB                                                       */
+        } Rx_VLAN_Packets_Good_Bad_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Watchdog_Error_Packets; /*!< (@ 0x000007DC) Rx_Watchdog_Error_Packets                                  */
+
+        struct
+        {
+            __IM uint32_t RXWDGERR : 32;         /*!< [31..0] RXWDGERR                                                          */
+        } Rx_Watchdog_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Receive_Error_Packets; /*!< (@ 0x000007E0) Rx_Receive_Error_Packets                                   */
+
+        struct
+        {
+            __IM uint32_t RXRCVERR : 32;        /*!< [31..0] RXRCVERR                                                          */
+        } Rx_Receive_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_Control_Packets_Good; /*!< (@ 0x000007E4) Rx_Control_Packets_Good                                    */
+
+        struct
+        {
+            __IM uint32_t RXCTRLG : 32;        /*!< [31..0] RXCTRLG                                                           */
+        } Rx_Control_Packets_Good_b;
+    };
+    __IM uint32_t RESERVED14;
+
+    union
+    {
+        __IM uint32_t Tx_LPI_USEC_Cntr;  /*!< (@ 0x000007EC) Tx_LPI_USEC_Cntr                                           */
+
+        struct
+        {
+            __IM uint32_t TXLPIUSC : 32; /*!< [31..0] TXLPIUSC                                                          */
+        } Tx_LPI_USEC_Cntr_b;
+    };
+
+    union
+    {
+        __IM uint32_t Tx_LPI_Tran_Cntr;  /*!< (@ 0x000007F0) Tx_LPI_Tran_Cntr                                           */
+
+        struct
+        {
+            __IM uint32_t TXLPITRC : 32; /*!< [31..0] TXLPITRC                                                          */
+        } Tx_LPI_Tran_Cntr_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_LPI_USEC_Cntr;  /*!< (@ 0x000007F4) Rx_LPI_USEC_Cntr                                           */
+
+        struct
+        {
+            __IM uint32_t RXLPIUSC : 32; /*!< [31..0] RXLPIUSC                                                          */
+        } Rx_LPI_USEC_Cntr_b;
+    };
+
+    union
+    {
+        __IM uint32_t Rx_LPI_Tran_Cntr;  /*!< (@ 0x000007F8) Rx_LPI_Tran_Cntr                                           */
+
+        struct
+        {
+            __IM uint32_t RXLPITRC : 32; /*!< [31..0] RXLPITRC                                                          */
+        } Rx_LPI_Tran_Cntr_b;
+    };
+    __IM uint32_t RESERVED15;
+
+    union
+    {
+        __IOM uint32_t MMC_IPC_Rx_Interrupt_Mask; /*!< (@ 0x00000800) MMC_IPC_Rx_Interrupt_Mask                                  */
+
+        struct
+        {
+            __IOM uint32_t RXIPV4GPIM     : 1;    /*!< [0..0] RXIPV4GPIM                                                         */
+            __IOM uint32_t RXIPV4HERPIM   : 1;    /*!< [1..1] RXIPV4HERPIM                                                       */
+            __IOM uint32_t RXIPV4NOPAYPIM : 1;    /*!< [2..2] RXIPV4NOPAYPIM                                                     */
+            __IOM uint32_t RXIPV4FRAGPIM  : 1;    /*!< [3..3] RXIPV4FRAGPIM                                                      */
+            __IOM uint32_t RXIPV4UDSBLPIM : 1;    /*!< [4..4] RXIPV4UDSBLPIM                                                     */
+            __IOM uint32_t RXIPV6GPIM     : 1;    /*!< [5..5] RXIPV6GPIM                                                         */
+            __IOM uint32_t RXIPV6HERPIM   : 1;    /*!< [6..6] RXIPV6HERPIM                                                       */
+            __IOM uint32_t RXIPV6NOPAYPIM : 1;    /*!< [7..7] RXIPV6NOPAYPIM                                                     */
+            __IOM uint32_t RXUDPGPIM      : 1;    /*!< [8..8] RXUDPGPIM                                                          */
+            __IOM uint32_t RXUDPERPIM     : 1;    /*!< [9..9] RXUDPERPIM                                                         */
+            __IOM uint32_t RXTCPGPIM      : 1;    /*!< [10..10] RXTCPGPIM                                                        */
+            __IOM uint32_t RXTCPERPIM     : 1;    /*!< [11..11] RXTCPERPIM                                                       */
+            __IOM uint32_t RXICMPGPIM     : 1;    /*!< [12..12] RXICMPGPIM                                                       */
+            __IOM uint32_t RXICMPERPIM    : 1;    /*!< [13..13] RXICMPERPIM                                                      */
+            uint32_t                      : 2;
+            __IOM uint32_t RXIPV4GOIM     : 1;    /*!< [16..16] RXIPV4GOIM                                                       */
+            __IOM uint32_t RXIPV4HEROIM   : 1;    /*!< [17..17] RXIPV4HEROIM                                                     */
+            __IOM uint32_t RXIPV4NOPAYOIM : 1;    /*!< [18..18] RXIPV4NOPAYOIM                                                   */
+            __IOM uint32_t RXIPV4FRAGOIM  : 1;    /*!< [19..19] RXIPV4FRAGOIM                                                    */
+            __IOM uint32_t RXIPV4UDSBLOIM : 1;    /*!< [20..20] RXIPV4UDSBLOIM                                                   */
+            __IOM uint32_t RXIPV6GOIM     : 1;    /*!< [21..21] RXIPV6GOIM                                                       */
+            __IOM uint32_t RXIPV6HEROIM   : 1;    /*!< [22..22] RXIPV6HEROIM                                                     */
+            __IOM uint32_t RXIPV6NOPAYOIM : 1;    /*!< [23..23] RXIPV6NOPAYOIM                                                   */
+            __IOM uint32_t RXUDPGOIM      : 1;    /*!< [24..24] RXUDPGOIM                                                        */
+            __IOM uint32_t RXUDPEROIM     : 1;    /*!< [25..25] RXUDPEROIM                                                       */
+            __IOM uint32_t RXTCPGOIM      : 1;    /*!< [26..26] RXTCPGOIM                                                        */
+            __IOM uint32_t RXTCPEROIM     : 1;    /*!< [27..27] RXTCPEROIM                                                       */
+            __IOM uint32_t RXICMPGOIM     : 1;    /*!< [28..28] RXICMPGOIM                                                       */
+            __IOM uint32_t RXICMPEROIM    : 1;    /*!< [29..29] RXICMPEROIM                                                      */
+            uint32_t                      : 2;
+        } MMC_IPC_Rx_Interrupt_Mask_b;
+    };
+    __IM uint32_t RESERVED16;
+
+    union
+    {
+        __IM uint32_t MMC_IPC_Rx_Interrupt;   /*!< (@ 0x00000808) MMC_IPC_Rx_Interrupt                                       */
+
+        struct
+        {
+            __IM uint32_t RXIPV4GPIS     : 1; /*!< [0..0] RXIPV4GPIS                                                         */
+            __IM uint32_t RXIPV4HERPIS   : 1; /*!< [1..1] RXIPV4HERPIS                                                       */
+            __IM uint32_t RXIPV4NOPAYPIS : 1; /*!< [2..2] RXIPV4NOPAYPIS                                                     */
+            __IM uint32_t RXIPV4FRAGPIS  : 1; /*!< [3..3] RXIPV4FRAGPIS                                                      */
+            __IM uint32_t RXIPV4UDSBLPIS : 1; /*!< [4..4] RXIPV4UDSBLPIS                                                     */
+            __IM uint32_t RXIPV6GPIS     : 1; /*!< [5..5] RXIPV6GPIS                                                         */
+            __IM uint32_t RXIPV6HERPIS   : 1; /*!< [6..6] RXIPV6HERPIS                                                       */
+            __IM uint32_t RXIPV6NOPAYPIS : 1; /*!< [7..7] RXIPV6NOPAYPIS                                                     */
+            __IM uint32_t RXUDPGPIS      : 1; /*!< [8..8] RXUDPGPIS                                                          */
+            __IM uint32_t RXUDPERPIS     : 1; /*!< [9..9] RXUDPERPIS                                                         */
+            __IM uint32_t RXTCPGPIS      : 1; /*!< [10..10] RXTCPGPIS                                                        */
+            __IM uint32_t RXTCPERPIS     : 1; /*!< [11..11] RXTCPERPIS                                                       */
+            __IM uint32_t RXICMPGPIS     : 1; /*!< [12..12] RXICMPGPIS                                                       */
+            __IM uint32_t RXICMPERPIS    : 1; /*!< [13..13] RXICMPERPIS                                                      */
+            uint32_t                     : 2;
+            __IM uint32_t RXIPV4GOIS     : 1; /*!< [16..16] RXIPV4GOIS                                                       */
+            __IM uint32_t RXIPV4HEROIS   : 1; /*!< [17..17] RXIPV4HEROIS                                                     */
+            __IM uint32_t RXIPV4NOPAYOIS : 1; /*!< [18..18] RXIPV4NOPAYOIS                                                   */
+            __IM uint32_t RXIPV4FRAGOIS  : 1; /*!< [19..19] RXIPV4FRAGOIS                                                    */
+            __IM uint32_t RXIPV4UDSBLOIS : 1; /*!< [20..20] RXIPV4UDSBLOIS                                                   */
+            __IM uint32_t RXIPV6GOIS     : 1; /*!< [21..21] RXIPV6GOIS                                                       */
+            __IM uint32_t RXIPV6HEROIS   : 1; /*!< [22..22] RXIPV6HEROIS                                                     */
+            __IM uint32_t RXIPV6NOPAYOIS : 1; /*!< [23..23] RXIPV6NOPAYOIS                                                   */
+            __IM uint32_t RXUDPGOIS      : 1; /*!< [24..24] RXUDPGOIS                                                        */
+            __IM uint32_t RXUDPEROIS     : 1; /*!< [25..25] RXUDPEROIS                                                       */
+            __IM uint32_t RXTCPGOIS      : 1; /*!< [26..26] RXTCPGOIS                                                        */
+            __IM uint32_t RXTCPEROIS     : 1; /*!< [27..27] RXTCPEROIS                                                       */
+            __IM uint32_t RXICMPGOIS     : 1; /*!< [28..28] RXICMPGOIS                                                       */
+            __IM uint32_t RXICMPEROIS    : 1; /*!< [29..29] RXICMPEROIS                                                      */
+            uint32_t                     : 2;
+        } MMC_IPC_Rx_Interrupt_b;
+    };
+    __IM uint32_t RESERVED17;
+
+    union
+    {
+        __IM uint32_t RxIPv4_Good_Packets;  /*!< (@ 0x00000810) RxIPv4_Good_Packets                                        */
+
+        struct
+        {
+            __IM uint32_t RXIPV4GDPKT : 32; /*!< [31..0] RXIPV4GDPKT                                                       */
+        } RxIPv4_Good_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv4_Header_Error_Packets; /*!< (@ 0x00000814) RxIPv4_Header_Error_Packets                                */
+
+        struct
+        {
+            __IM uint32_t RXIPV4HDRERRPKT : 32;    /*!< [31..0] RXIPV4HDRERRPKT                                                   */
+        } RxIPv4_Header_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv4_No_Payload_Packets; /*!< (@ 0x00000818) RxIPv4_No_Payload_Packets                                  */
+
+        struct
+        {
+            __IM uint32_t RXIPV4NOPAYPKT : 32;   /*!< [31..0] RXIPV4NOPAYPKT                                                    */
+        } RxIPv4_No_Payload_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv4_Fragmented_Packets; /*!< (@ 0x0000081C) RxIPv4_Fragmented_Packets                                  */
+
+        struct
+        {
+            __IM uint32_t RXIPV4FRAGPKT : 32;    /*!< [31..0] RXIPV4FRAGPKT                                                     */
+        } RxIPv4_Fragmented_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv4_UDP_Checksum_Disabled_Packets; /*!< (@ 0x00000820) RxIPv4_UDP_Checksum_Disabled_Packets               */
+
+        struct
+        {
+            __IM uint32_t RXIPV4UDSBLPKT : 32;              /*!< [31..0] RXIPV4UDSBLPKT                                                    */
+        } RxIPv4_UDP_Checksum_Disabled_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv6_Good_Packets;  /*!< (@ 0x00000824) RxIPv6_Good_Packets                                        */
+
+        struct
+        {
+            __IM uint32_t RXIPV6GDPKT : 32; /*!< [31..0] RXIPV6GDPKT                                                       */
+        } RxIPv6_Good_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv6_Header_Error_Packets; /*!< (@ 0x00000828) RxIPv6_Header_Error_Packets                                */
+
+        struct
+        {
+            __IM uint32_t RXIPV6HDRERRPKT : 32;    /*!< [31..0] RXIPV6HDRERRPKT                                                   */
+        } RxIPv6_Header_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv6_No_Payload_Packets; /*!< (@ 0x0000082C) RxIPv6_No_Payload_Packets                                  */
+
+        struct
+        {
+            __IM uint32_t RXIPV6NOPAYPKT : 32;   /*!< [31..0] RXIPV6NOPAYPKT                                                    */
+        } RxIPv6_No_Payload_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxUDP_Good_Packets;  /*!< (@ 0x00000830) RxUDP_Good_Packets                                         */
+
+        struct
+        {
+            __IM uint32_t RXUDPGDPKT : 32; /*!< [31..0] RXUDPGDPKT                                                        */
+        } RxUDP_Good_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxUDP_Error_Packets;  /*!< (@ 0x00000834) RxUDP_Error_Packets                                        */
+
+        struct
+        {
+            __IM uint32_t RXUDPERRPKT : 32; /*!< [31..0] RXUDPERRPKT                                                       */
+        } RxUDP_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxTCP_Good_Packets;  /*!< (@ 0x00000838) RxTCP_Good_Packets                                         */
+
+        struct
+        {
+            __IM uint32_t RXTCPGDPKT : 32; /*!< [31..0] RXTCPGDPKT                                                        */
+        } RxTCP_Good_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxTCP_Error_Packets;  /*!< (@ 0x0000083C) RxTCP_Error_Packets                                        */
+
+        struct
+        {
+            __IM uint32_t RXTCPERRPKT : 32; /*!< [31..0] RXTCPERRPKT                                                       */
+        } RxTCP_Error_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxICMP_Good_Packets;  /*!< (@ 0x00000840) RxICMP_Good_Packets                                        */
+
+        struct
+        {
+            __IM uint32_t RXICMPGDPKT : 32; /*!< [31..0] RXICMPGDPKT                                                       */
+        } RxICMP_Good_Packets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxICMP_Error_Packets;  /*!< (@ 0x00000844) RxICMP_Error_Packets                                       */
+
+        struct
+        {
+            __IM uint32_t RXICMPERRPKT : 32; /*!< [31..0] RXICMPERRPKT                                                      */
+        } RxICMP_Error_Packets_b;
+    };
+    __IM uint32_t RESERVED18[2];
+
+    union
+    {
+        __IM uint32_t RxIPv4_Good_Octets;   /*!< (@ 0x00000850) RxIPv4_Good_Octets                                         */
+
+        struct
+        {
+            __IM uint32_t RXIPV4GDOCT : 32; /*!< [31..0] RXIPV4GDOCT                                                       */
+        } RxIPv4_Good_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv4_Header_Error_Octets; /*!< (@ 0x00000854) RxIPv4_Header_Error_Octets                                 */
+
+        struct
+        {
+            __IM uint32_t RXIPV4HDRERROCT : 32;   /*!< [31..0] RXIPV4HDRERROCT                                                   */
+        } RxIPv4_Header_Error_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv4_No_Payload_Octets; /*!< (@ 0x00000858) RxIPv4_No_Payload_Octets                                   */
+
+        struct
+        {
+            __IM uint32_t RXIPV4NOPAYOCT : 32;  /*!< [31..0] RXIPV4NOPAYOCT                                                    */
+        } RxIPv4_No_Payload_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv4_Fragmented_Octets; /*!< (@ 0x0000085C) RxIPv4_Fragmented_Octets                                   */
+
+        struct
+        {
+            __IM uint32_t RXIPV4FRAGOCT : 32;   /*!< [31..0] RXIPV4FRAGOCT                                                     */
+        } RxIPv4_Fragmented_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv4_UDP_Checksum_Disable_Octets; /*!< (@ 0x00000860) RxIPv4_UDP_Checksum_Disable_Octets                   */
+
+        struct
+        {
+            __IM uint32_t RXIPV4UDSBLOCT : 32;            /*!< [31..0] RXIPV4UDSBLOCT                                                    */
+        } RxIPv4_UDP_Checksum_Disable_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv6_Good_Octets;   /*!< (@ 0x00000864) RxIPv6_Good_Octets                                         */
+
+        struct
+        {
+            __IM uint32_t RXIPV6GDOCT : 32; /*!< [31..0] RXIPV6GDOCT                                                       */
+        } RxIPv6_Good_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv6_Header_Error_Octets; /*!< (@ 0x00000868) RxIPv6_Header_Error_Octets                                 */
+
+        struct
+        {
+            __IM uint32_t RXIPV6HDRERROCT : 32;   /*!< [31..0] RXIPV6HDRERROCT                                                   */
+        } RxIPv6_Header_Error_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxIPv6_No_Payload_Octets; /*!< (@ 0x0000086C) RxIPv6_No_Payload_Octets                                   */
+
+        struct
+        {
+            __IM uint32_t RXIPV6NOPAYOCT : 32;  /*!< [31..0] RXIPV6NOPAYOCT                                                    */
+        } RxIPv6_No_Payload_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxUDP_Good_Octets;   /*!< (@ 0x00000870) RxUDP_Good_Octets                                          */
+
+        struct
+        {
+            __IM uint32_t RXUDPGDOCT : 32; /*!< [31..0] RXUDPGDOCT                                                        */
+        } RxUDP_Good_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxUDP_Error_Octets;   /*!< (@ 0x00000874) RxUDP_Error_Octets                                         */
+
+        struct
+        {
+            __IM uint32_t RXUDPERROCT : 32; /*!< [31..0] RXUDPERROCT                                                       */
+        } RxUDP_Error_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxTCP_Good_Octets;   /*!< (@ 0x00000878) RxTCP_Good_Octets                                          */
+
+        struct
+        {
+            __IM uint32_t RXTCPGDOCT : 32; /*!< [31..0] RXTCPGDOCT                                                        */
+        } RxTCP_Good_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxTCP_Error_Octets;   /*!< (@ 0x0000087C) RxTCP_Error_Octets                                         */
+
+        struct
+        {
+            __IM uint32_t RXTCPERROCT : 32; /*!< [31..0] RXTCPERROCT                                                       */
+        } RxTCP_Error_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxICMP_Good_Octets;   /*!< (@ 0x00000880) RxICMP_Good_Octets                                         */
+
+        struct
+        {
+            __IM uint32_t RXICMPGDOCT : 32; /*!< [31..0] RXICMPGDOCT                                                       */
+        } RxICMP_Good_Octets_b;
+    };
+
+    union
+    {
+        __IM uint32_t RxICMP_Error_Octets;   /*!< (@ 0x00000884) RxICMP_Error_Octets                                        */
+
+        struct
+        {
+            __IM uint32_t RXICMPERROCT : 32; /*!< [31..0] RXICMPERROCT                                                      */
+        } RxICMP_Error_Octets_b;
+    };
+    __IM uint32_t RESERVED19[6];
+
+    union
+    {
+        __IM uint32_t MMC_FPE_Tx_Interrupt; /*!< (@ 0x000008A0) MMC_FPE_Tx_Interrupt                                       */
+
+        struct
+        {
+            __IM uint32_t FCIS  : 1;        /*!< [0..0] FCIS                                                               */
+            __IM uint32_t HRCIS : 1;        /*!< [1..1] HRCIS                                                              */
+            uint32_t            : 30;
+        } MMC_FPE_Tx_Interrupt_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMC_FPE_Tx_Interrupt_Mask; /*!< (@ 0x000008A4) MMC_FPE_Tx_Interrupt_Mask                                  */
+
+        struct
+        {
+            __IOM uint32_t FCIM  : 1;             /*!< [0..0] FCIM                                                               */
+            __IOM uint32_t HRCIM : 1;             /*!< [1..1] HRCIM                                                              */
+            uint32_t             : 30;
+        } MMC_FPE_Tx_Interrupt_Mask_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Tx_FPE_Fragment_Cntr; /*!< (@ 0x000008A8) MMC_Tx_FPE_Fragment_Cntr                                   */
+
+        struct
+        {
+            __IM uint32_t TXFFC : 32;           /*!< [31..0] TXFFC                                                             */
+        } MMC_Tx_FPE_Fragment_Cntr_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Tx_Hold_Req_Cntr; /*!< (@ 0x000008AC) MMC_Tx_Hold_Req_Cntr                                       */
+
+        struct
+        {
+            __IM uint32_t TXHRC : 32;       /*!< [31..0] TXHRC                                                             */
+        } MMC_Tx_Hold_Req_Cntr_b;
+    };
+    __IM uint32_t RESERVED20[4];
+
+    union
+    {
+        __IM uint32_t MMC_FPE_Rx_Interrupt; /*!< (@ 0x000008C0) MMC_FPE_Rx_Interrupt                                       */
+
+        struct
+        {
+            __IM uint32_t PAECIS : 1;       /*!< [0..0] PAECIS                                                             */
+            __IM uint32_t PSECIS : 1;       /*!< [1..1] PSECIS                                                             */
+            __IM uint32_t PAOCIS : 1;       /*!< [2..2] PAOCIS                                                             */
+            __IM uint32_t FCIS   : 1;       /*!< [3..3] FCIS                                                               */
+            uint32_t             : 28;
+        } MMC_FPE_Rx_Interrupt_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMC_FPE_Rx_Interrupt_Mask; /*!< (@ 0x000008C4) MMC_FPE_Rx_Interrupt_Mask                                  */
+
+        struct
+        {
+            __IOM uint32_t PAECIM : 1;            /*!< [0..0] PAECIM                                                             */
+            __IOM uint32_t PSECIM : 1;            /*!< [1..1] PSECIM                                                             */
+            __IOM uint32_t PAOCIM : 1;            /*!< [2..2] PAOCIM                                                             */
+            __IOM uint32_t FCIM   : 1;            /*!< [3..3] FCIM                                                               */
+            uint32_t              : 28;
+        } MMC_FPE_Rx_Interrupt_Mask_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Rx_Packet_Assembly_Err_Cntr; /*!< (@ 0x000008C8) MMC_Rx_Packet_Assembly_Err_Cntr                         */
+
+        struct
+        {
+            __IM uint32_t PAEC : 32;                   /*!< [31..0] PAEC                                                              */
+        } MMC_Rx_Packet_Assembly_Err_Cntr_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Rx_Packet_SMD_Err_Cntr; /*!< (@ 0x000008CC) MMC_Rx_Packet_SMD_Err_Cntr                                 */
+
+        struct
+        {
+            __IM uint32_t PSEC : 32;              /*!< [31..0] PSEC                                                              */
+        } MMC_Rx_Packet_SMD_Err_Cntr_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Rx_Packet_Assembly_OK_Cntr; /*!< (@ 0x000008D0) MMC_Rx_Packet_Assembly_OK_Cntr                           */
+
+        struct
+        {
+            __IM uint32_t PAOC : 32;                  /*!< [31..0] PAOC                                                              */
+        } MMC_Rx_Packet_Assembly_OK_Cntr_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMC_Rx_FPE_Fragment_Cntr; /*!< (@ 0x000008D4) MMC_Rx_FPE_Fragment_Cntr                                   */
+
+        struct
+        {
+            __IM uint32_t FFC : 32;             /*!< [31..0] FFC                                                               */
+        } MMC_Rx_FPE_Fragment_Cntr_b;
+    };
+    __IM uint32_t RESERVED21[6];
+
+    struct
+    {
+        __IM uint32_t RESERVED22[4];
+        union
+        {
+            __IOM uint32_t MAC_L3_L4_CONTROL; /*!< (@ 0x00000900) 0                                                          */
+
+            struct
+            {
+                __IOM uint32_t L3PEN0  : 1;   /*!< [0..0] L3PEN0                                                             */
+                uint32_t               : 1;
+                __IOM uint32_t L3SAM0  : 1;   /*!< [2..2] L3SAM0                                                             */
+                __IOM uint32_t L3SAIM0 : 1;   /*!< [3..3] L3SAIM0                                                            */
+                __IOM uint32_t L3DAM0  : 1;   /*!< [4..4] L3DAM0                                                             */
+                __IOM uint32_t L3DAIM0 : 1;   /*!< [5..5] L3DAIM0                                                            */
+                __IOM uint32_t L3HSBM0 : 5;   /*!< [10..6] L3HSBM0                                                           */
+                __IOM uint32_t L3HDBM0 : 5;   /*!< [15..11] L3HDBM0                                                          */
+                __IOM uint32_t L4PEN0  : 1;   /*!< [16..16] L4PEN0                                                           */
+                uint32_t               : 1;
+                __IOM uint32_t L4SPM0  : 1;   /*!< [18..18] L4SPM0                                                           */
+                __IOM uint32_t L4SPIM0 : 1;   /*!< [19..19] L4SPIM0                                                          */
+                __IOM uint32_t L4DPM0  : 1;   /*!< [20..20] L4DPM0                                                           */
+                __IOM uint32_t L4DPIM0 : 1;   /*!< [21..21] L4DPIM0                                                          */
+                uint32_t               : 2;
+                __IOM uint32_t DMCHN0  : 3;   /*!< [26..24] DMCHN0                                                           */
+                uint32_t               : 1;
+                __IOM uint32_t DMCHEN0 : 1;   /*!< [28..28] DMCHEN0                                                          */
+                uint32_t               : 3;
+            } MAC_L3_L4_CONTROL_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MAC_LAYER4_ADDRESS; /*!< (@ 0x00000904) 0                                                          */
+
+            struct
+            {
+                __IOM uint32_t L4SP0 : 16;     /*!< [15..0] L4SP0                                                             */
+                __IOM uint32_t L4DP0 : 16;     /*!< [31..16] L4DP0                                                            */
+            } MAC_LAYER4_ADDRESS_b;
+        };
+        __IM uint32_t RESERVED23[2];
+
+        union
+        {
+            __IOM uint32_t MAC_LAYER3_ADDR0_REG; /*!< (@ 0x00000910) 0                                                          */
+
+            struct
+            {
+                __IOM uint32_t L3A00 : 32;       /*!< [31..0] L3A00                                                             */
+            } MAC_LAYER3_ADDR0_REG_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MAC_LAYER3_ADDR1_REG; /*!< (@ 0x00000914) 0                                                          */
+
+            struct
+            {
+                __IOM uint32_t L3A10 : 32;       /*!< [31..0] L3A10                                                             */
+            } MAC_LAYER3_ADDR1_REG_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MAC_LAYER3_ADDR2_REG; /*!< (@ 0x00000918) 0                                                          */
+
+            struct
+            {
+                __IOM uint32_t L3A20 : 32;       /*!< [31..0] L3A20                                                             */
+            } MAC_LAYER3_ADDR2_REG_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MAC_LAYER3_ADDR3_REG; /*!< (@ 0x0000091C) 0                                                          */
+
+            struct
+            {
+                __IOM uint32_t L3A30 : 32;       /*!< [31..0] L3A30                                                             */
+            } MAC_LAYER3_ADDR3_REG_b;
+        };
+    } MAC_L[8];
+
+    union
+    {
+        __IOM uint32_t MAC_Indir_Access_Ctrl; /*!< (@ 0x00000A70) MAC_Indir_Access_Ctrl                                      */
+
+        struct
+        {
+            __IOM uint32_t OB   : 1;          /*!< [0..0] OB                                                                 */
+            __IOM uint32_t COM  : 1;          /*!< [1..1] COM                                                                */
+            uint32_t            : 3;
+            __IOM uint32_t AUTO : 1;          /*!< [5..5] AUTO                                                               */
+            uint32_t            : 2;
+            __IOM uint32_t AOFF : 8;          /*!< [15..8] AOFF                                                              */
+            __IOM uint32_t MSEL : 4;          /*!< [19..16] MSEL                                                             */
+            uint32_t            : 12;
+        } MAC_Indir_Access_Ctrl_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Indir_Access_Data; /*!< (@ 0x00000A74) MAC_Indir_Access_Data                                      */
+
+        struct
+        {
+            __IOM uint32_t DATA : 32;         /*!< [31..0] DATA                                                              */
+        } MAC_Indir_Access_Data_b;
+    };
+    __IM uint32_t RESERVED24[34];
+
+    union
+    {
+        __IOM uint32_t MAC_Timestamp_Control; /*!< (@ 0x00000B00) MAC_Timestamp_Control                                      */
+
+        struct
+        {
+            __IOM uint32_t TSENA       : 1;   /*!< [0..0] TSENA                                                              */
+            uint32_t                   : 3;
+            __IOM uint32_t TSTRIG      : 1;   /*!< [4..4] TSTRIG                                                             */
+            uint32_t                   : 3;
+            __IOM uint32_t TSENALL     : 1;   /*!< [8..8] TSENALL                                                            */
+            __IOM uint32_t TSCTRLSSR   : 1;   /*!< [9..9] TSCTRLSSR                                                          */
+            __IOM uint32_t TSVER2ENA   : 1;   /*!< [10..10] TSVER2ENA                                                        */
+            __IOM uint32_t TSIPENA     : 1;   /*!< [11..11] TSIPENA                                                          */
+            __IOM uint32_t TSIPV6ENA   : 1;   /*!< [12..12] TSIPV6ENA                                                        */
+            __IOM uint32_t TSIPV4ENA   : 1;   /*!< [13..13] TSIPV4ENA                                                        */
+            __IOM uint32_t TSEVNTENA   : 1;   /*!< [14..14] TSEVNTENA                                                        */
+            __IOM uint32_t TSMSTRENA   : 1;   /*!< [15..15] TSMSTRENA                                                        */
+            __IOM uint32_t SNAPTYPSEL  : 2;   /*!< [17..16] SNAPTYPSEL                                                       */
+            __IOM uint32_t TSENMACADDR : 1;   /*!< [18..18] TSENMACADDR                                                      */
+            __IOM uint32_t CSC         : 1;   /*!< [19..19] CSC                                                              */
+            uint32_t                   : 4;
+            __IOM uint32_t TXTSSTSM    : 1;   /*!< [24..24] TXTSSTSM                                                         */
+            uint32_t                   : 3;
+            __IOM uint32_t AV8021ASMEN : 1;   /*!< [28..28] AV8021ASMEN                                                      */
+            uint32_t                   : 3;
+        } MAC_Timestamp_Control_b;
+    };
+    __IM uint32_t RESERVED25;
+
+    union
+    {
+        __IM uint32_t MAC_System_Time_Seconds; /*!< (@ 0x00000B08) MAC_System_Time_Seconds                                    */
+
+        struct
+        {
+            __IM uint32_t TSS : 32;            /*!< [31..0] TSS                                                               */
+        } MAC_System_Time_Seconds_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_System_Time_Nanoseconds; /*!< (@ 0x00000B0C) MAC_System_Time_Nanoseconds                                */
+
+        struct
+        {
+            __IM uint32_t TSSS : 31;               /*!< [30..0] TSSS                                                              */
+            uint32_t           : 1;
+        } MAC_System_Time_Nanoseconds_b;
+    };
+    __IM uint32_t RESERVED26[4];
+
+    union
+    {
+        __IM uint32_t MAC_Timestamp_Status; /*!< (@ 0x00000B20) MAC_Timestamp_Status                                       */
+
+        struct
+        {
+            uint32_t                : 2;
+            __IM uint32_t AUXTSTRIG : 1; /*!< [2..2] AUXTSTRIG                                                          */
+            uint32_t                : 12;
+            __IM uint32_t TXTSSIS   : 1; /*!< [15..15] TXTSSIS                                                          */
+            __IM uint32_t ATSSTN    : 2; /*!< [17..16] ATSSTN                                                           */
+            uint32_t                : 6;
+            __IM uint32_t ATSSTM    : 1; /*!< [24..24] ATSSTM                                                           */
+            __IM uint32_t ATSNS     : 5; /*!< [29..25] ATSNS                                                            */
+            uint32_t                : 2;
+        } MAC_Timestamp_Status_b;
+    };
+    __IM uint32_t RESERVED27[3];
+
+    union
+    {
+        __IM uint32_t MAC_Tx_Timestamp_Status_Nanoseconds; /*!< (@ 0x00000B30) MAC_Tx_Timestamp_Status_Nanoseconds                 */
+
+        struct
+        {
+            __IM uint32_t TXTSSLO  : 31;                   /*!< [30..0] TXTSSLO                                                           */
+            __IM uint32_t TXTSSMIS : 1;                    /*!< [31..31] TXTSSMIS                                                         */
+        } MAC_Tx_Timestamp_Status_Nanoseconds_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_Tx_Timestamp_Status_Seconds; /*!< (@ 0x00000B34) MAC_Tx_Timestamp_Status_Seconds                         */
+
+        struct
+        {
+            __IM uint32_t TXTSSHI : 32;                /*!< [31..0] TXTSSHI                                                           */
+        } MAC_Tx_Timestamp_Status_Seconds_b;
+    };
+    __IM uint32_t RESERVED28[2];
+
+    union
+    {
+        __IOM uint32_t MAC_Auxiliary_Control; /*!< (@ 0x00000B40) MAC_Auxiliary_Control                                      */
+
+        struct
+        {
+            __IOM uint32_t ATSFC  : 1;        /*!< [0..0] ATSFC                                                              */
+            uint32_t              : 3;
+            __IOM uint32_t ATSEN0 : 1;        /*!< [4..4] ATSEN0                                                             */
+            __IOM uint32_t ATSEN1 : 1;        /*!< [5..5] ATSEN1                                                             */
+            uint32_t              : 26;
+        } MAC_Auxiliary_Control_b;
+    };
+    __IM uint32_t RESERVED29;
+
+    union
+    {
+        __IM uint32_t MAC_Auxiliary_Timestamp_Nanoseconds; /*!< (@ 0x00000B48) MAC_Auxiliary_Timestamp_Nanoseconds                 */
+
+        struct
+        {
+            __IM uint32_t AUXTSLO : 31;                    /*!< [30..0] AUXTSLO                                                           */
+            uint32_t              : 1;
+        } MAC_Auxiliary_Timestamp_Nanoseconds_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_Auxiliary_Timestamp_Seconds; /*!< (@ 0x00000B4C) MAC_Auxiliary_Timestamp_Seconds                         */
+
+        struct
+        {
+            __IM uint32_t AUXTSHI : 32;                /*!< [31..0] AUXTSHI                                                           */
+        } MAC_Auxiliary_Timestamp_Seconds_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Timestamp_Ingress_Asym_Corr; /*!< (@ 0x00000B50) MAC_Timestamp_Ingress_Asym_Corr                         */
+
+        struct
+        {
+            __IOM uint32_t OSTIAC : 32;                 /*!< [31..0] OSTIAC                                                            */
+        } MAC_Timestamp_Ingress_Asym_Corr_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Timestamp_Egress_Asym_Corr; /*!< (@ 0x00000B54) MAC_Timestamp_Egress_Asym_Corr                           */
+
+        struct
+        {
+            __IOM uint32_t OSTEAC : 32;                /*!< [31..0] OSTEAC                                                            */
+        } MAC_Timestamp_Egress_Asym_Corr_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Timestamp_Ingress_Corr_Nanosecond; /*!< (@ 0x00000B58) MAC_Timestamp_Ingress_Corr_Nanosecond             */
+
+        struct
+        {
+            __IOM uint32_t TSIC : 32;                         /*!< [31..0] TSIC                                                              */
+        } MAC_Timestamp_Ingress_Corr_Nanosecond_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Timestamp_Egress_Corr_Nanosecond; /*!< (@ 0x00000B5C) MAC_Timestamp_Egress_Corr_Nanosecond               */
+
+        struct
+        {
+            __IOM uint32_t TSEC : 32;                        /*!< [31..0] TSEC                                                              */
+        } MAC_Timestamp_Egress_Corr_Nanosecond_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Timestamp_Ingress_Corr_Subnanosec; /*!< (@ 0x00000B60) MAC_Timestamp_Ingress_Corr_Subnanosec             */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IOM uint32_t TSICSNS : 8; /*!< [15..8] TSICSNS                                                           */
+            uint32_t               : 16;
+        } MAC_Timestamp_Ingress_Corr_Subnanosec_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Timestamp_Egress_Corr_Subnanosec; /*!< (@ 0x00000B64) MAC_Timestamp_Egress_Corr_Subnanosec               */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IOM uint32_t TSECSNS : 8; /*!< [15..8] TSECSNS                                                           */
+            uint32_t               : 16;
+        } MAC_Timestamp_Egress_Corr_Subnanosec_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_Timestamp_Ingress_Latency; /*!< (@ 0x00000B68) MAC_Timestamp_Ingress_Latency                             */
+
+        struct
+        {
+            uint32_t             : 8;
+            __IM uint32_t ITLSNS : 8;  /*!< [15..8] ITLSNS                                                            */
+            __IM uint32_t ITLNS  : 12; /*!< [27..16] ITLNS                                                            */
+            uint32_t             : 4;
+        } MAC_Timestamp_Ingress_Latency_b;
+    };
+
+    union
+    {
+        __IM uint32_t MAC_Timestamp_Egress_Latency; /*!< (@ 0x00000B6C) MAC_Timestamp_Egress_Latency                               */
+
+        struct
+        {
+            uint32_t             : 8;
+            __IM uint32_t ETLSNS : 8;  /*!< [15..8] ETLSNS                                                            */
+            __IM uint32_t ETLNS  : 12; /*!< [27..16] ETLNS                                                            */
+            uint32_t             : 4;
+        } MAC_Timestamp_Egress_Latency_b;
+    };
+    __IM uint32_t RESERVED30[20];
+
+    union
+    {
+        __IOM uint32_t MAC_PTO_Control;    /*!< (@ 0x00000BC0) MAC_PTO_Control                                            */
+
+        struct
+        {
+            __IOM uint32_t PTOEN      : 1; /*!< [0..0] PTOEN                                                              */
+            __IOM uint32_t ASYNCEN    : 1; /*!< [1..1] ASYNCEN                                                            */
+            __IOM uint32_t APDREQEN   : 1; /*!< [2..2] APDREQEN                                                           */
+            uint32_t                  : 1;
+            __IOM uint32_t ASYNCTRIG  : 1; /*!< [4..4] ASYNCTRIG                                                          */
+            __IOM uint32_t APDREQTRIG : 1; /*!< [5..5] APDREQTRIG                                                         */
+            __IOM uint32_t DRRDIS     : 1; /*!< [6..6] DRRDIS                                                             */
+            __IOM uint32_t PDRDIS     : 1; /*!< [7..7] PDRDIS                                                             */
+            __IOM uint32_t DN         : 8; /*!< [15..8] DN                                                                */
+            uint32_t                  : 16;
+        } MAC_PTO_Control_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Source_Port_Identity0; /*!< (@ 0x00000BC4) MAC_Source_Port_Identity0                                  */
+
+        struct
+        {
+            __IOM uint32_t SPI0 : 32;             /*!< [31..0] SPI0                                                              */
+        } MAC_Source_Port_Identity0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Source_Port_Identity1; /*!< (@ 0x00000BC8) MAC_Source_Port_Identity1                                  */
+
+        struct
+        {
+            __IOM uint32_t SPI1 : 32;             /*!< [31..0] SPI1                                                              */
+        } MAC_Source_Port_Identity1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Source_Port_Identity2; /*!< (@ 0x00000BCC) MAC_Source_Port_Identity2                                  */
+
+        struct
+        {
+            __IOM uint32_t SPI2 : 16;             /*!< [15..0] SPI2                                                              */
+            uint32_t            : 16;
+        } MAC_Source_Port_Identity2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_Log_Message_Interval; /*!< (@ 0x00000BD0) MAC_Log_Message_Interval                                   */
+
+        struct
+        {
+            __IOM uint32_t LSI     : 8;          /*!< [7..0] LSI                                                                */
+            __IOM uint32_t DRSYNCR : 3;          /*!< [10..8] DRSYNCR                                                           */
+            uint32_t               : 13;
+            __IOM uint32_t LMPDRI  : 8;          /*!< [31..24] LMPDRI                                                           */
+        } MAC_Log_Message_Interval_b;
+    };
+    __IM uint32_t RESERVED31[11];
+
+    union
+    {
+        __IOM uint32_t MTL_Operation_Mode; /*!< (@ 0x00000C00) MTL_Operation_Mode                                         */
+
+        struct
+        {
+            uint32_t               : 1;
+            __IOM uint32_t DTXSTS  : 1; /*!< [1..1] DTXSTS                                                             */
+            __IOM uint32_t RAA     : 1; /*!< [2..2] RAA                                                                */
+            uint32_t               : 2;
+            __IOM uint32_t SCHALG  : 2; /*!< [6..5] SCHALG                                                             */
+            uint32_t               : 1;
+            __IOM uint32_t CNTPRST : 1; /*!< [8..8] CNTPRST                                                            */
+            __IOM uint32_t CNTCLR  : 1; /*!< [9..9] CNTCLR                                                             */
+            uint32_t               : 22;
+        } MTL_Operation_Mode_b;
+    };
+    __IM uint32_t RESERVED32[7];
+
+    union
+    {
+        __IM uint32_t MTL_Interrupt_Status; /*!< (@ 0x00000C20) MTL_Interrupt_Status                                       */
+
+        struct
+        {
+            __IM uint32_t Q0IS  : 1;        /*!< [0..0] Q0IS                                                               */
+            __IM uint32_t Q1IS  : 1;        /*!< [1..1] Q1IS                                                               */
+            __IM uint32_t Q2IS  : 1;        /*!< [2..2] Q2IS                                                               */
+            __IM uint32_t Q3IS  : 1;        /*!< [3..3] Q3IS                                                               */
+            __IM uint32_t Q4IS  : 1;        /*!< [4..4] Q4IS                                                               */
+            __IM uint32_t Q5IS  : 1;        /*!< [5..5] Q5IS                                                               */
+            __IM uint32_t Q6IS  : 1;        /*!< [6..6] Q6IS                                                               */
+            __IM uint32_t Q7IS  : 1;        /*!< [7..7] Q7IS                                                               */
+            uint32_t            : 10;
+            __IM uint32_t ESTIS : 1;        /*!< [18..18] ESTIS                                                            */
+            uint32_t            : 13;
+        } MTL_Interrupt_Status_b;
+    };
+    __IM uint32_t RESERVED33[3];
+
+    union
+    {
+        __IOM uint32_t MTL_RxQ_DMA_Map0; /*!< (@ 0x00000C30) MTL_RxQ_DMA_Map0                                           */
+
+        struct
+        {
+            __IOM uint32_t Q0MDMACH : 3; /*!< [2..0] Q0MDMACH                                                           */
+            uint32_t                : 1;
+            __IOM uint32_t Q0DDMACH : 1; /*!< [4..4] Q0DDMACH                                                           */
+            uint32_t                : 3;
+            __IOM uint32_t Q1MDMACH : 3; /*!< [10..8] Q1MDMACH                                                          */
+            uint32_t                : 1;
+            __IOM uint32_t Q1DDMACH : 1; /*!< [12..12] Q1DDMACH                                                         */
+            uint32_t                : 3;
+            __IOM uint32_t Q2MDMACH : 3; /*!< [18..16] Q2MDMACH                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t Q2DDMACH : 1; /*!< [20..20] Q2DDMACH                                                         */
+            uint32_t                : 3;
+            __IOM uint32_t Q3MDMACH : 3; /*!< [26..24] Q3MDMACH                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t Q3DDMACH : 1; /*!< [28..28] Q3DDMACH                                                         */
+            uint32_t                : 3;
+        } MTL_RxQ_DMA_Map0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MTL_RxQ_DMA_Map1; /*!< (@ 0x00000C34) MTL_RxQ_DMA_Map1                                           */
+
+        struct
+        {
+            __IOM uint32_t Q4MDMACH : 3; /*!< [2..0] Q4MDMACH                                                           */
+            uint32_t                : 1;
+            __IOM uint32_t Q4DDMACH : 1; /*!< [4..4] Q4DDMACH                                                           */
+            uint32_t                : 3;
+            __IOM uint32_t Q5MDMACH : 3; /*!< [10..8] Q5MDMACH                                                          */
+            uint32_t                : 1;
+            __IOM uint32_t Q5DDMACH : 1; /*!< [12..12] Q5DDMACH                                                         */
+            uint32_t                : 3;
+            __IOM uint32_t Q6MDMACH : 3; /*!< [18..16] Q6MDMACH                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t Q6DDMACH : 1; /*!< [20..20] Q6DDMACH                                                         */
+            uint32_t                : 3;
+            __IOM uint32_t Q7MDMACH : 3; /*!< [26..24] Q7MDMACH                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t Q7DDMACH : 1; /*!< [28..28] Q7DDMACH                                                         */
+            uint32_t                : 3;
+        } MTL_RxQ_DMA_Map1_b;
+    };
+    __IM uint32_t RESERVED34[2];
+
+    union
+    {
+        __IOM uint32_t MTL_TBS_CTRL;   /*!< (@ 0x00000C40) MTL_TBS_CTRL                                               */
+
+        struct
+        {
+            __IOM uint32_t ESTM  : 1;  /*!< [0..0] ESTM                                                               */
+            __IOM uint32_t LEOV  : 1;  /*!< [1..1] LEOV                                                               */
+            uint32_t             : 2;
+            __IOM uint32_t LEGOS : 3;  /*!< [6..4] LEGOS                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t LEOS  : 24; /*!< [31..8] LEOS                                                              */
+        } MTL_TBS_CTRL_b;
+    };
+    __IM uint32_t RESERVED35[3];
+
+    union
+    {
+        __IOM uint32_t MTL_EST_Control; /*!< (@ 0x00000C50) MTL_EST_Control                                            */
+
+        struct
+        {
+            __IOM uint32_t EEST  : 1;   /*!< [0..0] EEST                                                               */
+            __IOM uint32_t SSWL  : 1;   /*!< [1..1] SSWL                                                               */
+            uint32_t             : 1;
+            __IOM uint32_t QHLBF : 1;   /*!< [3..3] QHLBF                                                              */
+            __IOM uint32_t DDBF  : 1;   /*!< [4..4] DDBF                                                               */
+            __IOM uint32_t DFBS  : 1;   /*!< [5..5] DFBS                                                               */
+            __IOM uint32_t LCSE  : 2;   /*!< [7..6] LCSE                                                               */
+            __IOM uint32_t TILS  : 3;   /*!< [10..8] TILS                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t CTOV  : 12;  /*!< [23..12] CTOV                                                             */
+            __IOM uint32_t PTOV  : 8;   /*!< [31..24] PTOV                                                             */
+        } MTL_EST_Control_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MTL_EST_Ext_Control; /*!< (@ 0x00000C54) MTL_EST_Ext_Control                                        */
+
+        struct
+        {
+            __IOM uint32_t OVHD : 6;        /*!< [5..0] OVHD                                                               */
+            uint32_t            : 26;
+        } MTL_EST_Ext_Control_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MTL_EST_Status; /*!< (@ 0x00000C58) MTL_EST_Status                                             */
+
+        struct
+        {
+            __IOM uint32_t SWLC : 1;   /*!< [0..0] SWLC                                                               */
+            __IOM uint32_t BTRE : 1;   /*!< [1..1] BTRE                                                               */
+            __IM uint32_t  HLBF : 1;   /*!< [2..2] HLBF                                                               */
+            __IM uint32_t  HLBS : 1;   /*!< [3..3] HLBS                                                               */
+            __IOM uint32_t CGCE : 1;   /*!< [4..4] CGCE                                                               */
+            uint32_t            : 2;
+            __IM uint32_t SWOL  : 1;   /*!< [7..7] SWOL                                                               */
+            __IM uint32_t BTRL  : 8;   /*!< [15..8] BTRL                                                              */
+            __IM uint32_t CGSN  : 4;   /*!< [19..16] CGSN                                                             */
+            uint32_t            : 12;
+        } MTL_EST_Status_b;
+    };
+    __IM uint32_t RESERVED36;
+
+    union
+    {
+        __IOM uint32_t MTL_EST_Sch_Error; /*!< (@ 0x00000C60) MTL_EST_Sch_Error                                          */
+
+        struct
+        {
+            __IOM uint32_t SEQN : 8;      /*!< [7..0] SEQN                                                               */
+            uint32_t            : 24;
+        } MTL_EST_Sch_Error_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MTL_EST_Frm_Size_Error; /*!< (@ 0x00000C64) MTL_EST_Frm_Size_Error                                     */
+
+        struct
+        {
+            __IOM uint32_t FEQN : 8;           /*!< [7..0] FEQN                                                               */
+            uint32_t            : 24;
+        } MTL_EST_Frm_Size_Error_b;
+    };
+
+    union
+    {
+        __IM uint32_t MTL_EST_Frm_Size_Capture; /*!< (@ 0x00000C68) MTL_EST_Frm_Size_Capture                                   */
+
+        struct
+        {
+            __IM uint32_t HBFS : 15;            /*!< [14..0] HBFS                                                              */
+            uint32_t           : 1;
+            __IM uint32_t HBFQ : 3;             /*!< [18..16] HBFQ                                                             */
+            uint32_t           : 13;
+        } MTL_EST_Frm_Size_Capture_b;
+    };
+    __IM uint32_t RESERVED37;
+
+    union
+    {
+        __IOM uint32_t MTL_EST_Intr_Enable; /*!< (@ 0x00000C70) MTL_EST_Intr_Enable                                        */
+
+        struct
+        {
+            __IOM uint32_t IECC : 1;        /*!< [0..0] IECC                                                               */
+            __IOM uint32_t IEBE : 1;        /*!< [1..1] IEBE                                                               */
+            __IOM uint32_t IEHF : 1;        /*!< [2..2] IEHF                                                               */
+            __IOM uint32_t IEHS : 1;        /*!< [3..3] IEHS                                                               */
+            __IOM uint32_t CGCE : 1;        /*!< [4..4] CGCE                                                               */
+            uint32_t            : 27;
+        } MTL_EST_Intr_Enable_b;
+    };
+    __IM uint32_t RESERVED38[3];
+
+    union
+    {
+        __IOM uint32_t MTL_EST_GCL_Control; /*!< (@ 0x00000C80) MTL_EST_GCL_Control                                        */
+
+        struct
+        {
+            __IOM uint32_t SRWO : 1;        /*!< [0..0] SRWO                                                               */
+            __IOM uint32_t R1W0 : 1;        /*!< [1..1] R1W0                                                               */
+            __IOM uint32_t GCRR : 1;        /*!< [2..2] GCRR                                                               */
+            uint32_t            : 1;
+            __IOM uint32_t DBGM : 1;        /*!< [4..4] DBGM                                                               */
+            __IOM uint32_t DBGB : 1;        /*!< [5..5] DBGB                                                               */
+            uint32_t            : 2;
+            __IOM uint32_t ADDR : 8;        /*!< [15..8] ADDR                                                              */
+            uint32_t            : 16;
+        } MTL_EST_GCL_Control_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MTL_EST_GCL_Data; /*!< (@ 0x00000C84) MTL_EST_GCL_Data                                           */
+
+        struct
+        {
+            __IOM uint32_t GCD : 32;     /*!< [31..0] GCD                                                               */
+        } MTL_EST_GCL_Data_b;
+    };
+    __IM uint32_t RESERVED39[2];
+
+    union
+    {
+        __IOM uint32_t MTL_FPE_CTRL_STS; /*!< (@ 0x00000C90) MTL_FPE_CTRL_STS                                           */
+
+        struct
+        {
+            __IOM uint32_t AFSZ : 2;     /*!< [1..0] AFSZ                                                               */
+            uint32_t            : 6;
+            __IOM uint32_t PEC  : 8;     /*!< [15..8] PEC                                                               */
+            uint32_t            : 12;
+            __IM uint32_t HRS   : 1;     /*!< [28..28] HRS                                                              */
+            uint32_t            : 3;
+        } MTL_FPE_CTRL_STS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MTL_FPE_Advance; /*!< (@ 0x00000C94) MTL_FPE_Advance                                            */
+
+        struct
+        {
+            __IOM uint32_t HADV : 16;   /*!< [15..0] HADV                                                              */
+            __IOM uint32_t RADV : 16;   /*!< [31..16] RADV                                                             */
+        } MTL_FPE_Advance_b;
+    };
+    __IM uint32_t RESERVED40[26];
+
+    struct
+    {
+        union
+        {
+            __IOM uint32_t MTL_TXQ_OPERATION_MODE; /*!< (@ 0x00000D40) 1                                              */
+
+            struct
+            {
+                __IOM uint32_t FTQ   : 1;          /*!< [0..0] FTQ                                                    */
+                __IOM uint32_t TSF   : 1;          /*!< [1..1] TSF                                                    */
+                __IOM uint32_t TXQEN : 2;          /*!< [3..2] TXQEN                                                  */
+                __IOM uint32_t TTC   : 3;          /*!< [6..4] TTC                                                    */
+                uint32_t             : 9;
+                __IOM uint32_t TQS   : 5;          /*!< [20..16] TQS                                                  */
+                uint32_t             : 11;
+            } MTL_TXQ_OPERATION_MODE_b;
+        };
+
+        union
+        {
+            __IM uint32_t MTL_TXQ_UNDERFLOW; /*!< (@ 0x00000D44) 1                                                    */
+
+            struct
+            {
+                __IM uint32_t UFFRMCNT : 11; /*!< [10..0] UFFRMCNT                                                    */
+                __IM uint32_t UFCNTOVF : 1;  /*!< [11..11] UFCNTOVF                                                   */
+                uint32_t               : 20;
+            } MTL_TXQ_UNDERFLOW_b;
+        };
+
+        union
+        {
+            __IM uint32_t MTL_TXQ_DEBUG;     /*!< (@ 0x00000D48) 1                                                     */
+
+            struct
+            {
+                __IM uint32_t TXQPAUSED : 1; /*!< [0..0] TXQPAUSED                                                     */
+                __IM uint32_t TRCSTS    : 2; /*!< [2..1] TRCSTS                                                        */
+                __IM uint32_t TWCSTS    : 1; /*!< [3..3] TWCSTS                                                        */
+                __IM uint32_t TXQSTS    : 1; /*!< [4..4] TXQSTS                                                        */
+                __IM uint32_t TXSTSFSTS : 1; /*!< [5..5] TXSTSFSTS                                                     */
+                uint32_t                : 10;
+                __IM uint32_t PTXQ      : 3; /*!< [18..16] PTXQ                                                        */
+                uint32_t                : 1;
+                __IM uint32_t STXSTSF   : 3; /*!< [22..20] STXSTSF                                                     */
+                uint32_t                : 9;
+            } MTL_TXQ_DEBUG_b;
+        };
+        __IM uint32_t RESERVED41;
+
+        union
+        {
+            __IOM uint32_t MTL_TXQ_ETS_CONTROL; /*!< (@ 0x00000D50) 1                                                 */
+
+            struct
+            {
+                uint32_t             : 2;
+                __IOM uint32_t AVALG : 1; /*!< [2..2] AVALG                                                     */
+                __IOM uint32_t CC    : 1; /*!< [3..3] CC                                                        */
+                __IOM uint32_t SLC   : 3; /*!< [6..4] SLC                                                       */
+                uint32_t             : 25;
+            } MTL_TXQ_ETS_CONTROL_b;
+        };
+
+        union
+        {
+            __IM uint32_t MTL_TXQ_ETS_STATUS; /*!< (@ 0x00000D54) 1                                                   */
+
+            struct
+            {
+                __IM uint32_t ABS : 24;       /*!< [23..0] ABS                                                        */
+                uint32_t          : 8;
+            } MTL_TXQ_ETS_STATUS_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MTL_TXQ_QUANTUM_WEIGHT; /*!< (@ 0x00000D58) 1                                              */
+
+            struct
+            {
+                __IOM uint32_t ISCQW : 21;         /*!< [20..0] ISCQW                                                 */
+                uint32_t             : 11;
+            } MTL_TXQ_QUANTUM_WEIGHT_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MTL_TXQ_SENDSLOPECREDIT; /*!< (@ 0x00000D5C) 1                                             */
+
+            struct
+            {
+                __IOM uint32_t SSC : 14;            /*!< [13..0] SSC                                                  */
+                uint32_t           : 18;
+            } MTL_TXQ_SENDSLOPECREDIT_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MTL_TXQ_HICREDIT; /*!< (@ 0x00000D60) 1                                                    */
+
+            struct
+            {
+                __IOM uint32_t HC : 29;      /*!< [28..0] HC                                                          */
+                uint32_t          : 3;
+            } MTL_TXQ_HICREDIT_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MTL_TXQ_LOCREDIT; /*!< (@ 0x00000D64) 1                                                    */
+
+            struct
+            {
+                __IOM uint32_t LC : 29;      /*!< [28..0] LC                                                          */
+                uint32_t          : 3;
+            } MTL_TXQ_LOCREDIT_b;
+        };
+        __IM uint32_t RESERVED42;
+
+        union
+        {
+            __IOM uint32_t MTL_Q_INTERRUPT_CONTROL_STATUS; /*!< (@ 0x00000D6C) 1                                      */
+
+            struct
+            {
+                __IOM uint32_t TXUNFIS : 1;                /*!< [0..0] TXUNFIS                                        */
+                __IOM uint32_t ABPSIS  : 1;                /*!< [1..1] ABPSIS                                         */
+                uint32_t               : 6;
+                __IOM uint32_t TXUIE   : 1;                /*!< [8..8] TXUIE                                          */
+                __IOM uint32_t ABPSIE  : 1;                /*!< [9..9] ABPSIE                                         */
+                uint32_t               : 6;
+                __IOM uint32_t RXOVFIS : 1;                /*!< [16..16] RXOVFIS                                      */
+                uint32_t               : 7;
+                __IOM uint32_t RXOIE   : 1;                /*!< [24..24] RXOIE                                        */
+                uint32_t               : 7;
+            } MTL_Q_INTERRUPT_CONTROL_STATUS_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MTL_RXQ_OPERATION_MODE; /*!< (@ 0x00000D70) 1                                              */
+
+            struct
+            {
+                __IOM uint32_t RTC        : 2;     /*!< [1..0] RTC                                                    */
+                uint32_t                  : 1;
+                __IOM uint32_t FUP        : 1;     /*!< [3..3] FUP                                                    */
+                __IOM uint32_t FEP        : 1;     /*!< [4..4] FEP                                                    */
+                __IOM uint32_t RSF        : 1;     /*!< [5..5] RSF                                                    */
+                __IOM uint32_t DIS_TCP_EF : 1;     /*!< [6..6] DIS_TCP_EF                                             */
+                __IOM uint32_t EHFC       : 1;     /*!< [7..7] EHFC                                                   */
+                __IOM uint32_t RFA        : 4;     /*!< [11..8] RFA                                                   */
+                uint32_t                  : 2;
+                __IOM uint32_t RFD        : 4;     /*!< [17..14] RFD                                                  */
+                uint32_t                  : 2;
+                __IOM uint32_t RQS        : 5;     /*!< [24..20] RQS                                                  */
+                uint32_t                  : 7;
+            } MTL_RXQ_OPERATION_MODE_b;
+        };
+
+        union
+        {
+            __IM uint32_t MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT; /*!< (@ 0x00000D74) 1                                   */
+
+            struct
+            {
+                __IM uint32_t OVFPKTCNT : 11;                 /*!< [10..0] OVFPKTCNT                                  */
+                __IM uint32_t OVFCNTOVF : 1;                  /*!< [11..11] OVFCNTOVF                                 */
+                uint32_t                : 4;
+                __IM uint32_t MISPKTCNT : 11;                 /*!< [26..16] MISPKTCNT                                 */
+                __IM uint32_t MISCNTOVF : 1;                  /*!< [27..27] MISCNTOVF                                 */
+                uint32_t                : 4;
+            } MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_b;
+        };
+
+        union
+        {
+            __IM uint32_t MTL_RXQ_DEBUG;   /*!< (@ 0x00000D78) 1                                                       */
+
+            struct
+            {
+                __IM uint32_t RWCSTS : 1;  /*!< [0..0] RWCSTS                                                          */
+                __IM uint32_t RRCSTS : 2;  /*!< [2..1] RRCSTS                                                          */
+                uint32_t             : 1;
+                __IM uint32_t RXQSTS : 2;  /*!< [5..4] RXQSTS                                                          */
+                uint32_t             : 10;
+                __IM uint32_t PRXQ   : 14; /*!< [29..16] PRXQ                                                          */
+                uint32_t             : 2;
+            } MTL_RXQ_DEBUG_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MTL_RXQ_CONTROL;       /*!< (@ 0x00000D7C) 1                                                */
+
+            struct
+            {
+                __IOM uint32_t RXQ_WEGT      : 3; /*!< [2..0] RXQ_WEGT                                                 */
+                __IOM uint32_t RXQ_FRM_ARBIT : 1; /*!< [3..3] RXQ_FRM_ARBIT                                            */
+                uint32_t                     : 28;
+            } MTL_RXQ_CONTROL_b;
+        };
+    }             MTL_Q[8];
+    __IM uint32_t RESERVED43[64];
+
+    union
+    {
+        __IOM uint32_t DMA_Mode;       /*!< (@ 0x00001000) DMA_Mode                                                   */
+
+        struct
+        {
+            __IOM uint32_t SWR  : 1;   /*!< [0..0] SWR                                                                */
+            uint32_t            : 1;
+            __IOM uint32_t TAA  : 3;   /*!< [4..2] TAA                                                                */
+            uint32_t            : 3;
+            __IOM uint32_t DSPW : 1;   /*!< [8..8] DSPW                                                               */
+            uint32_t            : 2;
+            __IOM uint32_t TXPR : 1;   /*!< [11..11] TXPR                                                             */
+            uint32_t            : 4;
+            __IOM uint32_t INTM : 2;   /*!< [17..16] INTM                                                             */
+            uint32_t            : 14;
+        } DMA_Mode_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMA_SysBus_Mode;     /*!< (@ 0x00001004) DMA_SysBus_Mode                                            */
+
+        struct
+        {
+            __IOM uint32_t FB          : 1; /*!< [0..0] FB                                                                 */
+            __IOM uint32_t BLEN4       : 1; /*!< [1..1] BLEN4                                                              */
+            __IOM uint32_t BLEN8       : 1; /*!< [2..2] BLEN8                                                              */
+            __IOM uint32_t BLEN16      : 1; /*!< [3..3] BLEN16                                                             */
+            uint32_t                   : 6;
+            __IOM uint32_t AALE        : 1; /*!< [10..10] AALE                                                             */
+            uint32_t                   : 1;
+            __IOM uint32_t AAL         : 1; /*!< [12..12] AAL                                                              */
+            __IOM uint32_t ONEKBBE     : 1; /*!< [13..13] ONEKBBE                                                          */
+            uint32_t                   : 2;
+            __IOM uint32_t RD_OSR_LMT  : 4; /*!< [19..16] RD_OSR_LMT                                                       */
+            uint32_t                   : 4;
+            __IOM uint32_t WR_OSR_LMT  : 4; /*!< [27..24] WR_OSR_LMT                                                       */
+            uint32_t                   : 2;
+            __IOM uint32_t LPI_XIT_PKT : 1; /*!< [30..30] LPI_XIT_PKT                                                      */
+            __IOM uint32_t EN_LPI      : 1; /*!< [31..31] EN_LPI                                                           */
+        } DMA_SysBus_Mode_b;
+    };
+
+    union
+    {
+        __IM uint32_t DMA_Interrupt_Status; /*!< (@ 0x00001008) DMA_Interrupt_Status                                       */
+
+        struct
+        {
+            __IM uint32_t DC0IS : 1;        /*!< [0..0] DC0IS                                                              */
+            __IM uint32_t DC1IS : 1;        /*!< [1..1] DC1IS                                                              */
+            __IM uint32_t DC2IS : 1;        /*!< [2..2] DC2IS                                                              */
+            __IM uint32_t DC3IS : 1;        /*!< [3..3] DC3IS                                                              */
+            __IM uint32_t DC4IS : 1;        /*!< [4..4] DC4IS                                                              */
+            __IM uint32_t DC5IS : 1;        /*!< [5..5] DC5IS                                                              */
+            __IM uint32_t DC6IS : 1;        /*!< [6..6] DC6IS                                                              */
+            __IM uint32_t DC7IS : 1;        /*!< [7..7] DC7IS                                                              */
+            uint32_t            : 8;
+            __IM uint32_t MTLIS : 1;        /*!< [16..16] MTLIS                                                            */
+            __IM uint32_t MACIS : 1;        /*!< [17..17] MACIS                                                            */
+            uint32_t            : 14;
+        } DMA_Interrupt_Status_b;
+    };
+
+    union
+    {
+        __IM uint32_t DMA_Debug_Status0; /*!< (@ 0x0000100C) DMA_Debug_Status0                                          */
+
+        struct
+        {
+            __IM uint32_t AXWHSTS : 1;   /*!< [0..0] AXWHSTS                                                            */
+            __IM uint32_t AXRHSTS : 1;   /*!< [1..1] AXRHSTS                                                            */
+            uint32_t              : 6;
+            __IM uint32_t RPS0    : 4;   /*!< [11..8] RPS0                                                              */
+            __IM uint32_t TPS0    : 4;   /*!< [15..12] TPS0                                                             */
+            __IM uint32_t RPS1    : 4;   /*!< [19..16] RPS1                                                             */
+            __IM uint32_t TPS1    : 4;   /*!< [23..20] TPS1                                                             */
+            __IM uint32_t RPS2    : 4;   /*!< [27..24] RPS2                                                             */
+            __IM uint32_t TPS2    : 4;   /*!< [31..28] TPS2                                                             */
+        } DMA_Debug_Status0_b;
+    };
+
+    union
+    {
+        __IM uint32_t DMA_Debug_Status1; /*!< (@ 0x00001010) DMA_Debug_Status1                                          */
+
+        struct
+        {
+            __IM uint32_t RPS3 : 4;      /*!< [3..0] RPS3                                                               */
+            __IM uint32_t TPS3 : 4;      /*!< [7..4] TPS3                                                               */
+            __IM uint32_t RPS4 : 4;      /*!< [11..8] RPS4                                                              */
+            __IM uint32_t TPS4 : 4;      /*!< [15..12] TPS4                                                             */
+            __IM uint32_t RPS5 : 4;      /*!< [19..16] RPS5                                                             */
+            __IM uint32_t TPS5 : 4;      /*!< [23..20] TPS5                                                             */
+            __IM uint32_t RPS6 : 4;      /*!< [27..24] RPS6                                                             */
+            __IM uint32_t TPS6 : 4;      /*!< [31..28] TPS6                                                             */
+        } DMA_Debug_Status1_b;
+    };
+
+    union
+    {
+        __IM uint32_t DMA_Debug_Status2; /*!< (@ 0x00001014) DMA_Debug_Status2                                          */
+
+        struct
+        {
+            __IM uint32_t RPS7 : 4;      /*!< [3..0] RPS7                                                               */
+            __IM uint32_t TPS7 : 4;      /*!< [7..4] TPS7                                                               */
+            uint32_t           : 24;
+        } DMA_Debug_Status2_b;
+    };
+    __IM uint32_t RESERVED44[10];
+
+    union
+    {
+        __IOM uint32_t AXI_LPI_Entry_Interval; /*!< (@ 0x00001040) AXI_LPI_Entry_Interval                                     */
+
+        struct
+        {
+            __IOM uint32_t LPIEI : 4;          /*!< [3..0] LPIEI                                                              */
+            uint32_t             : 28;
+        } AXI_LPI_Entry_Interval_b;
+    };
+    __IM uint32_t RESERVED45[3];
+
+    union
+    {
+        __IOM uint32_t DMA_TBS_CTRL0;  /*!< (@ 0x00001050) DMA_TBS_CTRL0                                              */
+
+        struct
+        {
+            __IOM uint32_t FTOV : 1;   /*!< [0..0] FTOV                                                               */
+            uint32_t            : 3;
+            __IOM uint32_t FGOS : 3;   /*!< [6..4] FGOS                                                               */
+            uint32_t            : 1;
+            __IOM uint32_t FTOS : 24;  /*!< [31..8] FTOS                                                              */
+        } DMA_TBS_CTRL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMA_TBS_CTRL1;  /*!< (@ 0x00001054) DMA_TBS_CTRL1                                              */
+
+        struct
+        {
+            __IOM uint32_t FTOV : 1;   /*!< [0..0] FTOV                                                               */
+            uint32_t            : 3;
+            __IOM uint32_t FGOS : 3;   /*!< [6..4] FGOS                                                               */
+            uint32_t            : 1;
+            __IOM uint32_t FTOS : 24;  /*!< [31..8] FTOS                                                              */
+        } DMA_TBS_CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMA_TBS_CTRL2;  /*!< (@ 0x00001058) DMA_TBS_CTRL2                                              */
+
+        struct
+        {
+            __IOM uint32_t FTOV : 1;   /*!< [0..0] FTOV                                                               */
+            uint32_t            : 3;
+            __IOM uint32_t FGOS : 3;   /*!< [6..4] FGOS                                                               */
+            uint32_t            : 1;
+            __IOM uint32_t FTOS : 24;  /*!< [31..8] FTOS                                                              */
+        } DMA_TBS_CTRL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMA_TBS_CTRL3;  /*!< (@ 0x0000105C) DMA_TBS_CTRL3                                              */
+
+        struct
+        {
+            __IOM uint32_t FTOV : 1;   /*!< [0..0] FTOV                                                               */
+            uint32_t            : 3;
+            __IOM uint32_t FGOS : 3;   /*!< [6..4] FGOS                                                               */
+            uint32_t            : 1;
+            __IOM uint32_t FTOS : 24;  /*!< [31..8] FTOS                                                              */
+        } DMA_TBS_CTRL3_b;
+    };
+    __IM uint32_t RESERVED46[40];
+
+    struct
+    {
+        union
+        {
+            __IOM uint32_t DMA_CH_CONTROL; /*!< (@ 0x00001100) 0                                                      */
+
+            struct
+            {
+                uint32_t           : 18;
+                __IOM uint32_t DSL : 3; /*!< [20..18] DSL                                                          */
+                uint32_t           : 3;
+                __IOM uint32_t SPH : 1; /*!< [24..24] SPH                                                          */
+                uint32_t           : 7;
+            } DMA_CH_CONTROL_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_TX_CONTROL; /*!< (@ 0x00001104) 0                                                  */
+
+            struct
+            {
+                __IOM uint32_t ST    : 1;     /*!< [0..0] ST                                                         */
+                __IOM uint32_t TCW   : 3;     /*!< [3..1] TCW                                                        */
+                __IOM uint32_t OSF   : 1;     /*!< [4..4] OSF                                                        */
+                uint32_t             : 10;
+                __IOM uint32_t IPBL  : 1;     /*!< [15..15] IPBL                                                     */
+                __IOM uint32_t TxPBL : 6;     /*!< [21..16] TxPBL                                                    */
+                uint32_t             : 6;
+                __IOM uint32_t EDSE  : 1;     /*!< [28..28] EDSE                                                     */
+                __IOM uint32_t TFSEL : 2;     /*!< [30..29] TFSEL                                                    */
+                uint32_t             : 1;
+            } DMA_CH_TX_CONTROL_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_RX_CONTROL;  /*!< (@ 0x00001108) 0                                                  */
+
+            struct
+            {
+                __IOM uint32_t SR        : 1;  /*!< [0..0] SR                                                         */
+                __IM uint32_t  RBSZ_x_0  : 4;  /*!< [4..1] RBSZ_x_0                                                   */
+                __IOM uint32_t RBSZ_13_y : 10; /*!< [14..5] RBSZ_13_y                                                 */
+                uint32_t                 : 1;
+                __IOM uint32_t RxPBL     : 6;  /*!< [21..16] RxPBL                                                    */
+                uint32_t                 : 9;
+                __IOM uint32_t RPF       : 1;  /*!< [31..31] RPF                                                      */
+            } DMA_CH_RX_CONTROL_b;
+        };
+        __IM uint32_t RESERVED47[2];
+
+        union
+        {
+            __IOM uint32_t DMA_CH_TXDESC_LIST_ADDRESS; /*!< (@ 0x00001114) 0                                         */
+
+            struct
+            {
+                __IOM uint32_t TDESLA : 32;            /*!< [31..0] TDESLA                                           */
+            } DMA_CH_TXDESC_LIST_ADDRESS_b;
+        };
+        __IM uint32_t RESERVED48;
+
+        union
+        {
+            __IOM uint32_t DMA_CH_RXDESC_LIST_ADDRESS; /*!< (@ 0x0000111C) 0                                         */
+
+            struct
+            {
+                __IOM uint32_t RDESLA : 32;            /*!< [31..0] RDESLA                                           */
+            } DMA_CH_RXDESC_LIST_ADDRESS_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_TXDESC_TAIL_POINTER; /*!< (@ 0x00001120) 0                                         */
+
+            struct
+            {
+                __IOM uint32_t TDTP : 32;              /*!< [31..0] TDTP                                             */
+            } DMA_CH_TXDESC_TAIL_POINTER_b;
+        };
+        __IM uint32_t RESERVED49;
+
+        union
+        {
+            __IOM uint32_t DMA_CH_RXDESC_TAIL_POINTER; /*!< (@ 0x00001128) 0                                         */
+
+            struct
+            {
+                __IOM uint32_t RDTP : 32;              /*!< [31..0] RDTP                                             */
+            } DMA_CH_RXDESC_TAIL_POINTER_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_TXDESC_RING_LENGTH; /*!< (@ 0x0000112C) 0                                          */
+
+            struct
+            {
+                __IOM uint32_t TDRL : 10;             /*!< [9..0] TDRL                                               */
+                uint32_t            : 22;
+            } DMA_CH_TXDESC_RING_LENGTH_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_RX_CONTROL2; /*!< (@ 0x00001130) 0                                                  */
+
+            struct
+            {
+                __IOM uint32_t RDRL : 10;      /*!< [9..0] RDRL                                                       */
+                uint32_t            : 8;
+                __IOM uint32_t ARBS : 6;       /*!< [23..18] ARBS                                                     */
+                uint32_t            : 8;
+            } DMA_CH_RX_CONTROL2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_INTERRUPT_ENABLE; /*!< (@ 0x00001134) 0                                             */
+
+            struct
+            {
+                __IOM uint32_t TIE  : 1;            /*!< [0..0] TIE                                                   */
+                __IOM uint32_t TXSE : 1;            /*!< [1..1] TXSE                                                  */
+                __IOM uint32_t TBUE : 1;            /*!< [2..2] TBUE                                                  */
+                uint32_t            : 3;
+                __IOM uint32_t RIE  : 1;            /*!< [6..6] RIE                                                   */
+                __IOM uint32_t RBUE : 1;            /*!< [7..7] RBUE                                                  */
+                __IOM uint32_t RSE  : 1;            /*!< [8..8] RSE                                                   */
+                __IOM uint32_t RWTE : 1;            /*!< [9..9] RWTE                                                  */
+                __IOM uint32_t ETIE : 1;            /*!< [10..10] ETIE                                                */
+                __IOM uint32_t ERIE : 1;            /*!< [11..11] ERIE                                                */
+                __IOM uint32_t FBEE : 1;            /*!< [12..12] FBEE                                                */
+                __IOM uint32_t CDEE : 1;            /*!< [13..13] CDEE                                                */
+                __IOM uint32_t AIE  : 1;            /*!< [14..14] AIE                                                 */
+                __IOM uint32_t NIE  : 1;            /*!< [15..15] NIE                                                 */
+                uint32_t            : 16;
+            } DMA_CH_INTERRUPT_ENABLE_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER; /*!< (@ 0x00001138) 0                                  */
+
+            struct
+            {
+                __IOM uint32_t RWT  : 8;                       /*!< [7..0] RWT                                        */
+                uint32_t            : 8;
+                __IOM uint32_t RWTU : 2;                       /*!< [17..16] RWTU                                     */
+                uint32_t            : 14;
+            } DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_SLOT_FUNCTION_CONTROL_STATUS; /*!< (@ 0x0000113C) 0                                 */
+
+            struct
+            {
+                __IOM uint32_t ESC : 1;                         /*!< [0..0] ESC                                       */
+                __IOM uint32_t ASC : 1;                         /*!< [1..1] ASC                                       */
+                uint32_t           : 2;
+                __IOM uint32_t SIV : 12;                        /*!< [15..4] SIV                                      */
+                __IM uint32_t  RSN : 4;                         /*!< [19..16] RSN                                     */
+                uint32_t           : 12;
+            } DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_b;
+        };
+        __IM uint32_t RESERVED50;
+
+        union
+        {
+            __IM uint32_t DMA_CH_CURRENT_APP_TXDESC; /*!< (@ 0x00001144) 0                                            */
+
+            struct
+            {
+                __IM uint32_t CURTDESAPTR : 32;      /*!< [31..0] CURTDESAPTR                                         */
+            } DMA_CH_CURRENT_APP_TXDESC_b;
+        };
+        __IM uint32_t RESERVED51;
+
+        union
+        {
+            __IM uint32_t DMA_CH_CURRENT_APP_RXDESC; /*!< (@ 0x0000114C) 0                                            */
+
+            struct
+            {
+                __IM uint32_t CURRDESAPTR : 32;      /*!< [31..0] CURRDESAPTR                                         */
+            } DMA_CH_CURRENT_APP_RXDESC_b;
+        };
+        __IM uint32_t RESERVED52;
+
+        union
+        {
+            __IM uint32_t DMA_CH_CURRENT_APP_TXBUFFER; /*!< (@ 0x00001154) 0                                          */
+
+            struct
+            {
+                __IM uint32_t CURTBUFAPTR : 32;        /*!< [31..0] CURTBUFAPTR                                       */
+            } DMA_CH_CURRENT_APP_TXBUFFER_b;
+        };
+        __IM uint32_t RESERVED53;
+
+        union
+        {
+            __IM uint32_t DMA_CH_CURRENT_APP_RXBUFFER; /*!< (@ 0x0000115C) 0                                          */
+
+            struct
+            {
+                __IM uint32_t CURRBUFAPTR : 32;        /*!< [31..0] CURRBUFAPTR                                       */
+            } DMA_CH_CURRENT_APP_RXBUFFER_b;
+        };
+
+        union
+        {
+            __IOM uint32_t DMA_CH_STATUS; /*!< (@ 0x00001160) 0                                                      */
+
+            struct
+            {
+                __IOM uint32_t TI  : 1;   /*!< [0..0] TI                                                             */
+                __IOM uint32_t TPS : 1;   /*!< [1..1] TPS                                                            */
+                __IOM uint32_t TBU : 1;   /*!< [2..2] TBU                                                            */
+                uint32_t           : 3;
+                __IOM uint32_t RI  : 1;   /*!< [6..6] RI                                                             */
+                __IOM uint32_t RBU : 1;   /*!< [7..7] RBU                                                            */
+                __IOM uint32_t RPS : 1;   /*!< [8..8] RPS                                                            */
+                __IOM uint32_t RWT : 1;   /*!< [9..9] RWT                                                            */
+                __IOM uint32_t ETI : 1;   /*!< [10..10] ETI                                                          */
+                __IOM uint32_t ERI : 1;   /*!< [11..11] ERI                                                          */
+                __IOM uint32_t FBE : 1;   /*!< [12..12] FBE                                                          */
+                __IOM uint32_t CDE : 1;   /*!< [13..13] CDE                                                          */
+                __IOM uint32_t AIS : 1;   /*!< [14..14] AIS                                                          */
+                __IOM uint32_t NIS : 1;   /*!< [15..15] NIS                                                          */
+                __IM uint32_t  TEB : 3;   /*!< [18..16] TEB                                                          */
+                __IM uint32_t  REB : 3;   /*!< [21..19] REB                                                          */
+                uint32_t           : 10;
+            } DMA_CH_STATUS_b;
+        };
+
+        union
+        {
+            __IM uint32_t DMA_CH_MISS_FRAME_CNT; /*!< (@ 0x00001164) 0                                                      */
+
+            struct
+            {
+                __IM uint32_t MFC  : 11;         /*!< [10..0] MFC                                                           */
+                uint32_t           : 4;
+                __IM uint32_t MFCO : 1;          /*!< [15..15] MFCO                                                         */
+                uint32_t           : 16;
+            } DMA_CH_MISS_FRAME_CNT_b;
+        };
+        __IM uint32_t RESERVED54[6];
+    } DMA_CH[8];
+} R_GMAC_Type;                         /*!< Size = 5352 (0x14e8)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ETHSS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet Subsystem (R_ETHSS)
+ */
+
+typedef struct                         /*!< (@ 0x80110000) R_ETHSS Structure                                          */
+{
+    __IOM uint32_t PRCMD;              /*!< (@ 0x00000000) Ethernet Protect Register                                  */
+    __IM uint32_t  RESERVED;
+
+    union
+    {
+        __IOM uint32_t MODCTRL;         /*!< (@ 0x00000008) Mode Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t SW_MODE : 3; /*!< [2..0] Selects the function of the Media interface of the MAC
+                                         *   to be used                                                                */
+            uint32_t : 29;
+        } MODCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPMCTRL;             /*!< (@ 0x0000000C) PTP Mode Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t PTP_MODE0 : 1;    /*!< [0..0] Select the unit number of PTP Timer for GMAC0 and Pulse
+                                              *   Generator (unit 0 - 3)                                                    */
+            __IOM uint32_t PTP_MODE1    : 1; /*!< [1..1] Select the unit number of PTP Timer for GMAC1                      */
+            __IOM uint32_t PTP_MODE2    : 1; /*!< [2..2] Select the unit number of PTP Timer for GMAC2                      */
+            uint32_t                    : 13;
+            __IOM uint32_t PTP_PLS_RSTn : 1; /*!< [16..16] Reset control for Pulse Generator (unit 0 - 3)                   */
+            uint32_t                    : 15;
+        } PTPMCTRL_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t PHYLNK;         /*!< (@ 0x00000014) Ethernet PHY Link Mode Register                            */
+
+        struct
+        {
+            __IOM uint32_t SWLINK : 3; /*!< [2..0] Specify the active level of the ETHSW_PHYLINKn signal
+                                        *   using the Ethernet switch interface                                       */
+            uint32_t              : 1;
+            __IOM uint32_t CATLNK : 3; /*!< [6..4] Specify the active level of the ESC_PHYLINKn signal using
+                                        *   the EtherCAT interface                                                    */
+            uint32_t : 25;
+        } PHYLNK_b;
+    };
+    __IM uint32_t RESERVED2[58];
+
+    union
+    {
+        __IOM uint32_t CONVCTRL[4];           /*!< (@ 0x00000100) RGMII/RMII Converter [0..3] Control Register               */
+
+        struct
+        {
+            __IOM uint32_t CONV_MODE     : 5; /*!< [4..0] Converter operation mode                                           */
+            uint32_t                     : 3;
+            __IOM uint32_t FULLD         : 1; /*!< [8..8] FULLD                                                              */
+            __IOM uint32_t RMII_RX_ER_EN : 1; /*!< [9..9] RMII_RX_ER_EN                                                      */
+            __IOM uint32_t RMII_CRS_MODE : 1; /*!< [10..10] RMII_CRS_MODE                                                    */
+            uint32_t                     : 1;
+            __IM uint32_t RGMII_LINK     : 1; /*!< [12..12] RGMII_LINK                                                       */
+            __IM uint32_t RGMII_DUPLEX   : 1; /*!< [13..13] RGMII_DUPLEX                                                     */
+            __IM uint32_t RGMII_SPEED    : 2; /*!< [15..14] RGMII_SPEED                                                      */
+            uint32_t                     : 16;
+        } CONVCTRL_b[4];
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t CONVRST;        /*!< (@ 0x00000114) RGMII/RMII Converter Reset Control Register                */
+
+        struct
+        {
+            __IOM uint32_t PHYIR : 4;  /*!< [3..0] PHYIR                                                              */
+            uint32_t             : 28;
+        } CONVRST_b;
+    };
+    __IM uint32_t RESERVED4[123];
+
+    union
+    {
+        __IOM uint32_t SWCTRL;                /*!< (@ 0x00000304) Switch Core Control Register                               */
+
+        struct
+        {
+            __IOM uint32_t SET10 : 3;         /*!< [2..0] Port control to select use of 10 Mbps. Bit 0 = port 0,
+                                               *   bit 1 = port 1, bit 2 = port 2.                                           */
+            uint32_t               : 1;
+            __IOM uint32_t SET1000 : 3;       /*!< [6..4] Port control to select use of 1000 Mbps. Bit 0 = port
+                                               *   0, bit 1 = port 1, bit 2 = port 2.                                        */
+            uint32_t                    : 9;
+            __IOM uint32_t STRAP_SX_ENB : 1;  /*!< [16..16] Initialize switch after reset (set during module reset
+                                               *   of ETHSW)                                                                 */
+            __IOM uint32_t STRAP_HUB_ENB : 1; /*!< [17..17] Initialize switch port 0 and 1 (set during module reset
+                                               *   of ETHSW)                                                                 */
+            uint32_t : 14;
+        } SWCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWDUPC;             /*!< (@ 0x00000308) Switch Core Duplex Mode Register                           */
+
+        struct
+        {
+            __IOM uint32_t PHY_DUPLEX : 3; /*!< [2..0] Configure the MAC of each port for full-duplex or half-duplex
+                                            *   operation. Bit 0 = port 0, bit 1 = port 1, bit 2 = port
+                                            *   2.                                                                        */
+            uint32_t : 29;
+        } SWDUPC_b;
+    };
+} R_ETHSS_Type;                            /*!< Size = 780 (0x30c)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ESC_INI                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Initial Configuration 1 for EtherCAT Slave Controller (R_ESC_INI)
+ */
+
+typedef struct                         /*!< (@ 0x80110200) R_ESC_INI Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t ECATOFFADR;     /*!< (@ 0x00000000) EtherCAT PHY Offset Address Setting Register               */
+
+        struct
+        {
+            __IOM uint32_t OADD : 5;   /*!< [4..0] PHY Offset Address Setting                                         */
+            uint32_t            : 27;
+        } ECATOFFADR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ECATOPMOD;          /*!< (@ 0x00000004) EtherCAT Operation Mode Register                           */
+
+        struct
+        {
+            __IOM uint32_t EEPROMSIZE : 1; /*!< [0..0] EEPROM Memory Size Specification                                   */
+            uint32_t                  : 31;
+        } ECATOPMOD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ECATDBGC;       /*!< (@ 0x00000008) EtherCAT Debug Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t TXSFT0 : 2; /*!< [1..0] Set the delay time for ETH0_TXEN and ETH0_TXDn of the
+                                        *   EtherCAT                                                                  */
+            __IOM uint32_t TXSFT1 : 2; /*!< [3..2] Set the delay time for ETH1_TXEN and ETH1_TXDn of the
+                                        *   EtherCAT                                                                  */
+            __IOM uint32_t TXSFT2 : 2; /*!< [5..4] Set the delay time for ETH2_TXEN and ETH2_TXDn of the
+                                        *   EtherCAT                                                                  */
+            uint32_t : 26;
+        } ECATDBGC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ECATTRGSEL;      /*!< (@ 0x0000000C) EtherCAT DC Latch Trigger Select Register                  */
+
+        struct
+        {
+            __IOM uint32_t TRGSEL0 : 1; /*!< [0..0] Select DC Latch Trigger 0 for ESC                                  */
+            __IOM uint32_t TRGSEL1 : 1; /*!< [1..1] Select DC Latch Trigger 1 for ESC                                  */
+            uint32_t               : 30;
+        } ECATTRGSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ECATRESOUT;          /*!< (@ 0x00000010) EtherCAT Reset Out Control register                        */
+
+        struct
+        {
+            __IOM uint32_t FORCE_RESET : 1; /*!< [0..0] FORCE_RESET                                                        */
+            __IOM uint32_t RESOUT_EN   : 1; /*!< [1..1] RESOUT_EN                                                          */
+            uint32_t                   : 30;
+        } ECATRESOUT_b;
+    };
+} R_ESC_INI_Type;                           /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_ETHSW_PTP                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet Switch for PTP (R_ETHSW_PTP)
+ */
+
+typedef struct                         /*!< (@ 0x80110400) R_ETHSW_PTP Structure                                      */
+{
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t SWPTPOUTSEL;     /*!< (@ 0x00000004) ETHSW_PTPOUT Select Register                               */
+
+        struct
+        {
+            __IOM uint32_t IOSEL0  : 1; /*!< [0..0] Select the source of the ETHSW_PTPOUT0 output signal               */
+            __IOM uint32_t IOSEL1  : 1; /*!< [1..1] Select the source of the ETHSW_PTPOUT1 output signal               */
+            __IOM uint32_t IOSEL2  : 1; /*!< [2..2] Select the source of the ETHSW_PTPOUT2 output signal               */
+            __IOM uint32_t IOSEL3  : 1; /*!< [3..3] Select the source of the ETHSW_PTPOUT3 output signal               */
+            __IOM uint32_t EVTSEL0 : 1; /*!< [4..4] Select the source of the ETHSW_PTPOUT0 event for GIC,
+                                         *   DMAC, and ELC                                                             */
+            __IOM uint32_t EVTSEL1 : 1; /*!< [5..5] Select the source of the ETHSW_PTPOUT1 event for GIC,
+                                         *   DMAC, and ELC                                                             */
+            __IOM uint32_t EVTSEL2 : 1; /*!< [6..6] Select the source of the ETHSW_PTPOUT2 event for GIC,
+                                         *   DMAC, and ELC                                                             */
+            __IOM uint32_t EVTSEL3 : 1; /*!< [7..7] Select the source of the ETHSW_PTPOUT3 event for GIC,
+                                         *   DMAC, and ELC                                                             */
+            uint32_t : 24;
+        } SWPTPOUTSEL_b;
+    };
+    __IM uint32_t               RESERVED1[254];
+    __IOM R_ETHSW_PTP_SWTM_Type SWTM[4]; /*!< (@ 0x00000400) Ethernet Switch Timer output pins 0-3 Registers            */
+} R_ETHSW_PTP_Type;                      /*!< Size = 2048 (0x800)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GMACC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_GMACC (R_GMACC)
+ */
+
+typedef struct                            /*!< (@ 0x80110400) R_GMACC Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t GMACTRGSEL;        /*!< (@ 0x00000000) GMACTRGSEL                                                 */
+
+        struct
+        {
+            __IOM uint32_t G0TRGSEL0 : 1; /*!< [0..0] G0TRGSEL0                                                          */
+            __IOM uint32_t G0TRGSEL1 : 1; /*!< [1..1] G0TRGSEL1                                                          */
+            __IOM uint32_t G1TRGSEL0 : 1; /*!< [2..2] G1TRGSEL0                                                          */
+            __IOM uint32_t G1TRGSEL1 : 1; /*!< [3..3] G1TRGSEL1                                                          */
+            __IOM uint32_t G2TRGSEL0 : 1; /*!< [4..4] G2TRGSEL0                                                          */
+            __IOM uint32_t G2TRGSEL1 : 1; /*!< [5..5] G2TRGSEL1                                                          */
+            uint32_t                 : 26;
+        } GMACTRGSEL_b;
+    };
+} R_GMACC_Type;                           /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ETHSW                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet Switch (R_ETHSW)
+ */
+
+typedef struct                         /*!< (@ 0x80120000) R_ETHSW Structure                                          */
+{
+    union
+    {
+        __IM uint32_t REVISION;        /*!< (@ 0x00000000) Switch Core Version Register                               */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] Revision                                                          */
+        } REVISION_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCRATCH;          /*!< (@ 0x00000004) Scratch Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SCRATCH : 32; /*!< [31..0] The Scratch Register provides a memory location to test
+                                          *   the register access.                                                      */
+        } SCRATCH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PORT_ENA;       /*!< (@ 0x00000008) Port Enable Register                                       */
+
+        struct
+        {
+            __IOM uint32_t TXENA : 4;  /*!< [3..0] Transmit Enable Mask                                               */
+            uint32_t             : 12;
+            __IOM uint32_t RXENA : 4;  /*!< [19..16] Receive Enable Mask                                              */
+            uint32_t             : 12;
+        } PORT_ENA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t UCAST_DEFAULT_MASK0; /*!< (@ 0x0000000C) Unicast Default Mask Register 0                            */
+
+        struct
+        {
+            __IOM uint32_t UCASTDM : 4;     /*!< [3..0] Default Unicast Resolution                                         */
+            uint32_t               : 28;
+        } UCAST_DEFAULT_MASK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_VERIFY;      /*!< (@ 0x00000010) Verify VLAN Domain Register                                */
+
+        struct
+        {
+            __IOM uint32_t VLANVERI : 4; /*!< [3..0] Verify VLAN Domain                                                 */
+            uint32_t                : 12;
+            __IOM uint32_t VLANDISC : 4; /*!< [19..16] Discard Unknown                                                  */
+            uint32_t                : 12;
+        } VLAN_VERIFY_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCAST_DEFAULT_MASK0; /*!< (@ 0x00000014) Broadcast Default Mask Register 0                          */
+
+        struct
+        {
+            __IOM uint32_t BCASTDM : 4;     /*!< [3..0] Default Broadcast Resolution                                       */
+            uint32_t               : 28;
+        } BCAST_DEFAULT_MASK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MCAST_DEFAULT_MASK0; /*!< (@ 0x00000018) Multicast Default Mask Register 0                          */
+
+        struct
+        {
+            __IOM uint32_t MCASTDM : 4;     /*!< [3..0] Default Multicast Resolution                                       */
+            uint32_t               : 28;
+        } MCAST_DEFAULT_MASK0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INPUT_LEARN_BLOCK; /*!< (@ 0x0000001C) Input Learning Block Register                              */
+
+        struct
+        {
+            __IOM uint32_t BLOCKEN  : 4;  /*!< [3..0] Blocking Enable                                                    */
+            uint32_t                : 12;
+            __IOM uint32_t LEARNDIS : 4;  /*!< [19..16] Learning Disable                                                 */
+            uint32_t                : 12;
+        } INPUT_LEARN_BLOCK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MGMT_CONFIG;       /*!< (@ 0x00000020) Management Configuration Register                          */
+
+        struct
+        {
+            __IOM uint32_t PORT : 4;      /*!< [3..0] The Port number of the port that should act as a management
+                                           *   port. Keep the initial value.                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t MSG_TRANS : 1; /*!< [5..5] Set (latched) when a BPDU message is transmitted from
+                                           *   the management port to any output port. This bit can be
+                                           *   used for handshaking to indicate that the port mask bits
+                                           *   are used and can now be changed again by setting it to
+                                           *   0.                                                                        */
+            __IOM uint32_t ENABLE : 1;    /*!< [6..6] If set, all Bridge Protocol Frames (BPDU) are forwarded
+                                           *   exclusively to the management port specified in bits [3:0].               */
+            __IOM uint32_t DISCARD : 1;   /*!< [7..7] If set, BPDU frames are discarded always.                          */
+            __IOM uint32_t MGMT_EN : 1;   /*!< [8..8] If set, BPDU frames received at the management port are
+                                           *   forwarded to the ports given in the portmask given in this
+                                           *   register, bypassing the normal forwarding decisions (except
+                                           *   forced forwarding).                                                       */
+            __IOM uint32_t MGMT_DISC : 1; /*!< [9..9] This bit is the same as DISCARD (bit 7) but for the management
+                                           *   port.                                                                     */
+            uint32_t                : 3;
+            __IOM uint32_t PRIORITY : 3;  /*!< [15..13] Priority to use for transmitted BPDU frames if non-zero.         */
+            __IOM uint32_t PORTMASK : 4;  /*!< [19..16] Portmask for transmission of management frames. When
+                                           *   the management port transmits a frame to the switch, it
+                                           *   is forwarded to all ports in this portmask (bit 16 = port
+                                           *   0, bit 17 = port 1, ..., bit 19 = port 3).                                */
+            uint32_t : 12;
+        } MGMT_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MODE_CONFIG;    /*!< (@ 0x00000024) Mode Configuration Register                                */
+
+        struct
+        {
+            uint32_t                   : 8;
+            __IOM uint32_t CUT_THRU_EN : 4; /*!< [11..8] Port Cut through Support Enable                                   */
+            uint32_t                   : 19;
+            __IOM uint32_t STATSRESET  : 1; /*!< [31..31] Reset Statistics Counters Command.                               */
+        } MODE_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_IN_MODE;       /*!< (@ 0x00000028) VLAN Input Manipulation Mode Register                      */
+
+        struct
+        {
+            __IOM uint32_t P0VLANINMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Input Manipulation Function         */
+            __IOM uint32_t P1VLANINMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Input Manipulation Function         */
+            __IOM uint32_t P2VLANINMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Input Manipulation Function         */
+            __IOM uint32_t P3VLANINMD : 2; /*!< [7..6] Port3 Define Behavior of VLAN Input Manipulation Function          */
+            uint32_t                  : 24;
+        } VLAN_IN_MODE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_OUT_MODE;       /*!< (@ 0x0000002C) VLAN Output Manipulation Mode Register                     */
+
+        struct
+        {
+            __IOM uint32_t P0VLANOUTMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Output Manipulation Function        */
+            __IOM uint32_t P1VLANOUTMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Output Manipulation Function        */
+            __IOM uint32_t P2VLANOUTMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Output Manipulation Function        */
+            __IOM uint32_t P3VLANOUTMD : 2; /*!< [7..6] Port 3 Define Behavior of VLAN Output Manipulation Function        */
+            uint32_t                   : 24;
+        } VLAN_OUT_MODE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_IN_MODE_ENA;   /*!< (@ 0x00000030) VLAN Input Mode Enable Register                            */
+
+        struct
+        {
+            __IOM uint32_t VLANINMDEN : 4; /*!< [3..0] Enable the input processing according to the VLAN_IN_MODE
+                                            *   for a port (1 bit per port).                                              */
+            uint32_t : 28;
+        } VLAN_IN_MODE_ENA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_TAG_ID;        /*!< (@ 0x00000034) VLAN Tag ID Register                                       */
+
+        struct
+        {
+            __IOM uint32_t VLANTAGID : 16; /*!< [15..0] The VLAN type field (TPID) value to expect to identify
+                                            *   a VLAN tagged frame.                                                      */
+            uint32_t : 16;
+        } VLAN_TAG_ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCAST_STORM_LIMIT;   /*!< (@ 0x00000038) Broadcast Storm Protection Register                        */
+
+        struct
+        {
+            __IOM uint32_t TMOUT      : 16; /*!< [15..0] Timeout in steps of 65535 switch operating clock cycles.          */
+            __IOM uint32_t BCASTLIMIT : 16; /*!< [31..16] Number of broadcast frames (-1) that can be accepted
+                                             *   on a port during a timeout period. If more are received,
+                                             *   they are discarded. The counter is implemented per port
+                                             *   independently. However, the limit is used for all ports.                  */
+        } BCAST_STORM_LIMIT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MCAST_STORM_LIMIT; /*!< (@ 0x0000003C) Multicast Storm Protection Register                        */
+
+        struct
+        {
+            uint32_t                  : 16;
+            __IOM uint32_t MCASTLIMIT : 16; /*!< [31..16] Number of multicast frames (-1) that can be accepted
+                                             *   on a port during a timeout period. If more are received,
+                                             *   they are discarded. The counter is implemented per port
+                                             *   independently. However, the limit is used for all ports.                  */
+        } MCAST_STORM_LIMIT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_CONTROL;       /*!< (@ 0x00000040) Port Mirroring Configuration Register                      */
+
+        struct
+        {
+            __IOM uint32_t PORT : 2;         /*!< [1..0] The port number of the port that acts as the mirror port
+                                              *   and receives all mirrored frames. Valid setting range is
+                                              *   0 to 3.                                                                   */
+            uint32_t                    : 2;
+            __IOM uint32_t MIRROR_EN    : 1; /*!< [4..4] MIRROR_EN                                                          */
+            __IOM uint32_t ING_MAP_EN   : 1; /*!< [5..5] If set, the ingress map is enabled (MIRROR_ING_MAP).               */
+            __IOM uint32_t EG_MAP_EN    : 1; /*!< [6..6] If set, the egress map is enabled (MIRROR_EG_MAP).                 */
+            __IOM uint32_t ING_SA_MATCH : 1; /*!< [7..7] If set, only frames received on an ingress port with
+                                              *   a source address matching the value programmed in MIRROR_ISRC
+                                              *   registers are mirrored. Other frames are not mirrored.                    */
+            __IOM uint32_t ING_DA_MATCH : 1; /*!< [8..8] If set, only frames received on an ingress port with
+                                              *   a destination address matching the value programmed in
+                                              *   MIRROR_IDST registers are mirrored. Other frames are not
+                                              *   mirrored.                                                                 */
+            __IOM uint32_t EG_SA_MATCH : 1;  /*!< [9..9] If set, only frames transmitted on an egress port with
+                                              *   a source address matching the value programmed in MIRROR_ESRC
+                                              *   registers are mirrored. Other frames are not mirrored.                    */
+            __IOM uint32_t EG_DA_MATCH : 1;  /*!< [10..10] If set, only frames transmitted on an egress port with
+                                              *   a destination address matching the value programmed in
+                                              *   MIRROR_EDST registers are mirrored. Other frames are not
+                                              *   mirrored.                                                                 */
+            uint32_t : 21;
+        } MIRROR_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_EG_MAP;  /*!< (@ 0x00000044) Port Mirroring Egress Port Definition Register             */
+
+        struct
+        {
+            __IOM uint32_t EMAP : 4;   /*!< [3..0] Port Mirroring Egress Port Definitions                             */
+            uint32_t            : 28;
+        } MIRROR_EG_MAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ING_MAP; /*!< (@ 0x00000048) Port Mirroring Ingress Port Definition Register            */
+
+        struct
+        {
+            __IOM uint32_t IMAP : 4;   /*!< [3..0] Port Mirroring Ingress Port Definitions                            */
+            uint32_t            : 28;
+        } MIRROR_ING_MAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ISRC_0;  /*!< (@ 0x0000004C) Ingress Source MAC Address for Mirror Filtering
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t ISRC : 32;  /*!< [31..0] Ingress Source MAC Address for Mirror Filtering                   */
+        } MIRROR_ISRC_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ISRC_1;  /*!< (@ 0x00000050) Ingress Source MAC Address for Mirror Filtering
+                                        *                  Register 1                                                 */
+
+        struct
+        {
+            __IOM uint32_t ISRC : 16;  /*!< [15..0] Ingress Source MAC Address for Mirror Filtering                   */
+            uint32_t            : 16;
+        } MIRROR_ISRC_1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_IDST_0;  /*!< (@ 0x00000054) Ingress Destination MAC Address for Mirror Filtering
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t IDST : 32;  /*!< [31..0] Ingress Destination MAC Address for Mirror Filtering              */
+        } MIRROR_IDST_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_IDST_1;  /*!< (@ 0x00000058) Ingress Destination MAC Address for Mirror Filtering
+                                        *                  Register 1                                                 */
+
+        struct
+        {
+            __IOM uint32_t IDST : 16;  /*!< [15..0] Ingress Destination MAC Address for Mirror Filtering              */
+            uint32_t            : 16;
+        } MIRROR_IDST_1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ESRC_0;  /*!< (@ 0x0000005C) Egress Source MAC Address for Mirror Filtering
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t ESRC : 32;  /*!< [31..0] Egress Source MAC Address for Mirror Filtering                    */
+        } MIRROR_ESRC_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_ESRC_1;  /*!< (@ 0x00000060) Egress Source MAC Address for Mirror Filtering
+                                        *                  Register 1                                                 */
+
+        struct
+        {
+            __IOM uint32_t ESRC : 16;  /*!< [15..0] Egress Source MAC Address for Mirror Filtering                    */
+            uint32_t            : 16;
+        } MIRROR_ESRC_1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_EDST_0;  /*!< (@ 0x00000064) Egress Destination MAC Address for Mirror Filtering
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t EDST : 32;  /*!< [31..0] Egress Destination MAC Address for Mirror Filtering               */
+        } MIRROR_EDST_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_EDST_1;  /*!< (@ 0x00000068) Egress Destination MAC Address for Mirror Filtering
+                                        *                  Register 1                                                 */
+
+        struct
+        {
+            __IOM uint32_t EDST : 16;  /*!< [15..0] Egress Destination MAC Address for Mirror Filtering               */
+            uint32_t            : 16;
+        } MIRROR_EDST_1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIRROR_CNT;     /*!< (@ 0x0000006C) Mirror Filtering Count Value Register                      */
+
+        struct
+        {
+            __IOM uint32_t CNT : 8;    /*!< [7..0] Count Value for Mirror Filtering                                   */
+            uint32_t           : 24;
+        } MIRROR_CNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t UCAST_DEFAULT_MASK1; /*!< (@ 0x00000070) Unicast Default Mask Register 1                            */
+
+        struct
+        {
+            __IOM uint32_t UCASTDM1 : 4;    /*!< [3..0] Default Unicast Resolution Mask 1                                  */
+            uint32_t                : 28;
+        } UCAST_DEFAULT_MASK1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCAST_DEFAULT_MASK1; /*!< (@ 0x00000074) Broadcast Default Mask Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t BCASTDM1 : 4;    /*!< [3..0] Default Broadcast Resolution Mask 1                                */
+            uint32_t                : 28;
+        } BCAST_DEFAULT_MASK1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MCAST_DEFAULT_MASK1; /*!< (@ 0x00000078) Multicast Default Mask Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t MCASTDM1 : 4;    /*!< [3..0] Default Multicast Resolution Mask 1                                */
+            uint32_t                : 28;
+        } MCAST_DEFAULT_MASK1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PORT_XCAST_MASK_SEL; /*!< (@ 0x0000007C) Port Mask Select Register                                  */
+
+        struct
+        {
+            __IOM uint32_t MSEL : 4;        /*!< [3..0] Mask Select                                                        */
+            uint32_t            : 28;
+        } PORT_XCAST_MASK_SEL_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t QMGR_ST_MINCELLS;    /*!< (@ 0x00000088) Minimum Memory Cell Statistics Register                    */
+
+        struct
+        {
+            __IOM uint32_t STMINCELLS : 11; /*!< [10..0] Minimum Free Cell Indication                                      */
+            uint32_t                  : 21;
+        } QMGR_ST_MINCELLS_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t QMGR_RED_MIN4;          /*!< (@ 0x00000094) RED Minimum Threshold Register                             */
+
+        struct
+        {
+            __IOM uint32_t CFGRED_MINTH4 : 32; /*!< [31..0] Random Early Detection (RED) Minimum Threshold for Queues
+                                                *   0 to 3                                                                    */
+        } QMGR_RED_MIN4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t QMGR_RED_MAX4;          /*!< (@ 0x00000098) RED Maximum Threshold Register                             */
+
+        struct
+        {
+            __IOM uint32_t CFGRED_MAXTH4 : 32; /*!< [31..0] Random Early Detection (RED) Maximum Threshold for Queues
+                                                *   0 to 3                                                                    */
+        } QMGR_RED_MAX4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t QMGR_RED_CONFIG;      /*!< (@ 0x0000009C) RED Configuration Register                                 */
+
+        struct
+        {
+            __IOM uint32_t QUEUE_RED_EN : 4; /*!< [3..0] Enable Random Early Detection (RED) (when this bit is
+                                              *   1) or Tail Drop (when this bit is 0) congestion management
+                                              *   for a queue.                                                              */
+            uint32_t                    : 4;
+            __IOM uint32_t GACTIVITY_EN : 1; /*!< [8..8] Enable Averaging on Global Switch Activity (when this
+                                              *   bit is 1) or on port local activity (when this bit is 0)
+                                              *   only.                                                                     */
+            uint32_t : 23;
+        } QMGR_RED_CONFIG_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_STATUS;               /*!< (@ 0x000000A0) Input Memory Controller Status Register                    */
+
+        struct
+        {
+            __IM uint32_t CELLS_AVAILABLE : 24; /*!< [23..0] Total number of memory cells (128-byte units) available
+                                                 *   in the shared memory (real time).                                         */
+            __IM uint32_t CF_ERR  : 1;          /*!< [24..24] Cell Factory Empty Error                                         */
+            __IM uint32_t DE_ERR  : 1;          /*!< [25..25] Deallocation Error                                               */
+            __IM uint32_t DE_INIT : 1;          /*!< [26..26] Asserts during Memory Initialization (deallocation
+                                                 *   module)                                                                   */
+            __IM uint32_t MEM_FULL : 1;         /*!< [27..27] Latched Indication that Memory is or was Full                    */
+            uint32_t               : 4;
+        } IMC_STATUS_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_ERR_FULL;          /*!< (@ 0x000000A4) Input Port Memory Full and Truncation Indicator
+                                              *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IPC_ERR_FULL  : 4; /*!< [3..0] Memory was full at start of a frame reception.                     */
+            uint32_t                    : 12;
+            __IM uint32_t IPC_ERR_TRUNC : 4; /*!< [19..16] Memory became full while a frame was received and was
+                                              *   partly written into memory.                                               */
+            uint32_t : 12;
+        } IMC_ERR_FULL_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_ERR_IFACE;         /*!< (@ 0x000000A8) Input Port Memory Error Indicator Register                 */
+
+        struct
+        {
+            __IM uint32_t IPC_ERR_IFACE : 4; /*!< [3..0] Error indication on memory input (receive from MAC) that
+                                              *   a frame has been truncated and discarded.                                 */
+            uint32_t               : 12;
+            __IM uint32_t WBUF_OVF : 4;      /*!< [19..16] Error indicating an overflow in the input write buffer
+                                              *   to the memory controller (a small decoupling FIFO at every
+                                              *   MAC RX).                                                                  */
+            uint32_t : 12;
+        } IMC_ERR_IFACE_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_ERR_QOFLOW;  /*!< (@ 0x000000AC) Output Port Queue Overflow Indicator Register              */
+
+        struct
+        {
+            __IM uint32_t OP_ERR : 4;  /*!< [3..0] A frame cannot be stored in an output queue of the port
+                                        *   as the queue FIFO overflowed (write occurred into full
+                                        *   fifo). The frame is ignored but stays stored in memory.
+                                        *   This should not occur during normal operation. This is
+                                        *   a fatal error as the memory allocated by that frame is
+                                        *   not freed, and resulting in memory leakage.                               */
+            uint32_t : 28;
+        } IMC_ERR_QOFLOW_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IMC_CONFIG;              /*!< (@ 0x000000B0) Input Memory Controller Configuration Register             */
+
+        struct
+        {
+            __IOM uint32_t WFQ_EN : 1;          /*!< [0..0] Enable weighted fair queuing (when this bit is 1) or
+                                                 *   strict priority (when this bit is 0, default) output queue
+                                                 *   scheduling.                                                               */
+            __IOM uint32_t RSV_ENA         : 1; /*!< [1..1] Enable Memory Reservations to Operate                              */
+            __IOM uint32_t SPEED_HIPRI_THR : 3; /*!< [4..2] High-Priority Speed Threshold                                      */
+            __IOM uint32_t CTFL_EMPTY_MD   : 1; /*!< [5..5] When this bit is set to 0, a frame received in Cut-Through
+                                                 *   mode that cannot allocate an entry in the CTFL is forwarded
+                                                 *   as store and forward.                                                     */
+            uint32_t : 26;
+        } IMC_CONFIG_b;
+    };
+
+    union
+    {
+        __IM uint32_t IMC_ERR_ALLOC;     /*!< (@ 0x000000B4) Input Port Error Indicator Register                        */
+
+        struct
+        {
+            __IM uint32_t DISC_FULL : 4; /*!< [3..0] Per port discard indication due to memory pool going
+                                          *   empty. Per port indication that one of the queues was full
+                                          *   and a frame was discarded.                                                */
+            uint32_t                : 12;
+            __IM uint32_t DISC_LATE : 4; /*!< [19..16] Per port discard indication due to lateness in the
+                                          *   priority resolution. The priority resolution can be delayed
+                                          *   by the pattern matchers. If it arrives too late (after
+                                          *   approximately 100 bytes into the frame), the frame is discarded.          */
+            uint32_t : 12;
+        } IMC_ERR_ALLOC_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t GPARSER0;             /*!< (@ 0x000000C0) [n + 1]th Parser of 1st Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask will be compared with the data in the frame.
+                                              *   All bits having a 0 will be 0 for the compare, however
+                                              *   this requires the compare value to have those bits also
+                                              *   set to 0.                                                                 */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type/length field of the frame, that
+                                              *   is, 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see IPDATA). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field found within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored.                                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
+                                              *   the given offset and MASK_VAL2[7:0] represent the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields. For example, setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames. No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
+                                              *   When set, the parser reports a match if the byte at given
+                                              *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
+            uint32_t : 1;
+        } GPARSER0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER1;             /*!< (@ 0x000000C4) [n + 1]th Parser of 1st Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask will be compared with the data in the frame.
+                                              *   All bits having a 0 will be 0 for the compare, however
+                                              *   this requires the compare value to have those bits also
+                                              *   set to 0.                                                                 */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type/length field of the frame, that
+                                              *   is, 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see IPDATA). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field found within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored.                                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
+                                              *   the given offset and MASK_VAL2[7:0] represent the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields. For example, setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames. No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
+                                              *   When set, the parser reports a match if the byte at given
+                                              *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
+            uint32_t : 1;
+        } GPARSER1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER2;             /*!< (@ 0x000000C8) [n + 1]th Parser of 1st Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask will be compared with the data in the frame.
+                                              *   All bits having a 0 will be 0 for the compare, however
+                                              *   this requires the compare value to have those bits also
+                                              *   set to 0.                                                                 */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type/length field of the frame, that
+                                              *   is, 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see IPDATA). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field found within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored.                                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
+                                              *   the given offset and MASK_VAL2[7:0] represent the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields. For example, setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames. No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
+                                              *   When set, the parser reports a match if the byte at given
+                                              *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
+            uint32_t : 1;
+        } GPARSER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER3;             /*!< (@ 0x000000CC) [n + 1]th Parser of 1st Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask will be compared with the data in the frame.
+                                              *   All bits having a 0 will be 0 for the compare, however
+                                              *   this requires the compare value to have those bits also
+                                              *   set to 0.                                                                 */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type/length field of the frame, that
+                                              *   is, 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see IPDATA). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field found within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored.                                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
+                                              *   the given offset and MASK_VAL2[7:0] represent the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields. For example, setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames. No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
+                                              *   When set, the parser reports a match if the byte at given
+                                              *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
+            uint32_t : 1;
+        } GPARSER3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH0;            /*!< (@ 0x000000D0) Snoop Configuration for Arithmetic [n + 1]th
+                                            *                  Stage of 1st Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH1;            /*!< (@ 0x000000D4) Snoop Configuration for Arithmetic [n + 1]th
+                                            *                  Stage of 1st Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH2;            /*!< (@ 0x000000D8) Snoop Configuration for Arithmetic [n + 1]th
+                                            *                  Stage of 1st Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH3;            /*!< (@ 0x000000DC) Snoop Configuration for Arithmetic [n + 1]th
+                                            *                  Stage of 1st Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER4;             /*!< (@ 0x000000E0) [n - 3]th Parser of 2nd Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask are compared with the data in the frame. All
+                                              *   bits having a 0 will be 0 for the compare, however this
+                                              *   requires the compare value to have those bits also set
+                                              *   to 0.                                                                     */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type or length field of the frame, for
+                                              *   example 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see bit 26). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field located within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored. If the bit is set, but the frame is not
+                                              *   an IPv4/v6 frame the parser reports a no match and does
+                                              *   not continue to inspect the frame. When cleared, the offset
+                                              *   is used normally on all frames.                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
+                                              *   at the given offset and MASK_VAL2[7:0] represents the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields, (for example setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames). No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
+                                              *   set, the parser reports a match if the byte at given offset
+                                              *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
+            uint32_t : 1;
+        } GPARSER4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER5;             /*!< (@ 0x000000E4) [n - 3]th Parser of 2nd Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask are compared with the data in the frame. All
+                                              *   bits having a 0 will be 0 for the compare, however this
+                                              *   requires the compare value to have those bits also set
+                                              *   to 0.                                                                     */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type or length field of the frame, for
+                                              *   example 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see bit 26). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field located within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored. If the bit is set, but the frame is not
+                                              *   an IPv4/v6 frame the parser reports a no match and does
+                                              *   not continue to inspect the frame. When cleared, the offset
+                                              *   is used normally on all frames.                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
+                                              *   at the given offset and MASK_VAL2[7:0] represents the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields, (for example setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames). No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
+                                              *   set, the parser reports a match if the byte at given offset
+                                              *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
+            uint32_t : 1;
+        } GPARSER5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER6;             /*!< (@ 0x000000E8) [n - 3]th Parser of 2nd Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask are compared with the data in the frame. All
+                                              *   bits having a 0 will be 0 for the compare, however this
+                                              *   requires the compare value to have those bits also set
+                                              *   to 0.                                                                     */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type or length field of the frame, for
+                                              *   example 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see bit 26). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field located within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored. If the bit is set, but the frame is not
+                                              *   an IPv4/v6 frame the parser reports a no match and does
+                                              *   not continue to inspect the frame. When cleared, the offset
+                                              *   is used normally on all frames.                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
+                                              *   at the given offset and MASK_VAL2[7:0] represents the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields, (for example setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames). No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
+                                              *   set, the parser reports a match if the byte at given offset
+                                              *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
+            uint32_t : 1;
+        } GPARSER6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GPARSER7;             /*!< (@ 0x000000EC) [n - 3]th Parser of 2nd Block                              */
+
+        struct
+        {
+            __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
+                                              *   bit 30 = 1) or least significant bits of a 16-bit compare
+                                              *   value (if bit 28 = 1). When used as a mask (bit 28, 30
+                                              *   = 0, 0), the data from the frame is ANDed with this mask,
+                                              *   then compared to the compare value. All bits having a 1
+                                              *   in the mask are compared with the data in the frame. All
+                                              *   bits having a 0 will be 0 for the compare, however this
+                                              *   requires the compare value to have those bits also set
+                                              *   to 0.                                                                     */
+            __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
+                                              *   offset.                                                                   */
+            __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
+                                              *   within the frame. The offset value starts at 0 to indicate
+                                              *   the very first byte after offset start. The offset start
+                                              *   can be either the type or length field of the frame, for
+                                              *   example 0 = first byte of type/length field) or the payload
+                                              *   following an IP header (see bit 26). Valid values range
+                                              *   from 0 to 60.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
+                                              *   byte of the MAC destination address.                                      */
+            __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
+                                              *   1) and should be used. When this bit is 0, the parser result
+                                              *   always indicates "no match" and none of the other bits
+                                              *   are relevant.                                                             */
+            __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
+                                              *   are skipped and the parser starts operating at the first
+                                              *   byte following any VLAN tags. When cleared, the parser
+                                              *   starts with the first byte following the source MAC address.              */
+            __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
+                                              *   an IP header if an IP frame is processed. The following
+                                              *   fields are skipped:                                                       */
+            __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
+                                              *   field located within the IP header for both IPv4 and IPv6
+                                              *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
+                                              *   VLAN tags if present. The offset setting has no meaning
+                                              *   and is ignored. If the bit is set, but the frame is not
+                                              *   an IPv4/v6 frame the parser reports a no match and does
+                                              *   not continue to inspect the frame. When cleared, the offset
+                                              *   is used normally on all frames.                                           */
+            __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
+                                              *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
+                                              *   at the given offset and MASK_VAL2[7:0] represents the byte
+                                              *   following at offset + 1 which matches the network byte
+                                              *   order for 16-bit fields, (for example setting a compare
+                                              *   value of 0x0800 and offset 0 matches IP frames). No mask
+                                              *   is available in this mode.                                                */
+            __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
+                                              *   at offset failed.                                                         */
+            __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
+                                              *   set, the parser reports a match if the byte at given offset
+                                              *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
+            uint32_t : 1;
+        } GPARSER7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH4;            /*!< (@ 0x000000F0) Snoop Configuration for Arithmetic [n - 3]th
+                                            *                  Stage of 2nd Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH5;            /*!< (@ 0x000000F4) Snoop Configuration for Arithmetic [n - 3]th
+                                            *                  Stage of 2nd Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH6;            /*!< (@ 0x000000F8) Snoop Configuration for Arithmetic [n - 3]th
+                                            *                  Stage of 2nd Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GARITH7;            /*!< (@ 0x000000FC) Snoop Configuration for Arithmetic [n - 3]th
+                                            *                  Stage of 2nd Block                                         */
+
+        struct
+        {
+            __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
+            uint32_t                  : 4;
+            __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
+            __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
+            __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
+            __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
+            uint32_t                  : 1;
+            __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
+            __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
+            uint32_t                  : 2;
+            __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
+            uint32_t                  : 10;
+        } GARITH7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VLAN_PRIORITY[4];  /*!< (@ 0x00000100) VLAN Priority Register [0..3]                              */
+
+        struct
+        {
+            __IOM uint32_t PRIORITY0 : 3; /*!< [2..0] Priority 0 Setting                                                 */
+            __IOM uint32_t PRIORITY1 : 3; /*!< [5..3] Priority 1 Setting                                                 */
+            __IOM uint32_t PRIORITY2 : 3; /*!< [8..6] Priority 2 Setting                                                 */
+            __IOM uint32_t PRIORITY3 : 3; /*!< [11..9] Priority 3 Setting                                                */
+            __IOM uint32_t PRIORITY4 : 3; /*!< [14..12] Priority 4 Setting                                               */
+            __IOM uint32_t PRIORITY5 : 3; /*!< [17..15] Priority 5 Setting                                               */
+            __IOM uint32_t PRIORITY6 : 3; /*!< [20..18] Priority 6 Setting                                               */
+            __IOM uint32_t PRIORITY7 : 3; /*!< [23..21] Priority 7 Setting                                               */
+            uint32_t                 : 8;
+        } VLAN_PRIORITY_b[4];
+    };
+    __IM uint32_t RESERVED3[12];
+
+    union
+    {
+        __IOM uint32_t IP_PRIORITY[4];     /*!< (@ 0x00000140) IP Priority Register [0..3]                                */
+
+        struct
+        {
+            __IOM uint32_t ADDRESS    : 8; /*!< [7..0] COS Table Address Specifying                                       */
+            __IOM uint32_t IPV6SELECT : 1; /*!< [8..8] IPv6 COS Table Selection                                           */
+            __IOM uint32_t PRIORITY   : 3; /*!< [11..9] COS Table Priority                                                */
+            uint32_t                  : 19;
+            __IOM uint32_t READ       : 1; /*!< [31..31] COS Table Operation Switching                                    */
+        } IP_PRIORITY_b[4];
+    };
+    __IM uint32_t RESERVED4[12];
+
+    union
+    {
+        __IOM uint32_t PRIORITY_CFG[4];        /*!< (@ 0x00000180) Priority Configuration Register [0..3]                     */
+
+        struct
+        {
+            __IOM uint32_t VLANEN        : 1;  /*!< [0..0] VLAN Priority Enable                                               */
+            __IOM uint32_t IPEN          : 1;  /*!< [1..1] IP Priority Enable                                                 */
+            __IOM uint32_t MACEN         : 1;  /*!< [2..2] MAC Based Priority Enable                                          */
+            __IOM uint32_t TYPE_EN       : 1;  /*!< [3..3] TYPE Based Priority Enable                                         */
+            __IOM uint32_t DEFAULTPRI    : 3;  /*!< [6..4] Default Priority Enable Setting                                    */
+            __IOM uint32_t PCP_REMAP_DIS : 1;  /*!< [7..7] Disables PCP remapping when set to 1.                              */
+            __IOM uint32_t PCP_REMAP     : 24; /*!< [31..8] PCP Remapping function                                            */
+        } PRIORITY_CFG_b[4];
+    };
+    __IM uint32_t RESERVED5[10];
+
+    union
+    {
+        __IOM uint32_t PRIORITY_TYPE1;    /*!< (@ 0x000001B8) Priority Type Register 1                                   */
+
+        struct
+        {
+            __IOM uint32_t TYPEVAL  : 16; /*!< [15..0] Type Priority                                                     */
+            __IOM uint32_t VALID    : 1;  /*!< [16..16] If set indicates, this register contains valid data.             */
+            __IOM uint32_t PRIORITY : 3;  /*!< [19..17] The priority value to use if a match occurs.                     */
+            uint32_t                : 12;
+        } PRIORITY_TYPE1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRIORITY_TYPE2;         /*!< (@ 0x000001BC) Priority Type Register 2                                   */
+
+        struct
+        {
+            __IOM uint32_t TYPEVAL  : 16;      /*!< [15..0] Type Priority                                                     */
+            __IOM uint32_t VALID    : 1;       /*!< [16..16] If set indicates, this register contains valid data.             */
+            __IOM uint32_t PRIORITY : 3;       /*!< [19..17] The priority value to use if a match occurs.                     */
+            uint32_t                : 12;
+        } PRIORITY_TYPE2_b;
+    };
+    __IOM R_ETHSW_MGMT_ADDR_Type MGMT_ADDR[4]; /*!< (@ 0x000001C0) MAC Address [0..3] for Bridge Protocol Frame
+                                                *                  Register                                                   */
+
+    union
+    {
+        __IOM uint32_t SRCFLT_ENA;             /*!< (@ 0x000001E0) MAC Source Address Filtering Enable Register               */
+
+        struct
+        {
+            __IOM uint32_t SRCENA : 3;         /*!< [2..0] Per-Source Port Enable                                             */
+            uint32_t              : 13;
+            __IOM uint32_t DSTENA : 4;         /*!< [19..16] Per-Destination Port Enable                                      */
+            uint32_t              : 12;
+        } SRCFLT_ENA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SRCFLT_CONTROL;         /*!< (@ 0x000001E4) MAC Source Address Filtering Control Register              */
+
+        struct
+        {
+            __IOM uint32_t MGMT_FWD      : 1;  /*!< [0..0] Management Forward Enable                                          */
+            __IOM uint32_t WATCHDOG_ENA  : 1;  /*!< [1..1] When set to 1, a watchdog is enabled.                              */
+            uint32_t                     : 14;
+            __IOM uint32_t WATCHDOG_TIME : 16; /*!< [31..16] Defines the watchdog expire time in milliseconds. The
+                                                *   default is 2000 milliseconds.                                             */
+        } SRCFLT_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SRCFLT_MACADDR_LO;       /*!< (@ 0x000001E8) Lower MAC Filtering Address Register                       */
+
+        struct
+        {
+            __IOM uint32_t SRCFLT_MACADDR : 32; /*!< [31..0] MAC address to use in source filtering                            */
+        } SRCFLT_MACADDR_LO_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SRCFLT_MACADDR_HI;       /*!< (@ 0x000001EC) Higher MAC Filtering Address Register                      */
+
+        struct
+        {
+            __IOM uint32_t SRCFLT_MACADDR : 16; /*!< [15..0] MAC address to use in source filtering                            */
+            __IOM uint32_t MASK           : 16; /*!< [31..16] The mask to apply to the last 16 bits of the MAC address         */
+        } SRCFLT_MACADDR_HI_b;
+    };
+    __IM uint32_t RESERVED6[3];
+
+    union
+    {
+        __IOM uint32_t PHY_FILTER_CFG;          /*!< (@ 0x000001FC) Debounce Filter Configuration Register                     */
+
+        struct
+        {
+            __IOM uint32_t FILTER_DURATION : 9; /*!< [8..0] This is the amount of time to wait after the last phy_link
+                                                 *   (ETHSW_PHYLINKn: n = port) transition from 0 to 1 to acknowledge
+                                                 *   the link-up condition.                                                    */
+            uint32_t              : 7;
+            __IOM uint32_t FLT_EN : 3;          /*!< [18..16] Per-port Enable Mask                                             */
+            uint32_t              : 13;
+        } PHY_FILTER_CFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYSTEM_TAGINFO[4];    /*!< (@ 0x00000200) One VLAN ID Field [0..3] for VLAN Input Manipulation       */
+
+        struct
+        {
+            __IOM uint32_t SYSVLANINFO : 16; /*!< [15..0] System VLAN Info (prio/cfi/vid) for Port n                        */
+            uint32_t                   : 16;
+        } SYSTEM_TAGINFO_b[4];
+    };
+    __IM uint32_t RESERVED7[12];
+
+    union
+    {
+        __IOM uint32_t AUTH_PORT[4];        /*!< (@ 0x00000240) Port [0..3] Authentication Control and Configuration       */
+
+        struct
+        {
+            __IOM uint32_t AUTH        : 1; /*!< [0..0] Authorized                                                         */
+            __IOM uint32_t CTRL_BOTH   : 1; /*!< [1..1] Controlled Both                                                    */
+            __IOM uint32_t EAPOL_EN    : 1; /*!< [2..2] EAPOL Enable                                                       */
+            __IOM uint32_t GUEST_EN    : 1; /*!< [3..3] Guest Enable                                                       */
+            __IOM uint32_t BPDU_EN     : 1; /*!< [4..4] BPDU Enable                                                        */
+            __IOM uint32_t EAPOL_UC_EN : 1; /*!< [5..5] EAPOL Unicast Enable                                               */
+            uint32_t                   : 5;
+            __IOM uint32_t ACHG_UNAUTH : 1; /*!< [11..11] Automatic Port Change to Unauthorized                            */
+            __IOM uint32_t EAPOL_PNUM  : 4; /*!< [15..12] EAPOL Port Number                                                */
+            __IOM uint32_t GUEST_MASK  : 4; /*!< [19..16] Destination port mask with all ports that are allowed
+                                             *   to receive non-EAPOL frames from this port while it is
+                                             *   unauthorized and guest (GUEST_EN) is enabled.                             */
+            uint32_t : 12;
+        } AUTH_PORT_b[4];
+    };
+    __IM uint32_t RESERVED8[12];
+
+    union
+    {
+        __IOM uint32_t VLAN_RES_TABLE[32]; /*!< (@ 0x00000280) 32 VLAN Domain Entries                                     */
+
+        struct
+        {
+            __IOM uint32_t PORTMASK : 4;   /*!< [3..0] When this bit is set to 1, it defines a port as a member
+                                            *   of the VLAN. When bit [28] or bit [29] is set, the tagged
+                                            *   bit mask is read/written instead of port mask.                            */
+            __IOM uint32_t VLANID    : 12; /*!< [15..4] The 12-bit VLAN identifier (VLAN ID) of the entry.                */
+            uint32_t                 : 12;
+            __IOM uint32_t RD_TAGMSK : 1;  /*!< [28..28] Read TAG Mask                                                    */
+            __IOM uint32_t WT_TAGMSK : 1;  /*!< [29..29] Write TAG Mask                                                   */
+            __IOM uint32_t WT_PRTMSK : 1;  /*!< [30..30] Write Port Mask                                                  */
+            uint32_t                 : 1;
+        } VLAN_RES_TABLE_b[32];
+    };
+
+    union
+    {
+        __IM uint32_t TOTAL_DISC;          /*!< (@ 0x00000300) Discarded Frame Total Number Register                      */
+
+        struct
+        {
+            __IM uint32_t TOTAL_DISC : 32; /*!< [31..0] Total number of incoming frames accepted by MAC RX but
+                                            *   discarded in the switch                                                   */
+        } TOTAL_DISC_b;
+    };
+
+    union
+    {
+        __IM uint32_t TOTAL_BYT_DISC;          /*!< (@ 0x00000304) Discarded Frame Total Bytes Register                       */
+
+        struct
+        {
+            __IM uint32_t TOTAL_BYT_DISC : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_DISC                      */
+        } TOTAL_BYT_DISC_b;
+    };
+
+    union
+    {
+        __IM uint32_t TOTAL_FRM;          /*!< (@ 0x00000308) Processed Frame Total Number Register                      */
+
+        struct
+        {
+            __IM uint32_t TOTAL_FRM : 32; /*!< [31..0] Total number of incoming frames processed by the switch           */
+        } TOTAL_FRM_b;
+    };
+
+    union
+    {
+        __IM uint32_t TOTAL_BYT_FRM;          /*!< (@ 0x0000030C) Processed Frame Total Bytes Register                       */
+
+        struct
+        {
+            __IM uint32_t TOTAL_BYT_FRM : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_FRM                       */
+        } TOTAL_BYT_FRM_b;
+    };
+    __IM uint32_t RESERVED9[12];
+
+    union
+    {
+        __IOM uint32_t IALK_CONTROL;        /*!< (@ 0x00000340) IA Lookup Function Enable Register                         */
+
+        struct
+        {
+            __IOM uint32_t IA_LKUP_ENA : 4; /*!< [3..0] Per-port Enable to the IA Lookup Table                             */
+            uint32_t                   : 12;
+            __IOM uint32_t CT_ENA      : 4; /*!< [19..16] Per-port Cut-Through Mode Enable                                 */
+            uint32_t                   : 12;
+        } IALK_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_OUI;          /*!< (@ 0x00000344) IA Frames MAC Address OUI Register                         */
+
+        struct
+        {
+            __IOM uint32_t IALK_OUI : 24; /*!< [23..0] IA Frames MAC Address OUI                                         */
+            uint32_t                : 8;
+        } IALK_OUI_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_ID_MIN;          /*!< (@ 0x00000348) Minimum Value ID MAC Address Register                      */
+
+        struct
+        {
+            __IOM uint32_t IALK_ID_MIN : 24; /*!< [23..0] Minimum value for the 24-bit ID in the MAC address                */
+            uint32_t                   : 8;
+        } IALK_ID_MIN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_ID_MAX;          /*!< (@ 0x0000034C) Maximum Value ID MAC Address Register                      */
+
+        struct
+        {
+            __IOM uint32_t IALK_ID_MAX : 24; /*!< [23..0] Maximum value for the 24-bit ID in the MAC address                */
+            uint32_t                   : 8;
+        } IALK_ID_MAX_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_ID_SUB;          /*!< (@ 0x00000350) Offset Value ID MAC Address Register                       */
+
+        struct
+        {
+            __IOM uint32_t IALK_ID_SUB : 24; /*!< [23..0] Offset value to subtract from the 24-bit ID in the MAC
+                                              *   address                                                                   */
+            uint32_t : 8;
+        } IALK_ID_SUB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_ID_CONFIG;              /*!< (@ 0x00000354) Configures Lookup Response Unknown IDs Register            */
+
+        struct
+        {
+            __IOM uint32_t INVLD_ID_FLOOD : 1;      /*!< [0..0] Setting this bit to 1 causes the IA table to return a
+                                                     *   found response for frames whose ID lies outside the ID
+                                                     *   range defined by [IA_LK_MAX:IA_LK_MIN] using INVLD_ID_FLOOD_MASK[3:0]
+                                                     *   bits.                                                                     */
+            __IOM uint32_t INVLD_ID_LRN_ENA : 1;    /*!< [1..1] Setting this bit to 1 allows automatic learning into
+                                                     *   the L2 FDB for frames with unknown IDs. When 0, learning
+                                                     *   is inhibited. This bit is only valid when INVLD_ID_FLOOD
+                                                     *   bit is set to 1.                                                          */
+            uint32_t                     : 2;
+            __IOM uint32_t INVLD_ID_PRIO : 3;       /*!< [6..4] Priority to use for found responses of an invalid ID.
+                                                     *   This bit is only valid when INVLD_ID_FLOOD bit is set to
+                                                     *   1.                                                                        */
+            __IOM uint32_t INVLD_ID_PRIO_VLD : 1;   /*!< [7..7] Indicates if the priority in INVLD_ID_PRIO is valid.
+                                                     *   This bit is valid only when INVLD_ID_FLOOD bit is set to
+                                                     *   1.                                                                        */
+            uint32_t                           : 8;
+            __IOM uint32_t INVLD_ID_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames whose ID is invalid.
+                                                     *   This bit is only valid when INVLD_ID_FLOOD bit is set to
+                                                     *   1. Setting this mask to 0 causes the frame to be dropped.                 */
+            uint32_t : 12;
+        } IALK_ID_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_VLAN_CONFIG;              /*!< (@ 0x00000358) Configure Lookup Response Unknown VLAN Register            */
+
+        struct
+        {
+            __IOM uint32_t UNKWN_VLAN_FLOOD : 1;      /*!< [0..0] When this bit is set to 1, a frame matching the OUI and
+                                                       *   with a valid ID but having a VLAN ID not matching any of
+                                                       *   the enabled values in IALK_VLANIDn causes the IA table
+                                                       *   to return a found response using the forwarding mask in
+                                                       *   UNKWN_VLAN_FLOOD_MASK[3:0].                                               */
+            __IOM uint32_t UNKWN_VLAN_LRN_ENA : 1;    /*!< [1..1] Setting this bit to 1 allows automatic learning into
+                                                       *   the L2 FDB for frames with unknown VLANs. When 0, learning
+                                                       *   is inhibited. This bit is only valid when UNKWN_VLAN_FLOOD
+                                                       *   bit is set to 1.                                                          */
+            uint32_t                       : 2;
+            __IOM uint32_t UNKWN_VLAN_PRIO : 3;       /*!< [6..4] Priority to use for found responses for an unknown VLAN.
+                                                       *   This bit is only valid when UNKWN_VLAN_FLOOD bit is set
+                                                       *   to 1.                                                                     */
+            __IOM uint32_t UNKWN_VLAN_PRIO_VLD : 1;   /*!< [7..7] Indicates if the priority in UNKWN_VLAN_PRIO[2:0] is
+                                                       *   valid. This bit is only valid when UNKWN_VLAN_FLOOD bit
+                                                       *   is set to 1.                                                              */
+            __IOM uint32_t VLANS_ENABLED : 3;         /*!< [10..8] Configures the logical geometry of the IA table by specifying
+                                                       *   the number of distinct VLAN IDs enabled. When set to 0,
+                                                       *   no VLANs are supported and the VLAN ID for the frames is
+                                                       *   ignored.                                                                  */
+            uint32_t                             : 5;
+            __IOM uint32_t UNKWN_VLAN_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames with an unknown VLAN
+                                                       *   ID.                                                                       */
+            uint32_t : 12;
+        } IALK_VLAN_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_TBL_ADDR;  /*!< (@ 0x0000035C) IA Lookup Database Address Register                        */
+
+        struct
+        {
+            __IOM uint32_t ADDR : 13;  /*!< [12..0] Defines the address to write to or read from the IA
+                                        *   Lookup table                                                              */
+            uint32_t            : 15;
+            __IOM uint32_t AINC : 4;   /*!< [31..28] Auto-Increment Control                                           */
+        } IALK_TBL_ADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IALK_TBL_DATA;    /*!< (@ 0x00000360) IA Lookup Database Data Register                           */
+
+        struct
+        {
+            __IOM uint32_t VALID : 1;    /*!< [0..0] Indicates whether the entry indicated by ADDR is valid
+                                          *   or not.                                                                   */
+            __IOM uint32_t FWD_MASK : 4; /*!< [4..1] Forwarding mask used for lookups that hit the entry and
+                                          *   when VALID is set to 1.                                                   */
+            uint32_t : 27;
+        } IALK_TBL_DATA_b;
+    };
+    __IM uint32_t RESERVED10[7];
+
+    union
+    {
+        __IOM uint32_t IALK_VLANID[4];            /*!< (@ 0x00000380) IA Lookup VLANIDn Register                                 */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12;           /*!< [11..0] Configure the VLAN ID to be used for VLAN n (n: IALK_VLAN_CONFIG.VLANS
+                                                   *   ENABLED). This bit is only valid when VLANID_ENA bit is
+                                                   *   set to 1. A value of 0 matches any VLAN ID.                               */
+            __IOM uint32_t VLANID_ENA : 1;        /*!< [12..12] Enables this VLAN ID. When set to 1, the VLAN ID of
+                                                   *   the frame is compared against VLANID[11:0].                               */
+            __IOM uint32_t VLANID_LRN_ENA : 1;    /*!< [13..13] Configures whether automatic learning in the L2 FDB
+                                                   *   is allowed for frames matching VLAN ID. This also includes
+                                                   *   frames that match the VLAN ID and that the entry in the
+                                                   *   IA table is invalid.                                                      */
+            uint32_t                         : 2;
+            __IOM uint32_t VLANID_FLOOD_MASK : 4; /*!< [19..16] Flooding mask to be used for frames matching this VLAN
+                                                   *   ID but with an invalid entry in the IA table.                             */
+            uint32_t                       : 8;
+            __IOM uint32_t VLANID_PRIO     : 3;   /*!< [30..28] Priority to use for found responses.                             */
+            __IOM uint32_t VLANID_PRIO_VLD : 1;   /*!< [31..31] Indicates if the priority in VLANID_PRIO[2:0] is valid.          */
+        } IALK_VLANID_b[4];
+    };
+    __IM uint32_t RESERVED11[12];
+
+    union
+    {
+        __IM uint32_t IMC_QLEVEL_P[4]; /*!< (@ 0x000003C0) Port [0..3] Queued Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t QUEUE0 : 4;  /*!< [3..0] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 0                                                         */
+            __IM uint32_t QUEUE1 : 4;  /*!< [7..4] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 1                                                         */
+            __IM uint32_t QUEUE2 : 4;  /*!< [11..8] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 2                                                         */
+            __IM uint32_t QUEUE3 : 4;  /*!< [15..12] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 3                                                         */
+            __IM uint32_t QUEUE4 : 4;  /*!< [19..16] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 4                                                         */
+            __IM uint32_t QUEUE5 : 4;  /*!< [23..20] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 5                                                         */
+            __IM uint32_t QUEUE6 : 4;  /*!< [27..24] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 6                                                         */
+            __IM uint32_t QUEUE7 : 4;  /*!< [31..28] A 4-bit value per queue indicating the number of frames
+                                        *   stored in queue 7                                                         */
+        } IMC_QLEVEL_P_b[4];
+    };
+    __IM uint32_t RESERVED12[12];
+
+    union
+    {
+        __IOM uint32_t LK_CTRL;               /*!< (@ 0x00000400) Learning/Lookup Function Global Configuration
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t LKUP_EN       : 1; /*!< [0..0] Lookup Controller Enable                                           */
+            __IOM uint32_t LEARN_EN      : 1; /*!< [1..1] Learning Enable                                                    */
+            __IOM uint32_t AGING_EN      : 1; /*!< [2..2] Aging Enable                                                       */
+            __IOM uint32_t ALW_MGRT      : 1; /*!< [3..3] Allow Migration                                                    */
+            __IOM uint32_t DISC_UNK_DEST : 1; /*!< [4..4] Discard Unknown Destination                                        */
+            uint32_t                     : 1;
+            __IOM uint32_t CLRTBL        : 1; /*!< [6..6] Clear Table                                                        */
+            __IOM uint32_t IND_VLAN      : 1; /*!< [7..7] Enable Independent VLAN Learning                                   */
+            uint32_t                     : 8;
+            __IOM uint32_t DISC_UNK_SRC  : 4; /*!< [19..16] Discard Unknown Source                                           */
+            uint32_t                     : 12;
+        } LK_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_STATUS;       /*!< (@ 0x00000404) Status Bits and Table Overflow Counter Register            */
+
+        struct
+        {
+            __IM uint32_t AGEADDR : 16; /*!< [15..0] Address the aging process will inspect when the aging
+                                         *   timer expires next time.                                                  */
+            __IOM uint32_t OVRF : 14;   /*!< [29..16] Counts number of table overflows that occurred (a new
+                                         *   address was learned but the table had no storage and an
+                                         *   older entry was deleted). The counter is cleared by writing
+                                         *   into the register and having bit 16 set to 1.                             */
+            uint32_t               : 1;
+            __IOM uint32_t LRNEVNT : 1; /*!< [31..31] Learn Event                                                      */
+        } LK_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_ADDR_CTRL;        /*!< (@ 0x00000408) Address Table Transaction Control and Read/Write
+                                             *                  Address                                                    */
+
+        struct
+        {
+            __IOM uint32_t ADDR_MSK : 12;   /*!< [11..0] Memory address for read and write transactions. This
+                                             *   is the address of a 69-bit entry. For the DEL_PORT bit,
+                                             *   a port mask can be provided in these bits instead of the
+                                             *   address. Bit 0 represents port 0, bit 1 port 1, and so
+                                             *   on.                                                                       */
+            uint32_t                   : 10;
+            __IOM uint32_t CLR_DYNAMIC : 1; /*!< [22..22] When set to 1, scans the complete table for valid dynamic
+                                             *   entries and deletes them (writes entry with all 0s). This
+                                             *   bit is cleared when the function has completed.                           */
+            __IOM uint32_t CLR_STATIC : 1;  /*!< [23..23] When set to 1, scans the complete table for valid static
+                                             *   entries and deletes them (writes entry with all 0s). This
+                                             *   bit is cleared when the function has completed.                           */
+            __IOM uint32_t GETLASTNEW : 1;  /*!< [24..24] When set to 1, retrieves the last source address that
+                                             *   was not found in the table and places it into LK_DATA_LO/HI/HI2.
+                                             *   The valid bit of the entry (bit LK_DATA_HI[16]) indicates
+                                             *   if the address is new (when valid bit is 1) or not (when
+                                             *   valid bit is 0) since the command was last issued.                        */
+            __IOM uint32_t WRITE     : 1;   /*!< [25..25] When set to 1, perform a single write transaction.               */
+            __IOM uint32_t READ      : 1;   /*!< [26..26] When set to 1, perform a single read transaction.                */
+            __IOM uint32_t WAIT_COMP : 1;   /*!< [27..27] When set to 1, instructs to stall the processor bus
+                                             *   until the transaction is completed. This allows performing
+                                             *   of consecutive writes into this register with varying commands
+                                             *   without the need for polling the BUSY bit.                                */
+            __IM uint32_t LOOKUP : 1;       /*!< [28..28] When set to 1, perform a lookup of the MAC address
+                                             *   given in LK_DATA_LO/HI/HI2.                                               */
+            __IOM uint32_t CLEAR : 1;       /*!< [29..29] When set to 1, writes all 0s to the entry selected
+                                             *   by the given address set in ADDR_MSK[11:0]. If this bit
+                                             *   is set together with the LOOKUP bit, first a lookup is
+                                             *   performed and if the lookup succeeds, the entry is then
+                                             *   deleted. The registers LK_DATA_LO/HI/HI2 are also cleared.
+                                             *   The memory address in this register is set from the lookup
+                                             *   result. If the lookup failed, the clear command is ignored
+                                             *   and memory address is arbitrary.                                          */
+            __IOM uint32_t DEL_PORT : 1;    /*!< [30..30] When set to 1, scans the complete table for valid dynamic
+                                             *   entries that contain the given ports in their destination
+                                             *   port mask and deletes the ports or the complete entry.
+                                             *   The port mask is provided in the ADDR_MSK[3:0] when writing
+                                             *   this register (1 bit per port, bit 0 = port 0, bit 1 =
+                                             *   port 1, and so on).                                                       */
+            __IM uint32_t BUSY : 1;         /*!< [31..31] Transaction Busy Indication                                      */
+        } LK_ADDR_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_DATA_LO;       /*!< (@ 0x0000040C) Lower 32-Bit Data of Lookup Memory Entry                   */
+
+        struct
+        {
+            __IOM uint32_t MEMDATA : 32; /*!< [31..0] Memory Data [31:0]                                                */
+        } LK_DATA_LO_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_DATA_HI;       /*!< (@ 0x00000410) Higher 25-Bit Data of Lookup Memory Entry                  */
+
+        struct
+        {
+            __IOM uint32_t MEMDATA : 25; /*!< [24..0] Memory Data [56:32]                                               */
+            uint32_t               : 7;
+        } LK_DATA_HI_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_DATA_HI2;    /*!< (@ 0x00000414) Higher2 12-Bit Data of Lookup Memory Entry                 */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IOM uint32_t MEMDATA : 12; /*!< [19..8] Memory Data [68:57]                                               */
+            uint32_t               : 12;
+        } LK_DATA_HI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_LEARNCOUNT;       /*!< (@ 0x00000418) Learned Address Count Register                             */
+
+        struct
+        {
+            __IOM uint32_t LEARNCOUNT : 13; /*!< [12..0] Number of Learned Addresses                                       */
+            uint32_t                  : 17;
+            __IOM uint32_t WRITE_MD   : 2;  /*!< [31..30] These bits define how the LEARNCOUNT value is modified
+                                             *   when writing into the register:                                           */
+        } LK_LEARNCOUNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LK_AGETIME;       /*!< (@ 0x0000041C) Period of the Aging Timer                                  */
+
+        struct
+        {
+            __IOM uint32_t AGETIME : 24; /*!< [23..0] 24-bit Timer Value                                                */
+            uint32_t               : 8;
+        } LK_AGETIME_b;
+    };
+    __IM uint32_t RESERVED13[24];
+
+    union
+    {
+        __IOM uint32_t MGMT_TAG_CONFIG;   /*!< (@ 0x00000480) Management Tag Configuration Register                      */
+
+        struct
+        {
+            __IOM uint32_t ENABLE    : 1; /*!< [0..0] Enable Management Tag Insertion Module                             */
+            __IOM uint32_t AL_FRAMES : 1; /*!< [1..1] Enable Tag Insertion for All Frames                                */
+            uint32_t                 : 2;
+            __IOM uint32_t TYPE1_EN  : 1; /*!< [4..4] When set, frames with a Type field that match the value
+                                           *   in PRIORITY_TYPE1.TYPEVAL[15:0] have management tag inserted.
+                                           *   This is in addition to BPDU frames which always have tag
+                                           *   inserted.                                                                 */
+            __IOM uint32_t TYPE2_EN : 1;  /*!< [5..5] When set, frames with a Type field that match the value
+                                           *   in PRIORITY_TYPE2.TYPEVAL[15:0] have management tag inserted.
+                                           *   This is in addition to BPDU frames which always have tag
+                                           *   inserted.                                                                 */
+            uint32_t                : 10;
+            __IOM uint32_t TAGFIELD : 16; /*!< [31..16] The value of the tag that is found in the first Type/Length
+                                           *   field of the frame to identify that the control information
+                                           *   is present within a frame. For example, [31:24] = first
+                                           *   octet, [23:16] = 2nd octet.                                               */
+        } MGMT_TAG_CONFIG_b;
+    };
+    __IM uint32_t RESERVED14[32];
+
+    union
+    {
+        __IOM uint32_t TSM_CONFIG;             /*!< (@ 0x00000504) Timestamping Control Module Configuration Register         */
+
+        struct
+        {
+            __IOM uint32_t IRQ_EN         : 1; /*!< [0..0] Final Interrupt enable                                             */
+            __IOM uint32_t IRQ_TEST       : 1; /*!< [1..1] Software controlled interrupt for testing purposes                 */
+            __IOM uint32_t IRQ_TSFIFO_OVR : 1; /*!< [2..2] Trigger interrupt enable for Transmit Timestamp Capture
+                                                *   Overflow event                                                            */
+            uint32_t                      : 1;
+            __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Trigger interrupt enable for the timer offset
+                                                *   event                                                                     */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Trigger interrupt enable for the timer periodical
+                                                *   event                                                                     */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Trigger interrupt enable for the timer wrap
+                                                *   (reached its maximum)                                                     */
+            uint32_t                 : 2;
+            __IOM uint32_t IRQ_TX_EN : 4;      /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt Enable             */
+            uint32_t                 : 12;
+        } TSM_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TSM_IRQ_STAT_ACK;       /*!< (@ 0x00000508) Interrupt Status/Acknowledge Register                      */
+
+        struct
+        {
+            __IM uint32_t  IRQ_STAT       : 1; /*!< [0..0] Interrupt Pending Status                                           */
+            __IOM uint32_t IRQ_TEST       : 1; /*!< [1..1] Test Interrupt Pending Status                                      */
+            __IM uint32_t  IRQ_TSFIFO_OVR : 1; /*!< [2..2] Transmit Timestamp Capture Overflow Interrupt Pending
+                                                *   Status                                                                    */
+            uint32_t                      : 1;
+            __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Offset Interrupt Pending Status                          */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Periodical Interrupt Pending Status                      */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Overflow Interrupt Pending Status                      */
+            uint32_t                      : 2;
+            __IOM uint32_t IRQ_TX         : 4; /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt                    */
+            uint32_t                      : 12;
+        } TSM_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTP_DOMAIN;      /*!< (@ 0x0000050C) Domain Number of PTP Frame                                 */
+
+        struct
+        {
+            __IOM uint32_t DOMAIN0 : 8; /*!< [7..0] DomainNumber to Match Against for Timer 0                          */
+            __IOM uint32_t DOMAIN1 : 8; /*!< [15..8] DomainNumber to Match Against for Timer 1                         */
+            uint32_t               : 16;
+        } PTP_DOMAIN_b;
+    };
+    __IM uint32_t RESERVED15[12];
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P0_T0;    /*!< (@ 0x00000540) Port 0 Peer Delay Value for Timer 0 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   0                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P0_T0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P0_T1;    /*!< (@ 0x00000544) Port 0 Peer Delay Value for Timer 1 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   1                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P0_T1_b;
+    };
+    __IM uint32_t RESERVED16[2];
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P1_T0;    /*!< (@ 0x00000550) Port 1 Peer Delay Value for Timer 0 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   0                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P1_T0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P1_T1;    /*!< (@ 0x00000554) Port 1 Peer Delay Value for Timer 1 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   1                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P1_T1_b;
+    };
+    __IM uint32_t RESERVED17[2];
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P2_T0;    /*!< (@ 0x00000560) Port 2 Peer Delay Value for Timer 0 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   0                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P2_T0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P2_T1;    /*!< (@ 0x00000564) Port 2 Peer Delay Value for Timer 1 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   1                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P2_T1_b;
+    };
+    __IM uint32_t RESERVED18[2];
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P3_T0;    /*!< (@ 0x00000570) Port 3 Peer Delay Value for Timer 0 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   0                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P3_T0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEERDELAY_P3_T1;    /*!< (@ 0x00000574) Port 3 Peer Delay Value for Timer 1 (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
+                                            *   1                                                                         */
+            uint32_t : 2;
+        } PEERDELAY_P3_T1_b;
+    };
+    __IM uint32_t RESERVED19[18];
+
+    union
+    {
+        __IOM uint32_t TS_FIFO_STATUS;  /*!< (@ 0x000005C0) Transmit Timestamp FIFO Status Register                    */
+
+        struct
+        {
+            __IM uint32_t FF_VALID : 4; /*!< [3..0] Per-port indication that a valid timestamp is available
+                                         *   in the corresponding FIFO of the port                                     */
+            uint32_t              : 12;
+            __IOM uint32_t FF_OVR : 4;  /*!< [19..16] Per-port indication that a timestamp cannot be written
+                                         *   to the FIFO because of the FIFO being full.                               */
+            uint32_t : 12;
+        } TS_FIFO_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TS_FIFO_READ_CTRL; /*!< (@ 0x000005C4) Transmit Timestamp FIFO Read Control Register              */
+
+        struct
+        {
+            __IOM uint32_t PORT_NUM : 2;  /*!< [1..0] Port Number to Read from                                           */
+            uint32_t                : 2;
+            __IM uint32_t TS_VALID  : 1;  /*!< [4..4] When reading from this register, this bit is 1 if the
+                                           *   FIFO indicated by PORT_NUM contained valid data.                          */
+            uint32_t             : 1;
+            __IM uint32_t TS_SEL : 1;     /*!< [6..6] When TS_VALID is 1, TS_SEL indicates the timer used for
+                                           *   the read timestamp.                                                       */
+            uint32_t            : 1;
+            __IM uint32_t TS_ID : 7;      /*!< [14..8] When TS_VALID is 1, TS_ID indicates the ID specified
+                                           *   by the application through the management tag control information,
+                                           *   if present.                                                               */
+            uint32_t : 17;
+        } TS_FIFO_READ_CTRL_b;
+    };
+
+    union
+    {
+        __IM uint32_t TS_FIFO_READ_TIMESTAMP; /*!< (@ 0x000005C8) 32-bit Timestamp Value Read from FIFO                      */
+
+        struct
+        {
+            __IM uint32_t TIMESTAMP : 32;     /*!< [31..0] 32-bit timestamp value read from the FIFO                         */
+        } TS_FIFO_READ_TIMESTAMP_b;
+    };
+    __IM uint32_t RESERVED20[13];
+
+    union
+    {
+        __IOM uint32_t INT_CONFIG;            /*!< (@ 0x00000600) Interrupt Enable Configuration Register                    */
+
+        struct
+        {
+            __IOM uint32_t IRQ_EN     : 1;    /*!< [0..0] Interrupt Global Enable                                            */
+            __IOM uint32_t MDIO1      : 1;    /*!< [1..1] Enable Interrupt on Transaction Complete from MDIO Controller      */
+            uint32_t                  : 1;
+            __IOM uint32_t LK_NEW_SRC : 1;    /*!< [3..3] Enable Interrupt for New Source Address                            */
+            __IOM uint32_t IRQ_TEST   : 1;    /*!< [4..4] When set, an interrupt is triggered immediately. Can
+                                               *   be used to cause a software controlled interrupt for testing
+                                               *   purposes.                                                                 */
+            __IOM uint32_t DLR_INT       : 1; /*!< [5..5] Enable Interrupt for DLR                                           */
+            __IOM uint32_t PRP_INT       : 1; /*!< [6..6] Enable Interrupt for PRP                                           */
+            __IOM uint32_t HUB_INT       : 1; /*!< [7..7] Enable Interrupt for HUB                                           */
+            __IOM uint32_t IRQ_LINK      : 3; /*!< [10..8] Per Line Port Phy Link Change Interrupt Enable                    */
+            uint32_t                     : 5;
+            __IOM uint32_t IRQ_MAC_EEE   : 3; /*!< [18..16] Per Line Port MAC interrupt                                      */
+            uint32_t                     : 8;
+            __IOM uint32_t EFP_INT       : 1; /*!< [27..27] Enable Interrupt for Extended Frame Parser                       */
+            __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] MAC Address Source Filtering Watchdog                            */
+            __IOM uint32_t TSM_INT       : 1; /*!< [29..29] Enable Interrupt for TSM (Timer, Timestamping)                   */
+            __IOM uint32_t TDMA_INT      : 1; /*!< [30..30] Enable Interrupt for TDMA scheduler                              */
+            __IOM uint32_t PATTERN_INT   : 1; /*!< [31..31] Enable Interrupt for RX Pattern Matcher                          */
+        } INT_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INT_STAT_ACK;          /*!< (@ 0x00000604) Interrupt Status/ACK Register                              */
+
+        struct
+        {
+            __IM uint32_t  IRQ_PEND      : 1; /*!< [0..0] Interrupt Pending Status                                           */
+            __IOM uint32_t MDIO1         : 1; /*!< [1..1] Latched Interrupt Status for MDIO1                                 */
+            uint32_t                     : 1;
+            __IOM uint32_t LK_NEW_SRC    : 1; /*!< [3..3] Latched Interrupt Status for LK_NEW_SRC                            */
+            __IM uint32_t  IRQ_TEST      : 1; /*!< [4..4] Interrupt Status for IRQ_TEST                                      */
+            __IM uint32_t  DLR_INT       : 1; /*!< [5..5] Interrupt Pending Status from DLR Module                           */
+            __IM uint32_t  PRP_INT       : 1; /*!< [6..6] Interrupt Pending Status from PRP Module                           */
+            __IM uint32_t  HUB_INT       : 1; /*!< [7..7] Interrupt Pending Status from Hub Module                           */
+            __IOM uint32_t IRQ_LINK      : 3; /*!< [10..8] Interrupt Pending per Line Port Phy Link Change Interrupt         */
+            uint32_t                     : 5;
+            __IOM uint32_t IRQ_MAC_EEE   : 3; /*!< [18..16] Interrupt Pending Status per Line Port MAC Interrupt             */
+            uint32_t                     : 8;
+            __IOM uint32_t EFP_INT       : 1; /*!< [27..27] Interrupt from Extended Frame Parser                             */
+            __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] Interrupt Pending Status for MAC Source Filtering Watchdog       */
+            __IM uint32_t  TSM_INT       : 1; /*!< [29..29] Interrupt Pending Interrupt Indication from TSM (Timestamping)
+                                               *   module                                                                    */
+            __IM uint32_t TDMA_INT    : 1;    /*!< [30..30] Interrupt Pending Status from TDMA Scheduler                     */
+            __IM uint32_t PATTERN_INT : 1;    /*!< [31..31] Interrupt Pending Status from RX Pattern Matcher Module          */
+        } INT_STAT_ACK_b;
+    };
+    __IM uint32_t RESERVED21[30];
+
+    union
+    {
+        __IOM uint32_t ATIME_CTRL0;            /*!< (@ 0x00000680) Timer 0 Control Register (n = 0, 1)                        */
+
+        struct
+        {
+            __IOM uint32_t ENABLE   : 1;       /*!< [0..0] ENABLE                                                             */
+            __IOM uint32_t ONE_SHOT : 1;       /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum.
+                                                *   An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs
+                                                *   (if enabled) when the maximum is reached.                                 */
+            __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event                                                */
+            uint32_t                      : 1;
+            __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event                                            */
+            __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event                                    */
+            uint32_t                      : 3;
+            __IOM uint32_t RESTART        : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit)                             */
+            uint32_t                      : 1;
+            __IOM uint32_t CAPTURE        : 1; /*!< [11..11] Capture Time Value (Command Bit)                                 */
+            __IOM uint32_t CAPTURE_ALL    : 1; /*!< [12..12] Capture All Timers Value (Command Bit)                           */
+            uint32_t                      : 19;
+        } ATIME_CTRL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME0;             /*!< (@ 0x00000684) Timer 0 Count Register (n = 0, 1)                          */
+
+        struct
+        {
+            __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value                                                       */
+        } ATIME0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_OFFSET0;   /*!< (@ 0x00000688) Timer 0 Offset Register (n = 0, 1)                         */
+
+        struct
+        {
+            __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without
+                                         *   changing the drift correction                                             */
+        } ATIME_OFFSET0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_EVT_PERIOD0; /*!< (@ 0x0000068C) Timer 0 Periodic Event Register (n = 0, 1)                 */
+
+        struct
+        {
+            __IOM uint32_t PERIOD : 32;   /*!< [31..0] Value for generating periodic events                              */
+        } ATIME_EVT_PERIOD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_CORR0;          /*!< (@ 0x00000690) Timer 0 Correction Period Register (n = 0, 1)              */
+
+        struct
+        {
+            __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period                                                 */
+            uint32_t                   : 1;
+        } ATIME_CORR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_INC0;            /*!< (@ 0x00000694) Timer 0 Increment Register (n = 0, 1)                      */
+
+        struct
+        {
+            __IOM uint32_t CLK_PERIOD    : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds    */
+            uint32_t                     : 1;
+            __IOM uint32_t CORR_INC      : 7; /*!< [14..8] Correction Increment Value                                        */
+            uint32_t                     : 1;
+            __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value                                */
+            uint32_t                     : 9;
+        } ATIME_INC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_SEC0;        /*!< (@ 0x00000698) Timer 0 Seconds Time Register (n = 0, 1)                   */
+
+        struct
+        {
+            __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value                                                */
+        } ATIME_SEC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_OFFS_CORR0;       /*!< (@ 0x0000069C) Timer 0 Offset Correction Counter Register (n
+                                                *                  = 0, 1)                                                    */
+
+        struct
+        {
+            __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter                                         */
+        } ATIME_OFFS_CORR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_CTRL1;            /*!< (@ 0x000006A0) Timer 1 Control Register (n = 0, 1)                        */
+
+        struct
+        {
+            __IOM uint32_t ENABLE   : 1;       /*!< [0..0] ENABLE                                                             */
+            __IOM uint32_t ONE_SHOT : 1;       /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum.
+                                                *   An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs
+                                                *   (if enabled) when the maximum is reached.                                 */
+            __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event                                                */
+            uint32_t                      : 1;
+            __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event                                            */
+            __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event                                    */
+            uint32_t                      : 3;
+            __IOM uint32_t RESTART        : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit)                             */
+            uint32_t                      : 1;
+            __IOM uint32_t CAPTURE        : 1; /*!< [11..11] Capture Time Value (Command Bit)                                 */
+            __IOM uint32_t CAPTURE_ALL    : 1; /*!< [12..12] Capture All Timers Value (Command Bit)                           */
+            uint32_t                      : 19;
+        } ATIME_CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME1;             /*!< (@ 0x000006A4) Timer 1 Count Register (n = 0, 1)                          */
+
+        struct
+        {
+            __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value                                                       */
+        } ATIME1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_OFFSET1;   /*!< (@ 0x000006A8) Timer 1 Offset Register (n = 0, 1)                         */
+
+        struct
+        {
+            __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without
+                                         *   changing the drift correction                                             */
+        } ATIME_OFFSET1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_EVT_PERIOD1; /*!< (@ 0x000006AC) Timer 1 Periodic Event Register (n = 0, 1)                 */
+
+        struct
+        {
+            __IOM uint32_t PERIOD : 32;   /*!< [31..0] Value for generating periodic events                              */
+        } ATIME_EVT_PERIOD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_CORR1;          /*!< (@ 0x000006B0) Timer 1 Correction Period Register (n = 0, 1)              */
+
+        struct
+        {
+            __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period                                                 */
+            uint32_t                   : 1;
+        } ATIME_CORR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_INC1;            /*!< (@ 0x000006B4) Timer 1 Increment Register (n = 0, 1)                      */
+
+        struct
+        {
+            __IOM uint32_t CLK_PERIOD    : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds    */
+            uint32_t                     : 1;
+            __IOM uint32_t CORR_INC      : 7; /*!< [14..8] Correction Increment Value                                        */
+            uint32_t                     : 1;
+            __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value                                */
+            uint32_t                     : 9;
+        } ATIME_INC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_SEC1;        /*!< (@ 0x000006B8) Timer 1 Seconds Time Register (n = 0, 1)                   */
+
+        struct
+        {
+            __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value                                                */
+        } ATIME_SEC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ATIME_OFFS_CORR1;       /*!< (@ 0x000006BC) Timer 1 Offset Correction Counter Register (n
+                                                *                  = 0, 1)                                                    */
+
+        struct
+        {
+            __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter                                         */
+        } ATIME_OFFS_CORR1_b;
+    };
+    __IM uint32_t RESERVED22[16];
+
+    union
+    {
+        __IOM uint32_t MDIO_CFG_STATUS;  /*!< (@ 0x00000700) MDIO Configuration and Status Register                     */
+
+        struct
+        {
+            __IM uint32_t  BUSY     : 1; /*!< [0..0] MDIO Busy                                                          */
+            __IM uint32_t  READERR  : 1; /*!< [1..1] MDIO Read Error                                                    */
+            __IOM uint32_t HOLD     : 3; /*!< [4..2] MDIO Hold Time Setting                                             */
+            __IOM uint32_t DISPREAM : 1; /*!< [5..5] Disable Preamble                                                   */
+            uint32_t                : 1;
+            __IOM uint32_t CLKDIV   : 9; /*!< [15..7] MDIO Clock Divisor                                                */
+            uint32_t                : 16;
+        } MDIO_CFG_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MDIO_COMMAND;     /*!< (@ 0x00000704) MDIO PHY Command Register                                  */
+
+        struct
+        {
+            __IOM uint32_t REGADDR  : 5; /*!< [4..0] Register Address                                                   */
+            __IOM uint32_t PHYADDR  : 5; /*!< [9..5] PHY Address                                                        */
+            uint32_t                : 5;
+            __IOM uint32_t TRANINIT : 1; /*!< [15..15] If set to 1, a read transaction is initiated.                    */
+            uint32_t                : 16;
+        } MDIO_COMMAND_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MDIO_DATA;          /*!< (@ 0x00000708) MDIO Data Register                                         */
+
+        struct
+        {
+            __IOM uint32_t MDIO_DATA : 16; /*!< [15..0] MDIO_DATA                                                         */
+            uint32_t                 : 16;
+        } MDIO_DATA_b;
+    };
+    __IM uint32_t RESERVED23[61];
+
+    union
+    {
+        __IM uint32_t REV_P0;          /*!< (@ 0x00000800) Port 0 MAC Core Revision (n = 0 to 3)                      */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
+        } REV_P0_b;
+    };
+    __IM uint32_t RESERVED24;
+
+    union
+    {
+        __IOM uint32_t COMMAND_CONFIG_P0;       /*!< (@ 0x00000808) Port 0 Command Configuration Register (n = 0
+                                                 *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
+            __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
+            __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
+                                                 *   the IMC until the current frame is completed. This can
+                                                 *   cause the IPG between frames to be more than the value
+                                                 *   in TX_IPG_LENGTH.                                                         */
+            __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
+            __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
+            __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
+            uint32_t                    : 1;
+            __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
+            __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
+            __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
+            __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
+                                                 *   full-duplex only (set to 0).                                              */
+            __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
+            uint32_t                     : 1;
+            __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
+            uint32_t                     : 9;
+            __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
+            __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
+            __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
+                                                 *   register.                                                                 */
+            __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
+            __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
+            uint32_t                   : 2;
+            __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
+                                                 *   on transmit and on receive. The value is used when not
+                                                 *   overridden by the PTP auto-response function, pattern matchers
+                                                 *   or force forwarding information in a management tag.                      */
+            uint32_t : 1;
+        } COMMAND_CONFIG_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_0_P0;     /*!< (@ 0x0000080C) Port 0 MAC Address Register 0 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
+                                           *   byte is bits [7:0]. The MAC address is used on locally
+                                           *   generated frames such as pause frames, peer-delay response.               */
+        } MAC_ADDR_0_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_1_P0;     /*!< (@ 0x00000810) Port 0 MAC Address Register 1 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
+                                           *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
+            uint32_t : 16;
+        } MAC_ADDR_1_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRM_LENGTH_P0;       /*!< (@ 0x00000814) Port 0 Maximum Frame Length Register (n = 0 to
+                                             *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
+            uint32_t                  : 18;
+        } FRM_LENGTH_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t PAUSE_QUANT_P0;       /*!< (@ 0x00000818) Port 0 MAC Pause Quanta (n = 0 to 3)                       */
+
+        struct
+        {
+            __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
+            uint32_t                  : 16;
+        } PAUSE_QUANT_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_LINK_QTRIG_P0;  /*!< (@ 0x0000081C) Port 0 Trigger Event Configuration Register (n
+                                            *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
+            uint32_t                  : 12;
+            __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
+                                            *   is transmitted from the ports indicated by PORT_MASK. A
+                                            *   single frame is transmitted per indicated port in PORT_MASK
+                                            *   among the queues indicated by QUEUE_MASK.                                 */
+            uint32_t                 : 4;
+            __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
+                                            *   a frame was transmitted. When MODE is set to 0, TRIGGERED
+                                            *   is always 0. This flag clears when the register is written.               */
+            __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
+                                            *   set to 1, the Link Queue Trigger occurs only if the DLR
+                                            *   state machine is in the NORMAL or FAULT state.                            */
+            __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
+                                            *   This is to prevent sending multiple frames due to link
+                                            *   flapping.                                                                 */
+            __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
+                                            *   When the link status (phy_link) transitions from 1 ->
+                                            *   0, a trigger event is generated to the memory controller
+                                            *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
+        } MAC_LINK_QTRIG_P0_b;
+    };
+    __IM uint32_t RESERVED25[4];
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY1_P0;  /*!< (@ 0x00000830) Port 0 PTP Clock Identity 1 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
+            __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
+            __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
+            __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
+        } PTPCLOCKIDENTITY1_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY2_P0;  /*!< (@ 0x00000834) Port 0 PTP Clock Identity 2 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
+            __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
+            __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
+            __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
+        } PTPCLOCKIDENTITY2_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPAUTORESPONSE_P0; /*!< (@ 0x00000838) Port 0 PTP Auto Response Register (n = 0 to 2)             */
+
+        struct
+        {
+            __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
+            __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
+            uint32_t                : 14;
+            __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
+            __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
+        } PTPAUTORESPONSE_P0_b;
+    };
+    __IM uint32_t RESERVED26;
+
+    union
+    {
+        __IOM uint32_t STATUS_P0;          /*!< (@ 0x00000840) Port 0 Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
+            __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
+            __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
+            __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
+                                            *   never occur during normal operation.                                      */
+            __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
+                                            *   to complete in time before the next frame was received
+                                            *   at the port. This should never occur under normal operation.
+                                            *   The cause could be from IPG violations in the received
+                                            *   frames.                                                                   */
+            __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
+                                            *   to clause 30.14.1.2 of the 802.3br specification                          */
+            uint32_t : 23;
+        } STATUS_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TX_IPG_LENGTH_P0;      /*!< (@ 0x00000844) Port 0 Transmit IPG Length Register (n = 0 to
+                                               *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
+                                               *   are in the range of 8 to 31.                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
+            uint32_t                  : 11;
+        } TX_IPG_LENGTH_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_CTL_STAT_P0;        /*!< (@ 0x00000848) Port 0 MAC EEE Functions Control and Status (n
+                                                *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
+            __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
+            __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
+            uint32_t                    : 5;
+            __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
+            __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
+            __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
+            __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
+                                                *   available for transmission.                                               */
+            __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
+            uint32_t                      : 3;
+            __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
+            __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
+                                                *   MAC                                                                       */
+            __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
+            uint32_t                   : 1;
+            __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
+            uint32_t                   : 11;
+        } EEE_CTL_STAT_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_IDLE_TIME_P0;       /*!< (@ 0x0000084C) Port 0 EEE Idle Time Register (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
+                                                *   of LPI begins. A 32-bit value in steps of 32 switch operating
+                                                *   clock cycles. A value of 0 disables the timer. The value
+                                                *   must be set to 1 less count.                                              */
+        } EEE_IDLE_TIME_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_TWSYS_TIME_P0;      /*!< (@ 0x00000850) Port 0 EEE Wake Up Time Register (n = 0 to 2)              */
+
+        struct
+        {
+            __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
+                                                *   to begin transmitting the first frame again. A 32-bit value
+                                                *   in steps of switch operating clock cycles. A value of 0
+                                                *   disables the timer. The value must be set to 1 less count.                */
+        } EEE_TWSYS_TIME_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IDLE_SLOPE_P0;       /*!< (@ 0x00000854) Port 0 MAC Traffic Shaper Bandwidth Control                */
+
+        struct
+        {
+            __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
+            uint32_t                  : 21;
+        } IDLE_SLOPE_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CT_DELAY_P0;      /*!< (@ 0x00000858) Port 0 Cut-Through Delay Indication Register               */
+
+        struct
+        {
+            __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
+                                          *   of the MII PHY interface)                                                 */
+            uint32_t : 23;
+        } CT_DELAY_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BR_CONTROL_P0;            /*!< (@ 0x0000085C) Port 0 802.3br Frame Configuration Register                */
+
+        struct
+        {
+            __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
+            __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
+                                                  *   preemption operation.                                                     */
+            __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
+                                                  *   frames.                                                                   */
+            uint32_t                      : 1;
+            __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
+            uint32_t                      : 2;
+            __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
+            uint32_t                      : 1;
+            __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
+                                                  *   except the SFD are 0x55. When set to 0, only the last 2
+                                                  *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
+                                                  *   It is recommended to set this bit to 1 to comply with the
+                                                  *   802.3br specification. This bit must be set to 0 if only
+                                                  *   non-802.3br traffic is expected (for example, normal Ethernet
+                                                  *   traffic) and if custom preamble is used.                                  */
+            __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
+                                                  *   SMDs and assumes all frames are express frames. This bit
+                                                  *   must be set to 0 for correct operation with 802.3br, and
+                                                  *   can be set to 1 when 802.3br is not enabled to avoid false
+                                                  *   detection of SMDs.                                                        */
+            __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
+                                                  *   frames is enabled. When set to 1, the frame contents and
+                                                  *   frame length checks are also performed on these frames.
+                                                  *   The mCRC is always checked regardless of the value of this
+                                                  *   register. This bit must be set to 0 to be compliant with
+                                                  *   the functionality described in IEEE 802.3br.                              */
+            __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for transmitted frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for received frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            uint32_t : 11;
+        } BR_CONTROL_P0_b;
+    };
+    __IM uint32_t RESERVED27[2];
+
+    union
+    {
+        __IM uint32_t AFRAMESTRANSMITTEDOK_P0; /*!< (@ 0x00000868) Port 0 MAC Transmitted Valid Frame Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                *   Transmitted, including pause.                                             */
+        } AFRAMESTRANSMITTEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMESRECEIVEDOK_P0;  /*!< (@ 0x0000086C) Port 0 MAC Received Valid Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                              *   Received, including pause.                                                */
+        } AFRAMESRECEIVEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P0; /*!< (@ 0x00000870) Port 0 MAC FCS Error Frame Count Register (n
+                                                     *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                     *   Length but CRC error.                                                     */
+        } AFRAMECHECKSEQUENCEERRORS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AALIGNMENTERRORS_P0;   /*!< (@ 0x00000874) Port 0 MAC Alignment Error Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
+                                              *   of Nibbles (MII) Received.                                                */
+        } AALIGNMENTERRORS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSTRANSMITTEDOK_P0; /*!< (@ 0x00000878) Port 0 MAC Transmitted Valid Frame Octets Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                                *   only) of MAC Valid Transmitted.                                           */
+        } AOCTETSTRANSMITTEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSRECEIVEDOK_P0;   /*!< (@ 0x0000087C) Port 0 MAC Received Valid Frame Octets Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                               *   only) of MAC Valid Received.                                              */
+        } AOCTETSRECEIVEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ATXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000880) Port 0 MAC Transmitted Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Transmitted.                                                        */
+        } ATXPAUSEMACCTRLFRAMES_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ARXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000884) Port 0 MAC Received Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Received.                                                           */
+        } ARXPAUSEMACCTRLFRAMES_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINERRORS_P0;       /*!< (@ 0x00000888) Port 0 MAC Input Error Count Register (n = 0
+                                            *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
+                                            *   During Reception such as CRC, Length, PHY Error, RX FIFO
+                                            *   Overflow.                                                                 */
+        } IFINERRORS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTERRORS_P0;       /*!< (@ 0x0000088C) Port 0 MAC Output Error Count Register (n = 0
+                                             *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
+                                             *   Transmitted with PHY error.                                               */
+        } IFOUTERRORS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINUCASTPKTS_P0;      /*!< (@ 0x00000890) Port 0 MAC Received Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINUCASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINMULTICASTPKTS_P0;  /*!< (@ 0x00000894) Port 0 MAC Received Multicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINMULTICASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINBROADCASTPKTS_P0;  /*!< (@ 0x00000898) Port 0 MAC Received Broadcast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Received.                                                     */
+        } IFINBROADCASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTDISCARDS_P0;     /*!< (@ 0x0000089C) Port 0 MAC Discarded Outbound Frame Count Register
+                                             *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
+        } IFOUTDISCARDS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTUCASTPKTS_P0;     /*!< (@ 0x000008A0) Port 0 MAC Transmitted Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTUCASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTMULTICASTPKTS_P0; /*!< (@ 0x000008A4) Port 0 MAC Transmitted Multicast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTMULTICASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTBROADCASTPKTS_P0; /*!< (@ 0x000008A8) Port 0 MAC Transmitted Broadcast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTBROADCASTPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSDROPEVENTS_P0; /*!< (@ 0x000008AC) Port 0 MAC Dropped Frame Count Register (n =
+                                                *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
+                                                *   Full at frame start.                                                      */
+        } ETHERSTATSDROPEVENTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOCTETS_P0; /*!< (@ 0x000008B0) Port 0 MAC All Frame Octets Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
+        } ETHERSTATSOCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS_P0; /*!< (@ 0x000008B4) Port 0 MAC All Frame Count Register (n = 0 to
+                                          *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
+        } ETHERSTATSPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P0; /*!< (@ 0x000008B8) Port 0 MAC Too Short Frame Count Register (n
+                                                   *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                                   *   Good CRC.                                                                 */
+        } ETHERSTATSUNDERSIZEPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOVERSIZEPKTS_P0; /*!< (@ 0x000008BC) Port 0 MAC Too Long Frame Count Register (n =
+                                                  *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                                  *   Good CRC.                                                                 */
+        } ETHERSTATSOVERSIZEPKTS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS64OCTETS_P0; /*!< (@ 0x000008C0) Port 0 MAC 64 Octets Frame Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                  *   Good and Bad (Packet Size: 64 bytes).                                     */
+        } ETHERSTATSPKTS64OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P0; /*!< (@ 0x000008C4) Port 0 MAC 65 to 127 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                       *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
+        } ETHERSTATSPKTS65TO127OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P0; /*!< (@ 0x000008C8) Port 0 MAC 128 to 255 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
+        } ETHERSTATSPKTS128TO255OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P0; /*!< (@ 0x000008CC) Port 0 MAC 256 to 511 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
+        } ETHERSTATSPKTS256TO511OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P0; /*!< (@ 0x000008D0) Port 0 MAC 512 to 1023 Octets Frame Count Register
+                                                         *              (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                         *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
+        } ETHERSTATSPKTS512TO1023OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P0; /*!< (@ 0x000008D4) Port 0 MAC 1024 to 1518 Octets Frame Count Register
+                                                          *             (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                          *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
+        } ETHERSTATSPKTS1024TO1518OCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P0; /*!< (@ 0x000008D8) Port 0 MAC Over 1519 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
+                                                       *   Good and Bad (Packet Size: over 1519 bytes).                              */
+        } ETHERSTATSPKTS1519TOXOCTETS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSJABBERS_P0; /*!< (@ 0x000008DC) Port 0 MAC Jabbers Frame Count Register (n =
+                                             *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                             *   Bad CRC.                                                                  */
+        } ETHERSTATSJABBERS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSFRAGMENTS_P0; /*!< (@ 0x000008E0) Port 0 MAC Fragment Frame Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                               *   Bad CRC.                                                                  */
+        } ETHERSTATSFRAGMENTS_P0_b;
+    };
+    __IM uint32_t RESERVED28;
+
+    union
+    {
+        __IM uint32_t VLANRECEIVEDOK_P0;     /*!< (@ 0x000008E8) Port 0 MAC Received VLAN Tagged Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Received.                                                   */
+        } VLANRECEIVEDOK_P0_b;
+    };
+    __IM uint32_t RESERVED29[2];
+
+    union
+    {
+        __IM uint32_t VLANTRANSMITTEDOK_P0;  /*!< (@ 0x000008F4) Port 0 MAC Transmitted VLAN Tagged Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Transmitted.                                                */
+        } VLANTRANSMITTEDOK_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRAMESRETRANSMITTED_P0; /*!< (@ 0x000008F8) Port 0 MAC Retransmitted Frame Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
+                                               *   Frames that experienced a collision and were retransmitted.               */
+        } FRAMESRETRANSMITTED_P0_b;
+    };
+    __IM uint32_t RESERVED30;
+
+    union
+    {
+        __IM uint32_t STATS_HIWORD_P0;       /*!< (@ 0x00000900) Port 0 MAC Statistics Counter High Word Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
+                                              *   Counter Last Read                                                         */
+        } STATS_HIWORD_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CTRL_P0;   /*!< (@ 0x00000904) Port 0 MAC Statistics Control Register (n = 0
+                                         *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
+            __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
+            uint32_t               : 30;
+        } STATS_CTRL_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUELO_P0;       /*!< (@ 0x00000908) Port 0 MAC Statistics Clear Value Lower Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUELO_P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUEHI_P0;       /*!< (@ 0x0000090C) Port 0 MAC Statistics Clear Value Higher Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUEHI_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADEFERRED_P0;        /*!< (@ 0x00000910) Port 0 MAC Deferred Count Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
+                                            *   without collision but was deferred at begin.                              */
+        } ADEFERRED_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AMULTIPLECOLLISIONS_P0;   /*!< (@ 0x00000914) Port 0 MAC Multiple Collision Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                 *   Transmit after multiple collisions.                                       */
+        } AMULTIPLECOLLISIONS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASINGLECOLLISIONS_P0;      /*!< (@ 0x00000918) Port 0 MAC Single Collision Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                  *   Transmit after single collision.                                          */
+        } ASINGLECOLLISIONS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ALATECOLLISIONS_P0;     /*!< (@ 0x0000091C) Port 0 MAC Late Collision Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
+                                               *   Collision. Frame was aborted and not retransmitted.                       */
+        } ALATECOLLISIONS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AEXCESSIVECOLLISIONS_P0; /*!< (@ 0x00000920) Port 0 MAC Excessive Collision Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
+                                                *   due to 16 consecutive collisions.                                         */
+        } AEXCESSIVECOLLISIONS_P0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACARRIERSENSEERRORS_P0; /*!< (@ 0x00000924) Port 0 MAC Carrier Sense Error Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
+                                               *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
+                                               *   asserted.                                                                 */
+        } ACARRIERSENSEERRORS_P0_b;
+    };
+    __IM uint32_t RESERVED31[182];
+
+    union
+    {
+        __IM uint32_t REV_P1;          /*!< (@ 0x00000C00) Port 1 MAC Core Revision (n = 0 to 3)                      */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
+        } REV_P1_b;
+    };
+    __IM uint32_t RESERVED32;
+
+    union
+    {
+        __IOM uint32_t COMMAND_CONFIG_P1;       /*!< (@ 0x00000C08) Port 1 Command Configuration Register (n = 0
+                                                 *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
+            __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
+            __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
+                                                 *   the IMC until the current frame is completed. This can
+                                                 *   cause the IPG between frames to be more than the value
+                                                 *   in TX_IPG_LENGTH.                                                         */
+            __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
+            __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
+            __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
+            uint32_t                    : 1;
+            __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
+            __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
+            __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
+            __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
+                                                 *   full-duplex only (set to 0).                                              */
+            __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
+            uint32_t                     : 1;
+            __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
+            uint32_t                     : 9;
+            __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
+            __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
+            __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
+                                                 *   register.                                                                 */
+            __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
+            __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
+            uint32_t                   : 2;
+            __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
+                                                 *   on transmit and on receive. The value is used when not
+                                                 *   overridden by the PTP auto-response function, pattern matchers
+                                                 *   or force forwarding information in a management tag.                      */
+            uint32_t : 1;
+        } COMMAND_CONFIG_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_0_P1;     /*!< (@ 0x00000C0C) Port 1 MAC Address Register 0 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
+                                           *   byte is bits [7:0]. The MAC address is used on locally
+                                           *   generated frames such as pause frames, peer-delay response.               */
+        } MAC_ADDR_0_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_1_P1;     /*!< (@ 0x00000C10) Port 1 MAC Address Register 1 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
+                                           *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
+            uint32_t : 16;
+        } MAC_ADDR_1_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRM_LENGTH_P1;       /*!< (@ 0x00000C14) Port 1 Maximum Frame Length Register (n = 0 to
+                                             *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
+            uint32_t                  : 18;
+        } FRM_LENGTH_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t PAUSE_QUANT_P1;       /*!< (@ 0x00000C18) Port 1 MAC Pause Quanta (n = 0 to 3)                       */
+
+        struct
+        {
+            __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
+            uint32_t                  : 16;
+        } PAUSE_QUANT_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_LINK_QTRIG_P1;  /*!< (@ 0x00000C1C) Port 1 Trigger Event Configuration Register (n
+                                            *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
+            uint32_t                  : 12;
+            __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
+                                            *   is transmitted from the ports indicated by PORT_MASK. A
+                                            *   single frame is transmitted per indicated port in PORT_MASK
+                                            *   among the queues indicated by QUEUE_MASK.                                 */
+            uint32_t                 : 4;
+            __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
+                                            *   a frame was transmitted. When MODE is set to 0, TRIGGERED
+                                            *   is always 0. This flag clears when the register is written.               */
+            __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
+                                            *   set to 1, the Link Queue Trigger occurs only if the DLR
+                                            *   state machine is in the NORMAL or FAULT state.                            */
+            __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
+                                            *   This is to prevent sending multiple frames due to link
+                                            *   flapping.                                                                 */
+            __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
+                                            *   When the link status (phy_link) transitions from 1 ->
+                                            *   0, a trigger event is generated to the memory controller
+                                            *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
+        } MAC_LINK_QTRIG_P1_b;
+    };
+    __IM uint32_t RESERVED33[4];
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY1_P1;  /*!< (@ 0x00000C30) Port 1 PTP Clock Identity 1 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
+            __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
+            __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
+            __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
+        } PTPCLOCKIDENTITY1_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY2_P1;  /*!< (@ 0x00000C34) Port 1 PTP Clock Identity 2 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
+            __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
+            __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
+            __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
+        } PTPCLOCKIDENTITY2_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPAUTORESPONSE_P1; /*!< (@ 0x00000C38) Port 1 PTP Auto Response Register (n = 0 to 2)             */
+
+        struct
+        {
+            __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
+            __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
+            uint32_t                : 14;
+            __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
+            __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
+        } PTPAUTORESPONSE_P1_b;
+    };
+    __IM uint32_t RESERVED34;
+
+    union
+    {
+        __IOM uint32_t STATUS_P1;          /*!< (@ 0x00000C40) Port 1 Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
+            __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
+            __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
+            __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
+                                            *   never occur during normal operation.                                      */
+            __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
+                                            *   to complete in time before the next frame was received
+                                            *   at the port. This should never occur under normal operation.
+                                            *   The cause could be from IPG violations in the received
+                                            *   frames.                                                                   */
+            __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
+                                            *   to clause 30.14.1.2 of the 802.3br specification                          */
+            uint32_t : 23;
+        } STATUS_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TX_IPG_LENGTH_P1;      /*!< (@ 0x00000C44) Port 1 Transmit IPG Length Register (n = 0 to
+                                               *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
+                                               *   are in the range of 8 to 31.                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
+            uint32_t                  : 11;
+        } TX_IPG_LENGTH_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_CTL_STAT_P1;        /*!< (@ 0x00000C48) Port 1 MAC EEE Functions Control and Status (n
+                                                *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
+            __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
+            __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
+            uint32_t                    : 5;
+            __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
+            __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
+            __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
+            __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
+                                                *   available for transmission.                                               */
+            __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
+            uint32_t                      : 3;
+            __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
+            __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
+                                                *   MAC                                                                       */
+            __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
+            uint32_t                   : 1;
+            __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
+            uint32_t                   : 11;
+        } EEE_CTL_STAT_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_IDLE_TIME_P1;       /*!< (@ 0x00000C4C) Port 1 EEE Idle Time Register (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
+                                                *   of LPI begins. A 32-bit value in steps of 32 switch operating
+                                                *   clock cycles. A value of 0 disables the timer. The value
+                                                *   must be set to 1 less count.                                              */
+        } EEE_IDLE_TIME_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_TWSYS_TIME_P1;      /*!< (@ 0x00000C50) Port 1 EEE Wake Up Time Register (n = 0 to 2)              */
+
+        struct
+        {
+            __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
+                                                *   to begin transmitting the first frame again. A 32-bit value
+                                                *   in steps of switch operating clock cycles. A value of 0
+                                                *   disables the timer. The value must be set to 1 less count.                */
+        } EEE_TWSYS_TIME_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IDLE_SLOPE_P1;       /*!< (@ 0x00000C54) Port 1 MAC Traffic Shaper Bandwidth Control                */
+
+        struct
+        {
+            __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
+            uint32_t                  : 21;
+        } IDLE_SLOPE_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CT_DELAY_P1;      /*!< (@ 0x00000C58) Port 1 Cut-Through Delay Indication Register               */
+
+        struct
+        {
+            __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
+                                          *   of the MII PHY interface)                                                 */
+            uint32_t : 23;
+        } CT_DELAY_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BR_CONTROL_P1;            /*!< (@ 0x00000C5C) Port 1 802.3br Frame Configuration Register                */
+
+        struct
+        {
+            __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
+            __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
+                                                  *   preemption operation.                                                     */
+            __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
+                                                  *   frames.                                                                   */
+            uint32_t                      : 1;
+            __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
+            uint32_t                      : 2;
+            __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
+            uint32_t                      : 1;
+            __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
+                                                  *   except the SFD are 0x55. When set to 0, only the last 2
+                                                  *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
+                                                  *   It is recommended to set this bit to 1 to comply with the
+                                                  *   802.3br specification. This bit must be set to 0 if only
+                                                  *   non-802.3br traffic is expected (for example, normal Ethernet
+                                                  *   traffic) and if custom preamble is used.                                  */
+            __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
+                                                  *   SMDs and assumes all frames are express frames. This bit
+                                                  *   must be set to 0 for correct operation with 802.3br, and
+                                                  *   can be set to 1 when 802.3br is not enabled to avoid false
+                                                  *   detection of SMDs.                                                        */
+            __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
+                                                  *   frames is enabled. When set to 1, the frame contents and
+                                                  *   frame length checks are also performed on these frames.
+                                                  *   The mCRC is always checked regardless of the value of this
+                                                  *   register. This bit must be set to 0 to be compliant with
+                                                  *   the functionality described in IEEE 802.3br.                              */
+            __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for transmitted frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for received frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            uint32_t : 11;
+        } BR_CONTROL_P1_b;
+    };
+    __IM uint32_t RESERVED35[2];
+
+    union
+    {
+        __IM uint32_t AFRAMESTRANSMITTEDOK_P1; /*!< (@ 0x00000C68) Port 1 MAC Transmitted Valid Frame Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                *   Transmitted, including pause.                                             */
+        } AFRAMESTRANSMITTEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMESRECEIVEDOK_P1;  /*!< (@ 0x00000C6C) Port 1 MAC Received Valid Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                              *   Received, including pause.                                                */
+        } AFRAMESRECEIVEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P1; /*!< (@ 0x00000C70) Port 1 MAC FCS Error Frame Count Register (n
+                                                     *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                     *   Length but CRC error.                                                     */
+        } AFRAMECHECKSEQUENCEERRORS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AALIGNMENTERRORS_P1;   /*!< (@ 0x00000C74) Port 1 MAC Alignment Error Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
+                                              *   of Nibbles (MII) Received.                                                */
+        } AALIGNMENTERRORS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSTRANSMITTEDOK_P1; /*!< (@ 0x00000C78) Port 1 MAC Transmitted Valid Frame Octets Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                                *   only) of MAC Valid Transmitted.                                           */
+        } AOCTETSTRANSMITTEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSRECEIVEDOK_P1;   /*!< (@ 0x00000C7C) Port 1 MAC Received Valid Frame Octets Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                               *   only) of MAC Valid Received.                                              */
+        } AOCTETSRECEIVEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ATXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C80) Port 1 MAC Transmitted Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Transmitted.                                                        */
+        } ATXPAUSEMACCTRLFRAMES_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ARXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C84) Port 1 MAC Received Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Received.                                                           */
+        } ARXPAUSEMACCTRLFRAMES_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINERRORS_P1;       /*!< (@ 0x00000C88) Port 1 MAC Input Error Count Register (n = 0
+                                            *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
+                                            *   During Reception such as CRC, Length, PHY Error, RX FIFO
+                                            *   Overflow.                                                                 */
+        } IFINERRORS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTERRORS_P1;       /*!< (@ 0x00000C8C) Port 1 MAC Output Error Count Register (n = 0
+                                             *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
+                                             *   Transmitted with PHY error.                                               */
+        } IFOUTERRORS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINUCASTPKTS_P1;      /*!< (@ 0x00000C90) Port 1 MAC Received Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINUCASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINMULTICASTPKTS_P1;  /*!< (@ 0x00000C94) Port 1 MAC Received Multicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINMULTICASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINBROADCASTPKTS_P1;  /*!< (@ 0x00000C98) Port 1 MAC Received Broadcast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Received.                                                     */
+        } IFINBROADCASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTDISCARDS_P1;     /*!< (@ 0x00000C9C) Port 1 MAC Discarded Outbound Frame Count Register
+                                             *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
+        } IFOUTDISCARDS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTUCASTPKTS_P1;     /*!< (@ 0x00000CA0) Port 1 MAC Transmitted Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTUCASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTMULTICASTPKTS_P1; /*!< (@ 0x00000CA4) Port 1 MAC Transmitted Multicast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTMULTICASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTBROADCASTPKTS_P1; /*!< (@ 0x00000CA8) Port 1 MAC Transmitted Broadcast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTBROADCASTPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSDROPEVENTS_P1; /*!< (@ 0x00000CAC) Port 1 MAC Dropped Frame Count Register (n =
+                                                *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
+                                                *   Full at frame start.                                                      */
+        } ETHERSTATSDROPEVENTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOCTETS_P1; /*!< (@ 0x00000CB0) Port 1 MAC All Frame Octets Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
+        } ETHERSTATSOCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS_P1; /*!< (@ 0x00000CB4) Port 1 MAC All Frame Count Register (n = 0 to
+                                          *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
+        } ETHERSTATSPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P1; /*!< (@ 0x00000CB8) Port 1 MAC Too Short Frame Count Register (n
+                                                   *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                                   *   Good CRC.                                                                 */
+        } ETHERSTATSUNDERSIZEPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOVERSIZEPKTS_P1; /*!< (@ 0x00000CBC) Port 1 MAC Too Long Frame Count Register (n =
+                                                  *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                                  *   Good CRC.                                                                 */
+        } ETHERSTATSOVERSIZEPKTS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS64OCTETS_P1; /*!< (@ 0x00000CC0) Port 1 MAC 64 Octets Frame Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                  *   Good and Bad (Packet Size: 64 bytes).                                     */
+        } ETHERSTATSPKTS64OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P1; /*!< (@ 0x00000CC4) Port 1 MAC 65 to 127 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                       *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
+        } ETHERSTATSPKTS65TO127OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P1; /*!< (@ 0x00000CC8) Port 1 MAC 128 to 255 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
+        } ETHERSTATSPKTS128TO255OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P1; /*!< (@ 0x00000CCC) Port 1 MAC 256 to 511 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
+        } ETHERSTATSPKTS256TO511OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P1; /*!< (@ 0x00000CD0) Port 1 MAC 512 to 1023 Octets Frame Count Register
+                                                         *              (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                         *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
+        } ETHERSTATSPKTS512TO1023OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P1; /*!< (@ 0x00000CD4) Port 1 MAC 1024 to 1518 Octets Frame Count Register
+                                                          *             (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                          *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
+        } ETHERSTATSPKTS1024TO1518OCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P1; /*!< (@ 0x00000CD8) Port 1 MAC Over 1519 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
+                                                       *   Good and Bad (Packet Size: over 1519 bytes).                              */
+        } ETHERSTATSPKTS1519TOXOCTETS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSJABBERS_P1; /*!< (@ 0x00000CDC) Port 1 MAC Jabbers Frame Count Register (n =
+                                             *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                             *   Bad CRC.                                                                  */
+        } ETHERSTATSJABBERS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSFRAGMENTS_P1; /*!< (@ 0x00000CE0) Port 1 MAC Fragment Frame Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                               *   Bad CRC.                                                                  */
+        } ETHERSTATSFRAGMENTS_P1_b;
+    };
+    __IM uint32_t RESERVED36;
+
+    union
+    {
+        __IM uint32_t VLANRECEIVEDOK_P1;     /*!< (@ 0x00000CE8) Port 1 MAC Received VLAN Tagged Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Received.                                                   */
+        } VLANRECEIVEDOK_P1_b;
+    };
+    __IM uint32_t RESERVED37[2];
+
+    union
+    {
+        __IM uint32_t VLANTRANSMITTEDOK_P1;  /*!< (@ 0x00000CF4) Port 1 MAC Transmitted VLAN Tagged Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Transmitted.                                                */
+        } VLANTRANSMITTEDOK_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRAMESRETRANSMITTED_P1; /*!< (@ 0x00000CF8) Port 1 MAC Retransmitted Frame Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
+                                               *   Frames that experienced a collision and were retransmitted.               */
+        } FRAMESRETRANSMITTED_P1_b;
+    };
+    __IM uint32_t RESERVED38;
+
+    union
+    {
+        __IM uint32_t STATS_HIWORD_P1;       /*!< (@ 0x00000D00) Port 1 MAC Statistics Counter High Word Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
+                                              *   Counter Last Read                                                         */
+        } STATS_HIWORD_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CTRL_P1;   /*!< (@ 0x00000D04) Port 1 MAC Statistics Control Register (n = 0
+                                         *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
+            __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
+            uint32_t               : 30;
+        } STATS_CTRL_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUELO_P1;       /*!< (@ 0x00000D08) Port 1 MAC Statistics Clear Value Lower Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUELO_P1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUEHI_P1;       /*!< (@ 0x00000D0C) Port 1 MAC Statistics Clear Value Higher Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUEHI_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADEFERRED_P1;        /*!< (@ 0x00000D10) Port 1 MAC Deferred Count Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
+                                            *   without collision but was deferred at begin.                              */
+        } ADEFERRED_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AMULTIPLECOLLISIONS_P1;   /*!< (@ 0x00000D14) Port 1 MAC Multiple Collision Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                 *   Transmit after multiple collisions.                                       */
+        } AMULTIPLECOLLISIONS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASINGLECOLLISIONS_P1;      /*!< (@ 0x00000D18) Port 1 MAC Single Collision Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                  *   Transmit after single collision.                                          */
+        } ASINGLECOLLISIONS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ALATECOLLISIONS_P1;     /*!< (@ 0x00000D1C) Port 1 MAC Late Collision Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
+                                               *   Collision. Frame was aborted and not retransmitted.                       */
+        } ALATECOLLISIONS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AEXCESSIVECOLLISIONS_P1; /*!< (@ 0x00000D20) Port 1 MAC Excessive Collision Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
+                                                *   due to 16 consecutive collisions.                                         */
+        } AEXCESSIVECOLLISIONS_P1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACARRIERSENSEERRORS_P1; /*!< (@ 0x00000D24) Port 1 MAC Carrier Sense Error Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
+                                               *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
+                                               *   asserted.                                                                 */
+        } ACARRIERSENSEERRORS_P1_b;
+    };
+    __IM uint32_t RESERVED39[182];
+
+    union
+    {
+        __IM uint32_t REV_P2;          /*!< (@ 0x00001000) Port 2 MAC Core Revision (n = 0 to 3)                      */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
+        } REV_P2_b;
+    };
+    __IM uint32_t RESERVED40;
+
+    union
+    {
+        __IOM uint32_t COMMAND_CONFIG_P2;       /*!< (@ 0x00001008) Port 2 Command Configuration Register (n = 0
+                                                 *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
+            __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
+            __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
+                                                 *   the IMC until the current frame is completed. This can
+                                                 *   cause the IPG between frames to be more than the value
+                                                 *   in TX_IPG_LENGTH.                                                         */
+            __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
+            __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
+            __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
+            uint32_t                    : 1;
+            __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
+            __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
+            __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
+            __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
+                                                 *   full-duplex only (set to 0).                                              */
+            __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
+            uint32_t                     : 1;
+            __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
+            uint32_t                     : 9;
+            __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
+            __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
+            __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
+                                                 *   register.                                                                 */
+            __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
+            __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
+            uint32_t                   : 2;
+            __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
+                                                 *   on transmit and on receive. The value is used when not
+                                                 *   overridden by the PTP auto-response function, pattern matchers
+                                                 *   or force forwarding information in a management tag.                      */
+            uint32_t : 1;
+        } COMMAND_CONFIG_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_0_P2;     /*!< (@ 0x0000100C) Port 2 MAC Address Register 0 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
+                                           *   byte is bits [7:0]. The MAC address is used on locally
+                                           *   generated frames such as pause frames, peer-delay response.               */
+        } MAC_ADDR_0_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_ADDR_1_P2;     /*!< (@ 0x00001010) Port 2 MAC Address Register 1 (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
+                                           *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
+            uint32_t : 16;
+        } MAC_ADDR_1_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRM_LENGTH_P2;       /*!< (@ 0x00001014) Port 2 Maximum Frame Length Register (n = 0 to
+                                             *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
+            uint32_t                  : 18;
+        } FRM_LENGTH_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t PAUSE_QUANT_P2;       /*!< (@ 0x00001018) Port 2 MAC Pause Quanta (n = 0 to 3)                       */
+
+        struct
+        {
+            __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
+            uint32_t                  : 16;
+        } PAUSE_QUANT_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAC_LINK_QTRIG_P2;  /*!< (@ 0x0000101C) Port 2 Trigger Event Configuration Register (n
+                                            *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
+            uint32_t                  : 12;
+            __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
+                                            *   is transmitted from the ports indicated by PORT_MASK. A
+                                            *   single frame is transmitted per indicated port in PORT_MASK
+                                            *   among the queues indicated by QUEUE_MASK.                                 */
+            uint32_t                 : 4;
+            __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
+                                            *   a frame was transmitted. When MODE is set to 0, TRIGGERED
+                                            *   is always 0. This flag clears when the register is written.               */
+            __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
+                                            *   set to 1, the Link Queue Trigger occurs only if the DLR
+                                            *   state machine is in the NORMAL or FAULT state.                            */
+            __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
+                                            *   This is to prevent sending multiple frames due to link
+                                            *   flapping.                                                                 */
+            __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
+                                            *   When the link status (phy_link) transitions from 1 ->
+                                            *   0, a trigger event is generated to the memory controller
+                                            *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
+        } MAC_LINK_QTRIG_P2_b;
+    };
+    __IM uint32_t RESERVED41[4];
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY1_P2;  /*!< (@ 0x00001030) Port 2 PTP Clock Identity 1 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
+            __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
+            __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
+            __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
+        } PTPCLOCKIDENTITY1_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPCLOCKIDENTITY2_P2;  /*!< (@ 0x00001034) Port 2 PTP Clock Identity 2 Register (n = 0 to
+                                               *                  2)                                                         */
+
+        struct
+        {
+            __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
+            __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
+            __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
+            __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
+        } PTPCLOCKIDENTITY2_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTPAUTORESPONSE_P2; /*!< (@ 0x00001038) Port 2 PTP Auto Response Register (n = 0 to 2)             */
+
+        struct
+        {
+            __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
+            __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
+            uint32_t                : 14;
+            __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
+            __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
+        } PTPAUTORESPONSE_P2_b;
+    };
+    __IM uint32_t RESERVED42;
+
+    union
+    {
+        __IOM uint32_t STATUS_P2;          /*!< (@ 0x00001040) Port 2 Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
+            __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
+            __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
+            __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
+                                            *   never occur during normal operation.                                      */
+            __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
+                                            *   to complete in time before the next frame was received
+                                            *   at the port. This should never occur under normal operation.
+                                            *   The cause could be from IPG violations in the received
+                                            *   frames.                                                                   */
+            __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
+                                            *   to clause 30.14.1.2 of the 802.3br specification                          */
+            uint32_t : 23;
+        } STATUS_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TX_IPG_LENGTH_P2;      /*!< (@ 0x00001044) Port 2 Transmit IPG Length Register (n = 0 to
+                                               *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
+                                               *   are in the range of 8 to 31.                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
+            uint32_t                  : 11;
+        } TX_IPG_LENGTH_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_CTL_STAT_P2;        /*!< (@ 0x00001048) Port 2 MAC EEE Functions Control and Status (n
+                                                *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
+            __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
+            __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
+            uint32_t                    : 5;
+            __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
+            __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
+            __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
+            __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
+                                                *   available for transmission.                                               */
+            __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
+            uint32_t                      : 3;
+            __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
+            __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
+                                                *   MAC                                                                       */
+            __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
+            uint32_t                   : 1;
+            __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
+            uint32_t                   : 11;
+        } EEE_CTL_STAT_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_IDLE_TIME_P2;       /*!< (@ 0x0000104C) Port 2 EEE Idle Time Register (n = 0 to 2)                 */
+
+        struct
+        {
+            __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
+                                                *   of LPI begins. A 32-bit value in steps of 32 switch operating
+                                                *   clock cycles. A value of 0 disables the timer. The value
+                                                *   must be set to 1 less count.                                              */
+        } EEE_IDLE_TIME_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEE_TWSYS_TIME_P2;      /*!< (@ 0x00001050) Port 2 EEE Wake Up Time Register (n = 0 to 2)              */
+
+        struct
+        {
+            __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
+                                                *   to begin transmitting the first frame again. A 32-bit value
+                                                *   in steps of switch operating clock cycles. A value of 0
+                                                *   disables the timer. The value must be set to 1 less count.                */
+        } EEE_TWSYS_TIME_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IDLE_SLOPE_P2;       /*!< (@ 0x00001054) Port 2 MAC Traffic Shaper Bandwidth Control                */
+
+        struct
+        {
+            __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
+            uint32_t                  : 21;
+        } IDLE_SLOPE_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CT_DELAY_P2;      /*!< (@ 0x00001058) Port 2 Cut-Through Delay Indication Register               */
+
+        struct
+        {
+            __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
+                                          *   of the MII PHY interface)                                                 */
+            uint32_t : 23;
+        } CT_DELAY_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BR_CONTROL_P2;            /*!< (@ 0x0000105C) Port 2 802.3br Frame Configuration Register                */
+
+        struct
+        {
+            __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
+            __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
+                                                  *   preemption operation.                                                     */
+            __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
+                                                  *   frames.                                                                   */
+            uint32_t                      : 1;
+            __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
+            uint32_t                      : 2;
+            __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
+            uint32_t                      : 1;
+            __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
+                                                  *   except the SFD are 0x55. When set to 0, only the last 2
+                                                  *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
+                                                  *   It is recommended to set this bit to 1 to comply with the
+                                                  *   802.3br specification. This bit must be set to 0 if only
+                                                  *   non-802.3br traffic is expected (for example, normal Ethernet
+                                                  *   traffic) and if custom preamble is used.                                  */
+            __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
+                                                  *   SMDs and assumes all frames are express frames. This bit
+                                                  *   must be set to 0 for correct operation with 802.3br, and
+                                                  *   can be set to 1 when 802.3br is not enabled to avoid false
+                                                  *   detection of SMDs.                                                        */
+            __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
+                                                  *   frames is enabled. When set to 1, the frame contents and
+                                                  *   frame length checks are also performed on these frames.
+                                                  *   The mCRC is always checked regardless of the value of this
+                                                  *   register. This bit must be set to 0 to be compliant with
+                                                  *   the functionality described in IEEE 802.3br.                              */
+            __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for transmitted frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
+                                                  *   the mCRC for received frames is inverted. This bit must
+                                                  *   always be written to 0 and only used for debugging.                       */
+            uint32_t : 11;
+        } BR_CONTROL_P2_b;
+    };
+    __IM uint32_t RESERVED43[2];
+
+    union
+    {
+        __IM uint32_t AFRAMESTRANSMITTEDOK_P2; /*!< (@ 0x00001068) Port 2 MAC Transmitted Valid Frame Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                *   Transmitted, including pause.                                             */
+        } AFRAMESTRANSMITTEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMESRECEIVEDOK_P2;  /*!< (@ 0x0000106C) Port 2 MAC Received Valid Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                              *   Received, including pause.                                                */
+        } AFRAMESRECEIVEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P2; /*!< (@ 0x00001070) Port 2 MAC FCS Error Frame Count Register (n
+                                                     *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                     *   Length but CRC error.                                                     */
+        } AFRAMECHECKSEQUENCEERRORS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AALIGNMENTERRORS_P2;   /*!< (@ 0x00001074) Port 2 MAC Alignment Error Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
+                                              *   of Nibbles (MII) Received.                                                */
+        } AALIGNMENTERRORS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSTRANSMITTEDOK_P2; /*!< (@ 0x00001078) Port 2 MAC Transmitted Valid Frame Octets Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                                *   only) of MAC Valid Transmitted.                                           */
+        } AOCTETSTRANSMITTEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSRECEIVEDOK_P2;   /*!< (@ 0x0000107C) Port 2 MAC Received Valid Frame Octets Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                               *   only) of MAC Valid Received.                                              */
+        } AOCTETSRECEIVEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ATXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001080) Port 2 MAC Transmitted Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Transmitted.                                                        */
+        } ATXPAUSEMACCTRLFRAMES_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ARXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001084) Port 2 MAC Received Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Received.                                                           */
+        } ARXPAUSEMACCTRLFRAMES_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINERRORS_P2;       /*!< (@ 0x00001088) Port 2 MAC Input Error Count Register (n = 0
+                                            *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
+                                            *   During Reception such as CRC, Length, PHY Error, RX FIFO
+                                            *   Overflow.                                                                 */
+        } IFINERRORS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTERRORS_P2;       /*!< (@ 0x0000108C) Port 2 MAC Output Error Count Register (n = 0
+                                             *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
+                                             *   Transmitted with PHY error.                                               */
+        } IFOUTERRORS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINUCASTPKTS_P2;      /*!< (@ 0x00001090) Port 2 MAC Received Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINUCASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINMULTICASTPKTS_P2;  /*!< (@ 0x00001094) Port 2 MAC Received Multicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINMULTICASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINBROADCASTPKTS_P2;  /*!< (@ 0x00001098) Port 2 MAC Received Broadcast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Received.                                                     */
+        } IFINBROADCASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTDISCARDS_P2;     /*!< (@ 0x0000109C) Port 2 MAC Discarded Outbound Frame Count Register
+                                             *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
+        } IFOUTDISCARDS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTUCASTPKTS_P2;     /*!< (@ 0x000010A0) Port 2 MAC Transmitted Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTUCASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTMULTICASTPKTS_P2; /*!< (@ 0x000010A4) Port 2 MAC Transmitted Multicast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTMULTICASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTBROADCASTPKTS_P2; /*!< (@ 0x000010A8) Port 2 MAC Transmitted Broadcast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTBROADCASTPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSDROPEVENTS_P2; /*!< (@ 0x000010AC) Port 2 MAC Dropped Frame Count Register (n =
+                                                *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
+                                                *   Full at frame start.                                                      */
+        } ETHERSTATSDROPEVENTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOCTETS_P2; /*!< (@ 0x000010B0) Port 2 MAC All Frame Octets Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
+        } ETHERSTATSOCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS_P2; /*!< (@ 0x000010B4) Port 2 MAC All Frame Count Register (n = 0 to
+                                          *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
+        } ETHERSTATSPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P2; /*!< (@ 0x000010B8) Port 2 MAC Too Short Frame Count Register (n
+                                                   *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                                   *   Good CRC.                                                                 */
+        } ETHERSTATSUNDERSIZEPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOVERSIZEPKTS_P2; /*!< (@ 0x000010BC) Port 2 MAC Too Long Frame Count Register (n =
+                                                  *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                                  *   Good CRC.                                                                 */
+        } ETHERSTATSOVERSIZEPKTS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS64OCTETS_P2; /*!< (@ 0x000010C0) Port 2 MAC 64 Octets Frame Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                  *   Good and Bad (Packet Size: 64 bytes).                                     */
+        } ETHERSTATSPKTS64OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P2; /*!< (@ 0x000010C4) Port 2 MAC 65 to 127 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                       *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
+        } ETHERSTATSPKTS65TO127OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P2; /*!< (@ 0x000010C8) Port 2 MAC 128 to 255 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
+        } ETHERSTATSPKTS128TO255OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P2; /*!< (@ 0x000010CC) Port 2 MAC 256 to 511 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
+        } ETHERSTATSPKTS256TO511OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P2; /*!< (@ 0x000010D0) Port 2 MAC 512 to 1023 Octets Frame Count Register
+                                                         *              (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                         *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
+        } ETHERSTATSPKTS512TO1023OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P2; /*!< (@ 0x000010D4) Port 2 MAC 1024 to 1518 Octets Frame Count Register
+                                                          *             (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                          *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
+        } ETHERSTATSPKTS1024TO1518OCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P2; /*!< (@ 0x000010D8) Port 2 MAC Over 1519 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
+                                                       *   Good and Bad (Packet Size: over 1519 bytes).                              */
+        } ETHERSTATSPKTS1519TOXOCTETS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSJABBERS_P2; /*!< (@ 0x000010DC) Port 2 MAC Jabbers Frame Count Register (n =
+                                             *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                             *   Bad CRC.                                                                  */
+        } ETHERSTATSJABBERS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSFRAGMENTS_P2; /*!< (@ 0x000010E0) Port 2 MAC Fragment Frame Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                               *   Bad CRC.                                                                  */
+        } ETHERSTATSFRAGMENTS_P2_b;
+    };
+    __IM uint32_t RESERVED44;
+
+    union
+    {
+        __IM uint32_t VLANRECEIVEDOK_P2;     /*!< (@ 0x000010E8) Port 2 MAC Received VLAN Tagged Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Received.                                                   */
+        } VLANRECEIVEDOK_P2_b;
+    };
+    __IM uint32_t RESERVED45[2];
+
+    union
+    {
+        __IM uint32_t VLANTRANSMITTEDOK_P2;  /*!< (@ 0x000010F4) Port 2 MAC Transmitted VLAN Tagged Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Transmitted.                                                */
+        } VLANTRANSMITTEDOK_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRAMESRETRANSMITTED_P2; /*!< (@ 0x000010F8) Port 2 MAC Retransmitted Frame Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
+                                               *   Frames that experienced a collision and were retransmitted.               */
+        } FRAMESRETRANSMITTED_P2_b;
+    };
+    __IM uint32_t RESERVED46;
+
+    union
+    {
+        __IM uint32_t STATS_HIWORD_P2;       /*!< (@ 0x00001100) Port 2 MAC Statistics Counter High Word Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
+                                              *   Counter Last Read                                                         */
+        } STATS_HIWORD_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CTRL_P2;   /*!< (@ 0x00001104) Port 2 MAC Statistics Control Register (n = 0
+                                         *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
+            __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
+            uint32_t               : 30;
+        } STATS_CTRL_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUELO_P2;       /*!< (@ 0x00001108) Port 2 MAC Statistics Clear Value Lower Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUELO_P2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUEHI_P2;       /*!< (@ 0x0000110C) Port 2 MAC Statistics Clear Value Higher Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUEHI_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADEFERRED_P2;        /*!< (@ 0x00001110) Port 2 MAC Deferred Count Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
+                                            *   without collision but was deferred at begin.                              */
+        } ADEFERRED_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AMULTIPLECOLLISIONS_P2;   /*!< (@ 0x00001114) Port 2 MAC Multiple Collision Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                 *   Transmit after multiple collisions.                                       */
+        } AMULTIPLECOLLISIONS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASINGLECOLLISIONS_P2;      /*!< (@ 0x00001118) Port 2 MAC Single Collision Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                  *   Transmit after single collision.                                          */
+        } ASINGLECOLLISIONS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ALATECOLLISIONS_P2;     /*!< (@ 0x0000111C) Port 2 MAC Late Collision Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
+                                               *   Collision. Frame was aborted and not retransmitted.                       */
+        } ALATECOLLISIONS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AEXCESSIVECOLLISIONS_P2; /*!< (@ 0x00001120) Port 2 MAC Excessive Collision Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
+                                                *   due to 16 consecutive collisions.                                         */
+        } AEXCESSIVECOLLISIONS_P2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACARRIERSENSEERRORS_P2; /*!< (@ 0x00001124) Port 2 MAC Carrier Sense Error Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
+                                               *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
+                                               *   asserted.                                                                 */
+        } ACARRIERSENSEERRORS_P2_b;
+    };
+    __IM uint32_t RESERVED47[182];
+
+    union
+    {
+        __IM uint32_t REV_P3;          /*!< (@ 0x00001400) Port 3 MAC Core Revision (n = 0 to 3)                      */
+
+        struct
+        {
+            __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
+        } REV_P3_b;
+    };
+    __IM uint32_t RESERVED48;
+
+    union
+    {
+        __IOM uint32_t COMMAND_CONFIG_P3;       /*!< (@ 0x00001408) Port 3 Command Configuration Register (n = 0
+                                                 *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
+            __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
+            __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
+                                                 *   the IMC until the current frame is completed. This can
+                                                 *   cause the IPG between frames to be more than the value
+                                                 *   in TX_IPG_LENGTH.                                                         */
+            __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
+            __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
+            __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
+            uint32_t                    : 1;
+            __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
+            __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
+            __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
+            __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
+                                                 *   full-duplex only (set to 0).                                              */
+            __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
+            uint32_t                     : 1;
+            __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
+            uint32_t                     : 9;
+            __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
+            __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
+            __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
+                                                 *   register.                                                                 */
+            __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
+            __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
+            uint32_t                   : 2;
+            __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
+                                                 *   on transmit and on receive. The value is used when not
+                                                 *   overridden by the PTP auto-response function, pattern matchers
+                                                 *   or force forwarding information in a management tag.                      */
+            uint32_t : 1;
+        } COMMAND_CONFIG_P3_b;
+    };
+    __IM uint32_t RESERVED49[2];
+
+    union
+    {
+        __IOM uint32_t FRM_LENGTH_P3;       /*!< (@ 0x00001414) Port 3 Maximum Frame Length Register (n = 0 to
+                                             *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
+            uint32_t                  : 18;
+        } FRM_LENGTH_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t PAUSE_QUANT_P3;       /*!< (@ 0x00001418) Port 3 MAC Pause Quanta (n = 0 to 3)                       */
+
+        struct
+        {
+            __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
+            uint32_t                  : 16;
+        } PAUSE_QUANT_P3_b;
+    };
+    __IM uint32_t RESERVED50[9];
+
+    union
+    {
+        __IOM uint32_t STATUS_P3;          /*!< (@ 0x00001440) Port 3 Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
+            __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
+            __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
+            __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
+                                            *   never occur during normal operation.                                      */
+            __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
+                                            *   to complete in time before the next frame was received
+                                            *   at the port. This should never occur under normal operation.
+                                            *   The cause could be from IPG violations in the received
+                                            *   frames.                                                                   */
+            __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
+                                            *   to clause 30.14.1.2 of the 802.3br specification                          */
+            uint32_t : 23;
+        } STATUS_P3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TX_IPG_LENGTH_P3;      /*!< (@ 0x00001444) Port 3 Transmit IPG Length Register (n = 0 to
+                                               *                  3)                                                         */
+
+        struct
+        {
+            __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
+                                               *   are in the range of 8 to 31.                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
+            uint32_t                  : 11;
+        } TX_IPG_LENGTH_P3_b;
+    };
+    __IM uint32_t RESERVED51[3];
+
+    union
+    {
+        __IOM uint32_t IDLE_SLOPE_P3;       /*!< (@ 0x00001454) Port 3 MAC Traffic Shaper Bandwidth Control                */
+
+        struct
+        {
+            __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
+            uint32_t                  : 21;
+        } IDLE_SLOPE_P3_b;
+    };
+    __IM uint32_t RESERVED52[4];
+
+    union
+    {
+        __IM uint32_t AFRAMESTRANSMITTEDOK_P3; /*!< (@ 0x00001468) Port 3 MAC Transmitted Valid Frame Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                *   Transmitted, including pause.                                             */
+        } AFRAMESTRANSMITTEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMESRECEIVEDOK_P3;  /*!< (@ 0x0000146C) Port 3 MAC Received Valid Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                              *   Received, including pause.                                                */
+        } AFRAMESRECEIVEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P3; /*!< (@ 0x00001470) Port 3 MAC FCS Error Frame Count Register (n
+                                                     *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                     *   Length but CRC error.                                                     */
+        } AFRAMECHECKSEQUENCEERRORS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AALIGNMENTERRORS_P3;   /*!< (@ 0x00001474) Port 3 MAC Alignment Error Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
+                                              *   of Nibbles (MII) Received.                                                */
+        } AALIGNMENTERRORS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSTRANSMITTEDOK_P3; /*!< (@ 0x00001478) Port 3 MAC Transmitted Valid Frame Octets Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                                *   only) of MAC Valid Transmitted.                                           */
+        } AOCTETSTRANSMITTEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AOCTETSRECEIVEDOK_P3;   /*!< (@ 0x0000147C) Port 3 MAC Received Valid Frame Octets Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
+                                               *   only) of MAC Valid Received.                                              */
+        } AOCTETSRECEIVEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ATXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001480) Port 3 MAC Transmitted Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Transmitted.                                                        */
+        } ATXPAUSEMACCTRLFRAMES_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ARXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001484) Port 3 MAC Received Pause Frame Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
+                                                 *   Pause Received.                                                           */
+        } ARXPAUSEMACCTRLFRAMES_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINERRORS_P3;       /*!< (@ 0x00001488) Port 3 MAC Input Error Count Register (n = 0
+                                            *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
+                                            *   During Reception such as CRC, Length, PHY Error, RX FIFO
+                                            *   Overflow.                                                                 */
+        } IFINERRORS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTERRORS_P3;       /*!< (@ 0x0000148C) Port 3 MAC Output Error Count Register (n = 0
+                                             *                  to 3)                                                      */
+
+        struct
+        {
+            __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
+                                             *   Transmitted with PHY error.                                               */
+        } IFOUTERRORS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINUCASTPKTS_P3;      /*!< (@ 0x00001490) Port 3 MAC Received Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINUCASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINMULTICASTPKTS_P3;  /*!< (@ 0x00001494) Port 3 MAC Received Multicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Received.                                                     */
+        } IFINMULTICASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFINBROADCASTPKTS_P3;  /*!< (@ 0x00001498) Port 3 MAC Received Broadcast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Received.                                                     */
+        } IFINBROADCASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTDISCARDS_P3;     /*!< (@ 0x0000149C) Port 3 MAC Discarded Outbound Frame Count Register
+                                             *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
+        } IFOUTDISCARDS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTUCASTPKTS_P3;     /*!< (@ 0x000014A0) Port 3 MAC Transmitted Unicast Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTUCASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTMULTICASTPKTS_P3; /*!< (@ 0x000014A4) Port 3 MAC Transmitted Multicast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTMULTICASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IFOUTBROADCASTPKTS_P3; /*!< (@ 0x000014A8) Port 3 MAC Transmitted Broadcast Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
+                                              *   Frame Valid Transmitted.                                                  */
+        } IFOUTBROADCASTPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSDROPEVENTS_P3; /*!< (@ 0x000014AC) Port 3 MAC Dropped Frame Count Register (n =
+                                                *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
+                                                *   Full at frame start.                                                      */
+        } ETHERSTATSDROPEVENTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOCTETS_P3; /*!< (@ 0x000014B0) Port 3 MAC All Frame Octets Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
+        } ETHERSTATSOCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS_P3; /*!< (@ 0x000014B4) Port 3 MAC All Frame Count Register (n = 0 to
+                                          *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
+        } ETHERSTATSPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P3; /*!< (@ 0x000014B8) Port 3 MAC Too Short Frame Count Register (n
+                                                   *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                                   *   Good CRC.                                                                 */
+        } ETHERSTATSUNDERSIZEPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSOVERSIZEPKTS_P3; /*!< (@ 0x000014BC) Port 3 MAC Too Long Frame Count Register (n =
+                                                  *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                                  *   Good CRC.                                                                 */
+        } ETHERSTATSOVERSIZEPKTS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS64OCTETS_P3; /*!< (@ 0x000014C0) Port 3 MAC 64 Octets Frame Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                  *   Good and Bad (Packet Size: 64 bytes).                                     */
+        } ETHERSTATSPKTS64OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P3; /*!< (@ 0x000014C4) Port 3 MAC 65 to 127 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                       *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
+        } ETHERSTATSPKTS65TO127OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P3; /*!< (@ 0x000014C8) Port 3 MAC 128 to 255 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
+        } ETHERSTATSPKTS128TO255OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P3; /*!< (@ 0x000014CC) Port 3 MAC 256 to 511 Octets Frame Count Register
+                                                        *               (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                        *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
+        } ETHERSTATSPKTS256TO511OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P3; /*!< (@ 0x000014D0) Port 3 MAC 512 to 1023 Octets Frame Count Register
+                                                         *              (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                         *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
+        } ETHERSTATSPKTS512TO1023OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P3; /*!< (@ 0x000014D4) Port 3 MAC 1024 to 1518 Octets Frame Count Register
+                                                          *             (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
+                                                          *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
+        } ETHERSTATSPKTS1024TO1518OCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P3; /*!< (@ 0x000014D8) Port 3 MAC Over 1519 Octets Frame Count Register
+                                                       *                (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
+                                                       *   Good and Bad (Packet Size: over 1519 bytes).                              */
+        } ETHERSTATSPKTS1519TOXOCTETS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSJABBERS_P3; /*!< (@ 0x000014DC) Port 3 MAC Jabbers Frame Count Register (n =
+                                             *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
+                                             *   Bad CRC.                                                                  */
+        } ETHERSTATSJABBERS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ETHERSTATSFRAGMENTS_P3; /*!< (@ 0x000014E0) Port 3 MAC Fragment Frame Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
+                                               *   Bad CRC.                                                                  */
+        } ETHERSTATSFRAGMENTS_P3_b;
+    };
+    __IM uint32_t RESERVED53;
+
+    union
+    {
+        __IM uint32_t VLANRECEIVEDOK_P3;     /*!< (@ 0x000014E8) Port 3 MAC Received VLAN Tagged Frame Count Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Received.                                                   */
+        } VLANRECEIVEDOK_P3_b;
+    };
+    __IM uint32_t RESERVED54[2];
+
+    union
+    {
+        __IM uint32_t VLANTRANSMITTEDOK_P3;  /*!< (@ 0x000014F4) Port 3 MAC Transmitted VLAN Tagged Frame Count
+                                              *                  Register (n = 0 to 3)                                      */
+
+        struct
+        {
+            __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
+                                              *   with VLAN Tag Transmitted.                                                */
+        } VLANTRANSMITTEDOK_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRAMESRETRANSMITTED_P3; /*!< (@ 0x000014F8) Port 3 MAC Retransmitted Frame Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
+                                               *   Frames that experienced a collision and were retransmitted.               */
+        } FRAMESRETRANSMITTED_P3_b;
+    };
+    __IM uint32_t RESERVED55;
+
+    union
+    {
+        __IM uint32_t STATS_HIWORD_P3;       /*!< (@ 0x00001500) Port 3 MAC Statistics Counter High Word Register
+                                              *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
+                                              *   Counter Last Read                                                         */
+        } STATS_HIWORD_P3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CTRL_P3;   /*!< (@ 0x00001504) Port 3 MAC Statistics Control Register (n = 0
+                                         *                  to 3)                                                      */
+
+        struct
+        {
+            __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
+            __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
+            uint32_t               : 30;
+        } STATS_CTRL_P3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUELO_P3;       /*!< (@ 0x00001508) Port 3 MAC Statistics Clear Value Lower Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUELO_P3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATS_CLEAR_VALUEHI_P3;       /*!< (@ 0x0000150C) Port 3 MAC Statistics Clear Value Higher Register
+                                                      *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
+                                                      *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
+                                                      *   command for test purposes. These bits should be set to
+                                                      *   0 normally.                                                               */
+        } STATS_CLEAR_VALUEHI_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADEFERRED_P3;        /*!< (@ 0x00001510) Port 3 MAC Deferred Count Register (n = 0 to
+                                            *                  3)                                                         */
+
+        struct
+        {
+            __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
+                                            *   without collision but was deferred at begin.                              */
+        } ADEFERRED_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AMULTIPLECOLLISIONS_P3;   /*!< (@ 0x00001514) Port 3 MAC Multiple Collision Count Register
+                                                 *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                 *   Transmit after multiple collisions.                                       */
+        } AMULTIPLECOLLISIONS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASINGLECOLLISIONS_P3;      /*!< (@ 0x00001518) Port 3 MAC Single Collision Count Register (n
+                                                  *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
+                                                  *   Transmit after single collision.                                          */
+        } ASINGLECOLLISIONS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ALATECOLLISIONS_P3;     /*!< (@ 0x0000151C) Port 3 MAC Late Collision Count Register (n =
+                                               *                  0 to 3)                                                    */
+
+        struct
+        {
+            __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
+                                               *   Collision. Frame was aborted and not retransmitted.                       */
+        } ALATECOLLISIONS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AEXCESSIVECOLLISIONS_P3; /*!< (@ 0x00001520) Port 3 MAC Excessive Collision Count Register
+                                                *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
+                                                *   due to 16 consecutive collisions.                                         */
+        } AEXCESSIVECOLLISIONS_P3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ACARRIERSENSEERRORS_P3; /*!< (@ 0x00001524) Port 3 MAC Carrier Sense Error Count Register
+                                               *                  (n = 0 to 3)                                               */
+
+        struct
+        {
+            __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
+                                               *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
+                                               *   asserted.                                                                 */
+        } ACARRIERSENSEERRORS_P3_b;
+    };
+    __IM uint32_t RESERVED56[694];
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU0;    /*!< (@ 0x00002000) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD0;    /*!< (@ 0x00002004) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU0;    /*!< (@ 0x00002008) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD0;    /*!< (@ 0x0000200C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL0;      /*!< (@ 0x00002010) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM0;      /*!< (@ 0x00002014) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL0;     /*!< (@ 0x00002018) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC0;       /*!< (@ 0x0000201C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC0;      /*!< (@ 0x00002020) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC0;      /*!< (@ 0x00002024) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU1;    /*!< (@ 0x00002028) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD1;    /*!< (@ 0x0000202C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU1;    /*!< (@ 0x00002030) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD1;    /*!< (@ 0x00002034) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL1;      /*!< (@ 0x00002038) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM1;      /*!< (@ 0x0000203C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL1;     /*!< (@ 0x00002040) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC1;       /*!< (@ 0x00002044) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC1;      /*!< (@ 0x00002048) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC1;      /*!< (@ 0x0000204C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU2;    /*!< (@ 0x00002050) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD2;    /*!< (@ 0x00002054) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU2;    /*!< (@ 0x00002058) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD2;    /*!< (@ 0x0000205C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL2;      /*!< (@ 0x00002060) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM2;      /*!< (@ 0x00002064) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL2;     /*!< (@ 0x00002068) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC2;       /*!< (@ 0x0000206C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC2;      /*!< (@ 0x00002070) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC2;      /*!< (@ 0x00002074) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU3;    /*!< (@ 0x00002078) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD3;    /*!< (@ 0x0000207C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU3;    /*!< (@ 0x00002080) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD3;    /*!< (@ 0x00002084) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL3;      /*!< (@ 0x00002088) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM3;      /*!< (@ 0x0000208C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL3;     /*!< (@ 0x00002090) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC3;       /*!< (@ 0x00002094) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC3;      /*!< (@ 0x00002098) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC3;      /*!< (@ 0x0000209C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU4;    /*!< (@ 0x000020A0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD4;    /*!< (@ 0x000020A4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU4;    /*!< (@ 0x000020A8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD4;    /*!< (@ 0x000020AC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL4;      /*!< (@ 0x000020B0) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM4;      /*!< (@ 0x000020B4) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL4;     /*!< (@ 0x000020B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC4;       /*!< (@ 0x000020BC) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC4;      /*!< (@ 0x000020C0) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC4;      /*!< (@ 0x000020C4) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU5;    /*!< (@ 0x000020C8) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD5;    /*!< (@ 0x000020CC) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU5;    /*!< (@ 0x000020D0) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD5;    /*!< (@ 0x000020D4) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL5;      /*!< (@ 0x000020D8) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM5;      /*!< (@ 0x000020DC) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL5;     /*!< (@ 0x000020E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC5;       /*!< (@ 0x000020E4) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC5;      /*!< (@ 0x000020E8) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC5;      /*!< (@ 0x000020EC) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU6;    /*!< (@ 0x000020F0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD6;    /*!< (@ 0x000020F4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU6;    /*!< (@ 0x000020F8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD6;    /*!< (@ 0x000020FC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL6;      /*!< (@ 0x00002100) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM6;      /*!< (@ 0x00002104) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL6;     /*!< (@ 0x00002108) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC6;       /*!< (@ 0x0000210C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC6;      /*!< (@ 0x00002110) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC6;      /*!< (@ 0x00002114) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACU7;    /*!< (@ 0x00002118) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P0_QSTMACU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMACD7;    /*!< (@ 0x0000211C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P0_QSTMACD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMU7;    /*!< (@ 0x00002120) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P0_QSTMAMU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSTMAMD7;    /*!< (@ 0x00002124) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P0_QSTMAMD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVL7;      /*!< (@ 0x00002128) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P0_QSFTVL7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTVLM7;      /*!< (@ 0x0000212C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P0_QSFTVLM7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSFTBL7;     /*!< (@ 0x00002130) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P0_QSFTBL7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QSMFC7;       /*!< (@ 0x00002134) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P0_QSMFC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSPPC7;      /*!< (@ 0x00002138) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P0_QMSPPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMSRPC7;      /*!< (@ 0x0000213C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P0_QMSRPC7_b;
+    };
+    __IM uint32_t RESERVED57[42];
+
+    union
+    {
+        __IOM uint32_t P0_QSEIS;       /*!< (@ 0x000021E8) Qci Stream Filter Error Interrupt Status (SDU
+                                        *                  Oversize)                                                  */
+
+        struct
+        {
+            __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
+            uint32_t              : 24;
+        } P0_QSEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QSEIE;       /*!< (@ 0x000021EC) Qci Stream Filter Error Interrupt Enable                   */
+
+        struct
+        {
+            __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
+            uint32_t              : 24;
+        } P0_QSEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P0_QSEID;        /*!< (@ 0x000021F0) Qci Stream Filter Error Interrupt Disable                  */
+
+        struct
+        {
+            __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
+            uint32_t             : 24;
+        } P0_QSEID_b;
+    };
+    __IM uint32_t RESERVED58[3];
+
+    union
+    {
+        __IOM uint32_t P0_QGMOD;       /*!< (@ 0x00002200) Qci Gate Mode Register                                     */
+
+        struct
+        {
+            __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
+            uint32_t             : 24;
+        } P0_QGMOD_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QGPPC;        /*!< (@ 0x00002204) Qci Gate (All) Passed Packet Count Port 0                  */
+
+        struct
+        {
+            __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
+            uint32_t            : 16;
+        } P0_QGPPC_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QGDPC0;       /*!< (@ 0x00002208) Qci Gate 0 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC0_b;
+    };
+    __IM uint32_t RESERVED59;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC1;       /*!< (@ 0x00002210) Qci Gate 1 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC1_b;
+    };
+    __IM uint32_t RESERVED60;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC2;       /*!< (@ 0x00002218) Qci Gate 2 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC2_b;
+    };
+    __IM uint32_t RESERVED61;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC3;       /*!< (@ 0x00002220) Qci Gate 3 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC3_b;
+    };
+    __IM uint32_t RESERVED62;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC4;       /*!< (@ 0x00002228) Qci Gate 4 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC4_b;
+    };
+    __IM uint32_t RESERVED63;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC5;       /*!< (@ 0x00002230) Qci Gate 5 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC5_b;
+    };
+    __IM uint32_t RESERVED64;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC6;       /*!< (@ 0x00002238) Qci Gate 6 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC6_b;
+    };
+    __IM uint32_t RESERVED65;
+
+    union
+    {
+        __IM uint32_t P0_QGDPC7;       /*!< (@ 0x00002240) Qci Gate 7 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P0_QGDPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QGEIS;       /*!< (@ 0x00002244) Qci Gate Error Interrupt Status                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
+            uint32_t              : 24;
+        } P0_QGEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QGEIE;       /*!< (@ 0x00002248) Qci Gate Error Interrupt Enable                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
+            uint32_t              : 24;
+        } P0_QGEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P0_QGEID;        /*!< (@ 0x0000224C) Qci Gate Error Interrupt Disable                           */
+
+        struct
+        {
+            __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
+            uint32_t             : 24;
+        } P0_QGEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC0;     /*!< (@ 0x00002250) Qci Port n Flow Meter 0 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC0;     /*!< (@ 0x00002254) Qci Meter CBS Configuration Port n, Meter 0                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC0;     /*!< (@ 0x00002258) Qci Meter CIR Configuration n 0                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC0;       /*!< (@ 0x0000225C) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC0;       /*!< (@ 0x00002260) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC1;     /*!< (@ 0x00002264) Qci Port n Flow Meter 1 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC1;     /*!< (@ 0x00002268) Qci Meter CBS Configuration Port n, Meter 1                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC1;     /*!< (@ 0x0000226C) Qci Meter CIR Configuration n 1                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC1;       /*!< (@ 0x00002270) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC1;       /*!< (@ 0x00002274) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC2;     /*!< (@ 0x00002278) Qci Port n Flow Meter 2 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC2;     /*!< (@ 0x0000227C) Qci Meter CBS Configuration Port n, Meter 2                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC2;     /*!< (@ 0x00002280) Qci Meter CIR Configuration n 2                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC2;       /*!< (@ 0x00002284) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC2;       /*!< (@ 0x00002288) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC3;     /*!< (@ 0x0000228C) Qci Port n Flow Meter 3 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC3;     /*!< (@ 0x00002290) Qci Meter CBS Configuration Port n, Meter 3                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC3;     /*!< (@ 0x00002294) Qci Meter CIR Configuration n 3                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC3;       /*!< (@ 0x00002298) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC3;       /*!< (@ 0x0000229C) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC4;     /*!< (@ 0x000022A0) Qci Port n Flow Meter 4 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC4;     /*!< (@ 0x000022A4) Qci Meter CBS Configuration Port n, Meter 4                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC4;     /*!< (@ 0x000022A8) Qci Meter CIR Configuration n 4                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC4;       /*!< (@ 0x000022AC) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC4;       /*!< (@ 0x000022B0) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC5;     /*!< (@ 0x000022B4) Qci Port n Flow Meter 5 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC5;     /*!< (@ 0x000022B8) Qci Meter CBS Configuration Port n, Meter 5                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC5;     /*!< (@ 0x000022BC) Qci Meter CIR Configuration n 5                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC5;       /*!< (@ 0x000022C0) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC5;       /*!< (@ 0x000022C4) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC6;     /*!< (@ 0x000022C8) Qci Port n Flow Meter 6 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC6;     /*!< (@ 0x000022CC) Qci Meter CBS Configuration Port n, Meter 6                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC6;     /*!< (@ 0x000022D0) Qci Meter CIR Configuration n 6                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC6;       /*!< (@ 0x000022D4) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC6;       /*!< (@ 0x000022D8) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMDESC7;     /*!< (@ 0x000022DC) Qci Port n Flow Meter 7 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P0_QMDESC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCBSC7;     /*!< (@ 0x000022E0) Qci Meter CBS Configuration Port n, Meter 7                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P0_QMCBSC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMCIRC7;     /*!< (@ 0x000022E4) Qci Meter CIR Configuration n 7                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P0_QMCIRC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMGPC7;       /*!< (@ 0x000022E8) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P0_QMGPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_QMRPC7;       /*!< (@ 0x000022EC) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P0_QMRPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMEC;        /*!< (@ 0x000022F0) Qci Meter Enable Configuration                             */
+
+        struct
+        {
+            __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
+            uint32_t          : 24;
+        } P0_QMEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMEIS;       /*!< (@ 0x000022F4) Qci Meter Error Interrupt Status                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
+            uint32_t             : 24;
+        } P0_QMEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_QMEIE;       /*!< (@ 0x000022F8) Qci Meter Error Interrupt Enable                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
+            uint32_t             : 24;
+        } P0_QMEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P0_QMEID;        /*!< (@ 0x000022FC) Qci Meter Error Interrupt Disable                          */
+
+        struct
+        {
+            __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
+            uint32_t            : 24;
+        } P0_QMEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_PCP_REMAP;       /*!< (@ 0x00002300) Port 0 VLAN Priority Code Point (PCP) Remap                */
+
+        struct
+        {
+            __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
+            __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
+            __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
+            __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
+            __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
+            __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
+            __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
+            __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
+            uint32_t                  : 8;
+        } P0_PCP_REMAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_VLAN_TAG;    /*!< (@ 0x00002304) Port 0 VLAN TAG Information for Priority Regeneration      */
+
+        struct
+        {
+            __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
+            __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
+        } P0_VLAN_TAG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_VLAN_MODE;   /*!< (@ 0x00002308) Port 0 VLAN Mode                                           */
+
+        struct
+        {
+            __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
+            __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
+            uint32_t            : 28;
+        } P0_VLAN_MODE_b;
+    };
+
+    union
+    {
+        __IM uint32_t P0_VIC_DROP_CNT;       /*!< (@ 0x0000230C) Port 0 VLAN Ingress Check Drop Frame Counter               */
+
+        struct
+        {
+            __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
+            uint32_t                   : 16;
+        } P0_VIC_DROP_CNT_b;
+    };
+    __IM uint32_t RESERVED66[6];
+
+    union
+    {
+        __IM uint32_t P0_LOOKUP_HIT_CNT;       /*!< (@ 0x00002328) Port 0 DST Address Lookup Hit Counter                      */
+
+        struct
+        {
+            __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
+            uint32_t                     : 8;
+        } P0_LOOKUP_HIT_CNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_ERROR_STATUS; /*!< (@ 0x0000232C) Port 0 Frame Parser Runtime Error Status                   */
+
+        struct
+        {
+            __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
+            __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
+                                         *   parser                                                                    */
+            __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
+            __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
+            __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
+            uint32_t              : 27;
+        } P0_ERROR_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0_ERROR_MASK;   /*!< (@ 0x00002330) Port 0 Frame Parser Runtime Error Mask                     */
+
+        struct
+        {
+            __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
+            __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
+            __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
+            __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
+            __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
+            uint32_t               : 27;
+        } P0_ERROR_MASK_b;
+    };
+    __IM uint32_t RESERVED67[35];
+
+    union
+    {
+        __IM uint32_t CHANNEL_STATE;   /*!< (@ 0x000023C0) Enable/Disable State of Ingress Channels                   */
+
+        struct
+        {
+            __IM uint32_t CH0ACT : 1;  /*!< [0..0] CH0ACT                                                             */
+            __IM uint32_t CH1ACT : 1;  /*!< [1..1] CH1ACT                                                             */
+            __IM uint32_t CH2ACT : 1;  /*!< [2..2] CH2ACT                                                             */
+            uint32_t             : 29;
+        } CHANNEL_STATE_b;
+    };
+
+    union
+    {
+        __OM uint32_t CHANNEL_ENABLE;  /*!< (@ 0x000023C4) Enable Operation of Channel                                */
+
+        struct
+        {
+            __OM uint32_t CH0ENA : 1;  /*!< [0..0] CH0ENA                                                             */
+            __OM uint32_t CH1ENA : 1;  /*!< [1..1] CH1ENA                                                             */
+            __OM uint32_t CH2ENA : 1;  /*!< [2..2] CH2ENA                                                             */
+            uint32_t             : 29;
+        } CHANNEL_ENABLE_b;
+    };
+
+    union
+    {
+        __OM uint32_t CHANNEL_DISABLE; /*!< (@ 0x000023C8) Disable and Reset Operation of Channel                     */
+
+        struct
+        {
+            __OM uint32_t CH0DIS : 1;  /*!< [0..0] CH0DIS                                                             */
+            __OM uint32_t CH1DIS : 1;  /*!< [1..1] CH1DIS                                                             */
+            __OM uint32_t CH2DIS : 1;  /*!< [2..2] CH2DIS                                                             */
+            uint32_t             : 29;
+        } CHANNEL_DISABLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ASI_MEM_WDATA[4]; /*!< (@ 0x000023CC) Memory Write Data Word [0..3]                              */
+
+        struct
+        {
+            __IOM uint32_t WDATA : 32;   /*!< [31..0] Destination MAC address regeneration write data                   */
+        } ASI_MEM_WDATA_b[4];
+    };
+
+    union
+    {
+        __IOM uint32_t ASI_MEM_ADDR;    /*!< (@ 0x000023DC) Memory Address and R/W Control                             */
+
+        struct
+        {
+            __IOM uint32_t ADDR    : 7; /*!< [6..0] Memory access address                                              */
+            __IOM uint32_t MEM_WEN : 1; /*!< [7..7] MEM_WEN                                                            */
+            __IOM uint32_t MEM_REQ : 3; /*!< [10..8] Memory access request                                             */
+            uint32_t               : 21;
+        } ASI_MEM_ADDR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ASI_MEM_RDATA[4]; /*!< (@ 0x000023E0) Memory Read Data Word [0..3]                               */
+
+        struct
+        {
+            __IM uint32_t RDATA : 32;   /*!< [31..0] Destination MAC address regeneration read data                    */
+        } ASI_MEM_RDATA_b[4];
+    };
+    __IM uint32_t RESERVED68[4];
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU0;    /*!< (@ 0x00002400) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD0;    /*!< (@ 0x00002404) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU0;    /*!< (@ 0x00002408) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD0;    /*!< (@ 0x0000240C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL0;      /*!< (@ 0x00002410) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM0;      /*!< (@ 0x00002414) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL0;     /*!< (@ 0x00002418) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC0;       /*!< (@ 0x0000241C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC0;      /*!< (@ 0x00002420) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC0;      /*!< (@ 0x00002424) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU1;    /*!< (@ 0x00002428) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD1;    /*!< (@ 0x0000242C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU1;    /*!< (@ 0x00002430) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD1;    /*!< (@ 0x00002434) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL1;      /*!< (@ 0x00002438) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM1;      /*!< (@ 0x0000243C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL1;     /*!< (@ 0x00002440) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC1;       /*!< (@ 0x00002444) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC1;      /*!< (@ 0x00002448) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC1;      /*!< (@ 0x0000244C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU2;    /*!< (@ 0x00002450) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD2;    /*!< (@ 0x00002454) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU2;    /*!< (@ 0x00002458) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD2;    /*!< (@ 0x0000245C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL2;      /*!< (@ 0x00002460) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM2;      /*!< (@ 0x00002464) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL2;     /*!< (@ 0x00002468) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC2;       /*!< (@ 0x0000246C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC2;      /*!< (@ 0x00002470) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC2;      /*!< (@ 0x00002474) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU3;    /*!< (@ 0x00002478) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD3;    /*!< (@ 0x0000247C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU3;    /*!< (@ 0x00002480) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD3;    /*!< (@ 0x00002484) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL3;      /*!< (@ 0x00002488) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM3;      /*!< (@ 0x0000248C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL3;     /*!< (@ 0x00002490) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC3;       /*!< (@ 0x00002494) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC3;      /*!< (@ 0x00002498) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC3;      /*!< (@ 0x0000249C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU4;    /*!< (@ 0x000024A0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD4;    /*!< (@ 0x000024A4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU4;    /*!< (@ 0x000024A8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD4;    /*!< (@ 0x000024AC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL4;      /*!< (@ 0x000024B0) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM4;      /*!< (@ 0x000024B4) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL4;     /*!< (@ 0x000024B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC4;       /*!< (@ 0x000024BC) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC4;      /*!< (@ 0x000024C0) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC4;      /*!< (@ 0x000024C4) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU5;    /*!< (@ 0x000024C8) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD5;    /*!< (@ 0x000024CC) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU5;    /*!< (@ 0x000024D0) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD5;    /*!< (@ 0x000024D4) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL5;      /*!< (@ 0x000024D8) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM5;      /*!< (@ 0x000024DC) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL5;     /*!< (@ 0x000024E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC5;       /*!< (@ 0x000024E4) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC5;      /*!< (@ 0x000024E8) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC5;      /*!< (@ 0x000024EC) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU6;    /*!< (@ 0x000024F0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD6;    /*!< (@ 0x000024F4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU6;    /*!< (@ 0x000024F8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD6;    /*!< (@ 0x000024FC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL6;      /*!< (@ 0x00002500) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM6;      /*!< (@ 0x00002504) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL6;     /*!< (@ 0x00002508) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC6;       /*!< (@ 0x0000250C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC6;      /*!< (@ 0x00002510) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC6;      /*!< (@ 0x00002514) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACU7;    /*!< (@ 0x00002518) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P1_QSTMACU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMACD7;    /*!< (@ 0x0000251C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P1_QSTMACD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMU7;    /*!< (@ 0x00002520) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P1_QSTMAMU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSTMAMD7;    /*!< (@ 0x00002524) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P1_QSTMAMD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVL7;      /*!< (@ 0x00002528) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P1_QSFTVL7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTVLM7;      /*!< (@ 0x0000252C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P1_QSFTVLM7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSFTBL7;     /*!< (@ 0x00002530) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P1_QSFTBL7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QSMFC7;       /*!< (@ 0x00002534) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P1_QSMFC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSPPC7;      /*!< (@ 0x00002538) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P1_QMSPPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMSRPC7;      /*!< (@ 0x0000253C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P1_QMSRPC7_b;
+    };
+    __IM uint32_t RESERVED69[42];
+
+    union
+    {
+        __IOM uint32_t P1_QSEIS;       /*!< (@ 0x000025E8) Qci Stream Filter Error Interrupt Status (SDU
+                                        *                  Oversize)                                                  */
+
+        struct
+        {
+            __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
+            uint32_t              : 24;
+        } P1_QSEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QSEIE;       /*!< (@ 0x000025EC) Qci Stream Filter Error Interrupt Enable                   */
+
+        struct
+        {
+            __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
+            uint32_t              : 24;
+        } P1_QSEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P1_QSEID;        /*!< (@ 0x000025F0) Qci Stream Filter Error Interrupt Disable                  */
+
+        struct
+        {
+            __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
+            uint32_t             : 24;
+        } P1_QSEID_b;
+    };
+    __IM uint32_t RESERVED70[3];
+
+    union
+    {
+        __IOM uint32_t P1_QGMOD;       /*!< (@ 0x00002600) Qci Gate Mode Register                                     */
+
+        struct
+        {
+            __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
+            uint32_t             : 24;
+        } P1_QGMOD_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QGPPC;        /*!< (@ 0x00002604) Qci Gate (All) Passed Packet Count Port 1                  */
+
+        struct
+        {
+            __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
+            uint32_t            : 16;
+        } P1_QGPPC_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QGDPC0;       /*!< (@ 0x00002608) Qci Gate 0 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC0_b;
+    };
+    __IM uint32_t RESERVED71;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC1;       /*!< (@ 0x00002610) Qci Gate 1 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC1_b;
+    };
+    __IM uint32_t RESERVED72;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC2;       /*!< (@ 0x00002618) Qci Gate 2 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC2_b;
+    };
+    __IM uint32_t RESERVED73;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC3;       /*!< (@ 0x00002620) Qci Gate 3 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC3_b;
+    };
+    __IM uint32_t RESERVED74;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC4;       /*!< (@ 0x00002628) Qci Gate 4 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC4_b;
+    };
+    __IM uint32_t RESERVED75;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC5;       /*!< (@ 0x00002630) Qci Gate 5 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC5_b;
+    };
+    __IM uint32_t RESERVED76;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC6;       /*!< (@ 0x00002638) Qci Gate 6 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC6_b;
+    };
+    __IM uint32_t RESERVED77;
+
+    union
+    {
+        __IM uint32_t P1_QGDPC7;       /*!< (@ 0x00002640) Qci Gate 7 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P1_QGDPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QGEIS;       /*!< (@ 0x00002644) Qci Gate Error Interrupt Status                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
+            uint32_t              : 24;
+        } P1_QGEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QGEIE;       /*!< (@ 0x00002648) Qci Gate Error Interrupt Enable                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
+            uint32_t              : 24;
+        } P1_QGEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P1_QGEID;        /*!< (@ 0x0000264C) Qci Gate Error Interrupt Disable                           */
+
+        struct
+        {
+            __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
+            uint32_t             : 24;
+        } P1_QGEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC0;     /*!< (@ 0x00002650) Qci Port n Flow Meter 0 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC0;     /*!< (@ 0x00002654) Qci Meter CBS Configuration Port n, Meter 0                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC0;     /*!< (@ 0x00002658) Qci Meter CIR Configuration n 0                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC0;       /*!< (@ 0x0000265C) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC0;       /*!< (@ 0x00002660) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC1;     /*!< (@ 0x00002664) Qci Port n Flow Meter 1 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC1;     /*!< (@ 0x00002668) Qci Meter CBS Configuration Port n, Meter 1                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC1;     /*!< (@ 0x0000266C) Qci Meter CIR Configuration n 1                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC1;       /*!< (@ 0x00002670) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC1;       /*!< (@ 0x00002674) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC2;     /*!< (@ 0x00002678) Qci Port n Flow Meter 2 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC2;     /*!< (@ 0x0000267C) Qci Meter CBS Configuration Port n, Meter 2                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC2;     /*!< (@ 0x00002680) Qci Meter CIR Configuration n 2                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC2;       /*!< (@ 0x00002684) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC2;       /*!< (@ 0x00002688) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC3;     /*!< (@ 0x0000268C) Qci Port n Flow Meter 3 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC3;     /*!< (@ 0x00002690) Qci Meter CBS Configuration Port n, Meter 3                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC3;     /*!< (@ 0x00002694) Qci Meter CIR Configuration n 3                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC3;       /*!< (@ 0x00002698) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC3;       /*!< (@ 0x0000269C) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC4;     /*!< (@ 0x000026A0) Qci Port n Flow Meter 4 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC4;     /*!< (@ 0x000026A4) Qci Meter CBS Configuration Port n, Meter 4                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC4;     /*!< (@ 0x000026A8) Qci Meter CIR Configuration n 4                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC4;       /*!< (@ 0x000026AC) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC4;       /*!< (@ 0x000026B0) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC5;     /*!< (@ 0x000026B4) Qci Port n Flow Meter 5 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC5;     /*!< (@ 0x000026B8) Qci Meter CBS Configuration Port n, Meter 5                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC5;     /*!< (@ 0x000026BC) Qci Meter CIR Configuration n 5                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC5;       /*!< (@ 0x000026C0) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC5;       /*!< (@ 0x000026C4) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC6;     /*!< (@ 0x000026C8) Qci Port n Flow Meter 6 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC6;     /*!< (@ 0x000026CC) Qci Meter CBS Configuration Port n, Meter 6                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC6;     /*!< (@ 0x000026D0) Qci Meter CIR Configuration n 6                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC6;       /*!< (@ 0x000026D4) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC6;       /*!< (@ 0x000026D8) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMDESC7;     /*!< (@ 0x000026DC) Qci Port n Flow Meter 7 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P1_QMDESC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCBSC7;     /*!< (@ 0x000026E0) Qci Meter CBS Configuration Port n, Meter 7                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P1_QMCBSC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMCIRC7;     /*!< (@ 0x000026E4) Qci Meter CIR Configuration n 7                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P1_QMCIRC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMGPC7;       /*!< (@ 0x000026E8) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P1_QMGPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_QMRPC7;       /*!< (@ 0x000026EC) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P1_QMRPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMEC;        /*!< (@ 0x000026F0) Qci Meter Enable Configuration                             */
+
+        struct
+        {
+            __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
+            uint32_t          : 24;
+        } P1_QMEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMEIS;       /*!< (@ 0x000026F4) Qci Meter Error Interrupt Status                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
+            uint32_t             : 24;
+        } P1_QMEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_QMEIE;       /*!< (@ 0x000026F8) Qci Meter Error Interrupt Enable                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
+            uint32_t             : 24;
+        } P1_QMEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P1_QMEID;        /*!< (@ 0x000026FC) Qci Meter Error Interrupt Disable                          */
+
+        struct
+        {
+            __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
+            uint32_t            : 24;
+        } P1_QMEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_PCP_REMAP;       /*!< (@ 0x00002700) Port 1 VLAN Priority Code Point (PCP) Remap                */
+
+        struct
+        {
+            __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
+            __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
+            __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
+            __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
+            __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
+            __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
+            __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
+            __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
+            uint32_t                  : 8;
+        } P1_PCP_REMAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_VLAN_TAG;    /*!< (@ 0x00002704) Port 1 VLAN TAG Information for Priority Regeneration      */
+
+        struct
+        {
+            __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
+            __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
+        } P1_VLAN_TAG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_VLAN_MODE;   /*!< (@ 0x00002708) Port 1 VLAN Mode                                           */
+
+        struct
+        {
+            __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
+            __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
+            uint32_t            : 28;
+        } P1_VLAN_MODE_b;
+    };
+
+    union
+    {
+        __IM uint32_t P1_VIC_DROP_CNT;       /*!< (@ 0x0000270C) Port 1 VLAN Ingress Check Drop Frame Counter               */
+
+        struct
+        {
+            __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
+            uint32_t                   : 16;
+        } P1_VIC_DROP_CNT_b;
+    };
+    __IM uint32_t RESERVED78[6];
+
+    union
+    {
+        __IM uint32_t P1_LOOKUP_HIT_CNT;       /*!< (@ 0x00002728) Port 1 DST Address Lookup Hit Counter                      */
+
+        struct
+        {
+            __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
+            uint32_t                     : 8;
+        } P1_LOOKUP_HIT_CNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_ERROR_STATUS; /*!< (@ 0x0000272C) Port 1 Frame Parser Runtime Error Status                   */
+
+        struct
+        {
+            __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
+            __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
+                                         *   parser                                                                    */
+            __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
+            __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
+            __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
+            uint32_t              : 27;
+        } P1_ERROR_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1_ERROR_MASK;   /*!< (@ 0x00002730) Port 1 Frame Parser Runtime Error Mask                     */
+
+        struct
+        {
+            __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
+            __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
+            __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
+            __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
+            __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
+            uint32_t               : 27;
+        } P1_ERROR_MASK_b;
+    };
+    __IM uint32_t RESERVED79[51];
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU0;    /*!< (@ 0x00002800) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD0;    /*!< (@ 0x00002804) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU0;    /*!< (@ 0x00002808) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD0;    /*!< (@ 0x0000280C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL0;      /*!< (@ 0x00002810) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM0;      /*!< (@ 0x00002814) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL0;     /*!< (@ 0x00002818) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC0;       /*!< (@ 0x0000281C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC0;      /*!< (@ 0x00002820) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC0;      /*!< (@ 0x00002824) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU1;    /*!< (@ 0x00002828) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD1;    /*!< (@ 0x0000282C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU1;    /*!< (@ 0x00002830) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD1;    /*!< (@ 0x00002834) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL1;      /*!< (@ 0x00002838) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM1;      /*!< (@ 0x0000283C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL1;     /*!< (@ 0x00002840) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC1;       /*!< (@ 0x00002844) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC1;      /*!< (@ 0x00002848) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC1;      /*!< (@ 0x0000284C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU2;    /*!< (@ 0x00002850) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD2;    /*!< (@ 0x00002854) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU2;    /*!< (@ 0x00002858) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD2;    /*!< (@ 0x0000285C) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL2;      /*!< (@ 0x00002860) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM2;      /*!< (@ 0x00002864) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL2;     /*!< (@ 0x00002868) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC2;       /*!< (@ 0x0000286C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC2;      /*!< (@ 0x00002870) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC2;      /*!< (@ 0x00002874) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU3;    /*!< (@ 0x00002878) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD3;    /*!< (@ 0x0000287C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU3;    /*!< (@ 0x00002880) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD3;    /*!< (@ 0x00002884) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL3;      /*!< (@ 0x00002888) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM3;      /*!< (@ 0x0000288C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL3;     /*!< (@ 0x00002890) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC3;       /*!< (@ 0x00002894) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC3;      /*!< (@ 0x00002898) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC3;      /*!< (@ 0x0000289C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU4;    /*!< (@ 0x000028A0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD4;    /*!< (@ 0x000028A4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU4;    /*!< (@ 0x000028A8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD4;    /*!< (@ 0x000028AC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL4;      /*!< (@ 0x000028B0) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM4;      /*!< (@ 0x000028B4) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL4;     /*!< (@ 0x000028B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC4;       /*!< (@ 0x000028BC) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC4;      /*!< (@ 0x000028C0) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC4;      /*!< (@ 0x000028C4) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU5;    /*!< (@ 0x000028C8) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD5;    /*!< (@ 0x000028CC) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU5;    /*!< (@ 0x000028D0) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD5;    /*!< (@ 0x000028D4) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL5;      /*!< (@ 0x000028D8) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM5;      /*!< (@ 0x000028DC) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL5;     /*!< (@ 0x000028E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC5;       /*!< (@ 0x000028E4) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC5;      /*!< (@ 0x000028E8) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC5;      /*!< (@ 0x000028EC) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU6;    /*!< (@ 0x000028F0) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD6;    /*!< (@ 0x000028F4) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU6;    /*!< (@ 0x000028F8) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD6;    /*!< (@ 0x000028FC) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL6;      /*!< (@ 0x00002900) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM6;      /*!< (@ 0x00002904) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL6;     /*!< (@ 0x00002908) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC6;       /*!< (@ 0x0000290C) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC6;      /*!< (@ 0x00002910) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC6;      /*!< (@ 0x00002914) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACU7;    /*!< (@ 0x00002918) Qci Stream Filter Table MAC Address Upper Part             */
+
+        struct
+        {
+            __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
+            __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
+            uint32_t            : 15;
+        } P2_QSTMACU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMACD7;    /*!< (@ 0x0000291C) Qci Stream Filter Table MAC Address Downer Part            */
+
+        struct
+        {
+            __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
+        } P2_QSTMACD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMU7;    /*!< (@ 0x00002920) Qci Stream Filter Table MAC Address Mask Upper
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
+            uint32_t             : 16;
+        } P2_QSTMAMU7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSTMAMD7;    /*!< (@ 0x00002924) Qci Stream Filter Table MAC Address Mask Downer
+                                        *                  Part                                                       */
+
+        struct
+        {
+            __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
+        } P2_QSTMAMD7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVL7;      /*!< (@ 0x00002928) Qci Stream Filter Table VLAN                               */
+
+        struct
+        {
+            __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
+            __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
+            uint32_t              : 14;
+        } P2_QSFTVL7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTVLM7;      /*!< (@ 0x0000292C) Qci Stream Filter Table VLAN Mask                          */
+
+        struct
+        {
+            __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
+            __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
+            __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
+            uint32_t               : 16;
+        } P2_QSFTVLM7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSFTBL7;     /*!< (@ 0x00002930) Qci Stream Filter Table SDU/Gate/Meter ID                  */
+
+        struct
+        {
+            __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
+            uint32_t             : 3;
+            __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
+            __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
+            __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
+            uint32_t             : 3;
+            __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
+            __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
+            __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
+            uint32_t             : 3;
+        } P2_QSFTBL7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QSMFC7;       /*!< (@ 0x00002934) Qci Stream Match Packet Count                              */
+
+        struct
+        {
+            __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
+            uint32_t            : 16;
+        } P2_QSMFC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSPPC7;      /*!< (@ 0x00002938) Qci MSDU Passed Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
+            uint32_t             : 16;
+        } P2_QMSPPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMSRPC7;      /*!< (@ 0x0000293C) Qci MSDU Reject Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
+            uint32_t             : 16;
+        } P2_QMSRPC7_b;
+    };
+    __IM uint32_t RESERVED80[42];
+
+    union
+    {
+        __IOM uint32_t P2_QSEIS;       /*!< (@ 0x000029E8) Qci Stream Filter Error Interrupt Status (SDU
+                                        *                  Oversize)                                                  */
+
+        struct
+        {
+            __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
+            uint32_t              : 24;
+        } P2_QSEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QSEIE;       /*!< (@ 0x000029EC) Qci Stream Filter Error Interrupt Enable                   */
+
+        struct
+        {
+            __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
+            uint32_t              : 24;
+        } P2_QSEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P2_QSEID;        /*!< (@ 0x000029F0) Qci Stream Filter Error Interrupt Disable                  */
+
+        struct
+        {
+            __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
+            uint32_t             : 24;
+        } P2_QSEID_b;
+    };
+    __IM uint32_t RESERVED81[3];
+
+    union
+    {
+        __IOM uint32_t P2_QGMOD;       /*!< (@ 0x00002A00) Qci Gate Mode Register                                     */
+
+        struct
+        {
+            __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
+            uint32_t             : 24;
+        } P2_QGMOD_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QGPPC;        /*!< (@ 0x00002A04) Qci Gate (All) Passed Packet Count Port 2                  */
+
+        struct
+        {
+            __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
+            uint32_t            : 16;
+        } P2_QGPPC_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QGDPC0;       /*!< (@ 0x00002A08) Qci Gate 0 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC0_b;
+    };
+    __IM uint32_t RESERVED82;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC1;       /*!< (@ 0x00002A10) Qci Gate 1 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC1_b;
+    };
+    __IM uint32_t RESERVED83;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC2;       /*!< (@ 0x00002A18) Qci Gate 2 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC2_b;
+    };
+    __IM uint32_t RESERVED84;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC3;       /*!< (@ 0x00002A20) Qci Gate 3 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC3_b;
+    };
+    __IM uint32_t RESERVED85;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC4;       /*!< (@ 0x00002A28) Qci Gate 4 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC4_b;
+    };
+    __IM uint32_t RESERVED86;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC5;       /*!< (@ 0x00002A30) Qci Gate 5 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC5_b;
+    };
+    __IM uint32_t RESERVED87;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC6;       /*!< (@ 0x00002A38) Qci Gate 6 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC6_b;
+    };
+    __IM uint32_t RESERVED88;
+
+    union
+    {
+        __IM uint32_t P2_QGDPC7;       /*!< (@ 0x00002A40) Qci Gate 7 Dropped Packet Count Port n                     */
+
+        struct
+        {
+            __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
+            uint32_t            : 16;
+        } P2_QGDPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QGEIS;       /*!< (@ 0x00002A44) Qci Gate Error Interrupt Status                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
+            uint32_t              : 24;
+        } P2_QGEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QGEIE;       /*!< (@ 0x00002A48) Qci Gate Error Interrupt Enable                            */
+
+        struct
+        {
+            __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
+            uint32_t              : 24;
+        } P2_QGEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P2_QGEID;        /*!< (@ 0x00002A4C) Qci Gate Error Interrupt Disable                           */
+
+        struct
+        {
+            __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
+            uint32_t             : 24;
+        } P2_QGEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC0;     /*!< (@ 0x00002A50) Qci Port n Flow Meter 0 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC0;     /*!< (@ 0x00002A54) Qci Meter CBS Configuration Port n, Meter 0                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC0;     /*!< (@ 0x00002A58) Qci Meter CIR Configuration n 0                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC0;       /*!< (@ 0x00002A5C) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC0;       /*!< (@ 0x00002A60) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC1;     /*!< (@ 0x00002A64) Qci Port n Flow Meter 1 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC1;     /*!< (@ 0x00002A68) Qci Meter CBS Configuration Port n, Meter 1                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC1;     /*!< (@ 0x00002A6C) Qci Meter CIR Configuration n 1                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC1;       /*!< (@ 0x00002A70) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC1;       /*!< (@ 0x00002A74) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC2;     /*!< (@ 0x00002A78) Qci Port n Flow Meter 2 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC2;     /*!< (@ 0x00002A7C) Qci Meter CBS Configuration Port n, Meter 2                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC2;     /*!< (@ 0x00002A80) Qci Meter CIR Configuration n 2                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC2;       /*!< (@ 0x00002A84) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC2;       /*!< (@ 0x00002A88) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC3;     /*!< (@ 0x00002A8C) Qci Port n Flow Meter 3 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC3;     /*!< (@ 0x00002A90) Qci Meter CBS Configuration Port n, Meter 3                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC3;     /*!< (@ 0x00002A94) Qci Meter CIR Configuration n 3                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC3;       /*!< (@ 0x00002A98) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC3;       /*!< (@ 0x00002A9C) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC4;     /*!< (@ 0x00002AA0) Qci Port n Flow Meter 4 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC4;     /*!< (@ 0x00002AA4) Qci Meter CBS Configuration Port n, Meter 4                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC4;     /*!< (@ 0x00002AA8) Qci Meter CIR Configuration n 4                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC4;       /*!< (@ 0x00002AAC) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC4_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC4;       /*!< (@ 0x00002AB0) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC5;     /*!< (@ 0x00002AB4) Qci Port n Flow Meter 5 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC5;     /*!< (@ 0x00002AB8) Qci Meter CBS Configuration Port n, Meter 5                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC5;     /*!< (@ 0x00002ABC) Qci Meter CIR Configuration n 5                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC5;       /*!< (@ 0x00002AC0) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC5_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC5;       /*!< (@ 0x00002AC4) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC6;     /*!< (@ 0x00002AC8) Qci Port n Flow Meter 6 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC6;     /*!< (@ 0x00002ACC) Qci Meter CBS Configuration Port n, Meter 6                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC6;     /*!< (@ 0x00002AD0) Qci Meter CIR Configuration n 6                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC6;       /*!< (@ 0x00002AD4) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC6_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC6;       /*!< (@ 0x00002AD8) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMDESC7;     /*!< (@ 0x00002ADC) Qci Port n Flow Meter 7 Descriptor Register                */
+
+        struct
+        {
+            __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
+            __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
+            __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
+            uint32_t           : 29;
+        } P2_QMDESC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCBSC7;     /*!< (@ 0x00002AE0) Qci Meter CBS Configuration Port n, Meter 7                */
+
+        struct
+        {
+            __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
+            uint32_t           : 14;
+        } P2_QMCBSC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMCIRC7;     /*!< (@ 0x00002AE4) Qci Meter CIR Configuration n 7                            */
+
+        struct
+        {
+            __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
+            uint32_t           : 15;
+        } P2_QMCIRC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMGPC7;       /*!< (@ 0x00002AE8) Qci Meter Green Packet Count                               */
+
+        struct
+        {
+            __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
+            uint32_t            : 16;
+        } P2_QMGPC7_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_QMRPC7;       /*!< (@ 0x00002AEC) Qci Meter Red Packet Count                                 */
+
+        struct
+        {
+            __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
+            uint32_t            : 16;
+        } P2_QMRPC7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMEC;        /*!< (@ 0x00002AF0) Qci Meter Enable Configuration                             */
+
+        struct
+        {
+            __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
+            uint32_t          : 24;
+        } P2_QMEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMEIS;       /*!< (@ 0x00002AF4) Qci Meter Error Interrupt Status                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
+            uint32_t             : 24;
+        } P2_QMEIS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_QMEIE;       /*!< (@ 0x00002AF8) Qci Meter Error Interrupt Enable                           */
+
+        struct
+        {
+            __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
+            uint32_t             : 24;
+        } P2_QMEIE_b;
+    };
+
+    union
+    {
+        __OM uint32_t P2_QMEID;        /*!< (@ 0x00002AFC) Qci Meter Error Interrupt Disable                          */
+
+        struct
+        {
+            __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
+            uint32_t            : 24;
+        } P2_QMEID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_PCP_REMAP;       /*!< (@ 0x00002B00) Port 2 VLAN Priority Code Point (PCP) Remap                */
+
+        struct
+        {
+            __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
+            __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
+            __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
+            __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
+            __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
+            __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
+            __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
+            __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
+            uint32_t                  : 8;
+        } P2_PCP_REMAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_VLAN_TAG;    /*!< (@ 0x00002B04) Port 2 VLAN TAG Information for Priority Regeneration      */
+
+        struct
+        {
+            __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
+            __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
+            __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
+            __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
+        } P2_VLAN_TAG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_VLAN_MODE;   /*!< (@ 0x00002B08) Port 2 VLAN Mode                                           */
+
+        struct
+        {
+            __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
+            __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
+            uint32_t            : 28;
+        } P2_VLAN_MODE_b;
+    };
+
+    union
+    {
+        __IM uint32_t P2_VIC_DROP_CNT;       /*!< (@ 0x00002B0C) Port 2 VLAN Ingress Check Drop Frame Counter               */
+
+        struct
+        {
+            __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
+            uint32_t                   : 16;
+        } P2_VIC_DROP_CNT_b;
+    };
+    __IM uint32_t RESERVED89[6];
+
+    union
+    {
+        __IM uint32_t P2_LOOKUP_HIT_CNT;       /*!< (@ 0x00002B28) Port 2 DST Address Lookup Hit Counter                      */
+
+        struct
+        {
+            __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
+            uint32_t                     : 8;
+        } P2_LOOKUP_HIT_CNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_ERROR_STATUS; /*!< (@ 0x00002B2C) Port 2 Frame Parser Runtime Error Status                   */
+
+        struct
+        {
+            __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
+            __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
+                                         *   parser                                                                    */
+            __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
+            __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
+            __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
+            uint32_t              : 27;
+        } P2_ERROR_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P2_ERROR_MASK;   /*!< (@ 0x00002B30) Port 2 Frame Parser Runtime Error Mask                     */
+
+        struct
+        {
+            __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
+            __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
+            __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
+            __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
+            __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
+            uint32_t               : 27;
+        } P2_ERROR_MASK_b;
+    };
+    __IM uint32_t RESERVED90[564];
+
+    union
+    {
+        __IM uint32_t STATN_STATUS;    /*!< (@ 0x00003404) Statistics Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t BUSY : 1;    /*!< [0..0] Statistics module is busy                                          */
+            uint32_t           : 31;
+        } STATN_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATN_CONFIG;   /*!< (@ 0x00003408) Statistics Configure Register                              */
+
+        struct
+        {
+            uint32_t                     : 1;
+            __IOM uint32_t CLEAR_ON_READ : 1; /*!< [1..1] When set to 1, a read to a counter resets it to 0. When
+                                               *   set to 0 (default), counters are not affected by read.                    */
+            uint32_t             : 29;
+            __IOM uint32_t RESET : 1;         /*!< [31..31] When set to 1, all internal functions are aborted and
+                                               *   return to a stable state (flushes prescalers). It also
+                                               *   triggers a clear of all counter memory (all ports are cleared)
+                                               *   by setting STATN_CONTROL.CMD_CLEAR with all mask bits.
+                                               *   Capture memory is not reset.                                              */
+        } STATN_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATN_CONTROL;     /*!< (@ 0x0000340C) Statistics Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t CHANMASK : 4;  /*!< [3..0] One bit per port. Bit 0 = port 0, bit 1 = port 1, and
+                                           *   so on.                                                                    */
+            uint32_t                 : 25;
+            __IOM uint32_t CLEAR_PRE : 1; /*!< [29..29] Clear the internal pre-scaler counters of ports when
+                                           *   a clear occurs. This bit can be used together with the
+                                           *   CMD_CLEAR command to clear the internal pre-scaler counters
+                                           *   of the ports.                                                             */
+            uint32_t                 : 1;
+            __IOM uint32_t CMD_CLEAR : 1; /*!< [31..31] Clear Channel Counters Command                                   */
+        } STATN_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STATN_CLEARVALUE_LO;          /*!< (@ 0x00003410) Statistics Clear Value Lower Register                      */
+
+        struct
+        {
+            __IOM uint32_t STATN_CLEARVALUE_LO : 32; /*!< [31..0] 32-bit value written into statistics memory when a clear
+                                                      *   command (STATN_CONTROL.CMD_CLEAR) is triggered (see ),
+                                                      *   or when a clear-after-read is used.                                       */
+        } STATN_CLEARVALUE_LO_b;
+    };
+    __IM uint32_t RESERVED91[21];
+
+    union
+    {
+        __IM uint32_t ODISC0;          /*!< (@ 0x00003468) Port 0 Discarded Outgoing Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
+                                        *   congestion.                                                               */
+        } ODISC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_VLAN0;         /*!< (@ 0x0000346C) Port 0 Discarded Incoming VLAN Tagged Frame Count
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
+                                            *   or missing VLAN ID while VLAN verification was enabled.                   */
+        } IDISC_VLAN0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_UNTAGGED0;         /*!< (@ 0x00003470) Port 0 Discarded Incoming VLAN Untagged Frame
+                                                *                  Count Register                                             */
+
+        struct
+        {
+            __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
+                                                *   tag.                                                                      */
+        } IDISC_UNTAGGED0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_BLOCKED0;         /*!< (@ 0x00003474) Port 0 Discarded Incoming Blocked Frame Count
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
+                                               *   the port is configured in blocking mode.                                  */
+        } IDISC_BLOCKED0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_ANY0;         /*!< (@ 0x00003478) Port 0 Discarded Any Frame Count Register (n
+                                           *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
+                                           *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
+        } IDISC_ANY0_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_SRCFLT0;         /*!< (@ 0x0000347C) Port 0 Discarded Address Source Count Register             */
+
+        struct
+        {
+            __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
+                                              *   due to the MAC address source filter.                                     */
+        } IDISC_SRCFLT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_HOLD_REQ_CNT0;         /*!< (@ 0x00003480) Port 0 TX Hold Request Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
+        } TX_HOLD_REQ_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_FRAG_CNT0;         /*!< (@ 0x00003484) Port 0 TX for Preemption Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
+                                             *   due to preemption.                                                        */
+        } TX_FRAG_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_FRAG_CNT0;         /*!< (@ 0x00003488) Port 0 RX Continuation Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
+        } RX_FRAG_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_OK_CNT0;         /*!< (@ 0x0000348C) Port 0 RX Preempted Frame Success Count Register           */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
+                                                *   assembled.                                                                */
+        } RX_ASSY_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_ERR_CNT0;         /*!< (@ 0x00003490) Port 0 RX Preempted Frame Incorrect Count Register         */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
+                                                 *   assembled.                                                                */
+            uint32_t : 16;
+        } RX_ASSY_ERR_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_SMD_ERR_CNT0;         /*!< (@ 0x00003494) Port 0 RX SMD Frame Count Register                         */
+
+        struct
+        {
+            __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
+                                                *   and no assembly is in progress.                                           */
+            uint32_t : 16;
+        } RX_SMD_ERR_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_VERIFY_OK_CNT0;        /*!< (@ 0x00003498) Port 0 TX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
+            uint32_t                       : 24;
+        } TX_VERIFY_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_RESPONSE_OK_CNT0;        /*!< (@ 0x0000349C) Port 0 TX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
+            uint32_t                         : 24;
+        } TX_RESPONSE_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_OK_CNT0;        /*!< (@ 0x000034A0) Port 0 RX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
+            uint32_t                       : 24;
+        } RX_VERIFY_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_OK_CNT0;        /*!< (@ 0x000034A4) Port 0 RX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
+            uint32_t                         : 24;
+        } RX_RESPONSE_OK_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_BAD_CNT0;        /*!< (@ 0x000034A8) Port 0 RX Error VERIFY Frame Count Register                */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
+            uint32_t                        : 24;
+        } RX_VERIFY_BAD_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_BAD_CNT0;        /*!< (@ 0x000034AC) Port 0 RX Error RESPONSE Frame Count Register              */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
+            uint32_t                          : 24;
+        } RX_RESPONSE_BAD_CNT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ODISC1;          /*!< (@ 0x000034B0) Port 1 Discarded Outgoing Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
+                                        *   congestion.                                                               */
+        } ODISC1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_VLAN1;         /*!< (@ 0x000034B4) Port 1 Discarded Incoming VLAN Tagged Frame Count
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
+                                            *   or missing VLAN ID while VLAN verification was enabled.                   */
+        } IDISC_VLAN1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_UNTAGGED1;         /*!< (@ 0x000034B8) Port 1 Discarded Incoming VLAN Untagged Frame
+                                                *                  Count Register                                             */
+
+        struct
+        {
+            __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
+                                                *   tag.                                                                      */
+        } IDISC_UNTAGGED1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_BLOCKED1;         /*!< (@ 0x000034BC) Port 1 Discarded Incoming Blocked Frame Count
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
+                                               *   the port is configured in blocking mode.                                  */
+        } IDISC_BLOCKED1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_ANY1;         /*!< (@ 0x000034C0) Port 1 Discarded Any Frame Count Register (n
+                                           *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
+                                           *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
+        } IDISC_ANY1_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_SRCFLT1;         /*!< (@ 0x000034C4) Port 1 Discarded Address Source Count Register             */
+
+        struct
+        {
+            __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
+                                              *   due to the MAC address source filter.                                     */
+        } IDISC_SRCFLT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_HOLD_REQ_CNT1;         /*!< (@ 0x000034C8) Port 1 TX Hold Request Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
+        } TX_HOLD_REQ_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_FRAG_CNT1;         /*!< (@ 0x000034CC) Port 1 TX for Preemption Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
+                                             *   due to preemption.                                                        */
+        } TX_FRAG_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_FRAG_CNT1;         /*!< (@ 0x000034D0) Port 1 RX Continuation Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
+        } RX_FRAG_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_OK_CNT1;         /*!< (@ 0x000034D4) Port 1 RX Preempted Frame Success Count Register           */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
+                                                *   assembled.                                                                */
+        } RX_ASSY_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_ERR_CNT1;         /*!< (@ 0x000034D8) Port 1 RX Preempted Frame Incorrect Count Register         */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
+                                                 *   assembled.                                                                */
+            uint32_t : 16;
+        } RX_ASSY_ERR_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_SMD_ERR_CNT1;         /*!< (@ 0x000034DC) Port 1 RX SMD Frame Count Register                         */
+
+        struct
+        {
+            __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
+                                                *   and no assembly is in progress.                                           */
+            uint32_t : 16;
+        } RX_SMD_ERR_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_VERIFY_OK_CNT1;        /*!< (@ 0x000034E0) Port 1 TX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
+            uint32_t                       : 24;
+        } TX_VERIFY_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_RESPONSE_OK_CNT1;        /*!< (@ 0x000034E4) Port 1 TX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
+            uint32_t                         : 24;
+        } TX_RESPONSE_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_OK_CNT1;        /*!< (@ 0x000034E8) Port 1 RX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
+            uint32_t                       : 24;
+        } RX_VERIFY_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_OK_CNT1;        /*!< (@ 0x000034EC) Port 1 RX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
+            uint32_t                         : 24;
+        } RX_RESPONSE_OK_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_BAD_CNT1;        /*!< (@ 0x000034F0) Port 1 RX Error VERIFY Frame Count Register                */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
+            uint32_t                        : 24;
+        } RX_VERIFY_BAD_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_BAD_CNT1;        /*!< (@ 0x000034F4) Port 1 RX Error RESPONSE Frame Count Register              */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
+            uint32_t                          : 24;
+        } RX_RESPONSE_BAD_CNT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ODISC2;          /*!< (@ 0x000034F8) Port 2 Discarded Outgoing Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
+                                        *   congestion.                                                               */
+        } ODISC2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_VLAN2;         /*!< (@ 0x000034FC) Port 2 Discarded Incoming VLAN Tagged Frame Count
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
+                                            *   or missing VLAN ID while VLAN verification was enabled.                   */
+        } IDISC_VLAN2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_UNTAGGED2;         /*!< (@ 0x00003500) Port 2 Discarded Incoming VLAN Untagged Frame
+                                                *                  Count Register                                             */
+
+        struct
+        {
+            __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
+                                                *   tag.                                                                      */
+        } IDISC_UNTAGGED2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_BLOCKED2;         /*!< (@ 0x00003504) Port 2 Discarded Incoming Blocked Frame Count
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
+                                               *   the port is configured in blocking mode.                                  */
+        } IDISC_BLOCKED2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_ANY2;         /*!< (@ 0x00003508) Port 2 Discarded Any Frame Count Register (n
+                                           *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
+                                           *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
+        } IDISC_ANY2_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_SRCFLT2;         /*!< (@ 0x0000350C) Port 2 Discarded Address Source Count Register             */
+
+        struct
+        {
+            __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
+                                              *   due to the MAC address source filter.                                     */
+        } IDISC_SRCFLT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_HOLD_REQ_CNT2;         /*!< (@ 0x00003510) Port 2 TX Hold Request Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
+        } TX_HOLD_REQ_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_FRAG_CNT2;         /*!< (@ 0x00003514) Port 2 TX for Preemption Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
+                                             *   due to preemption.                                                        */
+        } TX_FRAG_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_FRAG_CNT2;         /*!< (@ 0x00003518) Port 2 RX Continuation Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
+        } RX_FRAG_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_OK_CNT2;         /*!< (@ 0x0000351C) Port 2 RX Preempted Frame Success Count Register           */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
+                                                *   assembled.                                                                */
+        } RX_ASSY_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_ASSY_ERR_CNT2;         /*!< (@ 0x00003520) Port 2 RX Preempted Frame Incorrect Count Register         */
+
+        struct
+        {
+            __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
+                                                 *   assembled.                                                                */
+            uint32_t : 16;
+        } RX_ASSY_ERR_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_SMD_ERR_CNT2;         /*!< (@ 0x00003524) Port 2 RX SMD Frame Count Register                         */
+
+        struct
+        {
+            __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
+                                                *   and no assembly is in progress.                                           */
+            uint32_t : 16;
+        } RX_SMD_ERR_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_VERIFY_OK_CNT2;        /*!< (@ 0x00003528) Port 2 TX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
+            uint32_t                       : 24;
+        } TX_VERIFY_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t TX_RESPONSE_OK_CNT2;        /*!< (@ 0x0000352C) Port 2 TX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
+            uint32_t                         : 24;
+        } TX_RESPONSE_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_OK_CNT2;        /*!< (@ 0x00003530) Port 2 RX VERIFY Frame Count Register                      */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
+            uint32_t                       : 24;
+        } RX_VERIFY_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_OK_CNT2;        /*!< (@ 0x00003534) Port 2 RX RESPONSE Frame Count Register                    */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
+            uint32_t                         : 24;
+        } RX_RESPONSE_OK_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_VERIFY_BAD_CNT2;        /*!< (@ 0x00003538) Port 2 RX Error VERIFY Frame Count Register                */
+
+        struct
+        {
+            __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
+            uint32_t                        : 24;
+        } RX_VERIFY_BAD_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RX_RESPONSE_BAD_CNT2;        /*!< (@ 0x0000353C) Port 2 RX Error RESPONSE Frame Count Register              */
+
+        struct
+        {
+            __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
+            uint32_t                          : 24;
+        } RX_RESPONSE_BAD_CNT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ODISC3;          /*!< (@ 0x00003540) Port 3 Discarded Outgoing Frame Count Register             */
+
+        struct
+        {
+            __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
+                                        *   congestion.                                                               */
+        } ODISC3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_VLAN3;         /*!< (@ 0x00003544) Port 3 Discarded Incoming VLAN Tagged Frame Count
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
+                                            *   or missing VLAN ID while VLAN verification was enabled.                   */
+        } IDISC_VLAN3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_UNTAGGED3;         /*!< (@ 0x00003548) Port 3 Discarded Incoming VLAN Untagged Frame
+                                                *                  Count Register                                             */
+
+        struct
+        {
+            __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
+                                                *   tag.                                                                      */
+        } IDISC_UNTAGGED3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_BLOCKED3;         /*!< (@ 0x0000354C) Port 3 Discarded Incoming Blocked Frame Count
+                                               *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
+                                               *   the port is configured in blocking mode.                                  */
+        } IDISC_BLOCKED3_b;
+    };
+
+    union
+    {
+        __IM uint32_t IDISC_ANY3;         /*!< (@ 0x00003550) Port 3 Discarded Any Frame Count Register (n
+                                           *                  = 0 to 3)                                                  */
+
+        struct
+        {
+            __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
+                                           *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
+        } IDISC_ANY3_b;
+    };
+    __IM uint32_t RESERVED92[363];
+
+    union
+    {
+        __IOM uint32_t MMCTL_OUT_CT;       /*!< (@ 0x00003B00) Cut-Through Register                                       */
+
+        struct
+        {
+            __IOM uint32_t CT_OVR_ENA : 3; /*!< [2..0] Per-port bit mask to enable overriding the Cut-Through
+                                            *   (CT) behavior of the output ports with CT_OVR. When set
+                                            *   to 0, the frames are transmitted CT if the CT flag of the
+                                            *   frame context is set.                                                     */
+            uint32_t              : 13;
+            __IOM uint32_t CT_OVR : 3;     /*!< [18..16] 1 bit per-port value to set the Cut Through behavior
+                                            *   of the output ports. When set to 0, all frames are sent
+                                            *   as Store & Forward (SF) frames. When set to 1, frames with
+                                            *   the CT flag set in the frame context are started as soon
+                                            *   as the frame context information is available.                            */
+            uint32_t : 13;
+        } MMCTL_OUT_CT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_CTFL_P0_3_ENA; /*!< (@ 0x00003B04) Cut-Through Frame Length Enable Register                   */
+
+        struct
+        {
+            __IOM uint32_t CTFL_P0_ENA : 8; /*!< [7..0] Port 0 bit mask of n bits, where n is the number of queues
+                                             *   per port indicating whether the CTFL is used for Cut-Through
+                                             *   (CT) frames. When set to 1, a CT frame requires a CTFL
+                                             *   entry to be written as a CT frame in the output memory.                   */
+            __IOM uint32_t CTFL_P1_ENA : 8; /*!< [15..8] Port 1 bit mask of n bits, where n is the number of
+                                             *   queues per port indicating whether the CTFL is used for
+                                             *   Cut-Through (CT) frames. When set to 1, a CT frame requires
+                                             *   a CTFL entry to be written as a CT frame in the output
+                                             *   memory.                                                                   */
+            __IOM uint32_t CTFL_P2_ENA : 8; /*!< [23..16] Port 2 bit mask of n bits, where n is the number of
+                                             *   queues per port indicating whether the CTFL is used for
+                                             *   Cut-Through (CT) frames. When set to 1, a CT frame requires
+                                             *   a CTFL entry to be written as a CT frame in the output
+                                             *   memory.                                                                   */
+            uint32_t : 8;
+        } MMCTL_CTFL_P0_3_ENA_b;
+    };
+    __IM uint32_t RESERVED93[6];
+
+    union
+    {
+        __IOM uint32_t MMCTL_YELLOW_BYTE_LENGTH_P[3]; /*!< (@ 0x00003B20) Port [0..2] Yellow Period Byte Length Register            */
+
+        struct
+        {
+            uint32_t                  : 2;
+            __IOM uint32_t YELLOW_LEN : 14; /*!< [15..2] Length in bytes of the YELLOW period for port n. Determines
+                                             *   whether a frame can be transmitted before the YELLOW period
+                                             *   expires. The value is programmed in increments of 4 bytes
+                                             *   excluding the MAC overhead (IPG, Preamble and FCS if appended)
+                                             *   of the frame.                                                             */
+            __IOM uint32_t YLEN_EN : 1;     /*!< [16..16] When set to 1, enables transmission when OUT_CT_ENA
+                                             *   is low only if the frame length is less than YELLOW_LEN.
+                                             *   If cleared, YELLOW_LEN is ignored and frames are always
+                                             *   transmitted in SF mode when OUT_CT_ENA is 0.                              */
+            uint32_t : 15;
+        } MMCTL_YELLOW_BYTE_LENGTH_P_b[3];
+    };
+    __IM uint32_t RESERVED94[5];
+
+    union
+    {
+        __IOM uint32_t MMCTL_POOL0_CTR; /*!< (@ 0x00003B40) Memory Pool Counter (n = 0 to 1)                           */
+
+        struct
+        {
+            __IOM uint32_t CELLS : 10;  /*!< [9..0] Memory pool configuration for pool n. Configures, in
+                                         *   cells, the size of each memory pool.                                      */
+            uint32_t           : 6;
+            __IM uint32_t USED : 10;    /*!< [25..16] Reports the current available number of used cells
+                                         *   for this memory pool. The used number of free cells can
+                                         *   be calculated as CELLS - USED.                                          */
+            uint32_t : 6;
+        } MMCTL_POOL0_CTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_POOL1_CTR; /*!< (@ 0x00003B44) Memory Pool Counter (n = 0 to 1)                           */
+
+        struct
+        {
+            __IOM uint32_t CELLS : 10;  /*!< [9..0] Memory pool configuration for pool n. Configures, in
+                                         *   cells, the size of each memory pool.                                      */
+            uint32_t           : 6;
+            __IM uint32_t USED : 10;    /*!< [25..16] Reports the current available number of used cells
+                                         *   for this memory pool. The used number of free cells can
+                                         *   be calculated as CELLS - USED.                                          */
+            uint32_t : 6;
+        } MMCTL_POOL1_CTR_b;
+    };
+    __IM uint32_t RESERVED95[6];
+
+    union
+    {
+        __IOM uint32_t MMCTL_POOL_GLOBAL; /*!< (@ 0x00003B60) Memory Pool Configuration Register                         */
+
+        struct
+        {
+            __IOM uint32_t CELLS : 10;    /*!< [9..0] Memory pool configuration for the global pool. Configures,
+                                           *   in cells, the size of the global shared pool.                             */
+            uint32_t           : 6;
+            __IM uint32_t USED : 10;      /*!< [25..16] Reports the current number of used cells for the global
+                                           *   shared pool. The used number of free cells can be calculated
+                                           *   as CELLS - USED.                                                        */
+            uint32_t : 6;
+        } MMCTL_POOL_GLOBAL_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMCTL_POOL_STATUS;  /*!< (@ 0x00003B64) Memory Pool Status Register                                */
+
+        struct
+        {
+            __IM uint32_t QUEUE_FULL : 8; /*!< [7..0] Per-queue pool full indication. Indicates for each queue
+                                           *   whether all the blocks in the corresponding pool and global
+                                           *   pool are allocated.                                                       */
+            uint32_t : 24;
+        } MMCTL_POOL_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_POOL_QMAP; /*!< (@ 0x00003B68) Queue MAP Register                                         */
+
+        struct
+        {
+            __IOM uint32_t Q0_MAP : 1;  /*!< [0..0] Queue 0 Memory Pool                                                */
+            uint32_t              : 2;
+            __IOM uint32_t Q0_ENA : 1;  /*!< [3..3] Queue 0 Memory Pool Enabled                                        */
+            __IOM uint32_t Q1_MAP : 1;  /*!< [4..4] Queue 1 Memory Pool                                                */
+            uint32_t              : 2;
+            __IOM uint32_t Q1_ENA : 1;  /*!< [7..7] Queue 1 Memory Pool Enabled                                        */
+            __IOM uint32_t Q2_MAP : 1;  /*!< [8..8] Queue 2 Memory Pool                                                */
+            uint32_t              : 2;
+            __IOM uint32_t Q2_ENA : 1;  /*!< [11..11] Queue 2 Memory Pool Enabled                                      */
+            __IOM uint32_t Q3_MAP : 1;  /*!< [12..12] Queue 3 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q3_ENA : 1;  /*!< [15..15] Queue 3 Memory Pool Enabled                                      */
+            __IOM uint32_t Q4_MAP : 1;  /*!< [16..16] Queue 4 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q4_ENA : 1;  /*!< [19..19] Queue 4 Memory Pool Enabled                                      */
+            __IOM uint32_t Q5_MAP : 1;  /*!< [20..20] Queue 5 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q5_ENA : 1;  /*!< [23..23] Queue 5 Memory Pool Enabled                                      */
+            __IOM uint32_t Q6_MAP : 1;  /*!< [24..24] Queue 6 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q6_ENA : 1;  /*!< [27..27] Queue 6 Memory Pool Enabled                                      */
+            __IOM uint32_t Q7_MAP : 1;  /*!< [28..28] Queue 7 Memory Pool                                              */
+            uint32_t              : 2;
+            __IOM uint32_t Q7_ENA : 1;  /*!< [31..31] Queue 7 Memory Pool Enabled                                      */
+        } MMCTL_POOL_QMAP_b;
+    };
+
+    union
+    {
+        __OM uint32_t MMCTL_QGATE;         /*!< (@ 0x00003B6C) Queue Gate State Register                                  */
+
+        struct
+        {
+            __OM uint32_t PORT_MASK : 4;   /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue
+                                            *   gate state is changed for that port as indicated by QUEUE_GATE.           */
+            uint32_t                 : 12;
+            __OM uint32_t QUEUE_GATE : 16; /*!< [31..16] 2-bit per queue indicating the action to be performed
+                                            *   on each queue of the ports indicated by PORT_MASK.                        */
+        } MMCTL_QGATE_b;
+    };
+
+    union
+    {
+        __OM uint32_t MMCTL_QTRIG;        /*!< (@ 0x00003B70) Queue Trigger Register                                     */
+
+        struct
+        {
+            __OM uint32_t PORT_MASK : 4;  /*!< [3..0] Per-port bit mask. When set to 1 for a port, a frame
+                                           *   is triggered from the closed queues indicated by QUEUE_TRIG.              */
+            uint32_t                 : 12;
+            __OM uint32_t QUEUE_TRIG : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
+                                           *   is to be transmitted from the ports indicated by PORT_MASK.
+                                           *   When set to 1, a single frame is transmitted per indicated
+                                           *   port in PORT_MASK among the queues indicated by QUEUE_TRIG.               */
+            uint32_t : 8;
+        } MMCTL_QTRIG_b;
+    };
+
+    union
+    {
+        __OM uint32_t MMCTL_QFLUSH;       /*!< (@ 0x00003B74) Flush Event Select Register                                */
+
+        struct
+        {
+            __OM uint32_t PORT_MASK : 4;  /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue
+                                           *   flush status is changed for that port for the queues indicated
+                                           *   in QUEUE_MASK.                                                            */
+            uint32_t                 : 12;
+            __OM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1 bit per queue indicating for which queues of the
+                                           *   ports indicated by PORT_MASK the flush state is changed
+                                           *   as indicated in ACTION.                                                   */
+            __OM uint32_t ACTION : 2;     /*!< [25..24] Selects the flush state for the queues indicated by
+                                           *   QUEUE_MASK in the ports indicated by PORT_MASK. Possible
+                                           *   actions are:                                                              */
+            uint32_t : 6;
+        } MMCTL_QFLUSH_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMCTL_QCLOSED_STATUS_P0_3; /*!< (@ 0x00003B78) Queue Closed Status Register                               */
+
+        struct
+        {
+            __IM uint32_t P0_STATUS : 8;         /*!< [7..0] Per-queue closed status of Port 0 (1-bit per queue).
+                                                  *   A 0 indicates that the queue is open (enabled), and a 1
+                                                  *   indicates that the queue is closed (disabled).                            */
+            __IM uint32_t P1_STATUS : 8;         /*!< [15..8] Per-queue closed status of Port 1 (1-bit per queue).
+                                                  *   A 0 indicates that the queue is open (enabled), and a 1
+                                                  *   indicates that the queue is closed (disabled).                            */
+            __IM uint32_t P2_STATUS : 8;         /*!< [23..16] Per-queue closed status of Port 2 (1-bit per queue).
+                                                  *   A 0 indicates that the queue is open (enabled), and a 1
+                                                  *   indicates that the queue is closed (disabled).                            */
+            uint32_t : 8;
+        } MMCTL_QCLOSED_STATUS_P0_3_b;
+    };
+    __IM uint32_t RESERVED96;
+
+    union
+    {
+        __IOM uint32_t MMCTL_1FRAME_MODE_P[3]; /*!< (@ 0x00003B80) Port [0..2] 1-Frame Mode Configuration Register            */
+
+        struct
+        {
+            __IOM uint32_t Q_1FRAME_ENA : 8;   /*!< [7..0] 1 bit per queue. Setting a bit to 1 enables the 1-frame
+                                                *   mode for that queue for port n. In this mode, only one
+                                                *   frame is allowed in the queue. If a new frame is received,
+                                                *   the old frame is discarded.                                               */
+            uint32_t                 : 8;
+            __IOM uint32_t Q_BUF_ENA : 8;      /*!< [23..16] 1 bit per queue. Setting a bit to 1 enables the buffer
+                                                *   mode behavior for that queue for port n. This mode requires
+                                                *   also that Q_1FRAME_ENA is set to 1.                                       */
+            uint32_t : 8;
+        } MMCTL_1FRAME_MODE_P_b[3];
+    };
+    __IM uint32_t RESERVED97[5];
+
+    union
+    {
+        __IM uint32_t MMCTL_P0_3_QUEUE_STATUS; /*!< (@ 0x00003BA0) Queue Status Indicator                                     */
+
+        struct
+        {
+            __IM uint32_t P0_Q_STATUS : 8;     /*!< [7..0] Port 0 Per-Queue Bit Indication                                    */
+            __IM uint32_t P1_Q_STATUS : 8;     /*!< [15..8] Port 1 Per-Queue Bit Indication                                   */
+            __IM uint32_t P2_Q_STATUS : 8;     /*!< [23..16] Port 2 Per-Queue Bit Indication                                  */
+            uint32_t                  : 8;
+        } MMCTL_P0_3_QUEUE_STATUS_b;
+    };
+    __IM uint32_t RESERVED98;
+
+    union
+    {
+        __IM uint32_t MMCTL_P0_3_FLUSH_STATUS; /*!< (@ 0x00003BA8) Queue Flush Status Indicator                               */
+
+        struct
+        {
+            __IM uint32_t P0_F_STATUS : 8;     /*!< [7..0] Port 0 per-Queue Bit Indication on whether the queue
+                                                *   is flushing frames (read 1) or not (read 0).                              */
+            __IM uint32_t P1_F_STATUS : 8;     /*!< [15..8] Port 1 per-Queue Bit Indication on whether the queue
+                                                *   is flushing frames (read 1) or not (read 0).                              */
+            __IM uint32_t P2_F_STATUS : 8;     /*!< [23..16] Port 2 per-Queue Bit Indication on whether the queue
+                                                *   is flushing frames (read 1) or not (read 0).                              */
+            uint32_t : 8;
+        } MMCTL_P0_3_FLUSH_STATUS_b;
+    };
+    __IM uint32_t RESERVED99;
+
+    union
+    {
+        __IOM uint32_t MMCTL_DLY_QTRIGGER_CTRL; /*!< (@ 0x00003BB0) Delayed Queue Trigger Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t DELAY_TIME : 30;     /*!< [29..0] 30-bit time in nanoseconds indicates the time after
+                                                 *   the trigger request from the pattern matchers to generate
+                                                 *   the event.                                                                */
+            __IOM uint32_t TIMER_SEL : 1;       /*!< [30..30] Select the source timer to use for calculating the
+                                                 *   time.                                                                     */
+            uint32_t : 1;
+        } MMCTL_DLY_QTRIGGER_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_PREEMPT_QUEUES;      /*!< (@ 0x00003BB4) Preemptable Queues Configures Register                     */
+
+        struct
+        {
+            __IOM uint32_t PREEMPT_ENA : 8;       /*!< [7..0] Per-queue enable bit to configure which queues are used
+                                                   *   for preemptable traffic. Set to 1 the corresponding bit
+                                                   *   to configure a queue to be preemptable.                                   */
+            __IOM uint32_t PREEMPT_ON_QCLOSE : 8; /*!< [15..8] Per-queue configuration bit to enable preempting a frame
+                                                   *   when the queue goes from OPEN to CLOSED. When the corresponding
+                                                   *   bit is set to 1 and the queue is configured as preemptable
+                                                   *   in PREEMPT_ENA, a queue close event causes the current
+                                                   *   frame to be preempted, if preemption is operational.                      */
+            uint32_t : 16;
+        } MMCTL_PREEMPT_QUEUES_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_HOLD_CONTROL;         /*!< (@ 0x00003BB8) Request Preemption Register                                */
+
+        struct
+        {
+            __IOM uint32_t Q_HOLD_REQ_FORCE : 3;   /*!< [2..0] A per-port bit that forces a preempt request using MM_CTL.request
+                                                    *   (hold_req). When this bit is set to 1, it overrides other
+                                                    *   sources of hold request, including the TDMA controller.                   */
+            uint32_t                          : 13;
+            __IOM uint32_t Q_HOLD_REQ_RELEASE : 3; /*!< [18..16] A per-port bit that forces a release of preemption
+                                                    *   request using MM_CTL.request (hold_req). When this bit
+                                                    *   is set to 1, it overrides other sources of hold request,
+                                                    *   including the TDMA controller and Q_HOLD_REQ_FORCE[2:0].                  */
+            uint32_t : 13;
+        } MMCTL_HOLD_CONTROL_b;
+    };
+
+    union
+    {
+        __IM uint32_t MMCTL_PREEMPT_STATUS;   /*!< (@ 0x00003BBC) Preemption State Register                                  */
+
+        struct
+        {
+            __IM uint32_t PREEMPT_STATE : 3;  /*!< [2..0] A per-port bit that indicates if a port is in a preempted
+                                               *   state. This is a real-time indication meant for debugging.                */
+            uint32_t                     : 13;
+            __IM uint32_t HOLD_REQ_STATE : 3; /*!< [18..16] A per-port bit that indicates if a port is preempted
+                                               *   using MM_CTL.request (hold_req). This is a real-time indication
+                                               *   meant for debugging.                                                      */
+            uint32_t : 13;
+        } MMCTL_PREEMPT_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMCTL_CQF_CTRL_P[4];  /*!< (@ 0x00003BC0) Port [0..3] Cyclic Queuing and Forwarding Control
+                                              *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t PRIO_ENABLE0 : 8; /*!< [7..0] A per-queue enable to select which ingress priorities
+                                              *   are queued in the two CQF queues.                                         */
+            __IOM uint32_t QUEUE_SEL0 : 3;   /*!< [10..8] Select which two physical queues are used for CQF. The
+                                              *   queues used are QUEUE_SEL0 and QUEUE_SEL0 + 1. Frames are
+                                              *   written into QUEUE_SEL0 when the gate control selected
+                                              *   with GATE_SEL0 is 0, and into QUEUE_SEL0 + 1 when the gate
+                                              *   control is 1.                                                             */
+            __IOM uint32_t GATE_SEL0 : 3;    /*!< [13..11] Select which gate control signal is used for selecting
+                                              *   the output queue (these signals are the same as the ETHSW_TDMAOUT
+                                              *   pins).                                                                    */
+            __IOM uint32_t USE_SOP0 : 1;     /*!< [14..14] When set to 1, the CFQ queue is determined when the
+                                              *   SOP is received at the frame writer in the memory controller.
+                                              *   When set to 0, the queue is determined when the EOP is
+                                              *   received at the frame writer.                                             */
+            __IOM uint32_t REF_SEL0 : 1;     /*!< [15..15] Select whether the gate control signal used for the
+                                              *   CQF group is based on the egress port when set to 0, or
+                                              *   the ingress port when set to 1.                                           */
+            uint32_t : 16;
+        } MMCTL_CQF_CTRL_P_b[4];
+    };
+    __IM uint32_t RESERVED100[4];
+
+    union
+    {
+        __IM uint32_t MMCTL_P0_3_QCLOSED_NONEMPTY; /*!< (@ 0x00003BE0) Port Queue Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t P0_Q_STATUS : 8;         /*!< [7..0] Port 0 per-queue bit indication on whether the queue
+                                                    *   transitioned from open to closed state while frames were
+                                                    *   still queued.                                                             */
+            __IM uint32_t P1_Q_STATUS : 8;         /*!< [15..8] Port 1 per-queue bit indication on whether the queue
+                                                    *   transitioned from open to closed state while frames were
+                                                    *   still queued.                                                             */
+            __IM uint32_t P2_Q_STATUS : 8;         /*!< [23..16] Port 2 per-queue bit indication on whether the queue
+                                                    *   transitioned from open to closed state while frames were
+                                                    *   still queued.                                                             */
+            __IM uint32_t P3_Q_STATUS : 8;         /*!< [31..24] Port 3 per-queue bit indication on whether the queue
+                                                    *   transitioned from open to closed state while frames were
+                                                    *   still queued.                                                             */
+        } MMCTL_P0_3_QCLOSED_NONEMPTY_b;
+    };
+    __IM uint32_t RESERVED101;
+
+    union
+    {
+        __IOM uint32_t MMCTL_PREEMPT_EXTRA;   /*!< (@ 0x00003BE8) Frame Preemption Extra Configuration Register              */
+
+        struct
+        {
+            __IOM uint32_t MIN_PFRM_ADJ : 4;  /*!< [3..0] Adjust the minimum mPacket length, in increments of 4
+                                               *   bytes.                                                                    */
+            __IOM uint32_t LAST_PFRM_ADJ : 4; /*!< [7..4] Adjust the preemptable threshold when reaching the end
+                                               *   of the frame, in increments of 4 bytes. Incrementing this
+                                               *   value increments the length of the last mPacket.                          */
+            uint32_t : 24;
+        } MMCTL_PREEMPT_EXTRA_b;
+    };
+    __IM uint32_t RESERVED102[5];
+
+    union
+    {
+        __IOM uint32_t DLR_CONTROL;             /*!< (@ 0x00003C00) DLR Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t ENABLE : 1;          /*!< [0..0] Enable DLR extension module. When set, the DLR module
+                                                 *   becomes active. When DLR is enabled, the LOOP_FILTER_ENA
+                                                 *   must also be enabled for proper DLR operation.                            */
+            __IOM uint32_t AUTOFLUSH : 1;       /*!< [1..1] Enable automatic flushing of unicast entries in address
+                                                 *   table if ring reconfiguration occurs (see also DLR interrupt
+                                                 *   IRQ_flush_macaddr_ena in DLR_IRQ_CONTROL).                                */
+            __IOM uint32_t LOOP_FILTER_ENA : 1; /*!< [2..2] Enable the loop filter function. When set to 1, the ingress
+                                                 *   loop filter is enabled. This can be enabled regardless
+                                                 *   of the DLR ENABLE state, allowing the loop filter function
+                                                 *   to operate when DLR is not used.                                          */
+            uint32_t                    : 1;
+            __IOM uint32_t IGNORE_INVTM : 1;    /*!< [4..4] Enable ignore beacon frames with invalid timeout timer.
+                                                 *   When enabled (set to 1) frames with timeout timer value
+                                                 *   not within a range of 200 microseconds to 500 milliseconds
+                                                 *   are ignored and parameters are not locally stored or considered
+                                                 *   for state transitions. The invalid timeout timer value
+                                                 *   is always stored within the DLR_INV_TMOUT register irrespective
+                                                 *   of the value of this bit. Ignored frames are forwarded
+                                                 *   normally.                                                                 */
+            uint32_t               : 3;
+            __IOM uint32_t US_TIME : 12;        /*!< [19..8] Number of clock cycles required for 1 microsecond for
+                                                 *   the switch operating clock. This LSI operates at 200 MHz,
+                                                 *   therefore this register must be set to 0xC8. The value
+                                                 *   after reset must be changed.                                              */
+            uint32_t : 12;
+        } DLR_CONTROL_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_STATUS;             /*!< (@ 0x00003C04) DLR Status Register                                        */
+
+        struct
+        {
+            __IM uint32_t LastBcnRcvPort : 2; /*!< [1..0] Last Beacon Receive Port                                           */
+            uint32_t                     : 6;
+            __IM uint32_t NODE_STATE     : 8; /*!< [15..8] Local Node Current State                                          */
+            __IM uint32_t LINK_STATUS    : 2; /*!< [17..16] Link Status                                                      */
+            uint32_t                     : 6;
+            __IM uint32_t TOPOLOGY       : 8; /*!< [31..24] Current Network Topology                                         */
+        } DLR_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_ETH_TYP;          /*!< (@ 0x00003C08) DLR Ethernet Type Register                                 */
+
+        struct
+        {
+            __IOM uint32_t DLR_ETH_TYP : 16; /*!< [15..0] Ethernet type to compare for DLR frame detection (initial
+                                              *   value is 0x80E1)                                                          */
+            uint32_t : 16;
+        } DLR_ETH_TYP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_IRQ_CONTROL;               /*!< (@ 0x00003C0C) DLR Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t IRQ_state_chng_ena    : 1; /*!< [0..0] Enable Interrupt for State Change                                  */
+            __IOM uint32_t IRQ_flush_macaddr_ena : 1; /*!< [1..1] Enable Flush Local MAC Address Table Interrupt.                    */
+            __IOM uint32_t IRQ_stop_nbchk0_ena   : 1; /*!< [2..2] Enable Stop Request Neighbor Check Timeout Timer Interrupt
+                                                       *   for Port 0.                                                               */
+            __IOM uint32_t IRQ_stop_nbchk1_ena : 1;   /*!< [3..3] Enable Stop Request Neighbor Check Timeout Timer Interrupt
+                                                       *   for Port 1.                                                               */
+            __IOM uint32_t IRQ_bec_tmr0_exp_ena : 1;  /*!< [4..4] IRQ_bec_tmr0_exp_ena                                               */
+            __IOM uint32_t IRQ_bec_tmr1_exp_ena : 1;  /*!< [5..5] Enable Interrupt on Beacon Timeout Timer Expire for Port
+                                                       *   1.                                                                        */
+            __IOM uint32_t IRQ_supr_chng_ena  : 1;    /*!< [6..6] Enable Interrupt on Ring Supervisor Change.                        */
+            __IOM uint32_t IRQ_link_chng0_ena : 1;    /*!< [7..7] Enable Link Status Change Interrupt Event for Port 0.              */
+            __IOM uint32_t IRQ_link_chng1_ena : 1;    /*!< [8..8] Enable Link Status Change Interrupt Event for Port 1.              */
+            __IOM uint32_t IRQ_sup_ignord_ena : 1;    /*!< [9..9] Enable interrupt on beacon frame detection from a supervisor
+                                                       *   with lower precedence than the current ring supervisor
+                                                       *   or lower numeric value for MAC address when precedence
+                                                       *   is same.                                                                  */
+            __IOM uint32_t IRQ_ip_addr_chng_ena : 1;  /*!< [10..10] Enable interrupt on IP address change detection within
+                                                       *   beacon frame from ring supervisor.                                        */
+            __IOM uint32_t IRQ_invalid_tmr_ena : 1;   /*!< [11..11] Enable interrupt on invalid range for beacon timeout
+                                                       *   timer value detection.                                                    */
+            __IOM uint32_t IRQ_bec_rcv0_ena : 1;      /*!< [12..12] Enable interrupt on beacon frame detection on port
+                                                       *   0.                                                                        */
+            __IOM uint32_t IRQ_bec_rcv1_ena : 1;      /*!< [13..13] Enable interrupt on beacon frame detection on port
+                                                       *   1.                                                                        */
+            __IOM uint32_t IRQ_frm_dscrd0 : 1;        /*!< [14..14] Enable interrupt on frame discard due to source address
+                                                       *   match with the local address on port 0.                                   */
+            __IOM uint32_t IRQ_frm_dscrd1 : 1;        /*!< [15..15] Enable Interrupt on Frame discard due to source address
+                                                       *   match with the local address on port 1.                                   */
+            uint32_t                  : 13;
+            __IOM uint32_t low_int_en : 1;            /*!< [29..29] Enable active-low interrupt. Asserted to use active-low
+                                                       *   interrupt signal instead of active-high interrupt signal.                 */
+            __OM uint32_t atomic_OR : 1;              /*!< [30..30] When set during a register-write, the enable bits are
+                                                       *   ORed into the current setting of the register. By writing
+                                                       *   this bit at the same time, only the target bit can be set
+                                                       *   to 1.                                                                     */
+            __OM uint32_t atomic_AND : 1;             /*!< [31..31] When set during a register-write, the enable bits are
+                                                       *   ANDed with the current setting of the register. By writing
+                                                       *   this bit at the same time, only the target bit can be set
+                                                       *   to 0.                                                                     */
+        } DLR_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_IRQ_STAT_ACK;                /*!< (@ 0x00003C10) DLR Interrupt Status/ACK Register                          */
+
+        struct
+        {
+            __IOM uint32_t state_chng_IRQ_pending : 1;  /*!< [0..0] Latched State Change Event                                         */
+            __IOM uint32_t flush_IRQ_pending      : 1;  /*!< [1..1] Latched Flush Event for MAC Address Learning Table                 */
+            __IOM uint32_t nbchk0_IRQ_pending     : 1;  /*!< [2..2] Stop Request Event for Neighbor Check Timeout Timer for
+                                                         *   Port 0                                                                    */
+            __IOM uint32_t nbchk1_IRQ_pending : 1;      /*!< [3..3] Stop Request Event for Neighbor Check Timeout Timer for
+                                                         *   Port 1                                                                    */
+            __IOM uint32_t bec_tmr0_IRQ_pending   : 1;  /*!< [4..4] Beacon Timeout Timer Expire Event for Port 0                       */
+            __IOM uint32_t bec_tmr1_IRQ_pending   : 1;  /*!< [5..5] Beacon Timeout Timer Expire Event for Port 1                       */
+            __IOM uint32_t supr_chng_IRQ_pending  : 1;  /*!< [6..6] Latched Supervisor Change Event                                    */
+            __IOM uint32_t Link0_IRQ_pending      : 1;  /*!< [7..7] Latched Link Status Change Event for Port 0                        */
+            __IOM uint32_t Link1_IRQ_pending      : 1;  /*!< [8..8] Latched Link Status Change Event for Port 1                        */
+            __IOM uint32_t sup_ignord_IRQ_pending : 1;  /*!< [9..9] Latched Event for Beacon Frame Detection from Ignored
+                                                         *   Supervisor                                                                */
+            __IOM uint32_t ip_chng_IRQ_pending     : 1; /*!< [10..10] Latched IP Address Change Event                                  */
+            __IOM uint32_t invalid_tmr_IRQ_pending : 1; /*!< [11..11] Latched Event on Invalid Beacon Timeout Timer Value
+                                                         *  Detection Within Beacon Frame on Port 0 or Port 1                         */
+            __IOM uint32_t bec_rcv0_IRQ_pending   : 1;  /*!< [12..12] Latched Event on Beacon Frame Detection on Port 0                */
+            __IOM uint32_t bec_rcv1_IRQ_pending   : 1;  /*!< [13..13] Latched Event on Beacon Frame Detection on Port 1                */
+            __IOM uint32_t frm_dscrd0_IRQ_pending : 1;  /*!< [14..14] Latched Event on Frame Discard Due to Source Address
+                                                         *   Match with the Local Address on Port 0 (Loop Filter)                      */
+            __IOM uint32_t frm_dscrd1_IRQ_pending : 1;  /*!< [15..15] Latched Event on Frame Discard Due to Source Address
+                                                         *   Match with the Local Address on Port 1 (Loop Filter)                      */
+            uint32_t : 16;
+        } DLR_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_LOC_MAClo;    /*!< (@ 0x00003C14) DLR Local MAC Address Low Register                         */
+
+        struct
+        {
+            __IOM uint32_t LOC_MAC : 32; /*!< [31..0] First 4 octets of the Local MAC address for loop filter           */
+        } DLR_LOC_MAClo_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_LOC_MAChi;    /*!< (@ 0x00003C18) DLR Local MAC Address High Register                        */
+
+        struct
+        {
+            __IOM uint32_t LOC_MAC : 16; /*!< [15..0] Last 2 octets of local MAC address for loop filter                */
+            uint32_t               : 16;
+        } DLR_LOC_MAChi_b;
+    };
+    __IM uint32_t RESERVED103;
+
+    union
+    {
+        __IM uint32_t DLR_SUPR_MAClo;    /*!< (@ 0x00003C20) DLR Supervisor MAC Address Low Register                    */
+
+        struct
+        {
+            __IM uint32_t SUPR_MAC : 32; /*!< [31..0] First 4 octets of the active ring supervisor of the
+                                          *   MAC address extracted from the Source Address field of
+                                          *   the beacon frame.                                                         */
+        } DLR_SUPR_MAClo_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_SUPR_MAChi;    /*!< (@ 0x00003C24) DLR Supervisor MAC Address High Register                   */
+
+        struct
+        {
+            __IM uint32_t SUPR_MAC : 16; /*!< [15..0] Last 2 octets of the active ring supervisor of the MAC
+                                          *   address extracted from the Source Address field of the
+                                          *   beacon frame.                                                             */
+            __IM uint32_t PRECE : 8;     /*!< [23..16] Precedence value of the ring supervisor extracted from
+                                          *   the Supervisor precedence field of the beacon frame.                      */
+            uint32_t : 8;
+        } DLR_SUPR_MAChi_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_STATE_VLAN;     /*!< (@ 0x00003C28) DLR Ring Status/VLAN Register                              */
+
+        struct
+        {
+            __IM uint32_t RINGSTAT : 8;   /*!< [7..0] DLR ring state extracted from the Ring State field of
+                                           *   the beacon frame.                                                         */
+            __IM uint32_t VLANVALID : 1;  /*!< [8..8] VLAN Valid                                                         */
+            uint32_t                : 7;
+            __IM uint32_t VLANINFO  : 16; /*!< [31..16] IEEE 802.1Q VLAN Tag control field extracted from the
+                                           *   VLAN info field of the beacon frame.                                      */
+        } DLR_STATE_VLAN_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_BEC_TMOUT;      /*!< (@ 0x00003C2C) DLR Beacon Timeout Register                                */
+
+        struct
+        {
+            __IM uint32_t BEC_TMOUT : 32; /*!< [31..0] Beacon timeout timer value extracted from the Beacon
+                                           *   Timeout in microseconds field of the beacon frame.                        */
+        } DLR_BEC_TMOUT_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_BEC_INTRVL;      /*!< (@ 0x00003C30) DLR Beacon Interval Register                               */
+
+        struct
+        {
+            __IM uint32_t BEC_INTRVL : 32; /*!< [31..0] Beacon interval extracted from the Beacon Interval field
+                                            *   of the beacon frame                                                       */
+        } DLR_BEC_INTRVL_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_SUPR_IPADR;      /*!< (@ 0x00003C34) DLR Supervisor IP Address Register                         */
+
+        struct
+        {
+            __IM uint32_t SUPR_IPADR : 32; /*!< [31..0] IP address of the ring supervisor extracted from the
+                                            *   Source IP address field of the beacon frame. A value of
+                                            *   0x0 can be received when supervisor has no IP address.                    */
+        } DLR_SUPR_IPADR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_ETH_STYP_VER; /*!< (@ 0x00003C38) DLR Sub Type/Protocol Version Register                     */
+
+        struct
+        {
+            __IM uint32_t SUBTYPE : 8;  /*!< [7..0] DLR Ring Ether Sub Type extracted from the Ring Sub Type
+                                         *   field of the beacon frame.                                                */
+            __IM uint32_t PROTVER : 8;  /*!< [15..8] DLR Ring Protocol Version extracted from the Ring Protocol
+                                         *   Version field of the beacon frame.                                        */
+            __IM uint32_t SPORT : 8;    /*!< [23..16] Source port extracted from the Source Port field of
+                                         *   the beacon frame.                                                         */
+            uint32_t : 8;
+        } DLR_ETH_STYP_VER_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_INV_TMOUT;      /*!< (@ 0x00003C3C) DLR Beacon Timeout Timer Register                          */
+
+        struct
+        {
+            __IM uint32_t INV_TMOUT : 32; /*!< [31..0] Last out of range Beacon timeout timer value extracted
+                                           *   from beacon frame on any of the port.                                     */
+        } DLR_INV_TMOUT_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_SEQ_ID;      /*!< (@ 0x00003C40) DLR Sequence ID Register                                   */
+
+        struct
+        {
+            __IM uint32_t SEQ_ID : 32; /*!< [31..0] Sequence ID of the last beacon frame extracted from
+                                        *   the Sequence ID field of the beacon frame on port 0 or
+                                        *   port 1. Sequence ID of the ignored frames is not stored.                  */
+        } DLR_SEQ_ID_b;
+    };
+    __IM uint32_t RESERVED104[5];
+
+    union
+    {
+        __IOM uint32_t DLR_DSTlo;        /*!< (@ 0x00003C58) DLR Beacon Destination Address Low Register                */
+
+        struct
+        {
+            __IOM uint32_t DLR_DST : 32; /*!< [31..0] First 4 octets of the beacon frame destination multicast
+                                          *   address (01-21-6C-00-00-01).                                              */
+        } DLR_DSTlo_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DLR_DSThi;        /*!< (@ 0x00003C5C) DLR Beacon Destination Address High Register               */
+
+        struct
+        {
+            __IOM uint32_t DLR_DST : 16; /*!< [15..0] Last 2 octets of the beacon frame destination multicast
+                                          *   address (01-21-6C-00-00-01).                                              */
+            uint32_t : 16;
+        } DLR_DSThi_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_RX_STAT0;      /*!< (@ 0x00003C60) DLR Received Frame Statistic Register 0                    */
+
+        struct
+        {
+            __IM uint32_t RX_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 0                        */
+        } DLR_RX_STAT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_RX_ERR_STAT0;      /*!< (@ 0x00003C64) DLR Received Frame Error Statistic Register 0              */
+
+        struct
+        {
+            __IM uint32_t RX_ERR_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port
+                                              *   0                                                                         */
+        } DLR_RX_ERR_STAT0_b;
+    };
+    __IM uint32_t RESERVED105;
+
+    union
+    {
+        __IOM uint32_t DLR_RX_LF_STAT0;     /*!< (@ 0x00003C6C) DLR Received Frame Loop Filter Statistic Register
+                                             *                  0                                                          */
+
+        struct
+        {
+            __IOM uint32_t RX_LF_STAT0 : 8; /*!< [7..0] Number of discarded frames in port 0 due to loop filtering
+                                             *   when LOOP_FILTER_ENA is set to 1. Saturates at 255.                       */
+            uint32_t : 24;
+        } DLR_RX_LF_STAT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_RX_STAT1;      /*!< (@ 0x00003C70) DLR Received Frame Statistic Register 1                    */
+
+        struct
+        {
+            __IM uint32_t RX_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 1                        */
+        } DLR_RX_STAT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLR_RX_ERR_STAT1;      /*!< (@ 0x00003C74) DLR Received Frame Error Statistic Register 1              */
+
+        struct
+        {
+            __IM uint32_t RX_ERR_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port
+                                              *   1                                                                         */
+        } DLR_RX_ERR_STAT1_b;
+    };
+    __IM uint32_t RESERVED106;
+
+    union
+    {
+        __IOM uint32_t DLR_RX_LF_STAT1;     /*!< (@ 0x00003C7C) DLR Received Frame Loop Filter Statistic Register
+                                             *                  1                                                          */
+
+        struct
+        {
+            __IOM uint32_t RX_LF_STAT1 : 8; /*!< [7..0] Number of discarded frames in port 1 due to loop filtering
+                                             *   when LOOP_FILTER_ENA is set to 1. Saturates at 255.                       */
+            uint32_t : 24;
+        } DLR_RX_LF_STAT1_b;
+    };
+    __IM uint32_t RESERVED107[32];
+
+    union
+    {
+        __IOM uint32_t PRP_CONFIG;               /*!< (@ 0x00003D00) PRP Configuration Register                                 */
+
+        struct
+        {
+            __IOM uint32_t PRP_ENA       : 1;    /*!< [0..0] Enable PRP Operation                                               */
+            __IOM uint32_t RX_DUP_ACCEPT : 1;    /*!< [1..1] Enable Duplicate Accept Mode of Operation at Receive               */
+            __IOM uint32_t RX_REMOVE_RCT : 1;    /*!< [2..2] Allow PRP Port RX to Remove the RCT                                */
+            __IOM uint32_t TX_RCT_MODE   : 2;    /*!< [4..3] Control Appending the RCT to Transmitted Frames on the
+                                                  *   Redundant Ports                                                           */
+            __IOM uint32_t TX_RCT_BROADCAST : 1; /*!< [5..5] Should be 1 normally.                                              */
+            __IOM uint32_t TX_RCT_MULTICAST : 1; /*!< [6..6] Should be 1 normally.                                              */
+            __IOM uint32_t TX_RCT_UNKNOWN   : 1; /*!< [7..7] Should be 1 normally.                                              */
+            __IOM uint32_t TX_RCT_1588      : 1; /*!< [8..8] Setting this bit affects IEEE 1588 frames that are forwarded
+                                                  *   through the switch (for example, when used as RedBox) to
+                                                  *   both PRP_GROUP ports. Locally generated IEEE 1588 frames
+                                                  *   (peer-delay request/response) are not affected by this
+                                                  *   setting.                                                                  */
+            __IOM uint32_t RCT_LEN_CHK_DIS : 1;  /*!< [9..9] When set to 1, disables the RCT length field checking
+                                                  *   against the actual frame length.                                          */
+            uint32_t                   : 6;
+            __IOM uint32_t PRP_AGE_ENA : 1;      /*!< [16..16] Enable History Memory Aging Timer                                */
+            uint32_t                   : 15;
+        } PRP_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_GROUP;         /*!< (@ 0x00003D04) PRP Port Group Register                                    */
+
+        struct
+        {
+            __IOM uint32_t PRP_GROUP : 3; /*!< [2..0] Defines which two ports should be treated as redundant
+                                           *   ports for PRP.                                                            */
+            uint32_t                 : 13;
+            __IOM uint32_t LANB_MASK : 3; /*!< [18..16] Defines which of the ports is considered the LAN B
+                                           *   port.                                                                     */
+            uint32_t : 13;
+        } PRP_GROUP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_SUFFIX;          /*!< (@ 0x00003D08) PRP RCT Suffix                                             */
+
+        struct
+        {
+            __IOM uint32_t PRP_SUFFIX : 16; /*!< [15..0] The Redundancy Control Trailer (RCT) suffix (initial
+                                             *   value is 0x88FB)                                                          */
+            uint32_t : 16;
+        } PRP_SUFFIX_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_LANID;      /*!< (@ 0x00003D0C) PRP LAN Identifier                                         */
+
+        struct
+        {
+            __IOM uint32_t LANAID : 4; /*!< [3..0] LAN A Identifier                                                   */
+            __IOM uint32_t LANBID : 4; /*!< [7..4] LAN B Identifier                                                   */
+            uint32_t              : 24;
+        } PRP_LANID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DUP_W;          /*!< (@ 0x00003D10) PRP Max Duplicate Detection Window Size                    */
+
+        struct
+        {
+            __IOM uint32_t DUP_W : 8;  /*!< [7..0] Maximum Duplicate Detect Window Size                               */
+            uint32_t             : 24;
+        } DUP_W_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_AGETIME;          /*!< (@ 0x00003D14) PRP Aging Time Define Register                             */
+
+        struct
+        {
+            __IOM uint32_t PRP_AGETIME : 24; /*!< [23..0] Timeout in steps of 32 switch operating clock cycles
+                                              *   to control aging of duplicate history data.                               */
+            uint32_t : 8;
+        } PRP_AGETIME_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_IRQ_CONTROL;    /*!< (@ 0x00003D18) PRP Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Enable Interrupt for Memory Error Indications.                     */
+            __IOM uint32_t WRONGLAN   : 1; /*!< [1..1] Enable interrupt for frames received at a redundant port
+                                            *   with an invalid LAN identifier in its redundancy trailer.                 */
+            __IOM uint32_t OUTOFSEQ : 1;   /*!< [2..2] Enable interrupt for frames received and accepted but
+                                            *   have an unexpected sequence number.                                       */
+            __IOM uint32_t SEQMISSING : 1; /*!< [3..3] Enable interrupt for frames received and accepted that
+                                            *   caused the history to skip a sequence number that was never
+                                            *   received (for example, a missing sequence number is being
+                                            *   ignored and is now treated as a candidate for dropping).                  */
+            uint32_t : 28;
+        } PRP_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRP_IRQ_STAT_ACK;   /*!< (@ 0x00003D1C) PRP Interrupt Status/ACK Register                          */
+
+        struct
+        {
+            __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Interrupt Pending Indication                                       */
+            __IOM uint32_t WRONGLAN   : 1; /*!< [1..1] This bit functions the same as MEMTOOLATE bit.                     */
+            __IOM uint32_t OUTOFSEQ   : 1; /*!< [2..2] This bit functions the same as MEMTOOLATE bit.                     */
+            __IOM uint32_t SEQMISSING : 1; /*!< [3..3] This bit functions the same as MEMTOOLATE bit.                     */
+            uint32_t                  : 28;
+        } PRP_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RM_ADDR_CTRL;           /*!< (@ 0x00003D20) PRP History Memory Transactions Control Register           */
+
+        struct
+        {
+            __IOM uint32_t address       : 12; /*!< [11..0] Memory Address for Read and Write Transactions                    */
+            uint32_t                     : 10;
+            __IOM uint32_t CLEAR_DYNAMIC : 1;  /*!< [22..22] When set to 1, scan the complete table for valid dynamic
+                                                *   history entries and deletes them (writes entry with all
+                                                *   0s).                                                                      */
+            __IOM uint32_t CLEAR_MEMORY : 1;   /*!< [23..23] When set to 1, write all memory locations with 0.                */
+            uint32_t                    : 1;
+            __IOM uint32_t WRITE        : 1;   /*!< [25..25] When set to 1, perform a Single Write Transaction.               */
+            __IOM uint32_t READ         : 1;   /*!< [26..26] When set to 1, perform Single Read Transaction.                  */
+            uint32_t                    : 2;
+            __IOM uint32_t CLEAR        : 1;   /*!< [29..29] When set to 1, write all 0s to the entry selected by
+                                                *   the given address.                                                        */
+            uint32_t           : 1;
+            __IM uint32_t BUSY : 1;            /*!< [31..31] Transaction Busy Indication                                      */
+        } RM_ADDR_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RM_DATA;          /*!< (@ 0x00003D24) PRP Memory Data Register                                   */
+
+        struct
+        {
+            __IOM uint32_t RM_DATA : 32; /*!< [31..0] Memory data register for read/write transactions controlled
+                                          *   by RM_ADDR_CTRL.                                                          */
+        } RM_DATA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RM_DATA_HI;          /*!< (@ 0x00003D28) PRP Memory Data Higher Register                            */
+
+        struct
+        {
+            __IOM uint32_t RM_DATA_HI : 32; /*!< [31..0] A Second Data Register                                            */
+        } RM_DATA_HI_b;
+    };
+
+    union
+    {
+        __IM uint32_t RM_STATUS;           /*!< (@ 0x00003D2C) PRP Memory Controller Status Indication                    */
+
+        struct
+        {
+            __IM uint32_t ageaddress : 12; /*!< [11..0] Address of an entry which the aging process inspects
+                                            *   when the aging timer expires next time.                                   */
+            uint32_t : 20;
+        } RM_STATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TxSeqTooLate;         /*!< (@ 0x00003D30) PRP Frame Transmission Retrieval of Failed Sequence        */
+
+        struct
+        {
+            __IOM uint32_t TxSeqTooLate : 4; /*!< [3..0] Retrieval of a Sequence Number Failed                              */
+            uint32_t                    : 28;
+        } TxSeqTooLate_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntErrWrongLanA;          /*!< (@ 0x00003D34) PRP Wrong ID LAN-A Count Register                          */
+
+        struct
+        {
+            __IM uint32_t CntErrWrongLanA : 32; /*!< [31..0] Valid frames received on LAN A which have an RCT (valid
+                                                 *   length + suffix) but LAN ID is not matching LAN A.                        */
+        } CntErrWrongLanA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntErrWrongLanB;          /*!< (@ 0x00003D38) PRP Wrong ID LAN-B Count Register                          */
+
+        struct
+        {
+            __IM uint32_t CntErrWrongLanB : 32; /*!< [31..0] Valid frames received on LAN B which have an RCT (valid
+                                                 *   length + suffix) but LAN ID is not matching LAN B.                        */
+        } CntErrWrongLanB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntDupLanA;          /*!< (@ 0x00003D3C) PRP Duplicate LAN-A Count Register                         */
+
+        struct
+        {
+            __IM uint32_t CntDupLanA : 32; /*!< [31..0] Valid frames received on LAN A that were dropped by
+                                            *   duplicate detection.                                                      */
+        } CntDupLanA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntDupLanB;          /*!< (@ 0x00003D40) PRP Duplicate LAN-B Count Register                         */
+
+        struct
+        {
+            __IM uint32_t CntDupLanB : 32; /*!< [31..0] Valid frames received on LAN B that were dropped by
+                                            *   duplicate detection.                                                      */
+        } CntDupLanB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntOutOfSeqLowA;          /*!< (@ 0x00003D44) PRP Sequence Error Low LAN-A Count Register                */
+
+        struct
+        {
+            __IM uint32_t CntOutOfSeqLowA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with a sequence
+                                                 *   number less than last window (DUP_W).                                     */
+        } CntOutOfSeqLowA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntOutOfSeqLowB;          /*!< (@ 0x00003D48) PRP Sequence Error Low LAN-B Count Register                */
+
+        struct
+        {
+            __IM uint32_t CntOutOfSeqLowB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with a sequence
+                                                 *   number less than last window (DUP_W).                                     */
+        } CntOutOfSeqLowB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntOutOfSeqA;          /*!< (@ 0x00003D4C) PRP Sequence Error LAN-A Count Register                    */
+
+        struct
+        {
+            __IM uint32_t CntOutOfSeqA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with an
+                                              *   unexpected sequence number.                                               */
+        } CntOutOfSeqA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntOutOfSeqB;          /*!< (@ 0x00003D50) PRP Sequence Error LAN-B Count Register                    */
+
+        struct
+        {
+            __IM uint32_t CntOutOfSeqB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with an
+                                              *   unexpected sequence number.                                               */
+        } CntOutOfSeqB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntAcceptA;          /*!< (@ 0x00003D54) PRP Valid Frame LAN-A Count Register                       */
+
+        struct
+        {
+            __IM uint32_t CntAcceptA : 32; /*!< [31..0] Valid frames received on LAN A which had a valid sequence
+                                            *   number in the expected range.                                             */
+        } CntAcceptA_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntAcceptB;          /*!< (@ 0x00003D58) PRP Valid Frame LAN-B Count Register                       */
+
+        struct
+        {
+            __IM uint32_t CntAcceptB : 32; /*!< [31..0] Valid frames received on LAN B which had a valid sequence
+                                            *   number in the expected range.                                             */
+        } CntAcceptB_b;
+    };
+
+    union
+    {
+        __IM uint32_t CntMissing;          /*!< (@ 0x00003D5C) PRP Drop History Adjustment Count                          */
+
+        struct
+        {
+            __IM uint32_t CntMissing : 32; /*!< [31..0] Indicates adjustment of the drop history as a frame
+                                            *   was received with a sequence number of expected + history
+                                            + 1. This occurs if the same frame was dropped in both
+                                            +   LAN segments (one sequence number is missing) and the history
+                                            +   is now extended beyond that sequence number (causing it
+                                            +   to be treated as drop allowed).                                           */
+        } CntMissing_b;
+    };
+    __IM uint32_t RESERVED108[40];
+
+    union
+    {
+        __IOM uint32_t HUB_CONFIG;             /*!< (@ 0x00003E00) HUB Configuration Register                                 */
+
+        struct
+        {
+            __IOM uint32_t HUB_ENA        : 1; /*!< [0..0] Enable Integrated HUB Operation                                    */
+            __IOM uint32_t RETRANSMIT_ENA : 1; /*!< [1..1] Enable Hub Retransmit Capability                                   */
+            __IOM uint32_t TRIGGER_MODE   : 1; /*!< [2..2] Enable Single Frame Trigger Mode                                   */
+            __IOM uint32_t HUB_ISOLATE    : 1; /*!< [3..3] Isolate all hub ports from the other ports of the switch
+                                                *   and allow communication with management port only. It is
+                                                *   then up to the application of the management port to implement
+                                                *   some bridging functionality to other ports as required.                   */
+            __IOM uint32_t TIMER_SEL     : 1;  /*!< [4..4] Select the timer to use for timed triggers                         */
+            uint32_t                     : 1;
+            __IOM uint32_t IPG_WAIT      : 3;  /*!< [8..6] IPG_WAIT                                                           */
+            __IOM uint32_t CRS_GEN       : 1;  /*!< [9..9] CRS_GEN                                                            */
+            __IOM uint32_t PRMB_GEN_DIS  : 1;  /*!< [10..10] PRMB_GEN_DIS                                                     */
+            __IOM uint32_t JAM_WAIT_IDLE : 1;  /*!< [11..11] JAM_WAIT_IDLE                                                    */
+            uint32_t                     : 20;
+        } HUB_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_GROUP;         /*!< (@ 0x00003E04) HUB Port Group Register                                    */
+
+        struct
+        {
+            __IOM uint32_t HUB_GROUP : 3; /*!< [2..0] Define all ports that should be combined to a Hub Group.           */
+            uint32_t                 : 29;
+        } HUB_GROUP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_DEFPORT;         /*!< (@ 0x00003E08) HUB Default Port Selection Register                        */
+
+        struct
+        {
+            __IOM uint32_t HUB_DEFPORT : 3; /*!< [2..0] The default port within the Hub Group where all traffic
+                                             *   from a port outside the group is forwarded to port (bit
+                                             *   0 = port 0, bit 1 = port 1, and bit 2 = port 2). If a frame
+                                             *   should be forwarded to any of the hub ports, the frame
+                                             *   is sent to this port only. The copy function of the hub
+                                             *   copies it to all PHY interfaces of the group eventually.                  */
+            uint32_t : 29;
+        } HUB_DEFPORT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_TRIGGER_IMMEDIATE;         /*!< (@ 0x00003E0C) HUB Transmission Trigger Immediate Register                */
+
+        struct
+        {
+            __IOM uint32_t HUB_TRIGGER_IMMEDIATE : 3; /*!< [2..0] Trigger immediate transmission of a single frame from
+                                                       *   given port within the hub group (bit 0 = port 0, bit 1
+                                                       *   = port 1, and bit 2 = port 2).                                            */
+            uint32_t : 29;
+        } HUB_TRIGGER_IMMEDIATE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_TRIGGER_AT;         /*!< (@ 0x00003E10) HUB Transmission Trigger At Register                       */
+
+        struct
+        {
+            __IOM uint32_t HUB_TRIGGER_AT : 3; /*!< [2..0] Trigger Transmission of a Single Frame at a Specific
+                                                *   Time (bit 0 = port 0, bit 1 = port 1, and bit 2 = port
+                                                *   2).                                                                       */
+            uint32_t : 29;
+        } HUB_TRIGGER_AT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_TTIME;          /*!< (@ 0x00003E14) HUB Transmission Time Define Register                      */
+
+        struct
+        {
+            __IOM uint32_t HUB_TTIME : 32; /*!< [31..0] Define the Time Value when a Trigger Should Occur                 */
+        } HUB_TTIME_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_IRQ_CONTROL;           /*!< (@ 0x00003E18) HUB Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t RX_TRIGGER : 3;        /*!< [2..0] Enable Interrupt on Receive Pattern Match Trigger Function         */
+            __IOM uint32_t CHANGE_DET : 1;        /*!< [3..3] Enable interrupt for hub TX state machine port state
+                                                   *   change request detection                                                  */
+            __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] Enable interrupt when hub transmit started after writing
+                                                   *   the HUB_TRIGGER_IMMEDIATE register                                        */
+            __IOM uint32_t TRIGGER_TIMER : 1;     /*!< [5..5] Enable interrupt when hub transmit started after writing
+                                                   *   the HUB_TRIGGER_TIME register and the timeout value is
+                                                   *   reached (register HUB_TTIME).                                             */
+            uint32_t : 26;
+        } HUB_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HUB_IRQ_STAT_ACK;          /*!< (@ 0x00003E1C) HUB Interrupt Status/ACK Register                          */
+
+        struct
+        {
+            __IOM uint32_t RX_TRIGGER        : 3; /*!< [2..0] Interrupt Pending Indication                                       */
+            __IOM uint32_t CHANGE_DET        : 1; /*!< [3..3] This bit functions the same as RX_TRIGGER bit.                     */
+            __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] This bit functions the same as RX_TRIGGER bit.                     */
+            __IOM uint32_t TRIGGER_TIMER     : 1; /*!< [5..5] This bit functions the same as RX_TRIGGER bit.                     */
+            uint32_t                         : 26;
+        } HUB_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IM uint32_t HUB_STATUS;                /*!< (@ 0x00003E20) HUB Status Register                                        */
+
+        struct
+        {
+            __IM uint32_t PORTS_ACTIVE : 3;      /*!< [2..0] When this bit is 1, it shows the currently active ports
+                                                  *   of the Hub group which are allowed for transmit.                          */
+            uint32_t                : 6;
+            __IM uint32_t TX_ACTIVE : 1;         /*!< [9..9] When this bit is 1, the hub global transmit state machine
+                                                  *   has successfully entered Hub mode and is now controlling
+                                                  *   the hub group.                                                            */
+            __IM uint32_t TX_BUSY : 1;           /*!< [10..10] When this bit is 1, the local device currently transmits
+                                                  *   data to all ports within the hub group.                                   */
+            __IM uint32_t Speed_OK : 1;          /*!< [11..11] When this bit is 1, it indicates that the port speed
+                                                  *   of all group ports match.                                                 */
+            __IM uint32_t TX_Change_Pending : 1; /*!< [12..12] Indicate a pending change request in the hub transmitter
+                                                  *   that is unsolved and cause the hub to stop operation (no
+                                                  *   longer performing any transmissions).                                     */
+            uint32_t : 19;
+        } HUB_STATUS_b;
+    };
+
+    union
+    {
+        __IM uint32_t HUB_OPORT_STATUS;         /*!< (@ 0x00003E24) HUB Output Port Status Register                            */
+
+        struct
+        {
+            __IM uint32_t HUB_OPORT_STATUS : 3; /*!< [2..0] Per Output Port Data Available Status                              */
+            uint32_t                       : 29;
+        } HUB_OPORT_STATUS_b;
+    };
+    __IM uint32_t RESERVED109[22];
+
+    union
+    {
+        __IOM uint32_t TDMA_CONFIG;             /*!< (@ 0x00003E80) TDMA Configuration Register                                */
+
+        struct
+        {
+            __IOM uint32_t TDMA_ENA   : 1;      /*!< [0..0] Enable TDMA Scheduler                                              */
+            __IM uint32_t  WAIT_START : 1;      /*!< [1..1] Status bit which is set as long as the scheduler is enabled
+                                                 *   but has not yet reached the time given in register TDMA_START.            */
+            __IOM uint32_t TIMER_SEL : 1;       /*!< [2..2] Select which timer to use as the time source for the
+                                                 *   scheduler                                                                 */
+            uint32_t                    : 1;
+            __IM uint32_t  RED_PERIOD   : 1;    /*!< [4..4] Read only bit indicating the current period for Profinet           */
+            __IOM uint32_t RED_OVRD_ENA : 1;    /*!< [5..5] Enables overriding the RED period status, regardless
+                                                 *   of the indication by the TCV.                                             */
+            __IOM uint32_t RED_OVRD     : 1;    /*!< [6..6] Override Value for the RED Period                                  */
+            __OM uint32_t  IN_CT_WREN   : 1;    /*!< [7..7] IN_CT_WREN                                                         */
+            __OM uint32_t  OUT_CT_WREN  : 1;    /*!< [8..8] Enable writing the OUT_CT_ENA control to the egress ports.         */
+            __OM uint32_t  HOLD_REQ_CLR : 1;    /*!< [9..9] Writing 1 to this register clears the state of TDMA hold
+                                                 *   request.                                                                  */
+            uint32_t                       : 2;
+            __IM uint32_t TIMER_SEL_ACTIVE : 1; /*!< [12..12] Return the current timer being used for the TDMA Scheduler       */
+            uint32_t                       : 3;
+            __IOM uint32_t IN_CT_ENA       : 4; /*!< [19..16] On read, return the current status of the ingress Cut-Through
+                                                 *   enable indicated by the TDMA scheduler. On write, override
+                                                 *   the ingress Cut-Through enable if IN_CT_WREN is also 1.                   */
+            uint32_t                  : 4;
+            __IOM uint32_t OUT_CT_ENA : 4;      /*!< [27..24] On read, return the current status of the egress Cut-Through
+                                                 *   enable indicated by the TDMA scheduler. On write, override
+                                                 *   the egress Cut-Through enable if OUT_CT_WREN is also 1.                   */
+            uint32_t : 4;
+        } TDMA_CONFIG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_ENA_CTRL;     /*!< (@ 0x00003E84) TDMA Scheduling Enable Control Register                    */
+
+        struct
+        {
+            __IOM uint32_t PORT_ENA : 4;  /*!< [3..0] Set to 1 to indicate that a port is operating in TDMA
+                                           *   mode. When set to 1 for a port, the port does not prefetch
+                                           *   another frame until the current frame in progress is done
+                                           *   and if TDMA_PREBUF_DIS in COMMAND_CONFIG is set to 1. This
+                                           *   helps adding precision to the queue gating operations indicated
+                                           *   by the TDMA at the expense of loss of line rate.                          */
+            uint32_t                 : 12;
+            __IOM uint32_t QGATE_DIS : 8; /*!< [23..16] One bit per output queue. When a bit is set to 1, the
+                                           *   TDMA scheduler gating commands do not affect the queue
+                                           *   even if the queue mask in the TCV control data is set to
+                                           *   1.                                                                        */
+            __IOM uint32_t QTRIG_DIS : 8; /*!< [31..24] One bit per output queue. When a bit is set to 1, the
+                                           *   TDMA scheduler triggering commands do not affect the queue
+                                           *   even if the queue mask in the TCV control data is set to
+                                           *   1.                                                                        */
+        } TDMA_ENA_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_START;          /*!< (@ 0x00003E88) TDMA Start Time Set Register                               */
+
+        struct
+        {
+            __IOM uint32_t TDMA_START : 32; /*!< [31..0] Set the start time for the very first cycle after system
+                                             *   initialization has completed. The value is compared with
+                                             *   the system time (selected in TDMA_CONFIG.TIMER_SEL) and
+                                             *   when it is reached (crossed), the scheduler begins with
+                                             *   its first cycle. The 2nd cycle is then at TDMA_START +
+                                             *   TDMA_CYCLE.                                                               */
+        } TDMA_START_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_MODULO;          /*!< (@ 0x00003E8C) TDMA System Timer Modulo                                   */
+
+        struct
+        {
+            __IOM uint32_t TDMA_MODULO : 32; /*!< [31..0] The System Timer Modulo                                           */
+        } TDMA_MODULO_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_CYCLE;          /*!< (@ 0x00003E90) TDMA Periodic Cycle Set Register                           */
+
+        struct
+        {
+            __IOM uint32_t TDMA_CYCLE : 32; /*!< [31..0] The periodic cycle time for the scheduler given in system
+                                             *   timer time.                                                               */
+        } TDMA_CYCLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_SEQ_ADDR;        /*!< (@ 0x00003E94) TCV Sequence Address Register                              */
+
+        struct
+        {
+            __IOM uint32_t TCV_S_ADDR : 12; /*!< [11..0] Address to write to or read from in the TCV sequence
+                                             *   table.                                                                    */
+            uint32_t                 : 19;
+            __IOM uint32_t ADDR_AINC : 1;   /*!< [31..31] When set to 1, read and write operations performed
+                                             *   using TCV_SEQ_CTRL causes the address in TCV_S_ADDR to
+                                             *   auto-increment after the operation.                                       */
+        } TCV_SEQ_ADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_SEQ_CTRL;      /*!< (@ 0x00003E98) TCV Sequence Table Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t START : 1;     /*!< [0..0] Indicate this TCV must be executed after the next cycle
+                                           *   start                                                                     */
+            __IOM uint32_t INT : 1;       /*!< [1..1] Indicates this TCV generates an interrupt to the CPU
+                                           *   when activated                                                            */
+            __IOM uint32_t TCV_D_IDX : 9; /*!< [10..2] Index to the TCV Data Entry                                       */
+            uint32_t                 : 11;
+            __IOM uint32_t GPIO      : 8; /*!< [29..22] Generic bits that control the output pins ETHSW_TDMAOUTn
+                                           *   (n = 0 to 7)                                                              */
+            uint32_t                 : 1;
+            __IOM uint32_t READ_MODE : 1; /*!< [31..31] When set to 1, a read operation is performed instead
+                                           *   of writing to the TCV sequence table. The read data (START,
+                                           *   INT, TCV_D_IDX[8:0], and GPIO) can be obtained by reading
+                                           *   this register afterwards. On read, this field always returns
+                                           *   0.                                                                        */
+        } TCV_SEQ_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_SEQ_LAST;   /*!< (@ 0x00003E9C) TCV Sequence Last Entry                                    */
+
+        struct
+        {
+            __IOM uint32_t LAST : 12;  /*!< [11..0] Defines the last entry to read from the TCV sequence
+                                        *   table when the TDMA scheduler is operating.                               */
+            uint32_t             : 4;
+            __IM uint32_t ACTIVE : 12; /*!< [27..16] Return the active TCV sequence entry.                            */
+            uint32_t             : 4;
+        } TCV_SEQ_LAST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_D_ADDR;          /*!< (@ 0x00003EA0) TCV Data Address Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADDR        : 9; /*!< [8..0] Address to read from/write to in the TCV data table                */
+            uint32_t                   : 22;
+            __IOM uint32_t AINC_WR_ENA : 1; /*!< [31..31] Auto-Increment Enable                                            */
+        } TCV_D_ADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_D_OFFSET;          /*!< (@ 0x00003EA4) TCV Data Offset Register                                   */
+
+        struct
+        {
+            __IOM uint32_t TCV_D_OFFSET : 32; /*!< [31..0] 32-bit time offset for the TCV data entry indicated
+                                               *   by TCV_D_ADDR. When accessing the table, TCV_D_OFFSET must
+                                               *   be read or written before TCV_D_CTRL.                                     */
+        } TCV_D_OFFSET_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TCV_D_CTRL;           /*!< (@ 0x00003EA8) TCV Data Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t INC_CTR0     : 1; /*!< [0..0] Increment Control for Counter 0                                    */
+            __IOM uint32_t INC_CTR1     : 1; /*!< [1..1] Increment Control for Counter 1                                    */
+            __IOM uint32_t RED_PERIOD   : 1; /*!< [2..2] Period Color Control (for Profinet IRT)                            */
+            __IOM uint32_t OUT_CT_ENA   : 1; /*!< [3..3] Output Cut-Through Enable                                          */
+            __IOM uint32_t IN_CT_ENA    : 1; /*!< [4..4] Input Cut-Through Enable                                           */
+            __IOM uint32_t TRIGGER_MODE : 1; /*!< [5..5] Trigger mode enable when set to 1. GATE_MODE must be
+                                              *   0, otherwise, GATE_MODE has precedence.                                   */
+            __IOM uint32_t GATE_MODE : 1;    /*!< [6..6] Gate mode enable when set to 1.                                    */
+            __IOM uint32_t HOLD_REQ  : 1;    /*!< [7..7] Preemption hold request. Generates a hold request to
+                                              *   ports enabled in PMASK.                                                   */
+            __IOM uint32_t QGATE : 8;        /*!< [15..8] Bits mask, one per output queue                                   */
+            __IOM uint32_t PMASK : 4;        /*!< [19..16] Bits mask, one per output port                                   */
+            uint32_t             : 12;
+        } TCV_D_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_CTR0;          /*!< (@ 0x00003EAC) TDMA Counter 0                                             */
+
+        struct
+        {
+            __IOM uint32_t TDMA_CTR0 : 32; /*!< [31..0] 32-bit counter that is incremented when the TCV field
+                                            *   INC_CTR0 is set to 1.                                                     */
+        } TDMA_CTR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_CTR1;         /*!< (@ 0x00003EB0) TDMA Counter 1                                             */
+
+        struct
+        {
+            __IOM uint32_t VALUE     : 8; /*!< [7..0] Current Counter Value                                              */
+            __OM uint32_t  WRITE_ENA : 1; /*!< [8..8] Write Enable for VALUE                                             */
+            uint32_t                 : 7;
+            __IOM uint32_t MAX       : 8; /*!< [23..16] Counter Maximum Value                                            */
+            __IOM uint32_t INT_VALUE : 8; /*!< [31..24] Interrupt Value                                                  */
+        } TDMA_CTR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_TCV_START;          /*!< (@ 0x00003EB4) TDMA TCV Sequence Entry Start                              */
+
+        struct
+        {
+            __IOM uint32_t TDMA_TCV_START : 12; /*!< [11..0] Define the TCV_SEQ entry to start from.                           */
+            uint32_t                      : 20;
+        } TDMA_TCV_START_b;
+    };
+
+    union
+    {
+        __IM uint32_t TIME_LOAD_NEXT;          /*!< (@ 0x00003EB8) TDMA Calculated Next Loading Time                          */
+
+        struct
+        {
+            __IM uint32_t TIME_LOAD_NEXT : 32; /*!< [31..0] Status giving the calculated time the scheduler loads
+                                                *   into its internal compare register after the current running
+                                                *   slot end is reached (not the end of the current slot).                    */
+        } TIME_LOAD_NEXT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_IRQ_CONTROL;    /*!< (@ 0x00003EBC) TDMA IRQ Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t TCV_INT_EN  : 1; /*!< [0..0] Enable Interrupts Generated by the TCV                             */
+            uint32_t                   : 12;
+            __IOM uint32_t CTR1_INT_EN : 1; /*!< [13..13] Enable Interrupts Generated from Counter 1                       */
+            uint32_t                   : 18;
+        } TDMA_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_IRQ_STAT_ACK; /*!< (@ 0x00003EC0) TDMA IRQ Status/ACK Register                               */
+
+        struct
+        {
+            __IOM uint32_t TCV_ACK  : 1;  /*!< [0..0] TCV Execution Event                                                */
+            uint32_t                : 12;
+            __IOM uint32_t CTR1_ACK : 1;  /*!< [13..13] Counter 1 Event                                                  */
+            uint32_t                : 18;
+        } TDMA_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TDMA_GPIO;           /*!< (@ 0x00003EC4) TDMA GPIO Register                                         */
+
+        struct
+        {
+            __IM uint32_t GPIO_STATUS : 8;  /*!< [7..0] Status of the GPIO Output Pins                                     */
+            uint32_t                  : 8;
+            __IOM uint32_t GPIO_MODE  : 16; /*!< [31..16] 2 bits per GPIO pin to configure its operating mode              */
+        } TDMA_GPIO_b;
+    };
+    __IM uint32_t RESERVED110[14];
+
+    union
+    {
+        __IOM uint32_t RXMATCH_CONFIG[4];   /*!< (@ 0x00003F00) RX Pattern Matcher Configuration for Port [0..3]           */
+
+        struct
+        {
+            __IOM uint32_t PATTERN_EN : 12; /*!< [11..0] Enable Patterns on the Port (RX)                                  */
+            uint32_t                  : 20;
+        } RXMATCH_CONFIG_b[4];
+    };
+    __IM uint32_t RESERVED111[12];
+
+    union
+    {
+        __IOM uint32_t PATTERN_CTRL[12];        /*!< (@ 0x00003F40) RX Pattern Matcher Function Control for Pattern
+                                                 *                  [0..11]                                                    */
+
+        struct
+        {
+            __IOM uint32_t MATCH_NOT : 1;       /*!< [0..0] When set, a match is reported and the functions of this
+                                                 *   control are executed if the pattern does not match.                       */
+            __IOM uint32_t MGMTFWD : 1;         /*!< [1..1] When set, the frame is forwarded to the management port
+                                                 *   only (suppressing destination address lookup).                            */
+            __IOM uint32_t DISCARD       : 1;   /*!< [2..2] When set, the frame is discarded.                                  */
+            __IOM uint32_t SET_PRIO      : 1;   /*!< [3..3] Set frame priority, overriding normal classification.              */
+            __IOM uint32_t MODE          : 2;   /*!< [5..4] Selects the operating mode                                         */
+            __IOM uint32_t TIMER_SEL_OVR : 1;   /*!< [6..6] Overrides the default timer to use by timestamp operations
+                                                 *   when set to 1, using instead the value in TIMER_SEL.                      */
+            __IOM uint32_t FORCE_FORWARD : 1;   /*!< [7..7] When set, the frame is forwarded to the ports indicated
+                                                 *   in PORTMASK, ignoring the result from L2 lookups.                         */
+            __IOM uint32_t HUBTRIGGER : 1;      /*!< [8..8] When set, the port defined in the PORTMASK setting is
+                                                 *   allowed for transmitting one frame.                                       */
+            __IOM uint32_t MATCH_RED : 1;       /*!< [9..9] Enable the pattern matcher only when the TDMA indicates
+                                                 *   that this is the RED period.                                              */
+            __IOM uint32_t MATCH_NOT_RED : 1;   /*!< [10..10] Enable the pattern matcher only when the TDMA indicates
+                                                 *   that this is not the RED period.                                          */
+            __IOM uint32_t VLAN_SKIP : 1;       /*!< [11..11] When set to 1, for operating modes 1, 2, and 3. The
+                                                 *   first Length/Type after the MAC source address is compared
+                                                 *   against 0x8100. If it matches, a VLAN tag is assumed and
+                                                 *   4 bytes are skipped.                                                      */
+            __IOM uint32_t PRIORITY : 3;        /*!< [14..12] Priority of the frame used when SET_PRIO is set. The
+                                                 *   priority is used to forward the frame into the corresponding
+                                                 *   output queue of a port.                                                   */
+            __IOM uint32_t LEARNING_DIS : 1;    /*!< [15..15] When set to 1, the hardware learning function is not
+                                                 *   executed.                                                                 */
+            __IOM uint32_t PORTMASK : 4;        /*!< [19..16] A port mask used depending on the control bits (for
+                                                 *   example, HUBTRIGGER).                                                     */
+            uint32_t                   : 2;
+            __IOM uint32_t IMC_TRIGGER : 1;     /*!< [22..22] When set, the ports defined in the PORTMASK setting
+                                                 *   are allowed for transmitting one frame from the queues
+                                                 *   indicated by QUEUESEL. The trigger request is sent to the
+                                                 *   integrated memory controller.                                             */
+            __IOM uint32_t IMC_TRIGGER_DLY : 1; /*!< [23..23] When set, the ports defined in the PORTMASK setting
+                                                 *   are allowed for transmitting one frame from the queues
+                                                 *   indicated by QUEUESEL. The trigger request is sent to the
+                                                 *   integrated memory controller and the event is delayed by
+                                                 *   the value programmed in MMCTL_DLY_QTRIGGER_CTRL.                          */
+            __IOM uint32_t SWAP_BYTES : 1;      /*!< [24..24] Applicable only for operating modes 1, 2, and 3. When
+                                                 *   set to 1, the byte order is swapped from the order received
+                                                 *   by the frame. When set to 0, the first byte received by
+                                                 *   the frame is set into position 0 for comparison. When set
+                                                 *   to 1, the first byte received is set into position 3 (for
+                                                 *   mode 1) or position 2 (for mode 2 and 3) for comparison.                  */
+            __IOM uint32_t MATCH_LT : 1;        /*!< [25..25] For operating modes 1, 2, and 3. When set to 1, the
+                                                 *   Length/Type field in the frame after the MAC source address
+                                                 *   is compared against the value in length_type in the compare
+                                                 *   register. If VLAN_SKIP is set and the frame has a VLAN
+                                                 *   tag with Length/Type of 0x8100 then the comparison is performed
+                                                 *   in the Length/Type following the VLAN tag.                                */
+            __IOM uint32_t TIMER_SEL : 1;       /*!< [26..26] Override value to use when TIMER_SEL_OVR is set to
+                                                 *   1 for selecting the timer for this frame.                                 */
+            uint32_t                : 1;
+            __IOM uint32_t QUEUESEL : 4;        /*!< [31..28] A queue selector for the HUBTRIGGER function. Selects
+                                                 *   the queue to trigger a frame, or sets from 0x8 to 0xF to
+                                                 *   select one among all queues.                                              */
+        } PATTERN_CTRL_b[12];
+    };
+    __IM uint32_t RESERVED112[4];
+
+    union
+    {
+        __IOM uint32_t PATTERN_IRQ_CONTROL; /*!< (@ 0x00003F80) RX Pattern Matcher Interrupt Control Register              */
+
+        struct
+        {
+            __IOM uint32_t MATCHINT  : 12;  /*!< [11..0] Enable Interrupt on Receive Pattern Match                         */
+            uint32_t                 : 4;
+            __IOM uint32_t ERROR_INT : 4;   /*!< [19..16] Enable Interrupt on Internal Pattern Matcher Error               */
+            uint32_t                 : 12;
+        } PATTERN_IRQ_CONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PATTERN_IRQ_STAT_ACK; /*!< (@ 0x00003F84) RX Pattern Matcher Interrupt Status/ACK Register           */
+
+        struct
+        {
+            __IOM uint32_t MATCHINT : 12;    /*!< [11..0] Interrupt pending indication for the corresponding pattern
+                                              *   match events (see ).                                                      */
+            uint32_t                 : 4;
+            __IOM uint32_t ERROR_INT : 4;    /*!< [19..16] Interrupt pending indication for a pattern matcher
+                                              *   error, per port.                                                          */
+            uint32_t : 12;
+        } PATTERN_IRQ_STAT_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_VLANID;          /*!< (@ 0x00003F88) Custom VLAN ID Register                                    */
+
+        struct
+        {
+            __IOM uint32_t PTRN_VLANID : 16; /*!< [15..0] Custom VLAN ID to use. The default VLAN ID 0x8100 is
+                                              *   always considered by the hardware. This value can be changed
+                                              *   to detect other VLANs like 0x8808.                                        */
+            uint32_t : 16;
+        } PTRN_VLANID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PATTERN_SEL;         /*!< (@ 0x00003F8C) RX Pattern Number Selection Register                       */
+
+        struct
+        {
+            __IOM uint32_t PATTERN_SEL : 4; /*!< [3..0] Define the pattern number which is selected for read/write
+                                             *   through the PTRN_CMP_* and PTRN_MSK_* registers.                          */
+            uint32_t : 28;
+        } PATTERN_SEL_b;
+    };
+    __IM uint32_t RESERVED113[12];
+
+    union
+    {
+        __IOM uint32_t PTRN_CMP_30;          /*!< (@ 0x00003FC0) Pattern Compare Value Bytes 3 .. 0                         */
+
+        struct
+        {
+            __IOM uint32_t PTRN_CMP_30 : 32; /*!< [31..0] Pattern Compare Value Bytes 3 .. 0                                */
+        } PTRN_CMP_30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_CMP_74;          /*!< (@ 0x00003FC4) Pattern Compare Value Bytes 7 .. 4                         */
+
+        struct
+        {
+            __IOM uint32_t PTRN_CMP_74 : 32; /*!< [31..0] Pattern Compare Value Bytes 7 .. 4                                */
+        } PTRN_CMP_74_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_CMP_118;          /*!< (@ 0x00003FC8) Pattern Compare Value Bytes 11 .. 8                        */
+
+        struct
+        {
+            __IOM uint32_t PTRN_CMP_118 : 32; /*!< [31..0] Pattern Compare Value Bytes 11 .. 8                               */
+        } PTRN_CMP_118_b;
+    };
+    __IM uint32_t RESERVED114;
+
+    union
+    {
+        __IOM uint32_t PTRN_MSK_30;          /*!< (@ 0x00003FD0) Pattern Mask for Bytes 3 .. 0                              */
+
+        struct
+        {
+            __IOM uint32_t PTRN_MSK_30 : 32; /*!< [31..0] PTRN_MSK_30                                                       */
+        } PTRN_MSK_30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_MSK_74;          /*!< (@ 0x00003FD4) Pattern Mask for Bytes 7 .. 4                              */
+
+        struct
+        {
+            __IOM uint32_t PTRN_MSK_74 : 32; /*!< [31..0] PTRN_MSK_74                                                       */
+        } PTRN_MSK_74_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTRN_MSK_118;          /*!< (@ 0x00003FD8) Pattern Mask for Bytes 11 .. 8                             */
+
+        struct
+        {
+            __IOM uint32_t PTRN_MSK_118 : 32; /*!< [31..0] PTRN_MSK_118                                                      */
+        } PTRN_MSK_118_b;
+    };
+} R_ETHSW_Type;                               /*!< Size = 16348 (0x3fdc)                                                     */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ESC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief EtherCAT Slave Controller (R_ESC)
+ */
+
+typedef struct                         /*!< (@ 0x80130000) R_ESC Structure                                            */
+{
+    union
+    {
+        __IM uint8_t TYPE;             /*!< (@ 0x00000000) Type Register                                              */
+
+        struct
+        {
+            __IM uint8_t TYPE : 8;     /*!< [7..0] Type of the EtherCAT slave controller                              */
+        } TYPE_b;
+    };
+
+    union
+    {
+        __IM uint8_t REVISION;         /*!< (@ 0x00000001) Revision Register                                          */
+
+        struct
+        {
+            __IM uint8_t REV : 8;      /*!< [7..0] Revision of the EtherCAT slave controller                          */
+        } REVISION_b;
+    };
+
+    union
+    {
+        __IM uint8_t BUILD;            /*!< (@ 0x00000002) Build Register                                             */
+
+        struct
+        {
+            __IM uint8_t BUILD : 8;    /*!< [7..0] Build number of the EtherCAT slave controller                      */
+        } BUILD_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IM uint8_t FMMU_NUM;         /*!< (@ 0x00000004) FMMU Supported Register                                    */
+
+        struct
+        {
+            __IM uint8_t NUMFMMU : 8;  /*!< [7..0] Number of FMMU channels supported in the EtherCAT slave
+                                        *   controller                                                                */
+        } FMMU_NUM_b;
+    };
+
+    union
+    {
+        __IM uint8_t SYNC_MANAGER;     /*!< (@ 0x00000005) SyncManager Supported Register                             */
+
+        struct
+        {
+            __IM uint8_t NUMSYNC : 8;  /*!< [7..0] Number of SyncManager channels supported in the EtherCAT
+                                        *   slave controller                                                          */
+        } SYNC_MANAGER_b;
+    };
+
+    union
+    {
+        __IM uint8_t RAM_SIZE;         /*!< (@ 0x00000006) RAM Size Register                                          */
+
+        struct
+        {
+            __IM uint8_t RAMSIZE : 8;  /*!< [7..0] Process data RAM size supported in the EtherCAT slave
+                                        *   controller (unit: KB)                                                     */
+        } RAM_SIZE_b;
+    };
+
+    union
+    {
+        __IM uint8_t PORT_DESC;        /*!< (@ 0x00000007) Port Descriptor Register                                   */
+
+        struct
+        {
+            __IM uint8_t P0 : 2;       /*!< [1..0] Port 0 configuration                                               */
+            __IM uint8_t P1 : 2;       /*!< [3..2] Port 1 configuration                                               */
+            __IM uint8_t P2 : 2;       /*!< [5..4] Port 2 configuration                                               */
+            __IM uint8_t P3 : 2;       /*!< [7..6] Port 3 configuration                                               */
+        } PORT_DESC_b;
+    };
+
+    union
+    {
+        __IM uint16_t FEATURE;            /*!< (@ 0x00000008) ESC Features Supported Register                            */
+
+        struct
+        {
+            __IM uint16_t FMMU       : 1; /*!< [0..0] FMMU Operation                                                     */
+            uint16_t                 : 1;
+            __IM uint16_t DC         : 1; /*!< [2..2] Distributed Clock                                                  */
+            __IM uint16_t DCWID      : 1; /*!< [3..3] Distributed Clock Width                                            */
+            uint16_t                 : 2;
+            __IM uint16_t LINKDECMII : 1; /*!< [6..6] Enhanced Link Detection in MII                                     */
+            __IM uint16_t FCS        : 1; /*!< [7..7] Separate handling of FCS errors                                    */
+            __IM uint16_t DCSYNC     : 1; /*!< [8..8] Enhanced DC SYNC activation                                        */
+            __IM uint16_t LRW        : 1; /*!< [9..9] EtherCAT LRW command support                                       */
+            __IM uint16_t RWSUPP     : 1; /*!< [10..10] EtherCAT read/write command support (BRW, APRW, FPRW)            */
+            __IM uint16_t FSCONFIG   : 1; /*!< [11..11] Fixed FMMU/SyncManager configuration                             */
+            uint16_t                 : 4;
+        } FEATURE_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IM uint16_t STATION_ADR;      /*!< (@ 0x00000010) Configured Station Address Register                        */
+
+        struct
+        {
+            __IM uint16_t NODADDR : 16; /*!< [15..0] Node Addressing Address Indication                                */
+        } STATION_ADR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATION_ALIAS;       /*!< (@ 0x00000012) Configured Station Alias Register                          */
+
+        struct
+        {
+            __IOM uint16_t NODALIADDR : 16; /*!< [15..0] Alias Address Indication                                          */
+        } STATION_ALIAS_b;
+    };
+    __IM uint32_t RESERVED3[3];
+
+    union
+    {
+        __IM uint8_t WR_REG_ENABLE;    /*!< (@ 0x00000020) Write Register Enable Register                             */
+
+        struct
+        {
+            __IM uint8_t ENABLE : 1;   /*!< [0..0] Register Write Protection Unlock                                   */
+            uint8_t             : 7;
+        } WR_REG_ENABLE_b;
+    };
+
+    union
+    {
+        __IM uint8_t WR_REG_PROTECT;   /*!< (@ 0x00000021) Write Register Protection Register                         */
+
+        struct
+        {
+            __IM uint8_t PROTECT : 1;  /*!< [0..0] Register Write Protection Specification                            */
+            uint8_t              : 7;
+        } WR_REG_PROTECT_b;
+    };
+    __IM uint16_t RESERVED4;
+    __IM uint32_t RESERVED5[3];
+
+    union
+    {
+        __IM uint8_t ESC_WR_ENABLE;    /*!< (@ 0x00000030) ESC Write Enable Register                                  */
+
+        struct
+        {
+            __IM uint8_t ENABLE : 1;   /*!< [0..0] Register/Memory Write Protection Unlock                            */
+            uint8_t             : 7;
+        } ESC_WR_ENABLE_b;
+    };
+
+    union
+    {
+        __IM uint8_t ESC_WR_PROTECT;   /*!< (@ 0x00000031) ESC Write Protection Register                              */
+
+        struct
+        {
+            __IM uint8_t PROTECT : 1;  /*!< [0..0] Register/Memory Write Protection Specification                     */
+            uint8_t              : 7;
+        } ESC_WR_PROTECT_b;
+    };
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        union
+        {
+            __IM uint8_t ESC_RESET_ECAT_R;   /*!< (@ 0x00000040) ESC Reset ECAT Register for read                           */
+
+            struct
+            {
+                __IM uint8_t RESET_ECAT : 2; /*!< [1..0] Reset Progress Status                                              */
+                uint8_t                 : 6;
+            } ESC_RESET_ECAT_R_b;
+        };
+
+        union
+        {
+            __IM uint8_t ESC_RESET_ECAT_W;   /*!< (@ 0x00000040) ESC Reset ECAT Register for write                          */
+
+            struct
+            {
+                __IM uint8_t RESET_ECAT : 8; /*!< [7..0] Software Reset Setting                                             */
+            } ESC_RESET_ECAT_W_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t ESC_RESET_PDI_R;   /*!< (@ 0x00000041) ESC Reset PDI Register for read                            */
+
+            struct
+            {
+                __IOM uint8_t RESET_PDI : 2; /*!< [1..0] Reset Progress Status                                              */
+                uint8_t                 : 6;
+            } ESC_RESET_PDI_R_b;
+        };
+
+        union
+        {
+            __IOM uint8_t ESC_RESET_PDI_W;   /*!< (@ 0x00000041) ESC Reset PDI Register for write                           */
+
+            struct
+            {
+                __IOM uint8_t RESET_PDI : 8; /*!< [7..0] Software Reset Setting                                             */
+            } ESC_RESET_PDI_W_b;
+        };
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9[47];
+
+    union
+    {
+        __IM uint32_t ESC_DL_CONTROL;   /*!< (@ 0x00000100) ESC DL Control Register                                    */
+
+        struct
+        {
+            __IM uint32_t FWDRULE  : 1; /*!< [0..0] Forwarding Rule                                                    */
+            __IM uint32_t TEMPUSE  : 1; /*!< [1..1] Temporary Use of Bits 15 to 8 Settings                             */
+            uint32_t               : 6;
+            __IM uint32_t LP0      : 2; /*!< [9..8] Loop Port 0 Configuration                                          */
+            __IM uint32_t LP1      : 2; /*!< [11..10] Loop Port 1 Configuration                                        */
+            __IM uint32_t LP2      : 2; /*!< [13..12] Loop Port 2 Configuration                                        */
+            __IM uint32_t LP3      : 2; /*!< [15..14] Loop Port 3 Configuration                                        */
+            __IM uint32_t RXFIFO   : 3; /*!< [18..16] RX FIFO Size                                                     */
+            uint32_t               : 5;
+            __IM uint32_t STAALIAS : 1; /*!< [24..24] Station Alias Status                                             */
+            uint32_t               : 7;
+        } ESC_DL_CONTROL_b;
+    };
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IM uint16_t PHYSICAL_RW_OFFSET; /*!< (@ 0x00000108) Physical Read/Write Offset Register                        */
+
+        struct
+        {
+            __IM uint16_t RWOFFSET : 16;  /*!< [15..0] Offset between Read and Write Addresses                           */
+        } PHYSICAL_RW_OFFSET_b;
+    };
+    __IM uint16_t RESERVED11;
+    __IM uint32_t RESERVED12;
+
+    union
+    {
+        __IM uint16_t ESC_DL_STATUS;    /*!< (@ 0x00000110) ESC DL Status Register                                     */
+
+        struct
+        {
+            __IM uint16_t PDIOPE   : 1; /*!< [0..0] PDI/EEPROM Load State Indication                                   */
+            __IM uint16_t PDIWDST  : 1; /*!< [1..1] PDI Watchdog Timer Status                                          */
+            __IM uint16_t ENHLINKD : 1; /*!< [2..2] Enhanced Link Detection Indication                                 */
+            uint16_t               : 1;
+            __IM uint16_t PHYP0    : 1; /*!< [4..4] Port 0 Link State Indication                                       */
+            __IM uint16_t PHYP1    : 1; /*!< [5..5] Port 1 Link State Indication                                       */
+            __IM uint16_t PHYP2    : 1; /*!< [6..6] Port 2 Link State Indication                                       */
+            __IM uint16_t PHYP3    : 1; /*!< [7..7] Port 3 Link State Indication                                       */
+            __IM uint16_t LP0      : 1; /*!< [8..8] Loop Port 0 State Indication                                       */
+            __IM uint16_t COMP0    : 1; /*!< [9..9] Port 0 Communication State Indication                              */
+            __IM uint16_t LP1      : 1; /*!< [10..10] Loop Port 1 State Indication                                     */
+            __IM uint16_t COMP1    : 1; /*!< [11..11] Port 1 Communication State Indication                            */
+            __IM uint16_t LP2      : 1; /*!< [12..12] Loop Port 2 State Indication                                     */
+            __IM uint16_t COMP2    : 1; /*!< [13..13] Port 2 Communication State Indication                            */
+            __IM uint16_t LP3      : 1; /*!< [14..14] Loop Port 3 State Indication                                     */
+            __IM uint16_t COMP3    : 1; /*!< [15..15] Port 3 Communication State Indication                            */
+        } ESC_DL_STATUS_b;
+    };
+    __IM uint16_t RESERVED13;
+    __IM uint32_t RESERVED14[3];
+
+    union
+    {
+        __IM uint16_t AL_CONTROL;        /*!< (@ 0x00000120) AL Control Register                                        */
+
+        struct
+        {
+            __IM uint16_t INISTATE  : 4; /*!< [3..0] Change the state transition of the device state machine.           */
+            __IM uint16_t ERRINDACK : 1; /*!< [4..4] Error Indication Acknowledge (Response)                            */
+            __IM uint16_t DEVICEID  : 1; /*!< [5..5] Device ID Request                                                  */
+            uint16_t                : 10;
+        } AL_CONTROL_b;
+    };
+    __IM uint16_t RESERVED15;
+    __IM uint32_t RESERVED16[3];
+
+    union
+    {
+        __IOM uint16_t AL_STATUS;        /*!< (@ 0x00000130) AL Status Register                                         */
+
+        struct
+        {
+            __IOM uint16_t ACTSTATE : 4; /*!< [3..0] State Machine State Indication                                     */
+            __IOM uint16_t ERR      : 1; /*!< [4..4] Error State Indication                                             */
+            __IOM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Load State Indication                                    */
+            uint16_t                : 10;
+        } AL_STATUS_b;
+    };
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint16_t AL_STATUS_CODE;      /*!< (@ 0x00000134) AL Status Code Register                                    */
+
+        struct
+        {
+            __IOM uint16_t STATUSCODE : 16; /*!< [15..0] AL status code                                                    */
+        } AL_STATUS_CODE_b;
+    };
+    __IM uint16_t RESERVED18;
+
+    union
+    {
+        __IOM uint8_t RUN_LED_OVERRIDE;   /*!< (@ 0x00000138) RUN LED Override Register                                  */
+
+        struct
+        {
+            __IOM uint8_t LEDCODE : 4;    /*!< [3..0] LED Code Indication (FSM state: Bits [3:0] of the AL
+                                           *   Status register, AL_STATUS)                                               */
+            __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting                                                   */
+            uint8_t                  : 3;
+        } RUN_LED_OVERRIDE_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ERR_LED_OVERRIDE;   /*!< (@ 0x00000139) ERR LED Override Register                                  */
+
+        struct
+        {
+            __IOM uint8_t LEDCODE    : 4; /*!< [3..0] LED Code Indication                                                */
+            __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting                                                   */
+            uint8_t                  : 3;
+        } ERR_LED_OVERRIDE_b;
+    };
+    __IM uint16_t RESERVED19;
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        __IM uint8_t PDI_CONTROL;      /*!< (@ 0x00000140) PDI Control Register                                       */
+
+        struct
+        {
+            __IM uint8_t PDI : 8;      /*!< [7..0] Process Data Interface. In this LSI, the following value
+                                        *   is indicated.                                                             */
+        } PDI_CONTROL_b;
+    };
+
+    union
+    {
+        __IM uint8_t ESC_CONFIG;       /*!< (@ 0x00000141) ESC Configuration Register                                 */
+
+        struct
+        {
+            __IM uint8_t DEVEMU  : 1;  /*!< [0..0] Device emulation (control of AL status)                            */
+            __IM uint8_t ENLALLP : 1;  /*!< [1..1] Sets enhanced link detection for all ports                         */
+            __IM uint8_t DCSYNC  : 1;  /*!< [2..2] Sets the SYNC output unit for distributed clocks (fixed
+                                        *   to 1 in this LSI)                                                         */
+            __IM uint8_t DCLATCH : 1;  /*!< [3..3] Sets the latch input unit for distributed clocks                   */
+            __IM uint8_t ENLP0   : 1;  /*!< [4..4] Port 0 Enhanced Link Detection Setting                             */
+            __IM uint8_t ENLP1   : 1;  /*!< [5..5] Port 1 Enhanced Link Detection Setting                             */
+            __IM uint8_t ENLP2   : 1;  /*!< [6..6] Port 2 Enhanced Link Detection Setting                             */
+            __IM uint8_t ENLP3   : 1;  /*!< [7..7] Port 3 Enhanced Link Detection Setting                             */
+        } ESC_CONFIG_b;
+    };
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
+
+    union
+    {
+        __IM uint8_t PDI_CONFIG;           /*!< (@ 0x00000150) PDI Configuration Register                                 */
+
+        struct
+        {
+            __IM uint8_t ONCHIPBUSCLK : 5; /*!< [4..0] On-Chip Bus Clock Indication                                       */
+            __IM uint8_t ONCHIPBUS    : 3; /*!< [7..5] On-Chip Bus Type Indication                                        */
+        } PDI_CONFIG_b;
+    };
+
+    union
+    {
+        __IM uint8_t SYNC_LATCH_CONFIG; /*!< (@ 0x00000151) SYNC/LATCH PDI Configuration Register                      */
+
+        struct
+        {
+            __IM uint8_t SYNC0OUT : 2;  /*!< [1..0] SYNC0 Output Driver and Polarity Indication                        */
+            __IM uint8_t SYNCLAT0 : 1;  /*!< [2..2] SYNC0/LATCH0 Indication                                            */
+            __IM uint8_t SYNC0MAP : 1;  /*!< [3..3] SYNC0 State Mapping Indication                                     */
+            __IM uint8_t SYNC1OUT : 2;  /*!< [5..4] SYNC1 Output Driver and Polarity Indication                        */
+            __IM uint8_t SYNCLAT1 : 1;  /*!< [6..6] SYNC1/LATCH1 Indication                                            */
+            __IM uint8_t SYNC1MAP : 1;  /*!< [7..7] SYNC1 State Mapping Indication                                     */
+        } SYNC_LATCH_CONFIG_b;
+    };
+
+    union
+    {
+        __IM uint16_t EXT_PDI_CONFIG;     /*!< (@ 0x00000152) Extended PDI Configuration Register                        */
+
+        struct
+        {
+            __IM uint16_t DATABUSWID : 2; /*!< [1..0] PDI Data Bus Width Indication                                      */
+            uint16_t                 : 14;
+        } EXT_PDI_CONFIG_b;
+    };
+    __IM uint32_t RESERVED23[43];
+
+    union
+    {
+        __IM uint16_t ECAT_EVENT_MASK;     /*!< (@ 0x00000200) ECAT Event Mask Register                                   */
+
+        struct
+        {
+            __IM uint16_t ECATEVMASK : 16; /*!< [15..0] Event Request Mask Setting                                        */
+        } ECAT_EVENT_MASK_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint32_t AL_EVENT_MASK;     /*!< (@ 0x00000204) AL Event Mask Register                                     */
+
+        struct
+        {
+            __IOM uint32_t ALEVMASK : 32; /*!< [31..0] Event Request Mask Setting                                        */
+        } AL_EVENT_MASK_b;
+    };
+    __IM uint32_t RESERVED25[2];
+
+    union
+    {
+        __IM uint16_t ECAT_EVENT_REQ;  /*!< (@ 0x00000210) ECAT Event Request Register                                */
+
+        struct
+        {
+            __IM uint16_t DCLATCH : 1; /*!< [0..0] DC Latch Event State Indication                                    */
+            uint16_t              : 1;
+            __IM uint16_t DLSTA   : 1; /*!< [2..2] DL Status Event State Indication                                   */
+            __IM uint16_t ALSTA   : 1; /*!< [3..3] AL Status Event State Indication                                   */
+            __IM uint16_t SMSTA0  : 1; /*!< [4..4] Mirror value of SyncManager 0 Status Indication                    */
+            __IM uint16_t SMSTA1  : 1; /*!< [5..5] Mirror value of SyncManager 1 Status Indication                    */
+            __IM uint16_t SMSTA2  : 1; /*!< [6..6] Mirror value of SyncManager 2 Status Indication                    */
+            __IM uint16_t SMSTA3  : 1; /*!< [7..7] Mirror value of SyncManager 3 Status Indication                    */
+            __IM uint16_t SMSTA4  : 1; /*!< [8..8] Mirror value of SyncManager 4 Status Indication                    */
+            __IM uint16_t SMSTA5  : 1; /*!< [9..9] Mirror value of SyncManager 5 Status Indication                    */
+            __IM uint16_t SMSTA6  : 1; /*!< [10..10] Mirror value of SyncManager 6 Status Indication                  */
+            __IM uint16_t SMSTA7  : 1; /*!< [11..11] Mirror value of SyncManager 7 Status Indication                  */
+            uint16_t              : 4;
+        } ECAT_EVENT_REQ_b;
+    };
+    __IM uint16_t RESERVED26;
+    __IM uint32_t RESERVED27[3];
+
+    union
+    {
+        __IM uint32_t AL_EVENT_REQ;       /*!< (@ 0x00000220) AL Event Request Register                                  */
+
+        struct
+        {
+            __IM uint32_t ALCTRL     : 1; /*!< [0..0] AL Control Event State Indication                                  */
+            __IM uint32_t DCLATCH    : 1; /*!< [1..1] DC Latch Event State Indication                                    */
+            __IM uint32_t DCSYNC0STA : 1; /*!< [2..2] DC SYNC0 State Indication                                          */
+            __IM uint32_t DCSYNC1STA : 1; /*!< [3..3] DC SYNC1 State Indication                                          */
+            __IM uint32_t SYNCACT    : 1; /*!< [4..4] SyncManager Activation Indication                                  */
+            uint32_t                 : 1;
+            __IM uint32_t WDPD       : 1; /*!< [6..6] Watchdog Process Data Indication                                   */
+            uint32_t                 : 1;
+            __IM uint32_t SMINT0     : 1; /*!< [8..8] SyncManager 0 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x0805))                                                 */
+            __IM uint32_t SMINT1 : 1;     /*!< [9..9] SyncManager 1 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x080D))                                                 */
+            __IM uint32_t SMINT2 : 1;     /*!< [10..10] SyncManager 2 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x0815))                                                 */
+            __IM uint32_t SMINT3 : 1;     /*!< [11..11] SyncManager 3 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x081D))                                                 */
+            __IM uint32_t SMINT4 : 1;     /*!< [12..12] SyncManager 4 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x0825))                                                 */
+            __IM uint32_t SMINT5 : 1;     /*!< [13..13] SyncManager 5 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x082D))                                                 */
+            __IM uint32_t SMINT6 : 1;     /*!< [14..14] SyncManager 6 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x0835))                                                 */
+            __IM uint32_t SMINT7 : 1;     /*!< [15..15] SyncManager 7 interrupt (bit 0 or 1 of the SyncManager
+                                           *   status register (0x083D))                                                 */
+            uint32_t : 16;
+        } AL_EVENT_REQ_b;
+    };
+    __IM uint32_t RESERVED28[55];
+
+    union
+    {
+        __IM uint16_t RX_ERR_COUNT[3];   /*!< (@ 0x00000300) RX Error Counter [0..2] Register (n = 0 to 2)              */
+
+        struct
+        {
+            __IM uint16_t INVFRMCNT : 8; /*!< [7..0] Invalid Frame Counter Value Indication                             */
+            __IM uint16_t RXERRCNT  : 8; /*!< [15..8] RX Frame Error Counter Value Indication                           */
+        } RX_ERR_COUNT_b[3];
+    };
+    __IM uint16_t RESERVED29;
+
+    union
+    {
+        __IM uint8_t FWD_RX_ERR_COUNT[3]; /*!< (@ 0x00000308) Forwarded RX Error Counter [0..2] Register (n
+                                           *                  = 0 to 2)                                                  */
+
+        struct
+        {
+            __IM uint8_t FWDERRCNT : 8;   /*!< [7..0] Forwarded Error Counter Value Indication                           */
+        } FWD_RX_ERR_COUNT_b[3];
+    };
+    __IM uint8_t RESERVED30;
+
+    union
+    {
+        __IM uint8_t ECAT_PROC_ERR_COUNT; /*!< (@ 0x0000030C) ECAT Processing Unit Error Counter Register                */
+
+        struct
+        {
+            __IM uint8_t EPUERRCNT : 8;   /*!< [7..0] Processing Unit Error Counter Value Indication                     */
+        } ECAT_PROC_ERR_COUNT_b;
+    };
+
+    union
+    {
+        __IM uint8_t PDI_ERR_COUNT;     /*!< (@ 0x0000030D) PDI Error Counter Register                                 */
+
+        struct
+        {
+            __IM uint8_t PDIERRCNT : 8; /*!< [7..0] PDI Error Counter Value Indication                                 */
+        } PDI_ERR_COUNT_b;
+    };
+    __IM uint16_t RESERVED31;
+
+    union
+    {
+        __IM uint8_t LOST_LINK_COUNT[3];  /*!< (@ 0x00000310) Lost Link Counter [0..2] Register (n = 0 to 2)             */
+
+        struct
+        {
+            __IM uint8_t LOSTLINKCNT : 8; /*!< [7..0] Lost Link Counter Value Indication                                 */
+        } LOST_LINK_COUNT_b[3];
+    };
+    __IM uint8_t  RESERVED32;
+    __IM uint32_t RESERVED33[59];
+
+    union
+    {
+        __IM uint16_t WD_DIVIDE;       /*!< (@ 0x00000400) Watchdog Divider Register                                  */
+
+        struct
+        {
+            __IM uint16_t WDDIV : 16;  /*!< [15..0] Watchdog Clock Frequency Divisor Setting                          */
+        } WD_DIVIDE_b;
+    };
+    __IM uint16_t RESERVED34;
+    __IM uint32_t RESERVED35[3];
+
+    union
+    {
+        __IM uint16_t WDT_PDI;           /*!< (@ 0x00000410) Watchdog Time PDI Register                                 */
+
+        struct
+        {
+            __IM uint16_t WDTIMPDI : 16; /*!< [15..0] Watchdog Overflow Time Setting                                    */
+        } WDT_PDI_b;
+    };
+    __IM uint16_t RESERVED36;
+    __IM uint32_t RESERVED37[3];
+
+    union
+    {
+        __IM uint16_t WDT_DATA;         /*!< (@ 0x00000420) Watchdog Time Process Data Register                        */
+
+        struct
+        {
+            __IM uint16_t WDTIMPD : 16; /*!< [15..0] Watchdog Overflow Time Setting                                    */
+        } WDT_DATA_b;
+    };
+    __IM uint16_t RESERVED38;
+    __IM uint32_t RESERVED39[7];
+
+    union
+    {
+        __IM uint16_t WDS_DATA;        /*!< (@ 0x00000440) Watchdog Status Process Data Register                      */
+
+        struct
+        {
+            __IM uint16_t WDSTAPD : 1; /*!< [0..0] Watchdog State Indication                                          */
+            uint16_t              : 15;
+        } WDS_DATA_b;
+    };
+
+    union
+    {
+        __IM uint8_t WDC_DATA;         /*!< (@ 0x00000442) Watchdog Counter Process Data Register                     */
+
+        struct
+        {
+            __IM uint8_t WDCNTPD : 8;  /*!< [7..0] Watchdog Counter Value Indication                                  */
+        } WDC_DATA_b;
+    };
+
+    union
+    {
+        __IM uint8_t WDC_PDI;          /*!< (@ 0x00000443) Watchdog Counter PDI Register                              */
+
+        struct
+        {
+            __IM uint8_t WDCNTPDI : 8; /*!< [7..0] Watchdog Counter Value Indication                                  */
+        } WDC_PDI_b;
+    };
+    __IM uint32_t RESERVED40[47];
+
+    union
+    {
+        __IM uint8_t EEP_CONF;          /*!< (@ 0x00000500) EEPROM Configuration Register                              */
+
+        struct
+        {
+            __IM uint8_t CTRLPDI   : 1; /*!< [0..0] PDI EEPROM Control                                                 */
+            __IM uint8_t FORCEECAT : 1; /*!< [1..1] EEPROM Access Right Change                                         */
+            uint8_t                : 6;
+        } EEP_CONF_b;
+    };
+
+    union
+    {
+        __IOM uint8_t EEP_STATE;         /*!< (@ 0x00000501) EEPROM PDI Access State Register                           */
+
+        struct
+        {
+            __IOM uint8_t PDIACCESS : 1; /*!< [0..0] EEPROM Access Right Setting                                        */
+            uint8_t                 : 7;
+        } EEP_STATE_b;
+    };
+
+    union
+    {
+        __IOM uint16_t EEP_CONT_STAT;     /*!< (@ 0x00000502) EEPROM Control/Status Register                             */
+
+        struct
+        {
+            __IM uint16_t ECATWREN   : 1; /*!< [0..0] ECAT Write Enable                                                  */
+            uint16_t                 : 5;
+            __IM uint16_t  READBYTE  : 1; /*!< [6..6] EEPROM Read Byte Indication                                        */
+            __IM uint16_t  PROMSIZE  : 1; /*!< [7..7] EEPROM Algorithm Indication                                        */
+            __IOM uint16_t COMMAND   : 3; /*!< [10..8] Command                                                           */
+            __IM uint16_t  CKSUMERR  : 1; /*!< [11..11] Checksum Error Indication                                        */
+            __IM uint16_t  LOADSTA   : 1; /*!< [12..12] EEPROM Loading Status Indication                                 */
+            __IM uint16_t  ACKCMDERR : 1; /*!< [13..13] Acknowledge/Command Error Indication                             */
+            __IM uint16_t  WRENERR   : 1; /*!< [14..14] Write Enable Error Indication                                    */
+            __IM uint16_t  BUSY      : 1; /*!< [15..15] EEPROM Interface State Indication                                */
+        } EEP_CONT_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEP_ADR;          /*!< (@ 0x00000504) EEPROM Address Register                                    */
+
+        struct
+        {
+            __IOM uint32_t ADDRESS : 32; /*!< [31..0] EEPROM Address Setting                                            */
+        } EEP_ADR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EEP_DATA;        /*!< (@ 0x00000508) EEPROM Data Register                                       */
+
+        struct
+        {
+            __IOM uint32_t LODATA : 16; /*!< [15..0] Data to be written to the EEPROM or data read from the
+                                         *   EEPROM (lower 2 bytes)                                                    */
+            __IM uint32_t HIDATA : 16;  /*!< [31..16] Data read from the EEPROM (upper 2 bytes)                        */
+        } EEP_DATA_b;
+    };
+    __IM uint32_t RESERVED41;
+
+    union
+    {
+        __IOM uint16_t MII_CONT_STAT;     /*!< (@ 0x00000510) MII Management Control/Status Register                     */
+
+        struct
+        {
+            __IM uint16_t  WREN      : 1; /*!< [0..0] Write Enable                                                       */
+            __IM uint16_t  PDICTRL   : 1; /*!< [1..1] PDI Control Indication                                             */
+            __IM uint16_t  MILINK    : 1; /*!< [2..2] MI Link Detection                                                  */
+            __IM uint16_t  PHYOFFSET : 5; /*!< [7..3] PHY Address Offset Indication                                      */
+            __IOM uint16_t COMMAND   : 2; /*!< [9..8] Command                                                            */
+            uint16_t                 : 3;
+            __IOM uint16_t READERR   : 1; /*!< [13..13] Read Error Indication                                            */
+            __IM uint16_t  CMDERR    : 1; /*!< [14..14] Command Error Indication                                         */
+            __IM uint16_t  BUSY      : 1; /*!< [15..15] MII Management State Indication                                  */
+        } MII_CONT_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PHY_ADR;         /*!< (@ 0x00000512) PHY Address Register                                       */
+
+        struct
+        {
+            __IOM uint8_t PHYADDR : 5; /*!< [4..0] PHY Address Setting                                                */
+            uint8_t               : 3;
+        } PHY_ADR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PHY_REG_ADR;        /*!< (@ 0x00000513) PHY Register Address Register                              */
+
+        struct
+        {
+            __IOM uint8_t PHYREGADDR : 5; /*!< [4..0] Address of PHY register                                            */
+            uint8_t                  : 3;
+        } PHY_REG_ADR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PHY_DATA;            /*!< (@ 0x00000514) PHY Data Register                                          */
+
+        struct
+        {
+            __IOM uint16_t PHYREGDATA : 16; /*!< [15..0] PHY Register Data Indication/Setting                              */
+        } PHY_DATA_b;
+    };
+
+    union
+    {
+        __IM uint8_t MII_ECAT_ACS_STAT; /*!< (@ 0x00000516) MII Management ECAT Access State Register                  */
+
+        struct
+        {
+            __IM uint8_t ACSMII : 1;    /*!< [0..0] MII Management Interface Access Right Setting                      */
+            uint8_t             : 7;
+        } MII_ECAT_ACS_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MII_PDI_ACS_STAT; /*!< (@ 0x00000517) MII Management PDI Access State Register                   */
+
+        struct
+        {
+            __IOM uint8_t ACSMII : 1;   /*!< [0..0] Right of access to the MII management interface                    */
+            __IM uint8_t  FORPDI : 1;   /*!< [1..1] Forced change of access by the PDI (forced change of
+                                         *   bit 0)                                                                    */
+            uint8_t : 6;
+        } MII_PDI_ACS_STAT_b;
+    };
+    __IM uint32_t         RESERVED42[58];
+    __IOM R_ESC_FMMU_Type FMMU[8];     /*!< (@ 0x00000600) FMMU [0..7] Registers (n = 0 to 7)                         */
+    __IM uint32_t         RESERVED43[96];
+    __IOM R_ESC_SM_Type   SM[8];       /*!< (@ 0x00000800) SyncManager [0..7] Registers (n = 0 to 7)                  */
+    __IM uint32_t         RESERVED44[48];
+
+    union
+    {
+        __IM uint32_t DC_RCV_TIME_PORT[3]; /*!< (@ 0x00000900) Receive Time Port [0..2] Register                          */
+
+        struct
+        {
+            __IM uint32_t RCVTIME0 : 32;   /*!< [31..0] Receive Time Indication/Latch                                     */
+        } DC_RCV_TIME_PORT_b[3];
+    };
+    __IM uint32_t RESERVED45;
+    __IM uint32_t DC_SYS_TIME_L;           /*!< (@ 0x00000910) System Time Register L                                     */
+    __IM uint32_t DC_SYS_TIME_H;           /*!< (@ 0x00000914) System Time Register H                                     */
+    __IM uint32_t DC_RCV_TIME_UNIT_L;      /*!< (@ 0x00000918) Receive Time ECAT Processing Unit Register L               */
+    __IM uint32_t DC_RCV_TIME_UNIT_H;      /*!< (@ 0x0000091C) Receive Time ECAT Processing Unit Register H               */
+    __IM uint32_t DC_SYS_TIME_OFFSET_L;    /*!< (@ 0x00000920) System Time Offset Register L                              */
+    __IM uint32_t DC_SYS_TIME_OFFSET_H;    /*!< (@ 0x00000924) System Time Offset Register H                              */
+
+    union
+    {
+        __IM uint32_t DC_SYS_TIME_DELAY;   /*!< (@ 0x00000928) System Time Delay Register                                 */
+
+        struct
+        {
+            __IM uint32_t SYSTIMDLY : 32;  /*!< [31..0] Propagation Delay Indication                                      */
+        } DC_SYS_TIME_DELAY_b;
+    };
+
+    union
+    {
+        __IM uint32_t DC_SYS_TIME_DIFF; /*!< (@ 0x0000092C) System Time Difference Register                            */
+
+        struct
+        {
+            __IM uint32_t DIFF : 31;    /*!< [30..0] System Time Mean Difference Indication                            */
+            __IM uint32_t LCP  : 1;     /*!< [31..31] System Time Greater/Less Indication                              */
+        } DC_SYS_TIME_DIFF_b;
+    };
+
+    union
+    {
+        __IM uint16_t DC_SPEED_COUNT_START; /*!< (@ 0x00000930) Speed Counter Start Register                               */
+
+        struct
+        {
+            __IM uint16_t SPDCNTSTRT : 15;  /*!< [14..0] Drift Correction Bandwidth Setting                                */
+            uint16_t                 : 1;
+        } DC_SPEED_COUNT_START_b;
+    };
+
+    union
+    {
+        __IM uint16_t DC_SPEED_COUNT_DIFF; /*!< (@ 0x00000932) Speed Counter Difference Register                          */
+
+        struct
+        {
+            __IM uint16_t SPDCNTDIFF : 16; /*!< [15..0] Clock Period Deviation Indication                                 */
+        } DC_SPEED_COUNT_DIFF_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_SYS_TIME_DIFF_FIL_DEPTH; /*!< (@ 0x00000934) System Time Difference Filter Depth Register               */
+
+        struct
+        {
+            __IM uint8_t SYSTIMDEP : 4;          /*!< [3..0] Filter Depth Setting                                               */
+            uint8_t                : 4;
+        } DC_SYS_TIME_DIFF_FIL_DEPTH_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_SPEED_COUNT_FIL_DEPTH; /*!< (@ 0x00000935) Speed Counter Filter Depth Register                        */
+
+        struct
+        {
+            __IM uint8_t CLKPERDEP : 4;        /*!< [3..0] Filter Depth Setting                                               */
+            uint8_t                : 4;
+        } DC_SPEED_COUNT_FIL_DEPTH_b;
+    };
+    __IM uint16_t RESERVED46;
+    __IM uint32_t RESERVED47[18];
+
+    union
+    {
+        __IM uint8_t DC_CYC_CONT;      /*!< (@ 0x00000980) Cyclic Unit Control Register                               */
+
+        struct
+        {
+            __IM uint8_t SYNCOUT : 1;  /*!< [0..0] SYNC Output Unit Control Setting                                   */
+            uint8_t              : 3;
+            __IM uint8_t LATCH0  : 1;  /*!< [4..4] Latch Input Unit 0 Control Setting                                 */
+            __IM uint8_t LATCH1  : 1;  /*!< [5..5] Latch Input Unit 1 Control Setting                                 */
+            uint8_t              : 2;
+        } DC_CYC_CONT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DC_ACT;               /*!< (@ 0x00000981) Activation Register                                        */
+
+        struct
+        {
+            __IOM uint8_t SYNCACT      : 1; /*!< [0..0] Sync Output Unit Activation                                        */
+            __IOM uint8_t SYNC0        : 1; /*!< [1..1] SYNC0 Output Setting                                               */
+            __IOM uint8_t SYNC1        : 1; /*!< [2..2] SYNC1 Output Setting                                               */
+            __IOM uint8_t AUTOACT      : 1; /*!< [3..3] SYNC Output Unit Activation                                        */
+            __IOM uint8_t EXTSTARTTIME : 1; /*!< [4..4] Start Time Cyclic Operation Extension                              */
+            __IOM uint8_t STARTTIME    : 1; /*!< [5..5] Start Time Plausibility                                            */
+            __IOM uint8_t NEARFUTURE   : 1; /*!< [6..6] Near Future Range Setting                                          */
+            __IOM uint8_t DBGPULSE     : 1; /*!< [7..7] Debug Pulse Setting                                                */
+        } DC_ACT_b;
+    };
+
+    union
+    {
+        __IM uint16_t DC_PULSE_LEN;      /*!< (@ 0x00000982) SYNC Signal Pulse Length Register                          */
+
+        struct
+        {
+            __IM uint16_t PULSELEN : 16; /*!< [15..0] SYNC Signal Pulse Length Indication                               */
+        } DC_PULSE_LEN_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_ACT_STAT;       /*!< (@ 0x00000984) Activation Status Register                                 */
+
+        struct
+        {
+            __IM uint8_t SYNC0ACT  : 1; /*!< [0..0] SYNC0 Status Indication                                            */
+            __IM uint8_t SYNC1ACT  : 1; /*!< [1..1] SYNC1 Status Indication                                            */
+            __IM uint8_t STARTTIME : 1; /*!< [2..2] Plausibility Result Indication                                     */
+            uint8_t                : 5;
+        } DC_ACT_STAT_b;
+    };
+    __IM uint8_t  RESERVED48;
+    __IM uint16_t RESERVED49;
+    __IM uint32_t RESERVED50;
+    __IM uint16_t RESERVED51;
+
+    union
+    {
+        __IM uint8_t DC_SYNC0_STAT;    /*!< (@ 0x0000098E) SYNC0 Status Register                                      */
+
+        struct
+        {
+            __IM uint8_t SYNC0STA : 1; /*!< [0..0] SYNC0 State Indication                                             */
+            uint8_t               : 7;
+        } DC_SYNC0_STAT_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_SYNC1_STAT;       /*!< (@ 0x0000098F) SYNC1 Status Register                                      */
+
+        struct
+        {
+            __IM uint8_t SYNC1STA : 1;    /*!< [0..0] SYNC1 State Indication                                             */
+            uint8_t               : 7;
+        } DC_SYNC1_STAT_b;
+    };
+    __IOM uint32_t DC_CYC_START_TIME_L;   /*!< (@ 0x00000990) Start Time Cyclic Operation/Next SYNC0 Pulse
+                                           *                  Register L                                                 */
+    __IOM uint32_t DC_CYC_START_TIME_H;   /*!< (@ 0x00000994) Start Time Cyclic Operation/Next SYNC0 Pulse
+                                           *                  Register H                                                 */
+    __IM uint32_t DC_NEXT_SYNC1_PULSE_L;  /*!< (@ 0x00000998) Next SYNC1 Pulse Register L                                */
+    __IM uint32_t DC_NEXT_SYNC1_PULSE_H;  /*!< (@ 0x0000099C) Next SYNC1 Pulse Register H                                */
+
+    union
+    {
+        __IOM uint32_t DC_SYNC0_CYC_TIME; /*!< (@ 0x000009A0) SYNC0 Cycle Time Register                                  */
+
+        struct
+        {
+            __IOM uint32_t SYNC0CYC : 32; /*!< [31..0] Time Between Consecutive SYNC0 Pulses                             */
+        } DC_SYNC0_CYC_TIME_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DC_SYNC1_CYC_TIME; /*!< (@ 0x000009A4) SYNC1 Cycle Time Register                                  */
+
+        struct
+        {
+            __IOM uint32_t SYNC1CYC : 32; /*!< [31..0] Time between SYNC1 and SYNC0 Pulses                               */
+        } DC_SYNC1_CYC_TIME_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DC_LATCH0_CONT;  /*!< (@ 0x000009A8) Latch 0 Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 0 Positive Edge Function Setting                             */
+            __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 0 Negative Edge Function Setting                             */
+            uint8_t               : 6;
+        } DC_LATCH0_CONT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DC_LATCH1_CONT;  /*!< (@ 0x000009A9) Latch 1 Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 1 Positive Edge Function Setting                             */
+            __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 1 Negative Edge Function Setting                             */
+            uint8_t               : 6;
+        } DC_LATCH1_CONT_b;
+    };
+    __IM uint16_t RESERVED52[2];
+
+    union
+    {
+        __IM uint8_t DC_LATCH0_STAT;   /*!< (@ 0x000009AE) Latch 0 Status Register                                    */
+
+        struct
+        {
+            __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 0 Positive Edge Event Indication                             */
+            __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 0 Negative Edge Event Indication                             */
+            __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 0 Input Pin State Indication                                 */
+            uint8_t               : 5;
+        } DC_LATCH0_STAT_b;
+    };
+
+    union
+    {
+        __IM uint8_t DC_LATCH1_STAT;    /*!< (@ 0x000009AF) Latch 1 Status Register                                    */
+
+        struct
+        {
+            __IM uint8_t EVENTPOS : 1;  /*!< [0..0] Latch 1 Positive Edge Event Indication                             */
+            __IM uint8_t EVENTNEG : 1;  /*!< [1..1] Latch 1 Negative Edge Event Indication                             */
+            __IM uint8_t PINSTATE : 1;  /*!< [2..2] Latch 1 Input Pin State Indication                                 */
+            uint8_t               : 5;
+        } DC_LATCH1_STAT_b;
+    };
+    __IM uint32_t DC_LATCH0_TIME_POS_L; /*!< (@ 0x000009B0) Latch 0 Time Positive Edge Register L                      */
+    __IM uint32_t DC_LATCH0_TIME_POS_H; /*!< (@ 0x000009B4) Latch 0 Time Positive Edge Register H                      */
+    __IM uint32_t DC_LATCH0_TIME_NEG_L; /*!< (@ 0x000009B8) Latch 0 Time Negative Edge Register L                      */
+    __IM uint32_t DC_LATCH0_TIME_NEG_H; /*!< (@ 0x000009BC) Latch 0 Time Negative Edge Register H                      */
+    __IM uint32_t DC_LATCH1_TIME_POS_L; /*!< (@ 0x000009C0) Latch 1 Time Positive Edge Register L                      */
+    __IM uint32_t DC_LATCH1_TIME_POS_H; /*!< (@ 0x000009C4) Latch 1 Time Positive Edge Register H                      */
+    __IM uint32_t DC_LATCH1_TIME_NEG_L; /*!< (@ 0x000009C8) Latch 1 Time Negative Edge Register L                      */
+    __IM uint32_t DC_LATCH1_TIME_NEG_H; /*!< (@ 0x000009CC) Latch 1 Time Negative Edge Register H                      */
+    __IM uint32_t RESERVED53[8];
+
+    union
+    {
+        __IM uint32_t DC_ECAT_CNG_EV_TIME; /*!< (@ 0x000009F0) Buffer Change Event Time Register                          */
+
+        struct
+        {
+            __IM uint32_t ECATCHANGE : 32; /*!< [31..0] Local Time Indication                                             */
+        } DC_ECAT_CNG_EV_TIME_b;
+    };
+    __IM uint32_t RESERVED54;
+
+    union
+    {
+        __IM uint32_t DC_PDI_START_EV_TIME; /*!< (@ 0x000009F8) PDI Buffer Start Event Time Register                       */
+
+        struct
+        {
+            __IM uint32_t PDISTART : 32;    /*!< [31..0] Local Time Indication                                             */
+        } DC_PDI_START_EV_TIME_b;
+    };
+
+    union
+    {
+        __IM uint32_t DC_PDI_CNG_EV_TIME; /*!< (@ 0x000009FC) PDI Buffer Change Event Time Register                      */
+
+        struct
+        {
+            __IM uint32_t PDICHANGE : 32; /*!< [31..0] Local Time Indication                                             */
+        } DC_PDI_CNG_EV_TIME_b;
+    };
+    __IM uint32_t RESERVED55[256];
+    __IM uint32_t PRODUCT_ID_L;           /*!< (@ 0x00000E00) Product ID Register L                                      */
+    __IM uint32_t PRODUCT_ID_H;           /*!< (@ 0x00000E04) Product ID Register H                                      */
+
+    union
+    {
+        __IM uint32_t VENDOR_ID_L;        /*!< (@ 0x00000E08) Vendor ID Register L                                       */
+
+        struct
+        {
+            __IM uint32_t VENDORID : 32;  /*!< [31..0] Vendor ID Indication                                              */
+        } VENDOR_ID_L_b;
+    };
+} R_ESC_Type;                             /*!< Size = 3596 (0xe0c)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_XSPI0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief xSPI (R_XSPI0)
+ */
+
+typedef struct                         /*!< (@ 0x801C0000) R_XSPI0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t WRAPCFG;        /*!< (@ 0x00000000) xSPI Wrapper Configuration Register                        */
+
+        struct
+        {
+            uint32_t                : 8;
+            __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0                                               */
+            uint32_t                : 11;
+            __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1                                              */
+            uint32_t                : 3;
+        } WRAPCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t COMCFG;         /*!< (@ 0x00000004) xSPI Common Configuration Register                         */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension                                */
+            __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension                                 */
+            uint32_t               : 14;
+        } COMCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BMCFG;           /*!< (@ 0x00000008) xSPI Bridge Map Configuration Register                     */
+
+        struct
+        {
+            __IOM uint32_t WRMD    : 1; /*!< [0..0] AXI Write Response mode                                            */
+            uint32_t               : 6;
+            __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode                                      */
+            __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size                                                 */
+            __IOM uint32_t PREEN   : 1; /*!< [16..16] Prefetch enable                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t CMBTIM  : 8; /*!< [31..24] Combination timer                                                */
+        } BMCFG_b;
+    };
+    __IM uint32_t          RESERVED;
+    __IOM R_XSPI0_CSa_Type CSa[2];      /*!< (@ 0x00000010) xSPI Command Map Configuration Register [0..1]             */
+    __IM uint32_t          RESERVED1[8];
+
+    union
+    {
+        __IOM uint32_t LIOCFGCS[2];        /*!< (@ 0x00000050) xSPI Link I/O Configuration Register CSn                   */
+
+        struct
+        {
+            __IOM uint32_t PRTMD     : 10; /*!< [9..0] Protocol mode                                                      */
+            __IOM uint32_t LATEMD    : 1;  /*!< [10..10] Latency mode                                                     */
+            __IOM uint32_t WRMSKMD   : 1;  /*!< [11..11] Write mask mode                                                  */
+            uint32_t                 : 4;
+            __IOM uint32_t CSMIN     : 4;  /*!< [19..16] CS minimum idle term                                             */
+            __IOM uint32_t CSASTEX   : 1;  /*!< [20..20] CS asserting extension                                           */
+            __IOM uint32_t CSNEGEX   : 1;  /*!< [21..21] CS negating extension                                            */
+            __IOM uint32_t SDRDRV    : 1;  /*!< [22..22] SDR driving timing                                               */
+            __IOM uint32_t SDRSMPMD  : 1;  /*!< [23..23] SDR Sampling mode                                                */
+            __IOM uint32_t SDRSMPSFT : 4;  /*!< [27..24] SDR Sampling window shift                                        */
+            __IOM uint32_t DDRSMPEX  : 4;  /*!< [31..28] DDR sampling window extend                                       */
+        } LIOCFGCS_b[2];
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t BMCTL0;         /*!< (@ 0x00000060) xSPI Bridge Map Control Register 0                         */
+
+        struct
+        {
+            __IOM uint32_t CS0ACC : 2; /*!< [1..0] AXI bus channel to slave0 memory area access enable                */
+            __IOM uint32_t CS1ACC : 2; /*!< [3..2] AXI bus channel to slave1 memory area access enable                */
+            uint32_t              : 28;
+        } BMCTL0_b;
+    };
+
+    union
+    {
+        __OM uint32_t BMCTL1;          /*!< (@ 0x00000064) xSPI Bridge Map Control Register 1                         */
+
+        struct
+        {
+            uint32_t              : 8;
+            __OM uint32_t MWRPUSH : 1; /*!< [8..8] Memory Write Data Push                                             */
+            uint32_t              : 1;
+            __OM uint32_t PBUFCLR : 1; /*!< [10..10] Prefetch Buffer clear                                            */
+            uint32_t              : 21;
+        } BMCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMCTL;             /*!< (@ 0x00000068) xSPI Command Map Control Register                          */
+
+        struct
+        {
+            __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code                                                */
+            __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code                                                */
+            __IOM uint32_t XIPEN     : 1; /*!< [16..16] XiP mode enable                                                  */
+            uint32_t                 : 15;
+        } CMCTL_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t CDCTL0;         /*!< (@ 0x00000070) xSPI Command Manual Control Register 0                     */
+
+        struct
+        {
+            __IOM uint32_t TRREQ  : 1; /*!< [0..0] Transaction request                                                */
+            __IOM uint32_t PERMD  : 1; /*!< [1..1] Periodic mode                                                      */
+            uint32_t              : 1;
+            __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
+            __IOM uint32_t TRNUM  : 2; /*!< [5..4] Transaction number                                                 */
+            uint32_t              : 10;
+            __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval                                    */
+            uint32_t              : 3;
+            __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat                                      */
+            uint32_t              : 4;
+        } CDCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDCTL1;          /*!< (@ 0x00000074) xSPI Command Manual Control Register 1                     */
+
+        struct
+        {
+            __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value                               */
+        } CDCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CDCTL2;          /*!< (@ 0x00000078) xSPI Command Manual Control Register 2                     */
+
+        struct
+        {
+            __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value                                 */
+        } CDCTL2_b;
+    };
+    __IM uint32_t          RESERVED4;
+    __IOM R_XSPI0_BUF_Type BUF[4];      /*!< (@ 0x00000080) xSPI Command Manual Buf [0..3]                             */
+    __IM uint32_t          RESERVED5[16];
+
+    union
+    {
+        __IOM uint32_t LPCTL0;         /*!< (@ 0x00000100) xSPI Link Pattern Control Register 0                       */
+
+        struct
+        {
+            __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request                                                    */
+            uint32_t              : 2;
+            __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
+            __IOM uint32_t XDPIN  : 2; /*!< [5..4] XiP Disable pattern pin                                            */
+            uint32_t              : 10;
+            __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length                             */
+            uint32_t              : 2;
+            __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value                              */
+            __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length                             */
+            uint32_t              : 2;
+            __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value                              */
+        } LPCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LPCTL1;         /*!< (@ 0x00000104) xSPI Link Pattern Control Register 1                       */
+
+        struct
+        {
+            __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
+            __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat                                               */
+            uint32_t              : 2;
+            __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width                                               */
+            uint32_t              : 1;
+            __IOM uint32_t RSTSU  : 3; /*!< [14..12] Reset pattern data output setup time                             */
+            uint32_t              : 17;
+        } LPCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LIOCTL;         /*!< (@ 0x00000108) xSPI Link I/O Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t WPCS0  : 1; /*!< [0..0] WP drive for slave0                                                */
+            __IOM uint32_t WPCS1  : 1; /*!< [1..1] WP drive for slave1                                                */
+            uint32_t              : 14;
+            __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave0                                           */
+            __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave1                                           */
+            uint32_t              : 14;
+        } LIOCTL_b;
+    };
+    __IM uint32_t          RESERVED6[9];
+    __IOM R_XSPI0_CSb_Type CSb[2];     /*!< (@ 0x00000130) xSPI Command Calibration Control register [0..1]           */
+    __IM uint32_t          RESERVED7[4];
+
+    union
+    {
+        __IM uint32_t VERSTT;          /*!< (@ 0x00000180) xSPI Version Register                                      */
+
+        struct
+        {
+            __IM uint32_t VER : 32;    /*!< [31..0] Version                                                           */
+        } VERSTT_b;
+    };
+
+    union
+    {
+        __IM uint32_t COMSTT;          /*!< (@ 0x00000184) xSPI Common Status Register                                */
+
+        struct
+        {
+            __IM uint32_t MEMACC  : 1; /*!< [0..0] Memory access ongoing                                              */
+            uint32_t              : 3;
+            __IM uint32_t PBUFNE  : 1; /*!< [4..4] Prefetch Buffer Not Empty                                          */
+            uint32_t              : 1;
+            __IM uint32_t WRBUFNE : 1; /*!< [6..6] Write Buffer Not Empty                                             */
+            uint32_t              : 9;
+            __IM uint32_t ECSCS0  : 1; /*!< [16..16] ECS monitor for slave0                                           */
+            __IM uint32_t INTCS0  : 1; /*!< [17..17] INT monitor for slave0                                           */
+            __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0                                          */
+            uint32_t              : 1;
+            __IM uint32_t ECSCS1  : 1; /*!< [20..20] ECS monitor for slave1                                           */
+            __IM uint32_t INTCS1  : 1; /*!< [21..21] INT monitor for slave1                                           */
+            __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1                                          */
+            uint32_t              : 9;
+        } COMSTT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CASTTCS[2];      /*!< (@ 0x00000188) xSPI Calibration Status Register CSn                       */
+
+        struct
+        {
+            __IM uint32_t CASUC : 32;  /*!< [31..0] Calibration Success                                               */
+        } CASTTCS_b[2];
+    };
+
+    union
+    {
+        __IM uint32_t INTS;              /*!< (@ 0x00000190) xSPI Interrupt Status Register                             */
+
+        struct
+        {
+            __IM uint32_t CMDCMP    : 1; /*!< [0..0] Command Completed                                                  */
+            __IM uint32_t PATCMP    : 1; /*!< [1..1] Pattern Completed                                                  */
+            __IM uint32_t INICMP    : 1; /*!< [2..2] Initial Sequence Completed                                         */
+            __IM uint32_t PERTO     : 1; /*!< [3..3] Periodic transaction timeout                                       */
+            __IM uint32_t DSTOCS0   : 1; /*!< [4..4] DS timeout for slave0                                              */
+            __IM uint32_t DSTOCS1   : 1; /*!< [5..5] DS timeout for slave1                                              */
+            uint32_t                : 2;
+            __IM uint32_t ECSCS0    : 1; /*!< [8..8] ECC error detection for slave0                                     */
+            __IM uint32_t ECSCS1    : 1; /*!< [9..9] ECC error detection for slave1                                     */
+            uint32_t                : 2;
+            __IM uint32_t INTCS0    : 1; /*!< [12..12] Interrupt detection for slave0                                   */
+            __IM uint32_t INTCS1    : 1; /*!< [13..13] Interrupt detection for slave1                                   */
+            uint32_t                : 6;
+            __IM uint32_t BUSERR    : 1; /*!< [20..20] AXI bus error                                                    */
+            uint32_t                : 7;
+            __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0                                    */
+            __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1                                    */
+            __IM uint32_t CASUCCS0  : 1; /*!< [30..30] Calibration success for slave0                                   */
+            __IM uint32_t CASUCCS1  : 1; /*!< [31..31] Calibration success for slave1                                   */
+        } INTS_b;
+    };
+
+    union
+    {
+        __OM uint32_t INTC;               /*!< (@ 0x00000194) xSPI Interrupt Clear Register                              */
+
+        struct
+        {
+            __OM uint32_t CMDCMPC    : 1; /*!< [0..0] Command Completed interrupt clear                                  */
+            __OM uint32_t PATCMPC    : 1; /*!< [1..1] Pattern Completed interrupt clear                                  */
+            __OM uint32_t INICMPC    : 1; /*!< [2..2] Initial Sequence Completed interrupt clear                         */
+            __OM uint32_t PERTOC     : 1; /*!< [3..3] Periodic transaction timeout interrupt clear                       */
+            __OM uint32_t DSTOCS0C   : 1; /*!< [4..4] DS timeout for slave0 interrupt clear                              */
+            __OM uint32_t DSTOCS1C   : 1; /*!< [5..5] DS timeout for slave1 interrupt clear                              */
+            uint32_t                 : 2;
+            __OM uint32_t ECSCS0C    : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear                     */
+            __OM uint32_t ECSCS1C    : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear                     */
+            uint32_t                 : 2;
+            __OM uint32_t INTCS0C    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear                   */
+            __OM uint32_t INTCS1C    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear                   */
+            uint32_t                 : 6;
+            __OM uint32_t BUSERRC    : 1; /*!< [20..20] AXI bus error interrupt clear                                    */
+            uint32_t                 : 7;
+            __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear                    */
+            __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear                    */
+            __OM uint32_t CASUCCS0C  : 1; /*!< [30..30] Calibration success for slave0 interrupt clear                   */
+            __OM uint32_t CASUCCS1C  : 1; /*!< [31..31] Calibration success for slave1 interrupt clear                   */
+        } INTC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INTE;               /*!< (@ 0x00000198) xSPI Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint32_t CMDCMPE    : 1; /*!< [0..0] Command Completed interrupt enable                                 */
+            __IOM uint32_t PATCMPE    : 1; /*!< [1..1] Pattern Completed interrupt enable                                 */
+            __IOM uint32_t INICMPE    : 1; /*!< [2..2] Initial Sequence Completed interrupt enable                        */
+            __IOM uint32_t PERTOE     : 1; /*!< [3..3] Periodic transaction timeout interrupt enable                      */
+            __IOM uint32_t DSTOCS0E   : 1; /*!< [4..4] DS timeout for slave0 interrupt enable                             */
+            __IOM uint32_t DSTOCS1E   : 1; /*!< [5..5] DS timeout for slave1 interrupt enable                             */
+            uint32_t                  : 2;
+            __IOM uint32_t ECSCS0E    : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable                    */
+            __IOM uint32_t ECSCS1E    : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable                    */
+            uint32_t                  : 2;
+            __IOM uint32_t INTCS0E    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable                  */
+            __IOM uint32_t INTCS1E    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable                  */
+            uint32_t                  : 6;
+            __IOM uint32_t BUSERRE    : 1; /*!< [20..20] AXI bus error interrupt enable                                   */
+            uint32_t                  : 7;
+            __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable                   */
+            __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable                   */
+            __IOM uint32_t CASUCCS0E  : 1; /*!< [30..30] Calibration success for slave0 interrupt enable                  */
+            __IOM uint32_t CASUCCS1E  : 1; /*!< [31..31] Calibration success for slave1 interrupt enable                  */
+        } INTE_b;
+    };
+} R_XSPI0_Type;                            /*!< Size = 412 (0x19c)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BSC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus State Controller (R_BSC)
+ */
+
+typedef struct                         /*!< (@ 0x80210000) R_BSC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t CMNCR;          /*!< (@ 0x00000000) Common Control Register                                    */
+
+        struct
+        {
+            uint32_t             : 9;
+            __IOM uint32_t DPRTY : 2;  /*!< [10..9] DMA Burst Transfer Priority                                       */
+            uint32_t             : 13;
+            __IOM uint32_t AL    : 1;  /*!< [24..24] Acknowledge Level                                                */
+            uint32_t             : 3;
+            __IOM uint32_t TL    : 1;  /*!< [28..28] Transfer End Level                                               */
+            uint32_t             : 3;
+        } CMNCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CSnBCR[6];      /*!< (@ 0x00000004) CS[0..5] Space Bus Control Register                        */
+
+        struct
+        {
+            uint32_t             : 9;
+            __IOM uint32_t BSZ   : 2;  /*!< [10..9] Data Bus Width Specification                                      */
+            uint32_t             : 1;
+            __IOM uint32_t TYPE  : 3;  /*!< [14..12] Memory Connected to a Space                                      */
+            uint32_t             : 1;
+            __IOM uint32_t IWRRS : 3;  /*!< [18..16] Idle State Insertion between Read-Read Cycles in the
+                                        *   Same CS Space                                                             */
+            __IOM uint32_t IWRRD : 3;  /*!< [21..19] Idle State Insertion between Read-Read Cycles in Different
+                                        *   CS Spaces                                                                 */
+            __IOM uint32_t IWRWS : 3;  /*!< [24..22] Idle State Insertion between Read-Write Cycles in the
+                                        *   Same CS Space                                                             */
+            __IOM uint32_t IWRWD : 3;  /*!< [27..25] Idle State Insertion between Read-Write Cycles in Different
+                                        *   CS Spaces                                                                 */
+            __IOM uint32_t IWW : 3;    /*!< [30..28] Idle Cycles between Write-Read Cycles and Write-Write
+                                        *   Cycles                                                                    */
+            uint32_t : 1;
+        } CSnBCR_b[6];
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CS0WCR_0;    /*!< (@ 0x00000028) CS0 Space Wait Control Register for Normal Space,
+                                         *                  SRAM with Byte Selection                                   */
+
+            struct
+            {
+                __IOM uint32_t HW : 2;  /*!< [1..0] Delay States from RD#, WEn# Negation to Address, CS0#
+                                         *   Negation                                                                  */
+                uint32_t          : 4;
+                __IOM uint32_t WM : 1;  /*!< [6..6] External Wait Mask Specification                                   */
+                __IOM uint32_t WR : 4;  /*!< [10..7] Number of Access Waits                                            */
+                __IOM uint32_t SW : 2;  /*!< [12..11] Number of Delay Cycles from Address, CSn# Assertion
+                                         *   to RD#, WEn# Assertion                                                    */
+                uint32_t           : 7;
+                __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
+                uint32_t           : 11;
+            } CS0WCR_0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t CS0WCR_1;   /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM
+                                        *                  with Clocked Asynchronous                                  */
+
+            struct
+            {
+                uint32_t           : 6;
+                __IOM uint32_t WM  : 1; /*!< [6..6] External Wait Mask Specification                                   */
+                __IOM uint32_t W   : 4; /*!< [10..7] Number of Access Waits                                            */
+                uint32_t           : 5;
+                __IOM uint32_t BW  : 2; /*!< [17..16] Number of Waits during Burst Access                              */
+                uint32_t           : 2;
+                __IOM uint32_t BST : 2; /*!< [21..20] Burst Count Specification                                        */
+                uint32_t           : 10;
+            } CS0WCR_1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t CS0WCR_2;   /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM
+                                        *                  with Clocked Synchronous                                   */
+
+            struct
+            {
+                uint32_t          : 6;
+                __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification                                   */
+                __IOM uint32_t W  : 4; /*!< [10..7] Number of Access Waits                                            */
+                uint32_t          : 5;
+                __IOM uint32_t BW : 2; /*!< [17..16] Number of Burst Wait Cycles                                      */
+                uint32_t          : 14;
+            } CS0WCR_2_b;
+        };
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t CS2WCR_0;       /*!< (@ 0x00000030) CS2 Space Wait Control Register for Normal Space,
+                                        *                  SRAM with Byte Selection                                   */
+
+        struct
+        {
+            uint32_t           : 6;
+            __IOM uint32_t WM  : 1;    /*!< [6..6] External Wait Mask Specification                                   */
+            __IOM uint32_t WR  : 4;    /*!< [10..7] Number of Access Waits                                            */
+            uint32_t           : 9;
+            __IOM uint32_t BAS : 1;    /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
+            uint32_t           : 11;
+        } CS2WCR_0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CS3WCR_0;       /*!< (@ 0x00000034) CS3 Space Wait Control Register for Normal Space,
+                                        *                  SRAM with Byte Selection                                   */
+
+        struct
+        {
+            uint32_t           : 6;
+            __IOM uint32_t WM  : 1;    /*!< [6..6] External Wait Mask Specification                                   */
+            __IOM uint32_t WR  : 4;    /*!< [10..7] Number of Access Waits                                            */
+            uint32_t           : 9;
+            __IOM uint32_t BAS : 1;    /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
+            uint32_t           : 11;
+        } CS3WCR_0_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t CS5WCR;           /*!< (@ 0x0000003C) CS5 Space Wait Control Register for Normal Space,
+                                          *                  SRAM with Byte Selection, and MPX-I/O                      */
+
+        struct
+        {
+            __IOM uint32_t HW : 2;       /*!< [1..0] Delay Cycles from RD#, WEn# to Address, CS5#                       */
+            uint32_t          : 4;
+            __IOM uint32_t WM : 1;       /*!< [6..6] External Wait Mask Specification                                   */
+            __IOM uint32_t WR : 4;       /*!< [10..7] Number of Read Access Waits                                       */
+            __IOM uint32_t SW : 2;       /*!< [12..11] Number of Delay Cycles from Address, CS5# Assertion
+                                          *   to RD#, WEn# Assertion                                                    */
+            uint32_t                : 3;
+            __IOM uint32_t WW       : 3; /*!< [18..16] Number of Write Access Waits                                     */
+            uint32_t                : 1;
+            __IOM uint32_t MPXWSBAS : 1; /*!< [20..20] MPX-I/O Interface Address Cycle Wait and SRAM with
+                                          *   Byte Selection Byte Access Select                                         */
+            __IOM uint32_t SZSEL : 1;    /*!< [21..21] MPX-I/O Interface Bus Width Specification                        */
+            uint32_t             : 10;
+        } CS5WCR_b;
+    };
+    __IM uint32_t RESERVED3[8];
+
+    union
+    {
+        __IOM uint32_t TOSCOR[6];       /*!< (@ 0x00000060) Timeout Cycle Constant Register [0..5]                     */
+
+        struct
+        {
+            __IOM uint32_t TOCNUM : 16; /*!< [15..0] Timeout Cycle Number                                              */
+            uint32_t              : 16;
+        } TOSCOR_b[6];
+    };
+    __IM uint32_t RESERVED4[2];
+
+    union
+    {
+        __IOM uint32_t TOSTR;            /*!< (@ 0x00000080) Timeout Status Register                                    */
+
+        struct
+        {
+            __IOM uint32_t CS0TOSTF : 1; /*!< [0..0] CS0 Space Timeout Status Flag                                      */
+            uint32_t                : 1;
+            __IOM uint32_t CS2TOSTF : 1; /*!< [2..2] CS2 Space Timeout Status Flag                                      */
+            __IOM uint32_t CS3TOSTF : 1; /*!< [3..3] CS3 Space Timeout Status Flag                                      */
+            uint32_t                : 1;
+            __IOM uint32_t CS5TOSTF : 1; /*!< [5..5] CS5 Space Timeout Status Flag                                      */
+            uint32_t                : 26;
+        } TOSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TOENR;           /*!< (@ 0x00000084) Timeout Enable Register                                    */
+
+        struct
+        {
+            __IOM uint32_t CS0TOEN : 1; /*!< [0..0] CS0 Space Timeout Detection Enable                                 */
+            uint32_t               : 1;
+            __IOM uint32_t CS2TOEN : 1; /*!< [2..2] CS2 Space Timeout Detection Enable                                 */
+            __IOM uint32_t CS3TOEN : 1; /*!< [3..3] CS3 Space Timeout Detection Enable                                 */
+            uint32_t               : 1;
+            __IOM uint32_t CS5TOEN : 1; /*!< [5..5] CS5 Space Timeout Detection Enable                                 */
+            uint32_t               : 26;
+        } TOENR_b;
+    };
+} R_BSC_Type;                           /*!< Size = 136 (0x88)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MBXSEM                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Mailbox and Semaphore (R_MBXSEM)
+ */
+
+typedef struct                         /*!< (@ 0x80240000) R_MBXSEM Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t SEM[8];         /*!< (@ 0x00000000) Semaphore Register [0..7]                                  */
+
+        struct
+        {
+            __IOM uint32_t SEM : 1;    /*!< [0..0] Semaphore bit                                                      */
+            uint32_t           : 31;
+        } SEM_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t SEMRCEN;          /*!< (@ 0x00000020) Semaphore Read Clear Enable Register                       */
+
+        struct
+        {
+            __IOM uint32_t SEMRCEN0 : 1; /*!< [0..0] SEMRCEN0                                                           */
+            __IOM uint32_t SEMRCEN1 : 1; /*!< [1..1] SEMRCEN1                                                           */
+            __IOM uint32_t SEMRCEN2 : 1; /*!< [2..2] SEMRCEN2                                                           */
+            __IOM uint32_t SEMRCEN3 : 1; /*!< [3..3] SEMRCEN3                                                           */
+            __IOM uint32_t SEMRCEN4 : 1; /*!< [4..4] SEMRCEN4                                                           */
+            __IOM uint32_t SEMRCEN5 : 1; /*!< [5..5] SEMRCEN5                                                           */
+            __IOM uint32_t SEMRCEN6 : 1; /*!< [6..6] SEMRCEN6                                                           */
+            __IOM uint32_t SEMRCEN7 : 1; /*!< [7..7] SEMRCEN7                                                           */
+            uint32_t                : 24;
+        } SEMRCEN_b;
+    };
+    __IM uint32_t RESERVED[23];
+
+    union
+    {
+        __IM uint32_t MBXH2C[4];       /*!< (@ 0x00000080) Host to CA55/CR52 Mailbox Register [0..3]                  */
+
+        struct
+        {
+            __IM uint32_t MBX : 32;    /*!< [31..0] MBX                                                               */
+        } MBXH2C_b[4];
+    };
+
+    union
+    {
+        __IM uint32_t MBXISETH2C;        /*!< (@ 0x00000090) Host to CA55/CR52 Mailbox Interrupt Set Register           */
+
+        struct
+        {
+            __IM uint32_t MBX_INT0S : 1; /*!< [0..0] Generates or indicates MBX_INT0 interrupt of mailbox
+                                          *   from external host CPU to internal Cortex-A55/Cortex-R52/CoreSight.       */
+            __IM uint32_t MBX_INT1S : 1; /*!< [1..1] Generates or indicates MBX_INT1 interrupt of mailbox
+                                          *   from external host CPU to internal Cortex-A55/Cortex-R52/CoreSight.       */
+            __IM uint32_t MBX_INT2S : 1; /*!< [2..2] Generates or indicates MBX_INT2 interrupt of mailbox
+                                          *   from external host CPU to internal Cortex-A55/Cortex-R52/CoreSight.       */
+            __IM uint32_t MBX_INT3S : 1; /*!< [3..3] Generates or indicates MBX_INT3 interrupt of mailbox
+                                          *   from external host CPU to internal Cortex-A55/Cortex-R52/CoreSight.       */
+            uint32_t : 28;
+        } MBXISETH2C_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRH2C;        /*!< (@ 0x00000094) Host to CA55/CR52 Mailbox Interrupt Clear Register         */
+
+        struct
+        {
+            __IOM uint32_t MBX_INT0C : 1; /*!< [0..0] Clears or indicates MBX_INT0 interrupt of mailbox from
+                                           *   external host CPU to internal Cortex-A55/Cortex-R52/CoreSight.            */
+            __IOM uint32_t MBX_INT1C : 1; /*!< [1..1] Clears or indicates MBX_INT1 interrupt of mailbox from
+                                           *   external host CPU to internal Cortex-A55/Cortex-R52/CoreSight.            */
+            __IOM uint32_t MBX_INT2C : 1; /*!< [2..2] Clears or indicates MBX_INT2 interrupt of mailbox from
+                                           *   external host CPU to internal Cortex-A55/Cortex-R52/CoreSight.            */
+            __IOM uint32_t MBX_INT3C : 1; /*!< [3..3] Clears or indicates MBX_INT3 interrupt of mailbox from
+                                           *   external host CPU to internal Cortex-A55/Cortex-R52/CoreSight.            */
+            uint32_t : 28;
+        } MBXICLRH2C_b;
+    };
+    __IM uint32_t RESERVED1[26];
+
+    union
+    {
+        __IOM uint32_t MBXC2H[4];      /*!< (@ 0x00000100) CA55/CR52 to Host Mailbox Register [0..3]                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXC2H_b[4];
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETC2H;         /*!< (@ 0x00000110) CA55/CR52 to Host Mailbox Interrupt Set Register           */
+
+        struct
+        {
+            __IOM uint32_t MBX_HINT0S : 1; /*!< [0..0] Generates or indicates MBX_HINT0 interrupt of mailbox
+                                            *   from internal Cortex-A55/Cortex-R52/CoreSight to external
+                                            *   host CPU.                                                                 */
+            __IOM uint32_t MBX_HINT1S : 1; /*!< [1..1] Generates or indicates MBX_HINT1 interrupt of mailbox
+                                            *   from internal Cortex-A55/Cortex-R52/CoreSight to external
+                                            *   host CPU.                                                                 */
+            __IOM uint32_t MBX_HINT2S : 1; /*!< [2..2] Generates or indicates MBX_HINT2 interrupt of mailbox
+                                            *   from internal Cortex-A55/Cortex-R52/CoreSight to external
+                                            *   host CPU.                                                                 */
+            __IOM uint32_t MBX_HINT3S : 1; /*!< [3..3] Generates or indicates MBX_HINT3 interrupt of mailbox
+                                            *   from internal Cortex-A55/Cortex-R52/CoreSight to external
+                                            *   host CPU.                                                                 */
+            uint32_t : 28;
+        } MBXISETC2H_b;
+    };
+
+    union
+    {
+        __IM uint32_t MBXICLRC2H;         /*!< (@ 0x00000114) CA55/CR52 to Host Mailbox Interrupt Clear Register         */
+
+        struct
+        {
+            __IM uint32_t MBX_HINT0C : 1; /*!< [0..0] Clears or indicates MBX_HINT0 interrupt of mailbox from
+                                           *   internal Cortex-A55/Cortex-R52/CoreSight to external host
+                                           *   CPU.                                                                      */
+            __IM uint32_t MBX_HINT1C : 1; /*!< [1..1] Clears or indicates MBX_HINT1 interrupt of mailbox from
+                                           *   internal Cortex-A55/Cortex-R52/CoreSight to external host
+                                           *   CPU.                                                                      */
+            __IM uint32_t MBX_HINT2C : 1; /*!< [2..2] Clears or indicates MBX_HINT2 interrupt of mailbox from
+                                           *   internal Cortex-A55/Cortex-R52/CoreSight to external host
+                                           *   CPU.                                                                      */
+            __IM uint32_t MBX_HINT3C : 1; /*!< [3..3] Clears or indicates MBX_HINT3 interrupt of mailbox from
+                                           *   internal Cortex-A55/Cortex-R52/CoreSight to external host
+                                           *   CPU.                                                                      */
+            uint32_t : 28;
+        } MBXICLRC2H_b;
+    };
+    __IM uint32_t RESERVED2[26];
+
+    union
+    {
+        __IOM uint32_t SEMAR[8];       /*!< (@ 0x00000180) Semaphore Register n among Internal CPUs (n =
+                                        *                  0 to 7)                                                    */
+
+        struct
+        {
+            __IOM uint32_t SEM : 1;    /*!< [0..0] Semaphore bit                                                      */
+            uint32_t           : 31;
+        } SEMAR_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t SEMRCENAR;        /*!< (@ 0x000001A0) Semaphore Read Clear Enable Register among Internal
+                                          *                  CPUs                                                       */
+
+        struct
+        {
+            __IOM uint32_t SEMRCEN0 : 1; /*!< [0..0] SEMRCEN0                                                           */
+            __IOM uint32_t SEMRCEN1 : 1; /*!< [1..1] SEMRCEN1                                                           */
+            __IOM uint32_t SEMRCEN2 : 1; /*!< [2..2] SEMRCEN2                                                           */
+            __IOM uint32_t SEMRCEN3 : 1; /*!< [3..3] SEMRCEN3                                                           */
+            __IOM uint32_t SEMRCEN4 : 1; /*!< [4..4] SEMRCEN4                                                           */
+            __IOM uint32_t SEMRCEN5 : 1; /*!< [5..5] SEMRCEN5                                                           */
+            __IOM uint32_t SEMRCEN6 : 1; /*!< [6..6] SEMRCEN6                                                           */
+            __IOM uint32_t SEMRCEN7 : 1; /*!< [7..7] SEMRCEN7                                                           */
+            uint32_t                : 24;
+        } SEMRCENAR_b;
+    };
+    __IM uint32_t RESERVED3[23];
+
+    union
+    {
+        __IOM uint32_t MBXR0A00;       /*!< (@ 0x00000200) CR52 CPU0 to CA55 Core0 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A01;       /*!< (@ 0x00000204) CR52 CPU0 to CA55 Core0 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A02;       /*!< (@ 0x00000208) CR52 CPU0 to CA55 Core0 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A03;       /*!< (@ 0x0000020C) CR52 CPU0 to CA55 Core0 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR0A0;            /*!< (@ 0x00000210) CR52 CPU0 to CA55 Core0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0A0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR0A00)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR0A0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR0A01)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR0A0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR0A02)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR0A0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR0A03)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-A55 Core0.                    */
+            uint32_t : 28;
+        } MBXISETR0A0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR0A0;            /*!< (@ 0x00000214) CR52 CPU0 to CA55 Core0 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0A0_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR0A00)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR0A0_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR0A01)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR0A0_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR0A02)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR0A0_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR0A03)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-A55 Core0.                    */
+            uint32_t : 28;
+        } MBXICLRR0A0_b;
+    };
+    __IM uint32_t RESERVED4[26];
+
+    union
+    {
+        __IOM uint32_t MBXR0A10;       /*!< (@ 0x00000280) CR52 CPU0 to CA55 Core1 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A11;       /*!< (@ 0x00000284) CR52 CPU0 to CA55 Core1 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A12;       /*!< (@ 0x00000288) CR52 CPU0 to CA55 Core1 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A13;       /*!< (@ 0x0000028C) CR52 CPU0 to CA55 Core1 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR0A1;            /*!< (@ 0x00000290) CR52 CPU0 to CA55 Core1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0A1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR0A10)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR0A1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR0A11)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR0A1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR0A12)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR0A1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR0A13)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-A55 Core1.                    */
+            uint32_t : 28;
+        } MBXISETR0A1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR0A1;            /*!< (@ 0x00000294) CR52 CPU0 to CA55 Core1 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0A1_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR0A10)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR0A1_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR0A11)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR0A1_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR0A12)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR0A1_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR0A13)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-A55 Core1.                    */
+            uint32_t : 28;
+        } MBXICLRR0A1_b;
+    };
+    __IM uint32_t RESERVED5[26];
+
+    union
+    {
+        __IOM uint32_t MBXR0A20;       /*!< (@ 0x00000300) CR52 CPU0 to CA55 Core2 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A20_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A21;       /*!< (@ 0x00000304) CR52 CPU0 to CA55 Core2 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A21_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A22;       /*!< (@ 0x00000308) CR52 CPU0 to CA55 Core2 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A22_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A23;       /*!< (@ 0x0000030C) CR52 CPU0 to CA55 Core2 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A23_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR0A2;            /*!< (@ 0x00000310) CR52 CPU0 to CA55 Core2 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0A2_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR0A20)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR0A2_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR0A21)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR0A2_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR0A22)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR0A2_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR0A23)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-A55 Core2.                    */
+            uint32_t : 28;
+        } MBXISETR0A2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR0A2;            /*!< (@ 0x00000314) CR52 CPU0 to CA55 Core2 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0A2_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR0A20)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR0A2_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR0A21)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR0A2_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR0A22)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR0A2_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR0A23)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-A55 Core2.                    */
+            uint32_t : 28;
+        } MBXICLRR0A2_b;
+    };
+    __IM uint32_t RESERVED6[26];
+
+    union
+    {
+        __IOM uint32_t MBXR0A30;       /*!< (@ 0x00000380) CR52 CPU0 to CA55 Core3 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A31;       /*!< (@ 0x00000384) CR52 CPU0 to CA55 Core3 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A31_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A32;       /*!< (@ 0x00000388) CR52 CPU0 to CA55 Core3 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A32_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0A33;       /*!< (@ 0x0000038C) CR52 CPU0 to CA55 Core3 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR0A33_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR0A3;            /*!< (@ 0x00000390) CR52 CPU0 to CA55 Core3 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0A3_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR0A30)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR0A3_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR0A31)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR0A3_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR0A32)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR0A3_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR0A33)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-A55 Core3.                    */
+            uint32_t : 28;
+        } MBXISETR0A3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR0A3;            /*!< (@ 0x00000394) CR52 CPU0 to CA55 Core3 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0A3_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR0A30)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR0A3_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR0A31)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR0A3_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR0A32)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR0A3_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR0A33)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-A55 Core3.                    */
+            uint32_t : 28;
+        } MBXICLRR0A3_b;
+    };
+    __IM uint32_t RESERVED7[26];
+
+    union
+    {
+        __IOM uint32_t MBXR1A00;       /*!< (@ 0x00000400) CR52 CPU1 to CA55 Core0 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A01;       /*!< (@ 0x00000404) CR52 CPU1 to CA55 Core0 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A02;       /*!< (@ 0x00000408) CR52 CPU1 to CA55 Core0 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A03;       /*!< (@ 0x0000040C) CR52 CPU1 to CA55 Core0 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR1A0;            /*!< (@ 0x00000410) CR52 CPU1 to CA55 Core0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1A0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR1A00)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR1A0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR1A01)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR1A0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR1A02)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR1A0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR1A03)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-A55 Core0.                    */
+            uint32_t : 28;
+        } MBXISETR1A0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR1A0;            /*!< (@ 0x00000414) CR52 CPU1 to CA55 Core0 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1A0_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR1A00)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR1A0_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR1A01)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR1A0_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR1A02)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-A55 Core0.                    */
+            __IOM uint32_t MBX_INTR1A0_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR1A03)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-A55 Core0.                    */
+            uint32_t : 28;
+        } MBXICLRR1A0_b;
+    };
+    __IM uint32_t RESERVED8[26];
+
+    union
+    {
+        __IOM uint32_t MBXR1A10;       /*!< (@ 0x00000480) CR52 CPU1 to CA55 Core1 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A11;       /*!< (@ 0x00000484) CR52 CPU1 to CA55 Core1 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A12;       /*!< (@ 0x00000488) CR52 CPU1 to CA55 Core1 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A13;       /*!< (@ 0x0000048C) CR52 CPU1 to CA55 Core1 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR1A1;            /*!< (@ 0x00000490) CR52 CPU1 to CA55 Core1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1A1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR1A10)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR1A1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR1A11)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR1A1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR1A12)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR1A1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR1A13)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-A55 Core1.                    */
+            uint32_t : 28;
+        } MBXISETR1A1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR1A1;            /*!< (@ 0x00000494) CR52 CPU1 to CA55 Core1 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1A1_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR1A10)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR1A1_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR1A11)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR1A1_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR1A12)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-A55 Core1.                    */
+            __IOM uint32_t MBX_INTR1A1_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR1A13)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-A55 Core1.                    */
+            uint32_t : 28;
+        } MBXICLRR1A1_b;
+    };
+    __IM uint32_t RESERVED9[26];
+
+    union
+    {
+        __IOM uint32_t MBXR1A20;       /*!< (@ 0x00000500) CR52 CPU1 to CA55 Core2 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A20_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A21;       /*!< (@ 0x00000504) CR52 CPU1 to CA55 Core2 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A21_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A22;       /*!< (@ 0x00000508) CR52 CPU1 to CA55 Core2 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A22_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A23;       /*!< (@ 0x0000050C) CR52 CPU1 to CA55 Core2 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A23_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR1A2;            /*!< (@ 0x00000510) CR52 CPU1 to CA55 Core2 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1A2_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR1A20)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR1A2_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR1A21)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR1A2_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR1A22)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR1A2_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR1A23)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-A55 Core2.                    */
+            uint32_t : 28;
+        } MBXISETR1A2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR1A2;            /*!< (@ 0x00000514) CR52 CPU1 to CA55 Core2 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1A2_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR1A20)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR1A2_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR1A21)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR1A2_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR1A22)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-A55 Core2.                    */
+            __IOM uint32_t MBX_INTR1A2_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR1A23)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-A55 Core2.                    */
+            uint32_t : 28;
+        } MBXICLRR1A2_b;
+    };
+    __IM uint32_t RESERVED10[26];
+
+    union
+    {
+        __IOM uint32_t MBXR1A30;       /*!< (@ 0x00000580) CR52 CPU1 to CA55 Core3 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A31;       /*!< (@ 0x00000584) CR52 CPU1 to CA55 Core3 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A31_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A32;       /*!< (@ 0x00000588) CR52 CPU1 to CA55 Core3 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A32_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1A33;       /*!< (@ 0x0000058C) CR52 CPU1 to CA55 Core3 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXR1A33_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR1A3;            /*!< (@ 0x00000590) CR52 CPU1 to CA55 Core3 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1A3_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR1A30)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR1A3_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR1A31)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR1A3_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR1A32)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR1A3_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR1A33)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-A55 Core3.                    */
+            uint32_t : 28;
+        } MBXISETR1A3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR1A3;            /*!< (@ 0x00000594) CR52 CPU1 to CA55 Core3 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1A3_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR1A30)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR1A3_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR1A31)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR1A3_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR1A32)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-A55 Core3.                    */
+            __IOM uint32_t MBX_INTR1A3_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR1A33)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-A55 Core3.                    */
+            uint32_t : 28;
+        } MBXICLRR1A3_b;
+    };
+    __IM uint32_t RESERVED11[26];
+
+    union
+    {
+        __IOM uint32_t MBXA0R00;       /*!< (@ 0x00000600) CA55 Core0 to CR52 CPU0 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0R00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0R01;       /*!< (@ 0x00000604) CA55 Core0 to CR52 CPU0 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0R01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0R02;       /*!< (@ 0x00000608) CA55 Core0 to CR52 CPU0 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0R02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0R03;       /*!< (@ 0x0000060C) CA55 Core0 to CR52 CPU0 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0R03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1R00;       /*!< (@ 0x00000610) CA55 Core1 to CR52 CPU0 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1R00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1R01;       /*!< (@ 0x00000614) CA55 Core1 to CR52 CPU0 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1R01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1R02;       /*!< (@ 0x00000618) CA55 Core1 to CR52 CPU0 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1R02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1R03;       /*!< (@ 0x0000061C) CA55 Core1 to CR52 CPU0 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1R03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2R00;       /*!< (@ 0x00000620) CA55 Core2 to CR52 CPU0 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2R00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2R01;       /*!< (@ 0x00000624) CA55 Core2 to CR52 CPU0 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2R01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2R02;       /*!< (@ 0x00000628) CA55 Core2 to CR52 CPU0 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2R02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2R03;       /*!< (@ 0x0000062C) CA55 Core2 to CR52 CPU0 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2R03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3R00;       /*!< (@ 0x00000630) CA55 Core3 to CR52 CPU0 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3R00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3R01;       /*!< (@ 0x00000634) CA55 Core3 to CR52 CPU0 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3R01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3R02;       /*!< (@ 0x00000638) CA55 Core3 to CR52 CPU0 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3R02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3R03;       /*!< (@ 0x0000063C) CA55 Core3 to CR52 CPU0 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3R03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA0R0;            /*!< (@ 0x00000640) CA55 Core0 to CR52 CPU0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0R0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA0R00)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA0R0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA0R01)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA0R0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA0R02)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA0R0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA0R03)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-R52 CPU0.                    */
+            uint32_t : 28;
+        } MBXISETA0R0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA1R0;            /*!< (@ 0x00000644) CA55 Core1 to CR52 CPU0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA1R0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA1R00)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA1R0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA1R01)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA1R0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA1R02)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA1R0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA1R03)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-R52 CPU0.                    */
+            uint32_t : 28;
+        } MBXISETA1R0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA2R0;            /*!< (@ 0x00000648) CA55 Core2 to CR52 CPU0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA2R0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA2R00)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA2R0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA2R01)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA2R0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA2R02)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA2R0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA2R03)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-R52 CPU0.                    */
+            uint32_t : 28;
+        } MBXISETA2R0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA3R0;            /*!< (@ 0x0000064C) CA55 Core3 to CR52 CPU0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA3R0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA3R00)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA3R0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA3R01)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA3R0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA3R02)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA3R0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA3R03)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-R52 CPU0.                    */
+            uint32_t : 28;
+        } MBXISETA3R0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRAR0;             /*!< (@ 0x00000650) CA55 to CR52 CPU0 Mailbox Interrupt Clear Register         */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0R0_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA0R00)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA0R0_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA0R01)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA0R0_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA0R02)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA0R0_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA0R03)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA1R0_0C : 1; /*!< [4..4] Clears or indicates interrupt status flag (MBX_INTA1R00)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA1R0_1C : 1; /*!< [5..5] Clears or indicates interrupt status flag (MBX_INTA1R01)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA1R0_2C : 1; /*!< [6..6] Clears or indicates interrupt status flag (MBX_INTA1R02)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA1R0_3C : 1; /*!< [7..7] Clears or indicates interrupt status flag (MBX_INTA1R03)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA2R0_0C : 1; /*!< [8..8] Clears or indicates interrupt status flag (MBX_INTA2R00)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA2R0_1C : 1; /*!< [9..9] Clears or indicates interrupt status flag (MBX_INTA2R01)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA2R0_2C : 1; /*!< [10..10] Clears or indicates interrupt status flag (MBX_INTA2R02)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA2R0_3C : 1; /*!< [11..11] Clears or indicates interrupt status flag (MBX_INTA2R03)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA3R0_0C : 1; /*!< [12..12] Clears or indicates interrupt status flag (MBX_INTA3R00)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA3R0_1C : 1; /*!< [13..13] Clears or indicates interrupt status flag (MBX_INTA3R01)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA3R0_2C : 1; /*!< [14..14] Clears or indicates interrupt status flag (MBX_INTA3R02)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-R52 CPU0.                    */
+            __IOM uint32_t MBX_INTA3R0_3C : 1; /*!< [15..15] Clears or indicates interrupt status flag (MBX_INTA3R03)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-R52 CPU0.                    */
+            uint32_t : 16;
+        } MBXICLRAR0_b;
+    };
+    __IM uint32_t RESERVED12[11];
+
+    union
+    {
+        __IOM uint32_t MBXA0R10;       /*!< (@ 0x00000680) CA55 Core0 to CR52 CPU1 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0R10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0R11;       /*!< (@ 0x00000684) CA55 Core0 to CR52 CPU1 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0R11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0R12;       /*!< (@ 0x00000688) CA55 Core0 to CR52 CPU1 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0R12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0R13;       /*!< (@ 0x0000068C) CA55 Core0 to CR52 CPU1 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0R13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1R10;       /*!< (@ 0x00000690) CA55 Core1 to CR52 CPU1 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1R10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1R11;       /*!< (@ 0x00000694) CA55 Core1 to CR52 CPU1 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1R11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1R12;       /*!< (@ 0x00000698) CA55 Core1 to CR52 CPU1 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1R12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1R13;       /*!< (@ 0x0000069C) CA55 Core1 to CR52 CPU1 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1R13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2R10;       /*!< (@ 0x000006A0) CA55 Core2 to CR52 CPU1 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2R10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2R11;       /*!< (@ 0x000006A4) CA55 Core2 to CR52 CPU1 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2R11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2R12;       /*!< (@ 0x000006A8) CA55 Core2 to CR52 CPU1 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2R12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2R13;       /*!< (@ 0x000006AC) CA55 Core2 to CR52 CPU1 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2R13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3R10;       /*!< (@ 0x000006B0) CA55 Core3 to CR52 CPU1 Mailbox Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3R10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3R11;       /*!< (@ 0x000006B4) CA55 Core3 to CR52 CPU1 Mailbox Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3R11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3R12;       /*!< (@ 0x000006B8) CA55 Core3 to CR52 CPU1 Mailbox Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3R12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3R13;       /*!< (@ 0x000006BC) CA55 Core3 to CR52 CPU1 Mailbox Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3R13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA0R1;            /*!< (@ 0x000006C0) CA55 Core0 to CR52 CPU1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0R1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA0R10)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA0R1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA0R11)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA0R1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA0R12)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA0R1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA0R13)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-R52 CPU1.                    */
+            uint32_t : 28;
+        } MBXISETA0R1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA1R1;            /*!< (@ 0x000006C4) CA55 Core1 to CR52 CPU1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA1R1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA1R10)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA1R1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA1R11)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA1R1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA1R12)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA1R1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA1R13)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-R52 CPU1.                    */
+            uint32_t : 28;
+        } MBXISETA1R1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA2R1;            /*!< (@ 0x000006C8) CA55 Core2 to CR52 CPU1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA2R1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA2R10)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA2R1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA2R11)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA2R1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA2R12)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA2R1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA2R13)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-R52 CPU1.                    */
+            uint32_t : 28;
+        } MBXISETA2R1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA3R1;            /*!< (@ 0x000006CC) CA55 Core3 to CR52 CPU1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA3R1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA3R10)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA3R1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA3R11)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA3R1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA3R12)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA3R1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA3R13)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-R52 CPU1.                    */
+            uint32_t : 28;
+        } MBXISETA3R1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRAR1;             /*!< (@ 0x000006D0) CA55 to CR52 CPU1 Mailbox Interrupt Clear Register         */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0R1_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA0R10)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA0R1_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA0R11)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA0R1_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA0R12)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA0R1_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA0R13)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA1R1_0C : 1; /*!< [4..4] Clears or indicates interrupt status flag (MBX_INTA1R10)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA1R1_1C : 1; /*!< [5..5] Clears or indicates interrupt status flag (MBX_INTA1R11)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA1R1_2C : 1; /*!< [6..6] Clears or indicates interrupt status flag (MBX_INTA1R12)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA1R1_3C : 1; /*!< [7..7] Clears or indicates interrupt status flag (MBX_INTA1R13)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA2R1_0C : 1; /*!< [8..8] Clears or indicates interrupt status flag (MBX_INTA2R10)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA2R1_1C : 1; /*!< [9..9] Clears or indicates interrupt status flag (MBX_INTA2R11)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA2R1_2C : 1; /*!< [10..10] Clears or indicates interrupt status flag (MBX_INTA2R12)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA2R1_3C : 1; /*!< [11..11] Clears or indicates interrupt status flag (MBX_INTA2R13)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA3R1_0C : 1; /*!< [12..12] Clears or indicates interrupt status flag (MBX_INTA3R10)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA3R1_1C : 1; /*!< [13..13] Clears or indicates interrupt status flag (MBX_INTA3R11)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA3R1_2C : 1; /*!< [14..14] Clears or indicates interrupt status flag (MBX_INTA3R12)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-R52 CPU1.                    */
+            __IOM uint32_t MBX_INTA3R1_3C : 1; /*!< [15..15] Clears or indicates interrupt status flag (MBX_INTA3R13)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-R52 CPU1.                    */
+            uint32_t : 16;
+        } MBXICLRAR1_b;
+    };
+    __IM uint32_t RESERVED13[11];
+
+    union
+    {
+        __IOM uint32_t MBXR0R10;       /*!< (@ 0x00000700) CR52 CPU0 to CR52 CPU1 Mailbox Register 0                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] Mailbox from Cortex-R52 CPU0 to Cortex-R52 CPU1                   */
+        } MBXR0R10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0R11;       /*!< (@ 0x00000704) CR52 CPU0 to CR52 CPU1 Mailbox Register 1                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] Mailbox from Cortex-R52 CPU0 to Cortex-R52 CPU1                   */
+        } MBXR0R11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0R12;       /*!< (@ 0x00000708) CR52 CPU0 to CR52 CPU1 Mailbox Register 2                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] Mailbox from Cortex-R52 CPU0 to Cortex-R52 CPU1                   */
+        } MBXR0R12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR0R13;       /*!< (@ 0x0000070C) CR52 CPU0 to CR52 CPU1 Mailbox Register 3                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] Mailbox from Cortex-R52 CPU0 to Cortex-R52 CPU1                   */
+        } MBXR0R13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR0R1;            /*!< (@ 0x00000710) CR52 CPU0 to CR52 CPU1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0R1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR0R10)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-R52 CPU1.                     */
+            __IOM uint32_t MBX_INTR0R1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR0R11)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-R52 CPU1.                     */
+            __IOM uint32_t MBX_INTR0R1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR0R12)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-R52 CPU1.                     */
+            __IOM uint32_t MBX_INTR0R1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR0R13)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-R52 CPU1.                     */
+            uint32_t : 28;
+        } MBXISETR0R1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR0R1;            /*!< (@ 0x00000714) CR52 CPU0 to CR52 CPU1 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR0R1_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR0R10)
+                                                *   of mailbox 0 from Cortex-R52 CPU0 to Cortex-R52 CPU1.                     */
+            __IOM uint32_t MBX_INTR0R1_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR0R11)
+                                                *   of mailbox 1 from Cortex-R52 CPU0 to Cortex-R52 CPU1.                     */
+            __IOM uint32_t MBX_INTR0R1_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR0R12)
+                                                *   of mailbox 2 from Cortex-R52 CPU0 to Cortex-R52 CPU1.                     */
+            __IOM uint32_t MBX_INTR0R1_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR0R13)
+                                                *   of mailbox 3 from Cortex-R52 CPU0 to Cortex-R52 CPU1.                     */
+            uint32_t : 28;
+        } MBXICLRR0R1_b;
+    };
+    __IM uint32_t RESERVED14[26];
+
+    union
+    {
+        __IOM uint32_t MBXR1R00;       /*!< (@ 0x00000780) CR52 CPU1 to CR52 CPU0 Mailbox Register 0                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] Mailbox from Cortex-R52 CPU1 to Cortex-R52 CPU0                   */
+        } MBXR1R00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1R01;       /*!< (@ 0x00000784) CR52 CPU1 to CR52 CPU0 Mailbox Register 1                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] Mailbox from Cortex-R52 CPU1 to Cortex-R52 CPU0                   */
+        } MBXR1R01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1R02;       /*!< (@ 0x00000788) CR52 CPU1 to CR52 CPU0 Mailbox Register 2                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] Mailbox from Cortex-R52 CPU1 to Cortex-R52 CPU0                   */
+        } MBXR1R02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXR1R03;       /*!< (@ 0x0000078C) CR52 CPU1 to CR52 CPU0 Mailbox Register 3                  */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] Mailbox from Cortex-R52 CPU1 to Cortex-R52 CPU0                   */
+        } MBXR1R03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETR1R0;            /*!< (@ 0x00000790) CR52 CPU1 to CR52 CPU0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1R0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTR1R00)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-R52 CPU0.                     */
+            __IOM uint32_t MBX_INTR1R0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTR1R01)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-R52 CPU0.                     */
+            __IOM uint32_t MBX_INTR1R0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTR1R02)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-R52 CPU0.                     */
+            __IOM uint32_t MBX_INTR1R0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTR1R03)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-R52 CPU0.                     */
+            uint32_t : 28;
+        } MBXISETR1R0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRR1R0;            /*!< (@ 0x00000794) CR52 CPU1 to CR52 CPU0 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTR1R0_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTR1R00)
+                                                *   of mailbox 0 from Cortex-R52 CPU1 to Cortex-R52 CPU0.                     */
+            __IOM uint32_t MBX_INTR1R0_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTR1R01)
+                                                *   of mailbox 1 from Cortex-R52 CPU1 to Cortex-R52 CPU0.                     */
+            __IOM uint32_t MBX_INTR1R0_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTR1R02)
+                                                *   of mailbox 2 from Cortex-R52 CPU1 to Cortex-R52 CPU0.                     */
+            __IOM uint32_t MBX_INTR1R0_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTR1R03)
+                                                *   of mailbox 3 from Cortex-R52 CPU1 to Cortex-R52 CPU0.                     */
+            uint32_t : 28;
+        } MBXICLRR1R0_b;
+    };
+    __IM uint32_t RESERVED15[26];
+
+    union
+    {
+        __IOM uint32_t MBXA0A10;       /*!< (@ 0x00000800) CA55 Core0 to CA55 Core1 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A11;       /*!< (@ 0x00000804) CA55 Core0 to CA55 Core1 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A12;       /*!< (@ 0x00000808) CA55 Core0 to CA55 Core1 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A13;       /*!< (@ 0x0000080C) CA55 Core0 to CA55 Core1 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA0A1;            /*!< (@ 0x00000810) CA55 Core0 to CA55 Core1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0A1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA0A10)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA0A1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA0A11)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA0A1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA0A12)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA0A1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA0A13)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-A55 Core1.                   */
+            uint32_t : 28;
+        } MBXISETA0A1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA0A1;            /*!< (@ 0x00000814) CA55 Core0 to CA55 Core1 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0A1_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA0A10)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA0A1_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA0A11)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA0A1_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA0A12)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA0A1_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA0A13)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-A55 Core1.                   */
+            uint32_t : 28;
+        } MBXICLRA0A1_b;
+    };
+    __IM uint32_t RESERVED16[26];
+
+    union
+    {
+        __IOM uint32_t MBXA0A20;       /*!< (@ 0x00000880) CA55 Core0 to CA55 Core2 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A20_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A21;       /*!< (@ 0x00000884) CA55 Core0 to CA55 Core2 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A21_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A22;       /*!< (@ 0x00000888) CA55 Core0 to CA55 Core2 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A22_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A23;       /*!< (@ 0x0000088C) CA55 Core0 to CA55 Core2 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A23_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA0A2;            /*!< (@ 0x00000890) CA55 Core0 to CA55 Core2 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0A2_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA0A20)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA0A2_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA0A21)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA0A2_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA0A22)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA0A2_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA0A23)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-A55 Core2.                   */
+            uint32_t : 28;
+        } MBXISETA0A2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA0A2;            /*!< (@ 0x00000894) CA55 Core0 to CA55 Core2 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0A2_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA0A20)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA0A2_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA0A21)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA0A2_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA0A22)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA0A2_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA0A23)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-A55 Core2.                   */
+            uint32_t : 28;
+        } MBXICLRA0A2_b;
+    };
+    __IM uint32_t RESERVED17[26];
+
+    union
+    {
+        __IOM uint32_t MBXA0A30;       /*!< (@ 0x00000900) CA55 Core0 to CA55 Core3 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A31;       /*!< (@ 0x00000904) CA55 Core0 to CA55 Core3 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A31_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A32;       /*!< (@ 0x00000908) CA55 Core0 to CA55 Core3 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A32_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA0A33;       /*!< (@ 0x0000090C) CA55 Core0 to CA55 Core3 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA0A33_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA0A3;            /*!< (@ 0x00000910) CA55 Core0 to CA55 Core3 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0A3_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA0A30)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA0A3_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA0A31)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA0A3_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA0A32)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA0A3_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA0A33)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-A55 Core3.                   */
+            uint32_t : 28;
+        } MBXISETA0A3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA0A3;            /*!< (@ 0x00000914) CA55 Core0 to CA55 Core3 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA0A3_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA0A30)
+                                                *   of mailbox 0 from Cortex-A55 Core0 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA0A3_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA0A31)
+                                                *   of mailbox 1 from Cortex-A55 Core0 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA0A3_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA0A32)
+                                                *   of mailbox 2 from Cortex-A55 Core0 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA0A3_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA0A33)
+                                                *   of mailbox 3 from Cortex-A55 Core0 to Cortex-A55 Core3.                   */
+            uint32_t : 28;
+        } MBXICLRA0A3_b;
+    };
+    __IM uint32_t RESERVED18[26];
+
+    union
+    {
+        __IOM uint32_t MBXA1A00;       /*!< (@ 0x00000980) CA55 Core1 to CA55 Core0 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A01;       /*!< (@ 0x00000984) CA55 Core1 to CA55 Core0 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A02;       /*!< (@ 0x00000988) CA55 Core1 to CA55 Core0 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A03;       /*!< (@ 0x0000098C) CA55 Core1 to CA55 Core0 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA1A0;            /*!< (@ 0x00000990) CA55 Core1 to CA55 Core0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA1A0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA1A00)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA1A0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA1A01)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA1A0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA1A02)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA1A0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA1A03)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-A55 Core0.                   */
+            uint32_t : 28;
+        } MBXISETA1A0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA1A0;            /*!< (@ 0x00000994) CA55 Core1 to CA55 Core0 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA1A0_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA1A00)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA1A0_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA1A01)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA1A0_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA1A02)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA1A0_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA1A03)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-A55 Core0.                   */
+            uint32_t : 28;
+        } MBXICLRA1A0_b;
+    };
+    __IM uint32_t RESERVED19[26];
+
+    union
+    {
+        __IOM uint32_t MBXA1A20;       /*!< (@ 0x00000A00) CA55 Core1 to CA55 Core2 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A20_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A21;       /*!< (@ 0x00000A04) CA55 Core1 to CA55 Core2 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A21_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A22;       /*!< (@ 0x00000A08) CA55 Core1 to CA55 Core2 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A22_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A23;       /*!< (@ 0x00000A0C) CA55 Core1 to CA55 Core2 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A23_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA1A2;            /*!< (@ 0x00000A10) CA55 Core1 to CA55 Core2 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA1A2_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA1A20)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA1A2_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA1A21)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA1A2_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA1A22)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA1A2_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA1A23)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-A55 Core2.                   */
+            uint32_t : 28;
+        } MBXISETA1A2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA1A2;            /*!< (@ 0x00000A14) CA55 Core1 to CA55 Core2 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA1A2_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA1A20)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA1A2_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA1A21)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA1A2_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA1A22)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA1A2_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA1A23)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-A55 Core2.                   */
+            uint32_t : 28;
+        } MBXICLRA1A2_b;
+    };
+    __IM uint32_t RESERVED20[26];
+
+    union
+    {
+        __IOM uint32_t MBXA1A30;       /*!< (@ 0x00000A80) CA55 Core1 to CA55 Core3 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A31;       /*!< (@ 0x00000A84) CA55 Core1 to CA55 Core3 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A31_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A32;       /*!< (@ 0x00000A88) CA55 Core1 to CA55 Core3 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A32_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA1A33;       /*!< (@ 0x00000A8C) CA55 Core1 to CA55 Core3 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA1A33_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA1A3;            /*!< (@ 0x00000A90) CA55 Core1 to CA55 Core3 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA1A3_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA1A30)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA1A3_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA1A31)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA1A3_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA1A32)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA1A3_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA1A33)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-A55 Core3.                   */
+            uint32_t : 28;
+        } MBXISETA1A3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA1A3;            /*!< (@ 0x00000A94) CA55 Core1 to CA55 Core3 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA1A3_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA1A30)
+                                                *   of mailbox 0 from Cortex-A55 Core1 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA1A3_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA1A31)
+                                                *   of mailbox 1 from Cortex-A55 Core1 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA1A3_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA1A32)
+                                                *   of mailbox 2 from Cortex-A55 Core1 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA1A3_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA1A33)
+                                                *   of mailbox 3 from Cortex-A55 Core1 to Cortex-A55 Core3.                   */
+            uint32_t : 28;
+        } MBXICLRA1A3_b;
+    };
+    __IM uint32_t RESERVED21[26];
+
+    union
+    {
+        __IOM uint32_t MBXA2A00;       /*!< (@ 0x00000B00) CA55 Core2 to CA55 Core0 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A01;       /*!< (@ 0x00000B04) CA55 Core2 to CA55 Core0 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A02;       /*!< (@ 0x00000B08) CA55 Core2 to CA55 Core0 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A03;       /*!< (@ 0x00000B0C) CA55 Core2 to CA55 Core0 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA2A0;            /*!< (@ 0x00000B10) CA55 Core2 to CA55 Core0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA2A0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA2A00)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA2A0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA2A01)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA2A0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA2A02)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA2A0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA2A03)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-A55 Core0.                   */
+            uint32_t : 28;
+        } MBXISETA2A0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA2A0;            /*!< (@ 0x00000B14) CA55 Core2 to CA55 Core0 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA2A0_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA2A00)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA2A0_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA2A01)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA2A0_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA2A02)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA2A0_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA2A03)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-A55 Core0.                   */
+            uint32_t : 28;
+        } MBXICLRA2A0_b;
+    };
+    __IM uint32_t RESERVED22[26];
+
+    union
+    {
+        __IOM uint32_t MBXA2A10;       /*!< (@ 0x00000B80) CA55 Core2 to CA55 Core1 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A11;       /*!< (@ 0x00000B84) CA55 Core2 to CA55 Core1 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A12;       /*!< (@ 0x00000B88) CA55 Core2 to CA55 Core1 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A13;       /*!< (@ 0x00000B8C) CA55 Core2 to CA55 Core1 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA2A1;            /*!< (@ 0x00000B90) CA55 Core2 to CA55 Core1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA2A1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA2A10)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA2A1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA2A11)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA2A1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA2A12)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA2A1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA2A13)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-A55 Core1.                   */
+            uint32_t : 28;
+        } MBXISETA2A1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA2A1;            /*!< (@ 0x00000B94) CA55 Core2 to CA55 Core1 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA2A1_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA2A10)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA2A1_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA2A11)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA2A1_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA2A12)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA2A1_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA2A13)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-A55 Core1.                   */
+            uint32_t : 28;
+        } MBXICLRA2A1_b;
+    };
+    __IM uint32_t RESERVED23[26];
+
+    union
+    {
+        __IOM uint32_t MBXA2A30;       /*!< (@ 0x00000C00) CA55 Core2 to CA55 Core3 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A30_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A31;       /*!< (@ 0x00000C04) CA55 Core2 to CA55 Core3 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A31_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A32;       /*!< (@ 0x00000C08) CA55 Core2 to CA55 Core3 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A32_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA2A33;       /*!< (@ 0x00000C0C) CA55 Core2 to CA55 Core3 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA2A33_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA2A3;            /*!< (@ 0x00000C10) CA55 Core2 to CA55 Core3 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA2A3_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA2A30)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA2A3_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA2A31)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA2A3_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA2A32)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA2A3_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA2A33)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-A55 Core3.                   */
+            uint32_t : 28;
+        } MBXISETA2A3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA2A3;            /*!< (@ 0x00000C14) CA55 Core2 to CA55 Core3 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA2A3_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA2A30)
+                                                *   of mailbox 0 from Cortex-A55 Core2 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA2A3_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA2A31)
+                                                *   of mailbox 1 from Cortex-A55 Core2 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA2A3_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA2A32)
+                                                *   of mailbox 2 from Cortex-A55 Core2 to Cortex-A55 Core3.                   */
+            __IOM uint32_t MBX_INTA2A3_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA2A33)
+                                                *   of mailbox 3 from Cortex-A55 Core2 to Cortex-A55 Core3.                   */
+            uint32_t : 28;
+        } MBXICLRA2A3_b;
+    };
+    __IM uint32_t RESERVED24[26];
+
+    union
+    {
+        __IOM uint32_t MBXA3A00;       /*!< (@ 0x00000C80) CA55 Core3 to CA55 Core0 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A00_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A01;       /*!< (@ 0x00000C84) CA55 Core3 to CA55 Core0 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A02;       /*!< (@ 0x00000C88) CA55 Core3 to CA55 Core0 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A02_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A03;       /*!< (@ 0x00000C8C) CA55 Core3 to CA55 Core0 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A03_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA3A0;            /*!< (@ 0x00000C90) CA55 Core3 to CA55 Core0 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA3A0_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA3A00)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA3A0_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA3A01)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA3A0_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA3A02)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA3A0_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA3A03)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-A55 Core0.                   */
+            uint32_t : 28;
+        } MBXISETA3A0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA3A0;            /*!< (@ 0x00000C94) CA55 Core3 to CA55 Core0 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA3A0_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA3A00)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA3A0_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA3A01)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA3A0_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA3A02)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-A55 Core0.                   */
+            __IOM uint32_t MBX_INTA3A0_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA3A03)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-A55 Core0.                   */
+            uint32_t : 28;
+        } MBXICLRA3A0_b;
+    };
+    __IM uint32_t RESERVED25[26];
+
+    union
+    {
+        __IOM uint32_t MBXA3A10;       /*!< (@ 0x00000D00) CA55 Core3 to CA55 Core1 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A11;       /*!< (@ 0x00000D04) CA55 Core3 to CA55 Core1 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A12;       /*!< (@ 0x00000D08) CA55 Core3 to CA55 Core1 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A12_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A13;       /*!< (@ 0x00000D0C) CA55 Core3 to CA55 Core1 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A13_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA3A1;            /*!< (@ 0x00000D10) CA55 Core3 to CA55 Core1 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA3A1_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA3A10)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA3A1_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA3A11)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA3A1_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA3A12)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA3A1_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA3A13)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-A55 Core1.                   */
+            uint32_t : 28;
+        } MBXISETA3A1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA3A1;            /*!< (@ 0x00000D14) CA55 Core3 to CA55 Core1 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA3A1_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA3A10)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA3A1_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA3A11)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA3A1_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA3A12)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-A55 Core1.                   */
+            __IOM uint32_t MBX_INTA3A1_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA3A13)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-A55 Core1.                   */
+            uint32_t : 28;
+        } MBXICLRA3A1_b;
+    };
+    __IM uint32_t RESERVED26[26];
+
+    union
+    {
+        __IOM uint32_t MBXA3A20;       /*!< (@ 0x00000D80) CA55 Core3 to CA55 Core2 Mailbox Register 0                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A20_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A21;       /*!< (@ 0x00000D84) CA55 Core3 to CA55 Core2 Mailbox Register 1                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A21_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A22;       /*!< (@ 0x00000D88) CA55 Core3 to CA55 Core2 Mailbox Register 2                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A22_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXA3A23;       /*!< (@ 0x00000D8C) CA55 Core3 to CA55 Core2 Mailbox Register 3                */
+
+        struct
+        {
+            __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
+        } MBXA3A23_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXISETA3A2;            /*!< (@ 0x00000D90) CA55 Core3 to CA55 Core2 Mailbox Interrupt Set
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA3A2_0S : 1; /*!< [0..0] Sets or indicates interrupt status flag (MBX_INTA3A20)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA3A2_1S : 1; /*!< [1..1] Sets or indicates interrupt status flag (MBX_INTA3A21)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA3A2_2S : 1; /*!< [2..2] Sets or indicates interrupt status flag (MBX_INTA3A22)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA3A2_3S : 1; /*!< [3..3] Sets or indicates interrupt status flag (MBX_INTA3A23)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-A55 Core2.                   */
+            uint32_t : 28;
+        } MBXISETA3A2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MBXICLRA3A2;            /*!< (@ 0x00000D94) CA55 Core3 to CA55 Core2 Mailbox Interrupt Clear
+                                                *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t MBX_INTA3A2_0C : 1; /*!< [0..0] Clears or indicates interrupt status flag (MBX_INTA3A20)
+                                                *   of mailbox 0 from Cortex-A55 Core3 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA3A2_1C : 1; /*!< [1..1] Clears or indicates interrupt status flag (MBX_INTA3A21)
+                                                *   of mailbox 1 from Cortex-A55 Core3 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA3A2_2C : 1; /*!< [2..2] Clears or indicates interrupt status flag (MBX_INTA3A22)
+                                                *   of mailbox 2 from Cortex-A55 Core3 to Cortex-A55 Core2.                   */
+            __IOM uint32_t MBX_INTA3A2_3C : 1; /*!< [3..3] Clears or indicates interrupt status flag (MBX_INTA3A23)
+                                                *   of mailbox 3 from Cortex-A55 Core3 to Cortex-A55 Core2.                   */
+            uint32_t : 28;
+        } MBXICLRA3A2_b;
+    };
+} R_MBXSEM_Type;                               /*!< Size = 3480 (0xd98)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SHOSTIF                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_SHOSTIF (R_SHOSTIF)
+ */
+
+typedef struct                         /*!< (@ 0x80241000) R_SHOSTIF Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t CTRLR0;         /*!< (@ 0x00000000) CTRLR0                                                     */
+
+        struct
+        {
+            uint32_t             : 8;
+            __IOM uint32_t SCPH  : 1;  /*!< [8..8] SCPH                                                               */
+            __IOM uint32_t SCPOL : 1;  /*!< [9..9] SCPOL                                                              */
+            uint32_t             : 22;
+        } CTRLR0_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t ENR;            /*!< (@ 0x00000008) ENR                                                        */
+
+        struct
+        {
+            __IOM uint32_t ENABLE : 1; /*!< [0..0] ENABLE                                                             */
+            uint32_t              : 31;
+        } ENR_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t RXFBTR;         /*!< (@ 0x00000014) RXFBTR                                                     */
+
+        struct
+        {
+            __IOM uint32_t RXFBTL : 6; /*!< [5..0] RXFBTL                                                             */
+            uint32_t              : 26;
+        } RXFBTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TXFTLR;         /*!< (@ 0x00000018) TXFTLR                                                     */
+
+        struct
+        {
+            __IOM uint32_t TFT : 6;    /*!< [5..0] TFT                                                                */
+            uint32_t           : 26;
+        } TXFTLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RXFTLR;         /*!< (@ 0x0000001C) RXFTLR                                                     */
+
+        struct
+        {
+            __IOM uint32_t RFT : 6;    /*!< [5..0] RFT                                                                */
+            uint32_t           : 26;
+        } RXFTLR_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IM uint32_t SR;              /*!< (@ 0x00000028) SR                                                         */
+
+        struct
+        {
+            __IM uint32_t BUSY : 1;    /*!< [0..0] BUSY                                                               */
+            uint32_t           : 31;
+        } SR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IMR;            /*!< (@ 0x0000002C) IMR                                                        */
+
+        struct
+        {
+            __IOM uint32_t TXEIM  : 1; /*!< [0..0] TXEIM                                                              */
+            uint32_t              : 2;
+            __IOM uint32_t RXOIM  : 1; /*!< [3..3] RXOIM                                                              */
+            __IOM uint32_t RXFIM  : 1; /*!< [4..4] RXFIM                                                              */
+            uint32_t              : 2;
+            __IOM uint32_t TXUIM  : 1; /*!< [7..7] TXUIM                                                              */
+            __IOM uint32_t AHBEM  : 1; /*!< [8..8] AHBEM                                                              */
+            __IOM uint32_t SPIMEM : 1; /*!< [9..9] SPIMEM                                                             */
+            uint32_t              : 22;
+        } IMR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ISR;             /*!< (@ 0x00000030) ISR                                                        */
+
+        struct
+        {
+            __IM uint32_t TXEIS  : 1;  /*!< [0..0] TXEIS                                                              */
+            uint32_t             : 2;
+            __IM uint32_t RXOIS  : 1;  /*!< [3..3] RXOIS                                                              */
+            __IM uint32_t RXFIS  : 1;  /*!< [4..4] RXFIS                                                              */
+            uint32_t             : 2;
+            __IM uint32_t TXUIS  : 1;  /*!< [7..7] TXUIS                                                              */
+            __IM uint32_t AHBES  : 1;  /*!< [8..8] AHBES                                                              */
+            __IM uint32_t SPIMES : 1;  /*!< [9..9] SPIMES                                                             */
+            uint32_t             : 22;
+        } ISR_b;
+    };
+
+    union
+    {
+        __IM uint32_t RISR;            /*!< (@ 0x00000034) RISR                                                       */
+
+        struct
+        {
+            __IM uint32_t TXEIR  : 1;  /*!< [0..0] TXEIR                                                              */
+            uint32_t             : 2;
+            __IM uint32_t RXOIR  : 1;  /*!< [3..3] RXOIR                                                              */
+            __IM uint32_t RXFIR  : 1;  /*!< [4..4] RXFIR                                                              */
+            uint32_t             : 2;
+            __IM uint32_t TXUIR  : 1;  /*!< [7..7] TXUIR                                                              */
+            __IM uint32_t AHBER  : 1;  /*!< [8..8] AHBER                                                              */
+            __IM uint32_t SPIMER : 1;  /*!< [9..9] SPIMER                                                             */
+            uint32_t             : 22;
+        } RISR_b;
+    };
+
+    union
+    {
+        __IM uint32_t TXUICR;          /*!< (@ 0x00000038) TXUICR                                                     */
+
+        struct
+        {
+            __IM uint32_t TXUICR : 1;  /*!< [0..0] TXUICR                                                             */
+            uint32_t             : 31;
+        } TXUICR_b;
+    };
+
+    union
+    {
+        __IM uint32_t RXOICR;          /*!< (@ 0x0000003C) RXOICR                                                     */
+
+        struct
+        {
+            __IM uint32_t RXOICR : 1;  /*!< [0..0] RXOICR                                                             */
+            uint32_t             : 31;
+        } RXOICR_b;
+    };
+
+    union
+    {
+        __IM uint32_t SPIMECR;         /*!< (@ 0x00000040) SPIMECR                                                    */
+
+        struct
+        {
+            __IM uint32_t SPIMECR : 1; /*!< [0..0] SPIMECR                                                            */
+            uint32_t              : 31;
+        } SPIMECR_b;
+    };
+
+    union
+    {
+        __IM uint32_t AHBECR;          /*!< (@ 0x00000044) AHBECR                                                     */
+
+        struct
+        {
+            __IM uint32_t AHBECR : 1;  /*!< [0..0] AHBECR                                                             */
+            uint32_t             : 31;
+        } AHBECR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ICR;             /*!< (@ 0x00000048) ICR                                                        */
+
+        struct
+        {
+            __IM uint32_t ICR : 1;     /*!< [0..0] ICR                                                                */
+            uint32_t          : 31;
+        } ICR_b;
+    };
+} R_SHOSTIF_Type;                      /*!< Size = 76 (0x4c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSC_NS                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System Control for Non-safety region (R_SYSC_NS)
+ */
+
+typedef struct                              /*!< (@ 0x80280000) R_SYSC_NS Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t SCKCR;               /*!< (@ 0x00000000) System Clock Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t FSELXSPI0 : 3;   /*!< [2..0] Set the frequency of the clock provided to xSPI Unit
+                                             *   0 in combination with bit 6 (DIVSELXSPI0). The combination
+                                             *   is shown below.                                                           */
+            uint32_t                   : 3;
+            __IOM uint32_t DIVSELXSPI0 : 1; /*!< [6..6] Select the base clock to generate serial clock for xSPI
+                                             *   Unit 0                                                                    */
+            uint32_t                 : 1;
+            __IOM uint32_t FSELXSPI1 : 3;   /*!< [10..8] Set the frequency of the clock provided to xSPI Unit
+                                             *   1 in combination with bit 14 (DIVSELXSPI1).                               */
+            uint32_t                   : 3;
+            __IOM uint32_t DIVSELXSPI1 : 1; /*!< [14..14] Select the base clock to generate serial clock for
+                                             *   xSPI Unit 1                                                               */
+            uint32_t            : 1;
+            __IOM uint32_t CKIO : 3;        /*!< [18..16] Set the frequency of the external bus clock (CKIO)
+                                             *   and the clock supplied to BSC.                                            */
+            uint32_t                 : 1;
+            __IOM uint32_t FSELCANFD : 1;   /*!< [20..20] Select the frequency of the clock supplied to CANFD              */
+            __IOM uint32_t PHYSEL    : 1;   /*!< [21..21] Select the Ethernet PHY reference clock output (ETHn_REFCLK,
+                                             *   n = 0 to 3)                                                               */
+            __IOM uint32_t CLMASEL : 1;     /*!< [22..22] Select alternative clock when main clock abnormal oscillation
+                                             *   is detected in CLMA6                                                      */
+            uint32_t : 9;
+        } SCKCR_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t SCKCR3;               /*!< (@ 0x00000008) System Clock Control Register 3                            */
+
+        struct
+        {
+            __IOM uint32_t SPI0ASYNCSEL : 2; /*!< [1..0] SPI0ASYNCSEL                                                       */
+            __IOM uint32_t SPI1ASYNCSEL : 2; /*!< [3..2] SPI1ASYNCSEL                                                       */
+            __IOM uint32_t SPI2ASYNCSEL : 2; /*!< [5..4] SPI2ASYNCSEL                                                       */
+            __IOM uint32_t SCI0ASYNCSEL : 2; /*!< [7..6] SCI0ASYNCSEL                                                       */
+            __IOM uint32_t SCI1ASYNCSEL : 2; /*!< [9..8] SCI1ASYNCSEL                                                       */
+            __IOM uint32_t SCI2ASYNCSEL : 2; /*!< [11..10] SCI2ASYNCSEL                                                     */
+            __IOM uint32_t SCI3ASYNCSEL : 2; /*!< [13..12] SCI3ASYNCSEL                                                     */
+            __IOM uint32_t SCI4ASYNCSEL : 2; /*!< [15..14] SCI4ASYNCSEL                                                     */
+            uint32_t                    : 4;
+            __IOM uint32_t LCDCDIVSEL   : 4; /*!< [23..20] LCDCDIVSEL                                                       */
+            uint32_t                    : 8;
+        } SCKCR3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCKCR4;                 /*!< (@ 0x0000000C) System Clock Control Register 4                            */
+
+        struct
+        {
+            __IOM uint32_t SCIE0ASYNCSEL  : 2; /*!< [1..0] SCIE0ASYNCSEL                                                      */
+            __IOM uint32_t SCIE1ASYNCSEL  : 2; /*!< [3..2] SCIE1ASYNCSEL                                                      */
+            __IOM uint32_t SCIE2ASYNCSEL  : 2; /*!< [5..4] SCIE2ASYNCSEL                                                      */
+            __IOM uint32_t SCIE3ASYNCSEL  : 2; /*!< [7..6] SCIE3ASYNCSEL                                                      */
+            __IOM uint32_t SCIE4ASYNCSEL  : 2; /*!< [9..8] SCIE4ASYNCSEL                                                      */
+            __IOM uint32_t SCIE5ASYNCSEL  : 2; /*!< [11..10] SCIE5ASYNCSEL                                                    */
+            __IOM uint32_t SCIE6ASYNCSEL  : 2; /*!< [13..12] SCIE6ASYNCSEL                                                    */
+            __IOM uint32_t SCIE7ASYNCSEL  : 2; /*!< [15..14] SCIE7ASYNCSEL                                                    */
+            __IOM uint32_t SCIE8ASYNCSEL  : 2; /*!< [17..16] SCIE8ASYNCSEL                                                    */
+            __IOM uint32_t SCIE9ASYNCSEL  : 2; /*!< [19..18] SCIE9ASYNCSEL                                                    */
+            __IOM uint32_t SCIE10ASYNCSEL : 2; /*!< [21..20] SCIE10ASYNCSEL                                                   */
+            __IOM uint32_t SCIE11ASYNCSEL : 2; /*!< [23..22] SCIE11ASYNCSEL                                                   */
+            __IOM uint32_t ENCOUTCLK      : 1; /*!< [24..24] ENCOUTCLK                                                        */
+            uint32_t                      : 7;
+        } SCKCR4_b;
+    };
+    __IM uint32_t RESERVED1[124];
+
+    union
+    {
+        __IOM uint32_t RSTSR0;         /*!< (@ 0x00000200) Reset Status Register 0                                    */
+
+        struct
+        {
+            uint32_t              : 1;
+            __IOM uint32_t TRF    : 1; /*!< [1..1] RES# Pin Reset Detect Flag                                         */
+            __IOM uint32_t ERRF   : 1; /*!< [2..2] Error Reset Detect Flag                                            */
+            __IOM uint32_t SWRSF  : 1; /*!< [3..3] System Software Reset Detect Flag                                  */
+            __IOM uint32_t SWR0F  : 1; /*!< [4..4] Cortex-R52 CPU0 Software Reset Detect Flag                         */
+            __IOM uint32_t SWR1F  : 1; /*!< [5..5] Cortex-R52 CPU1 Software Reset Detect Flag                         */
+            __IOM uint32_t SWR55C : 1; /*!< [6..6] Cortex-A55 Cluster Software Reset Detect Flag                      */
+            __IOM uint32_t SWR550 : 1; /*!< [7..7] Cortex-A55 Core0 Software Reset Detect Flag                        */
+            __IOM uint32_t SWR551 : 1; /*!< [8..8] Cortex-A55 Core1 Software Reset Detect Flag                        */
+            __IOM uint32_t SWR552 : 1; /*!< [9..9] Cortex-A55 Core2 Software Reset Detect Flag                        */
+            __IOM uint32_t SWR553 : 1; /*!< [10..10] Cortex-A55 Core3 Software Reset Detect Flag                      */
+            uint32_t              : 21;
+        } RSTSR0_b;
+    };
+    __IM uint32_t RESERVED2[15];
+
+    union
+    {
+        __IOM uint32_t MRCTLA;         /*!< (@ 0x00000240) Module Reset Control Register A                            */
+
+        struct
+        {
+            uint32_t                : 4;
+            __IOM uint32_t MRCTLA04 : 1; /*!< [4..4] xSPI Unit 0 Reset Control                                          */
+            __IOM uint32_t MRCTLA05 : 1; /*!< [5..5] xSPI Unit 1 Reset Control                                          */
+            uint32_t                : 26;
+        } MRCTLA_b;
+    };
+    __IM uint32_t RESERVED3[3];
+
+    union
+    {
+        __IOM uint32_t MRCTLE;           /*!< (@ 0x00000250) Module Reset Control Register E                            */
+
+        struct
+        {
+            __IOM uint32_t MRCTLE00 : 1; /*!< [0..0] GMAC Unit 0 (PCLKH clock domain) Reset Control                     */
+            __IOM uint32_t MRCTLE01 : 1; /*!< [1..1] GMAC Unit 0 (PCLKM clock domain) Reset Control                     */
+            __IOM uint32_t MRCTLE02 : 1; /*!< [2..2] ETHSW Reset Control                                                */
+            __IOM uint32_t MRCTLE03 : 1; /*!< [3..3] ESC (Bus clock domain) Reset Control                               */
+            __IOM uint32_t MRCTLE04 : 1; /*!< [4..4] ESC (IP clock domain) Reset Control                                */
+            __IOM uint32_t MRCTLE05 : 1; /*!< [5..5] Ethernet Subsystem Register Reset Control                          */
+            __IOM uint32_t MRCTLE06 : 1; /*!< [6..6] MII Converter Reset Control                                        */
+            uint32_t                : 9;
+            __IOM uint32_t MRCTLE16 : 1; /*!< [16..16] GMAC Unit 1 (PCLKAH clock domain) Reset Control                  */
+            __IOM uint32_t MRCTLE17 : 1; /*!< [17..17] GMAC Unit 1 (PCLKAM clock domain) Reset Control                  */
+            __IOM uint32_t MRCTLE18 : 1; /*!< [18..18] GMAC Unit 2 (PCLKAH clock domain) Reset Control                  */
+            __IOM uint32_t MRCTLE19 : 1; /*!< [19..19] GMAC Unit 2 (PCLKAM clock domain) Reset Control                  */
+            uint32_t                : 12;
+        } MRCTLE_b;
+    };
+    __IM uint32_t RESERVED4[7];
+
+    union
+    {
+        __IOM uint32_t MRCTLM;         /*!< (@ 0x00000270) Module Reset Control Register M                            */
+
+        struct
+        {
+            uint32_t                : 8;
+            __IOM uint32_t MRCTLM8  : 1; /*!< [8..8] PCIE Reset Control                                                 */
+            uint32_t                : 7;
+            __IOM uint32_t MRCTLM16 : 1; /*!< [16..16] DDRSS (rst_n) Reset Control                                      */
+            __IOM uint32_t MRCTLM17 : 1; /*!< [17..17] DDRSS (PwrOkIn) Reset Control                                    */
+            __IOM uint32_t MRCTLM18 : 1; /*!< [18..18] DDRSS (Reset) Reset Control                                      */
+            __IOM uint32_t MRCTLM19 : 1; /*!< [19..19] DDRSS (axi0_ARESETn) Reset Control                               */
+            __IOM uint32_t MRCTLM20 : 1; /*!< [20..20] DDRSS (axi1_ARESETn) Reset Control                               */
+            __IOM uint32_t MRCTLM21 : 1; /*!< [21..21] DDRSS (axi2_ARESETn) Reset Control                               */
+            __IOM uint32_t MRCTLM22 : 1; /*!< [22..22] DDRSS (axi3_ARESETn) Reset Control                               */
+            __IOM uint32_t MRCTLM23 : 1; /*!< [23..23] DDRSS (axi4_ARESETn) Reset Control                               */
+            __IOM uint32_t MRCTLM24 : 1; /*!< [24..24] DDRSS (MC_PRESETn) Reset Control                                 */
+            __IOM uint32_t MRCTLM25 : 1; /*!< [25..25] DDRSS (PHY_PRESETn) Reset Control                                */
+            uint32_t                : 6;
+        } MRCTLM_b;
+    };
+    __IM uint32_t RESERVED5[35];
+
+    union
+    {
+        __IOM uint32_t MSTPCRA;           /*!< (@ 0x00000300) Module Stop Control Register A                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRA00 : 1; /*!< [0..0] BSC Module Stop                                                    */
+            uint32_t                 : 3;
+            __IOM uint32_t MSTPCRA04 : 1; /*!< [4..4] xSPI Unit 0 Module Stop                                            */
+            __IOM uint32_t MSTPCRA05 : 1; /*!< [5..5] xSPI Unit 1 Module Stop                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t MSTPCRA08 : 1; /*!< [8..8] SCI Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRA09 : 1; /*!< [9..9] SCI Unit 1 Module Stop                                             */
+            __IOM uint32_t MSTPCRA10 : 1; /*!< [10..10] SCI Unit 2 Module Stop                                           */
+            __IOM uint32_t MSTPCRA11 : 1; /*!< [11..11] SCI Unit 3 Module Stop                                           */
+            __IOM uint32_t MSTPCRA12 : 1; /*!< [12..12] SCI Unit 4 Module Stop                                           */
+            uint32_t                 : 3;
+            __IOM uint32_t MSTPCRA16 : 1; /*!< [16..16] SCIE Unit 0 Module Stop                                          */
+            __IOM uint32_t MSTPCRA17 : 1; /*!< [17..17] SCIE Unit 1 Module Stop                                          */
+            __IOM uint32_t MSTPCRA18 : 1; /*!< [18..18] SCIE Unit 2 Module Stop                                          */
+            __IOM uint32_t MSTPCRA19 : 1; /*!< [19..19] SCIE Unit 3 Module Stop                                          */
+            __IOM uint32_t MSTPCRA20 : 1; /*!< [20..20] SCIE Unit 4 Module Stop                                          */
+            __IOM uint32_t MSTPCRA21 : 1; /*!< [21..21] SCIE Unit 5 Module Stop                                          */
+            __IOM uint32_t MSTPCRA22 : 1; /*!< [22..22] SCIE Unit 6 Module Stop                                          */
+            __IOM uint32_t MSTPCRA23 : 1; /*!< [23..23] SCIE Unit 7 Module Stop                                          */
+            __IOM uint32_t MSTPCRA24 : 1; /*!< [24..24] SCIE Unit 8 Module Stop                                          */
+            __IOM uint32_t MSTPCRA25 : 1; /*!< [25..25] SCIE Unit 9 Module Stop                                          */
+            __IOM uint32_t MSTPCRA26 : 1; /*!< [26..26] SCIE Unit 10 Module Stop                                         */
+            __IOM uint32_t MSTPCRA27 : 1; /*!< [27..27] SCIE Unit 11 Module Stop                                         */
+            uint32_t                 : 4;
+        } MSTPCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRB;           /*!< (@ 0x00000304) Module Stop Control Register B                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRB00 : 1; /*!< [0..0] IIC Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRB01 : 1; /*!< [1..1] IIC Unit 1 Module Stop                                             */
+            uint32_t                 : 2;
+            __IOM uint32_t MSTPCRB04 : 1; /*!< [4..4] SPI Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRB05 : 1; /*!< [5..5] SPI Unit 1 Module Stop                                             */
+            __IOM uint32_t MSTPCRB06 : 1; /*!< [6..6] SPI Unit 2 Module Stop                                             */
+            uint32_t                 : 25;
+        } MSTPCRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRC;           /*!< (@ 0x00000308) Module Stop Control Register C                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRC00 : 1; /*!< [0..0] MTU3 Module Stop                                                   */
+            __IOM uint32_t MSTPCRC01 : 1; /*!< [1..1] GPT Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRC02 : 1; /*!< [2..2] GPT Unit 1 Module Stop                                             */
+            uint32_t                 : 2;
+            __IOM uint32_t MSTPCRC05 : 1; /*!< [5..5] TFU Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRC06 : 1; /*!< [6..6] ADC12 Unit 0 Module Stop                                           */
+            __IOM uint32_t MSTPCRC07 : 1; /*!< [7..7] ADC12 Unit 1 Module Stop                                           */
+            uint32_t                 : 8;
+            __IOM uint32_t MSTPCRC16 : 1; /*!< [16..16] MSTPCRC16                                                        */
+            __IOM uint32_t MSTPCRC17 : 1; /*!< [17..17] MSTPCRC17                                                        */
+            __IOM uint32_t MSTPCRC18 : 1; /*!< [18..18] MSTPCRC18                                                        */
+            __IOM uint32_t MSTPCRC19 : 1; /*!< [19..19] MSTPCRC19                                                        */
+            __IOM uint32_t MSTPCRC20 : 1; /*!< [20..20] MSTPCRC20                                                        */
+            __IOM uint32_t MSTPCRC21 : 1; /*!< [21..21] MSTPCRC21                                                        */
+            __IOM uint32_t MSTPCRC22 : 1; /*!< [22..22] MSTPCRC22                                                        */
+            __IOM uint32_t MSTPCRC23 : 1; /*!< [23..23] MSTPCRC23                                                        */
+            __IOM uint32_t MSTPCRC24 : 1; /*!< [24..24] MSTPCRC24                                                        */
+            __IOM uint32_t MSTPCRC25 : 1; /*!< [25..25] MSTPCRC25                                                        */
+            uint32_t                 : 6;
+        } MSTPCRC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRD;           /*!< (@ 0x0000030C) Module Stop Control Register D                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRD00 : 1; /*!< [0..0] DSMIF Unit 0 Module Stop                                           */
+            __IOM uint32_t MSTPCRD01 : 1; /*!< [1..1] DSMIF Unit 1 Module Stop                                           */
+            __IOM uint32_t MSTPCRD02 : 1; /*!< [2..2] CMT Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRD03 : 1; /*!< [3..3] CMT Unit 1 Module Stop                                             */
+            __IOM uint32_t MSTPCRD04 : 1; /*!< [4..4] CMT Unit 2 Module Stop                                             */
+            __IOM uint32_t MSTPCRD05 : 1; /*!< [5..5] CMTW Unit 0 Module Stop                                            */
+            __IOM uint32_t MSTPCRD06 : 1; /*!< [6..6] CMTW Unit 1 Module Stop                                            */
+            __IOM uint32_t MSTPCRD07 : 1; /*!< [7..7] TSU Module Stop                                                    */
+            __IOM uint32_t MSTPCRD08 : 1; /*!< [8..8] DOC Module Stop                                                    */
+            __IOM uint32_t MSTPCRD09 : 1; /*!< [9..9] CRC Unit 0 Module Stop                                             */
+            __IOM uint32_t MSTPCRD10 : 1; /*!< [10..10] CANFD Module Stop                                                */
+            __IOM uint32_t MSTPCRD11 : 1; /*!< [11..11] CKIO Module Stop                                                 */
+            uint32_t                 : 4;
+            __IOM uint32_t MSTPCRD16 : 1; /*!< [16..16] DSMIF Unit 2 Module Stop                                         */
+            __IOM uint32_t MSTPCRD17 : 1; /*!< [17..17] DSMIF Unit 3 Module Stop                                         */
+            __IOM uint32_t MSTPCRD18 : 1; /*!< [18..18] DSMIF Unit 4 Module Stop                                         */
+            __IOM uint32_t MSTPCRD19 : 1; /*!< [19..19] DSMIF Unit 5 Module Stop                                         */
+            __IOM uint32_t MSTPCRD20 : 1; /*!< [20..20] DSMIF Unit 6 Module Stop                                         */
+            __IOM uint32_t MSTPCRD21 : 1; /*!< [21..21] DSMIF Unit 7 Module Stop                                         */
+            __IOM uint32_t MSTPCRD22 : 1; /*!< [22..22] DSMIF Unit 8 Module Stop                                         */
+            __IOM uint32_t MSTPCRD23 : 1; /*!< [23..23] DSMIF Unit 9 Module Stop                                         */
+            uint32_t                 : 8;
+        } MSTPCRD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRE;           /*!< (@ 0x00000310) Module Stop Control Register E                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRE00 : 1; /*!< [0..0] GMAC Unit 0 Module Stop                                            */
+            __IOM uint32_t MSTPCRE01 : 1; /*!< [1..1] ETHSW Module Stop                                                  */
+            __IOM uint32_t MSTPCRE02 : 1; /*!< [2..2] ESC Module Stop                                                    */
+            __IOM uint32_t MSTPCRE03 : 1; /*!< [3..3] Ethernet Subsystem Register Module Stop                            */
+            uint32_t                 : 4;
+            __IOM uint32_t MSTPCRE08 : 1; /*!< [8..8] USB Module Stop                                                    */
+            uint32_t                 : 7;
+            __IOM uint32_t MSTPCRE16 : 1; /*!< [16..16] GMAC Unit 1 Module Stop                                          */
+            __IOM uint32_t MSTPCRE17 : 1; /*!< [17..17] GMAC Unit 2 Module Stop                                          */
+            uint32_t                 : 14;
+        } MSTPCRE_b;
+    };
+    __IM uint32_t RESERVED6[4];
+
+    union
+    {
+        __IOM uint32_t MSTPCRJ;           /*!< (@ 0x00000324) Module Stop Control Register J                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRJ00 : 1; /*!< [0..0] AFMT Unit 0 Module Stop                                            */
+            __IOM uint32_t MSTPCRJ01 : 1; /*!< [1..1] HDSL Unit 0 Module Stop                                            */
+            __IOM uint32_t MSTPCRJ02 : 1; /*!< [2..2] BISS Unit 0 Module Stop                                            */
+            __IOM uint32_t MSTPCRJ03 : 1; /*!< [3..3] ENDAT Unit 0 Module Stop                                           */
+            __IOM uint32_t MSTPCRJ04 : 1; /*!< [4..4] AFMT Unit 1 Module Stop                                            */
+            __IOM uint32_t MSTPCRJ05 : 1; /*!< [5..5] HDSL Unit 1 Module Stop                                            */
+            __IOM uint32_t MSTPCRJ06 : 1; /*!< [6..6] BISS Unit 1 Module Stop                                            */
+            __IOM uint32_t MSTPCRJ07 : 1; /*!< [7..7] ENDAT Unit 1 Module Stop                                           */
+            __IOM uint32_t MSTPCRJ08 : 1; /*!< [8..8] AFMT Unit 2 Module Stop                                            */
+            __IOM uint32_t MSTPCRJ09 : 1; /*!< [9..9] HDSL Unit 2 Module Stop                                            */
+            __IOM uint32_t MSTPCRJ10 : 1; /*!< [10..10] BISS Unit 2 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ11 : 1; /*!< [11..11] ENDAT Unit 2 Module Stop                                         */
+            __IOM uint32_t MSTPCRJ12 : 1; /*!< [12..12] AFMT Unit 3 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ13 : 1; /*!< [13..13] HDSL Unit 3 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ14 : 1; /*!< [14..14] BISS Unit 3 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ15 : 1; /*!< [15..15] ENDAT Unit 3 Module Stop                                         */
+            __IOM uint32_t MSTPCRJ16 : 1; /*!< [16..16] AFMT Unit 4 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ17 : 1; /*!< [17..17] HDSL Unit 4 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ18 : 1; /*!< [18..18] BISS Unit 4 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ19 : 1; /*!< [19..19] ENDAT Unit 4 Module Stop                                         */
+            __IOM uint32_t MSTPCRJ20 : 1; /*!< [20..20] AFMT Unit 5 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ21 : 1; /*!< [21..21] HDSL Unit 5 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ22 : 1; /*!< [22..22] BISS Unit 5 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ23 : 1; /*!< [23..23] ENDAT Unit 5 Module Stop                                         */
+            __IOM uint32_t MSTPCRJ24 : 1; /*!< [24..24] AFMT Unit 6 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ25 : 1; /*!< [25..25] HDSL Unit 6 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ26 : 1; /*!< [26..26] BISS Unit 6 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ27 : 1; /*!< [27..27] ENDAT Unit 6 Module Stop                                         */
+            __IOM uint32_t MSTPCRJ28 : 1; /*!< [28..28] AFMT Unit 7 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ29 : 1; /*!< [29..29] HDSL Unit 7 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ30 : 1; /*!< [30..30] BISS Unit 7 Module Stop                                          */
+            __IOM uint32_t MSTPCRJ31 : 1; /*!< [31..31] ENDAT Unit 7 Module Stop                                         */
+        } MSTPCRJ_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRK;           /*!< (@ 0x00000328) Module Stop Control Register K                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRK00 : 1; /*!< [0..0] AFMT Unit 8 Module Stop                                            */
+            __IOM uint32_t MSTPCRK01 : 1; /*!< [1..1] HDSL Unit 8 Module Stop                                            */
+            __IOM uint32_t MSTPCRK02 : 1; /*!< [2..2] BISS Unit 8 Module Stop                                            */
+            __IOM uint32_t MSTPCRK03 : 1; /*!< [3..3] ENDAT Unit 8 Module Stop                                           */
+            __IOM uint32_t MSTPCRK04 : 1; /*!< [4..4] AFMT Unit 9 Module Stop                                            */
+            __IOM uint32_t MSTPCRK05 : 1; /*!< [5..5] HDSL Unit 9 Module Stop                                            */
+            __IOM uint32_t MSTPCRK06 : 1; /*!< [6..6] BISS Unit 9 Module Stop                                            */
+            __IOM uint32_t MSTPCRK07 : 1; /*!< [7..7] ENDAT Unit 9 Module Stop                                           */
+            __IOM uint32_t MSTPCRK08 : 1; /*!< [8..8] AFMT Unit 10 Module Stop                                           */
+            __IOM uint32_t MSTPCRK09 : 1; /*!< [9..9] HDSL Unit 10 Module Stop                                           */
+            __IOM uint32_t MSTPCRK10 : 1; /*!< [10..10] BISS Unit 10 Module Stop                                         */
+            __IOM uint32_t MSTPCRK11 : 1; /*!< [11..11] ENDAT Unit 10 Module Stop                                        */
+            __IOM uint32_t MSTPCRK12 : 1; /*!< [12..12] AFMT Unit 11 Module Stop                                         */
+            __IOM uint32_t MSTPCRK13 : 1; /*!< [13..13] HDSL Unit 11 Module Stop                                         */
+            __IOM uint32_t MSTPCRK14 : 1; /*!< [14..14] BISS Unit 11 Module Stop                                         */
+            __IOM uint32_t MSTPCRK15 : 1; /*!< [15..15] ENDAT Unit 11 Module Stop                                        */
+            __IOM uint32_t MSTPCRK16 : 1; /*!< [16..16] AFMT Unit 12 Module Stop                                         */
+            __IOM uint32_t MSTPCRK17 : 1; /*!< [17..17] HDSL Unit 12 Module Stop                                         */
+            __IOM uint32_t MSTPCRK18 : 1; /*!< [18..18] BISS Unit 12 Module Stop                                         */
+            __IOM uint32_t MSTPCRK19 : 1; /*!< [19..19] ENDAT Unit 12 Module Stop                                        */
+            __IOM uint32_t MSTPCRK20 : 1; /*!< [20..20] AFMT Unit 13 Module Stop                                         */
+            __IOM uint32_t MSTPCRK21 : 1; /*!< [21..21] HDSL Unit 13 Module Stop                                         */
+            __IOM uint32_t MSTPCRK22 : 1; /*!< [22..22] BISS Unit 13 Module Stop                                         */
+            __IOM uint32_t MSTPCRK23 : 1; /*!< [23..23] ENDAT Unit 13 Module Stop                                        */
+            __IOM uint32_t MSTPCRK24 : 1; /*!< [24..24] AFMT Unit 14 Module Stop                                         */
+            __IOM uint32_t MSTPCRK25 : 1; /*!< [25..25] HDSL Unit 14 Module Stop                                         */
+            __IOM uint32_t MSTPCRK26 : 1; /*!< [26..26] BISS Unit 14 Module Stop                                         */
+            __IOM uint32_t MSTPCRK27 : 1; /*!< [27..27] ENDAT Unit 14 Module Stop                                        */
+            __IOM uint32_t MSTPCRK28 : 1; /*!< [28..28] AFMT Unit 15 Module Stop                                         */
+            __IOM uint32_t MSTPCRK29 : 1; /*!< [29..29] HDSL Unit 15 Module Stop                                         */
+            __IOM uint32_t MSTPCRK30 : 1; /*!< [30..30] BISS Unit 15 Module Stop                                         */
+            __IOM uint32_t MSTPCRK31 : 1; /*!< [31..31] ENDAT Unit 15 Module Stop                                        */
+        } MSTPCRK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRL;           /*!< (@ 0x0000032C) Module Stop Control Register L                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRL00 : 1; /*!< [0..0] ENCOUT Module Stop                                                 */
+            uint32_t                 : 31;
+        } MSTPCRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRM;           /*!< (@ 0x00000330) Module Stop Control Register M                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRM00 : 1; /*!< [0..0] DDRSS Module Stop                                                  */
+            uint32_t                 : 3;
+            __IOM uint32_t MSTPCRM04 : 1; /*!< [4..4] LCDC Module Stop                                                   */
+            uint32_t                 : 3;
+            __IOM uint32_t MSTPCRM08 : 1; /*!< [8..8] PCIE Module Stop                                                   */
+            uint32_t                 : 3;
+            __IOM uint32_t MSTPCRM12 : 1; /*!< [12..12] SDHI Unit 0 Module Stop                                          */
+            __IOM uint32_t MSTPCRM13 : 1; /*!< [13..13] SDHI Unit 1 Module Stop                                          */
+            uint32_t                 : 18;
+        } MSTPCRM_b;
+    };
+} R_SYSC_NS_Type;                         /*!< Size = 820 (0x334)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELO                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Event Link Option Setting (R_ELO)
+ */
+
+typedef struct                         /*!< (@ 0x80290000) R_ELO Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t ELOPA;          /*!< (@ 0x00000000) Event Link Option Setting Register A                       */
+
+        struct
+        {
+            __IOM uint32_t MTU0MD : 2; /*!< [1..0] MTU0 Operation Select                                              */
+            uint32_t              : 4;
+            __IOM uint32_t MTU3MD : 2; /*!< [7..6] MTU3 Operation Select                                              */
+            uint32_t              : 24;
+        } ELOPA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ELOPB;          /*!< (@ 0x00000004) Event Link Option Setting Register B                       */
+
+        struct
+        {
+            __IOM uint32_t MTU4MD : 2; /*!< [1..0] MTU4 Operation Select                                              */
+            uint32_t              : 30;
+        } ELOPB_b;
+    };
+} R_ELO_Type;                          /*!< Size = 8 (0x8)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_IC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Input Capture Selection (R_GPT_IC)
+ */
+
+typedef struct                            /*!< (@ 0x80290008) R_GPT_IC Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t GTIOCSEL;          /*!< (@ 0x00000000) General PWM Timer Input Capture Signal Select
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t GT00_ISEL : 1; /*!< [0..0] GT00_ISEL                                                          */
+            __IOM uint32_t GT01_ISEL : 1; /*!< [1..1] GT01_ISEL                                                          */
+            __IOM uint32_t GT02_ISEL : 1; /*!< [2..2] GT02_ISEL                                                          */
+            __IOM uint32_t GT03_ISEL : 1; /*!< [3..3] GT03_ISEL                                                          */
+            __IOM uint32_t GT04_ISEL : 1; /*!< [4..4] GT04_ISEL                                                          */
+            __IOM uint32_t GT05_ISEL : 1; /*!< [5..5] GT05_ISEL                                                          */
+            __IOM uint32_t GT06_ISEL : 1; /*!< [6..6] GT06_ISEL                                                          */
+            __IOM uint32_t GT07_ISEL : 1; /*!< [7..7] GT07_ISEL                                                          */
+            __IOM uint32_t GT08_ISEL : 1; /*!< [8..8] GT08_ISEL                                                          */
+            uint32_t                 : 23;
+        } GTIOCSEL_b;
+    };
+} R_GPT_IC_Type;                          /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ENCSS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Encoder Interface Subsystem (R_ENCSS)
+ */
+
+typedef struct                              /*!< (@ 0x80291000) R_ENCSS Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t ENCODER_CFG0;        /*!< (@ 0x00000000) Encoder IF Configuration Register 0                        */
+
+        struct
+        {
+            __IOM uint32_t HF0ENDIAN   : 1; /*!< [0..0] HIPERFACE DSL Unit 2*n Endian Mode                                 */
+            __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 2*n Safe 1 Interface Select                     */
+            __IOM uint32_t EVTSRC0     : 1; /*!< [2..2] Event Source Select                                                */
+            __IOM uint32_t SS0SEL      : 2; /*!< [4..3] Encoder Interface Port Select                                      */
+            __IOM uint32_t TRGSEL0     : 1; /*!< [5..5] EnDat 2.2 Unit 2*n Trigger Output Source Select                    */
+            __IOM uint32_t HF0SAFE2SEL : 1; /*!< [6..6] HIPERFACE DSL Unit 2*n Safe 2 Interface Select                     */
+            __IOM uint32_t SS0SYNCSEL  : 4; /*!< [10..7] Event Source Unit Number Select                                   */
+            uint32_t                   : 5;
+            __IOM uint32_t HF1ENDIAN   : 1; /*!< [16..16] HIPERFACE DSL Unit 2*n+1 Endian Mode                             */
+            __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 2*n+1 Safe 1 Interface Select                 */
+            __IOM uint32_t EVTSRC1     : 1; /*!< [18..18] Event Source Select                                              */
+            __IOM uint32_t SS1SEL      : 2; /*!< [20..19] Encoder Interface Port Select                                    */
+            __IOM uint32_t TRGSEL1     : 1; /*!< [21..21] EnDat 2.2 Unit 2*n+1 Trigger Output Source Select                */
+            __IOM uint32_t HF1SAFE2SEL : 1; /*!< [22..22] HIPERFACE DSL Unit 2*n+1 Safe 2 Interface Select                 */
+            __IOM uint32_t SS1SYNCSEL  : 4; /*!< [26..23] Event Source Unit Number Select                                  */
+            uint32_t                   : 5;
+        } ENCODER_CFG0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENCODER_CFG1;        /*!< (@ 0x00000004) Encoder IF Configuration Register 1                        */
+
+        struct
+        {
+            __IOM uint32_t HF0ENDIAN   : 1; /*!< [0..0] HIPERFACE DSL Unit 2*n Endian Mode                                 */
+            __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 2*n Safe 1 Interface Select                     */
+            __IOM uint32_t EVTSRC0     : 1; /*!< [2..2] Event Source Select                                                */
+            __IOM uint32_t SS0SEL      : 2; /*!< [4..3] Encoder Interface Port Select                                      */
+            __IOM uint32_t TRGSEL0     : 1; /*!< [5..5] EnDat 2.2 Unit 2*n Trigger Output Source Select                    */
+            __IOM uint32_t HF0SAFE2SEL : 1; /*!< [6..6] HIPERFACE DSL Unit 2*n Safe 2 Interface Select                     */
+            __IOM uint32_t SS0SYNCSEL  : 4; /*!< [10..7] Event Source Unit Number Select                                   */
+            uint32_t                   : 5;
+            __IOM uint32_t HF1ENDIAN   : 1; /*!< [16..16] HIPERFACE DSL Unit 2*n+1 Endian Mode                             */
+            __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 2*n+1 Safe 1 Interface Select                 */
+            __IOM uint32_t EVTSRC1     : 1; /*!< [18..18] Event Source Select                                              */
+            __IOM uint32_t SS1SEL      : 2; /*!< [20..19] Encoder Interface Port Select                                    */
+            __IOM uint32_t TRGSEL1     : 1; /*!< [21..21] EnDat 2.2 Unit 2*n+1 Trigger Output Source Select                */
+            __IOM uint32_t HF1SAFE2SEL : 1; /*!< [22..22] HIPERFACE DSL Unit 2*n+1 Safe 2 Interface Select                 */
+            __IOM uint32_t SS1SYNCSEL  : 4; /*!< [26..23] Event Source Unit Number Select                                  */
+            uint32_t                   : 5;
+        } ENCODER_CFG1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENCODER_CFG2;        /*!< (@ 0x00000008) Encoder IF Configuration Register 2                        */
+
+        struct
+        {
+            __IOM uint32_t HF0ENDIAN   : 1; /*!< [0..0] HIPERFACE DSL Unit 2*n Endian Mode                                 */
+            __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 2*n Safe 1 Interface Select                     */
+            __IOM uint32_t EVTSRC0     : 1; /*!< [2..2] Event Source Select                                                */
+            __IOM uint32_t SS0SEL      : 2; /*!< [4..3] Encoder Interface Port Select                                      */
+            __IOM uint32_t TRGSEL0     : 1; /*!< [5..5] EnDat 2.2 Unit 2*n Trigger Output Source Select                    */
+            __IOM uint32_t HF0SAFE2SEL : 1; /*!< [6..6] HIPERFACE DSL Unit 2*n Safe 2 Interface Select                     */
+            __IOM uint32_t SS0SYNCSEL  : 4; /*!< [10..7] Event Source Unit Number Select                                   */
+            uint32_t                   : 5;
+            __IOM uint32_t HF1ENDIAN   : 1; /*!< [16..16] HIPERFACE DSL Unit 2*n+1 Endian Mode                             */
+            __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 2*n+1 Safe 1 Interface Select                 */
+            __IOM uint32_t EVTSRC1     : 1; /*!< [18..18] Event Source Select                                              */
+            __IOM uint32_t SS1SEL      : 2; /*!< [20..19] Encoder Interface Port Select                                    */
+            __IOM uint32_t TRGSEL1     : 1; /*!< [21..21] EnDat 2.2 Unit 2*n+1 Trigger Output Source Select                */
+            __IOM uint32_t HF1SAFE2SEL : 1; /*!< [22..22] HIPERFACE DSL Unit 2*n+1 Safe 2 Interface Select                 */
+            __IOM uint32_t SS1SYNCSEL  : 4; /*!< [26..23] Event Source Unit Number Select                                  */
+            uint32_t                   : 5;
+        } ENCODER_CFG2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENCODER_CFG3;        /*!< (@ 0x0000000C) Encoder IF Configuration Register 3                        */
+
+        struct
+        {
+            __IOM uint32_t HF0ENDIAN   : 1; /*!< [0..0] HIPERFACE DSL Unit 2*n Endian Mode                                 */
+            __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 2*n Safe 1 Interface Select                     */
+            __IOM uint32_t EVTSRC0     : 1; /*!< [2..2] Event Source Select                                                */
+            __IOM uint32_t SS0SEL      : 2; /*!< [4..3] Encoder Interface Port Select                                      */
+            __IOM uint32_t TRGSEL0     : 1; /*!< [5..5] EnDat 2.2 Unit 2*n Trigger Output Source Select                    */
+            __IOM uint32_t HF0SAFE2SEL : 1; /*!< [6..6] HIPERFACE DSL Unit 2*n Safe 2 Interface Select                     */
+            __IOM uint32_t SS0SYNCSEL  : 4; /*!< [10..7] Event Source Unit Number Select                                   */
+            uint32_t                   : 5;
+            __IOM uint32_t HF1ENDIAN   : 1; /*!< [16..16] HIPERFACE DSL Unit 2*n+1 Endian Mode                             */
+            __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 2*n+1 Safe 1 Interface Select                 */
+            __IOM uint32_t EVTSRC1     : 1; /*!< [18..18] Event Source Select                                              */
+            __IOM uint32_t SS1SEL      : 2; /*!< [20..19] Encoder Interface Port Select                                    */
+            __IOM uint32_t TRGSEL1     : 1; /*!< [21..21] EnDat 2.2 Unit 2*n+1 Trigger Output Source Select                */
+            __IOM uint32_t HF1SAFE2SEL : 1; /*!< [22..22] HIPERFACE DSL Unit 2*n+1 Safe 2 Interface Select                 */
+            __IOM uint32_t SS1SYNCSEL  : 4; /*!< [26..23] Event Source Unit Number Select                                  */
+            uint32_t                   : 5;
+        } ENCODER_CFG3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENCODER_CFG4;        /*!< (@ 0x00000010) Encoder IF Configuration Register 4                        */
+
+        struct
+        {
+            __IOM uint32_t HF0ENDIAN   : 1; /*!< [0..0] HIPERFACE DSL Unit 2*n Endian Mode                                 */
+            __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 2*n Safe 1 Interface Select                     */
+            __IOM uint32_t EVTSRC0     : 1; /*!< [2..2] Event Source Select                                                */
+            __IOM uint32_t SS0SEL      : 2; /*!< [4..3] Encoder Interface Port Select                                      */
+            __IOM uint32_t TRGSEL0     : 1; /*!< [5..5] EnDat 2.2 Unit 2*n Trigger Output Source Select                    */
+            __IOM uint32_t HF0SAFE2SEL : 1; /*!< [6..6] HIPERFACE DSL Unit 2*n Safe 2 Interface Select                     */
+            __IOM uint32_t SS0SYNCSEL  : 4; /*!< [10..7] Event Source Unit Number Select                                   */
+            uint32_t                   : 5;
+            __IOM uint32_t HF1ENDIAN   : 1; /*!< [16..16] HIPERFACE DSL Unit 2*n+1 Endian Mode                             */
+            __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 2*n+1 Safe 1 Interface Select                 */
+            __IOM uint32_t EVTSRC1     : 1; /*!< [18..18] Event Source Select                                              */
+            __IOM uint32_t SS1SEL      : 2; /*!< [20..19] Encoder Interface Port Select                                    */
+            __IOM uint32_t TRGSEL1     : 1; /*!< [21..21] EnDat 2.2 Unit 2*n+1 Trigger Output Source Select                */
+            __IOM uint32_t HF1SAFE2SEL : 1; /*!< [22..22] HIPERFACE DSL Unit 2*n+1 Safe 2 Interface Select                 */
+            __IOM uint32_t SS1SYNCSEL  : 4; /*!< [26..23] Event Source Unit Number Select                                  */
+            uint32_t                   : 5;
+        } ENCODER_CFG4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENCODER_CFG5;        /*!< (@ 0x00000014) Encoder IF Configuration Register 5                        */
+
+        struct
+        {
+            __IOM uint32_t HF0ENDIAN   : 1; /*!< [0..0] HIPERFACE DSL Unit 2*n Endian Mode                                 */
+            __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 2*n Safe 1 Interface Select                     */
+            __IOM uint32_t EVTSRC0     : 1; /*!< [2..2] Event Source Select                                                */
+            __IOM uint32_t SS0SEL      : 2; /*!< [4..3] Encoder Interface Port Select                                      */
+            __IOM uint32_t TRGSEL0     : 1; /*!< [5..5] EnDat 2.2 Unit 2*n Trigger Output Source Select                    */
+            __IOM uint32_t HF0SAFE2SEL : 1; /*!< [6..6] HIPERFACE DSL Unit 2*n Safe 2 Interface Select                     */
+            __IOM uint32_t SS0SYNCSEL  : 4; /*!< [10..7] Event Source Unit Number Select                                   */
+            uint32_t                   : 5;
+            __IOM uint32_t HF1ENDIAN   : 1; /*!< [16..16] HIPERFACE DSL Unit 2*n+1 Endian Mode                             */
+            __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 2*n+1 Safe 1 Interface Select                 */
+            __IOM uint32_t EVTSRC1     : 1; /*!< [18..18] Event Source Select                                              */
+            __IOM uint32_t SS1SEL      : 2; /*!< [20..19] Encoder Interface Port Select                                    */
+            __IOM uint32_t TRGSEL1     : 1; /*!< [21..21] EnDat 2.2 Unit 2*n+1 Trigger Output Source Select                */
+            __IOM uint32_t HF1SAFE2SEL : 1; /*!< [22..22] HIPERFACE DSL Unit 2*n+1 Safe 2 Interface Select                 */
+            __IOM uint32_t SS1SYNCSEL  : 4; /*!< [26..23] Event Source Unit Number Select                                  */
+            uint32_t                   : 5;
+        } ENCODER_CFG5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENCODER_CFG6;        /*!< (@ 0x00000018) Encoder IF Configuration Register 6                        */
+
+        struct
+        {
+            __IOM uint32_t HF0ENDIAN   : 1; /*!< [0..0] HIPERFACE DSL Unit 2*n Endian Mode                                 */
+            __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 2*n Safe 1 Interface Select                     */
+            __IOM uint32_t EVTSRC0     : 1; /*!< [2..2] Event Source Select                                                */
+            __IOM uint32_t SS0SEL      : 2; /*!< [4..3] Encoder Interface Port Select                                      */
+            __IOM uint32_t TRGSEL0     : 1; /*!< [5..5] EnDat 2.2 Unit 2*n Trigger Output Source Select                    */
+            __IOM uint32_t HF0SAFE2SEL : 1; /*!< [6..6] HIPERFACE DSL Unit 2*n Safe 2 Interface Select                     */
+            __IOM uint32_t SS0SYNCSEL  : 4; /*!< [10..7] Event Source Unit Number Select                                   */
+            uint32_t                   : 5;
+            __IOM uint32_t HF1ENDIAN   : 1; /*!< [16..16] HIPERFACE DSL Unit 2*n+1 Endian Mode                             */
+            __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 2*n+1 Safe 1 Interface Select                 */
+            __IOM uint32_t EVTSRC1     : 1; /*!< [18..18] Event Source Select                                              */
+            __IOM uint32_t SS1SEL      : 2; /*!< [20..19] Encoder Interface Port Select                                    */
+            __IOM uint32_t TRGSEL1     : 1; /*!< [21..21] EnDat 2.2 Unit 2*n+1 Trigger Output Source Select                */
+            __IOM uint32_t HF1SAFE2SEL : 1; /*!< [22..22] HIPERFACE DSL Unit 2*n+1 Safe 2 Interface Select                 */
+            __IOM uint32_t SS1SYNCSEL  : 4; /*!< [26..23] Event Source Unit Number Select                                  */
+            uint32_t                   : 5;
+        } ENCODER_CFG6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENCODER_CFG7;        /*!< (@ 0x0000001C) Encoder IF Configuration Register 7                        */
+
+        struct
+        {
+            __IOM uint32_t HF0ENDIAN   : 1; /*!< [0..0] HIPERFACE DSL Unit 2*n Endian Mode                                 */
+            __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 2*n Safe 1 Interface Select                     */
+            __IOM uint32_t EVTSRC0     : 1; /*!< [2..2] Event Source Select                                                */
+            __IOM uint32_t SS0SEL      : 2; /*!< [4..3] Encoder Interface Port Select                                      */
+            __IOM uint32_t TRGSEL0     : 1; /*!< [5..5] EnDat 2.2 Unit 2*n Trigger Output Source Select                    */
+            __IOM uint32_t HF0SAFE2SEL : 1; /*!< [6..6] HIPERFACE DSL Unit 2*n Safe 2 Interface Select                     */
+            __IOM uint32_t SS0SYNCSEL  : 4; /*!< [10..7] Event Source Unit Number Select                                   */
+            uint32_t                   : 5;
+            __IOM uint32_t HF1ENDIAN   : 1; /*!< [16..16] HIPERFACE DSL Unit 2*n+1 Endian Mode                             */
+            __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 2*n+1 Safe 1 Interface Select                 */
+            __IOM uint32_t EVTSRC1     : 1; /*!< [18..18] Event Source Select                                              */
+            __IOM uint32_t SS1SEL      : 2; /*!< [20..19] Encoder Interface Port Select                                    */
+            __IOM uint32_t TRGSEL1     : 1; /*!< [21..21] EnDat 2.2 Unit 2*n+1 Trigger Output Source Select                */
+            __IOM uint32_t HF1SAFE2SEL : 1; /*!< [22..22] HIPERFACE DSL Unit 2*n+1 Safe 2 Interface Select                 */
+            __IOM uint32_t SS1SYNCSEL  : 4; /*!< [26..23] Event Source Unit Number Select                                  */
+            uint32_t                   : 5;
+        } ENCODER_CFG7_b;
+    };
+
+    union
+    {
+        __IM uint32_t BISS_STAT0;        /*!< (@ 0x00000020) BiSS-C Status Register 0                                   */
+
+        struct
+        {
+            __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 2*n Error                                              */
+            uint32_t                : 3;
+            __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 2*n                           */
+            uint32_t                : 11;
+            __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 2*n+1 Error                                          */
+            uint32_t                : 3;
+            __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 2*n+1                       */
+            uint32_t                : 11;
+        } BISS_STAT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t BISS_STAT1;        /*!< (@ 0x00000024) BiSS-C Status Register 1                                   */
+
+        struct
+        {
+            __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 2*n Error                                              */
+            uint32_t                : 3;
+            __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 2*n                           */
+            uint32_t                : 11;
+            __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 2*n+1 Error                                          */
+            uint32_t                : 3;
+            __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 2*n+1                       */
+            uint32_t                : 11;
+        } BISS_STAT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t BISS_STAT2;        /*!< (@ 0x00000028) BiSS-C Status Register 2                                   */
+
+        struct
+        {
+            __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 2*n Error                                              */
+            uint32_t                : 3;
+            __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 2*n                           */
+            uint32_t                : 11;
+            __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 2*n+1 Error                                          */
+            uint32_t                : 3;
+            __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 2*n+1                       */
+            uint32_t                : 11;
+        } BISS_STAT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t BISS_STAT3;        /*!< (@ 0x0000002C) BiSS-C Status Register 3                                   */
+
+        struct
+        {
+            __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 2*n Error                                              */
+            uint32_t                : 3;
+            __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 2*n                           */
+            uint32_t                : 11;
+            __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 2*n+1 Error                                          */
+            uint32_t                : 3;
+            __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 2*n+1                       */
+            uint32_t                : 11;
+        } BISS_STAT3_b;
+    };
+
+    union
+    {
+        __IM uint32_t BISS_STAT4;        /*!< (@ 0x00000030) BiSS-C Status Register 4                                   */
+
+        struct
+        {
+            __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 2*n Error                                              */
+            uint32_t                : 3;
+            __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 2*n                           */
+            uint32_t                : 11;
+            __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 2*n+1 Error                                          */
+            uint32_t                : 3;
+            __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 2*n+1                       */
+            uint32_t                : 11;
+        } BISS_STAT4_b;
+    };
+
+    union
+    {
+        __IM uint32_t BISS_STAT5;        /*!< (@ 0x00000034) BiSS-C Status Register 5                                   */
+
+        struct
+        {
+            __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 2*n Error                                              */
+            uint32_t                : 3;
+            __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 2*n                           */
+            uint32_t                : 11;
+            __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 2*n+1 Error                                          */
+            uint32_t                : 3;
+            __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 2*n+1                       */
+            uint32_t                : 11;
+        } BISS_STAT5_b;
+    };
+
+    union
+    {
+        __IM uint32_t BISS_STAT6;        /*!< (@ 0x00000038) BiSS-C Status Register 6                                   */
+
+        struct
+        {
+            __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 2*n Error                                              */
+            uint32_t                : 3;
+            __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 2*n                           */
+            uint32_t                : 11;
+            __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 2*n+1 Error                                          */
+            uint32_t                : 3;
+            __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 2*n+1                       */
+            uint32_t                : 11;
+        } BISS_STAT6_b;
+    };
+
+    union
+    {
+        __IM uint32_t BISS_STAT7;        /*!< (@ 0x0000003C) BiSS-C Status Register 7                                   */
+
+        struct
+        {
+            __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 2*n Error                                              */
+            uint32_t                : 3;
+            __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 2*n                           */
+            uint32_t                : 11;
+            __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 2*n+1 Error                                          */
+            uint32_t                : 3;
+            __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 2*n+1                       */
+            uint32_t                : 11;
+        } BISS_STAT7_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL_STAT0;             /*!< (@ 0x00000040) HIPERFACE DSL Status Register 0                            */
+
+        struct
+        {
+            __IM uint32_t HDSL0_LINK     : 1; /*!< [0..0] HIPERFACE-DSL Link                                                 */
+            __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked                                          */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL0_ESTON    : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON                                         */
+            __IM uint32_t HDSL0_SCHERR   : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error                                   */
+            __IM uint32_t HDSL0_SPERR    : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error                                  */
+            __IM uint32_t HDSL0_EDTERR   : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error                  */
+            __IM uint32_t HDSL0_ACCERR   : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error                                   */
+            __IM uint32_t HDSL0_ACTHERR  : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error                         */
+            __IM uint32_t HDSL0_ENCERR   : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+            __IM uint32_t HDSL1_LINK     : 1; /*!< [16..16] HIPERFACE-DSL Link                                               */
+            __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked                                        */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL1_ESTON    : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON                                       */
+            __IM uint32_t HDSL1_SCHERR   : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error                                 */
+            __IM uint32_t HDSL1_SPERR    : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error                                */
+            __IM uint32_t HDSL1_EDTERR   : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error                */
+            __IM uint32_t HDSL1_ACCERR   : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error                                 */
+            __IM uint32_t HDSL1_ACTHERR  : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error                       */
+            __IM uint32_t HDSL1_ENCERR   : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+        } HDSL_STAT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL_STAT1;             /*!< (@ 0x00000044) HIPERFACE DSL Status Register 1                            */
+
+        struct
+        {
+            __IM uint32_t HDSL0_LINK     : 1; /*!< [0..0] HIPERFACE-DSL Link                                                 */
+            __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked                                          */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL0_ESTON    : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON                                         */
+            __IM uint32_t HDSL0_SCHERR   : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error                                   */
+            __IM uint32_t HDSL0_SPERR    : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error                                  */
+            __IM uint32_t HDSL0_EDTERR   : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error                  */
+            __IM uint32_t HDSL0_ACCERR   : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error                                   */
+            __IM uint32_t HDSL0_ACTHERR  : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error                         */
+            __IM uint32_t HDSL0_ENCERR   : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+            __IM uint32_t HDSL1_LINK     : 1; /*!< [16..16] HIPERFACE-DSL Link                                               */
+            __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked                                        */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL1_ESTON    : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON                                       */
+            __IM uint32_t HDSL1_SCHERR   : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error                                 */
+            __IM uint32_t HDSL1_SPERR    : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error                                */
+            __IM uint32_t HDSL1_EDTERR   : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error                */
+            __IM uint32_t HDSL1_ACCERR   : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error                                 */
+            __IM uint32_t HDSL1_ACTHERR  : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error                       */
+            __IM uint32_t HDSL1_ENCERR   : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+        } HDSL_STAT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL_STAT2;             /*!< (@ 0x00000048) HIPERFACE DSL Status Register 2                            */
+
+        struct
+        {
+            __IM uint32_t HDSL0_LINK     : 1; /*!< [0..0] HIPERFACE-DSL Link                                                 */
+            __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked                                          */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL0_ESTON    : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON                                         */
+            __IM uint32_t HDSL0_SCHERR   : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error                                   */
+            __IM uint32_t HDSL0_SPERR    : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error                                  */
+            __IM uint32_t HDSL0_EDTERR   : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error                  */
+            __IM uint32_t HDSL0_ACCERR   : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error                                   */
+            __IM uint32_t HDSL0_ACTHERR  : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error                         */
+            __IM uint32_t HDSL0_ENCERR   : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+            __IM uint32_t HDSL1_LINK     : 1; /*!< [16..16] HIPERFACE-DSL Link                                               */
+            __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked                                        */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL1_ESTON    : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON                                       */
+            __IM uint32_t HDSL1_SCHERR   : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error                                 */
+            __IM uint32_t HDSL1_SPERR    : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error                                */
+            __IM uint32_t HDSL1_EDTERR   : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error                */
+            __IM uint32_t HDSL1_ACCERR   : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error                                 */
+            __IM uint32_t HDSL1_ACTHERR  : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error                       */
+            __IM uint32_t HDSL1_ENCERR   : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+        } HDSL_STAT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL_STAT3;             /*!< (@ 0x0000004C) HIPERFACE DSL Status Register 3                            */
+
+        struct
+        {
+            __IM uint32_t HDSL0_LINK     : 1; /*!< [0..0] HIPERFACE-DSL Link                                                 */
+            __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked                                          */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL0_ESTON    : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON                                         */
+            __IM uint32_t HDSL0_SCHERR   : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error                                   */
+            __IM uint32_t HDSL0_SPERR    : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error                                  */
+            __IM uint32_t HDSL0_EDTERR   : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error                  */
+            __IM uint32_t HDSL0_ACCERR   : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error                                   */
+            __IM uint32_t HDSL0_ACTHERR  : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error                         */
+            __IM uint32_t HDSL0_ENCERR   : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+            __IM uint32_t HDSL1_LINK     : 1; /*!< [16..16] HIPERFACE-DSL Link                                               */
+            __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked                                        */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL1_ESTON    : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON                                       */
+            __IM uint32_t HDSL1_SCHERR   : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error                                 */
+            __IM uint32_t HDSL1_SPERR    : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error                                */
+            __IM uint32_t HDSL1_EDTERR   : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error                */
+            __IM uint32_t HDSL1_ACCERR   : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error                                 */
+            __IM uint32_t HDSL1_ACTHERR  : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error                       */
+            __IM uint32_t HDSL1_ENCERR   : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+        } HDSL_STAT3_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL_STAT4;             /*!< (@ 0x00000050) HIPERFACE DSL Status Register 4                            */
+
+        struct
+        {
+            __IM uint32_t HDSL0_LINK     : 1; /*!< [0..0] HIPERFACE-DSL Link                                                 */
+            __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked                                          */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL0_ESTON    : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON                                         */
+            __IM uint32_t HDSL0_SCHERR   : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error                                   */
+            __IM uint32_t HDSL0_SPERR    : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error                                  */
+            __IM uint32_t HDSL0_EDTERR   : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error                  */
+            __IM uint32_t HDSL0_ACCERR   : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error                                   */
+            __IM uint32_t HDSL0_ACTHERR  : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error                         */
+            __IM uint32_t HDSL0_ENCERR   : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+            __IM uint32_t HDSL1_LINK     : 1; /*!< [16..16] HIPERFACE-DSL Link                                               */
+            __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked                                        */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL1_ESTON    : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON                                       */
+            __IM uint32_t HDSL1_SCHERR   : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error                                 */
+            __IM uint32_t HDSL1_SPERR    : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error                                */
+            __IM uint32_t HDSL1_EDTERR   : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error                */
+            __IM uint32_t HDSL1_ACCERR   : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error                                 */
+            __IM uint32_t HDSL1_ACTHERR  : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error                       */
+            __IM uint32_t HDSL1_ENCERR   : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+        } HDSL_STAT4_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL_STAT5;             /*!< (@ 0x00000054) HIPERFACE DSL Status Register 5                            */
+
+        struct
+        {
+            __IM uint32_t HDSL0_LINK     : 1; /*!< [0..0] HIPERFACE-DSL Link                                                 */
+            __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked                                          */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL0_ESTON    : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON                                         */
+            __IM uint32_t HDSL0_SCHERR   : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error                                   */
+            __IM uint32_t HDSL0_SPERR    : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error                                  */
+            __IM uint32_t HDSL0_EDTERR   : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error                  */
+            __IM uint32_t HDSL0_ACCERR   : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error                                   */
+            __IM uint32_t HDSL0_ACTHERR  : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error                         */
+            __IM uint32_t HDSL0_ENCERR   : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+            __IM uint32_t HDSL1_LINK     : 1; /*!< [16..16] HIPERFACE-DSL Link                                               */
+            __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked                                        */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL1_ESTON    : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON                                       */
+            __IM uint32_t HDSL1_SCHERR   : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error                                 */
+            __IM uint32_t HDSL1_SPERR    : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error                                */
+            __IM uint32_t HDSL1_EDTERR   : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error                */
+            __IM uint32_t HDSL1_ACCERR   : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error                                 */
+            __IM uint32_t HDSL1_ACTHERR  : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error                       */
+            __IM uint32_t HDSL1_ENCERR   : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+        } HDSL_STAT5_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL_STAT6;             /*!< (@ 0x00000058) HIPERFACE DSL Status Register 6                            */
+
+        struct
+        {
+            __IM uint32_t HDSL0_LINK     : 1; /*!< [0..0] HIPERFACE-DSL Link                                                 */
+            __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked                                          */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL0_ESTON    : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON                                         */
+            __IM uint32_t HDSL0_SCHERR   : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error                                   */
+            __IM uint32_t HDSL0_SPERR    : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error                                  */
+            __IM uint32_t HDSL0_EDTERR   : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error                  */
+            __IM uint32_t HDSL0_ACCERR   : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error                                   */
+            __IM uint32_t HDSL0_ACTHERR  : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error                         */
+            __IM uint32_t HDSL0_ENCERR   : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+            __IM uint32_t HDSL1_LINK     : 1; /*!< [16..16] HIPERFACE-DSL Link                                               */
+            __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked                                        */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL1_ESTON    : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON                                       */
+            __IM uint32_t HDSL1_SCHERR   : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error                                 */
+            __IM uint32_t HDSL1_SPERR    : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error                                */
+            __IM uint32_t HDSL1_EDTERR   : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error                */
+            __IM uint32_t HDSL1_ACCERR   : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error                                 */
+            __IM uint32_t HDSL1_ACTHERR  : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error                       */
+            __IM uint32_t HDSL1_ENCERR   : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+        } HDSL_STAT6_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL_STAT7;             /*!< (@ 0x0000005C) HIPERFACE DSL Status Register 7                            */
+
+        struct
+        {
+            __IM uint32_t HDSL0_LINK     : 1; /*!< [0..0] HIPERFACE-DSL Link                                                 */
+            __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked                                          */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL0_ESTON    : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON                                         */
+            __IM uint32_t HDSL0_SCHERR   : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error                                   */
+            __IM uint32_t HDSL0_SPERR    : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error                                  */
+            __IM uint32_t HDSL0_EDTERR   : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error                  */
+            __IM uint32_t HDSL0_ACCERR   : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error                                   */
+            __IM uint32_t HDSL0_ACTHERR  : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error                         */
+            __IM uint32_t HDSL0_ENCERR   : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+            __IM uint32_t HDSL1_LINK     : 1; /*!< [16..16] HIPERFACE-DSL Link                                               */
+            __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked                                        */
+            uint32_t                     : 2;
+            __IM uint32_t HDSL1_ESTON    : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON                                       */
+            __IM uint32_t HDSL1_SCHERR   : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error                                 */
+            __IM uint32_t HDSL1_SPERR    : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error                                */
+            __IM uint32_t HDSL1_EDTERR   : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error                */
+            __IM uint32_t HDSL1_ACCERR   : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error                                 */
+            __IM uint32_t HDSL1_ACTHERR  : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error                       */
+            __IM uint32_t HDSL1_ENCERR   : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error                                     */
+            uint32_t                     : 5;
+        } HDSL_STAT7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDAT_CFG0;           /*!< (@ 0x00000060) EnDat Configuration Register 0                             */
+
+        struct
+        {
+            __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 2*n Axis Address                                        */
+            uint32_t                    : 11;
+            __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 2*n+1 Axis Address                                    */
+            uint32_t                    : 11;
+        } ENDAT_CFG0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDAT_CFG1;           /*!< (@ 0x00000064) EnDat Configuration Register 1                             */
+
+        struct
+        {
+            __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 2*n Axis Address                                        */
+            uint32_t                    : 11;
+            __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 2*n+1 Axis Address                                    */
+            uint32_t                    : 11;
+        } ENDAT_CFG1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDAT_CFG2;           /*!< (@ 0x00000068) EnDat Configuration Register 2                             */
+
+        struct
+        {
+            __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 2*n Axis Address                                        */
+            uint32_t                    : 11;
+            __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 2*n+1 Axis Address                                    */
+            uint32_t                    : 11;
+        } ENDAT_CFG2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDAT_CFG3;           /*!< (@ 0x0000006C) EnDat Configuration Register 3                             */
+
+        struct
+        {
+            __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 2*n Axis Address                                        */
+            uint32_t                    : 11;
+            __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 2*n+1 Axis Address                                    */
+            uint32_t                    : 11;
+        } ENDAT_CFG3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDAT_CFG4;           /*!< (@ 0x00000070) EnDat Configuration Register 4                             */
+
+        struct
+        {
+            __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 2*n Axis Address                                        */
+            uint32_t                    : 11;
+            __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 2*n+1 Axis Address                                    */
+            uint32_t                    : 11;
+        } ENDAT_CFG4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDAT_CFG5;           /*!< (@ 0x00000074) EnDat Configuration Register 5                             */
+
+        struct
+        {
+            __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 2*n Axis Address                                        */
+            uint32_t                    : 11;
+            __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 2*n+1 Axis Address                                    */
+            uint32_t                    : 11;
+        } ENDAT_CFG5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDAT_CFG6;           /*!< (@ 0x00000078) EnDat Configuration Register 6                             */
+
+        struct
+        {
+            __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 2*n Axis Address                                        */
+            uint32_t                    : 11;
+            __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 2*n+1 Axis Address                                    */
+            uint32_t                    : 11;
+        } ENDAT_CFG6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENDAT_CFG7;           /*!< (@ 0x0000007C) EnDat Configuration Register 7                             */
+
+        struct
+        {
+            __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 2*n Axis Address                                        */
+            uint32_t                    : 11;
+            __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 2*n+1 Axis Address                                    */
+            uint32_t                    : 11;
+        } ENDAT_CFG7_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFMT_STAT0;          /*!< (@ 0x00000080) A-Format Status Register 0                                 */
+
+        struct
+        {
+            __IM uint32_t AFMT0_BUSY  : 1; /*!< [0..0] A-format Busy                                                      */
+            __IM uint32_t AFMT0_EOT   : 1; /*!< [1..1] A-format End-Of-Frame                                              */
+            __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout                                                   */
+            uint32_t                  : 13;
+            __IM uint32_t AFMT1_BUSY  : 1; /*!< [16..16] A-format Busy                                                    */
+            __IM uint32_t AFMT1_EOT   : 1; /*!< [17..17] A-format End-of-Frame                                            */
+            __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout                                                 */
+            uint32_t                  : 13;
+        } AFMT_STAT0_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFMT_STAT1;          /*!< (@ 0x00000084) A-Format Status Register 1                                 */
+
+        struct
+        {
+            __IM uint32_t AFMT0_BUSY  : 1; /*!< [0..0] A-format Busy                                                      */
+            __IM uint32_t AFMT0_EOT   : 1; /*!< [1..1] A-format End-Of-Frame                                              */
+            __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout                                                   */
+            uint32_t                  : 13;
+            __IM uint32_t AFMT1_BUSY  : 1; /*!< [16..16] A-format Busy                                                    */
+            __IM uint32_t AFMT1_EOT   : 1; /*!< [17..17] A-format End-of-Frame                                            */
+            __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout                                                 */
+            uint32_t                  : 13;
+        } AFMT_STAT1_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFMT_STAT2;          /*!< (@ 0x00000088) A-Format Status Register 2                                 */
+
+        struct
+        {
+            __IM uint32_t AFMT0_BUSY  : 1; /*!< [0..0] A-format Busy                                                      */
+            __IM uint32_t AFMT0_EOT   : 1; /*!< [1..1] A-format End-Of-Frame                                              */
+            __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout                                                   */
+            uint32_t                  : 13;
+            __IM uint32_t AFMT1_BUSY  : 1; /*!< [16..16] A-format Busy                                                    */
+            __IM uint32_t AFMT1_EOT   : 1; /*!< [17..17] A-format End-of-Frame                                            */
+            __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout                                                 */
+            uint32_t                  : 13;
+        } AFMT_STAT2_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFMT_STAT3;          /*!< (@ 0x0000008C) A-Format Status Register 3                                 */
+
+        struct
+        {
+            __IM uint32_t AFMT0_BUSY  : 1; /*!< [0..0] A-format Busy                                                      */
+            __IM uint32_t AFMT0_EOT   : 1; /*!< [1..1] A-format End-Of-Frame                                              */
+            __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout                                                   */
+            uint32_t                  : 13;
+            __IM uint32_t AFMT1_BUSY  : 1; /*!< [16..16] A-format Busy                                                    */
+            __IM uint32_t AFMT1_EOT   : 1; /*!< [17..17] A-format End-of-Frame                                            */
+            __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout                                                 */
+            uint32_t                  : 13;
+        } AFMT_STAT3_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFMT_STAT4;          /*!< (@ 0x00000090) A-Format Status Register 4                                 */
+
+        struct
+        {
+            __IM uint32_t AFMT0_BUSY  : 1; /*!< [0..0] A-format Busy                                                      */
+            __IM uint32_t AFMT0_EOT   : 1; /*!< [1..1] A-format End-Of-Frame                                              */
+            __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout                                                   */
+            uint32_t                  : 13;
+            __IM uint32_t AFMT1_BUSY  : 1; /*!< [16..16] A-format Busy                                                    */
+            __IM uint32_t AFMT1_EOT   : 1; /*!< [17..17] A-format End-of-Frame                                            */
+            __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout                                                 */
+            uint32_t                  : 13;
+        } AFMT_STAT4_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFMT_STAT5;          /*!< (@ 0x00000094) A-Format Status Register 5                                 */
+
+        struct
+        {
+            __IM uint32_t AFMT0_BUSY  : 1; /*!< [0..0] A-format Busy                                                      */
+            __IM uint32_t AFMT0_EOT   : 1; /*!< [1..1] A-format End-Of-Frame                                              */
+            __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout                                                   */
+            uint32_t                  : 13;
+            __IM uint32_t AFMT1_BUSY  : 1; /*!< [16..16] A-format Busy                                                    */
+            __IM uint32_t AFMT1_EOT   : 1; /*!< [17..17] A-format End-of-Frame                                            */
+            __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout                                                 */
+            uint32_t                  : 13;
+        } AFMT_STAT5_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFMT_STAT6;          /*!< (@ 0x00000098) A-Format Status Register 6                                 */
+
+        struct
+        {
+            __IM uint32_t AFMT0_BUSY  : 1; /*!< [0..0] A-format Busy                                                      */
+            __IM uint32_t AFMT0_EOT   : 1; /*!< [1..1] A-format End-Of-Frame                                              */
+            __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout                                                   */
+            uint32_t                  : 13;
+            __IM uint32_t AFMT1_BUSY  : 1; /*!< [16..16] A-format Busy                                                    */
+            __IM uint32_t AFMT1_EOT   : 1; /*!< [17..17] A-format End-of-Frame                                            */
+            __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout                                                 */
+            uint32_t                  : 13;
+        } AFMT_STAT6_b;
+    };
+
+    union
+    {
+        __IM uint32_t AFMT_STAT7;          /*!< (@ 0x0000009C) A-Format Status Register 7                                 */
+
+        struct
+        {
+            __IM uint32_t AFMT0_BUSY  : 1; /*!< [0..0] A-format Busy                                                      */
+            __IM uint32_t AFMT0_EOT   : 1; /*!< [1..1] A-format End-Of-Frame                                              */
+            __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout                                                   */
+            uint32_t                  : 13;
+            __IM uint32_t AFMT1_BUSY  : 1; /*!< [16..16] A-format Busy                                                    */
+            __IM uint32_t AFMT1_EOT   : 1; /*!< [17..17] A-format End-of-Frame                                            */
+            __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout                                                 */
+            uint32_t                  : 13;
+        } AFMT_STAT7_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL0_OS_D;      /*!< (@ 0x000000A0) HIPERFACE_DSL Online Status D Register 0                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL0_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL1_OS_D;      /*!< (@ 0x000000A4) HIPERFACE_DSL Online Status D Register 1                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL1_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL2_OS_D;      /*!< (@ 0x000000A8) HIPERFACE_DSL Online Status D Register 2                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL2_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL3_OS_D;      /*!< (@ 0x000000AC) HIPERFACE_DSL Online Status D Register 3                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL3_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL4_OS_D;      /*!< (@ 0x000000B0) HIPERFACE_DSL Online Status D Register 4                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL4_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL5_OS_D;      /*!< (@ 0x000000B4) HIPERFACE_DSL Online Status D Register 5                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL5_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL6_OS_D;      /*!< (@ 0x000000B8) HIPERFACE_DSL Online Status D Register 6                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL6_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL7_OS_D;      /*!< (@ 0x000000BC) HIPERFACE_DSL Online Status D Register 7                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL7_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL8_OS_D;      /*!< (@ 0x000000C0) HIPERFACE_DSL Online Status D Register 8                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL8_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL9_OS_D;      /*!< (@ 0x000000C4) HIPERFACE_DSL Online Status D Register 9                   */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL9_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL10_OS_D;     /*!< (@ 0x000000C8) HIPERFACE_DSL Online Status D Register 10                  */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL10_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL11_OS_D;     /*!< (@ 0x000000CC) HIPERFACE_DSL Online Status D Register 11                  */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL11_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL12_OS_D;     /*!< (@ 0x000000D0) HIPERFACE_DSL Online Status D Register 12                  */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL12_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL13_OS_D;     /*!< (@ 0x000000D4) HIPERFACE_DSL Online Status D Register 13                  */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL13_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL14_OS_D;     /*!< (@ 0x000000D8) HIPERFACE_DSL Online Status D Register 14                  */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL14_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL15_OS_D;     /*!< (@ 0x000000DC) HIPERFACE_DSL Online Status D Register 15                  */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t FREL  : 1;   /*!< [1..1] Channel Status for long message                                    */
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality monitoring at Low level                                    */
+            uint32_t            : 1;
+            __IM uint32_t ANS   : 1;   /*!< [4..4] Incorrect Answer Detected                                          */
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            __IM uint32_t DTE   : 1;   /*!< [9..9] Deviation Threshold Error                                          */
+            uint32_t            : 1;
+            __IM uint32_t POS   : 1;   /*!< [11..11] Estimator Turned On                                              */
+            uint32_t            : 2;
+            __IM uint32_t SUM   : 1;   /*!< [14..14] Summary Byte                                                     */
+            __IM uint32_t INT   : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL15_OS_D_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL0_OS_1;      /*!< (@ 0x000000E0) HIPERFACE_DSL Online Status 1 Register 0                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL0_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL1_OS_1;      /*!< (@ 0x000000E4) HIPERFACE_DSL Online Status 1 Register 1                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL1_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL2_OS_1;      /*!< (@ 0x000000E8) HIPERFACE_DSL Online Status 1 Register 2                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL2_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL3_OS_1;      /*!< (@ 0x000000EC) HIPERFACE_DSL Online Status 1 Register 3                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL3_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL4_OS_1;      /*!< (@ 0x000000F0) HIPERFACE_DSL Online Status 1 Register 4                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL4_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL5_OS_1;      /*!< (@ 0x000000F4) HIPERFACE_DSL Online Status 1 Register 5                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL5_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL6_OS_1;      /*!< (@ 0x000000F8) HIPERFACE_DSL Online Status 1 Register 6                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL6_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL7_OS_1;      /*!< (@ 0x000000FC) HIPERFACE_DSL Online Status 1 Register 7                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL7_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL8_OS_1;      /*!< (@ 0x00000100) HIPERFACE_DSL Online Status 1 Register 8                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL8_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL9_OS_1;      /*!< (@ 0x00000104) HIPERFACE_DSL Online Status 1 Register 9                   */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL9_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL10_OS_1;     /*!< (@ 0x00000108) HIPERFACE_DSL Online Status 1 Register 10                  */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL10_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL11_OS_1;     /*!< (@ 0x0000010C) HIPERFACE_DSL Online Status 1 Register 11                  */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL11_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL12_OS_1;     /*!< (@ 0x00000110) HIPERFACE_DSL Online Status 1 Register 12                  */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL12_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL13_OS_1;     /*!< (@ 0x00000114) HIPERFACE_DSL Online Status 1 Register 13                  */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL13_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL14_OS_1;     /*!< (@ 0x00000118) HIPERFACE_DSL Online Status 1 Register 14                  */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL14_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL15_OS_1;     /*!< (@ 0x0000011C) HIPERFACE_DSL Online Status 1 Register 15                  */
+
+        struct
+        {
+            __IM uint32_t FRES  : 1;   /*!< [0..0] Channel Status for the short message                               */
+            uint32_t            : 1;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 2;
+            __IM uint32_t MIN   : 1;   /*!< [5..5] Acknowledgment of Message Initialization                           */
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS  : 1;   /*!< [10..10] Safe Position Invalid                                            */
+            uint32_t            : 2;
+            __IM uint32_t SCE   : 1;   /*!< [13..13] CRC Error on the Safe Channel                                    */
+            __IM uint32_t SSUM  : 1;   /*!< [14..14] Safe Summary Bit                                                 */
+            __IM uint32_t SINT  : 1;   /*!< [15..15] Status of the Interrupt Output                                   */
+            uint32_t            : 16;
+        } HDSL15_OS_1_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL0_OS_2;      /*!< (@ 0x00000120) HIPERFACE_DSL Online Status 2 Register 0                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL0_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL1_OS_2;      /*!< (@ 0x00000124) HIPERFACE_DSL Online Status 2 Register 1                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL1_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL2_OS_2;      /*!< (@ 0x00000128) HIPERFACE_DSL Online Status 2 Register 2                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL2_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL3_OS_2;      /*!< (@ 0x0000012C) HIPERFACE_DSL Online Status 2 Register 3                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL3_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL4_OS_2;      /*!< (@ 0x00000130) HIPERFACE_DSL Online Status 2 Register 4                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL4_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL5_OS_2;      /*!< (@ 0x00000134) HIPERFACE_DSL Online Status 2 Register 5                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL5_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL6_OS_2;      /*!< (@ 0x00000138) HIPERFACE_DSL Online Status 2 Register 6                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL6_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL7_OS_2;      /*!< (@ 0x0000013C) HIPERFACE_DSL Online Status 2 Register 7                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL7_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL8_OS_2;      /*!< (@ 0x00000140) HIPERFACE_DSL Online Status 2 Register 8                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL8_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL9_OS_2;      /*!< (@ 0x00000144) HIPERFACE_DSL Online Status 2 Register 9                   */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL9_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL10_OS_2;     /*!< (@ 0x00000148) HIPERFACE_DSL Online Status 2 Register 10                  */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL10_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL11_OS_2;     /*!< (@ 0x0000014C) HIPERFACE_DSL Online Status 2 Register 11                  */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL11_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL12_OS_2;     /*!< (@ 0x00000150) HIPERFACE_DSL Online Status 2 Register 12                  */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL12_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL13_OS_2;     /*!< (@ 0x00000154) HIPERFACE_DSL Online Status 2 Register 13                  */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL13_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL14_OS_2;     /*!< (@ 0x00000158) HIPERFACE_DSL Online Status 2 Register 14                  */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL14_OS_2_b;
+    };
+
+    union
+    {
+        __IM uint32_t HDSL15_OS_2;     /*!< (@ 0x0000015C) HIPERFACE_DSL Online Status 2 Register 15                  */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IM uint32_t QMLW  : 1;   /*!< [2..2] Quality Monitoring at Low level                                    */
+            uint32_t            : 3;
+            __IM uint32_t POSTX : 2;   /*!< [7..6] Position Transmission Status                                       */
+            __IM uint32_t PRST  : 1;   /*!< [8..8] Protocol Reset                                                     */
+            uint32_t            : 1;
+            __IM uint32_t VPOS2 : 1;   /*!< [10..10] Safe Position 2 Invalid                                          */
+            uint32_t            : 2;
+            __IM uint32_t SCE2  : 1;   /*!< [13..13] Transmission Error Channel 2                                     */
+            __IM uint32_t SSUM2 : 1;   /*!< [14..14] Summary Bit Channel 2                                            */
+            uint32_t            : 17;
+        } HDSL15_OS_2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HDSL_HOSTF0;      /*!< (@ 0x00000160) HIPERFACE DSL Host_f Control Register 0                    */
+
+        struct
+        {
+            __IOM uint32_t HOSTD_F0 : 1; /*!< [0..0] HOSTD_F0                                                           */
+            __IOM uint32_t HOST1_F0 : 1; /*!< [1..1] HOST1_F0                                                           */
+            __IOM uint32_t HOST2_F0 : 1; /*!< [2..2] HOST2_F0                                                           */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F1 : 1; /*!< [4..4] HOSTD_F1                                                           */
+            __IOM uint32_t HOST1_F1 : 1; /*!< [5..5] HOST1_F1                                                           */
+            __IOM uint32_t HOST2_F1 : 1; /*!< [6..6] HOST2_F1                                                           */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F2 : 1; /*!< [8..8] HOSTD_F2                                                           */
+            __IOM uint32_t HOST1_F2 : 1; /*!< [9..9] HOST1_F2                                                           */
+            __IOM uint32_t HOST2_F2 : 1; /*!< [10..10] HOST2_F2                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F3 : 1; /*!< [12..12] HOSTD_F3                                                         */
+            __IOM uint32_t HOST1_F3 : 1; /*!< [13..13] HOST1_F3                                                         */
+            __IOM uint32_t HOST2_F3 : 1; /*!< [14..14] HOST2_F3                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F4 : 1; /*!< [16..16] HOSTD_F4                                                         */
+            __IOM uint32_t HOST1_F4 : 1; /*!< [17..17] HOST1_F4                                                         */
+            __IOM uint32_t HOST2_F4 : 1; /*!< [18..18] HOST2_F4                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F5 : 1; /*!< [20..20] HOSTD_F5                                                         */
+            __IOM uint32_t HOST1_F5 : 1; /*!< [21..21] HOST1_F5                                                         */
+            __IOM uint32_t HOST2_F5 : 1; /*!< [22..22] HOST2_F5                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F6 : 1; /*!< [24..24] HOSTD_F6                                                         */
+            __IOM uint32_t HOST1_F6 : 1; /*!< [25..25] HOST1_F6                                                         */
+            __IOM uint32_t HOST2_F6 : 1; /*!< [26..26] HOST2_F6                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F7 : 1; /*!< [28..28] Drive Interface Register Freeze (hostd_f) for HDSL
+                                          *   Unit 8*n+7                                                                */
+            __IOM uint32_t HOST1_F7 : 1; /*!< [29..29] HOST1_F7                                                         */
+            __IOM uint32_t HOST2_F7 : 1; /*!< [30..30] HOST2_F7                                                         */
+            uint32_t                : 1;
+        } HDSL_HOSTF0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HDSL_HOSTF1;      /*!< (@ 0x00000164) HIPERFACE DSL Host_f Control Register 1                    */
+
+        struct
+        {
+            __IOM uint32_t HOSTD_F0 : 1; /*!< [0..0] HOSTD_F0                                                           */
+            __IOM uint32_t HOST1_F0 : 1; /*!< [1..1] HOST1_F0                                                           */
+            __IOM uint32_t HOST2_F0 : 1; /*!< [2..2] HOST2_F0                                                           */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F1 : 1; /*!< [4..4] HOSTD_F1                                                           */
+            __IOM uint32_t HOST1_F1 : 1; /*!< [5..5] HOST1_F1                                                           */
+            __IOM uint32_t HOST2_F1 : 1; /*!< [6..6] HOST2_F1                                                           */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F2 : 1; /*!< [8..8] HOSTD_F2                                                           */
+            __IOM uint32_t HOST1_F2 : 1; /*!< [9..9] HOST1_F2                                                           */
+            __IOM uint32_t HOST2_F2 : 1; /*!< [10..10] HOST2_F2                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F3 : 1; /*!< [12..12] HOSTD_F3                                                         */
+            __IOM uint32_t HOST1_F3 : 1; /*!< [13..13] HOST1_F3                                                         */
+            __IOM uint32_t HOST2_F3 : 1; /*!< [14..14] HOST2_F3                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F4 : 1; /*!< [16..16] HOSTD_F4                                                         */
+            __IOM uint32_t HOST1_F4 : 1; /*!< [17..17] HOST1_F4                                                         */
+            __IOM uint32_t HOST2_F4 : 1; /*!< [18..18] HOST2_F4                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F5 : 1; /*!< [20..20] HOSTD_F5                                                         */
+            __IOM uint32_t HOST1_F5 : 1; /*!< [21..21] HOST1_F5                                                         */
+            __IOM uint32_t HOST2_F5 : 1; /*!< [22..22] HOST2_F5                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F6 : 1; /*!< [24..24] HOSTD_F6                                                         */
+            __IOM uint32_t HOST1_F6 : 1; /*!< [25..25] HOST1_F6                                                         */
+            __IOM uint32_t HOST2_F6 : 1; /*!< [26..26] HOST2_F6                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t HOSTD_F7 : 1; /*!< [28..28] Drive Interface Register Freeze (hostd_f) for HDSL
+                                          *   Unit 8*n+7                                                                */
+            __IOM uint32_t HOST1_F7 : 1; /*!< [29..29] HOST1_F7                                                         */
+            __IOM uint32_t HOST2_F7 : 1; /*!< [30..30] HOST2_F7                                                         */
+            uint32_t                : 1;
+        } HDSL_HOSTF1_b;
+    };
+} R_ENCSS_Type;                          /*!< Size = 360 (0x168)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PCIE_SPL0                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief PCIe Supplemental Settings Channel 0 (R_PCIE_SPL0)
+ */
+
+typedef struct                             /*!< (@ 0x80292000) R_PCIE_SPL0 Structure                                      */
+{
+    union
+    {
+        __IOM uint32_t PCIE_INTX;          /*!< (@ 0x00000000) PCIe INTX Register                                         */
+
+        struct
+        {
+            __IOM uint32_t INTX_EP_F0 : 1; /*!< [0..0] Legacy Interrupt (Assert_INTx/Deassert_INTx message)
+                                            *   Trigger for Endpoint Funtion #0                                           */
+            __IOM uint32_t INTX_EP_F1 : 1; /*!< [1..1] Legacy Interrupt (Assert_INTx/Deassert_INTx message)
+                                            *   Trigger for Endpoint Funtion #1                                           */
+            uint32_t : 30;
+        } PCIE_INTX_b;
+    };
+
+    union
+    {
+        __OM uint32_t PCIE_MSI1;              /*!< (@ 0x00000004) PCIe MSI Register 1                                        */
+
+        struct
+        {
+            __OM uint32_t UI_EXTMSI_VAL0 : 1; /*!< [0..0] MSI 0 Interrupt Trigger for Endpoint                               */
+            __OM uint32_t UI_EXTMSI_VAL1 : 1; /*!< [1..1] MSI 1 Interrupt Trigger for Endpoint                               */
+            __OM uint32_t UI_EXTMSI_VAL2 : 1; /*!< [2..2] MSI 2 Interrupt Trigger for Endpoint                               */
+            __OM uint32_t UI_EXTMSI_VAL3 : 1; /*!< [3..3] MSI 3 Interrupt Trigger for Endpoint                               */
+            __OM uint32_t UI_EXTMSI_VAL4 : 1; /*!< [4..4] MSI 4 Interrupt Trigger for Endpoint                               */
+            uint32_t                     : 27;
+        } PCIE_MSI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCIE_MSI2;              /*!< (@ 0x00000008) PCIe MSI Register 2                                        */
+
+        struct
+        {
+            __IOM uint32_t UI_EXTMSI_VEC0 : 5; /*!< [4..0] Specify the interrupt vector of MSI 0 interrupt for Endpoint.      */
+            uint32_t                      : 3;
+            __IOM uint32_t UI_EXTMSI_VEC1 : 5; /*!< [12..8] Specify the interrupt vector of MSI 1 interrupt for
+                                                *   Endpoint.                                                                 */
+            uint32_t                      : 3;
+            __IOM uint32_t UI_EXTMSI_VEC2 : 5; /*!< [20..16] Specify the interrupt vector of MSI 2 interrupt for
+                                                *   Endpoint.                                                                 */
+            uint32_t                      : 3;
+            __IOM uint32_t UI_EXTMSI_VEC3 : 5; /*!< [28..24] Specify the interrupt vector of MSI 3 interrupt for
+                                                *   Endpoint.                                                                 */
+            uint32_t : 3;
+        } PCIE_MSI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCIE_MSI3;              /*!< (@ 0x0000000C) PCIe MSI Register 3                                        */
+
+        struct
+        {
+            __IOM uint32_t UI_EXTMSI_VEC4 : 5; /*!< [4..0] Specify the interrupt vector of MSI 4 interrupt for Endpoint.      */
+            uint32_t                      : 27;
+        } PCIE_MSI3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCIE_MSI4;               /*!< (@ 0x00000010) PCIe MSI Register 4                                        */
+
+        struct
+        {
+            __IOM uint32_t UI_EXTMSI_FUNC0 : 3; /*!< [2..0] Specify the interrupt function number of MSI 0 interrupt
+                                                 *   for Endpoint.                                                             */
+            uint32_t                       : 5;
+            __IOM uint32_t UI_EXTMSI_FUNC1 : 3; /*!< [10..8] Specify the interrupt function number of MSI 1 interrupt
+                                                 *   for Endpoint.                                                             */
+            uint32_t                       : 5;
+            __IOM uint32_t UI_EXTMSI_FUNC2 : 3; /*!< [18..16] Specify the interrupt function number of MSI 2 interrupt
+                                                 *   for Endpoint.                                                             */
+            uint32_t                       : 5;
+            __IOM uint32_t UI_EXTMSI_FUNC3 : 3; /*!< [26..24] Specify the interrupt function number of MSI 3 interrupt
+                                                 *   for Endpoint.                                                             */
+            uint32_t : 5;
+        } PCIE_MSI4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCIE_MSI5;               /*!< (@ 0x00000014) PCIe MSI Register 5                                        */
+
+        struct
+        {
+            __IOM uint32_t UI_EXTMSI_FUNC4 : 3; /*!< [2..0] Specify the interrupt function number of MSI 4 interrupt
+                                                 *   for Endpoint.                                                             */
+            uint32_t : 29;
+        } PCIE_MSI5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCIE_PME;                        /*!< (@ 0x00000018) PCIe PME Register                                          */
+
+        struct
+        {
+            __IOM uint32_t PME_TIM                 : 1; /*!< [0..0] PM_PME Message Clock for Endpoint                                  */
+            uint32_t                               : 7;
+            __IOM uint32_t CFG_PMCSR_PME_STATUS_F0 : 1; /*!< [8..8] Power Management Event Setting for Endpoint Function
+                                                         #0                                                                        */
+            __IOM uint32_t CFG_PMCSR_PME_STATUS_F1 : 1; /*!< [9..9] Power Management Event Setting for Endpoint Function
+                                                         #1                                                                        */
+            uint32_t : 22;
+        } PCIE_PME_b;
+    };
+
+    union
+    {
+        __OM uint32_t PCIE_ACK;                   /*!< (@ 0x0000001C) PCIe ACK Register                                          */
+
+        struct
+        {
+            __OM uint32_t TURN_OFF_EVENT_ACK : 1; /*!< [0..0] Acknowledge to PME_Turn_Off Message for Endpoint                   */
+            uint32_t                         : 7;
+            __OM uint32_t D3_EVENT_ACK_F0    : 1; /*!< [8..8] Acknowledge to Power State Transition for Endpoint Function
+                                                   #0                                                                        */
+            __OM uint32_t D3_EVENT_ACK_F1 : 1;    /*!< [9..9] Acknowledge to Power State Transition for Endpoint Function
+                                                   #1                                                                        */
+            uint32_t : 22;
+        } PCIE_ACK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCIE_MISC;              /*!< (@ 0x00000020) PCIe MISC Register                                         */
+
+        struct
+        {
+            __IOM uint32_t ALLOW_ENTER_L1 : 1; /*!< [0..0] ASPM L1 State Transition Permission                                */
+            uint32_t                      : 15;
+            __OM uint32_t FLR_RESET0      : 1; /*!< [16..16] Function Level Reset (FLR) for Function #0                       */
+            __OM uint32_t FLR_RESET1      : 1; /*!< [17..17] Function Level Reset (FLR) for Function #1                       */
+            __IM uint32_t FLR_REQ0        : 1; /*!< [18..18] Indicates FLR Request for Funtion #0                             */
+            __IM uint32_t FLR_REQ1        : 1; /*!< [19..19] Indicates FLR Request for Funtion #1                             */
+            uint32_t                      : 12;
+        } PCIE_MISC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCIE_MODE;         /*!< (@ 0x00000024) PCIe Mode Register                                         */
+
+        struct
+        {
+            __IOM uint32_t MODE_PORT : 1; /*!< [0..0] Device Type Select                                                 */
+            uint32_t                 : 31;
+        } PCIE_MODE_b;
+    };
+} R_PCIE_SPL0_Type;                       /*!< Size = 40 (0x28)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PCIE_LNK                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief PCIe Supplimental Settings for LINK MODE (R_PCIE_LNK)
+ */
+
+typedef struct                         /*!< (@ 0x80292060) R_PCIE_LNK Structure                                       */
+{
+    union
+    {
+        __IOM uint32_t PCIE_LINKMODE;  /*!< (@ 0x00000000) PCIe Link Mode Register                                    */
+
+        struct
+        {
+            uint32_t                   : 8;
+            __IOM uint32_t LINK_MASTER : 2; /*!< [9..8] Channel Configuration                                              */
+            uint32_t                   : 22;
+        } PCIE_LINKMODE_b;
+    };
+} R_PCIE_LNK_Type;                          /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                       R_XSPI0_MISC                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief xSPI0 Voltage and Size Registers (R_XSPI0_MISC)
+ */
+
+typedef struct                           /*!< (@ 0x80293000) R_XSPI0_MISC Structure                                     */
+{
+    union
+    {
+        __IOM uint32_t IOVOLCTL;         /*!< (@ 0x00000000) xSPI IO Voltage Control Register                           */
+
+        struct
+        {
+            __IOM uint32_t XSPI_MDV : 1; /*!< [0..0] XSPI_MDV                                                           */
+            uint32_t                : 31;
+        } IOVOLCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CS0ENDAD;             /*!< (@ 0x00000004) xSPI CS0 End Address Register                              */
+
+        struct
+        {
+            __IOM uint32_t CS0_END_ADD : 32; /*!< [31..0] CS0 (slave 0) area end address                                    */
+        } CS0ENDAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CS1STRAD;             /*!< (@ 0x00000008) xSPI CS1 Start Address Register                            */
+
+        struct
+        {
+            __IOM uint32_t CS1_STR_ADD : 32; /*!< [31..0] CS1 (slave 1) area start address                                  */
+        } CS1STRAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CS1ENDAD;             /*!< (@ 0x0000000C) xSPI CS1 End Address Register                              */
+
+        struct
+        {
+            __IOM uint32_t CS1_END_ADD : 32; /*!< [31..0] CS1 (slave 0) area end address                                    */
+        } CS1ENDAD_b;
+    };
+} R_XSPI0_MISC_Type;                         /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MD_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Operating Mode for Non-safety Area (R_MD_NS)
+ */
+
+typedef struct                         /*!< (@ 0x80294100) R_MD_NS Structure                                          */
+{
+    union
+    {
+        __IM uint32_t MD_MON;          /*!< (@ 0x00000000) Operating Mode Monitor Register                            */
+
+        struct
+        {
+            __IM uint32_t MDDMON  : 1; /*!< [0..0] MDD status flag                                                    */
+            uint32_t              : 3;
+            __IM uint32_t MDW0MON : 1; /*!< [4..4] MDW0 status flag                                                   */
+            __IM uint32_t MDW1MON : 1; /*!< [5..5] MDW1 status flag                                                   */
+            uint32_t              : 2;
+            __IM uint32_t MDP     : 1; /*!< [8..8] Package type                                                       */
+            uint32_t              : 3;
+            __IM uint32_t MD0MON  : 1; /*!< [12..12] MD0 pin status flag                                              */
+            __IM uint32_t MD1MON  : 1; /*!< [13..13] MD1 pin status flag                                              */
+            __IM uint32_t MD2MON  : 1; /*!< [14..14] MD2 pin status flag                                              */
+            uint32_t              : 1;
+            __IM uint32_t MDVMON  : 1; /*!< [16..16] MDV status flag                                                  */
+            uint32_t              : 15;
+        } MD_MON_b;
+    };
+} R_MD_NS_Type;                        /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_RWP_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Register Write Protection for Non-safety Area (R_RWP_NS)
+ */
+
+typedef struct                         /*!< (@ 0x80294200) R_RWP_NS Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t PRCRN;          /*!< (@ 0x00000000) Non_Safety Area Protect Register                           */
+
+        struct
+        {
+            __IOM uint32_t PRC0 : 1;   /*!< [0..0] Protect 0                                                          */
+            __IOM uint32_t PRC1 : 1;   /*!< [1..1] Protect 1                                                          */
+            __IOM uint32_t PRC2 : 1;   /*!< [2..2] Protect 2                                                          */
+            __IOM uint32_t PRC3 : 1;   /*!< [3..3] Protect 3                                                          */
+            uint32_t            : 4;
+            __OM uint32_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
+            uint32_t            : 16;
+        } PRCRN_b;
+    };
+} R_RWP_NS_Type;                       /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ICU_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Controller in Non Safety Domain (R_ICU_NS)
+ */
+
+typedef struct                         /*!< (@ 0x802A0000) R_ICU_NS Structure                                         */
+{
+    union
+    {
+        __OM uint32_t NS_SWINT;        /*!< (@ 0x00000000) Software Interrupt Register                                */
+
+        struct
+        {
+            __OM uint32_t IC0  : 1;    /*!< [0..0] Software Interrupt register                                        */
+            __OM uint32_t IC1  : 1;    /*!< [1..1] Software Interrupt register                                        */
+            __OM uint32_t IC2  : 1;    /*!< [2..2] Software Interrupt register                                        */
+            __OM uint32_t IC3  : 1;    /*!< [3..3] Software Interrupt register                                        */
+            __OM uint32_t IC4  : 1;    /*!< [4..4] Software Interrupt register                                        */
+            __OM uint32_t IC5  : 1;    /*!< [5..5] Software Interrupt register                                        */
+            __OM uint32_t IC6  : 1;    /*!< [6..6] Software Interrupt register                                        */
+            __OM uint32_t IC7  : 1;    /*!< [7..7] Software Interrupt register                                        */
+            __OM uint32_t IC8  : 1;    /*!< [8..8] Software Interrupt register                                        */
+            __OM uint32_t IC9  : 1;    /*!< [9..9] Software Interrupt register                                        */
+            __OM uint32_t IC10 : 1;    /*!< [10..10] Software Interrupt register                                      */
+            __OM uint32_t IC11 : 1;    /*!< [11..11] Software Interrupt register                                      */
+            __OM uint32_t IC12 : 1;    /*!< [12..12] Software Interrupt register                                      */
+            __OM uint32_t IC13 : 1;    /*!< [13..13] Software Interrupt register                                      */
+            uint32_t           : 18;
+        } NS_SWINT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NS_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register                     */
+
+        struct
+        {
+            __IOM uint32_t FLT0   : 1;   /*!< [0..0] Noise filter enable for IRQ0                                       */
+            __IOM uint32_t FLT1   : 1;   /*!< [1..1] Noise filter enable for IRQ1                                       */
+            __IOM uint32_t FLT2   : 1;   /*!< [2..2] Noise filter enable for IRQ2                                       */
+            __IOM uint32_t FLT3   : 1;   /*!< [3..3] Noise filter enable for IRQ3                                       */
+            __IOM uint32_t FLT4   : 1;   /*!< [4..4] Noise filter enable for IRQ4                                       */
+            __IOM uint32_t FLT5   : 1;   /*!< [5..5] Noise filter enable for IRQ5                                       */
+            __IOM uint32_t FLT6   : 1;   /*!< [6..6] Noise filter enable for IRQ6                                       */
+            __IOM uint32_t FLT7   : 1;   /*!< [7..7] Noise filter enable for IRQ7                                       */
+            __IOM uint32_t FLT8   : 1;   /*!< [8..8] Noise filter enable for IRQ8                                       */
+            __IOM uint32_t FLT9   : 1;   /*!< [9..9] Noise filter enable for IRQ9                                       */
+            __IOM uint32_t FLT10  : 1;   /*!< [10..10] Noise filter enable for IRQ10                                    */
+            __IOM uint32_t FLT11  : 1;   /*!< [11..11] Noise filter enable for IRQ11                                    */
+            __IOM uint32_t FLT12  : 1;   /*!< [12..12] Noise filter enable for IRQ12                                    */
+            __IOM uint32_t FLT13  : 1;   /*!< [13..13] Noise filter enable for IRQ13                                    */
+            __IOM uint32_t FLTDRQ : 1;   /*!< [14..14] Noise filter enable for External DMA request (DREQ)              */
+            uint32_t              : 17;
+        } NS_PORTNF_FLTSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NS_PORTNF_CLKSEL;  /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t CKSEL0    : 2; /*!< [1..0] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL1    : 2; /*!< [3..2] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL2    : 2; /*!< [5..4] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL3    : 2; /*!< [7..6] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL4    : 2; /*!< [9..8] Noise filter sampling clock selector                               */
+            __IOM uint32_t CKSEL5    : 2; /*!< [11..10] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL6    : 2; /*!< [13..12] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL7    : 2; /*!< [15..14] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL8    : 2; /*!< [17..16] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL9    : 2; /*!< [19..18] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL10   : 2; /*!< [21..20] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL11   : 2; /*!< [23..22] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL12   : 2; /*!< [25..24] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSEL13   : 2; /*!< [27..26] Noise filter sampling clock selector                             */
+            __IOM uint32_t CKSELDREQ : 2; /*!< [29..28] Noise filter sampling clock selector                             */
+            uint32_t                 : 2;
+        } NS_PORTNF_CLKSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NS_PORTNF_MD;   /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register                  */
+
+        struct
+        {
+            __IOM uint32_t MD0   : 2;  /*!< [1..0] Select detection mode for IRQ0                                     */
+            __IOM uint32_t MD1   : 2;  /*!< [3..2] Select detection mode for IRQ1                                     */
+            __IOM uint32_t MD2   : 2;  /*!< [5..4] Select detection mode for IRQ2                                     */
+            __IOM uint32_t MD3   : 2;  /*!< [7..6] Select detection mode for IRQ3                                     */
+            __IOM uint32_t MD4   : 2;  /*!< [9..8] Select detection mode for IRQ4                                     */
+            __IOM uint32_t MD5   : 2;  /*!< [11..10] Select detection mode for IRQ5                                   */
+            __IOM uint32_t MD6   : 2;  /*!< [13..12] Select detection mode for IRQ6                                   */
+            __IOM uint32_t MD7   : 2;  /*!< [15..14] Select detection mode for IRQ7                                   */
+            __IOM uint32_t MD8   : 2;  /*!< [17..16] Select detection mode for IRQ8                                   */
+            __IOM uint32_t MD9   : 2;  /*!< [19..18] Select detection mode for IRQ9                                   */
+            __IOM uint32_t MD10  : 2;  /*!< [21..20] Select detection mode for IRQ10                                  */
+            __IOM uint32_t MD11  : 2;  /*!< [23..22] Select detection mode for IRQ11                                  */
+            __IOM uint32_t MD12  : 2;  /*!< [25..24] Select detection mode for IRQ12                                  */
+            __IOM uint32_t MD13  : 2;  /*!< [27..26] Select detection mode for IRQ13                                  */
+            __IOM uint32_t MDDRQ : 2;  /*!< [29..28] Select detection mode for DREQ of DMAC                           */
+            uint32_t             : 2;
+        } NS_PORTNF_MD_b;
+    };
+    __IM uint32_t RESERVED[16];
+
+    union
+    {
+        __IOM uint32_t CA55ERR_E0MSK;   /*!< (@ 0x00000050) CA55 E0 Error Event Mask Register                          */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0  : 1; /*!< [0..0] E0_MK0                                                             */
+            __IOM uint32_t E0_MK1  : 1; /*!< [1..1] E0_MK1                                                             */
+            __IOM uint32_t E0_MK2  : 1; /*!< [2..2] E0_MK2                                                             */
+            __IOM uint32_t E0_MK3  : 1; /*!< [3..3] E0_MK3                                                             */
+            __IOM uint32_t E0_MK4  : 1; /*!< [4..4] E0_MK4                                                             */
+            __IOM uint32_t E0_MK5  : 1; /*!< [5..5] E0_MK5                                                             */
+            __IOM uint32_t E0_MK6  : 1; /*!< [6..6] E0_MK6                                                             */
+            __IOM uint32_t E0_MK7  : 1; /*!< [7..7] E0_MK7                                                             */
+            __IOM uint32_t E0_MK8  : 1; /*!< [8..8] E0_MK8                                                             */
+            __IOM uint32_t E0_MK9  : 1; /*!< [9..9] E0_MK9                                                             */
+            __IOM uint32_t E0_MK10 : 1; /*!< [10..10] E0_MK10                                                          */
+            __IOM uint32_t E0_MK11 : 1; /*!< [11..11] E0_MK11                                                          */
+            __IOM uint32_t E0_MK12 : 1; /*!< [12..12] E0_MK12                                                          */
+            uint32_t               : 19;
+        } CA55ERR_E0MSK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CA55ERR_E1MSK;   /*!< (@ 0x00000054) CA55 E1 Error Event Mask Register                          */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0  : 1; /*!< [0..0] E1_MK0                                                             */
+            __IOM uint32_t E1_MK1  : 1; /*!< [1..1] E1_MK1                                                             */
+            __IOM uint32_t E1_MK2  : 1; /*!< [2..2] E1_MK2                                                             */
+            __IOM uint32_t E1_MK3  : 1; /*!< [3..3] E1_MK3                                                             */
+            __IOM uint32_t E1_MK4  : 1; /*!< [4..4] E1_MK4                                                             */
+            __IOM uint32_t E1_MK5  : 1; /*!< [5..5] E1_MK5                                                             */
+            __IOM uint32_t E1_MK6  : 1; /*!< [6..6] E1_MK6                                                             */
+            __IOM uint32_t E1_MK7  : 1; /*!< [7..7] E1_MK7                                                             */
+            __IOM uint32_t E1_MK8  : 1; /*!< [8..8] E1_MK8                                                             */
+            __IOM uint32_t E1_MK9  : 1; /*!< [9..9] E1_MK9                                                             */
+            __IOM uint32_t E1_MK10 : 1; /*!< [10..10] E1_MK10                                                          */
+            __IOM uint32_t E1_MK11 : 1; /*!< [11..11] E1_MK11                                                          */
+            __IOM uint32_t E1_MK12 : 1; /*!< [12..12] E1_MK12                                                          */
+            uint32_t               : 19;
+        } CA55ERR_E1MSK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CA55ERR_RSTMSK;  /*!< (@ 0x00000058) CA55 Error Event Reset Mask Register                       */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1; /*!< [0..0] RS_MK0                                                             */
+            __IOM uint32_t RS_MK1  : 1; /*!< [1..1] RS_MK1                                                             */
+            __IOM uint32_t RS_MK2  : 1; /*!< [2..2] RS_MK2                                                             */
+            __IOM uint32_t RS_MK3  : 1; /*!< [3..3] RS_MK3                                                             */
+            __IOM uint32_t RS_MK4  : 1; /*!< [4..4] RS_MK4                                                             */
+            __IOM uint32_t RS_MK5  : 1; /*!< [5..5] RS_MK5                                                             */
+            __IOM uint32_t RS_MK6  : 1; /*!< [6..6] RS_MK6                                                             */
+            __IOM uint32_t RS_MK7  : 1; /*!< [7..7] RS_MK7                                                             */
+            __IOM uint32_t RS_MK8  : 1; /*!< [8..8] RS_MK8                                                             */
+            __IOM uint32_t RS_MK9  : 1; /*!< [9..9] RS_MK9                                                             */
+            __IOM uint32_t RS_MK10 : 1; /*!< [10..10] RS_MK10                                                          */
+            __IOM uint32_t RS_MK11 : 1; /*!< [11..11] RS_MK11                                                          */
+            __IOM uint32_t RS_MK12 : 1; /*!< [12..12] RS_MK12                                                          */
+            uint32_t               : 19;
+        } CA55ERR_RSTMSK_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __OM uint32_t CA55ERR_CLR;     /*!< (@ 0x00000060) CA55 Error Event Status Clear Register                     */
+
+        struct
+        {
+            __OM uint32_t ER_CL0  : 1; /*!< [0..0] ER_CL0                                                             */
+            __OM uint32_t ER_CL1  : 1; /*!< [1..1] ER_CL1                                                             */
+            __OM uint32_t ER_CL2  : 1; /*!< [2..2] ER_CL2                                                             */
+            __OM uint32_t ER_CL3  : 1; /*!< [3..3] ER_CL3                                                             */
+            __OM uint32_t ER_CL4  : 1; /*!< [4..4] ER_CL4                                                             */
+            __OM uint32_t ER_CL5  : 1; /*!< [5..5] ER_CL5                                                             */
+            __OM uint32_t ER_CL6  : 1; /*!< [6..6] ER_CL6                                                             */
+            __OM uint32_t ER_CL7  : 1; /*!< [7..7] ER_CL7                                                             */
+            __OM uint32_t ER_CL8  : 1; /*!< [8..8] ER_CL8                                                             */
+            __OM uint32_t ER_CL9  : 1; /*!< [9..9] ER_CL9                                                             */
+            __OM uint32_t ER_CL10 : 1; /*!< [10..10] ER_CL10                                                          */
+            __OM uint32_t ER_CL11 : 1; /*!< [11..11] ER_CL11                                                          */
+            __OM uint32_t ER_CL12 : 1; /*!< [12..12] ER_CL12                                                          */
+            uint32_t              : 19;
+        } CA55ERR_CLR_b;
+    };
+
+    union
+    {
+        __IM uint32_t CA55ERR_STAT;    /*!< (@ 0x00000064) CA55 Error Event Status Register                           */
+
+        struct
+        {
+            __IM uint32_t ER_ST0  : 1; /*!< [0..0] ER_ST0                                                             */
+            __IM uint32_t ER_ST1  : 1; /*!< [1..1] ER_ST1                                                             */
+            __IM uint32_t ER_ST2  : 1; /*!< [2..2] ER_ST2                                                             */
+            __IM uint32_t ER_ST3  : 1; /*!< [3..3] ER_ST3                                                             */
+            __IM uint32_t ER_ST4  : 1; /*!< [4..4] ER_ST4                                                             */
+            __IM uint32_t ER_ST5  : 1; /*!< [5..5] ER_ST5                                                             */
+            __IM uint32_t ER_ST6  : 1; /*!< [6..6] ER_ST6                                                             */
+            __IM uint32_t ER_ST7  : 1; /*!< [7..7] ER_ST7                                                             */
+            __IM uint32_t ER_ST8  : 1; /*!< [8..8] ER_ST8                                                             */
+            __IM uint32_t ER_ST9  : 1; /*!< [9..9] ER_ST9                                                             */
+            __IM uint32_t ER_ST10 : 1; /*!< [10..10] ER_ST10                                                          */
+            __IM uint32_t ER_ST11 : 1; /*!< [11..11] ER_ST11                                                          */
+            __IM uint32_t ER_ST12 : 1; /*!< [12..12] ER_ST12                                                          */
+            uint32_t              : 19;
+        } CA55ERR_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CR520ERR_E0MSK;  /*!< (@ 0x00000068) CR52 CPU0 E0 Error Event Mask Register                     */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0 : 1;  /*!< [0..0] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK1 : 1;  /*!< [1..1] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK2 : 1;  /*!< [2..2] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK3 : 1;  /*!< [3..3] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK4 : 1;  /*!< [4..4] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK5 : 1;  /*!< [5..5] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK6 : 1;  /*!< [6..6] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK7 : 1;  /*!< [7..7] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK8 : 1;  /*!< [8..8] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK9 : 1;  /*!< [9..9] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an CR520_ERR0 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            uint32_t : 6;
+        } CR520ERR_E0MSK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CR520ERR_E1MSK;  /*!< (@ 0x0000006C) CR52 CPU0 E1 Error Event Mask Register                     */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0 : 1;  /*!< [0..0] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK1 : 1;  /*!< [1..1] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK2 : 1;  /*!< [2..2] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK3 : 1;  /*!< [3..3] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK4 : 1;  /*!< [4..4] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK5 : 1;  /*!< [5..5] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK6 : 1;  /*!< [6..6] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK7 : 1;  /*!< [7..7] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK8 : 1;  /*!< [8..8] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK9 : 1;  /*!< [9..9] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an CR520_ERR1 event for
+                                         *   NS_CR520ERR_STAT                                                          */
+            uint32_t : 6;
+        } CR520ERR_E1MSK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CR520ERR_RSTMSK; /*!< (@ 0x00000070) CR52 CPU0 Error Event Reset Mask Register                  */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1; /*!< [0..0] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK1  : 1; /*!< [1..1] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK2  : 1; /*!< [2..2] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK3  : 1; /*!< [3..3] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK4  : 1; /*!< [4..4] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK5  : 1; /*!< [5..5] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK6  : 1; /*!< [6..6] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK7  : 1; /*!< [7..7] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK8  : 1; /*!< [8..8] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK9  : 1; /*!< [9..9] Mask captured error status as a reset event for NS_CR520ERR_STAT   */
+            __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for NS_CR520ERR_STAT */
+            uint32_t               : 6;
+        } CR520ERR_RSTMSK_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __OM uint32_t CR520ERR_CLR;    /*!< (@ 0x00000078) CR52 CPU0 Error Event Status Clear Register                */
+
+        struct
+        {
+            __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL8 : 1;  /*!< [8..8] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL17 : 1; /*!< [17..17] ER_CL17                                                          */
+            __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for NS_CR520ERR_STAT register
+                                        *   by writing 1                                                              */
+            uint32_t : 6;
+        } CR520ERR_CLR_b;
+    };
+
+    union
+    {
+        __IM uint32_t CR520ERR_STAT;   /*!< (@ 0x0000007C) CR52 CPU0 Error Event Status Register                      */
+
+        struct
+        {
+            __IM uint32_t ER_ST0 : 1;  /*!< [0..0] Indicate captured error status for ERREVENT0 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST1 : 1;  /*!< [1..1] Indicate captured error status for ERREVENT1 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST2 : 1;  /*!< [2..2] Indicate captured error status for ERREVENT2 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST3 : 1;  /*!< [3..3] Indicate captured error status for ERREVENT3 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST4 : 1;  /*!< [4..4] Indicate captured error status for ERREVENT4 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST5 : 1;  /*!< [5..5] Indicate captured error status for ERREVENT5 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST6 : 1;  /*!< [6..6] Indicate captured error status for ERREVENT6 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST7 : 1;  /*!< [7..7] Indicate captured error status for ERREVENT7 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST8 : 1;  /*!< [8..8] Indicate captured error status for ERREVENT8 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST9 : 1;  /*!< [9..9] Indicate captured error status for ERREVENT9 from Cortex-R52
+                                        *   CPU0                                                                      */
+            __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for ERREVENT10 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for ERREVENT11 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for ERREVENT12 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for ERREVENT13 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for ERREVENT14 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for ERREVENT15 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for ERREVENT16 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for ERREVENT17 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for ERREVENT18 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for ERREVENT19 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for ERREVENT20 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for ERREVENT21 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for ERREVENT22 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for ERREVENT23 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for ERREVENT24 from
+                                        *   Cortex-R52 CPU0                                                           */
+            __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for ERREVENT25 from
+                                        *   Cortex-R52 CPU0                                                           */
+            uint32_t : 6;
+        } CR520ERR_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CR521ERR_E0MSK;  /*!< (@ 0x00000080) CR52 CPU1 E0 Error Event Mask Register                     */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0 : 1;  /*!< [0..0] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK1 : 1;  /*!< [1..1] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK2 : 1;  /*!< [2..2] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK3 : 1;  /*!< [3..3] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK4 : 1;  /*!< [4..4] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK5 : 1;  /*!< [5..5] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK6 : 1;  /*!< [6..6] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK7 : 1;  /*!< [7..7] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK8 : 1;  /*!< [8..8] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK9 : 1;  /*!< [9..9] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an CR521_ERR0 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            uint32_t : 6;
+        } CR521ERR_E0MSK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CR521ERR_E1MSK;  /*!< (@ 0x00000084) CR52 CPU1 E1 Error Event Mask Register                     */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0 : 1;  /*!< [0..0] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK1 : 1;  /*!< [1..1] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK2 : 1;  /*!< [2..2] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK3 : 1;  /*!< [3..3] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK4 : 1;  /*!< [4..4] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK5 : 1;  /*!< [5..5] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK6 : 1;  /*!< [6..6] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK7 : 1;  /*!< [7..7] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK8 : 1;  /*!< [8..8] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK9 : 1;  /*!< [9..9] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an CR521_ERR1 event for
+                                         *   NS_CR521ERR_STAT                                                          */
+            uint32_t : 6;
+        } CR521ERR_E1MSK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CR521ERR_RSTMSK; /*!< (@ 0x00000088) CR52 CPU1 Error Event Reset Mask Register                  */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1; /*!< [0..0] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK1  : 1; /*!< [1..1] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK2  : 1; /*!< [2..2] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK3  : 1; /*!< [3..3] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK4  : 1; /*!< [4..4] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK5  : 1; /*!< [5..5] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK6  : 1; /*!< [6..6] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK7  : 1; /*!< [7..7] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK8  : 1; /*!< [8..8] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK9  : 1; /*!< [9..9] Mask captured error status as a reset event for NS_CR521ERR_STAT   */
+            __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for NS_CR521ERR_STAT */
+            uint32_t               : 6;
+        } CR521ERR_RSTMSK_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __OM uint32_t CR521ERR_CLR;    /*!< (@ 0x00000090) CR52 CPU1 Error Event Status Clear Register                */
+
+        struct
+        {
+            __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL8 : 1;  /*!< [8..8] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for NS_CR521ERR_STAT register
+                                        *   by writing 1                                                              */
+            uint32_t : 6;
+        } CR521ERR_CLR_b;
+    };
+
+    union
+    {
+        __IM uint32_t CR521ERR_STAT;   /*!< (@ 0x00000094) CR52 CPU1 Error Event Status Register                      */
+
+        struct
+        {
+            __IM uint32_t ER_ST0 : 1;  /*!< [0..0] Indicate captured error status for ERREVENT0 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST1 : 1;  /*!< [1..1] Indicate captured error status for ERREVENT1 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST2 : 1;  /*!< [2..2] Indicate captured error status for ERREVENT2 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST3 : 1;  /*!< [3..3] Indicate captured error status for ERREVENT3 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST4 : 1;  /*!< [4..4] Indicate captured error status for ERREVENT4 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST5 : 1;  /*!< [5..5] Indicate captured error status for ERREVENT5 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST6 : 1;  /*!< [6..6] Indicate captured error status for ERREVENT6 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST7 : 1;  /*!< [7..7] Indicate captured error status for ERREVENT7 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST8 : 1;  /*!< [8..8] Indicate captured error status for ERREVENT8 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST9 : 1;  /*!< [9..9] Indicate captured error status for ERREVENT9 from Cortex-R52
+                                        *   CPU1                                                                      */
+            __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for ERREVENT10 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for ERREVENT11 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for ERREVENT12 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for ERREVENT13 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for ERREVENT14 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for ERREVENT15 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for ERREVENT16 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for ERREVENT17 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for ERREVENT18 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for ERREVENT19 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for ERREVENT20 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for ERREVENT21 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for ERREVENT22 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for ERREVENT23 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for ERREVENT24 from
+                                        *   Cortex-R52 CPU1                                                           */
+            __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for ERREVENT25 from
+                                        *   Cortex-R52 CPU1                                                           */
+            uint32_t : 6;
+        } CR521ERR_STAT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PERIERR_E0MSK[3]; /*!< (@ 0x00000098) PERIERR_E0MSKn Peripheral E0 Error Event Mask
+                                          *                  Register n (n = 0 to 2)                                    */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0  : 1;  /*!< [0..0] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK1  : 1;  /*!< [1..1] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK2  : 1;  /*!< [2..2] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK3  : 1;  /*!< [3..3] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK4  : 1;  /*!< [4..4] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK5  : 1;  /*!< [5..5] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK6  : 1;  /*!< [6..6] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK7  : 1;  /*!< [7..7] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK8  : 1;  /*!< [8..8] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK9  : 1;  /*!< [9..9] Mask captured error status as PERI_ERR0 event for PERIERR_STATn    */
+            __IOM uint32_t E0_MK10 : 1;  /*!< [10..10] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK11 : 1;  /*!< [11..11] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK12 : 1;  /*!< [12..12] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK13 : 1;  /*!< [13..13] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK14 : 1;  /*!< [14..14] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK15 : 1;  /*!< [15..15] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK16 : 1;  /*!< [16..16] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK17 : 1;  /*!< [17..17] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK18 : 1;  /*!< [18..18] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK19 : 1;  /*!< [19..19] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK20 : 1;  /*!< [20..20] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK21 : 1;  /*!< [21..21] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK22 : 1;  /*!< [22..22] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK23 : 1;  /*!< [23..23] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK24 : 1;  /*!< [24..24] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK25 : 1;  /*!< [25..25] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK26 : 1;  /*!< [26..26] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK27 : 1;  /*!< [27..27] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK28 : 1;  /*!< [28..28] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK29 : 1;  /*!< [29..29] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK30 : 1;  /*!< [30..30] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+            __IOM uint32_t E0_MK31 : 1;  /*!< [31..31] Mask captured error status as PERI_ERR0 event for PERIERR_STATn  */
+        } PERIERR_E0MSK_b[3];
+    };
+
+    union
+    {
+        __IOM uint32_t PERIERR_E1MSK[3]; /*!< (@ 0x000000A4) PERIERR_E1MSKn Peripheral E1 Error Event Mask
+                                          *                  Register n (n = 0 to 2)                                    */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0  : 1;  /*!< [0..0] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK1  : 1;  /*!< [1..1] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK2  : 1;  /*!< [2..2] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK3  : 1;  /*!< [3..3] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK4  : 1;  /*!< [4..4] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK5  : 1;  /*!< [5..5] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK6  : 1;  /*!< [6..6] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK7  : 1;  /*!< [7..7] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK8  : 1;  /*!< [8..8] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK9  : 1;  /*!< [9..9] Mask captured error status as PERI_ERR1 event for PERIERR_STATn    */
+            __IOM uint32_t E1_MK10 : 1;  /*!< [10..10] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK11 : 1;  /*!< [11..11] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK12 : 1;  /*!< [12..12] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK13 : 1;  /*!< [13..13] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK14 : 1;  /*!< [14..14] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK15 : 1;  /*!< [15..15] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK16 : 1;  /*!< [16..16] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK17 : 1;  /*!< [17..17] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK18 : 1;  /*!< [18..18] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK19 : 1;  /*!< [19..19] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK20 : 1;  /*!< [20..20] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK21 : 1;  /*!< [21..21] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK22 : 1;  /*!< [22..22] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK23 : 1;  /*!< [23..23] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK24 : 1;  /*!< [24..24] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK25 : 1;  /*!< [25..25] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK26 : 1;  /*!< [26..26] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK27 : 1;  /*!< [27..27] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK28 : 1;  /*!< [28..28] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK29 : 1;  /*!< [29..29] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK30 : 1;  /*!< [30..30] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+            __IOM uint32_t E1_MK31 : 1;  /*!< [31..31] Mask captured error status as PERI_ERR1 event for PERIERR_STATn  */
+        } PERIERR_E1MSK_b[3];
+    };
+
+    union
+    {
+        __IOM uint32_t PERIERR_RSTMSK[3]; /*!< (@ 0x000000B0) PERIERR_RSTMSKn Peripheral Error Event Reset
+                                           *                  Mask Register n (n = 0 to 2)                               */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1;   /*!< [0..0] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK1  : 1;   /*!< [1..1] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK2  : 1;   /*!< [2..2] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK3  : 1;   /*!< [3..3] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK4  : 1;   /*!< [4..4] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK5  : 1;   /*!< [5..5] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK6  : 1;   /*!< [6..6] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK7  : 1;   /*!< [7..7] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK8  : 1;   /*!< [8..8] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK9  : 1;   /*!< [9..9] Mask captured error status as a reset event for PERIERR_STATn      */
+            __IOM uint32_t RS_MK10 : 1;   /*!< [10..10] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK11 : 1;   /*!< [11..11] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK12 : 1;   /*!< [12..12] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK13 : 1;   /*!< [13..13] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK14 : 1;   /*!< [14..14] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK15 : 1;   /*!< [15..15] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK16 : 1;   /*!< [16..16] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK17 : 1;   /*!< [17..17] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK18 : 1;   /*!< [18..18] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK19 : 1;   /*!< [19..19] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK20 : 1;   /*!< [20..20] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK21 : 1;   /*!< [21..21] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK22 : 1;   /*!< [22..22] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK23 : 1;   /*!< [23..23] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK24 : 1;   /*!< [24..24] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK25 : 1;   /*!< [25..25] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK26 : 1;   /*!< [26..26] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK27 : 1;   /*!< [27..27] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK28 : 1;   /*!< [28..28] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK29 : 1;   /*!< [29..29] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK30 : 1;   /*!< [30..30] Mask captured error status as a reset event for PERIERR_STATn    */
+            __IOM uint32_t RS_MK31 : 1;   /*!< [31..31] Mask captured error status as a reset event for PERIERR_STATn    */
+        } PERIERR_RSTMSK_b[3];
+    };
+    __IM uint32_t RESERVED4[3];
+
+    union
+    {
+        __OM uint32_t PERIERR_CLR[3];  /*!< (@ 0x000000C8) PERIERR_CLRn Peripheral Error Event Status Clear
+                                        *                  Register n (n = 0 to 2)                                    */
+
+        struct
+        {
+            __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL8 : 1;  /*!< [8..8] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL26 : 1; /*!< [26..26] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL29 : 1; /*!< [29..29] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL30 : 1; /*!< [30..30] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL31 : 1; /*!< [31..31] Clear captured error status for PERIERR_STATn register
+                                        *   by writing 1                                                              */
+        } PERIERR_CLR_b[3];
+    };
+
+    union
+    {
+        __IM uint32_t PERIERR_STAT[3]; /*!< (@ 0x000000D4) PERIERR_STATn Peripheral Error Event Status Register
+                                        *                  n (n = 0 to 2)                                             */
+
+        struct
+        {
+            __IM uint32_t ER_ST0 : 1;  /*!< [0..0] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST1 : 1;  /*!< [1..1] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST2 : 1;  /*!< [2..2] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST3 : 1;  /*!< [3..3] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST4 : 1;  /*!< [4..4] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST5 : 1;  /*!< [5..5] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST6 : 1;  /*!< [6..6] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST7 : 1;  /*!< [7..7] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST8 : 1;  /*!< [8..8] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST9 : 1;  /*!< [9..9] Indicate captured error status for error event from peripheral
+                                        *   modules                                                                   */
+            __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST26 : 1; /*!< [26..26] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+            __IM uint32_t ER_ST31 : 1; /*!< [31..31] Indicate captured error status for error event from
+                                        *   peripheral modules                                                        */
+        } PERIERR_STAT_b[3];
+    };
+
+    union
+    {
+        __IOM uint32_t DSMIFERR_E0MSK[12]; /*!< (@ 0x000000E0) DSMIFERR_E0MSKn DSMIF E0 Error Event Mask Register
+                                            *                  n (n = 0 to 11)                                            */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0  : 1;    /*!< [0..0] E0_MK0                                                             */
+            __IOM uint32_t E0_MK1  : 1;    /*!< [1..1] E0_MK1                                                             */
+            __IOM uint32_t E0_MK2  : 1;    /*!< [2..2] E0_MK2                                                             */
+            __IOM uint32_t E0_MK3  : 1;    /*!< [3..3] E0_MK3                                                             */
+            __IOM uint32_t E0_MK4  : 1;    /*!< [4..4] E0_MK4                                                             */
+            __IOM uint32_t E0_MK5  : 1;    /*!< [5..5] E0_MK5                                                             */
+            __IOM uint32_t E0_MK6  : 1;    /*!< [6..6] E0_MK6                                                             */
+            __IOM uint32_t E0_MK7  : 1;    /*!< [7..7] E0_MK7                                                             */
+            __IOM uint32_t E0_MK8  : 1;    /*!< [8..8] E0_MK8                                                             */
+            __IOM uint32_t E0_MK9  : 1;    /*!< [9..9] E0_MK9                                                             */
+            __IOM uint32_t E0_MK10 : 1;    /*!< [10..10] E0_MK10                                                          */
+            __IOM uint32_t E0_MK11 : 1;    /*!< [11..11] E0_MK11                                                          */
+            __IOM uint32_t E0_MK12 : 1;    /*!< [12..12] E0_MK12                                                          */
+            __IOM uint32_t E0_MK13 : 1;    /*!< [13..13] E0_MK13                                                          */
+            __IOM uint32_t E0_MK14 : 1;    /*!< [14..14] E0_MK14                                                          */
+            __IOM uint32_t E0_MK15 : 1;    /*!< [15..15] E0_MK15                                                          */
+            __IOM uint32_t E0_MK16 : 1;    /*!< [16..16] E0_MK16                                                          */
+            __IOM uint32_t E0_MK17 : 1;    /*!< [17..17] E0_MK17                                                          */
+            __IOM uint32_t E0_MK18 : 1;    /*!< [18..18] E0_MK18                                                          */
+            __IOM uint32_t E0_MK19 : 1;    /*!< [19..19] E0_MK19                                                          */
+            __IOM uint32_t E0_MK20 : 1;    /*!< [20..20] E0_MK20                                                          */
+            __IOM uint32_t E0_MK21 : 1;    /*!< [21..21] E0_MK21                                                          */
+            __IOM uint32_t E0_MK22 : 1;    /*!< [22..22] E0_MK22                                                          */
+            __IOM uint32_t E0_MK23 : 1;    /*!< [23..23] E0_MK23                                                          */
+            __IOM uint32_t E0_MK24 : 1;    /*!< [24..24] E0_MK24                                                          */
+            __IOM uint32_t E0_MK25 : 1;    /*!< [25..25] E0_MK25                                                          */
+            __IOM uint32_t E0_MK26 : 1;    /*!< [26..26] E0_MK26                                                          */
+            __IOM uint32_t E0_MK27 : 1;    /*!< [27..27] E0_MK27                                                          */
+            __IOM uint32_t E0_MK28 : 1;    /*!< [28..28] E0_MK28                                                          */
+            __IOM uint32_t E0_MK29 : 1;    /*!< [29..29] E0_MK29                                                          */
+            __IOM uint32_t E0_MK30 : 1;    /*!< [30..30] E0_MK30                                                          */
+            __IOM uint32_t E0_MK31 : 1;    /*!< [31..31] E0_MK31                                                          */
+        } DSMIFERR_E0MSK_b[12];
+    };
+
+    union
+    {
+        __IOM uint32_t DSMIFERR_E1MSK[12]; /*!< (@ 0x00000110) DSMIFERR_E1MSKn DSMIF E1 Error Event Mask Register
+                                            *                  n (n = 0 to 11)                                            */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0  : 1;    /*!< [0..0] E1_MK0                                                             */
+            __IOM uint32_t E1_MK1  : 1;    /*!< [1..1] E1_MK1                                                             */
+            __IOM uint32_t E1_MK2  : 1;    /*!< [2..2] E1_MK2                                                             */
+            __IOM uint32_t E1_MK3  : 1;    /*!< [3..3] E1_MK3                                                             */
+            __IOM uint32_t E1_MK4  : 1;    /*!< [4..4] E1_MK4                                                             */
+            __IOM uint32_t E1_MK5  : 1;    /*!< [5..5] E1_MK5                                                             */
+            __IOM uint32_t E1_MK6  : 1;    /*!< [6..6] E1_MK6                                                             */
+            __IOM uint32_t E1_MK7  : 1;    /*!< [7..7] E1_MK7                                                             */
+            __IOM uint32_t E1_MK8  : 1;    /*!< [8..8] E1_MK8                                                             */
+            __IOM uint32_t E1_MK9  : 1;    /*!< [9..9] E1_MK9                                                             */
+            __IOM uint32_t E1_MK10 : 1;    /*!< [10..10] E1_MK10                                                          */
+            __IOM uint32_t E1_MK11 : 1;    /*!< [11..11] E1_MK11                                                          */
+            __IOM uint32_t E1_MK12 : 1;    /*!< [12..12] E1_MK12                                                          */
+            __IOM uint32_t E1_MK13 : 1;    /*!< [13..13] E1_MK13                                                          */
+            __IOM uint32_t E1_MK14 : 1;    /*!< [14..14] E1_MK14                                                          */
+            __IOM uint32_t E1_MK15 : 1;    /*!< [15..15] E1_MK15                                                          */
+            __IOM uint32_t E1_MK16 : 1;    /*!< [16..16] E1_MK16                                                          */
+            __IOM uint32_t E1_MK17 : 1;    /*!< [17..17] E1_MK17                                                          */
+            __IOM uint32_t E1_MK18 : 1;    /*!< [18..18] E1_MK18                                                          */
+            __IOM uint32_t E1_MK19 : 1;    /*!< [19..19] E1_MK19                                                          */
+            __IOM uint32_t E1_MK20 : 1;    /*!< [20..20] E1_MK20                                                          */
+            __IOM uint32_t E1_MK21 : 1;    /*!< [21..21] E1_MK21                                                          */
+            __IOM uint32_t E1_MK22 : 1;    /*!< [22..22] E1_MK22                                                          */
+            __IOM uint32_t E1_MK23 : 1;    /*!< [23..23] E1_MK23                                                          */
+            __IOM uint32_t E1_MK24 : 1;    /*!< [24..24] E1_MK24                                                          */
+            __IOM uint32_t E1_MK25 : 1;    /*!< [25..25] E1_MK25                                                          */
+            __IOM uint32_t E1_MK26 : 1;    /*!< [26..26] E1_MK26                                                          */
+            __IOM uint32_t E1_MK27 : 1;    /*!< [27..27] E1_MK27                                                          */
+            __IOM uint32_t E1_MK28 : 1;    /*!< [28..28] E1_MK28                                                          */
+            __IOM uint32_t E1_MK29 : 1;    /*!< [29..29] E1_MK29                                                          */
+            __IOM uint32_t E1_MK30 : 1;    /*!< [30..30] E1_MK30                                                          */
+            __IOM uint32_t E1_MK31 : 1;    /*!< [31..31] E1_MK31                                                          */
+        } DSMIFERR_E1MSK_b[12];
+    };
+
+    union
+    {
+        __IOM uint32_t DSMIFERR_RSTMSK[12]; /*!< (@ 0x00000140) DSMIFERR_RSTMSKn DSMIF Error Event Reset Mask
+                                             *                  Register n (n = 0 to 11)                                   */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1;     /*!< [0..0] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK1  : 1;     /*!< [1..1] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK2  : 1;     /*!< [2..2] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK3  : 1;     /*!< [3..3] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK4  : 1;     /*!< [4..4] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK5  : 1;     /*!< [5..5] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK6  : 1;     /*!< [6..6] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK7  : 1;     /*!< [7..7] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK8  : 1;     /*!< [8..8] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK9  : 1;     /*!< [9..9] Mask captured error status as a reset event for DSMIFERR_STATn     */
+            __IOM uint32_t RS_MK10 : 1;     /*!< [10..10] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK11 : 1;     /*!< [11..11] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK12 : 1;     /*!< [12..12] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK13 : 1;     /*!< [13..13] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK14 : 1;     /*!< [14..14] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK15 : 1;     /*!< [15..15] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK16 : 1;     /*!< [16..16] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK17 : 1;     /*!< [17..17] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK18 : 1;     /*!< [18..18] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK19 : 1;     /*!< [19..19] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK20 : 1;     /*!< [20..20] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK21 : 1;     /*!< [21..21] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK22 : 1;     /*!< [22..22] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK23 : 1;     /*!< [23..23] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK24 : 1;     /*!< [24..24] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK25 : 1;     /*!< [25..25] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK26 : 1;     /*!< [26..26] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK27 : 1;     /*!< [27..27] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK28 : 1;     /*!< [28..28] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK29 : 1;     /*!< [29..29] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK30 : 1;     /*!< [30..30] Mask captured error status as a reset event for DSMIFERR_STATn   */
+            __IOM uint32_t RS_MK31 : 1;     /*!< [31..31] Mask captured error status as a reset event for DSMIFERR_STATn   */
+        } DSMIFERR_RSTMSK_b[12];
+    };
+    __IM uint32_t RESERVED5[12];
+
+    union
+    {
+        __OM uint32_t DSMIFERR_CLR[12]; /*!< (@ 0x000001A0) DSMIFERR_CLRn DSMIF Error Event Status Clear
+                                         *                  Register n (n = 0 to 11)                                   */
+
+        struct
+        {
+            __OM uint32_t ER_CL0 : 1;   /*!< [0..0] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL1 : 1;   /*!< [1..1] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL2 : 1;   /*!< [2..2] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL3 : 1;   /*!< [3..3] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL4 : 1;   /*!< [4..4] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL5 : 1;   /*!< [5..5] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL6 : 1;   /*!< [6..6] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL7 : 1;   /*!< [7..7] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL8 : 1;   /*!< [8..8] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL9 : 1;   /*!< [9..9] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL10 : 1;  /*!< [10..10] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL11 : 1;  /*!< [11..11] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL12 : 1;  /*!< [12..12] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL13 : 1;  /*!< [13..13] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL14 : 1;  /*!< [14..14] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL15 : 1;  /*!< [15..15] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL16 : 1;  /*!< [16..16] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL17 : 1;  /*!< [17..17] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL18 : 1;  /*!< [18..18] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL19 : 1;  /*!< [19..19] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL20 : 1;  /*!< [20..20] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL21 : 1;  /*!< [21..21] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL22 : 1;  /*!< [22..22] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL23 : 1;  /*!< [23..23] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL24 : 1;  /*!< [24..24] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL25 : 1;  /*!< [25..25] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL26 : 1;  /*!< [26..26] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL27 : 1;  /*!< [27..27] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL28 : 1;  /*!< [28..28] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL29 : 1;  /*!< [29..29] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL30 : 1;  /*!< [30..30] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+            __OM uint32_t ER_CL31 : 1;  /*!< [31..31] Clear captured error status for DSMIFERR_STATn register
+                                         *   by writing 1                                                              */
+        } DSMIFERR_CLR_b[12];
+    };
+
+    union
+    {
+        __IM uint32_t DSMIFERR_STAT[12]; /*!< (@ 0x000001D0) DSMIFERR_STATn DSMIF Error Event Status Register
+                                          *                  n (n = 0 to 11)                                            */
+
+        struct
+        {
+            __IM uint32_t ER_ST0 : 1;    /*!< [0..0] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST1 : 1;    /*!< [1..1] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST2 : 1;    /*!< [2..2] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST3 : 1;    /*!< [3..3] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST4 : 1;    /*!< [4..4] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST5 : 1;    /*!< [5..5] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST6 : 1;    /*!< [6..6] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST7 : 1;    /*!< [7..7] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST8 : 1;    /*!< [8..8] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST9 : 1;    /*!< [9..9] Indicate captured error status for error event from DSMIF
+                                          *   modules                                                                   */
+            __IM uint32_t ER_ST10 : 1;   /*!< [10..10] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST11 : 1;   /*!< [11..11] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST12 : 1;   /*!< [12..12] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST13 : 1;   /*!< [13..13] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST14 : 1;   /*!< [14..14] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST15 : 1;   /*!< [15..15] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST16 : 1;   /*!< [16..16] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST17 : 1;   /*!< [17..17] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST18 : 1;   /*!< [18..18] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST19 : 1;   /*!< [19..19] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST20 : 1;   /*!< [20..20] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST21 : 1;   /*!< [21..21] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST22 : 1;   /*!< [22..22] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST23 : 1;   /*!< [23..23] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST24 : 1;   /*!< [24..24] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST25 : 1;   /*!< [25..25] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST26 : 1;   /*!< [26..26] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST27 : 1;   /*!< [27..27] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST28 : 1;   /*!< [28..28] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST29 : 1;   /*!< [29..29] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST30 : 1;   /*!< [30..30] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+            __IM uint32_t ER_ST31 : 1;   /*!< [31..31] Indicate captured error status for error event from
+                                          *   DSMIF modules                                                             */
+        } DSMIFERR_STAT_b[12];
+    };
+
+    union
+    {
+        __IOM uint32_t ENCIFERR_E0MSK[5]; /*!< (@ 0x00000200) ENCIFERR_E0MSKn ENCIF E0 Error Event Mask Register
+                                           *                  n (n = 0 to 4)                                             */
+
+        struct
+        {
+            __IOM uint32_t E0_MK0  : 1;   /*!< [0..0] E0_MK0                                                             */
+            __IOM uint32_t E0_MK1  : 1;   /*!< [1..1] E0_MK1                                                             */
+            __IOM uint32_t E0_MK2  : 1;   /*!< [2..2] E0_MK2                                                             */
+            __IOM uint32_t E0_MK3  : 1;   /*!< [3..3] E0_MK3                                                             */
+            __IOM uint32_t E0_MK4  : 1;   /*!< [4..4] E0_MK4                                                             */
+            __IOM uint32_t E0_MK5  : 1;   /*!< [5..5] E0_MK5                                                             */
+            __IOM uint32_t E0_MK6  : 1;   /*!< [6..6] E0_MK6                                                             */
+            __IOM uint32_t E0_MK7  : 1;   /*!< [7..7] E0_MK7                                                             */
+            __IOM uint32_t E0_MK8  : 1;   /*!< [8..8] E0_MK8                                                             */
+            __IOM uint32_t E0_MK9  : 1;   /*!< [9..9] E0_MK9                                                             */
+            __IOM uint32_t E0_MK10 : 1;   /*!< [10..10] E0_MK10                                                          */
+            __IOM uint32_t E0_MK11 : 1;   /*!< [11..11] E0_MK11                                                          */
+            __IOM uint32_t E0_MK12 : 1;   /*!< [12..12] E0_MK12                                                          */
+            __IOM uint32_t E0_MK13 : 1;   /*!< [13..13] E0_MK13                                                          */
+            __IOM uint32_t E0_MK14 : 1;   /*!< [14..14] E0_MK14                                                          */
+            __IOM uint32_t E0_MK15 : 1;   /*!< [15..15] E0_MK15                                                          */
+            __IOM uint32_t E0_MK16 : 1;   /*!< [16..16] E0_MK16                                                          */
+            __IOM uint32_t E0_MK17 : 1;   /*!< [17..17] E0_MK17                                                          */
+            __IOM uint32_t E0_MK18 : 1;   /*!< [18..18] E0_MK18                                                          */
+            __IOM uint32_t E0_MK19 : 1;   /*!< [19..19] E0_MK19                                                          */
+            __IOM uint32_t E0_MK20 : 1;   /*!< [20..20] E0_MK20                                                          */
+            __IOM uint32_t E0_MK21 : 1;   /*!< [21..21] E0_MK21                                                          */
+            __IOM uint32_t E0_MK22 : 1;   /*!< [22..22] E0_MK22                                                          */
+            __IOM uint32_t E0_MK23 : 1;   /*!< [23..23] E0_MK23                                                          */
+            __IOM uint32_t E0_MK24 : 1;   /*!< [24..24] E0_MK24                                                          */
+            __IOM uint32_t E0_MK25 : 1;   /*!< [25..25] E0_MK25                                                          */
+            __IOM uint32_t E0_MK26 : 1;   /*!< [26..26] E0_MK26                                                          */
+            __IOM uint32_t E0_MK27 : 1;   /*!< [27..27] E0_MK27                                                          */
+            __IOM uint32_t E0_MK28 : 1;   /*!< [28..28] E0_MK28                                                          */
+            __IOM uint32_t E0_MK29 : 1;   /*!< [29..29] E0_MK29                                                          */
+            __IOM uint32_t E0_MK30 : 1;   /*!< [30..30] E0_MK30                                                          */
+            __IOM uint32_t E0_MK31 : 1;   /*!< [31..31] E0_MK31                                                          */
+        } ENCIFERR_E0MSK_b[5];
+    };
+
+    union
+    {
+        __IOM uint32_t ENCIFERR_E1MSK[5]; /*!< (@ 0x00000214) ENCIFERR_E1MSKn ENCIF E1 Error Event Mask Register
+                                           *                  n (n = 0 to 4)                                             */
+
+        struct
+        {
+            __IOM uint32_t E1_MK0  : 1;   /*!< [0..0] E1_MK0                                                             */
+            __IOM uint32_t E1_MK1  : 1;   /*!< [1..1] E1_MK1                                                             */
+            __IOM uint32_t E1_MK2  : 1;   /*!< [2..2] E1_MK2                                                             */
+            __IOM uint32_t E1_MK3  : 1;   /*!< [3..3] E1_MK3                                                             */
+            __IOM uint32_t E1_MK4  : 1;   /*!< [4..4] E1_MK4                                                             */
+            __IOM uint32_t E1_MK5  : 1;   /*!< [5..5] E1_MK5                                                             */
+            __IOM uint32_t E1_MK6  : 1;   /*!< [6..6] E1_MK6                                                             */
+            __IOM uint32_t E1_MK7  : 1;   /*!< [7..7] E1_MK7                                                             */
+            __IOM uint32_t E1_MK8  : 1;   /*!< [8..8] E1_MK8                                                             */
+            __IOM uint32_t E1_MK9  : 1;   /*!< [9..9] E1_MK9                                                             */
+            __IOM uint32_t E1_MK10 : 1;   /*!< [10..10] E1_MK10                                                          */
+            __IOM uint32_t E1_MK11 : 1;   /*!< [11..11] E1_MK11                                                          */
+            __IOM uint32_t E1_MK12 : 1;   /*!< [12..12] E1_MK12                                                          */
+            __IOM uint32_t E1_MK13 : 1;   /*!< [13..13] E1_MK13                                                          */
+            __IOM uint32_t E1_MK14 : 1;   /*!< [14..14] E1_MK14                                                          */
+            __IOM uint32_t E1_MK15 : 1;   /*!< [15..15] E1_MK15                                                          */
+            __IOM uint32_t E1_MK16 : 1;   /*!< [16..16] E1_MK16                                                          */
+            __IOM uint32_t E1_MK17 : 1;   /*!< [17..17] E1_MK17                                                          */
+            __IOM uint32_t E1_MK18 : 1;   /*!< [18..18] E1_MK18                                                          */
+            __IOM uint32_t E1_MK19 : 1;   /*!< [19..19] E1_MK19                                                          */
+            __IOM uint32_t E1_MK20 : 1;   /*!< [20..20] E1_MK20                                                          */
+            __IOM uint32_t E1_MK21 : 1;   /*!< [21..21] E1_MK21                                                          */
+            __IOM uint32_t E1_MK22 : 1;   /*!< [22..22] E1_MK22                                                          */
+            __IOM uint32_t E1_MK23 : 1;   /*!< [23..23] E1_MK23                                                          */
+            __IOM uint32_t E1_MK24 : 1;   /*!< [24..24] E1_MK24                                                          */
+            __IOM uint32_t E1_MK25 : 1;   /*!< [25..25] E1_MK25                                                          */
+            __IOM uint32_t E1_MK26 : 1;   /*!< [26..26] E1_MK26                                                          */
+            __IOM uint32_t E1_MK27 : 1;   /*!< [27..27] E1_MK27                                                          */
+            __IOM uint32_t E1_MK28 : 1;   /*!< [28..28] E1_MK28                                                          */
+            __IOM uint32_t E1_MK29 : 1;   /*!< [29..29] E1_MK29                                                          */
+            __IOM uint32_t E1_MK30 : 1;   /*!< [30..30] E1_MK30                                                          */
+            __IOM uint32_t E1_MK31 : 1;   /*!< [31..31] E1_MK31                                                          */
+        } ENCIFERR_E1MSK_b[5];
+    };
+
+    union
+    {
+        __IOM uint32_t ENCIFERR_RSTMSK[5]; /*!< (@ 0x00000228) ENCIFERR_RSTMSKn ENCIF Error Event Reset Mask
+                                            *                  Register n (n = 0 to 4)                                    */
+
+        struct
+        {
+            __IOM uint32_t RS_MK0  : 1;    /*!< [0..0] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK1  : 1;    /*!< [1..1] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK2  : 1;    /*!< [2..2] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK3  : 1;    /*!< [3..3] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK4  : 1;    /*!< [4..4] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK5  : 1;    /*!< [5..5] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK6  : 1;    /*!< [6..6] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK7  : 1;    /*!< [7..7] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK8  : 1;    /*!< [8..8] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK9  : 1;    /*!< [9..9] Mask captured error status as a reset event for ENCIFERR_STATn     */
+            __IOM uint32_t RS_MK10 : 1;    /*!< [10..10] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK11 : 1;    /*!< [11..11] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK12 : 1;    /*!< [12..12] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK13 : 1;    /*!< [13..13] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK14 : 1;    /*!< [14..14] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK15 : 1;    /*!< [15..15] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK16 : 1;    /*!< [16..16] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK17 : 1;    /*!< [17..17] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK18 : 1;    /*!< [18..18] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK19 : 1;    /*!< [19..19] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK20 : 1;    /*!< [20..20] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK21 : 1;    /*!< [21..21] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK22 : 1;    /*!< [22..22] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK23 : 1;    /*!< [23..23] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK24 : 1;    /*!< [24..24] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK25 : 1;    /*!< [25..25] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK26 : 1;    /*!< [26..26] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK27 : 1;    /*!< [27..27] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK28 : 1;    /*!< [28..28] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK29 : 1;    /*!< [29..29] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK30 : 1;    /*!< [30..30] Mask captured error status as a reset event for ENCIFERR_STATn   */
+            __IOM uint32_t RS_MK31 : 1;    /*!< [31..31] Mask captured error status as a reset event for ENCIFERR_STATn   */
+        } ENCIFERR_RSTMSK_b[5];
+    };
+    __IM uint32_t RESERVED6[5];
+
+    union
+    {
+        __OM uint32_t ENCIFERR_CLR[5]; /*!< (@ 0x00000250) ENCIFERR_CLRn ENCIF Error Event Status Clear
+                                        *                  Register n (n = 0 to 4)                                    */
+
+        struct
+        {
+            __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL8 : 1;  /*!< [8..8] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL26 : 1; /*!< [26..26] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL29 : 1; /*!< [29..29] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL30 : 1; /*!< [30..30] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+            __OM uint32_t ER_CL31 : 1; /*!< [31..31] Clear captured error status for ENCIFERR_STATn register
+                                        *   by writing 1                                                              */
+        } ENCIFERR_CLR_b[5];
+    };
+
+    union
+    {
+        __IM uint32_t ENCIFERR_STAT[5]; /*!< (@ 0x00000264) ENCIFERR_STATn ENCIF Error Event Status Register
+                                         *                  n (n = 0 to 4)                                             */
+
+        struct
+        {
+            __IM uint32_t ER_ST0 : 1;   /*!< [0..0] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST1 : 1;   /*!< [1..1] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST2 : 1;   /*!< [2..2] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST3 : 1;   /*!< [3..3] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST4 : 1;   /*!< [4..4] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST5 : 1;   /*!< [5..5] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST6 : 1;   /*!< [6..6] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST7 : 1;   /*!< [7..7] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST8 : 1;   /*!< [8..8] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST9 : 1;   /*!< [9..9] Indicate captured error status for error event from Encoder
+                                         *   Interface modules                                                         */
+            __IM uint32_t ER_ST10 : 1;  /*!< [10..10] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST11 : 1;  /*!< [11..11] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST12 : 1;  /*!< [12..12] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST13 : 1;  /*!< [13..13] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST14 : 1;  /*!< [14..14] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST15 : 1;  /*!< [15..15] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST16 : 1;  /*!< [16..16] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST17 : 1;  /*!< [17..17] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST18 : 1;  /*!< [18..18] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST19 : 1;  /*!< [19..19] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST20 : 1;  /*!< [20..20] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST21 : 1;  /*!< [21..21] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST22 : 1;  /*!< [22..22] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST23 : 1;  /*!< [23..23] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST24 : 1;  /*!< [24..24] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST25 : 1;  /*!< [25..25] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST26 : 1;  /*!< [26..26] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST27 : 1;  /*!< [27..27] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST28 : 1;  /*!< [28..28] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST29 : 1;  /*!< [29..29] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST30 : 1;  /*!< [30..30] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+            __IM uint32_t ER_ST31 : 1;  /*!< [31..31] Indicate captured error status for error event from
+                                         *   Encoder Interface modules                                                 */
+        } ENCIFERR_STAT_b[5];
+    };
+    __IM uint32_t RESERVED7[6];
+
+    union
+    {
+        __IOM uint32_t ENCIF_ENCSEL0;   /*!< (@ 0x00000290) ENCIF Event Select Register 0                              */
+
+        struct
+        {
+            __IOM uint32_t ENCSEL0 : 3; /*!< [2..0] ENCSEL0                                                            */
+            uint32_t               : 1;
+            __IOM uint32_t ENCSEL1 : 3; /*!< [6..4] ENCSEL1                                                            */
+            uint32_t               : 1;
+            __IOM uint32_t ENCSEL2 : 3; /*!< [10..8] ENCSEL2                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t ENCSEL3 : 3; /*!< [14..12] ENCSEL3                                                          */
+            uint32_t               : 1;
+            __IOM uint32_t ENCSEL4 : 3; /*!< [18..16] ENCSEL4                                                          */
+            uint32_t               : 1;
+            __IOM uint32_t ENCSEL5 : 3; /*!< [22..20] ENCSEL5                                                          */
+            uint32_t               : 1;
+            __IOM uint32_t ENCSEL6 : 3; /*!< [26..24] ENCSEL6                                                          */
+            uint32_t               : 1;
+            __IOM uint32_t ENCSEL7 : 3; /*!< [30..28] ENCSEL7                                                          */
+            uint32_t               : 1;
+        } ENCIF_ENCSEL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ENCIF_ENCSEL1;    /*!< (@ 0x00000294) ENCIF Event Select Register 1                              */
+
+        struct
+        {
+            __IOM uint32_t ENCSEL8  : 3; /*!< [2..0] ENCSEL8                                                            */
+            uint32_t                : 1;
+            __IOM uint32_t ENCSEL9  : 3; /*!< [6..4] ENCSEL9                                                            */
+            uint32_t                : 1;
+            __IOM uint32_t ENCSEL10 : 3; /*!< [10..8] ENCSEL10                                                          */
+            uint32_t                : 1;
+            __IOM uint32_t ENCSEL11 : 3; /*!< [14..12] ENCSEL11                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t ENCSEL12 : 3; /*!< [18..16] ENCSEL12                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t ENCSEL13 : 3; /*!< [22..20] ENCSEL13                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t ENCSEL14 : 3; /*!< [26..24] ENCSEL14                                                         */
+            uint32_t                : 1;
+            __IOM uint32_t ENCSEL15 : 3; /*!< [30..28] ENCSEL15                                                         */
+            uint32_t                : 1;
+        } ENCIF_ENCSEL1_b;
+    };
+    __IM uint32_t RESERVED8[12];
+
+    union
+    {
+        __IOM uint32_t NS_GPT_INTSEL[26]; /*!< (@ 0x000002C8) NS_GPT_INTSELn GPT/MTU3 Interrupt Select Register
+                                           *                  n (n = 0 to 25)                                            */
+
+        struct
+        {
+            __IOM uint32_t INTSELX_0 : 4; /*!< [3..0] INTSELX_0                                                          */
+            __IOM uint32_t INTSELX_1 : 4; /*!< [7..4] Select GPT/MTU3 event source to be output as GPTx_INT1
+                                           *   event                                                                     */
+            __IOM uint32_t INTSELX_2 : 4; /*!< [11..8] Select GPT/MTU3 event source to be output as GPTx_INT2
+                                           *   event                                                                     */
+            __IOM uint32_t INTSELX_3 : 4; /*!< [15..12] Select GPT/MTU3 event source to be output as GPTx_INT3
+                                           *   event                                                                     */
+            __IOM uint32_t INTSELY_0 : 4; /*!< [19..16] Select GPT/MTU3 event source to be output as GPTy_INT0
+                                           *   event                                                                     */
+            __IOM uint32_t INTSELY_1 : 4; /*!< [23..20] Select GPT/MTU3 event source to be output as GPTy_INT1
+                                           *   event                                                                     */
+            __IOM uint32_t INTSELY_2 : 4; /*!< [27..24] Select GPT/MTU3 event source to be output as GPTy_INT2
+                                           *   event                                                                     */
+            __IOM uint32_t INTSELY_3 : 4; /*!< [31..28] Select GPT/MTU3 event source to be output as GPTy_INT3
+                                           *   event                                                                     */
+        } NS_GPT_INTSEL_b[26];
+    };
+
+    union
+    {
+        __IOM uint32_t ELC_GPT_INTSEL[26]; /*!< (@ 0x00000330) ELC_GPT_INTSELn GPT/MTU3 ELC event source Select
+                                            *                  Register n (n = 0 to 25)                                   */
+
+        struct
+        {
+            __IOM uint32_t INTSELX_0 : 4;  /*!< [3..0] INTSELX_0                                                          */
+            __IOM uint32_t INTSELX_1 : 4;  /*!< [7..4] Select GPT/MTU3 event source to be output as GPTx_INT1
+                                            *   event                                                                     */
+            __IOM uint32_t INTSELX_2 : 4;  /*!< [11..8] Select GPT/MTU3 event source to be output as GPTx_INT2
+                                            *   event                                                                     */
+            __IOM uint32_t INTSELX_3 : 4;  /*!< [15..12] Select GPT/MTU3 event source to be output as GPTx_INT3
+                                            *   event                                                                     */
+            __IOM uint32_t INTSELY_0 : 4;  /*!< [19..16] Select GPT/MTU3 event source to be output as GPTy_INT0
+                                            *   event                                                                     */
+            __IOM uint32_t INTSELY_1 : 4;  /*!< [23..20] Select GPT/MTU3 event source to be output as GPTy_INT1
+                                            *   event                                                                     */
+            __IOM uint32_t INTSELY_2 : 4;  /*!< [27..24] Select GPT/MTU3 event source to be output as GPTy_INT2
+                                            *   event                                                                     */
+            __IOM uint32_t INTSELY_3 : 4;  /*!< [31..28] Select GPT/MTU3 event source to be output as GPTy_INT3
+                                            *   event                                                                     */
+        } ELC_GPT_INTSEL_b[26];
+    };
+    __IM uint32_t RESERVED9[32];
+
+    union
+    {
+        __IOM uint32_t CR520_INTSEL[80]; /*!< (@ 0x00000418) CR52 CPU0 Interrupt Select Register n (n = 0
+                                          *                  to 79)                                                     */
+
+        struct
+        {
+            __IOM uint32_t INTSELX : 10; /*!< [9..0] Set the number of the event source to be select as Cortex-R52
+                                          *   CPU0 selected peripheral interrupt x (SELECT0_IRQx). Event
+                                          *   source is selectable from . If SELECT0_IRQx is not used,
+                                          *   set 0x3FF (Fixed to 0 output).                                            */
+            uint32_t               : 6;
+            __IOM uint32_t INTSELY : 10; /*!< [25..16] Set the number of the event source to be select as
+                                          *   Cortex-R52 CPU0 selected peripheral interrupt y (SELECT0_IRQy).
+                                          *   Event source is selectable from . If SELECT0_IRQy is not
+                                          *   used, set 0x3FF (Fixed to 0 output).                                      */
+            uint32_t : 6;
+        } CR520_INTSEL_b[80];
+    };
+
+    union
+    {
+        __IOM uint32_t CR521_INTSEL[80]; /*!< (@ 0x00000558) CR52 CPU1 Interrupt Select Register n (n = 0
+                                          *                  to 79)                                                     */
+
+        struct
+        {
+            __IOM uint32_t INTSELX : 10; /*!< [9..0] Set the number of the event source to be select as Cortex-R52
+                                          *   CPU1 selected peripheral interrupt x (SELECT1_IRQx). Event
+                                          *   source is selectable from . If SELECT1_IRQx is not used,
+                                          *   set 0x3FF (Fixed to 0 output).                                            */
+            uint32_t               : 6;
+            __IOM uint32_t INTSELY : 10; /*!< [25..16] Set the number of the event source to be select as
+                                          *   Cortex-R52 CPU1 selected peripheral interrupt y (SELECT1_IRQy).
+                                          *   Event source is selectable from . If SELECT1_IRQy is not
+                                          *   used, set 0x3FF (Fixed to 0 output).                                      */
+            uint32_t : 6;
+        } CR521_INTSEL_b[80];
+    };
+    __IM uint32_t RESERVED10[154];
+
+    union
+    {
+        __IOM uint32_t NS_GPT_INTMSK[26]; /*!< (@ 0x00000900) GPT/MTU3 Combined Interrupt Mask Register n (n
+                                           *                  = 0 to 25)                                                 */
+
+        struct
+        {
+            __IOM uint32_t IX_MK0 : 1;    /*!< [0..0] Mask GPTx_CCMPA event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK1 : 1;    /*!< [1..1] Mask GPTx_CCMPB event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK2 : 1;    /*!< [2..2] Mask GPTx_CMPC event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK3 : 1;    /*!< [3..3] Mask GPTx_CMPD event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK4 : 1;    /*!< [4..4] Mask GPTx_CMPE event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK5 : 1;    /*!< [5..5] Mask GPTx_CMPF event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK6 : 1;    /*!< [6..6] Mask GPTx_OVF event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK7 : 1;    /*!< [7..7] Mask GPTx_UDF event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK8 : 1;    /*!< [8..8] Mask GPTx_DTE event source from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK9 : 1;    /*!< [9..9] Mask MTU3 event source 0 from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK10 : 1;   /*!< [10..10] Mask MTU3 event source 1 from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK11 : 1;   /*!< [11..11] Mask MTU3 event source 2 from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK12 : 1;   /*!< [12..12] Mask MTU3 event source 3 from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK13 : 1;   /*!< [13..13] Mask MTU3 event source 4 from GPT/MTU3 combined event,
+                                           *   GPTx_INT4                                                                 */
+            uint32_t              : 2;
+            __IOM uint32_t IY_MK0 : 1;    /*!< [16..16] Mask GPTy_CCMPA event source from GPT/MTU3 combined
+                                           *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK1 : 1;    /*!< [17..17] Mask GPTy_CCMPB event source from GPT/MTU3 combined
+                                           *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK2 : 1;    /*!< [18..18] Mask GPTy_CMPC event source from GPT/MTU3 combined
+                                           *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK3 : 1;    /*!< [19..19] Mask GPTy_CMPD event source from GPT/MTU3 combined
+                                           *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK4 : 1;    /*!< [20..20] Mask GPTy_CMPE event source from GPT/MTU3 combined
+                                           *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK5 : 1;    /*!< [21..21] Mask GPTy_CMPF event source from GPT/MTU3 combined
+                                           *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK6 : 1;    /*!< [22..22] Mask GPTy_OVF event source from GPT/MTU3 combined event,
+                                           *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK7 : 1;    /*!< [23..23] Mask GPTy_UDF event source from GPT/MTU3 combined event,
+                                           *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK8 : 1;    /*!< [24..24] Mask GPTy_DTE event source from GPT/MTU3 combined event,
+                                           *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK9 : 1;    /*!< [25..25] Mask MTU3 event source 0 from GPT/MTU3 combined event,
+                                           *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK10 : 1;   /*!< [26..26] Mask MTU3 event source 1 from GPT/MTU3 combined event,
+                                           *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK11 : 1;   /*!< [27..27] Mask MTU3 event source 2 from GPT/MTU3 combined event,
+                                           *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK12 : 1;   /*!< [28..28] Mask MTU3 event source 3 from GPT/MTU3 combined event,
+                                           *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK13 : 1;   /*!< [29..29] Mask MTU3 event source 4 from GPT/MTU3 combined event,
+                                           *   GPTy_INT4                                                                 */
+            uint32_t : 2;
+        } NS_GPT_INTMSK_b[26];
+    };
+    __IM uint32_t RESERVED11[2];
+
+    union
+    {
+        __IOM uint32_t ELC_GPT_INTMSK[26]; /*!< (@ 0x00000970) GPT/MTU3 Combined ELC Event Mask Register n (n
+                                            *                  = 0 to 25)                                                 */
+
+        struct
+        {
+            __IOM uint32_t IX_MK0 : 1;     /*!< [0..0] Mask GPTx_CCMPA event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK1 : 1;     /*!< [1..1] Mask GPTx_CCMPB event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK2 : 1;     /*!< [2..2] Mask GPTx_CMPC event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK3 : 1;     /*!< [3..3] Mask GPTx_CMPD event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK4 : 1;     /*!< [4..4] Mask GPTx_CMPE event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK5 : 1;     /*!< [5..5] Mask GPTx_CMPF event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK6 : 1;     /*!< [6..6] Mask GPTx_OVF event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK7 : 1;     /*!< [7..7] Mask GPTx_UDF event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK8 : 1;     /*!< [8..8] Mask GPTx_DTE event source from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK9 : 1;     /*!< [9..9] Mask MTU3 event source 0 from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK10 : 1;    /*!< [10..10] Mask MTU3 event source 1 from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK11 : 1;    /*!< [11..11] Mask MTU3 event source 2 from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK12 : 1;    /*!< [12..12] Mask MTU3 event source 3 from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            __IOM uint32_t IX_MK13 : 1;    /*!< [13..13] Mask MTU3 event source 4 from GPT/MTU3 combined event,
+                                            *   GPTx_INT4                                                                 */
+            uint32_t              : 2;
+            __IOM uint32_t IY_MK0 : 1;     /*!< [16..16] Mask GPTy_CCMPA event source from GPT/MTU3 combined
+                                            *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK1 : 1;     /*!< [17..17] Mask GPTy_CCMPB event source from GPT/MTU3 combined
+                                            *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK2 : 1;     /*!< [18..18] Mask GPTy_CMPC event source from GPT/MTU3 combined
+                                            *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK3 : 1;     /*!< [19..19] Mask GPTy_CMPD event source from GPT/MTU3 combined
+                                            *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK4 : 1;     /*!< [20..20] Mask GPTy_CMPE event source from GPT/MTU3 combined
+                                            *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK5 : 1;     /*!< [21..21] Mask GPTy_CMPF event source from GPT/MTU3 combined
+                                            *   event, GPTy_INT4                                                          */
+            __IOM uint32_t IY_MK6 : 1;     /*!< [22..22] Mask GPTy_OVF event source from GPT/MTU3 combined event,
+                                            *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK7 : 1;     /*!< [23..23] Mask GPTy_UDF event source from GPT/MTU3 combined event,
+                                            *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK8 : 1;     /*!< [24..24] Mask GPTy_DTE event source from GPT/MTU3 combined event,
+                                            *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK9 : 1;     /*!< [25..25] Mask MTU3 event source 0 from GPT/MTU3 combined event,
+                                            *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK10 : 1;    /*!< [26..26] Mask MTU3 event source 1 from GPT/MTU3 combined event,
+                                            *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK11 : 1;    /*!< [27..27] Mask MTU3 event source 2 from GPT/MTU3 combined event,
+                                            *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK12 : 1;    /*!< [28..28] Mask MTU3 event source 3 from GPT/MTU3 combined event,
+                                            *   GPTy_INT4                                                                 */
+            __IOM uint32_t IY_MK13 : 1;    /*!< [29..29] Mask MTU3 event source 4 from GPT/MTU3 combined event,
+                                            *   GPTy_INT4                                                                 */
+            uint32_t : 2;
+        } ELC_GPT_INTMSK_b[26];
+    };
+    __IM uint32_t RESERVED12[2];
+
+    union
+    {
+        __OM uint32_t NS_GPT_INTCLR[26]; /*!< (@ 0x000009E0) GPT/MTU3 Combined Interrupt Status Clear Register
+                                          *                  n (n = 0 to 25)                                            */
+
+        struct
+        {
+            __OM uint32_t IX_CL0  : 1;   /*!< [0..0] IX_CL0                                                             */
+            __OM uint32_t IX_CL1  : 1;   /*!< [1..1] IX_CL1                                                             */
+            __OM uint32_t IX_CL2  : 1;   /*!< [2..2] IX_CL2                                                             */
+            __OM uint32_t IX_CL3  : 1;   /*!< [3..3] IX_CL3                                                             */
+            __OM uint32_t IX_CL4  : 1;   /*!< [4..4] IX_CL4                                                             */
+            __OM uint32_t IX_CL5  : 1;   /*!< [5..5] IX_CL5                                                             */
+            __OM uint32_t IX_CL6  : 1;   /*!< [6..6] IX_CL6                                                             */
+            __OM uint32_t IX_CL7  : 1;   /*!< [7..7] IX_CL7                                                             */
+            __OM uint32_t IX_CL8  : 1;   /*!< [8..8] IX_CL8                                                             */
+            __OM uint32_t IX_CL9  : 1;   /*!< [9..9] IX_CL9                                                             */
+            __OM uint32_t IX_CL10 : 1;   /*!< [10..10] IX_CL10                                                          */
+            __OM uint32_t IX_CL11 : 1;   /*!< [11..11] IX_CL11                                                          */
+            __OM uint32_t IX_CL12 : 1;   /*!< [12..12] IX_CL12                                                          */
+            __OM uint32_t IX_CL13 : 1;   /*!< [13..13] IX_CL13                                                          */
+            uint32_t              : 2;
+            __OM uint32_t IY_CL0  : 1;   /*!< [16..16] IY_CL0                                                           */
+            __OM uint32_t IY_CL1  : 1;   /*!< [17..17] IY_CL1                                                           */
+            __OM uint32_t IY_CL2  : 1;   /*!< [18..18] IY_CL2                                                           */
+            __OM uint32_t IY_CL3  : 1;   /*!< [19..19] IY_CL3                                                           */
+            __OM uint32_t IY_CL4  : 1;   /*!< [20..20] IY_CL4                                                           */
+            __OM uint32_t IY_CL5  : 1;   /*!< [21..21] IY_CL5                                                           */
+            __OM uint32_t IY_CL6  : 1;   /*!< [22..22] IY_CL6                                                           */
+            __OM uint32_t IY_CL7  : 1;   /*!< [23..23] IY_CL7                                                           */
+            __OM uint32_t IY_CL8  : 1;   /*!< [24..24] IY_CL8                                                           */
+            __OM uint32_t IY_CL9  : 1;   /*!< [25..25] IY_CL9                                                           */
+            __OM uint32_t IY_CL10 : 1;   /*!< [26..26] IY_CL10                                                          */
+            __OM uint32_t IY_CL11 : 1;   /*!< [27..27] IY_CL11                                                          */
+            __OM uint32_t IY_CL12 : 1;   /*!< [28..28] IY_CL12                                                          */
+            __OM uint32_t IY_CL13 : 1;   /*!< [29..29] IY_CL13                                                          */
+            uint32_t              : 2;
+        } NS_GPT_INTCLR_b[26];
+    };
+    __IM uint32_t RESERVED13[2];
+
+    union
+    {
+        __OM uint32_t ELC_GPT_INTCLR[26]; /*!< (@ 0x00000A50) GPT/MTU3 Combined ELC Event Status Clear Register
+                                           *                  n (n = 0 to 25)                                            */
+
+        struct
+        {
+            __OM uint32_t IX_CL0  : 1;    /*!< [0..0] IX_CL0                                                             */
+            __OM uint32_t IX_CL1  : 1;    /*!< [1..1] IX_CL1                                                             */
+            __OM uint32_t IX_CL2  : 1;    /*!< [2..2] IX_CL2                                                             */
+            __OM uint32_t IX_CL3  : 1;    /*!< [3..3] IX_CL3                                                             */
+            __OM uint32_t IX_CL4  : 1;    /*!< [4..4] IX_CL4                                                             */
+            __OM uint32_t IX_CL5  : 1;    /*!< [5..5] IX_CL5                                                             */
+            __OM uint32_t IX_CL6  : 1;    /*!< [6..6] IX_CL6                                                             */
+            __OM uint32_t IX_CL7  : 1;    /*!< [7..7] IX_CL7                                                             */
+            __OM uint32_t IX_CL8  : 1;    /*!< [8..8] IX_CL8                                                             */
+            __OM uint32_t IX_CL9  : 1;    /*!< [9..9] IX_CL9                                                             */
+            __OM uint32_t IX_CL10 : 1;    /*!< [10..10] IX_CL10                                                          */
+            __OM uint32_t IX_CL11 : 1;    /*!< [11..11] IX_CL11                                                          */
+            __OM uint32_t IX_CL12 : 1;    /*!< [12..12] IX_CL12                                                          */
+            __OM uint32_t IX_CL13 : 1;    /*!< [13..13] IX_CL13                                                          */
+            uint32_t              : 2;
+            __OM uint32_t IY_CL0  : 1;    /*!< [16..16] IY_CL0                                                           */
+            __OM uint32_t IY_CL1  : 1;    /*!< [17..17] IY_CL1                                                           */
+            __OM uint32_t IY_CL2  : 1;    /*!< [18..18] IY_CL2                                                           */
+            __OM uint32_t IY_CL3  : 1;    /*!< [19..19] IY_CL3                                                           */
+            __OM uint32_t IY_CL4  : 1;    /*!< [20..20] IY_CL4                                                           */
+            __OM uint32_t IY_CL5  : 1;    /*!< [21..21] IY_CL5                                                           */
+            __OM uint32_t IY_CL6  : 1;    /*!< [22..22] IY_CL6                                                           */
+            __OM uint32_t IY_CL7  : 1;    /*!< [23..23] IY_CL7                                                           */
+            __OM uint32_t IY_CL8  : 1;    /*!< [24..24] IY_CL8                                                           */
+            __OM uint32_t IY_CL9  : 1;    /*!< [25..25] IY_CL9                                                           */
+            __OM uint32_t IY_CL10 : 1;    /*!< [26..26] IY_CL10                                                          */
+            __OM uint32_t IY_CL11 : 1;    /*!< [27..27] IY_CL11                                                          */
+            __OM uint32_t IY_CL12 : 1;    /*!< [28..28] IY_CL12                                                          */
+            __OM uint32_t IY_CL13 : 1;    /*!< [29..29] IY_CL13                                                          */
+            uint32_t              : 2;
+        } ELC_GPT_INTCLR_b[26];
+    };
+    __IM uint32_t RESERVED14[2];
+
+    union
+    {
+        __IM uint32_t NS_GPT_INTSTAT[26]; /*!< (@ 0x00000AC0) GPT/MTU3 Combined Interrupt Status Register n
+                                           *                  (n = 0 to 25)                                              */
+
+        struct
+        {
+            __IM uint32_t IX_ST0  : 1;    /*!< [0..0] IX_ST0                                                             */
+            __IM uint32_t IX_ST1  : 1;    /*!< [1..1] IX_ST1                                                             */
+            __IM uint32_t IX_ST2  : 1;    /*!< [2..2] IX_ST2                                                             */
+            __IM uint32_t IX_ST3  : 1;    /*!< [3..3] IX_ST3                                                             */
+            __IM uint32_t IX_ST4  : 1;    /*!< [4..4] IX_ST4                                                             */
+            __IM uint32_t IX_ST5  : 1;    /*!< [5..5] IX_ST5                                                             */
+            __IM uint32_t IX_ST6  : 1;    /*!< [6..6] IX_ST6                                                             */
+            __IM uint32_t IX_ST7  : 1;    /*!< [7..7] IX_ST7                                                             */
+            __IM uint32_t IX_ST8  : 1;    /*!< [8..8] IX_ST8                                                             */
+            __IM uint32_t IX_ST9  : 1;    /*!< [9..9] IX_ST9                                                             */
+            __IM uint32_t IX_ST10 : 1;    /*!< [10..10] IX_ST10                                                          */
+            __IM uint32_t IX_ST11 : 1;    /*!< [11..11] IX_ST11                                                          */
+            __IM uint32_t IX_ST12 : 1;    /*!< [12..12] IX_ST12                                                          */
+            __IM uint32_t IX_ST13 : 1;    /*!< [13..13] IX_ST13                                                          */
+            uint32_t              : 2;
+            __IM uint32_t IY_ST0  : 1;    /*!< [16..16] IY_ST0                                                           */
+            __IM uint32_t IY_ST1  : 1;    /*!< [17..17] IY_ST1                                                           */
+            __IM uint32_t IY_ST2  : 1;    /*!< [18..18] IY_ST2                                                           */
+            __IM uint32_t IY_ST3  : 1;    /*!< [19..19] IY_ST3                                                           */
+            __IM uint32_t IY_ST4  : 1;    /*!< [20..20] IY_ST4                                                           */
+            __IM uint32_t IY_ST5  : 1;    /*!< [21..21] IY_ST5                                                           */
+            __IM uint32_t IY_ST6  : 1;    /*!< [22..22] IY_ST6                                                           */
+            __IM uint32_t IY_ST7  : 1;    /*!< [23..23] IY_ST7                                                           */
+            __IM uint32_t IY_ST8  : 1;    /*!< [24..24] IY_ST8                                                           */
+            __IM uint32_t IY_ST9  : 1;    /*!< [25..25] IY_ST9                                                           */
+            __IM uint32_t IY_ST10 : 1;    /*!< [26..26] IY_ST10                                                          */
+            __IM uint32_t IY_ST11 : 1;    /*!< [27..27] IY_ST11                                                          */
+            __IM uint32_t IY_ST12 : 1;    /*!< [28..28] IY_ST12                                                          */
+            __IM uint32_t IY_ST13 : 1;    /*!< [29..29] IY_ST13                                                          */
+            uint32_t              : 2;
+        } NS_GPT_INTSTAT_b[26];
+    };
+    __IM uint32_t RESERVED15[2];
+
+    union
+    {
+        __IM uint32_t ELC_GPT_INTSTAT[26]; /*!< (@ 0x00000B30) GPT/MTU3 Combined ELC Event Status Register n
+                                            *                  (n = 0 to 25)                                              */
+
+        struct
+        {
+            __IM uint32_t IX_ST0  : 1;     /*!< [0..0] IX_ST0                                                             */
+            __IM uint32_t IX_ST1  : 1;     /*!< [1..1] IX_ST1                                                             */
+            __IM uint32_t IX_ST2  : 1;     /*!< [2..2] IX_ST2                                                             */
+            __IM uint32_t IX_ST3  : 1;     /*!< [3..3] IX_ST3                                                             */
+            __IM uint32_t IX_ST4  : 1;     /*!< [4..4] IX_ST4                                                             */
+            __IM uint32_t IX_ST5  : 1;     /*!< [5..5] IX_ST5                                                             */
+            __IM uint32_t IX_ST6  : 1;     /*!< [6..6] IX_ST6                                                             */
+            __IM uint32_t IX_ST7  : 1;     /*!< [7..7] IX_ST7                                                             */
+            __IM uint32_t IX_ST8  : 1;     /*!< [8..8] IX_ST8                                                             */
+            __IM uint32_t IX_ST9  : 1;     /*!< [9..9] IX_ST9                                                             */
+            __IM uint32_t IX_ST10 : 1;     /*!< [10..10] IX_ST10                                                          */
+            __IM uint32_t IX_ST11 : 1;     /*!< [11..11] IX_ST11                                                          */
+            __IM uint32_t IX_ST12 : 1;     /*!< [12..12] IX_ST12                                                          */
+            __IM uint32_t IX_ST13 : 1;     /*!< [13..13] IX_ST13                                                          */
+            uint32_t              : 2;
+            __IM uint32_t IY_ST0  : 1;     /*!< [16..16] IY_ST0                                                           */
+            __IM uint32_t IY_ST1  : 1;     /*!< [17..17] IY_ST1                                                           */
+            __IM uint32_t IY_ST2  : 1;     /*!< [18..18] IY_ST2                                                           */
+            __IM uint32_t IY_ST3  : 1;     /*!< [19..19] IY_ST3                                                           */
+            __IM uint32_t IY_ST4  : 1;     /*!< [20..20] IY_ST4                                                           */
+            __IM uint32_t IY_ST5  : 1;     /*!< [21..21] IY_ST5                                                           */
+            __IM uint32_t IY_ST6  : 1;     /*!< [22..22] IY_ST6                                                           */
+            __IM uint32_t IY_ST7  : 1;     /*!< [23..23] IY_ST7                                                           */
+            __IM uint32_t IY_ST8  : 1;     /*!< [24..24] IY_ST8                                                           */
+            __IM uint32_t IY_ST9  : 1;     /*!< [25..25] IY_ST9                                                           */
+            __IM uint32_t IY_ST10 : 1;     /*!< [26..26] IY_ST10                                                          */
+            __IM uint32_t IY_ST11 : 1;     /*!< [27..27] IY_ST11                                                          */
+            __IM uint32_t IY_ST12 : 1;     /*!< [28..28] IY_ST12                                                          */
+            __IM uint32_t IY_ST13 : 1;     /*!< [29..29] IY_ST13                                                          */
+            uint32_t              : 2;
+        } ELC_GPT_INTSTAT_b[26];
+    };
+} R_ICU_NS_Type;                           /*!< Size = 2968 (0xb98)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Event Link Controller (R_ELC)
+ */
+
+typedef struct                            /*!< (@ 0x802A0698) R_ELC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t ELC_SSEL[65];      /*!< (@ 0x00000000) ELC Event Source Select Register [0..64]                   */
+
+        struct
+        {
+            __IOM uint32_t ELC_SEL0 : 10; /*!< [9..0] Set the number for ELC event source to be linked to the
+                                           *   ELC destination.                                                          */
+            __IOM uint32_t ELC_SEL1 : 10; /*!< [19..10] Set the number for ELC event source to be linked to
+                                           *   the ELC destination.                                                      */
+            __IOM uint32_t ELC_SEL2 : 10; /*!< [29..20] Set the number for ELC event source to be linked to
+                                           *   the ELC destination.                                                      */
+            uint32_t : 2;
+        } ELC_SSEL_b[65];
+    };
+} R_ELC_Type;                             /*!< Size = 260 (0x104)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMAC Configuration (R_DMA)
+ */
+
+typedef struct                            /*!< (@ 0x802A07D0) R_DMA Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t DMAC0_RSSEL[6];    /*!< (@ 0x00000000) DMAC Unit 0 Resource Select Register [0..5]                */
+
+        struct
+        {
+            __IOM uint32_t REQ_SELA : 10; /*!< [9..0] DMA Resource Select for Channel n                                  */
+            __IOM uint32_t REQ_SELB : 10; /*!< [19..10] DMA Resource Select for Channel n + 1                            */
+            __IOM uint32_t REQ_SELC : 10; /*!< [29..20] DMA Resource Select for Channel n + 2                            */
+            uint32_t                : 2;
+        } DMAC0_RSSEL_b[6];
+    };
+
+    union
+    {
+        __IOM uint32_t DMAC1_RSSEL[6];    /*!< (@ 0x00000018) DMAC Unit 1 Resource Select Register [0..5]                */
+
+        struct
+        {
+            __IOM uint32_t REQ_SELA : 10; /*!< [9..0] DMA Resource Select for Channel n                                  */
+            __IOM uint32_t REQ_SELB : 10; /*!< [19..10] DMA Resource Select for Channel n + 1                            */
+            __IOM uint32_t REQ_SELC : 10; /*!< [29..20] DMA Resource Select for Channel n + 2                            */
+            uint32_t                : 2;
+        } DMAC1_RSSEL_b[6];
+    };
+
+    union
+    {
+        __IOM uint32_t DMAC2_RSSEL[6];    /*!< (@ 0x00000030) DMAC Unit 2 Resource Select Register [0..5]                */
+
+        struct
+        {
+            __IOM uint32_t REQ_SELA : 10; /*!< [9..0] DMA Resource Select for Channel n                                  */
+            __IOM uint32_t REQ_SELB : 10; /*!< [19..10] DMA Resource Select for Channel n + 1                            */
+            __IOM uint32_t REQ_SELC : 10; /*!< [29..20] DMA Resource Select for Channel n + 2                            */
+            uint32_t                : 2;
+        } DMAC2_RSSEL_b[6];
+    };
+} R_DMA_Type;                             /*!< Size = 72 (0x48)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PORT_SRN                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports (Safety region N) (R_PORT_SRN)
+ */
+
+typedef struct                         /*!< (@ 0x802B0000) R_PORT_SRN Structure                                       */
+{
+    union
+    {
+        __IOM uint8_t P[13];           /*!< (@ 0x00000000) Port [0..12] Register                                      */
+
+        struct
+        {
+            __IOM uint8_t POUT_0 : 1;  /*!< [0..0] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_1 : 1;  /*!< [1..1] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_2 : 1;  /*!< [2..2] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_3 : 1;  /*!< [3..3] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_4 : 1;  /*!< [4..4] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_5 : 1;  /*!< [5..5] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_6 : 1;  /*!< [6..6] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_7 : 1;  /*!< [7..7] Pm_n Output Data Store (n: bit position)                           */
+        } P_b[13];
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[124];
+
+    union
+    {
+        __IOM uint16_t PM[13];         /*!< (@ 0x00000200) Port [0..12] Mode Register                                 */
+
+        struct
+        {
+            __IOM uint16_t PM0 : 2;    /*!< [1..0] Pm_0 I/O Select                                                    */
+            __IOM uint16_t PM1 : 2;    /*!< [3..2] Pm_1 I/O Select                                                    */
+            __IOM uint16_t PM2 : 2;    /*!< [5..4] Pm_2 I/O Select                                                    */
+            __IOM uint16_t PM3 : 2;    /*!< [7..6] Pm_3 I/O Select                                                    */
+            __IOM uint16_t PM4 : 2;    /*!< [9..8] Pm_4 I/O Select                                                    */
+            __IOM uint16_t PM5 : 2;    /*!< [11..10] Pm_5 I/O Select                                                  */
+            __IOM uint16_t PM6 : 2;    /*!< [13..12] Pm_6 I/O Select                                                  */
+            __IOM uint16_t PM7 : 2;    /*!< [15..14] Pm_7 I/O Select                                                  */
+        } PM_b[13];
+    };
+    __IM uint16_t RESERVED3;
+    __IM uint32_t RESERVED4[121];
+
+    union
+    {
+        __IOM uint8_t PMC[13];         /*!< (@ 0x00000400) Port [0..12] Mode Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t PMC0 : 1;    /*!< [0..0] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC1 : 1;    /*!< [1..1] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC2 : 1;    /*!< [2..2] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC3 : 1;    /*!< [3..3] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC4 : 1;    /*!< [4..4] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC5 : 1;    /*!< [5..5] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC6 : 1;    /*!< [6..6] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC7 : 1;    /*!< [7..7] Pm_n Pin Mode Control (n: bit position)                            */
+        } PMC_b[13];
+    };
+    __IM uint8_t          RESERVED5;
+    __IM uint16_t         RESERVED6;
+    __IM uint32_t         RESERVED7[124];
+    __IOM R_PORT_PFC_Type PFC[13];     /*!< (@ 0x00000600) Port [0..12] Function Control Register                     */
+    __IM uint32_t         RESERVED8[102];
+
+    union
+    {
+        __IM uint8_t PIN[13];          /*!< (@ 0x00000800) Port [0..12] Input Register                                */
+
+        struct
+        {
+            __IM uint8_t PIN0 : 1;     /*!< [0..0] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN1 : 1;     /*!< [1..1] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN2 : 1;     /*!< [2..2] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN3 : 1;     /*!< [3..3] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN4 : 1;     /*!< [4..4] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN5 : 1;     /*!< [5..5] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN6 : 1;     /*!< [6..6] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN7 : 1;     /*!< [7..7] Pm_n Pin Input (n: bit position)                                   */
+        } PIN_b[13];
+    };
+    __IM uint8_t            RESERVED9;
+    __IM uint16_t           RESERVED10;
+    __IM uint32_t           RESERVED11[124];
+    __IOM R_PORT_DRCTL_Type DRCTL[13]; /*!< (@ 0x00000A00) I/O Buffer [0..12] Function Switching Register             */
+    __IM uint32_t           RESERVED12[102];
+
+    union
+    {
+        __IOM uint8_t RSELP[13];       /*!< (@ 0x00000C00) Port [0..12] Region Select Register                        */
+
+        struct
+        {
+            __IOM uint8_t RS0 : 1;     /*!< [0..0] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS1 : 1;     /*!< [1..1] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS2 : 1;     /*!< [2..2] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS3 : 1;     /*!< [3..3] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS4 : 1;     /*!< [4..4] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS5 : 1;     /*!< [5..5] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS6 : 1;     /*!< [6..6] Pm_n pin I/O port registers Region Select (n = bit position)       */
+            __IOM uint8_t RS7 : 1;     /*!< [7..7] Pm_n pin I/O port registers Region Select (n = bit position)       */
+        } RSELP_b[13];
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+    __IM uint32_t RESERVED15[252];
+
+    union
+    {
+        __IOM uint8_t SLPORT[13];      /*!< (@ 0x00001000) Port [0..12] Access Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t SL : 2;      /*!< [1..0] SL                                                                 */
+            uint8_t          : 6;
+        } SLPORT_b[13];
+    };
+    __IM uint8_t  RESERVED16;
+    __IM uint16_t RESERVED17;
+    __IM uint32_t RESERVED18[764];
+
+    union
+    {
+        __IOM uint8_t SLRSELP;         /*!< (@ 0x00001C00) RSELP Access Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t SL : 2;      /*!< [1..0] SL                                                                 */
+            uint8_t          : 6;
+        } SLRSELP_b;
+    };
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
+    __IM uint32_t RESERVED21[191];
+
+    union
+    {
+        __IOM uint32_t SLPSR;          /*!< (@ 0x00001F00) Port Security Register Access Control Register             */
+
+        struct
+        {
+            __IOM uint32_t SL : 2;     /*!< [1..0] SL                                                                 */
+            uint32_t          : 30;
+        } SLPSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RSELPSR;         /*!< (@ 0x00001F04) Port Security Register Access Region Select Register       */
+
+        struct
+        {
+            __IOM uint8_t RS : 1;      /*!< [0..0] RS                                                                 */
+            uint8_t          : 7;
+        } RSELPSR_b;
+    };
+    __IM uint8_t  RESERVED22;
+    __IM uint16_t RESERVED23;
+} R_PORT_COMMON_Type;                  /*!< Size = 7944 (0x1f08)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PORT_NSR                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports (Non safety region) (R_PORT_NSR)
+ */
+
+typedef struct                         /*!< (@ 0x802C0000) R_PORT_NSR Structure                                       */
+{
+    union
+    {
+        __IOM uint8_t P[36];           /*!< (@ 0x00000000) Port [0..35] Register                                      */
+
+        struct
+        {
+            __IOM uint8_t POUT_0 : 1;  /*!< [0..0] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_1 : 1;  /*!< [1..1] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_2 : 1;  /*!< [2..2] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_3 : 1;  /*!< [3..3] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_4 : 1;  /*!< [4..4] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_5 : 1;  /*!< [5..5] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_6 : 1;  /*!< [6..6] Pm_n Output Data Store (n: bit position)                           */
+            __IOM uint8_t POUT_7 : 1;  /*!< [7..7] Pm_n Output Data Store (n: bit position)                           */
+        } P_b[36];
+    };
+    __IM uint32_t RESERVED[119];
+
+    union
+    {
+        __IOM uint16_t PM[36];         /*!< (@ 0x00000200) Port [0..35] Mode Register                                 */
+
+        struct
+        {
+            __IOM uint16_t PM0 : 2;    /*!< [1..0] Pm_0 I/O Select                                                    */
+            __IOM uint16_t PM1 : 2;    /*!< [3..2] Pm_1 I/O Select                                                    */
+            __IOM uint16_t PM2 : 2;    /*!< [5..4] Pm_2 I/O Select                                                    */
+            __IOM uint16_t PM3 : 2;    /*!< [7..6] Pm_3 I/O Select                                                    */
+            __IOM uint16_t PM4 : 2;    /*!< [9..8] Pm_4 I/O Select                                                    */
+            __IOM uint16_t PM5 : 2;    /*!< [11..10] Pm_5 I/O Select                                                  */
+            __IOM uint16_t PM6 : 2;    /*!< [13..12] Pm_6 I/O Select                                                  */
+            __IOM uint16_t PM7 : 2;    /*!< [15..14] Pm_7 I/O Select                                                  */
+        } PM_b[36];
+    };
+    __IM uint32_t RESERVED1[110];
+
+    union
+    {
+        __IOM uint8_t PMC[36];         /*!< (@ 0x00000400) Port [0..35] Mode Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t PMC0 : 1;    /*!< [0..0] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC1 : 1;    /*!< [1..1] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC2 : 1;    /*!< [2..2] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC3 : 1;    /*!< [3..3] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC4 : 1;    /*!< [4..4] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC5 : 1;    /*!< [5..5] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC6 : 1;    /*!< [6..6] Pm_n Pin Mode Control (n: bit position)                            */
+            __IOM uint8_t PMC7 : 1;    /*!< [7..7] Pm_n Pin Mode Control (n: bit position)                            */
+        } PMC_b[36];
+    };
+    __IM uint32_t            RESERVED2[119];
+    __IOM R_PORT_NS_PFC_Type PFC[36];  /*!< (@ 0x00000600) Port [0..35] Function Control Register                     */
+    __IM uint32_t            RESERVED3[56];
+
+    union
+    {
+        __IM uint8_t PIN[36];             /*!< (@ 0x00000800) Port [0..35] Input Register                                */
+
+        struct
+        {
+            __IM uint8_t PIN0 : 1;        /*!< [0..0] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN1 : 1;        /*!< [1..1] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN2 : 1;        /*!< [2..2] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN3 : 1;        /*!< [3..3] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN4 : 1;        /*!< [4..4] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN5 : 1;        /*!< [5..5] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN6 : 1;        /*!< [6..6] Pm_n Pin Input (n: bit position)                                   */
+            __IM uint8_t PIN7 : 1;        /*!< [7..7] Pm_n Pin Input (n: bit position)                                   */
+        } PIN_b[36];
+    };
+    __IM uint32_t              RESERVED4[119];
+    __IOM R_PORT_NS_DRCTL_Type DRCTL[36]; /*!< (@ 0x00000A00) I/O Buffer [0..35] Function Switching Register             */
+    __IM uint32_t              RESERVED5[184];
+
+    union
+    {
+        __IOM uint8_t ELC_PGR[2];      /*!< (@ 0x00000E00) ELC Port Group Setting Register [0..1]                     */
+
+        struct
+        {
+            __IOM uint8_t PG0 : 1;     /*!< [0..0] Port Group Setting                                                 */
+            __IOM uint8_t PG1 : 1;     /*!< [1..1] Port Group Setting                                                 */
+            __IOM uint8_t PG2 : 1;     /*!< [2..2] Port Group Setting                                                 */
+            __IOM uint8_t PG3 : 1;     /*!< [3..3] Port Group Setting                                                 */
+            __IOM uint8_t PG4 : 1;     /*!< [4..4] Port Group Setting                                                 */
+            __IOM uint8_t PG5 : 1;     /*!< [5..5] Port Group Setting                                                 */
+            __IOM uint8_t PG6 : 1;     /*!< [6..6] Port Group Setting                                                 */
+            __IOM uint8_t PG7 : 1;     /*!< [7..7] Port Group Setting                                                 */
+        } ELC_PGR_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t ELC_PGC[2];               /*!< (@ 0x00000E02) ELC Port Group Control Register [0..1]                     */
+
+        struct
+        {
+            __IOM uint8_t PGCI   : 2;           /*!< [1..0] Event Output Edge Select                                           */
+            __IOM uint8_t PGCOVE : 1;           /*!< [2..2] PDBF Overwrite                                                     */
+            uint8_t              : 1;
+            __IOM uint8_t PGCO   : 3;           /*!< [6..4] Port Group Operation Select                                        */
+            uint8_t              : 1;
+        } ELC_PGC_b[2];
+    };
+    __IOM R_PORT_NSR_ELC_PDBF_Type ELC_PDBF[2]; /*!< (@ 0x00000E04) ELC Port Buffer Register [0..1]                            */
+
+    union
+    {
+        __IOM uint8_t ELC_PEL[4];               /*!< (@ 0x00000E0C) ELC Port Setting Register [0..3]                           */
+
+        struct
+        {
+            __IOM uint8_t PSB : 3;              /*!< [2..0] Bit Number Specification                                           */
+            __IOM uint8_t PSP : 2;              /*!< [4..3] Port Number Specification                                          */
+            __IOM uint8_t PSM : 2;              /*!< [6..5] Event Link Specification                                           */
+            uint8_t           : 1;
+        } ELC_PEL_b[4];
+    };
+
+    union
+    {
+        __IOM uint8_t ELC_DPTC;        /*!< (@ 0x00000E10) ELC Edge Detection Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t PTC0 : 1;    /*!< [0..0] Single Input Port n Edge Detection                                 */
+            __IOM uint8_t PTC1 : 1;    /*!< [1..1] Single Input Port n Edge Detection                                 */
+            __IOM uint8_t PTC2 : 1;    /*!< [2..2] Single Input Port n Edge Detection                                 */
+            __IOM uint8_t PTC3 : 1;    /*!< [3..3] Single Input Port n Edge Detection                                 */
+            uint8_t            : 4;
+        } ELC_DPTC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ELC_ELSR2;       /*!< (@ 0x00000E11) ELC Port Event Control Register                            */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t PEG1 : 1;    /*!< [2..2] ELC Port Buffer Register (ELC_PDBFn) write access control.
+                                        *   When set to 1, writing to the ELC_PDBFn register via Internal
+                                        *   peripheral bus is disabled, preventing overwriting.                       */
+            __IOM uint8_t PEG2 : 1;    /*!< [3..3] ELC Port Buffer Register (ELC_PDBFn) write access control.
+                                        *   When set to 1, writing to the ELC_PDBFn register via Internal
+                                        *   peripheral bus is disabled, preventing overwriting.                       */
+            __IOM uint8_t PES0 : 1;    /*!< [4..4] Single Port n Event Link Function Enable                           */
+            __IOM uint8_t PES1 : 1;    /*!< [5..5] Single Port n Event Link Function Enable                           */
+            __IOM uint8_t PES2 : 1;    /*!< [6..6] Single Port n Event Link Function Enable                           */
+            __IOM uint8_t PES3 : 1;    /*!< [7..7] Single Port n Event Link Function Enable                           */
+        } ELC_ELSR2_b;
+    };
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[123];
+
+    union
+    {
+        __IOM uint8_t SLPORT[36];      /*!< (@ 0x00001000) Port [0..35] Access Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t SL : 2;      /*!< [1..0] SL                                                                 */
+            uint8_t          : 6;
+        } SLPORT_b[36];
+    };
+    __IM uint32_t RESERVED8[887];
+
+    union
+    {
+        __IOM uint32_t SLELC_PGRC;          /*!< (@ 0x00001E00) ELC_PGR/ELC_PGC Security Level Register                    */
+
+        struct
+        {
+            __IOM uint32_t ELC_PGR1_SL : 2; /*!< [1..0] ELC_PGR1_SL                                                        */
+            uint32_t                   : 6;
+            __IOM uint32_t ELC_PGR2_SL : 2; /*!< [9..8] ELC_PGR2_SL                                                        */
+            uint32_t                   : 6;
+            __IOM uint32_t ELC_PGC1_SL : 2; /*!< [17..16] ELC_PGC1_SL                                                      */
+            uint32_t                   : 6;
+            __IOM uint32_t ELC_PGC2_SL : 2; /*!< [25..24] ELC_PGC2_SL                                                      */
+            uint32_t                   : 6;
+        } SLELC_PGRC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SLELC_PDBF[2];       /*!< (@ 0x00001E04) ELC_PDBFn Security Level Register [0..1]                   */
+
+        struct
+        {
+            __IOM uint32_t ELC_PDBF_SL : 2; /*!< [1..0] ELC_PDBF_SL                                                        */
+            uint32_t                   : 30;
+        } SLELC_PDBF_b[2];
+    };
+
+    union
+    {
+        __IOM uint32_t SLELC_PEL;           /*!< (@ 0x00001E0C) ELC_PEL Security Level Register                            */
+
+        struct
+        {
+            __IOM uint32_t ELC_PEL0_SL : 2; /*!< [1..0] ELC_PEL0_SL                                                        */
+            uint32_t                   : 6;
+            __IOM uint32_t ELC_PEL1_SL : 2; /*!< [9..8] ELC_PEL1_SL                                                        */
+            uint32_t                   : 6;
+            __IOM uint32_t ELC_PEL2_SL : 2; /*!< [17..16] ELC_PEL2_SL                                                      */
+            uint32_t                   : 6;
+            __IOM uint32_t ELC_PEL3_SL : 2; /*!< [25..24] ELC_PEL3_SL                                                      */
+            uint32_t                   : 6;
+        } SLELC_PEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SLELC_DE;             /*!< (@ 0x00001E10) ELC_DPTC/ELC_ELSR2 Security Level Register                 */
+
+        struct
+        {
+            __IOM uint16_t ELC_DPTC_SL  : 2; /*!< [1..0] ELC_DPTC register Security Level                                   */
+            uint16_t                    : 6;
+            __IOM uint16_t ELC_ELSR2_SL : 2; /*!< [9..8] ELC_ELSR2 register Security Level                                  */
+            uint16_t                    : 6;
+        } SLELC_DE_b;
+    };
+    __IM uint16_t RESERVED9;
+    __IM uint32_t RESERVED10[59];
+
+    union
+    {
+        __IOM uint32_t SLPSRNS;        /*!< (@ 0x00001F00) Port NS Security Register Access Control Register          */
+
+        struct
+        {
+            __IOM uint32_t SL : 2;     /*!< [1..0] SL                                                                 */
+            uint32_t          : 30;
+        } SLPSRNS_b;
+    };
+} R_PORT_NS_COMMON_Type;               /*!< Size = 7940 (0x1f04)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DDRSS                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_DDRSS (R_DDRSS)
+ */
+
+typedef struct                                 /*!< (@ 0x80300000) R_DDRSS Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_00; /*!< (@ 0x00000000) DDR_MEMC_DENALI_CTL_00                                     */
+
+        struct
+        {
+            __IOM uint32_t start : 1;          /*!< [0..0] start                                                              */
+            uint32_t             : 31;
+        } DDR_MEMC_DENALI_CTL_00_b;
+    };
+    __IM uint32_t RESERVED[63];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_64; /*!< (@ 0x00000100) DDR_MEMC_DENALI_CTL_64                                     */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t BSTLEN : 6; /*!< [13..8] BSTLEN                                                            */
+            uint32_t              : 18;
+        } DDR_MEMC_DENALI_CTL_64_b;
+    };
+    __IM uint32_t RESERVED1[38];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_103;     /*!< (@ 0x0000019C) DDR_MEMC_DENALI_CTL_103                                    */
+
+        struct
+        {
+            __IOM uint32_t PWRUP_SREFRESH_EXIT : 1; /*!< [0..0] PWRUP_SREFRESH_EXIT                                                */
+            uint32_t                           : 31;
+        } DDR_MEMC_DENALI_CTL_103_b;
+    };
+    __IM uint32_t RESERVED2[54];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_158; /*!< (@ 0x00000278) DDR_MEMC_DENALI_CTL_158                                    */
+
+        struct
+        {
+            uint32_t                     : 16;
+            __IOM uint32_t LPI_WAKEUP_EN : 6; /*!< [21..16] LPI_WAKEUP_EN                                                    */
+            uint32_t                     : 10;
+        } DDR_MEMC_DENALI_CTL_158_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_160; /*!< (@ 0x00000280) DDR_MEMC_DENALI_CTL_160                                    */
+
+        struct
+        {
+            uint32_t                        : 24;
+            __IOM uint32_t LP_AUTO_ENTRY_EN : 4; /*!< [27..24] LP_AUTO_ENTRY_EN                                                 */
+            uint32_t                        : 4;
+        } DDR_MEMC_DENALI_CTL_160_b;
+    };
+    __IM uint32_t RESERVED4[6];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_167; /*!< (@ 0x0000029C) DDR_MEMC_DENALI_CTL_167                                    */
+
+        struct
+        {
+            uint32_t                   : 8;
+            __IOM uint32_t PCPCS_PD_EN : 1; /*!< [8..8] PCPCS_PD_EN                                                        */
+            uint32_t                   : 23;
+        } DDR_MEMC_DENALI_CTL_167_b;
+    };
+    __IM uint32_t RESERVED5[51];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_219; /*!< (@ 0x0000036C) DDR_MEMC_DENALI_CTL_219                                    */
+
+        struct
+        {
+            uint32_t                  : 8;
+            __IOM uint32_t BIST_GO    : 1; /*!< [8..8] BIST_GO                                                            */
+            uint32_t                  : 15;
+            __IOM uint32_t ADDR_SPACE : 6; /*!< [29..24] ADDR_SPACE                                                       */
+            uint32_t                  : 2;
+        } DDR_MEMC_DENALI_CTL_219_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_220; /*!< (@ 0x00000370) DDR_MEMC_DENALI_CTL_220                                    */
+
+        struct
+        {
+            __IOM uint32_t BIST_DATA_CHECK : 1; /*!< [0..0] BIST_DATA_CHECK                                                    */
+            uint32_t                       : 31;
+        } DDR_MEMC_DENALI_CTL_220_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_221;     /*!< (@ 0x00000374) DDR_MEMC_DENALI_CTL_221                                    */
+
+        struct
+        {
+            __IOM uint32_t BIST_START_ADDRESS : 32; /*!< [31..0] BIST_START_ADDRESS                                                */
+        } DDR_MEMC_DENALI_CTL_221_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_222;      /*!< (@ 0x00000378) DDR_MEMC_DENALI_CTL_222                                    */
+
+        struct
+        {
+            __IOM uint32_t BIST_START_ADDRESS32 : 1; /*!< [0..0] BIST_START_ADDRESS32                                               */
+            uint32_t                            : 31;
+        } DDR_MEMC_DENALI_CTL_222_b;
+    };
+    __IM uint32_t RESERVED6[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_225; /*!< (@ 0x00000384) DDR_MEMC_DENALI_CTL_225                                    */
+
+        struct
+        {
+            __IOM uint32_t BIST_TEST_MODE : 3;  /*!< [2..0] BIST_TEST_MODE                                                     */
+            uint32_t                      : 29;
+        } DDR_MEMC_DENALI_CTL_225_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_226;     /*!< (@ 0x00000388) DDR_MEMC_DENALI_CTL_226                                    */
+
+        struct
+        {
+            __IOM uint32_t BIST_DATA_PATTERN0 : 32; /*!< [31..0] BIST_DATA_PATTERN0                                                */
+        } DDR_MEMC_DENALI_CTL_226_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_227;     /*!< (@ 0x0000038C) DDR_MEMC_DENALI_CTL_227                                    */
+
+        struct
+        {
+            __IOM uint32_t BIST_DATA_PATTERN1 : 32; /*!< [31..0] BIST_DATA_PATTERN1                                                */
+        } DDR_MEMC_DENALI_CTL_227_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_228;     /*!< (@ 0x00000390) DDR_MEMC_DENALI_CTL_228                                    */
+
+        struct
+        {
+            __IOM uint32_t BIST_DATA_PATTERN2 : 32; /*!< [31..0] BIST_DATA_PATTERN2                                                */
+        } DDR_MEMC_DENALI_CTL_228_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_229;     /*!< (@ 0x00000394) DDR_MEMC_DENALI_CTL_229                                    */
+
+        struct
+        {
+            __IOM uint32_t BIST_DATA_PATTERN3 : 32; /*!< [31..0] BIST_DATA_PATTERN3                                                */
+        } DDR_MEMC_DENALI_CTL_229_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_231; /*!< (@ 0x0000039C) DDR_MEMC_DENALI_CTL_231                                    */
+
+        struct
+        {
+            uint32_t                  : 24;
+            __IOM uint32_t ECC_ENABLE : 2; /*!< [25..24] ECC_ENABLE                                                       */
+            uint32_t                  : 6;
+        } DDR_MEMC_DENALI_CTL_231_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_232;       /*!< (@ 0x000003A0) DDR_MEMC_DENALI_CTL_232                                    */
+
+        struct
+        {
+            __IOM uint32_t FWC                  : 1;  /*!< [0..0] FWC                                                                */
+            uint32_t                            : 7;
+            __IOM uint32_t XOR_CHECK_BITS       : 16; /*!< [23..8] XOR_CHECK_BITS                                                    */
+            __IOM uint32_t ECC_DISABLE_W_UC_ERR : 1;  /*!< [24..24] ECC_DISABLE_W_UC_ERR                                             */
+            uint32_t                            : 7;
+        } DDR_MEMC_DENALI_CTL_232_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_233;        /*!< (@ 0x000003A4) DDR_MEMC_DENALI_CTL_233                                    */
+
+        struct
+        {
+            __IOM uint32_t ECC_WRITEBACK_EN       : 1; /*!< [0..0] ECC_WRITEBACK_EN                                                   */
+            uint32_t                              : 7;
+            __IOM uint32_t INLINE_ECC_SAME_PAGE   : 1; /*!< [8..8] INLINE_ECC_SAME_PAGE                                               */
+            uint32_t                              : 7;
+            __IOM uint32_t INLINE_ECC_BANK_OFFSET : 3; /*!< [18..16] INLINE_ECC_BANK_OFFSET                                           */
+            uint32_t                              : 5;
+            __IOM uint32_t ECC_READ_CACHING_EN    : 1; /*!< [24..24] ECC_READ_CACHING_EN                                              */
+            uint32_t                              : 7;
+        } DDR_MEMC_DENALI_CTL_233_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_234;        /*!< (@ 0x000003A8) DDR_MEMC_DENALI_CTL_234                                    */
+
+        struct
+        {
+            __IOM uint32_t ECC_WRITE_COMBINING_EN : 1; /*!< [0..0] ECC_WRITE_COMBINING_EN                                             */
+            uint32_t                              : 31;
+        } DDR_MEMC_DENALI_CTL_234_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_235; /*!< (@ 0x000003AC) DDR_MEMC_DENALI_CTL_235                                    */
+
+        struct
+        {
+            __IM uint32_t ECC_U_ADDR : 32;     /*!< [31..0] ECC_U_ADDR                                                        */
+        } DDR_MEMC_DENALI_CTL_235_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_236; /*!< (@ 0x000003B0) DDR_MEMC_DENALI_CTL_236                                    */
+
+        struct
+        {
+            __IM uint32_t ECC_U_ADDR32 : 1;    /*!< [0..0] ECC_U_ADDR32                                                       */
+            uint32_t                   : 7;
+            __IM uint32_t ECC_U_SYND   : 8;    /*!< [15..8] ECC_U_SYND                                                        */
+            uint32_t                   : 16;
+        } DDR_MEMC_DENALI_CTL_236_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_237; /*!< (@ 0x000003B4) DDR_MEMC_DENALI_CTL_237                                    */
+
+        struct
+        {
+            __IM uint32_t ECC_U_DATA0 : 32;    /*!< [31..0] ECC_U_DATA0                                                       */
+        } DDR_MEMC_DENALI_CTL_237_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_238; /*!< (@ 0x000003B8) DDR_MEMC_DENALI_CTL_238                                    */
+
+        struct
+        {
+            __IM uint32_t ECC_U_DATA1 : 32;    /*!< [31..0] ECC_U_DATA1                                                       */
+        } DDR_MEMC_DENALI_CTL_238_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_239; /*!< (@ 0x000003BC) DDR_MEMC_DENALI_CTL_239                                    */
+
+        struct
+        {
+            __IM uint32_t ECC_C_ADDR : 32;     /*!< [31..0] ECC_C_ADDR                                                        */
+        } DDR_MEMC_DENALI_CTL_239_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_240; /*!< (@ 0x000003C0) DDR_MEMC_DENALI_CTL_240                                    */
+
+        struct
+        {
+            __IM uint32_t ECC_C_ADDR32 : 1;    /*!< [0..0] ECC_C_ADDR32                                                       */
+            uint32_t                   : 7;
+            __IM uint32_t ECC_C_SYND   : 8;    /*!< [15..8] ECC_C_SYND                                                        */
+            uint32_t                   : 16;
+        } DDR_MEMC_DENALI_CTL_240_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_241; /*!< (@ 0x000003C4) DDR_MEMC_DENALI_CTL_241                                    */
+
+        struct
+        {
+            __IM uint32_t ECC_C_DATA0 : 32;    /*!< [31..0] ECC_C_DATA0                                                       */
+        } DDR_MEMC_DENALI_CTL_241_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_242; /*!< (@ 0x000003C8) DDR_MEMC_DENALI_CTL_242                                    */
+
+        struct
+        {
+            __IM uint32_t ECC_C_DATA1 : 32;    /*!< [31..0] ECC_C_DATA1                                                       */
+        } DDR_MEMC_DENALI_CTL_242_b;
+    };
+    __IM uint32_t RESERVED8;
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_244;   /*!< (@ 0x000003D0) DDR_MEMC_DENALI_CTL_244                                    */
+
+        struct
+        {
+            __IM uint32_t RMODW_ECC_U_ADDR : 32; /*!< [31..0] RMODW_ECC_U_ADDR                                                  */
+        } DDR_MEMC_DENALI_CTL_244_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_245;    /*!< (@ 0x000003D4) DDR_MEMC_DENALI_CTL_245                                    */
+
+        struct
+        {
+            __IM uint32_t RMODW_ECC_U_ADDR32 : 1; /*!< [0..0] RMODW_ECC_U_ADDR32                                                 */
+            uint32_t                         : 7;
+            __IM uint32_t RMODW_ECC_U_SYND   : 8; /*!< [15..8] RMODW_ECC_U_SYND                                                  */
+            uint32_t                         : 16;
+        } DDR_MEMC_DENALI_CTL_245_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_246;    /*!< (@ 0x000003D8) DDR_MEMC_DENALI_CTL_246                                    */
+
+        struct
+        {
+            __IM uint32_t RMODW_ECC_U_DATA0 : 32; /*!< [31..0] RMODW_ECC_U_DATA0                                                 */
+        } DDR_MEMC_DENALI_CTL_246_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_247;    /*!< (@ 0x000003DC) DDR_MEMC_DENALI_CTL_247                                    */
+
+        struct
+        {
+            __IM uint32_t RMODW_ECC_U_DATA1 : 32; /*!< [31..0] RMODW_ECC_U_DATA1                                                 */
+        } DDR_MEMC_DENALI_CTL_247_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_248;   /*!< (@ 0x000003E0) DDR_MEMC_DENALI_CTL_248                                    */
+
+        struct
+        {
+            __IM uint32_t RMODW_ECC_C_ADDR : 32; /*!< [31..0] RMODW_ECC_C_ADDR                                                  */
+        } DDR_MEMC_DENALI_CTL_248_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_249;    /*!< (@ 0x000003E4) DDR_MEMC_DENALI_CTL_249                                    */
+
+        struct
+        {
+            __IM uint32_t RMODW_ECC_C_ADDR32 : 1; /*!< [0..0] RMODW_ECC_C_ADDR32                                                 */
+            uint32_t                         : 7;
+            __IM uint32_t RMODW_ECC_C_SYND   : 8; /*!< [15..8] RMODW_ECC_C_SYND                                                  */
+            uint32_t                         : 16;
+        } DDR_MEMC_DENALI_CTL_249_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_250;    /*!< (@ 0x000003E8) DDR_MEMC_DENALI_CTL_250                                    */
+
+        struct
+        {
+            __IM uint32_t RMODW_ECC_C_DATA0 : 32; /*!< [31..0] RMODW_ECC_C_DATA0                                                 */
+        } DDR_MEMC_DENALI_CTL_250_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_251;    /*!< (@ 0x000003EC) DDR_MEMC_DENALI_CTL_251                                    */
+
+        struct
+        {
+            __IM uint32_t RMODW_ECC_C_DATA1 : 32; /*!< [31..0] RMODW_ECC_C_DATA1                                                 */
+        } DDR_MEMC_DENALI_CTL_251_b;
+    };
+    __IM uint32_t RESERVED9[17];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_269; /*!< (@ 0x00000434) DDR_MEMC_DENALI_CTL_269                                    */
+
+        struct
+        {
+            uint32_t                            : 16;
+            __OM uint32_t ECC_SCRUB_START       : 1; /*!< [16..16] ECC_SCRUB_START                                                  */
+            uint32_t                            : 7;
+            __IM uint32_t ECC_SCRUB_IN_PROGRESS : 1; /*!< [24..24] ECC_SCRUB_IN_PROGRESS                                            */
+            uint32_t                            : 7;
+        } DDR_MEMC_DENALI_CTL_269_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_270; /*!< (@ 0x00000438) DDR_MEMC_DENALI_CTL_270                                    */
+
+        struct
+        {
+            __IOM uint32_t ECC_SCRUB_LEN  : 13; /*!< [12..0] ECC_SCRUB_LEN                                                     */
+            uint32_t                      : 3;
+            __IOM uint32_t ECC_SCRUB_MODE : 1;  /*!< [16..16] ECC_SCRUB_MODE                                                   */
+            uint32_t                      : 15;
+        } DDR_MEMC_DENALI_CTL_270_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_271;     /*!< (@ 0x0000043C) DDR_MEMC_DENALI_CTL_271                                    */
+
+        struct
+        {
+            __IOM uint32_t ECC_SCRUB_INTERVAL : 16; /*!< [15..0] ECC_SCRUB_INTERVAL                                                */
+            __IOM uint32_t ECC_SCRUB_IDLE_CNT : 16; /*!< [31..16] ECC_SCRUB_IDLE_CNT                                               */
+        } DDR_MEMC_DENALI_CTL_271_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_272;       /*!< (@ 0x00000440) DDR_MEMC_DENALI_CTL_272                                    */
+
+        struct
+        {
+            __IOM uint32_t ECC_SCRUB_START_ADDR : 32; /*!< [31..0] ECC_SCRUB_START_ADDR                                              */
+        } DDR_MEMC_DENALI_CTL_272_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_273;        /*!< (@ 0x00000444) DDR_MEMC_DENALI_CTL_273                                    */
+
+        struct
+        {
+            __IOM uint32_t ECC_SCRUB_START_ADDR32 : 1; /*!< [0..0] ECC_SCRUB_START_ADDR32                                             */
+            uint32_t                              : 31;
+        } DDR_MEMC_DENALI_CTL_273_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_274;     /*!< (@ 0x00000448) DDR_MEMC_DENALI_CTL_274                                    */
+
+        struct
+        {
+            __IOM uint32_t ECC_SCRUB_END_ADDR : 32; /*!< [31..0] ECC_SCRUB_END_ADDR                                                */
+        } DDR_MEMC_DENALI_CTL_274_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_275;      /*!< (@ 0x0000044C) DDR_MEMC_DENALI_CTL_275                                    */
+
+        struct
+        {
+            __IOM uint32_t ECC_SCRUB_END_ADDR32 : 1; /*!< [0..0] ECC_SCRUB_END_ADDR32                                               */
+            uint32_t                            : 31;
+        } DDR_MEMC_DENALI_CTL_275_b;
+    };
+    __IM uint32_t RESERVED10[28];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_304; /*!< (@ 0x000004C0) DDR_MEMC_DENALI_CTL_304                                    */
+
+        struct
+        {
+            uint32_t                      : 16;
+            __IOM uint32_t CS_VAL_UPPER_0 : 16; /*!< [31..16] CS_VAL_UPPER_0                                                   */
+        } DDR_MEMC_DENALI_CTL_304_b;
+    };
+    __IM uint32_t RESERVED11;
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_306; /*!< (@ 0x000004C8) DDR_MEMC_DENALI_CTL_306                                    */
+
+        struct
+        {
+            uint32_t                      : 16;
+            __IOM uint32_t CS_VAL_UPPER_1 : 16; /*!< [31..16] CS_VAL_UPPER_1                                                   */
+        } DDR_MEMC_DENALI_CTL_306_b;
+    };
+    __IM uint32_t RESERVED12[5];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_312; /*!< (@ 0x000004E0) DDR_MEMC_DENALI_CTL_312                                    */
+
+        struct
+        {
+            uint32_t              : 24;
+            __IOM uint32_t CS_MAP : 2; /*!< [25..24] CS_MAP                                                           */
+            uint32_t              : 6;
+        } DDR_MEMC_DENALI_CTL_312_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_313;  /*!< (@ 0x000004E4) DDR_MEMC_DENALI_CTL_313                                    */
+
+        struct
+        {
+            __IOM uint32_t MEM_DP_REDUCTION : 1; /*!< [0..0] MEM_DP_REDUCTION                                                   */
+            uint32_t                        : 31;
+        } DDR_MEMC_DENALI_CTL_313_b;
+    };
+    __IM uint32_t RESERVED13[4];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_318;   /*!< (@ 0x000004F8) DDR_MEMC_DENALI_CTL_318                                    */
+
+        struct
+        {
+            __IOM uint32_t device0_byte0_cs0 : 4; /*!< [3..0] device0_byte0_cs0                                                  */
+            uint32_t                         : 4;
+            __IOM uint32_t device1_byte0_cs0 : 4; /*!< [11..8] device1_byte0_cs0                                                 */
+            uint32_t                         : 4;
+            __IOM uint32_t device2_byte0_cs0 : 4; /*!< [19..16] device2_byte0_cs0                                                */
+            uint32_t                         : 4;
+            __IOM uint32_t device3_byte0_cs0 : 4; /*!< [27..24] device3_byte0_cs0                                                */
+            uint32_t                         : 4;
+        } DDR_MEMC_DENALI_CTL_318_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_319;   /*!< (@ 0x000004FC) DDR_MEMC_DENALI_CTL_319                                    */
+
+        struct
+        {
+            __IOM uint32_t device0_byte0_cs1 : 4; /*!< [3..0] device0_byte0_cs1                                                  */
+            uint32_t                         : 4;
+            __IOM uint32_t device1_byte0_cs1 : 4; /*!< [11..8] device1_byte0_cs1                                                 */
+            uint32_t                         : 4;
+            __IOM uint32_t device2_byte0_cs1 : 4; /*!< [19..16] device2_byte0_cs1                                                */
+            uint32_t                         : 4;
+            __IOM uint32_t device3_byte0_cs1 : 4; /*!< [27..24] device3_byte0_cs1                                                */
+            uint32_t                         : 4;
+        } DDR_MEMC_DENALI_CTL_319_b;
+    };
+    __IM uint32_t RESERVED14[6];
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_326;    /*!< (@ 0x00000518) DDR_MEMC_DENALI_CTL_326                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_MASTER : 32; /*!< [31..0] INT_STATUS_MASTER                                                 */
+        } DDR_MEMC_DENALI_CTL_326_b;
+    };
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_327;  /*!< (@ 0x0000051C) DDR_MEMC_DENALI_CTL_327                                    */
+
+        struct
+        {
+            __OM uint32_t INT_MASK_MASTER : 32; /*!< [31..0] INT_MASK_MASTER                                                   */
+        } DDR_MEMC_DENALI_CTL_327_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_328;     /*!< (@ 0x00000520) DDR_MEMC_DENALI_CTL_328                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_TIMEOUT : 32; /*!< [31..0] INT_STATUS_TIMEOUT                                                */
+        } DDR_MEMC_DENALI_CTL_328_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_329; /*!< (@ 0x00000524) DDR_MEMC_DENALI_CTL_329                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_ECC : 32; /*!< [31..0] INT_STATUS_ECC                                                    */
+        } DDR_MEMC_DENALI_CTL_329_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_330;      /*!< (@ 0x00000528) DDR_MEMC_DENALI_CTL_330                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_LOWPOWER : 16; /*!< [15..0] INT_STATUS_LOWPOWER                                               */
+            uint32_t                          : 16;
+        } DDR_MEMC_DENALI_CTL_330_b;
+    };
+    __IM uint32_t RESERVED15;
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_332;      /*!< (@ 0x00000530) DDR_MEMC_DENALI_CTL_332                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_TRAINING : 32; /*!< [31..0] INT_STATUS_TRAINING                                               */
+        } DDR_MEMC_DENALI_CTL_332_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_333;    /*!< (@ 0x00000534) DDR_MEMC_DENALI_CTL_333                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_USERIF : 32; /*!< [31..0] INT_STATUS_USERIF                                                 */
+        } DDR_MEMC_DENALI_CTL_333_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_334;  /*!< (@ 0x00000538) DDR_MEMC_DENALI_CTL_334                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_MISC : 16; /*!< [15..0] INT_STATUS_MISC                                                   */
+            __IM uint32_t INT_STATUS_BIST : 8;  /*!< [23..16] INT_STATUS_BIST                                                  */
+            uint32_t                      : 8;
+        } DDR_MEMC_DENALI_CTL_334_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_335; /*!< (@ 0x0000053C) DDR_MEMC_DENALI_CTL_335                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_DFI  : 8; /*!< [7..0] INT_STATUS_DFI                                                     */
+            uint32_t                      : 16;
+            __IM uint32_t INT_STATUS_INIT : 8; /*!< [31..24] INT_STATUS_INIT                                                  */
+        } DDR_MEMC_DENALI_CTL_335_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_336; /*!< (@ 0x00000540) DDR_MEMC_DENALI_CTL_336                                    */
+
+        struct
+        {
+            __IM uint32_t INT_STATUS_MODE : 8; /*!< [7..0] INT_STATUS_MODE                                                    */
+            uint32_t                      : 24;
+        } DDR_MEMC_DENALI_CTL_336_b;
+    };
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_337;  /*!< (@ 0x00000544) DDR_MEMC_DENALI_CTL_337                                    */
+
+        struct
+        {
+            __OM uint32_t INT_ACK_TIMEOUT : 32; /*!< [31..0] INT_ACK_TIMEOUT                                                   */
+        } DDR_MEMC_DENALI_CTL_337_b;
+    };
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_338; /*!< (@ 0x00000548) DDR_MEMC_DENALI_CTL_338                                    */
+
+        struct
+        {
+            __OM uint32_t INT_ACK_ECC : 32;    /*!< [31..0] INT_ACK_ECC                                                       */
+        } DDR_MEMC_DENALI_CTL_338_b;
+    };
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_339;   /*!< (@ 0x0000054C) DDR_MEMC_DENALI_CTL_339                                    */
+
+        struct
+        {
+            __OM uint32_t INT_ACK_LOWPOWER : 16; /*!< [15..0] INT_ACK_LOWPOWER                                                  */
+            uint32_t                       : 16;
+        } DDR_MEMC_DENALI_CTL_339_b;
+    };
+    __IM uint32_t RESERVED16;
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_341;   /*!< (@ 0x00000554) DDR_MEMC_DENALI_CTL_341                                    */
+
+        struct
+        {
+            __OM uint32_t INT_ACK_TRAINING : 32; /*!< [31..0] INT_ACK_TRAINING                                                  */
+        } DDR_MEMC_DENALI_CTL_341_b;
+    };
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_342; /*!< (@ 0x00000558) DDR_MEMC_DENALI_CTL_342                                    */
+
+        struct
+        {
+            __OM uint32_t INT_ACK_USERIF : 32; /*!< [31..0] INT_ACK_USERIF                                                    */
+        } DDR_MEMC_DENALI_CTL_342_b;
+    };
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_343; /*!< (@ 0x0000055C) DDR_MEMC_DENALI_CTL_343                                    */
+
+        struct
+        {
+            __OM uint32_t INT_ACK_MISC : 16;   /*!< [15..0] INT_ACK_MISC                                                      */
+            __OM uint32_t INT_ACK_BIST : 8;    /*!< [23..16] INT_ACK_BIST                                                     */
+            uint32_t                   : 8;
+        } DDR_MEMC_DENALI_CTL_343_b;
+    };
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_344; /*!< (@ 0x00000560) DDR_MEMC_DENALI_CTL_344                                    */
+
+        struct
+        {
+            __OM uint32_t INT_ACK_DFI  : 8;    /*!< [7..0] INT_ACK_DFI                                                        */
+            uint32_t                   : 16;
+            __OM uint32_t INT_ACK_INIT : 8;    /*!< [31..24] INT_ACK_INIT                                                     */
+        } DDR_MEMC_DENALI_CTL_344_b;
+    };
+
+    union
+    {
+        __OM uint32_t DDR_MEMC_DENALI_CTL_345; /*!< (@ 0x00000564) DDR_MEMC_DENALI_CTL_345                                    */
+
+        struct
+        {
+            __OM uint32_t INT_ACK_MODE : 8;    /*!< [7..0] INT_ACK_MODE                                                       */
+            uint32_t                   : 24;
+        } DDR_MEMC_DENALI_CTL_345_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_346;   /*!< (@ 0x00000568) DDR_MEMC_DENALI_CTL_346                                    */
+
+        struct
+        {
+            __IOM uint32_t INT_MASK_TIMEOUT : 32; /*!< [31..0] INT_MASK_TIMEOUT                                                  */
+        } DDR_MEMC_DENALI_CTL_346_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_347; /*!< (@ 0x0000056C) DDR_MEMC_DENALI_CTL_347                                    */
+
+        struct
+        {
+            __IOM uint32_t INT_MASK_ECC : 32;   /*!< [31..0] INT_MASK_ECC                                                      */
+        } DDR_MEMC_DENALI_CTL_347_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_348;    /*!< (@ 0x00000570) DDR_MEMC_DENALI_CTL_348                                    */
+
+        struct
+        {
+            __IOM uint32_t INT_MASK_LOWPOWER : 16; /*!< [15..0] INT_MASK_LOWPOWER                                                 */
+            uint32_t                         : 16;
+        } DDR_MEMC_DENALI_CTL_348_b;
+    };
+    __IM uint32_t RESERVED17;
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_350;    /*!< (@ 0x00000578) DDR_MEMC_DENALI_CTL_350                                    */
+
+        struct
+        {
+            __IOM uint32_t INT_MASK_TRAINING : 32; /*!< [31..0] INT_MASK_TRAINING                                                 */
+        } DDR_MEMC_DENALI_CTL_350_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_351;  /*!< (@ 0x0000057C) DDR_MEMC_DENALI_CTL_351                                    */
+
+        struct
+        {
+            __IOM uint32_t INT_MASK_USERIF : 32; /*!< [31..0] INT_MASK_USERIF                                                   */
+        } DDR_MEMC_DENALI_CTL_351_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_352; /*!< (@ 0x00000580) DDR_MEMC_DENALI_CTL_352                                    */
+
+        struct
+        {
+            __IOM uint32_t INT_MASK_MISC : 16;  /*!< [15..0] INT_MASK_MISC                                                     */
+            __IOM uint32_t INT_MASK_BIST : 8;   /*!< [23..16] INT_MASK_BIST                                                    */
+            uint32_t                     : 8;
+        } DDR_MEMC_DENALI_CTL_352_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_353; /*!< (@ 0x00000584) DDR_MEMC_DENALI_CTL_353                                    */
+
+        struct
+        {
+            __IOM uint32_t INT_MASK_DFI  : 8;   /*!< [7..0] INT_MASK_DFI                                                       */
+            uint32_t                     : 16;
+            __IOM uint32_t INT_MASK_INIT : 8;   /*!< [31..24] INT_MASK_INIT                                                    */
+        } DDR_MEMC_DENALI_CTL_353_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_354; /*!< (@ 0x00000588) DDR_MEMC_DENALI_CTL_354                                    */
+
+        struct
+        {
+            __IOM uint32_t INT_MASK_MODE : 8;   /*!< [7..0] INT_MASK_MODE                                                      */
+            uint32_t                     : 24;
+        } DDR_MEMC_DENALI_CTL_354_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_355;    /*!< (@ 0x0000058C) DDR_MEMC_DENALI_CTL_355                                    */
+
+        struct
+        {
+            __IM uint32_t OUT_OF_RANGE_ADDR : 32; /*!< [31..0] OUT_OF_RANGE_ADDR                                                 */
+        } DDR_MEMC_DENALI_CTL_355_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_356;      /*!< (@ 0x00000590) DDR_MEMC_DENALI_CTL_356                                    */
+
+        struct
+        {
+            __IM uint32_t OUT_OF_RANGE_ADDR32 : 1;  /*!< [0..0] OUT_OF_RANGE_ADDR32                                                */
+            uint32_t                          : 7;
+            __IM uint32_t OUT_OF_RANGE_LENGTH : 13; /*!< [20..8] OUT_OF_RANGE_LENGTH                                               */
+            uint32_t                          : 3;
+            __IM uint32_t OUT_OF_RANGE_TYPE0  : 1;  /*!< [24..24] OUT_OF_RANGE_TYPE0                                               */
+            __IM uint32_t OUT_OF_RANGE_TYPE1  : 1;  /*!< [25..25] OUT_OF_RANGE_TYPE1                                               */
+            __IM uint32_t OUT_OF_RANGE_TYPE2  : 1;  /*!< [26..26] OUT_OF_RANGE_TYPE2                                               */
+            __IM uint32_t OUT_OF_RANGE_TYPE3  : 1;  /*!< [27..27] OUT_OF_RANGE_TYPE3                                               */
+            __IM uint32_t OUT_OF_RANGE_TYPE4  : 1;  /*!< [28..28] OUT_OF_RANGE_TYPE4                                               */
+            __IM uint32_t OUT_OF_RANGE_TYPE5  : 1;  /*!< [29..29] OUT_OF_RANGE_TYPE5                                               */
+            uint32_t                          : 2;
+        } DDR_MEMC_DENALI_CTL_356_b;
+    };
+    __IM uint32_t RESERVED18[11];
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_368;      /*!< (@ 0x000005C0) DDR_MEMC_DENALI_CTL_368                                    */
+
+        struct
+        {
+            __IM uint32_t PORT_CMD_ERROR_ADDR : 32; /*!< [31..0] PORT_CMD_ERROR_ADDR                                               */
+        } DDR_MEMC_DENALI_CTL_368_b;
+    };
+
+    union
+    {
+        __IM uint32_t DDR_MEMC_DENALI_CTL_369;       /*!< (@ 0x000005C4) DDR_MEMC_DENALI_CTL_369                                    */
+
+        struct
+        {
+            __IM uint32_t PORT_CMD_ERROR_ADDR32 : 1; /*!< [0..0] PORT_CMD_ERROR_ADDR32                                              */
+            uint32_t                            : 25;
+            __IM uint32_t PORT_CMD_ERROR_TYPE   : 1; /*!< [26..26] PORT_CMD_ERROR_TYPE                                              */
+            uint32_t                            : 5;
+        } DDR_MEMC_DENALI_CTL_369_b;
+    };
+    __IM uint32_t RESERVED19[6];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_376; /*!< (@ 0x000005E0) DDR_MEMC_DENALI_CTL_376                                    */
+
+        struct
+        {
+            uint32_t                         : 16;
+            __IOM uint32_t R2R_DIFFCS_DLY_F0 : 5; /*!< [20..16] R2R_DIFFCS_DLY_F0                                                */
+            uint32_t                         : 3;
+            __IOM uint32_t R2W_DIFFCS_DLY_F0 : 5; /*!< [28..24] R2W_DIFFCS_DLY_F0                                                */
+            uint32_t                         : 3;
+        } DDR_MEMC_DENALI_CTL_376_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_377;   /*!< (@ 0x000005E4) DDR_MEMC_DENALI_CTL_377                                    */
+
+        struct
+        {
+            __IOM uint32_t W2R_DIFFCS_DLY_F0 : 5; /*!< [4..0] W2R_DIFFCS_DLY_F0                                                  */
+            uint32_t                         : 3;
+            __IOM uint32_t W2W_DIFFCS_DLY_F0 : 5; /*!< [12..8] W2W_DIFFCS_DLY_F0                                                 */
+            uint32_t                         : 19;
+        } DDR_MEMC_DENALI_CTL_377_b;
+    };
+    __IM uint32_t RESERVED20[4];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_382; /*!< (@ 0x000005F8) DDR_MEMC_DENALI_CTL_382                                    */
+
+        struct
+        {
+            uint32_t                                       : 24;
+            __IOM uint32_t axi0_fixed_port_priority_enable : 1; /*!< [24..24] axi0_fixed_port_priority_enable                         */
+            uint32_t                                       : 7;
+        } DDR_MEMC_DENALI_CTL_382_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_383;                 /*!< (@ 0x000005FC) DDR_MEMC_DENALI_CTL_383                                    */
+
+        struct
+        {
+            __IOM uint32_t axi0_r_priority                 : 3; /*!< [2..0] axi0_r_priority                                                    */
+            uint32_t                                       : 5;
+            __IOM uint32_t axi0_w_priority                 : 3; /*!< [10..8] axi0_w_priority                                                   */
+            uint32_t                                       : 13;
+            __IOM uint32_t axi1_fixed_port_priority_enable : 1; /*!< [24..24] axi1_fixed_port_priority_enable                         */
+            uint32_t                                       : 7;
+        } DDR_MEMC_DENALI_CTL_383_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_384;                 /*!< (@ 0x00000600) DDR_MEMC_DENALI_CTL_384                                    */
+
+        struct
+        {
+            __IOM uint32_t axi1_r_priority                 : 3; /*!< [2..0] axi1_r_priority                                                    */
+            uint32_t                                       : 5;
+            __IOM uint32_t axi1_w_priority                 : 3; /*!< [10..8] axi1_w_priority                                                   */
+            uint32_t                                       : 13;
+            __IOM uint32_t axi2_fixed_port_priority_enable : 1; /*!< [24..24] axi2_fixed_port_priority_enable                         */
+            uint32_t                                       : 7;
+        } DDR_MEMC_DENALI_CTL_384_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_385;                 /*!< (@ 0x00000604) DDR_MEMC_DENALI_CTL_385                                    */
+
+        struct
+        {
+            __IOM uint32_t axi2_r_priority                 : 3; /*!< [2..0] axi2_r_priority                                                    */
+            uint32_t                                       : 5;
+            __IOM uint32_t axi2_w_priority                 : 3; /*!< [10..8] axi2_w_priority                                                   */
+            uint32_t                                       : 13;
+            __IOM uint32_t axi3_fixed_port_priority_enable : 1; /*!< [24..24] axi3_fixed_port_priority_enable                         */
+            uint32_t                                       : 7;
+        } DDR_MEMC_DENALI_CTL_385_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_386;                 /*!< (@ 0x00000608) DDR_MEMC_DENALI_CTL_386                                    */
+
+        struct
+        {
+            __IOM uint32_t axi3_r_priority                 : 3; /*!< [2..0] axi3_r_priority                                                    */
+            uint32_t                                       : 5;
+            __IOM uint32_t axi3_w_priority                 : 3; /*!< [10..8] axi3_w_priority                                                   */
+            uint32_t                                       : 13;
+            __IOM uint32_t axi4_fixed_port_priority_enable : 1; /*!< [24..24] axi4_fixed_port_priority_enable                         */
+            uint32_t                                       : 7;
+        } DDR_MEMC_DENALI_CTL_386_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_387; /*!< (@ 0x0000060C) DDR_MEMC_DENALI_CTL_387                                    */
+
+        struct
+        {
+            __IOM uint32_t axi4_r_priority : 3; /*!< [2..0] axi4_r_priority                                                    */
+            uint32_t                       : 5;
+            __IOM uint32_t axi4_w_priority : 3; /*!< [10..8] axi4_w_priority                                                   */
+            uint32_t                       : 21;
+        } DDR_MEMC_DENALI_CTL_387_b;
+    };
+    __IM uint32_t RESERVED21[7];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_395; /*!< (@ 0x0000062C) DDR_MEMC_DENALI_CTL_395                                    */
+
+        struct
+        {
+            uint32_t                                 : 16;
+            __IOM uint32_t PORT_ADDR_PROTECTION_EN   : 1; /*!< [16..16] PORT_ADDR_PROTECTION_EN                                         */
+            uint32_t                                 : 7;
+            __IOM uint32_t AXI0_ADDRESS_RANGE_ENABLE : 1; /*!< [24..24] AXI0_ADDRESS_RANGE_ENABLE                                     */
+            uint32_t                                 : 7;
+        } DDR_MEMC_DENALI_CTL_395_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_396;  /*!< (@ 0x00000630) DDR_MEMC_DENALI_CTL_396                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_396_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_397;       /*!< (@ 0x00000634) DDR_MEMC_DENALI_CTL_397                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_397_b;
+    };
+    __IM uint32_t RESERVED22[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_400;  /*!< (@ 0x00000640) DDR_MEMC_DENALI_CTL_400                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_400_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_401;       /*!< (@ 0x00000644) DDR_MEMC_DENALI_CTL_401                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_401_b;
+    };
+    __IM uint32_t RESERVED23[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_404;  /*!< (@ 0x00000650) DDR_MEMC_DENALI_CTL_404                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_404_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_405;       /*!< (@ 0x00000654) DDR_MEMC_DENALI_CTL_405                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_405_b;
+    };
+    __IM uint32_t RESERVED24[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_408;  /*!< (@ 0x00000660) DDR_MEMC_DENALI_CTL_408                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_408_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_409;       /*!< (@ 0x00000664) DDR_MEMC_DENALI_CTL_409                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_409_b;
+    };
+    __IM uint32_t RESERVED25[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_412;  /*!< (@ 0x00000670) DDR_MEMC_DENALI_CTL_412                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_412_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_413;       /*!< (@ 0x00000674) DDR_MEMC_DENALI_CTL_413                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_413_b;
+    };
+    __IM uint32_t RESERVED26[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_416;  /*!< (@ 0x00000680) DDR_MEMC_DENALI_CTL_416                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_416_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_417;       /*!< (@ 0x00000684) DDR_MEMC_DENALI_CTL_417                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_417_b;
+    };
+    __IM uint32_t RESERVED27[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_420;  /*!< (@ 0x00000690) DDR_MEMC_DENALI_CTL_420                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_420_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_421;       /*!< (@ 0x00000694) DDR_MEMC_DENALI_CTL_421                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_421_b;
+    };
+    __IM uint32_t RESERVED28[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_424;  /*!< (@ 0x000006A0) DDR_MEMC_DENALI_CTL_424                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_424_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_425;       /*!< (@ 0x000006A4) DDR_MEMC_DENALI_CTL_425                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_425_b;
+    };
+    __IM uint32_t RESERVED29[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_428;  /*!< (@ 0x000006B0) DDR_MEMC_DENALI_CTL_428                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_428_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_429;       /*!< (@ 0x000006B4) DDR_MEMC_DENALI_CTL_429                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_429_b;
+    };
+    __IM uint32_t RESERVED30[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_432;  /*!< (@ 0x000006C0) DDR_MEMC_DENALI_CTL_432                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_432_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_433;       /*!< (@ 0x000006C4) DDR_MEMC_DENALI_CTL_433                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_433_b;
+    };
+    __IM uint32_t RESERVED31[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_436;  /*!< (@ 0x000006D0) DDR_MEMC_DENALI_CTL_436                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_436_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_437;       /*!< (@ 0x000006D4) DDR_MEMC_DENALI_CTL_437                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_437_b;
+    };
+    __IM uint32_t RESERVED32[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_440;  /*!< (@ 0x000006E0) DDR_MEMC_DENALI_CTL_440                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_440_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_441;       /*!< (@ 0x000006E4) DDR_MEMC_DENALI_CTL_441                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_441_b;
+    };
+    __IM uint32_t RESERVED33[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_444;  /*!< (@ 0x000006F0) DDR_MEMC_DENALI_CTL_444                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_444_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_445;       /*!< (@ 0x000006F4) DDR_MEMC_DENALI_CTL_445                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_445_b;
+    };
+    __IM uint32_t RESERVED34[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_448;  /*!< (@ 0x00000700) DDR_MEMC_DENALI_CTL_448                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_448_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_449;       /*!< (@ 0x00000704) DDR_MEMC_DENALI_CTL_449                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_449_b;
+    };
+    __IM uint32_t RESERVED35[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_452;  /*!< (@ 0x00000710) DDR_MEMC_DENALI_CTL_452                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_452_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_453;       /*!< (@ 0x00000714) DDR_MEMC_DENALI_CTL_453                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_453_b;
+    };
+    __IM uint32_t RESERVED36[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_456;  /*!< (@ 0x00000720) DDR_MEMC_DENALI_CTL_456                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_START_ADDR : 19; /*!< [18..0] AXI0_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_456_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_457;       /*!< (@ 0x00000724) DDR_MEMC_DENALI_CTL_457                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI0_END_ADDR        : 19; /*!< [18..0] AXI0_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI0_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI0_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_457_b;
+    };
+    __IM uint32_t RESERVED37[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_460;            /*!< (@ 0x00000730) DDR_MEMC_DENALI_CTL_460                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_ADDRESS_RANGE_ENABLE : 1;  /*!< [0..0] AXI1_ADDRESS_RANGE_ENABLE                                       */
+            uint32_t                                 : 7;
+            __IOM uint32_t AXI1_START_ADDR           : 19; /*!< [26..8] AXI1_START_ADDR                                                   */
+            uint32_t                                 : 5;
+        } DDR_MEMC_DENALI_CTL_460_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_461;       /*!< (@ 0x00000734) DDR_MEMC_DENALI_CTL_461                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_461_b;
+    };
+    __IM uint32_t RESERVED38[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_464;  /*!< (@ 0x00000740) DDR_MEMC_DENALI_CTL_464                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_464_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_465;       /*!< (@ 0x00000744) DDR_MEMC_DENALI_CTL_465                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_465_b;
+    };
+    __IM uint32_t RESERVED39[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_468;  /*!< (@ 0x00000750) DDR_MEMC_DENALI_CTL_468                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_468_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_469;       /*!< (@ 0x00000754) DDR_MEMC_DENALI_CTL_469                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_469_b;
+    };
+    __IM uint32_t RESERVED40[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_472;  /*!< (@ 0x00000760) DDR_MEMC_DENALI_CTL_472                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_472_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_473;       /*!< (@ 0x00000764) DDR_MEMC_DENALI_CTL_473                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_473_b;
+    };
+    __IM uint32_t RESERVED41[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_476;  /*!< (@ 0x00000770) DDR_MEMC_DENALI_CTL_476                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_476_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_477;       /*!< (@ 0x00000774) DDR_MEMC_DENALI_CTL_477                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_477_b;
+    };
+    __IM uint32_t RESERVED42[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_480;  /*!< (@ 0x00000780) DDR_MEMC_DENALI_CTL_480                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_480_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_481;       /*!< (@ 0x00000784) DDR_MEMC_DENALI_CTL_481                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_481_b;
+    };
+    __IM uint32_t RESERVED43[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_484;  /*!< (@ 0x00000790) DDR_MEMC_DENALI_CTL_484                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_484_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_485;       /*!< (@ 0x00000794) DDR_MEMC_DENALI_CTL_485                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_485_b;
+    };
+    __IM uint32_t RESERVED44[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_488;  /*!< (@ 0x000007A0) DDR_MEMC_DENALI_CTL_488                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_488_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_489;       /*!< (@ 0x000007A4) DDR_MEMC_DENALI_CTL_489                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_489_b;
+    };
+    __IM uint32_t RESERVED45[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_492;  /*!< (@ 0x000007B0) DDR_MEMC_DENALI_CTL_492                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_492_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_493;       /*!< (@ 0x000007B4) DDR_MEMC_DENALI_CTL_493                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_493_b;
+    };
+    __IM uint32_t RESERVED46[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_496;  /*!< (@ 0x000007C0) DDR_MEMC_DENALI_CTL_496                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_496_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_497;       /*!< (@ 0x000007C4) DDR_MEMC_DENALI_CTL_497                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_497_b;
+    };
+    __IM uint32_t RESERVED47[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_500;  /*!< (@ 0x000007D0) DDR_MEMC_DENALI_CTL_500                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_500_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_501;       /*!< (@ 0x000007D4) DDR_MEMC_DENALI_CTL_501                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_501_b;
+    };
+    __IM uint32_t RESERVED48[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_504;  /*!< (@ 0x000007E0) DDR_MEMC_DENALI_CTL_504                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_504_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_505;       /*!< (@ 0x000007E4) DDR_MEMC_DENALI_CTL_505                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_505_b;
+    };
+    __IM uint32_t RESERVED49[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_508;  /*!< (@ 0x000007F0) DDR_MEMC_DENALI_CTL_508                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_508_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_509;       /*!< (@ 0x000007F4) DDR_MEMC_DENALI_CTL_509                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_509_b;
+    };
+    __IM uint32_t RESERVED50[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_512;  /*!< (@ 0x00000800) DDR_MEMC_DENALI_CTL_512                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_512_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_513;       /*!< (@ 0x00000804) DDR_MEMC_DENALI_CTL_513                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_513_b;
+    };
+    __IM uint32_t RESERVED51[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_516;  /*!< (@ 0x00000810) DDR_MEMC_DENALI_CTL_516                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_516_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_517;       /*!< (@ 0x00000814) DDR_MEMC_DENALI_CTL_517                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_517_b;
+    };
+    __IM uint32_t RESERVED52[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_520;  /*!< (@ 0x00000820) DDR_MEMC_DENALI_CTL_520                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_START_ADDR : 19; /*!< [18..0] AXI1_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_520_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_521;       /*!< (@ 0x00000824) DDR_MEMC_DENALI_CTL_521                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI1_END_ADDR        : 19; /*!< [18..0] AXI1_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI1_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI1_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_521_b;
+    };
+    __IM uint32_t RESERVED53[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_524;            /*!< (@ 0x00000830) DDR_MEMC_DENALI_CTL_524                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_ADDRESS_RANGE_ENABLE : 1;  /*!< [0..0] AXI2_ADDRESS_RANGE_ENABLE                                       */
+            uint32_t                                 : 7;
+            __IOM uint32_t AXI2_START_ADDR           : 19; /*!< [26..8] AXI2_START_ADDR                                                   */
+            uint32_t                                 : 5;
+        } DDR_MEMC_DENALI_CTL_524_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_525;       /*!< (@ 0x00000834) DDR_MEMC_DENALI_CTL_525                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_525_b;
+    };
+    __IM uint32_t RESERVED54[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_528;  /*!< (@ 0x00000840) DDR_MEMC_DENALI_CTL_528                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_528_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_529;       /*!< (@ 0x00000844) DDR_MEMC_DENALI_CTL_529                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_529_b;
+    };
+    __IM uint32_t RESERVED55[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_532;  /*!< (@ 0x00000850) DDR_MEMC_DENALI_CTL_532                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_532_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_533;       /*!< (@ 0x00000854) DDR_MEMC_DENALI_CTL_533                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_533_b;
+    };
+    __IM uint32_t RESERVED56[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_536;  /*!< (@ 0x00000860) DDR_MEMC_DENALI_CTL_536                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_536_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_537;       /*!< (@ 0x00000864) DDR_MEMC_DENALI_CTL_537                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_537_b;
+    };
+    __IM uint32_t RESERVED57[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_540;  /*!< (@ 0x00000870) DDR_MEMC_DENALI_CTL_540                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_540_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_541;       /*!< (@ 0x00000874) DDR_MEMC_DENALI_CTL_541                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_541_b;
+    };
+    __IM uint32_t RESERVED58[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_544;  /*!< (@ 0x00000880) DDR_MEMC_DENALI_CTL_544                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_544_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_545;       /*!< (@ 0x00000884) DDR_MEMC_DENALI_CTL_545                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_545_b;
+    };
+    __IM uint32_t RESERVED59[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_548;  /*!< (@ 0x00000890) DDR_MEMC_DENALI_CTL_548                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_548_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_549;       /*!< (@ 0x00000894) DDR_MEMC_DENALI_CTL_549                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_549_b;
+    };
+    __IM uint32_t RESERVED60[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_552;  /*!< (@ 0x000008A0) DDR_MEMC_DENALI_CTL_552                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_552_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_553;       /*!< (@ 0x000008A4) DDR_MEMC_DENALI_CTL_553                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_553_b;
+    };
+    __IM uint32_t RESERVED61[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_556;  /*!< (@ 0x000008B0) DDR_MEMC_DENALI_CTL_556                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_556_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_557;       /*!< (@ 0x000008B4) DDR_MEMC_DENALI_CTL_557                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_557_b;
+    };
+    __IM uint32_t RESERVED62[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_560;  /*!< (@ 0x000008C0) DDR_MEMC_DENALI_CTL_560                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_560_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_561;       /*!< (@ 0x000008C4) DDR_MEMC_DENALI_CTL_561                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_561_b;
+    };
+    __IM uint32_t RESERVED63[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_564;  /*!< (@ 0x000008D0) DDR_MEMC_DENALI_CTL_564                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_564_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_565;       /*!< (@ 0x000008D4) DDR_MEMC_DENALI_CTL_565                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_565_b;
+    };
+    __IM uint32_t RESERVED64[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_568;  /*!< (@ 0x000008E0) DDR_MEMC_DENALI_CTL_568                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_568_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_569;       /*!< (@ 0x000008E4) DDR_MEMC_DENALI_CTL_569                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_569_b;
+    };
+    __IM uint32_t RESERVED65[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_572;  /*!< (@ 0x000008F0) DDR_MEMC_DENALI_CTL_572                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_572_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_573;       /*!< (@ 0x000008F4) DDR_MEMC_DENALI_CTL_573                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_573_b;
+    };
+    __IM uint32_t RESERVED66[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_576;  /*!< (@ 0x00000900) DDR_MEMC_DENALI_CTL_576                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_576_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_577;       /*!< (@ 0x00000904) DDR_MEMC_DENALI_CTL_577                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_577_b;
+    };
+    __IM uint32_t RESERVED67[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_580;  /*!< (@ 0x00000910) DDR_MEMC_DENALI_CTL_580                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_580_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_581;       /*!< (@ 0x00000914) DDR_MEMC_DENALI_CTL_581                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_581_b;
+    };
+    __IM uint32_t RESERVED68[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_584;  /*!< (@ 0x00000920) DDR_MEMC_DENALI_CTL_584                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_START_ADDR : 19; /*!< [18..0] AXI2_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_584_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_585;       /*!< (@ 0x00000924) DDR_MEMC_DENALI_CTL_585                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI2_END_ADDR        : 19; /*!< [18..0] AXI2_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI2_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI2_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_585_b;
+    };
+    __IM uint32_t RESERVED69[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_588;            /*!< (@ 0x00000930) DDR_MEMC_DENALI_CTL_588                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_ADDRESS_RANGE_ENABLE : 1;  /*!< [0..0] AXI3_ADDRESS_RANGE_ENABLE                                       */
+            uint32_t                                 : 7;
+            __IOM uint32_t AXI3_START_ADDR           : 19; /*!< [26..8] AXI3_START_ADDR                                                   */
+            uint32_t                                 : 5;
+        } DDR_MEMC_DENALI_CTL_588_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_589;       /*!< (@ 0x00000934) DDR_MEMC_DENALI_CTL_589                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_589_b;
+    };
+    __IM uint32_t RESERVED70[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_592;  /*!< (@ 0x00000940) DDR_MEMC_DENALI_CTL_592                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_592_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_593;       /*!< (@ 0x00000944) DDR_MEMC_DENALI_CTL_593                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_593_b;
+    };
+    __IM uint32_t RESERVED71[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_596;  /*!< (@ 0x00000950) DDR_MEMC_DENALI_CTL_596                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_596_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_597;       /*!< (@ 0x00000954) DDR_MEMC_DENALI_CTL_597                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_597_b;
+    };
+    __IM uint32_t RESERVED72[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_600;  /*!< (@ 0x00000960) DDR_MEMC_DENALI_CTL_600                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_600_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_601;       /*!< (@ 0x00000964) DDR_MEMC_DENALI_CTL_601                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_601_b;
+    };
+    __IM uint32_t RESERVED73[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_604;  /*!< (@ 0x00000970) DDR_MEMC_DENALI_CTL_604                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_604_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_605;       /*!< (@ 0x00000974) DDR_MEMC_DENALI_CTL_605                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_605_b;
+    };
+    __IM uint32_t RESERVED74[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_608;  /*!< (@ 0x00000980) DDR_MEMC_DENALI_CTL_608                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_608_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_609;       /*!< (@ 0x00000984) DDR_MEMC_DENALI_CTL_609                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_609_b;
+    };
+    __IM uint32_t RESERVED75[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_612;  /*!< (@ 0x00000990) DDR_MEMC_DENALI_CTL_612                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_612_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_613;       /*!< (@ 0x00000994) DDR_MEMC_DENALI_CTL_613                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_613_b;
+    };
+    __IM uint32_t RESERVED76[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_616;  /*!< (@ 0x000009A0) DDR_MEMC_DENALI_CTL_616                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_616_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_617;       /*!< (@ 0x000009A4) DDR_MEMC_DENALI_CTL_617                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_617_b;
+    };
+    __IM uint32_t RESERVED77[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_620;  /*!< (@ 0x000009B0) DDR_MEMC_DENALI_CTL_620                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_620_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_621;       /*!< (@ 0x000009B4) DDR_MEMC_DENALI_CTL_621                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_621_b;
+    };
+    __IM uint32_t RESERVED78[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_624;  /*!< (@ 0x000009C0) DDR_MEMC_DENALI_CTL_624                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_624_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_625;       /*!< (@ 0x000009C4) DDR_MEMC_DENALI_CTL_625                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_625_b;
+    };
+    __IM uint32_t RESERVED79[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_628;  /*!< (@ 0x000009D0) DDR_MEMC_DENALI_CTL_628                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_628_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_629;       /*!< (@ 0x000009D4) DDR_MEMC_DENALI_CTL_629                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_629_b;
+    };
+    __IM uint32_t RESERVED80[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_632;  /*!< (@ 0x000009E0) DDR_MEMC_DENALI_CTL_632                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_632_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_633;       /*!< (@ 0x000009E4) DDR_MEMC_DENALI_CTL_633                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_633_b;
+    };
+    __IM uint32_t RESERVED81[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_636;  /*!< (@ 0x000009F0) DDR_MEMC_DENALI_CTL_636                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_636_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_637;       /*!< (@ 0x000009F4) DDR_MEMC_DENALI_CTL_637                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_637_b;
+    };
+    __IM uint32_t RESERVED82[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_640;  /*!< (@ 0x00000A00) DDR_MEMC_DENALI_CTL_640                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_640_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_641;       /*!< (@ 0x00000A04) DDR_MEMC_DENALI_CTL_641                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_641_b;
+    };
+    __IM uint32_t RESERVED83[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_644;  /*!< (@ 0x00000A10) DDR_MEMC_DENALI_CTL_644                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_644_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_645;       /*!< (@ 0x00000A14) DDR_MEMC_DENALI_CTL_645                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_645_b;
+    };
+    __IM uint32_t RESERVED84[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_648;  /*!< (@ 0x00000A20) DDR_MEMC_DENALI_CTL_648                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_START_ADDR : 19; /*!< [18..0] AXI3_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_648_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_649;       /*!< (@ 0x00000A24) DDR_MEMC_DENALI_CTL_649                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI3_END_ADDR        : 19; /*!< [18..0] AXI3_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI3_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI3_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_649_b;
+    };
+    __IM uint32_t RESERVED85[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_652;            /*!< (@ 0x00000A30) DDR_MEMC_DENALI_CTL_652                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_ADDRESS_RANGE_ENABLE : 1;  /*!< [0..0] AXI4_ADDRESS_RANGE_ENABLE                                       */
+            uint32_t                                 : 7;
+            __IOM uint32_t AXI4_START_ADDR           : 19; /*!< [26..8] AXI4_START_ADDR                                                   */
+            uint32_t                                 : 5;
+        } DDR_MEMC_DENALI_CTL_652_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_653;       /*!< (@ 0x00000A34) DDR_MEMC_DENALI_CTL_653                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_653_b;
+    };
+    __IM uint32_t RESERVED86[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_656;  /*!< (@ 0x00000A40) DDR_MEMC_DENALI_CTL_656                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_656_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_657;       /*!< (@ 0x00000A44) DDR_MEMC_DENALI_CTL_657                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_657_b;
+    };
+    __IM uint32_t RESERVED87[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_660;  /*!< (@ 0x00000A50) DDR_MEMC_DENALI_CTL_660                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_660_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_661;       /*!< (@ 0x00000A54) DDR_MEMC_DENALI_CTL_661                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_661_b;
+    };
+    __IM uint32_t RESERVED88[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_664;  /*!< (@ 0x00000A60) DDR_MEMC_DENALI_CTL_664                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_664_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_665;       /*!< (@ 0x00000A64) DDR_MEMC_DENALI_CTL_665                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_665_b;
+    };
+    __IM uint32_t RESERVED89[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_668;  /*!< (@ 0x00000A70) DDR_MEMC_DENALI_CTL_668                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_668_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_669;       /*!< (@ 0x00000A74) DDR_MEMC_DENALI_CTL_669                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_669_b;
+    };
+    __IM uint32_t RESERVED90[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_672;  /*!< (@ 0x00000A80) DDR_MEMC_DENALI_CTL_672                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_672_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_673;       /*!< (@ 0x00000A84) DDR_MEMC_DENALI_CTL_673                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_673_b;
+    };
+    __IM uint32_t RESERVED91[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_676;  /*!< (@ 0x00000A90) DDR_MEMC_DENALI_CTL_676                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_676_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_677;       /*!< (@ 0x00000A94) DDR_MEMC_DENALI_CTL_677                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_677_b;
+    };
+    __IM uint32_t RESERVED92[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_680;  /*!< (@ 0x00000AA0) DDR_MEMC_DENALI_CTL_680                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_680_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_681;       /*!< (@ 0x00000AA4) DDR_MEMC_DENALI_CTL_681                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_681_b;
+    };
+    __IM uint32_t RESERVED93[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_684;  /*!< (@ 0x00000AB0) DDR_MEMC_DENALI_CTL_684                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_684_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_685;       /*!< (@ 0x00000AB4) DDR_MEMC_DENALI_CTL_685                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_685_b;
+    };
+    __IM uint32_t RESERVED94[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_688;  /*!< (@ 0x00000AC0) DDR_MEMC_DENALI_CTL_688                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_688_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_689;       /*!< (@ 0x00000AC4) DDR_MEMC_DENALI_CTL_689                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_689_b;
+    };
+    __IM uint32_t RESERVED95[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_692;  /*!< (@ 0x00000AD0) DDR_MEMC_DENALI_CTL_692                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_692_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_693;       /*!< (@ 0x00000AD4) DDR_MEMC_DENALI_CTL_693                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_693_b;
+    };
+    __IM uint32_t RESERVED96[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_696;  /*!< (@ 0x00000AE0) DDR_MEMC_DENALI_CTL_696                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_696_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_697;       /*!< (@ 0x00000AE4) DDR_MEMC_DENALI_CTL_697                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_697_b;
+    };
+    __IM uint32_t RESERVED97[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_700;  /*!< (@ 0x00000AF0) DDR_MEMC_DENALI_CTL_700                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_700_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_701;       /*!< (@ 0x00000AF4) DDR_MEMC_DENALI_CTL_701                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_701_b;
+    };
+    __IM uint32_t RESERVED98[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_704;  /*!< (@ 0x00000B00) DDR_MEMC_DENALI_CTL_704                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_704_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_705;       /*!< (@ 0x00000B04) DDR_MEMC_DENALI_CTL_705                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_705_b;
+    };
+    __IM uint32_t RESERVED99[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_708;  /*!< (@ 0x00000B10) DDR_MEMC_DENALI_CTL_708                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_708_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_709;       /*!< (@ 0x00000B14) DDR_MEMC_DENALI_CTL_709                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_709_b;
+    };
+    __IM uint32_t RESERVED100[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_712;  /*!< (@ 0x00000B20) DDR_MEMC_DENALI_CTL_712                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_START_ADDR : 19; /*!< [18..0] AXI4_START_ADDR                                                   */
+            uint32_t                       : 13;
+        } DDR_MEMC_DENALI_CTL_712_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_713;       /*!< (@ 0x00000B24) DDR_MEMC_DENALI_CTL_713                                    */
+
+        struct
+        {
+            __IOM uint32_t AXI4_END_ADDR        : 19; /*!< [18..0] AXI4_END_ADDR                                                     */
+            uint32_t                            : 5;
+            __IOM uint32_t AXI4_RANGE_PROT_BITS : 2;  /*!< [25..24] AXI4_RANGE_PROT_BITS                                             */
+            uint32_t                            : 6;
+        } DDR_MEMC_DENALI_CTL_713_b;
+    };
+    __IM uint32_t RESERVED101[2];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_716;                      /*!< (@ 0x00000B30) DDR_MEMC_DENALI_CTL_716                                    */
+
+        struct
+        {
+            __IOM uint32_t weighted_round_robin_latency_control : 1; /*!< [0..0] weighted_round_robin_latency_control                 */
+            uint32_t                                            : 7;
+            __IOM uint32_t weighted_round_robin_weight_sharing  : 2; /*!< [9..8] weighted_round_robin_weight_sharing                   */
+            uint32_t                                            : 6;
+            __IM uint32_t wrr_param_value_err                   : 4; /*!< [19..16] wrr_param_value_err                                              */
+            uint32_t                                            : 4;
+            __IOM uint32_t axi0_priority0_relative_priority     : 4; /*!< [27..24] axi0_priority0_relative_priority                       */
+            uint32_t                                            : 4;
+        } DDR_MEMC_DENALI_CTL_716_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_717;                  /*!< (@ 0x00000B34) DDR_MEMC_DENALI_CTL_717                                    */
+
+        struct
+        {
+            __IOM uint32_t axi0_priority1_relative_priority : 4; /*!< [3..0] axi0_priority1_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi0_priority2_relative_priority : 4; /*!< [11..8] axi0_priority2_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi0_priority3_relative_priority : 4; /*!< [19..16] axi0_priority3_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi0_priority4_relative_priority : 4; /*!< [27..24] axi0_priority4_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_717_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_718;                  /*!< (@ 0x00000B38) DDR_MEMC_DENALI_CTL_718                                    */
+
+        struct
+        {
+            __IOM uint32_t axi0_priority5_relative_priority : 4; /*!< [3..0] axi0_priority5_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi0_priority6_relative_priority : 4; /*!< [11..8] axi0_priority6_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi0_priority7_relative_priority : 4; /*!< [19..16] axi0_priority7_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi0_port_ordering               : 3; /*!< [26..24] axi0_port_ordering                                               */
+            uint32_t                                        : 5;
+        } DDR_MEMC_DENALI_CTL_718_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_719;                   /*!< (@ 0x00000B3C) DDR_MEMC_DENALI_CTL_719                                    */
+
+        struct
+        {
+            __IOM uint32_t axi0_priority_relax              : 10; /*!< [9..0] axi0_priority_relax                                                */
+            uint32_t                                        : 6;
+            __IOM uint32_t axi1_priority0_relative_priority : 4;  /*!< [19..16] axi1_priority0_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi1_priority1_relative_priority : 4;  /*!< [27..24] axi1_priority1_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_719_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_720;                  /*!< (@ 0x00000B40) DDR_MEMC_DENALI_CTL_720                                    */
+
+        struct
+        {
+            __IOM uint32_t axi1_priority2_relative_priority : 4; /*!< [3..0] axi1_priority2_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi1_priority3_relative_priority : 4; /*!< [11..8] axi1_priority3_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi1_priority4_relative_priority : 4; /*!< [19..16] axi1_priority4_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi1_priority5_relative_priority : 4; /*!< [27..24] axi1_priority5_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_720_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_721;                  /*!< (@ 0x00000B44) DDR_MEMC_DENALI_CTL_721                                    */
+
+        struct
+        {
+            __IOM uint32_t axi1_priority6_relative_priority : 4; /*!< [3..0] axi1_priority6_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi1_priority7_relative_priority : 4; /*!< [11..8] axi1_priority7_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi1_port_ordering               : 3; /*!< [18..16] axi1_port_ordering                                               */
+            uint32_t                                        : 13;
+        } DDR_MEMC_DENALI_CTL_721_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_722;                   /*!< (@ 0x00000B48) DDR_MEMC_DENALI_CTL_722                                    */
+
+        struct
+        {
+            __IOM uint32_t axi1_priority_relax              : 10; /*!< [9..0] axi1_priority_relax                                                */
+            uint32_t                                        : 6;
+            __IOM uint32_t axi2_priority0_relative_priority : 4;  /*!< [19..16] axi2_priority0_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi2_priority1_relative_priority : 4;  /*!< [27..24] axi2_priority1_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_722_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_723;                  /*!< (@ 0x00000B4C) DDR_MEMC_DENALI_CTL_723                                    */
+
+        struct
+        {
+            __IOM uint32_t axi2_priority2_relative_priority : 4; /*!< [3..0] axi2_priority2_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi2_priority3_relative_priority : 4; /*!< [11..8] axi2_priority3_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi2_priority4_relative_priority : 4; /*!< [19..16] axi2_priority4_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi2_priority5_relative_priority : 4; /*!< [27..24] axi2_priority5_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_723_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_724;                  /*!< (@ 0x00000B50) DDR_MEMC_DENALI_CTL_724                                    */
+
+        struct
+        {
+            __IOM uint32_t axi2_priority6_relative_priority : 4; /*!< [3..0] axi2_priority6_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi2_priority7_relative_priority : 4; /*!< [11..8] axi2_priority7_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi2_port_ordering               : 3; /*!< [18..16] axi2_port_ordering                                               */
+            uint32_t                                        : 13;
+        } DDR_MEMC_DENALI_CTL_724_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_725;                   /*!< (@ 0x00000B54) DDR_MEMC_DENALI_CTL_725                                    */
+
+        struct
+        {
+            __IOM uint32_t axi2_priority_relax              : 10; /*!< [9..0] axi2_priority_relax                                                */
+            uint32_t                                        : 6;
+            __IOM uint32_t axi3_priority0_relative_priority : 4;  /*!< [19..16] axi3_priority0_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi3_priority1_relative_priority : 4;  /*!< [27..24] axi3_priority1_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_725_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_726;                  /*!< (@ 0x00000B58) DDR_MEMC_DENALI_CTL_726                                    */
+
+        struct
+        {
+            __IOM uint32_t axi3_priority2_relative_priority : 4; /*!< [3..0] axi3_priority2_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi3_priority3_relative_priority : 4; /*!< [11..8] axi3_priority3_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi3_priority4_relative_priority : 4; /*!< [19..16] axi3_priority4_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi3_priority5_relative_priority : 4; /*!< [27..24] axi3_priority5_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_726_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_727;                  /*!< (@ 0x00000B5C) DDR_MEMC_DENALI_CTL_727                                    */
+
+        struct
+        {
+            __IOM uint32_t axi3_priority6_relative_priority : 4; /*!< [3..0] axi3_priority6_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi3_priority7_relative_priority : 4; /*!< [11..8] axi3_priority7_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi3_port_ordering               : 3; /*!< [18..16] axi3_port_ordering                                               */
+            uint32_t                                        : 13;
+        } DDR_MEMC_DENALI_CTL_727_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_728;                   /*!< (@ 0x00000B60) DDR_MEMC_DENALI_CTL_728                                    */
+
+        struct
+        {
+            __IOM uint32_t axi3_priority_relax              : 10; /*!< [9..0] axi3_priority_relax                                                */
+            uint32_t                                        : 6;
+            __IOM uint32_t axi4_priority0_relative_priority : 4;  /*!< [19..16] axi4_priority0_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi4_priority1_relative_priority : 4;  /*!< [27..24] axi4_priority1_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_728_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_729;                  /*!< (@ 0x00000B64) DDR_MEMC_DENALI_CTL_729                                    */
+
+        struct
+        {
+            __IOM uint32_t axi4_priority2_relative_priority : 4; /*!< [3..0] axi4_priority2_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi4_priority3_relative_priority : 4; /*!< [11..8] axi4_priority3_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi4_priority4_relative_priority : 4; /*!< [19..16] axi4_priority4_relative_priority                       */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi4_priority5_relative_priority : 4; /*!< [27..24] axi4_priority5_relative_priority                       */
+            uint32_t                                        : 4;
+        } DDR_MEMC_DENALI_CTL_729_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_730;                  /*!< (@ 0x00000B68) DDR_MEMC_DENALI_CTL_730                                    */
+
+        struct
+        {
+            __IOM uint32_t axi4_priority6_relative_priority : 4; /*!< [3..0] axi4_priority6_relative_priority                         */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi4_priority7_relative_priority : 4; /*!< [11..8] axi4_priority7_relative_priority                        */
+            uint32_t                                        : 4;
+            __IOM uint32_t axi4_port_ordering               : 3; /*!< [18..16] axi4_port_ordering                                               */
+            uint32_t                                        : 13;
+        } DDR_MEMC_DENALI_CTL_730_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_731;      /*!< (@ 0x00000B6C) DDR_MEMC_DENALI_CTL_731                                    */
+
+        struct
+        {
+            __IOM uint32_t axi4_priority_relax : 10; /*!< [9..0] axi4_priority_relax                                                */
+            uint32_t                           : 22;
+        } DDR_MEMC_DENALI_CTL_731_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_732;   /*!< (@ 0x00000B70) DDR_MEMC_DENALI_CTL_732                                    */
+
+        struct
+        {
+            __IOM uint32_t TDFI_PHY_RDLAT_F0 : 7; /*!< [6..0] TDFI_PHY_RDLAT_F0                                                  */
+            uint32_t                         : 25;
+        } DDR_MEMC_DENALI_CTL_732_b;
+    };
+    __IM uint32_t RESERVED102[28];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_DENALI_CTL_761; /*!< (@ 0x00000BE4) DDR_MEMC_DENALI_CTL_761                                    */
+
+        struct
+        {
+            uint32_t                   : 8;
+            __IOM uint32_t TDFI_WRDATA : 8; /*!< [15..8] TDFI_WRDATA                                                       */
+            uint32_t                   : 16;
+        } DDR_MEMC_DENALI_CTL_761_b;
+    };
+    __IM uint32_t RESERVED103[1286];
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_MCAR_CTL;         /*!< (@ 0x00002000) DDR_MEMC_MCAR_CTL                                          */
+
+        struct
+        {
+            __IOM uint32_t block_fm_norm_req : 1; /*!< [0..0] block_fm_norm_req                                                  */
+            uint32_t                         : 7;
+            __OM uint32_t set_axctl          : 1; /*!< [8..8] set_axctl                                                          */
+            uint32_t                         : 7;
+            __IOM uint32_t dfi_init_start    : 1; /*!< [16..16] dfi_init_start                                                   */
+            uint32_t                         : 15;
+        } DDR_MEMC_MCAR_CTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_MCAR_MON;         /*!< (@ 0x00002004) DDR_MEMC_MCAR_MON                                          */
+
+        struct
+        {
+            __IM uint32_t port_busy          : 5; /*!< [4..0] port_busy                                                          */
+            uint32_t                         : 11;
+            __IM uint32_t q_almost_full      : 1; /*!< [16..16] q_almost_full                                                    */
+            __IM uint32_t refresh_in_process : 1; /*!< [17..17] refresh_in_process                                               */
+            uint32_t                         : 14;
+        } DDR_MEMC_MCAR_MON_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DDR_MEMC_MCAR_AXCTL[5]; /*!< (@ 0x00002008) [0..4]                                                     */
+
+        struct
+        {
+            uint32_t                    : 8;
+            __IOM uint32_t axi0_awcobuf : 1; /*!< [8..8] axi0_awcobuf                                                       */
+            uint32_t                    : 23;
+        } DDR_MEMC_MCAR_AXCTL_b[5];
+    };
+} R_DDRSS_Type;                              /*!< Size = 8220 (0x201c)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT10_0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief General PWM Timer 10 (R_GPT10_0)
+ */
+
+typedef struct                         /*!< (@ 0x81000000) R_GPT10_0 Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
+
+        struct
+        {
+            __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disabled                                            */
+            __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disabled                                     */
+            __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disabled                                     */
+            __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disabled                                      */
+            __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
+            uint32_t             : 3;
+            __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
+            uint32_t             : 16;
+        } GTWP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTR;          /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
+
+        struct
+        {
+            __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel 0 Count Start                                              */
+            __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel 1 Count Start                                              */
+            __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel 2 Count Start                                              */
+            __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel 3 Count Start                                              */
+            __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel 4 Count Start                                              */
+            __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel 5 Count Start                                              */
+            __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel 6 Count Start                                              */
+            uint32_t              : 25;
+        } GTSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTP;          /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
+
+        struct
+        {
+            __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel 0 Count Stop                                               */
+            __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel 1 Count Stop                                               */
+            __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel 2 Count Stop                                               */
+            __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel 3 Count Stop                                               */
+            __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel 4 Count Stop                                               */
+            __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel 5 Count Stop                                               */
+            __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel 6 Count Stop                                               */
+            uint32_t              : 25;
+        } GTSTP_b;
+    };
+
+    union
+    {
+        __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
+
+        struct
+        {
+            __OM uint32_t CCLR0 : 1;   /*!< [0..0] Channel 0 Count Clear                                              */
+            __OM uint32_t CCLR1 : 1;   /*!< [1..1] Channel 1 Count Clear                                              */
+            __OM uint32_t CCLR2 : 1;   /*!< [2..2] Channel 2 Count Clear                                              */
+            __OM uint32_t CCLR3 : 1;   /*!< [3..3] Channel 3 Count Clear                                              */
+            __OM uint32_t CCLR4 : 1;   /*!< [4..4] Channel 4 Count Clear                                              */
+            __OM uint32_t CCLR5 : 1;   /*!< [5..5] Channel 5 Count Clear                                              */
+            __OM uint32_t CCLR6 : 1;   /*!< [6..6] Channel 6 Count Clear                                              */
+            uint32_t            : 25;
+        } GTCLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSSR;             /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t SSGTRGAFR : 2; /*!< [1..0] SSGTRGAFR                                                          */
+            __IOM uint32_t SSGTRGBFR : 2; /*!< [3..2] SSGTRGBFR                                                          */
+            __IOM uint32_t SSGTRGCFR : 2; /*!< [5..4] SSGTRGCFR                                                          */
+            __IOM uint32_t SSGTRGDFR : 2; /*!< [7..6] SSGTRGDFR                                                          */
+            __IOM uint32_t SSCARBHL  : 2; /*!< [9..8] SSCARBHL                                                           */
+            __IOM uint32_t SSCAFBHL  : 2; /*!< [11..10] SSCAFBHL                                                         */
+            __IOM uint32_t SSCBRAHL  : 2; /*!< [13..12] SSCBRAHL                                                         */
+            __IOM uint32_t SSCBFAHL  : 2; /*!< [15..14] SSCBFAHL                                                         */
+            __IOM uint32_t SSELCA    : 1; /*!< [16..16] SSELCA                                                           */
+            __IOM uint32_t SSELCB    : 1; /*!< [17..17] SSELCB                                                           */
+            __IOM uint32_t SSELCC    : 1; /*!< [18..18] SSELCC                                                           */
+            __IOM uint32_t SSELCD    : 1; /*!< [19..19] SSELCD                                                           */
+            __IOM uint32_t SSELCE    : 1; /*!< [20..20] SSELCE                                                           */
+            __IOM uint32_t SSELCF    : 1; /*!< [21..21] SSELCF                                                           */
+            __IOM uint32_t SSELCG    : 1; /*!< [22..22] SSELCG                                                           */
+            __IOM uint32_t SSELCH    : 1; /*!< [23..23] SSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CSTRT     : 1; /*!< [31..31] Software Source Count Start Enable                               */
+        } GTSSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPSR;             /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
+
+        struct
+        {
+            __IOM uint32_t PSGTRGAFR : 2; /*!< [1..0] PSGTRGAFR                                                          */
+            __IOM uint32_t PSGTRGBFR : 2; /*!< [3..2] PSGTRGBFR                                                          */
+            __IOM uint32_t PSGTRGCFR : 2; /*!< [5..4] PSGTRGCFR                                                          */
+            __IOM uint32_t PSGTRGDFR : 2; /*!< [7..6] PSGTRGDFR                                                          */
+            __IOM uint32_t PSCARBHL  : 2; /*!< [9..8] PSCARBHL                                                           */
+            __IOM uint32_t PSCAFBHL  : 2; /*!< [11..10] PSCAFBHL                                                         */
+            __IOM uint32_t PSCBRAHL  : 2; /*!< [13..12] PSCBRAHL                                                         */
+            __IOM uint32_t PSCBFAHL  : 2; /*!< [15..14] PSCBFAHL                                                         */
+            __IOM uint32_t PSELCA    : 1; /*!< [16..16] PSELCA                                                           */
+            __IOM uint32_t PSELCB    : 1; /*!< [17..17] PSELCB                                                           */
+            __IOM uint32_t PSELCC    : 1; /*!< [18..18] PSELCC                                                           */
+            __IOM uint32_t PSELCD    : 1; /*!< [19..19] PSELCD                                                           */
+            __IOM uint32_t PSELCE    : 1; /*!< [20..20] PSELCE                                                           */
+            __IOM uint32_t PSELCF    : 1; /*!< [21..21] PSELCF                                                           */
+            __IOM uint32_t PSELCG    : 1; /*!< [22..22] PSELCG                                                           */
+            __IOM uint32_t PSELCH    : 1; /*!< [23..23] PSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CSTOP     : 1; /*!< [31..31] CSTOP                                                            */
+        } GTPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCSR;             /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t CSGTRGAFR : 2; /*!< [1..0] CSGTRGAFR                                                          */
+            __IOM uint32_t CSGTRGBFR : 2; /*!< [3..2] CSGTRGBFR                                                          */
+            __IOM uint32_t CSGTRGCFR : 2; /*!< [5..4] CSGTRGCFR                                                          */
+            __IOM uint32_t CSGTRGDFR : 2; /*!< [7..6] CSGTRGDFR                                                          */
+            __IOM uint32_t CSCARBHL  : 2; /*!< [9..8] CSCARBHL                                                           */
+            __IOM uint32_t CSCAFBHL  : 2; /*!< [11..10] CSCAFBHL                                                         */
+            __IOM uint32_t CSCBRAHL  : 2; /*!< [13..12] CSCBRAHL                                                         */
+            __IOM uint32_t CSCBFAHL  : 2; /*!< [15..14] CSCBFAHL                                                         */
+            __IOM uint32_t CSELCA    : 1; /*!< [16..16] CSELCA                                                           */
+            __IOM uint32_t CSELCB    : 1; /*!< [17..17] CSELCB                                                           */
+            __IOM uint32_t CSELCC    : 1; /*!< [18..18] CSELCC                                                           */
+            __IOM uint32_t CSELCD    : 1; /*!< [19..19] CSELCD                                                           */
+            __IOM uint32_t CSELCE    : 1; /*!< [20..20] CSELCE                                                           */
+            __IOM uint32_t CSELCF    : 1; /*!< [21..21] CSELCF                                                           */
+            __IOM uint32_t CSELCG    : 1; /*!< [22..22] CSELCG                                                           */
+            __IOM uint32_t CSELCH    : 1; /*!< [23..23] CSELCH                                                           */
+            uint32_t                 : 7;
+            __IOM uint32_t CCLR      : 1; /*!< [31..31] CCLR                                                             */
+        } GTCSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUPSR;            /*!< (@ 0x0000001C) General PWM Timer Count-Up Source Select Register          */
+
+        struct
+        {
+            __IOM uint32_t USGTRGAFR : 2; /*!< [1..0] USGTRGAFR                                                          */
+            __IOM uint32_t USGTRGBFR : 2; /*!< [3..2] USGTRGBFR                                                          */
+            __IOM uint32_t USGTRGCFR : 2; /*!< [5..4] USGTRGCFR                                                          */
+            __IOM uint32_t USGTRGDFR : 2; /*!< [7..6] USGTRGDFR                                                          */
+            __IOM uint32_t USCARBHL  : 2; /*!< [9..8] USCARBHL                                                           */
+            __IOM uint32_t USCAFBHL  : 2; /*!< [11..10] USCAFBHL                                                         */
+            __IOM uint32_t USCBRAHL  : 2; /*!< [13..12] USCBRAHL                                                         */
+            __IOM uint32_t USCBFAHL  : 2; /*!< [15..14] USCBFAHL                                                         */
+            __IOM uint32_t USELCA    : 1; /*!< [16..16] USELCA                                                           */
+            __IOM uint32_t USELCB    : 1; /*!< [17..17] USELCB                                                           */
+            __IOM uint32_t USELCC    : 1; /*!< [18..18] USELCC                                                           */
+            __IOM uint32_t USELCD    : 1; /*!< [19..19] USELCD                                                           */
+            __IOM uint32_t USELCE    : 1; /*!< [20..20] USELCE                                                           */
+            __IOM uint32_t USELCF    : 1; /*!< [21..21] USELCF                                                           */
+            __IOM uint32_t USELCG    : 1; /*!< [22..22] USELCG                                                           */
+            __IOM uint32_t USELCH    : 1; /*!< [23..23] USELCH                                                           */
+            uint32_t                 : 8;
+        } GTUPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDNSR;            /*!< (@ 0x00000020) General PWM Timer Count-Down Source Select Register        */
+
+        struct
+        {
+            __IOM uint32_t DSGTRGAFR : 2; /*!< [1..0] DSGTRGAFR                                                          */
+            __IOM uint32_t DSGTRGBFR : 2; /*!< [3..2] DSGTRGBFR                                                          */
+            __IOM uint32_t DSGTRGCFR : 2; /*!< [5..4] DSGTRGCFR                                                          */
+            __IOM uint32_t DSGTRGDFR : 2; /*!< [7..6] DSGTRGDFR                                                          */
+            __IOM uint32_t DSCARBHL  : 2; /*!< [9..8] DSCARBHL                                                           */
+            __IOM uint32_t DSCAFBHL  : 2; /*!< [11..10] DSCAFBHL                                                         */
+            __IOM uint32_t DSCBRAHL  : 2; /*!< [13..12] DSCBRAHL                                                         */
+            __IOM uint32_t DSCBFAHL  : 2; /*!< [15..14] DSCBFAHL                                                         */
+            __IOM uint32_t DSELCA    : 1; /*!< [16..16] DSELCA                                                           */
+            __IOM uint32_t DSELCB    : 1; /*!< [17..17] DSELCB                                                           */
+            __IOM uint32_t DSELCC    : 1; /*!< [18..18] DSELCC                                                           */
+            __IOM uint32_t DSELCD    : 1; /*!< [19..19] DSELCD                                                           */
+            __IOM uint32_t DSELCE    : 1; /*!< [20..20] DSELCE                                                           */
+            __IOM uint32_t DSELCF    : 1; /*!< [21..21] DSELCF                                                           */
+            __IOM uint32_t DSELCG    : 1; /*!< [22..22] DSELCG                                                           */
+            __IOM uint32_t DSELCH    : 1; /*!< [23..23] DSELCH                                                           */
+            uint32_t                 : 8;
+        } GTDNSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICASR;           /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
+                                           *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t ASGTRGAFR : 2; /*!< [1..0] ASGTRGAFR                                                          */
+            __IOM uint32_t ASGTRGBFR : 2; /*!< [3..2] ASGTRGBFR                                                          */
+            __IOM uint32_t ASGTRGCFR : 2; /*!< [5..4] ASGTRGCFR                                                          */
+            __IOM uint32_t ASGTRGDFR : 2; /*!< [7..6] ASGTRGDFR                                                          */
+            __IOM uint32_t ASCARBHL  : 2; /*!< [9..8] ASCARBHL                                                           */
+            __IOM uint32_t ASCAFBHL  : 2; /*!< [11..10] ASCAFBHL                                                         */
+            __IOM uint32_t ASCBRAHL  : 2; /*!< [13..12] ASCBRAHL                                                         */
+            __IOM uint32_t ASCBFAHL  : 2; /*!< [15..14] ASCBFAHL                                                         */
+            __IOM uint32_t ASELCA    : 1; /*!< [16..16] ASELCA                                                           */
+            __IOM uint32_t ASELCB    : 1; /*!< [17..17] ASELCB                                                           */
+            __IOM uint32_t ASELCC    : 1; /*!< [18..18] ASELCC                                                           */
+            __IOM uint32_t ASELCD    : 1; /*!< [19..19] ASELCD                                                           */
+            __IOM uint32_t ASELCE    : 1; /*!< [20..20] ASELCE                                                           */
+            __IOM uint32_t ASELCF    : 1; /*!< [21..21] ASELCF                                                           */
+            __IOM uint32_t ASELCG    : 1; /*!< [22..22] ASELCG                                                           */
+            __IOM uint32_t ASELCH    : 1; /*!< [23..23] ASELCH                                                           */
+            uint32_t                 : 8;
+        } GTICASR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICBSR;           /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
+                                           *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t BSGTRGAFR : 2; /*!< [1..0] BSGTRGAFR                                                          */
+            __IOM uint32_t BSGTRGBFR : 2; /*!< [3..2] BSGTRGBFR                                                          */
+            __IOM uint32_t BSGTRGCFR : 2; /*!< [5..4] BSGTRGCFR                                                          */
+            __IOM uint32_t BSGTRGDFR : 2; /*!< [7..6] BSGTRGDFR                                                          */
+            __IOM uint32_t BSCARBHL  : 2; /*!< [9..8] BSCARBHL                                                           */
+            __IOM uint32_t BSCAFBHL  : 2; /*!< [11..10] BSCAFBHL                                                         */
+            __IOM uint32_t BSCBRAHL  : 2; /*!< [13..12] BSCBRAHL                                                         */
+            __IOM uint32_t BSCBFAHL  : 2; /*!< [15..14] BSCBFAHL                                                         */
+            __IOM uint32_t BSELCA    : 1; /*!< [16..16] BSELCA                                                           */
+            __IOM uint32_t BSELCB    : 1; /*!< [17..17] BSELCB                                                           */
+            __IOM uint32_t BSELCC    : 1; /*!< [18..18] BSELCC                                                           */
+            __IOM uint32_t BSELCD    : 1; /*!< [19..19] BSELCD                                                           */
+            __IOM uint32_t BSELCE    : 1; /*!< [20..20] BSELCE                                                           */
+            __IOM uint32_t BSELCF    : 1; /*!< [21..21] BSELCF                                                           */
+            __IOM uint32_t BSELCG    : 1; /*!< [22..22] BSELCG                                                           */
+            __IOM uint32_t BSELCH    : 1; /*!< [23..23] BSELCH                                                           */
+            uint32_t                 : 8;
+        } GTICBSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
+            uint32_t            : 7;
+            __IOM uint32_t ICDS : 1;   /*!< [8..8] Input Capture Operation Select at Count Stop                       */
+            uint32_t            : 7;
+            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
+            uint32_t            : 4;
+            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
+            uint32_t            : 2;
+            __IOM uint32_t SWMD : 3;   /*!< [31..29] Switch Mode Select                                               */
+        } GTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUDDTYC;        /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t UD     : 1;  /*!< [0..0] Count Direction Setting                                            */
+            __IOM uint32_t UDF    : 1;  /*!< [1..1] Forcible Count Direction Setting                                   */
+            uint32_t              : 14;
+            __IOM uint32_t OADTY  : 2;  /*!< [17..16] GTIOCm_nA Pin Output Duty Setting                                */
+            __IOM uint32_t OADTYF : 1;  /*!< [18..18] GTIOCm_nA Pin Output Duty Forced Setting                         */
+            __IOM uint32_t OADTYR : 1;  /*!< [19..19] Output after Release of GTIOCm_nA Pin Output 0%/100%
+                                         *   Duty Cycle Settings                                                       */
+            uint32_t              : 4;
+            __IOM uint32_t OBDTY  : 2;  /*!< [25..24] GTIOCm_nB Pin Output Duty Setting                                */
+            __IOM uint32_t OBDTYF : 1;  /*!< [26..26] GTIOCm_nB Pin Output Duty Forced Setting                         */
+            __IOM uint32_t OBDTYR : 1;  /*!< [27..27] Output after Release of GTIOCm_nB Pin Output 0%/100%
+                                         *   Duty Cycle Settings                                                       */
+            __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTUDDTYC.OADTY[1:0] and GTUDDTYC.OBDTY[1:0] reflect
+                                         *   timing setting in the triangle-wave mode                                  */
+            uint32_t : 3;
+        } GTUDDTYC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCm_nA Pin Function Select                                      */
+            uint32_t              : 1;
+            __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCm_nA Pin Output Value Setting at the Count Stop               */
+            __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCm_nA Pin Output Retention at the Start/Stop Count             */
+            __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCm_nA Pin Output Enable                                        */
+            __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCm_nA Pin Negate Value Setting                                */
+            uint32_t              : 2;
+            __IOM uint32_t NFAEN  : 1; /*!< [13..13] GTIOCm_nA Pin Input Noise Filter Enable                          */
+            __IOM uint32_t NFCSA  : 2; /*!< [15..14] GTIOCm_nA Pin Input Noise Filter Sampling Clock Select           */
+            __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCm_nB Pin Function Select                                    */
+            uint32_t              : 1;
+            __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCm_nB Pin Output Value Setting at the Count Stop             */
+            __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCm_nB Pin Output Retention at the Start/Stop Count           */
+            __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCm_nB Pin Output Enable                                      */
+            __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCm_nB Pin Negate Value Setting                               */
+            uint32_t              : 2;
+            __IOM uint32_t NFBEN  : 1; /*!< [29..29] GTIOCm_nB Pin Input Noise Filter Enable                          */
+            __IOM uint32_t NFCSB  : 2; /*!< [31..30] GTIOCm_nB Pin Input Noise Filter Sampling Clock Select           */
+        } GTIOR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTINTAD;          /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
+
+        struct
+        {
+            __IOM uint32_t GTINTA   : 1; /*!< [0..0] GTINTA                                                             */
+            __IOM uint32_t GTINTB   : 1; /*!< [1..1] GTINTB                                                             */
+            __IOM uint32_t GTINTC   : 1; /*!< [2..2] GTINTC                                                             */
+            __IOM uint32_t GTINTD   : 1; /*!< [3..3] GTINTD                                                             */
+            __IOM uint32_t GTINTE   : 1; /*!< [4..4] GTINTE                                                             */
+            __IOM uint32_t GTINTF   : 1; /*!< [5..5] GTINTF                                                             */
+            __IOM uint32_t GTINTPR  : 2; /*!< [7..6] GTINTPR                                                            */
+            uint32_t                : 8;
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] ADTRAUEN                                                         */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] ADTRADEN                                                         */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] ADTRBUEN                                                         */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] ADTRBDEN                                                         */
+            uint32_t                : 4;
+            __IOM uint32_t GRP      : 2; /*!< [25..24] Select the group to detect disabling of output (dead-time
+                                          *   error or simultaneous driving of outputs to the high or
+                                          *   low level) to POEG and to request of disabling of output
+                                          *   from POEG.                                                                */
+            uint32_t              : 2;
+            __IOM uint32_t GRPDTE : 1;   /*!< [28..28] GRPDTE                                                           */
+            __IOM uint32_t GRPABH : 1;   /*!< [29..29] (GTIOCm_nA pin and GTIOCm_nB output)                             */
+            __IOM uint32_t GRPABL : 1;   /*!< [30..30] (GTIOCm_nA pin and GTIOCm_nB output)                             */
+            uint32_t              : 1;
+        } GTINTAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTST;           /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IM uint32_t ITCNT    : 3; /*!< [10..8] GPTm_n_OVF/GPTm_n_UDF Interrupt Skipping Count Counter            */
+            uint32_t               : 4;
+            __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
+            __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Register Compare Match (Up-Counting) A/D Converter
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Register Compare Match (Down-Counting) A/D
+                                         *   Converter Start Request Flag                                              */
+            __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Register Compare Match (Up-Counting) A/D Converter
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Register Compare Match (Down-Counting) A/D
+                                         *   Converter Start Request Flag                                              */
+            uint32_t            : 4;
+            __IM uint32_t ODF   : 1;    /*!< [24..24] Output Stop Request Flag                                         */
+            uint32_t            : 3;
+            __IM uint32_t DTEF  : 1;    /*!< [28..28] Dead Time Error Flag                                             */
+            __IM uint32_t OABHF : 1;    /*!< [29..29] Simultaneous High Output Flag                                    */
+            __IM uint32_t OABLF : 1;    /*!< [30..30] Simultaneous Low Output Flag                                     */
+            uint32_t            : 1;
+        } GTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+
+        struct
+        {
+            __IOM uint32_t BD0     : 1; /*!< [0..0] GTCCRA/GTCCRB Registers Buffer Operation Disable                   */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] GTPR Register Buffer Operation Disable                             */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] GTADTRA/GTADTRB Registers Buffer Operation Disable                 */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] GTDVU/GTDVD Registers Buffer Operation Disable                     */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRA Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRB Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Register Buffer Operation                                 */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Register Buffer Operation                                 */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Register Buffer Operation                                   */
+            __IOM uint32_t CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Registers Forcible Buffer Operation            */
+            uint32_t               : 1;
+            __IOM uint32_t ADTTA   : 2; /*!< [25..24] GTADTRA Register Buffer Transfer Timing Select                   */
+            __IOM uint32_t ADTDA   : 1; /*!< [26..26] GTADTRA Register Double Buffer Operation                         */
+            uint32_t               : 1;
+            __IOM uint32_t ADTTB   : 2; /*!< [29..28] GTADTRB Register Buffer Transfer Timing Select                   */
+            __IOM uint32_t ADTDB   : 1; /*!< [30..30] GTADTRB Register Double Buffer Operation                         */
+            uint32_t               : 1;
+        } GTBER_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
+                                        *                  Start Request Skipping Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t ITLA  : 1;  /*!< [0..0] ITLA                                                               */
+            __IOM uint32_t ITLB  : 1;  /*!< [1..1] ITLB                                                               */
+            __IOM uint32_t ITLC  : 1;  /*!< [2..2] ITLC                                                               */
+            __IOM uint32_t ITLD  : 1;  /*!< [3..3] ITLD                                                               */
+            __IOM uint32_t ITLE  : 1;  /*!< [4..4] ITLE                                                               */
+            __IOM uint32_t ITLF  : 1;  /*!< [5..5] ITLF                                                               */
+            __IOM uint32_t IVTC  : 2;  /*!< [7..6] IVTC                                                               */
+            __IOM uint32_t IVTT  : 3;  /*!< [10..8] IVTT                                                              */
+            uint32_t             : 1;
+            __IOM uint32_t ADTAL : 1;  /*!< [12..12] ADTAL                                                            */
+            uint32_t             : 1;
+            __IOM uint32_t ADTBL : 1;  /*!< [14..14] ADTBL                                                            */
+            uint32_t             : 17;
+        } GTITC_b;
+    };
+    __IOM uint32_t GTCNT;              /*!< (@ 0x00000048) General PWM Timer Counter                                  */
+    __IOM uint32_t GTCCR[6];           /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register m
+                                        *                  (m = A,B,C,E,D,F)                                          */
+    __IOM uint32_t GTPR;               /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
+    __IOM uint32_t GTPBR;              /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
+    __IOM uint32_t GTPDBR;             /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
+                                        *                  Register                                                   */
+    __IM uint32_t RESERVED[6];
+
+    union
+    {
+        __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
+
+        struct
+        {
+            __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
+            uint32_t             : 3;
+            __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Register Buffer Operation Enable                             */
+            __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Register Buffer Operation Enable                             */
+            uint32_t             : 2;
+            __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Register Setting                                             */
+            uint32_t             : 23;
+        } GTDTCR_b;
+    };
+    __IOM uint32_t GTDVU;              /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U
+                                        *                  (m = U, D)                                                 */
+    __IOM uint32_t GTDVD;              /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D
+                                        *                  (m = U, D)                                                 */
+    __IOM uint32_t GTDBU;              /*!< (@ 0x00000094) General PWM Timer Dead Time Value Buffer Register
+                                        *                  U (m = U, D)                                               */
+    __IOM uint32_t GTDBD;              /*!< (@ 0x00000098) General PWM Timer Dead Time Value Buffer Register
+                                        *                  D (m = U, D)                                               */
+
+    union
+    {
+        __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
+                                        *                  Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
+            uint32_t          : 30;
+        } GTSOS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
+                                        *                  Temporary Release Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
+            uint32_t            : 31;
+        } GTSOTR_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   Select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match / Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA A/D Converter Start Request Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB A/D Converter Start Request Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
+    __IM uint32_t RESERVED2[6];
+
+    union
+    {
+        __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
+                                         *                  Control Channel Select Register                            */
+
+        struct
+        {
+            __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            uint32_t : 25;
+        } GTSECSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
+            __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
+            __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
+            __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 20;
+        } GTSECR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSWSR;          /*!< (@ 0x000000D8) General PWM Timer Switch Source Select Register            */
+
+        struct
+        {
+            __IOM uint32_t WSGTRGA : 2; /*!< [1..0] GTETRGA Signal Edge Select to Switch Counter (GTETRGSA
+                                         *   Signal for SAFTY)                                                         */
+            __IOM uint32_t WSGTRGB : 2; /*!< [3..2] GTETRGB Signal Edge Select to Switch Counter (GTETRGSB
+                                         *   Signal for SAFTY)                                                         */
+            __IOM uint32_t WSGTRGC : 2; /*!< [5..4] GTETRGC Signal Edge Select to Switch Counter (GTIOC10_0A
+                                         *   output Signal for SAFTY)                                                  */
+            __IOM uint32_t WSGTRGD : 2; /*!< [7..6] GTETRGD Signal Edge Select to Switch Counter (GTIOC10_1A
+                                         *   output Signal for SAFTY)                                                  */
+            uint32_t              : 8;
+            __IOM uint32_t WSELCA : 1;  /*!< [16..16] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCB : 1;  /*!< [17..17] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCC : 1;  /*!< [18..18] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCD : 1;  /*!< [19..19] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCE : 1;  /*!< [20..20] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCF : 1;  /*!< [21..21] Event Source Counter Switch Enable                               */
+            __IOM uint32_t WSELCG : 1;  /*!< [22..22] Event Source Counter Switch Enable                               */
+            __IOM uint32_t CSELCH : 1;  /*!< [23..23] Event Source Counter Switch Enable                               */
+            uint32_t              : 8;
+        } GTSWSR_b;
+    };
+    __IOM uint32_t GTSWOS;              /*!< (@ 0x000000DC) General PWM Timer Switch Offset Setting Register           */
+} R_GPT10_0_Type;                       /*!< Size = 224 (0xe0)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Real Time Clock (R_RTC)
+ */
+
+typedef struct                         /*!< (@ 0x81009000) R_RTC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t RTCA0CTL0;      /*!< (@ 0x00000000) RTC Control Register 0                                     */
+
+        struct
+        {
+            uint32_t                 : 4;
+            __IOM uint32_t RTCA0SLSB : 1; /*!< [4..4] RTCA0SCMP enable/disable setting                                   */
+            __IOM uint32_t RTCA0AMPM : 1; /*!< [5..5] RTCA0HOUR, RTCA0ALH display format selection bit                   */
+            __IM uint32_t  RTCA0CEST : 1; /*!< [6..6] RTC Controller Enable Status                                       */
+            __IOM uint32_t RTCA0CE   : 1; /*!< [7..7] RTC Controller Enable Bit                                          */
+            uint32_t                 : 24;
+        } RTCA0CTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0CTL1;         /*!< (@ 0x00000004) RTC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint32_t RTCA0CT   : 3; /*!< [2..0] Fixed interval interrupt (RTC_PRD) output setting bit              */
+            __IOM uint32_t RTCA01SE  : 1; /*!< [3..3] 1 second interrupt (RTC_1S) output enable bit                      */
+            __IOM uint32_t RTCA0ALME : 1; /*!< [4..4] Alarm interrupt (RTC_ALM) output enable bit                        */
+            __IOM uint32_t RTCA01HZE : 1; /*!< [5..5] This bit enables/disables 1 Hz pulse output (RTCAT1HZ).            */
+            uint32_t                 : 26;
+        } RTCA0CTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0CTL2;         /*!< (@ 0x00000008) RTC Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint32_t RTCA0WAIT : 1; /*!< [0..0] RTC Controller Counter Wait Control                                */
+            __IM uint32_t  RTCA0WST  : 1; /*!< [1..1] RTC Controller Counter Wait Status                                 */
+            __IOM uint32_t RTCA0RSUB : 1; /*!< [2..2] RTCA0SUBC Data Transfer Control                                    */
+            __IM uint32_t  RTCA0RSST : 1; /*!< [3..3] RTCA0SRBU Transfer Status                                          */
+            __IM uint32_t  RTCA0WSST : 1; /*!< [4..4] RTCA0SCMP Write Status                                             */
+            uint32_t                 : 27;
+        } RTCA0CTL2_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0SUBC;          /*!< (@ 0x0000000C) RTC Sub Count Register                                     */
+
+        struct
+        {
+            __IM uint32_t RTCA0SUBC : 22; /*!< [21..0] Register that counts the 1 second reference time                  */
+            uint32_t                : 10;
+        } RTCA0SUBC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0SRBU;          /*!< (@ 0x00000010) RTC Sub Count Register Read Buffer                         */
+
+        struct
+        {
+            __IM uint32_t RTCA0SRBU : 22; /*!< [21..0] Read buffer register of RTCA0SUBC                                 */
+            uint32_t                : 10;
+        } RTCA0SRBU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0SEC;         /*!< (@ 0x00000014) RTC Sec Count Buffer Register                              */
+
+        struct
+        {
+            __IOM uint32_t RTCA0SEC : 7; /*!< [6..0] Buffer register to read/write RTC Second Count register
+                                          *   (RTCA0SECC).                                                              */
+            uint32_t : 25;
+        } RTCA0SEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0MIN;         /*!< (@ 0x00000018) RTC Min Count Buffer Register                              */
+
+        struct
+        {
+            __IOM uint32_t RTCA0MIN : 7; /*!< [6..0] Buffer register to read/write RTC Minute Count register
+                                          *   (RTCA0MINC).                                                              */
+            uint32_t : 25;
+        } RTCA0MIN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0HOUR;         /*!< (@ 0x0000001C) RTC Hour Count Buffer Register                             */
+
+        struct
+        {
+            __IOM uint32_t RTCA0HOUR : 6; /*!< [5..0] Buffer register to read/write RTC Hour Count register
+                                           *   (RTCA0HOURC).                                                             */
+            uint32_t : 26;
+        } RTCA0HOUR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0WEEK;         /*!< (@ 0x00000020) RTC Week Count Buffer Register                             */
+
+        struct
+        {
+            __IOM uint32_t RTCA0WEEK : 3; /*!< [2..0] Buffer register to read/write RTC Week Count register
+                                           *   (RTCA0WEEKC).                                                             */
+            uint32_t : 29;
+        } RTCA0WEEK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0DAY;         /*!< (@ 0x00000024) RTC Day Count Buffer Register                              */
+
+        struct
+        {
+            __IOM uint32_t RTCA0DAY : 6; /*!< [5..0] Buffer register to read/write RTC Day Count register
+                                          *   (RTCA0DAYC).                                                              */
+            uint32_t : 26;
+        } RTCA0DAY_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0MONTH;         /*!< (@ 0x00000028) RTC Month Count Buffer Register                            */
+
+        struct
+        {
+            __IOM uint32_t RTCA0MONTH : 5; /*!< [4..0] Buffer register to read/write RTC Month Count register
+                                            *   (RTCA0MONC).                                                              */
+            uint32_t : 27;
+        } RTCA0MONTH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0YEAR;         /*!< (@ 0x0000002C) RTC Year Count Buffer Register                             */
+
+        struct
+        {
+            __IOM uint32_t RTCA0YEAR : 8; /*!< [7..0] Buffer register to read/write RTC Year Count register
+                                           *   (RTCA0YEARC).                                                             */
+            uint32_t : 24;
+        } RTCA0YEAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0TIME;         /*!< (@ 0x00000030) RTC Time Set Register                                      */
+
+        struct
+        {
+            __IOM uint32_t RTCA0SEC  : 8; /*!< [7..0] See RTCA0SEC register                                              */
+            __IOM uint32_t RTCA0MIN  : 8; /*!< [15..8] See RTCA0MIN register                                             */
+            __IOM uint32_t RTCA0HOUR : 8; /*!< [23..16] See RTCA0HOUR register                                           */
+            uint32_t                 : 8;
+        } RTCA0TIME_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0CAL;           /*!< (@ 0x00000034) RTC Calendar Set Register                                  */
+
+        struct
+        {
+            __IOM uint32_t RTCA0WEEK  : 8; /*!< [7..0] See RTCA0WEEK register                                             */
+            __IOM uint32_t RTCA0DAY   : 8; /*!< [15..8] See RTCA0DAY register                                             */
+            __IOM uint32_t RTCA0MONTH : 8; /*!< [23..16] See RTCA0MONTH register                                          */
+            __IOM uint32_t RTCA0YEAR  : 8; /*!< [31..24] See RTCA0YEAR register                                           */
+        } RTCA0CAL_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t RTCA0SCMP;          /*!< (@ 0x0000003C) RTC Sub Count Compare Register                             */
+
+        struct
+        {
+            __IOM uint32_t RTCA0SCMP : 22; /*!< [21..0] Register that sets the compare value of RTCA0SUBC (sub-counter).  */
+            uint32_t                 : 10;
+        } RTCA0SCMP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0ALM;         /*!< (@ 0x00000040) RTC Alarm Min Set Register                                 */
+
+        struct
+        {
+            __IOM uint32_t RTCA0ALM : 7; /*!< [6..0] RTCA0ALM is a register that performs the minute setting
+                                          *   for the alarm interrupt.                                                  */
+            uint32_t : 25;
+        } RTCA0ALM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0ALH;         /*!< (@ 0x00000044) RTC Alarm Hour Set Register                                */
+
+        struct
+        {
+            __IOM uint32_t RTCA0ALH : 6; /*!< [5..0] RTCA0ALH is a register that performs the hour setting
+                                          *   for the alarm interrupt.                                                  */
+            uint32_t : 26;
+        } RTCA0ALH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RTCA0ALW;          /*!< (@ 0x00000048) RTC Alarm Week Set Register                                */
+
+        struct
+        {
+            __IOM uint32_t RTCA0ALW0 : 1; /*!< [0..0] Alarm interrupt day of the week setting bit 0                      */
+            __IOM uint32_t RTCA0ALW1 : 1; /*!< [1..1] Alarm interrupt day of the week setting bit 1                      */
+            __IOM uint32_t RTCA0ALW2 : 1; /*!< [2..2] Alarm interrupt day of the week setting bit 2                      */
+            __IOM uint32_t RTCA0ALW3 : 1; /*!< [3..3] Alarm interrupt day of the week setting bit 3                      */
+            __IOM uint32_t RTCA0ALW4 : 1; /*!< [4..4] Alarm interrupt day of the week setting bit 4                      */
+            __IOM uint32_t RTCA0ALW5 : 1; /*!< [5..5] Alarm interrupt day of the week setting bit 5                      */
+            __IOM uint32_t RTCA0ALW6 : 1; /*!< [6..6] Alarm interrupt day of the week setting bit 6                      */
+            uint32_t                 : 25;
+        } RTCA0ALW_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0SECC;         /*!< (@ 0x0000004C) RTC Second Count Register                                  */
+
+        struct
+        {
+            __IM uint32_t RTCA0SECC : 7; /*!< [6..0] Counts up the seconds                                              */
+            uint32_t                : 25;
+        } RTCA0SECC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0MINC;         /*!< (@ 0x00000050) RTC Minute Count Register                                  */
+
+        struct
+        {
+            __IM uint32_t RTCA0MINC : 7; /*!< [6..0] Counts up the minutes                                              */
+            uint32_t                : 25;
+        } RTCA0MINC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0HOURC;         /*!< (@ 0x00000054) RTC Hour Count Register                                    */
+
+        struct
+        {
+            __IM uint32_t RTCA0HOURC : 6; /*!< [5..0] Counts up the hours                                                */
+            uint32_t                 : 26;
+        } RTCA0HOURC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0WEEKC;         /*!< (@ 0x00000058) RTC Week Count Register                                    */
+
+        struct
+        {
+            __IM uint32_t RTCA0WEEKC : 3; /*!< [2..0] Counts up the weeks                                                */
+            uint32_t                 : 29;
+        } RTCA0WEEKC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0DAYC;         /*!< (@ 0x0000005C) RTC Day Count Register                                     */
+
+        struct
+        {
+            __IM uint32_t RTCA0DAYC : 6; /*!< [5..0] Counts up the days                                                 */
+            uint32_t                : 26;
+        } RTCA0DAYC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0MONC;         /*!< (@ 0x00000060) RTC Month Count Register                                   */
+
+        struct
+        {
+            __IM uint32_t RTCA0MONC : 5; /*!< [4..0] Counts up the months                                               */
+            uint32_t                : 27;
+        } RTCA0MONC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0YEARC;         /*!< (@ 0x00000064) RTC Year Count Register                                    */
+
+        struct
+        {
+            __IM uint32_t RTCA0YEARC : 8; /*!< [7..0] Counts up the years                                                */
+            uint32_t                 : 24;
+        } RTCA0YEARC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0TIMEC;         /*!< (@ 0x00000068) RTC Time Count Register                                    */
+
+        struct
+        {
+            __IM uint32_t RTCA0SECC  : 8; /*!< [7..0] See RTCA0SECC register                                             */
+            __IM uint32_t RTCA0MINC  : 8; /*!< [15..8] See RTCA0MINC register                                            */
+            __IM uint32_t RTCA0HOURC : 8; /*!< [23..16] See RTCA0HOURC register                                          */
+            uint32_t                 : 8;
+        } RTCA0TIMEC_b;
+    };
+
+    union
+    {
+        __IM uint32_t RTCA0CALC;          /*!< (@ 0x0000006C) RTC Calendar Count Register                                */
+
+        struct
+        {
+            __IM uint32_t RTCA0WEEKC : 8; /*!< [7..0] See RTCA0WEEKC register                                            */
+            __IM uint32_t RTCA0DAYC  : 8; /*!< [15..8] See RTCA0DAYC register                                            */
+            __IM uint32_t RTCA0MONC  : 8; /*!< [23..16] See RTCA0MONC register                                           */
+            __IM uint32_t RTCA0YEARC : 8; /*!< [31..24] See RTCA0YEARC register                                          */
+        } RTCA0CALC_b;
+    };
+} R_RTC_Type;                             /*!< Size = 112 (0x70)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG2                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief GPT Port Output Enable 2 (R_POEG2)
+ */
+
+typedef struct                         /*!< (@ 0x8100A000) R_POEG2 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t POEG2GA0;       /*!< (@ 0x00000000) POEG2 Group A Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG2GA0_b;
+    };
+    __IM uint32_t RESERVED[255];
+
+    union
+    {
+        __IOM uint32_t POEG2GB0;       /*!< (@ 0x00000400) POEG2 Group B Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG2GB0_b;
+    };
+    __IM uint32_t RESERVED1[255];
+
+    union
+    {
+        __IOM uint32_t POEG2GC0;       /*!< (@ 0x00000800) POEG2 Group C Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG2GC0_b;
+    };
+    __IM uint32_t RESERVED2[255];
+
+    union
+    {
+        __IOM uint32_t POEG2GD0;       /*!< (@ 0x00000C00) POEG2 Group D Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG2GD0_b;
+    };
+} R_POEG2_Type;                        /*!< Size = 3076 (0xc04)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSRAM0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System SRAM 0 (R_SYSRAM0)
+ */
+
+typedef struct                         /*!< (@ 0x81040000) R_SYSRAM0 Structure                                        */
+{
+    __IOM R_SYSRAM0_W_Type W[4];       /*!< (@ 0x00000000) System SRAM Wn Registers (n = 0 to 3)                      */
+} R_SYSRAM0_Type;                      /*!< Size = 256 (0x100)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_OTP                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief One-Time Programmable Memory (R_OTP)
+ */
+
+typedef struct                         /*!< (@ 0x810C0000) R_OTP Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t OTPPWR;         /*!< (@ 0x00000000) OTP Power Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t PWR  : 1;   /*!< [0..0] OTP power on/off setting                                           */
+            uint32_t            : 3;
+            __IOM uint32_t ACCL : 1;   /*!< [4..4] Selects OTP access I/F                                             */
+            uint32_t            : 27;
+        } OTPPWR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPSTR;             /*!< (@ 0x00000004) OTP Access Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t CMD_RDY : 1;     /*!< [0..0] Indicates whether OTP controller is ready to receive
+                                            *   command or not.                                                           */
+            __IM uint32_t ERR_WR      : 2; /*!< [2..1] OTP write status                                                   */
+            __IM uint32_t ERR_WP      : 1; /*!< [3..3] Write protection error                                             */
+            __IM uint32_t ERR_RP      : 1; /*!< [4..4] Read protection error                                              */
+            uint32_t                  : 3;
+            __IOM uint32_t ERR_RDY_WR : 1; /*!< [8..8] OTP write command ready error                                      */
+            __IOM uint32_t ERR_RDY_RD : 1; /*!< [9..9] OTP read command ready error                                       */
+            uint32_t                  : 2;
+            __IM uint32_t OTP_PWOK    : 1; /*!< [12..12] Indicates power on/off status of OTP Memory                      */
+            uint32_t                  : 19;
+        } OTPSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPSTAWR;       /*!< (@ 0x00000008) OTP Write Command Register                                 */
+
+        struct
+        {
+            __IOM uint32_t STAWR : 1;  /*!< [0..0] OTP write start                                                    */
+            uint32_t             : 31;
+        } OTPSTAWR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPADRWR;       /*!< (@ 0x0000000C) OTP Write Address Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADRWR : 10; /*!< [9..0] OTP write address                                                  */
+            uint32_t             : 22;
+        } OTPADRWR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPDATAWR;       /*!< (@ 0x00000010) OTP Write Data Register                                    */
+
+        struct
+        {
+            __IOM uint32_t DATAWR : 32; /*!< [31..0] OTP write data                                                    */
+        } OTPDATAWR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OTPADRRD;       /*!< (@ 0x00000014) OTP Read Address Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ADRRD : 10; /*!< [9..0] OTP read address                                                   */
+            uint32_t             : 22;
+        } OTPADRRD_b;
+    };
+
+    union
+    {
+        __IM uint32_t OTPDATARD;       /*!< (@ 0x00000018) OTP Read Data Register                                     */
+
+        struct
+        {
+            __IM uint32_t DATARD : 32; /*!< [31..0] OTP read data                                                     */
+        } OTPDATARD_b;
+    };
+} R_OTP_Type;                          /*!< Size = 28 (0x1c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MPU_AC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Master MPU Access Control (R_MPU_AC)
+ */
+
+typedef struct                             /*!< (@ 0x81240000) R_MPU_AC Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t CPU_CTRL;           /*!< (@ 0x00000000) CPU Access Permission Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t CR521_CTRL : 1; /*!< [0..0] CR521_CTRL                                                         */
+            uint32_t                  : 7;
+            __IOM uint32_t CA550_CTRL : 1; /*!< [8..8] CA550_CTRL                                                         */
+            __IOM uint32_t CA551_CTRL : 1; /*!< [9..9] CA551_CTRL                                                         */
+            __IOM uint32_t CA552_CTRL : 1; /*!< [10..10] CA552_CTRL                                                       */
+            __IOM uint32_t CA553_CTRL : 1; /*!< [11..11] CA553_CTRL                                                       */
+            uint32_t                  : 20;
+        } CPU_CTRL_b;
+    };
+} R_MPU_AC_Type;                           /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSC_S                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Register Write Protection for Safety Area (R_SYSC_S)
+ */
+
+typedef struct                         /*!< (@ 0x81280000) R_SYSC_S Structure                                         */
+{
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t SCKCR2;               /*!< (@ 0x00000004) System Clock Control Register 2                            */
+
+        struct
+        {
+            __IOM uint32_t CR52CPU0     : 2; /*!< [1..0] CR52CPU0                                                           */
+            __IOM uint32_t CR52CPU1     : 2; /*!< [3..2] CR52CPU1                                                           */
+            uint32_t                    : 4;
+            __IOM uint32_t CA55CORE0    : 1; /*!< [8..8] CA55CORE0                                                          */
+            __IOM uint32_t CA55CORE1    : 1; /*!< [9..9] CA55CORE1                                                          */
+            __IOM uint32_t CA55CORE2    : 1; /*!< [10..10] CA55CORE2                                                        */
+            __IOM uint32_t CA55CORE3    : 1; /*!< [11..11] CA55CORE3                                                        */
+            __IOM uint32_t CA55SCLK     : 1; /*!< [12..12] CA55SCLK                                                         */
+            uint32_t                    : 3;
+            __IOM uint32_t SPI3ASYNCSEL : 2; /*!< [17..16] SPI3ASYNCSEL                                                     */
+            __IOM uint32_t SCI5ASYNCSEL : 2; /*!< [19..18] SCI5ASYNCSEL                                                     */
+            uint32_t                    : 12;
+        } SCKCR2_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t PMSEL;          /*!< (@ 0x00000010) PLL/Main OSC clock Select Register                         */
+
+        struct
+        {
+            uint32_t                : 9;
+            __IM uint32_t PMSEL0MON : 1; /*!< [9..9] PMSEL0MON                                                          */
+            __IM uint32_t PMSEL1MON : 1; /*!< [10..10] PMSEL1MON                                                        */
+            __IM uint32_t PMSEL2MON : 1; /*!< [11..11] PMSEL2MON                                                        */
+            __IM uint32_t PMSEL3MON : 1; /*!< [12..12] PMSEL3MON                                                        */
+            __IM uint32_t PMSEL4MON : 1; /*!< [13..13] PMSEL4MON                                                        */
+            uint32_t                : 18;
+        } PMSEL_b;
+    };
+    __IM uint32_t RESERVED2[3];
+
+    union
+    {
+        __IM uint32_t PLL0MON;         /*!< (@ 0x00000020) PLL0 Monitor Register                                      */
+
+        struct
+        {
+            __IM uint32_t PLL0MON : 1; /*!< [0..0] PLL0 Lock State Monitor                                            */
+            uint32_t              : 31;
+        } PLL0MON_b;
+    };
+    __IM uint32_t RESERVED3[3];
+
+    union
+    {
+        __IOM uint32_t PLL0EN;         /*!< (@ 0x00000030) PLL0 Enable Register                                       */
+
+        struct
+        {
+            __IOM uint32_t PLL0EN : 1; /*!< [0..0] PLL0EN                                                             */
+            uint32_t              : 31;
+        } PLL0EN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PLL0_SSC_CTR;      /*!< (@ 0x00000034) PLL0 SSC Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t PLL0SSCEN : 1; /*!< [0..0] PLL0SSCEN                                                          */
+            uint32_t                 : 15;
+            __IOM uint32_t PLL0MRR   : 6; /*!< [21..16] PLL0MRR                                                          */
+            uint32_t                 : 2;
+            __IOM uint32_t PLL0MFR   : 8; /*!< [31..24] PLL0MFR                                                          */
+        } PLL0_SSC_CTR_b;
+    };
+    __IM uint32_t RESERVED4[2];
+
+    union
+    {
+        __IM uint32_t PLL1MON;         /*!< (@ 0x00000040) PLL1 Monitor Register                                      */
+
+        struct
+        {
+            __IM uint32_t PLL1MON : 1; /*!< [0..0] PLL1 Lock State Monitor                                            */
+            uint32_t              : 31;
+        } PLL1MON_b;
+    };
+    __IM uint32_t RESERVED5[11];
+
+    union
+    {
+        __IOM uint32_t LOCOCR;         /*!< (@ 0x00000070) Low-Speed On-Chip Oscillator Control Register              */
+
+        struct
+        {
+            __IOM uint32_t LCSTP : 1;  /*!< [0..0] LOCO Stop                                                          */
+            uint32_t             : 31;
+        } LOCOCR_b;
+    };
+    __IM uint32_t RESERVED6[3];
+
+    union
+    {
+        __IOM uint32_t HIZCTRLEN;         /*!< (@ 0x00000080) High-Impedance Control Enable Register                     */
+
+        struct
+        {
+            __IOM uint32_t CLMA6MASK : 1; /*!< [0..0] CLMA6MASK                                                          */
+            __IOM uint32_t CLMA0MASK : 1; /*!< [1..1] CLMA0MASK                                                          */
+            __IOM uint32_t CLMA1MASK : 1; /*!< [2..2] CLMA1MASK                                                          */
+            __IOM uint32_t CLMA2MASK : 1; /*!< [3..3] CLMA2MASK                                                          */
+            __IOM uint32_t CLMA3MASK : 1; /*!< [4..4] CLMA3MASK                                                          */
+            __IOM uint32_t CLMA4MASK : 1; /*!< [5..5] CLMA4MASK                                                          */
+            uint32_t                 : 26;
+        } HIZCTRLEN_b;
+    };
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        __IM uint32_t PLL2MON;         /*!< (@ 0x00000090) PLL2 Monitor Register                                      */
+
+        struct
+        {
+            __IM uint32_t PLL2MON : 1; /*!< [0..0] PLL2 Lock State Monitor                                            */
+            uint32_t              : 31;
+        } PLL2MON_b;
+    };
+    __IM uint32_t RESERVED8[3];
+
+    union
+    {
+        __IOM uint32_t PLL2EN;         /*!< (@ 0x000000A0) PLL2 Enable Register                                       */
+
+        struct
+        {
+            __IOM uint32_t PLL2EN : 1; /*!< [0..0] PLL2EN                                                             */
+            uint32_t              : 31;
+        } PLL2EN_b;
+    };
+    __IM uint32_t RESERVED9[2];
+
+    union
+    {
+        __IOM uint32_t PLL2_SSC_CTR;      /*!< (@ 0x000000AC) PLL2 SSC Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t PLL2SSCEN : 1; /*!< [0..0] PLL2SSCEN                                                          */
+            uint32_t                 : 15;
+            __IOM uint32_t PLL2MRR   : 6; /*!< [21..16] PLL2MRR                                                          */
+            uint32_t                 : 2;
+            __IOM uint32_t PLL2MFR   : 8; /*!< [31..24] PLL2MFR                                                          */
+        } PLL2_SSC_CTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t PLL3MON;         /*!< (@ 0x000000B0) PLL3 Monitor Register                                      */
+
+        struct
+        {
+            __IM uint32_t PLL3MON : 1; /*!< [0..0] PLL3 Lock State Monitor                                            */
+            uint32_t              : 31;
+        } PLL3MON_b;
+    };
+    __IM uint32_t RESERVED10[3];
+
+    union
+    {
+        __IOM uint32_t PLL3EN;         /*!< (@ 0x000000C0) PLL3 Enable Register                                       */
+
+        struct
+        {
+            __IOM uint32_t PLL3EN : 1; /*!< [0..0] PLL3EN                                                             */
+            uint32_t              : 31;
+        } PLL3EN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PLL3_VCO_CTR0;  /*!< (@ 0x000000C4) PLL3 VCO Control Register 0                                */
+
+        struct
+        {
+            __IOM uint32_t PLL3M : 10; /*!< [9..0] PLL3 M-Divider Setting                                             */
+            uint32_t             : 6;
+            __IOM uint32_t PLL3P : 6;  /*!< [21..16] PLL3 P-Divider Setting                                           */
+            uint32_t             : 10;
+        } PLL3_VCO_CTR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PLL3_VCO_CTR1;  /*!< (@ 0x000000C8) PLL3 VCO Control Register 1                                */
+
+        struct
+        {
+            __IOM uint32_t PLL3S : 3;  /*!< [2..0] PLL3 S-Divider Setting                                             */
+            uint32_t             : 13;
+            __IOM uint32_t PLL3K : 16; /*!< [31..16] PLL3 Delta-Sigma Modulator Setting                               */
+        } PLL3_VCO_CTR1_b;
+    };
+    __IM uint32_t RESERVED11;
+
+    union
+    {
+        __IM uint32_t PLL4MON;         /*!< (@ 0x000000D0) PLL4 Monitor Register                                      */
+
+        struct
+        {
+            __IM uint32_t PLL4MON : 1; /*!< [0..0] PLL4 Lock State Monitor                                            */
+            uint32_t              : 31;
+        } PLL4MON_b;
+    };
+    __IM uint32_t RESERVED12[79];
+
+    union
+    {
+        __OM uint32_t SWRSYS;          /*!< (@ 0x00000210) System Software Reset Register                             */
+
+        struct
+        {
+            __OM uint32_t SWR : 32;    /*!< [31..0] System Software Reset                                             */
+        } SWRSYS_b;
+    };
+    __IM uint32_t RESERVED13[3];
+
+    union
+    {
+        __IOM uint32_t SWRCPU0;        /*!< (@ 0x00000220) Cortex-R52 CPU0 Software Reset Register                    */
+
+        struct
+        {
+            __IOM uint32_t SWR : 32;   /*!< [31..0] Cortex-R52 CPU0 Software Reset                                    */
+        } SWRCPU0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWRCPU1;        /*!< (@ 0x00000224) Cortex-R52 CPU1 Software Reset Register                    */
+
+        struct
+        {
+            __IOM uint32_t SWR : 32;   /*!< [31..0] Cortex-R52 CPU1 Software Reset                                    */
+        } SWRCPU1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWR55C;         /*!< (@ 0x00000228) Cortex-A55 Cluster Software Reset Register                 */
+
+        struct
+        {
+            __IOM uint32_t SWR : 32;   /*!< [31..0] Cortex-A55 Cluster Software Reset                                 */
+        } SWR55C_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWR550;         /*!< (@ 0x0000022C) Cortex-A55 Core0 Software Reset Register                   */
+
+        struct
+        {
+            __IOM uint32_t SWR : 32;   /*!< [31..0] Cortex-A55 Core0 Software Reset                                   */
+        } SWR550_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWR551;         /*!< (@ 0x00000230) Cortex-A55 Core1 Software Reset Register                   */
+
+        struct
+        {
+            __IOM uint32_t SWR : 32;   /*!< [31..0] Cortex-A55 Core1 Software Reset                                   */
+        } SWR551_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWR552;         /*!< (@ 0x00000234) Cortex-A55 Core2 Software Reset Register                   */
+
+        struct
+        {
+            __IOM uint32_t SWR : 32;   /*!< [31..0] Cortex-A55 Core2 Software Reset                                   */
+        } SWR552_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWR553;         /*!< (@ 0x00000238) Cortex-A55 Core3 Software Reset Register                   */
+
+        struct
+        {
+            __IOM uint32_t SWR : 32;   /*!< [31..0] Cortex-A55 Core3 Software Reset                                   */
+        } SWR553_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SWR55ARC;       /*!< (@ 0x0000023C) Cortex-A55 Software Reset Automatic Release Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t ARC550 : 1; /*!< [0..0] ARC550                                                             */
+            __IOM uint32_t ARC551 : 1; /*!< [1..1] ARC551                                                             */
+            __IOM uint32_t ARC552 : 1; /*!< [2..2] ARC552                                                             */
+            __IOM uint32_t ARC553 : 1; /*!< [3..3] ARC553                                                             */
+            uint32_t              : 28;
+        } SWR55ARC_b;
+    };
+    __IM uint32_t RESERVED14[8];
+
+    union
+    {
+        __IOM uint32_t MRCTLI;         /*!< (@ 0x00000260) Module Reset Control Register I                            */
+
+        struct
+        {
+            uint32_t                : 1;
+            __IOM uint32_t MRCTLI01 : 1; /*!< [1..1] SHOSTIF (Master bus clock domain) Reset Control                    */
+            __IOM uint32_t MRCTLI02 : 1; /*!< [2..2] SHOSTIF (Slave bus clock domain) Reset Control                     */
+            __IOM uint32_t MRCTLI03 : 1; /*!< [3..3] SHOSTIF (IP clock domain) Reset Control                            */
+            uint32_t                : 28;
+        } MRCTLI_b;
+    };
+    __IM uint32_t RESERVED15[45];
+
+    union
+    {
+        __IOM uint32_t MSTPCRG;           /*!< (@ 0x00000318) Module Stop Control Register G                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRG00 : 1; /*!< [0..0] SCI Unit 5 Module Stop                                             */
+            __IOM uint32_t MSTPCRG01 : 1; /*!< [1..1] IIC Unit 2 Module Stop                                             */
+            __IOM uint32_t MSTPCRG02 : 1; /*!< [2..2] SPI Unit 3 Module Stop                                             */
+            __IOM uint32_t MSTPCRG03 : 1; /*!< [3..3] GPT Unit 10 Module Stop                                            */
+            __IOM uint32_t MSTPCRG04 : 1; /*!< [4..4] CRC Unit 1 Module Stop                                             */
+            __IOM uint32_t MSTPCRG05 : 1; /*!< [5..5] RTC Module Stop                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t MSTPCRG08 : 1; /*!< [8..8] CLMA6 Module Stop                                                  */
+            __IOM uint32_t MSTPCRG09 : 1; /*!< [9..9] CLMA0 Module Stop                                                  */
+            __IOM uint32_t MSTPCRG10 : 1; /*!< [10..10] CLMA1 Module Stop                                                */
+            __IOM uint32_t MSTPCRG11 : 1; /*!< [11..11] CLMA2 Module Stop                                                */
+            __IOM uint32_t MSTPCRG12 : 1; /*!< [12..12] MSTPCRG12                                                        */
+            __IOM uint32_t MSTPCRG13 : 1; /*!< [13..13] MSTPCRG13                                                        */
+            __IOM uint32_t MSTPCRG14 : 1; /*!< [14..14] MSTPCRG14                                                        */
+            uint32_t                 : 17;
+        } MSTPCRG_b;
+    };
+    __IM uint32_t RESERVED16;
+
+    union
+    {
+        __IOM uint32_t MSTPCRI;        /*!< (@ 0x00000320) Module Stop Control Register I                             */
+
+        struct
+        {
+            uint32_t                 : 1;
+            __IOM uint32_t MSTPCRI01 : 1; /*!< [1..1] MSTPCRI01                                                          */
+            uint32_t                 : 30;
+        } MSTPCRI_b;
+    };
+    __IM uint32_t RESERVED17[4];
+
+    union
+    {
+        __IOM uint32_t MSTPCRN;           /*!< (@ 0x00000334) Module Stop Control Register N                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPCRN00 : 1; /*!< [0..0] Cortex-R52 CPU0 Module Stop                                        */
+            __IOM uint32_t MSTPCRN01 : 1; /*!< [1..1] Cortex-R52 CPU1 Module Stop                                        */
+            __IOM uint32_t MSTPCRN02 : 1; /*!< [2..2] Cortex-A55 Core0 Module Stop                                       */
+            __IOM uint32_t MSTPCRN03 : 1; /*!< [3..3] Cortex-A55 Core1 Module Stop                                       */
+            __IOM uint32_t MSTPCRN04 : 1; /*!< [4..4] Cortex-A55 Core2 Module Stop                                       */
+            __IOM uint32_t MSTPCRN05 : 1; /*!< [5..5] Cortex-A55 Core3 Module Stop                                       */
+            uint32_t                 : 26;
+        } MSTPCRN_b;
+    };
+} R_SYSC_S_Type;                          /*!< Size = 824 (0x338)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CLMA0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Clock Monitor Circuit 0 (R_CLMA0)
+ */
+
+typedef struct                         /*!< (@ 0x81288000) R_CLMA0 Structure                                          */
+{
+    union
+    {
+        __IOM uint8_t CTL0;            /*!< (@ 0x00000000) CLMA Control Register 0                                    */
+
+        struct
+        {
+            __IOM uint8_t CLME : 1;    /*!< [0..0] Clock Monitor m Enable (m = 0 to 6)                                */
+            uint8_t            : 7;
+        } CTL0_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint16_t CMPL;           /*!< (@ 0x00000008) CLMA Compare Register L                                    */
+
+        struct
+        {
+            __IOM uint16_t CMPL : 12;  /*!< [11..0] Clock Monitor m Compare L (m = 0 to 6)                            */
+            uint16_t            : 4;
+        } CMPL_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint16_t CMPH;           /*!< (@ 0x0000000C) CLMA Compare Register H                                    */
+
+        struct
+        {
+            __IOM uint16_t CMPH : 12;  /*!< [11..0] Clock Monitor m Compare H (m = 0 to 6)                            */
+            uint16_t            : 4;
+        } CMPH_b;
+    };
+    __IM uint16_t RESERVED3;
+    __OM uint8_t  PCMD;                /*!< (@ 0x00000010) CLMA Command Register                                      */
+    __IM uint8_t  RESERVED4;
+    __IM uint16_t RESERVED5;
+
+    union
+    {
+        __IM uint8_t PROTSR;           /*!< (@ 0x00000014) CLMA Protection Status Register                            */
+
+        struct
+        {
+            __IM uint8_t PRERR : 1;    /*!< [0..0] CLMAm Error (m = 0 to 6)                                           */
+            uint8_t            : 7;
+        } PROTSR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+} R_CLMA0_Type;                        /*!< Size = 24 (0x18)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADXC0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Address Expander Control 0 (R_ADXC0)
+ */
+
+typedef struct                           /*!< (@ 0x81290100) R_ADXC0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t ADXCTL0;          /*!< (@ 0x00000000) Address Expander Control Register 0                        */
+
+        struct
+        {
+            __IOM uint32_t PCIE0MIR : 5; /*!< [4..0] PCIE0 Mirror Address                                               */
+            uint32_t                : 3;
+            __IOM uint32_t PCIE1MIR : 5; /*!< [12..8] PCIE1 Mirror Address                                              */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR0  : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR1  : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t                : 3;
+        } ADXCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL1;          /*!< (@ 0x00000004) Address Expander Control Register 1                        */
+
+        struct
+        {
+            __IOM uint32_t PCIE0MIR : 5; /*!< [4..0] PCIE0 Mirror Address                                               */
+            uint32_t                : 3;
+            __IOM uint32_t PCIE1MIR : 5; /*!< [12..8] PCIE1 Mirror Address                                              */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR0  : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR1  : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t                : 3;
+        } ADXCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL2;          /*!< (@ 0x00000008) Address Expander Control Register 2                        */
+
+        struct
+        {
+            __IOM uint32_t PCIE0MIR : 5; /*!< [4..0] PCIE0 Mirror Address                                               */
+            uint32_t                : 3;
+            __IOM uint32_t PCIE1MIR : 5; /*!< [12..8] PCIE1 Mirror Address                                              */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR0  : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR1  : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t                : 3;
+        } ADXCTL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL3;          /*!< (@ 0x0000000C) Address Expander Control Register 3                        */
+
+        struct
+        {
+            __IOM uint32_t PCIE0MIR : 5; /*!< [4..0] PCIE0 Mirror Address                                               */
+            uint32_t                : 3;
+            __IOM uint32_t PCIE1MIR : 5; /*!< [12..8] PCIE1 Mirror Address                                              */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR0  : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR1  : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t                : 3;
+        } ADXCTL3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL4;          /*!< (@ 0x00000010) Address Expander Control Register 4                        */
+
+        struct
+        {
+            __IOM uint32_t PCIE0MIR : 5; /*!< [4..0] PCIE0 Mirror Address                                               */
+            uint32_t                : 3;
+            __IOM uint32_t PCIE1MIR : 5; /*!< [12..8] PCIE1 Mirror Address                                              */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR0  : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t                : 3;
+            __IOM uint32_t DDRMIR1  : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t                : 3;
+        } ADXCTL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL5;        /*!< (@ 0x00000014) Address Expander Control Register 5                        */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t DDRMIR0 : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t               : 3;
+            __IOM uint32_t DDRMIR1 : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t               : 3;
+        } ADXCTL5_b;
+    };
+} R_ADXC0_Type;                         /*!< Size = 24 (0x18)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_SSC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Slave Stop Control (R_SSC)
+ */
+
+typedef struct                            /*!< (@ 0x81290200) R_SSC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t SSTPCR4;           /*!< (@ 0x00000000) Slave Stop Control Register 4                              */
+
+        struct
+        {
+            __IOM uint32_t DDRR2_REQ : 1; /*!< [0..0] DDRR2_REQ                                                          */
+            __IM uint32_t  DDRR2_ACK : 1; /*!< [1..1] DDRR2_ACK                                                          */
+            uint32_t                 : 2;
+            __IOM uint32_t DDRR3_REQ : 1; /*!< [4..4] DDRR3_REQ                                                          */
+            __IM uint32_t  DDRR3_ACK : 1; /*!< [5..5] DDRR3_ACK                                                          */
+            uint32_t                 : 2;
+            __IOM uint32_t DDRAPB    : 1; /*!< [8..8] DDRAPB                                                             */
+            uint32_t                 : 23;
+        } SSTPCR4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSTPCR5;        /*!< (@ 0x00000004) Slave Stop Control Register 5                              */
+
+        struct
+        {
+            uint32_t                  : 16;
+            __IOM uint32_t GIC600_REQ : 1; /*!< [16..16] GIC600_REQ                                                       */
+            __IM uint32_t  GIC600_ACK : 1; /*!< [17..17] GIC600_ACK                                                       */
+            uint32_t                  : 14;
+        } SSTPCR5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSTPCR6;           /*!< (@ 0x00000008) Slave Stop Control Register 6                              */
+
+        struct
+        {
+            __IOM uint32_t XSPI0_REQ : 1; /*!< [0..0] XSPI0_REQ                                                          */
+            __IM uint32_t  XSPI0_ACK : 1; /*!< [1..1] XSPI0_ACK                                                          */
+            uint32_t                 : 2;
+            __IOM uint32_t XSPI1_REQ : 1; /*!< [4..4] XSPI1_REQ                                                          */
+            __IM uint32_t  XSPI1_ACK : 1; /*!< [5..5] XSPI1_ACK                                                          */
+            uint32_t                 : 26;
+        } SSTPCR6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSTPCR7;           /*!< (@ 0x0000000C) Slave Stop Control Register 7                              */
+
+        struct
+        {
+            __IOM uint32_t AXIS0_REQ : 1; /*!< [0..0] AXIS0_REQ                                                          */
+            __IM uint32_t  AXIS0_ACK : 1; /*!< [1..1] AXIS0_ACK                                                          */
+            uint32_t                 : 2;
+            __IOM uint32_t AXIS1_REQ : 1; /*!< [4..4] AXIS1_REQ                                                          */
+            __IM uint32_t  AXIS1_ACK : 1; /*!< [5..5] AXIS1_ACK                                                          */
+            uint32_t                 : 26;
+        } SSTPCR7_b;
+    };
+    __IM uint32_t RESERVED[1020];
+
+    union
+    {
+        __IOM uint32_t SSTPCR0;           /*!< (@ 0x00001000) Slave Stop Control Register 0                              */
+
+        struct
+        {
+            __IOM uint32_t DDRA0_REQ : 1; /*!< [0..0] DDRA0_REQ                                                          */
+            __IM uint32_t  DDRA0_ACK : 1; /*!< [1..1] DDRSS A0 I/F Bus Stop Acknowledge                                  */
+            uint32_t                 : 2;
+            __IOM uint32_t DDRA1_REQ : 1; /*!< [4..4] DDRA1_REQ                                                          */
+            __IM uint32_t  DDRA1_ACK : 1; /*!< [5..5] DDRA1_ACK                                                          */
+            uint32_t                 : 2;
+            __IOM uint32_t DDRA4_REQ : 1; /*!< [8..8] DDRA4_REQ                                                          */
+            __IM uint32_t  DDRA4_ACK : 1; /*!< [9..9] DDRA4_ACK                                                          */
+            uint32_t                 : 22;
+        } SSTPCR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSTPCR1;           /*!< (@ 0x00001004) Slave Stop Control Register 1                              */
+
+        struct
+        {
+            __IOM uint32_t PCIE0_REQ : 1; /*!< [0..0] PCIE0_REQ                                                          */
+            __IM uint32_t  PCIE0_ACK : 1; /*!< [1..1] PCIE0_ACK                                                          */
+            uint32_t                 : 2;
+            __IOM uint32_t PCIE1_REQ : 1; /*!< [4..4] PCIE1_REQ                                                          */
+            __IM uint32_t  PCIE1_ACK : 1; /*!< [5..5] PCIE1_ACK                                                          */
+            uint32_t                 : 10;
+            __IOM uint32_t SDHI0_REQ : 1; /*!< [16..16] SDHI0_REQ                                                        */
+            __IM uint32_t  SDHI0_ACK : 1; /*!< [17..17] SDHI0_ACK                                                        */
+            uint32_t                 : 2;
+            __IOM uint32_t SDHI1_REQ : 1; /*!< [20..20] SDHI1_REQ                                                        */
+            __IM uint32_t  SDHI1_ACK : 1; /*!< [21..21] SDHI1 I/F Bus Stop Acknowledge                                   */
+            uint32_t                 : 10;
+        } SSTPCR1_b;
+    };
+} R_SSC_Type;                             /*!< Size = 4104 (0x1008)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MSAC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Master and Slave Access Control (R_MSAC)
+ */
+
+typedef struct                                /*!< (@ 0x81290300) R_MSAC Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t MSTACCCTL2;            /*!< (@ 0x00000000) Master Access Control Register 2                           */
+
+        struct
+        {
+            __IOM uint32_t CSAXIAP_PROT0 : 1; /*!< [0..0] CS AXI-AP Privilege Attribute Overwrite                            */
+            __IOM uint32_t CSAXIAP_PROT1 : 1; /*!< [1..1] CS AXI-AP Security Attribute Overwrite                             */
+            __IOM uint32_t CSAXIAP_SEL0  : 1; /*!< [2..2] CS AXI-AP Privilege Attribute (AxPROT[0]) Overwrite Select         */
+            __IOM uint32_t CSAXIAP_SEL1  : 1; /*!< [3..3] CS AXI-AP Security Attribute (AxPROT[1]) Overwrite Select          */
+            __IOM uint32_t GMAC0_PROT0   : 1; /*!< [4..4] GMAC0 Privilege Attribute Overwrite                                */
+            __IOM uint32_t GMAC0_PROT1   : 1; /*!< [5..5] GMAC0 Security Attribute Overwrite                                 */
+            __IOM uint32_t GMAC0_SEL0    : 1; /*!< [6..6] GMAC0 Privilege Attribute (AxPROT[0]) Overwrite Select             */
+            __IOM uint32_t GMAC0_SEL1    : 1; /*!< [7..7] GMAC0 Security Attribute (AxPROT[1]) Overwrite Select              */
+            uint32_t                     : 4;
+            __IOM uint32_t DMAC0_PROT0   : 1; /*!< [12..12] DMAC0 Privilege Attribute Overwrite                              */
+            __IOM uint32_t DMAC0_PROT1   : 1; /*!< [13..13] DMAC0 Security Attribute Overwrite                               */
+            __IOM uint32_t DMAC0_SEL0    : 1; /*!< [14..14] DMAC0 Privilege Attribute (AxPROT[0]) Overwrite Select           */
+            __IOM uint32_t DMAC0_SEL1    : 1; /*!< [15..15] DMAC0 Security Attribute (AxPROT[1]) Overwrite Select            */
+            __IOM uint32_t DMAC1_PROT0   : 1; /*!< [16..16] DMAC1 Privilege Attribute Overwrite                              */
+            __IOM uint32_t DMAC1_PROT1   : 1; /*!< [17..17] DMAC1 Security Attribute Overwrite                               */
+            __IOM uint32_t DMAC1_SEL0    : 1; /*!< [18..18] DMAC1 Privilege Attribute (AxPROT[0]) Overwrite Select           */
+            __IOM uint32_t DMAC1_SEL1    : 1; /*!< [19..19] DMAC1 Security Attribute (AxPROT[1]) Overwrite Select            */
+            __IOM uint32_t DMAC2_PROT0   : 1; /*!< [20..20] DMAC2 Privilege Attribute Overwrite                              */
+            __IOM uint32_t DMAC2_PROT1   : 1; /*!< [21..21] DMAC2 Security Attribute Overwrite                               */
+            __IOM uint32_t DMAC2_SEL0    : 1; /*!< [22..22] DMAC2 Privilege Attribute (AxPROT[0]) Overwrite Select           */
+            __IOM uint32_t DMAC2_SEL1    : 1; /*!< [23..23] DMAC2 Security Attribute (AxPROT[1]) Overwrite Select            */
+            __IOM uint32_t CR520_PROT0   : 1; /*!< [24..24] CR520 Privilege Attribute Overwrite                              */
+            __IOM uint32_t CR520_PROT1   : 1; /*!< [25..25] CR520 Security Attribute Overwrite                               */
+            __IOM uint32_t CR520_SEL0    : 1; /*!< [26..26] CR520 Privilege Attribute (AxPROT[0]) Overwrite Select           */
+            __IOM uint32_t CR520_SEL1    : 1; /*!< [27..27] CR520 Security Attribute (AxPROT[1]) Overwrite Select            */
+            __IOM uint32_t CR521_PROT0   : 1; /*!< [28..28] CR521 Privilege Attribute Overwrite                              */
+            __IOM uint32_t CR521_PROT1   : 1; /*!< [29..29] CR521 Security Attribute Overwrite                               */
+            __IOM uint32_t CR521_SEL0    : 1; /*!< [30..30] CR521 Privilege Attribute (AxPROT[0]) Overwrite Select           */
+            __IOM uint32_t CR521_SEL1x   : 1; /*!< [31..31] CR521 Security Attribute (AxPROT[1]) Overwrite Select            */
+        } MSTACCCTL2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTACCCTL3;            /*!< (@ 0x00000004) Master Access Control Register 3                           */
+
+        struct
+        {
+            __IOM uint32_t SHOSTIF_PROT0 : 1; /*!< [0..0] SHOSTIF Privilege Attribute Overwrite                              */
+            __IOM uint32_t SHOSTIF_PROT1 : 1; /*!< [1..1] SHOSTIF Security Attribute Overwrite                               */
+            uint32_t                     : 1;
+            __IOM uint32_t SHOSTIF_SEL   : 1; /*!< [3..3] SHOSTIF Security Attribute (HNONSEC) and Privilege Attribute
+                                               *   (HPROT[1]) Overwrite Select                                               */
+            uint32_t : 28;
+        } MSTACCCTL3_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL6;         /*!< (@ 0x00000010) Slave Access Control Register 6                            */
+
+        struct
+        {
+            __IOM uint32_t ETHSS_SL   : 2; /*!< [1..0] ETHSS_SL                                                           */
+            __IOM uint32_t ETHSW_SL   : 2; /*!< [3..2] ETHSW_SL                                                           */
+            __IOM uint32_t ESC_SL     : 2; /*!< [5..4] ESC_SL                                                             */
+            __IOM uint32_t GMAC0_SL   : 2; /*!< [7..6] GMAC0_SL                                                           */
+            uint32_t                  : 2;
+            __IOM uint32_t CA55_SL    : 2; /*!< [11..10] CA55_SL                                                          */
+            __IOM uint32_t CR520_SL   : 2; /*!< [13..12] CR520_SL                                                         */
+            __IOM uint32_t CR521_SL   : 2; /*!< [15..14] CR521_SL                                                         */
+            __IOM uint32_t DMAC0_SL   : 2; /*!< [17..16] DMAC0_SL                                                         */
+            __IOM uint32_t DMAC1_SL   : 2; /*!< [19..18] DMAC1_SL                                                         */
+            __IOM uint32_t DMAC2_SL   : 2; /*!< [21..20] DMAC2_SL                                                         */
+            uint32_t                  : 2;
+            __IOM uint32_t SYSRAM0_SL : 2; /*!< [25..24] SYSRAM0_SL                                                       */
+            __IOM uint32_t SYSRAM1_SL : 2; /*!< [27..26] SYSRAM1_SL                                                       */
+            __IOM uint32_t SYSRAM2_SL : 2; /*!< [29..28] SYSRAM2_SL                                                       */
+            __IOM uint32_t SYSRAM3_SL : 2; /*!< [31..30] SYSRAM3_SL                                                       */
+        } SLVACCCTL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL7;          /*!< (@ 0x00000014) Slave Access Control Register 7                            */
+
+        struct
+        {
+            __IOM uint32_t MBXSEM_SL   : 2; /*!< [1..0] MBXSEM_SL                                                          */
+            __IOM uint32_t SHOSTIF_SL  : 2; /*!< [3..2] SHOSTIF_SL                                                         */
+            uint32_t                   : 14;
+            __IOM uint32_t LLPP_SL     : 2; /*!< [19..18] LLPP_SL                                                          */
+            uint32_t                   : 2;
+            __IOM uint32_t BUS_SL      : 2; /*!< [23..22] Bus Security Level                                               */
+            __IOM uint32_t RSIP_SL     : 2; /*!< [25..24] RSIP_SL                                                          */
+            __IOM uint32_t OTP_SL      : 2; /*!< [27..26] OTP_SL                                                           */
+            __IOM uint32_t GIC600_SL   : 2; /*!< [29..28] GIC600_SL                                                        */
+            __IOM uint32_t CSDBGAPB_SL : 2; /*!< [31..30] CSDBGAPB_SL                                                      */
+        } SLVACCCTL7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL8;           /*!< (@ 0x00000018) Slave Access Control Register 8                            */
+
+        struct
+        {
+            __IOM uint32_t DDRCTRL_SL   : 2; /*!< [1..0] DDRCTRL_SL                                                         */
+            uint32_t                    : 2;
+            __IOM uint32_t TZCTCM_SL    : 2; /*!< [5..4] TZCTCM_SL                                                          */
+            __IOM uint32_t TZCDDRR2_SL  : 2; /*!< [7..6] TZCDDRR2_SL                                                        */
+            __IOM uint32_t TZCDDRR3_SL  : 2; /*!< [9..8] TZCDDRR3_SL                                                        */
+            __IOM uint32_t TZCSYSRAM_SL : 2; /*!< [11..10] TZCSYSRAM_SL                                                     */
+            __IOM uint32_t TZCXSPI_SL   : 2; /*!< [13..12] TZCXSPI_SL                                                       */
+            __IOM uint32_t TZCBSC_SL    : 2; /*!< [15..14] TZCBSC_SL                                                        */
+            __IOM uint32_t PRCR_SL      : 2; /*!< [17..16] PRCR_SL                                                          */
+            __IOM uint32_t ICU_SL       : 2; /*!< [19..18] ICU_SL                                                           */
+            __IOM uint32_t SYSCTRL_SL   : 2; /*!< [21..20] SYSCTRL_SL                                                       */
+            uint32_t                    : 2;
+            __IOM uint32_t XSPI0_SL     : 2; /*!< [25..24] XSPI0_SL                                                         */
+            __IOM uint32_t XSPI1_SL     : 2; /*!< [27..26] XSPI1_SL                                                         */
+            uint32_t                    : 4;
+        } SLVACCCTL8_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL9;            /*!< (@ 0x0000001C) Slave Access Control Register 9                            */
+
+        struct
+        {
+            __IOM uint32_t ADDEXP_SL     : 2; /*!< [1..0] ADDEXP_SL                                                          */
+            uint32_t                     : 14;
+            __IOM uint32_t MPUSHOSTIF_SL : 2; /*!< [17..16] MPUSHOSTIF_SL                                                    */
+            __IOM uint32_t MPUGMAC0_SL   : 2; /*!< [19..18] MPUGMAC0_SL                                                      */
+            __IOM uint32_t MPUDMAC0_SL   : 2; /*!< [21..20] MPUDMAC0_SL                                                      */
+            __IOM uint32_t MPUDMAC1_SL   : 2; /*!< [23..22] MPUDMAC1_SL                                                      */
+            __IOM uint32_t MPUDMAC2_SL   : 2; /*!< [25..24] MPUDMAC2_SL                                                      */
+            __IOM uint32_t MPUCS_SL      : 2; /*!< [27..26] MPUCS_SL                                                         */
+            uint32_t                     : 4;
+        } SLVACCCTL9_b;
+    };
+    __IM uint32_t RESERVED1[1016];
+
+    union
+    {
+        __IOM uint32_t MSTACCCTL0;          /*!< (@ 0x00001000) Master Access Control Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t CSETR_PROT0 : 1; /*!< [0..0] CSETR_PROT0                                                        */
+            __IOM uint32_t CSETR_PROT1 : 1; /*!< [1..1] CSETR_PROT1                                                        */
+            __IOM uint32_t CSETR_SEL0  : 1; /*!< [2..2] CSETR_SEL0                                                         */
+            __IOM uint32_t CSETR_SEL1  : 1; /*!< [3..3] CSETR_SEL1                                                         */
+            __IOM uint32_t LCDC_PROT0  : 1; /*!< [4..4] LCDC_PROT0                                                         */
+            __IOM uint32_t LCDC_PROT1  : 1; /*!< [5..5] LCDC_PROT1                                                         */
+            __IOM uint32_t LCDC_SEL0   : 1; /*!< [6..6] LCDC_SEL0                                                          */
+            __IOM uint32_t LCDC_SEL1   : 1; /*!< [7..7] LCDC_SEL1                                                          */
+            __IOM uint32_t PCIE0_PROT0 : 1; /*!< [8..8] PCIE0_PROT0                                                        */
+            __IOM uint32_t PCIE0_PROT1 : 1; /*!< [9..9] PCIE0_PROT1                                                        */
+            __IOM uint32_t PCIE0_SEL0  : 1; /*!< [10..10] PCIE0_SEL0                                                       */
+            __IOM uint32_t PCIE0_SEL1  : 1; /*!< [11..11] PCIE0_SEL1                                                       */
+            __IOM uint32_t PCIE1_PROT0 : 1; /*!< [12..12] PCIE1_PROT0                                                      */
+            __IOM uint32_t PCIE1_PROT1 : 1; /*!< [13..13] PCIE1_PROT1                                                      */
+            __IOM uint32_t PCIE1_SEL0  : 1; /*!< [14..14] PCIE1_SEL0                                                       */
+            __IOM uint32_t PCIE1_SEL1  : 1; /*!< [15..15] PCIE1_SEL1                                                       */
+            __IOM uint32_t SDHI0_PROT0 : 1; /*!< [16..16] SDHI0_PROT0                                                      */
+            __IOM uint32_t SDHI0_PROT1 : 1; /*!< [17..17] SDHI0_PROT1                                                      */
+            __IOM uint32_t SDHI0_SEL0  : 1; /*!< [18..18] SDHI0_SEL0                                                       */
+            __IOM uint32_t SDHI0_SEL1  : 1; /*!< [19..19] SDHI0_SEL1                                                       */
+            __IOM uint32_t SDHI1_PROT0 : 1; /*!< [20..20] SDHI1_PROT0                                                      */
+            __IOM uint32_t SDHI1_PROT1 : 1; /*!< [21..21] SDHI1_PROT1                                                      */
+            __IOM uint32_t SDHI1_SEL0  : 1; /*!< [22..22] SDHI1_SEL0                                                       */
+            __IOM uint32_t SDHI1_SEL1  : 1; /*!< [23..23] SDHI1_SEL1                                                       */
+            __IOM uint32_t GMAC1_PROT0 : 1; /*!< [24..24] GMAC1_PROT0                                                      */
+            __IOM uint32_t GMAC1_PROT1 : 1; /*!< [25..25] GMAC1_PROT1                                                      */
+            __IOM uint32_t GMAC1_SEL0  : 1; /*!< [26..26] GMAC1_SEL0                                                       */
+            __IOM uint32_t GMAC1_SEL1  : 1; /*!< [27..27] GMAC1_SEL1                                                       */
+            __IOM uint32_t GMAC2_PROT0 : 1; /*!< [28..28] GMAC2_PROT0                                                      */
+            __IOM uint32_t GMAC2_PROT1 : 1; /*!< [29..29] GMAC2_PROT1                                                      */
+            __IOM uint32_t GMAC2_SEL0  : 1; /*!< [30..30] GMAC2_SEL0                                                       */
+            __IOM uint32_t GMAC2_SEL1x : 1; /*!< [31..31] GMAC2_SEL1x                                                      */
+        } MSTACCCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTACCCTL1;        /*!< (@ 0x00001004) Master Access Control Register 1                           */
+
+        struct
+        {
+            __IOM uint32_t USB_PROT0 : 1; /*!< [0..0] USB_PROT0                                                          */
+            __IOM uint32_t USB_PROT1 : 1; /*!< [1..1] USB_PROT1                                                          */
+            uint32_t                 : 1;
+            __IOM uint32_t USB_SEL   : 1; /*!< [3..3] USB_SEL                                                            */
+            uint32_t                 : 28;
+        } MSTACCCTL1_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL0;       /*!< (@ 0x00001010) Slave Access Control Register 0                            */
+
+        struct
+        {
+            __IOM uint32_t CMT0_SL  : 2; /*!< [1..0] CMT0_SL                                                            */
+            __IOM uint32_t CMT1_SL  : 2; /*!< [3..2] CMT1_SL                                                            */
+            __IOM uint32_t CMT2_SL  : 2; /*!< [5..4] CMT2_SL                                                            */
+            __IOM uint32_t CMTW0_SL : 2; /*!< [7..6] CMTW0_SL                                                           */
+            __IOM uint32_t CMTW1_SL : 2; /*!< [9..8] CMTW1_SL                                                           */
+            uint32_t                : 2;
+            __IOM uint32_t GPT09_SL : 2; /*!< [13..12] GPT09_SL                                                         */
+            __IOM uint32_t POEG1_SL : 2; /*!< [15..14] POEG1_SL                                                         */
+            __IOM uint32_t WDT0_SL  : 2; /*!< [17..16] WDT0_SL                                                          */
+            __IOM uint32_t WDT1_SL  : 2; /*!< [19..18] WDT1_SL                                                          */
+            __IOM uint32_t WDT2_SL  : 2; /*!< [21..20] WDT2_SL                                                          */
+            __IOM uint32_t WDT3_SL  : 2; /*!< [23..22] WDT3_SL                                                          */
+            __IOM uint32_t WDT4_SL  : 2; /*!< [25..24] WDT4_SL                                                          */
+            __IOM uint32_t WDT5_SL  : 2; /*!< [27..26] WDT5_SL                                                          */
+            uint32_t                : 2;
+            __IOM uint32_t ADC2_SL  : 2; /*!< [31..30] ADC2_SL                                                          */
+        } SLVACCCTL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL1;       /*!< (@ 0x00001014) Slave Access Control Register 1                            */
+
+        struct
+        {
+            __IOM uint32_t SCI0_SL  : 2; /*!< [1..0] SCI0_SL                                                            */
+            __IOM uint32_t SCI1_SL  : 2; /*!< [3..2] SCI1_SL                                                            */
+            __IOM uint32_t SCI2_SL  : 2; /*!< [5..4] SCI2_SL                                                            */
+            __IOM uint32_t SCI3_SL  : 2; /*!< [7..6] SCI3_SL                                                            */
+            __IOM uint32_t SCI4_SL  : 2; /*!< [9..8] SCI4_SL                                                            */
+            uint32_t                : 2;
+            __IOM uint32_t IIC0_SL  : 2; /*!< [13..12] IIC0_SL                                                          */
+            __IOM uint32_t IIC1_SL  : 2; /*!< [15..14] IIC1_SL                                                          */
+            __IOM uint32_t SPI0_SL  : 2; /*!< [17..16] SPI0_SL                                                          */
+            __IOM uint32_t SPI1_SL  : 2; /*!< [19..18] SPI1_SL                                                          */
+            __IOM uint32_t SPI2_SL  : 2; /*!< [21..20] SPI2_SL                                                          */
+            uint32_t                : 2;
+            __IOM uint32_t CANFD_SL : 2; /*!< [25..24] CANFD_SL                                                         */
+            __IOM uint32_t DOC_SL   : 2; /*!< [27..26] DOC_SL                                                           */
+            __IOM uint32_t CRC0_SL  : 2; /*!< [29..28] CRC0_SL                                                          */
+            __IOM uint32_t TSU_SL   : 2; /*!< [31..30] TSU_SL                                                           */
+        } SLVACCCTL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL2;       /*!< (@ 0x00001018) Slave Access Control Register 2                            */
+
+        struct
+        {
+            __IOM uint32_t GPT10_SL : 2; /*!< [1..0] GPT10_SL                                                           */
+            __IOM uint32_t POEG2_SL : 2; /*!< [3..2] POEG2_SL                                                           */
+            uint32_t                : 4;
+            __IOM uint32_t RTC_SL   : 2; /*!< [9..8] RTC_SL                                                             */
+            __IOM uint32_t CRC1_SL  : 2; /*!< [11..10] CRC1_SL                                                          */
+            uint32_t                : 4;
+            __IOM uint32_t SCI5_SL  : 2; /*!< [17..16] SCI5_SL                                                          */
+            __IOM uint32_t IIC2_SL  : 2; /*!< [19..18] IIC2_SL                                                          */
+            __IOM uint32_t SPI3_SL  : 2; /*!< [21..20] SPI3_SL                                                          */
+            uint32_t                : 10;
+        } SLVACCCTL2_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL4;       /*!< (@ 0x00001020) Slave Access Control Register 4                            */
+
+        struct
+        {
+            __IOM uint32_t USB_SL   : 2; /*!< [1..0] USB_SL                                                             */
+            uint32_t                : 6;
+            __IOM uint32_t LCDC_SL  : 2; /*!< [9..8] LCDC_SL                                                            */
+            uint32_t                : 6;
+            __IOM uint32_t SDHI0_SL : 2; /*!< [17..16] SDHI0_SL                                                         */
+            __IOM uint32_t SDHI1_SL : 2; /*!< [19..18] SDHI1_SL                                                         */
+            uint32_t                : 4;
+            __IOM uint32_t GMAC1_SL : 2; /*!< [25..24] GMAC1_SL                                                         */
+            __IOM uint32_t GMAC2_SL : 2; /*!< [27..26] GMAC2_SL                                                         */
+            uint32_t                : 4;
+        } SLVACCCTL4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SLVACCCTL5;            /*!< (@ 0x00001024) Slave Access Control Register 5                            */
+
+        struct
+        {
+            __IOM uint32_t TZCDDRA0A1_SL : 2; /*!< [1..0] TZCDDRA0A1_SL                                                      */
+            __IOM uint32_t TZCDDRA4_SL   : 2; /*!< [3..2] TZCDDRA4_SL                                                        */
+            __IOM uint32_t TZCPCIE_SL    : 2; /*!< [5..4] TZCPCIE_SL                                                         */
+            uint32_t                     : 10;
+            __IOM uint32_t MPUUSB_SL     : 2; /*!< [17..16] MPUUSB_SL                                                        */
+            __IOM uint32_t MPUPCIE0_SL   : 2; /*!< [19..18] MPUPCIE0_SL                                                      */
+            __IOM uint32_t MPUPCIE1_SL   : 2; /*!< [21..20] MPUPCIE1_SL                                                      */
+            __IOM uint32_t MPULCDC_SL    : 2; /*!< [23..22] MPULCDC_SL                                                       */
+            __IOM uint32_t MPUSDHI0_SL   : 2; /*!< [25..24] MPUSDHI0_SL                                                      */
+            __IOM uint32_t MPUSDHI1_SL   : 2; /*!< [27..26] MPUSDHI1_SL                                                      */
+            __IOM uint32_t MPUGMAC1_SL   : 2; /*!< [29..28] MPUGMAC1_SL                                                      */
+            __IOM uint32_t MPUGMAC2_SL   : 2; /*!< [31..30] MPUGMAC2_SL                                                      */
+        } SLVACCCTL5_b;
+    };
+} R_MSAC_Type;                                /*!< Size = 4136 (0x1028)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MPU10                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Master MPU 10 (R_MPU10)
+ */
+
+typedef struct                           /*!< (@ 0x81290400) R_MPU10 Structure                                          */
+{
+    __IOM R_MPU10_RGN_Type RGN[16];      /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register
+                                          *                  [0..15]                                                    */
+
+    union
+    {
+        __IOM uint32_t ERRINF_R;         /*!< (@ 0x00000080) Master MPU Error Information Register for AXI
+                                          *                  type                                                       */
+
+        struct
+        {
+            __IOM uint32_t VALID   : 1;  /*!< [0..0] Cleared to 0 when 0 is written.                                    */
+            __IM uint32_t  RW      : 1;  /*!< [1..1] RW                                                                 */
+            __IM uint32_t  ERRADDR : 30; /*!< [31..2] Access error address                                              */
+        } ERRINF_R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ERRINF_W;         /*!< (@ 0x00000084) Master MPU Error Information Register for AXI
+                                          *                  type                                                       */
+
+        struct
+        {
+            __IOM uint32_t VALID   : 1;  /*!< [0..0] Cleared to 0 when 0 is written.                                    */
+            __IM uint32_t  RW      : 1;  /*!< [1..1] RW                                                                 */
+            __IM uint32_t  ERRADDR : 30; /*!< [31..2] Access error address                                              */
+        } ERRINF_W_b;
+    };
+} R_MPU10_Type;                          /*!< Size = 136 (0x88)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADXC1                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Address Expander Control 1 (R_ADXC1)
+ */
+
+typedef struct                         /*!< (@ 0x81291100) R_ADXC1 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t ADXCTL6;        /*!< (@ 0x00000000) Address Expander Control Register 6                        */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t DDRMIR0 : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t               : 3;
+            __IOM uint32_t DDRMIR1 : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t               : 3;
+        } ADXCTL6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL7;        /*!< (@ 0x00000004) Address Expander Control Register 7                        */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t DDRMIR0 : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t               : 3;
+            __IOM uint32_t DDRMIR1 : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t               : 3;
+        } ADXCTL7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL8;        /*!< (@ 0x00000008) Address Expander Control Register 8                        */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t DDRMIR0 : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t               : 3;
+            __IOM uint32_t DDRMIR1 : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t               : 3;
+        } ADXCTL8_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL9;        /*!< (@ 0x0000000C) Address Expander Control Register 9                        */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t DDRMIR0 : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t               : 3;
+            __IOM uint32_t DDRMIR1 : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t               : 3;
+        } ADXCTL9_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL10;       /*!< (@ 0x00000010) Address Expander Control Register 10                       */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t DDRMIR0 : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t               : 3;
+            __IOM uint32_t DDRMIR1 : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t               : 3;
+        } ADXCTL10_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL11;       /*!< (@ 0x00000014) Address Expander Control Register 11                       */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t DDRMIR0 : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t               : 3;
+            __IOM uint32_t DDRMIR1 : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t               : 3;
+        } ADXCTL11_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ADXCTL12;       /*!< (@ 0x00000018) Address Expander Control Register 12                       */
+
+        struct
+        {
+            uint32_t               : 16;
+            __IOM uint32_t DDRMIR0 : 5; /*!< [20..16] DDR Mirror Address 0                                             */
+            uint32_t               : 3;
+            __IOM uint32_t DDRMIR1 : 5; /*!< [28..24] DDR Mirror Address 1                                             */
+            uint32_t               : 3;
+        } ADXCTL12_b;
+    };
+} R_ADXC1_Type;                         /*!< Size = 28 (0x1c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                       R_SYSRAM_CTL                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System SRAM Control (R_SYSRAM_CTL)
+ */
+
+typedef struct                              /*!< (@ 0x81293000) R_SYSRAM_CTL Structure                                     */
+{
+    union
+    {
+        __IOM uint32_t SYSRAM_CTRL0;        /*!< (@ 0x00000000) System SRAM Control Register 0                             */
+
+        struct
+        {
+            __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
+            uint32_t                   : 15;
+            __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
+            __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
+            __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
+            uint32_t                   : 2;
+            __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
+            uint32_t                   : 7;
+        } SYSRAM_CTRL0_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t SYSRAM_CTRL1;        /*!< (@ 0x00000010) System SRAM Control Register 1                             */
+
+        struct
+        {
+            __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
+            uint32_t                   : 15;
+            __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
+            __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
+            __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
+            uint32_t                   : 2;
+            __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
+            uint32_t                   : 7;
+        } SYSRAM_CTRL1_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint32_t SYSRAM_CTRL2;        /*!< (@ 0x00000020) System SRAM Control Register 2                             */
+
+        struct
+        {
+            __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
+            uint32_t                   : 15;
+            __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
+            __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
+            __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
+            uint32_t                   : 2;
+            __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
+            uint32_t                   : 7;
+        } SYSRAM_CTRL2_b;
+    };
+    __IM uint32_t RESERVED2[3];
+
+    union
+    {
+        __IOM uint32_t SYSRAM_CTRL3;        /*!< (@ 0x00000030) System SRAM Control Register 3                             */
+
+        struct
+        {
+            __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
+            uint32_t                   : 15;
+            __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
+            __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
+            __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
+            uint32_t                   : 2;
+            __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
+            uint32_t                   : 7;
+        } SYSRAM_CTRL3_b;
+    };
+} R_SYSRAM_CTL_Type;                        /*!< Size = 52 (0x34)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                       R_SHOSTIF_CFG                                       ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_SHOSTIF_CFG (R_SHOSTIF_CFG)
+ */
+
+typedef struct                             /*!< (@ 0x81294000) R_SHOSTIF_CFG Structure                                    */
+{
+    union
+    {
+        __IOM uint32_t SHCFG;              /*!< (@ 0x00000000) SHCFG                                                      */
+
+        struct
+        {
+            __IOM uint32_t SPIMODE    : 2; /*!< [1..0] SPIMODE                                                            */
+            __IOM uint32_t BYTESWAP   : 1; /*!< [2..2] BYTESWAP                                                           */
+            __IOM uint32_t ADDRESSING : 1; /*!< [3..3] ADDRESSING                                                         */
+            __IM uint32_t  SLEEP      : 1; /*!< [4..4] SLEEP                                                              */
+            uint32_t                  : 11;
+            __IOM uint32_t INTMASKI   : 6; /*!< [21..16] INTMASKI                                                         */
+            uint32_t                  : 2;
+            __IOM uint32_t INTMASKE   : 6; /*!< [29..24] INTMASKE                                                         */
+            uint32_t                  : 2;
+        } SHCFG_b;
+    };
+} R_SHOSTIF_CFG_Type;                      /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_TCMAW                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief TCM access wait state (R_TCMAW)
+ */
+
+typedef struct                         /*!< (@ 0x81295000) R_TCMAW Structure                                          */
+{
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IM uint32_t CPU0WAIT;         /*!< (@ 0x00000008) CPU0 ATCM Wait State Register                              */
+
+        struct
+        {
+            __IM uint32_t CPU0WAIT : 1; /*!< [0..0] ATCM Wait state                                                    */
+            uint32_t               : 31;
+        } CPU0WAIT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CPU1WAIT;         /*!< (@ 0x0000000C) CPU1 ATCM Wait State Register                              */
+
+        struct
+        {
+            __IM uint32_t CPU1WAIT : 1; /*!< [0..0] CPU1WAIT                                                           */
+            uint32_t               : 31;
+        } CPU1WAIT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CPU1HALT;         /*!< (@ 0x00000010) CPU1 HALT Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t CPU1HALT : 1; /*!< [0..0] CPU1HALT                                                           */
+            uint32_t                : 31;
+        } CPU1HALT_b;
+    };
+} R_TCMAW_Type;                          /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CA55                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Cortex-A55 (R_CA55)
+ */
+
+typedef struct                         /*!< (@ 0x81295020) R_CA55 Structure                                           */
+{
+    __IOM R_CA55_RVBA_Type RVBA[4];    /*!< (@ 0x00000000) CA55 Core [0..3] Reset Vector Address Configuration
+                                        *                  Register                                                   */
+} R_CA55_Type;                         /*!< Size = 32 (0x20)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_WDT_DBG                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief WDT for Debug (R_WDT_DBG)
+ */
+
+typedef struct                              /*!< (@ 0x81295100) R_WDT_DBG Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t WDTDCR[6];           /*!< (@ 0x00000000) WDT Debug Control Register m (m = 0 to 5)                  */
+
+        struct
+        {
+            __IOM uint32_t WDTSTOPCTRL : 1; /*!< [0..0] WDTSTOPCTRL                                                        */
+            uint32_t                   : 15;
+            __IOM uint32_t WDTSTOPMASK : 1; /*!< [16..16] WDTSTOPMASK                                                      */
+            uint32_t                   : 15;
+        } WDTDCR_b[6];
+    };
+} R_WDT_DBG_Type;                           /*!< Size = 24 (0x18)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_RWP_S                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Register Write Protection for Safety Area (R_RWP_S)
+ */
+
+typedef struct                         /*!< (@ 0x81296000) R_RWP_S Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t PRCRS;          /*!< (@ 0x00000000) Safety Area Protect Register                               */
+
+        struct
+        {
+            __IOM uint32_t PRC0 : 1;   /*!< [0..0] Protect 0                                                          */
+            __IOM uint32_t PRC1 : 1;   /*!< [1..1] Protect 1                                                          */
+            __IOM uint32_t PRC2 : 1;   /*!< [2..2] Protect 2                                                          */
+            __IOM uint32_t PRC3 : 1;   /*!< [3..3] Protect 3                                                          */
+            uint32_t            : 4;
+            __OM uint32_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
+            uint32_t            : 16;
+        } PRCRS_b;
+    };
+} R_RWP_S_Type;                        /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ICU_S                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Controller in Safety Domain (R_ICU_S)
+ */
+
+typedef struct                         /*!< (@ 0x812A0000) R_ICU_S Structure                                          */
+{
+    union
+    {
+        __OM uint32_t S_SWINT;         /*!< (@ 0x00000000) Software Interrupt Register for Safety Register            */
+
+        struct
+        {
+            __OM uint32_t IC14 : 1;    /*!< [0..0] Software Interrupt register                                        */
+            __OM uint32_t IC15 : 1;    /*!< [1..1] Software Interrupt register                                        */
+            uint32_t           : 30;
+        } S_SWINT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t S_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register for Safety
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t FLT14  : 1;  /*!< [0..0] Noise filter enable for IRQ14                                      */
+            __IOM uint32_t FLT15  : 1;  /*!< [1..1] Noise filter enable for IRQ15                                      */
+            __IOM uint32_t FLTSEI : 1;  /*!< [2..2] Noise filter enable for SEI                                        */
+            uint32_t              : 29;
+        } S_PORTNF_FLTSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t S_PORTNF_CLKSEL;   /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register for Safety
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t CKSEL14 : 2;   /*!< [1..0] Select noise filter sampling frequency dividend rate
+                                           *   for IRQ14.                                                                */
+            __IOM uint32_t CKSEL15 : 2;   /*!< [3..2] Select noise filter sampling frequency dividend rate
+                                           *   for IRQ15.                                                                */
+            __IOM uint32_t CLKSELSEI : 2; /*!< [5..4] Select noise filter sampling frequency dividend rate
+                                           *   for SEI.                                                                  */
+            uint32_t : 26;
+        } S_PORTNF_CLKSEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t S_PORTNF_MD;    /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register for
+                                        *                  Safety Register                                            */
+
+        struct
+        {
+            __IOM uint32_t MD14  : 2;  /*!< [1..0] Select detection mode for IRQ14                                    */
+            __IOM uint32_t MD15  : 2;  /*!< [3..2] Select detection mode for IRQ15                                    */
+            __IOM uint32_t MDSEI : 2;  /*!< [5..4] Select detection mode for SEI                                      */
+            uint32_t             : 26;
+        } S_PORTNF_MD_b;
+    };
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint32_t S_GPT_INTSEL[2];   /*!< (@ 0x00000020) Safety GPT Interrupt Select Register n (n = 0
+                                           *                  to 1)                                                      */
+
+        struct
+        {
+            __IOM uint32_t INTSELX_0 : 4; /*!< [3..0] INTSELX_0                                                          */
+            __IOM uint32_t INTSELX_1 : 4; /*!< [7..4] Select GPT event source to be output as GPTx_INT1 event            */
+            __IOM uint32_t INTSELX_2 : 4; /*!< [11..8] Select GPT event source to be output as GPTx_INT2 event           */
+            __IOM uint32_t INTSELX_3 : 4; /*!< [15..12] Select GPT event source to be output as GPTx_INT3 event          */
+            __IOM uint32_t INTSELY_0 : 4; /*!< [19..16] Select GPT event source to be output as GPTy_INT0 event          */
+            __IOM uint32_t INTSELY_1 : 4; /*!< [23..20] Select GPT event source to be output as GPTy_INT1 event          */
+            __IOM uint32_t INTSELY_2 : 4; /*!< [27..24] Select GPT event source to be output as GPTy_INT2 event          */
+            __IOM uint32_t INTSELY_3 : 4; /*!< [31..28] Select GPT event source to be output as GPTy_INT3 event          */
+        } S_GPT_INTSEL_b[2];
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t S_GPT_INTMSK[2]; /*!< (@ 0x00000030) Safety GPT Combined Interrupt Mask Register n
+                                         *                  (n = 0 to 1)                                               */
+
+        struct
+        {
+            __IOM uint32_t IX_MK0 : 1;  /*!< [0..0] IX_MK0                                                             */
+            __IOM uint32_t IX_MK1 : 1;  /*!< [1..1] IX_MK1                                                             */
+            __IOM uint32_t IX_MK2 : 1;  /*!< [2..2] IX_MK2                                                             */
+            __IOM uint32_t IX_MK3 : 1;  /*!< [3..3] IX_MK3                                                             */
+            __IOM uint32_t IX_MK4 : 1;  /*!< [4..4] IX_MK4                                                             */
+            __IOM uint32_t IX_MK5 : 1;  /*!< [5..5] IX_MK5                                                             */
+            __IOM uint32_t IX_MK6 : 1;  /*!< [6..6] IX_MK6                                                             */
+            __IOM uint32_t IX_MK7 : 1;  /*!< [7..7] IX_MK7                                                             */
+            uint32_t              : 8;
+            __IOM uint32_t IY_MK0 : 1;  /*!< [16..16] IY_MK0                                                           */
+            __IOM uint32_t IY_MK1 : 1;  /*!< [17..17] IY_MK1                                                           */
+            __IOM uint32_t IY_MK2 : 1;  /*!< [18..18] IY_MK2                                                           */
+            __IOM uint32_t IY_MK3 : 1;  /*!< [19..19] IY_MK3                                                           */
+            __IOM uint32_t IY_MK4 : 1;  /*!< [20..20] IY_MK4                                                           */
+            __IOM uint32_t IY_MK5 : 1;  /*!< [21..21] IY_MK5                                                           */
+            __IOM uint32_t IY_MK6 : 1;  /*!< [22..22] IY_MK6                                                           */
+            __IOM uint32_t IY_MK7 : 1;  /*!< [23..23] IY_MK7                                                           */
+            uint32_t              : 8;
+        } S_GPT_INTMSK_b[2];
+    };
+
+    union
+    {
+        __OM uint32_t S_GPT_INTCLR[2]; /*!< (@ 0x00000038) Safety GPT Combined Interrupt Status Clear Register
+                                        *                  n (n = 0 to 1)                                             */
+
+        struct
+        {
+            __OM uint32_t IX_CL0 : 1;  /*!< [0..0] IX_CL0                                                             */
+            __OM uint32_t IX_CL1 : 1;  /*!< [1..1] IX_CL1                                                             */
+            __OM uint32_t IX_CL2 : 1;  /*!< [2..2] IX_CL2                                                             */
+            __OM uint32_t IX_CL3 : 1;  /*!< [3..3] IX_CL3                                                             */
+            __OM uint32_t IX_CL4 : 1;  /*!< [4..4] IX_CL4                                                             */
+            __OM uint32_t IX_CL5 : 1;  /*!< [5..5] IX_CL5                                                             */
+            __OM uint32_t IX_CL6 : 1;  /*!< [6..6] IX_CL6                                                             */
+            __OM uint32_t IX_CL7 : 1;  /*!< [7..7] IX_CL7                                                             */
+            uint32_t             : 8;
+            __OM uint32_t IY_CL0 : 1;  /*!< [16..16] IY_CL0                                                           */
+            __OM uint32_t IY_CL1 : 1;  /*!< [17..17] IY_CL1                                                           */
+            __OM uint32_t IY_CL2 : 1;  /*!< [18..18] IY_CL2                                                           */
+            __OM uint32_t IY_CL3 : 1;  /*!< [19..19] IY_CL3                                                           */
+            __OM uint32_t IY_CL4 : 1;  /*!< [20..20] IY_CL4                                                           */
+            __OM uint32_t IY_CL5 : 1;  /*!< [21..21] IY_CL5                                                           */
+            __OM uint32_t IY_CL6 : 1;  /*!< [22..22] IY_CL6                                                           */
+            __OM uint32_t IY_CL7 : 1;  /*!< [23..23] IY_CL7                                                           */
+            uint32_t             : 8;
+        } S_GPT_INTCLR_b[2];
+    };
+
+    union
+    {
+        __IM uint32_t S_GPT_INTSTAT[2]; /*!< (@ 0x00000040) Safety GPT Combined Interrupt Status Register
+                                         *                  n (n = 0 to 1)                                             */
+
+        struct
+        {
+            __IM uint32_t IX_ST0 : 1;   /*!< [0..0] IX_ST0                                                             */
+            __IM uint32_t IX_ST1 : 1;   /*!< [1..1] IX_ST1                                                             */
+            __IM uint32_t IX_ST2 : 1;   /*!< [2..2] IX_ST2                                                             */
+            __IM uint32_t IX_ST3 : 1;   /*!< [3..3] IX_ST3                                                             */
+            __IM uint32_t IX_ST4 : 1;   /*!< [4..4] IX_ST4                                                             */
+            __IM uint32_t IX_ST5 : 1;   /*!< [5..5] IX_ST5                                                             */
+            __IM uint32_t IX_ST6 : 1;   /*!< [6..6] IX_ST6                                                             */
+            __IM uint32_t IX_ST7 : 1;   /*!< [7..7] IX_ST7                                                             */
+            uint32_t             : 8;
+            __IM uint32_t IY_ST0 : 1;   /*!< [16..16] IY_ST0                                                           */
+            __IM uint32_t IY_ST1 : 1;   /*!< [17..17] IY_ST1                                                           */
+            __IM uint32_t IY_ST2 : 1;   /*!< [18..18] IY_ST2                                                           */
+            __IM uint32_t IY_ST3 : 1;   /*!< [19..19] IY_ST3                                                           */
+            __IM uint32_t IY_ST4 : 1;   /*!< [20..20] IY_ST4                                                           */
+            __IM uint32_t IY_ST5 : 1;   /*!< [21..21] IY_ST5                                                           */
+            __IM uint32_t IY_ST6 : 1;   /*!< [22..22] IY_ST6                                                           */
+            __IM uint32_t IY_ST7 : 1;   /*!< [23..23] IY_ST7                                                           */
+            uint32_t             : 8;
+        } S_GPT_INTSTAT_b[2];
+    };
+} R_ICU_S_Type;                         /*!< Size = 72 (0x48)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_GSC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Global System Counter (R_GSC)
+ */
+
+typedef struct                         /*!< (@ 0x8C200000) R_GSC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t CNTCR;          /*!< (@ 0x00000000) Global System Counter Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t EN   : 1;   /*!< [0..0] Counter Enable                                                     */
+            __IOM uint32_t HDBG : 1;   /*!< [1..1] Halt on Debug                                                      */
+            uint32_t            : 30;
+        } CNTCR_b;
+    };
+
+    union
+    {
+        __IM uint32_t CNTSR;           /*!< (@ 0x00000004) Global System Counter Status Register                      */
+
+        struct
+        {
+            uint32_t           : 1;
+            __IM uint32_t DBGH : 1;    /*!< [1..1] Debug Halted                                                       */
+            uint32_t           : 30;
+        } CNTSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CNTCVL;               /*!< (@ 0x00000008) Global System Counter Current Value Lower Register         */
+
+        struct
+        {
+            __IOM uint32_t CNTCVL_L_32 : 32; /*!< [31..0] Current value of the counter, lower 32 bits                       */
+        } CNTCVL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CNTCVU;               /*!< (@ 0x0000000C) Global System Counter Current Value Upper Register         */
+
+        struct
+        {
+            __IOM uint32_t CNTCVU_U_32 : 32; /*!< [31..0] Current value of the counter, upper 32 bits                       */
+        } CNTCVU_b;
+    };
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint32_t CNTFID0;        /*!< (@ 0x00000020) Global System Counter Base Frequency ID Register           */
+
+        struct
+        {
+            __IOM uint32_t FREQ : 32;  /*!< [31..0] Frequency in number of ticks per second                           */
+        } CNTFID0_b;
+    };
+} R_GSC_Type;                          /*!< Size = 36 (0x24)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_MTU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit (R_MTU)
+ */
+
+typedef struct                         /*!< (@ 0x90001000) R_MTU Structure                                            */
+{
+    __IM uint16_t RESERVED[261];
+
+    union
+    {
+        __IOM uint8_t TOERA;           /*!< (@ 0x0000020A) Timer Output Master Enable Register A                      */
+
+        struct
+        {
+            __IOM uint8_t OE3B : 1;    /*!< [0..0] Master Enable MTIOC3B                                              */
+            __IOM uint8_t OE4A : 1;    /*!< [1..1] Master Enable MTIOC4A                                              */
+            __IOM uint8_t OE4B : 1;    /*!< [2..2] Master Enable MTIOC4B                                              */
+            __IOM uint8_t OE3D : 1;    /*!< [3..3] Master Enable MTIOC3D                                              */
+            __IOM uint8_t OE4C : 1;    /*!< [4..4] Master Enable MTIOC4C                                              */
+            __IOM uint8_t OE4D : 1;    /*!< [5..5] Master Enable MTIOC4D                                              */
+            uint8_t            : 2;
+        } TOERA_b;
+    };
+    __IM uint8_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint8_t TGCRA;           /*!< (@ 0x0000020D) Timer Gate Control Register A                              */
+
+        struct
+        {
+            __IOM uint8_t UF  : 1;     /*!< [0..0] Output Phase Switch                                                */
+            __IOM uint8_t VF  : 1;     /*!< [1..1] Output Phase Switch                                                */
+            __IOM uint8_t WF  : 1;     /*!< [2..2] Output Phase Switch                                                */
+            __IOM uint8_t FB  : 1;     /*!< [3..3] External Feedback Signal Enable                                    */
+            __IOM uint8_t P   : 1;     /*!< [4..4] Positive-Phase Output (P) Control                                  */
+            __IOM uint8_t N   : 1;     /*!< [5..5] Negative-Phase Output (N) Control                                  */
+            __IOM uint8_t BDC : 1;     /*!< [6..6] Brushless DC Motor                                                 */
+            uint8_t           : 1;
+        } TGCRA_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TOCR1A;          /*!< (@ 0x0000020E) Timer Output Control Register 1A                           */
+
+        struct
+        {
+            __IOM uint8_t OLSP : 1;    /*!< [0..0] Output Level Select P                                              */
+            __IOM uint8_t OLSN : 1;    /*!< [1..1] Output Level Select N                                              */
+            __IOM uint8_t TOCS : 1;    /*!< [2..2] TOC Select                                                         */
+            __IOM uint8_t TOCL : 1;    /*!< [3..3] TOC Register Write Protection                                      */
+            uint8_t            : 2;
+            __IOM uint8_t PSYE : 1;    /*!< [6..6] PWM Synchronous Output Enable                                      */
+            uint8_t            : 1;
+        } TOCR1A_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TOCR2A;          /*!< (@ 0x0000020F) Timer Output Control Register 2A                           */
+
+        struct
+        {
+            __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
+            __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
+            __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
+            __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
+            __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
+            __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
+            __IOM uint8_t BF    : 2;   /*!< [7..6] TOLBR Buffer Transfer Timing Select                                */
+        } TOCR2A_b;
+    };
+    __IM uint16_t  RESERVED2[2];
+    __IOM uint16_t TCDRA;              /*!< (@ 0x00000214) Timer Cycle Data Register A                                */
+    __IOM uint16_t TDDRA;              /*!< (@ 0x00000216) Timer Dead Time Data Register A                            */
+    __IM uint16_t  RESERVED3[4];
+    __IM uint16_t  TCNTSA;             /*!< (@ 0x00000220) Timer Subcounter A                                         */
+    __IOM uint16_t TCBRA;              /*!< (@ 0x00000222) Timer Cycle Buffer Register A                              */
+    __IM uint16_t  RESERVED4[6];
+
+    union
+    {
+        __IOM uint8_t TITCR1A;         /*!< (@ 0x00000230) Timer Interrupt Skipping Set Register 1A                   */
+
+        struct
+        {
+            __IOM uint8_t T4VCOR : 3;  /*!< [2..0] TCIV4 Interrupt Skipping Count Setting                             */
+            __IOM uint8_t T4VEN  : 1;  /*!< [3..3] TCIV4 Interrupt Skipping Enable                                    */
+            __IOM uint8_t T3ACOR : 3;  /*!< [6..4] TGIA3 Interrupt Skipping Count Setting                             */
+            __IOM uint8_t T3AEN  : 1;  /*!< [7..7] TGIA3 Interrupt Skipping Enable                                    */
+        } TITCR1A_b;
+    };
+
+    union
+    {
+        __IM uint8_t TITCNT1A;         /*!< (@ 0x00000231) Timer Interrupt Skipping Counter 1A                        */
+
+        struct
+        {
+            __IM uint8_t T4VCNT : 3;   /*!< [2..0] TCIV4 Interrupt Counter                                            */
+            uint8_t             : 1;
+            __IM uint8_t T3ACNT : 3;   /*!< [6..4] TGIA3 Interrupt Counter                                            */
+            uint8_t             : 1;
+        } TITCNT1A_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TBTERA;          /*!< (@ 0x00000232) Timer Buffer Transfer Set Register A                       */
+
+        struct
+        {
+            __IOM uint8_t BTE : 2;     /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting        */
+            uint8_t           : 6;
+        } TBTERA_b;
+    };
+    __IM uint8_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t TDERA;           /*!< (@ 0x00000234) Timer Dead Time Enable Register A                          */
+
+        struct
+        {
+            __IOM uint8_t TDER : 1;    /*!< [0..0] Dead Time Enable                                                   */
+            uint8_t            : 7;
+        } TDERA_b;
+    };
+    __IM uint8_t RESERVED6;
+
+    union
+    {
+        __IOM uint8_t TOLBRA;          /*!< (@ 0x00000236) Timer Output Level Buffer Register A                       */
+
+        struct
+        {
+            __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
+            __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
+            __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
+            __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
+            __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
+            __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
+            uint8_t             : 2;
+        } TOLBRA_b;
+    };
+    __IM uint8_t  RESERVED7;
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IOM uint8_t TITMRA;          /*!< (@ 0x0000023A) Timer Interrupt Skipping Mode Register A                   */
+
+        struct
+        {
+            __IOM uint8_t TITM : 1;    /*!< [0..0] Interrupt Skipping Function Select                                 */
+            uint8_t            : 7;
+        } TITMRA_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TITCR2A;         /*!< (@ 0x0000023B) Timer Interrupt Skipping Set Register 2A                   */
+
+        struct
+        {
+            __IOM uint8_t TRG4COR : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Skipping Count Setting                     */
+            uint8_t               : 5;
+        } TITCR2A_b;
+    };
+
+    union
+    {
+        __IM uint8_t TITCNT2A;         /*!< (@ 0x0000023C) Timer Interrupt Skipping Counter 2A                        */
+
+        struct
+        {
+            __IM uint8_t TRG4CNT : 3;  /*!< [2..0] TRG4AN/TRG4BN Interrupt Counter                                    */
+            uint8_t              : 5;
+        } TITCNT2A_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10[17];
+
+    union
+    {
+        __IOM uint8_t TWCRA;           /*!< (@ 0x00000260) Timer Waveform Control Register A                          */
+
+        struct
+        {
+            __IOM uint8_t WRE : 1;     /*!< [0..0] Waveform Retain Enable                                             */
+            __IOM uint8_t SCC : 1;     /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB)                 */
+            uint8_t           : 5;
+            __IOM uint8_t CCE : 1;     /*!< [7..7] Compare Match Clear Enable                                         */
+        } TWCRA_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12[7];
+
+    union
+    {
+        __IOM uint8_t TMDR2A;          /*!< (@ 0x00000270) Timer Mode Register 2A                                     */
+
+        struct
+        {
+            __IOM uint8_t DRS : 1;     /*!< [0..0] Double Buffer Select                                               */
+            uint8_t           : 7;
+        } TMDR2A_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14[7];
+
+    union
+    {
+        __IOM uint8_t TSTRA;           /*!< (@ 0x00000280) Timer Start Register A                                     */
+
+        struct
+        {
+            __IOM uint8_t CST0 : 1;    /*!< [0..0] Counter Start 0                                                    */
+            __IOM uint8_t CST1 : 1;    /*!< [1..1] Counter Start 1                                                    */
+            __IOM uint8_t CST2 : 1;    /*!< [2..2] Counter Start 2                                                    */
+            __IOM uint8_t CST8 : 1;    /*!< [3..3] Counter Start 8                                                    */
+            uint8_t            : 2;
+            __IOM uint8_t CST3 : 1;    /*!< [6..6] Counter Start 3                                                    */
+            __IOM uint8_t CST4 : 1;    /*!< [7..7] Counter Start 4                                                    */
+        } TSTRA_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TSYRA;           /*!< (@ 0x00000281) Timer Synchronous Register A                               */
+
+        struct
+        {
+            __IOM uint8_t SYNC0 : 1;   /*!< [0..0] Timer Synchronous Operation 0                                      */
+            __IOM uint8_t SYNC1 : 1;   /*!< [1..1] Timer Synchronous Operation 1                                      */
+            __IOM uint8_t SYNC2 : 1;   /*!< [2..2] Timer Synchronous Operation 2                                      */
+            uint8_t             : 3;
+            __IOM uint8_t SYNC3 : 1;   /*!< [6..6] Timer Synchronous Operation 3                                      */
+            __IOM uint8_t SYNC4 : 1;   /*!< [7..7] Timer Synchronous Operation 4                                      */
+        } TSYRA_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCSYSTR;         /*!< (@ 0x00000282) Timer Counter Synchronous Start Register                   */
+
+        struct
+        {
+            __IOM uint8_t SCH7 : 1;    /*!< [0..0] Synchronous Start 7                                                */
+            __IOM uint8_t SCH6 : 1;    /*!< [1..1] Synchronous Start 6                                                */
+            uint8_t            : 1;
+            __IOM uint8_t SCH4 : 1;    /*!< [3..3] Synchronous Start 4                                                */
+            __IOM uint8_t SCH3 : 1;    /*!< [4..4] Synchronous Start 3                                                */
+            __IOM uint8_t SCH2 : 1;    /*!< [5..5] Synchronous Start 2                                                */
+            __IOM uint8_t SCH1 : 1;    /*!< [6..6] Synchronous Start 1                                                */
+            __IOM uint8_t SCH0 : 1;    /*!< [7..7] Synchronous Start 0                                                */
+        } TCSYSTR_b;
+    };
+    __IM uint8_t RESERVED15;
+
+    union
+    {
+        __IOM uint8_t TRWERA;          /*!< (@ 0x00000284) Timer Read/Write Enable Register A                         */
+
+        struct
+        {
+            __IOM uint8_t RWE : 1;     /*!< [0..0] Read/Write Enable                                                  */
+            uint8_t           : 7;
+        } TRWERA_b;
+    };
+    __IM uint8_t  RESERVED16;
+    __IM uint16_t RESERVED17[962];
+
+    union
+    {
+        __IOM uint8_t TOERB;           /*!< (@ 0x00000A0A) Timer Output Master Enable Register B                      */
+
+        struct
+        {
+            __IOM uint8_t OE6B : 1;    /*!< [0..0] Master Enable MTIOC6B                                              */
+            __IOM uint8_t OE7A : 1;    /*!< [1..1] Master Enable MTIOC7A                                              */
+            __IOM uint8_t OE7B : 1;    /*!< [2..2] Master Enable MTIOC7B                                              */
+            __IOM uint8_t OE6D : 1;    /*!< [3..3] Master Enable MTIOC6D                                              */
+            __IOM uint8_t OE7C : 1;    /*!< [4..4] Master Enable MTIOC7C                                              */
+            __IOM uint8_t OE7D : 1;    /*!< [5..5] Master Enable MTIOC7D                                              */
+            uint8_t            : 2;
+        } TOERB_b;
+    };
+    __IM uint8_t  RESERVED18;
+    __IM uint16_t RESERVED19;
+
+    union
+    {
+        __IOM uint8_t TOCR1B;          /*!< (@ 0x00000A0E) Timer Output Control Register 1B                           */
+
+        struct
+        {
+            __IOM uint8_t OLSP : 1;    /*!< [0..0] Output Level Select P                                              */
+            __IOM uint8_t OLSN : 1;    /*!< [1..1] Output Level Select N                                              */
+            __IOM uint8_t TOCS : 1;    /*!< [2..2] TOC Select                                                         */
+            __IOM uint8_t TOCL : 1;    /*!< [3..3] TOC Register Write Protection                                      */
+            uint8_t            : 2;
+            __IOM uint8_t PSYE : 1;    /*!< [6..6] PWM Synchronous Output Enable                                      */
+            uint8_t            : 1;
+        } TOCR1B_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TOCR2B;          /*!< (@ 0x00000A0F) Timer Output Control Register 2B                           */
+
+        struct
+        {
+            __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
+            __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
+            __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
+            __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
+            __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
+            __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
+            __IOM uint8_t BF    : 2;   /*!< [7..6] TOLBR Buffer Transfer Timing Select                                */
+        } TOCR2B_b;
+    };
+    __IM uint16_t  RESERVED20[2];
+    __IOM uint16_t TCDRB;              /*!< (@ 0x00000A14) Timer Cycle Data Register B                                */
+    __IOM uint16_t TDDRB;              /*!< (@ 0x00000A16) Timer Dead Time Data Register B                            */
+    __IM uint16_t  RESERVED21[4];
+    __IM uint16_t  TCNTSB;             /*!< (@ 0x00000A20) Timer Subcounter B                                         */
+    __IOM uint16_t TCBRB;              /*!< (@ 0x00000A22) Timer Cycle Buffer Register B                              */
+    __IM uint16_t  RESERVED22[6];
+
+    union
+    {
+        __IOM uint8_t TITCR1B;         /*!< (@ 0x00000A30) Timer Interrupt Skipping Set Register 1B                   */
+
+        struct
+        {
+            __IOM uint8_t T7VCOR : 3;  /*!< [2..0] TCIV7 Interrupt Skipping Count Setting                             */
+            __IOM uint8_t T7VEN  : 1;  /*!< [3..3] TCIV7 Interrupt Skipping Enable                                    */
+            __IOM uint8_t T6ACOR : 3;  /*!< [6..4] TGIA6 Interrupt Skipping Count Setting                             */
+            __IOM uint8_t T6AEN  : 1;  /*!< [7..7] TGIA6 Interrupt Skipping Enable                                    */
+        } TITCR1B_b;
+    };
+
+    union
+    {
+        __IM uint8_t TITCNT1B;         /*!< (@ 0x00000A31) Timer Interrupt Skipping Counter 1B                        */
+
+        struct
+        {
+            __IM uint8_t T7VCNT : 3;   /*!< [2..0] TCIV7 Interrupt Counter                                            */
+            uint8_t             : 1;
+            __IM uint8_t T6ACNT : 3;   /*!< [6..4] TGIA6 Interrupt Counter                                            */
+            uint8_t             : 1;
+        } TITCNT1B_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TBTERB;          /*!< (@ 0x00000A32) Timer Buffer Transfer Set Register B                       */
+
+        struct
+        {
+            __IOM uint8_t BTE : 2;     /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting        */
+            uint8_t           : 6;
+        } TBTERB_b;
+    };
+    __IM uint8_t RESERVED23;
+
+    union
+    {
+        __IOM uint8_t TDERB;           /*!< (@ 0x00000A34) Timer Dead Time Enable Register B                          */
+
+        struct
+        {
+            __IOM uint8_t TDER : 1;    /*!< [0..0] Dead Time Enable                                                   */
+            uint8_t            : 7;
+        } TDERB_b;
+    };
+    __IM uint8_t RESERVED24;
+
+    union
+    {
+        __IOM uint8_t TOLBRB;          /*!< (@ 0x00000A36) Timer Output Level Buffer Register B                       */
+
+        struct
+        {
+            __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
+            __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
+            __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
+            __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
+            __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
+            __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
+            uint8_t             : 2;
+        } TOLBRB_b;
+    };
+    __IM uint8_t  RESERVED25;
+    __IM uint16_t RESERVED26;
+
+    union
+    {
+        __IOM uint8_t TITMRB;          /*!< (@ 0x00000A3A) Timer Interrupt Skipping Mode Register B                   */
+
+        struct
+        {
+            __IOM uint8_t TITM : 1;    /*!< [0..0] Interrupt Skipping Function Select                                 */
+            uint8_t            : 7;
+        } TITMRB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TITCR2B;         /*!< (@ 0x00000A3B) Timer Interrupt Skipping Set Register 2B                   */
+
+        struct
+        {
+            __IOM uint8_t TRG7COR : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Skipping Count Setting                     */
+            uint8_t               : 5;
+        } TITCR2B_b;
+    };
+
+    union
+    {
+        __IM uint8_t TITCNT2B;         /*!< (@ 0x00000A3C) Timer Interrupt Skipping Counter 2B                        */
+
+        struct
+        {
+            __IM uint8_t TRG7CNT : 3;  /*!< [2..0] TRG7AN/TRG7BN Interrupt Counter                                    */
+            uint8_t              : 5;
+        } TITCNT2B_b;
+    };
+    __IM uint8_t  RESERVED27;
+    __IM uint16_t RESERVED28[17];
+
+    union
+    {
+        __IOM uint8_t TWCRB;           /*!< (@ 0x00000A60) Timer Waveform Control Register B                          */
+
+        struct
+        {
+            __IOM uint8_t WRE : 1;     /*!< [0..0] Waveform Retain Enable                                             */
+            __IOM uint8_t SCC : 1;     /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB)                 */
+            uint8_t           : 5;
+            __IOM uint8_t CCE : 1;     /*!< [7..7] Compare Match Clear Enable                                         */
+        } TWCRB_b;
+    };
+    __IM uint8_t  RESERVED29;
+    __IM uint16_t RESERVED30[7];
+
+    union
+    {
+        __IOM uint8_t TMDR2B;          /*!< (@ 0x00000A70) Timer Mode Register 2B                                     */
+
+        struct
+        {
+            __IOM uint8_t DRS : 1;     /*!< [0..0] Double Buffer Select                                               */
+            uint8_t           : 7;
+        } TMDR2B_b;
+    };
+    __IM uint8_t  RESERVED31;
+    __IM uint16_t RESERVED32[7];
+
+    union
+    {
+        __IOM uint8_t TSTRB;           /*!< (@ 0x00000A80) Timer Start Register B                                     */
+
+        struct
+        {
+            uint8_t            : 6;
+            __IOM uint8_t CST6 : 1;    /*!< [6..6] Counter Start 6                                                    */
+            __IOM uint8_t CST7 : 1;    /*!< [7..7] Counter Start 7                                                    */
+        } TSTRB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TSYRB;           /*!< (@ 0x00000A81) Timer Synchronous Register B                               */
+
+        struct
+        {
+            uint8_t             : 6;
+            __IOM uint8_t SYNC6 : 1;   /*!< [6..6] Timer Synchronous Operation 6                                      */
+            __IOM uint8_t SYNC7 : 1;   /*!< [7..7] Timer Synchronous Operation 7                                      */
+        } TSYRB_b;
+    };
+    __IM uint16_t RESERVED33;
+
+    union
+    {
+        __IOM uint8_t TRWERB;          /*!< (@ 0x00000A84) Timer Read/Write Enable Register B                         */
+
+        struct
+        {
+            __IOM uint8_t RWE : 1;     /*!< [0..0] Read/Write Enable                                                  */
+            uint8_t           : 7;
+        } TRWERB_b;
+    };
+    __IM uint8_t  RESERVED34;
+    __IM uint16_t RESERVED35;
+} R_MTU_Type;                          /*!< Size = 2696 (0xa88)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU3                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 3 (R_MTU3)
+ */
+
+typedef struct                         /*!< (@ 0x90001100) R_MTU3 Structure                                           */
+{
+    __IM uint16_t RESERVED[128];
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000100) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000102) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000104) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000105) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000108) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 2;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint8_t   RESERVED4;
+    __IM uint16_t  RESERVED5[3];
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000110) Timer Counter                                              */
+    __IM uint16_t  RESERVED6[3];
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000118) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000011A) Timer General Register B                                   */
+    __IM uint16_t  RESERVED7[4];
+    __IOM uint16_t TGRC;               /*!< (@ 0x00000124) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x00000126) Timer General Register D                                   */
+    __IM uint16_t  RESERVED8[2];
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x0000012C) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10[5];
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            uint8_t            : 6;
+        } TBTM_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12[9];
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000014C) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint8_t   RESERVED13;
+    __IM uint16_t  RESERVED14[18];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000172) Timer General Register E                                   */
+} R_MTU3_Type;                         /*!< Size = 372 (0x174)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU4                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 4 (R_MTU4)
+ */
+
+typedef struct                         /*!< (@ 0x90001200) R_MTU4 Structure                                           */
+{
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000001) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000003) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000006) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000007) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000009) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 1;
+            __IOM uint8_t TTGE2 : 1;   /*!< [6..6] A/D Converter Start Request Enable 2                               */
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint16_t  RESERVED4[4];
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000012) Timer Counter                                              */
+    __IM uint16_t  RESERVED5[4];
+    __IOM uint16_t TGRA;               /*!< (@ 0x0000001C) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000001E) Timer General Register B                                   */
+    __IM uint16_t  RESERVED6[4];
+    __IOM uint16_t TGRC;               /*!< (@ 0x00000028) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x0000002A) Timer General Register D                                   */
+    __IM uint8_t   RESERVED7;
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x0000002D) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IM uint16_t RESERVED8[5];
+    __IM uint8_t  RESERVED9;
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            uint8_t            : 6;
+        } TBTM_b;
+    };
+    __IM uint16_t RESERVED10[3];
+
+    union
+    {
+        __IOM uint16_t TADCR;          /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register         */
+
+        struct
+        {
+            __IOM uint16_t ITB4VE : 1; /*!< [0..0] TCIV4 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITB3AE : 1; /*!< [1..1] TGIA3 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITA4VE : 1; /*!< [2..2] TCIV4 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITA3AE : 1; /*!< [3..3] TGIA3 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t DT4BE  : 1; /*!< [4..4] Down-Count TRG4BN Enable                                           */
+            __IOM uint16_t UT4BE  : 1; /*!< [5..5] Up-Count TRG4BN Enable                                             */
+            __IOM uint16_t DT4AE  : 1; /*!< [6..6] Down-Count TRG4AN Enable                                           */
+            __IOM uint16_t UT4AE  : 1; /*!< [7..7] Up-Count TRG4AN Enable                                             */
+            uint16_t              : 6;
+            __IOM uint16_t BF     : 2; /*!< [15..14] MTU4.TADCOBRA/TADCOBRB Transfer Timing Select                    */
+        } TADCR_b;
+    };
+    __IM uint16_t  RESERVED11;
+    __IOM uint16_t TADCORA;            /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register
+                                        *                  A                                                          */
+    __IOM uint16_t TADCORB;            /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register
+                                        *                  B                                                          */
+    __IOM uint16_t TADCOBRA;           /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer
+                                        *                  Register A                                                 */
+    __IOM uint16_t TADCOBRB;           /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer
+                                        *                  Register B                                                 */
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000004D) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint16_t  RESERVED13[19];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000074) Timer General Register E                                   */
+    __IOM uint16_t TGRF;               /*!< (@ 0x00000076) Timer General Register F                                   */
+} R_MTU4_Type;                         /*!< Size = 120 (0x78)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MTU_NF                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Noise Filter (R_MTU_NF)
+ */
+
+typedef struct                         /*!< (@ 0x90001290) R_MTU_NF Structure                                         */
+{
+    union
+    {
+        __IOM uint8_t NFCR0;           /*!< (@ 0x00000000) Noise Filter Control Register 0                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR1;           /*!< (@ 0x00000001) Noise Filter Control Register 1                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            uint8_t             : 2;
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR2;           /*!< (@ 0x00000002) Noise Filter Control Register 2                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            uint8_t             : 2;
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR3;           /*!< (@ 0x00000003) Noise Filter Control Register 3                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR4;           /*!< (@ 0x00000004) Noise Filter Control Register 4                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR4_b;
+    };
+    __IM uint8_t RESERVED[3];
+
+    union
+    {
+        __IOM uint8_t NFCR8;           /*!< (@ 0x00000008) Noise Filter Control Register 8                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR8_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCRC;           /*!< (@ 0x00000009) Noise Filter Control Register C                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCRC_b;
+    };
+    __IM uint8_t RESERVED1[2041];
+
+    union
+    {
+        __IOM uint8_t NFCR6;           /*!< (@ 0x00000803) Noise Filter Control Register 6                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR6_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR7;           /*!< (@ 0x00000804) Noise Filter Control Register 7                            */
+
+        struct
+        {
+            __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
+            __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
+            __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
+            __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR7_b;
+    };
+
+    union
+    {
+        __IOM uint8_t NFCR5;           /*!< (@ 0x00000805) Noise Filter Control Register 5                            */
+
+        struct
+        {
+            __IOM uint8_t NFUEN : 1;   /*!< [0..0] Noise Filter U Enable                                              */
+            __IOM uint8_t NFVEN : 1;   /*!< [1..1] Noise Filter V Enable                                              */
+            __IOM uint8_t NFWEN : 1;   /*!< [2..2] Noise Filter W Enable                                              */
+            uint8_t             : 1;
+            __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
+            uint8_t             : 2;
+        } NFCR5_b;
+    };
+} R_MTU_NF_Type;                       /*!< Size = 2054 (0x806)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 0 (R_MTU0)
+ */
+
+typedef struct                         /*!< (@ 0x90001300) R_MTU0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            __IOM uint8_t BFE : 1;     /*!< [6..6] Buffer Operation E                                                 */
+            uint8_t           : 1;
+        } TMDR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000002) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000003) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 2;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint8_t   RESERVED;
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
+    __IOM uint16_t TGRC;               /*!< (@ 0x0000000C) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x0000000E) Timer General Register D                                   */
+    __IM uint16_t  RESERVED1[8];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000020) Timer General Register E                                   */
+    __IOM uint16_t TGRF;               /*!< (@ 0x00000022) Timer General Register F                                   */
+
+    union
+    {
+        __IOM uint8_t TIER2;           /*!< (@ 0x00000024) Timer Interrupt Enable Register 2                          */
+
+        struct
+        {
+            __IOM uint8_t TGIEE : 1;   /*!< [0..0] TGR Interrupt Enable E                                             */
+            __IOM uint8_t TGIEF : 1;   /*!< [1..1] TGR Interrupt Enable F                                             */
+            uint8_t             : 5;
+            __IOM uint8_t TTGE2 : 1;   /*!< [7..7] A/D Converter Start Request Enable 2                               */
+        } TIER2_b;
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000026) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            __IOM uint8_t TTSE : 1;    /*!< [2..2] Timing Select E                                                    */
+            uint8_t            : 5;
+        } TBTM_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x00000028) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint8_t  RESERVED4;
+    __IM uint16_t RESERVED5;
+} R_MTU0_Type;                         /*!< Size = 44 (0x2c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU1                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 1 (R_MTU1)
+ */
+
+typedef struct                         /*!< (@ 0x90001380) R_MTU1 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD : 4;      /*!< [3..0] Mode Select                                                        */
+            uint8_t          : 4;
+        } TMDR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIOR;            /*!< (@ 0x00000002) Timer I/O Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIOR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            uint8_t             : 2;
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            __IOM uint8_t TCIEU : 1;   /*!< [5..5] Underflow Interrupt Enable                                         */
+            uint8_t             : 1;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x00000005) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
+    __IM uint32_t  RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TICCR;           /*!< (@ 0x00000010) Timer Input Capture Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t I1AE : 1;    /*!< [0..0] Input Capture Enable                                               */
+            __IOM uint8_t I1BE : 1;    /*!< [1..1] Input Capture Enable                                               */
+            __IOM uint8_t I2AE : 1;    /*!< [2..2] Input Capture Enable                                               */
+            __IOM uint8_t I2BE : 1;    /*!< [3..3] Input Capture Enable                                               */
+            uint8_t            : 4;
+        } TICCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR3;           /*!< (@ 0x00000011) Timer Mode Register 3                                      */
+
+        struct
+        {
+            __IOM uint8_t LWA     : 1; /*!< [0..0] MTU1/MTU2 Combination Longword Access Control                      */
+            __IOM uint8_t PHCKSEL : 1; /*!< [1..1] External Input Phase Clock Select                                  */
+            uint8_t               : 6;
+        } TMDR3_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x00000014) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t PCB   : 2;   /*!< [4..3] Functional Expansion Control for Phase Counting Modes
+                                        *   2, 3, and 5                                                               */
+            uint8_t : 3;
+        } TCR2_b;
+    };
+    __IM uint8_t   RESERVED3;
+    __IM uint16_t  RESERVED4;
+    __IM uint32_t  RESERVED5[2];
+    __IOM uint32_t TCNTLW;             /*!< (@ 0x00000020) Timer Longword Counter                                     */
+    __IOM uint32_t TGRALW;             /*!< (@ 0x00000024) Timer Longword General Register A                          */
+    __IOM uint32_t TGRBLW;             /*!< (@ 0x00000028) Timer Longword General Register B                          */
+} R_MTU1_Type;                         /*!< Size = 44 (0x2c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU2                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 2 (R_MTU2)
+ */
+
+typedef struct                         /*!< (@ 0x90001400) R_MTU2 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD : 4;      /*!< [3..0] Mode Select                                                        */
+            uint8_t          : 4;
+        } TMDR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIOR;            /*!< (@ 0x00000002) Timer I/O Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIOR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            uint8_t             : 2;
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            __IOM uint8_t TCIEU : 1;   /*!< [5..5] Underflow Interrupt Enable                                         */
+            uint8_t             : 1;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x00000005) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000000C) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t PCB   : 2;   /*!< [4..3] Functional Expansion Control for Phase Counting Modes
+                                        *   2, 3, and 5                                                               */
+            uint8_t : 3;
+        } TCR2_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+} R_MTU2_Type;                         /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU8                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 8 (R_MTU8)
+ */
+
+typedef struct                         /*!< (@ 0x90001600) R_MTU8 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000002) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000003) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 3;
+        } TIER_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x00000006) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint8_t   RESERVED1;
+    __IOM uint32_t TCNT;               /*!< (@ 0x00000008) Timer Counter                                              */
+    __IOM uint32_t TGRA;               /*!< (@ 0x0000000C) Timer General Register A                                   */
+    __IOM uint32_t TGRB;               /*!< (@ 0x00000010) Timer General Register B                                   */
+    __IOM uint32_t TGRC;               /*!< (@ 0x00000014) Timer General Register C                                   */
+    __IOM uint32_t TGRD;               /*!< (@ 0x00000018) Timer General Register D                                   */
+} R_MTU8_Type;                         /*!< Size = 28 (0x1c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU6                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 6 (R_MTU6)
+ */
+
+typedef struct                         /*!< (@ 0x90001900) R_MTU6 Structure                                           */
+{
+    __IM uint16_t RESERVED[128];
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000100) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000102) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000104) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000105) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000108) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 2;
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint8_t   RESERVED4;
+    __IM uint16_t  RESERVED5[3];
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000110) Timer Counter                                              */
+    __IM uint16_t  RESERVED6[3];
+    __IOM uint16_t TGRA;               /*!< (@ 0x00000118) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000011A) Timer General Register B                                   */
+    __IM uint16_t  RESERVED7[4];
+    __IOM uint16_t TGRC;               /*!< (@ 0x00000124) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x00000126) Timer General Register D                                   */
+    __IM uint16_t  RESERVED8[2];
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x0000012C) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10[5];
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            uint8_t            : 6;
+        } TBTM_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12[9];
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000014C) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t TSYCR;           /*!< (@ 0x00000150) Timer Synchronous Clear Register                           */
+
+        struct
+        {
+            __IOM uint8_t CE2B : 1;    /*!< [0..0] Clear Enable 2B                                                    */
+            __IOM uint8_t CE2A : 1;    /*!< [1..1] Clear Enable 2A                                                    */
+            __IOM uint8_t CE1B : 1;    /*!< [2..2] Clear Enable 1B                                                    */
+            __IOM uint8_t CE1A : 1;    /*!< [3..3] Clear Enable 1A                                                    */
+            __IOM uint8_t CE0D : 1;    /*!< [4..4] Clear Enable 0D                                                    */
+            __IOM uint8_t CE0C : 1;    /*!< [5..5] Clear Enable 0C                                                    */
+            __IOM uint8_t CE0B : 1;    /*!< [6..6] Clear Enable 0B                                                    */
+            __IOM uint8_t CE0A : 1;    /*!< [7..7] Clear Enable 0A                                                    */
+        } TSYCR_b;
+    };
+    __IM uint8_t   RESERVED15;
+    __IM uint16_t  RESERVED16[16];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000172) Timer General Register E                                   */
+} R_MTU6_Type;                         /*!< Size = 372 (0x174)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU7                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 7 (R_MTU7)
+ */
+
+typedef struct                         /*!< (@ 0x90001A00) R_MTU7 Structure                                           */
+{
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000001) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
+            __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
+        } TCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TMDR1;           /*!< (@ 0x00000003) Timer Mode Register 1                                      */
+
+        struct
+        {
+            __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
+            __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
+            __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
+            uint8_t           : 2;
+        } TMDR1_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t TIORH;           /*!< (@ 0x00000006) Timer I/O Control Register H                               */
+
+        struct
+        {
+            __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORL;           /*!< (@ 0x00000007) Timer I/O Control Register L                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
+            __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
+        } TIORL_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x00000009) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
+            __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
+            __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
+            __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
+            __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
+            uint8_t             : 1;
+            __IOM uint8_t TTGE2 : 1;   /*!< [6..6] A/D Converter Start Request Enable 2                               */
+            __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
+        } TIER_b;
+    };
+    __IM uint16_t  RESERVED4[4];
+    __IOM uint16_t TCNT;               /*!< (@ 0x00000012) Timer Counter                                              */
+    __IM uint16_t  RESERVED5[4];
+    __IOM uint16_t TGRA;               /*!< (@ 0x0000001C) Timer General Register A                                   */
+    __IOM uint16_t TGRB;               /*!< (@ 0x0000001E) Timer General Register B                                   */
+    __IM uint16_t  RESERVED6[4];
+    __IOM uint16_t TGRC;               /*!< (@ 0x00000028) Timer General Register C                                   */
+    __IOM uint16_t TGRD;               /*!< (@ 0x0000002A) Timer General Register D                                   */
+    __IM uint8_t   RESERVED7;
+
+    union
+    {
+        __IOM uint8_t TSR;             /*!< (@ 0x0000002D) Timer Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
+            __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
+            __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
+            __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
+            __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
+            __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
+            uint8_t            : 1;
+            __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
+        } TSR_b;
+    };
+    __IM uint16_t RESERVED8[5];
+    __IM uint8_t  RESERVED9;
+
+    union
+    {
+        __IOM uint8_t TBTM;            /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register              */
+
+        struct
+        {
+            __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
+            __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
+            uint8_t            : 6;
+        } TBTM_b;
+    };
+    __IM uint16_t RESERVED10[3];
+
+    union
+    {
+        __IOM uint16_t TADCR;          /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register         */
+
+        struct
+        {
+            __IOM uint16_t ITB7VE : 1; /*!< [0..0] TCIV7 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITB6AE : 1; /*!< [1..1] TGIA6 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITA7VE : 1; /*!< [2..2] TCIV7 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t ITA6AE : 1; /*!< [3..3] TGIA6 Interrupt Skipping Link Enable                               */
+            __IOM uint16_t DT7BE  : 1; /*!< [4..4] Down-Count TRG7BN Enable                                           */
+            __IOM uint16_t UT7BE  : 1; /*!< [5..5] Up-Count TRG7BN Enable                                             */
+            __IOM uint16_t DT7AE  : 1; /*!< [6..6] Down-Count TRG7AN Enable                                           */
+            __IOM uint16_t UT7AE  : 1; /*!< [7..7] Up-Count TRG7AN Enable                                             */
+            uint16_t              : 6;
+            __IOM uint16_t BF     : 2; /*!< [15..14] MTU7.TADCOBRA/TADCOBRB Transfer Timing Select                    */
+        } TADCR_b;
+    };
+    __IM uint16_t  RESERVED11;
+    __IOM uint16_t TADCORA;            /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register
+                                        *                  A                                                          */
+    __IOM uint16_t TADCORB;            /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register
+                                        *                  B                                                          */
+    __IOM uint16_t TADCOBRA;           /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer
+                                        *                  Register A                                                 */
+    __IOM uint16_t TADCOBRB;           /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer
+                                        *                  Register B                                                 */
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        __IOM uint8_t TCR2;            /*!< (@ 0x0000004D) Timer Control Register 2                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            uint8_t             : 5;
+        } TCR2_b;
+    };
+    __IM uint16_t  RESERVED13[19];
+    __IOM uint16_t TGRE;               /*!< (@ 0x00000074) Timer General Register E                                   */
+    __IOM uint16_t TGRF;               /*!< (@ 0x00000076) Timer General Register F                                   */
+} R_MTU7_Type;                         /*!< Size = 120 (0x78)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU5                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Multi-Function Timer Pulse Unit Channel 5 (R_MTU5)
+ */
+
+typedef struct                         /*!< (@ 0x90001C00) R_MTU5 Structure                                           */
+{
+    __IM uint16_t  RESERVED[64];
+    __IOM uint16_t TCNTU;              /*!< (@ 0x00000080) Timer Counter U                                            */
+    __IOM uint16_t TGRU;               /*!< (@ 0x00000082) Timer General Register U                                   */
+
+    union
+    {
+        __IOM uint8_t TCRU;            /*!< (@ 0x00000084) Timer Control Register U                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
+            uint8_t            : 6;
+        } TCRU_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCR2U;           /*!< (@ 0x00000085) Timer Control Register 2U                                  */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
+            uint8_t             : 3;
+        } TCR2U_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORU;           /*!< (@ 0x00000086) Timer I/O Control Register U                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
+            uint8_t           : 3;
+        } TIORU_b;
+    };
+    __IM uint8_t   RESERVED1;
+    __IM uint16_t  RESERVED2[4];
+    __IOM uint16_t TCNTV;              /*!< (@ 0x00000090) Timer Counter V                                            */
+    __IOM uint16_t TGRV;               /*!< (@ 0x00000092) Timer General Register V                                   */
+
+    union
+    {
+        __IOM uint8_t TCRV;            /*!< (@ 0x00000094) Timer Control Register V                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
+            uint8_t            : 6;
+        } TCRV_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCR2V;           /*!< (@ 0x00000095) Timer Control Register 2V                                  */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
+            uint8_t             : 3;
+        } TCR2V_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORV;           /*!< (@ 0x00000096) Timer I/O Control Register V                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
+            uint8_t           : 3;
+        } TIORV_b;
+    };
+    __IM uint8_t   RESERVED3;
+    __IM uint16_t  RESERVED4[4];
+    __IOM uint16_t TCNTW;              /*!< (@ 0x000000A0) Timer Counter W                                            */
+    __IOM uint16_t TGRW;               /*!< (@ 0x000000A2) Timer General Register W                                   */
+
+    union
+    {
+        __IOM uint8_t TCRW;            /*!< (@ 0x000000A4) Timer Control Register W                                   */
+
+        struct
+        {
+            __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
+            uint8_t            : 6;
+        } TCRW_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCR2W;           /*!< (@ 0x000000A5) Timer Control Register 2W                                  */
+
+        struct
+        {
+            __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
+            __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
+            uint8_t             : 3;
+        } TCR2W_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TIORW;           /*!< (@ 0x000000A6) Timer I/O Control Register W                               */
+
+        struct
+        {
+            __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
+            uint8_t           : 3;
+        } TIORW_b;
+    };
+    __IM uint8_t  RESERVED5;
+    __IM uint16_t RESERVED6[5];
+
+    union
+    {
+        __IOM uint8_t TIER;            /*!< (@ 0x000000B2) Timer Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t TGIE5W : 1;  /*!< [0..0] TGR Interrupt Enable 5W                                            */
+            __IOM uint8_t TGIE5V : 1;  /*!< [1..1] TGR Interrupt Enable 5V                                            */
+            __IOM uint8_t TGIE5U : 1;  /*!< [2..2] TGR Interrupt Enable 5U                                            */
+            uint8_t              : 5;
+        } TIER_b;
+    };
+    __IM uint8_t RESERVED7;
+
+    union
+    {
+        __IOM uint8_t TSTR;            /*!< (@ 0x000000B4) Timer Start Register                                       */
+
+        struct
+        {
+            __IOM uint8_t CSTW5 : 1;   /*!< [0..0] Counter Start W5                                                   */
+            __IOM uint8_t CSTV5 : 1;   /*!< [1..1] Counter Start V5                                                   */
+            __IOM uint8_t CSTU5 : 1;   /*!< [2..2] Counter Start U5                                                   */
+            uint8_t             : 5;
+        } TSTR_b;
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        __IOM uint8_t TCNTCMPCLR;       /*!< (@ 0x000000B6) Timer Compare Match Clear Register                         */
+
+        struct
+        {
+            __IOM uint8_t CMPCLR5W : 1; /*!< [0..0] TCNT Compare Clear 5W                                              */
+            __IOM uint8_t CMPCLR5V : 1; /*!< [1..1] TCNT Compare Clear 5V                                              */
+            __IOM uint8_t CMPCLR5U : 1; /*!< [2..2] TCNT Compare Clear 5U                                              */
+            uint8_t                : 5;
+        } TCNTCMPCLR_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10;
+} R_MTU5_Type;                         /*!< Size = 186 (0xba)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_TFU0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Trigonometric Function Unit 0 (R_TFU0)
+ */
+
+typedef struct                         /*!< (@ 0x90010000) R_TFU0 Structure                                           */
+{
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t FXSCIOC;         /*!< (@ 0x00000004) Fixed-point Sine Cosine Input/Output Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t IUF : 1;     /*!< [0..0] Input unit and format setting                                      */
+            uint8_t           : 3;
+            __IOM uint8_t OF  : 2;     /*!< [5..4] Output format setting                                              */
+            uint8_t           : 2;
+        } FXSCIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t FXATIOC;         /*!< (@ 0x00000005) Fixed-point Arctangent hypot_k Input/Output Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint8_t           : 4;
+            __IOM uint8_t OUF : 1;     /*!< [4..4] Output unit and format setting                                     */
+            uint8_t           : 3;
+        } FXATIOC_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t TRGSTS;          /*!< (@ 0x00000008) Trigonometric Status Register                              */
+
+        struct
+        {
+            __IOM uint8_t BSYF : 1;    /*!< [0..0] Calculation in progress flag                                       */
+            __IOM uint8_t ERRF : 1;    /*!< [1..1] Input error flag                                                   */
+            uint8_t            : 6;
+        } TRGSTS_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+    __IM uint32_t RESERVED4;
+
+    union
+    {
+        __IOM float FPSCDT0;             /*!< (@ 0x00000010) Floating-point Sine Cosine Data Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t FPSCDT0 : 32; /*!< [31..0] Floating-point Sine Cosine Data Register 0                        */
+        } FPSCDT0_b;
+    };
+
+    union
+    {
+        __IOM float FPSCDT1;             /*!< (@ 0x00000014) Floating-point Sine Cosine Data Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t FPSCDT1 : 32; /*!< [31..0] Floating-point Sine Cosine Data Register 1                        */
+        } FPSCDT1_b;
+    };
+
+    union
+    {
+        __IOM float FPATDT0;             /*!< (@ 0x00000018) Floating-point Arctangent hypot_k Data Register
+                                          *                  0                                                          */
+
+        struct
+        {
+            __IOM uint32_t FPATDT0 : 32; /*!< [31..0] Floating-point Arctangent hypot_k Data Register 0                 */
+        } FPATDT0_b;
+    };
+
+    union
+    {
+        __IOM float FPATDT1;             /*!< (@ 0x0000001C) Floating-point Arctangent hypot_k Data Register
+                                          *                  1                                                          */
+
+        struct
+        {
+            __IOM uint32_t FPATDT1 : 32; /*!< [31..0] Floating-point Arctangent hypot_k Data Register 1                 */
+        } FPATDT1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FXSCDT0;          /*!< (@ 0x00000020) Fixed-point Sine Cosine Data Register                      */
+
+        struct
+        {
+            __IOM uint32_t FXSCDT0 : 32; /*!< [31..0] Fixed-point Sine Cosine Data Register 0                           */
+        } FXSCDT0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FXSCDT1;          /*!< (@ 0x00000024) Fixed-point Sine Cosine Data Register 1                    */
+
+        struct
+        {
+            __IOM uint32_t FXSCDT1 : 32; /*!< [31..0] Fixed-point Sine Cosine Data Register 1                           */
+        } FXSCDT1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FXATDT0;          /*!< (@ 0x00000028) Fixed-point Arctangent hypot_k Data Register
+                                          *                  0                                                          */
+
+        struct
+        {
+            __IOM uint32_t FXATDT0 : 32; /*!< [31..0] Fixed-point Arctangent hypot_k Data Register 0                    */
+        } FXATDT0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FXATDT1;          /*!< (@ 0x0000002C) Fixed-point Arctangent hypot_k Data Register
+                                          *                  1                                                          */
+
+        struct
+        {
+            __IOM uint32_t FXATDT1 : 32; /*!< [31..0] Fixed-point Arctangent hypot_k Data Register 1                    */
+        } FXATDT1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DTSR0;          /*!< (@ 0x00000030) Data Save Restore Register 0                               */
+
+        struct
+        {
+            __IOM uint32_t DTSR0 : 32; /*!< [31..0] Data Save Restore Register 0                                      */
+        } DTSR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DTSR1;          /*!< (@ 0x00000034) Data Save Restore Register 1                               */
+
+        struct
+        {
+            __IOM uint32_t DTSR1 : 32; /*!< [31..0] Data Save Restore Register 1                                      */
+        } DTSR1_b;
+    };
+} R_TFU0_Type;                         /*!< Size = 56 (0x38)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ADC120                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief 12-Bit A/D converter 0 (R_ADC120)
+ */
+
+typedef struct                         /*!< (@ 0x90014000) R_ADC120 Structure                                         */
+{
+    union
+    {
+        __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel Select                                      */
+            uint16_t              : 1;
+            __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
+            __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
+            __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
+            __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
+            uint16_t              : 2;
+            __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
+            __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
+            __IOM uint16_t ADST   : 1; /*!< [15..15] A/D conversion Start                                             */
+        } ADCSR_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t ADANSA0;        /*!< (@ 0x00000004) A/D Channel Select Register A0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSA0 : 16; /*!< [15..0] A/D conversion Analog input Channel Select                        */
+        } ADANSA0_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t ADADS0;         /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Function
+                                        *                  Channel Select Register 0                                  */
+
+        struct
+        {
+            __IOM uint16_t ADS0 : 16;  /*!< [15..0] A/D-Converted Value Addition/Average Channel Select               */
+        } ADADS0_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t ADC  : 3;    /*!< [2..0] Addition Count Select                                              */
+            uint8_t            : 4;
+            __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable                                                */
+        } ADADC_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
+
+        struct
+        {
+            uint16_t              : 1;
+            __IOM uint16_t ADPRC  : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
+            uint16_t              : 2;
+            __IOM uint16_t ACE    : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
+            uint16_t              : 9;
+            __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select                                  */
+        } ADCER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
+
+        struct
+        {
+            __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group B                    */
+            uint16_t            : 2;
+            __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger Select                               */
+            uint16_t            : 2;
+        } ADSTRGR_b;
+    };
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint16_t ADANSB0;        /*!< (@ 0x00000014) A/D Channel Select Register B0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSB0 : 16; /*!< [15..0] A/D Conversion Analog Input Channel Select                        */
+        } ADANSB0_b;
+    };
+    __IM uint16_t RESERVED5;
+
+    union
+    {
+        __IM uint16_t ADDBLDR;         /*!< (@ 0x00000018) A/D Data Duplication Register                              */
+
+        struct
+        {
+            __IM uint16_t DBLDR : 16;  /*!< [15..0] The result of A/D conversion in response to the second
+                                        *   trigger in double trigger mode.                                           */
+        } ADDBLDR_b;
+    };
+    __IM uint16_t RESERVED6[3];
+
+    union
+    {
+        __IM uint16_t ADDR[4];         /*!< (@ 0x00000020) A/D Data Register n (n = 0 to 3)                           */
+
+        struct
+        {
+            __IM uint16_t DR : 16;     /*!< [15..0] The result of A/D conversion (n: Number of channel)               */
+        } ADDR_b[4];
+    };
+    __IM uint16_t RESERVED7[31];
+
+    union
+    {
+        __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Control Register                       */
+
+        struct
+        {
+            __IOM uint16_t SSTSH : 8;  /*!< [7..0] Sample and hold period setting                                     */
+            __IOM uint16_t SHANS : 3;  /*!< [10..8] Sample and hold use or bypass select for ch0-2                    */
+            uint16_t             : 5;
+        } ADSHCR_b;
+    };
+    __IM uint16_t RESERVED8[10];
+    __IM uint8_t  RESERVED9;
+
+    union
+    {
+        __IOM uint8_t ADELCCR;         /*!< (@ 0x0000007D) A/D Event Link Control Register                            */
+
+        struct
+        {
+            __IOM uint8_t ELCC  : 2;   /*!< [1..0] Event link control bits                                            */
+            __IOM uint8_t GCELC : 1;   /*!< [2..2] Event control bit for Group C                                      */
+            uint8_t             : 5;
+        } ADELCCR_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t ADGSPCR;        /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
+
+        struct
+        {
+            __IOM uint16_t PGS    : 1; /*!< [0..0] Group Priority Control Setting                                     */
+            __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting                                            */
+            uint16_t              : 12;
+            __IOM uint16_t LGRRS  : 1; /*!< [14..14] Restart Channel Select                                           */
+            __IOM uint16_t GBRP   : 1; /*!< [15..15] Group B Single Scan Continuous Start                             */
+        } ADGSPCR_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IM uint16_t ADDBLDRA;        /*!< (@ 0x00000084) A/D Data Duplication Register A                            */
+
+        struct
+        {
+            __IM uint16_t DBLDRA : 16; /*!< [15..0] The result of A/D conversion during extended operation
+                                        *   in double trigger mode                                                    */
+        } ADDBLDRA_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDRB;        /*!< (@ 0x00000086) A/D Data Duplication Register B                            */
+
+        struct
+        {
+            __IM uint16_t DBLDRB : 16; /*!< [15..0] The result of A/D conversion during extended operation
+                                        *   in double trigger mode                                                    */
+        } ADDBLDRB_b;
+    };
+    __IM uint16_t RESERVED12[2];
+
+    union
+    {
+        __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitoring
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitor                                         */
+            uint8_t              : 3;
+            __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparing result monitor for window A                              */
+            __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparing result monitor for window B                              */
+            uint8_t              : 2;
+        } ADWINMON_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t CMPAB  : 2; /*!< [1..0] Window A/B combination condition setting                           */
+            uint16_t              : 7;
+            __IOM uint16_t CMPBE  : 1; /*!< [9..9] Window B operation permission                                      */
+            uint16_t              : 1;
+            __IOM uint16_t CMPAE  : 1; /*!< [11..11] Window A operation permission                                    */
+            uint16_t              : 1;
+            __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare window B Interrupt Enable                                */
+            __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function enable                                           */
+            __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare window A Interrupt Enable                                */
+        } ADCMPCR_b;
+    };
+    __IM uint16_t RESERVED15;
+
+    union
+    {
+        __IOM uint16_t ADCMPANSR0;       /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
+                                          *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t CMPCHA0 : 16; /*!< [15..0] Window A Channel Select                                           */
+        } ADCMPANSR0_b;
+    };
+    __IM uint16_t RESERVED16;
+
+    union
+    {
+        __IOM uint16_t ADCMPLR0;          /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
+                                           *                  Setting Register 0                                         */
+
+        struct
+        {
+            __IOM uint16_t CMPLCHA0 : 16; /*!< [15..0] Window A comparison condition for target channel (ch0-15)
+                                           *   setting                                                                   */
+        } ADCMPLR0_b;
+    };
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint16_t ADCMPDR0;        /*!< (@ 0x0000009C) A/D Comparison Function Window A Lower Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLLA : 16; /*!< [15..0] Reference data setting when using the compare function
+                                         *   window A                                                                  */
+        } ADCMPDR0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR1;        /*!< (@ 0x0000009E) AD Comparison Function Window A Upper Level Setting
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPULA : 16; /*!< [15..0] Reference data setting when using the compare function
+                                         *   window A                                                                  */
+        } ADCMPDR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPSR0;           /*!< (@ 0x000000A0) A/D Comparison Function Window A Channel Status
+                                            *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t CMPSTCHA0 : 16; /*!< [15..0] Window A Status Flag                                              */
+        } ADCMPSR0_b;
+    };
+    __IM uint16_t RESERVED18[2];
+
+    union
+    {
+        __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Window B Channel Select                                            */
+            uint8_t              : 1;
+            __IOM uint8_t CMPLB  : 1;  /*!< [7..7] Window B Comparison Condition Setting                              */
+        } ADCMPBNSR_b;
+    };
+    __IM uint8_t RESERVED19;
+
+    union
+    {
+        __IOM uint16_t ADWINLLB;        /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLLB : 16; /*!< [15..0] Reference lower data setting when using the compare
+                                         *   function window B                                                         */
+        } ADWINLLB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADWINULB;        /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPULB : 16; /*!< [15..0] Reference upper data setting when using the compare
+                                         *   function window B                                                         */
+        } ADWINULB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
+
+        struct
+        {
+            __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Window B Flag                                                      */
+            uint8_t              : 7;
+        } ADCMPBSR_b;
+    };
+    __IM uint8_t  RESERVED20;
+    __IM uint16_t RESERVED21[19];
+
+    union
+    {
+        __IOM uint16_t ADANSC0;        /*!< (@ 0x000000D4) A/D Channel Select Register C0                             */
+
+        struct
+        {
+            __IOM uint16_t ANSC0 : 16; /*!< [15..0] A/D-Converted Channel Select for Group C in Group Scan
+                                        *   Mode                                                                      */
+        } ADANSC0_b;
+    };
+    __IM uint16_t RESERVED22;
+    __IM uint8_t  RESERVED23;
+
+    union
+    {
+        __IOM uint8_t ADGCTRGR;        /*!< (@ 0x000000D9) A/D Group C Trigger Select Register                        */
+
+        struct
+        {
+            __IOM uint8_t TRSC   : 6;  /*!< [5..0] Group C A/D Conversion Start Trigger Select                        */
+            __IOM uint8_t GCADIE : 1;  /*!< [6..6] Group C Scan Completion Interrupt Enable                           */
+            __IOM uint8_t GRCE   : 1;  /*!< [7..7] Group C A/D Conversion Enable                                      */
+        } ADGCTRGR_b;
+    };
+    __IM uint16_t RESERVED24[3];
+
+    union
+    {
+        __IOM uint8_t ADSSTR[4];       /*!< (@ 0x000000E0) A/D Sampling State Register n (n = 0 to 3)                 */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting                                              */
+        } ADSSTR_b[4];
+    };
+    __IM uint16_t RESERVED25[134];
+
+    union
+    {
+        __IOM uint16_t ADCALCTL;        /*!< (@ 0x000001F0) A/D Calibration Control Register                           */
+
+        struct
+        {
+            __IOM uint16_t CAL     : 1; /*!< [0..0] Calibration Start                                                  */
+            __IM uint16_t  CAL_RDY : 1; /*!< [1..1] Calibration Status                                                 */
+            __IM uint16_t  CAL_ERR : 1; /*!< [2..2] Calibration Result                                                 */
+            uint16_t               : 13;
+        } ADCALCTL_b;
+    };
+} R_ADC120_Type;                        /*!< Size = 498 (0x1f2)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POE3                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Port Output Enable 3 (R_POE3)
+ */
+
+typedef struct                         /*!< (@ 0x90018000) R_POE3 Structure                                           */
+{
+    union
+    {
+        __IOM uint16_t ICSR1;          /*!< (@ 0x00000000) Input Level Control/Status Register 1                      */
+
+        struct
+        {
+            __IOM uint16_t POE0M : 2;  /*!< [1..0] POE0 Mode Select                                                   */
+            uint16_t             : 6;
+            __IOM uint16_t PIE1  : 1;  /*!< [8..8] Port Interrupt Enable 1                                            */
+            uint16_t             : 3;
+            __IOM uint16_t POE0F : 1;  /*!< [12..12] POE0 Flag                                                        */
+            uint16_t             : 3;
+        } ICSR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t OCSR1;          /*!< (@ 0x00000002) Output Level Control/Status Register 1                     */
+
+        struct
+        {
+            uint16_t            : 8;
+            __IOM uint16_t OIE1 : 1;   /*!< [8..8] Output Short Circuit Interrupt Enable 1                            */
+            __IOM uint16_t OCE1 : 1;   /*!< [9..9] Output Short Circuit High-Impedance Enable 1                       */
+            uint16_t            : 5;
+            __IOM uint16_t OSF1 : 1;   /*!< [15..15] Output Short Circuit Flag 1                                      */
+        } OCSR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR2;          /*!< (@ 0x00000004) Input Level Control/Status Register 2                      */
+
+        struct
+        {
+            __IOM uint16_t POE4M : 2;  /*!< [1..0] POE4 Mode Select                                                   */
+            uint16_t             : 6;
+            __IOM uint16_t PIE2  : 1;  /*!< [8..8] Port Interrupt Enable 2                                            */
+            uint16_t             : 3;
+            __IOM uint16_t POE4F : 1;  /*!< [12..12] POE4 Flag                                                        */
+            uint16_t             : 3;
+        } ICSR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t OCSR2;          /*!< (@ 0x00000006) Output Level Control/Status Register 2                     */
+
+        struct
+        {
+            uint16_t            : 8;
+            __IOM uint16_t OIE2 : 1;   /*!< [8..8] Output Short Circuit Interrupt Enable 2                            */
+            __IOM uint16_t OCE2 : 1;   /*!< [9..9] Output Short Circuit High-Impedance Enable 2                       */
+            uint16_t            : 5;
+            __IOM uint16_t OSF2 : 1;   /*!< [15..15] Output Short Circuit Flag 2                                      */
+        } OCSR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR3;          /*!< (@ 0x00000008) Input Level Control/Status Register 3                      */
+
+        struct
+        {
+            __IOM uint16_t POE8M : 2;  /*!< [1..0] POE8 Mode Select                                                   */
+            uint16_t             : 6;
+            __IOM uint16_t PIE3  : 1;  /*!< [8..8] Port Interrupt Enable 3                                            */
+            __IOM uint16_t POE8E : 1;  /*!< [9..9] POE8 High-Impedance Enable                                         */
+            uint16_t             : 2;
+            __IOM uint16_t POE8F : 1;  /*!< [12..12] POE8 Flag                                                        */
+            uint16_t             : 3;
+        } ICSR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPOER;              /*!< (@ 0x0000000A) Software Port Output Enable Register                       */
+
+        struct
+        {
+            __IOM uint8_t MTUCH34HIZ : 1; /*!< [0..0] MTU3 and MTU4 Output High-Impedance Enable                         */
+            __IOM uint8_t MTUCH67HIZ : 1; /*!< [1..1] MTU6 and MTU7 Output High-Impedance Enable                         */
+            __IOM uint8_t MTUCH0HIZ  : 1; /*!< [2..2] MTU0 Pin High-Impedance Enable                                     */
+            uint8_t                  : 5;
+        } SPOER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t POECR1;          /*!< (@ 0x0000000B) Port Output Enable Control Register 1                      */
+
+        struct
+        {
+            __IOM uint8_t MTU0AZE : 1; /*!< [0..0] MTU0AZE                                                            */
+            __IOM uint8_t MTU0BZE : 1; /*!< [1..1] MTU0BZE                                                            */
+            __IOM uint8_t MTU0CZE : 1; /*!< [2..2] MTU0CZE                                                            */
+            __IOM uint8_t MTU0DZE : 1; /*!< [3..3] MTU0DZE                                                            */
+            uint8_t               : 4;
+        } POECR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR2;           /*!< (@ 0x0000000C) Port Output Enable Control Register 2                      */
+
+        struct
+        {
+            __IOM uint16_t MTU7BDZE : 1; /*!< [0..0] MTU7BDZE                                                           */
+            __IOM uint16_t MTU7ACZE : 1; /*!< [1..1] MTU7ACZE                                                           */
+            __IOM uint16_t MTU6BDZE : 1; /*!< [2..2] MTU6BDZE                                                           */
+            uint16_t                : 5;
+            __IOM uint16_t MTU4BDZE : 1; /*!< [8..8] MTU4BDZE                                                           */
+            __IOM uint16_t MTU4ACZE : 1; /*!< [9..9] MTU4ACZE                                                           */
+            __IOM uint16_t MTU3BDZE : 1; /*!< [10..10] MTU3BDZE                                                         */
+            uint16_t                : 5;
+        } POECR2_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t POECR4;         /*!< (@ 0x00000010) Port Output Enable Control Register 4                      */
+
+        struct
+        {
+            uint16_t                    : 2;
+            __IOM uint16_t IC2ADDMT34ZE : 1; /*!< [2..2] IC2ADDMT34ZE                                                       */
+            __IOM uint16_t IC3ADDMT34ZE : 1; /*!< [3..3] IC3ADDMT34ZE                                                       */
+            __IOM uint16_t IC4ADDMT34ZE : 1; /*!< [4..4] IC4ADDMT34ZE                                                       */
+            __IOM uint16_t IC5ADDMT34ZE : 1; /*!< [5..5] IC5ADDMT34ZE                                                       */
+            uint16_t                    : 3;
+            __IOM uint16_t IC1ADDMT67ZE : 1; /*!< [9..9] IC1ADDMT67ZE                                                       */
+            uint16_t                    : 1;
+            __IOM uint16_t IC3ADDMT67ZE : 1; /*!< [11..11] IC3ADDMT67ZE                                                     */
+            __IOM uint16_t IC4ADDMT67ZE : 1; /*!< [12..12] IC4ADDMT67ZE                                                     */
+            __IOM uint16_t IC5ADDMT67ZE : 1; /*!< [13..13] IC5ADDMT67ZE                                                     */
+            uint16_t                    : 2;
+        } POECR4_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR5;         /*!< (@ 0x00000012) Port Output Enable Control Register 5                      */
+
+        struct
+        {
+            uint16_t                   : 1;
+            __IOM uint16_t IC1ADDMT0ZE : 1; /*!< [1..1] IC1ADDMT0ZE                                                        */
+            __IOM uint16_t IC2ADDMT0ZE : 1; /*!< [2..2] IC2ADDMT0ZE                                                        */
+            uint16_t                   : 1;
+            __IOM uint16_t IC4ADDMT0ZE : 1; /*!< [4..4] IC4ADDMT0ZE                                                        */
+            __IOM uint16_t IC5ADDMT0ZE : 1; /*!< [5..5] IC5ADDMT0ZE                                                        */
+            uint16_t                   : 10;
+        } POECR5_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t ICSR4;          /*!< (@ 0x00000016) Input Level Control/Status Register 4                      */
+
+        struct
+        {
+            __IOM uint16_t POE10M : 2; /*!< [1..0] POE10 Mode Select                                                  */
+            uint16_t              : 6;
+            __IOM uint16_t PIE4   : 1; /*!< [8..8] Port Interrupt Enable 4                                            */
+            __IOM uint16_t POE10E : 1; /*!< [9..9] POE10 High-Impedance Enable                                        */
+            uint16_t              : 2;
+            __IOM uint16_t POE10F : 1; /*!< [12..12] POE10 Flag                                                       */
+            uint16_t              : 3;
+        } ICSR4_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR5;          /*!< (@ 0x00000018) Input Level Control/Status Register 5                      */
+
+        struct
+        {
+            __IOM uint16_t POE11M : 2; /*!< [1..0] POE11 Mode Select                                                  */
+            uint16_t              : 6;
+            __IOM uint16_t PIE5   : 1; /*!< [8..8] Port Interrupt Enable 5                                            */
+            __IOM uint16_t POE11E : 1; /*!< [9..9] POE11 High-Impedance Enable                                        */
+            uint16_t              : 2;
+            __IOM uint16_t POE11F : 1; /*!< [12..12] POE11 Flag                                                       */
+            uint16_t              : 3;
+        } ICSR5_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ALR1;           /*!< (@ 0x0000001A) Active Level Setting Register 1                            */
+
+        struct
+        {
+            __IOM uint16_t OLSG0A : 1; /*!< [0..0] MTIOC3B Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG0B : 1; /*!< [1..1] MTIOC3D Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG1A : 1; /*!< [2..2] MTIOC4A Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG1B : 1; /*!< [3..3] MTIOC4C Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG2A : 1; /*!< [4..4] MTIOC4B Pin Active Level Setting                                   */
+            __IOM uint16_t OLSG2B : 1; /*!< [5..5] MTIOC4D Pin Active Level Setting                                   */
+            uint16_t              : 1;
+            __IOM uint16_t OLSEN  : 1; /*!< [7..7] Active Level Setting Enable                                        */
+            uint16_t              : 8;
+        } ALR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR6;          /*!< (@ 0x0000001C) Input Level Control/Status Register 6                      */
+
+        struct
+        {
+            uint16_t              : 9;
+            __IOM uint16_t OSTSTE : 1; /*!< [9..9] Oscillation Stop High-Impedance Enable                             */
+            uint16_t              : 2;
+            __IOM uint16_t OSTSTF : 1; /*!< [12..12] Oscillation Stop High-Impedance Flag                             */
+            uint16_t              : 3;
+        } ICSR6_b;
+    };
+
+    union
+    {
+        __IM uint16_t ICSR7;            /*!< (@ 0x0000001E) Input Level Control/Status Register 7                      */
+
+        struct
+        {
+            __IM uint16_t D0ERR0ST : 1; /*!< [0..0] D0ERR0ST                                                           */
+            __IM uint16_t D1ERR0ST : 1; /*!< [1..1] D1ERR0ST                                                           */
+            __IM uint16_t D2ERR0ST : 1; /*!< [2..2] D2ERR0ST                                                           */
+            __IM uint16_t D3ERR0ST : 1; /*!< [3..3] D3ERR0ST                                                           */
+            __IM uint16_t D4ERR0ST : 1; /*!< [4..4] D4ERR0ST                                                           */
+            __IM uint16_t D5ERR0ST : 1; /*!< [5..5] D5ERR0ST                                                           */
+            __IM uint16_t D6ERR0ST : 1; /*!< [6..6] D6ERR0ST                                                           */
+            __IM uint16_t D7ERR0ST : 1; /*!< [7..7] D7ERR0ST                                                           */
+            __IM uint16_t D8ERR0ST : 1; /*!< [8..8] D8ERR0ST                                                           */
+            __IM uint16_t D9ERR0ST : 1; /*!< [9..9] D9ERR0ST                                                           */
+            uint16_t               : 6;
+        } ICSR7_b;
+    };
+    __IM uint16_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint8_t M0SELR1;         /*!< (@ 0x00000024) MTU0 Pin Select Register 1                                 */
+
+        struct
+        {
+            __IOM uint8_t M0ASEL : 4;  /*!< [3..0] MTU0-A (MTIOC0A) Pin Select                                        */
+            __IOM uint8_t M0BSEL : 4;  /*!< [7..4] MTU0-B (MTIOC0B) Pin Select                                        */
+        } M0SELR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M0SELR2;         /*!< (@ 0x00000025) MTU0 Pin Select Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t M0CSEL : 4;  /*!< [3..0] MTU0-C (MTIOC0C) Pin Select                                        */
+            __IOM uint8_t M0DSEL : 4;  /*!< [7..4] MTU0-D (MTIOC0D) Pin Select                                        */
+        } M0SELR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M3SELR;          /*!< (@ 0x00000026) MTU3 Pin Select Register                                   */
+
+        struct
+        {
+            __IOM uint8_t M3BSEL : 4;  /*!< [3..0] MTU3-B (MTIOC3B) Pin Select                                        */
+            __IOM uint8_t M3DSEL : 4;  /*!< [7..4] MTU3-D (MTIOC3D) Pin Select                                        */
+        } M3SELR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M4SELR1;         /*!< (@ 0x00000027) MTU4 Pin Select Register 1                                 */
+
+        struct
+        {
+            __IOM uint8_t M4ASEL : 4;  /*!< [3..0] MTU4-A (MTIOC4A) Pin Select                                        */
+            __IOM uint8_t M4CSEL : 4;  /*!< [7..4] MTU4-C (MTIOC4C) Pin Select                                        */
+        } M4SELR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M4SELR2;         /*!< (@ 0x00000028) MTU4 Pin Select Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t M4BSEL : 4;  /*!< [3..0] MTU4-B (MTIOC4B) Pin Select                                        */
+            __IOM uint8_t M4DSEL : 4;  /*!< [7..4] MTU4-D (MTIOC4D) Pin Select                                        */
+        } M4SELR2_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t M6SELR;          /*!< (@ 0x0000002A) MTU6 Pin Select Register                                   */
+
+        struct
+        {
+            __IOM uint8_t M6BSEL : 4;  /*!< [3..0] MTU6-B (MTIOC6B) Pin Select                                        */
+            __IOM uint8_t M6DSEL : 4;  /*!< [7..4] MTU6-D (MTIOC6D) Pin Select                                        */
+        } M6SELR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M7SELR1;         /*!< (@ 0x0000002B) MTU7 Pin Select Register 1                                 */
+
+        struct
+        {
+            __IOM uint8_t M7ASEL : 4;  /*!< [3..0] MTU7-A (MTIOC7A) Pin Select                                        */
+            __IOM uint8_t M7CSEL : 4;  /*!< [7..4] MTU7-C (MTIOC7C) Pin Select                                        */
+        } M7SELR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t M7SELR2;         /*!< (@ 0x0000002C) MTU7 Pin Select Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t M7BSEL : 4;  /*!< [3..0] MTU7-B (MTIOC7B) Pin Select                                        */
+            __IOM uint8_t M7DSEL : 4;  /*!< [7..4] MTU7-D (MTIOC7D) Pin Select                                        */
+        } M7SELR2_b;
+    };
+    __IM uint8_t  RESERVED4;
+    __IM uint16_t RESERVED5;
+
+    union
+    {
+        __IM uint16_t ICSR8;            /*!< (@ 0x00000030) Input Level Control/Status Register 8                      */
+
+        struct
+        {
+            __IM uint16_t D0ERR1ST : 1; /*!< [0..0] D0ERR1ST                                                           */
+            __IM uint16_t D1ERR1ST : 1; /*!< [1..1] D1ERR1ST                                                           */
+            __IM uint16_t D2ERR1ST : 1; /*!< [2..2] D2ERR1ST                                                           */
+            __IM uint16_t D3ERR1ST : 1; /*!< [3..3] D3ERR1ST                                                           */
+            __IM uint16_t D4ERR1ST : 1; /*!< [4..4] D4ERR1ST                                                           */
+            __IM uint16_t D5ERR1ST : 1; /*!< [5..5] D5ERR1ST                                                           */
+            __IM uint16_t D6ERR1ST : 1; /*!< [6..6] D6ERR1ST                                                           */
+            __IM uint16_t D7ERR1ST : 1; /*!< [7..7] D7ERR1ST                                                           */
+            __IM uint16_t D8ERR1ST : 1; /*!< [8..8] D8ERR1ST                                                           */
+            __IM uint16_t D9ERR1ST : 1; /*!< [9..9] D9ERR1ST                                                           */
+            uint16_t               : 6;
+        } ICSR8_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR9;            /*!< (@ 0x00000032) Input Level Control/Status Register 9                      */
+
+        struct
+        {
+            __IOM uint16_t D0ERR0IE : 1; /*!< [0..0] D0ERR0IE                                                           */
+            __IOM uint16_t D1ERR0IE : 1; /*!< [1..1] D1ERR0IE                                                           */
+            __IOM uint16_t D2ERR0IE : 1; /*!< [2..2] D2ERR0IE                                                           */
+            __IOM uint16_t D3ERR0IE : 1; /*!< [3..3] D3ERR0IE                                                           */
+            __IOM uint16_t D4ERR0IE : 1; /*!< [4..4] D4ERR0IE                                                           */
+            __IOM uint16_t D5ERR0IE : 1; /*!< [5..5] D5ERR0IE                                                           */
+            __IOM uint16_t D6ERR0IE : 1; /*!< [6..6] D6ERR0IE                                                           */
+            __IOM uint16_t D7ERR0IE : 1; /*!< [7..7] D7ERR0IE                                                           */
+            __IOM uint16_t D8ERR0IE : 1; /*!< [8..8] D8ERR0IE                                                           */
+            __IOM uint16_t D9ERR0IE : 1; /*!< [9..9] D9ERR0IE                                                           */
+            uint16_t                : 6;
+        } ICSR9_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ICSR10;           /*!< (@ 0x00000034) Input Level Control/Status Register 10                     */
+
+        struct
+        {
+            __IOM uint16_t D0ERR1IE : 1; /*!< [0..0] D0ERR1IE                                                           */
+            __IOM uint16_t D1ERR1IE : 1; /*!< [1..1] D1ERR1IE                                                           */
+            __IOM uint16_t D2ERR1IE : 1; /*!< [2..2] D2ERR1IE                                                           */
+            __IOM uint16_t D3ERR1IE : 1; /*!< [3..3] D3ERR1IE                                                           */
+            __IOM uint16_t D4ERR1IE : 1; /*!< [4..4] D4ERR1IE                                                           */
+            __IOM uint16_t D5ERR1IE : 1; /*!< [5..5] D5ERR1IE                                                           */
+            __IOM uint16_t D6ERR1IE : 1; /*!< [6..6] D6ERR1IE                                                           */
+            __IOM uint16_t D7ERR1IE : 1; /*!< [7..7] D7ERR1IE                                                           */
+            __IOM uint16_t D8ERR1IE : 1; /*!< [8..8] D8ERR1IE                                                           */
+            __IOM uint16_t D9ERR1IE : 1; /*!< [9..9] D9ERR1IE                                                           */
+            uint16_t                : 6;
+        } ICSR10_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR7;               /*!< (@ 0x00000036) Port Output Enable Control Register 7                      */
+
+        struct
+        {
+            __IOM uint16_t D0E0ADDMT0ZE : 1; /*!< [0..0] MTU0 High-Impedance D0ERR0ST Add                                   */
+            __IOM uint16_t D1E0ADDMT0ZE : 1; /*!< [1..1] MTU0 High-Impedance D1ERR0ST Add                                   */
+            __IOM uint16_t D2E0ADDMT0ZE : 1; /*!< [2..2] MTU0 High-Impedance D2ERR0ST Add                                   */
+            __IOM uint16_t D3E0ADDMT0ZE : 1; /*!< [3..3] MTU0 High-Impedance D3ERR0ST Add                                   */
+            __IOM uint16_t D4E0ADDMT0ZE : 1; /*!< [4..4] MTU0 High-Impedance D4ERR0ST Add                                   */
+            __IOM uint16_t D5E0ADDMT0ZE : 1; /*!< [5..5] MTU0 High-Impedance D5ERR0ST Add                                   */
+            __IOM uint16_t D6E0ADDMT0ZE : 1; /*!< [6..6] MTU0 High-Impedance D6ERR0ST Add                                   */
+            __IOM uint16_t D7E0ADDMT0ZE : 1; /*!< [7..7] MTU0 High-Impedance D7ERR0ST Add                                   */
+            __IOM uint16_t D8E0ADDMT0ZE : 1; /*!< [8..8] MTU0 High-Impedance D8ERR0ST Add                                   */
+            __IOM uint16_t D9E0ADDMT0ZE : 1; /*!< [9..9] MTU0 High-Impedance D9ERR0ST Add                                   */
+            uint16_t                    : 6;
+        } POECR7_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR8;               /*!< (@ 0x00000038) Port Output Enable Control Register 8                      */
+
+        struct
+        {
+            __IOM uint16_t D0E1ADDMT0ZE : 1; /*!< [0..0] MTU0 High-Impedance D0ERR1ST Add                                   */
+            __IOM uint16_t D1E1ADDMT0ZE : 1; /*!< [1..1] MTU0 High-Impedance D1ERR1ST Add                                   */
+            __IOM uint16_t D2E1ADDMT0ZE : 1; /*!< [2..2] MTU0 High-Impedance D2ERR1ST Add                                   */
+            __IOM uint16_t D3E1ADDMT0ZE : 1; /*!< [3..3] MTU0 High-Impedance D3ERR1ST Add                                   */
+            __IOM uint16_t D4E1ADDMT0ZE : 1; /*!< [4..4] MTU0 High-Impedance D4ERR1ST Add                                   */
+            __IOM uint16_t D5E1ADDMT0ZE : 1; /*!< [5..5] MTU0 High-Impedance D5ERR1ST Add                                   */
+            __IOM uint16_t D6E1ADDMT0ZE : 1; /*!< [6..6] MTU0 High-Impedance D6ERR1ST Add                                   */
+            __IOM uint16_t D7E1ADDMT0ZE : 1; /*!< [7..7] MTU0 High-Impedance D7ERR1ST Add                                   */
+            __IOM uint16_t D8E1ADDMT0ZE : 1; /*!< [8..8] MTU0 High-Impedance D8ERR1ST Add                                   */
+            __IOM uint16_t D9E1ADDMT0ZE : 1; /*!< [9..9] MTU0 High-Impedance D9ERR1ST Add                                   */
+            uint16_t                    : 6;
+        } POECR8_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR9;                /*!< (@ 0x0000003A) Port Output Enable Control Register 9                      */
+
+        struct
+        {
+            __IOM uint16_t D0E0ADDMT34ZE : 1; /*!< [0..0] D0E0ADDMT34ZE                                                      */
+            __IOM uint16_t D1E0ADDMT34ZE : 1; /*!< [1..1] D1E0ADDMT34ZE                                                      */
+            __IOM uint16_t D2E0ADDMT34ZE : 1; /*!< [2..2] D2E0ADDMT34ZE                                                      */
+            __IOM uint16_t D3E0ADDMT34ZE : 1; /*!< [3..3] D3E0ADDMT34ZE                                                      */
+            __IOM uint16_t D4E0ADDMT34ZE : 1; /*!< [4..4] D4E0ADDMT34ZE                                                      */
+            __IOM uint16_t D5E0ADDMT34ZE : 1; /*!< [5..5] D5E0ADDMT34ZE                                                      */
+            __IOM uint16_t D6E0ADDMT34ZE : 1; /*!< [6..6] D6E0ADDMT34ZE                                                      */
+            __IOM uint16_t D7E0ADDMT34ZE : 1; /*!< [7..7] D7E0ADDMT34ZE                                                      */
+            __IOM uint16_t D8E0ADDMT34ZE : 1; /*!< [8..8] D8E0ADDMT34ZE                                                      */
+            __IOM uint16_t D9E0ADDMT34ZE : 1; /*!< [9..9] D9E0ADDMT34ZE                                                      */
+            uint16_t                     : 6;
+        } POECR9_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR10;               /*!< (@ 0x0000003C) Port Output Enable Control Register 10                     */
+
+        struct
+        {
+            __IOM uint16_t D0E1ADDMT34ZE : 1; /*!< [0..0] D0E1ADDMT34ZE                                                      */
+            __IOM uint16_t D1E1ADDMT34ZE : 1; /*!< [1..1] D1E1ADDMT34ZE                                                      */
+            __IOM uint16_t D2E1ADDMT34ZE : 1; /*!< [2..2] D2E1ADDMT34ZE                                                      */
+            __IOM uint16_t D3E1ADDMT34ZE : 1; /*!< [3..3] D3E1ADDMT34ZE                                                      */
+            __IOM uint16_t D4E1ADDMT34ZE : 1; /*!< [4..4] D4E1ADDMT34ZE                                                      */
+            __IOM uint16_t D5E1ADDMT34ZE : 1; /*!< [5..5] D5E1ADDMT34ZE                                                      */
+            __IOM uint16_t D6E1ADDMT34ZE : 1; /*!< [6..6] D6E1ADDMT34ZE                                                      */
+            __IOM uint16_t D7E1ADDMT34ZE : 1; /*!< [7..7] D7E1ADDMT34ZE                                                      */
+            __IOM uint16_t D8E1ADDMT34ZE : 1; /*!< [8..8] D8E1ADDMT34ZE                                                      */
+            __IOM uint16_t D9E1ADDMT34ZE : 1; /*!< [9..9] D9E1ADDMT34ZE                                                      */
+            uint16_t                     : 6;
+        } POECR10_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR11;               /*!< (@ 0x0000003E) Port Output Enable Control Register 11                     */
+
+        struct
+        {
+            __IOM uint16_t D0E0ADDMT67ZE : 1; /*!< [0..0] D0E0ADDMT67ZE                                                      */
+            __IOM uint16_t D1E0ADDMT67ZE : 1; /*!< [1..1] D1E0ADDMT67ZE                                                      */
+            __IOM uint16_t D2E0ADDMT67ZE : 1; /*!< [2..2] D2E0ADDMT67ZE                                                      */
+            __IOM uint16_t D3E0ADDMT67ZE : 1; /*!< [3..3] D3E0ADDMT67ZE                                                      */
+            __IOM uint16_t D4E0ADDMT67ZE : 1; /*!< [4..4] D4E0ADDMT67ZE                                                      */
+            __IOM uint16_t D5E0ADDMT67ZE : 1; /*!< [5..5] D5E0ADDMT67ZE                                                      */
+            __IOM uint16_t D6E0ADDMT67ZE : 1; /*!< [6..6] D6E0ADDMT67ZE                                                      */
+            __IOM uint16_t D7E0ADDMT67ZE : 1; /*!< [7..7] D7E0ADDMT67ZE                                                      */
+            __IOM uint16_t D8E0ADDMT67ZE : 1; /*!< [8..8] D8E0ADDMT67ZE                                                      */
+            __IOM uint16_t D9E0ADDMT67ZE : 1; /*!< [9..9] D9E0ADDMT67ZE                                                      */
+            uint16_t                     : 6;
+        } POECR11_b;
+    };
+
+    union
+    {
+        __IOM uint16_t POECR12;               /*!< (@ 0x00000040) Port Output Enable Control Register 12                     */
+
+        struct
+        {
+            __IOM uint16_t D0E1ADDMT67ZE : 1; /*!< [0..0] D0E1ADDMT67ZE                                                      */
+            __IOM uint16_t D1E1ADDMT67ZE : 1; /*!< [1..1] D1E1ADDMT67ZE                                                      */
+            __IOM uint16_t D2E1ADDMT67ZE : 1; /*!< [2..2] D2E1ADDMT67ZE                                                      */
+            __IOM uint16_t D3E1ADDMT67ZE : 1; /*!< [3..3] D3E1ADDMT67ZE                                                      */
+            __IOM uint16_t D4E1ADDMT67ZE : 1; /*!< [4..4] D4E1ADDMT67ZE                                                      */
+            __IOM uint16_t D5E1ADDMT67ZE : 1; /*!< [5..5] D5E1ADDMT67ZE                                                      */
+            __IOM uint16_t D6E1ADDMT67ZE : 1; /*!< [6..6] D6E1ADDMT67ZE                                                      */
+            __IOM uint16_t D7E1ADDMT67ZE : 1; /*!< [7..7] D7E1ADDMT67ZE                                                      */
+            __IOM uint16_t D8E1ADDMT67ZE : 1; /*!< [8..8] D8E1ADDMT67ZE                                                      */
+            __IOM uint16_t D9E1ADDMT67ZE : 1; /*!< [9..9] D9E1ADDMT67ZE                                                      */
+            uint16_t                     : 6;
+        } POECR12_b;
+    };
+} R_POE3_Type;                                /*!< Size = 66 (0x42)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief GPT Port Output Enable 0 (R_POEG0)
+ */
+
+typedef struct                         /*!< (@ 0x90019000) R_POEG0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t POEG0GA0;       /*!< (@ 0x00000000) POEG0 Group A Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG0GA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t POEG0GA1;         /*!< (@ 0x00000004) POEG0 Group A Setting Register 1                           */
+
+        struct
+        {
+            __IM uint32_t D0ERR0ST : 1; /*!< [0..0] D0ERR0ST                                                           */
+            __IM uint32_t D1ERR0ST : 1; /*!< [1..1] D1ERR0ST                                                           */
+            __IM uint32_t D2ERR0ST : 1; /*!< [2..2] D2ERR0ST                                                           */
+            __IM uint32_t D3ERR0ST : 1; /*!< [3..3] D3ERR0ST                                                           */
+            __IM uint32_t D4ERR0ST : 1; /*!< [4..4] D4ERR0ST                                                           */
+            __IM uint32_t D5ERR0ST : 1; /*!< [5..5] D5ERR0ST                                                           */
+            __IM uint32_t D6ERR0ST : 1; /*!< [6..6] D6ERR0ST                                                           */
+            __IM uint32_t D7ERR0ST : 1; /*!< [7..7] D7ERR0ST                                                           */
+            __IM uint32_t D8ERR0ST : 1; /*!< [8..8] D8ERR0ST                                                           */
+            __IM uint32_t D9ERR0ST : 1; /*!< [9..9] D9ERR0ST                                                           */
+            uint32_t               : 6;
+            __IM uint32_t D0ERR1ST : 1; /*!< [16..16] D0ERR1ST                                                         */
+            __IM uint32_t D1ERR1ST : 1; /*!< [17..17] D1ERR1ST                                                         */
+            __IM uint32_t D2ERR1ST : 1; /*!< [18..18] D2ERR1ST                                                         */
+            __IM uint32_t D3ERR1ST : 1; /*!< [19..19] D3ERR1ST                                                         */
+            __IM uint32_t D4ERR1ST : 1; /*!< [20..20] D4ERR1ST                                                         */
+            __IM uint32_t D5ERR1ST : 1; /*!< [21..21] D5ERR1ST                                                         */
+            __IM uint32_t D6ERR1ST : 1; /*!< [22..22] D6ERR1ST                                                         */
+            __IM uint32_t D7ERR1ST : 1; /*!< [23..23] D7ERR1ST                                                         */
+            __IM uint32_t D8ERR1ST : 1; /*!< [24..24] D8ERR1ST                                                         */
+            __IM uint32_t D9ERR1ST : 1; /*!< [25..25] D9ERR1ST                                                         */
+            uint32_t               : 6;
+        } POEG0GA1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t POEG0GA2;        /*!< (@ 0x00000008) POEG0 Group A Setting Register 2                           */
+
+        struct
+        {
+            __IOM uint32_t D0ERR0E : 1; /*!< [0..0] D0ERR0E                                                            */
+            __IOM uint32_t D1ERR0E : 1; /*!< [1..1] D1ERR0E                                                            */
+            __IOM uint32_t D2ERR0E : 1; /*!< [2..2] D2ERR0E                                                            */
+            __IOM uint32_t D3ERR0E : 1; /*!< [3..3] D3ERR0E                                                            */
+            __IOM uint32_t D4ERR0E : 1; /*!< [4..4] D4ERR0E                                                            */
+            __IOM uint32_t D5ERR0E : 1; /*!< [5..5] D5ERR0E                                                            */
+            __IOM uint32_t D6ERR0E : 1; /*!< [6..6] D6ERR0E                                                            */
+            __IOM uint32_t D7ERR0E : 1; /*!< [7..7] D7ERR0E                                                            */
+            __IOM uint32_t D8ERR0E : 1; /*!< [8..8] D8ERR0E                                                            */
+            __IOM uint32_t D9ERR0E : 1; /*!< [9..9] D9ERR0E                                                            */
+            uint32_t               : 6;
+            __IOM uint32_t D0ERR1E : 1; /*!< [16..16] D0ERR1E                                                          */
+            __IOM uint32_t D1ERR1E : 1; /*!< [17..17] D1ERR1E                                                          */
+            __IOM uint32_t D2ERR1E : 1; /*!< [18..18] D2ERR1E                                                          */
+            __IOM uint32_t D3ERR1E : 1; /*!< [19..19] D3ERR1E                                                          */
+            __IOM uint32_t D4ERR1E : 1; /*!< [20..20] D4ERR1E                                                          */
+            __IOM uint32_t D5ERR1E : 1; /*!< [21..21] D5ERR1E                                                          */
+            __IOM uint32_t D6ERR1E : 1; /*!< [22..22] D6ERR1E                                                          */
+            __IOM uint32_t D7ERR1E : 1; /*!< [23..23] D7ERR1E                                                          */
+            __IOM uint32_t D8ERR1E : 1; /*!< [24..24] D8ERR1E                                                          */
+            __IOM uint32_t D9ERR1E : 1; /*!< [25..25] D9ERR1E                                                          */
+            uint32_t               : 6;
+        } POEG0GA2_b;
+    };
+    __IM uint32_t RESERVED[253];
+
+    union
+    {
+        __IOM uint32_t POEG0GB0;       /*!< (@ 0x00000400) POEG0 Group B Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG0GB0_b;
+    };
+
+    union
+    {
+        __IM uint32_t POEG0GB1;         /*!< (@ 0x00000404) POEG0 Group B Setting Register 1                           */
+
+        struct
+        {
+            __IM uint32_t D0ERR0ST : 1; /*!< [0..0] D0ERR0ST                                                           */
+            __IM uint32_t D1ERR0ST : 1; /*!< [1..1] D1ERR0ST                                                           */
+            __IM uint32_t D2ERR0ST : 1; /*!< [2..2] D2ERR0ST                                                           */
+            __IM uint32_t D3ERR0ST : 1; /*!< [3..3] D3ERR0ST                                                           */
+            __IM uint32_t D4ERR0ST : 1; /*!< [4..4] D4ERR0ST                                                           */
+            __IM uint32_t D5ERR0ST : 1; /*!< [5..5] D5ERR0ST                                                           */
+            __IM uint32_t D6ERR0ST : 1; /*!< [6..6] D6ERR0ST                                                           */
+            __IM uint32_t D7ERR0ST : 1; /*!< [7..7] D7ERR0ST                                                           */
+            __IM uint32_t D8ERR0ST : 1; /*!< [8..8] D8ERR0ST                                                           */
+            __IM uint32_t D9ERR0ST : 1; /*!< [9..9] D9ERR0ST                                                           */
+            uint32_t               : 6;
+            __IM uint32_t D0ERR1ST : 1; /*!< [16..16] D0ERR1ST                                                         */
+            __IM uint32_t D1ERR1ST : 1; /*!< [17..17] D1ERR1ST                                                         */
+            __IM uint32_t D2ERR1ST : 1; /*!< [18..18] D2ERR1ST                                                         */
+            __IM uint32_t D3ERR1ST : 1; /*!< [19..19] D3ERR1ST                                                         */
+            __IM uint32_t D4ERR1ST : 1; /*!< [20..20] D4ERR1ST                                                         */
+            __IM uint32_t D5ERR1ST : 1; /*!< [21..21] D5ERR1ST                                                         */
+            __IM uint32_t D6ERR1ST : 1; /*!< [22..22] D6ERR1ST                                                         */
+            __IM uint32_t D7ERR1ST : 1; /*!< [23..23] D7ERR1ST                                                         */
+            __IM uint32_t D8ERR1ST : 1; /*!< [24..24] D8ERR1ST                                                         */
+            __IM uint32_t D9ERR1ST : 1; /*!< [25..25] D9ERR1ST                                                         */
+            uint32_t               : 6;
+        } POEG0GB1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t POEG0GB2;        /*!< (@ 0x00000408) POEG0 Group B Setting Register 2                           */
+
+        struct
+        {
+            __IOM uint32_t D0ERR0E : 1; /*!< [0..0] D0ERR0E                                                            */
+            __IOM uint32_t D1ERR0E : 1; /*!< [1..1] D1ERR0E                                                            */
+            __IOM uint32_t D2ERR0E : 1; /*!< [2..2] D2ERR0E                                                            */
+            __IOM uint32_t D3ERR0E : 1; /*!< [3..3] D3ERR0E                                                            */
+            __IOM uint32_t D4ERR0E : 1; /*!< [4..4] D4ERR0E                                                            */
+            __IOM uint32_t D5ERR0E : 1; /*!< [5..5] D5ERR0E                                                            */
+            __IOM uint32_t D6ERR0E : 1; /*!< [6..6] D6ERR0E                                                            */
+            __IOM uint32_t D7ERR0E : 1; /*!< [7..7] D7ERR0E                                                            */
+            __IOM uint32_t D8ERR0E : 1; /*!< [8..8] D8ERR0E                                                            */
+            __IOM uint32_t D9ERR0E : 1; /*!< [9..9] D9ERR0E                                                            */
+            uint32_t               : 6;
+            __IOM uint32_t D0ERR1E : 1; /*!< [16..16] D0ERR1E                                                          */
+            __IOM uint32_t D1ERR1E : 1; /*!< [17..17] D1ERR1E                                                          */
+            __IOM uint32_t D2ERR1E : 1; /*!< [18..18] D2ERR1E                                                          */
+            __IOM uint32_t D3ERR1E : 1; /*!< [19..19] D3ERR1E                                                          */
+            __IOM uint32_t D4ERR1E : 1; /*!< [20..20] D4ERR1E                                                          */
+            __IOM uint32_t D5ERR1E : 1; /*!< [21..21] D5ERR1E                                                          */
+            __IOM uint32_t D6ERR1E : 1; /*!< [22..22] D6ERR1E                                                          */
+            __IOM uint32_t D7ERR1E : 1; /*!< [23..23] D7ERR1E                                                          */
+            __IOM uint32_t D8ERR1E : 1; /*!< [24..24] D8ERR1E                                                          */
+            __IOM uint32_t D9ERR1E : 1; /*!< [25..25] D9ERR1E                                                          */
+            uint32_t               : 6;
+        } POEG0GB2_b;
+    };
+    __IM uint32_t RESERVED1[253];
+
+    union
+    {
+        __IOM uint32_t POEG0GC0;       /*!< (@ 0x00000800) POEG0 Group C Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG0GC0_b;
+    };
+
+    union
+    {
+        __IM uint32_t POEG0GC1;         /*!< (@ 0x00000804) POEG0 Group C Setting Register 1                           */
+
+        struct
+        {
+            __IM uint32_t D0ERR0ST : 1; /*!< [0..0] D0ERR0ST                                                           */
+            __IM uint32_t D1ERR0ST : 1; /*!< [1..1] D1ERR0ST                                                           */
+            __IM uint32_t D2ERR0ST : 1; /*!< [2..2] D2ERR0ST                                                           */
+            __IM uint32_t D3ERR0ST : 1; /*!< [3..3] D3ERR0ST                                                           */
+            __IM uint32_t D4ERR0ST : 1; /*!< [4..4] D4ERR0ST                                                           */
+            __IM uint32_t D5ERR0ST : 1; /*!< [5..5] D5ERR0ST                                                           */
+            __IM uint32_t D6ERR0ST : 1; /*!< [6..6] D6ERR0ST                                                           */
+            __IM uint32_t D7ERR0ST : 1; /*!< [7..7] D7ERR0ST                                                           */
+            __IM uint32_t D8ERR0ST : 1; /*!< [8..8] D8ERR0ST                                                           */
+            __IM uint32_t D9ERR0ST : 1; /*!< [9..9] D9ERR0ST                                                           */
+            uint32_t               : 6;
+            __IM uint32_t D0ERR1ST : 1; /*!< [16..16] D0ERR1ST                                                         */
+            __IM uint32_t D1ERR1ST : 1; /*!< [17..17] D1ERR1ST                                                         */
+            __IM uint32_t D2ERR1ST : 1; /*!< [18..18] D2ERR1ST                                                         */
+            __IM uint32_t D3ERR1ST : 1; /*!< [19..19] D3ERR1ST                                                         */
+            __IM uint32_t D4ERR1ST : 1; /*!< [20..20] D4ERR1ST                                                         */
+            __IM uint32_t D5ERR1ST : 1; /*!< [21..21] D5ERR1ST                                                         */
+            __IM uint32_t D6ERR1ST : 1; /*!< [22..22] D6ERR1ST                                                         */
+            __IM uint32_t D7ERR1ST : 1; /*!< [23..23] D7ERR1ST                                                         */
+            __IM uint32_t D8ERR1ST : 1; /*!< [24..24] D8ERR1ST                                                         */
+            __IM uint32_t D9ERR1ST : 1; /*!< [25..25] D9ERR1ST                                                         */
+            uint32_t               : 6;
+        } POEG0GC1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t POEG0GC2;        /*!< (@ 0x00000808) POEG0 Group C Setting Register 2                           */
+
+        struct
+        {
+            __IOM uint32_t D0ERR0E : 1; /*!< [0..0] D0ERR0E                                                            */
+            __IOM uint32_t D1ERR0E : 1; /*!< [1..1] D1ERR0E                                                            */
+            __IOM uint32_t D2ERR0E : 1; /*!< [2..2] D2ERR0E                                                            */
+            __IOM uint32_t D3ERR0E : 1; /*!< [3..3] D3ERR0E                                                            */
+            __IOM uint32_t D4ERR0E : 1; /*!< [4..4] D4ERR0E                                                            */
+            __IOM uint32_t D5ERR0E : 1; /*!< [5..5] D5ERR0E                                                            */
+            __IOM uint32_t D6ERR0E : 1; /*!< [6..6] D6ERR0E                                                            */
+            __IOM uint32_t D7ERR0E : 1; /*!< [7..7] D7ERR0E                                                            */
+            __IOM uint32_t D8ERR0E : 1; /*!< [8..8] D8ERR0E                                                            */
+            __IOM uint32_t D9ERR0E : 1; /*!< [9..9] D9ERR0E                                                            */
+            uint32_t               : 6;
+            __IOM uint32_t D0ERR1E : 1; /*!< [16..16] D0ERR1E                                                          */
+            __IOM uint32_t D1ERR1E : 1; /*!< [17..17] D1ERR1E                                                          */
+            __IOM uint32_t D2ERR1E : 1; /*!< [18..18] D2ERR1E                                                          */
+            __IOM uint32_t D3ERR1E : 1; /*!< [19..19] D3ERR1E                                                          */
+            __IOM uint32_t D4ERR1E : 1; /*!< [20..20] D4ERR1E                                                          */
+            __IOM uint32_t D5ERR1E : 1; /*!< [21..21] D5ERR1E                                                          */
+            __IOM uint32_t D6ERR1E : 1; /*!< [22..22] D6ERR1E                                                          */
+            __IOM uint32_t D7ERR1E : 1; /*!< [23..23] D7ERR1E                                                          */
+            __IOM uint32_t D8ERR1E : 1; /*!< [24..24] D8ERR1E                                                          */
+            __IOM uint32_t D9ERR1E : 1; /*!< [25..25] D9ERR1E                                                          */
+            uint32_t               : 6;
+        } POEG0GC2_b;
+    };
+    __IM uint32_t RESERVED2[253];
+
+    union
+    {
+        __IOM uint32_t POEG0GD0;       /*!< (@ 0x00000C00) POEG0 Group D Setting Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
+            __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
+            uint32_t             : 9;
+            __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
+            uint32_t             : 11;
+            __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
+        } POEG0GD0_b;
+    };
+
+    union
+    {
+        __IM uint32_t POEG0GD1;         /*!< (@ 0x00000C04) POEG0 Group D Setting Register 1                           */
+
+        struct
+        {
+            __IM uint32_t D0ERR0ST : 1; /*!< [0..0] D0ERR0ST                                                           */
+            __IM uint32_t D1ERR0ST : 1; /*!< [1..1] D1ERR0ST                                                           */
+            __IM uint32_t D2ERR0ST : 1; /*!< [2..2] D2ERR0ST                                                           */
+            __IM uint32_t D3ERR0ST : 1; /*!< [3..3] D3ERR0ST                                                           */
+            __IM uint32_t D4ERR0ST : 1; /*!< [4..4] D4ERR0ST                                                           */
+            __IM uint32_t D5ERR0ST : 1; /*!< [5..5] D5ERR0ST                                                           */
+            __IM uint32_t D6ERR0ST : 1; /*!< [6..6] D6ERR0ST                                                           */
+            __IM uint32_t D7ERR0ST : 1; /*!< [7..7] D7ERR0ST                                                           */
+            __IM uint32_t D8ERR0ST : 1; /*!< [8..8] D8ERR0ST                                                           */
+            __IM uint32_t D9ERR0ST : 1; /*!< [9..9] D9ERR0ST                                                           */
+            uint32_t               : 6;
+            __IM uint32_t D0ERR1ST : 1; /*!< [16..16] D0ERR1ST                                                         */
+            __IM uint32_t D1ERR1ST : 1; /*!< [17..17] D1ERR1ST                                                         */
+            __IM uint32_t D2ERR1ST : 1; /*!< [18..18] D2ERR1ST                                                         */
+            __IM uint32_t D3ERR1ST : 1; /*!< [19..19] D3ERR1ST                                                         */
+            __IM uint32_t D4ERR1ST : 1; /*!< [20..20] D4ERR1ST                                                         */
+            __IM uint32_t D5ERR1ST : 1; /*!< [21..21] D5ERR1ST                                                         */
+            __IM uint32_t D6ERR1ST : 1; /*!< [22..22] D6ERR1ST                                                         */
+            __IM uint32_t D7ERR1ST : 1; /*!< [23..23] D7ERR1ST                                                         */
+            __IM uint32_t D8ERR1ST : 1; /*!< [24..24] D8ERR1ST                                                         */
+            __IM uint32_t D9ERR1ST : 1; /*!< [25..25] D9ERR1ST                                                         */
+            uint32_t               : 6;
+        } POEG0GD1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t POEG0GD2;        /*!< (@ 0x00000C08) POEG0 Group D Setting Register 2                           */
+
+        struct
+        {
+            __IOM uint32_t D0ERR0E : 1; /*!< [0..0] D0ERR0E                                                            */
+            __IOM uint32_t D1ERR0E : 1; /*!< [1..1] D1ERR0E                                                            */
+            __IOM uint32_t D2ERR0E : 1; /*!< [2..2] D2ERR0E                                                            */
+            __IOM uint32_t D3ERR0E : 1; /*!< [3..3] D3ERR0E                                                            */
+            __IOM uint32_t D4ERR0E : 1; /*!< [4..4] D4ERR0E                                                            */
+            __IOM uint32_t D5ERR0E : 1; /*!< [5..5] D5ERR0E                                                            */
+            __IOM uint32_t D6ERR0E : 1; /*!< [6..6] D6ERR0E                                                            */
+            __IOM uint32_t D7ERR0E : 1; /*!< [7..7] D7ERR0E                                                            */
+            __IOM uint32_t D8ERR0E : 1; /*!< [8..8] D8ERR0E                                                            */
+            __IOM uint32_t D9ERR0E : 1; /*!< [9..9] D9ERR0E                                                            */
+            uint32_t               : 6;
+            __IOM uint32_t D0ERR1E : 1; /*!< [16..16] D0ERR1E                                                          */
+            __IOM uint32_t D1ERR1E : 1; /*!< [17..17] D1ERR1E                                                          */
+            __IOM uint32_t D2ERR1E : 1; /*!< [18..18] D2ERR1E                                                          */
+            __IOM uint32_t D3ERR1E : 1; /*!< [19..19] D3ERR1E                                                          */
+            __IOM uint32_t D4ERR1E : 1; /*!< [20..20] D4ERR1E                                                          */
+            __IOM uint32_t D5ERR1E : 1; /*!< [21..21] D5ERR1E                                                          */
+            __IOM uint32_t D6ERR1E : 1; /*!< [22..22] D6ERR1E                                                          */
+            __IOM uint32_t D7ERR1E : 1; /*!< [23..23] D7ERR1E                                                          */
+            __IOM uint32_t D8ERR1E : 1; /*!< [24..24] D8ERR1E                                                          */
+            __IOM uint32_t D9ERR1E : 1; /*!< [25..25] D9ERR1E                                                          */
+            uint32_t               : 6;
+        } POEG0GD2_b;
+    };
+} R_POEG0_Type;                         /*!< Size = 3084 (0xc0c)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_DSMIF0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Delta-sigma Interface 0 (R_DSMIF0)
+ */
+
+typedef struct                         /*!< (@ 0x90020000) R_DSMIF0 Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t DSCCSCR;        /*!< (@ 0x00000000) Core Clock Selection Control Register                      */
+
+        struct
+        {
+            __IOM uint32_t CLKSEL : 1; /*!< [0..0] CLKSEL                                                             */
+            uint32_t              : 31;
+        } DSCCSCR_b;
+    };
+    __IM uint32_t RESERVED[31];
+
+    union
+    {
+        __IOM uint32_t DSSEICR;        /*!< (@ 0x00000080) Overcurrent Sum Error Detect Interrupt Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t ISEL : 1;   /*!< [0..0] Overcurrent sum error lower limit detection interrupt
+                                        *   enable bit                                                                */
+            __IOM uint32_t ISEH : 1;   /*!< [1..1] Overcurrent sum error upper limit detection interrupt
+                                        *   enable bit                                                                */
+            uint32_t : 30;
+        } DSSEICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSECSR;        /*!< (@ 0x00000084) Overcurrent Sum Error Detect Channel Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t SEDM : 3;   /*!< [2..0] Overcurrent sum error detect mode setting bit                      */
+            uint32_t            : 29;
+        } DSSECSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSELTR;          /*!< (@ 0x00000088) Overcurrent Sum Error Detect Low Threshold Register        */
+
+        struct
+        {
+            __IOM uint32_t SCMPTBL : 18; /*!< [17..0] Overcurrent sum error detect lower limit                          */
+            uint32_t               : 14;
+        } DSSELTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSEHTR;          /*!< (@ 0x0000008C) Overcurrent Sum Error Detect High Threshold Register       */
+
+        struct
+        {
+            __IOM uint32_t SCMPTBH : 18; /*!< [17..0] Overcurrent sum error detect upper limit                          */
+            uint32_t               : 14;
+        } DSSEHTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSSECR;         /*!< (@ 0x00000090) Overcurrent Sum Error Detect Control Register              */
+
+        struct
+        {
+            __IOM uint32_t SEEL : 1;   /*!< [0..0] Overcurrent sum error lower limit detection enable bit             */
+            __IOM uint32_t SEEH : 1;   /*!< [1..1] Overcurrent sum error upper limit detection enable bit             */
+            uint32_t            : 30;
+        } DSSECR_b;
+    };
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint32_t DSSECDR[3];     /*!< (@ 0x000000A0) Overcurrent Sum Error Detect Capture Data Register
+                                        *                  [0..2]                                                     */
+
+        struct
+        {
+            __IOM uint32_t SECDR : 16; /*!< [15..0] Overcurrent sum error detect capture data n                       */
+            uint32_t             : 16;
+        } DSSECDR_b[3];
+    };
+    __IM uint32_t RESERVED2[5];
+
+    union
+    {
+        __IOM uint32_t DSCMSR;         /*!< (@ 0x000000C0) Common Mode Setting Register                               */
+
+        struct
+        {
+            __IOM uint32_t DFS  : 1;   /*!< [0..0] Data Format Select                                                 */
+            __IOM uint32_t CISM : 2;   /*!< [2..1] Common Interrupt Synchronous channel Mode                          */
+            uint32_t            : 29;
+        } DSCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCICR;         /*!< (@ 0x000000C4) Common Interrupt Control Register                          */
+
+        struct
+        {
+            __IOM uint32_t IUCE : 1;   /*!< [0..0] Current data register update channel common interrupt
+                                        *   enable                                                                    */
+            __IOM uint32_t IAUCE : 1;  /*!< [1..1] Capture current data register A update channel common
+                                        *   interrupt enable                                                          */
+            __IOM uint32_t IBUCE : 1;  /*!< [2..2] Capture current data register B update channel common
+                                        *   interrupt enable                                                          */
+            uint32_t : 29;
+        } DSCICR_b;
+    };
+    __IM uint32_t RESERVED3[78];
+
+    union
+    {
+        __IOM uint32_t DSCSTRTR;        /*!< (@ 0x00000200) Channel Software Start Trigger Register                    */
+
+        struct
+        {
+            __IOM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger                                            */
+            __IOM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger                                            */
+            __IOM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger                                            */
+            uint32_t               : 29;
+        } DSCSTRTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCSTPTR;        /*!< (@ 0x00000204) Channel Software Stop Trigger Register                     */
+
+        struct
+        {
+            __IOM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger                                             */
+            __IOM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger                                             */
+            __IOM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger                                             */
+            uint32_t               : 29;
+        } DSCSTPTR_b;
+    };
+    __IM uint32_t RESERVED4[6];
+
+    union
+    {
+        __IM uint32_t DSCESR;          /*!< (@ 0x00000220) Channel Error Status Register                              */
+
+        struct
+        {
+            __IM uint32_t SCF0    : 1; /*!< [0..0] Channel 0 short circuit detection flag                             */
+            __IM uint32_t SCF1    : 1; /*!< [1..1] Channel 1 short circuit detection flag                             */
+            __IM uint32_t SCF2    : 1; /*!< [2..2] Channel 2 short circuit detection flag                             */
+            uint32_t              : 13;
+            __IM uint32_t SUMERRL : 1; /*!< [16..16] Overcurrent sum error lower limit detection flag                 */
+            __IM uint32_t SUMERRH : 1; /*!< [17..17] Overcurrent sum error upper limit detection flag                 */
+            uint32_t              : 14;
+        } DSCESR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCOCESR;        /*!< (@ 0x00000224) Channel Overcurrent Error Status Register                  */
+
+        struct
+        {
+            __IM uint32_t OC0FL0 : 1;  /*!< [0..0] Channel 0 overcurrent lower limit detection 0 flag                 */
+            __IM uint32_t OC0FL1 : 1;  /*!< [1..1] Channel 1 overcurrent lower limit detection 0 flag                 */
+            __IM uint32_t OC0FL2 : 1;  /*!< [2..2] Channel 2 overcurrent lower limit detection 0 flag                 */
+            uint32_t             : 1;
+            __IM uint32_t OC0FH0 : 1;  /*!< [4..4] Channel 0 overcurrent upper limit exceeded 0 flag                  */
+            __IM uint32_t OC0FH1 : 1;  /*!< [5..5] Channel 1 overcurrent upper limit exceeded 0 flag                  */
+            __IM uint32_t OC0FH2 : 1;  /*!< [6..6] Channel 2 overcurrent upper limit exceeded 0 flag                  */
+            uint32_t             : 1;
+            __IM uint32_t OC1FL0 : 1;  /*!< [8..8] Channel 0 overcurrent lower limit detection 1 flag                 */
+            __IM uint32_t OC1FL1 : 1;  /*!< [9..9] Channel 1 overcurrent lower limit detection 1 flag                 */
+            __IM uint32_t OC1FL2 : 1;  /*!< [10..10] Channel 2 overcurrent lower limit detection 1 flag               */
+            uint32_t             : 1;
+            __IM uint32_t OC1FH0 : 1;  /*!< [12..12] Channel 0 overcurrent upper limit exceeded 1 flag                */
+            __IM uint32_t OC1FH1 : 1;  /*!< [13..13] Channel 1 overcurrent upper limit exceeded 1 flag                */
+            __IM uint32_t OC1FH2 : 1;  /*!< [14..14] Channel 2 overcurrent upper limit exceeded 1 flag                */
+            uint32_t             : 1;
+            __IM uint32_t OC2FL0 : 1;  /*!< [16..16] Channel 0 overcurrent lower limit detection 2 flag               */
+            __IM uint32_t OC2FL1 : 1;  /*!< [17..17] Channel 1 overcurrent lower limit detection 2 flag               */
+            __IM uint32_t OC2FL2 : 1;  /*!< [18..18] Channel 2 overcurrent lower limit detection 2 flag               */
+            uint32_t             : 1;
+            __IM uint32_t OC2FH0 : 1;  /*!< [20..20] Channel 0 overcurrent upper limit exceeded 2 flag                */
+            __IM uint32_t OC2FH1 : 1;  /*!< [21..21] Channel 1 overcurrent upper limit exceeded 2 flag                */
+            __IM uint32_t OC2FH2 : 1;  /*!< [22..22] Channel 2 overcurrent upper limit exceeded 2 flag                */
+            uint32_t             : 9;
+        } DSCOCESR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCOCNSR;        /*!< (@ 0x00000228) Channel Overcurrent Notification Status Register           */
+
+        struct
+        {
+            __IM uint32_t OWD0N0 : 1;  /*!< [0..0] Channel 0 overcurrent detection window notification 0
+                                        *   flag                                                                      */
+            __IM uint32_t OWD0N1 : 1;  /*!< [1..1] Channel 1 overcurrent detection window notification 0
+                                        *   flag                                                                      */
+            __IM uint32_t OWD0N2 : 1;  /*!< [2..2] Channel 2 overcurrent detection window notification 0
+                                        *   flag                                                                      */
+            uint32_t             : 1;
+            __IM uint32_t OWD1N0 : 1;  /*!< [4..4] Channel 0 overcurrent detection window notification 1
+                                        *   flag                                                                      */
+            __IM uint32_t OWD1N1 : 1;  /*!< [5..5] Channel 1 overcurrent detection window notification 1
+                                        *   flag                                                                      */
+            __IM uint32_t OWD1N2 : 1;  /*!< [6..6] Channel 2 overcurrent detection window notification 1
+                                        *   flag                                                                      */
+            uint32_t             : 1;
+            __IM uint32_t OWD2N0 : 1;  /*!< [8..8] Channel 0 overcurrent detection window notification 2
+                                        *   flag                                                                      */
+            __IM uint32_t OWD2N1 : 1;  /*!< [9..9] Channel 1 overcurrent detection window notification 2
+                                        *   flag                                                                      */
+            __IM uint32_t OWD2N2 : 1;  /*!< [10..10] Channel 2 overcurrent detection window notification
+                                        *   2 flag                                                                    */
+            uint32_t             : 1;
+            __IM uint32_t OWD3N0 : 1;  /*!< [12..12] Channel 0 overcurrent detection window notification
+                                        *   3 flag                                                                    */
+            __IM uint32_t OWD3N1 : 1;  /*!< [13..13] Channel 1 overcurrent detection window notification
+                                        *   3 flag                                                                    */
+            __IM uint32_t OWD3N2 : 1;  /*!< [14..14] Channel 2 overcurrent detection window notification
+                                        *   3 flag                                                                    */
+            uint32_t : 17;
+        } DSCOCNSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCOCRMR;         /*!< (@ 0x0000022C) Channel Overcurrent Comparator Result Monitor
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t OC0CMPL0 : 1; /*!< [0..0] Channel 0 overcurrent detect 0 lower limit compare result          */
+            __IM uint32_t OC0CMPL1 : 1; /*!< [1..1] Channel 1 overcurrent detect 0 lower limit compare result          */
+            __IM uint32_t OC0CMPL2 : 1; /*!< [2..2] Channel 2 overcurrent detect 0 lower limit compare result          */
+            uint32_t               : 1;
+            __IM uint32_t OC0CMPH0 : 1; /*!< [4..4] Channel 0 overcurrent detect 0 upper limit compare result          */
+            __IM uint32_t OC0CMPH1 : 1; /*!< [5..5] Channel 1 overcurrent detect 0 upper limit compare result          */
+            __IM uint32_t OC0CMPH2 : 1; /*!< [6..6] Channel 2 overcurrent detect 0 upper limit compare result          */
+            uint32_t               : 1;
+            __IM uint32_t OC1CMPL0 : 1; /*!< [8..8] Channel 0 overcurrent detect 1 lower limit compare result          */
+            __IM uint32_t OC1CMPL1 : 1; /*!< [9..9] Channel 1 overcurrent detect 1 lower limit compare result          */
+            __IM uint32_t OC1CMPL2 : 1; /*!< [10..10] Channel 2 overcurrent detect 1 lower limit compare
+                                         *   result                                                                    */
+            uint32_t               : 1;
+            __IM uint32_t OC1CMPH0 : 1; /*!< [12..12] Channel 0 overcurrent detect 1 upper limit compare
+                                         *   result                                                                    */
+            __IM uint32_t OC1CMPH1 : 1; /*!< [13..13] Channel 1 overcurrent detect 1 upper limit compare
+                                         *   result                                                                    */
+            __IM uint32_t OC1CMPH2 : 1; /*!< [14..14] Channel 2 overcurrent detect 1 upper limit compare
+                                         *   result                                                                    */
+            uint32_t               : 1;
+            __IM uint32_t OC2CMPL0 : 1; /*!< [16..16] Channel 0 overcurrent detect 2 lower limit compare
+                                         *   result                                                                    */
+            __IM uint32_t OC2CMPL1 : 1; /*!< [17..17] Channel 1 overcurrent detect 2 lower limit compare
+                                         *   result                                                                    */
+            __IM uint32_t OC2CMPL2 : 1; /*!< [18..18] Channel 2 overcurrent detect 2 lower limit compare
+                                         *   result                                                                    */
+            uint32_t               : 1;
+            __IM uint32_t OC2CMPH0 : 1; /*!< [20..20] Channel 0 overcurrent detect 2 upper limit compare
+                                         *   result                                                                    */
+            __IM uint32_t OC2CMPH1 : 1; /*!< [21..21] Channel 1 overcurrent detect 2 upper limit compare
+                                         *   result                                                                    */
+            __IM uint32_t OC2CMPH2 : 1; /*!< [22..22] Channel 2 overcurrent detect 2 upper limit compare
+                                         *   result                                                                    */
+            uint32_t : 9;
+        } DSCOCRMR_b;
+    };
+    __IM uint32_t RESERVED5[4];
+
+    union
+    {
+        __IM uint32_t DSCSR;           /*!< (@ 0x00000240) Channel Status Register                                    */
+
+        struct
+        {
+            __IM uint32_t DUF0  : 1;   /*!< [0..0] Channel 0 Data Update flag                                         */
+            __IM uint32_t DUF1  : 1;   /*!< [1..1] Channel 1 Data Update flag                                         */
+            __IM uint32_t DUF2  : 1;   /*!< [2..2] Channel 2 Data Update flag                                         */
+            uint32_t            : 1;
+            __IM uint32_t CAUF0 : 1;   /*!< [4..4] Channel 0 capture data A update flag                               */
+            __IM uint32_t CAUF1 : 1;   /*!< [5..5] Channel 1 capture data A update flag                               */
+            __IM uint32_t CAUF2 : 1;   /*!< [6..6] Channel 2 capture data A update flag                               */
+            uint32_t            : 1;
+            __IM uint32_t CBUF0 : 1;   /*!< [8..8] Channel 0 capture data B update flag                               */
+            __IM uint32_t CBUF1 : 1;   /*!< [9..9] Channel 1 capture data B update flag                               */
+            __IM uint32_t CBUF2 : 1;   /*!< [10..10] Channel 2 capture data B update flag                             */
+            uint32_t            : 21;
+        } DSCSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSCSSR;           /*!< (@ 0x00000244) Channel State Status Register                              */
+
+        struct
+        {
+            __IM uint32_t CHSTATE0 : 1; /*!< [0..0] Channel 0 state                                                    */
+            uint32_t               : 3;
+            __IM uint32_t CHSTATE1 : 1; /*!< [4..4] Channel 1 state                                                    */
+            uint32_t               : 3;
+            __IM uint32_t CHSTATE2 : 1; /*!< [8..8] Channel 2 state                                                    */
+            uint32_t               : 23;
+        } DSCSSR_b;
+    };
+    __IM uint32_t RESERVED6[6];
+
+    union
+    {
+        __OM uint32_t DSCESCR;            /*!< (@ 0x00000260) Channel Error Status Clear Register                        */
+
+        struct
+        {
+            __OM uint32_t CLRSCF0    : 1; /*!< [0..0] Channel 0 Overcurrent Lower Limit Detection Flag Clear             */
+            __OM uint32_t CLRSCF1    : 1; /*!< [1..1] Channel 1 Overcurrent Lower Limit Detection Flag Clear             */
+            __OM uint32_t CLRSCF2    : 1; /*!< [2..2] Channel 2 Overcurrent Lower Limit Detection Flag Clear             */
+            uint32_t                 : 13;
+            __OM uint32_t CLRSUMERRL : 1; /*!< [16..16] Overcurrent Sum Error Lower Limit Detection Flag Clear           */
+            __OM uint32_t CLRSUMERRH : 1; /*!< [17..17] Overcurrent Sum Error Upper Limit Detection Flag Clear           */
+            uint32_t                 : 14;
+        } DSCESCR_b;
+    };
+
+    union
+    {
+        __OM uint32_t DSCOCESCR;         /*!< (@ 0x00000264) Channel Overcurrent Error Status Clear Register            */
+
+        struct
+        {
+            __OM uint32_t CLROC0FL0 : 1; /*!< [0..0] Channel 0 overcurrent lower limit detection 0 flag clear           */
+            __OM uint32_t CLROC0FL1 : 1; /*!< [1..1] Channel 1 overcurrent lower limit detection 0 flag clear           */
+            __OM uint32_t CLROC0FL2 : 1; /*!< [2..2] Channel 2 overcurrent lower limit detection 0 flag clear           */
+            uint32_t                : 1;
+            __OM uint32_t CLROC0FH0 : 1; /*!< [4..4] Channel 0 overcurrent upper limit exceeded 0 flag clear            */
+            __OM uint32_t CLROC0FH1 : 1; /*!< [5..5] Channel 1 overcurrent upper limit exceeded 0 flag clear            */
+            __OM uint32_t CLROC0FH2 : 1; /*!< [6..6] Channel 2 overcurrent upper limit exceeded 0 flag clear            */
+            uint32_t                : 1;
+            __OM uint32_t CLROC1FL0 : 1; /*!< [8..8] Channel 0 overcurrent lower limit detection 1 flag clear           */
+            __OM uint32_t CLROC1FL1 : 1; /*!< [9..9] Channel 1 overcurrent lower limit detection 1 flag clear           */
+            __OM uint32_t CLROC1FL2 : 1; /*!< [10..10] Channel 2 overcurrent lower limit detection 1 flag
+                                          *   clear                                                                     */
+            uint32_t                : 1;
+            __OM uint32_t CLROC1FH0 : 1; /*!< [12..12] Channel 0 overcurrent upper limit exceeded 1 flag clear          */
+            __OM uint32_t CLROC1FH1 : 1; /*!< [13..13] Channel 1 overcurrent upper limit exceeded 1 flag clear          */
+            __OM uint32_t CLROC1FH2 : 1; /*!< [14..14] Channel 2 overcurrent upper limit exceeded 1 flag clear          */
+            uint32_t                : 1;
+            __OM uint32_t CLROC2FL0 : 1; /*!< [16..16] Channel 0 overcurrent lower limit detection 2 flag
+                                          *   clear                                                                     */
+            __OM uint32_t CLROC2FL1 : 1; /*!< [17..17] Channel 1 overcurrent lower limit detection 2 flag
+                                          *   clear                                                                     */
+            __OM uint32_t CLROC2FL2 : 1; /*!< [18..18] Channel 2 overcurrent lower limit detection 2 flag
+                                          *   clear                                                                     */
+            uint32_t                : 1;
+            __OM uint32_t CLROC2FH0 : 1; /*!< [20..20] Channel 0 overcurrent upper limit exceeded 2 flag clear          */
+            __OM uint32_t CLROC2FH1 : 1; /*!< [21..21] Channel 1 overcurrent upper limit exceeded 2 flag                */
+            __OM uint32_t CLROC2FH2 : 1; /*!< [22..22] Channel 2 overcurrent upper limit exceeded 2 flag clear          */
+            uint32_t                : 9;
+        } DSCOCESCR_b;
+    };
+
+    union
+    {
+        __OM uint32_t DSCOCNSCR;         /*!< (@ 0x00000268) Channel Overcurrent Notification Status Clear
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __OM uint32_t CLROWD0N0 : 1; /*!< [0..0] Channel 0 overcurrent detection window notification 0
+                                          *   flag clear                                                                */
+            __OM uint32_t CLROWD0N1 : 1; /*!< [1..1] Channel 1 overcurrent detection window notification 0
+                                          *   flag clear                                                                */
+            __OM uint32_t CLROWD0N2 : 1; /*!< [2..2] Channel 2 overcurrent detection window notification 0
+                                          *   flag clear                                                                */
+            uint32_t                : 1;
+            __OM uint32_t CLROWD1N0 : 1; /*!< [4..4] Channel 0 overcurrent detection window notification 1
+                                          *   flag clear                                                                */
+            __OM uint32_t CLROWD1N1 : 1; /*!< [5..5] Channel 1 overcurrent detection window notification 1
+                                          *   flag clear                                                                */
+            __OM uint32_t CLROWD1N2 : 1; /*!< [6..6] Channel 2 overcurrent detection window notification 1
+                                          *   flag clear                                                                */
+            uint32_t                : 1;
+            __OM uint32_t CLROWD2N0 : 1; /*!< [8..8] Channel 0 overcurrent detection window notification 2
+                                          *   flag clear                                                                */
+            __OM uint32_t CLROWD2N1 : 1; /*!< [9..9] Channel 1 overcurrent detection window notification 2
+                                          *   flag clear                                                                */
+            __OM uint32_t CLROWD2N2 : 1; /*!< [10..10] Channel 2 overcurrent detection window notification
+                                          *   2 flag clear                                                              */
+            uint32_t                : 1;
+            __OM uint32_t CLROWD3N0 : 1; /*!< [12..12] Channel 0 overcurrent detection window notification
+                                          *   3 flag clear                                                              */
+            __OM uint32_t CLROWD3N1 : 1; /*!< [13..13] Channel 1 overcurrent detection window notification
+                                          *   3 flag clear                                                              */
+            __OM uint32_t CLROWD3N2 : 1; /*!< [14..14] Channel 2 overcurrent detection window notification
+                                          *   3 flag clear                                                              */
+            uint32_t : 17;
+        } DSCOCNSCR_b;
+    };
+    __IM uint32_t RESERVED7[5];
+
+    union
+    {
+        __OM uint32_t DSCSCR;           /*!< (@ 0x00000280) Channel Status Clear Register                              */
+
+        struct
+        {
+            __OM uint32_t CLRDUF0  : 1; /*!< [0..0] Channel 0 Data Update Flag Clear                                   */
+            __OM uint32_t CLRDUF1  : 1; /*!< [1..1] Channel 1 Data Update Flag Clear                                   */
+            __OM uint32_t CLRDUF2  : 1; /*!< [2..2] Channel 2 Data Update Flag Clear                                   */
+            uint32_t               : 1;
+            __OM uint32_t CLRCAUF0 : 1; /*!< [4..4] Channel 0 Capture Data A Update Flag Clear                         */
+            __OM uint32_t CLRCAUF1 : 1; /*!< [5..5] Channel 1 Capture Data A Update Flag Clear                         */
+            __OM uint32_t CLRCAUF2 : 1; /*!< [6..6] Channel 2 Capture Data A Update Flag Clear                         */
+            uint32_t               : 1;
+            __OM uint32_t CLRCBUF0 : 1; /*!< [8..8] Channel 0 Capture Data B Update Flag Clear                         */
+            __OM uint32_t CLRCBUF1 : 1; /*!< [9..9] Channel 1 Capture Data B Update Flag Clear                         */
+            __OM uint32_t CLRCBUF2 : 1; /*!< [10..10] Channel 2 Capture Data B Update Flag Clear                       */
+            uint32_t               : 21;
+        } DSCSCR_b;
+    };
+    __IM uint32_t          RESERVED8[31];
+    __IOM R_DSMIF0_CH_Type CH[3];      /*!< (@ 0x00000300) Channel Registers [0..2]                                   */
+} R_DSMIF0_Type;                       /*!< Size = 1728 (0x6c0)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_HDSLD0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief HIPERFACE DSL for Drive Interface Unit 0 (R_HDSLD0)
+ */
+
+typedef struct                         /*!< (@ 0x90200000) R_HDSLD0 Structure                                         */
+{
+    union
+    {
+        __IOM uint8_t SYS_CTRL;        /*!< (@ 0x00000000) System Control Register                                    */
+
+        struct
+        {
+            __IOM uint8_t OEN  : 1;    /*!< [0..0] Activation of the output                                           */
+            __IOM uint8_t SPOL : 1;    /*!< [1..1] Polarity of the synchronization pulse                              */
+            uint8_t            : 2;
+            __IOM uint8_t LOOP : 1;    /*!< [4..4] Test drive interface                                               */
+            __IOM uint8_t FRST : 1;    /*!< [5..5] Pipeline FIFO, reset                                               */
+            __IOM uint8_t MRST : 1;    /*!< [6..6] Messages reset                                                     */
+            __IOM uint8_t PRST : 1;    /*!< [7..7] Protocol reset                                                     */
+        } SYS_CTRL_b;
+    };
+
+    union
+    {
+        __OM uint8_t SYNC_CTRL;        /*!< (@ 0x00000001) Synchronization Control Register                           */
+
+        struct
+        {
+            __OM uint8_t ES : 8;       /*!< [7..0] External synchronization                                           */
+        } SYNC_CTRL_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IM uint8_t MASTER_QM;        /*!< (@ 0x00000003) Quality Monitoring Register                                */
+
+        struct
+        {
+            __IM uint8_t QM   : 4;     /*!< [3..0] Quality monitoring bits                                            */
+            uint8_t           : 3;
+            __IM uint8_t LINK : 1;     /*!< [7..7] DSL protocol connection status                                     */
+        } MASTER_QM_b;
+    };
+
+    union
+    {
+        __IOM uint8_t EVENT_H;         /*!< (@ 0x00000004) High Byte Event Register                                   */
+
+        struct
+        {
+            __IOM uint8_t PRST : 1;    /*!< [0..0] Protocol reset warning                                             */
+            __IOM uint8_t DTE  : 1;    /*!< [1..1] Estimator deviation threshold error                                */
+            uint8_t            : 1;
+            __IOM uint8_t POS  : 1;    /*!< [3..3] Estimator turned on                                                */
+            uint8_t            : 2;
+            __IOM uint8_t SUM  : 1;    /*!< [6..6] Remote event monitoring                                            */
+            __IM uint8_t  INT  : 1;    /*!< [7..7] Interrupt status                                                   */
+        } EVENT_H_b;
+    };
+
+    union
+    {
+        __IOM uint8_t EVENT_L;         /*!< (@ 0x00000005) Low Byte Event Register                                    */
+
+        struct
+        {
+            uint8_t            : 1;
+            __IOM uint8_t FREL : 1;    /*!< [1..1] Channel free for "long message"                                    */
+            __IOM uint8_t QMLW : 1;    /*!< [2..2] Quality monitoring low-value warning                               */
+            uint8_t            : 1;
+            __IOM uint8_t ANS  : 1;    /*!< [4..4] Erroneous answer to "long message"                                 */
+            __IOM uint8_t MIN  : 1;    /*!< [5..5] Message initialization                                             */
+            uint8_t            : 2;
+        } EVENT_L_b;
+    };
+
+    union
+    {
+        __OM uint8_t MASK_H;           /*!< (@ 0x00000006) High Byte Event Mask Register                              */
+
+        struct
+        {
+            __OM uint8_t MPRST : 1;    /*!< [0..0] Mask for protocol reset warning                                    */
+            __OM uint8_t MDTE  : 1;    /*!< [1..1] Mask for estimator deviation threshold error warning               */
+            uint8_t            : 1;
+            __OM uint8_t MPOS  : 1;    /*!< [3..3] Mask for fast position error                                       */
+            uint8_t            : 2;
+            __OM uint8_t MSUM  : 1;    /*!< [6..6] Mask for remote event monitoring                                   */
+            uint8_t            : 1;
+        } MASK_H_b;
+    };
+
+    union
+    {
+        __OM uint8_t MASK_L;           /*!< (@ 0x00000007) Low Byte Event Mask Register                               */
+
+        struct
+        {
+            uint8_t            : 1;
+            __OM uint8_t MFREL : 1;    /*!< [1..1] Mask for "channel free for "long message""                         */
+            __OM uint8_t MQMLW : 1;    /*!< [2..2] Mask for low-quality monitoring value warning                      */
+            uint8_t            : 1;
+            __OM uint8_t MANS  : 1;    /*!< [4..4] Mask for erroneous answer to "long message"                        */
+            __OM uint8_t MMIN  : 1;    /*!< [5..5] Mask for message initialization confirmation                       */
+            uint8_t            : 2;
+        } MASK_L_b;
+    };
+
+    union
+    {
+        __OM uint8_t MASK_SUM;         /*!< (@ 0x00000008) Summary Mask Register                                      */
+
+        struct
+        {
+            __OM uint8_t MSUM : 8;     /*!< [7..0] Mask for status summary bits                                       */
+        } MASK_SUM_b;
+    };
+
+    union
+    {
+        __IM uint8_t EDGES;            /*!< (@ 0x00000009) Edge Register                                              */
+
+        struct
+        {
+            __IM uint8_t EDGES : 8;    /*!< [7..0] Identification of edges in the cable signal                        */
+        } EDGES_b;
+    };
+
+    union
+    {
+        __IM uint8_t DELAY;            /*!< (@ 0x0000000A) Run Time Delay Register                                    */
+
+        struct
+        {
+            __IM uint8_t CBLDLY : 4;   /*!< [3..0] 4-bit value for cable delay                                        */
+            __IM uint8_t RSSI   : 4;   /*!< [7..4] Indication of the received signal strength                         */
+        } DELAY_b;
+    };
+
+    union
+    {
+        __IM uint8_t VERSION;          /*!< (@ 0x0000000B) Version Register                                           */
+
+        struct
+        {
+            __IM uint8_t MINOR : 4;    /*!< [3..0] Minor release number                                               */
+            __IM uint8_t MAJOR : 2;    /*!< [5..4] Major release number                                               */
+            __IM uint8_t CODE  : 2;    /*!< [7..6] Type of module                                                     */
+        } VERSION_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IM uint8_t ENC_ID2;          /*!< (@ 0x0000000D) Encoder ID 2 Register                                      */
+
+        struct
+        {
+            __IM uint8_t ENCID : 4;    /*!< [3..0] Encoder designation code bit 19 to bit 16                          */
+            __IM uint8_t SCI   : 3;    /*!< [6..4] Indication of special characters                                   */
+            uint8_t            : 1;
+        } ENC_ID2_b;
+    };
+
+    union
+    {
+        __IM uint8_t ENC_ID1;          /*!< (@ 0x0000000E) Encoder ID 1 Register                                      */
+
+        struct
+        {
+            __IM uint8_t ENCID : 8;    /*!< [7..0] Encoder designation code, byte n                                   */
+        } ENC_ID1_b;
+    };
+
+    union
+    {
+        __IM uint8_t ENC_ID0;          /*!< (@ 0x0000000F) Encoder ID 0 Register                                      */
+
+        struct
+        {
+            __IM uint8_t ENCID : 8;    /*!< [7..0] Encoder designation code, byte n                                   */
+        } ENC_ID0_b;
+    };
+
+    union
+    {
+        __IM uint8_t POS4;             /*!< (@ 0x00000010) Fast Position Byte 4 Register                              */
+
+        struct
+        {
+            __IM uint8_t POS : 8;      /*!< [7..0] Fast position, byte n                                              */
+        } POS4_b;
+    };
+
+    union
+    {
+        __IM uint8_t POS3;             /*!< (@ 0x00000011) Fast Position Byte 3 Register                              */
+
+        struct
+        {
+            __IM uint8_t POS : 8;      /*!< [7..0] Fast position, byte n                                              */
+        } POS3_b;
+    };
+
+    union
+    {
+        __IM uint8_t POS2;             /*!< (@ 0x00000012) Fast Position Byte 2 Register                              */
+
+        struct
+        {
+            __IM uint8_t POS : 8;      /*!< [7..0] Fast position, byte n                                              */
+        } POS2_b;
+    };
+
+    union
+    {
+        __IM uint8_t POS1;             /*!< (@ 0x00000013) Fast Position Byte 1 Register                              */
+
+        struct
+        {
+            __IM uint8_t POS : 8;      /*!< [7..0] Fast position, byte n                                              */
+        } POS1_b;
+    };
+
+    union
+    {
+        __IM uint8_t POS0;             /*!< (@ 0x00000014) Fast Position Byte 0 Register                              */
+
+        struct
+        {
+            __IM uint8_t POS : 8;      /*!< [7..0] Fast position, byte n                                              */
+        } POS0_b;
+    };
+
+    union
+    {
+        __IM uint8_t VEL2;             /*!< (@ 0x00000015) Speed Byte 2 Register                                      */
+
+        struct
+        {
+            __IM uint8_t VEL : 8;      /*!< [7..0] Speed, byte n                                                      */
+        } VEL2_b;
+    };
+
+    union
+    {
+        __IM uint8_t VEL1;             /*!< (@ 0x00000016) Speed Byte 1 Register                                      */
+
+        struct
+        {
+            __IM uint8_t VEL : 8;      /*!< [7..0] Speed, byte n                                                      */
+        } VEL1_b;
+    };
+
+    union
+    {
+        __IM uint8_t VEL0;             /*!< (@ 0x00000017) Speed Byte 0 Register                                      */
+
+        struct
+        {
+            __IM uint8_t VEL : 8;      /*!< [7..0] Speed, byte n                                                      */
+        } VEL0_b;
+    };
+
+    union
+    {
+        __IM uint8_t MIR_SUM;          /*!< (@ 0x00000018) Mirror Status Summary Register                             */
+
+        struct
+        {
+            __IM uint8_t SUM : 8;      /*!< [7..0] Status summary bit                                                 */
+        } MIR_SUM_b;
+    };
+    __IM uint8_t RESERVED2[7];
+
+    union
+    {
+        __IOM uint8_t PC_BUF[8];       /*!< (@ 0x00000020) Parameter Channel Buffer n Register (n = 0 to
+                                        *                  7)                                                         */
+
+        struct
+        {
+            __IOM uint8_t PCBUF : 8;   /*!< [7..0] Parameter Channel, byte n                                          */
+        } PC_BUF_b[8];
+    };
+
+    union
+    {
+        __IOM uint8_t PC_ADD_H;        /*!< (@ 0x00000028) High Byte Long Message Address Register                    */
+
+        struct
+        {
+            __OM uint8_t  LADDH : 2;   /*!< [1..0] Long message address, bit 9 to bit 8                               */
+            __OM uint8_t  LLEN  : 2;   /*!< [3..2] Data length of the "long message"                                  */
+            __OM uint8_t  LIND  : 1;   /*!< [4..4] Indirect addressing of long messages                               */
+            __IOM uint8_t LOFF  : 1;   /*!< [5..5] Long message addressing mode/long message error                    */
+            __OM uint8_t  LRW   : 1;   /*!< [6..6] Long message, read/write mode                                      */
+            uint8_t             : 1;
+        } PC_ADD_H_b;
+    };
+
+    union
+    {
+        __OM uint8_t PC_ADD_L;         /*!< (@ 0x00000029) Low Byte Long Message Address Register                     */
+
+        struct
+        {
+            __OM uint8_t LADDL : 8;    /*!< [7..0] Long message address, bit 7 to bit 0                               */
+        } PC_ADD_L_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PC_OFF_H;        /*!< (@ 0x0000002A) High Byte Long Message Address Offset Register             */
+
+        struct
+        {
+            __OM uint8_t LOFFADDH : 7; /*!< [6..0] Long message offset value, bit 14 to bit 8                         */
+            __IM uint8_t LID      : 1; /*!< [7..7] Long message identification                                        */
+        } PC_OFF_H_b;
+    };
+
+    union
+    {
+        __OM uint8_t PC_OFF_L;         /*!< (@ 0x0000002B) Low Byte Long Message Address Offset Register              */
+
+        struct
+        {
+            __OM uint8_t LOFFADDL : 8; /*!< [7..0] Long message offset value, bit 7 to bit 0                          */
+        } PC_OFF_L_b;
+    };
+
+    union
+    {
+        __OM uint8_t PC_CTRL;          /*!< (@ 0x0000002C) Parameter Channel Control Register                         */
+
+        struct
+        {
+            __OM uint8_t LSTA : 1;     /*!< [0..0] Control of the long message start                                  */
+            uint8_t           : 7;
+        } PC_CTRL_b;
+    };
+
+    union
+    {
+        __IM uint8_t PIPE_S;           /*!< (@ 0x0000002D) SensorHub Channel Status Register                          */
+
+        struct
+        {
+            __IM uint8_t PSCI : 1;     /*!< [0..0] Indication for special characters in the SensorHub Channel         */
+            __IM uint8_t PERR : 1;     /*!< [1..1] Coding error of the bits in the SensorHub Channel                  */
+            __IM uint8_t PEMP : 1;     /*!< [2..2] The SensorHub channel buffer is empty                              */
+            __IM uint8_t POVR : 1;     /*!< [3..3] SensorHub Channel overflow                                         */
+            uint8_t           : 4;
+        } PIPE_S_b;
+    };
+
+    union
+    {
+        __IM uint8_t PIPE_D;           /*!< (@ 0x0000002E) SensorHub Channel Data Register                            */
+
+        struct
+        {
+            __IM uint8_t SCDATA : 8;   /*!< [7..0] SensorHub Channel data                                             */
+        } PIPE_D_b;
+    };
+
+    union
+    {
+        __IM uint8_t PC_DATA;          /*!< (@ 0x0000002F) Parameter Channel Short Message Mirror Register            */
+
+        struct
+        {
+            __IM uint8_t PCDATA : 8;   /*!< [7..0] "Short message" Mirror register data                               */
+        } PC_DATA_b;
+    };
+    __IM uint8_t RESERVED3[8];
+
+    union
+    {
+        __IOM uint8_t ACC_ERR_CNT;     /*!< (@ 0x00000038) Fast Position Error Counter Register                       */
+
+        struct
+        {
+            __IOM uint8_t CNT : 5;     /*!< [4..0] Position error count/threshold                                     */
+            uint8_t           : 3;
+        } ACC_ERR_CNT_b;
+    };
+
+    union
+    {
+        __OM uint8_t MAXACC;           /*!< (@ 0x00000039) Fast Position Acceleration Boundary Register               */
+
+        struct
+        {
+            __OM uint8_t MNT : 6;      /*!< [5..0] Mantissa of fast position acceleration boundary                    */
+            __OM uint8_t RES : 2;      /*!< [7..6] Resolution of fast position acceleration boundary                  */
+        } MAXACC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MAXDEV_H;        /*!< (@ 0x0000003A) Fast Position Estimator Deviation High Byte Register       */
+
+        struct
+        {
+            __IOM uint8_t DEVH : 8;    /*!< [7..0] Fast position estimator deviation high byte                        */
+        } MAXDEV_H_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MAXDEV_L;        /*!< (@ 0x0000003B) Fast Position Estimator Deviation Low Byte Register        */
+
+        struct
+        {
+            __IOM uint8_t DEVL : 8;    /*!< [7..0] Fast position estimator deviation low byte                         */
+        } MAXDEV_L_b;
+    };
+    __IM uint8_t RESERVED4[3];
+
+    union
+    {
+        __IM uint8_t DUMMY;            /*!< (@ 0x0000003F) Dummy Register                                             */
+
+        struct
+        {
+            __IM uint8_t DUMMY : 8;    /*!< [7..0] Due to the transmission of the online-status, Online
+                                        *   Status read transactions need less time for transmission.
+                                        *   Therefore, dummy read transactions must be inserted to
+                                        *   avoid unwanted extra transactions.                                        */
+        } DUMMY_b;
+    };
+    __IM uint8_t RESERVED5[32];
+
+    union
+    {
+        __IOM uint8_t MIR_ST[8];       /*!< (@ 0x00000060) Mirror Status n Register (n = 0 to 7)                      */
+
+        struct
+        {
+            __IOM uint8_t MIRST : 8;   /*!< [7..0] Mirror status, byte n                                              */
+        } MIR_ST_b[8];
+    };
+} R_HDSLD0_Type;                       /*!< Size = 104 (0x68)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_HDSLS10                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief HIPERFACE DSL for Safe Channel 1 Unit 0 (R_HDSLS10)
+ */
+
+typedef struct                         /*!< (@ 0x90201000) R_HDSLS10 Structure                                        */
+{
+    __IM uint8_t RESERVED[9];
+
+    union
+    {
+        __IM uint8_t EDGES;            /*!< (@ 0x00000009) Edge Register                                              */
+
+        struct
+        {
+            __IM uint8_t EDGES : 8;    /*!< [7..0] Identification of edges in the cable signal                        */
+        } EDGES_b;
+    };
+
+    union
+    {
+        __IM uint8_t DELAY;            /*!< (@ 0x0000000A) Run Time Delay Register                                    */
+
+        struct
+        {
+            __IM uint8_t CBLDLY : 4;   /*!< [3..0] 4-bit value for cable delay                                        */
+            __IM uint8_t RSSI   : 4;   /*!< [7..4] Indication of the received signal strength                         */
+        } DELAY_b;
+    };
+
+    union
+    {
+        __IM uint8_t VERSION;          /*!< (@ 0x0000000B) Version Register                                           */
+
+        struct
+        {
+            __IM uint8_t MINOR : 4;    /*!< [3..0] Minor release number                                               */
+            __IM uint8_t MAJOR : 2;    /*!< [5..4] Major release number                                               */
+            __IM uint8_t CODE  : 2;    /*!< [7..6] Type of module                                                     */
+        } VERSION_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IM uint8_t ENC_ID2;          /*!< (@ 0x0000000D) Encoder ID 2 Register                                      */
+
+        struct
+        {
+            __IM uint8_t ENCID : 4;    /*!< [3..0] Encoder designation code bit 19 to bit 16                          */
+            __IM uint8_t SCI   : 3;    /*!< [6..4] Indication of special characters                                   */
+            uint8_t            : 1;
+        } ENC_ID2_b;
+    };
+
+    union
+    {
+        __IM uint8_t ENC_ID1;          /*!< (@ 0x0000000E) Encoder ID 1 Register                                      */
+
+        struct
+        {
+            __IM uint8_t ENCID : 8;    /*!< [7..0] Encoder designation code, byte n                                   */
+        } ENC_ID1_b;
+    };
+
+    union
+    {
+        __IM uint8_t ENC_ID0;          /*!< (@ 0x0000000F) Encoder ID 0 Register                                      */
+
+        struct
+        {
+            __IM uint8_t ENCID : 8;    /*!< [7..0] Encoder designation code, byte n                                   */
+        } ENC_ID0_b;
+    };
+    __IM uint8_t RESERVED2[9];
+
+    union
+    {
+        __IM uint8_t VPOS4;            /*!< (@ 0x00000019) Safe Position 4 Register                                   */
+
+        struct
+        {
+            __IM uint8_t VPOS : 8;     /*!< [7..0] Safe position, byte n                                              */
+        } VPOS4_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS3;            /*!< (@ 0x0000001A) Safe Position 3 Register                                   */
+
+        struct
+        {
+            __IM uint8_t VPOS : 8;     /*!< [7..0] Safe position, byte n                                              */
+        } VPOS3_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS2;            /*!< (@ 0x0000001B) Safe Position 2 Register                                   */
+
+        struct
+        {
+            __IM uint8_t VPOS : 8;     /*!< [7..0] Safe position, byte n                                              */
+        } VPOS2_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS1;            /*!< (@ 0x0000001C) Safe Position 1 Register                                   */
+
+        struct
+        {
+            __IM uint8_t VPOS : 8;     /*!< [7..0] Safe position, byte n                                              */
+        } VPOS1_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS0;            /*!< (@ 0x0000001D) Safe Position 0 Register                                   */
+
+        struct
+        {
+            __IM uint8_t VPOS : 8;     /*!< [7..0] Safe position, byte n                                              */
+        } VPOS0_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOSCRC_H;        /*!< (@ 0x0000001E) Safe Position CRC High Byte Register                       */
+
+        struct
+        {
+            __IM uint8_t VPOSCRCH : 8; /*!< [7..0] CRC of the safe position, bit 15 to bit 8                          */
+        } VPOSCRC_H_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOSCRC_L;        /*!< (@ 0x0000001F) Safe Position CRC Low Byte Register                        */
+
+        struct
+        {
+            __IM uint8_t VPOSCRCL : 8; /*!< [7..0] CRC of the safe position, bit 7 to bit 0                           */
+        } VPOSCRC_L_b;
+    };
+    __IM uint8_t RESERVED3[21];
+
+    union
+    {
+        __IOM uint8_t SAFE_CTRL;       /*!< (@ 0x00000035) Safe System Control Register                               */
+
+        struct
+        {
+            uint8_t            : 6;
+            __IOM uint8_t MRST : 1;    /*!< [6..6] Message reset                                                      */
+            __IOM uint8_t PRST : 1;    /*!< [7..7] Protocol reset                                                     */
+        } SAFE_CTRL_b;
+    };
+
+    union
+    {
+        __IM uint8_t SAFE_SUM;         /*!< (@ 0x00000036) Safety Status Summary Register                             */
+
+        struct
+        {
+            __IM uint8_t SSUM : 8;     /*!< [7..0] Status summary bit                                                 */
+        } SAFE_SUM_b;
+    };
+
+    union
+    {
+        __IM uint8_t S_PC_DATA;        /*!< (@ 0x00000037) Parameter Channel Short Message Register                   */
+
+        struct
+        {
+            __IM uint8_t SPCDATA : 8;  /*!< [7..0] "Short message" Parameter Channel data                             */
+        } S_PC_DATA_b;
+    };
+    __IM uint8_t RESERVED4[5];
+
+    union
+    {
+        __IOM uint8_t EVENT_S;         /*!< (@ 0x0000003D) Safe Event Register                                        */
+
+        struct
+        {
+            __IOM uint8_t FRES : 1;    /*!< [0..0] Channel free for "short message"                                   */
+            __IOM uint8_t MIN  : 1;    /*!< [1..1] Message init                                                       */
+            __IOM uint8_t PRST : 1;    /*!< [2..2] Protocol reset warning                                             */
+            __IOM uint8_t QMLW : 1;    /*!< [3..3] Quality monitoring low-value warning                               */
+            __IOM uint8_t VPOS : 1;    /*!< [4..4] Safe position error                                                */
+            __IOM uint8_t SCE  : 1;    /*!< [5..5] Error on the Safe Channel                                          */
+            __IOM uint8_t SSUM : 1;    /*!< [6..6] Remote event monitoring                                            */
+            __IM uint8_t  SINT : 1;    /*!< [7..7] Safe interrupt status                                              */
+        } EVENT_S_b;
+    };
+
+    union
+    {
+        __OM uint8_t MASK_S;           /*!< (@ 0x0000003E) Safe Event Mask Register                                   */
+
+        struct
+        {
+            __OM uint8_t MFRES : 1;    /*!< [0..0] Mask for "channel free for "short message""                        */
+            __OM uint8_t MMIN  : 1;    /*!< [1..1] Mask for message initialization confirmation                       */
+            __OM uint8_t MPRST : 1;    /*!< [2..2] Mask for protocol reset warning                                    */
+            __OM uint8_t MQMLW : 1;    /*!< [3..3] Mask for low-quality monitoring value warning                      */
+            __OM uint8_t MVPOS : 1;    /*!< [4..4] Mask for safe position error                                       */
+            __OM uint8_t MSCE  : 1;    /*!< [5..5] Mask for transmission errors on the Safe Channel                   */
+            __OM uint8_t MSSUM : 1;    /*!< [6..6] Mask for remote event monitoring                                   */
+            uint8_t            : 1;
+        } MASK_S_b;
+    };
+
+    union
+    {
+        __IM uint8_t DUMMY;            /*!< (@ 0x0000003F) Dummy Register                                             */
+
+        struct
+        {
+            __IM uint8_t DUMMY : 8;    /*!< [7..0] Due to the transmission of the online-status, Online
+                                        *   Status read transactions need less time for transmission.
+                                        *   Therefore, dummy read transactions must be inserted to
+                                        *   avoid unwanted extra transactions.                                        */
+        } DUMMY_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ENC_ST[8];       /*!< (@ 0x00000040) Encoder Status n Register (n = 0 to 7)                     */
+
+        struct
+        {
+            __IOM uint8_t ENCST : 8;   /*!< [7..0] Encoder status, byte n                                             */
+        } ENC_ST_b[8];
+    };
+    __IM uint8_t RESERVED5[52];
+
+    union
+    {
+        __IM uint8_t SRSSI;            /*!< (@ 0x0000007C) Slave RSSI Register                                        */
+
+        struct
+        {
+            __IM uint8_t SRSSI : 3;    /*!< [2..0] Value of the Slave RSSI                                            */
+            uint8_t            : 5;
+        } SRSSI_b;
+    };
+    __IM uint8_t RESERVED6;
+
+    union
+    {
+        __OM uint8_t MAIL;             /*!< (@ 0x0000007E) Slave Mail Register                                        */
+
+        struct
+        {
+            __OM uint8_t MAIL : 8;     /*!< [7..0] Slave-Mail                                                         */
+        } MAIL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PING;            /*!< (@ 0x0000007F) Slave Ping Register                                        */
+
+        struct
+        {
+            __IOM uint8_t PING : 8;    /*!< [7..0] Slave-Ping                                                         */
+        } PING_b;
+    };
+} R_HDSLS10_Type;                      /*!< Size = 128 (0x80)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_HDSLS20                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief HIPERFACE DSL for Safe Channel 2 Unit 0 (R_HDSLS20)
+ */
+
+typedef struct                         /*!< (@ 0x90202000) R_HDSLS20 Structure                                        */
+{
+    __IM uint8_t RESERVED[11];
+
+    union
+    {
+        __IM uint8_t VERSION2;         /*!< (@ 0x0000000B) Version in Safe Channel 2 Register                         */
+
+        struct
+        {
+            __IM uint8_t MINOR : 4;    /*!< [3..0] Minor release number                                               */
+            __IM uint8_t MAJOR : 2;    /*!< [5..4] Major release number                                               */
+            __IM uint8_t CODE  : 2;    /*!< [7..6] Type of module                                                     */
+        } VERSION2_b;
+    };
+    __IM uint8_t RESERVED1[3];
+
+    union
+    {
+        __IM uint8_t ENC2_ID;          /*!< (@ 0x0000000F) Encoder ID in Safe Channel 2 Register                      */
+
+        struct
+        {
+            __IM uint8_t ENC2ID : 8;   /*!< [7..0] Designation of the safe channel 2 channel                          */
+        } ENC2_ID_b;
+    };
+    __IM uint8_t RESERVED2[8];
+
+    union
+    {
+        __IM uint8_t STATUS2;          /*!< (@ 0x00000018) Safe Channel 2 Status Register                             */
+
+        struct
+        {
+            __IM uint8_t FIX2  : 5;    /*!< [4..0] Safe Channel 2 Fixed Bit Pattern                                   */
+            __IM uint8_t ERR2  : 1;    /*!< [5..5] Safe Channel 2 Position Error                                      */
+            __IM uint8_t TEST2 : 1;    /*!< [6..6] Safe Channel 2 Test                                                */
+            __IM uint8_t TOG2  : 1;    /*!< [7..7] Safe Channel 2 Toggle                                              */
+        } STATUS2_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS24;           /*!< (@ 0x00000019) Safe Position Channel 2 Byte 4 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS24_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS23;           /*!< (@ 0x0000001A) Safe Position Channel 2 Byte 3 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS23_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS22;           /*!< (@ 0x0000001B) Safe Position Channel 2 Byte 2 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS22_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS21;           /*!< (@ 0x0000001C) Safe Position Channel 2 Byte 1 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS21_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS20;           /*!< (@ 0x0000001D) Safe Position Channel 2 Byte 0 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS20_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOSCRC2_H;        /*!< (@ 0x0000001E) Safe Position CRC 2 High Byte Register                     */
+
+        struct
+        {
+            __IM uint8_t VPOSCRC2H : 8; /*!< [7..0] CRC of the safe position 2, bit 15 to bit 8                        */
+        } VPOSCRC2_H_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOSCRC2_L;        /*!< (@ 0x0000001F) Safe Position CRC 2 Low Byte Register                      */
+
+        struct
+        {
+            __IM uint8_t VPOSCRC2L : 8; /*!< [7..0] CRC of the safe position 2, bit 7 to bit 0                         */
+        } VPOSCRC2_L_b;
+    };
+    __IM uint8_t RESERVED3[31];
+
+    union
+    {
+        __IM uint8_t DUMMY2;           /*!< (@ 0x0000003F) Dummy in Safe Channel 2 Register                           */
+
+        struct
+        {
+            __IM uint8_t DUMMY : 8;    /*!< [7..0] Due to the transmission of the online-status, Online
+                                        *   status read transactions need less time for transmission.
+                                        *   Therefore, dummy read transactions must be inserted to
+                                        *   avoid unwanted extra transactions.                                        */
+        } DUMMY2_b;
+    };
+} R_HDSLS20_Type;                      /*!< Size = 64 (0x40)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_BISS0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief BiSS-C Unit 0 (R_BISS0)
+ */
+
+typedef struct                              /*!< (@ 0x90203000) R_BISS0 Structure                                          */
+{
+    __IOM R_BISS0_SCDATA_Type SCDATA[8];    /*!< (@ 0x00000000) Sensor Data [0..7]                                         */
+    __IM uint32_t             RESERVED[16];
+    __IOM uint32_t            RDATA[16];    /*!< (@ 0x00000080) Register Data n (n = 1 to 16)                              */
+
+    union
+    {
+        __IOM uint32_t CNFSLV[8];           /*!< (@ 0x000000C0) Configuration Slave n (n = 1 to 8)                         */
+
+        struct
+        {
+            __IOM uint32_t SCDLEN      : 6; /*!< [5..0] Single-cycle data length of slave n                                */
+            __IOM uint32_t ENSCD       : 1; /*!< [6..6] Enable single-cycle data for slave n                               */
+            __IOM uint32_t GRAYS       : 1; /*!< [7..7] Enable GRAY to binary conversion for SSI encoder                   */
+            __IOM uint32_t SCRCLENPOLY : 7; /*!< [14..8] CRC length with predefined CRC polynomial for slave
+                                             *   n (SCRCLEN[6:0])                                                          */
+            __IOM uint32_t SELCRCS   : 1;   /*!< [15..15] CRC polynomial selection for slave n                             */
+            __IOM uint32_t SCRCSTART : 16;  /*!< [31..16] CRC calculation start value for slave n                          */
+        } CNFSLV_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t REGACC;         /*!< (@ 0x000000E0) Register Access                                            */
+
+        struct
+        {
+            uint32_t              : 16;
+            __IOM uint32_t REGADR : 7; /*!< [22..16] Register communication start address                             */
+            __IOM uint32_t WNR    : 1; /*!< [23..23] Register communication direction                                 */
+            __IOM uint32_t REGNUM : 6; /*!< [29..24] Number of consecutive registers to access                        */
+            uint32_t              : 2;
+        } REGACC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CTRLCOMM;       /*!< (@ 0x000000E4) Control Communication                                      */
+
+        struct
+        {
+            uint32_t                   : 8;
+            __IOM uint32_t HOLDCDM     : 1; /*!< [8..8] Behavior of MA signal at the end of frame                          */
+            uint32_t                   : 2;
+            __IOM uint32_t SID_CMD_IDT : 3; /*!< [13..11]  Slave addressing for register communication (SLAVEID[2:0])   */
+            __IOM uint32_t REGVERS     : 1; /*!< [14..14] Type of protocol for register communication                      */
+            __IOM uint32_t CTS         : 1; /*!< [15..15] Type of control communication                                    */
+            __IOM uint32_t FREQS       : 5; /*!< [20..16] Single-cycle data clock frequency at MA (fMA)                    */
+            __IOM uint32_t FREQR       : 3; /*!< [23..21] BiSS register data frequency                                     */
+            __IOM uint32_t SINGLEBANK  : 1; /*!< [24..24] Usage of one/two RAM bank(s) for SCDATA                          */
+            __IOM uint32_t NOCRC       : 1; /*!< [25..25] Storage of received CRC in SCDATA                                */
+            uint32_t                   : 6;
+        } CTRLCOMM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTRCNF;         /*!< (@ 0x000000E8) Master Configuration                                       */
+
+        struct
+        {
+            __IOM uint32_t FREQAGS : 8; /*!< [7..0] Frame repetition rate (AGS frequency divider)                      */
+            uint32_t               : 8;
+            __IM uint32_t REVISION : 8; /*!< [23..16] Design ID                                                        */
+            __IM uint32_t VERSION  : 8; /*!< [31..24] Version                                                          */
+        } MSTRCNF_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CHCNF;          /*!< (@ 0x000000EC) Channel Configuration                                      */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t CFGCH1 : 2; /*!< [9..8] Channel configuration                                              */
+            uint32_t              : 22;
+        } CHCNF_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STINF;               /*!< (@ 0x000000F0) Status Information                                         */
+
+        struct
+        {
+            __IM uint32_t EOT         : 1;  /*!< [0..0] End of transmission                                                */
+            uint32_t                  : 1;
+            __IM uint32_t  REGEND     : 1;  /*!< [2..2] End of Control Communication                                       */
+            __IM uint32_t  nREGERR    : 1;  /*!< [3..3] Control communication error                                        */
+            __IM uint32_t  nSCDERR    : 1;  /*!< [4..4] Single-cycle data (SCD) transmission error                         */
+            __IM uint32_t  nDELAYERR  : 1;  /*!< [5..5] Start bit in register communication                                */
+            __IM uint32_t  nAGSERR    : 1;  /*!< [6..6] Automatic Get Sensor (AGS) error                                   */
+            __IM uint32_t  nERR       : 1;  /*!< [7..7] State of the error interrupt (NER)                                 */
+            __IOM uint32_t SVALID     : 16; /*!< [23..8] SCDATAn validity indication (n: slave, n = 1 to 8)                */
+            __IM uint32_t  REGBYTES   : 6;  /*!< [29..24] Number of valid register bytes                                   */
+            __IM uint32_t  CDSSEL     : 1;  /*!< [30..30] State of Control Data Slave (CDS)                                */
+            __IM uint32_t  CDMTIMEOUT : 1;  /*!< [31..31] Control Data Master (CDM) timeout reached                        */
+        } STINF_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INSTREG;          /*!< (@ 0x000000F4) Instruction Register                                       */
+
+        struct
+        {
+            __IOM uint32_t AGS      : 1; /*!< [0..0] Automatic Get Sensor Data (AGS)                                    */
+            __IOM uint32_t INSTR    : 3; /*!< [3..1] Single-Cycle Data (SCD) Control Instruction                        */
+            __IOM uint32_t INIT     : 1; /*!< [4..4] Start initialization sequence                                      */
+            __IOM uint32_t SWBANK   : 1; /*!< [5..5] RAM Bank Switching                                                 */
+            __IOM uint32_t HOLDBANK : 1; /*!< [6..6] RAM Bank Control                                                   */
+            __IOM uint32_t BREAK    : 1; /*!< [7..7] Start BREAK Sequence                                               */
+            uint32_t                : 4;
+            __IOM uint32_t MAFS     : 1; /*!< [12..12] Control of the MA line                                           */
+            __IOM uint32_t MAVS     : 1; /*!< [13..13] MA line force level                                              */
+            uint32_t                : 18;
+        } INSTREG_b;
+    };
+
+    union
+    {
+        __IM uint32_t STINF2;             /*!< (@ 0x000000F8) Status Information 2                                       */
+
+        struct
+        {
+            __IM uint32_t SL1        : 1; /*!< [0..0] SL input line state                                                */
+            __IM uint32_t CDS1       : 1; /*!< [1..1] Control Data Slave (CDS) bit value                                 */
+            uint32_t                 : 14;
+            __IM uint32_t IDL        : 4; /*!< [19..16] Number of set ID lock bits during control communication          */
+            uint32_t                 : 4;
+            __IM uint32_t SWBANKFAIL : 1; /*!< [24..24] Bank switching status                                            */
+            uint32_t                 : 7;
+        } STINF2_b;
+    };
+} R_BISS0_Type;                           /*!< Size = 252 (0xfc)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ENDAT0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief EnDat2.2 Unit 0 (R_ENDAT0)
+ */
+
+typedef struct                         /*!< (@ 0x90204000) R_ENDAT0 Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t SEND;           /*!< (@ 0x00000000) Send Register                                              */
+
+        struct
+        {
+            __IOM uint32_t D : 16;     /*!< [15..0] Parameters, Instructions                                          */
+            __IOM uint32_t A : 8;      /*!< [23..16] Memory Range Select (MRS) code, Address, Port address            */
+            __IOM uint32_t M : 6;      /*!< [29..24] Mode command                                                     */
+            uint32_t         : 2;
+        } SEND_b;
+    };
+
+    union
+    {
+        __IM uint32_t EMPFR1_L;         /*!< (@ 0x00000004) Receive Register 1, Low Double Word                        */
+
+        struct
+        {
+            __IM uint32_t RDATA_L : 32; /*!< [31..0] Received data, bit 31 to bit 0                                    */
+        } EMPFR1_L_b;
+    };
+
+    union
+    {
+        __IM uint32_t EMPFR1_H;         /*!< (@ 0x00000008) Receive Register 1, High Double Word                       */
+
+        struct
+        {
+            __IM uint32_t RDATA_H : 16; /*!< [15..0] Received data, bit 47 to bit 32                                   */
+            __IM uint32_t CRC     : 5;  /*!< [20..16] Received CRC                                                     */
+            __IM uint32_t F1      : 1;  /*!< [21..21] Safety-relevant error bit F1                                     */
+            __IM uint32_t IF2     : 1;  /*!< [22..22] Safety-relevant error bit F2 inversion                           */
+            __IM uint32_t POS1    : 1;  /*!< [23..23] Absolute position value 1                                        */
+            uint32_t              : 8;
+        } EMPFR1_H_b;
+    };
+
+    union
+    {
+        __IM uint32_t EMPFR2;          /*!< (@ 0x0000000C) Receive Register 2                                         */
+
+        struct
+        {
+            __IM uint32_t RDATA2 : 32; /*!< [31..0] Received data 2                                                   */
+        } EMPFR2_b;
+    };
+
+    union
+    {
+        __IM uint32_t EMPFR3;          /*!< (@ 0x00000010) Receive Register 3                                         */
+
+        struct
+        {
+            __IM uint32_t D : 16;      /*!< [15..0] Data in the additional information 1                              */
+            __IM uint32_t C : 8;       /*!< [23..16] Memory Range Select (MRS) code in the additional information
+                                        *   1                                                                         */
+            __IM uint32_t CRC : 5;     /*!< [28..24] CRC for additional information 1                                 */
+            uint32_t          : 3;
+        } EMPFR3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t KONFR1;           /*!< (@ 0x00000014) Configuration Register 1                                   */
+
+        struct
+        {
+            __IOM uint32_t HWSTRB   : 1; /*!< [0..0] Hardware strobe                                                    */
+            __IOM uint32_t DU       : 1; /*!< [1..1] DU                                                                 */
+            __IOM uint32_t DT       : 1; /*!< [2..2] DT                                                                 */
+            uint32_t                : 1;
+            __IOM uint32_t FTCLK    : 4; /*!< [7..4] fTCLK                                                              */
+            __IOM uint32_t DWLG     : 6; /*!< [13..8] Data word length                                                  */
+            __IOM uint32_t RSTWD    : 1; /*!< [14..14] Reset window                                                     */
+            __IOM uint32_t AUTORST  : 1; /*!< [15..15] Automatic reset                                                  */
+            __IOM uint32_t CPTIME   : 8; /*!< [23..16] Cable propagation time                                           */
+            __IOM uint32_t DELAYCMP : 1; /*!< [24..24] Delay compensation                                               */
+            uint32_t                : 1;
+            __IOM uint32_t FSYS     : 3; /*!< [28..26] System clock frequency (fsys)                                    */
+            __IOM uint32_t ICRST    : 1; /*!< [29..29] IC reset                                                         */
+            __IOM uint32_t SET      : 2; /*!< [31..30] EnDat set                                                        */
+        } KONFR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t KONFR2;             /*!< (@ 0x00000018) Configuration Register 2                                   */
+
+        struct
+        {
+            __IOM uint32_t TMSMPLRATE : 8; /*!< [7..0] Timer for sampling rate                                            */
+            __IOM uint32_t WTDOG      : 8; /*!< [15..8] Watchdog                                                          */
+            __IOM uint32_t RCVTIME    : 3; /*!< [18..16] Recovery time III tST                                            */
+            __IOM uint32_t FILTER     : 3; /*!< [21..19] Filter                                                           */
+            uint32_t                  : 2;
+            __IOM uint32_t HWSTRBDLY  : 8; /*!< [31..24] Hardware strobe delay                                            */
+        } KONFR2_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t STATR;            /*!< (@ 0x00000020) Status Register                                            */
+
+        struct
+        {
+            __IOM uint32_t EMPFR1   : 1; /*!< [0..0] EMPFR1 register update                                             */
+            __IOM uint32_t ERR1     : 1; /*!< [1..1] Error 1                                                            */
+            __IOM uint32_t CRC_PRTY : 1; /*!< [2..2] CRC-PW / parity                                                    */
+            __IOM uint32_t FTYPI    : 1; /*!< [3..3] F Type I                                                           */
+            __IOM uint32_t FTYPII   : 1; /*!< [4..4] F Type II                                                          */
+            __IOM uint32_t MRS_ADR  : 1; /*!< [5..5] MRS/Adr                                                            */
+            uint32_t                : 2;
+            __IOM uint32_t EMPFR2   : 1; /*!< [8..8] EMPFR2 register update                                             */
+            __IOM uint32_t EMPFR3   : 1; /*!< [9..9] EMPFR3 register update                                             */
+            __IOM uint32_t IERR2    : 1; /*!< [10..10] /Error2                                                          */
+            __IOM uint32_t CRCZI1   : 1; /*!< [11..11] CRC-ZI1                                                          */
+            __IOM uint32_t CRCZI2   : 1; /*!< [12..12] CRC-ZI2                                                          */
+            __IOM uint32_t BUSY     : 1; /*!< [13..13] Busy                                                             */
+            __IOM uint32_t RM       : 1; /*!< [14..14] RM                                                               */
+            __IOM uint32_t WRN      : 1; /*!< [15..15] WRN                                                              */
+            __IOM uint32_t SPIKE    : 1; /*!< [16..16] Spike                                                            */
+            __IOM uint32_t WTDG     : 1; /*!< [17..17] Watchdog                                                         */
+            __IOM uint32_t FTYPIII  : 1; /*!< [18..18] F Type III                                                       */
+            uint32_t                : 3;
+            __IOM uint32_t LZK      : 1; /*!< [22..22] Delay compensation                                               */
+            __IOM uint32_t LZM      : 1; /*!< [23..23] Propagation time measurement                                     */
+            uint32_t                : 5;
+            __IOM uint32_t SPDRDY   : 1; /*!< [29..29] Speed ready                                                      */
+            __IOM uint32_t RDY4STRB : 1; /*!< [30..30] Ready for strobe                                                 */
+            __IOM uint32_t RDY      : 1; /*!< [31..31] Ready                                                            */
+        } STATR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INTMR;            /*!< (@ 0x00000024) Interrupt Mask Register                                    */
+
+        struct
+        {
+            __IOM uint32_t EMPFR1   : 1; /*!< [0..0] Interrupt mask for EMPFR1 register update                          */
+            __IOM uint32_t ERR1     : 1; /*!< [1..1] Interrupt mask for Error 1                                         */
+            __IOM uint32_t CRC_PRTY : 1; /*!< [2..2] Interrupt mask for CRC-PW / parity                                 */
+            __IOM uint32_t FTYPI    : 1; /*!< [3..3] Interrupt mask for F Type I                                        */
+            __IOM uint32_t FTYPII   : 1; /*!< [4..4] Interrupt mask for F Type II                                       */
+            __IOM uint32_t MRS_ADR  : 1; /*!< [5..5] Interrupt mask for MRS/Adr                                         */
+            uint32_t                : 2;
+            __IOM uint32_t EMPFR2   : 1; /*!< [8..8] Interrupt mask for EMPFR2 register update                          */
+            __IOM uint32_t EMPFR3   : 1; /*!< [9..9] Interrupt mask for EMPFR3 register update                          */
+            __IOM uint32_t IERR2    : 1; /*!< [10..10] Interrupt mask for /Error2                                       */
+            __IOM uint32_t CRCZI1   : 1; /*!< [11..11] Interrupt mask for CRC-ZI1                                       */
+            __IOM uint32_t CRCZI2   : 1; /*!< [12..12] Interrupt mask for CRC-ZI2                                       */
+            __IOM uint32_t BUSY     : 1; /*!< [13..13] Interrupt mask for Busy                                          */
+            __IOM uint32_t RM       : 1; /*!< [14..14] Interrupt mask for RM                                            */
+            __IOM uint32_t WRN      : 1; /*!< [15..15] Interrupt mask for WRN                                           */
+            __IOM uint32_t SPIKE    : 1; /*!< [16..16] Interrupt mask for Spike                                         */
+            __IOM uint32_t WTDG     : 1; /*!< [17..17] Interrupt mask for Watchdog                                      */
+            __IOM uint32_t FTYPIII  : 1; /*!< [18..18] Interrupt mask for F Type III                                    */
+            uint32_t                : 10;
+            __IOM uint32_t SPDRDY   : 1; /*!< [29..29] Interrupt mask for Speed ready                                   */
+            uint32_t                : 1;
+            __IOM uint32_t RDY      : 1; /*!< [31..31] Interrupt mask for Ready                                         */
+        } INTMR_b;
+    };
+    __IM uint32_t RESERVED1[4];
+    __OM uint32_t SWSTRBR;               /*!< (@ 0x00000038) SW Strobe Register                                         */
+    __IM uint32_t IDR;                   /*!< (@ 0x0000003C) ID Register                                                */
+} R_ENDAT0_Type;                         /*!< Size = 64 (0x40)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_AFMT0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief A-format Unit 0 (R_AFMT0)
+ */
+
+typedef struct                         /*!< (@ 0x90206000) R_AFMT0 Structure                                          */
+{
+    union
+    {
+        union
+        {
+            __OM uint32_t COMMAND;     /*!< (@ 0x00000000) Command Code Encoder Address Register                      */
+
+            struct
+            {
+                __OM uint32_t XEA : 3; /*!< [2..0] Encoder address                                                    */
+                __OM uint32_t CC  : 5; /*!< [7..3] Command code                                                       */
+                __OM uint32_t SID : 5; /*!< [12..8] Subcommand ID                                                     */
+                uint32_t          : 19;
+            } COMMAND_b;
+        };
+
+        union
+        {
+            __IM uint32_t ENC1RXDATA0;   /*!< (@ 0x00000000) ENC1 Receive Data 0 Register                               */
+
+            struct
+            {
+                __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data                                                 */
+            } ENC1RXDATA0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t ENC1RXDATA1;   /*!< (@ 0x00000004) ENC1 Receive Data 1 Register                               */
+
+            struct
+            {
+                __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data                                                 */
+            } ENC1RXDATA1_b;
+        };
+
+        union
+        {
+            __OM uint32_t ROMDATA;       /*!< (@ 0x00000004) EEPROM Address and Write Data Register                     */
+
+            struct
+            {
+                __OM uint32_t DATA : 16; /*!< [15..0] 16-bit EEPROM data                                                */
+                __OM uint32_t ADDR : 8;  /*!< [23..16] 8-bit EEPROM address                                             */
+                uint32_t           : 8;
+            } ROMDATA_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t ENC1RXDATA2;   /*!< (@ 0x00000008) ENC1 Receive Data 2 Register                               */
+
+            struct
+            {
+                __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data                                                 */
+            } ENC1RXDATA2_b;
+        };
+
+        union
+        {
+            __OM uint32_t ID;            /*!< (@ 0x00000008) ID Code Register                                           */
+
+            struct
+            {
+                __OM uint32_t ID_L : 16; /*!< [15..0] 24-bit ID code, low word                                          */
+                __OM uint32_t ID_H : 8;  /*!< [23..16] 24-bit ID code, high byte                                        */
+                uint32_t           : 8;
+            } ID_b;
+        };
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA3;     /*!< (@ 0x0000000C) ENC1 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA4;     /*!< (@ 0x00000010) ENC1 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA5;     /*!< (@ 0x00000014) ENC1 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA6;     /*!< (@ 0x00000018) ENC1 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA7;     /*!< (@ 0x0000001C) ENC1 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA0;     /*!< (@ 0x00000020) ENC2 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA1;     /*!< (@ 0x00000024) ENC2 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA2;     /*!< (@ 0x00000028) ENC2 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA3;     /*!< (@ 0x0000002C) ENC2 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA4;     /*!< (@ 0x00000030) ENC2 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA5;     /*!< (@ 0x00000034) ENC2 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA6;     /*!< (@ 0x00000038) ENC2 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA7;     /*!< (@ 0x0000003C) ENC2 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA0;     /*!< (@ 0x00000040) ENC3 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA1;     /*!< (@ 0x00000044) ENC3 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA2;     /*!< (@ 0x00000048) ENC3 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA3;     /*!< (@ 0x0000004C) ENC3 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA4;     /*!< (@ 0x00000050) ENC3 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA5;     /*!< (@ 0x00000054) ENC3 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA6;     /*!< (@ 0x00000058) ENC3 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA7;     /*!< (@ 0x0000005C) ENC3 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA0;     /*!< (@ 0x00000060) ENC4 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA1;     /*!< (@ 0x00000064) ENC4 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA2;     /*!< (@ 0x00000068) ENC4 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA3;     /*!< (@ 0x0000006C) ENC4 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA4;     /*!< (@ 0x00000070) ENC4 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA5;     /*!< (@ 0x00000074) ENC4 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA6;     /*!< (@ 0x00000078) ENC4 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA7;     /*!< (@ 0x0000007C) ENC4 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA0;     /*!< (@ 0x00000080) ENC5 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA1;     /*!< (@ 0x00000084) ENC5 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA2;     /*!< (@ 0x00000088) ENC5 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA3;     /*!< (@ 0x0000008C) ENC5 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA4;     /*!< (@ 0x00000090) ENC5 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA5;     /*!< (@ 0x00000094) ENC5 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA6;     /*!< (@ 0x00000098) ENC5 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA7;     /*!< (@ 0x0000009C) ENC5 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA0;     /*!< (@ 0x000000A0) ENC6 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA1;     /*!< (@ 0x000000A4) ENC6 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA2;     /*!< (@ 0x000000A8) ENC6 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA3;     /*!< (@ 0x000000AC) ENC6 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA4;     /*!< (@ 0x000000B0) ENC6 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA5;     /*!< (@ 0x000000B4) ENC6 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA6;     /*!< (@ 0x000000B8) ENC6 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA7;     /*!< (@ 0x000000BC) ENC6 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA0;     /*!< (@ 0x000000C0) ENC7 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA1;     /*!< (@ 0x000000C4) ENC7 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA2;     /*!< (@ 0x000000C8) ENC7 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA3;     /*!< (@ 0x000000CC) ENC7 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA4;     /*!< (@ 0x000000D0) ENC7 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA5;     /*!< (@ 0x000000D4) ENC7 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA6;     /*!< (@ 0x000000D8) ENC7 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA7;     /*!< (@ 0x000000DC) ENC7 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA0;     /*!< (@ 0x000000E0) ENC8 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA1;     /*!< (@ 0x000000E4) ENC8 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA2;     /*!< (@ 0x000000E8) ENC8 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA3;     /*!< (@ 0x000000EC) ENC8 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA4;     /*!< (@ 0x000000F0) ENC8 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA5;     /*!< (@ 0x000000F4) ENC8 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA6;     /*!< (@ 0x000000F8) ENC8 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA7;     /*!< (@ 0x000000FC) ENC8 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA7_b;
+    };
+
+    union
+    {
+        __OM uint32_t TRGSEL;          /*!< (@ 0x00000100) Trigger Select Register                                    */
+
+        struct
+        {
+            __OM uint32_t EXT : 1;     /*!< [0..0] Trigger select                                                     */
+            uint32_t          : 31;
+        } TRGSEL_b;
+    };
+
+    union
+    {
+        __OM uint32_t TXTRG;           /*!< (@ 0x00000104) Transmission Trigger Register                              */
+
+        struct
+        {
+            __OM uint32_t TRG : 1;     /*!< [0..0] Command data transmission trigger generation                       */
+            uint32_t          : 31;
+        } TXTRG_b;
+    };
+    __IM uint32_t RESERVED[62];
+
+    union
+    {
+        __OM uint32_t BRSEL;           /*!< (@ 0x00000200) Baud Rate Setting Register                                 */
+
+        struct
+        {
+            __OM uint32_t BR : 3;      /*!< [2..0] Baud rate setting                                                  */
+            __OM uint32_t AS : 1;      /*!< [3..3] A-Safety enable                                                    */
+            __OM uint32_t TM : 8;      /*!< [11..4] t2 time setting N                                                 */
+            uint32_t         : 20;
+        } BRSEL_b;
+    };
+} R_AFMT0_Type;                        /*!< Size = 516 (0x204)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ENCOUT                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Encoder Divided-Output Module (R_ENCOUT)
+ */
+
+typedef struct                         /*!< (@ 0x902C0000) R_ENCOUT Structure                                         */
+{
+    union
+    {
+        __IOM uint32_t CTL;            /*!< (@ 0x00000000) Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t POL : 1;    /*!< [0..0] Polarity of Phase B                                                */
+            __IOM uint32_t ZW  : 3;    /*!< [3..1] Pulse Width of Phase Z                                             */
+            __IOM uint32_t ZS  : 1;    /*!< [4..4] Synchronization phase of Phase Z                                   */
+            uint32_t           : 27;
+        } CTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STR;            /*!< (@ 0x00000004) Start Register                                             */
+
+        struct
+        {
+            __IOM uint32_t ENCE : 1;   /*!< [0..0] ENCOUT Operation Start                                             */
+            uint32_t            : 31;
+        } STR_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t POSMAX_PERIOD;   /*!< (@ 0x0000000C) Maximum Position and Carrier Period Register               */
+
+        struct
+        {
+            __IOM uint32_t PERIOD : 16; /*!< [15..0] Carrier Period Setting                                            */
+            __IOM uint32_t POSMAX : 16; /*!< [31..16] Maximum Position Setting                                         */
+        } POSMAX_PERIOD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OUTCNT;          /*!< (@ 0x00000010) Output Count Register                                      */
+
+        struct
+        {
+            __IOM uint32_t EDGCNT : 16; /*!< [15..0] Edge Count Setting                                                */
+            uint32_t              : 16;
+        } OUTCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t POSCNT;          /*!< (@ 0x00000014) Position Count Register                                    */
+
+        struct
+        {
+            __IOM uint32_t POSCNT : 16; /*!< [15..0] Current Position                                                  */
+            uint32_t              : 16;
+        } POSCNT_b;
+    };
+} R_ENCOUT_Type;                        /*!< Size = 24 (0x18)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_HDSLS212                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief HIPERFACE DSL for Safe Channel 2 Unit 12 (R_HDSLS212)
+ */
+
+typedef struct                         /*!< (@ 0x90302000) R_HDSLS212 Structure                                       */
+{
+    __IM uint8_t RESERVED[11];
+
+    union
+    {
+        __IM uint8_t VERSION2;         /*!< (@ 0x0000000B) Version in Safe Channel 2 Register                         */
+
+        struct
+        {
+            __IM uint8_t MINOR : 4;    /*!< [3..0] Minor release number                                               */
+            __IM uint8_t MAJOR : 2;    /*!< [5..4] Major release number                                               */
+            __IM uint8_t CODE  : 2;    /*!< [7..6] Type of module                                                     */
+        } VERSION2_b;
+    };
+    __IM uint8_t RESERVED1[3];
+
+    union
+    {
+        __IM uint8_t ENC2_ID;          /*!< (@ 0x0000000F) Encoder ID in Safe Channel 2 Register                      */
+
+        struct
+        {
+            __IM uint8_t ENC2ID : 8;   /*!< [7..0] Designation of the safe channel 2 channel                          */
+        } ENC2_ID_b;
+    };
+    __IM uint8_t RESERVED2[8];
+
+    union
+    {
+        __IM uint8_t STATUS2;          /*!< (@ 0x00000018) Safe Channel 2 Status Register                             */
+
+        struct
+        {
+            __IM uint8_t FIX2  : 5;    /*!< [4..0] Safe Channel 2 Fixed Bit Pattern                                   */
+            __IM uint8_t ERR2  : 1;    /*!< [5..5] Safe Channel 2 Position Error                                      */
+            __IM uint8_t TEST2 : 1;    /*!< [6..6] Safe Channel 2 Test                                                */
+            __IM uint8_t TOG2  : 1;    /*!< [7..7] Safe Channel 2 Toggle                                              */
+        } STATUS2_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS24;           /*!< (@ 0x00000019) Safe Position Channel 2 Byte 4 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS24_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS23;           /*!< (@ 0x0000001A) Safe Position Channel 2 Byte 3 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS23_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS22;           /*!< (@ 0x0000001B) Safe Position Channel 2 Byte 2 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS22_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS21;           /*!< (@ 0x0000001C) Safe Position Channel 2 Byte 1 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS21_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOS20;           /*!< (@ 0x0000001D) Safe Position Channel 2 Byte 0 Register                    */
+
+        struct
+        {
+            __IM uint8_t VPOS2 : 8;    /*!< [7..0] Safe position, Channel 2, byte n                                   */
+        } VPOS20_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOSCRC2_H;        /*!< (@ 0x0000001E) Safe Position CRC 2 High Byte Register                     */
+
+        struct
+        {
+            __IM uint8_t VPOSCRC2H : 8; /*!< [7..0] CRC of the safe position 2, bit 15 to bit 8                        */
+        } VPOSCRC2_H_b;
+    };
+
+    union
+    {
+        __IM uint8_t VPOSCRC2_L;        /*!< (@ 0x0000001F) Safe Position CRC 2 Low Byte Register                      */
+
+        struct
+        {
+            __IM uint8_t VPOSCRC2L : 8; /*!< [7..0] CRC of the safe position 2, bit 7 to bit 0                         */
+        } VPOSCRC2_L_b;
+    };
+    __IM uint8_t RESERVED3[31];
+
+    union
+    {
+        __IM uint8_t DUMMY2;           /*!< (@ 0x0000003F) Dummy in Safe Channel 2 Register                           */
+
+        struct
+        {
+            __IM uint8_t DUMMY : 8;    /*!< [7..0] Due to the transmission of the online-status, Online
+                                        *   status read transactions need less time for transmission.
+                                        *   Therefore, dummy read transactions must be inserted to
+                                        *   avoid unwanted extra transactions.                                        */
+        } DUMMY2_b;
+    };
+} R_HDSLS212_Type;                     /*!< Size = 64 (0x40)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_AFMT12                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief A-format Unit 12 (R_AFMT12)
+ */
+
+typedef struct                         /*!< (@ 0x90306000) R_AFMT12 Structure                                         */
+{
+    union
+    {
+        union
+        {
+            __OM uint32_t COMMAND;     /*!< (@ 0x00000000) Command Code Encoder Address Register                      */
+
+            struct
+            {
+                __OM uint32_t XEA : 3; /*!< [2..0] Encoder address                                                    */
+                __OM uint32_t CC  : 5; /*!< [7..3] Command code                                                       */
+                __OM uint32_t SID : 5; /*!< [12..8] Subcommand ID                                                     */
+                uint32_t          : 19;
+            } COMMAND_b;
+        };
+
+        union
+        {
+            __IM uint32_t ENC1RXDATA0;   /*!< (@ 0x00000000) ENC1 Receive Data 0 Register                               */
+
+            struct
+            {
+                __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data                                                 */
+            } ENC1RXDATA0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t ENC1RXDATA1;   /*!< (@ 0x00000004) ENC1 Receive Data 1 Register                               */
+
+            struct
+            {
+                __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data                                                 */
+            } ENC1RXDATA1_b;
+        };
+
+        union
+        {
+            __OM uint32_t ROMDATA;       /*!< (@ 0x00000004) EEPROM Address and Write Data Register                     */
+
+            struct
+            {
+                __OM uint32_t DATA : 16; /*!< [15..0] 16-bit EEPROM data                                                */
+                __OM uint32_t ADDR : 8;  /*!< [23..16] 8-bit EEPROM address                                             */
+                uint32_t           : 8;
+            } ROMDATA_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t ENC1RXDATA2;   /*!< (@ 0x00000008) ENC1 Receive Data 2 Register                               */
+
+            struct
+            {
+                __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data                                                 */
+            } ENC1RXDATA2_b;
+        };
+
+        union
+        {
+            __OM uint32_t ID;            /*!< (@ 0x00000008) ID Code Register                                           */
+
+            struct
+            {
+                __OM uint32_t ID_L : 16; /*!< [15..0] 24-bit ID code, low word                                          */
+                __OM uint32_t ID_H : 8;  /*!< [23..16] 24-bit ID code, high byte                                        */
+                uint32_t           : 8;
+            } ID_b;
+        };
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA3;     /*!< (@ 0x0000000C) ENC1 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA4;     /*!< (@ 0x00000010) ENC1 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA5;     /*!< (@ 0x00000014) ENC1 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA6;     /*!< (@ 0x00000018) ENC1 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC1RXDATA7;     /*!< (@ 0x0000001C) ENC1 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC1RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA0;     /*!< (@ 0x00000020) ENC2 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA1;     /*!< (@ 0x00000024) ENC2 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA2;     /*!< (@ 0x00000028) ENC2 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA3;     /*!< (@ 0x0000002C) ENC2 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA4;     /*!< (@ 0x00000030) ENC2 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA5;     /*!< (@ 0x00000034) ENC2 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA6;     /*!< (@ 0x00000038) ENC2 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC2RXDATA7;     /*!< (@ 0x0000003C) ENC2 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC2RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA0;     /*!< (@ 0x00000040) ENC3 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA1;     /*!< (@ 0x00000044) ENC3 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA2;     /*!< (@ 0x00000048) ENC3 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA3;     /*!< (@ 0x0000004C) ENC3 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA4;     /*!< (@ 0x00000050) ENC3 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA5;     /*!< (@ 0x00000054) ENC3 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA6;     /*!< (@ 0x00000058) ENC3 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC3RXDATA7;     /*!< (@ 0x0000005C) ENC3 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC3RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA0;     /*!< (@ 0x00000060) ENC4 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA1;     /*!< (@ 0x00000064) ENC4 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA2;     /*!< (@ 0x00000068) ENC4 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA3;     /*!< (@ 0x0000006C) ENC4 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA4;     /*!< (@ 0x00000070) ENC4 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA5;     /*!< (@ 0x00000074) ENC4 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA6;     /*!< (@ 0x00000078) ENC4 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC4RXDATA7;     /*!< (@ 0x0000007C) ENC4 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC4RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA0;     /*!< (@ 0x00000080) ENC5 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA1;     /*!< (@ 0x00000084) ENC5 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA2;     /*!< (@ 0x00000088) ENC5 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA3;     /*!< (@ 0x0000008C) ENC5 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA4;     /*!< (@ 0x00000090) ENC5 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA5;     /*!< (@ 0x00000094) ENC5 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA6;     /*!< (@ 0x00000098) ENC5 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC5RXDATA7;     /*!< (@ 0x0000009C) ENC5 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC5RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA0;     /*!< (@ 0x000000A0) ENC6 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA1;     /*!< (@ 0x000000A4) ENC6 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA2;     /*!< (@ 0x000000A8) ENC6 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA3;     /*!< (@ 0x000000AC) ENC6 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA4;     /*!< (@ 0x000000B0) ENC6 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA5;     /*!< (@ 0x000000B4) ENC6 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA6;     /*!< (@ 0x000000B8) ENC6 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC6RXDATA7;     /*!< (@ 0x000000BC) ENC6 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC6RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA0;     /*!< (@ 0x000000C0) ENC7 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA1;     /*!< (@ 0x000000C4) ENC7 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA2;     /*!< (@ 0x000000C8) ENC7 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA3;     /*!< (@ 0x000000CC) ENC7 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA4;     /*!< (@ 0x000000D0) ENC7 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA5;     /*!< (@ 0x000000D4) ENC7 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA6;     /*!< (@ 0x000000D8) ENC7 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC7RXDATA7;     /*!< (@ 0x000000DC) ENC7 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC7RXDATA7_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA0;     /*!< (@ 0x000000E0) ENC8 Receive Data 0 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA0_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA1;     /*!< (@ 0x000000E4) ENC8 Receive Data 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA1_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA2;     /*!< (@ 0x000000E8) ENC8 Receive Data 2 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA2_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA3;     /*!< (@ 0x000000EC) ENC8 Receive Data 3 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA3_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA4;     /*!< (@ 0x000000F0) ENC8 Receive Data 4 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA4_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA5;     /*!< (@ 0x000000F4) ENC8 Receive Data 5 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA5_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA6;     /*!< (@ 0x000000F8) ENC8 Receive Data 6 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA6_b;
+    };
+
+    union
+    {
+        __IM uint32_t ENC8RXDATA7;     /*!< (@ 0x000000FC) ENC8 Receive Data 7 Register                               */
+
+        struct
+        {
+            __IM uint32_t DATA : 32;   /*!< [31..0] Encoder read data                                                 */
+        } ENC8RXDATA7_b;
+    };
+
+    union
+    {
+        __OM uint32_t TRGSEL;          /*!< (@ 0x00000100) Trigger Select Register                                    */
+
+        struct
+        {
+            __OM uint32_t EXT : 1;     /*!< [0..0] Trigger select                                                     */
+            uint32_t          : 31;
+        } TRGSEL_b;
+    };
+
+    union
+    {
+        __OM uint32_t TXTRG;           /*!< (@ 0x00000104) Transmission Trigger Register                              */
+
+        struct
+        {
+            __OM uint32_t TRG : 1;     /*!< [0..0] Command data transmission trigger generation                       */
+            uint32_t          : 31;
+        } TXTRG_b;
+    };
+    __IM uint32_t RESERVED[62];
+
+    union
+    {
+        __OM uint32_t BRSEL;           /*!< (@ 0x00000200) Baud Rate Setting Register                                 */
+
+        struct
+        {
+            __OM uint32_t BR : 3;      /*!< [2..0] Baud rate setting                                                  */
+            __OM uint32_t AS : 1;      /*!< [3..3] A-Safety enable                                                    */
+            __OM uint32_t TM : 8;      /*!< [11..4] t2 time setting N                                                 */
+            uint32_t         : 20;
+        } BRSEL_b;
+    };
+} R_AFMT12_Type;                       /*!< Size = 516 (0x204)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USBHC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 HS Host Module (R_USBHC)
+ */
+
+typedef struct                         /*!< (@ 0x92040000) R_USBHC Structure                                          */
+{
+    union
+    {
+        __IM uint32_t HCREVISION;      /*!< (@ 0x00000000) HcRevision Register                                        */
+
+        struct
+        {
+            __IM uint32_t REV : 8;     /*!< [7..0] HCI revision                                                       */
+            uint32_t          : 24;
+        } HCREVISION_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCCONTROL;      /*!< (@ 0x00000004) HcControl Register                                         */
+
+        struct
+        {
+            __IOM uint32_t CBSR : 2;   /*!< [1..0] Control/bulk transfer service ratio (ControlBulkServiceRatio)      */
+            __IOM uint32_t PLE  : 1;   /*!< [2..2] Periodic list setting (PeriodicListEnable)                         */
+            __IOM uint32_t IE   : 1;   /*!< [3..3] Isochronous ED processing setting (IsochronousEnable)              */
+            __IOM uint32_t CLE  : 1;   /*!< [4..4] Control list processing setting (ControlListEnable)                */
+            __IOM uint32_t BLE  : 1;   /*!< [5..5] Bulk list processing setting (BulkListEnable)                      */
+            __IOM uint32_t HCFS : 2;   /*!< [7..6] Host logic operation status (Host Controller FunctionalState)      */
+            __IOM uint32_t IR   : 1;   /*!< [8..8] HcInterruptStatus interrupt path setting (InterruptRouting)        */
+            __IOM uint32_t RWC  : 1;   /*!< [9..9] Remote Wakeup support setting (RemoteWakeUpConnect)                */
+            __IOM uint32_t RWE  : 1;   /*!< [10..10] PME assertion control (RemoteWakeUpEnable)                       */
+            uint32_t            : 21;
+        } HCCONTROL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCCOMMANDSTATUS; /*!< (@ 0x00000008) HcCommandStatus Register                                   */
+
+        struct
+        {
+            __OM uint32_t  HCR : 1;     /*!< [0..0] Host logic software reset start (HostController Reset)             */
+            __IOM uint32_t CLF : 1;     /*!< [1..1] Control list TD (ControlList Filled)                               */
+            __IOM uint32_t BLF : 1;     /*!< [2..2] Bulk list TD (BulkListFilled)                                      */
+            __OM uint32_t  OCR : 1;     /*!< [3..3] Host logic control right change (OwnershipChangeRequest)           */
+            uint32_t           : 12;
+            __IM uint32_t SOC  : 2;     /*!< [17..16] Schedule overrun count (Scheduling OverrunCount)                 */
+            uint32_t           : 14;
+        } HCCOMMANDSTATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCINTERRUPTSTATUS; /*!< (@ 0x0000000C) HcInterruptStatus Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SO  : 1;       /*!< [0..0] USB schedule overrun (Scheduling Overrun)                          */
+            __IOM uint32_t WDH : 1;       /*!< [1..1] Host logic HccaDoneHead update (Writeback Done Head)               */
+            __IOM uint32_t SF  : 1;       /*!< [2..2] HccaFrameNumber update (StartOfFrame)                              */
+            __IOM uint32_t RD  : 1;       /*!< [3..3] Resume detection (Resume Detected)                                 */
+            __IOM uint32_t UE  : 1;       /*!< [4..4] USB non-related system error detection (Unrecoverable
+                                           *   Error)                                                                    */
+            __IOM uint32_t FNO  : 1;      /*!< [5..5] FrameNumber bit MSB change (Frame Number Overflow)                 */
+            __IOM uint32_t RHSC : 1;      /*!< [6..6] HcRhStatus/HcRhPortStatus register status (RootHubStatus
+                                           *   Change)                                                                   */
+            uint32_t          : 23;
+            __IOM uint32_t OC : 1;        /*!< [30..30] Host logic control right change (OwnershipChange)                */
+            uint32_t          : 1;
+        } HCINTERRUPTSTATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCINTERRUPTENABLE; /*!< (@ 0x00000010) HcInterruptEnable Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SOE   : 1;     /*!< [0..0] SO interrupt source enable (Scheduling OverrunEnable)              */
+            __IOM uint32_t WDHE  : 1;     /*!< [1..1] WDH interrupt source enable (WritebackDone HeadEnable)             */
+            __IOM uint32_t SFE   : 1;     /*!< [2..2] SF interrupt source enable (StartOfFrame)                          */
+            __IOM uint32_t RDE   : 1;     /*!< [3..3] RD interrupt source enable (Resume DetectedEnable)                 */
+            __IOM uint32_t UEE   : 1;     /*!< [4..4] UE interrupt source enable (Unrecoverable ErrorEnable)             */
+            __IOM uint32_t FNOE  : 1;     /*!< [5..5] FNO interrupt source enable (FrameNumber OverflowEnable)           */
+            __IOM uint32_t RHSCE : 1;     /*!< [6..6] RHSC interrupt source enable (RootHubStatus ChangeEnable)          */
+            uint32_t             : 23;
+            __IOM uint32_t OCE   : 1;     /*!< [30..30] OC interrupt source enable (OwnershipChangeEnable)               */
+            __IOM uint32_t MIE   : 1;     /*!< [31..31] Interrupt 8 source enable (MasterInterrupt Enable)               */
+        } HCINTERRUPTENABLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCINTERRUPTDISABLE; /*!< (@ 0x00000014) HcInterruptDisable Register                                */
+
+        struct
+        {
+            __IOM uint32_t SOD   : 1;      /*!< [0..0] SO interrupt source disable (Scheduling Overrun Disable)           */
+            __IOM uint32_t WDHD  : 1;      /*!< [1..1] WDH interrupt source disable (Writeback DoneHead Disable)          */
+            __IOM uint32_t SFD   : 1;      /*!< [2..2] SF interrupt source disable (StartOfFrame Disable)                 */
+            __IOM uint32_t RDD   : 1;      /*!< [3..3] RD interrupt source disable (Resume Detected Disable)              */
+            __IOM uint32_t UED   : 1;      /*!< [4..4] UE interrupt source disable (Unrecoverable ErrorDisable)           */
+            __IOM uint32_t FNOD  : 1;      /*!< [5..5] FNO interrupt source disable (FrameNumberOverflow Disable)         */
+            __IOM uint32_t RHSCD : 1;      /*!< [6..6] RHSC interrupt source disable (RootHub StatusChange Disable)       */
+            uint32_t             : 23;
+            __IOM uint32_t OCD   : 1;      /*!< [30..30] OC interrupt source disable (OwnershipChangeDisable)             */
+            __IOM uint32_t MID   : 1;      /*!< [31..31] Interrupt 8 source disable (Master Interrupt Disable)            */
+        } HCINTERRUPTDISABLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCHCCA;         /*!< (@ 0x00000018) HcHCCA Register                                            */
+
+        struct
+        {
+            uint32_t             : 8;
+            __IOM uint32_t RAMBA : 24; /*!< [31..8] RAM base address setting                                          */
+        } HCHCCA_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCPERIODCCURRENTIED; /*!< (@ 0x0000001C) HcPeriodicCurrentED Register                               */
+
+        struct
+        {
+            uint32_t           : 4;
+            __IM uint32_t PCED : 28;   /*!< [31..4] ED physical address (PeriodicCurrentED)                           */
+        } HCPERIODCCURRENTIED_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCCONTROLHEADED; /*!< (@ 0x00000020) HcControlHeadED Register                                   */
+
+        struct
+        {
+            uint32_t            : 4;
+            __IOM uint32_t CHED : 28;  /*!< [31..4] Start ED physical address (ControlHeadED)                         */
+        } HCCONTROLHEADED_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCCONTROLCURRENTED; /*!< (@ 0x00000024) HcControlCurrentED Register                                */
+
+        struct
+        {
+            uint32_t            : 4;
+            __IOM uint32_t CCED : 28;  /*!< [31..4] ED physical address (ControlCurrentED)                            */
+        } HCCONTROLCURRENTED_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCBULKHEADED;   /*!< (@ 0x00000028) HcBulkHeadED Register                                      */
+
+        struct
+        {
+            uint32_t            : 4;
+            __IOM uint32_t BHED : 28;  /*!< [31..4] Start ED physical address (BulkHeadED)                            */
+        } HCBULKHEADED_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCBULKCURRENTED; /*!< (@ 0x0000002C) HcBulkCurrentED Register                                   */
+
+        struct
+        {
+            uint32_t            : 4;
+            __IOM uint32_t BCED : 28;  /*!< [31..4] ED physical address (BulkCurrentED)                               */
+        } HCBULKCURRENTED_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCDONEHEAD;      /*!< (@ 0x00000030) HcDoneHead Register                                        */
+
+        struct
+        {
+            uint32_t         : 4;
+            __IM uint32_t DH : 28;     /*!< [31..4] HcDoneHead physical address (DoneHead)                            */
+        } HCDONEHEAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCFMINTERVAL;   /*!< (@ 0x00000034) HcFmInterval Register                                      */
+
+        struct
+        {
+            __IOM uint32_t FI    : 14; /*!< [13..0] Frame interval setting (FrameInterval)                            */
+            uint32_t             : 2;
+            __IOM uint32_t FSMPS : 15; /*!< [30..16] FS transfer packet maximum size setting (FSLagest DataPacket)    */
+            __IOM uint32_t FIT   : 1;  /*!< [31..31] Frame synchronization (FrameInterval Toggle)                     */
+        } HCFMINTERVAL_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCFNREMAINING;   /*!< (@ 0x00000038) HcFmRemaining Register                                     */
+
+        struct
+        {
+            __IM uint32_t FR  : 14;    /*!< [13..0] Down counter frame (FrameRemaining)                               */
+            uint32_t          : 17;
+            __IM uint32_t FRT : 1;     /*!< [31..31] Frame synchronization (FrameRemainingToggle)                     */
+        } HCFNREMAINING_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCFMNUMBER;      /*!< (@ 0x0000003C) HcFmNumber Register                                        */
+
+        struct
+        {
+            __IM uint32_t FN : 16;     /*!< [15..0] Elapsed frame number (FrameNumber)                                */
+            uint32_t         : 16;
+        } HCFMNUMBER_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCPERIODSTART;  /*!< (@ 0x00000040) HcPeriodicStart Register                                   */
+
+        struct
+        {
+            __IOM uint32_t PS : 14;    /*!< [13..0] Periodic list processing start time (PeriodicStart)               */
+            uint32_t          : 18;
+        } HCPERIODSTART_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCLSTHRESHOLD;  /*!< (@ 0x00000044) HcLSThreshold Register                                     */
+
+        struct
+        {
+            __IOM uint32_t LS : 12;    /*!< [11..0] Transferrable threshold (LSThreshold)                             */
+            uint32_t          : 20;
+        } HCLSTHRESHOLD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCRHDESCRIPTORA; /*!< (@ 0x00000048) HcRhDescriptorA Register                                   */
+
+        struct
+        {
+            __IM uint32_t  NDP  : 8;    /*!< [7..0] Downstream port number (NumberDownstreamPorts)                     */
+            __IOM uint32_t PSM  : 1;    /*!< [8..8] Power switch control (PowerSwitchingMode)                          */
+            __IOM uint32_t NPS  : 1;    /*!< [9..9] Power control (NoPower Switching)                                  */
+            __IM uint32_t  DT   : 1;    /*!< [10..10] Device type (DeviceType)                                         */
+            __IOM uint32_t OCPM : 1;    /*!< [11..11] Overcurrent state reporting (OverCurrentProtection
+                                         *   Mode)                                                                     */
+            __IOM uint32_t NOCP   : 1;  /*!< [12..12] Overcurrent function support (NoOver Current Protection)         */
+            uint32_t              : 11;
+            __IOM uint32_t POTPGT : 8;  /*!< [31..24] Wait time (PowerOnToPowerGood Time)                              */
+        } HCRHDESCRIPTORA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCRHDESCRIPTORB; /*!< (@ 0x0000004C) HcRhDescriptorB Register                                   */
+
+        struct
+        {
+            __IOM uint32_t DR   : 16;   /*!< [15..0] Device Removable                                                  */
+            __IOM uint32_t PPCM : 16;   /*!< [31..16] Port Power Control Mask                                          */
+        } HCRHDESCRIPTORB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCRHSTATUS;     /*!< (@ 0x00000050) HcRhStatus Register                                        */
+
+        struct
+        {
+            __IOM uint32_t LPS  : 1;   /*!< [0..0] Local power status (LocalPowerStatus)                              */
+            __IM uint32_t  OCI  : 1;   /*!< [1..1] Overcurrent indicator (OverCurrent Indicator)                      */
+            uint32_t            : 13;
+            __IOM uint32_t DRWE : 1;   /*!< [15..15] Device remote start enable (DeviceRemoteWakeupEnable)            */
+            __IOM uint32_t LPSC : 1;   /*!< [16..16] Local power status change (LocalPowerStatusChange)               */
+            __IOM uint32_t OCIC : 1;   /*!< [17..17] OCI bit change report (OverCurrent Indicate Change)              */
+            uint32_t            : 13;
+            __OM uint32_t CRWE  : 1;   /*!< [31..31] DRWE bit clear (Clear Remote Wakeup Enable)                      */
+        } HCRHSTATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCRHPORTSTATUS1; /*!< (@ 0x00000054) HcRhPortStatus1 Register                                   */
+
+        struct
+        {
+            __IOM uint32_t CCS  : 1;    /*!< [0..0] Connection status indication (CurrentConnectStatus)                */
+            __IOM uint32_t PES  : 1;    /*!< [1..1] Port enable status (PortEnableStatus)                              */
+            __IOM uint32_t PSS  : 1;    /*!< [2..2] Suspend/Resume status (PortSuspendStatus)                          */
+            __IM uint32_t  POCI : 1;    /*!< [3..3] Downstream port overcurrent detection (PortOverCurrentIndicator)   */
+            __IOM uint32_t PRS  : 1;    /*!< [4..4] Port reset status (PortResetStatus)                                */
+            uint32_t            : 3;
+            __IOM uint32_t PPS  : 1;    /*!< [8..8] Power status (PortPowerStatus)                                     */
+            __IOM uint32_t LSDA : 1;    /*!< [9..9] Device speed (LowSpeedDeviceAttached)                              */
+            uint32_t            : 6;
+            __IOM uint32_t CSC  : 1;    /*!< [16..16] CCS bit status (ConnectStatus Change)                            */
+            __IOM uint32_t PESC : 1;    /*!< [17..17] PES bit status (PortEnable StatusChange)                         */
+            __IOM uint32_t PSSC : 1;    /*!< [18..18] RESUME sequence complete (PortSuspend StatusChange)              */
+            __IOM uint32_t OCIC : 1;    /*!< [19..19] Overcurrent state detection (OverCurrent IndicateChange)         */
+            __IOM uint32_t PRSC : 1;    /*!< [20..20] Port reset complete (PortReset StatusChange)                     */
+            uint32_t            : 11;
+        } HCRHPORTSTATUS1_b;
+    };
+    __IM uint32_t RESERVED[42];
+
+    union
+    {
+        __IM uint32_t CAPL_VERSION;    /*!< (@ 0x00000100) Capability Registers Length and EHCI Version
+                                        *                  Number Register                                            */
+
+        struct
+        {
+            __IM uint32_t CRL   : 8;   /*!< [7..0] Capability Registers Length                                        */
+            uint32_t            : 8;
+            __IM uint32_t HCIVN : 16;  /*!< [31..16] EHCI Version Number                                              */
+        } CAPL_VERSION_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCSPARAMS;           /*!< (@ 0x00000104) Structural Parameters Register                             */
+
+        struct
+        {
+            __IM uint32_t N_PORTS     : 4; /*!< [3..0] Number of downstream ports (Number of Ports)                       */
+            __IM uint32_t PPC         : 1; /*!< [4..4] Port power control (Port Power Control)                            */
+            uint32_t                  : 2;
+            __IM uint32_t PTRR        : 1; /*!< [7..7] Port routing rules                                                 */
+            __IM uint32_t N_PCC       : 4; /*!< [11..8] Number of ports (Number of Ports per Companion Controller)        */
+            __IM uint32_t N_CC        : 4; /*!< [15..12] Number of OHCI host logic (Number of Companion Controller)       */
+            __IM uint32_t P_INDICATOR : 1; /*!< [16..16] Port indicator control support                                   */
+            uint32_t                  : 3;
+            __IM uint32_t DBGPTNUM    : 4; /*!< [23..20] Debug port number                                                */
+            uint32_t                  : 8;
+        } HCSPARAMS_b;
+    };
+
+    union
+    {
+        __IM uint32_t HCCPARAMS;       /*!< (@ 0x00000108) Capability Parameters Register                             */
+
+        struct
+        {
+            __IM uint32_t AC64 : 1;    /*!< [0..0] Memory pointer selection                                           */
+            __IM uint32_t PFLF : 1;    /*!< [1..1] Programming frame list flag                                        */
+            __IM uint32_t ASPC : 1;    /*!< [2..2] Asynchronous schedule park support capability                      */
+            uint32_t           : 1;
+            __IM uint32_t IST  : 4;    /*!< [7..4] Isochronous data structure threshold                               */
+            __IM uint32_t EECP : 8;    /*!< [15..8] Offset address (EHCI Extend Capabilities Pointer)                 */
+            __IM uint32_t HP   : 1;    /*!< [16..16] Hardware prefetch capability                                     */
+            __IM uint32_t LPMC : 1;    /*!< [17..17] Link power management capability                                 */
+            __IM uint32_t PCEC : 1;    /*!< [18..18] Per-port change event capability                                 */
+            __IM uint32_t PL32 : 1;    /*!< [19..19] 32-frame periodic list capability                                */
+            uint32_t           : 12;
+        } HCCPARAMS_b;
+    };
+    __IM uint32_t HCSP_PORTROUTE;      /*!< (@ 0x0000010C) Companion Port Route Description Register                  */
+    __IM uint32_t RESERVED1[4];
+
+    union
+    {
+        __IOM uint32_t USBCMD;          /*!< (@ 0x00000120) USB Command Register                                       */
+
+        struct
+        {
+            __IOM uint32_t RS      : 1; /*!< [0..0] EHCI host logic run/stop (Run/Stop)                                */
+            __IOM uint32_t HCRESET : 1; /*!< [1..1] Host logic initialization (Host Controller Reset)                  */
+            __IOM uint32_t FLS     : 2; /*!< [3..2] Frame list size                                                    */
+            __IOM uint32_t PSE     : 1; /*!< [4..4] Periodic schedule enable                                           */
+            __IOM uint32_t ASYNSE  : 1; /*!< [5..5] Asynchronous schedule enable                                       */
+            __IOM uint32_t IAAD    : 1; /*!< [6..6] Interrupt on Async Advance Doorbell                                */
+            __IM uint32_t  LHCR    : 1; /*!< [7..7] Light host controller reset execution status                       */
+            __IOM uint32_t ASPMC   : 2; /*!< [9..8] Asynchronous schedule park mode count                              */
+            uint32_t               : 1;
+            __IOM uint32_t ASPME   : 1; /*!< [11..11] Asynchronous schedule park mode enable                           */
+            uint32_t               : 3;
+            __IOM uint32_t PPCEE   : 1; /*!< [15..15] Per-port change event enable                                     */
+            __IOM uint32_t ITC     : 8; /*!< [23..16] Host logic interrupt generation maximum rate (Interrupt
+                                         *   Threshold Control)                                                        */
+            __IOM uint32_t HIRD : 4;    /*!< [27..24] Host-Initiated Resume Duration (Minimum K-state drive
+                                         *   time)                                                                     */
+            uint32_t : 4;
+        } USBCMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t USBSTS;             /*!< (@ 0x00000124) USB Status Register                                        */
+
+        struct
+        {
+            __IOM uint32_t USBINT    : 1;  /*!< [0..0] USB transfer complete (USB Interrupt)                              */
+            __IOM uint32_t USBERRINT : 1;  /*!< [1..1] USB transaction status (USB Error Interrupt)                       */
+            __IOM uint32_t PTCGDET   : 1;  /*!< [2..2] Port state change detection                                        */
+            __IOM uint32_t FLROV     : 1;  /*!< [3..3] Frame list rollover                                                */
+            __IOM uint32_t HSYSE     : 1;  /*!< [4..4] Host system error                                                  */
+            __IOM uint32_t IAAIS     : 1;  /*!< [5..5] Async advance interrupt status                                     */
+            uint32_t                 : 6;
+            __IM uint32_t  EHCSTS    : 1;  /*!< [12..12] EHCI host logic status (HCHalted)                                */
+            __IM uint32_t  RECLAM    : 1;  /*!< [13..13] Empty asynchronous schedule detection (Reclamation)              */
+            __IM uint32_t  PSCHSTS   : 1;  /*!< [14..14] Periodic schedule status                                         */
+            __IM uint32_t  ASS       : 1;  /*!< [15..15] Asynchronous schedule status                                     */
+            __IOM uint32_t PTCGDETC  : 16; /*!< [31..16] Port-n Change Detect                                             */
+        } USBSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t USBINTR;           /*!< (@ 0x00000128) USB Interrupt Enable Register                              */
+
+        struct
+        {
+            __IOM uint32_t USBIE    : 1;  /*!< [0..0] USB interrupt enable                                               */
+            __IOM uint32_t USBEIE   : 1;  /*!< [1..1] USB error interrupt enable                                         */
+            __IOM uint32_t PTCGIE   : 1;  /*!< [2..2] Port change interrupt enable                                       */
+            __IOM uint32_t FMLSTROE : 1;  /*!< [3..3] Frame list rollover enable                                         */
+            __IOM uint32_t HSEE     : 1;  /*!< [4..4] Host system error enable                                           */
+            __IOM uint32_t INTAADVE : 1;  /*!< [5..5] Interrupt on async advance enable                                  */
+            uint32_t                : 10;
+            __IOM uint32_t PCGIE    : 16; /*!< [31..16] Port-n Change Interrupt Enable                                   */
+        } USBINTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRINDEX;             /*!< (@ 0x0000012C) USB Frame Index Register                                   */
+
+        struct
+        {
+            __IOM uint32_t FRAMEINDEX : 14; /*!< [13..0] Frame index                                                       */
+            uint32_t                  : 18;
+        } FRINDEX_b;
+    };
+    __IM uint32_t CTRLDSSEGMENT;            /*!< (@ 0x00000130) Control Data Structure Segment Register                    */
+
+    union
+    {
+        __IOM uint32_t PERIODICLISTBASE;    /*!< (@ 0x00000134) Periodic Frame List Base Address Register                  */
+
+        struct
+        {
+            uint32_t             : 12;
+            __IOM uint32_t PFLSA : 20; /*!< [31..12] Periodic frame list start address                                */
+        } PERIODICLISTBASE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ASYNCLISTADDR;  /*!< (@ 0x00000138) Next Asynchronous List Address Register                    */
+
+        struct
+        {
+            uint32_t           : 5;
+            __IOM uint32_t LPL : 27;   /*!< [31..5] Asynchronous Queue Head link pointer address (Link Pointer
+                                        *   Low)                                                                      */
+        } ASYNCLISTADDR_b;
+    };
+    __IM uint32_t RESERVED2[9];
+
+    union
+    {
+        __IOM uint32_t CONFIGFLAG;     /*!< (@ 0x00000160) Configure Flag Register                                    */
+
+        struct
+        {
+            __IOM uint32_t CF : 1;     /*!< [0..0] Port routing control circuit configuration flag (Configure
+                                        *   Flag)                                                                     */
+            uint32_t : 31;
+        } CONFIGFLAG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PORTSC1;            /*!< (@ 0x00000164) Port 1 Status and Control Register                         */
+
+        struct
+        {
+            __IM uint32_t  CCSTS    : 1;   /*!< [0..0] Port connection status                                             */
+            __IOM uint32_t CSC      : 1;   /*!< [1..1] Connect status change                                              */
+            __IOM uint32_t PTE      : 1;   /*!< [2..2] Port enable/disable status                                         */
+            __IOM uint32_t PTESC    : 1;   /*!< [3..3] Port enable/disable status change                                  */
+            __IM uint32_t  OVCACT   : 1;   /*!< [4..4] Port overcurrent status                                            */
+            __IOM uint32_t OVCC     : 1;   /*!< [5..5] Over-current Change                                                */
+            __IOM uint32_t FRCPTRSM : 1;   /*!< [6..6] Force Port Resume (Port resume detection flag)                     */
+            __IOM uint32_t SUSPEND  : 1;   /*!< [7..7] Port suspend                                                       */
+            __IOM uint32_t PTRST    : 1;   /*!< [8..8] Port reset status                                                  */
+            __IOM uint32_t LPMCTL   : 1;   /*!< [9..9] LPM control                                                        */
+            __IM uint32_t  LINESTS  : 2;   /*!< [11..10] D+/D- logic level                                              */
+            __IOM uint32_t PP       : 1;   /*!< [12..12] Port Power Supply Control (Port Power)                           */
+            __IOM uint32_t PTOWNR   : 1;   /*!< [13..13] Port ownership                                                   */
+            __IM uint32_t  PTINDCTL : 2;   /*!< [15..14] As the host logic does not support the port indicator
+                                            *   control function, these bits are set to 00b.                              */
+            __IOM uint32_t PTTST    : 4;   /*!< [19..16] Pin test control                                                 */
+            __IOM uint32_t WKCNNT_E : 1;   /*!< [20..20] Device connection detection enable (Wake on Connect
+                                            *   Enable)                                                                   */
+            __IOM uint32_t WKDSCNNT_E : 1; /*!< [21..21] Device disconnection detection enable (Wake on Disconnect
+                                            *   Enable)                                                                   */
+            __IOM uint32_t WKOC_E : 1;     /*!< [22..22] Overcurrent state detection enable (Wake on Over-current
+                                            *   Enable)                                                                   */
+            __IOM uint32_t SUSPSTS : 2;    /*!< [24..23] Suspend status                                                   */
+            __IOM uint32_t DVADDR  : 7;    /*!< [31..25] USB device address                                               */
+        } PORTSC1_b;
+    };
+    __IM uint32_t RESERVED3[38];
+
+    union
+    {
+        __IOM uint32_t INTENABLE;            /*!< (@ 0x00000200) INT_ENABLE Register                                        */
+
+        struct
+        {
+            __IOM uint32_t AHB_INTEN    : 1; /*!< [0..0] AHB_INT bit control                                                */
+            __IOM uint32_t USBH_INTAEN  : 1; /*!< [1..1] USBH_INTA bit control                                              */
+            __IOM uint32_t USBH_INTBEN  : 1; /*!< [2..2] USBH_INTB bit control                                              */
+            __IOM uint32_t UCOM_INTEN   : 1; /*!< [3..3] UCOM_INT bit control                                               */
+            __IOM uint32_t WAKEON_INTEN : 1; /*!< [4..4] WAKEON_INT bit control                                             */
+            uint32_t                    : 27;
+        } INTENABLE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INTSTATUS;          /*!< (@ 0x00000204) INT_STATUS Register                                        */
+
+        struct
+        {
+            __IOM uint32_t AHB_INT    : 1; /*!< [0..0] AHB bus error indication                                           */
+            __IM uint32_t  USBH_INTA  : 1; /*!< [1..1] OHCI interrupt status                                              */
+            __IM uint32_t  USBH_INTB  : 1; /*!< [2..2] USBH_INTB EHCI interrupt status                                    */
+            __IM uint32_t  UCOM_INT   : 1; /*!< [3..3] UCOM register interrupt status                                     */
+            __IOM uint32_t WAKEON_INT : 1; /*!< [4..4] WAKEON interrupt status                                            */
+            uint32_t                  : 27;
+        } INTSTATUS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AHBBUSCTR;             /*!< (@ 0x00000208) AHB_BUS_CTR Register                                       */
+
+        struct
+        {
+            __IOM uint32_t MAX_BURST_LEN : 2; /*!< [1..0] Maximum burst length                                               */
+            uint32_t                     : 2;
+            __IOM uint32_t ALIGN_ADDRESS : 2; /*!< [5..4] Address boundary setting                                           */
+            uint32_t                     : 2;
+            __IOM uint32_t PROT_MODE     : 1; /*!< [8..8] This bit selects the MHPROT[3:0] mode when the AHB master
+                                               *   interface initiates a transfer.                                           */
+            uint32_t                 : 3;
+            __IOM uint32_t PROT_TYPE : 4;     /*!< [15..12] These bits set MHPROT[3:0] when the AHB master interface
+                                               *   initiates a transfer.                                                     */
+            uint32_t : 16;
+        } AHBBUSCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t USBCTR;           /*!< (@ 0x0000020C) USBCTR Register                                            */
+
+        struct
+        {
+            __OM uint32_t  USBH_RST : 1; /*!< [0..0] Software reset for the core                                        */
+            __IOM uint32_t PLL_RST  : 1; /*!< [1..1] Reset of USB PHY PLL                                               */
+            __IOM uint32_t DIRPD    : 1; /*!< [2..2] Direct transition to power-down state                              */
+            uint32_t                : 29;
+        } USBCTR_b;
+    };
+    __IM uint32_t RESERVED4[60];
+
+    union
+    {
+        __IM uint32_t REVID;           /*!< (@ 0x00000300) Revision and Core ID Register                              */
+
+        struct
+        {
+            __IM uint32_t MINV   : 8;  /*!< [7..0] Minor Version                                                      */
+            __IM uint32_t MAJV   : 8;  /*!< [15..8] Major Version                                                     */
+            uint32_t             : 8;
+            __IM uint32_t COREID : 8;  /*!< [31..24] Core ID                                                          */
+        } REVID_b;
+    };
+    __IM uint32_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint32_t OCSLPTIMSET;          /*!< (@ 0x00000310) Overcurrent Detection/Sleep Timer Setting Register         */
+
+        struct
+        {
+            __IOM uint32_t TIMER_OC    : 20; /*!< [19..0] Overcurrent Timer setting                                         */
+            __IOM uint32_t TIMER_SLEEP : 9;  /*!< [28..20] Detection/Sleep Timer Setting                                    */
+            uint32_t                   : 3;
+        } OCSLPTIMSET_b;
+    };
+    __IM uint32_t RESERVED6[315];
+
+    union
+    {
+        __IOM uint32_t COMMCTRL;       /*!< (@ 0x00000800) Common Control Register                                    */
+
+        struct
+        {
+            uint32_t            : 31;
+            __IOM uint32_t PERI : 1;   /*!< [31..31] USB mode setting                                                 */
+        } COMMCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OBINTSTA;               /*!< (@ 0x00000804) OTG-BC Interrupt Status Register                           */
+
+        struct
+        {
+            __IOM uint32_t IDCHG_STA      : 1; /*!< [0..0] USB_OTG_ID change status                                           */
+            __IOM uint32_t OCINT_STA      : 1; /*!< [1..1] USB_OVRCUR assertion status                                        */
+            __IOM uint32_t VBSTACHG_STA   : 1; /*!< [2..2] VBSTA[3:0] change status                                           */
+            __IOM uint32_t VBSTAINT_STA   : 1; /*!< [3..3] VBUS voltage status interrupt                                      */
+            uint32_t                      : 6;
+            __IOM uint32_t VVLDCHG_STA    : 1; /*!< [10..10] VBUSVALID change status                                          */
+            __IOM uint32_t IDDIGCHG_STA   : 1; /*!< [11..11] IDDIG0 change status                                             */
+            __IOM uint32_t SESSVLDCHG_STA : 1; /*!< [12..12] OTGSESSVLD change status                                         */
+            uint32_t                      : 3;
+            __IOM uint32_t DMMONCHG_STA   : 1; /*!< [16..16] DMMON change status                                              */
+            __IOM uint32_t DPMONCHG_STA   : 1; /*!< [17..17] DPMON change status                                              */
+            uint32_t                      : 14;
+        } OBINTSTA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OBINTEN;               /*!< (@ 0x00000808) OTG-BC Interrupt Enable Register                           */
+
+        struct
+        {
+            __IOM uint32_t IDCHG_EN      : 1; /*!< [0..0] IDCHG_STA Interrupt enable                                         */
+            __IOM uint32_t OCINT_EN      : 1; /*!< [1..1] OCINT_STA interrupt enable                                         */
+            __IOM uint32_t VBSTACHG_EN   : 1; /*!< [2..2] VBSTACHG_STA interrupt enable                                      */
+            __IOM uint32_t VBSTAINT_EN   : 1; /*!< [3..3] VBSTAINT_STA interrupt enable                                      */
+            uint32_t                     : 6;
+            __IOM uint32_t VVLDCHG_EN    : 1; /*!< [10..10] VVLDCHG_STA interrupt enable                                     */
+            __IOM uint32_t IDDIGCHG_EN   : 1; /*!< [11..11] IDDIGCHG_STA interrupt enable                                    */
+            __IOM uint32_t SESSVLDCHG_EN : 1; /*!< [12..12] SESSVLDCHG_STA interrupt enable                                  */
+            uint32_t                     : 3;
+            __IOM uint32_t DMMONCHG_EN   : 1; /*!< [16..16] DMMONCHG_STA interrupt enable                                    */
+            __IOM uint32_t DPMONCHG_EN   : 1; /*!< [17..17] DPMONCHG_STA interrupt enable                                    */
+            uint32_t                     : 14;
+        } OBINTEN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VBCTRL;            /*!< (@ 0x0000080C) VBUS Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t VBOUT     : 1; /*!< [0..0] VBUS drive control (USB_VBUSEN pin)                                */
+            __IOM uint32_t VBUSENSEL : 1; /*!< [1..1] USB_VBUSEN pin control                                             */
+            __IOM uint32_t SIDDQREL  : 1; /*!< [2..2] SIDDQ mode control                                                 */
+            uint32_t                 : 1;
+            __IOM uint32_t VGPUO     : 1; /*!< [4..4] USB_EXICEN pin control                                             */
+            uint32_t                 : 11;
+            __IOM uint32_t OCCLRIEN  : 1; /*!< [16..16] USB_VBUSEN pin control at occurrence of overcurrent              */
+            __IOM uint32_t OCISEL    : 1; /*!< [17..17] Overcurrent detection                                            */
+            uint32_t                 : 2;
+            __IOM uint32_t VBLVL     : 4; /*!< [23..20] VBUS level detection                                             */
+            uint32_t                 : 4;
+            __IM uint32_t VBSTA      : 4; /*!< [31..28] VBUS indication                                                  */
+        } VBCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LINECTRL1;        /*!< (@ 0x00000810) Line Control Port 1 Register                               */
+
+        struct
+        {
+            __IM uint32_t IDMON   : 1;   /*!< [0..0] Indicates a value of USB_OTG_ID input pin.                         */
+            uint32_t              : 1;
+            __IM uint32_t DMMON   : 1;   /*!< [2..2] Indicates a value of USB bus DM.                                   */
+            __IM uint32_t DPMON   : 1;   /*!< [3..3] Indicates a value of USB bus DP.                                   */
+            uint32_t              : 12;
+            __IOM uint32_t DM_RPD : 1;   /*!< [16..16] Controls USB bus (DM) 15 kOhm pulldown resistor when
+                                          *   DMPPD_EN = 1.                                                             */
+            __IOM uint32_t DMRPD_EN : 1; /*!< [17..17] Enables DM_RPD to control USB bus (DM) 15 kOhm pulldown
+                                          *   resistor.                                                                 */
+            __IOM uint32_t DP_RPD : 1;   /*!< [18..18] Controls USB bus (DP) 15 kOhm pulldown resistor when
+                                          *   DRPPD_EN = 1.                                                             */
+            __IOM uint32_t DPRPD_EN : 1; /*!< [19..19] Enables DP_RPD to control USB bus (DP) 15 kOhm pulldown
+                                          *   resistor.                                                                 */
+            uint32_t : 12;
+        } LINECTRL1_b;
+    };
+    __IM uint32_t RESERVED7[7];
+
+    union
+    {
+        __IOM uint32_t PHYCTRL;        /*!< (@ 0x00000830) PHY Control Register                                       */
+
+        struct
+        {
+            uint32_t                 : 4;
+            __IOM uint32_t DRVVBUS   : 1; /*!< [4..4] Drive VBUS                                                         */
+            __IOM uint32_t IDPULLUP0 : 1; /*!< [5..5] ID Input Sample Enable                                             */
+            uint32_t                 : 12;
+            __IM uint32_t VBUSVALID  : 1; /*!< [18..18] VBUS Valid Indicator                                             */
+            __IM uint32_t IDDIG0     : 1; /*!< [19..19] Mini A/B Plug Indicator                                          */
+            __IM uint32_t OTGSESSVLD : 1; /*!< [20..20] OTG Device Session Valid Indicator                               */
+            uint32_t                 : 11;
+        } PHYCTRL_b;
+    };
+} R_USBHC_Type;                           /*!< Size = 2100 (0x834)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USBF                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 Host and Function Module (R_USBF)
+ */
+
+typedef struct                         /*!< (@ 0x92041000) R_USBF Structure                                           */
+{
+    union
+    {
+        __IOM uint16_t SYSCFG0;        /*!< (@ 0x00000000) System Configuration Control Register 0                    */
+
+        struct
+        {
+            __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Block Operation Enable                                         */
+            uint16_t             : 3;
+            __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
+            __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                      */
+            uint16_t             : 1;
+            __IOM uint16_t HSE   : 1;  /*!< [7..7] High-Speed Operation Enable                                        */
+            __IOM uint16_t CNEN  : 1;  /*!< [8..8] Single-End Receiver Operation Enable                               */
+            uint16_t             : 7;
+        } SYSCFG0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SYSCFG1;        /*!< (@ 0x00000002) System Configuration Control Register 1                    */
+
+        struct
+        {
+            __IOM uint16_t BWAIT : 6;  /*!< [5..0] CPU Bus Access Wait Specification                                  */
+            uint16_t             : 2;
+            __IOM uint16_t AWAIT : 6;  /*!< [13..8] AHB-DMA Bridge Bus Access Wait Specification                      */
+            uint16_t             : 2;
+        } SYSCFG1_b;
+    };
+
+    union
+    {
+        __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register                       */
+
+        struct
+        {
+            __IM uint16_t LNST : 2;    /*!< [1..0] USB Data Line Status Monitor                                       */
+            uint16_t           : 14;
+        } SYSSTS0_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t DVSTCTR0;       /*!< (@ 0x00000008) Device State Control Register 0                            */
+
+        struct
+        {
+            __IM uint16_t RHST  : 3;   /*!< [2..0] Reset Handshake                                                    */
+            uint16_t            : 5;
+            __IOM uint16_t WKUP : 1;   /*!< [8..8] Wakeup Output                                                      */
+            uint16_t            : 7;
+        } DVSTCTR0_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
+
+        struct
+        {
+            __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
+            uint16_t            : 12;
+        } TESTMODE_b;
+    };
+    __IM uint16_t RESERVED2;
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CFIFO;             /*!< (@ 0x00000014) FIFO Port Register                                         */
+
+            struct
+            {
+                __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
+            } CFIFO_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) FIFO Port Register                                         */
+                __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) FIFO Port Register                                         */
+            };
+
+            union
+            {
+                union
+                {
+                    __IOM uint16_t CFIFOH;            /*!< (@ 0x00000016) FIFO Port Register                                         */
+
+                    struct
+                    {
+                        __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
+                    } CFIFOH_b;
+                };
+
+                struct
+                {
+                    __IM uint8_t RESERVED4;
+
+                    union
+                    {
+                        __IOM uint8_t CFIFOHH;          /*!< (@ 0x00000017) FIFO Port Register                                         */
+
+                        struct
+                        {
+                            __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
+                        } CFIFOHH_b;
+                    };
+                };
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t D0FIFO;            /*!< (@ 0x00000018) FIFO Port Register                                         */
+
+            struct
+            {
+                __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
+            } D0FIFO_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) FIFO Port Register                                         */
+                __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) FIFO Port Register                                         */
+            };
+
+            union
+            {
+                union
+                {
+                    __IOM uint16_t D0FIFOH;           /*!< (@ 0x0000001A) FIFO Port Register                                         */
+
+                    struct
+                    {
+                        __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
+                    } D0FIFOH_b;
+                };
+
+                struct
+                {
+                    __IM uint8_t RESERVED5;
+
+                    union
+                    {
+                        __IOM uint8_t D0FIFOHH;         /*!< (@ 0x0000001B) FIFO Port Register                                         */
+
+                        struct
+                        {
+                            __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
+                        } D0FIFOHH_b;
+                    };
+                };
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t D1FIFO;            /*!< (@ 0x0000001C) FIFO Port Register                                         */
+
+            struct
+            {
+                __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
+            } D1FIFO_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) FIFO Port Register                                         */
+                __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) FIFO Port Register                                         */
+            };
+
+            union
+            {
+                union
+                {
+                    __IOM uint16_t D1FIFOH;           /*!< (@ 0x0000001E) FIFO Port Register                                         */
+
+                    struct
+                    {
+                        __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
+                    } D1FIFOH_b;
+                };
+
+                struct
+                {
+                    __IM uint8_t RESERVED6;
+
+                    union
+                    {
+                        __IOM uint8_t D1FIFOHH;         /*!< (@ 0x0000001F) FIFO Port Register                                         */
+
+                        struct
+                        {
+                            __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
+                        } D1FIFOHH_b;
+                    };
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 1;
+            __IOM uint16_t ISEL    : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected                    */
+            uint16_t               : 2;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
+            uint16_t               : 2;
+            __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
+        } CFIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) FIFO Port Control Register                                 */
+
+        struct
+        {
+            __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } CFIFOCTR_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA Request Enable                                               */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe
+                                         *   Data is Read                                                              */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D0FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) FIFO Port Control Register                                 */
+
+        struct
+        {
+            __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D0FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA Request Enable                                               */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe
+                                         *   Data is Read                                                              */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D1FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) FIFO Port Control Register                                 */
+
+        struct
+        {
+            __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D1FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
+            __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
+            __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
+            __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
+            __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
+            __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
+            __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
+            __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
+        } INTENB0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB1;           /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINTE : 1; /*!< [0..0] PDDETINT Detection Interrupt Enable                                */
+            uint16_t                 : 15;
+        } INTENB1_b;
+    };
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe                                */
+            uint16_t                 : 6;
+        } BRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe                                */
+            uint16_t                 : 6;
+        } NRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe                                */
+            uint16_t                 : 6;
+        } BEMPENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Pin Configuration Register                             */
+
+        struct
+        {
+            uint16_t               : 4;
+            __IM uint16_t  EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status                                   */
+            __IOM uint16_t INTL    : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
+            __IOM uint16_t BRDYM   : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing                             */
+            uint16_t               : 9;
+        } SOFCFG_b;
+    };
+    __IM uint16_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
+
+        struct
+        {
+            __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
+            __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
+            __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
+            __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
+            __IM uint16_t  BRDY  : 1;  /*!< [8..8] BRDY Interrupt Status                                              */
+            __IM uint16_t  NRDY  : 1;  /*!< [9..9] NRDY Interrupt Status                                              */
+            __IM uint16_t  BEMP  : 1;  /*!< [10..10] BEMP Interrupt Status                                            */
+            __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
+            __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
+            __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Update Interrupt Status                             */
+            __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
+            __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Change Detect Interrupt Status                              */
+        } INTSTS0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS1;          /*!< (@ 0x00000042) Interrupt Status Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINT : 1; /*!< [0..0] PDDET Detection Interrupt Status                                   */
+            uint16_t                : 15;
+        } INTSTS1_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe                                */
+            uint16_t                : 6;
+        } BRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe                                */
+            uint16_t                : 6;
+        } NRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe                                */
+            uint16_t                : 6;
+        } BEMPSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
+
+        struct
+        {
+            __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame Number                                                      */
+            uint16_t            : 3;
+            __IOM uint16_t CRCE : 1;   /*!< [14..14] CRC Error Detection Status                                       */
+            __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
+        } FRMNUM_b;
+    };
+
+    union
+    {
+        __IM uint16_t UFRMNUM;         /*!< (@ 0x0000004E) Frame Number Register                                      */
+
+        struct
+        {
+            __IM uint16_t UFRNM : 3;   /*!< [2..0] Microframe Number                                                  */
+            uint16_t            : 13;
+        } UFRMNUM_b;
+    };
+
+    union
+    {
+        __IM uint16_t USBADDR;         /*!< (@ 0x00000050) USB Address Register                                       */
+
+        struct
+        {
+            __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address                                                        */
+            uint16_t              : 9;
+        } USBADDR_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
+
+        struct
+        {
+            __IM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request Type                                                       */
+            __IM uint16_t BREQUEST      : 8; /*!< [15..8] Request                                                           */
+        } USBREQ_b;
+    };
+
+    union
+    {
+        __IM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
+
+        struct
+        {
+            __IM uint16_t WVALUE : 16; /*!< [15..0] Value                                                             */
+        } USBVAL_b;
+    };
+
+    union
+    {
+        __IM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
+
+        struct
+        {
+            __IM uint16_t WINDEX : 16; /*!< [15..0] Index                                                             */
+        } USBINDX_b;
+    };
+
+    union
+    {
+        __IM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
+
+        struct
+        {
+            __IM uint16_t WLENGTH : 16; /*!< [15..0] Length                                                            */
+        } USBLENG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
+
+        struct
+        {
+            uint16_t              : 7;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Disabling PIPE at the End of Transfer                              */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
+            uint16_t              : 7;
+        } DCPCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet Size                                                */
+            uint16_t            : 9;
+        } DCPMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCTR;         /*!< (@ 0x00000060) DCP Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t PID   : 2;  /*!< [1..0] Response PID                                                       */
+            __IOM uint16_t CCPL  : 1;  /*!< [2..2] Control Transfer End Enable                                        */
+            uint16_t             : 2;
+            __IM uint16_t  PBUSY : 1;  /*!< [5..5] PIPE Busy                                                          */
+            __IM uint16_t  SQMON : 1;  /*!< [6..6] Sequence Toggle Bit Monitor                                        */
+            __IOM uint16_t SQSET : 1;  /*!< [7..7] Toggle Bit Set                                                     */
+            __IOM uint16_t SQCLR : 1;  /*!< [8..8] Toggle Bit Clear                                                   */
+            uint16_t             : 6;
+            __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
+        } DCPCTR_b;
+    };
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
+            uint16_t               : 12;
+        } PIPESEL_b;
+    };
+    __IM uint16_t RESERVED13;
+
+    union
+    {
+        __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
+
+        struct
+        {
+            __IOM uint16_t EPNUM  : 4; /*!< [3..0] Endpoint Number                                                    */
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disable at the End of Transfer                                */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
+            __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
+            __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
+            uint16_t              : 3;
+            __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
+        } PIPECFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Specification Register                         */
+
+        struct
+        {
+            __IOM uint16_t BUFNMB  : 8; /*!< [7..0] Buffer number                                                      */
+            uint16_t               : 2;
+            __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer size                                                      */
+            uint16_t               : 1;
+        } PIPEBUF_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 11;  /*!< [10..0] Maximum Packet Size                                               */
+            uint16_t            : 5;
+        } PIPEMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Timing Control Register                               */
+
+        struct
+        {
+            __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection Spacing                                   */
+            uint16_t            : 9;
+            __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
+            uint16_t            : 3;
+        } PIPEPERI_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) PIPE[0..8] Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
+            uint16_t              : 3;
+            __IM uint16_t  PBUSY  : 1; /*!< [5..5] PIPE Busy                                                          */
+            __IM uint16_t  SQMON  : 1; /*!< [6..6] Toggle Bit Confirm                                                 */
+            __IOM uint16_t SQSET  : 1; /*!< [7..7] Toggle Bit Set                                                     */
+            __IOM uint16_t SQCLR  : 1; /*!< [8..8] Toggle Bit Clear                                                   */
+            __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
+            __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
+            uint16_t              : 3;
+            __IM uint16_t INBUFM  : 1; /*!< [14..14] Transfer Buffer Monitor                                          */
+            __IM uint16_t BSTS    : 1; /*!< [15..15] Buffer Status                                                    */
+        } PIPE_CTR_b[9];
+    };
+    __IM uint16_t             RESERVED14;
+    __IM uint32_t             RESERVED15[3];
+    __IOM R_USBF_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) PIPEn Transaction Counter Registers (n=1-5)                */
+    __IM uint32_t             RESERVED16[23];
+    __IM uint16_t             RESERVED17;
+
+    union
+    {
+        __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
+
+        struct
+        {
+            uint16_t             : 14;
+            __IOM uint16_t SUSPM : 1;  /*!< [14..14] UTMI SuspendM Control                                            */
+            uint16_t             : 1;
+        } LPSTS_b;
+    };
+    __IM uint32_t         RESERVED18[191];
+    __IOM R_USBF_CHa_Type CHa[2];      /*!< (@ 0x00000400) Next Register Set                                          */
+    __IM uint32_t         RESERVED19[96];
+    __IOM R_USBF_CHb_Type CHb[2];      /*!< (@ 0x00000600) Skip Register Set                                          */
+    __IM uint32_t         RESERVED20[48];
+
+    union
+    {
+        __IOM uint32_t DCTRL;          /*!< (@ 0x00000700) DMA Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t PR   : 1;   /*!< [0..0] Priority                                                           */
+            uint32_t            : 15;
+            __IOM uint32_t LDPR : 4;   /*!< [19..16] Link Descriptor PROT                                             */
+            uint32_t            : 4;
+            __IOM uint32_t LWPR : 4;   /*!< [27..24] Link WriteBack PROT                                              */
+            uint32_t            : 4;
+        } DCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DSCITVL;        /*!< (@ 0x00000704) Descriptor Interval Register                               */
+
+        struct
+        {
+            uint32_t             : 8;
+            __IOM uint32_t DITVL : 8;  /*!< [15..8] Descriptor Interval                                               */
+            uint32_t             : 16;
+        } DSCITVL_b;
+    };
+    __IM uint32_t RESERVED21[2];
+
+    union
+    {
+        __IM uint32_t DSTAT_EN;        /*!< (@ 0x00000710) DMA Status EN Register                                     */
+
+        struct
+        {
+            __IM uint32_t EN0 : 1;     /*!< [0..0] Channel 0 EN                                                       */
+            __IM uint32_t EN1 : 1;     /*!< [1..1] Channel 1 EN                                                       */
+            uint32_t          : 30;
+        } DSTAT_EN_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_ER;        /*!< (@ 0x00000714) DMA Status ER Register                                     */
+
+        struct
+        {
+            __IM uint32_t ER0 : 1;     /*!< [0..0] Channel 0 ER                                                       */
+            __IM uint32_t ER1 : 1;     /*!< [1..1] Channel 1 ER                                                       */
+            uint32_t          : 30;
+        } DSTAT_ER_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_END;       /*!< (@ 0x00000718) DMA Status END Register                                    */
+
+        struct
+        {
+            __IM uint32_t END0 : 1;    /*!< [0..0] Channel 0 END                                                      */
+            __IM uint32_t END1 : 1;    /*!< [1..1] Channel 1 END                                                      */
+            uint32_t           : 30;
+        } DSTAT_END_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_TC;        /*!< (@ 0x0000071C) DMA Status TC Register                                     */
+
+        struct
+        {
+            __IM uint32_t TC0 : 1;     /*!< [0..0] Channel 0 TC                                                       */
+            __IM uint32_t TC1 : 1;     /*!< [1..1] Channel 1 TC                                                       */
+            uint32_t          : 30;
+        } DSTAT_TC_b;
+    };
+
+    union
+    {
+        __IM uint32_t DSTAT_SUS;       /*!< (@ 0x00000720) DMA Status SUS Register                                    */
+
+        struct
+        {
+            __IM uint32_t SUS0 : 1;    /*!< [0..0] Channel 0 SUS                                                      */
+            __IM uint32_t SUS1 : 1;    /*!< [1..1] Channel 1 SUS                                                      */
+            uint32_t           : 30;
+        } DSTAT_SUS_b;
+    };
+} R_USBF_Type;                         /*!< Size = 1828 (0x724)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SDHI0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief SD/MMC Host Interface (R_SDHI0)
+ */
+
+typedef struct                           /*!< (@ 0x92080000) R_SDHI0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t SD_CMD;           /*!< (@ 0x00000000) Command Type Register                                      */
+
+        struct
+        {
+            __IOM uint32_t CF45CF40 : 6; /*!< [5..0] Command Index                                                      */
+            __IOM uint32_t C1C0     : 2; /*!< [7..6] C1C0                                                               */
+            __IOM uint32_t MD2MD0   : 3; /*!< [10..8] Mode/Response Type                                                */
+            __IOM uint32_t MD3      : 1; /*!< [11..11] Data Mode (Command Type)                                         */
+            __IOM uint32_t MD4      : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data
+                                          *   is handled)                                                               */
+            __IOM uint32_t MD5 : 1;      /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
+                                          *   with data is handled)                                                     */
+            __IOM uint32_t MD7MD6 : 2;   /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
+                                          *   transfer)                                                                 */
+            uint32_t : 16;
+        } SD_CMD_b;
+    };
+    __IM uint32_t  RESERVED[3];
+    __IOM uint32_t SD_ARG;             /*!< (@ 0x00000010) Command Argument Register                                  */
+    __IM uint32_t  RESERVED1;
+    __IOM uint32_t SD_ARG1;            /*!< (@ 0x00000018) Command Argument Register 1                                */
+    __IM uint32_t  RESERVED2;
+
+    union
+    {
+        __IOM uint32_t SD_STOP;         /*!< (@ 0x00000020) Data Stop Register                                         */
+
+        struct
+        {
+            __IOM uint32_t STP     : 1; /*!< [0..0] Stop                                                               */
+            uint32_t               : 7;
+            __IOM uint32_t SEC     : 1; /*!< [8..8] Block Count Enable                                                 */
+            uint32_t               : 7;
+            __IOM uint32_t HPICMD  : 1; /*!< [16..16] HPI Command Issue                                                */
+            __IOM uint32_t HPIMODE : 1; /*!< [17..17] HPI Mode Enable                                                  */
+            uint32_t               : 14;
+        } SD_STOP_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t SD_SECCNT;          /*!< (@ 0x00000028) Block Count Register                                       */
+
+        struct
+        {
+            __IOM uint32_t CNT31CNT0 : 32; /*!< [31..0] Number of Transfer Blocks                                         */
+        } SD_SECCNT_b;
+    };
+    __IM uint32_t RESERVED4;
+
+    union
+    {
+        __IM uint32_t SD_RSP10L;       /*!< (@ 0x00000030) SD Card Response 10L Register                              */
+
+        struct
+        {
+            __IM uint32_t R39R8 : 32;  /*!< [31..0] Hold the response from the SD card                                */
+        } SD_RSP10L_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t SD_RSP1;         /*!< (@ 0x00000038) SD Card Response 1 Register                                */
+
+            struct
+            {
+                __IM uint32_t R39R24 : 16; /*!< [15..0] Hold the response from the SD card                                */
+                uint32_t             : 16;
+            } SD_RSP1_b;
+        };
+
+        union
+        {
+            __IM uint32_t SD_RSP10H;       /*!< (@ 0x00000038) SD Card Response 10H Register                              */
+
+            struct
+            {
+                __IM uint32_t R71R40 : 32; /*!< [31..0] Hold the response from the SD card                                */
+            } SD_RSP10H_b;
+        };
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IM uint32_t SD_RSP32;        /*!< (@ 0x00000040) SD Card Response 32 Register                               */
+
+        struct
+        {
+            __IM uint32_t R71R40 : 32; /*!< [31..0] R71R40                                                            */
+        } SD_RSP32_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IM uint32_t SD_RSP3;         /*!< (@ 0x00000048) SD Card Response 3 Register                                */
+
+        struct
+        {
+            __IM uint32_t R71R56 : 16; /*!< [15..0] R71R56                                                            */
+            uint32_t             : 16;
+        } SD_RSP3_b;
+    };
+    __IM uint32_t RESERVED8;
+
+    union
+    {
+        __IM uint32_t SD_RSP54L;        /*!< (@ 0x00000050) SD Card Response 54L Register                              */
+
+        struct
+        {
+            __IM uint32_t R103R72 : 32; /*!< [31..0] Hold the response from the SD card                                */
+        } SD_RSP54L_b;
+    };
+    __IM uint32_t RESERVED9;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t SD_RSP5;          /*!< (@ 0x00000058) SD Card Response 5 Register                                */
+
+            struct
+            {
+                __IM uint32_t R103R88 : 16; /*!< [15..0] R103R88                                                           */
+                uint32_t              : 16;
+            } SD_RSP5_b;
+        };
+
+        union
+        {
+            __IM uint32_t SD_RSP54H;         /*!< (@ 0x00000058) SD Card Response 54H Register                              */
+
+            struct
+            {
+                __IM uint32_t R127R104 : 24; /*!< [23..0] Hold the response from the SD card                                */
+                uint32_t               : 8;
+            } SD_RSP54H_b;
+        };
+    };
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IM uint32_t SD_RSP76;          /*!< (@ 0x00000060) SD Card Response 76 Register                               */
+
+        struct
+        {
+            __IM uint32_t R127R104 : 24; /*!< [23..0] R127R104                                                          */
+            uint32_t               : 8;
+        } SD_RSP76_b;
+    };
+    __IM uint32_t RESERVED11;
+
+    union
+    {
+        __IM uint32_t SD_RSP7;          /*!< (@ 0x00000068) SD Card Response 7 Register                                */
+
+        struct
+        {
+            __IM uint32_t R127R120 : 8; /*!< [7..0] R127R120                                                           */
+            uint32_t               : 24;
+        } SD_RSP7_b;
+    };
+    __IM uint32_t RESERVED12;
+
+    union
+    {
+        __IOM uint32_t SD_INFO1;       /*!< (@ 0x00000070) SD Card Interrupt Flag Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t INFO0  : 1; /*!< [0..0] Response End                                                       */
+            uint32_t              : 1;
+            __IOM uint32_t INFO2  : 1; /*!< [2..2] Access End                                                         */
+            __IOM uint32_t INFO3  : 1; /*!< [3..3] ISDCD Card Removal                                                 */
+            __IOM uint32_t INFO4  : 1; /*!< [4..4] ISDCD Card Insertion                                               */
+            __IM uint32_t  INFO5  : 1; /*!< [5..5] Indicates the ISDCD state.                                         */
+            uint32_t              : 1;
+            __IM uint32_t  INFO7  : 1; /*!< [7..7] Write Protect                                                      */
+            __IOM uint32_t INFO8  : 1; /*!< [8..8] SDDAT3 Card Removal                                                */
+            __IOM uint32_t INFO9  : 1; /*!< [9..9] SDDAT3 Card Insertion                                              */
+            __IM uint32_t  INFO10 : 1; /*!< [10..10] INFO10                                                           */
+            uint32_t              : 5;
+            __IOM uint32_t HPIRES : 1; /*!< [16..16] Response Reception Completion                                    */
+            uint32_t              : 15;
+        } SD_INFO1_b;
+    };
+    __IM uint32_t RESERVED13;
+
+    union
+    {
+        __IOM uint32_t SD_INFO2;         /*!< (@ 0x00000078) SD Card Interrupt Flag Register 2                          */
+
+        struct
+        {
+            __IOM uint32_t ERR0     : 1; /*!< [0..0] CMD Error                                                          */
+            __IOM uint32_t ERR1     : 1; /*!< [1..1] CRC Error                                                          */
+            __IOM uint32_t ERR2     : 1; /*!< [2..2] END Error                                                          */
+            __IOM uint32_t ERR3     : 1; /*!< [3..3] Data Timeout (except response timeout)                             */
+            __IOM uint32_t ERR4     : 1; /*!< [4..4] SD_BUF Illegal Write Access                                        */
+            __IOM uint32_t ERR5     : 1; /*!< [5..5] SD_BUF Illegal Read Access                                         */
+            __IOM uint32_t ERR6     : 1; /*!< [6..6] Response Timeout                                                   */
+            __IM uint32_t  DAT0     : 1; /*!< [7..7] SDDAT0                                                             */
+            __IOM uint32_t BRE      : 1; /*!< [8..8] SD_BUF Read Enable                                                 */
+            __IOM uint32_t BWE      : 1; /*!< [9..9] SD_BUF Write Enable                                                */
+            uint32_t                : 3;
+            __IM uint32_t SCLKDIVEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
+                                          *   the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
+                                          *   bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
+                                          *   cycles of SDCLK have elapsed after setting of the CBSY
+                                          *   bit to 0 due to completion of the command sequence.                       */
+            __IM uint32_t  CBSY : 1;     /*!< [14..14] Command Type Register Busy                                       */
+            __IOM uint32_t ILA  : 1;     /*!< [15..15] Illegal Access Error                                             */
+            uint32_t            : 16;
+        } SD_INFO2_b;
+    };
+    __IM uint32_t RESERVED14;
+
+    union
+    {
+        __IOM uint32_t SD_INFO1_MASK;   /*!< (@ 0x00000080) SD_INFO1 Interrupt Mask Register                           */
+
+        struct
+        {
+            __IOM uint32_t IMASK0  : 1; /*!< [0..0] IMASK0                                                             */
+            uint32_t               : 1;
+            __IOM uint32_t IMASK2  : 1; /*!< [2..2] IMASK2                                                             */
+            __IOM uint32_t IMASK3  : 1; /*!< [3..3] IMASK3                                                             */
+            __IOM uint32_t IMASK4  : 1; /*!< [4..4] IMASK4                                                             */
+            uint32_t               : 3;
+            __IOM uint32_t IMASK8  : 1; /*!< [8..8] IMASK8                                                             */
+            __IOM uint32_t IMASK9  : 1; /*!< [9..9] IMASK9                                                             */
+            uint32_t               : 6;
+            __IOM uint32_t IMASK16 : 1; /*!< [16..16] IMASK16                                                          */
+            uint32_t               : 15;
+        } SD_INFO1_MASK_b;
+    };
+    __IM uint32_t RESERVED15;
+
+    union
+    {
+        __IOM uint32_t SD_INFO2_MASK;  /*!< (@ 0x00000088) SD_INFO2 Interrupt Mask Register                           */
+
+        struct
+        {
+            __IOM uint32_t EMASK0 : 1; /*!< [0..0] EMASK0                                                             */
+            __IOM uint32_t EMASK1 : 1; /*!< [1..1] EMASK1                                                             */
+            __IOM uint32_t EMASK2 : 1; /*!< [2..2] EMASK2                                                             */
+            __IOM uint32_t EMASK3 : 1; /*!< [3..3] EMASK3                                                             */
+            __IOM uint32_t EMASK4 : 1; /*!< [4..4] EMASK4                                                             */
+            __IOM uint32_t EMASK5 : 1; /*!< [5..5] EMASK5                                                             */
+            __IOM uint32_t EMASK6 : 1; /*!< [6..6] EMASK6                                                             */
+            uint32_t              : 1;
+            __IOM uint32_t BMASK0 : 1; /*!< [8..8] BMASK0                                                             */
+            __IOM uint32_t BMASK1 : 1; /*!< [9..9] BMASK1                                                             */
+            uint32_t              : 5;
+            __IOM uint32_t IMASK  : 1; /*!< [15..15] IMASK                                                            */
+            uint32_t              : 16;
+        } SD_INFO2_MASK_b;
+    };
+    __IM uint32_t RESERVED16;
+
+    union
+    {
+        __IOM uint32_t SD_CLK_CTRL;        /*!< (@ 0x00000090) SD Clock Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t DIV7DIV0   : 8; /*!< [7..0] SD Clock (SDCLK)                                                   */
+            __IOM uint32_t SCLKEN     : 1; /*!< [8..8] SCLKEN                                                             */
+            __IOM uint32_t SDCLKOFFEN : 1; /*!< [9..9] SD Clock (SDCLK) Output Automatic Control Enable                   */
+            uint32_t                  : 22;
+        } SD_CLK_CTRL_b;
+    };
+    __IM uint32_t RESERVED17;
+
+    union
+    {
+        __IOM uint32_t SD_SIZE;           /*!< (@ 0x00000098) Transfer Data Length Register                              */
+
+        struct
+        {
+            __IOM uint32_t LEN9LEN0 : 10; /*!< [9..0] Transfer Data Size                                                 */
+            uint32_t                : 22;
+        } SD_SIZE_b;
+    };
+    __IM uint32_t RESERVED18;
+
+    union
+    {
+        __IOM uint32_t SD_OPTION;            /*!< (@ 0x000000A0) SD Card Access Control Option Register                     */
+
+        struct
+        {
+            __IOM uint32_t CTOP24CTOP21 : 4; /*!< [3..0] Card Detect Time Counter                                           */
+            __IOM uint32_t TOP27TOP24   : 4; /*!< [7..4] TOP27TOP24                                                         */
+            __IOM uint32_t TOUTMASK     : 1; /*!< [8..8] Timeout Mask                                                       */
+            __IOM uint32_t EXTOP        : 1; /*!< [9..9] EXTOP                                                              */
+            uint32_t                    : 3;
+            __IOM uint32_t WIDTH8       : 1; /*!< [13..13] Bus width                                                        */
+            uint32_t                    : 1;
+            __IOM uint32_t WIDTH        : 1; /*!< [15..15] Bus width                                                        */
+            uint32_t                    : 16;
+        } SD_OPTION_b;
+    };
+    __IM uint32_t RESERVED19[3];
+
+    union
+    {
+        __IM uint32_t SD_ERR_STS1;     /*!< (@ 0x000000B0) SD Error Status Register 1                                 */
+
+        struct
+        {
+            __IM uint32_t E0 : 1;      /*!< [0..0] E0                                                                 */
+            __IM uint32_t E1 : 1;      /*!< [1..1] Set to 1 when an error occurs in the command index of
+                                        *   the response to a command issued within a command sequence.               */
+            __IM uint32_t E2 : 1;      /*!< [2..2] E2                                                                 */
+            __IM uint32_t E3 : 1;      /*!< [3..3] Set to 1 when an error occurs in the response length
+                                        *   to a command issued within a command sequence.                            */
+            __IM uint32_t E4 : 1;      /*!< [4..4] E4                                                                 */
+            __IM uint32_t E5 : 1;      /*!< [5..5] E5                                                                 */
+            uint32_t         : 2;
+            __IM uint32_t E8 : 1;      /*!< [8..8] E8                                                                 */
+            __IM uint32_t E9 : 1;      /*!< [9..9] Set to 1 when a CRC error occurs in the response to a
+                                        *   command issued within a command sequence.                                 */
+            __IM uint32_t E10    : 1;  /*!< [10..10] E10                                                              */
+            __IM uint32_t E11    : 1;  /*!< [11..11] E11                                                              */
+            __IM uint32_t E14E12 : 3;  /*!< [14..12] E14E12                                                           */
+            uint32_t             : 17;
+        } SD_ERR_STS1_b;
+    };
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        __IM uint32_t SD_ERR_STS2;     /*!< (@ 0x000000B8) SD Error Status Register 2                                 */
+
+        struct
+        {
+            __IM uint32_t E0 : 1;      /*!< [0..0] E0                                                                 */
+            __IM uint32_t E1 : 1;      /*!< [1..1] Set to 1 when the response to a command issued within
+                                        *   a command sequence is not received even after 640 cycles
+                                        *   of SDCLK have elapsed.                                                    */
+            __IM uint32_t E2 : 1;      /*!< [2..2] Set to 1 when the interface remains in a busy state for
+                                        *   at least Ncycle after R1b response.                                       */
+            __IM uint32_t E3 : 1;      /*!< [3..3] Set to 1 when the interface remains in a busy state for
+                                        *   at least Ncycle after CMD12 has been issued within a command
+                                        *   sequence.                                                                 */
+            __IM uint32_t E4 : 1;      /*!< [4..4] Set to 1 when read data is not received even after Ncycle
+                                        *   has elapsed after the command has been read.                              */
+            __IM uint32_t E5 : 1;      /*!< [5..5] E5                                                                 */
+            __IM uint32_t E6 : 1;      /*!< [6..6] E6                                                                 */
+            uint32_t         : 25;
+        } SD_ERR_STS2_b;
+    };
+    __IM uint32_t  RESERVED21;
+    __IOM uint32_t SD_BUF0H;           /*!< (@ 0x000000C0) SD Buffer Read/Write H Register                            */
+    __IOM uint32_t SD_BUF0L;           /*!< (@ 0x000000C4) SD Buffer Read/Write L Register                            */
+    __IM uint32_t  RESERVED22[2];
+
+    union
+    {
+        __IOM uint32_t SDIO_MODE;      /*!< (@ 0x000000D0) SDIO Mode Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t IOMOD  : 1; /*!< [0..0] SDIO Mode                                                          */
+            uint32_t              : 1;
+            __IOM uint32_t RWREQ  : 1; /*!< [2..2] Read Wait Request                                                  */
+            uint32_t              : 5;
+            __IOM uint32_t IOABT  : 1; /*!< [8..8] SDIO Abort                                                         */
+            __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None Abort                                                    */
+            uint32_t              : 22;
+        } SDIO_MODE_b;
+    };
+    __IM uint32_t RESERVED23;
+
+    union
+    {
+        __IOM uint32_t SDIO_INFO1;      /*!< (@ 0x000000D8) SDIO Interrupt Flag Register                               */
+
+        struct
+        {
+            __IOM uint32_t IOIRQ   : 1; /*!< [0..0] [Setting condition]                                                */
+            uint32_t               : 13;
+            __IOM uint32_t EXPUB52 : 1; /*!< [14..14] [Setting conditions]                                             */
+            __IOM uint32_t EXWT    : 1; /*!< [15..15] [Setting condition]                                              */
+            uint32_t               : 16;
+        } SDIO_INFO1_b;
+    };
+    __IM uint32_t RESERVED24;
+
+    union
+    {
+        __IOM uint32_t SDIO_INFO1_MASK;  /*!< (@ 0x000000E0) SDIO_INFO1 Interrupt Mask Register                         */
+
+        struct
+        {
+            __IOM uint32_t IOMSK    : 1; /*!< [0..0] IOMSK                                                              */
+            uint32_t                : 13;
+            __IOM uint32_t MEXPUB52 : 1; /*!< [14..14] MEXPUB52                                                         */
+            __IOM uint32_t MEXWT    : 1; /*!< [15..15] MEXWT                                                            */
+            uint32_t                : 16;
+        } SDIO_INFO1_MASK_b;
+    };
+    __IM uint32_t RESERVED25[159];
+
+    union
+    {
+        __IOM uint32_t CC_EXT_MODE;    /*!< (@ 0x00000360) DMA Mode Enable Register                                   */
+
+        struct
+        {
+            uint32_t               : 1;
+            __IOM uint32_t DMASDRW : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer                                     */
+            uint32_t               : 30;
+        } CC_EXT_MODE_b;
+    };
+    __IM uint32_t RESERVED26[7];
+
+    union
+    {
+        __IOM uint32_t SOFT_RST;       /*!< (@ 0x00000380) Software Reset Register                                    */
+
+        struct
+        {
+            __IOM uint32_t SDRST : 1;  /*!< [0..0] SDRST                                                              */
+            uint32_t             : 31;
+        } SOFT_RST_b;
+    };
+    __IM uint32_t RESERVED27;
+
+    union
+    {
+        __IM uint32_t VERSION;         /*!< (@ 0x00000388) Version Register                                           */
+
+        struct
+        {
+            __IM uint32_t IP7IP0 : 8;  /*!< [7..0] IP7IP0                                                             */
+            __IM uint32_t UR3UR0 : 4;  /*!< [11..8] UR3UR0                                                            */
+            uint32_t             : 20;
+        } VERSION_b;
+    };
+    __IM uint32_t RESERVED28;
+
+    union
+    {
+        __IOM uint32_t HOST_MODE;        /*!< (@ 0x00000390) Host Interface Mode Setting Register                       */
+
+        struct
+        {
+            __IOM uint32_t WMODE    : 1; /*!< [0..0] Width for Access to SD_BUF                                         */
+            __IOM uint32_t ENDIAN   : 1; /*!< [1..1] ENDIAN                                                             */
+            uint32_t                : 6;
+            __IOM uint32_t BUSWIDTH : 1; /*!< [8..8] Width for Access to SD_BUF                                         */
+            uint32_t                : 23;
+        } HOST_MODE_b;
+    };
+    __IM uint32_t RESERVED29;
+
+    union
+    {
+        __IOM uint32_t SDIF_MODE;       /*!< (@ 0x00000398) SD Interface Mode Setting Register                         */
+
+        struct
+        {
+            __IOM uint32_t DDR     : 1; /*!< [0..0] DDR Mode Select                                                    */
+            uint32_t               : 7;
+            __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (test command for MMC supported)                    */
+            uint32_t               : 23;
+        } SDIF_MODE_b;
+    };
+    __IM uint32_t RESERVED30[11];
+
+    union
+    {
+        __IOM uint32_t SD_STATUS;       /*!< (@ 0x000003C8) SD Status Register                                         */
+
+        struct
+        {
+            __IOM uint32_t SD_PWEN : 1; /*!< [0..0] SD_PWEN                                                            */
+            __IOM uint32_t SD_RST  : 1; /*!< [1..1] SD_RST                                                             */
+            uint32_t               : 14;
+            __IOM uint32_t SD_IOVS : 1; /*!< [16..16] SD_IOVS                                                          */
+            uint32_t               : 15;
+        } SD_STATUS_b;
+    };
+    __IM uint32_t RESERVED31[277];
+
+    union
+    {
+        __IOM uint32_t DM_CM_DTRAN_MODE; /*!< (@ 0x00000820) DMAC Transfer Mode Register                                */
+
+        struct
+        {
+            uint32_t                 : 4;
+            __IOM uint32_t BUS_WIDTH : 2; /*!< [5..4] BUS_WIDTH                                                          */
+            uint32_t                 : 10;
+            __IOM uint32_t CH_NUM    : 2; /*!< [17..16] CH_NUM                                                           */
+            uint32_t                 : 14;
+        } DM_CM_DTRAN_MODE_b;
+    };
+    __IM uint32_t RESERVED32;
+
+    union
+    {
+        __IOM uint32_t DM_CM_DTRAN_CTRL; /*!< (@ 0x00000828) DMAC Transfer Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t DM_START : 1; /*!< [0..0] DMAC Start                                                         */
+            uint32_t                : 31;
+        } DM_CM_DTRAN_CTRL_b;
+    };
+    __IM uint32_t RESERVED33;
+
+    union
+    {
+        __IOM uint32_t DM_CM_RST;      /*!< (@ 0x00000830) DMAC Reset Register                                        */
+
+        struct
+        {
+            uint32_t                 : 8;
+            __IOM uint32_t DTRANRST0 : 1; /*!< [8..8] DTRANRST0                                                          */
+            __IOM uint32_t DTRANRST1 : 1; /*!< [9..9] DTRANRST1                                                          */
+            uint32_t                 : 22;
+        } DM_CM_RST_b;
+    };
+    __IM uint32_t RESERVED34[3];
+
+    union
+    {
+        __IOM uint32_t DM_CM_INFO1;    /*!< (@ 0x00000840) DMAC Interrupt Register 1                                  */
+
+        struct
+        {
+            uint32_t                 : 16;
+            __IOM uint32_t DTRANEND0 : 1; /*!< [16..16] DMAC Channel 0 Transfer End                                      */
+            uint32_t                 : 3;
+            __IOM uint32_t DTRANEND1 : 1; /*!< [20..20] DMAC Channel 1 Transfer End                                      */
+            uint32_t                 : 11;
+        } DM_CM_INFO1_b;
+    };
+    __IM uint32_t RESERVED35;
+
+    union
+    {
+        __IOM uint32_t DM_CM_INFO1_MASK; /*!< (@ 0x00000848) DM_CM_INFO1 Interrupt Mask Register                        */
+
+        struct
+        {
+            uint32_t                      : 16;
+            __IOM uint32_t DTRANEND0_MASK : 1; /*!< [16..16] DTRANEND0_MASK                                                   */
+            uint32_t                      : 3;
+            __IOM uint32_t DTRANEND1_MASK : 1; /*!< [20..20] DTRANEND1_MASK                                                   */
+            uint32_t                      : 11;
+        } DM_CM_INFO1_MASK_b;
+    };
+    __IM uint32_t RESERVED36;
+
+    union
+    {
+        __IOM uint32_t DM_CM_INFO2;    /*!< (@ 0x00000850) DMAC Interrupt Register 2                                  */
+
+        struct
+        {
+            uint32_t                 : 16;
+            __IOM uint32_t DTRANERR0 : 1; /*!< [16..16] DMAC Channel 0 Error                                             */
+            __IOM uint32_t DTRANERR1 : 1; /*!< [17..17] DMAC Channel 1 Error                                             */
+            uint32_t                 : 14;
+        } DM_CM_INFO2_b;
+    };
+    __IM uint32_t RESERVED37;
+
+    union
+    {
+        __IOM uint32_t DM_CM_INFO2_MASK; /*!< (@ 0x00000858) DM_CM_INFO2 Interrupt Mask Register                        */
+
+        struct
+        {
+            uint32_t                      : 16;
+            __IOM uint32_t DTRANERR0_MASK : 1; /*!< [16..16] DTRANERR0_MASK                                                   */
+            __IOM uint32_t DTRANERR1_MASK : 1; /*!< [17..17] DTRANERR1_MASK                                                   */
+            uint32_t                      : 14;
+        } DM_CM_INFO2_MASK_b;
+    };
+    __IM uint32_t RESERVED38[9];
+
+    union
+    {
+        __IOM uint32_t DM_DTRAN_ADDR;  /*!< (@ 0x00000880) DMAC Transfer Address Register                             */
+
+        struct
+        {
+            uint32_t             : 3;
+            __IOM uint32_t DADDR : 29; /*!< [31..3] Destination address/Source address (8 byte unit)                  */
+        } DM_DTRAN_ADDR_b;
+    };
+    __IM uint32_t RESERVED39[479];
+
+    union
+    {
+        __IOM uint32_t SCC_DTCNTL;             /*!< (@ 0x00001000) Initial Setting Register                                   */
+
+        struct
+        {
+            __IOM uint32_t TAPEN          : 1; /*!< [0..0] TAPEN                                                              */
+            uint32_t                      : 15;
+            __IOM uint32_t TAPNUM7TAPNUM0 : 8; /*!< [23..16] TAPNUM7TAPNUM0                                                   */
+            uint32_t                      : 8;
+        } SCC_DTCNTL_b;
+    };
+    __IM uint32_t RESERVED40;
+
+    union
+    {
+        __IOM uint32_t SCC_TAPSET;             /*!< (@ 0x00001008) Sampling Clock Position Setting Register                   */
+
+        struct
+        {
+            __IOM uint32_t TAPSET7TAPSET0 : 8; /*!< [7..0] SCC Sampling Clock Position                                        */
+            uint32_t                      : 24;
+        } SCC_TAPSET_b;
+    };
+    __IM uint32_t RESERVED41;
+
+    union
+    {
+        __IOM uint32_t SCC_DT2FF;      /*!< (@ 0x00001010) Hardware Adjustment Register 1                             */
+
+        struct
+        {
+            __IOM uint32_t DT2NS : 8;  /*!< [7..0] Hardware Adjustment 1                                              */
+            __IOM uint32_t DT2NE : 8;  /*!< [15..8] Hardware Adjustment 2                                             */
+            uint32_t             : 16;
+        } SCC_DT2FF_b;
+    };
+    __IM uint32_t RESERVED42;
+
+    union
+    {
+        __IOM uint32_t SCC_CKSEL;      /*!< (@ 0x00001018) Sampling Clock Selection Register                          */
+
+        struct
+        {
+            __IOM uint32_t DTSEL : 1;  /*!< [0..0] Sampling Clock Selection                                           */
+            uint32_t             : 31;
+        } SCC_CKSEL_b;
+    };
+    __IM uint32_t RESERVED43;
+
+    union
+    {
+        __IOM uint32_t SCC_RVSCNTL;    /*!< (@ 0x00001020) Sampling Clock Position Correction Register                */
+
+        struct
+        {
+            __IOM uint32_t RVSEN : 1;  /*!< [0..0] SCC Sampling Clock Position Correction Enable                      */
+            uint32_t             : 7;
+            __IM uint32_t TAPSEL : 8;  /*!< [15..8] SCC Sampling Clock Position Display                               */
+            uint32_t             : 16;
+        } SCC_RVSCNTL_b;
+    };
+    __IM uint32_t RESERVED44;
+
+    union
+    {
+        __IOM uint32_t SCC_RVSREQ;        /*!< (@ 0x00001028) Sampling Clock Position Correction Request Register        */
+
+        struct
+        {
+            __IOM uint32_t REQTAPDWN : 1; /*!< [0..0] SCC Sampling Clock Position Negative Direction Correction
+                                           *   Request                                                                   */
+            __IOM uint32_t REQTAPUP : 1;  /*!< [1..1] SCC Sampling Clock Position Positive Direction Correction
+                                           *   Request                                                                   */
+            __IOM uint32_t RVSERR : 1;    /*!< [2..2] SCC Sampling Clock Position Correction Error                       */
+            uint32_t              : 29;
+        } SCC_RVSREQ_b;
+    };
+    __IM uint32_t RESERVED45;
+
+    union
+    {
+        __IOM uint32_t SCC_SMPCMP;     /*!< (@ 0x00001030) Sampling Data Comparison Register                          */
+
+        struct
+        {
+            __IOM uint32_t CMPNGD : 9; /*!< [8..0] Comparison of sampling data with the after TAP Clock               */
+            uint32_t              : 7;
+            __IOM uint32_t CMPNGU : 9; /*!< [24..16] Comparison of sampling data with the previous TAP Clock          */
+            uint32_t              : 7;
+        } SCC_SMPCMP_b;
+    };
+    __IM uint32_t RESERVED46;
+
+    union
+    {
+        __IOM uint32_t SCC_TMPPORT;     /*!< (@ 0x00001038) Hardware Adjustment Register 2                             */
+
+        struct
+        {
+            __IOM uint32_t TMPOUT : 16; /*!< [15..0] Hardware adjustment 3                                             */
+            uint32_t              : 16;
+        } SCC_TMPPORT_b;
+    };
+} R_SDHI0_Type;                         /*!< Size = 4156 (0x103c)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_LCDC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief LCD Controller (R_LCDC)
+ */
+
+typedef struct                         /*!< (@ 0x920C0000) R_LCDC Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t DU_MCR0;        /*!< (@ 0x00000000) DU Module Control Register 0                               */
+
+        struct
+        {
+            __IOM uint32_t DPI_OE : 1; /*!< [0..0] Display parallel interface output enable                           */
+            uint32_t              : 7;
+            __IOM uint32_t DI_EN  : 1; /*!< [8..8] DI_EN                                                              */
+            uint32_t              : 7;
+            __IOM uint32_t PB_CLR : 1; /*!< [16..16] Clear PBUF pointers                                              */
+            uint32_t              : 15;
+        } DU_MCR0_b;
+    };
+
+    union
+    {
+        __IM uint32_t DU_MSR0;         /*!< (@ 0x00000004) DU Module Status Register 0                                */
+
+        struct
+        {
+            uint32_t                   : 8;
+            __IM uint32_t ST_DI_BSY    : 1; /*!< [8..8] ST_DI_BSY                                                          */
+            uint32_t                   : 7;
+            __IM uint32_t ST_PB_WFULL  : 1; /*!< [16..16] ST_PB_WFULL                                                      */
+            uint32_t                   : 1;
+            __IM uint32_t ST_PB_WINIT  : 1; /*!< [18..18] ST_PB_WINIT                                                      */
+            uint32_t                   : 1;
+            __IM uint32_t ST_PB_REMPTY : 1; /*!< [20..20] ST_PB_REMPTY                                                     */
+            __IM uint32_t ST_PB_RUF    : 1; /*!< [21..21] ST_PB_RUF                                                        */
+            __IM uint32_t ST_PB_RINIT  : 1; /*!< [22..22] ST_PB_RINIT                                                      */
+            uint32_t                   : 9;
+        } DU_MSR0_b;
+    };
+
+    union
+    {
+        __IM uint32_t DU_MSR1;          /*!< (@ 0x00000008) DU Module Status Register 1                                */
+
+        struct
+        {
+            __IM uint32_t UF_HACT : 13; /*!< [12..0] Hactive counter when the PBUF underflow occurs                    */
+            uint32_t              : 3;
+            __IM uint32_t UF_VACT : 13; /*!< [28..16] Vactive counter when the PBUF underflow occurs                   */
+            uint32_t              : 3;
+        } DU_MSR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DU_IMR0;           /*!< (@ 0x0000000C) DU Interrupt Mask Register 0                               */
+
+        struct
+        {
+            __IOM uint32_t IM_PB_RUF : 1; /*!< [0..0] IM_PB_RUF                                                          */
+            uint32_t                 : 31;
+        } DU_IMR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DU_DITR0;          /*!< (@ 0x00000010) DU Display I/F Timing Register 0                           */
+
+        struct
+        {
+            __IOM uint32_t DPI_CLKMD : 1; /*!< [0..0] DPI_CLKMD                                                          */
+            uint32_t                 : 7;
+            __IOM uint32_t DEMD      : 2; /*!< [9..8] DEMD                                                               */
+            uint32_t                 : 6;
+            __IOM uint32_t VSPOL     : 1; /*!< [16..16] vsync polarity                                                   */
+            __IOM uint32_t HSPOL     : 1; /*!< [17..17] hsync polarity                                                   */
+            uint32_t                 : 14;
+        } DU_DITR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DU_DITR1;         /*!< (@ 0x00000014) DU Display I/F Timing Register 1                           */
+
+        struct
+        {
+            __IOM uint32_t VSA     : 12; /*!< [11..0] The number of lines in the Vsync period                           */
+            uint32_t               : 4;
+            __IOM uint32_t VACTIVE : 13; /*!< [28..16] The number of lines in the Vactive period                        */
+            uint32_t               : 3;
+        } DU_DITR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DU_DITR2;       /*!< (@ 0x00000018) DU Display I/F Timing Register 2                           */
+
+        struct
+        {
+            __IOM uint32_t VBP : 13;   /*!< [12..0] The number of lines in the Vback period                           */
+            uint32_t           : 3;
+            __IOM uint32_t VFP : 13;   /*!< [28..16] The number of lines in the Vfront period                         */
+            uint32_t           : 3;
+        } DU_DITR2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DU_DITR3;         /*!< (@ 0x0000001C) DU Display I/F Timing Register 3                           */
+
+        struct
+        {
+            __IOM uint32_t HSA     : 12; /*!< [11..0] The number of cycles in the Hsync period                          */
+            uint32_t               : 4;
+            __IOM uint32_t HACTIVE : 13; /*!< [28..16] The number of cycles (pixels) in the Hactive period              */
+            uint32_t               : 3;
+        } DU_DITR3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DU_DITR4;       /*!< (@ 0x00000020) DU Display I/F Timing Register 4                           */
+
+        struct
+        {
+            __IOM uint32_t HBP : 13;   /*!< [12..0] The number of cycles in the Hback period                          */
+            uint32_t           : 3;
+            __IOM uint32_t HFP : 13;   /*!< [28..16] The number of cycles in the Hfront period                        */
+            uint32_t           : 3;
+        } DU_DITR4_b;
+    };
+    __IM uint32_t RESERVED[7];
+
+    union
+    {
+        __IOM uint32_t DU_MCR1;            /*!< (@ 0x00000040) DU Module Control Register 1                               */
+
+        struct
+        {
+            __IOM uint32_t OPMD       : 2; /*!< [1..0] Operation mode                                                     */
+            uint32_t                  : 14;
+            __IOM uint32_t PB_AUTOCLR : 1; /*!< [16..16] PBUF pointers auto clear enable                                  */
+            uint32_t                  : 15;
+        } DU_MCR1_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t DU_PBCR0;       /*!< (@ 0x0000004C) DU PBUF Control Register 0                                 */
+
+        struct
+        {
+            __IOM uint32_t PB_DEP : 5; /*!< [4..0] Valid PBUF depth                                                   */
+            uint32_t              : 27;
+        } DU_PBCR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DU_PBCR1;         /*!< (@ 0x00000050) DU PBUF Control Register 1                                 */
+
+        struct
+        {
+            __IOM uint32_t PB_RUFOP : 1; /*!< [0..0] PB_RUFOP                                                           */
+            uint32_t                : 31;
+        } DU_PBCR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DU_PBCR2;           /*!< (@ 0x00000054) DU PBUF Control Register 2                                 */
+
+        struct
+        {
+            __IOM uint32_t PB_RUFDAT : 24; /*!< [23..0] PB_RUFDAT                                                         */
+            uint32_t                 : 8;
+        } DU_PBCR2_b;
+    };
+    __IM uint32_t RESERVED2[16362];
+
+    union
+    {
+        __IM uint32_t FCP_VCR;          /*!< (@ 0x00010000) FCPVD Version Control Register                             */
+
+        struct
+        {
+            __IM uint32_t REVISION : 8; /*!< [7..0] REVISION                                                           */
+            __IM uint32_t CATEGORY : 8; /*!< [15..8] CATEGORY                                                          */
+            uint32_t               : 16;
+        } FCP_VCR_b;
+    };
+    __IM uint32_t RESERVED3[16383];
+
+    union
+    {
+        __IOM uint32_t VI6_CMD0;       /*!< (@ 0x00020000) VSPD Start Register 0                                      */
+
+        struct
+        {
+            __IOM uint32_t STRCMD : 1; /*!< [0..0] Start reservation of WPF                                           */
+            uint32_t              : 3;
+            __IOM uint32_t UPDHDR : 1; /*!< [4..4] Reserved state of updating Display List Header (DLH)
+                                        *   address                                                                   */
+            uint32_t : 27;
+        } VI6_CMD0_b;
+    };
+    __IM uint32_t RESERVED4[3];
+
+    union
+    {
+        __IOM uint32_t VI6_CLK_CTRL0;  /*!< (@ 0x00020010) Clock Control Register 0                                   */
+
+        struct
+        {
+            __IOM uint32_t GCS3 : 5;   /*!< [4..0] GCS3                                                               */
+            uint32_t            : 3;
+            __IOM uint32_t GCS2 : 4;   /*!< [11..8] GCS2                                                              */
+            uint32_t            : 4;
+            __IOM uint32_t GCS1 : 1;   /*!< [16..16] GCS1                                                             */
+            uint32_t            : 11;
+            __IOM uint32_t GCS0 : 1;   /*!< [28..28] GCS0                                                             */
+            uint32_t            : 3;
+        } VI6_CLK_CTRL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_CLK_CTRL1;  /*!< (@ 0x00020014) Clock Control Register 1                                   */
+
+        struct
+        {
+            __IOM uint32_t GCS5 : 16;  /*!< [15..0] GCS5                                                              */
+            uint32_t            : 4;
+            __IOM uint32_t GCS6 : 1;   /*!< [20..20] GCS6                                                             */
+            uint32_t            : 3;
+            __IOM uint32_t GCS4 : 8;   /*!< [31..24] GCS4                                                             */
+        } VI6_CLK_CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_CLK_DCSWT;  /*!< (@ 0x00020018) Dynamic Clock Stop Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t CSTRW : 8;  /*!< [7..0] Dynamic Clock Stop Control 2                                       */
+            __IOM uint32_t CSTPW : 8;  /*!< [15..8] Dynamic Clock Stop Control 1                                      */
+            __IOM uint32_t DCC2  : 1;  /*!< [16..16] DCC2                                                             */
+            __IOM uint32_t DCC1  : 1;  /*!< [17..17] DCC1                                                             */
+            uint32_t             : 2;
+            __IOM uint32_t DCC0  : 2;  /*!< [21..20] DCC0                                                             */
+            uint32_t             : 10;
+        } VI6_CLK_DCSWT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_CLK_DCSM0;  /*!< (@ 0x0002001C) Dynamic Clock Stop Disable Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t DCD2 : 5;   /*!< [4..0] DCD2                                                               */
+            uint32_t            : 3;
+            __IOM uint32_t DCD1 : 4;   /*!< [11..8] DCD1                                                              */
+            uint32_t            : 4;
+            __IOM uint32_t DCD0 : 13;  /*!< [28..16] DCD0                                                             */
+            uint32_t            : 3;
+        } VI6_CLK_DCSM0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_CLK_DCSM1;  /*!< (@ 0x00020020) Dynamic Clock Stop Disable Register 1                      */
+
+        struct
+        {
+            __IOM uint32_t DCD4 : 16;  /*!< [15..0] DCD4                                                              */
+            uint32_t            : 4;
+            __IOM uint32_t DCD5 : 1;   /*!< [20..20] DCD5                                                             */
+            uint32_t            : 3;
+            __IOM uint32_t DCD3 : 8;   /*!< [31..24] DCD3                                                             */
+        } VI6_CLK_DCSM1_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint32_t VI6_SRESET;     /*!< (@ 0x00020028) Software Reset Register                                    */
+
+        struct
+        {
+            __IOM uint32_t SRST0 : 1;  /*!< [0..0] WPF0 Software Reset                                                */
+            uint32_t             : 31;
+        } VI6_SRESET_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_MRESET_ENB0; /*!< (@ 0x0002002C) Module Reset Enable Register 0                             */
+
+        struct
+        {
+            __IOM uint32_t MRSTE2 : 5;  /*!< [4..0] MRSTE2                                                             */
+            uint32_t              : 3;
+            __IOM uint32_t MRSTE1 : 4;  /*!< [11..8] MRSTE1                                                            */
+            uint32_t              : 16;
+            __IOM uint32_t MRSTE0 : 2;  /*!< [29..28] MRSTE0                                                           */
+            uint32_t              : 2;
+        } VI6_MRESET_ENB0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_MRESET_ENB1; /*!< (@ 0x00020030) Module Reset Enable Register 1                             */
+
+        struct
+        {
+            __IOM uint32_t MRSTE4 : 16; /*!< [15..0] MRSTE4                                                            */
+            uint32_t              : 8;
+            __IOM uint32_t MRSTE3 : 8;  /*!< [31..24] MRSTE3                                                           */
+        } VI6_MRESET_ENB1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_MRESET;     /*!< (@ 0x00020034) Module Reset Issuing Register                              */
+
+        struct
+        {
+            __IOM uint32_t MRST : 1;   /*!< [0..0] MRST                                                               */
+            uint32_t            : 31;
+        } VI6_MRESET_b;
+    };
+
+    union
+    {
+        __IM uint32_t VI6_STATUS;      /*!< (@ 0x00020038) Operating Status Register                                  */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IM uint32_t SYS0_ACT : 1; /*!< [8..8] WPF0 Operating Status                                              */
+            uint32_t               : 19;
+            __IM uint32_t FLDST0   : 1; /*!< [28..28] Field status of previous frame of WPF0                           */
+            uint32_t               : 3;
+        } VI6_STATUS_b;
+    };
+    __IM uint32_t RESERVED6[3];
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_IRQ_ENB; /*!< (@ 0x00020048) WPF0 Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint32_t FREE : 1;     /*!< [0..0] FREE                                                               */
+            __IOM uint32_t DFEE : 1;     /*!< [1..1] DFEE                                                               */
+            uint32_t            : 14;
+            __IOM uint32_t UNDE : 1;     /*!< [16..16] UNDE                                                             */
+            uint32_t            : 15;
+        } VI6_WPF0_IRQ_ENB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_IRQ_STA; /*!< (@ 0x0002004C) WPF0 Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint32_t FRE : 1;      /*!< [0..0] Interrupt Status and Clear for WPF0 Frame End                      */
+            __IOM uint32_t DFE : 1;      /*!< [1..1] Interrupt Status and Clear for WPF0 Display List Frame
+                                          *   End                                                                       */
+            uint32_t           : 14;
+            __IOM uint32_t UND : 1;      /*!< [16..16] Interrupt Status and Clear for WPF0 Underrun in case
+                                          *   of DU connection                                                          */
+            uint32_t : 15;
+        } VI6_WPF0_IRQ_STA_b;
+    };
+    __IM uint32_t RESERVED7[10];
+
+    union
+    {
+        __IOM uint32_t VI6_DISP0_IRQ_ENB; /*!< (@ 0x00020078) Display-0 Interrupt Enable Register                        */
+
+        struct
+        {
+            uint32_t            : 5;
+            __IOM uint32_t MAEE : 1;   /*!< [5..5] MAEE                                                               */
+            uint32_t            : 2;
+            __IOM uint32_t DSTE : 1;   /*!< [8..8] DSTE                                                               */
+            uint32_t            : 23;
+        } VI6_DISP0_IRQ_ENB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_DISP0_IRQ_STA; /*!< (@ 0x0002007C) Display-0 Interrupt Status Register                        */
+
+        struct
+        {
+            uint32_t           : 5;
+            __IOM uint32_t MAE : 1;    /*!< [5..5] Interrupt Status and Clear for Display Read Data End               */
+            uint32_t           : 2;
+            __IOM uint32_t DST : 1;    /*!< [8..8] Interrupt Status and Clear for Display Start                       */
+            uint32_t           : 23;
+        } VI6_DISP0_IRQ_STA_b;
+    };
+    __IM uint32_t RESERVED8[32];
+
+    union
+    {
+        __IOM uint32_t VI6_DL_CTRL;      /*!< (@ 0x00020100) Display List Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t DLE0 : 1;     /*!< [0..0] Display List Enable/Disable for WPF0                               */
+            __IOM uint32_t NH0  : 1;     /*!< [1..1] Header-less Display List Mode                                      */
+            __IOM uint32_t CFM0 : 1;     /*!< [2..2] Continuous Frame Mode for Header-less Display List for
+                                          *   WPF0                                                                      */
+            __IOM uint32_t RLM0    : 1;  /*!< [3..3] Loading two plane Registers Mode for WPF0                          */
+            __IOM uint32_t DLE1    : 1;  /*!< [4..4] This bit does not affect anything VSPD. (NOP)                      */
+            uint32_t               : 3;
+            __IOM uint32_t DC1     : 1;  /*!< [8..8] DC1                                                                */
+            uint32_t               : 3;
+            __IOM uint32_t DC2     : 1;  /*!< [12..12] DC2                                                              */
+            uint32_t               : 3;
+            __IOM uint32_t AR_WAIT : 16; /*!< [31..16] Display List Control Setting                                     */
+        } VI6_DL_CTRL_b;
+    };
+    __IOM uint32_t VI6_DL_HDR_ADDR0;     /*!< (@ 0x00020104) Display List-0 Header Address Register                     */
+    __IM uint32_t  RESERVED9[3];
+
+    union
+    {
+        __IOM uint32_t VI6_DL_SWAP0;   /*!< (@ 0x00020114) Display List-0 Data Swapping Register                      */
+
+        struct
+        {
+            __IOM uint32_t BTS : 1;    /*!< [0..0] Display List Data Swapping in Byte Units                           */
+            __IOM uint32_t WDS : 1;    /*!< [1..1] Display List Data Swapping in Word Units                           */
+            __IOM uint32_t LWS : 1;    /*!< [2..2] Display List Data Swapping in long word Units                      */
+            uint32_t           : 28;
+            __IOM uint32_t IND : 1;    /*!< [31..31] Enabling independent swap setting per WPF                        */
+        } VI6_DL_SWAP0_b;
+    };
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IOM uint32_t VI6_DL_EXT_CTRL0; /*!< (@ 0x0002011C) Extended Display List-0 Control Register                   */
+
+        struct
+        {
+            __IOM uint32_t EXT    : 1;   /*!< [0..0] Extended Display List for WPF0                                     */
+            uint32_t              : 3;
+            __IOM uint32_t EXPRI  : 1;   /*!< [4..4] Display List Control 1                                             */
+            __IOM uint32_t DLPRI  : 1;   /*!< [5..5] Display List Control 0                                             */
+            uint32_t              : 2;
+            __IOM uint32_t POLINT : 6;   /*!< [13..8] Extended Display List Command Control                             */
+            uint32_t              : 2;
+            __IOM uint32_t NWE    : 1;   /*!< [16..16] No Wait for Polling                                              */
+            uint32_t              : 15;
+        } VI6_DL_EXT_CTRL0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_DL_BODY_SIZE0; /*!< (@ 0x00020120) Display List Body Size Register 0                          */
+
+        struct
+        {
+            __IOM uint32_t BS0  : 17;     /*!< [16..0] Header-less Display List Body Size (WPF0)                         */
+            uint32_t            : 7;
+            __IOM uint32_t UPD0 : 1;      /*!< [24..24] Update Flag                                                      */
+            uint32_t            : 7;
+        } VI6_DL_BODY_SIZE0_b;
+    };
+    __IM uint32_t RESERVED11[3];
+    __IM uint32_t VI6_DL_HDR_REF_ADDR0; /*!< (@ 0x00020130) Display List-0 Header Reference Address Register           */
+    __IM uint32_t RESERVED12[115];
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_SRC_BSIZE; /*!< (@ 0x00020300) RPFn Basic Read Size Register                              */
+
+        struct
+        {
+            __IOM uint32_t BVSIZE : 13;    /*!< [12..0] Vertical Size of RPF Basic Read Area                              */
+            uint32_t              : 3;
+            __IOM uint32_t BHSIZE : 13;    /*!< [28..16] Horizontal Size of RPF Basic Read Area                           */
+            uint32_t              : 3;
+        } VI6_RPF0_SRC_BSIZE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_SRC_ESIZE; /*!< (@ 0x00020304) RPFn Extended Read Size Register                           */
+
+        struct
+        {
+            __IOM uint32_t EVSIZE : 13;    /*!< [12..0] RPF Extended Vertical Read Size                                   */
+            uint32_t              : 3;
+            __IOM uint32_t EHSIZE : 13;    /*!< [28..16] RPF Extended Horizontal Read Size                                */
+            uint32_t              : 3;
+        } VI6_RPF0_SRC_ESIZE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_INFMT; /*!< (@ 0x00020308) RPFn Input Format Register                                 */
+
+        struct
+        {
+            __IOM uint32_t RDFMT : 7;  /*!< [6..0] RPF Input Image Format Setting                                     */
+            uint32_t             : 1;
+            __IOM uint32_t CSC   : 1;  /*!< [8..8] Color Space Conversion Enable                                      */
+            __IOM uint32_t RDTM  : 3;  /*!< [11..9] CSC Conversion Expression Setting                                 */
+            __IOM uint32_t CEXT  : 2;  /*!< [13..12] Lower-Bit Color Data Extension Method Setting                    */
+            __IOM uint32_t SPUVS : 1;  /*!< [14..14] RPF Input Mode Setting 2                                         */
+            __IOM uint32_t SPYCS : 1;  /*!< [15..15] RPF Input Mode Setting 1                                         */
+            __IOM uint32_t CIPM  : 1;  /*!< [16..16] Horizontal Chrominance Interpolation Method Setting              */
+            uint32_t             : 11;
+            __IOM uint32_t VIR   : 1;  /*!< [28..28] Virtual Input Enable                                             */
+            uint32_t             : 3;
+        } VI6_RPF0_INFMT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_DSWAP; /*!< (@ 0x0002030C) RPFn Data Swapping Register                                */
+
+        struct
+        {
+            __IOM uint32_t P_BTS : 1;  /*!< [0..0] Picture Plane Data Swapping in Byte Units                          */
+            __IOM uint32_t P_WDS : 1;  /*!< [1..1] Picture Plane Data Swapping in Word Units                          */
+            __IOM uint32_t P_LWS : 1;  /*!< [2..2] Picture Plane Data Swapping in long word Units                     */
+            __IOM uint32_t P_LLS : 1;  /*!< [3..3] Picture Plane Data Swapping in LONG LWORD Units                    */
+            uint32_t             : 4;
+            __IOM uint32_t A_BTS : 1;  /*!< [8..8] alpha Plane Data Swapping in Byte Units                               */
+            __IOM uint32_t A_WDS : 1;  /*!< [9..9] alpha Plane Data Swapping in Word Units                               */
+            __IOM uint32_t A_LWS : 1;  /*!< [10..10] alpha Plane Data Swapping in long word Units                        */
+            __IOM uint32_t A_LLS : 1;  /*!< [11..11] alpha Plane Data Swapping in LONG LWORD Units                       */
+            uint32_t             : 20;
+        } VI6_RPF0_DSWAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_LOC;    /*!< (@ 0x00020310) RPFn Display Location Register                             */
+
+        struct
+        {
+            __IOM uint32_t VCOORD : 13; /*!< [12..0] Vertical Coordinate of Sublayer Display Location on
+                                         *   Master Layer                                                              */
+            uint32_t              : 3;
+            __IOM uint32_t HCOORD : 13; /*!< [28..16] Horizontal Coordinate of Sublayer Display Location
+                                         *   on Master Layer                                                           */
+            uint32_t : 3;
+        } VI6_RPF0_LOC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_ALPH_SEL; /*!< (@ 0x00020314) RPFn alpha Plane Selection Control Register                   */
+
+        struct
+        {
+            __IOM uint32_t ALPHA0 : 8;    /*!< [7..0] 8-Bit alpha Value Output when 1-Bit alpha Value is 0                     */
+            __IOM uint32_t ALPHA1 : 8;    /*!< [15..8] 8-Bit alpha Value Output when 1-Bit alpha Value is 1                    */
+            uint32_t              : 2;
+            __IOM uint32_t AEXT   : 2;    /*!< [19..18] Lower-Bit alpha Value Extension Method Set                          */
+            uint32_t              : 3;
+            __IOM uint32_t BSEL   : 1;    /*!< [23..23] alpha Bit Count Conversion Selection for 1-Bit Mask Generator       */
+            __IOM uint32_t IROP   : 4;    /*!< [27..24] IROP Operation Setting                                           */
+            __IOM uint32_t ASEL   : 3;    /*!< [30..28] alpha Format and Processing Method Select                           */
+            uint32_t              : 1;
+        } VI6_RPF0_ALPH_SEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_VRTCOL_SET; /*!< (@ 0x00020318) RPFn Virtual Plane Color Information Register              */
+
+        struct
+        {
+            __IOM uint32_t LAYB : 8;        /*!< [7..0] Virtual-Input Fixed B/Cb Component Value                           */
+            __IOM uint32_t LAYG : 8;        /*!< [15..8] Virtual-Input Fixed G/Y Component Value                           */
+            __IOM uint32_t LAYR : 8;        /*!< [23..16] Virtual-Input Fixed R/Cr Component Value                         */
+            __IOM uint32_t LAYA : 8;        /*!< [31..24] Virtual-Input Fixed alpha Value                                     */
+        } VI6_RPF0_VRTCOL_SET_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_MSKCTRL; /*!< (@ 0x0002031C) RPFn Mask Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t MGB    : 8;   /*!< [7..0] B/Cb Comparison Value for 1-Bit alpha Generation                      */
+            __IOM uint32_t MGG    : 8;   /*!< [15..8] G/Y Comparison Value for 1-Bit alpha Generation                      */
+            __IOM uint32_t MGR    : 8;   /*!< [23..16] R/Cr Comparison Value for 1-Bit alpha Generation                    */
+            __IOM uint32_t MSK_EN : 1;   /*!< [24..24] Mask Generation Specification                                    */
+            uint32_t              : 7;
+        } VI6_RPF0_MSKCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_MSKSET0; /*!< (@ 0x00020320) RPFn IROP-SRC Input Value Register 0                       */
+
+        struct
+        {
+            __IOM uint32_t MSB0 : 8;     /*!< [7..0] IROP-Source Input B/Cb Value when 1-Bit alpha is 0                    */
+            __IOM uint32_t MSG0 : 8;     /*!< [15..8] IROP-Source Input G/Y Value when 1-Bit alpha is 0                    */
+            __IOM uint32_t MSR0 : 8;     /*!< [23..16] IROP-Source Input R/Cr Value when 1-Bit alpha is 0                  */
+            __IOM uint32_t MSA0 : 8;     /*!< [31..24] IROP-Source Input alpha Value when 1-Bit alpha is 0                    */
+        } VI6_RPF0_MSKSET0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_MSKSET1; /*!< (@ 0x00020324) RPFn IROP-SRC Input Value Register 1                       */
+
+        struct
+        {
+            __IOM uint32_t MSB1 : 8;     /*!< [7..0] IROP-Source Input B/Cb Value when 1-Bit alpha is 1                    */
+            __IOM uint32_t MSG1 : 8;     /*!< [15..8] IROP-Source Input G/Y Value when 1-Bit alpha is 1                    */
+            __IOM uint32_t MSR1 : 8;     /*!< [23..16] IROP-Source Input R/Cr Value when 1-Bit alpha is 1                  */
+            __IOM uint32_t MSA1 : 8;     /*!< [31..24] IROP-Source Input alpha Value when 1-Bit alpha is 1                    */
+        } VI6_RPF0_MSKSET1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_CKEY_CTRL; /*!< (@ 0x00020328) RPFn Color Keying Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t SAPE0 : 1;      /*!< [0..0] Comparison Color Data Setting 0 Enable/Disable                     */
+            __IOM uint32_t SAPE1 : 1;      /*!< [1..1] Comparison Color Data Setting 1 Enable/Disable                     */
+            uint32_t             : 2;
+            __IOM uint32_t CV    : 1;      /*!< [4..4] Color Replacement Control                                          */
+            uint32_t             : 3;
+            __IOM uint32_t LTH   : 1;      /*!< [8..8] Transparent color-luma Threshold Mode Enable/Disable               */
+            uint32_t             : 23;
+        } VI6_RPF0_CKEY_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_CKEY_SET0; /*!< (@ 0x0002032C) RPFn Color Keying Color Setting Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t B0  : 8;        /*!< [7..0] B/Cb Component Data in Color Keying Color Information-0            */
+            __IOM uint32_t GY0 : 8;        /*!< [15..8] G/Y Component Data in Color Keying Color Information-0            */
+            __IOM uint32_t R0  : 8;        /*!< [23..16] R/Cr Component Data in Color Keying Color Information-0          */
+            __IOM uint32_t AP0 : 8;        /*!< [31..24] alpha Data in Color Keying Color Information-0                      */
+        } VI6_RPF0_CKEY_SET0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_CKEY_SET1; /*!< (@ 0x00020330) RPFn Color Keying Color Setting Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t B1  : 8;        /*!< [7..0] B/Cb Component Data in Color Keying Color Information-1            */
+            __IOM uint32_t GY1 : 8;        /*!< [15..8] G/Y Component Data in Color Keying Color Information-1            */
+            __IOM uint32_t R1  : 8;        /*!< [23..16] R/Cr Component Data in Color Keying Color Information-1          */
+            __IOM uint32_t AP1 : 8;        /*!< [31..24] alpha Data in Color Keying Color Information-1                      */
+        } VI6_RPF0_CKEY_SET1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_SRCM_PSTRIDE; /*!< (@ 0x00020334) RPFn Source Picture Memory Stride Setting Register         */
+
+        struct
+        {
+            __IOM uint32_t PICT_STRD_C : 16;  /*!< [15..0] Memory Stride of Source Picture C Plane                           */
+            __IOM uint32_t PICT_STRD_Y : 16;  /*!< [31..16] Memory Stride of Source Picture Y/RGB Plane                      */
+        } VI6_RPF0_SRCM_PSTRIDE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_SRCM_ASTRIDE; /*!< (@ 0x00020338) RPFn Source alpha Memory Stride Setting Register              */
+
+        struct
+        {
+            __IOM uint32_t ALPH_STRD : 16;    /*!< [15..0] Memory Stride of Source alpha Plane                                  */
+            uint32_t                 : 16;
+        } VI6_RPF0_SRCM_ASTRIDE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_SRCM_ADDR_Y; /*!< (@ 0x0002033C) RPFn Source Y/RGB Address Register                         */
+
+        struct
+        {
+            __IOM uint32_t SRCM_ADDR_Y : 32; /*!< [31..0] Source Image Y/RGB Plane Storing Address                          */
+        } VI6_RPF0_SRCM_ADDR_Y_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_SRCM_ADDR_C0; /*!< (@ 0x00020340) RPFn Source Chroma Address Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t SRCM_ADDR_C0 : 32; /*!< [31..0] Source Image C Plane Storing Address 0                            */
+        } VI6_RPF0_SRCM_ADDR_C0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_SRCM_ADDR_C1; /*!< (@ 0x00020344) RPFn Source Chroma Address Register 1                      */
+
+        struct
+        {
+            __IOM uint32_t SRCM_ADDR_C1 : 32; /*!< [31..0] Source Image C Plane Storing Address 1                            */
+        } VI6_RPF0_SRCM_ADDR_C1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_SRCM_ADDR_AI; /*!< (@ 0x00020348) RPFn Source alpha Address Register                            */
+
+        struct
+        {
+            __IOM uint32_t SRCM_ADDR_AI : 32; /*!< [31..0] Source Image alpha Plane Storing Address                             */
+        } VI6_RPF0_SRCM_ADDR_AI_b;
+    };
+    __IM uint32_t RESERVED13;
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_BAC;   /*!< (@ 0x00020350) RPFn Bus Access Control Register                           */
+
+        struct
+        {
+            uint32_t            : 16;
+            __IOM uint32_t B512 : 1;   /*!< [16..16] Burst access in 512 pixels' enable                               */
+            uint32_t            : 15;
+        } VI6_RPF0_BAC_b;
+    };
+    __IM uint32_t RESERVED14[6];
+
+    union
+    {
+        __IOM uint32_t VI6_RPF0_MULT_ALPH;  /*!< (@ 0x0002036C) RPFn Multiply Alpha Control Register                       */
+
+        struct
+        {
+            __IOM uint32_t ALPHA_RATIO : 8; /*!< [7..0] Multiply-alpha value                                               */
+            __IOM uint32_t P_MMD       : 2; /*!< [9..8] P_MMD[1:0]                                                         */
+            uint32_t                   : 2;
+            __IOM uint32_t A_MMD       : 1; /*!< [12..12] A_MMD                                                            */
+            uint32_t                   : 19;
+        } VI6_RPF0_MULT_ALPH_b;
+    };
+    __IM uint32_t RESERVED15[36];
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_SRC_BSIZE; /*!< (@ 0x00020400) RPFn Basic Read Size Register                              */
+
+        struct
+        {
+            __IOM uint32_t BVSIZE : 13;    /*!< [12..0] Vertical Size of RPF Basic Read Area                              */
+            uint32_t              : 3;
+            __IOM uint32_t BHSIZE : 13;    /*!< [28..16] Horizontal Size of RPF Basic Read Area                           */
+            uint32_t              : 3;
+        } VI6_RPF1_SRC_BSIZE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_SRC_ESIZE; /*!< (@ 0x00020404) RPFn Extended Read Size Register                           */
+
+        struct
+        {
+            __IOM uint32_t EVSIZE : 13;    /*!< [12..0] RPF Extended Vertical Read Size                                   */
+            uint32_t              : 3;
+            __IOM uint32_t EHSIZE : 13;    /*!< [28..16] RPF Extended Horizontal Read Size                                */
+            uint32_t              : 3;
+        } VI6_RPF1_SRC_ESIZE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_INFMT; /*!< (@ 0x00020408) RPFn Input Format Register                                 */
+
+        struct
+        {
+            __IOM uint32_t RDFMT : 7;  /*!< [6..0] RPF Input Image Format Setting                                     */
+            uint32_t             : 1;
+            __IOM uint32_t CSC   : 1;  /*!< [8..8] Color Space Conversion Enable                                      */
+            __IOM uint32_t RDTM  : 3;  /*!< [11..9] CSC Conversion Expression Setting                                 */
+            __IOM uint32_t CEXT  : 2;  /*!< [13..12] Lower-Bit Color Data Extension Method Setting                    */
+            __IOM uint32_t SPUVS : 1;  /*!< [14..14] RPF Input Mode Setting 2                                         */
+            __IOM uint32_t SPYCS : 1;  /*!< [15..15] RPF Input Mode Setting 1                                         */
+            __IOM uint32_t CIPM  : 1;  /*!< [16..16] Horizontal Chrominance Interpolation Method Setting              */
+            uint32_t             : 11;
+            __IOM uint32_t VIR   : 1;  /*!< [28..28] Virtual Input Enable                                             */
+            uint32_t             : 3;
+        } VI6_RPF1_INFMT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_DSWAP; /*!< (@ 0x0002040C) RPFn Data Swapping Register                                */
+
+        struct
+        {
+            __IOM uint32_t P_BTS : 1;  /*!< [0..0] Picture Plane Data Swapping in Byte Units                          */
+            __IOM uint32_t P_WDS : 1;  /*!< [1..1] Picture Plane Data Swapping in Word Units                          */
+            __IOM uint32_t P_LWS : 1;  /*!< [2..2] Picture Plane Data Swapping in long word Units                     */
+            __IOM uint32_t P_LLS : 1;  /*!< [3..3] Picture Plane Data Swapping in LONG LWORD Units                    */
+            uint32_t             : 4;
+            __IOM uint32_t A_BTS : 1;  /*!< [8..8] alpha Plane Data Swapping in Byte Units                               */
+            __IOM uint32_t A_WDS : 1;  /*!< [9..9] alpha Plane Data Swapping in Word Units                               */
+            __IOM uint32_t A_LWS : 1;  /*!< [10..10] alpha Plane Data Swapping in long word Units                        */
+            __IOM uint32_t A_LLS : 1;  /*!< [11..11] alpha Plane Data Swapping in LONG LWORD Units                       */
+            uint32_t             : 20;
+        } VI6_RPF1_DSWAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_LOC;    /*!< (@ 0x00020410) RPFn Display Location Register                             */
+
+        struct
+        {
+            __IOM uint32_t VCOORD : 13; /*!< [12..0] Vertical Coordinate of Sublayer Display Location on
+                                         *   Master Layer                                                              */
+            uint32_t              : 3;
+            __IOM uint32_t HCOORD : 13; /*!< [28..16] Horizontal Coordinate of Sublayer Display Location
+                                         *   on Master Layer                                                           */
+            uint32_t : 3;
+        } VI6_RPF1_LOC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_ALPH_SEL; /*!< (@ 0x00020414) RPFn alpha Plane Selection Control Register                   */
+
+        struct
+        {
+            __IOM uint32_t ALPHA0 : 8;    /*!< [7..0] 8-Bit alpha Value Output when 1-Bit alpha Value is 0                     */
+            __IOM uint32_t ALPHA1 : 8;    /*!< [15..8] 8-Bit alpha Value Output when 1-Bit alpha Value is 1                    */
+            uint32_t              : 2;
+            __IOM uint32_t AEXT   : 2;    /*!< [19..18] Lower-Bit alpha Value Extension Method Set                          */
+            uint32_t              : 3;
+            __IOM uint32_t BSEL   : 1;    /*!< [23..23] alpha Bit Count Conversion Selection for 1-Bit Mask Generator       */
+            __IOM uint32_t IROP   : 4;    /*!< [27..24] IROP Operation Setting                                           */
+            __IOM uint32_t ASEL   : 3;    /*!< [30..28] alpha Format and Processing Method Select                           */
+            uint32_t              : 1;
+        } VI6_RPF1_ALPH_SEL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_VRTCOL_SET; /*!< (@ 0x00020418) RPFn Virtual Plane Color Information Register              */
+
+        struct
+        {
+            __IOM uint32_t LAYB : 8;        /*!< [7..0] Virtual-Input Fixed B/Cb Component Value                           */
+            __IOM uint32_t LAYG : 8;        /*!< [15..8] Virtual-Input Fixed G/Y Component Value                           */
+            __IOM uint32_t LAYR : 8;        /*!< [23..16] Virtual-Input Fixed R/Cr Component Value                         */
+            __IOM uint32_t LAYA : 8;        /*!< [31..24] Virtual-Input Fixed alpha Value                                     */
+        } VI6_RPF1_VRTCOL_SET_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_MSKCTRL; /*!< (@ 0x0002041C) RPFn Mask Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t MGB    : 8;   /*!< [7..0] B/Cb Comparison Value for 1-Bit alpha Generation                      */
+            __IOM uint32_t MGG    : 8;   /*!< [15..8] G/Y Comparison Value for 1-Bit alpha Generation                      */
+            __IOM uint32_t MGR    : 8;   /*!< [23..16] R/Cr Comparison Value for 1-Bit alpha Generation                    */
+            __IOM uint32_t MSK_EN : 1;   /*!< [24..24] Mask Generation Specification                                    */
+            uint32_t              : 7;
+        } VI6_RPF1_MSKCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_MSKSET0; /*!< (@ 0x00020420) RPFn IROP-SRC Input Value Register 0                       */
+
+        struct
+        {
+            __IOM uint32_t MSB0 : 8;     /*!< [7..0] IROP-Source Input B/Cb Value when 1-Bit alpha is 0                    */
+            __IOM uint32_t MSG0 : 8;     /*!< [15..8] IROP-Source Input G/Y Value when 1-Bit alpha is 0                    */
+            __IOM uint32_t MSR0 : 8;     /*!< [23..16] IROP-Source Input R/Cr Value when 1-Bit alpha is 0                  */
+            __IOM uint32_t MSA0 : 8;     /*!< [31..24] IROP-Source Input alpha Value when 1-Bit alpha is 0                    */
+        } VI6_RPF1_MSKSET0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_MSKSET1; /*!< (@ 0x00020424) RPFn IROP-SRC Input Value Register 1                       */
+
+        struct
+        {
+            __IOM uint32_t MSB1 : 8;     /*!< [7..0] IROP-Source Input B/Cb Value when 1-Bit alpha is 1                    */
+            __IOM uint32_t MSG1 : 8;     /*!< [15..8] IROP-Source Input G/Y Value when 1-Bit alpha is 1                    */
+            __IOM uint32_t MSR1 : 8;     /*!< [23..16] IROP-Source Input R/Cr Value when 1-Bit alpha is 1                  */
+            __IOM uint32_t MSA1 : 8;     /*!< [31..24] IROP-Source Input alpha Value when 1-Bit alpha is 1                    */
+        } VI6_RPF1_MSKSET1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_CKEY_CTRL; /*!< (@ 0x00020428) RPFn Color Keying Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t SAPE0 : 1;      /*!< [0..0] Comparison Color Data Setting 0 Enable/Disable                     */
+            __IOM uint32_t SAPE1 : 1;      /*!< [1..1] Comparison Color Data Setting 1 Enable/Disable                     */
+            uint32_t             : 2;
+            __IOM uint32_t CV    : 1;      /*!< [4..4] Color Replacement Control                                          */
+            uint32_t             : 3;
+            __IOM uint32_t LTH   : 1;      /*!< [8..8] Transparent color-luma Threshold Mode Enable/Disable               */
+            uint32_t             : 23;
+        } VI6_RPF1_CKEY_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_CKEY_SET0; /*!< (@ 0x0002042C) RPFn Color Keying Color Setting Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t B0  : 8;        /*!< [7..0] B/Cb Component Data in Color Keying Color Information-0            */
+            __IOM uint32_t GY0 : 8;        /*!< [15..8] G/Y Component Data in Color Keying Color Information-0            */
+            __IOM uint32_t R0  : 8;        /*!< [23..16] R/Cr Component Data in Color Keying Color Information-0          */
+            __IOM uint32_t AP0 : 8;        /*!< [31..24] alpha Data in Color Keying Color Information-0                      */
+        } VI6_RPF1_CKEY_SET0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_CKEY_SET1; /*!< (@ 0x00020430) RPFn Color Keying Color Setting Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t B1  : 8;        /*!< [7..0] B/Cb Component Data in Color Keying Color Information-1            */
+            __IOM uint32_t GY1 : 8;        /*!< [15..8] G/Y Component Data in Color Keying Color Information-1            */
+            __IOM uint32_t R1  : 8;        /*!< [23..16] R/Cr Component Data in Color Keying Color Information-1          */
+            __IOM uint32_t AP1 : 8;        /*!< [31..24] alpha Data in Color Keying Color Information-1                      */
+        } VI6_RPF1_CKEY_SET1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_SRCM_PSTRIDE; /*!< (@ 0x00020434) RPFn Source Picture Memory Stride Setting Register         */
+
+        struct
+        {
+            __IOM uint32_t PICT_STRD_C : 16;  /*!< [15..0] Memory Stride of Source Picture C Plane                           */
+            __IOM uint32_t PICT_STRD_Y : 16;  /*!< [31..16] Memory Stride of Source Picture Y/RGB Plane                      */
+        } VI6_RPF1_SRCM_PSTRIDE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_SRCM_ASTRIDE; /*!< (@ 0x00020438) RPFn Source alpha Memory Stride Setting Register              */
+
+        struct
+        {
+            __IOM uint32_t ALPH_STRD : 16;    /*!< [15..0] Memory Stride of Source alpha Plane                                  */
+            uint32_t                 : 16;
+        } VI6_RPF1_SRCM_ASTRIDE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_SRCM_ADDR_Y; /*!< (@ 0x0002043C) RPFn Source Y/RGB Address Register                         */
+
+        struct
+        {
+            __IOM uint32_t SRCM_ADDR_Y : 32; /*!< [31..0] Source Image Y/RGB Plane Storing Address                          */
+        } VI6_RPF1_SRCM_ADDR_Y_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_SRCM_ADDR_C0; /*!< (@ 0x00020440) RPFn Source Chroma Address Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t SRCM_ADDR_C0 : 32; /*!< [31..0] Source Image C Plane Storing Address 0                            */
+        } VI6_RPF1_SRCM_ADDR_C0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_SRCM_ADDR_C1; /*!< (@ 0x00020444) RPFn Source Chroma Address Register 1                      */
+
+        struct
+        {
+            __IOM uint32_t SRCM_ADDR_C1 : 32; /*!< [31..0] Source Image C Plane Storing Address 1                            */
+        } VI6_RPF1_SRCM_ADDR_C1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_SRCM_ADDR_AI; /*!< (@ 0x00020448) RPFn Source alpha Address Register                            */
+
+        struct
+        {
+            __IOM uint32_t SRCM_ADDR_AI : 32; /*!< [31..0] Source Image alpha Plane Storing Address                             */
+        } VI6_RPF1_SRCM_ADDR_AI_b;
+    };
+    __IM uint32_t RESERVED16;
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_BAC;   /*!< (@ 0x00020450) RPFn Bus Access Control Register                           */
+
+        struct
+        {
+            uint32_t            : 16;
+            __IOM uint32_t B512 : 1;   /*!< [16..16] Burst access in 512 pixels' enable                               */
+            uint32_t            : 15;
+        } VI6_RPF1_BAC_b;
+    };
+    __IM uint32_t RESERVED17[6];
+
+    union
+    {
+        __IOM uint32_t VI6_RPF1_MULT_ALPH;  /*!< (@ 0x0002046C) RPFn Multiply Alpha Control Register                       */
+
+        struct
+        {
+            __IOM uint32_t ALPHA_RATIO : 8; /*!< [7..0] Multiply-alpha value                                               */
+            __IOM uint32_t P_MMD       : 2; /*!< [9..8] P_MMD[1:0]                                                         */
+            uint32_t                   : 2;
+            __IOM uint32_t A_MMD       : 1; /*!< [12..12] A_MMD                                                            */
+            uint32_t                   : 19;
+        } VI6_RPF1_MULT_ALPH_b;
+    };
+    __IM uint32_t RESERVED18[740];
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_SRCRPF;  /*!< (@ 0x00021000) WPF0-Source-RPF Register                                   */
+
+        struct
+        {
+            __IOM uint32_t RPF0_ACT : 2; /*!< [1..0] RPF0 Start Enable                                                  */
+            __IOM uint32_t RPF1_ACT : 2; /*!< [3..2] RPF1 Start Enable                                                  */
+            uint32_t                : 20;
+            __IOM uint32_t VIR_ACT2 : 2; /*!< [25..24] Virtual RPF Start Enable in BRS                                  */
+            uint32_t                : 6;
+        } VI6_WPF0_SRCRPF_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_HSZCLIP;  /*!< (@ 0x00021004) WPF0 Horizontal Input Size Clipping Register               */
+
+        struct
+        {
+            __IOM uint32_t HCL_SIZE : 13; /*!< [12..0] Horizontal Clipping Size Setting                                  */
+            uint32_t                : 3;
+            __IOM uint32_t HCL_OFST : 8;  /*!< [23..16] Horizontal Size Clipping Offset Value Setting                    */
+            uint32_t                : 4;
+            __IOM uint32_t HCEN     : 1;  /*!< [28..28] Horizontal Size Clipping Enable/Disable                          */
+            uint32_t                : 3;
+        } VI6_WPF0_HSZCLIP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_VSZCLIP;  /*!< (@ 0x00021008) WPF0 Vertical Input Size Clipping Register                 */
+
+        struct
+        {
+            __IOM uint32_t VCL_SIZE : 13; /*!< [12..0] Vertical Clipping Size Setting                                    */
+            uint32_t                : 3;
+            __IOM uint32_t VCL_OFST : 8;  /*!< [23..16] Vertical Size Clipping Offset Value Setting                      */
+            uint32_t                : 4;
+            __IOM uint32_t VCEN     : 1;  /*!< [28..28] Vertical Size Clipping Enable/Disable                            */
+            uint32_t                : 3;
+        } VI6_WPF0_VSZCLIP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_OUTFMT; /*!< (@ 0x0002100C) WPF0 Output Format Register                                */
+
+        struct
+        {
+            __IOM uint32_t WRFMT : 7;   /*!< [6..0] WPF Output Image Format Setting                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CSC   : 1;   /*!< [8..8] Color Space Conversion Setting                                     */
+            __IOM uint32_t WRTM  : 3;   /*!< [11..9] CSC Conversion Expression Setting                                 */
+            __IOM uint32_t DITH  : 2;   /*!< [13..12] Ordered Dither (mode B) Enable/Disable                           */
+            __IOM uint32_t SPUVS : 1;   /*!< [14..14] WPF Output Mode Setting 2                                        */
+            __IOM uint32_t SPYCS : 1;   /*!< [15..15] WPF Output Mode Setting 1                                        */
+            __IOM uint32_t ROT   : 3;   /*!< [18..16] Rotation Processing Select                                       */
+            uint32_t             : 3;
+            __IOM uint32_t ODE   : 1;   /*!< [22..22] Ordered Dither (mode A) Enable/Disable                           */
+            __IOM uint32_t PXA   : 1;   /*!< [23..23] PAD Data Select                                                  */
+            __IOM uint32_t PDV   : 8;   /*!< [31..24] PAD Value in Output Packed Data                                  */
+        } VI6_WPF0_OUTFMT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_DSWAP; /*!< (@ 0x00021010) WPF0 Data Swapping Register                                */
+
+        struct
+        {
+            __IOM uint32_t P_BTS : 1;  /*!< [0..0] P_BTS                                                              */
+            __IOM uint32_t P_WDS : 1;  /*!< [1..1] WPF Output Data Swapping in Word Units                             */
+            __IOM uint32_t P_LWS : 1;  /*!< [2..2] P_LWS                                                              */
+            __IOM uint32_t P_LLS : 1;  /*!< [3..3] P_LLS                                                              */
+            uint32_t             : 28;
+        } VI6_WPF0_DSWAP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_RNDCTRL; /*!< (@ 0x00021014) WPF0 Rounding Control Register                             */
+
+        struct
+        {
+            uint32_t               : 12;
+            __IOM uint32_t CLMD    : 2; /*!< [13..12] Color Data Clipping                                              */
+            uint32_t               : 2;
+            __IOM uint32_t ATHRESH : 8; /*!< [23..16] Threshold for Conversion to 1-Bit alpha Data                        */
+            __IOM uint32_t ABRM    : 2; /*!< [25..24] Bit Count Reduction Method Selection for Data Storage
+                                         *   in PAD                                                                    */
+            uint32_t            : 2;
+            __IOM uint32_t CBRM : 1;    /*!< [28..28] Bit Count Reduction Method Selection for Data Storage
+                                         *   in Packed RGB                                                             */
+            uint32_t : 3;
+        } VI6_WPF0_RNDCTRL_b;
+    };
+    __IM uint32_t RESERVED19;
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_DSTM_STRIDE_Y; /*!< (@ 0x0002101C) WPF0 Destination Y Plane Memory Stride Register            */
+
+        struct
+        {
+            __IOM uint32_t PICT_STRD_Y : 16;   /*!< [15..0] Memory Stride of Destination Picture Y/RGB Plane                  */
+            uint32_t                   : 16;
+        } VI6_WPF0_DSTM_STRIDE_Y_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_DSTM_STRIDE_C; /*!< (@ 0x00021020) WPF0 Destination C Plane Memory Stride Register            */
+
+        struct
+        {
+            __IOM uint32_t PICT_STRD_C : 16;   /*!< [15..0] Memory Stride of Destination Picture C Plane                      */
+            uint32_t                   : 16;
+        } VI6_WPF0_DSTM_STRIDE_C_b;
+    };
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_DSTM_ADDR_C0; /*!< (@ 0x00021028) WPF0 Destination Chroma Address Register 0                 */
+
+        struct
+        {
+            __IOM uint32_t DSTM_ADDR_C0 : 32; /*!< [31..0] Destination Image C Plane Storing Address 0                       */
+        } VI6_WPF0_DSTM_ADDR_C0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_DSTM_ADDR_C1; /*!< (@ 0x0002102C) WPF0 Destination Chroma Address Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t DSTM_ADDR_C1 : 32; /*!< [31..0] Destination Image C Plane Storing Address 1                       */
+        } VI6_WPF0_DSTM_ADDR_C1_b;
+    };
+    __IM uint32_t RESERVED21;
+
+    union
+    {
+        __IOM uint32_t VI6_WPF0_WRBCK_CTRL; /*!< (@ 0x00021034) WPF0 LIF Write Back Control Register                       */
+
+        struct
+        {
+            __IOM uint32_t WBMD : 2;        /*!< [1..0] Display Data Write Back Control                                    */
+            uint32_t            : 30;
+        } VI6_WPF0_WRBCK_CTRL_b;
+    };
+    __IM uint32_t RESERVED22[1010];
+
+    union
+    {
+        __IOM uint32_t VI6_DPR_RPF0_ROUTE; /*!< (@ 0x00022000) RPF0 Routing Register                                      */
+
+        struct
+        {
+            __IOM uint32_t RT_RPF0 : 6;    /*!< [5..0] RPF0 Target Node Value                                             */
+            uint32_t               : 26;
+        } VI6_DPR_RPF0_ROUTE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_DPR_RPF1_ROUTE; /*!< (@ 0x00022004) RPF1 Routing Register                                      */
+
+        struct
+        {
+            __IOM uint32_t RT_RPF1 : 6;    /*!< [5..0] RPF1 Target Node Value                                             */
+            uint32_t               : 26;
+        } VI6_DPR_RPF1_ROUTE_b;
+    };
+    __IM uint32_t RESERVED23[3];
+
+    union
+    {
+        __IOM uint32_t VI6_DPR_WPF0_FPORCH; /*!< (@ 0x00022014) WPF0 Timing Control Register                               */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IOM uint32_t FP_WPF0 : 6; /*!< [13..8] WPF0 Internal Operation Timing Setting                            */
+            uint32_t               : 18;
+        } VI6_DPR_WPF0_FPORCH_b;
+    };
+    __IM uint32_t RESERVED24[9];
+
+    union
+    {
+        __IOM uint32_t VI6_DPR_LUT_ROUTE; /*!< (@ 0x0002203C) LUT Routing Register                                       */
+
+        struct
+        {
+            __IOM uint32_t RT  : 6;       /*!< [5..0] LUT Target Node Value                                              */
+            uint32_t           : 2;
+            __IOM uint32_t FP  : 6;       /*!< [13..8] LUT Internal Operation Timing Setting                             */
+            uint32_t           : 2;
+            __IOM uint32_t FXA : 8;       /*!< [23..16] Fixed alpha Output Value for LUT                                    */
+            uint32_t           : 8;
+        } VI6_DPR_LUT_ROUTE_b;
+    };
+    __IM uint32_t RESERVED25[4];
+
+    union
+    {
+        __IOM uint32_t VI6_DPR_BRS_ROUTE; /*!< (@ 0x00022050) BRS Routing Register                                       */
+
+        struct
+        {
+            __IOM uint32_t RT     : 6;    /*!< [5..0] BRS Target Node Value                                              */
+            uint32_t              : 2;
+            __IOM uint32_t FP     : 6;    /*!< [13..8] BRS Internal Operation Timing Setting                             */
+            uint32_t              : 14;
+            __IOM uint32_t BRSSEL : 1;    /*!< [28..28] Always set this bit to 1.                                        */
+            uint32_t              : 3;
+        } VI6_DPR_BRS_ROUTE_b;
+    };
+    __IM uint32_t RESERVED26[491];
+
+    union
+    {
+        __IOM uint32_t VI6_LUT_CTRL;   /*!< (@ 0x00022800) LUT Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t LUT_EN : 1; /*!< [0..0] 1D-LUT Enable/Disable                                              */
+            uint32_t              : 31;
+        } VI6_LUT_CTRL_b;
+    };
+    __IM uint32_t RESERVED27[1087];
+
+    union
+    {
+        __IOM uint32_t VI6_BRS_INCTRL; /*!< (@ 0x00023900) BRS Input Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t DITH0 : 3;  /*!< [2..0] Dithering of CH0 Input to BRS                                      */
+            __IOM uint32_t ODE0  : 1;  /*!< [3..3] Ordered Dither (mode A) of CH0 Input to BRS Enable/Disable         */
+            __IOM uint32_t DITH1 : 3;  /*!< [6..4] Dithering of CH1 Input to BRS                                      */
+            __IOM uint32_t ODE1  : 1;  /*!< [7..7] Ordered Dither (mode A) of CH1 Input to BRS Enable/Disable         */
+            uint32_t             : 8;
+            __IOM uint32_t D0ON  : 1;  /*!< [16..16] Ordered dither (mode B) Enable of BRS Input 0                    */
+            __IOM uint32_t D1ON  : 1;  /*!< [17..17] Ordered dither (mode B) Enable of BRS Input 1                    */
+            uint32_t             : 10;
+            __IOM uint32_t NRM   : 1;  /*!< [28..28] Color Data Normalization                                         */
+            uint32_t             : 3;
+        } VI6_BRS_INCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_BRS_VIRRPF_SIZE; /*!< (@ 0x00023904) Size Register of BRS Input Virtual RPF                     */
+
+        struct
+        {
+            __IOM uint32_t VIR_VSIZE : 13;  /*!< [12..0] Virtual RPF Vertical Size                                         */
+            uint32_t                 : 3;
+            __IOM uint32_t VIR_HSIZE : 13;  /*!< [28..16] Virtual RPF Horizontal Size                                      */
+            uint32_t                 : 3;
+        } VI6_BRS_VIRRPF_SIZE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_BRS_VIRRPF_LOC; /*!< (@ 0x00023908) Display Location Register of BRS Input Virtual
+                                            *                  RPF                                                        */
+
+        struct
+        {
+            __IOM uint32_t VCOORD : 13;    /*!< [12..0] Vertical Coordinate of Virtual RPF Location on Master
+                                            *   Layer                                                                     */
+            uint32_t              : 3;
+            __IOM uint32_t HCOORD : 13;    /*!< [28..16] Horizontal Coordinate of Virtual RPF Location on Master
+                                            *   Layer                                                                     */
+            uint32_t : 3;
+        } VI6_BRS_VIRRPF_LOC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_BRS_VIRRPF_COL; /*!< (@ 0x0002390C) Color Information Register of BRS Input Virtual
+                                            *                  RPF                                                        */
+
+        struct
+        {
+            __IOM uint32_t COL_BCB : 8;    /*!< [7..0] Fixed B/Cb of Virtual RPF                                          */
+            __IOM uint32_t COL_GY  : 8;    /*!< [15..8] Fixed G/Y of Virtual RPF                                          */
+            __IOM uint32_t COL_RCR : 8;    /*!< [23..16] Fixed R/Cr of Virtual RPF                                        */
+            __IOM uint32_t COL_A   : 8;    /*!< [31..24] Fixed alpha of Virtual RPF                                          */
+        } VI6_BRS_VIRRPF_COL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_BRSA_CTRL;  /*!< (@ 0x00023910) BRS Control Register A                                     */
+
+        struct
+        {
+            __IOM uint32_t AROP   : 4; /*!< [3..0] alpha Data ROP Operator                                               */
+            __IOM uint32_t CROP   : 4; /*!< [7..4] Color Data ROP Operator                                            */
+            uint32_t              : 8;
+            __IOM uint32_t SRCSEL : 3; /*!< [18..16] Input Selection for SRC Side of Blending/ROP Unit A              */
+            uint32_t              : 1;
+            __IOM uint32_t DSTSEL : 3; /*!< [22..20] Input Selection for DST Side of Blending/ROP Unit A              */
+            uint32_t              : 8;
+            __IOM uint32_t RBC    : 1; /*!< [31..31] Operation Type of Blending/ROP Unit A                            */
+        } VI6_BRSA_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_BRSA_BLD;   /*!< (@ 0x00023914) BRS Blend Control Register A                               */
+
+        struct
+        {
+            __IOM uint32_t COEFY : 8;  /*!< [7..0] Fixed alpha Value 1                                                   */
+            __IOM uint32_t COEFX : 8;  /*!< [15..8] Fixed alpha Value 0                                                  */
+            __IOM uint32_t ACMDY : 3;  /*!< [18..16] alpha Creation Coefficient Y                                        */
+            uint32_t             : 1;
+            __IOM uint32_t ACMDX : 3;  /*!< [22..20] alpha Creation Coefficient X                                        */
+            __IOM uint32_t ABES  : 1;  /*!< [23..23] Blending alpha Creation Expression                                  */
+            __IOM uint32_t CCMDY : 3;  /*!< [26..24] Blending Coefficient Y Selection                                 */
+            uint32_t             : 1;
+            __IOM uint32_t CCMDX : 3;  /*!< [30..28] Blending Coefficient X Selection                                 */
+            __IOM uint32_t CBES  : 1;  /*!< [31..31] Blending Expression Selection                                    */
+        } VI6_BRSA_BLD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_BRSB_CTRL;  /*!< (@ 0x00023918) BRS Control Register B                                     */
+
+        struct
+        {
+            __IOM uint32_t AROP : 4;   /*!< [3..0] alpha Data ROP Operator                                               */
+            __IOM uint32_t CROP : 4;   /*!< [7..4] Color Data ROP Operator                                            */
+            uint32_t            : 23;
+            __IOM uint32_t RBC  : 1;   /*!< [31..31] Operation Type of Blending/ROP Unit B                            */
+        } VI6_BRSB_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_BRSB_BLD;   /*!< (@ 0x0002391C) BRS Blend Control Register B                               */
+
+        struct
+        {
+            __IOM uint32_t COEFY : 8;  /*!< [7..0] Fixed alpha Value 1                                                   */
+            __IOM uint32_t COEFX : 8;  /*!< [15..8] Fixed alpha Value 0                                                  */
+            __IOM uint32_t ACMDY : 3;  /*!< [18..16] alpha Creation Coefficient Y                                        */
+            uint32_t             : 1;
+            __IOM uint32_t ACMDX : 3;  /*!< [22..20] alpha Creation Coefficient X                                        */
+            __IOM uint32_t ABES  : 1;  /*!< [23..23] Blending alpha Creation Expression                                  */
+            __IOM uint32_t CCMDY : 3;  /*!< [26..24] Blending Coefficient Y Selection                                 */
+            uint32_t             : 1;
+            __IOM uint32_t CCMDX : 3;  /*!< [30..28] Blending Coefficient X Selection                                 */
+            __IOM uint32_t CBES  : 1;  /*!< [31..31] Blending Expression Selection                                    */
+        } VI6_BRSB_BLD_b;
+    };
+    __IM uint32_t RESERVED28[120];
+
+    union
+    {
+        __IOM uint32_t VI6_LIF0_CTRL;   /*!< (@ 0x00023B00) LIF0 Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t LIF_EN : 1;  /*!< [0..0] Enable/Disable of Data Output to External Display Module           */
+            __IOM uint32_t REQSEL : 1;  /*!< [1..1] REQSEL                                                             */
+            uint32_t              : 2;
+            __IOM uint32_t CFMT   : 1;  /*!< [4..4] Chroma Format                                                      */
+            uint32_t              : 3;
+            __IOM uint32_t PADL   : 1;  /*!< [8..8] PADL                                                               */
+            uint32_t              : 7;
+            __IOM uint32_t OBTH   : 12; /*!< [27..16] Buffer Threshold for Start Ready Notification to Display
+                                         *   Module                                                                    */
+            uint32_t : 4;
+        } VI6_LIF0_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_LIF0_CSBTH; /*!< (@ 0x00023B04) LIF0 Clock Stop Buffer Control Register                    */
+
+        struct
+        {
+            __IOM uint32_t LBTH : 12;  /*!< [11..0] Buffer Threshold for Clock Start in Dynamic Clock Control         */
+            uint32_t            : 4;
+            __IOM uint32_t HBTH : 12;  /*!< [27..16] Buffer Threshold for Clock Stop in Dynamic Clock Control         */
+            uint32_t            : 4;
+        } VI6_LIF0_CSBTH_b;
+    };
+    __IM uint32_t RESERVED29;
+
+    union
+    {
+        __IOM uint32_t VI6_LIF0_LBA;   /*!< (@ 0x00023B0C) LIF0 Buffer Attribute Register                             */
+
+        struct
+        {
+            __IOM uint32_t LBA2 : 12;  /*!< [11..0] LIF Buffer Attribute Register 2                                   */
+            uint32_t            : 4;
+            __IOM uint32_t LBA1 : 12;  /*!< [27..16] LIF Buffer Attribute Register 1                                  */
+            uint32_t            : 3;
+            __IOM uint32_t LBA0 : 1;   /*!< [31..31] LIF Buffer Attribute Register 0                                  */
+        } VI6_LIF0_LBA_b;
+    };
+    __IM uint32_t RESERVED30[8];
+
+    union
+    {
+        __IOM uint32_t VI6_LIF0_PADLN_CYC; /*!< (@ 0x00023B30) LIF0 Padding Line Cycle Register                           */
+
+        struct
+        {
+            __IOM uint32_t PADLN_CYC : 6;  /*!< [5..0] Cycle of padding pattern                                           */
+            uint32_t                 : 26;
+        } VI6_LIF0_PADLN_CYC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_LIF0_PADLN_PT;      /*!< (@ 0x00023B34) LIF0 Padding Line Pattern Register                         */
+
+        struct
+        {
+            __IOM uint32_t PADLN_PATTERN : 32; /*!< [31..0] Pattern of padding with dummy lines                               */
+        } VI6_LIF0_PADLN_PT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_LIF0_PADLN_VAL; /*!< (@ 0x00023B38) LIF0 Padding Line Value Register                           */
+
+        struct
+        {
+            __IOM uint32_t PADB : 8;       /*!< [7..0] PADB                                                               */
+            __IOM uint32_t PADG : 8;       /*!< [15..8] PADG                                                              */
+            __IOM uint32_t PADR : 8;       /*!< [23..16] PADR                                                             */
+            __IOM uint32_t PADA : 8;       /*!< [31..24] PADA                                                             */
+        } VI6_LIF0_PADLN_VAL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VI6_LIF0_PADLN_SIZE;  /*!< (@ 0x00023B3C) LIF0 Padding Line Size Register                            */
+
+        struct
+        {
+            __IOM uint32_t PADLN_VSIZE : 13; /*!< [12..0] Vertical Size of LIF output in case of enabling Padding
+                                              *   line                                                                      */
+            uint32_t : 19;
+        } VI6_LIF0_PADLN_SIZE_b;
+    };
+} R_LCDC_Type;                               /*!< Size = 146240 (0x23b40)                                                   */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PCIE0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief PCI Express 3.0 Interface 0 (R_PCIE0)
+ */
+
+typedef struct                                     /*!< (@ 0x92100000) R_PCIE0 Structure                                          */
+{
+    __IM uint32_t RESERVED[32];
+    __IOM R_PCIE0_PCI_REQDATA_Type PCI_REQDATA[3]; /*!< (@ 0x00000080) [0..2]                                                     */
+
+    union
+    {
+        __IM uint32_t PCI_EP_REQRCVDAT;            /*!< (@ 0x0000008C) Request Receive Data Register                              */
+        __IM uint32_t PCI_RC_REQRCVDAT;            /*!< (@ 0x0000008C) Request Receive Data Register                              */
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_REQADR1; /*!< (@ 0x00000090) Request Address Register 1                                 */
+        __IOM uint32_t PCI_RC_REQADR1; /*!< (@ 0x00000090) Request Address Register 1                                 */
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_REQADR2; /*!< (@ 0x00000094) Request Address Register 2                                 */
+        __IOM uint32_t PCI_RC_REQADR2; /*!< (@ 0x00000094) Request Address Register 2                                 */
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_REQBE; /*!< (@ 0x00000098) Request Byte Enable Register                               */
+
+            struct
+            {
+                __IOM uint32_t RBE : 4;  /*!< [3..0] Request Byte Enable                                                */
+                uint32_t           : 28;
+            } PCI_EP_REQBE_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_REQBE; /*!< (@ 0x00000098) Request Byte Enable Register                               */
+
+            struct
+            {
+                __IOM uint32_t RBE : 4;  /*!< [3..0] Request Byte Enable                                                */
+                uint32_t           : 28;
+            } PCI_RC_REQBE_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_REQISS;      /*!< (@ 0x0000009C) Request Issue Register                                     */
+
+            struct
+            {
+                __IOM uint32_t RI        : 1;  /*!< [0..0] Request Issue                                                      */
+                uint32_t                 : 7;
+                __IOM uint32_t TR_TYPE   : 4;  /*!< [11..8] Set the type of Request.                                          */
+                __IOM uint32_t FUNC      : 3;  /*!< [14..12] Set the function of Request.                                     */
+                uint32_t                 : 1;
+                __IM uint32_t MOR_STATUS : 3;  /*!< [18..16] These bits retain the MOR Status of Completion TLP
+                                                *   for Non-Posted requests issued.                                           */
+                __IM uint32_t MOR_EP_ERR : 1;  /*!< [19..19] It is set to 1 when a Poisoned Completion TLP for a
+                                                *   Non-Posted request issued by this register is received.                   */
+                __IM uint32_t MOR_CH_PERR : 1; /*!< [20..20] It is set to 1 when a header error occurs in the Completion
+                                                *   TLP for the Non-Posted request issued by this register.                   */
+                __IM uint32_t MOR_CD_PERR : 1; /*!< [21..21] It is set to 1 when a data error occurs in the Completion
+                                                *   TLP for the Non-Posted request issued by this register.                   */
+                __IM uint32_t RR : 1;          /*!< [22..22] Request Rejection                                                */
+                uint32_t         : 9;
+            } PCI_EP_REQISS_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_REQISS;      /*!< (@ 0x0000009C) Request Issue Register                                     */
+
+            struct
+            {
+                __IOM uint32_t RI        : 1;  /*!< [0..0] Request Issue                                                      */
+                uint32_t                 : 7;
+                __IOM uint32_t TR_TYPE   : 4;  /*!< [11..8] Set the type of Request.                                          */
+                __IOM uint32_t FUNC      : 3;  /*!< [14..12] Set the function of Request.                                     */
+                uint32_t                 : 1;
+                __IM uint32_t MOR_STATUS : 3;  /*!< [18..16] These bits retain the MOR Status of Completion TLP
+                                                *   for Non-Posted requests issued.                                           */
+                __IM uint32_t MOR_EP_ERR : 1;  /*!< [19..19] It is set to 1 when a Poisoned Completion TLP for a
+                                                *   Non-Posted request issued by this register is received.                   */
+                __IM uint32_t MOR_CH_PERR : 1; /*!< [20..20] It is set to 1 when a header error occurs in the Completion
+                                                *   TLP for the Non-Posted request issued by this register.                   */
+                __IM uint32_t MOR_CD_PERR : 1; /*!< [21..21] It is set to 1 when a data error occurs in the Completion
+                                                *   TLP for the Non-Posted request issued by this register.                   */
+                __IM uint32_t RR : 1;          /*!< [22..22] Request Rejection                                                */
+                uint32_t         : 9;
+            } PCI_RC_REQISS_b;
+        };
+    };
+    __IM uint32_t RESERVED1[24];
+
+    union
+    {
+        __IOM uint32_t PCI_RC_MSIRCVWADRL; /*!< (@ 0x00000100) MSI Receive Window Address (Lower) Register                */
+
+        struct
+        {
+            __IOM uint32_t MSIRWE  : 1;    /*!< [0..0] MSI Receive Window Enable                                          */
+            __IOM uint32_t MDE     : 1;    /*!< [1..1] Message Data Enabled                                               */
+            uint32_t               : 1;
+            __IOM uint32_t MSIRWAL : 29;   /*!< [31..3] MSI Receive Window Address (Lower)                                */
+        } PCI_RC_MSIRCVWADRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_MSIRCVWADRU; /*!< (@ 0x00000104) MSI Receive Window Address (Upper) Register                */
+
+        struct
+        {
+            __IOM uint32_t MSIRWAU : 32;   /*!< [31..0] MSI Receive Window Address (Upper)                                */
+        } PCI_RC_MSIRCVWADRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_MSIRCVWMSKL; /*!< (@ 0x00000108) MSI Receive Window Mask (Lower) Register                   */
+
+        struct
+        {
+            __IOM uint32_t MSIRWML : 32;   /*!< [31..0] MSI Receive Window Mask (Lower)                                   */
+        } PCI_RC_MSIRCVWMSKL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_MSIRCVWMSKU; /*!< (@ 0x0000010C) MSI Receive Window Mask (Upper) Register                   */
+
+        struct
+        {
+            __IOM uint32_t MSIRWMU : 31;   /*!< [30..0] MSI Receive Window Mask (Upper)                                   */
+            uint32_t               : 1;
+        } PCI_RC_MSIRCVWMSKU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_PINTRCVIE; /*!< (@ 0x00000110) PCI INTx Receive Interrupt Enable Register                 */
+
+        struct
+        {
+            __IOM uint32_t INTARIE : 1;  /*!< [0..0] INTA Receive Interrupt Enable                                      */
+            __IOM uint32_t INTBRIE : 1;  /*!< [1..1] INTB Receive Interrupt Enable                                      */
+            __IOM uint32_t INTCRIE : 1;  /*!< [2..2] INTC Receive Interrupt Enable                                      */
+            __IOM uint32_t INTDRIE : 1;  /*!< [3..3] INTD Receive Interrupt Enable                                      */
+            __IOM uint32_t MSIRIE  : 1;  /*!< [4..4] MSI Receive Interrupt Enable                                       */
+            uint32_t               : 27;
+        } PCI_RC_PINTRCVIE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_PINTRCVIS; /*!< (@ 0x00000114) PCI INTx Receive Interrupt Status Register                 */
+
+        struct
+        {
+            __IOM uint32_t INTARIS : 1;  /*!< [0..0] INTA Receive Interrupt Status                                      */
+            __IOM uint32_t INTBRIS : 1;  /*!< [1..1] INTB Receive Interrupt Status                                      */
+            __IOM uint32_t INTCRIS : 1;  /*!< [2..2] INTC Receive Interrupt Status                                      */
+            __IOM uint32_t INTDRIS : 1;  /*!< [3..3] INTD Receive Interrupt Status                                      */
+            __IOM uint32_t MSIRIS  : 1;  /*!< [4..4] MSI Receive Interrupt Status                                       */
+            uint32_t               : 27;
+        } PCI_RC_PINTRCVIS_b;
+    };
+
+    union
+    {
+        __IM uint32_t PCI_EP_INTXOUTS; /*!< (@ 0x00000118) PCI INTx Out Status Register                               */
+
+        struct
+        {
+            __IM uint32_t INTAS : 1;   /*!< [0..0] INTA Status                                                        */
+            __IM uint32_t INTBS : 1;   /*!< [1..1] INTB Status                                                        */
+            __IM uint32_t INTCS : 1;   /*!< [2..2] INTC Status                                                        */
+            __IM uint32_t INTDS : 1;   /*!< [3..3] INTD Status                                                        */
+            uint32_t            : 28;
+        } PCI_EP_INTXOUTS_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_MSGRCVIE; /*!< (@ 0x00000120) Message Receive Interrupt Enable Register                  */
+
+            struct
+            {
+                uint32_t                 : 16;
+                __IOM uint32_t PMETOARIE : 1; /*!< [16..16] PME_TO_Ack Receive Interrupt Enable                              */
+                __IOM uint32_t PMETORIE  : 1; /*!< [17..17] PME_Turn_Off Receive Interrupt Enable                            */
+                __IOM uint32_t PMPMERIE  : 1; /*!< [18..18] PM_PME Receive Interrupt Enable                                  */
+                __IOM uint32_t PMASNRI   : 1; /*!< [19..19] PM_Active_State_Nak Receive Interrupt                            */
+                uint32_t                 : 4;
+                __IOM uint32_t MRIE      : 1; /*!< [24..24] Message Receive Interrupt Enable                                 */
+                uint32_t                 : 7;
+            } PCI_EP_MSGRCVIE_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_MSGRCVIE; /*!< (@ 0x00000120) Message Receive Interrupt Enable Register                  */
+
+            struct
+            {
+                uint32_t                : 16;
+                __IOM uint32_t PMETOARI : 1; /*!< [16..16] PME_TO_Ack Receive Interrupt                                     */
+                __IOM uint32_t PMETORI  : 1; /*!< [17..17] PME_Turn_Off Receive Interrupt                                   */
+                __IOM uint32_t PMPMERI  : 1; /*!< [18..18] PM_PME Receive Interrupt                                         */
+                __IOM uint32_t PMASNR   : 1; /*!< [19..19] PM_Active_State_Nak Receive                                      */
+                uint32_t                : 4;
+                __IOM uint32_t MRI      : 1; /*!< [24..24] Message Receive Interrupt                                        */
+                uint32_t                : 7;
+            } PCI_RC_MSGRCVIE_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_MSGRCVIS; /*!< (@ 0x00000124) Message Receive Interrupt Status Register                  */
+
+            struct
+            {
+                uint32_t                : 16;
+                __IOM uint32_t PMETOARI : 1; /*!< [16..16] PME_TO_Ack Receive Interrupt                                     */
+                __IOM uint32_t PMETORI  : 1; /*!< [17..17] PME_Turn_Off Receive Interrupt                                   */
+                __IOM uint32_t PMPMERI  : 1; /*!< [18..18] PM_PME Receive Interrupt                                         */
+                __IOM uint32_t PMASNR   : 1; /*!< [19..19] PM_Active_State_Nak Receive                                      */
+                uint32_t                : 4;
+                __IOM uint32_t MRI      : 1; /*!< [24..24] Message Receive Interrupt                                        */
+                uint32_t                : 7;
+            } PCI_EP_MSGRCVIS_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_MSGRCVIS; /*!< (@ 0x00000124) Message Receive Interrupt Status Register                  */
+
+            struct
+            {
+                uint32_t                : 16;
+                __IOM uint32_t PMETOARI : 1; /*!< [16..16] PME_TO_Ack Receive Interrupt                                     */
+                __IOM uint32_t PMETORI  : 1; /*!< [17..17] PME_Turn_Off Receive Interrupt                                   */
+                __IOM uint32_t PMPMERI  : 1; /*!< [18..18] PM_PME Receive Interrupt                                         */
+                __IOM uint32_t PMASNR   : 1; /*!< [19..19] PM_Active_State_Nak Receive                                      */
+                uint32_t                : 4;
+                __IOM uint32_t MRI      : 1; /*!< [24..24] Message Receive Interrupt                                        */
+                uint32_t                : 7;
+            } PCI_RC_MSGRCVIS_b;
+        };
+    };
+    __IM uint32_t RESERVED3[2];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_MSGCODE; /*!< (@ 0x00000130) Message Code Register                                      */
+
+            struct
+            {
+                __IM uint32_t MP : 1;     /*!< [0..0] Message Payload                                                    */
+                uint32_t         : 4;
+                __IM uint32_t R  : 3;     /*!< [7..5] Routing                                                            */
+                __IM uint32_t MC : 8;     /*!< [15..8] Message Code                                                      */
+                uint32_t         : 16;
+            } PCI_EP_MSGCODE_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_MSGCODE; /*!< (@ 0x00000130) Message Code Register                                      */
+
+            struct
+            {
+                __IM uint32_t MP : 1;     /*!< [0..0] Message Payload                                                    */
+                uint32_t         : 4;
+                __IM uint32_t R  : 3;     /*!< [7..5] Routing                                                            */
+                __IM uint32_t MC : 8;     /*!< [15..8] Message Code                                                      */
+                uint32_t         : 16;
+            } PCI_RC_MSGCODE_b;
+        };
+    };
+
+    union
+    {
+        __IM uint32_t PCI_EP_MSGDATA;  /*!< (@ 0x00000134) Message Data Register                                      */
+        __IM uint32_t PCI_RC_MSGDATA;  /*!< (@ 0x00000134) Message Data Register                                      */
+    };
+
+    union
+    {
+        __IM uint32_t PCI_EP_MSGH3DW;  /*!< (@ 0x00000138) Message Header 3rdDW Register                              */
+        __IM uint32_t PCI_RC_MSGH3DW;  /*!< (@ 0x00000138) Message Header 3rdDW Register                              */
+    };
+
+    union
+    {
+        __IM uint32_t PCI_EP_MSGH4DW;  /*!< (@ 0x0000013C) Message Header 4thDW Register                              */
+        __IM uint32_t PCI_RC_MSGH4DW;  /*!< (@ 0x0000013C) Message Header 4thDW Register                              */
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_INTTABLE; /*!< (@ 0x00000140) Interrupt Table Register                                   */
+
+            struct
+            {
+                uint32_t                   : 8;
+                __IM uint32_t MSG_INT      : 1; /*!< [8..8] Message interrupt signal monitor                                   */
+                __IM uint32_t PCIE_EVT_INT : 1; /*!< [9..9] Event interrupt signal monitor                                     */
+                __IM uint32_t AXI_ERR_IN   : 1; /*!< [10..10] Error interrupt signal monitor                                   */
+                uint32_t                   : 13;
+                __IM uint32_t DMA_INT      : 8; /*!< [31..24] DMA_INT interrupt signal monitor                                 */
+            } PCI_EP_INTTABLE_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_INTTABLE;                       /*!< (@ 0x00000140) Interrupt Table Register                                   */
+
+            struct
+            {
+                __IM uint32_t INTA_RC                       : 1; /*!< [0..0] INTA_RC interrupt signal monitor                                   */
+                __IM uint32_t INTB_RC                       : 1; /*!< [1..1] INTB_RC interrupt signal monitor                                   */
+                __IM uint32_t INTC_RC                       : 1; /*!< [2..2] INTC_RC interrupt signal monitor                                   */
+                __IM uint32_t INTD_RC                       : 1; /*!< [3..3] INTD_RC interrupt signal monitor                                   */
+                __IM uint32_t INTMSI_RC                     : 1; /*!< [4..4] INT_MSI interrupt signal monitor                                   */
+                uint32_t                                    : 3;
+                __IM uint32_t MSG_INT                       : 1; /*!< [8..8] Message interrupt signal monitor                                   */
+                __IM uint32_t PCIE_EVT_INT                  : 1; /*!< [9..9] Event interrupt signal monitor                                     */
+                __IM uint32_t AXI_ERR_IN                    : 1; /*!< [10..10] Error interrupt signal monitor                                   */
+                uint32_t                                    : 4;
+                __IM uint32_t INT_LINK_EQUALIZATION_REQUEST : 1; /*!< [15..15] LINK_EQUALIZATION_REQUEST Interrupt signal level monitor */
+                uint32_t                                    : 16;
+            } PCI_RC_INTTABLE_b;
+        };
+    };
+    __IM uint32_t RESERVED4[47];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PEIE0; /*!< (@ 0x00000200) PCIe Event Interrupt Enable 0 Register                     */
+
+            struct
+            {
+                uint32_t                                    : 9;
+                __IOM uint32_t DLUDEN                       : 1; /*!< [9..9] DL_UpDown EN                                                       */
+                __IOM uint32_t ASPML1REN                    : 1; /*!< [10..10] ASPM L1 Rejected interrupt enable                                */
+                uint32_t                                    : 1;
+                __IOM uint32_t RX_DLLP_PM_ENTER_L23_EN      : 1; /*!< [12..12] RX_DLLP_PM_ENTER_L23 interrupt enable                         */
+                uint32_t                                    : 2;
+                __IOM uint32_t BME_PERR_EN                  : 1; /*!< [15..15] Enable BME Parity Error interrupt.                               */
+                uint32_t                                    : 8;
+                __IOM uint32_t CA_EN                        : 1; /*!< [24..24] CA (Completer Abort) interrupt enable                            */
+                __IOM uint32_t AXI_PERR_EN                  : 1; /*!< [25..25] Enable AXIM RAM parity error interrupt                           */
+                uint32_t                                    : 2;
+                __IOM uint32_t RDEN                         : 1; /*!< [28..28] Request complete interrupt enable                                */
+                __IOM uint32_t UI_LINK_SPEED_CHANGE_DONE_EN : 1; /*!< [29..29] Speed change operation completion interrupt enable       */
+                __IOM uint32_t UI_LINK_WIDTH_CHANGE_DONE_EN : 1; /*!< [30..30] Up/Down Configure operation complete interrupt enable    */
+                uint32_t                                    : 1;
+            } PCI_EP_PEIE0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PEIE0; /*!< (@ 0x00000200) PCIe Event Interrupt Enable 0 Register                     */
+
+            struct
+            {
+                uint32_t                                    : 9;
+                __IOM uint32_t DLUDEN                       : 1; /*!< [9..9] DL_UpDown EN                                                       */
+                __IOM uint32_t ASPML1REN                    : 1; /*!< [10..10] ASPM L1 Rejected interrupt enable                                */
+                uint32_t                                    : 1;
+                __IOM uint32_t RX_DLLP_PM_ENTER_L23_EN      : 1; /*!< [12..12] RX_DLLP_PM_ENTER_L23 interrupt enable                         */
+                uint32_t                                    : 11;
+                __IOM uint32_t CA_EN                        : 1; /*!< [24..24] CA (Completer Abort) interrupt enable                            */
+                uint32_t                                    : 3;
+                __IOM uint32_t RDEN                         : 1; /*!< [28..28] Request complete interrupt enable                                */
+                __IOM uint32_t UI_LINK_SPEED_CHANGE_DONE_EN : 1; /*!< [29..29] Speed change operation completion interrupt enable       */
+                __IOM uint32_t UI_LINK_WIDTH_CHANGE_DONE_EN : 1; /*!< [30..30] Up/Down Configure operation complete interrupt enable    */
+                uint32_t                                    : 1;
+            } PCI_RC_PEIE0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PEIS0; /*!< (@ 0x00000204) PCIe Event Interrupt Status 0 Register                     */
+
+            struct
+            {
+                uint32_t                            : 9;
+                __IOM uint32_t DLUDEN               : 1;      /*!< [9..9] DL_UpDown EN                                                       */
+                __IOM uint32_t ASPML1               : 1;      /*!< [10..10] ASPM L1                                                          */
+                uint32_t                            : 1;
+                __IOM uint32_t RX_DLLP_PM_ENTER_L23 : 1;      /*!< [12..12] Indicates transition to L2/L3 State in Power Management
+                                                               *   control.                                                                  */
+                uint32_t                : 2;
+                __IOM uint32_t BME_PERR : 1;                  /*!< [15..15] Indicates that a parity error has occurred in the BME
+                                                               *   RAM.                                                                      */
+                uint32_t          : 8;
+                __IOM uint32_t CA : 1;                        /*!< [24..24] Indicates that the device has responded with CA (Completer
+                                                               *   Abort).                                                                   */
+                __IOM uint32_t AXIM_PERR : 1;                 /*!< [25..25] Indicates that a parity error has occurred in the AXIM
+                                                               *   RAM.                                                                      */
+                uint32_t                                 : 2;
+                __IOM uint32_t RD                        : 1; /*!< [28..28] Request Done                                                     */
+                __IOM uint32_t UI_LINK_SPEED_CHANGE_DONE : 1; /*!< [29..29] Indicates completion of Speed Change operation.             */
+                __IOM uint32_t UI_LINK_WIDTH_CHANGE_DONE : 1; /*!< [30..30] Indicates completion of Up/DownConfigure operation.         */
+                uint32_t                                 : 1;
+            } PCI_EP_PEIS0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PEIS0; /*!< (@ 0x00000204) PCIe Event Interrupt Status 0 Register                     */
+
+            struct
+            {
+                uint32_t                            : 9;
+                __IOM uint32_t DLUDEN               : 1;      /*!< [9..9] DL_UpDown EN                                                       */
+                __IOM uint32_t ASPML1R              : 1;      /*!< [10..10] ASPM L1 Rejected                                                 */
+                uint32_t                            : 1;
+                __IOM uint32_t RX_DLLP_PM_ENTER_L23 : 1;      /*!< [12..12] Indicates transition to L2/L3 State in Power Management
+                                                               *   control.                                                                  */
+                uint32_t          : 11;
+                __IOM uint32_t CA : 1;                        /*!< [24..24] Indicates that the device has responded with CA (Completer
+                                                               *   Abort).                                                                   */
+                uint32_t                                 : 3;
+                __IOM uint32_t RD                        : 1; /*!< [28..28] Request Done                                                     */
+                __IOM uint32_t UI_LINK_SPEED_CHANGE_DONE : 1; /*!< [29..29] Indicates completion of Speed Change operation.             */
+                __IOM uint32_t UI_LINK_WIDTH_CHANGE_DONE : 1; /*!< [30..30] Indicates completion of Up/DownConfigure operation.         */
+                uint32_t                                 : 1;
+            } PCI_RC_PEIS0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PEIE1;                                    /*!< (@ 0x00000208) PCIe Event Interrupt Enable 1 Register                     */
+
+            struct
+            {
+                __IOM uint32_t ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN : 1; /*!< [0..0] Enable ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR interrupts. */
+                __IOM uint32_t ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN : 1; /*!< [1..1] Enable ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR interrupts. */
+                uint32_t                                               : 6;
+                __IOM uint32_t ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN   : 1; /*!< [8..8] Enable ERR_REPLAY_LOWER_CORRECTABLE_ERROR interrupts. */
+                __IOM uint32_t ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN   : 1; /*!< [9..9] Enable ERR_REPLAY_UPPER_CORRECTABLE_ERROR interrupts. */
+                uint32_t                                               : 6;
+                __IOM uint32_t ERR_RPC_REPLAYFIFO_PERR_EN              : 1; /*!< [16..16] Enable ERR_RPC_REPLAYFIFO_PERR interrupts.                 */
+                __IOM uint32_t TXB_PARITY_ERR_EN                       : 1; /*!< [17..17] Enable the TXB_PARITY_ERR interrupt.                             */
+                uint32_t                                               : 14;
+            } PCI_EP_PEIE1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PEIE1;                                    /*!< (@ 0x00000208) PCIe Event Interrupt Enable 1 Register                     */
+
+            struct
+            {
+                __IOM uint32_t ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN : 1; /*!< [0..0] Enable ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR interrupts. */
+                __IOM uint32_t ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN : 1; /*!< [1..1] Enable ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR interrupts. */
+                uint32_t                                               : 6;
+                __IOM uint32_t ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN   : 1; /*!< [8..8] Enable ERR_REPLAY_LOWER_CORRECTABLE_ERROR interrupts. */
+                __IOM uint32_t ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN   : 1; /*!< [9..9] Enable ERR_REPLAY_UPPER_CORRECTABLE_ERROR interrupts. */
+                uint32_t                                               : 6;
+                __IOM uint32_t ERR_RPC_REPLAYFIFO_PERR_EN              : 1; /*!< [16..16] Enable ERR_RPC_REPLAYFIFO_PERR interrupts.                 */
+                __IOM uint32_t TXB_PARITY_ERR_EN                       : 1; /*!< [17..17] Enable the TXB_PARITY_ERR interrupt.                             */
+                uint32_t                                               : 14;
+            } PCI_RC_PEIE1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PEIS1;                                 /*!< (@ 0x0000020C) PCIe Event Interrupt Status 1 Register                     */
+
+            struct
+            {
+                __IOM uint32_t ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR : 1; /*!< [0..0] ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR interrupt     */
+                __IOM uint32_t ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR : 1; /*!< [1..1] ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR interrupt     */
+                uint32_t                                            : 6;
+                __IOM uint32_t ERR_REPLAY_LOWER_CORRECTABLE_ERROR   : 1; /*!< [8..8] ERR_REPLAY_LOWER_CORRECTABLE_ERROR interrupt         */
+                __IOM uint32_t ERR_REPLAY_UPPER_CORRECTABLE_ERROR   : 1; /*!< [9..9] ERR_REPLAY_UPPER_CORRECTABLE_ERROR interrupt         */
+                uint32_t                                            : 6;
+                __IOM uint32_t ERR_RPC_REPLAYFIFO_PERR              : 1; /*!< [16..16] ERR_RPC_REPLAYFIFO_PERR interrupt                             */
+                __IOM uint32_t TXB_PARITY_ERR                       : 1; /*!< [17..17] TXB_PARITY_ERR interrupt                                         */
+                uint32_t                                            : 14;
+            } PCI_EP_PEIS1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PEIS1;                                 /*!< (@ 0x0000020C) PCIe Event Interrupt Status 1 Register                     */
+
+            struct
+            {
+                __IOM uint32_t ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR : 1; /*!< [0..0] ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR interrupt     */
+                __IOM uint32_t ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR : 1; /*!< [1..1] ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR interrupt     */
+                uint32_t                                            : 6;
+                __IOM uint32_t ERR_REPLAY_LOWER_CORRECTABLE_ERROR   : 1; /*!< [8..8] ERR_REPLAY_LOWER_CORRECTABLE_ERROR interrupt         */
+                __IOM uint32_t ERR_REPLAY_UPPER_CORRECTABLE_ERROR   : 1; /*!< [9..9] ERR_REPLAY_UPPER_CORRECTABLE_ERROR interrupt         */
+                uint32_t                                            : 6;
+                __IOM uint32_t ERR_RPC_REPLAYFIFO_PERR              : 1; /*!< [16..16] ERR_RPC_REPLAYFIFO_PERR interrupt                             */
+                __IOM uint32_t TXB_PARITY_ERR                       : 1; /*!< [17..17] TXB_PARITY_ERR interrupt                                         */
+                uint32_t                                            : 14;
+            } PCI_RC_PEIS1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AMEIE;         /*!< (@ 0x00000210) AXI Master Error Interrupt Enable Register                 */
+
+            struct
+            {
+                __IOM uint32_t RMSTERRINTEN : 4; /*!< [3..0] Read MSTERR INT Enable                                             */
+                uint32_t                    : 4;
+                __IOM uint32_t WMSTERRINTEN : 4; /*!< [11..8] Write MSTERR INT Enable                                           */
+                uint32_t                    : 20;
+            } PCI_EP_AMEIE_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AMEIE;         /*!< (@ 0x00000210) AXI Master Error Interrupt Enable Register                 */
+
+            struct
+            {
+                __IOM uint32_t RMSTERRINTEN : 4; /*!< [3..0] Read MSTERR INT Enable                                             */
+                uint32_t                    : 4;
+                __IOM uint32_t WMSTERRINTEN : 4; /*!< [11..8] Write MSTERR INT Enable                                           */
+                uint32_t                    : 20;
+            } PCI_RC_AMEIE_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AMEIS;       /*!< (@ 0x00000214) AXI Master Error Interrupt Status Register                 */
+
+            struct
+            {
+                __IOM uint32_t RMSTERRINT : 4; /*!< [3..0] Read MSTERR INT                                                    */
+                uint32_t                  : 4;
+                __IOM uint32_t WMSTERRINT : 4; /*!< [11..8] Write MSTERR INT                                                  */
+                uint32_t                  : 4;
+                __IM uint32_t RERRID      : 4; /*!< [19..16] Read ERR ID                                                      */
+                uint32_t                  : 4;
+                __IM uint32_t WERRID      : 4; /*!< [27..24] Write ERR ID                                                     */
+                uint32_t                  : 4;
+            } PCI_EP_AMEIS_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AMEIS;       /*!< (@ 0x00000214) AXI Master Error Interrupt Status Register                 */
+
+            struct
+            {
+                __IOM uint32_t RMSTERRINT : 4; /*!< [3..0] Read MSTERR INT                                                    */
+                uint32_t                  : 4;
+                __IOM uint32_t WMSTERRINT : 4; /*!< [11..8] Write MSTERR INT                                                  */
+                uint32_t                  : 4;
+                __IM uint32_t RERRID      : 4; /*!< [19..16] Read ERR ID                                                      */
+                uint32_t                  : 4;
+                __IM uint32_t WERRID      : 4; /*!< [27..24] Write ERR ID                                                     */
+                uint32_t                  : 4;
+            } PCI_RC_AMEIS_b;
+        };
+    };
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ASEIE1;        /*!< (@ 0x00000220) AXI Slave Error Interrupt Enable 1 Register                */
+
+            struct
+            {
+                __IOM uint32_t RSLVERRINTEN : 2; /*!< [1..0] Read SLVERR INT EN                                                 */
+                uint32_t                    : 6;
+                __IOM uint32_t WSLVERRINTEN : 4; /*!< [11..8] Write SLVERR INT EN                                               */
+                uint32_t                    : 20;
+            } PCI_EP_ASEIE1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ASEIE1;        /*!< (@ 0x00000220) AXI Slave Error Interrupt Enable 1 Register                */
+
+            struct
+            {
+                __IOM uint32_t RSLVERRINTEN : 2; /*!< [1..0] Read SLVERR INT EN                                                 */
+                uint32_t                    : 6;
+                __IOM uint32_t WSLVERRINTEN : 4; /*!< [11..8] Write SLVERR INT EN                                               */
+                uint32_t                    : 20;
+            } PCI_RC_ASEIE1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ASEIS1;      /*!< (@ 0x00000224) AXI Slave Error Interrupt Status 1 Register                */
+
+            struct
+            {
+                __IOM uint32_t RSLVERRINT : 2; /*!< [1..0] Read SLVERR INT                                                    */
+                uint32_t                  : 6;
+                __IOM uint32_t WSLVERRINT : 4; /*!< [11..8] Write SLVERR INT                                                  */
+                uint32_t                  : 20;
+            } PCI_EP_ASEIS1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ASEIS1;      /*!< (@ 0x00000224) AXI Slave Error Interrupt Status 1 Register                */
+
+            struct
+            {
+                __IOM uint32_t RSLVERRINT : 2; /*!< [1..0] Read SLVERR INT                                                    */
+                uint32_t                  : 6;
+                __IOM uint32_t WSLVERRINT : 4; /*!< [11..8] Write SLVERR INT                                                  */
+                uint32_t                  : 20;
+            } PCI_RC_ASEIS1_b;
+        };
+    };
+    __IM uint32_t RESERVED6[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_ASEIS3;   /*!< (@ 0x00000230) AXI Slave Error Interrupt Status 3 Register                */
+        __IM uint32_t PCI_RC_ASEIS3;   /*!< (@ 0x00000230) AXI Slave Error Interrupt Status 3 Register                */
+    };
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PEIE2;   /*!< (@ 0x00000240) PCIe Event Interrupt Enable 2 Register                     */
+
+        struct
+        {
+            uint32_t                        : 8;
+            __IOM uint32_t D3_HOT_ERR_EN    : 8; /*!< [15..8] D3_hot_err_EN                                                     */
+            __IOM uint32_t LTR_MECHANISM_EN : 1; /*!< [16..16] Interrupt enable for the ability to detect changes
+                                                  *   in CFG_LTR_MECHANISM                                                      */
+            uint32_t : 15;
+        } PCI_EP_PEIE2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PEIS2;   /*!< (@ 0x00000244) PCIe Event Interrupt Status 2 Register                     */
+
+        struct
+        {
+            uint32_t                     : 8;
+            __IOM uint32_t D3_HOT_ERR    : 8; /*!< [15..8] D3_hot_err                                                        */
+            __IOM uint32_t LTR_MECHANISM : 1; /*!< [16..16] Status to detect and notify changes in CFG_LTR_MECHANISM         */
+            uint32_t                     : 15;
+        } PCI_EP_PEIS2_b;
+    };
+    __IM uint32_t RESERVED8[46];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PERM; /*!< (@ 0x00000300) Permission Register                                        */
+
+            struct
+            {
+                uint32_t                      : 1;
+                __IOM uint32_t PHY_REG_CLK_EN : 1; /*!< [1..1] Write enable for Physical Layer Control/Status Registers.          */
+                uint32_t                      : 30;
+            } PCI_EP_PERM_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PERM; /*!< (@ 0x00000300) Permission Register                                        */
+
+            struct
+            {
+                uint32_t                      : 1;
+                __IOM uint32_t PHY_REG_CLK_EN : 1; /*!< [1..1] Write enable for Physical Layer Control/Status Registers.          */
+                __IOM uint32_t CFG_HWINIT_EN  : 1; /*!< [2..2] Enable HwInit attribute registers to be rewritten from
+                                                    *   AXI.                                                                      */
+                uint32_t : 29;
+            } PCI_RC_PERM_b;
+        };
+    };
+    __IM uint32_t RESERVED9[3];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_RESET;       /*!< (@ 0x00000310) Reset Register                                             */
+
+            struct
+            {
+                __IOM uint32_t RST_B    : 1;   /*!< [0..0] Reset to PCI Express core part inside macro                        */
+                __IOM uint32_t RST_GP_B : 1;   /*!< [1..1] Reset to the PCI Express core part (ACLK domain) inside
+                                                *   the macro                                                                 */
+                __IOM uint32_t RST_RSM_B  : 1; /*!< [2..2] POWERGOOD reset of AUX Power (AUX not supported)                   */
+                __IOM uint32_t RST_CFG_B  : 1; /*!< [3..3] Reset to Configuration Register                                    */
+                __IOM uint32_t RST_LOAD_B : 1; /*!< [4..4] Reset to Configuration Register                                    */
+                __IOM uint32_t RST_PS_B   : 1; /*!< [5..5] Reset to the PCI Express core part (PCLK domain) inside
+                                                *   the macro                                                                 */
+                __IOM uint32_t RST_OUT_B  : 1; /*!< [6..6] RST_OUT_B output                                                   */
+                __IOM uint32_t RST_PREG_B : 1; /*!< [7..7] Not used in this macro. The setting value does not affect
+                                                *   macro behavior.                                                           */
+                uint32_t            : 8;
+                __IOM uint32_t FTD0 : 1;       /*!< [16..16] force to D0                                                      */
+                uint32_t            : 15;
+            } PCI_EP_RESET_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_RESET;       /*!< (@ 0x00000310) Reset Register                                             */
+
+            struct
+            {
+                __IOM uint32_t RST_B    : 1;   /*!< [0..0] Reset to PCI Express core part inside macro                        */
+                __IOM uint32_t RST_GP_B : 1;   /*!< [1..1] Reset to the PCI Express core part (ACLK domain) inside
+                                                *   the macro                                                                 */
+                __IOM uint32_t RST_RSM_B  : 1; /*!< [2..2] POWERGOOD reset of AUX Power (AUX not supported)                   */
+                __IOM uint32_t RST_CFG_B  : 1; /*!< [3..3] Reset to Configuration Register                                    */
+                __IOM uint32_t RST_LOAD_B : 1; /*!< [4..4] Reset to Configuration Register                                    */
+                __IOM uint32_t RST_PS_B   : 1; /*!< [5..5] Reset to the PCI Express core part (PCLK domain) inside
+                                                *   the macro                                                                 */
+                __IOM uint32_t RST_OUT_B  : 1; /*!< [6..6] RST_OUT_B output                                                   */
+                __IOM uint32_t RST_PREG_B : 1; /*!< [7..7] Not used in this macro. The setting value does not affect
+                                                *   macro behavior.                                                           */
+                uint32_t            : 8;
+                __IOM uint32_t FTD0 : 1;       /*!< [16..16] force to D0                                                      */
+                uint32_t            : 15;
+            } PCI_RC_RESET_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_MSET0;      /*!< (@ 0x00000314) Mode Set 0 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t ARCACHE : 4;   /*!< [3..0] Lock type for PCIe-to-AXI transactions. This bit provides
+                                               *   information about the atomic nature of the transfer.                      */
+                __IOM uint32_t ARLOCK : 2;    /*!< [5..4] Lock type for PCIe-to-AXI transactions. This bit provides
+                                               *   information about the atomic nature of the transfer.                      */
+                uint32_t                 : 6;
+                __IOM uint32_t ARPROT    : 3; /*!< [14..12] Sets the protection type for PCIe->AXI transactions.            */
+                uint32_t                 : 1;
+                __IOM uint32_t AWCACHE_D : 4; /*!< [19..16] Indicates the value of MAWCACHE[3:0] to be issued to
+                                               *   AXI.                                                                      */
+                __IOM uint32_t AWLOCK    : 2; /*!< [21..20] Lock type for PCIe-to-AXI transactions.                          */
+                uint32_t                 : 2;
+                __IOM uint32_t AWCACHE_L : 4; /*!< [27..24] Indicates the value of MAWCACHE[3:0] to be issued to
+                                               *   AXI.                                                                      */
+                __IOM uint32_t AWPROT : 3;    /*!< [30..28] Sets the protection type for PCIe->AXI transactions.            */
+                uint32_t              : 1;
+            } PCI_EP_MSET0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_MSET0;      /*!< (@ 0x00000314) Mode Set 0 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t ARCACHE : 4;   /*!< [3..0] Lock type for PCIe-to-AXI transactions. This bit provides
+                                               *   information about the atomic nature of the transfer.                      */
+                __IOM uint32_t ARLOCK : 2;    /*!< [5..4] Lock type for PCIe-to-AXI transactions. This bit provides
+                                               *   information about the atomic nature of the transfer.                      */
+                uint32_t                 : 6;
+                __IOM uint32_t ARPROT    : 3; /*!< [14..12] Sets the protection type for PCIe->AXI transactions.            */
+                uint32_t                 : 1;
+                __IOM uint32_t AWCACHE_D : 4; /*!< [19..16] Indicates the value of MAWCACHE[3:0] to be issued to
+                                               *   AXI.                                                                      */
+                __IOM uint32_t AWLOCK    : 2; /*!< [21..20] Lock type for PCIe-to-AXI transactions.                          */
+                uint32_t                 : 2;
+                __IOM uint32_t AWCACHE_L : 4; /*!< [27..24] Indicates the value of MAWCACHE[3:0] to be issued to
+                                               *   AXI.                                                                      */
+                __IOM uint32_t AWPROT : 3;    /*!< [30..28] Sets the protection type for PCIe->AXI transactions.            */
+                uint32_t              : 1;
+            } PCI_RC_MSET0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_MSET1;   /*!< (@ 0x00000318) Mode Set 1 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIERO : 1; /*!< [0..0] PCIe Request Order                                                 */
+                __IOM uint32_t RAMPE  : 1; /*!< [1..1] RAM Parity Enable                                                  */
+                uint32_t              : 2;
+                __IOM uint32_t AXIMMB : 4; /*!< [7..4] AXI Master Max Burst                                               */
+                __IOM uint32_t AXIMIR : 4; /*!< [11..8] AXI Max Issue Read                                                */
+                __IOM uint32_t AXIMIW : 4; /*!< [15..12] AXI Max Issue Write                                              */
+                uint32_t              : 16;
+            } PCI_EP_MSET1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_MSET1;   /*!< (@ 0x00000318) Mode Set 1 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIERO : 1; /*!< [0..0] PCIe Request Order                                                 */
+                __IOM uint32_t RAMPE  : 1; /*!< [1..1] RAM Parity Enable                                                  */
+                uint32_t              : 2;
+                __IOM uint32_t AXIMMB : 4; /*!< [7..4] AXI Master Max Burst                                               */
+                __IOM uint32_t AXIMIR : 4; /*!< [11..8] AXI Max Issue Read                                                */
+                __IOM uint32_t AXIMIW : 4; /*!< [15..12] AXI Max Issue Write                                              */
+                uint32_t              : 16;
+            } PCI_RC_MSET1_b;
+        };
+    };
+    __IM uint32_t RESERVED10[25];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_MSET3;     /*!< (@ 0x00000380) Mode Set 3 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t ASPML1IT : 8; /*!< [7..0] ASPM L1 Idle Time                                                  */
+                uint32_t                : 24;
+            } PCI_EP_MSET3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_MSET3;     /*!< (@ 0x00000380) Mode Set 3 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t ASPML1IT : 8; /*!< [7..0] ASPM L1 Idle Time                                                  */
+                uint32_t                : 24;
+            } PCI_RC_MSET3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_MSET4;                    /*!< (@ 0x00000384) Mode Set 4 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t UI_EQ_REQUEST : 1;           /*!< [0..0] Set when sending an Equalization Request with Quiesce
+                                                             *   Guarantee = 1 in the Recovery.RcvrCfg state.                              */
+                __IOM uint32_t UI_EQ_REQTYPE : 2;           /*!< [2..1] Operation specification when sending Equalization Request
+                                                             *   with Quiesce Guarantee = 1 in Recovery.RcvrCfg state                      */
+                uint32_t                               : 2;
+                __IOM uint32_t MODE_EQ_AUTONOMOUS1     : 1; /*!< [5..5] Fixed 0                                                            */
+                __IOM uint32_t MODE_EQ_PHASE23_ENABLE1 : 1; /*!< [6..6] Fixed 0                                                         */
+                __IOM uint32_t MODE_8GT_EQTS2          : 1; /*!< [7..7] 8GT EQ TS2OS transmission enable/disable setting for
+                                                             *   Upstream Port                                                             */
+                uint32_t                            : 4;
+                __IOM uint32_t MODE_EQ_RX_EVAL_WAIT : 20;   /*!< [31..12] During RxEval (Downstream Port Phase3, Upstream Port
+                                                             *  Phase2), wait time setting until RxEval is executed when
+                                                             *  Block Alignment cannot be obtained.                                       */
+            } PCI_EP_MSET4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_MSET4;                    /*!< (@ 0x00000384) Mode Set 4 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t UI_EQ_REQUEST : 1;           /*!< [0..0] Set when sending an Equalization Request with Quiesce
+                                                             *   Guarantee = 1 in the Recovery.RcvrCfg state.                              */
+                __IOM uint32_t UI_EQ_REQTYPE : 2;           /*!< [2..1] Operation specification when sending Equalization Request
+                                                             *   with Quiesce Guarantee = 1 in Recovery.RcvrCfg state                      */
+                uint32_t                               : 2;
+                __IOM uint32_t MODE_EQ_AUTONOMOUS1     : 1; /*!< [5..5] Fixed 0                                                            */
+                __IOM uint32_t MODE_EQ_PHASE23_ENABLE1 : 1; /*!< [6..6] Fixed 0                                                         */
+                __IOM uint32_t MODE_8GT_EQTS2          : 1; /*!< [7..7] 8GT EQ TS2OS transmission enable/disable setting for
+                                                             *   Upstream Port                                                             */
+                uint32_t                            : 4;
+                __IOM uint32_t MODE_EQ_RX_EVAL_WAIT : 20;   /*!< [31..12] During RxEval (Downstream Port Phase3, Upstream Port
+                                                             *  Phase2), wait time setting until RxEval is executed when
+                                                             *  Block Alignment cannot be obtained.                                       */
+            } PCI_RC_MSET4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_MSET5;                   /*!< (@ 0x00000388) Mode Set 5 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t MODE_8GT_EQTS2_PRESET : 16; /*!< [15..0] Transmitter Preset value of 8GT EQ TS2OS to transmit
+                                                            * at Upstream Port (USP).                                                   */
+                uint32_t : 16;
+            } PCI_EP_MSET5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_MSET5;                   /*!< (@ 0x00000388) Mode Set 5 Register                                        */
+
+            struct
+            {
+                __IOM uint32_t MODE_8GT_EQTS2_PRESET : 16; /*!< [15..0] Transmitter Preset value of 8GT EQ TS2OS to transmit
+                                                            * at Upstream Port (USP).                                                   */
+                uint32_t : 16;
+            } PCI_RC_MSET5_b;
+        };
+    };
+    __IM uint32_t RESERVED11;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_MSTAT0;         /*!< (@ 0x00000390) Mode Status 0 Register                                     */
+
+            struct
+            {
+                __IM uint32_t UI_EQ_DONE : 1;    /*!< [0..0] Set Equalization Request with Quiesce Guarantee=1 in
+                                                  *   Recovery .RcvrCfg state when sending                                      */
+                __IM uint32_t RX_EQ_REQUEST : 1; /*!< [1..1] Status display when receiving 8 consecutive TS2OS with
+                                                  *   Request Equalization bit (Symbol6, bit7) = 1 in Recovery.RcvrCfg
+                                                  *   state                                                                     */
+                __IM uint32_t RX_EQ_REQTYPE : 2; /*!< [3..2] Quiesce Guarantee and Equalization Request Data Rate
+                                                  *   bit display when receiv ing 8 consecutive TS2OS with Request
+                                                  *   Equalization bit (Symbol6, bit7) = 1 in Recovery.RcvrCfg
+                                                  *   state                                                                     */
+                uint32_t : 28;
+            } PCI_EP_MSTAT0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_MSTAT0;         /*!< (@ 0x00000390) Mode Status 0 Register                                     */
+
+            struct
+            {
+                __IM uint32_t UI_EQ_DONE : 1;    /*!< [0..0] Set Equalization Request with Quiesce Guarantee=1 in
+                                                  *   Recovery .RcvrCfg state when sending                                      */
+                __IM uint32_t RX_EQ_REQUEST : 1; /*!< [1..1] Status display when receiving 8 consecutive TS2OS with
+                                                  *   Request Equalization bit (Symbol6, bit7) = 1 in Recovery.RcvrCfg
+                                                  *   state                                                                     */
+                __IM uint32_t RX_EQ_REQTYPE : 2; /*!< [3..2] Quiesce Guarantee and Equalization Request Data Rate
+                                                  *   bit display when receiv ing 8 consecutive TS2OS with Request
+                                                  *   Equalization bit (Symbol6, bit7) = 1 in Recovery.RcvrCfg
+                                                  *   state                                                                     */
+                uint32_t : 28;
+            } PCI_RC_MSTAT0_b;
+        };
+    };
+    __IM uint32_t RESERVED12[27];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PCMSET1; /*!< (@ 0x00000400) PCIe Core Mode Set 1 Register                              */
+
+            struct
+            {
+                uint32_t                                  : 1;
+                __IOM uint32_t MODE_PORT                  : 1;                /*!< [1..1] Device type setting register.                                      */
+                uint32_t                                  : 6;
+                __IOM uint32_t MODE_SELECTABLE_DEEMPHASIS : 1;                /*!< [8..8] For Endpoint, set the De-emphasis value for 5.0 GT/s
+                                                                               * operation. Initial value of select_deemphasis variable
+                                                                               * described in PCIe Base Spec.                                              */
+                uint32_t                                                 : 1;
+                __IOM uint32_t MODE_TXSWING                              : 1; /*!< [10..10] SerDes serial output amplitude control                           */
+                uint32_t                                                 : 1;
+                __IOM uint32_t MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED : 1; /*!< [12..12] Setting of Link Upconfigure Capability bit of Training
+                                                                               * Sequence Ordered-set (TS-OS)                                              */
+                uint32_t                             : 3;
+                __IOM uint32_t ASPM_L1_INTERVAL_TIME : 12;                    /*!< [27..16] Interval settings for ASPM L1 requests                         */
+                uint32_t                             : 4;
+            } PCI_EP_PCMSET1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PCMSET1; /*!< (@ 0x00000400) PCIe Core Mode Set 1 Register                              */
+
+            struct
+            {
+                uint32_t                                                 : 1;
+                __IOM uint32_t MODE_PORT                                 : 1; /*!< [1..1] Device type setting register.                                      */
+                uint32_t                                                 : 8;
+                __IOM uint32_t MODE_TXSWING                              : 1; /*!< [10..10] SerDes serial output amplitude control                           */
+                uint32_t                                                 : 1;
+                __IOM uint32_t MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED : 1; /*!< [12..12] Setting of Link Upconfigure Capability bit of Training
+                                                                               * Sequence Ordered-set (TS-OS)                                              */
+                uint32_t                             : 3;
+                __IOM uint32_t ASPM_L1_INTERVAL_TIME : 12;                    /*!< [27..16] Interval settings for ASPM L1 requests                         */
+                uint32_t                             : 4;
+            } PCI_RC_PCMSET1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PCCTRL1; /*!< (@ 0x00000404) PCIe Core Control 1 Register                               */
+
+            struct
+            {
+                uint32_t                                    : 8;
+                __IOM uint32_t MODE_RESET_EIEOS_INTERVALL0S : 1; /*!< [8..8] Gen3 features:                                             */
+                __IOM uint32_t MODE_EQ_PHASE23_ENABLE       : 1; /*!< [9..9] Gen3 features:                                                   */
+                __IOM uint32_t MODE_EQ_AUTONOMOUS           : 1; /*!< [10..10] Gen3 feature: Autonomous Equalization                            */
+                __IOM uint32_t UI_ENTER_TXMODE_SRIS         : 1; /*!< [11..11] Setting Clock Tolerance Compensation                             */
+                __IOM uint32_t MODE_QUIESCE_GUARANTEE       : 1; /*!< [12..12] Symbol6 bit6 Quiesce Guarantee control bit of TS2OS            */
+                uint32_t                                    : 3;
+                __IOM uint32_t UI_ENTER_TXL0S               : 1; /*!< [16..16] TxL0s transition control                                         */
+                uint32_t                                    : 4;
+                __IOM uint32_t UI_ENTER_L1_STATUS           : 1; /*!< [21..21] L1 transition status                                             */
+                __IOM uint32_t UI_ENTER_L1S                 : 1; /*!< [22..22] L1SubState transition permission setting                         */
+                uint32_t                                    : 5;
+                __IOM uint32_t BLB_RELAX_ORDERING_EN        : 1; /*!< [28..28] Control of RO bit of Request to be sent                         */
+                uint32_t                                    : 3;
+            } PCI_EP_PCCTRL1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PCCTRL1; /*!< (@ 0x00000404) PCIe Core Control 1 Register                               */
+
+            struct
+            {
+                uint32_t                                    : 8;
+                __IOM uint32_t MODE_RESET_EIEOS_INTERVALL0S : 1; /*!< [8..8] Gen3 features:                                             */
+                __IOM uint32_t MODE_EQ_PHASE23_ENABLE       : 1; /*!< [9..9] Gen3 features:                                                   */
+                __IOM uint32_t MODE_EQ_AUTONOMOUS           : 1; /*!< [10..10] Gen3 feature: Autonomous Equalization                            */
+                __IOM uint32_t UI_ENTER_TXMODE_SRIS         : 1; /*!< [11..11] Setting Clock Tolerance Compensation                             */
+                __IOM uint32_t MODE_QUIESCE_GUARANTEE       : 1; /*!< [12..12] Symbol6 bit6 Quiesce Guarantee control bit of TS2OS            */
+                uint32_t                                    : 3;
+                __IOM uint32_t UI_ENTER_TXL0S               : 1; /*!< [16..16] TxL0s transition control                                         */
+                __IOM uint32_t UI_ENTER_L2                  : 1; /*!< [17..17] RC mode L2 transition control                                    */
+                __IOM uint32_t APMASN                       : 1; /*!< [18..18] Auto PM_Active_State_Nak                                         */
+                __IOM uint32_t UI_RC_REJECT_ASPML1          : 1; /*!< [19..19] ASPM L1 transition rejection control                             */
+                __IOM uint32_t RETURN_TO_L0                 : 1; /*!< [20..20] RC mode L1, L2 state to L0 state control (usually not
+                                                                  *   used)                                                                     */
+                uint32_t                             : 1;
+                __IOM uint32_t UI_ENTER_L1S          : 1;        /*!< [22..22] L1SubState transition permission setting                         */
+                uint32_t                             : 5;
+                __IOM uint32_t BLB_RELAX_ORDERING_EN : 1;        /*!< [28..28] Control of RO bit of Request to be sent                         */
+                uint32_t                             : 3;
+            } PCI_RC_PCCTRL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PCSTAT1;                        /*!< (@ 0x00000408) PCIe Core Status 1 Register                                */
+
+            struct
+            {
+                __IM uint32_t DLDS                          : 1; /*!< [0..0] DL_Down status                                                     */
+                __IM uint32_t STATE_VC0_NEGOTIATION_PENDING : 1; /*!< [1..1] Flow Control initialization operation monitor             */
+                uint32_t                                    : 2;
+                __IM uint32_t PMU_LINKSTATE                 : 4; /*!< [7..4] L-state monitor of power management control unit                   */
+                __IM uint32_t LTSSM_STATE                   : 7; /*!< [14..8] Indicates the state of the Link Training & Status State
+                                                                  *   Machine in the PCIe Core Link.                                            */
+                uint32_t                         : 2;
+                __IM uint32_t BD                 : 1;            /*!< [17..17] bme_down                                                         */
+                uint32_t                         : 8;
+                __IM uint32_t TURN_OFF_EVENT     : 1;            /*!< [26..26] TURN_OFF_EVENT                                                   */
+                __IM uint32_t TURN_OFF_EVENT_ACK : 1;            /*!< [27..27] TURN_OFF_EVENT_ACK                                               */
+                uint32_t                         : 4;
+            } PCI_EP_PCSTAT1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PCSTAT1;                        /*!< (@ 0x00000408) PCIe Core Status 1 Register                                */
+
+            struct
+            {
+                __IM uint32_t DLDS                          : 1; /*!< [0..0] DL_Down status                                                     */
+                __IM uint32_t STATE_VC0_NEGOTIATION_PENDING : 1; /*!< [1..1] Flow Control initialization operation monitor             */
+                uint32_t                                    : 2;
+                __IM uint32_t PMU_LINKSTATE                 : 4; /*!< [7..4] L-state monitor of power management control unit                   */
+                __IM uint32_t LTSSM_STATE                   : 7; /*!< [14..8] Indicates the state of the Link Training & Status State
+                                                                  *   Machine in the PCIe Core Link.                                            */
+                uint32_t         : 2;
+                __IM uint32_t BD : 1;                            /*!< [17..17] bme_down                                                         */
+                uint32_t         : 14;
+            } PCI_RC_PCSTAT1_b;
+        };
+    };
+    __IM uint32_t RESERVED13;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PCCTRL2;                      /*!< (@ 0x00000410) PCIe Core Control 2 Register                               */
+
+            struct
+            {
+                __IOM uint32_t UI_LINK_SPEED_CHANGE_REQ    : 1; /*!< [0..0] Link Speed change request control                              */
+                uint32_t                                   : 3;
+                __IOM uint32_t UI_LINK_CHANGE_AUTONOMOUS   : 1; /*!< [4..4] Link Width/Speed change reason setting                        */
+                uint32_t                                   : 3;
+                __IOM uint32_t UI_LINK_SPEED_CHANGE        : 2; /*!< [9..8] Link speed setting                                                 */
+                uint32_t                                   : 6;
+                __IOM uint32_t UI_LINK_WIDTH_CHANGE_REQ    : 1; /*!< [16..16] Link Width change request control                            */
+                __IOM uint32_t MODE_PRESET_ENABLE          : 5; /*!< [21..17] Reduced Swing mode setting for Gen3 operation                    */
+                __IOM uint32_t MODE_NODEEMPHASIS           : 2; /*!< [23..22] No de-emphasis mode setting for Gen1/Gen3 operation              */
+                __IOM uint32_t UI_LINK_WIDTH_CHANGE_ENABLE : 8; /*!< [31..24] Link Width setting to change                              */
+            } PCI_EP_PCCTRL2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PCCTRL2;                      /*!< (@ 0x00000410) PCIe Core Control 2 Register                               */
+
+            struct
+            {
+                __IOM uint32_t UI_LINK_SPEED_CHANGE_REQ    : 1; /*!< [0..0] Link Speed change request control                              */
+                uint32_t                                   : 3;
+                __IOM uint32_t UI_LINK_CHANGE_AUTONOMOUS   : 1; /*!< [4..4] Link Width/Speed change reason setting                        */
+                uint32_t                                   : 3;
+                __IOM uint32_t UI_LINK_SPEED_CHANGE        : 2; /*!< [9..8] Link speed setting                                                 */
+                uint32_t                                   : 6;
+                __IOM uint32_t UI_LINK_WIDTH_CHANGE_REQ    : 1; /*!< [16..16] Link Width change request control                            */
+                __IOM uint32_t MODE_PRESET_ENABLE          : 5; /*!< [21..17] Reduced Swing mode setting for Gen3 operation                    */
+                __IOM uint32_t MODE_NODEEMPHASIS           : 2; /*!< [23..22] No de-emphasis mode setting for Gen1/Gen2 operation              */
+                __IOM uint32_t UI_LINK_WIDTH_CHANGE_ENABLE : 8; /*!< [31..24] Link Width setting to change                              */
+            } PCI_RC_PCCTRL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PCSTAT2;                              /*!< (@ 0x00000414) PCIe Core Status 2 Register                                */
+
+            struct
+            {
+                __IM uint32_t STATE_DATA_RATE_IDENTIFIER_RECEIVED : 8; /*!< [7..0] Link Speed display supported by the opposite device */
+                __IM uint32_t STATE_RECEIVER_DETECTED             : 8; /*!< [15..8] Connection status display with other device                    */
+                __IM uint32_t STATE_NEGOTIATED_LANE_START         : 3; /*!< [18..16] Displays the position of Lane Number 0 after Link Negotiation
+                                                                        * with the opposite device during n-lane operation.                         */
+                uint32_t                                : 1;
+                __IM uint32_t STATE_NEGOTIATED_LANE_END : 3;           /*!< [22..20] Displays the position of Lane Number (n-1) (meaning
+                                                                        * Lane 1 when n=2) after Link Negotiation with the opposite
+                                                                        * device during n-lane operation.                                           */
+                uint32_t                                : 1;
+                __IM uint32_t STATE_UPCONFIGURE_CAPABLE : 1;           /*!< [24..24] Upconfigure Capable bit display of opposite device          */
+                uint32_t                                : 3;
+                __IM uint32_t UI_LINK_SPEED_CHANGE_DONE : 1;           /*!< [28..28] Link Speed Change operation complete display                */
+                __IM uint32_t UI_LINK_WIDTH_CHANGE_DONE : 1;           /*!< [29..29] Link Width Change operation complete display                */
+                uint32_t                                : 2;
+            } PCI_EP_PCSTAT2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PCSTAT2;                              /*!< (@ 0x00000414) PCIe Core Status 2 Register                                */
+
+            struct
+            {
+                __IM uint32_t STATE_DATA_RATE_IDENTIFIER_RECEIVED : 8; /*!< [7..0] Link Speed display supported by the opposite device */
+                __IM uint32_t STATE_RECEIVER_DETECTED             : 8; /*!< [15..8] Connection status display with other device                    */
+                __IM uint32_t STATE_NEGOTIATED_LANE_START         : 3; /*!< [18..16] Displays the position of Lane Number 0 after Link Negotiation
+                                                                        * with the opposite device during n-lane operation.                         */
+                uint32_t                                : 1;
+                __IM uint32_t STATE_NEGOTIATED_LANE_END : 3;           /*!< [22..20] Displays the position of Lane Number (n-1) (meaning
+                                                                        * Lane 1 when n=2) after Link Negotiation with the opposite
+                                                                        * device during n-lane operation.                                           */
+                uint32_t                                : 1;
+                __IM uint32_t STATE_UPCONFIGURE_CAPABLE : 1;           /*!< [24..24] Upconfigure Capable bit display of opposite device          */
+                uint32_t                                : 3;
+                __IM uint32_t UI_LINK_SPEED_CHANGE_DONE : 1;           /*!< [28..28] Link Speed Change operation complete display                */
+                __IM uint32_t UI_LINK_WIDTH_CHANGE_DONE : 1;           /*!< [29..29] Link Width Change operation complete display                */
+                uint32_t                                : 2;
+            } PCI_RC_PCSTAT2_b;
+        };
+    };
+    __IM uint32_t RESERVED14[5];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PCSTAT5;                  /*!< (@ 0x0000042C) PCIe Core Status 5 Register                                */
+
+            struct
+            {
+                __IM uint32_t ORT_TRANSACTION_PENDING : 8; /*!< [7..0] Outstanding Request Monitor by Function                         */
+                __IM uint32_t D3_EVENT_ACK            : 8; /*!< [15..8] D3_EVENT_ACK signal monitor for each function                     */
+                __IM uint32_t D3_EVENT                : 8; /*!< [23..16] D3_EVENT signal monitor for each function                        */
+                __IM uint32_t SBME                    : 8; /*!< [31..24] Suspend_bme                                                      */
+            } PCI_EP_PCSTAT5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PCSTAT5;                  /*!< (@ 0x0000042C) PCIe Core Status 5 Register                                */
+
+            struct
+            {
+                __IM uint32_t ORT_TRANSACTION_PENDING : 2; /*!< [1..0] Indicates whether or not there are Outstanding Requests
+                                                            * (a state in which all Completions corresponding to Non-Posted
+                                                            * Requests sent from the AXI side have not been received).                  */
+                uint32_t : 30;
+            } PCI_RC_PCSTAT5_b;
+        };
+    };
+    __IM uint32_t RESERVED15[40];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMAINTVEC0;      /*!< (@ 0x000004D0) DMA Interrupt Vector 0 Register                            */
+
+            struct
+            {
+                __IOM uint32_t DMA_CH0_V      : 5; /*!< [4..0] Vector value of MSI interrupt transmitted by DMAC Ch0              */
+                __IOM uint32_t DMA_CH0_MSI_EN : 1; /*!< [5..5] DMA Ch0 MSI Enable                                                 */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH1_V      : 5; /*!< [12..8] Vector value of MSI interrupt transmitted by DMAC Ch1             */
+                __IOM uint32_t DMA_CH1_MSI_EN : 1; /*!< [13..13] DMA Ch1 MSI Enable                                               */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH2_V      : 5; /*!< [20..16] Vector value of MSI interrupt transmitted by DMAC Ch2            */
+                __IOM uint32_t DMA_CH2_MSI_EN : 1; /*!< [21..21] DMA Ch2 MSI Enable                                               */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH3_V      : 5; /*!< [28..24] Vector value of MSI interrupt transmitted by DMAC Ch3            */
+                __IOM uint32_t DMA_CH3_MSI_EN : 1; /*!< [29..29] DMA Ch3 MSI Enable                                               */
+                uint32_t                      : 2;
+            } PCI_EP_DMAINTVEC0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMAINTVEC0;      /*!< (@ 0x000004D0) DMA Interrupt Vector 0 Register                            */
+
+            struct
+            {
+                __IOM uint32_t DMA_CH0_V      : 5; /*!< [4..0] Vector value of MSI interrupt transmitted by DMAC Ch0              */
+                __IOM uint32_t DMA_CH0_MSI_EN : 1; /*!< [5..5] DMA Ch0 MSI Enable                                                 */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH1_V      : 5; /*!< [12..8] Vector value of MSI interrupt transmitted by DMAC Ch1             */
+                __IOM uint32_t DMA_CH1_MSI_EN : 1; /*!< [13..13] DMA Ch1 MSI Enable                                               */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH2_V      : 5; /*!< [20..16] Vector value of MSI interrupt transmitted by DMAC Ch2            */
+                __IOM uint32_t DMA_CH2_MSI_EN : 1; /*!< [21..21] DMA Ch2 MSI Enable                                               */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH3_V      : 5; /*!< [28..24] Vector value of MSI interrupt transmitted by DMAC Ch3            */
+                __IOM uint32_t DMA_CH3_MSI_EN : 1; /*!< [29..29] DMA Ch3 MSI Enable                                               */
+                uint32_t                      : 2;
+            } PCI_RC_DMAINTVEC0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMAINTVEC1;      /*!< (@ 0x000004D4) DMA Interrupt Vector 1 Register                            */
+
+            struct
+            {
+                __IOM uint32_t DMA_CH4_V      : 5; /*!< [4..0] Vector value of MSI interrupt transmitted by DMAC Ch4              */
+                __IOM uint32_t DMA_CH4_MSI_EN : 1; /*!< [5..5] DMA Ch4 MSI Enable                                                 */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH5_V      : 5; /*!< [12..8] Vector value of MSI interrupt transmitted by DMAC Ch5             */
+                __IOM uint32_t DMA_CH5_MSI_EN : 1; /*!< [13..13] DMA Ch5 MSI Enable                                               */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH6_V      : 5; /*!< [20..16] Vector value of MSI interrupt transmitted by DMAC Ch6            */
+                __IOM uint32_t DMA_CH6_MSI_EN : 1; /*!< [21..21] DMA Ch6 MSI Enable                                               */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH7_V      : 5; /*!< [28..24] Vector value of MSI interrupt transmitted by DMAC Ch7            */
+                __IOM uint32_t DMA_CH7_MSI_EN : 1; /*!< [29..29] DMA Ch7 MSI Enable                                               */
+                uint32_t                      : 2;
+            } PCI_EP_DMAINTVEC1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMAINTVEC1;      /*!< (@ 0x000004D4) DMA Interrupt Vector 1 Register                            */
+
+            struct
+            {
+                __IOM uint32_t DMA_CH4_V      : 5; /*!< [4..0] Vector value of MSI interrupt transmitted by DMAC Ch4              */
+                __IOM uint32_t DMA_CH4_MSI_EN : 1; /*!< [5..5] DMA Ch4 MSI Enable                                                 */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH5_V      : 5; /*!< [12..8] Vector value of MSI interrupt transmitted by DMAC Ch5             */
+                __IOM uint32_t DMA_CH5_MSI_EN : 1; /*!< [13..13] DMA Ch5 MSI Enable                                               */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH6_V      : 5; /*!< [20..16] Vector value of MSI interrupt transmitted by DMAC Ch6            */
+                __IOM uint32_t DMA_CH6_MSI_EN : 1; /*!< [21..21] DMA Ch6 MSI Enable                                               */
+                uint32_t                      : 2;
+                __IOM uint32_t DMA_CH7_V      : 5; /*!< [28..24] Vector value of MSI interrupt transmitted by DMAC Ch7            */
+                __IOM uint32_t DMA_CH7_MSI_EN : 1; /*!< [29..29] DMA Ch7 MSI Enable                                               */
+                uint32_t                      : 2;
+            } PCI_RC_DMAINTVEC1_b;
+        };
+    };
+    __IM uint32_t RESERVED16[74];
+    __IOM R_PCIE0_PCI_RC_MSIRCV_Type PCI_RC_MSIRCV[16]; /*!< (@ 0x00000600) [0..15]                                               */
+    __IM uint32_t RESERVED17[64];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACTRL; /*!< (@ 0x00000800) DMAC Control Register                                      */
+
+            struct
+            {
+                __IOM uint32_t D_PMRS : 3; /*!< [2..0] DMAC PCIe Max Read Request Size                                    */
+                uint32_t              : 29;
+            } PCI_EP_DMACTRL_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACTRL; /*!< (@ 0x00000800) DMAC Control Register                                      */
+
+            struct
+            {
+                __IOM uint32_t D_PMRS : 3; /*!< [2..0] DMAC PCIe Max Read Request Size                                    */
+                uint32_t              : 29;
+            } PCI_RC_DMACTRL_b;
+        };
+    };
+    __IM uint32_t RESERVED18;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMAINTE;         /*!< (@ 0x00000808) DMAC Interrupt Enable Register                             */
+
+            struct
+            {
+                __IOM uint32_t CH0_END_EN     : 1; /*!< [0..0] CH0 Completion Interrupt Enable                                    */
+                __IOM uint32_t CH0_STOP_EN    : 1; /*!< [1..1] CH0 Stop Interrupt Enable                                          */
+                __IOM uint32_t CH0_QUE_EMP_EN : 1; /*!< [2..2] CH0 Que Empty Interrupt Enable                                     */
+                __IOM uint32_t CH0_ERR_EN     : 1; /*!< [3..3] CH0 Error Interrupt Enable                                         */
+                __IOM uint32_t CH1_END_EN     : 1; /*!< [4..4] CH1 Completion Interrupt Enable                                    */
+                __IOM uint32_t CH1_STOP_EN    : 1; /*!< [5..5] CH1 Stop Interrupt Enable                                          */
+                __IOM uint32_t CH1_QUE_EMP_EN : 1; /*!< [6..6] CH1 Que Empty Interrupt Enable                                     */
+                __IOM uint32_t CH1_ERR_EN     : 1; /*!< [7..7] CH1 Error Interrupt Enable                                         */
+                __IOM uint32_t CH2_END_EN     : 1; /*!< [8..8] CH2 Completion Interrupt Enable                                    */
+                __IOM uint32_t CH2_STOP_EN    : 1; /*!< [9..9] CH2 Stop Interrupt Enable                                          */
+                __IOM uint32_t CH2_QUE_EMP_EN : 1; /*!< [10..10] CH2 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH2_ERR_EN     : 1; /*!< [11..11] CH2 Error Interrupt Enable                                       */
+                __IOM uint32_t CH3_END_EN     : 1; /*!< [12..12] CH3 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH3_STOP_EN    : 1; /*!< [13..13] CH3 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH3_QUE_EMP_EN : 1; /*!< [14..14] CH3 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH3_ERR_EN     : 1; /*!< [15..15] CH3 Error Interrupt Enable                                       */
+                __IOM uint32_t CH4_END_EN     : 1; /*!< [16..16] CH4 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH4_STOP_EN    : 1; /*!< [17..17] CH4 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH4_QUE_EMP_EN : 1; /*!< [18..18] CH4 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH4_ERR_EN     : 1; /*!< [19..19] CH4 Error Interrupt Enable                                       */
+                __IOM uint32_t CH5_END_EN     : 1; /*!< [20..20] CH5 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH5_STOP_EN    : 1; /*!< [21..21] CH5 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH5_QUE_EMP_EN : 1; /*!< [22..22] CH5 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH5_ERR_EN     : 1; /*!< [23..23] CH5 Error Interrupt Enable                                       */
+                __IOM uint32_t CH6_END_EN     : 1; /*!< [24..24] CH6 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH6_STOP_EN    : 1; /*!< [25..25] CH6 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH6_QUE_EMP_EN : 1; /*!< [26..26] CH6 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH6_ERR_EN     : 1; /*!< [27..27] CH6 Error Interrupt Enable                                       */
+                __IOM uint32_t CH7_END_EN     : 1; /*!< [28..28] CH7 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH7_STOP_EN    : 1; /*!< [29..29] CH7 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH7_QUE_EMP_EN : 1; /*!< [30..30] CH7 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH7_ERR_EN     : 1; /*!< [31..31] CH7 Error Interrupt Enable                                       */
+            } PCI_EP_DMAINTE_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMAINTE;         /*!< (@ 0x00000808) DMAC Interrupt Enable Register                             */
+
+            struct
+            {
+                __IOM uint32_t CH0_END_EN     : 1; /*!< [0..0] CH0 Completion Interrupt Enable                                    */
+                __IOM uint32_t CH0_STOP_EN    : 1; /*!< [1..1] CH0 Stop Interrupt Enable                                          */
+                __IOM uint32_t CH0_QUE_EMP_EN : 1; /*!< [2..2] CH0 Que Empty Interrupt Enable                                     */
+                __IOM uint32_t CH0_ERR_EN     : 1; /*!< [3..3] CH0 Error Interrupt Enable                                         */
+                __IOM uint32_t CH1_END_EN     : 1; /*!< [4..4] CH1 Completion Interrupt Enable                                    */
+                __IOM uint32_t CH1_STOP_EN    : 1; /*!< [5..5] CH1 Stop Interrupt Enable                                          */
+                __IOM uint32_t CH1_QUE_EMP_EN : 1; /*!< [6..6] CH1 Que Empty Interrupt Enable                                     */
+                __IOM uint32_t CH1_ERR_EN     : 1; /*!< [7..7] CH1 Error Interrupt Enable                                         */
+                __IOM uint32_t CH2_END_EN     : 1; /*!< [8..8] CH2 Completion Interrupt Enable                                    */
+                __IOM uint32_t CH2_STOP_EN    : 1; /*!< [9..9] CH2 Stop Interrupt Enable                                          */
+                __IOM uint32_t CH2_QUE_EMP_EN : 1; /*!< [10..10] CH2 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH2_ERR_EN     : 1; /*!< [11..11] CH2 Error Interrupt Enable                                       */
+                __IOM uint32_t CH3_END_EN     : 1; /*!< [12..12] CH3 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH3_STOP_EN    : 1; /*!< [13..13] CH3 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH3_QUE_EMP_EN : 1; /*!< [14..14] CH3 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH3_ERR_EN     : 1; /*!< [15..15] CH3 Error Interrupt Enable                                       */
+                __IOM uint32_t CH4_END_EN     : 1; /*!< [16..16] CH4 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH4_STOP_EN    : 1; /*!< [17..17] CH4 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH4_QUE_EMP_EN : 1; /*!< [18..18] CH4 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH4_ERR_EN     : 1; /*!< [19..19] CH4 Error Interrupt Enable                                       */
+                __IOM uint32_t CH5_END_EN     : 1; /*!< [20..20] CH5 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH5_STOP_EN    : 1; /*!< [21..21] CH5 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH5_QUE_EMP_EN : 1; /*!< [22..22] CH5 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH5_ERR_EN     : 1; /*!< [23..23] CH5 Error Interrupt Enable                                       */
+                __IOM uint32_t CH6_END_EN     : 1; /*!< [24..24] CH6 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH6_STOP_EN    : 1; /*!< [25..25] CH6 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH6_QUE_EMP_EN : 1; /*!< [26..26] CH6 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH6_ERR_EN     : 1; /*!< [27..27] CH6 Error Interrupt Enable                                       */
+                __IOM uint32_t CH7_END_EN     : 1; /*!< [28..28] CH7 Completion Interrupt Enable                                  */
+                __IOM uint32_t CH7_STOP_EN    : 1; /*!< [29..29] CH7 Stop Interrupt Enable                                        */
+                __IOM uint32_t CH7_QUE_EMP_EN : 1; /*!< [30..30] CH7 Que Empty Interrupt Enable                                   */
+                __IOM uint32_t CH7_ERR_EN     : 1; /*!< [31..31] CH7 Error Interrupt Enable                                       */
+            } PCI_RC_DMAINTE_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMAINTS;      /*!< (@ 0x0000080C) DMAC Interrupt Status Register                             */
+
+            struct
+            {
+                __IOM uint32_t CH0_END     : 1; /*!< [0..0] Set when the DMAC ends normally.                                   */
+                __IOM uint32_t CH0_STOP    : 1; /*!< [1..1] Set when the DMAC is prematurely stopped.                          */
+                __IOM uint32_t CH0_QUE_EMP : 1; /*!< [2..2] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH0_ERR     : 1; /*!< [3..3] Set when an error occurs during DMA transfer.                      */
+                __IOM uint32_t CH1_END     : 1; /*!< [4..4] Set when the DMAC ends normally.                                   */
+                __IOM uint32_t CH1_STOP    : 1; /*!< [5..5] Set when the DMAC is prematurely stopped.                          */
+                __IOM uint32_t CH1_QUE_EMP : 1; /*!< [6..6] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH1_ERR     : 1; /*!< [7..7] Set when an error occurs during DMA transfer.                      */
+                __IOM uint32_t CH2_END     : 1; /*!< [8..8] Set when the DMAC ends normally.                                   */
+                __IOM uint32_t CH2_STOP    : 1; /*!< [9..9] Set when the DMAC is prematurely stopped.                          */
+                __IOM uint32_t CH2_QUE_EMP : 1; /*!< [10..10] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH2_ERR     : 1; /*!< [11..11] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH3_END     : 1; /*!< [12..12] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH3_STOP    : 1; /*!< [13..13] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH3_QUE_EMP : 1; /*!< [14..14] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH3_ERR     : 1; /*!< [15..15] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH4_END     : 1; /*!< [16..16] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH4_STOP    : 1; /*!< [17..17] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH4_QUE_EMP : 1; /*!< [18..18] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH4_ERR     : 1; /*!< [19..19] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH5_END     : 1; /*!< [20..20] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH5_STOP    : 1; /*!< [21..21] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH5_QUE_EMP : 1; /*!< [22..22] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH5_ERR     : 1; /*!< [23..23] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH6_END     : 1; /*!< [24..24] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH6_STOP    : 1; /*!< [25..25] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH6_QUE_EMP : 1; /*!< [26..26] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH6_ERR     : 1; /*!< [27..27] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH7_END     : 1; /*!< [28..28] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH7_STOP    : 1; /*!< [29..29] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH7_QUE_EMP : 1; /*!< [30..30] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH7_ERR : 1;     /*!< [31..31] Set when an error occurs during DMA transfer.                    */
+            } PCI_EP_DMAINTS_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMAINTS;      /*!< (@ 0x0000080C) DMAC Interrupt Status Register                             */
+
+            struct
+            {
+                __IOM uint32_t CH0_END     : 1; /*!< [0..0] Set when the DMAC ends normally.                                   */
+                __IOM uint32_t CH0_STOP    : 1; /*!< [1..1] Set when the DMAC is prematurely stopped.                          */
+                __IOM uint32_t CH0_QUE_EMP : 1; /*!< [2..2] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH0_ERR     : 1; /*!< [3..3] Set when an error occurs during DMA transfer.                      */
+                __IOM uint32_t CH1_END     : 1; /*!< [4..4] Set when the DMAC ends normally.                                   */
+                __IOM uint32_t CH1_STOP    : 1; /*!< [5..5] Set when the DMAC is prematurely stopped.                          */
+                __IOM uint32_t CH1_QUE_EMP : 1; /*!< [6..6] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH1_ERR     : 1; /*!< [7..7] Set when an error occurs during DMA transfer.                      */
+                __IOM uint32_t CH2_END     : 1; /*!< [8..8] Set when the DMAC ends normally.                                   */
+                __IOM uint32_t CH2_STOP    : 1; /*!< [9..9] Set when the DMAC is prematurely stopped.                          */
+                __IOM uint32_t CH2_QUE_EMP : 1; /*!< [10..10] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH2_ERR     : 1; /*!< [11..11] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH3_END     : 1; /*!< [12..12] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH3_STOP    : 1; /*!< [13..13] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH3_QUE_EMP : 1; /*!< [14..14] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH3_ERR     : 1; /*!< [15..15] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH4_END     : 1; /*!< [16..16] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH4_STOP    : 1; /*!< [17..17] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH4_QUE_EMP : 1; /*!< [18..18] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH4_ERR     : 1; /*!< [19..19] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH5_END     : 1; /*!< [20..20] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH5_STOP    : 1; /*!< [21..21] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH5_QUE_EMP : 1; /*!< [22..22] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH5_ERR     : 1; /*!< [23..23] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH6_END     : 1; /*!< [24..24] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH6_STOP    : 1; /*!< [25..25] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH6_QUE_EMP : 1; /*!< [26..26] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH6_ERR     : 1; /*!< [27..27] Set when an error occurs during DMA transfer.                    */
+                __IOM uint32_t CH7_END     : 1; /*!< [28..28] Set when the DMAC ends normally.                                 */
+                __IOM uint32_t CH7_STOP    : 1; /*!< [29..29] Set when the DMAC is prematurely stopped.                        */
+                __IOM uint32_t CH7_QUE_EMP : 1; /*!< [30..30] Set when the list is removed from the descriptor queue
+                                                 *   (transferred to the execution descriptor list) and the
+                                                 *   QUE is empty.                                                             */
+                __IOM uint32_t CH7_ERR : 1;     /*!< [31..31] Set when an error occurs during DMA transfer.                    */
+            } PCI_RC_DMAINTS_b;
+        };
+    };
+    __IM uint32_t RESERVED19[60];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACHCTL0; /*!< (@ 0x00000900) DMAC Channel Control Register 0                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_EP_DMACHCTL0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACHCTL0; /*!< (@ 0x00000900) DMAC Channel Control Register 0                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_RC_DMACHCTL0_b;
+        };
+    };
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRL0;            /*!< (@ 0x00000908) Descriptor Start Address (Lower) Register 0                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRL0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRL0;            /*!< (@ 0x00000908) Descriptor Start Address (Lower) Register 0                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRU0;            /*!< (@ 0x0000090C) Descriptor Start Address (Upper) Registers 0               */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRU0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRU0;            /*!< (@ 0x0000090C) Descriptor Start Address (Upper) Register 0                */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRU0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_QUEE0;             /*!< (@ 0x00000910) QUE Entry Register 0                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_EP_QUEE0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_QUEE0;             /*!< (@ 0x00000910) QUE Entry Register 0                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_RC_QUEE0_b;
+        };
+    };
+    __IM uint32_t RESERVED21[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPCTL0; /*!< (@ 0x00000920) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  0                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_EP_DMADPCTL0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPCTL0; /*!< (@ 0x00000920) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  0                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_RC_DMADPCTL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMATCTL0;  /*!< (@ 0x00000924) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  0                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_EP_DMATCTL0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMATCTL0;  /*!< (@ 0x00000924) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  0                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_RC_DMATCTL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASIZE0;       /*!< (@ 0x00000928) DMA Size (Descriptor 0x08) Register 0                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_EP_DMASIZE0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASIZE0;       /*!< (@ 0x00000928) DMA Size (Descriptor 0x08) Register 0                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_RC_DMASIZE0_b;
+        };
+    };
+    __IM uint32_t RESERVED22;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASLA0;          /*!< (@ 0x00000930) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  0                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_EP_DMASLA0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASLA0;          /*!< (@ 0x00000930) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  0                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_RC_DMASLA0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASUA0;          /*!< (@ 0x00000934) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  0                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_EP_DMASUA0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASUA0;          /*!< (@ 0x00000934) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  0                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_RC_DMASUA0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTLA0;       /*!< (@ 0x00000938) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 0                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTLA0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTLA0;       /*!< (@ 0x00000938) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 0                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTLA0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTUA0;       /*!< (@ 0x0000093C) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 0                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTUA0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTUA0;       /*!< (@ 0x0000093C) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 0                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTUA0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPLLP0;    /*!< (@ 0x00000940) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 0                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPLLP0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPLLP0;    /*!< (@ 0x00000940) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 0                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPLLP0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPULP0;    /*!< (@ 0x00000944) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 0                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPULP0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPULP0;    /*!< (@ 0x00000944) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 0                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPULP0_b;
+        };
+    };
+    __IM uint32_t RESERVED23[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_DMARESTSIZE0; /*!< (@ 0x00000950) DMA Rest Size Register 0                                   */
+        __IM uint32_t PCI_RC_DMARESTSIZE0; /*!< (@ 0x00000950) DMA Rest Size Register 0                                   */
+    };
+    __IM uint32_t RESERVED24[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAL0;            /*!< (@ 0x00000960) AXI Request Address (Lower) Register 0                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAL0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAL0;            /*!< (@ 0x00000960) AXI Request Address (Lower) Register 0                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAU0;            /*!< (@ 0x00000964) AXI Request Address (Upper) Register 0                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAU0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAU0;            /*!< (@ 0x00000964) AXI Request Address (Upper) Register 0                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAU0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAL0;             /*!< (@ 0x00000968) PCIe Request Address (Lower) Register 0                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAL0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAL0;             /*!< (@ 0x00000968) PCIe Request Address (Lower) Register 0                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAU0;             /*!< (@ 0x0000096C) PCIe Request Address (Upper) Register 0                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAU0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAU0;             /*!< (@ 0x0000096C) PCIe Request Address (Upper) Register 0                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAU0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_QUESTA0;   /*!< (@ 0x00000970) QUE Status Register 0                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_EP_QUESTA0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_QUESTA0;   /*!< (@ 0x00000970) QUE Status Register 0                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_RC_QUESTA0_b;
+        };
+    };
+    __IM uint32_t RESERVED25;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMACESTA0;      /*!< (@ 0x00000978) DMAC Error Status Register 0                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_EP_DMACESTA0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMACESTA0;      /*!< (@ 0x00000978) DMAC Error Status Register 0                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_RC_DMACESTA0_b;
+        };
+    };
+    __IM uint32_t RESERVED26;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACHCTL1; /*!< (@ 0x00000980) DMAC Channel Control Register 1                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_EP_DMACHCTL1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACHCTL1; /*!< (@ 0x00000980) DMAC Channel Control Register 1                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_RC_DMACHCTL1_b;
+        };
+    };
+    __IM uint32_t RESERVED27;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRL1;            /*!< (@ 0x00000988) Descriptor Start Address (Lower) Register 1                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRL1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRL1;            /*!< (@ 0x00000988) Descriptor Start Address (Lower) Register 1                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRU1;            /*!< (@ 0x0000098C) Descriptor Start Address (Upper) Registers 1               */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRU1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRU1;            /*!< (@ 0x0000098C) Descriptor Start Address (Upper) Register 1                */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRU1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_QUEE1;             /*!< (@ 0x00000990) QUE Entry Register 1                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_EP_QUEE1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_QUEE1;             /*!< (@ 0x00000990) QUE Entry Register 1                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_RC_QUEE1_b;
+        };
+    };
+    __IM uint32_t RESERVED28[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPCTL1; /*!< (@ 0x000009A0) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  1                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_EP_DMADPCTL1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPCTL1; /*!< (@ 0x000009A0) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  1                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_RC_DMADPCTL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMATCTL1;  /*!< (@ 0x000009A4) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  1                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_EP_DMATCTL1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMATCTL1;  /*!< (@ 0x000009A4) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  1                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_RC_DMATCTL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASIZE1;       /*!< (@ 0x000009A8) DMA Size (Descriptor 0x08) Register 1                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_EP_DMASIZE1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASIZE1;       /*!< (@ 0x000009A8) DMA Size (Descriptor 0x08) Register 1                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_RC_DMASIZE1_b;
+        };
+    };
+    __IM uint32_t RESERVED29;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASLA1;          /*!< (@ 0x000009B0) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  1                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_EP_DMASLA1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASLA1;          /*!< (@ 0x000009B0) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  1                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_RC_DMASLA1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASUA1;          /*!< (@ 0x000009B4) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  1                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_EP_DMASUA1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASUA1;          /*!< (@ 0x000009B4) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  1                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_RC_DMASUA1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTLA1;       /*!< (@ 0x000009B8) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 1                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTLA1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTLA1;       /*!< (@ 0x000009B8) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 1                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTLA1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTUA1;       /*!< (@ 0x000009BC) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 1                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTUA1_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTUA1;       /*!< (@ 0x000009BC) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 1                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTUA1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPLLP1;    /*!< (@ 0x000009C0) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 1                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPLLP1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPLLP1;    /*!< (@ 0x000009C0) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 1                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPLLP1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPULP1;    /*!< (@ 0x000009C4) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 1                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPULP1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPULP1;    /*!< (@ 0x000009C4) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 1                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPULP1_b;
+        };
+    };
+    __IM uint32_t RESERVED30[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_DMARESTSIZE1; /*!< (@ 0x000009D0) DMA Rest Size Register 1                                   */
+        __IM uint32_t PCI_RC_DMARESTSIZE1; /*!< (@ 0x000009D0) DMA Rest Size Register 1                                   */
+    };
+    __IM uint32_t RESERVED31[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAL1;            /*!< (@ 0x000009E0) AXI Request Address (Lower) Register 1                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAL1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAL1;            /*!< (@ 0x000009E0) AXI Request Address (Lower) Register 1                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAU1;            /*!< (@ 0x000009E4) AXI Request Address (Upper) Register 1                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAU1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAU1;            /*!< (@ 0x000009E4) AXI Request Address (Upper) Register 1                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAU1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAL1;             /*!< (@ 0x000009E8) PCIe Request Address (Lower) Register 1                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAL1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAL1;             /*!< (@ 0x000009E8) PCIe Request Address (Lower) Register 1                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAU1;             /*!< (@ 0x000009EC) PCIe Request Address (Upper) Register 1                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAU1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAU1;             /*!< (@ 0x000009EC) PCIe Request Address (Upper) Register 1                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAU1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_QUESTA1;   /*!< (@ 0x000009F0) QUE Status Register 1                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_EP_QUESTA1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_QUESTA1;   /*!< (@ 0x000009F0) QUE Status Register 1                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_RC_QUESTA1_b;
+        };
+    };
+    __IM uint32_t RESERVED32;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMACESTA1;      /*!< (@ 0x000009F8) DMAC Error Status Register 1                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_EP_DMACESTA1_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMACESTA1;      /*!< (@ 0x000009F8) DMAC Error Status Register 1                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_RC_DMACESTA1_b;
+        };
+    };
+    __IM uint32_t RESERVED33;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACHCTL2; /*!< (@ 0x00000A00) DMAC Channel Control Register 2                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_EP_DMACHCTL2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACHCTL2; /*!< (@ 0x00000A00) DMAC Channel Control Register 2                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_RC_DMACHCTL2_b;
+        };
+    };
+    __IM uint32_t RESERVED34;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRL2;            /*!< (@ 0x00000A08) Descriptor Start Address (Lower) Register 2                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRL2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRL2;            /*!< (@ 0x00000A08) Descriptor Start Address (Lower) Register 2                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRU2;            /*!< (@ 0x00000A0C) Descriptor Start Address (Upper) Registers 2               */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRU2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRU2;            /*!< (@ 0x00000A0C) Descriptor Start Address (Upper) Register 2                */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRU2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_QUEE2;             /*!< (@ 0x00000A10) QUE Entry Register 2                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_EP_QUEE2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_QUEE2;             /*!< (@ 0x00000A10) QUE Entry Register 2                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_RC_QUEE2_b;
+        };
+    };
+    __IM uint32_t RESERVED35[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPCTL2; /*!< (@ 0x00000A20) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  2                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_EP_DMADPCTL2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPCTL2; /*!< (@ 0x00000A20) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  2                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_RC_DMADPCTL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMATCTL2;  /*!< (@ 0x00000A24) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  2                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_EP_DMATCTL2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMATCTL2;  /*!< (@ 0x00000A24) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  2                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_RC_DMATCTL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASIZE2;       /*!< (@ 0x00000A28) DMA Size (Descriptor 0x08) Register 2                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_EP_DMASIZE2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASIZE2;       /*!< (@ 0x00000A28) DMA Size (Descriptor 0x08) Register 2                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_RC_DMASIZE2_b;
+        };
+    };
+    __IM uint32_t RESERVED36;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASLA2;          /*!< (@ 0x00000A30) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  2                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_EP_DMASLA2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASLA2;          /*!< (@ 0x00000A30) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  2                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_RC_DMASLA2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASUA2;          /*!< (@ 0x00000A34) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  2                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_EP_DMASUA2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASUA2;          /*!< (@ 0x00000A34) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  2                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_RC_DMASUA2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTLA2;       /*!< (@ 0x00000A38) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 2                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTLA2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTLA2;       /*!< (@ 0x00000A38) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 2                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTLA2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTUA2;       /*!< (@ 0x00000A3C) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 2                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTUA2_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTUA2;       /*!< (@ 0x00000A3C) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 2                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTUA2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPLLP2;    /*!< (@ 0x00000A40) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 2                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPLLP2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPLLP2;    /*!< (@ 0x00000A40) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 2                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPLLP2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPULP2;    /*!< (@ 0x00000A44) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 2                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPULP2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPULP2;    /*!< (@ 0x00000A44) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 2                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPULP2_b;
+        };
+    };
+    __IM uint32_t RESERVED37[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_DMARESTSIZE2; /*!< (@ 0x00000A50) DMA Rest Size Register 2                                   */
+        __IM uint32_t PCI_RC_DMARESTSIZE2; /*!< (@ 0x00000A50) DMA Rest Size Register 2                                   */
+    };
+    __IM uint32_t RESERVED38[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAL2;            /*!< (@ 0x00000A60) AXI Request Address (Lower) Register 2                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAL2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAL2;            /*!< (@ 0x00000A60) AXI Request Address (Lower) Register 2                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAU2;            /*!< (@ 0x00000A64) AXI Request Address (Upper) Register 2                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAU2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAU2;            /*!< (@ 0x00000A64) AXI Request Address (Upper) Register 2                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAU2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAL2;             /*!< (@ 0x00000A68) PCIe Request Address (Lower) Register 2                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAL2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAL2;             /*!< (@ 0x00000A68) PCIe Request Address (Lower) Register 2                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAU2;             /*!< (@ 0x00000A6C) PCIe Request Address (Upper) Register 2                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAU2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAU2;             /*!< (@ 0x00000A6C) PCIe Request Address (Upper) Register 2                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAU2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_QUESTA2;   /*!< (@ 0x00000A70) QUE Status Register 2                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_EP_QUESTA2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_QUESTA2;   /*!< (@ 0x00000A70) QUE Status Register 2                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_RC_QUESTA2_b;
+        };
+    };
+    __IM uint32_t RESERVED39;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMACESTA2;      /*!< (@ 0x00000A78) DMAC Error Status Register 2                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_EP_DMACESTA2_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMACESTA2;      /*!< (@ 0x00000A78) DMAC Error Status Register 2                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_RC_DMACESTA2_b;
+        };
+    };
+    __IM uint32_t RESERVED40;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACHCTL3; /*!< (@ 0x00000A80) DMAC Channel Control Register 3                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_EP_DMACHCTL3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACHCTL3; /*!< (@ 0x00000A80) DMAC Channel Control Register 3                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_RC_DMACHCTL3_b;
+        };
+    };
+    __IM uint32_t RESERVED41;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRL3;            /*!< (@ 0x00000A88) Descriptor Start Address (Lower) Register 3                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRL3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRL3;            /*!< (@ 0x00000A88) Descriptor Start Address (Lower) Register 3                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRU3;            /*!< (@ 0x00000A8C) Descriptor Start Address (Upper) Registers 3               */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRU3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRU3;            /*!< (@ 0x00000A8C) Descriptor Start Address (Upper) Register 3                */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRU3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_QUEE3;             /*!< (@ 0x00000A90) QUE Entry Register 3                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_EP_QUEE3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_QUEE3;             /*!< (@ 0x00000A90) QUE Entry Register 3                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_RC_QUEE3_b;
+        };
+    };
+    __IM uint32_t RESERVED42[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPCTL3; /*!< (@ 0x00000AA0) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  3                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_EP_DMADPCTL3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPCTL3; /*!< (@ 0x00000AA0) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  3                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_RC_DMADPCTL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMATCTL3;  /*!< (@ 0x00000AA4) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  3                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_EP_DMATCTL3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMATCTL3;  /*!< (@ 0x00000AA4) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  3                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_RC_DMATCTL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASIZE3;       /*!< (@ 0x00000AA8) DMA Size (Descriptor 0x08) Register 3                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_EP_DMASIZE3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASIZE3;       /*!< (@ 0x00000AA8) DMA Size (Descriptor 0x08) Register 3                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_RC_DMASIZE3_b;
+        };
+    };
+    __IM uint32_t RESERVED43;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASLA3;          /*!< (@ 0x00000AB0) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  3                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_EP_DMASLA3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASLA3;          /*!< (@ 0x00000AB0) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  3                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_RC_DMASLA3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASUA3;          /*!< (@ 0x00000AB4) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  3                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_EP_DMASUA3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASUA3;          /*!< (@ 0x00000AB4) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  3                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_RC_DMASUA3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTLA3;       /*!< (@ 0x00000AB8) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 3                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTLA3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTLA3;       /*!< (@ 0x00000AB8) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 3                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTLA3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTUA3;       /*!< (@ 0x00000ABC) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 3                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTUA3_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTUA3;       /*!< (@ 0x00000ABC) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 3                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTUA3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPLLP3;    /*!< (@ 0x00000AC0) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 3                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPLLP3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPLLP3;    /*!< (@ 0x00000AC0) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 3                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPLLP3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPULP3;    /*!< (@ 0x00000AC4) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 3                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPULP3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPULP3;    /*!< (@ 0x00000AC4) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 3                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPULP3_b;
+        };
+    };
+    __IM uint32_t RESERVED44[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_DMARESTSIZE3; /*!< (@ 0x00000AD0) DMA Rest Size Register 3                                   */
+        __IM uint32_t PCI_RC_DMARESTSIZE3; /*!< (@ 0x00000AD0) DMA Rest Size Register 3                                   */
+    };
+    __IM uint32_t RESERVED45[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAL3;            /*!< (@ 0x00000AE0) AXI Request Address (Lower) Register 3                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAL3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAL3;            /*!< (@ 0x00000AE0) AXI Request Address (Lower) Register 3                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAU3;            /*!< (@ 0x00000AE4) AXI Request Address (Upper) Register 3                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAU3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAU3;            /*!< (@ 0x00000AE4) AXI Request Address (Upper) Register 3                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAU3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAL3;             /*!< (@ 0x00000AE8) PCIe Request Address (Lower) Register 3                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAL3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAL3;             /*!< (@ 0x00000AE8) PCIe Request Address (Lower) Register 3                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAU3;             /*!< (@ 0x00000AEC) PCIe Request Address (Upper) Register 3                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAU3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAU3;             /*!< (@ 0x00000AEC) PCIe Request Address (Upper) Register 3                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAU3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_QUESTA3;   /*!< (@ 0x00000AF0) QUE Status Register 3                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_EP_QUESTA3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_QUESTA3;   /*!< (@ 0x00000AF0) QUE Status Register 3                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_RC_QUESTA3_b;
+        };
+    };
+    __IM uint32_t RESERVED46;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMACESTA3;      /*!< (@ 0x00000AF8) DMAC Error Status Register 3                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_EP_DMACESTA3_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMACESTA3;      /*!< (@ 0x00000AF8) DMAC Error Status Register 3                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_RC_DMACESTA3_b;
+        };
+    };
+    __IM uint32_t RESERVED47;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACHCTL4; /*!< (@ 0x00000B00) DMAC Channel Control Register 4                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_EP_DMACHCTL4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACHCTL4; /*!< (@ 0x00000B00) DMAC Channel Control Register 4                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_RC_DMACHCTL4_b;
+        };
+    };
+    __IM uint32_t RESERVED48;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRL4;            /*!< (@ 0x00000B08) Descriptor Start Address (Lower) Register 4                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRL4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRL4;            /*!< (@ 0x00000B08) Descriptor Start Address (Lower) Register 4                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRU4;            /*!< (@ 0x00000B0C) Descriptor Start Address (Upper) Registers 4               */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRU4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRU4;            /*!< (@ 0x00000B0C) Descriptor Start Address (Upper) Register 4                */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRU4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_QUEE4;             /*!< (@ 0x00000B10) QUE Entry Register 4                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_EP_QUEE4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_QUEE4;             /*!< (@ 0x00000B10) QUE Entry Register 4                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_RC_QUEE4_b;
+        };
+    };
+    __IM uint32_t RESERVED49[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPCTL4; /*!< (@ 0x00000B20) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  4                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_EP_DMADPCTL4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPCTL4; /*!< (@ 0x00000B20) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  4                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_RC_DMADPCTL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMATCTL4;  /*!< (@ 0x00000B24) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  4                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_EP_DMATCTL4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMATCTL4;  /*!< (@ 0x00000B24) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  4                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_RC_DMATCTL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASIZE4;       /*!< (@ 0x00000B28) DMA Size (Descriptor 0x08) Register 4                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_EP_DMASIZE4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASIZE4;       /*!< (@ 0x00000B28) DMA Size (Descriptor 0x08) Register 4                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_RC_DMASIZE4_b;
+        };
+    };
+    __IM uint32_t RESERVED50;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASLA4;          /*!< (@ 0x00000B30) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  4                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_EP_DMASLA4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASLA4;          /*!< (@ 0x00000B30) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  4                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_RC_DMASLA4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASUA4;          /*!< (@ 0x00000B34) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  4                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_EP_DMASUA4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASUA4;          /*!< (@ 0x00000B34) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  4                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_RC_DMASUA4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTLA4;       /*!< (@ 0x00000B38) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 4                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTLA4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTLA4;       /*!< (@ 0x00000B38) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 4                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTLA4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTUA4;       /*!< (@ 0x00000B3C) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 4                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTUA4_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTUA4;       /*!< (@ 0x00000B3C) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 4                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTUA4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPLLP4;    /*!< (@ 0x00000B40) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 4                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPLLP4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPLLP4;    /*!< (@ 0x00000B40) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 4                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPLLP4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPULP4;    /*!< (@ 0x00000B44) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 4                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPULP4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPULP4;    /*!< (@ 0x00000B44) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 4                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPULP4_b;
+        };
+    };
+    __IM uint32_t RESERVED51[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_DMARESTSIZE4; /*!< (@ 0x00000B50) DMA Rest Size Register 4                                   */
+        __IM uint32_t PCI_RC_DMARESTSIZE4; /*!< (@ 0x00000B50) DMA Rest Size Register 4                                   */
+    };
+    __IM uint32_t RESERVED52[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAL4;            /*!< (@ 0x00000B60) AXI Request Address (Lower) Register 4                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAL4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAL4;            /*!< (@ 0x00000B60) AXI Request Address (Lower) Register 4                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAU4;            /*!< (@ 0x00000B64) AXI Request Address (Upper) Register 4                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAU4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAU4;            /*!< (@ 0x00000B64) AXI Request Address (Upper) Register 4                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAU4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAL4;             /*!< (@ 0x00000B68) PCIe Request Address (Lower) Register 4                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAL4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAL4;             /*!< (@ 0x00000B68) PCIe Request Address (Lower) Register 4                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAU4;             /*!< (@ 0x00000B6C) PCIe Request Address (Upper) Register 4                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAU4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAU4;             /*!< (@ 0x00000B6C) PCIe Request Address (Upper) Register 4                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAU4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_QUESTA4;   /*!< (@ 0x00000B70) QUE Status Register 4                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_EP_QUESTA4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_QUESTA4;   /*!< (@ 0x00000B70) QUE Status Register 4                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_RC_QUESTA4_b;
+        };
+    };
+    __IM uint32_t RESERVED53;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMACESTA4;      /*!< (@ 0x00000B78) DMAC Error Status Register 4                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_EP_DMACESTA4_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMACESTA4;      /*!< (@ 0x00000B78) DMAC Error Status Register 4                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_RC_DMACESTA4_b;
+        };
+    };
+    __IM uint32_t RESERVED54;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACHCTL5; /*!< (@ 0x00000B80) DMAC Channel Control Register 5                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_EP_DMACHCTL5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACHCTL5; /*!< (@ 0x00000B80) DMAC Channel Control Register 5                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_RC_DMACHCTL5_b;
+        };
+    };
+    __IM uint32_t RESERVED55;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRL5;            /*!< (@ 0x00000B88) Descriptor Start Address (Lower) Register 5                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRL5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRL5;            /*!< (@ 0x00000B88) Descriptor Start Address (Lower) Register 5                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRU5;            /*!< (@ 0x00000B8C) Descriptor Start Address (Upper) Registers 5               */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRU5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRU5;            /*!< (@ 0x00000B8C) Descriptor Start Address (Upper) Register 5                */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRU5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_QUEE5;             /*!< (@ 0x00000B90) QUE Entry Register 5                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_EP_QUEE5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_QUEE5;             /*!< (@ 0x00000B90) QUE Entry Register 5                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_RC_QUEE5_b;
+        };
+    };
+    __IM uint32_t RESERVED56[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPCTL5; /*!< (@ 0x00000BA0) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  5                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_EP_DMADPCTL5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPCTL5; /*!< (@ 0x00000BA0) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  5                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_RC_DMADPCTL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMATCTL5;  /*!< (@ 0x00000BA4) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  5                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_EP_DMATCTL5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMATCTL5;  /*!< (@ 0x00000BA4) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  5                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_RC_DMATCTL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASIZE5;       /*!< (@ 0x00000BA8) DMA Size (Descriptor 0x08) Register 5                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_EP_DMASIZE5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASIZE5;       /*!< (@ 0x00000BA8) DMA Size (Descriptor 0x08) Register 5                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_RC_DMASIZE5_b;
+        };
+    };
+    __IM uint32_t RESERVED57;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASLA5;          /*!< (@ 0x00000BB0) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  5                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_EP_DMASLA5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASLA5;          /*!< (@ 0x00000BB0) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  5                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_RC_DMASLA5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASUA5;          /*!< (@ 0x00000BB4) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  5                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_EP_DMASUA5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASUA5;          /*!< (@ 0x00000BB4) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  5                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_RC_DMASUA5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTLA5;       /*!< (@ 0x00000BB8) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 5                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTLA5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTLA5;       /*!< (@ 0x00000BB8) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 5                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTLA5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTUA5;       /*!< (@ 0x00000BBC) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 5                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTUA5_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTUA5;       /*!< (@ 0x00000BBC) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 5                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTUA5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPLLP5;    /*!< (@ 0x00000BC0) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 5                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPLLP5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPLLP5;    /*!< (@ 0x00000BC0) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 5                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPLLP5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPULP5;    /*!< (@ 0x00000BC4) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 5                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPULP5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPULP5;    /*!< (@ 0x00000BC4) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 5                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPULP5_b;
+        };
+    };
+    __IM uint32_t RESERVED58[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_DMARESTSIZE5; /*!< (@ 0x00000BD0) DMA Rest Size Register 5                                   */
+        __IM uint32_t PCI_RC_DMARESTSIZE5; /*!< (@ 0x00000BD0) DMA Rest Size Register 5                                   */
+    };
+    __IM uint32_t RESERVED59[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAL5;            /*!< (@ 0x00000BE0) AXI Request Address (Lower) Register 5                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAL5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAL5;            /*!< (@ 0x00000BE0) AXI Request Address (Lower) Register 5                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAU5;            /*!< (@ 0x00000BE4) AXI Request Address (Upper) Register 5                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAU5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAU5;            /*!< (@ 0x00000BE4) AXI Request Address (Upper) Register 5                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAU5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAL5;             /*!< (@ 0x00000BE8) PCIe Request Address (Lower) Register 5                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAL5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAL5;             /*!< (@ 0x00000BE8) PCIe Request Address (Lower) Register 5                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAU5;             /*!< (@ 0x00000BEC) PCIe Request Address (Upper) Register 5                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAU5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAU5;             /*!< (@ 0x00000BEC) PCIe Request Address (Upper) Register 5                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAU5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_QUESTA5;   /*!< (@ 0x00000BF0) QUE Status Register 5                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_EP_QUESTA5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_QUESTA5;   /*!< (@ 0x00000BF0) QUE Status Register 5                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_RC_QUESTA5_b;
+        };
+    };
+    __IM uint32_t RESERVED60;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMACESTA5;      /*!< (@ 0x00000BF8) DMAC Error Status Register 5                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_EP_DMACESTA5_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMACESTA5;      /*!< (@ 0x00000BF8) DMAC Error Status Register 5                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_RC_DMACESTA5_b;
+        };
+    };
+    __IM uint32_t RESERVED61;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACHCTL6; /*!< (@ 0x00000C00) DMAC Channel Control Register 6                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_EP_DMACHCTL6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACHCTL6; /*!< (@ 0x00000C00) DMAC Channel Control Register 6                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_RC_DMACHCTL6_b;
+        };
+    };
+    __IM uint32_t RESERVED62;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRL6;            /*!< (@ 0x00000C08) Descriptor Start Address (Lower) Register 6                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRL6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRL6;            /*!< (@ 0x00000C08) Descriptor Start Address (Lower) Register 6                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRU6;            /*!< (@ 0x00000C0C) Descriptor Start Address (Upper) Registers 6               */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRU6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRU6;            /*!< (@ 0x00000C0C) Descriptor Start Address (Upper) Register 6                */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRU6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_QUEE6;             /*!< (@ 0x00000C10) QUE Entry Register 6                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_EP_QUEE6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_QUEE6;             /*!< (@ 0x00000C10) QUE Entry Register 6                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_RC_QUEE6_b;
+        };
+    };
+    __IM uint32_t RESERVED63[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPCTL6; /*!< (@ 0x00000C20) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  6                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_EP_DMADPCTL6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPCTL6; /*!< (@ 0x00000C20) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  6                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_RC_DMADPCTL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMATCTL6;  /*!< (@ 0x00000C24) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  6                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_EP_DMATCTL6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMATCTL6;  /*!< (@ 0x00000C24) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  6                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_RC_DMATCTL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASIZE6;       /*!< (@ 0x00000C28) DMA Size (Descriptor 0x08) Register 6                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_EP_DMASIZE6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASIZE6;       /*!< (@ 0x00000C28) DMA Size (Descriptor 0x08) Register 6                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_RC_DMASIZE6_b;
+        };
+    };
+    __IM uint32_t RESERVED64;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASLA6;          /*!< (@ 0x00000C30) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  6                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_EP_DMASLA6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASLA6;          /*!< (@ 0x00000C30) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  6                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_RC_DMASLA6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASUA6;          /*!< (@ 0x00000C34) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  6                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_EP_DMASUA6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASUA6;          /*!< (@ 0x00000C34) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  6                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_RC_DMASUA6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTLA6;       /*!< (@ 0x00000C38) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 6                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTLA6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTLA6;       /*!< (@ 0x00000C38) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 6                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTLA6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTUA6;       /*!< (@ 0x00000C3C) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 6                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTUA6_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTUA6;       /*!< (@ 0x00000C3C) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 6                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTUA6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPLLP6;    /*!< (@ 0x00000C40) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 6                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPLLP6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPLLP6;    /*!< (@ 0x00000C40) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 6                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPLLP6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPULP6;    /*!< (@ 0x00000C44) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 6                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPULP6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPULP6;    /*!< (@ 0x00000C44) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 6                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPULP6_b;
+        };
+    };
+    __IM uint32_t RESERVED65[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_DMARESTSIZE6; /*!< (@ 0x00000C50) DMA Rest Size Register 6                                   */
+        __IM uint32_t PCI_RC_DMARESTSIZE6; /*!< (@ 0x00000C50) DMA Rest Size Register 6                                   */
+    };
+    __IM uint32_t RESERVED66[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAL6;            /*!< (@ 0x00000C60) AXI Request Address (Lower) Register 6                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAL6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAL6;            /*!< (@ 0x00000C60) AXI Request Address (Lower) Register 6                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAU6;            /*!< (@ 0x00000C64) AXI Request Address (Upper) Register 6                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAU6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAU6;            /*!< (@ 0x00000C64) AXI Request Address (Upper) Register 6                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAU6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAL6;             /*!< (@ 0x00000C68) PCIe Request Address (Lower) Register 6                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAL6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAL6;             /*!< (@ 0x00000C68) PCIe Request Address (Lower) Register 6                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAU6;             /*!< (@ 0x00000C6C) PCIe Request Address (Upper) Register 6                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAU6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAU6;             /*!< (@ 0x00000C6C) PCIe Request Address (Upper) Register 6                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAU6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_QUESTA6;   /*!< (@ 0x00000C70) QUE Status Register 6                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_EP_QUESTA6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_QUESTA6;   /*!< (@ 0x00000C70) QUE Status Register 6                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_RC_QUESTA6_b;
+        };
+    };
+    __IM uint32_t RESERVED67;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMACESTA6;      /*!< (@ 0x00000C78) DMAC Error Status Register 6                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_EP_DMACESTA6_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMACESTA6;      /*!< (@ 0x00000C78) DMAC Error Status Register 6                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_RC_DMACESTA6_b;
+        };
+    };
+    __IM uint32_t RESERVED68;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMACHCTL7; /*!< (@ 0x00000C80) DMAC Channel Control Register 7                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_EP_DMACHCTL7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMACHCTL7; /*!< (@ 0x00000C80) DMAC Channel Control Register 7                            */
+
+            struct
+            {
+                __IOM uint32_t RDMA_EN : 1;  /*!< [0..0] Register method DMA transfer Enable                                */
+                __IOM uint32_t QUE_EN  : 1;  /*!< [1..1] QUE Enable                                                         */
+                uint32_t               : 6;
+                __IOM uint32_t QUE_CLR : 1;  /*!< [8..8] QUE Clear                                                          */
+                uint32_t               : 23;
+            } PCI_RC_DMACHCTL7_b;
+        };
+    };
+    __IM uint32_t RESERVED69;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRL7;            /*!< (@ 0x00000C88) Descriptor Start Address (Lower) Register 7                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRL7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRL7;            /*!< (@ 0x00000C88) Descriptor Start Address (Lower) Register 7                */
+
+            struct
+            {
+                __IM uint32_t QUE_ENTRY_DSA0500 : 6;   /*!< [5..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+                __IOM uint32_t QUE_ENTRY_DSA3106 : 26; /*!< [31..6] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DPSADRU7;            /*!< (@ 0x00000C8C) Descriptor Start Address (Upper) Registers 7               */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_EP_DPSADRU7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DPSADRU7;            /*!< (@ 0x00000C8C) Descriptor Start Address (Upper) Register 7                */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_DSA6332 : 32; /*!< [31..0] Descriptor list queue registration register. This area
+                                                        *   will be the DSA.                                                          */
+            } PCI_RC_DPSADRU7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_QUEE7;             /*!< (@ 0x00000C90) QUE Entry Register 7                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_EP_QUEE7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_QUEE7;             /*!< (@ 0x00000C90) QUE Entry Register 7                                       */
+
+            struct
+            {
+                __IOM uint32_t QUE_ENTRY_LABEL : 16; /*!< [15..0] There is no particular rule on how to set the labels
+                                                      *   in the list.                                                              */
+                uint32_t                    : 8;
+                __IOM uint32_t QUE_ENTRY_LS : 1;     /*!< [24..24] Indicates whether to stop the DMA when processing of
+                                                      *   the descriptor list is complete.                                          */
+                __IOM uint32_t QUE_ENTRY_EI : 1;     /*!< [25..25] Indicates whether an interrupt (Interrupt Status CHx_END)
+                                                      *   is sent when the processing of the descriptor list is completed.          */
+                __IOM uint32_t QUE_R : 6;            /*!< [31..26] QUE_Registration                                                 */
+            } PCI_RC_QUEE7_b;
+        };
+    };
+    __IM uint32_t RESERVED70[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPCTL7; /*!< (@ 0x00000CA0) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  7                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_EP_DMADPCTL7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPCTL7; /*!< (@ 0x00000CA0) DMA Descriptor Control (Descriptor 0x00) Register
+                                             *                  7                                                          */
+
+            struct
+            {
+                __IM uint32_t STS : 16;     /*!< [15..0] Shows the value of the STS field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t        : 7;
+                __IM uint32_t D : 1;        /*!< [23..23] Shows the value of the D field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LV : 1;       /*!< [24..24] Shows the value of the LV field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t LE : 1;       /*!< [25..25] Shows the value of the LE field in the running descriptor
+                                             *   table.                                                                    */
+                __IM uint32_t WBD : 1;      /*!< [26..26] Shows the value of the WBD field in the running descriptor
+                                             *   table.                                                                    */
+                uint32_t            : 1;
+                __IM uint32_t DSCFM : 4;    /*!< [31..28] Shows the value of the DSCFM field in the running descriptor
+                                             *   table.                                                                    */
+            } PCI_RC_DMADPCTL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMATCTL7;  /*!< (@ 0x00000CA4) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  7                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_EP_DMATCTL7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMATCTL7;  /*!< (@ 0x00000CA4) DMA Transaction Control (Descriptor 0x04) Register
+                                              *                  7                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_DIR  : 1; /*!< [0..0] Sets the DMA transfer direction.                                   */
+                uint32_t                : 3;
+                __IOM uint32_t DMA_FUNC : 3; /*!< [6..4] Specify the function number of the request issued to
+                                              *   PCIe.                                                                     */
+                uint32_t               : 1;
+                __IOM uint32_t DMA_ATB : 2;  /*!< [9..8] Attributes to publish to PCIe.                                     */
+                uint32_t               : 2;
+                __IOM uint32_t DMA_TC  : 3;  /*!< [14..12] Traffic class to publish to PCIe.                                */
+                uint32_t               : 1;
+                __IOM uint32_t CCH_D   : 4;  /*!< [19..16] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                __IOM uint32_t CCH_L : 4;    /*!< [23..20] Indicates the value of A*CACHE[3:0] to be issued to
+                                              *   AXI.                                                                      */
+                uint32_t : 8;
+            } PCI_RC_DMATCTL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASIZE7;       /*!< (@ 0x00000CA8) DMA Size (Descriptor 0x08) Register 7                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_EP_DMASIZE7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASIZE7;       /*!< (@ 0x00000CA8) DMA Size (Descriptor 0x08) Register 7                      */
+
+            struct
+            {
+                __IM uint32_t  DMA_SIZE0300 : 4;  /*!< [3..0] Sets the number of DMA transfer bytes.                             */
+                __IOM uint32_t DMA_SIZE3104 : 28; /*!< [31..4] Sets the number of DMA transfer bytes.                            */
+            } PCI_RC_DMASIZE7_b;
+        };
+    };
+    __IM uint32_t RESERVED71;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASLA7;          /*!< (@ 0x00000CB0) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  7                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_EP_DMASLA7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASLA7;          /*!< (@ 0x00000CB0) DMA Source Lower Address (Descriptor 0x10) Register
+                                                     *                  7                                                          */
+
+            struct
+            {
+                __IM uint32_t DMA_S_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+                __IOM uint32_t DMA_S_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer source start address
+                                                     *   for DMA transfer.                                                         */
+            } PCI_RC_DMASLA7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMASUA7;          /*!< (@ 0x00000CB4) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  7                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_EP_DMASUA7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMASUA7;          /*!< (@ 0x00000CB4) DMA Source Upper Address (Descriptor 0x14) Register
+                                                     *                  7                                                          */
+
+            struct
+            {
+                __IOM uint32_t DMA_S_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer source start address
+                                                     *   for MA transfer.                                                          */
+            } PCI_RC_DMASUA7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTLA7;       /*!< (@ 0x00000CB8) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 7                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTLA7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTLA7;       /*!< (@ 0x00000CB8) DMA Destination Lower Address (Descriptor 0x18)
+                                                     *                  Register 7                                                 */
+
+            struct
+            {
+                __IM uint32_t DMA_D_ADDR0300 : 4;   /*!< [3..0] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+                __IOM uint32_t DMA_D_ADDR3104 : 28; /*!< [31..4] Set the lower 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTLA7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DMADESTUA7;       /*!< (@ 0x00000CBC) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 7                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_EP_DMADESTUA7_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DMADESTUA7;       /*!< (@ 0x00000CBC) DMA Destination Upper Address (Descriptor 0x1C)
+                                                     *                  Register 7                                                 */
+
+            struct
+            {
+                __IOM uint32_t DMA_D_ADDR6332 : 32; /*!< [31..0] Set the upper 32 bits of the transfer destination start
+                                                     *   address for DMA transfer.                                                 */
+            } PCI_RC_DMADESTUA7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPLLP7;    /*!< (@ 0x00000CC0) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 7                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPLLP7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPLLP7;    /*!< (@ 0x00000CC0) DMA Descriptor Lower Link Pointer (Descriptor
+                                                *                  0x20) Register 7                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP3100 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPLLP7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMADPULP7;    /*!< (@ 0x00000CC4) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 7                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_EP_DMADPULP7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMADPULP7;    /*!< (@ 0x00000CC4) DMA Descriptor Upper Link Pointer (Descriptor
+                                                *                  0x24) Register 7                                           */
+
+            struct
+            {
+                __IM uint32_t DMA_LP6332 : 32; /*!< [31..0] Indicates the value of the LP field of the running descriptor
+                                                *   table.                                                                    */
+            } PCI_RC_DMADPULP7_b;
+        };
+    };
+    __IM uint32_t RESERVED72[2];
+
+    union
+    {
+        __IM uint32_t PCI_EP_DMARESTSIZE7; /*!< (@ 0x00000CD0) DMA Rest Size Register 7                                   */
+        __IM uint32_t PCI_RC_DMARESTSIZE7; /*!< (@ 0x00000CD0) DMA Rest Size Register 7                                   */
+    };
+    __IM uint32_t RESERVED73[3];
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAL7;            /*!< (@ 0x00000CE0) AXI Request Address (Lower) Register 7                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAL7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAL7;            /*!< (@ 0x00000CE0) AXI Request Address (Lower) Register 7                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_AREQAU7;            /*!< (@ 0x00000CE4) AXI Request Address (Upper) Register 7                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_EP_AREQAU7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_AREQAU7;            /*!< (@ 0x00000CE4) AXI Request Address (Upper) Register 7                     */
+
+            struct
+            {
+                __IM uint32_t AXI_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                      *   completed AXI transfer or the transfer that just completed.
+                                                      *   (Register/descriptor method common)                                       */
+            } PCI_RC_AREQAU7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAL7;             /*!< (@ 0x00000CE8) PCIe Request Address (Lower) Register 7                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAL7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAL7;             /*!< (@ 0x00000CE8) PCIe Request Address (Lower) Register 7                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR3100 : 32; /*!< [31..0] Displays the lower 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_PREQAU7;             /*!< (@ 0x00000CEC) PCIe Request Address (Upper) Register 7                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_EP_PREQAU7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_PREQAU7;             /*!< (@ 0x00000CEC) PCIe Request Address (Upper) Register 7                    */
+
+            struct
+            {
+                __IM uint32_t PCIE_REQ_ADDR6332 : 32; /*!< [31..0] Displays the upper 32 bits of the address of the currently
+                                                       *   completed PCIe transfer or the transfer completed immediately
+                                                       *   before. (Register/descriptor method common)                               */
+            } PCI_RC_PREQAU7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_QUESTA7;   /*!< (@ 0x00000CF0) QUE Status Register 7                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_EP_QUESTA7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_QUESTA7;   /*!< (@ 0x00000CF0) QUE Status Register 7                                      */
+
+            struct
+            {
+                __IM uint32_t LIST_NUM : 4; /*!< [3..0] Displays the number of descriptor lists loaded on QUE
+                                             *   (not including the list currently being executed).                        */
+                __IM uint32_t GO_LIST : 1;  /*!< [4..4] Shows whether there is a running descriptor list.                  */
+                uint32_t              : 27;
+            } PCI_RC_QUESTA7_b;
+        };
+    };
+    __IM uint32_t RESERVED74;
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_DMACESTA7;      /*!< (@ 0x00000CF8) DMAC Error Status Register 7                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_EP_DMACESTA7_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_DMACESTA7;      /*!< (@ 0x00000CF8) DMAC Error Status Register 7                               */
+
+            struct
+            {
+                __IM uint32_t AXI_RESP   : 2;    /*!< [1..0] Displays the slave response during AXI Master transactions.        */
+                uint32_t                 : 6;
+                __IM uint32_t MOR_STATUS : 3;    /*!< [10..8] Indicates the value when MOR_STATUS is other than 000b
+                                                  *   (Success) as a set factor of CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t MOR_EP_ERR : 1;    /*!< [11..11] It is set when it is Poisoned Completion as a set factor
+                                                  *   of CHx_ERR. Holds value until CHx_ERR is cleared.                         */
+                __IM uint32_t MOR_CH_PERR : 1;   /*!< [12..12] It is set when MOR_CH_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                __IM uint32_t MOR_CD_PERR : 1;   /*!< [13..13] It is set when MOR_CD_PERR is detected as a set factor
+                                                  *   for CHx_ERR. Holds value until CHx_ERR is cleared.                        */
+                uint32_t               : 2;
+                __IM uint32_t BME_DOWN : 1;      /*!< [16..16] It is set when a stop signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t BME_SUP : 1;       /*!< [17..17] It is set when a sleep signal from the PCIe core is
+                                                  *   detected as a cause for setting CHx_ERR. Holds value until
+                                                  *   CHx_ERR is cleared.                                                       */
+                __IM uint32_t CFG_BM_DIS_EP : 1; /*!< [18..18] CHx_ERR is set when the macro operates as an End Point
+                                                  *   and detects the state of Bus Master Enable Off (Configuration
+                                                  *   Space 0x004 bit [2] = 0). Holds value until CHx_ERR is
+                                                  *   cleared.                                                                  */
+                uint32_t : 13;
+            } PCI_RC_DMACESTA7_b;
+        };
+    };
+    __IM uint32_t RESERVED75[193];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEL0_F0; /*!< (@ 0x00001000) AXI Window Base (Lower) Register 0 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+                __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+            } PCI_EP_AWBASEL0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEL0;  /*!< (@ 0x00001000) AXI Window Base (Lower) Register 0                         */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;  /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;  /*!< [11..4] AWBase11:4                                                        */
+                __IOM uint32_t AWB3112 : 20; /*!< [31..12] AWBase31:12                                                      */
+            } PCI_RC_AWBASEL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEU0_F0; /*!< (@ 0x00001004) AXI Window Base (Upper) Register 0 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+            } PCI_EP_AWBASEU0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEU0;  /*!< (@ 0x00001004) AXI Window Base (Upper) Register 0                         */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32; /*!< [31..0] AWBase63:32                                                       */
+            } PCI_RC_AWBASEU0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKL0_F0; /*!< (@ 0x00001008) AXI Window Mask (Lower) Register 0 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+                __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+            } PCI_EP_AWMASKL0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKL0;  /*!< (@ 0x00001008) AXI Window Mask (Lower) Register 0                         */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12; /*!< [11..0] AWMask11:0                                                        */
+                __IOM uint32_t AWM3112 : 20; /*!< [31..12] AWMask31:12                                                      */
+            } PCI_RC_AWMASKL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKU0_F0; /*!< (@ 0x0000100C) AXI Window Mask (Upper) Register 0 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_AWMASKU0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKU0;  /*!< (@ 0x0000100C) AXI Window Mask Upper Register 0                           */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31; /*!< [30..0] AWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_AWMASKU0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTL0_F0; /*!< (@ 0x00001010) AXI Destination (Lower) Register 0 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+                __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+            } PCI_EP_ADESTL0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTL0;  /*!< (@ 0x00001010) AXI Destination (Lower) Register 0                         */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12; /*!< [11..0] ADest11:0                                                         */
+                __IOM uint32_t AD3112 : 20; /*!< [31..12] ADest31:12                                                       */
+            } PCI_RC_ADESTL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTU0_F0; /*!< (@ 0x00001014) AXI Destination (Upper) Register 0 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+            } PCI_EP_ADESTU0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTU0;  /*!< (@ 0x00001014) AXI Destination (Upper) Register 0                         */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32; /*!< [31..0] ADest63:32                                                        */
+            } PCI_RC_ADESTU0_b;
+        };
+    };
+    __IM uint32_t RESERVED76[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEL1_F0; /*!< (@ 0x00001020) AXI Window Base (Lower) Register 1 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+                __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+            } PCI_EP_AWBASEL1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEL1;  /*!< (@ 0x00001020) AXI Window Base (Lower) Register 1                         */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;  /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;  /*!< [11..4] AWBase11:4                                                        */
+                __IOM uint32_t AWB3112 : 20; /*!< [31..12] AWBase31:12                                                      */
+            } PCI_RC_AWBASEL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEU1_F0; /*!< (@ 0x00001024) AXI Window Base (Upper) Register 1 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+            } PCI_EP_AWBASEU1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEU1;  /*!< (@ 0x00001024) AXI Window Base (Upper) Register 1                         */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32; /*!< [31..0] AWBase63:32                                                       */
+            } PCI_RC_AWBASEU1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKL1_F0; /*!< (@ 0x00001028) AXI Window Mask (Lower) Register 1 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+                __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+            } PCI_EP_AWMASKL1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKL1;  /*!< (@ 0x00001028) AXI Window Mask (Lower) Register 1                         */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12; /*!< [11..0] AWMask11:0                                                        */
+                __IOM uint32_t AWM3112 : 20; /*!< [31..12] AWMask31:12                                                      */
+            } PCI_RC_AWMASKL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKU1_F0; /*!< (@ 0x0000102C) AXI Window Mask (Upper) Register 1 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_AWMASKU1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKU1;  /*!< (@ 0x0000102C) AXI Window Mask Upper Register 1                           */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31; /*!< [30..0] AWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_AWMASKU1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTL1_F0; /*!< (@ 0x00001030) AXI Destination (Lower) Register 1 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+                __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+            } PCI_EP_ADESTL1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTL1;  /*!< (@ 0x00001030) AXI Destination (Lower) Register 1                         */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12; /*!< [11..0] ADest11:0                                                         */
+                __IOM uint32_t AD3112 : 20; /*!< [31..12] ADest31:12                                                       */
+            } PCI_RC_ADESTL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTU1_F0; /*!< (@ 0x00001034) AXI Destination (Upper) Register 1 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+            } PCI_EP_ADESTU1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTU1;  /*!< (@ 0x00001034) AXI Destination (Upper) Register 1                         */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32; /*!< [31..0] ADest63:32                                                        */
+            } PCI_RC_ADESTU1_b;
+        };
+    };
+    __IM uint32_t RESERVED77[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEL2_F0; /*!< (@ 0x00001040) AXI Window Base (Lower) Register 2 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+                __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+            } PCI_EP_AWBASEL2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEL2;  /*!< (@ 0x00001040) AXI Window Base (Lower) Register 2                         */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;  /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;  /*!< [11..4] AWBase11:4                                                        */
+                __IOM uint32_t AWB3112 : 20; /*!< [31..12] AWBase31:12                                                      */
+            } PCI_RC_AWBASEL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEU2_F0; /*!< (@ 0x00001044) AXI Window Base (Upper) Register 2 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+            } PCI_EP_AWBASEU2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEU2;  /*!< (@ 0x00001044) AXI Window Base (Upper) Register 2                         */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32; /*!< [31..0] AWBase63:32                                                       */
+            } PCI_RC_AWBASEU2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKL2_F0; /*!< (@ 0x00001048) AXI Window Mask (Lower) Register 2 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+                __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+            } PCI_EP_AWMASKL2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKL2;  /*!< (@ 0x00001048) AXI Window Mask (Lower) Register 2                         */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12; /*!< [11..0] AWMask11:0                                                        */
+                __IOM uint32_t AWM3112 : 20; /*!< [31..12] AWMask31:12                                                      */
+            } PCI_RC_AWMASKL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKU2_F0; /*!< (@ 0x0000104C) AXI Window Mask (Upper) Register 2 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_AWMASKU2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKU2;  /*!< (@ 0x0000104C) AXI Window Mask Upper Register 2                           */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31; /*!< [30..0] AWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_AWMASKU2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTL2_F0; /*!< (@ 0x00001050) AXI Destination (Lower) Register 2 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+                __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+            } PCI_EP_ADESTL2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTL2;  /*!< (@ 0x00001050) AXI Destination (Lower) Register 2                         */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12; /*!< [11..0] ADest11:0                                                         */
+                __IOM uint32_t AD3112 : 20; /*!< [31..12] ADest31:12                                                       */
+            } PCI_RC_ADESTL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTU2_F0; /*!< (@ 0x00001054) AXI Destination (Upper) Register 2 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+            } PCI_EP_ADESTU2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTU2;  /*!< (@ 0x00001054) AXI Destination (Upper) Register 2                         */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32; /*!< [31..0] ADest63:32                                                        */
+            } PCI_RC_ADESTU2_b;
+        };
+    };
+    __IM uint32_t RESERVED78[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEL3_F0; /*!< (@ 0x00001060) AXI Window Base (Lower) Register 3 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+                __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+            } PCI_EP_AWBASEL3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEL3;  /*!< (@ 0x00001060) AXI Window Base (Lower) Register 3                         */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;  /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;  /*!< [11..4] AWBase11:4                                                        */
+                __IOM uint32_t AWB3112 : 20; /*!< [31..12] AWBase31:12                                                      */
+            } PCI_RC_AWBASEL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEU3_F0; /*!< (@ 0x00001064) AXI Window Base (Upper) Register 3 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+            } PCI_EP_AWBASEU3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEU3;  /*!< (@ 0x00001064) AXI Window Base (Upper) Register 3                         */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32; /*!< [31..0] AWBase63:32                                                       */
+            } PCI_RC_AWBASEU3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKL3_F0; /*!< (@ 0x00001068) AXI Window Mask (Lower) Register 3 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+                __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+            } PCI_EP_AWMASKL3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKL3;  /*!< (@ 0x00001068) AXI Window Mask (Lower) Register 3                         */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12; /*!< [11..0] AWMask11:0                                                        */
+                __IOM uint32_t AWM3112 : 20; /*!< [31..12] AWMask31:12                                                      */
+            } PCI_RC_AWMASKL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKU3_F0; /*!< (@ 0x0000106C) AXI Window Mask (Upper) Register 3 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_AWMASKU3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKU3;  /*!< (@ 0x0000106C) AXI Window Mask Upper Register 3                           */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31; /*!< [30..0] AWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_AWMASKU3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTL3_F0; /*!< (@ 0x00001070) AXI Destination (Lower) Register 3 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+                __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+            } PCI_EP_ADESTL3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTL3;  /*!< (@ 0x00001070) AXI Destination (Lower) Register 3                         */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12; /*!< [11..0] ADest11:0                                                         */
+                __IOM uint32_t AD3112 : 20; /*!< [31..12] ADest31:12                                                       */
+            } PCI_RC_ADESTL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTU3_F0; /*!< (@ 0x00001074) AXI Destination (Upper) Register 3 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+            } PCI_EP_ADESTU3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTU3;  /*!< (@ 0x00001074) AXI Destination (Upper) Register 3                         */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32; /*!< [31..0] ADest63:32                                                        */
+            } PCI_RC_ADESTU3_b;
+        };
+    };
+    __IM uint32_t RESERVED79[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEL4_F0; /*!< (@ 0x00001080) AXI Window Base (Lower) Register 4 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+                __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+            } PCI_EP_AWBASEL4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEL4;  /*!< (@ 0x00001080) AXI Window Base (Lower) Register 4                         */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;  /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;  /*!< [11..4] AWBase11:4                                                        */
+                __IOM uint32_t AWB3112 : 20; /*!< [31..12] AWBase31:12                                                      */
+            } PCI_RC_AWBASEL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEU4_F0; /*!< (@ 0x00001084) AXI Window Base (Upper) Register 4 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+            } PCI_EP_AWBASEU4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEU4;  /*!< (@ 0x00001084) AXI Window Base (Upper) Register 4                         */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32; /*!< [31..0] AWBase63:32                                                       */
+            } PCI_RC_AWBASEU4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKL4_F0; /*!< (@ 0x00001088) AXI Window Mask (Lower) Register 4 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+                __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+            } PCI_EP_AWMASKL4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKL4;  /*!< (@ 0x00001088) AXI Window Mask (Lower) Register 4                         */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12; /*!< [11..0] AWMask11:0                                                        */
+                __IOM uint32_t AWM3112 : 20; /*!< [31..12] AWMask31:12                                                      */
+            } PCI_RC_AWMASKL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKU4_F0; /*!< (@ 0x0000108C) AXI Window Mask (Upper) Register 4 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_AWMASKU4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKU4;  /*!< (@ 0x0000108C) AXI Window Mask Upper Register 4                           */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31; /*!< [30..0] AWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_AWMASKU4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTL4_F0; /*!< (@ 0x00001090) AXI Destination (Lower) Register 4 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+                __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+            } PCI_EP_ADESTL4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTL4;  /*!< (@ 0x00001090) AXI Destination (Lower) Register 4                         */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12; /*!< [11..0] ADest11:0                                                         */
+                __IOM uint32_t AD3112 : 20; /*!< [31..12] ADest31:12                                                       */
+            } PCI_RC_ADESTL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTU4_F0; /*!< (@ 0x00001094) AXI Destination (Upper) Register 4 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+            } PCI_EP_ADESTU4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTU4;  /*!< (@ 0x00001094) AXI Destination (Upper) Register 4                         */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32; /*!< [31..0] ADest63:32                                                        */
+            } PCI_RC_ADESTU4_b;
+        };
+    };
+    __IM uint32_t RESERVED80[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEL5_F0; /*!< (@ 0x000010A0) AXI Window Base (Lower) Register 5 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+                __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+            } PCI_EP_AWBASEL5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEL5;  /*!< (@ 0x000010A0) AXI Window Base (Lower) Register 5                         */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;  /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;  /*!< [11..4] AWBase11:4                                                        */
+                __IOM uint32_t AWB3112 : 20; /*!< [31..12] AWBase31:12                                                      */
+            } PCI_RC_AWBASEL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEU5_F0; /*!< (@ 0x000010A4) AXI Window Base (Upper) Register 5 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+            } PCI_EP_AWBASEU5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEU5;  /*!< (@ 0x000010A4) AXI Window Base (Upper) Register 5                         */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32; /*!< [31..0] AWBase63:32                                                       */
+            } PCI_RC_AWBASEU5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKL5_F0; /*!< (@ 0x000010A8) AXI Window Mask (Lower) Register 5 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+                __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+            } PCI_EP_AWMASKL5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKL5;  /*!< (@ 0x000010A8) AXI Window Mask (Lower) Register 5                         */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12; /*!< [11..0] AWMask11:0                                                        */
+                __IOM uint32_t AWM3112 : 20; /*!< [31..12] AWMask31:12                                                      */
+            } PCI_RC_AWMASKL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKU5_F0; /*!< (@ 0x000010AC) AXI Window Mask (Upper) Register 5 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_AWMASKU5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKU5;  /*!< (@ 0x000010AC) AXI Window Mask Upper Register 5                           */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31; /*!< [30..0] AWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_AWMASKU5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTL5_F0; /*!< (@ 0x000010B0) AXI Destination (Lower) Register 5 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+                __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+            } PCI_EP_ADESTL5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTL5;  /*!< (@ 0x000010B0) AXI Destination (Lower) Register 5                         */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12; /*!< [11..0] ADest11:0                                                         */
+                __IOM uint32_t AD3112 : 20; /*!< [31..12] ADest31:12                                                       */
+            } PCI_RC_ADESTL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTU5_F0; /*!< (@ 0x000010B4) AXI Destination (Upper) Register 5 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+            } PCI_EP_ADESTU5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTU5;  /*!< (@ 0x000010B4) AXI Destination (Upper) Register 5                         */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32; /*!< [31..0] ADest63:32                                                        */
+            } PCI_RC_ADESTU5_b;
+        };
+    };
+    __IM uint32_t RESERVED81[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEL6_F0; /*!< (@ 0x000010C0) AXI Window Base (Lower) Register 6 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+                __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+            } PCI_EP_AWBASEL6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEL6;  /*!< (@ 0x000010C0) AXI Window Base (Lower) Register 6                         */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;  /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;  /*!< [11..4] AWBase11:4                                                        */
+                __IOM uint32_t AWB3112 : 20; /*!< [31..12] AWBase31:12                                                      */
+            } PCI_RC_AWBASEL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEU6_F0; /*!< (@ 0x000010C4) AXI Window Base (Upper) Register 6 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+            } PCI_EP_AWBASEU6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEU6;  /*!< (@ 0x000010C4) AXI Window Base (Upper) Register 6                         */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32; /*!< [31..0] AWBase63:32                                                       */
+            } PCI_RC_AWBASEU6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKL6_F0; /*!< (@ 0x000010C8) AXI Window Mask (Lower) Register 6 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+                __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+            } PCI_EP_AWMASKL6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKL6;  /*!< (@ 0x000010C8) AXI Window Mask (Lower) Register 6                         */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12; /*!< [11..0] AWMask11:0                                                        */
+                __IOM uint32_t AWM3112 : 20; /*!< [31..12] AWMask31:12                                                      */
+            } PCI_RC_AWMASKL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKU6_F0; /*!< (@ 0x000010CC) AXI Window Mask (Upper) Register 6 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_AWMASKU6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKU6;  /*!< (@ 0x000010CC) AXI Window Mask Upper Register 6                           */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31; /*!< [30..0] AWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_AWMASKU6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTL6_F0; /*!< (@ 0x000010D0) AXI Destination (Lower) Register 6 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+                __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+            } PCI_EP_ADESTL6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTL6;  /*!< (@ 0x000010D0) AXI Destination (Lower) Register 6                         */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12; /*!< [11..0] ADest11:0                                                         */
+                __IOM uint32_t AD3112 : 20; /*!< [31..12] ADest31:12                                                       */
+            } PCI_RC_ADESTL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTU6_F0; /*!< (@ 0x000010D4) AXI Destination (Upper) Register 6 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+            } PCI_EP_ADESTU6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTU6;  /*!< (@ 0x000010D4) AXI Destination (Upper) Register 6                         */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32; /*!< [31..0] ADest63:32                                                        */
+            } PCI_RC_ADESTU6_b;
+        };
+    };
+    __IM uint32_t RESERVED82[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEL7_F0; /*!< (@ 0x000010E0) AXI Window Base (Lower) Register 7 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+                __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+            } PCI_EP_AWBASEL7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEL7;  /*!< (@ 0x000010E0) AXI Window Base (Lower) Register 7                         */
+
+            struct
+            {
+                __IOM uint32_t AXIWE   : 1;  /*!< [0..0] AXI Window Enable                                                  */
+                uint32_t               : 3;
+                __IM uint32_t  AWB1104 : 8;  /*!< [11..4] AWBase11:4                                                        */
+                __IOM uint32_t AWB3112 : 20; /*!< [31..12] AWBase31:12                                                      */
+            } PCI_RC_AWBASEL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWBASEU7_F0; /*!< (@ 0x000010E4) AXI Window Base (Upper) Register 7 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+            } PCI_EP_AWBASEU7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWBASEU7;  /*!< (@ 0x000010E4) AXI Window Base (Upper) Register 7                         */
+
+            struct
+            {
+                __IOM uint32_t AWB6332 : 32; /*!< [31..0] AWBase63:32                                                       */
+            } PCI_RC_AWBASEU7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKL7_F0; /*!< (@ 0x000010E8) AXI Window Mask (Lower) Register 7 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+                __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+            } PCI_EP_AWMASKL7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKL7;  /*!< (@ 0x000010E8) AXI Window Mask (Lower) Register 7                         */
+
+            struct
+            {
+                __IM uint32_t  AWM1100 : 12; /*!< [11..0] AWMask11:0                                                        */
+                __IOM uint32_t AWM3112 : 20; /*!< [31..12] AWMask31:12                                                      */
+            } PCI_RC_AWMASKL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_AWMASKU7_F0; /*!< (@ 0x000010EC) AXI Window Mask (Upper) Register 7 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_AWMASKU7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_AWMASKU7;  /*!< (@ 0x000010EC) AXI Window Mask Upper Register 7                           */
+
+            struct
+            {
+                __IOM uint32_t AWM6232 : 31; /*!< [30..0] AWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_AWMASKU7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTL7_F0; /*!< (@ 0x000010F0) AXI Destination (Lower) Register 7 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+                __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+            } PCI_EP_ADESTL7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTL7;  /*!< (@ 0x000010F0) AXI Destination (Lower) Register 7                         */
+
+            struct
+            {
+                __IM uint32_t  AD1100 : 12; /*!< [11..0] ADest11:0                                                         */
+                __IOM uint32_t AD3112 : 20; /*!< [31..12] ADest31:12                                                       */
+            } PCI_RC_ADESTL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADESTU7_F0; /*!< (@ 0x000010F4) AXI Destination (Upper) Register 7 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+            } PCI_EP_ADESTU7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADESTU7;  /*!< (@ 0x000010F4) AXI Destination (Upper) Register 7                         */
+
+            struct
+            {
+                __IOM uint32_t AD6332 : 32; /*!< [31..0] ADest63:32                                                        */
+            } PCI_RC_ADESTU7_b;
+        };
+    };
+    __IM uint32_t RESERVED83[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEL0_F0; /*!< (@ 0x00001100) PCIe Window Base (Lower) Register 0 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+                __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+            } PCI_EP_PWBASEL0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEL0;  /*!< (@ 0x00001100) PCIe Window Base (Lower) Register 0                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;  /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB1104 : 8;  /*!< [11..4] PWBase11:4                                                        */
+                __IOM uint32_t PWB3112 : 20; /*!< [31..12] PWBase31:12                                                      */
+            } PCI_RC_PWBASEL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEU0_F0; /*!< (@ 0x00001104) PCIe Window Base (Upper) Register 0 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+            } PCI_EP_PWBASEU0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEU0;  /*!< (@ 0x00001104) PCIe Window Base (Upper) Register 0                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32; /*!< [31..0] PWBase63:32                                                       */
+            } PCI_RC_PWBASEU0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKL0_F0; /*!< (@ 0x00001108) PCIe Window Mask (Lower) Register 0 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+                __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+            } PCI_EP_PWMASKL0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKL0;  /*!< (@ 0x00001108) PCIe Window Mask (Lower) Register 0                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12; /*!< [11..0] PWMask                                                            */
+                __IOM uint32_t PWM3112 : 20; /*!< [31..12] PWMask31:12                                                      */
+            } PCI_RC_PWMASKL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKU0_F0; /*!< (@ 0x0000110C) PCIe Window Mask (Upper) Register 0 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_PWMASKU0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKU0;  /*!< (@ 0x0000110C) PCIe Window Mask (Upper) Register 0                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31; /*!< [30..0] PWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_PWMASKU0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTL0_F0; /*!< (@ 0x00001110) PCIe Destination (Lower) Register 0 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+                __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+            } PCI_EP_PDESTL0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTL0;  /*!< (@ 0x00001110) PCIe Destination (Lower) Register 0                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12; /*!< [11..0] PDest11:0                                                         */
+                __IOM uint32_t PD3112 : 20; /*!< [31..12] PDest31:12                                                       */
+            } PCI_RC_PDESTL0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTU0_F0; /*!< (@ 0x00001114) PCIe Destination (Upper) Register 0 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+            } PCI_EP_PDESTU0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTU0;  /*!< (@ 0x00001114) PCIe Destination (Upper) Register 0                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32; /*!< [31..0] PDest63:32                                                        */
+            } PCI_RC_PDESTU0_b;
+        };
+    };
+    __IM uint32_t RESERVED84[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEL1_F0; /*!< (@ 0x00001120) PCIe Window Base (Lower) Register 1 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+                __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+            } PCI_EP_PWBASEL1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEL1;  /*!< (@ 0x00001120) PCIe Window Base (Lower) Register 1                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;  /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB1104 : 8;  /*!< [11..4] PWBase11:4                                                        */
+                __IOM uint32_t PWB3112 : 20; /*!< [31..12] PWBase31:12                                                      */
+            } PCI_RC_PWBASEL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEU1_F0; /*!< (@ 0x00001124) PCIe Window Base (Upper) Register 1 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+            } PCI_EP_PWBASEU1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEU1;  /*!< (@ 0x00001124) PCIe Window Base (Upper) Register 1                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32; /*!< [31..0] PWBase63:32                                                       */
+            } PCI_RC_PWBASEU1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKL1_F0; /*!< (@ 0x00001128) PCIe Window Mask (Lower) Register 1 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+                __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+            } PCI_EP_PWMASKL1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKL1;  /*!< (@ 0x00001128) PCIe Window Mask (Lower) Register 1                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12; /*!< [11..0] PWMask                                                            */
+                __IOM uint32_t PWM3112 : 20; /*!< [31..12] PWMask31:12                                                      */
+            } PCI_RC_PWMASKL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKU1_F0; /*!< (@ 0x0000112C) PCIe Window Mask (Upper) Register 1 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_PWMASKU1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKU1;  /*!< (@ 0x0000112C) PCIe Window Mask (Upper) Register 1                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31; /*!< [30..0] PWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_PWMASKU1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTL1_F0; /*!< (@ 0x00001130) PCIe Destination (Lower) Register 1 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+                __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+            } PCI_EP_PDESTL1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTL1;  /*!< (@ 0x00001130) PCIe Destination (Lower) Register 1                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12; /*!< [11..0] PDest11:0                                                         */
+                __IOM uint32_t PD3112 : 20; /*!< [31..12] PDest31:12                                                       */
+            } PCI_RC_PDESTL1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTU1_F0; /*!< (@ 0x00001134) PCIe Destination (Upper) Register 1 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+            } PCI_EP_PDESTU1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTU1;  /*!< (@ 0x00001134) PCIe Destination (Upper) Register 1                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32; /*!< [31..0] PDest63:32                                                        */
+            } PCI_RC_PDESTU1_b;
+        };
+    };
+    __IM uint32_t RESERVED85[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEL2_F0; /*!< (@ 0x00001140) PCIe Window Base (Lower) Register 2 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+                __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+            } PCI_EP_PWBASEL2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEL2;  /*!< (@ 0x00001140) PCIe Window Base (Lower) Register 2                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;  /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB1104 : 8;  /*!< [11..4] PWBase11:4                                                        */
+                __IOM uint32_t PWB3112 : 20; /*!< [31..12] PWBase31:12                                                      */
+            } PCI_RC_PWBASEL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEU2_F0; /*!< (@ 0x00001144) PCIe Window Base (Upper) Register 2 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+            } PCI_EP_PWBASEU2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEU2;  /*!< (@ 0x00001144) PCIe Window Base (Upper) Register 2                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32; /*!< [31..0] PWBase63:32                                                       */
+            } PCI_RC_PWBASEU2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKL2_F0; /*!< (@ 0x00001148) PCIe Window Mask (Lower) Register 2 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+                __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+            } PCI_EP_PWMASKL2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKL2;  /*!< (@ 0x00001148) PCIe Window Mask (Lower) Register 2                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12; /*!< [11..0] PWMask                                                            */
+                __IOM uint32_t PWM3112 : 20; /*!< [31..12] PWMask31:12                                                      */
+            } PCI_RC_PWMASKL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKU2_F0; /*!< (@ 0x0000114C) PCIe Window Mask (Upper) Register 2 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_PWMASKU2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKU2;  /*!< (@ 0x0000114C) PCIe Window Mask (Upper) Register 2                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31; /*!< [30..0] PWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_PWMASKU2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTL2_F0; /*!< (@ 0x00001150) PCIe Destination (Lower) Register 2 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+                __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+            } PCI_EP_PDESTL2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTL2;  /*!< (@ 0x00001150) PCIe Destination (Lower) Register 2                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12; /*!< [11..0] PDest11:0                                                         */
+                __IOM uint32_t PD3112 : 20; /*!< [31..12] PDest31:12                                                       */
+            } PCI_RC_PDESTL2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTU2_F0; /*!< (@ 0x00001154) PCIe Destination (Upper) Register 2 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+            } PCI_EP_PDESTU2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTU2;  /*!< (@ 0x00001154) PCIe Destination (Upper) Register 2                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32; /*!< [31..0] PDest63:32                                                        */
+            } PCI_RC_PDESTU2_b;
+        };
+    };
+    __IM uint32_t RESERVED86[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEL3_F0; /*!< (@ 0x00001160) PCIe Window Base (Lower) Register 3 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+                __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+            } PCI_EP_PWBASEL3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEL3;  /*!< (@ 0x00001160) PCIe Window Base (Lower) Register 3                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;  /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB1104 : 8;  /*!< [11..4] PWBase11:4                                                        */
+                __IOM uint32_t PWB3112 : 20; /*!< [31..12] PWBase31:12                                                      */
+            } PCI_RC_PWBASEL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEU3_F0; /*!< (@ 0x00001164) PCIe Window Base (Upper) Register 3 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+            } PCI_EP_PWBASEU3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEU3;  /*!< (@ 0x00001164) PCIe Window Base (Upper) Register 3                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32; /*!< [31..0] PWBase63:32                                                       */
+            } PCI_RC_PWBASEU3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKL3_F0; /*!< (@ 0x00001168) PCIe Window Mask (Lower) Register 3 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+                __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+            } PCI_EP_PWMASKL3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKL3;  /*!< (@ 0x00001168) PCIe Window Mask (Lower) Register 3                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12; /*!< [11..0] PWMask                                                            */
+                __IOM uint32_t PWM3112 : 20; /*!< [31..12] PWMask31:12                                                      */
+            } PCI_RC_PWMASKL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKU3_F0; /*!< (@ 0x0000116C) PCIe Window Mask (Upper) Register 3 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_PWMASKU3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKU3;  /*!< (@ 0x0000116C) PCIe Window Mask (Upper) Register 3                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31; /*!< [30..0] PWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_PWMASKU3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTL3_F0; /*!< (@ 0x00001170) PCIe Destination (Lower) Register 3 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+                __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+            } PCI_EP_PDESTL3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTL3;  /*!< (@ 0x00001170) PCIe Destination (Lower) Register 3                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12; /*!< [11..0] PDest11:0                                                         */
+                __IOM uint32_t PD3112 : 20; /*!< [31..12] PDest31:12                                                       */
+            } PCI_RC_PDESTL3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTU3_F0; /*!< (@ 0x00001174) PCIe Destination (Upper) Register 3 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+            } PCI_EP_PDESTU3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTU3;  /*!< (@ 0x00001174) PCIe Destination (Upper) Register 3                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32; /*!< [31..0] PDest63:32                                                        */
+            } PCI_RC_PDESTU3_b;
+        };
+    };
+    __IM uint32_t RESERVED87[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEL4_F0; /*!< (@ 0x00001180) PCIe Window Base (Lower) Register 4 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+                __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+            } PCI_EP_PWBASEL4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEL4;  /*!< (@ 0x00001180) PCIe Window Base (Lower) Register 4                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;  /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB1104 : 8;  /*!< [11..4] PWBase11:4                                                        */
+                __IOM uint32_t PWB3112 : 20; /*!< [31..12] PWBase31:12                                                      */
+            } PCI_RC_PWBASEL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEU4_F0; /*!< (@ 0x00001184) PCIe Window Base (Upper) Register 4 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+            } PCI_EP_PWBASEU4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEU4;  /*!< (@ 0x00001184) PCIe Window Base (Upper) Register 4                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32; /*!< [31..0] PWBase63:32                                                       */
+            } PCI_RC_PWBASEU4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKL4_F0; /*!< (@ 0x00001188) PCIe Window Mask (Lower) Register 4 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+                __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+            } PCI_EP_PWMASKL4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKL4;  /*!< (@ 0x00001188) PCIe Window Mask (Lower) Register 4                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12; /*!< [11..0] PWMask                                                            */
+                __IOM uint32_t PWM3112 : 20; /*!< [31..12] PWMask31:12                                                      */
+            } PCI_RC_PWMASKL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKU4_F0; /*!< (@ 0x0000118C) PCIe Window Mask (Upper) Register 4 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_PWMASKU4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKU4;  /*!< (@ 0x0000118C) PCIe Window Mask (Upper) Register 4                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31; /*!< [30..0] PWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_PWMASKU4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTL4_F0; /*!< (@ 0x00001190) PCIe Destination (Lower) Register 4 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+                __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+            } PCI_EP_PDESTL4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTL4;  /*!< (@ 0x00001190) PCIe Destination (Lower) Register 4                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12; /*!< [11..0] PDest11:0                                                         */
+                __IOM uint32_t PD3112 : 20; /*!< [31..12] PDest31:12                                                       */
+            } PCI_RC_PDESTL4_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTU4_F0; /*!< (@ 0x00001194) PCIe Destination (Upper) Register 4 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+            } PCI_EP_PDESTU4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTU4;  /*!< (@ 0x00001194) PCIe Destination (Upper) Register 4                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32; /*!< [31..0] PDest63:32                                                        */
+            } PCI_RC_PDESTU4_b;
+        };
+    };
+    __IM uint32_t RESERVED88[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEL5_F0; /*!< (@ 0x000011A0) PCIe Window Base (Lower) Register 5 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+                __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+            } PCI_EP_PWBASEL5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEL5;  /*!< (@ 0x000011A0) PCIe Window Base (Lower) Register 5                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;  /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB1104 : 8;  /*!< [11..4] PWBase11:4                                                        */
+                __IOM uint32_t PWB3112 : 20; /*!< [31..12] PWBase31:12                                                      */
+            } PCI_RC_PWBASEL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEU5_F0; /*!< (@ 0x000011A4) PCIe Window Base (Upper) Register 5 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+            } PCI_EP_PWBASEU5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEU5;  /*!< (@ 0x000011A4) PCIe Window Base (Upper) Register 5                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32; /*!< [31..0] PWBase63:32                                                       */
+            } PCI_RC_PWBASEU5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKL5_F0; /*!< (@ 0x000011A8) PCIe Window Mask (Lower) Register 5 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+                __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+            } PCI_EP_PWMASKL5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKL5;  /*!< (@ 0x000011A8) PCIe Window Mask (Lower) Register 5                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12; /*!< [11..0] PWMask                                                            */
+                __IOM uint32_t PWM3112 : 20; /*!< [31..12] PWMask31:12                                                      */
+            } PCI_RC_PWMASKL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKU5_F0; /*!< (@ 0x000011AC) PCIe Window Mask (Upper) Register 5 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_PWMASKU5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKU5;  /*!< (@ 0x000011AC) PCIe Window Mask (Upper) Register 5                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31; /*!< [30..0] PWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_PWMASKU5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTL5_F0; /*!< (@ 0x000011B0) PCIe Destination (Lower) Register 5 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+                __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+            } PCI_EP_PDESTL5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTL5;  /*!< (@ 0x000011B0) PCIe Destination (Lower) Register 5                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12; /*!< [11..0] PDest11:0                                                         */
+                __IOM uint32_t PD3112 : 20; /*!< [31..12] PDest31:12                                                       */
+            } PCI_RC_PDESTL5_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTU5_F0; /*!< (@ 0x000011B4) PCIe Destination (Upper) Register 5 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+            } PCI_EP_PDESTU5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTU5;  /*!< (@ 0x000011B4) PCIe Destination (Upper) Register 5                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32; /*!< [31..0] PDest63:32                                                        */
+            } PCI_RC_PDESTU5_b;
+        };
+    };
+    __IM uint32_t RESERVED89[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEL6_F0; /*!< (@ 0x000011C0) PCIe Window Base (Lower) Register 6 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+                __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+            } PCI_EP_PWBASEL6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEL6;  /*!< (@ 0x000011C0) PCIe Window Base (Lower) Register 6                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;  /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB1104 : 8;  /*!< [11..4] PWBase11:4                                                        */
+                __IOM uint32_t PWB3112 : 20; /*!< [31..12] PWBase31:12                                                      */
+            } PCI_RC_PWBASEL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEU6_F0; /*!< (@ 0x000011C4) PCIe Window Base (Upper) Register 6 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+            } PCI_EP_PWBASEU6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEU6;  /*!< (@ 0x000011C4) PCIe Window Base (Upper) Register 6                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32; /*!< [31..0] PWBase63:32                                                       */
+            } PCI_RC_PWBASEU6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKL6_F0; /*!< (@ 0x000011C8) PCIe Window Mask (Lower) Register 6 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+                __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+            } PCI_EP_PWMASKL6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKL6;  /*!< (@ 0x000011C8) PCIe Window Mask (Lower) Register 6                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12; /*!< [11..0] PWMask                                                            */
+                __IOM uint32_t PWM3112 : 20; /*!< [31..12] PWMask31:12                                                      */
+            } PCI_RC_PWMASKL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKU6_F0; /*!< (@ 0x000011CC) PCIe Window Mask (Upper) Register 6 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_PWMASKU6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKU6;  /*!< (@ 0x000011CC) PCIe Window Mask (Upper) Register 6                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31; /*!< [30..0] PWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_PWMASKU6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTL6_F0; /*!< (@ 0x000011D0) PCIe Destination (Lower) Register 6 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+                __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+            } PCI_EP_PDESTL6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTL6;  /*!< (@ 0x000011D0) PCIe Destination (Lower) Register 6                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12; /*!< [11..0] PDest11:0                                                         */
+                __IOM uint32_t PD3112 : 20; /*!< [31..12] PDest31:12                                                       */
+            } PCI_RC_PDESTL6_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTU6_F0; /*!< (@ 0x000011D4) PCIe Destination (Upper) Register 6 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+            } PCI_EP_PDESTU6_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTU6;  /*!< (@ 0x000011D4) PCIe Destination (Upper) Register 6                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32; /*!< [31..0] PDest63:32                                                        */
+            } PCI_RC_PDESTU6_b;
+        };
+    };
+    __IM uint32_t RESERVED90[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEL7_F0; /*!< (@ 0x000011E0) PCIe Window Base (Lower) Register 7 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+                __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+            } PCI_EP_PWBASEL7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEL7;  /*!< (@ 0x000011E0) PCIe Window Base (Lower) Register 7                        */
+
+            struct
+            {
+                __IOM uint32_t PCIWE   : 1;  /*!< [0..0] PCIe Window Enable                                                 */
+                uint32_t               : 3;
+                __IM uint32_t  PWB1104 : 8;  /*!< [11..4] PWBase11:4                                                        */
+                __IOM uint32_t PWB3112 : 20; /*!< [31..12] PWBase31:12                                                      */
+            } PCI_RC_PWBASEL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWBASEU7_F0; /*!< (@ 0x000011E4) PCIe Window Base (Upper) Register 7 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+            } PCI_EP_PWBASEU7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWBASEU7;  /*!< (@ 0x000011E4) PCIe Window Base (Upper) Register 7                        */
+
+            struct
+            {
+                __IOM uint32_t PWB6332 : 32; /*!< [31..0] PWBase63:32                                                       */
+            } PCI_RC_PWBASEU7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKL7_F0; /*!< (@ 0x000011E8) PCIe Window Mask (Lower) Register 7 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+                __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+            } PCI_EP_PWMASKL7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKL7;  /*!< (@ 0x000011E8) PCIe Window Mask (Lower) Register 7                        */
+
+            struct
+            {
+                __IM uint32_t  PWM1100 : 12; /*!< [11..0] PWMask                                                            */
+                __IOM uint32_t PWM3112 : 20; /*!< [31..12] PWMask31:12                                                      */
+            } PCI_RC_PWMASKL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PWMASKU7_F0; /*!< (@ 0x000011EC) PCIe Window Mask (Upper) Register 7 (Function
+                                                #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+                uint32_t               : 1;
+            } PCI_EP_PWMASKU7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PWMASKU7;  /*!< (@ 0x000011EC) PCIe Window Mask (Upper) Register 7                        */
+
+            struct
+            {
+                __IOM uint32_t PWM6232 : 31; /*!< [30..0] PWMask62:32                                                       */
+                uint32_t               : 1;
+            } PCI_RC_PWMASKU7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTL7_F0; /*!< (@ 0x000011F0) PCIe Destination (Lower) Register 7 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+                __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+            } PCI_EP_PDESTL7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTL7;  /*!< (@ 0x000011F0) PCIe Destination (Lower) Register 7                        */
+
+            struct
+            {
+                __IM uint32_t  PD1100 : 12; /*!< [11..0] PDest11:0                                                         */
+                __IOM uint32_t PD3112 : 20; /*!< [31..12] PDest31:12                                                       */
+            } PCI_RC_PDESTL7_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PDESTU7_F0; /*!< (@ 0x000011F4) PCIe Destination (Upper) Register 7 (Function
+                                               #0)                                                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+            } PCI_EP_PDESTU7_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PDESTU7;  /*!< (@ 0x000011F4) PCIe Destination (Upper) Register 7                        */
+
+            struct
+            {
+                __IOM uint32_t PD6332 : 32; /*!< [31..0] PDest63:32                                                        */
+            } PCI_RC_PDESTU7_b;
+        };
+    };
+    __IM uint32_t RESERVED91[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEL0_F1; /*!< (@ 0x00001200) AXI Window Base (Lower) Register 0 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+            uint32_t               : 3;
+            __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+            __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+        } PCI_EP_AWBASEL0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEU0_F1; /*!< (@ 0x00001204) AXI Window Base (Upper) Register 0 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+        } PCI_EP_AWBASEU0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKL0_F1; /*!< (@ 0x00001208) AXI Window Mask (Lower) Register 0 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+            __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+        } PCI_EP_AWMASKL0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKU0_F1; /*!< (@ 0x0000120C) AXI Window Mask (Upper) Register 0 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_AWMASKU0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTL0_F1; /*!< (@ 0x00001210) AXI Destination (Lower) Register 0 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+            __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+        } PCI_EP_ADESTL0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTU0_F1; /*!< (@ 0x00001214) AXI Destination (Upper) Register 0 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+        } PCI_EP_ADESTU0_F1_b;
+    };
+    __IM uint32_t RESERVED92[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEL1_F1; /*!< (@ 0x00001220) AXI Window Base (Lower) Register 1 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+            uint32_t               : 3;
+            __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+            __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+        } PCI_EP_AWBASEL1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEU1_F1; /*!< (@ 0x00001224) AXI Window Base (Upper) Register 1 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+        } PCI_EP_AWBASEU1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKL1_F1; /*!< (@ 0x00001228) AXI Window Mask (Lower) Register 1 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+            __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+        } PCI_EP_AWMASKL1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKU1_F1; /*!< (@ 0x0000122C) AXI Window Mask (Upper) Register 1 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_AWMASKU1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTL1_F1; /*!< (@ 0x00001230) AXI Destination (Lower) Register 1 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+            __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+        } PCI_EP_ADESTL1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTU1_F1; /*!< (@ 0x00001234) AXI Destination (Upper) Register 1 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+        } PCI_EP_ADESTU1_F1_b;
+    };
+    __IM uint32_t RESERVED93[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEL2_F1; /*!< (@ 0x00001240) AXI Window Base (Lower) Register 2 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+            uint32_t               : 3;
+            __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+            __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+        } PCI_EP_AWBASEL2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEU2_F1; /*!< (@ 0x00001244) AXI Window Base (Upper) Register 2 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+        } PCI_EP_AWBASEU2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKL2_F1; /*!< (@ 0x00001248) AXI Window Mask (Lower) Register 2 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+            __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+        } PCI_EP_AWMASKL2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKU2_F1; /*!< (@ 0x0000124C) AXI Window Mask (Upper) Register 2 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_AWMASKU2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTL2_F1; /*!< (@ 0x00001250) AXI Destination (Lower) Register 2 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+            __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+        } PCI_EP_ADESTL2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTU2_F1; /*!< (@ 0x00001254) AXI Destination (Upper) Register 2 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+        } PCI_EP_ADESTU2_F1_b;
+    };
+    __IM uint32_t RESERVED94[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEL3_F1; /*!< (@ 0x00001260) AXI Window Base (Lower) Register 3 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+            uint32_t               : 3;
+            __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+            __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+        } PCI_EP_AWBASEL3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEU3_F1; /*!< (@ 0x00001264) AXI Window Base (Upper) Register 3 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+        } PCI_EP_AWBASEU3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKL3_F1; /*!< (@ 0x00001268) AXI Window Mask (Lower) Register 3 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+            __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+        } PCI_EP_AWMASKL3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKU3_F1; /*!< (@ 0x0000126C) AXI Window Mask (Upper) Register 3 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_AWMASKU3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTL3_F1; /*!< (@ 0x00001270) AXI Destination (Lower) Register 3 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+            __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+        } PCI_EP_ADESTL3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTU3_F1; /*!< (@ 0x00001274) AXI Destination (Upper) Register 3 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+        } PCI_EP_ADESTU3_F1_b;
+    };
+    __IM uint32_t RESERVED95[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEL4_F1; /*!< (@ 0x00001280) AXI Window Base (Lower) Register 4 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+            uint32_t               : 3;
+            __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+            __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+        } PCI_EP_AWBASEL4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEU4_F1; /*!< (@ 0x00001284) AXI Window Base (Upper) Register 4 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+        } PCI_EP_AWBASEU4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKL4_F1; /*!< (@ 0x00001288) AXI Window Mask (Lower) Register 4 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+            __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+        } PCI_EP_AWMASKL4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKU4_F1; /*!< (@ 0x0000128C) AXI Window Mask (Upper) Register 4 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_AWMASKU4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTL4_F1; /*!< (@ 0x00001290) AXI Destination (Lower) Register 4 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+            __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+        } PCI_EP_ADESTL4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTU4_F1; /*!< (@ 0x00001294) AXI Destination (Upper) Register 4 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+        } PCI_EP_ADESTU4_F1_b;
+    };
+    __IM uint32_t RESERVED96[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEL5_F1; /*!< (@ 0x000012A0) AXI Window Base (Lower) Register 5 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+            uint32_t               : 3;
+            __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+            __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+        } PCI_EP_AWBASEL5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEU5_F1; /*!< (@ 0x000012A4) AXI Window Base (Upper) Register 5 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+        } PCI_EP_AWBASEU5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKL5_F1; /*!< (@ 0x000012A8) AXI Window Mask (Lower) Register 5 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+            __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+        } PCI_EP_AWMASKL5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKU5_F1; /*!< (@ 0x000012AC) AXI Window Mask (Upper) Register 5 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_AWMASKU5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTL5_F1; /*!< (@ 0x000012B0) AXI Destination (Lower) Register 5 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+            __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+        } PCI_EP_ADESTL5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTU5_F1; /*!< (@ 0x000012B4) AXI Destination (Upper) Register 5 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+        } PCI_EP_ADESTU5_F1_b;
+    };
+    __IM uint32_t RESERVED97[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEL6_F1; /*!< (@ 0x000012C0) AXI Window Base (Lower) Register 6 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+            uint32_t               : 3;
+            __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+            __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+        } PCI_EP_AWBASEL6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEU6_F1; /*!< (@ 0x000012C4) AXI Window Base (Upper) Register 6 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+        } PCI_EP_AWBASEU6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKL6_F1; /*!< (@ 0x000012C8) AXI Window Mask (Lower) Register 6 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+            __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+        } PCI_EP_AWMASKL6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKU6_F1; /*!< (@ 0x000012CC) AXI Window Mask (Upper) Register 6 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_AWMASKU6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTL6_F1; /*!< (@ 0x000012D0) AXI Destination (Lower) Register 6 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+            __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+        } PCI_EP_ADESTL6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTU6_F1; /*!< (@ 0x000012D4) AXI Destination (Upper) Register 6 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+        } PCI_EP_ADESTU6_F1_b;
+    };
+    __IM uint32_t RESERVED98[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEL7_F1; /*!< (@ 0x000012E0) AXI Window Base (Lower) Register 7 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AXIWE   : 1;    /*!< [0..0] AXI Window Enable                                                  */
+            uint32_t               : 3;
+            __IM uint32_t  AWB1104 : 8;    /*!< [11..4] AWBase[11:4]                                                      */
+            __IOM uint32_t AWB3112 : 20;   /*!< [31..12] AWBase[31:12]                                                    */
+        } PCI_EP_AWBASEL7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWBASEU7_F1; /*!< (@ 0x000012E4) AXI Window Base (Upper) Register 7 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWB6332 : 32;   /*!< [31..0] AWBase[63:32]                                                     */
+        } PCI_EP_AWBASEU7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKL7_F1; /*!< (@ 0x000012E8) AXI Window Mask (Lower) Register 7 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AWM1100 : 12;   /*!< [11..0] AWMask[11:0]                                                      */
+            __IOM uint32_t AWM3112 : 20;   /*!< [31..12] AWMask[31:12]                                                    */
+        } PCI_EP_AWMASKL7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_AWMASKU7_F1; /*!< (@ 0x000012EC) AXI Window Mask (Upper) Register 7 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AWM6232 : 31;   /*!< [30..0] AWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_AWMASKU7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTL7_F1; /*!< (@ 0x000012F0) AXI Destination (Lower) Register 7 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  AD1100 : 12;   /*!< [11..0] ADest[11:0]                                                       */
+            __IOM uint32_t AD3112 : 20;   /*!< [31..12] ADest[31:12]                                                     */
+        } PCI_EP_ADESTL7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADESTU7_F1; /*!< (@ 0x000012F4) AXI Destination (Upper) Register 7 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t AD6332 : 32;   /*!< [31..0] ADest[63:32]                                                      */
+        } PCI_EP_ADESTU7_F1_b;
+    };
+    __IM uint32_t RESERVED99[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEL0_F1; /*!< (@ 0x00001300) PCIe Window Base (Lower) Register 0 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+            uint32_t               : 3;
+            __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+            __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+        } PCI_EP_PWBASEL0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEU0_F1; /*!< (@ 0x00001304) PCIe Window Base (Upper) Register 0 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+        } PCI_EP_PWBASEU0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKL0_F1; /*!< (@ 0x00001308) PCIe Window Mask (Lower) Register 0 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+            __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+        } PCI_EP_PWMASKL0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKU0_F1; /*!< (@ 0x0000130C) PCIe Window Mask (Upper) Register 0 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_PWMASKU0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTL0_F1; /*!< (@ 0x00001310) PCIe Destination (Lower) Register 0 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+            __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+        } PCI_EP_PDESTL0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTU0_F1; /*!< (@ 0x00001314) PCIe Destination (Upper) Register 0 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+        } PCI_EP_PDESTU0_F1_b;
+    };
+    __IM uint32_t RESERVED100[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEL1_F1; /*!< (@ 0x00001320) PCIe Window Base (Lower) Register 1 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+            uint32_t               : 3;
+            __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+            __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+        } PCI_EP_PWBASEL1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEU1_F1; /*!< (@ 0x00001324) PCIe Window Base (Upper) Register 1 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+        } PCI_EP_PWBASEU1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKL1_F1; /*!< (@ 0x00001328) PCIe Window Mask (Lower) Register 1 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+            __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+        } PCI_EP_PWMASKL1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKU1_F1; /*!< (@ 0x0000132C) PCIe Window Mask (Upper) Register 1 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_PWMASKU1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTL1_F1; /*!< (@ 0x00001330) PCIe Destination (Lower) Register 1 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+            __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+        } PCI_EP_PDESTL1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTU1_F1; /*!< (@ 0x00001334) PCIe Destination (Upper) Register 1 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+        } PCI_EP_PDESTU1_F1_b;
+    };
+    __IM uint32_t RESERVED101[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEL2_F1; /*!< (@ 0x00001340) PCIe Window Base (Lower) Register 2 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+            uint32_t               : 3;
+            __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+            __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+        } PCI_EP_PWBASEL2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEU2_F1; /*!< (@ 0x00001344) PCIe Window Base (Upper) Register 2 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+        } PCI_EP_PWBASEU2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKL2_F1; /*!< (@ 0x00001348) PCIe Window Mask (Lower) Register 2 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+            __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+        } PCI_EP_PWMASKL2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKU2_F1; /*!< (@ 0x0000134C) PCIe Window Mask (Upper) Register 2 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_PWMASKU2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTL2_F1; /*!< (@ 0x00001350) PCIe Destination (Lower) Register 2 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+            __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+        } PCI_EP_PDESTL2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTU2_F1; /*!< (@ 0x00001354) PCIe Destination (Upper) Register 2 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+        } PCI_EP_PDESTU2_F1_b;
+    };
+    __IM uint32_t RESERVED102[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEL3_F1; /*!< (@ 0x00001360) PCIe Window Base (Lower) Register 3 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+            uint32_t               : 3;
+            __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+            __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+        } PCI_EP_PWBASEL3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEU3_F1; /*!< (@ 0x00001364) PCIe Window Base (Upper) Register 3 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+        } PCI_EP_PWBASEU3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKL3_F1; /*!< (@ 0x00001368) PCIe Window Mask (Lower) Register 3 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+            __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+        } PCI_EP_PWMASKL3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKU3_F1; /*!< (@ 0x0000136C) PCIe Window Mask (Upper) Register 3 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_PWMASKU3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTL3_F1; /*!< (@ 0x00001370) PCIe Destination (Lower) Register 3 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+            __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+        } PCI_EP_PDESTL3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTU3_F1; /*!< (@ 0x00001374) PCIe Destination (Upper) Register 3 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+        } PCI_EP_PDESTU3_F1_b;
+    };
+    __IM uint32_t RESERVED103[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEL4_F1; /*!< (@ 0x00001380) PCIe Window Base (Lower) Register 4 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+            uint32_t               : 3;
+            __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+            __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+        } PCI_EP_PWBASEL4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEU4_F1; /*!< (@ 0x00001384) PCIe Window Base (Upper) Register 4 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+        } PCI_EP_PWBASEU4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKL4_F1; /*!< (@ 0x00001388) PCIe Window Mask (Lower) Register 4 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+            __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+        } PCI_EP_PWMASKL4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKU4_F1; /*!< (@ 0x0000138C) PCIe Window Mask (Upper) Register 4 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_PWMASKU4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTL4_F1; /*!< (@ 0x00001390) PCIe Destination (Lower) Register 4 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+            __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+        } PCI_EP_PDESTL4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTU4_F1; /*!< (@ 0x00001394) PCIe Destination (Upper) Register 4 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+        } PCI_EP_PDESTU4_F1_b;
+    };
+    __IM uint32_t RESERVED104[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEL5_F1; /*!< (@ 0x000013A0) PCIe Window Base (Lower) Register 5 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+            uint32_t               : 3;
+            __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+            __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+        } PCI_EP_PWBASEL5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEU5_F1; /*!< (@ 0x000013A4) PCIe Window Base (Upper) Register 5 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+        } PCI_EP_PWBASEU5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKL5_F1; /*!< (@ 0x000013A8) PCIe Window Mask (Lower) Register 5 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+            __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+        } PCI_EP_PWMASKL5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKU5_F1; /*!< (@ 0x000013AC) PCIe Window Mask (Upper) Register 5 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_PWMASKU5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTL5_F1; /*!< (@ 0x000013B0) PCIe Destination (Lower) Register 5 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+            __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+        } PCI_EP_PDESTL5_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTU5_F1; /*!< (@ 0x000013B4) PCIe Destination (Upper) Register 5 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+        } PCI_EP_PDESTU5_F1_b;
+    };
+    __IM uint32_t RESERVED105[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEL6_F1; /*!< (@ 0x000013C0) PCIe Window Base (Lower) Register 6 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+            uint32_t               : 3;
+            __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+            __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+        } PCI_EP_PWBASEL6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEU6_F1; /*!< (@ 0x000013C4) PCIe Window Base (Upper) Register 6 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+        } PCI_EP_PWBASEU6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKL6_F1; /*!< (@ 0x000013C8) PCIe Window Mask (Lower) Register 6 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+            __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+        } PCI_EP_PWMASKL6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKU6_F1; /*!< (@ 0x000013CC) PCIe Window Mask (Upper) Register 6 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_PWMASKU6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTL6_F1; /*!< (@ 0x000013D0) PCIe Destination (Lower) Register 6 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+            __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+        } PCI_EP_PDESTL6_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTU6_F1; /*!< (@ 0x000013D4) PCIe Destination (Upper) Register 6 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+        } PCI_EP_PDESTU6_F1_b;
+    };
+    __IM uint32_t RESERVED106[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEL7_F1; /*!< (@ 0x000013E0) PCIe Window Base (Lower) Register 7 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PCIWE   : 1;    /*!< [0..0] PCIe Window Enable                                                 */
+            uint32_t               : 3;
+            __IM uint32_t  PWB114  : 8;    /*!< [11..4] PWBase[11:4]                                                      */
+            __IOM uint32_t PWB3112 : 20;   /*!< [31..12] PWBase[31:12]                                                    */
+        } PCI_EP_PWBASEL7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWBASEU7_F1; /*!< (@ 0x000013E4) PCIe Window Base (Upper) Register 7 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWB6332 : 32;   /*!< [31..0] PWBase[63:32]                                                     */
+        } PCI_EP_PWBASEU7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKL7_F1; /*!< (@ 0x000013E8) PCIe Window Mask (Lower) Register 7 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PWM1100 : 12;   /*!< [11..0] PWMask[11:0]                                                      */
+            __IOM uint32_t PWM3112 : 20;   /*!< [31..12] PWMask[31:12]                                                    */
+        } PCI_EP_PWMASKL7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PWMASKU7_F1; /*!< (@ 0x000013EC) PCIe Window Mask (Upper) Register 7 (Function
+                                            #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PWM6232 : 31;   /*!< [30..0] PWMask[62:32]                                                     */
+            uint32_t               : 1;
+        } PCI_EP_PWMASKU7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTL7_F1; /*!< (@ 0x000013F0) PCIe Destination (Lower) Register 7 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PD1100 : 12;   /*!< [11..0] PDest[11:0]                                                       */
+            __IOM uint32_t PD3112 : 20;   /*!< [31..12] PDest[31:12]                                                     */
+        } PCI_EP_PDESTL7_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PDESTU7_F1; /*!< (@ 0x000013F4) PCIe Destination (Upper) Register 7 (Function
+                                           #1)                                                        */
+
+        struct
+        {
+            __IOM uint32_t PD6332 : 32;   /*!< [31..0] PDest[63:32]                                                      */
+        } PCI_EP_PDESTU7_F1_b;
+    };
+    __IM uint32_t RESERVED107[4866];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_VID_F0; /*!< (@ 0x00006000) Vendor and Device ID (Function #i)                         */
+
+            struct
+            {
+                __IOM uint32_t VID : 16;  /*!< [15..0] Vendor ID                                                         */
+                __IOM uint32_t DID : 16;  /*!< [31..16] Device ID                                                        */
+            } PCI_EP_VID_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_VID;   /*!< (@ 0x00006000) Vendor and Device ID Register                              */
+
+            struct
+            {
+                __IOM uint32_t VID : 16; /*!< [15..0] Vendor ID                                                         */
+                __IOM uint32_t DID : 16; /*!< [31..16] Device ID                                                        */
+            } PCI_RC_VID_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_COM_STA_F0; /*!< (@ 0x00006004) Command and Status (Function #i)                           */
+
+            struct
+            {
+                __IM uint32_t  IOSE  : 1;     /*!< [0..0] IO Space Enable                                                    */
+                __IOM uint32_t MSE   : 1;     /*!< [1..1] Memory Space Enable                                                */
+                __IOM uint32_t BME   : 1;     /*!< [2..2] Bus Master Enable                                                  */
+                uint32_t             : 3;
+                __IOM uint32_t PER   : 1;     /*!< [6..6] Parity Error Response                                              */
+                uint32_t             : 1;
+                __IOM uint32_t SERRE : 1;     /*!< [8..8] SERR# Enable                                                       */
+                uint32_t             : 1;
+                __IOM uint32_t ID    : 1;     /*!< [10..10] Interrupt Disable                                                */
+                uint32_t             : 5;
+                __IM uint32_t IR     : 1;     /*!< [16..16] Fixed 0                                                          */
+                uint32_t             : 2;
+                __IM uint32_t IS     : 1;     /*!< [19..19] Interrupt Status                                                 */
+                __IM uint32_t CL     : 1;     /*!< [20..20] Capabilities List                                                */
+                uint32_t             : 3;
+                __IOM uint32_t MDPE  : 1;     /*!< [24..24] Master Data Parity Error                                         */
+                uint32_t             : 2;
+                __IOM uint32_t STA   : 1;     /*!< [27..27] Signaled Target Abort                                            */
+                __IOM uint32_t RTA   : 1;     /*!< [28..28] Received Target Abort                                            */
+                __IOM uint32_t RMA   : 1;     /*!< [29..29] Received Master Abort                                            */
+                __IOM uint32_t SSE   : 1;     /*!< [30..30] Signaled System Error                                            */
+                __IOM uint32_t DPE   : 1;     /*!< [31..31] Detected Parity Error                                            */
+            } PCI_EP_COM_STA_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_COM_STA; /*!< (@ 0x00006004) Command and Status Register                                */
+
+            struct
+            {
+                __IM uint32_t  IOSE  : 1;  /*!< [0..0] IO Space Enable                                                    */
+                __IOM uint32_t MSE   : 1;  /*!< [1..1] Memory Space Enable                                                */
+                __IOM uint32_t BME   : 1;  /*!< [2..2] Bus Master Enable                                                  */
+                uint32_t             : 3;
+                __IOM uint32_t PER   : 1;  /*!< [6..6] Parity Error Response                                              */
+                uint32_t             : 1;
+                __IOM uint32_t SERRE : 1;  /*!< [8..8] SERR# Enable                                                       */
+                uint32_t             : 1;
+                __IOM uint32_t ID    : 1;  /*!< [10..10] Interrupt Disable                                                */
+                uint32_t             : 8;
+                __IM uint32_t IS     : 1;  /*!< [19..19] Interrupt Status                                                 */
+                __IM uint32_t CL     : 1;  /*!< [20..20] Capabilities List                                                */
+                uint32_t             : 9;
+                __IOM uint32_t SSE   : 1;  /*!< [30..30] Signaled System Error                                            */
+                uint32_t             : 1;
+            } PCI_RC_COM_STA_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_RID_CC_F0; /*!< (@ 0x00006008) Revision ID and Class Code (Function #i)                   */
+
+            struct
+            {
+                __IOM uint32_t RID : 8;      /*!< [7..0] Revision ID                                                        */
+                __IOM uint32_t CC  : 24;     /*!< [31..8] Class Code                                                        */
+            } PCI_EP_RID_CC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_RID_CC; /*!< (@ 0x00006008) Revision ID and Class Code Register                        */
+
+            struct
+            {
+                __IOM uint32_t RID : 8;   /*!< [7..0] Revision ID                                                        */
+                __IOM uint32_t CC  : 24;  /*!< [31..8] Class Code                                                        */
+            } PCI_RC_RID_CC_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_CL_HT_F0; /*!< (@ 0x0000600C) Cache Line and Header Type (Function #i)                   */
+
+            struct
+            {
+                __IM uint32_t CLS : 8;     /*!< [7..0] Cache Line Size                                                    */
+                uint32_t          : 8;
+                __IM uint32_t HT  : 8;     /*!< [23..16] Header Type                                                      */
+                uint32_t          : 8;
+            } PCI_EP_CL_HT_F0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_CL_HT; /*!< (@ 0x0000600C) Cache Line and Header Type Register                        */
+
+            struct
+            {
+                __IM uint32_t CLS : 8;  /*!< [7..0] Cache Line Size                                                    */
+                uint32_t          : 8;
+                __IM uint32_t HT  : 8;  /*!< [23..16] Header Type                                                      */
+                uint32_t          : 8;
+            } PCI_RC_CL_HT_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BAR0_F0; /*!< (@ 0x00006010) Base Address Register 0 (Function #i)                      */
+
+            struct
+            {
+                __IOM uint32_t MSI  : 1;   /*!< [0..0] Memory Space Indicator                                             */
+                uint32_t            : 1;
+                __IOM uint32_t TYPE : 1;   /*!< [2..2] Type                                                               */
+                __IOM uint32_t PF   : 1;   /*!< [3..3] Prefetch                                                           */
+                __IOM uint32_t BAR0 : 28;  /*!< [31..4] Base Address Register 0                                           */
+            } PCI_EP_BAR0_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_BAR0;   /*!< (@ 0x00006010) Base Address Register 0                                    */
+
+            struct
+            {
+                __IM uint32_t MSI   : 1;  /*!< [0..0] Memory Space Indicator                                             */
+                uint32_t            : 1;
+                __IM uint32_t  TYPE : 1;  /*!< [2..2] Type                                                               */
+                __IOM uint32_t PF   : 1;  /*!< [3..3] Prefetch                                                           */
+                __IOM uint32_t BAR0 : 28; /*!< [31..4] Base Address Register 0                                           */
+            } PCI_RC_BAR0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BAR1_F0; /*!< (@ 0x00006014) Base Address Register 1 (Function #i)                      */
+
+            struct
+            {
+                __IOM uint32_t BAR1 : 32;  /*!< [31..0] Base Address Register 1 (64-bit Upper Address)                    */
+            } PCI_EP_BAR1_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_BAR1;   /*!< (@ 0x00006014) Base Address Register 1                                    */
+
+            struct
+            {
+                __IOM uint32_t BAR1 : 32; /*!< [31..0] Base Address Register 1 (64-bit Upper Address)                    */
+            } PCI_RC_BAR1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BAR2_F0; /*!< (@ 0x00006018) Base Address Register 2 (Function #i)                      */
+
+            struct
+            {
+                __IM uint32_t MSI   : 1;   /*!< [0..0] Memory Space Indicator                                             */
+                uint32_t            : 1;
+                __IOM uint32_t TYPE : 1;   /*!< [2..2] Type                                                               */
+                __IOM uint32_t PF   : 1;   /*!< [3..3] Prefetch                                                           */
+                __IOM uint32_t BAR2 : 28;  /*!< [31..4] Base Address Register 2                                           */
+            } PCI_EP_BAR2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_BNR;  /*!< (@ 0x00006018) Bus Number Register                                        */
+
+            struct
+            {
+                __IOM uint32_t PBN : 8; /*!< [7..0] Primary Bus Number                                                 */
+                __IOM uint32_t SBN : 8; /*!< [15..8] Secondary Bus Number                                              */
+                __IOM uint32_t SB  : 8; /*!< [23..16] Subordinate Bus                                                  */
+                uint32_t           : 8;
+            } PCI_RC_BNR_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BAR3_F0; /*!< (@ 0x0000601C) Base Address Register 3 (Function #i)                      */
+
+            struct
+            {
+                __IOM uint32_t BAR3 : 32;  /*!< [31..0] Base Address Register 3 (64-bit Upper Address)                    */
+            } PCI_EP_BAR3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_IOBL_SS; /*!< (@ 0x0000601C) I/O Base/ Limit and Secondary Status                       */
+
+            struct
+            {
+                __IOM uint32_t IOB  : 8;   /*!< [7..0] IO Base                                                            */
+                __IOM uint32_t IOL  : 8;   /*!< [15..8] IO Limit                                                          */
+                uint32_t            : 8;
+                __IOM uint32_t MDPE : 1;   /*!< [24..24] Master Data Parity Error                                         */
+                uint32_t            : 2;
+                __IOM uint32_t STA  : 1;   /*!< [27..27] Signaled Target Abort                                            */
+                __IOM uint32_t RTA  : 1;   /*!< [28..28] Received Target Abort                                            */
+                __IOM uint32_t RMA  : 1;   /*!< [29..29] Received Master Abort                                            */
+                __IOM uint32_t RSE  : 1;   /*!< [30..30] Received System Error                                            */
+                __IOM uint32_t DPE  : 1;   /*!< [31..31] Detected Parity Error                                            */
+            } PCI_RC_IOBL_SS_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BAR4_F0; /*!< (@ 0x00006020) Base Address Register 4 (Function #i)                      */
+
+            struct
+            {
+                __IM uint32_t MSI   : 1;   /*!< [0..0] Memory Space Indicator                                             */
+                uint32_t            : 1;
+                __IOM uint32_t TYPE : 1;   /*!< [2..2] Type                                                               */
+                __IOM uint32_t PF   : 1;   /*!< [3..3] Prefetch                                                           */
+                __IOM uint32_t BAR4 : 28;  /*!< [31..4] Base Address Register 4                                           */
+            } PCI_EP_BAR4_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_MEMBL; /*!< (@ 0x00006020) Memory Base/ Limit Register                                */
+
+            struct
+            {
+                uint32_t          : 4;
+                __IOM uint32_t MB : 12; /*!< [15..4] Memory Base                                                       */
+                uint32_t          : 4;
+                __IOM uint32_t ML : 12; /*!< [31..20] Memory Limit                                                     */
+            } PCI_RC_MEMBL_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BAR5_F0; /*!< (@ 0x00006024) Base Address Register 5 (Function #i)                      */
+
+            struct
+            {
+                __IOM uint32_t BAR5 : 32;  /*!< [31..0] Base Address Register 5 (64-bit Upper Address)                    */
+            } PCI_EP_BAR5_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PMBL;  /*!< (@ 0x00006024) Prefetchable Memory Base/ Limit Register                   */
+
+            struct
+            {
+                __IOM uint32_t PMB : 16; /*!< [15..0] Prefetchable Memory Base                                          */
+                __IOM uint32_t PML : 16; /*!< [31..16] Prefetchable Memory Limit                                        */
+            } PCI_RC_PMBL_b;
+        };
+    };
+    __IOM uint32_t PCI_RC_PBUP32;        /*!< (@ 0x00006028) Prefetchable Base Upper 32 Bits Register                   */
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_SUBSID_F0; /*!< (@ 0x0000602C) Subsystem ID (Function #i)                                 */
+
+            struct
+            {
+                __IOM uint32_t SVID : 16;    /*!< [15..0] Subsystem Vendor ID                                               */
+                __IOM uint32_t SID  : 16;    /*!< [31..16] Subsystem ID                                                     */
+            } PCI_EP_SUBSID_F0_b;
+        };
+        __IOM uint32_t PCI_RC_PLUP32;        /*!< (@ 0x0000602C) Prefetchable Limit Upper 32 Bits Register                  */
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_IOBLUP16; /*!< (@ 0x00006030) I/O Base/Limit Upper 16 bits Register                      */
+
+        struct
+        {
+            __IOM uint32_t IOBU16 : 16; /*!< [15..0] IO Base Upper 16 bits                                             */
+            __IOM uint32_t IOLU16 : 16; /*!< [31..16] IO Limit Upper 16 bits                                           */
+        } PCI_RC_IOBLUP16_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_CP_F0; /*!< (@ 0x00006034) Capabilities Pointer (Function #i)                         */
+
+            struct
+            {
+                __IM uint32_t CP : 8;   /*!< [7..0] Capabilities Pointer                                               */
+                uint32_t         : 24;
+            } PCI_EP_CP_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_CP;  /*!< (@ 0x00006034) Capabilities Pointer Register                              */
+
+            struct
+            {
+                __IOM uint32_t CP : 8; /*!< [7..0] Capability Pointer                                                 */
+                uint32_t          : 24;
+            } PCI_RC_CP_b;
+        };
+    };
+    __IM uint32_t RESERVED108;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_INT_F0; /*!< (@ 0x0000603C) Interrupt Register (Function #i)                           */
+
+            struct
+            {
+                __IOM uint32_t IL : 8;    /*!< [7..0] Interrupt Line                                                     */
+                __IOM uint32_t IP : 8;    /*!< [15..8] Interrupt Pin                                                     */
+                uint32_t          : 16;
+            } PCI_EP_INT_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_BC_INT;  /*!< (@ 0x0000603C) Bridge Control and Interrupt                               */
+
+            struct
+            {
+                __IOM uint32_t IL     : 8; /*!< [7..0] Interrupt Line                                                     */
+                __IOM uint32_t IP     : 8; /*!< [15..8] Interrupt Pin                                                     */
+                __IOM uint32_t PERE   : 1; /*!< [16..16] Parity Error Response Enable                                     */
+                __IOM uint32_t SERRE  : 1; /*!< [17..17] SERR# Enable                                                     */
+                __IOM uint32_t ISAE   : 1; /*!< [18..18] ISA Enable                                                       */
+                __IOM uint32_t VGAE   : 1; /*!< [19..19] VGA Enable                                                       */
+                __IOM uint32_t VGA16D : 1; /*!< [20..20] VGA 16-bit Decode                                                */
+                uint32_t              : 1;
+                __IOM uint32_t SBR    : 1; /*!< [22..22] Secondary Bus Reset                                              */
+                uint32_t              : 9;
+            } PCI_RC_BC_INT_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PMC_F0;   /*!< (@ 0x00006040) PM Capabilities (Function #i)                              */
+
+            struct
+            {
+                __IM uint32_t  CID     : 8; /*!< [7..0] Capability ID                                                      */
+                __IM uint32_t  NCP     : 8; /*!< [15..8] Next Capability Pointer                                           */
+                __IOM uint32_t V       : 3; /*!< [18..16] Version                                                          */
+                uint32_t               : 1;
+                __IM uint32_t  IRORTD0 : 1; /*!< [20..20] Immediate_Readiness_on_Return_to_D0                              */
+                __IOM uint32_t DSI     : 1; /*!< [21..21] Device Specific Initialization                                   */
+                __IOM uint32_t AUXC    : 3; /*!< [24..22] AUX_Current                                                      */
+                __IOM uint32_t D1S     : 1; /*!< [25..25] D1 Support                                                       */
+                __IOM uint32_t D2S     : 1; /*!< [26..26] D2 Support                                                       */
+                __IOM uint32_t PMES    : 5; /*!< [31..27] PME Support                                                      */
+            } PCI_EP_PMC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PMC;    /*!< (@ 0x00006040) PM Capabilities                                            */
+
+            struct
+            {
+                __IM uint32_t  CID   : 8; /*!< [7..0] Capability ID                                                      */
+                __IM uint32_t  NCP   : 8; /*!< [15..8] Next Capability Pointer                                           */
+                __IOM uint32_t V     : 3; /*!< [18..16] Version                                                          */
+                uint32_t             : 1;
+                __IM uint32_t  IRRD0 : 1; /*!< [20..20] Immediate_Readiness_on_Return_to_D0                              */
+                __IOM uint32_t DSI   : 1; /*!< [21..21] Device Specific Initialization (DSI)                             */
+                __IOM uint32_t AUXC  : 3; /*!< [24..22] AUX_Current                                                      */
+                __IOM uint32_t D1S   : 1; /*!< [25..25] D1 Support                                                       */
+                __IOM uint32_t D2S   : 1; /*!< [26..26] D2 Support                                                       */
+                __IOM uint32_t PMES  : 5; /*!< [31..27] PME Support                                                      */
+            } PCI_RC_PMC_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PMSC_F0; /*!< (@ 0x00006044) PM Status/Control (Function #i)                            */
+
+            struct
+            {
+                __IOM uint32_t PS   : 2;   /*!< [1..0] PowerState                                                         */
+                uint32_t            : 1;
+                __IM uint32_t NSR   : 1;   /*!< [3..3] No_Soft_Reset                                                      */
+                uint32_t            : 4;
+                __IOM uint32_t PMEE : 1;   /*!< [8..8] PME Enable                                                         */
+                uint32_t            : 6;
+                __IOM uint32_t PMES : 1;   /*!< [15..15] PME Status                                                       */
+                uint32_t            : 16;
+            } PCI_EP_PMSC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PMSC;  /*!< (@ 0x00006044) PM Status/Control Register                                 */
+
+            struct
+            {
+                __IOM uint32_t PS   : 2; /*!< [1..0] PowerState                                                         */
+                uint32_t            : 1;
+                __IM uint32_t NSR   : 1; /*!< [3..3] No_Soft_Reset                                                      */
+                uint32_t            : 4;
+                __IOM uint32_t PMEE : 1; /*!< [8..8] PME Enable                                                         */
+                uint32_t            : 6;
+                __IOM uint32_t PMES : 1; /*!< [15..15] PME Status                                                       */
+                uint32_t            : 16;
+            } PCI_RC_PMSC_b;
+        };
+    };
+    __IM uint32_t RESERVED109[6];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_PCIEC_F0; /*!< (@ 0x00006060) PCI Express Capability (Function #i)                       */
+
+            struct
+            {
+                __IM uint32_t  CID : 8;     /*!< [7..0] Capability ID                                                      */
+                __IM uint32_t  NCP : 8;     /*!< [15..8] Next Capability Pointer                                           */
+                __IOM uint32_t CV  : 4;     /*!< [19..16] Capability Version                                               */
+                __IOM uint32_t DPT : 4;     /*!< [23..20] DevicePort Type                                                  */
+                uint32_t           : 1;
+                __IOM uint32_t IMN : 5;     /*!< [29..25] Interrupt Message Number                                         */
+                uint32_t           : 2;
+            } PCI_EP_PCIEC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_PCIEC; /*!< (@ 0x00006060) PCI Express Capability Register                            */
+
+            struct
+            {
+                __IM uint32_t  CID : 8;  /*!< [7..0] Capability ID                                                      */
+                __IOM uint32_t NCP : 8;  /*!< [15..8] Next Capability Pointer                                           */
+                __IOM uint32_t CV  : 4;  /*!< [19..16] Capability Version                                               */
+                __IM uint32_t  DPT : 4;  /*!< [23..20] DevicePort Type                                                  */
+                __IOM uint32_t SI  : 1;  /*!< [24..24] Slot Implemented                                                 */
+                __IM uint32_t  IMN : 5;  /*!< [29..25] Interrupt Message Number                                         */
+                uint32_t           : 2;
+            } PCI_RC_PCIEC_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DEVC_F0; /*!< (@ 0x00006064) Device Capabilities (Function #i)                          */
+
+            struct
+            {
+                __IOM uint32_t MPSS  : 3;  /*!< [2..0] Max_Payload_Size Supported                                         */
+                uint32_t             : 2;
+                __IOM uint32_t ETFS  : 1;  /*!< [5..5] Extended Tag Field Supported                                       */
+                __IOM uint32_t EL0AL : 3;  /*!< [8..6] Endpoint L0 Acceptable Latency                                     */
+                __IOM uint32_t EL1AL : 3;  /*!< [11..9] Endpoint L1 Acceptable Latency                                    */
+                uint32_t             : 3;
+                __IM uint32_t RBER   : 1;  /*!< [15..15] Role-Based Error Reporting                                       */
+                uint32_t             : 2;
+                __IOM uint32_t CSPLV : 8;  /*!< [25..18] Captured Slot Power Limit Value                                  */
+                __IOM uint32_t CSPLS : 2;  /*!< [27..26] Captured Slot Power Limit Scale                                  */
+                __IOM uint32_t FLRC  : 1;  /*!< [28..28] Function Level Reset Capability                                  */
+                uint32_t             : 3;
+            } PCI_EP_DEVC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DEVC;  /*!< (@ 0x00006064) Device Capabilities Register                               */
+
+            struct
+            {
+                __IOM uint32_t MPSS : 3; /*!< [2..0] Max_Payload_Size Supported                                         */
+                uint32_t            : 12;
+                __IM uint32_t RBER  : 1; /*!< [15..15] Role-Based Error Reporting                                       */
+                uint32_t            : 16;
+            } PCI_RC_DEVC_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DEVCS_F0; /*!< (@ 0x00006068) Device Control/Status (Function #i)                        */
+
+            struct
+            {
+                __IOM uint32_t CERE  : 1;   /*!< [0..0] Correctable Error Reporting Enable                                 */
+                __IOM uint32_t NFERE : 1;   /*!< [1..1] Non-Fatal Error Reporting Enable                                   */
+                __IOM uint32_t FERE  : 1;   /*!< [2..2] Fatal Error Reporting Enable                                       */
+                __IOM uint32_t URRE  : 1;   /*!< [3..3] Unsupported Request Reporting Enable                               */
+                __IOM uint32_t ERO   : 1;   /*!< [4..4] Enable Relaxed Ordering                                            */
+                __IOM uint32_t MPS   : 3;   /*!< [7..5] Max_Payload_Size                                                   */
+                uint32_t             : 4;
+                __IOM uint32_t MRRS  : 3;   /*!< [14..12] Max_Read_Request_Size                                            */
+                __IOM uint32_t IFLR  : 1;   /*!< [15..15] Initiate Function Level Reset                                    */
+                __IOM uint32_t CED   : 1;   /*!< [16..16] Correctable Error Detected                                       */
+                __IOM uint32_t NFED  : 1;   /*!< [17..17] Non-Fatal Error Detected                                         */
+                __IOM uint32_t FED   : 1;   /*!< [18..18] Fatal Error Detected                                             */
+                __IOM uint32_t URD   : 1;   /*!< [19..19] Unsupported Request Detected                                     */
+                uint32_t             : 1;
+                __IM uint32_t TP     : 1;   /*!< [21..21] Transaction Pending                                              */
+                uint32_t             : 10;
+            } PCI_EP_DEVCS_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DEVCS;  /*!< (@ 0x00006068) Device Control/Status Register                             */
+
+            struct
+            {
+                __IOM uint32_t CERE  : 1; /*!< [0..0] Correctable Error Reporting Enable                                 */
+                __IOM uint32_t NFERE : 1; /*!< [1..1] Non-Fatal Error Reporting Enable                                   */
+                __IOM uint32_t FERE  : 1; /*!< [2..2] Fatal Error Reporting Enable                                       */
+                __IOM uint32_t URRE  : 1; /*!< [3..3] Unsupported Request Reporting Enable                               */
+                __IOM uint32_t ERO   : 1; /*!< [4..4] Enable Relaxed Ordering                                            */
+                __IOM uint32_t MPS   : 3; /*!< [7..5] Max_Payload_Size                                                   */
+                uint32_t             : 4;
+                __IOM uint32_t MRRS  : 3; /*!< [14..12] Max_Read_Request_Size                                            */
+                uint32_t             : 1;
+                __IOM uint32_t CED   : 1; /*!< [16..16] Correctable Error Detected                                       */
+                __IOM uint32_t NFED  : 1; /*!< [17..17] Non-Fatal Error Detected                                         */
+                __IOM uint32_t FED   : 1; /*!< [18..18] Fatal Error Detected                                             */
+                __IOM uint32_t URD   : 1; /*!< [19..19] Unsupported Request Detected                                     */
+                uint32_t             : 12;
+            } PCI_RC_DEVCS_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_LINKC_F0; /*!< (@ 0x0000606C) Link Capabilities (Function #i)                            */
+
+            struct
+            {
+                __IOM uint32_t MLS    : 4;  /*!< [3..0] Max Link Speed                                                     */
+                __IOM uint32_t MLW    : 6;  /*!< [9..4] Maximum Link Width                                                 */
+                __IOM uint32_t ASPMS  : 2;  /*!< [11..10] Active State Power Management (ASPM) Support                     */
+                __IOM uint32_t L0EL   : 3;  /*!< [14..12] L0s Exit Latency                                                 */
+                __IOM uint32_t L1EL   : 3;  /*!< [17..15] L1 Exit Latency                                                  */
+                __IOM uint32_t CPM    : 1;  /*!< [18..18] Clock Power Management                                           */
+                uint32_t              : 3;
+                __IOM uint32_t ASPMOC : 1;  /*!< [22..22] ASPM Optionality Compliance                                      */
+                uint32_t              : 1;
+                __IOM uint32_t PN     : 8;  /*!< [31..24] Port Number                                                      */
+            } PCI_EP_LINKC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_LINKC;    /*!< (@ 0x0000606C) Link Capabilities Register                                 */
+
+            struct
+            {
+                __IOM uint32_t SLS     : 4; /*!< [3..0] Supported Link Speed                                               */
+                __IOM uint32_t MLW     : 6; /*!< [9..4] Maximum Link Width                                                 */
+                __IOM uint32_t ASPMS   : 2; /*!< [11..10] Active State Power Management (ASPM) Support                     */
+                __IOM uint32_t L0EL    : 3; /*!< [14..12] L0s Exit Latency                                                 */
+                __IOM uint32_t L1EL    : 3; /*!< [17..15] L1 Exit Latency                                                  */
+                uint32_t               : 2;
+                __IOM uint32_t DLLLARC : 1; /*!< [20..20] Data Link Layer Link Active Reporting Capable                    */
+                __IOM uint32_t LBNC    : 1; /*!< [21..21] Link Bandwidth Notification Capability                           */
+                __IOM uint32_t ASPMOC  : 1; /*!< [22..22] ASPM Optionality Compliance                                      */
+                uint32_t               : 1;
+                __IOM uint32_t PN      : 8; /*!< [31..24] Port Number                                                      */
+            } PCI_RC_LINKC_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_LINKCS_F0; /*!< (@ 0x00006070) Link Control/Status (Function #i)                          */
+
+            struct
+            {
+                __IOM uint32_t ASPMC : 2;    /*!< [1..0] Active State Power Management (ASPM) Control                       */
+                uint32_t             : 1;
+                __IOM uint32_t RCB   : 1;    /*!< [3..3] Read Completion Boundary (RCB)                                     */
+                uint32_t             : 2;
+                __IOM uint32_t CCC   : 1;    /*!< [6..6] Common Clock Configuration                                         */
+                __IOM uint32_t ES    : 1;    /*!< [7..7] Extended Synch                                                     */
+                __IOM uint32_t ECPM  : 1;    /*!< [8..8] Enable Clock Power Management                                      */
+                __IOM uint32_t HAWD  : 1;    /*!< [9..9] Hardware Autonomous Width Disable                                  */
+                uint32_t             : 6;
+                __IM uint32_t CLS    : 4;    /*!< [19..16] Current Link Speed                                               */
+                __IM uint32_t NLW    : 6;    /*!< [25..20] Negotiated Link Width                                            */
+                uint32_t             : 2;
+                __IOM uint32_t SCC   : 1;    /*!< [28..28] Slot Clock Configuration                                         */
+                __IM uint32_t  DLLLA : 1;    /*!< [29..29] Data Link Layer Link Active                                      */
+                uint32_t             : 2;
+            } PCI_EP_LINKCS_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_LINKCS; /*!< (@ 0x00006070) Link Control/Status Register                               */
+
+            struct
+            {
+                __IOM uint32_t ASPMC : 2; /*!< [1..0] Active State Power Management (ASPM) Control                       */
+                uint32_t             : 1;
+                __IM uint32_t  RCB   : 1; /*!< [3..3] Read Completion Boundary (RCB)                                     */
+                __IOM uint32_t LD    : 1; /*!< [4..4] Link Disable                                                       */
+                __IOM uint32_t RL    : 1; /*!< [5..5] Retrain Link                                                       */
+                __IOM uint32_t CCC   : 1; /*!< [6..6] Common Clock Configuration                                         */
+                __IOM uint32_t ES    : 1; /*!< [7..7] Extended Synch                                                     */
+                uint32_t             : 1;
+                __IOM uint32_t HAWD  : 1; /*!< [9..9] Hardware Autonomous Width Disable                                  */
+                __IOM uint32_t LBMIE : 1; /*!< [10..10] Link Bandwidth Management Interrupt Enable                       */
+                __IOM uint32_t LABIE : 1; /*!< [11..11] Link Autonomous Bandwidth Interrupt Enable                       */
+                uint32_t             : 4;
+                __IM uint32_t CLS    : 4; /*!< [19..16] Current Link Speed                                               */
+                __IM uint32_t NLW    : 6; /*!< [25..20] Negotiated Link Width                                            */
+                uint32_t             : 1;
+                __IM uint32_t  LT    : 1; /*!< [27..27] Link Training                                                    */
+                __IOM uint32_t SCC   : 1; /*!< [28..28] Slot Clock Configuration                                         */
+                __IM uint32_t  DLLLA : 1; /*!< [29..29] Data Link Layer Link Active                                      */
+                __IOM uint32_t LBMS  : 1; /*!< [30..30] Link Bandwidth Management Status                                 */
+                __IOM uint32_t LABS  : 1; /*!< [31..31] Link Autonomous Bandwidth Status                                 */
+            } PCI_RC_LINKCS_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_SLOTC;   /*!< (@ 0x00006074) Slot Capabilities                                          */
+
+        struct
+        {
+            __IOM uint32_t ABP   : 1;  /*!< [0..0] Attention Button Present                                           */
+            __IOM uint32_t PCP   : 1;  /*!< [1..1] Power Control Present                                              */
+            __IOM uint32_t MRLSP : 1;  /*!< [2..2] MRL Sensor Present                                                 */
+            __IOM uint32_t AIP   : 1;  /*!< [3..3] Attention Indicator Present                                        */
+            __IOM uint32_t PIP   : 1;  /*!< [4..4] Power Indicator Present                                            */
+            __IOM uint32_t HPS   : 1;  /*!< [5..5] Hot-Plug Surprise                                                  */
+            __IOM uint32_t HPC   : 1;  /*!< [6..6] Hot-Plug Capable                                                   */
+            __IOM uint32_t SPLV  : 8;  /*!< [14..7] Slot Power Limit Value                                            */
+            __IOM uint32_t SPLS  : 2;  /*!< [16..15] Slot Power Limit Scale                                           */
+            __IOM uint32_t EIP   : 1;  /*!< [17..17] Electromechanical Interlock Present                              */
+            __IOM uint32_t NCCS  : 1;  /*!< [18..18] No Command Completed Support                                     */
+            __IOM uint32_t PSN   : 13; /*!< [31..19] Physical Slot Number                                             */
+        } PCI_RC_SLOTC_b;
+    };
+    __IM uint32_t PCI_RC_SLOTCS;       /*!< (@ 0x00006078) Slot Control/Status                                        */
+
+    union
+    {
+        __IOM uint32_t PCI_RC_ROOTCC;  /*!< (@ 0x0000607C) Root Control/Capabilities                                  */
+
+        struct
+        {
+            __IOM uint32_t SECEE  : 1; /*!< [0..0] System Error on Correctable Error Enable                           */
+            __IOM uint32_t SENFEE : 1; /*!< [1..1] System Error on Non-Fatal Error Enable                             */
+            __IOM uint32_t SEFEE  : 1; /*!< [2..2] System Error on Fatal Error Enable                                 */
+            __IOM uint32_t PMEIE  : 1; /*!< [3..3] PME Interrupt Enable                                               */
+            uint32_t              : 28;
+        } PCI_RC_ROOTCC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_ROOTS;    /*!< (@ 0x00006080) Root Status                                                */
+
+        struct
+        {
+            __IM uint32_t  PMERID : 16; /*!< [15..0] PME Requester ID                                                  */
+            __IOM uint32_t PMES   : 1;  /*!< [16..16] PME Status                                                       */
+            __IM uint32_t  PMEP   : 1;  /*!< [17..17] PME Pending                                                      */
+            uint32_t              : 14;
+        } PCI_RC_ROOTS_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DEVC2_F0; /*!< (@ 0x00006084) Device Capabilities 2 (Function #i)                        */
+
+            struct
+            {
+                __IOM uint32_t CTRS : 4;    /*!< [3..0] Completion Timeout Ranges Supported                                */
+                __IOM uint32_t CTDS : 1;    /*!< [4..4] Completion Timeout Disable Supported                               */
+                uint32_t            : 27;
+            } PCI_EP_DEVC2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DEVC2; /*!< (@ 0x00006084) Device Capabilities 2 Register                             */
+
+            struct
+            {
+                __IOM uint32_t CTRS : 4; /*!< [3..0] Completion Timeout Ranges Supported                                */
+                __IOM uint32_t CTDS : 1; /*!< [4..4] Completion Timeout Disable Supported                               */
+                uint32_t            : 27;
+            } PCI_RC_DEVC2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DEVCS2_F0; /*!< (@ 0x00006088) Device Control 2/Status 2 (Function #i)                    */
+
+            struct
+            {
+                __IOM uint32_t CTV : 4;      /*!< [3..0] Completion Timeout Value                                           */
+                __IOM uint32_t CTD : 1;      /*!< [4..4] Completion Timeout Disable                                         */
+                uint32_t           : 27;
+            } PCI_EP_DEVCS2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DEVCS2; /*!< (@ 0x00006088) Device Control 2/Status 2 Register                         */
+
+            struct
+            {
+                __IOM uint32_t CTV : 4;   /*!< [3..0] Completion Timeout Value                                           */
+                __IOM uint32_t CTD : 1;   /*!< [4..4] Completion Timeout Disable                                         */
+                uint32_t           : 27;
+            } PCI_RC_DEVCS2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_LINKC2_F0; /*!< (@ 0x0000608C) Link Capabilities 2 (Function #i)                          */
+
+            struct
+            {
+                uint32_t            : 1;
+                __IOM uint32_t SLSV : 7; /*!< [7..1] Supported Link Speeds Vector                                       */
+                uint32_t            : 24;
+            } PCI_EP_LINKC2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_LINKC2; /*!< (@ 0x0000608C) Link Capabilities 2 Register                               */
+
+            struct
+            {
+                uint32_t            : 1;
+                __IOM uint32_t SLSV : 7; /*!< [7..1] Supported Link Speeds Vector                                       */
+                uint32_t            : 24;
+            } PCI_RC_LINKC2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_LINKCS2_F0; /*!< (@ 0x00006090) Link Control 2/Status 2 (Function #n)                      */
+
+            struct
+            {
+                __IOM uint32_t TLS  : 4;      /*!< [3..0] Target Link Speed                                                  */
+                __IOM uint32_t ETC  : 1;      /*!< [4..4] Enter Compliance                                                   */
+                __IOM uint32_t HASD : 1;      /*!< [5..5] Hardware Autonomous Speed Disable                                  */
+                uint32_t            : 1;
+                __IOM uint32_t TM   : 3;      /*!< [9..7] Transmit Margin                                                    */
+                __IOM uint32_t EMC  : 1;      /*!< [10..10] Enter Modified Compliance                                        */
+                __IOM uint32_t CSOS : 1;      /*!< [11..11] Compliance SOS                                                   */
+                __IOM uint32_t CPD  : 4;      /*!< [15..12] Compliance Preset De-emphasis                                    */
+                __IM uint32_t  CDL  : 1;      /*!< [16..16] Current De-emphasis Level                                        */
+                __IM uint32_t  EQC  : 1;      /*!< [17..17] Equalization Complete                                            */
+                __IM uint32_t  EP1S : 1;      /*!< [18..18] Equalization Phase 1 Successful                                  */
+                __IM uint32_t  EP2S : 1;      /*!< [19..19] Equalization Phase 2 Successful                                  */
+                __IM uint32_t  EP3S : 1;      /*!< [20..20] Equalization Phase 3 Successful                                  */
+                __IOM uint32_t LER  : 1;      /*!< [21..21] Link Equalization Request                                        */
+                uint32_t            : 10;
+            } PCI_EP_LINKCS2_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_LINKCS2; /*!< (@ 0x00006090) Link Control 2/Status 2 Register                           */
+
+            struct
+            {
+                __IOM uint32_t TLS  : 4;   /*!< [3..0] Target Link Speed                                                  */
+                __IOM uint32_t ETC  : 1;   /*!< [4..4] Enter Compliance                                                   */
+                __IOM uint32_t HASD : 1;   /*!< [5..5] Hardware Autonomous Speed Disable                                  */
+                __IOM uint32_t SD   : 1;   /*!< [6..6] Selectable Deemphasis                                              */
+                __IOM uint32_t TM   : 3;   /*!< [9..7] Transmit Margin                                                    */
+                __IOM uint32_t EMC  : 1;   /*!< [10..10] Enter Modified Compliance                                        */
+                __IOM uint32_t CSOS : 1;   /*!< [11..11] Compliance SOS                                                   */
+                __IOM uint32_t CPD  : 4;   /*!< [15..12] Compliance Preset De-emphasis                                    */
+                __IM uint32_t  CDL  : 1;   /*!< [16..16] Current De-emphasis Level                                        */
+                __IM uint32_t  EQC  : 1;   /*!< [17..17] Equalization Complete                                            */
+                __IM uint32_t  EP1S : 1;   /*!< [18..18] Equalization Phase 1 Successful                                  */
+                __IM uint32_t  EP2S : 1;   /*!< [19..19] Equalization Phase 2 Successful                                  */
+                __IM uint32_t  EP3S : 1;   /*!< [20..20] Equalization Phase 3 Successful                                  */
+                __IOM uint32_t LER  : 1;   /*!< [21..21] Link Equalization Request                                        */
+                uint32_t            : 10;
+            } PCI_RC_LINKCS2_b;
+        };
+    };
+    __IM uint32_t RESERVED110[3];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BARMSK00L_F0; /*!< (@ 0x000060A0) Base Address Register Mask00 (Lower) (Function
+                                                 #i)                                                        */
+
+            struct
+            {
+                __IOM uint32_t BARM00L : 32;    /*!< [31..0] Base Address Register Mask00 (Lower)                              */
+            } PCI_EP_BARMSK00L_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_BARMSK00L; /*!< (@ 0x000060A0) Base Address Register Mask00 (Lower)                       */
+
+            struct
+            {
+                __IOM uint32_t BARM00L : 32; /*!< [31..0] Base Address Register Mask00 (Lower)                              */
+            } PCI_RC_BARMSK00L_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BARMSK00U_F0; /*!< (@ 0x000060A4) Base Address Register Mask00 (Upper) (Function
+                                                 #i)                                                        */
+
+            struct
+            {
+                __IOM uint32_t BARM00U : 32;    /*!< [31..0] Base Address Register Mask00 (Upper)                              */
+            } PCI_EP_BARMSK00U_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_BARMSK00U; /*!< (@ 0x000060A4) Base Address Register Mask00 (Upper)                       */
+
+            struct
+            {
+                __IOM uint32_t BARM00U : 32; /*!< [31..0] Base Address Register Mask00 (Upper)                              */
+            } PCI_RC_BARMSK00U_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK01L_F0; /*!< (@ 0x000060A8) Base Address Register Mask01 (Lower) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM01L : 32;    /*!< [31..0] Base Address Register Mask01 (Lower)                              */
+        } PCI_EP_BARMSK01L_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK01U_F0; /*!< (@ 0x000060AC) Base Address Register Mask01 (Upper) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM01U : 32;    /*!< [31..0] Base Address Register Mask01 (Upper)                              */
+        } PCI_EP_BARMSK01U_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK02L_F0; /*!< (@ 0x000060B0) Base Address Register Mask02 (Lower) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM02L : 32;    /*!< [31..0] Base Address Register Mask02 (Lower)                              */
+        } PCI_EP_BARMSK02L_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK02U_F0; /*!< (@ 0x000060B4) Base Address Register Mask02 (Upper) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM02U : 32;    /*!< [31..0] Base Address Register Mask02 (Upper)                              */
+        } PCI_EP_BARMSK02U_F0_b;
+    };
+    __IM uint32_t RESERVED111[4];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_BSIZE00_01_F0; /*!< (@ 0x000060C8) Base Size 00/01 (Function #i)                              */
+
+            struct
+            {
+                __IOM uint32_t BS00 : 10;        /*!< [9..0] Base Size 00                                                       */
+                uint32_t            : 6;
+                __IOM uint32_t BS01 : 10;        /*!< [25..16] Base Size 01                                                     */
+                uint32_t            : 6;
+            } PCI_EP_BSIZE00_01_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_BSIZE00_01; /*!< (@ 0x000060C8) Base Size 00/01 Register                                   */
+
+            struct
+            {
+                __IOM uint32_t BS00 : 10;     /*!< [9..0] Base Size 00                                                       */
+                uint32_t            : 22;
+            } PCI_RC_BSIZE00_01_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BSIZE02_03_F0; /*!< (@ 0x000060CC) Base Size 02/03 (Function #i)                              */
+
+        struct
+        {
+            __IOM uint32_t BS02 : 10;        /*!< [9..0] Base Size 02                                                       */
+            uint32_t            : 6;
+            __IOM uint32_t BS03 : 10;        /*!< [25..16] Base Size 03                                                     */
+            uint32_t            : 6;
+        } PCI_EP_BSIZE02_03_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BSIZE04_05_F0; /*!< (@ 0x000060D0) Base Size 04/05 (Function #i)                              */
+
+        struct
+        {
+            __IOM uint32_t BS04 : 10;        /*!< [9..0] Base Size 04                                                       */
+            uint32_t            : 6;
+            __IOM uint32_t BS05 : 10;        /*!< [25..16] Base Size 05                                                     */
+            uint32_t            : 6;
+        } PCI_EP_BSIZE04_05_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BSIZE06_F0; /*!< (@ 0x000060D4) Base Size 06 (Function #i)                                 */
+
+        struct
+        {
+            __IOM uint32_t BS06 : 10;     /*!< [9..0] Base Size 06                                                       */
+            uint32_t            : 22;
+        } PCI_EP_BSIZE06_F0_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_TSUPPORT00_01_02_F0; /*!< (@ 0x000060D8) Type Supported 00/01/02 (Function #i)                      */
+
+            struct
+            {
+                __IOM uint32_t TS00 : 8;               /*!< [7..0] Type Supported 00                                                  */
+                __IOM uint32_t TS01 : 8;               /*!< [15..8] Type Supported 01                                                 */
+                __IOM uint32_t TS02 : 8;               /*!< [23..16] Type Supported 02                                                */
+                uint32_t            : 8;
+            } PCI_EP_TSUPPORT00_01_02_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_TSUPPORT00_01_02; /*!< (@ 0x000060D8) Type Supported 00/01/02 Register                           */
+
+            struct
+            {
+                __IOM uint32_t TS00 : 8;            /*!< [7..0] Type Supported 00                                                  */
+                uint32_t            : 24;
+            } PCI_RC_TSUPPORT00_01_02_b;
+        };
+    };
+    __IM uint32_t RESERVED112;
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSICAP_F0; /*!< (@ 0x000060E0) MSI Capability (Function #i)                               */
+
+        struct
+        {
+            __IM uint32_t  CID  : 8;     /*!< [7..0] Capability ID                                                      */
+            __IM uint32_t  NCP  : 8;     /*!< [15..8] Next Capability Pointer                                           */
+            __IOM uint32_t MSIE : 1;     /*!< [16..16] MSI Enable                                                       */
+            __IM uint32_t  MMC  : 3;     /*!< [19..17] Multiple Message Capable                                         */
+            __IOM uint32_t MME  : 3;     /*!< [22..20] Multiple Message Enable                                          */
+            __IM uint32_t  AC64 : 1;     /*!< [23..23] 64-bit Address Capable                                           */
+            __IM uint32_t  PVMC : 1;     /*!< [24..24] Per-vector masking capable                                       */
+            uint32_t            : 7;
+        } PCI_EP_MSICAP_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSGADR_F0; /*!< (@ 0x000060E4) Message Address (Function #i)                              */
+
+        struct
+        {
+            uint32_t          : 2;
+            __IOM uint32_t MA : 30;    /*!< [31..2] Message Address                                                   */
+        } PCI_EP_MSGADR_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSGUADR_F0; /*!< (@ 0x000060E8) Message Upper Address (Function #i)                        */
+
+        struct
+        {
+            __IOM uint32_t MUA : 32;      /*!< [31..0] Message Upper Address                                             */
+        } PCI_EP_MSGUADR_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSGDAT_F0; /*!< (@ 0x000060EC) Message Data (Function #i)                                 */
+
+        struct
+        {
+            __IOM uint32_t MD : 16;      /*!< [15..0] Message Data                                                      */
+            uint32_t          : 16;
+        } PCI_EP_MSGDAT_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSKBIT_F0; /*!< (@ 0x000060F0) Mask Bits (Function #i)                                    */
+
+        struct
+        {
+            __IOM uint32_t MB : 32;      /*!< [31..0] Mask Bits                                                         */
+        } PCI_EP_MSKBIT_F0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PENDBIT_F0; /*!< (@ 0x000060F4) Pending Bits (Function #i)                                 */
+
+        struct
+        {
+            __IOM uint32_t PB : 32;       /*!< [31..0] Pending Bits                                                      */
+        } PCI_EP_PENDBIT_F0_b;
+    };
+    __IM uint32_t RESERVED113[2];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADVERC_F0;  /*!< (@ 0x00006100) Advanced Error Reporting Capability (Function
+                                               #i)                                                        */
+
+            struct
+            {
+                __IM uint32_t  PCIEECID : 16; /*!< [15..0] PCI Express Extended Capability ID                                */
+                __IOM uint32_t CV       : 4;  /*!< [19..16] Capability Version                                               */
+                __IM uint32_t  NCO      : 12; /*!< [31..20] Next Capability Offset                                           */
+            } PCI_EP_ADVERC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADVERC;     /*!< (@ 0x00006100) Advanced Error Reporting Capability Register               */
+
+            struct
+            {
+                __IM uint32_t  PCIEECID : 16; /*!< [15..0] PCI Express Extended Capability ID                                */
+                __IOM uint32_t CV       : 4;  /*!< [19..16] Capability Version                                               */
+                __IOM uint32_t NCO      : 12; /*!< [31..20] Next Capability Offset                                           */
+            } PCI_RC_ADVERC_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_UNCESTS_F0; /*!< (@ 0x00006104) Uncorrectable Error Status Register (Function
+                                               #i)                                                        */
+
+            struct
+            {
+                uint32_t               : 4;
+                __IOM uint32_t DLPES   : 1; /*!< [4..4] Data Link Protocol Error Status                                    */
+                uint32_t               : 7;
+                __IOM uint32_t PTLPRS  : 1; /*!< [12..12] Poisoned TLP Received Status                                     */
+                uint32_t               : 1;
+                __IOM uint32_t CTS     : 1; /*!< [14..14] Completion Timeout Status                                        */
+                __IOM uint32_t CASO    : 1; /*!< [15..15] Completer Abort Status (Optional)                                */
+                __IOM uint32_t UCS     : 1; /*!< [16..16] Unexpected Completion Status                                     */
+                __IOM uint32_t ROSO    : 1; /*!< [17..17] Receiver Overflow Status (Optional)                              */
+                __IOM uint32_t MTLPS   : 1; /*!< [18..18] Malformed TLP Status                                             */
+                __IOM uint32_t ECRCESO : 1; /*!< [19..19] ECRC Error Status (Optional)                                     */
+                __IOM uint32_t URES    : 1; /*!< [20..20] Unsupported Request Error Status                                 */
+                uint32_t               : 11;
+            } PCI_EP_UNCESTS_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_UNCESTS; /*!< (@ 0x00006104) Uncorrectable Error Status Register                        */
+
+            struct
+            {
+                uint32_t               : 4;
+                __IOM uint32_t DLPES   : 1; /*!< [4..4] Data Link Protocol Error Status                                    */
+                uint32_t               : 7;
+                __IOM uint32_t PTLPRS  : 1; /*!< [12..12] Poisoned TLP Received Status                                     */
+                uint32_t               : 1;
+                __IOM uint32_t CTS     : 1; /*!< [14..14] Completion Timeout Status                                        */
+                __IOM uint32_t CASO    : 1; /*!< [15..15] Completer Abort Status (Optional)                                */
+                __IOM uint32_t UCS     : 1; /*!< [16..16] Unexpected Completion Status                                     */
+                __IOM uint32_t ROSO    : 1; /*!< [17..17] Receiver Overflow Status (Optional)                              */
+                __IOM uint32_t MTLPS   : 1; /*!< [18..18] Malformed TLP Status                                             */
+                __IOM uint32_t ECRCESO : 1; /*!< [19..19] ECRC Error Status (Optional)                                     */
+                __IOM uint32_t URES    : 1; /*!< [20..20] Unsupported Request Error Status                                 */
+                uint32_t               : 11;
+            } PCI_RC_UNCESTS_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_UNCEMASK_F0; /*!< (@ 0x00006108) Uncorrectable Error Mask Register (Function #i)            */
+
+            struct
+            {
+                uint32_t               : 4;
+                __IOM uint32_t DLPEM   : 1; /*!< [4..4] Data Link Protocol Error Mask                                      */
+                uint32_t               : 7;
+                __IOM uint32_t PTLPRM  : 1; /*!< [12..12] Poisoned TLP Received Mask                                       */
+                uint32_t               : 1;
+                __IOM uint32_t CTM     : 1; /*!< [14..14] Completion Timeout Mask                                          */
+                __IOM uint32_t CAMO    : 1; /*!< [15..15] Completer Abort Mask (Optional)                                  */
+                __IOM uint32_t UCM     : 1; /*!< [16..16] Unexpected Completion Mask                                       */
+                __IOM uint32_t ROMO    : 1; /*!< [17..17] Receiver Overflow Mask (Optional)                                */
+                __IOM uint32_t MTLPM   : 1; /*!< [18..18] Malformed TLP Mask                                               */
+                __IOM uint32_t ECRCEMO : 1; /*!< [19..19] ECRC Error Mask (Optional)                                       */
+                __IOM uint32_t UREM    : 1; /*!< [20..20] Unsupported Request Error Mask                                   */
+                uint32_t               : 11;
+            } PCI_EP_UNCEMASK_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_UNCEMASK; /*!< (@ 0x00006108) Uncorrectable Error Mask Register                          */
+
+            struct
+            {
+                uint32_t               : 4;
+                __IOM uint32_t DLPEM   : 1; /*!< [4..4] Data Link Protocol Error Mask                                      */
+                uint32_t               : 7;
+                __IOM uint32_t PTLPRM  : 1; /*!< [12..12] Poisoned TLP Received Mask                                       */
+                uint32_t               : 1;
+                __IOM uint32_t CTM     : 1; /*!< [14..14] Completion Timeout Mask                                          */
+                __IOM uint32_t CAMO    : 1; /*!< [15..15] Completer Abort Mask (Optional)                                  */
+                __IOM uint32_t UCM     : 1; /*!< [16..16] Unexpected Completion Mask                                       */
+                __IOM uint32_t ROMO    : 1; /*!< [17..17] Receiver Overflow Mask (Optional)                                */
+                __IOM uint32_t MTLPM   : 1; /*!< [18..18] Malformed TLP Mask                                               */
+                __IOM uint32_t ECRCEMO : 1; /*!< [19..19] ECRC Error Mask (Optional)                                       */
+                __IOM uint32_t UREM    : 1; /*!< [20..20] Unsupported Request Error Mask                                   */
+                uint32_t               : 11;
+            } PCI_RC_UNCEMASK_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_UNCESVY_F0; /*!< (@ 0x0000610C) Uncorrectable Error Severity Register (Function
+                                               #i)                                                        */
+
+            struct
+            {
+                uint32_t               : 4;
+                __IOM uint32_t DLPES   : 1; /*!< [4..4] Data Link Protocol Error Severity                                  */
+                uint32_t               : 7;
+                __IOM uint32_t PTLPRS  : 1; /*!< [12..12] Poisoned TLP Received Severity                                   */
+                uint32_t               : 1;
+                __IOM uint32_t CTS     : 1; /*!< [14..14] Completion Timeout Severity                                      */
+                __IOM uint32_t CASO    : 1; /*!< [15..15] Completer Abort Severity (Optional)                              */
+                __IOM uint32_t UCS     : 1; /*!< [16..16] Unexpected Completion Severity                                   */
+                __IOM uint32_t ROSO    : 1; /*!< [17..17] Receiver Overflow Severity (Optional)                            */
+                __IOM uint32_t MTLPS   : 1; /*!< [18..18] Malformed TLP Severity                                           */
+                __IOM uint32_t ECRCESO : 1; /*!< [19..19] ECRC Error Severity (Optional)                                   */
+                __IOM uint32_t URES    : 1; /*!< [20..20] Unsupported Request Error Severity                               */
+                uint32_t               : 11;
+            } PCI_EP_UNCESVY_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_UNCESVY; /*!< (@ 0x0000610C) Uncorrectable Error Severity Register                      */
+
+            struct
+            {
+                uint32_t               : 4;
+                __IOM uint32_t DLPES   : 1; /*!< [4..4] Data Link Protocol Error Severity                                  */
+                uint32_t               : 7;
+                __IOM uint32_t PTLPRS  : 1; /*!< [12..12] Poisoned TLP Received Severity                                   */
+                uint32_t               : 1;
+                __IOM uint32_t CTS     : 1; /*!< [14..14] Completion Timeout Severity                                      */
+                __IOM uint32_t CASO    : 1; /*!< [15..15] Completer Abort Severity (Optional)                              */
+                __IOM uint32_t UCS     : 1; /*!< [16..16] Unexpected Completion Severity                                   */
+                __IOM uint32_t ROSO    : 1; /*!< [17..17] Receiver Overflow Severity (Optional)                            */
+                __IOM uint32_t MTLPS   : 1; /*!< [18..18] Malformed TLP Severity                                           */
+                __IOM uint32_t ECRCESO : 1; /*!< [19..19] ECRC Error Severity (Optional)                                   */
+                __IOM uint32_t URES    : 1; /*!< [20..20] Unsupported Request Error Severity                               */
+                uint32_t               : 11;
+            } PCI_RC_UNCESVY_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_CESTS_F0;     /*!< (@ 0x00006110) Correctable Error Status Register (Function #i)            */
+
+            struct
+            {
+                __IM uint32_t RES         : 1; /*!< [0..0] Receiver Error Status (optional)                                   */
+                uint32_t                  : 5;
+                __IM uint32_t BTLPS       : 1; /*!< [6..6] Bad TLP Status                                                     */
+                __IM uint32_t BDLLPS      : 1; /*!< [7..7] Bad DLLP Status                                                    */
+                __IM uint32_t REPLAYNUMRS : 1; /*!< [8..8] REPLAY_NUM Rollover Status                                         */
+                uint32_t                  : 3;
+                __IM uint32_t RTTS        : 1; /*!< [12..12] Replay Timer Timeout Status                                      */
+                __IM uint32_t ANFES       : 1; /*!< [13..13] Advisory Non-Fatal Error Status                                  */
+                uint32_t                  : 18;
+            } PCI_EP_CESTS_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_CESTS;        /*!< (@ 0x00006110) Correctable Error Status Register                          */
+
+            struct
+            {
+                __IOM uint32_t RES         : 1; /*!< [0..0] Receiver Error Status (optional)                                   */
+                uint32_t                   : 5;
+                __IOM uint32_t BTLPS       : 1; /*!< [6..6] Bad TLP Status                                                     */
+                __IOM uint32_t BDLLPS      : 1; /*!< [7..7] Bad DLLP Status                                                    */
+                __IOM uint32_t REPLAYNUMRS : 1; /*!< [8..8] REPLAY_NUM Rollover Status                                         */
+                uint32_t                   : 3;
+                __IOM uint32_t RTTS        : 1; /*!< [12..12] Replay Timer Timeout Status                                      */
+                __IOM uint32_t ANFES       : 1; /*!< [13..13] Advisory Non-Fatal Error Status                                  */
+                uint32_t                   : 18;
+            } PCI_RC_CESTS_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_CEMASK_F0;    /*!< (@ 0x00006114) Correctable Error Mask Register (Function #i)              */
+
+            struct
+            {
+                __IOM uint32_t REM         : 1; /*!< [0..0] Receiver Error Mask (optional)                                     */
+                uint32_t                   : 5;
+                __IOM uint32_t BTLPM       : 1; /*!< [6..6] Bad TLP Mask                                                       */
+                __IOM uint32_t BDLLPM      : 1; /*!< [7..7] Bad DLLP Mask                                                      */
+                __IOM uint32_t REPLAYNUMRM : 1; /*!< [8..8] REPLAY_NUM Rollover Mask                                           */
+                uint32_t                   : 3;
+                __IOM uint32_t RTTM        : 1; /*!< [12..12] Replay Timer Timeout Mask                                        */
+                __IOM uint32_t ANFEM       : 1; /*!< [13..13] Advisory Non-Fatal Error Mask                                    */
+                uint32_t                   : 18;
+            } PCI_EP_CEMASK_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_CEMASK;       /*!< (@ 0x00006114) Correctable Error Mask Register                            */
+
+            struct
+            {
+                __IOM uint32_t REM         : 1; /*!< [0..0] Receiver Error Mask (optional)                                     */
+                uint32_t                   : 5;
+                __IOM uint32_t BTLPM       : 1; /*!< [6..6] Bad TLP Mask                                                       */
+                __IOM uint32_t BDLLPM      : 1; /*!< [7..7] Bad DLLP Mask                                                      */
+                __IOM uint32_t REPLAYNUMRM : 1; /*!< [8..8] REPLAY_NUM Rollover Mask                                           */
+                uint32_t                   : 3;
+                __IOM uint32_t RTTM        : 1; /*!< [12..12] Replay Timer Timeout Mask                                        */
+                __IOM uint32_t ANFEM       : 1; /*!< [13..13] Advisory Non-Fatal Error Mask                                    */
+                uint32_t                   : 18;
+            } PCI_RC_CEMASK_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_ADVECC_F0; /*!< (@ 0x00006118) Advanced Error Capabilities and Control Register
+                                              *                  (Function #i)                                              */
+
+            struct
+            {
+                __IM uint32_t  FEP    : 5;   /*!< [4..0] First Error Pointer                                                */
+                __IM uint32_t  ECRCGC : 1;   /*!< [5..5] ECRC Generation Capable                                            */
+                __IOM uint32_t ECRCGE : 1;   /*!< [6..6] ECRC Generation Enable                                             */
+                __IM uint32_t  ECRCCC : 1;   /*!< [7..7] ECRC Check Capable                                                 */
+                __IOM uint32_t ECRCCE : 1;   /*!< [8..8] ECRC Check Enable                                                  */
+                uint32_t              : 23;
+            } PCI_EP_ADVECC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_ADVECC;  /*!< (@ 0x00006118) Advanced Error Capabilities and Control Register           */
+
+            struct
+            {
+                __IM uint32_t  FEP    : 5; /*!< [4..0] First Error Pointer                                                */
+                __IM uint32_t  ECRCGC : 1; /*!< [5..5] ECRC Generation Capable                                            */
+                __IOM uint32_t ECRCGE : 1; /*!< [6..6] ECRC Generation Enable                                             */
+                __IM uint32_t  ECRCCC : 1; /*!< [7..7] ECRC Check Capable                                                 */
+                __IOM uint32_t ECRCCE : 1; /*!< [8..8] ECRC Check Enable                                                  */
+                uint32_t              : 23;
+            } PCI_RC_ADVECC_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_HLOG0_F0; /*!< (@ 0x0000611C) Header Log Register 0 (Function #i)                        */
+
+            struct
+            {
+                __IM uint32_t HTLPE0 : 32; /*!< [31..0] Header of TLP associated with error 0                             */
+            } PCI_EP_HLOG0_F0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_HLOG0;    /*!< (@ 0x0000611C) Header Log Register 0                                      */
+
+            struct
+            {
+                __IM uint32_t HTLPE0 : 32; /*!< [31..0] Header of TLP associated with error 0                             */
+            } PCI_RC_HLOG0_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_HLOG1_Fi; /*!< (@ 0x00006120) Header Log Register 1 (Function #i)                        */
+
+            struct
+            {
+                __IM uint32_t HTLPE1 : 32; /*!< [31..0] Header of TLP associated with error 1                             */
+            } PCI_EP_HLOG1_Fi_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_HLOG1;    /*!< (@ 0x00006120) Header Log Register 1                                      */
+
+            struct
+            {
+                __IM uint32_t HTLPE1 : 32; /*!< [31..0] Header of TLP associated with error 1                             */
+            } PCI_RC_HLOG1_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_HLOG2_F0; /*!< (@ 0x00006124) Header Log Register 2 (Function #i)                        */
+
+            struct
+            {
+                __IM uint32_t HTLPE2 : 32; /*!< [31..0] Header of TLP associated with error 2                             */
+            } PCI_EP_HLOG2_F0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_HLOG2;    /*!< (@ 0x00006124) Header Log Register 2                                      */
+
+            struct
+            {
+                __IM uint32_t HTLPE2 : 32; /*!< [31..0] Header of TLP associated with error 2                             */
+            } PCI_RC_HLOG2_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_HLOG3_F0; /*!< (@ 0x00006128) Header Log Register 3 (Function #i)                        */
+
+            struct
+            {
+                __IM uint32_t HTLPE3 : 32; /*!< [31..0] Header of TLP associated with error 3                             */
+            } PCI_EP_HLOG3_F0_b;
+        };
+
+        union
+        {
+            __IM uint32_t PCI_RC_HLOG3;    /*!< (@ 0x00006128) Header Log Register 3                                      */
+
+            struct
+            {
+                __IM uint32_t HTLPE3 : 32; /*!< [31..0] Header of TLP associated with error 3                             */
+            } PCI_RC_HLOG3_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_ROOTEC;  /*!< (@ 0x0000612C) Root Error Command                                         */
+
+        struct
+        {
+            __IOM uint32_t CERE  : 1;  /*!< [0..0] Correctable Error Reporting Enable                                 */
+            __IOM uint32_t NFERE : 1;  /*!< [1..1] Non-Fatal Error Reporting Enable                                   */
+            __IOM uint32_t FERE  : 1;  /*!< [2..2] Fatal Error Reporting Enable                                       */
+            uint32_t             : 29;
+        } PCI_RC_ROOTEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_RC_ROOTES;              /*!< (@ 0x00006130) Root Error Status                                          */
+
+        struct
+        {
+            __IOM uint32_t ERRCORR            : 1; /*!< [0..0] ERR_COR Received                                                   */
+            __IOM uint32_t MERRCORR           : 1; /*!< [1..1] Multiple ERR_COR Received                                          */
+            __IOM uint32_t ERRFATALNONFATALR  : 1; /*!< [2..2] ERR_FATALNONFATAL Received                                         */
+            __IOM uint32_t MERRFATALNONFATALR : 1; /*!< [3..3] Multiple ERR_FATALNONFATAL Received                                */
+            __IOM uint32_t FUF                : 1; /*!< [4..4] First Uncorrectable Fatal                                          */
+            __IOM uint32_t NFEMR              : 1; /*!< [5..5] Non-Fatal Error Message Received                                   */
+            __IOM uint32_t FEMR               : 1; /*!< [6..6] Fatal Error Message Received                                       */
+            uint32_t                          : 25;
+        } PCI_RC_ROOTES_b;
+    };
+
+    union
+    {
+        __IM uint32_t PCI_RC_ERRSI;                /*!< (@ 0x00006134) Error Source Identification Register                       */
+
+        struct
+        {
+            __IM uint32_t ERRCORSI           : 16; /*!< [15..0] ERR_COR Source Identification                                     */
+            __IM uint32_t ERRFATALNONFATALSI : 16; /*!< [31..16] ERR_FATALNONFATAL Source Identification                          */
+        } PCI_RC_ERRSI_b;
+    };
+    __IM uint32_t RESERVED114[6];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_DEVSNEXTC_F0; /*!< (@ 0x00006150) Device Serial Number Extended Capability Register
+                                                 *                  (Function #i)                                              */
+
+            struct
+            {
+                __IM uint32_t  PCIEECID : 16;   /*!< [15..0] PCI Express Extended Capability ID                                */
+                __IOM uint32_t CV       : 4;    /*!< [19..16] Capability Version                                               */
+                __IM uint32_t  NCO      : 12;   /*!< [31..20] Next Capability Offset                                           */
+            } PCI_EP_DEVSNEXTC_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_DEVSNEXTC;  /*!< (@ 0x00006150) Device Serial Number Extended Capability Register          */
+
+            struct
+            {
+                __IM uint32_t  PCIEECID : 16; /*!< [15..0] PCI Express Extended Capability ID                                */
+                __IOM uint32_t CV       : 4;  /*!< [19..16] Capability Version                                               */
+                __IM uint32_t  NCO      : 12; /*!< [31..20] Next Capability Offset                                           */
+            } PCI_RC_DEVSNEXTC_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_SNL_F0;        /*!< (@ 0x00006154) Serial Number Register (Lower DW) (Function #i)            */
+
+            struct
+            {
+                __IOM uint32_t PCIEDSN_LDW : 32; /*!< [31..0] PCI Express Device Serial Number (Lower DW)                       */
+            } PCI_EP_SNL_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_SNL;           /*!< (@ 0x00006154) Serial Number Register (Lower DW)                          */
+
+            struct
+            {
+                __IOM uint32_t PCIEDSN_LDW : 32; /*!< [31..0] PCI Express Device Serial Number (Lower DW)                       */
+            } PCI_RC_SNL_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_SNU_F0;        /*!< (@ 0x00006158) Serial Number Register (Upper DW) (Function #i)            */
+
+            struct
+            {
+                __IOM uint32_t PCIEDSN_UDW : 32; /*!< [31..0] PCI Express Device Serial Number (Upper DW)                       */
+            } PCI_EP_SNU_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_SNU;           /*!< (@ 0x00006158) Serial Number Register (Upper DW)                          */
+
+            struct
+            {
+                __IOM uint32_t PCIEDSN_UDW : 32; /*!< [31..0] PCI Express Device Serial Number (Upper DW)                       */
+            } PCI_RC_SNU_b;
+        };
+    };
+    __IM uint32_t RESERVED115[21];
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_SPEECH_F0;  /*!< (@ 0x000061B0) Secondary PCI Express Extended Capability Header
+                                               *                  (Function #0)                                              */
+
+            struct
+            {
+                __IM uint32_t  PCIEECID : 16; /*!< [15..0] PCI Express Extended Capability ID                                */
+                __IOM uint32_t CV       : 4;  /*!< [19..16] Capability Version                                               */
+                __IM uint32_t  NCO      : 12; /*!< [31..20] Next Capability Offset                                           */
+            } PCI_EP_SPEECH_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_SPEECH;     /*!< (@ 0x000061B0) Secondary PCI Express Extended Capability Header           */
+
+            struct
+            {
+                __IM uint32_t  PCIEECID : 16; /*!< [15..0] PCI Express Extended Capability ID                                */
+                __IOM uint32_t CV       : 4;  /*!< [19..16] Capability Version                                               */
+                __IM uint32_t  NCO      : 12; /*!< [31..20] Next Capability Offset                                           */
+            } PCI_RC_SPEECH_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_LINC3_F0; /*!< (@ 0x000061B4) Link Control 3 Register (Function #0)                      */
+
+            struct
+            {
+                uint32_t                 : 9;
+                __IOM uint32_t ELSKPOSGV : 7; /*!< [15..9] Enable Lower SKP OS Generation Vector                             */
+                uint32_t                 : 16;
+            } PCI_EP_LINC3_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_LINC3;      /*!< (@ 0x000061B4) Link Control 3 Register                                    */
+
+            struct
+            {
+                __IOM uint32_t PE        : 1; /*!< [0..0] Perform Equalization                                               */
+                __IOM uint32_t LERIE     : 1; /*!< [1..1] Link Equalization Request Interrupt Enable                         */
+                uint32_t                 : 7;
+                __IOM uint32_t ELSKPOSGV : 7; /*!< [15..9] Enable Lower SKP OS Generation Vector                             */
+                uint32_t                 : 16;
+            } PCI_RC_LINC3_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCI_EP_LESTA_F0; /*!< (@ 0x000061B8) Lane Error Status Register (Function #0)                   */
+
+            struct
+            {
+                __IOM uint32_t LESB : 2;    /*!< [1..0] Lane Error Status Bits                                             */
+                uint32_t            : 30;
+            } PCI_EP_LESTA_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_LESTA; /*!< (@ 0x000061B8) Lane Error Status Register                                 */
+
+            struct
+            {
+                __IOM uint32_t LESB : 4; /*!< [3..0] Lane Error Status Bits                                             */
+                uint32_t            : 28;
+            } PCI_RC_LESTA_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCI_EP_LEQCTL_F0; /*!< (@ 0x000061BC) Lane Equalization Control Register (Function
+                                             #0)                                                        */
+
+            struct
+            {
+                __IM uint32_t DPTP0  : 4;   /*!< [3..0] Downstream Port 8.0 GTs Transmitter Preset Lane0                   */
+                __IM uint32_t DPRPH0 : 3;   /*!< [6..4] Downstream Port 8.0 GTs Receiver Preset Hint Lane0                 */
+                uint32_t             : 1;
+                __IM uint32_t UPTP0  : 4;   /*!< [11..8] Upstream Port 8.0 GTs Transmitter Preset Lane0                    */
+                __IM uint32_t UPRPH0 : 3;   /*!< [14..12] Upstream Port 8.0 GTs Receiver Preset Hint Lane0                 */
+                uint32_t             : 1;
+                __IM uint32_t DPTP1  : 4;   /*!< [19..16] Downstream Port 8.0 GTs Transmitter Preset Lane1                 */
+                __IM uint32_t DPRPH1 : 3;   /*!< [22..20] Downstream Port 8.0 GTs Receiver Preset Hint Lane1               */
+                uint32_t             : 1;
+                __IM uint32_t UPTP1  : 4;   /*!< [27..24] Upstream Port 8.0 GTs Transmitter Preset Lane1                   */
+                __IM uint32_t UPRPH1 : 3;   /*!< [30..28] Upstream Port 8.0 GTs Receiver Preset Hint Lane1                 */
+                uint32_t             : 1;
+            } PCI_EP_LEQCTL_F0_b;
+        };
+
+        union
+        {
+            __IOM uint32_t PCI_RC_LEQCTL;  /*!< (@ 0x000061BC) Lane Equalization Control Register                         */
+
+            struct
+            {
+                __IOM uint32_t DPTP0  : 4; /*!< [3..0] Downstream Port 8.0 GTs Transmitter Preset Lane0                   */
+                __IOM uint32_t DPRPH0 : 3; /*!< [6..4] Downstream Port 8.0 GTs Receiver Preset Hint Lane0                 */
+                uint32_t              : 1;
+                __IOM uint32_t UPTP0  : 4; /*!< [11..8] Upstream Port 8.0 GTs Transmitter Preset Lane0                    */
+                __IOM uint32_t UPRPH0 : 3; /*!< [14..12] Upstream Port 8.0 GTs Receiver Preset Hint Lane0                 */
+                uint32_t              : 1;
+                __IOM uint32_t DPTP1  : 4; /*!< [19..16] Downstream Port 8.0 GTs Transmitter Preset Lane1                 */
+                __IOM uint32_t DPRPH1 : 3; /*!< [22..20] Downstream Port 8.0 GTs Receiver Preset Hint Lane1               */
+                uint32_t              : 1;
+                __IOM uint32_t UPTP1  : 4; /*!< [27..24] Upstream Port 8.0 GTs Transmitter Preset Lane1                   */
+                __IOM uint32_t UPRPH1 : 3; /*!< [30..28] Upstream Port 8.0 GTs Receiver Preset Hint Lane1                 */
+                uint32_t              : 1;
+            } PCI_RC_LEQCTL_b;
+        };
+    };
+    __IM uint32_t RESERVED116[912];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_VID_F1;  /*!< (@ 0x00007000) Vendor and Device ID (Function #i)                         */
+
+        struct
+        {
+            __IOM uint32_t VID : 16;   /*!< [15..0] Vendor ID                                                         */
+            __IOM uint32_t DID : 16;   /*!< [31..16] Device ID                                                        */
+        } PCI_EP_VID_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_COM_STA_F1; /*!< (@ 0x00007004) Command and Status (Function #i)                           */
+
+        struct
+        {
+            __IM uint32_t  IOSE  : 1;     /*!< [0..0] IO Space Enable                                                    */
+            __IOM uint32_t MSE   : 1;     /*!< [1..1] Memory Space Enable                                                */
+            __IOM uint32_t BME   : 1;     /*!< [2..2] Bus Master Enable                                                  */
+            uint32_t             : 3;
+            __IOM uint32_t PER   : 1;     /*!< [6..6] Parity Error Response                                              */
+            uint32_t             : 1;
+            __IOM uint32_t SERRE : 1;     /*!< [8..8] SERR# Enable                                                       */
+            uint32_t             : 1;
+            __IOM uint32_t ID    : 1;     /*!< [10..10] Interrupt Disable                                                */
+            uint32_t             : 5;
+            __IM uint32_t IR     : 1;     /*!< [16..16] Fixed 0                                                          */
+            uint32_t             : 2;
+            __IM uint32_t IS     : 1;     /*!< [19..19] Interrupt Status                                                 */
+            __IM uint32_t CL     : 1;     /*!< [20..20] Capabilities List                                                */
+            uint32_t             : 3;
+            __IOM uint32_t MDPE  : 1;     /*!< [24..24] Master Data Parity Error                                         */
+            uint32_t             : 2;
+            __IOM uint32_t STA   : 1;     /*!< [27..27] Signaled Target Abort                                            */
+            __IOM uint32_t RTA   : 1;     /*!< [28..28] Received Target Abort                                            */
+            __IOM uint32_t RMA   : 1;     /*!< [29..29] Received Master Abort                                            */
+            __IOM uint32_t SSE   : 1;     /*!< [30..30] Signaled System Error                                            */
+            __IOM uint32_t DPE   : 1;     /*!< [31..31] Detected Parity Error                                            */
+        } PCI_EP_COM_STA_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_RID_CC_F1; /*!< (@ 0x00007008) Revision ID and Class Code (Function #i)                   */
+
+        struct
+        {
+            __IOM uint32_t RID : 8;      /*!< [7..0] Revision ID                                                        */
+            __IOM uint32_t CC  : 24;     /*!< [31..8] Class Code                                                        */
+        } PCI_EP_RID_CC_F1_b;
+    };
+
+    union
+    {
+        __IM uint32_t PCI_EP_CL_HT_F1; /*!< (@ 0x0000700C) Cache Line and Header Type (Function #i)                   */
+
+        struct
+        {
+            __IM uint32_t CLS : 8;     /*!< [7..0] Cache Line Size                                                    */
+            uint32_t          : 8;
+            __IM uint32_t HT  : 8;     /*!< [23..16] Header Type                                                      */
+            uint32_t          : 8;
+        } PCI_EP_CL_HT_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BAR0_F1; /*!< (@ 0x00007010) Base Address Register 0 (Function #i)                      */
+
+        struct
+        {
+            __IOM uint32_t MSI  : 1;   /*!< [0..0] Memory Space Indicator                                             */
+            uint32_t            : 1;
+            __IOM uint32_t TYPE : 1;   /*!< [2..2] Type                                                               */
+            __IOM uint32_t PF   : 1;   /*!< [3..3] Prefetch                                                           */
+            __IOM uint32_t BAR0 : 28;  /*!< [31..4] Base Address Register 0                                           */
+        } PCI_EP_BAR0_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BAR1_F1; /*!< (@ 0x00007014) Base Address Register 1 (Function #i)                      */
+
+        struct
+        {
+            __IOM uint32_t BAR1 : 32;  /*!< [31..0] Base Address Register 1 (64-bit Upper Address)                    */
+        } PCI_EP_BAR1_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BAR2_F1; /*!< (@ 0x00007018) Base Address Register 2 (Function #i)                      */
+
+        struct
+        {
+            __IM uint32_t MSI   : 1;   /*!< [0..0] Memory Space Indicator                                             */
+            uint32_t            : 1;
+            __IOM uint32_t TYPE : 1;   /*!< [2..2] Type                                                               */
+            __IOM uint32_t PF   : 1;   /*!< [3..3] Prefetch                                                           */
+            __IOM uint32_t BAR2 : 28;  /*!< [31..4] Base Address Register 2                                           */
+        } PCI_EP_BAR2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BAR3_F1; /*!< (@ 0x0000701C) Base Address Register 3 (Function #i)                      */
+
+        struct
+        {
+            __IOM uint32_t BAR3 : 32;  /*!< [31..0] Base Address Register 3 (64-bit Upper Address)                    */
+        } PCI_EP_BAR3_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BAR4_F1; /*!< (@ 0x00007020) Base Address Register 4 (Function #i)                      */
+
+        struct
+        {
+            __IM uint32_t MSI   : 1;   /*!< [0..0] Memory Space Indicator                                             */
+            uint32_t            : 1;
+            __IOM uint32_t TYPE : 1;   /*!< [2..2] Type                                                               */
+            __IOM uint32_t PF   : 1;   /*!< [3..3] Prefetch                                                           */
+            __IOM uint32_t BAR4 : 28;  /*!< [31..4] Base Address Register 4                                           */
+        } PCI_EP_BAR4_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BAR5_F1; /*!< (@ 0x00007024) Base Address Register 5 (Function #i)                      */
+
+        struct
+        {
+            __IOM uint32_t BAR5 : 32;  /*!< [31..0] Base Address Register 5 (64-bit Upper Address)                    */
+        } PCI_EP_BAR5_F1_b;
+    };
+    __IM uint32_t RESERVED117;
+
+    union
+    {
+        __IOM uint32_t PCI_EP_SUBSID_F1; /*!< (@ 0x0000702C) Subsystem ID (Function #i)                                 */
+
+        struct
+        {
+            __IOM uint32_t SVID : 16;    /*!< [15..0] Subsystem Vendor ID                                               */
+            __IOM uint32_t SID  : 16;    /*!< [31..16] Subsystem ID                                                     */
+        } PCI_EP_SUBSID_F1_b;
+    };
+    __IM uint32_t RESERVED118;
+
+    union
+    {
+        __IM uint32_t PCI_EP_CP_F1;    /*!< (@ 0x00007034) Capabilities Pointer (Function #i)                         */
+
+        struct
+        {
+            __IM uint32_t CP : 8;      /*!< [7..0] Capabilities Pointer                                               */
+            uint32_t         : 24;
+        } PCI_EP_CP_F1_b;
+    };
+    __IM uint32_t RESERVED119;
+
+    union
+    {
+        __IOM uint32_t PCI_EP_INT_F1;  /*!< (@ 0x0000703C) Interrupt Register (Function #i)                           */
+
+        struct
+        {
+            __IOM uint32_t IL : 8;     /*!< [7..0] Interrupt Line                                                     */
+            __IOM uint32_t IP : 8;     /*!< [15..8] Interrupt Pin                                                     */
+            uint32_t          : 16;
+        } PCI_EP_INT_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PMC_F1;   /*!< (@ 0x00007040) PM Capabilities (Function #i)                              */
+
+        struct
+        {
+            __IM uint32_t  CID     : 8; /*!< [7..0] Capability ID                                                      */
+            __IM uint32_t  NCP     : 8; /*!< [15..8] Next Capability Pointer                                           */
+            __IOM uint32_t V       : 3; /*!< [18..16] Version                                                          */
+            uint32_t               : 1;
+            __IM uint32_t  IRORTD0 : 1; /*!< [20..20] Immediate_Readiness_on_Return_to_D0                              */
+            __IOM uint32_t DSI     : 1; /*!< [21..21] Device Specific Initialization                                   */
+            __IOM uint32_t AUXC    : 3; /*!< [24..22] AUX_Current                                                      */
+            __IOM uint32_t D1S     : 1; /*!< [25..25] D1 Support                                                       */
+            __IOM uint32_t D2S     : 1; /*!< [26..26] D2 Support                                                       */
+            __IOM uint32_t PMES    : 5; /*!< [31..27] PME Support                                                      */
+        } PCI_EP_PMC_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PMSC_F1; /*!< (@ 0x00007044) PM Status/Control (Function #i)                            */
+
+        struct
+        {
+            __IOM uint32_t PS   : 2;   /*!< [1..0] PowerState                                                         */
+            uint32_t            : 1;
+            __IM uint32_t NSR   : 1;   /*!< [3..3] No_Soft_Reset                                                      */
+            uint32_t            : 4;
+            __IOM uint32_t PMEE : 1;   /*!< [8..8] PME Enable                                                         */
+            uint32_t            : 6;
+            __IOM uint32_t PMES : 1;   /*!< [15..15] PME Status                                                       */
+            uint32_t            : 16;
+        } PCI_EP_PMSC_F1_b;
+    };
+    __IM uint32_t RESERVED120[6];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PCIEC_F1; /*!< (@ 0x00007060) PCI Express Capability (Function #i)                       */
+
+        struct
+        {
+            __IM uint32_t  CID : 8;     /*!< [7..0] Capability ID                                                      */
+            __IM uint32_t  NCP : 8;     /*!< [15..8] Next Capability Pointer                                           */
+            __IOM uint32_t CV  : 4;     /*!< [19..16] Capability Version                                               */
+            __IOM uint32_t DPT : 4;     /*!< [23..20] DevicePort Type                                                  */
+            uint32_t           : 1;
+            __IOM uint32_t IMN : 5;     /*!< [29..25] Interrupt Message Number                                         */
+            uint32_t           : 2;
+        } PCI_EP_PCIEC_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_DEVC_F1; /*!< (@ 0x00007064) Device Capabilities (Function #i)                          */
+
+        struct
+        {
+            __IOM uint32_t MPSS  : 3;  /*!< [2..0] Max_Payload_Size Supported                                         */
+            uint32_t             : 2;
+            __IOM uint32_t ETFS  : 1;  /*!< [5..5] Extended Tag Field Supported                                       */
+            __IOM uint32_t EL0AL : 3;  /*!< [8..6] Endpoint L0 Acceptable Latency                                     */
+            __IOM uint32_t EL1AL : 3;  /*!< [11..9] Endpoint L1 Acceptable Latency                                    */
+            uint32_t             : 3;
+            __IM uint32_t RBER   : 1;  /*!< [15..15] Role-Based Error Reporting                                       */
+            uint32_t             : 2;
+            __IOM uint32_t CSPLV : 8;  /*!< [25..18] Captured Slot Power Limit Value                                  */
+            __IOM uint32_t CSPLS : 2;  /*!< [27..26] Captured Slot Power Limit Scale                                  */
+            __IOM uint32_t FLRC  : 1;  /*!< [28..28] Function Level Reset Capability                                  */
+            uint32_t             : 3;
+        } PCI_EP_DEVC_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_DEVCS_F1; /*!< (@ 0x00007068) Device Control/Status (Function #i)                        */
+
+        struct
+        {
+            __IOM uint32_t CERE  : 1;   /*!< [0..0] Correctable Error Reporting Enable                                 */
+            __IOM uint32_t NFERE : 1;   /*!< [1..1] Non-Fatal Error Reporting Enable                                   */
+            __IOM uint32_t FERE  : 1;   /*!< [2..2] Fatal Error Reporting Enable                                       */
+            __IOM uint32_t URRE  : 1;   /*!< [3..3] Unsupported Request Reporting Enable                               */
+            __IOM uint32_t ERO   : 1;   /*!< [4..4] Enable Relaxed Ordering                                            */
+            __IOM uint32_t MPS   : 3;   /*!< [7..5] Max_Payload_Size                                                   */
+            uint32_t             : 4;
+            __IOM uint32_t MRRS  : 3;   /*!< [14..12] Max_Read_Request_Size                                            */
+            __IOM uint32_t IFLR  : 1;   /*!< [15..15] Initiate Function Level Reset                                    */
+            __IOM uint32_t CED   : 1;   /*!< [16..16] Correctable Error Detected                                       */
+            __IOM uint32_t NFED  : 1;   /*!< [17..17] Non-Fatal Error Detected                                         */
+            __IOM uint32_t FED   : 1;   /*!< [18..18] Fatal Error Detected                                             */
+            __IOM uint32_t URD   : 1;   /*!< [19..19] Unsupported Request Detected                                     */
+            uint32_t             : 1;
+            __IM uint32_t TP     : 1;   /*!< [21..21] Transaction Pending                                              */
+            uint32_t             : 10;
+        } PCI_EP_DEVCS_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_LINKC_F1; /*!< (@ 0x0000706C) Link Capabilities (Function #i)                            */
+
+        struct
+        {
+            __IOM uint32_t MLS    : 4;  /*!< [3..0] Max Link Speed                                                     */
+            __IOM uint32_t MLW    : 6;  /*!< [9..4] Maximum Link Width                                                 */
+            __IOM uint32_t ASPMS  : 2;  /*!< [11..10] Active State Power Management (ASPM) Support                     */
+            __IOM uint32_t L0EL   : 3;  /*!< [14..12] L0s Exit Latency                                                 */
+            __IOM uint32_t L1EL   : 3;  /*!< [17..15] L1 Exit Latency                                                  */
+            __IOM uint32_t CPM    : 1;  /*!< [18..18] Clock Power Management                                           */
+            uint32_t              : 3;
+            __IOM uint32_t ASPMOC : 1;  /*!< [22..22] ASPM Optionality Compliance                                      */
+            uint32_t              : 1;
+            __IOM uint32_t PN     : 8;  /*!< [31..24] Port Number                                                      */
+        } PCI_EP_LINKC_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_LINKCS_F1; /*!< (@ 0x00007070) Link Control/Status (Function #i)                          */
+
+        struct
+        {
+            __IOM uint32_t ASPMC : 2;    /*!< [1..0] Active State Power Management (ASPM) Control                       */
+            uint32_t             : 1;
+            __IOM uint32_t RCB   : 1;    /*!< [3..3] Read Completion Boundary (RCB)                                     */
+            uint32_t             : 2;
+            __IOM uint32_t CCC   : 1;    /*!< [6..6] Common Clock Configuration                                         */
+            __IOM uint32_t ES    : 1;    /*!< [7..7] Extended Synch                                                     */
+            __IOM uint32_t ECPM  : 1;    /*!< [8..8] Enable Clock Power Management                                      */
+            __IOM uint32_t HAWD  : 1;    /*!< [9..9] Hardware Autonomous Width Disable                                  */
+            uint32_t             : 6;
+            __IM uint32_t CLS    : 4;    /*!< [19..16] Current Link Speed                                               */
+            __IM uint32_t NLW    : 6;    /*!< [25..20] Negotiated Link Width                                            */
+            uint32_t             : 2;
+            __IOM uint32_t SCC   : 1;    /*!< [28..28] Slot Clock Configuration                                         */
+            __IM uint32_t  DLLLA : 1;    /*!< [29..29] Data Link Layer Link Active                                      */
+            uint32_t             : 2;
+        } PCI_EP_LINKCS_F1_b;
+    };
+    __IM uint32_t RESERVED121[4];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_DEVC2_F1; /*!< (@ 0x00007084) Device Capabilities 2 (Function #i)                        */
+
+        struct
+        {
+            __IOM uint32_t CTRS : 4;    /*!< [3..0] Completion Timeout Ranges Supported                                */
+            __IOM uint32_t CTDS : 1;    /*!< [4..4] Completion Timeout Disable Supported                               */
+            uint32_t            : 27;
+        } PCI_EP_DEVC2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_DEVCS2_F1; /*!< (@ 0x00007088) Device Control 2/Status 2 (Function #i)                    */
+
+        struct
+        {
+            __IOM uint32_t CTV : 4;      /*!< [3..0] Completion Timeout Value                                           */
+            __IOM uint32_t CTD : 1;      /*!< [4..4] Completion Timeout Disable                                         */
+            uint32_t           : 27;
+        } PCI_EP_DEVCS2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_LINKC2_F1; /*!< (@ 0x0000708C) Link Capabilities 2 (Function #i)                          */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IOM uint32_t SLSV : 7;   /*!< [7..1] Supported Link Speeds Vector                                       */
+            uint32_t            : 24;
+        } PCI_EP_LINKC2_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_LINKCS2_F1; /*!< (@ 0x00007090) Link Control 2/Status 2 (Function #n)                      */
+
+        struct
+        {
+            __IOM uint32_t TLS  : 4;      /*!< [3..0] Target Link Speed                                                  */
+            __IOM uint32_t ETC  : 1;      /*!< [4..4] Enter Compliance                                                   */
+            __IOM uint32_t HASD : 1;      /*!< [5..5] Hardware Autonomous Speed Disable                                  */
+            uint32_t            : 1;
+            __IOM uint32_t TM   : 3;      /*!< [9..7] Transmit Margin                                                    */
+            __IOM uint32_t EMC  : 1;      /*!< [10..10] Enter Modified Compliance                                        */
+            __IOM uint32_t CSOS : 1;      /*!< [11..11] Compliance SOS                                                   */
+            __IOM uint32_t CPD  : 4;      /*!< [15..12] Compliance Preset De-emphasis                                    */
+            __IM uint32_t  CDL  : 1;      /*!< [16..16] Current De-emphasis Level                                        */
+            __IM uint32_t  EQC  : 1;      /*!< [17..17] Equalization Complete                                            */
+            __IM uint32_t  EP1S : 1;      /*!< [18..18] Equalization Phase 1 Successful                                  */
+            __IM uint32_t  EP2S : 1;      /*!< [19..19] Equalization Phase 2 Successful                                  */
+            __IM uint32_t  EP3S : 1;      /*!< [20..20] Equalization Phase 3 Successful                                  */
+            __IOM uint32_t LER  : 1;      /*!< [21..21] Link Equalization Request                                        */
+            uint32_t            : 10;
+        } PCI_EP_LINKCS2_F1_b;
+    };
+    __IM uint32_t RESERVED122[3];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK00L_F1; /*!< (@ 0x000070A0) Base Address Register Mask00 (Lower) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM00L : 32;    /*!< [31..0] Base Address Register Mask00 (Lower)                              */
+        } PCI_EP_BARMSK00L_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK00U_F1; /*!< (@ 0x000070A4) Base Address Register Mask00 (Upper) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM00U : 32;    /*!< [31..0] Base Address Register Mask00 (Upper)                              */
+        } PCI_EP_BARMSK00U_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK01L_F1; /*!< (@ 0x000070A8) Base Address Register Mask01 (Lower) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM01L : 32;    /*!< [31..0] Base Address Register Mask01 (Lower)                              */
+        } PCI_EP_BARMSK01L_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK01U_F1; /*!< (@ 0x000070AC) Base Address Register Mask01 (Upper) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM01U : 32;    /*!< [31..0] Base Address Register Mask01 (Upper)                              */
+        } PCI_EP_BARMSK01U_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK02L_F1; /*!< (@ 0x000070B0) Base Address Register Mask02 (Lower) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM02L : 32;    /*!< [31..0] Base Address Register Mask02 (Lower)                              */
+        } PCI_EP_BARMSK02L_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BARMSK02U_F1; /*!< (@ 0x000070B4) Base Address Register Mask02 (Upper) (Function
+                                             #i)                                                        */
+
+        struct
+        {
+            __IOM uint32_t BARM02U : 32;    /*!< [31..0] Base Address Register Mask02 (Upper)                              */
+        } PCI_EP_BARMSK02U_F1_b;
+    };
+    __IM uint32_t RESERVED123[4];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BSIZE00_01_F1; /*!< (@ 0x000070C8) Base Size 00/01 (Function #i)                              */
+
+        struct
+        {
+            __IOM uint32_t BS00 : 10;        /*!< [9..0] Base Size 00                                                       */
+            uint32_t            : 6;
+            __IOM uint32_t BS01 : 10;        /*!< [25..16] Base Size 01                                                     */
+            uint32_t            : 6;
+        } PCI_EP_BSIZE00_01_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BSIZE02_03_F1; /*!< (@ 0x000070CC) Base Size 02/03 (Function #i)                              */
+
+        struct
+        {
+            __IOM uint32_t BS02 : 10;        /*!< [9..0] Base Size 02                                                       */
+            uint32_t            : 6;
+            __IOM uint32_t BS03 : 10;        /*!< [25..16] Base Size 03                                                     */
+            uint32_t            : 6;
+        } PCI_EP_BSIZE02_03_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BSIZE04_05_F1; /*!< (@ 0x000070D0) Base Size 04/05 (Function #i)                              */
+
+        struct
+        {
+            __IOM uint32_t BS04 : 10;        /*!< [9..0] Base Size 04                                                       */
+            uint32_t            : 6;
+            __IOM uint32_t BS05 : 10;        /*!< [25..16] Base Size 05                                                     */
+            uint32_t            : 6;
+        } PCI_EP_BSIZE04_05_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_BSIZE06_F1; /*!< (@ 0x000070D4) Base Size 06 (Function #i)                                 */
+
+        struct
+        {
+            __IOM uint32_t BS06 : 10;     /*!< [9..0] Base Size 06                                                       */
+            uint32_t            : 22;
+        } PCI_EP_BSIZE06_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_TSUPPORT00_01_02_F1; /*!< (@ 0x000070D8) Type Supported 00/01/02 (Function #i)                      */
+
+        struct
+        {
+            __IOM uint32_t TS00 : 8;               /*!< [7..0] Type Supported 00                                                  */
+            __IOM uint32_t TS01 : 8;               /*!< [15..8] Type Supported 01                                                 */
+            __IOM uint32_t TS02 : 8;               /*!< [23..16] Type Supported 02                                                */
+            uint32_t            : 8;
+        } PCI_EP_TSUPPORT00_01_02_F1_b;
+    };
+    __IM uint32_t RESERVED124;
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSICAP_F1; /*!< (@ 0x000070E0) MSI Capability (Function #i)                               */
+
+        struct
+        {
+            __IM uint32_t  CID  : 8;     /*!< [7..0] Capability ID                                                      */
+            __IM uint32_t  NCP  : 8;     /*!< [15..8] Next Capability Pointer                                           */
+            __IOM uint32_t MSIE : 1;     /*!< [16..16] MSI Enable                                                       */
+            __IM uint32_t  MMC  : 3;     /*!< [19..17] Multiple Message Capable                                         */
+            __IOM uint32_t MME  : 3;     /*!< [22..20] Multiple Message Enable                                          */
+            __IM uint32_t  AC64 : 1;     /*!< [23..23] 64-bit Address Capable                                           */
+            __IM uint32_t  PVMC : 1;     /*!< [24..24] Per-vector masking capable                                       */
+            uint32_t            : 7;
+        } PCI_EP_MSICAP_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSGADR_F1; /*!< (@ 0x000070E4) Message Address (Function #i)                              */
+
+        struct
+        {
+            uint32_t          : 2;
+            __IOM uint32_t MA : 30;    /*!< [31..2] Message Address                                                   */
+        } PCI_EP_MSGADR_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSGUADR_F1; /*!< (@ 0x000070E8) Message Upper Address (Function #i)                        */
+
+        struct
+        {
+            __IOM uint32_t MUA : 32;      /*!< [31..0] Message Upper Address                                             */
+        } PCI_EP_MSGUADR_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSGDAT_F1; /*!< (@ 0x000070EC) Message Data (Function #i)                                 */
+
+        struct
+        {
+            __IOM uint32_t MD : 16;      /*!< [15..0] Message Data                                                      */
+            uint32_t          : 16;
+        } PCI_EP_MSGDAT_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_MSKBIT_F1; /*!< (@ 0x000070F0) Mask Bits (Function #i)                                    */
+
+        struct
+        {
+            __IOM uint32_t MB : 32;      /*!< [31..0] Mask Bits                                                         */
+        } PCI_EP_MSKBIT_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_PENDBIT_F1; /*!< (@ 0x000070F4) Pending Bits (Function #i)                                 */
+
+        struct
+        {
+            __IOM uint32_t PB : 32;       /*!< [31..0] Pending Bits                                                      */
+        } PCI_EP_PENDBIT_F1_b;
+    };
+    __IM uint32_t RESERVED125[2];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADVERC_F1;  /*!< (@ 0x00007100) Advanced Error Reporting Capability (Function
+                                           #i)                                                        */
+
+        struct
+        {
+            __IM uint32_t  PCIEECID : 16; /*!< [15..0] PCI Express Extended Capability ID                                */
+            __IOM uint32_t CV       : 4;  /*!< [19..16] Capability Version                                               */
+            __IM uint32_t  NCO      : 12; /*!< [31..20] Next Capability Offset                                           */
+        } PCI_EP_ADVERC_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_UNCESTS_F1; /*!< (@ 0x00007104) Uncorrectable Error Status Register (Function
+                                           #i)                                                        */
+
+        struct
+        {
+            uint32_t               : 4;
+            __IOM uint32_t DLPES   : 1; /*!< [4..4] Data Link Protocol Error Status                                    */
+            uint32_t               : 7;
+            __IOM uint32_t PTLPRS  : 1; /*!< [12..12] Poisoned TLP Received Status                                     */
+            uint32_t               : 1;
+            __IOM uint32_t CTS     : 1; /*!< [14..14] Completion Timeout Status                                        */
+            __IOM uint32_t CASO    : 1; /*!< [15..15] Completer Abort Status (Optional)                                */
+            __IOM uint32_t UCS     : 1; /*!< [16..16] Unexpected Completion Status                                     */
+            __IOM uint32_t ROSO    : 1; /*!< [17..17] Receiver Overflow Status (Optional)                              */
+            __IOM uint32_t MTLPS   : 1; /*!< [18..18] Malformed TLP Status                                             */
+            __IOM uint32_t ECRCESO : 1; /*!< [19..19] ECRC Error Status (Optional)                                     */
+            __IOM uint32_t URES    : 1; /*!< [20..20] Unsupported Request Error Status                                 */
+            uint32_t               : 11;
+        } PCI_EP_UNCESTS_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_UNCEMASK_F1; /*!< (@ 0x00007108) Uncorrectable Error Mask Register (Function #i)            */
+
+        struct
+        {
+            uint32_t               : 4;
+            __IOM uint32_t DLPEM   : 1; /*!< [4..4] Data Link Protocol Error Mask                                      */
+            uint32_t               : 7;
+            __IOM uint32_t PTLPRM  : 1; /*!< [12..12] Poisoned TLP Received Mask                                       */
+            uint32_t               : 1;
+            __IOM uint32_t CTM     : 1; /*!< [14..14] Completion Timeout Mask                                          */
+            __IOM uint32_t CAMO    : 1; /*!< [15..15] Completer Abort Mask (Optional)                                  */
+            __IOM uint32_t UCM     : 1; /*!< [16..16] Unexpected Completion Mask                                       */
+            __IOM uint32_t ROMO    : 1; /*!< [17..17] Receiver Overflow Mask (Optional)                                */
+            __IOM uint32_t MTLPM   : 1; /*!< [18..18] Malformed TLP Mask                                               */
+            __IOM uint32_t ECRCEMO : 1; /*!< [19..19] ECRC Error Mask (Optional)                                       */
+            __IOM uint32_t UREM    : 1; /*!< [20..20] Unsupported Request Error Mask                                   */
+            uint32_t               : 11;
+        } PCI_EP_UNCEMASK_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_UNCESVY_F1; /*!< (@ 0x0000710C) Uncorrectable Error Severity Register (Function
+                                           #i)                                                        */
+
+        struct
+        {
+            uint32_t               : 4;
+            __IOM uint32_t DLPES   : 1; /*!< [4..4] Data Link Protocol Error Severity                                  */
+            uint32_t               : 7;
+            __IOM uint32_t PTLPRS  : 1; /*!< [12..12] Poisoned TLP Received Severity                                   */
+            uint32_t               : 1;
+            __IOM uint32_t CTS     : 1; /*!< [14..14] Completion Timeout Severity                                      */
+            __IOM uint32_t CASO    : 1; /*!< [15..15] Completer Abort Severity (Optional)                              */
+            __IOM uint32_t UCS     : 1; /*!< [16..16] Unexpected Completion Severity                                   */
+            __IOM uint32_t ROSO    : 1; /*!< [17..17] Receiver Overflow Severity (Optional)                            */
+            __IOM uint32_t MTLPS   : 1; /*!< [18..18] Malformed TLP Severity                                           */
+            __IOM uint32_t ECRCESO : 1; /*!< [19..19] ECRC Error Severity (Optional)                                   */
+            __IOM uint32_t URES    : 1; /*!< [20..20] Unsupported Request Error Severity                               */
+            uint32_t               : 11;
+        } PCI_EP_UNCESVY_F1_b;
+    };
+
+    union
+    {
+        __IM uint32_t PCI_EP_CESTS_F1;     /*!< (@ 0x00007110) Correctable Error Status Register (Function #i)            */
+
+        struct
+        {
+            __IM uint32_t RES         : 1; /*!< [0..0] Receiver Error Status (optional)                                   */
+            uint32_t                  : 5;
+            __IM uint32_t BTLPS       : 1; /*!< [6..6] Bad TLP Status                                                     */
+            __IM uint32_t BDLLPS      : 1; /*!< [7..7] Bad DLLP Status                                                    */
+            __IM uint32_t REPLAYNUMRS : 1; /*!< [8..8] REPLAY_NUM Rollover Status                                         */
+            uint32_t                  : 3;
+            __IM uint32_t RTTS        : 1; /*!< [12..12] Replay Timer Timeout Status                                      */
+            __IM uint32_t ANFES       : 1; /*!< [13..13] Advisory Non-Fatal Error Status                                  */
+            uint32_t                  : 18;
+        } PCI_EP_CESTS_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_CEMASK_F1;    /*!< (@ 0x00007114) Correctable Error Mask Register (Function #i)              */
+
+        struct
+        {
+            __IOM uint32_t REM         : 1; /*!< [0..0] Receiver Error Mask (optional)                                     */
+            uint32_t                   : 5;
+            __IOM uint32_t BTLPM       : 1; /*!< [6..6] Bad TLP Mask                                                       */
+            __IOM uint32_t BDLLPM      : 1; /*!< [7..7] Bad DLLP Mask                                                      */
+            __IOM uint32_t REPLAYNUMRM : 1; /*!< [8..8] REPLAY_NUM Rollover Mask                                           */
+            uint32_t                   : 3;
+            __IOM uint32_t RTTM        : 1; /*!< [12..12] Replay Timer Timeout Mask                                        */
+            __IOM uint32_t ANFEM       : 1; /*!< [13..13] Advisory Non-Fatal Error Mask                                    */
+            uint32_t                   : 18;
+        } PCI_EP_CEMASK_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_ADVECC_F1; /*!< (@ 0x00007118) Advanced Error Capabilities and Control Register
+                                          *                  (Function #i)                                              */
+
+        struct
+        {
+            __IM uint32_t  FEP    : 5;   /*!< [4..0] First Error Pointer                                                */
+            __IM uint32_t  ECRCGC : 1;   /*!< [5..5] ECRC Generation Capable                                            */
+            __IOM uint32_t ECRCGE : 1;   /*!< [6..6] ECRC Generation Enable                                             */
+            __IM uint32_t  ECRCCC : 1;   /*!< [7..7] ECRC Check Capable                                                 */
+            __IOM uint32_t ECRCCE : 1;   /*!< [8..8] ECRC Check Enable                                                  */
+            uint32_t              : 23;
+        } PCI_EP_ADVECC_F1_b;
+    };
+
+    union
+    {
+        __IM uint32_t PCI_EP_HLOG0_F1; /*!< (@ 0x0000711C) Header Log Register 0 (Function #i)                        */
+
+        struct
+        {
+            __IM uint32_t HTLPE0 : 32; /*!< [31..0] Header of TLP associated with error 0                             */
+        } PCI_EP_HLOG0_F1_b;
+    };
+    __IM uint32_t RESERVED126;
+
+    union
+    {
+        __IM uint32_t PCI_EP_HLOG2_F1; /*!< (@ 0x00007124) Header Log Register 2 (Function #i)                        */
+
+        struct
+        {
+            __IM uint32_t HTLPE2 : 32; /*!< [31..0] Header of TLP associated with error 2                             */
+        } PCI_EP_HLOG2_F1_b;
+    };
+
+    union
+    {
+        __IM uint32_t PCI_EP_HLOG3_F1; /*!< (@ 0x00007128) Header Log Register 3 (Function #i)                        */
+
+        struct
+        {
+            __IM uint32_t HTLPE3 : 32; /*!< [31..0] Header of TLP associated with error 3                             */
+        } PCI_EP_HLOG3_F1_b;
+    };
+    __IM uint32_t RESERVED127[9];
+
+    union
+    {
+        __IOM uint32_t PCI_EP_DEVSNEXTC_F1; /*!< (@ 0x00007150) Device Serial Number Extended Capability Register
+                                             *                  (Function #i)                                              */
+
+        struct
+        {
+            __IM uint32_t  PCIEECID : 16;   /*!< [15..0] PCI Express Extended Capability ID                                */
+            __IOM uint32_t CV       : 4;    /*!< [19..16] Capability Version                                               */
+            __IM uint32_t  NCO      : 12;   /*!< [31..20] Next Capability Offset                                           */
+        } PCI_EP_DEVSNEXTC_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_SNL_F1;        /*!< (@ 0x00007154) Serial Number Register (Lower DW) (Function #i)            */
+
+        struct
+        {
+            __IOM uint32_t PCIEDSN_LDW : 32; /*!< [31..0] PCI Express Device Serial Number (Lower DW)                       */
+        } PCI_EP_SNL_F1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCI_EP_SNU_F1;        /*!< (@ 0x00007158) Serial Number Register (Upper DW) (Function #i)            */
+
+        struct
+        {
+            __IOM uint32_t PCIEDSN_UDW : 32; /*!< [31..0] PCI Express Device Serial Number (Upper DW)                       */
+        } PCI_EP_SNU_F1_b;
+    };
+} R_PCIE0_Type;                              /*!< Size = 29020 (0x715c)                                                     */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PCIE_PHY                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief PCIe PHY (R_PCIE_PHY)
+ */
+
+typedef struct                                                     /*!< (@ 0x92102000) R_PCIE_PHY Structure                                       */
+{
+    __IOM R_PCIE_PHY_PCI_PHY_XCFGD_Type PCI_PHY_XCFGD[27];         /*!< (@ 0x00000000) XCFGD Setting Register n (n = 0 to 26)             */
+    __IM uint32_t RESERVED[148];
+    __IOM R_PCIE_PHY_PCI_PHY_XCFGA_CMN_Type PCI_PHY_XCFGA_CMN[16]; /*!< (@ 0x00000400) XCFGA_CMN Setting Register n (n = 0 to 15) */
+    __IOM R_PCIE_PHY_PCI_PHY_XCFGA_L0_Type  PCI_PHY_XCFGA_L0[6];   /*!< (@ 0x00000500) XCFGA_LN0 Setting Register n (n = 0 to 5)     */
+    __IOM R_PCIE_PHY_PCI_PHY_XCFGA_L1_Type  PCI_PHY_XCFGA_L1[6];   /*!< (@ 0x00000560) XCFGA_LN1 Setting Register n (n = 0 to 5)     */
+} R_PCIE_PHY_Type;                                                 /*!< Size = 1472 (0x5c0)                                                       */
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+ #define R_GPT09_0_BASE        0x80000000UL
+ #define R_GPT09_1_BASE        0x80000100UL
+ #define R_GPT09_2_BASE        0x80000200UL
+ #define R_GPT09_3_BASE        0x80000300UL
+ #define R_GPT09_4_BASE        0x80000400UL
+ #define R_GPT09_5_BASE        0x80000500UL
+ #define R_GPT09_6_BASE        0x80000600UL
+ #define R_CRC0_BASE           0x80004000UL
+ #define R_SCI0_BASE           0x80005000UL
+ #define R_SCI1_BASE           0x80005400UL
+ #define R_SCI2_BASE           0x80005800UL
+ #define R_SCI3_BASE           0x80005C00UL
+ #define R_SCI4_BASE           0x80006000UL
+ #define R_SPI0_BASE           0x80007000UL
+ #define R_SPI1_BASE           0x80007400UL
+ #define R_SPI2_BASE           0x80007800UL
+ #define R_ADC122_BASE         0x80008000UL
+ #define R_CANFD_BASE          0x80040000UL
+ #define R_CMT_BASE            0x80080000UL
+ #define R_CMTW0_BASE          0x80081000UL
+ #define R_CMTW1_BASE          0x80081400UL
+ #define R_WDT0_BASE           0x80082000UL
+ #define R_WDT1_BASE           0x80082400UL
+ #define R_WDT2_BASE           0x80082800UL
+ #define R_WDT3_BASE           0x80082C00UL
+ #define R_WDT4_BASE           0x80083000UL
+ #define R_WDT5_BASE           0x80083400UL
+ #define R_DOC_BASE            0x80084000UL
+ #define R_TSU_B0_BASE         0x80086000UL
+ #define R_POEG1_BASE          0x80087000UL
+ #define R_IIC0_BASE           0x80088000UL
+ #define R_IIC1_BASE           0x80088400UL
+ #define R_DMAC0_BASE          0x800C0000UL
+ #define R_DMAC1_BASE          0x800C1000UL
+ #define R_DMAC2_BASE          0x800C2000UL
+ #define R_GMAC0_BASE          0x80100000UL
+ #define R_ETHSS_BASE          0x80110000UL
+ #define R_ESC_INI_BASE        0x80110200UL
+ #define R_ETHSW_PTP_BASE      0x80110400UL
+ #define R_GMACC_BASE          0x80110400UL
+ #define R_ETHSW_BASE          0x80120000UL
+ #define R_ESC_BASE            0x80130000UL
+ #define R_XSPI0_BASE          0x801C0000UL
+ #define R_XSPI1_BASE          0x801C1000UL
+ #define R_BSC_BASE            0x80210000UL
+ #define R_MBXSEM_BASE         0x80240000UL
+ #define R_SHOSTIF_BASE        0x80241000UL
+ #define R_SYSC_NS_BASE        0x80280000UL
+ #define R_ELO_BASE            0x80290000UL
+ #define R_GPT_IC_BASE         0x80290008UL
+ #define R_ENCSS_BASE          0x80291000UL
+ #define R_PCIE_SPL0_BASE      0x80292000UL
+ #define R_PCIE_SPL1_BASE      0x80292030UL
+ #define R_PCIE_LNK_BASE       0x80292060UL
+ #define R_XSPI0_MISC_BASE     0x80293000UL
+ #define R_XSPI1_MISC_BASE     0x80293100UL
+ #define R_MD_NS_BASE          0x80294100UL
+ #define R_RWP_NS_BASE         0x80294200UL
+ #define R_ICU_NS_BASE         0x802A0000UL
+ #define R_ELC_BASE            0x802A0698UL
+ #define R_DMA_BASE            0x802A07D0UL
+ #define R_PORT_SRN_BASE       0x802B0000UL
+ #define R_PORT_NSR_BASE       0x802C0000UL
+ #define R_DDRSS_BASE          0x80300000UL
+ #define R_GPT10_0_BASE        0x81000000UL
+ #define R_GPT10_1_BASE        0x81000100UL
+ #define R_GPT10_2_BASE        0x81000200UL
+ #define R_GPT10_3_BASE        0x81000300UL
+ #define R_CRC1_BASE           0x81004000UL
+ #define R_SCI5_BASE           0x81005000UL
+ #define R_SPI3_BASE           0x81007000UL
+ #define R_IIC2_BASE           0x81008000UL
+ #define R_RTC_BASE            0x81009000UL
+ #define R_POEG2_BASE          0x8100A000UL
+ #define R_SYSRAM0_BASE        0x81040000UL
+ #define R_SYSRAM1_BASE        0x81041000UL
+ #define R_SYSRAM2_BASE        0x81042000UL
+ #define R_SYSRAM3_BASE        0x81043000UL
+ #define R_OTP_BASE            0x810C0000UL
+ #define R_MPU_AC_BASE         0x81240000UL
+ #define R_SYSC_S_BASE         0x81280000UL
+ #define R_CLMA0_BASE          0x81288000UL
+ #define R_CLMA1_BASE          0x81288020UL
+ #define R_CLMA2_BASE          0x81288040UL
+ #define R_CLMA3_BASE          0x81288060UL
+ #define R_CLMA4_BASE          0x81288080UL
+ #define R_CLMA5_BASE          0x812880A0UL
+ #define R_CLMA6_BASE          0x812880C0UL
+ #define R_ADXC0_BASE          0x81290100UL
+ #define R_SSC_BASE            0x81290200UL
+ #define R_MSAC_BASE           0x81290300UL
+ #define R_MPU10_BASE          0x81290400UL
+ #define R_MPU11_BASE          0x81290500UL
+ #define R_MPU12_BASE          0x81290600UL
+ #define R_MPU13_BASE          0x81290700UL
+ #define R_MPU14_BASE          0x81290800UL
+ #define R_MPU15_BASE          0x81290900UL
+ #define R_ADXC1_BASE          0x81291100UL
+ #define R_MPU0_BASE           0x81291400UL
+ #define R_MPU1_BASE           0x81291500UL
+ #define R_MPU2_BASE           0x81291600UL
+ #define R_MPU3_BASE           0x81291700UL
+ #define R_MPU4_BASE           0x81291800UL
+ #define R_MPU5_BASE           0x81291900UL
+ #define R_MPU6_BASE           0x81291A00UL
+ #define R_MPU7_BASE           0x81291B00UL
+ #define R_MPU8_BASE           0x81291C00UL
+ #define R_MPU9_BASE           0x81291D00UL
+ #define R_SYSRAM_CTL_BASE     0x81293000UL
+ #define R_SHOSTIF_CFG_BASE    0x81294000UL
+ #define R_TCMAW_BASE          0x81295000UL
+ #define R_CA55_BASE           0x81295020UL
+ #define R_WDT_DBG_BASE        0x81295100UL
+ #define R_RWP_S_BASE          0x81296000UL
+ #define R_ICU_S_BASE          0x812A0000UL
+ #define R_PORT_SRS_BASE       0x812C0000UL
+ #define R_GSC_BASE            0x8C200000UL
+ #define R_MTU_BASE            0x90001000UL
+ #define R_MTU3_BASE           0x90001100UL
+ #define R_MTU4_BASE           0x90001200UL
+ #define R_MTU_NF_BASE         0x90001290UL
+ #define R_MTU0_BASE           0x90001300UL
+ #define R_MTU1_BASE           0x90001380UL
+ #define R_MTU2_BASE           0x90001400UL
+ #define R_MTU8_BASE           0x90001600UL
+ #define R_MTU6_BASE           0x90001900UL
+ #define R_MTU7_BASE           0x90001A00UL
+ #define R_MTU5_BASE           0x90001C00UL
+ #define R_GPT00_0_BASE        0x90002000UL
+ #define R_GPT00_1_BASE        0x90002100UL
+ #define R_GPT00_2_BASE        0x90002200UL
+ #define R_GPT00_3_BASE        0x90002300UL
+ #define R_GPT00_4_BASE        0x90002400UL
+ #define R_GPT01_0_BASE        0x90003000UL
+ #define R_GPT01_1_BASE        0x90003100UL
+ #define R_GPT01_2_BASE        0x90003200UL
+ #define R_GPT01_3_BASE        0x90003300UL
+ #define R_GPT01_4_BASE        0x90003400UL
+ #define R_GPT02_0_BASE        0x90004000UL
+ #define R_GPT02_1_BASE        0x90004100UL
+ #define R_GPT02_2_BASE        0x90004200UL
+ #define R_GPT02_3_BASE        0x90004300UL
+ #define R_GPT02_4_BASE        0x90004400UL
+ #define R_GPT03_0_BASE        0x90005000UL
+ #define R_GPT03_1_BASE        0x90005100UL
+ #define R_GPT03_2_BASE        0x90005200UL
+ #define R_GPT03_3_BASE        0x90005300UL
+ #define R_GPT03_4_BASE        0x90005400UL
+ #define R_GPT04_0_BASE        0x90006000UL
+ #define R_GPT04_1_BASE        0x90006100UL
+ #define R_GPT04_2_BASE        0x90006200UL
+ #define R_GPT04_3_BASE        0x90006300UL
+ #define R_GPT04_4_BASE        0x90006400UL
+ #define R_GPT05_0_BASE        0x90007000UL
+ #define R_GPT05_1_BASE        0x90007100UL
+ #define R_GPT05_2_BASE        0x90007200UL
+ #define R_GPT05_3_BASE        0x90007300UL
+ #define R_GPT05_4_BASE        0x90007400UL
+ #define R_TFU0_BASE           0x90010000UL
+ #define R_ADC120_BASE         0x90014000UL
+ #define R_ADC121_BASE         0x90014400UL
+ #define R_POE3_BASE           0x90018000UL
+ #define R_POEG0_BASE          0x90019000UL
+ #define R_DSMIF0_BASE         0x90020000UL
+ #define R_DSMIF1_BASE         0x90021000UL
+ #define R_DSMIF2_BASE         0x90022000UL
+ #define R_DSMIF3_BASE         0x90023000UL
+ #define R_DSMIF4_BASE         0x90024000UL
+ #define R_DSMIF5_BASE         0x90025000UL
+ #define R_SCIE0_BASE          0x90030000UL
+ #define R_SCIE1_BASE          0x90030400UL
+ #define R_SCIE2_BASE          0x90030800UL
+ #define R_SCIE3_BASE          0x90030C00UL
+ #define R_SCIE4_BASE          0x90031000UL
+ #define R_SCIE5_BASE          0x90031400UL
+ #define R_SCIE6_BASE          0x90031800UL
+ #define R_SCIE7_BASE          0x90031C00UL
+ #define R_GPT06_0_BASE        0x90100000UL
+ #define R_GPT06_1_BASE        0x90100100UL
+ #define R_GPT06_2_BASE        0x90100200UL
+ #define R_GPT06_3_BASE        0x90100300UL
+ #define R_GPT06_4_BASE        0x90100400UL
+ #define R_GPT07_0_BASE        0x90101000UL
+ #define R_GPT07_1_BASE        0x90101100UL
+ #define R_GPT07_2_BASE        0x90101200UL
+ #define R_GPT07_3_BASE        0x90101300UL
+ #define R_GPT07_4_BASE        0x90101400UL
+ #define R_GPT08_0_BASE        0x90102000UL
+ #define R_GPT08_1_BASE        0x90102100UL
+ #define R_GPT08_2_BASE        0x90102200UL
+ #define R_GPT08_3_BASE        0x90102300UL
+ #define R_GPT08_4_BASE        0x90102400UL
+ #define R_TFU1_BASE           0x90110000UL
+ #define R_DSMIF6_BASE         0x90120000UL
+ #define R_DSMIF7_BASE         0x90121000UL
+ #define R_DSMIF8_BASE         0x90122000UL
+ #define R_DSMIF9_BASE         0x90123000UL
+ #define R_SCIE8_BASE          0x90130000UL
+ #define R_SCIE9_BASE          0x90130400UL
+ #define R_SCIE10_BASE         0x90130800UL
+ #define R_SCIE11_BASE         0x90130C00UL
+ #define R_HDSLD0_BASE         0x90200000UL
+ #define R_HDSLS10_BASE        0x90201000UL
+ #define R_HDSLS20_BASE        0x90202000UL
+ #define R_BISS0_BASE          0x90203000UL
+ #define R_ENDAT0_BASE         0x90204000UL
+ #define R_AFMT0_BASE          0x90206000UL
+ #define R_HDSLD1_BASE         0x90210000UL
+ #define R_HDSLS11_BASE        0x90211000UL
+ #define R_HDSLS21_BASE        0x90212000UL
+ #define R_BISS1_BASE          0x90213000UL
+ #define R_ENDAT1_BASE         0x90214000UL
+ #define R_AFMT1_BASE          0x90216000UL
+ #define R_HDSLD2_BASE         0x90220000UL
+ #define R_HDSLS12_BASE        0x90221000UL
+ #define R_HDSLS22_BASE        0x90222000UL
+ #define R_BISS2_BASE          0x90223000UL
+ #define R_ENDAT2_BASE         0x90224000UL
+ #define R_AFMT2_BASE          0x90226000UL
+ #define R_HDSLD3_BASE         0x90230000UL
+ #define R_HDSLS13_BASE        0x90231000UL
+ #define R_HDSLS23_BASE        0x90232000UL
+ #define R_BISS3_BASE          0x90233000UL
+ #define R_ENDAT3_BASE         0x90234000UL
+ #define R_AFMT3_BASE          0x90236000UL
+ #define R_HDSLD4_BASE         0x90240000UL
+ #define R_HDSLS14_BASE        0x90241000UL
+ #define R_HDSLS24_BASE        0x90242000UL
+ #define R_BISS4_BASE          0x90243000UL
+ #define R_ENDAT4_BASE         0x90244000UL
+ #define R_AFMT4_BASE          0x90246000UL
+ #define R_HDSLD5_BASE         0x90250000UL
+ #define R_HDSLS15_BASE        0x90251000UL
+ #define R_HDSLS25_BASE        0x90252000UL
+ #define R_BISS5_BASE          0x90253000UL
+ #define R_ENDAT5_BASE         0x90254000UL
+ #define R_AFMT5_BASE          0x90256000UL
+ #define R_HDSLD6_BASE         0x90260000UL
+ #define R_HDSLS16_BASE        0x90261000UL
+ #define R_HDSLS26_BASE        0x90262000UL
+ #define R_BISS6_BASE          0x90263000UL
+ #define R_ENDAT6_BASE         0x90264000UL
+ #define R_AFMT6_BASE          0x90266000UL
+ #define R_HDSLD7_BASE         0x90270000UL
+ #define R_HDSLS17_BASE        0x90271000UL
+ #define R_HDSLS27_BASE        0x90272000UL
+ #define R_BISS7_BASE          0x90273000UL
+ #define R_ENDAT7_BASE         0x90274000UL
+ #define R_AFMT7_BASE          0x90276000UL
+ #define R_HDSLD8_BASE         0x90280000UL
+ #define R_HDSLS18_BASE        0x90281000UL
+ #define R_HDSLS28_BASE        0x90282000UL
+ #define R_BISS8_BASE          0x90283000UL
+ #define R_ENDAT8_BASE         0x90284000UL
+ #define R_AFMT8_BASE          0x90286000UL
+ #define R_HDSLD9_BASE         0x90290000UL
+ #define R_HDSLS19_BASE        0x90291000UL
+ #define R_HDSLS29_BASE        0x90292000UL
+ #define R_BISS9_BASE          0x90293000UL
+ #define R_ENDAT9_BASE         0x90294000UL
+ #define R_AFMT9_BASE          0x90296000UL
+ #define R_HDSLD10_BASE        0x902A0000UL
+ #define R_HDSLS110_BASE       0x902A1000UL
+ #define R_HDSLS210_BASE       0x902A2000UL
+ #define R_BISS10_BASE         0x902A3000UL
+ #define R_ENDAT10_BASE        0x902A4000UL
+ #define R_AFMT10_BASE         0x902A6000UL
+ #define R_HDSLD11_BASE        0x902B0000UL
+ #define R_HDSLS111_BASE       0x902B1000UL
+ #define R_HDSLS211_BASE       0x902B2000UL
+ #define R_BISS11_BASE         0x902B3000UL
+ #define R_ENDAT11_BASE        0x902B4000UL
+ #define R_AFMT11_BASE         0x902B6000UL
+ #define R_ENCOUT_BASE         0x902C0000UL
+ #define R_HDSLD12_BASE        0x90300000UL
+ #define R_HDSLS112_BASE       0x90301000UL
+ #define R_HDSLS212_BASE       0x90302000UL
+ #define R_BISS12_BASE         0x90303000UL
+ #define R_ENDAT12_BASE        0x90304000UL
+ #define R_AFMT12_BASE         0x90306000UL
+ #define R_HDSLD13_BASE        0x90310000UL
+ #define R_HDSLS113_BASE       0x90311000UL
+ #define R_HDSLS213_BASE       0x90312000UL
+ #define R_BISS13_BASE         0x90313000UL
+ #define R_ENDAT13_BASE        0x90314000UL
+ #define R_AFMT13_BASE         0x90316000UL
+ #define R_HDSLD14_BASE        0x90320000UL
+ #define R_HDSLS114_BASE       0x90321000UL
+ #define R_HDSLS214_BASE       0x90322000UL
+ #define R_BISS14_BASE         0x90323000UL
+ #define R_ENDAT14_BASE        0x90324000UL
+ #define R_AFMT14_BASE         0x90326000UL
+ #define R_HDSLD15_BASE        0x90330000UL
+ #define R_HDSLS115_BASE       0x90331000UL
+ #define R_HDSLS215_BASE       0x90332000UL
+ #define R_BISS15_BASE         0x90333000UL
+ #define R_ENDAT15_BASE        0x90334000UL
+ #define R_AFMT15_BASE         0x90336000UL
+ #define R_GMAC1_BASE          0x92000000UL
+ #define R_GMAC2_BASE          0x92010000UL
+ #define R_USBHC_BASE          0x92040000UL
+ #define R_USBF_BASE           0x92041000UL
+ #define R_SDHI0_BASE          0x92080000UL
+ #define R_SDHI1_BASE          0x92090000UL
+ #define R_LCDC_BASE           0x920C0000UL
+ #define R_PCIE0_BASE          0x92100000UL
+ #define R_PCIE_PHY_BASE       0x92102000UL
+ #define R_PCIE1_BASE          0x92110000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+ #define R_GPT09_0        ((R_GPT00_0_Type *) R_GPT09_0_BASE)
+ #define R_GPT09_1        ((R_GPT00_0_Type *) R_GPT09_1_BASE)
+ #define R_GPT09_2        ((R_GPT00_0_Type *) R_GPT09_2_BASE)
+ #define R_GPT09_3        ((R_GPT00_0_Type *) R_GPT09_3_BASE)
+ #define R_GPT09_4        ((R_GPT00_0_Type *) R_GPT09_4_BASE)
+ #define R_GPT09_5        ((R_GPT00_0_Type *) R_GPT09_5_BASE)
+ #define R_GPT09_6        ((R_GPT00_0_Type *) R_GPT09_6_BASE)
+ #define R_CRC0           ((R_CRC0_Type *) R_CRC0_BASE)
+ #define R_SCI0           ((R_SCI0_Type *) R_SCI0_BASE)
+ #define R_SCI1           ((R_SCI0_Type *) R_SCI1_BASE)
+ #define R_SCI2           ((R_SCI0_Type *) R_SCI2_BASE)
+ #define R_SCI3           ((R_SCI0_Type *) R_SCI3_BASE)
+ #define R_SCI4           ((R_SCI0_Type *) R_SCI4_BASE)
+ #define R_SPI0           ((R_SPI0_Type *) R_SPI0_BASE)
+ #define R_SPI1           ((R_SPI0_Type *) R_SPI1_BASE)
+ #define R_SPI2           ((R_SPI0_Type *) R_SPI2_BASE)
+ #define R_ADC122         ((R_ADC122_Type *) R_ADC122_BASE)
+ #define R_CANFD          ((R_CANFD_Type *) R_CANFD_BASE)
+ #define R_CMT            ((R_CMT_Type *) R_CMT_BASE)
+ #define R_CMTW0          ((R_CMTW0_Type *) R_CMTW0_BASE)
+ #define R_CMTW1          ((R_CMTW0_Type *) R_CMTW1_BASE)
+ #define R_WDT0           ((R_WDT0_Type *) R_WDT0_BASE)
+ #define R_WDT1           ((R_WDT0_Type *) R_WDT1_BASE)
+ #define R_WDT2           ((R_WDT0_Type *) R_WDT2_BASE)
+ #define R_WDT3           ((R_WDT0_Type *) R_WDT3_BASE)
+ #define R_WDT4           ((R_WDT0_Type *) R_WDT4_BASE)
+ #define R_WDT5           ((R_WDT0_Type *) R_WDT5_BASE)
+ #define R_DOC            ((R_DOC_Type *) R_DOC_BASE)
+ #define R_TSU_B0         ((R_TSU_B0_Type *) R_TSU_B0_BASE)
+ #define R_POEG1          ((R_POEG1_Type *) R_POEG1_BASE)
+ #define R_IIC0           ((R_IIC0_Type *) R_IIC0_BASE)
+ #define R_IIC1           ((R_IIC0_Type *) R_IIC1_BASE)
+ #define R_DMAC0          ((R_DMAC0_Type *) R_DMAC0_BASE)
+ #define R_DMAC1          ((R_DMAC0_Type *) R_DMAC1_BASE)
+ #define R_DMAC2          ((R_DMAC0_Type *) R_DMAC2_BASE)
+ #define R_GMAC0          ((R_GMAC_Type *) R_GMAC0_BASE)
+ #define R_ETHSS          ((R_ETHSS_Type *) R_ETHSS_BASE)
+ #define R_ESC_INI        ((R_ESC_INI_Type *) R_ESC_INI_BASE)
+ #define R_ETHSW_PTP      ((R_ETHSW_PTP_Type *) R_ETHSW_PTP_BASE)
+ #define R_GMACC          ((R_GMACC_Type *) R_GMACC_BASE)
+ #define R_ETHSW          ((R_ETHSW_Type *) R_ETHSW_BASE)
+ #define R_ESC            ((R_ESC_Type *) R_ESC_BASE)
+ #define R_XSPI0          ((R_XSPI0_Type *) R_XSPI0_BASE)
+ #define R_XSPI1          ((R_XSPI0_Type *) R_XSPI1_BASE)
+ #define R_BSC            ((R_BSC_Type *) R_BSC_BASE)
+ #define R_MBXSEM         ((R_MBXSEM_Type *) R_MBXSEM_BASE)
+ #define R_SHOSTIF        ((R_SHOSTIF_Type *) R_SHOSTIF_BASE)
+ #define R_SYSC_NS        ((R_SYSC_NS_Type *) R_SYSC_NS_BASE)
+ #define R_ELO            ((R_ELO_Type *) R_ELO_BASE)
+ #define R_GPT_IC         ((R_GPT_IC_Type *) R_GPT_IC_BASE)
+ #define R_ENCSS          ((R_ENCSS_Type *) R_ENCSS_BASE)
+ #define R_PCIE_SPL0      ((R_PCIE_SPL0_Type *) R_PCIE_SPL0_BASE)
+ #define R_PCIE_SPL1      ((R_PCIE_SPL0_Type *) R_PCIE_SPL1_BASE)
+ #define R_PCIE_LNK       ((R_PCIE_LNK_Type *) R_PCIE_LNK_BASE)
+ #define R_XSPI0_MISC     ((R_XSPI0_MISC_Type *) R_XSPI0_MISC_BASE)
+ #define R_XSPI1_MISC     ((R_XSPI0_MISC_Type *) R_XSPI1_MISC_BASE)
+ #define R_MD_NS          ((R_MD_NS_Type *) R_MD_NS_BASE)
+ #define R_RWP_NS         ((R_RWP_NS_Type *) R_RWP_NS_BASE)
+ #define R_ICU_NS         ((R_ICU_NS_Type *) R_ICU_NS_BASE)
+ #define R_ELC            ((R_ELC_Type *) R_ELC_BASE)
+ #define R_DMA            ((R_DMA_Type *) R_DMA_BASE)
+ #define R_PORT_SRN       ((R_PORT_COMMON_Type *) R_PORT_SRN_BASE)
+ #define R_PORT_NSR       ((R_PORT_NS_COMMON_Type *) R_PORT_NSR_BASE)
+ #define R_DDRSS          ((R_DDRSS_Type *) R_DDRSS_BASE)
+ #define R_GPT10_0        ((R_GPT10_0_Type *) R_GPT10_0_BASE)
+ #define R_GPT10_1        ((R_GPT10_0_Type *) R_GPT10_1_BASE)
+ #define R_GPT10_2        ((R_GPT10_0_Type *) R_GPT10_2_BASE)
+ #define R_GPT10_3        ((R_GPT10_0_Type *) R_GPT10_3_BASE)
+ #define R_CRC1           ((R_CRC0_Type *) R_CRC1_BASE)
+ #define R_SCI5           ((R_SCI0_Type *) R_SCI5_BASE)
+ #define R_SPI3           ((R_SPI0_Type *) R_SPI3_BASE)
+ #define R_IIC2           ((R_IIC0_Type *) R_IIC2_BASE)
+ #define R_RTC            ((R_RTC_Type *) R_RTC_BASE)
+ #define R_POEG2          ((R_POEG2_Type *) R_POEG2_BASE)
+ #define R_SYSRAM0        ((R_SYSRAM0_Type *) R_SYSRAM0_BASE)
+ #define R_SYSRAM1        ((R_SYSRAM0_Type *) R_SYSRAM1_BASE)
+ #define R_SYSRAM2        ((R_SYSRAM0_Type *) R_SYSRAM2_BASE)
+ #define R_SYSRAM3        ((R_SYSRAM0_Type *) R_SYSRAM3_BASE)
+ #define R_OTP            ((R_OTP_Type *) R_OTP_BASE)
+ #define R_MPU_AC         ((R_MPU_AC_Type *) R_MPU_AC_BASE)
+ #define R_SYSC_S         ((R_SYSC_S_Type *) R_SYSC_S_BASE)
+ #define R_CLMA0          ((R_CLMA0_Type *) R_CLMA0_BASE)
+ #define R_CLMA1          ((R_CLMA0_Type *) R_CLMA1_BASE)
+ #define R_CLMA2          ((R_CLMA0_Type *) R_CLMA2_BASE)
+ #define R_CLMA3          ((R_CLMA0_Type *) R_CLMA3_BASE)
+ #define R_CLMA4          ((R_CLMA0_Type *) R_CLMA4_BASE)
+ #define R_CLMA5          ((R_CLMA0_Type *) R_CLMA5_BASE)
+ #define R_CLMA6          ((R_CLMA0_Type *) R_CLMA6_BASE)
+ #define R_ADXC0          ((R_ADXC0_Type *) R_ADXC0_BASE)
+ #define R_SSC            ((R_SSC_Type *) R_SSC_BASE)
+ #define R_MSAC           ((R_MSAC_Type *) R_MSAC_BASE)
+ #define R_MPU10          ((R_MPU10_Type *) R_MPU10_BASE)
+ #define R_MPU11          ((R_MPU10_Type *) R_MPU11_BASE)
+ #define R_MPU12          ((R_MPU10_Type *) R_MPU12_BASE)
+ #define R_MPU13          ((R_MPU10_Type *) R_MPU13_BASE)
+ #define R_MPU14          ((R_MPU10_Type *) R_MPU14_BASE)
+ #define R_MPU15          ((R_MPU10_Type *) R_MPU15_BASE)
+ #define R_ADXC1          ((R_ADXC1_Type *) R_ADXC1_BASE)
+ #define R_MPU0           ((R_MPU10_Type *) R_MPU0_BASE)
+ #define R_MPU1           ((R_MPU10_Type *) R_MPU1_BASE)
+ #define R_MPU2           ((R_MPU10_Type *) R_MPU2_BASE)
+ #define R_MPU3           ((R_MPU10_Type *) R_MPU3_BASE)
+ #define R_MPU4           ((R_MPU10_Type *) R_MPU4_BASE)
+ #define R_MPU5           ((R_MPU10_Type *) R_MPU5_BASE)
+ #define R_MPU6           ((R_MPU10_Type *) R_MPU6_BASE)
+ #define R_MPU7           ((R_MPU10_Type *) R_MPU7_BASE)
+ #define R_MPU8           ((R_MPU10_Type *) R_MPU8_BASE)
+ #define R_MPU9           ((R_MPU10_Type *) R_MPU9_BASE)
+ #define R_SYSRAM_CTL     ((R_SYSRAM_CTL_Type *) R_SYSRAM_CTL_BASE)
+ #define R_SHOSTIF_CFG    ((R_SHOSTIF_CFG_Type *) R_SHOSTIF_CFG_BASE)
+ #define R_TCMAW          ((R_TCMAW_Type *) R_TCMAW_BASE)
+ #define R_CA55           ((R_CA55_Type *) R_CA55_BASE)
+ #define R_WDT_DBG        ((R_WDT_DBG_Type *) R_WDT_DBG_BASE)
+ #define R_RWP_S          ((R_RWP_S_Type *) R_RWP_S_BASE)
+ #define R_ICU_S          ((R_ICU_S_Type *) R_ICU_S_BASE)
+ #define R_PORT_SRS       ((R_PORT_COMMON_Type *) R_PORT_SRS_BASE)
+ #define R_GSC            ((R_GSC_Type *) R_GSC_BASE)
+ #define R_MTU            ((R_MTU_Type *) R_MTU_BASE)
+ #define R_MTU3           ((R_MTU3_Type *) R_MTU3_BASE)
+ #define R_MTU4           ((R_MTU4_Type *) R_MTU4_BASE)
+ #define R_MTU_NF         ((R_MTU_NF_Type *) R_MTU_NF_BASE)
+ #define R_MTU0           ((R_MTU0_Type *) R_MTU0_BASE)
+ #define R_MTU1           ((R_MTU1_Type *) R_MTU1_BASE)
+ #define R_MTU2           ((R_MTU2_Type *) R_MTU2_BASE)
+ #define R_MTU8           ((R_MTU8_Type *) R_MTU8_BASE)
+ #define R_MTU6           ((R_MTU6_Type *) R_MTU6_BASE)
+ #define R_MTU7           ((R_MTU7_Type *) R_MTU7_BASE)
+ #define R_MTU5           ((R_MTU5_Type *) R_MTU5_BASE)
+ #define R_GPT00_0        ((R_GPT00_0_Type *) R_GPT00_0_BASE)
+ #define R_GPT00_1        ((R_GPT00_0_Type *) R_GPT00_1_BASE)
+ #define R_GPT00_2        ((R_GPT00_0_Type *) R_GPT00_2_BASE)
+ #define R_GPT00_3        ((R_GPT00_0_Type *) R_GPT00_3_BASE)
+ #define R_GPT00_4        ((R_GPT00_0_Type *) R_GPT00_4_BASE)
+ #define R_GPT01_0        ((R_GPT00_0_Type *) R_GPT01_0_BASE)
+ #define R_GPT01_1        ((R_GPT00_0_Type *) R_GPT01_1_BASE)
+ #define R_GPT01_2        ((R_GPT00_0_Type *) R_GPT01_2_BASE)
+ #define R_GPT01_3        ((R_GPT00_0_Type *) R_GPT01_3_BASE)
+ #define R_GPT01_4        ((R_GPT00_0_Type *) R_GPT01_4_BASE)
+ #define R_GPT02_0        ((R_GPT00_0_Type *) R_GPT02_0_BASE)
+ #define R_GPT02_1        ((R_GPT00_0_Type *) R_GPT02_1_BASE)
+ #define R_GPT02_2        ((R_GPT00_0_Type *) R_GPT02_2_BASE)
+ #define R_GPT02_3        ((R_GPT00_0_Type *) R_GPT02_3_BASE)
+ #define R_GPT02_4        ((R_GPT00_0_Type *) R_GPT02_4_BASE)
+ #define R_GPT03_0        ((R_GPT00_0_Type *) R_GPT03_0_BASE)
+ #define R_GPT03_1        ((R_GPT00_0_Type *) R_GPT03_1_BASE)
+ #define R_GPT03_2        ((R_GPT00_0_Type *) R_GPT03_2_BASE)
+ #define R_GPT03_3        ((R_GPT00_0_Type *) R_GPT03_3_BASE)
+ #define R_GPT03_4        ((R_GPT00_0_Type *) R_GPT03_4_BASE)
+ #define R_GPT04_0        ((R_GPT00_0_Type *) R_GPT04_0_BASE)
+ #define R_GPT04_1        ((R_GPT00_0_Type *) R_GPT04_1_BASE)
+ #define R_GPT04_2        ((R_GPT00_0_Type *) R_GPT04_2_BASE)
+ #define R_GPT04_3        ((R_GPT00_0_Type *) R_GPT04_3_BASE)
+ #define R_GPT04_4        ((R_GPT00_0_Type *) R_GPT04_4_BASE)
+ #define R_GPT05_0        ((R_GPT00_0_Type *) R_GPT05_0_BASE)
+ #define R_GPT05_1        ((R_GPT00_0_Type *) R_GPT05_1_BASE)
+ #define R_GPT05_2        ((R_GPT00_0_Type *) R_GPT05_2_BASE)
+ #define R_GPT05_3        ((R_GPT00_0_Type *) R_GPT05_3_BASE)
+ #define R_GPT05_4        ((R_GPT00_0_Type *) R_GPT05_4_BASE)
+ #define R_TFU0           ((R_TFU0_Type *) R_TFU0_BASE)
+ #define R_ADC120         ((R_ADC120_Type *) R_ADC120_BASE)
+ #define R_ADC121         ((R_ADC120_Type *) R_ADC121_BASE)
+ #define R_POE3           ((R_POE3_Type *) R_POE3_BASE)
+ #define R_POEG0          ((R_POEG0_Type *) R_POEG0_BASE)
+ #define R_DSMIF0         ((R_DSMIF0_Type *) R_DSMIF0_BASE)
+ #define R_DSMIF1         ((R_DSMIF0_Type *) R_DSMIF1_BASE)
+ #define R_DSMIF2         ((R_DSMIF0_Type *) R_DSMIF2_BASE)
+ #define R_DSMIF3         ((R_DSMIF0_Type *) R_DSMIF3_BASE)
+ #define R_DSMIF4         ((R_DSMIF0_Type *) R_DSMIF4_BASE)
+ #define R_DSMIF5         ((R_DSMIF0_Type *) R_DSMIF5_BASE)
+ #define R_SCIE0          ((R_SCI0_Type *) R_SCIE0_BASE)
+ #define R_SCIE1          ((R_SCI0_Type *) R_SCIE1_BASE)
+ #define R_SCIE2          ((R_SCI0_Type *) R_SCIE2_BASE)
+ #define R_SCIE3          ((R_SCI0_Type *) R_SCIE3_BASE)
+ #define R_SCIE4          ((R_SCI0_Type *) R_SCIE4_BASE)
+ #define R_SCIE5          ((R_SCI0_Type *) R_SCIE5_BASE)
+ #define R_SCIE6          ((R_SCI0_Type *) R_SCIE6_BASE)
+ #define R_SCIE7          ((R_SCI0_Type *) R_SCIE7_BASE)
+ #define R_GPT06_0        ((R_GPT00_0_Type *) R_GPT06_0_BASE)
+ #define R_GPT06_1        ((R_GPT00_0_Type *) R_GPT06_1_BASE)
+ #define R_GPT06_2        ((R_GPT00_0_Type *) R_GPT06_2_BASE)
+ #define R_GPT06_3        ((R_GPT00_0_Type *) R_GPT06_3_BASE)
+ #define R_GPT06_4        ((R_GPT00_0_Type *) R_GPT06_4_BASE)
+ #define R_GPT07_0        ((R_GPT00_0_Type *) R_GPT07_0_BASE)
+ #define R_GPT07_1        ((R_GPT00_0_Type *) R_GPT07_1_BASE)
+ #define R_GPT07_2        ((R_GPT00_0_Type *) R_GPT07_2_BASE)
+ #define R_GPT07_3        ((R_GPT00_0_Type *) R_GPT07_3_BASE)
+ #define R_GPT07_4        ((R_GPT00_0_Type *) R_GPT07_4_BASE)
+ #define R_GPT08_0        ((R_GPT00_0_Type *) R_GPT08_0_BASE)
+ #define R_GPT08_1        ((R_GPT00_0_Type *) R_GPT08_1_BASE)
+ #define R_GPT08_2        ((R_GPT00_0_Type *) R_GPT08_2_BASE)
+ #define R_GPT08_3        ((R_GPT00_0_Type *) R_GPT08_3_BASE)
+ #define R_GPT08_4        ((R_GPT00_0_Type *) R_GPT08_4_BASE)
+ #define R_TFU1           ((R_TFU0_Type *) R_TFU1_BASE)
+ #define R_DSMIF6         ((R_DSMIF0_Type *) R_DSMIF6_BASE)
+ #define R_DSMIF7         ((R_DSMIF0_Type *) R_DSMIF7_BASE)
+ #define R_DSMIF8         ((R_DSMIF0_Type *) R_DSMIF8_BASE)
+ #define R_DSMIF9         ((R_DSMIF0_Type *) R_DSMIF9_BASE)
+ #define R_SCIE8          ((R_SCI0_Type *) R_SCIE8_BASE)
+ #define R_SCIE9          ((R_SCI0_Type *) R_SCIE9_BASE)
+ #define R_SCIE10         ((R_SCI0_Type *) R_SCIE10_BASE)
+ #define R_SCIE11         ((R_SCI0_Type *) R_SCIE11_BASE)
+ #define R_HDSLD0         ((R_HDSLD0_Type *) R_HDSLD0_BASE)
+ #define R_HDSLS10        ((R_HDSLS10_Type *) R_HDSLS10_BASE)
+ #define R_HDSLS20        ((R_HDSLS20_Type *) R_HDSLS20_BASE)
+ #define R_BISS0          ((R_BISS0_Type *) R_BISS0_BASE)
+ #define R_ENDAT0         ((R_ENDAT0_Type *) R_ENDAT0_BASE)
+ #define R_AFMT0          ((R_AFMT0_Type *) R_AFMT0_BASE)
+ #define R_HDSLD1         ((R_HDSLD0_Type *) R_HDSLD1_BASE)
+ #define R_HDSLS11        ((R_HDSLS10_Type *) R_HDSLS11_BASE)
+ #define R_HDSLS21        ((R_HDSLS20_Type *) R_HDSLS21_BASE)
+ #define R_BISS1          ((R_BISS0_Type *) R_BISS1_BASE)
+ #define R_ENDAT1         ((R_ENDAT0_Type *) R_ENDAT1_BASE)
+ #define R_AFMT1          ((R_AFMT0_Type *) R_AFMT1_BASE)
+ #define R_HDSLD2         ((R_HDSLD0_Type *) R_HDSLD2_BASE)
+ #define R_HDSLS12        ((R_HDSLS10_Type *) R_HDSLS12_BASE)
+ #define R_HDSLS22        ((R_HDSLS20_Type *) R_HDSLS22_BASE)
+ #define R_BISS2          ((R_BISS0_Type *) R_BISS2_BASE)
+ #define R_ENDAT2         ((R_ENDAT0_Type *) R_ENDAT2_BASE)
+ #define R_AFMT2          ((R_AFMT0_Type *) R_AFMT2_BASE)
+ #define R_HDSLD3         ((R_HDSLD0_Type *) R_HDSLD3_BASE)
+ #define R_HDSLS13        ((R_HDSLS10_Type *) R_HDSLS13_BASE)
+ #define R_HDSLS23        ((R_HDSLS20_Type *) R_HDSLS23_BASE)
+ #define R_BISS3          ((R_BISS0_Type *) R_BISS3_BASE)
+ #define R_ENDAT3         ((R_ENDAT0_Type *) R_ENDAT3_BASE)
+ #define R_AFMT3          ((R_AFMT0_Type *) R_AFMT3_BASE)
+ #define R_HDSLD4         ((R_HDSLD0_Type *) R_HDSLD4_BASE)
+ #define R_HDSLS14        ((R_HDSLS10_Type *) R_HDSLS14_BASE)
+ #define R_HDSLS24        ((R_HDSLS20_Type *) R_HDSLS24_BASE)
+ #define R_BISS4          ((R_BISS0_Type *) R_BISS4_BASE)
+ #define R_ENDAT4         ((R_ENDAT0_Type *) R_ENDAT4_BASE)
+ #define R_AFMT4          ((R_AFMT0_Type *) R_AFMT4_BASE)
+ #define R_HDSLD5         ((R_HDSLD0_Type *) R_HDSLD5_BASE)
+ #define R_HDSLS15        ((R_HDSLS10_Type *) R_HDSLS15_BASE)
+ #define R_HDSLS25        ((R_HDSLS20_Type *) R_HDSLS25_BASE)
+ #define R_BISS5          ((R_BISS0_Type *) R_BISS5_BASE)
+ #define R_ENDAT5         ((R_ENDAT0_Type *) R_ENDAT5_BASE)
+ #define R_AFMT5          ((R_AFMT0_Type *) R_AFMT5_BASE)
+ #define R_HDSLD6         ((R_HDSLD0_Type *) R_HDSLD6_BASE)
+ #define R_HDSLS16        ((R_HDSLS10_Type *) R_HDSLS16_BASE)
+ #define R_HDSLS26        ((R_HDSLS20_Type *) R_HDSLS26_BASE)
+ #define R_BISS6          ((R_BISS0_Type *) R_BISS6_BASE)
+ #define R_ENDAT6         ((R_ENDAT0_Type *) R_ENDAT6_BASE)
+ #define R_AFMT6          ((R_AFMT0_Type *) R_AFMT6_BASE)
+ #define R_HDSLD7         ((R_HDSLD0_Type *) R_HDSLD7_BASE)
+ #define R_HDSLS17        ((R_HDSLS10_Type *) R_HDSLS17_BASE)
+ #define R_HDSLS27        ((R_HDSLS20_Type *) R_HDSLS27_BASE)
+ #define R_BISS7          ((R_BISS0_Type *) R_BISS7_BASE)
+ #define R_ENDAT7         ((R_ENDAT0_Type *) R_ENDAT7_BASE)
+ #define R_AFMT7          ((R_AFMT0_Type *) R_AFMT7_BASE)
+ #define R_HDSLD8         ((R_HDSLD0_Type *) R_HDSLD8_BASE)
+ #define R_HDSLS18        ((R_HDSLS10_Type *) R_HDSLS18_BASE)
+ #define R_HDSLS28        ((R_HDSLS20_Type *) R_HDSLS28_BASE)
+ #define R_BISS8          ((R_BISS0_Type *) R_BISS8_BASE)
+ #define R_ENDAT8         ((R_ENDAT0_Type *) R_ENDAT8_BASE)
+ #define R_AFMT8          ((R_AFMT0_Type *) R_AFMT8_BASE)
+ #define R_HDSLD9         ((R_HDSLD0_Type *) R_HDSLD9_BASE)
+ #define R_HDSLS19        ((R_HDSLS10_Type *) R_HDSLS19_BASE)
+ #define R_HDSLS29        ((R_HDSLS20_Type *) R_HDSLS29_BASE)
+ #define R_BISS9          ((R_BISS0_Type *) R_BISS9_BASE)
+ #define R_ENDAT9         ((R_ENDAT0_Type *) R_ENDAT9_BASE)
+ #define R_AFMT9          ((R_AFMT0_Type *) R_AFMT9_BASE)
+ #define R_HDSLD10        ((R_HDSLD0_Type *) R_HDSLD10_BASE)
+ #define R_HDSLS110       ((R_HDSLS10_Type *) R_HDSLS110_BASE)
+ #define R_HDSLS210       ((R_HDSLS20_Type *) R_HDSLS210_BASE)
+ #define R_BISS10         ((R_BISS0_Type *) R_BISS10_BASE)
+ #define R_ENDAT10        ((R_ENDAT0_Type *) R_ENDAT10_BASE)
+ #define R_AFMT10         ((R_AFMT0_Type *) R_AFMT10_BASE)
+ #define R_HDSLD11        ((R_HDSLD0_Type *) R_HDSLD11_BASE)
+ #define R_HDSLS111       ((R_HDSLS10_Type *) R_HDSLS111_BASE)
+ #define R_HDSLS211       ((R_HDSLS20_Type *) R_HDSLS211_BASE)
+ #define R_BISS11         ((R_BISS0_Type *) R_BISS11_BASE)
+ #define R_ENDAT11        ((R_ENDAT0_Type *) R_ENDAT11_BASE)
+ #define R_AFMT11         ((R_AFMT0_Type *) R_AFMT11_BASE)
+ #define R_ENCOUT         ((R_ENCOUT_Type *) R_ENCOUT_BASE)
+ #define R_HDSLD12        ((R_HDSLD0_Type *) R_HDSLD12_BASE)
+ #define R_HDSLS112       ((R_HDSLS10_Type *) R_HDSLS112_BASE)
+ #define R_HDSLS212       ((R_HDSLS212_Type *) R_HDSLS212_BASE)
+ #define R_BISS12         ((R_BISS0_Type *) R_BISS12_BASE)
+ #define R_ENDAT12        ((R_ENDAT0_Type *) R_ENDAT12_BASE)
+ #define R_AFMT12         ((R_AFMT12_Type *) R_AFMT12_BASE)
+ #define R_HDSLD13        ((R_HDSLD0_Type *) R_HDSLD13_BASE)
+ #define R_HDSLS113       ((R_HDSLS10_Type *) R_HDSLS113_BASE)
+ #define R_HDSLS213       ((R_HDSLS212_Type *) R_HDSLS213_BASE)
+ #define R_BISS13         ((R_BISS0_Type *) R_BISS13_BASE)
+ #define R_ENDAT13        ((R_ENDAT0_Type *) R_ENDAT13_BASE)
+ #define R_AFMT13         ((R_AFMT12_Type *) R_AFMT13_BASE)
+ #define R_HDSLD14        ((R_HDSLD0_Type *) R_HDSLD14_BASE)
+ #define R_HDSLS114       ((R_HDSLS10_Type *) R_HDSLS114_BASE)
+ #define R_HDSLS214       ((R_HDSLS212_Type *) R_HDSLS214_BASE)
+ #define R_BISS14         ((R_BISS0_Type *) R_BISS14_BASE)
+ #define R_ENDAT14        ((R_ENDAT0_Type *) R_ENDAT14_BASE)
+ #define R_AFMT14         ((R_AFMT12_Type *) R_AFMT14_BASE)
+ #define R_HDSLD15        ((R_HDSLD0_Type *) R_HDSLD15_BASE)
+ #define R_HDSLS115       ((R_HDSLS10_Type *) R_HDSLS115_BASE)
+ #define R_HDSLS215       ((R_HDSLS212_Type *) R_HDSLS215_BASE)
+ #define R_BISS15         ((R_BISS0_Type *) R_BISS15_BASE)
+ #define R_ENDAT15        ((R_ENDAT0_Type *) R_ENDAT15_BASE)
+ #define R_AFMT15         ((R_AFMT12_Type *) R_AFMT15_BASE)
+ #define R_GMAC1          ((R_GMAC_Type *) R_GMAC1_BASE)
+ #define R_GMAC2          ((R_GMAC_Type *) R_GMAC2_BASE)
+ #define R_USBHC          ((R_USBHC_Type *) R_USBHC_BASE)
+ #define R_USBF           ((R_USBF_Type *) R_USBF_BASE)
+ #define R_SDHI0          ((R_SDHI0_Type *) R_SDHI0_BASE)
+ #define R_SDHI1          ((R_SDHI0_Type *) R_SDHI1_BASE)
+ #define R_LCDC           ((R_LCDC_Type *) R_LCDC_BASE)
+ #define R_PCIE0          ((R_PCIE0_Type *) R_PCIE0_BASE)
+ #define R_PCIE_PHY       ((R_PCIE_PHY_Type *) R_PCIE_PHY_BASE)
+ #define R_PCIE1          ((R_PCIE0_Type *) R_PCIE1_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+ #if defined(__CC_ARM)
+  #pragma pop
+ #elif defined(__ICCARM__)
+
+/* leave anonymous unions enabled */
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning restore
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                                 Pos/Mask Cluster Section                                  ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_clusters
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDC                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  NCFG  ========================================================== */
+ #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
+ #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
+ #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
+ #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
+/* ==========================================================  CTR  ========================================================== */
+ #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
+ #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
+ #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
+ #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
+ #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
+ #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
+ #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
+ #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
+ #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
+ #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
+ #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
+ #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
+ #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
+ #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
+ #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
+ #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
+ #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
+ #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
+ #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
+ #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  STS  ========================================================== */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
+ #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
+ #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
+ #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
+ #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
+ #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
+ #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
+ #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
+ #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
+/* =========================================================  ERFL  ========================================================== */
+ #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
+ #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
+ #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
+ #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
+ #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
+ #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
+ #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
+ #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
+ #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
+ #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
+ #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
+ #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
+ #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
+ #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDC2                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DCFG  ========================================================== */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  FDCFG  ========================================================= */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_FDCFG_GWEN_Pos      (24UL)         /*!< GWEN (Bit 24)                                         */
+ #define R_CANFD_CFDC2_FDCFG_GWEN_Msk      (0x1000000UL)  /*!< GWEN (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos     (25UL)         /*!< GWFDF (Bit 25)                                        */
+ #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk     (0x2000000UL)  /*!< GWFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos     (26UL)         /*!< GWBRS (Bit 26)                                        */
+ #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk     (0x4000000UL)  /*!< GWBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos     (31UL)         /*!< CFDTE (Bit 31)                                        */
+ #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk     (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FDCTR  ========================================================= */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
+/* =========================================================  FDCRC  ========================================================= */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (25UL)         /*!< SCNT (Bit 25)                                         */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0x1e000000UL) /*!< SCNT (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BLCT  ========================================================== */
+ #define R_CANFD_CFDC2_BLCT_BLCE_Pos       (0UL)          /*!< BLCE (Bit 0)                                          */
+ #define R_CANFD_CFDC2_BLCT_BLCE_Msk       (0x1UL)        /*!< BLCE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_BLCT_BLCLD_Pos      (8UL)          /*!< BLCLD (Bit 8)                                         */
+ #define R_CANFD_CFDC2_BLCT_BLCLD_Msk      (0x100UL)      /*!< BLCLD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  BLSTS  ========================================================= */
+ #define R_CANFD_CFDC2_BLSTS_BLC_Pos       (3UL)          /*!< BLC (Bit 3)                                           */
+ #define R_CANFD_CFDC2_BLSTS_BLC_Msk       (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          CFDGAFL                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
+/* ===========================================================  M  =========================================================== */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
+/* ==========================================================  P0  =========================================================== */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos    (4UL)          /*!< GAFLSRD0 (Bit 4)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk    (0x10UL)       /*!< GAFLSRD0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos    (5UL)          /*!< GAFLSRD1 (Bit 5)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk    (0x20UL)       /*!< GAFLSRD1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos    (6UL)          /*!< GAFLSRD2 (Bit 6)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk    (0x40UL)       /*!< GAFLSRD2 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
+/* ==========================================================  P1  =========================================================== */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x3fffUL)     /*!< GAFLFDP (Bitfield-Mask: 0x3fff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDRM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDRM_ID_RMID_Pos          (0UL)          /*!< RMID (Bit 0)                                          */
+ #define R_CANFD_CFDRM_ID_RMID_Msk          (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDRM_ID_RMRTR_Pos         (30UL)         /*!< RMRTR (Bit 30)                                        */
+ #define R_CANFD_CFDRM_ID_RMRTR_Msk         (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_ID_RMIDE_Pos         (31UL)         /*!< RMIDE (Bit 31)                                        */
+ #define R_CANFD_CFDRM_ID_RMIDE_Msk         (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDRM_PTR_RMTS_Pos         (0UL)          /*!< RMTS (Bit 0)                                          */
+ #define R_CANFD_CFDRM_PTR_RMTS_Msk         (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDRM_PTR_RMDLC_Pos        (28UL)         /*!< RMDLC (Bit 28)                                        */
+ #define R_CANFD_CFDRM_PTR_RMDLC_Msk        (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDRM_FDSTS_RMESI_Pos      (0UL)          /*!< RMESI (Bit 0)                                         */
+ #define R_CANFD_CFDRM_FDSTS_RMESI_Msk      (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos      (1UL)          /*!< RMBRS (Bit 1)                                         */
+ #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk      (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos      (2UL)          /*!< RMFDF (Bit 2)                                         */
+ #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk      (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos      (8UL)          /*!< RMIFL (Bit 8)                                         */
+ #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk      (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos      (16UL)         /*!< RMPTR (Bit 16)                                        */
+ #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk      (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DF_WD  ========================================================= */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Pos    (0UL)          /*!< RMDB_LL (Bit 0)                                       */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Msk    (0xffUL)       /*!< RMDB_LL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Pos    (8UL)          /*!< RMDB_LH (Bit 8)                                       */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Msk    (0xff00UL)     /*!< RMDB_LH (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Pos    (16UL)         /*!< RMDB_HL (Bit 16)                                      */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Msk    (0xff0000UL)   /*!< RMDB_HL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Pos    (24UL)         /*!< RMDB_HH (Bit 24)                                      */
+ #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Msk    (0xff000000UL) /*!< RMDB_HH (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDRM_DF_RMDB_Pos          (0UL)          /*!< RMDB (Bit 0)                                          */
+ #define R_CANFD_CFDRM_DF_RMDB_Msk          (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDRF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDRF_ID_RFID_Pos           (0UL)          /*!< RFID (Bit 0)                                          */
+ #define R_CANFD_CFDRF_ID_RFID_Msk           (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDRF_ID_RFRTR_Pos          (30UL)         /*!< RFRTR (Bit 30)                                        */
+ #define R_CANFD_CFDRF_ID_RFRTR_Msk          (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_ID_RFIDE_Pos          (31UL)         /*!< RFIDE (Bit 31)                                        */
+ #define R_CANFD_CFDRF_ID_RFIDE_Msk          (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDRF_PTR_RFTS_Pos          (0UL)          /*!< RFTS (Bit 0)                                          */
+ #define R_CANFD_CFDRF_PTR_RFTS_Msk          (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Pos         (28UL)         /*!< RFDLC (Bit 28)                                        */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Msk         (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Pos       (0UL)          /*!< RFESI (Bit 0)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Msk       (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos       (1UL)          /*!< RFBRS (Bit 1)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk       (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos       (2UL)          /*!< RFFDF (Bit 2)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk       (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos       (8UL)          /*!< RFIFL (Bit 8)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk       (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Pos    (16UL)         /*!< CFDRFPTR (Bit 16)                                     */
+ #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Msk    (0xffff0000UL) /*!< CFDRFPTR (Bitfield-Mask: 0xffff)                      */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDRF_DF_RFDB_Pos           (0UL)          /*!< RFDB (Bit 0)                                          */
+ #define R_CANFD_CFDRF_DF_RFDB_Msk           (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
+/* =========================================================  DF_WD  ========================================================= */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Pos     (0UL)          /*!< RFDB_LL (Bit 0)                                       */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Msk     (0xffUL)       /*!< RFDB_LL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Pos     (8UL)          /*!< RFDB_LH (Bit 8)                                       */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Msk     (0xff00UL)     /*!< RFDB_LH (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Pos     (16UL)         /*!< RFDB_HL (Bit 16)                                      */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Msk     (0xff0000UL)   /*!< RFDB_HL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Pos     (24UL)         /*!< RFDB_HH (Bit 24)                                      */
+ #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Msk     (0xff000000UL) /*!< RFDB_HH (Bitfield-Mask: 0xff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDCF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDCF_ID_CFID_Pos          (0UL)          /*!< CFID (Bit 0)                                          */
+ #define R_CANFD_CFDCF_ID_CFID_Msk          (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDCF_ID_THLEN_Pos         (29UL)         /*!< THLEN (Bit 29)                                        */
+ #define R_CANFD_CFDCF_ID_THLEN_Msk         (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_ID_CFRTR_Pos         (30UL)         /*!< CFRTR (Bit 30)                                        */
+ #define R_CANFD_CFDCF_ID_CFRTR_Msk         (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_ID_CFIDE_Pos         (31UL)         /*!< CFIDE (Bit 31)                                        */
+ #define R_CANFD_CFDCF_ID_CFIDE_Msk         (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDCF_PTR_CFTS_Pos         (0UL)          /*!< CFTS (Bit 0)                                          */
+ #define R_CANFD_CFDCF_PTR_CFTS_Msk         (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Pos        (28UL)         /*!< CFDLC (Bit 28)                                        */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Msk        (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  FDCSTS  ========================================================= */
+ #define R_CANFD_CFDCF_FDCSTS_CFESI_Pos     (0UL)          /*!< CFESI (Bit 0)                                         */
+ #define R_CANFD_CFDCF_FDCSTS_CFESI_Msk     (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDCSTS_CFBRS_Pos     (1UL)          /*!< CFBRS (Bit 1)                                         */
+ #define R_CANFD_CFDCF_FDCSTS_CFBRS_Msk     (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDCSTS_CFFDF_Pos     (2UL)          /*!< CFFDF (Bit 2)                                         */
+ #define R_CANFD_CFDCF_FDCSTS_CFFDF_Msk     (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDCSTS_CFIFL_Pos     (8UL)          /*!< CFIFL (Bit 8)                                         */
+ #define R_CANFD_CFDCF_FDCSTS_CFIFL_Msk     (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDCF_FDCSTS_CFPTR_Pos     (16UL)         /*!< CFPTR (Bit 16)                                        */
+ #define R_CANFD_CFDCF_FDCSTS_CFPTR_Msk     (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DF_WD  ========================================================= */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Pos    (0UL)          /*!< CFDB_LL (Bit 0)                                       */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Msk    (0xffUL)       /*!< CFDB_LL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Pos    (8UL)          /*!< CFDB_LH (Bit 8)                                       */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Msk    (0xff00UL)     /*!< CFDB_LH (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Pos    (16UL)         /*!< CFDB_HL (Bit 16)                                      */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Msk    (0xff0000UL)   /*!< CFDB_HL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Pos    (24UL)         /*!< CFDB_HH (Bit 24)                                      */
+ #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Msk    (0xff000000UL) /*!< CFDB_HH (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDCF_DF_CFDB_Pos          (0UL)          /*!< CFDB (Bit 0)                                          */
+ #define R_CANFD_CFDCF_DF_CFDB_Msk          (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          CFDTHL                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ACC0  ========================================================== */
+ #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
+ #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
+ #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
+ #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
+ #define R_CANFD_CFDTHL_ACC0_TGW_Pos     (15UL)         /*!< TGW (Bit 15)                                          */
+ #define R_CANFD_CFDTHL_ACC0_TGW_Msk     (0x8000UL)     /*!< TGW (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  ACC1  ========================================================== */
+ #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
+ #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDTM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDTM_ID_TMID_Pos          (0UL)          /*!< TMID (Bit 0)                                          */
+ #define R_CANFD_CFDTM_ID_TMID_Msk          (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDTM_ID_THLEN_Pos         (29UL)         /*!< THLEN (Bit 29)                                        */
+ #define R_CANFD_CFDTM_ID_THLEN_Msk         (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_ID_TMRTR_Pos         (30UL)         /*!< TMRTR (Bit 30)                                        */
+ #define R_CANFD_CFDTM_ID_TMRTR_Msk         (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_ID_TMIDE_Pos         (31UL)         /*!< TMIDE (Bit 31)                                        */
+ #define R_CANFD_CFDTM_ID_TMIDE_Msk         (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Pos        (28UL)         /*!< TMDLC (Bit 28)                                        */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Msk        (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDCTR  ========================================================= */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Pos      (0UL)          /*!< TMESI (Bit 0)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Msk      (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos      (1UL)          /*!< TMBRS (Bit 1)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk      (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos      (2UL)          /*!< TMFDF (Bit 2)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk      (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos      (8UL)          /*!< TMIFL (Bit 8)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk      (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos      (16UL)         /*!< TMPTR (Bit 16)                                        */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk      (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DF_WD  ========================================================= */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Pos    (0UL)          /*!< TMDB_LL (Bit 0)                                       */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Msk    (0xffUL)       /*!< TMDB_LL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Pos    (8UL)          /*!< TMDB_LH (Bit 8)                                       */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Msk    (0xff00UL)     /*!< TMDB_LH (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Pos    (16UL)         /*!< TMDB_HL (Bit 16)                                      */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Msk    (0xff0000UL)   /*!< TMDB_HL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Pos    (24UL)         /*!< TMDB_HH (Bit 24)                                      */
+ #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Msk    (0xff000000UL) /*!< TMDB_HH (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDTM_DF_TMDB_Pos          (0UL)          /*!< TMDB (Bit 0)                                          */
+ #define R_CANFD_CFDTM_DF_TMDB_Msk          (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            CM                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+ #define R_CMT_UNT_CM_CR_CKS_Pos     (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_CMT_UNT_CM_CR_CKS_Msk     (0x3UL)  /*!< CKS (Bitfield-Mask: 0x03)                             */
+ #define R_CMT_UNT_CM_CR_CMIE_Pos    (6UL)    /*!< CMIE (Bit 6)                                          */
+ #define R_CMT_UNT_CM_CR_CMIE_Msk    (0x40UL) /*!< CMIE (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CNT  ========================================================== */
+/* ==========================================================  COR  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                            UNT                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CMSTR0  ========================================================= */
+ #define R_CMT_UNT_CMSTR0_STR0_Pos    (0UL)   /*!< STR0 (Bit 0)                                          */
+ #define R_CMT_UNT_CMSTR0_STR0_Msk    (0x1UL) /*!< STR0 (Bitfield-Mask: 0x01)                            */
+ #define R_CMT_UNT_CMSTR0_STR1_Pos    (1UL)   /*!< STR1 (Bit 1)                                          */
+ #define R_CMT_UNT_CMSTR0_STR1_Msk    (0x2UL) /*!< STR1 (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            SAR                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_IIC0_SAR_L_SVA0_Pos    (0UL)    /*!< SVA0 (Bit 0)                                          */
+ #define R_IIC0_SAR_L_SVA0_Msk    (0x1UL)  /*!< SVA0 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_SAR_L_SVA_Pos     (1UL)    /*!< SVA (Bit 1)                                           */
+ #define R_IIC0_SAR_L_SVA_Msk     (0xfeUL) /*!< SVA (Bitfield-Mask: 0x7f)                             */
+/* ===========================================================  U  =========================================================== */
+ #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
+ #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_SAR_U_SVA_Pos     (1UL)    /*!< SVA (Bit 1)                                           */
+ #define R_IIC0_SAR_U_SVA_Msk     (0x6UL)  /*!< SVA (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                             N                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SA  =========================================================== */
+/* ==========================================================  DA  =========================================================== */
+/* ==========================================================  TB  =========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                            CH                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CRSA  ========================================================== */
+/* =========================================================  CRDA  ========================================================== */
+/* =========================================================  CRTB  ========================================================== */
+/* ========================================================  CHSTAT  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHSTAT_EN_Pos         (0UL)          /*!< EN (Bit 0)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_EN_Msk         (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_RQST_Pos       (1UL)          /*!< RQST (Bit 1)                                          */
+ #define R_DMAC0_GRP_CH_CHSTAT_RQST_Msk       (0x2UL)        /*!< RQST (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_TACT_Pos       (2UL)          /*!< TACT (Bit 2)                                          */
+ #define R_DMAC0_GRP_CH_CHSTAT_TACT_Msk       (0x4UL)        /*!< TACT (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_SUS_Pos        (3UL)          /*!< SUS (Bit 3)                                           */
+ #define R_DMAC0_GRP_CH_CHSTAT_SUS_Msk        (0x8UL)        /*!< SUS (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHSTAT_ER_Pos         (4UL)          /*!< ER (Bit 4)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_ER_Msk         (0x10UL)       /*!< ER (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_END_Pos        (5UL)          /*!< END (Bit 5)                                           */
+ #define R_DMAC0_GRP_CH_CHSTAT_END_Msk        (0x20UL)       /*!< END (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHSTAT_TC_Pos         (6UL)          /*!< TC (Bit 6)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_TC_Msk         (0x40UL)       /*!< TC (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_SR_Pos         (7UL)          /*!< SR (Bit 7)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_SR_Msk         (0x80UL)       /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_DL_Pos         (8UL)          /*!< DL (Bit 8)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_DL_Msk         (0x100UL)      /*!< DL (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_DW_Pos         (9UL)          /*!< DW (Bit 9)                                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_DW_Msk         (0x200UL)      /*!< DW (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHSTAT_DER_Pos        (10UL)         /*!< DER (Bit 10)                                          */
+ #define R_DMAC0_GRP_CH_CHSTAT_DER_Msk        (0x400UL)      /*!< DER (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHSTAT_MODE_Pos       (11UL)         /*!< MODE (Bit 11)                                         */
+ #define R_DMAC0_GRP_CH_CHSTAT_MODE_Msk       (0x800UL)      /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHSTAT_INTM_Pos       (16UL)         /*!< INTM (Bit 16)                                         */
+ #define R_DMAC0_GRP_CH_CHSTAT_INTM_Msk       (0x10000UL)    /*!< INTM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CHCTRL  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Pos      (0UL)          /*!< SETEN (Bit 0)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Msk      (0x1UL)        /*!< SETEN (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Pos      (1UL)          /*!< CLREN (Bit 1)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Msk      (0x2UL)        /*!< CLREN (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_STG_Pos        (2UL)          /*!< STG (Bit 2)                                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_STG_Msk        (0x4UL)        /*!< STG (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Pos      (3UL)          /*!< SWRST (Bit 3)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Msk      (0x8UL)        /*!< SWRST (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Pos      (4UL)          /*!< CLRRQ (Bit 4)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Msk      (0x10UL)       /*!< CLRRQ (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Pos     (5UL)          /*!< CLREND (Bit 5)                                        */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Msk     (0x20UL)       /*!< CLREND (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Pos      (6UL)          /*!< CLRTC (Bit 6)                                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Msk      (0x40UL)       /*!< CLRTC (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Pos     (8UL)          /*!< SETSUS (Bit 8)                                        */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Msk     (0x100UL)      /*!< SETSUS (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Pos     (9UL)          /*!< CLRSUS (Bit 9)                                        */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Msk     (0x200UL)      /*!< CLRSUS (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Pos    (16UL)         /*!< SETINTM (Bit 16)                                      */
+ #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Msk    (0x10000UL)    /*!< SETINTM (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Pos    (17UL)         /*!< CLRINTM (Bit 17)                                      */
+ #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Msk    (0x20000UL)    /*!< CLRINTM (Bitfield-Mask: 0x01)                         */
+/* =========================================================  CHCFG  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHCFG_SEL_Pos         (0UL)          /*!< SEL (Bit 0)                                           */
+ #define R_DMAC0_GRP_CH_CHCFG_SEL_Msk         (0x7UL)        /*!< SEL (Bitfield-Mask: 0x07)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_REQD_Pos        (3UL)          /*!< REQD (Bit 3)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_REQD_Msk        (0x8UL)        /*!< REQD (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHCFG_LOEN_Pos        (4UL)          /*!< LOEN (Bit 4)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_LOEN_Msk        (0x10UL)       /*!< LOEN (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHCFG_HIEN_Pos        (5UL)          /*!< HIEN (Bit 5)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_HIEN_Msk        (0x20UL)       /*!< HIEN (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHCFG_LVL_Pos         (6UL)          /*!< LVL (Bit 6)                                           */
+ #define R_DMAC0_GRP_CH_CHCFG_LVL_Msk         (0x40UL)       /*!< LVL (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_AM_Pos          (8UL)          /*!< AM (Bit 8)                                            */
+ #define R_DMAC0_GRP_CH_CHCFG_AM_Msk          (0x700UL)      /*!< AM (Bitfield-Mask: 0x07)                              */
+ #define R_DMAC0_GRP_CH_CHCFG_SDS_Pos         (12UL)         /*!< SDS (Bit 12)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_SDS_Msk         (0xf000UL)     /*!< SDS (Bitfield-Mask: 0x0f)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_DDS_Pos         (16UL)         /*!< DDS (Bit 16)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_DDS_Msk         (0xf0000UL)    /*!< DDS (Bitfield-Mask: 0x0f)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_SAD_Pos         (20UL)         /*!< SAD (Bit 20)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_SAD_Msk         (0x100000UL)   /*!< SAD (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_DAD_Pos         (21UL)         /*!< DAD (Bit 21)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_DAD_Msk         (0x200000UL)   /*!< DAD (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_TM_Pos          (22UL)         /*!< TM (Bit 22)                                           */
+ #define R_DMAC0_GRP_CH_CHCFG_TM_Msk          (0x400000UL)   /*!< TM (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_CH_CHCFG_DEM_Pos         (24UL)         /*!< DEM (Bit 24)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_DEM_Msk         (0x1000000UL)  /*!< DEM (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_TCM_Pos         (25UL)         /*!< TCM (Bit 25)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_TCM_Msk         (0x2000000UL)  /*!< TCM (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_SBE_Pos         (27UL)         /*!< SBE (Bit 27)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_SBE_Msk         (0x8000000UL)  /*!< SBE (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_RSEL_Pos        (28UL)         /*!< RSEL (Bit 28)                                         */
+ #define R_DMAC0_GRP_CH_CHCFG_RSEL_Msk        (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_GRP_CH_CHCFG_RSW_Pos         (29UL)         /*!< RSW (Bit 29)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_RSW_Msk         (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_REN_Pos         (30UL)         /*!< REN (Bit 30)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_REN_Msk         (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_GRP_CH_CHCFG_DMS_Pos         (31UL)         /*!< DMS (Bit 31)                                          */
+ #define R_DMAC0_GRP_CH_CHCFG_DMS_Msk         (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CHITVL  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHITVL_ITVL_Pos       (0UL)          /*!< ITVL (Bit 0)                                          */
+ #define R_DMAC0_GRP_CH_CHITVL_ITVL_Msk       (0xffffUL)     /*!< ITVL (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  CHEXT  ========================================================= */
+ #define R_DMAC0_GRP_CH_CHEXT_SPR_Pos         (0UL)          /*!< SPR (Bit 0)                                           */
+ #define R_DMAC0_GRP_CH_CHEXT_SPR_Msk         (0x7UL)        /*!< SPR (Bitfield-Mask: 0x07)                             */
+ #define R_DMAC0_GRP_CH_CHEXT_SCA_Pos         (4UL)          /*!< SCA (Bit 4)                                           */
+ #define R_DMAC0_GRP_CH_CHEXT_SCA_Msk         (0xf0UL)       /*!< SCA (Bitfield-Mask: 0x0f)                             */
+ #define R_DMAC0_GRP_CH_CHEXT_DPR_Pos         (8UL)          /*!< DPR (Bit 8)                                           */
+ #define R_DMAC0_GRP_CH_CHEXT_DPR_Msk         (0x700UL)      /*!< DPR (Bitfield-Mask: 0x07)                             */
+ #define R_DMAC0_GRP_CH_CHEXT_DCA_Pos         (12UL)         /*!< DCA (Bit 12)                                          */
+ #define R_DMAC0_GRP_CH_CHEXT_DCA_Msk         (0xf000UL)     /*!< DCA (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  NXLA  ========================================================== */
+/* =========================================================  CRLA  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                            GRP                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DCTRL  ========================================================= */
+ #define R_DMAC0_GRP_DCTRL_PR_Pos             (0UL)    /*!< PR (Bit 0)                                            */
+ #define R_DMAC0_GRP_DCTRL_PR_Msk             (0x1UL)  /*!< PR (Bitfield-Mask: 0x01)                              */
+ #define R_DMAC0_GRP_DCTRL_LVINT_Pos          (1UL)    /*!< LVINT (Bit 1)                                         */
+ #define R_DMAC0_GRP_DCTRL_LVINT_Msk          (0x2UL)  /*!< LVINT (Bitfield-Mask: 0x01)                           */
+/* =======================================================  DSTAT_EN  ======================================================== */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0008_Pos      (0UL)    /*!< EN0008 (Bit 0)                                        */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0008_Msk      (0x1UL)  /*!< EN0008 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0109_Pos      (1UL)    /*!< EN0109 (Bit 1)                                        */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0109_Msk      (0x2UL)  /*!< EN0109 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0210_Pos      (2UL)    /*!< EN0210 (Bit 2)                                        */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0210_Msk      (0x4UL)  /*!< EN0210 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0311_Pos      (3UL)    /*!< EN0311 (Bit 3)                                        */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0311_Msk      (0x8UL)  /*!< EN0311 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0412_Pos      (4UL)    /*!< EN0412 (Bit 4)                                        */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0412_Msk      (0x10UL) /*!< EN0412 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0513_Pos      (5UL)    /*!< EN0513 (Bit 5)                                        */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0513_Msk      (0x20UL) /*!< EN0513 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0614_Pos      (6UL)    /*!< EN0614 (Bit 6)                                        */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0614_Msk      (0x40UL) /*!< EN0614 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0715_Pos      (7UL)    /*!< EN0715 (Bit 7)                                        */
+ #define R_DMAC0_GRP_DSTAT_EN_EN0715_Msk      (0x80UL) /*!< EN0715 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DSTAT_ER  ======================================================== */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0008_Pos      (0UL)    /*!< ER0008 (Bit 0)                                        */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0008_Msk      (0x1UL)  /*!< ER0008 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0109_Pos      (1UL)    /*!< ER0109 (Bit 1)                                        */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0109_Msk      (0x2UL)  /*!< ER0109 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0210_Pos      (2UL)    /*!< ER0210 (Bit 2)                                        */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0210_Msk      (0x4UL)  /*!< ER0210 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0311_Pos      (3UL)    /*!< ER0311 (Bit 3)                                        */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0311_Msk      (0x8UL)  /*!< ER0311 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0412_Pos      (4UL)    /*!< ER0412 (Bit 4)                                        */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0412_Msk      (0x10UL) /*!< ER0412 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0513_Pos      (5UL)    /*!< ER0513 (Bit 5)                                        */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0513_Msk      (0x20UL) /*!< ER0513 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0614_Pos      (6UL)    /*!< ER0614 (Bit 6)                                        */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0614_Msk      (0x40UL) /*!< ER0614 (Bitfield-Mask: 0x01)                          */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0715_Pos      (7UL)    /*!< ER0715 (Bit 7)                                        */
+ #define R_DMAC0_GRP_DSTAT_ER_ER0715_Msk      (0x80UL) /*!< ER0715 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DSTAT_END  ======================================================= */
+ #define R_DMAC0_GRP_DSTAT_END_END0008_Pos    (0UL)    /*!< END0008 (Bit 0)                                       */
+ #define R_DMAC0_GRP_DSTAT_END_END0008_Msk    (0x1UL)  /*!< END0008 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_END_END0109_Pos    (1UL)    /*!< END0109 (Bit 1)                                       */
+ #define R_DMAC0_GRP_DSTAT_END_END0109_Msk    (0x2UL)  /*!< END0109 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_END_END0210_Pos    (2UL)    /*!< END0210 (Bit 2)                                       */
+ #define R_DMAC0_GRP_DSTAT_END_END0210_Msk    (0x4UL)  /*!< END0210 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_END_END0311_Pos    (3UL)    /*!< END0311 (Bit 3)                                       */
+ #define R_DMAC0_GRP_DSTAT_END_END0311_Msk    (0x8UL)  /*!< END0311 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_END_END0412_Pos    (4UL)    /*!< END0412 (Bit 4)                                       */
+ #define R_DMAC0_GRP_DSTAT_END_END0412_Msk    (0x10UL) /*!< END0412 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_END_END0513_Pos    (5UL)    /*!< END0513 (Bit 5)                                       */
+ #define R_DMAC0_GRP_DSTAT_END_END0513_Msk    (0x20UL) /*!< END0513 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_END_END0614_Pos    (6UL)    /*!< END0614 (Bit 6)                                       */
+ #define R_DMAC0_GRP_DSTAT_END_END0614_Msk    (0x40UL) /*!< END0614 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_END_END0715_Pos    (7UL)    /*!< END0715 (Bit 7)                                       */
+ #define R_DMAC0_GRP_DSTAT_END_END0715_Msk    (0x80UL) /*!< END0715 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DSTAT_SUS  ======================================================= */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0008_Pos    (0UL)    /*!< SUS0008 (Bit 0)                                       */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0008_Msk    (0x1UL)  /*!< SUS0008 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0109_Pos    (1UL)    /*!< SUS0109 (Bit 1)                                       */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0109_Msk    (0x2UL)  /*!< SUS0109 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0210_Pos    (2UL)    /*!< SUS0210 (Bit 2)                                       */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0210_Msk    (0x4UL)  /*!< SUS0210 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0311_Pos    (3UL)    /*!< SUS0311 (Bit 3)                                       */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0311_Msk    (0x8UL)  /*!< SUS0311 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0412_Pos    (4UL)    /*!< SUS0412 (Bit 4)                                       */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0412_Msk    (0x10UL) /*!< SUS0412 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0513_Pos    (5UL)    /*!< SUS0513 (Bit 5)                                       */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0513_Msk    (0x20UL) /*!< SUS0513 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0614_Pos    (6UL)    /*!< SUS0614 (Bit 6)                                       */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0614_Msk    (0x40UL) /*!< SUS0614 (Bitfield-Mask: 0x01)                         */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0715_Pos    (7UL)    /*!< SUS0715 (Bit 7)                                       */
+ #define R_DMAC0_GRP_DSTAT_SUS_SUS0715_Msk    (0x80UL) /*!< SUS0715 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           SWTM                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  EN  =========================================================== */
+ #define R_ETHSW_PTP_SWTM_EN_OUTEN_Pos         (0UL)          /*!< OUTEN (Bit 0)                                         */
+ #define R_ETHSW_PTP_SWTM_EN_OUTEN_Msk         (0x1UL)        /*!< OUTEN (Bitfield-Mask: 0x01)                           */
+/* =========================================================  STSEC  ========================================================= */
+ #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Pos      (0UL)          /*!< STSEC (Bit 0)                                         */
+ #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Msk      (0xffffffffUL) /*!< STSEC (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  STNS  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_STNS_STNS_Pos        (0UL)          /*!< STNS (Bit 0)                                          */
+ #define R_ETHSW_PTP_SWTM_STNS_STNS_Msk        (0xffffffffUL) /*!< STNS (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  PSEC  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Pos        (0UL)          /*!< PSEC (Bit 0)                                          */
+ #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Msk        (0xffffffffUL) /*!< PSEC (Bitfield-Mask: 0xffffffff)                      */
+/* ==========================================================  PNS  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_PNS_PNS_Pos          (0UL)          /*!< PNS (Bit 0)                                           */
+ #define R_ETHSW_PTP_SWTM_PNS_PNS_Msk          (0xffffffffUL) /*!< PNS (Bitfield-Mask: 0xffffffff)                       */
+/* ==========================================================  WTH  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Pos        (0UL)          /*!< WIDTH (Bit 0)                                         */
+ #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Msk        (0xffffUL)     /*!< WIDTH (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  MAXP  ========================================================== */
+ #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Pos        (0UL)          /*!< MAXP (Bit 0)                                          */
+ #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Msk        (0xffffffffUL) /*!< MAXP (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  LATSEC  ========================================================= */
+ #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Pos    (0UL)          /*!< LATSEC (Bit 0)                                        */
+ #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Msk    (0xffffffffUL) /*!< LATSEC (Bitfield-Mask: 0xffffffff)                    */
+/* =========================================================  LATNS  ========================================================= */
+ #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Pos      (0UL)          /*!< LATNS (Bit 0)                                         */
+ #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Msk      (0xffffffffUL) /*!< LATNS (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                         MGMT_ADDR                                         ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  lo  =========================================================== */
+ #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Pos    (0UL)          /*!< BPDU_DST (Bit 0)                                      */
+ #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Msk    (0xffffffffUL) /*!< BPDU_DST (Bitfield-Mask: 0xffffffff)                  */
+/* ==========================================================  hi  =========================================================== */
+ #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Pos    (0UL)          /*!< BPDU_DST (Bit 0)                                      */
+ #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Msk    (0xffffUL)     /*!< BPDU_DST (Bitfield-Mask: 0xffff)                      */
+ #define R_ETHSW_MGMT_ADDR_hi_MASK_Pos        (16UL)         /*!< MASK (Bit 16)                                         */
+ #define R_ETHSW_MGMT_ADDR_hi_MASK_Msk        (0xff0000UL)   /*!< MASK (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           FMMU                                            ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  L_START_ADR  ====================================================== */
+ #define R_ESC_FMMU_L_START_ADR_LSTAADR_Pos      (0UL)          /*!< LSTAADR (Bit 0)                                       */
+ #define R_ESC_FMMU_L_START_ADR_LSTAADR_Msk      (0xffffffffUL) /*!< LSTAADR (Bitfield-Mask: 0xffffffff)                   */
+/* ==========================================================  LEN  ========================================================== */
+ #define R_ESC_FMMU_LEN_FMMULEN_Pos              (0UL)          /*!< FMMULEN (Bit 0)                                       */
+ #define R_ESC_FMMU_LEN_FMMULEN_Msk              (0xffffUL)     /*!< FMMULEN (Bitfield-Mask: 0xffff)                       */
+/* ======================================================  L_START_BIT  ====================================================== */
+ #define R_ESC_FMMU_L_START_BIT_LSTABIT_Pos      (0UL)          /*!< LSTABIT (Bit 0)                                       */
+ #define R_ESC_FMMU_L_START_BIT_LSTABIT_Msk      (0x7UL)        /*!< LSTABIT (Bitfield-Mask: 0x07)                         */
+/* ======================================================  L_STOP_BIT  ======================================================= */
+ #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Pos       (0UL)          /*!< LSTPBIT (Bit 0)                                       */
+ #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Msk       (0x7UL)        /*!< LSTPBIT (Bitfield-Mask: 0x07)                         */
+/* ======================================================  P_START_ADR  ====================================================== */
+ #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Pos    (0UL)          /*!< PHYSTAADR (Bit 0)                                     */
+ #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Msk    (0xffffUL)     /*!< PHYSTAADR (Bitfield-Mask: 0xffff)                     */
+/* ======================================================  P_START_BIT  ====================================================== */
+ #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Pos    (0UL)          /*!< PHYSTABIT (Bit 0)                                     */
+ #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Msk    (0x7UL)        /*!< PHYSTABIT (Bitfield-Mask: 0x07)                       */
+/* =========================================================  TYPE  ========================================================== */
+ #define R_ESC_FMMU_TYPE_READ_Pos                (0UL)          /*!< READ (Bit 0)                                          */
+ #define R_ESC_FMMU_TYPE_READ_Msk                (0x1UL)        /*!< READ (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_FMMU_TYPE_WRITE_Pos               (1UL)          /*!< WRITE (Bit 1)                                         */
+ #define R_ESC_FMMU_TYPE_WRITE_Msk               (0x2UL)        /*!< WRITE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  ACT  ========================================================== */
+ #define R_ESC_FMMU_ACT_ACTIVATE_Pos             (0UL)          /*!< ACTIVATE (Bit 0)                                      */
+ #define R_ESC_FMMU_ACT_ACTIVATE_Msk             (0x1UL)        /*!< ACTIVATE (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                            SM                                             ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  P_START_ADR  ====================================================== */
+ #define R_ESC_SM_P_START_ADR_SMSTAADDR_Pos    (0UL)      /*!< SMSTAADDR (Bit 0)                                     */
+ #define R_ESC_SM_P_START_ADR_SMSTAADDR_Msk    (0xffffUL) /*!< SMSTAADDR (Bitfield-Mask: 0xffff)                     */
+/* ==========================================================  LEN  ========================================================== */
+ #define R_ESC_SM_LEN_SMLEN_Pos                (0UL)      /*!< SMLEN (Bit 0)                                         */
+ #define R_ESC_SM_LEN_SMLEN_Msk                (0xffffUL) /*!< SMLEN (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  CONTROL  ======================================================== */
+ #define R_ESC_SM_CONTROL_OPEMODE_Pos          (0UL)      /*!< OPEMODE (Bit 0)                                       */
+ #define R_ESC_SM_CONTROL_OPEMODE_Msk          (0x3UL)    /*!< OPEMODE (Bitfield-Mask: 0x03)                         */
+ #define R_ESC_SM_CONTROL_DIR_Pos              (2UL)      /*!< DIR (Bit 2)                                           */
+ #define R_ESC_SM_CONTROL_DIR_Msk              (0xcUL)    /*!< DIR (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_SM_CONTROL_IRQECAT_Pos          (4UL)      /*!< IRQECAT (Bit 4)                                       */
+ #define R_ESC_SM_CONTROL_IRQECAT_Msk          (0x10UL)   /*!< IRQECAT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_SM_CONTROL_IRQPDI_Pos           (5UL)      /*!< IRQPDI (Bit 5)                                        */
+ #define R_ESC_SM_CONTROL_IRQPDI_Msk           (0x20UL)   /*!< IRQPDI (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_SM_CONTROL_WDTRGEN_Pos          (6UL)      /*!< WDTRGEN (Bit 6)                                       */
+ #define R_ESC_SM_CONTROL_WDTRGEN_Msk          (0x40UL)   /*!< WDTRGEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  STATUS  ========================================================= */
+ #define R_ESC_SM_STATUS_INTWR_Pos             (0UL)      /*!< INTWR (Bit 0)                                         */
+ #define R_ESC_SM_STATUS_INTWR_Msk             (0x1UL)    /*!< INTWR (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_SM_STATUS_INTRD_Pos             (1UL)      /*!< INTRD (Bit 1)                                         */
+ #define R_ESC_SM_STATUS_INTRD_Msk             (0x2UL)    /*!< INTRD (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_SM_STATUS_MAILBOX_Pos           (3UL)      /*!< MAILBOX (Bit 3)                                       */
+ #define R_ESC_SM_STATUS_MAILBOX_Msk           (0x8UL)    /*!< MAILBOX (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_SM_STATUS_BUFFERED_Pos          (4UL)      /*!< BUFFERED (Bit 4)                                      */
+ #define R_ESC_SM_STATUS_BUFFERED_Msk          (0x30UL)   /*!< BUFFERED (Bitfield-Mask: 0x03)                        */
+ #define R_ESC_SM_STATUS_RDBUF_Pos             (6UL)      /*!< RDBUF (Bit 6)                                         */
+ #define R_ESC_SM_STATUS_RDBUF_Msk             (0x40UL)   /*!< RDBUF (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_SM_STATUS_WRBUF_Pos             (7UL)      /*!< WRBUF (Bit 7)                                         */
+ #define R_ESC_SM_STATUS_WRBUF_Msk             (0x80UL)   /*!< WRBUF (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  ACT  ========================================================== */
+ #define R_ESC_SM_ACT_SMEN_Pos                 (0UL)      /*!< SMEN (Bit 0)                                          */
+ #define R_ESC_SM_ACT_SMEN_Msk                 (0x1UL)    /*!< SMEN (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_SM_ACT_REPEATREQ_Pos            (1UL)      /*!< REPEATREQ (Bit 1)                                     */
+ #define R_ESC_SM_ACT_REPEATREQ_Msk            (0x2UL)    /*!< REPEATREQ (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_SM_ACT_LATCHECAT_Pos            (6UL)      /*!< LATCHECAT (Bit 6)                                     */
+ #define R_ESC_SM_ACT_LATCHECAT_Msk            (0x40UL)   /*!< LATCHECAT (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_SM_ACT_LATCHPDI_Pos             (7UL)      /*!< LATCHPDI (Bit 7)                                      */
+ #define R_ESC_SM_ACT_LATCHPDI_Msk             (0x80UL)   /*!< LATCHPDI (Bitfield-Mask: 0x01)                        */
+/* =======================================================  PDI_CONT  ======================================================== */
+ #define R_ESC_SM_PDI_CONT_DEACTIVE_Pos        (0UL)      /*!< DEACTIVE (Bit 0)                                      */
+ #define R_ESC_SM_PDI_CONT_DEACTIVE_Msk        (0x1UL)    /*!< DEACTIVE (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_SM_PDI_CONT_REPEATACK_Pos       (1UL)      /*!< REPEATACK (Bit 1)                                     */
+ #define R_ESC_SM_PDI_CONT_REPEATACK_Msk       (0x2UL)    /*!< REPEATACK (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                            CSa                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CMCFG0  ========================================================= */
+ #define R_XSPI0_CSa_CMCFG0_FFMT_Pos       (0UL)          /*!< FFMT (Bit 0)                                          */
+ #define R_XSPI0_CSa_CMCFG0_FFMT_Msk       (0x3UL)        /*!< FFMT (Bitfield-Mask: 0x03)                            */
+ #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Pos    (2UL)          /*!< ADDSIZE (Bit 2)                                       */
+ #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Msk    (0xcUL)        /*!< ADDSIZE (Bitfield-Mask: 0x03)                         */
+ #define R_XSPI0_CSa_CMCFG0_WPBSTMD_Pos    (4UL)          /*!< WPBSTMD (Bit 4)                                       */
+ #define R_XSPI0_CSa_CMCFG0_WPBSTMD_Msk    (0x10UL)       /*!< WPBSTMD (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_CSa_CMCFG0_ARYAMD_Pos     (5UL)          /*!< ARYAMD (Bit 5)                                        */
+ #define R_XSPI0_CSa_CMCFG0_ARYAMD_Msk     (0x20UL)       /*!< ARYAMD (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Pos    (16UL)         /*!< ADDRPEN (Bit 16)                                      */
+ #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Msk    (0xff0000UL)   /*!< ADDRPEN (Bitfield-Mask: 0xff)                         */
+ #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Pos    (24UL)         /*!< ADDRPCD (Bit 24)                                      */
+ #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Msk    (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff)                         */
+/* ========================================================  CMCFG1  ========================================================= */
+ #define R_XSPI0_CSa_CMCFG1_RDCMD_Pos      (0UL)          /*!< RDCMD (Bit 0)                                         */
+ #define R_XSPI0_CSa_CMCFG1_RDCMD_Msk      (0xffffUL)     /*!< RDCMD (Bitfield-Mask: 0xffff)                         */
+ #define R_XSPI0_CSa_CMCFG1_RDLATE_Pos     (16UL)         /*!< RDLATE (Bit 16)                                       */
+ #define R_XSPI0_CSa_CMCFG1_RDLATE_Msk     (0x1f0000UL)   /*!< RDLATE (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  CMCFG2  ========================================================= */
+ #define R_XSPI0_CSa_CMCFG2_WRCMD_Pos      (0UL)          /*!< WRCMD (Bit 0)                                         */
+ #define R_XSPI0_CSa_CMCFG2_WRCMD_Msk      (0xffffUL)     /*!< WRCMD (Bitfield-Mask: 0xffff)                         */
+ #define R_XSPI0_CSa_CMCFG2_WRLATE_Pos     (16UL)         /*!< WRLATE (Bit 16)                                       */
+ #define R_XSPI0_CSa_CMCFG2_WRLATE_Msk     (0x1f0000UL)   /*!< WRLATE (Bitfield-Mask: 0x1f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                            BUF                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CDT  ========================================================== */
+ #define R_XSPI0_BUF_CDT_CMDSIZE_Pos     (0UL)          /*!< CMDSIZE (Bit 0)                                       */
+ #define R_XSPI0_BUF_CDT_CMDSIZE_Msk     (0x3UL)        /*!< CMDSIZE (Bitfield-Mask: 0x03)                         */
+ #define R_XSPI0_BUF_CDT_ADDSIZE_Pos     (2UL)          /*!< ADDSIZE (Bit 2)                                       */
+ #define R_XSPI0_BUF_CDT_ADDSIZE_Msk     (0x1cUL)       /*!< ADDSIZE (Bitfield-Mask: 0x07)                         */
+ #define R_XSPI0_BUF_CDT_DATASIZE_Pos    (5UL)          /*!< DATASIZE (Bit 5)                                      */
+ #define R_XSPI0_BUF_CDT_DATASIZE_Msk    (0x1e0UL)      /*!< DATASIZE (Bitfield-Mask: 0x0f)                        */
+ #define R_XSPI0_BUF_CDT_LATE_Pos        (9UL)          /*!< LATE (Bit 9)                                          */
+ #define R_XSPI0_BUF_CDT_LATE_Msk        (0x3e00UL)     /*!< LATE (Bitfield-Mask: 0x1f)                            */
+ #define R_XSPI0_BUF_CDT_TRTYPE_Pos      (15UL)         /*!< TRTYPE (Bit 15)                                       */
+ #define R_XSPI0_BUF_CDT_TRTYPE_Msk      (0x8000UL)     /*!< TRTYPE (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_BUF_CDT_CMD_Pos         (16UL)         /*!< CMD (Bit 16)                                          */
+ #define R_XSPI0_BUF_CDT_CMD_Msk         (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff)                           */
+/* ==========================================================  CDA  ========================================================== */
+ #define R_XSPI0_BUF_CDA_ADD_Pos         (0UL)          /*!< ADD (Bit 0)                                           */
+ #define R_XSPI0_BUF_CDA_ADD_Msk         (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff)                       */
+/* =========================================================  CDD0  ========================================================== */
+ #define R_XSPI0_BUF_CDD0_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_XSPI0_BUF_CDD0_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CDD1  ========================================================== */
+ #define R_XSPI0_BUF_CDD1_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_XSPI0_BUF_CDD1_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                            CSb                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CCCTL0  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL0_CAEN_Pos          (0UL)          /*!< CAEN (Bit 0)                                          */
+ #define R_XSPI0_CSb_CCCTL0_CAEN_Msk          (0x1UL)        /*!< CAEN (Bitfield-Mask: 0x01)                            */
+ #define R_XSPI0_CSb_CCCTL0_CANOWR_Pos        (1UL)          /*!< CANOWR (Bit 1)                                        */
+ #define R_XSPI0_CSb_CCCTL0_CANOWR_Msk        (0x2UL)        /*!< CANOWR (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_CSb_CCCTL0_CAITV_Pos         (8UL)          /*!< CAITV (Bit 8)                                         */
+ #define R_XSPI0_CSb_CCCTL0_CAITV_Msk         (0x1f00UL)     /*!< CAITV (Bitfield-Mask: 0x1f)                           */
+ #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Pos      (16UL)         /*!< CASFTSTA (Bit 16)                                     */
+ #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Msk      (0x1f0000UL)   /*!< CASFTSTA (Bitfield-Mask: 0x1f)                        */
+ #define R_XSPI0_CSb_CCCTL0_CASFTEND_Pos      (24UL)         /*!< CASFTEND (Bit 24)                                     */
+ #define R_XSPI0_CSb_CCCTL0_CASFTEND_Msk      (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f)                        */
+/* ========================================================  CCCTL1  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Pos     (0UL)          /*!< CACMDSIZE (Bit 0)                                     */
+ #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Msk     (0x3UL)        /*!< CACMDSIZE (Bitfield-Mask: 0x03)                       */
+ #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Pos     (2UL)          /*!< CAADDSIZE (Bit 2)                                     */
+ #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Msk     (0x1cUL)       /*!< CAADDSIZE (Bitfield-Mask: 0x07)                       */
+ #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Pos    (5UL)          /*!< CADATASIZE (Bit 5)                                    */
+ #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Msk    (0x1e0UL)      /*!< CADATASIZE (Bitfield-Mask: 0x0f)                      */
+ #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Pos      (16UL)         /*!< CAWRLATE (Bit 16)                                     */
+ #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Msk      (0x1f0000UL)   /*!< CAWRLATE (Bitfield-Mask: 0x1f)                        */
+ #define R_XSPI0_CSb_CCCTL1_CARDLATE_Pos      (24UL)         /*!< CARDLATE (Bit 24)                                     */
+ #define R_XSPI0_CSb_CCCTL1_CARDLATE_Msk      (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f)                        */
+/* ========================================================  CCCTL2  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Pos       (0UL)          /*!< CAWRCMD (Bit 0)                                       */
+ #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Msk       (0xffffUL)     /*!< CAWRCMD (Bitfield-Mask: 0xffff)                       */
+ #define R_XSPI0_CSb_CCCTL2_CARDCMD_Pos       (16UL)         /*!< CARDCMD (Bit 16)                                      */
+ #define R_XSPI0_CSb_CCCTL2_CARDCMD_Msk       (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  CCCTL3  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL3_CAADD_Pos         (0UL)          /*!< CAADD (Bit 0)                                         */
+ #define R_XSPI0_CSb_CCCTL3_CAADD_Msk         (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  CCCTL4  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL4_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
+ #define R_XSPI0_CSb_CCCTL4_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CCCTL5  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL5_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
+ #define R_XSPI0_CSb_CCCTL5_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CCCTL6  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL6_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
+ #define R_XSPI0_CSb_CCCTL6_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CCCTL7  ========================================================= */
+ #define R_XSPI0_CSb_CCCTL7_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
+ #define R_XSPI0_CSb_CCCTL7_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
+
+/* =========================================================================================================================== */
+/* ================                                            PFC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_PORT_SRN_PFC_L_PFC0_Pos    (0UL)          /*!< PFC0 (Bit 0)                                          */
+ #define R_PORT_SRN_PFC_L_PFC0_Msk    (0x3fUL)       /*!< PFC0 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_SRN_PFC_L_PFC1_Pos    (8UL)          /*!< PFC1 (Bit 8)                                          */
+ #define R_PORT_SRN_PFC_L_PFC1_Msk    (0x3f00UL)     /*!< PFC1 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_SRN_PFC_L_PFC2_Pos    (16UL)         /*!< PFC2 (Bit 16)                                         */
+ #define R_PORT_SRN_PFC_L_PFC2_Msk    (0x3f0000UL)   /*!< PFC2 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_SRN_PFC_L_PFC3_Pos    (24UL)         /*!< PFC3 (Bit 24)                                         */
+ #define R_PORT_SRN_PFC_L_PFC3_Msk    (0x3f000000UL) /*!< PFC3 (Bitfield-Mask: 0x3f)                            */
+/* ===========================================================  H  =========================================================== */
+ #define R_PORT_SRN_PFC_H_PFC4_Pos    (0UL)          /*!< PFC4 (Bit 0)                                          */
+ #define R_PORT_SRN_PFC_H_PFC4_Msk    (0x3fUL)       /*!< PFC4 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_SRN_PFC_H_PFC5_Pos    (8UL)          /*!< PFC5 (Bit 8)                                          */
+ #define R_PORT_SRN_PFC_H_PFC5_Msk    (0x3f00UL)     /*!< PFC5 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_SRN_PFC_H_PFC6_Pos    (16UL)         /*!< PFC6 (Bit 16)                                         */
+ #define R_PORT_SRN_PFC_H_PFC6_Msk    (0x3f0000UL)   /*!< PFC6 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_SRN_PFC_H_PFC7_Pos    (24UL)         /*!< PFC7 (Bit 24)                                         */
+ #define R_PORT_SRN_PFC_H_PFC7_Msk    (0x3f000000UL) /*!< PFC7 (Bitfield-Mask: 0x3f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           DRCTL                                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_PORT_SRN_DRCTL_L_DRV0_Pos    (0UL)          /*!< DRV0 (Bit 0)                                          */
+ #define R_PORT_SRN_DRCTL_L_DRV0_Msk    (0x3UL)        /*!< DRV0 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_L_PUD0_Pos    (2UL)          /*!< PUD0 (Bit 2)                                          */
+ #define R_PORT_SRN_DRCTL_L_PUD0_Msk    (0xcUL)        /*!< PUD0 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_L_SMT0_Pos    (4UL)          /*!< SMT0 (Bit 4)                                          */
+ #define R_PORT_SRN_DRCTL_L_SMT0_Msk    (0x10UL)       /*!< SMT0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_DRCTL_L_SR0_Pos     (5UL)          /*!< SR0 (Bit 5)                                           */
+ #define R_PORT_SRN_DRCTL_L_SR0_Msk     (0x20UL)       /*!< SR0 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_DRCTL_L_DRV1_Pos    (8UL)          /*!< DRV1 (Bit 8)                                          */
+ #define R_PORT_SRN_DRCTL_L_DRV1_Msk    (0x300UL)      /*!< DRV1 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_L_PUD1_Pos    (10UL)         /*!< PUD1 (Bit 10)                                         */
+ #define R_PORT_SRN_DRCTL_L_PUD1_Msk    (0xc00UL)      /*!< PUD1 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_L_SMT1_Pos    (12UL)         /*!< SMT1 (Bit 12)                                         */
+ #define R_PORT_SRN_DRCTL_L_SMT1_Msk    (0x1000UL)     /*!< SMT1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_DRCTL_L_SR1_Pos     (13UL)         /*!< SR1 (Bit 13)                                          */
+ #define R_PORT_SRN_DRCTL_L_SR1_Msk     (0x2000UL)     /*!< SR1 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_DRCTL_L_DRV2_Pos    (16UL)         /*!< DRV2 (Bit 16)                                         */
+ #define R_PORT_SRN_DRCTL_L_DRV2_Msk    (0x30000UL)    /*!< DRV2 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_L_PUD2_Pos    (18UL)         /*!< PUD2 (Bit 18)                                         */
+ #define R_PORT_SRN_DRCTL_L_PUD2_Msk    (0xc0000UL)    /*!< PUD2 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_L_SMT2_Pos    (20UL)         /*!< SMT2 (Bit 20)                                         */
+ #define R_PORT_SRN_DRCTL_L_SMT2_Msk    (0x100000UL)   /*!< SMT2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_DRCTL_L_SR2_Pos     (21UL)         /*!< SR2 (Bit 21)                                          */
+ #define R_PORT_SRN_DRCTL_L_SR2_Msk     (0x200000UL)   /*!< SR2 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_DRCTL_L_DRV3_Pos    (24UL)         /*!< DRV3 (Bit 24)                                         */
+ #define R_PORT_SRN_DRCTL_L_DRV3_Msk    (0x3000000UL)  /*!< DRV3 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_L_PUD3_Pos    (26UL)         /*!< PUD3 (Bit 26)                                         */
+ #define R_PORT_SRN_DRCTL_L_PUD3_Msk    (0xc000000UL)  /*!< PUD3 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_L_SMT3_Pos    (28UL)         /*!< SMT3 (Bit 28)                                         */
+ #define R_PORT_SRN_DRCTL_L_SMT3_Msk    (0x10000000UL) /*!< SMT3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_DRCTL_L_SR3_Pos     (29UL)         /*!< SR3 (Bit 29)                                          */
+ #define R_PORT_SRN_DRCTL_L_SR3_Msk     (0x20000000UL) /*!< SR3 (Bitfield-Mask: 0x01)                             */
+/* ===========================================================  H  =========================================================== */
+ #define R_PORT_SRN_DRCTL_H_DRV4_Pos    (0UL)          /*!< DRV4 (Bit 0)                                          */
+ #define R_PORT_SRN_DRCTL_H_DRV4_Msk    (0x3UL)        /*!< DRV4 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_H_PUD4_Pos    (2UL)          /*!< PUD4 (Bit 2)                                          */
+ #define R_PORT_SRN_DRCTL_H_PUD4_Msk    (0xcUL)        /*!< PUD4 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_H_SMT4_Pos    (4UL)          /*!< SMT4 (Bit 4)                                          */
+ #define R_PORT_SRN_DRCTL_H_SMT4_Msk    (0x10UL)       /*!< SMT4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_DRCTL_H_SR4_Pos     (5UL)          /*!< SR4 (Bit 5)                                           */
+ #define R_PORT_SRN_DRCTL_H_SR4_Msk     (0x20UL)       /*!< SR4 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_DRCTL_H_DRV5_Pos    (8UL)          /*!< DRV5 (Bit 8)                                          */
+ #define R_PORT_SRN_DRCTL_H_DRV5_Msk    (0x300UL)      /*!< DRV5 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_H_PUD5_Pos    (10UL)         /*!< PUD5 (Bit 10)                                         */
+ #define R_PORT_SRN_DRCTL_H_PUD5_Msk    (0xc00UL)      /*!< PUD5 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_H_SMT5_Pos    (12UL)         /*!< SMT5 (Bit 12)                                         */
+ #define R_PORT_SRN_DRCTL_H_SMT5_Msk    (0x1000UL)     /*!< SMT5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_DRCTL_H_SR5_Pos     (13UL)         /*!< SR5 (Bit 13)                                          */
+ #define R_PORT_SRN_DRCTL_H_SR5_Msk     (0x2000UL)     /*!< SR5 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_DRCTL_H_DRV6_Pos    (16UL)         /*!< DRV6 (Bit 16)                                         */
+ #define R_PORT_SRN_DRCTL_H_DRV6_Msk    (0x30000UL)    /*!< DRV6 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_H_PUD6_Pos    (18UL)         /*!< PUD6 (Bit 18)                                         */
+ #define R_PORT_SRN_DRCTL_H_PUD6_Msk    (0xc0000UL)    /*!< PUD6 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_H_SMT6_Pos    (20UL)         /*!< SMT6 (Bit 20)                                         */
+ #define R_PORT_SRN_DRCTL_H_SMT6_Msk    (0x100000UL)   /*!< SMT6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_DRCTL_H_SR6_Pos     (21UL)         /*!< SR6 (Bit 21)                                          */
+ #define R_PORT_SRN_DRCTL_H_SR6_Msk     (0x200000UL)   /*!< SR6 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_DRCTL_H_DRV7_Pos    (24UL)         /*!< DRV7 (Bit 24)                                         */
+ #define R_PORT_SRN_DRCTL_H_DRV7_Msk    (0x3000000UL)  /*!< DRV7 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_H_PUD7_Pos    (26UL)         /*!< PUD7 (Bit 26)                                         */
+ #define R_PORT_SRN_DRCTL_H_PUD7_Msk    (0xc000000UL)  /*!< PUD7 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_SRN_DRCTL_H_SMT7_Pos    (28UL)         /*!< SMT7 (Bit 28)                                         */
+ #define R_PORT_SRN_DRCTL_H_SMT7_Msk    (0x10000000UL) /*!< SMT7 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_DRCTL_H_SR7_Pos     (29UL)         /*!< SR7 (Bit 29)                                          */
+ #define R_PORT_SRN_DRCTL_H_SR7_Msk     (0x20000000UL) /*!< SR7 (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                            PFC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_PORT_NSR_PFC_L_PFC0_Pos    (0UL)          /*!< PFC0 (Bit 0)                                          */
+ #define R_PORT_NSR_PFC_L_PFC0_Msk    (0x3fUL)       /*!< PFC0 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_NSR_PFC_L_PFC1_Pos    (8UL)          /*!< PFC1 (Bit 8)                                          */
+ #define R_PORT_NSR_PFC_L_PFC1_Msk    (0x3f00UL)     /*!< PFC1 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_NSR_PFC_L_PFC2_Pos    (16UL)         /*!< PFC2 (Bit 16)                                         */
+ #define R_PORT_NSR_PFC_L_PFC2_Msk    (0x3f0000UL)   /*!< PFC2 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_NSR_PFC_L_PFC3_Pos    (24UL)         /*!< PFC3 (Bit 24)                                         */
+ #define R_PORT_NSR_PFC_L_PFC3_Msk    (0x3f000000UL) /*!< PFC3 (Bitfield-Mask: 0x3f)                            */
+/* ===========================================================  H  =========================================================== */
+ #define R_PORT_NSR_PFC_H_PFC4_Pos    (0UL)          /*!< PFC4 (Bit 0)                                          */
+ #define R_PORT_NSR_PFC_H_PFC4_Msk    (0x3fUL)       /*!< PFC4 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_NSR_PFC_H_PFC5_Pos    (8UL)          /*!< PFC5 (Bit 8)                                          */
+ #define R_PORT_NSR_PFC_H_PFC5_Msk    (0x3f00UL)     /*!< PFC5 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_NSR_PFC_H_PFC6_Pos    (16UL)         /*!< PFC6 (Bit 16)                                         */
+ #define R_PORT_NSR_PFC_H_PFC6_Msk    (0x3f0000UL)   /*!< PFC6 (Bitfield-Mask: 0x3f)                            */
+ #define R_PORT_NSR_PFC_H_PFC7_Pos    (24UL)         /*!< PFC7 (Bit 24)                                         */
+ #define R_PORT_NSR_PFC_H_PFC7_Msk    (0x3f000000UL) /*!< PFC7 (Bitfield-Mask: 0x3f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           DRCTL                                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_PORT_NSR_DRCTL_L_DRV0_Pos    (0UL)          /*!< DRV0 (Bit 0)                                          */
+ #define R_PORT_NSR_DRCTL_L_DRV0_Msk    (0x3UL)        /*!< DRV0 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_PUD0_Pos    (2UL)          /*!< PUD0 (Bit 2)                                          */
+ #define R_PORT_NSR_DRCTL_L_PUD0_Msk    (0xcUL)        /*!< PUD0 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_SMT0_Pos    (4UL)          /*!< SMT0 (Bit 4)                                          */
+ #define R_PORT_NSR_DRCTL_L_SMT0_Msk    (0x10UL)       /*!< SMT0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_L_SR0_Pos     (5UL)          /*!< SR0 (Bit 5)                                           */
+ #define R_PORT_NSR_DRCTL_L_SR0_Msk     (0x20UL)       /*!< SR0 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_L_DRV1_Pos    (8UL)          /*!< DRV1 (Bit 8)                                          */
+ #define R_PORT_NSR_DRCTL_L_DRV1_Msk    (0x300UL)      /*!< DRV1 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_PUD1_Pos    (10UL)         /*!< PUD1 (Bit 10)                                         */
+ #define R_PORT_NSR_DRCTL_L_PUD1_Msk    (0xc00UL)      /*!< PUD1 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_SMT1_Pos    (12UL)         /*!< SMT1 (Bit 12)                                         */
+ #define R_PORT_NSR_DRCTL_L_SMT1_Msk    (0x1000UL)     /*!< SMT1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_L_SR1_Pos     (13UL)         /*!< SR1 (Bit 13)                                          */
+ #define R_PORT_NSR_DRCTL_L_SR1_Msk     (0x2000UL)     /*!< SR1 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_L_DRV2_Pos    (16UL)         /*!< DRV2 (Bit 16)                                         */
+ #define R_PORT_NSR_DRCTL_L_DRV2_Msk    (0x30000UL)    /*!< DRV2 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_PUD2_Pos    (18UL)         /*!< PUD2 (Bit 18)                                         */
+ #define R_PORT_NSR_DRCTL_L_PUD2_Msk    (0xc0000UL)    /*!< PUD2 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_SMT2_Pos    (20UL)         /*!< SMT2 (Bit 20)                                         */
+ #define R_PORT_NSR_DRCTL_L_SMT2_Msk    (0x100000UL)   /*!< SMT2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_L_SR2_Pos     (21UL)         /*!< SR2 (Bit 21)                                          */
+ #define R_PORT_NSR_DRCTL_L_SR2_Msk     (0x200000UL)   /*!< SR2 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_L_DRV3_Pos    (24UL)         /*!< DRV3 (Bit 24)                                         */
+ #define R_PORT_NSR_DRCTL_L_DRV3_Msk    (0x3000000UL)  /*!< DRV3 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_PUD3_Pos    (26UL)         /*!< PUD3 (Bit 26)                                         */
+ #define R_PORT_NSR_DRCTL_L_PUD3_Msk    (0xc000000UL)  /*!< PUD3 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_L_SMT3_Pos    (28UL)         /*!< SMT3 (Bit 28)                                         */
+ #define R_PORT_NSR_DRCTL_L_SMT3_Msk    (0x10000000UL) /*!< SMT3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_L_SR3_Pos     (29UL)         /*!< SR3 (Bit 29)                                          */
+ #define R_PORT_NSR_DRCTL_L_SR3_Msk     (0x20000000UL) /*!< SR3 (Bitfield-Mask: 0x01)                             */
+/* ===========================================================  H  =========================================================== */
+ #define R_PORT_NSR_DRCTL_H_DRV4_Pos    (0UL)          /*!< DRV4 (Bit 0)                                          */
+ #define R_PORT_NSR_DRCTL_H_DRV4_Msk    (0x3UL)        /*!< DRV4 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_PUD4_Pos    (2UL)          /*!< PUD4 (Bit 2)                                          */
+ #define R_PORT_NSR_DRCTL_H_PUD4_Msk    (0xcUL)        /*!< PUD4 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_SMT4_Pos    (4UL)          /*!< SMT4 (Bit 4)                                          */
+ #define R_PORT_NSR_DRCTL_H_SMT4_Msk    (0x10UL)       /*!< SMT4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_H_SR4_Pos     (5UL)          /*!< SR4 (Bit 5)                                           */
+ #define R_PORT_NSR_DRCTL_H_SR4_Msk     (0x20UL)       /*!< SR4 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_H_DRV5_Pos    (8UL)          /*!< DRV5 (Bit 8)                                          */
+ #define R_PORT_NSR_DRCTL_H_DRV5_Msk    (0x300UL)      /*!< DRV5 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_PUD5_Pos    (10UL)         /*!< PUD5 (Bit 10)                                         */
+ #define R_PORT_NSR_DRCTL_H_PUD5_Msk    (0xc00UL)      /*!< PUD5 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_SMT5_Pos    (12UL)         /*!< SMT5 (Bit 12)                                         */
+ #define R_PORT_NSR_DRCTL_H_SMT5_Msk    (0x1000UL)     /*!< SMT5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_H_SR5_Pos     (13UL)         /*!< SR5 (Bit 13)                                          */
+ #define R_PORT_NSR_DRCTL_H_SR5_Msk     (0x2000UL)     /*!< SR5 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_H_DRV6_Pos    (16UL)         /*!< DRV6 (Bit 16)                                         */
+ #define R_PORT_NSR_DRCTL_H_DRV6_Msk    (0x30000UL)    /*!< DRV6 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_PUD6_Pos    (18UL)         /*!< PUD6 (Bit 18)                                         */
+ #define R_PORT_NSR_DRCTL_H_PUD6_Msk    (0xc0000UL)    /*!< PUD6 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_SMT6_Pos    (20UL)         /*!< SMT6 (Bit 20)                                         */
+ #define R_PORT_NSR_DRCTL_H_SMT6_Msk    (0x100000UL)   /*!< SMT6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_H_SR6_Pos     (21UL)         /*!< SR6 (Bit 21)                                          */
+ #define R_PORT_NSR_DRCTL_H_SR6_Msk     (0x200000UL)   /*!< SR6 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_DRCTL_H_DRV7_Pos    (24UL)         /*!< DRV7 (Bit 24)                                         */
+ #define R_PORT_NSR_DRCTL_H_DRV7_Msk    (0x3000000UL)  /*!< DRV7 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_PUD7_Pos    (26UL)         /*!< PUD7 (Bit 26)                                         */
+ #define R_PORT_NSR_DRCTL_H_PUD7_Msk    (0xc000000UL)  /*!< PUD7 (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_DRCTL_H_SMT7_Pos    (28UL)         /*!< SMT7 (Bit 28)                                         */
+ #define R_PORT_NSR_DRCTL_H_SMT7_Msk    (0x10000000UL) /*!< SMT7 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_DRCTL_H_SR7_Pos     (29UL)         /*!< SR7 (Bit 29)                                          */
+ #define R_PORT_NSR_DRCTL_H_SR7_Msk     (0x20000000UL) /*!< SR7 (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                         ELC_PDBF                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  BY  =========================================================== */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB0_Pos    (0UL)    /*!< PB0 (Bit 0)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB0_Msk    (0x1UL)  /*!< PB0 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB1_Pos    (1UL)    /*!< PB1 (Bit 1)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB1_Msk    (0x2UL)  /*!< PB1 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB2_Pos    (2UL)    /*!< PB2 (Bit 2)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB2_Msk    (0x4UL)  /*!< PB2 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB3_Pos    (3UL)    /*!< PB3 (Bit 3)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB3_Msk    (0x8UL)  /*!< PB3 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB4_Pos    (4UL)    /*!< PB4 (Bit 4)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB4_Msk    (0x10UL) /*!< PB4 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB5_Pos    (5UL)    /*!< PB5 (Bit 5)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB5_Msk    (0x20UL) /*!< PB5 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB6_Pos    (6UL)    /*!< PB6 (Bit 6)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB6_Msk    (0x40UL) /*!< PB6 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB7_Pos    (7UL)    /*!< PB7 (Bit 7)                                           */
+ #define R_PORT_NSR_ELC_PDBF_BY_PB7_Msk    (0x80UL) /*!< PB7 (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                             W                                             ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  EC710CTL  ======================================================== */
+ #define R_SYSRAM0_W_EC710CTL_ECEMF_Pos      (0UL)          /*!< ECEMF (Bit 0)                                         */
+ #define R_SYSRAM0_W_EC710CTL_ECEMF_Msk      (0x1UL)        /*!< ECEMF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM0_W_EC710CTL_ECER1F_Pos     (1UL)          /*!< ECER1F (Bit 1)                                        */
+ #define R_SYSRAM0_W_EC710CTL_ECER1F_Msk     (0x2UL)        /*!< ECER1F (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECER2F_Pos     (2UL)          /*!< ECER2F (Bit 2)                                        */
+ #define R_SYSRAM0_W_EC710CTL_ECER2F_Msk     (0x4UL)        /*!< ECER2F (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Pos    (3UL)          /*!< EC1EDIC (Bit 3)                                       */
+ #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Msk    (0x8UL)        /*!< EC1EDIC (Bitfield-Mask: 0x01)                         */
+ #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Pos    (4UL)          /*!< EC2EDIC (Bit 4)                                       */
+ #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Msk    (0x10UL)       /*!< EC2EDIC (Bitfield-Mask: 0x01)                         */
+ #define R_SYSRAM0_W_EC710CTL_EC1ECP_Pos     (5UL)          /*!< EC1ECP (Bit 5)                                        */
+ #define R_SYSRAM0_W_EC710CTL_EC1ECP_Msk     (0x20UL)       /*!< EC1ECP (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECERVF_Pos     (6UL)          /*!< ECERVF (Bit 6)                                        */
+ #define R_SYSRAM0_W_EC710CTL_ECERVF_Msk     (0x40UL)       /*!< ECERVF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECTHM_Pos      (7UL)          /*!< ECTHM (Bit 7)                                         */
+ #define R_SYSRAM0_W_EC710CTL_ECTHM_Msk      (0x80UL)       /*!< ECTHM (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM0_W_EC710CTL_ECER1C_Pos     (9UL)          /*!< ECER1C (Bit 9)                                        */
+ #define R_SYSRAM0_W_EC710CTL_ECER1C_Msk     (0x200UL)      /*!< ECER1C (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECER2C_Pos     (10UL)         /*!< ECER2C (Bit 10)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECER2C_Msk     (0x400UL)      /*!< ECER2C (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECOVFF_Pos     (11UL)         /*!< ECOVFF (Bit 11)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECOVFF_Msk     (0x800UL)      /*!< ECOVFF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710CTL_EMCA_Pos       (14UL)         /*!< EMCA (Bit 14)                                         */
+ #define R_SYSRAM0_W_EC710CTL_EMCA_Msk       (0xc000UL)     /*!< EMCA (Bitfield-Mask: 0x03)                            */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF0_Pos     (16UL)         /*!< ECEDF0 (Bit 16)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF0_Msk     (0x30000UL)    /*!< ECEDF0 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF1_Pos     (18UL)         /*!< ECEDF1 (Bit 18)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF1_Msk     (0xc0000UL)    /*!< ECEDF1 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF2_Pos     (20UL)         /*!< ECEDF2 (Bit 20)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF2_Msk     (0x300000UL)   /*!< ECEDF2 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF3_Pos     (22UL)         /*!< ECEDF3 (Bit 22)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF3_Msk     (0xc00000UL)   /*!< ECEDF3 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF4_Pos     (24UL)         /*!< ECEDF4 (Bit 24)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF4_Msk     (0x3000000UL)  /*!< ECEDF4 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF5_Pos     (26UL)         /*!< ECEDF5 (Bit 26)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF5_Msk     (0xc000000UL)  /*!< ECEDF5 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF6_Pos     (28UL)         /*!< ECEDF6 (Bit 28)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF6_Msk     (0x30000000UL) /*!< ECEDF6 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF7_Pos     (30UL)         /*!< ECEDF7 (Bit 30)                                       */
+ #define R_SYSRAM0_W_EC710CTL_ECEDF7_Msk     (0xc0000000UL) /*!< ECEDF7 (Bitfield-Mask: 0x03)                          */
+/* =======================================================  EC710TMC  ======================================================== */
+ #define R_SYSRAM0_W_EC710TMC_ECREIS_Pos     (0UL)          /*!< ECREIS (Bit 0)                                        */
+ #define R_SYSRAM0_W_EC710TMC_ECREIS_Msk     (0x1UL)        /*!< ECREIS (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710TMC_ECDCS_Pos      (1UL)          /*!< ECDCS (Bit 1)                                         */
+ #define R_SYSRAM0_W_EC710TMC_ECDCS_Msk      (0x2UL)        /*!< ECDCS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM0_W_EC710TMC_ECENS_Pos      (2UL)          /*!< ECENS (Bit 2)                                         */
+ #define R_SYSRAM0_W_EC710TMC_ECENS_Msk      (0x4UL)        /*!< ECENS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM0_W_EC710TMC_ECREOS_Pos     (3UL)          /*!< ECREOS (Bit 3)                                        */
+ #define R_SYSRAM0_W_EC710TMC_ECREOS_Msk     (0x8UL)        /*!< ECREOS (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710TMC_ECTRRS_Pos     (4UL)          /*!< ECTRRS (Bit 4)                                        */
+ #define R_SYSRAM0_W_EC710TMC_ECTRRS_Msk     (0x10UL)       /*!< ECTRRS (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710TMC_ECTMCE_Pos     (7UL)          /*!< ECTMCE (Bit 7)                                        */
+ #define R_SYSRAM0_W_EC710TMC_ECTMCE_Msk     (0x80UL)       /*!< ECTMCE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSRAM0_W_EC710TMC_ETMA_Pos       (14UL)         /*!< ETMA (Bit 14)                                         */
+ #define R_SYSRAM0_W_EC710TMC_ETMA_Msk       (0xc000UL)     /*!< ETMA (Bitfield-Mask: 0x03)                            */
+/* =======================================================  EC710TRC  ======================================================== */
+ #define R_SYSRAM0_W_EC710TRC_ECERDB_Pos     (0UL)          /*!< ECERDB (Bit 0)                                        */
+ #define R_SYSRAM0_W_EC710TRC_ECERDB_Msk     (0x7fUL)       /*!< ECERDB (Bitfield-Mask: 0x7f)                          */
+ #define R_SYSRAM0_W_EC710TRC_ECECRD_Pos     (8UL)          /*!< ECECRD (Bit 8)                                        */
+ #define R_SYSRAM0_W_EC710TRC_ECECRD_Msk     (0x7f00UL)     /*!< ECECRD (Bitfield-Mask: 0x7f)                          */
+ #define R_SYSRAM0_W_EC710TRC_ECHORD_Pos     (16UL)         /*!< ECHORD (Bit 16)                                       */
+ #define R_SYSRAM0_W_EC710TRC_ECHORD_Msk     (0x7f0000UL)   /*!< ECHORD (Bitfield-Mask: 0x7f)                          */
+ #define R_SYSRAM0_W_EC710TRC_ECSYND_Pos     (24UL)         /*!< ECSYND (Bit 24)                                       */
+ #define R_SYSRAM0_W_EC710TRC_ECSYND_Msk     (0x7f000000UL) /*!< ECSYND (Bitfield-Mask: 0x7f)                          */
+/* =======================================================  EC710TED  ======================================================== */
+ #define R_SYSRAM0_W_EC710TED_ECEDB_Pos      (0UL)          /*!< ECEDB (Bit 0)                                         */
+ #define R_SYSRAM0_W_EC710TED_ECEDB_Msk      (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff)                     */
+/* =======================================================  EC710EAD  ======================================================== */
+ #define R_SYSRAM0_W_EC710EAD_ECEAD_Pos      (0UL)          /*!< ECEAD (Bit 0)                                         */
+ #define R_SYSRAM0_W_EC710EAD_ECEAD_Msk      (0x7fffUL)     /*!< ECEAD (Bitfield-Mask: 0x7fff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                            RGN                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  STADD  ========================================================= */
+ #define R_MPU10_RGN_STADD_RDPR_Pos         (0UL)          /*!< RDPR (Bit 0)                                          */
+ #define R_MPU10_RGN_STADD_RDPR_Msk         (0x1UL)        /*!< RDPR (Bitfield-Mask: 0x01)                            */
+ #define R_MPU10_RGN_STADD_WRPR_Pos         (1UL)          /*!< WRPR (Bit 1)                                          */
+ #define R_MPU10_RGN_STADD_WRPR_Msk         (0x2UL)        /*!< WRPR (Bitfield-Mask: 0x01)                            */
+ #define R_MPU10_RGN_STADD_STADDR2_Pos      (4UL)          /*!< STADDR2 (Bit 4)                                       */
+ #define R_MPU10_RGN_STADD_STADDR2_Msk      (0x70UL)       /*!< STADDR2 (Bitfield-Mask: 0x07)                         */
+ #define R_MPU10_RGN_STADD_STADDR_Pos       (10UL)         /*!< STADDR (Bit 10)                                       */
+ #define R_MPU10_RGN_STADD_STADDR_Msk       (0xfffffc00UL) /*!< STADDR (Bitfield-Mask: 0x3fffff)                      */
+/* ========================================================  ENDADD  ========================================================= */
+ #define R_MPU10_RGN_ENDADD_ENDADDR2_Pos    (4UL)          /*!< ENDADDR2 (Bit 4)                                      */
+ #define R_MPU10_RGN_ENDADD_ENDADDR2_Msk    (0x70UL)       /*!< ENDADDR2 (Bitfield-Mask: 0x07)                        */
+ #define R_MPU10_RGN_ENDADD_ENDADDR_Pos     (10UL)         /*!< ENDADDR (Bit 10)                                      */
+ #define R_MPU10_RGN_ENDADD_ENDADDR_Msk     (0xfffffc00UL) /*!< ENDADDR (Bitfield-Mask: 0x3fffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                           RVBA                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_CA55_RVBA_L_RVBARADDRL_Pos    (2UL)          /*!< RVBARADDRL (Bit 2)                                    */
+ #define R_CA55_RVBA_L_RVBARADDRL_Msk    (0xfffffffcUL) /*!< RVBARADDRL (Bitfield-Mask: 0x3fffffff)                */
+/* ===========================================================  H  =========================================================== */
+ #define R_CA55_RVBA_H_RVBARADDRH_Pos    (0UL)          /*!< RVBARADDRH (Bit 0)                                    */
+ #define R_CA55_RVBA_H_RVBARADDRH_Msk    (0xffUL)       /*!< RVBARADDRH (Bitfield-Mask: 0xff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                            TR                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DSOCL  ========================================================= */
+ #define R_DSMIF0_CH_TR_DSOCL_OCMPTBL0_Pos    (0UL)      /*!< OCMPTBL0 (Bit 0)                                      */
+ #define R_DSMIF0_CH_TR_DSOCL_OCMPTBL0_Msk    (0xffffUL) /*!< OCMPTBL0 (Bitfield-Mask: 0xffff)                      */
+/* =========================================================  DSOCH  ========================================================= */
+ #define R_DSMIF0_CH_TR_DSOCH_OCMPTBH0_Pos    (0UL)      /*!< OCMPTBH0 (Bit 0)                                      */
+ #define R_DSMIF0_CH_TR_DSOCH_OCMPTBH0_Msk    (0xffffUL) /*!< OCMPTBH0 (Bitfield-Mask: 0xffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                            DR                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DSCOC  ========================================================= */
+ #define R_DSMIF0_CH_DR_DSCOC_CODR0_Pos    (0UL)      /*!< CODR0 (Bit 0)                                         */
+ #define R_DSMIF0_CH_DR_DSCOC_CODR0_Msk    (0xffffUL) /*!< CODR0 (Bitfield-Mask: 0xffff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                            CH                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DSICR  ========================================================= */
+ #define R_DSMIF0_CH_DSICR_IUE_Pos          (0UL)          /*!< IUE (Bit 0)                                           */
+ #define R_DSMIF0_CH_DSICR_IUE_Msk          (0x1UL)        /*!< IUE (Bitfield-Mask: 0x01)                             */
+ #define R_DSMIF0_CH_DSICR_IAUE_Pos         (1UL)          /*!< IAUE (Bit 1)                                          */
+ #define R_DSMIF0_CH_DSICR_IAUE_Msk         (0x2UL)        /*!< IAUE (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSICR_IBUE_Pos         (2UL)          /*!< IBUE (Bit 2)                                          */
+ #define R_DSMIF0_CH_DSICR_IBUE_Msk         (0x4UL)        /*!< IBUE (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSICR_ISE_Pos          (3UL)          /*!< ISE (Bit 3)                                           */
+ #define R_DSMIF0_CH_DSICR_ISE_Msk          (0x8UL)        /*!< ISE (Bitfield-Mask: 0x01)                             */
+ #define R_DSMIF0_CH_DSICR_IOEL0_Pos        (8UL)          /*!< IOEL0 (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSICR_IOEL0_Msk        (0x100UL)      /*!< IOEL0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_IOEH0_Pos        (9UL)          /*!< IOEH0 (Bit 9)                                         */
+ #define R_DSMIF0_CH_DSICR_IOEH0_Msk        (0x200UL)      /*!< IOEH0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_IOEL1_Pos        (10UL)         /*!< IOEL1 (Bit 10)                                        */
+ #define R_DSMIF0_CH_DSICR_IOEL1_Msk        (0x400UL)      /*!< IOEL1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_IOEH1_Pos        (11UL)         /*!< IOEH1 (Bit 11)                                        */
+ #define R_DSMIF0_CH_DSICR_IOEH1_Msk        (0x800UL)      /*!< IOEH1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_IOEL2_Pos        (12UL)         /*!< IOEL2 (Bit 12)                                        */
+ #define R_DSMIF0_CH_DSICR_IOEL2_Msk        (0x1000UL)     /*!< IOEL2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_IOEH2_Pos        (13UL)         /*!< IOEH2 (Bit 13)                                        */
+ #define R_DSMIF0_CH_DSICR_IOEH2_Msk        (0x2000UL)     /*!< IOEH2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_OWNE0_Pos        (16UL)         /*!< OWNE0 (Bit 16)                                        */
+ #define R_DSMIF0_CH_DSICR_OWNE0_Msk        (0x10000UL)    /*!< OWNE0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_OWNE1_Pos        (17UL)         /*!< OWNE1 (Bit 17)                                        */
+ #define R_DSMIF0_CH_DSICR_OWNE1_Msk        (0x20000UL)    /*!< OWNE1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_OWNE2_Pos        (18UL)         /*!< OWNE2 (Bit 18)                                        */
+ #define R_DSMIF0_CH_DSICR_OWNE2_Msk        (0x40000UL)    /*!< OWNE2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSICR_OWNE3_Pos        (19UL)         /*!< OWNE3 (Bit 19)                                        */
+ #define R_DSMIF0_CH_DSICR_OWNE3_Msk        (0x80000UL)    /*!< OWNE3 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DSCMCCR  ======================================================== */
+ #define R_DSMIF0_CH_DSCMCCR_CKDIR_Pos      (0UL)          /*!< CKDIR (Bit 0)                                         */
+ #define R_DSMIF0_CH_DSCMCCR_CKDIR_Msk      (0x1UL)        /*!< CKDIR (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCMCCR_SEDGE_Pos      (7UL)          /*!< SEDGE (Bit 7)                                         */
+ #define R_DSMIF0_CH_DSCMCCR_SEDGE_Msk      (0x80UL)       /*!< SEDGE (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCMCCR_CKDIV_Pos      (8UL)          /*!< CKDIV (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSCMCCR_CKDIV_Msk      (0x3f00UL)     /*!< CKDIV (Bitfield-Mask: 0x3f)                           */
+/* ========================================================  DSCMFCR  ======================================================== */
+ #define R_DSMIF0_CH_DSCMFCR_CMSINC_Pos     (0UL)          /*!< CMSINC (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCMFCR_CMSINC_Msk     (0x3UL)        /*!< CMSINC (Bitfield-Mask: 0x03)                          */
+ #define R_DSMIF0_CH_DSCMFCR_CMDEC_Pos      (8UL)          /*!< CMDEC (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSCMFCR_CMDEC_Msk      (0xff00UL)     /*!< CMDEC (Bitfield-Mask: 0xff)                           */
+ #define R_DSMIF0_CH_DSCMFCR_CMSH_Pos       (16UL)         /*!< CMSH (Bit 16)                                         */
+ #define R_DSMIF0_CH_DSCMFCR_CMSH_Msk       (0x1f0000UL)   /*!< CMSH (Bitfield-Mask: 0x1f)                            */
+/* =======================================================  DSCMCTCR  ======================================================== */
+ #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Pos    (0UL)          /*!< CTSELA (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Msk    (0x7UL)        /*!< CTSELA (Bitfield-Mask: 0x07)                          */
+ #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Pos    (8UL)          /*!< CTSELB (Bit 8)                                        */
+ #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Msk    (0x700UL)      /*!< CTSELB (Bitfield-Mask: 0x07)                          */
+ #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Pos    (16UL)         /*!< DITSEL (Bit 16)                                       */
+ #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Msk    (0x30000UL)    /*!< DITSEL (Bitfield-Mask: 0x03)                          */
+ #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Pos     (23UL)         /*!< DEDGE (Bit 23)                                        */
+ #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Msk     (0x800000UL)   /*!< DEDGE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DSEDCR  ========================================================= */
+ #define R_DSMIF0_CH_DSEDCR_SDE_Pos         (0UL)          /*!< SDE (Bit 0)                                           */
+ #define R_DSMIF0_CH_DSEDCR_SDE_Msk         (0x1UL)        /*!< SDE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DSSCTSR  ======================================================== */
+ #define R_DSMIF0_CH_DSSCTSR_SCNTL_Pos      (0UL)          /*!< SCNTL (Bit 0)                                         */
+ #define R_DSMIF0_CH_DSSCTSR_SCNTL_Msk      (0x1fffUL)     /*!< SCNTL (Bitfield-Mask: 0x1fff)                         */
+ #define R_DSMIF0_CH_DSSCTSR_SCNTH_Pos      (16UL)         /*!< SCNTH (Bit 16)                                        */
+ #define R_DSMIF0_CH_DSSCTSR_SCNTH_Msk      (0x1fff0000UL) /*!< SCNTH (Bitfield-Mask: 0x1fff)                         */
+/* ========================================================  DSOCFCR  ======================================================== */
+ #define R_DSMIF0_CH_DSOCFCR_OCSINC_Pos     (0UL)          /*!< OCSINC (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSOCFCR_OCSINC_Msk     (0x3UL)        /*!< OCSINC (Bitfield-Mask: 0x03)                          */
+ #define R_DSMIF0_CH_DSOCFCR_OCDEC_Pos      (8UL)          /*!< OCDEC (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSOCFCR_OCDEC_Msk      (0xff00UL)     /*!< OCDEC (Bitfield-Mask: 0xff)                           */
+ #define R_DSMIF0_CH_DSOCFCR_OCSH_Pos       (16UL)         /*!< OCSH (Bit 16)                                         */
+ #define R_DSMIF0_CH_DSOCFCR_OCSH_Msk       (0x1f0000UL)   /*!< OCSH (Bitfield-Mask: 0x1f)                            */
+/* ========================================================  DSODCR  ========================================================= */
+ #define R_DSMIF0_CH_DSODCR_ODEL0_Pos       (0UL)          /*!< ODEL0 (Bit 0)                                         */
+ #define R_DSMIF0_CH_DSODCR_ODEL0_Msk       (0x1UL)        /*!< ODEL0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_ODEH0_Pos       (1UL)          /*!< ODEH0 (Bit 1)                                         */
+ #define R_DSMIF0_CH_DSODCR_ODEH0_Msk       (0x2UL)        /*!< ODEH0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_ODEL1_Pos       (2UL)          /*!< ODEL1 (Bit 2)                                         */
+ #define R_DSMIF0_CH_DSODCR_ODEL1_Msk       (0x4UL)        /*!< ODEL1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_ODEH1_Pos       (3UL)          /*!< ODEH1 (Bit 3)                                         */
+ #define R_DSMIF0_CH_DSODCR_ODEH1_Msk       (0x8UL)        /*!< ODEH1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_ODEL2_Pos       (4UL)          /*!< ODEL2 (Bit 4)                                         */
+ #define R_DSMIF0_CH_DSODCR_ODEL2_Msk       (0x10UL)       /*!< ODEL2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_ODEH2_Pos       (5UL)          /*!< ODEH2 (Bit 5)                                         */
+ #define R_DSMIF0_CH_DSODCR_ODEH2_Msk       (0x20UL)       /*!< ODEH2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_OWFE0_Pos       (8UL)          /*!< OWFE0 (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSODCR_OWFE0_Msk       (0x100UL)      /*!< OWFE0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_OWFE1_Pos       (9UL)          /*!< OWFE1 (Bit 9)                                         */
+ #define R_DSMIF0_CH_DSODCR_OWFE1_Msk       (0x200UL)      /*!< OWFE1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_OWFE2_Pos       (10UL)         /*!< OWFE2 (Bit 10)                                        */
+ #define R_DSMIF0_CH_DSODCR_OWFE2_Msk       (0x400UL)      /*!< OWFE2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODCR_OWFE3_Pos       (11UL)         /*!< OWFE3 (Bit 11)                                        */
+ #define R_DSMIF0_CH_DSODCR_OWFE3_Msk       (0x800UL)      /*!< OWFE3 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DSODWCR  ======================================================== */
+ #define R_DSMIF0_CH_DSODWCR_OWNM0_Pos      (0UL)          /*!< OWNM0 (Bit 0)                                         */
+ #define R_DSMIF0_CH_DSODWCR_OWNM0_Msk      (0x1UL)        /*!< OWNM0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODWCR_OWNM1_Pos      (1UL)          /*!< OWNM1 (Bit 1)                                         */
+ #define R_DSMIF0_CH_DSODWCR_OWNM1_Msk      (0x2UL)        /*!< OWNM1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODWCR_OWNM2_Pos      (2UL)          /*!< OWNM2 (Bit 2)                                         */
+ #define R_DSMIF0_CH_DSODWCR_OWNM2_Msk      (0x4UL)        /*!< OWNM2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSODWCR_OWNM3_Pos      (3UL)          /*!< OWNM3 (Bit 3)                                         */
+ #define R_DSMIF0_CH_DSODWCR_OWNM3_Msk      (0x78UL)       /*!< OWNM3 (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  DSCSTRTR  ======================================================== */
+ #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Pos    (0UL)          /*!< STRTRG (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Msk    (0x1UL)        /*!< STRTRG (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DSCSTPTR  ======================================================== */
+ #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Pos    (0UL)          /*!< STPTRG (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Msk    (0x1UL)        /*!< STPTRG (Bitfield-Mask: 0x01)                          */
+/* =========================================================  DSCDR  ========================================================= */
+ #define R_DSMIF0_CH_DSCDR_ADDR_Pos         (0UL)          /*!< ADDR (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSCDR_ADDR_Msk         (0xffffUL)     /*!< ADDR (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  DSCCDRA  ======================================================== */
+ #define R_DSMIF0_CH_DSCCDRA_CDRA_Pos       (0UL)          /*!< CDRA (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSCCDRA_CDRA_Msk       (0xffffUL)     /*!< CDRA (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  DSCCDRB  ======================================================== */
+ #define R_DSMIF0_CH_DSCCDRB_CDRB_Pos       (0UL)          /*!< CDRB (Bit 0)                                          */
+ #define R_DSMIF0_CH_DSCCDRB_CDRB_Msk       (0xffffUL)     /*!< CDRB (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  DSOCDR  ========================================================= */
+ #define R_DSMIF0_CH_DSOCDR_ODR_Pos         (0UL)          /*!< ODR (Bit 0)                                           */
+ #define R_DSMIF0_CH_DSOCDR_ODR_Msk         (0xffffUL)     /*!< ODR (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  DSCSR  ========================================================= */
+ #define R_DSMIF0_CH_DSCSR_DUF_Pos          (0UL)          /*!< DUF (Bit 0)                                           */
+ #define R_DSMIF0_CH_DSCSR_DUF_Msk          (0x1UL)        /*!< DUF (Bitfield-Mask: 0x01)                             */
+ #define R_DSMIF0_CH_DSCSR_CAUF_Pos         (1UL)          /*!< CAUF (Bit 1)                                          */
+ #define R_DSMIF0_CH_DSCSR_CAUF_Msk         (0x2UL)        /*!< CAUF (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSCSR_CBUF_Pos         (2UL)          /*!< CBUF (Bit 2)                                          */
+ #define R_DSMIF0_CH_DSCSR_CBUF_Msk         (0x4UL)        /*!< CBUF (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_CH_DSCSR_SCF_Pos          (3UL)          /*!< SCF (Bit 3)                                           */
+ #define R_DSMIF0_CH_DSCSR_SCF_Msk          (0x8UL)        /*!< SCF (Bitfield-Mask: 0x01)                             */
+ #define R_DSMIF0_CH_DSCSR_CHSTATE_Pos      (7UL)          /*!< CHSTATE (Bit 7)                                       */
+ #define R_DSMIF0_CH_DSCSR_CHSTATE_Msk      (0x80UL)       /*!< CHSTATE (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSR_OC0FL_Pos        (8UL)          /*!< OC0FL (Bit 8)                                         */
+ #define R_DSMIF0_CH_DSCSR_OC0FL_Msk        (0x100UL)      /*!< OC0FL (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OC0FH_Pos        (9UL)          /*!< OC0FH (Bit 9)                                         */
+ #define R_DSMIF0_CH_DSCSR_OC0FH_Msk        (0x200UL)      /*!< OC0FH (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OC1FL_Pos        (10UL)         /*!< OC1FL (Bit 10)                                        */
+ #define R_DSMIF0_CH_DSCSR_OC1FL_Msk        (0x400UL)      /*!< OC1FL (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OC1FH_Pos        (11UL)         /*!< OC1FH (Bit 11)                                        */
+ #define R_DSMIF0_CH_DSCSR_OC1FH_Msk        (0x800UL)      /*!< OC1FH (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OC2FL_Pos        (12UL)         /*!< OC2FL (Bit 12)                                        */
+ #define R_DSMIF0_CH_DSCSR_OC2FL_Msk        (0x1000UL)     /*!< OC2FL (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OC2FH_Pos        (13UL)         /*!< OC2FH (Bit 13)                                        */
+ #define R_DSMIF0_CH_DSCSR_OC2FH_Msk        (0x2000UL)     /*!< OC2FH (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OWD0N_Pos        (16UL)         /*!< OWD0N (Bit 16)                                        */
+ #define R_DSMIF0_CH_DSCSR_OWD0N_Msk        (0x10000UL)    /*!< OWD0N (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OWD1N_Pos        (17UL)         /*!< OWD1N (Bit 17)                                        */
+ #define R_DSMIF0_CH_DSCSR_OWD1N_Msk        (0x20000UL)    /*!< OWD1N (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OWD2N_Pos        (18UL)         /*!< OWD2N (Bit 18)                                        */
+ #define R_DSMIF0_CH_DSCSR_OWD2N_Msk        (0x40000UL)    /*!< OWD2N (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OWD3N_Pos        (19UL)         /*!< OWD3N (Bit 19)                                        */
+ #define R_DSMIF0_CH_DSCSR_OWD3N_Msk        (0x80000UL)    /*!< OWD3N (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_CH_DSCSR_OC0CMPL_Pos      (24UL)         /*!< OC0CMPL (Bit 24)                                      */
+ #define R_DSMIF0_CH_DSCSR_OC0CMPL_Msk      (0x1000000UL)  /*!< OC0CMPL (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSR_OC0CMPH_Pos      (25UL)         /*!< OC0CMPH (Bit 25)                                      */
+ #define R_DSMIF0_CH_DSCSR_OC0CMPH_Msk      (0x2000000UL)  /*!< OC0CMPH (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSR_OC1CMPL_Pos      (26UL)         /*!< OC1CMPL (Bit 26)                                      */
+ #define R_DSMIF0_CH_DSCSR_OC1CMPL_Msk      (0x4000000UL)  /*!< OC1CMPL (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSR_OC1CMPH_Pos      (27UL)         /*!< OC1CMPH (Bit 27)                                      */
+ #define R_DSMIF0_CH_DSCSR_OC1CMPH_Msk      (0x8000000UL)  /*!< OC1CMPH (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSR_OC2CMPL_Pos      (28UL)         /*!< OC2CMPL (Bit 28)                                      */
+ #define R_DSMIF0_CH_DSCSR_OC2CMPL_Msk      (0x10000000UL) /*!< OC2CMPL (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSR_OC2CMPH_Pos      (29UL)         /*!< OC2CMPH (Bit 29)                                      */
+ #define R_DSMIF0_CH_DSCSR_OC2CMPH_Msk      (0x20000000UL) /*!< OC2CMPH (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DSCSCR  ========================================================= */
+ #define R_DSMIF0_CH_DSCSCR_CLRDUF_Pos      (0UL)          /*!< CLRDUF (Bit 0)                                        */
+ #define R_DSMIF0_CH_DSCSCR_CLRDUF_Msk      (0x1UL)        /*!< CLRDUF (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_CH_DSCSCR_CLRCAUF_Pos     (1UL)          /*!< CLRCAUF (Bit 1)                                       */
+ #define R_DSMIF0_CH_DSCSCR_CLRCAUF_Msk     (0x2UL)        /*!< CLRCAUF (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSCR_CLRCBUF_Pos     (2UL)          /*!< CLRCBUF (Bit 2)                                       */
+ #define R_DSMIF0_CH_DSCSCR_CLRCBUF_Msk     (0x4UL)        /*!< CLRCBUF (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_CH_DSCSCR_CLRSCF_Pos      (3UL)          /*!< CLRSCF (Bit 3)                                        */
+ #define R_DSMIF0_CH_DSCSCR_CLRSCF_Msk      (0x8UL)        /*!< CLRSCF (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_CH_DSCSCR_CLROC0FL_Pos    (8UL)          /*!< CLROC0FL (Bit 8)                                      */
+ #define R_DSMIF0_CH_DSCSCR_CLROC0FL_Msk    (0x100UL)      /*!< CLROC0FL (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROC0FH_Pos    (9UL)          /*!< CLROC0FH (Bit 9)                                      */
+ #define R_DSMIF0_CH_DSCSCR_CLROC0FH_Msk    (0x200UL)      /*!< CLROC0FH (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROC1FL_Pos    (10UL)         /*!< CLROC1FL (Bit 10)                                     */
+ #define R_DSMIF0_CH_DSCSCR_CLROC1FL_Msk    (0x400UL)      /*!< CLROC1FL (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROC1FH_Pos    (11UL)         /*!< CLROC1FH (Bit 11)                                     */
+ #define R_DSMIF0_CH_DSCSCR_CLROC1FH_Msk    (0x800UL)      /*!< CLROC1FH (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROC2FL_Pos    (12UL)         /*!< CLROC2FL (Bit 12)                                     */
+ #define R_DSMIF0_CH_DSCSCR_CLROC2FL_Msk    (0x1000UL)     /*!< CLROC2FL (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROC2FH_Pos    (13UL)         /*!< CLROC2FH (Bit 13)                                     */
+ #define R_DSMIF0_CH_DSCSCR_CLROC2FH_Msk    (0x2000UL)     /*!< CLROC2FH (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROWD0N_Pos    (16UL)         /*!< CLROWD0N (Bit 16)                                     */
+ #define R_DSMIF0_CH_DSCSCR_CLROWD0N_Msk    (0x10000UL)    /*!< CLROWD0N (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROWD1N_Pos    (17UL)         /*!< CLROWD1N (Bit 17)                                     */
+ #define R_DSMIF0_CH_DSCSCR_CLROWD1N_Msk    (0x20000UL)    /*!< CLROWD1N (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROWD2N_Pos    (18UL)         /*!< CLROWD2N (Bit 18)                                     */
+ #define R_DSMIF0_CH_DSCSCR_CLROWD2N_Msk    (0x40000UL)    /*!< CLROWD2N (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_CH_DSCSCR_CLROWD3N_Pos    (19UL)         /*!< CLROWD3N (Bit 19)                                     */
+ #define R_DSMIF0_CH_DSCSCR_CLROWD3N_Msk    (0x80000UL)    /*!< CLROWD3N (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          SCDATA                                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+/* ===========================================================  H  =========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          PIPE_TR                                          ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  E  =========================================================== */
+ #define R_USBF_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
+ #define R_USBF_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
+ #define R_USBF_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
+/* ===========================================================  N  =========================================================== */
+ #define R_USBF_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
+ #define R_USBF_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                             N                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SA  =========================================================== */
+ #define R_USBF_CHa_N_SA_SAWD_Pos    (0UL)          /*!< SAWD (Bit 0)                                          */
+ #define R_USBF_CHa_N_SA_SAWD_Msk    (0xffffffffUL) /*!< SAWD (Bitfield-Mask: 0xffffffff)                      */
+/* ==========================================================  DA  =========================================================== */
+ #define R_USBF_CHa_N_DA_DA_Pos      (0UL)          /*!< DA (Bit 0)                                            */
+ #define R_USBF_CHa_N_DA_DA_Msk      (0xffffffffUL) /*!< DA (Bitfield-Mask: 0xffffffff)                        */
+/* ==========================================================  TB  =========================================================== */
+ #define R_USBF_CHa_N_TB_TB_Pos      (0UL)          /*!< TB (Bit 0)                                            */
+ #define R_USBF_CHa_N_TB_TB_Msk      (0xffffffffUL) /*!< TB (Bitfield-Mask: 0xffffffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                            CHa                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CRSA  ========================================================== */
+ #define R_USBF_CHa_CRSA_CRSA_Pos           (0UL)          /*!< CRSA (Bit 0)                                          */
+ #define R_USBF_CHa_CRSA_CRSA_Msk           (0xffffffffUL) /*!< CRSA (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CRDA  ========================================================== */
+ #define R_USBF_CHa_CRDA_CRDA_Pos           (0UL)          /*!< CRDA (Bit 0)                                          */
+ #define R_USBF_CHa_CRDA_CRDA_Msk           (0xffffffffUL) /*!< CRDA (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CRTB  ========================================================== */
+ #define R_USBF_CHa_CRTB_CRTB_Pos           (0UL)          /*!< CRTB (Bit 0)                                          */
+ #define R_USBF_CHa_CRTB_CRTB_Msk           (0xffffffffUL) /*!< CRTB (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  CHSTAT  ========================================================= */
+ #define R_USBF_CHa_CHSTAT_EN_Pos           (0UL)          /*!< EN (Bit 0)                                            */
+ #define R_USBF_CHa_CHSTAT_EN_Msk           (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_RQST_Pos         (1UL)          /*!< RQST (Bit 1)                                          */
+ #define R_USBF_CHa_CHSTAT_RQST_Msk         (0x2UL)        /*!< RQST (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHSTAT_TACT_Pos         (2UL)          /*!< TACT (Bit 2)                                          */
+ #define R_USBF_CHa_CHSTAT_TACT_Msk         (0x4UL)        /*!< TACT (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHSTAT_SUS_Pos          (3UL)          /*!< SUS (Bit 3)                                           */
+ #define R_USBF_CHa_CHSTAT_SUS_Msk          (0x8UL)        /*!< SUS (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHSTAT_ER_Pos           (4UL)          /*!< ER (Bit 4)                                            */
+ #define R_USBF_CHa_CHSTAT_ER_Msk           (0x10UL)       /*!< ER (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_END_Pos          (5UL)          /*!< END (Bit 5)                                           */
+ #define R_USBF_CHa_CHSTAT_END_Msk          (0x20UL)       /*!< END (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHSTAT_TC_Pos           (6UL)          /*!< TC (Bit 6)                                            */
+ #define R_USBF_CHa_CHSTAT_TC_Msk           (0x40UL)       /*!< TC (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_SR_Pos           (7UL)          /*!< SR (Bit 7)                                            */
+ #define R_USBF_CHa_CHSTAT_SR_Msk           (0x80UL)       /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_DL_Pos           (8UL)          /*!< DL (Bit 8)                                            */
+ #define R_USBF_CHa_CHSTAT_DL_Msk           (0x100UL)      /*!< DL (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_DW_Pos           (9UL)          /*!< DW (Bit 9)                                            */
+ #define R_USBF_CHa_CHSTAT_DW_Msk           (0x200UL)      /*!< DW (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHSTAT_DER_Pos          (10UL)         /*!< DER (Bit 10)                                          */
+ #define R_USBF_CHa_CHSTAT_DER_Msk          (0x400UL)      /*!< DER (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHSTAT_MODE_Pos         (11UL)         /*!< MODE (Bit 11)                                         */
+ #define R_USBF_CHa_CHSTAT_MODE_Msk         (0x800UL)      /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHSTAT_INTM_Pos         (16UL)         /*!< INTM (Bit 16)                                         */
+ #define R_USBF_CHa_CHSTAT_INTM_Msk         (0x10000UL)    /*!< INTM (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHSTAT_DMARQM_Pos       (17UL)         /*!< DMARQM (Bit 17)                                       */
+ #define R_USBF_CHa_CHSTAT_DMARQM_Msk       (0x20000UL)    /*!< DMARQM (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHSTAT_SWPRQ_Pos        (18UL)         /*!< SWPRQ (Bit 18)                                        */
+ #define R_USBF_CHa_CHSTAT_SWPRQ_Msk        (0x40000UL)    /*!< SWPRQ (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHSTAT_DNUM_Pos         (24UL)         /*!< DNUM (Bit 24)                                         */
+ #define R_USBF_CHa_CHSTAT_DNUM_Msk         (0xff000000UL) /*!< DNUM (Bitfield-Mask: 0xff)                            */
+/* ========================================================  CHCTRL  ========================================================= */
+ #define R_USBF_CHa_CHCTRL_SETEN_Pos        (0UL)          /*!< SETEN (Bit 0)                                         */
+ #define R_USBF_CHa_CHCTRL_SETEN_Msk        (0x1UL)        /*!< SETEN (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_CLREN_Pos        (1UL)          /*!< CLREN (Bit 1)                                         */
+ #define R_USBF_CHa_CHCTRL_CLREN_Msk        (0x2UL)        /*!< CLREN (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_STG_Pos          (2UL)          /*!< STG (Bit 2)                                           */
+ #define R_USBF_CHa_CHCTRL_STG_Msk          (0x4UL)        /*!< STG (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCTRL_SWRST_Pos        (3UL)          /*!< SWRST (Bit 3)                                         */
+ #define R_USBF_CHa_CHCTRL_SWRST_Msk        (0x8UL)        /*!< SWRST (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_CLRRQ_Pos        (4UL)          /*!< CLRRQ (Bit 4)                                         */
+ #define R_USBF_CHa_CHCTRL_CLRRQ_Msk        (0x10UL)       /*!< CLRRQ (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_CLREND_Pos       (5UL)          /*!< CLREND (Bit 5)                                        */
+ #define R_USBF_CHa_CHCTRL_CLREND_Msk       (0x20UL)       /*!< CLREND (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_CLRTC_Pos        (6UL)          /*!< CLRTC (Bit 6)                                         */
+ #define R_USBF_CHa_CHCTRL_CLRTC_Msk        (0x40UL)       /*!< CLRTC (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCTRL_CLRDER_Pos       (7UL)          /*!< CLRDER (Bit 7)                                        */
+ #define R_USBF_CHa_CHCTRL_CLRDER_Msk       (0x80UL)       /*!< CLRDER (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_SETSUS_Pos       (8UL)          /*!< SETSUS (Bit 8)                                        */
+ #define R_USBF_CHa_CHCTRL_SETSUS_Msk       (0x100UL)      /*!< SETSUS (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_CLRSUS_Pos       (9UL)          /*!< CLRSUS (Bit 9)                                        */
+ #define R_USBF_CHa_CHCTRL_CLRSUS_Msk       (0x200UL)      /*!< CLRSUS (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_SETREN_Pos       (12UL)         /*!< SETREN (Bit 12)                                       */
+ #define R_USBF_CHa_CHCTRL_SETREN_Msk       (0x1000UL)     /*!< SETREN (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Pos    (14UL)         /*!< SETSSWPRQ (Bit 14)                                    */
+ #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Msk    (0x4000UL)     /*!< SETSSWPRQ (Bitfield-Mask: 0x01)                       */
+ #define R_USBF_CHa_CHCTRL_SETINTM_Pos      (16UL)         /*!< SETINTM (Bit 16)                                      */
+ #define R_USBF_CHa_CHCTRL_SETINTM_Msk      (0x10000UL)    /*!< SETINTM (Bitfield-Mask: 0x01)                         */
+ #define R_USBF_CHa_CHCTRL_CLRINTM_Pos      (17UL)         /*!< CLRINTM (Bit 17)                                      */
+ #define R_USBF_CHa_CHCTRL_CLRINTM_Msk      (0x20000UL)    /*!< CLRINTM (Bitfield-Mask: 0x01)                         */
+ #define R_USBF_CHa_CHCTRL_SETDMARQM_Pos    (18UL)         /*!< SETDMARQM (Bit 18)                                    */
+ #define R_USBF_CHa_CHCTRL_SETDMARQM_Msk    (0x40000UL)    /*!< SETDMARQM (Bitfield-Mask: 0x01)                       */
+ #define R_USBF_CHa_CHCTRL_CLRDMARQM_Pos    (19UL)         /*!< CLRDMARQM (Bit 19)                                    */
+ #define R_USBF_CHa_CHCTRL_CLRDMARQM_Msk    (0x80000UL)    /*!< CLRDMARQM (Bitfield-Mask: 0x01)                       */
+/* =========================================================  CHCFG  ========================================================= */
+ #define R_USBF_CHa_CHCFG_SEL_Pos           (0UL)          /*!< SEL (Bit 0)                                           */
+ #define R_USBF_CHa_CHCFG_SEL_Msk           (0x1UL)        /*!< SEL (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_REQD_Pos          (3UL)          /*!< REQD (Bit 3)                                          */
+ #define R_USBF_CHa_CHCFG_REQD_Msk          (0x8UL)        /*!< REQD (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_LOEN_Pos          (4UL)          /*!< LOEN (Bit 4)                                          */
+ #define R_USBF_CHa_CHCFG_LOEN_Msk          (0x10UL)       /*!< LOEN (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_HIEN_Pos          (5UL)          /*!< HIEN (Bit 5)                                          */
+ #define R_USBF_CHa_CHCFG_HIEN_Msk          (0x20UL)       /*!< HIEN (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_LVL_Pos           (6UL)          /*!< LVL (Bit 6)                                           */
+ #define R_USBF_CHa_CHCFG_LVL_Msk           (0x40UL)       /*!< LVL (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_AM_Pos            (8UL)          /*!< AM (Bit 8)                                            */
+ #define R_USBF_CHa_CHCFG_AM_Msk            (0x700UL)      /*!< AM (Bitfield-Mask: 0x07)                              */
+ #define R_USBF_CHa_CHCFG_DRRP_Pos          (11UL)         /*!< DRRP (Bit 11)                                         */
+ #define R_USBF_CHa_CHCFG_DRRP_Msk          (0x800UL)      /*!< DRRP (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_SDS_Pos           (12UL)         /*!< SDS (Bit 12)                                          */
+ #define R_USBF_CHa_CHCFG_SDS_Msk           (0xf000UL)     /*!< SDS (Bitfield-Mask: 0x0f)                             */
+ #define R_USBF_CHa_CHCFG_DDS_Pos           (16UL)         /*!< DDS (Bit 16)                                          */
+ #define R_USBF_CHa_CHCFG_DDS_Msk           (0xf0000UL)    /*!< DDS (Bitfield-Mask: 0x0f)                             */
+ #define R_USBF_CHa_CHCFG_SAD_Pos           (20UL)         /*!< SAD (Bit 20)                                          */
+ #define R_USBF_CHa_CHCFG_SAD_Msk           (0x100000UL)   /*!< SAD (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_DAD_Pos           (21UL)         /*!< DAD (Bit 21)                                          */
+ #define R_USBF_CHa_CHCFG_DAD_Msk           (0x200000UL)   /*!< DAD (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_TM_Pos            (22UL)         /*!< TM (Bit 22)                                           */
+ #define R_USBF_CHa_CHCFG_TM_Msk            (0x400000UL)   /*!< TM (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_CHa_CHCFG_WONLY_Pos         (23UL)         /*!< WONLY (Bit 23)                                        */
+ #define R_USBF_CHa_CHCFG_WONLY_Msk         (0x800000UL)   /*!< WONLY (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_CHa_CHCFG_DEM_Pos           (24UL)         /*!< DEM (Bit 24)                                          */
+ #define R_USBF_CHa_CHCFG_DEM_Msk           (0x1000000UL)  /*!< DEM (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_DIM_Pos           (26UL)         /*!< DIM (Bit 26)                                          */
+ #define R_USBF_CHa_CHCFG_DIM_Msk           (0x4000000UL)  /*!< DIM (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_SBE_Pos           (27UL)         /*!< SBE (Bit 27)                                          */
+ #define R_USBF_CHa_CHCFG_SBE_Msk           (0x8000000UL)  /*!< SBE (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_RSEL_Pos          (28UL)         /*!< RSEL (Bit 28)                                         */
+ #define R_USBF_CHa_CHCFG_RSEL_Msk          (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CHa_CHCFG_RSW_Pos           (29UL)         /*!< RSW (Bit 29)                                          */
+ #define R_USBF_CHa_CHCFG_RSW_Msk           (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_REN_Pos           (30UL)         /*!< REN (Bit 30)                                          */
+ #define R_USBF_CHa_CHCFG_REN_Msk           (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CHa_CHCFG_DMS_Pos           (31UL)         /*!< DMS (Bit 31)                                          */
+ #define R_USBF_CHa_CHCFG_DMS_Msk           (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CHITVL  ========================================================= */
+ #define R_USBF_CHa_CHITVL_ITVL_Pos         (0UL)          /*!< ITVL (Bit 0)                                          */
+ #define R_USBF_CHa_CHITVL_ITVL_Msk         (0xffffUL)     /*!< ITVL (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  CHEXT  ========================================================= */
+ #define R_USBF_CHa_CHEXT_SPR_Pos           (0UL)          /*!< SPR (Bit 0)                                           */
+ #define R_USBF_CHa_CHEXT_SPR_Msk           (0xfUL)        /*!< SPR (Bitfield-Mask: 0x0f)                             */
+ #define R_USBF_CHa_CHEXT_DPR_Pos           (8UL)          /*!< DPR (Bit 8)                                           */
+ #define R_USBF_CHa_CHEXT_DPR_Msk           (0xf00UL)      /*!< DPR (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  NXLA  ========================================================== */
+ #define R_USBF_CHa_NXLA_NXLA_Pos           (0UL)          /*!< NXLA (Bit 0)                                          */
+ #define R_USBF_CHa_NXLA_NXLA_Msk           (0xffffffffUL) /*!< NXLA (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CRLA  ========================================================== */
+ #define R_USBF_CHa_CRLA_CRLA_Pos           (0UL)          /*!< CRLA (Bit 0)                                          */
+ #define R_USBF_CHa_CRLA_CRLA_Msk           (0xffffffffUL) /*!< CRLA (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                            CHb                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SCNT  ========================================================== */
+ #define R_USBF_CHb_SCNT_SCNT_Pos    (0UL)          /*!< SCNT (Bit 0)                                          */
+ #define R_USBF_CHb_SCNT_SCNT_Msk    (0xffffffffUL) /*!< SCNT (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  SSKP  ========================================================== */
+ #define R_USBF_CHb_SSKP_SSKP_Pos    (0UL)          /*!< SSKP (Bit 0)                                          */
+ #define R_USBF_CHb_SSKP_SSKP_Msk    (0xffffffffUL) /*!< SSKP (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  DCNT  ========================================================== */
+ #define R_USBF_CHb_DCNT_DCNT_Pos    (0UL)          /*!< DCNT (Bit 0)                                          */
+ #define R_USBF_CHb_DCNT_DCNT_Msk    (0xffffffffUL) /*!< DCNT (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  DSKP  ========================================================== */
+ #define R_USBF_CHb_DSKP_DSKP_Pos    (0UL)          /*!< DSKP (Bit 0)                                          */
+ #define R_USBF_CHb_DSKP_DSKP_Msk    (0xffffffffUL) /*!< DSKP (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                        PCI_REQDATA                                        ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  EP  =========================================================== */
+/* ==========================================================  RC  =========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                       PCI_RC_MSIRCV                                       ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  E  =========================================================== */
+ #define R_PCIE0_PCI_RC_MSIRCV_E_E_Pos    (0UL)   /*!< E (Bit 0)                                             */
+ #define R_PCIE0_PCI_RC_MSIRCV_E_E_Msk    (0x1UL) /*!< E (Bitfield-Mask: 0x01)                               */
+/* ========================================================  MSGDATA  ======================================================== */
+/* ==========================================================  MSK  ========================================================== */
+/* =========================================================  STAT  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                       PCI_PHY_XCFGD                                       ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  XCFGD  ========================================================= */
+ #define R_PCIE_PHY_PCI_PHY_XCFGD_XCFGD_XCFGD_Pos    (0UL)          /*!< XCFGD (Bit 0)                                         */
+ #define R_PCIE_PHY_PCI_PHY_XCFGD_XCFGD_XCFGD_Msk    (0xffffffffUL) /*!< XCFGD (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                     PCI_PHY_XCFGA_CMN                                     ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  XCFGA_CMN  ======================================================= */
+ #define R_PCIE_PHY_PCI_PHY_XCFGA_CMN_XCFGA_CMN_XCFGA_CMN_Pos    (0UL)          /*!< XCFGA_CMN (Bit 0)                                     */
+ #define R_PCIE_PHY_PCI_PHY_XCFGA_CMN_XCFGA_CMN_XCFGA_CMN_Msk    (0xffffffffUL) /*!< XCFGA_CMN (Bitfield-Mask: 0xffffffff)         */
+
+/* =========================================================================================================================== */
+/* ================                                     PCI_PHY_XCFGA_L0                                      ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  XCFGA_LN0  ======================================================= */
+ #define R_PCIE_PHY_PCI_PHY_XCFGA_L0_XCFGA_LN0_XCFGA_LN0_Pos    (0UL)          /*!< XCFGA_LN0 (Bit 0)                                     */
+ #define R_PCIE_PHY_PCI_PHY_XCFGA_L0_XCFGA_LN0_XCFGA_LN0_Msk    (0xffffffffUL) /*!< XCFGA_LN0 (Bitfield-Mask: 0xffffffff)          */
+
+/* =========================================================================================================================== */
+/* ================                                     PCI_PHY_XCFGA_L1                                      ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  XCFGA_LN1  ======================================================= */
+ #define R_PCIE_PHY_PCI_PHY_XCFGA_L1_XCFGA_LN1_XCFGA_LN1_Pos    (0UL)          /*!< XCFGA_LN1 (Bit 0)                                     */
+ #define R_PCIE_PHY_PCI_PHY_XCFGA_L1_XCFGA_LN1_XCFGA_LN1_Msk    (0xffffffffUL) /*!< XCFGA_LN1 (Bitfield-Mask: 0xffffffff)          */
+
+/** @} */ /* End of group PosMask_clusters */
+
+/* =========================================================================================================================== */
+/* ================                                Pos/Mask Peripheral Section                                ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT00_0                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  GTWP  ========================================================== */
+ #define R_GPT09_0_GTWP_WP_Pos              (0UL)          /*!< WP (Bit 0)                                            */
+ #define R_GPT09_0_GTWP_WP_Msk              (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
+ #define R_GPT09_0_GTWP_STRWP_Pos           (1UL)          /*!< STRWP (Bit 1)                                         */
+ #define R_GPT09_0_GTWP_STRWP_Msk           (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTWP_STPWP_Pos           (2UL)          /*!< STPWP (Bit 2)                                         */
+ #define R_GPT09_0_GTWP_STPWP_Msk           (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTWP_CLRWP_Pos           (3UL)          /*!< CLRWP (Bit 3)                                         */
+ #define R_GPT09_0_GTWP_CLRWP_Msk           (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTWP_CMNWP_Pos           (4UL)          /*!< CMNWP (Bit 4)                                         */
+ #define R_GPT09_0_GTWP_CMNWP_Msk           (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTWP_PRKEY_Pos           (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_GPT09_0_GTWP_PRKEY_Msk           (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+/* =========================================================  GTSTR  ========================================================= */
+ #define R_GPT09_0_GTSTR_CSTRT0_Pos         (0UL)          /*!< CSTRT0 (Bit 0)                                        */
+ #define R_GPT09_0_GTSTR_CSTRT0_Msk         (0x1UL)        /*!< CSTRT0 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTR_CSTRT1_Pos         (1UL)          /*!< CSTRT1 (Bit 1)                                        */
+ #define R_GPT09_0_GTSTR_CSTRT1_Msk         (0x2UL)        /*!< CSTRT1 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTR_CSTRT2_Pos         (2UL)          /*!< CSTRT2 (Bit 2)                                        */
+ #define R_GPT09_0_GTSTR_CSTRT2_Msk         (0x4UL)        /*!< CSTRT2 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTR_CSTRT3_Pos         (3UL)          /*!< CSTRT3 (Bit 3)                                        */
+ #define R_GPT09_0_GTSTR_CSTRT3_Msk         (0x8UL)        /*!< CSTRT3 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTR_CSTRT4_Pos         (4UL)          /*!< CSTRT4 (Bit 4)                                        */
+ #define R_GPT09_0_GTSTR_CSTRT4_Msk         (0x10UL)       /*!< CSTRT4 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTR_CSTRT5_Pos         (5UL)          /*!< CSTRT5 (Bit 5)                                        */
+ #define R_GPT09_0_GTSTR_CSTRT5_Msk         (0x20UL)       /*!< CSTRT5 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTR_CSTRT6_Pos         (6UL)          /*!< CSTRT6 (Bit 6)                                        */
+ #define R_GPT09_0_GTSTR_CSTRT6_Msk         (0x40UL)       /*!< CSTRT6 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTSTP  ========================================================= */
+ #define R_GPT09_0_GTSTP_CSTOP0_Pos         (0UL)          /*!< CSTOP0 (Bit 0)                                        */
+ #define R_GPT09_0_GTSTP_CSTOP0_Msk         (0x1UL)        /*!< CSTOP0 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTP_CSTOP1_Pos         (1UL)          /*!< CSTOP1 (Bit 1)                                        */
+ #define R_GPT09_0_GTSTP_CSTOP1_Msk         (0x2UL)        /*!< CSTOP1 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTP_CSTOP2_Pos         (2UL)          /*!< CSTOP2 (Bit 2)                                        */
+ #define R_GPT09_0_GTSTP_CSTOP2_Msk         (0x4UL)        /*!< CSTOP2 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTP_CSTOP3_Pos         (3UL)          /*!< CSTOP3 (Bit 3)                                        */
+ #define R_GPT09_0_GTSTP_CSTOP3_Msk         (0x8UL)        /*!< CSTOP3 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTP_CSTOP4_Pos         (4UL)          /*!< CSTOP4 (Bit 4)                                        */
+ #define R_GPT09_0_GTSTP_CSTOP4_Msk         (0x10UL)       /*!< CSTOP4 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTP_CSTOP5_Pos         (5UL)          /*!< CSTOP5 (Bit 5)                                        */
+ #define R_GPT09_0_GTSTP_CSTOP5_Msk         (0x20UL)       /*!< CSTOP5 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSTP_CSTOP6_Pos         (6UL)          /*!< CSTOP6 (Bit 6)                                        */
+ #define R_GPT09_0_GTSTP_CSTOP6_Msk         (0x40UL)       /*!< CSTOP6 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTCLR  ========================================================= */
+ #define R_GPT09_0_GTCLR_CCLR0_Pos          (0UL)          /*!< CCLR0 (Bit 0)                                         */
+ #define R_GPT09_0_GTCLR_CCLR0_Msk          (0x1UL)        /*!< CCLR0 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTCLR_CCLR1_Pos          (1UL)          /*!< CCLR1 (Bit 1)                                         */
+ #define R_GPT09_0_GTCLR_CCLR1_Msk          (0x2UL)        /*!< CCLR1 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTCLR_CCLR2_Pos          (2UL)          /*!< CCLR2 (Bit 2)                                         */
+ #define R_GPT09_0_GTCLR_CCLR2_Msk          (0x4UL)        /*!< CCLR2 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTCLR_CCLR3_Pos          (3UL)          /*!< CCLR3 (Bit 3)                                         */
+ #define R_GPT09_0_GTCLR_CCLR3_Msk          (0x8UL)        /*!< CCLR3 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTCLR_CCLR4_Pos          (4UL)          /*!< CCLR4 (Bit 4)                                         */
+ #define R_GPT09_0_GTCLR_CCLR4_Msk          (0x10UL)       /*!< CCLR4 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTCLR_CCLR5_Pos          (5UL)          /*!< CCLR5 (Bit 5)                                         */
+ #define R_GPT09_0_GTCLR_CCLR5_Msk          (0x20UL)       /*!< CCLR5 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTCLR_CCLR6_Pos          (6UL)          /*!< CCLR6 (Bit 6)                                         */
+ #define R_GPT09_0_GTCLR_CCLR6_Msk          (0x40UL)       /*!< CCLR6 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTSSR  ========================================================= */
+ #define R_GPT09_0_GTSSR_SSGTRGAFR_Pos      (0UL)          /*!< SSGTRGAFR (Bit 0)                                     */
+ #define R_GPT09_0_GTSSR_SSGTRGAFR_Msk      (0x3UL)        /*!< SSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTSSR_SSGTRGBFR_Pos      (2UL)          /*!< SSGTRGBFR (Bit 2)                                     */
+ #define R_GPT09_0_GTSSR_SSGTRGBFR_Msk      (0xcUL)        /*!< SSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTSSR_SSGTRGCFR_Pos      (4UL)          /*!< SSGTRGCFR (Bit 4)                                     */
+ #define R_GPT09_0_GTSSR_SSGTRGCFR_Msk      (0x30UL)       /*!< SSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTSSR_SSGTRGDFR_Pos      (6UL)          /*!< SSGTRGDFR (Bit 6)                                     */
+ #define R_GPT09_0_GTSSR_SSGTRGDFR_Msk      (0xc0UL)       /*!< SSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTSSR_SSCARBHL_Pos       (8UL)          /*!< SSCARBHL (Bit 8)                                      */
+ #define R_GPT09_0_GTSSR_SSCARBHL_Msk       (0x300UL)      /*!< SSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTSSR_SSCAFBHL_Pos       (10UL)         /*!< SSCAFBHL (Bit 10)                                     */
+ #define R_GPT09_0_GTSSR_SSCAFBHL_Msk       (0xc00UL)      /*!< SSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTSSR_SSCBRAHL_Pos       (12UL)         /*!< SSCBRAHL (Bit 12)                                     */
+ #define R_GPT09_0_GTSSR_SSCBRAHL_Msk       (0x3000UL)     /*!< SSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTSSR_SSCBFAHL_Pos       (14UL)         /*!< SSCBFAHL (Bit 14)                                     */
+ #define R_GPT09_0_GTSSR_SSCBFAHL_Msk       (0xc000UL)     /*!< SSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTSSR_SSELCA_Pos         (16UL)         /*!< SSELCA (Bit 16)                                       */
+ #define R_GPT09_0_GTSSR_SSELCA_Msk         (0x10000UL)    /*!< SSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSSR_SSELCB_Pos         (17UL)         /*!< SSELCB (Bit 17)                                       */
+ #define R_GPT09_0_GTSSR_SSELCB_Msk         (0x20000UL)    /*!< SSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSSR_SSELCC_Pos         (18UL)         /*!< SSELCC (Bit 18)                                       */
+ #define R_GPT09_0_GTSSR_SSELCC_Msk         (0x40000UL)    /*!< SSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSSR_SSELCD_Pos         (19UL)         /*!< SSELCD (Bit 19)                                       */
+ #define R_GPT09_0_GTSSR_SSELCD_Msk         (0x80000UL)    /*!< SSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSSR_SSELCE_Pos         (20UL)         /*!< SSELCE (Bit 20)                                       */
+ #define R_GPT09_0_GTSSR_SSELCE_Msk         (0x100000UL)   /*!< SSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSSR_SSELCF_Pos         (21UL)         /*!< SSELCF (Bit 21)                                       */
+ #define R_GPT09_0_GTSSR_SSELCF_Msk         (0x200000UL)   /*!< SSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSSR_SSELCG_Pos         (22UL)         /*!< SSELCG (Bit 22)                                       */
+ #define R_GPT09_0_GTSSR_SSELCG_Msk         (0x400000UL)   /*!< SSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSSR_SSELCH_Pos         (23UL)         /*!< SSELCH (Bit 23)                                       */
+ #define R_GPT09_0_GTSSR_SSELCH_Msk         (0x800000UL)   /*!< SSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSSR_CSTRT_Pos          (31UL)         /*!< CSTRT (Bit 31)                                        */
+ #define R_GPT09_0_GTSSR_CSTRT_Msk          (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTPSR  ========================================================= */
+ #define R_GPT09_0_GTPSR_PSGTRGAFR_Pos      (0UL)          /*!< PSGTRGAFR (Bit 0)                                     */
+ #define R_GPT09_0_GTPSR_PSGTRGAFR_Msk      (0x3UL)        /*!< PSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTPSR_PSGTRGBFR_Pos      (2UL)          /*!< PSGTRGBFR (Bit 2)                                     */
+ #define R_GPT09_0_GTPSR_PSGTRGBFR_Msk      (0xcUL)        /*!< PSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTPSR_PSGTRGCFR_Pos      (4UL)          /*!< PSGTRGCFR (Bit 4)                                     */
+ #define R_GPT09_0_GTPSR_PSGTRGCFR_Msk      (0x30UL)       /*!< PSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTPSR_PSGTRGDFR_Pos      (6UL)          /*!< PSGTRGDFR (Bit 6)                                     */
+ #define R_GPT09_0_GTPSR_PSGTRGDFR_Msk      (0xc0UL)       /*!< PSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTPSR_PSCARBHL_Pos       (8UL)          /*!< PSCARBHL (Bit 8)                                      */
+ #define R_GPT09_0_GTPSR_PSCARBHL_Msk       (0x300UL)      /*!< PSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTPSR_PSCAFBHL_Pos       (10UL)         /*!< PSCAFBHL (Bit 10)                                     */
+ #define R_GPT09_0_GTPSR_PSCAFBHL_Msk       (0xc00UL)      /*!< PSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTPSR_PSCBRAHL_Pos       (12UL)         /*!< PSCBRAHL (Bit 12)                                     */
+ #define R_GPT09_0_GTPSR_PSCBRAHL_Msk       (0x3000UL)     /*!< PSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTPSR_PSCBFAHL_Pos       (14UL)         /*!< PSCBFAHL (Bit 14)                                     */
+ #define R_GPT09_0_GTPSR_PSCBFAHL_Msk       (0xc000UL)     /*!< PSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTPSR_PSELCA_Pos         (16UL)         /*!< PSELCA (Bit 16)                                       */
+ #define R_GPT09_0_GTPSR_PSELCA_Msk         (0x10000UL)    /*!< PSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTPSR_PSELCB_Pos         (17UL)         /*!< PSELCB (Bit 17)                                       */
+ #define R_GPT09_0_GTPSR_PSELCB_Msk         (0x20000UL)    /*!< PSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTPSR_PSELCC_Pos         (18UL)         /*!< PSELCC (Bit 18)                                       */
+ #define R_GPT09_0_GTPSR_PSELCC_Msk         (0x40000UL)    /*!< PSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTPSR_PSELCD_Pos         (19UL)         /*!< PSELCD (Bit 19)                                       */
+ #define R_GPT09_0_GTPSR_PSELCD_Msk         (0x80000UL)    /*!< PSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTPSR_PSELCE_Pos         (20UL)         /*!< PSELCE (Bit 20)                                       */
+ #define R_GPT09_0_GTPSR_PSELCE_Msk         (0x100000UL)   /*!< PSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTPSR_PSELCF_Pos         (21UL)         /*!< PSELCF (Bit 21)                                       */
+ #define R_GPT09_0_GTPSR_PSELCF_Msk         (0x200000UL)   /*!< PSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTPSR_PSELCG_Pos         (22UL)         /*!< PSELCG (Bit 22)                                       */
+ #define R_GPT09_0_GTPSR_PSELCG_Msk         (0x400000UL)   /*!< PSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTPSR_PSELCH_Pos         (23UL)         /*!< PSELCH (Bit 23)                                       */
+ #define R_GPT09_0_GTPSR_PSELCH_Msk         (0x800000UL)   /*!< PSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTPSR_CSTOP_Pos          (31UL)         /*!< CSTOP (Bit 31)                                        */
+ #define R_GPT09_0_GTPSR_CSTOP_Msk          (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCSR  ========================================================= */
+ #define R_GPT09_0_GTCSR_CSGTRGAFR_Pos      (0UL)          /*!< CSGTRGAFR (Bit 0)                                     */
+ #define R_GPT09_0_GTCSR_CSGTRGAFR_Msk      (0x3UL)        /*!< CSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTCSR_CSGTRGBFR_Pos      (2UL)          /*!< CSGTRGBFR (Bit 2)                                     */
+ #define R_GPT09_0_GTCSR_CSGTRGBFR_Msk      (0xcUL)        /*!< CSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTCSR_CSGTRGCFR_Pos      (4UL)          /*!< CSGTRGCFR (Bit 4)                                     */
+ #define R_GPT09_0_GTCSR_CSGTRGCFR_Msk      (0x30UL)       /*!< CSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTCSR_CSGTRGDFR_Pos      (6UL)          /*!< CSGTRGDFR (Bit 6)                                     */
+ #define R_GPT09_0_GTCSR_CSGTRGDFR_Msk      (0xc0UL)       /*!< CSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTCSR_CSCARBHL_Pos       (8UL)          /*!< CSCARBHL (Bit 8)                                      */
+ #define R_GPT09_0_GTCSR_CSCARBHL_Msk       (0x300UL)      /*!< CSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTCSR_CSCAFBHL_Pos       (10UL)         /*!< CSCAFBHL (Bit 10)                                     */
+ #define R_GPT09_0_GTCSR_CSCAFBHL_Msk       (0xc00UL)      /*!< CSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTCSR_CSCBRAHL_Pos       (12UL)         /*!< CSCBRAHL (Bit 12)                                     */
+ #define R_GPT09_0_GTCSR_CSCBRAHL_Msk       (0x3000UL)     /*!< CSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTCSR_CSCBFAHL_Pos       (14UL)         /*!< CSCBFAHL (Bit 14)                                     */
+ #define R_GPT09_0_GTCSR_CSCBFAHL_Msk       (0xc000UL)     /*!< CSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTCSR_CSELCA_Pos         (16UL)         /*!< CSELCA (Bit 16)                                       */
+ #define R_GPT09_0_GTCSR_CSELCA_Msk         (0x10000UL)    /*!< CSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTCSR_CSELCB_Pos         (17UL)         /*!< CSELCB (Bit 17)                                       */
+ #define R_GPT09_0_GTCSR_CSELCB_Msk         (0x20000UL)    /*!< CSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTCSR_CSELCC_Pos         (18UL)         /*!< CSELCC (Bit 18)                                       */
+ #define R_GPT09_0_GTCSR_CSELCC_Msk         (0x40000UL)    /*!< CSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTCSR_CSELCD_Pos         (19UL)         /*!< CSELCD (Bit 19)                                       */
+ #define R_GPT09_0_GTCSR_CSELCD_Msk         (0x80000UL)    /*!< CSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTCSR_CSELCE_Pos         (20UL)         /*!< CSELCE (Bit 20)                                       */
+ #define R_GPT09_0_GTCSR_CSELCE_Msk         (0x100000UL)   /*!< CSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTCSR_CSELCF_Pos         (21UL)         /*!< CSELCF (Bit 21)                                       */
+ #define R_GPT09_0_GTCSR_CSELCF_Msk         (0x200000UL)   /*!< CSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTCSR_CSELCG_Pos         (22UL)         /*!< CSELCG (Bit 22)                                       */
+ #define R_GPT09_0_GTCSR_CSELCG_Msk         (0x400000UL)   /*!< CSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTCSR_CSELCH_Pos         (23UL)         /*!< CSELCH (Bit 23)                                       */
+ #define R_GPT09_0_GTCSR_CSELCH_Msk         (0x800000UL)   /*!< CSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTCSR_CCLR_Pos           (31UL)         /*!< CCLR (Bit 31)                                         */
+ #define R_GPT09_0_GTCSR_CCLR_Msk           (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTUPSR  ========================================================= */
+ #define R_GPT09_0_GTUPSR_USGTRGAFR_Pos     (0UL)          /*!< USGTRGAFR (Bit 0)                                     */
+ #define R_GPT09_0_GTUPSR_USGTRGAFR_Msk     (0x3UL)        /*!< USGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTUPSR_USGTRGBFR_Pos     (2UL)          /*!< USGTRGBFR (Bit 2)                                     */
+ #define R_GPT09_0_GTUPSR_USGTRGBFR_Msk     (0xcUL)        /*!< USGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTUPSR_USGTRGCFR_Pos     (4UL)          /*!< USGTRGCFR (Bit 4)                                     */
+ #define R_GPT09_0_GTUPSR_USGTRGCFR_Msk     (0x30UL)       /*!< USGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTUPSR_USGTRGDFR_Pos     (6UL)          /*!< USGTRGDFR (Bit 6)                                     */
+ #define R_GPT09_0_GTUPSR_USGTRGDFR_Msk     (0xc0UL)       /*!< USGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTUPSR_USCARBHL_Pos      (8UL)          /*!< USCARBHL (Bit 8)                                      */
+ #define R_GPT09_0_GTUPSR_USCARBHL_Msk      (0x300UL)      /*!< USCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTUPSR_USCAFBHL_Pos      (10UL)         /*!< USCAFBHL (Bit 10)                                     */
+ #define R_GPT09_0_GTUPSR_USCAFBHL_Msk      (0xc00UL)      /*!< USCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTUPSR_USCBRAHL_Pos      (12UL)         /*!< USCBRAHL (Bit 12)                                     */
+ #define R_GPT09_0_GTUPSR_USCBRAHL_Msk      (0x3000UL)     /*!< USCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTUPSR_USCBFAHL_Pos      (14UL)         /*!< USCBFAHL (Bit 14)                                     */
+ #define R_GPT09_0_GTUPSR_USCBFAHL_Msk      (0xc000UL)     /*!< USCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTUPSR_USELCA_Pos        (16UL)         /*!< USELCA (Bit 16)                                       */
+ #define R_GPT09_0_GTUPSR_USELCA_Msk        (0x10000UL)    /*!< USELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUPSR_USELCB_Pos        (17UL)         /*!< USELCB (Bit 17)                                       */
+ #define R_GPT09_0_GTUPSR_USELCB_Msk        (0x20000UL)    /*!< USELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUPSR_USELCC_Pos        (18UL)         /*!< USELCC (Bit 18)                                       */
+ #define R_GPT09_0_GTUPSR_USELCC_Msk        (0x40000UL)    /*!< USELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUPSR_USELCD_Pos        (19UL)         /*!< USELCD (Bit 19)                                       */
+ #define R_GPT09_0_GTUPSR_USELCD_Msk        (0x80000UL)    /*!< USELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUPSR_USELCE_Pos        (20UL)         /*!< USELCE (Bit 20)                                       */
+ #define R_GPT09_0_GTUPSR_USELCE_Msk        (0x100000UL)   /*!< USELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUPSR_USELCF_Pos        (21UL)         /*!< USELCF (Bit 21)                                       */
+ #define R_GPT09_0_GTUPSR_USELCF_Msk        (0x200000UL)   /*!< USELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUPSR_USELCG_Pos        (22UL)         /*!< USELCG (Bit 22)                                       */
+ #define R_GPT09_0_GTUPSR_USELCG_Msk        (0x400000UL)   /*!< USELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUPSR_USELCH_Pos        (23UL)         /*!< USELCH (Bit 23)                                       */
+ #define R_GPT09_0_GTUPSR_USELCH_Msk        (0x800000UL)   /*!< USELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTDNSR  ========================================================= */
+ #define R_GPT09_0_GTDNSR_DSGTRGAFR_Pos     (0UL)          /*!< DSGTRGAFR (Bit 0)                                     */
+ #define R_GPT09_0_GTDNSR_DSGTRGAFR_Msk     (0x3UL)        /*!< DSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTDNSR_DSGTRGBFR_Pos     (2UL)          /*!< DSGTRGBFR (Bit 2)                                     */
+ #define R_GPT09_0_GTDNSR_DSGTRGBFR_Msk     (0xcUL)        /*!< DSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTDNSR_DSGTRGCFR_Pos     (4UL)          /*!< DSGTRGCFR (Bit 4)                                     */
+ #define R_GPT09_0_GTDNSR_DSGTRGCFR_Msk     (0x30UL)       /*!< DSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTDNSR_DSGTRGDFR_Pos     (6UL)          /*!< DSGTRGDFR (Bit 6)                                     */
+ #define R_GPT09_0_GTDNSR_DSGTRGDFR_Msk     (0xc0UL)       /*!< DSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTDNSR_DSCARBHL_Pos      (8UL)          /*!< DSCARBHL (Bit 8)                                      */
+ #define R_GPT09_0_GTDNSR_DSCARBHL_Msk      (0x300UL)      /*!< DSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTDNSR_DSCAFBHL_Pos      (10UL)         /*!< DSCAFBHL (Bit 10)                                     */
+ #define R_GPT09_0_GTDNSR_DSCAFBHL_Msk      (0xc00UL)      /*!< DSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTDNSR_DSCBRAHL_Pos      (12UL)         /*!< DSCBRAHL (Bit 12)                                     */
+ #define R_GPT09_0_GTDNSR_DSCBRAHL_Msk      (0x3000UL)     /*!< DSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTDNSR_DSCBFAHL_Pos      (14UL)         /*!< DSCBFAHL (Bit 14)                                     */
+ #define R_GPT09_0_GTDNSR_DSCBFAHL_Msk      (0xc000UL)     /*!< DSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTDNSR_DSELCA_Pos        (16UL)         /*!< DSELCA (Bit 16)                                       */
+ #define R_GPT09_0_GTDNSR_DSELCA_Msk        (0x10000UL)    /*!< DSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTDNSR_DSELCB_Pos        (17UL)         /*!< DSELCB (Bit 17)                                       */
+ #define R_GPT09_0_GTDNSR_DSELCB_Msk        (0x20000UL)    /*!< DSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTDNSR_DSELCC_Pos        (18UL)         /*!< DSELCC (Bit 18)                                       */
+ #define R_GPT09_0_GTDNSR_DSELCC_Msk        (0x40000UL)    /*!< DSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTDNSR_DSELCD_Pos        (19UL)         /*!< DSELCD (Bit 19)                                       */
+ #define R_GPT09_0_GTDNSR_DSELCD_Msk        (0x80000UL)    /*!< DSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTDNSR_DSELCE_Pos        (20UL)         /*!< DSELCE (Bit 20)                                       */
+ #define R_GPT09_0_GTDNSR_DSELCE_Msk        (0x100000UL)   /*!< DSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTDNSR_DSELCF_Pos        (21UL)         /*!< DSELCF (Bit 21)                                       */
+ #define R_GPT09_0_GTDNSR_DSELCF_Msk        (0x200000UL)   /*!< DSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTDNSR_DSELCG_Pos        (22UL)         /*!< DSELCG (Bit 22)                                       */
+ #define R_GPT09_0_GTDNSR_DSELCG_Msk        (0x400000UL)   /*!< DSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTDNSR_DSELCH_Pos        (23UL)         /*!< DSELCH (Bit 23)                                       */
+ #define R_GPT09_0_GTDNSR_DSELCH_Msk        (0x800000UL)   /*!< DSELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTICASR  ======================================================== */
+ #define R_GPT09_0_GTICASR_ASGTRGAFR_Pos    (0UL)          /*!< ASGTRGAFR (Bit 0)                                     */
+ #define R_GPT09_0_GTICASR_ASGTRGAFR_Msk    (0x3UL)        /*!< ASGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTICASR_ASGTRGBFR_Pos    (2UL)          /*!< ASGTRGBFR (Bit 2)                                     */
+ #define R_GPT09_0_GTICASR_ASGTRGBFR_Msk    (0xcUL)        /*!< ASGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTICASR_ASGTRGCFR_Pos    (4UL)          /*!< ASGTRGCFR (Bit 4)                                     */
+ #define R_GPT09_0_GTICASR_ASGTRGCFR_Msk    (0x30UL)       /*!< ASGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTICASR_ASGTRGDFR_Pos    (6UL)          /*!< ASGTRGDFR (Bit 6)                                     */
+ #define R_GPT09_0_GTICASR_ASGTRGDFR_Msk    (0xc0UL)       /*!< ASGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTICASR_ASCARBHL_Pos     (8UL)          /*!< ASCARBHL (Bit 8)                                      */
+ #define R_GPT09_0_GTICASR_ASCARBHL_Msk     (0x300UL)      /*!< ASCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTICASR_ASCAFBHL_Pos     (10UL)         /*!< ASCAFBHL (Bit 10)                                     */
+ #define R_GPT09_0_GTICASR_ASCAFBHL_Msk     (0xc00UL)      /*!< ASCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTICASR_ASCBRAHL_Pos     (12UL)         /*!< ASCBRAHL (Bit 12)                                     */
+ #define R_GPT09_0_GTICASR_ASCBRAHL_Msk     (0x3000UL)     /*!< ASCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTICASR_ASCBFAHL_Pos     (14UL)         /*!< ASCBFAHL (Bit 14)                                     */
+ #define R_GPT09_0_GTICASR_ASCBFAHL_Msk     (0xc000UL)     /*!< ASCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTICASR_ASELCA_Pos       (16UL)         /*!< ASELCA (Bit 16)                                       */
+ #define R_GPT09_0_GTICASR_ASELCA_Msk       (0x10000UL)    /*!< ASELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICASR_ASELCB_Pos       (17UL)         /*!< ASELCB (Bit 17)                                       */
+ #define R_GPT09_0_GTICASR_ASELCB_Msk       (0x20000UL)    /*!< ASELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICASR_ASELCC_Pos       (18UL)         /*!< ASELCC (Bit 18)                                       */
+ #define R_GPT09_0_GTICASR_ASELCC_Msk       (0x40000UL)    /*!< ASELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICASR_ASELCD_Pos       (19UL)         /*!< ASELCD (Bit 19)                                       */
+ #define R_GPT09_0_GTICASR_ASELCD_Msk       (0x80000UL)    /*!< ASELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICASR_ASELCE_Pos       (20UL)         /*!< ASELCE (Bit 20)                                       */
+ #define R_GPT09_0_GTICASR_ASELCE_Msk       (0x100000UL)   /*!< ASELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICASR_ASELCF_Pos       (21UL)         /*!< ASELCF (Bit 21)                                       */
+ #define R_GPT09_0_GTICASR_ASELCF_Msk       (0x200000UL)   /*!< ASELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICASR_ASELCG_Pos       (22UL)         /*!< ASELCG (Bit 22)                                       */
+ #define R_GPT09_0_GTICASR_ASELCG_Msk       (0x400000UL)   /*!< ASELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICASR_ASELCH_Pos       (23UL)         /*!< ASELCH (Bit 23)                                       */
+ #define R_GPT09_0_GTICASR_ASELCH_Msk       (0x800000UL)   /*!< ASELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTICBSR  ======================================================== */
+ #define R_GPT09_0_GTICBSR_BSGTRGAFR_Pos    (0UL)          /*!< BSGTRGAFR (Bit 0)                                     */
+ #define R_GPT09_0_GTICBSR_BSGTRGAFR_Msk    (0x3UL)        /*!< BSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTICBSR_BSGTRGBFR_Pos    (2UL)          /*!< BSGTRGBFR (Bit 2)                                     */
+ #define R_GPT09_0_GTICBSR_BSGTRGBFR_Msk    (0xcUL)        /*!< BSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTICBSR_BSGTRGCFR_Pos    (4UL)          /*!< BSGTRGCFR (Bit 4)                                     */
+ #define R_GPT09_0_GTICBSR_BSGTRGCFR_Msk    (0x30UL)       /*!< BSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTICBSR_BSGTRGDFR_Pos    (6UL)          /*!< BSGTRGDFR (Bit 6)                                     */
+ #define R_GPT09_0_GTICBSR_BSGTRGDFR_Msk    (0xc0UL)       /*!< BSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT09_0_GTICBSR_BSCARBHL_Pos     (8UL)          /*!< BSCARBHL (Bit 8)                                      */
+ #define R_GPT09_0_GTICBSR_BSCARBHL_Msk     (0x300UL)      /*!< BSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTICBSR_BSCAFBHL_Pos     (10UL)         /*!< BSCAFBHL (Bit 10)                                     */
+ #define R_GPT09_0_GTICBSR_BSCAFBHL_Msk     (0xc00UL)      /*!< BSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTICBSR_BSCBRAHL_Pos     (12UL)         /*!< BSCBRAHL (Bit 12)                                     */
+ #define R_GPT09_0_GTICBSR_BSCBRAHL_Msk     (0x3000UL)     /*!< BSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTICBSR_BSCBFAHL_Pos     (14UL)         /*!< BSCBFAHL (Bit 14)                                     */
+ #define R_GPT09_0_GTICBSR_BSCBFAHL_Msk     (0xc000UL)     /*!< BSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT09_0_GTICBSR_BSELCA_Pos       (16UL)         /*!< BSELCA (Bit 16)                                       */
+ #define R_GPT09_0_GTICBSR_BSELCA_Msk       (0x10000UL)    /*!< BSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICBSR_BSELCB_Pos       (17UL)         /*!< BSELCB (Bit 17)                                       */
+ #define R_GPT09_0_GTICBSR_BSELCB_Msk       (0x20000UL)    /*!< BSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICBSR_BSELCC_Pos       (18UL)         /*!< BSELCC (Bit 18)                                       */
+ #define R_GPT09_0_GTICBSR_BSELCC_Msk       (0x40000UL)    /*!< BSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICBSR_BSELCD_Pos       (19UL)         /*!< BSELCD (Bit 19)                                       */
+ #define R_GPT09_0_GTICBSR_BSELCD_Msk       (0x80000UL)    /*!< BSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICBSR_BSELCE_Pos       (20UL)         /*!< BSELCE (Bit 20)                                       */
+ #define R_GPT09_0_GTICBSR_BSELCE_Msk       (0x100000UL)   /*!< BSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICBSR_BSELCF_Pos       (21UL)         /*!< BSELCF (Bit 21)                                       */
+ #define R_GPT09_0_GTICBSR_BSELCF_Msk       (0x200000UL)   /*!< BSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICBSR_BSELCG_Pos       (22UL)         /*!< BSELCG (Bit 22)                                       */
+ #define R_GPT09_0_GTICBSR_BSELCG_Msk       (0x400000UL)   /*!< BSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTICBSR_BSELCH_Pos       (23UL)         /*!< BSELCH (Bit 23)                                       */
+ #define R_GPT09_0_GTICBSR_BSELCH_Msk       (0x800000UL)   /*!< BSELCH (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTCR  ========================================================== */
+ #define R_GPT09_0_GTCR_CST_Pos             (0UL)          /*!< CST (Bit 0)                                           */
+ #define R_GPT09_0_GTCR_CST_Msk             (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTCR_ICDS_Pos            (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT09_0_GTCR_ICDS_Msk            (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTCR_MD_Pos              (16UL)         /*!< MD (Bit 16)                                           */
+ #define R_GPT09_0_GTCR_MD_Msk              (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT09_0_GTCR_TPCS_Pos            (23UL)         /*!< TPCS (Bit 23)                                         */
+ #define R_GPT09_0_GTCR_TPCS_Msk            (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
+ #define R_GPT09_0_GTCR_SWMD_Pos            (29UL)         /*!< SWMD (Bit 29)                                         */
+ #define R_GPT09_0_GTCR_SWMD_Msk            (0xe0000000UL) /*!< SWMD (Bitfield-Mask: 0x07)                            */
+/* =======================================================  GTUDDTYC  ======================================================== */
+ #define R_GPT09_0_GTUDDTYC_UD_Pos          (0UL)          /*!< UD (Bit 0)                                            */
+ #define R_GPT09_0_GTUDDTYC_UD_Msk          (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
+ #define R_GPT09_0_GTUDDTYC_UDF_Pos         (1UL)          /*!< UDF (Bit 1)                                           */
+ #define R_GPT09_0_GTUDDTYC_UDF_Msk         (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTUDDTYC_OADTY_Pos       (16UL)         /*!< OADTY (Bit 16)                                        */
+ #define R_GPT09_0_GTUDDTYC_OADTY_Msk       (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT09_0_GTUDDTYC_OADTYF_Pos      (18UL)         /*!< OADTYF (Bit 18)                                       */
+ #define R_GPT09_0_GTUDDTYC_OADTYF_Msk      (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUDDTYC_OADTYR_Pos      (19UL)         /*!< OADTYR (Bit 19)                                       */
+ #define R_GPT09_0_GTUDDTYC_OADTYR_Msk      (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUDDTYC_OBDTY_Pos       (24UL)         /*!< OBDTY (Bit 24)                                        */
+ #define R_GPT09_0_GTUDDTYC_OBDTY_Msk       (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT09_0_GTUDDTYC_OBDTYF_Pos      (26UL)         /*!< OBDTYF (Bit 26)                                       */
+ #define R_GPT09_0_GTUDDTYC_OBDTYF_Msk      (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUDDTYC_OBDTYR_Pos      (27UL)         /*!< OBDTYR (Bit 27)                                       */
+ #define R_GPT09_0_GTUDDTYC_OBDTYR_Msk      (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTUDDTYC_OABDTYT_Pos     (28UL)         /*!< OABDTYT (Bit 28)                                      */
+ #define R_GPT09_0_GTUDDTYC_OABDTYT_Msk     (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTIOR  ========================================================= */
+ #define R_GPT09_0_GTIOR_GTIOA_Pos          (0UL)          /*!< GTIOA (Bit 0)                                         */
+ #define R_GPT09_0_GTIOR_GTIOA_Msk          (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT09_0_GTIOR_OADFLT_Pos         (6UL)          /*!< OADFLT (Bit 6)                                        */
+ #define R_GPT09_0_GTIOR_OADFLT_Msk         (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTIOR_OAHLD_Pos          (7UL)          /*!< OAHLD (Bit 7)                                         */
+ #define R_GPT09_0_GTIOR_OAHLD_Msk          (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTIOR_OAE_Pos            (8UL)          /*!< OAE (Bit 8)                                           */
+ #define R_GPT09_0_GTIOR_OAE_Msk            (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTIOR_OADF_Pos           (9UL)          /*!< OADF (Bit 9)                                          */
+ #define R_GPT09_0_GTIOR_OADF_Msk           (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT09_0_GTIOR_NFAEN_Pos          (13UL)         /*!< NFAEN (Bit 13)                                        */
+ #define R_GPT09_0_GTIOR_NFAEN_Msk          (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTIOR_NFCSA_Pos          (14UL)         /*!< NFCSA (Bit 14)                                        */
+ #define R_GPT09_0_GTIOR_NFCSA_Msk          (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT09_0_GTIOR_GTIOB_Pos          (16UL)         /*!< GTIOB (Bit 16)                                        */
+ #define R_GPT09_0_GTIOR_GTIOB_Msk          (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT09_0_GTIOR_OBDFLT_Pos         (22UL)         /*!< OBDFLT (Bit 22)                                       */
+ #define R_GPT09_0_GTIOR_OBDFLT_Msk         (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTIOR_OBHLD_Pos          (23UL)         /*!< OBHLD (Bit 23)                                        */
+ #define R_GPT09_0_GTIOR_OBHLD_Msk          (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTIOR_OBE_Pos            (24UL)         /*!< OBE (Bit 24)                                          */
+ #define R_GPT09_0_GTIOR_OBE_Msk            (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTIOR_OBDF_Pos           (25UL)         /*!< OBDF (Bit 25)                                         */
+ #define R_GPT09_0_GTIOR_OBDF_Msk           (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT09_0_GTIOR_NFBEN_Pos          (29UL)         /*!< NFBEN (Bit 29)                                        */
+ #define R_GPT09_0_GTIOR_NFBEN_Msk          (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTIOR_NFCSB_Pos          (30UL)         /*!< NFCSB (Bit 30)                                        */
+ #define R_GPT09_0_GTIOR_NFCSB_Msk          (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT09_0_GTINTAD_GTINTA_Pos       (0UL)          /*!< GTINTA (Bit 0)                                        */
+ #define R_GPT09_0_GTINTAD_GTINTA_Msk       (0x1UL)        /*!< GTINTA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTINTAD_GTINTB_Pos       (1UL)          /*!< GTINTB (Bit 1)                                        */
+ #define R_GPT09_0_GTINTAD_GTINTB_Msk       (0x2UL)        /*!< GTINTB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTINTAD_GTINTC_Pos       (2UL)          /*!< GTINTC (Bit 2)                                        */
+ #define R_GPT09_0_GTINTAD_GTINTC_Msk       (0x4UL)        /*!< GTINTC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTINTAD_GTINTD_Pos       (3UL)          /*!< GTINTD (Bit 3)                                        */
+ #define R_GPT09_0_GTINTAD_GTINTD_Msk       (0x8UL)        /*!< GTINTD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTINTAD_GTINTE_Pos       (4UL)          /*!< GTINTE (Bit 4)                                        */
+ #define R_GPT09_0_GTINTAD_GTINTE_Msk       (0x10UL)       /*!< GTINTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTINTAD_GTINTF_Pos       (5UL)          /*!< GTINTF (Bit 5)                                        */
+ #define R_GPT09_0_GTINTAD_GTINTF_Msk       (0x20UL)       /*!< GTINTF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTINTAD_GTINTPR_Pos      (6UL)          /*!< GTINTPR (Bit 6)                                       */
+ #define R_GPT09_0_GTINTAD_GTINTPR_Msk      (0xc0UL)       /*!< GTINTPR (Bitfield-Mask: 0x03)                         */
+ #define R_GPT09_0_GTINTAD_ADTRAUEN_Pos     (16UL)         /*!< ADTRAUEN (Bit 16)                                     */
+ #define R_GPT09_0_GTINTAD_ADTRAUEN_Msk     (0x10000UL)    /*!< ADTRAUEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT09_0_GTINTAD_ADTRADEN_Pos     (17UL)         /*!< ADTRADEN (Bit 17)                                     */
+ #define R_GPT09_0_GTINTAD_ADTRADEN_Msk     (0x20000UL)    /*!< ADTRADEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT09_0_GTINTAD_ADTRBUEN_Pos     (18UL)         /*!< ADTRBUEN (Bit 18)                                     */
+ #define R_GPT09_0_GTINTAD_ADTRBUEN_Msk     (0x40000UL)    /*!< ADTRBUEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT09_0_GTINTAD_ADTRBDEN_Pos     (19UL)         /*!< ADTRBDEN (Bit 19)                                     */
+ #define R_GPT09_0_GTINTAD_ADTRBDEN_Msk     (0x80000UL)    /*!< ADTRBDEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT09_0_GTINTAD_GRP_Pos          (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT09_0_GTINTAD_GRP_Msk          (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+ #define R_GPT09_0_GTINTAD_GRPDTE_Pos       (28UL)         /*!< GRPDTE (Bit 28)                                       */
+ #define R_GPT09_0_GTINTAD_GRPDTE_Msk       (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTINTAD_GRPABH_Pos       (29UL)         /*!< GRPABH (Bit 29)                                       */
+ #define R_GPT09_0_GTINTAD_GRPABH_Msk       (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTINTAD_GRPABL_Pos       (30UL)         /*!< GRPABL (Bit 30)                                       */
+ #define R_GPT09_0_GTINTAD_GRPABL_Msk       (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTST  ========================================================== */
+ #define R_GPT09_0_GTST_ITCNT_Pos           (8UL)          /*!< ITCNT (Bit 8)                                         */
+ #define R_GPT09_0_GTST_ITCNT_Msk           (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
+ #define R_GPT09_0_GTST_TUCF_Pos            (15UL)         /*!< TUCF (Bit 15)                                         */
+ #define R_GPT09_0_GTST_TUCF_Msk            (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTST_ADTRAUF_Pos         (16UL)         /*!< ADTRAUF (Bit 16)                                      */
+ #define R_GPT09_0_GTST_ADTRAUF_Msk         (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTST_ADTRADF_Pos         (17UL)         /*!< ADTRADF (Bit 17)                                      */
+ #define R_GPT09_0_GTST_ADTRADF_Msk         (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTST_ADTRBUF_Pos         (18UL)         /*!< ADTRBUF (Bit 18)                                      */
+ #define R_GPT09_0_GTST_ADTRBUF_Msk         (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTST_ADTRBDF_Pos         (19UL)         /*!< ADTRBDF (Bit 19)                                      */
+ #define R_GPT09_0_GTST_ADTRBDF_Msk         (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTST_ODF_Pos             (24UL)         /*!< ODF (Bit 24)                                          */
+ #define R_GPT09_0_GTST_ODF_Msk             (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTST_DTEF_Pos            (28UL)         /*!< DTEF (Bit 28)                                         */
+ #define R_GPT09_0_GTST_DTEF_Msk            (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTST_OABHF_Pos           (29UL)         /*!< OABHF (Bit 29)                                        */
+ #define R_GPT09_0_GTST_OABHF_Msk           (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTST_OABLF_Pos           (30UL)         /*!< OABLF (Bit 30)                                        */
+ #define R_GPT09_0_GTST_OABLF_Msk           (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTBER  ========================================================= */
+ #define R_GPT09_0_GTBER_BD0_Pos            (0UL)          /*!< BD0 (Bit 0)                                           */
+ #define R_GPT09_0_GTBER_BD0_Msk            (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTBER_BD1_Pos            (1UL)          /*!< BD1 (Bit 1)                                           */
+ #define R_GPT09_0_GTBER_BD1_Msk            (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTBER_BD2_Pos            (2UL)          /*!< BD2 (Bit 2)                                           */
+ #define R_GPT09_0_GTBER_BD2_Msk            (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTBER_BD3_Pos            (3UL)          /*!< BD3 (Bit 3)                                           */
+ #define R_GPT09_0_GTBER_BD3_Msk            (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTBER_DBRTECA_Pos        (8UL)          /*!< DBRTECA (Bit 8)                                       */
+ #define R_GPT09_0_GTBER_DBRTECA_Msk        (0x100UL)      /*!< DBRTECA (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTBER_DBRTECB_Pos        (10UL)         /*!< DBRTECB (Bit 10)                                      */
+ #define R_GPT09_0_GTBER_DBRTECB_Msk        (0x400UL)      /*!< DBRTECB (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTBER_CCRA_Pos           (16UL)         /*!< CCRA (Bit 16)                                         */
+ #define R_GPT09_0_GTBER_CCRA_Msk           (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT09_0_GTBER_CCRB_Pos           (18UL)         /*!< CCRB (Bit 18)                                         */
+ #define R_GPT09_0_GTBER_CCRB_Msk           (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
+ #define R_GPT09_0_GTBER_PR_Pos             (20UL)         /*!< PR (Bit 20)                                           */
+ #define R_GPT09_0_GTBER_PR_Msk             (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
+ #define R_GPT09_0_GTBER_CCRSWT_Pos         (22UL)         /*!< CCRSWT (Bit 22)                                       */
+ #define R_GPT09_0_GTBER_CCRSWT_Msk         (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTBER_ADTTA_Pos          (24UL)         /*!< ADTTA (Bit 24)                                        */
+ #define R_GPT09_0_GTBER_ADTTA_Msk          (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT09_0_GTBER_ADTDA_Pos          (26UL)         /*!< ADTDA (Bit 26)                                        */
+ #define R_GPT09_0_GTBER_ADTDA_Msk          (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTBER_ADTTB_Pos          (28UL)         /*!< ADTTB (Bit 28)                                        */
+ #define R_GPT09_0_GTBER_ADTTB_Msk          (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT09_0_GTBER_ADTDB_Pos          (30UL)         /*!< ADTDB (Bit 30)                                        */
+ #define R_GPT09_0_GTBER_ADTDB_Msk          (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTITC  ========================================================= */
+ #define R_GPT09_0_GTITC_ITLA_Pos           (0UL)          /*!< ITLA (Bit 0)                                          */
+ #define R_GPT09_0_GTITC_ITLA_Msk           (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTITC_ITLB_Pos           (1UL)          /*!< ITLB (Bit 1)                                          */
+ #define R_GPT09_0_GTITC_ITLB_Msk           (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTITC_ITLC_Pos           (2UL)          /*!< ITLC (Bit 2)                                          */
+ #define R_GPT09_0_GTITC_ITLC_Msk           (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTITC_ITLD_Pos           (3UL)          /*!< ITLD (Bit 3)                                          */
+ #define R_GPT09_0_GTITC_ITLD_Msk           (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTITC_ITLE_Pos           (4UL)          /*!< ITLE (Bit 4)                                          */
+ #define R_GPT09_0_GTITC_ITLE_Msk           (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTITC_ITLF_Pos           (5UL)          /*!< ITLF (Bit 5)                                          */
+ #define R_GPT09_0_GTITC_ITLF_Msk           (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT09_0_GTITC_IVTC_Pos           (6UL)          /*!< IVTC (Bit 6)                                          */
+ #define R_GPT09_0_GTITC_IVTC_Msk           (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
+ #define R_GPT09_0_GTITC_IVTT_Pos           (8UL)          /*!< IVTT (Bit 8)                                          */
+ #define R_GPT09_0_GTITC_IVTT_Msk           (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
+ #define R_GPT09_0_GTITC_ADTAL_Pos          (12UL)         /*!< ADTAL (Bit 12)                                        */
+ #define R_GPT09_0_GTITC_ADTAL_Msk          (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTITC_ADTBL_Pos          (14UL)         /*!< ADTBL (Bit 14)                                        */
+ #define R_GPT09_0_GTITC_ADTBL_Msk          (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCNT  ========================================================= */
+/* =========================================================  GTCCR  ========================================================= */
+/* =========================================================  GTPR  ========================================================== */
+/* =========================================================  GTPBR  ========================================================= */
+/* ========================================================  GTPDBR  ========================================================= */
+/* ========================================================  GTADTRA  ======================================================== */
+/* =======================================================  GTADTBRA  ======================================================== */
+/* =======================================================  GTADTDBRA  ======================================================= */
+/* ========================================================  GTADTRB  ======================================================== */
+/* =======================================================  GTADTBRB  ======================================================== */
+/* =======================================================  GTADTDBRB  ======================================================= */
+/* ========================================================  GTDTCR  ========================================================= */
+ #define R_GPT09_0_GTDTCR_TDE_Pos      (0UL)     /*!< TDE (Bit 0)                                           */
+ #define R_GPT09_0_GTDTCR_TDE_Msk      (0x1UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT09_0_GTDTCR_TDBUE_Pos    (4UL)     /*!< TDBUE (Bit 4)                                         */
+ #define R_GPT09_0_GTDTCR_TDBUE_Msk    (0x10UL)  /*!< TDBUE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTDTCR_TDBDE_Pos    (5UL)     /*!< TDBDE (Bit 5)                                         */
+ #define R_GPT09_0_GTDTCR_TDBDE_Msk    (0x20UL)  /*!< TDBDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTDTCR_TDFER_Pos    (8UL)     /*!< TDFER (Bit 8)                                         */
+ #define R_GPT09_0_GTDTCR_TDFER_Msk    (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTDVU  ========================================================= */
+/* =========================================================  GTDVD  ========================================================= */
+/* =========================================================  GTDBU  ========================================================= */
+/* =========================================================  GTDBD  ========================================================= */
+/* =========================================================  GTSOS  ========================================================= */
+ #define R_GPT09_0_GTSOS_SOS_Pos           (0UL)          /*!< SOS (Bit 0)                                           */
+ #define R_GPT09_0_GTSOS_SOS_Msk           (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
+/* ========================================================  GTSOTR  ========================================================= */
+ #define R_GPT09_0_GTSOTR_SOTR_Pos         (0UL)          /*!< SOTR (Bit 0)                                          */
+ #define R_GPT09_0_GTSOTR_SOTR_Msk         (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT09_0_GTADSMR_ADSMS0_Pos      (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT09_0_GTADSMR_ADSMS0_Msk      (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT09_0_GTADSMR_ADSMEN0_Pos     (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT09_0_GTADSMR_ADSMEN0_Msk     (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTADSMR_ADSMS1_Pos      (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT09_0_GTADSMR_ADSMS1_Msk      (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT09_0_GTADSMR_ADSMEN1_Pos     (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT09_0_GTADSMR_ADSMEN1_Msk     (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT09_0_GTEITC_EIVTC1_Pos       (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT09_0_GTEITC_EIVTC1_Msk       (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT09_0_GTEITC_EIVTT1_Pos       (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT09_0_GTEITC_EIVTT1_Msk       (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT09_0_GTEITC_EITCNT1_Pos      (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT09_0_GTEITC_EITCNT1_Msk      (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT09_0_GTEITC_EIVTC2_Pos       (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT09_0_GTEITC_EIVTC2_Msk       (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT09_0_GTEITC_EIVTT2_Pos       (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT09_0_GTEITC_EIVTT2_Msk       (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT09_0_GTEITC_EITCNT2IV_Pos    (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT09_0_GTEITC_EITCNT2IV_Msk    (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT09_0_GTEITC_EITCNT2_Pos      (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT09_0_GTEITC_EITCNT2_Msk      (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT09_0_GTEITLI1_EITLA_Pos      (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT09_0_GTEITLI1_EITLA_Msk      (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT09_0_GTEITLI1_EITLB_Pos      (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT09_0_GTEITLI1_EITLB_Msk      (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT09_0_GTEITLI1_EITLC_Pos      (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT09_0_GTEITLI1_EITLC_Msk      (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT09_0_GTEITLI1_EITLD_Pos      (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT09_0_GTEITLI1_EITLD_Msk      (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT09_0_GTEITLI1_EITLE_Pos      (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT09_0_GTEITLI1_EITLE_Msk      (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT09_0_GTEITLI1_EITLF_Pos      (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT09_0_GTEITLI1_EITLF_Msk      (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT09_0_GTEITLI1_EITLV_Pos      (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT09_0_GTEITLI1_EITLV_Msk      (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT09_0_GTEITLI1_EITLU_Pos      (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT09_0_GTEITLI1_EITLU_Msk      (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT09_0_GTEITLI2_EADTAL_Pos     (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT09_0_GTEITLI2_EADTAL_Msk     (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT09_0_GTEITLI2_EADTBL_Pos     (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT09_0_GTEITLI2_EADTBL_Msk     (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT09_0_GTEITLB_EBTLCA_Pos      (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT09_0_GTEITLB_EBTLCA_Msk      (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT09_0_GTEITLB_EBTLCB_Pos      (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT09_0_GTEITLB_EBTLCB_Msk      (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT09_0_GTEITLB_EBTLPR_Pos      (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT09_0_GTEITLB_EBTLPR_Msk      (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT09_0_GTEITLB_EBTLADA_Pos     (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT09_0_GTEITLB_EBTLADA_Msk     (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT09_0_GTEITLB_EBTLADB_Pos     (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT09_0_GTEITLB_EBTLADB_Msk     (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT09_0_GTEITLB_EBTLDVU_Pos     (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT09_0_GTEITLB_EBTLDVU_Msk     (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT09_0_GTEITLB_EBTLDVD_Pos     (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT09_0_GTEITLB_EBTLDVD_Msk     (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
+/* ========================================================  GTSECSR  ======================================================== */
+ #define R_GPT09_0_GTSECSR_SECSEL0_Pos     (0UL)          /*!< SECSEL0 (Bit 0)                                       */
+ #define R_GPT09_0_GTSECSR_SECSEL0_Msk     (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTSECSR_SECSEL1_Pos     (1UL)          /*!< SECSEL1 (Bit 1)                                       */
+ #define R_GPT09_0_GTSECSR_SECSEL1_Msk     (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTSECSR_SECSEL2_Pos     (2UL)          /*!< SECSEL2 (Bit 2)                                       */
+ #define R_GPT09_0_GTSECSR_SECSEL2_Msk     (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTSECSR_SECSEL3_Pos     (3UL)          /*!< SECSEL3 (Bit 3)                                       */
+ #define R_GPT09_0_GTSECSR_SECSEL3_Msk     (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTSECSR_SECSEL4_Pos     (4UL)          /*!< SECSEL4 (Bit 4)                                       */
+ #define R_GPT09_0_GTSECSR_SECSEL4_Msk     (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTSECSR_SECSEL5_Pos     (5UL)          /*!< SECSEL5 (Bit 5)                                       */
+ #define R_GPT09_0_GTSECSR_SECSEL5_Msk     (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT09_0_GTSECSR_SECSEL6_Pos     (6UL)          /*!< SECSEL6 (Bit 6)                                       */
+ #define R_GPT09_0_GTSECSR_SECSEL6_Msk     (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTSECR  ========================================================= */
+ #define R_GPT09_0_GTSECR_SBDCE_Pos        (0UL)          /*!< SBDCE (Bit 0)                                         */
+ #define R_GPT09_0_GTSECR_SBDCE_Msk        (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTSECR_SBDPE_Pos        (1UL)          /*!< SBDPE (Bit 1)                                         */
+ #define R_GPT09_0_GTSECR_SBDPE_Msk        (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTSECR_SBDAE_Pos        (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT09_0_GTSECR_SBDAE_Msk        (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTSECR_SBDDE_Pos        (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT09_0_GTSECR_SBDDE_Msk        (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTSECR_SBDCD_Pos        (8UL)          /*!< SBDCD (Bit 8)                                         */
+ #define R_GPT09_0_GTSECR_SBDCD_Msk        (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTSECR_SBDPD_Pos        (9UL)          /*!< SBDPD (Bit 9)                                         */
+ #define R_GPT09_0_GTSECR_SBDPD_Msk        (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTSECR_SBDAD_Pos        (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT09_0_GTSECR_SBDAD_Msk        (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT09_0_GTSECR_SBDDD_Pos        (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT09_0_GTSECR_SBDDD_Msk        (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  GTSWSR  ========================================================= */
+ #define R_GPT09_0_GTSWSR_WSGTRGA_Pos      (0UL)          /*!< WSGTRGA (Bit 0)                                       */
+ #define R_GPT09_0_GTSWSR_WSGTRGA_Msk      (0x3UL)        /*!< WSGTRGA (Bitfield-Mask: 0x03)                         */
+ #define R_GPT09_0_GTSWSR_WSGTRGB_Pos      (2UL)          /*!< WSGTRGB (Bit 2)                                       */
+ #define R_GPT09_0_GTSWSR_WSGTRGB_Msk      (0xcUL)        /*!< WSGTRGB (Bitfield-Mask: 0x03)                         */
+ #define R_GPT09_0_GTSWSR_WSGTRGC_Pos      (4UL)          /*!< WSGTRGC (Bit 4)                                       */
+ #define R_GPT09_0_GTSWSR_WSGTRGC_Msk      (0x30UL)       /*!< WSGTRGC (Bitfield-Mask: 0x03)                         */
+ #define R_GPT09_0_GTSWSR_WSGTRGD_Pos      (6UL)          /*!< WSGTRGD (Bit 6)                                       */
+ #define R_GPT09_0_GTSWSR_WSGTRGD_Msk      (0xc0UL)       /*!< WSGTRGD (Bitfield-Mask: 0x03)                         */
+ #define R_GPT09_0_GTSWSR_WSELCA_Pos       (16UL)         /*!< WSELCA (Bit 16)                                       */
+ #define R_GPT09_0_GTSWSR_WSELCA_Msk       (0x10000UL)    /*!< WSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSWSR_WSELCB_Pos       (17UL)         /*!< WSELCB (Bit 17)                                       */
+ #define R_GPT09_0_GTSWSR_WSELCB_Msk       (0x20000UL)    /*!< WSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSWSR_WSELCC_Pos       (18UL)         /*!< WSELCC (Bit 18)                                       */
+ #define R_GPT09_0_GTSWSR_WSELCC_Msk       (0x40000UL)    /*!< WSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSWSR_WSELCD_Pos       (19UL)         /*!< WSELCD (Bit 19)                                       */
+ #define R_GPT09_0_GTSWSR_WSELCD_Msk       (0x80000UL)    /*!< WSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSWSR_WSELCE_Pos       (20UL)         /*!< WSELCE (Bit 20)                                       */
+ #define R_GPT09_0_GTSWSR_WSELCE_Msk       (0x100000UL)   /*!< WSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSWSR_WSELCF_Pos       (21UL)         /*!< WSELCF (Bit 21)                                       */
+ #define R_GPT09_0_GTSWSR_WSELCF_Msk       (0x200000UL)   /*!< WSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSWSR_WSELCG_Pos       (22UL)         /*!< WSELCG (Bit 22)                                       */
+ #define R_GPT09_0_GTSWSR_WSELCG_Msk       (0x400000UL)   /*!< WSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT09_0_GTSWSR_CSELCH_Pos       (23UL)         /*!< CSELCH (Bit 23)                                       */
+ #define R_GPT09_0_GTSWSR_CSELCH_Msk       (0x800000UL)   /*!< CSELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTSWOS  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CRC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CRCCR0  ========================================================= */
+ #define R_CRC0_CRCCR0_GPS_Pos       (0UL)    /*!< GPS (Bit 0)                                           */
+ #define R_CRC0_CRCCR0_GPS_Msk       (0x7UL)  /*!< GPS (Bitfield-Mask: 0x07)                             */
+ #define R_CRC0_CRCCR0_LMS_Pos       (6UL)    /*!< LMS (Bit 6)                                           */
+ #define R_CRC0_CRCCR0_LMS_Msk       (0x40UL) /*!< LMS (Bitfield-Mask: 0x01)                             */
+ #define R_CRC0_CRCCR0_DORCLR_Pos    (7UL)    /*!< DORCLR (Bit 7)                                        */
+ #define R_CRC0_CRCCR0_DORCLR_Msk    (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CRCDIR  ========================================================= */
+/* =======================================================  CRCDIR_BY  ======================================================= */
+/* ========================================================  CRCDOR  ========================================================= */
+/* =======================================================  CRCDOR_HA  ======================================================= */
+/* =======================================================  CRCDOR_BY  ======================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  RDR  ========================================================== */
+ #define R_SCI0_RDR_RDAT_Pos           (0UL)          /*!< RDAT (Bit 0)                                          */
+ #define R_SCI0_RDR_RDAT_Msk           (0x1ffUL)      /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
+ #define R_SCI0_RDR_MPB_Pos            (9UL)          /*!< MPB (Bit 9)                                           */
+ #define R_SCI0_RDR_MPB_Msk            (0x200UL)      /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_RDR_DR_Pos             (10UL)         /*!< DR (Bit 10)                                           */
+ #define R_SCI0_RDR_DR_Msk             (0x400UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_RDR_FPER_Pos           (11UL)         /*!< FPER (Bit 11)                                         */
+ #define R_SCI0_RDR_FPER_Msk           (0x800UL)      /*!< FPER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_RDR_FFER_Pos           (12UL)         /*!< FFER (Bit 12)                                         */
+ #define R_SCI0_RDR_FFER_Msk           (0x1000UL)     /*!< FFER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_RDR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
+ #define R_SCI0_RDR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_RDR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
+ #define R_SCI0_RDR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_RDR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
+ #define R_SCI0_RDR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  TDR  ========================================================== */
+ #define R_SCI0_TDR_TDAT_Pos           (0UL)          /*!< TDAT (Bit 0)                                          */
+ #define R_SCI0_TDR_TDAT_Msk           (0x1ffUL)      /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
+ #define R_SCI0_TDR_MPBT_Pos           (9UL)          /*!< MPBT (Bit 9)                                          */
+ #define R_SCI0_TDR_MPBT_Msk           (0x200UL)      /*!< MPBT (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_TDR_TSYNC_Pos          (12UL)         /*!< TSYNC (Bit 12)                                        */
+ #define R_SCI0_TDR_TSYNC_Msk          (0x1000UL)     /*!< TSYNC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CCR0  ========================================================== */
+ #define R_SCI0_CCR0_RE_Pos            (0UL)          /*!< RE (Bit 0)                                            */
+ #define R_SCI0_CCR0_RE_Msk            (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR0_TE_Pos            (4UL)          /*!< TE (Bit 4)                                            */
+ #define R_SCI0_CCR0_TE_Msk            (0x10UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR0_MPIE_Pos          (8UL)          /*!< MPIE (Bit 8)                                          */
+ #define R_SCI0_CCR0_MPIE_Msk          (0x100UL)      /*!< MPIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR0_DCME_Pos          (9UL)          /*!< DCME (Bit 9)                                          */
+ #define R_SCI0_CCR0_DCME_Msk          (0x200UL)      /*!< DCME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR0_IDSEL_Pos         (10UL)         /*!< IDSEL (Bit 10)                                        */
+ #define R_SCI0_CCR0_IDSEL_Msk         (0x400UL)      /*!< IDSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CCR0_RIE_Pos           (16UL)         /*!< RIE (Bit 16)                                          */
+ #define R_SCI0_CCR0_RIE_Msk           (0x10000UL)    /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR0_TIE_Pos           (20UL)         /*!< TIE (Bit 20)                                          */
+ #define R_SCI0_CCR0_TIE_Msk           (0x100000UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR0_TEIE_Pos          (21UL)         /*!< TEIE (Bit 21)                                         */
+ #define R_SCI0_CCR0_TEIE_Msk          (0x200000UL)   /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR0_SSE_Pos           (24UL)         /*!< SSE (Bit 24)                                          */
+ #define R_SCI0_CCR0_SSE_Msk           (0x1000000UL)  /*!< SSE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CCR1  ========================================================== */
+ #define R_SCI0_CCR1_CTSE_Pos          (0UL)          /*!< CTSE (Bit 0)                                          */
+ #define R_SCI0_CCR1_CTSE_Msk          (0x1UL)        /*!< CTSE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR1_CTSPEN_Pos        (1UL)          /*!< CTSPEN (Bit 1)                                        */
+ #define R_SCI0_CCR1_CTSPEN_Msk        (0x2UL)        /*!< CTSPEN (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CCR1_SPB2DT_Pos        (4UL)          /*!< SPB2DT (Bit 4)                                        */
+ #define R_SCI0_CCR1_SPB2DT_Msk        (0x10UL)       /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CCR1_SPB2IO_Pos        (5UL)          /*!< SPB2IO (Bit 5)                                        */
+ #define R_SCI0_CCR1_SPB2IO_Msk        (0x20UL)       /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CCR1_PE_Pos            (8UL)          /*!< PE (Bit 8)                                            */
+ #define R_SCI0_CCR1_PE_Msk            (0x100UL)      /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR1_PM_Pos            (9UL)          /*!< PM (Bit 9)                                            */
+ #define R_SCI0_CCR1_PM_Msk            (0x200UL)      /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR1_TINV_Pos          (12UL)         /*!< TINV (Bit 12)                                         */
+ #define R_SCI0_CCR1_TINV_Msk          (0x1000UL)     /*!< TINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR1_RINV_Pos          (13UL)         /*!< RINV (Bit 13)                                         */
+ #define R_SCI0_CCR1_RINV_Msk          (0x2000UL)     /*!< RINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR1_SPLP_Pos          (16UL)         /*!< SPLP (Bit 16)                                         */
+ #define R_SCI0_CCR1_SPLP_Msk          (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR1_SHARPS_Pos        (20UL)         /*!< SHARPS (Bit 20)                                       */
+ #define R_SCI0_CCR1_SHARPS_Msk        (0x100000UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CCR1_NFCS_Pos          (24UL)         /*!< NFCS (Bit 24)                                         */
+ #define R_SCI0_CCR1_NFCS_Msk          (0x7000000UL)  /*!< NFCS (Bitfield-Mask: 0x07)                            */
+ #define R_SCI0_CCR1_NFEN_Pos          (28UL)         /*!< NFEN (Bit 28)                                         */
+ #define R_SCI0_CCR1_NFEN_Msk          (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CCR2  ========================================================== */
+ #define R_SCI0_CCR2_BCP_Pos           (0UL)          /*!< BCP (Bit 0)                                           */
+ #define R_SCI0_CCR2_BCP_Msk           (0x7UL)        /*!< BCP (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_CCR2_BGDM_Pos          (4UL)          /*!< BGDM (Bit 4)                                          */
+ #define R_SCI0_CCR2_BGDM_Msk          (0x10UL)       /*!< BGDM (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR2_ABCS_Pos          (5UL)          /*!< ABCS (Bit 5)                                          */
+ #define R_SCI0_CCR2_ABCS_Msk          (0x20UL)       /*!< ABCS (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR2_ABCSE_Pos         (6UL)          /*!< ABCSE (Bit 6)                                         */
+ #define R_SCI0_CCR2_ABCSE_Msk         (0x40UL)       /*!< ABCSE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CCR2_BRR_Pos           (8UL)          /*!< BRR (Bit 8)                                           */
+ #define R_SCI0_CCR2_BRR_Msk           (0xff00UL)     /*!< BRR (Bitfield-Mask: 0xff)                             */
+ #define R_SCI0_CCR2_BRME_Pos          (16UL)         /*!< BRME (Bit 16)                                         */
+ #define R_SCI0_CCR2_BRME_Msk          (0x10000UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR2_CKS_Pos           (20UL)         /*!< CKS (Bit 20)                                          */
+ #define R_SCI0_CCR2_CKS_Msk           (0x300000UL)   /*!< CKS (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_CCR2_MDDR_Pos          (24UL)         /*!< MDDR (Bit 24)                                         */
+ #define R_SCI0_CCR2_MDDR_Msk          (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff)                            */
+/* =========================================================  CCR3  ========================================================== */
+ #define R_SCI0_CCR3_CPHA_Pos          (0UL)          /*!< CPHA (Bit 0)                                          */
+ #define R_SCI0_CCR3_CPHA_Msk          (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_CPOL_Pos          (1UL)          /*!< CPOL (Bit 1)                                          */
+ #define R_SCI0_CCR3_CPOL_Msk          (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_BPEN_Pos          (7UL)          /*!< BPEN (Bit 7)                                          */
+ #define R_SCI0_CCR3_BPEN_Msk          (0x80UL)       /*!< BPEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_CHR_Pos           (8UL)          /*!< CHR (Bit 8)                                           */
+ #define R_SCI0_CCR3_CHR_Msk           (0x300UL)      /*!< CHR (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_CCR3_LSBF_Pos          (12UL)         /*!< LSBF (Bit 12)                                         */
+ #define R_SCI0_CCR3_LSBF_Msk          (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_SINV_Pos          (13UL)         /*!< SINV (Bit 13)                                         */
+ #define R_SCI0_CCR3_SINV_Msk          (0x2000UL)     /*!< SINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR3_STP_Pos           (14UL)         /*!< STP (Bit 14)                                          */
+ #define R_SCI0_CCR3_STP_Msk           (0x4000UL)     /*!< STP (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR3_RXDESEL_Pos       (15UL)         /*!< RXDESEL (Bit 15)                                      */
+ #define R_SCI0_CCR3_RXDESEL_Msk       (0x8000UL)     /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_CCR3_MOD_Pos           (16UL)         /*!< MOD (Bit 16)                                          */
+ #define R_SCI0_CCR3_MOD_Msk           (0x70000UL)    /*!< MOD (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_CCR3_MP_Pos            (19UL)         /*!< MP (Bit 19)                                           */
+ #define R_SCI0_CCR3_MP_Msk            (0x80000UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR3_FM_Pos            (20UL)         /*!< FM (Bit 20)                                           */
+ #define R_SCI0_CCR3_FM_Msk            (0x100000UL)   /*!< FM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR3_DEN_Pos           (21UL)         /*!< DEN (Bit 21)                                          */
+ #define R_SCI0_CCR3_DEN_Msk           (0x200000UL)   /*!< DEN (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR3_CKE_Pos           (24UL)         /*!< CKE (Bit 24)                                          */
+ #define R_SCI0_CCR3_CKE_Msk           (0x3000000UL)  /*!< CKE (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_CCR3_GM_Pos            (28UL)         /*!< GM (Bit 28)                                           */
+ #define R_SCI0_CCR3_GM_Msk            (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_CCR3_BLK_Pos           (29UL)         /*!< BLK (Bit 29)                                          */
+ #define R_SCI0_CCR3_BLK_Msk           (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CCR4  ========================================================== */
+ #define R_SCI0_CCR4_CMPD_Pos          (0UL)          /*!< CMPD (Bit 0)                                          */
+ #define R_SCI0_CCR4_CMPD_Msk          (0x1ffUL)      /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
+ #define R_SCI0_CCR4_ASEN_Pos          (16UL)         /*!< ASEN (Bit 16)                                         */
+ #define R_SCI0_CCR4_ASEN_Msk          (0x10000UL)    /*!< ASEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR4_ATEN_Pos          (17UL)         /*!< ATEN (Bit 17)                                         */
+ #define R_SCI0_CCR4_ATEN_Msk          (0x20000UL)    /*!< ATEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CCR4_AST_Pos           (24UL)         /*!< AST (Bit 24)                                          */
+ #define R_SCI0_CCR4_AST_Msk           (0x7000000UL)  /*!< AST (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_CCR4_AJD_Pos           (27UL)         /*!< AJD (Bit 27)                                          */
+ #define R_SCI0_CCR4_AJD_Msk           (0x8000000UL)  /*!< AJD (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CCR4_ATT_Pos           (28UL)         /*!< ATT (Bit 28)                                          */
+ #define R_SCI0_CCR4_ATT_Msk           (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_CCR4_AET_Pos           (31UL)         /*!< AET (Bit 31)                                          */
+ #define R_SCI0_CCR4_AET_Msk           (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  ICR  ========================================================== */
+ #define R_SCI0_ICR_IICDL_Pos          (0UL)          /*!< IICDL (Bit 0)                                         */
+ #define R_SCI0_ICR_IICDL_Msk          (0x1fUL)       /*!< IICDL (Bitfield-Mask: 0x1f)                           */
+ #define R_SCI0_ICR_IICINTM_Pos        (8UL)          /*!< IICINTM (Bit 8)                                       */
+ #define R_SCI0_ICR_IICINTM_Msk        (0x100UL)      /*!< IICINTM (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_ICR_IICCSC_Pos         (9UL)          /*!< IICCSC (Bit 9)                                        */
+ #define R_SCI0_ICR_IICCSC_Msk         (0x200UL)      /*!< IICCSC (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_ICR_IICACKT_Pos        (13UL)         /*!< IICACKT (Bit 13)                                      */
+ #define R_SCI0_ICR_IICACKT_Msk        (0x2000UL)     /*!< IICACKT (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_ICR_IICSTAREQ_Pos      (16UL)         /*!< IICSTAREQ (Bit 16)                                    */
+ #define R_SCI0_ICR_IICSTAREQ_Msk      (0x10000UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SCI0_ICR_IICRSTAREQ_Pos     (17UL)         /*!< IICRSTAREQ (Bit 17)                                   */
+ #define R_SCI0_ICR_IICRSTAREQ_Msk     (0x20000UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
+ #define R_SCI0_ICR_IICSTPREQ_Pos      (18UL)         /*!< IICSTPREQ (Bit 18)                                    */
+ #define R_SCI0_ICR_IICSTPREQ_Msk      (0x40000UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SCI0_ICR_IICSDAS_Pos        (20UL)         /*!< IICSDAS (Bit 20)                                      */
+ #define R_SCI0_ICR_IICSDAS_Msk        (0x300000UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
+ #define R_SCI0_ICR_IICSCLS_Pos        (22UL)         /*!< IICSCLS (Bit 22)                                      */
+ #define R_SCI0_ICR_IICSCLS_Msk        (0xc00000UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
+/* ==========================================================  FCR  ========================================================== */
+ #define R_SCI0_FCR_DRES_Pos           (0UL)          /*!< DRES (Bit 0)                                          */
+ #define R_SCI0_FCR_DRES_Msk           (0x1UL)        /*!< DRES (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FCR_TTRG_Pos           (8UL)          /*!< TTRG (Bit 8)                                          */
+ #define R_SCI0_FCR_TTRG_Msk           (0x1f00UL)     /*!< TTRG (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_FCR_TFRST_Pos          (15UL)         /*!< TFRST (Bit 15)                                        */
+ #define R_SCI0_FCR_TFRST_Msk          (0x8000UL)     /*!< TFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_RTRG_Pos           (16UL)         /*!< RTRG (Bit 16)                                         */
+ #define R_SCI0_FCR_RTRG_Msk           (0x1f0000UL)   /*!< RTRG (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_FCR_RFRST_Pos          (23UL)         /*!< RFRST (Bit 23)                                        */
+ #define R_SCI0_FCR_RFRST_Msk          (0x800000UL)   /*!< RFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_RSTRG_Pos          (24UL)         /*!< RSTRG (Bit 24)                                        */
+ #define R_SCI0_FCR_RSTRG_Msk          (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f)                           */
+/* ==========================================================  MCR  ========================================================== */
+ #define R_SCI0_MCR_RMPOL_Pos          (0UL)          /*!< RMPOL (Bit 0)                                         */
+ #define R_SCI0_MCR_RMPOL_Msk          (0x1UL)        /*!< RMPOL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_MCR_TMPOL_Pos          (1UL)          /*!< TMPOL (Bit 1)                                         */
+ #define R_SCI0_MCR_TMPOL_Msk          (0x2UL)        /*!< TMPOL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_MCR_ERTEN_Pos          (2UL)          /*!< ERTEN (Bit 2)                                         */
+ #define R_SCI0_MCR_ERTEN_Msk          (0x4UL)        /*!< ERTEN (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_MCR_SYNVAL_Pos         (4UL)          /*!< SYNVAL (Bit 4)                                        */
+ #define R_SCI0_MCR_SYNVAL_Msk         (0x10UL)       /*!< SYNVAL (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_MCR_SYNSEL_Pos         (5UL)          /*!< SYNSEL (Bit 5)                                        */
+ #define R_SCI0_MCR_SYNSEL_Msk         (0x20UL)       /*!< SYNSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_MCR_SBSEL_Pos          (6UL)          /*!< SBSEL (Bit 6)                                         */
+ #define R_SCI0_MCR_SBSEL_Msk          (0x40UL)       /*!< SBSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_MCR_TPLEN_Pos          (8UL)          /*!< TPLEN (Bit 8)                                         */
+ #define R_SCI0_MCR_TPLEN_Msk          (0xf00UL)      /*!< TPLEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SCI0_MCR_TPPAT_Pos          (12UL)         /*!< TPPAT (Bit 12)                                        */
+ #define R_SCI0_MCR_TPPAT_Msk          (0x3000UL)     /*!< TPPAT (Bitfield-Mask: 0x03)                           */
+ #define R_SCI0_MCR_RPLEN_Pos          (16UL)         /*!< RPLEN (Bit 16)                                        */
+ #define R_SCI0_MCR_RPLEN_Msk          (0xf0000UL)    /*!< RPLEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SCI0_MCR_RPPAT_Pos          (20UL)         /*!< RPPAT (Bit 20)                                        */
+ #define R_SCI0_MCR_RPPAT_Msk          (0x300000UL)   /*!< RPPAT (Bitfield-Mask: 0x03)                           */
+ #define R_SCI0_MCR_PFEREN_Pos         (24UL)         /*!< PFEREN (Bit 24)                                       */
+ #define R_SCI0_MCR_PFEREN_Msk         (0x1000000UL)  /*!< PFEREN (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_MCR_SYEREN_Pos         (25UL)         /*!< SYEREN (Bit 25)                                       */
+ #define R_SCI0_MCR_SYEREN_Msk         (0x2000000UL)  /*!< SYEREN (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_MCR_SBEREN_Pos         (26UL)         /*!< SBEREN (Bit 26)                                       */
+ #define R_SCI0_MCR_SBEREN_Msk         (0x4000000UL)  /*!< SBEREN (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  DCR  ========================================================== */
+ #define R_SCI0_DCR_DEPOL_Pos          (0UL)          /*!< DEPOL (Bit 0)                                         */
+ #define R_SCI0_DCR_DEPOL_Msk          (0x1UL)        /*!< DEPOL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_DCR_DEAST_Pos          (8UL)          /*!< DEAST (Bit 8)                                         */
+ #define R_SCI0_DCR_DEAST_Msk          (0x1f00UL)     /*!< DEAST (Bitfield-Mask: 0x1f)                           */
+ #define R_SCI0_DCR_DENGT_Pos          (16UL)         /*!< DENGT (Bit 16)                                        */
+ #define R_SCI0_DCR_DENGT_Msk          (0x1f0000UL)   /*!< DENGT (Bitfield-Mask: 0x1f)                           */
+/* ==========================================================  CSR  ========================================================== */
+ #define R_SCI0_CSR_ERS_Pos            (4UL)          /*!< ERS (Bit 4)                                           */
+ #define R_SCI0_CSR_ERS_Msk            (0x10UL)       /*!< ERS (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CSR_RXDMON_Pos         (15UL)         /*!< RXDMON (Bit 15)                                       */
+ #define R_SCI0_CSR_RXDMON_Msk         (0x8000UL)     /*!< RXDMON (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CSR_DCMF_Pos           (16UL)         /*!< DCMF (Bit 16)                                         */
+ #define R_SCI0_CSR_DCMF_Msk           (0x10000UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_DPER_Pos           (17UL)         /*!< DPER (Bit 17)                                         */
+ #define R_SCI0_CSR_DPER_Msk           (0x20000UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_DFER_Pos           (18UL)         /*!< DFER (Bit 18)                                         */
+ #define R_SCI0_CSR_DFER_Msk           (0x40000UL)    /*!< DFER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
+ #define R_SCI0_CSR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_MFF_Pos            (26UL)         /*!< MFF (Bit 26)                                          */
+ #define R_SCI0_CSR_MFF_Msk            (0x4000000UL)  /*!< MFF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CSR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
+ #define R_SCI0_CSR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CSR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
+ #define R_SCI0_CSR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CSR_TDRE_Pos           (29UL)         /*!< TDRE (Bit 29)                                         */
+ #define R_SCI0_CSR_TDRE_Msk           (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_TEND_Pos           (30UL)         /*!< TEND (Bit 30)                                         */
+ #define R_SCI0_CSR_TEND_Msk           (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CSR_RDRF_Pos           (31UL)         /*!< RDRF (Bit 31)                                         */
+ #define R_SCI0_CSR_RDRF_Msk           (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  ISR  ========================================================== */
+ #define R_SCI0_ISR_IICACKR_Pos        (0UL)          /*!< IICACKR (Bit 0)                                       */
+ #define R_SCI0_ISR_IICACKR_Msk        (0x1UL)        /*!< IICACKR (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_ISR_IICSTIF_Pos        (3UL)          /*!< IICSTIF (Bit 3)                                       */
+ #define R_SCI0_ISR_IICSTIF_Msk        (0x8UL)        /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
+/* =========================================================  FRSR  ========================================================== */
+ #define R_SCI0_FRSR_DR_Pos            (0UL)          /*!< DR (Bit 0)                                            */
+ #define R_SCI0_FRSR_DR_Msk            (0x1UL)        /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_FRSR_R_Pos             (8UL)          /*!< R (Bit 8)                                             */
+ #define R_SCI0_FRSR_R_Msk             (0x3f00UL)     /*!< R (Bitfield-Mask: 0x3f)                               */
+ #define R_SCI0_FRSR_PNUM_Pos          (16UL)         /*!< PNUM (Bit 16)                                         */
+ #define R_SCI0_FRSR_PNUM_Msk          (0x3f0000UL)   /*!< PNUM (Bitfield-Mask: 0x3f)                            */
+ #define R_SCI0_FRSR_FNUM_Pos          (24UL)         /*!< FNUM (Bit 24)                                         */
+ #define R_SCI0_FRSR_FNUM_Msk          (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f)                            */
+/* =========================================================  FTSR  ========================================================== */
+ #define R_SCI0_FTSR_T_Pos             (0UL)          /*!< T (Bit 0)                                             */
+ #define R_SCI0_FTSR_T_Msk             (0x3fUL)       /*!< T (Bitfield-Mask: 0x3f)                               */
+/* ==========================================================  MSR  ========================================================== */
+ #define R_SCI0_MSR_PFER_Pos           (0UL)          /*!< PFER (Bit 0)                                          */
+ #define R_SCI0_MSR_PFER_Msk           (0x1UL)        /*!< PFER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_MSR_SYER_Pos           (1UL)          /*!< SYER (Bit 1)                                          */
+ #define R_SCI0_MSR_SYER_Msk           (0x2UL)        /*!< SYER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_MSR_SBER_Pos           (2UL)          /*!< SBER (Bit 2)                                          */
+ #define R_SCI0_MSR_SBER_Msk           (0x4UL)        /*!< SBER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_MSR_MER_Pos            (4UL)          /*!< MER (Bit 4)                                           */
+ #define R_SCI0_MSR_MER_Msk            (0x10UL)       /*!< MER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_MSR_RSYNC_Pos          (6UL)          /*!< RSYNC (Bit 6)                                         */
+ #define R_SCI0_MSR_RSYNC_Msk          (0x40UL)       /*!< RSYNC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CFCLR  ========================================================= */
+ #define R_SCI0_CFCLR_ERSC_Pos         (4UL)          /*!< ERSC (Bit 4)                                          */
+ #define R_SCI0_CFCLR_ERSC_Msk         (0x10UL)       /*!< ERSC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CFCLR_DCMFC_Pos        (16UL)         /*!< DCMFC (Bit 16)                                        */
+ #define R_SCI0_CFCLR_DCMFC_Msk        (0x10000UL)    /*!< DCMFC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_DPERC_Pos        (17UL)         /*!< DPERC (Bit 17)                                        */
+ #define R_SCI0_CFCLR_DPERC_Msk        (0x20000UL)    /*!< DPERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_DFERC_Pos        (18UL)         /*!< DFERC (Bit 18)                                        */
+ #define R_SCI0_CFCLR_DFERC_Msk        (0x40000UL)    /*!< DFERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_ORERC_Pos        (24UL)         /*!< ORERC (Bit 24)                                        */
+ #define R_SCI0_CFCLR_ORERC_Msk        (0x1000000UL)  /*!< ORERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_MFFC_Pos         (26UL)         /*!< MFFC (Bit 26)                                         */
+ #define R_SCI0_CFCLR_MFFC_Msk         (0x4000000UL)  /*!< MFFC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CFCLR_PERC_Pos         (27UL)         /*!< PERC (Bit 27)                                         */
+ #define R_SCI0_CFCLR_PERC_Msk         (0x8000000UL)  /*!< PERC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CFCLR_FERC_Pos         (28UL)         /*!< FERC (Bit 28)                                         */
+ #define R_SCI0_CFCLR_FERC_Msk         (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CFCLR_TDREC_Pos        (29UL)         /*!< TDREC (Bit 29)                                        */
+ #define R_SCI0_CFCLR_TDREC_Msk        (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CFCLR_RDRFC_Pos        (31UL)         /*!< RDRFC (Bit 31)                                        */
+ #define R_SCI0_CFCLR_RDRFC_Msk        (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ICFCLR  ========================================================= */
+ #define R_SCI0_ICFCLR_IICSTIFC_Pos    (3UL)          /*!< IICSTIFC (Bit 3)                                      */
+ #define R_SCI0_ICFCLR_IICSTIFC_Msk    (0x8UL)        /*!< IICSTIFC (Bitfield-Mask: 0x01)                        */
+/* =========================================================  FFCLR  ========================================================= */
+ #define R_SCI0_FFCLR_DRC_Pos          (0UL)          /*!< DRC (Bit 0)                                           */
+ #define R_SCI0_FFCLR_DRC_Msk          (0x1UL)        /*!< DRC (Bitfield-Mask: 0x01)                             */
+/* =========================================================  MFCLR  ========================================================= */
+ #define R_SCI0_MFCLR_PFERC_Pos        (0UL)          /*!< PFERC (Bit 0)                                         */
+ #define R_SCI0_MFCLR_PFERC_Msk        (0x1UL)        /*!< PFERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_MFCLR_SYERC_Pos        (1UL)          /*!< SYERC (Bit 1)                                         */
+ #define R_SCI0_MFCLR_SYERC_Msk        (0x2UL)        /*!< SYERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_MFCLR_SBERC_Pos        (2UL)          /*!< SBERC (Bit 2)                                         */
+ #define R_SCI0_MFCLR_SBERC_Msk        (0x4UL)        /*!< SBERC (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_MFCLR_MERC_Pos         (4UL)          /*!< MERC (Bit 4)                                          */
+ #define R_SCI0_MFCLR_MERC_Msk         (0x10UL)       /*!< MERC (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SPDR  ========================================================== */
+ #define R_SPI0_SPDR_SPD_Pos         (0UL)          /*!< SPD (Bit 0)                                           */
+ #define R_SPI0_SPDR_SPD_Msk         (0xffffffffUL) /*!< SPD (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SPDR_HA  ======================================================== */
+/* ========================================================  SPDR_BY  ======================================================== */
+/* =========================================================  SPCKD  ========================================================= */
+ #define R_SPI0_SPCKD_SCKDL_Pos      (0UL)          /*!< SCKDL (Bit 0)                                         */
+ #define R_SPI0_SPCKD_SCKDL_Msk      (0x7UL)        /*!< SCKDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SSLND  ========================================================= */
+ #define R_SPI0_SSLND_SLNDL_Pos      (0UL)          /*!< SLNDL (Bit 0)                                         */
+ #define R_SPI0_SSLND_SLNDL_Msk      (0x7UL)        /*!< SLNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPND  ========================================================== */
+ #define R_SPI0_SPND_SPNDL_Pos       (0UL)          /*!< SPNDL (Bit 0)                                         */
+ #define R_SPI0_SPND_SPNDL_Msk       (0x7UL)        /*!< SPNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  MRCKD  ========================================================= */
+ #define R_SPI0_MRCKD_ARST_Pos       (0UL)          /*!< ARST (Bit 0)                                          */
+ #define R_SPI0_MRCKD_ARST_Msk       (0x7UL)        /*!< ARST (Bitfield-Mask: 0x07)                            */
+/* =========================================================  SPCR  ========================================================== */
+ #define R_SPI0_SPCR_SPE_Pos         (0UL)          /*!< SPE (Bit 0)                                           */
+ #define R_SPI0_SPCR_SPE_Msk         (0x1UL)        /*!< SPE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR_SPSCKSEL_Pos    (7UL)          /*!< SPSCKSEL (Bit 7)                                      */
+ #define R_SPI0_SPCR_SPSCKSEL_Msk    (0x80UL)       /*!< SPSCKSEL (Bitfield-Mask: 0x01)                        */
+ #define R_SPI0_SPCR_SPPE_Pos        (8UL)          /*!< SPPE (Bit 8)                                          */
+ #define R_SPI0_SPCR_SPPE_Msk        (0x100UL)      /*!< SPPE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_SPOE_Pos        (9UL)          /*!< SPOE (Bit 9)                                          */
+ #define R_SPI0_SPCR_SPOE_Msk        (0x200UL)      /*!< SPOE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_PTE_Pos         (11UL)         /*!< PTE (Bit 11)                                          */
+ #define R_SPI0_SPCR_PTE_Msk         (0x800UL)      /*!< PTE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR_SCKASE_Pos      (12UL)         /*!< SCKASE (Bit 12)                                       */
+ #define R_SPI0_SPCR_SCKASE_Msk      (0x1000UL)     /*!< SCKASE (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_BFDS_Pos        (13UL)         /*!< BFDS (Bit 13)                                         */
+ #define R_SPI0_SPCR_BFDS_Msk        (0x2000UL)     /*!< BFDS (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_MODFEN_Pos      (14UL)         /*!< MODFEN (Bit 14)                                       */
+ #define R_SPI0_SPCR_MODFEN_Msk      (0x4000UL)     /*!< MODFEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_SPEIE_Pos       (16UL)         /*!< SPEIE (Bit 16)                                        */
+ #define R_SPI0_SPCR_SPEIE_Msk       (0x10000UL)    /*!< SPEIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPRIE_Pos       (17UL)         /*!< SPRIE (Bit 17)                                        */
+ #define R_SPI0_SPCR_SPRIE_Msk       (0x20000UL)    /*!< SPRIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPIIE_Pos       (18UL)         /*!< SPIIE (Bit 18)                                        */
+ #define R_SPI0_SPCR_SPIIE_Msk       (0x40000UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPDRES_Pos      (19UL)         /*!< SPDRES (Bit 19)                                       */
+ #define R_SPI0_SPCR_SPDRES_Msk      (0x80000UL)    /*!< SPDRES (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_SPTIE_Pos       (20UL)         /*!< SPTIE (Bit 20)                                        */
+ #define R_SPI0_SPCR_SPTIE_Msk       (0x100000UL)   /*!< SPTIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_CENDIE_Pos      (21UL)         /*!< CENDIE (Bit 21)                                       */
+ #define R_SPI0_SPCR_CENDIE_Msk      (0x200000UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_SPMS_Pos        (24UL)         /*!< SPMS (Bit 24)                                         */
+ #define R_SPI0_SPCR_SPMS_Msk        (0x1000000UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_SPFRF_Pos       (25UL)         /*!< SPFRF (Bit 25)                                        */
+ #define R_SPI0_SPCR_SPFRF_Msk       (0x2000000UL)  /*!< SPFRF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_TXMD_Pos        (28UL)         /*!< TXMD (Bit 28)                                         */
+ #define R_SPI0_SPCR_TXMD_Msk        (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPCR_MSTR_Pos        (30UL)         /*!< MSTR (Bit 30)                                         */
+ #define R_SPI0_SPCR_MSTR_Msk        (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_BPEN_Pos        (31UL)         /*!< BPEN (Bit 31)                                         */
+ #define R_SPI0_SPCR_BPEN_Msk        (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SPCRRM  ========================================================= */
+ #define R_SPI0_SPCRRM_RMFM_Pos      (0UL)          /*!< RMFM (Bit 0)                                          */
+ #define R_SPI0_SPCRRM_RMFM_Msk      (0x1fUL)       /*!< RMFM (Bitfield-Mask: 0x1f)                            */
+ #define R_SPI0_SPCRRM_RMEDTG_Pos    (6UL)          /*!< RMEDTG (Bit 6)                                        */
+ #define R_SPI0_SPCRRM_RMEDTG_Msk    (0x40UL)       /*!< RMEDTG (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCRRM_RMSTTG_Pos    (7UL)          /*!< RMSTTG (Bit 7)                                        */
+ #define R_SPI0_SPCRRM_RMSTTG_Msk    (0x80UL)       /*!< RMSTTG (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SPDRCR  ========================================================= */
+ #define R_SPI0_SPDRCR_SPDRC_Pos     (0UL)          /*!< SPDRC (Bit 0)                                         */
+ #define R_SPI0_SPDRCR_SPDRC_Msk     (0xffUL)       /*!< SPDRC (Bitfield-Mask: 0xff)                           */
+/* =========================================================  SPPCR  ========================================================= */
+ #define R_SPI0_SPPCR_SPLP_Pos       (0UL)          /*!< SPLP (Bit 0)                                          */
+ #define R_SPI0_SPPCR_SPLP_Msk       (0x1UL)        /*!< SPLP (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPPCR_SPLP2_Pos      (1UL)          /*!< SPLP2 (Bit 1)                                         */
+ #define R_SPI0_SPPCR_SPLP2_Msk      (0x2UL)        /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_SPOM_Pos       (2UL)          /*!< SPOM (Bit 2)                                          */
+ #define R_SPI0_SPPCR_SPOM_Msk       (0x4UL)        /*!< SPOM (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPPCR_MOIFV_Pos      (4UL)          /*!< MOIFV (Bit 4)                                         */
+ #define R_SPI0_SPPCR_MOIFV_Msk      (0x10UL)       /*!< MOIFV (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_MOIFE_Pos      (5UL)          /*!< MOIFE (Bit 5)                                         */
+ #define R_SPI0_SPPCR_MOIFE_Msk      (0x20UL)       /*!< MOIFE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPCR2  ========================================================= */
+ #define R_SPI0_SPCR2_SPSCKDL_Pos    (0UL)          /*!< SPSCKDL (Bit 0)                                       */
+ #define R_SPI0_SPCR2_SPSCKDL_Msk    (0x7UL)        /*!< SPSCKDL (Bitfield-Mask: 0x07)                         */
+/* =========================================================  SSLP  ========================================================== */
+ #define R_SPI0_SSLP_SSL0P_Pos       (0UL)          /*!< SSL0P (Bit 0)                                         */
+ #define R_SPI0_SSLP_SSL0P_Msk       (0x1UL)        /*!< SSL0P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL1P_Pos       (1UL)          /*!< SSL1P (Bit 1)                                         */
+ #define R_SPI0_SSLP_SSL1P_Msk       (0x2UL)        /*!< SSL1P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL2P_Pos       (2UL)          /*!< SSL2P (Bit 2)                                         */
+ #define R_SPI0_SSLP_SSL2P_Msk       (0x4UL)        /*!< SSL2P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL3P_Pos       (3UL)          /*!< SSL3P (Bit 3)                                         */
+ #define R_SPI0_SSLP_SSL3P_Msk       (0x8UL)        /*!< SSL3P (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPBR  ========================================================== */
+ #define R_SPI0_SPBR_SPR_Pos         (0UL)          /*!< SPR (Bit 0)                                           */
+ #define R_SPI0_SPBR_SPR_Msk         (0xffUL)       /*!< SPR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  SPSCR  ========================================================= */
+ #define R_SPI0_SPSCR_SPSLN_Pos      (0UL)          /*!< SPSLN (Bit 0)                                         */
+ #define R_SPI0_SPSCR_SPSLN_Msk      (0x7UL)        /*!< SPSLN (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPCMD  ========================================================= */
+ #define R_SPI0_SPCMD_CPHA_Pos       (0UL)          /*!< CPHA (Bit 0)                                          */
+ #define R_SPI0_SPCMD_CPHA_Msk       (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_CPOL_Pos       (1UL)          /*!< CPOL (Bit 1)                                          */
+ #define R_SPI0_SPCMD_CPOL_Msk       (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_BRDV_Pos       (2UL)          /*!< BRDV (Bit 2)                                          */
+ #define R_SPI0_SPCMD_BRDV_Msk       (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPCMD_SSLKP_Pos      (7UL)          /*!< SSLKP (Bit 7)                                         */
+ #define R_SPI0_SPCMD_SSLKP_Msk      (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCMD_LSBF_Pos       (12UL)         /*!< LSBF (Bit 12)                                         */
+ #define R_SPI0_SPCMD_LSBF_Msk       (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_SPNDEN_Pos     (13UL)         /*!< SPNDEN (Bit 13)                                       */
+ #define R_SPI0_SPCMD_SPNDEN_Msk     (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SLNDEN_Pos     (14UL)         /*!< SLNDEN (Bit 14)                                       */
+ #define R_SPI0_SPCMD_SLNDEN_Msk     (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SCKDEN_Pos     (15UL)         /*!< SCKDEN (Bit 15)                                       */
+ #define R_SPI0_SPCMD_SCKDEN_Msk     (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SPB_Pos        (16UL)         /*!< SPB (Bit 16)                                          */
+ #define R_SPI0_SPCMD_SPB_Msk        (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
+ #define R_SPI0_SPCMD_SSLA_Pos       (24UL)         /*!< SSLA (Bit 24)                                         */
+ #define R_SPI0_SPCMD_SSLA_Msk       (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x03)                            */
+/* =========================================================  SPDCR  ========================================================= */
+ #define R_SPI0_SPDCR_BYSW_Pos       (0UL)          /*!< BYSW (Bit 0)                                          */
+ #define R_SPI0_SPDCR_BYSW_Msk       (0x1UL)        /*!< BYSW (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR_SLSEL_Pos      (1UL)          /*!< SLSEL (Bit 1)                                         */
+ #define R_SPI0_SPDCR_SLSEL_Msk      (0x6UL)        /*!< SLSEL (Bitfield-Mask: 0x03)                           */
+ #define R_SPI0_SPDCR_SPRDTD_Pos     (3UL)          /*!< SPRDTD (Bit 3)                                        */
+ #define R_SPI0_SPDCR_SPRDTD_Msk     (0x8UL)        /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPDCR_SINV_Pos       (4UL)          /*!< SINV (Bit 4)                                          */
+ #define R_SPI0_SPDCR_SINV_Msk       (0x10UL)       /*!< SINV (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR_SPFC_Pos       (8UL)          /*!< SPFC (Bit 8)                                          */
+ #define R_SPI0_SPDCR_SPFC_Msk       (0x300UL)      /*!< SPFC (Bitfield-Mask: 0x03)                            */
+/* ========================================================  SPDCR2  ========================================================= */
+ #define R_SPI0_SPDCR2_RTRG_Pos      (0UL)          /*!< RTRG (Bit 0)                                          */
+ #define R_SPI0_SPDCR2_RTRG_Msk      (0x3UL)        /*!< RTRG (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPDCR2_TTRG_Pos      (8UL)          /*!< TTRG (Bit 8)                                          */
+ #define R_SPI0_SPDCR2_TTRG_Msk      (0x300UL)      /*!< TTRG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  SPSSR  ========================================================= */
+ #define R_SPI0_SPSSR_SPCP_Pos       (0UL)          /*!< SPCP (Bit 0)                                          */
+ #define R_SPI0_SPSSR_SPCP_Msk       (0x7UL)        /*!< SPCP (Bitfield-Mask: 0x07)                            */
+ #define R_SPI0_SPSSR_SPECM_Pos      (4UL)          /*!< SPECM (Bit 4)                                         */
+ #define R_SPI0_SPSSR_SPECM_Msk      (0x70UL)       /*!< SPECM (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPSR  ========================================================== */
+ #define R_SPI0_SPSR_SPDRF_Pos       (7UL)          /*!< SPDRF (Bit 7)                                         */
+ #define R_SPI0_SPSR_SPDRF_Msk       (0x80UL)       /*!< SPDRF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_OVRF_Pos        (8UL)          /*!< OVRF (Bit 8)                                          */
+ #define R_SPI0_SPSR_OVRF_Msk        (0x100UL)      /*!< OVRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_IDLNF_Pos       (9UL)          /*!< IDLNF (Bit 9)                                         */
+ #define R_SPI0_SPSR_IDLNF_Msk       (0x200UL)      /*!< IDLNF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_MODF_Pos        (10UL)         /*!< MODF (Bit 10)                                         */
+ #define R_SPI0_SPSR_MODF_Msk        (0x400UL)      /*!< MODF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_PERF_Pos        (11UL)         /*!< PERF (Bit 11)                                         */
+ #define R_SPI0_SPSR_PERF_Msk        (0x800UL)      /*!< PERF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_UDRF_Pos        (12UL)         /*!< UDRF (Bit 12)                                         */
+ #define R_SPI0_SPSR_UDRF_Msk        (0x1000UL)     /*!< UDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_SPTEF_Pos       (13UL)         /*!< SPTEF (Bit 13)                                        */
+ #define R_SPI0_SPSR_SPTEF_Msk       (0x2000UL)     /*!< SPTEF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_CENDF_Pos       (14UL)         /*!< CENDF (Bit 14)                                        */
+ #define R_SPI0_SPSR_CENDF_Msk       (0x4000UL)     /*!< CENDF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_SPRF_Pos        (15UL)         /*!< SPRF (Bit 15)                                         */
+ #define R_SPI0_SPSR_SPRF_Msk        (0x8000UL)     /*!< SPRF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SPTFSR  ========================================================= */
+ #define R_SPI0_SPTFSR_TFDN_Pos      (0UL)          /*!< TFDN (Bit 0)                                          */
+ #define R_SPI0_SPTFSR_TFDN_Msk      (0x7UL)        /*!< TFDN (Bitfield-Mask: 0x07)                            */
+/* ========================================================  SPRFSR  ========================================================= */
+ #define R_SPI0_SPRFSR_RFDN_Pos      (0UL)          /*!< RFDN (Bit 0)                                          */
+ #define R_SPI0_SPRFSR_RFDN_Msk      (0x7UL)        /*!< RFDN (Bitfield-Mask: 0x07)                            */
+/* =========================================================  SPPSR  ========================================================= */
+ #define R_SPI0_SPPSR_SPEPS_Pos      (0UL)          /*!< SPEPS (Bit 0)                                         */
+ #define R_SPI0_SPPSR_SPEPS_Msk      (0x1UL)        /*!< SPEPS (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPSRC  ========================================================= */
+ #define R_SPI0_SPSRC_SPDRFC_Pos     (7UL)          /*!< SPDRFC (Bit 7)                                        */
+ #define R_SPI0_SPSRC_SPDRFC_Msk     (0x80UL)       /*!< SPDRFC (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPSRC_OVRFC_Pos      (8UL)          /*!< OVRFC (Bit 8)                                         */
+ #define R_SPI0_SPSRC_OVRFC_Msk      (0x100UL)      /*!< OVRFC (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSRC_MODFC_Pos      (10UL)         /*!< MODFC (Bit 10)                                        */
+ #define R_SPI0_SPSRC_MODFC_Msk      (0x400UL)      /*!< MODFC (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSRC_PERFC_Pos      (11UL)         /*!< PERFC (Bit 11)                                        */
+ #define R_SPI0_SPSRC_PERFC_Msk      (0x800UL)      /*!< PERFC (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSRC_UDRFC_Pos      (12UL)         /*!< UDRFC (Bit 12)                                        */
+ #define R_SPI0_SPSRC_UDRFC_Msk      (0x1000UL)     /*!< UDRFC (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSRC_SPTEFC_Pos     (13UL)         /*!< SPTEFC (Bit 13)                                       */
+ #define R_SPI0_SPSRC_SPTEFC_Msk     (0x2000UL)     /*!< SPTEFC (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPSRC_CENDFC_Pos     (14UL)         /*!< CENDFC (Bit 14)                                       */
+ #define R_SPI0_SPSRC_CENDFC_Msk     (0x4000UL)     /*!< CENDFC (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPSRC_SPRFC_Pos      (15UL)         /*!< SPRFC (Bit 15)                                        */
+ #define R_SPI0_SPSRC_SPRFC_Msk      (0x8000UL)     /*!< SPRFC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPFCR  ========================================================= */
+ #define R_SPI0_SPFCR_SPFRST_Pos     (0UL)          /*!< SPFRST (Bit 0)                                        */
+ #define R_SPI0_SPFCR_SPFRST_Msk     (0x1UL)        /*!< SPFRST (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ADC122                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ADCSR  ========================================================= */
+ #define R_ADC122_ADCSR_DBLANS_Pos          (0UL)      /*!< DBLANS (Bit 0)                                        */
+ #define R_ADC122_ADCSR_DBLANS_Msk          (0x1fUL)   /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
+ #define R_ADC122_ADCSR_GBADIE_Pos          (6UL)      /*!< GBADIE (Bit 6)                                        */
+ #define R_ADC122_ADCSR_GBADIE_Msk          (0x40UL)   /*!< GBADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC122_ADCSR_DBLE_Pos            (7UL)      /*!< DBLE (Bit 7)                                          */
+ #define R_ADC122_ADCSR_DBLE_Msk            (0x80UL)   /*!< DBLE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC122_ADCSR_EXTRG_Pos           (8UL)      /*!< EXTRG (Bit 8)                                         */
+ #define R_ADC122_ADCSR_EXTRG_Msk           (0x100UL)  /*!< EXTRG (Bitfield-Mask: 0x01)                           */
+ #define R_ADC122_ADCSR_TRGE_Pos            (9UL)      /*!< TRGE (Bit 9)                                          */
+ #define R_ADC122_ADCSR_TRGE_Msk            (0x200UL)  /*!< TRGE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC122_ADCSR_ADIE_Pos            (12UL)     /*!< ADIE (Bit 12)                                         */
+ #define R_ADC122_ADCSR_ADIE_Msk            (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC122_ADCSR_ADCS_Pos            (13UL)     /*!< ADCS (Bit 13)                                         */
+ #define R_ADC122_ADCSR_ADCS_Msk            (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03)                            */
+ #define R_ADC122_ADCSR_ADST_Pos            (15UL)     /*!< ADST (Bit 15)                                         */
+ #define R_ADC122_ADCSR_ADST_Msk            (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADANSA0  ======================================================== */
+ #define R_ADC122_ADANSA0_ANSA0_Pos         (0UL)      /*!< ANSA0 (Bit 0)                                         */
+ #define R_ADC122_ADANSA0_ANSA0_Msk         (0xffffUL) /*!< ANSA0 (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADADS0  ========================================================= */
+ #define R_ADC122_ADADS0_ADS0_Pos           (0UL)      /*!< ADS0 (Bit 0)                                          */
+ #define R_ADC122_ADADS0_ADS0_Msk           (0xffffUL) /*!< ADS0 (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  ADADC  ========================================================= */
+ #define R_ADC122_ADADC_ADC_Pos             (0UL)      /*!< ADC (Bit 0)                                           */
+ #define R_ADC122_ADADC_ADC_Msk             (0x7UL)    /*!< ADC (Bitfield-Mask: 0x07)                             */
+ #define R_ADC122_ADADC_AVEE_Pos            (7UL)      /*!< AVEE (Bit 7)                                          */
+ #define R_ADC122_ADADC_AVEE_Msk            (0x80UL)   /*!< AVEE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADCER  ========================================================= */
+ #define R_ADC122_ADCER_ADPRC_Pos           (1UL)      /*!< ADPRC (Bit 1)                                         */
+ #define R_ADC122_ADCER_ADPRC_Msk           (0x6UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
+ #define R_ADC122_ADCER_ACE_Pos             (5UL)      /*!< ACE (Bit 5)                                           */
+ #define R_ADC122_ADCER_ACE_Msk             (0x20UL)   /*!< ACE (Bitfield-Mask: 0x01)                             */
+ #define R_ADC122_ADCER_ADRFMT_Pos          (15UL)     /*!< ADRFMT (Bit 15)                                       */
+ #define R_ADC122_ADCER_ADRFMT_Msk          (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADSTRGR  ======================================================== */
+ #define R_ADC122_ADSTRGR_TRSB_Pos          (0UL)      /*!< TRSB (Bit 0)                                          */
+ #define R_ADC122_ADSTRGR_TRSB_Msk          (0x3fUL)   /*!< TRSB (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC122_ADSTRGR_TRSA_Pos          (8UL)      /*!< TRSA (Bit 8)                                          */
+ #define R_ADC122_ADSTRGR_TRSA_Msk          (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f)                            */
+/* ========================================================  ADANSB0  ======================================================== */
+ #define R_ADC122_ADANSB0_ANSB0_Pos         (0UL)      /*!< ANSB0 (Bit 0)                                         */
+ #define R_ADC122_ADANSB0_ANSB0_Msk         (0xffffUL) /*!< ANSB0 (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADDBLDR  ======================================================== */
+ #define R_ADC122_ADDBLDR_DBLDR_Pos         (0UL)      /*!< DBLDR (Bit 0)                                         */
+ #define R_ADC122_ADDBLDR_DBLDR_Msk         (0xffffUL) /*!< DBLDR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  ADDR  ========================================================== */
+ #define R_ADC122_ADDR_DR_Pos               (0UL)      /*!< DR (Bit 0)                                            */
+ #define R_ADC122_ADDR_DR_Msk               (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff)                            */
+/* ========================================================  ADSHCR  ========================================================= */
+ #define R_ADC122_ADSHCR_SSTSH_Pos          (0UL)      /*!< SSTSH (Bit 0)                                         */
+ #define R_ADC122_ADSHCR_SSTSH_Msk          (0xffUL)   /*!< SSTSH (Bitfield-Mask: 0xff)                           */
+ #define R_ADC122_ADSHCR_SHANS_Pos          (8UL)      /*!< SHANS (Bit 8)                                         */
+ #define R_ADC122_ADSHCR_SHANS_Msk          (0x700UL)  /*!< SHANS (Bitfield-Mask: 0x07)                           */
+/* ========================================================  ADELCCR  ======================================================== */
+ #define R_ADC122_ADELCCR_ELCC_Pos          (0UL)      /*!< ELCC (Bit 0)                                          */
+ #define R_ADC122_ADELCCR_ELCC_Msk          (0x3UL)    /*!< ELCC (Bitfield-Mask: 0x03)                            */
+ #define R_ADC122_ADELCCR_GCELC_Pos         (2UL)      /*!< GCELC (Bit 2)                                         */
+ #define R_ADC122_ADELCCR_GCELC_Msk         (0x4UL)    /*!< GCELC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADGSPCR  ======================================================== */
+ #define R_ADC122_ADGSPCR_PGS_Pos           (0UL)      /*!< PGS (Bit 0)                                           */
+ #define R_ADC122_ADGSPCR_PGS_Msk           (0x1UL)    /*!< PGS (Bitfield-Mask: 0x01)                             */
+ #define R_ADC122_ADGSPCR_GBRSCN_Pos        (1UL)      /*!< GBRSCN (Bit 1)                                        */
+ #define R_ADC122_ADGSPCR_GBRSCN_Msk        (0x2UL)    /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
+ #define R_ADC122_ADGSPCR_LGRRS_Pos         (14UL)     /*!< LGRRS (Bit 14)                                        */
+ #define R_ADC122_ADGSPCR_LGRRS_Msk         (0x4000UL) /*!< LGRRS (Bitfield-Mask: 0x01)                           */
+ #define R_ADC122_ADGSPCR_GBRP_Pos          (15UL)     /*!< GBRP (Bit 15)                                         */
+ #define R_ADC122_ADGSPCR_GBRP_Msk          (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADDBLDRA  ======================================================== */
+ #define R_ADC122_ADDBLDRA_DBLDRA_Pos       (0UL)      /*!< DBLDRA (Bit 0)                                        */
+ #define R_ADC122_ADDBLDRA_DBLDRA_Msk       (0xffffUL) /*!< DBLDRA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADDBLDRB  ======================================================== */
+ #define R_ADC122_ADDBLDRB_DBLDRB_Pos       (0UL)      /*!< DBLDRB (Bit 0)                                        */
+ #define R_ADC122_ADDBLDRB_DBLDRB_Msk       (0xffffUL) /*!< DBLDRB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADWINMON  ======================================================== */
+ #define R_ADC122_ADWINMON_MONCOMB_Pos      (0UL)      /*!< MONCOMB (Bit 0)                                       */
+ #define R_ADC122_ADWINMON_MONCOMB_Msk      (0x1UL)    /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
+ #define R_ADC122_ADWINMON_MONCMPA_Pos      (4UL)      /*!< MONCMPA (Bit 4)                                       */
+ #define R_ADC122_ADWINMON_MONCMPA_Msk      (0x10UL)   /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC122_ADWINMON_MONCMPB_Pos      (5UL)      /*!< MONCMPB (Bit 5)                                       */
+ #define R_ADC122_ADWINMON_MONCMPB_Msk      (0x20UL)   /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADCMPCR  ======================================================== */
+ #define R_ADC122_ADCMPCR_CMPAB_Pos         (0UL)      /*!< CMPAB (Bit 0)                                         */
+ #define R_ADC122_ADCMPCR_CMPAB_Msk         (0x3UL)    /*!< CMPAB (Bitfield-Mask: 0x03)                           */
+ #define R_ADC122_ADCMPCR_CMPBE_Pos         (9UL)      /*!< CMPBE (Bit 9)                                         */
+ #define R_ADC122_ADCMPCR_CMPBE_Msk         (0x200UL)  /*!< CMPBE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC122_ADCMPCR_CMPAE_Pos         (11UL)     /*!< CMPAE (Bit 11)                                        */
+ #define R_ADC122_ADCMPCR_CMPAE_Msk         (0x800UL)  /*!< CMPAE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC122_ADCMPCR_CMPBIE_Pos        (13UL)     /*!< CMPBIE (Bit 13)                                       */
+ #define R_ADC122_ADCMPCR_CMPBIE_Msk        (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC122_ADCMPCR_WCMPE_Pos         (14UL)     /*!< WCMPE (Bit 14)                                        */
+ #define R_ADC122_ADCMPCR_WCMPE_Msk         (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC122_ADCMPCR_CMPAIE_Pos        (15UL)     /*!< CMPAIE (Bit 15)                                       */
+ #define R_ADC122_ADCMPCR_CMPAIE_Msk        (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
+/* ======================================================  ADCMPANSR0  ======================================================= */
+ #define R_ADC122_ADCMPANSR0_CMPCHA0_Pos    (0UL)      /*!< CMPCHA0 (Bit 0)                                       */
+ #define R_ADC122_ADCMPANSR0_CMPCHA0_Msk    (0xffffUL) /*!< CMPCHA0 (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  ADCMPLR0  ======================================================== */
+ #define R_ADC122_ADCMPLR0_CMPLCHA0_Pos     (0UL)      /*!< CMPLCHA0 (Bit 0)                                      */
+ #define R_ADC122_ADCMPLR0_CMPLCHA0_Msk     (0xffffUL) /*!< CMPLCHA0 (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADCMPDR0  ======================================================== */
+ #define R_ADC122_ADCMPDR0_CMPLLA_Pos       (0UL)      /*!< CMPLLA (Bit 0)                                        */
+ #define R_ADC122_ADCMPDR0_CMPLLA_Msk       (0xffffUL) /*!< CMPLLA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPDR1  ======================================================== */
+ #define R_ADC122_ADCMPDR1_CMPULA_Pos       (0UL)      /*!< CMPULA (Bit 0)                                        */
+ #define R_ADC122_ADCMPDR1_CMPULA_Msk       (0xffffUL) /*!< CMPULA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPSR0  ======================================================== */
+ #define R_ADC122_ADCMPSR0_CMPSTCHA0_Pos    (0UL)      /*!< CMPSTCHA0 (Bit 0)                                     */
+ #define R_ADC122_ADCMPSR0_CMPSTCHA0_Msk    (0xffffUL) /*!< CMPSTCHA0 (Bitfield-Mask: 0xffff)                     */
+/* =======================================================  ADCMPBNSR  ======================================================= */
+ #define R_ADC122_ADCMPBNSR_CMPCHB_Pos      (0UL)      /*!< CMPCHB (Bit 0)                                        */
+ #define R_ADC122_ADCMPBNSR_CMPCHB_Msk      (0x3fUL)   /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
+ #define R_ADC122_ADCMPBNSR_CMPLB_Pos       (7UL)      /*!< CMPLB (Bit 7)                                         */
+ #define R_ADC122_ADCMPBNSR_CMPLB_Msk       (0x80UL)   /*!< CMPLB (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADWINLLB  ======================================================== */
+ #define R_ADC122_ADWINLLB_CMPLLB_Pos       (0UL)      /*!< CMPLLB (Bit 0)                                        */
+ #define R_ADC122_ADWINLLB_CMPLLB_Msk       (0xffffUL) /*!< CMPLLB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADWINULB  ======================================================== */
+ #define R_ADC122_ADWINULB_CMPULB_Pos       (0UL)      /*!< CMPULB (Bit 0)                                        */
+ #define R_ADC122_ADWINULB_CMPULB_Msk       (0xffffUL) /*!< CMPULB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPBSR  ======================================================== */
+ #define R_ADC122_ADCMPBSR_CMPSTB_Pos       (0UL)      /*!< CMPSTB (Bit 0)                                        */
+ #define R_ADC122_ADCMPBSR_CMPSTB_Msk       (0x1UL)    /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADANSC0  ======================================================== */
+ #define R_ADC122_ADANSC0_ANSC0_Pos         (0UL)      /*!< ANSC0 (Bit 0)                                         */
+ #define R_ADC122_ADANSC0_ANSC0_Msk         (0xffffUL) /*!< ANSC0 (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  ADGCTRGR  ======================================================== */
+ #define R_ADC122_ADGCTRGR_TRSC_Pos         (0UL)      /*!< TRSC (Bit 0)                                          */
+ #define R_ADC122_ADGCTRGR_TRSC_Msk         (0x3fUL)   /*!< TRSC (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC122_ADGCTRGR_GCADIE_Pos       (6UL)      /*!< GCADIE (Bit 6)                                        */
+ #define R_ADC122_ADGCTRGR_GCADIE_Msk       (0x40UL)   /*!< GCADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC122_ADGCTRGR_GRCE_Pos         (7UL)      /*!< GRCE (Bit 7)                                          */
+ #define R_ADC122_ADGCTRGR_GRCE_Msk         (0x80UL)   /*!< GRCE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADSSTR  ========================================================= */
+ #define R_ADC122_ADSSTR_SST_Pos            (0UL)      /*!< SST (Bit 0)                                           */
+ #define R_ADC122_ADSSTR_SST_Msk            (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
+/* =======================================================  ADCALCTL  ======================================================== */
+ #define R_ADC122_ADCALCTL_CAL_Pos          (0UL)      /*!< CAL (Bit 0)                                           */
+ #define R_ADC122_ADCALCTL_CAL_Msk          (0x1UL)    /*!< CAL (Bitfield-Mask: 0x01)                             */
+ #define R_ADC122_ADCALCTL_CAL_RDY_Pos      (1UL)      /*!< CAL_RDY (Bit 1)                                       */
+ #define R_ADC122_ADCALCTL_CAL_RDY_Msk      (0x2UL)    /*!< CAL_RDY (Bitfield-Mask: 0x01)                         */
+ #define R_ADC122_ADCALCTL_CAL_ERR_Pos      (2UL)      /*!< CAL_ERR (Bit 2)                                       */
+ #define R_ADC122_ADCALCTL_CAL_ERR_Msk      (0x4UL)    /*!< CAL_ERR (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CANFD                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CFDGIPV  ======================================================== */
+ #define R_CANFD_CFDGIPV_IPV_Pos                 (0UL)          /*!< IPV (Bit 0)                                           */
+ #define R_CANFD_CFDGIPV_IPV_Msk                 (0xffUL)       /*!< IPV (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDGIPV_IPT_Pos                 (8UL)          /*!< IPT (Bit 8)                                           */
+ #define R_CANFD_CFDGIPV_IPT_Msk                 (0x300UL)      /*!< IPT (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDGIPV_PSI_Pos                 (16UL)         /*!< PSI (Bit 16)                                          */
+ #define R_CANFD_CFDGIPV_PSI_Msk                 (0x3fff0000UL) /*!< PSI (Bitfield-Mask: 0x3fff)                           */
+/* ========================================================  CFDGCFG  ======================================================== */
+ #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
+ #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
+ #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
+ #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
+ #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
+ #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
+ #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
+ #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
+ #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
+ #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCFG_TSBTCS_Pos              (13UL)         /*!< TSBTCS (Bit 13)                                       */
+ #define R_CANFD_CFDGCFG_TSBTCS_Msk              (0xe000UL)     /*!< TSBTCS (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
+ #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  CFDGCTR  ======================================================== */
+ #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
+ #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
+ #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
+ #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
+ #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
+ #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
+ #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGCTR_QOWEIE_Pos              (12UL)         /*!< QOWEIE (Bit 12)                                       */
+ #define R_CANFD_CFDGCTR_QOWEIE_Msk              (0x1000UL)     /*!< QOWEIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGCTR_QMEIE_Pos               (14UL)         /*!< QMEIE (Bit 14)                                        */
+ #define R_CANFD_CFDGCTR_QMEIE_Msk               (0x4000UL)     /*!< QMEIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCTR_MOWEIE_Pos              (15UL)         /*!< MOWEIE (Bit 15)                                       */
+ #define R_CANFD_CFDGCTR_MOWEIE_Msk              (0x8000UL)     /*!< MOWEIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
+ #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CFDGSTS  ======================================================== */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
+/* =======================================================  CFDGERFL  ======================================================== */
+ #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
+ #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
+ #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
+ #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
+ #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_QOWES_Pos              (4UL)          /*!< QOWES (Bit 4)                                         */
+ #define R_CANFD_CFDGERFL_QOWES_Msk              (0x10UL)       /*!< QOWES (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_QMES_Pos               (6UL)          /*!< QMES (Bit 6)                                          */
+ #define R_CANFD_CFDGERFL_QMES_Msk               (0x40UL)       /*!< QMES (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGERFL_MOWES_Pos              (7UL)          /*!< MOWES (Bit 7)                                         */
+ #define R_CANFD_CFDGERFL_MOWES_Msk              (0x80UL)       /*!< MOWES (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CFDGTSC  ======================================================== */
+ #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
+ #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
+/* ======================================================  CFDGAFLECTR  ====================================================== */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDGAFLCFG0  ====================================================== */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  CFDRMNB  ======================================================== */
+ #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
+ #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
+ #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
+ #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
+/* =======================================================  CFDRMND0  ======================================================== */
+ #define R_CANFD_CFDRMND0_RMNS_Pos               (0UL)          /*!< RMNS (Bit 0)                                          */
+ #define R_CANFD_CFDRMND0_RMNS_Msk               (0xffffffffUL) /*!< RMNS (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  CFDRFCC  ======================================================== */
+ #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
+ #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
+ #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
+ #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
+ #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
+ #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
+ #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDRFCC_RFFIE_Pos               (16UL)         /*!< RFFIE (Bit 16)                                        */
+ #define R_CANFD_CFDRFCC_RFFIE_Msk               (0x10000UL)    /*!< RFFIE (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDRFSTS  ======================================================== */
+ #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
+ #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
+ #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
+ #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
+ #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
+ #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDRFSTS_RFFIF_Pos              (16UL)         /*!< RFFIF (Bit 16)                                        */
+ #define R_CANFD_CFDRFSTS_RFFIF_Msk              (0x10000UL)    /*!< RFFIF (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDRFPCTR  ======================================================= */
+ #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
+ #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
+/* ========================================================  CFDCFCC  ======================================================== */
+ #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
+ #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
+ #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
+ #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
+ #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
+ #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
+ #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
+ #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
+ #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
+ #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
+ #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
+ #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
+ #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDCFCCE  ======================================================== */
+ #define R_CANFD_CFDCFCCE_CFFIE_Pos              (0UL)          /*!< CFFIE (Bit 0)                                         */
+ #define R_CANFD_CFDCFCCE_CFFIE_Msk              (0x1UL)        /*!< CFFIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos           (1UL)          /*!< CFOFRXIE (Bit 1)                                      */
+ #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk           (0x2UL)        /*!< CFOFRXIE (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos           (2UL)          /*!< CFOFTXIE (Bit 2)                                      */
+ #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk           (0x4UL)        /*!< CFOFTXIE (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCFCCE_CFMOWM_Pos             (8UL)          /*!< CFMOWM (Bit 8)                                        */
+ #define R_CANFD_CFDCFCCE_CFMOWM_Msk             (0x100UL)      /*!< CFMOWM (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCCE_CFBME_Pos              (16UL)         /*!< CFBME (Bit 16)                                        */
+ #define R_CANFD_CFDCFCCE_CFBME_Msk              (0x10000UL)    /*!< CFBME (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDCFSTS  ======================================================== */
+ #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
+ #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
+ #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
+ #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
+ #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDCFSTS_CFFIF_Pos              (16UL)         /*!< CFFIF (Bit 16)                                        */
+ #define R_CANFD_CFDCFSTS_CFFIF_Msk              (0x10000UL)    /*!< CFFIF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos           (17UL)         /*!< CFOFRXIF (Bit 17)                                     */
+ #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk           (0x20000UL)    /*!< CFOFRXIF (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos           (18UL)         /*!< CFOFTXIF (Bit 18)                                     */
+ #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk           (0x40000UL)    /*!< CFOFTXIF (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCFSTS_CFMOW_Pos              (24UL)         /*!< CFMOW (Bit 24)                                        */
+ #define R_CANFD_CFDCFSTS_CFMOW_Msk              (0x1000000UL)  /*!< CFMOW (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDCFPCTR  ======================================================= */
+ #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
+ #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
+/* =======================================================  CFDFESTS  ======================================================== */
+ #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
+ #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0xffUL)       /*!< RFXEMP (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
+ #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x3f00UL)     /*!< CFXEMP (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CFDFFSTS  ======================================================== */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0xffUL)       /*!< RFXFLL (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x3f00UL)     /*!< CFXFLL (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CFDFMSTS  ======================================================== */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0xffUL)       /*!< RFXMLT (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x3f00UL)     /*!< CFXMLT (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CFDRFISTS  ======================================================= */
+ #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
+ #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0xffUL)       /*!< RFXIF (Bitfield-Mask: 0xff)                           */
+ #define R_CANFD_CFDRFISTS_RFXFFLL_Pos           (16UL)         /*!< RFXFFLL (Bit 16)                                      */
+ #define R_CANFD_CFDRFISTS_RFXFFLL_Msk           (0xff0000UL)   /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
+/* ======================================================  CFDCFRISTS  ======================================================= */
+ #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos          (0UL)          /*!< CFXRXIF (Bit 0)                                       */
+ #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk          (0x3fUL)       /*!< CFXRXIF (Bitfield-Mask: 0x3f)                         */
+/* ======================================================  CFDCFTISTS  ======================================================= */
+ #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos          (0UL)          /*!< CFXTXIF (Bit 0)                                       */
+ #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk          (0x3fUL)       /*!< CFXTXIF (Bitfield-Mask: 0x3f)                         */
+/* =====================================================  CFDCFOFRISTS  ====================================================== */
+ #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos      (0UL)          /*!< CFXOFRXIF (Bit 0)                                     */
+ #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk      (0x3fUL)       /*!< CFXOFRXIF (Bitfield-Mask: 0x3f)                       */
+/* =====================================================  CFDCFOFTISTS  ====================================================== */
+ #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos      (0UL)          /*!< CFXOFTXIF (Bit 0)                                     */
+ #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk      (0x3fUL)       /*!< CFXOFTXIF (Bitfield-Mask: 0x3f)                       */
+/* ======================================================  CFDCFMOWSTS  ====================================================== */
+ #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos          (0UL)          /*!< CFXMOW (Bit 0)                                        */
+ #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk          (0x3fUL)       /*!< CFXMOW (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CFDFFFSTS  ======================================================= */
+ #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos           (0UL)          /*!< RFXFFLL (Bit 0)                                       */
+ #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk           (0xffUL)       /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
+ #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos           (8UL)          /*!< CFXFFLL (Bit 8)                                       */
+ #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk           (0x3f00UL)     /*!< CFXFFLL (Bitfield-Mask: 0x3f)                         */
+/* ========================================================  CFDTMC  ========================================================= */
+ #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
+ #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
+ #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
+ #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFDTMSTS  ======================================================== */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
+ #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
+ #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
+ #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTMTRSTS  ======================================================= */
+ #define R_CANFD_CFDTMTRSTS_TMTRSTS_Pos          (0UL)          /*!< TMTRSTS (Bit 0)                                       */
+ #define R_CANFD_CFDTMTRSTS_TMTRSTS_Msk          (0xffffUL)     /*!< TMTRSTS (Bitfield-Mask: 0xffff)                       */
+/* ======================================================  CFDTMTARSTS  ====================================================== */
+ #define R_CANFD_CFDTMTARSTS_TMTARSTS_Pos        (0UL)          /*!< TMTARSTS (Bit 0)                                      */
+ #define R_CANFD_CFDTMTARSTS_TMTARSTS_Msk        (0xffffUL)     /*!< TMTARSTS (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  CFDTMTCSTS  ======================================================= */
+ #define R_CANFD_CFDTMTCSTS_TMTCSTS_Pos          (0UL)          /*!< TMTCSTS (Bit 0)                                       */
+ #define R_CANFD_CFDTMTCSTS_TMTCSTS_Msk          (0xffffUL)     /*!< TMTCSTS (Bitfield-Mask: 0xffff)                       */
+/* ======================================================  CFDTMTASTS  ======================================================= */
+ #define R_CANFD_CFDTMTASTS_TMTASTS_Pos          (0UL)          /*!< TMTASTS (Bit 0)                                       */
+ #define R_CANFD_CFDTMTASTS_TMTASTS_Msk          (0xffffUL)     /*!< TMTASTS (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  CFDTMIEC  ======================================================== */
+ #define R_CANFD_CFDTMIEC_TMIE_Pos               (0UL)          /*!< TMIE (Bit 0)                                          */
+ #define R_CANFD_CFDTMIEC_TMIE_Msk               (0xffffUL)     /*!< TMIE (Bitfield-Mask: 0xffff)                          */
+/* =======================================================  CFDTXQCC0  ======================================================= */
+ #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC0_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
+ #define R_CANFD_CFDTXQCC0_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC0_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
+ #define R_CANFD_CFDTXQCC0_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDTXQCC0_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
+ #define R_CANFD_CFDTXQCC0_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
+ #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
+ #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDTXQSTS0  ======================================================= */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+ #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
+ #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
+ #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTXQPCTR0  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDTXQCC1  ======================================================= */
+ #define R_CANFD_CFDTXQCC1_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC1_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC1_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
+ #define R_CANFD_CFDTXQCC1_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC1_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
+ #define R_CANFD_CFDTXQCC1_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC1_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC1_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC1_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC1_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDTXQCC1_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
+ #define R_CANFD_CFDTXQCC1_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
+ #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
+ #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDTXQSTS1  ======================================================= */
+ #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS1_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS1_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+ #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
+ #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
+ #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
+ #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
+ #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS1_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
+ #define R_CANFD_CFDTXQSTS1_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTXQPCTR1  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDTXQCC2  ======================================================= */
+ #define R_CANFD_CFDTXQCC2_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC2_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC2_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
+ #define R_CANFD_CFDTXQCC2_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC2_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
+ #define R_CANFD_CFDTXQCC2_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC2_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC2_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC2_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC2_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDTXQCC2_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
+ #define R_CANFD_CFDTXQCC2_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
+ #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
+ #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDTXQSTS2  ======================================================= */
+ #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS2_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS2_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+ #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
+ #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
+ #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
+ #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
+ #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS2_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
+ #define R_CANFD_CFDTXQSTS2_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTXQPCTR2  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDTXQCC3  ======================================================= */
+ #define R_CANFD_CFDTXQCC3_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC3_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC3_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
+ #define R_CANFD_CFDTXQCC3_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC3_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC3_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC3_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC3_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
+ #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDTXQSTS3  ======================================================= */
+ #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS3_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS3_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+ #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
+ #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDTXQSTS3_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
+ #define R_CANFD_CFDTXQSTS3_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTXQPCTR3  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* ======================================================  CFDTXQESTS  ======================================================= */
+ #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos          (0UL)          /*!< TXQxEMP (Bit 0)                                       */
+ #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk          (0xffUL)       /*!< TXQxEMP (Bitfield-Mask: 0xff)                         */
+/* ======================================================  CFDTXQFISTS  ====================================================== */
+ #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos        (0UL)          /*!< TXQ0FULL (Bit 0)                                      */
+ #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk        (0x7UL)        /*!< TXQ0FULL (Bitfield-Mask: 0x07)                        */
+ #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos        (4UL)          /*!< TXQ1FULL (Bit 4)                                      */
+ #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk        (0x70UL)       /*!< TXQ1FULL (Bitfield-Mask: 0x07)                        */
+/* ======================================================  CFDTXQMSTS  ======================================================= */
+ #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos           (0UL)          /*!< TXQ0ML (Bit 0)                                        */
+ #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk           (0x7UL)        /*!< TXQ0ML (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos           (4UL)          /*!< TXQ1ML (Bit 4)                                        */
+ #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk           (0x70UL)       /*!< TXQ1ML (Bitfield-Mask: 0x07)                          */
+/* ======================================================  CFDTXQISTS  ======================================================= */
+ #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos          (0UL)          /*!< TXQ0ISF (Bit 0)                                       */
+ #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk          (0xfUL)        /*!< TXQ0ISF (Bitfield-Mask: 0x0f)                         */
+ #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos          (4UL)          /*!< TXQ1ISF (Bit 4)                                       */
+ #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk          (0xf0UL)       /*!< TXQ1ISF (Bitfield-Mask: 0x0f)                         */
+/* =====================================================  CFDTXQOFTISTS  ===================================================== */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos    (0UL)          /*!< TXQ0OFTISF (Bit 0)                                    */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk    (0xfUL)        /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f)                      */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos    (4UL)          /*!< TXQ1OFTISF (Bit 4)                                    */
+ #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk    (0xf0UL)       /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  CFDTXQOFRISTS  ===================================================== */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos    (0UL)          /*!< TXQ0OFRISF (Bit 0)                                    */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk    (0x7UL)        /*!< TXQ0OFRISF (Bitfield-Mask: 0x07)                      */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos    (4UL)          /*!< TXQ1OFRISF (Bit 4)                                    */
+ #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk    (0x70UL)       /*!< TXQ1OFRISF (Bitfield-Mask: 0x07)                      */
+/* ======================================================  CFDTXQFSTS  ======================================================= */
+ #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos          (0UL)          /*!< TXQ0FSF (Bit 0)                                       */
+ #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk          (0xfUL)        /*!< TXQ0FSF (Bitfield-Mask: 0x0f)                         */
+ #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos          (4UL)          /*!< TXQ1FSF (Bit 4)                                       */
+ #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk          (0xf0UL)       /*!< TXQ1FSF (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  CFDTHLCC  ======================================================== */
+ #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
+ #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
+ #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
+ #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
+ #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLCC_THLDGE_Pos             (11UL)         /*!< THLDGE (Bit 11)                                       */
+ #define R_CANFD_CFDTHLCC_THLDGE_Msk             (0x800UL)      /*!< THLDGE (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDTHLSTS  ======================================================= */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
+ #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
+ #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
+ #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
+/* ======================================================  CFDTHLPCTR  ======================================================= */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
+/* =====================================================  CFDGTINTSTS0  ====================================================== */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos        (5UL)          /*!< TQOFIF0 (Bit 5)                                       */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk        (0x20UL)       /*!< TQOFIF0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos        (6UL)          /*!< CFOTIF0 (Bit 6)                                       */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk        (0x40UL)       /*!< CFOTIF0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos          (8UL)          /*!< TSIF1 (Bit 8)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk          (0x100UL)      /*!< TSIF1 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos          (9UL)          /*!< TAIF1 (Bit 9)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk          (0x200UL)      /*!< TAIF1 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos          (10UL)         /*!< TQIF1 (Bit 10)                                        */
+ #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk          (0x400UL)      /*!< TQIF1 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos         (11UL)         /*!< CFTIF1 (Bit 11)                                       */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk         (0x800UL)      /*!< CFTIF1 (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGTINTSTS0_THIF1_Pos          (12UL)         /*!< THIF1 (Bit 12)                                        */
+ #define R_CANFD_CFDGTINTSTS0_THIF1_Msk          (0x1000UL)     /*!< THIF1 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos        (13UL)         /*!< TQOFIF1 (Bit 13)                                      */
+ #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk        (0x2000UL)     /*!< TQOFIF1 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos        (14UL)         /*!< CFOTIF1 (Bit 14)                                      */
+ #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk        (0x4000UL)     /*!< CFOTIF1 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  CFDGTSTCFG  ======================================================= */
+ #define R_CANFD_CFDGTSTCFG_C0ICBCE_Pos          (0UL)          /*!< C0ICBCE (Bit 0)                                       */
+ #define R_CANFD_CFDGTSTCFG_C0ICBCE_Msk          (0x1UL)        /*!< C0ICBCE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTSTCFG_C1ICBCE_Pos          (1UL)          /*!< C1ICBCE (Bit 1)                                       */
+ #define R_CANFD_CFDGTSTCFG_C1ICBCE_Msk          (0x2UL)        /*!< C1ICBCE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
+/* ======================================================  CFDGTSTCTR  ======================================================= */
+ #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos          (0UL)          /*!< ICBCTME (Bit 0)                                       */
+ #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk          (0x1UL)        /*!< ICBCTME (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
+ #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFDGFDCFG  ======================================================= */
+ #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
+ #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
+/* =======================================================  CFDGLOCKK  ======================================================= */
+ #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
+ #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
+/* =======================================================  CFDCDTCT  ======================================================== */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE2_Pos            (2UL)          /*!< RFDMAE2 (Bit 2)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE2_Msk            (0x4UL)        /*!< RFDMAE2 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE3_Pos            (3UL)          /*!< RFDMAE3 (Bit 3)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE3_Msk            (0x8UL)        /*!< RFDMAE3 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE4_Pos            (4UL)          /*!< RFDMAE4 (Bit 4)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE4_Msk            (0x10UL)       /*!< RFDMAE4 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE5_Pos            (5UL)          /*!< RFDMAE5 (Bit 5)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE5_Msk            (0x20UL)       /*!< RFDMAE5 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE6_Pos            (6UL)          /*!< RFDMAE6 (Bit 6)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE6_Msk            (0x40UL)       /*!< RFDMAE6 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE7_Pos            (7UL)          /*!< RFDMAE7 (Bit 7)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE7_Msk            (0x80UL)       /*!< RFDMAE7 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_CFDMAE1_Pos            (9UL)          /*!< CFDMAE1 (Bit 9)                                       */
+ #define R_CANFD_CFDCDTCT_CFDMAE1_Msk            (0x200UL)      /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  CFDCDTSTS  ======================================================= */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos         (2UL)          /*!< RFDMASTS2 (Bit 2)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk         (0x4UL)        /*!< RFDMASTS2 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos         (3UL)          /*!< RFDMASTS3 (Bit 3)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk         (0x8UL)        /*!< RFDMASTS3 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos         (4UL)          /*!< RFDMASTS4 (Bit 4)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk         (0x10UL)       /*!< RFDMASTS4 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos         (5UL)          /*!< RFDMASTS5 (Bit 5)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk         (0x20UL)       /*!< RFDMASTS5 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos         (6UL)          /*!< RFDMASTS6 (Bit 6)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk         (0x40UL)       /*!< RFDMASTS6 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos         (7UL)          /*!< RFDMASTS7 (Bit 7)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk         (0x80UL)       /*!< RFDMASTS7 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos         (9UL)          /*!< CFDMASTS1 (Bit 9)                                     */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk         (0x200UL)      /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  CFDCDTTCT  ======================================================= */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos          (0UL)          /*!< TQ0DMAE0 (Bit 0)                                      */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk          (0x1UL)        /*!< TQ0DMAE0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos          (1UL)          /*!< TQ0DMAE1 (Bit 1)                                      */
+ #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk          (0x2UL)        /*!< TQ0DMAE1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos          (8UL)          /*!< TQ3DMAE0 (Bit 8)                                      */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk          (0x100UL)      /*!< TQ3DMAE0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos          (9UL)          /*!< TQ3DMAE1 (Bit 9)                                      */
+ #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk          (0x200UL)      /*!< TQ3DMAE1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos           (16UL)         /*!< CFDMAE0 (Bit 16)                                      */
+ #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk           (0x10000UL)    /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos           (17UL)         /*!< CFDMAE1 (Bit 17)                                      */
+ #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk           (0x20000UL)    /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  CFDCDTTSTS  ======================================================= */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos       (0UL)          /*!< TQ0DMASTS0 (Bit 0)                                    */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk       (0x1UL)        /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01)                      */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos       (1UL)          /*!< TQ0DMASTS1 (Bit 1)                                    */
+ #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk       (0x2UL)        /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01)                      */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos       (8UL)          /*!< TQ3DMASTS0 (Bit 8)                                    */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk       (0x100UL)      /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01)                      */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos       (9UL)          /*!< TQ3DMASTS1 (Bit 9)                                    */
+ #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk       (0x200UL)      /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01)                      */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos        (16UL)         /*!< CFDMASTS0 (Bit 16)                                    */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk        (0x10000UL)    /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos        (17UL)         /*!< CFDMASTS1 (Bit 17)                                    */
+ #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk        (0x20000UL)    /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
+/* ======================================================  CFDGRINTSTS  ====================================================== */
+ #define R_CANFD_CFDGRINTSTS_QFIF_Pos            (0UL)          /*!< QFIF (Bit 0)                                          */
+ #define R_CANFD_CFDGRINTSTS_QFIF_Msk            (0x7UL)        /*!< QFIF (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDGRINTSTS_BQFIF_Pos           (4UL)          /*!< BQFIF (Bit 4)                                         */
+ #define R_CANFD_CFDGRINTSTS_BQFIF_Msk           (0x30UL)       /*!< BQFIF (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos          (8UL)          /*!< QOFRIF (Bit 8)                                        */
+ #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk          (0x700UL)      /*!< QOFRIF (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDGRINTSTS_BQOFRIF_Pos         (12UL)         /*!< BQOFRIF (Bit 12)                                      */
+ #define R_CANFD_CFDGRINTSTS_BQOFRIF_Msk         (0x3000UL)     /*!< BQOFRIF (Bitfield-Mask: 0x03)                         */
+ #define R_CANFD_CFDGRINTSTS_CFRIF_Pos           (16UL)         /*!< CFRIF (Bit 16)                                        */
+ #define R_CANFD_CFDGRINTSTS_CFRIF_Msk           (0x70000UL)    /*!< CFRIF (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos          (24UL)         /*!< CFRFIF (Bit 24)                                       */
+ #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk          (0x7000000UL)  /*!< CFRFIF (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos         (28UL)         /*!< CFOFRIF (Bit 28)                                      */
+ #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk         (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07)                         */
+/* =======================================================  CFDGRSTC  ======================================================== */
+ #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
+ #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* =======================================================  CFDGFCMC  ======================================================== */
+ #define R_CANFD_CFDGFCMC_FLXC0_Pos              (0UL)          /*!< FLXC0 (Bit 0)                                         */
+ #define R_CANFD_CFDGFCMC_FLXC0_Msk              (0x1UL)        /*!< FLXC0 (Bitfield-Mask: 0x01)                           */
+/* =======================================================  CFDGFTBAC  ======================================================= */
+ #define R_CANFD_CFDGFTBAC_FLXMB0_Pos            (0UL)          /*!< FLXMB0 (Bit 0)                                        */
+ #define R_CANFD_CFDGFTBAC_FLXMB0_Msk            (0xfUL)        /*!< FLXMB0 (Bitfield-Mask: 0x0f)                          */
+/* =======================================================  CFDRPGACC  ======================================================= */
+ #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
+ #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CMT                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CMTW0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CMWSTR  ========================================================= */
+ #define R_CMTW0_CMWSTR_STR_Pos     (0UL)      /*!< STR (Bit 0)                                           */
+ #define R_CMTW0_CMWSTR_STR_Msk     (0x1UL)    /*!< STR (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CMWCR  ========================================================= */
+ #define R_CMTW0_CMWCR_CKS_Pos      (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_CMTW0_CMWCR_CKS_Msk      (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWCR_CMWIE_Pos    (3UL)      /*!< CMWIE (Bit 3)                                         */
+ #define R_CMTW0_CMWCR_CMWIE_Msk    (0x8UL)    /*!< CMWIE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_IC0IE_Pos    (4UL)      /*!< IC0IE (Bit 4)                                         */
+ #define R_CMTW0_CMWCR_IC0IE_Msk    (0x10UL)   /*!< IC0IE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_IC1IE_Pos    (5UL)      /*!< IC1IE (Bit 5)                                         */
+ #define R_CMTW0_CMWCR_IC1IE_Msk    (0x20UL)   /*!< IC1IE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_OC0IE_Pos    (6UL)      /*!< OC0IE (Bit 6)                                         */
+ #define R_CMTW0_CMWCR_OC0IE_Msk    (0x40UL)   /*!< OC0IE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_OC1IE_Pos    (7UL)      /*!< OC1IE (Bit 7)                                         */
+ #define R_CMTW0_CMWCR_OC1IE_Msk    (0x80UL)   /*!< OC1IE (Bitfield-Mask: 0x01)                           */
+ #define R_CMTW0_CMWCR_CMS_Pos      (9UL)      /*!< CMS (Bit 9)                                           */
+ #define R_CMTW0_CMWCR_CMS_Msk      (0x200UL)  /*!< CMS (Bitfield-Mask: 0x01)                             */
+ #define R_CMTW0_CMWCR_CCLR_Pos     (13UL)     /*!< CCLR (Bit 13)                                         */
+ #define R_CMTW0_CMWCR_CCLR_Msk     (0xe000UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* ========================================================  CMWIOR  ========================================================= */
+ #define R_CMTW0_CMWIOR_IC0_Pos     (0UL)      /*!< IC0 (Bit 0)                                           */
+ #define R_CMTW0_CMWIOR_IC0_Msk     (0x3UL)    /*!< IC0 (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWIOR_IC1_Pos     (2UL)      /*!< IC1 (Bit 2)                                           */
+ #define R_CMTW0_CMWIOR_IC1_Msk     (0xcUL)    /*!< IC1 (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWIOR_IC0E_Pos    (4UL)      /*!< IC0E (Bit 4)                                          */
+ #define R_CMTW0_CMWIOR_IC0E_Msk    (0x10UL)   /*!< IC0E (Bitfield-Mask: 0x01)                            */
+ #define R_CMTW0_CMWIOR_IC1E_Pos    (5UL)      /*!< IC1E (Bit 5)                                          */
+ #define R_CMTW0_CMWIOR_IC1E_Msk    (0x20UL)   /*!< IC1E (Bitfield-Mask: 0x01)                            */
+ #define R_CMTW0_CMWIOR_OC0_Pos     (8UL)      /*!< OC0 (Bit 8)                                           */
+ #define R_CMTW0_CMWIOR_OC0_Msk     (0x300UL)  /*!< OC0 (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWIOR_OC1_Pos     (10UL)     /*!< OC1 (Bit 10)                                          */
+ #define R_CMTW0_CMWIOR_OC1_Msk     (0xc00UL)  /*!< OC1 (Bitfield-Mask: 0x03)                             */
+ #define R_CMTW0_CMWIOR_OC0E_Pos    (12UL)     /*!< OC0E (Bit 12)                                         */
+ #define R_CMTW0_CMWIOR_OC0E_Msk    (0x1000UL) /*!< OC0E (Bitfield-Mask: 0x01)                            */
+ #define R_CMTW0_CMWIOR_OC1E_Pos    (13UL)     /*!< OC1E (Bit 13)                                         */
+ #define R_CMTW0_CMWIOR_OC1E_Msk    (0x2000UL) /*!< OC1E (Bitfield-Mask: 0x01)                            */
+ #define R_CMTW0_CMWIOR_CMWE_Pos    (15UL)     /*!< CMWE (Bit 15)                                         */
+ #define R_CMTW0_CMWIOR_CMWE_Msk    (0x8000UL) /*!< CMWE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CMWCNT  ========================================================= */
+/* ========================================================  CMWCOR  ========================================================= */
+/* ========================================================  CMWICR0  ======================================================== */
+/* ========================================================  CMWICR1  ======================================================== */
+/* ========================================================  CMWOCR0  ======================================================== */
+/* ========================================================  CMWOCR1  ======================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_WDT0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  WDTRR  ========================================================= */
+/* =========================================================  WDTCR  ========================================================= */
+ #define R_WDT0_WDTCR_TOPS_Pos        (0UL)      /*!< TOPS (Bit 0)                                          */
+ #define R_WDT0_WDTCR_TOPS_Msk        (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
+ #define R_WDT0_WDTCR_CKS_Pos         (4UL)      /*!< CKS (Bit 4)                                           */
+ #define R_WDT0_WDTCR_CKS_Msk         (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
+ #define R_WDT0_WDTCR_RPES_Pos        (8UL)      /*!< RPES (Bit 8)                                          */
+ #define R_WDT0_WDTCR_RPES_Msk        (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
+ #define R_WDT0_WDTCR_RPSS_Pos        (12UL)     /*!< RPSS (Bit 12)                                         */
+ #define R_WDT0_WDTCR_RPSS_Msk        (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  WDTSR  ========================================================= */
+ #define R_WDT0_WDTSR_CNTVAL_Pos      (0UL)      /*!< CNTVAL (Bit 0)                                        */
+ #define R_WDT0_WDTSR_CNTVAL_Msk      (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
+ #define R_WDT0_WDTSR_UNDFF_Pos       (14UL)     /*!< UNDFF (Bit 14)                                        */
+ #define R_WDT0_WDTSR_UNDFF_Msk       (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
+ #define R_WDT0_WDTSR_REFEF_Pos       (15UL)     /*!< REFEF (Bit 15)                                        */
+ #define R_WDT0_WDTSR_REFEF_Msk       (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  WDTRCR  ========================================================= */
+ #define R_WDT0_WDTRCR_RSTIRQS_Pos    (7UL)      /*!< RSTIRQS (Bit 7)                                       */
+ #define R_WDT0_WDTRCR_RSTIRQS_Msk    (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DOCR  ========================================================== */
+ #define R_DOC_DOCR_OMS_Pos        (0UL)    /*!< OMS (Bit 0)                                           */
+ #define R_DOC_DOCR_OMS_Msk        (0x3UL)  /*!< OMS (Bitfield-Mask: 0x03)                             */
+ #define R_DOC_DOCR_DCSEL_Pos      (2UL)    /*!< DCSEL (Bit 2)                                         */
+ #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)  /*!< DCSEL (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_DOPCIE_Pos     (4UL)    /*!< DOPCIE (Bit 4)                                        */
+ #define R_DOC_DOCR_DOPCIE_Msk     (0x10UL) /*!< DOPCIE (Bitfield-Mask: 0x01)                          */
+ #define R_DOC_DOCR_DOPCF_Pos      (5UL)    /*!< DOPCF (Bit 5)                                         */
+ #define R_DOC_DOCR_DOPCF_Msk      (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)    /*!< DOPCFCL (Bit 6)                                       */
+ #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
+/* =========================================================  DODIR  ========================================================= */
+/* =========================================================  DODSR  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                         R_TSU_B0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SSUSR  ========================================================= */
+ #define R_TSU_B0_SSUSR_EN_TS_Pos         (0UL)     /*!< EN_TS (Bit 0)                                         */
+ #define R_TSU_B0_SSUSR_EN_TS_Msk         (0x1UL)   /*!< EN_TS (Bitfield-Mask: 0x01)                           */
+ #define R_TSU_B0_SSUSR_ADC_PD_Pos        (1UL)     /*!< ADC_PD (Bit 1)                                        */
+ #define R_TSU_B0_SSUSR_ADC_PD_Msk        (0x2UL)   /*!< ADC_PD (Bitfield-Mask: 0x01)                          */
+ #define R_TSU_B0_SSUSR_SOC_TS_EN_Pos     (2UL)     /*!< SOC_TS_EN (Bit 2)                                     */
+ #define R_TSU_B0_SSUSR_SOC_TS_EN_Msk     (0x4UL)   /*!< SOC_TS_EN (Bitfield-Mask: 0x01)                       */
+/* =========================================================  STRGR  ========================================================= */
+ #define R_TSU_B0_STRGR_ADST_Pos          (0UL)     /*!< ADST (Bit 0)                                          */
+ #define R_TSU_B0_STRGR_ADST_Msk          (0x1UL)   /*!< ADST (Bitfield-Mask: 0x01)                            */
+ #define R_TSU_B0_STRGR_ADEND_Pos         (1UL)     /*!< ADEND (Bit 1)                                         */
+ #define R_TSU_B0_STRGR_ADEND_Msk         (0x2UL)   /*!< ADEND (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SOSR1  ========================================================= */
+ #define R_TSU_B0_SOSR1_ADCT_Pos          (0UL)     /*!< ADCT (Bit 0)                                          */
+ #define R_TSU_B0_SOSR1_ADCT_Msk          (0x3UL)   /*!< ADCT (Bitfield-Mask: 0x03)                            */
+ #define R_TSU_B0_SOSR1_ADCS_Pos          (4UL)     /*!< ADCS (Bit 4)                                          */
+ #define R_TSU_B0_SOSR1_ADCS_Msk          (0x10UL)  /*!< ADCS (Bitfield-Mask: 0x01)                            */
+ #define R_TSU_B0_SOSR1_OUTSEL_Pos        (9UL)     /*!< OUTSEL (Bit 9)                                        */
+ #define R_TSU_B0_SOSR1_OUTSEL_Msk        (0x200UL) /*!< OUTSEL (Bitfield-Mask: 0x01)                          */
+/* =========================================================  SCRR  ========================================================== */
+ #define R_TSU_B0_SCRR_OUT12BIT_TS_Pos    (0UL)     /*!< OUT12BIT_TS (Bit 0)                                   */
+ #define R_TSU_B0_SCRR_OUT12BIT_TS_Msk    (0xfffUL) /*!< OUT12BIT_TS (Bitfield-Mask: 0xfff)                    */
+/* ==========================================================  SSR  ========================================================== */
+ #define R_TSU_B0_SSR_CONV_Pos            (0UL)     /*!< CONV (Bit 0)                                          */
+ #define R_TSU_B0_SSR_CONV_Msk            (0x1UL)   /*!< CONV (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CMSR  ========================================================== */
+ #define R_TSU_B0_CMSR_CMPEN_Pos          (0UL)     /*!< CMPEN (Bit 0)                                         */
+ #define R_TSU_B0_CMSR_CMPEN_Msk          (0x1UL)   /*!< CMPEN (Bitfield-Mask: 0x01)                           */
+ #define R_TSU_B0_CMSR_CMPCOND_Pos        (1UL)     /*!< CMPCOND (Bit 1)                                       */
+ #define R_TSU_B0_CMSR_CMPCOND_Msk        (0x2UL)   /*!< CMPCOND (Bitfield-Mask: 0x01)                         */
+/* =========================================================  LLSR  ========================================================== */
+ #define R_TSU_B0_LLSR_LLIM_Pos           (0UL)     /*!< LLIM (Bit 0)                                          */
+ #define R_TSU_B0_LLSR_LLIM_Msk           (0xfffUL) /*!< LLIM (Bitfield-Mask: 0xfff)                           */
+/* =========================================================  ULSR  ========================================================== */
+ #define R_TSU_B0_ULSR_ULIM_Pos           (0UL)     /*!< ULIM (Bit 0)                                          */
+ #define R_TSU_B0_ULSR_ULIM_Msk           (0xfffUL) /*!< ULIM (Bitfield-Mask: 0xfff)                           */
+/* =========================================================  SISR  ========================================================== */
+ #define R_TSU_B0_SISR_ADF_Pos            (0UL)     /*!< ADF (Bit 0)                                           */
+ #define R_TSU_B0_SISR_ADF_Msk            (0x1UL)   /*!< ADF (Bitfield-Mask: 0x01)                             */
+ #define R_TSU_B0_SISR_CMPF_Pos           (1UL)     /*!< CMPF (Bit 1)                                          */
+ #define R_TSU_B0_SISR_CMPF_Msk           (0x2UL)   /*!< CMPF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SIER  ========================================================== */
+ #define R_TSU_B0_SIER_ADIE_Pos           (0UL)     /*!< ADIE (Bit 0)                                          */
+ #define R_TSU_B0_SIER_ADIE_Msk           (0x1UL)   /*!< ADIE (Bitfield-Mask: 0x01)                            */
+ #define R_TSU_B0_SIER_CMPIE_Pos          (1UL)     /*!< CMPIE (Bit 1)                                         */
+ #define R_TSU_B0_SIER_CMPIE_Msk          (0x2UL)   /*!< CMPIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SICR  ========================================================== */
+ #define R_TSU_B0_SICR_ADCLR_Pos          (0UL)     /*!< ADCLR (Bit 0)                                         */
+ #define R_TSU_B0_SICR_ADCLR_Msk          (0x1UL)   /*!< ADCLR (Bitfield-Mask: 0x01)                           */
+ #define R_TSU_B0_SICR_CMPCLR_Pos         (1UL)     /*!< CMPCLR (Bit 1)                                        */
+ #define R_TSU_B0_SICR_CMPCLR_Msk         (0x2UL)   /*!< CMPCLR (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG1                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  POEG1GA0  ======================================================== */
+ #define R_POEG1_POEG1GA0_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG1_POEG1GA0_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA0_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG1_POEG1GA0_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA0_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG1_POEG1GA0_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GA0_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG1_POEG1GA0_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GA0_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG1_POEG1GA0_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA0_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG1_POEG1GA0_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA0_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG1_POEG1GA0_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GA0_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG1_POEG1GA0_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG1_POEG1GA0_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG1_POEG1GA0_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GA0_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG1_POEG1GA0_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GA0_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG1_POEG1GA0_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG1GB0  ======================================================== */
+ #define R_POEG1_POEG1GB0_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG1_POEG1GB0_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB0_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG1_POEG1GB0_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB0_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG1_POEG1GB0_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GB0_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG1_POEG1GB0_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GB0_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG1_POEG1GB0_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB0_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG1_POEG1GB0_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB0_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG1_POEG1GB0_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GB0_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG1_POEG1GB0_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG1_POEG1GB0_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG1_POEG1GB0_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GB0_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG1_POEG1GB0_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GB0_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG1_POEG1GB0_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG1GC0  ======================================================== */
+ #define R_POEG1_POEG1GC0_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG1_POEG1GC0_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC0_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG1_POEG1GC0_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC0_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG1_POEG1GC0_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GC0_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG1_POEG1GC0_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GC0_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG1_POEG1GC0_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC0_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG1_POEG1GC0_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC0_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG1_POEG1GC0_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GC0_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG1_POEG1GC0_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG1_POEG1GC0_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG1_POEG1GC0_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GC0_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG1_POEG1GC0_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GC0_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG1_POEG1GC0_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG1GD0  ======================================================== */
+ #define R_POEG1_POEG1GD0_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG1_POEG1GD0_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD0_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG1_POEG1GD0_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD0_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG1_POEG1GD0_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GD0_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG1_POEG1GD0_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GD0_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG1_POEG1GD0_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD0_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG1_POEG1GD0_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD0_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG1_POEG1GD0_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG1_POEG1GD0_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG1_POEG1GD0_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG1_POEG1GD0_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG1_POEG1GD0_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG1_POEG1GD0_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG1_POEG1GD0_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG1_POEG1GD0_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG1_POEG1GD0_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ICCR1  ========================================================= */
+ #define R_IIC0_ICCR1_SDAI_Pos      (0UL)    /*!< SDAI (Bit 0)                                          */
+ #define R_IIC0_ICCR1_SDAI_Msk      (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLI_Pos      (1UL)    /*!< SCLI (Bit 1)                                          */
+ #define R_IIC0_ICCR1_SCLI_Msk      (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SDAO_Pos      (2UL)    /*!< SDAO (Bit 2)                                          */
+ #define R_IIC0_ICCR1_SDAO_Msk      (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLO_Pos      (3UL)    /*!< SCLO (Bit 3)                                          */
+ #define R_IIC0_ICCR1_SCLO_Msk      (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SOWP_Pos      (4UL)    /*!< SOWP (Bit 4)                                          */
+ #define R_IIC0_ICCR1_SOWP_Msk      (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_CLO_Pos       (5UL)    /*!< CLO (Bit 5)                                           */
+ #define R_IIC0_ICCR1_CLO_Msk       (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR1_IICRST_Pos    (6UL)    /*!< IICRST (Bit 6)                                        */
+ #define R_IIC0_ICCR1_IICRST_Msk    (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
+ #define R_IIC0_ICCR1_ICE_Pos       (7UL)    /*!< ICE (Bit 7)                                           */
+ #define R_IIC0_ICCR1_ICE_Msk       (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ICCR2  ========================================================= */
+ #define R_IIC0_ICCR2_ST_Pos        (1UL)    /*!< ST (Bit 1)                                            */
+ #define R_IIC0_ICCR2_ST_Msk        (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_RS_Pos        (2UL)    /*!< RS (Bit 2)                                            */
+ #define R_IIC0_ICCR2_RS_Msk        (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_SP_Pos        (3UL)    /*!< SP (Bit 3)                                            */
+ #define R_IIC0_ICCR2_SP_Msk        (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_TRS_Pos       (5UL)    /*!< TRS (Bit 5)                                           */
+ #define R_IIC0_ICCR2_TRS_Msk       (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_MST_Pos       (6UL)    /*!< MST (Bit 6)                                           */
+ #define R_IIC0_ICCR2_MST_Msk       (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_BBSY_Pos      (7UL)    /*!< BBSY (Bit 7)                                          */
+ #define R_IIC0_ICCR2_BBSY_Msk      (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR1  ========================================================= */
+ #define R_IIC0_ICMR1_BC_Pos        (0UL)    /*!< BC (Bit 0)                                            */
+ #define R_IIC0_ICMR1_BC_Msk        (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
+ #define R_IIC0_ICMR1_BCWP_Pos      (3UL)    /*!< BCWP (Bit 3)                                          */
+ #define R_IIC0_ICMR1_BCWP_Msk      (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR1_CKS_Pos       (4UL)    /*!< CKS (Bit 4)                                           */
+ #define R_IIC0_ICMR1_CKS_Msk       (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
+ #define R_IIC0_ICMR1_MTWP_Pos      (7UL)    /*!< MTWP (Bit 7)                                          */
+ #define R_IIC0_ICMR1_MTWP_Msk      (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR2  ========================================================= */
+ #define R_IIC0_ICMR2_TMOS_Pos      (0UL)    /*!< TMOS (Bit 0)                                          */
+ #define R_IIC0_ICMR2_TMOS_Msk      (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOL_Pos      (1UL)    /*!< TMOL (Bit 1)                                          */
+ #define R_IIC0_ICMR2_TMOL_Msk      (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOH_Pos      (2UL)    /*!< TMOH (Bit 2)                                          */
+ #define R_IIC0_ICMR2_TMOH_Msk      (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_SDDL_Pos      (4UL)    /*!< SDDL (Bit 4)                                          */
+ #define R_IIC0_ICMR2_SDDL_Msk      (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
+ #define R_IIC0_ICMR2_DLCS_Pos      (7UL)    /*!< DLCS (Bit 7)                                          */
+ #define R_IIC0_ICMR2_DLCS_Msk      (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR3  ========================================================= */
+ #define R_IIC0_ICMR3_NF_Pos        (0UL)    /*!< NF (Bit 0)                                            */
+ #define R_IIC0_ICMR3_NF_Msk        (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
+ #define R_IIC0_ICMR3_ACKBR_Pos     (2UL)    /*!< ACKBR (Bit 2)                                         */
+ #define R_IIC0_ICMR3_ACKBR_Msk     (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKBT_Pos     (3UL)    /*!< ACKBT (Bit 3)                                         */
+ #define R_IIC0_ICMR3_ACKBT_Msk     (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKWP_Pos     (4UL)    /*!< ACKWP (Bit 4)                                         */
+ #define R_IIC0_ICMR3_ACKWP_Msk     (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_RDRFS_Pos     (5UL)    /*!< RDRFS (Bit 5)                                         */
+ #define R_IIC0_ICMR3_RDRFS_Msk     (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_WAIT_Pos      (6UL)    /*!< WAIT (Bit 6)                                          */
+ #define R_IIC0_ICMR3_WAIT_Msk      (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR3_SMBS_Pos      (7UL)    /*!< SMBS (Bit 7)                                          */
+ #define R_IIC0_ICMR3_SMBS_Msk      (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICFER  ========================================================= */
+ #define R_IIC0_ICFER_TMOE_Pos      (0UL)    /*!< TMOE (Bit 0)                                          */
+ #define R_IIC0_ICFER_TMOE_Msk      (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_MALE_Pos      (1UL)    /*!< MALE (Bit 1)                                          */
+ #define R_IIC0_ICFER_MALE_Msk      (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NALE_Pos      (2UL)    /*!< NALE (Bit 2)                                          */
+ #define R_IIC0_ICFER_NALE_Msk      (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_SALE_Pos      (3UL)    /*!< SALE (Bit 3)                                          */
+ #define R_IIC0_ICFER_SALE_Msk      (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NACKE_Pos     (4UL)    /*!< NACKE (Bit 4)                                         */
+ #define R_IIC0_ICFER_NACKE_Msk     (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICFER_NFE_Pos       (5UL)    /*!< NFE (Bit 5)                                           */
+ #define R_IIC0_ICFER_NFE_Msk       (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICFER_SCLE_Pos      (6UL)    /*!< SCLE (Bit 6)                                          */
+ #define R_IIC0_ICFER_SCLE_Msk      (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSER  ========================================================= */
+ #define R_IIC0_ICSER_SAR0E_Pos     (0UL)    /*!< SAR0E (Bit 0)                                         */
+ #define R_IIC0_ICSER_SAR0E_Msk     (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR1E_Pos     (1UL)    /*!< SAR1E (Bit 1)                                         */
+ #define R_IIC0_ICSER_SAR1E_Msk     (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR2E_Pos     (2UL)    /*!< SAR2E (Bit 2)                                         */
+ #define R_IIC0_ICSER_SAR2E_Msk     (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_GCAE_Pos      (3UL)    /*!< GCAE (Bit 3)                                          */
+ #define R_IIC0_ICSER_GCAE_Msk      (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_DIDE_Pos      (5UL)    /*!< DIDE (Bit 5)                                          */
+ #define R_IIC0_ICSER_DIDE_Msk      (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_HOAE_Pos      (7UL)    /*!< HOAE (Bit 7)                                          */
+ #define R_IIC0_ICSER_HOAE_Msk      (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICIER  ========================================================= */
+ #define R_IIC0_ICIER_TMOIE_Pos     (0UL)    /*!< TMOIE (Bit 0)                                         */
+ #define R_IIC0_ICIER_TMOIE_Msk     (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICIER_ALIE_Pos      (1UL)    /*!< ALIE (Bit 1)                                          */
+ #define R_IIC0_ICIER_ALIE_Msk      (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_STIE_Pos      (2UL)    /*!< STIE (Bit 2)                                          */
+ #define R_IIC0_ICIER_STIE_Msk      (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_SPIE_Pos      (3UL)    /*!< SPIE (Bit 3)                                          */
+ #define R_IIC0_ICIER_SPIE_Msk      (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_NAKIE_Pos     (4UL)    /*!< NAKIE (Bit 4)                                         */
+ #define R_IIC0_ICIER_NAKIE_Msk     (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICIER_RIE_Pos       (5UL)    /*!< RIE (Bit 5)                                           */
+ #define R_IIC0_ICIER_RIE_Msk       (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICIER_TEIE_Pos      (6UL)    /*!< TEIE (Bit 6)                                          */
+ #define R_IIC0_ICIER_TEIE_Msk      (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_TIE_Pos       (7UL)    /*!< TIE (Bit 7)                                           */
+ #define R_IIC0_ICIER_TIE_Msk       (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ICSR1  ========================================================= */
+ #define R_IIC0_ICSR1_AAS0_Pos      (0UL)    /*!< AAS0 (Bit 0)                                          */
+ #define R_IIC0_ICSR1_AAS0_Msk      (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS1_Pos      (1UL)    /*!< AAS1 (Bit 1)                                          */
+ #define R_IIC0_ICSR1_AAS1_Msk      (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS2_Pos      (2UL)    /*!< AAS2 (Bit 2)                                          */
+ #define R_IIC0_ICSR1_AAS2_Msk      (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_GCA_Pos       (3UL)    /*!< GCA (Bit 3)                                           */
+ #define R_IIC0_ICSR1_GCA_Msk       (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_DID_Pos       (5UL)    /*!< DID (Bit 5)                                           */
+ #define R_IIC0_ICSR1_DID_Msk       (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_HOA_Pos       (7UL)    /*!< HOA (Bit 7)                                           */
+ #define R_IIC0_ICSR1_HOA_Msk       (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ICSR2  ========================================================= */
+ #define R_IIC0_ICSR2_TMOF_Pos      (0UL)    /*!< TMOF (Bit 0)                                          */
+ #define R_IIC0_ICSR2_TMOF_Msk      (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_AL_Pos        (1UL)    /*!< AL (Bit 1)                                            */
+ #define R_IIC0_ICSR2_AL_Msk        (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICSR2_START_Pos     (2UL)    /*!< START (Bit 2)                                         */
+ #define R_IIC0_ICSR2_START_Msk     (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_STOP_Pos      (3UL)    /*!< STOP (Bit 3)                                          */
+ #define R_IIC0_ICSR2_STOP_Msk      (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_NACKF_Pos     (4UL)    /*!< NACKF (Bit 4)                                         */
+ #define R_IIC0_ICSR2_NACKF_Msk     (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_RDRF_Pos      (5UL)    /*!< RDRF (Bit 5)                                          */
+ #define R_IIC0_ICSR2_RDRF_Msk      (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_TEND_Pos      (6UL)    /*!< TEND (Bit 6)                                          */
+ #define R_IIC0_ICSR2_TEND_Msk      (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_TDRE_Pos      (7UL)    /*!< TDRE (Bit 7)                                          */
+ #define R_IIC0_ICSR2_TDRE_Msk      (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICBRL  ========================================================= */
+ #define R_IIC0_ICBRL_BRL_Pos       (0UL)    /*!< BRL (Bit 0)                                           */
+ #define R_IIC0_ICBRL_BRL_Msk       (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICBRH  ========================================================= */
+ #define R_IIC0_ICBRH_BRH_Pos       (0UL)    /*!< BRH (Bit 0)                                           */
+ #define R_IIC0_ICBRH_BRH_Msk       (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICDRT  ========================================================= */
+/* =========================================================  ICDRR  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================  MAC_Configuration  =================================================== */
+ #define R_GMAC0_MAC_Configuration_RE_Pos                                   (0UL)          /*!< RE (Bit 0)                                            */
+ #define R_GMAC0_MAC_Configuration_RE_Msk                                   (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_TE_Pos                                   (1UL)          /*!< TE (Bit 1)                                            */
+ #define R_GMAC0_MAC_Configuration_TE_Msk                                   (0x2UL)        /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_PRELEN_Pos                               (2UL)          /*!< PRELEN (Bit 2)                                        */
+ #define R_GMAC0_MAC_Configuration_PRELEN_Msk                               (0xcUL)        /*!< PRELEN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_Configuration_DC_Pos                                   (4UL)          /*!< DC (Bit 4)                                            */
+ #define R_GMAC0_MAC_Configuration_DC_Msk                                   (0x10UL)       /*!< DC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_BL_Pos                                   (5UL)          /*!< BL (Bit 5)                                            */
+ #define R_GMAC0_MAC_Configuration_BL_Msk                                   (0x60UL)       /*!< BL (Bitfield-Mask: 0x03)                              */
+ #define R_GMAC0_MAC_Configuration_DR_Pos                                   (8UL)          /*!< DR (Bit 8)                                            */
+ #define R_GMAC0_MAC_Configuration_DR_Msk                                   (0x100UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_DCRS_Pos                                 (9UL)          /*!< DCRS (Bit 9)                                          */
+ #define R_GMAC0_MAC_Configuration_DCRS_Msk                                 (0x200UL)      /*!< DCRS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Configuration_DO_Pos                                   (10UL)         /*!< DO (Bit 10)                                           */
+ #define R_GMAC0_MAC_Configuration_DO_Msk                                   (0x400UL)      /*!< DO (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_ECRSFD_Pos                               (11UL)         /*!< ECRSFD (Bit 11)                                       */
+ #define R_GMAC0_MAC_Configuration_ECRSFD_Msk                               (0x800UL)      /*!< ECRSFD (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Configuration_LM_Pos                                   (12UL)         /*!< LM (Bit 12)                                           */
+ #define R_GMAC0_MAC_Configuration_LM_Msk                                   (0x1000UL)     /*!< LM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_DM_Pos                                   (13UL)         /*!< DM (Bit 13)                                           */
+ #define R_GMAC0_MAC_Configuration_DM_Msk                                   (0x2000UL)     /*!< DM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_FES_Pos                                  (14UL)         /*!< FES (Bit 14)                                          */
+ #define R_GMAC0_MAC_Configuration_FES_Msk                                  (0x4000UL)     /*!< FES (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Configuration_PS_Pos                                   (15UL)         /*!< PS (Bit 15)                                           */
+ #define R_GMAC0_MAC_Configuration_PS_Msk                                   (0x8000UL)     /*!< PS (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_JE_Pos                                   (16UL)         /*!< JE (Bit 16)                                           */
+ #define R_GMAC0_MAC_Configuration_JE_Msk                                   (0x10000UL)    /*!< JE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_JD_Pos                                   (17UL)         /*!< JD (Bit 17)                                           */
+ #define R_GMAC0_MAC_Configuration_JD_Msk                                   (0x20000UL)    /*!< JD (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_BE_Pos                                   (18UL)         /*!< BE (Bit 18)                                           */
+ #define R_GMAC0_MAC_Configuration_BE_Msk                                   (0x40000UL)    /*!< BE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_WD_Pos                                   (19UL)         /*!< WD (Bit 19)                                           */
+ #define R_GMAC0_MAC_Configuration_WD_Msk                                   (0x80000UL)    /*!< WD (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Configuration_ACS_Pos                                  (20UL)         /*!< ACS (Bit 20)                                          */
+ #define R_GMAC0_MAC_Configuration_ACS_Msk                                  (0x100000UL)   /*!< ACS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Configuration_CST_Pos                                  (21UL)         /*!< CST (Bit 21)                                          */
+ #define R_GMAC0_MAC_Configuration_CST_Msk                                  (0x200000UL)   /*!< CST (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Configuration_S2KP_Pos                                 (22UL)         /*!< S2KP (Bit 22)                                         */
+ #define R_GMAC0_MAC_Configuration_S2KP_Msk                                 (0x400000UL)   /*!< S2KP (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Configuration_GPSLCE_Pos                               (23UL)         /*!< GPSLCE (Bit 23)                                       */
+ #define R_GMAC0_MAC_Configuration_GPSLCE_Msk                               (0x800000UL)   /*!< GPSLCE (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Configuration_IPG_Pos                                  (24UL)         /*!< IPG (Bit 24)                                          */
+ #define R_GMAC0_MAC_Configuration_IPG_Msk                                  (0x7000000UL)  /*!< IPG (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MAC_Configuration_IPC_Pos                                  (27UL)         /*!< IPC (Bit 27)                                          */
+ #define R_GMAC0_MAC_Configuration_IPC_Msk                                  (0x8000000UL)  /*!< IPC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Configuration_ARPEN_Pos                                (31UL)         /*!< ARPEN (Bit 31)                                        */
+ #define R_GMAC0_MAC_Configuration_ARPEN_Msk                                (0x80000000UL) /*!< ARPEN (Bitfield-Mask: 0x01)                           */
+/* =================================================  MAC_Ext_Configuration  ================================================= */
+ #define R_GMAC0_MAC_Ext_Configuration_GPSL_Pos                             (0UL)          /*!< GPSL (Bit 0)                                          */
+ #define R_GMAC0_MAC_Ext_Configuration_GPSL_Msk                             (0x3fffUL)     /*!< GPSL (Bitfield-Mask: 0x3fff)                          */
+ #define R_GMAC0_MAC_Ext_Configuration_DCRCC_Pos                            (16UL)         /*!< DCRCC (Bit 16)                                        */
+ #define R_GMAC0_MAC_Ext_Configuration_DCRCC_Msk                            (0x10000UL)    /*!< DCRCC (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Ext_Configuration_SPEN_Pos                             (17UL)         /*!< SPEN (Bit 17)                                         */
+ #define R_GMAC0_MAC_Ext_Configuration_SPEN_Msk                             (0x20000UL)    /*!< SPEN (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Ext_Configuration_USP_Pos                              (18UL)         /*!< USP (Bit 18)                                          */
+ #define R_GMAC0_MAC_Ext_Configuration_USP_Msk                              (0x40000UL)    /*!< USP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Ext_Configuration_PDC_Pos                              (19UL)         /*!< PDC (Bit 19)                                          */
+ #define R_GMAC0_MAC_Ext_Configuration_PDC_Msk                              (0x80000UL)    /*!< PDC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Ext_Configuration_HDSMS_Pos                            (20UL)         /*!< HDSMS (Bit 20)                                        */
+ #define R_GMAC0_MAC_Ext_Configuration_HDSMS_Msk                            (0x700000UL)   /*!< HDSMS (Bitfield-Mask: 0x07)                           */
+ #define R_GMAC0_MAC_Ext_Configuration_EIPGEN_Pos                           (24UL)         /*!< EIPGEN (Bit 24)                                       */
+ #define R_GMAC0_MAC_Ext_Configuration_EIPGEN_Msk                           (0x1000000UL)  /*!< EIPGEN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Ext_Configuration_EIPG_Pos                             (25UL)         /*!< EIPG (Bit 25)                                         */
+ #define R_GMAC0_MAC_Ext_Configuration_EIPG_Msk                             (0x3e000000UL) /*!< EIPG (Bitfield-Mask: 0x1f)                            */
+ #define R_GMAC0_MAC_Ext_Configuration_APDIM_Pos                            (30UL)         /*!< APDIM (Bit 30)                                        */
+ #define R_GMAC0_MAC_Ext_Configuration_APDIM_Msk                            (0x40000000UL) /*!< APDIM (Bitfield-Mask: 0x01)                           */
+/* ===================================================  MAC_Packet_Filter  =================================================== */
+ #define R_GMAC0_MAC_Packet_Filter_PR_Pos                                   (0UL)          /*!< PR (Bit 0)                                            */
+ #define R_GMAC0_MAC_Packet_Filter_PR_Msk                                   (0x1UL)        /*!< PR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Packet_Filter_HUC_Pos                                  (1UL)          /*!< HUC (Bit 1)                                           */
+ #define R_GMAC0_MAC_Packet_Filter_HUC_Msk                                  (0x2UL)        /*!< HUC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Packet_Filter_HMC_Pos                                  (2UL)          /*!< HMC (Bit 2)                                           */
+ #define R_GMAC0_MAC_Packet_Filter_HMC_Msk                                  (0x4UL)        /*!< HMC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Packet_Filter_DAIF_Pos                                 (3UL)          /*!< DAIF (Bit 3)                                          */
+ #define R_GMAC0_MAC_Packet_Filter_DAIF_Msk                                 (0x8UL)        /*!< DAIF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Packet_Filter_PM_Pos                                   (4UL)          /*!< PM (Bit 4)                                            */
+ #define R_GMAC0_MAC_Packet_Filter_PM_Msk                                   (0x10UL)       /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Packet_Filter_DBF_Pos                                  (5UL)          /*!< DBF (Bit 5)                                           */
+ #define R_GMAC0_MAC_Packet_Filter_DBF_Msk                                  (0x20UL)       /*!< DBF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Packet_Filter_PCF_Pos                                  (6UL)          /*!< PCF (Bit 6)                                           */
+ #define R_GMAC0_MAC_Packet_Filter_PCF_Msk                                  (0xc0UL)       /*!< PCF (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MAC_Packet_Filter_SAIF_Pos                                 (8UL)          /*!< SAIF (Bit 8)                                          */
+ #define R_GMAC0_MAC_Packet_Filter_SAIF_Msk                                 (0x100UL)      /*!< SAIF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Packet_Filter_SAF_Pos                                  (9UL)          /*!< SAF (Bit 9)                                           */
+ #define R_GMAC0_MAC_Packet_Filter_SAF_Msk                                  (0x200UL)      /*!< SAF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Packet_Filter_HPF_Pos                                  (10UL)         /*!< HPF (Bit 10)                                          */
+ #define R_GMAC0_MAC_Packet_Filter_HPF_Msk                                  (0x400UL)      /*!< HPF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Packet_Filter_VTFE_Pos                                 (16UL)         /*!< VTFE (Bit 16)                                         */
+ #define R_GMAC0_MAC_Packet_Filter_VTFE_Msk                                 (0x10000UL)    /*!< VTFE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Packet_Filter_IPFE_Pos                                 (20UL)         /*!< IPFE (Bit 20)                                         */
+ #define R_GMAC0_MAC_Packet_Filter_IPFE_Msk                                 (0x100000UL)   /*!< IPFE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Packet_Filter_DNTU_Pos                                 (21UL)         /*!< DNTU (Bit 21)                                         */
+ #define R_GMAC0_MAC_Packet_Filter_DNTU_Msk                                 (0x200000UL)   /*!< DNTU (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Packet_Filter_RA_Pos                                   (31UL)         /*!< RA (Bit 31)                                           */
+ #define R_GMAC0_MAC_Packet_Filter_RA_Msk                                   (0x80000000UL) /*!< RA (Bitfield-Mask: 0x01)                              */
+/* =================================================  MAC_Watchdog_Timeout  ================================================== */
+ #define R_GMAC0_MAC_Watchdog_Timeout_WTO_Pos                               (0UL)          /*!< WTO (Bit 0)                                           */
+ #define R_GMAC0_MAC_Watchdog_Timeout_WTO_Msk                               (0xfUL)        /*!< WTO (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MAC_Watchdog_Timeout_PWE_Pos                               (8UL)          /*!< PWE (Bit 8)                                           */
+ #define R_GMAC0_MAC_Watchdog_Timeout_PWE_Msk                               (0x100UL)      /*!< PWE (Bitfield-Mask: 0x01)                             */
+/* ==================================================  MAC_HASH_TABLE_REG0  ================================================== */
+ #define R_GMAC0_MAC_HASH_TABLE_REG0_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC0_MAC_HASH_TABLE_REG0_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG1  ================================================== */
+ #define R_GMAC0_MAC_HASH_TABLE_REG1_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC0_MAC_HASH_TABLE_REG1_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG2  ================================================== */
+ #define R_GMAC0_MAC_HASH_TABLE_REG2_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC0_MAC_HASH_TABLE_REG2_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG3  ================================================== */
+ #define R_GMAC0_MAC_HASH_TABLE_REG3_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC0_MAC_HASH_TABLE_REG3_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG4  ================================================== */
+ #define R_GMAC0_MAC_HASH_TABLE_REG4_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC0_MAC_HASH_TABLE_REG4_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG5  ================================================== */
+ #define R_GMAC0_MAC_HASH_TABLE_REG5_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC0_MAC_HASH_TABLE_REG5_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG6  ================================================== */
+ #define R_GMAC0_MAC_HASH_TABLE_REG6_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC0_MAC_HASH_TABLE_REG6_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG7  ================================================== */
+ #define R_GMAC0_MAC_HASH_TABLE_REG7_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC0_MAC_HASH_TABLE_REG7_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ===================================================  MAC_VLAN_Tag_Ctrl  =================================================== */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_OB_Pos                                   (0UL)          /*!< OB (Bit 0)                                            */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_OB_Msk                                   (0x1UL)        /*!< OB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_CT_Pos                                   (1UL)          /*!< CT (Bit 1)                                            */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_CT_Msk                                   (0x2UL)        /*!< CT (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_OFS_Pos                                  (2UL)          /*!< OFS (Bit 2)                                           */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_OFS_Msk                                  (0x3cUL)       /*!< OFS (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_ETV_Pos                                  (16UL)         /*!< ETV (Bit 16)                                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_ETV_Msk                                  (0x10000UL)    /*!< ETV (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_VTIM_Pos                                 (17UL)         /*!< VTIM (Bit 17)                                         */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_VTIM_Msk                                 (0x20000UL)    /*!< VTIM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_ESVL_Pos                                 (18UL)         /*!< ESVL (Bit 18)                                         */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_ESVL_Msk                                 (0x40000UL)    /*!< ESVL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_ERSVLM_Pos                               (19UL)         /*!< ERSVLM (Bit 19)                                       */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_ERSVLM_Msk                               (0x80000UL)    /*!< ERSVLM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_DOVLTC_Pos                               (20UL)         /*!< DOVLTC (Bit 20)                                       */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_DOVLTC_Msk                               (0x100000UL)   /*!< DOVLTC (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EVLS_Pos                                 (21UL)         /*!< EVLS (Bit 21)                                         */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EVLS_Msk                                 (0x600000UL)   /*!< EVLS (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EVLRXS_Pos                               (24UL)         /*!< EVLRXS (Bit 24)                                       */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EVLRXS_Msk                               (0x1000000UL)  /*!< EVLRXS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_VTHM_Pos                                 (25UL)         /*!< VTHM (Bit 25)                                         */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_VTHM_Msk                                 (0x2000000UL)  /*!< VTHM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EDVLP_Pos                                (26UL)         /*!< EDVLP (Bit 26)                                        */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EDVLP_Msk                                (0x4000000UL)  /*!< EDVLP (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_ERIVLT_Pos                               (27UL)         /*!< ERIVLT (Bit 27)                                       */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_ERIVLT_Msk                               (0x8000000UL)  /*!< ERIVLT (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EIVLS_Pos                                (28UL)         /*!< EIVLS (Bit 28)                                        */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EIVLS_Msk                                (0x30000000UL) /*!< EIVLS (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EIVLRXS_Pos                              (31UL)         /*!< EIVLRXS (Bit 31)                                      */
+ #define R_GMAC0_MAC_VLAN_Tag_Ctrl_EIVLRXS_Msk                              (0x80000000UL) /*!< EIVLRXS (Bitfield-Mask: 0x01)                         */
+/* ===================================================  MAC_VLAN_Tag_Data  =================================================== */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_VID_Pos                                  (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_VID_Msk                                  (0xffffUL)     /*!< VID (Bitfield-Mask: 0xffff)                           */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_VEN_Pos                                  (16UL)         /*!< VEN (Bit 16)                                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_VEN_Msk                                  (0x10000UL)    /*!< VEN (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_ETV_Pos                                  (17UL)         /*!< ETV (Bit 17)                                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_ETV_Msk                                  (0x20000UL)    /*!< ETV (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_DOVLTC_Pos                               (18UL)         /*!< DOVLTC (Bit 18)                                       */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_DOVLTC_Msk                               (0x40000UL)    /*!< DOVLTC (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_ERSVLM_Pos                               (19UL)         /*!< ERSVLM (Bit 19)                                       */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_ERSVLM_Msk                               (0x80000UL)    /*!< ERSVLM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_RIVLT_Pos                                (20UL)         /*!< RIVLT (Bit 20)                                        */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_RIVLT_Msk                                (0x100000UL)   /*!< RIVLT (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_DMACHEN_Pos                              (24UL)         /*!< DMACHEN (Bit 24)                                      */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_DMACHEN_Msk                              (0x1000000UL)  /*!< DMACHEN (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_DMACHN_Pos                               (25UL)         /*!< DMACHN (Bit 25)                                       */
+ #define R_GMAC0_MAC_VLAN_Tag_Data_DMACHN_Msk                               (0xe000000UL)  /*!< DMACHN (Bitfield-Mask: 0x07)                          */
+/* ==================================================  MAC_VLAN_Hash_Table  ================================================== */
+ #define R_GMAC0_MAC_VLAN_Hash_Table_VLHT_Pos                               (0UL)          /*!< VLHT (Bit 0)                                          */
+ #define R_GMAC0_MAC_VLAN_Hash_Table_VLHT_Msk                               (0xffffUL)     /*!< VLHT (Bitfield-Mask: 0xffff)                          */
+/* ==================================================  MAC_Q0_Tx_Flow_Ctrl  ================================================== */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_FCB_BPA_Pos                            (0UL)          /*!< FCB_BPA (Bit 0)                                       */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_FCB_BPA_Msk                            (0x1UL)        /*!< FCB_BPA (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_TFE_Pos                                (1UL)          /*!< TFE (Bit 1)                                           */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_TFE_Msk                                (0x2UL)        /*!< TFE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_PLT_Pos                                (4UL)          /*!< PLT (Bit 4)                                           */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_PLT_Msk                                (0x70UL)       /*!< PLT (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_DZPQ_Pos                               (7UL)          /*!< DZPQ (Bit 7)                                          */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_DZPQ_Msk                               (0x80UL)       /*!< DZPQ (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_PT_Pos                                 (16UL)         /*!< PT (Bit 16)                                           */
+ #define R_GMAC0_MAC_Q0_Tx_Flow_Ctrl_PT_Msk                                 (0xffff0000UL) /*!< PT (Bitfield-Mask: 0xffff)                            */
+/* ===================================================  MAC_Rx_Flow_Ctrl  ==================================================== */
+ #define R_GMAC0_MAC_Rx_Flow_Ctrl_RFE_Pos                                   (0UL)          /*!< RFE (Bit 0)                                           */
+ #define R_GMAC0_MAC_Rx_Flow_Ctrl_RFE_Msk                                   (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Rx_Flow_Ctrl_UP_Pos                                    (1UL)          /*!< UP (Bit 1)                                            */
+ #define R_GMAC0_MAC_Rx_Flow_Ctrl_UP_Msk                                    (0x2UL)        /*!< UP (Bitfield-Mask: 0x01)                              */
+/* =====================================================  MAC_RxQ_Ctrl4  ===================================================== */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_UFFQE_Pos                                    (0UL)          /*!< UFFQE (Bit 0)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_UFFQE_Msk                                    (0x1UL)        /*!< UFFQE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_UFFQ_Pos                                     (1UL)          /*!< UFFQ (Bit 1)                                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_UFFQ_Msk                                     (0xeUL)        /*!< UFFQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_MFFQE_Pos                                    (8UL)          /*!< MFFQE (Bit 8)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_MFFQE_Msk                                    (0x100UL)      /*!< MFFQE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_MFFQ_Pos                                     (9UL)          /*!< MFFQ (Bit 9)                                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_MFFQ_Msk                                     (0xe00UL)      /*!< MFFQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_VFFQE_Pos                                    (16UL)         /*!< VFFQE (Bit 16)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_VFFQE_Msk                                    (0x10000UL)    /*!< VFFQE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_VFFQ_Pos                                     (17UL)         /*!< VFFQ (Bit 17)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl4_VFFQ_Msk                                     (0xe0000UL)    /*!< VFFQ (Bitfield-Mask: 0x07)                            */
+/* =====================================================  MAC_RxQ_Ctrl0  ===================================================== */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ0EN_Pos                                   (0UL)          /*!< RXQ0EN (Bit 0)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ0EN_Msk                                   (0x3UL)        /*!< RXQ0EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ1EN_Pos                                   (2UL)          /*!< RXQ1EN (Bit 2)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ1EN_Msk                                   (0xcUL)        /*!< RXQ1EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ2EN_Pos                                   (4UL)          /*!< RXQ2EN (Bit 4)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ2EN_Msk                                   (0x30UL)       /*!< RXQ2EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ3EN_Pos                                   (6UL)          /*!< RXQ3EN (Bit 6)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ3EN_Msk                                   (0xc0UL)       /*!< RXQ3EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ4EN_Pos                                   (8UL)          /*!< RXQ4EN (Bit 8)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ4EN_Msk                                   (0x300UL)      /*!< RXQ4EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ5EN_Pos                                   (10UL)         /*!< RXQ5EN (Bit 10)                                       */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ5EN_Msk                                   (0xc00UL)      /*!< RXQ5EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ6EN_Pos                                   (12UL)         /*!< RXQ6EN (Bit 12)                                       */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ6EN_Msk                                   (0x3000UL)     /*!< RXQ6EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ7EN_Pos                                   (14UL)         /*!< RXQ7EN (Bit 14)                                       */
+ #define R_GMAC0_MAC_RxQ_Ctrl0_RXQ7EN_Msk                                   (0xc000UL)     /*!< RXQ7EN (Bitfield-Mask: 0x03)                          */
+/* =====================================================  MAC_RxQ_Ctrl1  ===================================================== */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_AVCPQ_Pos                                    (0UL)          /*!< AVCPQ (Bit 0)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_AVCPQ_Msk                                    (0x7UL)        /*!< AVCPQ (Bitfield-Mask: 0x07)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_PTPQ_Pos                                     (4UL)          /*!< PTPQ (Bit 4)                                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_PTPQ_Msk                                     (0x70UL)       /*!< PTPQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_UPQ_Pos                                      (12UL)         /*!< UPQ (Bit 12)                                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_UPQ_Msk                                      (0x7000UL)     /*!< UPQ (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_MCBCQ_Pos                                    (16UL)         /*!< MCBCQ (Bit 16)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_MCBCQ_Msk                                    (0x70000UL)    /*!< MCBCQ (Bitfield-Mask: 0x07)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_MCBCQEN_Pos                                  (20UL)         /*!< MCBCQEN (Bit 20)                                      */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_MCBCQEN_Msk                                  (0x100000UL)   /*!< MCBCQEN (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_TACPQE_Pos                                   (21UL)         /*!< TACPQE (Bit 21)                                       */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_TACPQE_Msk                                   (0x200000UL)   /*!< TACPQE (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_TPQC_Pos                                     (22UL)         /*!< TPQC (Bit 22)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_TPQC_Msk                                     (0xc00000UL)   /*!< TPQC (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_FPRQ_Pos                                     (24UL)         /*!< FPRQ (Bit 24)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_FPRQ_Msk                                     (0x7000000UL)  /*!< FPRQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_OMCBCQ_Pos                                   (28UL)         /*!< OMCBCQ (Bit 28)                                       */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_OMCBCQ_Msk                                   (0x10000000UL) /*!< OMCBCQ (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_TBRQE_Pos                                    (29UL)         /*!< TBRQE (Bit 29)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl1_TBRQE_Msk                                    (0x20000000UL) /*!< TBRQE (Bitfield-Mask: 0x01)                           */
+/* =====================================================  MAC_RxQ_Ctrl2  ===================================================== */
+ #define R_GMAC0_MAC_RxQ_Ctrl2_PSRQ0_Pos                                    (0UL)          /*!< PSRQ0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl2_PSRQ0_Msk                                    (0xffUL)       /*!< PSRQ0 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl2_PSRQ1_Pos                                    (8UL)          /*!< PSRQ1 (Bit 8)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl2_PSRQ1_Msk                                    (0xff00UL)     /*!< PSRQ1 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl2_PSRQ2_Pos                                    (16UL)         /*!< PSRQ2 (Bit 16)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl2_PSRQ2_Msk                                    (0xff0000UL)   /*!< PSRQ2 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl2_PSRQ3_Pos                                    (24UL)         /*!< PSRQ3 (Bit 24)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl2_PSRQ3_Msk                                    (0xff000000UL) /*!< PSRQ3 (Bitfield-Mask: 0xff)                           */
+/* =====================================================  MAC_RxQ_Ctrl3  ===================================================== */
+ #define R_GMAC0_MAC_RxQ_Ctrl3_PSRQ4_Pos                                    (0UL)          /*!< PSRQ4 (Bit 0)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl3_PSRQ4_Msk                                    (0xffUL)       /*!< PSRQ4 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl3_PSRQ5_Pos                                    (8UL)          /*!< PSRQ5 (Bit 8)                                         */
+ #define R_GMAC0_MAC_RxQ_Ctrl3_PSRQ5_Msk                                    (0xff00UL)     /*!< PSRQ5 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl3_PSRQ6_Pos                                    (16UL)         /*!< PSRQ6 (Bit 16)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl3_PSRQ6_Msk                                    (0xff0000UL)   /*!< PSRQ6 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC0_MAC_RxQ_Ctrl3_PSRQ7_Pos                                    (24UL)         /*!< PSRQ7 (Bit 24)                                        */
+ #define R_GMAC0_MAC_RxQ_Ctrl3_PSRQ7_Msk                                    (0xff000000UL) /*!< PSRQ7 (Bitfield-Mask: 0xff)                           */
+/* =================================================  MAC_Interrupt_Status  ================================================== */
+ #define R_GMAC0_MAC_Interrupt_Status_PMTIS_Pos                             (4UL)          /*!< PMTIS (Bit 4)                                         */
+ #define R_GMAC0_MAC_Interrupt_Status_PMTIS_Msk                             (0x10UL)       /*!< PMTIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Status_LPIIS_Pos                             (5UL)          /*!< LPIIS (Bit 5)                                         */
+ #define R_GMAC0_MAC_Interrupt_Status_LPIIS_Msk                             (0x20UL)       /*!< LPIIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Status_MMCIS_Pos                             (8UL)          /*!< MMCIS (Bit 8)                                         */
+ #define R_GMAC0_MAC_Interrupt_Status_MMCIS_Msk                             (0x100UL)      /*!< MMCIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Status_MMCRXIS_Pos                           (9UL)          /*!< MMCRXIS (Bit 9)                                       */
+ #define R_GMAC0_MAC_Interrupt_Status_MMCRXIS_Msk                           (0x200UL)      /*!< MMCRXIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Interrupt_Status_MMCTXIS_Pos                           (10UL)         /*!< MMCTXIS (Bit 10)                                      */
+ #define R_GMAC0_MAC_Interrupt_Status_MMCTXIS_Msk                           (0x400UL)      /*!< MMCTXIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Interrupt_Status_MMCRXIPIS_Pos                         (11UL)         /*!< MMCRXIPIS (Bit 11)                                    */
+ #define R_GMAC0_MAC_Interrupt_Status_MMCRXIPIS_Msk                         (0x800UL)      /*!< MMCRXIPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_Interrupt_Status_TSIS_Pos                              (12UL)         /*!< TSIS (Bit 12)                                         */
+ #define R_GMAC0_MAC_Interrupt_Status_TSIS_Msk                              (0x1000UL)     /*!< TSIS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Interrupt_Status_TXSTSIS_Pos                           (13UL)         /*!< TXSTSIS (Bit 13)                                      */
+ #define R_GMAC0_MAC_Interrupt_Status_TXSTSIS_Msk                           (0x2000UL)     /*!< TXSTSIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Interrupt_Status_RXSTSIS_Pos                           (14UL)         /*!< RXSTSIS (Bit 14)                                      */
+ #define R_GMAC0_MAC_Interrupt_Status_RXSTSIS_Msk                           (0x4000UL)     /*!< RXSTSIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Interrupt_Status_FPEIS_Pos                             (17UL)         /*!< FPEIS (Bit 17)                                        */
+ #define R_GMAC0_MAC_Interrupt_Status_FPEIS_Msk                             (0x20000UL)    /*!< FPEIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Status_MDIOIS_Pos                            (18UL)         /*!< MDIOIS (Bit 18)                                       */
+ #define R_GMAC0_MAC_Interrupt_Status_MDIOIS_Msk                            (0x40000UL)    /*!< MDIOIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Interrupt_Status_MFTIS_Pos                             (19UL)         /*!< MFTIS (Bit 19)                                        */
+ #define R_GMAC0_MAC_Interrupt_Status_MFTIS_Msk                             (0x80000UL)    /*!< MFTIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Status_MFRIS_Pos                             (20UL)         /*!< MFRIS (Bit 20)                                        */
+ #define R_GMAC0_MAC_Interrupt_Status_MFRIS_Msk                             (0x100000UL)   /*!< MFRIS (Bitfield-Mask: 0x01)                           */
+/* =================================================  MAC_Interrupt_Enable  ================================================== */
+ #define R_GMAC0_MAC_Interrupt_Enable_PHYIE_Pos                             (3UL)          /*!< PHYIE (Bit 3)                                         */
+ #define R_GMAC0_MAC_Interrupt_Enable_PHYIE_Msk                             (0x8UL)        /*!< PHYIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Enable_PMTIE_Pos                             (4UL)          /*!< PMTIE (Bit 4)                                         */
+ #define R_GMAC0_MAC_Interrupt_Enable_PMTIE_Msk                             (0x10UL)       /*!< PMTIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Enable_LPIIE_Pos                             (5UL)          /*!< LPIIE (Bit 5)                                         */
+ #define R_GMAC0_MAC_Interrupt_Enable_LPIIE_Msk                             (0x20UL)       /*!< LPIIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Enable_TSIE_Pos                              (12UL)         /*!< TSIE (Bit 12)                                         */
+ #define R_GMAC0_MAC_Interrupt_Enable_TSIE_Msk                              (0x1000UL)     /*!< TSIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Interrupt_Enable_TXSTSIE_Pos                           (13UL)         /*!< TXSTSIE (Bit 13)                                      */
+ #define R_GMAC0_MAC_Interrupt_Enable_TXSTSIE_Msk                           (0x2000UL)     /*!< TXSTSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Interrupt_Enable_RXSTSIE_Pos                           (14UL)         /*!< RXSTSIE (Bit 14)                                      */
+ #define R_GMAC0_MAC_Interrupt_Enable_RXSTSIE_Msk                           (0x4000UL)     /*!< RXSTSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Interrupt_Enable_FPEIE_Pos                             (17UL)         /*!< FPEIE (Bit 17)                                        */
+ #define R_GMAC0_MAC_Interrupt_Enable_FPEIE_Msk                             (0x20000UL)    /*!< FPEIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Interrupt_Enable_MDIOIE_Pos                            (18UL)         /*!< MDIOIE (Bit 18)                                       */
+ #define R_GMAC0_MAC_Interrupt_Enable_MDIOIE_Msk                            (0x40000UL)    /*!< MDIOIE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_Rx_Tx_Status  ==================================================== */
+ #define R_GMAC0_MAC_Rx_Tx_Status_TJT_Pos                                   (0UL)          /*!< TJT (Bit 0)                                           */
+ #define R_GMAC0_MAC_Rx_Tx_Status_TJT_Msk                                   (0x1UL)        /*!< TJT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Rx_Tx_Status_NCARR_Pos                                 (1UL)          /*!< NCARR (Bit 1)                                         */
+ #define R_GMAC0_MAC_Rx_Tx_Status_NCARR_Msk                                 (0x2UL)        /*!< NCARR (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Rx_Tx_Status_LCARR_Pos                                 (2UL)          /*!< LCARR (Bit 2)                                         */
+ #define R_GMAC0_MAC_Rx_Tx_Status_LCARR_Msk                                 (0x4UL)        /*!< LCARR (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Rx_Tx_Status_EXDEF_Pos                                 (3UL)          /*!< EXDEF (Bit 3)                                         */
+ #define R_GMAC0_MAC_Rx_Tx_Status_EXDEF_Msk                                 (0x8UL)        /*!< EXDEF (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Rx_Tx_Status_LCOL_Pos                                  (4UL)          /*!< LCOL (Bit 4)                                          */
+ #define R_GMAC0_MAC_Rx_Tx_Status_LCOL_Msk                                  (0x10UL)       /*!< LCOL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Rx_Tx_Status_EXCOL_Pos                                 (5UL)          /*!< EXCOL (Bit 5)                                         */
+ #define R_GMAC0_MAC_Rx_Tx_Status_EXCOL_Msk                                 (0x20UL)       /*!< EXCOL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Rx_Tx_Status_RWT_Pos                                   (8UL)          /*!< RWT (Bit 8)                                           */
+ #define R_GMAC0_MAC_Rx_Tx_Status_RWT_Msk                                   (0x100UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+/* ================================================  MAC_PMT_Control_Status  ================================================= */
+ #define R_GMAC0_MAC_PMT_Control_Status_PWRDWN_Pos                          (0UL)          /*!< PWRDWN (Bit 0)                                        */
+ #define R_GMAC0_MAC_PMT_Control_Status_PWRDWN_Msk                          (0x1UL)        /*!< PWRDWN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_PMT_Control_Status_MGKPKTEN_Pos                        (1UL)          /*!< MGKPKTEN (Bit 1)                                      */
+ #define R_GMAC0_MAC_PMT_Control_Status_MGKPKTEN_Msk                        (0x2UL)        /*!< MGKPKTEN (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKPKTEN_Pos                        (2UL)          /*!< RWKPKTEN (Bit 2)                                      */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKPKTEN_Msk                        (0x4UL)        /*!< RWKPKTEN (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_PMT_Control_Status_MGKPRCVD_Pos                        (5UL)          /*!< MGKPRCVD (Bit 5)                                      */
+ #define R_GMAC0_MAC_PMT_Control_Status_MGKPRCVD_Msk                        (0x20UL)       /*!< MGKPRCVD (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKPRCVD_Pos                        (6UL)          /*!< RWKPRCVD (Bit 6)                                      */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKPRCVD_Msk                        (0x40UL)       /*!< RWKPRCVD (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_PMT_Control_Status_GLBLUCAST_Pos                       (9UL)          /*!< GLBLUCAST (Bit 9)                                     */
+ #define R_GMAC0_MAC_PMT_Control_Status_GLBLUCAST_Msk                       (0x200UL)      /*!< GLBLUCAST (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKPFE_Pos                          (10UL)         /*!< RWKPFE (Bit 10)                                       */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKPFE_Msk                          (0x400UL)      /*!< RWKPFE (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKPTR_Pos                          (24UL)         /*!< RWKPTR (Bit 24)                                       */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKPTR_Msk                          (0x1f000000UL) /*!< RWKPTR (Bitfield-Mask: 0x1f)                          */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKFILTRST_Pos                      (31UL)         /*!< RWKFILTRST (Bit 31)                                   */
+ #define R_GMAC0_MAC_PMT_Control_Status_RWKFILTRST_Msk                      (0x80000000UL) /*!< RWKFILTRST (Bitfield-Mask: 0x01)                     */
+/* =================================================  MAC_RWK_Packet_Filter  ================================================= */
+ #define R_GMAC0_MAC_RWK_Packet_Filter_WKUPFRMFTR_Pos                       (0UL)          /*!< WKUPFRMFTR (Bit 0)                                    */
+ #define R_GMAC0_MAC_RWK_Packet_Filter_WKUPFRMFTR_Msk                       (0xffffffffUL) /*!< WKUPFRMFTR (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  MAC_LPI_Control_Status  ================================================= */
+ #define R_GMAC0_MAC_LPI_Control_Status_TLPIEN_Pos                          (0UL)          /*!< TLPIEN (Bit 0)                                        */
+ #define R_GMAC0_MAC_LPI_Control_Status_TLPIEN_Msk                          (0x1UL)        /*!< TLPIEN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_LPI_Control_Status_TLPIEX_Pos                          (1UL)          /*!< TLPIEX (Bit 1)                                        */
+ #define R_GMAC0_MAC_LPI_Control_Status_TLPIEX_Msk                          (0x2UL)        /*!< TLPIEX (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_LPI_Control_Status_RLPIEN_Pos                          (2UL)          /*!< RLPIEN (Bit 2)                                        */
+ #define R_GMAC0_MAC_LPI_Control_Status_RLPIEN_Msk                          (0x4UL)        /*!< RLPIEN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_LPI_Control_Status_RLPIEX_Pos                          (3UL)          /*!< RLPIEX (Bit 3)                                        */
+ #define R_GMAC0_MAC_LPI_Control_Status_RLPIEX_Msk                          (0x8UL)        /*!< RLPIEX (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_LPI_Control_Status_TLPIST_Pos                          (8UL)          /*!< TLPIST (Bit 8)                                        */
+ #define R_GMAC0_MAC_LPI_Control_Status_TLPIST_Msk                          (0x100UL)      /*!< TLPIST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_LPI_Control_Status_RLPIST_Pos                          (9UL)          /*!< RLPIST (Bit 9)                                        */
+ #define R_GMAC0_MAC_LPI_Control_Status_RLPIST_Msk                          (0x200UL)      /*!< RLPIST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_LPI_Control_Status_LPIEN_Pos                           (16UL)         /*!< LPIEN (Bit 16)                                        */
+ #define R_GMAC0_MAC_LPI_Control_Status_LPIEN_Msk                           (0x10000UL)    /*!< LPIEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_LPI_Control_Status_PLS_Pos                             (17UL)         /*!< PLS (Bit 17)                                          */
+ #define R_GMAC0_MAC_LPI_Control_Status_PLS_Msk                             (0x20000UL)    /*!< PLS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_LPI_Control_Status_LPITXA_Pos                          (19UL)         /*!< LPITXA (Bit 19)                                       */
+ #define R_GMAC0_MAC_LPI_Control_Status_LPITXA_Msk                          (0x80000UL)    /*!< LPITXA (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_LPI_Control_Status_LPIATE_Pos                          (20UL)         /*!< LPIATE (Bit 20)                                       */
+ #define R_GMAC0_MAC_LPI_Control_Status_LPIATE_Msk                          (0x100000UL)   /*!< LPIATE (Bitfield-Mask: 0x01)                          */
+/* ================================================  MAC_LPI_Timers_Control  ================================================= */
+ #define R_GMAC0_MAC_LPI_Timers_Control_TWT_Pos                             (0UL)          /*!< TWT (Bit 0)                                           */
+ #define R_GMAC0_MAC_LPI_Timers_Control_TWT_Msk                             (0xffffUL)     /*!< TWT (Bitfield-Mask: 0xffff)                           */
+ #define R_GMAC0_MAC_LPI_Timers_Control_LST_Pos                             (16UL)         /*!< LST (Bit 16)                                          */
+ #define R_GMAC0_MAC_LPI_Timers_Control_LST_Msk                             (0x3ff0000UL)  /*!< LST (Bitfield-Mask: 0x3ff)                            */
+/* ==================================================  MAC_LPI_Entry_Timer  ================================================== */
+ #define R_GMAC0_MAC_LPI_Entry_Timer_LPIET_Pos                              (3UL)          /*!< LPIET (Bit 3)                                         */
+ #define R_GMAC0_MAC_LPI_Entry_Timer_LPIET_Msk                              (0xffff8UL)    /*!< LPIET (Bitfield-Mask: 0x1ffff)                        */
+/* ==================================================  MAC_1US_Tic_Counter  ================================================== */
+ #define R_GMAC0_MAC_1US_Tic_Counter_TIC_1US_CNTR_Pos                       (0UL)          /*!< TIC_1US_CNTR (Bit 0)                                  */
+ #define R_GMAC0_MAC_1US_Tic_Counter_TIC_1US_CNTR_Msk                       (0xfffUL)      /*!< TIC_1US_CNTR (Bitfield-Mask: 0xfff)                   */
+/* ======================================================  MAC_Version  ====================================================== */
+ #define R_GMAC0_MAC_Version_VER_Pos                                        (0UL)          /*!< VER (Bit 0)                                           */
+ #define R_GMAC0_MAC_Version_VER_Msk                                        (0xffffUL)     /*!< VER (Bitfield-Mask: 0xffff)                           */
+/* =======================================================  MAC_Debug  ======================================================= */
+ #define R_GMAC0_MAC_Debug_RPESTS_Pos                                       (0UL)          /*!< RPESTS (Bit 0)                                        */
+ #define R_GMAC0_MAC_Debug_RPESTS_Msk                                       (0x1UL)        /*!< RPESTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Debug_RFCFCSTS_Pos                                     (1UL)          /*!< RFCFCSTS (Bit 1)                                      */
+ #define R_GMAC0_MAC_Debug_RFCFCSTS_Msk                                     (0x6UL)        /*!< RFCFCSTS (Bitfield-Mask: 0x03)                        */
+ #define R_GMAC0_MAC_Debug_TPESTS_Pos                                       (16UL)         /*!< TPESTS (Bit 16)                                       */
+ #define R_GMAC0_MAC_Debug_TPESTS_Msk                                       (0x10000UL)    /*!< TPESTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Debug_TFCSTS_Pos                                       (17UL)         /*!< TFCSTS (Bit 17)                                       */
+ #define R_GMAC0_MAC_Debug_TFCSTS_Msk                                       (0x60000UL)    /*!< TFCSTS (Bitfield-Mask: 0x03)                          */
+/* ====================================================  MAC_HW_Feature0  ==================================================== */
+ #define R_GMAC0_MAC_HW_Feature0_MIISEL_Pos                                 (0UL)          /*!< MIISEL (Bit 0)                                        */
+ #define R_GMAC0_MAC_HW_Feature0_MIISEL_Msk                                 (0x1UL)        /*!< MIISEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature0_GMIISEL_Pos                                (1UL)          /*!< GMIISEL (Bit 1)                                       */
+ #define R_GMAC0_MAC_HW_Feature0_GMIISEL_Msk                                (0x2UL)        /*!< GMIISEL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_HW_Feature0_HDSEL_Pos                                  (2UL)          /*!< HDSEL (Bit 2)                                         */
+ #define R_GMAC0_MAC_HW_Feature0_HDSEL_Msk                                  (0x4UL)        /*!< HDSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_HW_Feature0_VLHASH_Pos                                 (4UL)          /*!< VLHASH (Bit 4)                                        */
+ #define R_GMAC0_MAC_HW_Feature0_VLHASH_Msk                                 (0x10UL)       /*!< VLHASH (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature0_SMASEL_Pos                                 (5UL)          /*!< SMASEL (Bit 5)                                        */
+ #define R_GMAC0_MAC_HW_Feature0_SMASEL_Msk                                 (0x20UL)       /*!< SMASEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature0_RWKSEL_Pos                                 (6UL)          /*!< RWKSEL (Bit 6)                                        */
+ #define R_GMAC0_MAC_HW_Feature0_RWKSEL_Msk                                 (0x40UL)       /*!< RWKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature0_MGKSEL_Pos                                 (7UL)          /*!< MGKSEL (Bit 7)                                        */
+ #define R_GMAC0_MAC_HW_Feature0_MGKSEL_Msk                                 (0x80UL)       /*!< MGKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature0_MMCSEL_Pos                                 (8UL)          /*!< MMCSEL (Bit 8)                                        */
+ #define R_GMAC0_MAC_HW_Feature0_MMCSEL_Msk                                 (0x100UL)      /*!< MMCSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature0_ARPOFFSEL_Pos                              (9UL)          /*!< ARPOFFSEL (Bit 9)                                     */
+ #define R_GMAC0_MAC_HW_Feature0_ARPOFFSEL_Msk                              (0x200UL)      /*!< ARPOFFSEL (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_HW_Feature0_TSSEL_Pos                                  (12UL)         /*!< TSSEL (Bit 12)                                        */
+ #define R_GMAC0_MAC_HW_Feature0_TSSEL_Msk                                  (0x1000UL)     /*!< TSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_HW_Feature0_EEESEL_Pos                                 (13UL)         /*!< EEESEL (Bit 13)                                       */
+ #define R_GMAC0_MAC_HW_Feature0_EEESEL_Msk                                 (0x2000UL)     /*!< EEESEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature0_TXCOESEL_Pos                               (14UL)         /*!< TXCOESEL (Bit 14)                                     */
+ #define R_GMAC0_MAC_HW_Feature0_TXCOESEL_Msk                               (0x4000UL)     /*!< TXCOESEL (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_HW_Feature0_RXCOESEL_Pos                               (16UL)         /*!< RXCOESEL (Bit 16)                                     */
+ #define R_GMAC0_MAC_HW_Feature0_RXCOESEL_Msk                               (0x10000UL)    /*!< RXCOESEL (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_HW_Feature0_ADDMACADRSEL_Pos                           (18UL)         /*!< ADDMACADRSEL (Bit 18)                                 */
+ #define R_GMAC0_MAC_HW_Feature0_ADDMACADRSEL_Msk                           (0x7c0000UL)   /*!< ADDMACADRSEL (Bitfield-Mask: 0x1f)                    */
+ #define R_GMAC0_MAC_HW_Feature0_TSSTSSEL_Pos                               (25UL)         /*!< TSSTSSEL (Bit 25)                                     */
+ #define R_GMAC0_MAC_HW_Feature0_TSSTSSEL_Msk                               (0x6000000UL)  /*!< TSSTSSEL (Bitfield-Mask: 0x03)                        */
+/* ====================================================  MAC_HW_Feature1  ==================================================== */
+ #define R_GMAC0_MAC_HW_Feature1_RXFIFOSIZE_Pos                             (0UL)          /*!< RXFIFOSIZE (Bit 0)                                    */
+ #define R_GMAC0_MAC_HW_Feature1_RXFIFOSIZE_Msk                             (0x1fUL)       /*!< RXFIFOSIZE (Bitfield-Mask: 0x1f)                      */
+ #define R_GMAC0_MAC_HW_Feature1_TXFIFOSIZE_Pos                             (6UL)          /*!< TXFIFOSIZE (Bit 6)                                    */
+ #define R_GMAC0_MAC_HW_Feature1_TXFIFOSIZE_Msk                             (0x7c0UL)      /*!< TXFIFOSIZE (Bitfield-Mask: 0x1f)                      */
+ #define R_GMAC0_MAC_HW_Feature1_OSTEN_Pos                                  (11UL)         /*!< OSTEN (Bit 11)                                        */
+ #define R_GMAC0_MAC_HW_Feature1_OSTEN_Msk                                  (0x800UL)      /*!< OSTEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_HW_Feature1_PTOEN_Pos                                  (12UL)         /*!< PTOEN (Bit 12)                                        */
+ #define R_GMAC0_MAC_HW_Feature1_PTOEN_Msk                                  (0x1000UL)     /*!< PTOEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_HW_Feature1_ADDR64_Pos                                 (14UL)         /*!< ADDR64 (Bit 14)                                       */
+ #define R_GMAC0_MAC_HW_Feature1_ADDR64_Msk                                 (0xc000UL)     /*!< ADDR64 (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_HW_Feature1_SPHEN_Pos                                  (17UL)         /*!< SPHEN (Bit 17)                                        */
+ #define R_GMAC0_MAC_HW_Feature1_SPHEN_Msk                                  (0x20000UL)    /*!< SPHEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_HW_Feature1_AVSEL_Pos                                  (20UL)         /*!< AVSEL (Bit 20)                                        */
+ #define R_GMAC0_MAC_HW_Feature1_AVSEL_Msk                                  (0x100000UL)   /*!< AVSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_HW_Feature1_POUOST_Pos                                 (23UL)         /*!< POUOST (Bit 23)                                       */
+ #define R_GMAC0_MAC_HW_Feature1_POUOST_Msk                                 (0x800000UL)   /*!< POUOST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature1_HASHTBLSZ_Pos                              (24UL)         /*!< HASHTBLSZ (Bit 24)                                    */
+ #define R_GMAC0_MAC_HW_Feature1_HASHTBLSZ_Msk                              (0x3000000UL)  /*!< HASHTBLSZ (Bitfield-Mask: 0x03)                       */
+ #define R_GMAC0_MAC_HW_Feature1_L3L4FNUM_Pos                               (27UL)         /*!< L3L4FNUM (Bit 27)                                     */
+ #define R_GMAC0_MAC_HW_Feature1_L3L4FNUM_Msk                               (0x78000000UL) /*!< L3L4FNUM (Bitfield-Mask: 0x0f)                        */
+/* ====================================================  MAC_HW_Feature2  ==================================================== */
+ #define R_GMAC0_MAC_HW_Feature2_RXQCNT_Pos                                 (0UL)          /*!< RXQCNT (Bit 0)                                        */
+ #define R_GMAC0_MAC_HW_Feature2_RXQCNT_Msk                                 (0xfUL)        /*!< RXQCNT (Bitfield-Mask: 0x0f)                          */
+ #define R_GMAC0_MAC_HW_Feature2_TXQCNT_Pos                                 (6UL)          /*!< TXQCNT (Bit 6)                                        */
+ #define R_GMAC0_MAC_HW_Feature2_TXQCNT_Msk                                 (0x3c0UL)      /*!< TXQCNT (Bitfield-Mask: 0x0f)                          */
+ #define R_GMAC0_MAC_HW_Feature2_RXCHCNT_Pos                                (12UL)         /*!< RXCHCNT (Bit 12)                                      */
+ #define R_GMAC0_MAC_HW_Feature2_RXCHCNT_Msk                                (0xf000UL)     /*!< RXCHCNT (Bitfield-Mask: 0x0f)                         */
+ #define R_GMAC0_MAC_HW_Feature2_TXCHCNT_Pos                                (18UL)         /*!< TXCHCNT (Bit 18)                                      */
+ #define R_GMAC0_MAC_HW_Feature2_TXCHCNT_Msk                                (0x3c0000UL)   /*!< TXCHCNT (Bitfield-Mask: 0x0f)                         */
+ #define R_GMAC0_MAC_HW_Feature2_AUXSNAPNUM_Pos                             (28UL)         /*!< AUXSNAPNUM (Bit 28)                                   */
+ #define R_GMAC0_MAC_HW_Feature2_AUXSNAPNUM_Msk                             (0x70000000UL) /*!< AUXSNAPNUM (Bitfield-Mask: 0x07)                      */
+/* ====================================================  MAC_HW_Feature3  ==================================================== */
+ #define R_GMAC0_MAC_HW_Feature3_NRVF_Pos                                   (0UL)          /*!< NRVF (Bit 0)                                          */
+ #define R_GMAC0_MAC_HW_Feature3_NRVF_Msk                                   (0x7UL)        /*!< NRVF (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MAC_HW_Feature3_DVLAN_Pos                                  (5UL)          /*!< DVLAN (Bit 5)                                         */
+ #define R_GMAC0_MAC_HW_Feature3_DVLAN_Msk                                  (0x20UL)       /*!< DVLAN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_HW_Feature3_PDUPSEL_Pos                                (9UL)          /*!< PDUPSEL (Bit 9)                                       */
+ #define R_GMAC0_MAC_HW_Feature3_PDUPSEL_Msk                                (0x200UL)      /*!< PDUPSEL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_HW_Feature3_ESTSEL_Pos                                 (16UL)         /*!< ESTSEL (Bit 16)                                       */
+ #define R_GMAC0_MAC_HW_Feature3_ESTSEL_Msk                                 (0x10000UL)    /*!< ESTSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature3_ESTDEP_Pos                                 (17UL)         /*!< ESTDEP (Bit 17)                                       */
+ #define R_GMAC0_MAC_HW_Feature3_ESTDEP_Msk                                 (0xe0000UL)    /*!< ESTDEP (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_HW_Feature3_ESTWID_Pos                                 (20UL)         /*!< ESTWID (Bit 20)                                       */
+ #define R_GMAC0_MAC_HW_Feature3_ESTWID_Msk                                 (0x300000UL)   /*!< ESTWID (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_HW_Feature3_FPESEL_Pos                                 (26UL)         /*!< FPESEL (Bit 26)                                       */
+ #define R_GMAC0_MAC_HW_Feature3_FPESEL_Msk                                 (0x4000000UL)  /*!< FPESEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_HW_Feature3_TBSSEL_Pos                                 (27UL)         /*!< TBSSEL (Bit 27)                                       */
+ #define R_GMAC0_MAC_HW_Feature3_TBSSEL_Msk                                 (0x8000000UL)  /*!< TBSSEL (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_MDIO_Address  ==================================================== */
+ #define R_GMAC0_MAC_MDIO_Address_GB_Pos                                    (0UL)          /*!< GB (Bit 0)                                            */
+ #define R_GMAC0_MAC_MDIO_Address_GB_Msk                                    (0x1UL)        /*!< GB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_MDIO_Address_C45E_Pos                                  (1UL)          /*!< C45E (Bit 1)                                          */
+ #define R_GMAC0_MAC_MDIO_Address_C45E_Msk                                  (0x2UL)        /*!< C45E (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_MDIO_Address_GOC_Pos                                   (2UL)          /*!< GOC (Bit 2)                                           */
+ #define R_GMAC0_MAC_MDIO_Address_GOC_Msk                                   (0xcUL)        /*!< GOC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MAC_MDIO_Address_SKAP_Pos                                  (4UL)          /*!< SKAP (Bit 4)                                          */
+ #define R_GMAC0_MAC_MDIO_Address_SKAP_Msk                                  (0x10UL)       /*!< SKAP (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_MDIO_Address_CR_Pos                                    (8UL)          /*!< CR (Bit 8)                                            */
+ #define R_GMAC0_MAC_MDIO_Address_CR_Msk                                    (0xf00UL)      /*!< CR (Bitfield-Mask: 0x0f)                              */
+ #define R_GMAC0_MAC_MDIO_Address_NTC_Pos                                   (12UL)         /*!< NTC (Bit 12)                                          */
+ #define R_GMAC0_MAC_MDIO_Address_NTC_Msk                                   (0x7000UL)     /*!< NTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MAC_MDIO_Address_RDA_Pos                                   (16UL)         /*!< RDA (Bit 16)                                          */
+ #define R_GMAC0_MAC_MDIO_Address_RDA_Msk                                   (0x1f0000UL)   /*!< RDA (Bitfield-Mask: 0x1f)                             */
+ #define R_GMAC0_MAC_MDIO_Address_PA_Pos                                    (21UL)         /*!< PA (Bit 21)                                           */
+ #define R_GMAC0_MAC_MDIO_Address_PA_Msk                                    (0x3e00000UL)  /*!< PA (Bitfield-Mask: 0x1f)                              */
+ #define R_GMAC0_MAC_MDIO_Address_BTB_Pos                                   (26UL)         /*!< BTB (Bit 26)                                          */
+ #define R_GMAC0_MAC_MDIO_Address_BTB_Msk                                   (0x4000000UL)  /*!< BTB (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_MDIO_Address_PSE_Pos                                   (27UL)         /*!< PSE (Bit 27)                                          */
+ #define R_GMAC0_MAC_MDIO_Address_PSE_Msk                                   (0x8000000UL)  /*!< PSE (Bitfield-Mask: 0x01)                             */
+/* =====================================================  MAC_MDIO_Data  ===================================================== */
+ #define R_GMAC0_MAC_MDIO_Data_GD_Pos                                       (0UL)          /*!< GD (Bit 0)                                            */
+ #define R_GMAC0_MAC_MDIO_Data_GD_Msk                                       (0xffffUL)     /*!< GD (Bitfield-Mask: 0xffff)                            */
+ #define R_GMAC0_MAC_MDIO_Data_RA_Pos                                       (16UL)         /*!< RA (Bit 16)                                           */
+ #define R_GMAC0_MAC_MDIO_Data_RA_Msk                                       (0xffff0000UL) /*!< RA (Bitfield-Mask: 0xffff)                            */
+/* ====================================================  MAC_ARP_Address  ==================================================== */
+ #define R_GMAC0_MAC_ARP_Address_ARPPA_Pos                                  (0UL)          /*!< ARPPA (Bit 0)                                         */
+ #define R_GMAC0_MAC_ARP_Address_ARPPA_Msk                                  (0xffffffffUL) /*!< ARPPA (Bitfield-Mask: 0xffffffff)                     */
+/* ====================================================  MAC_CSR_SW_Ctrl  ==================================================== */
+ #define R_GMAC0_MAC_CSR_SW_Ctrl_RCWE_Pos                                   (0UL)          /*!< RCWE (Bit 0)                                          */
+ #define R_GMAC0_MAC_CSR_SW_Ctrl_RCWE_Msk                                   (0x1UL)        /*!< RCWE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_CSR_SW_Ctrl_SEEN_Pos                                   (8UL)          /*!< SEEN (Bit 8)                                          */
+ #define R_GMAC0_MAC_CSR_SW_Ctrl_SEEN_Msk                                   (0x100UL)      /*!< SEEN (Bitfield-Mask: 0x01)                            */
+/* ===================================================  MAC_FPE_CTRL_STS  ==================================================== */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_EFPE_Pos                                  (0UL)          /*!< EFPE (Bit 0)                                          */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_EFPE_Msk                                  (0x1UL)        /*!< EFPE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_SVER_Pos                                  (1UL)          /*!< SVER (Bit 1)                                          */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_SVER_Msk                                  (0x2UL)        /*!< SVER (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_SRSP_Pos                                  (2UL)          /*!< SRSP (Bit 2)                                          */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_SRSP_Msk                                  (0x4UL)        /*!< SRSP (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_S1_SET_0_Pos                              (3UL)          /*!< S1_SET_0 (Bit 3)                                      */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_S1_SET_0_Msk                              (0x8UL)        /*!< S1_SET_0 (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_RVER_Pos                                  (16UL)         /*!< RVER (Bit 16)                                         */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_RVER_Msk                                  (0x10000UL)    /*!< RVER (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_RRSP_Pos                                  (17UL)         /*!< RRSP (Bit 17)                                         */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_RRSP_Msk                                  (0x20000UL)    /*!< RRSP (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_TVER_Pos                                  (18UL)         /*!< TVER (Bit 18)                                         */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_TVER_Msk                                  (0x40000UL)    /*!< TVER (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_TRSP_Pos                                  (19UL)         /*!< TRSP (Bit 19)                                         */
+ #define R_GMAC0_MAC_FPE_CTRL_STS_TRSP_Msk                                  (0x80000UL)    /*!< TRSP (Bitfield-Mask: 0x01)                            */
+/* =====================================================  MAC_Ext_Cfg1  ====================================================== */
+ #define R_GMAC0_MAC_Ext_Cfg1_SPLOFST_Pos                                   (0UL)          /*!< SPLOFST (Bit 0)                                       */
+ #define R_GMAC0_MAC_Ext_Cfg1_SPLOFST_Msk                                   (0x7fUL)       /*!< SPLOFST (Bitfield-Mask: 0x7f)                         */
+ #define R_GMAC0_MAC_Ext_Cfg1_SPLM_Pos                                      (8UL)          /*!< SPLM (Bit 8)                                          */
+ #define R_GMAC0_MAC_Ext_Cfg1_SPLM_Msk                                      (0x300UL)      /*!< SPLM (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC0_MAC_Ext_Cfg1_SAVO_Pos                                      (16UL)         /*!< SAVO (Bit 16)                                         */
+ #define R_GMAC0_MAC_Ext_Cfg1_SAVO_Msk                                      (0x7f0000UL)   /*!< SAVO (Bitfield-Mask: 0x7f)                            */
+ #define R_GMAC0_MAC_Ext_Cfg1_SAVE_Pos                                      (24UL)         /*!< SAVE (Bit 24)                                         */
+ #define R_GMAC0_MAC_Ext_Cfg1_SAVE_Msk                                      (0x1000000UL)  /*!< SAVE (Bitfield-Mask: 0x01)                            */
+/* ===================================================  MAC_ADDRESS0_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS0_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS0_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS0_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS0_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS0_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS0_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS0_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS0_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS0_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS1_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS1_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS2_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS2_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS3_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS3_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS4_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS4_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS5_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS5_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS6_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS6_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS7_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS7_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS8_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS8_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS9_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS9_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS10_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS10_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS11_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS11_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS12_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS12_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS13_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS13_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS14_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS14_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS15_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS15_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS16_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS16_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS17_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS17_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS18_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS18_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS19_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS19_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS20_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS20_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS21_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS21_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS22_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS22_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS23_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS23_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS24_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS24_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS25_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS25_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS26_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS26_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS27_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS27_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS28_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS28_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS29_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS29_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS30_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS30_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS31_HIGH  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC0_MAC_ADDRESS31_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS1_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS1_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS1_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS2_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS2_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS2_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS3_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS3_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS3_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS4_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS4_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS4_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS5_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS5_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS5_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS6_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS6_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS6_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS7_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS7_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS7_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS8_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS8_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS8_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS9_LOW  ==================================================== */
+ #define R_GMAC0_MAC_ADDRESS9_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS9_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS10_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS10_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS10_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS11_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS11_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS11_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS12_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS12_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS12_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS13_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS13_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS13_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS14_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS14_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS14_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS15_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS15_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS15_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS16_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS16_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS16_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS17_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS17_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS17_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS18_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS18_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS18_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS19_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS19_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS19_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS20_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS20_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS20_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS21_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS21_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS21_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS22_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS22_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS22_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS23_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS23_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS23_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS24_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS24_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS24_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS25_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS25_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS25_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS26_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS26_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS26_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS27_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS27_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS27_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS28_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS28_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS28_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS29_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS29_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS29_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS30_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS30_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS30_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS31_LOW  =================================================== */
+ #define R_GMAC0_MAC_ADDRESS31_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC0_MAC_ADDRESS31_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ======================================================  MMC_Control  ====================================================== */
+ #define R_GMAC0_MMC_Control_CNTRST_Pos                                     (0UL)          /*!< CNTRST (Bit 0)                                        */
+ #define R_GMAC0_MMC_Control_CNTRST_Msk                                     (0x1UL)        /*!< CNTRST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MMC_Control_CNTSTOPRO_Pos                                  (1UL)          /*!< CNTSTOPRO (Bit 1)                                     */
+ #define R_GMAC0_MMC_Control_CNTSTOPRO_Msk                                  (0x2UL)        /*!< CNTSTOPRO (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Control_RSTONRD_Pos                                    (2UL)          /*!< RSTONRD (Bit 2)                                       */
+ #define R_GMAC0_MMC_Control_RSTONRD_Msk                                    (0x4UL)        /*!< RSTONRD (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MMC_Control_CNTFREEZ_Pos                                   (3UL)          /*!< CNTFREEZ (Bit 3)                                      */
+ #define R_GMAC0_MMC_Control_CNTFREEZ_Msk                                   (0x8UL)        /*!< CNTFREEZ (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Control_CNTPRST_Pos                                    (4UL)          /*!< CNTPRST (Bit 4)                                       */
+ #define R_GMAC0_MMC_Control_CNTPRST_Msk                                    (0x10UL)       /*!< CNTPRST (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MMC_Control_CNTPRSTLVL_Pos                                 (5UL)          /*!< CNTPRSTLVL (Bit 5)                                    */
+ #define R_GMAC0_MMC_Control_CNTPRSTLVL_Msk                                 (0x20UL)       /*!< CNTPRSTLVL (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Control_UCDBC_Pos                                      (8UL)          /*!< UCDBC (Bit 8)                                         */
+ #define R_GMAC0_MMC_Control_UCDBC_Msk                                      (0x100UL)      /*!< UCDBC (Bitfield-Mask: 0x01)                           */
+/* ===================================================  MMC_Rx_Interrupt  ==================================================== */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXGBPKTIS_Pos                             (0UL)          /*!< RXGBPKTIS (Bit 0)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXGBPKTIS_Msk                             (0x1UL)        /*!< RXGBPKTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXGBOCTIS_Pos                             (1UL)          /*!< RXGBOCTIS (Bit 1)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXGBOCTIS_Msk                             (0x2UL)        /*!< RXGBOCTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXGOCTIS_Pos                              (2UL)          /*!< RXGOCTIS (Bit 2)                                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXGOCTIS_Msk                              (0x4UL)        /*!< RXGOCTIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXBCGPIS_Pos                              (3UL)          /*!< RXBCGPIS (Bit 3)                                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXBCGPIS_Msk                              (0x8UL)        /*!< RXBCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXMCGPIS_Pos                              (4UL)          /*!< RXMCGPIS (Bit 4)                                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXMCGPIS_Msk                              (0x10UL)       /*!< RXMCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXCRCERPIS_Pos                            (5UL)          /*!< RXCRCERPIS (Bit 5)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXCRCERPIS_Msk                            (0x20UL)       /*!< RXCRCERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXALGNERPIS_Pos                           (6UL)          /*!< RXALGNERPIS (Bit 6)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXALGNERPIS_Msk                           (0x40UL)       /*!< RXALGNERPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXRUNTPIS_Pos                             (7UL)          /*!< RXRUNTPIS (Bit 7)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXRUNTPIS_Msk                             (0x80UL)       /*!< RXRUNTPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXJABERPIS_Pos                            (8UL)          /*!< RXJABERPIS (Bit 8)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXJABERPIS_Msk                            (0x100UL)      /*!< RXJABERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXUSIZEGPIS_Pos                           (9UL)          /*!< RXUSIZEGPIS (Bit 9)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXUSIZEGPIS_Msk                           (0x200UL)      /*!< RXUSIZEGPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXOSIZEGPIS_Pos                           (10UL)         /*!< RXOSIZEGPIS (Bit 10)                                  */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXOSIZEGPIS_Msk                           (0x400UL)      /*!< RXOSIZEGPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX64OCTGBPIS_Pos                          (11UL)         /*!< RX64OCTGBPIS (Bit 11)                                 */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX64OCTGBPIS_Msk                          (0x800UL)      /*!< RX64OCTGBPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX65T127OCTGBPIS_Pos                      (12UL)         /*!< RX65T127OCTGBPIS (Bit 12)                             */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX65T127OCTGBPIS_Msk                      (0x1000UL)     /*!< RX65T127OCTGBPIS (Bitfield-Mask: 0x01)                */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX128T255OCTGBPIS_Pos                     (13UL)         /*!< RX128T255OCTGBPIS (Bit 13)                            */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX128T255OCTGBPIS_Msk                     (0x2000UL)     /*!< RX128T255OCTGBPIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX256T511OCTGBPIS_Pos                     (14UL)         /*!< RX256T511OCTGBPIS (Bit 14)                            */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX256T511OCTGBPIS_Msk                     (0x4000UL)     /*!< RX256T511OCTGBPIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX512T1023OCTGBPIS_Pos                    (15UL)         /*!< RX512T1023OCTGBPIS (Bit 15)                           */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX512T1023OCTGBPIS_Msk                    (0x8000UL)     /*!< RX512T1023OCTGBPIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX1024TMAXOCTGBPIS_Pos                    (16UL)         /*!< RX1024TMAXOCTGBPIS (Bit 16)                           */
+ #define R_GMAC0_MMC_Rx_Interrupt_RX1024TMAXOCTGBPIS_Msk                    (0x10000UL)    /*!< RX1024TMAXOCTGBPIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXUCGPIS_Pos                              (17UL)         /*!< RXUCGPIS (Bit 17)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXUCGPIS_Msk                              (0x20000UL)    /*!< RXUCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXLENERPIS_Pos                            (18UL)         /*!< RXLENERPIS (Bit 18)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXLENERPIS_Msk                            (0x40000UL)    /*!< RXLENERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXORANGEPIS_Pos                           (19UL)         /*!< RXORANGEPIS (Bit 19)                                  */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXORANGEPIS_Msk                           (0x80000UL)    /*!< RXORANGEPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXPAUSPIS_Pos                             (20UL)         /*!< RXPAUSPIS (Bit 20)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXPAUSPIS_Msk                             (0x100000UL)   /*!< RXPAUSPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXFOVPIS_Pos                              (21UL)         /*!< RXFOVPIS (Bit 21)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXFOVPIS_Msk                              (0x200000UL)   /*!< RXFOVPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXVLANGBPIS_Pos                           (22UL)         /*!< RXVLANGBPIS (Bit 22)                                  */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXVLANGBPIS_Msk                           (0x400000UL)   /*!< RXVLANGBPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXWDOGPIS_Pos                             (23UL)         /*!< RXWDOGPIS (Bit 23)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXWDOGPIS_Msk                             (0x800000UL)   /*!< RXWDOGPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXRCVERRPIS_Pos                           (24UL)         /*!< RXRCVERRPIS (Bit 24)                                  */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXRCVERRPIS_Msk                           (0x1000000UL)  /*!< RXRCVERRPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXCTRLPIS_Pos                             (25UL)         /*!< RXCTRLPIS (Bit 25)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXCTRLPIS_Msk                             (0x2000000UL)  /*!< RXCTRLPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXLPIUSCIS_Pos                            (26UL)         /*!< RXLPIUSCIS (Bit 26)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXLPIUSCIS_Msk                            (0x4000000UL)  /*!< RXLPIUSCIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXLPITRCIS_Pos                            (27UL)         /*!< RXLPITRCIS (Bit 27)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_RXLPITRCIS_Msk                            (0x8000000UL)  /*!< RXLPITRCIS (Bitfield-Mask: 0x01)                      */
+/* ===================================================  MMC_Tx_Interrupt  ==================================================== */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXGBOCTIS_Pos                             (0UL)          /*!< TXGBOCTIS (Bit 0)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXGBOCTIS_Msk                             (0x1UL)        /*!< TXGBOCTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXGBPKTIS_Pos                             (1UL)          /*!< TXGBPKTIS (Bit 1)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXGBPKTIS_Msk                             (0x2UL)        /*!< TXGBPKTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXBCGPIS_Pos                              (2UL)          /*!< TXBCGPIS (Bit 2)                                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXBCGPIS_Msk                              (0x4UL)        /*!< TXBCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXMCGPIS_Pos                              (3UL)          /*!< TXMCGPIS (Bit 3)                                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXMCGPIS_Msk                              (0x8UL)        /*!< TXMCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX64OCTGBPIS_Pos                          (4UL)          /*!< TX64OCTGBPIS (Bit 4)                                  */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX64OCTGBPIS_Msk                          (0x10UL)       /*!< TX64OCTGBPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX65T127OCTGBPIS_Pos                      (5UL)          /*!< TX65T127OCTGBPIS (Bit 5)                              */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX65T127OCTGBPIS_Msk                      (0x20UL)       /*!< TX65T127OCTGBPIS (Bitfield-Mask: 0x01)                */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX128T255OCTGBPIS_Pos                     (6UL)          /*!< TX128T255OCTGBPIS (Bit 6)                             */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX128T255OCTGBPIS_Msk                     (0x40UL)       /*!< TX128T255OCTGBPIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX256T511OCTGBPIS_Pos                     (7UL)          /*!< TX256T511OCTGBPIS (Bit 7)                             */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX256T511OCTGBPIS_Msk                     (0x80UL)       /*!< TX256T511OCTGBPIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX512T1023OCTGBPIS_Pos                    (8UL)          /*!< TX512T1023OCTGBPIS (Bit 8)                            */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX512T1023OCTGBPIS_Msk                    (0x100UL)      /*!< TX512T1023OCTGBPIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX1024TMAXOCTGBPIS_Pos                    (9UL)          /*!< TX1024TMAXOCTGBPIS (Bit 9)                            */
+ #define R_GMAC0_MMC_Tx_Interrupt_TX1024TMAXOCTGBPIS_Msk                    (0x200UL)      /*!< TX1024TMAXOCTGBPIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXUCGBPIS_Pos                             (10UL)         /*!< TXUCGBPIS (Bit 10)                                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXUCGBPIS_Msk                             (0x400UL)      /*!< TXUCGBPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXMCGBPIS_Pos                             (11UL)         /*!< TXMCGBPIS (Bit 11)                                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXMCGBPIS_Msk                             (0x800UL)      /*!< TXMCGBPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXBCGBPIS_Pos                             (12UL)         /*!< TXBCGBPIS (Bit 12)                                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXBCGBPIS_Msk                             (0x1000UL)     /*!< TXBCGBPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXUFLOWERPIS_Pos                          (13UL)         /*!< TXUFLOWERPIS (Bit 13)                                 */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXUFLOWERPIS_Msk                          (0x2000UL)     /*!< TXUFLOWERPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXSCOLGPIS_Pos                            (14UL)         /*!< TXSCOLGPIS (Bit 14)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXSCOLGPIS_Msk                            (0x4000UL)     /*!< TXSCOLGPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXMCOLGPIS_Pos                            (15UL)         /*!< TXMCOLGPIS (Bit 15)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXMCOLGPIS_Msk                            (0x8000UL)     /*!< TXMCOLGPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXDEFPIS_Pos                              (16UL)         /*!< TXDEFPIS (Bit 16)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXDEFPIS_Msk                              (0x10000UL)    /*!< TXDEFPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXLATCOLPIS_Pos                           (17UL)         /*!< TXLATCOLPIS (Bit 17)                                  */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXLATCOLPIS_Msk                           (0x20000UL)    /*!< TXLATCOLPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXEXCOLPIS_Pos                            (18UL)         /*!< TXEXCOLPIS (Bit 18)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXEXCOLPIS_Msk                            (0x40000UL)    /*!< TXEXCOLPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXCARERPIS_Pos                            (19UL)         /*!< TXCARERPIS (Bit 19)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXCARERPIS_Msk                            (0x80000UL)    /*!< TXCARERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXGOCTIS_Pos                              (20UL)         /*!< TXGOCTIS (Bit 20)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXGOCTIS_Msk                              (0x100000UL)   /*!< TXGOCTIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXGPKTIS_Pos                              (21UL)         /*!< TXGPKTIS (Bit 21)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXGPKTIS_Msk                              (0x200000UL)   /*!< TXGPKTIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXEXDEFPIS_Pos                            (22UL)         /*!< TXEXDEFPIS (Bit 22)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXEXDEFPIS_Msk                            (0x400000UL)   /*!< TXEXDEFPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXPAUSPIS_Pos                             (23UL)         /*!< TXPAUSPIS (Bit 23)                                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXPAUSPIS_Msk                             (0x800000UL)   /*!< TXPAUSPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXVLANGPIS_Pos                            (24UL)         /*!< TXVLANGPIS (Bit 24)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXVLANGPIS_Msk                            (0x1000000UL)  /*!< TXVLANGPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXOSIZEGPIS_Pos                           (25UL)         /*!< TXOSIZEGPIS (Bit 25)                                  */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXOSIZEGPIS_Msk                           (0x2000000UL)  /*!< TXOSIZEGPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXLPIUSCIS_Pos                            (26UL)         /*!< TXLPIUSCIS (Bit 26)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXLPIUSCIS_Msk                            (0x4000000UL)  /*!< TXLPIUSCIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXLPITRCIS_Pos                            (27UL)         /*!< TXLPITRCIS (Bit 27)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_TXLPITRCIS_Msk                            (0x8000000UL)  /*!< TXLPITRCIS (Bitfield-Mask: 0x01)                      */
+/* =================================================  MMC_Rx_Interrupt_Mask  ================================================= */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXGBPKTIM_Pos                        (0UL)          /*!< RXGBPKTIM (Bit 0)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXGBPKTIM_Msk                        (0x1UL)        /*!< RXGBPKTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXGBOCTIM_Pos                        (1UL)          /*!< RXGBOCTIM (Bit 1)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXGBOCTIM_Msk                        (0x2UL)        /*!< RXGBOCTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXGOCTIM_Pos                         (2UL)          /*!< RXGOCTIM (Bit 2)                                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXGOCTIM_Msk                         (0x4UL)        /*!< RXGOCTIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXBCGPIM_Pos                         (3UL)          /*!< RXBCGPIM (Bit 3)                                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXBCGPIM_Msk                         (0x8UL)        /*!< RXBCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXMCGPIM_Pos                         (4UL)          /*!< RXMCGPIM (Bit 4)                                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXMCGPIM_Msk                         (0x10UL)       /*!< RXMCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXCRCERPIM_Pos                       (5UL)          /*!< RXCRCERPIM (Bit 5)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXCRCERPIM_Msk                       (0x20UL)       /*!< RXCRCERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXALGNERPIM_Pos                      (6UL)          /*!< RXALGNERPIM (Bit 6)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXALGNERPIM_Msk                      (0x40UL)       /*!< RXALGNERPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXRUNTPIM_Pos                        (7UL)          /*!< RXRUNTPIM (Bit 7)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXRUNTPIM_Msk                        (0x80UL)       /*!< RXRUNTPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXJABERPIM_Pos                       (8UL)          /*!< RXJABERPIM (Bit 8)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXJABERPIM_Msk                       (0x100UL)      /*!< RXJABERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXUSIZEGPIM_Pos                      (9UL)          /*!< RXUSIZEGPIM (Bit 9)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXUSIZEGPIM_Msk                      (0x200UL)      /*!< RXUSIZEGPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXOSIZEGPIM_Pos                      (10UL)         /*!< RXOSIZEGPIM (Bit 10)                                  */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXOSIZEGPIM_Msk                      (0x400UL)      /*!< RXOSIZEGPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX64OCTGBPIM_Pos                     (11UL)         /*!< RX64OCTGBPIM (Bit 11)                                 */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX64OCTGBPIM_Msk                     (0x800UL)      /*!< RX64OCTGBPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX65T127OCTGBPIM_Pos                 (12UL)         /*!< RX65T127OCTGBPIM (Bit 12)                             */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX65T127OCTGBPIM_Msk                 (0x1000UL)     /*!< RX65T127OCTGBPIM (Bitfield-Mask: 0x01)              */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX128T255OCTGBPIM_Pos                (13UL)         /*!< RX128T255OCTGBPIM (Bit 13)                            */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX128T255OCTGBPIM_Msk                (0x2000UL)     /*!< RX128T255OCTGBPIM (Bitfield-Mask: 0x01)            */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX256T511OCTGBPIM_Pos                (14UL)         /*!< RX256T511OCTGBPIM (Bit 14)                            */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX256T511OCTGBPIM_Msk                (0x4000UL)     /*!< RX256T511OCTGBPIM (Bitfield-Mask: 0x01)            */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX512T1023OCTGBPIM_Pos               (15UL)         /*!< RX512T1023OCTGBPIM (Bit 15)                           */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX512T1023OCTGBPIM_Msk               (0x8000UL)     /*!< RX512T1023OCTGBPIM (Bitfield-Mask: 0x01)          */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX1024TMAXOCTGBPIM_Pos               (16UL)         /*!< RX1024TMAXOCTGBPIM (Bit 16)                           */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RX1024TMAXOCTGBPIM_Msk               (0x10000UL)    /*!< RX1024TMAXOCTGBPIM (Bitfield-Mask: 0x01)         */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXUCGPIM_Pos                         (17UL)         /*!< RXUCGPIM (Bit 17)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXUCGPIM_Msk                         (0x20000UL)    /*!< RXUCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXLENERPIM_Pos                       (18UL)         /*!< RXLENERPIM (Bit 18)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXLENERPIM_Msk                       (0x40000UL)    /*!< RXLENERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXORANGEPIM_Pos                      (19UL)         /*!< RXORANGEPIM (Bit 19)                                  */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXORANGEPIM_Msk                      (0x80000UL)    /*!< RXORANGEPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXPAUSPIM_Pos                        (20UL)         /*!< RXPAUSPIM (Bit 20)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXPAUSPIM_Msk                        (0x100000UL)   /*!< RXPAUSPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXFOVPIM_Pos                         (21UL)         /*!< RXFOVPIM (Bit 21)                                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXFOVPIM_Msk                         (0x200000UL)   /*!< RXFOVPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXVLANGBPIM_Pos                      (22UL)         /*!< RXVLANGBPIM (Bit 22)                                  */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXVLANGBPIM_Msk                      (0x400000UL)   /*!< RXVLANGBPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXWDOGPIM_Pos                        (23UL)         /*!< RXWDOGPIM (Bit 23)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXWDOGPIM_Msk                        (0x800000UL)   /*!< RXWDOGPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXRCVERRPIM_Pos                      (24UL)         /*!< RXRCVERRPIM (Bit 24)                                  */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXRCVERRPIM_Msk                      (0x1000000UL)  /*!< RXRCVERRPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXCTRLPIM_Pos                        (25UL)         /*!< RXCTRLPIM (Bit 25)                                    */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXCTRLPIM_Msk                        (0x2000000UL)  /*!< RXCTRLPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXLPIUSCIM_Pos                       (26UL)         /*!< RXLPIUSCIM (Bit 26)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXLPIUSCIM_Msk                       (0x4000000UL)  /*!< RXLPIUSCIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXLPITRCIM_Pos                       (27UL)         /*!< RXLPITRCIM (Bit 27)                                   */
+ #define R_GMAC0_MMC_Rx_Interrupt_Mask_RXLPITRCIM_Msk                       (0x8000000UL)  /*!< RXLPITRCIM (Bitfield-Mask: 0x01)                      */
+/* =================================================  MMC_Tx_Interrupt_Mask  ================================================= */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXGBOCTIM_Pos                        (0UL)          /*!< TXGBOCTIM (Bit 0)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXGBOCTIM_Msk                        (0x1UL)        /*!< TXGBOCTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXGBPKTIM_Pos                        (1UL)          /*!< TXGBPKTIM (Bit 1)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXGBPKTIM_Msk                        (0x2UL)        /*!< TXGBPKTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXBCGPIM_Pos                         (2UL)          /*!< TXBCGPIM (Bit 2)                                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXBCGPIM_Msk                         (0x4UL)        /*!< TXBCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXMCGPIM_Pos                         (3UL)          /*!< TXMCGPIM (Bit 3)                                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXMCGPIM_Msk                         (0x8UL)        /*!< TXMCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX64OCTGBPIM_Pos                     (4UL)          /*!< TX64OCTGBPIM (Bit 4)                                  */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX64OCTGBPIM_Msk                     (0x10UL)       /*!< TX64OCTGBPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX65T127OCTGBPIM_Pos                 (5UL)          /*!< TX65T127OCTGBPIM (Bit 5)                              */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX65T127OCTGBPIM_Msk                 (0x20UL)       /*!< TX65T127OCTGBPIM (Bitfield-Mask: 0x01)                */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX128T255OCTGBPIM_Pos                (6UL)          /*!< TX128T255OCTGBPIM (Bit 6)                             */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX128T255OCTGBPIM_Msk                (0x40UL)       /*!< TX128T255OCTGBPIM (Bitfield-Mask: 0x01)              */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX256T511OCTGBPIM_Pos                (7UL)          /*!< TX256T511OCTGBPIM (Bit 7)                             */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX256T511OCTGBPIM_Msk                (0x80UL)       /*!< TX256T511OCTGBPIM (Bitfield-Mask: 0x01)              */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX512T1023OCTGBPIM_Pos               (8UL)          /*!< TX512T1023OCTGBPIM (Bit 8)                            */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX512T1023OCTGBPIM_Msk               (0x100UL)      /*!< TX512T1023OCTGBPIM (Bitfield-Mask: 0x01)           */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX1024TMAXOCTGBPIM_Pos               (9UL)          /*!< TX1024TMAXOCTGBPIM (Bit 9)                            */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TX1024TMAXOCTGBPIM_Msk               (0x200UL)      /*!< TX1024TMAXOCTGBPIM (Bitfield-Mask: 0x01)           */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXUCGBPIM_Pos                        (10UL)         /*!< TXUCGBPIM (Bit 10)                                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXUCGBPIM_Msk                        (0x400UL)      /*!< TXUCGBPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXMCGBPIM_Pos                        (11UL)         /*!< TXMCGBPIM (Bit 11)                                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXMCGBPIM_Msk                        (0x800UL)      /*!< TXMCGBPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXBCGBPIM_Pos                        (12UL)         /*!< TXBCGBPIM (Bit 12)                                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXBCGBPIM_Msk                        (0x1000UL)     /*!< TXBCGBPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXUFLOWERPIM_Pos                     (13UL)         /*!< TXUFLOWERPIM (Bit 13)                                 */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXUFLOWERPIM_Msk                     (0x2000UL)     /*!< TXUFLOWERPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXSCOLGPIM_Pos                       (14UL)         /*!< TXSCOLGPIM (Bit 14)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXSCOLGPIM_Msk                       (0x4000UL)     /*!< TXSCOLGPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXMCOLGPIM_Pos                       (15UL)         /*!< TXMCOLGPIM (Bit 15)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXMCOLGPIM_Msk                       (0x8000UL)     /*!< TXMCOLGPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXDEFPIM_Pos                         (16UL)         /*!< TXDEFPIM (Bit 16)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXDEFPIM_Msk                         (0x10000UL)    /*!< TXDEFPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXLATCOLPIM_Pos                      (17UL)         /*!< TXLATCOLPIM (Bit 17)                                  */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXLATCOLPIM_Msk                      (0x20000UL)    /*!< TXLATCOLPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXEXCOLPIM_Pos                       (18UL)         /*!< TXEXCOLPIM (Bit 18)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXEXCOLPIM_Msk                       (0x40000UL)    /*!< TXEXCOLPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXCARERPIM_Pos                       (19UL)         /*!< TXCARERPIM (Bit 19)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXCARERPIM_Msk                       (0x80000UL)    /*!< TXCARERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXGOCTIM_Pos                         (20UL)         /*!< TXGOCTIM (Bit 20)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXGOCTIM_Msk                         (0x100000UL)   /*!< TXGOCTIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXGPKTIM_Pos                         (21UL)         /*!< TXGPKTIM (Bit 21)                                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXGPKTIM_Msk                         (0x200000UL)   /*!< TXGPKTIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXEXDEFPIM_Pos                       (22UL)         /*!< TXEXDEFPIM (Bit 22)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXEXDEFPIM_Msk                       (0x400000UL)   /*!< TXEXDEFPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXPAUSPIM_Pos                        (23UL)         /*!< TXPAUSPIM (Bit 23)                                    */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXPAUSPIM_Msk                        (0x800000UL)   /*!< TXPAUSPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXVLANGPIM_Pos                       (24UL)         /*!< TXVLANGPIM (Bit 24)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXVLANGPIM_Msk                       (0x1000000UL)  /*!< TXVLANGPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXOSIZEGPIM_Pos                      (25UL)         /*!< TXOSIZEGPIM (Bit 25)                                  */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXOSIZEGPIM_Msk                      (0x2000000UL)  /*!< TXOSIZEGPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXLPIUSCIM_Pos                       (26UL)         /*!< TXLPIUSCIM (Bit 26)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXLPIUSCIM_Msk                       (0x4000000UL)  /*!< TXLPIUSCIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXLPITRCIM_Pos                       (27UL)         /*!< TXLPITRCIM (Bit 27)                                   */
+ #define R_GMAC0_MMC_Tx_Interrupt_Mask_TXLPITRCIM_Msk                       (0x8000000UL)  /*!< TXLPITRCIM (Bitfield-Mask: 0x01)                      */
+/* ================================================  Tx_Octet_Count_Good_Bad  ================================================ */
+ #define R_GMAC0_Tx_Octet_Count_Good_Bad_TXOCTGB_Pos                        (0UL)          /*!< TXOCTGB (Bit 0)                                       */
+ #define R_GMAC0_Tx_Octet_Count_Good_Bad_TXOCTGB_Msk                        (0xffffffffUL) /*!< TXOCTGB (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Tx_Packet_Count_Good_Bad  ================================================ */
+ #define R_GMAC0_Tx_Packet_Count_Good_Bad_TXPKTGB_Pos                       (0UL)          /*!< TXPKTGB (Bit 0)                                       */
+ #define R_GMAC0_Tx_Packet_Count_Good_Bad_TXPKTGB_Msk                       (0xffffffffUL) /*!< TXPKTGB (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Tx_Broadcast_Packets_Good  =============================================== */
+ #define R_GMAC0_Tx_Broadcast_Packets_Good_TXBCASTG_Pos                     (0UL)          /*!< TXBCASTG (Bit 0)                                      */
+ #define R_GMAC0_Tx_Broadcast_Packets_Good_TXBCASTG_Msk                     (0xffffffffUL) /*!< TXBCASTG (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  Tx_Multicast_Packets_Good  =============================================== */
+ #define R_GMAC0_Tx_Multicast_Packets_Good_TXMCASTG_Pos                     (0UL)          /*!< TXMCASTG (Bit 0)                                      */
+ #define R_GMAC0_Tx_Multicast_Packets_Good_TXMCASTG_Msk                     (0xffffffffUL) /*!< TXMCASTG (Bitfield-Mask: 0xffffffff)                */
+/* =============================================  Tx_64Octets_Packets_Good_Bad  ============================================== */
+ #define R_GMAC0_Tx_64Octets_Packets_Good_Bad_TX64OCTGB_Pos                 (0UL)          /*!< TX64OCTGB (Bit 0)                                     */
+ #define R_GMAC0_Tx_64Octets_Packets_Good_Bad_TX64OCTGB_Msk                 (0xffffffffUL) /*!< TX64OCTGB (Bitfield-Mask: 0xffffffff)           */
+/* ===========================================  Tx_65To127Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC0_Tx_65To127Octets_Packets_Good_Bad_TX65_127OCTGB_Pos        (0UL)          /*!< TX65_127OCTGB (Bit 0)                           */
+ #define R_GMAC0_Tx_65To127Octets_Packets_Good_Bad_TX65_127OCTGB_Msk        (0xffffffffUL) /*!< TX65_127OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_128To255Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC0_Tx_128To255Octets_Packets_Good_Bad_TX128_255OCTGB_Pos      (0UL)          /*!< TX128_255OCTGB (Bit 0)                        */
+ #define R_GMAC0_Tx_128To255Octets_Packets_Good_Bad_TX128_255OCTGB_Msk      (0xffffffffUL) /*!< TX128_255OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_256To511Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC0_Tx_256To511Octets_Packets_Good_Bad_TX256_511OCTGB_Pos      (0UL)          /*!< TX256_511OCTGB (Bit 0)                        */
+ #define R_GMAC0_Tx_256To511Octets_Packets_Good_Bad_TX256_511OCTGB_Msk      (0xffffffffUL) /*!< TX256_511OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_512To1023Octets_Packets_Good_Bad  ========================================== */
+ #define R_GMAC0_Tx_512To1023Octets_Packets_Good_Bad_TX512_1023OCTGB_Pos    (0UL)          /*!< TX512_1023OCTGB (Bit 0)                     */
+ #define R_GMAC0_Tx_512To1023Octets_Packets_Good_Bad_TX512_1023OCTGB_Msk    (0xffffffffUL) /*!< TX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_1024ToMaxOctets_Packets_Good_Bad  ========================================== */
+ #define R_GMAC0_Tx_1024ToMaxOctets_Packets_Good_Bad_TX1024_MAXOCTGB_Pos    (0UL)          /*!< TX1024_MAXOCTGB (Bit 0)                     */
+ #define R_GMAC0_Tx_1024ToMaxOctets_Packets_Good_Bad_TX1024_MAXOCTGB_Msk    (0xffffffffUL) /*!< TX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==============================================  Tx_Unicast_Packets_Good_Bad  ============================================== */
+ #define R_GMAC0_Tx_Unicast_Packets_Good_Bad_TXUCASTGB_Pos                  (0UL)          /*!< TXUCASTGB (Bit 0)                                     */
+ #define R_GMAC0_Tx_Unicast_Packets_Good_Bad_TXUCASTGB_Msk                  (0xffffffffUL) /*!< TXUCASTGB (Bitfield-Mask: 0xffffffff)            */
+/* =============================================  Tx_Multicast_Packets_Good_Bad  ============================================= */
+ #define R_GMAC0_Tx_Multicast_Packets_Good_Bad_TXMCASTGB_Pos                (0UL)          /*!< TXMCASTGB (Bit 0)                                     */
+ #define R_GMAC0_Tx_Multicast_Packets_Good_Bad_TXMCASTGB_Msk                (0xffffffffUL) /*!< TXMCASTGB (Bitfield-Mask: 0xffffffff)          */
+/* =============================================  Tx_Broadcast_Packets_Good_Bad  ============================================= */
+ #define R_GMAC0_Tx_Broadcast_Packets_Good_Bad_TXBCASTGB_Pos                (0UL)          /*!< TXBCASTGB (Bit 0)                                     */
+ #define R_GMAC0_Tx_Broadcast_Packets_Good_Bad_TXBCASTGB_Msk                (0xffffffffUL) /*!< TXBCASTGB (Bitfield-Mask: 0xffffffff)          */
+/* ==============================================  Tx_Underflow_Error_Packets  =============================================== */
+ #define R_GMAC0_Tx_Underflow_Error_Packets_TXUNDRFLW_Pos                   (0UL)          /*!< TXUNDRFLW (Bit 0)                                     */
+ #define R_GMAC0_Tx_Underflow_Error_Packets_TXUNDRFLW_Msk                   (0xffffffffUL) /*!< TXUNDRFLW (Bitfield-Mask: 0xffffffff)             */
+/* ===========================================  Tx_Single_Collision_Good_Packets  ============================================ */
+ #define R_GMAC0_Tx_Single_Collision_Good_Packets_TXSNGLCOLG_Pos            (0UL)          /*!< TXSNGLCOLG (Bit 0)                                  */
+ #define R_GMAC0_Tx_Single_Collision_Good_Packets_TXSNGLCOLG_Msk            (0xffffffffUL) /*!< TXSNGLCOLG (Bitfield-Mask: 0xffffffff)     */
+/* ==========================================  Tx_Multiple_Collision_Good_Packets  =========================================== */
+ #define R_GMAC0_Tx_Multiple_Collision_Good_Packets_TXMULTCOLG_Pos          (0UL)          /*!< TXMULTCOLG (Bit 0)                                */
+ #define R_GMAC0_Tx_Multiple_Collision_Good_Packets_TXMULTCOLG_Msk          (0xffffffffUL) /*!< TXMULTCOLG (Bitfield-Mask: 0xffffffff)   */
+/* ==================================================  Tx_Deferred_Packets  ================================================== */
+ #define R_GMAC0_Tx_Deferred_Packets_TXDEFRD_Pos                            (0UL)          /*!< TXDEFRD (Bit 0)                                       */
+ #define R_GMAC0_Tx_Deferred_Packets_TXDEFRD_Msk                            (0xffffffffUL) /*!< TXDEFRD (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Tx_Late_Collision_Packets  =============================================== */
+ #define R_GMAC0_Tx_Late_Collision_Packets_TXLATECOL_Pos                    (0UL)          /*!< TXLATECOL (Bit 0)                                     */
+ #define R_GMAC0_Tx_Late_Collision_Packets_TXLATECOL_Msk                    (0xffffffffUL) /*!< TXLATECOL (Bitfield-Mask: 0xffffffff)              */
+/* ============================================  Tx_Excessive_Collision_Packets  ============================================= */
+ #define R_GMAC0_Tx_Excessive_Collision_Packets_TXEXSCOL_Pos                (0UL)          /*!< TXEXSCOL (Bit 0)                                      */
+ #define R_GMAC0_Tx_Excessive_Collision_Packets_TXEXSCOL_Msk                (0xffffffffUL) /*!< TXEXSCOL (Bitfield-Mask: 0xffffffff)           */
+/* ===============================================  Tx_Carrier_Error_Packets  ================================================ */
+ #define R_GMAC0_Tx_Carrier_Error_Packets_TXCARR_Pos                        (0UL)          /*!< TXCARR (Bit 0)                                        */
+ #define R_GMAC0_Tx_Carrier_Error_Packets_TXCARR_Msk                        (0xffffffffUL) /*!< TXCARR (Bitfield-Mask: 0xffffffff)                    */
+/* ==================================================  Tx_Octet_Count_Good  ================================================== */
+ #define R_GMAC0_Tx_Octet_Count_Good_TXOCTG_Pos                             (0UL)          /*!< TXOCTG (Bit 0)                                        */
+ #define R_GMAC0_Tx_Octet_Count_Good_TXOCTG_Msk                             (0xffffffffUL) /*!< TXOCTG (Bitfield-Mask: 0xffffffff)                    */
+/* =================================================  Tx_Packet_Count_Good  ================================================== */
+ #define R_GMAC0_Tx_Packet_Count_Good_TXPKTG_Pos                            (0UL)          /*!< TXPKTG (Bit 0)                                        */
+ #define R_GMAC0_Tx_Packet_Count_Good_TXPKTG_Msk                            (0xffffffffUL) /*!< TXPKTG (Bitfield-Mask: 0xffffffff)                    */
+/* ==============================================  Tx_Excessive_Deferral_Error  ============================================== */
+ #define R_GMAC0_Tx_Excessive_Deferral_Error_TXEXSDEF_Pos                   (0UL)          /*!< TXEXSDEF (Bit 0)                                      */
+ #define R_GMAC0_Tx_Excessive_Deferral_Error_TXEXSDEF_Msk                   (0xffffffffUL) /*!< TXEXSDEF (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  Tx_Pause_Packets  ==================================================== */
+ #define R_GMAC0_Tx_Pause_Packets_TXPAUSE_Pos                               (0UL)          /*!< TXPAUSE (Bit 0)                                       */
+ #define R_GMAC0_Tx_Pause_Packets_TXPAUSE_Msk                               (0xffffffffUL) /*!< TXPAUSE (Bitfield-Mask: 0xffffffff)                   */
+/* =================================================  Tx_VLAN_Packets_Good  ================================================== */
+ #define R_GMAC0_Tx_VLAN_Packets_Good_TXVLANG_Pos                           (0UL)          /*!< TXVLANG (Bit 0)                                       */
+ #define R_GMAC0_Tx_VLAN_Packets_Good_TXVLANG_Msk                           (0xffffffffUL) /*!< TXVLANG (Bitfield-Mask: 0xffffffff)                   */
+/* =================================================  Tx_OSize_Packets_Good  ================================================= */
+ #define R_GMAC0_Tx_OSize_Packets_Good_TXOSIZG_Pos                          (0UL)          /*!< TXOSIZG (Bit 0)                                       */
+ #define R_GMAC0_Tx_OSize_Packets_Good_TXOSIZG_Msk                          (0xffffffffUL) /*!< TXOSIZG (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Rx_Packets_Count_Good_Bad  =============================================== */
+ #define R_GMAC0_Rx_Packets_Count_Good_Bad_RXPKTGB_Pos                      (0UL)          /*!< RXPKTGB (Bit 0)                                       */
+ #define R_GMAC0_Rx_Packets_Count_Good_Bad_RXPKTGB_Msk                      (0xffffffffUL) /*!< RXPKTGB (Bitfield-Mask: 0xffffffff)                  */
+/* ================================================  Rx_Octet_Count_Good_Bad  ================================================ */
+ #define R_GMAC0_Rx_Octet_Count_Good_Bad_RXOCTGB_Pos                        (0UL)          /*!< RXOCTGB (Bit 0)                                       */
+ #define R_GMAC0_Rx_Octet_Count_Good_Bad_RXOCTGB_Msk                        (0xffffffffUL) /*!< RXOCTGB (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  Rx_Octet_Count_Good  ================================================== */
+ #define R_GMAC0_Rx_Octet_Count_Good_RXOCTG_Pos                             (0UL)          /*!< RXOCTG (Bit 0)                                        */
+ #define R_GMAC0_Rx_Octet_Count_Good_RXOCTG_Msk                             (0xffffffffUL) /*!< RXOCTG (Bitfield-Mask: 0xffffffff)                    */
+/* ===============================================  Rx_Broadcast_Packets_Good  =============================================== */
+ #define R_GMAC0_Rx_Broadcast_Packets_Good_RXBCASTG_Pos                     (0UL)          /*!< RXBCASTG (Bit 0)                                      */
+ #define R_GMAC0_Rx_Broadcast_Packets_Good_RXBCASTG_Msk                     (0xffffffffUL) /*!< RXBCASTG (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  Rx_Multicast_Packets_Good  =============================================== */
+ #define R_GMAC0_Rx_Multicast_Packets_Good_RXMCASTG_Pos                     (0UL)          /*!< RXMCASTG (Bit 0)                                      */
+ #define R_GMAC0_Rx_Multicast_Packets_Good_RXMCASTG_Msk                     (0xffffffffUL) /*!< RXMCASTG (Bitfield-Mask: 0xffffffff)                */
+/* =================================================  Rx_CRC_Error_Packets  ================================================== */
+ #define R_GMAC0_Rx_CRC_Error_Packets_RXCRCERR_Pos                          (0UL)          /*!< RXCRCERR (Bit 0)                                      */
+ #define R_GMAC0_Rx_CRC_Error_Packets_RXCRCERR_Msk                          (0xffffffffUL) /*!< RXCRCERR (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  Rx_Alignment_Error_Packets  =============================================== */
+ #define R_GMAC0_Rx_Alignment_Error_Packets_RXALGNERR_Pos                   (0UL)          /*!< RXALGNERR (Bit 0)                                     */
+ #define R_GMAC0_Rx_Alignment_Error_Packets_RXALGNERR_Msk                   (0xffffffffUL) /*!< RXALGNERR (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  Rx_Runt_Error_Packets  ================================================= */
+ #define R_GMAC0_Rx_Runt_Error_Packets_RXRUNTERR_Pos                        (0UL)          /*!< RXRUNTERR (Bit 0)                                     */
+ #define R_GMAC0_Rx_Runt_Error_Packets_RXRUNTERR_Msk                        (0xffffffffUL) /*!< RXRUNTERR (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  Rx_Jabber_Error_Packets  ================================================ */
+ #define R_GMAC0_Rx_Jabber_Error_Packets_RXJABERR_Pos                       (0UL)          /*!< RXJABERR (Bit 0)                                      */
+ #define R_GMAC0_Rx_Jabber_Error_Packets_RXJABERR_Msk                       (0xffffffffUL) /*!< RXJABERR (Bitfield-Mask: 0xffffffff)                  */
+/* ===============================================  Rx_Undersize_Packets_Good  =============================================== */
+ #define R_GMAC0_Rx_Undersize_Packets_Good_RXUNDERSZG_Pos                   (0UL)          /*!< RXUNDERSZG (Bit 0)                                    */
+ #define R_GMAC0_Rx_Undersize_Packets_Good_RXUNDERSZG_Msk                   (0xffffffffUL) /*!< RXUNDERSZG (Bitfield-Mask: 0xffffffff)            */
+/* ===============================================  Rx_Oversize_Packets_Good  ================================================ */
+ #define R_GMAC0_Rx_Oversize_Packets_Good_RXOVERSZG_Pos                     (0UL)          /*!< RXOVERSZG (Bit 0)                                     */
+ #define R_GMAC0_Rx_Oversize_Packets_Good_RXOVERSZG_Msk                     (0xffffffffUL) /*!< RXOVERSZG (Bitfield-Mask: 0xffffffff)               */
+/* =============================================  Rx_64Octets_Packets_Good_Bad  ============================================== */
+ #define R_GMAC0_Rx_64Octets_Packets_Good_Bad_RX64OCTGB_Pos                 (0UL)          /*!< RX64OCTGB (Bit 0)                                     */
+ #define R_GMAC0_Rx_64Octets_Packets_Good_Bad_RX64OCTGB_Msk                 (0xffffffffUL) /*!< RX64OCTGB (Bitfield-Mask: 0xffffffff)           */
+/* ===========================================  Rx_65To127Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC0_Rx_65To127Octets_Packets_Good_Bad_RX65_127OCTGB_Pos        (0UL)          /*!< RX65_127OCTGB (Bit 0)                           */
+ #define R_GMAC0_Rx_65To127Octets_Packets_Good_Bad_RX65_127OCTGB_Msk        (0xffffffffUL) /*!< RX65_127OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_128To255Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC0_Rx_128To255Octets_Packets_Good_Bad_RX128_255OCTGB_Pos      (0UL)          /*!< RX128_255OCTGB (Bit 0)                        */
+ #define R_GMAC0_Rx_128To255Octets_Packets_Good_Bad_RX128_255OCTGB_Msk      (0xffffffffUL) /*!< RX128_255OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_256To511Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC0_Rx_256To511Octets_Packets_Good_Bad_RX256_511OCTGB_Pos      (0UL)          /*!< RX256_511OCTGB (Bit 0)                        */
+ #define R_GMAC0_Rx_256To511Octets_Packets_Good_Bad_RX256_511OCTGB_Msk      (0xffffffffUL) /*!< RX256_511OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_512To1023Octets_Packets_Good_Bad  ========================================== */
+ #define R_GMAC0_Rx_512To1023Octets_Packets_Good_Bad_RX512_1023OCTGB_Pos    (0UL)          /*!< RX512_1023OCTGB (Bit 0)                     */
+ #define R_GMAC0_Rx_512To1023Octets_Packets_Good_Bad_RX512_1023OCTGB_Msk    (0xffffffffUL) /*!< RX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_1024ToMaxOctets_Packets_Good_Bad  ========================================== */
+ #define R_GMAC0_Rx_1024ToMaxOctets_Packets_Good_Bad_RX1024_MAXOCTGB_Pos    (0UL)          /*!< RX1024_MAXOCTGB (Bit 0)                     */
+ #define R_GMAC0_Rx_1024ToMaxOctets_Packets_Good_Bad_RX1024_MAXOCTGB_Msk    (0xffffffffUL) /*!< RX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */
+/* ================================================  Rx_Unicast_Packets_Good  ================================================ */
+ #define R_GMAC0_Rx_Unicast_Packets_Good_RXUCASTG_Pos                       (0UL)          /*!< RXUCASTG (Bit 0)                                      */
+ #define R_GMAC0_Rx_Unicast_Packets_Good_RXUCASTG_Msk                       (0xffffffffUL) /*!< RXUCASTG (Bitfield-Mask: 0xffffffff)                  */
+/* ================================================  Rx_Length_Error_Packets  ================================================ */
+ #define R_GMAC0_Rx_Length_Error_Packets_RXLENERR_Pos                       (0UL)          /*!< RXLENERR (Bit 0)                                      */
+ #define R_GMAC0_Rx_Length_Error_Packets_RXLENERR_Msk                       (0xffffffffUL) /*!< RXLENERR (Bitfield-Mask: 0xffffffff)                  */
+/* =============================================  Rx_Out_Of_Range_Type_Packets  ============================================== */
+ #define R_GMAC0_Rx_Out_Of_Range_Type_Packets_RXOUTOFRNG_Pos                (0UL)          /*!< RXOUTOFRNG (Bit 0)                                    */
+ #define R_GMAC0_Rx_Out_Of_Range_Type_Packets_RXOUTOFRNG_Msk                (0xffffffffUL) /*!< RXOUTOFRNG (Bitfield-Mask: 0xffffffff)         */
+/* ===================================================  Rx_Pause_Packets  ==================================================== */
+ #define R_GMAC0_Rx_Pause_Packets_RXPAUSEPKT_Pos                            (0UL)          /*!< RXPAUSEPKT (Bit 0)                                    */
+ #define R_GMAC0_Rx_Pause_Packets_RXPAUSEPKT_Msk                            (0xffffffffUL) /*!< RXPAUSEPKT (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  Rx_FIFO_Overflow_Packets  ================================================ */
+ #define R_GMAC0_Rx_FIFO_Overflow_Packets_RXFIFOOVFL_Pos                    (0UL)          /*!< RXFIFOOVFL (Bit 0)                                    */
+ #define R_GMAC0_Rx_FIFO_Overflow_Packets_RXFIFOOVFL_Msk                    (0xffffffffUL) /*!< RXFIFOOVFL (Bitfield-Mask: 0xffffffff)             */
+/* ===============================================  Rx_VLAN_Packets_Good_Bad  ================================================ */
+ #define R_GMAC0_Rx_VLAN_Packets_Good_Bad_RXVLANPKTGB_Pos                   (0UL)          /*!< RXVLANPKTGB (Bit 0)                                   */
+ #define R_GMAC0_Rx_VLAN_Packets_Good_Bad_RXVLANPKTGB_Msk                   (0xffffffffUL) /*!< RXVLANPKTGB (Bitfield-Mask: 0xffffffff)           */
+/* ===============================================  Rx_Watchdog_Error_Packets  =============================================== */
+ #define R_GMAC0_Rx_Watchdog_Error_Packets_RXWDGERR_Pos                     (0UL)          /*!< RXWDGERR (Bit 0)                                      */
+ #define R_GMAC0_Rx_Watchdog_Error_Packets_RXWDGERR_Msk                     (0xffffffffUL) /*!< RXWDGERR (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  Rx_Receive_Error_Packets  ================================================ */
+ #define R_GMAC0_Rx_Receive_Error_Packets_RXRCVERR_Pos                      (0UL)          /*!< RXRCVERR (Bit 0)                                      */
+ #define R_GMAC0_Rx_Receive_Error_Packets_RXRCVERR_Msk                      (0xffffffffUL) /*!< RXRCVERR (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  Rx_Control_Packets_Good  ================================================ */
+ #define R_GMAC0_Rx_Control_Packets_Good_RXCTRLG_Pos                        (0UL)          /*!< RXCTRLG (Bit 0)                                       */
+ #define R_GMAC0_Rx_Control_Packets_Good_RXCTRLG_Msk                        (0xffffffffUL) /*!< RXCTRLG (Bitfield-Mask: 0xffffffff)                   */
+/* ===================================================  Tx_LPI_USEC_Cntr  ==================================================== */
+ #define R_GMAC0_Tx_LPI_USEC_Cntr_TXLPIUSC_Pos                              (0UL)          /*!< TXLPIUSC (Bit 0)                                      */
+ #define R_GMAC0_Tx_LPI_USEC_Cntr_TXLPIUSC_Msk                              (0xffffffffUL) /*!< TXLPIUSC (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  Tx_LPI_Tran_Cntr  ==================================================== */
+ #define R_GMAC0_Tx_LPI_Tran_Cntr_TXLPITRC_Pos                              (0UL)          /*!< TXLPITRC (Bit 0)                                      */
+ #define R_GMAC0_Tx_LPI_Tran_Cntr_TXLPITRC_Msk                              (0xffffffffUL) /*!< TXLPITRC (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  Rx_LPI_USEC_Cntr  ==================================================== */
+ #define R_GMAC0_Rx_LPI_USEC_Cntr_RXLPIUSC_Pos                              (0UL)          /*!< RXLPIUSC (Bit 0)                                      */
+ #define R_GMAC0_Rx_LPI_USEC_Cntr_RXLPIUSC_Msk                              (0xffffffffUL) /*!< RXLPIUSC (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  Rx_LPI_Tran_Cntr  ==================================================== */
+ #define R_GMAC0_Rx_LPI_Tran_Cntr_RXLPITRC_Pos                              (0UL)          /*!< RXLPITRC (Bit 0)                                      */
+ #define R_GMAC0_Rx_LPI_Tran_Cntr_RXLPITRC_Msk                              (0xffffffffUL) /*!< RXLPITRC (Bitfield-Mask: 0xffffffff)                  */
+/* ===============================================  MMC_IPC_Rx_Interrupt_Mask  =============================================== */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4GPIM_Pos                   (0UL)          /*!< RXIPV4GPIM (Bit 0)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4GPIM_Msk                   (0x1UL)        /*!< RXIPV4GPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4HERPIM_Pos                 (1UL)          /*!< RXIPV4HERPIM (Bit 1)                                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4HERPIM_Msk                 (0x2UL)        /*!< RXIPV4HERPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4NOPAYPIM_Pos               (2UL)          /*!< RXIPV4NOPAYPIM (Bit 2)                                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4NOPAYPIM_Msk               (0x4UL)        /*!< RXIPV4NOPAYPIM (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4FRAGPIM_Pos                (3UL)          /*!< RXIPV4FRAGPIM (Bit 3)                                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4FRAGPIM_Msk                (0x8UL)        /*!< RXIPV4FRAGPIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4UDSBLPIM_Pos               (4UL)          /*!< RXIPV4UDSBLPIM (Bit 4)                                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4UDSBLPIM_Msk               (0x10UL)       /*!< RXIPV4UDSBLPIM (Bitfield-Mask: 0x01)                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6GPIM_Pos                   (5UL)          /*!< RXIPV6GPIM (Bit 5)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6GPIM_Msk                   (0x20UL)       /*!< RXIPV6GPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6HERPIM_Pos                 (6UL)          /*!< RXIPV6HERPIM (Bit 6)                                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6HERPIM_Msk                 (0x40UL)       /*!< RXIPV6HERPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6NOPAYPIM_Pos               (7UL)          /*!< RXIPV6NOPAYPIM (Bit 7)                                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6NOPAYPIM_Msk               (0x80UL)       /*!< RXIPV6NOPAYPIM (Bitfield-Mask: 0x01)                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXUDPGPIM_Pos                    (8UL)          /*!< RXUDPGPIM (Bit 8)                                     */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXUDPGPIM_Msk                    (0x100UL)      /*!< RXUDPGPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXUDPERPIM_Pos                   (9UL)          /*!< RXUDPERPIM (Bit 9)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXUDPERPIM_Msk                   (0x200UL)      /*!< RXUDPERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXTCPGPIM_Pos                    (10UL)         /*!< RXTCPGPIM (Bit 10)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXTCPGPIM_Msk                    (0x400UL)      /*!< RXTCPGPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXTCPERPIM_Pos                   (11UL)         /*!< RXTCPERPIM (Bit 11)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXTCPERPIM_Msk                   (0x800UL)      /*!< RXTCPERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXICMPGPIM_Pos                   (12UL)         /*!< RXICMPGPIM (Bit 12)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXICMPGPIM_Msk                   (0x1000UL)     /*!< RXICMPGPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXICMPERPIM_Pos                  (13UL)         /*!< RXICMPERPIM (Bit 13)                                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXICMPERPIM_Msk                  (0x2000UL)     /*!< RXICMPERPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4GOIM_Pos                   (16UL)         /*!< RXIPV4GOIM (Bit 16)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4GOIM_Msk                   (0x10000UL)    /*!< RXIPV4GOIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4HEROIM_Pos                 (17UL)         /*!< RXIPV4HEROIM (Bit 17)                                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4HEROIM_Msk                 (0x20000UL)    /*!< RXIPV4HEROIM (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4NOPAYOIM_Pos               (18UL)         /*!< RXIPV4NOPAYOIM (Bit 18)                               */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4NOPAYOIM_Msk               (0x40000UL)    /*!< RXIPV4NOPAYOIM (Bitfield-Mask: 0x01)             */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4FRAGOIM_Pos                (19UL)         /*!< RXIPV4FRAGOIM (Bit 19)                                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4FRAGOIM_Msk                (0x80000UL)    /*!< RXIPV4FRAGOIM (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4UDSBLOIM_Pos               (20UL)         /*!< RXIPV4UDSBLOIM (Bit 20)                               */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV4UDSBLOIM_Msk               (0x100000UL)   /*!< RXIPV4UDSBLOIM (Bitfield-Mask: 0x01)            */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6GOIM_Pos                   (21UL)         /*!< RXIPV6GOIM (Bit 21)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6GOIM_Msk                   (0x200000UL)   /*!< RXIPV6GOIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6HEROIM_Pos                 (22UL)         /*!< RXIPV6HEROIM (Bit 22)                                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6HEROIM_Msk                 (0x400000UL)   /*!< RXIPV6HEROIM (Bitfield-Mask: 0x01)                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6NOPAYOIM_Pos               (23UL)         /*!< RXIPV6NOPAYOIM (Bit 23)                               */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXIPV6NOPAYOIM_Msk               (0x800000UL)   /*!< RXIPV6NOPAYOIM (Bitfield-Mask: 0x01)            */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXUDPGOIM_Pos                    (24UL)         /*!< RXUDPGOIM (Bit 24)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXUDPGOIM_Msk                    (0x1000000UL)  /*!< RXUDPGOIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXUDPEROIM_Pos                   (25UL)         /*!< RXUDPEROIM (Bit 25)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXUDPEROIM_Msk                   (0x2000000UL)  /*!< RXUDPEROIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXTCPGOIM_Pos                    (26UL)         /*!< RXTCPGOIM (Bit 26)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXTCPGOIM_Msk                    (0x4000000UL)  /*!< RXTCPGOIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXTCPEROIM_Pos                   (27UL)         /*!< RXTCPEROIM (Bit 27)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXTCPEROIM_Msk                   (0x8000000UL)  /*!< RXTCPEROIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXICMPGOIM_Pos                   (28UL)         /*!< RXICMPGOIM (Bit 28)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXICMPGOIM_Msk                   (0x10000000UL) /*!< RXICMPGOIM (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXICMPEROIM_Pos                  (29UL)         /*!< RXICMPEROIM (Bit 29)                                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_Mask_RXICMPEROIM_Msk                  (0x20000000UL) /*!< RXICMPEROIM (Bitfield-Mask: 0x01)                */
+/* =================================================  MMC_IPC_Rx_Interrupt  ================================================== */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4GPIS_Pos                        (0UL)          /*!< RXIPV4GPIS (Bit 0)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4GPIS_Msk                        (0x1UL)        /*!< RXIPV4GPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4HERPIS_Pos                      (1UL)          /*!< RXIPV4HERPIS (Bit 1)                                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4HERPIS_Msk                      (0x2UL)        /*!< RXIPV4HERPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4NOPAYPIS_Pos                    (2UL)          /*!< RXIPV4NOPAYPIS (Bit 2)                                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4NOPAYPIS_Msk                    (0x4UL)        /*!< RXIPV4NOPAYPIS (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4FRAGPIS_Pos                     (3UL)          /*!< RXIPV4FRAGPIS (Bit 3)                                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4FRAGPIS_Msk                     (0x8UL)        /*!< RXIPV4FRAGPIS (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4UDSBLPIS_Pos                    (4UL)          /*!< RXIPV4UDSBLPIS (Bit 4)                                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4UDSBLPIS_Msk                    (0x10UL)       /*!< RXIPV4UDSBLPIS (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6GPIS_Pos                        (5UL)          /*!< RXIPV6GPIS (Bit 5)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6GPIS_Msk                        (0x20UL)       /*!< RXIPV6GPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6HERPIS_Pos                      (6UL)          /*!< RXIPV6HERPIS (Bit 6)                                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6HERPIS_Msk                      (0x40UL)       /*!< RXIPV6HERPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6NOPAYPIS_Pos                    (7UL)          /*!< RXIPV6NOPAYPIS (Bit 7)                                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6NOPAYPIS_Msk                    (0x80UL)       /*!< RXIPV6NOPAYPIS (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXUDPGPIS_Pos                         (8UL)          /*!< RXUDPGPIS (Bit 8)                                     */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXUDPGPIS_Msk                         (0x100UL)      /*!< RXUDPGPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXUDPERPIS_Pos                        (9UL)          /*!< RXUDPERPIS (Bit 9)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXUDPERPIS_Msk                        (0x200UL)      /*!< RXUDPERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXTCPGPIS_Pos                         (10UL)         /*!< RXTCPGPIS (Bit 10)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXTCPGPIS_Msk                         (0x400UL)      /*!< RXTCPGPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXTCPERPIS_Pos                        (11UL)         /*!< RXTCPERPIS (Bit 11)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXTCPERPIS_Msk                        (0x800UL)      /*!< RXTCPERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXICMPGPIS_Pos                        (12UL)         /*!< RXICMPGPIS (Bit 12)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXICMPGPIS_Msk                        (0x1000UL)     /*!< RXICMPGPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXICMPERPIS_Pos                       (13UL)         /*!< RXICMPERPIS (Bit 13)                                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXICMPERPIS_Msk                       (0x2000UL)     /*!< RXICMPERPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4GOIS_Pos                        (16UL)         /*!< RXIPV4GOIS (Bit 16)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4GOIS_Msk                        (0x10000UL)    /*!< RXIPV4GOIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4HEROIS_Pos                      (17UL)         /*!< RXIPV4HEROIS (Bit 17)                                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4HEROIS_Msk                      (0x20000UL)    /*!< RXIPV4HEROIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4NOPAYOIS_Pos                    (18UL)         /*!< RXIPV4NOPAYOIS (Bit 18)                               */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4NOPAYOIS_Msk                    (0x40000UL)    /*!< RXIPV4NOPAYOIS (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4FRAGOIS_Pos                     (19UL)         /*!< RXIPV4FRAGOIS (Bit 19)                                */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4FRAGOIS_Msk                     (0x80000UL)    /*!< RXIPV4FRAGOIS (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4UDSBLOIS_Pos                    (20UL)         /*!< RXIPV4UDSBLOIS (Bit 20)                               */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV4UDSBLOIS_Msk                    (0x100000UL)   /*!< RXIPV4UDSBLOIS (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6GOIS_Pos                        (21UL)         /*!< RXIPV6GOIS (Bit 21)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6GOIS_Msk                        (0x200000UL)   /*!< RXIPV6GOIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6HEROIS_Pos                      (22UL)         /*!< RXIPV6HEROIS (Bit 22)                                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6HEROIS_Msk                      (0x400000UL)   /*!< RXIPV6HEROIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6NOPAYOIS_Pos                    (23UL)         /*!< RXIPV6NOPAYOIS (Bit 23)                               */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXIPV6NOPAYOIS_Msk                    (0x800000UL)   /*!< RXIPV6NOPAYOIS (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXUDPGOIS_Pos                         (24UL)         /*!< RXUDPGOIS (Bit 24)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXUDPGOIS_Msk                         (0x1000000UL)  /*!< RXUDPGOIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXUDPEROIS_Pos                        (25UL)         /*!< RXUDPEROIS (Bit 25)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXUDPEROIS_Msk                        (0x2000000UL)  /*!< RXUDPEROIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXTCPGOIS_Pos                         (26UL)         /*!< RXTCPGOIS (Bit 26)                                    */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXTCPGOIS_Msk                         (0x4000000UL)  /*!< RXTCPGOIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXTCPEROIS_Pos                        (27UL)         /*!< RXTCPEROIS (Bit 27)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXTCPEROIS_Msk                        (0x8000000UL)  /*!< RXTCPEROIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXICMPGOIS_Pos                        (28UL)         /*!< RXICMPGOIS (Bit 28)                                   */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXICMPGOIS_Msk                        (0x10000000UL) /*!< RXICMPGOIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXICMPEROIS_Pos                       (29UL)         /*!< RXICMPEROIS (Bit 29)                                  */
+ #define R_GMAC0_MMC_IPC_Rx_Interrupt_RXICMPEROIS_Msk                       (0x20000000UL) /*!< RXICMPEROIS (Bitfield-Mask: 0x01)                     */
+/* ==================================================  RxIPv4_Good_Packets  ================================================== */
+ #define R_GMAC0_RxIPv4_Good_Packets_RXIPV4GDPKT_Pos                        (0UL)          /*!< RXIPV4GDPKT (Bit 0)                                   */
+ #define R_GMAC0_RxIPv4_Good_Packets_RXIPV4GDPKT_Msk                        (0xffffffffUL) /*!< RXIPV4GDPKT (Bitfield-Mask: 0xffffffff)               */
+/* ==============================================  RxIPv4_Header_Error_Packets  ============================================== */
+ #define R_GMAC0_RxIPv4_Header_Error_Packets_RXIPV4HDRERRPKT_Pos            (0UL)          /*!< RXIPV4HDRERRPKT (Bit 0)                             */
+ #define R_GMAC0_RxIPv4_Header_Error_Packets_RXIPV4HDRERRPKT_Msk            (0xffffffffUL) /*!< RXIPV4HDRERRPKT (Bitfield-Mask: 0xffffffff) */
+/* ===============================================  RxIPv4_No_Payload_Packets  =============================================== */
+ #define R_GMAC0_RxIPv4_No_Payload_Packets_RXIPV4NOPAYPKT_Pos               (0UL)          /*!< RXIPV4NOPAYPKT (Bit 0)                                */
+ #define R_GMAC0_RxIPv4_No_Payload_Packets_RXIPV4NOPAYPKT_Msk               (0xffffffffUL) /*!< RXIPV4NOPAYPKT (Bitfield-Mask: 0xffffffff)    */
+/* ===============================================  RxIPv4_Fragmented_Packets  =============================================== */
+ #define R_GMAC0_RxIPv4_Fragmented_Packets_RXIPV4FRAGPKT_Pos                (0UL)          /*!< RXIPV4FRAGPKT (Bit 0)                                 */
+ #define R_GMAC0_RxIPv4_Fragmented_Packets_RXIPV4FRAGPKT_Msk                (0xffffffffUL) /*!< RXIPV4FRAGPKT (Bitfield-Mask: 0xffffffff)      */
+/* =========================================  RxIPv4_UDP_Checksum_Disabled_Packets  ========================================== */
+ #define R_GMAC0_RxIPv4_UDP_Checksum_Disabled_Packets_RXIPV4UDSBLPKT_Pos    (0UL)          /*!< RXIPV4UDSBLPKT (Bit 0)                      */
+ #define R_GMAC0_RxIPv4_UDP_Checksum_Disabled_Packets_RXIPV4UDSBLPKT_Msk    (0xffffffffUL) /*!< RXIPV4UDSBLPKT (Bitfield-Mask: 0xffffffff) */
+/* ==================================================  RxIPv6_Good_Packets  ================================================== */
+ #define R_GMAC0_RxIPv6_Good_Packets_RXIPV6GDPKT_Pos                        (0UL)          /*!< RXIPV6GDPKT (Bit 0)                                   */
+ #define R_GMAC0_RxIPv6_Good_Packets_RXIPV6GDPKT_Msk                        (0xffffffffUL) /*!< RXIPV6GDPKT (Bitfield-Mask: 0xffffffff)               */
+/* ==============================================  RxIPv6_Header_Error_Packets  ============================================== */
+ #define R_GMAC0_RxIPv6_Header_Error_Packets_RXIPV6HDRERRPKT_Pos            (0UL)          /*!< RXIPV6HDRERRPKT (Bit 0)                             */
+ #define R_GMAC0_RxIPv6_Header_Error_Packets_RXIPV6HDRERRPKT_Msk            (0xffffffffUL) /*!< RXIPV6HDRERRPKT (Bitfield-Mask: 0xffffffff) */
+/* ===============================================  RxIPv6_No_Payload_Packets  =============================================== */
+ #define R_GMAC0_RxIPv6_No_Payload_Packets_RXIPV6NOPAYPKT_Pos               (0UL)          /*!< RXIPV6NOPAYPKT (Bit 0)                                */
+ #define R_GMAC0_RxIPv6_No_Payload_Packets_RXIPV6NOPAYPKT_Msk               (0xffffffffUL) /*!< RXIPV6NOPAYPKT (Bitfield-Mask: 0xffffffff)    */
+/* ==================================================  RxUDP_Good_Packets  =================================================== */
+ #define R_GMAC0_RxUDP_Good_Packets_RXUDPGDPKT_Pos                          (0UL)          /*!< RXUDPGDPKT (Bit 0)                                    */
+ #define R_GMAC0_RxUDP_Good_Packets_RXUDPGDPKT_Msk                          (0xffffffffUL) /*!< RXUDPGDPKT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  RxUDP_Error_Packets  ================================================== */
+ #define R_GMAC0_RxUDP_Error_Packets_RXUDPERRPKT_Pos                        (0UL)          /*!< RXUDPERRPKT (Bit 0)                                   */
+ #define R_GMAC0_RxUDP_Error_Packets_RXUDPERRPKT_Msk                        (0xffffffffUL) /*!< RXUDPERRPKT (Bitfield-Mask: 0xffffffff)               */
+/* ==================================================  RxTCP_Good_Packets  =================================================== */
+ #define R_GMAC0_RxTCP_Good_Packets_RXTCPGDPKT_Pos                          (0UL)          /*!< RXTCPGDPKT (Bit 0)                                    */
+ #define R_GMAC0_RxTCP_Good_Packets_RXTCPGDPKT_Msk                          (0xffffffffUL) /*!< RXTCPGDPKT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  RxTCP_Error_Packets  ================================================== */
+ #define R_GMAC0_RxTCP_Error_Packets_RXTCPERRPKT_Pos                        (0UL)          /*!< RXTCPERRPKT (Bit 0)                                   */
+ #define R_GMAC0_RxTCP_Error_Packets_RXTCPERRPKT_Msk                        (0xffffffffUL) /*!< RXTCPERRPKT (Bitfield-Mask: 0xffffffff)               */
+/* ==================================================  RxICMP_Good_Packets  ================================================== */
+ #define R_GMAC0_RxICMP_Good_Packets_RXICMPGDPKT_Pos                        (0UL)          /*!< RXICMPGDPKT (Bit 0)                                   */
+ #define R_GMAC0_RxICMP_Good_Packets_RXICMPGDPKT_Msk                        (0xffffffffUL) /*!< RXICMPGDPKT (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  RxICMP_Error_Packets  ================================================== */
+ #define R_GMAC0_RxICMP_Error_Packets_RXICMPERRPKT_Pos                      (0UL)          /*!< RXICMPERRPKT (Bit 0)                                  */
+ #define R_GMAC0_RxICMP_Error_Packets_RXICMPERRPKT_Msk                      (0xffffffffUL) /*!< RXICMPERRPKT (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  RxIPv4_Good_Octets  =================================================== */
+ #define R_GMAC0_RxIPv4_Good_Octets_RXIPV4GDOCT_Pos                         (0UL)          /*!< RXIPV4GDOCT (Bit 0)                                   */
+ #define R_GMAC0_RxIPv4_Good_Octets_RXIPV4GDOCT_Msk                         (0xffffffffUL) /*!< RXIPV4GDOCT (Bitfield-Mask: 0xffffffff)               */
+/* ==============================================  RxIPv4_Header_Error_Octets  =============================================== */
+ #define R_GMAC0_RxIPv4_Header_Error_Octets_RXIPV4HDRERROCT_Pos             (0UL)          /*!< RXIPV4HDRERROCT (Bit 0)                              */
+ #define R_GMAC0_RxIPv4_Header_Error_Octets_RXIPV4HDRERROCT_Msk             (0xffffffffUL) /*!< RXIPV4HDRERROCT (Bitfield-Mask: 0xffffffff) */
+/* ===============================================  RxIPv4_No_Payload_Octets  ================================================ */
+ #define R_GMAC0_RxIPv4_No_Payload_Octets_RXIPV4NOPAYOCT_Pos                (0UL)          /*!< RXIPV4NOPAYOCT (Bit 0)                                */
+ #define R_GMAC0_RxIPv4_No_Payload_Octets_RXIPV4NOPAYOCT_Msk                (0xffffffffUL) /*!< RXIPV4NOPAYOCT (Bitfield-Mask: 0xffffffff)     */
+/* ===============================================  RxIPv4_Fragmented_Octets  ================================================ */
+ #define R_GMAC0_RxIPv4_Fragmented_Octets_RXIPV4FRAGOCT_Pos                 (0UL)          /*!< RXIPV4FRAGOCT (Bit 0)                                 */
+ #define R_GMAC0_RxIPv4_Fragmented_Octets_RXIPV4FRAGOCT_Msk                 (0xffffffffUL) /*!< RXIPV4FRAGOCT (Bitfield-Mask: 0xffffffff)       */
+/* ==========================================  RxIPv4_UDP_Checksum_Disable_Octets  =========================================== */
+ #define R_GMAC0_RxIPv4_UDP_Checksum_Disable_Octets_RXIPV4UDSBLOCT_Pos      (0UL)          /*!< RXIPV4UDSBLOCT (Bit 0)                        */
+ #define R_GMAC0_RxIPv4_UDP_Checksum_Disable_Octets_RXIPV4UDSBLOCT_Msk      (0xffffffffUL) /*!< RXIPV4UDSBLOCT (Bitfield-Mask: 0xffffffff) */
+/* ==================================================  RxIPv6_Good_Octets  =================================================== */
+ #define R_GMAC0_RxIPv6_Good_Octets_RXIPV6GDOCT_Pos                         (0UL)          /*!< RXIPV6GDOCT (Bit 0)                                   */
+ #define R_GMAC0_RxIPv6_Good_Octets_RXIPV6GDOCT_Msk                         (0xffffffffUL) /*!< RXIPV6GDOCT (Bitfield-Mask: 0xffffffff)               */
+/* ==============================================  RxIPv6_Header_Error_Octets  =============================================== */
+ #define R_GMAC0_RxIPv6_Header_Error_Octets_RXIPV6HDRERROCT_Pos             (0UL)          /*!< RXIPV6HDRERROCT (Bit 0)                              */
+ #define R_GMAC0_RxIPv6_Header_Error_Octets_RXIPV6HDRERROCT_Msk             (0xffffffffUL) /*!< RXIPV6HDRERROCT (Bitfield-Mask: 0xffffffff) */
+/* ===============================================  RxIPv6_No_Payload_Octets  ================================================ */
+ #define R_GMAC0_RxIPv6_No_Payload_Octets_RXIPV6NOPAYOCT_Pos                (0UL)          /*!< RXIPV6NOPAYOCT (Bit 0)                                */
+ #define R_GMAC0_RxIPv6_No_Payload_Octets_RXIPV6NOPAYOCT_Msk                (0xffffffffUL) /*!< RXIPV6NOPAYOCT (Bitfield-Mask: 0xffffffff)     */
+/* ===================================================  RxUDP_Good_Octets  =================================================== */
+ #define R_GMAC0_RxUDP_Good_Octets_RXUDPGDOCT_Pos                           (0UL)          /*!< RXUDPGDOCT (Bit 0)                                    */
+ #define R_GMAC0_RxUDP_Good_Octets_RXUDPGDOCT_Msk                           (0xffffffffUL) /*!< RXUDPGDOCT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  RxUDP_Error_Octets  =================================================== */
+ #define R_GMAC0_RxUDP_Error_Octets_RXUDPERROCT_Pos                         (0UL)          /*!< RXUDPERROCT (Bit 0)                                   */
+ #define R_GMAC0_RxUDP_Error_Octets_RXUDPERROCT_Msk                         (0xffffffffUL) /*!< RXUDPERROCT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  RxTCP_Good_Octets  =================================================== */
+ #define R_GMAC0_RxTCP_Good_Octets_RXTCPGDOCT_Pos                           (0UL)          /*!< RXTCPGDOCT (Bit 0)                                    */
+ #define R_GMAC0_RxTCP_Good_Octets_RXTCPGDOCT_Msk                           (0xffffffffUL) /*!< RXTCPGDOCT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  RxTCP_Error_Octets  =================================================== */
+ #define R_GMAC0_RxTCP_Error_Octets_RXTCPERROCT_Pos                         (0UL)          /*!< RXTCPERROCT (Bit 0)                                   */
+ #define R_GMAC0_RxTCP_Error_Octets_RXTCPERROCT_Msk                         (0xffffffffUL) /*!< RXTCPERROCT (Bitfield-Mask: 0xffffffff)               */
+/* ==================================================  RxICMP_Good_Octets  =================================================== */
+ #define R_GMAC0_RxICMP_Good_Octets_RXICMPGDOCT_Pos                         (0UL)          /*!< RXICMPGDOCT (Bit 0)                                   */
+ #define R_GMAC0_RxICMP_Good_Octets_RXICMPGDOCT_Msk                         (0xffffffffUL) /*!< RXICMPGDOCT (Bitfield-Mask: 0xffffffff)               */
+/* ==================================================  RxICMP_Error_Octets  ================================================== */
+ #define R_GMAC0_RxICMP_Error_Octets_RXICMPERROCT_Pos                       (0UL)          /*!< RXICMPERROCT (Bit 0)                                  */
+ #define R_GMAC0_RxICMP_Error_Octets_RXICMPERROCT_Msk                       (0xffffffffUL) /*!< RXICMPERROCT (Bitfield-Mask: 0xffffffff)              */
+/* =================================================  MMC_FPE_Tx_Interrupt  ================================================== */
+ #define R_GMAC0_MMC_FPE_Tx_Interrupt_FCIS_Pos                              (0UL)          /*!< FCIS (Bit 0)                                          */
+ #define R_GMAC0_MMC_FPE_Tx_Interrupt_FCIS_Msk                              (0x1UL)        /*!< FCIS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MMC_FPE_Tx_Interrupt_HRCIS_Pos                             (1UL)          /*!< HRCIS (Bit 1)                                         */
+ #define R_GMAC0_MMC_FPE_Tx_Interrupt_HRCIS_Msk                             (0x2UL)        /*!< HRCIS (Bitfield-Mask: 0x01)                           */
+/* ===============================================  MMC_FPE_Tx_Interrupt_Mask  =============================================== */
+ #define R_GMAC0_MMC_FPE_Tx_Interrupt_Mask_FCIM_Pos                         (0UL)          /*!< FCIM (Bit 0)                                          */
+ #define R_GMAC0_MMC_FPE_Tx_Interrupt_Mask_FCIM_Msk                         (0x1UL)        /*!< FCIM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MMC_FPE_Tx_Interrupt_Mask_HRCIM_Pos                        (1UL)          /*!< HRCIM (Bit 1)                                         */
+ #define R_GMAC0_MMC_FPE_Tx_Interrupt_Mask_HRCIM_Msk                        (0x2UL)        /*!< HRCIM (Bitfield-Mask: 0x01)                           */
+/* ===============================================  MMC_Tx_FPE_Fragment_Cntr  ================================================ */
+ #define R_GMAC0_MMC_Tx_FPE_Fragment_Cntr_TXFFC_Pos                         (0UL)          /*!< TXFFC (Bit 0)                                         */
+ #define R_GMAC0_MMC_Tx_FPE_Fragment_Cntr_TXFFC_Msk                         (0xffffffffUL) /*!< TXFFC (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MMC_Tx_Hold_Req_Cntr  ================================================== */
+ #define R_GMAC0_MMC_Tx_Hold_Req_Cntr_TXHRC_Pos                             (0UL)          /*!< TXHRC (Bit 0)                                         */
+ #define R_GMAC0_MMC_Tx_Hold_Req_Cntr_TXHRC_Msk                             (0xffffffffUL) /*!< TXHRC (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MMC_FPE_Rx_Interrupt  ================================================== */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_PAECIS_Pos                            (0UL)          /*!< PAECIS (Bit 0)                                        */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_PAECIS_Msk                            (0x1UL)        /*!< PAECIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_PSECIS_Pos                            (1UL)          /*!< PSECIS (Bit 1)                                        */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_PSECIS_Msk                            (0x2UL)        /*!< PSECIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_PAOCIS_Pos                            (2UL)          /*!< PAOCIS (Bit 2)                                        */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_PAOCIS_Msk                            (0x4UL)        /*!< PAOCIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_FCIS_Pos                              (3UL)          /*!< FCIS (Bit 3)                                          */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_FCIS_Msk                              (0x8UL)        /*!< FCIS (Bitfield-Mask: 0x01)                            */
+/* ===============================================  MMC_FPE_Rx_Interrupt_Mask  =============================================== */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_Mask_PAECIM_Pos                       (0UL)          /*!< PAECIM (Bit 0)                                        */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_Mask_PAECIM_Msk                       (0x1UL)        /*!< PAECIM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_Mask_PSECIM_Pos                       (1UL)          /*!< PSECIM (Bit 1)                                        */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_Mask_PSECIM_Msk                       (0x2UL)        /*!< PSECIM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_Mask_PAOCIM_Pos                       (2UL)          /*!< PAOCIM (Bit 2)                                        */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_Mask_PAOCIM_Msk                       (0x4UL)        /*!< PAOCIM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_Mask_FCIM_Pos                         (3UL)          /*!< FCIM (Bit 3)                                          */
+ #define R_GMAC0_MMC_FPE_Rx_Interrupt_Mask_FCIM_Msk                         (0x8UL)        /*!< FCIM (Bitfield-Mask: 0x01)                            */
+/* ============================================  MMC_Rx_Packet_Assembly_Err_Cntr  ============================================ */
+ #define R_GMAC0_MMC_Rx_Packet_Assembly_Err_Cntr_PAEC_Pos                   (0UL)          /*!< PAEC (Bit 0)                                          */
+ #define R_GMAC0_MMC_Rx_Packet_Assembly_Err_Cntr_PAEC_Msk                   (0xffffffffUL) /*!< PAEC (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  MMC_Rx_Packet_SMD_Err_Cntr  =============================================== */
+ #define R_GMAC0_MMC_Rx_Packet_SMD_Err_Cntr_PSEC_Pos                        (0UL)          /*!< PSEC (Bit 0)                                          */
+ #define R_GMAC0_MMC_Rx_Packet_SMD_Err_Cntr_PSEC_Msk                        (0xffffffffUL) /*!< PSEC (Bitfield-Mask: 0xffffffff)                      */
+/* ============================================  MMC_Rx_Packet_Assembly_OK_Cntr  ============================================= */
+ #define R_GMAC0_MMC_Rx_Packet_Assembly_OK_Cntr_PAOC_Pos                    (0UL)          /*!< PAOC (Bit 0)                                          */
+ #define R_GMAC0_MMC_Rx_Packet_Assembly_OK_Cntr_PAOC_Msk                    (0xffffffffUL) /*!< PAOC (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  MMC_Rx_FPE_Fragment_Cntr  ================================================ */
+ #define R_GMAC0_MMC_Rx_FPE_Fragment_Cntr_FFC_Pos                           (0UL)          /*!< FFC (Bit 0)                                           */
+ #define R_GMAC0_MMC_Rx_FPE_Fragment_Cntr_FFC_Msk                           (0xffffffffUL) /*!< FFC (Bitfield-Mask: 0xffffffff)                       */
+/* ==================================================  MAC_L3_L4_CONTROL0  =================================================== */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL0_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL1  =================================================== */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL1_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL2  =================================================== */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL2_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL3  =================================================== */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL3_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL4  =================================================== */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL4_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL5  =================================================== */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL5_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL6  =================================================== */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL6_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL7  =================================================== */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC0_MAC_L3_L4_CONTROL7_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS0  ================================================== */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS0_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS0_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS0_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS0_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS1  ================================================== */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS1_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS1_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS1_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS1_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS2  ================================================== */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS2_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS2_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS2_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS2_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS3  ================================================== */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS3_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS3_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS3_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS3_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS4  ================================================== */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS4_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS4_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS4_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS4_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS5  ================================================== */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS5_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS5_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS5_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS5_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS6  ================================================== */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS6_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS6_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS6_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS6_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS7  ================================================== */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS7_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS7_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS7_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC0_MAC_LAYER4_ADDRESS7_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* =================================================  MAC_LAYER3_ADDR0_REG0  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG0_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG0_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG1  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG1_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG1_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG2  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG2_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG2_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG3  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG3_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG3_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG4  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG4_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG4_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG5  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG5_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG5_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG6  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG6_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG6_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG7  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG7_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR0_REG7_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG0  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG0_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG0_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG1  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG1_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG1_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG2  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG2_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG2_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG3  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG3_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG3_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG4  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG4_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG4_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG5  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG5_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG5_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG6  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG6_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG6_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG7  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG7_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR1_REG7_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG0  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG0_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG0_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG1  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG1_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG1_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG2  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG2_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG2_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG3  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG3_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG3_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG4  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG4_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG4_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG5  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG5_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG5_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG6  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG6_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG6_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG7  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG7_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR2_REG7_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG0  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG0_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG0_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG1  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG1_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG1_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG2  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG2_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG2_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG3  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG3_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG3_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG4  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG4_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG4_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG5  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG5_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG5_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG6  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG6_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG6_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG7  ================================================= */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG7_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC0_MAC_LAYER3_ADDR3_REG7_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_Indir_Access_Ctrl  ================================================= */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_OB_Pos                               (0UL)          /*!< OB (Bit 0)                                            */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_OB_Msk                               (0x1UL)        /*!< OB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_COM_Pos                              (1UL)          /*!< COM (Bit 1)                                           */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_COM_Msk                              (0x2UL)        /*!< COM (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_AUTO_Pos                             (5UL)          /*!< AUTO (Bit 5)                                          */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_AUTO_Msk                             (0x20UL)       /*!< AUTO (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_AOFF_Pos                             (8UL)          /*!< AOFF (Bit 8)                                          */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_AOFF_Msk                             (0xff00UL)     /*!< AOFF (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_MSEL_Pos                             (16UL)         /*!< MSEL (Bit 16)                                         */
+ #define R_GMAC0_MAC_Indir_Access_Ctrl_MSEL_Msk                             (0xf0000UL)    /*!< MSEL (Bitfield-Mask: 0x0f)                            */
+/* =================================================  MAC_Indir_Access_Data  ================================================= */
+ #define R_GMAC0_MAC_Indir_Access_Data_DATA_Pos                             (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_GMAC0_MAC_Indir_Access_Data_DATA_Msk                             (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* =================================================  MAC_Timestamp_Control  ================================================= */
+ #define R_GMAC0_MAC_Timestamp_Control_TSENA_Pos                            (0UL)          /*!< TSENA (Bit 0)                                         */
+ #define R_GMAC0_MAC_Timestamp_Control_TSENA_Msk                            (0x1UL)        /*!< TSENA (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Timestamp_Control_TSTRIG_Pos                           (4UL)          /*!< TSTRIG (Bit 4)                                        */
+ #define R_GMAC0_MAC_Timestamp_Control_TSTRIG_Msk                           (0x10UL)       /*!< TSTRIG (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Timestamp_Control_TSENALL_Pos                          (8UL)          /*!< TSENALL (Bit 8)                                       */
+ #define R_GMAC0_MAC_Timestamp_Control_TSENALL_Msk                          (0x100UL)      /*!< TSENALL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Timestamp_Control_TSCTRLSSR_Pos                        (9UL)          /*!< TSCTRLSSR (Bit 9)                                     */
+ #define R_GMAC0_MAC_Timestamp_Control_TSCTRLSSR_Msk                        (0x200UL)      /*!< TSCTRLSSR (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_Timestamp_Control_TSVER2ENA_Pos                        (10UL)         /*!< TSVER2ENA (Bit 10)                                    */
+ #define R_GMAC0_MAC_Timestamp_Control_TSVER2ENA_Msk                        (0x400UL)      /*!< TSVER2ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_Timestamp_Control_TSIPENA_Pos                          (11UL)         /*!< TSIPENA (Bit 11)                                      */
+ #define R_GMAC0_MAC_Timestamp_Control_TSIPENA_Msk                          (0x800UL)      /*!< TSIPENA (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Timestamp_Control_TSIPV6ENA_Pos                        (12UL)         /*!< TSIPV6ENA (Bit 12)                                    */
+ #define R_GMAC0_MAC_Timestamp_Control_TSIPV6ENA_Msk                        (0x1000UL)     /*!< TSIPV6ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_Timestamp_Control_TSIPV4ENA_Pos                        (13UL)         /*!< TSIPV4ENA (Bit 13)                                    */
+ #define R_GMAC0_MAC_Timestamp_Control_TSIPV4ENA_Msk                        (0x2000UL)     /*!< TSIPV4ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_Timestamp_Control_TSEVNTENA_Pos                        (14UL)         /*!< TSEVNTENA (Bit 14)                                    */
+ #define R_GMAC0_MAC_Timestamp_Control_TSEVNTENA_Msk                        (0x4000UL)     /*!< TSEVNTENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_Timestamp_Control_TSMSTRENA_Pos                        (15UL)         /*!< TSMSTRENA (Bit 15)                                    */
+ #define R_GMAC0_MAC_Timestamp_Control_TSMSTRENA_Msk                        (0x8000UL)     /*!< TSMSTRENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_Timestamp_Control_SNAPTYPSEL_Pos                       (16UL)         /*!< SNAPTYPSEL (Bit 16)                                   */
+ #define R_GMAC0_MAC_Timestamp_Control_SNAPTYPSEL_Msk                       (0x30000UL)    /*!< SNAPTYPSEL (Bitfield-Mask: 0x03)                      */
+ #define R_GMAC0_MAC_Timestamp_Control_TSENMACADDR_Pos                      (18UL)         /*!< TSENMACADDR (Bit 18)                                  */
+ #define R_GMAC0_MAC_Timestamp_Control_TSENMACADDR_Msk                      (0x40000UL)    /*!< TSENMACADDR (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MAC_Timestamp_Control_CSC_Pos                              (19UL)         /*!< CSC (Bit 19)                                          */
+ #define R_GMAC0_MAC_Timestamp_Control_CSC_Msk                              (0x80000UL)    /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MAC_Timestamp_Control_TXTSSTSM_Pos                         (24UL)         /*!< TXTSSTSM (Bit 24)                                     */
+ #define R_GMAC0_MAC_Timestamp_Control_TXTSSTSM_Msk                         (0x1000000UL)  /*!< TXTSSTSM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_Timestamp_Control_AV8021ASMEN_Pos                      (28UL)         /*!< AV8021ASMEN (Bit 28)                                  */
+ #define R_GMAC0_MAC_Timestamp_Control_AV8021ASMEN_Msk                      (0x10000000UL) /*!< AV8021ASMEN (Bitfield-Mask: 0x01)                    */
+/* ================================================  MAC_System_Time_Seconds  ================================================ */
+ #define R_GMAC0_MAC_System_Time_Seconds_TSS_Pos                            (0UL)          /*!< TSS (Bit 0)                                           */
+ #define R_GMAC0_MAC_System_Time_Seconds_TSS_Msk                            (0xffffffffUL) /*!< TSS (Bitfield-Mask: 0xffffffff)                       */
+/* ==============================================  MAC_System_Time_Nanoseconds  ============================================== */
+ #define R_GMAC0_MAC_System_Time_Nanoseconds_TSSS_Pos                       (0UL)          /*!< TSSS (Bit 0)                                          */
+ #define R_GMAC0_MAC_System_Time_Nanoseconds_TSSS_Msk                       (0x7fffffffUL) /*!< TSSS (Bitfield-Mask: 0x7fffffff)                      */
+/* =================================================  MAC_Timestamp_Status  ================================================== */
+ #define R_GMAC0_MAC_Timestamp_Status_AUXTSTRIG_Pos                         (2UL)          /*!< AUXTSTRIG (Bit 2)                                     */
+ #define R_GMAC0_MAC_Timestamp_Status_AUXTSTRIG_Msk                         (0x4UL)        /*!< AUXTSTRIG (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_Timestamp_Status_TXTSSIS_Pos                           (15UL)         /*!< TXTSSIS (Bit 15)                                      */
+ #define R_GMAC0_MAC_Timestamp_Status_TXTSSIS_Msk                           (0x8000UL)     /*!< TXTSSIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_Timestamp_Status_ATSSTN_Pos                            (16UL)         /*!< ATSSTN (Bit 16)                                       */
+ #define R_GMAC0_MAC_Timestamp_Status_ATSSTN_Msk                            (0x30000UL)    /*!< ATSSTN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MAC_Timestamp_Status_ATSSTM_Pos                            (24UL)         /*!< ATSSTM (Bit 24)                                       */
+ #define R_GMAC0_MAC_Timestamp_Status_ATSSTM_Msk                            (0x1000000UL)  /*!< ATSSTM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Timestamp_Status_ATSNS_Pos                             (25UL)         /*!< ATSNS (Bit 25)                                        */
+ #define R_GMAC0_MAC_Timestamp_Status_ATSNS_Msk                             (0x3e000000UL) /*!< ATSNS (Bitfield-Mask: 0x1f)                           */
+/* ==========================================  MAC_Tx_Timestamp_Status_Nanoseconds  ========================================== */
+ #define R_GMAC0_MAC_Tx_Timestamp_Status_Nanoseconds_TXTSSLO_Pos            (0UL)          /*!< TXTSSLO (Bit 0)                                     */
+ #define R_GMAC0_MAC_Tx_Timestamp_Status_Nanoseconds_TXTSSLO_Msk            (0x7fffffffUL) /*!< TXTSSLO (Bitfield-Mask: 0x7fffffff)        */
+ #define R_GMAC0_MAC_Tx_Timestamp_Status_Nanoseconds_TXTSSMIS_Pos           (31UL)         /*!< TXTSSMIS (Bit 31)                                 */
+ #define R_GMAC0_MAC_Tx_Timestamp_Status_Nanoseconds_TXTSSMIS_Msk           (0x80000000UL) /*!< TXTSSMIS (Bitfield-Mask: 0x01)            */
+/* ============================================  MAC_Tx_Timestamp_Status_Seconds  ============================================ */
+ #define R_GMAC0_MAC_Tx_Timestamp_Status_Seconds_TXTSSHI_Pos                (0UL)          /*!< TXTSSHI (Bit 0)                                       */
+ #define R_GMAC0_MAC_Tx_Timestamp_Status_Seconds_TXTSSHI_Msk                (0xffffffffUL) /*!< TXTSSHI (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  MAC_Auxiliary_Control  ================================================= */
+ #define R_GMAC0_MAC_Auxiliary_Control_ATSFC_Pos                            (0UL)          /*!< ATSFC (Bit 0)                                         */
+ #define R_GMAC0_MAC_Auxiliary_Control_ATSFC_Msk                            (0x1UL)        /*!< ATSFC (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_Auxiliary_Control_ATSEN0_Pos                           (4UL)          /*!< ATSEN0 (Bit 4)                                        */
+ #define R_GMAC0_MAC_Auxiliary_Control_ATSEN0_Msk                           (0x10UL)       /*!< ATSEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_Auxiliary_Control_ATSEN1_Pos                           (5UL)          /*!< ATSEN1 (Bit 5)                                        */
+ #define R_GMAC0_MAC_Auxiliary_Control_ATSEN1_Msk                           (0x20UL)       /*!< ATSEN1 (Bitfield-Mask: 0x01)                          */
+/* ==========================================  MAC_Auxiliary_Timestamp_Nanoseconds  ========================================== */
+ #define R_GMAC0_MAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Pos            (0UL)          /*!< AUXTSLO (Bit 0)                                     */
+ #define R_GMAC0_MAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Msk            (0x7fffffffUL) /*!< AUXTSLO (Bitfield-Mask: 0x7fffffff)        */
+/* ============================================  MAC_Auxiliary_Timestamp_Seconds  ============================================ */
+ #define R_GMAC0_MAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Pos                (0UL)          /*!< AUXTSHI (Bit 0)                                       */
+ #define R_GMAC0_MAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Msk                (0xffffffffUL) /*!< AUXTSHI (Bitfield-Mask: 0xffffffff)            */
+/* ============================================  MAC_Timestamp_Ingress_Asym_Corr  ============================================ */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Asym_Corr_OSTIAC_Pos                 (0UL)          /*!< OSTIAC (Bit 0)                                        */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Asym_Corr_OSTIAC_Msk                 (0xffffffffUL) /*!< OSTIAC (Bitfield-Mask: 0xffffffff)              */
+/* ============================================  MAC_Timestamp_Egress_Asym_Corr  ============================================= */
+ #define R_GMAC0_MAC_Timestamp_Egress_Asym_Corr_OSTEAC_Pos                  (0UL)          /*!< OSTEAC (Bit 0)                                        */
+ #define R_GMAC0_MAC_Timestamp_Egress_Asym_Corr_OSTEAC_Msk                  (0xffffffffUL) /*!< OSTEAC (Bitfield-Mask: 0xffffffff)               */
+/* =========================================  MAC_Timestamp_Ingress_Corr_Nanosecond  ========================================= */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Corr_Nanosecond_TSIC_Pos             (0UL)          /*!< TSIC (Bit 0)                                         */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Corr_Nanosecond_TSIC_Msk             (0xffffffffUL) /*!< TSIC (Bitfield-Mask: 0xffffffff)            */
+/* =========================================  MAC_Timestamp_Egress_Corr_Nanosecond  ========================================== */
+ #define R_GMAC0_MAC_Timestamp_Egress_Corr_Nanosecond_TSEC_Pos              (0UL)          /*!< TSEC (Bit 0)                                          */
+ #define R_GMAC0_MAC_Timestamp_Egress_Corr_Nanosecond_TSEC_Msk              (0xffffffffUL) /*!< TSEC (Bitfield-Mask: 0xffffffff)             */
+/* =========================================  MAC_Timestamp_Ingress_Corr_Subnanosec  ========================================= */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Corr_Subnanosec_TSICSNS_Pos          (8UL)          /*!< TSICSNS (Bit 8)                                   */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Corr_Subnanosec_TSICSNS_Msk          (0xff00UL)     /*!< TSICSNS (Bitfield-Mask: 0xff)                */
+/* =========================================  MAC_Timestamp_Egress_Corr_Subnanosec  ========================================== */
+ #define R_GMAC0_MAC_Timestamp_Egress_Corr_Subnanosec_TSECSNS_Pos           (8UL)          /*!< TSECSNS (Bit 8)                                    */
+ #define R_GMAC0_MAC_Timestamp_Egress_Corr_Subnanosec_TSECSNS_Msk           (0xff00UL)     /*!< TSECSNS (Bitfield-Mask: 0xff)                 */
+/* =============================================  MAC_Timestamp_Ingress_Latency  ============================================= */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Latency_ITLSNS_Pos                   (8UL)          /*!< ITLSNS (Bit 8)                                        */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Latency_ITLSNS_Msk                   (0xff00UL)     /*!< ITLSNS (Bitfield-Mask: 0xff)                          */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Latency_ITLNS_Pos                    (16UL)         /*!< ITLNS (Bit 16)                                        */
+ #define R_GMAC0_MAC_Timestamp_Ingress_Latency_ITLNS_Msk                    (0xfff0000UL)  /*!< ITLNS (Bitfield-Mask: 0xfff)                        */
+/* =============================================  MAC_Timestamp_Egress_Latency  ============================================== */
+ #define R_GMAC0_MAC_Timestamp_Egress_Latency_ETLSNS_Pos                    (8UL)          /*!< ETLSNS (Bit 8)                                        */
+ #define R_GMAC0_MAC_Timestamp_Egress_Latency_ETLSNS_Msk                    (0xff00UL)     /*!< ETLSNS (Bitfield-Mask: 0xff)                          */
+ #define R_GMAC0_MAC_Timestamp_Egress_Latency_ETLNS_Pos                     (16UL)         /*!< ETLNS (Bit 16)                                        */
+ #define R_GMAC0_MAC_Timestamp_Egress_Latency_ETLNS_Msk                     (0xfff0000UL)  /*!< ETLNS (Bitfield-Mask: 0xfff)                         */
+/* ====================================================  MAC_PTO_Control  ==================================================== */
+ #define R_GMAC0_MAC_PTO_Control_PTOEN_Pos                                  (0UL)          /*!< PTOEN (Bit 0)                                         */
+ #define R_GMAC0_MAC_PTO_Control_PTOEN_Msk                                  (0x1UL)        /*!< PTOEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MAC_PTO_Control_ASYNCEN_Pos                                (1UL)          /*!< ASYNCEN (Bit 1)                                       */
+ #define R_GMAC0_MAC_PTO_Control_ASYNCEN_Msk                                (0x2UL)        /*!< ASYNCEN (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MAC_PTO_Control_APDREQEN_Pos                               (2UL)          /*!< APDREQEN (Bit 2)                                      */
+ #define R_GMAC0_MAC_PTO_Control_APDREQEN_Msk                               (0x4UL)        /*!< APDREQEN (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MAC_PTO_Control_ASYNCTRIG_Pos                              (4UL)          /*!< ASYNCTRIG (Bit 4)                                     */
+ #define R_GMAC0_MAC_PTO_Control_ASYNCTRIG_Msk                              (0x10UL)       /*!< ASYNCTRIG (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MAC_PTO_Control_APDREQTRIG_Pos                             (5UL)          /*!< APDREQTRIG (Bit 5)                                    */
+ #define R_GMAC0_MAC_PTO_Control_APDREQTRIG_Msk                             (0x20UL)       /*!< APDREQTRIG (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MAC_PTO_Control_DRRDIS_Pos                                 (6UL)          /*!< DRRDIS (Bit 6)                                        */
+ #define R_GMAC0_MAC_PTO_Control_DRRDIS_Msk                                 (0x40UL)       /*!< DRRDIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_PTO_Control_PDRDIS_Pos                                 (7UL)          /*!< PDRDIS (Bit 7)                                        */
+ #define R_GMAC0_MAC_PTO_Control_PDRDIS_Msk                                 (0x80UL)       /*!< PDRDIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MAC_PTO_Control_DN_Pos                                     (8UL)          /*!< DN (Bit 8)                                            */
+ #define R_GMAC0_MAC_PTO_Control_DN_Msk                                     (0xff00UL)     /*!< DN (Bitfield-Mask: 0xff)                              */
+/* ===============================================  MAC_Source_Port_Identity0  =============================================== */
+ #define R_GMAC0_MAC_Source_Port_Identity0_SPI0_Pos                         (0UL)          /*!< SPI0 (Bit 0)                                          */
+ #define R_GMAC0_MAC_Source_Port_Identity0_SPI0_Msk                         (0xffffffffUL) /*!< SPI0 (Bitfield-Mask: 0xffffffff)                      */
+/* ===============================================  MAC_Source_Port_Identity1  =============================================== */
+ #define R_GMAC0_MAC_Source_Port_Identity1_SPI1_Pos                         (0UL)          /*!< SPI1 (Bit 0)                                          */
+ #define R_GMAC0_MAC_Source_Port_Identity1_SPI1_Msk                         (0xffffffffUL) /*!< SPI1 (Bitfield-Mask: 0xffffffff)                      */
+/* ===============================================  MAC_Source_Port_Identity2  =============================================== */
+ #define R_GMAC0_MAC_Source_Port_Identity2_SPI2_Pos                         (0UL)          /*!< SPI2 (Bit 0)                                          */
+ #define R_GMAC0_MAC_Source_Port_Identity2_SPI2_Msk                         (0xffffUL)     /*!< SPI2 (Bitfield-Mask: 0xffff)                          */
+/* ===============================================  MAC_Log_Message_Interval  ================================================ */
+ #define R_GMAC0_MAC_Log_Message_Interval_LSI_Pos                           (0UL)          /*!< LSI (Bit 0)                                           */
+ #define R_GMAC0_MAC_Log_Message_Interval_LSI_Msk                           (0xffUL)       /*!< LSI (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MAC_Log_Message_Interval_DRSYNCR_Pos                       (8UL)          /*!< DRSYNCR (Bit 8)                                       */
+ #define R_GMAC0_MAC_Log_Message_Interval_DRSYNCR_Msk                       (0x700UL)      /*!< DRSYNCR (Bitfield-Mask: 0x07)                         */
+ #define R_GMAC0_MAC_Log_Message_Interval_LMPDRI_Pos                        (24UL)         /*!< LMPDRI (Bit 24)                                       */
+ #define R_GMAC0_MAC_Log_Message_Interval_LMPDRI_Msk                        (0xff000000UL) /*!< LMPDRI (Bitfield-Mask: 0xff)                          */
+/* ==================================================  MTL_Operation_Mode  =================================================== */
+ #define R_GMAC0_MTL_Operation_Mode_DTXSTS_Pos                              (1UL)          /*!< DTXSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Operation_Mode_DTXSTS_Msk                              (0x2UL)        /*!< DTXSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Operation_Mode_RAA_Pos                                 (2UL)          /*!< RAA (Bit 2)                                           */
+ #define R_GMAC0_MTL_Operation_Mode_RAA_Msk                                 (0x4UL)        /*!< RAA (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_Operation_Mode_SCHALG_Pos                              (5UL)          /*!< SCHALG (Bit 5)                                        */
+ #define R_GMAC0_MTL_Operation_Mode_SCHALG_Msk                              (0x60UL)       /*!< SCHALG (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_Operation_Mode_CNTPRST_Pos                             (8UL)          /*!< CNTPRST (Bit 8)                                       */
+ #define R_GMAC0_MTL_Operation_Mode_CNTPRST_Msk                             (0x100UL)      /*!< CNTPRST (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Operation_Mode_CNTCLR_Pos                              (9UL)          /*!< CNTCLR (Bit 9)                                        */
+ #define R_GMAC0_MTL_Operation_Mode_CNTCLR_Msk                              (0x200UL)      /*!< CNTCLR (Bitfield-Mask: 0x01)                          */
+/* =================================================  MTL_Interrupt_Status  ================================================== */
+ #define R_GMAC0_MTL_Interrupt_Status_Q0IS_Pos                              (0UL)          /*!< Q0IS (Bit 0)                                          */
+ #define R_GMAC0_MTL_Interrupt_Status_Q0IS_Msk                              (0x1UL)        /*!< Q0IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_Interrupt_Status_Q1IS_Pos                              (1UL)          /*!< Q1IS (Bit 1)                                          */
+ #define R_GMAC0_MTL_Interrupt_Status_Q1IS_Msk                              (0x2UL)        /*!< Q1IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_Interrupt_Status_Q2IS_Pos                              (2UL)          /*!< Q2IS (Bit 2)                                          */
+ #define R_GMAC0_MTL_Interrupt_Status_Q2IS_Msk                              (0x4UL)        /*!< Q2IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_Interrupt_Status_Q3IS_Pos                              (3UL)          /*!< Q3IS (Bit 3)                                          */
+ #define R_GMAC0_MTL_Interrupt_Status_Q3IS_Msk                              (0x8UL)        /*!< Q3IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_Interrupt_Status_Q4IS_Pos                              (4UL)          /*!< Q4IS (Bit 4)                                          */
+ #define R_GMAC0_MTL_Interrupt_Status_Q4IS_Msk                              (0x10UL)       /*!< Q4IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_Interrupt_Status_Q5IS_Pos                              (5UL)          /*!< Q5IS (Bit 5)                                          */
+ #define R_GMAC0_MTL_Interrupt_Status_Q5IS_Msk                              (0x20UL)       /*!< Q5IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_Interrupt_Status_Q6IS_Pos                              (6UL)          /*!< Q6IS (Bit 6)                                          */
+ #define R_GMAC0_MTL_Interrupt_Status_Q6IS_Msk                              (0x40UL)       /*!< Q6IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_Interrupt_Status_Q7IS_Pos                              (7UL)          /*!< Q7IS (Bit 7)                                          */
+ #define R_GMAC0_MTL_Interrupt_Status_Q7IS_Msk                              (0x80UL)       /*!< Q7IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_Interrupt_Status_ESTIS_Pos                             (18UL)         /*!< ESTIS (Bit 18)                                        */
+ #define R_GMAC0_MTL_Interrupt_Status_ESTIS_Msk                             (0x40000UL)    /*!< ESTIS (Bitfield-Mask: 0x01)                           */
+/* ===================================================  MTL_RxQ_DMA_Map0  ==================================================== */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q0MDMACH_Pos                              (0UL)          /*!< Q0MDMACH (Bit 0)                                      */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q0MDMACH_Msk                              (0x7UL)        /*!< Q0MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q0DDMACH_Pos                              (4UL)          /*!< Q0DDMACH (Bit 4)                                      */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q0DDMACH_Msk                              (0x10UL)       /*!< Q0DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q1MDMACH_Pos                              (8UL)          /*!< Q1MDMACH (Bit 8)                                      */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q1MDMACH_Msk                              (0x700UL)      /*!< Q1MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q1DDMACH_Pos                              (12UL)         /*!< Q1DDMACH (Bit 12)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q1DDMACH_Msk                              (0x1000UL)     /*!< Q1DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q2MDMACH_Pos                              (16UL)         /*!< Q2MDMACH (Bit 16)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q2MDMACH_Msk                              (0x70000UL)    /*!< Q2MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q2DDMACH_Pos                              (20UL)         /*!< Q2DDMACH (Bit 20)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q2DDMACH_Msk                              (0x100000UL)   /*!< Q2DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q3MDMACH_Pos                              (24UL)         /*!< Q3MDMACH (Bit 24)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q3MDMACH_Msk                              (0x7000000UL)  /*!< Q3MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q3DDMACH_Pos                              (28UL)         /*!< Q3DDMACH (Bit 28)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map0_Q3DDMACH_Msk                              (0x10000000UL) /*!< Q3DDMACH (Bitfield-Mask: 0x01)                        */
+/* ===================================================  MTL_RxQ_DMA_Map1  ==================================================== */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q4MDMACH_Pos                              (0UL)          /*!< Q4MDMACH (Bit 0)                                      */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q4MDMACH_Msk                              (0x7UL)        /*!< Q4MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q4DDMACH_Pos                              (4UL)          /*!< Q4DDMACH (Bit 4)                                      */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q4DDMACH_Msk                              (0x10UL)       /*!< Q4DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q5MDMACH_Pos                              (8UL)          /*!< Q5MDMACH (Bit 8)                                      */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q5MDMACH_Msk                              (0x700UL)      /*!< Q5MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q5DDMACH_Pos                              (12UL)         /*!< Q5DDMACH (Bit 12)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q5DDMACH_Msk                              (0x1000UL)     /*!< Q5DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q6MDMACH_Pos                              (16UL)         /*!< Q6MDMACH (Bit 16)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q6MDMACH_Msk                              (0x70000UL)    /*!< Q6MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q6DDMACH_Pos                              (20UL)         /*!< Q6DDMACH (Bit 20)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q6DDMACH_Msk                              (0x100000UL)   /*!< Q6DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q7MDMACH_Pos                              (24UL)         /*!< Q7MDMACH (Bit 24)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q7MDMACH_Msk                              (0x7000000UL)  /*!< Q7MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q7DDMACH_Pos                              (28UL)         /*!< Q7DDMACH (Bit 28)                                     */
+ #define R_GMAC0_MTL_RxQ_DMA_Map1_Q7DDMACH_Msk                              (0x10000000UL) /*!< Q7DDMACH (Bitfield-Mask: 0x01)                        */
+/* =====================================================  MTL_TBS_CTRL  ====================================================== */
+ #define R_GMAC0_MTL_TBS_CTRL_ESTM_Pos                                      (0UL)          /*!< ESTM (Bit 0)                                          */
+ #define R_GMAC0_MTL_TBS_CTRL_ESTM_Msk                                      (0x1UL)        /*!< ESTM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_TBS_CTRL_LEOV_Pos                                      (1UL)          /*!< LEOV (Bit 1)                                          */
+ #define R_GMAC0_MTL_TBS_CTRL_LEOV_Msk                                      (0x2UL)        /*!< LEOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_TBS_CTRL_LEGOS_Pos                                     (4UL)          /*!< LEGOS (Bit 4)                                         */
+ #define R_GMAC0_MTL_TBS_CTRL_LEGOS_Msk                                     (0x70UL)       /*!< LEGOS (Bitfield-Mask: 0x07)                           */
+ #define R_GMAC0_MTL_TBS_CTRL_LEOS_Pos                                      (8UL)          /*!< LEOS (Bit 8)                                          */
+ #define R_GMAC0_MTL_TBS_CTRL_LEOS_Msk                                      (0xffffff00UL) /*!< LEOS (Bitfield-Mask: 0xffffff)                        */
+/* ====================================================  MTL_EST_Control  ==================================================== */
+ #define R_GMAC0_MTL_EST_Control_EEST_Pos                                   (0UL)          /*!< EEST (Bit 0)                                          */
+ #define R_GMAC0_MTL_EST_Control_EEST_Msk                                   (0x1UL)        /*!< EEST (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Control_SSWL_Pos                                   (1UL)          /*!< SSWL (Bit 1)                                          */
+ #define R_GMAC0_MTL_EST_Control_SSWL_Msk                                   (0x2UL)        /*!< SSWL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Control_QHLBF_Pos                                  (3UL)          /*!< QHLBF (Bit 3)                                         */
+ #define R_GMAC0_MTL_EST_Control_QHLBF_Msk                                  (0x8UL)        /*!< QHLBF (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_EST_Control_DDBF_Pos                                   (4UL)          /*!< DDBF (Bit 4)                                          */
+ #define R_GMAC0_MTL_EST_Control_DDBF_Msk                                   (0x10UL)       /*!< DDBF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Control_DFBS_Pos                                   (5UL)          /*!< DFBS (Bit 5)                                          */
+ #define R_GMAC0_MTL_EST_Control_DFBS_Msk                                   (0x20UL)       /*!< DFBS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Control_LCSE_Pos                                   (6UL)          /*!< LCSE (Bit 6)                                          */
+ #define R_GMAC0_MTL_EST_Control_LCSE_Msk                                   (0xc0UL)       /*!< LCSE (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC0_MTL_EST_Control_TILS_Pos                                   (8UL)          /*!< TILS (Bit 8)                                          */
+ #define R_GMAC0_MTL_EST_Control_TILS_Msk                                   (0x700UL)      /*!< TILS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_EST_Control_CTOV_Pos                                   (12UL)         /*!< CTOV (Bit 12)                                         */
+ #define R_GMAC0_MTL_EST_Control_CTOV_Msk                                   (0xfff000UL)   /*!< CTOV (Bitfield-Mask: 0xfff)                           */
+ #define R_GMAC0_MTL_EST_Control_PTOV_Pos                                   (24UL)         /*!< PTOV (Bit 24)                                         */
+ #define R_GMAC0_MTL_EST_Control_PTOV_Msk                                   (0xff000000UL) /*!< PTOV (Bitfield-Mask: 0xff)                            */
+/* ==================================================  MTL_EST_Ext_Control  ================================================== */
+ #define R_GMAC0_MTL_EST_Ext_Control_OVHD_Pos                               (0UL)          /*!< OVHD (Bit 0)                                          */
+ #define R_GMAC0_MTL_EST_Ext_Control_OVHD_Msk                               (0x3fUL)       /*!< OVHD (Bitfield-Mask: 0x3f)                            */
+/* ====================================================  MTL_EST_Status  ===================================================== */
+ #define R_GMAC0_MTL_EST_Status_SWLC_Pos                                    (0UL)          /*!< SWLC (Bit 0)                                          */
+ #define R_GMAC0_MTL_EST_Status_SWLC_Msk                                    (0x1UL)        /*!< SWLC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Status_BTRE_Pos                                    (1UL)          /*!< BTRE (Bit 1)                                          */
+ #define R_GMAC0_MTL_EST_Status_BTRE_Msk                                    (0x2UL)        /*!< BTRE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Status_HLBF_Pos                                    (2UL)          /*!< HLBF (Bit 2)                                          */
+ #define R_GMAC0_MTL_EST_Status_HLBF_Msk                                    (0x4UL)        /*!< HLBF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Status_HLBS_Pos                                    (3UL)          /*!< HLBS (Bit 3)                                          */
+ #define R_GMAC0_MTL_EST_Status_HLBS_Msk                                    (0x8UL)        /*!< HLBS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Status_CGCE_Pos                                    (4UL)          /*!< CGCE (Bit 4)                                          */
+ #define R_GMAC0_MTL_EST_Status_CGCE_Msk                                    (0x10UL)       /*!< CGCE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Status_SWOL_Pos                                    (7UL)          /*!< SWOL (Bit 7)                                          */
+ #define R_GMAC0_MTL_EST_Status_SWOL_Msk                                    (0x80UL)       /*!< SWOL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Status_BTRL_Pos                                    (8UL)          /*!< BTRL (Bit 8)                                          */
+ #define R_GMAC0_MTL_EST_Status_BTRL_Msk                                    (0xff00UL)     /*!< BTRL (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_MTL_EST_Status_CGSN_Pos                                    (16UL)         /*!< CGSN (Bit 16)                                         */
+ #define R_GMAC0_MTL_EST_Status_CGSN_Msk                                    (0xf0000UL)    /*!< CGSN (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  MTL_EST_Sch_Error  =================================================== */
+ #define R_GMAC0_MTL_EST_Sch_Error_SEQN_Pos                                 (0UL)          /*!< SEQN (Bit 0)                                          */
+ #define R_GMAC0_MTL_EST_Sch_Error_SEQN_Msk                                 (0xffUL)       /*!< SEQN (Bitfield-Mask: 0xff)                            */
+/* ================================================  MTL_EST_Frm_Size_Error  ================================================= */
+ #define R_GMAC0_MTL_EST_Frm_Size_Error_FEQN_Pos                            (0UL)          /*!< FEQN (Bit 0)                                          */
+ #define R_GMAC0_MTL_EST_Frm_Size_Error_FEQN_Msk                            (0xffUL)       /*!< FEQN (Bitfield-Mask: 0xff)                            */
+/* ===============================================  MTL_EST_Frm_Size_Capture  ================================================ */
+ #define R_GMAC0_MTL_EST_Frm_Size_Capture_HBFS_Pos                          (0UL)          /*!< HBFS (Bit 0)                                          */
+ #define R_GMAC0_MTL_EST_Frm_Size_Capture_HBFS_Msk                          (0x7fffUL)     /*!< HBFS (Bitfield-Mask: 0x7fff)                          */
+ #define R_GMAC0_MTL_EST_Frm_Size_Capture_HBFQ_Pos                          (16UL)         /*!< HBFQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_EST_Frm_Size_Capture_HBFQ_Msk                          (0x70000UL)    /*!< HBFQ (Bitfield-Mask: 0x07)                            */
+/* ==================================================  MTL_EST_Intr_Enable  ================================================== */
+ #define R_GMAC0_MTL_EST_Intr_Enable_IECC_Pos                               (0UL)          /*!< IECC (Bit 0)                                          */
+ #define R_GMAC0_MTL_EST_Intr_Enable_IECC_Msk                               (0x1UL)        /*!< IECC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Intr_Enable_IEBE_Pos                               (1UL)          /*!< IEBE (Bit 1)                                          */
+ #define R_GMAC0_MTL_EST_Intr_Enable_IEBE_Msk                               (0x2UL)        /*!< IEBE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Intr_Enable_IEHF_Pos                               (2UL)          /*!< IEHF (Bit 2)                                          */
+ #define R_GMAC0_MTL_EST_Intr_Enable_IEHF_Msk                               (0x4UL)        /*!< IEHF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Intr_Enable_IEHS_Pos                               (3UL)          /*!< IEHS (Bit 3)                                          */
+ #define R_GMAC0_MTL_EST_Intr_Enable_IEHS_Msk                               (0x8UL)        /*!< IEHS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_Intr_Enable_CGCE_Pos                               (4UL)          /*!< CGCE (Bit 4)                                          */
+ #define R_GMAC0_MTL_EST_Intr_Enable_CGCE_Msk                               (0x10UL)       /*!< CGCE (Bitfield-Mask: 0x01)                            */
+/* ==================================================  MTL_EST_GCL_Control  ================================================== */
+ #define R_GMAC0_MTL_EST_GCL_Control_SRWO_Pos                               (0UL)          /*!< SRWO (Bit 0)                                          */
+ #define R_GMAC0_MTL_EST_GCL_Control_SRWO_Msk                               (0x1UL)        /*!< SRWO (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_GCL_Control_R1W0_Pos                               (1UL)          /*!< R1W0 (Bit 1)                                          */
+ #define R_GMAC0_MTL_EST_GCL_Control_R1W0_Msk                               (0x2UL)        /*!< R1W0 (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_GCL_Control_GCRR_Pos                               (2UL)          /*!< GCRR (Bit 2)                                          */
+ #define R_GMAC0_MTL_EST_GCL_Control_GCRR_Msk                               (0x4UL)        /*!< GCRR (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_GCL_Control_DBGM_Pos                               (4UL)          /*!< DBGM (Bit 4)                                          */
+ #define R_GMAC0_MTL_EST_GCL_Control_DBGM_Msk                               (0x10UL)       /*!< DBGM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_GCL_Control_DBGB_Pos                               (5UL)          /*!< DBGB (Bit 5)                                          */
+ #define R_GMAC0_MTL_EST_GCL_Control_DBGB_Msk                               (0x20UL)       /*!< DBGB (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_EST_GCL_Control_ADDR_Pos                               (8UL)          /*!< ADDR (Bit 8)                                          */
+ #define R_GMAC0_MTL_EST_GCL_Control_ADDR_Msk                               (0xff00UL)     /*!< ADDR (Bitfield-Mask: 0xff)                            */
+/* ===================================================  MTL_EST_GCL_Data  ==================================================== */
+ #define R_GMAC0_MTL_EST_GCL_Data_GCD_Pos                                   (0UL)          /*!< GCD (Bit 0)                                           */
+ #define R_GMAC0_MTL_EST_GCL_Data_GCD_Msk                                   (0xffffffffUL) /*!< GCD (Bitfield-Mask: 0xffffffff)                       */
+/* ===================================================  MTL_FPE_CTRL_STS  ==================================================== */
+ #define R_GMAC0_MTL_FPE_CTRL_STS_AFSZ_Pos                                  (0UL)          /*!< AFSZ (Bit 0)                                          */
+ #define R_GMAC0_MTL_FPE_CTRL_STS_AFSZ_Msk                                  (0x3UL)        /*!< AFSZ (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC0_MTL_FPE_CTRL_STS_PEC_Pos                                   (8UL)          /*!< PEC (Bit 8)                                           */
+ #define R_GMAC0_MTL_FPE_CTRL_STS_PEC_Msk                                   (0xff00UL)     /*!< PEC (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC0_MTL_FPE_CTRL_STS_HRS_Pos                                   (28UL)         /*!< HRS (Bit 28)                                          */
+ #define R_GMAC0_MTL_FPE_CTRL_STS_HRS_Msk                                   (0x10000000UL) /*!< HRS (Bitfield-Mask: 0x01)                             */
+/* ====================================================  MTL_FPE_Advance  ==================================================== */
+ #define R_GMAC0_MTL_FPE_Advance_HADV_Pos                                   (0UL)          /*!< HADV (Bit 0)                                          */
+ #define R_GMAC0_MTL_FPE_Advance_HADV_Msk                                   (0xffffUL)     /*!< HADV (Bitfield-Mask: 0xffff)                          */
+ #define R_GMAC0_MTL_FPE_Advance_RADV_Pos                                   (16UL)         /*!< RADV (Bit 16)                                         */
+ #define R_GMAC0_MTL_FPE_Advance_RADV_Msk                                   (0xffff0000UL) /*!< RADV (Bitfield-Mask: 0xffff)                          */
+/* ================================================  MTL_TXQ0_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC0_MTL_TXQ0_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ==================================================  MTL_TXQ0_UNDERFLOW  =================================================== */
+ #define R_GMAC0_MTL_TXQ0_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC0_MTL_TXQ0_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC0_MTL_TXQ0_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC0_MTL_TXQ0_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ====================================================  MTL_TXQ0_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC0_MTL_TXQ0_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ==================================================  MTL_TXQ0_ETS_STATUS  ================================================== */
+ #define R_GMAC0_MTL_TXQ0_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ0_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ================================================  MTL_TXQ0_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC0_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC0_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ============================================  MTL_Q0_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC0_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ================================================  MTL_RXQ0_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC0_MTL_RXQ0_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ==========================================  MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC0_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC0_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC0_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC0_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC0_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC0_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC0_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ====================================================  MTL_RXQ0_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_RXQ0_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC0_MTL_RXQ0_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_RXQ0_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_RXQ0_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ0_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_RXQ0_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ0_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_RXQ0_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ===================================================  MTL_RXQ0_CONTROL  ==================================================== */
+ #define R_GMAC0_MTL_RXQ0_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC0_MTL_RXQ0_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC0_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ================================================  MTL_TXQ1_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC0_MTL_TXQ1_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ2_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC0_MTL_TXQ2_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ3_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC0_MTL_TXQ3_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ4_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC0_MTL_TXQ4_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ5_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC0_MTL_TXQ5_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ6_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC0_MTL_TXQ6_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ7_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC0_MTL_TXQ7_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ==================================================  MTL_TXQ1_UNDERFLOW  =================================================== */
+ #define R_GMAC0_MTL_TXQ1_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC0_MTL_TXQ1_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC0_MTL_TXQ1_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC0_MTL_TXQ1_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ2_UNDERFLOW  =================================================== */
+ #define R_GMAC0_MTL_TXQ2_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC0_MTL_TXQ2_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC0_MTL_TXQ2_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC0_MTL_TXQ2_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ3_UNDERFLOW  =================================================== */
+ #define R_GMAC0_MTL_TXQ3_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC0_MTL_TXQ3_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC0_MTL_TXQ3_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC0_MTL_TXQ3_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ4_UNDERFLOW  =================================================== */
+ #define R_GMAC0_MTL_TXQ4_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC0_MTL_TXQ4_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC0_MTL_TXQ4_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC0_MTL_TXQ4_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ5_UNDERFLOW  =================================================== */
+ #define R_GMAC0_MTL_TXQ5_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC0_MTL_TXQ5_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC0_MTL_TXQ5_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC0_MTL_TXQ5_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ6_UNDERFLOW  =================================================== */
+ #define R_GMAC0_MTL_TXQ6_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC0_MTL_TXQ6_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC0_MTL_TXQ6_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC0_MTL_TXQ6_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ7_UNDERFLOW  =================================================== */
+ #define R_GMAC0_MTL_TXQ7_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC0_MTL_TXQ7_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC0_MTL_TXQ7_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC0_MTL_TXQ7_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ====================================================  MTL_TXQ1_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC0_MTL_TXQ1_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ2_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC0_MTL_TXQ2_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ3_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC0_MTL_TXQ3_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ4_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC0_MTL_TXQ4_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ5_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC0_MTL_TXQ5_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ6_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC0_MTL_TXQ6_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ7_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC0_MTL_TXQ7_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* =================================================  MTL_TXQ1_ETS_CONTROL  ================================================== */
+ #define R_GMAC0_MTL_TXQ1_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ1_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_TXQ1_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC0_MTL_TXQ1_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MTL_TXQ1_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ1_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ2_ETS_CONTROL  ================================================== */
+ #define R_GMAC0_MTL_TXQ2_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ2_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_TXQ2_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC0_MTL_TXQ2_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MTL_TXQ2_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ2_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ3_ETS_CONTROL  ================================================== */
+ #define R_GMAC0_MTL_TXQ3_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ3_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_TXQ3_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC0_MTL_TXQ3_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MTL_TXQ3_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ3_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ4_ETS_CONTROL  ================================================== */
+ #define R_GMAC0_MTL_TXQ4_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ4_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_TXQ4_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC0_MTL_TXQ4_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MTL_TXQ4_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ4_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ5_ETS_CONTROL  ================================================== */
+ #define R_GMAC0_MTL_TXQ5_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ5_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_TXQ5_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC0_MTL_TXQ5_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MTL_TXQ5_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ5_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ6_ETS_CONTROL  ================================================== */
+ #define R_GMAC0_MTL_TXQ6_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ6_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_TXQ6_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC0_MTL_TXQ6_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MTL_TXQ6_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ6_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ7_ETS_CONTROL  ================================================== */
+ #define R_GMAC0_MTL_TXQ7_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC0_MTL_TXQ7_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_TXQ7_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC0_MTL_TXQ7_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_MTL_TXQ7_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC0_MTL_TXQ7_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* ==================================================  MTL_TXQ1_ETS_STATUS  ================================================== */
+ #define R_GMAC0_MTL_TXQ1_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ1_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ2_ETS_STATUS  ================================================== */
+ #define R_GMAC0_MTL_TXQ2_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ2_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ3_ETS_STATUS  ================================================== */
+ #define R_GMAC0_MTL_TXQ3_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ3_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ4_ETS_STATUS  ================================================== */
+ #define R_GMAC0_MTL_TXQ4_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ4_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ5_ETS_STATUS  ================================================== */
+ #define R_GMAC0_MTL_TXQ5_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ5_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ6_ETS_STATUS  ================================================== */
+ #define R_GMAC0_MTL_TXQ6_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ6_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ7_ETS_STATUS  ================================================== */
+ #define R_GMAC0_MTL_TXQ7_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ7_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ================================================  MTL_TXQ1_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC0_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC0_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ2_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC0_MTL_TXQ2_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC0_MTL_TXQ2_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ3_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC0_MTL_TXQ3_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC0_MTL_TXQ3_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ4_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC0_MTL_TXQ4_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC0_MTL_TXQ4_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ5_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC0_MTL_TXQ5_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC0_MTL_TXQ5_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ6_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC0_MTL_TXQ6_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC0_MTL_TXQ6_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ7_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC0_MTL_TXQ7_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC0_MTL_TXQ7_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ===============================================  MTL_TXQ1_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC0_MTL_TXQ1_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ1_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ2_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC0_MTL_TXQ2_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ2_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ3_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC0_MTL_TXQ3_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ3_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ4_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC0_MTL_TXQ4_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ4_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ5_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC0_MTL_TXQ5_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ5_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ6_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC0_MTL_TXQ6_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ6_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ7_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC0_MTL_TXQ7_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC0_MTL_TXQ7_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===================================================  MTL_TXQ1_HICREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ1_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ1_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ2_HICREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ2_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ2_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ3_HICREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ3_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ3_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ4_HICREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ4_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ4_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ5_HICREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ5_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ5_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ6_HICREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ6_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ6_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ7_HICREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ7_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ7_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ1_LOCREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ1_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ1_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ2_LOCREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ2_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ2_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ3_LOCREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ3_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ3_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ4_LOCREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ4_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ4_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ5_LOCREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ5_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ5_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ6_LOCREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ6_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ6_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ7_LOCREDIT  =================================================== */
+ #define R_GMAC0_MTL_TXQ7_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC0_MTL_TXQ7_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ============================================  MTL_Q1_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC0_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q2_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC0_MTL_Q2_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q3_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC0_MTL_Q3_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q4_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC0_MTL_Q4_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q5_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC0_MTL_Q5_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q6_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC0_MTL_Q6_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q7_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC0_MTL_Q7_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ================================================  MTL_RXQ1_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC0_MTL_RXQ1_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ2_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC0_MTL_RXQ2_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ3_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC0_MTL_RXQ3_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ4_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC0_MTL_RXQ4_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ5_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC0_MTL_RXQ5_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ6_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC0_MTL_RXQ6_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ7_OPERATION_MODE  ================================================ */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC0_MTL_RXQ7_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ==========================================  MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC0_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC0_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC0_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC0_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC0_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC0_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC0_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC0_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC0_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC0_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC0_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC0_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC0_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC0_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC0_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC0_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC0_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC0_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC0_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC0_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC0_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC0_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC0_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC0_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC0_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC0_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC0_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC0_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC0_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC0_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC0_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC0_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC0_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC0_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC0_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC0_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC0_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC0_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC0_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC0_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC0_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC0_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC0_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC0_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC0_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC0_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC0_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC0_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC0_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC0_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ====================================================  MTL_RXQ1_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_RXQ1_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC0_MTL_RXQ1_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_RXQ1_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_RXQ1_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ1_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_RXQ1_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ1_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_RXQ1_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ2_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_RXQ2_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC0_MTL_RXQ2_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_RXQ2_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_RXQ2_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ2_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_RXQ2_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ2_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_RXQ2_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ3_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_RXQ3_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC0_MTL_RXQ3_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_RXQ3_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_RXQ3_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ3_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_RXQ3_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ3_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_RXQ3_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ4_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_RXQ4_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC0_MTL_RXQ4_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_RXQ4_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_RXQ4_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ4_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_RXQ4_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ4_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_RXQ4_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ5_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_RXQ5_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC0_MTL_RXQ5_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_RXQ5_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_RXQ5_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ5_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_RXQ5_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ5_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_RXQ5_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ6_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_RXQ6_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC0_MTL_RXQ6_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_RXQ6_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_RXQ6_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ6_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_RXQ6_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ6_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_RXQ6_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ7_DEBUG  ===================================================== */
+ #define R_GMAC0_MTL_RXQ7_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC0_MTL_RXQ7_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_MTL_RXQ7_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC0_MTL_RXQ7_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ7_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC0_MTL_RXQ7_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC0_MTL_RXQ7_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC0_MTL_RXQ7_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ===================================================  MTL_RXQ1_CONTROL  ==================================================== */
+ #define R_GMAC0_MTL_RXQ1_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC0_MTL_RXQ1_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC0_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ2_CONTROL  ==================================================== */
+ #define R_GMAC0_MTL_RXQ2_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC0_MTL_RXQ2_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RXQ2_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC0_MTL_RXQ2_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ3_CONTROL  ==================================================== */
+ #define R_GMAC0_MTL_RXQ3_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC0_MTL_RXQ3_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RXQ3_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC0_MTL_RXQ3_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ4_CONTROL  ==================================================== */
+ #define R_GMAC0_MTL_RXQ4_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC0_MTL_RXQ4_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RXQ4_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC0_MTL_RXQ4_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ5_CONTROL  ==================================================== */
+ #define R_GMAC0_MTL_RXQ5_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC0_MTL_RXQ5_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RXQ5_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC0_MTL_RXQ5_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ6_CONTROL  ==================================================== */
+ #define R_GMAC0_MTL_RXQ6_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC0_MTL_RXQ6_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RXQ6_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC0_MTL_RXQ6_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ7_CONTROL  ==================================================== */
+ #define R_GMAC0_MTL_RXQ7_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC0_MTL_RXQ7_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC0_MTL_RXQ7_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC0_MTL_RXQ7_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* =======================================================  DMA_Mode  ======================================================== */
+ #define R_GMAC0_DMA_Mode_SWR_Pos                                           (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_GMAC0_DMA_Mode_SWR_Msk                                           (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_Mode_TAA_Pos                                           (2UL)          /*!< TAA (Bit 2)                                           */
+ #define R_GMAC0_DMA_Mode_TAA_Msk                                           (0x1cUL)       /*!< TAA (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_Mode_DSPW_Pos                                          (8UL)          /*!< DSPW (Bit 8)                                          */
+ #define R_GMAC0_DMA_Mode_DSPW_Msk                                          (0x100UL)      /*!< DSPW (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_Mode_TXPR_Pos                                          (11UL)         /*!< TXPR (Bit 11)                                         */
+ #define R_GMAC0_DMA_Mode_TXPR_Msk                                          (0x800UL)      /*!< TXPR (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_Mode_INTM_Pos                                          (16UL)         /*!< INTM (Bit 16)                                         */
+ #define R_GMAC0_DMA_Mode_INTM_Msk                                          (0x30000UL)    /*!< INTM (Bitfield-Mask: 0x03)                            */
+/* ====================================================  DMA_SysBus_Mode  ==================================================== */
+ #define R_GMAC0_DMA_SysBus_Mode_FB_Pos                                     (0UL)          /*!< FB (Bit 0)                                            */
+ #define R_GMAC0_DMA_SysBus_Mode_FB_Msk                                     (0x1UL)        /*!< FB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_SysBus_Mode_BLEN4_Pos                                  (1UL)          /*!< BLEN4 (Bit 1)                                         */
+ #define R_GMAC0_DMA_SysBus_Mode_BLEN4_Msk                                  (0x2UL)        /*!< BLEN4 (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_SysBus_Mode_BLEN8_Pos                                  (2UL)          /*!< BLEN8 (Bit 2)                                         */
+ #define R_GMAC0_DMA_SysBus_Mode_BLEN8_Msk                                  (0x4UL)        /*!< BLEN8 (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_SysBus_Mode_BLEN16_Pos                                 (3UL)          /*!< BLEN16 (Bit 3)                                        */
+ #define R_GMAC0_DMA_SysBus_Mode_BLEN16_Msk                                 (0x8UL)        /*!< BLEN16 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC0_DMA_SysBus_Mode_AALE_Pos                                   (10UL)         /*!< AALE (Bit 10)                                         */
+ #define R_GMAC0_DMA_SysBus_Mode_AALE_Msk                                   (0x400UL)      /*!< AALE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_SysBus_Mode_AAL_Pos                                    (12UL)         /*!< AAL (Bit 12)                                          */
+ #define R_GMAC0_DMA_SysBus_Mode_AAL_Msk                                    (0x1000UL)     /*!< AAL (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_SysBus_Mode_ONEKBBE_Pos                                (13UL)         /*!< ONEKBBE (Bit 13)                                      */
+ #define R_GMAC0_DMA_SysBus_Mode_ONEKBBE_Msk                                (0x2000UL)     /*!< ONEKBBE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_DMA_SysBus_Mode_RD_OSR_LMT_Pos                             (16UL)         /*!< RD_OSR_LMT (Bit 16)                                   */
+ #define R_GMAC0_DMA_SysBus_Mode_RD_OSR_LMT_Msk                             (0xf0000UL)    /*!< RD_OSR_LMT (Bitfield-Mask: 0x0f)                      */
+ #define R_GMAC0_DMA_SysBus_Mode_WR_OSR_LMT_Pos                             (24UL)         /*!< WR_OSR_LMT (Bit 24)                                   */
+ #define R_GMAC0_DMA_SysBus_Mode_WR_OSR_LMT_Msk                             (0xf000000UL)  /*!< WR_OSR_LMT (Bitfield-Mask: 0x0f)                      */
+ #define R_GMAC0_DMA_SysBus_Mode_LPI_XIT_PKT_Pos                            (30UL)         /*!< LPI_XIT_PKT (Bit 30)                                  */
+ #define R_GMAC0_DMA_SysBus_Mode_LPI_XIT_PKT_Msk                            (0x40000000UL) /*!< LPI_XIT_PKT (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC0_DMA_SysBus_Mode_EN_LPI_Pos                                 (31UL)         /*!< EN_LPI (Bit 31)                                       */
+ #define R_GMAC0_DMA_SysBus_Mode_EN_LPI_Msk                                 (0x80000000UL) /*!< EN_LPI (Bitfield-Mask: 0x01)                          */
+/* =================================================  DMA_Interrupt_Status  ================================================== */
+ #define R_GMAC0_DMA_Interrupt_Status_DC0IS_Pos                             (0UL)          /*!< DC0IS (Bit 0)                                         */
+ #define R_GMAC0_DMA_Interrupt_Status_DC0IS_Msk                             (0x1UL)        /*!< DC0IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_DC1IS_Pos                             (1UL)          /*!< DC1IS (Bit 1)                                         */
+ #define R_GMAC0_DMA_Interrupt_Status_DC1IS_Msk                             (0x2UL)        /*!< DC1IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_DC2IS_Pos                             (2UL)          /*!< DC2IS (Bit 2)                                         */
+ #define R_GMAC0_DMA_Interrupt_Status_DC2IS_Msk                             (0x4UL)        /*!< DC2IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_DC3IS_Pos                             (3UL)          /*!< DC3IS (Bit 3)                                         */
+ #define R_GMAC0_DMA_Interrupt_Status_DC3IS_Msk                             (0x8UL)        /*!< DC3IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_DC4IS_Pos                             (4UL)          /*!< DC4IS (Bit 4)                                         */
+ #define R_GMAC0_DMA_Interrupt_Status_DC4IS_Msk                             (0x10UL)       /*!< DC4IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_DC5IS_Pos                             (5UL)          /*!< DC5IS (Bit 5)                                         */
+ #define R_GMAC0_DMA_Interrupt_Status_DC5IS_Msk                             (0x20UL)       /*!< DC5IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_DC6IS_Pos                             (6UL)          /*!< DC6IS (Bit 6)                                         */
+ #define R_GMAC0_DMA_Interrupt_Status_DC6IS_Msk                             (0x40UL)       /*!< DC6IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_DC7IS_Pos                             (7UL)          /*!< DC7IS (Bit 7)                                         */
+ #define R_GMAC0_DMA_Interrupt_Status_DC7IS_Msk                             (0x80UL)       /*!< DC7IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_MTLIS_Pos                             (16UL)         /*!< MTLIS (Bit 16)                                        */
+ #define R_GMAC0_DMA_Interrupt_Status_MTLIS_Msk                             (0x10000UL)    /*!< MTLIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC0_DMA_Interrupt_Status_MACIS_Pos                             (17UL)         /*!< MACIS (Bit 17)                                        */
+ #define R_GMAC0_DMA_Interrupt_Status_MACIS_Msk                             (0x20000UL)    /*!< MACIS (Bitfield-Mask: 0x01)                           */
+/* ===================================================  DMA_Debug_Status0  =================================================== */
+ #define R_GMAC0_DMA_Debug_Status0_AXWHSTS_Pos                              (0UL)          /*!< AXWHSTS (Bit 0)                                       */
+ #define R_GMAC0_DMA_Debug_Status0_AXWHSTS_Msk                              (0x1UL)        /*!< AXWHSTS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_DMA_Debug_Status0_AXRHSTS_Pos                              (1UL)          /*!< AXRHSTS (Bit 1)                                       */
+ #define R_GMAC0_DMA_Debug_Status0_AXRHSTS_Msk                              (0x2UL)        /*!< AXRHSTS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC0_DMA_Debug_Status0_RPS0_Pos                                 (8UL)          /*!< RPS0 (Bit 8)                                          */
+ #define R_GMAC0_DMA_Debug_Status0_RPS0_Msk                                 (0xf00UL)      /*!< RPS0 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status0_TPS0_Pos                                 (12UL)         /*!< TPS0 (Bit 12)                                         */
+ #define R_GMAC0_DMA_Debug_Status0_TPS0_Msk                                 (0xf000UL)     /*!< TPS0 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status0_RPS1_Pos                                 (16UL)         /*!< RPS1 (Bit 16)                                         */
+ #define R_GMAC0_DMA_Debug_Status0_RPS1_Msk                                 (0xf0000UL)    /*!< RPS1 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status0_TPS1_Pos                                 (20UL)         /*!< TPS1 (Bit 20)                                         */
+ #define R_GMAC0_DMA_Debug_Status0_TPS1_Msk                                 (0xf00000UL)   /*!< TPS1 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status0_RPS2_Pos                                 (24UL)         /*!< RPS2 (Bit 24)                                         */
+ #define R_GMAC0_DMA_Debug_Status0_RPS2_Msk                                 (0xf000000UL)  /*!< RPS2 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status0_TPS2_Pos                                 (28UL)         /*!< TPS2 (Bit 28)                                         */
+ #define R_GMAC0_DMA_Debug_Status0_TPS2_Msk                                 (0xf0000000UL) /*!< TPS2 (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  DMA_Debug_Status1  =================================================== */
+ #define R_GMAC0_DMA_Debug_Status1_RPS3_Pos                                 (0UL)          /*!< RPS3 (Bit 0)                                          */
+ #define R_GMAC0_DMA_Debug_Status1_RPS3_Msk                                 (0xfUL)        /*!< RPS3 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status1_TPS3_Pos                                 (4UL)          /*!< TPS3 (Bit 4)                                          */
+ #define R_GMAC0_DMA_Debug_Status1_TPS3_Msk                                 (0xf0UL)       /*!< TPS3 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status1_RPS4_Pos                                 (8UL)          /*!< RPS4 (Bit 8)                                          */
+ #define R_GMAC0_DMA_Debug_Status1_RPS4_Msk                                 (0xf00UL)      /*!< RPS4 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status1_TPS4_Pos                                 (12UL)         /*!< TPS4 (Bit 12)                                         */
+ #define R_GMAC0_DMA_Debug_Status1_TPS4_Msk                                 (0xf000UL)     /*!< TPS4 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status1_RPS5_Pos                                 (16UL)         /*!< RPS5 (Bit 16)                                         */
+ #define R_GMAC0_DMA_Debug_Status1_RPS5_Msk                                 (0xf0000UL)    /*!< RPS5 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status1_TPS5_Pos                                 (20UL)         /*!< TPS5 (Bit 20)                                         */
+ #define R_GMAC0_DMA_Debug_Status1_TPS5_Msk                                 (0xf00000UL)   /*!< TPS5 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status1_RPS6_Pos                                 (24UL)         /*!< RPS6 (Bit 24)                                         */
+ #define R_GMAC0_DMA_Debug_Status1_RPS6_Msk                                 (0xf000000UL)  /*!< RPS6 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status1_TPS6_Pos                                 (28UL)         /*!< TPS6 (Bit 28)                                         */
+ #define R_GMAC0_DMA_Debug_Status1_TPS6_Msk                                 (0xf0000000UL) /*!< TPS6 (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  DMA_Debug_Status2  =================================================== */
+ #define R_GMAC0_DMA_Debug_Status2_RPS7_Pos                                 (0UL)          /*!< RPS7 (Bit 0)                                          */
+ #define R_GMAC0_DMA_Debug_Status2_RPS7_Msk                                 (0xfUL)        /*!< RPS7 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC0_DMA_Debug_Status2_TPS7_Pos                                 (4UL)          /*!< TPS7 (Bit 4)                                          */
+ #define R_GMAC0_DMA_Debug_Status2_TPS7_Msk                                 (0xf0UL)       /*!< TPS7 (Bitfield-Mask: 0x0f)                            */
+/* ================================================  AXI_LPI_Entry_Interval  ================================================= */
+ #define R_GMAC0_AXI_LPI_Entry_Interval_LPIEI_Pos                           (0UL)          /*!< LPIEI (Bit 0)                                         */
+ #define R_GMAC0_AXI_LPI_Entry_Interval_LPIEI_Msk                           (0xfUL)        /*!< LPIEI (Bitfield-Mask: 0x0f)                           */
+/* =====================================================  DMA_TBS_CTRL0  ===================================================== */
+ #define R_GMAC0_DMA_TBS_CTRL0_FTOV_Pos                                     (0UL)          /*!< FTOV (Bit 0)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL0_FTOV_Msk                                     (0x1UL)        /*!< FTOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_TBS_CTRL0_FGOS_Pos                                     (4UL)          /*!< FGOS (Bit 4)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL0_FGOS_Msk                                     (0x70UL)       /*!< FGOS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_DMA_TBS_CTRL0_FTOS_Pos                                     (8UL)          /*!< FTOS (Bit 8)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL0_FTOS_Msk                                     (0xffffff00UL) /*!< FTOS (Bitfield-Mask: 0xffffff)                        */
+/* =====================================================  DMA_TBS_CTRL1  ===================================================== */
+ #define R_GMAC0_DMA_TBS_CTRL1_FTOV_Pos                                     (0UL)          /*!< FTOV (Bit 0)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL1_FTOV_Msk                                     (0x1UL)        /*!< FTOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_TBS_CTRL1_FGOS_Pos                                     (4UL)          /*!< FGOS (Bit 4)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL1_FGOS_Msk                                     (0x70UL)       /*!< FGOS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_DMA_TBS_CTRL1_FTOS_Pos                                     (8UL)          /*!< FTOS (Bit 8)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL1_FTOS_Msk                                     (0xffffff00UL) /*!< FTOS (Bitfield-Mask: 0xffffff)                        */
+/* =====================================================  DMA_TBS_CTRL2  ===================================================== */
+ #define R_GMAC0_DMA_TBS_CTRL2_FTOV_Pos                                     (0UL)          /*!< FTOV (Bit 0)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL2_FTOV_Msk                                     (0x1UL)        /*!< FTOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_TBS_CTRL2_FGOS_Pos                                     (4UL)          /*!< FGOS (Bit 4)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL2_FGOS_Msk                                     (0x70UL)       /*!< FGOS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_DMA_TBS_CTRL2_FTOS_Pos                                     (8UL)          /*!< FTOS (Bit 8)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL2_FTOS_Msk                                     (0xffffff00UL) /*!< FTOS (Bitfield-Mask: 0xffffff)                        */
+/* =====================================================  DMA_TBS_CTRL3  ===================================================== */
+ #define R_GMAC0_DMA_TBS_CTRL3_FTOV_Pos                                     (0UL)          /*!< FTOV (Bit 0)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL3_FTOV_Msk                                     (0x1UL)        /*!< FTOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_TBS_CTRL3_FGOS_Pos                                     (4UL)          /*!< FGOS (Bit 4)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL3_FGOS_Msk                                     (0x70UL)       /*!< FGOS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC0_DMA_TBS_CTRL3_FTOS_Pos                                     (8UL)          /*!< FTOS (Bit 8)                                          */
+ #define R_GMAC0_DMA_TBS_CTRL3_FTOS_Msk                                     (0xffffff00UL) /*!< FTOS (Bitfield-Mask: 0xffffff)                        */
+/* ====================================================  DMA_CH0_CONTROL  ==================================================== */
+ #define R_GMAC0_DMA_CH0_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC0_DMA_CH0_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH0_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC0_DMA_CH0_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH1_CONTROL  ==================================================== */
+ #define R_GMAC0_DMA_CH1_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC0_DMA_CH1_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH1_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC0_DMA_CH1_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH2_CONTROL  ==================================================== */
+ #define R_GMAC0_DMA_CH2_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC0_DMA_CH2_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH2_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC0_DMA_CH2_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH3_CONTROL  ==================================================== */
+ #define R_GMAC0_DMA_CH3_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC0_DMA_CH3_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH3_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC0_DMA_CH3_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH4_CONTROL  ==================================================== */
+ #define R_GMAC0_DMA_CH4_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC0_DMA_CH4_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH4_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC0_DMA_CH4_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH5_CONTROL  ==================================================== */
+ #define R_GMAC0_DMA_CH5_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC0_DMA_CH5_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH5_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC0_DMA_CH5_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH6_CONTROL  ==================================================== */
+ #define R_GMAC0_DMA_CH6_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC0_DMA_CH6_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH6_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC0_DMA_CH6_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH7_CONTROL  ==================================================== */
+ #define R_GMAC0_DMA_CH7_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC0_DMA_CH7_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH7_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC0_DMA_CH7_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH0_TX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC0_DMA_CH0_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH1_TX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC0_DMA_CH1_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH2_TX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC0_DMA_CH2_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH3_TX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC0_DMA_CH3_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH4_TX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC0_DMA_CH4_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH5_TX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC0_DMA_CH5_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH6_TX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC0_DMA_CH6_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH7_TX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC0_DMA_CH7_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH0_RX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH1_RX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH2_RX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH3_RX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH4_RX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH5_RX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH6_RX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH7_RX_CONTROL  =================================================== */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==============================================  DMA_CH0_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH1_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH2_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH2_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH2_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH3_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH3_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH3_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH4_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH4_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH4_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH5_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH5_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH5_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH6_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH6_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH6_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH7_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH7_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH7_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH0_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH1_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH2_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH2_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH2_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH3_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH3_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH3_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH4_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH4_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH4_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH5_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH5_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH5_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH6_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH6_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH6_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH7_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC0_DMA_CH7_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC0_DMA_CH7_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH0_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH1_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH2_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH2_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH2_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH3_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH3_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH3_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH4_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH4_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH4_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH5_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH5_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH5_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH6_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH6_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH6_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH7_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH7_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH7_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH0_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH1_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH2_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH2_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH2_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH3_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH3_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH3_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH4_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH4_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH4_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH5_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH5_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH5_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH6_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH6_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH6_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH7_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC0_DMA_CH7_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH7_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH0_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC0_DMA_CH0_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH0_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH1_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC0_DMA_CH1_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH1_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH2_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC0_DMA_CH2_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH2_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH3_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC0_DMA_CH3_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH3_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH4_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC0_DMA_CH4_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH4_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH5_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC0_DMA_CH5_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH5_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH6_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC0_DMA_CH6_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH6_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH7_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC0_DMA_CH7_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH7_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==================================================  DMA_CH0_RX_CONTROL2  ================================================== */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC0_DMA_CH0_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH1_RX_CONTROL2  ================================================== */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC0_DMA_CH1_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH2_RX_CONTROL2  ================================================== */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC0_DMA_CH2_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH3_RX_CONTROL2  ================================================== */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC0_DMA_CH3_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH4_RX_CONTROL2  ================================================== */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC0_DMA_CH4_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH5_RX_CONTROL2  ================================================== */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC0_DMA_CH5_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH6_RX_CONTROL2  ================================================== */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC0_DMA_CH6_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH7_RX_CONTROL2  ================================================== */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC0_DMA_CH7_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ===============================================  DMA_CH0_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH0_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH1_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH1_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH2_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH2_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH3_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH3_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH4_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH4_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH5_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH5_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH6_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH6_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH7_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH7_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ==========================================  DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC0_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC0_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC0_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC0_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC0_DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC0_DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC0_DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC0_DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC0_DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC0_DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC0_DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC0_DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC0_DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC0_DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC0_DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC0_DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC0_DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* =========================================  DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC0_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC0_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC0_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC0_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC0_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC0_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC0_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC0_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC0_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC0_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC0_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC0_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC0_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC0_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC0_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC0_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC0_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC0_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* ==============================================  DMA_CH0_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH1_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH2_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH2_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH2_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH3_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH3_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH3_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH4_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH4_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH4_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH5_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH5_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH5_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH6_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH6_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH6_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH7_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH7_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH7_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH0_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH1_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH2_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH2_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH2_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH3_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH3_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH3_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH4_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH4_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH4_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH5_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH5_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH5_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH6_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH6_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH6_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH7_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC0_DMA_CH7_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH7_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* =============================================  DMA_CH0_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH1_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH2_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH2_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH2_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH3_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH3_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH3_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH4_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH4_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH4_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH5_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH5_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH5_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH6_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH6_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH6_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH7_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH7_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH7_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH0_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH1_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH2_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH2_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH2_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH3_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH3_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH3_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH4_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH4_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH4_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH5_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH5_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH5_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH6_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH6_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH6_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH7_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC0_DMA_CH7_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC0_DMA_CH7_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* ====================================================  DMA_CH0_STATUS  ===================================================== */
+ #define R_GMAC0_DMA_CH0_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH0_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH0_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH0_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC0_DMA_CH0_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC0_DMA_CH0_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH0_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC0_DMA_CH0_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH0_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC0_DMA_CH0_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC0_DMA_CH0_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC0_DMA_CH0_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC0_DMA_CH0_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC0_DMA_CH0_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH0_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH0_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH0_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH0_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC0_DMA_CH0_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH1_STATUS  ===================================================== */
+ #define R_GMAC0_DMA_CH1_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH1_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH1_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH1_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC0_DMA_CH1_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC0_DMA_CH1_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH1_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC0_DMA_CH1_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH1_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC0_DMA_CH1_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC0_DMA_CH1_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC0_DMA_CH1_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC0_DMA_CH1_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC0_DMA_CH1_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH1_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH1_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH1_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH1_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC0_DMA_CH1_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH2_STATUS  ===================================================== */
+ #define R_GMAC0_DMA_CH2_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH2_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH2_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH2_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC0_DMA_CH2_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC0_DMA_CH2_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH2_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC0_DMA_CH2_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH2_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC0_DMA_CH2_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC0_DMA_CH2_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC0_DMA_CH2_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC0_DMA_CH2_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC0_DMA_CH2_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH2_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH2_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH2_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH2_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC0_DMA_CH2_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH3_STATUS  ===================================================== */
+ #define R_GMAC0_DMA_CH3_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH3_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH3_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH3_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC0_DMA_CH3_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC0_DMA_CH3_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH3_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC0_DMA_CH3_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH3_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC0_DMA_CH3_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC0_DMA_CH3_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC0_DMA_CH3_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC0_DMA_CH3_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC0_DMA_CH3_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH3_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH3_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH3_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH3_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC0_DMA_CH3_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH4_STATUS  ===================================================== */
+ #define R_GMAC0_DMA_CH4_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH4_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH4_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH4_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC0_DMA_CH4_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC0_DMA_CH4_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH4_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC0_DMA_CH4_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH4_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC0_DMA_CH4_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC0_DMA_CH4_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC0_DMA_CH4_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC0_DMA_CH4_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC0_DMA_CH4_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH4_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH4_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH4_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH4_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC0_DMA_CH4_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH5_STATUS  ===================================================== */
+ #define R_GMAC0_DMA_CH5_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH5_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH5_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH5_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC0_DMA_CH5_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC0_DMA_CH5_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH5_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC0_DMA_CH5_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH5_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC0_DMA_CH5_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC0_DMA_CH5_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC0_DMA_CH5_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC0_DMA_CH5_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC0_DMA_CH5_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH5_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH5_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH5_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH5_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC0_DMA_CH5_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH6_STATUS  ===================================================== */
+ #define R_GMAC0_DMA_CH6_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH6_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH6_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH6_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC0_DMA_CH6_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC0_DMA_CH6_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH6_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC0_DMA_CH6_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH6_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC0_DMA_CH6_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC0_DMA_CH6_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC0_DMA_CH6_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC0_DMA_CH6_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC0_DMA_CH6_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH6_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH6_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH6_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH6_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC0_DMA_CH6_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH7_STATUS  ===================================================== */
+ #define R_GMAC0_DMA_CH7_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC0_DMA_CH7_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH7_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC0_DMA_CH7_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC0_DMA_CH7_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC0_DMA_CH7_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC0_DMA_CH7_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC0_DMA_CH7_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC0_DMA_CH7_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC0_DMA_CH7_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC0_DMA_CH7_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC0_DMA_CH7_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC0_DMA_CH7_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC0_DMA_CH7_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC0_DMA_CH7_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC0_DMA_CH7_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC0_DMA_CH7_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC0_DMA_CH7_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC0_DMA_CH7_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ================================================  DMA_CH0_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC0_DMA_CH0_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH0_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC0_DMA_CH0_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH0_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH1_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC0_DMA_CH1_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH1_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC0_DMA_CH1_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH1_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH2_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC0_DMA_CH2_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH2_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC0_DMA_CH2_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH2_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH3_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC0_DMA_CH3_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH3_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC0_DMA_CH3_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH3_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH4_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC0_DMA_CH4_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH4_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC0_DMA_CH4_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH4_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH5_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC0_DMA_CH5_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH5_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC0_DMA_CH5_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH5_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH6_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC0_DMA_CH6_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH6_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC0_DMA_CH6_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH6_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH7_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC0_DMA_CH7_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC0_DMA_CH7_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC0_DMA_CH7_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC0_DMA_CH7_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ETHSS                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PRCMD  ========================================================= */
+/* ========================================================  MODCTRL  ======================================================== */
+ #define R_ETHSS_MODCTRL_SW_MODE_Pos           (0UL)       /*!< SW_MODE (Bit 0)                                       */
+ #define R_ETHSS_MODCTRL_SW_MODE_Msk           (0x7UL)     /*!< SW_MODE (Bitfield-Mask: 0x07)                         */
+/* =======================================================  PTPMCTRL  ======================================================== */
+ #define R_ETHSS_PTPMCTRL_PTP_MODE0_Pos        (0UL)       /*!< PTP_MODE0 (Bit 0)                                     */
+ #define R_ETHSS_PTPMCTRL_PTP_MODE0_Msk        (0x1UL)     /*!< PTP_MODE0 (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSS_PTPMCTRL_PTP_MODE1_Pos        (1UL)       /*!< PTP_MODE1 (Bit 1)                                     */
+ #define R_ETHSS_PTPMCTRL_PTP_MODE1_Msk        (0x2UL)     /*!< PTP_MODE1 (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSS_PTPMCTRL_PTP_MODE2_Pos        (2UL)       /*!< PTP_MODE2 (Bit 2)                                     */
+ #define R_ETHSS_PTPMCTRL_PTP_MODE2_Msk        (0x4UL)     /*!< PTP_MODE2 (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Pos     (16UL)      /*!< PTP_PLS_RSTn (Bit 16)                                 */
+ #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Msk     (0x10000UL) /*!< PTP_PLS_RSTn (Bitfield-Mask: 0x01)                    */
+/* ========================================================  PHYLNK  ========================================================= */
+ #define R_ETHSS_PHYLNK_SWLINK_Pos             (0UL)       /*!< SWLINK (Bit 0)                                        */
+ #define R_ETHSS_PHYLNK_SWLINK_Msk             (0x7UL)     /*!< SWLINK (Bitfield-Mask: 0x07)                          */
+ #define R_ETHSS_PHYLNK_CATLNK_Pos             (4UL)       /*!< CATLNK (Bit 4)                                        */
+ #define R_ETHSS_PHYLNK_CATLNK_Msk             (0x70UL)    /*!< CATLNK (Bitfield-Mask: 0x07)                          */
+/* =======================================================  CONVCTRL  ======================================================== */
+ #define R_ETHSS_CONVCTRL_CONV_MODE_Pos        (0UL)       /*!< CONV_MODE (Bit 0)                                     */
+ #define R_ETHSS_CONVCTRL_CONV_MODE_Msk        (0x1fUL)    /*!< CONV_MODE (Bitfield-Mask: 0x1f)                       */
+ #define R_ETHSS_CONVCTRL_FULLD_Pos            (8UL)       /*!< FULLD (Bit 8)                                         */
+ #define R_ETHSS_CONVCTRL_FULLD_Msk            (0x100UL)   /*!< FULLD (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Pos    (9UL)       /*!< RMII_RX_ER_EN (Bit 9)                                 */
+ #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Msk    (0x200UL)   /*!< RMII_RX_ER_EN (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Pos    (10UL)      /*!< RMII_CRS_MODE (Bit 10)                                */
+ #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Msk    (0x400UL)   /*!< RMII_CRS_MODE (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSS_CONVCTRL_RGMII_LINK_Pos       (12UL)      /*!< RGMII_LINK (Bit 12)                                   */
+ #define R_ETHSS_CONVCTRL_RGMII_LINK_Msk       (0x1000UL)  /*!< RGMII_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Pos     (13UL)      /*!< RGMII_DUPLEX (Bit 13)                                 */
+ #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Msk     (0x2000UL)  /*!< RGMII_DUPLEX (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSS_CONVCTRL_RGMII_SPEED_Pos      (14UL)      /*!< RGMII_SPEED (Bit 14)                                  */
+ #define R_ETHSS_CONVCTRL_RGMII_SPEED_Msk      (0xc000UL)  /*!< RGMII_SPEED (Bitfield-Mask: 0x03)                     */
+/* ========================================================  CONVRST  ======================================================== */
+ #define R_ETHSS_CONVRST_PHYIR_Pos             (0UL)       /*!< PHYIR (Bit 0)                                         */
+ #define R_ETHSS_CONVRST_PHYIR_Msk             (0xfUL)     /*!< PHYIR (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  SWCTRL  ========================================================= */
+ #define R_ETHSS_SWCTRL_SET10_Pos              (0UL)       /*!< SET10 (Bit 0)                                         */
+ #define R_ETHSS_SWCTRL_SET10_Msk              (0x7UL)     /*!< SET10 (Bitfield-Mask: 0x07)                           */
+ #define R_ETHSS_SWCTRL_SET1000_Pos            (4UL)       /*!< SET1000 (Bit 4)                                       */
+ #define R_ETHSS_SWCTRL_SET1000_Msk            (0x70UL)    /*!< SET1000 (Bitfield-Mask: 0x07)                         */
+ #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Pos       (16UL)      /*!< STRAP_SX_ENB (Bit 16)                                 */
+ #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Msk       (0x10000UL) /*!< STRAP_SX_ENB (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Pos      (17UL)      /*!< STRAP_HUB_ENB (Bit 17)                                */
+ #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Msk      (0x20000UL) /*!< STRAP_HUB_ENB (Bitfield-Mask: 0x01)                   */
+/* ========================================================  SWDUPC  ========================================================= */
+ #define R_ETHSS_SWDUPC_PHY_DUPLEX_Pos         (0UL)       /*!< PHY_DUPLEX (Bit 0)                                    */
+ #define R_ETHSS_SWDUPC_PHY_DUPLEX_Msk         (0x7UL)     /*!< PHY_DUPLEX (Bitfield-Mask: 0x07)                      */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ESC_INI                                         ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  ECATOFFADR  ======================================================= */
+ #define R_ESC_INI_ECATOFFADR_OADD_Pos           (0UL)    /*!< OADD (Bit 0)                                          */
+ #define R_ESC_INI_ECATOFFADR_OADD_Msk           (0x1fUL) /*!< OADD (Bitfield-Mask: 0x1f)                            */
+/* =======================================================  ECATOPMOD  ======================================================= */
+ #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Pos      (0UL)    /*!< EEPROMSIZE (Bit 0)                                    */
+ #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Msk      (0x1UL)  /*!< EEPROMSIZE (Bitfield-Mask: 0x01)                      */
+/* =======================================================  ECATDBGC  ======================================================== */
+ #define R_ESC_INI_ECATDBGC_TXSFT0_Pos           (0UL)    /*!< TXSFT0 (Bit 0)                                        */
+ #define R_ESC_INI_ECATDBGC_TXSFT0_Msk           (0x3UL)  /*!< TXSFT0 (Bitfield-Mask: 0x03)                          */
+ #define R_ESC_INI_ECATDBGC_TXSFT1_Pos           (2UL)    /*!< TXSFT1 (Bit 2)                                        */
+ #define R_ESC_INI_ECATDBGC_TXSFT1_Msk           (0xcUL)  /*!< TXSFT1 (Bitfield-Mask: 0x03)                          */
+ #define R_ESC_INI_ECATDBGC_TXSFT2_Pos           (4UL)    /*!< TXSFT2 (Bit 4)                                        */
+ #define R_ESC_INI_ECATDBGC_TXSFT2_Msk           (0x30UL) /*!< TXSFT2 (Bitfield-Mask: 0x03)                          */
+/* ======================================================  ECATTRGSEL  ======================================================= */
+ #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Pos        (0UL)    /*!< TRGSEL0 (Bit 0)                                       */
+ #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Msk        (0x1UL)  /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Pos        (1UL)    /*!< TRGSEL1 (Bit 1)                                       */
+ #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Msk        (0x2UL)  /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  ECATRESOUT  ======================================================= */
+ #define R_ESC_INI_ECATRESOUT_FORCE_RESET_Pos    (0UL)    /*!< FORCE_RESET (Bit 0)                                   */
+ #define R_ESC_INI_ECATRESOUT_FORCE_RESET_Msk    (0x1UL)  /*!< FORCE_RESET (Bitfield-Mask: 0x01)                     */
+ #define R_ESC_INI_ECATRESOUT_RESOUT_EN_Pos      (1UL)    /*!< RESOUT_EN (Bit 1)                                     */
+ #define R_ESC_INI_ECATRESOUT_RESOUT_EN_Msk      (0x2UL)  /*!< RESOUT_EN (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                        R_ETHSW_PTP                                        ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  SWPTPOUTSEL  ====================================================== */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Pos     (0UL)    /*!< IOSEL0 (Bit 0)                                        */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Msk     (0x1UL)  /*!< IOSEL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Pos     (1UL)    /*!< IOSEL1 (Bit 1)                                        */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Msk     (0x2UL)  /*!< IOSEL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Pos     (2UL)    /*!< IOSEL2 (Bit 2)                                        */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Msk     (0x4UL)  /*!< IOSEL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Pos     (3UL)    /*!< IOSEL3 (Bit 3)                                        */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Msk     (0x8UL)  /*!< IOSEL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Pos    (4UL)    /*!< EVTSEL0 (Bit 4)                                       */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Msk    (0x10UL) /*!< EVTSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Pos    (5UL)    /*!< EVTSEL1 (Bit 5)                                       */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Msk    (0x20UL) /*!< EVTSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Pos    (6UL)    /*!< EVTSEL2 (Bit 6)                                       */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Msk    (0x40UL) /*!< EVTSEL2 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Pos    (7UL)    /*!< EVTSEL3 (Bit 7)                                       */
+ #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Msk    (0x80UL) /*!< EVTSEL3 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GMACC                                          ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  GMACTRGSEL  ======================================================= */
+ #define R_GMACC_GMACTRGSEL_G0TRGSEL0_Pos    (0UL)    /*!< G0TRGSEL0 (Bit 0)                                     */
+ #define R_GMACC_GMACTRGSEL_G0TRGSEL0_Msk    (0x1UL)  /*!< G0TRGSEL0 (Bitfield-Mask: 0x01)                       */
+ #define R_GMACC_GMACTRGSEL_G0TRGSEL1_Pos    (1UL)    /*!< G0TRGSEL1 (Bit 1)                                     */
+ #define R_GMACC_GMACTRGSEL_G0TRGSEL1_Msk    (0x2UL)  /*!< G0TRGSEL1 (Bitfield-Mask: 0x01)                       */
+ #define R_GMACC_GMACTRGSEL_G1TRGSEL0_Pos    (2UL)    /*!< G1TRGSEL0 (Bit 2)                                     */
+ #define R_GMACC_GMACTRGSEL_G1TRGSEL0_Msk    (0x4UL)  /*!< G1TRGSEL0 (Bitfield-Mask: 0x01)                       */
+ #define R_GMACC_GMACTRGSEL_G1TRGSEL1_Pos    (3UL)    /*!< G1TRGSEL1 (Bit 3)                                     */
+ #define R_GMACC_GMACTRGSEL_G1TRGSEL1_Msk    (0x8UL)  /*!< G1TRGSEL1 (Bitfield-Mask: 0x01)                       */
+ #define R_GMACC_GMACTRGSEL_G2TRGSEL0_Pos    (4UL)    /*!< G2TRGSEL0 (Bit 4)                                     */
+ #define R_GMACC_GMACTRGSEL_G2TRGSEL0_Msk    (0x10UL) /*!< G2TRGSEL0 (Bitfield-Mask: 0x01)                       */
+ #define R_GMACC_GMACTRGSEL_G2TRGSEL1_Pos    (5UL)    /*!< G2TRGSEL1 (Bit 5)                                     */
+ #define R_GMACC_GMACTRGSEL_G2TRGSEL1_Msk    (0x20UL) /*!< G2TRGSEL1 (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ETHSW                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  REVISION  ======================================================== */
+ #define R_ETHSW_REVISION_REV_Pos                                         (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REVISION_REV_Msk                                         (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SCRATCH  ======================================================== */
+ #define R_ETHSW_SCRATCH_SCRATCH_Pos                                      (0UL)          /*!< SCRATCH (Bit 0)                                       */
+ #define R_ETHSW_SCRATCH_SCRATCH_Msk                                      (0xffffffffUL) /*!< SCRATCH (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  PORT_ENA  ======================================================== */
+ #define R_ETHSW_PORT_ENA_TXENA_Pos                                       (0UL)          /*!< TXENA (Bit 0)                                         */
+ #define R_ETHSW_PORT_ENA_TXENA_Msk                                       (0xfUL)        /*!< TXENA (Bitfield-Mask: 0x0f)                           */
+ #define R_ETHSW_PORT_ENA_RXENA_Pos                                       (16UL)         /*!< RXENA (Bit 16)                                        */
+ #define R_ETHSW_PORT_ENA_RXENA_Msk                                       (0xf0000UL)    /*!< RXENA (Bitfield-Mask: 0x0f)                           */
+/* ==================================================  UCAST_DEFAULT_MASK0  ================================================== */
+ #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Pos                          (0UL)          /*!< UCASTDM (Bit 0)                                       */
+ #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Msk                          (0xfUL)        /*!< UCASTDM (Bitfield-Mask: 0x0f)                         */
+/* ======================================================  VLAN_VERIFY  ====================================================== */
+ #define R_ETHSW_VLAN_VERIFY_VLANVERI_Pos                                 (0UL)          /*!< VLANVERI (Bit 0)                                      */
+ #define R_ETHSW_VLAN_VERIFY_VLANVERI_Msk                                 (0xfUL)        /*!< VLANVERI (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_VLAN_VERIFY_VLANDISC_Pos                                 (16UL)         /*!< VLANDISC (Bit 16)                                     */
+ #define R_ETHSW_VLAN_VERIFY_VLANDISC_Msk                                 (0xf0000UL)    /*!< VLANDISC (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  BCAST_DEFAULT_MASK0  ================================================== */
+ #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Pos                          (0UL)          /*!< BCASTDM (Bit 0)                                       */
+ #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Msk                          (0xfUL)        /*!< BCASTDM (Bitfield-Mask: 0x0f)                         */
+/* ==================================================  MCAST_DEFAULT_MASK0  ================================================== */
+ #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Pos                          (0UL)          /*!< MCASTDM (Bit 0)                                       */
+ #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Msk                          (0xfUL)        /*!< MCASTDM (Bitfield-Mask: 0x0f)                         */
+/* ===================================================  INPUT_LEARN_BLOCK  =================================================== */
+ #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Pos                            (0UL)          /*!< BLOCKEN (Bit 0)                                       */
+ #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Msk                            (0xfUL)        /*!< BLOCKEN (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Pos                           (16UL)         /*!< LEARNDIS (Bit 16)                                     */
+ #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Msk                           (0xf0000UL)    /*!< LEARNDIS (Bitfield-Mask: 0x0f)                        */
+/* ======================================================  MGMT_CONFIG  ====================================================== */
+ #define R_ETHSW_MGMT_CONFIG_PORT_Pos                                     (0UL)          /*!< PORT (Bit 0)                                          */
+ #define R_ETHSW_MGMT_CONFIG_PORT_Msk                                     (0xfUL)        /*!< PORT (Bitfield-Mask: 0x0f)                            */
+ #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Pos                                (5UL)          /*!< MSG_TRANS (Bit 5)                                     */
+ #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Msk                                (0x20UL)       /*!< MSG_TRANS (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MGMT_CONFIG_ENABLE_Pos                                   (6UL)          /*!< ENABLE (Bit 6)                                        */
+ #define R_ETHSW_MGMT_CONFIG_ENABLE_Msk                                   (0x40UL)       /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MGMT_CONFIG_DISCARD_Pos                                  (7UL)          /*!< DISCARD (Bit 7)                                       */
+ #define R_ETHSW_MGMT_CONFIG_DISCARD_Msk                                  (0x80UL)       /*!< DISCARD (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Pos                                  (8UL)          /*!< MGMT_EN (Bit 8)                                       */
+ #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Msk                                  (0x100UL)      /*!< MGMT_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Pos                                (9UL)          /*!< MGMT_DISC (Bit 9)                                     */
+ #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Msk                                (0x200UL)      /*!< MGMT_DISC (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MGMT_CONFIG_PRIORITY_Pos                                 (13UL)         /*!< PRIORITY (Bit 13)                                     */
+ #define R_ETHSW_MGMT_CONFIG_PRIORITY_Msk                                 (0xe000UL)     /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_MGMT_CONFIG_PORTMASK_Pos                                 (16UL)         /*!< PORTMASK (Bit 16)                                     */
+ #define R_ETHSW_MGMT_CONFIG_PORTMASK_Msk                                 (0xf0000UL)    /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
+/* ======================================================  MODE_CONFIG  ====================================================== */
+ #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Pos                              (8UL)          /*!< CUT_THRU_EN (Bit 8)                                   */
+ #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Msk                              (0xf00UL)      /*!< CUT_THRU_EN (Bitfield-Mask: 0x0f)                     */
+ #define R_ETHSW_MODE_CONFIG_STATSRESET_Pos                               (31UL)         /*!< STATSRESET (Bit 31)                                   */
+ #define R_ETHSW_MODE_CONFIG_STATSRESET_Msk                               (0x80000000UL) /*!< STATSRESET (Bitfield-Mask: 0x01)                      */
+/* =====================================================  VLAN_IN_MODE  ====================================================== */
+ #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Pos                              (0UL)          /*!< P0VLANINMD (Bit 0)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Msk                              (0x3UL)        /*!< P0VLANINMD (Bitfield-Mask: 0x03)                      */
+ #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Pos                              (2UL)          /*!< P1VLANINMD (Bit 2)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Msk                              (0xcUL)        /*!< P1VLANINMD (Bitfield-Mask: 0x03)                      */
+ #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Pos                              (4UL)          /*!< P2VLANINMD (Bit 4)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Msk                              (0x30UL)       /*!< P2VLANINMD (Bitfield-Mask: 0x03)                      */
+ #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Pos                              (6UL)          /*!< P3VLANINMD (Bit 6)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Msk                              (0xc0UL)       /*!< P3VLANINMD (Bitfield-Mask: 0x03)                      */
+/* =====================================================  VLAN_OUT_MODE  ===================================================== */
+ #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Pos                            (0UL)          /*!< P0VLANOUTMD (Bit 0)                                   */
+ #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Msk                            (0x3UL)        /*!< P0VLANOUTMD (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Pos                            (2UL)          /*!< P1VLANOUTMD (Bit 2)                                   */
+ #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Msk                            (0xcUL)        /*!< P1VLANOUTMD (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Pos                            (4UL)          /*!< P2VLANOUTMD (Bit 4)                                   */
+ #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Msk                            (0x30UL)       /*!< P2VLANOUTMD (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Pos                            (6UL)          /*!< P3VLANOUTMD (Bit 6)                                   */
+ #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Msk                            (0xc0UL)       /*!< P3VLANOUTMD (Bitfield-Mask: 0x03)                     */
+/* ===================================================  VLAN_IN_MODE_ENA  ==================================================== */
+ #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Pos                          (0UL)          /*!< VLANINMDEN (Bit 0)                                    */
+ #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Msk                          (0xfUL)        /*!< VLANINMDEN (Bitfield-Mask: 0x0f)                      */
+/* ======================================================  VLAN_TAG_ID  ====================================================== */
+ #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Pos                                (0UL)          /*!< VLANTAGID (Bit 0)                                     */
+ #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Msk                                (0xffffUL)     /*!< VLANTAGID (Bitfield-Mask: 0xffff)                     */
+/* ===================================================  BCAST_STORM_LIMIT  =================================================== */
+ #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Pos                              (0UL)          /*!< TMOUT (Bit 0)                                         */
+ #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Msk                              (0xffffUL)     /*!< TMOUT (Bitfield-Mask: 0xffff)                         */
+ #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Pos                         (16UL)         /*!< BCASTLIMIT (Bit 16)                                   */
+ #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Msk                         (0xffff0000UL) /*!< BCASTLIMIT (Bitfield-Mask: 0xffff)                    */
+/* ===================================================  MCAST_STORM_LIMIT  =================================================== */
+ #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Pos                         (16UL)         /*!< MCASTLIMIT (Bit 16)                                   */
+ #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Msk                         (0xffff0000UL) /*!< MCASTLIMIT (Bitfield-Mask: 0xffff)                    */
+/* ====================================================  MIRROR_CONTROL  ===================================================== */
+ #define R_ETHSW_MIRROR_CONTROL_PORT_Pos                                  (0UL)          /*!< PORT (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_CONTROL_PORT_Msk                                  (0x3UL)        /*!< PORT (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Pos                             (4UL)          /*!< MIRROR_EN (Bit 4)                                     */
+ #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Msk                             (0x10UL)       /*!< MIRROR_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Pos                            (5UL)          /*!< ING_MAP_EN (Bit 5)                                    */
+ #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Msk                            (0x20UL)       /*!< ING_MAP_EN (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Pos                             (6UL)          /*!< EG_MAP_EN (Bit 6)                                     */
+ #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Msk                             (0x40UL)       /*!< EG_MAP_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Pos                          (7UL)          /*!< ING_SA_MATCH (Bit 7)                                  */
+ #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Msk                          (0x80UL)       /*!< ING_SA_MATCH (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Pos                          (8UL)          /*!< ING_DA_MATCH (Bit 8)                                  */
+ #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Msk                          (0x100UL)      /*!< ING_DA_MATCH (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Pos                           (9UL)          /*!< EG_SA_MATCH (Bit 9)                                   */
+ #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Msk                           (0x200UL)      /*!< EG_SA_MATCH (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Pos                           (10UL)         /*!< EG_DA_MATCH (Bit 10)                                  */
+ #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Msk                           (0x400UL)      /*!< EG_DA_MATCH (Bitfield-Mask: 0x01)                     */
+/* =====================================================  MIRROR_EG_MAP  ===================================================== */
+ #define R_ETHSW_MIRROR_EG_MAP_EMAP_Pos                                   (0UL)          /*!< EMAP (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_EG_MAP_EMAP_Msk                                   (0xfUL)        /*!< EMAP (Bitfield-Mask: 0x0f)                            */
+/* ====================================================  MIRROR_ING_MAP  ===================================================== */
+ #define R_ETHSW_MIRROR_ING_MAP_IMAP_Pos                                  (0UL)          /*!< IMAP (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ING_MAP_IMAP_Msk                                  (0xfUL)        /*!< IMAP (Bitfield-Mask: 0x0f)                            */
+/* =====================================================  MIRROR_ISRC_0  ===================================================== */
+ #define R_ETHSW_MIRROR_ISRC_0_ISRC_Pos                                   (0UL)          /*!< ISRC (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ISRC_0_ISRC_Msk                                   (0xffffffffUL) /*!< ISRC (Bitfield-Mask: 0xffffffff)                      */
+/* =====================================================  MIRROR_ISRC_1  ===================================================== */
+ #define R_ETHSW_MIRROR_ISRC_1_ISRC_Pos                                   (0UL)          /*!< ISRC (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ISRC_1_ISRC_Msk                                   (0xffffUL)     /*!< ISRC (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  MIRROR_IDST_0  ===================================================== */
+ #define R_ETHSW_MIRROR_IDST_0_IDST_Pos                                   (0UL)          /*!< IDST (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_IDST_0_IDST_Msk                                   (0xffffffffUL) /*!< IDST (Bitfield-Mask: 0xffffffff)                      */
+/* =====================================================  MIRROR_IDST_1  ===================================================== */
+ #define R_ETHSW_MIRROR_IDST_1_IDST_Pos                                   (0UL)          /*!< IDST (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_IDST_1_IDST_Msk                                   (0xffffUL)     /*!< IDST (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  MIRROR_ESRC_0  ===================================================== */
+ #define R_ETHSW_MIRROR_ESRC_0_ESRC_Pos                                   (0UL)          /*!< ESRC (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ESRC_0_ESRC_Msk                                   (0xffffffffUL) /*!< ESRC (Bitfield-Mask: 0xffffffff)                      */
+/* =====================================================  MIRROR_ESRC_1  ===================================================== */
+ #define R_ETHSW_MIRROR_ESRC_1_ESRC_Pos                                   (0UL)          /*!< ESRC (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_ESRC_1_ESRC_Msk                                   (0xffffUL)     /*!< ESRC (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  MIRROR_EDST_0  ===================================================== */
+ #define R_ETHSW_MIRROR_EDST_0_EDST_Pos                                   (0UL)          /*!< EDST (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_EDST_0_EDST_Msk                                   (0xffffffffUL) /*!< EDST (Bitfield-Mask: 0xffffffff)                      */
+/* =====================================================  MIRROR_EDST_1  ===================================================== */
+ #define R_ETHSW_MIRROR_EDST_1_EDST_Pos                                   (0UL)          /*!< EDST (Bit 0)                                          */
+ #define R_ETHSW_MIRROR_EDST_1_EDST_Msk                                   (0xffffUL)     /*!< EDST (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  MIRROR_CNT  ======================================================= */
+ #define R_ETHSW_MIRROR_CNT_CNT_Pos                                       (0UL)          /*!< CNT (Bit 0)                                           */
+ #define R_ETHSW_MIRROR_CNT_CNT_Msk                                       (0xffUL)       /*!< CNT (Bitfield-Mask: 0xff)                             */
+/* ==================================================  UCAST_DEFAULT_MASK1  ================================================== */
+ #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Pos                         (0UL)          /*!< UCASTDM1 (Bit 0)                                      */
+ #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Msk                         (0xfUL)        /*!< UCASTDM1 (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  BCAST_DEFAULT_MASK1  ================================================== */
+ #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Pos                         (0UL)          /*!< BCASTDM1 (Bit 0)                                      */
+ #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Msk                         (0xfUL)        /*!< BCASTDM1 (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  MCAST_DEFAULT_MASK1  ================================================== */
+ #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Pos                         (0UL)          /*!< MCASTDM1 (Bit 0)                                      */
+ #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Msk                         (0xfUL)        /*!< MCASTDM1 (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  PORT_XCAST_MASK_SEL  ================================================== */
+ #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Pos                             (0UL)          /*!< MSEL (Bit 0)                                          */
+ #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Msk                             (0xfUL)        /*!< MSEL (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  QMGR_ST_MINCELLS  ==================================================== */
+ #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Pos                          (0UL)          /*!< STMINCELLS (Bit 0)                                    */
+ #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Msk                          (0x7ffUL)      /*!< STMINCELLS (Bitfield-Mask: 0x7ff)                     */
+/* =====================================================  QMGR_RED_MIN4  ===================================================== */
+ #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Pos                          (0UL)          /*!< CFGRED_MINTH4 (Bit 0)                                 */
+ #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Msk                          (0xffffffffUL) /*!< CFGRED_MINTH4 (Bitfield-Mask: 0xffffffff)             */
+/* =====================================================  QMGR_RED_MAX4  ===================================================== */
+ #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Pos                          (0UL)          /*!< CFGRED_MAXTH4 (Bit 0)                                 */
+ #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Msk                          (0xffffffffUL) /*!< CFGRED_MAXTH4 (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  QMGR_RED_CONFIG  ==================================================== */
+ #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Pos                         (0UL)          /*!< QUEUE_RED_EN (Bit 0)                                  */
+ #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Msk                         (0xfUL)        /*!< QUEUE_RED_EN (Bitfield-Mask: 0x0f)                    */
+ #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Pos                         (8UL)          /*!< GACTIVITY_EN (Bit 8)                                  */
+ #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Msk                         (0x100UL)      /*!< GACTIVITY_EN (Bitfield-Mask: 0x01)                    */
+/* ======================================================  IMC_STATUS  ======================================================= */
+ #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Pos                           (0UL)          /*!< CELLS_AVAILABLE (Bit 0)                               */
+ #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Msk                           (0xffffffUL)   /*!< CELLS_AVAILABLE (Bitfield-Mask: 0xffffff)             */
+ #define R_ETHSW_IMC_STATUS_CF_ERR_Pos                                    (24UL)         /*!< CF_ERR (Bit 24)                                       */
+ #define R_ETHSW_IMC_STATUS_CF_ERR_Msk                                    (0x1000000UL)  /*!< CF_ERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_IMC_STATUS_DE_ERR_Pos                                    (25UL)         /*!< DE_ERR (Bit 25)                                       */
+ #define R_ETHSW_IMC_STATUS_DE_ERR_Msk                                    (0x2000000UL)  /*!< DE_ERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_IMC_STATUS_DE_INIT_Pos                                   (26UL)         /*!< DE_INIT (Bit 26)                                      */
+ #define R_ETHSW_IMC_STATUS_DE_INIT_Msk                                   (0x4000000UL)  /*!< DE_INIT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_IMC_STATUS_MEM_FULL_Pos                                  (27UL)         /*!< MEM_FULL (Bit 27)                                     */
+ #define R_ETHSW_IMC_STATUS_MEM_FULL_Msk                                  (0x8000000UL)  /*!< MEM_FULL (Bitfield-Mask: 0x01)                        */
+/* =====================================================  IMC_ERR_FULL  ====================================================== */
+ #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Pos                            (0UL)          /*!< IPC_ERR_FULL (Bit 0)                                  */
+ #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Msk                            (0xfUL)        /*!< IPC_ERR_FULL (Bitfield-Mask: 0x0f)                    */
+ #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Pos                           (16UL)         /*!< IPC_ERR_TRUNC (Bit 16)                                */
+ #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Msk                           (0xf0000UL)    /*!< IPC_ERR_TRUNC (Bitfield-Mask: 0x0f)                   */
+/* =====================================================  IMC_ERR_IFACE  ===================================================== */
+ #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Pos                          (0UL)          /*!< IPC_ERR_IFACE (Bit 0)                                 */
+ #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Msk                          (0xfUL)        /*!< IPC_ERR_IFACE (Bitfield-Mask: 0x0f)                   */
+ #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Pos                               (16UL)         /*!< WBUF_OVF (Bit 16)                                     */
+ #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Msk                               (0xf0000UL)    /*!< WBUF_OVF (Bitfield-Mask: 0x0f)                        */
+/* ====================================================  IMC_ERR_QOFLOW  ===================================================== */
+ #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Pos                                (0UL)          /*!< OP_ERR (Bit 0)                                        */
+ #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Msk                                (0xfUL)        /*!< OP_ERR (Bitfield-Mask: 0x0f)                          */
+/* ======================================================  IMC_CONFIG  ======================================================= */
+ #define R_ETHSW_IMC_CONFIG_WFQ_EN_Pos                                    (0UL)          /*!< WFQ_EN (Bit 0)                                        */
+ #define R_ETHSW_IMC_CONFIG_WFQ_EN_Msk                                    (0x1UL)        /*!< WFQ_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_IMC_CONFIG_RSV_ENA_Pos                                   (1UL)          /*!< RSV_ENA (Bit 1)                                       */
+ #define R_ETHSW_IMC_CONFIG_RSV_ENA_Msk                                   (0x2UL)        /*!< RSV_ENA (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Pos                           (2UL)          /*!< SPEED_HIPRI_THR (Bit 2)                               */
+ #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Msk                           (0x1cUL)       /*!< SPEED_HIPRI_THR (Bitfield-Mask: 0x07)                 */
+ #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Pos                             (5UL)          /*!< CTFL_EMPTY_MD (Bit 5)                                 */
+ #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Msk                             (0x20UL)       /*!< CTFL_EMPTY_MD (Bitfield-Mask: 0x01)                   */
+/* =====================================================  IMC_ERR_ALLOC  ===================================================== */
+ #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Pos                              (0UL)          /*!< DISC_FULL (Bit 0)                                     */
+ #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Msk                              (0xfUL)        /*!< DISC_FULL (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Pos                              (16UL)         /*!< DISC_LATE (Bit 16)                                    */
+ #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Msk                              (0xf0000UL)    /*!< DISC_LATE (Bitfield-Mask: 0x0f)                       */
+/* =======================================================  GPARSER0  ======================================================== */
+ #define R_ETHSW_GPARSER0_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER0_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER0_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER0_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER0_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER0_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER0_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER0_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER0_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER0_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER0_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER0_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER0_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER0_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER0_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER0_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER0_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER0_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER0_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER0_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER1  ======================================================== */
+ #define R_ETHSW_GPARSER1_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER1_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER1_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER1_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER1_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER1_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER1_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER1_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER1_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER1_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER1_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER1_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER1_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER1_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER1_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER1_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER1_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER1_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER1_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER1_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER2  ======================================================== */
+ #define R_ETHSW_GPARSER2_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER2_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER2_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER2_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER2_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER2_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER2_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER2_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER2_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER2_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER2_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER2_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER2_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER2_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER2_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER2_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER2_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER2_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER2_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER2_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER3  ======================================================== */
+ #define R_ETHSW_GPARSER3_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER3_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER3_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER3_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER3_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER3_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER3_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER3_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER3_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER3_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER3_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER3_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER3_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER3_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER3_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER3_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER3_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER3_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER3_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER3_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* ========================================================  GARITH0  ======================================================== */
+ #define R_ETHSW_GARITH0_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH0_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH0_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH0_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH0_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH0_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH0_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH0_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH0_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH0_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH0_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH0_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH0_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH0_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH0_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH0_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH1  ======================================================== */
+ #define R_ETHSW_GARITH1_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH1_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH1_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH1_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH1_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH1_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH1_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH1_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH1_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH1_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH1_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH1_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH1_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH1_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH1_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH1_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH2  ======================================================== */
+ #define R_ETHSW_GARITH2_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH2_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH2_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH2_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH2_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH2_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH2_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH2_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH2_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH2_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH2_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH2_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH2_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH2_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH2_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH2_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH3  ======================================================== */
+ #define R_ETHSW_GARITH3_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH3_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH3_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH3_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH3_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH3_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH3_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH3_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH3_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH3_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH3_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH3_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH3_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH3_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH3_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH3_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* =======================================================  GPARSER4  ======================================================== */
+ #define R_ETHSW_GPARSER4_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER4_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER4_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER4_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER4_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER4_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER4_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER4_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER4_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER4_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER4_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER4_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER4_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER4_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER4_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER4_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER4_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER4_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER4_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER4_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER5  ======================================================== */
+ #define R_ETHSW_GPARSER5_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER5_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER5_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER5_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER5_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER5_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER5_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER5_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER5_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER5_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER5_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER5_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER5_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER5_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER5_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER5_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER5_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER5_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER5_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER5_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER6  ======================================================== */
+ #define R_ETHSW_GPARSER6_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER6_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER6_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER6_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER6_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER6_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER6_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER6_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER6_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER6_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER6_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER6_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER6_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER6_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER6_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER6_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER6_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER6_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER6_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER6_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* =======================================================  GPARSER7  ======================================================== */
+ #define R_ETHSW_GPARSER7_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
+ #define R_ETHSW_GPARSER7_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_GPARSER7_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
+ #define R_ETHSW_GPARSER7_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_GPARSER7_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
+ #define R_ETHSW_GPARSER7_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
+ #define R_ETHSW_GPARSER7_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
+ #define R_ETHSW_GPARSER7_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_GPARSER7_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
+ #define R_ETHSW_GPARSER7_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER7_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
+ #define R_ETHSW_GPARSER7_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_GPARSER7_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
+ #define R_ETHSW_GPARSER7_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_GPARSER7_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
+ #define R_ETHSW_GPARSER7_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GPARSER7_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
+ #define R_ETHSW_GPARSER7_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
+ #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_GPARSER7_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
+ #define R_ETHSW_GPARSER7_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
+/* ========================================================  GARITH4  ======================================================== */
+ #define R_ETHSW_GARITH4_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH4_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH4_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH4_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH4_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH4_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH4_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH4_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH4_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH4_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH4_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH4_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH4_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH4_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH4_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH4_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH5  ======================================================== */
+ #define R_ETHSW_GARITH5_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH5_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH5_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH5_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH5_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH5_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH5_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH5_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH5_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH5_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH5_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH5_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH5_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH5_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH5_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH5_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH6  ======================================================== */
+ #define R_ETHSW_GARITH6_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH6_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH6_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH6_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH6_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH6_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH6_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH6_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH6_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH6_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH6_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH6_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH6_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH6_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH6_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH6_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  GARITH7  ======================================================== */
+ #define R_ETHSW_GARITH7_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
+ #define R_ETHSW_GARITH7_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
+ #define R_ETHSW_GARITH7_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
+ #define R_ETHSW_GARITH7_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_GARITH7_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
+ #define R_ETHSW_GARITH7_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH7_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
+ #define R_ETHSW_GARITH7_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH7_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
+ #define R_ETHSW_GARITH7_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH7_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
+ #define R_ETHSW_GARITH7_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_GARITH7_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
+ #define R_ETHSW_GARITH7_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_GARITH7_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
+ #define R_ETHSW_GARITH7_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
+/* =====================================================  VLAN_PRIORITY  ===================================================== */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Pos                              (0UL)          /*!< PRIORITY0 (Bit 0)                                     */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Msk                              (0x7UL)        /*!< PRIORITY0 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Pos                              (3UL)          /*!< PRIORITY1 (Bit 3)                                     */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Msk                              (0x38UL)       /*!< PRIORITY1 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Pos                              (6UL)          /*!< PRIORITY2 (Bit 6)                                     */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Msk                              (0x1c0UL)      /*!< PRIORITY2 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Pos                              (9UL)          /*!< PRIORITY3 (Bit 9)                                     */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Msk                              (0xe00UL)      /*!< PRIORITY3 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Pos                              (12UL)         /*!< PRIORITY4 (Bit 12)                                    */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Msk                              (0x7000UL)     /*!< PRIORITY4 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Pos                              (15UL)         /*!< PRIORITY5 (Bit 15)                                    */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Msk                              (0x38000UL)    /*!< PRIORITY5 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Pos                              (18UL)         /*!< PRIORITY6 (Bit 18)                                    */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Msk                              (0x1c0000UL)   /*!< PRIORITY6 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Pos                              (21UL)         /*!< PRIORITY7 (Bit 21)                                    */
+ #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Msk                              (0xe00000UL)   /*!< PRIORITY7 (Bitfield-Mask: 0x07)                       */
+/* ======================================================  IP_PRIORITY  ====================================================== */
+ #define R_ETHSW_IP_PRIORITY_ADDRESS_Pos                                  (0UL)          /*!< ADDRESS (Bit 0)                                       */
+ #define R_ETHSW_IP_PRIORITY_ADDRESS_Msk                                  (0xffUL)       /*!< ADDRESS (Bitfield-Mask: 0xff)                         */
+ #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Pos                               (8UL)          /*!< IPV6SELECT (Bit 8)                                    */
+ #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Msk                               (0x100UL)      /*!< IPV6SELECT (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_IP_PRIORITY_PRIORITY_Pos                                 (9UL)          /*!< PRIORITY (Bit 9)                                      */
+ #define R_ETHSW_IP_PRIORITY_PRIORITY_Msk                                 (0xe00UL)      /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_IP_PRIORITY_READ_Pos                                     (31UL)         /*!< READ (Bit 31)                                         */
+ #define R_ETHSW_IP_PRIORITY_READ_Msk                                     (0x80000000UL) /*!< READ (Bitfield-Mask: 0x01)                            */
+/* =====================================================  PRIORITY_CFG  ====================================================== */
+ #define R_ETHSW_PRIORITY_CFG_VLANEN_Pos                                  (0UL)          /*!< VLANEN (Bit 0)                                        */
+ #define R_ETHSW_PRIORITY_CFG_VLANEN_Msk                                  (0x1UL)        /*!< VLANEN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_PRIORITY_CFG_IPEN_Pos                                    (1UL)          /*!< IPEN (Bit 1)                                          */
+ #define R_ETHSW_PRIORITY_CFG_IPEN_Msk                                    (0x2UL)        /*!< IPEN (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_PRIORITY_CFG_MACEN_Pos                                   (2UL)          /*!< MACEN (Bit 2)                                         */
+ #define R_ETHSW_PRIORITY_CFG_MACEN_Msk                                   (0x4UL)        /*!< MACEN (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Pos                                 (3UL)          /*!< TYPE_EN (Bit 3)                                       */
+ #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Msk                                 (0x8UL)        /*!< TYPE_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Pos                              (4UL)          /*!< DEFAULTPRI (Bit 4)                                    */
+ #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Msk                              (0x70UL)       /*!< DEFAULTPRI (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_DIS_Pos                           (7UL)          /*!< PCP_REMAP_DIS (Bit 7)                                 */
+ #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_DIS_Msk                           (0x80UL)       /*!< PCP_REMAP_DIS (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_Pos                               (8UL)          /*!< PCP_REMAP (Bit 8)                                     */
+ #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_Msk                               (0xffffff00UL) /*!< PCP_REMAP (Bitfield-Mask: 0xffffff)                   */
+/* ====================================================  PRIORITY_TYPE1  ===================================================== */
+ #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Pos                               (0UL)          /*!< TYPEVAL (Bit 0)                                       */
+ #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Msk                               (0xffffUL)     /*!< TYPEVAL (Bitfield-Mask: 0xffff)                       */
+ #define R_ETHSW_PRIORITY_TYPE1_VALID_Pos                                 (16UL)         /*!< VALID (Bit 16)                                        */
+ #define R_ETHSW_PRIORITY_TYPE1_VALID_Msk                                 (0x10000UL)    /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Pos                              (17UL)         /*!< PRIORITY (Bit 17)                                     */
+ #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Msk                              (0xe0000UL)    /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+/* ====================================================  PRIORITY_TYPE2  ===================================================== */
+ #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Pos                               (0UL)          /*!< TYPEVAL (Bit 0)                                       */
+ #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Msk                               (0xffffUL)     /*!< TYPEVAL (Bitfield-Mask: 0xffff)                       */
+ #define R_ETHSW_PRIORITY_TYPE2_VALID_Pos                                 (16UL)         /*!< VALID (Bit 16)                                        */
+ #define R_ETHSW_PRIORITY_TYPE2_VALID_Msk                                 (0x10000UL)    /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Pos                              (17UL)         /*!< PRIORITY (Bit 17)                                     */
+ #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Msk                              (0xe0000UL)    /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+/* ======================================================  SRCFLT_ENA  ======================================================= */
+ #define R_ETHSW_SRCFLT_ENA_SRCENA_Pos                                    (0UL)          /*!< SRCENA (Bit 0)                                        */
+ #define R_ETHSW_SRCFLT_ENA_SRCENA_Msk                                    (0x7UL)        /*!< SRCENA (Bitfield-Mask: 0x07)                          */
+ #define R_ETHSW_SRCFLT_ENA_DSTENA_Pos                                    (16UL)         /*!< DSTENA (Bit 16)                                       */
+ #define R_ETHSW_SRCFLT_ENA_DSTENA_Msk                                    (0xf0000UL)    /*!< DSTENA (Bitfield-Mask: 0x0f)                          */
+/* ====================================================  SRCFLT_CONTROL  ===================================================== */
+ #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Pos                              (0UL)          /*!< MGMT_FWD (Bit 0)                                      */
+ #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Msk                              (0x1UL)        /*!< MGMT_FWD (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Pos                          (1UL)          /*!< WATCHDOG_ENA (Bit 1)                                  */
+ #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Msk                          (0x2UL)        /*!< WATCHDOG_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Pos                         (16UL)         /*!< WATCHDOG_TIME (Bit 16)                                */
+ #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Msk                         (0xffff0000UL) /*!< WATCHDOG_TIME (Bitfield-Mask: 0xffff)                 */
+/* ===================================================  SRCFLT_MACADDR_LO  =================================================== */
+ #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Pos                     (0UL)          /*!< SRCFLT_MACADDR (Bit 0)                                */
+ #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Msk                     (0xffffffffUL) /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  SRCFLT_MACADDR_HI  =================================================== */
+ #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Pos                     (0UL)          /*!< SRCFLT_MACADDR (Bit 0)                                */
+ #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Msk                     (0xffffUL)     /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffff)                */
+ #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Pos                               (16UL)         /*!< MASK (Bit 16)                                         */
+ #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Msk                               (0xffff0000UL) /*!< MASK (Bitfield-Mask: 0xffff)                          */
+/* ====================================================  PHY_FILTER_CFG  ===================================================== */
+ #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Pos                       (0UL)          /*!< FILTER_DURATION (Bit 0)                               */
+ #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Msk                       (0x1ffUL)      /*!< FILTER_DURATION (Bitfield-Mask: 0x1ff)                */
+ #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Pos                                (16UL)         /*!< FLT_EN (Bit 16)                                       */
+ #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Msk                                (0x70000UL)    /*!< FLT_EN (Bitfield-Mask: 0x07)                          */
+/* ====================================================  SYSTEM_TAGINFO  ===================================================== */
+ #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Pos                           (0UL)          /*!< SYSVLANINFO (Bit 0)                                   */
+ #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Msk                           (0xffffUL)     /*!< SYSVLANINFO (Bitfield-Mask: 0xffff)                   */
+/* =======================================================  AUTH_PORT  ======================================================= */
+ #define R_ETHSW_AUTH_PORT_AUTH_Pos                                       (0UL)          /*!< AUTH (Bit 0)                                          */
+ #define R_ETHSW_AUTH_PORT_AUTH_Msk                                       (0x1UL)        /*!< AUTH (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Pos                                  (1UL)          /*!< CTRL_BOTH (Bit 1)                                     */
+ #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Msk                                  (0x2UL)        /*!< CTRL_BOTH (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_AUTH_PORT_EAPOL_EN_Pos                                   (2UL)          /*!< EAPOL_EN (Bit 2)                                      */
+ #define R_ETHSW_AUTH_PORT_EAPOL_EN_Msk                                   (0x4UL)        /*!< EAPOL_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_AUTH_PORT_GUEST_EN_Pos                                   (3UL)          /*!< GUEST_EN (Bit 3)                                      */
+ #define R_ETHSW_AUTH_PORT_GUEST_EN_Msk                                   (0x8UL)        /*!< GUEST_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_AUTH_PORT_BPDU_EN_Pos                                    (4UL)          /*!< BPDU_EN (Bit 4)                                       */
+ #define R_ETHSW_AUTH_PORT_BPDU_EN_Msk                                    (0x10UL)       /*!< BPDU_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Pos                                (5UL)          /*!< EAPOL_UC_EN (Bit 5)                                   */
+ #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Msk                                (0x20UL)       /*!< EAPOL_UC_EN (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Pos                                (11UL)         /*!< ACHG_UNAUTH (Bit 11)                                  */
+ #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Msk                                (0x800UL)      /*!< ACHG_UNAUTH (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Pos                                 (12UL)         /*!< EAPOL_PNUM (Bit 12)                                   */
+ #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Msk                                 (0xf000UL)     /*!< EAPOL_PNUM (Bitfield-Mask: 0x0f)                      */
+ #define R_ETHSW_AUTH_PORT_GUEST_MASK_Pos                                 (16UL)         /*!< GUEST_MASK (Bit 16)                                   */
+ #define R_ETHSW_AUTH_PORT_GUEST_MASK_Msk                                 (0xf0000UL)    /*!< GUEST_MASK (Bitfield-Mask: 0x0f)                      */
+/* ====================================================  VLAN_RES_TABLE  ===================================================== */
+ #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos                              (0UL)          /*!< PORTMASK (Bit 0)                                      */
+ #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk                              (0xfUL)        /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_VLAN_RES_TABLE_VLANID_Pos                                (4UL)          /*!< VLANID (Bit 4)                                        */
+ #define R_ETHSW_VLAN_RES_TABLE_VLANID_Msk                                (0xfff0UL)     /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Pos                             (28UL)         /*!< RD_TAGMSK (Bit 28)                                    */
+ #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Msk                             (0x10000000UL) /*!< RD_TAGMSK (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Pos                             (29UL)         /*!< WT_TAGMSK (Bit 29)                                    */
+ #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Msk                             (0x20000000UL) /*!< WT_TAGMSK (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Pos                             (30UL)         /*!< WT_PRTMSK (Bit 30)                                    */
+ #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Msk                             (0x40000000UL) /*!< WT_PRTMSK (Bitfield-Mask: 0x01)                       */
+/* ======================================================  TOTAL_DISC  ======================================================= */
+ #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Pos                                (0UL)          /*!< TOTAL_DISC (Bit 0)                                    */
+ #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Msk                                (0xffffffffUL) /*!< TOTAL_DISC (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  TOTAL_BYT_DISC  ===================================================== */
+ #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Pos                        (0UL)          /*!< TOTAL_BYT_DISC (Bit 0)                                */
+ #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Msk                        (0xffffffffUL) /*!< TOTAL_BYT_DISC (Bitfield-Mask: 0xffffffff)            */
+/* =======================================================  TOTAL_FRM  ======================================================= */
+ #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Pos                                  (0UL)          /*!< TOTAL_FRM (Bit 0)                                     */
+ #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Msk                                  (0xffffffffUL) /*!< TOTAL_FRM (Bitfield-Mask: 0xffffffff)                 */
+/* =====================================================  TOTAL_BYT_FRM  ===================================================== */
+ #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Pos                          (0UL)          /*!< TOTAL_BYT_FRM (Bit 0)                                 */
+ #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Msk                          (0xffffffffUL) /*!< TOTAL_BYT_FRM (Bitfield-Mask: 0xffffffff)             */
+/* =====================================================  IALK_CONTROL  ====================================================== */
+ #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Pos                             (0UL)          /*!< IA_LKUP_ENA (Bit 0)                                   */
+ #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Msk                             (0xfUL)        /*!< IA_LKUP_ENA (Bitfield-Mask: 0x0f)                     */
+ #define R_ETHSW_IALK_CONTROL_CT_ENA_Pos                                  (16UL)         /*!< CT_ENA (Bit 16)                                       */
+ #define R_ETHSW_IALK_CONTROL_CT_ENA_Msk                                  (0xf0000UL)    /*!< CT_ENA (Bitfield-Mask: 0x0f)                          */
+/* =======================================================  IALK_OUI  ======================================================== */
+ #define R_ETHSW_IALK_OUI_IALK_OUI_Pos                                    (0UL)          /*!< IALK_OUI (Bit 0)                                      */
+ #define R_ETHSW_IALK_OUI_IALK_OUI_Msk                                    (0xffffffUL)   /*!< IALK_OUI (Bitfield-Mask: 0xffffff)                    */
+/* ======================================================  IALK_ID_MIN  ====================================================== */
+ #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Pos                              (0UL)          /*!< IALK_ID_MIN (Bit 0)                                   */
+ #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Msk                              (0xffffffUL)   /*!< IALK_ID_MIN (Bitfield-Mask: 0xffffff)                 */
+/* ======================================================  IALK_ID_MAX  ====================================================== */
+ #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Pos                              (0UL)          /*!< IALK_ID_MAX (Bit 0)                                   */
+ #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Msk                              (0xffffffUL)   /*!< IALK_ID_MAX (Bitfield-Mask: 0xffffff)                 */
+/* ======================================================  IALK_ID_SUB  ====================================================== */
+ #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Pos                              (0UL)          /*!< IALK_ID_SUB (Bit 0)                                   */
+ #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Msk                              (0xffffffUL)   /*!< IALK_ID_SUB (Bitfield-Mask: 0xffffff)                 */
+/* ====================================================  IALK_ID_CONFIG  ===================================================== */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Pos                        (0UL)          /*!< INVLD_ID_FLOOD (Bit 0)                                */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Msk                        (0x1UL)        /*!< INVLD_ID_FLOOD (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Pos                      (1UL)          /*!< INVLD_ID_LRN_ENA (Bit 1)                              */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Msk                      (0x2UL)        /*!< INVLD_ID_LRN_ENA (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Pos                         (4UL)          /*!< INVLD_ID_PRIO (Bit 4)                                 */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Msk                         (0x70UL)       /*!< INVLD_ID_PRIO (Bitfield-Mask: 0x07)                   */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Pos                     (7UL)          /*!< INVLD_ID_PRIO_VLD (Bit 7)                             */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Msk                     (0x80UL)       /*!< INVLD_ID_PRIO_VLD (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Pos                   (16UL)         /*!< INVLD_ID_FLOOD_MASK (Bit 16)                          */
+ #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Msk                   (0xf0000UL)    /*!< INVLD_ID_FLOOD_MASK (Bitfield-Mask: 0x0f)             */
+/* ===================================================  IALK_VLAN_CONFIG  ==================================================== */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Pos                    (0UL)          /*!< UNKWN_VLAN_FLOOD (Bit 0)                              */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Msk                    (0x1UL)        /*!< UNKWN_VLAN_FLOOD (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Pos                  (1UL)          /*!< UNKWN_VLAN_LRN_ENA (Bit 1)                            */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Msk                  (0x2UL)        /*!< UNKWN_VLAN_LRN_ENA (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Pos                     (4UL)          /*!< UNKWN_VLAN_PRIO (Bit 4)                               */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Msk                     (0x70UL)       /*!< UNKWN_VLAN_PRIO (Bitfield-Mask: 0x07)                 */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Pos                 (7UL)          /*!< UNKWN_VLAN_PRIO_VLD (Bit 7)                           */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Msk                 (0x80UL)       /*!< UNKWN_VLAN_PRIO_VLD (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Pos                       (8UL)          /*!< VLANS_ENABLED (Bit 8)                                 */
+ #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Msk                       (0x700UL)      /*!< VLANS_ENABLED (Bitfield-Mask: 0x07)                   */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Pos               (16UL)         /*!< UNKWN_VLAN_FLOOD_MASK (Bit 16)                        */
+ #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Msk               (0xf0000UL)    /*!< UNKWN_VLAN_FLOOD_MASK (Bitfield-Mask: 0x0f)        */
+/* =====================================================  IALK_TBL_ADDR  ===================================================== */
+ #define R_ETHSW_IALK_TBL_ADDR_ADDR_Pos                                   (0UL)          /*!< ADDR (Bit 0)                                          */
+ #define R_ETHSW_IALK_TBL_ADDR_ADDR_Msk                                   (0x1fffUL)     /*!< ADDR (Bitfield-Mask: 0x1fff)                          */
+ #define R_ETHSW_IALK_TBL_ADDR_AINC_Pos                                   (28UL)         /*!< AINC (Bit 28)                                         */
+ #define R_ETHSW_IALK_TBL_ADDR_AINC_Msk                                   (0xf0000000UL) /*!< AINC (Bitfield-Mask: 0x0f)                            */
+/* =====================================================  IALK_TBL_DATA  ===================================================== */
+ #define R_ETHSW_IALK_TBL_DATA_VALID_Pos                                  (0UL)          /*!< VALID (Bit 0)                                         */
+ #define R_ETHSW_IALK_TBL_DATA_VALID_Msk                                  (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Pos                               (1UL)          /*!< FWD_MASK (Bit 1)                                      */
+ #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Msk                               (0x1eUL)       /*!< FWD_MASK (Bitfield-Mask: 0x0f)                        */
+/* ======================================================  IALK_VLANID  ====================================================== */
+ #define R_ETHSW_IALK_VLANID_VLANID_Pos                                   (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_IALK_VLANID_VLANID_Msk                                   (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_IALK_VLANID_VLANID_ENA_Pos                               (12UL)         /*!< VLANID_ENA (Bit 12)                                   */
+ #define R_ETHSW_IALK_VLANID_VLANID_ENA_Msk                               (0x1000UL)     /*!< VLANID_ENA (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Pos                           (13UL)         /*!< VLANID_LRN_ENA (Bit 13)                               */
+ #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Msk                           (0x2000UL)     /*!< VLANID_LRN_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Pos                        (16UL)         /*!< VLANID_FLOOD_MASK (Bit 16)                            */
+ #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Msk                        (0xf0000UL)    /*!< VLANID_FLOOD_MASK (Bitfield-Mask: 0x0f)               */
+ #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Pos                              (28UL)         /*!< VLANID_PRIO (Bit 28)                                  */
+ #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Msk                              (0x70000000UL) /*!< VLANID_PRIO (Bitfield-Mask: 0x07)                     */
+ #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Pos                          (31UL)         /*!< VLANID_PRIO_VLD (Bit 31)                              */
+ #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Msk                          (0x80000000UL) /*!< VLANID_PRIO_VLD (Bitfield-Mask: 0x01)                 */
+/* =====================================================  IMC_QLEVEL_P  ====================================================== */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Pos                                  (0UL)          /*!< QUEUE0 (Bit 0)                                        */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Msk                                  (0xfUL)        /*!< QUEUE0 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Pos                                  (4UL)          /*!< QUEUE1 (Bit 4)                                        */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Msk                                  (0xf0UL)       /*!< QUEUE1 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Pos                                  (8UL)          /*!< QUEUE2 (Bit 8)                                        */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Msk                                  (0xf00UL)      /*!< QUEUE2 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Pos                                  (12UL)         /*!< QUEUE3 (Bit 12)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Msk                                  (0xf000UL)     /*!< QUEUE3 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Pos                                  (16UL)         /*!< QUEUE4 (Bit 16)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Msk                                  (0xf0000UL)    /*!< QUEUE4 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Pos                                  (20UL)         /*!< QUEUE5 (Bit 20)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Msk                                  (0xf00000UL)   /*!< QUEUE5 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Pos                                  (24UL)         /*!< QUEUE6 (Bit 24)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Msk                                  (0xf000000UL)  /*!< QUEUE6 (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Pos                                  (28UL)         /*!< QUEUE7 (Bit 28)                                       */
+ #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Msk                                  (0xf0000000UL) /*!< QUEUE7 (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  LK_CTRL  ======================================================== */
+ #define R_ETHSW_LK_CTRL_LKUP_EN_Pos                                      (0UL)          /*!< LKUP_EN (Bit 0)                                       */
+ #define R_ETHSW_LK_CTRL_LKUP_EN_Msk                                      (0x1UL)        /*!< LKUP_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_LK_CTRL_LEARN_EN_Pos                                     (1UL)          /*!< LEARN_EN (Bit 1)                                      */
+ #define R_ETHSW_LK_CTRL_LEARN_EN_Msk                                     (0x2UL)        /*!< LEARN_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_CTRL_AGING_EN_Pos                                     (2UL)          /*!< AGING_EN (Bit 2)                                      */
+ #define R_ETHSW_LK_CTRL_AGING_EN_Msk                                     (0x4UL)        /*!< AGING_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_CTRL_ALW_MGRT_Pos                                     (3UL)          /*!< ALW_MGRT (Bit 3)                                      */
+ #define R_ETHSW_LK_CTRL_ALW_MGRT_Msk                                     (0x8UL)        /*!< ALW_MGRT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Pos                                (4UL)          /*!< DISC_UNK_DEST (Bit 4)                                 */
+ #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Msk                                (0x10UL)       /*!< DISC_UNK_DEST (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_LK_CTRL_CLRTBL_Pos                                       (6UL)          /*!< CLRTBL (Bit 6)                                        */
+ #define R_ETHSW_LK_CTRL_CLRTBL_Msk                                       (0x40UL)       /*!< CLRTBL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_LK_CTRL_IND_VLAN_Pos                                     (7UL)          /*!< IND_VLAN (Bit 7)                                      */
+ #define R_ETHSW_LK_CTRL_IND_VLAN_Msk                                     (0x80UL)       /*!< IND_VLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Pos                                 (16UL)         /*!< DISC_UNK_SRC (Bit 16)                                 */
+ #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Msk                                 (0xf0000UL)    /*!< DISC_UNK_SRC (Bitfield-Mask: 0x0f)                    */
+/* =======================================================  LK_STATUS  ======================================================= */
+ #define R_ETHSW_LK_STATUS_AGEADDR_Pos                                    (0UL)          /*!< AGEADDR (Bit 0)                                       */
+ #define R_ETHSW_LK_STATUS_AGEADDR_Msk                                    (0xffffUL)     /*!< AGEADDR (Bitfield-Mask: 0xffff)                       */
+ #define R_ETHSW_LK_STATUS_OVRF_Pos                                       (16UL)         /*!< OVRF (Bit 16)                                         */
+ #define R_ETHSW_LK_STATUS_OVRF_Msk                                       (0x3fff0000UL) /*!< OVRF (Bitfield-Mask: 0x3fff)                          */
+ #define R_ETHSW_LK_STATUS_LRNEVNT_Pos                                    (31UL)         /*!< LRNEVNT (Bit 31)                                      */
+ #define R_ETHSW_LK_STATUS_LRNEVNT_Msk                                    (0x80000000UL) /*!< LRNEVNT (Bitfield-Mask: 0x01)                         */
+/* =====================================================  LK_ADDR_CTRL  ====================================================== */
+ #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Pos                                (0UL)          /*!< ADDR_MSK (Bit 0)                                      */
+ #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Msk                                (0xfffUL)      /*!< ADDR_MSK (Bitfield-Mask: 0xfff)                       */
+ #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Pos                             (22UL)         /*!< CLR_DYNAMIC (Bit 22)                                  */
+ #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Msk                             (0x400000UL)   /*!< CLR_DYNAMIC (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Pos                              (23UL)         /*!< CLR_STATIC (Bit 23)                                   */
+ #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Msk                              (0x800000UL)   /*!< CLR_STATIC (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Pos                              (24UL)         /*!< GETLASTNEW (Bit 24)                                   */
+ #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Msk                              (0x1000000UL)  /*!< GETLASTNEW (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_LK_ADDR_CTRL_WRITE_Pos                                   (25UL)         /*!< WRITE (Bit 25)                                        */
+ #define R_ETHSW_LK_ADDR_CTRL_WRITE_Msk                                   (0x2000000UL)  /*!< WRITE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_LK_ADDR_CTRL_READ_Pos                                    (26UL)         /*!< READ (Bit 26)                                         */
+ #define R_ETHSW_LK_ADDR_CTRL_READ_Msk                                    (0x4000000UL)  /*!< READ (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Pos                               (27UL)         /*!< WAIT_COMP (Bit 27)                                    */
+ #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Msk                               (0x8000000UL)  /*!< WAIT_COMP (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Pos                                  (28UL)         /*!< LOOKUP (Bit 28)                                       */
+ #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Msk                                  (0x10000000UL) /*!< LOOKUP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Pos                                   (29UL)         /*!< CLEAR (Bit 29)                                        */
+ #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Msk                                   (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Pos                                (30UL)         /*!< DEL_PORT (Bit 30)                                     */
+ #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Msk                                (0x40000000UL) /*!< DEL_PORT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_LK_ADDR_CTRL_BUSY_Pos                                    (31UL)         /*!< BUSY (Bit 31)                                         */
+ #define R_ETHSW_LK_ADDR_CTRL_BUSY_Msk                                    (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ======================================================  LK_DATA_LO  ======================================================= */
+ #define R_ETHSW_LK_DATA_LO_MEMDATA_Pos                                   (0UL)          /*!< MEMDATA (Bit 0)                                       */
+ #define R_ETHSW_LK_DATA_LO_MEMDATA_Msk                                   (0xffffffffUL) /*!< MEMDATA (Bitfield-Mask: 0xffffffff)                   */
+/* ======================================================  LK_DATA_HI  ======================================================= */
+ #define R_ETHSW_LK_DATA_HI_MEMDATA_Pos                                   (0UL)          /*!< MEMDATA (Bit 0)                                       */
+ #define R_ETHSW_LK_DATA_HI_MEMDATA_Msk                                   (0x1ffffffUL)  /*!< MEMDATA (Bitfield-Mask: 0x1ffffff)                    */
+/* ======================================================  LK_DATA_HI2  ====================================================== */
+ #define R_ETHSW_LK_DATA_HI2_MEMDATA_Pos                                  (8UL)          /*!< MEMDATA (Bit 8)                                       */
+ #define R_ETHSW_LK_DATA_HI2_MEMDATA_Msk                                  (0xfff00UL)    /*!< MEMDATA (Bitfield-Mask: 0xfff)                        */
+/* =====================================================  LK_LEARNCOUNT  ===================================================== */
+ #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Pos                             (0UL)          /*!< LEARNCOUNT (Bit 0)                                    */
+ #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Msk                             (0x1fffUL)     /*!< LEARNCOUNT (Bitfield-Mask: 0x1fff)                    */
+ #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Pos                               (30UL)         /*!< WRITE_MD (Bit 30)                                     */
+ #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Msk                               (0xc0000000UL) /*!< WRITE_MD (Bitfield-Mask: 0x03)                        */
+/* ======================================================  LK_AGETIME  ======================================================= */
+ #define R_ETHSW_LK_AGETIME_AGETIME_Pos                                   (0UL)          /*!< AGETIME (Bit 0)                                       */
+ #define R_ETHSW_LK_AGETIME_AGETIME_Msk                                   (0xffffffUL)   /*!< AGETIME (Bitfield-Mask: 0xffffff)                     */
+/* ====================================================  MGMT_TAG_CONFIG  ==================================================== */
+ #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Pos                               (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Msk                               (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Pos                            (1UL)          /*!< AL_FRAMES (Bit 1)                                     */
+ #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Msk                            (0x2UL)        /*!< AL_FRAMES (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Pos                             (4UL)          /*!< TYPE1_EN (Bit 4)                                      */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Msk                             (0x10UL)       /*!< TYPE1_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Pos                             (5UL)          /*!< TYPE2_EN (Bit 5)                                      */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Msk                             (0x20UL)       /*!< TYPE2_EN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Pos                             (16UL)         /*!< TAGFIELD (Bit 16)                                     */
+ #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Msk                             (0xffff0000UL) /*!< TAGFIELD (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  TSM_CONFIG  ======================================================= */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EN_Pos                                    (0UL)          /*!< IRQ_EN (Bit 0)                                        */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EN_Msk                                    (0x1UL)        /*!< IRQ_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Pos                                  (1UL)          /*!< IRQ_TEST (Bit 1)                                      */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Msk                                  (0x2UL)        /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Pos                            (2UL)          /*!< IRQ_TSFIFO_OVR (Bit 2)                                */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Msk                            (0x4UL)        /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Pos                            (4UL)          /*!< IRQ_EVT_OFFSET (Bit 4)                                */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Msk                            (0x30UL)       /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Pos                            (8UL)          /*!< IRQ_EVT_PERIOD (Bit 8)                                */
+ #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Msk                            (0x300UL)      /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Pos                            (12UL)         /*!< IRQ_ATIME_OVER (Bit 12)                               */
+ #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Msk                            (0x3000UL)     /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Pos                                 (16UL)         /*!< IRQ_TX_EN (Bit 16)                                    */
+ #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Msk                                 (0xf0000UL)    /*!< IRQ_TX_EN (Bitfield-Mask: 0x0f)                       */
+/* ===================================================  TSM_IRQ_STAT_ACK  ==================================================== */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Pos                            (0UL)          /*!< IRQ_STAT (Bit 0)                                      */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Msk                            (0x1UL)        /*!< IRQ_STAT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Pos                            (1UL)          /*!< IRQ_TEST (Bit 1)                                      */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Msk                            (0x2UL)        /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Pos                      (2UL)          /*!< IRQ_TSFIFO_OVR (Bit 2)                                */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Msk                      (0x4UL)        /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Pos                      (4UL)          /*!< IRQ_EVT_OFFSET (Bit 4)                                */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Msk                      (0x30UL)       /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Pos                      (8UL)          /*!< IRQ_EVT_PERIOD (Bit 8)                                */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Msk                      (0x300UL)      /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Pos                      (12UL)         /*!< IRQ_ATIME_OVER (Bit 12)                               */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Msk                      (0x3000UL)     /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Pos                              (16UL)         /*!< IRQ_TX (Bit 16)                                       */
+ #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Msk                              (0xf0000UL)    /*!< IRQ_TX (Bitfield-Mask: 0x0f)                          */
+/* ======================================================  PTP_DOMAIN  ======================================================= */
+ #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Pos                                   (0UL)          /*!< DOMAIN0 (Bit 0)                                       */
+ #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Msk                                   (0xffUL)       /*!< DOMAIN0 (Bitfield-Mask: 0xff)                         */
+ #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Pos                                   (8UL)          /*!< DOMAIN1 (Bit 8)                                       */
+ #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Msk                                   (0xff00UL)     /*!< DOMAIN1 (Bitfield-Mask: 0xff)                         */
+/* ====================================================  PEERDELAY_P0_T0  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P1_T0  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P2_T0  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P3_T0  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P0_T1  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P1_T1  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P2_T1  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  PEERDELAY_P3_T1  ==================================================== */
+ #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
+ #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
+/* ====================================================  TS_FIFO_STATUS  ===================================================== */
+ #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Pos                              (0UL)          /*!< FF_VALID (Bit 0)                                      */
+ #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Msk                              (0xfUL)        /*!< FF_VALID (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Pos                                (16UL)         /*!< FF_OVR (Bit 16)                                       */
+ #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Msk                                (0xf0000UL)    /*!< FF_OVR (Bitfield-Mask: 0x0f)                          */
+/* ===================================================  TS_FIFO_READ_CTRL  =================================================== */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Pos                           (0UL)          /*!< PORT_NUM (Bit 0)                                      */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Msk                           (0x3UL)        /*!< PORT_NUM (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Pos                           (4UL)          /*!< TS_VALID (Bit 4)                                      */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Msk                           (0x10UL)       /*!< TS_VALID (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Pos                             (6UL)          /*!< TS_SEL (Bit 6)                                        */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Msk                             (0x40UL)       /*!< TS_SEL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Pos                              (8UL)          /*!< TS_ID (Bit 8)                                         */
+ #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Msk                              (0x7f00UL)     /*!< TS_ID (Bitfield-Mask: 0x7f)                           */
+/* ================================================  TS_FIFO_READ_TIMESTAMP  ================================================= */
+ #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Pos                     (0UL)          /*!< TIMESTAMP (Bit 0)                                     */
+ #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Msk                     (0xffffffffUL) /*!< TIMESTAMP (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  INT_CONFIG  ======================================================= */
+ #define R_ETHSW_INT_CONFIG_IRQ_EN_Pos                                    (0UL)          /*!< IRQ_EN (Bit 0)                                        */
+ #define R_ETHSW_INT_CONFIG_IRQ_EN_Msk                                    (0x1UL)        /*!< IRQ_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_INT_CONFIG_MDIO1_Pos                                     (1UL)          /*!< MDIO1 (Bit 1)                                         */
+ #define R_ETHSW_INT_CONFIG_MDIO1_Msk                                     (0x2UL)        /*!< MDIO1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Pos                                (3UL)          /*!< LK_NEW_SRC (Bit 3)                                    */
+ #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Msk                                (0x8UL)        /*!< LK_NEW_SRC (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_INT_CONFIG_IRQ_TEST_Pos                                  (4UL)          /*!< IRQ_TEST (Bit 4)                                      */
+ #define R_ETHSW_INT_CONFIG_IRQ_TEST_Msk                                  (0x10UL)       /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_CONFIG_DLR_INT_Pos                                   (5UL)          /*!< DLR_INT (Bit 5)                                       */
+ #define R_ETHSW_INT_CONFIG_DLR_INT_Msk                                   (0x20UL)       /*!< DLR_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_PRP_INT_Pos                                   (6UL)          /*!< PRP_INT (Bit 6)                                       */
+ #define R_ETHSW_INT_CONFIG_PRP_INT_Msk                                   (0x40UL)       /*!< PRP_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_HUB_INT_Pos                                   (7UL)          /*!< HUB_INT (Bit 7)                                       */
+ #define R_ETHSW_INT_CONFIG_HUB_INT_Msk                                   (0x80UL)       /*!< HUB_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_IRQ_LINK_Pos                                  (8UL)          /*!< IRQ_LINK (Bit 8)                                      */
+ #define R_ETHSW_INT_CONFIG_IRQ_LINK_Msk                                  (0x700UL)      /*!< IRQ_LINK (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Pos                               (16UL)         /*!< IRQ_MAC_EEE (Bit 16)                                  */
+ #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Msk                               (0x70000UL)    /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07)                     */
+ #define R_ETHSW_INT_CONFIG_EFP_INT_Pos                                   (27UL)         /*!< EFP_INT (Bit 27)                                      */
+ #define R_ETHSW_INT_CONFIG_EFP_INT_Msk                                   (0x8000000UL)  /*!< EFP_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Pos                             (28UL)         /*!< SRCFLT_WD_INT (Bit 28)                                */
+ #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Msk                             (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_INT_CONFIG_TSM_INT_Pos                                   (29UL)         /*!< TSM_INT (Bit 29)                                      */
+ #define R_ETHSW_INT_CONFIG_TSM_INT_Msk                                   (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_CONFIG_TDMA_INT_Pos                                  (30UL)         /*!< TDMA_INT (Bit 30)                                     */
+ #define R_ETHSW_INT_CONFIG_TDMA_INT_Msk                                  (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_CONFIG_PATTERN_INT_Pos                               (31UL)         /*!< PATTERN_INT (Bit 31)                                  */
+ #define R_ETHSW_INT_CONFIG_PATTERN_INT_Msk                               (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01)                     */
+/* =====================================================  INT_STAT_ACK  ====================================================== */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Pos                                (0UL)          /*!< IRQ_PEND (Bit 0)                                      */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Msk                                (0x1UL)        /*!< IRQ_PEND (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_STAT_ACK_MDIO1_Pos                                   (1UL)          /*!< MDIO1 (Bit 1)                                         */
+ #define R_ETHSW_INT_STAT_ACK_MDIO1_Msk                                   (0x2UL)        /*!< MDIO1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Pos                              (3UL)          /*!< LK_NEW_SRC (Bit 3)                                    */
+ #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Msk                              (0x8UL)        /*!< LK_NEW_SRC (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Pos                                (4UL)          /*!< IRQ_TEST (Bit 4)                                      */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Msk                                (0x10UL)       /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_STAT_ACK_DLR_INT_Pos                                 (5UL)          /*!< DLR_INT (Bit 5)                                       */
+ #define R_ETHSW_INT_STAT_ACK_DLR_INT_Msk                                 (0x20UL)       /*!< DLR_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_PRP_INT_Pos                                 (6UL)          /*!< PRP_INT (Bit 6)                                       */
+ #define R_ETHSW_INT_STAT_ACK_PRP_INT_Msk                                 (0x40UL)       /*!< PRP_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_HUB_INT_Pos                                 (7UL)          /*!< HUB_INT (Bit 7)                                       */
+ #define R_ETHSW_INT_STAT_ACK_HUB_INT_Msk                                 (0x80UL)       /*!< HUB_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Pos                                (8UL)          /*!< IRQ_LINK (Bit 8)                                      */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Msk                                (0x700UL)      /*!< IRQ_LINK (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Pos                             (16UL)         /*!< IRQ_MAC_EEE (Bit 16)                                  */
+ #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Msk                             (0x70000UL)    /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07)                     */
+ #define R_ETHSW_INT_STAT_ACK_EFP_INT_Pos                                 (27UL)         /*!< EFP_INT (Bit 27)                                      */
+ #define R_ETHSW_INT_STAT_ACK_EFP_INT_Msk                                 (0x8000000UL)  /*!< EFP_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Pos                           (28UL)         /*!< SRCFLT_WD_INT (Bit 28)                                */
+ #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Msk                           (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_INT_STAT_ACK_TSM_INT_Pos                                 (29UL)         /*!< TSM_INT (Bit 29)                                      */
+ #define R_ETHSW_INT_STAT_ACK_TSM_INT_Msk                                 (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Pos                                (30UL)         /*!< TDMA_INT (Bit 30)                                     */
+ #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Msk                                (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Pos                             (31UL)         /*!< PATTERN_INT (Bit 31)                                  */
+ #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Msk                             (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  ATIME_CTRL0  ====================================================== */
+ #define R_ETHSW_ATIME_CTRL0_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ETHSW_ATIME_CTRL0_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Pos                                 (1UL)          /*!< ONE_SHOT (Bit 1)                                      */
+ #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Msk                                 (0x2UL)        /*!< ONE_SHOT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Pos                           (2UL)          /*!< EVT_OFFSET_ENA (Bit 2)                                */
+ #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Msk                           (0x4UL)        /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Pos                           (4UL)          /*!< EVT_PERIOD_ENA (Bit 4)                                */
+ #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Msk                           (0x10UL)       /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Pos                           (5UL)          /*!< EVT_PERIOD_RST (Bit 5)                                */
+ #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Msk                           (0x20UL)       /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL0_RESTART_Pos                                  (9UL)          /*!< RESTART (Bit 9)                                       */
+ #define R_ETHSW_ATIME_CTRL0_RESTART_Msk                                  (0x200UL)      /*!< RESTART (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ATIME_CTRL0_CAPTURE_Pos                                  (11UL)         /*!< CAPTURE (Bit 11)                                      */
+ #define R_ETHSW_ATIME_CTRL0_CAPTURE_Msk                                  (0x800UL)      /*!< CAPTURE (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Pos                              (12UL)         /*!< CAPTURE_ALL (Bit 12)                                  */
+ #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Msk                              (0x1000UL)     /*!< CAPTURE_ALL (Bitfield-Mask: 0x01)                     */
+/* ======================================================  ATIME_CTRL1  ====================================================== */
+ #define R_ETHSW_ATIME_CTRL1_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ETHSW_ATIME_CTRL1_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Pos                                 (1UL)          /*!< ONE_SHOT (Bit 1)                                      */
+ #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Msk                                 (0x2UL)        /*!< ONE_SHOT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Pos                           (2UL)          /*!< EVT_OFFSET_ENA (Bit 2)                                */
+ #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Msk                           (0x4UL)        /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Pos                           (4UL)          /*!< EVT_PERIOD_ENA (Bit 4)                                */
+ #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Msk                           (0x10UL)       /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Pos                           (5UL)          /*!< EVT_PERIOD_RST (Bit 5)                                */
+ #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Msk                           (0x20UL)       /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_ATIME_CTRL1_RESTART_Pos                                  (9UL)          /*!< RESTART (Bit 9)                                       */
+ #define R_ETHSW_ATIME_CTRL1_RESTART_Msk                                  (0x200UL)      /*!< RESTART (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ATIME_CTRL1_CAPTURE_Pos                                  (11UL)         /*!< CAPTURE (Bit 11)                                      */
+ #define R_ETHSW_ATIME_CTRL1_CAPTURE_Msk                                  (0x800UL)      /*!< CAPTURE (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Pos                              (12UL)         /*!< CAPTURE_ALL (Bit 12)                                  */
+ #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Msk                              (0x1000UL)     /*!< CAPTURE_ALL (Bitfield-Mask: 0x01)                     */
+/* ========================================================  ATIME0  ========================================================= */
+ #define R_ETHSW_ATIME0_TIMER_VAL_Pos                                     (0UL)          /*!< TIMER_VAL (Bit 0)                                     */
+ #define R_ETHSW_ATIME0_TIMER_VAL_Msk                                     (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff)                 */
+/* ========================================================  ATIME1  ========================================================= */
+ #define R_ETHSW_ATIME1_TIMER_VAL_Pos                                     (0UL)          /*!< TIMER_VAL (Bit 0)                                     */
+ #define R_ETHSW_ATIME1_TIMER_VAL_Msk                                     (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff)                 */
+/* =====================================================  ATIME_OFFSET0  ===================================================== */
+ #define R_ETHSW_ATIME_OFFSET0_OFFSET_Pos                                 (0UL)          /*!< OFFSET (Bit 0)                                        */
+ #define R_ETHSW_ATIME_OFFSET0_OFFSET_Msk                                 (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  ATIME_OFFSET1  ===================================================== */
+ #define R_ETHSW_ATIME_OFFSET1_OFFSET_Pos                                 (0UL)          /*!< OFFSET (Bit 0)                                        */
+ #define R_ETHSW_ATIME_OFFSET1_OFFSET_Msk                                 (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  ATIME_EVT_PERIOD0  =================================================== */
+ #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Pos                             (0UL)          /*!< PERIOD (Bit 0)                                        */
+ #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Msk                             (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  ATIME_EVT_PERIOD1  =================================================== */
+ #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Pos                             (0UL)          /*!< PERIOD (Bit 0)                                        */
+ #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Msk                             (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff)                    */
+/* ======================================================  ATIME_CORR0  ====================================================== */
+ #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Pos                              (0UL)          /*!< CORR_PERIOD (Bit 0)                                   */
+ #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Msk                              (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff)               */
+/* ======================================================  ATIME_CORR1  ====================================================== */
+ #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Pos                              (0UL)          /*!< CORR_PERIOD (Bit 0)                                   */
+ #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Msk                              (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff)               */
+/* ======================================================  ATIME_INC0  ======================================================= */
+ #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Pos                                (0UL)          /*!< CLK_PERIOD (Bit 0)                                    */
+ #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Msk                                (0x7fUL)       /*!< CLK_PERIOD (Bitfield-Mask: 0x7f)                      */
+ #define R_ETHSW_ATIME_INC0_CORR_INC_Pos                                  (8UL)          /*!< CORR_INC (Bit 8)                                      */
+ #define R_ETHSW_ATIME_INC0_CORR_INC_Msk                                  (0x7f00UL)     /*!< CORR_INC (Bitfield-Mask: 0x7f)                        */
+ #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Pos                             (16UL)         /*!< OFFS_CORR_INC (Bit 16)                                */
+ #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Msk                             (0x7f0000UL)   /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f)                   */
+/* ======================================================  ATIME_INC1  ======================================================= */
+ #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Pos                                (0UL)          /*!< CLK_PERIOD (Bit 0)                                    */
+ #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Msk                                (0x7fUL)       /*!< CLK_PERIOD (Bitfield-Mask: 0x7f)                      */
+ #define R_ETHSW_ATIME_INC1_CORR_INC_Pos                                  (8UL)          /*!< CORR_INC (Bit 8)                                      */
+ #define R_ETHSW_ATIME_INC1_CORR_INC_Msk                                  (0x7f00UL)     /*!< CORR_INC (Bitfield-Mask: 0x7f)                        */
+ #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Pos                             (16UL)         /*!< OFFS_CORR_INC (Bit 16)                                */
+ #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Msk                             (0x7f0000UL)   /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f)                   */
+/* ======================================================  ATIME_SEC0  ======================================================= */
+ #define R_ETHSW_ATIME_SEC0_SEC_TIME_Pos                                  (0UL)          /*!< SEC_TIME (Bit 0)                                      */
+ #define R_ETHSW_ATIME_SEC0_SEC_TIME_Msk                                  (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff)                  */
+/* ======================================================  ATIME_SEC1  ======================================================= */
+ #define R_ETHSW_ATIME_SEC1_SEC_TIME_Pos                                  (0UL)          /*!< SEC_TIME (Bit 0)                                      */
+ #define R_ETHSW_ATIME_SEC1_SEC_TIME_Msk                                  (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  ATIME_OFFS_CORR0  ==================================================== */
+ #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Pos                       (0UL)          /*!< OFFS_CORR_CNT (Bit 0)                                 */
+ #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Msk                       (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  ATIME_OFFS_CORR1  ==================================================== */
+ #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Pos                       (0UL)          /*!< OFFS_CORR_CNT (Bit 0)                                 */
+ #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Msk                       (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  MDIO_CFG_STATUS  ==================================================== */
+ #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Pos                                 (0UL)          /*!< BUSY (Bit 0)                                          */
+ #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Msk                                 (0x1UL)        /*!< BUSY (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_MDIO_CFG_STATUS_READERR_Pos                              (1UL)          /*!< READERR (Bit 1)                                       */
+ #define R_ETHSW_MDIO_CFG_STATUS_READERR_Msk                              (0x2UL)        /*!< READERR (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Pos                                 (2UL)          /*!< HOLD (Bit 2)                                          */
+ #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Msk                                 (0x1cUL)       /*!< HOLD (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Pos                             (5UL)          /*!< DISPREAM (Bit 5)                                      */
+ #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Msk                             (0x20UL)       /*!< DISPREAM (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Pos                               (7UL)          /*!< CLKDIV (Bit 7)                                        */
+ #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Msk                               (0xff80UL)     /*!< CLKDIV (Bitfield-Mask: 0x1ff)                         */
+/* =====================================================  MDIO_COMMAND  ====================================================== */
+ #define R_ETHSW_MDIO_COMMAND_REGADDR_Pos                                 (0UL)          /*!< REGADDR (Bit 0)                                       */
+ #define R_ETHSW_MDIO_COMMAND_REGADDR_Msk                                 (0x1fUL)       /*!< REGADDR (Bitfield-Mask: 0x1f)                         */
+ #define R_ETHSW_MDIO_COMMAND_PHYADDR_Pos                                 (5UL)          /*!< PHYADDR (Bit 5)                                       */
+ #define R_ETHSW_MDIO_COMMAND_PHYADDR_Msk                                 (0x3e0UL)      /*!< PHYADDR (Bitfield-Mask: 0x1f)                         */
+ #define R_ETHSW_MDIO_COMMAND_TRANINIT_Pos                                (15UL)         /*!< TRANINIT (Bit 15)                                     */
+ #define R_ETHSW_MDIO_COMMAND_TRANINIT_Msk                                (0x8000UL)     /*!< TRANINIT (Bitfield-Mask: 0x01)                        */
+/* =======================================================  MDIO_DATA  ======================================================= */
+ #define R_ETHSW_MDIO_DATA_MDIO_DATA_Pos                                  (0UL)          /*!< MDIO_DATA (Bit 0)                                     */
+ #define R_ETHSW_MDIO_DATA_MDIO_DATA_Msk                                  (0xffffUL)     /*!< MDIO_DATA (Bitfield-Mask: 0xffff)                     */
+/* ========================================================  REV_P0  ========================================================= */
+ #define R_ETHSW_REV_P0_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REV_P0_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  REV_P1  ========================================================= */
+ #define R_ETHSW_REV_P1_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REV_P1_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  REV_P2  ========================================================= */
+ #define R_ETHSW_REV_P2_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REV_P2_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  REV_P3  ========================================================= */
+ #define R_ETHSW_REV_P3_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ETHSW_REV_P3_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
+/* ===================================================  COMMAND_CONFIG_P0  =================================================== */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
+ #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+/* ===================================================  COMMAND_CONFIG_P1  =================================================== */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
+ #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P1_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P1_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+/* ===================================================  COMMAND_CONFIG_P2  =================================================== */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
+ #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P2_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P2_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+/* ===================================================  COMMAND_CONFIG_P3  =================================================== */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
+ #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
+ #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_COMMAND_CONFIG_P3_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P3_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+/* =====================================================  MAC_ADDR_0_P0  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  MAC_ADDR_0_P1  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  MAC_ADDR_0_P2  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  MAC_ADDR_1_P0  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  MAC_ADDR_1_P1  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  MAC_ADDR_1_P2  ===================================================== */
+ #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
+ #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  FRM_LENGTH_P0  ===================================================== */
+ #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
+ #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
+/* =====================================================  FRM_LENGTH_P1  ===================================================== */
+ #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
+ #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
+/* =====================================================  FRM_LENGTH_P2  ===================================================== */
+ #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
+ #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
+/* =====================================================  FRM_LENGTH_P3  ===================================================== */
+ #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
+ #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
+/* ====================================================  PAUSE_QUANT_P0  ===================================================== */
+ #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
+ #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  PAUSE_QUANT_P1  ===================================================== */
+ #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
+ #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  PAUSE_QUANT_P2  ===================================================== */
+ #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
+ #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  PAUSE_QUANT_P3  ===================================================== */
+ #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
+ #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
+/* ===================================================  MAC_LINK_QTRIG_P0  =================================================== */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_LINK_QTRIG_P1  =================================================== */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_LINK_QTRIG_P2  =================================================== */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
+ #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* =================================================  PTPCLOCKIDENTITY1_P0  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY1_P1  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY1_P2  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY2_P0  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY2_P1  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
+/* =================================================  PTPCLOCKIDENTITY2_P2  ================================================== */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
+ #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
+/* ==================================================  PTPAUTORESPONSE_P0  =================================================== */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
+/* ==================================================  PTPAUTORESPONSE_P1  =================================================== */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
+/* ==================================================  PTPAUTORESPONSE_P2  =================================================== */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
+ #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
+/* =======================================================  STATUS_P0  ======================================================= */
+ #define R_ETHSW_STATUS_P0_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
+ #define R_ETHSW_STATUS_P0_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_STATUS_P0_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
+ #define R_ETHSW_STATUS_P0_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_STATUS_P0_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
+ #define R_ETHSW_STATUS_P0_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P0_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
+ #define R_ETHSW_STATUS_P0_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P0_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
+ #define R_ETHSW_STATUS_P0_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
+ #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
+/* =======================================================  STATUS_P1  ======================================================= */
+ #define R_ETHSW_STATUS_P1_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
+ #define R_ETHSW_STATUS_P1_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_STATUS_P1_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
+ #define R_ETHSW_STATUS_P1_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_STATUS_P1_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
+ #define R_ETHSW_STATUS_P1_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P1_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
+ #define R_ETHSW_STATUS_P1_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P1_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
+ #define R_ETHSW_STATUS_P1_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
+ #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
+/* =======================================================  STATUS_P2  ======================================================= */
+ #define R_ETHSW_STATUS_P2_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
+ #define R_ETHSW_STATUS_P2_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_STATUS_P2_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
+ #define R_ETHSW_STATUS_P2_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_STATUS_P2_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
+ #define R_ETHSW_STATUS_P2_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P2_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
+ #define R_ETHSW_STATUS_P2_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P2_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
+ #define R_ETHSW_STATUS_P2_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
+ #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
+/* =======================================================  STATUS_P3  ======================================================= */
+ #define R_ETHSW_STATUS_P3_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
+ #define R_ETHSW_STATUS_P3_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
+ #define R_ETHSW_STATUS_P3_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
+ #define R_ETHSW_STATUS_P3_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_STATUS_P3_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
+ #define R_ETHSW_STATUS_P3_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P3_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
+ #define R_ETHSW_STATUS_P3_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATUS_P3_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
+ #define R_ETHSW_STATUS_P3_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
+ #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
+/* ===================================================  TX_IPG_LENGTH_P0  ==================================================== */
+ #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
+ #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
+/* ===================================================  TX_IPG_LENGTH_P1  ==================================================== */
+ #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
+ #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
+/* ===================================================  TX_IPG_LENGTH_P2  ==================================================== */
+ #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
+ #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
+/* ===================================================  TX_IPG_LENGTH_P3  ==================================================== */
+ #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
+ #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
+ #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
+/* ====================================================  EEE_CTL_STAT_P0  ==================================================== */
+ #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
+ #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
+/* ====================================================  EEE_CTL_STAT_P1  ==================================================== */
+ #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
+ #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
+/* ====================================================  EEE_CTL_STAT_P2  ==================================================== */
+ #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
+ #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
+ #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
+ #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
+/* ===================================================  EEE_IDLE_TIME_P0  ==================================================== */
+ #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_IDLE_TIME_P1  ==================================================== */
+ #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_IDLE_TIME_P2  ==================================================== */
+ #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_TWSYS_TIME_P0  =================================================== */
+ #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_TWSYS_TIME_P1  =================================================== */
+ #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  EEE_TWSYS_TIME_P2  =================================================== */
+ #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
+ #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
+/* =====================================================  IDLE_SLOPE_P0  ===================================================== */
+ #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
+ #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
+/* =====================================================  IDLE_SLOPE_P1  ===================================================== */
+ #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
+ #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
+/* =====================================================  IDLE_SLOPE_P2  ===================================================== */
+ #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
+ #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
+/* =====================================================  IDLE_SLOPE_P3  ===================================================== */
+ #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
+ #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
+/* ======================================================  CT_DELAY_P0  ====================================================== */
+ #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
+ #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
+/* ======================================================  CT_DELAY_P1  ====================================================== */
+ #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
+ #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
+/* ======================================================  CT_DELAY_P2  ====================================================== */
+ #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
+ #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
+/* =====================================================  BR_CONTROL_P0  ===================================================== */
+ #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
+ #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
+ #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
+ #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
+ #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
+ #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
+ #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
+ #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
+ #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
+ #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
+ #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
+ #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+/* =====================================================  BR_CONTROL_P1  ===================================================== */
+ #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
+ #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
+ #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
+ #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
+ #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
+ #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
+ #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
+ #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
+ #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
+ #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
+ #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
+ #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+/* =====================================================  BR_CONTROL_P2  ===================================================== */
+ #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
+ #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
+ #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
+ #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
+ #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
+ #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
+ #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
+ #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
+ #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
+ #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
+ #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
+ #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
+/* ================================================  AFRAMESTRANSMITTEDOK_P0  ================================================ */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AFRAMESTRANSMITTEDOK_P1  ================================================ */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AFRAMESTRANSMITTEDOK_P2  ================================================ */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AFRAMESTRANSMITTEDOK_P3  ================================================ */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* =================================================  AFRAMESRECEIVEDOK_P0  ================================================== */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  AFRAMESRECEIVEDOK_P1  ================================================== */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  AFRAMESRECEIVEDOK_P2  ================================================== */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  AFRAMESRECEIVEDOK_P3  ================================================== */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =============================================  AFRAMECHECKSEQUENCEERRORS_P0  ============================================== */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  AFRAMECHECKSEQUENCEERRORS_P1  ============================================== */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  AFRAMECHECKSEQUENCEERRORS_P2  ============================================== */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  AFRAMECHECKSEQUENCEERRORS_P3  ============================================== */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ==================================================  AALIGNMENTERRORS_P0  ================================================== */
+ #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ==================================================  AALIGNMENTERRORS_P1  ================================================== */
+ #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ==================================================  AALIGNMENTERRORS_P2  ================================================== */
+ #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ==================================================  AALIGNMENTERRORS_P3  ================================================== */
+ #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ================================================  AOCTETSTRANSMITTEDOK_P0  ================================================ */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
+/* ================================================  AOCTETSTRANSMITTEDOK_P1  ================================================ */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
+/* ================================================  AOCTETSTRANSMITTEDOK_P2  ================================================ */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
+/* ================================================  AOCTETSTRANSMITTEDOK_P3  ================================================ */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
+/* =================================================  AOCTETSRECEIVEDOK_P0  ================================================== */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
+/* =================================================  AOCTETSRECEIVEDOK_P1  ================================================== */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
+/* =================================================  AOCTETSRECEIVEDOK_P2  ================================================== */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
+/* =================================================  AOCTETSRECEIVEDOK_P3  ================================================== */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
+ #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
+/* ===============================================  ATXPAUSEMACCTRLFRAMES_P0  ================================================ */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ATXPAUSEMACCTRLFRAMES_P1  ================================================ */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ATXPAUSEMACCTRLFRAMES_P2  ================================================ */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ATXPAUSEMACCTRLFRAMES_P3  ================================================ */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ARXPAUSEMACCTRLFRAMES_P0  ================================================ */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ARXPAUSEMACCTRLFRAMES_P1  ================================================ */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ARXPAUSEMACCTRLFRAMES_P2  ================================================ */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* ===============================================  ARXPAUSEMACCTRLFRAMES_P3  ================================================ */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
+ #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
+/* =====================================================  IFINERRORS_P0  ===================================================== */
+ #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  IFINERRORS_P1  ===================================================== */
+ #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  IFINERRORS_P2  ===================================================== */
+ #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  IFINERRORS_P3  ===================================================== */
+ #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  IFOUTERRORS_P0  ===================================================== */
+ #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ====================================================  IFOUTERRORS_P1  ===================================================== */
+ #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ====================================================  IFOUTERRORS_P2  ===================================================== */
+ #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ====================================================  IFOUTERRORS_P3  ===================================================== */
+ #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFINUCASTPKTS_P0  ==================================================== */
+ #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFINUCASTPKTS_P1  ==================================================== */
+ #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFINUCASTPKTS_P2  ==================================================== */
+ #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFINUCASTPKTS_P3  ==================================================== */
+ #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* =================================================  IFINMULTICASTPKTS_P0  ================================================== */
+ #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINMULTICASTPKTS_P1  ================================================== */
+ #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINMULTICASTPKTS_P2  ================================================== */
+ #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINMULTICASTPKTS_P3  ================================================== */
+ #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINBROADCASTPKTS_P0  ================================================== */
+ #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINBROADCASTPKTS_P1  ================================================== */
+ #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINBROADCASTPKTS_P2  ================================================== */
+ #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  IFINBROADCASTPKTS_P3  ================================================== */
+ #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  IFOUTDISCARDS_P0  ==================================================== */
+ #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFOUTDISCARDS_P1  ==================================================== */
+ #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFOUTDISCARDS_P2  ==================================================== */
+ #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFOUTDISCARDS_P3  ==================================================== */
+ #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
+ #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  IFOUTUCASTPKTS_P0  =================================================== */
+ #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFOUTUCASTPKTS_P1  =================================================== */
+ #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFOUTUCASTPKTS_P2  =================================================== */
+ #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  IFOUTUCASTPKTS_P3  =================================================== */
+ #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
+/* =================================================  IFOUTMULTICASTPKTS_P0  ================================================= */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTMULTICASTPKTS_P1  ================================================= */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTMULTICASTPKTS_P2  ================================================= */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTMULTICASTPKTS_P3  ================================================= */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTBROADCASTPKTS_P0  ================================================= */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTBROADCASTPKTS_P1  ================================================= */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTBROADCASTPKTS_P2  ================================================= */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  IFOUTBROADCASTPKTS_P3  ================================================= */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
+/* ================================================  ETHERSTATSDROPEVENTS_P0  ================================================ */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  ETHERSTATSDROPEVENTS_P1  ================================================ */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  ETHERSTATSDROPEVENTS_P2  ================================================ */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  ETHERSTATSDROPEVENTS_P3  ================================================ */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  ETHERSTATSOCTETS_P0  ================================================== */
+ #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
+/* ==================================================  ETHERSTATSOCTETS_P1  ================================================== */
+ #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
+/* ==================================================  ETHERSTATSOCTETS_P2  ================================================== */
+ #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
+/* ==================================================  ETHERSTATSOCTETS_P3  ================================================== */
+ #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
+/* ===================================================  ETHERSTATSPKTS_P0  =================================================== */
+ #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  ETHERSTATSPKTS_P1  =================================================== */
+ #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  ETHERSTATSPKTS_P2  =================================================== */
+ #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  ETHERSTATSPKTS_P3  =================================================== */
+ #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  ETHERSTATSUNDERSIZEPKTS_P0  =============================================== */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ==============================================  ETHERSTATSUNDERSIZEPKTS_P1  =============================================== */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ==============================================  ETHERSTATSUNDERSIZEPKTS_P2  =============================================== */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ==============================================  ETHERSTATSUNDERSIZEPKTS_P3  =============================================== */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
+/* ===============================================  ETHERSTATSOVERSIZEPKTS_P0  =============================================== */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
+/* ===============================================  ETHERSTATSOVERSIZEPKTS_P1  =============================================== */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
+/* ===============================================  ETHERSTATSOVERSIZEPKTS_P2  =============================================== */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
+/* ===============================================  ETHERSTATSOVERSIZEPKTS_P3  =============================================== */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
+ #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
+/* ===============================================  ETHERSTATSPKTS64OCTETS_P0  =============================================== */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  ETHERSTATSPKTS64OCTETS_P1  =============================================== */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  ETHERSTATSPKTS64OCTETS_P2  =============================================== */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  ETHERSTATSPKTS64OCTETS_P3  =============================================== */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
+ #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
+/* ============================================  ETHERSTATSPKTS65TO127OCTETS_P0  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS65TO127OCTETS_P1  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS65TO127OCTETS_P2  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS65TO127OCTETS_P3  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS128TO255OCTETS_P0  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS128TO255OCTETS_P1  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS128TO255OCTETS_P2  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS128TO255OCTETS_P3  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS256TO511OCTETS_P0  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS256TO511OCTETS_P1  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS256TO511OCTETS_P2  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS256TO511OCTETS_P3  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
+ #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P0  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P1  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P2  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P3  ============================================ */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
+ #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P0  =========================================== */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P1  =========================================== */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P2  =========================================== */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
+/* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P3  =========================================== */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
+ #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
+/* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P0  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P1  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P2  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
+/* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P3  ============================================= */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
+ #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
+/* =================================================  ETHERSTATSJABBERS_P0  ================================================== */
+ #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
+ #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  ETHERSTATSJABBERS_P1  ================================================== */
+ #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
+ #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  ETHERSTATSJABBERS_P2  ================================================== */
+ #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
+ #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  ETHERSTATSJABBERS_P3  ================================================== */
+ #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
+ #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ================================================  ETHERSTATSFRAGMENTS_P0  ================================================= */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  ETHERSTATSFRAGMENTS_P1  ================================================= */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  ETHERSTATSFRAGMENTS_P2  ================================================= */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  ETHERSTATSFRAGMENTS_P3  ================================================= */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
+ #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ===================================================  VLANRECEIVEDOK_P0  =================================================== */
+ #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  VLANRECEIVEDOK_P1  =================================================== */
+ #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  VLANRECEIVEDOK_P2  =================================================== */
+ #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  VLANRECEIVEDOK_P3  =================================================== */
+ #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
+/* =================================================  VLANTRANSMITTEDOK_P0  ================================================== */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VLANTRANSMITTEDOK_P1  ================================================== */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VLANTRANSMITTEDOK_P2  ================================================== */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VLANTRANSMITTEDOK_P3  ================================================== */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
+ #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
+/* ================================================  FRAMESRETRANSMITTED_P0  ================================================= */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  FRAMESRETRANSMITTED_P1  ================================================= */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  FRAMESRETRANSMITTED_P2  ================================================= */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  FRAMESRETRANSMITTED_P3  ================================================= */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
+ #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ====================================================  STATS_HIWORD_P0  ==================================================== */
+ #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
+ #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  STATS_HIWORD_P1  ==================================================== */
+ #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
+ #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  STATS_HIWORD_P2  ==================================================== */
+ #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
+ #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  STATS_HIWORD_P3  ==================================================== */
+ #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
+ #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
+/* =====================================================  STATS_CTRL_P0  ===================================================== */
+ #define R_ETHSW_STATS_CTRL_P0_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
+ #define R_ETHSW_STATS_CTRL_P0_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
+ #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
+/* =====================================================  STATS_CTRL_P1  ===================================================== */
+ #define R_ETHSW_STATS_CTRL_P1_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
+ #define R_ETHSW_STATS_CTRL_P1_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
+ #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
+/* =====================================================  STATS_CTRL_P2  ===================================================== */
+ #define R_ETHSW_STATS_CTRL_P2_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
+ #define R_ETHSW_STATS_CTRL_P2_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
+ #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
+/* =====================================================  STATS_CTRL_P3  ===================================================== */
+ #define R_ETHSW_STATS_CTRL_P3_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
+ #define R_ETHSW_STATS_CTRL_P3_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
+ #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
+/* ================================================  STATS_CLEAR_VALUELO_P0  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUELO_P1  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUELO_P2  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUELO_P3  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUEHI_P0  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUEHI_P1  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUEHI_P2  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
+/* ================================================  STATS_CLEAR_VALUEHI_P3  ================================================= */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
+ #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
+/* =====================================================  ADEFERRED_P0  ====================================================== */
+ #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  ADEFERRED_P1  ====================================================== */
+ #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  ADEFERRED_P2  ====================================================== */
+ #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  ADEFERRED_P3  ====================================================== */
+ #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  AMULTIPLECOLLISIONS_P0  ================================================= */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
+/* ================================================  AMULTIPLECOLLISIONS_P1  ================================================= */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
+/* ================================================  AMULTIPLECOLLISIONS_P2  ================================================= */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
+/* ================================================  AMULTIPLECOLLISIONS_P3  ================================================= */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
+ #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
+/* =================================================  ASINGLECOLLISIONS_P0  ================================================== */
+ #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
+ #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
+/* =================================================  ASINGLECOLLISIONS_P1  ================================================== */
+ #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
+ #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
+/* =================================================  ASINGLECOLLISIONS_P2  ================================================== */
+ #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
+ #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
+/* =================================================  ASINGLECOLLISIONS_P3  ================================================== */
+ #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
+ #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
+/* ==================================================  ALATECOLLISIONS_P0  =================================================== */
+ #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
+ #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  ALATECOLLISIONS_P1  =================================================== */
+ #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
+ #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  ALATECOLLISIONS_P2  =================================================== */
+ #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
+ #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  ALATECOLLISIONS_P3  =================================================== */
+ #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
+ #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
+/* ================================================  AEXCESSIVECOLLISIONS_P0  ================================================ */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AEXCESSIVECOLLISIONS_P1  ================================================ */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AEXCESSIVECOLLISIONS_P2  ================================================ */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  AEXCESSIVECOLLISIONS_P3  ================================================ */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
+ #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  ACARRIERSENSEERRORS_P0  ================================================= */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ================================================  ACARRIERSENSEERRORS_P1  ================================================= */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ================================================  ACARRIERSENSEERRORS_P2  ================================================= */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ================================================  ACARRIERSENSEERRORS_P3  ================================================= */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
+ #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  P0_QSTMACU0  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU1  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU2  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU3  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU4  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU5  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU6  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACU7  ====================================================== */
+ #define R_ETHSW_P0_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P0_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P0_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P0_QSTMACD0  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD1  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD2  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD3  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD4  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD5  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD6  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMACD7  ====================================================== */
+ #define R_ETHSW_P0_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P0_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P0_QSTMAMU0  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU1  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU2  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU3  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU4  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU5  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU6  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMU7  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QSTMAMD0  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD1  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD2  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD3  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD4  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD5  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD6  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSTMAMD7  ====================================================== */
+ #define R_ETHSW_P0_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P0_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P0_QSFTVL0  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL1  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL2  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL3  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL4  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL5  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL6  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVL7  ======================================================= */
+ #define R_ETHSW_P0_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P0_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P0_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P0_QSFTVLM0  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM1  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM2  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM3  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM4  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM5  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM6  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTVLM7  ====================================================== */
+ #define R_ETHSW_P0_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P0_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P0_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P0_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P0_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P0_QSFTBL0  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL1  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL2  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL3  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL4  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL5  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL6  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P0_QSFTBL7  ======================================================= */
+ #define R_ETHSW_P0_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P0_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P0_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P0_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P0_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P0_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P0_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P0_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P0_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P0_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P0_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P0_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P0_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  P0_QSMFC0  ======================================================= */
+ #define R_ETHSW_P0_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC1  ======================================================= */
+ #define R_ETHSW_P0_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC2  ======================================================= */
+ #define R_ETHSW_P0_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC3  ======================================================= */
+ #define R_ETHSW_P0_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC4  ======================================================= */
+ #define R_ETHSW_P0_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC5  ======================================================= */
+ #define R_ETHSW_P0_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC6  ======================================================= */
+ #define R_ETHSW_P0_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QSMFC7  ======================================================= */
+ #define R_ETHSW_P0_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P0_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P0_QMSPPC0  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC1  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC2  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC3  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC4  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC5  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC6  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSPPC7  ======================================================= */
+ #define R_ETHSW_P0_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC0  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC1  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC2  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC3  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC4  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC5  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC6  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P0_QMSRPC7  ======================================================= */
+ #define R_ETHSW_P0_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P0_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  P0_QSEIS  ======================================================== */
+ #define R_ETHSW_P0_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
+ #define R_ETHSW_P0_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QSEIS  ======================================================== */
+ #define R_ETHSW_P1_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
+ #define R_ETHSW_P1_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QSEIS  ======================================================== */
+ #define R_ETHSW_P2_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
+ #define R_ETHSW_P2_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QSEIE  ======================================================== */
+ #define R_ETHSW_P0_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
+ #define R_ETHSW_P0_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QSEIE  ======================================================== */
+ #define R_ETHSW_P1_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
+ #define R_ETHSW_P1_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QSEIE  ======================================================== */
+ #define R_ETHSW_P2_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
+ #define R_ETHSW_P2_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QSEID  ======================================================== */
+ #define R_ETHSW_P0_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
+ #define R_ETHSW_P0_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QSEID  ======================================================== */
+ #define R_ETHSW_P1_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QSEID  ======================================================== */
+ #define R_ETHSW_P2_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QGMOD  ======================================================== */
+ #define R_ETHSW_P0_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
+ #define R_ETHSW_P0_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P1_QGMOD  ======================================================== */
+ #define R_ETHSW_P1_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
+ #define R_ETHSW_P1_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P2_QGMOD  ======================================================== */
+ #define R_ETHSW_P2_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
+ #define R_ETHSW_P2_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P0_QGPPC  ======================================================== */
+ #define R_ETHSW_P0_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGPPC  ======================================================== */
+ #define R_ETHSW_P1_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGPPC  ======================================================== */
+ #define R_ETHSW_P2_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC0  ======================================================= */
+ #define R_ETHSW_P0_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC1  ======================================================= */
+ #define R_ETHSW_P0_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC2  ======================================================= */
+ #define R_ETHSW_P0_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC3  ======================================================= */
+ #define R_ETHSW_P0_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC4  ======================================================= */
+ #define R_ETHSW_P0_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC5  ======================================================= */
+ #define R_ETHSW_P0_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC6  ======================================================= */
+ #define R_ETHSW_P0_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGDPC7  ======================================================= */
+ #define R_ETHSW_P0_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QGEIS  ======================================================== */
+ #define R_ETHSW_P0_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
+ #define R_ETHSW_P0_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QGEIS  ======================================================== */
+ #define R_ETHSW_P1_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
+ #define R_ETHSW_P1_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QGEIS  ======================================================== */
+ #define R_ETHSW_P2_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
+ #define R_ETHSW_P2_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QGEIE  ======================================================== */
+ #define R_ETHSW_P0_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
+ #define R_ETHSW_P0_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QGEIE  ======================================================== */
+ #define R_ETHSW_P1_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
+ #define R_ETHSW_P1_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QGEIE  ======================================================== */
+ #define R_ETHSW_P2_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
+ #define R_ETHSW_P2_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P0_QGEID  ======================================================== */
+ #define R_ETHSW_P0_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
+ #define R_ETHSW_P0_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P1_QGEID  ======================================================== */
+ #define R_ETHSW_P1_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
+ #define R_ETHSW_P1_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
+/* =======================================================  P2_QGEID  ======================================================== */
+ #define R_ETHSW_P2_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
+ #define R_ETHSW_P2_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
+/* ======================================================  P0_QMDESC0  ======================================================= */
+ #define R_ETHSW_P0_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC1  ======================================================= */
+ #define R_ETHSW_P0_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC2  ======================================================= */
+ #define R_ETHSW_P0_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC3  ======================================================= */
+ #define R_ETHSW_P0_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC4  ======================================================= */
+ #define R_ETHSW_P0_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC5  ======================================================= */
+ #define R_ETHSW_P0_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC6  ======================================================= */
+ #define R_ETHSW_P0_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMDESC7  ======================================================= */
+ #define R_ETHSW_P0_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P0_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P0_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P0_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P0_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P0_QMCBSC0  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC1  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC2  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC3  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC4  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC5  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC6  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCBSC7  ======================================================= */
+ #define R_ETHSW_P0_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P0_QMCIRC0  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC1  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC2  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC3  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC4  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC5  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC6  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P0_QMCIRC7  ======================================================= */
+ #define R_ETHSW_P0_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P0_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* =======================================================  P0_QMGPC0  ======================================================= */
+ #define R_ETHSW_P0_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC1  ======================================================= */
+ #define R_ETHSW_P0_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC2  ======================================================= */
+ #define R_ETHSW_P0_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC3  ======================================================= */
+ #define R_ETHSW_P0_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC4  ======================================================= */
+ #define R_ETHSW_P0_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC5  ======================================================= */
+ #define R_ETHSW_P0_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC6  ======================================================= */
+ #define R_ETHSW_P0_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMGPC7  ======================================================= */
+ #define R_ETHSW_P0_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC0  ======================================================= */
+ #define R_ETHSW_P0_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC1  ======================================================= */
+ #define R_ETHSW_P0_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC2  ======================================================= */
+ #define R_ETHSW_P0_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC3  ======================================================= */
+ #define R_ETHSW_P0_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC4  ======================================================= */
+ #define R_ETHSW_P0_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC5  ======================================================= */
+ #define R_ETHSW_P0_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC6  ======================================================= */
+ #define R_ETHSW_P0_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P0_QMRPC7  ======================================================= */
+ #define R_ETHSW_P0_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P0_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  P0_QMEC  ======================================================== */
+ #define R_ETHSW_P0_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
+ #define R_ETHSW_P0_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
+/* ========================================================  P1_QMEC  ======================================================== */
+ #define R_ETHSW_P1_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
+ #define R_ETHSW_P1_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
+/* ========================================================  P2_QMEC  ======================================================== */
+ #define R_ETHSW_P2_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
+ #define R_ETHSW_P2_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
+/* =======================================================  P0_QMEIS  ======================================================== */
+ #define R_ETHSW_P0_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
+ #define R_ETHSW_P0_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P1_QMEIS  ======================================================== */
+ #define R_ETHSW_P1_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
+ #define R_ETHSW_P1_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P2_QMEIS  ======================================================== */
+ #define R_ETHSW_P2_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
+ #define R_ETHSW_P2_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P0_QMEIE  ======================================================== */
+ #define R_ETHSW_P0_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
+ #define R_ETHSW_P0_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P1_QMEIE  ======================================================== */
+ #define R_ETHSW_P1_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
+ #define R_ETHSW_P1_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P2_QMEIE  ======================================================== */
+ #define R_ETHSW_P2_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
+ #define R_ETHSW_P2_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P0_QMEID  ======================================================== */
+ #define R_ETHSW_P0_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
+ #define R_ETHSW_P0_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P1_QMEID  ======================================================== */
+ #define R_ETHSW_P1_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
+ #define R_ETHSW_P1_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
+/* =======================================================  P2_QMEID  ======================================================== */
+ #define R_ETHSW_P2_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
+ #define R_ETHSW_P2_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
+/* =====================================================  P0_PCP_REMAP  ====================================================== */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
+ #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
+/* =====================================================  P1_PCP_REMAP  ====================================================== */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
+ #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
+/* =====================================================  P2_PCP_REMAP  ====================================================== */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
+ #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
+/* ======================================================  P0_VLAN_TAG  ====================================================== */
+ #define R_ETHSW_P0_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_ETHSW_P0_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
+ #define R_ETHSW_P0_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P0_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P0_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P0_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P0_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
+ #define R_ETHSW_P0_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  P1_VLAN_TAG  ====================================================== */
+ #define R_ETHSW_P1_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_ETHSW_P1_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
+ #define R_ETHSW_P1_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
+ #define R_ETHSW_P1_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  P2_VLAN_TAG  ====================================================== */
+ #define R_ETHSW_P2_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_ETHSW_P2_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
+ #define R_ETHSW_P2_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
+ #define R_ETHSW_P2_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  P0_VLAN_MODE  ====================================================== */
+ #define R_ETHSW_P0_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
+ #define R_ETHSW_P0_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_P0_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
+ #define R_ETHSW_P0_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
+/* =====================================================  P1_VLAN_MODE  ====================================================== */
+ #define R_ETHSW_P1_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
+ #define R_ETHSW_P1_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_P1_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
+ #define R_ETHSW_P1_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
+/* =====================================================  P2_VLAN_MODE  ====================================================== */
+ #define R_ETHSW_P2_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
+ #define R_ETHSW_P2_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_P2_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
+ #define R_ETHSW_P2_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
+/* ====================================================  P0_VIC_DROP_CNT  ==================================================== */
+ #define R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
+ #define R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
+/* ====================================================  P1_VIC_DROP_CNT  ==================================================== */
+ #define R_ETHSW_P1_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
+ #define R_ETHSW_P1_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
+/* ====================================================  P2_VIC_DROP_CNT  ==================================================== */
+ #define R_ETHSW_P2_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
+ #define R_ETHSW_P2_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
+/* ===================================================  P0_LOOKUP_HIT_CNT  =================================================== */
+ #define R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
+ #define R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
+/* ===================================================  P1_LOOKUP_HIT_CNT  =================================================== */
+ #define R_ETHSW_P1_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
+ #define R_ETHSW_P1_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
+/* ===================================================  P2_LOOKUP_HIT_CNT  =================================================== */
+ #define R_ETHSW_P2_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
+ #define R_ETHSW_P2_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
+/* ====================================================  P0_ERROR_STATUS  ==================================================== */
+ #define R_ETHSW_P0_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P0_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
+ #define R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
+/* ====================================================  P1_ERROR_STATUS  ==================================================== */
+ #define R_ETHSW_P1_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P1_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P1_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P1_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P1_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
+ #define R_ETHSW_P1_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
+/* ====================================================  P2_ERROR_STATUS  ==================================================== */
+ #define R_ETHSW_P2_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P2_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P2_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P2_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_P2_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
+ #define R_ETHSW_P2_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
+/* =====================================================  P0_ERROR_MASK  ===================================================== */
+ #define R_ETHSW_P0_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
+ #define R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
+/* =====================================================  P1_ERROR_MASK  ===================================================== */
+ #define R_ETHSW_P1_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P1_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P1_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P1_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P1_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
+ #define R_ETHSW_P1_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
+/* =====================================================  P2_ERROR_MASK  ===================================================== */
+ #define R_ETHSW_P2_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P2_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P2_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P2_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_P2_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
+ #define R_ETHSW_P2_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CHANNEL_STATE  ===================================================== */
+ #define R_ETHSW_CHANNEL_STATE_CH0ACT_Pos                                 (0UL)          /*!< CH0ACT (Bit 0)                                        */
+ #define R_ETHSW_CHANNEL_STATE_CH0ACT_Msk                                 (0x1UL)        /*!< CH0ACT (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_STATE_CH1ACT_Pos                                 (1UL)          /*!< CH1ACT (Bit 1)                                        */
+ #define R_ETHSW_CHANNEL_STATE_CH1ACT_Msk                                 (0x2UL)        /*!< CH1ACT (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_STATE_CH2ACT_Pos                                 (2UL)          /*!< CH2ACT (Bit 2)                                        */
+ #define R_ETHSW_CHANNEL_STATE_CH2ACT_Msk                                 (0x4UL)        /*!< CH2ACT (Bitfield-Mask: 0x01)                          */
+/* ====================================================  CHANNEL_ENABLE  ===================================================== */
+ #define R_ETHSW_CHANNEL_ENABLE_CH0ENA_Pos                                (0UL)          /*!< CH0ENA (Bit 0)                                        */
+ #define R_ETHSW_CHANNEL_ENABLE_CH0ENA_Msk                                (0x1UL)        /*!< CH0ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_ENABLE_CH1ENA_Pos                                (1UL)          /*!< CH1ENA (Bit 1)                                        */
+ #define R_ETHSW_CHANNEL_ENABLE_CH1ENA_Msk                                (0x2UL)        /*!< CH1ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_ENABLE_CH2ENA_Pos                                (2UL)          /*!< CH2ENA (Bit 2)                                        */
+ #define R_ETHSW_CHANNEL_ENABLE_CH2ENA_Msk                                (0x4UL)        /*!< CH2ENA (Bitfield-Mask: 0x01)                          */
+/* ====================================================  CHANNEL_DISABLE  ==================================================== */
+ #define R_ETHSW_CHANNEL_DISABLE_CH0DIS_Pos                               (0UL)          /*!< CH0DIS (Bit 0)                                        */
+ #define R_ETHSW_CHANNEL_DISABLE_CH0DIS_Msk                               (0x1UL)        /*!< CH0DIS (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_DISABLE_CH1DIS_Pos                               (1UL)          /*!< CH1DIS (Bit 1)                                        */
+ #define R_ETHSW_CHANNEL_DISABLE_CH1DIS_Msk                               (0x2UL)        /*!< CH1DIS (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_CHANNEL_DISABLE_CH2DIS_Pos                               (2UL)          /*!< CH2DIS (Bit 2)                                        */
+ #define R_ETHSW_CHANNEL_DISABLE_CH2DIS_Msk                               (0x4UL)        /*!< CH2DIS (Bitfield-Mask: 0x01)                          */
+/* =====================================================  ASI_MEM_WDATA  ===================================================== */
+ #define R_ETHSW_ASI_MEM_WDATA_WDATA_Pos                                  (0UL)          /*!< WDATA (Bit 0)                                         */
+ #define R_ETHSW_ASI_MEM_WDATA_WDATA_Msk                                  (0xffffffffUL) /*!< WDATA (Bitfield-Mask: 0xffffffff)                     */
+/* =====================================================  ASI_MEM_ADDR  ====================================================== */
+ #define R_ETHSW_ASI_MEM_ADDR_ADDR_Pos                                    (0UL)          /*!< ADDR (Bit 0)                                          */
+ #define R_ETHSW_ASI_MEM_ADDR_ADDR_Msk                                    (0x7fUL)       /*!< ADDR (Bitfield-Mask: 0x7f)                            */
+ #define R_ETHSW_ASI_MEM_ADDR_MEM_WEN_Pos                                 (7UL)          /*!< MEM_WEN (Bit 7)                                       */
+ #define R_ETHSW_ASI_MEM_ADDR_MEM_WEN_Msk                                 (0x80UL)       /*!< MEM_WEN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos                                 (8UL)          /*!< MEM_REQ (Bit 8)                                       */
+ #define R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk                                 (0x700UL)      /*!< MEM_REQ (Bitfield-Mask: 0x07)                         */
+/* =====================================================  ASI_MEM_RDATA  ===================================================== */
+ #define R_ETHSW_ASI_MEM_RDATA_RDATA_Pos                                  (0UL)          /*!< RDATA (Bit 0)                                         */
+ #define R_ETHSW_ASI_MEM_RDATA_RDATA_Msk                                  (0xffffffffUL) /*!< RDATA (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMACU0  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU1  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU2  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU3  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU4  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU5  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU6  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACU7  ====================================================== */
+ #define R_ETHSW_P1_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P1_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P1_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P1_QSTMACD0  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD1  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD2  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD3  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD4  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD5  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD6  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMACD7  ====================================================== */
+ #define R_ETHSW_P1_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P1_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P1_QSTMAMU0  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU1  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU2  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU3  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU4  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU5  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU6  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMU7  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QSTMAMD0  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD1  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD2  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD3  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD4  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD5  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD6  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSTMAMD7  ====================================================== */
+ #define R_ETHSW_P1_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P1_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P1_QSFTVL0  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL1  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL2  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL3  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL4  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL5  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL6  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVL7  ======================================================= */
+ #define R_ETHSW_P1_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P1_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P1_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P1_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P1_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P1_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P1_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P1_QSFTVLM0  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM1  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM2  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM3  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM4  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM5  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM6  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTVLM7  ====================================================== */
+ #define R_ETHSW_P1_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P1_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P1_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P1_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P1_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P1_QSFTBL0  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL1  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL2  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL3  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL4  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL5  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL6  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P1_QSFTBL7  ======================================================= */
+ #define R_ETHSW_P1_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P1_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P1_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P1_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P1_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P1_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P1_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P1_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P1_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P1_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P1_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P1_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P1_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  P1_QSMFC0  ======================================================= */
+ #define R_ETHSW_P1_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC1  ======================================================= */
+ #define R_ETHSW_P1_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC2  ======================================================= */
+ #define R_ETHSW_P1_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC3  ======================================================= */
+ #define R_ETHSW_P1_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC4  ======================================================= */
+ #define R_ETHSW_P1_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC5  ======================================================= */
+ #define R_ETHSW_P1_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC6  ======================================================= */
+ #define R_ETHSW_P1_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QSMFC7  ======================================================= */
+ #define R_ETHSW_P1_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P1_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QMSPPC0  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC1  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC2  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC3  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC4  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC5  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC6  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSPPC7  ======================================================= */
+ #define R_ETHSW_P1_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC0  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC1  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC2  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC3  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC4  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC5  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC6  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P1_QMSRPC7  ======================================================= */
+ #define R_ETHSW_P1_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P1_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  P1_QGDPC0  ======================================================= */
+ #define R_ETHSW_P1_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC1  ======================================================= */
+ #define R_ETHSW_P1_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC2  ======================================================= */
+ #define R_ETHSW_P1_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC3  ======================================================= */
+ #define R_ETHSW_P1_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC4  ======================================================= */
+ #define R_ETHSW_P1_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC5  ======================================================= */
+ #define R_ETHSW_P1_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC6  ======================================================= */
+ #define R_ETHSW_P1_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QGDPC7  ======================================================= */
+ #define R_ETHSW_P1_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P1_QMDESC0  ======================================================= */
+ #define R_ETHSW_P1_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC1  ======================================================= */
+ #define R_ETHSW_P1_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC2  ======================================================= */
+ #define R_ETHSW_P1_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC3  ======================================================= */
+ #define R_ETHSW_P1_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC4  ======================================================= */
+ #define R_ETHSW_P1_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC5  ======================================================= */
+ #define R_ETHSW_P1_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC6  ======================================================= */
+ #define R_ETHSW_P1_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMDESC7  ======================================================= */
+ #define R_ETHSW_P1_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P1_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P1_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P1_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P1_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P1_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P1_QMCBSC0  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC1  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC2  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC3  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC4  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC5  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC6  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCBSC7  ======================================================= */
+ #define R_ETHSW_P1_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P1_QMCIRC0  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC1  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC2  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC3  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC4  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC5  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC6  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P1_QMCIRC7  ======================================================= */
+ #define R_ETHSW_P1_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P1_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* =======================================================  P1_QMGPC0  ======================================================= */
+ #define R_ETHSW_P1_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC1  ======================================================= */
+ #define R_ETHSW_P1_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC2  ======================================================= */
+ #define R_ETHSW_P1_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC3  ======================================================= */
+ #define R_ETHSW_P1_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC4  ======================================================= */
+ #define R_ETHSW_P1_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC5  ======================================================= */
+ #define R_ETHSW_P1_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC6  ======================================================= */
+ #define R_ETHSW_P1_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMGPC7  ======================================================= */
+ #define R_ETHSW_P1_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC0  ======================================================= */
+ #define R_ETHSW_P1_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC1  ======================================================= */
+ #define R_ETHSW_P1_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC2  ======================================================= */
+ #define R_ETHSW_P1_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC3  ======================================================= */
+ #define R_ETHSW_P1_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC4  ======================================================= */
+ #define R_ETHSW_P1_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC5  ======================================================= */
+ #define R_ETHSW_P1_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC6  ======================================================= */
+ #define R_ETHSW_P1_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P1_QMRPC7  ======================================================= */
+ #define R_ETHSW_P1_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P1_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMACU0  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU1  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU2  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU3  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU4  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU5  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU6  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACU7  ====================================================== */
+ #define R_ETHSW_P2_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHSW_P2_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
+ #define R_ETHSW_P2_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
+/* ======================================================  P2_QSTMACD0  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD1  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD2  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD3  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD4  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD5  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD6  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMACD7  ====================================================== */
+ #define R_ETHSW_P2_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
+ #define R_ETHSW_P2_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  P2_QSTMAMU0  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU1  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU2  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU3  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU4  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU5  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU6  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMU7  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QSTMAMD0  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD1  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD2  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD3  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD4  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD5  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD6  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSTMAMD7  ====================================================== */
+ #define R_ETHSW_P2_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
+ #define R_ETHSW_P2_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  P2_QSFTVL0  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL1  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL2  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL3  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL4  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL5  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL6  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVL7  ======================================================= */
+ #define R_ETHSW_P2_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
+ #define R_ETHSW_P2_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
+ #define R_ETHSW_P2_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
+ #define R_ETHSW_P2_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
+ #define R_ETHSW_P2_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
+ #define R_ETHSW_P2_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
+ #define R_ETHSW_P2_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
+/* ======================================================  P2_QSFTVLM0  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM1  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM2  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM3  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM4  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM5  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM6  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTVLM7  ====================================================== */
+ #define R_ETHSW_P2_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
+ #define R_ETHSW_P2_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_P2_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
+ #define R_ETHSW_P2_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
+ #define R_ETHSW_P2_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
+/* ======================================================  P2_QSFTBL0  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL1  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL2  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL3  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL4  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL5  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL6  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  P2_QSFTBL7  ======================================================= */
+ #define R_ETHSW_P2_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
+ #define R_ETHSW_P2_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_P2_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
+ #define R_ETHSW_P2_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
+ #define R_ETHSW_P2_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
+ #define R_ETHSW_P2_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
+ #define R_ETHSW_P2_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
+ #define R_ETHSW_P2_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
+ #define R_ETHSW_P2_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
+ #define R_ETHSW_P2_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
+ #define R_ETHSW_P2_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_P2_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
+ #define R_ETHSW_P2_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  P2_QSMFC0  ======================================================= */
+ #define R_ETHSW_P2_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC1  ======================================================= */
+ #define R_ETHSW_P2_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC2  ======================================================= */
+ #define R_ETHSW_P2_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC3  ======================================================= */
+ #define R_ETHSW_P2_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC4  ======================================================= */
+ #define R_ETHSW_P2_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC5  ======================================================= */
+ #define R_ETHSW_P2_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC6  ======================================================= */
+ #define R_ETHSW_P2_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QSMFC7  ======================================================= */
+ #define R_ETHSW_P2_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
+ #define R_ETHSW_P2_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QMSPPC0  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC1  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC2  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC3  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC4  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC5  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC6  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSPPC7  ======================================================= */
+ #define R_ETHSW_P2_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC0  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC1  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC2  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC3  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC4  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC5  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC6  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  P2_QMSRPC7  ======================================================= */
+ #define R_ETHSW_P2_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
+ #define R_ETHSW_P2_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  P2_QGDPC0  ======================================================= */
+ #define R_ETHSW_P2_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC1  ======================================================= */
+ #define R_ETHSW_P2_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC2  ======================================================= */
+ #define R_ETHSW_P2_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC3  ======================================================= */
+ #define R_ETHSW_P2_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC4  ======================================================= */
+ #define R_ETHSW_P2_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC5  ======================================================= */
+ #define R_ETHSW_P2_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC6  ======================================================= */
+ #define R_ETHSW_P2_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QGDPC7  ======================================================= */
+ #define R_ETHSW_P2_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
+/* ======================================================  P2_QMDESC0  ======================================================= */
+ #define R_ETHSW_P2_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC1  ======================================================= */
+ #define R_ETHSW_P2_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC2  ======================================================= */
+ #define R_ETHSW_P2_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC3  ======================================================= */
+ #define R_ETHSW_P2_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC4  ======================================================= */
+ #define R_ETHSW_P2_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC5  ======================================================= */
+ #define R_ETHSW_P2_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC6  ======================================================= */
+ #define R_ETHSW_P2_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMDESC7  ======================================================= */
+ #define R_ETHSW_P2_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHSW_P2_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_P2_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
+ #define R_ETHSW_P2_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHSW_P2_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
+ #define R_ETHSW_P2_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ======================================================  P2_QMCBSC0  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC1  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC2  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC3  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC4  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC5  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC6  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCBSC7  ======================================================= */
+ #define R_ETHSW_P2_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
+/* ======================================================  P2_QMCIRC0  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC1  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC2  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC3  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC4  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC5  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC6  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* ======================================================  P2_QMCIRC7  ======================================================= */
+ #define R_ETHSW_P2_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
+ #define R_ETHSW_P2_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
+/* =======================================================  P2_QMGPC0  ======================================================= */
+ #define R_ETHSW_P2_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC1  ======================================================= */
+ #define R_ETHSW_P2_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC2  ======================================================= */
+ #define R_ETHSW_P2_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC3  ======================================================= */
+ #define R_ETHSW_P2_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC4  ======================================================= */
+ #define R_ETHSW_P2_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC5  ======================================================= */
+ #define R_ETHSW_P2_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC6  ======================================================= */
+ #define R_ETHSW_P2_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMGPC7  ======================================================= */
+ #define R_ETHSW_P2_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC0  ======================================================= */
+ #define R_ETHSW_P2_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC1  ======================================================= */
+ #define R_ETHSW_P2_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC2  ======================================================= */
+ #define R_ETHSW_P2_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC3  ======================================================= */
+ #define R_ETHSW_P2_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC4  ======================================================= */
+ #define R_ETHSW_P2_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC5  ======================================================= */
+ #define R_ETHSW_P2_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC6  ======================================================= */
+ #define R_ETHSW_P2_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  P2_QMRPC7  ======================================================= */
+ #define R_ETHSW_P2_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
+ #define R_ETHSW_P2_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
+/* =====================================================  STATN_STATUS  ====================================================== */
+ #define R_ETHSW_STATN_STATUS_BUSY_Pos                                    (0UL)          /*!< BUSY (Bit 0)                                          */
+ #define R_ETHSW_STATN_STATUS_BUSY_Msk                                    (0x1UL)        /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* =====================================================  STATN_CONFIG  ====================================================== */
+ #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Pos                           (1UL)          /*!< CLEAR_ON_READ (Bit 1)                                 */
+ #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Msk                           (0x2UL)        /*!< CLEAR_ON_READ (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_STATN_CONFIG_RESET_Pos                                   (31UL)         /*!< RESET (Bit 31)                                        */
+ #define R_ETHSW_STATN_CONFIG_RESET_Msk                                   (0x80000000UL) /*!< RESET (Bitfield-Mask: 0x01)                           */
+/* =====================================================  STATN_CONTROL  ===================================================== */
+ #define R_ETHSW_STATN_CONTROL_CHANMASK_Pos                               (0UL)          /*!< CHANMASK (Bit 0)                                      */
+ #define R_ETHSW_STATN_CONTROL_CHANMASK_Msk                               (0xfUL)        /*!< CHANMASK (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Pos                              (29UL)         /*!< CLEAR_PRE (Bit 29)                                    */
+ #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Msk                              (0x20000000UL) /*!< CLEAR_PRE (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Pos                              (31UL)         /*!< CMD_CLEAR (Bit 31)                                    */
+ #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Msk                              (0x80000000UL) /*!< CMD_CLEAR (Bitfield-Mask: 0x01)                       */
+/* ==================================================  STATN_CLEARVALUE_LO  ================================================== */
+ #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Pos              (0UL)          /*!< STATN_CLEARVALUE_LO (Bit 0)                           */
+ #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Msk              (0xffffffffUL) /*!< STATN_CLEARVALUE_LO (Bitfield-Mask: 0xffffffff) */
+/* ========================================================  ODISC0  ========================================================= */
+ #define R_ETHSW_ODISC0_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
+ #define R_ETHSW_ODISC0_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  ODISC1  ========================================================= */
+ #define R_ETHSW_ODISC1_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
+ #define R_ETHSW_ODISC1_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  ODISC2  ========================================================= */
+ #define R_ETHSW_ODISC2_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
+ #define R_ETHSW_ODISC2_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  ODISC3  ========================================================= */
+ #define R_ETHSW_ODISC3_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
+ #define R_ETHSW_ODISC3_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
+/* ======================================================  IDISC_VLAN0  ====================================================== */
+ #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
+ #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  IDISC_VLAN1  ====================================================== */
+ #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
+ #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  IDISC_VLAN2  ====================================================== */
+ #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
+ #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  IDISC_VLAN3  ====================================================== */
+ #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
+ #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  IDISC_UNTAGGED0  ==================================================== */
+ #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
+ #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  IDISC_UNTAGGED1  ==================================================== */
+ #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
+ #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  IDISC_UNTAGGED2  ==================================================== */
+ #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
+ #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  IDISC_UNTAGGED3  ==================================================== */
+ #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
+ #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  IDISC_BLOCKED0  ===================================================== */
+ #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
+ #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  IDISC_BLOCKED1  ===================================================== */
+ #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
+ #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  IDISC_BLOCKED2  ===================================================== */
+ #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
+ #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
+/* ====================================================  IDISC_BLOCKED3  ===================================================== */
+ #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
+ #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
+/* ======================================================  IDISC_ANY0  ======================================================= */
+ #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
+ #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  IDISC_ANY1  ======================================================= */
+ #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
+ #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  IDISC_ANY2  ======================================================= */
+ #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
+ #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  IDISC_ANY3  ======================================================= */
+ #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
+ #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
+/* =====================================================  IDISC_SRCFLT0  ===================================================== */
+ #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
+ #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
+/* =====================================================  IDISC_SRCFLT1  ===================================================== */
+ #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
+ #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
+/* =====================================================  IDISC_SRCFLT2  ===================================================== */
+ #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
+ #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  TX_HOLD_REQ_CNT0  ==================================================== */
+ #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
+ #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
+/* ===================================================  TX_HOLD_REQ_CNT1  ==================================================== */
+ #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
+ #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
+/* ===================================================  TX_HOLD_REQ_CNT2  ==================================================== */
+ #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
+ #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
+/* =====================================================  TX_FRAG_CNT0  ====================================================== */
+ #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  TX_FRAG_CNT1  ====================================================== */
+ #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  TX_FRAG_CNT2  ====================================================== */
+ #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  RX_FRAG_CNT0  ====================================================== */
+ #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  RX_FRAG_CNT1  ====================================================== */
+ #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  RX_FRAG_CNT2  ====================================================== */
+ #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
+ #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
+/* ====================================================  RX_ASSY_OK_CNT0  ==================================================== */
+ #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  RX_ASSY_OK_CNT1  ==================================================== */
+ #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  RX_ASSY_OK_CNT2  ==================================================== */
+ #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  RX_ASSY_ERR_CNT0  ==================================================== */
+ #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
+ #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
+/* ===================================================  RX_ASSY_ERR_CNT1  ==================================================== */
+ #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
+ #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
+/* ===================================================  RX_ASSY_ERR_CNT2  ==================================================== */
+ #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
+ #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
+/* ====================================================  RX_SMD_ERR_CNT0  ==================================================== */
+ #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
+/* ====================================================  RX_SMD_ERR_CNT1  ==================================================== */
+ #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
+/* ====================================================  RX_SMD_ERR_CNT2  ==================================================== */
+ #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
+ #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
+/* ===================================================  TX_VERIFY_OK_CNT0  =================================================== */
+ #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ===================================================  TX_VERIFY_OK_CNT1  =================================================== */
+ #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ===================================================  TX_VERIFY_OK_CNT2  =================================================== */
+ #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ==================================================  TX_RESPONSE_OK_CNT0  ================================================== */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  TX_RESPONSE_OK_CNT1  ================================================== */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  TX_RESPONSE_OK_CNT2  ================================================== */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ===================================================  RX_VERIFY_OK_CNT0  =================================================== */
+ #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ===================================================  RX_VERIFY_OK_CNT1  =================================================== */
+ #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ===================================================  RX_VERIFY_OK_CNT2  =================================================== */
+ #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
+ #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
+/* ==================================================  RX_RESPONSE_OK_CNT0  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  RX_RESPONSE_OK_CNT1  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  RX_RESPONSE_OK_CNT2  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
+ #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
+/* ==================================================  RX_VERIFY_BAD_CNT0  =================================================== */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
+/* ==================================================  RX_VERIFY_BAD_CNT1  =================================================== */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
+/* ==================================================  RX_VERIFY_BAD_CNT2  =================================================== */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
+ #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
+/* =================================================  RX_RESPONSE_BAD_CNT0  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
+/* =================================================  RX_RESPONSE_BAD_CNT1  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
+/* =================================================  RX_RESPONSE_BAD_CNT2  ================================================== */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
+ #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
+/* =====================================================  MMCTL_OUT_CT  ====================================================== */
+ #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Pos                              (0UL)          /*!< CT_OVR_ENA (Bit 0)                                    */
+ #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Msk                              (0x7UL)        /*!< CT_OVR_ENA (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Pos                                  (16UL)         /*!< CT_OVR (Bit 16)                                       */
+ #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Msk                                  (0x70000UL)    /*!< CT_OVR (Bitfield-Mask: 0x07)                          */
+/* ==================================================  MMCTL_CTFL_P0_3_ENA  ================================================== */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Pos                      (0UL)          /*!< CTFL_P0_ENA (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Msk                      (0xffUL)       /*!< CTFL_P0_ENA (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Pos                      (8UL)          /*!< CTFL_P1_ENA (Bit 8)                                   */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Msk                      (0xff00UL)     /*!< CTFL_P1_ENA (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Pos                      (16UL)         /*!< CTFL_P2_ENA (Bit 16)                                  */
+ #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Msk                      (0xff0000UL)   /*!< CTFL_P2_ENA (Bitfield-Mask: 0xff)                     */
+/* ==============================================  MMCTL_YELLOW_BYTE_LENGTH_P  =============================================== */
+ #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Pos                (2UL)          /*!< YELLOW_LEN (Bit 2)                                    */
+ #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Msk                (0xfffcUL)     /*!< YELLOW_LEN (Bitfield-Mask: 0x3fff)                   */
+ #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Pos                   (16UL)         /*!< YLEN_EN (Bit 16)                                      */
+ #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Msk                   (0x10000UL)    /*!< YLEN_EN (Bitfield-Mask: 0x01)                         */
+/* ====================================================  MMCTL_POOL0_CTR  ==================================================== */
+ #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Pos                                (0UL)          /*!< CELLS (Bit 0)                                         */
+ #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Msk                                (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
+ #define R_ETHSW_MMCTL_POOL0_CTR_USED_Pos                                 (16UL)         /*!< USED (Bit 16)                                         */
+ #define R_ETHSW_MMCTL_POOL0_CTR_USED_Msk                                 (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
+/* ====================================================  MMCTL_POOL1_CTR  ==================================================== */
+ #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Pos                                (0UL)          /*!< CELLS (Bit 0)                                         */
+ #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Msk                                (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
+ #define R_ETHSW_MMCTL_POOL1_CTR_USED_Pos                                 (16UL)         /*!< USED (Bit 16)                                         */
+ #define R_ETHSW_MMCTL_POOL1_CTR_USED_Msk                                 (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
+/* ===================================================  MMCTL_POOL_GLOBAL  =================================================== */
+ #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Pos                              (0UL)          /*!< CELLS (Bit 0)                                         */
+ #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Msk                              (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
+ #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Pos                               (16UL)         /*!< USED (Bit 16)                                         */
+ #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Msk                               (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
+/* ===================================================  MMCTL_POOL_STATUS  =================================================== */
+ #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Pos                         (0UL)          /*!< QUEUE_FULL (Bit 0)                                    */
+ #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Msk                         (0xffUL)       /*!< QUEUE_FULL (Bitfield-Mask: 0xff)                      */
+/* ====================================================  MMCTL_POOL_QMAP  ==================================================== */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Pos                               (0UL)          /*!< Q0_MAP (Bit 0)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Msk                               (0x1UL)        /*!< Q0_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Pos                               (3UL)          /*!< Q0_ENA (Bit 3)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Msk                               (0x8UL)        /*!< Q0_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Pos                               (4UL)          /*!< Q1_MAP (Bit 4)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Msk                               (0x10UL)       /*!< Q1_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Pos                               (7UL)          /*!< Q1_ENA (Bit 7)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Msk                               (0x80UL)       /*!< Q1_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Pos                               (8UL)          /*!< Q2_MAP (Bit 8)                                        */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Msk                               (0x100UL)      /*!< Q2_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Pos                               (11UL)         /*!< Q2_ENA (Bit 11)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Msk                               (0x800UL)      /*!< Q2_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Pos                               (12UL)         /*!< Q3_MAP (Bit 12)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Msk                               (0x1000UL)     /*!< Q3_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Pos                               (15UL)         /*!< Q3_ENA (Bit 15)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Msk                               (0x8000UL)     /*!< Q3_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Pos                               (16UL)         /*!< Q4_MAP (Bit 16)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Msk                               (0x10000UL)    /*!< Q4_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Pos                               (19UL)         /*!< Q4_ENA (Bit 19)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Msk                               (0x80000UL)    /*!< Q4_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Pos                               (20UL)         /*!< Q5_MAP (Bit 20)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Msk                               (0x100000UL)   /*!< Q5_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Pos                               (23UL)         /*!< Q5_ENA (Bit 23)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Msk                               (0x800000UL)   /*!< Q5_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Pos                               (24UL)         /*!< Q6_MAP (Bit 24)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Msk                               (0x1000000UL)  /*!< Q6_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Pos                               (27UL)         /*!< Q6_ENA (Bit 27)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Msk                               (0x8000000UL)  /*!< Q6_ENA (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Pos                               (28UL)         /*!< Q7_MAP (Bit 28)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Msk                               (0x10000000UL) /*!< Q7_MAP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Pos                               (31UL)         /*!< Q7_ENA (Bit 31)                                       */
+ #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Msk                               (0x80000000UL) /*!< Q7_ENA (Bitfield-Mask: 0x01)                          */
+/* ======================================================  MMCTL_QGATE  ====================================================== */
+ #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Pos                                (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Msk                                (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Pos                               (16UL)         /*!< QUEUE_GATE (Bit 16)                                   */
+ #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Msk                               (0xffff0000UL) /*!< QUEUE_GATE (Bitfield-Mask: 0xffff)                    */
+/* ======================================================  MMCTL_QTRIG  ====================================================== */
+ #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Pos                                (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Msk                                (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Pos                               (16UL)         /*!< QUEUE_TRIG (Bit 16)                                   */
+ #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Msk                               (0xff0000UL)   /*!< QUEUE_TRIG (Bitfield-Mask: 0xff)                      */
+/* =====================================================  MMCTL_QFLUSH  ====================================================== */
+ #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Pos                               (0UL)          /*!< PORT_MASK (Bit 0)                                     */
+ #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Msk                               (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Pos                              (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
+ #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Msk                              (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_MMCTL_QFLUSH_ACTION_Pos                                  (24UL)         /*!< ACTION (Bit 24)                                       */
+ #define R_ETHSW_MMCTL_QFLUSH_ACTION_Msk                                  (0x3000000UL)  /*!< ACTION (Bitfield-Mask: 0x03)                          */
+/* ===============================================  MMCTL_QCLOSED_STATUS_P0_3  =============================================== */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Pos                  (0UL)          /*!< P0_STATUS (Bit 0)                                     */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Msk                  (0xffUL)       /*!< P0_STATUS (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Pos                  (8UL)          /*!< P1_STATUS (Bit 8)                                     */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Msk                  (0xff00UL)     /*!< P1_STATUS (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Pos                  (16UL)         /*!< P2_STATUS (Bit 16)                                    */
+ #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Msk                  (0xff0000UL)   /*!< P2_STATUS (Bitfield-Mask: 0xff)                      */
+/* ==================================================  MMCTL_1FRAME_MODE_P  ================================================== */
+ #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Pos                     (0UL)          /*!< Q_1FRAME_ENA (Bit 0)                                  */
+ #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Msk                     (0xffUL)       /*!< Q_1FRAME_ENA (Bitfield-Mask: 0xff)                    */
+ #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Pos                        (16UL)         /*!< Q_BUF_ENA (Bit 16)                                    */
+ #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Msk                        (0xff0000UL)   /*!< Q_BUF_ENA (Bitfield-Mask: 0xff)                       */
+/* ================================================  MMCTL_P0_3_QUEUE_STATUS  ================================================ */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Pos                  (0UL)          /*!< P0_Q_STATUS (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Msk                  (0xffUL)       /*!< P0_Q_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Pos                  (8UL)          /*!< P1_Q_STATUS (Bit 8)                                   */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Msk                  (0xff00UL)     /*!< P1_Q_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Pos                  (16UL)         /*!< P2_Q_STATUS (Bit 16)                                  */
+ #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Msk                  (0xff0000UL)   /*!< P2_Q_STATUS (Bitfield-Mask: 0xff)                    */
+/* ================================================  MMCTL_P0_3_FLUSH_STATUS  ================================================ */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Pos                  (0UL)          /*!< P0_F_STATUS (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Msk                  (0xffUL)       /*!< P0_F_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Pos                  (8UL)          /*!< P1_F_STATUS (Bit 8)                                   */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Msk                  (0xff00UL)     /*!< P1_F_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Pos                  (16UL)         /*!< P2_F_STATUS (Bit 16)                                  */
+ #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Msk                  (0xff0000UL)   /*!< P2_F_STATUS (Bitfield-Mask: 0xff)                    */
+/* ================================================  MMCTL_DLY_QTRIGGER_CTRL  ================================================ */
+ #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Pos                   (0UL)          /*!< DELAY_TIME (Bit 0)                                    */
+ #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Msk                   (0x3fffffffUL) /*!< DELAY_TIME (Bitfield-Mask: 0x3fffffff)              */
+ #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Pos                    (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
+ #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Msk                    (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                      */
+/* =================================================  MMCTL_PREEMPT_QUEUES  ================================================== */
+ #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Pos                     (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Msk                     (0xffUL)       /*!< PREEMPT_ENA (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Pos               (8UL)          /*!< PREEMPT_ON_QCLOSE (Bit 8)                             */
+ #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Msk               (0xff00UL)     /*!< PREEMPT_ON_QCLOSE (Bitfield-Mask: 0xff)             */
+/* ==================================================  MMCTL_HOLD_CONTROL  =================================================== */
+ #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Pos                  (0UL)          /*!< Q_HOLD_REQ_FORCE (Bit 0)                              */
+ #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Msk                  (0x7UL)        /*!< Q_HOLD_REQ_FORCE (Bitfield-Mask: 0x07)                */
+ #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Pos                (16UL)         /*!< Q_HOLD_REQ_RELEASE (Bit 16)                           */
+ #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Msk                (0x70000UL)    /*!< Q_HOLD_REQ_RELEASE (Bitfield-Mask: 0x07)            */
+/* =================================================  MMCTL_PREEMPT_STATUS  ================================================== */
+ #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Pos                   (0UL)          /*!< PREEMPT_STATE (Bit 0)                                 */
+ #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Msk                   (0x7UL)        /*!< PREEMPT_STATE (Bitfield-Mask: 0x07)                   */
+ #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Pos                  (16UL)         /*!< HOLD_REQ_STATE (Bit 16)                               */
+ #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Msk                  (0x70000UL)    /*!< HOLD_REQ_STATE (Bitfield-Mask: 0x07)                  */
+/* ===================================================  MMCTL_CQF_CTRL_P  ==================================================== */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Pos                        (0UL)          /*!< PRIO_ENABLE0 (Bit 0)                                  */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Msk                        (0xffUL)       /*!< PRIO_ENABLE0 (Bitfield-Mask: 0xff)                    */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Pos                          (8UL)          /*!< QUEUE_SEL0 (Bit 8)                                    */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Msk                          (0x700UL)      /*!< QUEUE_SEL0 (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Pos                           (11UL)         /*!< GATE_SEL0 (Bit 11)                                    */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Msk                           (0x3800UL)     /*!< GATE_SEL0 (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Pos                            (14UL)         /*!< USE_SOP0 (Bit 14)                                     */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Msk                            (0x4000UL)     /*!< USE_SOP0 (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Pos                            (15UL)         /*!< REF_SEL0 (Bit 15)                                     */
+ #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Msk                            (0x8000UL)     /*!< REF_SEL0 (Bitfield-Mask: 0x01)                        */
+/* ==============================================  MMCTL_P0_3_QCLOSED_NONEMPTY  ============================================== */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Pos              (0UL)          /*!< P0_Q_STATUS (Bit 0)                                   */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Msk              (0xffUL)       /*!< P0_Q_STATUS (Bitfield-Mask: 0xff)                    */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Pos              (8UL)          /*!< P1_Q_STATUS (Bit 8)                                   */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Msk              (0xff00UL)     /*!< P1_Q_STATUS (Bitfield-Mask: 0xff)                  */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Pos              (16UL)         /*!< P2_Q_STATUS (Bit 16)                                  */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Msk              (0xff0000UL)   /*!< P2_Q_STATUS (Bitfield-Mask: 0xff)                */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Pos              (24UL)         /*!< P3_Q_STATUS (Bit 24)                                  */
+ #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Msk              (0xff000000UL) /*!< P3_Q_STATUS (Bitfield-Mask: 0xff)              */
+/* ==================================================  MMCTL_PREEMPT_EXTRA  ================================================== */
+ #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Pos                     (0UL)          /*!< MIN_PFRM_ADJ (Bit 0)                                  */
+ #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Msk                     (0xfUL)        /*!< MIN_PFRM_ADJ (Bitfield-Mask: 0x0f)                    */
+ #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Pos                    (4UL)          /*!< LAST_PFRM_ADJ (Bit 4)                                 */
+ #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Msk                    (0xf0UL)       /*!< LAST_PFRM_ADJ (Bitfield-Mask: 0x0f)                   */
+/* ======================================================  DLR_CONTROL  ====================================================== */
+ #define R_ETHSW_DLR_CONTROL_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ETHSW_DLR_CONTROL_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Pos                                (1UL)          /*!< AUTOFLUSH (Bit 1)                                     */
+ #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Msk                                (0x2UL)        /*!< AUTOFLUSH (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Pos                          (2UL)          /*!< LOOP_FILTER_ENA (Bit 2)                               */
+ #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Msk                          (0x4UL)        /*!< LOOP_FILTER_ENA (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Pos                             (4UL)          /*!< IGNORE_INVTM (Bit 4)                                  */
+ #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Msk                             (0x10UL)       /*!< IGNORE_INVTM (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_DLR_CONTROL_US_TIME_Pos                                  (8UL)          /*!< US_TIME (Bit 8)                                       */
+ #define R_ETHSW_DLR_CONTROL_US_TIME_Msk                                  (0xfff00UL)    /*!< US_TIME (Bitfield-Mask: 0xfff)                        */
+/* ======================================================  DLR_STATUS  ======================================================= */
+ #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Pos                            (0UL)          /*!< LastBcnRcvPort (Bit 0)                                */
+ #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Msk                            (0x3UL)        /*!< LastBcnRcvPort (Bitfield-Mask: 0x03)                  */
+ #define R_ETHSW_DLR_STATUS_NODE_STATE_Pos                                (8UL)          /*!< NODE_STATE (Bit 8)                                    */
+ #define R_ETHSW_DLR_STATUS_NODE_STATE_Msk                                (0xff00UL)     /*!< NODE_STATE (Bitfield-Mask: 0xff)                      */
+ #define R_ETHSW_DLR_STATUS_LINK_STATUS_Pos                               (16UL)         /*!< LINK_STATUS (Bit 16)                                  */
+ #define R_ETHSW_DLR_STATUS_LINK_STATUS_Msk                               (0x30000UL)    /*!< LINK_STATUS (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_DLR_STATUS_TOPOLOGY_Pos                                  (24UL)         /*!< TOPOLOGY (Bit 24)                                     */
+ #define R_ETHSW_DLR_STATUS_TOPOLOGY_Msk                                  (0xff000000UL) /*!< TOPOLOGY (Bitfield-Mask: 0xff)                        */
+/* ======================================================  DLR_ETH_TYP  ====================================================== */
+ #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Pos                              (0UL)          /*!< DLR_ETH_TYP (Bit 0)                                   */
+ #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Msk                              (0xffffUL)     /*!< DLR_ETH_TYP (Bitfield-Mask: 0xffff)                   */
+/* ====================================================  DLR_IRQ_CONTROL  ==================================================== */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Pos                   (0UL)          /*!< IRQ_state_chng_ena (Bit 0)                            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Msk                   (0x1UL)        /*!< IRQ_state_chng_ena (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Pos                (1UL)          /*!< IRQ_flush_macaddr_ena (Bit 1)                         */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Msk                (0x2UL)        /*!< IRQ_flush_macaddr_ena (Bitfield-Mask: 0x01)           */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Pos                  (2UL)          /*!< IRQ_stop_nbchk0_ena (Bit 2)                           */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Msk                  (0x4UL)        /*!< IRQ_stop_nbchk0_ena (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Pos                  (3UL)          /*!< IRQ_stop_nbchk1_ena (Bit 3)                           */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Msk                  (0x8UL)        /*!< IRQ_stop_nbchk1_ena (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Pos                 (4UL)          /*!< IRQ_bec_tmr0_exp_ena (Bit 4)                          */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Msk                 (0x10UL)       /*!< IRQ_bec_tmr0_exp_ena (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Pos                 (5UL)          /*!< IRQ_bec_tmr1_exp_ena (Bit 5)                          */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Msk                 (0x20UL)       /*!< IRQ_bec_tmr1_exp_ena (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Pos                    (6UL)          /*!< IRQ_supr_chng_ena (Bit 6)                             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Msk                    (0x40UL)       /*!< IRQ_supr_chng_ena (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Pos                   (7UL)          /*!< IRQ_link_chng0_ena (Bit 7)                            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Msk                   (0x80UL)       /*!< IRQ_link_chng0_ena (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Pos                   (8UL)          /*!< IRQ_link_chng1_ena (Bit 8)                            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Msk                   (0x100UL)      /*!< IRQ_link_chng1_ena (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Pos                   (9UL)          /*!< IRQ_sup_ignord_ena (Bit 9)                            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Msk                   (0x200UL)      /*!< IRQ_sup_ignord_ena (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Pos                 (10UL)         /*!< IRQ_ip_addr_chng_ena (Bit 10)                         */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Msk                 (0x400UL)      /*!< IRQ_ip_addr_chng_ena (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Pos                  (11UL)         /*!< IRQ_invalid_tmr_ena (Bit 11)                          */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Msk                  (0x800UL)      /*!< IRQ_invalid_tmr_ena (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Pos                     (12UL)         /*!< IRQ_bec_rcv0_ena (Bit 12)                             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Msk                     (0x1000UL)     /*!< IRQ_bec_rcv0_ena (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Pos                     (13UL)         /*!< IRQ_bec_rcv1_ena (Bit 13)                             */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Msk                     (0x2000UL)     /*!< IRQ_bec_rcv1_ena (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Pos                       (14UL)         /*!< IRQ_frm_dscrd0 (Bit 14)                               */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Msk                       (0x4000UL)     /*!< IRQ_frm_dscrd0 (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Pos                       (15UL)         /*!< IRQ_frm_dscrd1 (Bit 15)                               */
+ #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Msk                       (0x8000UL)     /*!< IRQ_frm_dscrd1 (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Pos                           (29UL)         /*!< low_int_en (Bit 29)                                   */
+ #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Msk                           (0x20000000UL) /*!< low_int_en (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Pos                            (30UL)         /*!< atomic_OR (Bit 30)                                    */
+ #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Msk                            (0x40000000UL) /*!< atomic_OR (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Pos                           (31UL)         /*!< atomic_AND (Bit 31)                                   */
+ #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Msk                           (0x80000000UL) /*!< atomic_AND (Bitfield-Mask: 0x01)                      */
+/* ===================================================  DLR_IRQ_STAT_ACK  ==================================================== */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Pos              (0UL)          /*!< state_chng_IRQ_pending (Bit 0)                        */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Msk              (0x1UL)        /*!< state_chng_IRQ_pending (Bitfield-Mask: 0x01)          */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Pos                   (1UL)          /*!< flush_IRQ_pending (Bit 1)                             */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Msk                   (0x2UL)        /*!< flush_IRQ_pending (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Pos                  (2UL)          /*!< nbchk0_IRQ_pending (Bit 2)                            */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Msk                  (0x4UL)        /*!< nbchk0_IRQ_pending (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Pos                  (3UL)          /*!< nbchk1_IRQ_pending (Bit 3)                            */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Msk                  (0x8UL)        /*!< nbchk1_IRQ_pending (Bitfield-Mask: 0x01)              */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Pos                (4UL)          /*!< bec_tmr0_IRQ_pending (Bit 4)                          */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Msk                (0x10UL)       /*!< bec_tmr0_IRQ_pending (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Pos                (5UL)          /*!< bec_tmr1_IRQ_pending (Bit 5)                          */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Msk                (0x20UL)       /*!< bec_tmr1_IRQ_pending (Bitfield-Mask: 0x01)            */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Pos               (6UL)          /*!< supr_chng_IRQ_pending (Bit 6)                         */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Msk               (0x40UL)       /*!< supr_chng_IRQ_pending (Bitfield-Mask: 0x01)           */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Pos                   (7UL)          /*!< Link0_IRQ_pending (Bit 7)                             */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Msk                   (0x80UL)       /*!< Link0_IRQ_pending (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Pos                   (8UL)          /*!< Link1_IRQ_pending (Bit 8)                             */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Msk                   (0x100UL)      /*!< Link1_IRQ_pending (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Pos              (9UL)          /*!< sup_ignord_IRQ_pending (Bit 9)                        */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Msk              (0x200UL)      /*!< sup_ignord_IRQ_pending (Bitfield-Mask: 0x01)        */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Pos                 (10UL)         /*!< ip_chng_IRQ_pending (Bit 10)                          */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Msk                 (0x400UL)      /*!< ip_chng_IRQ_pending (Bitfield-Mask: 0x01)             */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Pos             (11UL)         /*!< invalid_tmr_IRQ_pending (Bit 11)                      */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Msk             (0x800UL)      /*!< invalid_tmr_IRQ_pending (Bitfield-Mask: 0x01)      */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Pos                (12UL)         /*!< bec_rcv0_IRQ_pending (Bit 12)                         */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Msk                (0x1000UL)     /*!< bec_rcv0_IRQ_pending (Bitfield-Mask: 0x01)           */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Pos                (13UL)         /*!< bec_rcv1_IRQ_pending (Bit 13)                         */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Msk                (0x2000UL)     /*!< bec_rcv1_IRQ_pending (Bitfield-Mask: 0x01)           */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Pos              (14UL)         /*!< frm_dscrd0_IRQ_pending (Bit 14)                       */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Msk              (0x4000UL)     /*!< frm_dscrd0_IRQ_pending (Bitfield-Mask: 0x01)       */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Pos              (15UL)         /*!< frm_dscrd1_IRQ_pending (Bit 15)                       */
+ #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Msk              (0x8000UL)     /*!< frm_dscrd1_IRQ_pending (Bitfield-Mask: 0x01)       */
+/* =====================================================  DLR_LOC_MAClo  ===================================================== */
+ #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Pos                                (0UL)          /*!< LOC_MAC (Bit 0)                                       */
+ #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Msk                                (0xffffffffUL) /*!< LOC_MAC (Bitfield-Mask: 0xffffffff)                   */
+/* =====================================================  DLR_LOC_MAChi  ===================================================== */
+ #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Pos                                (0UL)          /*!< LOC_MAC (Bit 0)                                       */
+ #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Msk                                (0xffffUL)     /*!< LOC_MAC (Bitfield-Mask: 0xffff)                       */
+/* ====================================================  DLR_SUPR_MAClo  ===================================================== */
+ #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Pos                              (0UL)          /*!< SUPR_MAC (Bit 0)                                      */
+ #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Msk                              (0xffffffffUL) /*!< SUPR_MAC (Bitfield-Mask: 0xffffffff)                  */
+/* ====================================================  DLR_SUPR_MAChi  ===================================================== */
+ #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Pos                              (0UL)          /*!< SUPR_MAC (Bit 0)                                      */
+ #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Msk                              (0xffffUL)     /*!< SUPR_MAC (Bitfield-Mask: 0xffff)                      */
+ #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Pos                                 (16UL)         /*!< PRECE (Bit 16)                                        */
+ #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Msk                                 (0xff0000UL)   /*!< PRECE (Bitfield-Mask: 0xff)                           */
+/* ====================================================  DLR_STATE_VLAN  ===================================================== */
+ #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Pos                              (0UL)          /*!< RINGSTAT (Bit 0)                                      */
+ #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Msk                              (0xffUL)       /*!< RINGSTAT (Bitfield-Mask: 0xff)                        */
+ #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Pos                             (8UL)          /*!< VLANVALID (Bit 8)                                     */
+ #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Msk                             (0x100UL)      /*!< VLANVALID (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Pos                              (16UL)         /*!< VLANINFO (Bit 16)                                     */
+ #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Msk                              (0xffff0000UL) /*!< VLANINFO (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  DLR_BEC_TMOUT  ===================================================== */
+ #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Pos                              (0UL)          /*!< BEC_TMOUT (Bit 0)                                     */
+ #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Msk                              (0xffffffffUL) /*!< BEC_TMOUT (Bitfield-Mask: 0xffffffff)                 */
+/* ====================================================  DLR_BEC_INTRVL  ===================================================== */
+ #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Pos                            (0UL)          /*!< BEC_INTRVL (Bit 0)                                    */
+ #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Msk                            (0xffffffffUL) /*!< BEC_INTRVL (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  DLR_SUPR_IPADR  ===================================================== */
+ #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Pos                            (0UL)          /*!< SUPR_IPADR (Bit 0)                                    */
+ #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Msk                            (0xffffffffUL) /*!< SUPR_IPADR (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  DLR_ETH_STYP_VER  ==================================================== */
+ #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Pos                             (0UL)          /*!< SUBTYPE (Bit 0)                                       */
+ #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Msk                             (0xffUL)       /*!< SUBTYPE (Bitfield-Mask: 0xff)                         */
+ #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Pos                             (8UL)          /*!< PROTVER (Bit 8)                                       */
+ #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Msk                             (0xff00UL)     /*!< PROTVER (Bitfield-Mask: 0xff)                         */
+ #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Pos                               (16UL)         /*!< SPORT (Bit 16)                                        */
+ #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Msk                               (0xff0000UL)   /*!< SPORT (Bitfield-Mask: 0xff)                           */
+/* =====================================================  DLR_INV_TMOUT  ===================================================== */
+ #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Pos                              (0UL)          /*!< INV_TMOUT (Bit 0)                                     */
+ #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Msk                              (0xffffffffUL) /*!< INV_TMOUT (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  DLR_SEQ_ID  ======================================================= */
+ #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Pos                                    (0UL)          /*!< SEQ_ID (Bit 0)                                        */
+ #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Msk                                    (0xffffffffUL) /*!< SEQ_ID (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  DLR_DSTlo  ======================================================= */
+ #define R_ETHSW_DLR_DSTlo_DLR_DST_Pos                                    (0UL)          /*!< DLR_DST (Bit 0)                                       */
+ #define R_ETHSW_DLR_DSTlo_DLR_DST_Msk                                    (0xffffffffUL) /*!< DLR_DST (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  DLR_DSThi  ======================================================= */
+ #define R_ETHSW_DLR_DSThi_DLR_DST_Pos                                    (0UL)          /*!< DLR_DST (Bit 0)                                       */
+ #define R_ETHSW_DLR_DSThi_DLR_DST_Msk                                    (0xffffUL)     /*!< DLR_DST (Bitfield-Mask: 0xffff)                       */
+/* =====================================================  DLR_RX_STAT0  ====================================================== */
+ #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Pos                                (0UL)          /*!< RX_STAT0 (Bit 0)                                      */
+ #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Msk                                (0xffffffffUL) /*!< RX_STAT0 (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  DLR_RX_ERR_STAT0  ==================================================== */
+ #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Pos                        (0UL)          /*!< RX_ERR_STAT0 (Bit 0)                                  */
+ #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Msk                        (0xffffffffUL) /*!< RX_ERR_STAT0 (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  DLR_RX_LF_STAT0  ==================================================== */
+ #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Pos                          (0UL)          /*!< RX_LF_STAT0 (Bit 0)                                   */
+ #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Msk                          (0xffUL)       /*!< RX_LF_STAT0 (Bitfield-Mask: 0xff)                     */
+/* =====================================================  DLR_RX_STAT1  ====================================================== */
+ #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Pos                                (0UL)          /*!< RX_STAT1 (Bit 0)                                      */
+ #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Msk                                (0xffffffffUL) /*!< RX_STAT1 (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  DLR_RX_ERR_STAT1  ==================================================== */
+ #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Pos                        (0UL)          /*!< RX_ERR_STAT1 (Bit 0)                                  */
+ #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Msk                        (0xffffffffUL) /*!< RX_ERR_STAT1 (Bitfield-Mask: 0xffffffff)              */
+/* ====================================================  DLR_RX_LF_STAT1  ==================================================== */
+ #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Pos                          (0UL)          /*!< RX_LF_STAT1 (Bit 0)                                   */
+ #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Msk                          (0xffUL)       /*!< RX_LF_STAT1 (Bitfield-Mask: 0xff)                     */
+/* ======================================================  PRP_CONFIG  ======================================================= */
+ #define R_ETHSW_PRP_CONFIG_PRP_ENA_Pos                                   (0UL)          /*!< PRP_ENA (Bit 0)                                       */
+ #define R_ETHSW_PRP_CONFIG_PRP_ENA_Msk                                   (0x1UL)        /*!< PRP_ENA (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Pos                             (1UL)          /*!< RX_DUP_ACCEPT (Bit 1)                                 */
+ #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Msk                             (0x2UL)        /*!< RX_DUP_ACCEPT (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Pos                             (2UL)          /*!< RX_REMOVE_RCT (Bit 2)                                 */
+ #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Msk                             (0x4UL)        /*!< RX_REMOVE_RCT (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Pos                               (3UL)          /*!< TX_RCT_MODE (Bit 3)                                   */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Msk                               (0x18UL)       /*!< TX_RCT_MODE (Bitfield-Mask: 0x03)                     */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Pos                          (5UL)          /*!< TX_RCT_BROADCAST (Bit 5)                              */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Msk                          (0x20UL)       /*!< TX_RCT_BROADCAST (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Pos                          (6UL)          /*!< TX_RCT_MULTICAST (Bit 6)                              */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Msk                          (0x40UL)       /*!< TX_RCT_MULTICAST (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Pos                            (7UL)          /*!< TX_RCT_UNKNOWN (Bit 7)                                */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Msk                            (0x80UL)       /*!< TX_RCT_UNKNOWN (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Pos                               (8UL)          /*!< TX_RCT_1588 (Bit 8)                                   */
+ #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Msk                               (0x100UL)      /*!< TX_RCT_1588 (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Pos                           (9UL)          /*!< RCT_LEN_CHK_DIS (Bit 9)                               */
+ #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Msk                           (0x200UL)      /*!< RCT_LEN_CHK_DIS (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Pos                               (16UL)         /*!< PRP_AGE_ENA (Bit 16)                                  */
+ #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Msk                               (0x10000UL)    /*!< PRP_AGE_ENA (Bitfield-Mask: 0x01)                     */
+/* =======================================================  PRP_GROUP  ======================================================= */
+ #define R_ETHSW_PRP_GROUP_PRP_GROUP_Pos                                  (0UL)          /*!< PRP_GROUP (Bit 0)                                     */
+ #define R_ETHSW_PRP_GROUP_PRP_GROUP_Msk                                  (0x7UL)        /*!< PRP_GROUP (Bitfield-Mask: 0x07)                       */
+ #define R_ETHSW_PRP_GROUP_LANB_MASK_Pos                                  (16UL)         /*!< LANB_MASK (Bit 16)                                    */
+ #define R_ETHSW_PRP_GROUP_LANB_MASK_Msk                                  (0x70000UL)    /*!< LANB_MASK (Bitfield-Mask: 0x07)                       */
+/* ======================================================  PRP_SUFFIX  ======================================================= */
+ #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Pos                                (0UL)          /*!< PRP_SUFFIX (Bit 0)                                    */
+ #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Msk                                (0xffffUL)     /*!< PRP_SUFFIX (Bitfield-Mask: 0xffff)                    */
+/* =======================================================  PRP_LANID  ======================================================= */
+ #define R_ETHSW_PRP_LANID_LANAID_Pos                                     (0UL)          /*!< LANAID (Bit 0)                                        */
+ #define R_ETHSW_PRP_LANID_LANAID_Msk                                     (0xfUL)        /*!< LANAID (Bitfield-Mask: 0x0f)                          */
+ #define R_ETHSW_PRP_LANID_LANBID_Pos                                     (4UL)          /*!< LANBID (Bit 4)                                        */
+ #define R_ETHSW_PRP_LANID_LANBID_Msk                                     (0xf0UL)       /*!< LANBID (Bitfield-Mask: 0x0f)                          */
+/* =========================================================  DUP_W  ========================================================= */
+ #define R_ETHSW_DUP_W_DUP_W_Pos                                          (0UL)          /*!< DUP_W (Bit 0)                                         */
+ #define R_ETHSW_DUP_W_DUP_W_Msk                                          (0xffUL)       /*!< DUP_W (Bitfield-Mask: 0xff)                           */
+/* ======================================================  PRP_AGETIME  ====================================================== */
+ #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Pos                              (0UL)          /*!< PRP_AGETIME (Bit 0)                                   */
+ #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Msk                              (0xffffffUL)   /*!< PRP_AGETIME (Bitfield-Mask: 0xffffff)                 */
+/* ====================================================  PRP_IRQ_CONTROL  ==================================================== */
+ #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Pos                           (0UL)          /*!< MEMTOOLATE (Bit 0)                                    */
+ #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Msk                           (0x1UL)        /*!< MEMTOOLATE (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Pos                             (1UL)          /*!< WRONGLAN (Bit 1)                                      */
+ #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Msk                             (0x2UL)        /*!< WRONGLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Pos                             (2UL)          /*!< OUTOFSEQ (Bit 2)                                      */
+ #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Msk                             (0x4UL)        /*!< OUTOFSEQ (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Pos                           (3UL)          /*!< SEQMISSING (Bit 3)                                    */
+ #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Msk                           (0x8UL)        /*!< SEQMISSING (Bitfield-Mask: 0x01)                      */
+/* ===================================================  PRP_IRQ_STAT_ACK  ==================================================== */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Pos                          (0UL)          /*!< MEMTOOLATE (Bit 0)                                    */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Msk                          (0x1UL)        /*!< MEMTOOLATE (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Pos                            (1UL)          /*!< WRONGLAN (Bit 1)                                      */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Msk                            (0x2UL)        /*!< WRONGLAN (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Pos                            (2UL)          /*!< OUTOFSEQ (Bit 2)                                      */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Msk                            (0x4UL)        /*!< OUTOFSEQ (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Pos                          (3UL)          /*!< SEQMISSING (Bit 3)                                    */
+ #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Msk                          (0x8UL)        /*!< SEQMISSING (Bitfield-Mask: 0x01)                      */
+/* =====================================================  RM_ADDR_CTRL  ====================================================== */
+ #define R_ETHSW_RM_ADDR_CTRL_address_Pos                                 (0UL)          /*!< address (Bit 0)                                       */
+ #define R_ETHSW_RM_ADDR_CTRL_address_Msk                                 (0xfffUL)      /*!< address (Bitfield-Mask: 0xfff)                        */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Pos                           (22UL)         /*!< CLEAR_DYNAMIC (Bit 22)                                */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Msk                           (0x400000UL)   /*!< CLEAR_DYNAMIC (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Pos                            (23UL)         /*!< CLEAR_MEMORY (Bit 23)                                 */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Msk                            (0x800000UL)   /*!< CLEAR_MEMORY (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_RM_ADDR_CTRL_WRITE_Pos                                   (25UL)         /*!< WRITE (Bit 25)                                        */
+ #define R_ETHSW_RM_ADDR_CTRL_WRITE_Msk                                   (0x2000000UL)  /*!< WRITE (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_RM_ADDR_CTRL_READ_Pos                                    (26UL)         /*!< READ (Bit 26)                                         */
+ #define R_ETHSW_RM_ADDR_CTRL_READ_Msk                                    (0x4000000UL)  /*!< READ (Bitfield-Mask: 0x01)                            */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Pos                                   (29UL)         /*!< CLEAR (Bit 29)                                        */
+ #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Msk                                   (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_RM_ADDR_CTRL_BUSY_Pos                                    (31UL)         /*!< BUSY (Bit 31)                                         */
+ #define R_ETHSW_RM_ADDR_CTRL_BUSY_Msk                                    (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ========================================================  RM_DATA  ======================================================== */
+ #define R_ETHSW_RM_DATA_RM_DATA_Pos                                      (0UL)          /*!< RM_DATA (Bit 0)                                       */
+ #define R_ETHSW_RM_DATA_RM_DATA_Msk                                      (0xffffffffUL) /*!< RM_DATA (Bitfield-Mask: 0xffffffff)                   */
+/* ======================================================  RM_DATA_HI  ======================================================= */
+ #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Pos                                (0UL)          /*!< RM_DATA_HI (Bit 0)                                    */
+ #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Msk                                (0xffffffffUL) /*!< RM_DATA_HI (Bitfield-Mask: 0xffffffff)                */
+/* =======================================================  RM_STATUS  ======================================================= */
+ #define R_ETHSW_RM_STATUS_ageaddress_Pos                                 (0UL)          /*!< ageaddress (Bit 0)                                    */
+ #define R_ETHSW_RM_STATUS_ageaddress_Msk                                 (0xfffUL)      /*!< ageaddress (Bitfield-Mask: 0xfff)                     */
+/* =====================================================  TxSeqTooLate  ====================================================== */
+ #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Pos                            (0UL)          /*!< TxSeqTooLate (Bit 0)                                  */
+ #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Msk                            (0xfUL)        /*!< TxSeqTooLate (Bitfield-Mask: 0x0f)                    */
+/* ====================================================  CntErrWrongLanA  ==================================================== */
+ #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Pos                      (0UL)          /*!< CntErrWrongLanA (Bit 0)                               */
+ #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Msk                      (0xffffffffUL) /*!< CntErrWrongLanA (Bitfield-Mask: 0xffffffff)           */
+/* ====================================================  CntErrWrongLanB  ==================================================== */
+ #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Pos                      (0UL)          /*!< CntErrWrongLanB (Bit 0)                               */
+ #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Msk                      (0xffffffffUL) /*!< CntErrWrongLanB (Bitfield-Mask: 0xffffffff)           */
+/* ======================================================  CntDupLanA  ======================================================= */
+ #define R_ETHSW_CntDupLanA_CntDupLanA_Pos                                (0UL)          /*!< CntDupLanA (Bit 0)                                    */
+ #define R_ETHSW_CntDupLanA_CntDupLanA_Msk                                (0xffffffffUL) /*!< CntDupLanA (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  CntDupLanB  ======================================================= */
+ #define R_ETHSW_CntDupLanB_CntDupLanB_Pos                                (0UL)          /*!< CntDupLanB (Bit 0)                                    */
+ #define R_ETHSW_CntDupLanB_CntDupLanB_Msk                                (0xffffffffUL) /*!< CntDupLanB (Bitfield-Mask: 0xffffffff)                */
+/* ====================================================  CntOutOfSeqLowA  ==================================================== */
+ #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Pos                      (0UL)          /*!< CntOutOfSeqLowA (Bit 0)                               */
+ #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Msk                      (0xffffffffUL) /*!< CntOutOfSeqLowA (Bitfield-Mask: 0xffffffff)           */
+/* ====================================================  CntOutOfSeqLowB  ==================================================== */
+ #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Pos                      (0UL)          /*!< CntOutOfSeqLowB (Bit 0)                               */
+ #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Msk                      (0xffffffffUL) /*!< CntOutOfSeqLowB (Bitfield-Mask: 0xffffffff)           */
+/* =====================================================  CntOutOfSeqA  ====================================================== */
+ #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Pos                            (0UL)          /*!< CntOutOfSeqA (Bit 0)                                  */
+ #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Msk                            (0xffffffffUL) /*!< CntOutOfSeqA (Bitfield-Mask: 0xffffffff)              */
+/* =====================================================  CntOutOfSeqB  ====================================================== */
+ #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Pos                            (0UL)          /*!< CntOutOfSeqB (Bit 0)                                  */
+ #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Msk                            (0xffffffffUL) /*!< CntOutOfSeqB (Bitfield-Mask: 0xffffffff)              */
+/* ======================================================  CntAcceptA  ======================================================= */
+ #define R_ETHSW_CntAcceptA_CntAcceptA_Pos                                (0UL)          /*!< CntAcceptA (Bit 0)                                    */
+ #define R_ETHSW_CntAcceptA_CntAcceptA_Msk                                (0xffffffffUL) /*!< CntAcceptA (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  CntAcceptB  ======================================================= */
+ #define R_ETHSW_CntAcceptB_CntAcceptB_Pos                                (0UL)          /*!< CntAcceptB (Bit 0)                                    */
+ #define R_ETHSW_CntAcceptB_CntAcceptB_Msk                                (0xffffffffUL) /*!< CntAcceptB (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  CntMissing  ======================================================= */
+ #define R_ETHSW_CntMissing_CntMissing_Pos                                (0UL)          /*!< CntMissing (Bit 0)                                    */
+ #define R_ETHSW_CntMissing_CntMissing_Msk                                (0xffffffffUL) /*!< CntMissing (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  HUB_CONFIG  ======================================================= */
+ #define R_ETHSW_HUB_CONFIG_HUB_ENA_Pos                                   (0UL)          /*!< HUB_ENA (Bit 0)                                       */
+ #define R_ETHSW_HUB_CONFIG_HUB_ENA_Msk                                   (0x1UL)        /*!< HUB_ENA (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Pos                            (1UL)          /*!< RETRANSMIT_ENA (Bit 1)                                */
+ #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Msk                            (0x2UL)        /*!< RETRANSMIT_ENA (Bitfield-Mask: 0x01)                  */
+ #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Pos                              (2UL)          /*!< TRIGGER_MODE (Bit 2)                                  */
+ #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Msk                              (0x4UL)        /*!< TRIGGER_MODE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Pos                               (3UL)          /*!< HUB_ISOLATE (Bit 3)                                   */
+ #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Msk                               (0x8UL)        /*!< HUB_ISOLATE (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Pos                                 (4UL)          /*!< TIMER_SEL (Bit 4)                                     */
+ #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Msk                                 (0x10UL)       /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Pos                                  (6UL)          /*!< IPG_WAIT (Bit 6)                                      */
+ #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Msk                                  (0x1c0UL)      /*!< IPG_WAIT (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_HUB_CONFIG_CRS_GEN_Pos                                   (9UL)          /*!< CRS_GEN (Bit 9)                                       */
+ #define R_ETHSW_HUB_CONFIG_CRS_GEN_Msk                                   (0x200UL)      /*!< CRS_GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Pos                              (10UL)         /*!< PRMB_GEN_DIS (Bit 10)                                 */
+ #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Msk                              (0x400UL)      /*!< PRMB_GEN_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Pos                             (11UL)         /*!< JAM_WAIT_IDLE (Bit 11)                                */
+ #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Msk                             (0x800UL)      /*!< JAM_WAIT_IDLE (Bitfield-Mask: 0x01)                   */
+/* =======================================================  HUB_GROUP  ======================================================= */
+ #define R_ETHSW_HUB_GROUP_HUB_GROUP_Pos                                  (0UL)          /*!< HUB_GROUP (Bit 0)                                     */
+ #define R_ETHSW_HUB_GROUP_HUB_GROUP_Msk                                  (0x7UL)        /*!< HUB_GROUP (Bitfield-Mask: 0x07)                       */
+/* ======================================================  HUB_DEFPORT  ====================================================== */
+ #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Pos                              (0UL)          /*!< HUB_DEFPORT (Bit 0)                                   */
+ #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Msk                              (0x7UL)        /*!< HUB_DEFPORT (Bitfield-Mask: 0x07)                     */
+/* =================================================  HUB_TRIGGER_IMMEDIATE  ================================================= */
+ #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Pos          (0UL)          /*!< HUB_TRIGGER_IMMEDIATE (Bit 0)                       */
+ #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Msk          (0x7UL)        /*!< HUB_TRIGGER_IMMEDIATE (Bitfield-Mask: 0x07)       */
+/* ====================================================  HUB_TRIGGER_AT  ===================================================== */
+ #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Pos                        (0UL)          /*!< HUB_TRIGGER_AT (Bit 0)                                */
+ #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Msk                        (0x7UL)        /*!< HUB_TRIGGER_AT (Bitfield-Mask: 0x07)                  */
+/* =======================================================  HUB_TTIME  ======================================================= */
+ #define R_ETHSW_HUB_TTIME_HUB_TTIME_Pos                                  (0UL)          /*!< HUB_TTIME (Bit 0)                                     */
+ #define R_ETHSW_HUB_TTIME_HUB_TTIME_Msk                                  (0xffffffffUL) /*!< HUB_TTIME (Bitfield-Mask: 0xffffffff)                 */
+/* ====================================================  HUB_IRQ_CONTROL  ==================================================== */
+ #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Pos                           (0UL)          /*!< RX_TRIGGER (Bit 0)                                    */
+ #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Msk                           (0x7UL)        /*!< RX_TRIGGER (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Pos                           (3UL)          /*!< CHANGE_DET (Bit 3)                                    */
+ #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Msk                           (0x8UL)        /*!< CHANGE_DET (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Pos                    (4UL)          /*!< TRIGGER_IMMEDIATE (Bit 4)                             */
+ #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Msk                    (0x10UL)       /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Pos                        (5UL)          /*!< TRIGGER_TIMER (Bit 5)                                 */
+ #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Msk                        (0x20UL)       /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01)                   */
+/* ===================================================  HUB_IRQ_STAT_ACK  ==================================================== */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Pos                          (0UL)          /*!< RX_TRIGGER (Bit 0)                                    */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Msk                          (0x7UL)        /*!< RX_TRIGGER (Bitfield-Mask: 0x07)                      */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Pos                          (3UL)          /*!< CHANGE_DET (Bit 3)                                    */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Msk                          (0x8UL)        /*!< CHANGE_DET (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Pos                   (4UL)          /*!< TRIGGER_IMMEDIATE (Bit 4)                             */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Msk                   (0x10UL)       /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01)               */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Pos                       (5UL)          /*!< TRIGGER_TIMER (Bit 5)                                 */
+ #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Msk                       (0x20UL)       /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01)                   */
+/* ======================================================  HUB_STATUS  ======================================================= */
+ #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Pos                              (0UL)          /*!< PORTS_ACTIVE (Bit 0)                                  */
+ #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Msk                              (0x7UL)        /*!< PORTS_ACTIVE (Bitfield-Mask: 0x07)                    */
+ #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Pos                                 (9UL)          /*!< TX_ACTIVE (Bit 9)                                     */
+ #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Msk                                 (0x200UL)      /*!< TX_ACTIVE (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_HUB_STATUS_TX_BUSY_Pos                                   (10UL)         /*!< TX_BUSY (Bit 10)                                      */
+ #define R_ETHSW_HUB_STATUS_TX_BUSY_Msk                                   (0x400UL)      /*!< TX_BUSY (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_HUB_STATUS_Speed_OK_Pos                                  (11UL)         /*!< Speed_OK (Bit 11)                                     */
+ #define R_ETHSW_HUB_STATUS_Speed_OK_Msk                                  (0x800UL)      /*!< Speed_OK (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Pos                         (12UL)         /*!< TX_Change_Pending (Bit 12)                            */
+ #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Msk                         (0x1000UL)     /*!< TX_Change_Pending (Bitfield-Mask: 0x01)               */
+/* ===================================================  HUB_OPORT_STATUS  ==================================================== */
+ #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Pos                    (0UL)          /*!< HUB_OPORT_STATUS (Bit 0)                              */
+ #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Msk                    (0x7UL)        /*!< HUB_OPORT_STATUS (Bitfield-Mask: 0x07)                */
+/* ======================================================  TDMA_CONFIG  ====================================================== */
+ #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Pos                                 (0UL)          /*!< TDMA_ENA (Bit 0)                                      */
+ #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Msk                                 (0x1UL)        /*!< TDMA_ENA (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TDMA_CONFIG_WAIT_START_Pos                               (1UL)          /*!< WAIT_START (Bit 1)                                    */
+ #define R_ETHSW_TDMA_CONFIG_WAIT_START_Msk                               (0x2UL)        /*!< WAIT_START (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Pos                                (2UL)          /*!< TIMER_SEL (Bit 2)                                     */
+ #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Msk                                (0x4UL)        /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Pos                               (4UL)          /*!< RED_PERIOD (Bit 4)                                    */
+ #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Msk                               (0x10UL)       /*!< RED_PERIOD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Pos                             (5UL)          /*!< RED_OVRD_ENA (Bit 5)                                  */
+ #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Msk                             (0x20UL)       /*!< RED_OVRD_ENA (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Pos                                 (6UL)          /*!< RED_OVRD (Bit 6)                                      */
+ #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Msk                                 (0x40UL)       /*!< RED_OVRD (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Pos                               (7UL)          /*!< IN_CT_WREN (Bit 7)                                    */
+ #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Msk                               (0x80UL)       /*!< IN_CT_WREN (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Pos                              (8UL)          /*!< OUT_CT_WREN (Bit 8)                                   */
+ #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Msk                              (0x100UL)      /*!< OUT_CT_WREN (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Pos                             (9UL)          /*!< HOLD_REQ_CLR (Bit 9)                                  */
+ #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Msk                             (0x200UL)      /*!< HOLD_REQ_CLR (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Pos                         (12UL)         /*!< TIMER_SEL_ACTIVE (Bit 12)                             */
+ #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Msk                         (0x1000UL)     /*!< TIMER_SEL_ACTIVE (Bitfield-Mask: 0x01)                */
+ #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Pos                                (16UL)         /*!< IN_CT_ENA (Bit 16)                                    */
+ #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Msk                                (0xf0000UL)    /*!< IN_CT_ENA (Bitfield-Mask: 0x0f)                       */
+ #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Pos                               (24UL)         /*!< OUT_CT_ENA (Bit 24)                                   */
+ #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Msk                               (0xf000000UL)  /*!< OUT_CT_ENA (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  TDMA_ENA_CTRL  ===================================================== */
+ #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Pos                               (0UL)          /*!< PORT_ENA (Bit 0)                                      */
+ #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Msk                               (0xfUL)        /*!< PORT_ENA (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Pos                              (16UL)         /*!< QGATE_DIS (Bit 16)                                    */
+ #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Msk                              (0xff0000UL)   /*!< QGATE_DIS (Bitfield-Mask: 0xff)                       */
+ #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Pos                              (24UL)         /*!< QTRIG_DIS (Bit 24)                                    */
+ #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Msk                              (0xff000000UL) /*!< QTRIG_DIS (Bitfield-Mask: 0xff)                       */
+/* ======================================================  TDMA_START  ======================================================= */
+ #define R_ETHSW_TDMA_START_TDMA_START_Pos                                (0UL)          /*!< TDMA_START (Bit 0)                                    */
+ #define R_ETHSW_TDMA_START_TDMA_START_Msk                                (0xffffffffUL) /*!< TDMA_START (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  TDMA_MODULO  ====================================================== */
+ #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Pos                              (0UL)          /*!< TDMA_MODULO (Bit 0)                                   */
+ #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Msk                              (0xffffffffUL) /*!< TDMA_MODULO (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  TDMA_CYCLE  ======================================================= */
+ #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Pos                                (0UL)          /*!< TDMA_CYCLE (Bit 0)                                    */
+ #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Msk                                (0xffffffffUL) /*!< TDMA_CYCLE (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  TCV_SEQ_ADDR  ====================================================== */
+ #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Pos                              (0UL)          /*!< TCV_S_ADDR (Bit 0)                                    */
+ #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Msk                              (0xfffUL)      /*!< TCV_S_ADDR (Bitfield-Mask: 0xfff)                     */
+ #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Pos                               (31UL)         /*!< ADDR_AINC (Bit 31)                                    */
+ #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Msk                               (0x80000000UL) /*!< ADDR_AINC (Bitfield-Mask: 0x01)                       */
+/* =====================================================  TCV_SEQ_CTRL  ====================================================== */
+ #define R_ETHSW_TCV_SEQ_CTRL_START_Pos                                   (0UL)          /*!< START (Bit 0)                                         */
+ #define R_ETHSW_TCV_SEQ_CTRL_START_Msk                                   (0x1UL)        /*!< START (Bitfield-Mask: 0x01)                           */
+ #define R_ETHSW_TCV_SEQ_CTRL_INT_Pos                                     (1UL)          /*!< INT (Bit 1)                                           */
+ #define R_ETHSW_TCV_SEQ_CTRL_INT_Msk                                     (0x2UL)        /*!< INT (Bitfield-Mask: 0x01)                             */
+ #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Pos                               (2UL)          /*!< TCV_D_IDX (Bit 2)                                     */
+ #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Msk                               (0x7fcUL)      /*!< TCV_D_IDX (Bitfield-Mask: 0x1ff)                      */
+ #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Pos                                    (22UL)         /*!< GPIO (Bit 22)                                         */
+ #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Msk                                    (0x3fc00000UL) /*!< GPIO (Bitfield-Mask: 0xff)                            */
+ #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Pos                               (31UL)         /*!< READ_MODE (Bit 31)                                    */
+ #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Msk                               (0x80000000UL) /*!< READ_MODE (Bitfield-Mask: 0x01)                       */
+/* =====================================================  TCV_SEQ_LAST  ====================================================== */
+ #define R_ETHSW_TCV_SEQ_LAST_LAST_Pos                                    (0UL)          /*!< LAST (Bit 0)                                          */
+ #define R_ETHSW_TCV_SEQ_LAST_LAST_Msk                                    (0xfffUL)      /*!< LAST (Bitfield-Mask: 0xfff)                           */
+ #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Pos                                  (16UL)         /*!< ACTIVE (Bit 16)                                       */
+ #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Msk                                  (0xfff0000UL)  /*!< ACTIVE (Bitfield-Mask: 0xfff)                         */
+/* ======================================================  TCV_D_ADDR  ======================================================= */
+ #define R_ETHSW_TCV_D_ADDR_ADDR_Pos                                      (0UL)          /*!< ADDR (Bit 0)                                          */
+ #define R_ETHSW_TCV_D_ADDR_ADDR_Msk                                      (0x1ffUL)      /*!< ADDR (Bitfield-Mask: 0x1ff)                           */
+ #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Pos                               (31UL)         /*!< AINC_WR_ENA (Bit 31)                                  */
+ #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Msk                               (0x80000000UL) /*!< AINC_WR_ENA (Bitfield-Mask: 0x01)                     */
+/* =====================================================  TCV_D_OFFSET  ====================================================== */
+ #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Pos                            (0UL)          /*!< TCV_D_OFFSET (Bit 0)                                  */
+ #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Msk                            (0xffffffffUL) /*!< TCV_D_OFFSET (Bitfield-Mask: 0xffffffff)              */
+/* ======================================================  TCV_D_CTRL  ======================================================= */
+ #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Pos                                  (0UL)          /*!< INC_CTR0 (Bit 0)                                      */
+ #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Msk                                  (0x1UL)        /*!< INC_CTR0 (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Pos                                  (1UL)          /*!< INC_CTR1 (Bit 1)                                      */
+ #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Msk                                  (0x2UL)        /*!< INC_CTR1 (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Pos                                (2UL)          /*!< RED_PERIOD (Bit 2)                                    */
+ #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Msk                                (0x4UL)        /*!< RED_PERIOD (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Pos                                (3UL)          /*!< OUT_CT_ENA (Bit 3)                                    */
+ #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Msk                                (0x8UL)        /*!< OUT_CT_ENA (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Pos                                 (4UL)          /*!< IN_CT_ENA (Bit 4)                                     */
+ #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Msk                                 (0x10UL)       /*!< IN_CT_ENA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Pos                              (5UL)          /*!< TRIGGER_MODE (Bit 5)                                  */
+ #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Msk                              (0x20UL)       /*!< TRIGGER_MODE (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Pos                                 (6UL)          /*!< GATE_MODE (Bit 6)                                     */
+ #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Msk                                 (0x40UL)       /*!< GATE_MODE (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Pos                                  (7UL)          /*!< HOLD_REQ (Bit 7)                                      */
+ #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Msk                                  (0x80UL)       /*!< HOLD_REQ (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_TCV_D_CTRL_QGATE_Pos                                     (8UL)          /*!< QGATE (Bit 8)                                         */
+ #define R_ETHSW_TCV_D_CTRL_QGATE_Msk                                     (0xff00UL)     /*!< QGATE (Bitfield-Mask: 0xff)                           */
+ #define R_ETHSW_TCV_D_CTRL_PMASK_Pos                                     (16UL)         /*!< PMASK (Bit 16)                                        */
+ #define R_ETHSW_TCV_D_CTRL_PMASK_Msk                                     (0xf0000UL)    /*!< PMASK (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  TDMA_CTR0  ======================================================= */
+ #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Pos                                  (0UL)          /*!< TDMA_CTR0 (Bit 0)                                     */
+ #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Msk                                  (0xffffffffUL) /*!< TDMA_CTR0 (Bitfield-Mask: 0xffffffff)                 */
+/* =======================================================  TDMA_CTR1  ======================================================= */
+ #define R_ETHSW_TDMA_CTR1_VALUE_Pos                                      (0UL)          /*!< VALUE (Bit 0)                                         */
+ #define R_ETHSW_TDMA_CTR1_VALUE_Msk                                      (0xffUL)       /*!< VALUE (Bitfield-Mask: 0xff)                           */
+ #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Pos                                  (8UL)          /*!< WRITE_ENA (Bit 8)                                     */
+ #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Msk                                  (0x100UL)      /*!< WRITE_ENA (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_TDMA_CTR1_MAX_Pos                                        (16UL)         /*!< MAX (Bit 16)                                          */
+ #define R_ETHSW_TDMA_CTR1_MAX_Msk                                        (0xff0000UL)   /*!< MAX (Bitfield-Mask: 0xff)                             */
+ #define R_ETHSW_TDMA_CTR1_INT_VALUE_Pos                                  (24UL)         /*!< INT_VALUE (Bit 24)                                    */
+ #define R_ETHSW_TDMA_CTR1_INT_VALUE_Msk                                  (0xff000000UL) /*!< INT_VALUE (Bitfield-Mask: 0xff)                       */
+/* ====================================================  TDMA_TCV_START  ===================================================== */
+ #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Pos                        (0UL)          /*!< TDMA_TCV_START (Bit 0)                                */
+ #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Msk                        (0xfffUL)      /*!< TDMA_TCV_START (Bitfield-Mask: 0xfff)                 */
+/* ====================================================  TIME_LOAD_NEXT  ===================================================== */
+ #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Pos                        (0UL)          /*!< TIME_LOAD_NEXT (Bit 0)                                */
+ #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Msk                        (0xffffffffUL) /*!< TIME_LOAD_NEXT (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  TDMA_IRQ_CONTROL  ==================================================== */
+ #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Pos                          (0UL)          /*!< TCV_INT_EN (Bit 0)                                    */
+ #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Msk                          (0x1UL)        /*!< TCV_INT_EN (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Pos                         (13UL)         /*!< CTR1_INT_EN (Bit 13)                                  */
+ #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Msk                         (0x2000UL)     /*!< CTR1_INT_EN (Bitfield-Mask: 0x01)                     */
+/* ===================================================  TDMA_IRQ_STAT_ACK  =================================================== */
+ #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Pos                            (0UL)          /*!< TCV_ACK (Bit 0)                                       */
+ #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Msk                            (0x1UL)        /*!< TCV_ACK (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Pos                           (13UL)         /*!< CTR1_ACK (Bit 13)                                     */
+ #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Msk                           (0x2000UL)     /*!< CTR1_ACK (Bitfield-Mask: 0x01)                        */
+/* =======================================================  TDMA_GPIO  ======================================================= */
+ #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Pos                                (0UL)          /*!< GPIO_STATUS (Bit 0)                                   */
+ #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Msk                                (0xffUL)       /*!< GPIO_STATUS (Bitfield-Mask: 0xff)                     */
+ #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Pos                                  (16UL)         /*!< GPIO_MODE (Bit 16)                                    */
+ #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Msk                                  (0xffff0000UL) /*!< GPIO_MODE (Bitfield-Mask: 0xffff)                     */
+/* ====================================================  RXMATCH_CONFIG  ===================================================== */
+ #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Pos                            (0UL)          /*!< PATTERN_EN (Bit 0)                                    */
+ #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk                            (0xfffUL)      /*!< PATTERN_EN (Bitfield-Mask: 0xfff)                     */
+/* =====================================================  PATTERN_CTRL  ====================================================== */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Pos                               (0UL)          /*!< MATCH_NOT (Bit 0)                                     */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Msk                               (0x1UL)        /*!< MATCH_NOT (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Pos                                 (1UL)          /*!< MGMTFWD (Bit 1)                                       */
+ #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Msk                                 (0x2UL)        /*!< MGMTFWD (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PATTERN_CTRL_DISCARD_Pos                                 (2UL)          /*!< DISCARD (Bit 2)                                       */
+ #define R_ETHSW_PATTERN_CTRL_DISCARD_Msk                                 (0x4UL)        /*!< DISCARD (Bitfield-Mask: 0x01)                         */
+ #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Pos                                (3UL)          /*!< SET_PRIO (Bit 3)                                      */
+ #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Msk                                (0x8UL)        /*!< SET_PRIO (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PATTERN_CTRL_MODE_Pos                                    (4UL)          /*!< MODE (Bit 4)                                          */
+ #define R_ETHSW_PATTERN_CTRL_MODE_Msk                                    (0x30UL)       /*!< MODE (Bitfield-Mask: 0x03)                            */
+ #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Pos                           (6UL)          /*!< TIMER_SEL_OVR (Bit 6)                                 */
+ #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Msk                           (0x40UL)       /*!< TIMER_SEL_OVR (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Pos                           (7UL)          /*!< FORCE_FORWARD (Bit 7)                                 */
+ #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Msk                           (0x80UL)       /*!< FORCE_FORWARD (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Pos                              (8UL)          /*!< HUBTRIGGER (Bit 8)                                    */
+ #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Msk                              (0x100UL)      /*!< HUBTRIGGER (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Pos                               (9UL)          /*!< MATCH_RED (Bit 9)                                     */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Msk                               (0x200UL)      /*!< MATCH_RED (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Pos                           (10UL)         /*!< MATCH_NOT_RED (Bit 10)                                */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Msk                           (0x400UL)      /*!< MATCH_NOT_RED (Bitfield-Mask: 0x01)                   */
+ #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Pos                               (11UL)         /*!< VLAN_SKIP (Bit 11)                                    */
+ #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Msk                               (0x800UL)      /*!< VLAN_SKIP (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_PATTERN_CTRL_PRIORITY_Pos                                (12UL)         /*!< PRIORITY (Bit 12)                                     */
+ #define R_ETHSW_PATTERN_CTRL_PRIORITY_Msk                                (0x7000UL)     /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
+ #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Pos                            (15UL)         /*!< LEARNING_DIS (Bit 15)                                 */
+ #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Msk                            (0x8000UL)     /*!< LEARNING_DIS (Bitfield-Mask: 0x01)                    */
+ #define R_ETHSW_PATTERN_CTRL_PORTMASK_Pos                                (16UL)         /*!< PORTMASK (Bit 16)                                     */
+ #define R_ETHSW_PATTERN_CTRL_PORTMASK_Msk                                (0xf0000UL)    /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
+ #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Pos                             (22UL)         /*!< IMC_TRIGGER (Bit 22)                                  */
+ #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Msk                             (0x400000UL)   /*!< IMC_TRIGGER (Bitfield-Mask: 0x01)                     */
+ #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Pos                         (23UL)         /*!< IMC_TRIGGER_DLY (Bit 23)                              */
+ #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Msk                         (0x800000UL)   /*!< IMC_TRIGGER_DLY (Bitfield-Mask: 0x01)                 */
+ #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Pos                              (24UL)         /*!< SWAP_BYTES (Bit 24)                                   */
+ #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Msk                              (0x1000000UL)  /*!< SWAP_BYTES (Bitfield-Mask: 0x01)                      */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Pos                                (25UL)         /*!< MATCH_LT (Bit 25)                                     */
+ #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Msk                                (0x2000000UL)  /*!< MATCH_LT (Bitfield-Mask: 0x01)                        */
+ #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Pos                               (26UL)         /*!< TIMER_SEL (Bit 26)                                    */
+ #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Msk                               (0x4000000UL)  /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
+ #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Pos                                (28UL)         /*!< QUEUESEL (Bit 28)                                     */
+ #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Msk                                (0xf0000000UL) /*!< QUEUESEL (Bitfield-Mask: 0x0f)                        */
+/* ==================================================  PATTERN_IRQ_CONTROL  ================================================== */
+ #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Pos                         (0UL)          /*!< MATCHINT (Bit 0)                                      */
+ #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Msk                         (0xfffUL)      /*!< MATCHINT (Bitfield-Mask: 0xfff)                       */
+ #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Pos                        (16UL)         /*!< ERROR_INT (Bit 16)                                    */
+ #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Msk                        (0xf0000UL)    /*!< ERROR_INT (Bitfield-Mask: 0x0f)                       */
+/* =================================================  PATTERN_IRQ_STAT_ACK  ================================================== */
+ #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Pos                        (0UL)          /*!< MATCHINT (Bit 0)                                      */
+ #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Msk                        (0xfffUL)      /*!< MATCHINT (Bitfield-Mask: 0xfff)                       */
+ #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Pos                       (16UL)         /*!< ERROR_INT (Bit 16)                                    */
+ #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Msk                       (0xf0000UL)    /*!< ERROR_INT (Bitfield-Mask: 0x0f)                       */
+/* ======================================================  PTRN_VLANID  ====================================================== */
+ #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Pos                              (0UL)          /*!< PTRN_VLANID (Bit 0)                                   */
+ #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Msk                              (0xffffUL)     /*!< PTRN_VLANID (Bitfield-Mask: 0xffff)                   */
+/* ======================================================  PATTERN_SEL  ====================================================== */
+ #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Pos                              (0UL)          /*!< PATTERN_SEL (Bit 0)                                   */
+ #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Msk                              (0xfUL)        /*!< PATTERN_SEL (Bitfield-Mask: 0x0f)                     */
+/* ======================================================  PTRN_CMP_30  ====================================================== */
+ #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Pos                              (0UL)          /*!< PTRN_CMP_30 (Bit 0)                                   */
+ #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Msk                              (0xffffffffUL) /*!< PTRN_CMP_30 (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  PTRN_CMP_74  ====================================================== */
+ #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Pos                              (0UL)          /*!< PTRN_CMP_74 (Bit 0)                                   */
+ #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Msk                              (0xffffffffUL) /*!< PTRN_CMP_74 (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  PTRN_CMP_118  ====================================================== */
+ #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Pos                            (0UL)          /*!< PTRN_CMP_118 (Bit 0)                                  */
+ #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Msk                            (0xffffffffUL) /*!< PTRN_CMP_118 (Bitfield-Mask: 0xffffffff)              */
+/* ======================================================  PTRN_MSK_30  ====================================================== */
+ #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Pos                              (0UL)          /*!< PTRN_MSK_30 (Bit 0)                                   */
+ #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Msk                              (0xffffffffUL) /*!< PTRN_MSK_30 (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  PTRN_MSK_74  ====================================================== */
+ #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Pos                              (0UL)          /*!< PTRN_MSK_74 (Bit 0)                                   */
+ #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Msk                              (0xffffffffUL) /*!< PTRN_MSK_74 (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  PTRN_MSK_118  ====================================================== */
+ #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Pos                            (0UL)          /*!< PTRN_MSK_118 (Bit 0)                                  */
+ #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Msk                            (0xffffffffUL) /*!< PTRN_MSK_118 (Bitfield-Mask: 0xffffffff)              */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ESC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TYPE  ========================================================== */
+ #define R_ESC_TYPE_TYPE_Pos                        (0UL)          /*!< TYPE (Bit 0)                                          */
+ #define R_ESC_TYPE_TYPE_Msk                        (0xffUL)       /*!< TYPE (Bitfield-Mask: 0xff)                            */
+/* =======================================================  REVISION  ======================================================== */
+ #define R_ESC_REVISION_REV_Pos                     (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_ESC_REVISION_REV_Msk                     (0xffUL)       /*!< REV (Bitfield-Mask: 0xff)                             */
+/* =========================================================  BUILD  ========================================================= */
+ #define R_ESC_BUILD_BUILD_Pos                      (0UL)          /*!< BUILD (Bit 0)                                         */
+ #define R_ESC_BUILD_BUILD_Msk                      (0xffUL)       /*!< BUILD (Bitfield-Mask: 0xff)                           */
+/* =======================================================  FMMU_NUM  ======================================================== */
+ #define R_ESC_FMMU_NUM_NUMFMMU_Pos                 (0UL)          /*!< NUMFMMU (Bit 0)                                       */
+ #define R_ESC_FMMU_NUM_NUMFMMU_Msk                 (0xffUL)       /*!< NUMFMMU (Bitfield-Mask: 0xff)                         */
+/* =====================================================  SYNC_MANAGER  ====================================================== */
+ #define R_ESC_SYNC_MANAGER_NUMSYNC_Pos             (0UL)          /*!< NUMSYNC (Bit 0)                                       */
+ #define R_ESC_SYNC_MANAGER_NUMSYNC_Msk             (0xffUL)       /*!< NUMSYNC (Bitfield-Mask: 0xff)                         */
+/* =======================================================  RAM_SIZE  ======================================================== */
+ #define R_ESC_RAM_SIZE_RAMSIZE_Pos                 (0UL)          /*!< RAMSIZE (Bit 0)                                       */
+ #define R_ESC_RAM_SIZE_RAMSIZE_Msk                 (0xffUL)       /*!< RAMSIZE (Bitfield-Mask: 0xff)                         */
+/* =======================================================  PORT_DESC  ======================================================= */
+ #define R_ESC_PORT_DESC_P0_Pos                     (0UL)          /*!< P0 (Bit 0)                                            */
+ #define R_ESC_PORT_DESC_P0_Msk                     (0x3UL)        /*!< P0 (Bitfield-Mask: 0x03)                              */
+ #define R_ESC_PORT_DESC_P1_Pos                     (2UL)          /*!< P1 (Bit 2)                                            */
+ #define R_ESC_PORT_DESC_P1_Msk                     (0xcUL)        /*!< P1 (Bitfield-Mask: 0x03)                              */
+ #define R_ESC_PORT_DESC_P2_Pos                     (4UL)          /*!< P2 (Bit 4)                                            */
+ #define R_ESC_PORT_DESC_P2_Msk                     (0x30UL)       /*!< P2 (Bitfield-Mask: 0x03)                              */
+ #define R_ESC_PORT_DESC_P3_Pos                     (6UL)          /*!< P3 (Bit 6)                                            */
+ #define R_ESC_PORT_DESC_P3_Msk                     (0xc0UL)       /*!< P3 (Bitfield-Mask: 0x03)                              */
+/* ========================================================  FEATURE  ======================================================== */
+ #define R_ESC_FEATURE_FMMU_Pos                     (0UL)          /*!< FMMU (Bit 0)                                          */
+ #define R_ESC_FEATURE_FMMU_Msk                     (0x1UL)        /*!< FMMU (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_FEATURE_DC_Pos                       (2UL)          /*!< DC (Bit 2)                                            */
+ #define R_ESC_FEATURE_DC_Msk                       (0x4UL)        /*!< DC (Bitfield-Mask: 0x01)                              */
+ #define R_ESC_FEATURE_DCWID_Pos                    (3UL)          /*!< DCWID (Bit 3)                                         */
+ #define R_ESC_FEATURE_DCWID_Msk                    (0x8UL)        /*!< DCWID (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_FEATURE_LINKDECMII_Pos               (6UL)          /*!< LINKDECMII (Bit 6)                                    */
+ #define R_ESC_FEATURE_LINKDECMII_Msk               (0x40UL)       /*!< LINKDECMII (Bitfield-Mask: 0x01)                      */
+ #define R_ESC_FEATURE_FCS_Pos                      (7UL)          /*!< FCS (Bit 7)                                           */
+ #define R_ESC_FEATURE_FCS_Msk                      (0x80UL)       /*!< FCS (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_FEATURE_DCSYNC_Pos                   (8UL)          /*!< DCSYNC (Bit 8)                                        */
+ #define R_ESC_FEATURE_DCSYNC_Msk                   (0x100UL)      /*!< DCSYNC (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_FEATURE_LRW_Pos                      (9UL)          /*!< LRW (Bit 9)                                           */
+ #define R_ESC_FEATURE_LRW_Msk                      (0x200UL)      /*!< LRW (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_FEATURE_RWSUPP_Pos                   (10UL)         /*!< RWSUPP (Bit 10)                                       */
+ #define R_ESC_FEATURE_RWSUPP_Msk                   (0x400UL)      /*!< RWSUPP (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_FEATURE_FSCONFIG_Pos                 (11UL)         /*!< FSCONFIG (Bit 11)                                     */
+ #define R_ESC_FEATURE_FSCONFIG_Msk                 (0x800UL)      /*!< FSCONFIG (Bitfield-Mask: 0x01)                        */
+/* ======================================================  STATION_ADR  ====================================================== */
+ #define R_ESC_STATION_ADR_NODADDR_Pos              (0UL)          /*!< NODADDR (Bit 0)                                       */
+ #define R_ESC_STATION_ADR_NODADDR_Msk              (0xffffUL)     /*!< NODADDR (Bitfield-Mask: 0xffff)                       */
+/* =====================================================  STATION_ALIAS  ===================================================== */
+ #define R_ESC_STATION_ALIAS_NODALIADDR_Pos         (0UL)          /*!< NODALIADDR (Bit 0)                                    */
+ #define R_ESC_STATION_ALIAS_NODALIADDR_Msk         (0xffffUL)     /*!< NODALIADDR (Bitfield-Mask: 0xffff)                    */
+/* =====================================================  WR_REG_ENABLE  ===================================================== */
+ #define R_ESC_WR_REG_ENABLE_ENABLE_Pos             (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ESC_WR_REG_ENABLE_ENABLE_Msk             (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ====================================================  WR_REG_PROTECT  ===================================================== */
+ #define R_ESC_WR_REG_PROTECT_PROTECT_Pos           (0UL)          /*!< PROTECT (Bit 0)                                       */
+ #define R_ESC_WR_REG_PROTECT_PROTECT_Msk           (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+/* =====================================================  ESC_WR_ENABLE  ===================================================== */
+ #define R_ESC_ESC_WR_ENABLE_ENABLE_Pos             (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_ESC_ESC_WR_ENABLE_ENABLE_Msk             (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ====================================================  ESC_WR_PROTECT  ===================================================== */
+ #define R_ESC_ESC_WR_PROTECT_PROTECT_Pos           (0UL)          /*!< PROTECT (Bit 0)                                       */
+ #define R_ESC_ESC_WR_PROTECT_PROTECT_Msk           (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+/* ===================================================  ESC_RESET_ECAT_R  ==================================================== */
+ #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Pos      (0UL)          /*!< RESET_ECAT (Bit 0)                                    */
+ #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Msk      (0x3UL)        /*!< RESET_ECAT (Bitfield-Mask: 0x03)                      */
+/* ===================================================  ESC_RESET_ECAT_W  ==================================================== */
+ #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Pos      (0UL)          /*!< RESET_ECAT (Bit 0)                                    */
+ #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Msk      (0xffUL)       /*!< RESET_ECAT (Bitfield-Mask: 0xff)                      */
+/* ====================================================  ESC_RESET_PDI_R  ==================================================== */
+ #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Pos        (0UL)          /*!< RESET_PDI (Bit 0)                                     */
+ #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Msk        (0x3UL)        /*!< RESET_PDI (Bitfield-Mask: 0x03)                       */
+/* ====================================================  ESC_RESET_PDI_W  ==================================================== */
+ #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Pos        (0UL)          /*!< RESET_PDI (Bit 0)                                     */
+ #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Msk        (0xffUL)       /*!< RESET_PDI (Bitfield-Mask: 0xff)                       */
+/* ====================================================  ESC_DL_CONTROL  ===================================================== */
+ #define R_ESC_ESC_DL_CONTROL_FWDRULE_Pos           (0UL)          /*!< FWDRULE (Bit 0)                                       */
+ #define R_ESC_ESC_DL_CONTROL_FWDRULE_Msk           (0x1UL)        /*!< FWDRULE (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Pos           (1UL)          /*!< TEMPUSE (Bit 1)                                       */
+ #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Msk           (0x2UL)        /*!< TEMPUSE (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_DL_CONTROL_LP0_Pos               (8UL)          /*!< LP0 (Bit 8)                                           */
+ #define R_ESC_ESC_DL_CONTROL_LP0_Msk               (0x300UL)      /*!< LP0 (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_ESC_DL_CONTROL_LP1_Pos               (10UL)         /*!< LP1 (Bit 10)                                          */
+ #define R_ESC_ESC_DL_CONTROL_LP1_Msk               (0xc00UL)      /*!< LP1 (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_ESC_DL_CONTROL_LP2_Pos               (12UL)         /*!< LP2 (Bit 12)                                          */
+ #define R_ESC_ESC_DL_CONTROL_LP2_Msk               (0x3000UL)     /*!< LP2 (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_ESC_DL_CONTROL_LP3_Pos               (14UL)         /*!< LP3 (Bit 14)                                          */
+ #define R_ESC_ESC_DL_CONTROL_LP3_Msk               (0xc000UL)     /*!< LP3 (Bitfield-Mask: 0x03)                             */
+ #define R_ESC_ESC_DL_CONTROL_RXFIFO_Pos            (16UL)         /*!< RXFIFO (Bit 16)                                       */
+ #define R_ESC_ESC_DL_CONTROL_RXFIFO_Msk            (0x70000UL)    /*!< RXFIFO (Bitfield-Mask: 0x07)                          */
+ #define R_ESC_ESC_DL_CONTROL_STAALIAS_Pos          (24UL)         /*!< STAALIAS (Bit 24)                                     */
+ #define R_ESC_ESC_DL_CONTROL_STAALIAS_Msk          (0x1000000UL)  /*!< STAALIAS (Bitfield-Mask: 0x01)                        */
+/* ==================================================  PHYSICAL_RW_OFFSET  =================================================== */
+ #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Pos      (0UL)          /*!< RWOFFSET (Bit 0)                                      */
+ #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Msk      (0xffffUL)     /*!< RWOFFSET (Bitfield-Mask: 0xffff)                      */
+/* =====================================================  ESC_DL_STATUS  ===================================================== */
+ #define R_ESC_ESC_DL_STATUS_PDIOPE_Pos             (0UL)          /*!< PDIOPE (Bit 0)                                        */
+ #define R_ESC_ESC_DL_STATUS_PDIOPE_Msk             (0x1UL)        /*!< PDIOPE (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ESC_DL_STATUS_PDIWDST_Pos            (1UL)          /*!< PDIWDST (Bit 1)                                       */
+ #define R_ESC_ESC_DL_STATUS_PDIWDST_Msk            (0x2UL)        /*!< PDIWDST (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_DL_STATUS_ENHLINKD_Pos           (2UL)          /*!< ENHLINKD (Bit 2)                                      */
+ #define R_ESC_ESC_DL_STATUS_ENHLINKD_Msk           (0x4UL)        /*!< ENHLINKD (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_ESC_DL_STATUS_PHYP0_Pos              (4UL)          /*!< PHYP0 (Bit 4)                                         */
+ #define R_ESC_ESC_DL_STATUS_PHYP0_Msk              (0x10UL)       /*!< PHYP0 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_PHYP1_Pos              (5UL)          /*!< PHYP1 (Bit 5)                                         */
+ #define R_ESC_ESC_DL_STATUS_PHYP1_Msk              (0x20UL)       /*!< PHYP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_PHYP2_Pos              (6UL)          /*!< PHYP2 (Bit 6)                                         */
+ #define R_ESC_ESC_DL_STATUS_PHYP2_Msk              (0x40UL)       /*!< PHYP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_PHYP3_Pos              (7UL)          /*!< PHYP3 (Bit 7)                                         */
+ #define R_ESC_ESC_DL_STATUS_PHYP3_Msk              (0x80UL)       /*!< PHYP3 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_LP0_Pos                (8UL)          /*!< LP0 (Bit 8)                                           */
+ #define R_ESC_ESC_DL_STATUS_LP0_Msk                (0x100UL)      /*!< LP0 (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_ESC_DL_STATUS_COMP0_Pos              (9UL)          /*!< COMP0 (Bit 9)                                         */
+ #define R_ESC_ESC_DL_STATUS_COMP0_Msk              (0x200UL)      /*!< COMP0 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_LP1_Pos                (10UL)         /*!< LP1 (Bit 10)                                          */
+ #define R_ESC_ESC_DL_STATUS_LP1_Msk                (0x400UL)      /*!< LP1 (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_ESC_DL_STATUS_COMP1_Pos              (11UL)         /*!< COMP1 (Bit 11)                                        */
+ #define R_ESC_ESC_DL_STATUS_COMP1_Msk              (0x800UL)      /*!< COMP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_LP2_Pos                (12UL)         /*!< LP2 (Bit 12)                                          */
+ #define R_ESC_ESC_DL_STATUS_LP2_Msk                (0x1000UL)     /*!< LP2 (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_ESC_DL_STATUS_COMP2_Pos              (13UL)         /*!< COMP2 (Bit 13)                                        */
+ #define R_ESC_ESC_DL_STATUS_COMP2_Msk              (0x2000UL)     /*!< COMP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_DL_STATUS_LP3_Pos                (14UL)         /*!< LP3 (Bit 14)                                          */
+ #define R_ESC_ESC_DL_STATUS_LP3_Msk                (0x4000UL)     /*!< LP3 (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_ESC_DL_STATUS_COMP3_Pos              (15UL)         /*!< COMP3 (Bit 15)                                        */
+ #define R_ESC_ESC_DL_STATUS_COMP3_Msk              (0x8000UL)     /*!< COMP3 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  AL_CONTROL  ======================================================= */
+ #define R_ESC_AL_CONTROL_INISTATE_Pos              (0UL)          /*!< INISTATE (Bit 0)                                      */
+ #define R_ESC_AL_CONTROL_INISTATE_Msk              (0xfUL)        /*!< INISTATE (Bitfield-Mask: 0x0f)                        */
+ #define R_ESC_AL_CONTROL_ERRINDACK_Pos             (4UL)          /*!< ERRINDACK (Bit 4)                                     */
+ #define R_ESC_AL_CONTROL_ERRINDACK_Msk             (0x10UL)       /*!< ERRINDACK (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_AL_CONTROL_DEVICEID_Pos              (5UL)          /*!< DEVICEID (Bit 5)                                      */
+ #define R_ESC_AL_CONTROL_DEVICEID_Msk              (0x20UL)       /*!< DEVICEID (Bitfield-Mask: 0x01)                        */
+/* =======================================================  AL_STATUS  ======================================================= */
+ #define R_ESC_AL_STATUS_ACTSTATE_Pos               (0UL)          /*!< ACTSTATE (Bit 0)                                      */
+ #define R_ESC_AL_STATUS_ACTSTATE_Msk               (0xfUL)        /*!< ACTSTATE (Bitfield-Mask: 0x0f)                        */
+ #define R_ESC_AL_STATUS_ERR_Pos                    (4UL)          /*!< ERR (Bit 4)                                           */
+ #define R_ESC_AL_STATUS_ERR_Msk                    (0x10UL)       /*!< ERR (Bitfield-Mask: 0x01)                             */
+ #define R_ESC_AL_STATUS_DEVICEID_Pos               (5UL)          /*!< DEVICEID (Bit 5)                                      */
+ #define R_ESC_AL_STATUS_DEVICEID_Msk               (0x20UL)       /*!< DEVICEID (Bitfield-Mask: 0x01)                        */
+/* ====================================================  AL_STATUS_CODE  ===================================================== */
+ #define R_ESC_AL_STATUS_CODE_STATUSCODE_Pos        (0UL)          /*!< STATUSCODE (Bit 0)                                    */
+ #define R_ESC_AL_STATUS_CODE_STATUSCODE_Msk        (0xffffUL)     /*!< STATUSCODE (Bitfield-Mask: 0xffff)                    */
+/* ===================================================  RUN_LED_OVERRIDE  ==================================================== */
+ #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Pos         (0UL)          /*!< LEDCODE (Bit 0)                                       */
+ #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Msk         (0xfUL)        /*!< LEDCODE (Bitfield-Mask: 0x0f)                         */
+ #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Pos      (4UL)          /*!< OVERRIDEEN (Bit 4)                                    */
+ #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Msk      (0x10UL)       /*!< OVERRIDEEN (Bitfield-Mask: 0x01)                      */
+/* ===================================================  ERR_LED_OVERRIDE  ==================================================== */
+ #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Pos         (0UL)          /*!< LEDCODE (Bit 0)                                       */
+ #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Msk         (0xfUL)        /*!< LEDCODE (Bitfield-Mask: 0x0f)                         */
+ #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Pos      (4UL)          /*!< OVERRIDEEN (Bit 4)                                    */
+ #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Msk      (0x10UL)       /*!< OVERRIDEEN (Bitfield-Mask: 0x01)                      */
+/* ======================================================  PDI_CONTROL  ====================================================== */
+ #define R_ESC_PDI_CONTROL_PDI_Pos                  (0UL)          /*!< PDI (Bit 0)                                           */
+ #define R_ESC_PDI_CONTROL_PDI_Msk                  (0xffUL)       /*!< PDI (Bitfield-Mask: 0xff)                             */
+/* ======================================================  ESC_CONFIG  ======================================================= */
+ #define R_ESC_ESC_CONFIG_DEVEMU_Pos                (0UL)          /*!< DEVEMU (Bit 0)                                        */
+ #define R_ESC_ESC_CONFIG_DEVEMU_Msk                (0x1UL)        /*!< DEVEMU (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ESC_CONFIG_ENLALLP_Pos               (1UL)          /*!< ENLALLP (Bit 1)                                       */
+ #define R_ESC_ESC_CONFIG_ENLALLP_Msk               (0x2UL)        /*!< ENLALLP (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_CONFIG_DCSYNC_Pos                (2UL)          /*!< DCSYNC (Bit 2)                                        */
+ #define R_ESC_ESC_CONFIG_DCSYNC_Msk                (0x4UL)        /*!< DCSYNC (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ESC_CONFIG_DCLATCH_Pos               (3UL)          /*!< DCLATCH (Bit 3)                                       */
+ #define R_ESC_ESC_CONFIG_DCLATCH_Msk               (0x8UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ESC_CONFIG_ENLP0_Pos                 (4UL)          /*!< ENLP0 (Bit 4)                                         */
+ #define R_ESC_ESC_CONFIG_ENLP0_Msk                 (0x10UL)       /*!< ENLP0 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_CONFIG_ENLP1_Pos                 (5UL)          /*!< ENLP1 (Bit 5)                                         */
+ #define R_ESC_ESC_CONFIG_ENLP1_Msk                 (0x20UL)       /*!< ENLP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_CONFIG_ENLP2_Pos                 (6UL)          /*!< ENLP2 (Bit 6)                                         */
+ #define R_ESC_ESC_CONFIG_ENLP2_Msk                 (0x40UL)       /*!< ENLP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ESC_CONFIG_ENLP3_Pos                 (7UL)          /*!< ENLP3 (Bit 7)                                         */
+ #define R_ESC_ESC_CONFIG_ENLP3_Msk                 (0x80UL)       /*!< ENLP3 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  PDI_CONFIG  ======================================================= */
+ #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Pos          (0UL)          /*!< ONCHIPBUSCLK (Bit 0)                                  */
+ #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Msk          (0x1fUL)       /*!< ONCHIPBUSCLK (Bitfield-Mask: 0x1f)                    */
+ #define R_ESC_PDI_CONFIG_ONCHIPBUS_Pos             (5UL)          /*!< ONCHIPBUS (Bit 5)                                     */
+ #define R_ESC_PDI_CONFIG_ONCHIPBUS_Msk             (0xe0UL)       /*!< ONCHIPBUS (Bitfield-Mask: 0x07)                       */
+/* ===================================================  SYNC_LATCH_CONFIG  =================================================== */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Pos       (0UL)          /*!< SYNC0OUT (Bit 0)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Msk       (0x3UL)        /*!< SYNC0OUT (Bitfield-Mask: 0x03)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Pos       (2UL)          /*!< SYNCLAT0 (Bit 2)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Msk       (0x4UL)        /*!< SYNCLAT0 (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Pos       (3UL)          /*!< SYNC0MAP (Bit 3)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Msk       (0x8UL)        /*!< SYNC0MAP (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Pos       (4UL)          /*!< SYNC1OUT (Bit 4)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Msk       (0x30UL)       /*!< SYNC1OUT (Bitfield-Mask: 0x03)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Pos       (6UL)          /*!< SYNCLAT1 (Bit 6)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Msk       (0x40UL)       /*!< SYNCLAT1 (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Pos       (7UL)          /*!< SYNC1MAP (Bit 7)                                      */
+ #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Msk       (0x80UL)       /*!< SYNC1MAP (Bitfield-Mask: 0x01)                        */
+/* ====================================================  EXT_PDI_CONFIG  ===================================================== */
+ #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Pos        (0UL)          /*!< DATABUSWID (Bit 0)                                    */
+ #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Msk        (0x3UL)        /*!< DATABUSWID (Bitfield-Mask: 0x03)                      */
+/* ====================================================  ECAT_EVENT_MASK  ==================================================== */
+ #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Pos       (0UL)          /*!< ECATEVMASK (Bit 0)                                    */
+ #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Msk       (0xffffUL)     /*!< ECATEVMASK (Bitfield-Mask: 0xffff)                    */
+/* =====================================================  AL_EVENT_MASK  ===================================================== */
+ #define R_ESC_AL_EVENT_MASK_ALEVMASK_Pos           (0UL)          /*!< ALEVMASK (Bit 0)                                      */
+ #define R_ESC_AL_EVENT_MASK_ALEVMASK_Msk           (0xffffffffUL) /*!< ALEVMASK (Bitfield-Mask: 0xffffffff)                  */
+/* ====================================================  ECAT_EVENT_REQ  ===================================================== */
+ #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Pos           (0UL)          /*!< DCLATCH (Bit 0)                                       */
+ #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Msk           (0x1UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_ECAT_EVENT_REQ_DLSTA_Pos             (2UL)          /*!< DLSTA (Bit 2)                                         */
+ #define R_ESC_ECAT_EVENT_REQ_DLSTA_Msk             (0x4UL)        /*!< DLSTA (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ECAT_EVENT_REQ_ALSTA_Pos             (3UL)          /*!< ALSTA (Bit 3)                                         */
+ #define R_ESC_ECAT_EVENT_REQ_ALSTA_Msk             (0x8UL)        /*!< ALSTA (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Pos            (4UL)          /*!< SMSTA0 (Bit 4)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Msk            (0x10UL)       /*!< SMSTA0 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Pos            (5UL)          /*!< SMSTA1 (Bit 5)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Msk            (0x20UL)       /*!< SMSTA1 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Pos            (6UL)          /*!< SMSTA2 (Bit 6)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Msk            (0x40UL)       /*!< SMSTA2 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Pos            (7UL)          /*!< SMSTA3 (Bit 7)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Msk            (0x80UL)       /*!< SMSTA3 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Pos            (8UL)          /*!< SMSTA4 (Bit 8)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Msk            (0x100UL)      /*!< SMSTA4 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Pos            (9UL)          /*!< SMSTA5 (Bit 9)                                        */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Msk            (0x200UL)      /*!< SMSTA5 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Pos            (10UL)         /*!< SMSTA6 (Bit 10)                                       */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Msk            (0x400UL)      /*!< SMSTA6 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Pos            (11UL)         /*!< SMSTA7 (Bit 11)                                       */
+ #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Msk            (0x800UL)      /*!< SMSTA7 (Bitfield-Mask: 0x01)                          */
+/* =====================================================  AL_EVENT_REQ  ====================================================== */
+ #define R_ESC_AL_EVENT_REQ_ALCTRL_Pos              (0UL)          /*!< ALCTRL (Bit 0)                                        */
+ #define R_ESC_AL_EVENT_REQ_ALCTRL_Msk              (0x1UL)        /*!< ALCTRL (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_DCLATCH_Pos             (1UL)          /*!< DCLATCH (Bit 1)                                       */
+ #define R_ESC_AL_EVENT_REQ_DCLATCH_Msk             (0x2UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Pos          (2UL)          /*!< DCSYNC0STA (Bit 2)                                    */
+ #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Msk          (0x4UL)        /*!< DCSYNC0STA (Bitfield-Mask: 0x01)                      */
+ #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Pos          (3UL)          /*!< DCSYNC1STA (Bit 3)                                    */
+ #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Msk          (0x8UL)        /*!< DCSYNC1STA (Bitfield-Mask: 0x01)                      */
+ #define R_ESC_AL_EVENT_REQ_SYNCACT_Pos             (4UL)          /*!< SYNCACT (Bit 4)                                       */
+ #define R_ESC_AL_EVENT_REQ_SYNCACT_Msk             (0x10UL)       /*!< SYNCACT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_AL_EVENT_REQ_WDPD_Pos                (6UL)          /*!< WDPD (Bit 6)                                          */
+ #define R_ESC_AL_EVENT_REQ_WDPD_Msk                (0x40UL)       /*!< WDPD (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_AL_EVENT_REQ_SMINT0_Pos              (8UL)          /*!< SMINT0 (Bit 8)                                        */
+ #define R_ESC_AL_EVENT_REQ_SMINT0_Msk              (0x100UL)      /*!< SMINT0 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT1_Pos              (9UL)          /*!< SMINT1 (Bit 9)                                        */
+ #define R_ESC_AL_EVENT_REQ_SMINT1_Msk              (0x200UL)      /*!< SMINT1 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT2_Pos              (10UL)         /*!< SMINT2 (Bit 10)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT2_Msk              (0x400UL)      /*!< SMINT2 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT3_Pos              (11UL)         /*!< SMINT3 (Bit 11)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT3_Msk              (0x800UL)      /*!< SMINT3 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT4_Pos              (12UL)         /*!< SMINT4 (Bit 12)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT4_Msk              (0x1000UL)     /*!< SMINT4 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT5_Pos              (13UL)         /*!< SMINT5 (Bit 13)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT5_Msk              (0x2000UL)     /*!< SMINT5 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT6_Pos              (14UL)         /*!< SMINT6 (Bit 14)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT6_Msk              (0x4000UL)     /*!< SMINT6 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_AL_EVENT_REQ_SMINT7_Pos              (15UL)         /*!< SMINT7 (Bit 15)                                       */
+ #define R_ESC_AL_EVENT_REQ_SMINT7_Msk              (0x8000UL)     /*!< SMINT7 (Bitfield-Mask: 0x01)                          */
+/* =====================================================  RX_ERR_COUNT  ====================================================== */
+ #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Pos           (0UL)          /*!< INVFRMCNT (Bit 0)                                     */
+ #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Msk           (0xffUL)       /*!< INVFRMCNT (Bitfield-Mask: 0xff)                       */
+ #define R_ESC_RX_ERR_COUNT_RXERRCNT_Pos            (8UL)          /*!< RXERRCNT (Bit 8)                                      */
+ #define R_ESC_RX_ERR_COUNT_RXERRCNT_Msk            (0xff00UL)     /*!< RXERRCNT (Bitfield-Mask: 0xff)                        */
+/* ===================================================  FWD_RX_ERR_COUNT  ==================================================== */
+ #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Pos       (0UL)          /*!< FWDERRCNT (Bit 0)                                     */
+ #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Msk       (0xffUL)       /*!< FWDERRCNT (Bitfield-Mask: 0xff)                       */
+/* ==================================================  ECAT_PROC_ERR_COUNT  ================================================== */
+ #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Pos    (0UL)          /*!< EPUERRCNT (Bit 0)                                     */
+ #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Msk    (0xffUL)       /*!< EPUERRCNT (Bitfield-Mask: 0xff)                       */
+/* =====================================================  PDI_ERR_COUNT  ===================================================== */
+ #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Pos          (0UL)          /*!< PDIERRCNT (Bit 0)                                     */
+ #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Msk          (0xffUL)       /*!< PDIERRCNT (Bitfield-Mask: 0xff)                       */
+/* ====================================================  LOST_LINK_COUNT  ==================================================== */
+ #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Pos      (0UL)          /*!< LOSTLINKCNT (Bit 0)                                   */
+ #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Msk      (0xffUL)       /*!< LOSTLINKCNT (Bitfield-Mask: 0xff)                     */
+/* =======================================================  WD_DIVIDE  ======================================================= */
+ #define R_ESC_WD_DIVIDE_WDDIV_Pos                  (0UL)          /*!< WDDIV (Bit 0)                                         */
+ #define R_ESC_WD_DIVIDE_WDDIV_Msk                  (0xffffUL)     /*!< WDDIV (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  WDT_PDI  ======================================================== */
+ #define R_ESC_WDT_PDI_WDTIMPDI_Pos                 (0UL)          /*!< WDTIMPDI (Bit 0)                                      */
+ #define R_ESC_WDT_PDI_WDTIMPDI_Msk                 (0xffffUL)     /*!< WDTIMPDI (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  WDT_DATA  ======================================================== */
+ #define R_ESC_WDT_DATA_WDTIMPD_Pos                 (0UL)          /*!< WDTIMPD (Bit 0)                                       */
+ #define R_ESC_WDT_DATA_WDTIMPD_Msk                 (0xffffUL)     /*!< WDTIMPD (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  WDS_DATA  ======================================================== */
+ #define R_ESC_WDS_DATA_WDSTAPD_Pos                 (0UL)          /*!< WDSTAPD (Bit 0)                                       */
+ #define R_ESC_WDS_DATA_WDSTAPD_Msk                 (0x1UL)        /*!< WDSTAPD (Bitfield-Mask: 0x01)                         */
+/* =======================================================  WDC_DATA  ======================================================== */
+ #define R_ESC_WDC_DATA_WDCNTPD_Pos                 (0UL)          /*!< WDCNTPD (Bit 0)                                       */
+ #define R_ESC_WDC_DATA_WDCNTPD_Msk                 (0xffUL)       /*!< WDCNTPD (Bitfield-Mask: 0xff)                         */
+/* ========================================================  WDC_PDI  ======================================================== */
+ #define R_ESC_WDC_PDI_WDCNTPDI_Pos                 (0UL)          /*!< WDCNTPDI (Bit 0)                                      */
+ #define R_ESC_WDC_PDI_WDCNTPDI_Msk                 (0xffUL)       /*!< WDCNTPDI (Bitfield-Mask: 0xff)                        */
+/* =======================================================  EEP_CONF  ======================================================== */
+ #define R_ESC_EEP_CONF_CTRLPDI_Pos                 (0UL)          /*!< CTRLPDI (Bit 0)                                       */
+ #define R_ESC_EEP_CONF_CTRLPDI_Msk                 (0x1UL)        /*!< CTRLPDI (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_EEP_CONF_FORCEECAT_Pos               (1UL)          /*!< FORCEECAT (Bit 1)                                     */
+ #define R_ESC_EEP_CONF_FORCEECAT_Msk               (0x2UL)        /*!< FORCEECAT (Bitfield-Mask: 0x01)                       */
+/* =======================================================  EEP_STATE  ======================================================= */
+ #define R_ESC_EEP_STATE_PDIACCESS_Pos              (0UL)          /*!< PDIACCESS (Bit 0)                                     */
+ #define R_ESC_EEP_STATE_PDIACCESS_Msk              (0x1UL)        /*!< PDIACCESS (Bitfield-Mask: 0x01)                       */
+/* =====================================================  EEP_CONT_STAT  ===================================================== */
+ #define R_ESC_EEP_CONT_STAT_ECATWREN_Pos           (0UL)          /*!< ECATWREN (Bit 0)                                      */
+ #define R_ESC_EEP_CONT_STAT_ECATWREN_Msk           (0x1UL)        /*!< ECATWREN (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_EEP_CONT_STAT_READBYTE_Pos           (6UL)          /*!< READBYTE (Bit 6)                                      */
+ #define R_ESC_EEP_CONT_STAT_READBYTE_Msk           (0x40UL)       /*!< READBYTE (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_EEP_CONT_STAT_PROMSIZE_Pos           (7UL)          /*!< PROMSIZE (Bit 7)                                      */
+ #define R_ESC_EEP_CONT_STAT_PROMSIZE_Msk           (0x80UL)       /*!< PROMSIZE (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_EEP_CONT_STAT_COMMAND_Pos            (8UL)          /*!< COMMAND (Bit 8)                                       */
+ #define R_ESC_EEP_CONT_STAT_COMMAND_Msk            (0x700UL)      /*!< COMMAND (Bitfield-Mask: 0x07)                         */
+ #define R_ESC_EEP_CONT_STAT_CKSUMERR_Pos           (11UL)         /*!< CKSUMERR (Bit 11)                                     */
+ #define R_ESC_EEP_CONT_STAT_CKSUMERR_Msk           (0x800UL)      /*!< CKSUMERR (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_EEP_CONT_STAT_LOADSTA_Pos            (12UL)         /*!< LOADSTA (Bit 12)                                      */
+ #define R_ESC_EEP_CONT_STAT_LOADSTA_Msk            (0x1000UL)     /*!< LOADSTA (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Pos          (13UL)         /*!< ACKCMDERR (Bit 13)                                    */
+ #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Msk          (0x2000UL)     /*!< ACKCMDERR (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_EEP_CONT_STAT_WRENERR_Pos            (14UL)         /*!< WRENERR (Bit 14)                                      */
+ #define R_ESC_EEP_CONT_STAT_WRENERR_Msk            (0x4000UL)     /*!< WRENERR (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_EEP_CONT_STAT_BUSY_Pos               (15UL)         /*!< BUSY (Bit 15)                                         */
+ #define R_ESC_EEP_CONT_STAT_BUSY_Msk               (0x8000UL)     /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ========================================================  EEP_ADR  ======================================================== */
+ #define R_ESC_EEP_ADR_ADDRESS_Pos                  (0UL)          /*!< ADDRESS (Bit 0)                                       */
+ #define R_ESC_EEP_ADR_ADDRESS_Msk                  (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  EEP_DATA  ======================================================== */
+ #define R_ESC_EEP_DATA_LODATA_Pos                  (0UL)          /*!< LODATA (Bit 0)                                        */
+ #define R_ESC_EEP_DATA_LODATA_Msk                  (0xffffUL)     /*!< LODATA (Bitfield-Mask: 0xffff)                        */
+ #define R_ESC_EEP_DATA_HIDATA_Pos                  (16UL)         /*!< HIDATA (Bit 16)                                       */
+ #define R_ESC_EEP_DATA_HIDATA_Msk                  (0xffff0000UL) /*!< HIDATA (Bitfield-Mask: 0xffff)                        */
+/* =====================================================  MII_CONT_STAT  ===================================================== */
+ #define R_ESC_MII_CONT_STAT_WREN_Pos               (0UL)          /*!< WREN (Bit 0)                                          */
+ #define R_ESC_MII_CONT_STAT_WREN_Msk               (0x1UL)        /*!< WREN (Bitfield-Mask: 0x01)                            */
+ #define R_ESC_MII_CONT_STAT_PDICTRL_Pos            (1UL)          /*!< PDICTRL (Bit 1)                                       */
+ #define R_ESC_MII_CONT_STAT_PDICTRL_Msk            (0x2UL)        /*!< PDICTRL (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_MII_CONT_STAT_MILINK_Pos             (2UL)          /*!< MILINK (Bit 2)                                        */
+ #define R_ESC_MII_CONT_STAT_MILINK_Msk             (0x4UL)        /*!< MILINK (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_MII_CONT_STAT_PHYOFFSET_Pos          (3UL)          /*!< PHYOFFSET (Bit 3)                                     */
+ #define R_ESC_MII_CONT_STAT_PHYOFFSET_Msk          (0xf8UL)       /*!< PHYOFFSET (Bitfield-Mask: 0x1f)                       */
+ #define R_ESC_MII_CONT_STAT_COMMAND_Pos            (8UL)          /*!< COMMAND (Bit 8)                                       */
+ #define R_ESC_MII_CONT_STAT_COMMAND_Msk            (0x300UL)      /*!< COMMAND (Bitfield-Mask: 0x03)                         */
+ #define R_ESC_MII_CONT_STAT_READERR_Pos            (13UL)         /*!< READERR (Bit 13)                                      */
+ #define R_ESC_MII_CONT_STAT_READERR_Msk            (0x2000UL)     /*!< READERR (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_MII_CONT_STAT_CMDERR_Pos             (14UL)         /*!< CMDERR (Bit 14)                                       */
+ #define R_ESC_MII_CONT_STAT_CMDERR_Msk             (0x4000UL)     /*!< CMDERR (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_MII_CONT_STAT_BUSY_Pos               (15UL)         /*!< BUSY (Bit 15)                                         */
+ #define R_ESC_MII_CONT_STAT_BUSY_Msk               (0x8000UL)     /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PHY_ADR  ======================================================== */
+ #define R_ESC_PHY_ADR_PHYADDR_Pos                  (0UL)          /*!< PHYADDR (Bit 0)                                       */
+ #define R_ESC_PHY_ADR_PHYADDR_Msk                  (0x1fUL)       /*!< PHYADDR (Bitfield-Mask: 0x1f)                         */
+/* ======================================================  PHY_REG_ADR  ====================================================== */
+ #define R_ESC_PHY_REG_ADR_PHYREGADDR_Pos           (0UL)          /*!< PHYREGADDR (Bit 0)                                    */
+ #define R_ESC_PHY_REG_ADR_PHYREGADDR_Msk           (0x1fUL)       /*!< PHYREGADDR (Bitfield-Mask: 0x1f)                      */
+/* =======================================================  PHY_DATA  ======================================================== */
+ #define R_ESC_PHY_DATA_PHYREGDATA_Pos              (0UL)          /*!< PHYREGDATA (Bit 0)                                    */
+ #define R_ESC_PHY_DATA_PHYREGDATA_Msk              (0xffffUL)     /*!< PHYREGDATA (Bitfield-Mask: 0xffff)                    */
+/* ===================================================  MII_ECAT_ACS_STAT  =================================================== */
+ #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Pos         (0UL)          /*!< ACSMII (Bit 0)                                        */
+ #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Msk         (0x1UL)        /*!< ACSMII (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MII_PDI_ACS_STAT  ==================================================== */
+ #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Pos          (0UL)          /*!< ACSMII (Bit 0)                                        */
+ #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Msk          (0x1UL)        /*!< ACSMII (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Pos          (1UL)          /*!< FORPDI (Bit 1)                                        */
+ #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Msk          (0x2UL)        /*!< FORPDI (Bitfield-Mask: 0x01)                          */
+/* ===================================================  DC_RCV_TIME_PORT  ==================================================== */
+ #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Pos        (0UL)          /*!< RCVTIME0 (Bit 0)                                      */
+ #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Msk        (0xffffffffUL) /*!< RCVTIME0 (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  DC_SYS_TIME_L  ===================================================== */
+/* =====================================================  DC_SYS_TIME_H  ===================================================== */
+/* ==================================================  DC_RCV_TIME_UNIT_L  =================================================== */
+/* ==================================================  DC_RCV_TIME_UNIT_H  =================================================== */
+/* =================================================  DC_SYS_TIME_OFFSET_L  ================================================== */
+/* =================================================  DC_SYS_TIME_OFFSET_H  ================================================== */
+/* ===================================================  DC_SYS_TIME_DELAY  =================================================== */
+ #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Pos             (0UL)          /*!< SYSTIMDLY (Bit 0)                                     */
+ #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Msk             (0xffffffffUL) /*!< SYSTIMDLY (Bitfield-Mask: 0xffffffff)                 */
+/* ===================================================  DC_SYS_TIME_DIFF  ==================================================== */
+ #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Pos                   (0UL)          /*!< DIFF (Bit 0)                                          */
+ #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Msk                   (0x7fffffffUL) /*!< DIFF (Bitfield-Mask: 0x7fffffff)                      */
+ #define R_ESC_DC_SYS_TIME_DIFF_LCP_Pos                    (31UL)         /*!< LCP (Bit 31)                                          */
+ #define R_ESC_DC_SYS_TIME_DIFF_LCP_Msk                    (0x80000000UL) /*!< LCP (Bitfield-Mask: 0x01)                             */
+/* =================================================  DC_SPEED_COUNT_START  ================================================== */
+ #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Pos         (0UL)          /*!< SPDCNTSTRT (Bit 0)                                    */
+ #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Msk         (0x7fffUL)     /*!< SPDCNTSTRT (Bitfield-Mask: 0x7fff)                    */
+/* ==================================================  DC_SPEED_COUNT_DIFF  ================================================== */
+ #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Pos          (0UL)          /*!< SPDCNTDIFF (Bit 0)                                    */
+ #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Msk          (0xffffUL)     /*!< SPDCNTDIFF (Bitfield-Mask: 0xffff)                    */
+/* ==============================================  DC_SYS_TIME_DIFF_FIL_DEPTH  =============================================== */
+ #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Pos    (0UL)          /*!< SYSTIMDEP (Bit 0)                                     */
+ #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Msk    (0xfUL)        /*!< SYSTIMDEP (Bitfield-Mask: 0x0f)                       */
+/* ===============================================  DC_SPEED_COUNT_FIL_DEPTH  ================================================ */
+ #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Pos      (0UL)          /*!< CLKPERDEP (Bit 0)                                     */
+ #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Msk      (0xfUL)        /*!< CLKPERDEP (Bitfield-Mask: 0x0f)                       */
+/* ======================================================  DC_CYC_CONT  ====================================================== */
+ #define R_ESC_DC_CYC_CONT_SYNCOUT_Pos                     (0UL)          /*!< SYNCOUT (Bit 0)                                       */
+ #define R_ESC_DC_CYC_CONT_SYNCOUT_Msk                     (0x1UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_CYC_CONT_LATCH0_Pos                      (4UL)          /*!< LATCH0 (Bit 4)                                        */
+ #define R_ESC_DC_CYC_CONT_LATCH0_Msk                      (0x10UL)       /*!< LATCH0 (Bitfield-Mask: 0x01)                          */
+ #define R_ESC_DC_CYC_CONT_LATCH1_Pos                      (5UL)          /*!< LATCH1 (Bit 5)                                        */
+ #define R_ESC_DC_CYC_CONT_LATCH1_Msk                      (0x20UL)       /*!< LATCH1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DC_ACT  ========================================================= */
+ #define R_ESC_DC_ACT_SYNCACT_Pos                          (0UL)          /*!< SYNCACT (Bit 0)                                       */
+ #define R_ESC_DC_ACT_SYNCACT_Msk                          (0x1UL)        /*!< SYNCACT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_ACT_SYNC0_Pos                            (1UL)          /*!< SYNC0 (Bit 1)                                         */
+ #define R_ESC_DC_ACT_SYNC0_Msk                            (0x2UL)        /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_DC_ACT_SYNC1_Pos                            (2UL)          /*!< SYNC1 (Bit 2)                                         */
+ #define R_ESC_DC_ACT_SYNC1_Msk                            (0x4UL)        /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
+ #define R_ESC_DC_ACT_AUTOACT_Pos                          (3UL)          /*!< AUTOACT (Bit 3)                                       */
+ #define R_ESC_DC_ACT_AUTOACT_Msk                          (0x8UL)        /*!< AUTOACT (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_ACT_EXTSTARTTIME_Pos                     (4UL)          /*!< EXTSTARTTIME (Bit 4)                                  */
+ #define R_ESC_DC_ACT_EXTSTARTTIME_Msk                     (0x10UL)       /*!< EXTSTARTTIME (Bitfield-Mask: 0x01)                    */
+ #define R_ESC_DC_ACT_STARTTIME_Pos                        (5UL)          /*!< STARTTIME (Bit 5)                                     */
+ #define R_ESC_DC_ACT_STARTTIME_Msk                        (0x20UL)       /*!< STARTTIME (Bitfield-Mask: 0x01)                       */
+ #define R_ESC_DC_ACT_NEARFUTURE_Pos                       (6UL)          /*!< NEARFUTURE (Bit 6)                                    */
+ #define R_ESC_DC_ACT_NEARFUTURE_Msk                       (0x40UL)       /*!< NEARFUTURE (Bitfield-Mask: 0x01)                      */
+ #define R_ESC_DC_ACT_DBGPULSE_Pos                         (7UL)          /*!< DBGPULSE (Bit 7)                                      */
+ #define R_ESC_DC_ACT_DBGPULSE_Msk                         (0x80UL)       /*!< DBGPULSE (Bitfield-Mask: 0x01)                        */
+/* =====================================================  DC_PULSE_LEN  ====================================================== */
+ #define R_ESC_DC_PULSE_LEN_PULSELEN_Pos                   (0UL)          /*!< PULSELEN (Bit 0)                                      */
+ #define R_ESC_DC_PULSE_LEN_PULSELEN_Msk                   (0xffffUL)     /*!< PULSELEN (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  DC_ACT_STAT  ====================================================== */
+ #define R_ESC_DC_ACT_STAT_SYNC0ACT_Pos                    (0UL)          /*!< SYNC0ACT (Bit 0)                                      */
+ #define R_ESC_DC_ACT_STAT_SYNC0ACT_Msk                    (0x1UL)        /*!< SYNC0ACT (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_ACT_STAT_SYNC1ACT_Pos                    (1UL)          /*!< SYNC1ACT (Bit 1)                                      */
+ #define R_ESC_DC_ACT_STAT_SYNC1ACT_Msk                    (0x2UL)        /*!< SYNC1ACT (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_ACT_STAT_STARTTIME_Pos                   (2UL)          /*!< STARTTIME (Bit 2)                                     */
+ #define R_ESC_DC_ACT_STAT_STARTTIME_Msk                   (0x4UL)        /*!< STARTTIME (Bitfield-Mask: 0x01)                       */
+/* =====================================================  DC_SYNC0_STAT  ===================================================== */
+ #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Pos                  (0UL)          /*!< SYNC0STA (Bit 0)                                      */
+ #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Msk                  (0x1UL)        /*!< SYNC0STA (Bitfield-Mask: 0x01)                        */
+/* =====================================================  DC_SYNC1_STAT  ===================================================== */
+ #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Pos                  (0UL)          /*!< SYNC1STA (Bit 0)                                      */
+ #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Msk                  (0x1UL)        /*!< SYNC1STA (Bitfield-Mask: 0x01)                        */
+/* ==================================================  DC_CYC_START_TIME_L  ================================================== */
+/* ==================================================  DC_CYC_START_TIME_H  ================================================== */
+/* =================================================  DC_NEXT_SYNC1_PULSE_L  ================================================= */
+/* =================================================  DC_NEXT_SYNC1_PULSE_H  ================================================= */
+/* ===================================================  DC_SYNC0_CYC_TIME  =================================================== */
+ #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Pos    (0UL)          /*!< SYNC0CYC (Bit 0)                                      */
+ #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Msk    (0xffffffffUL) /*!< SYNC0CYC (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  DC_SYNC1_CYC_TIME  =================================================== */
+ #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Pos    (0UL)          /*!< SYNC1CYC (Bit 0)                                      */
+ #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Msk    (0xffffffffUL) /*!< SYNC1CYC (Bitfield-Mask: 0xffffffff)                  */
+/* ====================================================  DC_LATCH0_CONT  ===================================================== */
+ #define R_ESC_DC_LATCH0_CONT_POSEDGE_Pos        (0UL)          /*!< POSEDGE (Bit 0)                                       */
+ #define R_ESC_DC_LATCH0_CONT_POSEDGE_Msk        (0x1UL)        /*!< POSEDGE (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Pos        (1UL)          /*!< NEGEDGE (Bit 1)                                       */
+ #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Msk        (0x2UL)        /*!< NEGEDGE (Bitfield-Mask: 0x01)                         */
+/* ====================================================  DC_LATCH1_CONT  ===================================================== */
+ #define R_ESC_DC_LATCH1_CONT_POSEDGE_Pos        (0UL)          /*!< POSEDGE (Bit 0)                                       */
+ #define R_ESC_DC_LATCH1_CONT_POSEDGE_Msk        (0x1UL)        /*!< POSEDGE (Bitfield-Mask: 0x01)                         */
+ #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Pos        (1UL)          /*!< NEGEDGE (Bit 1)                                       */
+ #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Msk        (0x2UL)        /*!< NEGEDGE (Bitfield-Mask: 0x01)                         */
+/* ====================================================  DC_LATCH0_STAT  ===================================================== */
+ #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Pos       (0UL)          /*!< EVENTPOS (Bit 0)                                      */
+ #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Msk       (0x1UL)        /*!< EVENTPOS (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Pos       (1UL)          /*!< EVENTNEG (Bit 1)                                      */
+ #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Msk       (0x2UL)        /*!< EVENTNEG (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_LATCH0_STAT_PINSTATE_Pos       (2UL)          /*!< PINSTATE (Bit 2)                                      */
+ #define R_ESC_DC_LATCH0_STAT_PINSTATE_Msk       (0x4UL)        /*!< PINSTATE (Bitfield-Mask: 0x01)                        */
+/* ====================================================  DC_LATCH1_STAT  ===================================================== */
+ #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Pos       (0UL)          /*!< EVENTPOS (Bit 0)                                      */
+ #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Msk       (0x1UL)        /*!< EVENTPOS (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Pos       (1UL)          /*!< EVENTNEG (Bit 1)                                      */
+ #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Msk       (0x2UL)        /*!< EVENTNEG (Bitfield-Mask: 0x01)                        */
+ #define R_ESC_DC_LATCH1_STAT_PINSTATE_Pos       (2UL)          /*!< PINSTATE (Bit 2)                                      */
+ #define R_ESC_DC_LATCH1_STAT_PINSTATE_Msk       (0x4UL)        /*!< PINSTATE (Bitfield-Mask: 0x01)                        */
+/* =================================================  DC_LATCH0_TIME_POS_L  ================================================== */
+/* =================================================  DC_LATCH0_TIME_POS_H  ================================================== */
+/* =================================================  DC_LATCH0_TIME_NEG_L  ================================================== */
+/* =================================================  DC_LATCH0_TIME_NEG_H  ================================================== */
+/* =================================================  DC_LATCH1_TIME_POS_L  ================================================== */
+/* =================================================  DC_LATCH1_TIME_POS_H  ================================================== */
+/* =================================================  DC_LATCH1_TIME_NEG_L  ================================================== */
+/* =================================================  DC_LATCH1_TIME_NEG_H  ================================================== */
+/* ==================================================  DC_ECAT_CNG_EV_TIME  ================================================== */
+ #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Pos    (0UL)          /*!< ECATCHANGE (Bit 0)                                    */
+ #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Msk    (0xffffffffUL) /*!< ECATCHANGE (Bitfield-Mask: 0xffffffff)                */
+/* =================================================  DC_PDI_START_EV_TIME  ================================================== */
+ #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Pos     (0UL)          /*!< PDISTART (Bit 0)                                      */
+ #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Msk     (0xffffffffUL) /*!< PDISTART (Bitfield-Mask: 0xffffffff)                  */
+/* ==================================================  DC_PDI_CNG_EV_TIME  =================================================== */
+ #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Pos      (0UL)          /*!< PDICHANGE (Bit 0)                                     */
+ #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Msk      (0xffffffffUL) /*!< PDICHANGE (Bitfield-Mask: 0xffffffff)                 */
+/* =====================================================  PRODUCT_ID_L  ====================================================== */
+/* =====================================================  PRODUCT_ID_H  ====================================================== */
+/* ======================================================  VENDOR_ID_L  ====================================================== */
+ #define R_ESC_VENDOR_ID_L_VENDORID_Pos              (0UL)          /*!< VENDORID (Bit 0)                                      */
+ #define R_ESC_VENDOR_ID_L_VENDORID_Msk              (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff)                  */
+
+/* =========================================================================================================================== */
+/* ================                                          R_XSPI0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  WRAPCFG  ======================================================== */
+ #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos      (8UL)          /*!< DSSFTCS0 (Bit 8)                                      */
+ #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk      (0x1f00UL)     /*!< DSSFTCS0 (Bitfield-Mask: 0x1f)                        */
+ #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos      (24UL)         /*!< DSSFTCS1 (Bit 24)                                     */
+ #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk      (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f)                        */
+/* ========================================================  COMCFG  ========================================================= */
+ #define R_XSPI0_COMCFG_OEASTEX_Pos        (16UL)         /*!< OEASTEX (Bit 16)                                      */
+ #define R_XSPI0_COMCFG_OEASTEX_Msk        (0x10000UL)    /*!< OEASTEX (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_COMCFG_OENEGEX_Pos        (17UL)         /*!< OENEGEX (Bit 17)                                      */
+ #define R_XSPI0_COMCFG_OENEGEX_Msk        (0x20000UL)    /*!< OENEGEX (Bitfield-Mask: 0x01)                         */
+/* =========================================================  BMCFG  ========================================================= */
+ #define R_XSPI0_BMCFG_WRMD_Pos            (0UL)          /*!< WRMD (Bit 0)                                          */
+ #define R_XSPI0_BMCFG_WRMD_Msk            (0x1UL)        /*!< WRMD (Bitfield-Mask: 0x01)                            */
+ #define R_XSPI0_BMCFG_MWRCOMB_Pos         (7UL)          /*!< MWRCOMB (Bit 7)                                       */
+ #define R_XSPI0_BMCFG_MWRCOMB_Msk         (0x80UL)       /*!< MWRCOMB (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_BMCFG_MWRSIZE_Pos         (8UL)          /*!< MWRSIZE (Bit 8)                                       */
+ #define R_XSPI0_BMCFG_MWRSIZE_Msk         (0xff00UL)     /*!< MWRSIZE (Bitfield-Mask: 0xff)                         */
+ #define R_XSPI0_BMCFG_PREEN_Pos           (16UL)         /*!< PREEN (Bit 16)                                        */
+ #define R_XSPI0_BMCFG_PREEN_Msk           (0x10000UL)    /*!< PREEN (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_BMCFG_CMBTIM_Pos          (24UL)         /*!< CMBTIM (Bit 24)                                       */
+ #define R_XSPI0_BMCFG_CMBTIM_Msk          (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff)                          */
+/* =======================================================  LIOCFGCS  ======================================================== */
+ #define R_XSPI0_LIOCFGCS_PRTMD_Pos        (0UL)          /*!< PRTMD (Bit 0)                                         */
+ #define R_XSPI0_LIOCFGCS_PRTMD_Msk        (0x3ffUL)      /*!< PRTMD (Bitfield-Mask: 0x3ff)                          */
+ #define R_XSPI0_LIOCFGCS_LATEMD_Pos       (10UL)         /*!< LATEMD (Bit 10)                                       */
+ #define R_XSPI0_LIOCFGCS_LATEMD_Msk       (0x400UL)      /*!< LATEMD (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos      (11UL)         /*!< WRMSKMD (Bit 11)                                      */
+ #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk      (0x800UL)      /*!< WRMSKMD (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_LIOCFGCS_CSMIN_Pos        (16UL)         /*!< CSMIN (Bit 16)                                        */
+ #define R_XSPI0_LIOCFGCS_CSMIN_Msk        (0xf0000UL)    /*!< CSMIN (Bitfield-Mask: 0x0f)                           */
+ #define R_XSPI0_LIOCFGCS_CSASTEX_Pos      (20UL)         /*!< CSASTEX (Bit 20)                                      */
+ #define R_XSPI0_LIOCFGCS_CSASTEX_Msk      (0x100000UL)   /*!< CSASTEX (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos      (21UL)         /*!< CSNEGEX (Bit 21)                                      */
+ #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk      (0x200000UL)   /*!< CSNEGEX (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_LIOCFGCS_SDRDRV_Pos       (22UL)         /*!< SDRDRV (Bit 22)                                       */
+ #define R_XSPI0_LIOCFGCS_SDRDRV_Msk       (0x400000UL)   /*!< SDRDRV (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos     (23UL)         /*!< SDRSMPMD (Bit 23)                                     */
+ #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk     (0x800000UL)   /*!< SDRSMPMD (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos    (24UL)         /*!< SDRSMPSFT (Bit 24)                                    */
+ #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk    (0xf000000UL)  /*!< SDRSMPSFT (Bitfield-Mask: 0x0f)                       */
+ #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos     (28UL)         /*!< DDRSMPEX (Bit 28)                                     */
+ #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk     (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f)                        */
+/* ========================================================  BMCTL0  ========================================================= */
+ #define R_XSPI0_BMCTL0_CS0ACC_Pos         (0UL)          /*!< CS0ACC (Bit 0)                                        */
+ #define R_XSPI0_BMCTL0_CS0ACC_Msk         (0x3UL)        /*!< CS0ACC (Bitfield-Mask: 0x03)                          */
+ #define R_XSPI0_BMCTL0_CS1ACC_Pos         (2UL)          /*!< CS1ACC (Bit 2)                                        */
+ #define R_XSPI0_BMCTL0_CS1ACC_Msk         (0xcUL)        /*!< CS1ACC (Bitfield-Mask: 0x03)                          */
+/* ========================================================  BMCTL1  ========================================================= */
+ #define R_XSPI0_BMCTL1_MWRPUSH_Pos        (8UL)          /*!< MWRPUSH (Bit 8)                                       */
+ #define R_XSPI0_BMCTL1_MWRPUSH_Msk        (0x100UL)      /*!< MWRPUSH (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_BMCTL1_PBUFCLR_Pos        (10UL)         /*!< PBUFCLR (Bit 10)                                      */
+ #define R_XSPI0_BMCTL1_PBUFCLR_Msk        (0x400UL)      /*!< PBUFCLR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  CMCTL  ========================================================= */
+ #define R_XSPI0_CMCTL_XIPENCODE_Pos       (0UL)          /*!< XIPENCODE (Bit 0)                                     */
+ #define R_XSPI0_CMCTL_XIPENCODE_Msk       (0xffUL)       /*!< XIPENCODE (Bitfield-Mask: 0xff)                       */
+ #define R_XSPI0_CMCTL_XIPEXCODE_Pos       (8UL)          /*!< XIPEXCODE (Bit 8)                                     */
+ #define R_XSPI0_CMCTL_XIPEXCODE_Msk       (0xff00UL)     /*!< XIPEXCODE (Bitfield-Mask: 0xff)                       */
+ #define R_XSPI0_CMCTL_XIPEN_Pos           (16UL)         /*!< XIPEN (Bit 16)                                        */
+ #define R_XSPI0_CMCTL_XIPEN_Msk           (0x10000UL)    /*!< XIPEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CDCTL0  ========================================================= */
+ #define R_XSPI0_CDCTL0_TRREQ_Pos          (0UL)          /*!< TRREQ (Bit 0)                                         */
+ #define R_XSPI0_CDCTL0_TRREQ_Msk          (0x1UL)        /*!< TRREQ (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_CDCTL0_PERMD_Pos          (1UL)          /*!< PERMD (Bit 1)                                         */
+ #define R_XSPI0_CDCTL0_PERMD_Msk          (0x2UL)        /*!< PERMD (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_CDCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
+ #define R_XSPI0_CDCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_CDCTL0_TRNUM_Pos          (4UL)          /*!< TRNUM (Bit 4)                                         */
+ #define R_XSPI0_CDCTL0_TRNUM_Msk          (0x30UL)       /*!< TRNUM (Bitfield-Mask: 0x03)                           */
+ #define R_XSPI0_CDCTL0_PERITV_Pos         (16UL)         /*!< PERITV (Bit 16)                                       */
+ #define R_XSPI0_CDCTL0_PERITV_Msk         (0x1f0000UL)   /*!< PERITV (Bitfield-Mask: 0x1f)                          */
+ #define R_XSPI0_CDCTL0_PERREP_Pos         (24UL)         /*!< PERREP (Bit 24)                                       */
+ #define R_XSPI0_CDCTL0_PERREP_Msk         (0xf000000UL)  /*!< PERREP (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  CDCTL1  ========================================================= */
+ #define R_XSPI0_CDCTL1_PEREXP_Pos         (0UL)          /*!< PEREXP (Bit 0)                                        */
+ #define R_XSPI0_CDCTL1_PEREXP_Msk         (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CDCTL2  ========================================================= */
+ #define R_XSPI0_CDCTL2_PERMSK_Pos         (0UL)          /*!< PERMSK (Bit 0)                                        */
+ #define R_XSPI0_CDCTL2_PERMSK_Msk         (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  LPCTL0  ========================================================= */
+ #define R_XSPI0_LPCTL0_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
+ #define R_XSPI0_LPCTL0_PATREQ_Msk         (0x1UL)        /*!< PATREQ (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LPCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
+ #define R_XSPI0_LPCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_LPCTL0_XDPIN_Pos          (4UL)          /*!< XDPIN (Bit 4)                                         */
+ #define R_XSPI0_LPCTL0_XDPIN_Msk          (0x30UL)       /*!< XDPIN (Bitfield-Mask: 0x03)                           */
+ #define R_XSPI0_LPCTL0_XD1LEN_Pos         (16UL)         /*!< XD1LEN (Bit 16)                                       */
+ #define R_XSPI0_LPCTL0_XD1LEN_Msk         (0x1f0000UL)   /*!< XD1LEN (Bitfield-Mask: 0x1f)                          */
+ #define R_XSPI0_LPCTL0_XD1VAL_Pos         (23UL)         /*!< XD1VAL (Bit 23)                                       */
+ #define R_XSPI0_LPCTL0_XD1VAL_Msk         (0x800000UL)   /*!< XD1VAL (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LPCTL0_XD2LEN_Pos         (24UL)         /*!< XD2LEN (Bit 24)                                       */
+ #define R_XSPI0_LPCTL0_XD2LEN_Msk         (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f)                          */
+ #define R_XSPI0_LPCTL0_XD2VAL_Pos         (31UL)         /*!< XD2VAL (Bit 31)                                       */
+ #define R_XSPI0_LPCTL0_XD2VAL_Msk         (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01)                          */
+/* ========================================================  LPCTL1  ========================================================= */
+ #define R_XSPI0_LPCTL1_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
+ #define R_XSPI0_LPCTL1_PATREQ_Msk         (0x3UL)        /*!< PATREQ (Bitfield-Mask: 0x03)                          */
+ #define R_XSPI0_LPCTL1_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
+ #define R_XSPI0_LPCTL1_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_LPCTL1_RSTREP_Pos         (4UL)          /*!< RSTREP (Bit 4)                                        */
+ #define R_XSPI0_LPCTL1_RSTREP_Msk         (0x30UL)       /*!< RSTREP (Bitfield-Mask: 0x03)                          */
+ #define R_XSPI0_LPCTL1_RSTWID_Pos         (8UL)          /*!< RSTWID (Bit 8)                                        */
+ #define R_XSPI0_LPCTL1_RSTWID_Msk         (0x700UL)      /*!< RSTWID (Bitfield-Mask: 0x07)                          */
+ #define R_XSPI0_LPCTL1_RSTSU_Pos          (12UL)         /*!< RSTSU (Bit 12)                                        */
+ #define R_XSPI0_LPCTL1_RSTSU_Msk          (0x7000UL)     /*!< RSTSU (Bitfield-Mask: 0x07)                           */
+/* ========================================================  LIOCTL  ========================================================= */
+ #define R_XSPI0_LIOCTL_WPCS0_Pos          (0UL)          /*!< WPCS0 (Bit 0)                                         */
+ #define R_XSPI0_LIOCTL_WPCS0_Msk          (0x1UL)        /*!< WPCS0 (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_LIOCTL_WPCS1_Pos          (1UL)          /*!< WPCS1 (Bit 1)                                         */
+ #define R_XSPI0_LIOCTL_WPCS1_Msk          (0x2UL)        /*!< WPCS1 (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_LIOCTL_RSTCS0_Pos         (16UL)         /*!< RSTCS0 (Bit 16)                                       */
+ #define R_XSPI0_LIOCTL_RSTCS0_Msk         (0x10000UL)    /*!< RSTCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_LIOCTL_RSTCS1_Pos         (17UL)         /*!< RSTCS1 (Bit 17)                                       */
+ #define R_XSPI0_LIOCTL_RSTCS1_Msk         (0x20000UL)    /*!< RSTCS1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  VERSTT  ========================================================= */
+ #define R_XSPI0_VERSTT_VER_Pos            (0UL)          /*!< VER (Bit 0)                                           */
+ #define R_XSPI0_VERSTT_VER_Msk            (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  COMSTT  ========================================================= */
+ #define R_XSPI0_COMSTT_MEMACC_Pos         (0UL)          /*!< MEMACC (Bit 0)                                        */
+ #define R_XSPI0_COMSTT_MEMACC_Msk         (0x1UL)        /*!< MEMACC (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_PBUFNE_Pos         (4UL)          /*!< PBUFNE (Bit 4)                                        */
+ #define R_XSPI0_COMSTT_PBUFNE_Msk         (0x10UL)       /*!< PBUFNE (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_WRBUFNE_Pos        (6UL)          /*!< WRBUFNE (Bit 6)                                       */
+ #define R_XSPI0_COMSTT_WRBUFNE_Msk        (0x40UL)       /*!< WRBUFNE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_COMSTT_ECSCS0_Pos         (16UL)         /*!< ECSCS0 (Bit 16)                                       */
+ #define R_XSPI0_COMSTT_ECSCS0_Msk         (0x10000UL)    /*!< ECSCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_INTCS0_Pos         (17UL)         /*!< INTCS0 (Bit 17)                                       */
+ #define R_XSPI0_COMSTT_INTCS0_Msk         (0x20000UL)    /*!< INTCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_RSTOCS0_Pos        (18UL)         /*!< RSTOCS0 (Bit 18)                                      */
+ #define R_XSPI0_COMSTT_RSTOCS0_Msk        (0x40000UL)    /*!< RSTOCS0 (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_COMSTT_ECSCS1_Pos         (20UL)         /*!< ECSCS1 (Bit 20)                                       */
+ #define R_XSPI0_COMSTT_ECSCS1_Msk         (0x100000UL)   /*!< ECSCS1 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_INTCS1_Pos         (21UL)         /*!< INTCS1 (Bit 21)                                       */
+ #define R_XSPI0_COMSTT_INTCS1_Msk         (0x200000UL)   /*!< INTCS1 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_COMSTT_RSTOCS1_Pos        (22UL)         /*!< RSTOCS1 (Bit 22)                                      */
+ #define R_XSPI0_COMSTT_RSTOCS1_Msk        (0x400000UL)   /*!< RSTOCS1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  CASTTCS  ======================================================== */
+ #define R_XSPI0_CASTTCS_CASUC_Pos         (0UL)          /*!< CASUC (Bit 0)                                         */
+ #define R_XSPI0_CASTTCS_CASUC_Msk         (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  INTS  ========================================================== */
+ #define R_XSPI0_INTS_CMDCMP_Pos           (0UL)          /*!< CMDCMP (Bit 0)                                        */
+ #define R_XSPI0_INTS_CMDCMP_Msk           (0x1UL)        /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_PATCMP_Pos           (1UL)          /*!< PATCMP (Bit 1)                                        */
+ #define R_XSPI0_INTS_PATCMP_Msk           (0x2UL)        /*!< PATCMP (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_INICMP_Pos           (2UL)          /*!< INICMP (Bit 2)                                        */
+ #define R_XSPI0_INTS_INICMP_Msk           (0x4UL)        /*!< INICMP (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_PERTO_Pos            (3UL)          /*!< PERTO (Bit 3)                                         */
+ #define R_XSPI0_INTS_PERTO_Msk            (0x8UL)        /*!< PERTO (Bitfield-Mask: 0x01)                           */
+ #define R_XSPI0_INTS_DSTOCS0_Pos          (4UL)          /*!< DSTOCS0 (Bit 4)                                       */
+ #define R_XSPI0_INTS_DSTOCS0_Msk          (0x10UL)       /*!< DSTOCS0 (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTS_DSTOCS1_Pos          (5UL)          /*!< DSTOCS1 (Bit 5)                                       */
+ #define R_XSPI0_INTS_DSTOCS1_Msk          (0x20UL)       /*!< DSTOCS1 (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTS_ECSCS0_Pos           (8UL)          /*!< ECSCS0 (Bit 8)                                        */
+ #define R_XSPI0_INTS_ECSCS0_Msk           (0x100UL)      /*!< ECSCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_ECSCS1_Pos           (9UL)          /*!< ECSCS1 (Bit 9)                                        */
+ #define R_XSPI0_INTS_ECSCS1_Msk           (0x200UL)      /*!< ECSCS1 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_INTCS0_Pos           (12UL)         /*!< INTCS0 (Bit 12)                                       */
+ #define R_XSPI0_INTS_INTCS0_Msk           (0x1000UL)     /*!< INTCS0 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_INTCS1_Pos           (13UL)         /*!< INTCS1 (Bit 13)                                       */
+ #define R_XSPI0_INTS_INTCS1_Msk           (0x2000UL)     /*!< INTCS1 (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_BUSERR_Pos           (20UL)         /*!< BUSERR (Bit 20)                                       */
+ #define R_XSPI0_INTS_BUSERR_Msk           (0x100000UL)   /*!< BUSERR (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTS_CAFAILCS0_Pos        (28UL)         /*!< CAFAILCS0 (Bit 28)                                    */
+ #define R_XSPI0_INTS_CAFAILCS0_Msk        (0x10000000UL) /*!< CAFAILCS0 (Bitfield-Mask: 0x01)                       */
+ #define R_XSPI0_INTS_CAFAILCS1_Pos        (29UL)         /*!< CAFAILCS1 (Bit 29)                                    */
+ #define R_XSPI0_INTS_CAFAILCS1_Msk        (0x20000000UL) /*!< CAFAILCS1 (Bitfield-Mask: 0x01)                       */
+ #define R_XSPI0_INTS_CASUCCS0_Pos         (30UL)         /*!< CASUCCS0 (Bit 30)                                     */
+ #define R_XSPI0_INTS_CASUCCS0_Msk         (0x40000000UL) /*!< CASUCCS0 (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTS_CASUCCS1_Pos         (31UL)         /*!< CASUCCS1 (Bit 31)                                     */
+ #define R_XSPI0_INTS_CASUCCS1_Msk         (0x80000000UL) /*!< CASUCCS1 (Bitfield-Mask: 0x01)                        */
+/* =========================================================  INTC  ========================================================== */
+ #define R_XSPI0_INTC_CMDCMPC_Pos          (0UL)          /*!< CMDCMPC (Bit 0)                                       */
+ #define R_XSPI0_INTC_CMDCMPC_Msk          (0x1UL)        /*!< CMDCMPC (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_PATCMPC_Pos          (1UL)          /*!< PATCMPC (Bit 1)                                       */
+ #define R_XSPI0_INTC_PATCMPC_Msk          (0x2UL)        /*!< PATCMPC (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_INICMPC_Pos          (2UL)          /*!< INICMPC (Bit 2)                                       */
+ #define R_XSPI0_INTC_INICMPC_Msk          (0x4UL)        /*!< INICMPC (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_PERTOC_Pos           (3UL)          /*!< PERTOC (Bit 3)                                        */
+ #define R_XSPI0_INTC_PERTOC_Msk           (0x8UL)        /*!< PERTOC (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTC_DSTOCS0C_Pos         (4UL)          /*!< DSTOCS0C (Bit 4)                                      */
+ #define R_XSPI0_INTC_DSTOCS0C_Msk         (0x10UL)       /*!< DSTOCS0C (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTC_DSTOCS1C_Pos         (5UL)          /*!< DSTOCS1C (Bit 5)                                      */
+ #define R_XSPI0_INTC_DSTOCS1C_Msk         (0x20UL)       /*!< DSTOCS1C (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTC_ECSCS0C_Pos          (8UL)          /*!< ECSCS0C (Bit 8)                                       */
+ #define R_XSPI0_INTC_ECSCS0C_Msk          (0x100UL)      /*!< ECSCS0C (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_ECSCS1C_Pos          (9UL)          /*!< ECSCS1C (Bit 9)                                       */
+ #define R_XSPI0_INTC_ECSCS1C_Msk          (0x200UL)      /*!< ECSCS1C (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_INTCS0C_Pos          (12UL)         /*!< INTCS0C (Bit 12)                                      */
+ #define R_XSPI0_INTC_INTCS0C_Msk          (0x1000UL)     /*!< INTCS0C (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_INTCS1C_Pos          (13UL)         /*!< INTCS1C (Bit 13)                                      */
+ #define R_XSPI0_INTC_INTCS1C_Msk          (0x2000UL)     /*!< INTCS1C (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_BUSERRC_Pos          (20UL)         /*!< BUSERRC (Bit 20)                                      */
+ #define R_XSPI0_INTC_BUSERRC_Msk          (0x100000UL)   /*!< BUSERRC (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTC_CAFAILCS0C_Pos       (28UL)         /*!< CAFAILCS0C (Bit 28)                                   */
+ #define R_XSPI0_INTC_CAFAILCS0C_Msk       (0x10000000UL) /*!< CAFAILCS0C (Bitfield-Mask: 0x01)                      */
+ #define R_XSPI0_INTC_CAFAILCS1C_Pos       (29UL)         /*!< CAFAILCS1C (Bit 29)                                   */
+ #define R_XSPI0_INTC_CAFAILCS1C_Msk       (0x20000000UL) /*!< CAFAILCS1C (Bitfield-Mask: 0x01)                      */
+ #define R_XSPI0_INTC_CASUCCS0C_Pos        (30UL)         /*!< CASUCCS0C (Bit 30)                                    */
+ #define R_XSPI0_INTC_CASUCCS0C_Msk        (0x40000000UL) /*!< CASUCCS0C (Bitfield-Mask: 0x01)                       */
+ #define R_XSPI0_INTC_CASUCCS1C_Pos        (31UL)         /*!< CASUCCS1C (Bit 31)                                    */
+ #define R_XSPI0_INTC_CASUCCS1C_Msk        (0x80000000UL) /*!< CASUCCS1C (Bitfield-Mask: 0x01)                       */
+/* =========================================================  INTE  ========================================================== */
+ #define R_XSPI0_INTE_CMDCMPE_Pos          (0UL)          /*!< CMDCMPE (Bit 0)                                       */
+ #define R_XSPI0_INTE_CMDCMPE_Msk          (0x1UL)        /*!< CMDCMPE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_PATCMPE_Pos          (1UL)          /*!< PATCMPE (Bit 1)                                       */
+ #define R_XSPI0_INTE_PATCMPE_Msk          (0x2UL)        /*!< PATCMPE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_INICMPE_Pos          (2UL)          /*!< INICMPE (Bit 2)                                       */
+ #define R_XSPI0_INTE_INICMPE_Msk          (0x4UL)        /*!< INICMPE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_PERTOE_Pos           (3UL)          /*!< PERTOE (Bit 3)                                        */
+ #define R_XSPI0_INTE_PERTOE_Msk           (0x8UL)        /*!< PERTOE (Bitfield-Mask: 0x01)                          */
+ #define R_XSPI0_INTE_DSTOCS0E_Pos         (4UL)          /*!< DSTOCS0E (Bit 4)                                      */
+ #define R_XSPI0_INTE_DSTOCS0E_Msk         (0x10UL)       /*!< DSTOCS0E (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTE_DSTOCS1E_Pos         (5UL)          /*!< DSTOCS1E (Bit 5)                                      */
+ #define R_XSPI0_INTE_DSTOCS1E_Msk         (0x20UL)       /*!< DSTOCS1E (Bitfield-Mask: 0x01)                        */
+ #define R_XSPI0_INTE_ECSCS0E_Pos          (8UL)          /*!< ECSCS0E (Bit 8)                                       */
+ #define R_XSPI0_INTE_ECSCS0E_Msk          (0x100UL)      /*!< ECSCS0E (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_ECSCS1E_Pos          (9UL)          /*!< ECSCS1E (Bit 9)                                       */
+ #define R_XSPI0_INTE_ECSCS1E_Msk          (0x200UL)      /*!< ECSCS1E (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_INTCS0E_Pos          (12UL)         /*!< INTCS0E (Bit 12)                                      */
+ #define R_XSPI0_INTE_INTCS0E_Msk          (0x1000UL)     /*!< INTCS0E (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_INTCS1E_Pos          (13UL)         /*!< INTCS1E (Bit 13)                                      */
+ #define R_XSPI0_INTE_INTCS1E_Msk          (0x2000UL)     /*!< INTCS1E (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_BUSERRE_Pos          (20UL)         /*!< BUSERRE (Bit 20)                                      */
+ #define R_XSPI0_INTE_BUSERRE_Msk          (0x100000UL)   /*!< BUSERRE (Bitfield-Mask: 0x01)                         */
+ #define R_XSPI0_INTE_CAFAILCS0E_Pos       (28UL)         /*!< CAFAILCS0E (Bit 28)                                   */
+ #define R_XSPI0_INTE_CAFAILCS0E_Msk       (0x10000000UL) /*!< CAFAILCS0E (Bitfield-Mask: 0x01)                      */
+ #define R_XSPI0_INTE_CAFAILCS1E_Pos       (29UL)         /*!< CAFAILCS1E (Bit 29)                                   */
+ #define R_XSPI0_INTE_CAFAILCS1E_Msk       (0x20000000UL) /*!< CAFAILCS1E (Bitfield-Mask: 0x01)                      */
+ #define R_XSPI0_INTE_CASUCCS0E_Pos        (30UL)         /*!< CASUCCS0E (Bit 30)                                    */
+ #define R_XSPI0_INTE_CASUCCS0E_Msk        (0x40000000UL) /*!< CASUCCS0E (Bitfield-Mask: 0x01)                       */
+ #define R_XSPI0_INTE_CASUCCS1E_Pos        (31UL)         /*!< CASUCCS1E (Bit 31)                                    */
+ #define R_XSPI0_INTE_CASUCCS1E_Msk        (0x80000000UL) /*!< CASUCCS1E (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BSC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CMNCR  ========================================================= */
+ #define R_BSC_CMNCR_DPRTY_Pos        (9UL)          /*!< DPRTY (Bit 9)                                         */
+ #define R_BSC_CMNCR_DPRTY_Msk        (0x600UL)      /*!< DPRTY (Bitfield-Mask: 0x03)                           */
+ #define R_BSC_CMNCR_AL_Pos           (24UL)         /*!< AL (Bit 24)                                           */
+ #define R_BSC_CMNCR_AL_Msk           (0x1000000UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CMNCR_TL_Pos           (28UL)         /*!< TL (Bit 28)                                           */
+ #define R_BSC_CMNCR_TL_Msk           (0x10000000UL) /*!< TL (Bitfield-Mask: 0x01)                              */
+/* ========================================================  CSnBCR  ========================================================= */
+ #define R_BSC_CSnBCR_BSZ_Pos         (9UL)          /*!< BSZ (Bit 9)                                           */
+ #define R_BSC_CSnBCR_BSZ_Msk         (0x600UL)      /*!< BSZ (Bitfield-Mask: 0x03)                             */
+ #define R_BSC_CSnBCR_TYPE_Pos        (12UL)         /*!< TYPE (Bit 12)                                         */
+ #define R_BSC_CSnBCR_TYPE_Msk        (0x7000UL)     /*!< TYPE (Bitfield-Mask: 0x07)                            */
+ #define R_BSC_CSnBCR_IWRRS_Pos       (16UL)         /*!< IWRRS (Bit 16)                                        */
+ #define R_BSC_CSnBCR_IWRRS_Msk       (0x70000UL)    /*!< IWRRS (Bitfield-Mask: 0x07)                           */
+ #define R_BSC_CSnBCR_IWRRD_Pos       (19UL)         /*!< IWRRD (Bit 19)                                        */
+ #define R_BSC_CSnBCR_IWRRD_Msk       (0x380000UL)   /*!< IWRRD (Bitfield-Mask: 0x07)                           */
+ #define R_BSC_CSnBCR_IWRWS_Pos       (22UL)         /*!< IWRWS (Bit 22)                                        */
+ #define R_BSC_CSnBCR_IWRWS_Msk       (0x1c00000UL)  /*!< IWRWS (Bitfield-Mask: 0x07)                           */
+ #define R_BSC_CSnBCR_IWRWD_Pos       (25UL)         /*!< IWRWD (Bit 25)                                        */
+ #define R_BSC_CSnBCR_IWRWD_Msk       (0xe000000UL)  /*!< IWRWD (Bitfield-Mask: 0x07)                           */
+ #define R_BSC_CSnBCR_IWW_Pos         (28UL)         /*!< IWW (Bit 28)                                          */
+ #define R_BSC_CSnBCR_IWW_Msk         (0x70000000UL) /*!< IWW (Bitfield-Mask: 0x07)                             */
+/* =======================================================  CS0WCR_0  ======================================================== */
+ #define R_BSC_CS0WCR_0_HW_Pos        (0UL)          /*!< HW (Bit 0)                                            */
+ #define R_BSC_CS0WCR_0_HW_Msk        (0x3UL)        /*!< HW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS0WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS0WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS0WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
+ #define R_BSC_CS0WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
+ #define R_BSC_CS0WCR_0_SW_Pos        (11UL)         /*!< SW (Bit 11)                                           */
+ #define R_BSC_CS0WCR_0_SW_Msk        (0x1800UL)     /*!< SW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS0WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
+ #define R_BSC_CS0WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
+/* =======================================================  CS0WCR_1  ======================================================== */
+ #define R_BSC_CS0WCR_1_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS0WCR_1_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS0WCR_1_W_Pos         (7UL)          /*!< W (Bit 7)                                             */
+ #define R_BSC_CS0WCR_1_W_Msk         (0x780UL)      /*!< W (Bitfield-Mask: 0x0f)                               */
+ #define R_BSC_CS0WCR_1_BW_Pos        (16UL)         /*!< BW (Bit 16)                                           */
+ #define R_BSC_CS0WCR_1_BW_Msk        (0x30000UL)    /*!< BW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS0WCR_1_BST_Pos       (20UL)         /*!< BST (Bit 20)                                          */
+ #define R_BSC_CS0WCR_1_BST_Msk       (0x300000UL)   /*!< BST (Bitfield-Mask: 0x03)                             */
+/* =======================================================  CS0WCR_2  ======================================================== */
+ #define R_BSC_CS0WCR_2_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS0WCR_2_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS0WCR_2_W_Pos         (7UL)          /*!< W (Bit 7)                                             */
+ #define R_BSC_CS0WCR_2_W_Msk         (0x780UL)      /*!< W (Bitfield-Mask: 0x0f)                               */
+ #define R_BSC_CS0WCR_2_BW_Pos        (16UL)         /*!< BW (Bit 16)                                           */
+ #define R_BSC_CS0WCR_2_BW_Msk        (0x30000UL)    /*!< BW (Bitfield-Mask: 0x03)                              */
+/* =======================================================  CS2WCR_0  ======================================================== */
+ #define R_BSC_CS2WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS2WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS2WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
+ #define R_BSC_CS2WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
+ #define R_BSC_CS2WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
+ #define R_BSC_CS2WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
+/* =======================================================  CS3WCR_0  ======================================================== */
+ #define R_BSC_CS3WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS3WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS3WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
+ #define R_BSC_CS3WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
+ #define R_BSC_CS3WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
+ #define R_BSC_CS3WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CS5WCR  ========================================================= */
+ #define R_BSC_CS5WCR_HW_Pos          (0UL)          /*!< HW (Bit 0)                                            */
+ #define R_BSC_CS5WCR_HW_Msk          (0x3UL)        /*!< HW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS5WCR_WM_Pos          (6UL)          /*!< WM (Bit 6)                                            */
+ #define R_BSC_CS5WCR_WM_Msk          (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
+ #define R_BSC_CS5WCR_WR_Pos          (7UL)          /*!< WR (Bit 7)                                            */
+ #define R_BSC_CS5WCR_WR_Msk          (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
+ #define R_BSC_CS5WCR_SW_Pos          (11UL)         /*!< SW (Bit 11)                                           */
+ #define R_BSC_CS5WCR_SW_Msk          (0x1800UL)     /*!< SW (Bitfield-Mask: 0x03)                              */
+ #define R_BSC_CS5WCR_WW_Pos          (16UL)         /*!< WW (Bit 16)                                           */
+ #define R_BSC_CS5WCR_WW_Msk          (0x70000UL)    /*!< WW (Bitfield-Mask: 0x07)                              */
+ #define R_BSC_CS5WCR_MPXWSBAS_Pos    (20UL)         /*!< MPXWSBAS (Bit 20)                                     */
+ #define R_BSC_CS5WCR_MPXWSBAS_Msk    (0x100000UL)   /*!< MPXWSBAS (Bitfield-Mask: 0x01)                        */
+ #define R_BSC_CS5WCR_SZSEL_Pos       (21UL)         /*!< SZSEL (Bit 21)                                        */
+ #define R_BSC_CS5WCR_SZSEL_Msk       (0x200000UL)   /*!< SZSEL (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TOSCOR  ========================================================= */
+ #define R_BSC_TOSCOR_TOCNUM_Pos      (0UL)          /*!< TOCNUM (Bit 0)                                        */
+ #define R_BSC_TOSCOR_TOCNUM_Msk      (0xffffUL)     /*!< TOCNUM (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  TOSTR  ========================================================= */
+ #define R_BSC_TOSTR_CS0TOSTF_Pos     (0UL)          /*!< CS0TOSTF (Bit 0)                                      */
+ #define R_BSC_TOSTR_CS0TOSTF_Msk     (0x1UL)        /*!< CS0TOSTF (Bitfield-Mask: 0x01)                        */
+ #define R_BSC_TOSTR_CS2TOSTF_Pos     (2UL)          /*!< CS2TOSTF (Bit 2)                                      */
+ #define R_BSC_TOSTR_CS2TOSTF_Msk     (0x4UL)        /*!< CS2TOSTF (Bitfield-Mask: 0x01)                        */
+ #define R_BSC_TOSTR_CS3TOSTF_Pos     (3UL)          /*!< CS3TOSTF (Bit 3)                                      */
+ #define R_BSC_TOSTR_CS3TOSTF_Msk     (0x8UL)        /*!< CS3TOSTF (Bitfield-Mask: 0x01)                        */
+ #define R_BSC_TOSTR_CS5TOSTF_Pos     (5UL)          /*!< CS5TOSTF (Bit 5)                                      */
+ #define R_BSC_TOSTR_CS5TOSTF_Msk     (0x20UL)       /*!< CS5TOSTF (Bitfield-Mask: 0x01)                        */
+/* =========================================================  TOENR  ========================================================= */
+ #define R_BSC_TOENR_CS0TOEN_Pos      (0UL)          /*!< CS0TOEN (Bit 0)                                       */
+ #define R_BSC_TOENR_CS0TOEN_Msk      (0x1UL)        /*!< CS0TOEN (Bitfield-Mask: 0x01)                         */
+ #define R_BSC_TOENR_CS2TOEN_Pos      (2UL)          /*!< CS2TOEN (Bit 2)                                       */
+ #define R_BSC_TOENR_CS2TOEN_Msk      (0x4UL)        /*!< CS2TOEN (Bitfield-Mask: 0x01)                         */
+ #define R_BSC_TOENR_CS3TOEN_Pos      (3UL)          /*!< CS3TOEN (Bit 3)                                       */
+ #define R_BSC_TOENR_CS3TOEN_Msk      (0x8UL)        /*!< CS3TOEN (Bitfield-Mask: 0x01)                         */
+ #define R_BSC_TOENR_CS5TOEN_Pos      (5UL)          /*!< CS5TOEN (Bit 5)                                       */
+ #define R_BSC_TOENR_CS5TOEN_Msk      (0x20UL)       /*!< CS5TOEN (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MBXSEM                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SEM  ========================================================== */
+ #define R_MBXSEM_SEM_SEM_Pos                       (0UL)          /*!< SEM (Bit 0)                                           */
+ #define R_MBXSEM_SEM_SEM_Msk                       (0x1UL)        /*!< SEM (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SEMRCEN  ======================================================== */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN0_Pos              (0UL)          /*!< SEMRCEN0 (Bit 0)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN0_Msk              (0x1UL)        /*!< SEMRCEN0 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN1_Pos              (1UL)          /*!< SEMRCEN1 (Bit 1)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN1_Msk              (0x2UL)        /*!< SEMRCEN1 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN2_Pos              (2UL)          /*!< SEMRCEN2 (Bit 2)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN2_Msk              (0x4UL)        /*!< SEMRCEN2 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN3_Pos              (3UL)          /*!< SEMRCEN3 (Bit 3)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN3_Msk              (0x8UL)        /*!< SEMRCEN3 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN4_Pos              (4UL)          /*!< SEMRCEN4 (Bit 4)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN4_Msk              (0x10UL)       /*!< SEMRCEN4 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN5_Pos              (5UL)          /*!< SEMRCEN5 (Bit 5)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN5_Msk              (0x20UL)       /*!< SEMRCEN5 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN6_Pos              (6UL)          /*!< SEMRCEN6 (Bit 6)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN6_Msk              (0x40UL)       /*!< SEMRCEN6 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN7_Pos              (7UL)          /*!< SEMRCEN7 (Bit 7)                                      */
+ #define R_MBXSEM_SEMRCEN_SEMRCEN7_Msk              (0x80UL)       /*!< SEMRCEN7 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MBXH2C  ========================================================= */
+ #define R_MBXSEM_MBXH2C_MBX_Pos                    (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXH2C_MBX_Msk                    (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETH2C  ======================================================= */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Pos          (0UL)          /*!< MBX_INT0S (Bit 0)                                     */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Msk          (0x1UL)        /*!< MBX_INT0S (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Pos          (1UL)          /*!< MBX_INT1S (Bit 1)                                     */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Msk          (0x2UL)        /*!< MBX_INT1S (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Pos          (2UL)          /*!< MBX_INT2S (Bit 2)                                     */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Msk          (0x4UL)        /*!< MBX_INT2S (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Pos          (3UL)          /*!< MBX_INT3S (Bit 3)                                     */
+ #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Msk          (0x8UL)        /*!< MBX_INT3S (Bitfield-Mask: 0x01)                       */
+/* ======================================================  MBXICLRH2C  ======================================================= */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Pos          (0UL)          /*!< MBX_INT0C (Bit 0)                                     */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Msk          (0x1UL)        /*!< MBX_INT0C (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Pos          (1UL)          /*!< MBX_INT1C (Bit 1)                                     */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Msk          (0x2UL)        /*!< MBX_INT1C (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Pos          (2UL)          /*!< MBX_INT2C (Bit 2)                                     */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Msk          (0x4UL)        /*!< MBX_INT2C (Bitfield-Mask: 0x01)                       */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Pos          (3UL)          /*!< MBX_INT3C (Bit 3)                                     */
+ #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Msk          (0x8UL)        /*!< MBX_INT3C (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MBXC2H  ========================================================= */
+ #define R_MBXSEM_MBXC2H_MBX_Pos                    (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXC2H_MBX_Msk                    (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETC2H  ======================================================= */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Pos         (0UL)          /*!< MBX_HINT0S (Bit 0)                                    */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Msk         (0x1UL)        /*!< MBX_HINT0S (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Pos         (1UL)          /*!< MBX_HINT1S (Bit 1)                                    */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Msk         (0x2UL)        /*!< MBX_HINT1S (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Pos         (2UL)          /*!< MBX_HINT2S (Bit 2)                                    */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Msk         (0x4UL)        /*!< MBX_HINT2S (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Pos         (3UL)          /*!< MBX_HINT3S (Bit 3)                                    */
+ #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Msk         (0x8UL)        /*!< MBX_HINT3S (Bitfield-Mask: 0x01)                      */
+/* ======================================================  MBXICLRC2H  ======================================================= */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Pos         (0UL)          /*!< MBX_HINT0C (Bit 0)                                    */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Msk         (0x1UL)        /*!< MBX_HINT0C (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Pos         (1UL)          /*!< MBX_HINT1C (Bit 1)                                    */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Msk         (0x2UL)        /*!< MBX_HINT1C (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Pos         (2UL)          /*!< MBX_HINT2C (Bit 2)                                    */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Msk         (0x4UL)        /*!< MBX_HINT2C (Bitfield-Mask: 0x01)                      */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Pos         (3UL)          /*!< MBX_HINT3C (Bit 3)                                    */
+ #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Msk         (0x8UL)        /*!< MBX_HINT3C (Bitfield-Mask: 0x01)                      */
+/* =========================================================  SEMAR  ========================================================= */
+ #define R_MBXSEM_SEMAR_SEM_Pos                     (0UL)          /*!< SEM (Bit 0)                                           */
+ #define R_MBXSEM_SEMAR_SEM_Msk                     (0x1UL)        /*!< SEM (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SEMRCENAR  ======================================================= */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN0_Pos            (0UL)          /*!< SEMRCEN0 (Bit 0)                                      */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN0_Msk            (0x1UL)        /*!< SEMRCEN0 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN1_Pos            (1UL)          /*!< SEMRCEN1 (Bit 1)                                      */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN1_Msk            (0x2UL)        /*!< SEMRCEN1 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN2_Pos            (2UL)          /*!< SEMRCEN2 (Bit 2)                                      */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN2_Msk            (0x4UL)        /*!< SEMRCEN2 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN3_Pos            (3UL)          /*!< SEMRCEN3 (Bit 3)                                      */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN3_Msk            (0x8UL)        /*!< SEMRCEN3 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN4_Pos            (4UL)          /*!< SEMRCEN4 (Bit 4)                                      */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN4_Msk            (0x10UL)       /*!< SEMRCEN4 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN5_Pos            (5UL)          /*!< SEMRCEN5 (Bit 5)                                      */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN5_Msk            (0x20UL)       /*!< SEMRCEN5 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN6_Pos            (6UL)          /*!< SEMRCEN6 (Bit 6)                                      */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN6_Msk            (0x40UL)       /*!< SEMRCEN6 (Bitfield-Mask: 0x01)                        */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN7_Pos            (7UL)          /*!< SEMRCEN7 (Bit 7)                                      */
+ #define R_MBXSEM_SEMRCENAR_SEMRCEN7_Msk            (0x80UL)       /*!< SEMRCEN7 (Bitfield-Mask: 0x01)                        */
+/* =======================================================  MBXR0A00  ======================================================== */
+ #define R_MBXSEM_MBXR0A00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A01  ======================================================== */
+ #define R_MBXSEM_MBXR0A01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A02  ======================================================== */
+ #define R_MBXSEM_MBXR0A02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A03  ======================================================== */
+ #define R_MBXSEM_MBXR0A03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR0A0  ====================================================== */
+ #define R_MBXSEM_MBXISETR0A0_MBX_INTR0A0_0S_Pos    (0UL)          /*!< MBX_INTR0A0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR0A0_MBX_INTR0A0_0S_Msk    (0x1UL)        /*!< MBX_INTR0A0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A0_MBX_INTR0A0_1S_Pos    (1UL)          /*!< MBX_INTR0A0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR0A0_MBX_INTR0A0_1S_Msk    (0x2UL)        /*!< MBX_INTR0A0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A0_MBX_INTR0A0_2S_Pos    (2UL)          /*!< MBX_INTR0A0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR0A0_MBX_INTR0A0_2S_Msk    (0x4UL)        /*!< MBX_INTR0A0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A0_MBX_INTR0A0_3S_Pos    (3UL)          /*!< MBX_INTR0A0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR0A0_MBX_INTR0A0_3S_Msk    (0x8UL)        /*!< MBX_INTR0A0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR0A0  ====================================================== */
+ #define R_MBXSEM_MBXICLRR0A0_MBX_INTR0A0_0C_Pos    (0UL)          /*!< MBX_INTR0A0_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR0A0_MBX_INTR0A0_0C_Msk    (0x1UL)        /*!< MBX_INTR0A0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A0_MBX_INTR0A0_1C_Pos    (1UL)          /*!< MBX_INTR0A0_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR0A0_MBX_INTR0A0_1C_Msk    (0x2UL)        /*!< MBX_INTR0A0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A0_MBX_INTR0A0_2C_Pos    (2UL)          /*!< MBX_INTR0A0_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR0A0_MBX_INTR0A0_2C_Msk    (0x4UL)        /*!< MBX_INTR0A0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A0_MBX_INTR0A0_3C_Pos    (3UL)          /*!< MBX_INTR0A0_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR0A0_MBX_INTR0A0_3C_Msk    (0x8UL)        /*!< MBX_INTR0A0_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR0A10  ======================================================== */
+ #define R_MBXSEM_MBXR0A10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A11  ======================================================== */
+ #define R_MBXSEM_MBXR0A11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A12  ======================================================== */
+ #define R_MBXSEM_MBXR0A12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A13  ======================================================== */
+ #define R_MBXSEM_MBXR0A13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR0A1  ====================================================== */
+ #define R_MBXSEM_MBXISETR0A1_MBX_INTR0A1_0S_Pos    (0UL)          /*!< MBX_INTR0A1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR0A1_MBX_INTR0A1_0S_Msk    (0x1UL)        /*!< MBX_INTR0A1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A1_MBX_INTR0A1_1S_Pos    (1UL)          /*!< MBX_INTR0A1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR0A1_MBX_INTR0A1_1S_Msk    (0x2UL)        /*!< MBX_INTR0A1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A1_MBX_INTR0A1_2S_Pos    (2UL)          /*!< MBX_INTR0A1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR0A1_MBX_INTR0A1_2S_Msk    (0x4UL)        /*!< MBX_INTR0A1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A1_MBX_INTR0A1_3S_Pos    (3UL)          /*!< MBX_INTR0A1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR0A1_MBX_INTR0A1_3S_Msk    (0x8UL)        /*!< MBX_INTR0A1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR0A1  ====================================================== */
+ #define R_MBXSEM_MBXICLRR0A1_MBX_INTR0A1_0C_Pos    (0UL)          /*!< MBX_INTR0A1_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR0A1_MBX_INTR0A1_0C_Msk    (0x1UL)        /*!< MBX_INTR0A1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A1_MBX_INTR0A1_1C_Pos    (1UL)          /*!< MBX_INTR0A1_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR0A1_MBX_INTR0A1_1C_Msk    (0x2UL)        /*!< MBX_INTR0A1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A1_MBX_INTR0A1_2C_Pos    (2UL)          /*!< MBX_INTR0A1_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR0A1_MBX_INTR0A1_2C_Msk    (0x4UL)        /*!< MBX_INTR0A1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A1_MBX_INTR0A1_3C_Pos    (3UL)          /*!< MBX_INTR0A1_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR0A1_MBX_INTR0A1_3C_Msk    (0x8UL)        /*!< MBX_INTR0A1_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR0A20  ======================================================== */
+ #define R_MBXSEM_MBXR0A20_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A20_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A21  ======================================================== */
+ #define R_MBXSEM_MBXR0A21_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A21_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A22  ======================================================== */
+ #define R_MBXSEM_MBXR0A22_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A22_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A23  ======================================================== */
+ #define R_MBXSEM_MBXR0A23_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A23_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR0A2  ====================================================== */
+ #define R_MBXSEM_MBXISETR0A2_MBX_INTR0A2_0S_Pos    (0UL)          /*!< MBX_INTR0A2_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR0A2_MBX_INTR0A2_0S_Msk    (0x1UL)        /*!< MBX_INTR0A2_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A2_MBX_INTR0A2_1S_Pos    (1UL)          /*!< MBX_INTR0A2_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR0A2_MBX_INTR0A2_1S_Msk    (0x2UL)        /*!< MBX_INTR0A2_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A2_MBX_INTR0A2_2S_Pos    (2UL)          /*!< MBX_INTR0A2_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR0A2_MBX_INTR0A2_2S_Msk    (0x4UL)        /*!< MBX_INTR0A2_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A2_MBX_INTR0A2_3S_Pos    (3UL)          /*!< MBX_INTR0A2_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR0A2_MBX_INTR0A2_3S_Msk    (0x8UL)        /*!< MBX_INTR0A2_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR0A2  ====================================================== */
+ #define R_MBXSEM_MBXICLRR0A2_MBX_INTR0A2_0C_Pos    (0UL)          /*!< MBX_INTR0A2_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR0A2_MBX_INTR0A2_0C_Msk    (0x1UL)        /*!< MBX_INTR0A2_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A2_MBX_INTR0A2_1C_Pos    (1UL)          /*!< MBX_INTR0A2_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR0A2_MBX_INTR0A2_1C_Msk    (0x2UL)        /*!< MBX_INTR0A2_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A2_MBX_INTR0A2_2C_Pos    (2UL)          /*!< MBX_INTR0A2_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR0A2_MBX_INTR0A2_2C_Msk    (0x4UL)        /*!< MBX_INTR0A2_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A2_MBX_INTR0A2_3C_Pos    (3UL)          /*!< MBX_INTR0A2_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR0A2_MBX_INTR0A2_3C_Msk    (0x8UL)        /*!< MBX_INTR0A2_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR0A30  ======================================================== */
+ #define R_MBXSEM_MBXR0A30_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A30_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A31  ======================================================== */
+ #define R_MBXSEM_MBXR0A31_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A31_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A32  ======================================================== */
+ #define R_MBXSEM_MBXR0A32_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A32_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0A33  ======================================================== */
+ #define R_MBXSEM_MBXR0A33_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0A33_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR0A3  ====================================================== */
+ #define R_MBXSEM_MBXISETR0A3_MBX_INTR0A3_0S_Pos    (0UL)          /*!< MBX_INTR0A3_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR0A3_MBX_INTR0A3_0S_Msk    (0x1UL)        /*!< MBX_INTR0A3_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A3_MBX_INTR0A3_1S_Pos    (1UL)          /*!< MBX_INTR0A3_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR0A3_MBX_INTR0A3_1S_Msk    (0x2UL)        /*!< MBX_INTR0A3_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A3_MBX_INTR0A3_2S_Pos    (2UL)          /*!< MBX_INTR0A3_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR0A3_MBX_INTR0A3_2S_Msk    (0x4UL)        /*!< MBX_INTR0A3_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0A3_MBX_INTR0A3_3S_Pos    (3UL)          /*!< MBX_INTR0A3_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR0A3_MBX_INTR0A3_3S_Msk    (0x8UL)        /*!< MBX_INTR0A3_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR0A3  ====================================================== */
+ #define R_MBXSEM_MBXICLRR0A3_MBX_INTR0A3_0C_Pos    (0UL)          /*!< MBX_INTR0A3_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR0A3_MBX_INTR0A3_0C_Msk    (0x1UL)        /*!< MBX_INTR0A3_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A3_MBX_INTR0A3_1C_Pos    (1UL)          /*!< MBX_INTR0A3_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR0A3_MBX_INTR0A3_1C_Msk    (0x2UL)        /*!< MBX_INTR0A3_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A3_MBX_INTR0A3_2C_Pos    (2UL)          /*!< MBX_INTR0A3_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR0A3_MBX_INTR0A3_2C_Msk    (0x4UL)        /*!< MBX_INTR0A3_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0A3_MBX_INTR0A3_3C_Pos    (3UL)          /*!< MBX_INTR0A3_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR0A3_MBX_INTR0A3_3C_Msk    (0x8UL)        /*!< MBX_INTR0A3_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR1A00  ======================================================== */
+ #define R_MBXSEM_MBXR1A00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A01  ======================================================== */
+ #define R_MBXSEM_MBXR1A01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A02  ======================================================== */
+ #define R_MBXSEM_MBXR1A02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A03  ======================================================== */
+ #define R_MBXSEM_MBXR1A03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR1A0  ====================================================== */
+ #define R_MBXSEM_MBXISETR1A0_MBX_INTR1A0_0S_Pos    (0UL)          /*!< MBX_INTR1A0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR1A0_MBX_INTR1A0_0S_Msk    (0x1UL)        /*!< MBX_INTR1A0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A0_MBX_INTR1A0_1S_Pos    (1UL)          /*!< MBX_INTR1A0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR1A0_MBX_INTR1A0_1S_Msk    (0x2UL)        /*!< MBX_INTR1A0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A0_MBX_INTR1A0_2S_Pos    (2UL)          /*!< MBX_INTR1A0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR1A0_MBX_INTR1A0_2S_Msk    (0x4UL)        /*!< MBX_INTR1A0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A0_MBX_INTR1A0_3S_Pos    (3UL)          /*!< MBX_INTR1A0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR1A0_MBX_INTR1A0_3S_Msk    (0x8UL)        /*!< MBX_INTR1A0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR1A0  ====================================================== */
+ #define R_MBXSEM_MBXICLRR1A0_MBX_INTR1A0_0C_Pos    (0UL)          /*!< MBX_INTR1A0_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR1A0_MBX_INTR1A0_0C_Msk    (0x1UL)        /*!< MBX_INTR1A0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A0_MBX_INTR1A0_1C_Pos    (1UL)          /*!< MBX_INTR1A0_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR1A0_MBX_INTR1A0_1C_Msk    (0x2UL)        /*!< MBX_INTR1A0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A0_MBX_INTR1A0_2C_Pos    (2UL)          /*!< MBX_INTR1A0_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR1A0_MBX_INTR1A0_2C_Msk    (0x4UL)        /*!< MBX_INTR1A0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A0_MBX_INTR1A0_3C_Pos    (3UL)          /*!< MBX_INTR1A0_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR1A0_MBX_INTR1A0_3C_Msk    (0x8UL)        /*!< MBX_INTR1A0_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR1A10  ======================================================== */
+ #define R_MBXSEM_MBXR1A10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A11  ======================================================== */
+ #define R_MBXSEM_MBXR1A11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A12  ======================================================== */
+ #define R_MBXSEM_MBXR1A12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A13  ======================================================== */
+ #define R_MBXSEM_MBXR1A13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR1A1  ====================================================== */
+ #define R_MBXSEM_MBXISETR1A1_MBX_INTR1A1_0S_Pos    (0UL)          /*!< MBX_INTR1A1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR1A1_MBX_INTR1A1_0S_Msk    (0x1UL)        /*!< MBX_INTR1A1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A1_MBX_INTR1A1_1S_Pos    (1UL)          /*!< MBX_INTR1A1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR1A1_MBX_INTR1A1_1S_Msk    (0x2UL)        /*!< MBX_INTR1A1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A1_MBX_INTR1A1_2S_Pos    (2UL)          /*!< MBX_INTR1A1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR1A1_MBX_INTR1A1_2S_Msk    (0x4UL)        /*!< MBX_INTR1A1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A1_MBX_INTR1A1_3S_Pos    (3UL)          /*!< MBX_INTR1A1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR1A1_MBX_INTR1A1_3S_Msk    (0x8UL)        /*!< MBX_INTR1A1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR1A1  ====================================================== */
+ #define R_MBXSEM_MBXICLRR1A1_MBX_INTR1A1_0C_Pos    (0UL)          /*!< MBX_INTR1A1_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR1A1_MBX_INTR1A1_0C_Msk    (0x1UL)        /*!< MBX_INTR1A1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A1_MBX_INTR1A1_1C_Pos    (1UL)          /*!< MBX_INTR1A1_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR1A1_MBX_INTR1A1_1C_Msk    (0x2UL)        /*!< MBX_INTR1A1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A1_MBX_INTR1A1_2C_Pos    (2UL)          /*!< MBX_INTR1A1_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR1A1_MBX_INTR1A1_2C_Msk    (0x4UL)        /*!< MBX_INTR1A1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A1_MBX_INTR1A1_3C_Pos    (3UL)          /*!< MBX_INTR1A1_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR1A1_MBX_INTR1A1_3C_Msk    (0x8UL)        /*!< MBX_INTR1A1_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR1A20  ======================================================== */
+ #define R_MBXSEM_MBXR1A20_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A20_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A21  ======================================================== */
+ #define R_MBXSEM_MBXR1A21_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A21_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A22  ======================================================== */
+ #define R_MBXSEM_MBXR1A22_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A22_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A23  ======================================================== */
+ #define R_MBXSEM_MBXR1A23_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A23_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR1A2  ====================================================== */
+ #define R_MBXSEM_MBXISETR1A2_MBX_INTR1A2_0S_Pos    (0UL)          /*!< MBX_INTR1A2_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR1A2_MBX_INTR1A2_0S_Msk    (0x1UL)        /*!< MBX_INTR1A2_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A2_MBX_INTR1A2_1S_Pos    (1UL)          /*!< MBX_INTR1A2_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR1A2_MBX_INTR1A2_1S_Msk    (0x2UL)        /*!< MBX_INTR1A2_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A2_MBX_INTR1A2_2S_Pos    (2UL)          /*!< MBX_INTR1A2_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR1A2_MBX_INTR1A2_2S_Msk    (0x4UL)        /*!< MBX_INTR1A2_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A2_MBX_INTR1A2_3S_Pos    (3UL)          /*!< MBX_INTR1A2_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR1A2_MBX_INTR1A2_3S_Msk    (0x8UL)        /*!< MBX_INTR1A2_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR1A2  ====================================================== */
+ #define R_MBXSEM_MBXICLRR1A2_MBX_INTR1A2_0C_Pos    (0UL)          /*!< MBX_INTR1A2_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR1A2_MBX_INTR1A2_0C_Msk    (0x1UL)        /*!< MBX_INTR1A2_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A2_MBX_INTR1A2_1C_Pos    (1UL)          /*!< MBX_INTR1A2_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR1A2_MBX_INTR1A2_1C_Msk    (0x2UL)        /*!< MBX_INTR1A2_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A2_MBX_INTR1A2_2C_Pos    (2UL)          /*!< MBX_INTR1A2_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR1A2_MBX_INTR1A2_2C_Msk    (0x4UL)        /*!< MBX_INTR1A2_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A2_MBX_INTR1A2_3C_Pos    (3UL)          /*!< MBX_INTR1A2_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR1A2_MBX_INTR1A2_3C_Msk    (0x8UL)        /*!< MBX_INTR1A2_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR1A30  ======================================================== */
+ #define R_MBXSEM_MBXR1A30_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A30_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A31  ======================================================== */
+ #define R_MBXSEM_MBXR1A31_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A31_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A32  ======================================================== */
+ #define R_MBXSEM_MBXR1A32_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A32_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1A33  ======================================================== */
+ #define R_MBXSEM_MBXR1A33_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1A33_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR1A3  ====================================================== */
+ #define R_MBXSEM_MBXISETR1A3_MBX_INTR1A3_0S_Pos    (0UL)          /*!< MBX_INTR1A3_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR1A3_MBX_INTR1A3_0S_Msk    (0x1UL)        /*!< MBX_INTR1A3_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A3_MBX_INTR1A3_1S_Pos    (1UL)          /*!< MBX_INTR1A3_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR1A3_MBX_INTR1A3_1S_Msk    (0x2UL)        /*!< MBX_INTR1A3_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A3_MBX_INTR1A3_2S_Pos    (2UL)          /*!< MBX_INTR1A3_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR1A3_MBX_INTR1A3_2S_Msk    (0x4UL)        /*!< MBX_INTR1A3_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1A3_MBX_INTR1A3_3S_Pos    (3UL)          /*!< MBX_INTR1A3_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR1A3_MBX_INTR1A3_3S_Msk    (0x8UL)        /*!< MBX_INTR1A3_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR1A3  ====================================================== */
+ #define R_MBXSEM_MBXICLRR1A3_MBX_INTR1A3_0C_Pos    (0UL)          /*!< MBX_INTR1A3_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR1A3_MBX_INTR1A3_0C_Msk    (0x1UL)        /*!< MBX_INTR1A3_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A3_MBX_INTR1A3_1C_Pos    (1UL)          /*!< MBX_INTR1A3_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR1A3_MBX_INTR1A3_1C_Msk    (0x2UL)        /*!< MBX_INTR1A3_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A3_MBX_INTR1A3_2C_Pos    (2UL)          /*!< MBX_INTR1A3_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR1A3_MBX_INTR1A3_2C_Msk    (0x4UL)        /*!< MBX_INTR1A3_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1A3_MBX_INTR1A3_3C_Pos    (3UL)          /*!< MBX_INTR1A3_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR1A3_MBX_INTR1A3_3C_Msk    (0x8UL)        /*!< MBX_INTR1A3_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA0R00  ======================================================== */
+ #define R_MBXSEM_MBXA0R00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0R00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0R01  ======================================================== */
+ #define R_MBXSEM_MBXA0R01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0R01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0R02  ======================================================== */
+ #define R_MBXSEM_MBXA0R02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0R02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0R03  ======================================================== */
+ #define R_MBXSEM_MBXA0R03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0R03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1R00  ======================================================== */
+ #define R_MBXSEM_MBXA1R00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1R00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1R01  ======================================================== */
+ #define R_MBXSEM_MBXA1R01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1R01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1R02  ======================================================== */
+ #define R_MBXSEM_MBXA1R02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1R02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1R03  ======================================================== */
+ #define R_MBXSEM_MBXA1R03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1R03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2R00  ======================================================== */
+ #define R_MBXSEM_MBXA2R00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2R00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2R01  ======================================================== */
+ #define R_MBXSEM_MBXA2R01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2R01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2R02  ======================================================== */
+ #define R_MBXSEM_MBXA2R02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2R02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2R03  ======================================================== */
+ #define R_MBXSEM_MBXA2R03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2R03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3R00  ======================================================== */
+ #define R_MBXSEM_MBXA3R00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3R00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3R01  ======================================================== */
+ #define R_MBXSEM_MBXA3R01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3R01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3R02  ======================================================== */
+ #define R_MBXSEM_MBXA3R02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3R02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3R03  ======================================================== */
+ #define R_MBXSEM_MBXA3R03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3R03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA0R0  ====================================================== */
+ #define R_MBXSEM_MBXISETA0R0_MBX_INTA0R0_0S_Pos    (0UL)          /*!< MBX_INTA0R0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA0R0_MBX_INTA0R0_0S_Msk    (0x1UL)        /*!< MBX_INTA0R0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0R0_MBX_INTA0R0_1S_Pos    (1UL)          /*!< MBX_INTA0R0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA0R0_MBX_INTA0R0_1S_Msk    (0x2UL)        /*!< MBX_INTA0R0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0R0_MBX_INTA0R0_2S_Pos    (2UL)          /*!< MBX_INTA0R0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA0R0_MBX_INTA0R0_2S_Msk    (0x4UL)        /*!< MBX_INTA0R0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0R0_MBX_INTA0R0_3S_Pos    (3UL)          /*!< MBX_INTA0R0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA0R0_MBX_INTA0R0_3S_Msk    (0x8UL)        /*!< MBX_INTA0R0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXISETA1R0  ====================================================== */
+ #define R_MBXSEM_MBXISETA1R0_MBX_INTA1R0_0S_Pos    (0UL)          /*!< MBX_INTA1R0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA1R0_MBX_INTA1R0_0S_Msk    (0x1UL)        /*!< MBX_INTA1R0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1R0_MBX_INTA1R0_1S_Pos    (1UL)          /*!< MBX_INTA1R0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA1R0_MBX_INTA1R0_1S_Msk    (0x2UL)        /*!< MBX_INTA1R0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1R0_MBX_INTA1R0_2S_Pos    (2UL)          /*!< MBX_INTA1R0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA1R0_MBX_INTA1R0_2S_Msk    (0x4UL)        /*!< MBX_INTA1R0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1R0_MBX_INTA1R0_3S_Pos    (3UL)          /*!< MBX_INTA1R0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA1R0_MBX_INTA1R0_3S_Msk    (0x8UL)        /*!< MBX_INTA1R0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXISETA2R0  ====================================================== */
+ #define R_MBXSEM_MBXISETA2R0_MBX_INTA2R0_0S_Pos    (0UL)          /*!< MBX_INTA2R0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA2R0_MBX_INTA2R0_0S_Msk    (0x1UL)        /*!< MBX_INTA2R0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2R0_MBX_INTA2R0_1S_Pos    (1UL)          /*!< MBX_INTA2R0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA2R0_MBX_INTA2R0_1S_Msk    (0x2UL)        /*!< MBX_INTA2R0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2R0_MBX_INTA2R0_2S_Pos    (2UL)          /*!< MBX_INTA2R0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA2R0_MBX_INTA2R0_2S_Msk    (0x4UL)        /*!< MBX_INTA2R0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2R0_MBX_INTA2R0_3S_Pos    (3UL)          /*!< MBX_INTA2R0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA2R0_MBX_INTA2R0_3S_Msk    (0x8UL)        /*!< MBX_INTA2R0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXISETA3R0  ====================================================== */
+ #define R_MBXSEM_MBXISETA3R0_MBX_INTA3R0_0S_Pos    (0UL)          /*!< MBX_INTA3R0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA3R0_MBX_INTA3R0_0S_Msk    (0x1UL)        /*!< MBX_INTA3R0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3R0_MBX_INTA3R0_1S_Pos    (1UL)          /*!< MBX_INTA3R0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA3R0_MBX_INTA3R0_1S_Msk    (0x2UL)        /*!< MBX_INTA3R0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3R0_MBX_INTA3R0_2S_Pos    (2UL)          /*!< MBX_INTA3R0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA3R0_MBX_INTA3R0_2S_Msk    (0x4UL)        /*!< MBX_INTA3R0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3R0_MBX_INTA3R0_3S_Pos    (3UL)          /*!< MBX_INTA3R0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA3R0_MBX_INTA3R0_3S_Msk    (0x8UL)        /*!< MBX_INTA3R0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRAR0  ======================================================= */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA0R0_0C_Pos     (0UL)          /*!< MBX_INTA0R0_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA0R0_0C_Msk     (0x1UL)        /*!< MBX_INTA0R0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA0R0_1C_Pos     (1UL)          /*!< MBX_INTA0R0_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA0R0_1C_Msk     (0x2UL)        /*!< MBX_INTA0R0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA0R0_2C_Pos     (2UL)          /*!< MBX_INTA0R0_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA0R0_2C_Msk     (0x4UL)        /*!< MBX_INTA0R0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA0R0_3C_Pos     (3UL)          /*!< MBX_INTA0R0_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA0R0_3C_Msk     (0x8UL)        /*!< MBX_INTA0R0_3C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA1R0_0C_Pos     (4UL)          /*!< MBX_INTA1R0_0C (Bit 4)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA1R0_0C_Msk     (0x10UL)       /*!< MBX_INTA1R0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA1R0_1C_Pos     (5UL)          /*!< MBX_INTA1R0_1C (Bit 5)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA1R0_1C_Msk     (0x20UL)       /*!< MBX_INTA1R0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA1R0_2C_Pos     (6UL)          /*!< MBX_INTA1R0_2C (Bit 6)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA1R0_2C_Msk     (0x40UL)       /*!< MBX_INTA1R0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA1R0_3C_Pos     (7UL)          /*!< MBX_INTA1R0_3C (Bit 7)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA1R0_3C_Msk     (0x80UL)       /*!< MBX_INTA1R0_3C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA2R0_0C_Pos     (8UL)          /*!< MBX_INTA2R0_0C (Bit 8)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA2R0_0C_Msk     (0x100UL)      /*!< MBX_INTA2R0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA2R0_1C_Pos     (9UL)          /*!< MBX_INTA2R0_1C (Bit 9)                                */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA2R0_1C_Msk     (0x200UL)      /*!< MBX_INTA2R0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA2R0_2C_Pos     (10UL)         /*!< MBX_INTA2R0_2C (Bit 10)                               */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA2R0_2C_Msk     (0x400UL)      /*!< MBX_INTA2R0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA2R0_3C_Pos     (11UL)         /*!< MBX_INTA2R0_3C (Bit 11)                               */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA2R0_3C_Msk     (0x800UL)      /*!< MBX_INTA2R0_3C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA3R0_0C_Pos     (12UL)         /*!< MBX_INTA3R0_0C (Bit 12)                               */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA3R0_0C_Msk     (0x1000UL)     /*!< MBX_INTA3R0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA3R0_1C_Pos     (13UL)         /*!< MBX_INTA3R0_1C (Bit 13)                               */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA3R0_1C_Msk     (0x2000UL)     /*!< MBX_INTA3R0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA3R0_2C_Pos     (14UL)         /*!< MBX_INTA3R0_2C (Bit 14)                               */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA3R0_2C_Msk     (0x4000UL)     /*!< MBX_INTA3R0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA3R0_3C_Pos     (15UL)         /*!< MBX_INTA3R0_3C (Bit 15)                               */
+ #define R_MBXSEM_MBXICLRAR0_MBX_INTA3R0_3C_Msk     (0x8000UL)     /*!< MBX_INTA3R0_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA0R10  ======================================================== */
+ #define R_MBXSEM_MBXA0R10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0R10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0R11  ======================================================== */
+ #define R_MBXSEM_MBXA0R11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0R11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0R12  ======================================================== */
+ #define R_MBXSEM_MBXA0R12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0R12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0R13  ======================================================== */
+ #define R_MBXSEM_MBXA0R13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0R13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1R10  ======================================================== */
+ #define R_MBXSEM_MBXA1R10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1R10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1R11  ======================================================== */
+ #define R_MBXSEM_MBXA1R11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1R11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1R12  ======================================================== */
+ #define R_MBXSEM_MBXA1R12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1R12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1R13  ======================================================== */
+ #define R_MBXSEM_MBXA1R13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1R13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2R10  ======================================================== */
+ #define R_MBXSEM_MBXA2R10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2R10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2R11  ======================================================== */
+ #define R_MBXSEM_MBXA2R11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2R11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2R12  ======================================================== */
+ #define R_MBXSEM_MBXA2R12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2R12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2R13  ======================================================== */
+ #define R_MBXSEM_MBXA2R13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2R13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3R10  ======================================================== */
+ #define R_MBXSEM_MBXA3R10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3R10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3R11  ======================================================== */
+ #define R_MBXSEM_MBXA3R11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3R11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3R12  ======================================================== */
+ #define R_MBXSEM_MBXA3R12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3R12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3R13  ======================================================== */
+ #define R_MBXSEM_MBXA3R13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3R13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA0R1  ====================================================== */
+ #define R_MBXSEM_MBXISETA0R1_MBX_INTA0R1_0S_Pos    (0UL)          /*!< MBX_INTA0R1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA0R1_MBX_INTA0R1_0S_Msk    (0x1UL)        /*!< MBX_INTA0R1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0R1_MBX_INTA0R1_1S_Pos    (1UL)          /*!< MBX_INTA0R1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA0R1_MBX_INTA0R1_1S_Msk    (0x2UL)        /*!< MBX_INTA0R1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0R1_MBX_INTA0R1_2S_Pos    (2UL)          /*!< MBX_INTA0R1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA0R1_MBX_INTA0R1_2S_Msk    (0x4UL)        /*!< MBX_INTA0R1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0R1_MBX_INTA0R1_3S_Pos    (3UL)          /*!< MBX_INTA0R1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA0R1_MBX_INTA0R1_3S_Msk    (0x8UL)        /*!< MBX_INTA0R1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXISETA1R1  ====================================================== */
+ #define R_MBXSEM_MBXISETA1R1_MBX_INTA1R1_0S_Pos    (0UL)          /*!< MBX_INTA1R1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA1R1_MBX_INTA1R1_0S_Msk    (0x1UL)        /*!< MBX_INTA1R1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1R1_MBX_INTA1R1_1S_Pos    (1UL)          /*!< MBX_INTA1R1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA1R1_MBX_INTA1R1_1S_Msk    (0x2UL)        /*!< MBX_INTA1R1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1R1_MBX_INTA1R1_2S_Pos    (2UL)          /*!< MBX_INTA1R1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA1R1_MBX_INTA1R1_2S_Msk    (0x4UL)        /*!< MBX_INTA1R1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1R1_MBX_INTA1R1_3S_Pos    (3UL)          /*!< MBX_INTA1R1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA1R1_MBX_INTA1R1_3S_Msk    (0x8UL)        /*!< MBX_INTA1R1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXISETA2R1  ====================================================== */
+ #define R_MBXSEM_MBXISETA2R1_MBX_INTA2R1_0S_Pos    (0UL)          /*!< MBX_INTA2R1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA2R1_MBX_INTA2R1_0S_Msk    (0x1UL)        /*!< MBX_INTA2R1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2R1_MBX_INTA2R1_1S_Pos    (1UL)          /*!< MBX_INTA2R1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA2R1_MBX_INTA2R1_1S_Msk    (0x2UL)        /*!< MBX_INTA2R1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2R1_MBX_INTA2R1_2S_Pos    (2UL)          /*!< MBX_INTA2R1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA2R1_MBX_INTA2R1_2S_Msk    (0x4UL)        /*!< MBX_INTA2R1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2R1_MBX_INTA2R1_3S_Pos    (3UL)          /*!< MBX_INTA2R1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA2R1_MBX_INTA2R1_3S_Msk    (0x8UL)        /*!< MBX_INTA2R1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXISETA3R1  ====================================================== */
+ #define R_MBXSEM_MBXISETA3R1_MBX_INTA3R1_0S_Pos    (0UL)          /*!< MBX_INTA3R1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA3R1_MBX_INTA3R1_0S_Msk    (0x1UL)        /*!< MBX_INTA3R1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3R1_MBX_INTA3R1_1S_Pos    (1UL)          /*!< MBX_INTA3R1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA3R1_MBX_INTA3R1_1S_Msk    (0x2UL)        /*!< MBX_INTA3R1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3R1_MBX_INTA3R1_2S_Pos    (2UL)          /*!< MBX_INTA3R1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA3R1_MBX_INTA3R1_2S_Msk    (0x4UL)        /*!< MBX_INTA3R1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3R1_MBX_INTA3R1_3S_Pos    (3UL)          /*!< MBX_INTA3R1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA3R1_MBX_INTA3R1_3S_Msk    (0x8UL)        /*!< MBX_INTA3R1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRAR1  ======================================================= */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA0R1_0C_Pos     (0UL)          /*!< MBX_INTA0R1_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA0R1_0C_Msk     (0x1UL)        /*!< MBX_INTA0R1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA0R1_1C_Pos     (1UL)          /*!< MBX_INTA0R1_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA0R1_1C_Msk     (0x2UL)        /*!< MBX_INTA0R1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA0R1_2C_Pos     (2UL)          /*!< MBX_INTA0R1_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA0R1_2C_Msk     (0x4UL)        /*!< MBX_INTA0R1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA0R1_3C_Pos     (3UL)          /*!< MBX_INTA0R1_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA0R1_3C_Msk     (0x8UL)        /*!< MBX_INTA0R1_3C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA1R1_0C_Pos     (4UL)          /*!< MBX_INTA1R1_0C (Bit 4)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA1R1_0C_Msk     (0x10UL)       /*!< MBX_INTA1R1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA1R1_1C_Pos     (5UL)          /*!< MBX_INTA1R1_1C (Bit 5)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA1R1_1C_Msk     (0x20UL)       /*!< MBX_INTA1R1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA1R1_2C_Pos     (6UL)          /*!< MBX_INTA1R1_2C (Bit 6)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA1R1_2C_Msk     (0x40UL)       /*!< MBX_INTA1R1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA1R1_3C_Pos     (7UL)          /*!< MBX_INTA1R1_3C (Bit 7)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA1R1_3C_Msk     (0x80UL)       /*!< MBX_INTA1R1_3C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA2R1_0C_Pos     (8UL)          /*!< MBX_INTA2R1_0C (Bit 8)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA2R1_0C_Msk     (0x100UL)      /*!< MBX_INTA2R1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA2R1_1C_Pos     (9UL)          /*!< MBX_INTA2R1_1C (Bit 9)                                */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA2R1_1C_Msk     (0x200UL)      /*!< MBX_INTA2R1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA2R1_2C_Pos     (10UL)         /*!< MBX_INTA2R1_2C (Bit 10)                               */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA2R1_2C_Msk     (0x400UL)      /*!< MBX_INTA2R1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA2R1_3C_Pos     (11UL)         /*!< MBX_INTA2R1_3C (Bit 11)                               */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA2R1_3C_Msk     (0x800UL)      /*!< MBX_INTA2R1_3C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA3R1_0C_Pos     (12UL)         /*!< MBX_INTA3R1_0C (Bit 12)                               */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA3R1_0C_Msk     (0x1000UL)     /*!< MBX_INTA3R1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA3R1_1C_Pos     (13UL)         /*!< MBX_INTA3R1_1C (Bit 13)                               */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA3R1_1C_Msk     (0x2000UL)     /*!< MBX_INTA3R1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA3R1_2C_Pos     (14UL)         /*!< MBX_INTA3R1_2C (Bit 14)                               */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA3R1_2C_Msk     (0x4000UL)     /*!< MBX_INTA3R1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA3R1_3C_Pos     (15UL)         /*!< MBX_INTA3R1_3C (Bit 15)                               */
+ #define R_MBXSEM_MBXICLRAR1_MBX_INTA3R1_3C_Msk     (0x8000UL)     /*!< MBX_INTA3R1_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR0R10  ======================================================== */
+ #define R_MBXSEM_MBXR0R10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0R10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0R11  ======================================================== */
+ #define R_MBXSEM_MBXR0R11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0R11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0R12  ======================================================== */
+ #define R_MBXSEM_MBXR0R12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0R12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR0R13  ======================================================== */
+ #define R_MBXSEM_MBXR0R13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR0R13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR0R1  ====================================================== */
+ #define R_MBXSEM_MBXISETR0R1_MBX_INTR0R1_0S_Pos    (0UL)          /*!< MBX_INTR0R1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR0R1_MBX_INTR0R1_0S_Msk    (0x1UL)        /*!< MBX_INTR0R1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0R1_MBX_INTR0R1_1S_Pos    (1UL)          /*!< MBX_INTR0R1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR0R1_MBX_INTR0R1_1S_Msk    (0x2UL)        /*!< MBX_INTR0R1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0R1_MBX_INTR0R1_2S_Pos    (2UL)          /*!< MBX_INTR0R1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR0R1_MBX_INTR0R1_2S_Msk    (0x4UL)        /*!< MBX_INTR0R1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR0R1_MBX_INTR0R1_3S_Pos    (3UL)          /*!< MBX_INTR0R1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR0R1_MBX_INTR0R1_3S_Msk    (0x8UL)        /*!< MBX_INTR0R1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR0R1  ====================================================== */
+ #define R_MBXSEM_MBXICLRR0R1_MBX_INTR0R1_0C_Pos    (0UL)          /*!< MBX_INTR0R1_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR0R1_MBX_INTR0R1_0C_Msk    (0x1UL)        /*!< MBX_INTR0R1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0R1_MBX_INTR0R1_1C_Pos    (1UL)          /*!< MBX_INTR0R1_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR0R1_MBX_INTR0R1_1C_Msk    (0x2UL)        /*!< MBX_INTR0R1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0R1_MBX_INTR0R1_2C_Pos    (2UL)          /*!< MBX_INTR0R1_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR0R1_MBX_INTR0R1_2C_Msk    (0x4UL)        /*!< MBX_INTR0R1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR0R1_MBX_INTR0R1_3C_Pos    (3UL)          /*!< MBX_INTR0R1_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR0R1_MBX_INTR0R1_3C_Msk    (0x8UL)        /*!< MBX_INTR0R1_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXR1R00  ======================================================== */
+ #define R_MBXSEM_MBXR1R00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1R00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1R01  ======================================================== */
+ #define R_MBXSEM_MBXR1R01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1R01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1R02  ======================================================== */
+ #define R_MBXSEM_MBXR1R02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1R02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXR1R03  ======================================================== */
+ #define R_MBXSEM_MBXR1R03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXR1R03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETR1R0  ====================================================== */
+ #define R_MBXSEM_MBXISETR1R0_MBX_INTR1R0_0S_Pos    (0UL)          /*!< MBX_INTR1R0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETR1R0_MBX_INTR1R0_0S_Msk    (0x1UL)        /*!< MBX_INTR1R0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1R0_MBX_INTR1R0_1S_Pos    (1UL)          /*!< MBX_INTR1R0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETR1R0_MBX_INTR1R0_1S_Msk    (0x2UL)        /*!< MBX_INTR1R0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1R0_MBX_INTR1R0_2S_Pos    (2UL)          /*!< MBX_INTR1R0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETR1R0_MBX_INTR1R0_2S_Msk    (0x4UL)        /*!< MBX_INTR1R0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETR1R0_MBX_INTR1R0_3S_Pos    (3UL)          /*!< MBX_INTR1R0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETR1R0_MBX_INTR1R0_3S_Msk    (0x8UL)        /*!< MBX_INTR1R0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRR1R0  ====================================================== */
+ #define R_MBXSEM_MBXICLRR1R0_MBX_INTR1R0_0C_Pos    (0UL)          /*!< MBX_INTR1R0_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRR1R0_MBX_INTR1R0_0C_Msk    (0x1UL)        /*!< MBX_INTR1R0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1R0_MBX_INTR1R0_1C_Pos    (1UL)          /*!< MBX_INTR1R0_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRR1R0_MBX_INTR1R0_1C_Msk    (0x2UL)        /*!< MBX_INTR1R0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1R0_MBX_INTR1R0_2C_Pos    (2UL)          /*!< MBX_INTR1R0_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRR1R0_MBX_INTR1R0_2C_Msk    (0x4UL)        /*!< MBX_INTR1R0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRR1R0_MBX_INTR1R0_3C_Pos    (3UL)          /*!< MBX_INTR1R0_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRR1R0_MBX_INTR1R0_3C_Msk    (0x8UL)        /*!< MBX_INTR1R0_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA0A10  ======================================================== */
+ #define R_MBXSEM_MBXA0A10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A11  ======================================================== */
+ #define R_MBXSEM_MBXA0A11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A12  ======================================================== */
+ #define R_MBXSEM_MBXA0A12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A13  ======================================================== */
+ #define R_MBXSEM_MBXA0A13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA0A1  ====================================================== */
+ #define R_MBXSEM_MBXISETA0A1_MBX_INTA0A1_0S_Pos    (0UL)          /*!< MBX_INTA0A1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA0A1_MBX_INTA0A1_0S_Msk    (0x1UL)        /*!< MBX_INTA0A1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A1_MBX_INTA0A1_1S_Pos    (1UL)          /*!< MBX_INTA0A1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA0A1_MBX_INTA0A1_1S_Msk    (0x2UL)        /*!< MBX_INTA0A1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A1_MBX_INTA0A1_2S_Pos    (2UL)          /*!< MBX_INTA0A1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA0A1_MBX_INTA0A1_2S_Msk    (0x4UL)        /*!< MBX_INTA0A1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A1_MBX_INTA0A1_3S_Pos    (3UL)          /*!< MBX_INTA0A1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA0A1_MBX_INTA0A1_3S_Msk    (0x8UL)        /*!< MBX_INTA0A1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA0A1  ====================================================== */
+ #define R_MBXSEM_MBXICLRA0A1_MBX_INTA0A1_0C_Pos    (0UL)          /*!< MBX_INTA0A1_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA0A1_MBX_INTA0A1_0C_Msk    (0x1UL)        /*!< MBX_INTA0A1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A1_MBX_INTA0A1_1C_Pos    (1UL)          /*!< MBX_INTA0A1_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA0A1_MBX_INTA0A1_1C_Msk    (0x2UL)        /*!< MBX_INTA0A1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A1_MBX_INTA0A1_2C_Pos    (2UL)          /*!< MBX_INTA0A1_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA0A1_MBX_INTA0A1_2C_Msk    (0x4UL)        /*!< MBX_INTA0A1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A1_MBX_INTA0A1_3C_Pos    (3UL)          /*!< MBX_INTA0A1_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA0A1_MBX_INTA0A1_3C_Msk    (0x8UL)        /*!< MBX_INTA0A1_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA0A20  ======================================================== */
+ #define R_MBXSEM_MBXA0A20_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A20_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A21  ======================================================== */
+ #define R_MBXSEM_MBXA0A21_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A21_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A22  ======================================================== */
+ #define R_MBXSEM_MBXA0A22_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A22_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A23  ======================================================== */
+ #define R_MBXSEM_MBXA0A23_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A23_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA0A2  ====================================================== */
+ #define R_MBXSEM_MBXISETA0A2_MBX_INTA0A2_0S_Pos    (0UL)          /*!< MBX_INTA0A2_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA0A2_MBX_INTA0A2_0S_Msk    (0x1UL)        /*!< MBX_INTA0A2_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A2_MBX_INTA0A2_1S_Pos    (1UL)          /*!< MBX_INTA0A2_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA0A2_MBX_INTA0A2_1S_Msk    (0x2UL)        /*!< MBX_INTA0A2_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A2_MBX_INTA0A2_2S_Pos    (2UL)          /*!< MBX_INTA0A2_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA0A2_MBX_INTA0A2_2S_Msk    (0x4UL)        /*!< MBX_INTA0A2_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A2_MBX_INTA0A2_3S_Pos    (3UL)          /*!< MBX_INTA0A2_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA0A2_MBX_INTA0A2_3S_Msk    (0x8UL)        /*!< MBX_INTA0A2_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA0A2  ====================================================== */
+ #define R_MBXSEM_MBXICLRA0A2_MBX_INTA0A2_0C_Pos    (0UL)          /*!< MBX_INTA0A2_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA0A2_MBX_INTA0A2_0C_Msk    (0x1UL)        /*!< MBX_INTA0A2_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A2_MBX_INTA0A2_1C_Pos    (1UL)          /*!< MBX_INTA0A2_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA0A2_MBX_INTA0A2_1C_Msk    (0x2UL)        /*!< MBX_INTA0A2_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A2_MBX_INTA0A2_2C_Pos    (2UL)          /*!< MBX_INTA0A2_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA0A2_MBX_INTA0A2_2C_Msk    (0x4UL)        /*!< MBX_INTA0A2_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A2_MBX_INTA0A2_3C_Pos    (3UL)          /*!< MBX_INTA0A2_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA0A2_MBX_INTA0A2_3C_Msk    (0x8UL)        /*!< MBX_INTA0A2_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA0A30  ======================================================== */
+ #define R_MBXSEM_MBXA0A30_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A30_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A31  ======================================================== */
+ #define R_MBXSEM_MBXA0A31_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A31_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A32  ======================================================== */
+ #define R_MBXSEM_MBXA0A32_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A32_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA0A33  ======================================================== */
+ #define R_MBXSEM_MBXA0A33_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA0A33_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA0A3  ====================================================== */
+ #define R_MBXSEM_MBXISETA0A3_MBX_INTA0A3_0S_Pos    (0UL)          /*!< MBX_INTA0A3_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA0A3_MBX_INTA0A3_0S_Msk    (0x1UL)        /*!< MBX_INTA0A3_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A3_MBX_INTA0A3_1S_Pos    (1UL)          /*!< MBX_INTA0A3_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA0A3_MBX_INTA0A3_1S_Msk    (0x2UL)        /*!< MBX_INTA0A3_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A3_MBX_INTA0A3_2S_Pos    (2UL)          /*!< MBX_INTA0A3_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA0A3_MBX_INTA0A3_2S_Msk    (0x4UL)        /*!< MBX_INTA0A3_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA0A3_MBX_INTA0A3_3S_Pos    (3UL)          /*!< MBX_INTA0A3_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA0A3_MBX_INTA0A3_3S_Msk    (0x8UL)        /*!< MBX_INTA0A3_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA0A3  ====================================================== */
+ #define R_MBXSEM_MBXICLRA0A3_MBX_INTA0A3_0C_Pos    (0UL)          /*!< MBX_INTA0A3_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA0A3_MBX_INTA0A3_0C_Msk    (0x1UL)        /*!< MBX_INTA0A3_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A3_MBX_INTA0A3_1C_Pos    (1UL)          /*!< MBX_INTA0A3_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA0A3_MBX_INTA0A3_1C_Msk    (0x2UL)        /*!< MBX_INTA0A3_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A3_MBX_INTA0A3_2C_Pos    (2UL)          /*!< MBX_INTA0A3_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA0A3_MBX_INTA0A3_2C_Msk    (0x4UL)        /*!< MBX_INTA0A3_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA0A3_MBX_INTA0A3_3C_Pos    (3UL)          /*!< MBX_INTA0A3_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA0A3_MBX_INTA0A3_3C_Msk    (0x8UL)        /*!< MBX_INTA0A3_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA1A00  ======================================================== */
+ #define R_MBXSEM_MBXA1A00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A01  ======================================================== */
+ #define R_MBXSEM_MBXA1A01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A02  ======================================================== */
+ #define R_MBXSEM_MBXA1A02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A03  ======================================================== */
+ #define R_MBXSEM_MBXA1A03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA1A0  ====================================================== */
+ #define R_MBXSEM_MBXISETA1A0_MBX_INTA1A0_0S_Pos    (0UL)          /*!< MBX_INTA1A0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA1A0_MBX_INTA1A0_0S_Msk    (0x1UL)        /*!< MBX_INTA1A0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A0_MBX_INTA1A0_1S_Pos    (1UL)          /*!< MBX_INTA1A0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA1A0_MBX_INTA1A0_1S_Msk    (0x2UL)        /*!< MBX_INTA1A0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A0_MBX_INTA1A0_2S_Pos    (2UL)          /*!< MBX_INTA1A0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA1A0_MBX_INTA1A0_2S_Msk    (0x4UL)        /*!< MBX_INTA1A0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A0_MBX_INTA1A0_3S_Pos    (3UL)          /*!< MBX_INTA1A0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA1A0_MBX_INTA1A0_3S_Msk    (0x8UL)        /*!< MBX_INTA1A0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA1A0  ====================================================== */
+ #define R_MBXSEM_MBXICLRA1A0_MBX_INTA1A0_0C_Pos    (0UL)          /*!< MBX_INTA1A0_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA1A0_MBX_INTA1A0_0C_Msk    (0x1UL)        /*!< MBX_INTA1A0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A0_MBX_INTA1A0_1C_Pos    (1UL)          /*!< MBX_INTA1A0_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA1A0_MBX_INTA1A0_1C_Msk    (0x2UL)        /*!< MBX_INTA1A0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A0_MBX_INTA1A0_2C_Pos    (2UL)          /*!< MBX_INTA1A0_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA1A0_MBX_INTA1A0_2C_Msk    (0x4UL)        /*!< MBX_INTA1A0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A0_MBX_INTA1A0_3C_Pos    (3UL)          /*!< MBX_INTA1A0_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA1A0_MBX_INTA1A0_3C_Msk    (0x8UL)        /*!< MBX_INTA1A0_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA1A20  ======================================================== */
+ #define R_MBXSEM_MBXA1A20_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A20_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A21  ======================================================== */
+ #define R_MBXSEM_MBXA1A21_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A21_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A22  ======================================================== */
+ #define R_MBXSEM_MBXA1A22_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A22_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A23  ======================================================== */
+ #define R_MBXSEM_MBXA1A23_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A23_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA1A2  ====================================================== */
+ #define R_MBXSEM_MBXISETA1A2_MBX_INTA1A2_0S_Pos    (0UL)          /*!< MBX_INTA1A2_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA1A2_MBX_INTA1A2_0S_Msk    (0x1UL)        /*!< MBX_INTA1A2_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A2_MBX_INTA1A2_1S_Pos    (1UL)          /*!< MBX_INTA1A2_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA1A2_MBX_INTA1A2_1S_Msk    (0x2UL)        /*!< MBX_INTA1A2_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A2_MBX_INTA1A2_2S_Pos    (2UL)          /*!< MBX_INTA1A2_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA1A2_MBX_INTA1A2_2S_Msk    (0x4UL)        /*!< MBX_INTA1A2_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A2_MBX_INTA1A2_3S_Pos    (3UL)          /*!< MBX_INTA1A2_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA1A2_MBX_INTA1A2_3S_Msk    (0x8UL)        /*!< MBX_INTA1A2_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA1A2  ====================================================== */
+ #define R_MBXSEM_MBXICLRA1A2_MBX_INTA1A2_0C_Pos    (0UL)          /*!< MBX_INTA1A2_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA1A2_MBX_INTA1A2_0C_Msk    (0x1UL)        /*!< MBX_INTA1A2_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A2_MBX_INTA1A2_1C_Pos    (1UL)          /*!< MBX_INTA1A2_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA1A2_MBX_INTA1A2_1C_Msk    (0x2UL)        /*!< MBX_INTA1A2_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A2_MBX_INTA1A2_2C_Pos    (2UL)          /*!< MBX_INTA1A2_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA1A2_MBX_INTA1A2_2C_Msk    (0x4UL)        /*!< MBX_INTA1A2_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A2_MBX_INTA1A2_3C_Pos    (3UL)          /*!< MBX_INTA1A2_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA1A2_MBX_INTA1A2_3C_Msk    (0x8UL)        /*!< MBX_INTA1A2_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA1A30  ======================================================== */
+ #define R_MBXSEM_MBXA1A30_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A30_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A31  ======================================================== */
+ #define R_MBXSEM_MBXA1A31_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A31_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A32  ======================================================== */
+ #define R_MBXSEM_MBXA1A32_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A32_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA1A33  ======================================================== */
+ #define R_MBXSEM_MBXA1A33_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA1A33_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA1A3  ====================================================== */
+ #define R_MBXSEM_MBXISETA1A3_MBX_INTA1A3_0S_Pos    (0UL)          /*!< MBX_INTA1A3_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA1A3_MBX_INTA1A3_0S_Msk    (0x1UL)        /*!< MBX_INTA1A3_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A3_MBX_INTA1A3_1S_Pos    (1UL)          /*!< MBX_INTA1A3_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA1A3_MBX_INTA1A3_1S_Msk    (0x2UL)        /*!< MBX_INTA1A3_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A3_MBX_INTA1A3_2S_Pos    (2UL)          /*!< MBX_INTA1A3_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA1A3_MBX_INTA1A3_2S_Msk    (0x4UL)        /*!< MBX_INTA1A3_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA1A3_MBX_INTA1A3_3S_Pos    (3UL)          /*!< MBX_INTA1A3_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA1A3_MBX_INTA1A3_3S_Msk    (0x8UL)        /*!< MBX_INTA1A3_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA1A3  ====================================================== */
+ #define R_MBXSEM_MBXICLRA1A3_MBX_INTA1A3_0C_Pos    (0UL)          /*!< MBX_INTA1A3_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA1A3_MBX_INTA1A3_0C_Msk    (0x1UL)        /*!< MBX_INTA1A3_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A3_MBX_INTA1A3_1C_Pos    (1UL)          /*!< MBX_INTA1A3_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA1A3_MBX_INTA1A3_1C_Msk    (0x2UL)        /*!< MBX_INTA1A3_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A3_MBX_INTA1A3_2C_Pos    (2UL)          /*!< MBX_INTA1A3_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA1A3_MBX_INTA1A3_2C_Msk    (0x4UL)        /*!< MBX_INTA1A3_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA1A3_MBX_INTA1A3_3C_Pos    (3UL)          /*!< MBX_INTA1A3_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA1A3_MBX_INTA1A3_3C_Msk    (0x8UL)        /*!< MBX_INTA1A3_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA2A00  ======================================================== */
+ #define R_MBXSEM_MBXA2A00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A01  ======================================================== */
+ #define R_MBXSEM_MBXA2A01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A02  ======================================================== */
+ #define R_MBXSEM_MBXA2A02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A03  ======================================================== */
+ #define R_MBXSEM_MBXA2A03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA2A0  ====================================================== */
+ #define R_MBXSEM_MBXISETA2A0_MBX_INTA2A0_0S_Pos    (0UL)          /*!< MBX_INTA2A0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA2A0_MBX_INTA2A0_0S_Msk    (0x1UL)        /*!< MBX_INTA2A0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A0_MBX_INTA2A0_1S_Pos    (1UL)          /*!< MBX_INTA2A0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA2A0_MBX_INTA2A0_1S_Msk    (0x2UL)        /*!< MBX_INTA2A0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A0_MBX_INTA2A0_2S_Pos    (2UL)          /*!< MBX_INTA2A0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA2A0_MBX_INTA2A0_2S_Msk    (0x4UL)        /*!< MBX_INTA2A0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A0_MBX_INTA2A0_3S_Pos    (3UL)          /*!< MBX_INTA2A0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA2A0_MBX_INTA2A0_3S_Msk    (0x8UL)        /*!< MBX_INTA2A0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA2A0  ====================================================== */
+ #define R_MBXSEM_MBXICLRA2A0_MBX_INTA2A0_0C_Pos    (0UL)          /*!< MBX_INTA2A0_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA2A0_MBX_INTA2A0_0C_Msk    (0x1UL)        /*!< MBX_INTA2A0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A0_MBX_INTA2A0_1C_Pos    (1UL)          /*!< MBX_INTA2A0_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA2A0_MBX_INTA2A0_1C_Msk    (0x2UL)        /*!< MBX_INTA2A0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A0_MBX_INTA2A0_2C_Pos    (2UL)          /*!< MBX_INTA2A0_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA2A0_MBX_INTA2A0_2C_Msk    (0x4UL)        /*!< MBX_INTA2A0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A0_MBX_INTA2A0_3C_Pos    (3UL)          /*!< MBX_INTA2A0_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA2A0_MBX_INTA2A0_3C_Msk    (0x8UL)        /*!< MBX_INTA2A0_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA2A10  ======================================================== */
+ #define R_MBXSEM_MBXA2A10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A11  ======================================================== */
+ #define R_MBXSEM_MBXA2A11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A12  ======================================================== */
+ #define R_MBXSEM_MBXA2A12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A13  ======================================================== */
+ #define R_MBXSEM_MBXA2A13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA2A1  ====================================================== */
+ #define R_MBXSEM_MBXISETA2A1_MBX_INTA2A1_0S_Pos    (0UL)          /*!< MBX_INTA2A1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA2A1_MBX_INTA2A1_0S_Msk    (0x1UL)        /*!< MBX_INTA2A1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A1_MBX_INTA2A1_1S_Pos    (1UL)          /*!< MBX_INTA2A1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA2A1_MBX_INTA2A1_1S_Msk    (0x2UL)        /*!< MBX_INTA2A1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A1_MBX_INTA2A1_2S_Pos    (2UL)          /*!< MBX_INTA2A1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA2A1_MBX_INTA2A1_2S_Msk    (0x4UL)        /*!< MBX_INTA2A1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A1_MBX_INTA2A1_3S_Pos    (3UL)          /*!< MBX_INTA2A1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA2A1_MBX_INTA2A1_3S_Msk    (0x8UL)        /*!< MBX_INTA2A1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA2A1  ====================================================== */
+ #define R_MBXSEM_MBXICLRA2A1_MBX_INTA2A1_0C_Pos    (0UL)          /*!< MBX_INTA2A1_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA2A1_MBX_INTA2A1_0C_Msk    (0x1UL)        /*!< MBX_INTA2A1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A1_MBX_INTA2A1_1C_Pos    (1UL)          /*!< MBX_INTA2A1_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA2A1_MBX_INTA2A1_1C_Msk    (0x2UL)        /*!< MBX_INTA2A1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A1_MBX_INTA2A1_2C_Pos    (2UL)          /*!< MBX_INTA2A1_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA2A1_MBX_INTA2A1_2C_Msk    (0x4UL)        /*!< MBX_INTA2A1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A1_MBX_INTA2A1_3C_Pos    (3UL)          /*!< MBX_INTA2A1_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA2A1_MBX_INTA2A1_3C_Msk    (0x8UL)        /*!< MBX_INTA2A1_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA2A30  ======================================================== */
+ #define R_MBXSEM_MBXA2A30_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A30_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A31  ======================================================== */
+ #define R_MBXSEM_MBXA2A31_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A31_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A32  ======================================================== */
+ #define R_MBXSEM_MBXA2A32_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A32_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA2A33  ======================================================== */
+ #define R_MBXSEM_MBXA2A33_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA2A33_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA2A3  ====================================================== */
+ #define R_MBXSEM_MBXISETA2A3_MBX_INTA2A3_0S_Pos    (0UL)          /*!< MBX_INTA2A3_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA2A3_MBX_INTA2A3_0S_Msk    (0x1UL)        /*!< MBX_INTA2A3_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A3_MBX_INTA2A3_1S_Pos    (1UL)          /*!< MBX_INTA2A3_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA2A3_MBX_INTA2A3_1S_Msk    (0x2UL)        /*!< MBX_INTA2A3_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A3_MBX_INTA2A3_2S_Pos    (2UL)          /*!< MBX_INTA2A3_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA2A3_MBX_INTA2A3_2S_Msk    (0x4UL)        /*!< MBX_INTA2A3_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA2A3_MBX_INTA2A3_3S_Pos    (3UL)          /*!< MBX_INTA2A3_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA2A3_MBX_INTA2A3_3S_Msk    (0x8UL)        /*!< MBX_INTA2A3_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA2A3  ====================================================== */
+ #define R_MBXSEM_MBXICLRA2A3_MBX_INTA2A3_0C_Pos    (0UL)          /*!< MBX_INTA2A3_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA2A3_MBX_INTA2A3_0C_Msk    (0x1UL)        /*!< MBX_INTA2A3_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A3_MBX_INTA2A3_1C_Pos    (1UL)          /*!< MBX_INTA2A3_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA2A3_MBX_INTA2A3_1C_Msk    (0x2UL)        /*!< MBX_INTA2A3_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A3_MBX_INTA2A3_2C_Pos    (2UL)          /*!< MBX_INTA2A3_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA2A3_MBX_INTA2A3_2C_Msk    (0x4UL)        /*!< MBX_INTA2A3_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA2A3_MBX_INTA2A3_3C_Pos    (3UL)          /*!< MBX_INTA2A3_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA2A3_MBX_INTA2A3_3C_Msk    (0x8UL)        /*!< MBX_INTA2A3_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA3A00  ======================================================== */
+ #define R_MBXSEM_MBXA3A00_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A00_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A01  ======================================================== */
+ #define R_MBXSEM_MBXA3A01_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A01_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A02  ======================================================== */
+ #define R_MBXSEM_MBXA3A02_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A02_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A03  ======================================================== */
+ #define R_MBXSEM_MBXA3A03_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A03_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA3A0  ====================================================== */
+ #define R_MBXSEM_MBXISETA3A0_MBX_INTA3A0_0S_Pos    (0UL)          /*!< MBX_INTA3A0_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA3A0_MBX_INTA3A0_0S_Msk    (0x1UL)        /*!< MBX_INTA3A0_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A0_MBX_INTA3A0_1S_Pos    (1UL)          /*!< MBX_INTA3A0_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA3A0_MBX_INTA3A0_1S_Msk    (0x2UL)        /*!< MBX_INTA3A0_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A0_MBX_INTA3A0_2S_Pos    (2UL)          /*!< MBX_INTA3A0_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA3A0_MBX_INTA3A0_2S_Msk    (0x4UL)        /*!< MBX_INTA3A0_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A0_MBX_INTA3A0_3S_Pos    (3UL)          /*!< MBX_INTA3A0_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA3A0_MBX_INTA3A0_3S_Msk    (0x8UL)        /*!< MBX_INTA3A0_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA3A0  ====================================================== */
+ #define R_MBXSEM_MBXICLRA3A0_MBX_INTA3A0_0C_Pos    (0UL)          /*!< MBX_INTA3A0_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA3A0_MBX_INTA3A0_0C_Msk    (0x1UL)        /*!< MBX_INTA3A0_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A0_MBX_INTA3A0_1C_Pos    (1UL)          /*!< MBX_INTA3A0_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA3A0_MBX_INTA3A0_1C_Msk    (0x2UL)        /*!< MBX_INTA3A0_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A0_MBX_INTA3A0_2C_Pos    (2UL)          /*!< MBX_INTA3A0_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA3A0_MBX_INTA3A0_2C_Msk    (0x4UL)        /*!< MBX_INTA3A0_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A0_MBX_INTA3A0_3C_Pos    (3UL)          /*!< MBX_INTA3A0_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA3A0_MBX_INTA3A0_3C_Msk    (0x8UL)        /*!< MBX_INTA3A0_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA3A10  ======================================================== */
+ #define R_MBXSEM_MBXA3A10_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A10_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A11  ======================================================== */
+ #define R_MBXSEM_MBXA3A11_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A11_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A12  ======================================================== */
+ #define R_MBXSEM_MBXA3A12_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A12_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A13  ======================================================== */
+ #define R_MBXSEM_MBXA3A13_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A13_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA3A1  ====================================================== */
+ #define R_MBXSEM_MBXISETA3A1_MBX_INTA3A1_0S_Pos    (0UL)          /*!< MBX_INTA3A1_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA3A1_MBX_INTA3A1_0S_Msk    (0x1UL)        /*!< MBX_INTA3A1_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A1_MBX_INTA3A1_1S_Pos    (1UL)          /*!< MBX_INTA3A1_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA3A1_MBX_INTA3A1_1S_Msk    (0x2UL)        /*!< MBX_INTA3A1_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A1_MBX_INTA3A1_2S_Pos    (2UL)          /*!< MBX_INTA3A1_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA3A1_MBX_INTA3A1_2S_Msk    (0x4UL)        /*!< MBX_INTA3A1_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A1_MBX_INTA3A1_3S_Pos    (3UL)          /*!< MBX_INTA3A1_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA3A1_MBX_INTA3A1_3S_Msk    (0x8UL)        /*!< MBX_INTA3A1_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA3A1  ====================================================== */
+ #define R_MBXSEM_MBXICLRA3A1_MBX_INTA3A1_0C_Pos    (0UL)          /*!< MBX_INTA3A1_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA3A1_MBX_INTA3A1_0C_Msk    (0x1UL)        /*!< MBX_INTA3A1_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A1_MBX_INTA3A1_1C_Pos    (1UL)          /*!< MBX_INTA3A1_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA3A1_MBX_INTA3A1_1C_Msk    (0x2UL)        /*!< MBX_INTA3A1_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A1_MBX_INTA3A1_2C_Pos    (2UL)          /*!< MBX_INTA3A1_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA3A1_MBX_INTA3A1_2C_Msk    (0x4UL)        /*!< MBX_INTA3A1_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A1_MBX_INTA3A1_3C_Pos    (3UL)          /*!< MBX_INTA3A1_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA3A1_MBX_INTA3A1_3C_Msk    (0x8UL)        /*!< MBX_INTA3A1_3C (Bitfield-Mask: 0x01)                  */
+/* =======================================================  MBXA3A20  ======================================================== */
+ #define R_MBXSEM_MBXA3A20_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A20_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A21  ======================================================== */
+ #define R_MBXSEM_MBXA3A21_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A21_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A22  ======================================================== */
+ #define R_MBXSEM_MBXA3A22_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A22_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  MBXA3A23  ======================================================== */
+ #define R_MBXSEM_MBXA3A23_MBX_Pos                  (0UL)          /*!< MBX (Bit 0)                                           */
+ #define R_MBXSEM_MBXA3A23_MBX_Msk                  (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
+/* ======================================================  MBXISETA3A2  ====================================================== */
+ #define R_MBXSEM_MBXISETA3A2_MBX_INTA3A2_0S_Pos    (0UL)          /*!< MBX_INTA3A2_0S (Bit 0)                                */
+ #define R_MBXSEM_MBXISETA3A2_MBX_INTA3A2_0S_Msk    (0x1UL)        /*!< MBX_INTA3A2_0S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A2_MBX_INTA3A2_1S_Pos    (1UL)          /*!< MBX_INTA3A2_1S (Bit 1)                                */
+ #define R_MBXSEM_MBXISETA3A2_MBX_INTA3A2_1S_Msk    (0x2UL)        /*!< MBX_INTA3A2_1S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A2_MBX_INTA3A2_2S_Pos    (2UL)          /*!< MBX_INTA3A2_2S (Bit 2)                                */
+ #define R_MBXSEM_MBXISETA3A2_MBX_INTA3A2_2S_Msk    (0x4UL)        /*!< MBX_INTA3A2_2S (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXISETA3A2_MBX_INTA3A2_3S_Pos    (3UL)          /*!< MBX_INTA3A2_3S (Bit 3)                                */
+ #define R_MBXSEM_MBXISETA3A2_MBX_INTA3A2_3S_Msk    (0x8UL)        /*!< MBX_INTA3A2_3S (Bitfield-Mask: 0x01)                  */
+/* ======================================================  MBXICLRA3A2  ====================================================== */
+ #define R_MBXSEM_MBXICLRA3A2_MBX_INTA3A2_0C_Pos    (0UL)          /*!< MBX_INTA3A2_0C (Bit 0)                                */
+ #define R_MBXSEM_MBXICLRA3A2_MBX_INTA3A2_0C_Msk    (0x1UL)        /*!< MBX_INTA3A2_0C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A2_MBX_INTA3A2_1C_Pos    (1UL)          /*!< MBX_INTA3A2_1C (Bit 1)                                */
+ #define R_MBXSEM_MBXICLRA3A2_MBX_INTA3A2_1C_Msk    (0x2UL)        /*!< MBX_INTA3A2_1C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A2_MBX_INTA3A2_2C_Pos    (2UL)          /*!< MBX_INTA3A2_2C (Bit 2)                                */
+ #define R_MBXSEM_MBXICLRA3A2_MBX_INTA3A2_2C_Msk    (0x4UL)        /*!< MBX_INTA3A2_2C (Bitfield-Mask: 0x01)                  */
+ #define R_MBXSEM_MBXICLRA3A2_MBX_INTA3A2_3C_Pos    (3UL)          /*!< MBX_INTA3A2_3C (Bit 3)                                */
+ #define R_MBXSEM_MBXICLRA3A2_MBX_INTA3A2_3C_Msk    (0x8UL)        /*!< MBX_INTA3A2_3C (Bitfield-Mask: 0x01)                  */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SHOSTIF                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CTRLR0  ========================================================= */
+ #define R_SHOSTIF_CTRLR0_SCPH_Pos        (8UL)     /*!< SCPH (Bit 8)                                          */
+ #define R_SHOSTIF_CTRLR0_SCPH_Msk        (0x100UL) /*!< SCPH (Bitfield-Mask: 0x01)                            */
+ #define R_SHOSTIF_CTRLR0_SCPOL_Pos       (9UL)     /*!< SCPOL (Bit 9)                                         */
+ #define R_SHOSTIF_CTRLR0_SCPOL_Msk       (0x200UL) /*!< SCPOL (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  ENR  ========================================================== */
+ #define R_SHOSTIF_ENR_ENABLE_Pos         (0UL)     /*!< ENABLE (Bit 0)                                        */
+ #define R_SHOSTIF_ENR_ENABLE_Msk         (0x1UL)   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RXFBTR  ========================================================= */
+ #define R_SHOSTIF_RXFBTR_RXFBTL_Pos      (0UL)     /*!< RXFBTL (Bit 0)                                        */
+ #define R_SHOSTIF_RXFBTR_RXFBTL_Msk      (0x3fUL)  /*!< RXFBTL (Bitfield-Mask: 0x3f)                          */
+/* ========================================================  TXFTLR  ========================================================= */
+ #define R_SHOSTIF_TXFTLR_TFT_Pos         (0UL)     /*!< TFT (Bit 0)                                           */
+ #define R_SHOSTIF_TXFTLR_TFT_Msk         (0x3fUL)  /*!< TFT (Bitfield-Mask: 0x3f)                             */
+/* ========================================================  RXFTLR  ========================================================= */
+ #define R_SHOSTIF_RXFTLR_RFT_Pos         (0UL)     /*!< RFT (Bit 0)                                           */
+ #define R_SHOSTIF_RXFTLR_RFT_Msk         (0x3fUL)  /*!< RFT (Bitfield-Mask: 0x3f)                             */
+/* ==========================================================  SR  =========================================================== */
+ #define R_SHOSTIF_SR_BUSY_Pos            (0UL)     /*!< BUSY (Bit 0)                                          */
+ #define R_SHOSTIF_SR_BUSY_Msk            (0x1UL)   /*!< BUSY (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  IMR  ========================================================== */
+ #define R_SHOSTIF_IMR_TXEIM_Pos          (0UL)     /*!< TXEIM (Bit 0)                                         */
+ #define R_SHOSTIF_IMR_TXEIM_Msk          (0x1UL)   /*!< TXEIM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_RXOIM_Pos          (3UL)     /*!< RXOIM (Bit 3)                                         */
+ #define R_SHOSTIF_IMR_RXOIM_Msk          (0x8UL)   /*!< RXOIM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_RXFIM_Pos          (4UL)     /*!< RXFIM (Bit 4)                                         */
+ #define R_SHOSTIF_IMR_RXFIM_Msk          (0x10UL)  /*!< RXFIM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_TXUIM_Pos          (7UL)     /*!< TXUIM (Bit 7)                                         */
+ #define R_SHOSTIF_IMR_TXUIM_Msk          (0x80UL)  /*!< TXUIM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_AHBEM_Pos          (8UL)     /*!< AHBEM (Bit 8)                                         */
+ #define R_SHOSTIF_IMR_AHBEM_Msk          (0x100UL) /*!< AHBEM (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_IMR_SPIMEM_Pos         (9UL)     /*!< SPIMEM (Bit 9)                                        */
+ #define R_SHOSTIF_IMR_SPIMEM_Msk         (0x200UL) /*!< SPIMEM (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  ISR  ========================================================== */
+ #define R_SHOSTIF_ISR_TXEIS_Pos          (0UL)     /*!< TXEIS (Bit 0)                                         */
+ #define R_SHOSTIF_ISR_TXEIS_Msk          (0x1UL)   /*!< TXEIS (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_RXOIS_Pos          (3UL)     /*!< RXOIS (Bit 3)                                         */
+ #define R_SHOSTIF_ISR_RXOIS_Msk          (0x8UL)   /*!< RXOIS (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_RXFIS_Pos          (4UL)     /*!< RXFIS (Bit 4)                                         */
+ #define R_SHOSTIF_ISR_RXFIS_Msk          (0x10UL)  /*!< RXFIS (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_TXUIS_Pos          (7UL)     /*!< TXUIS (Bit 7)                                         */
+ #define R_SHOSTIF_ISR_TXUIS_Msk          (0x80UL)  /*!< TXUIS (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_AHBES_Pos          (8UL)     /*!< AHBES (Bit 8)                                         */
+ #define R_SHOSTIF_ISR_AHBES_Msk          (0x100UL) /*!< AHBES (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_ISR_SPIMES_Pos         (9UL)     /*!< SPIMES (Bit 9)                                        */
+ #define R_SHOSTIF_ISR_SPIMES_Msk         (0x200UL) /*!< SPIMES (Bitfield-Mask: 0x01)                          */
+/* =========================================================  RISR  ========================================================== */
+ #define R_SHOSTIF_RISR_TXEIR_Pos         (0UL)     /*!< TXEIR (Bit 0)                                         */
+ #define R_SHOSTIF_RISR_TXEIR_Msk         (0x1UL)   /*!< TXEIR (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_RXOIR_Pos         (3UL)     /*!< RXOIR (Bit 3)                                         */
+ #define R_SHOSTIF_RISR_RXOIR_Msk         (0x8UL)   /*!< RXOIR (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_RXFIR_Pos         (4UL)     /*!< RXFIR (Bit 4)                                         */
+ #define R_SHOSTIF_RISR_RXFIR_Msk         (0x10UL)  /*!< RXFIR (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_TXUIR_Pos         (7UL)     /*!< TXUIR (Bit 7)                                         */
+ #define R_SHOSTIF_RISR_TXUIR_Msk         (0x80UL)  /*!< TXUIR (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_AHBER_Pos         (8UL)     /*!< AHBER (Bit 8)                                         */
+ #define R_SHOSTIF_RISR_AHBER_Msk         (0x100UL) /*!< AHBER (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_RISR_SPIMER_Pos        (9UL)     /*!< SPIMER (Bit 9)                                        */
+ #define R_SHOSTIF_RISR_SPIMER_Msk        (0x200UL) /*!< SPIMER (Bitfield-Mask: 0x01)                          */
+/* ========================================================  TXUICR  ========================================================= */
+ #define R_SHOSTIF_TXUICR_TXUICR_Pos      (0UL)     /*!< TXUICR (Bit 0)                                        */
+ #define R_SHOSTIF_TXUICR_TXUICR_Msk      (0x1UL)   /*!< TXUICR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RXOICR  ========================================================= */
+ #define R_SHOSTIF_RXOICR_RXOICR_Pos      (0UL)     /*!< RXOICR (Bit 0)                                        */
+ #define R_SHOSTIF_RXOICR_RXOICR_Msk      (0x1UL)   /*!< RXOICR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SPIMECR  ======================================================== */
+ #define R_SHOSTIF_SPIMECR_SPIMECR_Pos    (0UL)     /*!< SPIMECR (Bit 0)                                       */
+ #define R_SHOSTIF_SPIMECR_SPIMECR_Msk    (0x1UL)   /*!< SPIMECR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AHBECR  ========================================================= */
+ #define R_SHOSTIF_AHBECR_AHBECR_Pos      (0UL)     /*!< AHBECR (Bit 0)                                        */
+ #define R_SHOSTIF_AHBECR_AHBECR_Msk      (0x1UL)   /*!< AHBECR (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  ICR  ========================================================== */
+ #define R_SHOSTIF_ICR_ICR_Pos            (0UL)     /*!< ICR (Bit 0)                                           */
+ #define R_SHOSTIF_ICR_ICR_Msk            (0x1UL)   /*!< ICR (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSC_NS                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SCKCR  ========================================================= */
+ #define R_SYSC_NS_SCKCR_FSELXSPI0_Pos          (0UL)          /*!< FSELXSPI0 (Bit 0)                                     */
+ #define R_SYSC_NS_SCKCR_FSELXSPI0_Msk          (0x7UL)        /*!< FSELXSPI0 (Bitfield-Mask: 0x07)                       */
+ #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Pos        (6UL)          /*!< DIVSELXSPI0 (Bit 6)                                   */
+ #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Msk        (0x40UL)       /*!< DIVSELXSPI0 (Bitfield-Mask: 0x01)                     */
+ #define R_SYSC_NS_SCKCR_FSELXSPI1_Pos          (8UL)          /*!< FSELXSPI1 (Bit 8)                                     */
+ #define R_SYSC_NS_SCKCR_FSELXSPI1_Msk          (0x700UL)      /*!< FSELXSPI1 (Bitfield-Mask: 0x07)                       */
+ #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Pos        (14UL)         /*!< DIVSELXSPI1 (Bit 14)                                  */
+ #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Msk        (0x4000UL)     /*!< DIVSELXSPI1 (Bitfield-Mask: 0x01)                     */
+ #define R_SYSC_NS_SCKCR_CKIO_Pos               (16UL)         /*!< CKIO (Bit 16)                                         */
+ #define R_SYSC_NS_SCKCR_CKIO_Msk               (0x70000UL)    /*!< CKIO (Bitfield-Mask: 0x07)                            */
+ #define R_SYSC_NS_SCKCR_FSELCANFD_Pos          (20UL)         /*!< FSELCANFD (Bit 20)                                    */
+ #define R_SYSC_NS_SCKCR_FSELCANFD_Msk          (0x100000UL)   /*!< FSELCANFD (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_SCKCR_PHYSEL_Pos             (21UL)         /*!< PHYSEL (Bit 21)                                       */
+ #define R_SYSC_NS_SCKCR_PHYSEL_Msk             (0x200000UL)   /*!< PHYSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_SCKCR_CLMASEL_Pos            (22UL)         /*!< CLMASEL (Bit 22)                                      */
+ #define R_SYSC_NS_SCKCR_CLMASEL_Msk            (0x400000UL)   /*!< CLMASEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  SCKCR3  ========================================================= */
+ #define R_SYSC_NS_SCKCR3_SPI0ASYNCSEL_Pos      (0UL)          /*!< SPI0ASYNCSEL (Bit 0)                                  */
+ #define R_SYSC_NS_SCKCR3_SPI0ASYNCSEL_Msk      (0x3UL)        /*!< SPI0ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_NS_SCKCR3_SPI1ASYNCSEL_Pos      (2UL)          /*!< SPI1ASYNCSEL (Bit 2)                                  */
+ #define R_SYSC_NS_SCKCR3_SPI1ASYNCSEL_Msk      (0xcUL)        /*!< SPI1ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_NS_SCKCR3_SPI2ASYNCSEL_Pos      (4UL)          /*!< SPI2ASYNCSEL (Bit 4)                                  */
+ #define R_SYSC_NS_SCKCR3_SPI2ASYNCSEL_Msk      (0x30UL)       /*!< SPI2ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_NS_SCKCR3_SCI0ASYNCSEL_Pos      (6UL)          /*!< SCI0ASYNCSEL (Bit 6)                                  */
+ #define R_SYSC_NS_SCKCR3_SCI0ASYNCSEL_Msk      (0xc0UL)       /*!< SCI0ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_NS_SCKCR3_SCI1ASYNCSEL_Pos      (8UL)          /*!< SCI1ASYNCSEL (Bit 8)                                  */
+ #define R_SYSC_NS_SCKCR3_SCI1ASYNCSEL_Msk      (0x300UL)      /*!< SCI1ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_NS_SCKCR3_SCI2ASYNCSEL_Pos      (10UL)         /*!< SCI2ASYNCSEL (Bit 10)                                 */
+ #define R_SYSC_NS_SCKCR3_SCI2ASYNCSEL_Msk      (0xc00UL)      /*!< SCI2ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_NS_SCKCR3_SCI3ASYNCSEL_Pos      (12UL)         /*!< SCI3ASYNCSEL (Bit 12)                                 */
+ #define R_SYSC_NS_SCKCR3_SCI3ASYNCSEL_Msk      (0x3000UL)     /*!< SCI3ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_NS_SCKCR3_SCI4ASYNCSEL_Pos      (14UL)         /*!< SCI4ASYNCSEL (Bit 14)                                 */
+ #define R_SYSC_NS_SCKCR3_SCI4ASYNCSEL_Msk      (0xc000UL)     /*!< SCI4ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_NS_SCKCR3_LCDCDIVSEL_Pos        (20UL)         /*!< LCDCDIVSEL (Bit 20)                                   */
+ #define R_SYSC_NS_SCKCR3_LCDCDIVSEL_Msk        (0xf00000UL)   /*!< LCDCDIVSEL (Bitfield-Mask: 0x0f)                      */
+/* ========================================================  SCKCR4  ========================================================= */
+ #define R_SYSC_NS_SCKCR4_SCIE0ASYNCSEL_Pos     (0UL)          /*!< SCIE0ASYNCSEL (Bit 0)                                 */
+ #define R_SYSC_NS_SCKCR4_SCIE0ASYNCSEL_Msk     (0x3UL)        /*!< SCIE0ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE1ASYNCSEL_Pos     (2UL)          /*!< SCIE1ASYNCSEL (Bit 2)                                 */
+ #define R_SYSC_NS_SCKCR4_SCIE1ASYNCSEL_Msk     (0xcUL)        /*!< SCIE1ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE2ASYNCSEL_Pos     (4UL)          /*!< SCIE2ASYNCSEL (Bit 4)                                 */
+ #define R_SYSC_NS_SCKCR4_SCIE2ASYNCSEL_Msk     (0x30UL)       /*!< SCIE2ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE3ASYNCSEL_Pos     (6UL)          /*!< SCIE3ASYNCSEL (Bit 6)                                 */
+ #define R_SYSC_NS_SCKCR4_SCIE3ASYNCSEL_Msk     (0xc0UL)       /*!< SCIE3ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE4ASYNCSEL_Pos     (8UL)          /*!< SCIE4ASYNCSEL (Bit 8)                                 */
+ #define R_SYSC_NS_SCKCR4_SCIE4ASYNCSEL_Msk     (0x300UL)      /*!< SCIE4ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE5ASYNCSEL_Pos     (10UL)         /*!< SCIE5ASYNCSEL (Bit 10)                                */
+ #define R_SYSC_NS_SCKCR4_SCIE5ASYNCSEL_Msk     (0xc00UL)      /*!< SCIE5ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE6ASYNCSEL_Pos     (12UL)         /*!< SCIE6ASYNCSEL (Bit 12)                                */
+ #define R_SYSC_NS_SCKCR4_SCIE6ASYNCSEL_Msk     (0x3000UL)     /*!< SCIE6ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE7ASYNCSEL_Pos     (14UL)         /*!< SCIE7ASYNCSEL (Bit 14)                                */
+ #define R_SYSC_NS_SCKCR4_SCIE7ASYNCSEL_Msk     (0xc000UL)     /*!< SCIE7ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE8ASYNCSEL_Pos     (16UL)         /*!< SCIE8ASYNCSEL (Bit 16)                                */
+ #define R_SYSC_NS_SCKCR4_SCIE8ASYNCSEL_Msk     (0x30000UL)    /*!< SCIE8ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE9ASYNCSEL_Pos     (18UL)         /*!< SCIE9ASYNCSEL (Bit 18)                                */
+ #define R_SYSC_NS_SCKCR4_SCIE9ASYNCSEL_Msk     (0xc0000UL)    /*!< SCIE9ASYNCSEL (Bitfield-Mask: 0x03)                   */
+ #define R_SYSC_NS_SCKCR4_SCIE10ASYNCSEL_Pos    (20UL)         /*!< SCIE10ASYNCSEL (Bit 20)                               */
+ #define R_SYSC_NS_SCKCR4_SCIE10ASYNCSEL_Msk    (0x300000UL)   /*!< SCIE10ASYNCSEL (Bitfield-Mask: 0x03)                  */
+ #define R_SYSC_NS_SCKCR4_SCIE11ASYNCSEL_Pos    (22UL)         /*!< SCIE11ASYNCSEL (Bit 22)                               */
+ #define R_SYSC_NS_SCKCR4_SCIE11ASYNCSEL_Msk    (0xc00000UL)   /*!< SCIE11ASYNCSEL (Bitfield-Mask: 0x03)                  */
+ #define R_SYSC_NS_SCKCR4_ENCOUTCLK_Pos         (24UL)         /*!< ENCOUTCLK (Bit 24)                                    */
+ #define R_SYSC_NS_SCKCR4_ENCOUTCLK_Msk         (0x1000000UL)  /*!< ENCOUTCLK (Bitfield-Mask: 0x01)                       */
+/* ========================================================  RSTSR0  ========================================================= */
+ #define R_SYSC_NS_RSTSR0_TRF_Pos               (1UL)          /*!< TRF (Bit 1)                                           */
+ #define R_SYSC_NS_RSTSR0_TRF_Msk               (0x2UL)        /*!< TRF (Bitfield-Mask: 0x01)                             */
+ #define R_SYSC_NS_RSTSR0_ERRF_Pos              (2UL)          /*!< ERRF (Bit 2)                                          */
+ #define R_SYSC_NS_RSTSR0_ERRF_Msk              (0x4UL)        /*!< ERRF (Bitfield-Mask: 0x01)                            */
+ #define R_SYSC_NS_RSTSR0_SWRSF_Pos             (3UL)          /*!< SWRSF (Bit 3)                                         */
+ #define R_SYSC_NS_RSTSR0_SWRSF_Msk             (0x8UL)        /*!< SWRSF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSC_NS_RSTSR0_SWR0F_Pos             (4UL)          /*!< SWR0F (Bit 4)                                         */
+ #define R_SYSC_NS_RSTSR0_SWR0F_Msk             (0x10UL)       /*!< SWR0F (Bitfield-Mask: 0x01)                           */
+ #define R_SYSC_NS_RSTSR0_SWR1F_Pos             (5UL)          /*!< SWR1F (Bit 5)                                         */
+ #define R_SYSC_NS_RSTSR0_SWR1F_Msk             (0x20UL)       /*!< SWR1F (Bitfield-Mask: 0x01)                           */
+ #define R_SYSC_NS_RSTSR0_SWR55C_Pos            (6UL)          /*!< SWR55C (Bit 6)                                        */
+ #define R_SYSC_NS_RSTSR0_SWR55C_Msk            (0x40UL)       /*!< SWR55C (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_RSTSR0_SWR550_Pos            (7UL)          /*!< SWR550 (Bit 7)                                        */
+ #define R_SYSC_NS_RSTSR0_SWR550_Msk            (0x80UL)       /*!< SWR550 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_RSTSR0_SWR551_Pos            (8UL)          /*!< SWR551 (Bit 8)                                        */
+ #define R_SYSC_NS_RSTSR0_SWR551_Msk            (0x100UL)      /*!< SWR551 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_RSTSR0_SWR552_Pos            (9UL)          /*!< SWR552 (Bit 9)                                        */
+ #define R_SYSC_NS_RSTSR0_SWR552_Msk            (0x200UL)      /*!< SWR552 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_NS_RSTSR0_SWR553_Pos            (10UL)         /*!< SWR553 (Bit 10)                                       */
+ #define R_SYSC_NS_RSTSR0_SWR553_Msk            (0x400UL)      /*!< SWR553 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MRCTLA  ========================================================= */
+ #define R_SYSC_NS_MRCTLA_MRCTLA04_Pos          (4UL)          /*!< MRCTLA04 (Bit 4)                                      */
+ #define R_SYSC_NS_MRCTLA_MRCTLA04_Msk          (0x10UL)       /*!< MRCTLA04 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLA_MRCTLA05_Pos          (5UL)          /*!< MRCTLA05 (Bit 5)                                      */
+ #define R_SYSC_NS_MRCTLA_MRCTLA05_Msk          (0x20UL)       /*!< MRCTLA05 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MRCTLE  ========================================================= */
+ #define R_SYSC_NS_MRCTLE_MRCTLE00_Pos          (0UL)          /*!< MRCTLE00 (Bit 0)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE00_Msk          (0x1UL)        /*!< MRCTLE00 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE01_Pos          (1UL)          /*!< MRCTLE01 (Bit 1)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE01_Msk          (0x2UL)        /*!< MRCTLE01 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE02_Pos          (2UL)          /*!< MRCTLE02 (Bit 2)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE02_Msk          (0x4UL)        /*!< MRCTLE02 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE03_Pos          (3UL)          /*!< MRCTLE03 (Bit 3)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE03_Msk          (0x8UL)        /*!< MRCTLE03 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE04_Pos          (4UL)          /*!< MRCTLE04 (Bit 4)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE04_Msk          (0x10UL)       /*!< MRCTLE04 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE05_Pos          (5UL)          /*!< MRCTLE05 (Bit 5)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE05_Msk          (0x20UL)       /*!< MRCTLE05 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE06_Pos          (6UL)          /*!< MRCTLE06 (Bit 6)                                      */
+ #define R_SYSC_NS_MRCTLE_MRCTLE06_Msk          (0x40UL)       /*!< MRCTLE06 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE16_Pos          (16UL)         /*!< MRCTLE16 (Bit 16)                                     */
+ #define R_SYSC_NS_MRCTLE_MRCTLE16_Msk          (0x10000UL)    /*!< MRCTLE16 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE17_Pos          (17UL)         /*!< MRCTLE17 (Bit 17)                                     */
+ #define R_SYSC_NS_MRCTLE_MRCTLE17_Msk          (0x20000UL)    /*!< MRCTLE17 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE18_Pos          (18UL)         /*!< MRCTLE18 (Bit 18)                                     */
+ #define R_SYSC_NS_MRCTLE_MRCTLE18_Msk          (0x40000UL)    /*!< MRCTLE18 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLE_MRCTLE19_Pos          (19UL)         /*!< MRCTLE19 (Bit 19)                                     */
+ #define R_SYSC_NS_MRCTLE_MRCTLE19_Msk          (0x80000UL)    /*!< MRCTLE19 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MRCTLM  ========================================================= */
+ #define R_SYSC_NS_MRCTLM_MRCTLM8_Pos           (8UL)          /*!< MRCTLM8 (Bit 8)                                       */
+ #define R_SYSC_NS_MRCTLM_MRCTLM8_Msk           (0x100UL)      /*!< MRCTLM8 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSC_NS_MRCTLM_MRCTLM16_Pos          (16UL)         /*!< MRCTLM16 (Bit 16)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM16_Msk          (0x10000UL)    /*!< MRCTLM16 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM17_Pos          (17UL)         /*!< MRCTLM17 (Bit 17)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM17_Msk          (0x20000UL)    /*!< MRCTLM17 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM18_Pos          (18UL)         /*!< MRCTLM18 (Bit 18)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM18_Msk          (0x40000UL)    /*!< MRCTLM18 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM19_Pos          (19UL)         /*!< MRCTLM19 (Bit 19)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM19_Msk          (0x80000UL)    /*!< MRCTLM19 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM20_Pos          (20UL)         /*!< MRCTLM20 (Bit 20)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM20_Msk          (0x100000UL)   /*!< MRCTLM20 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM21_Pos          (21UL)         /*!< MRCTLM21 (Bit 21)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM21_Msk          (0x200000UL)   /*!< MRCTLM21 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM22_Pos          (22UL)         /*!< MRCTLM22 (Bit 22)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM22_Msk          (0x400000UL)   /*!< MRCTLM22 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM23_Pos          (23UL)         /*!< MRCTLM23 (Bit 23)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM23_Msk          (0x800000UL)   /*!< MRCTLM23 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM24_Pos          (24UL)         /*!< MRCTLM24 (Bit 24)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM24_Msk          (0x1000000UL)  /*!< MRCTLM24 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_NS_MRCTLM_MRCTLM25_Pos          (25UL)         /*!< MRCTLM25 (Bit 25)                                     */
+ #define R_SYSC_NS_MRCTLM_MRCTLM25_Msk          (0x2000000UL)  /*!< MRCTLM25 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MSTPCRA  ======================================================== */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Pos        (0UL)          /*!< MSTPCRA00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Msk        (0x1UL)        /*!< MSTPCRA00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Pos        (4UL)          /*!< MSTPCRA04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Msk        (0x10UL)       /*!< MSTPCRA04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Pos        (5UL)          /*!< MSTPCRA05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Msk        (0x20UL)       /*!< MSTPCRA05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Pos        (8UL)          /*!< MSTPCRA08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Msk        (0x100UL)      /*!< MSTPCRA08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Pos        (9UL)          /*!< MSTPCRA09 (Bit 9)                                     */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Msk        (0x200UL)      /*!< MSTPCRA09 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Pos        (10UL)         /*!< MSTPCRA10 (Bit 10)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Msk        (0x400UL)      /*!< MSTPCRA10 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Pos        (11UL)         /*!< MSTPCRA11 (Bit 11)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Msk        (0x800UL)      /*!< MSTPCRA11 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Pos        (12UL)         /*!< MSTPCRA12 (Bit 12)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Msk        (0x1000UL)     /*!< MSTPCRA12 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA16_Pos        (16UL)         /*!< MSTPCRA16 (Bit 16)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA16_Msk        (0x10000UL)    /*!< MSTPCRA16 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA17_Pos        (17UL)         /*!< MSTPCRA17 (Bit 17)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA17_Msk        (0x20000UL)    /*!< MSTPCRA17 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA18_Pos        (18UL)         /*!< MSTPCRA18 (Bit 18)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA18_Msk        (0x40000UL)    /*!< MSTPCRA18 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA19_Pos        (19UL)         /*!< MSTPCRA19 (Bit 19)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA19_Msk        (0x80000UL)    /*!< MSTPCRA19 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA20_Pos        (20UL)         /*!< MSTPCRA20 (Bit 20)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA20_Msk        (0x100000UL)   /*!< MSTPCRA20 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA21_Pos        (21UL)         /*!< MSTPCRA21 (Bit 21)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA21_Msk        (0x200000UL)   /*!< MSTPCRA21 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA22_Pos        (22UL)         /*!< MSTPCRA22 (Bit 22)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA22_Msk        (0x400000UL)   /*!< MSTPCRA22 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA23_Pos        (23UL)         /*!< MSTPCRA23 (Bit 23)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA23_Msk        (0x800000UL)   /*!< MSTPCRA23 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA24_Pos        (24UL)         /*!< MSTPCRA24 (Bit 24)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA24_Msk        (0x1000000UL)  /*!< MSTPCRA24 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA25_Pos        (25UL)         /*!< MSTPCRA25 (Bit 25)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA25_Msk        (0x2000000UL)  /*!< MSTPCRA25 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA26_Pos        (26UL)         /*!< MSTPCRA26 (Bit 26)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA26_Msk        (0x4000000UL)  /*!< MSTPCRA26 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA27_Pos        (27UL)         /*!< MSTPCRA27 (Bit 27)                                    */
+ #define R_SYSC_NS_MSTPCRA_MSTPCRA27_Msk        (0x8000000UL)  /*!< MSTPCRA27 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRB  ======================================================== */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Pos        (0UL)          /*!< MSTPCRB00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Msk        (0x1UL)        /*!< MSTPCRB00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Pos        (1UL)          /*!< MSTPCRB01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Msk        (0x2UL)        /*!< MSTPCRB01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Pos        (4UL)          /*!< MSTPCRB04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Msk        (0x10UL)       /*!< MSTPCRB04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Pos        (5UL)          /*!< MSTPCRB05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Msk        (0x20UL)       /*!< MSTPCRB05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Pos        (6UL)          /*!< MSTPCRB06 (Bit 6)                                     */
+ #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Msk        (0x40UL)       /*!< MSTPCRB06 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRC  ======================================================== */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Pos        (0UL)          /*!< MSTPCRC00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Msk        (0x1UL)        /*!< MSTPCRC00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Pos        (1UL)          /*!< MSTPCRC01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Msk        (0x2UL)        /*!< MSTPCRC01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Pos        (2UL)          /*!< MSTPCRC02 (Bit 2)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Msk        (0x4UL)        /*!< MSTPCRC02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Pos        (5UL)          /*!< MSTPCRC05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Msk        (0x20UL)       /*!< MSTPCRC05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Pos        (6UL)          /*!< MSTPCRC06 (Bit 6)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Msk        (0x40UL)       /*!< MSTPCRC06 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Pos        (7UL)          /*!< MSTPCRC07 (Bit 7)                                     */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Msk        (0x80UL)       /*!< MSTPCRC07 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC16_Pos        (16UL)         /*!< MSTPCRC16 (Bit 16)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC16_Msk        (0x10000UL)    /*!< MSTPCRC16 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC17_Pos        (17UL)         /*!< MSTPCRC17 (Bit 17)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC17_Msk        (0x20000UL)    /*!< MSTPCRC17 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC18_Pos        (18UL)         /*!< MSTPCRC18 (Bit 18)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC18_Msk        (0x40000UL)    /*!< MSTPCRC18 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC19_Pos        (19UL)         /*!< MSTPCRC19 (Bit 19)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC19_Msk        (0x80000UL)    /*!< MSTPCRC19 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC20_Pos        (20UL)         /*!< MSTPCRC20 (Bit 20)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC20_Msk        (0x100000UL)   /*!< MSTPCRC20 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC21_Pos        (21UL)         /*!< MSTPCRC21 (Bit 21)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC21_Msk        (0x200000UL)   /*!< MSTPCRC21 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC22_Pos        (22UL)         /*!< MSTPCRC22 (Bit 22)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC22_Msk        (0x400000UL)   /*!< MSTPCRC22 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC23_Pos        (23UL)         /*!< MSTPCRC23 (Bit 23)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC23_Msk        (0x800000UL)   /*!< MSTPCRC23 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC24_Pos        (24UL)         /*!< MSTPCRC24 (Bit 24)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC24_Msk        (0x1000000UL)  /*!< MSTPCRC24 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC25_Pos        (25UL)         /*!< MSTPCRC25 (Bit 25)                                    */
+ #define R_SYSC_NS_MSTPCRC_MSTPCRC25_Msk        (0x2000000UL)  /*!< MSTPCRC25 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRD  ======================================================== */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Pos        (0UL)          /*!< MSTPCRD00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Msk        (0x1UL)        /*!< MSTPCRD00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Pos        (1UL)          /*!< MSTPCRD01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Msk        (0x2UL)        /*!< MSTPCRD01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Pos        (2UL)          /*!< MSTPCRD02 (Bit 2)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Msk        (0x4UL)        /*!< MSTPCRD02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Pos        (3UL)          /*!< MSTPCRD03 (Bit 3)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Msk        (0x8UL)        /*!< MSTPCRD03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Pos        (4UL)          /*!< MSTPCRD04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Msk        (0x10UL)       /*!< MSTPCRD04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Pos        (5UL)          /*!< MSTPCRD05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Msk        (0x20UL)       /*!< MSTPCRD05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Pos        (6UL)          /*!< MSTPCRD06 (Bit 6)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Msk        (0x40UL)       /*!< MSTPCRD06 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Pos        (7UL)          /*!< MSTPCRD07 (Bit 7)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Msk        (0x80UL)       /*!< MSTPCRD07 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Pos        (8UL)          /*!< MSTPCRD08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Msk        (0x100UL)      /*!< MSTPCRD08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Pos        (9UL)          /*!< MSTPCRD09 (Bit 9)                                     */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Msk        (0x200UL)      /*!< MSTPCRD09 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Pos        (10UL)         /*!< MSTPCRD10 (Bit 10)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Msk        (0x400UL)      /*!< MSTPCRD10 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Pos        (11UL)         /*!< MSTPCRD11 (Bit 11)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Msk        (0x800UL)      /*!< MSTPCRD11 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD16_Pos        (16UL)         /*!< MSTPCRD16 (Bit 16)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD16_Msk        (0x10000UL)    /*!< MSTPCRD16 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD17_Pos        (17UL)         /*!< MSTPCRD17 (Bit 17)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD17_Msk        (0x20000UL)    /*!< MSTPCRD17 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD18_Pos        (18UL)         /*!< MSTPCRD18 (Bit 18)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD18_Msk        (0x40000UL)    /*!< MSTPCRD18 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD19_Pos        (19UL)         /*!< MSTPCRD19 (Bit 19)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD19_Msk        (0x80000UL)    /*!< MSTPCRD19 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD20_Pos        (20UL)         /*!< MSTPCRD20 (Bit 20)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD20_Msk        (0x100000UL)   /*!< MSTPCRD20 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD21_Pos        (21UL)         /*!< MSTPCRD21 (Bit 21)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD21_Msk        (0x200000UL)   /*!< MSTPCRD21 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD22_Pos        (22UL)         /*!< MSTPCRD22 (Bit 22)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD22_Msk        (0x400000UL)   /*!< MSTPCRD22 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD23_Pos        (23UL)         /*!< MSTPCRD23 (Bit 23)                                    */
+ #define R_SYSC_NS_MSTPCRD_MSTPCRD23_Msk        (0x800000UL)   /*!< MSTPCRD23 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRE  ======================================================== */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Pos        (0UL)          /*!< MSTPCRE00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Msk        (0x1UL)        /*!< MSTPCRE00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Pos        (1UL)          /*!< MSTPCRE01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Msk        (0x2UL)        /*!< MSTPCRE01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Pos        (2UL)          /*!< MSTPCRE02 (Bit 2)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Msk        (0x4UL)        /*!< MSTPCRE02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Pos        (3UL)          /*!< MSTPCRE03 (Bit 3)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Msk        (0x8UL)        /*!< MSTPCRE03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Pos        (8UL)          /*!< MSTPCRE08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Msk        (0x100UL)      /*!< MSTPCRE08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE16_Pos        (16UL)         /*!< MSTPCRE16 (Bit 16)                                    */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE16_Msk        (0x10000UL)    /*!< MSTPCRE16 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE17_Pos        (17UL)         /*!< MSTPCRE17 (Bit 17)                                    */
+ #define R_SYSC_NS_MSTPCRE_MSTPCRE17_Msk        (0x20000UL)    /*!< MSTPCRE17 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRJ  ======================================================== */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ00_Pos        (0UL)          /*!< MSTPCRJ00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ00_Msk        (0x1UL)        /*!< MSTPCRJ00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ01_Pos        (1UL)          /*!< MSTPCRJ01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ01_Msk        (0x2UL)        /*!< MSTPCRJ01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ02_Pos        (2UL)          /*!< MSTPCRJ02 (Bit 2)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ02_Msk        (0x4UL)        /*!< MSTPCRJ02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ03_Pos        (3UL)          /*!< MSTPCRJ03 (Bit 3)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ03_Msk        (0x8UL)        /*!< MSTPCRJ03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ04_Pos        (4UL)          /*!< MSTPCRJ04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ04_Msk        (0x10UL)       /*!< MSTPCRJ04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ05_Pos        (5UL)          /*!< MSTPCRJ05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ05_Msk        (0x20UL)       /*!< MSTPCRJ05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ06_Pos        (6UL)          /*!< MSTPCRJ06 (Bit 6)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ06_Msk        (0x40UL)       /*!< MSTPCRJ06 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ07_Pos        (7UL)          /*!< MSTPCRJ07 (Bit 7)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ07_Msk        (0x80UL)       /*!< MSTPCRJ07 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ08_Pos        (8UL)          /*!< MSTPCRJ08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ08_Msk        (0x100UL)      /*!< MSTPCRJ08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ09_Pos        (9UL)          /*!< MSTPCRJ09 (Bit 9)                                     */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ09_Msk        (0x200UL)      /*!< MSTPCRJ09 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ10_Pos        (10UL)         /*!< MSTPCRJ10 (Bit 10)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ10_Msk        (0x400UL)      /*!< MSTPCRJ10 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ11_Pos        (11UL)         /*!< MSTPCRJ11 (Bit 11)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ11_Msk        (0x800UL)      /*!< MSTPCRJ11 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ12_Pos        (12UL)         /*!< MSTPCRJ12 (Bit 12)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ12_Msk        (0x1000UL)     /*!< MSTPCRJ12 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ13_Pos        (13UL)         /*!< MSTPCRJ13 (Bit 13)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ13_Msk        (0x2000UL)     /*!< MSTPCRJ13 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ14_Pos        (14UL)         /*!< MSTPCRJ14 (Bit 14)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ14_Msk        (0x4000UL)     /*!< MSTPCRJ14 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ15_Pos        (15UL)         /*!< MSTPCRJ15 (Bit 15)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ15_Msk        (0x8000UL)     /*!< MSTPCRJ15 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ16_Pos        (16UL)         /*!< MSTPCRJ16 (Bit 16)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ16_Msk        (0x10000UL)    /*!< MSTPCRJ16 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ17_Pos        (17UL)         /*!< MSTPCRJ17 (Bit 17)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ17_Msk        (0x20000UL)    /*!< MSTPCRJ17 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ18_Pos        (18UL)         /*!< MSTPCRJ18 (Bit 18)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ18_Msk        (0x40000UL)    /*!< MSTPCRJ18 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ19_Pos        (19UL)         /*!< MSTPCRJ19 (Bit 19)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ19_Msk        (0x80000UL)    /*!< MSTPCRJ19 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ20_Pos        (20UL)         /*!< MSTPCRJ20 (Bit 20)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ20_Msk        (0x100000UL)   /*!< MSTPCRJ20 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ21_Pos        (21UL)         /*!< MSTPCRJ21 (Bit 21)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ21_Msk        (0x200000UL)   /*!< MSTPCRJ21 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ22_Pos        (22UL)         /*!< MSTPCRJ22 (Bit 22)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ22_Msk        (0x400000UL)   /*!< MSTPCRJ22 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ23_Pos        (23UL)         /*!< MSTPCRJ23 (Bit 23)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ23_Msk        (0x800000UL)   /*!< MSTPCRJ23 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ24_Pos        (24UL)         /*!< MSTPCRJ24 (Bit 24)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ24_Msk        (0x1000000UL)  /*!< MSTPCRJ24 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ25_Pos        (25UL)         /*!< MSTPCRJ25 (Bit 25)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ25_Msk        (0x2000000UL)  /*!< MSTPCRJ25 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ26_Pos        (26UL)         /*!< MSTPCRJ26 (Bit 26)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ26_Msk        (0x4000000UL)  /*!< MSTPCRJ26 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ27_Pos        (27UL)         /*!< MSTPCRJ27 (Bit 27)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ27_Msk        (0x8000000UL)  /*!< MSTPCRJ27 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ28_Pos        (28UL)         /*!< MSTPCRJ28 (Bit 28)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ28_Msk        (0x10000000UL) /*!< MSTPCRJ28 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ29_Pos        (29UL)         /*!< MSTPCRJ29 (Bit 29)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ29_Msk        (0x20000000UL) /*!< MSTPCRJ29 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ30_Pos        (30UL)         /*!< MSTPCRJ30 (Bit 30)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ30_Msk        (0x40000000UL) /*!< MSTPCRJ30 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ31_Pos        (31UL)         /*!< MSTPCRJ31 (Bit 31)                                    */
+ #define R_SYSC_NS_MSTPCRJ_MSTPCRJ31_Msk        (0x80000000UL) /*!< MSTPCRJ31 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRK  ======================================================== */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK00_Pos        (0UL)          /*!< MSTPCRK00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK00_Msk        (0x1UL)        /*!< MSTPCRK00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK01_Pos        (1UL)          /*!< MSTPCRK01 (Bit 1)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK01_Msk        (0x2UL)        /*!< MSTPCRK01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK02_Pos        (2UL)          /*!< MSTPCRK02 (Bit 2)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK02_Msk        (0x4UL)        /*!< MSTPCRK02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK03_Pos        (3UL)          /*!< MSTPCRK03 (Bit 3)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK03_Msk        (0x8UL)        /*!< MSTPCRK03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK04_Pos        (4UL)          /*!< MSTPCRK04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK04_Msk        (0x10UL)       /*!< MSTPCRK04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK05_Pos        (5UL)          /*!< MSTPCRK05 (Bit 5)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK05_Msk        (0x20UL)       /*!< MSTPCRK05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK06_Pos        (6UL)          /*!< MSTPCRK06 (Bit 6)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK06_Msk        (0x40UL)       /*!< MSTPCRK06 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK07_Pos        (7UL)          /*!< MSTPCRK07 (Bit 7)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK07_Msk        (0x80UL)       /*!< MSTPCRK07 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK08_Pos        (8UL)          /*!< MSTPCRK08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK08_Msk        (0x100UL)      /*!< MSTPCRK08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK09_Pos        (9UL)          /*!< MSTPCRK09 (Bit 9)                                     */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK09_Msk        (0x200UL)      /*!< MSTPCRK09 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK10_Pos        (10UL)         /*!< MSTPCRK10 (Bit 10)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK10_Msk        (0x400UL)      /*!< MSTPCRK10 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK11_Pos        (11UL)         /*!< MSTPCRK11 (Bit 11)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK11_Msk        (0x800UL)      /*!< MSTPCRK11 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK12_Pos        (12UL)         /*!< MSTPCRK12 (Bit 12)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK12_Msk        (0x1000UL)     /*!< MSTPCRK12 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK13_Pos        (13UL)         /*!< MSTPCRK13 (Bit 13)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK13_Msk        (0x2000UL)     /*!< MSTPCRK13 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK14_Pos        (14UL)         /*!< MSTPCRK14 (Bit 14)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK14_Msk        (0x4000UL)     /*!< MSTPCRK14 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK15_Pos        (15UL)         /*!< MSTPCRK15 (Bit 15)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK15_Msk        (0x8000UL)     /*!< MSTPCRK15 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK16_Pos        (16UL)         /*!< MSTPCRK16 (Bit 16)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK16_Msk        (0x10000UL)    /*!< MSTPCRK16 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK17_Pos        (17UL)         /*!< MSTPCRK17 (Bit 17)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK17_Msk        (0x20000UL)    /*!< MSTPCRK17 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK18_Pos        (18UL)         /*!< MSTPCRK18 (Bit 18)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK18_Msk        (0x40000UL)    /*!< MSTPCRK18 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK19_Pos        (19UL)         /*!< MSTPCRK19 (Bit 19)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK19_Msk        (0x80000UL)    /*!< MSTPCRK19 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK20_Pos        (20UL)         /*!< MSTPCRK20 (Bit 20)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK20_Msk        (0x100000UL)   /*!< MSTPCRK20 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK21_Pos        (21UL)         /*!< MSTPCRK21 (Bit 21)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK21_Msk        (0x200000UL)   /*!< MSTPCRK21 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK22_Pos        (22UL)         /*!< MSTPCRK22 (Bit 22)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK22_Msk        (0x400000UL)   /*!< MSTPCRK22 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK23_Pos        (23UL)         /*!< MSTPCRK23 (Bit 23)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK23_Msk        (0x800000UL)   /*!< MSTPCRK23 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK24_Pos        (24UL)         /*!< MSTPCRK24 (Bit 24)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK24_Msk        (0x1000000UL)  /*!< MSTPCRK24 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK25_Pos        (25UL)         /*!< MSTPCRK25 (Bit 25)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK25_Msk        (0x2000000UL)  /*!< MSTPCRK25 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK26_Pos        (26UL)         /*!< MSTPCRK26 (Bit 26)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK26_Msk        (0x4000000UL)  /*!< MSTPCRK26 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK27_Pos        (27UL)         /*!< MSTPCRK27 (Bit 27)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK27_Msk        (0x8000000UL)  /*!< MSTPCRK27 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK28_Pos        (28UL)         /*!< MSTPCRK28 (Bit 28)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK28_Msk        (0x10000000UL) /*!< MSTPCRK28 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK29_Pos        (29UL)         /*!< MSTPCRK29 (Bit 29)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK29_Msk        (0x20000000UL) /*!< MSTPCRK29 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK30_Pos        (30UL)         /*!< MSTPCRK30 (Bit 30)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK30_Msk        (0x40000000UL) /*!< MSTPCRK30 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK31_Pos        (31UL)         /*!< MSTPCRK31 (Bit 31)                                    */
+ #define R_SYSC_NS_MSTPCRK_MSTPCRK31_Msk        (0x80000000UL) /*!< MSTPCRK31 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRL  ======================================================== */
+ #define R_SYSC_NS_MSTPCRL_MSTPCRL00_Pos        (0UL)          /*!< MSTPCRL00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRL_MSTPCRL00_Msk        (0x1UL)        /*!< MSTPCRL00 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRM  ======================================================== */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM00_Pos        (0UL)          /*!< MSTPCRM00 (Bit 0)                                     */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM00_Msk        (0x1UL)        /*!< MSTPCRM00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM04_Pos        (4UL)          /*!< MSTPCRM04 (Bit 4)                                     */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM04_Msk        (0x10UL)       /*!< MSTPCRM04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM08_Pos        (8UL)          /*!< MSTPCRM08 (Bit 8)                                     */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM08_Msk        (0x100UL)      /*!< MSTPCRM08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM12_Pos        (12UL)         /*!< MSTPCRM12 (Bit 12)                                    */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM12_Msk        (0x1000UL)     /*!< MSTPCRM12 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM13_Pos        (13UL)         /*!< MSTPCRM13 (Bit 13)                                    */
+ #define R_SYSC_NS_MSTPCRM_MSTPCRM13_Msk        (0x2000UL)     /*!< MSTPCRM13 (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELO                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ELOPA  ========================================================= */
+ #define R_ELO_ELOPA_MTU0MD_Pos    (0UL)    /*!< MTU0MD (Bit 0)                                        */
+ #define R_ELO_ELOPA_MTU0MD_Msk    (0x3UL)  /*!< MTU0MD (Bitfield-Mask: 0x03)                          */
+ #define R_ELO_ELOPA_MTU3MD_Pos    (6UL)    /*!< MTU3MD (Bit 6)                                        */
+ #define R_ELO_ELOPA_MTU3MD_Msk    (0xc0UL) /*!< MTU3MD (Bitfield-Mask: 0x03)                          */
+/* =========================================================  ELOPB  ========================================================= */
+ #define R_ELO_ELOPB_MTU4MD_Pos    (0UL)    /*!< MTU4MD (Bit 0)                                        */
+ #define R_ELO_ELOPB_MTU4MD_Msk    (0x3UL)  /*!< MTU4MD (Bitfield-Mask: 0x03)                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_IC                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  GTIOCSEL  ======================================================== */
+ #define R_GPT_IC_GTIOCSEL_GT00_ISEL_Pos    (0UL)     /*!< GT00_ISEL (Bit 0)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT00_ISEL_Msk    (0x1UL)   /*!< GT00_ISEL (Bitfield-Mask: 0x01)                       */
+ #define R_GPT_IC_GTIOCSEL_GT01_ISEL_Pos    (1UL)     /*!< GT01_ISEL (Bit 1)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT01_ISEL_Msk    (0x2UL)   /*!< GT01_ISEL (Bitfield-Mask: 0x01)                       */
+ #define R_GPT_IC_GTIOCSEL_GT02_ISEL_Pos    (2UL)     /*!< GT02_ISEL (Bit 2)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT02_ISEL_Msk    (0x4UL)   /*!< GT02_ISEL (Bitfield-Mask: 0x01)                       */
+ #define R_GPT_IC_GTIOCSEL_GT03_ISEL_Pos    (3UL)     /*!< GT03_ISEL (Bit 3)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT03_ISEL_Msk    (0x8UL)   /*!< GT03_ISEL (Bitfield-Mask: 0x01)                       */
+ #define R_GPT_IC_GTIOCSEL_GT04_ISEL_Pos    (4UL)     /*!< GT04_ISEL (Bit 4)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT04_ISEL_Msk    (0x10UL)  /*!< GT04_ISEL (Bitfield-Mask: 0x01)                       */
+ #define R_GPT_IC_GTIOCSEL_GT05_ISEL_Pos    (5UL)     /*!< GT05_ISEL (Bit 5)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT05_ISEL_Msk    (0x20UL)  /*!< GT05_ISEL (Bitfield-Mask: 0x01)                       */
+ #define R_GPT_IC_GTIOCSEL_GT06_ISEL_Pos    (6UL)     /*!< GT06_ISEL (Bit 6)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT06_ISEL_Msk    (0x40UL)  /*!< GT06_ISEL (Bitfield-Mask: 0x01)                       */
+ #define R_GPT_IC_GTIOCSEL_GT07_ISEL_Pos    (7UL)     /*!< GT07_ISEL (Bit 7)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT07_ISEL_Msk    (0x80UL)  /*!< GT07_ISEL (Bitfield-Mask: 0x01)                       */
+ #define R_GPT_IC_GTIOCSEL_GT08_ISEL_Pos    (8UL)     /*!< GT08_ISEL (Bit 8)                                     */
+ #define R_GPT_IC_GTIOCSEL_GT08_ISEL_Msk    (0x100UL) /*!< GT08_ISEL (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ENCSS                                          ================ */
+/* =========================================================================================================================== */
+
+/* =====================================================  ENCODER_CFG0  ====================================================== */
+ #define R_ENCSS_ENCODER_CFG0_HF0ENDIAN_Pos       (0UL)          /*!< HF0ENDIAN (Bit 0)                                     */
+ #define R_ENCSS_ENCODER_CFG0_HF0ENDIAN_Msk       (0x1UL)        /*!< HF0ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG0_HF0SAFE1SEL_Pos     (1UL)          /*!< HF0SAFE1SEL (Bit 1)                                   */
+ #define R_ENCSS_ENCODER_CFG0_HF0SAFE1SEL_Msk     (0x2UL)        /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG0_EVTSRC0_Pos         (2UL)          /*!< EVTSRC0 (Bit 2)                                       */
+ #define R_ENCSS_ENCODER_CFG0_EVTSRC0_Msk         (0x4UL)        /*!< EVTSRC0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG0_SS0SEL_Pos          (3UL)          /*!< SS0SEL (Bit 3)                                        */
+ #define R_ENCSS_ENCODER_CFG0_SS0SEL_Msk          (0x18UL)       /*!< SS0SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG0_TRGSEL0_Pos         (5UL)          /*!< TRGSEL0 (Bit 5)                                       */
+ #define R_ENCSS_ENCODER_CFG0_TRGSEL0_Msk         (0x20UL)       /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG0_HF0SAFE2SEL_Pos     (6UL)          /*!< HF0SAFE2SEL (Bit 6)                                   */
+ #define R_ENCSS_ENCODER_CFG0_HF0SAFE2SEL_Msk     (0x40UL)       /*!< HF0SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG0_SS0SYNCSEL_Pos      (7UL)          /*!< SS0SYNCSEL (Bit 7)                                    */
+ #define R_ENCSS_ENCODER_CFG0_SS0SYNCSEL_Msk      (0x780UL)      /*!< SS0SYNCSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_ENCSS_ENCODER_CFG0_HF1ENDIAN_Pos       (16UL)         /*!< HF1ENDIAN (Bit 16)                                    */
+ #define R_ENCSS_ENCODER_CFG0_HF1ENDIAN_Msk       (0x10000UL)    /*!< HF1ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG0_HF1SAFE1SEL_Pos     (17UL)         /*!< HF1SAFE1SEL (Bit 17)                                  */
+ #define R_ENCSS_ENCODER_CFG0_HF1SAFE1SEL_Msk     (0x20000UL)    /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG0_EVTSRC1_Pos         (18UL)         /*!< EVTSRC1 (Bit 18)                                      */
+ #define R_ENCSS_ENCODER_CFG0_EVTSRC1_Msk         (0x40000UL)    /*!< EVTSRC1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG0_SS1SEL_Pos          (19UL)         /*!< SS1SEL (Bit 19)                                       */
+ #define R_ENCSS_ENCODER_CFG0_SS1SEL_Msk          (0x180000UL)   /*!< SS1SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG0_TRGSEL1_Pos         (21UL)         /*!< TRGSEL1 (Bit 21)                                      */
+ #define R_ENCSS_ENCODER_CFG0_TRGSEL1_Msk         (0x200000UL)   /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG0_HF1SAFE2SEL_Pos     (22UL)         /*!< HF1SAFE2SEL (Bit 22)                                  */
+ #define R_ENCSS_ENCODER_CFG0_HF1SAFE2SEL_Msk     (0x400000UL)   /*!< HF1SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG0_SS1SYNCSEL_Pos      (23UL)         /*!< SS1SYNCSEL (Bit 23)                                   */
+ #define R_ENCSS_ENCODER_CFG0_SS1SYNCSEL_Msk      (0x7800000UL)  /*!< SS1SYNCSEL (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  ENCODER_CFG1  ====================================================== */
+ #define R_ENCSS_ENCODER_CFG1_HF0ENDIAN_Pos       (0UL)          /*!< HF0ENDIAN (Bit 0)                                     */
+ #define R_ENCSS_ENCODER_CFG1_HF0ENDIAN_Msk       (0x1UL)        /*!< HF0ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG1_HF0SAFE1SEL_Pos     (1UL)          /*!< HF0SAFE1SEL (Bit 1)                                   */
+ #define R_ENCSS_ENCODER_CFG1_HF0SAFE1SEL_Msk     (0x2UL)        /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG1_EVTSRC0_Pos         (2UL)          /*!< EVTSRC0 (Bit 2)                                       */
+ #define R_ENCSS_ENCODER_CFG1_EVTSRC0_Msk         (0x4UL)        /*!< EVTSRC0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG1_SS0SEL_Pos          (3UL)          /*!< SS0SEL (Bit 3)                                        */
+ #define R_ENCSS_ENCODER_CFG1_SS0SEL_Msk          (0x18UL)       /*!< SS0SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG1_TRGSEL0_Pos         (5UL)          /*!< TRGSEL0 (Bit 5)                                       */
+ #define R_ENCSS_ENCODER_CFG1_TRGSEL0_Msk         (0x20UL)       /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG1_HF0SAFE2SEL_Pos     (6UL)          /*!< HF0SAFE2SEL (Bit 6)                                   */
+ #define R_ENCSS_ENCODER_CFG1_HF0SAFE2SEL_Msk     (0x40UL)       /*!< HF0SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG1_SS0SYNCSEL_Pos      (7UL)          /*!< SS0SYNCSEL (Bit 7)                                    */
+ #define R_ENCSS_ENCODER_CFG1_SS0SYNCSEL_Msk      (0x780UL)      /*!< SS0SYNCSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_ENCSS_ENCODER_CFG1_HF1ENDIAN_Pos       (16UL)         /*!< HF1ENDIAN (Bit 16)                                    */
+ #define R_ENCSS_ENCODER_CFG1_HF1ENDIAN_Msk       (0x10000UL)    /*!< HF1ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG1_HF1SAFE1SEL_Pos     (17UL)         /*!< HF1SAFE1SEL (Bit 17)                                  */
+ #define R_ENCSS_ENCODER_CFG1_HF1SAFE1SEL_Msk     (0x20000UL)    /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG1_EVTSRC1_Pos         (18UL)         /*!< EVTSRC1 (Bit 18)                                      */
+ #define R_ENCSS_ENCODER_CFG1_EVTSRC1_Msk         (0x40000UL)    /*!< EVTSRC1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG1_SS1SEL_Pos          (19UL)         /*!< SS1SEL (Bit 19)                                       */
+ #define R_ENCSS_ENCODER_CFG1_SS1SEL_Msk          (0x180000UL)   /*!< SS1SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG1_TRGSEL1_Pos         (21UL)         /*!< TRGSEL1 (Bit 21)                                      */
+ #define R_ENCSS_ENCODER_CFG1_TRGSEL1_Msk         (0x200000UL)   /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG1_HF1SAFE2SEL_Pos     (22UL)         /*!< HF1SAFE2SEL (Bit 22)                                  */
+ #define R_ENCSS_ENCODER_CFG1_HF1SAFE2SEL_Msk     (0x400000UL)   /*!< HF1SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG1_SS1SYNCSEL_Pos      (23UL)         /*!< SS1SYNCSEL (Bit 23)                                   */
+ #define R_ENCSS_ENCODER_CFG1_SS1SYNCSEL_Msk      (0x7800000UL)  /*!< SS1SYNCSEL (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  ENCODER_CFG2  ====================================================== */
+ #define R_ENCSS_ENCODER_CFG2_HF0ENDIAN_Pos       (0UL)          /*!< HF0ENDIAN (Bit 0)                                     */
+ #define R_ENCSS_ENCODER_CFG2_HF0ENDIAN_Msk       (0x1UL)        /*!< HF0ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG2_HF0SAFE1SEL_Pos     (1UL)          /*!< HF0SAFE1SEL (Bit 1)                                   */
+ #define R_ENCSS_ENCODER_CFG2_HF0SAFE1SEL_Msk     (0x2UL)        /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG2_EVTSRC0_Pos         (2UL)          /*!< EVTSRC0 (Bit 2)                                       */
+ #define R_ENCSS_ENCODER_CFG2_EVTSRC0_Msk         (0x4UL)        /*!< EVTSRC0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG2_SS0SEL_Pos          (3UL)          /*!< SS0SEL (Bit 3)                                        */
+ #define R_ENCSS_ENCODER_CFG2_SS0SEL_Msk          (0x18UL)       /*!< SS0SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG2_TRGSEL0_Pos         (5UL)          /*!< TRGSEL0 (Bit 5)                                       */
+ #define R_ENCSS_ENCODER_CFG2_TRGSEL0_Msk         (0x20UL)       /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG2_HF0SAFE2SEL_Pos     (6UL)          /*!< HF0SAFE2SEL (Bit 6)                                   */
+ #define R_ENCSS_ENCODER_CFG2_HF0SAFE2SEL_Msk     (0x40UL)       /*!< HF0SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG2_SS0SYNCSEL_Pos      (7UL)          /*!< SS0SYNCSEL (Bit 7)                                    */
+ #define R_ENCSS_ENCODER_CFG2_SS0SYNCSEL_Msk      (0x780UL)      /*!< SS0SYNCSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_ENCSS_ENCODER_CFG2_HF1ENDIAN_Pos       (16UL)         /*!< HF1ENDIAN (Bit 16)                                    */
+ #define R_ENCSS_ENCODER_CFG2_HF1ENDIAN_Msk       (0x10000UL)    /*!< HF1ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG2_HF1SAFE1SEL_Pos     (17UL)         /*!< HF1SAFE1SEL (Bit 17)                                  */
+ #define R_ENCSS_ENCODER_CFG2_HF1SAFE1SEL_Msk     (0x20000UL)    /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG2_EVTSRC1_Pos         (18UL)         /*!< EVTSRC1 (Bit 18)                                      */
+ #define R_ENCSS_ENCODER_CFG2_EVTSRC1_Msk         (0x40000UL)    /*!< EVTSRC1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG2_SS1SEL_Pos          (19UL)         /*!< SS1SEL (Bit 19)                                       */
+ #define R_ENCSS_ENCODER_CFG2_SS1SEL_Msk          (0x180000UL)   /*!< SS1SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG2_TRGSEL1_Pos         (21UL)         /*!< TRGSEL1 (Bit 21)                                      */
+ #define R_ENCSS_ENCODER_CFG2_TRGSEL1_Msk         (0x200000UL)   /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG2_HF1SAFE2SEL_Pos     (22UL)         /*!< HF1SAFE2SEL (Bit 22)                                  */
+ #define R_ENCSS_ENCODER_CFG2_HF1SAFE2SEL_Msk     (0x400000UL)   /*!< HF1SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG2_SS1SYNCSEL_Pos      (23UL)         /*!< SS1SYNCSEL (Bit 23)                                   */
+ #define R_ENCSS_ENCODER_CFG2_SS1SYNCSEL_Msk      (0x7800000UL)  /*!< SS1SYNCSEL (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  ENCODER_CFG3  ====================================================== */
+ #define R_ENCSS_ENCODER_CFG3_HF0ENDIAN_Pos       (0UL)          /*!< HF0ENDIAN (Bit 0)                                     */
+ #define R_ENCSS_ENCODER_CFG3_HF0ENDIAN_Msk       (0x1UL)        /*!< HF0ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG3_HF0SAFE1SEL_Pos     (1UL)          /*!< HF0SAFE1SEL (Bit 1)                                   */
+ #define R_ENCSS_ENCODER_CFG3_HF0SAFE1SEL_Msk     (0x2UL)        /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG3_EVTSRC0_Pos         (2UL)          /*!< EVTSRC0 (Bit 2)                                       */
+ #define R_ENCSS_ENCODER_CFG3_EVTSRC0_Msk         (0x4UL)        /*!< EVTSRC0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG3_SS0SEL_Pos          (3UL)          /*!< SS0SEL (Bit 3)                                        */
+ #define R_ENCSS_ENCODER_CFG3_SS0SEL_Msk          (0x18UL)       /*!< SS0SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG3_TRGSEL0_Pos         (5UL)          /*!< TRGSEL0 (Bit 5)                                       */
+ #define R_ENCSS_ENCODER_CFG3_TRGSEL0_Msk         (0x20UL)       /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG3_HF0SAFE2SEL_Pos     (6UL)          /*!< HF0SAFE2SEL (Bit 6)                                   */
+ #define R_ENCSS_ENCODER_CFG3_HF0SAFE2SEL_Msk     (0x40UL)       /*!< HF0SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG3_SS0SYNCSEL_Pos      (7UL)          /*!< SS0SYNCSEL (Bit 7)                                    */
+ #define R_ENCSS_ENCODER_CFG3_SS0SYNCSEL_Msk      (0x780UL)      /*!< SS0SYNCSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_ENCSS_ENCODER_CFG3_HF1ENDIAN_Pos       (16UL)         /*!< HF1ENDIAN (Bit 16)                                    */
+ #define R_ENCSS_ENCODER_CFG3_HF1ENDIAN_Msk       (0x10000UL)    /*!< HF1ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG3_HF1SAFE1SEL_Pos     (17UL)         /*!< HF1SAFE1SEL (Bit 17)                                  */
+ #define R_ENCSS_ENCODER_CFG3_HF1SAFE1SEL_Msk     (0x20000UL)    /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG3_EVTSRC1_Pos         (18UL)         /*!< EVTSRC1 (Bit 18)                                      */
+ #define R_ENCSS_ENCODER_CFG3_EVTSRC1_Msk         (0x40000UL)    /*!< EVTSRC1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG3_SS1SEL_Pos          (19UL)         /*!< SS1SEL (Bit 19)                                       */
+ #define R_ENCSS_ENCODER_CFG3_SS1SEL_Msk          (0x180000UL)   /*!< SS1SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG3_TRGSEL1_Pos         (21UL)         /*!< TRGSEL1 (Bit 21)                                      */
+ #define R_ENCSS_ENCODER_CFG3_TRGSEL1_Msk         (0x200000UL)   /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG3_HF1SAFE2SEL_Pos     (22UL)         /*!< HF1SAFE2SEL (Bit 22)                                  */
+ #define R_ENCSS_ENCODER_CFG3_HF1SAFE2SEL_Msk     (0x400000UL)   /*!< HF1SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG3_SS1SYNCSEL_Pos      (23UL)         /*!< SS1SYNCSEL (Bit 23)                                   */
+ #define R_ENCSS_ENCODER_CFG3_SS1SYNCSEL_Msk      (0x7800000UL)  /*!< SS1SYNCSEL (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  ENCODER_CFG4  ====================================================== */
+ #define R_ENCSS_ENCODER_CFG4_HF0ENDIAN_Pos       (0UL)          /*!< HF0ENDIAN (Bit 0)                                     */
+ #define R_ENCSS_ENCODER_CFG4_HF0ENDIAN_Msk       (0x1UL)        /*!< HF0ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG4_HF0SAFE1SEL_Pos     (1UL)          /*!< HF0SAFE1SEL (Bit 1)                                   */
+ #define R_ENCSS_ENCODER_CFG4_HF0SAFE1SEL_Msk     (0x2UL)        /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG4_EVTSRC0_Pos         (2UL)          /*!< EVTSRC0 (Bit 2)                                       */
+ #define R_ENCSS_ENCODER_CFG4_EVTSRC0_Msk         (0x4UL)        /*!< EVTSRC0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG4_SS0SEL_Pos          (3UL)          /*!< SS0SEL (Bit 3)                                        */
+ #define R_ENCSS_ENCODER_CFG4_SS0SEL_Msk          (0x18UL)       /*!< SS0SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG4_TRGSEL0_Pos         (5UL)          /*!< TRGSEL0 (Bit 5)                                       */
+ #define R_ENCSS_ENCODER_CFG4_TRGSEL0_Msk         (0x20UL)       /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG4_HF0SAFE2SEL_Pos     (6UL)          /*!< HF0SAFE2SEL (Bit 6)                                   */
+ #define R_ENCSS_ENCODER_CFG4_HF0SAFE2SEL_Msk     (0x40UL)       /*!< HF0SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG4_SS0SYNCSEL_Pos      (7UL)          /*!< SS0SYNCSEL (Bit 7)                                    */
+ #define R_ENCSS_ENCODER_CFG4_SS0SYNCSEL_Msk      (0x780UL)      /*!< SS0SYNCSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_ENCSS_ENCODER_CFG4_HF1ENDIAN_Pos       (16UL)         /*!< HF1ENDIAN (Bit 16)                                    */
+ #define R_ENCSS_ENCODER_CFG4_HF1ENDIAN_Msk       (0x10000UL)    /*!< HF1ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG4_HF1SAFE1SEL_Pos     (17UL)         /*!< HF1SAFE1SEL (Bit 17)                                  */
+ #define R_ENCSS_ENCODER_CFG4_HF1SAFE1SEL_Msk     (0x20000UL)    /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG4_EVTSRC1_Pos         (18UL)         /*!< EVTSRC1 (Bit 18)                                      */
+ #define R_ENCSS_ENCODER_CFG4_EVTSRC1_Msk         (0x40000UL)    /*!< EVTSRC1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG4_SS1SEL_Pos          (19UL)         /*!< SS1SEL (Bit 19)                                       */
+ #define R_ENCSS_ENCODER_CFG4_SS1SEL_Msk          (0x180000UL)   /*!< SS1SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG4_TRGSEL1_Pos         (21UL)         /*!< TRGSEL1 (Bit 21)                                      */
+ #define R_ENCSS_ENCODER_CFG4_TRGSEL1_Msk         (0x200000UL)   /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG4_HF1SAFE2SEL_Pos     (22UL)         /*!< HF1SAFE2SEL (Bit 22)                                  */
+ #define R_ENCSS_ENCODER_CFG4_HF1SAFE2SEL_Msk     (0x400000UL)   /*!< HF1SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG4_SS1SYNCSEL_Pos      (23UL)         /*!< SS1SYNCSEL (Bit 23)                                   */
+ #define R_ENCSS_ENCODER_CFG4_SS1SYNCSEL_Msk      (0x7800000UL)  /*!< SS1SYNCSEL (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  ENCODER_CFG5  ====================================================== */
+ #define R_ENCSS_ENCODER_CFG5_HF0ENDIAN_Pos       (0UL)          /*!< HF0ENDIAN (Bit 0)                                     */
+ #define R_ENCSS_ENCODER_CFG5_HF0ENDIAN_Msk       (0x1UL)        /*!< HF0ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG5_HF0SAFE1SEL_Pos     (1UL)          /*!< HF0SAFE1SEL (Bit 1)                                   */
+ #define R_ENCSS_ENCODER_CFG5_HF0SAFE1SEL_Msk     (0x2UL)        /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG5_EVTSRC0_Pos         (2UL)          /*!< EVTSRC0 (Bit 2)                                       */
+ #define R_ENCSS_ENCODER_CFG5_EVTSRC0_Msk         (0x4UL)        /*!< EVTSRC0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG5_SS0SEL_Pos          (3UL)          /*!< SS0SEL (Bit 3)                                        */
+ #define R_ENCSS_ENCODER_CFG5_SS0SEL_Msk          (0x18UL)       /*!< SS0SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG5_TRGSEL0_Pos         (5UL)          /*!< TRGSEL0 (Bit 5)                                       */
+ #define R_ENCSS_ENCODER_CFG5_TRGSEL0_Msk         (0x20UL)       /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG5_HF0SAFE2SEL_Pos     (6UL)          /*!< HF0SAFE2SEL (Bit 6)                                   */
+ #define R_ENCSS_ENCODER_CFG5_HF0SAFE2SEL_Msk     (0x40UL)       /*!< HF0SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG5_SS0SYNCSEL_Pos      (7UL)          /*!< SS0SYNCSEL (Bit 7)                                    */
+ #define R_ENCSS_ENCODER_CFG5_SS0SYNCSEL_Msk      (0x780UL)      /*!< SS0SYNCSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_ENCSS_ENCODER_CFG5_HF1ENDIAN_Pos       (16UL)         /*!< HF1ENDIAN (Bit 16)                                    */
+ #define R_ENCSS_ENCODER_CFG5_HF1ENDIAN_Msk       (0x10000UL)    /*!< HF1ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG5_HF1SAFE1SEL_Pos     (17UL)         /*!< HF1SAFE1SEL (Bit 17)                                  */
+ #define R_ENCSS_ENCODER_CFG5_HF1SAFE1SEL_Msk     (0x20000UL)    /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG5_EVTSRC1_Pos         (18UL)         /*!< EVTSRC1 (Bit 18)                                      */
+ #define R_ENCSS_ENCODER_CFG5_EVTSRC1_Msk         (0x40000UL)    /*!< EVTSRC1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG5_SS1SEL_Pos          (19UL)         /*!< SS1SEL (Bit 19)                                       */
+ #define R_ENCSS_ENCODER_CFG5_SS1SEL_Msk          (0x180000UL)   /*!< SS1SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG5_TRGSEL1_Pos         (21UL)         /*!< TRGSEL1 (Bit 21)                                      */
+ #define R_ENCSS_ENCODER_CFG5_TRGSEL1_Msk         (0x200000UL)   /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG5_HF1SAFE2SEL_Pos     (22UL)         /*!< HF1SAFE2SEL (Bit 22)                                  */
+ #define R_ENCSS_ENCODER_CFG5_HF1SAFE2SEL_Msk     (0x400000UL)   /*!< HF1SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG5_SS1SYNCSEL_Pos      (23UL)         /*!< SS1SYNCSEL (Bit 23)                                   */
+ #define R_ENCSS_ENCODER_CFG5_SS1SYNCSEL_Msk      (0x7800000UL)  /*!< SS1SYNCSEL (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  ENCODER_CFG6  ====================================================== */
+ #define R_ENCSS_ENCODER_CFG6_HF0ENDIAN_Pos       (0UL)          /*!< HF0ENDIAN (Bit 0)                                     */
+ #define R_ENCSS_ENCODER_CFG6_HF0ENDIAN_Msk       (0x1UL)        /*!< HF0ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG6_HF0SAFE1SEL_Pos     (1UL)          /*!< HF0SAFE1SEL (Bit 1)                                   */
+ #define R_ENCSS_ENCODER_CFG6_HF0SAFE1SEL_Msk     (0x2UL)        /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG6_EVTSRC0_Pos         (2UL)          /*!< EVTSRC0 (Bit 2)                                       */
+ #define R_ENCSS_ENCODER_CFG6_EVTSRC0_Msk         (0x4UL)        /*!< EVTSRC0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG6_SS0SEL_Pos          (3UL)          /*!< SS0SEL (Bit 3)                                        */
+ #define R_ENCSS_ENCODER_CFG6_SS0SEL_Msk          (0x18UL)       /*!< SS0SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG6_TRGSEL0_Pos         (5UL)          /*!< TRGSEL0 (Bit 5)                                       */
+ #define R_ENCSS_ENCODER_CFG6_TRGSEL0_Msk         (0x20UL)       /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG6_HF0SAFE2SEL_Pos     (6UL)          /*!< HF0SAFE2SEL (Bit 6)                                   */
+ #define R_ENCSS_ENCODER_CFG6_HF0SAFE2SEL_Msk     (0x40UL)       /*!< HF0SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG6_SS0SYNCSEL_Pos      (7UL)          /*!< SS0SYNCSEL (Bit 7)                                    */
+ #define R_ENCSS_ENCODER_CFG6_SS0SYNCSEL_Msk      (0x780UL)      /*!< SS0SYNCSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_ENCSS_ENCODER_CFG6_HF1ENDIAN_Pos       (16UL)         /*!< HF1ENDIAN (Bit 16)                                    */
+ #define R_ENCSS_ENCODER_CFG6_HF1ENDIAN_Msk       (0x10000UL)    /*!< HF1ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG6_HF1SAFE1SEL_Pos     (17UL)         /*!< HF1SAFE1SEL (Bit 17)                                  */
+ #define R_ENCSS_ENCODER_CFG6_HF1SAFE1SEL_Msk     (0x20000UL)    /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG6_EVTSRC1_Pos         (18UL)         /*!< EVTSRC1 (Bit 18)                                      */
+ #define R_ENCSS_ENCODER_CFG6_EVTSRC1_Msk         (0x40000UL)    /*!< EVTSRC1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG6_SS1SEL_Pos          (19UL)         /*!< SS1SEL (Bit 19)                                       */
+ #define R_ENCSS_ENCODER_CFG6_SS1SEL_Msk          (0x180000UL)   /*!< SS1SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG6_TRGSEL1_Pos         (21UL)         /*!< TRGSEL1 (Bit 21)                                      */
+ #define R_ENCSS_ENCODER_CFG6_TRGSEL1_Msk         (0x200000UL)   /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG6_HF1SAFE2SEL_Pos     (22UL)         /*!< HF1SAFE2SEL (Bit 22)                                  */
+ #define R_ENCSS_ENCODER_CFG6_HF1SAFE2SEL_Msk     (0x400000UL)   /*!< HF1SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG6_SS1SYNCSEL_Pos      (23UL)         /*!< SS1SYNCSEL (Bit 23)                                   */
+ #define R_ENCSS_ENCODER_CFG6_SS1SYNCSEL_Msk      (0x7800000UL)  /*!< SS1SYNCSEL (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  ENCODER_CFG7  ====================================================== */
+ #define R_ENCSS_ENCODER_CFG7_HF0ENDIAN_Pos       (0UL)          /*!< HF0ENDIAN (Bit 0)                                     */
+ #define R_ENCSS_ENCODER_CFG7_HF0ENDIAN_Msk       (0x1UL)        /*!< HF0ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG7_HF0SAFE1SEL_Pos     (1UL)          /*!< HF0SAFE1SEL (Bit 1)                                   */
+ #define R_ENCSS_ENCODER_CFG7_HF0SAFE1SEL_Msk     (0x2UL)        /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG7_EVTSRC0_Pos         (2UL)          /*!< EVTSRC0 (Bit 2)                                       */
+ #define R_ENCSS_ENCODER_CFG7_EVTSRC0_Msk         (0x4UL)        /*!< EVTSRC0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG7_SS0SEL_Pos          (3UL)          /*!< SS0SEL (Bit 3)                                        */
+ #define R_ENCSS_ENCODER_CFG7_SS0SEL_Msk          (0x18UL)       /*!< SS0SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG7_TRGSEL0_Pos         (5UL)          /*!< TRGSEL0 (Bit 5)                                       */
+ #define R_ENCSS_ENCODER_CFG7_TRGSEL0_Msk         (0x20UL)       /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG7_HF0SAFE2SEL_Pos     (6UL)          /*!< HF0SAFE2SEL (Bit 6)                                   */
+ #define R_ENCSS_ENCODER_CFG7_HF0SAFE2SEL_Msk     (0x40UL)       /*!< HF0SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG7_SS0SYNCSEL_Pos      (7UL)          /*!< SS0SYNCSEL (Bit 7)                                    */
+ #define R_ENCSS_ENCODER_CFG7_SS0SYNCSEL_Msk      (0x780UL)      /*!< SS0SYNCSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_ENCSS_ENCODER_CFG7_HF1ENDIAN_Pos       (16UL)         /*!< HF1ENDIAN (Bit 16)                                    */
+ #define R_ENCSS_ENCODER_CFG7_HF1ENDIAN_Msk       (0x10000UL)    /*!< HF1ENDIAN (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_ENCODER_CFG7_HF1SAFE1SEL_Pos     (17UL)         /*!< HF1SAFE1SEL (Bit 17)                                  */
+ #define R_ENCSS_ENCODER_CFG7_HF1SAFE1SEL_Msk     (0x20000UL)    /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG7_EVTSRC1_Pos         (18UL)         /*!< EVTSRC1 (Bit 18)                                      */
+ #define R_ENCSS_ENCODER_CFG7_EVTSRC1_Msk         (0x40000UL)    /*!< EVTSRC1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG7_SS1SEL_Pos          (19UL)         /*!< SS1SEL (Bit 19)                                       */
+ #define R_ENCSS_ENCODER_CFG7_SS1SEL_Msk          (0x180000UL)   /*!< SS1SEL (Bitfield-Mask: 0x03)                          */
+ #define R_ENCSS_ENCODER_CFG7_TRGSEL1_Pos         (21UL)         /*!< TRGSEL1 (Bit 21)                                      */
+ #define R_ENCSS_ENCODER_CFG7_TRGSEL1_Msk         (0x200000UL)   /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ENCSS_ENCODER_CFG7_HF1SAFE2SEL_Pos     (22UL)         /*!< HF1SAFE2SEL (Bit 22)                                  */
+ #define R_ENCSS_ENCODER_CFG7_HF1SAFE2SEL_Msk     (0x400000UL)   /*!< HF1SAFE2SEL (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_ENCODER_CFG7_SS1SYNCSEL_Pos      (23UL)         /*!< SS1SYNCSEL (Bit 23)                                   */
+ #define R_ENCSS_ENCODER_CFG7_SS1SYNCSEL_Msk      (0x7800000UL)  /*!< SS1SYNCSEL (Bitfield-Mask: 0x0f)                      */
+/* ======================================================  BISS_STAT0  ======================================================= */
+ #define R_ENCSS_BISS_STAT0_BISS0_ERR_Pos         (0UL)          /*!< BISS0_ERR (Bit 0)                                     */
+ #define R_ENCSS_BISS_STAT0_BISS0_ERR_Msk         (0x1UL)        /*!< BISS0_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT0_BISS0_EOT_Pos         (4UL)          /*!< BISS0_EOT (Bit 4)                                     */
+ #define R_ENCSS_BISS_STAT0_BISS0_EOT_Msk         (0x10UL)       /*!< BISS0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT0_BISS1_ERR_Pos         (16UL)         /*!< BISS1_ERR (Bit 16)                                    */
+ #define R_ENCSS_BISS_STAT0_BISS1_ERR_Msk         (0x10000UL)    /*!< BISS1_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT0_BISS1_EOT_Pos         (20UL)         /*!< BISS1_EOT (Bit 20)                                    */
+ #define R_ENCSS_BISS_STAT0_BISS1_EOT_Msk         (0x100000UL)   /*!< BISS1_EOT (Bitfield-Mask: 0x01)                       */
+/* ======================================================  BISS_STAT1  ======================================================= */
+ #define R_ENCSS_BISS_STAT1_BISS0_ERR_Pos         (0UL)          /*!< BISS0_ERR (Bit 0)                                     */
+ #define R_ENCSS_BISS_STAT1_BISS0_ERR_Msk         (0x1UL)        /*!< BISS0_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT1_BISS0_EOT_Pos         (4UL)          /*!< BISS0_EOT (Bit 4)                                     */
+ #define R_ENCSS_BISS_STAT1_BISS0_EOT_Msk         (0x10UL)       /*!< BISS0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT1_BISS1_ERR_Pos         (16UL)         /*!< BISS1_ERR (Bit 16)                                    */
+ #define R_ENCSS_BISS_STAT1_BISS1_ERR_Msk         (0x10000UL)    /*!< BISS1_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT1_BISS1_EOT_Pos         (20UL)         /*!< BISS1_EOT (Bit 20)                                    */
+ #define R_ENCSS_BISS_STAT1_BISS1_EOT_Msk         (0x100000UL)   /*!< BISS1_EOT (Bitfield-Mask: 0x01)                       */
+/* ======================================================  BISS_STAT2  ======================================================= */
+ #define R_ENCSS_BISS_STAT2_BISS0_ERR_Pos         (0UL)          /*!< BISS0_ERR (Bit 0)                                     */
+ #define R_ENCSS_BISS_STAT2_BISS0_ERR_Msk         (0x1UL)        /*!< BISS0_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT2_BISS0_EOT_Pos         (4UL)          /*!< BISS0_EOT (Bit 4)                                     */
+ #define R_ENCSS_BISS_STAT2_BISS0_EOT_Msk         (0x10UL)       /*!< BISS0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT2_BISS1_ERR_Pos         (16UL)         /*!< BISS1_ERR (Bit 16)                                    */
+ #define R_ENCSS_BISS_STAT2_BISS1_ERR_Msk         (0x10000UL)    /*!< BISS1_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT2_BISS1_EOT_Pos         (20UL)         /*!< BISS1_EOT (Bit 20)                                    */
+ #define R_ENCSS_BISS_STAT2_BISS1_EOT_Msk         (0x100000UL)   /*!< BISS1_EOT (Bitfield-Mask: 0x01)                       */
+/* ======================================================  BISS_STAT3  ======================================================= */
+ #define R_ENCSS_BISS_STAT3_BISS0_ERR_Pos         (0UL)          /*!< BISS0_ERR (Bit 0)                                     */
+ #define R_ENCSS_BISS_STAT3_BISS0_ERR_Msk         (0x1UL)        /*!< BISS0_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT3_BISS0_EOT_Pos         (4UL)          /*!< BISS0_EOT (Bit 4)                                     */
+ #define R_ENCSS_BISS_STAT3_BISS0_EOT_Msk         (0x10UL)       /*!< BISS0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT3_BISS1_ERR_Pos         (16UL)         /*!< BISS1_ERR (Bit 16)                                    */
+ #define R_ENCSS_BISS_STAT3_BISS1_ERR_Msk         (0x10000UL)    /*!< BISS1_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT3_BISS1_EOT_Pos         (20UL)         /*!< BISS1_EOT (Bit 20)                                    */
+ #define R_ENCSS_BISS_STAT3_BISS1_EOT_Msk         (0x100000UL)   /*!< BISS1_EOT (Bitfield-Mask: 0x01)                       */
+/* ======================================================  BISS_STAT4  ======================================================= */
+ #define R_ENCSS_BISS_STAT4_BISS0_ERR_Pos         (0UL)          /*!< BISS0_ERR (Bit 0)                                     */
+ #define R_ENCSS_BISS_STAT4_BISS0_ERR_Msk         (0x1UL)        /*!< BISS0_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT4_BISS0_EOT_Pos         (4UL)          /*!< BISS0_EOT (Bit 4)                                     */
+ #define R_ENCSS_BISS_STAT4_BISS0_EOT_Msk         (0x10UL)       /*!< BISS0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT4_BISS1_ERR_Pos         (16UL)         /*!< BISS1_ERR (Bit 16)                                    */
+ #define R_ENCSS_BISS_STAT4_BISS1_ERR_Msk         (0x10000UL)    /*!< BISS1_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT4_BISS1_EOT_Pos         (20UL)         /*!< BISS1_EOT (Bit 20)                                    */
+ #define R_ENCSS_BISS_STAT4_BISS1_EOT_Msk         (0x100000UL)   /*!< BISS1_EOT (Bitfield-Mask: 0x01)                       */
+/* ======================================================  BISS_STAT5  ======================================================= */
+ #define R_ENCSS_BISS_STAT5_BISS0_ERR_Pos         (0UL)          /*!< BISS0_ERR (Bit 0)                                     */
+ #define R_ENCSS_BISS_STAT5_BISS0_ERR_Msk         (0x1UL)        /*!< BISS0_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT5_BISS0_EOT_Pos         (4UL)          /*!< BISS0_EOT (Bit 4)                                     */
+ #define R_ENCSS_BISS_STAT5_BISS0_EOT_Msk         (0x10UL)       /*!< BISS0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT5_BISS1_ERR_Pos         (16UL)         /*!< BISS1_ERR (Bit 16)                                    */
+ #define R_ENCSS_BISS_STAT5_BISS1_ERR_Msk         (0x10000UL)    /*!< BISS1_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT5_BISS1_EOT_Pos         (20UL)         /*!< BISS1_EOT (Bit 20)                                    */
+ #define R_ENCSS_BISS_STAT5_BISS1_EOT_Msk         (0x100000UL)   /*!< BISS1_EOT (Bitfield-Mask: 0x01)                       */
+/* ======================================================  BISS_STAT6  ======================================================= */
+ #define R_ENCSS_BISS_STAT6_BISS0_ERR_Pos         (0UL)          /*!< BISS0_ERR (Bit 0)                                     */
+ #define R_ENCSS_BISS_STAT6_BISS0_ERR_Msk         (0x1UL)        /*!< BISS0_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT6_BISS0_EOT_Pos         (4UL)          /*!< BISS0_EOT (Bit 4)                                     */
+ #define R_ENCSS_BISS_STAT6_BISS0_EOT_Msk         (0x10UL)       /*!< BISS0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT6_BISS1_ERR_Pos         (16UL)         /*!< BISS1_ERR (Bit 16)                                    */
+ #define R_ENCSS_BISS_STAT6_BISS1_ERR_Msk         (0x10000UL)    /*!< BISS1_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT6_BISS1_EOT_Pos         (20UL)         /*!< BISS1_EOT (Bit 20)                                    */
+ #define R_ENCSS_BISS_STAT6_BISS1_EOT_Msk         (0x100000UL)   /*!< BISS1_EOT (Bitfield-Mask: 0x01)                       */
+/* ======================================================  BISS_STAT7  ======================================================= */
+ #define R_ENCSS_BISS_STAT7_BISS0_ERR_Pos         (0UL)          /*!< BISS0_ERR (Bit 0)                                     */
+ #define R_ENCSS_BISS_STAT7_BISS0_ERR_Msk         (0x1UL)        /*!< BISS0_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT7_BISS0_EOT_Pos         (4UL)          /*!< BISS0_EOT (Bit 4)                                     */
+ #define R_ENCSS_BISS_STAT7_BISS0_EOT_Msk         (0x10UL)       /*!< BISS0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT7_BISS1_ERR_Pos         (16UL)         /*!< BISS1_ERR (Bit 16)                                    */
+ #define R_ENCSS_BISS_STAT7_BISS1_ERR_Msk         (0x10000UL)    /*!< BISS1_ERR (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_BISS_STAT7_BISS1_EOT_Pos         (20UL)         /*!< BISS1_EOT (Bit 20)                                    */
+ #define R_ENCSS_BISS_STAT7_BISS1_EOT_Msk         (0x100000UL)   /*!< BISS1_EOT (Bitfield-Mask: 0x01)                       */
+/* ======================================================  HDSL_STAT0  ======================================================= */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_LINK_Pos        (0UL)          /*!< HDSL0_LINK (Bit 0)                                    */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_LINK_Msk        (0x1UL)        /*!< HDSL0_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_SYNCLCKD_Pos    (1UL)          /*!< HDSL0_SYNCLCKD (Bit 1)                                */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_SYNCLCKD_Msk    (0x2UL)        /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_ESTON_Pos       (4UL)          /*!< HDSL0_ESTON (Bit 4)                                   */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_ESTON_Msk       (0x10UL)       /*!< HDSL0_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_SCHERR_Pos      (5UL)          /*!< HDSL0_SCHERR (Bit 5)                                  */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_SCHERR_Msk      (0x20UL)       /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_SPERR_Pos       (6UL)          /*!< HDSL0_SPERR (Bit 6)                                   */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_SPERR_Msk       (0x40UL)       /*!< HDSL0_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_EDTERR_Pos      (7UL)          /*!< HDSL0_EDTERR (Bit 7)                                  */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_EDTERR_Msk      (0x80UL)       /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_ACCERR_Pos      (8UL)          /*!< HDSL0_ACCERR (Bit 8)                                  */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_ACCERR_Msk      (0x100UL)      /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_ACTHERR_Pos     (9UL)          /*!< HDSL0_ACTHERR (Bit 9)                                 */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_ACTHERR_Msk     (0x200UL)      /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_ENCERR_Pos      (10UL)         /*!< HDSL0_ENCERR (Bit 10)                                 */
+ #define R_ENCSS_HDSL_STAT0_HDSL0_ENCERR_Msk      (0x400UL)      /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_LINK_Pos        (16UL)         /*!< HDSL1_LINK (Bit 16)                                   */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_LINK_Msk        (0x10000UL)    /*!< HDSL1_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_SYNCLCKD_Pos    (17UL)         /*!< HDSL1_SYNCLCKD (Bit 17)                               */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_SYNCLCKD_Msk    (0x20000UL)    /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_ESTON_Pos       (20UL)         /*!< HDSL1_ESTON (Bit 20)                                  */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_ESTON_Msk       (0x100000UL)   /*!< HDSL1_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_SCHERR_Pos      (21UL)         /*!< HDSL1_SCHERR (Bit 21)                                 */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_SCHERR_Msk      (0x200000UL)   /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_SPERR_Pos       (22UL)         /*!< HDSL1_SPERR (Bit 22)                                  */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_SPERR_Msk       (0x400000UL)   /*!< HDSL1_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_EDTERR_Pos      (23UL)         /*!< HDSL1_EDTERR (Bit 23)                                 */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_EDTERR_Msk      (0x800000UL)   /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_ACCERR_Pos      (24UL)         /*!< HDSL1_ACCERR (Bit 24)                                 */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_ACCERR_Msk      (0x1000000UL)  /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_ACTHERR_Pos     (25UL)         /*!< HDSL1_ACTHERR (Bit 25)                                */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_ACTHERR_Msk     (0x2000000UL)  /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_ENCERR_Pos      (26UL)         /*!< HDSL1_ENCERR (Bit 26)                                 */
+ #define R_ENCSS_HDSL_STAT0_HDSL1_ENCERR_Msk      (0x4000000UL)  /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01)                    */
+/* ======================================================  HDSL_STAT1  ======================================================= */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_LINK_Pos        (0UL)          /*!< HDSL0_LINK (Bit 0)                                    */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_LINK_Msk        (0x1UL)        /*!< HDSL0_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_SYNCLCKD_Pos    (1UL)          /*!< HDSL0_SYNCLCKD (Bit 1)                                */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_SYNCLCKD_Msk    (0x2UL)        /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_ESTON_Pos       (4UL)          /*!< HDSL0_ESTON (Bit 4)                                   */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_ESTON_Msk       (0x10UL)       /*!< HDSL0_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_SCHERR_Pos      (5UL)          /*!< HDSL0_SCHERR (Bit 5)                                  */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_SCHERR_Msk      (0x20UL)       /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_SPERR_Pos       (6UL)          /*!< HDSL0_SPERR (Bit 6)                                   */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_SPERR_Msk       (0x40UL)       /*!< HDSL0_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_EDTERR_Pos      (7UL)          /*!< HDSL0_EDTERR (Bit 7)                                  */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_EDTERR_Msk      (0x80UL)       /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_ACCERR_Pos      (8UL)          /*!< HDSL0_ACCERR (Bit 8)                                  */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_ACCERR_Msk      (0x100UL)      /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_ACTHERR_Pos     (9UL)          /*!< HDSL0_ACTHERR (Bit 9)                                 */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_ACTHERR_Msk     (0x200UL)      /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_ENCERR_Pos      (10UL)         /*!< HDSL0_ENCERR (Bit 10)                                 */
+ #define R_ENCSS_HDSL_STAT1_HDSL0_ENCERR_Msk      (0x400UL)      /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_LINK_Pos        (16UL)         /*!< HDSL1_LINK (Bit 16)                                   */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_LINK_Msk        (0x10000UL)    /*!< HDSL1_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_SYNCLCKD_Pos    (17UL)         /*!< HDSL1_SYNCLCKD (Bit 17)                               */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_SYNCLCKD_Msk    (0x20000UL)    /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_ESTON_Pos       (20UL)         /*!< HDSL1_ESTON (Bit 20)                                  */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_ESTON_Msk       (0x100000UL)   /*!< HDSL1_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_SCHERR_Pos      (21UL)         /*!< HDSL1_SCHERR (Bit 21)                                 */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_SCHERR_Msk      (0x200000UL)   /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_SPERR_Pos       (22UL)         /*!< HDSL1_SPERR (Bit 22)                                  */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_SPERR_Msk       (0x400000UL)   /*!< HDSL1_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_EDTERR_Pos      (23UL)         /*!< HDSL1_EDTERR (Bit 23)                                 */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_EDTERR_Msk      (0x800000UL)   /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_ACCERR_Pos      (24UL)         /*!< HDSL1_ACCERR (Bit 24)                                 */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_ACCERR_Msk      (0x1000000UL)  /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_ACTHERR_Pos     (25UL)         /*!< HDSL1_ACTHERR (Bit 25)                                */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_ACTHERR_Msk     (0x2000000UL)  /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_ENCERR_Pos      (26UL)         /*!< HDSL1_ENCERR (Bit 26)                                 */
+ #define R_ENCSS_HDSL_STAT1_HDSL1_ENCERR_Msk      (0x4000000UL)  /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01)                    */
+/* ======================================================  HDSL_STAT2  ======================================================= */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_LINK_Pos        (0UL)          /*!< HDSL0_LINK (Bit 0)                                    */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_LINK_Msk        (0x1UL)        /*!< HDSL0_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_SYNCLCKD_Pos    (1UL)          /*!< HDSL0_SYNCLCKD (Bit 1)                                */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_SYNCLCKD_Msk    (0x2UL)        /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_ESTON_Pos       (4UL)          /*!< HDSL0_ESTON (Bit 4)                                   */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_ESTON_Msk       (0x10UL)       /*!< HDSL0_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_SCHERR_Pos      (5UL)          /*!< HDSL0_SCHERR (Bit 5)                                  */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_SCHERR_Msk      (0x20UL)       /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_SPERR_Pos       (6UL)          /*!< HDSL0_SPERR (Bit 6)                                   */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_SPERR_Msk       (0x40UL)       /*!< HDSL0_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_EDTERR_Pos      (7UL)          /*!< HDSL0_EDTERR (Bit 7)                                  */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_EDTERR_Msk      (0x80UL)       /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_ACCERR_Pos      (8UL)          /*!< HDSL0_ACCERR (Bit 8)                                  */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_ACCERR_Msk      (0x100UL)      /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_ACTHERR_Pos     (9UL)          /*!< HDSL0_ACTHERR (Bit 9)                                 */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_ACTHERR_Msk     (0x200UL)      /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_ENCERR_Pos      (10UL)         /*!< HDSL0_ENCERR (Bit 10)                                 */
+ #define R_ENCSS_HDSL_STAT2_HDSL0_ENCERR_Msk      (0x400UL)      /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_LINK_Pos        (16UL)         /*!< HDSL1_LINK (Bit 16)                                   */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_LINK_Msk        (0x10000UL)    /*!< HDSL1_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_SYNCLCKD_Pos    (17UL)         /*!< HDSL1_SYNCLCKD (Bit 17)                               */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_SYNCLCKD_Msk    (0x20000UL)    /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_ESTON_Pos       (20UL)         /*!< HDSL1_ESTON (Bit 20)                                  */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_ESTON_Msk       (0x100000UL)   /*!< HDSL1_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_SCHERR_Pos      (21UL)         /*!< HDSL1_SCHERR (Bit 21)                                 */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_SCHERR_Msk      (0x200000UL)   /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_SPERR_Pos       (22UL)         /*!< HDSL1_SPERR (Bit 22)                                  */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_SPERR_Msk       (0x400000UL)   /*!< HDSL1_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_EDTERR_Pos      (23UL)         /*!< HDSL1_EDTERR (Bit 23)                                 */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_EDTERR_Msk      (0x800000UL)   /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_ACCERR_Pos      (24UL)         /*!< HDSL1_ACCERR (Bit 24)                                 */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_ACCERR_Msk      (0x1000000UL)  /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_ACTHERR_Pos     (25UL)         /*!< HDSL1_ACTHERR (Bit 25)                                */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_ACTHERR_Msk     (0x2000000UL)  /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_ENCERR_Pos      (26UL)         /*!< HDSL1_ENCERR (Bit 26)                                 */
+ #define R_ENCSS_HDSL_STAT2_HDSL1_ENCERR_Msk      (0x4000000UL)  /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01)                    */
+/* ======================================================  HDSL_STAT3  ======================================================= */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_LINK_Pos        (0UL)          /*!< HDSL0_LINK (Bit 0)                                    */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_LINK_Msk        (0x1UL)        /*!< HDSL0_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_SYNCLCKD_Pos    (1UL)          /*!< HDSL0_SYNCLCKD (Bit 1)                                */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_SYNCLCKD_Msk    (0x2UL)        /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_ESTON_Pos       (4UL)          /*!< HDSL0_ESTON (Bit 4)                                   */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_ESTON_Msk       (0x10UL)       /*!< HDSL0_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_SCHERR_Pos      (5UL)          /*!< HDSL0_SCHERR (Bit 5)                                  */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_SCHERR_Msk      (0x20UL)       /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_SPERR_Pos       (6UL)          /*!< HDSL0_SPERR (Bit 6)                                   */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_SPERR_Msk       (0x40UL)       /*!< HDSL0_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_EDTERR_Pos      (7UL)          /*!< HDSL0_EDTERR (Bit 7)                                  */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_EDTERR_Msk      (0x80UL)       /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_ACCERR_Pos      (8UL)          /*!< HDSL0_ACCERR (Bit 8)                                  */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_ACCERR_Msk      (0x100UL)      /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_ACTHERR_Pos     (9UL)          /*!< HDSL0_ACTHERR (Bit 9)                                 */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_ACTHERR_Msk     (0x200UL)      /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_ENCERR_Pos      (10UL)         /*!< HDSL0_ENCERR (Bit 10)                                 */
+ #define R_ENCSS_HDSL_STAT3_HDSL0_ENCERR_Msk      (0x400UL)      /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_LINK_Pos        (16UL)         /*!< HDSL1_LINK (Bit 16)                                   */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_LINK_Msk        (0x10000UL)    /*!< HDSL1_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_SYNCLCKD_Pos    (17UL)         /*!< HDSL1_SYNCLCKD (Bit 17)                               */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_SYNCLCKD_Msk    (0x20000UL)    /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_ESTON_Pos       (20UL)         /*!< HDSL1_ESTON (Bit 20)                                  */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_ESTON_Msk       (0x100000UL)   /*!< HDSL1_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_SCHERR_Pos      (21UL)         /*!< HDSL1_SCHERR (Bit 21)                                 */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_SCHERR_Msk      (0x200000UL)   /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_SPERR_Pos       (22UL)         /*!< HDSL1_SPERR (Bit 22)                                  */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_SPERR_Msk       (0x400000UL)   /*!< HDSL1_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_EDTERR_Pos      (23UL)         /*!< HDSL1_EDTERR (Bit 23)                                 */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_EDTERR_Msk      (0x800000UL)   /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_ACCERR_Pos      (24UL)         /*!< HDSL1_ACCERR (Bit 24)                                 */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_ACCERR_Msk      (0x1000000UL)  /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_ACTHERR_Pos     (25UL)         /*!< HDSL1_ACTHERR (Bit 25)                                */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_ACTHERR_Msk     (0x2000000UL)  /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_ENCERR_Pos      (26UL)         /*!< HDSL1_ENCERR (Bit 26)                                 */
+ #define R_ENCSS_HDSL_STAT3_HDSL1_ENCERR_Msk      (0x4000000UL)  /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01)                    */
+/* ======================================================  HDSL_STAT4  ======================================================= */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_LINK_Pos        (0UL)          /*!< HDSL0_LINK (Bit 0)                                    */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_LINK_Msk        (0x1UL)        /*!< HDSL0_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_SYNCLCKD_Pos    (1UL)          /*!< HDSL0_SYNCLCKD (Bit 1)                                */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_SYNCLCKD_Msk    (0x2UL)        /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_ESTON_Pos       (4UL)          /*!< HDSL0_ESTON (Bit 4)                                   */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_ESTON_Msk       (0x10UL)       /*!< HDSL0_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_SCHERR_Pos      (5UL)          /*!< HDSL0_SCHERR (Bit 5)                                  */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_SCHERR_Msk      (0x20UL)       /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_SPERR_Pos       (6UL)          /*!< HDSL0_SPERR (Bit 6)                                   */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_SPERR_Msk       (0x40UL)       /*!< HDSL0_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_EDTERR_Pos      (7UL)          /*!< HDSL0_EDTERR (Bit 7)                                  */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_EDTERR_Msk      (0x80UL)       /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_ACCERR_Pos      (8UL)          /*!< HDSL0_ACCERR (Bit 8)                                  */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_ACCERR_Msk      (0x100UL)      /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_ACTHERR_Pos     (9UL)          /*!< HDSL0_ACTHERR (Bit 9)                                 */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_ACTHERR_Msk     (0x200UL)      /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_ENCERR_Pos      (10UL)         /*!< HDSL0_ENCERR (Bit 10)                                 */
+ #define R_ENCSS_HDSL_STAT4_HDSL0_ENCERR_Msk      (0x400UL)      /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_LINK_Pos        (16UL)         /*!< HDSL1_LINK (Bit 16)                                   */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_LINK_Msk        (0x10000UL)    /*!< HDSL1_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_SYNCLCKD_Pos    (17UL)         /*!< HDSL1_SYNCLCKD (Bit 17)                               */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_SYNCLCKD_Msk    (0x20000UL)    /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_ESTON_Pos       (20UL)         /*!< HDSL1_ESTON (Bit 20)                                  */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_ESTON_Msk       (0x100000UL)   /*!< HDSL1_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_SCHERR_Pos      (21UL)         /*!< HDSL1_SCHERR (Bit 21)                                 */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_SCHERR_Msk      (0x200000UL)   /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_SPERR_Pos       (22UL)         /*!< HDSL1_SPERR (Bit 22)                                  */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_SPERR_Msk       (0x400000UL)   /*!< HDSL1_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_EDTERR_Pos      (23UL)         /*!< HDSL1_EDTERR (Bit 23)                                 */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_EDTERR_Msk      (0x800000UL)   /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_ACCERR_Pos      (24UL)         /*!< HDSL1_ACCERR (Bit 24)                                 */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_ACCERR_Msk      (0x1000000UL)  /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_ACTHERR_Pos     (25UL)         /*!< HDSL1_ACTHERR (Bit 25)                                */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_ACTHERR_Msk     (0x2000000UL)  /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_ENCERR_Pos      (26UL)         /*!< HDSL1_ENCERR (Bit 26)                                 */
+ #define R_ENCSS_HDSL_STAT4_HDSL1_ENCERR_Msk      (0x4000000UL)  /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01)                    */
+/* ======================================================  HDSL_STAT5  ======================================================= */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_LINK_Pos        (0UL)          /*!< HDSL0_LINK (Bit 0)                                    */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_LINK_Msk        (0x1UL)        /*!< HDSL0_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_SYNCLCKD_Pos    (1UL)          /*!< HDSL0_SYNCLCKD (Bit 1)                                */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_SYNCLCKD_Msk    (0x2UL)        /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_ESTON_Pos       (4UL)          /*!< HDSL0_ESTON (Bit 4)                                   */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_ESTON_Msk       (0x10UL)       /*!< HDSL0_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_SCHERR_Pos      (5UL)          /*!< HDSL0_SCHERR (Bit 5)                                  */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_SCHERR_Msk      (0x20UL)       /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_SPERR_Pos       (6UL)          /*!< HDSL0_SPERR (Bit 6)                                   */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_SPERR_Msk       (0x40UL)       /*!< HDSL0_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_EDTERR_Pos      (7UL)          /*!< HDSL0_EDTERR (Bit 7)                                  */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_EDTERR_Msk      (0x80UL)       /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_ACCERR_Pos      (8UL)          /*!< HDSL0_ACCERR (Bit 8)                                  */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_ACCERR_Msk      (0x100UL)      /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_ACTHERR_Pos     (9UL)          /*!< HDSL0_ACTHERR (Bit 9)                                 */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_ACTHERR_Msk     (0x200UL)      /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_ENCERR_Pos      (10UL)         /*!< HDSL0_ENCERR (Bit 10)                                 */
+ #define R_ENCSS_HDSL_STAT5_HDSL0_ENCERR_Msk      (0x400UL)      /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_LINK_Pos        (16UL)         /*!< HDSL1_LINK (Bit 16)                                   */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_LINK_Msk        (0x10000UL)    /*!< HDSL1_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_SYNCLCKD_Pos    (17UL)         /*!< HDSL1_SYNCLCKD (Bit 17)                               */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_SYNCLCKD_Msk    (0x20000UL)    /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_ESTON_Pos       (20UL)         /*!< HDSL1_ESTON (Bit 20)                                  */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_ESTON_Msk       (0x100000UL)   /*!< HDSL1_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_SCHERR_Pos      (21UL)         /*!< HDSL1_SCHERR (Bit 21)                                 */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_SCHERR_Msk      (0x200000UL)   /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_SPERR_Pos       (22UL)         /*!< HDSL1_SPERR (Bit 22)                                  */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_SPERR_Msk       (0x400000UL)   /*!< HDSL1_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_EDTERR_Pos      (23UL)         /*!< HDSL1_EDTERR (Bit 23)                                 */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_EDTERR_Msk      (0x800000UL)   /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_ACCERR_Pos      (24UL)         /*!< HDSL1_ACCERR (Bit 24)                                 */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_ACCERR_Msk      (0x1000000UL)  /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_ACTHERR_Pos     (25UL)         /*!< HDSL1_ACTHERR (Bit 25)                                */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_ACTHERR_Msk     (0x2000000UL)  /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_ENCERR_Pos      (26UL)         /*!< HDSL1_ENCERR (Bit 26)                                 */
+ #define R_ENCSS_HDSL_STAT5_HDSL1_ENCERR_Msk      (0x4000000UL)  /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01)                    */
+/* ======================================================  HDSL_STAT6  ======================================================= */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_LINK_Pos        (0UL)          /*!< HDSL0_LINK (Bit 0)                                    */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_LINK_Msk        (0x1UL)        /*!< HDSL0_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_SYNCLCKD_Pos    (1UL)          /*!< HDSL0_SYNCLCKD (Bit 1)                                */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_SYNCLCKD_Msk    (0x2UL)        /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_ESTON_Pos       (4UL)          /*!< HDSL0_ESTON (Bit 4)                                   */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_ESTON_Msk       (0x10UL)       /*!< HDSL0_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_SCHERR_Pos      (5UL)          /*!< HDSL0_SCHERR (Bit 5)                                  */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_SCHERR_Msk      (0x20UL)       /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_SPERR_Pos       (6UL)          /*!< HDSL0_SPERR (Bit 6)                                   */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_SPERR_Msk       (0x40UL)       /*!< HDSL0_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_EDTERR_Pos      (7UL)          /*!< HDSL0_EDTERR (Bit 7)                                  */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_EDTERR_Msk      (0x80UL)       /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_ACCERR_Pos      (8UL)          /*!< HDSL0_ACCERR (Bit 8)                                  */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_ACCERR_Msk      (0x100UL)      /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_ACTHERR_Pos     (9UL)          /*!< HDSL0_ACTHERR (Bit 9)                                 */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_ACTHERR_Msk     (0x200UL)      /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_ENCERR_Pos      (10UL)         /*!< HDSL0_ENCERR (Bit 10)                                 */
+ #define R_ENCSS_HDSL_STAT6_HDSL0_ENCERR_Msk      (0x400UL)      /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_LINK_Pos        (16UL)         /*!< HDSL1_LINK (Bit 16)                                   */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_LINK_Msk        (0x10000UL)    /*!< HDSL1_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_SYNCLCKD_Pos    (17UL)         /*!< HDSL1_SYNCLCKD (Bit 17)                               */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_SYNCLCKD_Msk    (0x20000UL)    /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_ESTON_Pos       (20UL)         /*!< HDSL1_ESTON (Bit 20)                                  */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_ESTON_Msk       (0x100000UL)   /*!< HDSL1_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_SCHERR_Pos      (21UL)         /*!< HDSL1_SCHERR (Bit 21)                                 */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_SCHERR_Msk      (0x200000UL)   /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_SPERR_Pos       (22UL)         /*!< HDSL1_SPERR (Bit 22)                                  */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_SPERR_Msk       (0x400000UL)   /*!< HDSL1_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_EDTERR_Pos      (23UL)         /*!< HDSL1_EDTERR (Bit 23)                                 */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_EDTERR_Msk      (0x800000UL)   /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_ACCERR_Pos      (24UL)         /*!< HDSL1_ACCERR (Bit 24)                                 */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_ACCERR_Msk      (0x1000000UL)  /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_ACTHERR_Pos     (25UL)         /*!< HDSL1_ACTHERR (Bit 25)                                */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_ACTHERR_Msk     (0x2000000UL)  /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_ENCERR_Pos      (26UL)         /*!< HDSL1_ENCERR (Bit 26)                                 */
+ #define R_ENCSS_HDSL_STAT6_HDSL1_ENCERR_Msk      (0x4000000UL)  /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01)                    */
+/* ======================================================  HDSL_STAT7  ======================================================= */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_LINK_Pos        (0UL)          /*!< HDSL0_LINK (Bit 0)                                    */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_LINK_Msk        (0x1UL)        /*!< HDSL0_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_SYNCLCKD_Pos    (1UL)          /*!< HDSL0_SYNCLCKD (Bit 1)                                */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_SYNCLCKD_Msk    (0x2UL)        /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_ESTON_Pos       (4UL)          /*!< HDSL0_ESTON (Bit 4)                                   */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_ESTON_Msk       (0x10UL)       /*!< HDSL0_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_SCHERR_Pos      (5UL)          /*!< HDSL0_SCHERR (Bit 5)                                  */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_SCHERR_Msk      (0x20UL)       /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_SPERR_Pos       (6UL)          /*!< HDSL0_SPERR (Bit 6)                                   */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_SPERR_Msk       (0x40UL)       /*!< HDSL0_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_EDTERR_Pos      (7UL)          /*!< HDSL0_EDTERR (Bit 7)                                  */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_EDTERR_Msk      (0x80UL)       /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_ACCERR_Pos      (8UL)          /*!< HDSL0_ACCERR (Bit 8)                                  */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_ACCERR_Msk      (0x100UL)      /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_ACTHERR_Pos     (9UL)          /*!< HDSL0_ACTHERR (Bit 9)                                 */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_ACTHERR_Msk     (0x200UL)      /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_ENCERR_Pos      (10UL)         /*!< HDSL0_ENCERR (Bit 10)                                 */
+ #define R_ENCSS_HDSL_STAT7_HDSL0_ENCERR_Msk      (0x400UL)      /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_LINK_Pos        (16UL)         /*!< HDSL1_LINK (Bit 16)                                   */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_LINK_Msk        (0x10000UL)    /*!< HDSL1_LINK (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_SYNCLCKD_Pos    (17UL)         /*!< HDSL1_SYNCLCKD (Bit 17)                               */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_SYNCLCKD_Msk    (0x20000UL)    /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01)                  */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_ESTON_Pos       (20UL)         /*!< HDSL1_ESTON (Bit 20)                                  */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_ESTON_Msk       (0x100000UL)   /*!< HDSL1_ESTON (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_SCHERR_Pos      (21UL)         /*!< HDSL1_SCHERR (Bit 21)                                 */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_SCHERR_Msk      (0x200000UL)   /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_SPERR_Pos       (22UL)         /*!< HDSL1_SPERR (Bit 22)                                  */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_SPERR_Msk       (0x400000UL)   /*!< HDSL1_SPERR (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_EDTERR_Pos      (23UL)         /*!< HDSL1_EDTERR (Bit 23)                                 */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_EDTERR_Msk      (0x800000UL)   /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_ACCERR_Pos      (24UL)         /*!< HDSL1_ACCERR (Bit 24)                                 */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_ACCERR_Msk      (0x1000000UL)  /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01)                    */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_ACTHERR_Pos     (25UL)         /*!< HDSL1_ACTHERR (Bit 25)                                */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_ACTHERR_Msk     (0x2000000UL)  /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01)                   */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_ENCERR_Pos      (26UL)         /*!< HDSL1_ENCERR (Bit 26)                                 */
+ #define R_ENCSS_HDSL_STAT7_HDSL1_ENCERR_Msk      (0x4000000UL)  /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01)                    */
+/* ======================================================  ENDAT_CFG0  ======================================================= */
+ #define R_ENCSS_ENDAT_CFG0_ENDAT0_AXADD_Pos      (0UL)          /*!< ENDAT0_AXADD (Bit 0)                                  */
+ #define R_ENCSS_ENDAT_CFG0_ENDAT0_AXADD_Msk      (0x1fUL)       /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f)                    */
+ #define R_ENCSS_ENDAT_CFG0_ENDAT1_AXADD_Pos      (16UL)         /*!< ENDAT1_AXADD (Bit 16)                                 */
+ #define R_ENCSS_ENDAT_CFG0_ENDAT1_AXADD_Msk      (0x1f0000UL)   /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f)                    */
+/* ======================================================  ENDAT_CFG1  ======================================================= */
+ #define R_ENCSS_ENDAT_CFG1_ENDAT0_AXADD_Pos      (0UL)          /*!< ENDAT0_AXADD (Bit 0)                                  */
+ #define R_ENCSS_ENDAT_CFG1_ENDAT0_AXADD_Msk      (0x1fUL)       /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f)                    */
+ #define R_ENCSS_ENDAT_CFG1_ENDAT1_AXADD_Pos      (16UL)         /*!< ENDAT1_AXADD (Bit 16)                                 */
+ #define R_ENCSS_ENDAT_CFG1_ENDAT1_AXADD_Msk      (0x1f0000UL)   /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f)                    */
+/* ======================================================  ENDAT_CFG2  ======================================================= */
+ #define R_ENCSS_ENDAT_CFG2_ENDAT0_AXADD_Pos      (0UL)          /*!< ENDAT0_AXADD (Bit 0)                                  */
+ #define R_ENCSS_ENDAT_CFG2_ENDAT0_AXADD_Msk      (0x1fUL)       /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f)                    */
+ #define R_ENCSS_ENDAT_CFG2_ENDAT1_AXADD_Pos      (16UL)         /*!< ENDAT1_AXADD (Bit 16)                                 */
+ #define R_ENCSS_ENDAT_CFG2_ENDAT1_AXADD_Msk      (0x1f0000UL)   /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f)                    */
+/* ======================================================  ENDAT_CFG3  ======================================================= */
+ #define R_ENCSS_ENDAT_CFG3_ENDAT0_AXADD_Pos      (0UL)          /*!< ENDAT0_AXADD (Bit 0)                                  */
+ #define R_ENCSS_ENDAT_CFG3_ENDAT0_AXADD_Msk      (0x1fUL)       /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f)                    */
+ #define R_ENCSS_ENDAT_CFG3_ENDAT1_AXADD_Pos      (16UL)         /*!< ENDAT1_AXADD (Bit 16)                                 */
+ #define R_ENCSS_ENDAT_CFG3_ENDAT1_AXADD_Msk      (0x1f0000UL)   /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f)                    */
+/* ======================================================  ENDAT_CFG4  ======================================================= */
+ #define R_ENCSS_ENDAT_CFG4_ENDAT0_AXADD_Pos      (0UL)          /*!< ENDAT0_AXADD (Bit 0)                                  */
+ #define R_ENCSS_ENDAT_CFG4_ENDAT0_AXADD_Msk      (0x1fUL)       /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f)                    */
+ #define R_ENCSS_ENDAT_CFG4_ENDAT1_AXADD_Pos      (16UL)         /*!< ENDAT1_AXADD (Bit 16)                                 */
+ #define R_ENCSS_ENDAT_CFG4_ENDAT1_AXADD_Msk      (0x1f0000UL)   /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f)                    */
+/* ======================================================  ENDAT_CFG5  ======================================================= */
+ #define R_ENCSS_ENDAT_CFG5_ENDAT0_AXADD_Pos      (0UL)          /*!< ENDAT0_AXADD (Bit 0)                                  */
+ #define R_ENCSS_ENDAT_CFG5_ENDAT0_AXADD_Msk      (0x1fUL)       /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f)                    */
+ #define R_ENCSS_ENDAT_CFG5_ENDAT1_AXADD_Pos      (16UL)         /*!< ENDAT1_AXADD (Bit 16)                                 */
+ #define R_ENCSS_ENDAT_CFG5_ENDAT1_AXADD_Msk      (0x1f0000UL)   /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f)                    */
+/* ======================================================  ENDAT_CFG6  ======================================================= */
+ #define R_ENCSS_ENDAT_CFG6_ENDAT0_AXADD_Pos      (0UL)          /*!< ENDAT0_AXADD (Bit 0)                                  */
+ #define R_ENCSS_ENDAT_CFG6_ENDAT0_AXADD_Msk      (0x1fUL)       /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f)                    */
+ #define R_ENCSS_ENDAT_CFG6_ENDAT1_AXADD_Pos      (16UL)         /*!< ENDAT1_AXADD (Bit 16)                                 */
+ #define R_ENCSS_ENDAT_CFG6_ENDAT1_AXADD_Msk      (0x1f0000UL)   /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f)                    */
+/* ======================================================  ENDAT_CFG7  ======================================================= */
+ #define R_ENCSS_ENDAT_CFG7_ENDAT0_AXADD_Pos      (0UL)          /*!< ENDAT0_AXADD (Bit 0)                                  */
+ #define R_ENCSS_ENDAT_CFG7_ENDAT0_AXADD_Msk      (0x1fUL)       /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f)                    */
+ #define R_ENCSS_ENDAT_CFG7_ENDAT1_AXADD_Pos      (16UL)         /*!< ENDAT1_AXADD (Bit 16)                                 */
+ #define R_ENCSS_ENDAT_CFG7_ENDAT1_AXADD_Msk      (0x1f0000UL)   /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f)                    */
+/* ======================================================  AFMT_STAT0  ======================================================= */
+ #define R_ENCSS_AFMT_STAT0_AFMT0_BUSY_Pos        (0UL)          /*!< AFMT0_BUSY (Bit 0)                                    */
+ #define R_ENCSS_AFMT_STAT0_AFMT0_BUSY_Msk        (0x1UL)        /*!< AFMT0_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT0_AFMT0_EOT_Pos         (1UL)          /*!< AFMT0_EOT (Bit 1)                                     */
+ #define R_ENCSS_AFMT_STAT0_AFMT0_EOT_Msk         (0x2UL)        /*!< AFMT0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT0_AFMT0_TMOUT_Pos       (2UL)          /*!< AFMT0_TMOUT (Bit 2)                                   */
+ #define R_ENCSS_AFMT_STAT0_AFMT0_TMOUT_Msk       (0x4UL)        /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_AFMT_STAT0_AFMT1_BUSY_Pos        (16UL)         /*!< AFMT1_BUSY (Bit 16)                                   */
+ #define R_ENCSS_AFMT_STAT0_AFMT1_BUSY_Msk        (0x10000UL)    /*!< AFMT1_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT0_AFMT1_EOT_Pos         (17UL)         /*!< AFMT1_EOT (Bit 17)                                    */
+ #define R_ENCSS_AFMT_STAT0_AFMT1_EOT_Msk         (0x20000UL)    /*!< AFMT1_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT0_AFMT1_TMOUT_Pos       (18UL)         /*!< AFMT1_TMOUT (Bit 18)                                  */
+ #define R_ENCSS_AFMT_STAT0_AFMT1_TMOUT_Msk       (0x40000UL)    /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  AFMT_STAT1  ======================================================= */
+ #define R_ENCSS_AFMT_STAT1_AFMT0_BUSY_Pos        (0UL)          /*!< AFMT0_BUSY (Bit 0)                                    */
+ #define R_ENCSS_AFMT_STAT1_AFMT0_BUSY_Msk        (0x1UL)        /*!< AFMT0_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT1_AFMT0_EOT_Pos         (1UL)          /*!< AFMT0_EOT (Bit 1)                                     */
+ #define R_ENCSS_AFMT_STAT1_AFMT0_EOT_Msk         (0x2UL)        /*!< AFMT0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT1_AFMT0_TMOUT_Pos       (2UL)          /*!< AFMT0_TMOUT (Bit 2)                                   */
+ #define R_ENCSS_AFMT_STAT1_AFMT0_TMOUT_Msk       (0x4UL)        /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_AFMT_STAT1_AFMT1_BUSY_Pos        (16UL)         /*!< AFMT1_BUSY (Bit 16)                                   */
+ #define R_ENCSS_AFMT_STAT1_AFMT1_BUSY_Msk        (0x10000UL)    /*!< AFMT1_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT1_AFMT1_EOT_Pos         (17UL)         /*!< AFMT1_EOT (Bit 17)                                    */
+ #define R_ENCSS_AFMT_STAT1_AFMT1_EOT_Msk         (0x20000UL)    /*!< AFMT1_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT1_AFMT1_TMOUT_Pos       (18UL)         /*!< AFMT1_TMOUT (Bit 18)                                  */
+ #define R_ENCSS_AFMT_STAT1_AFMT1_TMOUT_Msk       (0x40000UL)    /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  AFMT_STAT2  ======================================================= */
+ #define R_ENCSS_AFMT_STAT2_AFMT0_BUSY_Pos        (0UL)          /*!< AFMT0_BUSY (Bit 0)                                    */
+ #define R_ENCSS_AFMT_STAT2_AFMT0_BUSY_Msk        (0x1UL)        /*!< AFMT0_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT2_AFMT0_EOT_Pos         (1UL)          /*!< AFMT0_EOT (Bit 1)                                     */
+ #define R_ENCSS_AFMT_STAT2_AFMT0_EOT_Msk         (0x2UL)        /*!< AFMT0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT2_AFMT0_TMOUT_Pos       (2UL)          /*!< AFMT0_TMOUT (Bit 2)                                   */
+ #define R_ENCSS_AFMT_STAT2_AFMT0_TMOUT_Msk       (0x4UL)        /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_AFMT_STAT2_AFMT1_BUSY_Pos        (16UL)         /*!< AFMT1_BUSY (Bit 16)                                   */
+ #define R_ENCSS_AFMT_STAT2_AFMT1_BUSY_Msk        (0x10000UL)    /*!< AFMT1_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT2_AFMT1_EOT_Pos         (17UL)         /*!< AFMT1_EOT (Bit 17)                                    */
+ #define R_ENCSS_AFMT_STAT2_AFMT1_EOT_Msk         (0x20000UL)    /*!< AFMT1_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT2_AFMT1_TMOUT_Pos       (18UL)         /*!< AFMT1_TMOUT (Bit 18)                                  */
+ #define R_ENCSS_AFMT_STAT2_AFMT1_TMOUT_Msk       (0x40000UL)    /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  AFMT_STAT3  ======================================================= */
+ #define R_ENCSS_AFMT_STAT3_AFMT0_BUSY_Pos        (0UL)          /*!< AFMT0_BUSY (Bit 0)                                    */
+ #define R_ENCSS_AFMT_STAT3_AFMT0_BUSY_Msk        (0x1UL)        /*!< AFMT0_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT3_AFMT0_EOT_Pos         (1UL)          /*!< AFMT0_EOT (Bit 1)                                     */
+ #define R_ENCSS_AFMT_STAT3_AFMT0_EOT_Msk         (0x2UL)        /*!< AFMT0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT3_AFMT0_TMOUT_Pos       (2UL)          /*!< AFMT0_TMOUT (Bit 2)                                   */
+ #define R_ENCSS_AFMT_STAT3_AFMT0_TMOUT_Msk       (0x4UL)        /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_AFMT_STAT3_AFMT1_BUSY_Pos        (16UL)         /*!< AFMT1_BUSY (Bit 16)                                   */
+ #define R_ENCSS_AFMT_STAT3_AFMT1_BUSY_Msk        (0x10000UL)    /*!< AFMT1_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT3_AFMT1_EOT_Pos         (17UL)         /*!< AFMT1_EOT (Bit 17)                                    */
+ #define R_ENCSS_AFMT_STAT3_AFMT1_EOT_Msk         (0x20000UL)    /*!< AFMT1_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT3_AFMT1_TMOUT_Pos       (18UL)         /*!< AFMT1_TMOUT (Bit 18)                                  */
+ #define R_ENCSS_AFMT_STAT3_AFMT1_TMOUT_Msk       (0x40000UL)    /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  AFMT_STAT4  ======================================================= */
+ #define R_ENCSS_AFMT_STAT4_AFMT0_BUSY_Pos        (0UL)          /*!< AFMT0_BUSY (Bit 0)                                    */
+ #define R_ENCSS_AFMT_STAT4_AFMT0_BUSY_Msk        (0x1UL)        /*!< AFMT0_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT4_AFMT0_EOT_Pos         (1UL)          /*!< AFMT0_EOT (Bit 1)                                     */
+ #define R_ENCSS_AFMT_STAT4_AFMT0_EOT_Msk         (0x2UL)        /*!< AFMT0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT4_AFMT0_TMOUT_Pos       (2UL)          /*!< AFMT0_TMOUT (Bit 2)                                   */
+ #define R_ENCSS_AFMT_STAT4_AFMT0_TMOUT_Msk       (0x4UL)        /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_AFMT_STAT4_AFMT1_BUSY_Pos        (16UL)         /*!< AFMT1_BUSY (Bit 16)                                   */
+ #define R_ENCSS_AFMT_STAT4_AFMT1_BUSY_Msk        (0x10000UL)    /*!< AFMT1_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT4_AFMT1_EOT_Pos         (17UL)         /*!< AFMT1_EOT (Bit 17)                                    */
+ #define R_ENCSS_AFMT_STAT4_AFMT1_EOT_Msk         (0x20000UL)    /*!< AFMT1_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT4_AFMT1_TMOUT_Pos       (18UL)         /*!< AFMT1_TMOUT (Bit 18)                                  */
+ #define R_ENCSS_AFMT_STAT4_AFMT1_TMOUT_Msk       (0x40000UL)    /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  AFMT_STAT5  ======================================================= */
+ #define R_ENCSS_AFMT_STAT5_AFMT0_BUSY_Pos        (0UL)          /*!< AFMT0_BUSY (Bit 0)                                    */
+ #define R_ENCSS_AFMT_STAT5_AFMT0_BUSY_Msk        (0x1UL)        /*!< AFMT0_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT5_AFMT0_EOT_Pos         (1UL)          /*!< AFMT0_EOT (Bit 1)                                     */
+ #define R_ENCSS_AFMT_STAT5_AFMT0_EOT_Msk         (0x2UL)        /*!< AFMT0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT5_AFMT0_TMOUT_Pos       (2UL)          /*!< AFMT0_TMOUT (Bit 2)                                   */
+ #define R_ENCSS_AFMT_STAT5_AFMT0_TMOUT_Msk       (0x4UL)        /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_AFMT_STAT5_AFMT1_BUSY_Pos        (16UL)         /*!< AFMT1_BUSY (Bit 16)                                   */
+ #define R_ENCSS_AFMT_STAT5_AFMT1_BUSY_Msk        (0x10000UL)    /*!< AFMT1_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT5_AFMT1_EOT_Pos         (17UL)         /*!< AFMT1_EOT (Bit 17)                                    */
+ #define R_ENCSS_AFMT_STAT5_AFMT1_EOT_Msk         (0x20000UL)    /*!< AFMT1_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT5_AFMT1_TMOUT_Pos       (18UL)         /*!< AFMT1_TMOUT (Bit 18)                                  */
+ #define R_ENCSS_AFMT_STAT5_AFMT1_TMOUT_Msk       (0x40000UL)    /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  AFMT_STAT6  ======================================================= */
+ #define R_ENCSS_AFMT_STAT6_AFMT0_BUSY_Pos        (0UL)          /*!< AFMT0_BUSY (Bit 0)                                    */
+ #define R_ENCSS_AFMT_STAT6_AFMT0_BUSY_Msk        (0x1UL)        /*!< AFMT0_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT6_AFMT0_EOT_Pos         (1UL)          /*!< AFMT0_EOT (Bit 1)                                     */
+ #define R_ENCSS_AFMT_STAT6_AFMT0_EOT_Msk         (0x2UL)        /*!< AFMT0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT6_AFMT0_TMOUT_Pos       (2UL)          /*!< AFMT0_TMOUT (Bit 2)                                   */
+ #define R_ENCSS_AFMT_STAT6_AFMT0_TMOUT_Msk       (0x4UL)        /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_AFMT_STAT6_AFMT1_BUSY_Pos        (16UL)         /*!< AFMT1_BUSY (Bit 16)                                   */
+ #define R_ENCSS_AFMT_STAT6_AFMT1_BUSY_Msk        (0x10000UL)    /*!< AFMT1_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT6_AFMT1_EOT_Pos         (17UL)         /*!< AFMT1_EOT (Bit 17)                                    */
+ #define R_ENCSS_AFMT_STAT6_AFMT1_EOT_Msk         (0x20000UL)    /*!< AFMT1_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT6_AFMT1_TMOUT_Pos       (18UL)         /*!< AFMT1_TMOUT (Bit 18)                                  */
+ #define R_ENCSS_AFMT_STAT6_AFMT1_TMOUT_Msk       (0x40000UL)    /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  AFMT_STAT7  ======================================================= */
+ #define R_ENCSS_AFMT_STAT7_AFMT0_BUSY_Pos        (0UL)          /*!< AFMT0_BUSY (Bit 0)                                    */
+ #define R_ENCSS_AFMT_STAT7_AFMT0_BUSY_Msk        (0x1UL)        /*!< AFMT0_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT7_AFMT0_EOT_Pos         (1UL)          /*!< AFMT0_EOT (Bit 1)                                     */
+ #define R_ENCSS_AFMT_STAT7_AFMT0_EOT_Msk         (0x2UL)        /*!< AFMT0_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT7_AFMT0_TMOUT_Pos       (2UL)          /*!< AFMT0_TMOUT (Bit 2)                                   */
+ #define R_ENCSS_AFMT_STAT7_AFMT0_TMOUT_Msk       (0x4UL)        /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01)                     */
+ #define R_ENCSS_AFMT_STAT7_AFMT1_BUSY_Pos        (16UL)         /*!< AFMT1_BUSY (Bit 16)                                   */
+ #define R_ENCSS_AFMT_STAT7_AFMT1_BUSY_Msk        (0x10000UL)    /*!< AFMT1_BUSY (Bitfield-Mask: 0x01)                      */
+ #define R_ENCSS_AFMT_STAT7_AFMT1_EOT_Pos         (17UL)         /*!< AFMT1_EOT (Bit 17)                                    */
+ #define R_ENCSS_AFMT_STAT7_AFMT1_EOT_Msk         (0x20000UL)    /*!< AFMT1_EOT (Bitfield-Mask: 0x01)                       */
+ #define R_ENCSS_AFMT_STAT7_AFMT1_TMOUT_Pos       (18UL)         /*!< AFMT1_TMOUT (Bit 18)                                  */
+ #define R_ENCSS_AFMT_STAT7_AFMT1_TMOUT_Msk       (0x40000UL)    /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01)                     */
+/* ======================================================  HDSL0_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL0_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL0_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL0_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL0_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL0_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL0_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL0_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL0_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL0_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL0_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL0_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL0_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL0_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL0_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL0_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL0_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL0_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL1_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL1_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL1_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL1_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL1_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL1_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL1_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL1_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL1_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL1_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL1_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL1_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL1_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL1_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL1_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL1_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL1_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL1_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL2_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL2_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL2_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL2_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL2_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL2_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL2_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL2_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL2_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL2_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL2_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL2_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL2_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL2_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL2_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL2_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL2_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL2_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL3_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL3_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL3_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL3_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL3_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL3_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL3_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL3_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL3_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL3_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL3_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL3_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL3_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL3_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL3_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL3_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL3_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL3_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL4_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL4_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL4_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL4_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL4_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL4_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL4_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL4_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL4_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL4_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL4_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL4_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL4_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL4_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL4_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL4_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL4_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL4_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL5_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL5_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL5_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL5_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL5_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL5_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL5_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL5_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL5_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL5_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL5_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL5_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL5_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL5_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL5_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL5_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL5_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL5_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL6_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL6_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL6_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL6_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL6_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL6_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL6_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL6_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL6_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL6_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL6_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL6_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL6_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL6_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL6_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL6_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL6_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL6_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL7_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL7_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL7_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL7_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL7_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL7_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL7_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL7_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL7_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL7_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL7_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL7_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL7_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL7_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL7_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL7_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL7_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL7_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL8_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL8_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL8_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL8_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL8_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL8_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL8_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL8_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL8_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL8_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL8_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL8_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL8_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL8_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL8_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL8_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL8_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL8_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL9_OS_D  ======================================================= */
+ #define R_ENCSS_HDSL9_OS_D_FREL_Pos              (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL9_OS_D_FREL_Msk              (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_D_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL9_OS_D_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_D_ANS_Pos               (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL9_OS_D_ANS_Msk               (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL9_OS_D_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL9_OS_D_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL9_OS_D_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL9_OS_D_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL9_OS_D_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL9_OS_D_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_D_DTE_Pos               (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL9_OS_D_DTE_Msk               (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL9_OS_D_POS_Pos               (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL9_OS_D_POS_Msk               (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL9_OS_D_SUM_Pos               (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL9_OS_D_SUM_Msk               (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL9_OS_D_INT_Pos               (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL9_OS_D_INT_Msk               (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL10_OS_D  ====================================================== */
+ #define R_ENCSS_HDSL10_OS_D_FREL_Pos             (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL10_OS_D_FREL_Msk             (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_D_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL10_OS_D_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_D_ANS_Pos              (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL10_OS_D_ANS_Msk              (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL10_OS_D_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL10_OS_D_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL10_OS_D_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL10_OS_D_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL10_OS_D_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL10_OS_D_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_D_DTE_Pos              (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL10_OS_D_DTE_Msk              (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL10_OS_D_POS_Pos              (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL10_OS_D_POS_Msk              (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL10_OS_D_SUM_Pos              (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL10_OS_D_SUM_Msk              (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL10_OS_D_INT_Pos              (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL10_OS_D_INT_Msk              (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL11_OS_D  ====================================================== */
+ #define R_ENCSS_HDSL11_OS_D_FREL_Pos             (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL11_OS_D_FREL_Msk             (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_D_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL11_OS_D_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_D_ANS_Pos              (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL11_OS_D_ANS_Msk              (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL11_OS_D_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL11_OS_D_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL11_OS_D_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL11_OS_D_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL11_OS_D_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL11_OS_D_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_D_DTE_Pos              (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL11_OS_D_DTE_Msk              (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL11_OS_D_POS_Pos              (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL11_OS_D_POS_Msk              (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL11_OS_D_SUM_Pos              (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL11_OS_D_SUM_Msk              (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL11_OS_D_INT_Pos              (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL11_OS_D_INT_Msk              (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL12_OS_D  ====================================================== */
+ #define R_ENCSS_HDSL12_OS_D_FREL_Pos             (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL12_OS_D_FREL_Msk             (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_D_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL12_OS_D_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_D_ANS_Pos              (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL12_OS_D_ANS_Msk              (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL12_OS_D_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL12_OS_D_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL12_OS_D_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL12_OS_D_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL12_OS_D_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL12_OS_D_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_D_DTE_Pos              (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL12_OS_D_DTE_Msk              (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL12_OS_D_POS_Pos              (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL12_OS_D_POS_Msk              (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL12_OS_D_SUM_Pos              (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL12_OS_D_SUM_Msk              (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL12_OS_D_INT_Pos              (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL12_OS_D_INT_Msk              (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL13_OS_D  ====================================================== */
+ #define R_ENCSS_HDSL13_OS_D_FREL_Pos             (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL13_OS_D_FREL_Msk             (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_D_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL13_OS_D_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_D_ANS_Pos              (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL13_OS_D_ANS_Msk              (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL13_OS_D_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL13_OS_D_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL13_OS_D_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL13_OS_D_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL13_OS_D_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL13_OS_D_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_D_DTE_Pos              (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL13_OS_D_DTE_Msk              (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL13_OS_D_POS_Pos              (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL13_OS_D_POS_Msk              (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL13_OS_D_SUM_Pos              (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL13_OS_D_SUM_Msk              (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL13_OS_D_INT_Pos              (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL13_OS_D_INT_Msk              (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL14_OS_D  ====================================================== */
+ #define R_ENCSS_HDSL14_OS_D_FREL_Pos             (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL14_OS_D_FREL_Msk             (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_D_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL14_OS_D_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_D_ANS_Pos              (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL14_OS_D_ANS_Msk              (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL14_OS_D_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL14_OS_D_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL14_OS_D_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL14_OS_D_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL14_OS_D_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL14_OS_D_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_D_DTE_Pos              (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL14_OS_D_DTE_Msk              (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL14_OS_D_POS_Pos              (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL14_OS_D_POS_Msk              (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL14_OS_D_SUM_Pos              (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL14_OS_D_SUM_Msk              (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL14_OS_D_INT_Pos              (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL14_OS_D_INT_Msk              (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL15_OS_D  ====================================================== */
+ #define R_ENCSS_HDSL15_OS_D_FREL_Pos             (1UL)          /*!< FREL (Bit 1)                                          */
+ #define R_ENCSS_HDSL15_OS_D_FREL_Msk             (0x2UL)        /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_D_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL15_OS_D_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_D_ANS_Pos              (4UL)          /*!< ANS (Bit 4)                                           */
+ #define R_ENCSS_HDSL15_OS_D_ANS_Msk              (0x10UL)       /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL15_OS_D_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL15_OS_D_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL15_OS_D_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL15_OS_D_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL15_OS_D_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL15_OS_D_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_D_DTE_Pos              (9UL)          /*!< DTE (Bit 9)                                           */
+ #define R_ENCSS_HDSL15_OS_D_DTE_Msk              (0x200UL)      /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL15_OS_D_POS_Pos              (11UL)         /*!< POS (Bit 11)                                          */
+ #define R_ENCSS_HDSL15_OS_D_POS_Msk              (0x800UL)      /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL15_OS_D_SUM_Pos              (14UL)         /*!< SUM (Bit 14)                                          */
+ #define R_ENCSS_HDSL15_OS_D_SUM_Msk              (0x4000UL)     /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL15_OS_D_INT_Pos              (15UL)         /*!< INT (Bit 15)                                          */
+ #define R_ENCSS_HDSL15_OS_D_INT_Msk              (0x8000UL)     /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HDSL0_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL0_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL0_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL0_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL0_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL0_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL0_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL0_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL0_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL0_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL0_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL0_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL0_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL0_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL1_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL1_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL1_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL1_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL1_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL1_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL1_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL1_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL1_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL1_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL1_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL1_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL1_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL1_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL2_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL2_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL2_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL2_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL2_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL2_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL2_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL2_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL2_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL2_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL2_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL2_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL2_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL2_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL3_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL3_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL3_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL3_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL3_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL3_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL3_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL3_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL3_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL3_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL3_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL3_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL3_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL3_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL4_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL4_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL4_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL4_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL4_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL4_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL4_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL4_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL4_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL4_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL4_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL4_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL4_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL4_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL5_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL5_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL5_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL5_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL5_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL5_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL5_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL5_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL5_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL5_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL5_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL5_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL5_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL5_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL6_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL6_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL6_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL6_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL6_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL6_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL6_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL6_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL6_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL6_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL6_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL6_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL6_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL6_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL7_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL7_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL7_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL7_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL7_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL7_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL7_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL7_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL7_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL7_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL7_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL7_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL7_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL7_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL8_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL8_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL8_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL8_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL8_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL8_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL8_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL8_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL8_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL8_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL8_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL8_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL8_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL8_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL9_OS_1  ======================================================= */
+ #define R_ENCSS_HDSL9_OS_1_FRES_Pos              (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL9_OS_1_FRES_Msk              (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_1_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL9_OS_1_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_1_MIN_Pos               (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL9_OS_1_MIN_Msk               (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL9_OS_1_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL9_OS_1_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL9_OS_1_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL9_OS_1_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_1_VPOS_Pos              (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL9_OS_1_VPOS_Msk              (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_1_SCE_Pos               (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL9_OS_1_SCE_Msk               (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL9_OS_1_SSUM_Pos              (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL9_OS_1_SSUM_Msk              (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_1_SINT_Pos              (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL9_OS_1_SINT_Msk              (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL10_OS_1  ====================================================== */
+ #define R_ENCSS_HDSL10_OS_1_FRES_Pos             (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL10_OS_1_FRES_Msk             (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_1_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL10_OS_1_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_1_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL10_OS_1_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL10_OS_1_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL10_OS_1_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL10_OS_1_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL10_OS_1_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_1_VPOS_Pos             (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL10_OS_1_VPOS_Msk             (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_1_SCE_Pos              (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL10_OS_1_SCE_Msk              (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL10_OS_1_SSUM_Pos             (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL10_OS_1_SSUM_Msk             (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_1_SINT_Pos             (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL10_OS_1_SINT_Msk             (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL11_OS_1  ====================================================== */
+ #define R_ENCSS_HDSL11_OS_1_FRES_Pos             (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL11_OS_1_FRES_Msk             (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_1_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL11_OS_1_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_1_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL11_OS_1_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL11_OS_1_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL11_OS_1_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL11_OS_1_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL11_OS_1_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_1_VPOS_Pos             (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL11_OS_1_VPOS_Msk             (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_1_SCE_Pos              (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL11_OS_1_SCE_Msk              (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL11_OS_1_SSUM_Pos             (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL11_OS_1_SSUM_Msk             (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_1_SINT_Pos             (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL11_OS_1_SINT_Msk             (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL12_OS_1  ====================================================== */
+ #define R_ENCSS_HDSL12_OS_1_FRES_Pos             (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL12_OS_1_FRES_Msk             (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_1_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL12_OS_1_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_1_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL12_OS_1_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL12_OS_1_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL12_OS_1_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL12_OS_1_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL12_OS_1_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_1_VPOS_Pos             (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL12_OS_1_VPOS_Msk             (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_1_SCE_Pos              (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL12_OS_1_SCE_Msk              (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL12_OS_1_SSUM_Pos             (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL12_OS_1_SSUM_Msk             (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_1_SINT_Pos             (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL12_OS_1_SINT_Msk             (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL13_OS_1  ====================================================== */
+ #define R_ENCSS_HDSL13_OS_1_FRES_Pos             (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL13_OS_1_FRES_Msk             (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_1_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL13_OS_1_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_1_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL13_OS_1_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL13_OS_1_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL13_OS_1_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL13_OS_1_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL13_OS_1_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_1_VPOS_Pos             (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL13_OS_1_VPOS_Msk             (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_1_SCE_Pos              (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL13_OS_1_SCE_Msk              (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL13_OS_1_SSUM_Pos             (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL13_OS_1_SSUM_Msk             (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_1_SINT_Pos             (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL13_OS_1_SINT_Msk             (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL14_OS_1  ====================================================== */
+ #define R_ENCSS_HDSL14_OS_1_FRES_Pos             (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL14_OS_1_FRES_Msk             (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_1_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL14_OS_1_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_1_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL14_OS_1_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL14_OS_1_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL14_OS_1_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL14_OS_1_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL14_OS_1_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_1_VPOS_Pos             (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL14_OS_1_VPOS_Msk             (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_1_SCE_Pos              (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL14_OS_1_SCE_Msk              (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL14_OS_1_SSUM_Pos             (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL14_OS_1_SSUM_Msk             (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_1_SINT_Pos             (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL14_OS_1_SINT_Msk             (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL15_OS_1  ====================================================== */
+ #define R_ENCSS_HDSL15_OS_1_FRES_Pos             (0UL)          /*!< FRES (Bit 0)                                          */
+ #define R_ENCSS_HDSL15_OS_1_FRES_Msk             (0x1UL)        /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_1_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL15_OS_1_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_1_MIN_Pos              (5UL)          /*!< MIN (Bit 5)                                           */
+ #define R_ENCSS_HDSL15_OS_1_MIN_Msk              (0x20UL)       /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL15_OS_1_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL15_OS_1_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL15_OS_1_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL15_OS_1_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_1_VPOS_Pos             (10UL)         /*!< VPOS (Bit 10)                                         */
+ #define R_ENCSS_HDSL15_OS_1_VPOS_Msk             (0x400UL)      /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_1_SCE_Pos              (13UL)         /*!< SCE (Bit 13)                                          */
+ #define R_ENCSS_HDSL15_OS_1_SCE_Msk              (0x2000UL)     /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_ENCSS_HDSL15_OS_1_SSUM_Pos             (14UL)         /*!< SSUM (Bit 14)                                         */
+ #define R_ENCSS_HDSL15_OS_1_SSUM_Msk             (0x4000UL)     /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_1_SINT_Pos             (15UL)         /*!< SINT (Bit 15)                                         */
+ #define R_ENCSS_HDSL15_OS_1_SINT_Msk             (0x8000UL)     /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ======================================================  HDSL0_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL0_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL0_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL0_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL0_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL0_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL0_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL0_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL0_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL0_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL0_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL1_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL1_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL1_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL1_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL1_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL1_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL1_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL1_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL1_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL1_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL1_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL2_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL2_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL2_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL2_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL2_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL2_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL2_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL2_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL2_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL2_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL2_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL3_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL3_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL3_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL3_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL3_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL3_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL3_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL3_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL3_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL3_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL3_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL4_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL4_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL4_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL4_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL4_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL4_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL4_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL4_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL4_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL4_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL4_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL5_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL5_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL5_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL5_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL5_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL5_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL5_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL5_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL5_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL5_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL5_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL6_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL6_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL6_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL6_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL6_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL6_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL6_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL6_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL6_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL6_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL6_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL7_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL7_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL7_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL7_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL7_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL7_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL7_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL7_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL7_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL7_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL7_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL8_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL8_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL8_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL8_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL8_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL8_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL8_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL8_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL8_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL8_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL8_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL9_OS_2  ======================================================= */
+ #define R_ENCSS_HDSL9_OS_2_QMLW_Pos              (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL9_OS_2_QMLW_Msk              (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_2_POSTX_Pos             (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL9_OS_2_POSTX_Msk             (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL9_OS_2_PRST_Pos              (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL9_OS_2_PRST_Msk              (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_2_VPOS2_Pos             (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL9_OS_2_VPOS2_Msk             (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL9_OS_2_SCE2_Pos              (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL9_OS_2_SCE2_Msk              (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL9_OS_2_SSUM2_Pos             (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL9_OS_2_SSUM2_Msk             (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL10_OS_2  ====================================================== */
+ #define R_ENCSS_HDSL10_OS_2_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL10_OS_2_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_2_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL10_OS_2_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL10_OS_2_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL10_OS_2_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_2_VPOS2_Pos            (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL10_OS_2_VPOS2_Msk            (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL10_OS_2_SCE2_Pos             (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL10_OS_2_SCE2_Msk             (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL10_OS_2_SSUM2_Pos            (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL10_OS_2_SSUM2_Msk            (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL11_OS_2  ====================================================== */
+ #define R_ENCSS_HDSL11_OS_2_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL11_OS_2_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_2_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL11_OS_2_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL11_OS_2_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL11_OS_2_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_2_VPOS2_Pos            (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL11_OS_2_VPOS2_Msk            (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL11_OS_2_SCE2_Pos             (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL11_OS_2_SCE2_Msk             (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL11_OS_2_SSUM2_Pos            (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL11_OS_2_SSUM2_Msk            (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL12_OS_2  ====================================================== */
+ #define R_ENCSS_HDSL12_OS_2_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL12_OS_2_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_2_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL12_OS_2_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL12_OS_2_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL12_OS_2_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_2_VPOS2_Pos            (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL12_OS_2_VPOS2_Msk            (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL12_OS_2_SCE2_Pos             (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL12_OS_2_SCE2_Msk             (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL12_OS_2_SSUM2_Pos            (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL12_OS_2_SSUM2_Msk            (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL13_OS_2  ====================================================== */
+ #define R_ENCSS_HDSL13_OS_2_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL13_OS_2_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_2_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL13_OS_2_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL13_OS_2_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL13_OS_2_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_2_VPOS2_Pos            (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL13_OS_2_VPOS2_Msk            (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL13_OS_2_SCE2_Pos             (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL13_OS_2_SCE2_Msk             (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL13_OS_2_SSUM2_Pos            (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL13_OS_2_SSUM2_Msk            (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL14_OS_2  ====================================================== */
+ #define R_ENCSS_HDSL14_OS_2_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL14_OS_2_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_2_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL14_OS_2_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL14_OS_2_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL14_OS_2_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_2_VPOS2_Pos            (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL14_OS_2_VPOS2_Msk            (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL14_OS_2_SCE2_Pos             (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL14_OS_2_SCE2_Msk             (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL14_OS_2_SSUM2_Pos            (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL14_OS_2_SSUM2_Msk            (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL15_OS_2  ====================================================== */
+ #define R_ENCSS_HDSL15_OS_2_QMLW_Pos             (2UL)          /*!< QMLW (Bit 2)                                          */
+ #define R_ENCSS_HDSL15_OS_2_QMLW_Msk             (0x4UL)        /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_2_POSTX_Pos            (6UL)          /*!< POSTX (Bit 6)                                         */
+ #define R_ENCSS_HDSL15_OS_2_POSTX_Msk            (0xc0UL)       /*!< POSTX (Bitfield-Mask: 0x03)                           */
+ #define R_ENCSS_HDSL15_OS_2_PRST_Pos             (8UL)          /*!< PRST (Bit 8)                                          */
+ #define R_ENCSS_HDSL15_OS_2_PRST_Msk             (0x100UL)      /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_2_VPOS2_Pos            (10UL)         /*!< VPOS2 (Bit 10)                                        */
+ #define R_ENCSS_HDSL15_OS_2_VPOS2_Msk            (0x400UL)      /*!< VPOS2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENCSS_HDSL15_OS_2_SCE2_Pos             (13UL)         /*!< SCE2 (Bit 13)                                         */
+ #define R_ENCSS_HDSL15_OS_2_SCE2_Msk             (0x2000UL)     /*!< SCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_ENCSS_HDSL15_OS_2_SSUM2_Pos            (14UL)         /*!< SSUM2 (Bit 14)                                        */
+ #define R_ENCSS_HDSL15_OS_2_SSUM2_Msk            (0x4000UL)     /*!< SSUM2 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  HDSL_HOSTF0  ====================================================== */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F0_Pos         (0UL)          /*!< HOSTD_F0 (Bit 0)                                      */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F0_Msk         (0x1UL)        /*!< HOSTD_F0 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F0_Pos         (1UL)          /*!< HOST1_F0 (Bit 1)                                      */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F0_Msk         (0x2UL)        /*!< HOST1_F0 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F0_Pos         (2UL)          /*!< HOST2_F0 (Bit 2)                                      */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F0_Msk         (0x4UL)        /*!< HOST2_F0 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F1_Pos         (4UL)          /*!< HOSTD_F1 (Bit 4)                                      */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F1_Msk         (0x10UL)       /*!< HOSTD_F1 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F1_Pos         (5UL)          /*!< HOST1_F1 (Bit 5)                                      */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F1_Msk         (0x20UL)       /*!< HOST1_F1 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F1_Pos         (6UL)          /*!< HOST2_F1 (Bit 6)                                      */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F1_Msk         (0x40UL)       /*!< HOST2_F1 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F2_Pos         (8UL)          /*!< HOSTD_F2 (Bit 8)                                      */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F2_Msk         (0x100UL)      /*!< HOSTD_F2 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F2_Pos         (9UL)          /*!< HOST1_F2 (Bit 9)                                      */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F2_Msk         (0x200UL)      /*!< HOST1_F2 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F2_Pos         (10UL)         /*!< HOST2_F2 (Bit 10)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F2_Msk         (0x400UL)      /*!< HOST2_F2 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F3_Pos         (12UL)         /*!< HOSTD_F3 (Bit 12)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F3_Msk         (0x1000UL)     /*!< HOSTD_F3 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F3_Pos         (13UL)         /*!< HOST1_F3 (Bit 13)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F3_Msk         (0x2000UL)     /*!< HOST1_F3 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F3_Pos         (14UL)         /*!< HOST2_F3 (Bit 14)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F3_Msk         (0x4000UL)     /*!< HOST2_F3 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F4_Pos         (16UL)         /*!< HOSTD_F4 (Bit 16)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F4_Msk         (0x10000UL)    /*!< HOSTD_F4 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F4_Pos         (17UL)         /*!< HOST1_F4 (Bit 17)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F4_Msk         (0x20000UL)    /*!< HOST1_F4 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F4_Pos         (18UL)         /*!< HOST2_F4 (Bit 18)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F4_Msk         (0x40000UL)    /*!< HOST2_F4 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F5_Pos         (20UL)         /*!< HOSTD_F5 (Bit 20)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F5_Msk         (0x100000UL)   /*!< HOSTD_F5 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F5_Pos         (21UL)         /*!< HOST1_F5 (Bit 21)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F5_Msk         (0x200000UL)   /*!< HOST1_F5 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F5_Pos         (22UL)         /*!< HOST2_F5 (Bit 22)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F5_Msk         (0x400000UL)   /*!< HOST2_F5 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F6_Pos         (24UL)         /*!< HOSTD_F6 (Bit 24)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F6_Msk         (0x1000000UL)  /*!< HOSTD_F6 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F6_Pos         (25UL)         /*!< HOST1_F6 (Bit 25)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F6_Msk         (0x2000000UL)  /*!< HOST1_F6 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F6_Pos         (26UL)         /*!< HOST2_F6 (Bit 26)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F6_Msk         (0x4000000UL)  /*!< HOST2_F6 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F7_Pos         (28UL)         /*!< HOSTD_F7 (Bit 28)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOSTD_F7_Msk         (0x10000000UL) /*!< HOSTD_F7 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F7_Pos         (29UL)         /*!< HOST1_F7 (Bit 29)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST1_F7_Msk         (0x20000000UL) /*!< HOST1_F7 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F7_Pos         (30UL)         /*!< HOST2_F7 (Bit 30)                                     */
+ #define R_ENCSS_HDSL_HOSTF0_HOST2_F7_Msk         (0x40000000UL) /*!< HOST2_F7 (Bitfield-Mask: 0x01)                        */
+/* ======================================================  HDSL_HOSTF1  ====================================================== */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F0_Pos         (0UL)          /*!< HOSTD_F0 (Bit 0)                                      */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F0_Msk         (0x1UL)        /*!< HOSTD_F0 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F0_Pos         (1UL)          /*!< HOST1_F0 (Bit 1)                                      */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F0_Msk         (0x2UL)        /*!< HOST1_F0 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F0_Pos         (2UL)          /*!< HOST2_F0 (Bit 2)                                      */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F0_Msk         (0x4UL)        /*!< HOST2_F0 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F1_Pos         (4UL)          /*!< HOSTD_F1 (Bit 4)                                      */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F1_Msk         (0x10UL)       /*!< HOSTD_F1 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F1_Pos         (5UL)          /*!< HOST1_F1 (Bit 5)                                      */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F1_Msk         (0x20UL)       /*!< HOST1_F1 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F1_Pos         (6UL)          /*!< HOST2_F1 (Bit 6)                                      */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F1_Msk         (0x40UL)       /*!< HOST2_F1 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F2_Pos         (8UL)          /*!< HOSTD_F2 (Bit 8)                                      */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F2_Msk         (0x100UL)      /*!< HOSTD_F2 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F2_Pos         (9UL)          /*!< HOST1_F2 (Bit 9)                                      */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F2_Msk         (0x200UL)      /*!< HOST1_F2 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F2_Pos         (10UL)         /*!< HOST2_F2 (Bit 10)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F2_Msk         (0x400UL)      /*!< HOST2_F2 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F3_Pos         (12UL)         /*!< HOSTD_F3 (Bit 12)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F3_Msk         (0x1000UL)     /*!< HOSTD_F3 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F3_Pos         (13UL)         /*!< HOST1_F3 (Bit 13)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F3_Msk         (0x2000UL)     /*!< HOST1_F3 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F3_Pos         (14UL)         /*!< HOST2_F3 (Bit 14)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F3_Msk         (0x4000UL)     /*!< HOST2_F3 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F4_Pos         (16UL)         /*!< HOSTD_F4 (Bit 16)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F4_Msk         (0x10000UL)    /*!< HOSTD_F4 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F4_Pos         (17UL)         /*!< HOST1_F4 (Bit 17)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F4_Msk         (0x20000UL)    /*!< HOST1_F4 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F4_Pos         (18UL)         /*!< HOST2_F4 (Bit 18)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F4_Msk         (0x40000UL)    /*!< HOST2_F4 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F5_Pos         (20UL)         /*!< HOSTD_F5 (Bit 20)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F5_Msk         (0x100000UL)   /*!< HOSTD_F5 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F5_Pos         (21UL)         /*!< HOST1_F5 (Bit 21)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F5_Msk         (0x200000UL)   /*!< HOST1_F5 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F5_Pos         (22UL)         /*!< HOST2_F5 (Bit 22)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F5_Msk         (0x400000UL)   /*!< HOST2_F5 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F6_Pos         (24UL)         /*!< HOSTD_F6 (Bit 24)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F6_Msk         (0x1000000UL)  /*!< HOSTD_F6 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F6_Pos         (25UL)         /*!< HOST1_F6 (Bit 25)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F6_Msk         (0x2000000UL)  /*!< HOST1_F6 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F6_Pos         (26UL)         /*!< HOST2_F6 (Bit 26)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F6_Msk         (0x4000000UL)  /*!< HOST2_F6 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F7_Pos         (28UL)         /*!< HOSTD_F7 (Bit 28)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOSTD_F7_Msk         (0x10000000UL) /*!< HOSTD_F7 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F7_Pos         (29UL)         /*!< HOST1_F7 (Bit 29)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST1_F7_Msk         (0x20000000UL) /*!< HOST1_F7 (Bitfield-Mask: 0x01)                        */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F7_Pos         (30UL)         /*!< HOST2_F7 (Bit 30)                                     */
+ #define R_ENCSS_HDSL_HOSTF1_HOST2_F7_Msk         (0x40000000UL) /*!< HOST2_F7 (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PCIE_SPL0                                        ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  PCIE_INTX  ======================================================= */
+ #define R_PCIE_SPL0_PCIE_INTX_INTX_EP_F0_Pos                (0UL)          /*!< INTX_EP_F0 (Bit 0)                                    */
+ #define R_PCIE_SPL0_PCIE_INTX_INTX_EP_F0_Msk                (0x1UL)        /*!< INTX_EP_F0 (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE_SPL0_PCIE_INTX_INTX_EP_F1_Pos                (1UL)          /*!< INTX_EP_F1 (Bit 1)                                    */
+ #define R_PCIE_SPL0_PCIE_INTX_INTX_EP_F1_Msk                (0x2UL)        /*!< INTX_EP_F1 (Bitfield-Mask: 0x01)                      */
+/* =======================================================  PCIE_MSI1  ======================================================= */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL0_Pos            (0UL)          /*!< UI_EXTMSI_VAL0 (Bit 0)                                */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL0_Msk            (0x1UL)        /*!< UI_EXTMSI_VAL0 (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL1_Pos            (1UL)          /*!< UI_EXTMSI_VAL1 (Bit 1)                                */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL1_Msk            (0x2UL)        /*!< UI_EXTMSI_VAL1 (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL2_Pos            (2UL)          /*!< UI_EXTMSI_VAL2 (Bit 2)                                */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL2_Msk            (0x4UL)        /*!< UI_EXTMSI_VAL2 (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL3_Pos            (3UL)          /*!< UI_EXTMSI_VAL3 (Bit 3)                                */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL3_Msk            (0x8UL)        /*!< UI_EXTMSI_VAL3 (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL4_Pos            (4UL)          /*!< UI_EXTMSI_VAL4 (Bit 4)                                */
+ #define R_PCIE_SPL0_PCIE_MSI1_UI_EXTMSI_VAL4_Msk            (0x10UL)       /*!< UI_EXTMSI_VAL4 (Bitfield-Mask: 0x01)                  */
+/* =======================================================  PCIE_MSI2  ======================================================= */
+ #define R_PCIE_SPL0_PCIE_MSI2_UI_EXTMSI_VEC0_Pos            (0UL)          /*!< UI_EXTMSI_VEC0 (Bit 0)                                */
+ #define R_PCIE_SPL0_PCIE_MSI2_UI_EXTMSI_VEC0_Msk            (0x1fUL)       /*!< UI_EXTMSI_VEC0 (Bitfield-Mask: 0x1f)                  */
+ #define R_PCIE_SPL0_PCIE_MSI2_UI_EXTMSI_VEC1_Pos            (8UL)          /*!< UI_EXTMSI_VEC1 (Bit 8)                                */
+ #define R_PCIE_SPL0_PCIE_MSI2_UI_EXTMSI_VEC1_Msk            (0x1f00UL)     /*!< UI_EXTMSI_VEC1 (Bitfield-Mask: 0x1f)                  */
+ #define R_PCIE_SPL0_PCIE_MSI2_UI_EXTMSI_VEC2_Pos            (16UL)         /*!< UI_EXTMSI_VEC2 (Bit 16)                               */
+ #define R_PCIE_SPL0_PCIE_MSI2_UI_EXTMSI_VEC2_Msk            (0x1f0000UL)   /*!< UI_EXTMSI_VEC2 (Bitfield-Mask: 0x1f)                  */
+ #define R_PCIE_SPL0_PCIE_MSI2_UI_EXTMSI_VEC3_Pos            (24UL)         /*!< UI_EXTMSI_VEC3 (Bit 24)                               */
+ #define R_PCIE_SPL0_PCIE_MSI2_UI_EXTMSI_VEC3_Msk            (0x1f000000UL) /*!< UI_EXTMSI_VEC3 (Bitfield-Mask: 0x1f)                  */
+/* =======================================================  PCIE_MSI3  ======================================================= */
+ #define R_PCIE_SPL0_PCIE_MSI3_UI_EXTMSI_VEC4_Pos            (0UL)          /*!< UI_EXTMSI_VEC4 (Bit 0)                                */
+ #define R_PCIE_SPL0_PCIE_MSI3_UI_EXTMSI_VEC4_Msk            (0x1fUL)       /*!< UI_EXTMSI_VEC4 (Bitfield-Mask: 0x1f)                  */
+/* =======================================================  PCIE_MSI4  ======================================================= */
+ #define R_PCIE_SPL0_PCIE_MSI4_UI_EXTMSI_FUNC0_Pos           (0UL)          /*!< UI_EXTMSI_FUNC0 (Bit 0)                               */
+ #define R_PCIE_SPL0_PCIE_MSI4_UI_EXTMSI_FUNC0_Msk           (0x7UL)        /*!< UI_EXTMSI_FUNC0 (Bitfield-Mask: 0x07)                 */
+ #define R_PCIE_SPL0_PCIE_MSI4_UI_EXTMSI_FUNC1_Pos           (8UL)          /*!< UI_EXTMSI_FUNC1 (Bit 8)                               */
+ #define R_PCIE_SPL0_PCIE_MSI4_UI_EXTMSI_FUNC1_Msk           (0x700UL)      /*!< UI_EXTMSI_FUNC1 (Bitfield-Mask: 0x07)                 */
+ #define R_PCIE_SPL0_PCIE_MSI4_UI_EXTMSI_FUNC2_Pos           (16UL)         /*!< UI_EXTMSI_FUNC2 (Bit 16)                              */
+ #define R_PCIE_SPL0_PCIE_MSI4_UI_EXTMSI_FUNC2_Msk           (0x70000UL)    /*!< UI_EXTMSI_FUNC2 (Bitfield-Mask: 0x07)                 */
+ #define R_PCIE_SPL0_PCIE_MSI4_UI_EXTMSI_FUNC3_Pos           (24UL)         /*!< UI_EXTMSI_FUNC3 (Bit 24)                              */
+ #define R_PCIE_SPL0_PCIE_MSI4_UI_EXTMSI_FUNC3_Msk           (0x7000000UL)  /*!< UI_EXTMSI_FUNC3 (Bitfield-Mask: 0x07)                 */
+/* =======================================================  PCIE_MSI5  ======================================================= */
+ #define R_PCIE_SPL0_PCIE_MSI5_UI_EXTMSI_FUNC4_Pos           (0UL)          /*!< UI_EXTMSI_FUNC4 (Bit 0)                               */
+ #define R_PCIE_SPL0_PCIE_MSI5_UI_EXTMSI_FUNC4_Msk           (0x7UL)        /*!< UI_EXTMSI_FUNC4 (Bitfield-Mask: 0x07)                 */
+/* =======================================================  PCIE_PME  ======================================================== */
+ #define R_PCIE_SPL0_PCIE_PME_PME_TIM_Pos                    (0UL)          /*!< PME_TIM (Bit 0)                                       */
+ #define R_PCIE_SPL0_PCIE_PME_PME_TIM_Msk                    (0x1UL)        /*!< PME_TIM (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE_SPL0_PCIE_PME_CFG_PMCSR_PME_STATUS_F0_Pos    (8UL)          /*!< CFG_PMCSR_PME_STATUS_F0 (Bit 8)                       */
+ #define R_PCIE_SPL0_PCIE_PME_CFG_PMCSR_PME_STATUS_F0_Msk    (0x100UL)      /*!< CFG_PMCSR_PME_STATUS_F0 (Bitfield-Mask: 0x01)         */
+ #define R_PCIE_SPL0_PCIE_PME_CFG_PMCSR_PME_STATUS_F1_Pos    (9UL)          /*!< CFG_PMCSR_PME_STATUS_F1 (Bit 9)                       */
+ #define R_PCIE_SPL0_PCIE_PME_CFG_PMCSR_PME_STATUS_F1_Msk    (0x200UL)      /*!< CFG_PMCSR_PME_STATUS_F1 (Bitfield-Mask: 0x01)         */
+/* =======================================================  PCIE_ACK  ======================================================== */
+ #define R_PCIE_SPL0_PCIE_ACK_TURN_OFF_EVENT_ACK_Pos         (0UL)          /*!< TURN_OFF_EVENT_ACK (Bit 0)                            */
+ #define R_PCIE_SPL0_PCIE_ACK_TURN_OFF_EVENT_ACK_Msk         (0x1UL)        /*!< TURN_OFF_EVENT_ACK (Bitfield-Mask: 0x01)              */
+ #define R_PCIE_SPL0_PCIE_ACK_D3_EVENT_ACK_F0_Pos            (8UL)          /*!< D3_EVENT_ACK_F0 (Bit 8)                               */
+ #define R_PCIE_SPL0_PCIE_ACK_D3_EVENT_ACK_F0_Msk            (0x100UL)      /*!< D3_EVENT_ACK_F0 (Bitfield-Mask: 0x01)                 */
+ #define R_PCIE_SPL0_PCIE_ACK_D3_EVENT_ACK_F1_Pos            (9UL)          /*!< D3_EVENT_ACK_F1 (Bit 9)                               */
+ #define R_PCIE_SPL0_PCIE_ACK_D3_EVENT_ACK_F1_Msk            (0x200UL)      /*!< D3_EVENT_ACK_F1 (Bitfield-Mask: 0x01)                 */
+/* =======================================================  PCIE_MISC  ======================================================= */
+ #define R_PCIE_SPL0_PCIE_MISC_ALLOW_ENTER_L1_Pos            (0UL)          /*!< ALLOW_ENTER_L1 (Bit 0)                                */
+ #define R_PCIE_SPL0_PCIE_MISC_ALLOW_ENTER_L1_Msk            (0x1UL)        /*!< ALLOW_ENTER_L1 (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE_SPL0_PCIE_MISC_FLR_RESET0_Pos                (16UL)         /*!< FLR_RESET0 (Bit 16)                                   */
+ #define R_PCIE_SPL0_PCIE_MISC_FLR_RESET0_Msk                (0x10000UL)    /*!< FLR_RESET0 (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE_SPL0_PCIE_MISC_FLR_RESET1_Pos                (17UL)         /*!< FLR_RESET1 (Bit 17)                                   */
+ #define R_PCIE_SPL0_PCIE_MISC_FLR_RESET1_Msk                (0x20000UL)    /*!< FLR_RESET1 (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE_SPL0_PCIE_MISC_FLR_REQ0_Pos                  (18UL)         /*!< FLR_REQ0 (Bit 18)                                     */
+ #define R_PCIE_SPL0_PCIE_MISC_FLR_REQ0_Msk                  (0x40000UL)    /*!< FLR_REQ0 (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE_SPL0_PCIE_MISC_FLR_REQ1_Pos                  (19UL)         /*!< FLR_REQ1 (Bit 19)                                     */
+ #define R_PCIE_SPL0_PCIE_MISC_FLR_REQ1_Msk                  (0x80000UL)    /*!< FLR_REQ1 (Bitfield-Mask: 0x01)                        */
+/* =======================================================  PCIE_MODE  ======================================================= */
+ #define R_PCIE_SPL0_PCIE_MODE_MODE_PORT_Pos                 (0UL)          /*!< MODE_PORT (Bit 0)                                     */
+ #define R_PCIE_SPL0_PCIE_MODE_MODE_PORT_Msk                 (0x1UL)        /*!< MODE_PORT (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PCIE_LNK                                         ================ */
+/* =========================================================================================================================== */
+
+/* =====================================================  PCIE_LINKMODE  ===================================================== */
+ #define R_PCIE_LNK_PCIE_LINKMODE_LINK_MASTER_Pos    (8UL)     /*!< LINK_MASTER (Bit 8)                                   */
+ #define R_PCIE_LNK_PCIE_LINKMODE_LINK_MASTER_Msk    (0x300UL) /*!< LINK_MASTER (Bitfield-Mask: 0x03)                     */
+
+/* =========================================================================================================================== */
+/* ================                                       R_XSPI0_MISC                                        ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  IOVOLCTL  ======================================================== */
+ #define R_XSPI0_MISC_IOVOLCTL_XSPI_MDV_Pos       (0UL)          /*!< XSPI_MDV (Bit 0)                                      */
+ #define R_XSPI0_MISC_IOVOLCTL_XSPI_MDV_Msk       (0x1UL)        /*!< XSPI_MDV (Bitfield-Mask: 0x01)                        */
+/* =======================================================  CS0ENDAD  ======================================================== */
+ #define R_XSPI0_MISC_CS0ENDAD_CS0_END_ADD_Pos    (0UL)          /*!< CS0_END_ADD (Bit 0)                                   */
+ #define R_XSPI0_MISC_CS0ENDAD_CS0_END_ADD_Msk    (0xffffffffUL) /*!< CS0_END_ADD (Bitfield-Mask: 0xffffffff)               */
+/* =======================================================  CS1STRAD  ======================================================== */
+ #define R_XSPI0_MISC_CS1STRAD_CS1_STR_ADD_Pos    (0UL)          /*!< CS1_STR_ADD (Bit 0)                                   */
+ #define R_XSPI0_MISC_CS1STRAD_CS1_STR_ADD_Msk    (0xffffffffUL) /*!< CS1_STR_ADD (Bitfield-Mask: 0xffffffff)               */
+/* =======================================================  CS1ENDAD  ======================================================== */
+ #define R_XSPI0_MISC_CS1ENDAD_CS1_END_ADD_Pos    (0UL)          /*!< CS1_END_ADD (Bit 0)                                   */
+ #define R_XSPI0_MISC_CS1ENDAD_CS1_END_ADD_Msk    (0xffffffffUL) /*!< CS1_END_ADD (Bitfield-Mask: 0xffffffff)               */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MD_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  MD_MON  ========================================================= */
+ #define R_MD_NS_MD_MON_MDDMON_Pos     (0UL)       /*!< MDDMON (Bit 0)                                        */
+ #define R_MD_NS_MD_MON_MDDMON_Msk     (0x1UL)     /*!< MDDMON (Bitfield-Mask: 0x01)                          */
+ #define R_MD_NS_MD_MON_MDW0MON_Pos    (4UL)       /*!< MDW0MON (Bit 4)                                       */
+ #define R_MD_NS_MD_MON_MDW0MON_Msk    (0x10UL)    /*!< MDW0MON (Bitfield-Mask: 0x01)                         */
+ #define R_MD_NS_MD_MON_MDW1MON_Pos    (5UL)       /*!< MDW1MON (Bit 5)                                       */
+ #define R_MD_NS_MD_MON_MDW1MON_Msk    (0x20UL)    /*!< MDW1MON (Bitfield-Mask: 0x01)                         */
+ #define R_MD_NS_MD_MON_MDP_Pos        (8UL)       /*!< MDP (Bit 8)                                           */
+ #define R_MD_NS_MD_MON_MDP_Msk        (0x100UL)   /*!< MDP (Bitfield-Mask: 0x01)                             */
+ #define R_MD_NS_MD_MON_MD0MON_Pos     (12UL)      /*!< MD0MON (Bit 12)                                       */
+ #define R_MD_NS_MD_MON_MD0MON_Msk     (0x1000UL)  /*!< MD0MON (Bitfield-Mask: 0x01)                          */
+ #define R_MD_NS_MD_MON_MD1MON_Pos     (13UL)      /*!< MD1MON (Bit 13)                                       */
+ #define R_MD_NS_MD_MON_MD1MON_Msk     (0x2000UL)  /*!< MD1MON (Bitfield-Mask: 0x01)                          */
+ #define R_MD_NS_MD_MON_MD2MON_Pos     (14UL)      /*!< MD2MON (Bit 14)                                       */
+ #define R_MD_NS_MD_MON_MD2MON_Msk     (0x4000UL)  /*!< MD2MON (Bitfield-Mask: 0x01)                          */
+ #define R_MD_NS_MD_MON_MDVMON_Pos     (16UL)      /*!< MDVMON (Bit 16)                                       */
+ #define R_MD_NS_MD_MON_MDVMON_Msk     (0x10000UL) /*!< MDVMON (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_RWP_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PRCRN  ========================================================= */
+ #define R_RWP_NS_PRCRN_PRC0_Pos     (0UL)      /*!< PRC0 (Bit 0)                                          */
+ #define R_RWP_NS_PRCRN_PRC0_Msk     (0x1UL)    /*!< PRC0 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_NS_PRCRN_PRC1_Pos     (1UL)      /*!< PRC1 (Bit 1)                                          */
+ #define R_RWP_NS_PRCRN_PRC1_Msk     (0x2UL)    /*!< PRC1 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_NS_PRCRN_PRC2_Pos     (2UL)      /*!< PRC2 (Bit 2)                                          */
+ #define R_RWP_NS_PRCRN_PRC2_Msk     (0x4UL)    /*!< PRC2 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_NS_PRCRN_PRC3_Pos     (3UL)      /*!< PRC3 (Bit 3)                                          */
+ #define R_RWP_NS_PRCRN_PRC3_Msk     (0x8UL)    /*!< PRC3 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_NS_PRCRN_PRKEY_Pos    (8UL)      /*!< PRKEY (Bit 8)                                         */
+ #define R_RWP_NS_PRCRN_PRKEY_Msk    (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ICU_NS                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  NS_SWINT  ======================================================== */
+ #define R_ICU_NS_NS_SWINT_IC0_Pos                  (0UL)          /*!< IC0 (Bit 0)                                           */
+ #define R_ICU_NS_NS_SWINT_IC0_Msk                  (0x1UL)        /*!< IC0 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC1_Pos                  (1UL)          /*!< IC1 (Bit 1)                                           */
+ #define R_ICU_NS_NS_SWINT_IC1_Msk                  (0x2UL)        /*!< IC1 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC2_Pos                  (2UL)          /*!< IC2 (Bit 2)                                           */
+ #define R_ICU_NS_NS_SWINT_IC2_Msk                  (0x4UL)        /*!< IC2 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC3_Pos                  (3UL)          /*!< IC3 (Bit 3)                                           */
+ #define R_ICU_NS_NS_SWINT_IC3_Msk                  (0x8UL)        /*!< IC3 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC4_Pos                  (4UL)          /*!< IC4 (Bit 4)                                           */
+ #define R_ICU_NS_NS_SWINT_IC4_Msk                  (0x10UL)       /*!< IC4 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC5_Pos                  (5UL)          /*!< IC5 (Bit 5)                                           */
+ #define R_ICU_NS_NS_SWINT_IC5_Msk                  (0x20UL)       /*!< IC5 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC6_Pos                  (6UL)          /*!< IC6 (Bit 6)                                           */
+ #define R_ICU_NS_NS_SWINT_IC6_Msk                  (0x40UL)       /*!< IC6 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC7_Pos                  (7UL)          /*!< IC7 (Bit 7)                                           */
+ #define R_ICU_NS_NS_SWINT_IC7_Msk                  (0x80UL)       /*!< IC7 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC8_Pos                  (8UL)          /*!< IC8 (Bit 8)                                           */
+ #define R_ICU_NS_NS_SWINT_IC8_Msk                  (0x100UL)      /*!< IC8 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC9_Pos                  (9UL)          /*!< IC9 (Bit 9)                                           */
+ #define R_ICU_NS_NS_SWINT_IC9_Msk                  (0x200UL)      /*!< IC9 (Bitfield-Mask: 0x01)                             */
+ #define R_ICU_NS_NS_SWINT_IC10_Pos                 (10UL)         /*!< IC10 (Bit 10)                                         */
+ #define R_ICU_NS_NS_SWINT_IC10_Msk                 (0x400UL)      /*!< IC10 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_SWINT_IC11_Pos                 (11UL)         /*!< IC11 (Bit 11)                                         */
+ #define R_ICU_NS_NS_SWINT_IC11_Msk                 (0x800UL)      /*!< IC11 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_SWINT_IC12_Pos                 (12UL)         /*!< IC12 (Bit 12)                                         */
+ #define R_ICU_NS_NS_SWINT_IC12_Msk                 (0x1000UL)     /*!< IC12 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_SWINT_IC13_Pos                 (13UL)         /*!< IC13 (Bit 13)                                         */
+ #define R_ICU_NS_NS_SWINT_IC13_Msk                 (0x2000UL)     /*!< IC13 (Bitfield-Mask: 0x01)                            */
+/* ===================================================  NS_PORTNF_FLTSEL  ==================================================== */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Pos         (0UL)          /*!< FLT0 (Bit 0)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Msk         (0x1UL)        /*!< FLT0 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Pos         (1UL)          /*!< FLT1 (Bit 1)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Msk         (0x2UL)        /*!< FLT1 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Pos         (2UL)          /*!< FLT2 (Bit 2)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Msk         (0x4UL)        /*!< FLT2 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Pos         (3UL)          /*!< FLT3 (Bit 3)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Msk         (0x8UL)        /*!< FLT3 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Pos         (4UL)          /*!< FLT4 (Bit 4)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Msk         (0x10UL)       /*!< FLT4 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Pos         (5UL)          /*!< FLT5 (Bit 5)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Msk         (0x20UL)       /*!< FLT5 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Pos         (6UL)          /*!< FLT6 (Bit 6)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Msk         (0x40UL)       /*!< FLT6 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Pos         (7UL)          /*!< FLT7 (Bit 7)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Msk         (0x80UL)       /*!< FLT7 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Pos         (8UL)          /*!< FLT8 (Bit 8)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Msk         (0x100UL)      /*!< FLT8 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Pos         (9UL)          /*!< FLT9 (Bit 9)                                          */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Msk         (0x200UL)      /*!< FLT9 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Pos        (10UL)         /*!< FLT10 (Bit 10)                                        */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Msk        (0x400UL)      /*!< FLT10 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Pos        (11UL)         /*!< FLT11 (Bit 11)                                        */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Msk        (0x800UL)      /*!< FLT11 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Pos        (12UL)         /*!< FLT12 (Bit 12)                                        */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Msk        (0x1000UL)     /*!< FLT12 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Pos        (13UL)         /*!< FLT13 (Bit 13)                                        */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Msk        (0x2000UL)     /*!< FLT13 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Pos       (14UL)         /*!< FLTDRQ (Bit 14)                                       */
+ #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Msk       (0x4000UL)     /*!< FLTDRQ (Bitfield-Mask: 0x01)                          */
+/* ===================================================  NS_PORTNF_CLKSEL  ==================================================== */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Pos       (0UL)          /*!< CKSEL0 (Bit 0)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Msk       (0x3UL)        /*!< CKSEL0 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Pos       (2UL)          /*!< CKSEL1 (Bit 2)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Msk       (0xcUL)        /*!< CKSEL1 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Pos       (4UL)          /*!< CKSEL2 (Bit 4)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Msk       (0x30UL)       /*!< CKSEL2 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Pos       (6UL)          /*!< CKSEL3 (Bit 6)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Msk       (0xc0UL)       /*!< CKSEL3 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Pos       (8UL)          /*!< CKSEL4 (Bit 8)                                        */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Msk       (0x300UL)      /*!< CKSEL4 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Pos       (10UL)         /*!< CKSEL5 (Bit 10)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Msk       (0xc00UL)      /*!< CKSEL5 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Pos       (12UL)         /*!< CKSEL6 (Bit 12)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Msk       (0x3000UL)     /*!< CKSEL6 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Pos       (14UL)         /*!< CKSEL7 (Bit 14)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Msk       (0xc000UL)     /*!< CKSEL7 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Pos       (16UL)         /*!< CKSEL8 (Bit 16)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Msk       (0x30000UL)    /*!< CKSEL8 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Pos       (18UL)         /*!< CKSEL9 (Bit 18)                                       */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Msk       (0xc0000UL)    /*!< CKSEL9 (Bitfield-Mask: 0x03)                          */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Pos      (20UL)         /*!< CKSEL10 (Bit 20)                                      */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Msk      (0x300000UL)   /*!< CKSEL10 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Pos      (22UL)         /*!< CKSEL11 (Bit 22)                                      */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Msk      (0xc00000UL)   /*!< CKSEL11 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Pos      (24UL)         /*!< CKSEL12 (Bit 24)                                      */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Msk      (0x3000000UL)  /*!< CKSEL12 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Pos      (26UL)         /*!< CKSEL13 (Bit 26)                                      */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Msk      (0xc000000UL)  /*!< CKSEL13 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Pos    (28UL)         /*!< CKSELDREQ (Bit 28)                                    */
+ #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Msk    (0x30000000UL) /*!< CKSELDREQ (Bitfield-Mask: 0x03)                       */
+/* =====================================================  NS_PORTNF_MD  ====================================================== */
+ #define R_ICU_NS_NS_PORTNF_MD_MD0_Pos              (0UL)          /*!< MD0 (Bit 0)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD0_Msk              (0x3UL)        /*!< MD0 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD1_Pos              (2UL)          /*!< MD1 (Bit 2)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD1_Msk              (0xcUL)        /*!< MD1 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD2_Pos              (4UL)          /*!< MD2 (Bit 4)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD2_Msk              (0x30UL)       /*!< MD2 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD3_Pos              (6UL)          /*!< MD3 (Bit 6)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD3_Msk              (0xc0UL)       /*!< MD3 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD4_Pos              (8UL)          /*!< MD4 (Bit 8)                                           */
+ #define R_ICU_NS_NS_PORTNF_MD_MD4_Msk              (0x300UL)      /*!< MD4 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD5_Pos              (10UL)         /*!< MD5 (Bit 10)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD5_Msk              (0xc00UL)      /*!< MD5 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD6_Pos              (12UL)         /*!< MD6 (Bit 12)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD6_Msk              (0x3000UL)     /*!< MD6 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD7_Pos              (14UL)         /*!< MD7 (Bit 14)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD7_Msk              (0xc000UL)     /*!< MD7 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD8_Pos              (16UL)         /*!< MD8 (Bit 16)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD8_Msk              (0x30000UL)    /*!< MD8 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD9_Pos              (18UL)         /*!< MD9 (Bit 18)                                          */
+ #define R_ICU_NS_NS_PORTNF_MD_MD9_Msk              (0xc0000UL)    /*!< MD9 (Bitfield-Mask: 0x03)                             */
+ #define R_ICU_NS_NS_PORTNF_MD_MD10_Pos             (20UL)         /*!< MD10 (Bit 20)                                         */
+ #define R_ICU_NS_NS_PORTNF_MD_MD10_Msk             (0x300000UL)   /*!< MD10 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_NS_NS_PORTNF_MD_MD11_Pos             (22UL)         /*!< MD11 (Bit 22)                                         */
+ #define R_ICU_NS_NS_PORTNF_MD_MD11_Msk             (0xc00000UL)   /*!< MD11 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_NS_NS_PORTNF_MD_MD12_Pos             (24UL)         /*!< MD12 (Bit 24)                                         */
+ #define R_ICU_NS_NS_PORTNF_MD_MD12_Msk             (0x3000000UL)  /*!< MD12 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_NS_NS_PORTNF_MD_MD13_Pos             (26UL)         /*!< MD13 (Bit 26)                                         */
+ #define R_ICU_NS_NS_PORTNF_MD_MD13_Msk             (0xc000000UL)  /*!< MD13 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Pos            (28UL)         /*!< MDDRQ (Bit 28)                                        */
+ #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Msk            (0x30000000UL) /*!< MDDRQ (Bitfield-Mask: 0x03)                           */
+/* =====================================================  CA55ERR_E0MSK  ===================================================== */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK0_Pos          (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK0_Msk          (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK1_Pos          (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK1_Msk          (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK2_Pos          (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK2_Msk          (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK3_Pos          (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK3_Msk          (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK4_Pos          (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK4_Msk          (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK5_Pos          (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK5_Msk          (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK6_Pos          (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK6_Msk          (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK7_Pos          (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK7_Msk          (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK8_Pos          (8UL)          /*!< E0_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK8_Msk          (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK9_Pos          (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK9_Msk          (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK10_Pos         (10UL)         /*!< E0_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK10_Msk         (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK11_Pos         (11UL)         /*!< E0_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK11_Msk         (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK12_Pos         (12UL)         /*!< E0_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CA55ERR_E0MSK_E0_MK12_Msk         (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CA55ERR_E1MSK  ===================================================== */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK0_Pos          (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK0_Msk          (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK1_Pos          (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK1_Msk          (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK2_Pos          (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK2_Msk          (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK3_Pos          (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK3_Msk          (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK4_Pos          (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK4_Msk          (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK5_Pos          (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK5_Msk          (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK6_Pos          (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK6_Msk          (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK7_Pos          (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK7_Msk          (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK8_Pos          (8UL)          /*!< E1_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK8_Msk          (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK9_Pos          (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK9_Msk          (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK10_Pos         (10UL)         /*!< E1_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK10_Msk         (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK11_Pos         (11UL)         /*!< E1_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK11_Msk         (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK12_Pos         (12UL)         /*!< E1_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CA55ERR_E1MSK_E1_MK12_Msk         (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  CA55ERR_RSTMSK  ===================================================== */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK0_Pos         (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK0_Msk         (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK1_Pos         (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK1_Msk         (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK2_Pos         (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK2_Msk         (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK3_Pos         (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK3_Msk         (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK4_Pos         (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK4_Msk         (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK5_Pos         (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK5_Msk         (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK6_Pos         (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK6_Msk         (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK7_Pos         (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK7_Msk         (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK8_Pos         (8UL)          /*!< RS_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK8_Msk         (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK9_Pos         (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK9_Msk         (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK10_Pos        (10UL)         /*!< RS_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK10_Msk        (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK11_Pos        (11UL)         /*!< RS_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK11_Msk        (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK12_Pos        (12UL)         /*!< RS_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CA55ERR_RSTMSK_RS_MK12_Msk        (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  CA55ERR_CLR  ====================================================== */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL0_Pos            (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL0_Msk            (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL1_Pos            (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL1_Msk            (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL2_Pos            (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL2_Msk            (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL3_Pos            (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL3_Msk            (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL4_Pos            (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL4_Msk            (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL5_Pos            (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL5_Msk            (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL6_Pos            (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL6_Msk            (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL7_Pos            (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL7_Msk            (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL8_Pos            (8UL)          /*!< ER_CL8 (Bit 8)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL8_Msk            (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL9_Pos            (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL9_Msk            (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL10_Pos           (10UL)         /*!< ER_CL10 (Bit 10)                                      */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL10_Msk           (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL11_Pos           (11UL)         /*!< ER_CL11 (Bit 11)                                      */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL11_Msk           (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL12_Pos           (12UL)         /*!< ER_CL12 (Bit 12)                                      */
+ #define R_ICU_NS_CA55ERR_CLR_ER_CL12_Msk           (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CA55ERR_STAT  ====================================================== */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST0_Pos           (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST0_Msk           (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST1_Pos           (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST1_Msk           (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST2_Pos           (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST2_Msk           (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST3_Pos           (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST3_Msk           (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST4_Pos           (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST4_Msk           (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST5_Pos           (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST5_Msk           (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST6_Pos           (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST6_Msk           (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST7_Pos           (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST7_Msk           (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST8_Pos           (8UL)          /*!< ER_ST8 (Bit 8)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST8_Msk           (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST9_Pos           (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST9_Msk           (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST10_Pos          (10UL)         /*!< ER_ST10 (Bit 10)                                      */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST10_Msk          (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST11_Pos          (11UL)         /*!< ER_ST11 (Bit 11)                                      */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST11_Msk          (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST12_Pos          (12UL)         /*!< ER_ST12 (Bit 12)                                      */
+ #define R_ICU_NS_CA55ERR_STAT_ER_ST12_Msk          (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  CR520ERR_E0MSK  ===================================================== */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK0_Pos         (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK0_Msk         (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK1_Pos         (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK1_Msk         (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK2_Pos         (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK2_Msk         (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK3_Pos         (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK3_Msk         (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK4_Pos         (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK4_Msk         (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK5_Pos         (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK5_Msk         (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK6_Pos         (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK6_Msk         (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK7_Pos         (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK7_Msk         (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK8_Pos         (8UL)          /*!< E0_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK8_Msk         (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK9_Pos         (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK9_Msk         (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK10_Pos        (10UL)         /*!< E0_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK10_Msk        (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK11_Pos        (11UL)         /*!< E0_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK11_Msk        (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK12_Pos        (12UL)         /*!< E0_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK12_Msk        (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK13_Pos        (13UL)         /*!< E0_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK13_Msk        (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK14_Pos        (14UL)         /*!< E0_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK14_Msk        (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK15_Pos        (15UL)         /*!< E0_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK15_Msk        (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK16_Pos        (16UL)         /*!< E0_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK16_Msk        (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK17_Pos        (17UL)         /*!< E0_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK17_Msk        (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK18_Pos        (18UL)         /*!< E0_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK18_Msk        (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK19_Pos        (19UL)         /*!< E0_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK19_Msk        (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK20_Pos        (20UL)         /*!< E0_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK20_Msk        (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK21_Pos        (21UL)         /*!< E0_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK21_Msk        (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK22_Pos        (22UL)         /*!< E0_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK22_Msk        (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK23_Pos        (23UL)         /*!< E0_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK23_Msk        (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK24_Pos        (24UL)         /*!< E0_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK24_Msk        (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK25_Pos        (25UL)         /*!< E0_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_CR520ERR_E0MSK_E0_MK25_Msk        (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  CR520ERR_E1MSK  ===================================================== */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK0_Pos         (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK0_Msk         (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK1_Pos         (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK1_Msk         (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK2_Pos         (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK2_Msk         (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK3_Pos         (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK3_Msk         (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK4_Pos         (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK4_Msk         (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK5_Pos         (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK5_Msk         (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK6_Pos         (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK6_Msk         (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK7_Pos         (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK7_Msk         (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK8_Pos         (8UL)          /*!< E1_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK8_Msk         (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK9_Pos         (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK9_Msk         (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK10_Pos        (10UL)         /*!< E1_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK10_Msk        (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK11_Pos        (11UL)         /*!< E1_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK11_Msk        (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK12_Pos        (12UL)         /*!< E1_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK12_Msk        (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK13_Pos        (13UL)         /*!< E1_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK13_Msk        (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK14_Pos        (14UL)         /*!< E1_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK14_Msk        (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK15_Pos        (15UL)         /*!< E1_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK15_Msk        (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK16_Pos        (16UL)         /*!< E1_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK16_Msk        (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK17_Pos        (17UL)         /*!< E1_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK17_Msk        (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK18_Pos        (18UL)         /*!< E1_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK18_Msk        (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK19_Pos        (19UL)         /*!< E1_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK19_Msk        (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK20_Pos        (20UL)         /*!< E1_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK20_Msk        (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK21_Pos        (21UL)         /*!< E1_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK21_Msk        (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK22_Pos        (22UL)         /*!< E1_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK22_Msk        (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK23_Pos        (23UL)         /*!< E1_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK23_Msk        (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK24_Pos        (24UL)         /*!< E1_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK24_Msk        (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK25_Pos        (25UL)         /*!< E1_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_CR520ERR_E1MSK_E1_MK25_Msk        (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  CR520ERR_RSTMSK  ==================================================== */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK0_Pos        (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK0_Msk        (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK1_Pos        (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK1_Msk        (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK2_Pos        (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK2_Msk        (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK3_Pos        (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK3_Msk        (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK4_Pos        (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK4_Msk        (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK5_Pos        (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK5_Msk        (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK6_Pos        (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK6_Msk        (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK7_Pos        (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK7_Msk        (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK8_Pos        (8UL)          /*!< RS_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK8_Msk        (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK9_Pos        (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK9_Msk        (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK10_Pos       (10UL)         /*!< RS_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK10_Msk       (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK11_Pos       (11UL)         /*!< RS_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK11_Msk       (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK12_Pos       (12UL)         /*!< RS_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK12_Msk       (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK13_Pos       (13UL)         /*!< RS_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK13_Msk       (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK14_Pos       (14UL)         /*!< RS_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK14_Msk       (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK15_Pos       (15UL)         /*!< RS_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK15_Msk       (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK16_Pos       (16UL)         /*!< RS_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK16_Msk       (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK17_Pos       (17UL)         /*!< RS_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK17_Msk       (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK18_Pos       (18UL)         /*!< RS_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK18_Msk       (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK19_Pos       (19UL)         /*!< RS_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK19_Msk       (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK20_Pos       (20UL)         /*!< RS_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK20_Msk       (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK21_Pos       (21UL)         /*!< RS_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK21_Msk       (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK22_Pos       (22UL)         /*!< RS_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK22_Msk       (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK23_Pos       (23UL)         /*!< RS_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK23_Msk       (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK24_Pos       (24UL)         /*!< RS_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK24_Msk       (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK25_Pos       (25UL)         /*!< RS_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_CR520ERR_RSTMSK_RS_MK25_Msk       (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CR520ERR_CLR  ====================================================== */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL0_Pos           (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL0_Msk           (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL1_Pos           (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL1_Msk           (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL2_Pos           (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL2_Msk           (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL3_Pos           (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL3_Msk           (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL4_Pos           (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL4_Msk           (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL5_Pos           (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL5_Msk           (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL6_Pos           (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL6_Msk           (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL7_Pos           (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL7_Msk           (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL8_Pos           (8UL)          /*!< ER_CL8 (Bit 8)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL8_Msk           (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL9_Pos           (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL9_Msk           (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL10_Pos          (10UL)         /*!< ER_CL10 (Bit 10)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL10_Msk          (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL11_Pos          (11UL)         /*!< ER_CL11 (Bit 11)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL11_Msk          (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL12_Pos          (12UL)         /*!< ER_CL12 (Bit 12)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL12_Msk          (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL13_Pos          (13UL)         /*!< ER_CL13 (Bit 13)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL13_Msk          (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL14_Pos          (14UL)         /*!< ER_CL14 (Bit 14)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL14_Msk          (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL15_Pos          (15UL)         /*!< ER_CL15 (Bit 15)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL15_Msk          (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL16_Pos          (16UL)         /*!< ER_CL16 (Bit 16)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL16_Msk          (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL17_Pos          (17UL)         /*!< ER_CL17 (Bit 17)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL17_Msk          (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL18_Pos          (18UL)         /*!< ER_CL18 (Bit 18)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL18_Msk          (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL19_Pos          (19UL)         /*!< ER_CL19 (Bit 19)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL19_Msk          (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL20_Pos          (20UL)         /*!< ER_CL20 (Bit 20)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL20_Msk          (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL21_Pos          (21UL)         /*!< ER_CL21 (Bit 21)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL21_Msk          (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL22_Pos          (22UL)         /*!< ER_CL22 (Bit 22)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL22_Msk          (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL23_Pos          (23UL)         /*!< ER_CL23 (Bit 23)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL23_Msk          (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL24_Pos          (24UL)         /*!< ER_CL24 (Bit 24)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL24_Msk          (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL25_Pos          (25UL)         /*!< ER_CL25 (Bit 25)                                      */
+ #define R_ICU_NS_CR520ERR_CLR_ER_CL25_Msk          (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CR520ERR_STAT  ===================================================== */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST0_Pos          (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST0_Msk          (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST1_Pos          (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST1_Msk          (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST2_Pos          (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST2_Msk          (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST3_Pos          (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST3_Msk          (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST4_Pos          (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST4_Msk          (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST5_Pos          (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST5_Msk          (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST6_Pos          (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST6_Msk          (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST7_Pos          (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST7_Msk          (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST8_Pos          (8UL)          /*!< ER_ST8 (Bit 8)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST8_Msk          (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST9_Pos          (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST9_Msk          (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST10_Pos         (10UL)         /*!< ER_ST10 (Bit 10)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST10_Msk         (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST11_Pos         (11UL)         /*!< ER_ST11 (Bit 11)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST11_Msk         (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST12_Pos         (12UL)         /*!< ER_ST12 (Bit 12)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST12_Msk         (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST13_Pos         (13UL)         /*!< ER_ST13 (Bit 13)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST13_Msk         (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST14_Pos         (14UL)         /*!< ER_ST14 (Bit 14)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST14_Msk         (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST15_Pos         (15UL)         /*!< ER_ST15 (Bit 15)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST15_Msk         (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST16_Pos         (16UL)         /*!< ER_ST16 (Bit 16)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST16_Msk         (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST17_Pos         (17UL)         /*!< ER_ST17 (Bit 17)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST17_Msk         (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST18_Pos         (18UL)         /*!< ER_ST18 (Bit 18)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST18_Msk         (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST19_Pos         (19UL)         /*!< ER_ST19 (Bit 19)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST19_Msk         (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST20_Pos         (20UL)         /*!< ER_ST20 (Bit 20)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST20_Msk         (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST21_Pos         (21UL)         /*!< ER_ST21 (Bit 21)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST21_Msk         (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST22_Pos         (22UL)         /*!< ER_ST22 (Bit 22)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST22_Msk         (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST23_Pos         (23UL)         /*!< ER_ST23 (Bit 23)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST23_Msk         (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST24_Pos         (24UL)         /*!< ER_ST24 (Bit 24)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST24_Msk         (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST25_Pos         (25UL)         /*!< ER_ST25 (Bit 25)                                      */
+ #define R_ICU_NS_CR520ERR_STAT_ER_ST25_Msk         (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  CR521ERR_E0MSK  ===================================================== */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK0_Pos         (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK0_Msk         (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK1_Pos         (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK1_Msk         (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK2_Pos         (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK2_Msk         (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK3_Pos         (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK3_Msk         (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK4_Pos         (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK4_Msk         (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK5_Pos         (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK5_Msk         (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK6_Pos         (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK6_Msk         (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK7_Pos         (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK7_Msk         (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK8_Pos         (8UL)          /*!< E0_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK8_Msk         (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK9_Pos         (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK9_Msk         (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK10_Pos        (10UL)         /*!< E0_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK10_Msk        (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK11_Pos        (11UL)         /*!< E0_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK11_Msk        (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK12_Pos        (12UL)         /*!< E0_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK12_Msk        (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK13_Pos        (13UL)         /*!< E0_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK13_Msk        (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK14_Pos        (14UL)         /*!< E0_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK14_Msk        (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK15_Pos        (15UL)         /*!< E0_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK15_Msk        (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK16_Pos        (16UL)         /*!< E0_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK16_Msk        (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK17_Pos        (17UL)         /*!< E0_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK17_Msk        (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK18_Pos        (18UL)         /*!< E0_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK18_Msk        (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK19_Pos        (19UL)         /*!< E0_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK19_Msk        (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK20_Pos        (20UL)         /*!< E0_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK20_Msk        (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK21_Pos        (21UL)         /*!< E0_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK21_Msk        (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK22_Pos        (22UL)         /*!< E0_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK22_Msk        (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK23_Pos        (23UL)         /*!< E0_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK23_Msk        (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK24_Pos        (24UL)         /*!< E0_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK24_Msk        (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK25_Pos        (25UL)         /*!< E0_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_CR521ERR_E0MSK_E0_MK25_Msk        (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  CR521ERR_E1MSK  ===================================================== */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK0_Pos         (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK0_Msk         (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK1_Pos         (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK1_Msk         (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK2_Pos         (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK2_Msk         (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK3_Pos         (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK3_Msk         (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK4_Pos         (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK4_Msk         (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK5_Pos         (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK5_Msk         (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK6_Pos         (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK6_Msk         (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK7_Pos         (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK7_Msk         (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK8_Pos         (8UL)          /*!< E1_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK8_Msk         (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK9_Pos         (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK9_Msk         (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK10_Pos        (10UL)         /*!< E1_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK10_Msk        (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK11_Pos        (11UL)         /*!< E1_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK11_Msk        (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK12_Pos        (12UL)         /*!< E1_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK12_Msk        (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK13_Pos        (13UL)         /*!< E1_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK13_Msk        (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK14_Pos        (14UL)         /*!< E1_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK14_Msk        (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK15_Pos        (15UL)         /*!< E1_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK15_Msk        (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK16_Pos        (16UL)         /*!< E1_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK16_Msk        (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK17_Pos        (17UL)         /*!< E1_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK17_Msk        (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK18_Pos        (18UL)         /*!< E1_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK18_Msk        (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK19_Pos        (19UL)         /*!< E1_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK19_Msk        (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK20_Pos        (20UL)         /*!< E1_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK20_Msk        (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK21_Pos        (21UL)         /*!< E1_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK21_Msk        (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK22_Pos        (22UL)         /*!< E1_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK22_Msk        (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK23_Pos        (23UL)         /*!< E1_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK23_Msk        (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK24_Pos        (24UL)         /*!< E1_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK24_Msk        (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK25_Pos        (25UL)         /*!< E1_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_CR521ERR_E1MSK_E1_MK25_Msk        (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  CR521ERR_RSTMSK  ==================================================== */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK0_Pos        (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK0_Msk        (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK1_Pos        (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK1_Msk        (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK2_Pos        (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK2_Msk        (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK3_Pos        (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK3_Msk        (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK4_Pos        (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK4_Msk        (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK5_Pos        (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK5_Msk        (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK6_Pos        (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK6_Msk        (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK7_Pos        (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK7_Msk        (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK8_Pos        (8UL)          /*!< RS_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK8_Msk        (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK9_Pos        (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK9_Msk        (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK10_Pos       (10UL)         /*!< RS_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK10_Msk       (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK11_Pos       (11UL)         /*!< RS_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK11_Msk       (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK12_Pos       (12UL)         /*!< RS_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK12_Msk       (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK13_Pos       (13UL)         /*!< RS_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK13_Msk       (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK14_Pos       (14UL)         /*!< RS_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK14_Msk       (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK15_Pos       (15UL)         /*!< RS_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK15_Msk       (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK16_Pos       (16UL)         /*!< RS_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK16_Msk       (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK17_Pos       (17UL)         /*!< RS_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK17_Msk       (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK18_Pos       (18UL)         /*!< RS_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK18_Msk       (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK19_Pos       (19UL)         /*!< RS_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK19_Msk       (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK20_Pos       (20UL)         /*!< RS_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK20_Msk       (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK21_Pos       (21UL)         /*!< RS_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK21_Msk       (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK22_Pos       (22UL)         /*!< RS_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK22_Msk       (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK23_Pos       (23UL)         /*!< RS_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK23_Msk       (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK24_Pos       (24UL)         /*!< RS_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK24_Msk       (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK25_Pos       (25UL)         /*!< RS_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_CR521ERR_RSTMSK_RS_MK25_Msk       (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CR521ERR_CLR  ====================================================== */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL0_Pos           (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL0_Msk           (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL1_Pos           (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL1_Msk           (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL2_Pos           (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL2_Msk           (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL3_Pos           (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL3_Msk           (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL4_Pos           (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL4_Msk           (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL5_Pos           (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL5_Msk           (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL6_Pos           (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL6_Msk           (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL7_Pos           (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL7_Msk           (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL8_Pos           (8UL)          /*!< ER_CL8 (Bit 8)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL8_Msk           (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL9_Pos           (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL9_Msk           (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL10_Pos          (10UL)         /*!< ER_CL10 (Bit 10)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL10_Msk          (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL11_Pos          (11UL)         /*!< ER_CL11 (Bit 11)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL11_Msk          (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL12_Pos          (12UL)         /*!< ER_CL12 (Bit 12)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL12_Msk          (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL13_Pos          (13UL)         /*!< ER_CL13 (Bit 13)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL13_Msk          (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL14_Pos          (14UL)         /*!< ER_CL14 (Bit 14)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL14_Msk          (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL15_Pos          (15UL)         /*!< ER_CL15 (Bit 15)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL15_Msk          (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL16_Pos          (16UL)         /*!< ER_CL16 (Bit 16)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL16_Msk          (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL17_Pos          (17UL)         /*!< ER_CL17 (Bit 17)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL17_Msk          (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL18_Pos          (18UL)         /*!< ER_CL18 (Bit 18)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL18_Msk          (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL19_Pos          (19UL)         /*!< ER_CL19 (Bit 19)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL19_Msk          (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL20_Pos          (20UL)         /*!< ER_CL20 (Bit 20)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL20_Msk          (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL21_Pos          (21UL)         /*!< ER_CL21 (Bit 21)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL21_Msk          (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL22_Pos          (22UL)         /*!< ER_CL22 (Bit 22)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL22_Msk          (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL23_Pos          (23UL)         /*!< ER_CL23 (Bit 23)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL23_Msk          (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL24_Pos          (24UL)         /*!< ER_CL24 (Bit 24)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL24_Msk          (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL25_Pos          (25UL)         /*!< ER_CL25 (Bit 25)                                      */
+ #define R_ICU_NS_CR521ERR_CLR_ER_CL25_Msk          (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  CR521ERR_STAT  ===================================================== */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST0_Pos          (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST0_Msk          (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST1_Pos          (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST1_Msk          (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST2_Pos          (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST2_Msk          (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST3_Pos          (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST3_Msk          (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST4_Pos          (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST4_Msk          (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST5_Pos          (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST5_Msk          (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST6_Pos          (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST6_Msk          (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST7_Pos          (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST7_Msk          (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST8_Pos          (8UL)          /*!< ER_ST8 (Bit 8)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST8_Msk          (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST9_Pos          (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST9_Msk          (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST10_Pos         (10UL)         /*!< ER_ST10 (Bit 10)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST10_Msk         (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST11_Pos         (11UL)         /*!< ER_ST11 (Bit 11)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST11_Msk         (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST12_Pos         (12UL)         /*!< ER_ST12 (Bit 12)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST12_Msk         (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST13_Pos         (13UL)         /*!< ER_ST13 (Bit 13)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST13_Msk         (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST14_Pos         (14UL)         /*!< ER_ST14 (Bit 14)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST14_Msk         (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST15_Pos         (15UL)         /*!< ER_ST15 (Bit 15)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST15_Msk         (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST16_Pos         (16UL)         /*!< ER_ST16 (Bit 16)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST16_Msk         (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST17_Pos         (17UL)         /*!< ER_ST17 (Bit 17)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST17_Msk         (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST18_Pos         (18UL)         /*!< ER_ST18 (Bit 18)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST18_Msk         (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST19_Pos         (19UL)         /*!< ER_ST19 (Bit 19)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST19_Msk         (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST20_Pos         (20UL)         /*!< ER_ST20 (Bit 20)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST20_Msk         (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST21_Pos         (21UL)         /*!< ER_ST21 (Bit 21)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST21_Msk         (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST22_Pos         (22UL)         /*!< ER_ST22 (Bit 22)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST22_Msk         (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST23_Pos         (23UL)         /*!< ER_ST23 (Bit 23)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST23_Msk         (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST24_Pos         (24UL)         /*!< ER_ST24 (Bit 24)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST24_Msk         (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST25_Pos         (25UL)         /*!< ER_ST25 (Bit 25)                                      */
+ #define R_ICU_NS_CR521ERR_STAT_ER_ST25_Msk         (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  PERIERR_E0MSK  ===================================================== */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK0_Pos          (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK0_Msk          (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK1_Pos          (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK1_Msk          (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK2_Pos          (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK2_Msk          (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK3_Pos          (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK3_Msk          (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK4_Pos          (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK4_Msk          (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK5_Pos          (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK5_Msk          (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK6_Pos          (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK6_Msk          (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK7_Pos          (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK7_Msk          (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK8_Pos          (8UL)          /*!< E0_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK8_Msk          (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK9_Pos          (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK9_Msk          (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK10_Pos         (10UL)         /*!< E0_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK10_Msk         (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK11_Pos         (11UL)         /*!< E0_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK11_Msk         (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK12_Pos         (12UL)         /*!< E0_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK12_Msk         (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK13_Pos         (13UL)         /*!< E0_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK13_Msk         (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK14_Pos         (14UL)         /*!< E0_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK14_Msk         (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK15_Pos         (15UL)         /*!< E0_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK15_Msk         (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK16_Pos         (16UL)         /*!< E0_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK16_Msk         (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK17_Pos         (17UL)         /*!< E0_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK17_Msk         (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK18_Pos         (18UL)         /*!< E0_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK18_Msk         (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK19_Pos         (19UL)         /*!< E0_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK19_Msk         (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK20_Pos         (20UL)         /*!< E0_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK20_Msk         (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK21_Pos         (21UL)         /*!< E0_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK21_Msk         (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK22_Pos         (22UL)         /*!< E0_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK22_Msk         (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK23_Pos         (23UL)         /*!< E0_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK23_Msk         (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK24_Pos         (24UL)         /*!< E0_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK24_Msk         (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK25_Pos         (25UL)         /*!< E0_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK25_Msk         (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK26_Pos         (26UL)         /*!< E0_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK26_Msk         (0x4000000UL)  /*!< E0_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK27_Pos         (27UL)         /*!< E0_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK27_Msk         (0x8000000UL)  /*!< E0_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK28_Pos         (28UL)         /*!< E0_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK28_Msk         (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK29_Pos         (29UL)         /*!< E0_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK29_Msk         (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK30_Pos         (30UL)         /*!< E0_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK30_Msk         (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK31_Pos         (31UL)         /*!< E0_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_PERIERR_E0MSK_E0_MK31_Msk         (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  PERIERR_E1MSK  ===================================================== */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK0_Pos          (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK0_Msk          (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK1_Pos          (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK1_Msk          (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK2_Pos          (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK2_Msk          (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK3_Pos          (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK3_Msk          (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK4_Pos          (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK4_Msk          (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK5_Pos          (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK5_Msk          (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK6_Pos          (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK6_Msk          (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK7_Pos          (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK7_Msk          (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK8_Pos          (8UL)          /*!< E1_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK8_Msk          (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK9_Pos          (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK9_Msk          (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK10_Pos         (10UL)         /*!< E1_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK10_Msk         (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK11_Pos         (11UL)         /*!< E1_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK11_Msk         (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK12_Pos         (12UL)         /*!< E1_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK12_Msk         (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK13_Pos         (13UL)         /*!< E1_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK13_Msk         (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK14_Pos         (14UL)         /*!< E1_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK14_Msk         (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK15_Pos         (15UL)         /*!< E1_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK15_Msk         (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK16_Pos         (16UL)         /*!< E1_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK16_Msk         (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK17_Pos         (17UL)         /*!< E1_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK17_Msk         (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK18_Pos         (18UL)         /*!< E1_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK18_Msk         (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK19_Pos         (19UL)         /*!< E1_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK19_Msk         (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK20_Pos         (20UL)         /*!< E1_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK20_Msk         (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK21_Pos         (21UL)         /*!< E1_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK21_Msk         (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK22_Pos         (22UL)         /*!< E1_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK22_Msk         (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK23_Pos         (23UL)         /*!< E1_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK23_Msk         (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK24_Pos         (24UL)         /*!< E1_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK24_Msk         (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK25_Pos         (25UL)         /*!< E1_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK25_Msk         (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK26_Pos         (26UL)         /*!< E1_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK26_Msk         (0x4000000UL)  /*!< E1_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK27_Pos         (27UL)         /*!< E1_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK27_Msk         (0x8000000UL)  /*!< E1_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK28_Pos         (28UL)         /*!< E1_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK28_Msk         (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK29_Pos         (29UL)         /*!< E1_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK29_Msk         (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK30_Pos         (30UL)         /*!< E1_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK30_Msk         (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK31_Pos         (31UL)         /*!< E1_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_PERIERR_E1MSK_E1_MK31_Msk         (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PERIERR_RSTMSK  ===================================================== */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK0_Pos         (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK0_Msk         (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK1_Pos         (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK1_Msk         (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK2_Pos         (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK2_Msk         (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK3_Pos         (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK3_Msk         (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK4_Pos         (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK4_Msk         (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK5_Pos         (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK5_Msk         (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK6_Pos         (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK6_Msk         (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK7_Pos         (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK7_Msk         (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK8_Pos         (8UL)          /*!< RS_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK8_Msk         (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK9_Pos         (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK9_Msk         (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK10_Pos        (10UL)         /*!< RS_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK10_Msk        (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK11_Pos        (11UL)         /*!< RS_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK11_Msk        (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK12_Pos        (12UL)         /*!< RS_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK12_Msk        (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK13_Pos        (13UL)         /*!< RS_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK13_Msk        (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK14_Pos        (14UL)         /*!< RS_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK14_Msk        (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK15_Pos        (15UL)         /*!< RS_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK15_Msk        (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK16_Pos        (16UL)         /*!< RS_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK16_Msk        (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK17_Pos        (17UL)         /*!< RS_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK17_Msk        (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK18_Pos        (18UL)         /*!< RS_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK18_Msk        (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK19_Pos        (19UL)         /*!< RS_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK19_Msk        (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK20_Pos        (20UL)         /*!< RS_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK20_Msk        (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK21_Pos        (21UL)         /*!< RS_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK21_Msk        (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK22_Pos        (22UL)         /*!< RS_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK22_Msk        (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK23_Pos        (23UL)         /*!< RS_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK23_Msk        (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK24_Pos        (24UL)         /*!< RS_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK24_Msk        (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK25_Pos        (25UL)         /*!< RS_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK25_Msk        (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK26_Pos        (26UL)         /*!< RS_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK26_Msk        (0x4000000UL)  /*!< RS_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK27_Pos        (27UL)         /*!< RS_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK27_Msk        (0x8000000UL)  /*!< RS_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK28_Pos        (28UL)         /*!< RS_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK28_Msk        (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK29_Pos        (29UL)         /*!< RS_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK29_Msk        (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK30_Pos        (30UL)         /*!< RS_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK30_Msk        (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK31_Pos        (31UL)         /*!< RS_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_PERIERR_RSTMSK_RS_MK31_Msk        (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  PERIERR_CLR  ====================================================== */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL0_Pos            (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL0_Msk            (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL1_Pos            (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL1_Msk            (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL2_Pos            (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL2_Msk            (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL3_Pos            (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL3_Msk            (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL4_Pos            (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL4_Msk            (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL5_Pos            (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL5_Msk            (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL6_Pos            (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL6_Msk            (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL7_Pos            (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL7_Msk            (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL8_Pos            (8UL)          /*!< ER_CL8 (Bit 8)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL8_Msk            (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL9_Pos            (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL9_Msk            (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL10_Pos           (10UL)         /*!< ER_CL10 (Bit 10)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL10_Msk           (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL11_Pos           (11UL)         /*!< ER_CL11 (Bit 11)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL11_Msk           (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL12_Pos           (12UL)         /*!< ER_CL12 (Bit 12)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL12_Msk           (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL13_Pos           (13UL)         /*!< ER_CL13 (Bit 13)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL13_Msk           (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL14_Pos           (14UL)         /*!< ER_CL14 (Bit 14)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL14_Msk           (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL15_Pos           (15UL)         /*!< ER_CL15 (Bit 15)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL15_Msk           (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL16_Pos           (16UL)         /*!< ER_CL16 (Bit 16)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL16_Msk           (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL17_Pos           (17UL)         /*!< ER_CL17 (Bit 17)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL17_Msk           (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL18_Pos           (18UL)         /*!< ER_CL18 (Bit 18)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL18_Msk           (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL19_Pos           (19UL)         /*!< ER_CL19 (Bit 19)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL19_Msk           (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL20_Pos           (20UL)         /*!< ER_CL20 (Bit 20)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL20_Msk           (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL21_Pos           (21UL)         /*!< ER_CL21 (Bit 21)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL21_Msk           (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL22_Pos           (22UL)         /*!< ER_CL22 (Bit 22)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL22_Msk           (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL23_Pos           (23UL)         /*!< ER_CL23 (Bit 23)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL23_Msk           (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL24_Pos           (24UL)         /*!< ER_CL24 (Bit 24)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL24_Msk           (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL25_Pos           (25UL)         /*!< ER_CL25 (Bit 25)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL25_Msk           (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL26_Pos           (26UL)         /*!< ER_CL26 (Bit 26)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL26_Msk           (0x4000000UL)  /*!< ER_CL26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL27_Pos           (27UL)         /*!< ER_CL27 (Bit 27)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL27_Msk           (0x8000000UL)  /*!< ER_CL27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL28_Pos           (28UL)         /*!< ER_CL28 (Bit 28)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL28_Msk           (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL29_Pos           (29UL)         /*!< ER_CL29 (Bit 29)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL29_Msk           (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL30_Pos           (30UL)         /*!< ER_CL30 (Bit 30)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL30_Msk           (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL31_Pos           (31UL)         /*!< ER_CL31 (Bit 31)                                      */
+ #define R_ICU_NS_PERIERR_CLR_ER_CL31_Msk           (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  PERIERR_STAT  ====================================================== */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST0_Pos           (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST0_Msk           (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST1_Pos           (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST1_Msk           (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST2_Pos           (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST2_Msk           (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST3_Pos           (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST3_Msk           (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST4_Pos           (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST4_Msk           (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST5_Pos           (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST5_Msk           (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST6_Pos           (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST6_Msk           (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST7_Pos           (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST7_Msk           (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST8_Pos           (8UL)          /*!< ER_ST8 (Bit 8)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST8_Msk           (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST9_Pos           (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST9_Msk           (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST10_Pos          (10UL)         /*!< ER_ST10 (Bit 10)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST10_Msk          (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST11_Pos          (11UL)         /*!< ER_ST11 (Bit 11)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST11_Msk          (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST12_Pos          (12UL)         /*!< ER_ST12 (Bit 12)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST12_Msk          (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST13_Pos          (13UL)         /*!< ER_ST13 (Bit 13)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST13_Msk          (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST14_Pos          (14UL)         /*!< ER_ST14 (Bit 14)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST14_Msk          (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST15_Pos          (15UL)         /*!< ER_ST15 (Bit 15)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST15_Msk          (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST16_Pos          (16UL)         /*!< ER_ST16 (Bit 16)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST16_Msk          (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST17_Pos          (17UL)         /*!< ER_ST17 (Bit 17)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST17_Msk          (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST18_Pos          (18UL)         /*!< ER_ST18 (Bit 18)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST18_Msk          (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST19_Pos          (19UL)         /*!< ER_ST19 (Bit 19)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST19_Msk          (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST20_Pos          (20UL)         /*!< ER_ST20 (Bit 20)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST20_Msk          (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST21_Pos          (21UL)         /*!< ER_ST21 (Bit 21)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST21_Msk          (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST22_Pos          (22UL)         /*!< ER_ST22 (Bit 22)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST22_Msk          (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST23_Pos          (23UL)         /*!< ER_ST23 (Bit 23)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST23_Msk          (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST24_Pos          (24UL)         /*!< ER_ST24 (Bit 24)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST24_Msk          (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST25_Pos          (25UL)         /*!< ER_ST25 (Bit 25)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST25_Msk          (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST26_Pos          (26UL)         /*!< ER_ST26 (Bit 26)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST26_Msk          (0x4000000UL)  /*!< ER_ST26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST27_Pos          (27UL)         /*!< ER_ST27 (Bit 27)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST27_Msk          (0x8000000UL)  /*!< ER_ST27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST28_Pos          (28UL)         /*!< ER_ST28 (Bit 28)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST28_Msk          (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST29_Pos          (29UL)         /*!< ER_ST29 (Bit 29)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST29_Msk          (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST30_Pos          (30UL)         /*!< ER_ST30 (Bit 30)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST30_Msk          (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST31_Pos          (31UL)         /*!< ER_ST31 (Bit 31)                                      */
+ #define R_ICU_NS_PERIERR_STAT_ER_ST31_Msk          (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  DSMIFERR_E0MSK  ===================================================== */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK0_Pos         (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK0_Msk         (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK1_Pos         (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK1_Msk         (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK2_Pos         (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK2_Msk         (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK3_Pos         (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK3_Msk         (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK4_Pos         (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK4_Msk         (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK5_Pos         (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK5_Msk         (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK6_Pos         (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK6_Msk         (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK7_Pos         (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK7_Msk         (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK8_Pos         (8UL)          /*!< E0_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK8_Msk         (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK9_Pos         (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK9_Msk         (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK10_Pos        (10UL)         /*!< E0_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK10_Msk        (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK11_Pos        (11UL)         /*!< E0_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK11_Msk        (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK12_Pos        (12UL)         /*!< E0_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK12_Msk        (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK13_Pos        (13UL)         /*!< E0_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK13_Msk        (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK14_Pos        (14UL)         /*!< E0_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK14_Msk        (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK15_Pos        (15UL)         /*!< E0_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK15_Msk        (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK16_Pos        (16UL)         /*!< E0_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK16_Msk        (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK17_Pos        (17UL)         /*!< E0_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK17_Msk        (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK18_Pos        (18UL)         /*!< E0_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK18_Msk        (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK19_Pos        (19UL)         /*!< E0_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK19_Msk        (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK20_Pos        (20UL)         /*!< E0_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK20_Msk        (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK21_Pos        (21UL)         /*!< E0_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK21_Msk        (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK22_Pos        (22UL)         /*!< E0_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK22_Msk        (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK23_Pos        (23UL)         /*!< E0_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK23_Msk        (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK24_Pos        (24UL)         /*!< E0_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK24_Msk        (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK25_Pos        (25UL)         /*!< E0_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK25_Msk        (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK26_Pos        (26UL)         /*!< E0_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK26_Msk        (0x4000000UL)  /*!< E0_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK27_Pos        (27UL)         /*!< E0_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK27_Msk        (0x8000000UL)  /*!< E0_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK28_Pos        (28UL)         /*!< E0_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK28_Msk        (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK29_Pos        (29UL)         /*!< E0_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK29_Msk        (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK30_Pos        (30UL)         /*!< E0_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK30_Msk        (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK31_Pos        (31UL)         /*!< E0_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_DSMIFERR_E0MSK_E0_MK31_Msk        (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  DSMIFERR_E1MSK  ===================================================== */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK0_Pos         (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK0_Msk         (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK1_Pos         (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK1_Msk         (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK2_Pos         (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK2_Msk         (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK3_Pos         (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK3_Msk         (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK4_Pos         (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK4_Msk         (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK5_Pos         (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK5_Msk         (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK6_Pos         (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK6_Msk         (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK7_Pos         (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK7_Msk         (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK8_Pos         (8UL)          /*!< E1_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK8_Msk         (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK9_Pos         (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK9_Msk         (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK10_Pos        (10UL)         /*!< E1_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK10_Msk        (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK11_Pos        (11UL)         /*!< E1_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK11_Msk        (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK12_Pos        (12UL)         /*!< E1_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK12_Msk        (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK13_Pos        (13UL)         /*!< E1_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK13_Msk        (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK14_Pos        (14UL)         /*!< E1_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK14_Msk        (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK15_Pos        (15UL)         /*!< E1_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK15_Msk        (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK16_Pos        (16UL)         /*!< E1_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK16_Msk        (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK17_Pos        (17UL)         /*!< E1_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK17_Msk        (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK18_Pos        (18UL)         /*!< E1_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK18_Msk        (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK19_Pos        (19UL)         /*!< E1_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK19_Msk        (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK20_Pos        (20UL)         /*!< E1_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK20_Msk        (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK21_Pos        (21UL)         /*!< E1_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK21_Msk        (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK22_Pos        (22UL)         /*!< E1_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK22_Msk        (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK23_Pos        (23UL)         /*!< E1_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK23_Msk        (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK24_Pos        (24UL)         /*!< E1_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK24_Msk        (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK25_Pos        (25UL)         /*!< E1_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK25_Msk        (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK26_Pos        (26UL)         /*!< E1_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK26_Msk        (0x4000000UL)  /*!< E1_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK27_Pos        (27UL)         /*!< E1_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK27_Msk        (0x8000000UL)  /*!< E1_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK28_Pos        (28UL)         /*!< E1_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK28_Msk        (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK29_Pos        (29UL)         /*!< E1_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK29_Msk        (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK30_Pos        (30UL)         /*!< E1_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK30_Msk        (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK31_Pos        (31UL)         /*!< E1_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_DSMIFERR_E1MSK_E1_MK31_Msk        (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  DSMIFERR_RSTMSK  ==================================================== */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK0_Pos        (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK0_Msk        (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK1_Pos        (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK1_Msk        (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK2_Pos        (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK2_Msk        (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK3_Pos        (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK3_Msk        (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK4_Pos        (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK4_Msk        (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK5_Pos        (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK5_Msk        (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK6_Pos        (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK6_Msk        (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK7_Pos        (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK7_Msk        (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK8_Pos        (8UL)          /*!< RS_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK8_Msk        (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK9_Pos        (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK9_Msk        (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK10_Pos       (10UL)         /*!< RS_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK10_Msk       (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK11_Pos       (11UL)         /*!< RS_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK11_Msk       (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK12_Pos       (12UL)         /*!< RS_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK12_Msk       (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK13_Pos       (13UL)         /*!< RS_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK13_Msk       (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK14_Pos       (14UL)         /*!< RS_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK14_Msk       (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK15_Pos       (15UL)         /*!< RS_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK15_Msk       (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK16_Pos       (16UL)         /*!< RS_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK16_Msk       (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK17_Pos       (17UL)         /*!< RS_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK17_Msk       (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK18_Pos       (18UL)         /*!< RS_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK18_Msk       (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK19_Pos       (19UL)         /*!< RS_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK19_Msk       (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK20_Pos       (20UL)         /*!< RS_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK20_Msk       (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK21_Pos       (21UL)         /*!< RS_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK21_Msk       (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK22_Pos       (22UL)         /*!< RS_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK22_Msk       (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK23_Pos       (23UL)         /*!< RS_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK23_Msk       (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK24_Pos       (24UL)         /*!< RS_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK24_Msk       (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK25_Pos       (25UL)         /*!< RS_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK25_Msk       (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK26_Pos       (26UL)         /*!< RS_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK26_Msk       (0x4000000UL)  /*!< RS_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK27_Pos       (27UL)         /*!< RS_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK27_Msk       (0x8000000UL)  /*!< RS_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK28_Pos       (28UL)         /*!< RS_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK28_Msk       (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK29_Pos       (29UL)         /*!< RS_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK29_Msk       (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK30_Pos       (30UL)         /*!< RS_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK30_Msk       (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK31_Pos       (31UL)         /*!< RS_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_DSMIFERR_RSTMSK_RS_MK31_Msk       (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  DSMIFERR_CLR  ====================================================== */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL0_Pos           (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL0_Msk           (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL1_Pos           (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL1_Msk           (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL2_Pos           (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL2_Msk           (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL3_Pos           (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL3_Msk           (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL4_Pos           (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL4_Msk           (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL5_Pos           (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL5_Msk           (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL6_Pos           (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL6_Msk           (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL7_Pos           (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL7_Msk           (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL8_Pos           (8UL)          /*!< ER_CL8 (Bit 8)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL8_Msk           (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL9_Pos           (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL9_Msk           (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL10_Pos          (10UL)         /*!< ER_CL10 (Bit 10)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL10_Msk          (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL11_Pos          (11UL)         /*!< ER_CL11 (Bit 11)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL11_Msk          (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL12_Pos          (12UL)         /*!< ER_CL12 (Bit 12)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL12_Msk          (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL13_Pos          (13UL)         /*!< ER_CL13 (Bit 13)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL13_Msk          (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL14_Pos          (14UL)         /*!< ER_CL14 (Bit 14)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL14_Msk          (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL15_Pos          (15UL)         /*!< ER_CL15 (Bit 15)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL15_Msk          (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL16_Pos          (16UL)         /*!< ER_CL16 (Bit 16)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL16_Msk          (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL17_Pos          (17UL)         /*!< ER_CL17 (Bit 17)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL17_Msk          (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL18_Pos          (18UL)         /*!< ER_CL18 (Bit 18)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL18_Msk          (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL19_Pos          (19UL)         /*!< ER_CL19 (Bit 19)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL19_Msk          (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL20_Pos          (20UL)         /*!< ER_CL20 (Bit 20)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL20_Msk          (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL21_Pos          (21UL)         /*!< ER_CL21 (Bit 21)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL21_Msk          (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL22_Pos          (22UL)         /*!< ER_CL22 (Bit 22)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL22_Msk          (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL23_Pos          (23UL)         /*!< ER_CL23 (Bit 23)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL23_Msk          (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL24_Pos          (24UL)         /*!< ER_CL24 (Bit 24)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL24_Msk          (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL25_Pos          (25UL)         /*!< ER_CL25 (Bit 25)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL25_Msk          (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL26_Pos          (26UL)         /*!< ER_CL26 (Bit 26)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL26_Msk          (0x4000000UL)  /*!< ER_CL26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL27_Pos          (27UL)         /*!< ER_CL27 (Bit 27)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL27_Msk          (0x8000000UL)  /*!< ER_CL27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL28_Pos          (28UL)         /*!< ER_CL28 (Bit 28)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL28_Msk          (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL29_Pos          (29UL)         /*!< ER_CL29 (Bit 29)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL29_Msk          (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL30_Pos          (30UL)         /*!< ER_CL30 (Bit 30)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL30_Msk          (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL31_Pos          (31UL)         /*!< ER_CL31 (Bit 31)                                      */
+ #define R_ICU_NS_DSMIFERR_CLR_ER_CL31_Msk          (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  DSMIFERR_STAT  ===================================================== */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST0_Pos          (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST0_Msk          (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST1_Pos          (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST1_Msk          (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST2_Pos          (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST2_Msk          (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST3_Pos          (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST3_Msk          (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST4_Pos          (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST4_Msk          (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST5_Pos          (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST5_Msk          (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST6_Pos          (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST6_Msk          (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST7_Pos          (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST7_Msk          (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST8_Pos          (8UL)          /*!< ER_ST8 (Bit 8)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST8_Msk          (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST9_Pos          (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST9_Msk          (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST10_Pos         (10UL)         /*!< ER_ST10 (Bit 10)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST10_Msk         (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST11_Pos         (11UL)         /*!< ER_ST11 (Bit 11)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST11_Msk         (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST12_Pos         (12UL)         /*!< ER_ST12 (Bit 12)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST12_Msk         (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST13_Pos         (13UL)         /*!< ER_ST13 (Bit 13)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST13_Msk         (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST14_Pos         (14UL)         /*!< ER_ST14 (Bit 14)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST14_Msk         (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST15_Pos         (15UL)         /*!< ER_ST15 (Bit 15)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST15_Msk         (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST16_Pos         (16UL)         /*!< ER_ST16 (Bit 16)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST16_Msk         (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST17_Pos         (17UL)         /*!< ER_ST17 (Bit 17)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST17_Msk         (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST18_Pos         (18UL)         /*!< ER_ST18 (Bit 18)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST18_Msk         (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST19_Pos         (19UL)         /*!< ER_ST19 (Bit 19)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST19_Msk         (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST20_Pos         (20UL)         /*!< ER_ST20 (Bit 20)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST20_Msk         (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST21_Pos         (21UL)         /*!< ER_ST21 (Bit 21)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST21_Msk         (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST22_Pos         (22UL)         /*!< ER_ST22 (Bit 22)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST22_Msk         (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST23_Pos         (23UL)         /*!< ER_ST23 (Bit 23)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST23_Msk         (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST24_Pos         (24UL)         /*!< ER_ST24 (Bit 24)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST24_Msk         (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST25_Pos         (25UL)         /*!< ER_ST25 (Bit 25)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST25_Msk         (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST26_Pos         (26UL)         /*!< ER_ST26 (Bit 26)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST26_Msk         (0x4000000UL)  /*!< ER_ST26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST27_Pos         (27UL)         /*!< ER_ST27 (Bit 27)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST27_Msk         (0x8000000UL)  /*!< ER_ST27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST28_Pos         (28UL)         /*!< ER_ST28 (Bit 28)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST28_Msk         (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST29_Pos         (29UL)         /*!< ER_ST29 (Bit 29)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST29_Msk         (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST30_Pos         (30UL)         /*!< ER_ST30 (Bit 30)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST30_Msk         (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST31_Pos         (31UL)         /*!< ER_ST31 (Bit 31)                                      */
+ #define R_ICU_NS_DSMIFERR_STAT_ER_ST31_Msk         (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  ENCIFERR_E0MSK  ===================================================== */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK0_Pos         (0UL)          /*!< E0_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK0_Msk         (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK1_Pos         (1UL)          /*!< E0_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK1_Msk         (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK2_Pos         (2UL)          /*!< E0_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK2_Msk         (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK3_Pos         (3UL)          /*!< E0_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK3_Msk         (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK4_Pos         (4UL)          /*!< E0_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK4_Msk         (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK5_Pos         (5UL)          /*!< E0_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK5_Msk         (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK6_Pos         (6UL)          /*!< E0_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK6_Msk         (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK7_Pos         (7UL)          /*!< E0_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK7_Msk         (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK8_Pos         (8UL)          /*!< E0_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK8_Msk         (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK9_Pos         (9UL)          /*!< E0_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK9_Msk         (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK10_Pos        (10UL)         /*!< E0_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK10_Msk        (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK11_Pos        (11UL)         /*!< E0_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK11_Msk        (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK12_Pos        (12UL)         /*!< E0_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK12_Msk        (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK13_Pos        (13UL)         /*!< E0_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK13_Msk        (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK14_Pos        (14UL)         /*!< E0_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK14_Msk        (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK15_Pos        (15UL)         /*!< E0_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK15_Msk        (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK16_Pos        (16UL)         /*!< E0_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK16_Msk        (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK17_Pos        (17UL)         /*!< E0_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK17_Msk        (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK18_Pos        (18UL)         /*!< E0_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK18_Msk        (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK19_Pos        (19UL)         /*!< E0_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK19_Msk        (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK20_Pos        (20UL)         /*!< E0_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK20_Msk        (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK21_Pos        (21UL)         /*!< E0_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK21_Msk        (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK22_Pos        (22UL)         /*!< E0_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK22_Msk        (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK23_Pos        (23UL)         /*!< E0_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK23_Msk        (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK24_Pos        (24UL)         /*!< E0_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK24_Msk        (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK25_Pos        (25UL)         /*!< E0_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK25_Msk        (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK26_Pos        (26UL)         /*!< E0_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK26_Msk        (0x4000000UL)  /*!< E0_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK27_Pos        (27UL)         /*!< E0_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK27_Msk        (0x8000000UL)  /*!< E0_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK28_Pos        (28UL)         /*!< E0_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK28_Msk        (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK29_Pos        (29UL)         /*!< E0_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK29_Msk        (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK30_Pos        (30UL)         /*!< E0_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK30_Msk        (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK31_Pos        (31UL)         /*!< E0_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_ENCIFERR_E0MSK_E0_MK31_Msk        (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  ENCIFERR_E1MSK  ===================================================== */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK0_Pos         (0UL)          /*!< E1_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK0_Msk         (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK1_Pos         (1UL)          /*!< E1_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK1_Msk         (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK2_Pos         (2UL)          /*!< E1_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK2_Msk         (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK3_Pos         (3UL)          /*!< E1_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK3_Msk         (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK4_Pos         (4UL)          /*!< E1_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK4_Msk         (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK5_Pos         (5UL)          /*!< E1_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK5_Msk         (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK6_Pos         (6UL)          /*!< E1_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK6_Msk         (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK7_Pos         (7UL)          /*!< E1_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK7_Msk         (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK8_Pos         (8UL)          /*!< E1_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK8_Msk         (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK9_Pos         (9UL)          /*!< E1_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK9_Msk         (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK10_Pos        (10UL)         /*!< E1_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK10_Msk        (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK11_Pos        (11UL)         /*!< E1_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK11_Msk        (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK12_Pos        (12UL)         /*!< E1_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK12_Msk        (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK13_Pos        (13UL)         /*!< E1_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK13_Msk        (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK14_Pos        (14UL)         /*!< E1_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK14_Msk        (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK15_Pos        (15UL)         /*!< E1_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK15_Msk        (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK16_Pos        (16UL)         /*!< E1_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK16_Msk        (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK17_Pos        (17UL)         /*!< E1_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK17_Msk        (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK18_Pos        (18UL)         /*!< E1_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK18_Msk        (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK19_Pos        (19UL)         /*!< E1_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK19_Msk        (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK20_Pos        (20UL)         /*!< E1_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK20_Msk        (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK21_Pos        (21UL)         /*!< E1_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK21_Msk        (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK22_Pos        (22UL)         /*!< E1_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK22_Msk        (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK23_Pos        (23UL)         /*!< E1_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK23_Msk        (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK24_Pos        (24UL)         /*!< E1_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK24_Msk        (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK25_Pos        (25UL)         /*!< E1_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK25_Msk        (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK26_Pos        (26UL)         /*!< E1_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK26_Msk        (0x4000000UL)  /*!< E1_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK27_Pos        (27UL)         /*!< E1_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK27_Msk        (0x8000000UL)  /*!< E1_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK28_Pos        (28UL)         /*!< E1_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK28_Msk        (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK29_Pos        (29UL)         /*!< E1_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK29_Msk        (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK30_Pos        (30UL)         /*!< E1_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK30_Msk        (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK31_Pos        (31UL)         /*!< E1_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_ENCIFERR_E1MSK_E1_MK31_Msk        (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  ENCIFERR_RSTMSK  ==================================================== */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK0_Pos        (0UL)          /*!< RS_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK0_Msk        (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK1_Pos        (1UL)          /*!< RS_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK1_Msk        (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK2_Pos        (2UL)          /*!< RS_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK2_Msk        (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK3_Pos        (3UL)          /*!< RS_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK3_Msk        (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK4_Pos        (4UL)          /*!< RS_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK4_Msk        (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK5_Pos        (5UL)          /*!< RS_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK5_Msk        (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK6_Pos        (6UL)          /*!< RS_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK6_Msk        (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK7_Pos        (7UL)          /*!< RS_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK7_Msk        (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK8_Pos        (8UL)          /*!< RS_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK8_Msk        (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK9_Pos        (9UL)          /*!< RS_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK9_Msk        (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK10_Pos       (10UL)         /*!< RS_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK10_Msk       (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK11_Pos       (11UL)         /*!< RS_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK11_Msk       (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK12_Pos       (12UL)         /*!< RS_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK12_Msk       (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK13_Pos       (13UL)         /*!< RS_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK13_Msk       (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK14_Pos       (14UL)         /*!< RS_MK14 (Bit 14)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK14_Msk       (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK15_Pos       (15UL)         /*!< RS_MK15 (Bit 15)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK15_Msk       (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK16_Pos       (16UL)         /*!< RS_MK16 (Bit 16)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK16_Msk       (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK17_Pos       (17UL)         /*!< RS_MK17 (Bit 17)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK17_Msk       (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK18_Pos       (18UL)         /*!< RS_MK18 (Bit 18)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK18_Msk       (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK19_Pos       (19UL)         /*!< RS_MK19 (Bit 19)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK19_Msk       (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK20_Pos       (20UL)         /*!< RS_MK20 (Bit 20)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK20_Msk       (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK21_Pos       (21UL)         /*!< RS_MK21 (Bit 21)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK21_Msk       (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK22_Pos       (22UL)         /*!< RS_MK22 (Bit 22)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK22_Msk       (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK23_Pos       (23UL)         /*!< RS_MK23 (Bit 23)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK23_Msk       (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK24_Pos       (24UL)         /*!< RS_MK24 (Bit 24)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK24_Msk       (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK25_Pos       (25UL)         /*!< RS_MK25 (Bit 25)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK25_Msk       (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK26_Pos       (26UL)         /*!< RS_MK26 (Bit 26)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK26_Msk       (0x4000000UL)  /*!< RS_MK26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK27_Pos       (27UL)         /*!< RS_MK27 (Bit 27)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK27_Msk       (0x8000000UL)  /*!< RS_MK27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK28_Pos       (28UL)         /*!< RS_MK28 (Bit 28)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK28_Msk       (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK29_Pos       (29UL)         /*!< RS_MK29 (Bit 29)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK29_Msk       (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK30_Pos       (30UL)         /*!< RS_MK30 (Bit 30)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK30_Msk       (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK31_Pos       (31UL)         /*!< RS_MK31 (Bit 31)                                      */
+ #define R_ICU_NS_ENCIFERR_RSTMSK_RS_MK31_Msk       (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  ENCIFERR_CLR  ====================================================== */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL0_Pos           (0UL)          /*!< ER_CL0 (Bit 0)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL0_Msk           (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL1_Pos           (1UL)          /*!< ER_CL1 (Bit 1)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL1_Msk           (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL2_Pos           (2UL)          /*!< ER_CL2 (Bit 2)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL2_Msk           (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL3_Pos           (3UL)          /*!< ER_CL3 (Bit 3)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL3_Msk           (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL4_Pos           (4UL)          /*!< ER_CL4 (Bit 4)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL4_Msk           (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL5_Pos           (5UL)          /*!< ER_CL5 (Bit 5)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL5_Msk           (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL6_Pos           (6UL)          /*!< ER_CL6 (Bit 6)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL6_Msk           (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL7_Pos           (7UL)          /*!< ER_CL7 (Bit 7)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL7_Msk           (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL8_Pos           (8UL)          /*!< ER_CL8 (Bit 8)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL8_Msk           (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL9_Pos           (9UL)          /*!< ER_CL9 (Bit 9)                                        */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL9_Msk           (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL10_Pos          (10UL)         /*!< ER_CL10 (Bit 10)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL10_Msk          (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL11_Pos          (11UL)         /*!< ER_CL11 (Bit 11)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL11_Msk          (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL12_Pos          (12UL)         /*!< ER_CL12 (Bit 12)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL12_Msk          (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL13_Pos          (13UL)         /*!< ER_CL13 (Bit 13)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL13_Msk          (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL14_Pos          (14UL)         /*!< ER_CL14 (Bit 14)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL14_Msk          (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL15_Pos          (15UL)         /*!< ER_CL15 (Bit 15)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL15_Msk          (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL16_Pos          (16UL)         /*!< ER_CL16 (Bit 16)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL16_Msk          (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL17_Pos          (17UL)         /*!< ER_CL17 (Bit 17)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL17_Msk          (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL18_Pos          (18UL)         /*!< ER_CL18 (Bit 18)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL18_Msk          (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL19_Pos          (19UL)         /*!< ER_CL19 (Bit 19)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL19_Msk          (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL20_Pos          (20UL)         /*!< ER_CL20 (Bit 20)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL20_Msk          (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL21_Pos          (21UL)         /*!< ER_CL21 (Bit 21)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL21_Msk          (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL22_Pos          (22UL)         /*!< ER_CL22 (Bit 22)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL22_Msk          (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL23_Pos          (23UL)         /*!< ER_CL23 (Bit 23)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL23_Msk          (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL24_Pos          (24UL)         /*!< ER_CL24 (Bit 24)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL24_Msk          (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL25_Pos          (25UL)         /*!< ER_CL25 (Bit 25)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL25_Msk          (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL26_Pos          (26UL)         /*!< ER_CL26 (Bit 26)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL26_Msk          (0x4000000UL)  /*!< ER_CL26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL27_Pos          (27UL)         /*!< ER_CL27 (Bit 27)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL27_Msk          (0x8000000UL)  /*!< ER_CL27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL28_Pos          (28UL)         /*!< ER_CL28 (Bit 28)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL28_Msk          (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL29_Pos          (29UL)         /*!< ER_CL29 (Bit 29)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL29_Msk          (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL30_Pos          (30UL)         /*!< ER_CL30 (Bit 30)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL30_Msk          (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL31_Pos          (31UL)         /*!< ER_CL31 (Bit 31)                                      */
+ #define R_ICU_NS_ENCIFERR_CLR_ER_CL31_Msk          (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  ENCIFERR_STAT  ===================================================== */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST0_Pos          (0UL)          /*!< ER_ST0 (Bit 0)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST0_Msk          (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST1_Pos          (1UL)          /*!< ER_ST1 (Bit 1)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST1_Msk          (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST2_Pos          (2UL)          /*!< ER_ST2 (Bit 2)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST2_Msk          (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST3_Pos          (3UL)          /*!< ER_ST3 (Bit 3)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST3_Msk          (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST4_Pos          (4UL)          /*!< ER_ST4 (Bit 4)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST4_Msk          (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST5_Pos          (5UL)          /*!< ER_ST5 (Bit 5)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST5_Msk          (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST6_Pos          (6UL)          /*!< ER_ST6 (Bit 6)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST6_Msk          (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST7_Pos          (7UL)          /*!< ER_ST7 (Bit 7)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST7_Msk          (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST8_Pos          (8UL)          /*!< ER_ST8 (Bit 8)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST8_Msk          (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST9_Pos          (9UL)          /*!< ER_ST9 (Bit 9)                                        */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST9_Msk          (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST10_Pos         (10UL)         /*!< ER_ST10 (Bit 10)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST10_Msk         (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST11_Pos         (11UL)         /*!< ER_ST11 (Bit 11)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST11_Msk         (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST12_Pos         (12UL)         /*!< ER_ST12 (Bit 12)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST12_Msk         (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST13_Pos         (13UL)         /*!< ER_ST13 (Bit 13)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST13_Msk         (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST14_Pos         (14UL)         /*!< ER_ST14 (Bit 14)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST14_Msk         (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST15_Pos         (15UL)         /*!< ER_ST15 (Bit 15)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST15_Msk         (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST16_Pos         (16UL)         /*!< ER_ST16 (Bit 16)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST16_Msk         (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST17_Pos         (17UL)         /*!< ER_ST17 (Bit 17)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST17_Msk         (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST18_Pos         (18UL)         /*!< ER_ST18 (Bit 18)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST18_Msk         (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST19_Pos         (19UL)         /*!< ER_ST19 (Bit 19)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST19_Msk         (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST20_Pos         (20UL)         /*!< ER_ST20 (Bit 20)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST20_Msk         (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST21_Pos         (21UL)         /*!< ER_ST21 (Bit 21)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST21_Msk         (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST22_Pos         (22UL)         /*!< ER_ST22 (Bit 22)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST22_Msk         (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST23_Pos         (23UL)         /*!< ER_ST23 (Bit 23)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST23_Msk         (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST24_Pos         (24UL)         /*!< ER_ST24 (Bit 24)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST24_Msk         (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST25_Pos         (25UL)         /*!< ER_ST25 (Bit 25)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST25_Msk         (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST26_Pos         (26UL)         /*!< ER_ST26 (Bit 26)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST26_Msk         (0x4000000UL)  /*!< ER_ST26 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST27_Pos         (27UL)         /*!< ER_ST27 (Bit 27)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST27_Msk         (0x8000000UL)  /*!< ER_ST27 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST28_Pos         (28UL)         /*!< ER_ST28 (Bit 28)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST28_Msk         (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST29_Pos         (29UL)         /*!< ER_ST29 (Bit 29)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST29_Msk         (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST30_Pos         (30UL)         /*!< ER_ST30 (Bit 30)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST30_Msk         (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST31_Pos         (31UL)         /*!< ER_ST31 (Bit 31)                                      */
+ #define R_ICU_NS_ENCIFERR_STAT_ER_ST31_Msk         (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  ENCIF_ENCSEL0  ===================================================== */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL0_Pos         (0UL)          /*!< ENCSEL0 (Bit 0)                                       */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL0_Msk         (0x7UL)        /*!< ENCSEL0 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL1_Pos         (4UL)          /*!< ENCSEL1 (Bit 4)                                       */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL1_Msk         (0x70UL)       /*!< ENCSEL1 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL2_Pos         (8UL)          /*!< ENCSEL2 (Bit 8)                                       */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL2_Msk         (0x700UL)      /*!< ENCSEL2 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL3_Pos         (12UL)         /*!< ENCSEL3 (Bit 12)                                      */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL3_Msk         (0x7000UL)     /*!< ENCSEL3 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL4_Pos         (16UL)         /*!< ENCSEL4 (Bit 16)                                      */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL4_Msk         (0x70000UL)    /*!< ENCSEL4 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL5_Pos         (20UL)         /*!< ENCSEL5 (Bit 20)                                      */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL5_Msk         (0x700000UL)   /*!< ENCSEL5 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL6_Pos         (24UL)         /*!< ENCSEL6 (Bit 24)                                      */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL6_Msk         (0x7000000UL)  /*!< ENCSEL6 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL7_Pos         (28UL)         /*!< ENCSEL7 (Bit 28)                                      */
+ #define R_ICU_NS_ENCIF_ENCSEL0_ENCSEL7_Msk         (0x70000000UL) /*!< ENCSEL7 (Bitfield-Mask: 0x07)                         */
+/* =====================================================  ENCIF_ENCSEL1  ===================================================== */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL8_Pos         (0UL)          /*!< ENCSEL8 (Bit 0)                                       */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL8_Msk         (0x7UL)        /*!< ENCSEL8 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL9_Pos         (4UL)          /*!< ENCSEL9 (Bit 4)                                       */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL9_Msk         (0x70UL)       /*!< ENCSEL9 (Bitfield-Mask: 0x07)                         */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL10_Pos        (8UL)          /*!< ENCSEL10 (Bit 8)                                      */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL10_Msk        (0x700UL)      /*!< ENCSEL10 (Bitfield-Mask: 0x07)                        */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL11_Pos        (12UL)         /*!< ENCSEL11 (Bit 12)                                     */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL11_Msk        (0x7000UL)     /*!< ENCSEL11 (Bitfield-Mask: 0x07)                        */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL12_Pos        (16UL)         /*!< ENCSEL12 (Bit 16)                                     */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL12_Msk        (0x70000UL)    /*!< ENCSEL12 (Bitfield-Mask: 0x07)                        */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL13_Pos        (20UL)         /*!< ENCSEL13 (Bit 20)                                     */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL13_Msk        (0x700000UL)   /*!< ENCSEL13 (Bitfield-Mask: 0x07)                        */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL14_Pos        (24UL)         /*!< ENCSEL14 (Bit 24)                                     */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL14_Msk        (0x7000000UL)  /*!< ENCSEL14 (Bitfield-Mask: 0x07)                        */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL15_Pos        (28UL)         /*!< ENCSEL15 (Bit 28)                                     */
+ #define R_ICU_NS_ENCIF_ENCSEL1_ENCSEL15_Msk        (0x70000000UL) /*!< ENCSEL15 (Bitfield-Mask: 0x07)                        */
+/* =====================================================  NS_GPT_INTSEL  ===================================================== */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELX_0_Pos       (0UL)          /*!< INTSELX_0 (Bit 0)                                     */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELX_0_Msk       (0xfUL)        /*!< INTSELX_0 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELX_1_Pos       (4UL)          /*!< INTSELX_1 (Bit 4)                                     */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELX_1_Msk       (0xf0UL)       /*!< INTSELX_1 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELX_2_Pos       (8UL)          /*!< INTSELX_2 (Bit 8)                                     */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELX_2_Msk       (0xf00UL)      /*!< INTSELX_2 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELX_3_Pos       (12UL)         /*!< INTSELX_3 (Bit 12)                                    */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELX_3_Msk       (0xf000UL)     /*!< INTSELX_3 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELY_0_Pos       (16UL)         /*!< INTSELY_0 (Bit 16)                                    */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELY_0_Msk       (0xf0000UL)    /*!< INTSELY_0 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELY_1_Pos       (20UL)         /*!< INTSELY_1 (Bit 20)                                    */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELY_1_Msk       (0xf00000UL)   /*!< INTSELY_1 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELY_2_Pos       (24UL)         /*!< INTSELY_2 (Bit 24)                                    */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELY_2_Msk       (0xf000000UL)  /*!< INTSELY_2 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELY_3_Pos       (28UL)         /*!< INTSELY_3 (Bit 28)                                    */
+ #define R_ICU_NS_NS_GPT_INTSEL_INTSELY_3_Msk       (0xf0000000UL) /*!< INTSELY_3 (Bitfield-Mask: 0x0f)                       */
+/* ====================================================  ELC_GPT_INTSEL  ===================================================== */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELX_0_Pos      (0UL)          /*!< INTSELX_0 (Bit 0)                                     */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELX_0_Msk      (0xfUL)        /*!< INTSELX_0 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELX_1_Pos      (4UL)          /*!< INTSELX_1 (Bit 4)                                     */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELX_1_Msk      (0xf0UL)       /*!< INTSELX_1 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELX_2_Pos      (8UL)          /*!< INTSELX_2 (Bit 8)                                     */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELX_2_Msk      (0xf00UL)      /*!< INTSELX_2 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELX_3_Pos      (12UL)         /*!< INTSELX_3 (Bit 12)                                    */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELX_3_Msk      (0xf000UL)     /*!< INTSELX_3 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELY_0_Pos      (16UL)         /*!< INTSELY_0 (Bit 16)                                    */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELY_0_Msk      (0xf0000UL)    /*!< INTSELY_0 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELY_1_Pos      (20UL)         /*!< INTSELY_1 (Bit 20)                                    */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELY_1_Msk      (0xf00000UL)   /*!< INTSELY_1 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELY_2_Pos      (24UL)         /*!< INTSELY_2 (Bit 24)                                    */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELY_2_Msk      (0xf000000UL)  /*!< INTSELY_2 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELY_3_Pos      (28UL)         /*!< INTSELY_3 (Bit 28)                                    */
+ #define R_ICU_NS_ELC_GPT_INTSEL_INTSELY_3_Msk      (0xf0000000UL) /*!< INTSELY_3 (Bitfield-Mask: 0x0f)                       */
+/* =====================================================  CR520_INTSEL  ====================================================== */
+ #define R_ICU_NS_CR520_INTSEL_INTSELX_Pos          (0UL)          /*!< INTSELX (Bit 0)                                       */
+ #define R_ICU_NS_CR520_INTSEL_INTSELX_Msk          (0x3ffUL)      /*!< INTSELX (Bitfield-Mask: 0x3ff)                        */
+ #define R_ICU_NS_CR520_INTSEL_INTSELY_Pos          (16UL)         /*!< INTSELY (Bit 16)                                      */
+ #define R_ICU_NS_CR520_INTSEL_INTSELY_Msk          (0x3ff0000UL)  /*!< INTSELY (Bitfield-Mask: 0x3ff)                        */
+/* =====================================================  CR521_INTSEL  ====================================================== */
+ #define R_ICU_NS_CR521_INTSEL_INTSELX_Pos          (0UL)          /*!< INTSELX (Bit 0)                                       */
+ #define R_ICU_NS_CR521_INTSEL_INTSELX_Msk          (0x3ffUL)      /*!< INTSELX (Bitfield-Mask: 0x3ff)                        */
+ #define R_ICU_NS_CR521_INTSEL_INTSELY_Pos          (16UL)         /*!< INTSELY (Bit 16)                                      */
+ #define R_ICU_NS_CR521_INTSEL_INTSELY_Msk          (0x3ff0000UL)  /*!< INTSELY (Bitfield-Mask: 0x3ff)                        */
+/* =====================================================  NS_GPT_INTMSK  ===================================================== */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK0_Pos          (0UL)          /*!< IX_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK0_Msk          (0x1UL)        /*!< IX_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK1_Pos          (1UL)          /*!< IX_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK1_Msk          (0x2UL)        /*!< IX_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK2_Pos          (2UL)          /*!< IX_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK2_Msk          (0x4UL)        /*!< IX_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK3_Pos          (3UL)          /*!< IX_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK3_Msk          (0x8UL)        /*!< IX_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK4_Pos          (4UL)          /*!< IX_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK4_Msk          (0x10UL)       /*!< IX_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK5_Pos          (5UL)          /*!< IX_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK5_Msk          (0x20UL)       /*!< IX_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK6_Pos          (6UL)          /*!< IX_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK6_Msk          (0x40UL)       /*!< IX_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK7_Pos          (7UL)          /*!< IX_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK7_Msk          (0x80UL)       /*!< IX_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK8_Pos          (8UL)          /*!< IX_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK8_Msk          (0x100UL)      /*!< IX_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK9_Pos          (9UL)          /*!< IX_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK9_Msk          (0x200UL)      /*!< IX_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK10_Pos         (10UL)         /*!< IX_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK10_Msk         (0x400UL)      /*!< IX_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK11_Pos         (11UL)         /*!< IX_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK11_Msk         (0x800UL)      /*!< IX_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK12_Pos         (12UL)         /*!< IX_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK12_Msk         (0x1000UL)     /*!< IX_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK13_Pos         (13UL)         /*!< IX_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_NS_GPT_INTMSK_IX_MK13_Msk         (0x2000UL)     /*!< IX_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK0_Pos          (16UL)         /*!< IY_MK0 (Bit 16)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK0_Msk          (0x10000UL)    /*!< IY_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK1_Pos          (17UL)         /*!< IY_MK1 (Bit 17)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK1_Msk          (0x20000UL)    /*!< IY_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK2_Pos          (18UL)         /*!< IY_MK2 (Bit 18)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK2_Msk          (0x40000UL)    /*!< IY_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK3_Pos          (19UL)         /*!< IY_MK3 (Bit 19)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK3_Msk          (0x80000UL)    /*!< IY_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK4_Pos          (20UL)         /*!< IY_MK4 (Bit 20)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK4_Msk          (0x100000UL)   /*!< IY_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK5_Pos          (21UL)         /*!< IY_MK5 (Bit 21)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK5_Msk          (0x200000UL)   /*!< IY_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK6_Pos          (22UL)         /*!< IY_MK6 (Bit 22)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK6_Msk          (0x400000UL)   /*!< IY_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK7_Pos          (23UL)         /*!< IY_MK7 (Bit 23)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK7_Msk          (0x800000UL)   /*!< IY_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK8_Pos          (24UL)         /*!< IY_MK8 (Bit 24)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK8_Msk          (0x1000000UL)  /*!< IY_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK9_Pos          (25UL)         /*!< IY_MK9 (Bit 25)                                       */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK9_Msk          (0x2000000UL)  /*!< IY_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK10_Pos         (26UL)         /*!< IY_MK10 (Bit 26)                                      */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK10_Msk         (0x4000000UL)  /*!< IY_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK11_Pos         (27UL)         /*!< IY_MK11 (Bit 27)                                      */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK11_Msk         (0x8000000UL)  /*!< IY_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK12_Pos         (28UL)         /*!< IY_MK12 (Bit 28)                                      */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK12_Msk         (0x10000000UL) /*!< IY_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK13_Pos         (29UL)         /*!< IY_MK13 (Bit 29)                                      */
+ #define R_ICU_NS_NS_GPT_INTMSK_IY_MK13_Msk         (0x20000000UL) /*!< IY_MK13 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  ELC_GPT_INTMSK  ===================================================== */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK0_Pos         (0UL)          /*!< IX_MK0 (Bit 0)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK0_Msk         (0x1UL)        /*!< IX_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK1_Pos         (1UL)          /*!< IX_MK1 (Bit 1)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK1_Msk         (0x2UL)        /*!< IX_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK2_Pos         (2UL)          /*!< IX_MK2 (Bit 2)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK2_Msk         (0x4UL)        /*!< IX_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK3_Pos         (3UL)          /*!< IX_MK3 (Bit 3)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK3_Msk         (0x8UL)        /*!< IX_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK4_Pos         (4UL)          /*!< IX_MK4 (Bit 4)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK4_Msk         (0x10UL)       /*!< IX_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK5_Pos         (5UL)          /*!< IX_MK5 (Bit 5)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK5_Msk         (0x20UL)       /*!< IX_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK6_Pos         (6UL)          /*!< IX_MK6 (Bit 6)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK6_Msk         (0x40UL)       /*!< IX_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK7_Pos         (7UL)          /*!< IX_MK7 (Bit 7)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK7_Msk         (0x80UL)       /*!< IX_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK8_Pos         (8UL)          /*!< IX_MK8 (Bit 8)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK8_Msk         (0x100UL)      /*!< IX_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK9_Pos         (9UL)          /*!< IX_MK9 (Bit 9)                                        */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK9_Msk         (0x200UL)      /*!< IX_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK10_Pos        (10UL)         /*!< IX_MK10 (Bit 10)                                      */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK10_Msk        (0x400UL)      /*!< IX_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK11_Pos        (11UL)         /*!< IX_MK11 (Bit 11)                                      */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK11_Msk        (0x800UL)      /*!< IX_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK12_Pos        (12UL)         /*!< IX_MK12 (Bit 12)                                      */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK12_Msk        (0x1000UL)     /*!< IX_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK13_Pos        (13UL)         /*!< IX_MK13 (Bit 13)                                      */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IX_MK13_Msk        (0x2000UL)     /*!< IX_MK13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK0_Pos         (16UL)         /*!< IY_MK0 (Bit 16)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK0_Msk         (0x10000UL)    /*!< IY_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK1_Pos         (17UL)         /*!< IY_MK1 (Bit 17)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK1_Msk         (0x20000UL)    /*!< IY_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK2_Pos         (18UL)         /*!< IY_MK2 (Bit 18)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK2_Msk         (0x40000UL)    /*!< IY_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK3_Pos         (19UL)         /*!< IY_MK3 (Bit 19)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK3_Msk         (0x80000UL)    /*!< IY_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK4_Pos         (20UL)         /*!< IY_MK4 (Bit 20)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK4_Msk         (0x100000UL)   /*!< IY_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK5_Pos         (21UL)         /*!< IY_MK5 (Bit 21)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK5_Msk         (0x200000UL)   /*!< IY_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK6_Pos         (22UL)         /*!< IY_MK6 (Bit 22)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK6_Msk         (0x400000UL)   /*!< IY_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK7_Pos         (23UL)         /*!< IY_MK7 (Bit 23)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK7_Msk         (0x800000UL)   /*!< IY_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK8_Pos         (24UL)         /*!< IY_MK8 (Bit 24)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK8_Msk         (0x1000000UL)  /*!< IY_MK8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK9_Pos         (25UL)         /*!< IY_MK9 (Bit 25)                                       */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK9_Msk         (0x2000000UL)  /*!< IY_MK9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK10_Pos        (26UL)         /*!< IY_MK10 (Bit 26)                                      */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK10_Msk        (0x4000000UL)  /*!< IY_MK10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK11_Pos        (27UL)         /*!< IY_MK11 (Bit 27)                                      */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK11_Msk        (0x8000000UL)  /*!< IY_MK11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK12_Pos        (28UL)         /*!< IY_MK12 (Bit 28)                                      */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK12_Msk        (0x10000000UL) /*!< IY_MK12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK13_Pos        (29UL)         /*!< IY_MK13 (Bit 29)                                      */
+ #define R_ICU_NS_ELC_GPT_INTMSK_IY_MK13_Msk        (0x20000000UL) /*!< IY_MK13 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  NS_GPT_INTCLR  ===================================================== */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL0_Pos          (0UL)          /*!< IX_CL0 (Bit 0)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL0_Msk          (0x1UL)        /*!< IX_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL1_Pos          (1UL)          /*!< IX_CL1 (Bit 1)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL1_Msk          (0x2UL)        /*!< IX_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL2_Pos          (2UL)          /*!< IX_CL2 (Bit 2)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL2_Msk          (0x4UL)        /*!< IX_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL3_Pos          (3UL)          /*!< IX_CL3 (Bit 3)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL3_Msk          (0x8UL)        /*!< IX_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL4_Pos          (4UL)          /*!< IX_CL4 (Bit 4)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL4_Msk          (0x10UL)       /*!< IX_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL5_Pos          (5UL)          /*!< IX_CL5 (Bit 5)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL5_Msk          (0x20UL)       /*!< IX_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL6_Pos          (6UL)          /*!< IX_CL6 (Bit 6)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL6_Msk          (0x40UL)       /*!< IX_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL7_Pos          (7UL)          /*!< IX_CL7 (Bit 7)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL7_Msk          (0x80UL)       /*!< IX_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL8_Pos          (8UL)          /*!< IX_CL8 (Bit 8)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL8_Msk          (0x100UL)      /*!< IX_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL9_Pos          (9UL)          /*!< IX_CL9 (Bit 9)                                        */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL9_Msk          (0x200UL)      /*!< IX_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL10_Pos         (10UL)         /*!< IX_CL10 (Bit 10)                                      */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL10_Msk         (0x400UL)      /*!< IX_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL11_Pos         (11UL)         /*!< IX_CL11 (Bit 11)                                      */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL11_Msk         (0x800UL)      /*!< IX_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL12_Pos         (12UL)         /*!< IX_CL12 (Bit 12)                                      */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL12_Msk         (0x1000UL)     /*!< IX_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL13_Pos         (13UL)         /*!< IX_CL13 (Bit 13)                                      */
+ #define R_ICU_NS_NS_GPT_INTCLR_IX_CL13_Msk         (0x2000UL)     /*!< IX_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL0_Pos          (16UL)         /*!< IY_CL0 (Bit 16)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL0_Msk          (0x10000UL)    /*!< IY_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL1_Pos          (17UL)         /*!< IY_CL1 (Bit 17)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL1_Msk          (0x20000UL)    /*!< IY_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL2_Pos          (18UL)         /*!< IY_CL2 (Bit 18)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL2_Msk          (0x40000UL)    /*!< IY_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL3_Pos          (19UL)         /*!< IY_CL3 (Bit 19)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL3_Msk          (0x80000UL)    /*!< IY_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL4_Pos          (20UL)         /*!< IY_CL4 (Bit 20)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL4_Msk          (0x100000UL)   /*!< IY_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL5_Pos          (21UL)         /*!< IY_CL5 (Bit 21)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL5_Msk          (0x200000UL)   /*!< IY_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL6_Pos          (22UL)         /*!< IY_CL6 (Bit 22)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL6_Msk          (0x400000UL)   /*!< IY_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL7_Pos          (23UL)         /*!< IY_CL7 (Bit 23)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL7_Msk          (0x800000UL)   /*!< IY_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL8_Pos          (24UL)         /*!< IY_CL8 (Bit 24)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL8_Msk          (0x1000000UL)  /*!< IY_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL9_Pos          (25UL)         /*!< IY_CL9 (Bit 25)                                       */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL9_Msk          (0x2000000UL)  /*!< IY_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL10_Pos         (26UL)         /*!< IY_CL10 (Bit 26)                                      */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL10_Msk         (0x4000000UL)  /*!< IY_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL11_Pos         (27UL)         /*!< IY_CL11 (Bit 27)                                      */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL11_Msk         (0x8000000UL)  /*!< IY_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL12_Pos         (28UL)         /*!< IY_CL12 (Bit 28)                                      */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL12_Msk         (0x10000000UL) /*!< IY_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL13_Pos         (29UL)         /*!< IY_CL13 (Bit 29)                                      */
+ #define R_ICU_NS_NS_GPT_INTCLR_IY_CL13_Msk         (0x20000000UL) /*!< IY_CL13 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  ELC_GPT_INTCLR  ===================================================== */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL0_Pos         (0UL)          /*!< IX_CL0 (Bit 0)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL0_Msk         (0x1UL)        /*!< IX_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL1_Pos         (1UL)          /*!< IX_CL1 (Bit 1)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL1_Msk         (0x2UL)        /*!< IX_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL2_Pos         (2UL)          /*!< IX_CL2 (Bit 2)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL2_Msk         (0x4UL)        /*!< IX_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL3_Pos         (3UL)          /*!< IX_CL3 (Bit 3)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL3_Msk         (0x8UL)        /*!< IX_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL4_Pos         (4UL)          /*!< IX_CL4 (Bit 4)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL4_Msk         (0x10UL)       /*!< IX_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL5_Pos         (5UL)          /*!< IX_CL5 (Bit 5)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL5_Msk         (0x20UL)       /*!< IX_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL6_Pos         (6UL)          /*!< IX_CL6 (Bit 6)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL6_Msk         (0x40UL)       /*!< IX_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL7_Pos         (7UL)          /*!< IX_CL7 (Bit 7)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL7_Msk         (0x80UL)       /*!< IX_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL8_Pos         (8UL)          /*!< IX_CL8 (Bit 8)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL8_Msk         (0x100UL)      /*!< IX_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL9_Pos         (9UL)          /*!< IX_CL9 (Bit 9)                                        */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL9_Msk         (0x200UL)      /*!< IX_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL10_Pos        (10UL)         /*!< IX_CL10 (Bit 10)                                      */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL10_Msk        (0x400UL)      /*!< IX_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL11_Pos        (11UL)         /*!< IX_CL11 (Bit 11)                                      */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL11_Msk        (0x800UL)      /*!< IX_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL12_Pos        (12UL)         /*!< IX_CL12 (Bit 12)                                      */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL12_Msk        (0x1000UL)     /*!< IX_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL13_Pos        (13UL)         /*!< IX_CL13 (Bit 13)                                      */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IX_CL13_Msk        (0x2000UL)     /*!< IX_CL13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL0_Pos         (16UL)         /*!< IY_CL0 (Bit 16)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL0_Msk         (0x10000UL)    /*!< IY_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL1_Pos         (17UL)         /*!< IY_CL1 (Bit 17)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL1_Msk         (0x20000UL)    /*!< IY_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL2_Pos         (18UL)         /*!< IY_CL2 (Bit 18)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL2_Msk         (0x40000UL)    /*!< IY_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL3_Pos         (19UL)         /*!< IY_CL3 (Bit 19)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL3_Msk         (0x80000UL)    /*!< IY_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL4_Pos         (20UL)         /*!< IY_CL4 (Bit 20)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL4_Msk         (0x100000UL)   /*!< IY_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL5_Pos         (21UL)         /*!< IY_CL5 (Bit 21)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL5_Msk         (0x200000UL)   /*!< IY_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL6_Pos         (22UL)         /*!< IY_CL6 (Bit 22)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL6_Msk         (0x400000UL)   /*!< IY_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL7_Pos         (23UL)         /*!< IY_CL7 (Bit 23)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL7_Msk         (0x800000UL)   /*!< IY_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL8_Pos         (24UL)         /*!< IY_CL8 (Bit 24)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL8_Msk         (0x1000000UL)  /*!< IY_CL8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL9_Pos         (25UL)         /*!< IY_CL9 (Bit 25)                                       */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL9_Msk         (0x2000000UL)  /*!< IY_CL9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL10_Pos        (26UL)         /*!< IY_CL10 (Bit 26)                                      */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL10_Msk        (0x4000000UL)  /*!< IY_CL10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL11_Pos        (27UL)         /*!< IY_CL11 (Bit 27)                                      */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL11_Msk        (0x8000000UL)  /*!< IY_CL11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL12_Pos        (28UL)         /*!< IY_CL12 (Bit 28)                                      */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL12_Msk        (0x10000000UL) /*!< IY_CL12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL13_Pos        (29UL)         /*!< IY_CL13 (Bit 29)                                      */
+ #define R_ICU_NS_ELC_GPT_INTCLR_IY_CL13_Msk        (0x20000000UL) /*!< IY_CL13 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  NS_GPT_INTSTAT  ===================================================== */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST0_Pos         (0UL)          /*!< IX_ST0 (Bit 0)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST0_Msk         (0x1UL)        /*!< IX_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST1_Pos         (1UL)          /*!< IX_ST1 (Bit 1)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST1_Msk         (0x2UL)        /*!< IX_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST2_Pos         (2UL)          /*!< IX_ST2 (Bit 2)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST2_Msk         (0x4UL)        /*!< IX_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST3_Pos         (3UL)          /*!< IX_ST3 (Bit 3)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST3_Msk         (0x8UL)        /*!< IX_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST4_Pos         (4UL)          /*!< IX_ST4 (Bit 4)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST4_Msk         (0x10UL)       /*!< IX_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST5_Pos         (5UL)          /*!< IX_ST5 (Bit 5)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST5_Msk         (0x20UL)       /*!< IX_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST6_Pos         (6UL)          /*!< IX_ST6 (Bit 6)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST6_Msk         (0x40UL)       /*!< IX_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST7_Pos         (7UL)          /*!< IX_ST7 (Bit 7)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST7_Msk         (0x80UL)       /*!< IX_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST8_Pos         (8UL)          /*!< IX_ST8 (Bit 8)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST8_Msk         (0x100UL)      /*!< IX_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST9_Pos         (9UL)          /*!< IX_ST9 (Bit 9)                                        */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST9_Msk         (0x200UL)      /*!< IX_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST10_Pos        (10UL)         /*!< IX_ST10 (Bit 10)                                      */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST10_Msk        (0x400UL)      /*!< IX_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST11_Pos        (11UL)         /*!< IX_ST11 (Bit 11)                                      */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST11_Msk        (0x800UL)      /*!< IX_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST12_Pos        (12UL)         /*!< IX_ST12 (Bit 12)                                      */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST12_Msk        (0x1000UL)     /*!< IX_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST13_Pos        (13UL)         /*!< IX_ST13 (Bit 13)                                      */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IX_ST13_Msk        (0x2000UL)     /*!< IX_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST0_Pos         (16UL)         /*!< IY_ST0 (Bit 16)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST0_Msk         (0x10000UL)    /*!< IY_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST1_Pos         (17UL)         /*!< IY_ST1 (Bit 17)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST1_Msk         (0x20000UL)    /*!< IY_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST2_Pos         (18UL)         /*!< IY_ST2 (Bit 18)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST2_Msk         (0x40000UL)    /*!< IY_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST3_Pos         (19UL)         /*!< IY_ST3 (Bit 19)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST3_Msk         (0x80000UL)    /*!< IY_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST4_Pos         (20UL)         /*!< IY_ST4 (Bit 20)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST4_Msk         (0x100000UL)   /*!< IY_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST5_Pos         (21UL)         /*!< IY_ST5 (Bit 21)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST5_Msk         (0x200000UL)   /*!< IY_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST6_Pos         (22UL)         /*!< IY_ST6 (Bit 22)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST6_Msk         (0x400000UL)   /*!< IY_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST7_Pos         (23UL)         /*!< IY_ST7 (Bit 23)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST7_Msk         (0x800000UL)   /*!< IY_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST8_Pos         (24UL)         /*!< IY_ST8 (Bit 24)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST8_Msk         (0x1000000UL)  /*!< IY_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST9_Pos         (25UL)         /*!< IY_ST9 (Bit 25)                                       */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST9_Msk         (0x2000000UL)  /*!< IY_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST10_Pos        (26UL)         /*!< IY_ST10 (Bit 26)                                      */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST10_Msk        (0x4000000UL)  /*!< IY_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST11_Pos        (27UL)         /*!< IY_ST11 (Bit 27)                                      */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST11_Msk        (0x8000000UL)  /*!< IY_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST12_Pos        (28UL)         /*!< IY_ST12 (Bit 28)                                      */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST12_Msk        (0x10000000UL) /*!< IY_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST13_Pos        (29UL)         /*!< IY_ST13 (Bit 29)                                      */
+ #define R_ICU_NS_NS_GPT_INTSTAT_IY_ST13_Msk        (0x20000000UL) /*!< IY_ST13 (Bitfield-Mask: 0x01)                         */
+/* ====================================================  ELC_GPT_INTSTAT  ==================================================== */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST0_Pos        (0UL)          /*!< IX_ST0 (Bit 0)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST0_Msk        (0x1UL)        /*!< IX_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST1_Pos        (1UL)          /*!< IX_ST1 (Bit 1)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST1_Msk        (0x2UL)        /*!< IX_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST2_Pos        (2UL)          /*!< IX_ST2 (Bit 2)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST2_Msk        (0x4UL)        /*!< IX_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST3_Pos        (3UL)          /*!< IX_ST3 (Bit 3)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST3_Msk        (0x8UL)        /*!< IX_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST4_Pos        (4UL)          /*!< IX_ST4 (Bit 4)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST4_Msk        (0x10UL)       /*!< IX_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST5_Pos        (5UL)          /*!< IX_ST5 (Bit 5)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST5_Msk        (0x20UL)       /*!< IX_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST6_Pos        (6UL)          /*!< IX_ST6 (Bit 6)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST6_Msk        (0x40UL)       /*!< IX_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST7_Pos        (7UL)          /*!< IX_ST7 (Bit 7)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST7_Msk        (0x80UL)       /*!< IX_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST8_Pos        (8UL)          /*!< IX_ST8 (Bit 8)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST8_Msk        (0x100UL)      /*!< IX_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST9_Pos        (9UL)          /*!< IX_ST9 (Bit 9)                                        */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST9_Msk        (0x200UL)      /*!< IX_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST10_Pos       (10UL)         /*!< IX_ST10 (Bit 10)                                      */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST10_Msk       (0x400UL)      /*!< IX_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST11_Pos       (11UL)         /*!< IX_ST11 (Bit 11)                                      */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST11_Msk       (0x800UL)      /*!< IX_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST12_Pos       (12UL)         /*!< IX_ST12 (Bit 12)                                      */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST12_Msk       (0x1000UL)     /*!< IX_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST13_Pos       (13UL)         /*!< IX_ST13 (Bit 13)                                      */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IX_ST13_Msk       (0x2000UL)     /*!< IX_ST13 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST0_Pos        (16UL)         /*!< IY_ST0 (Bit 16)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST0_Msk        (0x10000UL)    /*!< IY_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST1_Pos        (17UL)         /*!< IY_ST1 (Bit 17)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST1_Msk        (0x20000UL)    /*!< IY_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST2_Pos        (18UL)         /*!< IY_ST2 (Bit 18)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST2_Msk        (0x40000UL)    /*!< IY_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST3_Pos        (19UL)         /*!< IY_ST3 (Bit 19)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST3_Msk        (0x80000UL)    /*!< IY_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST4_Pos        (20UL)         /*!< IY_ST4 (Bit 20)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST4_Msk        (0x100000UL)   /*!< IY_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST5_Pos        (21UL)         /*!< IY_ST5 (Bit 21)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST5_Msk        (0x200000UL)   /*!< IY_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST6_Pos        (22UL)         /*!< IY_ST6 (Bit 22)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST6_Msk        (0x400000UL)   /*!< IY_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST7_Pos        (23UL)         /*!< IY_ST7 (Bit 23)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST7_Msk        (0x800000UL)   /*!< IY_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST8_Pos        (24UL)         /*!< IY_ST8 (Bit 24)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST8_Msk        (0x1000000UL)  /*!< IY_ST8 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST9_Pos        (25UL)         /*!< IY_ST9 (Bit 25)                                       */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST9_Msk        (0x2000000UL)  /*!< IY_ST9 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST10_Pos       (26UL)         /*!< IY_ST10 (Bit 26)                                      */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST10_Msk       (0x4000000UL)  /*!< IY_ST10 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST11_Pos       (27UL)         /*!< IY_ST11 (Bit 27)                                      */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST11_Msk       (0x8000000UL)  /*!< IY_ST11 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST12_Pos       (28UL)         /*!< IY_ST12 (Bit 28)                                      */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST12_Msk       (0x10000000UL) /*!< IY_ST12 (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST13_Pos       (29UL)         /*!< IY_ST13 (Bit 29)                                      */
+ #define R_ICU_NS_ELC_GPT_INTSTAT_IY_ST13_Msk       (0x20000000UL) /*!< IY_ST13 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  ELC_SSEL  ======================================================== */
+ #define R_ELC_ELC_SSEL_ELC_SEL0_Pos    (0UL)          /*!< ELC_SEL0 (Bit 0)                                      */
+ #define R_ELC_ELC_SSEL_ELC_SEL0_Msk    (0x3ffUL)      /*!< ELC_SEL0 (Bitfield-Mask: 0x3ff)                       */
+ #define R_ELC_ELC_SSEL_ELC_SEL1_Pos    (10UL)         /*!< ELC_SEL1 (Bit 10)                                     */
+ #define R_ELC_ELC_SSEL_ELC_SEL1_Msk    (0xffc00UL)    /*!< ELC_SEL1 (Bitfield-Mask: 0x3ff)                       */
+ #define R_ELC_ELC_SSEL_ELC_SEL2_Pos    (20UL)         /*!< ELC_SEL2 (Bit 20)                                     */
+ #define R_ELC_ELC_SSEL_ELC_SEL2_Msk    (0x3ff00000UL) /*!< ELC_SEL2 (Bitfield-Mask: 0x3ff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  DMAC0_RSSEL  ====================================================== */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELA_Pos    (0UL)          /*!< REQ_SELA (Bit 0)                                      */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELA_Msk    (0x3ffUL)      /*!< REQ_SELA (Bitfield-Mask: 0x3ff)                       */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELB_Pos    (10UL)         /*!< REQ_SELB (Bit 10)                                     */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELB_Msk    (0xffc00UL)    /*!< REQ_SELB (Bitfield-Mask: 0x3ff)                       */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELC_Pos    (20UL)         /*!< REQ_SELC (Bit 20)                                     */
+ #define R_DMA_DMAC0_RSSEL_REQ_SELC_Msk    (0x3ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x3ff)                       */
+/* ======================================================  DMAC1_RSSEL  ====================================================== */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELA_Pos    (0UL)          /*!< REQ_SELA (Bit 0)                                      */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELA_Msk    (0x3ffUL)      /*!< REQ_SELA (Bitfield-Mask: 0x3ff)                       */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELB_Pos    (10UL)         /*!< REQ_SELB (Bit 10)                                     */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELB_Msk    (0xffc00UL)    /*!< REQ_SELB (Bitfield-Mask: 0x3ff)                       */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELC_Pos    (20UL)         /*!< REQ_SELC (Bit 20)                                     */
+ #define R_DMA_DMAC1_RSSEL_REQ_SELC_Msk    (0x3ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x3ff)                       */
+/* ======================================================  DMAC2_RSSEL  ====================================================== */
+ #define R_DMA_DMAC2_RSSEL_REQ_SELA_Pos    (0UL)          /*!< REQ_SELA (Bit 0)                                      */
+ #define R_DMA_DMAC2_RSSEL_REQ_SELA_Msk    (0x3ffUL)      /*!< REQ_SELA (Bitfield-Mask: 0x3ff)                       */
+ #define R_DMA_DMAC2_RSSEL_REQ_SELB_Pos    (10UL)         /*!< REQ_SELB (Bit 10)                                     */
+ #define R_DMA_DMAC2_RSSEL_REQ_SELB_Msk    (0xffc00UL)    /*!< REQ_SELB (Bitfield-Mask: 0x3ff)                       */
+ #define R_DMA_DMAC2_RSSEL_REQ_SELC_Pos    (20UL)         /*!< REQ_SELC (Bit 20)                                     */
+ #define R_DMA_DMAC2_RSSEL_REQ_SELC_Msk    (0x3ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x3ff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                       R_PORT_COMMON                                       ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  P  =========================================================== */
+ #define R_PORT_SRN_P_POUT_0_Pos      (0UL)      /*!< POUT_0 (Bit 0)                                        */
+ #define R_PORT_SRN_P_POUT_0_Msk      (0x1UL)    /*!< POUT_0 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_SRN_P_POUT_1_Pos      (1UL)      /*!< POUT_1 (Bit 1)                                        */
+ #define R_PORT_SRN_P_POUT_1_Msk      (0x2UL)    /*!< POUT_1 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_SRN_P_POUT_2_Pos      (2UL)      /*!< POUT_2 (Bit 2)                                        */
+ #define R_PORT_SRN_P_POUT_2_Msk      (0x4UL)    /*!< POUT_2 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_SRN_P_POUT_3_Pos      (3UL)      /*!< POUT_3 (Bit 3)                                        */
+ #define R_PORT_SRN_P_POUT_3_Msk      (0x8UL)    /*!< POUT_3 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_SRN_P_POUT_4_Pos      (4UL)      /*!< POUT_4 (Bit 4)                                        */
+ #define R_PORT_SRN_P_POUT_4_Msk      (0x10UL)   /*!< POUT_4 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_SRN_P_POUT_5_Pos      (5UL)      /*!< POUT_5 (Bit 5)                                        */
+ #define R_PORT_SRN_P_POUT_5_Msk      (0x20UL)   /*!< POUT_5 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_SRN_P_POUT_6_Pos      (6UL)      /*!< POUT_6 (Bit 6)                                        */
+ #define R_PORT_SRN_P_POUT_6_Msk      (0x40UL)   /*!< POUT_6 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_SRN_P_POUT_7_Pos      (7UL)      /*!< POUT_7 (Bit 7)                                        */
+ #define R_PORT_SRN_P_POUT_7_Msk      (0x80UL)   /*!< POUT_7 (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  PM  =========================================================== */
+ #define R_PORT_SRN_PM_PM0_Pos        (0UL)      /*!< PM0 (Bit 0)                                           */
+ #define R_PORT_SRN_PM_PM0_Msk        (0x3UL)    /*!< PM0 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_SRN_PM_PM1_Pos        (2UL)      /*!< PM1 (Bit 2)                                           */
+ #define R_PORT_SRN_PM_PM1_Msk        (0xcUL)    /*!< PM1 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_SRN_PM_PM2_Pos        (4UL)      /*!< PM2 (Bit 4)                                           */
+ #define R_PORT_SRN_PM_PM2_Msk        (0x30UL)   /*!< PM2 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_SRN_PM_PM3_Pos        (6UL)      /*!< PM3 (Bit 6)                                           */
+ #define R_PORT_SRN_PM_PM3_Msk        (0xc0UL)   /*!< PM3 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_SRN_PM_PM4_Pos        (8UL)      /*!< PM4 (Bit 8)                                           */
+ #define R_PORT_SRN_PM_PM4_Msk        (0x300UL)  /*!< PM4 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_SRN_PM_PM5_Pos        (10UL)     /*!< PM5 (Bit 10)                                          */
+ #define R_PORT_SRN_PM_PM5_Msk        (0xc00UL)  /*!< PM5 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_SRN_PM_PM6_Pos        (12UL)     /*!< PM6 (Bit 12)                                          */
+ #define R_PORT_SRN_PM_PM6_Msk        (0x3000UL) /*!< PM6 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_SRN_PM_PM7_Pos        (14UL)     /*!< PM7 (Bit 14)                                          */
+ #define R_PORT_SRN_PM_PM7_Msk        (0xc000UL) /*!< PM7 (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  PMC  ========================================================== */
+ #define R_PORT_SRN_PMC_PMC0_Pos      (0UL)      /*!< PMC0 (Bit 0)                                          */
+ #define R_PORT_SRN_PMC_PMC0_Msk      (0x1UL)    /*!< PMC0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PMC_PMC1_Pos      (1UL)      /*!< PMC1 (Bit 1)                                          */
+ #define R_PORT_SRN_PMC_PMC1_Msk      (0x2UL)    /*!< PMC1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PMC_PMC2_Pos      (2UL)      /*!< PMC2 (Bit 2)                                          */
+ #define R_PORT_SRN_PMC_PMC2_Msk      (0x4UL)    /*!< PMC2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PMC_PMC3_Pos      (3UL)      /*!< PMC3 (Bit 3)                                          */
+ #define R_PORT_SRN_PMC_PMC3_Msk      (0x8UL)    /*!< PMC3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PMC_PMC4_Pos      (4UL)      /*!< PMC4 (Bit 4)                                          */
+ #define R_PORT_SRN_PMC_PMC4_Msk      (0x10UL)   /*!< PMC4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PMC_PMC5_Pos      (5UL)      /*!< PMC5 (Bit 5)                                          */
+ #define R_PORT_SRN_PMC_PMC5_Msk      (0x20UL)   /*!< PMC5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PMC_PMC6_Pos      (6UL)      /*!< PMC6 (Bit 6)                                          */
+ #define R_PORT_SRN_PMC_PMC6_Msk      (0x40UL)   /*!< PMC6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PMC_PMC7_Pos      (7UL)      /*!< PMC7 (Bit 7)                                          */
+ #define R_PORT_SRN_PMC_PMC7_Msk      (0x80UL)   /*!< PMC7 (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  PIN  ========================================================== */
+ #define R_PORT_SRN_PIN_PIN0_Pos      (0UL)      /*!< PIN0 (Bit 0)                                          */
+ #define R_PORT_SRN_PIN_PIN0_Msk      (0x1UL)    /*!< PIN0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PIN_PIN1_Pos      (1UL)      /*!< PIN1 (Bit 1)                                          */
+ #define R_PORT_SRN_PIN_PIN1_Msk      (0x2UL)    /*!< PIN1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PIN_PIN2_Pos      (2UL)      /*!< PIN2 (Bit 2)                                          */
+ #define R_PORT_SRN_PIN_PIN2_Msk      (0x4UL)    /*!< PIN2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PIN_PIN3_Pos      (3UL)      /*!< PIN3 (Bit 3)                                          */
+ #define R_PORT_SRN_PIN_PIN3_Msk      (0x8UL)    /*!< PIN3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PIN_PIN4_Pos      (4UL)      /*!< PIN4 (Bit 4)                                          */
+ #define R_PORT_SRN_PIN_PIN4_Msk      (0x10UL)   /*!< PIN4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PIN_PIN5_Pos      (5UL)      /*!< PIN5 (Bit 5)                                          */
+ #define R_PORT_SRN_PIN_PIN5_Msk      (0x20UL)   /*!< PIN5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PIN_PIN6_Pos      (6UL)      /*!< PIN6 (Bit 6)                                          */
+ #define R_PORT_SRN_PIN_PIN6_Msk      (0x40UL)   /*!< PIN6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_SRN_PIN_PIN7_Pos      (7UL)      /*!< PIN7 (Bit 7)                                          */
+ #define R_PORT_SRN_PIN_PIN7_Msk      (0x80UL)   /*!< PIN7 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  RSELP  ========================================================= */
+ #define R_PORT_SRN_RSELP_RS0_Pos     (0UL)      /*!< RS0 (Bit 0)                                           */
+ #define R_PORT_SRN_RSELP_RS0_Msk     (0x1UL)    /*!< RS0 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_RSELP_RS1_Pos     (1UL)      /*!< RS1 (Bit 1)                                           */
+ #define R_PORT_SRN_RSELP_RS1_Msk     (0x2UL)    /*!< RS1 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_RSELP_RS2_Pos     (2UL)      /*!< RS2 (Bit 2)                                           */
+ #define R_PORT_SRN_RSELP_RS2_Msk     (0x4UL)    /*!< RS2 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_RSELP_RS3_Pos     (3UL)      /*!< RS3 (Bit 3)                                           */
+ #define R_PORT_SRN_RSELP_RS3_Msk     (0x8UL)    /*!< RS3 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_RSELP_RS4_Pos     (4UL)      /*!< RS4 (Bit 4)                                           */
+ #define R_PORT_SRN_RSELP_RS4_Msk     (0x10UL)   /*!< RS4 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_RSELP_RS5_Pos     (5UL)      /*!< RS5 (Bit 5)                                           */
+ #define R_PORT_SRN_RSELP_RS5_Msk     (0x20UL)   /*!< RS5 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_RSELP_RS6_Pos     (6UL)      /*!< RS6 (Bit 6)                                           */
+ #define R_PORT_SRN_RSELP_RS6_Msk     (0x40UL)   /*!< RS6 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_SRN_RSELP_RS7_Pos     (7UL)      /*!< RS7 (Bit 7)                                           */
+ #define R_PORT_SRN_RSELP_RS7_Msk     (0x80UL)   /*!< RS7 (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SLPORT  ========================================================= */
+ #define R_PORT_SRN_SLPORT_SL_Pos     (0UL)      /*!< SL (Bit 0)                                            */
+ #define R_PORT_SRN_SLPORT_SL_Msk     (0x3UL)    /*!< SL (Bitfield-Mask: 0x03)                              */
+/* ========================================================  SLRSELP  ======================================================== */
+ #define R_PORT_SRN_SLRSELP_SL_Pos    (0UL)      /*!< SL (Bit 0)                                            */
+ #define R_PORT_SRN_SLRSELP_SL_Msk    (0x3UL)    /*!< SL (Bitfield-Mask: 0x03)                              */
+/* =========================================================  SLPSR  ========================================================= */
+ #define R_PORT_SRN_SLPSR_SL_Pos      (0UL)      /*!< SL (Bit 0)                                            */
+ #define R_PORT_SRN_SLPSR_SL_Msk      (0x3UL)    /*!< SL (Bitfield-Mask: 0x03)                              */
+/* ========================================================  RSELPSR  ======================================================== */
+ #define R_PORT_SRN_RSELPSR_RS_Pos    (0UL)      /*!< RS (Bit 0)                                            */
+ #define R_PORT_SRN_RSELPSR_RS_Msk    (0x1UL)    /*!< RS (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                     R_PORT_NS_COMMON                                      ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  P  =========================================================== */
+ #define R_PORT_NSR_P_POUT_0_Pos                  (0UL)         /*!< POUT_0 (Bit 0)                                        */
+ #define R_PORT_NSR_P_POUT_0_Msk                  (0x1UL)       /*!< POUT_0 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_1_Pos                  (1UL)         /*!< POUT_1 (Bit 1)                                        */
+ #define R_PORT_NSR_P_POUT_1_Msk                  (0x2UL)       /*!< POUT_1 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_2_Pos                  (2UL)         /*!< POUT_2 (Bit 2)                                        */
+ #define R_PORT_NSR_P_POUT_2_Msk                  (0x4UL)       /*!< POUT_2 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_3_Pos                  (3UL)         /*!< POUT_3 (Bit 3)                                        */
+ #define R_PORT_NSR_P_POUT_3_Msk                  (0x8UL)       /*!< POUT_3 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_4_Pos                  (4UL)         /*!< POUT_4 (Bit 4)                                        */
+ #define R_PORT_NSR_P_POUT_4_Msk                  (0x10UL)      /*!< POUT_4 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_5_Pos                  (5UL)         /*!< POUT_5 (Bit 5)                                        */
+ #define R_PORT_NSR_P_POUT_5_Msk                  (0x20UL)      /*!< POUT_5 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_6_Pos                  (6UL)         /*!< POUT_6 (Bit 6)                                        */
+ #define R_PORT_NSR_P_POUT_6_Msk                  (0x40UL)      /*!< POUT_6 (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_P_POUT_7_Pos                  (7UL)         /*!< POUT_7 (Bit 7)                                        */
+ #define R_PORT_NSR_P_POUT_7_Msk                  (0x80UL)      /*!< POUT_7 (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  PM  =========================================================== */
+ #define R_PORT_NSR_PM_PM0_Pos                    (0UL)         /*!< PM0 (Bit 0)                                           */
+ #define R_PORT_NSR_PM_PM0_Msk                    (0x3UL)       /*!< PM0 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM1_Pos                    (2UL)         /*!< PM1 (Bit 2)                                           */
+ #define R_PORT_NSR_PM_PM1_Msk                    (0xcUL)       /*!< PM1 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM2_Pos                    (4UL)         /*!< PM2 (Bit 4)                                           */
+ #define R_PORT_NSR_PM_PM2_Msk                    (0x30UL)      /*!< PM2 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM3_Pos                    (6UL)         /*!< PM3 (Bit 6)                                           */
+ #define R_PORT_NSR_PM_PM3_Msk                    (0xc0UL)      /*!< PM3 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM4_Pos                    (8UL)         /*!< PM4 (Bit 8)                                           */
+ #define R_PORT_NSR_PM_PM4_Msk                    (0x300UL)     /*!< PM4 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM5_Pos                    (10UL)        /*!< PM5 (Bit 10)                                          */
+ #define R_PORT_NSR_PM_PM5_Msk                    (0xc00UL)     /*!< PM5 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM6_Pos                    (12UL)        /*!< PM6 (Bit 12)                                          */
+ #define R_PORT_NSR_PM_PM6_Msk                    (0x3000UL)    /*!< PM6 (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_PM_PM7_Pos                    (14UL)        /*!< PM7 (Bit 14)                                          */
+ #define R_PORT_NSR_PM_PM7_Msk                    (0xc000UL)    /*!< PM7 (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  PMC  ========================================================== */
+ #define R_PORT_NSR_PMC_PMC0_Pos                  (0UL)         /*!< PMC0 (Bit 0)                                          */
+ #define R_PORT_NSR_PMC_PMC0_Msk                  (0x1UL)       /*!< PMC0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC1_Pos                  (1UL)         /*!< PMC1 (Bit 1)                                          */
+ #define R_PORT_NSR_PMC_PMC1_Msk                  (0x2UL)       /*!< PMC1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC2_Pos                  (2UL)         /*!< PMC2 (Bit 2)                                          */
+ #define R_PORT_NSR_PMC_PMC2_Msk                  (0x4UL)       /*!< PMC2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC3_Pos                  (3UL)         /*!< PMC3 (Bit 3)                                          */
+ #define R_PORT_NSR_PMC_PMC3_Msk                  (0x8UL)       /*!< PMC3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC4_Pos                  (4UL)         /*!< PMC4 (Bit 4)                                          */
+ #define R_PORT_NSR_PMC_PMC4_Msk                  (0x10UL)      /*!< PMC4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC5_Pos                  (5UL)         /*!< PMC5 (Bit 5)                                          */
+ #define R_PORT_NSR_PMC_PMC5_Msk                  (0x20UL)      /*!< PMC5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC6_Pos                  (6UL)         /*!< PMC6 (Bit 6)                                          */
+ #define R_PORT_NSR_PMC_PMC6_Msk                  (0x40UL)      /*!< PMC6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PMC_PMC7_Pos                  (7UL)         /*!< PMC7 (Bit 7)                                          */
+ #define R_PORT_NSR_PMC_PMC7_Msk                  (0x80UL)      /*!< PMC7 (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  PIN  ========================================================== */
+ #define R_PORT_NSR_PIN_PIN0_Pos                  (0UL)         /*!< PIN0 (Bit 0)                                          */
+ #define R_PORT_NSR_PIN_PIN0_Msk                  (0x1UL)       /*!< PIN0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN1_Pos                  (1UL)         /*!< PIN1 (Bit 1)                                          */
+ #define R_PORT_NSR_PIN_PIN1_Msk                  (0x2UL)       /*!< PIN1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN2_Pos                  (2UL)         /*!< PIN2 (Bit 2)                                          */
+ #define R_PORT_NSR_PIN_PIN2_Msk                  (0x4UL)       /*!< PIN2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN3_Pos                  (3UL)         /*!< PIN3 (Bit 3)                                          */
+ #define R_PORT_NSR_PIN_PIN3_Msk                  (0x8UL)       /*!< PIN3 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN4_Pos                  (4UL)         /*!< PIN4 (Bit 4)                                          */
+ #define R_PORT_NSR_PIN_PIN4_Msk                  (0x10UL)      /*!< PIN4 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN5_Pos                  (5UL)         /*!< PIN5 (Bit 5)                                          */
+ #define R_PORT_NSR_PIN_PIN5_Msk                  (0x20UL)      /*!< PIN5 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN6_Pos                  (6UL)         /*!< PIN6 (Bit 6)                                          */
+ #define R_PORT_NSR_PIN_PIN6_Msk                  (0x40UL)      /*!< PIN6 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_PIN_PIN7_Pos                  (7UL)         /*!< PIN7 (Bit 7)                                          */
+ #define R_PORT_NSR_PIN_PIN7_Msk                  (0x80UL)      /*!< PIN7 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ELC_PGR  ======================================================== */
+ #define R_PORT_NSR_ELC_PGR_PG0_Pos               (0UL)         /*!< PG0 (Bit 0)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG0_Msk               (0x1UL)       /*!< PG0 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG1_Pos               (1UL)         /*!< PG1 (Bit 1)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG1_Msk               (0x2UL)       /*!< PG1 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG2_Pos               (2UL)         /*!< PG2 (Bit 2)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG2_Msk               (0x4UL)       /*!< PG2 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG3_Pos               (3UL)         /*!< PG3 (Bit 3)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG3_Msk               (0x8UL)       /*!< PG3 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG4_Pos               (4UL)         /*!< PG4 (Bit 4)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG4_Msk               (0x10UL)      /*!< PG4 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG5_Pos               (5UL)         /*!< PG5 (Bit 5)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG5_Msk               (0x20UL)      /*!< PG5 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG6_Pos               (6UL)         /*!< PG6 (Bit 6)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG6_Msk               (0x40UL)      /*!< PG6 (Bitfield-Mask: 0x01)                             */
+ #define R_PORT_NSR_ELC_PGR_PG7_Pos               (7UL)         /*!< PG7 (Bit 7)                                           */
+ #define R_PORT_NSR_ELC_PGR_PG7_Msk               (0x80UL)      /*!< PG7 (Bitfield-Mask: 0x01)                             */
+/* ========================================================  ELC_PGC  ======================================================== */
+ #define R_PORT_NSR_ELC_PGC_PGCI_Pos              (0UL)         /*!< PGCI (Bit 0)                                          */
+ #define R_PORT_NSR_ELC_PGC_PGCI_Msk              (0x3UL)       /*!< PGCI (Bitfield-Mask: 0x03)                            */
+ #define R_PORT_NSR_ELC_PGC_PGCOVE_Pos            (2UL)         /*!< PGCOVE (Bit 2)                                        */
+ #define R_PORT_NSR_ELC_PGC_PGCOVE_Msk            (0x4UL)       /*!< PGCOVE (Bitfield-Mask: 0x01)                          */
+ #define R_PORT_NSR_ELC_PGC_PGCO_Pos              (4UL)         /*!< PGCO (Bit 4)                                          */
+ #define R_PORT_NSR_ELC_PGC_PGCO_Msk              (0x70UL)      /*!< PGCO (Bitfield-Mask: 0x07)                            */
+/* ========================================================  ELC_PEL  ======================================================== */
+ #define R_PORT_NSR_ELC_PEL_PSB_Pos               (0UL)         /*!< PSB (Bit 0)                                           */
+ #define R_PORT_NSR_ELC_PEL_PSB_Msk               (0x7UL)       /*!< PSB (Bitfield-Mask: 0x07)                             */
+ #define R_PORT_NSR_ELC_PEL_PSP_Pos               (3UL)         /*!< PSP (Bit 3)                                           */
+ #define R_PORT_NSR_ELC_PEL_PSP_Msk               (0x18UL)      /*!< PSP (Bitfield-Mask: 0x03)                             */
+ #define R_PORT_NSR_ELC_PEL_PSM_Pos               (5UL)         /*!< PSM (Bit 5)                                           */
+ #define R_PORT_NSR_ELC_PEL_PSM_Msk               (0x60UL)      /*!< PSM (Bitfield-Mask: 0x03)                             */
+/* =======================================================  ELC_DPTC  ======================================================== */
+ #define R_PORT_NSR_ELC_DPTC_PTC0_Pos             (0UL)         /*!< PTC0 (Bit 0)                                          */
+ #define R_PORT_NSR_ELC_DPTC_PTC0_Msk             (0x1UL)       /*!< PTC0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_DPTC_PTC1_Pos             (1UL)         /*!< PTC1 (Bit 1)                                          */
+ #define R_PORT_NSR_ELC_DPTC_PTC1_Msk             (0x2UL)       /*!< PTC1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_DPTC_PTC2_Pos             (2UL)         /*!< PTC2 (Bit 2)                                          */
+ #define R_PORT_NSR_ELC_DPTC_PTC2_Msk             (0x4UL)       /*!< PTC2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_DPTC_PTC3_Pos             (3UL)         /*!< PTC3 (Bit 3)                                          */
+ #define R_PORT_NSR_ELC_DPTC_PTC3_Msk             (0x8UL)       /*!< PTC3 (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ELC_ELSR2  ======================================================= */
+ #define R_PORT_NSR_ELC_ELSR2_PEG1_Pos            (2UL)         /*!< PEG1 (Bit 2)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PEG1_Msk            (0x4UL)       /*!< PEG1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PEG2_Pos            (3UL)         /*!< PEG2 (Bit 3)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PEG2_Msk            (0x8UL)       /*!< PEG2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PES0_Pos            (4UL)         /*!< PES0 (Bit 4)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PES0_Msk            (0x10UL)      /*!< PES0 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PES1_Pos            (5UL)         /*!< PES1 (Bit 5)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PES1_Msk            (0x20UL)      /*!< PES1 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PES2_Pos            (6UL)         /*!< PES2 (Bit 6)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PES2_Msk            (0x40UL)      /*!< PES2 (Bitfield-Mask: 0x01)                            */
+ #define R_PORT_NSR_ELC_ELSR2_PES3_Pos            (7UL)         /*!< PES3 (Bit 7)                                          */
+ #define R_PORT_NSR_ELC_ELSR2_PES3_Msk            (0x80UL)      /*!< PES3 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SLPORT  ========================================================= */
+ #define R_PORT_NSR_SLPORT_SL_Pos                 (0UL)         /*!< SL (Bit 0)                                            */
+ #define R_PORT_NSR_SLPORT_SL_Msk                 (0x3UL)       /*!< SL (Bitfield-Mask: 0x03)                              */
+/* ======================================================  SLELC_PGRC  ======================================================= */
+ #define R_PORT_NSR_SLELC_PGRC_ELC_PGR1_SL_Pos    (0UL)         /*!< ELC_PGR1_SL (Bit 0)                                   */
+ #define R_PORT_NSR_SLELC_PGRC_ELC_PGR1_SL_Msk    (0x3UL)       /*!< ELC_PGR1_SL (Bitfield-Mask: 0x03)                     */
+ #define R_PORT_NSR_SLELC_PGRC_ELC_PGR2_SL_Pos    (8UL)         /*!< ELC_PGR2_SL (Bit 8)                                   */
+ #define R_PORT_NSR_SLELC_PGRC_ELC_PGR2_SL_Msk    (0x300UL)     /*!< ELC_PGR2_SL (Bitfield-Mask: 0x03)                     */
+ #define R_PORT_NSR_SLELC_PGRC_ELC_PGC1_SL_Pos    (16UL)        /*!< ELC_PGC1_SL (Bit 16)                                  */
+ #define R_PORT_NSR_SLELC_PGRC_ELC_PGC1_SL_Msk    (0x30000UL)   /*!< ELC_PGC1_SL (Bitfield-Mask: 0x03)                     */
+ #define R_PORT_NSR_SLELC_PGRC_ELC_PGC2_SL_Pos    (24UL)        /*!< ELC_PGC2_SL (Bit 24)                                  */
+ #define R_PORT_NSR_SLELC_PGRC_ELC_PGC2_SL_Msk    (0x3000000UL) /*!< ELC_PGC2_SL (Bitfield-Mask: 0x03)                     */
+/* ======================================================  SLELC_PDBF  ======================================================= */
+ #define R_PORT_NSR_SLELC_PDBF_ELC_PDBF_SL_Pos    (0UL)         /*!< ELC_PDBF_SL (Bit 0)                                   */
+ #define R_PORT_NSR_SLELC_PDBF_ELC_PDBF_SL_Msk    (0x3UL)       /*!< ELC_PDBF_SL (Bitfield-Mask: 0x03)                     */
+/* =======================================================  SLELC_PEL  ======================================================= */
+ #define R_PORT_NSR_SLELC_PEL_ELC_PEL0_SL_Pos     (0UL)         /*!< ELC_PEL0_SL (Bit 0)                                   */
+ #define R_PORT_NSR_SLELC_PEL_ELC_PEL0_SL_Msk     (0x3UL)       /*!< ELC_PEL0_SL (Bitfield-Mask: 0x03)                     */
+ #define R_PORT_NSR_SLELC_PEL_ELC_PEL1_SL_Pos     (8UL)         /*!< ELC_PEL1_SL (Bit 8)                                   */
+ #define R_PORT_NSR_SLELC_PEL_ELC_PEL1_SL_Msk     (0x300UL)     /*!< ELC_PEL1_SL (Bitfield-Mask: 0x03)                     */
+ #define R_PORT_NSR_SLELC_PEL_ELC_PEL2_SL_Pos     (16UL)        /*!< ELC_PEL2_SL (Bit 16)                                  */
+ #define R_PORT_NSR_SLELC_PEL_ELC_PEL2_SL_Msk     (0x30000UL)   /*!< ELC_PEL2_SL (Bitfield-Mask: 0x03)                     */
+ #define R_PORT_NSR_SLELC_PEL_ELC_PEL3_SL_Pos     (24UL)        /*!< ELC_PEL3_SL (Bit 24)                                  */
+ #define R_PORT_NSR_SLELC_PEL_ELC_PEL3_SL_Msk     (0x3000000UL) /*!< ELC_PEL3_SL (Bitfield-Mask: 0x03)                     */
+/* =======================================================  SLELC_DE  ======================================================== */
+ #define R_PORT_NSR_SLELC_DE_ELC_DPTC_SL_Pos      (0UL)         /*!< ELC_DPTC_SL (Bit 0)                                   */
+ #define R_PORT_NSR_SLELC_DE_ELC_DPTC_SL_Msk      (0x3UL)       /*!< ELC_DPTC_SL (Bitfield-Mask: 0x03)                     */
+ #define R_PORT_NSR_SLELC_DE_ELC_ELSR2_SL_Pos     (8UL)         /*!< ELC_ELSR2_SL (Bit 8)                                  */
+ #define R_PORT_NSR_SLELC_DE_ELC_ELSR2_SL_Msk     (0x300UL)     /*!< ELC_ELSR2_SL (Bitfield-Mask: 0x03)                    */
+/* ========================================================  SLPSRNS  ======================================================== */
+ #define R_PORT_NSR_SLPSRNS_SL_Pos                (0UL)         /*!< SL (Bit 0)                                            */
+ #define R_PORT_NSR_SLPSRNS_SL_Msk                (0x3UL)       /*!< SL (Bitfield-Mask: 0x03)                              */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DDRSS                                          ================ */
+/* =========================================================================================================================== */
+
+/* ================================================  DDR_MEMC_DENALI_CTL_00  ================================================= */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_00_start_Pos                                    (0UL)          /*!< start (Bit 0)                                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_00_start_Msk                                    (0x1UL)        /*!< start (Bitfield-Mask: 0x01)                           */
+/* ================================================  DDR_MEMC_DENALI_CTL_64  ================================================= */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_64_BSTLEN_Pos                                   (8UL)          /*!< BSTLEN (Bit 8)                                        */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_64_BSTLEN_Msk                                   (0x3f00UL)     /*!< BSTLEN (Bitfield-Mask: 0x3f)                          */
+/* ================================================  DDR_MEMC_DENALI_CTL_103  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_103_PWRUP_SREFRESH_EXIT_Pos                     (0UL)          /*!< PWRUP_SREFRESH_EXIT (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_103_PWRUP_SREFRESH_EXIT_Msk                     (0x1UL)        /*!< PWRUP_SREFRESH_EXIT (Bitfield-Mask: 0x01)         */
+/* ================================================  DDR_MEMC_DENALI_CTL_158  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_158_LPI_WAKEUP_EN_Pos                           (16UL)         /*!< LPI_WAKEUP_EN (Bit 16)                                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_158_LPI_WAKEUP_EN_Msk                           (0x3f0000UL)   /*!< LPI_WAKEUP_EN (Bitfield-Mask: 0x3f)                */
+/* ================================================  DDR_MEMC_DENALI_CTL_160  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_160_LP_AUTO_ENTRY_EN_Pos                        (24UL)         /*!< LP_AUTO_ENTRY_EN (Bit 24)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_160_LP_AUTO_ENTRY_EN_Msk                        (0xf000000UL)  /*!< LP_AUTO_ENTRY_EN (Bitfield-Mask: 0x0f)         */
+/* ================================================  DDR_MEMC_DENALI_CTL_167  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_167_PCPCS_PD_EN_Pos                             (8UL)          /*!< PCPCS_PD_EN (Bit 8)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_167_PCPCS_PD_EN_Msk                             (0x100UL)      /*!< PCPCS_PD_EN (Bitfield-Mask: 0x01)                     */
+/* ================================================  DDR_MEMC_DENALI_CTL_219  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_219_BIST_GO_Pos                                 (8UL)          /*!< BIST_GO (Bit 8)                                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_219_BIST_GO_Msk                                 (0x100UL)      /*!< BIST_GO (Bitfield-Mask: 0x01)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_219_ADDR_SPACE_Pos                              (24UL)         /*!< ADDR_SPACE (Bit 24)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_219_ADDR_SPACE_Msk                              (0x3f000000UL) /*!< ADDR_SPACE (Bitfield-Mask: 0x3f)                    */
+/* ================================================  DDR_MEMC_DENALI_CTL_220  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_220_BIST_DATA_CHECK_Pos                         (0UL)          /*!< BIST_DATA_CHECK (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_220_BIST_DATA_CHECK_Msk                         (0x1UL)        /*!< BIST_DATA_CHECK (Bitfield-Mask: 0x01)                 */
+/* ================================================  DDR_MEMC_DENALI_CTL_221  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_221_BIST_START_ADDRESS_Pos                      (0UL)          /*!< BIST_START_ADDRESS (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_221_BIST_START_ADDRESS_Msk                      (0xffffffffUL) /*!< BIST_START_ADDRESS (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_222  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_222_BIST_START_ADDRESS32_Pos                    (0UL)          /*!< BIST_START_ADDRESS32 (Bit 0)                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_222_BIST_START_ADDRESS32_Msk                    (0x1UL)        /*!< BIST_START_ADDRESS32 (Bitfield-Mask: 0x01)       */
+/* ================================================  DDR_MEMC_DENALI_CTL_225  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_225_BIST_TEST_MODE_Pos                          (0UL)          /*!< BIST_TEST_MODE (Bit 0)                                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_225_BIST_TEST_MODE_Msk                          (0x7UL)        /*!< BIST_TEST_MODE (Bitfield-Mask: 0x07)                  */
+/* ================================================  DDR_MEMC_DENALI_CTL_226  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_226_BIST_DATA_PATTERN0_Pos                      (0UL)          /*!< BIST_DATA_PATTERN0 (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_226_BIST_DATA_PATTERN0_Msk                      (0xffffffffUL) /*!< BIST_DATA_PATTERN0 (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_227  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_227_BIST_DATA_PATTERN1_Pos                      (0UL)          /*!< BIST_DATA_PATTERN1 (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_227_BIST_DATA_PATTERN1_Msk                      (0xffffffffUL) /*!< BIST_DATA_PATTERN1 (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_228  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_228_BIST_DATA_PATTERN2_Pos                      (0UL)          /*!< BIST_DATA_PATTERN2 (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_228_BIST_DATA_PATTERN2_Msk                      (0xffffffffUL) /*!< BIST_DATA_PATTERN2 (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_229  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_229_BIST_DATA_PATTERN3_Pos                      (0UL)          /*!< BIST_DATA_PATTERN3 (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_229_BIST_DATA_PATTERN3_Msk                      (0xffffffffUL) /*!< BIST_DATA_PATTERN3 (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_231  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_231_ECC_ENABLE_Pos                              (24UL)         /*!< ECC_ENABLE (Bit 24)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_231_ECC_ENABLE_Msk                              (0x3000000UL)  /*!< ECC_ENABLE (Bitfield-Mask: 0x03)                     */
+/* ================================================  DDR_MEMC_DENALI_CTL_232  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_232_FWC_Pos                                     (0UL)          /*!< FWC (Bit 0)                                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_232_FWC_Msk                                     (0x1UL)        /*!< FWC (Bitfield-Mask: 0x01)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_232_XOR_CHECK_BITS_Pos                          (8UL)          /*!< XOR_CHECK_BITS (Bit 8)                                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_232_XOR_CHECK_BITS_Msk                          (0xffff00UL)   /*!< XOR_CHECK_BITS (Bitfield-Mask: 0xffff)            */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_232_ECC_DISABLE_W_UC_ERR_Pos                    (24UL)         /*!< ECC_DISABLE_W_UC_ERR (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_232_ECC_DISABLE_W_UC_ERR_Msk                    (0x1000000UL)  /*!< ECC_DISABLE_W_UC_ERR (Bitfield-Mask: 0x01) */
+/* ================================================  DDR_MEMC_DENALI_CTL_233  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_233_ECC_WRITEBACK_EN_Pos                        (0UL)          /*!< ECC_WRITEBACK_EN (Bit 0)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_233_ECC_WRITEBACK_EN_Msk                        (0x1UL)        /*!< ECC_WRITEBACK_EN (Bitfield-Mask: 0x01)               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_233_INLINE_ECC_SAME_PAGE_Pos                    (8UL)          /*!< INLINE_ECC_SAME_PAGE (Bit 8)                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_233_INLINE_ECC_SAME_PAGE_Msk                    (0x100UL)      /*!< INLINE_ECC_SAME_PAGE (Bitfield-Mask: 0x01)     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_233_INLINE_ECC_BANK_OFFSET_Pos                  (16UL)         /*!< INLINE_ECC_BANK_OFFSET (Bit 16)                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_233_INLINE_ECC_BANK_OFFSET_Msk                  (0x70000UL)    /*!< INLINE_ECC_BANK_OFFSET (Bitfield-Mask: 0x07) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_233_ECC_READ_CACHING_EN_Pos                     (24UL)         /*!< ECC_READ_CACHING_EN (Bit 24)                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_233_ECC_READ_CACHING_EN_Msk                     (0x1000000UL)  /*!< ECC_READ_CACHING_EN (Bitfield-Mask: 0x01)   */
+/* ================================================  DDR_MEMC_DENALI_CTL_234  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_234_ECC_WRITE_COMBINING_EN_Pos                  (0UL)          /*!< ECC_WRITE_COMBINING_EN (Bit 0)                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_234_ECC_WRITE_COMBINING_EN_Msk                  (0x1UL)        /*!< ECC_WRITE_COMBINING_EN (Bitfield-Mask: 0x01)   */
+/* ================================================  DDR_MEMC_DENALI_CTL_235  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_235_ECC_U_ADDR_Pos                              (0UL)          /*!< ECC_U_ADDR (Bit 0)                                    */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_235_ECC_U_ADDR_Msk                              (0xffffffffUL) /*!< ECC_U_ADDR (Bitfield-Mask: 0xffffffff)              */
+/* ================================================  DDR_MEMC_DENALI_CTL_236  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_236_ECC_U_ADDR32_Pos                            (0UL)          /*!< ECC_U_ADDR32 (Bit 0)                                  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_236_ECC_U_ADDR32_Msk                            (0x1UL)        /*!< ECC_U_ADDR32 (Bitfield-Mask: 0x01)                    */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_236_ECC_U_SYND_Pos                              (8UL)          /*!< ECC_U_SYND (Bit 8)                                    */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_236_ECC_U_SYND_Msk                              (0xff00UL)     /*!< ECC_U_SYND (Bitfield-Mask: 0xff)                      */
+/* ================================================  DDR_MEMC_DENALI_CTL_237  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_237_ECC_U_DATA0_Pos                             (0UL)          /*!< ECC_U_DATA0 (Bit 0)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_237_ECC_U_DATA0_Msk                             (0xffffffffUL) /*!< ECC_U_DATA0 (Bitfield-Mask: 0xffffffff)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_238  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_238_ECC_U_DATA1_Pos                             (0UL)          /*!< ECC_U_DATA1 (Bit 0)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_238_ECC_U_DATA1_Msk                             (0xffffffffUL) /*!< ECC_U_DATA1 (Bitfield-Mask: 0xffffffff)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_239  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_239_ECC_C_ADDR_Pos                              (0UL)          /*!< ECC_C_ADDR (Bit 0)                                    */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_239_ECC_C_ADDR_Msk                              (0xffffffffUL) /*!< ECC_C_ADDR (Bitfield-Mask: 0xffffffff)              */
+/* ================================================  DDR_MEMC_DENALI_CTL_240  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_240_ECC_C_ADDR32_Pos                            (0UL)          /*!< ECC_C_ADDR32 (Bit 0)                                  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_240_ECC_C_ADDR32_Msk                            (0x1UL)        /*!< ECC_C_ADDR32 (Bitfield-Mask: 0x01)                    */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_240_ECC_C_SYND_Pos                              (8UL)          /*!< ECC_C_SYND (Bit 8)                                    */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_240_ECC_C_SYND_Msk                              (0xff00UL)     /*!< ECC_C_SYND (Bitfield-Mask: 0xff)                      */
+/* ================================================  DDR_MEMC_DENALI_CTL_241  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_241_ECC_C_DATA0_Pos                             (0UL)          /*!< ECC_C_DATA0 (Bit 0)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_241_ECC_C_DATA0_Msk                             (0xffffffffUL) /*!< ECC_C_DATA0 (Bitfield-Mask: 0xffffffff)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_242  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_242_ECC_C_DATA1_Pos                             (0UL)          /*!< ECC_C_DATA1 (Bit 0)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_242_ECC_C_DATA1_Msk                             (0xffffffffUL) /*!< ECC_C_DATA1 (Bitfield-Mask: 0xffffffff)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_244  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_244_RMODW_ECC_U_ADDR_Pos                        (0UL)          /*!< RMODW_ECC_U_ADDR (Bit 0)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_244_RMODW_ECC_U_ADDR_Msk                        (0xffffffffUL) /*!< RMODW_ECC_U_ADDR (Bitfield-Mask: 0xffffffff)  */
+/* ================================================  DDR_MEMC_DENALI_CTL_245  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_245_RMODW_ECC_U_ADDR32_Pos                      (0UL)          /*!< RMODW_ECC_U_ADDR32 (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_245_RMODW_ECC_U_ADDR32_Msk                      (0x1UL)        /*!< RMODW_ECC_U_ADDR32 (Bitfield-Mask: 0x01)           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_245_RMODW_ECC_U_SYND_Pos                        (8UL)          /*!< RMODW_ECC_U_SYND (Bit 8)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_245_RMODW_ECC_U_SYND_Msk                        (0xff00UL)     /*!< RMODW_ECC_U_SYND (Bitfield-Mask: 0xff)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_246  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_246_RMODW_ECC_U_DATA0_Pos                       (0UL)          /*!< RMODW_ECC_U_DATA0 (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_246_RMODW_ECC_U_DATA0_Msk                       (0xffffffffUL) /*!< RMODW_ECC_U_DATA0 (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_247  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_247_RMODW_ECC_U_DATA1_Pos                       (0UL)          /*!< RMODW_ECC_U_DATA1 (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_247_RMODW_ECC_U_DATA1_Msk                       (0xffffffffUL) /*!< RMODW_ECC_U_DATA1 (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_248  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_248_RMODW_ECC_C_ADDR_Pos                        (0UL)          /*!< RMODW_ECC_C_ADDR (Bit 0)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_248_RMODW_ECC_C_ADDR_Msk                        (0xffffffffUL) /*!< RMODW_ECC_C_ADDR (Bitfield-Mask: 0xffffffff)  */
+/* ================================================  DDR_MEMC_DENALI_CTL_249  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_249_RMODW_ECC_C_ADDR32_Pos                      (0UL)          /*!< RMODW_ECC_C_ADDR32 (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_249_RMODW_ECC_C_ADDR32_Msk                      (0x1UL)        /*!< RMODW_ECC_C_ADDR32 (Bitfield-Mask: 0x01)           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_249_RMODW_ECC_C_SYND_Pos                        (8UL)          /*!< RMODW_ECC_C_SYND (Bit 8)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_249_RMODW_ECC_C_SYND_Msk                        (0xff00UL)     /*!< RMODW_ECC_C_SYND (Bitfield-Mask: 0xff)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_250  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_250_RMODW_ECC_C_DATA0_Pos                       (0UL)          /*!< RMODW_ECC_C_DATA0 (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_250_RMODW_ECC_C_DATA0_Msk                       (0xffffffffUL) /*!< RMODW_ECC_C_DATA0 (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_251  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_251_RMODW_ECC_C_DATA1_Pos                       (0UL)          /*!< RMODW_ECC_C_DATA1 (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_251_RMODW_ECC_C_DATA1_Msk                       (0xffffffffUL) /*!< RMODW_ECC_C_DATA1 (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_269  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_269_ECC_SCRUB_START_Pos                         (16UL)         /*!< ECC_SCRUB_START (Bit 16)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_269_ECC_SCRUB_START_Msk                         (0x10000UL)    /*!< ECC_SCRUB_START (Bitfield-Mask: 0x01)             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_269_ECC_SCRUB_IN_PROGRESS_Pos                   (24UL)         /*!< ECC_SCRUB_IN_PROGRESS (Bit 24)                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_269_ECC_SCRUB_IN_PROGRESS_Msk                   (0x1000000UL)  /*!< ECC_SCRUB_IN_PROGRESS (Bitfield-Mask: 0x01) */
+/* ================================================  DDR_MEMC_DENALI_CTL_270  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_270_ECC_SCRUB_LEN_Pos                           (0UL)          /*!< ECC_SCRUB_LEN (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_270_ECC_SCRUB_LEN_Msk                           (0x1fffUL)     /*!< ECC_SCRUB_LEN (Bitfield-Mask: 0x1fff)                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_270_ECC_SCRUB_MODE_Pos                          (16UL)         /*!< ECC_SCRUB_MODE (Bit 16)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_270_ECC_SCRUB_MODE_Msk                          (0x10000UL)    /*!< ECC_SCRUB_MODE (Bitfield-Mask: 0x01)               */
+/* ================================================  DDR_MEMC_DENALI_CTL_271  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_271_ECC_SCRUB_INTERVAL_Pos                      (0UL)          /*!< ECC_SCRUB_INTERVAL (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_271_ECC_SCRUB_INTERVAL_Msk                      (0xffffUL)     /*!< ECC_SCRUB_INTERVAL (Bitfield-Mask: 0xffff)      */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_271_ECC_SCRUB_IDLE_CNT_Pos                      (16UL)         /*!< ECC_SCRUB_IDLE_CNT (Bit 16)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_271_ECC_SCRUB_IDLE_CNT_Msk                      (0xffff0000UL) /*!< ECC_SCRUB_IDLE_CNT (Bitfield-Mask: 0xffff)  */
+/* ================================================  DDR_MEMC_DENALI_CTL_272  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_272_ECC_SCRUB_START_ADDR_Pos                    (0UL)          /*!< ECC_SCRUB_START_ADDR (Bit 0)                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_272_ECC_SCRUB_START_ADDR_Msk                    (0xffffffffUL) /*!< ECC_SCRUB_START_ADDR (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_273  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_273_ECC_SCRUB_START_ADDR32_Pos                  (0UL)          /*!< ECC_SCRUB_START_ADDR32 (Bit 0)                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_273_ECC_SCRUB_START_ADDR32_Msk                  (0x1UL)        /*!< ECC_SCRUB_START_ADDR32 (Bitfield-Mask: 0x01)   */
+/* ================================================  DDR_MEMC_DENALI_CTL_274  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_274_ECC_SCRUB_END_ADDR_Pos                      (0UL)          /*!< ECC_SCRUB_END_ADDR (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_274_ECC_SCRUB_END_ADDR_Msk                      (0xffffffffUL) /*!< ECC_SCRUB_END_ADDR (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_275  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_275_ECC_SCRUB_END_ADDR32_Pos                    (0UL)          /*!< ECC_SCRUB_END_ADDR32 (Bit 0)                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_275_ECC_SCRUB_END_ADDR32_Msk                    (0x1UL)        /*!< ECC_SCRUB_END_ADDR32 (Bitfield-Mask: 0x01)       */
+/* ================================================  DDR_MEMC_DENALI_CTL_304  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_304_CS_VAL_UPPER_0_Pos                          (16UL)         /*!< CS_VAL_UPPER_0 (Bit 16)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_304_CS_VAL_UPPER_0_Msk                          (0xffff0000UL) /*!< CS_VAL_UPPER_0 (Bitfield-Mask: 0xffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_306  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_306_CS_VAL_UPPER_1_Pos                          (16UL)         /*!< CS_VAL_UPPER_1 (Bit 16)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_306_CS_VAL_UPPER_1_Msk                          (0xffff0000UL) /*!< CS_VAL_UPPER_1 (Bitfield-Mask: 0xffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_312  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_312_CS_MAP_Pos                                  (24UL)         /*!< CS_MAP (Bit 24)                                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_312_CS_MAP_Msk                                  (0x3000000UL)  /*!< CS_MAP (Bitfield-Mask: 0x03)                          */
+/* ================================================  DDR_MEMC_DENALI_CTL_313  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_313_MEM_DP_REDUCTION_Pos                        (0UL)          /*!< MEM_DP_REDUCTION (Bit 0)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_313_MEM_DP_REDUCTION_Msk                        (0x1UL)        /*!< MEM_DP_REDUCTION (Bitfield-Mask: 0x01)               */
+/* ================================================  DDR_MEMC_DENALI_CTL_318  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_318_device0_byte0_cs0_Pos                       (0UL)          /*!< device0_byte0_cs0 (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_318_device0_byte0_cs0_Msk                       (0xfUL)        /*!< device0_byte0_cs0 (Bitfield-Mask: 0x0f)             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_318_device1_byte0_cs0_Pos                       (8UL)          /*!< device1_byte0_cs0 (Bit 8)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_318_device1_byte0_cs0_Msk                       (0xf00UL)      /*!< device1_byte0_cs0 (Bitfield-Mask: 0x0f)           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_318_device2_byte0_cs0_Pos                       (16UL)         /*!< device2_byte0_cs0 (Bit 16)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_318_device2_byte0_cs0_Msk                       (0xf0000UL)    /*!< device2_byte0_cs0 (Bitfield-Mask: 0x0f)         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_318_device3_byte0_cs0_Pos                       (24UL)         /*!< device3_byte0_cs0 (Bit 24)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_318_device3_byte0_cs0_Msk                       (0xf000000UL)  /*!< device3_byte0_cs0 (Bitfield-Mask: 0x0f)       */
+/* ================================================  DDR_MEMC_DENALI_CTL_319  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_319_device0_byte0_cs1_Pos                       (0UL)          /*!< device0_byte0_cs1 (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_319_device0_byte0_cs1_Msk                       (0xfUL)        /*!< device0_byte0_cs1 (Bitfield-Mask: 0x0f)             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_319_device1_byte0_cs1_Pos                       (8UL)          /*!< device1_byte0_cs1 (Bit 8)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_319_device1_byte0_cs1_Msk                       (0xf00UL)      /*!< device1_byte0_cs1 (Bitfield-Mask: 0x0f)           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_319_device2_byte0_cs1_Pos                       (16UL)         /*!< device2_byte0_cs1 (Bit 16)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_319_device2_byte0_cs1_Msk                       (0xf0000UL)    /*!< device2_byte0_cs1 (Bitfield-Mask: 0x0f)         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_319_device3_byte0_cs1_Pos                       (24UL)         /*!< device3_byte0_cs1 (Bit 24)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_319_device3_byte0_cs1_Msk                       (0xf000000UL)  /*!< device3_byte0_cs1 (Bitfield-Mask: 0x0f)       */
+/* ================================================  DDR_MEMC_DENALI_CTL_326  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_326_INT_STATUS_MASTER_Pos                       (0UL)          /*!< INT_STATUS_MASTER (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_326_INT_STATUS_MASTER_Msk                       (0xffffffffUL) /*!< INT_STATUS_MASTER (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_327  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_327_INT_MASK_MASTER_Pos                         (0UL)          /*!< INT_MASK_MASTER (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_327_INT_MASK_MASTER_Msk                         (0xffffffffUL) /*!< INT_MASK_MASTER (Bitfield-Mask: 0xffffffff)    */
+/* ================================================  DDR_MEMC_DENALI_CTL_328  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_328_INT_STATUS_TIMEOUT_Pos                      (0UL)          /*!< INT_STATUS_TIMEOUT (Bit 0)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_328_INT_STATUS_TIMEOUT_Msk                      (0xffffffffUL) /*!< INT_STATUS_TIMEOUT (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_329  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_329_INT_STATUS_ECC_Pos                          (0UL)          /*!< INT_STATUS_ECC (Bit 0)                                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_329_INT_STATUS_ECC_Msk                          (0xffffffffUL) /*!< INT_STATUS_ECC (Bitfield-Mask: 0xffffffff)      */
+/* ================================================  DDR_MEMC_DENALI_CTL_330  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_330_INT_STATUS_LOWPOWER_Pos                     (0UL)          /*!< INT_STATUS_LOWPOWER (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_330_INT_STATUS_LOWPOWER_Msk                     (0xffffUL)     /*!< INT_STATUS_LOWPOWER (Bitfield-Mask: 0xffff)    */
+/* ================================================  DDR_MEMC_DENALI_CTL_332  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_332_INT_STATUS_TRAINING_Pos                     (0UL)          /*!< INT_STATUS_TRAINING (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_332_INT_STATUS_TRAINING_Msk                     (0xffffffffUL) /*!< INT_STATUS_TRAINING (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_333  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_333_INT_STATUS_USERIF_Pos                       (0UL)          /*!< INT_STATUS_USERIF (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_333_INT_STATUS_USERIF_Msk                       (0xffffffffUL) /*!< INT_STATUS_USERIF (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_334  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_334_INT_STATUS_MISC_Pos                         (0UL)          /*!< INT_STATUS_MISC (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_334_INT_STATUS_MISC_Msk                         (0xffffUL)     /*!< INT_STATUS_MISC (Bitfield-Mask: 0xffff)            */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_334_INT_STATUS_BIST_Pos                         (16UL)         /*!< INT_STATUS_BIST (Bit 16)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_334_INT_STATUS_BIST_Msk                         (0xff0000UL)   /*!< INT_STATUS_BIST (Bitfield-Mask: 0xff)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_335  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_335_INT_STATUS_DFI_Pos                          (0UL)          /*!< INT_STATUS_DFI (Bit 0)                                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_335_INT_STATUS_DFI_Msk                          (0xffUL)       /*!< INT_STATUS_DFI (Bitfield-Mask: 0xff)                  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_335_INT_STATUS_INIT_Pos                         (24UL)         /*!< INT_STATUS_INIT (Bit 24)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_335_INT_STATUS_INIT_Msk                         (0xff000000UL) /*!< INT_STATUS_INIT (Bitfield-Mask: 0xff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_336  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_336_INT_STATUS_MODE_Pos                         (0UL)          /*!< INT_STATUS_MODE (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_336_INT_STATUS_MODE_Msk                         (0xffUL)       /*!< INT_STATUS_MODE (Bitfield-Mask: 0xff)                */
+/* ================================================  DDR_MEMC_DENALI_CTL_337  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_337_INT_ACK_TIMEOUT_Pos                         (0UL)          /*!< INT_ACK_TIMEOUT (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_337_INT_ACK_TIMEOUT_Msk                         (0xffffffffUL) /*!< INT_ACK_TIMEOUT (Bitfield-Mask: 0xffffffff)    */
+/* ================================================  DDR_MEMC_DENALI_CTL_338  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_338_INT_ACK_ECC_Pos                             (0UL)          /*!< INT_ACK_ECC (Bit 0)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_338_INT_ACK_ECC_Msk                             (0xffffffffUL) /*!< INT_ACK_ECC (Bitfield-Mask: 0xffffffff)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_339  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_339_INT_ACK_LOWPOWER_Pos                        (0UL)          /*!< INT_ACK_LOWPOWER (Bit 0)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_339_INT_ACK_LOWPOWER_Msk                        (0xffffUL)     /*!< INT_ACK_LOWPOWER (Bitfield-Mask: 0xffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_341  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_341_INT_ACK_TRAINING_Pos                        (0UL)          /*!< INT_ACK_TRAINING (Bit 0)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_341_INT_ACK_TRAINING_Msk                        (0xffffffffUL) /*!< INT_ACK_TRAINING (Bitfield-Mask: 0xffffffff)  */
+/* ================================================  DDR_MEMC_DENALI_CTL_342  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_342_INT_ACK_USERIF_Pos                          (0UL)          /*!< INT_ACK_USERIF (Bit 0)                                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_342_INT_ACK_USERIF_Msk                          (0xffffffffUL) /*!< INT_ACK_USERIF (Bitfield-Mask: 0xffffffff)      */
+/* ================================================  DDR_MEMC_DENALI_CTL_343  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_343_INT_ACK_MISC_Pos                            (0UL)          /*!< INT_ACK_MISC (Bit 0)                                  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_343_INT_ACK_MISC_Msk                            (0xffffUL)     /*!< INT_ACK_MISC (Bitfield-Mask: 0xffff)                  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_343_INT_ACK_BIST_Pos                            (16UL)         /*!< INT_ACK_BIST (Bit 16)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_343_INT_ACK_BIST_Msk                            (0xff0000UL)   /*!< INT_ACK_BIST (Bitfield-Mask: 0xff)                  */
+/* ================================================  DDR_MEMC_DENALI_CTL_344  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_344_INT_ACK_DFI_Pos                             (0UL)          /*!< INT_ACK_DFI (Bit 0)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_344_INT_ACK_DFI_Msk                             (0xffUL)       /*!< INT_ACK_DFI (Bitfield-Mask: 0xff)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_344_INT_ACK_INIT_Pos                            (24UL)         /*!< INT_ACK_INIT (Bit 24)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_344_INT_ACK_INIT_Msk                            (0xff000000UL) /*!< INT_ACK_INIT (Bitfield-Mask: 0xff)                */
+/* ================================================  DDR_MEMC_DENALI_CTL_345  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_345_INT_ACK_MODE_Pos                            (0UL)          /*!< INT_ACK_MODE (Bit 0)                                  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_345_INT_ACK_MODE_Msk                            (0xffUL)       /*!< INT_ACK_MODE (Bitfield-Mask: 0xff)                    */
+/* ================================================  DDR_MEMC_DENALI_CTL_346  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_346_INT_MASK_TIMEOUT_Pos                        (0UL)          /*!< INT_MASK_TIMEOUT (Bit 0)                              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_346_INT_MASK_TIMEOUT_Msk                        (0xffffffffUL) /*!< INT_MASK_TIMEOUT (Bitfield-Mask: 0xffffffff)  */
+/* ================================================  DDR_MEMC_DENALI_CTL_347  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_347_INT_MASK_ECC_Pos                            (0UL)          /*!< INT_MASK_ECC (Bit 0)                                  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_347_INT_MASK_ECC_Msk                            (0xffffffffUL) /*!< INT_MASK_ECC (Bitfield-Mask: 0xffffffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_348  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_348_INT_MASK_LOWPOWER_Pos                       (0UL)          /*!< INT_MASK_LOWPOWER (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_348_INT_MASK_LOWPOWER_Msk                       (0xffffUL)     /*!< INT_MASK_LOWPOWER (Bitfield-Mask: 0xffff)        */
+/* ================================================  DDR_MEMC_DENALI_CTL_350  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_350_INT_MASK_TRAINING_Pos                       (0UL)          /*!< INT_MASK_TRAINING (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_350_INT_MASK_TRAINING_Msk                       (0xffffffffUL) /*!< INT_MASK_TRAINING (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_351  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_351_INT_MASK_USERIF_Pos                         (0UL)          /*!< INT_MASK_USERIF (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_351_INT_MASK_USERIF_Msk                         (0xffffffffUL) /*!< INT_MASK_USERIF (Bitfield-Mask: 0xffffffff)    */
+/* ================================================  DDR_MEMC_DENALI_CTL_352  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_352_INT_MASK_MISC_Pos                           (0UL)          /*!< INT_MASK_MISC (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_352_INT_MASK_MISC_Msk                           (0xffffUL)     /*!< INT_MASK_MISC (Bitfield-Mask: 0xffff)                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_352_INT_MASK_BIST_Pos                           (16UL)         /*!< INT_MASK_BIST (Bit 16)                                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_352_INT_MASK_BIST_Msk                           (0xff0000UL)   /*!< INT_MASK_BIST (Bitfield-Mask: 0xff)                */
+/* ================================================  DDR_MEMC_DENALI_CTL_353  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_353_INT_MASK_DFI_Pos                            (0UL)          /*!< INT_MASK_DFI (Bit 0)                                  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_353_INT_MASK_DFI_Msk                            (0xffUL)       /*!< INT_MASK_DFI (Bitfield-Mask: 0xff)                    */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_353_INT_MASK_INIT_Pos                           (24UL)         /*!< INT_MASK_INIT (Bit 24)                                */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_353_INT_MASK_INIT_Msk                           (0xff000000UL) /*!< INT_MASK_INIT (Bitfield-Mask: 0xff)              */
+/* ================================================  DDR_MEMC_DENALI_CTL_354  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_354_INT_MASK_MODE_Pos                           (0UL)          /*!< INT_MASK_MODE (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_354_INT_MASK_MODE_Msk                           (0xffUL)       /*!< INT_MASK_MODE (Bitfield-Mask: 0xff)                   */
+/* ================================================  DDR_MEMC_DENALI_CTL_355  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_355_OUT_OF_RANGE_ADDR_Pos                       (0UL)          /*!< OUT_OF_RANGE_ADDR (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_355_OUT_OF_RANGE_ADDR_Msk                       (0xffffffffUL) /*!< OUT_OF_RANGE_ADDR (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_356  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_ADDR32_Pos                     (0UL)          /*!< OUT_OF_RANGE_ADDR32 (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_ADDR32_Msk                     (0x1UL)        /*!< OUT_OF_RANGE_ADDR32 (Bitfield-Mask: 0x01)         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_LENGTH_Pos                     (8UL)          /*!< OUT_OF_RANGE_LENGTH (Bit 8)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_LENGTH_Msk                     (0x1fff00UL)   /*!< OUT_OF_RANGE_LENGTH (Bitfield-Mask: 0x1fff)  */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE0_Pos                      (24UL)         /*!< OUT_OF_RANGE_TYPE0 (Bit 24)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE0_Msk                      (0x1000000UL)  /*!< OUT_OF_RANGE_TYPE0 (Bitfield-Mask: 0x01)     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE1_Pos                      (25UL)         /*!< OUT_OF_RANGE_TYPE1 (Bit 25)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE1_Msk                      (0x2000000UL)  /*!< OUT_OF_RANGE_TYPE1 (Bitfield-Mask: 0x01)     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE2_Pos                      (26UL)         /*!< OUT_OF_RANGE_TYPE2 (Bit 26)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE2_Msk                      (0x4000000UL)  /*!< OUT_OF_RANGE_TYPE2 (Bitfield-Mask: 0x01)     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE3_Pos                      (27UL)         /*!< OUT_OF_RANGE_TYPE3 (Bit 27)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE3_Msk                      (0x8000000UL)  /*!< OUT_OF_RANGE_TYPE3 (Bitfield-Mask: 0x01)     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE4_Pos                      (28UL)         /*!< OUT_OF_RANGE_TYPE4 (Bit 28)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE4_Msk                      (0x10000000UL) /*!< OUT_OF_RANGE_TYPE4 (Bitfield-Mask: 0x01)    */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE5_Pos                      (29UL)         /*!< OUT_OF_RANGE_TYPE5 (Bit 29)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_356_OUT_OF_RANGE_TYPE5_Msk                      (0x20000000UL) /*!< OUT_OF_RANGE_TYPE5 (Bitfield-Mask: 0x01)    */
+/* ================================================  DDR_MEMC_DENALI_CTL_368  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_368_PORT_CMD_ERROR_ADDR_Pos                     (0UL)          /*!< PORT_CMD_ERROR_ADDR (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_368_PORT_CMD_ERROR_ADDR_Msk                     (0xffffffffUL) /*!< PORT_CMD_ERROR_ADDR (Bitfield-Mask: 0xffffffff) */
+/* ================================================  DDR_MEMC_DENALI_CTL_369  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_369_PORT_CMD_ERROR_ADDR32_Pos                   (0UL)          /*!< PORT_CMD_ERROR_ADDR32 (Bit 0)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_369_PORT_CMD_ERROR_ADDR32_Msk                   (0x1UL)        /*!< PORT_CMD_ERROR_ADDR32 (Bitfield-Mask: 0x01)     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_369_PORT_CMD_ERROR_TYPE_Pos                     (26UL)         /*!< PORT_CMD_ERROR_TYPE (Bit 26)                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_369_PORT_CMD_ERROR_TYPE_Msk                     (0x4000000UL)  /*!< PORT_CMD_ERROR_TYPE (Bitfield-Mask: 0x01)   */
+/* ================================================  DDR_MEMC_DENALI_CTL_376  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_376_R2R_DIFFCS_DLY_F0_Pos                       (16UL)         /*!< R2R_DIFFCS_DLY_F0 (Bit 16)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_376_R2R_DIFFCS_DLY_F0_Msk                       (0x1f0000UL)   /*!< R2R_DIFFCS_DLY_F0 (Bitfield-Mask: 0x1f)        */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_376_R2W_DIFFCS_DLY_F0_Pos                       (24UL)         /*!< R2W_DIFFCS_DLY_F0 (Bit 24)                           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_376_R2W_DIFFCS_DLY_F0_Msk                       (0x1f000000UL) /*!< R2W_DIFFCS_DLY_F0 (Bitfield-Mask: 0x1f)      */
+/* ================================================  DDR_MEMC_DENALI_CTL_377  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_377_W2R_DIFFCS_DLY_F0_Pos                       (0UL)          /*!< W2R_DIFFCS_DLY_F0 (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_377_W2R_DIFFCS_DLY_F0_Msk                       (0x1fUL)       /*!< W2R_DIFFCS_DLY_F0 (Bitfield-Mask: 0x1f)            */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_377_W2W_DIFFCS_DLY_F0_Pos                       (8UL)          /*!< W2W_DIFFCS_DLY_F0 (Bit 8)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_377_W2W_DIFFCS_DLY_F0_Msk                       (0x1f00UL)     /*!< W2W_DIFFCS_DLY_F0 (Bitfield-Mask: 0x1f)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_382  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_382_axi0_fixed_port_priority_enable_Pos         (24UL)         /*!< axi0_fixed_port_priority_enable (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_382_axi0_fixed_port_priority_enable_Msk         (0x1000000UL)  /*!< axi0_fixed_port_priority_enable (Bitfield-Mask: 0x01) */
+/* ================================================  DDR_MEMC_DENALI_CTL_383  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_383_axi0_r_priority_Pos                         (0UL)          /*!< axi0_r_priority (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_383_axi0_r_priority_Msk                         (0x7UL)        /*!< axi0_r_priority (Bitfield-Mask: 0x07)                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_383_axi0_w_priority_Pos                         (8UL)          /*!< axi0_w_priority (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_383_axi0_w_priority_Msk                         (0x700UL)      /*!< axi0_w_priority (Bitfield-Mask: 0x07)               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_383_axi1_fixed_port_priority_enable_Pos         (24UL)         /*!< axi1_fixed_port_priority_enable (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_383_axi1_fixed_port_priority_enable_Msk         (0x1000000UL)  /*!< axi1_fixed_port_priority_enable (Bitfield-Mask: 0x01) */
+/* ================================================  DDR_MEMC_DENALI_CTL_384  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_384_axi1_r_priority_Pos                         (0UL)          /*!< axi1_r_priority (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_384_axi1_r_priority_Msk                         (0x7UL)        /*!< axi1_r_priority (Bitfield-Mask: 0x07)                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_384_axi1_w_priority_Pos                         (8UL)          /*!< axi1_w_priority (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_384_axi1_w_priority_Msk                         (0x700UL)      /*!< axi1_w_priority (Bitfield-Mask: 0x07)               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_384_axi2_fixed_port_priority_enable_Pos         (24UL)         /*!< axi2_fixed_port_priority_enable (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_384_axi2_fixed_port_priority_enable_Msk         (0x1000000UL)  /*!< axi2_fixed_port_priority_enable (Bitfield-Mask: 0x01) */
+/* ================================================  DDR_MEMC_DENALI_CTL_385  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_385_axi2_r_priority_Pos                         (0UL)          /*!< axi2_r_priority (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_385_axi2_r_priority_Msk                         (0x7UL)        /*!< axi2_r_priority (Bitfield-Mask: 0x07)                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_385_axi2_w_priority_Pos                         (8UL)          /*!< axi2_w_priority (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_385_axi2_w_priority_Msk                         (0x700UL)      /*!< axi2_w_priority (Bitfield-Mask: 0x07)               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_385_axi3_fixed_port_priority_enable_Pos         (24UL)         /*!< axi3_fixed_port_priority_enable (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_385_axi3_fixed_port_priority_enable_Msk         (0x1000000UL)  /*!< axi3_fixed_port_priority_enable (Bitfield-Mask: 0x01) */
+/* ================================================  DDR_MEMC_DENALI_CTL_386  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_386_axi3_r_priority_Pos                         (0UL)          /*!< axi3_r_priority (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_386_axi3_r_priority_Msk                         (0x7UL)        /*!< axi3_r_priority (Bitfield-Mask: 0x07)                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_386_axi3_w_priority_Pos                         (8UL)          /*!< axi3_w_priority (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_386_axi3_w_priority_Msk                         (0x700UL)      /*!< axi3_w_priority (Bitfield-Mask: 0x07)               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_386_axi4_fixed_port_priority_enable_Pos         (24UL)         /*!< axi4_fixed_port_priority_enable (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_386_axi4_fixed_port_priority_enable_Msk         (0x1000000UL)  /*!< axi4_fixed_port_priority_enable (Bitfield-Mask: 0x01) */
+/* ================================================  DDR_MEMC_DENALI_CTL_387  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_387_axi4_r_priority_Pos                         (0UL)          /*!< axi4_r_priority (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_387_axi4_r_priority_Msk                         (0x7UL)        /*!< axi4_r_priority (Bitfield-Mask: 0x07)                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_387_axi4_w_priority_Pos                         (8UL)          /*!< axi4_w_priority (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_387_axi4_w_priority_Msk                         (0x700UL)      /*!< axi4_w_priority (Bitfield-Mask: 0x07)               */
+/* ================================================  DDR_MEMC_DENALI_CTL_395  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_395_PORT_ADDR_PROTECTION_EN_Pos                 (16UL)         /*!< PORT_ADDR_PROTECTION_EN (Bit 16)               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_395_PORT_ADDR_PROTECTION_EN_Msk                 (0x10000UL)    /*!< PORT_ADDR_PROTECTION_EN (Bitfield-Mask: 0x01) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_395_AXI0_ADDRESS_RANGE_ENABLE_Pos               (24UL)         /*!< AXI0_ADDRESS_RANGE_ENABLE (Bit 24)           */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_395_AXI0_ADDRESS_RANGE_ENABLE_Msk               (0x1000000UL)  /*!< AXI0_ADDRESS_RANGE_ENABLE (Bitfield-Mask: 0x01) */
+/* ================================================  DDR_MEMC_DENALI_CTL_396  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_396_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_396_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_397  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_397_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_397_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_397_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_397_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_400  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_400_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_400_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_401  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_401_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_401_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_401_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_401_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_404  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_404_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_404_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_405  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_405_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_405_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_405_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_405_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_408  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_408_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_408_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_409  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_409_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_409_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_409_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_409_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_412  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_412_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_412_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_413  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_413_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_413_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_413_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_413_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_416  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_416_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_416_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_417  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_417_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_417_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_417_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_417_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_420  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_420_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_420_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_421  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_421_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_421_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_421_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_421_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_424  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_424_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_424_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_425  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_425_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_425_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_425_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_425_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_428  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_428_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_428_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_429  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_429_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_429_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_429_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_429_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_432  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_432_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_432_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_433  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_433_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_433_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_433_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_433_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_436  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_436_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_436_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_437  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_437_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_437_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_437_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_437_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_440  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_440_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_440_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_441  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_441_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_441_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_441_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_441_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_444  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_444_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_444_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_445  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_445_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_445_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_445_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_445_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_448  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_448_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_448_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_449  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_449_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_449_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_449_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_449_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_452  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_452_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_452_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_453  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_453_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_453_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_453_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_453_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_456  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_456_AXI0_START_ADDR_Pos                         (0UL)          /*!< AXI0_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_456_AXI0_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI0_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_457  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_457_AXI0_END_ADDR_Pos                           (0UL)          /*!< AXI0_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_457_AXI0_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI0_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_457_AXI0_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI0_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_457_AXI0_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI0_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_460  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_460_AXI1_ADDRESS_RANGE_ENABLE_Pos               (0UL)          /*!< AXI1_ADDRESS_RANGE_ENABLE (Bit 0)             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_460_AXI1_ADDRESS_RANGE_ENABLE_Msk               (0x1UL)        /*!< AXI1_ADDRESS_RANGE_ENABLE (Bitfield-Mask: 0x01) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_460_AXI1_START_ADDR_Pos                         (8UL)          /*!< AXI1_START_ADDR (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_460_AXI1_START_ADDR_Msk                         (0x7ffff00UL)  /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)        */
+/* ================================================  DDR_MEMC_DENALI_CTL_461  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_461_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_461_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_461_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_461_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_464  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_464_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_464_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_465  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_465_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_465_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_465_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_465_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_468  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_468_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_468_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_469  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_469_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_469_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_469_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_469_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_472  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_472_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_472_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_473  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_473_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_473_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_473_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_473_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_476  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_476_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_476_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_477  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_477_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_477_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_477_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_477_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_480  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_480_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_480_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_481  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_481_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_481_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_481_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_481_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_484  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_484_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_484_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_485  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_485_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_485_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_485_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_485_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_488  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_488_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_488_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_489  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_489_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_489_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_489_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_489_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_492  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_492_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_492_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_493  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_493_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_493_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_493_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_493_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_496  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_496_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_496_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_497  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_497_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_497_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_497_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_497_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_500  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_500_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_500_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_501  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_501_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_501_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_501_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_501_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_504  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_504_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_504_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_505  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_505_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_505_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_505_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_505_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_508  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_508_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_508_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_509  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_509_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_509_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_509_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_509_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_512  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_512_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_512_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_513  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_513_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_513_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_513_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_513_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_516  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_516_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_516_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_517  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_517_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_517_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_517_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_517_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_520  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_520_AXI1_START_ADDR_Pos                         (0UL)          /*!< AXI1_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_520_AXI1_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI1_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_521  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_521_AXI1_END_ADDR_Pos                           (0UL)          /*!< AXI1_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_521_AXI1_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI1_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_521_AXI1_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI1_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_521_AXI1_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI1_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_524  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_524_AXI2_ADDRESS_RANGE_ENABLE_Pos               (0UL)          /*!< AXI2_ADDRESS_RANGE_ENABLE (Bit 0)             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_524_AXI2_ADDRESS_RANGE_ENABLE_Msk               (0x1UL)        /*!< AXI2_ADDRESS_RANGE_ENABLE (Bitfield-Mask: 0x01) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_524_AXI2_START_ADDR_Pos                         (8UL)          /*!< AXI2_START_ADDR (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_524_AXI2_START_ADDR_Msk                         (0x7ffff00UL)  /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)        */
+/* ================================================  DDR_MEMC_DENALI_CTL_525  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_525_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_525_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_525_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_525_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_528  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_528_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_528_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_529  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_529_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_529_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_529_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_529_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_532  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_532_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_532_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_533  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_533_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_533_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_533_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_533_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_536  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_536_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_536_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_537  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_537_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_537_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_537_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_537_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_540  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_540_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_540_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_541  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_541_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_541_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_541_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_541_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_544  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_544_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_544_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_545  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_545_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_545_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_545_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_545_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_548  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_548_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_548_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_549  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_549_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_549_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_549_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_549_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_552  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_552_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_552_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_553  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_553_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_553_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_553_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_553_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_556  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_556_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_556_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_557  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_557_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_557_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_557_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_557_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_560  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_560_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_560_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_561  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_561_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_561_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_561_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_561_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_564  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_564_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_564_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_565  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_565_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_565_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_565_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_565_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_568  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_568_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_568_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_569  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_569_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_569_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_569_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_569_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_572  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_572_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_572_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_573  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_573_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_573_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_573_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_573_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_576  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_576_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_576_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_577  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_577_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_577_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_577_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_577_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_580  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_580_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_580_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_581  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_581_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_581_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_581_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_581_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_584  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_584_AXI2_START_ADDR_Pos                         (0UL)          /*!< AXI2_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_584_AXI2_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI2_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_585  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_585_AXI2_END_ADDR_Pos                           (0UL)          /*!< AXI2_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_585_AXI2_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI2_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_585_AXI2_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI2_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_585_AXI2_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI2_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_588  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_588_AXI3_ADDRESS_RANGE_ENABLE_Pos               (0UL)          /*!< AXI3_ADDRESS_RANGE_ENABLE (Bit 0)             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_588_AXI3_ADDRESS_RANGE_ENABLE_Msk               (0x1UL)        /*!< AXI3_ADDRESS_RANGE_ENABLE (Bitfield-Mask: 0x01) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_588_AXI3_START_ADDR_Pos                         (8UL)          /*!< AXI3_START_ADDR (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_588_AXI3_START_ADDR_Msk                         (0x7ffff00UL)  /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)        */
+/* ================================================  DDR_MEMC_DENALI_CTL_589  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_589_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_589_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_589_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_589_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_592  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_592_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_592_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_593  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_593_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_593_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_593_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_593_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_596  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_596_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_596_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_597  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_597_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_597_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_597_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_597_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_600  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_600_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_600_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_601  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_601_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_601_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_601_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_601_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_604  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_604_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_604_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_605  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_605_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_605_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_605_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_605_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_608  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_608_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_608_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_609  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_609_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_609_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_609_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_609_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_612  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_612_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_612_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_613  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_613_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_613_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_613_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_613_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_616  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_616_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_616_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_617  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_617_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_617_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_617_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_617_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_620  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_620_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_620_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_621  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_621_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_621_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_621_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_621_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_624  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_624_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_624_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_625  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_625_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_625_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_625_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_625_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_628  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_628_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_628_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_629  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_629_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_629_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_629_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_629_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_632  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_632_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_632_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_633  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_633_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_633_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_633_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_633_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_636  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_636_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_636_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_637  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_637_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_637_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_637_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_637_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_640  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_640_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_640_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_641  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_641_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_641_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_641_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_641_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_644  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_644_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_644_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_645  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_645_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_645_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_645_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_645_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_648  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_648_AXI3_START_ADDR_Pos                         (0UL)          /*!< AXI3_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_648_AXI3_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI3_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_649  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_649_AXI3_END_ADDR_Pos                           (0UL)          /*!< AXI3_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_649_AXI3_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI3_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_649_AXI3_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI3_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_649_AXI3_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI3_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_652  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_652_AXI4_ADDRESS_RANGE_ENABLE_Pos               (0UL)          /*!< AXI4_ADDRESS_RANGE_ENABLE (Bit 0)             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_652_AXI4_ADDRESS_RANGE_ENABLE_Msk               (0x1UL)        /*!< AXI4_ADDRESS_RANGE_ENABLE (Bitfield-Mask: 0x01) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_652_AXI4_START_ADDR_Pos                         (8UL)          /*!< AXI4_START_ADDR (Bit 8)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_652_AXI4_START_ADDR_Msk                         (0x7ffff00UL)  /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)        */
+/* ================================================  DDR_MEMC_DENALI_CTL_653  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_653_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_653_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_653_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_653_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_656  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_656_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_656_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_657  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_657_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_657_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_657_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_657_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_660  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_660_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_660_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_661  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_661_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_661_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_661_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_661_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_664  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_664_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_664_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_665  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_665_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_665_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_665_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_665_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_668  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_668_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_668_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_669  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_669_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_669_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_669_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_669_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_672  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_672_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_672_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_673  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_673_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_673_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_673_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_673_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_676  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_676_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_676_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_677  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_677_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_677_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_677_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_677_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_680  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_680_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_680_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_681  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_681_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_681_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_681_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_681_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_684  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_684_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_684_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_685  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_685_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_685_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_685_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_685_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_688  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_688_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_688_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_689  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_689_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_689_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_689_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_689_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_692  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_692_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_692_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_693  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_693_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_693_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_693_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_693_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_696  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_696_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_696_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_697  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_697_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_697_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_697_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_697_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_700  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_700_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_700_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_701  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_701_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_701_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_701_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_701_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_704  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_704_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_704_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_705  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_705_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_705_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_705_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_705_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_708  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_708_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_708_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_709  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_709_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_709_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_709_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_709_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_712  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_712_AXI4_START_ADDR_Pos                         (0UL)          /*!< AXI4_START_ADDR (Bit 0)                               */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_712_AXI4_START_ADDR_Msk                         (0x7ffffUL)    /*!< AXI4_START_ADDR (Bitfield-Mask: 0x7ffff)          */
+/* ================================================  DDR_MEMC_DENALI_CTL_713  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_713_AXI4_END_ADDR_Pos                           (0UL)          /*!< AXI4_END_ADDR (Bit 0)                                 */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_713_AXI4_END_ADDR_Msk                           (0x7ffffUL)    /*!< AXI4_END_ADDR (Bitfield-Mask: 0x7ffff)              */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_713_AXI4_RANGE_PROT_BITS_Pos                    (24UL)         /*!< AXI4_RANGE_PROT_BITS (Bit 24)                     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_713_AXI4_RANGE_PROT_BITS_Msk                    (0x3000000UL)  /*!< AXI4_RANGE_PROT_BITS (Bitfield-Mask: 0x03) */
+/* ================================================  DDR_MEMC_DENALI_CTL_716  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_716_weighted_round_robin_latency_control_Pos    (0UL)          /*!< weighted_round_robin_latency_control (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_716_weighted_round_robin_latency_control_Msk    (0x1UL)        /*!< weighted_round_robin_latency_control (Bitfield-Mask: 0x01) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_716_weighted_round_robin_weight_sharing_Pos     (8UL)          /*!< weighted_round_robin_weight_sharing (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_716_weighted_round_robin_weight_sharing_Msk     (0x300UL)      /*!< weighted_round_robin_weight_sharing (Bitfield-Mask: 0x03) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_716_wrr_param_value_err_Pos                     (16UL)         /*!< wrr_param_value_err (Bit 16)                       */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_716_wrr_param_value_err_Msk                     (0xf0000UL)    /*!< wrr_param_value_err (Bitfield-Mask: 0x0f)     */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_716_axi0_priority0_relative_priority_Pos        (24UL)         /*!< axi0_priority0_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_716_axi0_priority0_relative_priority_Msk        (0xf000000UL)  /*!< axi0_priority0_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_717  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_717_axi0_priority1_relative_priority_Pos        (0UL)          /*!< axi0_priority1_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_717_axi0_priority1_relative_priority_Msk        (0xfUL)        /*!< axi0_priority1_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_717_axi0_priority2_relative_priority_Pos        (8UL)          /*!< axi0_priority2_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_717_axi0_priority2_relative_priority_Msk        (0xf00UL)      /*!< axi0_priority2_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_717_axi0_priority3_relative_priority_Pos        (16UL)         /*!< axi0_priority3_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_717_axi0_priority3_relative_priority_Msk        (0xf0000UL)    /*!< axi0_priority3_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_717_axi0_priority4_relative_priority_Pos        (24UL)         /*!< axi0_priority4_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_717_axi0_priority4_relative_priority_Msk        (0xf000000UL)  /*!< axi0_priority4_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_718  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_718_axi0_priority5_relative_priority_Pos        (0UL)          /*!< axi0_priority5_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_718_axi0_priority5_relative_priority_Msk        (0xfUL)        /*!< axi0_priority5_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_718_axi0_priority6_relative_priority_Pos        (8UL)          /*!< axi0_priority6_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_718_axi0_priority6_relative_priority_Msk        (0xf00UL)      /*!< axi0_priority6_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_718_axi0_priority7_relative_priority_Pos        (16UL)         /*!< axi0_priority7_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_718_axi0_priority7_relative_priority_Msk        (0xf0000UL)    /*!< axi0_priority7_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_718_axi0_port_ordering_Pos                      (24UL)         /*!< axi0_port_ordering (Bit 24)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_718_axi0_port_ordering_Msk                      (0x7000000UL)  /*!< axi0_port_ordering (Bitfield-Mask: 0x07)     */
+/* ================================================  DDR_MEMC_DENALI_CTL_719  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_719_axi0_priority_relax_Pos                     (0UL)          /*!< axi0_priority_relax (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_719_axi0_priority_relax_Msk                     (0x3ffUL)      /*!< axi0_priority_relax (Bitfield-Mask: 0x3ff)      */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_719_axi1_priority0_relative_priority_Pos        (16UL)         /*!< axi1_priority0_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_719_axi1_priority0_relative_priority_Msk        (0xf0000UL)    /*!< axi1_priority0_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_719_axi1_priority1_relative_priority_Pos        (24UL)         /*!< axi1_priority1_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_719_axi1_priority1_relative_priority_Msk        (0xf000000UL)  /*!< axi1_priority1_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_720  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_720_axi1_priority2_relative_priority_Pos        (0UL)          /*!< axi1_priority2_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_720_axi1_priority2_relative_priority_Msk        (0xfUL)        /*!< axi1_priority2_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_720_axi1_priority3_relative_priority_Pos        (8UL)          /*!< axi1_priority3_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_720_axi1_priority3_relative_priority_Msk        (0xf00UL)      /*!< axi1_priority3_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_720_axi1_priority4_relative_priority_Pos        (16UL)         /*!< axi1_priority4_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_720_axi1_priority4_relative_priority_Msk        (0xf0000UL)    /*!< axi1_priority4_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_720_axi1_priority5_relative_priority_Pos        (24UL)         /*!< axi1_priority5_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_720_axi1_priority5_relative_priority_Msk        (0xf000000UL)  /*!< axi1_priority5_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_721  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_721_axi1_priority6_relative_priority_Pos        (0UL)          /*!< axi1_priority6_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_721_axi1_priority6_relative_priority_Msk        (0xfUL)        /*!< axi1_priority6_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_721_axi1_priority7_relative_priority_Pos        (8UL)          /*!< axi1_priority7_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_721_axi1_priority7_relative_priority_Msk        (0xf00UL)      /*!< axi1_priority7_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_721_axi1_port_ordering_Pos                      (16UL)         /*!< axi1_port_ordering (Bit 16)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_721_axi1_port_ordering_Msk                      (0x70000UL)    /*!< axi1_port_ordering (Bitfield-Mask: 0x07)       */
+/* ================================================  DDR_MEMC_DENALI_CTL_722  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_722_axi1_priority_relax_Pos                     (0UL)          /*!< axi1_priority_relax (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_722_axi1_priority_relax_Msk                     (0x3ffUL)      /*!< axi1_priority_relax (Bitfield-Mask: 0x3ff)      */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_722_axi2_priority0_relative_priority_Pos        (16UL)         /*!< axi2_priority0_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_722_axi2_priority0_relative_priority_Msk        (0xf0000UL)    /*!< axi2_priority0_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_722_axi2_priority1_relative_priority_Pos        (24UL)         /*!< axi2_priority1_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_722_axi2_priority1_relative_priority_Msk        (0xf000000UL)  /*!< axi2_priority1_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_723  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_723_axi2_priority2_relative_priority_Pos        (0UL)          /*!< axi2_priority2_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_723_axi2_priority2_relative_priority_Msk        (0xfUL)        /*!< axi2_priority2_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_723_axi2_priority3_relative_priority_Pos        (8UL)          /*!< axi2_priority3_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_723_axi2_priority3_relative_priority_Msk        (0xf00UL)      /*!< axi2_priority3_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_723_axi2_priority4_relative_priority_Pos        (16UL)         /*!< axi2_priority4_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_723_axi2_priority4_relative_priority_Msk        (0xf0000UL)    /*!< axi2_priority4_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_723_axi2_priority5_relative_priority_Pos        (24UL)         /*!< axi2_priority5_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_723_axi2_priority5_relative_priority_Msk        (0xf000000UL)  /*!< axi2_priority5_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_724  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_724_axi2_priority6_relative_priority_Pos        (0UL)          /*!< axi2_priority6_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_724_axi2_priority6_relative_priority_Msk        (0xfUL)        /*!< axi2_priority6_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_724_axi2_priority7_relative_priority_Pos        (8UL)          /*!< axi2_priority7_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_724_axi2_priority7_relative_priority_Msk        (0xf00UL)      /*!< axi2_priority7_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_724_axi2_port_ordering_Pos                      (16UL)         /*!< axi2_port_ordering (Bit 16)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_724_axi2_port_ordering_Msk                      (0x70000UL)    /*!< axi2_port_ordering (Bitfield-Mask: 0x07)       */
+/* ================================================  DDR_MEMC_DENALI_CTL_725  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_725_axi2_priority_relax_Pos                     (0UL)          /*!< axi2_priority_relax (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_725_axi2_priority_relax_Msk                     (0x3ffUL)      /*!< axi2_priority_relax (Bitfield-Mask: 0x3ff)      */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_725_axi3_priority0_relative_priority_Pos        (16UL)         /*!< axi3_priority0_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_725_axi3_priority0_relative_priority_Msk        (0xf0000UL)    /*!< axi3_priority0_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_725_axi3_priority1_relative_priority_Pos        (24UL)         /*!< axi3_priority1_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_725_axi3_priority1_relative_priority_Msk        (0xf000000UL)  /*!< axi3_priority1_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_726  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_726_axi3_priority2_relative_priority_Pos        (0UL)          /*!< axi3_priority2_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_726_axi3_priority2_relative_priority_Msk        (0xfUL)        /*!< axi3_priority2_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_726_axi3_priority3_relative_priority_Pos        (8UL)          /*!< axi3_priority3_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_726_axi3_priority3_relative_priority_Msk        (0xf00UL)      /*!< axi3_priority3_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_726_axi3_priority4_relative_priority_Pos        (16UL)         /*!< axi3_priority4_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_726_axi3_priority4_relative_priority_Msk        (0xf0000UL)    /*!< axi3_priority4_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_726_axi3_priority5_relative_priority_Pos        (24UL)         /*!< axi3_priority5_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_726_axi3_priority5_relative_priority_Msk        (0xf000000UL)  /*!< axi3_priority5_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_727  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_727_axi3_priority6_relative_priority_Pos        (0UL)          /*!< axi3_priority6_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_727_axi3_priority6_relative_priority_Msk        (0xfUL)        /*!< axi3_priority6_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_727_axi3_priority7_relative_priority_Pos        (8UL)          /*!< axi3_priority7_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_727_axi3_priority7_relative_priority_Msk        (0xf00UL)      /*!< axi3_priority7_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_727_axi3_port_ordering_Pos                      (16UL)         /*!< axi3_port_ordering (Bit 16)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_727_axi3_port_ordering_Msk                      (0x70000UL)    /*!< axi3_port_ordering (Bitfield-Mask: 0x07)       */
+/* ================================================  DDR_MEMC_DENALI_CTL_728  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_728_axi3_priority_relax_Pos                     (0UL)          /*!< axi3_priority_relax (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_728_axi3_priority_relax_Msk                     (0x3ffUL)      /*!< axi3_priority_relax (Bitfield-Mask: 0x3ff)      */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_728_axi4_priority0_relative_priority_Pos        (16UL)         /*!< axi4_priority0_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_728_axi4_priority0_relative_priority_Msk        (0xf0000UL)    /*!< axi4_priority0_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_728_axi4_priority1_relative_priority_Pos        (24UL)         /*!< axi4_priority1_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_728_axi4_priority1_relative_priority_Msk        (0xf000000UL)  /*!< axi4_priority1_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_729  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_729_axi4_priority2_relative_priority_Pos        (0UL)          /*!< axi4_priority2_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_729_axi4_priority2_relative_priority_Msk        (0xfUL)        /*!< axi4_priority2_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_729_axi4_priority3_relative_priority_Pos        (8UL)          /*!< axi4_priority3_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_729_axi4_priority3_relative_priority_Msk        (0xf00UL)      /*!< axi4_priority3_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_729_axi4_priority4_relative_priority_Pos        (16UL)         /*!< axi4_priority4_relative_priority (Bit 16) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_729_axi4_priority4_relative_priority_Msk        (0xf0000UL)    /*!< axi4_priority4_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_729_axi4_priority5_relative_priority_Pos        (24UL)         /*!< axi4_priority5_relative_priority (Bit 24) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_729_axi4_priority5_relative_priority_Msk        (0xf000000UL)  /*!< axi4_priority5_relative_priority (Bitfield-Mask: 0x0f) */
+/* ================================================  DDR_MEMC_DENALI_CTL_730  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_730_axi4_priority6_relative_priority_Pos        (0UL)          /*!< axi4_priority6_relative_priority (Bit 0) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_730_axi4_priority6_relative_priority_Msk        (0xfUL)        /*!< axi4_priority6_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_730_axi4_priority7_relative_priority_Pos        (8UL)          /*!< axi4_priority7_relative_priority (Bit 8) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_730_axi4_priority7_relative_priority_Msk        (0xf00UL)      /*!< axi4_priority7_relative_priority (Bitfield-Mask: 0x0f) */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_730_axi4_port_ordering_Pos                      (16UL)         /*!< axi4_port_ordering (Bit 16)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_730_axi4_port_ordering_Msk                      (0x70000UL)    /*!< axi4_port_ordering (Bitfield-Mask: 0x07)       */
+/* ================================================  DDR_MEMC_DENALI_CTL_731  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_731_axi4_priority_relax_Pos                     (0UL)          /*!< axi4_priority_relax (Bit 0)                         */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_731_axi4_priority_relax_Msk                     (0x3ffUL)      /*!< axi4_priority_relax (Bitfield-Mask: 0x3ff)      */
+/* ================================================  DDR_MEMC_DENALI_CTL_732  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_732_TDFI_PHY_RDLAT_F0_Pos                       (0UL)          /*!< TDFI_PHY_RDLAT_F0 (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_732_TDFI_PHY_RDLAT_F0_Msk                       (0x7fUL)       /*!< TDFI_PHY_RDLAT_F0 (Bitfield-Mask: 0x7f)            */
+/* ================================================  DDR_MEMC_DENALI_CTL_761  ================================================ */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_761_TDFI_WRDATA_Pos                             (8UL)          /*!< TDFI_WRDATA (Bit 8)                                   */
+ #define R_DDRSS_DDR_MEMC_DENALI_CTL_761_TDFI_WRDATA_Msk                             (0xff00UL)     /*!< TDFI_WRDATA (Bitfield-Mask: 0xff)                     */
+/* ===================================================  DDR_MEMC_MCAR_CTL  =================================================== */
+ #define R_DDRSS_DDR_MEMC_MCAR_CTL_block_fm_norm_req_Pos                             (0UL)          /*!< block_fm_norm_req (Bit 0)                             */
+ #define R_DDRSS_DDR_MEMC_MCAR_CTL_block_fm_norm_req_Msk                             (0x1UL)        /*!< block_fm_norm_req (Bitfield-Mask: 0x01)               */
+ #define R_DDRSS_DDR_MEMC_MCAR_CTL_set_axctl_Pos                                     (8UL)          /*!< set_axctl (Bit 8)                                     */
+ #define R_DDRSS_DDR_MEMC_MCAR_CTL_set_axctl_Msk                                     (0x100UL)      /*!< set_axctl (Bitfield-Mask: 0x01)                       */
+ #define R_DDRSS_DDR_MEMC_MCAR_CTL_dfi_init_start_Pos                                (16UL)         /*!< dfi_init_start (Bit 16)                               */
+ #define R_DDRSS_DDR_MEMC_MCAR_CTL_dfi_init_start_Msk                                (0x10000UL)    /*!< dfi_init_start (Bitfield-Mask: 0x01)                  */
+/* ===================================================  DDR_MEMC_MCAR_MON  =================================================== */
+ #define R_DDRSS_DDR_MEMC_MCAR_MON_port_busy_Pos                                     (0UL)          /*!< port_busy (Bit 0)                                     */
+ #define R_DDRSS_DDR_MEMC_MCAR_MON_port_busy_Msk                                     (0x1fUL)       /*!< port_busy (Bitfield-Mask: 0x1f)                       */
+ #define R_DDRSS_DDR_MEMC_MCAR_MON_q_almost_full_Pos                                 (16UL)         /*!< q_almost_full (Bit 16)                                */
+ #define R_DDRSS_DDR_MEMC_MCAR_MON_q_almost_full_Msk                                 (0x10000UL)    /*!< q_almost_full (Bitfield-Mask: 0x01)                   */
+ #define R_DDRSS_DDR_MEMC_MCAR_MON_refresh_in_process_Pos                            (17UL)         /*!< refresh_in_process (Bit 17)                           */
+ #define R_DDRSS_DDR_MEMC_MCAR_MON_refresh_in_process_Msk                            (0x20000UL)    /*!< refresh_in_process (Bitfield-Mask: 0x01)             */
+/* ==================================================  DDR_MEMC_MCAR_AXCTL  ================================================== */
+ #define R_DDRSS_DDR_MEMC_MCAR_AXCTL_axi0_awcobuf_Pos                                (8UL)          /*!< axi0_awcobuf (Bit 8)                                  */
+ #define R_DDRSS_DDR_MEMC_MCAR_AXCTL_axi0_awcobuf_Msk                                (0x100UL)      /*!< axi0_awcobuf (Bitfield-Mask: 0x01)                    */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT10_0                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  GTWP  ========================================================== */
+ #define R_GPT10_0_GTWP_WP_Pos              (0UL)          /*!< WP (Bit 0)                                            */
+ #define R_GPT10_0_GTWP_WP_Msk              (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
+ #define R_GPT10_0_GTWP_STRWP_Pos           (1UL)          /*!< STRWP (Bit 1)                                         */
+ #define R_GPT10_0_GTWP_STRWP_Msk           (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTWP_STPWP_Pos           (2UL)          /*!< STPWP (Bit 2)                                         */
+ #define R_GPT10_0_GTWP_STPWP_Msk           (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTWP_CLRWP_Pos           (3UL)          /*!< CLRWP (Bit 3)                                         */
+ #define R_GPT10_0_GTWP_CLRWP_Msk           (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTWP_CMNWP_Pos           (4UL)          /*!< CMNWP (Bit 4)                                         */
+ #define R_GPT10_0_GTWP_CMNWP_Msk           (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTWP_PRKEY_Pos           (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_GPT10_0_GTWP_PRKEY_Msk           (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+/* =========================================================  GTSTR  ========================================================= */
+ #define R_GPT10_0_GTSTR_CSTRT0_Pos         (0UL)          /*!< CSTRT0 (Bit 0)                                        */
+ #define R_GPT10_0_GTSTR_CSTRT0_Msk         (0x1UL)        /*!< CSTRT0 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTR_CSTRT1_Pos         (1UL)          /*!< CSTRT1 (Bit 1)                                        */
+ #define R_GPT10_0_GTSTR_CSTRT1_Msk         (0x2UL)        /*!< CSTRT1 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTR_CSTRT2_Pos         (2UL)          /*!< CSTRT2 (Bit 2)                                        */
+ #define R_GPT10_0_GTSTR_CSTRT2_Msk         (0x4UL)        /*!< CSTRT2 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTR_CSTRT3_Pos         (3UL)          /*!< CSTRT3 (Bit 3)                                        */
+ #define R_GPT10_0_GTSTR_CSTRT3_Msk         (0x8UL)        /*!< CSTRT3 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTR_CSTRT4_Pos         (4UL)          /*!< CSTRT4 (Bit 4)                                        */
+ #define R_GPT10_0_GTSTR_CSTRT4_Msk         (0x10UL)       /*!< CSTRT4 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTR_CSTRT5_Pos         (5UL)          /*!< CSTRT5 (Bit 5)                                        */
+ #define R_GPT10_0_GTSTR_CSTRT5_Msk         (0x20UL)       /*!< CSTRT5 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTR_CSTRT6_Pos         (6UL)          /*!< CSTRT6 (Bit 6)                                        */
+ #define R_GPT10_0_GTSTR_CSTRT6_Msk         (0x40UL)       /*!< CSTRT6 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTSTP  ========================================================= */
+ #define R_GPT10_0_GTSTP_CSTOP0_Pos         (0UL)          /*!< CSTOP0 (Bit 0)                                        */
+ #define R_GPT10_0_GTSTP_CSTOP0_Msk         (0x1UL)        /*!< CSTOP0 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTP_CSTOP1_Pos         (1UL)          /*!< CSTOP1 (Bit 1)                                        */
+ #define R_GPT10_0_GTSTP_CSTOP1_Msk         (0x2UL)        /*!< CSTOP1 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTP_CSTOP2_Pos         (2UL)          /*!< CSTOP2 (Bit 2)                                        */
+ #define R_GPT10_0_GTSTP_CSTOP2_Msk         (0x4UL)        /*!< CSTOP2 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTP_CSTOP3_Pos         (3UL)          /*!< CSTOP3 (Bit 3)                                        */
+ #define R_GPT10_0_GTSTP_CSTOP3_Msk         (0x8UL)        /*!< CSTOP3 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTP_CSTOP4_Pos         (4UL)          /*!< CSTOP4 (Bit 4)                                        */
+ #define R_GPT10_0_GTSTP_CSTOP4_Msk         (0x10UL)       /*!< CSTOP4 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTP_CSTOP5_Pos         (5UL)          /*!< CSTOP5 (Bit 5)                                        */
+ #define R_GPT10_0_GTSTP_CSTOP5_Msk         (0x20UL)       /*!< CSTOP5 (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSTP_CSTOP6_Pos         (6UL)          /*!< CSTOP6 (Bit 6)                                        */
+ #define R_GPT10_0_GTSTP_CSTOP6_Msk         (0x40UL)       /*!< CSTOP6 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTCLR  ========================================================= */
+ #define R_GPT10_0_GTCLR_CCLR0_Pos          (0UL)          /*!< CCLR0 (Bit 0)                                         */
+ #define R_GPT10_0_GTCLR_CCLR0_Msk          (0x1UL)        /*!< CCLR0 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTCLR_CCLR1_Pos          (1UL)          /*!< CCLR1 (Bit 1)                                         */
+ #define R_GPT10_0_GTCLR_CCLR1_Msk          (0x2UL)        /*!< CCLR1 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTCLR_CCLR2_Pos          (2UL)          /*!< CCLR2 (Bit 2)                                         */
+ #define R_GPT10_0_GTCLR_CCLR2_Msk          (0x4UL)        /*!< CCLR2 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTCLR_CCLR3_Pos          (3UL)          /*!< CCLR3 (Bit 3)                                         */
+ #define R_GPT10_0_GTCLR_CCLR3_Msk          (0x8UL)        /*!< CCLR3 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTCLR_CCLR4_Pos          (4UL)          /*!< CCLR4 (Bit 4)                                         */
+ #define R_GPT10_0_GTCLR_CCLR4_Msk          (0x10UL)       /*!< CCLR4 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTCLR_CCLR5_Pos          (5UL)          /*!< CCLR5 (Bit 5)                                         */
+ #define R_GPT10_0_GTCLR_CCLR5_Msk          (0x20UL)       /*!< CCLR5 (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTCLR_CCLR6_Pos          (6UL)          /*!< CCLR6 (Bit 6)                                         */
+ #define R_GPT10_0_GTCLR_CCLR6_Msk          (0x40UL)       /*!< CCLR6 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTSSR  ========================================================= */
+ #define R_GPT10_0_GTSSR_SSGTRGAFR_Pos      (0UL)          /*!< SSGTRGAFR (Bit 0)                                     */
+ #define R_GPT10_0_GTSSR_SSGTRGAFR_Msk      (0x3UL)        /*!< SSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTSSR_SSGTRGBFR_Pos      (2UL)          /*!< SSGTRGBFR (Bit 2)                                     */
+ #define R_GPT10_0_GTSSR_SSGTRGBFR_Msk      (0xcUL)        /*!< SSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTSSR_SSGTRGCFR_Pos      (4UL)          /*!< SSGTRGCFR (Bit 4)                                     */
+ #define R_GPT10_0_GTSSR_SSGTRGCFR_Msk      (0x30UL)       /*!< SSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTSSR_SSGTRGDFR_Pos      (6UL)          /*!< SSGTRGDFR (Bit 6)                                     */
+ #define R_GPT10_0_GTSSR_SSGTRGDFR_Msk      (0xc0UL)       /*!< SSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTSSR_SSCARBHL_Pos       (8UL)          /*!< SSCARBHL (Bit 8)                                      */
+ #define R_GPT10_0_GTSSR_SSCARBHL_Msk       (0x300UL)      /*!< SSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTSSR_SSCAFBHL_Pos       (10UL)         /*!< SSCAFBHL (Bit 10)                                     */
+ #define R_GPT10_0_GTSSR_SSCAFBHL_Msk       (0xc00UL)      /*!< SSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTSSR_SSCBRAHL_Pos       (12UL)         /*!< SSCBRAHL (Bit 12)                                     */
+ #define R_GPT10_0_GTSSR_SSCBRAHL_Msk       (0x3000UL)     /*!< SSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTSSR_SSCBFAHL_Pos       (14UL)         /*!< SSCBFAHL (Bit 14)                                     */
+ #define R_GPT10_0_GTSSR_SSCBFAHL_Msk       (0xc000UL)     /*!< SSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTSSR_SSELCA_Pos         (16UL)         /*!< SSELCA (Bit 16)                                       */
+ #define R_GPT10_0_GTSSR_SSELCA_Msk         (0x10000UL)    /*!< SSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSSR_SSELCB_Pos         (17UL)         /*!< SSELCB (Bit 17)                                       */
+ #define R_GPT10_0_GTSSR_SSELCB_Msk         (0x20000UL)    /*!< SSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSSR_SSELCC_Pos         (18UL)         /*!< SSELCC (Bit 18)                                       */
+ #define R_GPT10_0_GTSSR_SSELCC_Msk         (0x40000UL)    /*!< SSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSSR_SSELCD_Pos         (19UL)         /*!< SSELCD (Bit 19)                                       */
+ #define R_GPT10_0_GTSSR_SSELCD_Msk         (0x80000UL)    /*!< SSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSSR_SSELCE_Pos         (20UL)         /*!< SSELCE (Bit 20)                                       */
+ #define R_GPT10_0_GTSSR_SSELCE_Msk         (0x100000UL)   /*!< SSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSSR_SSELCF_Pos         (21UL)         /*!< SSELCF (Bit 21)                                       */
+ #define R_GPT10_0_GTSSR_SSELCF_Msk         (0x200000UL)   /*!< SSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSSR_SSELCG_Pos         (22UL)         /*!< SSELCG (Bit 22)                                       */
+ #define R_GPT10_0_GTSSR_SSELCG_Msk         (0x400000UL)   /*!< SSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSSR_SSELCH_Pos         (23UL)         /*!< SSELCH (Bit 23)                                       */
+ #define R_GPT10_0_GTSSR_SSELCH_Msk         (0x800000UL)   /*!< SSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSSR_CSTRT_Pos          (31UL)         /*!< CSTRT (Bit 31)                                        */
+ #define R_GPT10_0_GTSSR_CSTRT_Msk          (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTPSR  ========================================================= */
+ #define R_GPT10_0_GTPSR_PSGTRGAFR_Pos      (0UL)          /*!< PSGTRGAFR (Bit 0)                                     */
+ #define R_GPT10_0_GTPSR_PSGTRGAFR_Msk      (0x3UL)        /*!< PSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTPSR_PSGTRGBFR_Pos      (2UL)          /*!< PSGTRGBFR (Bit 2)                                     */
+ #define R_GPT10_0_GTPSR_PSGTRGBFR_Msk      (0xcUL)        /*!< PSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTPSR_PSGTRGCFR_Pos      (4UL)          /*!< PSGTRGCFR (Bit 4)                                     */
+ #define R_GPT10_0_GTPSR_PSGTRGCFR_Msk      (0x30UL)       /*!< PSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTPSR_PSGTRGDFR_Pos      (6UL)          /*!< PSGTRGDFR (Bit 6)                                     */
+ #define R_GPT10_0_GTPSR_PSGTRGDFR_Msk      (0xc0UL)       /*!< PSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTPSR_PSCARBHL_Pos       (8UL)          /*!< PSCARBHL (Bit 8)                                      */
+ #define R_GPT10_0_GTPSR_PSCARBHL_Msk       (0x300UL)      /*!< PSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTPSR_PSCAFBHL_Pos       (10UL)         /*!< PSCAFBHL (Bit 10)                                     */
+ #define R_GPT10_0_GTPSR_PSCAFBHL_Msk       (0xc00UL)      /*!< PSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTPSR_PSCBRAHL_Pos       (12UL)         /*!< PSCBRAHL (Bit 12)                                     */
+ #define R_GPT10_0_GTPSR_PSCBRAHL_Msk       (0x3000UL)     /*!< PSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTPSR_PSCBFAHL_Pos       (14UL)         /*!< PSCBFAHL (Bit 14)                                     */
+ #define R_GPT10_0_GTPSR_PSCBFAHL_Msk       (0xc000UL)     /*!< PSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTPSR_PSELCA_Pos         (16UL)         /*!< PSELCA (Bit 16)                                       */
+ #define R_GPT10_0_GTPSR_PSELCA_Msk         (0x10000UL)    /*!< PSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTPSR_PSELCB_Pos         (17UL)         /*!< PSELCB (Bit 17)                                       */
+ #define R_GPT10_0_GTPSR_PSELCB_Msk         (0x20000UL)    /*!< PSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTPSR_PSELCC_Pos         (18UL)         /*!< PSELCC (Bit 18)                                       */
+ #define R_GPT10_0_GTPSR_PSELCC_Msk         (0x40000UL)    /*!< PSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTPSR_PSELCD_Pos         (19UL)         /*!< PSELCD (Bit 19)                                       */
+ #define R_GPT10_0_GTPSR_PSELCD_Msk         (0x80000UL)    /*!< PSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTPSR_PSELCE_Pos         (20UL)         /*!< PSELCE (Bit 20)                                       */
+ #define R_GPT10_0_GTPSR_PSELCE_Msk         (0x100000UL)   /*!< PSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTPSR_PSELCF_Pos         (21UL)         /*!< PSELCF (Bit 21)                                       */
+ #define R_GPT10_0_GTPSR_PSELCF_Msk         (0x200000UL)   /*!< PSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTPSR_PSELCG_Pos         (22UL)         /*!< PSELCG (Bit 22)                                       */
+ #define R_GPT10_0_GTPSR_PSELCG_Msk         (0x400000UL)   /*!< PSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTPSR_PSELCH_Pos         (23UL)         /*!< PSELCH (Bit 23)                                       */
+ #define R_GPT10_0_GTPSR_PSELCH_Msk         (0x800000UL)   /*!< PSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTPSR_CSTOP_Pos          (31UL)         /*!< CSTOP (Bit 31)                                        */
+ #define R_GPT10_0_GTPSR_CSTOP_Msk          (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCSR  ========================================================= */
+ #define R_GPT10_0_GTCSR_CSGTRGAFR_Pos      (0UL)          /*!< CSGTRGAFR (Bit 0)                                     */
+ #define R_GPT10_0_GTCSR_CSGTRGAFR_Msk      (0x3UL)        /*!< CSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTCSR_CSGTRGBFR_Pos      (2UL)          /*!< CSGTRGBFR (Bit 2)                                     */
+ #define R_GPT10_0_GTCSR_CSGTRGBFR_Msk      (0xcUL)        /*!< CSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTCSR_CSGTRGCFR_Pos      (4UL)          /*!< CSGTRGCFR (Bit 4)                                     */
+ #define R_GPT10_0_GTCSR_CSGTRGCFR_Msk      (0x30UL)       /*!< CSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTCSR_CSGTRGDFR_Pos      (6UL)          /*!< CSGTRGDFR (Bit 6)                                     */
+ #define R_GPT10_0_GTCSR_CSGTRGDFR_Msk      (0xc0UL)       /*!< CSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTCSR_CSCARBHL_Pos       (8UL)          /*!< CSCARBHL (Bit 8)                                      */
+ #define R_GPT10_0_GTCSR_CSCARBHL_Msk       (0x300UL)      /*!< CSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTCSR_CSCAFBHL_Pos       (10UL)         /*!< CSCAFBHL (Bit 10)                                     */
+ #define R_GPT10_0_GTCSR_CSCAFBHL_Msk       (0xc00UL)      /*!< CSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTCSR_CSCBRAHL_Pos       (12UL)         /*!< CSCBRAHL (Bit 12)                                     */
+ #define R_GPT10_0_GTCSR_CSCBRAHL_Msk       (0x3000UL)     /*!< CSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTCSR_CSCBFAHL_Pos       (14UL)         /*!< CSCBFAHL (Bit 14)                                     */
+ #define R_GPT10_0_GTCSR_CSCBFAHL_Msk       (0xc000UL)     /*!< CSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTCSR_CSELCA_Pos         (16UL)         /*!< CSELCA (Bit 16)                                       */
+ #define R_GPT10_0_GTCSR_CSELCA_Msk         (0x10000UL)    /*!< CSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTCSR_CSELCB_Pos         (17UL)         /*!< CSELCB (Bit 17)                                       */
+ #define R_GPT10_0_GTCSR_CSELCB_Msk         (0x20000UL)    /*!< CSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTCSR_CSELCC_Pos         (18UL)         /*!< CSELCC (Bit 18)                                       */
+ #define R_GPT10_0_GTCSR_CSELCC_Msk         (0x40000UL)    /*!< CSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTCSR_CSELCD_Pos         (19UL)         /*!< CSELCD (Bit 19)                                       */
+ #define R_GPT10_0_GTCSR_CSELCD_Msk         (0x80000UL)    /*!< CSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTCSR_CSELCE_Pos         (20UL)         /*!< CSELCE (Bit 20)                                       */
+ #define R_GPT10_0_GTCSR_CSELCE_Msk         (0x100000UL)   /*!< CSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTCSR_CSELCF_Pos         (21UL)         /*!< CSELCF (Bit 21)                                       */
+ #define R_GPT10_0_GTCSR_CSELCF_Msk         (0x200000UL)   /*!< CSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTCSR_CSELCG_Pos         (22UL)         /*!< CSELCG (Bit 22)                                       */
+ #define R_GPT10_0_GTCSR_CSELCG_Msk         (0x400000UL)   /*!< CSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTCSR_CSELCH_Pos         (23UL)         /*!< CSELCH (Bit 23)                                       */
+ #define R_GPT10_0_GTCSR_CSELCH_Msk         (0x800000UL)   /*!< CSELCH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTCSR_CCLR_Pos           (31UL)         /*!< CCLR (Bit 31)                                         */
+ #define R_GPT10_0_GTCSR_CCLR_Msk           (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTUPSR  ========================================================= */
+ #define R_GPT10_0_GTUPSR_USGTRGAFR_Pos     (0UL)          /*!< USGTRGAFR (Bit 0)                                     */
+ #define R_GPT10_0_GTUPSR_USGTRGAFR_Msk     (0x3UL)        /*!< USGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTUPSR_USGTRGBFR_Pos     (2UL)          /*!< USGTRGBFR (Bit 2)                                     */
+ #define R_GPT10_0_GTUPSR_USGTRGBFR_Msk     (0xcUL)        /*!< USGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTUPSR_USGTRGCFR_Pos     (4UL)          /*!< USGTRGCFR (Bit 4)                                     */
+ #define R_GPT10_0_GTUPSR_USGTRGCFR_Msk     (0x30UL)       /*!< USGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTUPSR_USGTRGDFR_Pos     (6UL)          /*!< USGTRGDFR (Bit 6)                                     */
+ #define R_GPT10_0_GTUPSR_USGTRGDFR_Msk     (0xc0UL)       /*!< USGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTUPSR_USCARBHL_Pos      (8UL)          /*!< USCARBHL (Bit 8)                                      */
+ #define R_GPT10_0_GTUPSR_USCARBHL_Msk      (0x300UL)      /*!< USCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTUPSR_USCAFBHL_Pos      (10UL)         /*!< USCAFBHL (Bit 10)                                     */
+ #define R_GPT10_0_GTUPSR_USCAFBHL_Msk      (0xc00UL)      /*!< USCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTUPSR_USCBRAHL_Pos      (12UL)         /*!< USCBRAHL (Bit 12)                                     */
+ #define R_GPT10_0_GTUPSR_USCBRAHL_Msk      (0x3000UL)     /*!< USCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTUPSR_USCBFAHL_Pos      (14UL)         /*!< USCBFAHL (Bit 14)                                     */
+ #define R_GPT10_0_GTUPSR_USCBFAHL_Msk      (0xc000UL)     /*!< USCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTUPSR_USELCA_Pos        (16UL)         /*!< USELCA (Bit 16)                                       */
+ #define R_GPT10_0_GTUPSR_USELCA_Msk        (0x10000UL)    /*!< USELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUPSR_USELCB_Pos        (17UL)         /*!< USELCB (Bit 17)                                       */
+ #define R_GPT10_0_GTUPSR_USELCB_Msk        (0x20000UL)    /*!< USELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUPSR_USELCC_Pos        (18UL)         /*!< USELCC (Bit 18)                                       */
+ #define R_GPT10_0_GTUPSR_USELCC_Msk        (0x40000UL)    /*!< USELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUPSR_USELCD_Pos        (19UL)         /*!< USELCD (Bit 19)                                       */
+ #define R_GPT10_0_GTUPSR_USELCD_Msk        (0x80000UL)    /*!< USELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUPSR_USELCE_Pos        (20UL)         /*!< USELCE (Bit 20)                                       */
+ #define R_GPT10_0_GTUPSR_USELCE_Msk        (0x100000UL)   /*!< USELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUPSR_USELCF_Pos        (21UL)         /*!< USELCF (Bit 21)                                       */
+ #define R_GPT10_0_GTUPSR_USELCF_Msk        (0x200000UL)   /*!< USELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUPSR_USELCG_Pos        (22UL)         /*!< USELCG (Bit 22)                                       */
+ #define R_GPT10_0_GTUPSR_USELCG_Msk        (0x400000UL)   /*!< USELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUPSR_USELCH_Pos        (23UL)         /*!< USELCH (Bit 23)                                       */
+ #define R_GPT10_0_GTUPSR_USELCH_Msk        (0x800000UL)   /*!< USELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTDNSR  ========================================================= */
+ #define R_GPT10_0_GTDNSR_DSGTRGAFR_Pos     (0UL)          /*!< DSGTRGAFR (Bit 0)                                     */
+ #define R_GPT10_0_GTDNSR_DSGTRGAFR_Msk     (0x3UL)        /*!< DSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTDNSR_DSGTRGBFR_Pos     (2UL)          /*!< DSGTRGBFR (Bit 2)                                     */
+ #define R_GPT10_0_GTDNSR_DSGTRGBFR_Msk     (0xcUL)        /*!< DSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTDNSR_DSGTRGCFR_Pos     (4UL)          /*!< DSGTRGCFR (Bit 4)                                     */
+ #define R_GPT10_0_GTDNSR_DSGTRGCFR_Msk     (0x30UL)       /*!< DSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTDNSR_DSGTRGDFR_Pos     (6UL)          /*!< DSGTRGDFR (Bit 6)                                     */
+ #define R_GPT10_0_GTDNSR_DSGTRGDFR_Msk     (0xc0UL)       /*!< DSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTDNSR_DSCARBHL_Pos      (8UL)          /*!< DSCARBHL (Bit 8)                                      */
+ #define R_GPT10_0_GTDNSR_DSCARBHL_Msk      (0x300UL)      /*!< DSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTDNSR_DSCAFBHL_Pos      (10UL)         /*!< DSCAFBHL (Bit 10)                                     */
+ #define R_GPT10_0_GTDNSR_DSCAFBHL_Msk      (0xc00UL)      /*!< DSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTDNSR_DSCBRAHL_Pos      (12UL)         /*!< DSCBRAHL (Bit 12)                                     */
+ #define R_GPT10_0_GTDNSR_DSCBRAHL_Msk      (0x3000UL)     /*!< DSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTDNSR_DSCBFAHL_Pos      (14UL)         /*!< DSCBFAHL (Bit 14)                                     */
+ #define R_GPT10_0_GTDNSR_DSCBFAHL_Msk      (0xc000UL)     /*!< DSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTDNSR_DSELCA_Pos        (16UL)         /*!< DSELCA (Bit 16)                                       */
+ #define R_GPT10_0_GTDNSR_DSELCA_Msk        (0x10000UL)    /*!< DSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTDNSR_DSELCB_Pos        (17UL)         /*!< DSELCB (Bit 17)                                       */
+ #define R_GPT10_0_GTDNSR_DSELCB_Msk        (0x20000UL)    /*!< DSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTDNSR_DSELCC_Pos        (18UL)         /*!< DSELCC (Bit 18)                                       */
+ #define R_GPT10_0_GTDNSR_DSELCC_Msk        (0x40000UL)    /*!< DSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTDNSR_DSELCD_Pos        (19UL)         /*!< DSELCD (Bit 19)                                       */
+ #define R_GPT10_0_GTDNSR_DSELCD_Msk        (0x80000UL)    /*!< DSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTDNSR_DSELCE_Pos        (20UL)         /*!< DSELCE (Bit 20)                                       */
+ #define R_GPT10_0_GTDNSR_DSELCE_Msk        (0x100000UL)   /*!< DSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTDNSR_DSELCF_Pos        (21UL)         /*!< DSELCF (Bit 21)                                       */
+ #define R_GPT10_0_GTDNSR_DSELCF_Msk        (0x200000UL)   /*!< DSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTDNSR_DSELCG_Pos        (22UL)         /*!< DSELCG (Bit 22)                                       */
+ #define R_GPT10_0_GTDNSR_DSELCG_Msk        (0x400000UL)   /*!< DSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTDNSR_DSELCH_Pos        (23UL)         /*!< DSELCH (Bit 23)                                       */
+ #define R_GPT10_0_GTDNSR_DSELCH_Msk        (0x800000UL)   /*!< DSELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTICASR  ======================================================== */
+ #define R_GPT10_0_GTICASR_ASGTRGAFR_Pos    (0UL)          /*!< ASGTRGAFR (Bit 0)                                     */
+ #define R_GPT10_0_GTICASR_ASGTRGAFR_Msk    (0x3UL)        /*!< ASGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTICASR_ASGTRGBFR_Pos    (2UL)          /*!< ASGTRGBFR (Bit 2)                                     */
+ #define R_GPT10_0_GTICASR_ASGTRGBFR_Msk    (0xcUL)        /*!< ASGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTICASR_ASGTRGCFR_Pos    (4UL)          /*!< ASGTRGCFR (Bit 4)                                     */
+ #define R_GPT10_0_GTICASR_ASGTRGCFR_Msk    (0x30UL)       /*!< ASGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTICASR_ASGTRGDFR_Pos    (6UL)          /*!< ASGTRGDFR (Bit 6)                                     */
+ #define R_GPT10_0_GTICASR_ASGTRGDFR_Msk    (0xc0UL)       /*!< ASGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTICASR_ASCARBHL_Pos     (8UL)          /*!< ASCARBHL (Bit 8)                                      */
+ #define R_GPT10_0_GTICASR_ASCARBHL_Msk     (0x300UL)      /*!< ASCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTICASR_ASCAFBHL_Pos     (10UL)         /*!< ASCAFBHL (Bit 10)                                     */
+ #define R_GPT10_0_GTICASR_ASCAFBHL_Msk     (0xc00UL)      /*!< ASCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTICASR_ASCBRAHL_Pos     (12UL)         /*!< ASCBRAHL (Bit 12)                                     */
+ #define R_GPT10_0_GTICASR_ASCBRAHL_Msk     (0x3000UL)     /*!< ASCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTICASR_ASCBFAHL_Pos     (14UL)         /*!< ASCBFAHL (Bit 14)                                     */
+ #define R_GPT10_0_GTICASR_ASCBFAHL_Msk     (0xc000UL)     /*!< ASCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTICASR_ASELCA_Pos       (16UL)         /*!< ASELCA (Bit 16)                                       */
+ #define R_GPT10_0_GTICASR_ASELCA_Msk       (0x10000UL)    /*!< ASELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICASR_ASELCB_Pos       (17UL)         /*!< ASELCB (Bit 17)                                       */
+ #define R_GPT10_0_GTICASR_ASELCB_Msk       (0x20000UL)    /*!< ASELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICASR_ASELCC_Pos       (18UL)         /*!< ASELCC (Bit 18)                                       */
+ #define R_GPT10_0_GTICASR_ASELCC_Msk       (0x40000UL)    /*!< ASELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICASR_ASELCD_Pos       (19UL)         /*!< ASELCD (Bit 19)                                       */
+ #define R_GPT10_0_GTICASR_ASELCD_Msk       (0x80000UL)    /*!< ASELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICASR_ASELCE_Pos       (20UL)         /*!< ASELCE (Bit 20)                                       */
+ #define R_GPT10_0_GTICASR_ASELCE_Msk       (0x100000UL)   /*!< ASELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICASR_ASELCF_Pos       (21UL)         /*!< ASELCF (Bit 21)                                       */
+ #define R_GPT10_0_GTICASR_ASELCF_Msk       (0x200000UL)   /*!< ASELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICASR_ASELCG_Pos       (22UL)         /*!< ASELCG (Bit 22)                                       */
+ #define R_GPT10_0_GTICASR_ASELCG_Msk       (0x400000UL)   /*!< ASELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICASR_ASELCH_Pos       (23UL)         /*!< ASELCH (Bit 23)                                       */
+ #define R_GPT10_0_GTICASR_ASELCH_Msk       (0x800000UL)   /*!< ASELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTICBSR  ======================================================== */
+ #define R_GPT10_0_GTICBSR_BSGTRGAFR_Pos    (0UL)          /*!< BSGTRGAFR (Bit 0)                                     */
+ #define R_GPT10_0_GTICBSR_BSGTRGAFR_Msk    (0x3UL)        /*!< BSGTRGAFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTICBSR_BSGTRGBFR_Pos    (2UL)          /*!< BSGTRGBFR (Bit 2)                                     */
+ #define R_GPT10_0_GTICBSR_BSGTRGBFR_Msk    (0xcUL)        /*!< BSGTRGBFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTICBSR_BSGTRGCFR_Pos    (4UL)          /*!< BSGTRGCFR (Bit 4)                                     */
+ #define R_GPT10_0_GTICBSR_BSGTRGCFR_Msk    (0x30UL)       /*!< BSGTRGCFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTICBSR_BSGTRGDFR_Pos    (6UL)          /*!< BSGTRGDFR (Bit 6)                                     */
+ #define R_GPT10_0_GTICBSR_BSGTRGDFR_Msk    (0xc0UL)       /*!< BSGTRGDFR (Bitfield-Mask: 0x03)                       */
+ #define R_GPT10_0_GTICBSR_BSCARBHL_Pos     (8UL)          /*!< BSCARBHL (Bit 8)                                      */
+ #define R_GPT10_0_GTICBSR_BSCARBHL_Msk     (0x300UL)      /*!< BSCARBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTICBSR_BSCAFBHL_Pos     (10UL)         /*!< BSCAFBHL (Bit 10)                                     */
+ #define R_GPT10_0_GTICBSR_BSCAFBHL_Msk     (0xc00UL)      /*!< BSCAFBHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTICBSR_BSCBRAHL_Pos     (12UL)         /*!< BSCBRAHL (Bit 12)                                     */
+ #define R_GPT10_0_GTICBSR_BSCBRAHL_Msk     (0x3000UL)     /*!< BSCBRAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTICBSR_BSCBFAHL_Pos     (14UL)         /*!< BSCBFAHL (Bit 14)                                     */
+ #define R_GPT10_0_GTICBSR_BSCBFAHL_Msk     (0xc000UL)     /*!< BSCBFAHL (Bitfield-Mask: 0x03)                        */
+ #define R_GPT10_0_GTICBSR_BSELCA_Pos       (16UL)         /*!< BSELCA (Bit 16)                                       */
+ #define R_GPT10_0_GTICBSR_BSELCA_Msk       (0x10000UL)    /*!< BSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICBSR_BSELCB_Pos       (17UL)         /*!< BSELCB (Bit 17)                                       */
+ #define R_GPT10_0_GTICBSR_BSELCB_Msk       (0x20000UL)    /*!< BSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICBSR_BSELCC_Pos       (18UL)         /*!< BSELCC (Bit 18)                                       */
+ #define R_GPT10_0_GTICBSR_BSELCC_Msk       (0x40000UL)    /*!< BSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICBSR_BSELCD_Pos       (19UL)         /*!< BSELCD (Bit 19)                                       */
+ #define R_GPT10_0_GTICBSR_BSELCD_Msk       (0x80000UL)    /*!< BSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICBSR_BSELCE_Pos       (20UL)         /*!< BSELCE (Bit 20)                                       */
+ #define R_GPT10_0_GTICBSR_BSELCE_Msk       (0x100000UL)   /*!< BSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICBSR_BSELCF_Pos       (21UL)         /*!< BSELCF (Bit 21)                                       */
+ #define R_GPT10_0_GTICBSR_BSELCF_Msk       (0x200000UL)   /*!< BSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICBSR_BSELCG_Pos       (22UL)         /*!< BSELCG (Bit 22)                                       */
+ #define R_GPT10_0_GTICBSR_BSELCG_Msk       (0x400000UL)   /*!< BSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTICBSR_BSELCH_Pos       (23UL)         /*!< BSELCH (Bit 23)                                       */
+ #define R_GPT10_0_GTICBSR_BSELCH_Msk       (0x800000UL)   /*!< BSELCH (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTCR  ========================================================== */
+ #define R_GPT10_0_GTCR_CST_Pos             (0UL)          /*!< CST (Bit 0)                                           */
+ #define R_GPT10_0_GTCR_CST_Msk             (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTCR_ICDS_Pos            (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT10_0_GTCR_ICDS_Msk            (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTCR_MD_Pos              (16UL)         /*!< MD (Bit 16)                                           */
+ #define R_GPT10_0_GTCR_MD_Msk              (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT10_0_GTCR_TPCS_Pos            (23UL)         /*!< TPCS (Bit 23)                                         */
+ #define R_GPT10_0_GTCR_TPCS_Msk            (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
+ #define R_GPT10_0_GTCR_SWMD_Pos            (29UL)         /*!< SWMD (Bit 29)                                         */
+ #define R_GPT10_0_GTCR_SWMD_Msk            (0xe0000000UL) /*!< SWMD (Bitfield-Mask: 0x07)                            */
+/* =======================================================  GTUDDTYC  ======================================================== */
+ #define R_GPT10_0_GTUDDTYC_UD_Pos          (0UL)          /*!< UD (Bit 0)                                            */
+ #define R_GPT10_0_GTUDDTYC_UD_Msk          (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
+ #define R_GPT10_0_GTUDDTYC_UDF_Pos         (1UL)          /*!< UDF (Bit 1)                                           */
+ #define R_GPT10_0_GTUDDTYC_UDF_Msk         (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTUDDTYC_OADTY_Pos       (16UL)         /*!< OADTY (Bit 16)                                        */
+ #define R_GPT10_0_GTUDDTYC_OADTY_Msk       (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT10_0_GTUDDTYC_OADTYF_Pos      (18UL)         /*!< OADTYF (Bit 18)                                       */
+ #define R_GPT10_0_GTUDDTYC_OADTYF_Msk      (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUDDTYC_OADTYR_Pos      (19UL)         /*!< OADTYR (Bit 19)                                       */
+ #define R_GPT10_0_GTUDDTYC_OADTYR_Msk      (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUDDTYC_OBDTY_Pos       (24UL)         /*!< OBDTY (Bit 24)                                        */
+ #define R_GPT10_0_GTUDDTYC_OBDTY_Msk       (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT10_0_GTUDDTYC_OBDTYF_Pos      (26UL)         /*!< OBDTYF (Bit 26)                                       */
+ #define R_GPT10_0_GTUDDTYC_OBDTYF_Msk      (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUDDTYC_OBDTYR_Pos      (27UL)         /*!< OBDTYR (Bit 27)                                       */
+ #define R_GPT10_0_GTUDDTYC_OBDTYR_Msk      (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTUDDTYC_OABDTYT_Pos     (28UL)         /*!< OABDTYT (Bit 28)                                      */
+ #define R_GPT10_0_GTUDDTYC_OABDTYT_Msk     (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTIOR  ========================================================= */
+ #define R_GPT10_0_GTIOR_GTIOA_Pos          (0UL)          /*!< GTIOA (Bit 0)                                         */
+ #define R_GPT10_0_GTIOR_GTIOA_Msk          (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT10_0_GTIOR_OADFLT_Pos         (6UL)          /*!< OADFLT (Bit 6)                                        */
+ #define R_GPT10_0_GTIOR_OADFLT_Msk         (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTIOR_OAHLD_Pos          (7UL)          /*!< OAHLD (Bit 7)                                         */
+ #define R_GPT10_0_GTIOR_OAHLD_Msk          (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTIOR_OAE_Pos            (8UL)          /*!< OAE (Bit 8)                                           */
+ #define R_GPT10_0_GTIOR_OAE_Msk            (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTIOR_OADF_Pos           (9UL)          /*!< OADF (Bit 9)                                          */
+ #define R_GPT10_0_GTIOR_OADF_Msk           (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT10_0_GTIOR_NFAEN_Pos          (13UL)         /*!< NFAEN (Bit 13)                                        */
+ #define R_GPT10_0_GTIOR_NFAEN_Msk          (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTIOR_NFCSA_Pos          (14UL)         /*!< NFCSA (Bit 14)                                        */
+ #define R_GPT10_0_GTIOR_NFCSA_Msk          (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT10_0_GTIOR_GTIOB_Pos          (16UL)         /*!< GTIOB (Bit 16)                                        */
+ #define R_GPT10_0_GTIOR_GTIOB_Msk          (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT10_0_GTIOR_OBDFLT_Pos         (22UL)         /*!< OBDFLT (Bit 22)                                       */
+ #define R_GPT10_0_GTIOR_OBDFLT_Msk         (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTIOR_OBHLD_Pos          (23UL)         /*!< OBHLD (Bit 23)                                        */
+ #define R_GPT10_0_GTIOR_OBHLD_Msk          (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTIOR_OBE_Pos            (24UL)         /*!< OBE (Bit 24)                                          */
+ #define R_GPT10_0_GTIOR_OBE_Msk            (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTIOR_OBDF_Pos           (25UL)         /*!< OBDF (Bit 25)                                         */
+ #define R_GPT10_0_GTIOR_OBDF_Msk           (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT10_0_GTIOR_NFBEN_Pos          (29UL)         /*!< NFBEN (Bit 29)                                        */
+ #define R_GPT10_0_GTIOR_NFBEN_Msk          (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTIOR_NFCSB_Pos          (30UL)         /*!< NFCSB (Bit 30)                                        */
+ #define R_GPT10_0_GTIOR_NFCSB_Msk          (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT10_0_GTINTAD_GTINTA_Pos       (0UL)          /*!< GTINTA (Bit 0)                                        */
+ #define R_GPT10_0_GTINTAD_GTINTA_Msk       (0x1UL)        /*!< GTINTA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTINTAD_GTINTB_Pos       (1UL)          /*!< GTINTB (Bit 1)                                        */
+ #define R_GPT10_0_GTINTAD_GTINTB_Msk       (0x2UL)        /*!< GTINTB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTINTAD_GTINTC_Pos       (2UL)          /*!< GTINTC (Bit 2)                                        */
+ #define R_GPT10_0_GTINTAD_GTINTC_Msk       (0x4UL)        /*!< GTINTC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTINTAD_GTINTD_Pos       (3UL)          /*!< GTINTD (Bit 3)                                        */
+ #define R_GPT10_0_GTINTAD_GTINTD_Msk       (0x8UL)        /*!< GTINTD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTINTAD_GTINTE_Pos       (4UL)          /*!< GTINTE (Bit 4)                                        */
+ #define R_GPT10_0_GTINTAD_GTINTE_Msk       (0x10UL)       /*!< GTINTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTINTAD_GTINTF_Pos       (5UL)          /*!< GTINTF (Bit 5)                                        */
+ #define R_GPT10_0_GTINTAD_GTINTF_Msk       (0x20UL)       /*!< GTINTF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTINTAD_GTINTPR_Pos      (6UL)          /*!< GTINTPR (Bit 6)                                       */
+ #define R_GPT10_0_GTINTAD_GTINTPR_Msk      (0xc0UL)       /*!< GTINTPR (Bitfield-Mask: 0x03)                         */
+ #define R_GPT10_0_GTINTAD_ADTRAUEN_Pos     (16UL)         /*!< ADTRAUEN (Bit 16)                                     */
+ #define R_GPT10_0_GTINTAD_ADTRAUEN_Msk     (0x10000UL)    /*!< ADTRAUEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT10_0_GTINTAD_ADTRADEN_Pos     (17UL)         /*!< ADTRADEN (Bit 17)                                     */
+ #define R_GPT10_0_GTINTAD_ADTRADEN_Msk     (0x20000UL)    /*!< ADTRADEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT10_0_GTINTAD_ADTRBUEN_Pos     (18UL)         /*!< ADTRBUEN (Bit 18)                                     */
+ #define R_GPT10_0_GTINTAD_ADTRBUEN_Msk     (0x40000UL)    /*!< ADTRBUEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT10_0_GTINTAD_ADTRBDEN_Pos     (19UL)         /*!< ADTRBDEN (Bit 19)                                     */
+ #define R_GPT10_0_GTINTAD_ADTRBDEN_Msk     (0x80000UL)    /*!< ADTRBDEN (Bitfield-Mask: 0x01)                        */
+ #define R_GPT10_0_GTINTAD_GRP_Pos          (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT10_0_GTINTAD_GRP_Msk          (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+ #define R_GPT10_0_GTINTAD_GRPDTE_Pos       (28UL)         /*!< GRPDTE (Bit 28)                                       */
+ #define R_GPT10_0_GTINTAD_GRPDTE_Msk       (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTINTAD_GRPABH_Pos       (29UL)         /*!< GRPABH (Bit 29)                                       */
+ #define R_GPT10_0_GTINTAD_GRPABH_Msk       (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTINTAD_GRPABL_Pos       (30UL)         /*!< GRPABL (Bit 30)                                       */
+ #define R_GPT10_0_GTINTAD_GRPABL_Msk       (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
+/* =========================================================  GTST  ========================================================== */
+ #define R_GPT10_0_GTST_ITCNT_Pos           (8UL)          /*!< ITCNT (Bit 8)                                         */
+ #define R_GPT10_0_GTST_ITCNT_Msk           (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
+ #define R_GPT10_0_GTST_TUCF_Pos            (15UL)         /*!< TUCF (Bit 15)                                         */
+ #define R_GPT10_0_GTST_TUCF_Msk            (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTST_ADTRAUF_Pos         (16UL)         /*!< ADTRAUF (Bit 16)                                      */
+ #define R_GPT10_0_GTST_ADTRAUF_Msk         (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTST_ADTRADF_Pos         (17UL)         /*!< ADTRADF (Bit 17)                                      */
+ #define R_GPT10_0_GTST_ADTRADF_Msk         (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTST_ADTRBUF_Pos         (18UL)         /*!< ADTRBUF (Bit 18)                                      */
+ #define R_GPT10_0_GTST_ADTRBUF_Msk         (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTST_ADTRBDF_Pos         (19UL)         /*!< ADTRBDF (Bit 19)                                      */
+ #define R_GPT10_0_GTST_ADTRBDF_Msk         (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTST_ODF_Pos             (24UL)         /*!< ODF (Bit 24)                                          */
+ #define R_GPT10_0_GTST_ODF_Msk             (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTST_DTEF_Pos            (28UL)         /*!< DTEF (Bit 28)                                         */
+ #define R_GPT10_0_GTST_DTEF_Msk            (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTST_OABHF_Pos           (29UL)         /*!< OABHF (Bit 29)                                        */
+ #define R_GPT10_0_GTST_OABHF_Msk           (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTST_OABLF_Pos           (30UL)         /*!< OABLF (Bit 30)                                        */
+ #define R_GPT10_0_GTST_OABLF_Msk           (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTBER  ========================================================= */
+ #define R_GPT10_0_GTBER_BD0_Pos            (0UL)          /*!< BD0 (Bit 0)                                           */
+ #define R_GPT10_0_GTBER_BD0_Msk            (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTBER_BD1_Pos            (1UL)          /*!< BD1 (Bit 1)                                           */
+ #define R_GPT10_0_GTBER_BD1_Msk            (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTBER_BD2_Pos            (2UL)          /*!< BD2 (Bit 2)                                           */
+ #define R_GPT10_0_GTBER_BD2_Msk            (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTBER_BD3_Pos            (3UL)          /*!< BD3 (Bit 3)                                           */
+ #define R_GPT10_0_GTBER_BD3_Msk            (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTBER_DBRTECA_Pos        (8UL)          /*!< DBRTECA (Bit 8)                                       */
+ #define R_GPT10_0_GTBER_DBRTECA_Msk        (0x100UL)      /*!< DBRTECA (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTBER_DBRTECB_Pos        (10UL)         /*!< DBRTECB (Bit 10)                                      */
+ #define R_GPT10_0_GTBER_DBRTECB_Msk        (0x400UL)      /*!< DBRTECB (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTBER_CCRA_Pos           (16UL)         /*!< CCRA (Bit 16)                                         */
+ #define R_GPT10_0_GTBER_CCRA_Msk           (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT10_0_GTBER_CCRB_Pos           (18UL)         /*!< CCRB (Bit 18)                                         */
+ #define R_GPT10_0_GTBER_CCRB_Msk           (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
+ #define R_GPT10_0_GTBER_PR_Pos             (20UL)         /*!< PR (Bit 20)                                           */
+ #define R_GPT10_0_GTBER_PR_Msk             (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
+ #define R_GPT10_0_GTBER_CCRSWT_Pos         (22UL)         /*!< CCRSWT (Bit 22)                                       */
+ #define R_GPT10_0_GTBER_CCRSWT_Msk         (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTBER_ADTTA_Pos          (24UL)         /*!< ADTTA (Bit 24)                                        */
+ #define R_GPT10_0_GTBER_ADTTA_Msk          (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT10_0_GTBER_ADTDA_Pos          (26UL)         /*!< ADTDA (Bit 26)                                        */
+ #define R_GPT10_0_GTBER_ADTDA_Msk          (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTBER_ADTTB_Pos          (28UL)         /*!< ADTTB (Bit 28)                                        */
+ #define R_GPT10_0_GTBER_ADTTB_Msk          (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT10_0_GTBER_ADTDB_Pos          (30UL)         /*!< ADTDB (Bit 30)                                        */
+ #define R_GPT10_0_GTBER_ADTDB_Msk          (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTITC  ========================================================= */
+ #define R_GPT10_0_GTITC_ITLA_Pos           (0UL)          /*!< ITLA (Bit 0)                                          */
+ #define R_GPT10_0_GTITC_ITLA_Msk           (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTITC_ITLB_Pos           (1UL)          /*!< ITLB (Bit 1)                                          */
+ #define R_GPT10_0_GTITC_ITLB_Msk           (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTITC_ITLC_Pos           (2UL)          /*!< ITLC (Bit 2)                                          */
+ #define R_GPT10_0_GTITC_ITLC_Msk           (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTITC_ITLD_Pos           (3UL)          /*!< ITLD (Bit 3)                                          */
+ #define R_GPT10_0_GTITC_ITLD_Msk           (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTITC_ITLE_Pos           (4UL)          /*!< ITLE (Bit 4)                                          */
+ #define R_GPT10_0_GTITC_ITLE_Msk           (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTITC_ITLF_Pos           (5UL)          /*!< ITLF (Bit 5)                                          */
+ #define R_GPT10_0_GTITC_ITLF_Msk           (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT10_0_GTITC_IVTC_Pos           (6UL)          /*!< IVTC (Bit 6)                                          */
+ #define R_GPT10_0_GTITC_IVTC_Msk           (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
+ #define R_GPT10_0_GTITC_IVTT_Pos           (8UL)          /*!< IVTT (Bit 8)                                          */
+ #define R_GPT10_0_GTITC_IVTT_Msk           (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
+ #define R_GPT10_0_GTITC_ADTAL_Pos          (12UL)         /*!< ADTAL (Bit 12)                                        */
+ #define R_GPT10_0_GTITC_ADTAL_Msk          (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTITC_ADTBL_Pos          (14UL)         /*!< ADTBL (Bit 14)                                        */
+ #define R_GPT10_0_GTITC_ADTBL_Msk          (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCNT  ========================================================= */
+/* =========================================================  GTCCR  ========================================================= */
+/* =========================================================  GTPR  ========================================================== */
+/* =========================================================  GTPBR  ========================================================= */
+/* ========================================================  GTPDBR  ========================================================= */
+/* ========================================================  GTDTCR  ========================================================= */
+ #define R_GPT10_0_GTDTCR_TDE_Pos      (0UL)     /*!< TDE (Bit 0)                                           */
+ #define R_GPT10_0_GTDTCR_TDE_Msk      (0x1UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT10_0_GTDTCR_TDBUE_Pos    (4UL)     /*!< TDBUE (Bit 4)                                         */
+ #define R_GPT10_0_GTDTCR_TDBUE_Msk    (0x10UL)  /*!< TDBUE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTDTCR_TDBDE_Pos    (5UL)     /*!< TDBDE (Bit 5)                                         */
+ #define R_GPT10_0_GTDTCR_TDBDE_Msk    (0x20UL)  /*!< TDBDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTDTCR_TDFER_Pos    (8UL)     /*!< TDFER (Bit 8)                                         */
+ #define R_GPT10_0_GTDTCR_TDFER_Msk    (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTDVU  ========================================================= */
+/* =========================================================  GTDVD  ========================================================= */
+/* =========================================================  GTDBU  ========================================================= */
+/* =========================================================  GTDBD  ========================================================= */
+/* =========================================================  GTSOS  ========================================================= */
+ #define R_GPT10_0_GTSOS_SOS_Pos           (0UL)          /*!< SOS (Bit 0)                                           */
+ #define R_GPT10_0_GTSOS_SOS_Msk           (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
+/* ========================================================  GTSOTR  ========================================================= */
+ #define R_GPT10_0_GTSOTR_SOTR_Pos         (0UL)          /*!< SOTR (Bit 0)                                          */
+ #define R_GPT10_0_GTSOTR_SOTR_Msk         (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT10_0_GTEITC_EIVTC1_Pos       (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT10_0_GTEITC_EIVTC1_Msk       (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT10_0_GTEITC_EIVTT1_Pos       (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT10_0_GTEITC_EIVTT1_Msk       (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT10_0_GTEITC_EITCNT1_Pos      (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT10_0_GTEITC_EITCNT1_Msk      (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT10_0_GTEITC_EIVTC2_Pos       (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT10_0_GTEITC_EIVTC2_Msk       (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT10_0_GTEITC_EIVTT2_Pos       (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT10_0_GTEITC_EIVTT2_Msk       (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT10_0_GTEITC_EITCNT2IV_Pos    (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT10_0_GTEITC_EITCNT2IV_Msk    (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT10_0_GTEITC_EITCNT2_Pos      (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT10_0_GTEITC_EITCNT2_Msk      (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT10_0_GTEITLI1_EITLA_Pos      (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT10_0_GTEITLI1_EITLA_Msk      (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT10_0_GTEITLI1_EITLB_Pos      (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT10_0_GTEITLI1_EITLB_Msk      (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT10_0_GTEITLI1_EITLC_Pos      (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT10_0_GTEITLI1_EITLC_Msk      (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT10_0_GTEITLI1_EITLD_Pos      (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT10_0_GTEITLI1_EITLD_Msk      (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT10_0_GTEITLI1_EITLE_Pos      (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT10_0_GTEITLI1_EITLE_Msk      (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT10_0_GTEITLI1_EITLF_Pos      (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT10_0_GTEITLI1_EITLF_Msk      (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT10_0_GTEITLI1_EITLV_Pos      (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT10_0_GTEITLI1_EITLV_Msk      (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT10_0_GTEITLI1_EITLU_Pos      (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT10_0_GTEITLI1_EITLU_Msk      (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT10_0_GTEITLI2_EADTAL_Pos     (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT10_0_GTEITLI2_EADTAL_Msk     (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT10_0_GTEITLI2_EADTBL_Pos     (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT10_0_GTEITLI2_EADTBL_Msk     (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT10_0_GTEITLB_EBTLCA_Pos      (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT10_0_GTEITLB_EBTLCA_Msk      (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT10_0_GTEITLB_EBTLCB_Pos      (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT10_0_GTEITLB_EBTLCB_Msk      (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT10_0_GTEITLB_EBTLPR_Pos      (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT10_0_GTEITLB_EBTLPR_Msk      (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT10_0_GTEITLB_EBTLADA_Pos     (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT10_0_GTEITLB_EBTLADA_Msk     (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT10_0_GTEITLB_EBTLADB_Pos     (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT10_0_GTEITLB_EBTLADB_Msk     (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT10_0_GTEITLB_EBTLDVU_Pos     (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT10_0_GTEITLB_EBTLDVU_Msk     (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT10_0_GTEITLB_EBTLDVD_Pos     (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT10_0_GTEITLB_EBTLDVD_Msk     (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
+/* ========================================================  GTSECSR  ======================================================== */
+ #define R_GPT10_0_GTSECSR_SECSEL0_Pos     (0UL)          /*!< SECSEL0 (Bit 0)                                       */
+ #define R_GPT10_0_GTSECSR_SECSEL0_Msk     (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTSECSR_SECSEL1_Pos     (1UL)          /*!< SECSEL1 (Bit 1)                                       */
+ #define R_GPT10_0_GTSECSR_SECSEL1_Msk     (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTSECSR_SECSEL2_Pos     (2UL)          /*!< SECSEL2 (Bit 2)                                       */
+ #define R_GPT10_0_GTSECSR_SECSEL2_Msk     (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTSECSR_SECSEL3_Pos     (3UL)          /*!< SECSEL3 (Bit 3)                                       */
+ #define R_GPT10_0_GTSECSR_SECSEL3_Msk     (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTSECSR_SECSEL4_Pos     (4UL)          /*!< SECSEL4 (Bit 4)                                       */
+ #define R_GPT10_0_GTSECSR_SECSEL4_Msk     (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTSECSR_SECSEL5_Pos     (5UL)          /*!< SECSEL5 (Bit 5)                                       */
+ #define R_GPT10_0_GTSECSR_SECSEL5_Msk     (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT10_0_GTSECSR_SECSEL6_Pos     (6UL)          /*!< SECSEL6 (Bit 6)                                       */
+ #define R_GPT10_0_GTSECSR_SECSEL6_Msk     (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTSECR  ========================================================= */
+ #define R_GPT10_0_GTSECR_SBDCE_Pos        (0UL)          /*!< SBDCE (Bit 0)                                         */
+ #define R_GPT10_0_GTSECR_SBDCE_Msk        (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTSECR_SBDPE_Pos        (1UL)          /*!< SBDPE (Bit 1)                                         */
+ #define R_GPT10_0_GTSECR_SBDPE_Msk        (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTSECR_SBDAE_Pos        (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT10_0_GTSECR_SBDAE_Msk        (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTSECR_SBDDE_Pos        (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT10_0_GTSECR_SBDDE_Msk        (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTSECR_SBDCD_Pos        (8UL)          /*!< SBDCD (Bit 8)                                         */
+ #define R_GPT10_0_GTSECR_SBDCD_Msk        (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTSECR_SBDPD_Pos        (9UL)          /*!< SBDPD (Bit 9)                                         */
+ #define R_GPT10_0_GTSECR_SBDPD_Msk        (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTSECR_SBDAD_Pos        (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT10_0_GTSECR_SBDAD_Msk        (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT10_0_GTSECR_SBDDD_Pos        (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT10_0_GTSECR_SBDDD_Msk        (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  GTSWSR  ========================================================= */
+ #define R_GPT10_0_GTSWSR_WSGTRGA_Pos      (0UL)          /*!< WSGTRGA (Bit 0)                                       */
+ #define R_GPT10_0_GTSWSR_WSGTRGA_Msk      (0x3UL)        /*!< WSGTRGA (Bitfield-Mask: 0x03)                         */
+ #define R_GPT10_0_GTSWSR_WSGTRGB_Pos      (2UL)          /*!< WSGTRGB (Bit 2)                                       */
+ #define R_GPT10_0_GTSWSR_WSGTRGB_Msk      (0xcUL)        /*!< WSGTRGB (Bitfield-Mask: 0x03)                         */
+ #define R_GPT10_0_GTSWSR_WSGTRGC_Pos      (4UL)          /*!< WSGTRGC (Bit 4)                                       */
+ #define R_GPT10_0_GTSWSR_WSGTRGC_Msk      (0x30UL)       /*!< WSGTRGC (Bitfield-Mask: 0x03)                         */
+ #define R_GPT10_0_GTSWSR_WSGTRGD_Pos      (6UL)          /*!< WSGTRGD (Bit 6)                                       */
+ #define R_GPT10_0_GTSWSR_WSGTRGD_Msk      (0xc0UL)       /*!< WSGTRGD (Bitfield-Mask: 0x03)                         */
+ #define R_GPT10_0_GTSWSR_WSELCA_Pos       (16UL)         /*!< WSELCA (Bit 16)                                       */
+ #define R_GPT10_0_GTSWSR_WSELCA_Msk       (0x10000UL)    /*!< WSELCA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSWSR_WSELCB_Pos       (17UL)         /*!< WSELCB (Bit 17)                                       */
+ #define R_GPT10_0_GTSWSR_WSELCB_Msk       (0x20000UL)    /*!< WSELCB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSWSR_WSELCC_Pos       (18UL)         /*!< WSELCC (Bit 18)                                       */
+ #define R_GPT10_0_GTSWSR_WSELCC_Msk       (0x40000UL)    /*!< WSELCC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSWSR_WSELCD_Pos       (19UL)         /*!< WSELCD (Bit 19)                                       */
+ #define R_GPT10_0_GTSWSR_WSELCD_Msk       (0x80000UL)    /*!< WSELCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSWSR_WSELCE_Pos       (20UL)         /*!< WSELCE (Bit 20)                                       */
+ #define R_GPT10_0_GTSWSR_WSELCE_Msk       (0x100000UL)   /*!< WSELCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSWSR_WSELCF_Pos       (21UL)         /*!< WSELCF (Bit 21)                                       */
+ #define R_GPT10_0_GTSWSR_WSELCF_Msk       (0x200000UL)   /*!< WSELCF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSWSR_WSELCG_Pos       (22UL)         /*!< WSELCG (Bit 22)                                       */
+ #define R_GPT10_0_GTSWSR_WSELCG_Msk       (0x400000UL)   /*!< WSELCG (Bitfield-Mask: 0x01)                          */
+ #define R_GPT10_0_GTSWSR_CSELCH_Pos       (23UL)         /*!< CSELCH (Bit 23)                                       */
+ #define R_GPT10_0_GTSWSR_CSELCH_Msk       (0x800000UL)   /*!< CSELCH (Bitfield-Mask: 0x01)                          */
+/* ========================================================  GTSWOS  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  RTCA0CTL0  ======================================================= */
+ #define R_RTC_RTCA0CTL0_RTCA0SLSB_Pos      (4UL)          /*!< RTCA0SLSB (Bit 4)                                     */
+ #define R_RTC_RTCA0CTL0_RTCA0SLSB_Msk      (0x10UL)       /*!< RTCA0SLSB (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL0_RTCA0AMPM_Pos      (5UL)          /*!< RTCA0AMPM (Bit 5)                                     */
+ #define R_RTC_RTCA0CTL0_RTCA0AMPM_Msk      (0x20UL)       /*!< RTCA0AMPM (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL0_RTCA0CEST_Pos      (6UL)          /*!< RTCA0CEST (Bit 6)                                     */
+ #define R_RTC_RTCA0CTL0_RTCA0CEST_Msk      (0x40UL)       /*!< RTCA0CEST (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL0_RTCA0CE_Pos        (7UL)          /*!< RTCA0CE (Bit 7)                                       */
+ #define R_RTC_RTCA0CTL0_RTCA0CE_Msk        (0x80UL)       /*!< RTCA0CE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  RTCA0CTL1  ======================================================= */
+ #define R_RTC_RTCA0CTL1_RTCA0CT_Pos        (0UL)          /*!< RTCA0CT (Bit 0)                                       */
+ #define R_RTC_RTCA0CTL1_RTCA0CT_Msk        (0x7UL)        /*!< RTCA0CT (Bitfield-Mask: 0x07)                         */
+ #define R_RTC_RTCA0CTL1_RTCA01SE_Pos       (3UL)          /*!< RTCA01SE (Bit 3)                                      */
+ #define R_RTC_RTCA0CTL1_RTCA01SE_Msk       (0x8UL)        /*!< RTCA01SE (Bitfield-Mask: 0x01)                        */
+ #define R_RTC_RTCA0CTL1_RTCA0ALME_Pos      (4UL)          /*!< RTCA0ALME (Bit 4)                                     */
+ #define R_RTC_RTCA0CTL1_RTCA0ALME_Msk      (0x10UL)       /*!< RTCA0ALME (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL1_RTCA01HZE_Pos      (5UL)          /*!< RTCA01HZE (Bit 5)                                     */
+ #define R_RTC_RTCA0CTL1_RTCA01HZE_Msk      (0x20UL)       /*!< RTCA01HZE (Bitfield-Mask: 0x01)                       */
+/* =======================================================  RTCA0CTL2  ======================================================= */
+ #define R_RTC_RTCA0CTL2_RTCA0WAIT_Pos      (0UL)          /*!< RTCA0WAIT (Bit 0)                                     */
+ #define R_RTC_RTCA0CTL2_RTCA0WAIT_Msk      (0x1UL)        /*!< RTCA0WAIT (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL2_RTCA0WST_Pos       (1UL)          /*!< RTCA0WST (Bit 1)                                      */
+ #define R_RTC_RTCA0CTL2_RTCA0WST_Msk       (0x2UL)        /*!< RTCA0WST (Bitfield-Mask: 0x01)                        */
+ #define R_RTC_RTCA0CTL2_RTCA0RSUB_Pos      (2UL)          /*!< RTCA0RSUB (Bit 2)                                     */
+ #define R_RTC_RTCA0CTL2_RTCA0RSUB_Msk      (0x4UL)        /*!< RTCA0RSUB (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL2_RTCA0RSST_Pos      (3UL)          /*!< RTCA0RSST (Bit 3)                                     */
+ #define R_RTC_RTCA0CTL2_RTCA0RSST_Msk      (0x8UL)        /*!< RTCA0RSST (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0CTL2_RTCA0WSST_Pos      (4UL)          /*!< RTCA0WSST (Bit 4)                                     */
+ #define R_RTC_RTCA0CTL2_RTCA0WSST_Msk      (0x10UL)       /*!< RTCA0WSST (Bitfield-Mask: 0x01)                       */
+/* =======================================================  RTCA0SUBC  ======================================================= */
+ #define R_RTC_RTCA0SUBC_RTCA0SUBC_Pos      (0UL)          /*!< RTCA0SUBC (Bit 0)                                     */
+ #define R_RTC_RTCA0SUBC_RTCA0SUBC_Msk      (0x3fffffUL)   /*!< RTCA0SUBC (Bitfield-Mask: 0x3fffff)                   */
+/* =======================================================  RTCA0SRBU  ======================================================= */
+ #define R_RTC_RTCA0SRBU_RTCA0SRBU_Pos      (0UL)          /*!< RTCA0SRBU (Bit 0)                                     */
+ #define R_RTC_RTCA0SRBU_RTCA0SRBU_Msk      (0x3fffffUL)   /*!< RTCA0SRBU (Bitfield-Mask: 0x3fffff)                   */
+/* =======================================================  RTCA0SEC  ======================================================== */
+ #define R_RTC_RTCA0SEC_RTCA0SEC_Pos        (0UL)          /*!< RTCA0SEC (Bit 0)                                      */
+ #define R_RTC_RTCA0SEC_RTCA0SEC_Msk        (0x7fUL)       /*!< RTCA0SEC (Bitfield-Mask: 0x7f)                        */
+/* =======================================================  RTCA0MIN  ======================================================== */
+ #define R_RTC_RTCA0MIN_RTCA0MIN_Pos        (0UL)          /*!< RTCA0MIN (Bit 0)                                      */
+ #define R_RTC_RTCA0MIN_RTCA0MIN_Msk        (0x7fUL)       /*!< RTCA0MIN (Bitfield-Mask: 0x7f)                        */
+/* =======================================================  RTCA0HOUR  ======================================================= */
+ #define R_RTC_RTCA0HOUR_RTCA0HOUR_Pos      (0UL)          /*!< RTCA0HOUR (Bit 0)                                     */
+ #define R_RTC_RTCA0HOUR_RTCA0HOUR_Msk      (0x3fUL)       /*!< RTCA0HOUR (Bitfield-Mask: 0x3f)                       */
+/* =======================================================  RTCA0WEEK  ======================================================= */
+ #define R_RTC_RTCA0WEEK_RTCA0WEEK_Pos      (0UL)          /*!< RTCA0WEEK (Bit 0)                                     */
+ #define R_RTC_RTCA0WEEK_RTCA0WEEK_Msk      (0x7UL)        /*!< RTCA0WEEK (Bitfield-Mask: 0x07)                       */
+/* =======================================================  RTCA0DAY  ======================================================== */
+ #define R_RTC_RTCA0DAY_RTCA0DAY_Pos        (0UL)          /*!< RTCA0DAY (Bit 0)                                      */
+ #define R_RTC_RTCA0DAY_RTCA0DAY_Msk        (0x3fUL)       /*!< RTCA0DAY (Bitfield-Mask: 0x3f)                        */
+/* ======================================================  RTCA0MONTH  ======================================================= */
+ #define R_RTC_RTCA0MONTH_RTCA0MONTH_Pos    (0UL)          /*!< RTCA0MONTH (Bit 0)                                    */
+ #define R_RTC_RTCA0MONTH_RTCA0MONTH_Msk    (0x1fUL)       /*!< RTCA0MONTH (Bitfield-Mask: 0x1f)                      */
+/* =======================================================  RTCA0YEAR  ======================================================= */
+ #define R_RTC_RTCA0YEAR_RTCA0YEAR_Pos      (0UL)          /*!< RTCA0YEAR (Bit 0)                                     */
+ #define R_RTC_RTCA0YEAR_RTCA0YEAR_Msk      (0xffUL)       /*!< RTCA0YEAR (Bitfield-Mask: 0xff)                       */
+/* =======================================================  RTCA0TIME  ======================================================= */
+ #define R_RTC_RTCA0TIME_RTCA0SEC_Pos       (0UL)          /*!< RTCA0SEC (Bit 0)                                      */
+ #define R_RTC_RTCA0TIME_RTCA0SEC_Msk       (0xffUL)       /*!< RTCA0SEC (Bitfield-Mask: 0xff)                        */
+ #define R_RTC_RTCA0TIME_RTCA0MIN_Pos       (8UL)          /*!< RTCA0MIN (Bit 8)                                      */
+ #define R_RTC_RTCA0TIME_RTCA0MIN_Msk       (0xff00UL)     /*!< RTCA0MIN (Bitfield-Mask: 0xff)                        */
+ #define R_RTC_RTCA0TIME_RTCA0HOUR_Pos      (16UL)         /*!< RTCA0HOUR (Bit 16)                                    */
+ #define R_RTC_RTCA0TIME_RTCA0HOUR_Msk      (0xff0000UL)   /*!< RTCA0HOUR (Bitfield-Mask: 0xff)                       */
+/* =======================================================  RTCA0CAL  ======================================================== */
+ #define R_RTC_RTCA0CAL_RTCA0WEEK_Pos       (0UL)          /*!< RTCA0WEEK (Bit 0)                                     */
+ #define R_RTC_RTCA0CAL_RTCA0WEEK_Msk       (0xffUL)       /*!< RTCA0WEEK (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0CAL_RTCA0DAY_Pos        (8UL)          /*!< RTCA0DAY (Bit 8)                                      */
+ #define R_RTC_RTCA0CAL_RTCA0DAY_Msk        (0xff00UL)     /*!< RTCA0DAY (Bitfield-Mask: 0xff)                        */
+ #define R_RTC_RTCA0CAL_RTCA0MONTH_Pos      (16UL)         /*!< RTCA0MONTH (Bit 16)                                   */
+ #define R_RTC_RTCA0CAL_RTCA0MONTH_Msk      (0xff0000UL)   /*!< RTCA0MONTH (Bitfield-Mask: 0xff)                      */
+ #define R_RTC_RTCA0CAL_RTCA0YEAR_Pos       (24UL)         /*!< RTCA0YEAR (Bit 24)                                    */
+ #define R_RTC_RTCA0CAL_RTCA0YEAR_Msk       (0xff000000UL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff)                       */
+/* =======================================================  RTCA0SCMP  ======================================================= */
+ #define R_RTC_RTCA0SCMP_RTCA0SCMP_Pos      (0UL)          /*!< RTCA0SCMP (Bit 0)                                     */
+ #define R_RTC_RTCA0SCMP_RTCA0SCMP_Msk      (0x3fffffUL)   /*!< RTCA0SCMP (Bitfield-Mask: 0x3fffff)                   */
+/* =======================================================  RTCA0ALM  ======================================================== */
+ #define R_RTC_RTCA0ALM_RTCA0ALM_Pos        (0UL)          /*!< RTCA0ALM (Bit 0)                                      */
+ #define R_RTC_RTCA0ALM_RTCA0ALM_Msk        (0x7fUL)       /*!< RTCA0ALM (Bitfield-Mask: 0x7f)                        */
+/* =======================================================  RTCA0ALH  ======================================================== */
+ #define R_RTC_RTCA0ALH_RTCA0ALH_Pos        (0UL)          /*!< RTCA0ALH (Bit 0)                                      */
+ #define R_RTC_RTCA0ALH_RTCA0ALH_Msk        (0x3fUL)       /*!< RTCA0ALH (Bitfield-Mask: 0x3f)                        */
+/* =======================================================  RTCA0ALW  ======================================================== */
+ #define R_RTC_RTCA0ALW_RTCA0ALW0_Pos       (0UL)          /*!< RTCA0ALW0 (Bit 0)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW0_Msk       (0x1UL)        /*!< RTCA0ALW0 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW1_Pos       (1UL)          /*!< RTCA0ALW1 (Bit 1)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW1_Msk       (0x2UL)        /*!< RTCA0ALW1 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW2_Pos       (2UL)          /*!< RTCA0ALW2 (Bit 2)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW2_Msk       (0x4UL)        /*!< RTCA0ALW2 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW3_Pos       (3UL)          /*!< RTCA0ALW3 (Bit 3)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW3_Msk       (0x8UL)        /*!< RTCA0ALW3 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW4_Pos       (4UL)          /*!< RTCA0ALW4 (Bit 4)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW4_Msk       (0x10UL)       /*!< RTCA0ALW4 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW5_Pos       (5UL)          /*!< RTCA0ALW5 (Bit 5)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW5_Msk       (0x20UL)       /*!< RTCA0ALW5 (Bitfield-Mask: 0x01)                       */
+ #define R_RTC_RTCA0ALW_RTCA0ALW6_Pos       (6UL)          /*!< RTCA0ALW6 (Bit 6)                                     */
+ #define R_RTC_RTCA0ALW_RTCA0ALW6_Msk       (0x40UL)       /*!< RTCA0ALW6 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  RTCA0SECC  ======================================================= */
+ #define R_RTC_RTCA0SECC_RTCA0SECC_Pos      (0UL)          /*!< RTCA0SECC (Bit 0)                                     */
+ #define R_RTC_RTCA0SECC_RTCA0SECC_Msk      (0x7fUL)       /*!< RTCA0SECC (Bitfield-Mask: 0x7f)                       */
+/* =======================================================  RTCA0MINC  ======================================================= */
+ #define R_RTC_RTCA0MINC_RTCA0MINC_Pos      (0UL)          /*!< RTCA0MINC (Bit 0)                                     */
+ #define R_RTC_RTCA0MINC_RTCA0MINC_Msk      (0x7fUL)       /*!< RTCA0MINC (Bitfield-Mask: 0x7f)                       */
+/* ======================================================  RTCA0HOURC  ======================================================= */
+ #define R_RTC_RTCA0HOURC_RTCA0HOURC_Pos    (0UL)          /*!< RTCA0HOURC (Bit 0)                                    */
+ #define R_RTC_RTCA0HOURC_RTCA0HOURC_Msk    (0x3fUL)       /*!< RTCA0HOURC (Bitfield-Mask: 0x3f)                      */
+/* ======================================================  RTCA0WEEKC  ======================================================= */
+ #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Pos    (0UL)          /*!< RTCA0WEEKC (Bit 0)                                    */
+ #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Msk    (0x7UL)        /*!< RTCA0WEEKC (Bitfield-Mask: 0x07)                      */
+/* =======================================================  RTCA0DAYC  ======================================================= */
+ #define R_RTC_RTCA0DAYC_RTCA0DAYC_Pos      (0UL)          /*!< RTCA0DAYC (Bit 0)                                     */
+ #define R_RTC_RTCA0DAYC_RTCA0DAYC_Msk      (0x3fUL)       /*!< RTCA0DAYC (Bitfield-Mask: 0x3f)                       */
+/* =======================================================  RTCA0MONC  ======================================================= */
+ #define R_RTC_RTCA0MONC_RTCA0MONC_Pos      (0UL)          /*!< RTCA0MONC (Bit 0)                                     */
+ #define R_RTC_RTCA0MONC_RTCA0MONC_Msk      (0x1fUL)       /*!< RTCA0MONC (Bitfield-Mask: 0x1f)                       */
+/* ======================================================  RTCA0YEARC  ======================================================= */
+ #define R_RTC_RTCA0YEARC_RTCA0YEARC_Pos    (0UL)          /*!< RTCA0YEARC (Bit 0)                                    */
+ #define R_RTC_RTCA0YEARC_RTCA0YEARC_Msk    (0xffUL)       /*!< RTCA0YEARC (Bitfield-Mask: 0xff)                      */
+/* ======================================================  RTCA0TIMEC  ======================================================= */
+ #define R_RTC_RTCA0TIMEC_RTCA0SECC_Pos     (0UL)          /*!< RTCA0SECC (Bit 0)                                     */
+ #define R_RTC_RTCA0TIMEC_RTCA0SECC_Msk     (0xffUL)       /*!< RTCA0SECC (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0TIMEC_RTCA0MINC_Pos     (8UL)          /*!< RTCA0MINC (Bit 8)                                     */
+ #define R_RTC_RTCA0TIMEC_RTCA0MINC_Msk     (0xff00UL)     /*!< RTCA0MINC (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Pos    (16UL)         /*!< RTCA0HOURC (Bit 16)                                   */
+ #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Msk    (0xff0000UL)   /*!< RTCA0HOURC (Bitfield-Mask: 0xff)                      */
+/* =======================================================  RTCA0CALC  ======================================================= */
+ #define R_RTC_RTCA0CALC_RTCA0WEEKC_Pos     (0UL)          /*!< RTCA0WEEKC (Bit 0)                                    */
+ #define R_RTC_RTCA0CALC_RTCA0WEEKC_Msk     (0xffUL)       /*!< RTCA0WEEKC (Bitfield-Mask: 0xff)                      */
+ #define R_RTC_RTCA0CALC_RTCA0DAYC_Pos      (8UL)          /*!< RTCA0DAYC (Bit 8)                                     */
+ #define R_RTC_RTCA0CALC_RTCA0DAYC_Msk      (0xff00UL)     /*!< RTCA0DAYC (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0CALC_RTCA0MONC_Pos      (16UL)         /*!< RTCA0MONC (Bit 16)                                    */
+ #define R_RTC_RTCA0CALC_RTCA0MONC_Msk      (0xff0000UL)   /*!< RTCA0MONC (Bitfield-Mask: 0xff)                       */
+ #define R_RTC_RTCA0CALC_RTCA0YEARC_Pos     (24UL)         /*!< RTCA0YEARC (Bit 24)                                   */
+ #define R_RTC_RTCA0CALC_RTCA0YEARC_Msk     (0xff000000UL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG2                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  POEG2GA0  ======================================================== */
+ #define R_POEG2_POEG2GA0_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG2_POEG2GA0_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA0_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG2_POEG2GA0_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA0_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG2_POEG2GA0_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GA0_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG2_POEG2GA0_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GA0_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG2_POEG2GA0_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA0_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG2_POEG2GA0_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA0_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG2_POEG2GA0_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GA0_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG2_POEG2GA0_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG2_POEG2GA0_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG2_POEG2GA0_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GA0_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG2_POEG2GA0_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GA0_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG2_POEG2GA0_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG2GB0  ======================================================== */
+ #define R_POEG2_POEG2GB0_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG2_POEG2GB0_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB0_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG2_POEG2GB0_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB0_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG2_POEG2GB0_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GB0_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG2_POEG2GB0_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GB0_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG2_POEG2GB0_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB0_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG2_POEG2GB0_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB0_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG2_POEG2GB0_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GB0_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG2_POEG2GB0_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG2_POEG2GB0_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG2_POEG2GB0_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GB0_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG2_POEG2GB0_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GB0_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG2_POEG2GB0_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG2GC0  ======================================================== */
+ #define R_POEG2_POEG2GC0_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG2_POEG2GC0_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC0_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG2_POEG2GC0_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC0_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG2_POEG2GC0_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GC0_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG2_POEG2GC0_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GC0_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG2_POEG2GC0_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC0_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG2_POEG2GC0_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC0_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG2_POEG2GC0_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GC0_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG2_POEG2GC0_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG2_POEG2GC0_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG2_POEG2GC0_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GC0_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG2_POEG2GC0_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GC0_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG2_POEG2GC0_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG2GD0  ======================================================== */
+ #define R_POEG2_POEG2GD0_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG2_POEG2GD0_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD0_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG2_POEG2GD0_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD0_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG2_POEG2GD0_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GD0_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG2_POEG2GD0_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GD0_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG2_POEG2GD0_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD0_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG2_POEG2GD0_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD0_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG2_POEG2GD0_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG2_POEG2GD0_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG2_POEG2GD0_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG2_POEG2GD0_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG2_POEG2GD0_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG2_POEG2GD0_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG2_POEG2GD0_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG2_POEG2GD0_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG2_POEG2GD0_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSRAM0                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                           R_OTP                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  OTPPWR  ========================================================= */
+ #define R_OTP_OTPPWR_PWR_Pos           (0UL)          /*!< PWR (Bit 0)                                           */
+ #define R_OTP_OTPPWR_PWR_Msk           (0x1UL)        /*!< PWR (Bitfield-Mask: 0x01)                             */
+ #define R_OTP_OTPPWR_ACCL_Pos          (4UL)          /*!< ACCL (Bit 4)                                          */
+ #define R_OTP_OTPPWR_ACCL_Msk          (0x10UL)       /*!< ACCL (Bitfield-Mask: 0x01)                            */
+/* ========================================================  OTPSTR  ========================================================= */
+ #define R_OTP_OTPSTR_CMD_RDY_Pos       (0UL)          /*!< CMD_RDY (Bit 0)                                       */
+ #define R_OTP_OTPSTR_CMD_RDY_Msk       (0x1UL)        /*!< CMD_RDY (Bitfield-Mask: 0x01)                         */
+ #define R_OTP_OTPSTR_ERR_WR_Pos        (1UL)          /*!< ERR_WR (Bit 1)                                        */
+ #define R_OTP_OTPSTR_ERR_WR_Msk        (0x6UL)        /*!< ERR_WR (Bitfield-Mask: 0x03)                          */
+ #define R_OTP_OTPSTR_ERR_WP_Pos        (3UL)          /*!< ERR_WP (Bit 3)                                        */
+ #define R_OTP_OTPSTR_ERR_WP_Msk        (0x8UL)        /*!< ERR_WP (Bitfield-Mask: 0x01)                          */
+ #define R_OTP_OTPSTR_ERR_RP_Pos        (4UL)          /*!< ERR_RP (Bit 4)                                        */
+ #define R_OTP_OTPSTR_ERR_RP_Msk        (0x10UL)       /*!< ERR_RP (Bitfield-Mask: 0x01)                          */
+ #define R_OTP_OTPSTR_ERR_RDY_WR_Pos    (8UL)          /*!< ERR_RDY_WR (Bit 8)                                    */
+ #define R_OTP_OTPSTR_ERR_RDY_WR_Msk    (0x100UL)      /*!< ERR_RDY_WR (Bitfield-Mask: 0x01)                      */
+ #define R_OTP_OTPSTR_ERR_RDY_RD_Pos    (9UL)          /*!< ERR_RDY_RD (Bit 9)                                    */
+ #define R_OTP_OTPSTR_ERR_RDY_RD_Msk    (0x200UL)      /*!< ERR_RDY_RD (Bitfield-Mask: 0x01)                      */
+ #define R_OTP_OTPSTR_OTP_PWOK_Pos      (12UL)         /*!< OTP_PWOK (Bit 12)                                     */
+ #define R_OTP_OTPSTR_OTP_PWOK_Msk      (0x1000UL)     /*!< OTP_PWOK (Bitfield-Mask: 0x01)                        */
+/* =======================================================  OTPSTAWR  ======================================================== */
+ #define R_OTP_OTPSTAWR_STAWR_Pos       (0UL)          /*!< STAWR (Bit 0)                                         */
+ #define R_OTP_OTPSTAWR_STAWR_Msk       (0x1UL)        /*!< STAWR (Bitfield-Mask: 0x01)                           */
+/* =======================================================  OTPADRWR  ======================================================== */
+ #define R_OTP_OTPADRWR_ADRWR_Pos       (0UL)          /*!< ADRWR (Bit 0)                                         */
+ #define R_OTP_OTPADRWR_ADRWR_Msk       (0x3ffUL)      /*!< ADRWR (Bitfield-Mask: 0x3ff)                          */
+/* =======================================================  OTPDATAWR  ======================================================= */
+ #define R_OTP_OTPDATAWR_DATAWR_Pos     (0UL)          /*!< DATAWR (Bit 0)                                        */
+ #define R_OTP_OTPDATAWR_DATAWR_Msk     (0xffffffffUL) /*!< DATAWR (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  OTPADRRD  ======================================================== */
+ #define R_OTP_OTPADRRD_ADRRD_Pos       (0UL)          /*!< ADRRD (Bit 0)                                         */
+ #define R_OTP_OTPADRRD_ADRRD_Msk       (0x3ffUL)      /*!< ADRRD (Bitfield-Mask: 0x3ff)                          */
+/* =======================================================  OTPDATARD  ======================================================= */
+ #define R_OTP_OTPDATARD_DATARD_Pos     (0UL)          /*!< DATARD (Bit 0)                                        */
+ #define R_OTP_OTPDATARD_DATARD_Msk     (0xffffffffUL) /*!< DATARD (Bitfield-Mask: 0xffffffff)                    */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MPU_AC                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  CPU_CTRL  ======================================================== */
+ #define R_MPU_AC_CPU_CTRL_CR521_CTRL_Pos    (0UL)     /*!< CR521_CTRL (Bit 0)                                    */
+ #define R_MPU_AC_CPU_CTRL_CR521_CTRL_Msk    (0x1UL)   /*!< CR521_CTRL (Bitfield-Mask: 0x01)                      */
+ #define R_MPU_AC_CPU_CTRL_CA550_CTRL_Pos    (8UL)     /*!< CA550_CTRL (Bit 8)                                    */
+ #define R_MPU_AC_CPU_CTRL_CA550_CTRL_Msk    (0x100UL) /*!< CA550_CTRL (Bitfield-Mask: 0x01)                      */
+ #define R_MPU_AC_CPU_CTRL_CA551_CTRL_Pos    (9UL)     /*!< CA551_CTRL (Bit 9)                                    */
+ #define R_MPU_AC_CPU_CTRL_CA551_CTRL_Msk    (0x200UL) /*!< CA551_CTRL (Bitfield-Mask: 0x01)                      */
+ #define R_MPU_AC_CPU_CTRL_CA552_CTRL_Pos    (10UL)    /*!< CA552_CTRL (Bit 10)                                   */
+ #define R_MPU_AC_CPU_CTRL_CA552_CTRL_Msk    (0x400UL) /*!< CA552_CTRL (Bitfield-Mask: 0x01)                      */
+ #define R_MPU_AC_CPU_CTRL_CA553_CTRL_Pos    (11UL)    /*!< CA553_CTRL (Bit 11)                                   */
+ #define R_MPU_AC_CPU_CTRL_CA553_CTRL_Msk    (0x800UL) /*!< CA553_CTRL (Bitfield-Mask: 0x01)                      */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSC_S                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SCKCR2  ========================================================= */
+ #define R_SYSC_S_SCKCR2_CR52CPU0_Pos           (0UL)          /*!< CR52CPU0 (Bit 0)                                      */
+ #define R_SYSC_S_SCKCR2_CR52CPU0_Msk           (0x3UL)        /*!< CR52CPU0 (Bitfield-Mask: 0x03)                        */
+ #define R_SYSC_S_SCKCR2_CR52CPU1_Pos           (2UL)          /*!< CR52CPU1 (Bit 2)                                      */
+ #define R_SYSC_S_SCKCR2_CR52CPU1_Msk           (0xcUL)        /*!< CR52CPU1 (Bitfield-Mask: 0x03)                        */
+ #define R_SYSC_S_SCKCR2_CA55CORE0_Pos          (8UL)          /*!< CA55CORE0 (Bit 8)                                     */
+ #define R_SYSC_S_SCKCR2_CA55CORE0_Msk          (0x100UL)      /*!< CA55CORE0 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_SCKCR2_CA55CORE1_Pos          (9UL)          /*!< CA55CORE1 (Bit 9)                                     */
+ #define R_SYSC_S_SCKCR2_CA55CORE1_Msk          (0x200UL)      /*!< CA55CORE1 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_SCKCR2_CA55CORE2_Pos          (10UL)         /*!< CA55CORE2 (Bit 10)                                    */
+ #define R_SYSC_S_SCKCR2_CA55CORE2_Msk          (0x400UL)      /*!< CA55CORE2 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_SCKCR2_CA55CORE3_Pos          (11UL)         /*!< CA55CORE3 (Bit 11)                                    */
+ #define R_SYSC_S_SCKCR2_CA55CORE3_Msk          (0x800UL)      /*!< CA55CORE3 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_SCKCR2_CA55SCLK_Pos           (12UL)         /*!< CA55SCLK (Bit 12)                                     */
+ #define R_SYSC_S_SCKCR2_CA55SCLK_Msk           (0x1000UL)     /*!< CA55SCLK (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Pos       (16UL)         /*!< SPI3ASYNCSEL (Bit 16)                                 */
+ #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Msk       (0x30000UL)    /*!< SPI3ASYNCSEL (Bitfield-Mask: 0x03)                    */
+ #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Pos       (18UL)         /*!< SCI5ASYNCSEL (Bit 18)                                 */
+ #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Msk       (0xc0000UL)    /*!< SCI5ASYNCSEL (Bitfield-Mask: 0x03)                    */
+/* =========================================================  PMSEL  ========================================================= */
+ #define R_SYSC_S_PMSEL_PMSEL0MON_Pos           (9UL)          /*!< PMSEL0MON (Bit 9)                                     */
+ #define R_SYSC_S_PMSEL_PMSEL0MON_Msk           (0x200UL)      /*!< PMSEL0MON (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_PMSEL_PMSEL1MON_Pos           (10UL)         /*!< PMSEL1MON (Bit 10)                                    */
+ #define R_SYSC_S_PMSEL_PMSEL1MON_Msk           (0x400UL)      /*!< PMSEL1MON (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_PMSEL_PMSEL2MON_Pos           (11UL)         /*!< PMSEL2MON (Bit 11)                                    */
+ #define R_SYSC_S_PMSEL_PMSEL2MON_Msk           (0x800UL)      /*!< PMSEL2MON (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_PMSEL_PMSEL3MON_Pos           (12UL)         /*!< PMSEL3MON (Bit 12)                                    */
+ #define R_SYSC_S_PMSEL_PMSEL3MON_Msk           (0x1000UL)     /*!< PMSEL3MON (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_PMSEL_PMSEL4MON_Pos           (13UL)         /*!< PMSEL4MON (Bit 13)                                    */
+ #define R_SYSC_S_PMSEL_PMSEL4MON_Msk           (0x2000UL)     /*!< PMSEL4MON (Bitfield-Mask: 0x01)                       */
+/* ========================================================  PLL0MON  ======================================================== */
+ #define R_SYSC_S_PLL0MON_PLL0MON_Pos           (0UL)          /*!< PLL0MON (Bit 0)                                       */
+ #define R_SYSC_S_PLL0MON_PLL0MON_Msk           (0x1UL)        /*!< PLL0MON (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PLL0EN  ========================================================= */
+ #define R_SYSC_S_PLL0EN_PLL0EN_Pos             (0UL)          /*!< PLL0EN (Bit 0)                                        */
+ #define R_SYSC_S_PLL0EN_PLL0EN_Msk             (0x1UL)        /*!< PLL0EN (Bitfield-Mask: 0x01)                          */
+/* =====================================================  PLL0_SSC_CTR  ====================================================== */
+ #define R_SYSC_S_PLL0_SSC_CTR_PLL0SSCEN_Pos    (0UL)          /*!< PLL0SSCEN (Bit 0)                                     */
+ #define R_SYSC_S_PLL0_SSC_CTR_PLL0SSCEN_Msk    (0x1UL)        /*!< PLL0SSCEN (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_PLL0_SSC_CTR_PLL0MRR_Pos      (16UL)         /*!< PLL0MRR (Bit 16)                                      */
+ #define R_SYSC_S_PLL0_SSC_CTR_PLL0MRR_Msk      (0x3f0000UL)   /*!< PLL0MRR (Bitfield-Mask: 0x3f)                         */
+ #define R_SYSC_S_PLL0_SSC_CTR_PLL0MFR_Pos      (24UL)         /*!< PLL0MFR (Bit 24)                                      */
+ #define R_SYSC_S_PLL0_SSC_CTR_PLL0MFR_Msk      (0xff000000UL) /*!< PLL0MFR (Bitfield-Mask: 0xff)                         */
+/* ========================================================  PLL1MON  ======================================================== */
+ #define R_SYSC_S_PLL1MON_PLL1MON_Pos           (0UL)          /*!< PLL1MON (Bit 0)                                       */
+ #define R_SYSC_S_PLL1MON_PLL1MON_Msk           (0x1UL)        /*!< PLL1MON (Bitfield-Mask: 0x01)                         */
+/* ========================================================  LOCOCR  ========================================================= */
+ #define R_SYSC_S_LOCOCR_LCSTP_Pos              (0UL)          /*!< LCSTP (Bit 0)                                         */
+ #define R_SYSC_S_LOCOCR_LCSTP_Msk              (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  HIZCTRLEN  ======================================================= */
+ #define R_SYSC_S_HIZCTRLEN_CLMA6MASK_Pos       (0UL)          /*!< CLMA6MASK (Bit 0)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA6MASK_Msk       (0x1UL)        /*!< CLMA6MASK (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Pos       (1UL)          /*!< CLMA0MASK (Bit 1)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Msk       (0x2UL)        /*!< CLMA0MASK (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Pos       (2UL)          /*!< CLMA1MASK (Bit 2)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Msk       (0x4UL)        /*!< CLMA1MASK (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_HIZCTRLEN_CLMA2MASK_Pos       (3UL)          /*!< CLMA2MASK (Bit 3)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA2MASK_Msk       (0x8UL)        /*!< CLMA2MASK (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Pos       (4UL)          /*!< CLMA3MASK (Bit 4)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Msk       (0x10UL)       /*!< CLMA3MASK (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_HIZCTRLEN_CLMA4MASK_Pos       (5UL)          /*!< CLMA4MASK (Bit 5)                                     */
+ #define R_SYSC_S_HIZCTRLEN_CLMA4MASK_Msk       (0x20UL)       /*!< CLMA4MASK (Bitfield-Mask: 0x01)                       */
+/* ========================================================  PLL2MON  ======================================================== */
+ #define R_SYSC_S_PLL2MON_PLL2MON_Pos           (0UL)          /*!< PLL2MON (Bit 0)                                       */
+ #define R_SYSC_S_PLL2MON_PLL2MON_Msk           (0x1UL)        /*!< PLL2MON (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PLL2EN  ========================================================= */
+ #define R_SYSC_S_PLL2EN_PLL2EN_Pos             (0UL)          /*!< PLL2EN (Bit 0)                                        */
+ #define R_SYSC_S_PLL2EN_PLL2EN_Msk             (0x1UL)        /*!< PLL2EN (Bitfield-Mask: 0x01)                          */
+/* =====================================================  PLL2_SSC_CTR  ====================================================== */
+ #define R_SYSC_S_PLL2_SSC_CTR_PLL2SSCEN_Pos    (0UL)          /*!< PLL2SSCEN (Bit 0)                                     */
+ #define R_SYSC_S_PLL2_SSC_CTR_PLL2SSCEN_Msk    (0x1UL)        /*!< PLL2SSCEN (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_PLL2_SSC_CTR_PLL2MRR_Pos      (16UL)         /*!< PLL2MRR (Bit 16)                                      */
+ #define R_SYSC_S_PLL2_SSC_CTR_PLL2MRR_Msk      (0x3f0000UL)   /*!< PLL2MRR (Bitfield-Mask: 0x3f)                         */
+ #define R_SYSC_S_PLL2_SSC_CTR_PLL2MFR_Pos      (24UL)         /*!< PLL2MFR (Bit 24)                                      */
+ #define R_SYSC_S_PLL2_SSC_CTR_PLL2MFR_Msk      (0xff000000UL) /*!< PLL2MFR (Bitfield-Mask: 0xff)                         */
+/* ========================================================  PLL3MON  ======================================================== */
+ #define R_SYSC_S_PLL3MON_PLL3MON_Pos           (0UL)          /*!< PLL3MON (Bit 0)                                       */
+ #define R_SYSC_S_PLL3MON_PLL3MON_Msk           (0x1UL)        /*!< PLL3MON (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PLL3EN  ========================================================= */
+ #define R_SYSC_S_PLL3EN_PLL3EN_Pos             (0UL)          /*!< PLL3EN (Bit 0)                                        */
+ #define R_SYSC_S_PLL3EN_PLL3EN_Msk             (0x1UL)        /*!< PLL3EN (Bitfield-Mask: 0x01)                          */
+/* =====================================================  PLL3_VCO_CTR0  ===================================================== */
+ #define R_SYSC_S_PLL3_VCO_CTR0_PLL3M_Pos       (0UL)          /*!< PLL3M (Bit 0)                                         */
+ #define R_SYSC_S_PLL3_VCO_CTR0_PLL3M_Msk       (0x3ffUL)      /*!< PLL3M (Bitfield-Mask: 0x3ff)                          */
+ #define R_SYSC_S_PLL3_VCO_CTR0_PLL3P_Pos       (16UL)         /*!< PLL3P (Bit 16)                                        */
+ #define R_SYSC_S_PLL3_VCO_CTR0_PLL3P_Msk       (0x3f0000UL)   /*!< PLL3P (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PLL3_VCO_CTR1  ===================================================== */
+ #define R_SYSC_S_PLL3_VCO_CTR1_PLL3S_Pos       (0UL)          /*!< PLL3S (Bit 0)                                         */
+ #define R_SYSC_S_PLL3_VCO_CTR1_PLL3S_Msk       (0x7UL)        /*!< PLL3S (Bitfield-Mask: 0x07)                           */
+ #define R_SYSC_S_PLL3_VCO_CTR1_PLL3K_Pos       (16UL)         /*!< PLL3K (Bit 16)                                        */
+ #define R_SYSC_S_PLL3_VCO_CTR1_PLL3K_Msk       (0xffff0000UL) /*!< PLL3K (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  PLL4MON  ======================================================== */
+ #define R_SYSC_S_PLL4MON_PLL4MON_Pos           (0UL)          /*!< PLL4MON (Bit 0)                                       */
+ #define R_SYSC_S_PLL4MON_PLL4MON_Msk           (0x1UL)        /*!< PLL4MON (Bitfield-Mask: 0x01)                         */
+/* ========================================================  SWRSYS  ========================================================= */
+ #define R_SYSC_S_SWRSYS_SWR_Pos                (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWRSYS_SWR_Msk                (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SWRCPU0  ======================================================== */
+ #define R_SYSC_S_SWRCPU0_SWR_Pos               (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWRCPU0_SWR_Msk               (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SWRCPU1  ======================================================== */
+ #define R_SYSC_S_SWRCPU1_SWR_Pos               (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWRCPU1_SWR_Msk               (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SWR55C  ========================================================= */
+ #define R_SYSC_S_SWR55C_SWR_Pos                (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWR55C_SWR_Msk                (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SWR550  ========================================================= */
+ #define R_SYSC_S_SWR550_SWR_Pos                (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWR550_SWR_Msk                (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SWR551  ========================================================= */
+ #define R_SYSC_S_SWR551_SWR_Pos                (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWR551_SWR_Msk                (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SWR552  ========================================================= */
+ #define R_SYSC_S_SWR552_SWR_Pos                (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWR552_SWR_Msk                (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  SWR553  ========================================================= */
+ #define R_SYSC_S_SWR553_SWR_Pos                (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_SYSC_S_SWR553_SWR_Msk                (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  SWR55ARC  ======================================================== */
+ #define R_SYSC_S_SWR55ARC_ARC550_Pos           (0UL)          /*!< ARC550 (Bit 0)                                        */
+ #define R_SYSC_S_SWR55ARC_ARC550_Msk           (0x1UL)        /*!< ARC550 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_S_SWR55ARC_ARC551_Pos           (1UL)          /*!< ARC551 (Bit 1)                                        */
+ #define R_SYSC_S_SWR55ARC_ARC551_Msk           (0x2UL)        /*!< ARC551 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_S_SWR55ARC_ARC552_Pos           (2UL)          /*!< ARC552 (Bit 2)                                        */
+ #define R_SYSC_S_SWR55ARC_ARC552_Msk           (0x4UL)        /*!< ARC552 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSC_S_SWR55ARC_ARC553_Pos           (3UL)          /*!< ARC553 (Bit 3)                                        */
+ #define R_SYSC_S_SWR55ARC_ARC553_Msk           (0x8UL)        /*!< ARC553 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MRCTLI  ========================================================= */
+ #define R_SYSC_S_MRCTLI_MRCTLI01_Pos           (1UL)          /*!< MRCTLI01 (Bit 1)                                      */
+ #define R_SYSC_S_MRCTLI_MRCTLI01_Msk           (0x2UL)        /*!< MRCTLI01 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_S_MRCTLI_MRCTLI02_Pos           (2UL)          /*!< MRCTLI02 (Bit 2)                                      */
+ #define R_SYSC_S_MRCTLI_MRCTLI02_Msk           (0x4UL)        /*!< MRCTLI02 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSC_S_MRCTLI_MRCTLI03_Pos           (3UL)          /*!< MRCTLI03 (Bit 3)                                      */
+ #define R_SYSC_S_MRCTLI_MRCTLI03_Msk           (0x8UL)        /*!< MRCTLI03 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MSTPCRG  ======================================================== */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG00_Pos         (0UL)          /*!< MSTPCRG00 (Bit 0)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG00_Msk         (0x1UL)        /*!< MSTPCRG00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG01_Pos         (1UL)          /*!< MSTPCRG01 (Bit 1)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG01_Msk         (0x2UL)        /*!< MSTPCRG01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG02_Pos         (2UL)          /*!< MSTPCRG02 (Bit 2)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG02_Msk         (0x4UL)        /*!< MSTPCRG02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG03_Pos         (3UL)          /*!< MSTPCRG03 (Bit 3)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG03_Msk         (0x8UL)        /*!< MSTPCRG03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG04_Pos         (4UL)          /*!< MSTPCRG04 (Bit 4)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG04_Msk         (0x10UL)       /*!< MSTPCRG04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG05_Pos         (5UL)          /*!< MSTPCRG05 (Bit 5)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG05_Msk         (0x20UL)       /*!< MSTPCRG05 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG08_Pos         (8UL)          /*!< MSTPCRG08 (Bit 8)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG08_Msk         (0x100UL)      /*!< MSTPCRG08 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG09_Pos         (9UL)          /*!< MSTPCRG09 (Bit 9)                                     */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG09_Msk         (0x200UL)      /*!< MSTPCRG09 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG10_Pos         (10UL)         /*!< MSTPCRG10 (Bit 10)                                    */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG10_Msk         (0x400UL)      /*!< MSTPCRG10 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG11_Pos         (11UL)         /*!< MSTPCRG11 (Bit 11)                                    */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG11_Msk         (0x800UL)      /*!< MSTPCRG11 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG12_Pos         (12UL)         /*!< MSTPCRG12 (Bit 12)                                    */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG12_Msk         (0x1000UL)     /*!< MSTPCRG12 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG13_Pos         (13UL)         /*!< MSTPCRG13 (Bit 13)                                    */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG13_Msk         (0x2000UL)     /*!< MSTPCRG13 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG14_Pos         (14UL)         /*!< MSTPCRG14 (Bit 14)                                    */
+ #define R_SYSC_S_MSTPCRG_MSTPCRG14_Msk         (0x4000UL)     /*!< MSTPCRG14 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRI  ======================================================== */
+ #define R_SYSC_S_MSTPCRI_MSTPCRI01_Pos         (1UL)          /*!< MSTPCRI01 (Bit 1)                                     */
+ #define R_SYSC_S_MSTPCRI_MSTPCRI01_Msk         (0x2UL)        /*!< MSTPCRI01 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  MSTPCRN  ======================================================== */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN00_Pos         (0UL)          /*!< MSTPCRN00 (Bit 0)                                     */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN00_Msk         (0x1UL)        /*!< MSTPCRN00 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN01_Pos         (1UL)          /*!< MSTPCRN01 (Bit 1)                                     */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN01_Msk         (0x2UL)        /*!< MSTPCRN01 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN02_Pos         (2UL)          /*!< MSTPCRN02 (Bit 2)                                     */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN02_Msk         (0x4UL)        /*!< MSTPCRN02 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN03_Pos         (3UL)          /*!< MSTPCRN03 (Bit 3)                                     */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN03_Msk         (0x8UL)        /*!< MSTPCRN03 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN04_Pos         (4UL)          /*!< MSTPCRN04 (Bit 4)                                     */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN04_Msk         (0x10UL)       /*!< MSTPCRN04 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN05_Pos         (5UL)          /*!< MSTPCRN05 (Bit 5)                                     */
+ #define R_SYSC_S_MSTPCRN_MSTPCRN05_Msk         (0x20UL)       /*!< MSTPCRN05 (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CLMA0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CTL0  ========================================================== */
+ #define R_CLMA0_CTL0_CLME_Pos       (0UL)     /*!< CLME (Bit 0)                                          */
+ #define R_CLMA0_CTL0_CLME_Msk       (0x1UL)   /*!< CLME (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CMPL  ========================================================== */
+ #define R_CLMA0_CMPL_CMPL_Pos       (0UL)     /*!< CMPL (Bit 0)                                          */
+ #define R_CLMA0_CMPL_CMPL_Msk       (0xfffUL) /*!< CMPL (Bitfield-Mask: 0xfff)                           */
+/* =========================================================  CMPH  ========================================================== */
+ #define R_CLMA0_CMPH_CMPH_Pos       (0UL)     /*!< CMPH (Bit 0)                                          */
+ #define R_CLMA0_CMPH_CMPH_Msk       (0xfffUL) /*!< CMPH (Bitfield-Mask: 0xfff)                           */
+/* =========================================================  PCMD  ========================================================== */
+/* ========================================================  PROTSR  ========================================================= */
+ #define R_CLMA0_PROTSR_PRERR_Pos    (0UL)     /*!< PRERR (Bit 0)                                         */
+ #define R_CLMA0_PROTSR_PRERR_Msk    (0x1UL)   /*!< PRERR (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADXC0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  ADXCTL0  ======================================================== */
+ #define R_ADXC0_ADXCTL0_PCIE0MIR_Pos    (0UL)          /*!< PCIE0MIR (Bit 0)                                      */
+ #define R_ADXC0_ADXCTL0_PCIE0MIR_Msk    (0x1fUL)       /*!< PCIE0MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL0_PCIE1MIR_Pos    (8UL)          /*!< PCIE1MIR (Bit 8)                                      */
+ #define R_ADXC0_ADXCTL0_PCIE1MIR_Msk    (0x1f00UL)     /*!< PCIE1MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL0_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC0_ADXCTL0_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC0_ADXCTL0_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC0_ADXCTL0_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  ADXCTL1  ======================================================== */
+ #define R_ADXC0_ADXCTL1_PCIE0MIR_Pos    (0UL)          /*!< PCIE0MIR (Bit 0)                                      */
+ #define R_ADXC0_ADXCTL1_PCIE0MIR_Msk    (0x1fUL)       /*!< PCIE0MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL1_PCIE1MIR_Pos    (8UL)          /*!< PCIE1MIR (Bit 8)                                      */
+ #define R_ADXC0_ADXCTL1_PCIE1MIR_Msk    (0x1f00UL)     /*!< PCIE1MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL1_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC0_ADXCTL1_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC0_ADXCTL1_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC0_ADXCTL1_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  ADXCTL2  ======================================================== */
+ #define R_ADXC0_ADXCTL2_PCIE0MIR_Pos    (0UL)          /*!< PCIE0MIR (Bit 0)                                      */
+ #define R_ADXC0_ADXCTL2_PCIE0MIR_Msk    (0x1fUL)       /*!< PCIE0MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL2_PCIE1MIR_Pos    (8UL)          /*!< PCIE1MIR (Bit 8)                                      */
+ #define R_ADXC0_ADXCTL2_PCIE1MIR_Msk    (0x1f00UL)     /*!< PCIE1MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL2_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC0_ADXCTL2_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC0_ADXCTL2_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC0_ADXCTL2_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  ADXCTL3  ======================================================== */
+ #define R_ADXC0_ADXCTL3_PCIE0MIR_Pos    (0UL)          /*!< PCIE0MIR (Bit 0)                                      */
+ #define R_ADXC0_ADXCTL3_PCIE0MIR_Msk    (0x1fUL)       /*!< PCIE0MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL3_PCIE1MIR_Pos    (8UL)          /*!< PCIE1MIR (Bit 8)                                      */
+ #define R_ADXC0_ADXCTL3_PCIE1MIR_Msk    (0x1f00UL)     /*!< PCIE1MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL3_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC0_ADXCTL3_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC0_ADXCTL3_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC0_ADXCTL3_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  ADXCTL4  ======================================================== */
+ #define R_ADXC0_ADXCTL4_PCIE0MIR_Pos    (0UL)          /*!< PCIE0MIR (Bit 0)                                      */
+ #define R_ADXC0_ADXCTL4_PCIE0MIR_Msk    (0x1fUL)       /*!< PCIE0MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL4_PCIE1MIR_Pos    (8UL)          /*!< PCIE1MIR (Bit 8)                                      */
+ #define R_ADXC0_ADXCTL4_PCIE1MIR_Msk    (0x1f00UL)     /*!< PCIE1MIR (Bitfield-Mask: 0x1f)                        */
+ #define R_ADXC0_ADXCTL4_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC0_ADXCTL4_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC0_ADXCTL4_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC0_ADXCTL4_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  ADXCTL5  ======================================================== */
+ #define R_ADXC0_ADXCTL5_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC0_ADXCTL5_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC0_ADXCTL5_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC0_ADXCTL5_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_SSC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SSTPCR4  ======================================================== */
+ #define R_SSC_SSTPCR4_DDRR2_REQ_Pos     (0UL)        /*!< DDRR2_REQ (Bit 0)                                     */
+ #define R_SSC_SSTPCR4_DDRR2_REQ_Msk     (0x1UL)      /*!< DDRR2_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR4_DDRR2_ACK_Pos     (1UL)        /*!< DDRR2_ACK (Bit 1)                                     */
+ #define R_SSC_SSTPCR4_DDRR2_ACK_Msk     (0x2UL)      /*!< DDRR2_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR4_DDRR3_REQ_Pos     (4UL)        /*!< DDRR3_REQ (Bit 4)                                     */
+ #define R_SSC_SSTPCR4_DDRR3_REQ_Msk     (0x10UL)     /*!< DDRR3_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR4_DDRR3_ACK_Pos     (5UL)        /*!< DDRR3_ACK (Bit 5)                                     */
+ #define R_SSC_SSTPCR4_DDRR3_ACK_Msk     (0x20UL)     /*!< DDRR3_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR4_DDRAPB_Pos        (8UL)        /*!< DDRAPB (Bit 8)                                        */
+ #define R_SSC_SSTPCR4_DDRAPB_Msk        (0x100UL)    /*!< DDRAPB (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SSTPCR5  ======================================================== */
+ #define R_SSC_SSTPCR5_GIC600_REQ_Pos    (16UL)       /*!< GIC600_REQ (Bit 16)                                   */
+ #define R_SSC_SSTPCR5_GIC600_REQ_Msk    (0x10000UL)  /*!< GIC600_REQ (Bitfield-Mask: 0x01)                      */
+ #define R_SSC_SSTPCR5_GIC600_ACK_Pos    (17UL)       /*!< GIC600_ACK (Bit 17)                                   */
+ #define R_SSC_SSTPCR5_GIC600_ACK_Msk    (0x20000UL)  /*!< GIC600_ACK (Bitfield-Mask: 0x01)                      */
+/* ========================================================  SSTPCR6  ======================================================== */
+ #define R_SSC_SSTPCR6_XSPI0_REQ_Pos     (0UL)        /*!< XSPI0_REQ (Bit 0)                                     */
+ #define R_SSC_SSTPCR6_XSPI0_REQ_Msk     (0x1UL)      /*!< XSPI0_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR6_XSPI0_ACK_Pos     (1UL)        /*!< XSPI0_ACK (Bit 1)                                     */
+ #define R_SSC_SSTPCR6_XSPI0_ACK_Msk     (0x2UL)      /*!< XSPI0_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR6_XSPI1_REQ_Pos     (4UL)        /*!< XSPI1_REQ (Bit 4)                                     */
+ #define R_SSC_SSTPCR6_XSPI1_REQ_Msk     (0x10UL)     /*!< XSPI1_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR6_XSPI1_ACK_Pos     (5UL)        /*!< XSPI1_ACK (Bit 5)                                     */
+ #define R_SSC_SSTPCR6_XSPI1_ACK_Msk     (0x20UL)     /*!< XSPI1_ACK (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SSTPCR7  ======================================================== */
+ #define R_SSC_SSTPCR7_AXIS0_REQ_Pos     (0UL)        /*!< AXIS0_REQ (Bit 0)                                     */
+ #define R_SSC_SSTPCR7_AXIS0_REQ_Msk     (0x1UL)      /*!< AXIS0_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR7_AXIS0_ACK_Pos     (1UL)        /*!< AXIS0_ACK (Bit 1)                                     */
+ #define R_SSC_SSTPCR7_AXIS0_ACK_Msk     (0x2UL)      /*!< AXIS0_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR7_AXIS1_REQ_Pos     (4UL)        /*!< AXIS1_REQ (Bit 4)                                     */
+ #define R_SSC_SSTPCR7_AXIS1_REQ_Msk     (0x10UL)     /*!< AXIS1_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR7_AXIS1_ACK_Pos     (5UL)        /*!< AXIS1_ACK (Bit 5)                                     */
+ #define R_SSC_SSTPCR7_AXIS1_ACK_Msk     (0x20UL)     /*!< AXIS1_ACK (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SSTPCR0  ======================================================== */
+ #define R_SSC_SSTPCR0_DDRA0_REQ_Pos     (0UL)        /*!< DDRA0_REQ (Bit 0)                                     */
+ #define R_SSC_SSTPCR0_DDRA0_REQ_Msk     (0x1UL)      /*!< DDRA0_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR0_DDRA0_ACK_Pos     (1UL)        /*!< DDRA0_ACK (Bit 1)                                     */
+ #define R_SSC_SSTPCR0_DDRA0_ACK_Msk     (0x2UL)      /*!< DDRA0_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR0_DDRA1_REQ_Pos     (4UL)        /*!< DDRA1_REQ (Bit 4)                                     */
+ #define R_SSC_SSTPCR0_DDRA1_REQ_Msk     (0x10UL)     /*!< DDRA1_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR0_DDRA1_ACK_Pos     (5UL)        /*!< DDRA1_ACK (Bit 5)                                     */
+ #define R_SSC_SSTPCR0_DDRA1_ACK_Msk     (0x20UL)     /*!< DDRA1_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR0_DDRA4_REQ_Pos     (8UL)        /*!< DDRA4_REQ (Bit 8)                                     */
+ #define R_SSC_SSTPCR0_DDRA4_REQ_Msk     (0x100UL)    /*!< DDRA4_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR0_DDRA4_ACK_Pos     (9UL)        /*!< DDRA4_ACK (Bit 9)                                     */
+ #define R_SSC_SSTPCR0_DDRA4_ACK_Msk     (0x200UL)    /*!< DDRA4_ACK (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SSTPCR1  ======================================================== */
+ #define R_SSC_SSTPCR1_PCIE0_REQ_Pos     (0UL)        /*!< PCIE0_REQ (Bit 0)                                     */
+ #define R_SSC_SSTPCR1_PCIE0_REQ_Msk     (0x1UL)      /*!< PCIE0_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR1_PCIE0_ACK_Pos     (1UL)        /*!< PCIE0_ACK (Bit 1)                                     */
+ #define R_SSC_SSTPCR1_PCIE0_ACK_Msk     (0x2UL)      /*!< PCIE0_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR1_PCIE1_REQ_Pos     (4UL)        /*!< PCIE1_REQ (Bit 4)                                     */
+ #define R_SSC_SSTPCR1_PCIE1_REQ_Msk     (0x10UL)     /*!< PCIE1_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR1_PCIE1_ACK_Pos     (5UL)        /*!< PCIE1_ACK (Bit 5)                                     */
+ #define R_SSC_SSTPCR1_PCIE1_ACK_Msk     (0x20UL)     /*!< PCIE1_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR1_SDHI0_REQ_Pos     (16UL)       /*!< SDHI0_REQ (Bit 16)                                    */
+ #define R_SSC_SSTPCR1_SDHI0_REQ_Msk     (0x10000UL)  /*!< SDHI0_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR1_SDHI0_ACK_Pos     (17UL)       /*!< SDHI0_ACK (Bit 17)                                    */
+ #define R_SSC_SSTPCR1_SDHI0_ACK_Msk     (0x20000UL)  /*!< SDHI0_ACK (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR1_SDHI1_REQ_Pos     (20UL)       /*!< SDHI1_REQ (Bit 20)                                    */
+ #define R_SSC_SSTPCR1_SDHI1_REQ_Msk     (0x100000UL) /*!< SDHI1_REQ (Bitfield-Mask: 0x01)                       */
+ #define R_SSC_SSTPCR1_SDHI1_ACK_Pos     (21UL)       /*!< SDHI1_ACK (Bit 21)                                    */
+ #define R_SSC_SSTPCR1_SDHI1_ACK_Msk     (0x200000UL) /*!< SDHI1_ACK (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MSAC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  MSTACCCTL2  ======================================================= */
+ #define R_MSAC_MSTACCCTL2_CSAXIAP_PROT0_Pos    (0UL)          /*!< CSAXIAP_PROT0 (Bit 0)                                 */
+ #define R_MSAC_MSTACCCTL2_CSAXIAP_PROT0_Msk    (0x1UL)        /*!< CSAXIAP_PROT0 (Bitfield-Mask: 0x01)                   */
+ #define R_MSAC_MSTACCCTL2_CSAXIAP_PROT1_Pos    (1UL)          /*!< CSAXIAP_PROT1 (Bit 1)                                 */
+ #define R_MSAC_MSTACCCTL2_CSAXIAP_PROT1_Msk    (0x2UL)        /*!< CSAXIAP_PROT1 (Bitfield-Mask: 0x01)                   */
+ #define R_MSAC_MSTACCCTL2_CSAXIAP_SEL0_Pos     (2UL)          /*!< CSAXIAP_SEL0 (Bit 2)                                  */
+ #define R_MSAC_MSTACCCTL2_CSAXIAP_SEL0_Msk     (0x4UL)        /*!< CSAXIAP_SEL0 (Bitfield-Mask: 0x01)                    */
+ #define R_MSAC_MSTACCCTL2_CSAXIAP_SEL1_Pos     (3UL)          /*!< CSAXIAP_SEL1 (Bit 3)                                  */
+ #define R_MSAC_MSTACCCTL2_CSAXIAP_SEL1_Msk     (0x8UL)        /*!< CSAXIAP_SEL1 (Bitfield-Mask: 0x01)                    */
+ #define R_MSAC_MSTACCCTL2_GMAC0_PROT0_Pos      (4UL)          /*!< GMAC0_PROT0 (Bit 4)                                   */
+ #define R_MSAC_MSTACCCTL2_GMAC0_PROT0_Msk      (0x10UL)       /*!< GMAC0_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_GMAC0_PROT1_Pos      (5UL)          /*!< GMAC0_PROT1 (Bit 5)                                   */
+ #define R_MSAC_MSTACCCTL2_GMAC0_PROT1_Msk      (0x20UL)       /*!< GMAC0_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_GMAC0_SEL0_Pos       (6UL)          /*!< GMAC0_SEL0 (Bit 6)                                    */
+ #define R_MSAC_MSTACCCTL2_GMAC0_SEL0_Msk       (0x40UL)       /*!< GMAC0_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_GMAC0_SEL1_Pos       (7UL)          /*!< GMAC0_SEL1 (Bit 7)                                    */
+ #define R_MSAC_MSTACCCTL2_GMAC0_SEL1_Msk       (0x80UL)       /*!< GMAC0_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_DMAC0_PROT0_Pos      (12UL)         /*!< DMAC0_PROT0 (Bit 12)                                  */
+ #define R_MSAC_MSTACCCTL2_DMAC0_PROT0_Msk      (0x1000UL)     /*!< DMAC0_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_DMAC0_PROT1_Pos      (13UL)         /*!< DMAC0_PROT1 (Bit 13)                                  */
+ #define R_MSAC_MSTACCCTL2_DMAC0_PROT1_Msk      (0x2000UL)     /*!< DMAC0_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_DMAC0_SEL0_Pos       (14UL)         /*!< DMAC0_SEL0 (Bit 14)                                   */
+ #define R_MSAC_MSTACCCTL2_DMAC0_SEL0_Msk       (0x4000UL)     /*!< DMAC0_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_DMAC0_SEL1_Pos       (15UL)         /*!< DMAC0_SEL1 (Bit 15)                                   */
+ #define R_MSAC_MSTACCCTL2_DMAC0_SEL1_Msk       (0x8000UL)     /*!< DMAC0_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_DMAC1_PROT0_Pos      (16UL)         /*!< DMAC1_PROT0 (Bit 16)                                  */
+ #define R_MSAC_MSTACCCTL2_DMAC1_PROT0_Msk      (0x10000UL)    /*!< DMAC1_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_DMAC1_PROT1_Pos      (17UL)         /*!< DMAC1_PROT1 (Bit 17)                                  */
+ #define R_MSAC_MSTACCCTL2_DMAC1_PROT1_Msk      (0x20000UL)    /*!< DMAC1_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_DMAC1_SEL0_Pos       (18UL)         /*!< DMAC1_SEL0 (Bit 18)                                   */
+ #define R_MSAC_MSTACCCTL2_DMAC1_SEL0_Msk       (0x40000UL)    /*!< DMAC1_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_DMAC1_SEL1_Pos       (19UL)         /*!< DMAC1_SEL1 (Bit 19)                                   */
+ #define R_MSAC_MSTACCCTL2_DMAC1_SEL1_Msk       (0x80000UL)    /*!< DMAC1_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_DMAC2_PROT0_Pos      (20UL)         /*!< DMAC2_PROT0 (Bit 20)                                  */
+ #define R_MSAC_MSTACCCTL2_DMAC2_PROT0_Msk      (0x100000UL)   /*!< DMAC2_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_DMAC2_PROT1_Pos      (21UL)         /*!< DMAC2_PROT1 (Bit 21)                                  */
+ #define R_MSAC_MSTACCCTL2_DMAC2_PROT1_Msk      (0x200000UL)   /*!< DMAC2_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_DMAC2_SEL0_Pos       (22UL)         /*!< DMAC2_SEL0 (Bit 22)                                   */
+ #define R_MSAC_MSTACCCTL2_DMAC2_SEL0_Msk       (0x400000UL)   /*!< DMAC2_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_DMAC2_SEL1_Pos       (23UL)         /*!< DMAC2_SEL1 (Bit 23)                                   */
+ #define R_MSAC_MSTACCCTL2_DMAC2_SEL1_Msk       (0x800000UL)   /*!< DMAC2_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_CR520_PROT0_Pos      (24UL)         /*!< CR520_PROT0 (Bit 24)                                  */
+ #define R_MSAC_MSTACCCTL2_CR520_PROT0_Msk      (0x1000000UL)  /*!< CR520_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_CR520_PROT1_Pos      (25UL)         /*!< CR520_PROT1 (Bit 25)                                  */
+ #define R_MSAC_MSTACCCTL2_CR520_PROT1_Msk      (0x2000000UL)  /*!< CR520_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_CR520_SEL0_Pos       (26UL)         /*!< CR520_SEL0 (Bit 26)                                   */
+ #define R_MSAC_MSTACCCTL2_CR520_SEL0_Msk       (0x4000000UL)  /*!< CR520_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_CR520_SEL1_Pos       (27UL)         /*!< CR520_SEL1 (Bit 27)                                   */
+ #define R_MSAC_MSTACCCTL2_CR520_SEL1_Msk       (0x8000000UL)  /*!< CR520_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_CR521_PROT0_Pos      (28UL)         /*!< CR521_PROT0 (Bit 28)                                  */
+ #define R_MSAC_MSTACCCTL2_CR521_PROT0_Msk      (0x10000000UL) /*!< CR521_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_CR521_PROT1_Pos      (29UL)         /*!< CR521_PROT1 (Bit 29)                                  */
+ #define R_MSAC_MSTACCCTL2_CR521_PROT1_Msk      (0x20000000UL) /*!< CR521_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL2_CR521_SEL0_Pos       (30UL)         /*!< CR521_SEL0 (Bit 30)                                   */
+ #define R_MSAC_MSTACCCTL2_CR521_SEL0_Msk       (0x40000000UL) /*!< CR521_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL2_CR521_SEL1x_Pos      (31UL)         /*!< CR521_SEL1x (Bit 31)                                  */
+ #define R_MSAC_MSTACCCTL2_CR521_SEL1x_Msk      (0x80000000UL) /*!< CR521_SEL1x (Bitfield-Mask: 0x01)                     */
+/* ======================================================  MSTACCCTL3  ======================================================= */
+ #define R_MSAC_MSTACCCTL3_SHOSTIF_PROT0_Pos    (0UL)          /*!< SHOSTIF_PROT0 (Bit 0)                                 */
+ #define R_MSAC_MSTACCCTL3_SHOSTIF_PROT0_Msk    (0x1UL)        /*!< SHOSTIF_PROT0 (Bitfield-Mask: 0x01)                   */
+ #define R_MSAC_MSTACCCTL3_SHOSTIF_PROT1_Pos    (1UL)          /*!< SHOSTIF_PROT1 (Bit 1)                                 */
+ #define R_MSAC_MSTACCCTL3_SHOSTIF_PROT1_Msk    (0x2UL)        /*!< SHOSTIF_PROT1 (Bitfield-Mask: 0x01)                   */
+ #define R_MSAC_MSTACCCTL3_SHOSTIF_SEL_Pos      (3UL)          /*!< SHOSTIF_SEL (Bit 3)                                   */
+ #define R_MSAC_MSTACCCTL3_SHOSTIF_SEL_Msk      (0x8UL)        /*!< SHOSTIF_SEL (Bitfield-Mask: 0x01)                     */
+/* ======================================================  SLVACCCTL6  ======================================================= */
+ #define R_MSAC_SLVACCCTL6_ETHSS_SL_Pos         (0UL)          /*!< ETHSS_SL (Bit 0)                                      */
+ #define R_MSAC_SLVACCCTL6_ETHSS_SL_Msk         (0x3UL)        /*!< ETHSS_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL6_ETHSW_SL_Pos         (2UL)          /*!< ETHSW_SL (Bit 2)                                      */
+ #define R_MSAC_SLVACCCTL6_ETHSW_SL_Msk         (0xcUL)        /*!< ETHSW_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL6_ESC_SL_Pos           (4UL)          /*!< ESC_SL (Bit 4)                                        */
+ #define R_MSAC_SLVACCCTL6_ESC_SL_Msk           (0x30UL)       /*!< ESC_SL (Bitfield-Mask: 0x03)                          */
+ #define R_MSAC_SLVACCCTL6_GMAC0_SL_Pos         (6UL)          /*!< GMAC0_SL (Bit 6)                                      */
+ #define R_MSAC_SLVACCCTL6_GMAC0_SL_Msk         (0xc0UL)       /*!< GMAC0_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL6_CA55_SL_Pos          (10UL)         /*!< CA55_SL (Bit 10)                                      */
+ #define R_MSAC_SLVACCCTL6_CA55_SL_Msk          (0xc00UL)      /*!< CA55_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL6_CR520_SL_Pos         (12UL)         /*!< CR520_SL (Bit 12)                                     */
+ #define R_MSAC_SLVACCCTL6_CR520_SL_Msk         (0x3000UL)     /*!< CR520_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL6_CR521_SL_Pos         (14UL)         /*!< CR521_SL (Bit 14)                                     */
+ #define R_MSAC_SLVACCCTL6_CR521_SL_Msk         (0xc000UL)     /*!< CR521_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL6_DMAC0_SL_Pos         (16UL)         /*!< DMAC0_SL (Bit 16)                                     */
+ #define R_MSAC_SLVACCCTL6_DMAC0_SL_Msk         (0x30000UL)    /*!< DMAC0_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL6_DMAC1_SL_Pos         (18UL)         /*!< DMAC1_SL (Bit 18)                                     */
+ #define R_MSAC_SLVACCCTL6_DMAC1_SL_Msk         (0xc0000UL)    /*!< DMAC1_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL6_DMAC2_SL_Pos         (20UL)         /*!< DMAC2_SL (Bit 20)                                     */
+ #define R_MSAC_SLVACCCTL6_DMAC2_SL_Msk         (0x300000UL)   /*!< DMAC2_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL6_SYSRAM0_SL_Pos       (24UL)         /*!< SYSRAM0_SL (Bit 24)                                   */
+ #define R_MSAC_SLVACCCTL6_SYSRAM0_SL_Msk       (0x3000000UL)  /*!< SYSRAM0_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL6_SYSRAM1_SL_Pos       (26UL)         /*!< SYSRAM1_SL (Bit 26)                                   */
+ #define R_MSAC_SLVACCCTL6_SYSRAM1_SL_Msk       (0xc000000UL)  /*!< SYSRAM1_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL6_SYSRAM2_SL_Pos       (28UL)         /*!< SYSRAM2_SL (Bit 28)                                   */
+ #define R_MSAC_SLVACCCTL6_SYSRAM2_SL_Msk       (0x30000000UL) /*!< SYSRAM2_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL6_SYSRAM3_SL_Pos       (30UL)         /*!< SYSRAM3_SL (Bit 30)                                   */
+ #define R_MSAC_SLVACCCTL6_SYSRAM3_SL_Msk       (0xc0000000UL) /*!< SYSRAM3_SL (Bitfield-Mask: 0x03)                      */
+/* ======================================================  SLVACCCTL7  ======================================================= */
+ #define R_MSAC_SLVACCCTL7_MBXSEM_SL_Pos        (0UL)          /*!< MBXSEM_SL (Bit 0)                                     */
+ #define R_MSAC_SLVACCCTL7_MBXSEM_SL_Msk        (0x3UL)        /*!< MBXSEM_SL (Bitfield-Mask: 0x03)                       */
+ #define R_MSAC_SLVACCCTL7_SHOSTIF_SL_Pos       (2UL)          /*!< SHOSTIF_SL (Bit 2)                                    */
+ #define R_MSAC_SLVACCCTL7_SHOSTIF_SL_Msk       (0xcUL)        /*!< SHOSTIF_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL7_LLPP_SL_Pos          (18UL)         /*!< LLPP_SL (Bit 18)                                      */
+ #define R_MSAC_SLVACCCTL7_LLPP_SL_Msk          (0xc0000UL)    /*!< LLPP_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL7_BUS_SL_Pos           (22UL)         /*!< BUS_SL (Bit 22)                                       */
+ #define R_MSAC_SLVACCCTL7_BUS_SL_Msk           (0xc00000UL)   /*!< BUS_SL (Bitfield-Mask: 0x03)                          */
+ #define R_MSAC_SLVACCCTL7_RSIP_SL_Pos          (24UL)         /*!< RSIP_SL (Bit 24)                                      */
+ #define R_MSAC_SLVACCCTL7_RSIP_SL_Msk          (0x3000000UL)  /*!< RSIP_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL7_OTP_SL_Pos           (26UL)         /*!< OTP_SL (Bit 26)                                       */
+ #define R_MSAC_SLVACCCTL7_OTP_SL_Msk           (0xc000000UL)  /*!< OTP_SL (Bitfield-Mask: 0x03)                          */
+ #define R_MSAC_SLVACCCTL7_GIC600_SL_Pos        (28UL)         /*!< GIC600_SL (Bit 28)                                    */
+ #define R_MSAC_SLVACCCTL7_GIC600_SL_Msk        (0x30000000UL) /*!< GIC600_SL (Bitfield-Mask: 0x03)                       */
+ #define R_MSAC_SLVACCCTL7_CSDBGAPB_SL_Pos      (30UL)         /*!< CSDBGAPB_SL (Bit 30)                                  */
+ #define R_MSAC_SLVACCCTL7_CSDBGAPB_SL_Msk      (0xc0000000UL) /*!< CSDBGAPB_SL (Bitfield-Mask: 0x03)                     */
+/* ======================================================  SLVACCCTL8  ======================================================= */
+ #define R_MSAC_SLVACCCTL8_DDRCTRL_SL_Pos       (0UL)          /*!< DDRCTRL_SL (Bit 0)                                    */
+ #define R_MSAC_SLVACCCTL8_DDRCTRL_SL_Msk       (0x3UL)        /*!< DDRCTRL_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL8_TZCTCM_SL_Pos        (4UL)          /*!< TZCTCM_SL (Bit 4)                                     */
+ #define R_MSAC_SLVACCCTL8_TZCTCM_SL_Msk        (0x30UL)       /*!< TZCTCM_SL (Bitfield-Mask: 0x03)                       */
+ #define R_MSAC_SLVACCCTL8_TZCDDRR2_SL_Pos      (6UL)          /*!< TZCDDRR2_SL (Bit 6)                                   */
+ #define R_MSAC_SLVACCCTL8_TZCDDRR2_SL_Msk      (0xc0UL)       /*!< TZCDDRR2_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL8_TZCDDRR3_SL_Pos      (8UL)          /*!< TZCDDRR3_SL (Bit 8)                                   */
+ #define R_MSAC_SLVACCCTL8_TZCDDRR3_SL_Msk      (0x300UL)      /*!< TZCDDRR3_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL8_TZCSYSRAM_SL_Pos     (10UL)         /*!< TZCSYSRAM_SL (Bit 10)                                 */
+ #define R_MSAC_SLVACCCTL8_TZCSYSRAM_SL_Msk     (0xc00UL)      /*!< TZCSYSRAM_SL (Bitfield-Mask: 0x03)                    */
+ #define R_MSAC_SLVACCCTL8_TZCXSPI_SL_Pos       (12UL)         /*!< TZCXSPI_SL (Bit 12)                                   */
+ #define R_MSAC_SLVACCCTL8_TZCXSPI_SL_Msk       (0x3000UL)     /*!< TZCXSPI_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL8_TZCBSC_SL_Pos        (14UL)         /*!< TZCBSC_SL (Bit 14)                                    */
+ #define R_MSAC_SLVACCCTL8_TZCBSC_SL_Msk        (0xc000UL)     /*!< TZCBSC_SL (Bitfield-Mask: 0x03)                       */
+ #define R_MSAC_SLVACCCTL8_PRCR_SL_Pos          (16UL)         /*!< PRCR_SL (Bit 16)                                      */
+ #define R_MSAC_SLVACCCTL8_PRCR_SL_Msk          (0x30000UL)    /*!< PRCR_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL8_ICU_SL_Pos           (18UL)         /*!< ICU_SL (Bit 18)                                       */
+ #define R_MSAC_SLVACCCTL8_ICU_SL_Msk           (0xc0000UL)    /*!< ICU_SL (Bitfield-Mask: 0x03)                          */
+ #define R_MSAC_SLVACCCTL8_SYSCTRL_SL_Pos       (20UL)         /*!< SYSCTRL_SL (Bit 20)                                   */
+ #define R_MSAC_SLVACCCTL8_SYSCTRL_SL_Msk       (0x300000UL)   /*!< SYSCTRL_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL8_XSPI0_SL_Pos         (24UL)         /*!< XSPI0_SL (Bit 24)                                     */
+ #define R_MSAC_SLVACCCTL8_XSPI0_SL_Msk         (0x3000000UL)  /*!< XSPI0_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL8_XSPI1_SL_Pos         (26UL)         /*!< XSPI1_SL (Bit 26)                                     */
+ #define R_MSAC_SLVACCCTL8_XSPI1_SL_Msk         (0xc000000UL)  /*!< XSPI1_SL (Bitfield-Mask: 0x03)                        */
+/* ======================================================  SLVACCCTL9  ======================================================= */
+ #define R_MSAC_SLVACCCTL9_ADDEXP_SL_Pos        (0UL)          /*!< ADDEXP_SL (Bit 0)                                     */
+ #define R_MSAC_SLVACCCTL9_ADDEXP_SL_Msk        (0x3UL)        /*!< ADDEXP_SL (Bitfield-Mask: 0x03)                       */
+ #define R_MSAC_SLVACCCTL9_MPUSHOSTIF_SL_Pos    (16UL)         /*!< MPUSHOSTIF_SL (Bit 16)                                */
+ #define R_MSAC_SLVACCCTL9_MPUSHOSTIF_SL_Msk    (0x30000UL)    /*!< MPUSHOSTIF_SL (Bitfield-Mask: 0x03)                   */
+ #define R_MSAC_SLVACCCTL9_MPUGMAC0_SL_Pos      (18UL)         /*!< MPUGMAC0_SL (Bit 18)                                  */
+ #define R_MSAC_SLVACCCTL9_MPUGMAC0_SL_Msk      (0xc0000UL)    /*!< MPUGMAC0_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL9_MPUDMAC0_SL_Pos      (20UL)         /*!< MPUDMAC0_SL (Bit 20)                                  */
+ #define R_MSAC_SLVACCCTL9_MPUDMAC0_SL_Msk      (0x300000UL)   /*!< MPUDMAC0_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL9_MPUDMAC1_SL_Pos      (22UL)         /*!< MPUDMAC1_SL (Bit 22)                                  */
+ #define R_MSAC_SLVACCCTL9_MPUDMAC1_SL_Msk      (0xc00000UL)   /*!< MPUDMAC1_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL9_MPUDMAC2_SL_Pos      (24UL)         /*!< MPUDMAC2_SL (Bit 24)                                  */
+ #define R_MSAC_SLVACCCTL9_MPUDMAC2_SL_Msk      (0x3000000UL)  /*!< MPUDMAC2_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL9_MPUCS_SL_Pos         (26UL)         /*!< MPUCS_SL (Bit 26)                                     */
+ #define R_MSAC_SLVACCCTL9_MPUCS_SL_Msk         (0xc000000UL)  /*!< MPUCS_SL (Bitfield-Mask: 0x03)                        */
+/* ======================================================  MSTACCCTL0  ======================================================= */
+ #define R_MSAC_MSTACCCTL0_CSETR_PROT0_Pos      (0UL)          /*!< CSETR_PROT0 (Bit 0)                                   */
+ #define R_MSAC_MSTACCCTL0_CSETR_PROT0_Msk      (0x1UL)        /*!< CSETR_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_CSETR_PROT1_Pos      (1UL)          /*!< CSETR_PROT1 (Bit 1)                                   */
+ #define R_MSAC_MSTACCCTL0_CSETR_PROT1_Msk      (0x2UL)        /*!< CSETR_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_CSETR_SEL0_Pos       (2UL)          /*!< CSETR_SEL0 (Bit 2)                                    */
+ #define R_MSAC_MSTACCCTL0_CSETR_SEL0_Msk       (0x4UL)        /*!< CSETR_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_CSETR_SEL1_Pos       (3UL)          /*!< CSETR_SEL1 (Bit 3)                                    */
+ #define R_MSAC_MSTACCCTL0_CSETR_SEL1_Msk       (0x8UL)        /*!< CSETR_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_LCDC_PROT0_Pos       (4UL)          /*!< LCDC_PROT0 (Bit 4)                                    */
+ #define R_MSAC_MSTACCCTL0_LCDC_PROT0_Msk       (0x10UL)       /*!< LCDC_PROT0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_LCDC_PROT1_Pos       (5UL)          /*!< LCDC_PROT1 (Bit 5)                                    */
+ #define R_MSAC_MSTACCCTL0_LCDC_PROT1_Msk       (0x20UL)       /*!< LCDC_PROT1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_LCDC_SEL0_Pos        (6UL)          /*!< LCDC_SEL0 (Bit 6)                                     */
+ #define R_MSAC_MSTACCCTL0_LCDC_SEL0_Msk        (0x40UL)       /*!< LCDC_SEL0 (Bitfield-Mask: 0x01)                       */
+ #define R_MSAC_MSTACCCTL0_LCDC_SEL1_Pos        (7UL)          /*!< LCDC_SEL1 (Bit 7)                                     */
+ #define R_MSAC_MSTACCCTL0_LCDC_SEL1_Msk        (0x80UL)       /*!< LCDC_SEL1 (Bitfield-Mask: 0x01)                       */
+ #define R_MSAC_MSTACCCTL0_PCIE0_PROT0_Pos      (8UL)          /*!< PCIE0_PROT0 (Bit 8)                                   */
+ #define R_MSAC_MSTACCCTL0_PCIE0_PROT0_Msk      (0x100UL)      /*!< PCIE0_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_PCIE0_PROT1_Pos      (9UL)          /*!< PCIE0_PROT1 (Bit 9)                                   */
+ #define R_MSAC_MSTACCCTL0_PCIE0_PROT1_Msk      (0x200UL)      /*!< PCIE0_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_PCIE0_SEL0_Pos       (10UL)         /*!< PCIE0_SEL0 (Bit 10)                                   */
+ #define R_MSAC_MSTACCCTL0_PCIE0_SEL0_Msk       (0x400UL)      /*!< PCIE0_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_PCIE0_SEL1_Pos       (11UL)         /*!< PCIE0_SEL1 (Bit 11)                                   */
+ #define R_MSAC_MSTACCCTL0_PCIE0_SEL1_Msk       (0x800UL)      /*!< PCIE0_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_PCIE1_PROT0_Pos      (12UL)         /*!< PCIE1_PROT0 (Bit 12)                                  */
+ #define R_MSAC_MSTACCCTL0_PCIE1_PROT0_Msk      (0x1000UL)     /*!< PCIE1_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_PCIE1_PROT1_Pos      (13UL)         /*!< PCIE1_PROT1 (Bit 13)                                  */
+ #define R_MSAC_MSTACCCTL0_PCIE1_PROT1_Msk      (0x2000UL)     /*!< PCIE1_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_PCIE1_SEL0_Pos       (14UL)         /*!< PCIE1_SEL0 (Bit 14)                                   */
+ #define R_MSAC_MSTACCCTL0_PCIE1_SEL0_Msk       (0x4000UL)     /*!< PCIE1_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_PCIE1_SEL1_Pos       (15UL)         /*!< PCIE1_SEL1 (Bit 15)                                   */
+ #define R_MSAC_MSTACCCTL0_PCIE1_SEL1_Msk       (0x8000UL)     /*!< PCIE1_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_SDHI0_PROT0_Pos      (16UL)         /*!< SDHI0_PROT0 (Bit 16)                                  */
+ #define R_MSAC_MSTACCCTL0_SDHI0_PROT0_Msk      (0x10000UL)    /*!< SDHI0_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_SDHI0_PROT1_Pos      (17UL)         /*!< SDHI0_PROT1 (Bit 17)                                  */
+ #define R_MSAC_MSTACCCTL0_SDHI0_PROT1_Msk      (0x20000UL)    /*!< SDHI0_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_SDHI0_SEL0_Pos       (18UL)         /*!< SDHI0_SEL0 (Bit 18)                                   */
+ #define R_MSAC_MSTACCCTL0_SDHI0_SEL0_Msk       (0x40000UL)    /*!< SDHI0_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_SDHI0_SEL1_Pos       (19UL)         /*!< SDHI0_SEL1 (Bit 19)                                   */
+ #define R_MSAC_MSTACCCTL0_SDHI0_SEL1_Msk       (0x80000UL)    /*!< SDHI0_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_SDHI1_PROT0_Pos      (20UL)         /*!< SDHI1_PROT0 (Bit 20)                                  */
+ #define R_MSAC_MSTACCCTL0_SDHI1_PROT0_Msk      (0x100000UL)   /*!< SDHI1_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_SDHI1_PROT1_Pos      (21UL)         /*!< SDHI1_PROT1 (Bit 21)                                  */
+ #define R_MSAC_MSTACCCTL0_SDHI1_PROT1_Msk      (0x200000UL)   /*!< SDHI1_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_SDHI1_SEL0_Pos       (22UL)         /*!< SDHI1_SEL0 (Bit 22)                                   */
+ #define R_MSAC_MSTACCCTL0_SDHI1_SEL0_Msk       (0x400000UL)   /*!< SDHI1_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_SDHI1_SEL1_Pos       (23UL)         /*!< SDHI1_SEL1 (Bit 23)                                   */
+ #define R_MSAC_MSTACCCTL0_SDHI1_SEL1_Msk       (0x800000UL)   /*!< SDHI1_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_GMAC1_PROT0_Pos      (24UL)         /*!< GMAC1_PROT0 (Bit 24)                                  */
+ #define R_MSAC_MSTACCCTL0_GMAC1_PROT0_Msk      (0x1000000UL)  /*!< GMAC1_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_GMAC1_PROT1_Pos      (25UL)         /*!< GMAC1_PROT1 (Bit 25)                                  */
+ #define R_MSAC_MSTACCCTL0_GMAC1_PROT1_Msk      (0x2000000UL)  /*!< GMAC1_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_GMAC1_SEL0_Pos       (26UL)         /*!< GMAC1_SEL0 (Bit 26)                                   */
+ #define R_MSAC_MSTACCCTL0_GMAC1_SEL0_Msk       (0x4000000UL)  /*!< GMAC1_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_GMAC1_SEL1_Pos       (27UL)         /*!< GMAC1_SEL1 (Bit 27)                                   */
+ #define R_MSAC_MSTACCCTL0_GMAC1_SEL1_Msk       (0x8000000UL)  /*!< GMAC1_SEL1 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_GMAC2_PROT0_Pos      (28UL)         /*!< GMAC2_PROT0 (Bit 28)                                  */
+ #define R_MSAC_MSTACCCTL0_GMAC2_PROT0_Msk      (0x10000000UL) /*!< GMAC2_PROT0 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_GMAC2_PROT1_Pos      (29UL)         /*!< GMAC2_PROT1 (Bit 29)                                  */
+ #define R_MSAC_MSTACCCTL0_GMAC2_PROT1_Msk      (0x20000000UL) /*!< GMAC2_PROT1 (Bitfield-Mask: 0x01)                     */
+ #define R_MSAC_MSTACCCTL0_GMAC2_SEL0_Pos       (30UL)         /*!< GMAC2_SEL0 (Bit 30)                                   */
+ #define R_MSAC_MSTACCCTL0_GMAC2_SEL0_Msk       (0x40000000UL) /*!< GMAC2_SEL0 (Bitfield-Mask: 0x01)                      */
+ #define R_MSAC_MSTACCCTL0_GMAC2_SEL1x_Pos      (31UL)         /*!< GMAC2_SEL1x (Bit 31)                                  */
+ #define R_MSAC_MSTACCCTL0_GMAC2_SEL1x_Msk      (0x80000000UL) /*!< GMAC2_SEL1x (Bitfield-Mask: 0x01)                     */
+/* ======================================================  MSTACCCTL1  ======================================================= */
+ #define R_MSAC_MSTACCCTL1_USB_PROT0_Pos        (0UL)          /*!< USB_PROT0 (Bit 0)                                     */
+ #define R_MSAC_MSTACCCTL1_USB_PROT0_Msk        (0x1UL)        /*!< USB_PROT0 (Bitfield-Mask: 0x01)                       */
+ #define R_MSAC_MSTACCCTL1_USB_PROT1_Pos        (1UL)          /*!< USB_PROT1 (Bit 1)                                     */
+ #define R_MSAC_MSTACCCTL1_USB_PROT1_Msk        (0x2UL)        /*!< USB_PROT1 (Bitfield-Mask: 0x01)                       */
+ #define R_MSAC_MSTACCCTL1_USB_SEL_Pos          (3UL)          /*!< USB_SEL (Bit 3)                                       */
+ #define R_MSAC_MSTACCCTL1_USB_SEL_Msk          (0x8UL)        /*!< USB_SEL (Bitfield-Mask: 0x01)                         */
+/* ======================================================  SLVACCCTL0  ======================================================= */
+ #define R_MSAC_SLVACCCTL0_CMT0_SL_Pos          (0UL)          /*!< CMT0_SL (Bit 0)                                       */
+ #define R_MSAC_SLVACCCTL0_CMT0_SL_Msk          (0x3UL)        /*!< CMT0_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_CMT1_SL_Pos          (2UL)          /*!< CMT1_SL (Bit 2)                                       */
+ #define R_MSAC_SLVACCCTL0_CMT1_SL_Msk          (0xcUL)        /*!< CMT1_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_CMT2_SL_Pos          (4UL)          /*!< CMT2_SL (Bit 4)                                       */
+ #define R_MSAC_SLVACCCTL0_CMT2_SL_Msk          (0x30UL)       /*!< CMT2_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_CMTW0_SL_Pos         (6UL)          /*!< CMTW0_SL (Bit 6)                                      */
+ #define R_MSAC_SLVACCCTL0_CMTW0_SL_Msk         (0xc0UL)       /*!< CMTW0_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL0_CMTW1_SL_Pos         (8UL)          /*!< CMTW1_SL (Bit 8)                                      */
+ #define R_MSAC_SLVACCCTL0_CMTW1_SL_Msk         (0x300UL)      /*!< CMTW1_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL0_GPT09_SL_Pos         (12UL)         /*!< GPT09_SL (Bit 12)                                     */
+ #define R_MSAC_SLVACCCTL0_GPT09_SL_Msk         (0x3000UL)     /*!< GPT09_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL0_POEG1_SL_Pos         (14UL)         /*!< POEG1_SL (Bit 14)                                     */
+ #define R_MSAC_SLVACCCTL0_POEG1_SL_Msk         (0xc000UL)     /*!< POEG1_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL0_WDT0_SL_Pos          (16UL)         /*!< WDT0_SL (Bit 16)                                      */
+ #define R_MSAC_SLVACCCTL0_WDT0_SL_Msk          (0x30000UL)    /*!< WDT0_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_WDT1_SL_Pos          (18UL)         /*!< WDT1_SL (Bit 18)                                      */
+ #define R_MSAC_SLVACCCTL0_WDT1_SL_Msk          (0xc0000UL)    /*!< WDT1_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_WDT2_SL_Pos          (20UL)         /*!< WDT2_SL (Bit 20)                                      */
+ #define R_MSAC_SLVACCCTL0_WDT2_SL_Msk          (0x300000UL)   /*!< WDT2_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_WDT3_SL_Pos          (22UL)         /*!< WDT3_SL (Bit 22)                                      */
+ #define R_MSAC_SLVACCCTL0_WDT3_SL_Msk          (0xc00000UL)   /*!< WDT3_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_WDT4_SL_Pos          (24UL)         /*!< WDT4_SL (Bit 24)                                      */
+ #define R_MSAC_SLVACCCTL0_WDT4_SL_Msk          (0x3000000UL)  /*!< WDT4_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_WDT5_SL_Pos          (26UL)         /*!< WDT5_SL (Bit 26)                                      */
+ #define R_MSAC_SLVACCCTL0_WDT5_SL_Msk          (0xc000000UL)  /*!< WDT5_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL0_ADC2_SL_Pos          (30UL)         /*!< ADC2_SL (Bit 30)                                      */
+ #define R_MSAC_SLVACCCTL0_ADC2_SL_Msk          (0xc0000000UL) /*!< ADC2_SL (Bitfield-Mask: 0x03)                         */
+/* ======================================================  SLVACCCTL1  ======================================================= */
+ #define R_MSAC_SLVACCCTL1_SCI0_SL_Pos          (0UL)          /*!< SCI0_SL (Bit 0)                                       */
+ #define R_MSAC_SLVACCCTL1_SCI0_SL_Msk          (0x3UL)        /*!< SCI0_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_SCI1_SL_Pos          (2UL)          /*!< SCI1_SL (Bit 2)                                       */
+ #define R_MSAC_SLVACCCTL1_SCI1_SL_Msk          (0xcUL)        /*!< SCI1_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_SCI2_SL_Pos          (4UL)          /*!< SCI2_SL (Bit 4)                                       */
+ #define R_MSAC_SLVACCCTL1_SCI2_SL_Msk          (0x30UL)       /*!< SCI2_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_SCI3_SL_Pos          (6UL)          /*!< SCI3_SL (Bit 6)                                       */
+ #define R_MSAC_SLVACCCTL1_SCI3_SL_Msk          (0xc0UL)       /*!< SCI3_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_SCI4_SL_Pos          (8UL)          /*!< SCI4_SL (Bit 8)                                       */
+ #define R_MSAC_SLVACCCTL1_SCI4_SL_Msk          (0x300UL)      /*!< SCI4_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_IIC0_SL_Pos          (12UL)         /*!< IIC0_SL (Bit 12)                                      */
+ #define R_MSAC_SLVACCCTL1_IIC0_SL_Msk          (0x3000UL)     /*!< IIC0_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_IIC1_SL_Pos          (14UL)         /*!< IIC1_SL (Bit 14)                                      */
+ #define R_MSAC_SLVACCCTL1_IIC1_SL_Msk          (0xc000UL)     /*!< IIC1_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_SPI0_SL_Pos          (16UL)         /*!< SPI0_SL (Bit 16)                                      */
+ #define R_MSAC_SLVACCCTL1_SPI0_SL_Msk          (0x30000UL)    /*!< SPI0_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_SPI1_SL_Pos          (18UL)         /*!< SPI1_SL (Bit 18)                                      */
+ #define R_MSAC_SLVACCCTL1_SPI1_SL_Msk          (0xc0000UL)    /*!< SPI1_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_SPI2_SL_Pos          (20UL)         /*!< SPI2_SL (Bit 20)                                      */
+ #define R_MSAC_SLVACCCTL1_SPI2_SL_Msk          (0x300000UL)   /*!< SPI2_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_CANFD_SL_Pos         (24UL)         /*!< CANFD_SL (Bit 24)                                     */
+ #define R_MSAC_SLVACCCTL1_CANFD_SL_Msk         (0x3000000UL)  /*!< CANFD_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL1_DOC_SL_Pos           (26UL)         /*!< DOC_SL (Bit 26)                                       */
+ #define R_MSAC_SLVACCCTL1_DOC_SL_Msk           (0xc000000UL)  /*!< DOC_SL (Bitfield-Mask: 0x03)                          */
+ #define R_MSAC_SLVACCCTL1_CRC0_SL_Pos          (28UL)         /*!< CRC0_SL (Bit 28)                                      */
+ #define R_MSAC_SLVACCCTL1_CRC0_SL_Msk          (0x30000000UL) /*!< CRC0_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL1_TSU_SL_Pos           (30UL)         /*!< TSU_SL (Bit 30)                                       */
+ #define R_MSAC_SLVACCCTL1_TSU_SL_Msk           (0xc0000000UL) /*!< TSU_SL (Bitfield-Mask: 0x03)                          */
+/* ======================================================  SLVACCCTL2  ======================================================= */
+ #define R_MSAC_SLVACCCTL2_GPT10_SL_Pos         (0UL)          /*!< GPT10_SL (Bit 0)                                      */
+ #define R_MSAC_SLVACCCTL2_GPT10_SL_Msk         (0x3UL)        /*!< GPT10_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL2_POEG2_SL_Pos         (2UL)          /*!< POEG2_SL (Bit 2)                                      */
+ #define R_MSAC_SLVACCCTL2_POEG2_SL_Msk         (0xcUL)        /*!< POEG2_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL2_RTC_SL_Pos           (8UL)          /*!< RTC_SL (Bit 8)                                        */
+ #define R_MSAC_SLVACCCTL2_RTC_SL_Msk           (0x300UL)      /*!< RTC_SL (Bitfield-Mask: 0x03)                          */
+ #define R_MSAC_SLVACCCTL2_CRC1_SL_Pos          (10UL)         /*!< CRC1_SL (Bit 10)                                      */
+ #define R_MSAC_SLVACCCTL2_CRC1_SL_Msk          (0xc00UL)      /*!< CRC1_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL2_SCI5_SL_Pos          (16UL)         /*!< SCI5_SL (Bit 16)                                      */
+ #define R_MSAC_SLVACCCTL2_SCI5_SL_Msk          (0x30000UL)    /*!< SCI5_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL2_IIC2_SL_Pos          (18UL)         /*!< IIC2_SL (Bit 18)                                      */
+ #define R_MSAC_SLVACCCTL2_IIC2_SL_Msk          (0xc0000UL)    /*!< IIC2_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL2_SPI3_SL_Pos          (20UL)         /*!< SPI3_SL (Bit 20)                                      */
+ #define R_MSAC_SLVACCCTL2_SPI3_SL_Msk          (0x300000UL)   /*!< SPI3_SL (Bitfield-Mask: 0x03)                         */
+/* ======================================================  SLVACCCTL4  ======================================================= */
+ #define R_MSAC_SLVACCCTL4_USB_SL_Pos           (0UL)          /*!< USB_SL (Bit 0)                                        */
+ #define R_MSAC_SLVACCCTL4_USB_SL_Msk           (0x3UL)        /*!< USB_SL (Bitfield-Mask: 0x03)                          */
+ #define R_MSAC_SLVACCCTL4_LCDC_SL_Pos          (8UL)          /*!< LCDC_SL (Bit 8)                                       */
+ #define R_MSAC_SLVACCCTL4_LCDC_SL_Msk          (0x300UL)      /*!< LCDC_SL (Bitfield-Mask: 0x03)                         */
+ #define R_MSAC_SLVACCCTL4_SDHI0_SL_Pos         (16UL)         /*!< SDHI0_SL (Bit 16)                                     */
+ #define R_MSAC_SLVACCCTL4_SDHI0_SL_Msk         (0x30000UL)    /*!< SDHI0_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL4_SDHI1_SL_Pos         (18UL)         /*!< SDHI1_SL (Bit 18)                                     */
+ #define R_MSAC_SLVACCCTL4_SDHI1_SL_Msk         (0xc0000UL)    /*!< SDHI1_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL4_GMAC1_SL_Pos         (24UL)         /*!< GMAC1_SL (Bit 24)                                     */
+ #define R_MSAC_SLVACCCTL4_GMAC1_SL_Msk         (0x3000000UL)  /*!< GMAC1_SL (Bitfield-Mask: 0x03)                        */
+ #define R_MSAC_SLVACCCTL4_GMAC2_SL_Pos         (26UL)         /*!< GMAC2_SL (Bit 26)                                     */
+ #define R_MSAC_SLVACCCTL4_GMAC2_SL_Msk         (0xc000000UL)  /*!< GMAC2_SL (Bitfield-Mask: 0x03)                        */
+/* ======================================================  SLVACCCTL5  ======================================================= */
+ #define R_MSAC_SLVACCCTL5_TZCDDRA0A1_SL_Pos    (0UL)          /*!< TZCDDRA0A1_SL (Bit 0)                                 */
+ #define R_MSAC_SLVACCCTL5_TZCDDRA0A1_SL_Msk    (0x3UL)        /*!< TZCDDRA0A1_SL (Bitfield-Mask: 0x03)                   */
+ #define R_MSAC_SLVACCCTL5_TZCDDRA4_SL_Pos      (2UL)          /*!< TZCDDRA4_SL (Bit 2)                                   */
+ #define R_MSAC_SLVACCCTL5_TZCDDRA4_SL_Msk      (0xcUL)        /*!< TZCDDRA4_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL5_TZCPCIE_SL_Pos       (4UL)          /*!< TZCPCIE_SL (Bit 4)                                    */
+ #define R_MSAC_SLVACCCTL5_TZCPCIE_SL_Msk       (0x30UL)       /*!< TZCPCIE_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL5_MPUUSB_SL_Pos        (16UL)         /*!< MPUUSB_SL (Bit 16)                                    */
+ #define R_MSAC_SLVACCCTL5_MPUUSB_SL_Msk        (0x30000UL)    /*!< MPUUSB_SL (Bitfield-Mask: 0x03)                       */
+ #define R_MSAC_SLVACCCTL5_MPUPCIE0_SL_Pos      (18UL)         /*!< MPUPCIE0_SL (Bit 18)                                  */
+ #define R_MSAC_SLVACCCTL5_MPUPCIE0_SL_Msk      (0xc0000UL)    /*!< MPUPCIE0_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL5_MPUPCIE1_SL_Pos      (20UL)         /*!< MPUPCIE1_SL (Bit 20)                                  */
+ #define R_MSAC_SLVACCCTL5_MPUPCIE1_SL_Msk      (0x300000UL)   /*!< MPUPCIE1_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL5_MPULCDC_SL_Pos       (22UL)         /*!< MPULCDC_SL (Bit 22)                                   */
+ #define R_MSAC_SLVACCCTL5_MPULCDC_SL_Msk       (0xc00000UL)   /*!< MPULCDC_SL (Bitfield-Mask: 0x03)                      */
+ #define R_MSAC_SLVACCCTL5_MPUSDHI0_SL_Pos      (24UL)         /*!< MPUSDHI0_SL (Bit 24)                                  */
+ #define R_MSAC_SLVACCCTL5_MPUSDHI0_SL_Msk      (0x3000000UL)  /*!< MPUSDHI0_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL5_MPUSDHI1_SL_Pos      (26UL)         /*!< MPUSDHI1_SL (Bit 26)                                  */
+ #define R_MSAC_SLVACCCTL5_MPUSDHI1_SL_Msk      (0xc000000UL)  /*!< MPUSDHI1_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL5_MPUGMAC1_SL_Pos      (28UL)         /*!< MPUGMAC1_SL (Bit 28)                                  */
+ #define R_MSAC_SLVACCCTL5_MPUGMAC1_SL_Msk      (0x30000000UL) /*!< MPUGMAC1_SL (Bitfield-Mask: 0x03)                     */
+ #define R_MSAC_SLVACCCTL5_MPUGMAC2_SL_Pos      (30UL)         /*!< MPUGMAC2_SL (Bit 30)                                  */
+ #define R_MSAC_SLVACCCTL5_MPUGMAC2_SL_Msk      (0xc0000000UL) /*!< MPUGMAC2_SL (Bitfield-Mask: 0x03)                     */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MPU10                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  ERRINF_R  ======================================================== */
+ #define R_MPU10_ERRINF_R_VALID_Pos      (0UL)          /*!< VALID (Bit 0)                                         */
+ #define R_MPU10_ERRINF_R_VALID_Msk      (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_MPU10_ERRINF_R_RW_Pos         (1UL)          /*!< RW (Bit 1)                                            */
+ #define R_MPU10_ERRINF_R_RW_Msk         (0x2UL)        /*!< RW (Bitfield-Mask: 0x01)                              */
+ #define R_MPU10_ERRINF_R_ERRADDR_Pos    (2UL)          /*!< ERRADDR (Bit 2)                                       */
+ #define R_MPU10_ERRINF_R_ERRADDR_Msk    (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff)                   */
+/* =======================================================  ERRINF_W  ======================================================== */
+ #define R_MPU10_ERRINF_W_VALID_Pos      (0UL)          /*!< VALID (Bit 0)                                         */
+ #define R_MPU10_ERRINF_W_VALID_Msk      (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_MPU10_ERRINF_W_RW_Pos         (1UL)          /*!< RW (Bit 1)                                            */
+ #define R_MPU10_ERRINF_W_RW_Msk         (0x2UL)        /*!< RW (Bitfield-Mask: 0x01)                              */
+ #define R_MPU10_ERRINF_W_ERRADDR_Pos    (2UL)          /*!< ERRADDR (Bit 2)                                       */
+ #define R_MPU10_ERRINF_W_ERRADDR_Msk    (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff)                   */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADXC1                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  ADXCTL6  ======================================================== */
+ #define R_ADXC1_ADXCTL6_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC1_ADXCTL6_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC1_ADXCTL6_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC1_ADXCTL6_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  ADXCTL7  ======================================================== */
+ #define R_ADXC1_ADXCTL7_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC1_ADXCTL7_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC1_ADXCTL7_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC1_ADXCTL7_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  ADXCTL8  ======================================================== */
+ #define R_ADXC1_ADXCTL8_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC1_ADXCTL8_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC1_ADXCTL8_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC1_ADXCTL8_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  ADXCTL9  ======================================================== */
+ #define R_ADXC1_ADXCTL9_DDRMIR0_Pos     (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC1_ADXCTL9_DDRMIR0_Msk     (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC1_ADXCTL9_DDRMIR1_Pos     (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC1_ADXCTL9_DDRMIR1_Msk     (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  ADXCTL10  ======================================================== */
+ #define R_ADXC1_ADXCTL10_DDRMIR0_Pos    (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC1_ADXCTL10_DDRMIR0_Msk    (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC1_ADXCTL10_DDRMIR1_Pos    (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC1_ADXCTL10_DDRMIR1_Msk    (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  ADXCTL11  ======================================================== */
+ #define R_ADXC1_ADXCTL11_DDRMIR0_Pos    (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC1_ADXCTL11_DDRMIR0_Msk    (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC1_ADXCTL11_DDRMIR1_Pos    (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC1_ADXCTL11_DDRMIR1_Msk    (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  ADXCTL12  ======================================================== */
+ #define R_ADXC1_ADXCTL12_DDRMIR0_Pos    (16UL)         /*!< DDRMIR0 (Bit 16)                                      */
+ #define R_ADXC1_ADXCTL12_DDRMIR0_Msk    (0x1f0000UL)   /*!< DDRMIR0 (Bitfield-Mask: 0x1f)                         */
+ #define R_ADXC1_ADXCTL12_DDRMIR1_Pos    (24UL)         /*!< DDRMIR1 (Bit 24)                                      */
+ #define R_ADXC1_ADXCTL12_DDRMIR1_Msk    (0x1f000000UL) /*!< DDRMIR1 (Bitfield-Mask: 0x1f)                         */
+
+/* =========================================================================================================================== */
+/* ================                                       R_SYSRAM_CTL                                        ================ */
+/* =========================================================================================================================== */
+
+/* =====================================================  SYSRAM_CTRL0  ====================================================== */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
+/* =====================================================  SYSRAM_CTRL1  ====================================================== */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
+/* =====================================================  SYSRAM_CTRL2  ====================================================== */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
+/* =====================================================  SYSRAM_CTRL3  ====================================================== */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
+ #define R_SYSRAM_CTL_SYSRAM_CTRL3_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
+
+/* =========================================================================================================================== */
+/* ================                                       R_SHOSTIF_CFG                                       ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SHCFG  ========================================================= */
+ #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Pos       (0UL)          /*!< SPIMODE (Bit 0)                                       */
+ #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Msk       (0x3UL)        /*!< SPIMODE (Bitfield-Mask: 0x03)                         */
+ #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Pos      (2UL)          /*!< BYTESWAP (Bit 2)                                      */
+ #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Msk      (0x4UL)        /*!< BYTESWAP (Bitfield-Mask: 0x01)                        */
+ #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Pos    (3UL)          /*!< ADDRESSING (Bit 3)                                    */
+ #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Msk    (0x8UL)        /*!< ADDRESSING (Bitfield-Mask: 0x01)                      */
+ #define R_SHOSTIF_CFG_SHCFG_SLEEP_Pos         (4UL)          /*!< SLEEP (Bit 4)                                         */
+ #define R_SHOSTIF_CFG_SHCFG_SLEEP_Msk         (0x10UL)       /*!< SLEEP (Bitfield-Mask: 0x01)                           */
+ #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Pos      (16UL)         /*!< INTMASKI (Bit 16)                                     */
+ #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Msk      (0x3f0000UL)   /*!< INTMASKI (Bitfield-Mask: 0x3f)                        */
+ #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Pos      (24UL)         /*!< INTMASKE (Bit 24)                                     */
+ #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Msk      (0x3f000000UL) /*!< INTMASKE (Bitfield-Mask: 0x3f)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_TCMAW                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  CPU0WAIT  ======================================================== */
+ #define R_TCMAW_CPU0WAIT_CPU0WAIT_Pos    (0UL)   /*!< CPU0WAIT (Bit 0)                                      */
+ #define R_TCMAW_CPU0WAIT_CPU0WAIT_Msk    (0x1UL) /*!< CPU0WAIT (Bitfield-Mask: 0x01)                        */
+/* =======================================================  CPU1WAIT  ======================================================== */
+ #define R_TCMAW_CPU1WAIT_CPU1WAIT_Pos    (0UL)   /*!< CPU1WAIT (Bit 0)                                      */
+ #define R_TCMAW_CPU1WAIT_CPU1WAIT_Msk    (0x1UL) /*!< CPU1WAIT (Bitfield-Mask: 0x01)                        */
+/* =======================================================  CPU1HALT  ======================================================== */
+ #define R_TCMAW_CPU1HALT_CPU1HALT_Pos    (0UL)   /*!< CPU1HALT (Bit 0)                                      */
+ #define R_TCMAW_CPU1HALT_CPU1HALT_Msk    (0x1UL) /*!< CPU1HALT (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CA55                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                         R_WDT_DBG                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  WDTDCR  ========================================================= */
+ #define R_WDT_DBG_WDTDCR_WDTSTOPCTRL_Pos    (0UL)       /*!< WDTSTOPCTRL (Bit 0)                                   */
+ #define R_WDT_DBG_WDTDCR_WDTSTOPCTRL_Msk    (0x1UL)     /*!< WDTSTOPCTRL (Bitfield-Mask: 0x01)                     */
+ #define R_WDT_DBG_WDTDCR_WDTSTOPMASK_Pos    (16UL)      /*!< WDTSTOPMASK (Bit 16)                                  */
+ #define R_WDT_DBG_WDTDCR_WDTSTOPMASK_Msk    (0x10000UL) /*!< WDTSTOPMASK (Bitfield-Mask: 0x01)                     */
+
+/* =========================================================================================================================== */
+/* ================                                          R_RWP_S                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PRCRS  ========================================================= */
+ #define R_RWP_S_PRCRS_PRC0_Pos     (0UL)      /*!< PRC0 (Bit 0)                                          */
+ #define R_RWP_S_PRCRS_PRC0_Msk     (0x1UL)    /*!< PRC0 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_S_PRCRS_PRC1_Pos     (1UL)      /*!< PRC1 (Bit 1)                                          */
+ #define R_RWP_S_PRCRS_PRC1_Msk     (0x2UL)    /*!< PRC1 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_S_PRCRS_PRC2_Pos     (2UL)      /*!< PRC2 (Bit 2)                                          */
+ #define R_RWP_S_PRCRS_PRC2_Msk     (0x4UL)    /*!< PRC2 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_S_PRCRS_PRC3_Pos     (3UL)      /*!< PRC3 (Bit 3)                                          */
+ #define R_RWP_S_PRCRS_PRC3_Msk     (0x8UL)    /*!< PRC3 (Bitfield-Mask: 0x01)                            */
+ #define R_RWP_S_PRCRS_PRKEY_Pos    (8UL)      /*!< PRKEY (Bit 8)                                         */
+ #define R_RWP_S_PRCRS_PRKEY_Msk    (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ICU_S                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  S_SWINT  ======================================================== */
+ #define R_ICU_S_S_SWINT_IC14_Pos                 (0UL)          /*!< IC14 (Bit 0)                                          */
+ #define R_ICU_S_S_SWINT_IC14_Msk                 (0x1UL)        /*!< IC14 (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_S_S_SWINT_IC15_Pos                 (1UL)          /*!< IC15 (Bit 1)                                          */
+ #define R_ICU_S_S_SWINT_IC15_Msk                 (0x2UL)        /*!< IC15 (Bitfield-Mask: 0x01)                            */
+/* ====================================================  S_PORTNF_FLTSEL  ==================================================== */
+ #define R_ICU_S_S_PORTNF_FLTSEL_FLT14_Pos        (0UL)          /*!< FLT14 (Bit 0)                                         */
+ #define R_ICU_S_S_PORTNF_FLTSEL_FLT14_Msk        (0x1UL)        /*!< FLT14 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_S_S_PORTNF_FLTSEL_FLT15_Pos        (1UL)          /*!< FLT15 (Bit 1)                                         */
+ #define R_ICU_S_S_PORTNF_FLTSEL_FLT15_Msk        (0x2UL)        /*!< FLT15 (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_S_S_PORTNF_FLTSEL_FLTSEI_Pos       (2UL)          /*!< FLTSEI (Bit 2)                                        */
+ #define R_ICU_S_S_PORTNF_FLTSEL_FLTSEI_Msk       (0x4UL)        /*!< FLTSEI (Bitfield-Mask: 0x01)                          */
+/* ====================================================  S_PORTNF_CLKSEL  ==================================================== */
+ #define R_ICU_S_S_PORTNF_CLKSEL_CKSEL14_Pos      (0UL)          /*!< CKSEL14 (Bit 0)                                       */
+ #define R_ICU_S_S_PORTNF_CLKSEL_CKSEL14_Msk      (0x3UL)        /*!< CKSEL14 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_S_S_PORTNF_CLKSEL_CKSEL15_Pos      (2UL)          /*!< CKSEL15 (Bit 2)                                       */
+ #define R_ICU_S_S_PORTNF_CLKSEL_CKSEL15_Msk      (0xcUL)        /*!< CKSEL15 (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_S_S_PORTNF_CLKSEL_CLKSELSEI_Pos    (4UL)          /*!< CLKSELSEI (Bit 4)                                     */
+ #define R_ICU_S_S_PORTNF_CLKSEL_CLKSELSEI_Msk    (0x30UL)       /*!< CLKSELSEI (Bitfield-Mask: 0x03)                       */
+/* ======================================================  S_PORTNF_MD  ====================================================== */
+ #define R_ICU_S_S_PORTNF_MD_MD14_Pos             (0UL)          /*!< MD14 (Bit 0)                                          */
+ #define R_ICU_S_S_PORTNF_MD_MD14_Msk             (0x3UL)        /*!< MD14 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_S_S_PORTNF_MD_MD15_Pos             (2UL)          /*!< MD15 (Bit 2)                                          */
+ #define R_ICU_S_S_PORTNF_MD_MD15_Msk             (0xcUL)        /*!< MD15 (Bitfield-Mask: 0x03)                            */
+ #define R_ICU_S_S_PORTNF_MD_MDSEI_Pos            (4UL)          /*!< MDSEI (Bit 4)                                         */
+ #define R_ICU_S_S_PORTNF_MD_MDSEI_Msk            (0x30UL)       /*!< MDSEI (Bitfield-Mask: 0x03)                           */
+/* =====================================================  S_GPT_INTSEL  ====================================================== */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELX_0_Pos       (0UL)          /*!< INTSELX_0 (Bit 0)                                     */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELX_0_Msk       (0xfUL)        /*!< INTSELX_0 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELX_1_Pos       (4UL)          /*!< INTSELX_1 (Bit 4)                                     */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELX_1_Msk       (0xf0UL)       /*!< INTSELX_1 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELX_2_Pos       (8UL)          /*!< INTSELX_2 (Bit 8)                                     */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELX_2_Msk       (0xf00UL)      /*!< INTSELX_2 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELX_3_Pos       (12UL)         /*!< INTSELX_3 (Bit 12)                                    */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELX_3_Msk       (0xf000UL)     /*!< INTSELX_3 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELY_0_Pos       (16UL)         /*!< INTSELY_0 (Bit 16)                                    */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELY_0_Msk       (0xf0000UL)    /*!< INTSELY_0 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELY_1_Pos       (20UL)         /*!< INTSELY_1 (Bit 20)                                    */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELY_1_Msk       (0xf00000UL)   /*!< INTSELY_1 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELY_2_Pos       (24UL)         /*!< INTSELY_2 (Bit 24)                                    */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELY_2_Msk       (0xf000000UL)  /*!< INTSELY_2 (Bitfield-Mask: 0x0f)                       */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELY_3_Pos       (28UL)         /*!< INTSELY_3 (Bit 28)                                    */
+ #define R_ICU_S_S_GPT_INTSEL_INTSELY_3_Msk       (0xf0000000UL) /*!< INTSELY_3 (Bitfield-Mask: 0x0f)                       */
+/* =====================================================  S_GPT_INTMSK  ====================================================== */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK0_Pos          (0UL)          /*!< IX_MK0 (Bit 0)                                        */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK0_Msk          (0x1UL)        /*!< IX_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK1_Pos          (1UL)          /*!< IX_MK1 (Bit 1)                                        */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK1_Msk          (0x2UL)        /*!< IX_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK2_Pos          (2UL)          /*!< IX_MK2 (Bit 2)                                        */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK2_Msk          (0x4UL)        /*!< IX_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK3_Pos          (3UL)          /*!< IX_MK3 (Bit 3)                                        */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK3_Msk          (0x8UL)        /*!< IX_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK4_Pos          (4UL)          /*!< IX_MK4 (Bit 4)                                        */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK4_Msk          (0x10UL)       /*!< IX_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK5_Pos          (5UL)          /*!< IX_MK5 (Bit 5)                                        */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK5_Msk          (0x20UL)       /*!< IX_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK6_Pos          (6UL)          /*!< IX_MK6 (Bit 6)                                        */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK6_Msk          (0x40UL)       /*!< IX_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK7_Pos          (7UL)          /*!< IX_MK7 (Bit 7)                                        */
+ #define R_ICU_S_S_GPT_INTMSK_IX_MK7_Msk          (0x80UL)       /*!< IX_MK7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK0_Pos          (16UL)         /*!< IY_MK0 (Bit 16)                                       */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK0_Msk          (0x10000UL)    /*!< IY_MK0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK1_Pos          (17UL)         /*!< IY_MK1 (Bit 17)                                       */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK1_Msk          (0x20000UL)    /*!< IY_MK1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK2_Pos          (18UL)         /*!< IY_MK2 (Bit 18)                                       */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK2_Msk          (0x40000UL)    /*!< IY_MK2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK3_Pos          (19UL)         /*!< IY_MK3 (Bit 19)                                       */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK3_Msk          (0x80000UL)    /*!< IY_MK3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK4_Pos          (20UL)         /*!< IY_MK4 (Bit 20)                                       */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK4_Msk          (0x100000UL)   /*!< IY_MK4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK5_Pos          (21UL)         /*!< IY_MK5 (Bit 21)                                       */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK5_Msk          (0x200000UL)   /*!< IY_MK5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK6_Pos          (22UL)         /*!< IY_MK6 (Bit 22)                                       */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK6_Msk          (0x400000UL)   /*!< IY_MK6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK7_Pos          (23UL)         /*!< IY_MK7 (Bit 23)                                       */
+ #define R_ICU_S_S_GPT_INTMSK_IY_MK7_Msk          (0x800000UL)   /*!< IY_MK7 (Bitfield-Mask: 0x01)                          */
+/* =====================================================  S_GPT_INTCLR  ====================================================== */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL0_Pos          (0UL)          /*!< IX_CL0 (Bit 0)                                        */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL0_Msk          (0x1UL)        /*!< IX_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL1_Pos          (1UL)          /*!< IX_CL1 (Bit 1)                                        */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL1_Msk          (0x2UL)        /*!< IX_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL2_Pos          (2UL)          /*!< IX_CL2 (Bit 2)                                        */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL2_Msk          (0x4UL)        /*!< IX_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL3_Pos          (3UL)          /*!< IX_CL3 (Bit 3)                                        */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL3_Msk          (0x8UL)        /*!< IX_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL4_Pos          (4UL)          /*!< IX_CL4 (Bit 4)                                        */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL4_Msk          (0x10UL)       /*!< IX_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL5_Pos          (5UL)          /*!< IX_CL5 (Bit 5)                                        */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL5_Msk          (0x20UL)       /*!< IX_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL6_Pos          (6UL)          /*!< IX_CL6 (Bit 6)                                        */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL6_Msk          (0x40UL)       /*!< IX_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL7_Pos          (7UL)          /*!< IX_CL7 (Bit 7)                                        */
+ #define R_ICU_S_S_GPT_INTCLR_IX_CL7_Msk          (0x80UL)       /*!< IX_CL7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL0_Pos          (16UL)         /*!< IY_CL0 (Bit 16)                                       */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL0_Msk          (0x10000UL)    /*!< IY_CL0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL1_Pos          (17UL)         /*!< IY_CL1 (Bit 17)                                       */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL1_Msk          (0x20000UL)    /*!< IY_CL1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL2_Pos          (18UL)         /*!< IY_CL2 (Bit 18)                                       */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL2_Msk          (0x40000UL)    /*!< IY_CL2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL3_Pos          (19UL)         /*!< IY_CL3 (Bit 19)                                       */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL3_Msk          (0x80000UL)    /*!< IY_CL3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL4_Pos          (20UL)         /*!< IY_CL4 (Bit 20)                                       */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL4_Msk          (0x100000UL)   /*!< IY_CL4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL5_Pos          (21UL)         /*!< IY_CL5 (Bit 21)                                       */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL5_Msk          (0x200000UL)   /*!< IY_CL5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL6_Pos          (22UL)         /*!< IY_CL6 (Bit 22)                                       */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL6_Msk          (0x400000UL)   /*!< IY_CL6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL7_Pos          (23UL)         /*!< IY_CL7 (Bit 23)                                       */
+ #define R_ICU_S_S_GPT_INTCLR_IY_CL7_Msk          (0x800000UL)   /*!< IY_CL7 (Bitfield-Mask: 0x01)                          */
+/* =====================================================  S_GPT_INTSTAT  ===================================================== */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST0_Pos         (0UL)          /*!< IX_ST0 (Bit 0)                                        */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST0_Msk         (0x1UL)        /*!< IX_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST1_Pos         (1UL)          /*!< IX_ST1 (Bit 1)                                        */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST1_Msk         (0x2UL)        /*!< IX_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST2_Pos         (2UL)          /*!< IX_ST2 (Bit 2)                                        */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST2_Msk         (0x4UL)        /*!< IX_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST3_Pos         (3UL)          /*!< IX_ST3 (Bit 3)                                        */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST3_Msk         (0x8UL)        /*!< IX_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST4_Pos         (4UL)          /*!< IX_ST4 (Bit 4)                                        */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST4_Msk         (0x10UL)       /*!< IX_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST5_Pos         (5UL)          /*!< IX_ST5 (Bit 5)                                        */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST5_Msk         (0x20UL)       /*!< IX_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST6_Pos         (6UL)          /*!< IX_ST6 (Bit 6)                                        */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST6_Msk         (0x40UL)       /*!< IX_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST7_Pos         (7UL)          /*!< IX_ST7 (Bit 7)                                        */
+ #define R_ICU_S_S_GPT_INTSTAT_IX_ST7_Msk         (0x80UL)       /*!< IX_ST7 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST0_Pos         (16UL)         /*!< IY_ST0 (Bit 16)                                       */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST0_Msk         (0x10000UL)    /*!< IY_ST0 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST1_Pos         (17UL)         /*!< IY_ST1 (Bit 17)                                       */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST1_Msk         (0x20000UL)    /*!< IY_ST1 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST2_Pos         (18UL)         /*!< IY_ST2 (Bit 18)                                       */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST2_Msk         (0x40000UL)    /*!< IY_ST2 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST3_Pos         (19UL)         /*!< IY_ST3 (Bit 19)                                       */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST3_Msk         (0x80000UL)    /*!< IY_ST3 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST4_Pos         (20UL)         /*!< IY_ST4 (Bit 20)                                       */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST4_Msk         (0x100000UL)   /*!< IY_ST4 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST5_Pos         (21UL)         /*!< IY_ST5 (Bit 21)                                       */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST5_Msk         (0x200000UL)   /*!< IY_ST5 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST6_Pos         (22UL)         /*!< IY_ST6 (Bit 22)                                       */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST6_Msk         (0x400000UL)   /*!< IY_ST6 (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST7_Pos         (23UL)         /*!< IY_ST7 (Bit 23)                                       */
+ #define R_ICU_S_S_GPT_INTSTAT_IY_ST7_Msk         (0x800000UL)   /*!< IY_ST7 (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_GSC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CNTCR  ========================================================= */
+ #define R_GSC_CNTCR_EN_Pos              (0UL)          /*!< EN (Bit 0)                                            */
+ #define R_GSC_CNTCR_EN_Msk              (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_GSC_CNTCR_HDBG_Pos            (1UL)          /*!< HDBG (Bit 1)                                          */
+ #define R_GSC_CNTCR_HDBG_Msk            (0x2UL)        /*!< HDBG (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CNTSR  ========================================================= */
+ #define R_GSC_CNTSR_DBGH_Pos            (1UL)          /*!< DBGH (Bit 1)                                          */
+ #define R_GSC_CNTSR_DBGH_Msk            (0x2UL)        /*!< DBGH (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CNTCVL  ========================================================= */
+ #define R_GSC_CNTCVL_CNTCVL_L_32_Pos    (0UL)          /*!< CNTCVL_L_32 (Bit 0)                                   */
+ #define R_GSC_CNTCVL_CNTCVL_L_32_Msk    (0xffffffffUL) /*!< CNTCVL_L_32 (Bitfield-Mask: 0xffffffff)               */
+/* ========================================================  CNTCVU  ========================================================= */
+ #define R_GSC_CNTCVU_CNTCVU_U_32_Pos    (0UL)          /*!< CNTCVU_U_32 (Bit 0)                                   */
+ #define R_GSC_CNTCVU_CNTCVU_U_32_Msk    (0xffffffffUL) /*!< CNTCVU_U_32 (Bitfield-Mask: 0xffffffff)               */
+/* ========================================================  CNTFID0  ======================================================== */
+ #define R_GSC_CNTFID0_FREQ_Pos          (0UL)          /*!< FREQ (Bit 0)                                          */
+ #define R_GSC_CNTFID0_FREQ_Msk          (0xffffffffUL) /*!< FREQ (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_MTU                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TOERA  ========================================================= */
+ #define R_MTU_TOERA_OE3B_Pos      (0UL)    /*!< OE3B (Bit 0)                                          */
+ #define R_MTU_TOERA_OE3B_Msk      (0x1UL)  /*!< OE3B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE4A_Pos      (1UL)    /*!< OE4A (Bit 1)                                          */
+ #define R_MTU_TOERA_OE4A_Msk      (0x2UL)  /*!< OE4A (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE4B_Pos      (2UL)    /*!< OE4B (Bit 2)                                          */
+ #define R_MTU_TOERA_OE4B_Msk      (0x4UL)  /*!< OE4B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE3D_Pos      (3UL)    /*!< OE3D (Bit 3)                                          */
+ #define R_MTU_TOERA_OE3D_Msk      (0x8UL)  /*!< OE3D (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE4C_Pos      (4UL)    /*!< OE4C (Bit 4)                                          */
+ #define R_MTU_TOERA_OE4C_Msk      (0x10UL) /*!< OE4C (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERA_OE4D_Pos      (5UL)    /*!< OE4D (Bit 5)                                          */
+ #define R_MTU_TOERA_OE4D_Msk      (0x20UL) /*!< OE4D (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TGCRA  ========================================================= */
+ #define R_MTU_TGCRA_UF_Pos        (0UL)    /*!< UF (Bit 0)                                            */
+ #define R_MTU_TGCRA_UF_Msk        (0x1UL)  /*!< UF (Bitfield-Mask: 0x01)                              */
+ #define R_MTU_TGCRA_VF_Pos        (1UL)    /*!< VF (Bit 1)                                            */
+ #define R_MTU_TGCRA_VF_Msk        (0x2UL)  /*!< VF (Bitfield-Mask: 0x01)                              */
+ #define R_MTU_TGCRA_WF_Pos        (2UL)    /*!< WF (Bit 2)                                            */
+ #define R_MTU_TGCRA_WF_Msk        (0x4UL)  /*!< WF (Bitfield-Mask: 0x01)                              */
+ #define R_MTU_TGCRA_FB_Pos        (3UL)    /*!< FB (Bit 3)                                            */
+ #define R_MTU_TGCRA_FB_Msk        (0x8UL)  /*!< FB (Bitfield-Mask: 0x01)                              */
+ #define R_MTU_TGCRA_P_Pos         (4UL)    /*!< P (Bit 4)                                             */
+ #define R_MTU_TGCRA_P_Msk         (0x10UL) /*!< P (Bitfield-Mask: 0x01)                               */
+ #define R_MTU_TGCRA_N_Pos         (5UL)    /*!< N (Bit 5)                                             */
+ #define R_MTU_TGCRA_N_Msk         (0x20UL) /*!< N (Bitfield-Mask: 0x01)                               */
+ #define R_MTU_TGCRA_BDC_Pos       (6UL)    /*!< BDC (Bit 6)                                           */
+ #define R_MTU_TGCRA_BDC_Msk       (0x40UL) /*!< BDC (Bitfield-Mask: 0x01)                             */
+/* ========================================================  TOCR1A  ========================================================= */
+ #define R_MTU_TOCR1A_OLSP_Pos     (0UL)    /*!< OLSP (Bit 0)                                          */
+ #define R_MTU_TOCR1A_OLSP_Msk     (0x1UL)  /*!< OLSP (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1A_OLSN_Pos     (1UL)    /*!< OLSN (Bit 1)                                          */
+ #define R_MTU_TOCR1A_OLSN_Msk     (0x2UL)  /*!< OLSN (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1A_TOCS_Pos     (2UL)    /*!< TOCS (Bit 2)                                          */
+ #define R_MTU_TOCR1A_TOCS_Msk     (0x4UL)  /*!< TOCS (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1A_TOCL_Pos     (3UL)    /*!< TOCL (Bit 3)                                          */
+ #define R_MTU_TOCR1A_TOCL_Msk     (0x8UL)  /*!< TOCL (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1A_PSYE_Pos     (6UL)    /*!< PSYE (Bit 6)                                          */
+ #define R_MTU_TOCR1A_PSYE_Msk     (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOCR2A  ========================================================= */
+ #define R_MTU_TOCR2A_OLS1P_Pos    (0UL)    /*!< OLS1P (Bit 0)                                         */
+ #define R_MTU_TOCR2A_OLS1P_Msk    (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS1N_Pos    (1UL)    /*!< OLS1N (Bit 1)                                         */
+ #define R_MTU_TOCR2A_OLS1N_Msk    (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS2P_Pos    (2UL)    /*!< OLS2P (Bit 2)                                         */
+ #define R_MTU_TOCR2A_OLS2P_Msk    (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS2N_Pos    (3UL)    /*!< OLS2N (Bit 3)                                         */
+ #define R_MTU_TOCR2A_OLS2N_Msk    (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS3P_Pos    (4UL)    /*!< OLS3P (Bit 4)                                         */
+ #define R_MTU_TOCR2A_OLS3P_Msk    (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_OLS3N_Pos    (5UL)    /*!< OLS3N (Bit 5)                                         */
+ #define R_MTU_TOCR2A_OLS3N_Msk    (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2A_BF_Pos       (6UL)    /*!< BF (Bit 6)                                            */
+ #define R_MTU_TOCR2A_BF_Msk       (0xc0UL) /*!< BF (Bitfield-Mask: 0x03)                              */
+/* =========================================================  TCDRA  ========================================================= */
+/* =========================================================  TDDRA  ========================================================= */
+/* ========================================================  TCNTSA  ========================================================= */
+/* =========================================================  TCBRA  ========================================================= */
+/* ========================================================  TITCR1A  ======================================================== */
+ #define R_MTU_TITCR1A_T4VCOR_Pos      (0UL)    /*!< T4VCOR (Bit 0)                                        */
+ #define R_MTU_TITCR1A_T4VCOR_Msk      (0x7UL)  /*!< T4VCOR (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCR1A_T4VEN_Pos       (3UL)    /*!< T4VEN (Bit 3)                                         */
+ #define R_MTU_TITCR1A_T4VEN_Msk       (0x8UL)  /*!< T4VEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TITCR1A_T3ACOR_Pos      (4UL)    /*!< T3ACOR (Bit 4)                                        */
+ #define R_MTU_TITCR1A_T3ACOR_Msk      (0x70UL) /*!< T3ACOR (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCR1A_T3AEN_Pos       (7UL)    /*!< T3AEN (Bit 7)                                         */
+ #define R_MTU_TITCR1A_T3AEN_Msk       (0x80UL) /*!< T3AEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  TITCNT1A  ======================================================== */
+ #define R_MTU_TITCNT1A_T4VCNT_Pos     (0UL)    /*!< T4VCNT (Bit 0)                                        */
+ #define R_MTU_TITCNT1A_T4VCNT_Msk     (0x7UL)  /*!< T4VCNT (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCNT1A_T3ACNT_Pos     (4UL)    /*!< T3ACNT (Bit 4)                                        */
+ #define R_MTU_TITCNT1A_T3ACNT_Msk     (0x70UL) /*!< T3ACNT (Bitfield-Mask: 0x07)                          */
+/* ========================================================  TBTERA  ========================================================= */
+ #define R_MTU_TBTERA_BTE_Pos          (0UL)    /*!< BTE (Bit 0)                                           */
+ #define R_MTU_TBTERA_BTE_Msk          (0x3UL)  /*!< BTE (Bitfield-Mask: 0x03)                             */
+/* =========================================================  TDERA  ========================================================= */
+ #define R_MTU_TDERA_TDER_Pos          (0UL)    /*!< TDER (Bit 0)                                          */
+ #define R_MTU_TDERA_TDER_Msk          (0x1UL)  /*!< TDER (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOLBRA  ========================================================= */
+ #define R_MTU_TOLBRA_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
+ #define R_MTU_TOLBRA_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
+ #define R_MTU_TOLBRA_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
+ #define R_MTU_TOLBRA_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
+ #define R_MTU_TOLBRA_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
+ #define R_MTU_TOLBRA_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRA_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
+ #define R_MTU_TOLBRA_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TITMRA  ========================================================= */
+ #define R_MTU_TITMRA_TITM_Pos         (0UL)    /*!< TITM (Bit 0)                                          */
+ #define R_MTU_TITMRA_TITM_Msk         (0x1UL)  /*!< TITM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TITCR2A  ======================================================== */
+ #define R_MTU_TITCR2A_TRG4COR_Pos     (0UL)    /*!< TRG4COR (Bit 0)                                       */
+ #define R_MTU_TITCR2A_TRG4COR_Msk     (0x7UL)  /*!< TRG4COR (Bitfield-Mask: 0x07)                         */
+/* =======================================================  TITCNT2A  ======================================================== */
+ #define R_MTU_TITCNT2A_TRG4CNT_Pos    (0UL)    /*!< TRG4CNT (Bit 0)                                       */
+ #define R_MTU_TITCNT2A_TRG4CNT_Msk    (0x7UL)  /*!< TRG4CNT (Bitfield-Mask: 0x07)                         */
+/* =========================================================  TWCRA  ========================================================= */
+ #define R_MTU_TWCRA_WRE_Pos           (0UL)    /*!< WRE (Bit 0)                                           */
+ #define R_MTU_TWCRA_WRE_Msk           (0x1UL)  /*!< WRE (Bitfield-Mask: 0x01)                             */
+ #define R_MTU_TWCRA_SCC_Pos           (1UL)    /*!< SCC (Bit 1)                                           */
+ #define R_MTU_TWCRA_SCC_Msk           (0x2UL)  /*!< SCC (Bitfield-Mask: 0x01)                             */
+ #define R_MTU_TWCRA_CCE_Pos           (7UL)    /*!< CCE (Bit 7)                                           */
+ #define R_MTU_TWCRA_CCE_Msk           (0x80UL) /*!< CCE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  TMDR2A  ========================================================= */
+ #define R_MTU_TMDR2A_DRS_Pos          (0UL)    /*!< DRS (Bit 0)                                           */
+ #define R_MTU_TMDR2A_DRS_Msk          (0x1UL)  /*!< DRS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TSTRA  ========================================================= */
+ #define R_MTU_TSTRA_CST0_Pos          (0UL)    /*!< CST0 (Bit 0)                                          */
+ #define R_MTU_TSTRA_CST0_Msk          (0x1UL)  /*!< CST0 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST1_Pos          (1UL)    /*!< CST1 (Bit 1)                                          */
+ #define R_MTU_TSTRA_CST1_Msk          (0x2UL)  /*!< CST1 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST2_Pos          (2UL)    /*!< CST2 (Bit 2)                                          */
+ #define R_MTU_TSTRA_CST2_Msk          (0x4UL)  /*!< CST2 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST8_Pos          (3UL)    /*!< CST8 (Bit 3)                                          */
+ #define R_MTU_TSTRA_CST8_Msk          (0x8UL)  /*!< CST8 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST3_Pos          (6UL)    /*!< CST3 (Bit 6)                                          */
+ #define R_MTU_TSTRA_CST3_Msk          (0x40UL) /*!< CST3 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRA_CST4_Pos          (7UL)    /*!< CST4 (Bit 7)                                          */
+ #define R_MTU_TSTRA_CST4_Msk          (0x80UL) /*!< CST4 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TSYRA  ========================================================= */
+ #define R_MTU_TSYRA_SYNC0_Pos         (0UL)    /*!< SYNC0 (Bit 0)                                         */
+ #define R_MTU_TSYRA_SYNC0_Msk         (0x1UL)  /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRA_SYNC1_Pos         (1UL)    /*!< SYNC1 (Bit 1)                                         */
+ #define R_MTU_TSYRA_SYNC1_Msk         (0x2UL)  /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRA_SYNC2_Pos         (2UL)    /*!< SYNC2 (Bit 2)                                         */
+ #define R_MTU_TSYRA_SYNC2_Msk         (0x4UL)  /*!< SYNC2 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRA_SYNC3_Pos         (6UL)    /*!< SYNC3 (Bit 6)                                         */
+ #define R_MTU_TSYRA_SYNC3_Msk         (0x40UL) /*!< SYNC3 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRA_SYNC4_Pos         (7UL)    /*!< SYNC4 (Bit 7)                                         */
+ #define R_MTU_TSYRA_SYNC4_Msk         (0x80UL) /*!< SYNC4 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TCSYSTR  ======================================================== */
+ #define R_MTU_TCSYSTR_SCH7_Pos        (0UL)    /*!< SCH7 (Bit 0)                                          */
+ #define R_MTU_TCSYSTR_SCH7_Msk        (0x1UL)  /*!< SCH7 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH6_Pos        (1UL)    /*!< SCH6 (Bit 1)                                          */
+ #define R_MTU_TCSYSTR_SCH6_Msk        (0x2UL)  /*!< SCH6 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH4_Pos        (3UL)    /*!< SCH4 (Bit 3)                                          */
+ #define R_MTU_TCSYSTR_SCH4_Msk        (0x8UL)  /*!< SCH4 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH3_Pos        (4UL)    /*!< SCH3 (Bit 4)                                          */
+ #define R_MTU_TCSYSTR_SCH3_Msk        (0x10UL) /*!< SCH3 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH2_Pos        (5UL)    /*!< SCH2 (Bit 5)                                          */
+ #define R_MTU_TCSYSTR_SCH2_Msk        (0x20UL) /*!< SCH2 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH1_Pos        (6UL)    /*!< SCH1 (Bit 6)                                          */
+ #define R_MTU_TCSYSTR_SCH1_Msk        (0x40UL) /*!< SCH1 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TCSYSTR_SCH0_Pos        (7UL)    /*!< SCH0 (Bit 7)                                          */
+ #define R_MTU_TCSYSTR_SCH0_Msk        (0x80UL) /*!< SCH0 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TRWERA  ========================================================= */
+ #define R_MTU_TRWERA_RWE_Pos          (0UL)    /*!< RWE (Bit 0)                                           */
+ #define R_MTU_TRWERA_RWE_Msk          (0x1UL)  /*!< RWE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TOERB  ========================================================= */
+ #define R_MTU_TOERB_OE6B_Pos          (0UL)    /*!< OE6B (Bit 0)                                          */
+ #define R_MTU_TOERB_OE6B_Msk          (0x1UL)  /*!< OE6B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE7A_Pos          (1UL)    /*!< OE7A (Bit 1)                                          */
+ #define R_MTU_TOERB_OE7A_Msk          (0x2UL)  /*!< OE7A (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE7B_Pos          (2UL)    /*!< OE7B (Bit 2)                                          */
+ #define R_MTU_TOERB_OE7B_Msk          (0x4UL)  /*!< OE7B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE6D_Pos          (3UL)    /*!< OE6D (Bit 3)                                          */
+ #define R_MTU_TOERB_OE6D_Msk          (0x8UL)  /*!< OE6D (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE7C_Pos          (4UL)    /*!< OE7C (Bit 4)                                          */
+ #define R_MTU_TOERB_OE7C_Msk          (0x10UL) /*!< OE7C (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOERB_OE7D_Pos          (5UL)    /*!< OE7D (Bit 5)                                          */
+ #define R_MTU_TOERB_OE7D_Msk          (0x20UL) /*!< OE7D (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOCR1B  ========================================================= */
+ #define R_MTU_TOCR1B_OLSP_Pos         (0UL)    /*!< OLSP (Bit 0)                                          */
+ #define R_MTU_TOCR1B_OLSP_Msk         (0x1UL)  /*!< OLSP (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1B_OLSN_Pos         (1UL)    /*!< OLSN (Bit 1)                                          */
+ #define R_MTU_TOCR1B_OLSN_Msk         (0x2UL)  /*!< OLSN (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1B_TOCS_Pos         (2UL)    /*!< TOCS (Bit 2)                                          */
+ #define R_MTU_TOCR1B_TOCS_Msk         (0x4UL)  /*!< TOCS (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1B_TOCL_Pos         (3UL)    /*!< TOCL (Bit 3)                                          */
+ #define R_MTU_TOCR1B_TOCL_Msk         (0x8UL)  /*!< TOCL (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TOCR1B_PSYE_Pos         (6UL)    /*!< PSYE (Bit 6)                                          */
+ #define R_MTU_TOCR1B_PSYE_Msk         (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOCR2B  ========================================================= */
+ #define R_MTU_TOCR2B_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
+ #define R_MTU_TOCR2B_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
+ #define R_MTU_TOCR2B_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
+ #define R_MTU_TOCR2B_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
+ #define R_MTU_TOCR2B_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
+ #define R_MTU_TOCR2B_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
+ #define R_MTU_TOCR2B_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOCR2B_BF_Pos           (6UL)    /*!< BF (Bit 6)                                            */
+ #define R_MTU_TOCR2B_BF_Msk           (0xc0UL) /*!< BF (Bitfield-Mask: 0x03)                              */
+/* =========================================================  TCDRB  ========================================================= */
+/* =========================================================  TDDRB  ========================================================= */
+/* ========================================================  TCNTSB  ========================================================= */
+/* =========================================================  TCBRB  ========================================================= */
+/* ========================================================  TITCR1B  ======================================================== */
+ #define R_MTU_TITCR1B_T7VCOR_Pos      (0UL)    /*!< T7VCOR (Bit 0)                                        */
+ #define R_MTU_TITCR1B_T7VCOR_Msk      (0x7UL)  /*!< T7VCOR (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCR1B_T7VEN_Pos       (3UL)    /*!< T7VEN (Bit 3)                                         */
+ #define R_MTU_TITCR1B_T7VEN_Msk       (0x8UL)  /*!< T7VEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TITCR1B_T6ACOR_Pos      (4UL)    /*!< T6ACOR (Bit 4)                                        */
+ #define R_MTU_TITCR1B_T6ACOR_Msk      (0x70UL) /*!< T6ACOR (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCR1B_T6AEN_Pos       (7UL)    /*!< T6AEN (Bit 7)                                         */
+ #define R_MTU_TITCR1B_T6AEN_Msk       (0x80UL) /*!< T6AEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  TITCNT1B  ======================================================== */
+ #define R_MTU_TITCNT1B_T7VCNT_Pos     (0UL)    /*!< T7VCNT (Bit 0)                                        */
+ #define R_MTU_TITCNT1B_T7VCNT_Msk     (0x7UL)  /*!< T7VCNT (Bitfield-Mask: 0x07)                          */
+ #define R_MTU_TITCNT1B_T6ACNT_Pos     (4UL)    /*!< T6ACNT (Bit 4)                                        */
+ #define R_MTU_TITCNT1B_T6ACNT_Msk     (0x70UL) /*!< T6ACNT (Bitfield-Mask: 0x07)                          */
+/* ========================================================  TBTERB  ========================================================= */
+ #define R_MTU_TBTERB_BTE_Pos          (0UL)    /*!< BTE (Bit 0)                                           */
+ #define R_MTU_TBTERB_BTE_Msk          (0x3UL)  /*!< BTE (Bitfield-Mask: 0x03)                             */
+/* =========================================================  TDERB  ========================================================= */
+ #define R_MTU_TDERB_TDER_Pos          (0UL)    /*!< TDER (Bit 0)                                          */
+ #define R_MTU_TDERB_TDER_Msk          (0x1UL)  /*!< TDER (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TOLBRB  ========================================================= */
+ #define R_MTU_TOLBRB_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
+ #define R_MTU_TOLBRB_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
+ #define R_MTU_TOLBRB_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
+ #define R_MTU_TOLBRB_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
+ #define R_MTU_TOLBRB_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
+ #define R_MTU_TOLBRB_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TOLBRB_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
+ #define R_MTU_TOLBRB_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TITMRB  ========================================================= */
+ #define R_MTU_TITMRB_TITM_Pos         (0UL)    /*!< TITM (Bit 0)                                          */
+ #define R_MTU_TITMRB_TITM_Msk         (0x1UL)  /*!< TITM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TITCR2B  ======================================================== */
+ #define R_MTU_TITCR2B_TRG7COR_Pos     (0UL)    /*!< TRG7COR (Bit 0)                                       */
+ #define R_MTU_TITCR2B_TRG7COR_Msk     (0x7UL)  /*!< TRG7COR (Bitfield-Mask: 0x07)                         */
+/* =======================================================  TITCNT2B  ======================================================== */
+ #define R_MTU_TITCNT2B_TRG7CNT_Pos    (0UL)    /*!< TRG7CNT (Bit 0)                                       */
+ #define R_MTU_TITCNT2B_TRG7CNT_Msk    (0x7UL)  /*!< TRG7CNT (Bitfield-Mask: 0x07)                         */
+/* =========================================================  TWCRB  ========================================================= */
+ #define R_MTU_TWCRB_WRE_Pos           (0UL)    /*!< WRE (Bit 0)                                           */
+ #define R_MTU_TWCRB_WRE_Msk           (0x1UL)  /*!< WRE (Bitfield-Mask: 0x01)                             */
+ #define R_MTU_TWCRB_SCC_Pos           (1UL)    /*!< SCC (Bit 1)                                           */
+ #define R_MTU_TWCRB_SCC_Msk           (0x2UL)  /*!< SCC (Bitfield-Mask: 0x01)                             */
+ #define R_MTU_TWCRB_CCE_Pos           (7UL)    /*!< CCE (Bit 7)                                           */
+ #define R_MTU_TWCRB_CCE_Msk           (0x80UL) /*!< CCE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  TMDR2B  ========================================================= */
+ #define R_MTU_TMDR2B_DRS_Pos          (0UL)    /*!< DRS (Bit 0)                                           */
+ #define R_MTU_TMDR2B_DRS_Msk          (0x1UL)  /*!< DRS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TSTRB  ========================================================= */
+ #define R_MTU_TSTRB_CST6_Pos          (6UL)    /*!< CST6 (Bit 6)                                          */
+ #define R_MTU_TSTRB_CST6_Msk          (0x40UL) /*!< CST6 (Bitfield-Mask: 0x01)                            */
+ #define R_MTU_TSTRB_CST7_Pos          (7UL)    /*!< CST7 (Bit 7)                                          */
+ #define R_MTU_TSTRB_CST7_Msk          (0x80UL) /*!< CST7 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TSYRB  ========================================================= */
+ #define R_MTU_TSYRB_SYNC6_Pos         (6UL)    /*!< SYNC6 (Bit 6)                                         */
+ #define R_MTU_TSYRB_SYNC6_Msk         (0x40UL) /*!< SYNC6 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_TSYRB_SYNC7_Pos         (7UL)    /*!< SYNC7 (Bit 7)                                         */
+ #define R_MTU_TSYRB_SYNC7_Msk         (0x80UL) /*!< SYNC7 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TRWERB  ========================================================= */
+ #define R_MTU_TRWERB_RWE_Pos          (0UL)    /*!< RWE (Bit 0)                                           */
+ #define R_MTU_TRWERB_RWE_Msk          (0x1UL)  /*!< RWE (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU3                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU3_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU3_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU3_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU3_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU3_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU3_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU3_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU3_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU3_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU3_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU3_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU3_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU3_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU3_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU3_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU3_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU3_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU3_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU3_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU3_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU3_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU3_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU3_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU3_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU3_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU3_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU3_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU3_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU3_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
+ #define R_MTU3_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
+ #define R_MTU3_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
+ #define R_MTU3_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
+ #define R_MTU3_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
+ #define R_MTU3_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
+ #define R_MTU3_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
+ #define R_MTU3_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU3_TBTM_TTSA_Pos     (0UL)    /*!< TTSA (Bit 0)                                          */
+ #define R_MTU3_TBTM_TTSA_Msk     (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU3_TBTM_TTSB_Pos     (1UL)    /*!< TTSB (Bit 1)                                          */
+ #define R_MTU3_TBTM_TTSB_Msk     (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU3_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU3_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TGRE  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU4                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU4_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU4_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU4_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU4_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU4_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU4_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU4_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU4_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU4_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU4_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU4_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU4_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU4_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU4_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU4_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU4_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU4_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU4_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU4_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU4_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU4_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU4_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU4_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU4_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU4_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU4_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TTGE2_Pos    (6UL)    /*!< TTGE2 (Bit 6)                                         */
+ #define R_MTU4_TIER_TTGE2_Msk    (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU4_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU4_TSR_TGFA_Pos        (0UL)      /*!< TGFA (Bit 0)                                          */
+ #define R_MTU4_TSR_TGFA_Msk        (0x1UL)    /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TGFB_Pos        (1UL)      /*!< TGFB (Bit 1)                                          */
+ #define R_MTU4_TSR_TGFB_Msk        (0x2UL)    /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TGFC_Pos        (2UL)      /*!< TGFC (Bit 2)                                          */
+ #define R_MTU4_TSR_TGFC_Msk        (0x4UL)    /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TGFD_Pos        (3UL)      /*!< TGFD (Bit 3)                                          */
+ #define R_MTU4_TSR_TGFD_Msk        (0x8UL)    /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TCFV_Pos        (4UL)      /*!< TCFV (Bit 4)                                          */
+ #define R_MTU4_TSR_TCFV_Msk        (0x10UL)   /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TCFU_Pos        (5UL)      /*!< TCFU (Bit 5)                                          */
+ #define R_MTU4_TSR_TCFU_Msk        (0x20UL)   /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TSR_TCFD_Pos        (7UL)      /*!< TCFD (Bit 7)                                          */
+ #define R_MTU4_TSR_TCFD_Msk        (0x80UL)   /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU4_TBTM_TTSA_Pos       (0UL)      /*!< TTSA (Bit 0)                                          */
+ #define R_MTU4_TBTM_TTSA_Msk       (0x1UL)    /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU4_TBTM_TTSB_Pos       (1UL)      /*!< TTSB (Bit 1)                                          */
+ #define R_MTU4_TBTM_TTSB_Msk       (0x2UL)    /*!< TTSB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TADCR  ========================================================= */
+ #define R_MTU4_TADCR_ITB4VE_Pos    (0UL)      /*!< ITB4VE (Bit 0)                                        */
+ #define R_MTU4_TADCR_ITB4VE_Msk    (0x1UL)    /*!< ITB4VE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU4_TADCR_ITB3AE_Pos    (1UL)      /*!< ITB3AE (Bit 1)                                        */
+ #define R_MTU4_TADCR_ITB3AE_Msk    (0x2UL)    /*!< ITB3AE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU4_TADCR_ITA4VE_Pos    (2UL)      /*!< ITA4VE (Bit 2)                                        */
+ #define R_MTU4_TADCR_ITA4VE_Msk    (0x4UL)    /*!< ITA4VE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU4_TADCR_ITA3AE_Pos    (3UL)      /*!< ITA3AE (Bit 3)                                        */
+ #define R_MTU4_TADCR_ITA3AE_Msk    (0x8UL)    /*!< ITA3AE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU4_TADCR_DT4BE_Pos     (4UL)      /*!< DT4BE (Bit 4)                                         */
+ #define R_MTU4_TADCR_DT4BE_Msk     (0x10UL)   /*!< DT4BE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TADCR_UT4BE_Pos     (5UL)      /*!< UT4BE (Bit 5)                                         */
+ #define R_MTU4_TADCR_UT4BE_Msk     (0x20UL)   /*!< UT4BE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TADCR_DT4AE_Pos     (6UL)      /*!< DT4AE (Bit 6)                                         */
+ #define R_MTU4_TADCR_DT4AE_Msk     (0x40UL)   /*!< DT4AE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TADCR_UT4AE_Pos     (7UL)      /*!< UT4AE (Bit 7)                                         */
+ #define R_MTU4_TADCR_UT4AE_Msk     (0x80UL)   /*!< UT4AE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU4_TADCR_BF_Pos        (14UL)     /*!< BF (Bit 14)                                           */
+ #define R_MTU4_TADCR_BF_Msk        (0xc000UL) /*!< BF (Bitfield-Mask: 0x03)                              */
+/* ========================================================  TADCORA  ======================================================== */
+/* ========================================================  TADCORB  ======================================================== */
+/* =======================================================  TADCOBRA  ======================================================== */
+/* =======================================================  TADCOBRB  ======================================================== */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU4_TCR2_TPSC2_Pos    (0UL)   /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU4_TCR2_TPSC2_Msk    (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TGRE  ========================================================== */
+/* =========================================================  TGRF  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                         R_MTU_NF                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  NFCR0  ========================================================= */
+ #define R_MTU_NF_NFCR0_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR0_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR0_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR0_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR0_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR0_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR0_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR0_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR0_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR0_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR1  ========================================================= */
+ #define R_MTU_NF_NFCR1_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR1_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR1_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR1_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR1_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR1_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR2  ========================================================= */
+ #define R_MTU_NF_NFCR2_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR2_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR2_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR2_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR2_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR2_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR3  ========================================================= */
+ #define R_MTU_NF_NFCR3_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR3_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR3_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR3_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR3_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR3_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR3_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR3_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR3_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR3_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR4  ========================================================= */
+ #define R_MTU_NF_NFCR4_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR4_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR4_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR4_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR4_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR4_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR4_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR4_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR4_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR4_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR8  ========================================================= */
+ #define R_MTU_NF_NFCR8_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR8_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR8_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR8_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR8_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR8_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR8_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR8_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR8_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR8_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCRC  ========================================================= */
+ #define R_MTU_NF_NFCRC_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCRC_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCRC_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCRC_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCRC_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCRC_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCRC_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCRC_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCRC_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCRC_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR6  ========================================================= */
+ #define R_MTU_NF_NFCR6_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR6_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR6_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR6_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR6_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR6_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR6_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR6_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR6_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR6_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR7  ========================================================= */
+ #define R_MTU_NF_NFCR7_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR7_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR7_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR7_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR7_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR7_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR7_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
+ #define R_MTU_NF_NFCR7_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR7_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR7_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  NFCR5  ========================================================= */
+ #define R_MTU_NF_NFCR5_NFUEN_Pos    (0UL)    /*!< NFUEN (Bit 0)                                         */
+ #define R_MTU_NF_NFCR5_NFUEN_Msk    (0x1UL)  /*!< NFUEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR5_NFVEN_Pos    (1UL)    /*!< NFVEN (Bit 1)                                         */
+ #define R_MTU_NF_NFCR5_NFVEN_Msk    (0x2UL)  /*!< NFVEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR5_NFWEN_Pos    (2UL)    /*!< NFWEN (Bit 2)                                         */
+ #define R_MTU_NF_NFCR5_NFWEN_Msk    (0x4UL)  /*!< NFWEN (Bitfield-Mask: 0x01)                           */
+ #define R_MTU_NF_NFCR5_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
+ #define R_MTU_NF_NFCR5_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU0_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU0_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU0_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU0_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU0_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU0_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU0_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU0_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU0_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU0_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU0_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU0_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+ #define R_MTU0_TMDR1_BFE_Pos     (6UL)    /*!< BFE (Bit 6)                                           */
+ #define R_MTU0_TMDR1_BFE_Msk     (0x40UL) /*!< BFE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU0_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU0_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU0_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU0_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU0_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU0_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU0_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU0_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU0_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU0_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU0_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU0_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU0_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU0_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU0_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* =========================================================  TGRE  ========================================================== */
+/* =========================================================  TGRF  ========================================================== */
+/* =========================================================  TIER2  ========================================================= */
+ #define R_MTU0_TIER2_TGIEE_Pos    (0UL)    /*!< TGIEE (Bit 0)                                         */
+ #define R_MTU0_TIER2_TGIEE_Msk    (0x1UL)  /*!< TGIEE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER2_TGIEF_Pos    (1UL)    /*!< TGIEF (Bit 1)                                         */
+ #define R_MTU0_TIER2_TGIEF_Msk    (0x2UL)  /*!< TGIEF (Bitfield-Mask: 0x01)                           */
+ #define R_MTU0_TIER2_TTGE2_Pos    (7UL)    /*!< TTGE2 (Bit 7)                                         */
+ #define R_MTU0_TIER2_TTGE2_Msk    (0x80UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU0_TBTM_TTSA_Pos      (0UL)    /*!< TTSA (Bit 0)                                          */
+ #define R_MTU0_TBTM_TTSA_Msk      (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU0_TBTM_TTSB_Pos      (1UL)    /*!< TTSB (Bit 1)                                          */
+ #define R_MTU0_TBTM_TTSB_Msk      (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU0_TBTM_TTSE_Pos      (2UL)    /*!< TTSE (Bit 2)                                          */
+ #define R_MTU0_TBTM_TTSE_Msk      (0x4UL)  /*!< TTSE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU0_TCR2_TPSC2_Pos     (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU0_TCR2_TPSC2_Msk     (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU1                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU1_TCR_TPSC_Pos         (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU1_TCR_TPSC_Msk         (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU1_TCR_CKEG_Pos         (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU1_TCR_CKEG_Msk         (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU1_TCR_CCLR_Pos         (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU1_TCR_CCLR_Msk         (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU1_TMDR1_MD_Pos         (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU1_TMDR1_MD_Msk         (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+/* =========================================================  TIOR  ========================================================== */
+ #define R_MTU1_TIOR_IOA_Pos         (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU1_TIOR_IOA_Msk         (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU1_TIOR_IOB_Pos         (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU1_TIOR_IOB_Msk         (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU1_TIER_TGIEA_Pos       (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU1_TIER_TGIEA_Msk       (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU1_TIER_TGIEB_Pos       (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU1_TIER_TGIEB_Msk       (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU1_TIER_TCIEV_Pos       (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU1_TIER_TCIEV_Msk       (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU1_TIER_TCIEU_Pos       (5UL)    /*!< TCIEU (Bit 5)                                         */
+ #define R_MTU1_TIER_TCIEU_Msk       (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01)                           */
+ #define R_MTU1_TIER_TTGE_Pos        (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU1_TIER_TTGE_Msk        (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU1_TSR_TGFA_Pos         (0UL)    /*!< TGFA (Bit 0)                                          */
+ #define R_MTU1_TSR_TGFA_Msk         (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TGFB_Pos         (1UL)    /*!< TGFB (Bit 1)                                          */
+ #define R_MTU1_TSR_TGFB_Msk         (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TGFC_Pos         (2UL)    /*!< TGFC (Bit 2)                                          */
+ #define R_MTU1_TSR_TGFC_Msk         (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TGFD_Pos         (3UL)    /*!< TGFD (Bit 3)                                          */
+ #define R_MTU1_TSR_TGFD_Msk         (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TCFV_Pos         (4UL)    /*!< TCFV (Bit 4)                                          */
+ #define R_MTU1_TSR_TCFV_Msk         (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TCFU_Pos         (5UL)    /*!< TCFU (Bit 5)                                          */
+ #define R_MTU1_TSR_TCFU_Msk         (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TSR_TCFD_Pos         (7UL)    /*!< TCFD (Bit 7)                                          */
+ #define R_MTU1_TSR_TCFD_Msk         (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TICCR  ========================================================= */
+ #define R_MTU1_TICCR_I1AE_Pos       (0UL)    /*!< I1AE (Bit 0)                                          */
+ #define R_MTU1_TICCR_I1AE_Msk       (0x1UL)  /*!< I1AE (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TICCR_I1BE_Pos       (1UL)    /*!< I1BE (Bit 1)                                          */
+ #define R_MTU1_TICCR_I1BE_Msk       (0x2UL)  /*!< I1BE (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TICCR_I2AE_Pos       (2UL)    /*!< I2AE (Bit 2)                                          */
+ #define R_MTU1_TICCR_I2AE_Msk       (0x4UL)  /*!< I2AE (Bitfield-Mask: 0x01)                            */
+ #define R_MTU1_TICCR_I2BE_Pos       (3UL)    /*!< I2BE (Bit 3)                                          */
+ #define R_MTU1_TICCR_I2BE_Msk       (0x8UL)  /*!< I2BE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TMDR3  ========================================================= */
+ #define R_MTU1_TMDR3_LWA_Pos        (0UL)    /*!< LWA (Bit 0)                                           */
+ #define R_MTU1_TMDR3_LWA_Msk        (0x1UL)  /*!< LWA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU1_TMDR3_PHCKSEL_Pos    (1UL)    /*!< PHCKSEL (Bit 1)                                       */
+ #define R_MTU1_TMDR3_PHCKSEL_Msk    (0x2UL)  /*!< PHCKSEL (Bitfield-Mask: 0x01)                         */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU1_TCR2_TPSC2_Pos       (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU1_TCR2_TPSC2_Msk       (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU1_TCR2_PCB_Pos         (3UL)    /*!< PCB (Bit 3)                                           */
+ #define R_MTU1_TCR2_PCB_Msk         (0x18UL) /*!< PCB (Bitfield-Mask: 0x03)                             */
+/* ========================================================  TCNTLW  ========================================================= */
+/* ========================================================  TGRALW  ========================================================= */
+/* ========================================================  TGRBLW  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU2                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU2_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU2_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU2_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU2_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU2_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU2_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU2_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU2_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+/* =========================================================  TIOR  ========================================================== */
+ #define R_MTU2_TIOR_IOA_Pos      (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU2_TIOR_IOA_Msk      (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU2_TIOR_IOB_Pos      (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU2_TIOR_IOB_Msk      (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU2_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU2_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU2_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU2_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU2_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU2_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU2_TIER_TCIEU_Pos    (5UL)    /*!< TCIEU (Bit 5)                                         */
+ #define R_MTU2_TIER_TCIEU_Msk    (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01)                           */
+ #define R_MTU2_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU2_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU2_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
+ #define R_MTU2_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
+ #define R_MTU2_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
+ #define R_MTU2_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
+ #define R_MTU2_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
+ #define R_MTU2_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
+ #define R_MTU2_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU2_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
+ #define R_MTU2_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU2_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU2_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU2_TCR2_PCB_Pos      (3UL)    /*!< PCB (Bit 3)                                           */
+ #define R_MTU2_TCR2_PCB_Msk      (0x18UL) /*!< PCB (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU8                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU8_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU8_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU8_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU8_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU8_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU8_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU8_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU8_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU8_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU8_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU8_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU8_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU8_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU8_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU8_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU8_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU8_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU8_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU8_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU8_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU8_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU8_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU8_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU8_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU8_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU8_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU8_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU8_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU8_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU8_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU8_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU8_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU6                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU6_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU6_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU6_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU6_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU6_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU6_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU6_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU6_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU6_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU6_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU6_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU6_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU6_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU6_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU6_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU6_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU6_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU6_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU6_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU6_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU6_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU6_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU6_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU6_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU6_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU6_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU6_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU6_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU6_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
+ #define R_MTU6_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
+ #define R_MTU6_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
+ #define R_MTU6_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
+ #define R_MTU6_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
+ #define R_MTU6_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
+ #define R_MTU6_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
+ #define R_MTU6_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU6_TBTM_TTSA_Pos     (0UL)    /*!< TTSA (Bit 0)                                          */
+ #define R_MTU6_TBTM_TTSA_Msk     (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TBTM_TTSB_Pos     (1UL)    /*!< TTSB (Bit 1)                                          */
+ #define R_MTU6_TBTM_TTSB_Msk     (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU6_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU6_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TSYCR  ========================================================= */
+ #define R_MTU6_TSYCR_CE2B_Pos    (0UL)    /*!< CE2B (Bit 0)                                          */
+ #define R_MTU6_TSYCR_CE2B_Msk    (0x1UL)  /*!< CE2B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE2A_Pos    (1UL)    /*!< CE2A (Bit 1)                                          */
+ #define R_MTU6_TSYCR_CE2A_Msk    (0x2UL)  /*!< CE2A (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE1B_Pos    (2UL)    /*!< CE1B (Bit 2)                                          */
+ #define R_MTU6_TSYCR_CE1B_Msk    (0x4UL)  /*!< CE1B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE1A_Pos    (3UL)    /*!< CE1A (Bit 3)                                          */
+ #define R_MTU6_TSYCR_CE1A_Msk    (0x8UL)  /*!< CE1A (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE0D_Pos    (4UL)    /*!< CE0D (Bit 4)                                          */
+ #define R_MTU6_TSYCR_CE0D_Msk    (0x10UL) /*!< CE0D (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE0C_Pos    (5UL)    /*!< CE0C (Bit 5)                                          */
+ #define R_MTU6_TSYCR_CE0C_Msk    (0x20UL) /*!< CE0C (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE0B_Pos    (6UL)    /*!< CE0B (Bit 6)                                          */
+ #define R_MTU6_TSYCR_CE0B_Msk    (0x40UL) /*!< CE0B (Bitfield-Mask: 0x01)                            */
+ #define R_MTU6_TSYCR_CE0A_Pos    (7UL)    /*!< CE0A (Bit 7)                                          */
+ #define R_MTU6_TSYCR_CE0A_Msk    (0x80UL) /*!< CE0A (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TGRE  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU7                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TCR  ========================================================== */
+ #define R_MTU7_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU7_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
+ #define R_MTU7_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU7_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_MTU7_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
+ #define R_MTU7_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TMDR1  ========================================================= */
+ #define R_MTU7_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
+ #define R_MTU7_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_MTU7_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
+ #define R_MTU7_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
+ #define R_MTU7_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
+ #define R_MTU7_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TIORH  ========================================================= */
+ #define R_MTU7_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
+ #define R_MTU7_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU7_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
+ #define R_MTU7_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIORL  ========================================================= */
+ #define R_MTU7_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU7_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
+ #define R_MTU7_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
+ #define R_MTU7_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU7_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
+ #define R_MTU7_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
+ #define R_MTU7_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
+ #define R_MTU7_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
+ #define R_MTU7_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
+ #define R_MTU7_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TTGE2_Pos    (6UL)    /*!< TTGE2 (Bit 6)                                         */
+ #define R_MTU7_TIER_TTGE2_Msk    (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
+ #define R_MTU7_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TCNT  ========================================================== */
+/* =========================================================  TGRA  ========================================================== */
+/* =========================================================  TGRB  ========================================================== */
+/* =========================================================  TGRC  ========================================================== */
+/* =========================================================  TGRD  ========================================================== */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_MTU7_TSR_TGFA_Pos        (0UL)      /*!< TGFA (Bit 0)                                          */
+ #define R_MTU7_TSR_TGFA_Msk        (0x1UL)    /*!< TGFA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TGFB_Pos        (1UL)      /*!< TGFB (Bit 1)                                          */
+ #define R_MTU7_TSR_TGFB_Msk        (0x2UL)    /*!< TGFB (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TGFC_Pos        (2UL)      /*!< TGFC (Bit 2)                                          */
+ #define R_MTU7_TSR_TGFC_Msk        (0x4UL)    /*!< TGFC (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TGFD_Pos        (3UL)      /*!< TGFD (Bit 3)                                          */
+ #define R_MTU7_TSR_TGFD_Msk        (0x8UL)    /*!< TGFD (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TCFV_Pos        (4UL)      /*!< TCFV (Bit 4)                                          */
+ #define R_MTU7_TSR_TCFV_Msk        (0x10UL)   /*!< TCFV (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TCFU_Pos        (5UL)      /*!< TCFU (Bit 5)                                          */
+ #define R_MTU7_TSR_TCFU_Msk        (0x20UL)   /*!< TCFU (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TSR_TCFD_Pos        (7UL)      /*!< TCFD (Bit 7)                                          */
+ #define R_MTU7_TSR_TCFD_Msk        (0x80UL)   /*!< TCFD (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TBTM  ========================================================== */
+ #define R_MTU7_TBTM_TTSA_Pos       (0UL)      /*!< TTSA (Bit 0)                                          */
+ #define R_MTU7_TBTM_TTSA_Msk       (0x1UL)    /*!< TTSA (Bitfield-Mask: 0x01)                            */
+ #define R_MTU7_TBTM_TTSB_Pos       (1UL)      /*!< TTSB (Bit 1)                                          */
+ #define R_MTU7_TBTM_TTSB_Msk       (0x2UL)    /*!< TTSB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TADCR  ========================================================= */
+ #define R_MTU7_TADCR_ITB7VE_Pos    (0UL)      /*!< ITB7VE (Bit 0)                                        */
+ #define R_MTU7_TADCR_ITB7VE_Msk    (0x1UL)    /*!< ITB7VE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU7_TADCR_ITB6AE_Pos    (1UL)      /*!< ITB6AE (Bit 1)                                        */
+ #define R_MTU7_TADCR_ITB6AE_Msk    (0x2UL)    /*!< ITB6AE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU7_TADCR_ITA7VE_Pos    (2UL)      /*!< ITA7VE (Bit 2)                                        */
+ #define R_MTU7_TADCR_ITA7VE_Msk    (0x4UL)    /*!< ITA7VE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU7_TADCR_ITA6AE_Pos    (3UL)      /*!< ITA6AE (Bit 3)                                        */
+ #define R_MTU7_TADCR_ITA6AE_Msk    (0x8UL)    /*!< ITA6AE (Bitfield-Mask: 0x01)                          */
+ #define R_MTU7_TADCR_DT7BE_Pos     (4UL)      /*!< DT7BE (Bit 4)                                         */
+ #define R_MTU7_TADCR_DT7BE_Msk     (0x10UL)   /*!< DT7BE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TADCR_UT7BE_Pos     (5UL)      /*!< UT7BE (Bit 5)                                         */
+ #define R_MTU7_TADCR_UT7BE_Msk     (0x20UL)   /*!< UT7BE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TADCR_DT7AE_Pos     (6UL)      /*!< DT7AE (Bit 6)                                         */
+ #define R_MTU7_TADCR_DT7AE_Msk     (0x40UL)   /*!< DT7AE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TADCR_UT7AE_Pos     (7UL)      /*!< UT7AE (Bit 7)                                         */
+ #define R_MTU7_TADCR_UT7AE_Msk     (0x80UL)   /*!< UT7AE (Bitfield-Mask: 0x01)                           */
+ #define R_MTU7_TADCR_BF_Pos        (14UL)     /*!< BF (Bit 14)                                           */
+ #define R_MTU7_TADCR_BF_Msk        (0xc000UL) /*!< BF (Bitfield-Mask: 0x03)                              */
+/* ========================================================  TADCORA  ======================================================== */
+/* ========================================================  TADCORB  ======================================================== */
+/* =======================================================  TADCOBRA  ======================================================== */
+/* =======================================================  TADCOBRB  ======================================================== */
+/* =========================================================  TCR2  ========================================================== */
+ #define R_MTU7_TCR2_TPSC2_Pos    (0UL)   /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU7_TCR2_TPSC2_Msk    (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+/* =========================================================  TGRE  ========================================================== */
+/* =========================================================  TGRF  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MTU5                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TCNTU  ========================================================= */
+/* =========================================================  TGRU  ========================================================== */
+/* =========================================================  TCRU  ========================================================== */
+ #define R_MTU5_TCRU_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU5_TCRU_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TCR2U  ========================================================= */
+ #define R_MTU5_TCR2U_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU5_TCR2U_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU5_TCR2U_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU5_TCR2U_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TIORU  ========================================================= */
+ #define R_MTU5_TIORU_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU5_TIORU_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  TCNTV  ========================================================= */
+/* =========================================================  TGRV  ========================================================== */
+/* =========================================================  TCRV  ========================================================== */
+ #define R_MTU5_TCRV_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU5_TCRV_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TCR2V  ========================================================= */
+ #define R_MTU5_TCR2V_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU5_TCR2V_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU5_TCR2V_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU5_TCR2V_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TIORV  ========================================================= */
+ #define R_MTU5_TIORV_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU5_TIORV_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  TCNTW  ========================================================= */
+/* =========================================================  TGRW  ========================================================== */
+/* =========================================================  TCRW  ========================================================== */
+ #define R_MTU5_TCRW_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
+ #define R_MTU5_TCRW_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TCR2W  ========================================================= */
+ #define R_MTU5_TCR2W_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
+ #define R_MTU5_TCR2W_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
+ #define R_MTU5_TCR2W_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
+ #define R_MTU5_TCR2W_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TIORW  ========================================================= */
+ #define R_MTU5_TIORW_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
+ #define R_MTU5_TIORW_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  TIER  ========================================================== */
+ #define R_MTU5_TIER_TGIE5W_Pos            (0UL)    /*!< TGIE5W (Bit 0)                                        */
+ #define R_MTU5_TIER_TGIE5W_Msk            (0x1UL)  /*!< TGIE5W (Bitfield-Mask: 0x01)                          */
+ #define R_MTU5_TIER_TGIE5V_Pos            (1UL)    /*!< TGIE5V (Bit 1)                                        */
+ #define R_MTU5_TIER_TGIE5V_Msk            (0x2UL)  /*!< TGIE5V (Bitfield-Mask: 0x01)                          */
+ #define R_MTU5_TIER_TGIE5U_Pos            (2UL)    /*!< TGIE5U (Bit 2)                                        */
+ #define R_MTU5_TIER_TGIE5U_Msk            (0x4UL)  /*!< TGIE5U (Bitfield-Mask: 0x01)                          */
+/* =========================================================  TSTR  ========================================================== */
+ #define R_MTU5_TSTR_CSTW5_Pos             (0UL)    /*!< CSTW5 (Bit 0)                                         */
+ #define R_MTU5_TSTR_CSTW5_Msk             (0x1UL)  /*!< CSTW5 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU5_TSTR_CSTV5_Pos             (1UL)    /*!< CSTV5 (Bit 1)                                         */
+ #define R_MTU5_TSTR_CSTV5_Msk             (0x2UL)  /*!< CSTV5 (Bitfield-Mask: 0x01)                           */
+ #define R_MTU5_TSTR_CSTU5_Pos             (2UL)    /*!< CSTU5 (Bit 2)                                         */
+ #define R_MTU5_TSTR_CSTU5_Msk             (0x4UL)  /*!< CSTU5 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  TCNTCMPCLR  ======================================================= */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Pos    (0UL)    /*!< CMPCLR5W (Bit 0)                                      */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Msk    (0x1UL)  /*!< CMPCLR5W (Bitfield-Mask: 0x01)                        */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Pos    (1UL)    /*!< CMPCLR5V (Bit 1)                                      */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Msk    (0x2UL)  /*!< CMPCLR5V (Bitfield-Mask: 0x01)                        */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Pos    (2UL)    /*!< CMPCLR5U (Bit 2)                                      */
+ #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Msk    (0x4UL)  /*!< CMPCLR5U (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_TFU0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FXSCIOC  ======================================================== */
+ #define R_TFU0_FXSCIOC_IUF_Pos        (0UL)          /*!< IUF (Bit 0)                                           */
+ #define R_TFU0_FXSCIOC_IUF_Msk        (0x1UL)        /*!< IUF (Bitfield-Mask: 0x01)                             */
+ #define R_TFU0_FXSCIOC_OF_Pos         (4UL)          /*!< OF (Bit 4)                                            */
+ #define R_TFU0_FXSCIOC_OF_Msk         (0x30UL)       /*!< OF (Bitfield-Mask: 0x03)                              */
+/* ========================================================  FXATIOC  ======================================================== */
+ #define R_TFU0_FXATIOC_OUF_Pos        (4UL)          /*!< OUF (Bit 4)                                           */
+ #define R_TFU0_FXATIOC_OUF_Msk        (0x10UL)       /*!< OUF (Bitfield-Mask: 0x01)                             */
+/* ========================================================  TRGSTS  ========================================================= */
+ #define R_TFU0_TRGSTS_BSYF_Pos        (0UL)          /*!< BSYF (Bit 0)                                          */
+ #define R_TFU0_TRGSTS_BSYF_Msk        (0x1UL)        /*!< BSYF (Bitfield-Mask: 0x01)                            */
+ #define R_TFU0_TRGSTS_ERRF_Pos        (1UL)          /*!< ERRF (Bit 1)                                          */
+ #define R_TFU0_TRGSTS_ERRF_Msk        (0x2UL)        /*!< ERRF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  FPSCDT0  ======================================================== */
+ #define R_TFU0_FPSCDT0_FPSCDT0_Pos    (0UL)          /*!< FPSCDT0 (Bit 0)                                       */
+ #define R_TFU0_FPSCDT0_FPSCDT0_Msk    (0xffffffffUL) /*!< FPSCDT0 (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  FPSCDT1  ======================================================== */
+ #define R_TFU0_FPSCDT1_FPSCDT1_Pos    (0UL)          /*!< FPSCDT1 (Bit 0)                                       */
+ #define R_TFU0_FPSCDT1_FPSCDT1_Msk    (0xffffffffUL) /*!< FPSCDT1 (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  FPATDT0  ======================================================== */
+ #define R_TFU0_FPATDT0_FPATDT0_Pos    (0UL)          /*!< FPATDT0 (Bit 0)                                       */
+ #define R_TFU0_FPATDT0_FPATDT0_Msk    (0xffffffffUL) /*!< FPATDT0 (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  FPATDT1  ======================================================== */
+ #define R_TFU0_FPATDT1_FPATDT1_Pos    (0UL)          /*!< FPATDT1 (Bit 0)                                       */
+ #define R_TFU0_FPATDT1_FPATDT1_Msk    (0xffffffffUL) /*!< FPATDT1 (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  FXSCDT0  ======================================================== */
+ #define R_TFU0_FXSCDT0_FXSCDT0_Pos    (0UL)          /*!< FXSCDT0 (Bit 0)                                       */
+ #define R_TFU0_FXSCDT0_FXSCDT0_Msk    (0xffffffffUL) /*!< FXSCDT0 (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  FXSCDT1  ======================================================== */
+ #define R_TFU0_FXSCDT1_FXSCDT1_Pos    (0UL)          /*!< FXSCDT1 (Bit 0)                                       */
+ #define R_TFU0_FXSCDT1_FXSCDT1_Msk    (0xffffffffUL) /*!< FXSCDT1 (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  FXATDT0  ======================================================== */
+ #define R_TFU0_FXATDT0_FXATDT0_Pos    (0UL)          /*!< FXATDT0 (Bit 0)                                       */
+ #define R_TFU0_FXATDT0_FXATDT0_Msk    (0xffffffffUL) /*!< FXATDT0 (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  FXATDT1  ======================================================== */
+ #define R_TFU0_FXATDT1_FXATDT1_Pos    (0UL)          /*!< FXATDT1 (Bit 0)                                       */
+ #define R_TFU0_FXATDT1_FXATDT1_Msk    (0xffffffffUL) /*!< FXATDT1 (Bitfield-Mask: 0xffffffff)                   */
+/* =========================================================  DTSR0  ========================================================= */
+ #define R_TFU0_DTSR0_DTSR0_Pos        (0UL)          /*!< DTSR0 (Bit 0)                                         */
+ #define R_TFU0_DTSR0_DTSR0_Msk        (0xffffffffUL) /*!< DTSR0 (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DTSR1  ========================================================= */
+ #define R_TFU0_DTSR1_DTSR1_Pos        (0UL)          /*!< DTSR1 (Bit 0)                                         */
+ #define R_TFU0_DTSR1_DTSR1_Msk        (0xffffffffUL) /*!< DTSR1 (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ADC120                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ADCSR  ========================================================= */
+ #define R_ADC120_ADCSR_DBLANS_Pos          (0UL)      /*!< DBLANS (Bit 0)                                        */
+ #define R_ADC120_ADCSR_DBLANS_Msk          (0x1fUL)   /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
+ #define R_ADC120_ADCSR_GBADIE_Pos          (6UL)      /*!< GBADIE (Bit 6)                                        */
+ #define R_ADC120_ADCSR_GBADIE_Msk          (0x40UL)   /*!< GBADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC120_ADCSR_DBLE_Pos            (7UL)      /*!< DBLE (Bit 7)                                          */
+ #define R_ADC120_ADCSR_DBLE_Msk            (0x80UL)   /*!< DBLE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC120_ADCSR_EXTRG_Pos           (8UL)      /*!< EXTRG (Bit 8)                                         */
+ #define R_ADC120_ADCSR_EXTRG_Msk           (0x100UL)  /*!< EXTRG (Bitfield-Mask: 0x01)                           */
+ #define R_ADC120_ADCSR_TRGE_Pos            (9UL)      /*!< TRGE (Bit 9)                                          */
+ #define R_ADC120_ADCSR_TRGE_Msk            (0x200UL)  /*!< TRGE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC120_ADCSR_ADIE_Pos            (12UL)     /*!< ADIE (Bit 12)                                         */
+ #define R_ADC120_ADCSR_ADIE_Msk            (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC120_ADCSR_ADCS_Pos            (13UL)     /*!< ADCS (Bit 13)                                         */
+ #define R_ADC120_ADCSR_ADCS_Msk            (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03)                            */
+ #define R_ADC120_ADCSR_ADST_Pos            (15UL)     /*!< ADST (Bit 15)                                         */
+ #define R_ADC120_ADCSR_ADST_Msk            (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADANSA0  ======================================================== */
+ #define R_ADC120_ADANSA0_ANSA0_Pos         (0UL)      /*!< ANSA0 (Bit 0)                                         */
+ #define R_ADC120_ADANSA0_ANSA0_Msk         (0xffffUL) /*!< ANSA0 (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADADS0  ========================================================= */
+ #define R_ADC120_ADADS0_ADS0_Pos           (0UL)      /*!< ADS0 (Bit 0)                                          */
+ #define R_ADC120_ADADS0_ADS0_Msk           (0xffffUL) /*!< ADS0 (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  ADADC  ========================================================= */
+ #define R_ADC120_ADADC_ADC_Pos             (0UL)      /*!< ADC (Bit 0)                                           */
+ #define R_ADC120_ADADC_ADC_Msk             (0x7UL)    /*!< ADC (Bitfield-Mask: 0x07)                             */
+ #define R_ADC120_ADADC_AVEE_Pos            (7UL)      /*!< AVEE (Bit 7)                                          */
+ #define R_ADC120_ADADC_AVEE_Msk            (0x80UL)   /*!< AVEE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADCER  ========================================================= */
+ #define R_ADC120_ADCER_ADPRC_Pos           (1UL)      /*!< ADPRC (Bit 1)                                         */
+ #define R_ADC120_ADCER_ADPRC_Msk           (0x6UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
+ #define R_ADC120_ADCER_ACE_Pos             (5UL)      /*!< ACE (Bit 5)                                           */
+ #define R_ADC120_ADCER_ACE_Msk             (0x20UL)   /*!< ACE (Bitfield-Mask: 0x01)                             */
+ #define R_ADC120_ADCER_ADRFMT_Pos          (15UL)     /*!< ADRFMT (Bit 15)                                       */
+ #define R_ADC120_ADCER_ADRFMT_Msk          (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADSTRGR  ======================================================== */
+ #define R_ADC120_ADSTRGR_TRSB_Pos          (0UL)      /*!< TRSB (Bit 0)                                          */
+ #define R_ADC120_ADSTRGR_TRSB_Msk          (0x3fUL)   /*!< TRSB (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC120_ADSTRGR_TRSA_Pos          (8UL)      /*!< TRSA (Bit 8)                                          */
+ #define R_ADC120_ADSTRGR_TRSA_Msk          (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f)                            */
+/* ========================================================  ADANSB0  ======================================================== */
+ #define R_ADC120_ADANSB0_ANSB0_Pos         (0UL)      /*!< ANSB0 (Bit 0)                                         */
+ #define R_ADC120_ADANSB0_ANSB0_Msk         (0xffffUL) /*!< ANSB0 (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADDBLDR  ======================================================== */
+ #define R_ADC120_ADDBLDR_DBLDR_Pos         (0UL)      /*!< DBLDR (Bit 0)                                         */
+ #define R_ADC120_ADDBLDR_DBLDR_Msk         (0xffffUL) /*!< DBLDR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  ADDR  ========================================================== */
+ #define R_ADC120_ADDR_DR_Pos               (0UL)      /*!< DR (Bit 0)                                            */
+ #define R_ADC120_ADDR_DR_Msk               (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff)                            */
+/* ========================================================  ADSHCR  ========================================================= */
+ #define R_ADC120_ADSHCR_SSTSH_Pos          (0UL)      /*!< SSTSH (Bit 0)                                         */
+ #define R_ADC120_ADSHCR_SSTSH_Msk          (0xffUL)   /*!< SSTSH (Bitfield-Mask: 0xff)                           */
+ #define R_ADC120_ADSHCR_SHANS_Pos          (8UL)      /*!< SHANS (Bit 8)                                         */
+ #define R_ADC120_ADSHCR_SHANS_Msk          (0x700UL)  /*!< SHANS (Bitfield-Mask: 0x07)                           */
+/* ========================================================  ADELCCR  ======================================================== */
+ #define R_ADC120_ADELCCR_ELCC_Pos          (0UL)      /*!< ELCC (Bit 0)                                          */
+ #define R_ADC120_ADELCCR_ELCC_Msk          (0x3UL)    /*!< ELCC (Bitfield-Mask: 0x03)                            */
+ #define R_ADC120_ADELCCR_GCELC_Pos         (2UL)      /*!< GCELC (Bit 2)                                         */
+ #define R_ADC120_ADELCCR_GCELC_Msk         (0x4UL)    /*!< GCELC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADGSPCR  ======================================================== */
+ #define R_ADC120_ADGSPCR_PGS_Pos           (0UL)      /*!< PGS (Bit 0)                                           */
+ #define R_ADC120_ADGSPCR_PGS_Msk           (0x1UL)    /*!< PGS (Bitfield-Mask: 0x01)                             */
+ #define R_ADC120_ADGSPCR_GBRSCN_Pos        (1UL)      /*!< GBRSCN (Bit 1)                                        */
+ #define R_ADC120_ADGSPCR_GBRSCN_Msk        (0x2UL)    /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
+ #define R_ADC120_ADGSPCR_LGRRS_Pos         (14UL)     /*!< LGRRS (Bit 14)                                        */
+ #define R_ADC120_ADGSPCR_LGRRS_Msk         (0x4000UL) /*!< LGRRS (Bitfield-Mask: 0x01)                           */
+ #define R_ADC120_ADGSPCR_GBRP_Pos          (15UL)     /*!< GBRP (Bit 15)                                         */
+ #define R_ADC120_ADGSPCR_GBRP_Msk          (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADDBLDRA  ======================================================== */
+ #define R_ADC120_ADDBLDRA_DBLDRA_Pos       (0UL)      /*!< DBLDRA (Bit 0)                                        */
+ #define R_ADC120_ADDBLDRA_DBLDRA_Msk       (0xffffUL) /*!< DBLDRA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADDBLDRB  ======================================================== */
+ #define R_ADC120_ADDBLDRB_DBLDRB_Pos       (0UL)      /*!< DBLDRB (Bit 0)                                        */
+ #define R_ADC120_ADDBLDRB_DBLDRB_Msk       (0xffffUL) /*!< DBLDRB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADWINMON  ======================================================== */
+ #define R_ADC120_ADWINMON_MONCOMB_Pos      (0UL)      /*!< MONCOMB (Bit 0)                                       */
+ #define R_ADC120_ADWINMON_MONCOMB_Msk      (0x1UL)    /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
+ #define R_ADC120_ADWINMON_MONCMPA_Pos      (4UL)      /*!< MONCMPA (Bit 4)                                       */
+ #define R_ADC120_ADWINMON_MONCMPA_Msk      (0x10UL)   /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC120_ADWINMON_MONCMPB_Pos      (5UL)      /*!< MONCMPB (Bit 5)                                       */
+ #define R_ADC120_ADWINMON_MONCMPB_Msk      (0x20UL)   /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADCMPCR  ======================================================== */
+ #define R_ADC120_ADCMPCR_CMPAB_Pos         (0UL)      /*!< CMPAB (Bit 0)                                         */
+ #define R_ADC120_ADCMPCR_CMPAB_Msk         (0x3UL)    /*!< CMPAB (Bitfield-Mask: 0x03)                           */
+ #define R_ADC120_ADCMPCR_CMPBE_Pos         (9UL)      /*!< CMPBE (Bit 9)                                         */
+ #define R_ADC120_ADCMPCR_CMPBE_Msk         (0x200UL)  /*!< CMPBE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC120_ADCMPCR_CMPAE_Pos         (11UL)     /*!< CMPAE (Bit 11)                                        */
+ #define R_ADC120_ADCMPCR_CMPAE_Msk         (0x800UL)  /*!< CMPAE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC120_ADCMPCR_CMPBIE_Pos        (13UL)     /*!< CMPBIE (Bit 13)                                       */
+ #define R_ADC120_ADCMPCR_CMPBIE_Msk        (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC120_ADCMPCR_WCMPE_Pos         (14UL)     /*!< WCMPE (Bit 14)                                        */
+ #define R_ADC120_ADCMPCR_WCMPE_Msk         (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC120_ADCMPCR_CMPAIE_Pos        (15UL)     /*!< CMPAIE (Bit 15)                                       */
+ #define R_ADC120_ADCMPCR_CMPAIE_Msk        (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
+/* ======================================================  ADCMPANSR0  ======================================================= */
+ #define R_ADC120_ADCMPANSR0_CMPCHA0_Pos    (0UL)      /*!< CMPCHA0 (Bit 0)                                       */
+ #define R_ADC120_ADCMPANSR0_CMPCHA0_Msk    (0xffffUL) /*!< CMPCHA0 (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  ADCMPLR0  ======================================================== */
+ #define R_ADC120_ADCMPLR0_CMPLCHA0_Pos     (0UL)      /*!< CMPLCHA0 (Bit 0)                                      */
+ #define R_ADC120_ADCMPLR0_CMPLCHA0_Msk     (0xffffUL) /*!< CMPLCHA0 (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADCMPDR0  ======================================================== */
+ #define R_ADC120_ADCMPDR0_CMPLLA_Pos       (0UL)      /*!< CMPLLA (Bit 0)                                        */
+ #define R_ADC120_ADCMPDR0_CMPLLA_Msk       (0xffffUL) /*!< CMPLLA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPDR1  ======================================================== */
+ #define R_ADC120_ADCMPDR1_CMPULA_Pos       (0UL)      /*!< CMPULA (Bit 0)                                        */
+ #define R_ADC120_ADCMPDR1_CMPULA_Msk       (0xffffUL) /*!< CMPULA (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPSR0  ======================================================== */
+ #define R_ADC120_ADCMPSR0_CMPSTCHA0_Pos    (0UL)      /*!< CMPSTCHA0 (Bit 0)                                     */
+ #define R_ADC120_ADCMPSR0_CMPSTCHA0_Msk    (0xffffUL) /*!< CMPSTCHA0 (Bitfield-Mask: 0xffff)                     */
+/* =======================================================  ADCMPBNSR  ======================================================= */
+ #define R_ADC120_ADCMPBNSR_CMPCHB_Pos      (0UL)      /*!< CMPCHB (Bit 0)                                        */
+ #define R_ADC120_ADCMPBNSR_CMPCHB_Msk      (0x3fUL)   /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
+ #define R_ADC120_ADCMPBNSR_CMPLB_Pos       (7UL)      /*!< CMPLB (Bit 7)                                         */
+ #define R_ADC120_ADCMPBNSR_CMPLB_Msk       (0x80UL)   /*!< CMPLB (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADWINLLB  ======================================================== */
+ #define R_ADC120_ADWINLLB_CMPLLB_Pos       (0UL)      /*!< CMPLLB (Bit 0)                                        */
+ #define R_ADC120_ADWINLLB_CMPLLB_Msk       (0xffffUL) /*!< CMPLLB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADWINULB  ======================================================== */
+ #define R_ADC120_ADWINULB_CMPULB_Pos       (0UL)      /*!< CMPULB (Bit 0)                                        */
+ #define R_ADC120_ADWINULB_CMPULB_Msk       (0xffffUL) /*!< CMPULB (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  ADCMPBSR  ======================================================== */
+ #define R_ADC120_ADCMPBSR_CMPSTB_Pos       (0UL)      /*!< CMPSTB (Bit 0)                                        */
+ #define R_ADC120_ADCMPBSR_CMPSTB_Msk       (0x1UL)    /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADANSC0  ======================================================== */
+ #define R_ADC120_ADANSC0_ANSC0_Pos         (0UL)      /*!< ANSC0 (Bit 0)                                         */
+ #define R_ADC120_ADANSC0_ANSC0_Msk         (0xffffUL) /*!< ANSC0 (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  ADGCTRGR  ======================================================== */
+ #define R_ADC120_ADGCTRGR_TRSC_Pos         (0UL)      /*!< TRSC (Bit 0)                                          */
+ #define R_ADC120_ADGCTRGR_TRSC_Msk         (0x3fUL)   /*!< TRSC (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC120_ADGCTRGR_GCADIE_Pos       (6UL)      /*!< GCADIE (Bit 6)                                        */
+ #define R_ADC120_ADGCTRGR_GCADIE_Msk       (0x40UL)   /*!< GCADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC120_ADGCTRGR_GRCE_Pos         (7UL)      /*!< GRCE (Bit 7)                                          */
+ #define R_ADC120_ADGCTRGR_GRCE_Msk         (0x80UL)   /*!< GRCE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADSSTR  ========================================================= */
+ #define R_ADC120_ADSSTR_SST_Pos            (0UL)      /*!< SST (Bit 0)                                           */
+ #define R_ADC120_ADSSTR_SST_Msk            (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
+/* =======================================================  ADCALCTL  ======================================================== */
+ #define R_ADC120_ADCALCTL_CAL_Pos          (0UL)      /*!< CAL (Bit 0)                                           */
+ #define R_ADC120_ADCALCTL_CAL_Msk          (0x1UL)    /*!< CAL (Bitfield-Mask: 0x01)                             */
+ #define R_ADC120_ADCALCTL_CAL_RDY_Pos      (1UL)      /*!< CAL_RDY (Bit 1)                                       */
+ #define R_ADC120_ADCALCTL_CAL_RDY_Msk      (0x2UL)    /*!< CAL_RDY (Bitfield-Mask: 0x01)                         */
+ #define R_ADC120_ADCALCTL_CAL_ERR_Pos      (2UL)      /*!< CAL_ERR (Bit 2)                                       */
+ #define R_ADC120_ADCALCTL_CAL_ERR_Msk      (0x4UL)    /*!< CAL_ERR (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POE3                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ICSR1  ========================================================= */
+ #define R_POE3_ICSR1_POE0M_Pos              (0UL)      /*!< POE0M (Bit 0)                                         */
+ #define R_POE3_ICSR1_POE0M_Msk              (0x3UL)    /*!< POE0M (Bitfield-Mask: 0x03)                           */
+ #define R_POE3_ICSR1_PIE1_Pos               (8UL)      /*!< PIE1 (Bit 8)                                          */
+ #define R_POE3_ICSR1_PIE1_Msk               (0x100UL)  /*!< PIE1 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR1_POE0F_Pos              (12UL)     /*!< POE0F (Bit 12)                                        */
+ #define R_POE3_ICSR1_POE0F_Msk              (0x1000UL) /*!< POE0F (Bitfield-Mask: 0x01)                           */
+/* =========================================================  OCSR1  ========================================================= */
+ #define R_POE3_OCSR1_OIE1_Pos               (8UL)      /*!< OIE1 (Bit 8)                                          */
+ #define R_POE3_OCSR1_OIE1_Msk               (0x100UL)  /*!< OIE1 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_OCSR1_OCE1_Pos               (9UL)      /*!< OCE1 (Bit 9)                                          */
+ #define R_POE3_OCSR1_OCE1_Msk               (0x200UL)  /*!< OCE1 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_OCSR1_OSF1_Pos               (15UL)     /*!< OSF1 (Bit 15)                                         */
+ #define R_POE3_OCSR1_OSF1_Msk               (0x8000UL) /*!< OSF1 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSR2  ========================================================= */
+ #define R_POE3_ICSR2_POE4M_Pos              (0UL)      /*!< POE4M (Bit 0)                                         */
+ #define R_POE3_ICSR2_POE4M_Msk              (0x3UL)    /*!< POE4M (Bitfield-Mask: 0x03)                           */
+ #define R_POE3_ICSR2_PIE2_Pos               (8UL)      /*!< PIE2 (Bit 8)                                          */
+ #define R_POE3_ICSR2_PIE2_Msk               (0x100UL)  /*!< PIE2 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR2_POE4F_Pos              (12UL)     /*!< POE4F (Bit 12)                                        */
+ #define R_POE3_ICSR2_POE4F_Msk              (0x1000UL) /*!< POE4F (Bitfield-Mask: 0x01)                           */
+/* =========================================================  OCSR2  ========================================================= */
+ #define R_POE3_OCSR2_OIE2_Pos               (8UL)      /*!< OIE2 (Bit 8)                                          */
+ #define R_POE3_OCSR2_OIE2_Msk               (0x100UL)  /*!< OIE2 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_OCSR2_OCE2_Pos               (9UL)      /*!< OCE2 (Bit 9)                                          */
+ #define R_POE3_OCSR2_OCE2_Msk               (0x200UL)  /*!< OCE2 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_OCSR2_OSF2_Pos               (15UL)     /*!< OSF2 (Bit 15)                                         */
+ #define R_POE3_OCSR2_OSF2_Msk               (0x8000UL) /*!< OSF2 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSR3  ========================================================= */
+ #define R_POE3_ICSR3_POE8M_Pos              (0UL)      /*!< POE8M (Bit 0)                                         */
+ #define R_POE3_ICSR3_POE8M_Msk              (0x3UL)    /*!< POE8M (Bitfield-Mask: 0x03)                           */
+ #define R_POE3_ICSR3_PIE3_Pos               (8UL)      /*!< PIE3 (Bit 8)                                          */
+ #define R_POE3_ICSR3_PIE3_Msk               (0x100UL)  /*!< PIE3 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR3_POE8E_Pos              (9UL)      /*!< POE8E (Bit 9)                                         */
+ #define R_POE3_ICSR3_POE8E_Msk              (0x200UL)  /*!< POE8E (Bitfield-Mask: 0x01)                           */
+ #define R_POE3_ICSR3_POE8F_Pos              (12UL)     /*!< POE8F (Bit 12)                                        */
+ #define R_POE3_ICSR3_POE8F_Msk              (0x1000UL) /*!< POE8F (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPOER  ========================================================= */
+ #define R_POE3_SPOER_MTUCH34HIZ_Pos         (0UL)      /*!< MTUCH34HIZ (Bit 0)                                    */
+ #define R_POE3_SPOER_MTUCH34HIZ_Msk         (0x1UL)    /*!< MTUCH34HIZ (Bitfield-Mask: 0x01)                      */
+ #define R_POE3_SPOER_MTUCH67HIZ_Pos         (1UL)      /*!< MTUCH67HIZ (Bit 1)                                    */
+ #define R_POE3_SPOER_MTUCH67HIZ_Msk         (0x2UL)    /*!< MTUCH67HIZ (Bitfield-Mask: 0x01)                      */
+ #define R_POE3_SPOER_MTUCH0HIZ_Pos          (2UL)      /*!< MTUCH0HIZ (Bit 2)                                     */
+ #define R_POE3_SPOER_MTUCH0HIZ_Msk          (0x4UL)    /*!< MTUCH0HIZ (Bitfield-Mask: 0x01)                       */
+/* ========================================================  POECR1  ========================================================= */
+ #define R_POE3_POECR1_MTU0AZE_Pos           (0UL)      /*!< MTU0AZE (Bit 0)                                       */
+ #define R_POE3_POECR1_MTU0AZE_Msk           (0x1UL)    /*!< MTU0AZE (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_POECR1_MTU0BZE_Pos           (1UL)      /*!< MTU0BZE (Bit 1)                                       */
+ #define R_POE3_POECR1_MTU0BZE_Msk           (0x2UL)    /*!< MTU0BZE (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_POECR1_MTU0CZE_Pos           (2UL)      /*!< MTU0CZE (Bit 2)                                       */
+ #define R_POE3_POECR1_MTU0CZE_Msk           (0x4UL)    /*!< MTU0CZE (Bitfield-Mask: 0x01)                         */
+ #define R_POE3_POECR1_MTU0DZE_Pos           (3UL)      /*!< MTU0DZE (Bit 3)                                       */
+ #define R_POE3_POECR1_MTU0DZE_Msk           (0x8UL)    /*!< MTU0DZE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  POECR2  ========================================================= */
+ #define R_POE3_POECR2_MTU7BDZE_Pos          (0UL)      /*!< MTU7BDZE (Bit 0)                                      */
+ #define R_POE3_POECR2_MTU7BDZE_Msk          (0x1UL)    /*!< MTU7BDZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU7ACZE_Pos          (1UL)      /*!< MTU7ACZE (Bit 1)                                      */
+ #define R_POE3_POECR2_MTU7ACZE_Msk          (0x2UL)    /*!< MTU7ACZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU6BDZE_Pos          (2UL)      /*!< MTU6BDZE (Bit 2)                                      */
+ #define R_POE3_POECR2_MTU6BDZE_Msk          (0x4UL)    /*!< MTU6BDZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU4BDZE_Pos          (8UL)      /*!< MTU4BDZE (Bit 8)                                      */
+ #define R_POE3_POECR2_MTU4BDZE_Msk          (0x100UL)  /*!< MTU4BDZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU4ACZE_Pos          (9UL)      /*!< MTU4ACZE (Bit 9)                                      */
+ #define R_POE3_POECR2_MTU4ACZE_Msk          (0x200UL)  /*!< MTU4ACZE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_POECR2_MTU3BDZE_Pos          (10UL)     /*!< MTU3BDZE (Bit 10)                                     */
+ #define R_POE3_POECR2_MTU3BDZE_Msk          (0x400UL)  /*!< MTU3BDZE (Bitfield-Mask: 0x01)                        */
+/* ========================================================  POECR4  ========================================================= */
+ #define R_POE3_POECR4_IC2ADDMT34ZE_Pos      (2UL)      /*!< IC2ADDMT34ZE (Bit 2)                                  */
+ #define R_POE3_POECR4_IC2ADDMT34ZE_Msk      (0x4UL)    /*!< IC2ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC3ADDMT34ZE_Pos      (3UL)      /*!< IC3ADDMT34ZE (Bit 3)                                  */
+ #define R_POE3_POECR4_IC3ADDMT34ZE_Msk      (0x8UL)    /*!< IC3ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC4ADDMT34ZE_Pos      (4UL)      /*!< IC4ADDMT34ZE (Bit 4)                                  */
+ #define R_POE3_POECR4_IC4ADDMT34ZE_Msk      (0x10UL)   /*!< IC4ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC5ADDMT34ZE_Pos      (5UL)      /*!< IC5ADDMT34ZE (Bit 5)                                  */
+ #define R_POE3_POECR4_IC5ADDMT34ZE_Msk      (0x20UL)   /*!< IC5ADDMT34ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC1ADDMT67ZE_Pos      (9UL)      /*!< IC1ADDMT67ZE (Bit 9)                                  */
+ #define R_POE3_POECR4_IC1ADDMT67ZE_Msk      (0x200UL)  /*!< IC1ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC3ADDMT67ZE_Pos      (11UL)     /*!< IC3ADDMT67ZE (Bit 11)                                 */
+ #define R_POE3_POECR4_IC3ADDMT67ZE_Msk      (0x800UL)  /*!< IC3ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC4ADDMT67ZE_Pos      (12UL)     /*!< IC4ADDMT67ZE (Bit 12)                                 */
+ #define R_POE3_POECR4_IC4ADDMT67ZE_Msk      (0x1000UL) /*!< IC4ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR4_IC5ADDMT67ZE_Pos      (13UL)     /*!< IC5ADDMT67ZE (Bit 13)                                 */
+ #define R_POE3_POECR4_IC5ADDMT67ZE_Msk      (0x2000UL) /*!< IC5ADDMT67ZE (Bitfield-Mask: 0x01)                    */
+/* ========================================================  POECR5  ========================================================= */
+ #define R_POE3_POECR5_IC1ADDMT0ZE_Pos       (1UL)      /*!< IC1ADDMT0ZE (Bit 1)                                   */
+ #define R_POE3_POECR5_IC1ADDMT0ZE_Msk       (0x2UL)    /*!< IC1ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+ #define R_POE3_POECR5_IC2ADDMT0ZE_Pos       (2UL)      /*!< IC2ADDMT0ZE (Bit 2)                                   */
+ #define R_POE3_POECR5_IC2ADDMT0ZE_Msk       (0x4UL)    /*!< IC2ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+ #define R_POE3_POECR5_IC4ADDMT0ZE_Pos       (4UL)      /*!< IC4ADDMT0ZE (Bit 4)                                   */
+ #define R_POE3_POECR5_IC4ADDMT0ZE_Msk       (0x10UL)   /*!< IC4ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+ #define R_POE3_POECR5_IC5ADDMT0ZE_Pos       (5UL)      /*!< IC5ADDMT0ZE (Bit 5)                                   */
+ #define R_POE3_POECR5_IC5ADDMT0ZE_Msk       (0x20UL)   /*!< IC5ADDMT0ZE (Bitfield-Mask: 0x01)                     */
+/* =========================================================  ICSR4  ========================================================= */
+ #define R_POE3_ICSR4_POE10M_Pos             (0UL)      /*!< POE10M (Bit 0)                                        */
+ #define R_POE3_ICSR4_POE10M_Msk             (0x3UL)    /*!< POE10M (Bitfield-Mask: 0x03)                          */
+ #define R_POE3_ICSR4_PIE4_Pos               (8UL)      /*!< PIE4 (Bit 8)                                          */
+ #define R_POE3_ICSR4_PIE4_Msk               (0x100UL)  /*!< PIE4 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR4_POE10E_Pos             (9UL)      /*!< POE10E (Bit 9)                                        */
+ #define R_POE3_ICSR4_POE10E_Msk             (0x200UL)  /*!< POE10E (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ICSR4_POE10F_Pos             (12UL)     /*!< POE10F (Bit 12)                                       */
+ #define R_POE3_ICSR4_POE10F_Msk             (0x1000UL) /*!< POE10F (Bitfield-Mask: 0x01)                          */
+/* =========================================================  ICSR5  ========================================================= */
+ #define R_POE3_ICSR5_POE11M_Pos             (0UL)      /*!< POE11M (Bit 0)                                        */
+ #define R_POE3_ICSR5_POE11M_Msk             (0x3UL)    /*!< POE11M (Bitfield-Mask: 0x03)                          */
+ #define R_POE3_ICSR5_PIE5_Pos               (8UL)      /*!< PIE5 (Bit 8)                                          */
+ #define R_POE3_ICSR5_PIE5_Msk               (0x100UL)  /*!< PIE5 (Bitfield-Mask: 0x01)                            */
+ #define R_POE3_ICSR5_POE11E_Pos             (9UL)      /*!< POE11E (Bit 9)                                        */
+ #define R_POE3_ICSR5_POE11E_Msk             (0x200UL)  /*!< POE11E (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ICSR5_POE11F_Pos             (12UL)     /*!< POE11F (Bit 12)                                       */
+ #define R_POE3_ICSR5_POE11F_Msk             (0x1000UL) /*!< POE11F (Bitfield-Mask: 0x01)                          */
+/* =========================================================  ALR1  ========================================================== */
+ #define R_POE3_ALR1_OLSG0A_Pos              (0UL)      /*!< OLSG0A (Bit 0)                                        */
+ #define R_POE3_ALR1_OLSG0A_Msk              (0x1UL)    /*!< OLSG0A (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG0B_Pos              (1UL)      /*!< OLSG0B (Bit 1)                                        */
+ #define R_POE3_ALR1_OLSG0B_Msk              (0x2UL)    /*!< OLSG0B (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG1A_Pos              (2UL)      /*!< OLSG1A (Bit 2)                                        */
+ #define R_POE3_ALR1_OLSG1A_Msk              (0x4UL)    /*!< OLSG1A (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG1B_Pos              (3UL)      /*!< OLSG1B (Bit 3)                                        */
+ #define R_POE3_ALR1_OLSG1B_Msk              (0x8UL)    /*!< OLSG1B (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG2A_Pos              (4UL)      /*!< OLSG2A (Bit 4)                                        */
+ #define R_POE3_ALR1_OLSG2A_Msk              (0x10UL)   /*!< OLSG2A (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSG2B_Pos              (5UL)      /*!< OLSG2B (Bit 5)                                        */
+ #define R_POE3_ALR1_OLSG2B_Msk              (0x20UL)   /*!< OLSG2B (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ALR1_OLSEN_Pos               (7UL)      /*!< OLSEN (Bit 7)                                         */
+ #define R_POE3_ALR1_OLSEN_Msk               (0x80UL)   /*!< OLSEN (Bitfield-Mask: 0x01)                           */
+/* =========================================================  ICSR6  ========================================================= */
+ #define R_POE3_ICSR6_OSTSTE_Pos             (9UL)      /*!< OSTSTE (Bit 9)                                        */
+ #define R_POE3_ICSR6_OSTSTE_Msk             (0x200UL)  /*!< OSTSTE (Bitfield-Mask: 0x01)                          */
+ #define R_POE3_ICSR6_OSTSTF_Pos             (12UL)     /*!< OSTSTF (Bit 12)                                       */
+ #define R_POE3_ICSR6_OSTSTF_Msk             (0x1000UL) /*!< OSTSTF (Bitfield-Mask: 0x01)                          */
+/* =========================================================  ICSR7  ========================================================= */
+ #define R_POE3_ICSR7_D0ERR0ST_Pos           (0UL)      /*!< D0ERR0ST (Bit 0)                                      */
+ #define R_POE3_ICSR7_D0ERR0ST_Msk           (0x1UL)    /*!< D0ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D1ERR0ST_Pos           (1UL)      /*!< D1ERR0ST (Bit 1)                                      */
+ #define R_POE3_ICSR7_D1ERR0ST_Msk           (0x2UL)    /*!< D1ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D2ERR0ST_Pos           (2UL)      /*!< D2ERR0ST (Bit 2)                                      */
+ #define R_POE3_ICSR7_D2ERR0ST_Msk           (0x4UL)    /*!< D2ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D3ERR0ST_Pos           (3UL)      /*!< D3ERR0ST (Bit 3)                                      */
+ #define R_POE3_ICSR7_D3ERR0ST_Msk           (0x8UL)    /*!< D3ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D4ERR0ST_Pos           (4UL)      /*!< D4ERR0ST (Bit 4)                                      */
+ #define R_POE3_ICSR7_D4ERR0ST_Msk           (0x10UL)   /*!< D4ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D5ERR0ST_Pos           (5UL)      /*!< D5ERR0ST (Bit 5)                                      */
+ #define R_POE3_ICSR7_D5ERR0ST_Msk           (0x20UL)   /*!< D5ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D6ERR0ST_Pos           (6UL)      /*!< D6ERR0ST (Bit 6)                                      */
+ #define R_POE3_ICSR7_D6ERR0ST_Msk           (0x40UL)   /*!< D6ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D7ERR0ST_Pos           (7UL)      /*!< D7ERR0ST (Bit 7)                                      */
+ #define R_POE3_ICSR7_D7ERR0ST_Msk           (0x80UL)   /*!< D7ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D8ERR0ST_Pos           (8UL)      /*!< D8ERR0ST (Bit 8)                                      */
+ #define R_POE3_ICSR7_D8ERR0ST_Msk           (0x100UL)  /*!< D8ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR7_D9ERR0ST_Pos           (9UL)      /*!< D9ERR0ST (Bit 9)                                      */
+ #define R_POE3_ICSR7_D9ERR0ST_Msk           (0x200UL)  /*!< D9ERR0ST (Bitfield-Mask: 0x01)                        */
+/* ========================================================  M0SELR1  ======================================================== */
+ #define R_POE3_M0SELR1_M0ASEL_Pos           (0UL)      /*!< M0ASEL (Bit 0)                                        */
+ #define R_POE3_M0SELR1_M0ASEL_Msk           (0xfUL)    /*!< M0ASEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M0SELR1_M0BSEL_Pos           (4UL)      /*!< M0BSEL (Bit 4)                                        */
+ #define R_POE3_M0SELR1_M0BSEL_Msk           (0xf0UL)   /*!< M0BSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M0SELR2  ======================================================== */
+ #define R_POE3_M0SELR2_M0CSEL_Pos           (0UL)      /*!< M0CSEL (Bit 0)                                        */
+ #define R_POE3_M0SELR2_M0CSEL_Msk           (0xfUL)    /*!< M0CSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M0SELR2_M0DSEL_Pos           (4UL)      /*!< M0DSEL (Bit 4)                                        */
+ #define R_POE3_M0SELR2_M0DSEL_Msk           (0xf0UL)   /*!< M0DSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M3SELR  ========================================================= */
+ #define R_POE3_M3SELR_M3BSEL_Pos            (0UL)      /*!< M3BSEL (Bit 0)                                        */
+ #define R_POE3_M3SELR_M3BSEL_Msk            (0xfUL)    /*!< M3BSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M3SELR_M3DSEL_Pos            (4UL)      /*!< M3DSEL (Bit 4)                                        */
+ #define R_POE3_M3SELR_M3DSEL_Msk            (0xf0UL)   /*!< M3DSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M4SELR1  ======================================================== */
+ #define R_POE3_M4SELR1_M4ASEL_Pos           (0UL)      /*!< M4ASEL (Bit 0)                                        */
+ #define R_POE3_M4SELR1_M4ASEL_Msk           (0xfUL)    /*!< M4ASEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M4SELR1_M4CSEL_Pos           (4UL)      /*!< M4CSEL (Bit 4)                                        */
+ #define R_POE3_M4SELR1_M4CSEL_Msk           (0xf0UL)   /*!< M4CSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M4SELR2  ======================================================== */
+ #define R_POE3_M4SELR2_M4BSEL_Pos           (0UL)      /*!< M4BSEL (Bit 0)                                        */
+ #define R_POE3_M4SELR2_M4BSEL_Msk           (0xfUL)    /*!< M4BSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M4SELR2_M4DSEL_Pos           (4UL)      /*!< M4DSEL (Bit 4)                                        */
+ #define R_POE3_M4SELR2_M4DSEL_Msk           (0xf0UL)   /*!< M4DSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M6SELR  ========================================================= */
+ #define R_POE3_M6SELR_M6BSEL_Pos            (0UL)      /*!< M6BSEL (Bit 0)                                        */
+ #define R_POE3_M6SELR_M6BSEL_Msk            (0xfUL)    /*!< M6BSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M6SELR_M6DSEL_Pos            (4UL)      /*!< M6DSEL (Bit 4)                                        */
+ #define R_POE3_M6SELR_M6DSEL_Msk            (0xf0UL)   /*!< M6DSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M7SELR1  ======================================================== */
+ #define R_POE3_M7SELR1_M7ASEL_Pos           (0UL)      /*!< M7ASEL (Bit 0)                                        */
+ #define R_POE3_M7SELR1_M7ASEL_Msk           (0xfUL)    /*!< M7ASEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M7SELR1_M7CSEL_Pos           (4UL)      /*!< M7CSEL (Bit 4)                                        */
+ #define R_POE3_M7SELR1_M7CSEL_Msk           (0xf0UL)   /*!< M7CSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  M7SELR2  ======================================================== */
+ #define R_POE3_M7SELR2_M7BSEL_Pos           (0UL)      /*!< M7BSEL (Bit 0)                                        */
+ #define R_POE3_M7SELR2_M7BSEL_Msk           (0xfUL)    /*!< M7BSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_POE3_M7SELR2_M7DSEL_Pos           (4UL)      /*!< M7DSEL (Bit 4)                                        */
+ #define R_POE3_M7SELR2_M7DSEL_Msk           (0xf0UL)   /*!< M7DSEL (Bitfield-Mask: 0x0f)                          */
+/* =========================================================  ICSR8  ========================================================= */
+ #define R_POE3_ICSR8_D0ERR1ST_Pos           (0UL)      /*!< D0ERR1ST (Bit 0)                                      */
+ #define R_POE3_ICSR8_D0ERR1ST_Msk           (0x1UL)    /*!< D0ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D1ERR1ST_Pos           (1UL)      /*!< D1ERR1ST (Bit 1)                                      */
+ #define R_POE3_ICSR8_D1ERR1ST_Msk           (0x2UL)    /*!< D1ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D2ERR1ST_Pos           (2UL)      /*!< D2ERR1ST (Bit 2)                                      */
+ #define R_POE3_ICSR8_D2ERR1ST_Msk           (0x4UL)    /*!< D2ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D3ERR1ST_Pos           (3UL)      /*!< D3ERR1ST (Bit 3)                                      */
+ #define R_POE3_ICSR8_D3ERR1ST_Msk           (0x8UL)    /*!< D3ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D4ERR1ST_Pos           (4UL)      /*!< D4ERR1ST (Bit 4)                                      */
+ #define R_POE3_ICSR8_D4ERR1ST_Msk           (0x10UL)   /*!< D4ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D5ERR1ST_Pos           (5UL)      /*!< D5ERR1ST (Bit 5)                                      */
+ #define R_POE3_ICSR8_D5ERR1ST_Msk           (0x20UL)   /*!< D5ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D6ERR1ST_Pos           (6UL)      /*!< D6ERR1ST (Bit 6)                                      */
+ #define R_POE3_ICSR8_D6ERR1ST_Msk           (0x40UL)   /*!< D6ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D7ERR1ST_Pos           (7UL)      /*!< D7ERR1ST (Bit 7)                                      */
+ #define R_POE3_ICSR8_D7ERR1ST_Msk           (0x80UL)   /*!< D7ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D8ERR1ST_Pos           (8UL)      /*!< D8ERR1ST (Bit 8)                                      */
+ #define R_POE3_ICSR8_D8ERR1ST_Msk           (0x100UL)  /*!< D8ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR8_D9ERR1ST_Pos           (9UL)      /*!< D9ERR1ST (Bit 9)                                      */
+ #define R_POE3_ICSR8_D9ERR1ST_Msk           (0x200UL)  /*!< D9ERR1ST (Bitfield-Mask: 0x01)                        */
+/* =========================================================  ICSR9  ========================================================= */
+ #define R_POE3_ICSR9_D0ERR0IE_Pos           (0UL)      /*!< D0ERR0IE (Bit 0)                                      */
+ #define R_POE3_ICSR9_D0ERR0IE_Msk           (0x1UL)    /*!< D0ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D1ERR0IE_Pos           (1UL)      /*!< D1ERR0IE (Bit 1)                                      */
+ #define R_POE3_ICSR9_D1ERR0IE_Msk           (0x2UL)    /*!< D1ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D2ERR0IE_Pos           (2UL)      /*!< D2ERR0IE (Bit 2)                                      */
+ #define R_POE3_ICSR9_D2ERR0IE_Msk           (0x4UL)    /*!< D2ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D3ERR0IE_Pos           (3UL)      /*!< D3ERR0IE (Bit 3)                                      */
+ #define R_POE3_ICSR9_D3ERR0IE_Msk           (0x8UL)    /*!< D3ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D4ERR0IE_Pos           (4UL)      /*!< D4ERR0IE (Bit 4)                                      */
+ #define R_POE3_ICSR9_D4ERR0IE_Msk           (0x10UL)   /*!< D4ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D5ERR0IE_Pos           (5UL)      /*!< D5ERR0IE (Bit 5)                                      */
+ #define R_POE3_ICSR9_D5ERR0IE_Msk           (0x20UL)   /*!< D5ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D6ERR0IE_Pos           (6UL)      /*!< D6ERR0IE (Bit 6)                                      */
+ #define R_POE3_ICSR9_D6ERR0IE_Msk           (0x40UL)   /*!< D6ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D7ERR0IE_Pos           (7UL)      /*!< D7ERR0IE (Bit 7)                                      */
+ #define R_POE3_ICSR9_D7ERR0IE_Msk           (0x80UL)   /*!< D7ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D8ERR0IE_Pos           (8UL)      /*!< D8ERR0IE (Bit 8)                                      */
+ #define R_POE3_ICSR9_D8ERR0IE_Msk           (0x100UL)  /*!< D8ERR0IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR9_D9ERR0IE_Pos           (9UL)      /*!< D9ERR0IE (Bit 9)                                      */
+ #define R_POE3_ICSR9_D9ERR0IE_Msk           (0x200UL)  /*!< D9ERR0IE (Bitfield-Mask: 0x01)                        */
+/* ========================================================  ICSR10  ========================================================= */
+ #define R_POE3_ICSR10_D0ERR1IE_Pos          (0UL)      /*!< D0ERR1IE (Bit 0)                                      */
+ #define R_POE3_ICSR10_D0ERR1IE_Msk          (0x1UL)    /*!< D0ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D1ERR1IE_Pos          (1UL)      /*!< D1ERR1IE (Bit 1)                                      */
+ #define R_POE3_ICSR10_D1ERR1IE_Msk          (0x2UL)    /*!< D1ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D2ERR1IE_Pos          (2UL)      /*!< D2ERR1IE (Bit 2)                                      */
+ #define R_POE3_ICSR10_D2ERR1IE_Msk          (0x4UL)    /*!< D2ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D3ERR1IE_Pos          (3UL)      /*!< D3ERR1IE (Bit 3)                                      */
+ #define R_POE3_ICSR10_D3ERR1IE_Msk          (0x8UL)    /*!< D3ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D4ERR1IE_Pos          (4UL)      /*!< D4ERR1IE (Bit 4)                                      */
+ #define R_POE3_ICSR10_D4ERR1IE_Msk          (0x10UL)   /*!< D4ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D5ERR1IE_Pos          (5UL)      /*!< D5ERR1IE (Bit 5)                                      */
+ #define R_POE3_ICSR10_D5ERR1IE_Msk          (0x20UL)   /*!< D5ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D6ERR1IE_Pos          (6UL)      /*!< D6ERR1IE (Bit 6)                                      */
+ #define R_POE3_ICSR10_D6ERR1IE_Msk          (0x40UL)   /*!< D6ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D7ERR1IE_Pos          (7UL)      /*!< D7ERR1IE (Bit 7)                                      */
+ #define R_POE3_ICSR10_D7ERR1IE_Msk          (0x80UL)   /*!< D7ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D8ERR1IE_Pos          (8UL)      /*!< D8ERR1IE (Bit 8)                                      */
+ #define R_POE3_ICSR10_D8ERR1IE_Msk          (0x100UL)  /*!< D8ERR1IE (Bitfield-Mask: 0x01)                        */
+ #define R_POE3_ICSR10_D9ERR1IE_Pos          (9UL)      /*!< D9ERR1IE (Bit 9)                                      */
+ #define R_POE3_ICSR10_D9ERR1IE_Msk          (0x200UL)  /*!< D9ERR1IE (Bitfield-Mask: 0x01)                        */
+/* ========================================================  POECR7  ========================================================= */
+ #define R_POE3_POECR7_D0E0ADDMT0ZE_Pos      (0UL)      /*!< D0E0ADDMT0ZE (Bit 0)                                  */
+ #define R_POE3_POECR7_D0E0ADDMT0ZE_Msk      (0x1UL)    /*!< D0E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D1E0ADDMT0ZE_Pos      (1UL)      /*!< D1E0ADDMT0ZE (Bit 1)                                  */
+ #define R_POE3_POECR7_D1E0ADDMT0ZE_Msk      (0x2UL)    /*!< D1E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D2E0ADDMT0ZE_Pos      (2UL)      /*!< D2E0ADDMT0ZE (Bit 2)                                  */
+ #define R_POE3_POECR7_D2E0ADDMT0ZE_Msk      (0x4UL)    /*!< D2E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D3E0ADDMT0ZE_Pos      (3UL)      /*!< D3E0ADDMT0ZE (Bit 3)                                  */
+ #define R_POE3_POECR7_D3E0ADDMT0ZE_Msk      (0x8UL)    /*!< D3E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D4E0ADDMT0ZE_Pos      (4UL)      /*!< D4E0ADDMT0ZE (Bit 4)                                  */
+ #define R_POE3_POECR7_D4E0ADDMT0ZE_Msk      (0x10UL)   /*!< D4E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D5E0ADDMT0ZE_Pos      (5UL)      /*!< D5E0ADDMT0ZE (Bit 5)                                  */
+ #define R_POE3_POECR7_D5E0ADDMT0ZE_Msk      (0x20UL)   /*!< D5E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D6E0ADDMT0ZE_Pos      (6UL)      /*!< D6E0ADDMT0ZE (Bit 6)                                  */
+ #define R_POE3_POECR7_D6E0ADDMT0ZE_Msk      (0x40UL)   /*!< D6E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D7E0ADDMT0ZE_Pos      (7UL)      /*!< D7E0ADDMT0ZE (Bit 7)                                  */
+ #define R_POE3_POECR7_D7E0ADDMT0ZE_Msk      (0x80UL)   /*!< D7E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D8E0ADDMT0ZE_Pos      (8UL)      /*!< D8E0ADDMT0ZE (Bit 8)                                  */
+ #define R_POE3_POECR7_D8E0ADDMT0ZE_Msk      (0x100UL)  /*!< D8E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR7_D9E0ADDMT0ZE_Pos      (9UL)      /*!< D9E0ADDMT0ZE (Bit 9)                                  */
+ #define R_POE3_POECR7_D9E0ADDMT0ZE_Msk      (0x200UL)  /*!< D9E0ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+/* ========================================================  POECR8  ========================================================= */
+ #define R_POE3_POECR8_D0E1ADDMT0ZE_Pos      (0UL)      /*!< D0E1ADDMT0ZE (Bit 0)                                  */
+ #define R_POE3_POECR8_D0E1ADDMT0ZE_Msk      (0x1UL)    /*!< D0E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D1E1ADDMT0ZE_Pos      (1UL)      /*!< D1E1ADDMT0ZE (Bit 1)                                  */
+ #define R_POE3_POECR8_D1E1ADDMT0ZE_Msk      (0x2UL)    /*!< D1E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D2E1ADDMT0ZE_Pos      (2UL)      /*!< D2E1ADDMT0ZE (Bit 2)                                  */
+ #define R_POE3_POECR8_D2E1ADDMT0ZE_Msk      (0x4UL)    /*!< D2E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D3E1ADDMT0ZE_Pos      (3UL)      /*!< D3E1ADDMT0ZE (Bit 3)                                  */
+ #define R_POE3_POECR8_D3E1ADDMT0ZE_Msk      (0x8UL)    /*!< D3E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D4E1ADDMT0ZE_Pos      (4UL)      /*!< D4E1ADDMT0ZE (Bit 4)                                  */
+ #define R_POE3_POECR8_D4E1ADDMT0ZE_Msk      (0x10UL)   /*!< D4E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D5E1ADDMT0ZE_Pos      (5UL)      /*!< D5E1ADDMT0ZE (Bit 5)                                  */
+ #define R_POE3_POECR8_D5E1ADDMT0ZE_Msk      (0x20UL)   /*!< D5E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D6E1ADDMT0ZE_Pos      (6UL)      /*!< D6E1ADDMT0ZE (Bit 6)                                  */
+ #define R_POE3_POECR8_D6E1ADDMT0ZE_Msk      (0x40UL)   /*!< D6E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D7E1ADDMT0ZE_Pos      (7UL)      /*!< D7E1ADDMT0ZE (Bit 7)                                  */
+ #define R_POE3_POECR8_D7E1ADDMT0ZE_Msk      (0x80UL)   /*!< D7E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D8E1ADDMT0ZE_Pos      (8UL)      /*!< D8E1ADDMT0ZE (Bit 8)                                  */
+ #define R_POE3_POECR8_D8E1ADDMT0ZE_Msk      (0x100UL)  /*!< D8E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+ #define R_POE3_POECR8_D9E1ADDMT0ZE_Pos      (9UL)      /*!< D9E1ADDMT0ZE (Bit 9)                                  */
+ #define R_POE3_POECR8_D9E1ADDMT0ZE_Msk      (0x200UL)  /*!< D9E1ADDMT0ZE (Bitfield-Mask: 0x01)                    */
+/* ========================================================  POECR9  ========================================================= */
+ #define R_POE3_POECR9_D0E0ADDMT34ZE_Pos     (0UL)      /*!< D0E0ADDMT34ZE (Bit 0)                                 */
+ #define R_POE3_POECR9_D0E0ADDMT34ZE_Msk     (0x1UL)    /*!< D0E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D1E0ADDMT34ZE_Pos     (1UL)      /*!< D1E0ADDMT34ZE (Bit 1)                                 */
+ #define R_POE3_POECR9_D1E0ADDMT34ZE_Msk     (0x2UL)    /*!< D1E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D2E0ADDMT34ZE_Pos     (2UL)      /*!< D2E0ADDMT34ZE (Bit 2)                                 */
+ #define R_POE3_POECR9_D2E0ADDMT34ZE_Msk     (0x4UL)    /*!< D2E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D3E0ADDMT34ZE_Pos     (3UL)      /*!< D3E0ADDMT34ZE (Bit 3)                                 */
+ #define R_POE3_POECR9_D3E0ADDMT34ZE_Msk     (0x8UL)    /*!< D3E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D4E0ADDMT34ZE_Pos     (4UL)      /*!< D4E0ADDMT34ZE (Bit 4)                                 */
+ #define R_POE3_POECR9_D4E0ADDMT34ZE_Msk     (0x10UL)   /*!< D4E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D5E0ADDMT34ZE_Pos     (5UL)      /*!< D5E0ADDMT34ZE (Bit 5)                                 */
+ #define R_POE3_POECR9_D5E0ADDMT34ZE_Msk     (0x20UL)   /*!< D5E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D6E0ADDMT34ZE_Pos     (6UL)      /*!< D6E0ADDMT34ZE (Bit 6)                                 */
+ #define R_POE3_POECR9_D6E0ADDMT34ZE_Msk     (0x40UL)   /*!< D6E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D7E0ADDMT34ZE_Pos     (7UL)      /*!< D7E0ADDMT34ZE (Bit 7)                                 */
+ #define R_POE3_POECR9_D7E0ADDMT34ZE_Msk     (0x80UL)   /*!< D7E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D8E0ADDMT34ZE_Pos     (8UL)      /*!< D8E0ADDMT34ZE (Bit 8)                                 */
+ #define R_POE3_POECR9_D8E0ADDMT34ZE_Msk     (0x100UL)  /*!< D8E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR9_D9E0ADDMT34ZE_Pos     (9UL)      /*!< D9E0ADDMT34ZE (Bit 9)                                 */
+ #define R_POE3_POECR9_D9E0ADDMT34ZE_Msk     (0x200UL)  /*!< D9E0ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+/* ========================================================  POECR10  ======================================================== */
+ #define R_POE3_POECR10_D0E1ADDMT34ZE_Pos    (0UL)      /*!< D0E1ADDMT34ZE (Bit 0)                                 */
+ #define R_POE3_POECR10_D0E1ADDMT34ZE_Msk    (0x1UL)    /*!< D0E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D1E1ADDMT34ZE_Pos    (1UL)      /*!< D1E1ADDMT34ZE (Bit 1)                                 */
+ #define R_POE3_POECR10_D1E1ADDMT34ZE_Msk    (0x2UL)    /*!< D1E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D2E1ADDMT34ZE_Pos    (2UL)      /*!< D2E1ADDMT34ZE (Bit 2)                                 */
+ #define R_POE3_POECR10_D2E1ADDMT34ZE_Msk    (0x4UL)    /*!< D2E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D3E1ADDMT34ZE_Pos    (3UL)      /*!< D3E1ADDMT34ZE (Bit 3)                                 */
+ #define R_POE3_POECR10_D3E1ADDMT34ZE_Msk    (0x8UL)    /*!< D3E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D4E1ADDMT34ZE_Pos    (4UL)      /*!< D4E1ADDMT34ZE (Bit 4)                                 */
+ #define R_POE3_POECR10_D4E1ADDMT34ZE_Msk    (0x10UL)   /*!< D4E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D5E1ADDMT34ZE_Pos    (5UL)      /*!< D5E1ADDMT34ZE (Bit 5)                                 */
+ #define R_POE3_POECR10_D5E1ADDMT34ZE_Msk    (0x20UL)   /*!< D5E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D6E1ADDMT34ZE_Pos    (6UL)      /*!< D6E1ADDMT34ZE (Bit 6)                                 */
+ #define R_POE3_POECR10_D6E1ADDMT34ZE_Msk    (0x40UL)   /*!< D6E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D7E1ADDMT34ZE_Pos    (7UL)      /*!< D7E1ADDMT34ZE (Bit 7)                                 */
+ #define R_POE3_POECR10_D7E1ADDMT34ZE_Msk    (0x80UL)   /*!< D7E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D8E1ADDMT34ZE_Pos    (8UL)      /*!< D8E1ADDMT34ZE (Bit 8)                                 */
+ #define R_POE3_POECR10_D8E1ADDMT34ZE_Msk    (0x100UL)  /*!< D8E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR10_D9E1ADDMT34ZE_Pos    (9UL)      /*!< D9E1ADDMT34ZE (Bit 9)                                 */
+ #define R_POE3_POECR10_D9E1ADDMT34ZE_Msk    (0x200UL)  /*!< D9E1ADDMT34ZE (Bitfield-Mask: 0x01)                   */
+/* ========================================================  POECR11  ======================================================== */
+ #define R_POE3_POECR11_D0E0ADDMT67ZE_Pos    (0UL)      /*!< D0E0ADDMT67ZE (Bit 0)                                 */
+ #define R_POE3_POECR11_D0E0ADDMT67ZE_Msk    (0x1UL)    /*!< D0E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D1E0ADDMT67ZE_Pos    (1UL)      /*!< D1E0ADDMT67ZE (Bit 1)                                 */
+ #define R_POE3_POECR11_D1E0ADDMT67ZE_Msk    (0x2UL)    /*!< D1E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D2E0ADDMT67ZE_Pos    (2UL)      /*!< D2E0ADDMT67ZE (Bit 2)                                 */
+ #define R_POE3_POECR11_D2E0ADDMT67ZE_Msk    (0x4UL)    /*!< D2E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D3E0ADDMT67ZE_Pos    (3UL)      /*!< D3E0ADDMT67ZE (Bit 3)                                 */
+ #define R_POE3_POECR11_D3E0ADDMT67ZE_Msk    (0x8UL)    /*!< D3E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D4E0ADDMT67ZE_Pos    (4UL)      /*!< D4E0ADDMT67ZE (Bit 4)                                 */
+ #define R_POE3_POECR11_D4E0ADDMT67ZE_Msk    (0x10UL)   /*!< D4E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D5E0ADDMT67ZE_Pos    (5UL)      /*!< D5E0ADDMT67ZE (Bit 5)                                 */
+ #define R_POE3_POECR11_D5E0ADDMT67ZE_Msk    (0x20UL)   /*!< D5E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D6E0ADDMT67ZE_Pos    (6UL)      /*!< D6E0ADDMT67ZE (Bit 6)                                 */
+ #define R_POE3_POECR11_D6E0ADDMT67ZE_Msk    (0x40UL)   /*!< D6E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D7E0ADDMT67ZE_Pos    (7UL)      /*!< D7E0ADDMT67ZE (Bit 7)                                 */
+ #define R_POE3_POECR11_D7E0ADDMT67ZE_Msk    (0x80UL)   /*!< D7E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D8E0ADDMT67ZE_Pos    (8UL)      /*!< D8E0ADDMT67ZE (Bit 8)                                 */
+ #define R_POE3_POECR11_D8E0ADDMT67ZE_Msk    (0x100UL)  /*!< D8E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR11_D9E0ADDMT67ZE_Pos    (9UL)      /*!< D9E0ADDMT67ZE (Bit 9)                                 */
+ #define R_POE3_POECR11_D9E0ADDMT67ZE_Msk    (0x200UL)  /*!< D9E0ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+/* ========================================================  POECR12  ======================================================== */
+ #define R_POE3_POECR12_D0E1ADDMT67ZE_Pos    (0UL)      /*!< D0E1ADDMT67ZE (Bit 0)                                 */
+ #define R_POE3_POECR12_D0E1ADDMT67ZE_Msk    (0x1UL)    /*!< D0E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D1E1ADDMT67ZE_Pos    (1UL)      /*!< D1E1ADDMT67ZE (Bit 1)                                 */
+ #define R_POE3_POECR12_D1E1ADDMT67ZE_Msk    (0x2UL)    /*!< D1E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D2E1ADDMT67ZE_Pos    (2UL)      /*!< D2E1ADDMT67ZE (Bit 2)                                 */
+ #define R_POE3_POECR12_D2E1ADDMT67ZE_Msk    (0x4UL)    /*!< D2E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D3E1ADDMT67ZE_Pos    (3UL)      /*!< D3E1ADDMT67ZE (Bit 3)                                 */
+ #define R_POE3_POECR12_D3E1ADDMT67ZE_Msk    (0x8UL)    /*!< D3E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D4E1ADDMT67ZE_Pos    (4UL)      /*!< D4E1ADDMT67ZE (Bit 4)                                 */
+ #define R_POE3_POECR12_D4E1ADDMT67ZE_Msk    (0x10UL)   /*!< D4E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D5E1ADDMT67ZE_Pos    (5UL)      /*!< D5E1ADDMT67ZE (Bit 5)                                 */
+ #define R_POE3_POECR12_D5E1ADDMT67ZE_Msk    (0x20UL)   /*!< D5E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D6E1ADDMT67ZE_Pos    (6UL)      /*!< D6E1ADDMT67ZE (Bit 6)                                 */
+ #define R_POE3_POECR12_D6E1ADDMT67ZE_Msk    (0x40UL)   /*!< D6E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D7E1ADDMT67ZE_Pos    (7UL)      /*!< D7E1ADDMT67ZE (Bit 7)                                 */
+ #define R_POE3_POECR12_D7E1ADDMT67ZE_Msk    (0x80UL)   /*!< D7E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D8E1ADDMT67ZE_Pos    (8UL)      /*!< D8E1ADDMT67ZE (Bit 8)                                 */
+ #define R_POE3_POECR12_D8E1ADDMT67ZE_Msk    (0x100UL)  /*!< D8E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+ #define R_POE3_POECR12_D9E1ADDMT67ZE_Pos    (9UL)      /*!< D9E1ADDMT67ZE (Bit 9)                                 */
+ #define R_POE3_POECR12_D9E1ADDMT67ZE_Msk    (0x200UL)  /*!< D9E1ADDMT67ZE (Bitfield-Mask: 0x01)                   */
+
+/* =========================================================================================================================== */
+/* ================                                          R_POEG0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  POEG0GA0  ======================================================== */
+ #define R_POEG0_POEG0GA0_PIDF_Pos        (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG0_POEG0GA0_PIDF_Msk        (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA0_IOCF_Pos        (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG0_POEG0GA0_IOCF_Msk        (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA0_OSTPF_Pos       (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG0_POEG0GA0_OSTPF_Msk       (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GA0_SSF_Pos         (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG0_POEG0GA0_SSF_Msk         (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GA0_PIDE_Pos        (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG0_POEG0GA0_PIDE_Msk        (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA0_IOCE_Pos        (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG0_POEG0GA0_IOCE_Msk        (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA0_OSTPE_Pos       (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG0_POEG0GA0_OSTPE_Msk       (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GA0_ST_Pos          (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG0_POEG0GA0_ST_Msk          (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG0_POEG0GA0_INV_Pos         (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG0_POEG0GA0_INV_Msk         (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GA0_NFEN_Pos        (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG0_POEG0GA0_NFEN_Msk        (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GA0_NFCS_Pos        (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG0_POEG0GA0_NFCS_Msk        (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG0GA1  ======================================================== */
+ #define R_POEG0_POEG0GA1_D0ERR0ST_Pos    (0UL)          /*!< D0ERR0ST (Bit 0)                                      */
+ #define R_POEG0_POEG0GA1_D0ERR0ST_Msk    (0x1UL)        /*!< D0ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D1ERR0ST_Pos    (1UL)          /*!< D1ERR0ST (Bit 1)                                      */
+ #define R_POEG0_POEG0GA1_D1ERR0ST_Msk    (0x2UL)        /*!< D1ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D2ERR0ST_Pos    (2UL)          /*!< D2ERR0ST (Bit 2)                                      */
+ #define R_POEG0_POEG0GA1_D2ERR0ST_Msk    (0x4UL)        /*!< D2ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D3ERR0ST_Pos    (3UL)          /*!< D3ERR0ST (Bit 3)                                      */
+ #define R_POEG0_POEG0GA1_D3ERR0ST_Msk    (0x8UL)        /*!< D3ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D4ERR0ST_Pos    (4UL)          /*!< D4ERR0ST (Bit 4)                                      */
+ #define R_POEG0_POEG0GA1_D4ERR0ST_Msk    (0x10UL)       /*!< D4ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D5ERR0ST_Pos    (5UL)          /*!< D5ERR0ST (Bit 5)                                      */
+ #define R_POEG0_POEG0GA1_D5ERR0ST_Msk    (0x20UL)       /*!< D5ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D6ERR0ST_Pos    (6UL)          /*!< D6ERR0ST (Bit 6)                                      */
+ #define R_POEG0_POEG0GA1_D6ERR0ST_Msk    (0x40UL)       /*!< D6ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D7ERR0ST_Pos    (7UL)          /*!< D7ERR0ST (Bit 7)                                      */
+ #define R_POEG0_POEG0GA1_D7ERR0ST_Msk    (0x80UL)       /*!< D7ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D8ERR0ST_Pos    (8UL)          /*!< D8ERR0ST (Bit 8)                                      */
+ #define R_POEG0_POEG0GA1_D8ERR0ST_Msk    (0x100UL)      /*!< D8ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D9ERR0ST_Pos    (9UL)          /*!< D9ERR0ST (Bit 9)                                      */
+ #define R_POEG0_POEG0GA1_D9ERR0ST_Msk    (0x200UL)      /*!< D9ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D0ERR1ST_Pos    (16UL)         /*!< D0ERR1ST (Bit 16)                                     */
+ #define R_POEG0_POEG0GA1_D0ERR1ST_Msk    (0x10000UL)    /*!< D0ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D1ERR1ST_Pos    (17UL)         /*!< D1ERR1ST (Bit 17)                                     */
+ #define R_POEG0_POEG0GA1_D1ERR1ST_Msk    (0x20000UL)    /*!< D1ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D2ERR1ST_Pos    (18UL)         /*!< D2ERR1ST (Bit 18)                                     */
+ #define R_POEG0_POEG0GA1_D2ERR1ST_Msk    (0x40000UL)    /*!< D2ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D3ERR1ST_Pos    (19UL)         /*!< D3ERR1ST (Bit 19)                                     */
+ #define R_POEG0_POEG0GA1_D3ERR1ST_Msk    (0x80000UL)    /*!< D3ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D4ERR1ST_Pos    (20UL)         /*!< D4ERR1ST (Bit 20)                                     */
+ #define R_POEG0_POEG0GA1_D4ERR1ST_Msk    (0x100000UL)   /*!< D4ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D5ERR1ST_Pos    (21UL)         /*!< D5ERR1ST (Bit 21)                                     */
+ #define R_POEG0_POEG0GA1_D5ERR1ST_Msk    (0x200000UL)   /*!< D5ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D6ERR1ST_Pos    (22UL)         /*!< D6ERR1ST (Bit 22)                                     */
+ #define R_POEG0_POEG0GA1_D6ERR1ST_Msk    (0x400000UL)   /*!< D6ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D7ERR1ST_Pos    (23UL)         /*!< D7ERR1ST (Bit 23)                                     */
+ #define R_POEG0_POEG0GA1_D7ERR1ST_Msk    (0x800000UL)   /*!< D7ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D8ERR1ST_Pos    (24UL)         /*!< D8ERR1ST (Bit 24)                                     */
+ #define R_POEG0_POEG0GA1_D8ERR1ST_Msk    (0x1000000UL)  /*!< D8ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GA1_D9ERR1ST_Pos    (25UL)         /*!< D9ERR1ST (Bit 25)                                     */
+ #define R_POEG0_POEG0GA1_D9ERR1ST_Msk    (0x2000000UL)  /*!< D9ERR1ST (Bitfield-Mask: 0x01)                        */
+/* =======================================================  POEG0GA2  ======================================================== */
+ #define R_POEG0_POEG0GA2_D0ERR0E_Pos     (0UL)          /*!< D0ERR0E (Bit 0)                                       */
+ #define R_POEG0_POEG0GA2_D0ERR0E_Msk     (0x1UL)        /*!< D0ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D1ERR0E_Pos     (1UL)          /*!< D1ERR0E (Bit 1)                                       */
+ #define R_POEG0_POEG0GA2_D1ERR0E_Msk     (0x2UL)        /*!< D1ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D2ERR0E_Pos     (2UL)          /*!< D2ERR0E (Bit 2)                                       */
+ #define R_POEG0_POEG0GA2_D2ERR0E_Msk     (0x4UL)        /*!< D2ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D3ERR0E_Pos     (3UL)          /*!< D3ERR0E (Bit 3)                                       */
+ #define R_POEG0_POEG0GA2_D3ERR0E_Msk     (0x8UL)        /*!< D3ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D4ERR0E_Pos     (4UL)          /*!< D4ERR0E (Bit 4)                                       */
+ #define R_POEG0_POEG0GA2_D4ERR0E_Msk     (0x10UL)       /*!< D4ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D5ERR0E_Pos     (5UL)          /*!< D5ERR0E (Bit 5)                                       */
+ #define R_POEG0_POEG0GA2_D5ERR0E_Msk     (0x20UL)       /*!< D5ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D6ERR0E_Pos     (6UL)          /*!< D6ERR0E (Bit 6)                                       */
+ #define R_POEG0_POEG0GA2_D6ERR0E_Msk     (0x40UL)       /*!< D6ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D7ERR0E_Pos     (7UL)          /*!< D7ERR0E (Bit 7)                                       */
+ #define R_POEG0_POEG0GA2_D7ERR0E_Msk     (0x80UL)       /*!< D7ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D8ERR0E_Pos     (8UL)          /*!< D8ERR0E (Bit 8)                                       */
+ #define R_POEG0_POEG0GA2_D8ERR0E_Msk     (0x100UL)      /*!< D8ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D9ERR0E_Pos     (9UL)          /*!< D9ERR0E (Bit 9)                                       */
+ #define R_POEG0_POEG0GA2_D9ERR0E_Msk     (0x200UL)      /*!< D9ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D0ERR1E_Pos     (16UL)         /*!< D0ERR1E (Bit 16)                                      */
+ #define R_POEG0_POEG0GA2_D0ERR1E_Msk     (0x10000UL)    /*!< D0ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D1ERR1E_Pos     (17UL)         /*!< D1ERR1E (Bit 17)                                      */
+ #define R_POEG0_POEG0GA2_D1ERR1E_Msk     (0x20000UL)    /*!< D1ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D2ERR1E_Pos     (18UL)         /*!< D2ERR1E (Bit 18)                                      */
+ #define R_POEG0_POEG0GA2_D2ERR1E_Msk     (0x40000UL)    /*!< D2ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D3ERR1E_Pos     (19UL)         /*!< D3ERR1E (Bit 19)                                      */
+ #define R_POEG0_POEG0GA2_D3ERR1E_Msk     (0x80000UL)    /*!< D3ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D4ERR1E_Pos     (20UL)         /*!< D4ERR1E (Bit 20)                                      */
+ #define R_POEG0_POEG0GA2_D4ERR1E_Msk     (0x100000UL)   /*!< D4ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D5ERR1E_Pos     (21UL)         /*!< D5ERR1E (Bit 21)                                      */
+ #define R_POEG0_POEG0GA2_D5ERR1E_Msk     (0x200000UL)   /*!< D5ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D6ERR1E_Pos     (22UL)         /*!< D6ERR1E (Bit 22)                                      */
+ #define R_POEG0_POEG0GA2_D6ERR1E_Msk     (0x400000UL)   /*!< D6ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D7ERR1E_Pos     (23UL)         /*!< D7ERR1E (Bit 23)                                      */
+ #define R_POEG0_POEG0GA2_D7ERR1E_Msk     (0x800000UL)   /*!< D7ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D8ERR1E_Pos     (24UL)         /*!< D8ERR1E (Bit 24)                                      */
+ #define R_POEG0_POEG0GA2_D8ERR1E_Msk     (0x1000000UL)  /*!< D8ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GA2_D9ERR1E_Pos     (25UL)         /*!< D9ERR1E (Bit 25)                                      */
+ #define R_POEG0_POEG0GA2_D9ERR1E_Msk     (0x2000000UL)  /*!< D9ERR1E (Bitfield-Mask: 0x01)                         */
+/* =======================================================  POEG0GB0  ======================================================== */
+ #define R_POEG0_POEG0GB0_PIDF_Pos        (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG0_POEG0GB0_PIDF_Msk        (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB0_IOCF_Pos        (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG0_POEG0GB0_IOCF_Msk        (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB0_OSTPF_Pos       (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG0_POEG0GB0_OSTPF_Msk       (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GB0_SSF_Pos         (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG0_POEG0GB0_SSF_Msk         (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GB0_PIDE_Pos        (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG0_POEG0GB0_PIDE_Msk        (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB0_IOCE_Pos        (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG0_POEG0GB0_IOCE_Msk        (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB0_OSTPE_Pos       (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG0_POEG0GB0_OSTPE_Msk       (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GB0_ST_Pos          (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG0_POEG0GB0_ST_Msk          (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG0_POEG0GB0_INV_Pos         (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG0_POEG0GB0_INV_Msk         (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GB0_NFEN_Pos        (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG0_POEG0GB0_NFEN_Msk        (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GB0_NFCS_Pos        (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG0_POEG0GB0_NFCS_Msk        (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG0GB1  ======================================================== */
+ #define R_POEG0_POEG0GB1_D0ERR0ST_Pos    (0UL)          /*!< D0ERR0ST (Bit 0)                                      */
+ #define R_POEG0_POEG0GB1_D0ERR0ST_Msk    (0x1UL)        /*!< D0ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D1ERR0ST_Pos    (1UL)          /*!< D1ERR0ST (Bit 1)                                      */
+ #define R_POEG0_POEG0GB1_D1ERR0ST_Msk    (0x2UL)        /*!< D1ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D2ERR0ST_Pos    (2UL)          /*!< D2ERR0ST (Bit 2)                                      */
+ #define R_POEG0_POEG0GB1_D2ERR0ST_Msk    (0x4UL)        /*!< D2ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D3ERR0ST_Pos    (3UL)          /*!< D3ERR0ST (Bit 3)                                      */
+ #define R_POEG0_POEG0GB1_D3ERR0ST_Msk    (0x8UL)        /*!< D3ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D4ERR0ST_Pos    (4UL)          /*!< D4ERR0ST (Bit 4)                                      */
+ #define R_POEG0_POEG0GB1_D4ERR0ST_Msk    (0x10UL)       /*!< D4ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D5ERR0ST_Pos    (5UL)          /*!< D5ERR0ST (Bit 5)                                      */
+ #define R_POEG0_POEG0GB1_D5ERR0ST_Msk    (0x20UL)       /*!< D5ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D6ERR0ST_Pos    (6UL)          /*!< D6ERR0ST (Bit 6)                                      */
+ #define R_POEG0_POEG0GB1_D6ERR0ST_Msk    (0x40UL)       /*!< D6ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D7ERR0ST_Pos    (7UL)          /*!< D7ERR0ST (Bit 7)                                      */
+ #define R_POEG0_POEG0GB1_D7ERR0ST_Msk    (0x80UL)       /*!< D7ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D8ERR0ST_Pos    (8UL)          /*!< D8ERR0ST (Bit 8)                                      */
+ #define R_POEG0_POEG0GB1_D8ERR0ST_Msk    (0x100UL)      /*!< D8ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D9ERR0ST_Pos    (9UL)          /*!< D9ERR0ST (Bit 9)                                      */
+ #define R_POEG0_POEG0GB1_D9ERR0ST_Msk    (0x200UL)      /*!< D9ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D0ERR1ST_Pos    (16UL)         /*!< D0ERR1ST (Bit 16)                                     */
+ #define R_POEG0_POEG0GB1_D0ERR1ST_Msk    (0x10000UL)    /*!< D0ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D1ERR1ST_Pos    (17UL)         /*!< D1ERR1ST (Bit 17)                                     */
+ #define R_POEG0_POEG0GB1_D1ERR1ST_Msk    (0x20000UL)    /*!< D1ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D2ERR1ST_Pos    (18UL)         /*!< D2ERR1ST (Bit 18)                                     */
+ #define R_POEG0_POEG0GB1_D2ERR1ST_Msk    (0x40000UL)    /*!< D2ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D3ERR1ST_Pos    (19UL)         /*!< D3ERR1ST (Bit 19)                                     */
+ #define R_POEG0_POEG0GB1_D3ERR1ST_Msk    (0x80000UL)    /*!< D3ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D4ERR1ST_Pos    (20UL)         /*!< D4ERR1ST (Bit 20)                                     */
+ #define R_POEG0_POEG0GB1_D4ERR1ST_Msk    (0x100000UL)   /*!< D4ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D5ERR1ST_Pos    (21UL)         /*!< D5ERR1ST (Bit 21)                                     */
+ #define R_POEG0_POEG0GB1_D5ERR1ST_Msk    (0x200000UL)   /*!< D5ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D6ERR1ST_Pos    (22UL)         /*!< D6ERR1ST (Bit 22)                                     */
+ #define R_POEG0_POEG0GB1_D6ERR1ST_Msk    (0x400000UL)   /*!< D6ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D7ERR1ST_Pos    (23UL)         /*!< D7ERR1ST (Bit 23)                                     */
+ #define R_POEG0_POEG0GB1_D7ERR1ST_Msk    (0x800000UL)   /*!< D7ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D8ERR1ST_Pos    (24UL)         /*!< D8ERR1ST (Bit 24)                                     */
+ #define R_POEG0_POEG0GB1_D8ERR1ST_Msk    (0x1000000UL)  /*!< D8ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GB1_D9ERR1ST_Pos    (25UL)         /*!< D9ERR1ST (Bit 25)                                     */
+ #define R_POEG0_POEG0GB1_D9ERR1ST_Msk    (0x2000000UL)  /*!< D9ERR1ST (Bitfield-Mask: 0x01)                        */
+/* =======================================================  POEG0GB2  ======================================================== */
+ #define R_POEG0_POEG0GB2_D0ERR0E_Pos     (0UL)          /*!< D0ERR0E (Bit 0)                                       */
+ #define R_POEG0_POEG0GB2_D0ERR0E_Msk     (0x1UL)        /*!< D0ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D1ERR0E_Pos     (1UL)          /*!< D1ERR0E (Bit 1)                                       */
+ #define R_POEG0_POEG0GB2_D1ERR0E_Msk     (0x2UL)        /*!< D1ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D2ERR0E_Pos     (2UL)          /*!< D2ERR0E (Bit 2)                                       */
+ #define R_POEG0_POEG0GB2_D2ERR0E_Msk     (0x4UL)        /*!< D2ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D3ERR0E_Pos     (3UL)          /*!< D3ERR0E (Bit 3)                                       */
+ #define R_POEG0_POEG0GB2_D3ERR0E_Msk     (0x8UL)        /*!< D3ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D4ERR0E_Pos     (4UL)          /*!< D4ERR0E (Bit 4)                                       */
+ #define R_POEG0_POEG0GB2_D4ERR0E_Msk     (0x10UL)       /*!< D4ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D5ERR0E_Pos     (5UL)          /*!< D5ERR0E (Bit 5)                                       */
+ #define R_POEG0_POEG0GB2_D5ERR0E_Msk     (0x20UL)       /*!< D5ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D6ERR0E_Pos     (6UL)          /*!< D6ERR0E (Bit 6)                                       */
+ #define R_POEG0_POEG0GB2_D6ERR0E_Msk     (0x40UL)       /*!< D6ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D7ERR0E_Pos     (7UL)          /*!< D7ERR0E (Bit 7)                                       */
+ #define R_POEG0_POEG0GB2_D7ERR0E_Msk     (0x80UL)       /*!< D7ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D8ERR0E_Pos     (8UL)          /*!< D8ERR0E (Bit 8)                                       */
+ #define R_POEG0_POEG0GB2_D8ERR0E_Msk     (0x100UL)      /*!< D8ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D9ERR0E_Pos     (9UL)          /*!< D9ERR0E (Bit 9)                                       */
+ #define R_POEG0_POEG0GB2_D9ERR0E_Msk     (0x200UL)      /*!< D9ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D0ERR1E_Pos     (16UL)         /*!< D0ERR1E (Bit 16)                                      */
+ #define R_POEG0_POEG0GB2_D0ERR1E_Msk     (0x10000UL)    /*!< D0ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D1ERR1E_Pos     (17UL)         /*!< D1ERR1E (Bit 17)                                      */
+ #define R_POEG0_POEG0GB2_D1ERR1E_Msk     (0x20000UL)    /*!< D1ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D2ERR1E_Pos     (18UL)         /*!< D2ERR1E (Bit 18)                                      */
+ #define R_POEG0_POEG0GB2_D2ERR1E_Msk     (0x40000UL)    /*!< D2ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D3ERR1E_Pos     (19UL)         /*!< D3ERR1E (Bit 19)                                      */
+ #define R_POEG0_POEG0GB2_D3ERR1E_Msk     (0x80000UL)    /*!< D3ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D4ERR1E_Pos     (20UL)         /*!< D4ERR1E (Bit 20)                                      */
+ #define R_POEG0_POEG0GB2_D4ERR1E_Msk     (0x100000UL)   /*!< D4ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D5ERR1E_Pos     (21UL)         /*!< D5ERR1E (Bit 21)                                      */
+ #define R_POEG0_POEG0GB2_D5ERR1E_Msk     (0x200000UL)   /*!< D5ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D6ERR1E_Pos     (22UL)         /*!< D6ERR1E (Bit 22)                                      */
+ #define R_POEG0_POEG0GB2_D6ERR1E_Msk     (0x400000UL)   /*!< D6ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D7ERR1E_Pos     (23UL)         /*!< D7ERR1E (Bit 23)                                      */
+ #define R_POEG0_POEG0GB2_D7ERR1E_Msk     (0x800000UL)   /*!< D7ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D8ERR1E_Pos     (24UL)         /*!< D8ERR1E (Bit 24)                                      */
+ #define R_POEG0_POEG0GB2_D8ERR1E_Msk     (0x1000000UL)  /*!< D8ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GB2_D9ERR1E_Pos     (25UL)         /*!< D9ERR1E (Bit 25)                                      */
+ #define R_POEG0_POEG0GB2_D9ERR1E_Msk     (0x2000000UL)  /*!< D9ERR1E (Bitfield-Mask: 0x01)                         */
+/* =======================================================  POEG0GC0  ======================================================== */
+ #define R_POEG0_POEG0GC0_PIDF_Pos        (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG0_POEG0GC0_PIDF_Msk        (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC0_IOCF_Pos        (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG0_POEG0GC0_IOCF_Msk        (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC0_OSTPF_Pos       (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG0_POEG0GC0_OSTPF_Msk       (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GC0_SSF_Pos         (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG0_POEG0GC0_SSF_Msk         (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GC0_PIDE_Pos        (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG0_POEG0GC0_PIDE_Msk        (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC0_IOCE_Pos        (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG0_POEG0GC0_IOCE_Msk        (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC0_OSTPE_Pos       (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG0_POEG0GC0_OSTPE_Msk       (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GC0_ST_Pos          (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG0_POEG0GC0_ST_Msk          (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG0_POEG0GC0_INV_Pos         (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG0_POEG0GC0_INV_Msk         (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GC0_NFEN_Pos        (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG0_POEG0GC0_NFEN_Msk        (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GC0_NFCS_Pos        (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG0_POEG0GC0_NFCS_Msk        (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG0GC1  ======================================================== */
+ #define R_POEG0_POEG0GC1_D0ERR0ST_Pos    (0UL)          /*!< D0ERR0ST (Bit 0)                                      */
+ #define R_POEG0_POEG0GC1_D0ERR0ST_Msk    (0x1UL)        /*!< D0ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D1ERR0ST_Pos    (1UL)          /*!< D1ERR0ST (Bit 1)                                      */
+ #define R_POEG0_POEG0GC1_D1ERR0ST_Msk    (0x2UL)        /*!< D1ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D2ERR0ST_Pos    (2UL)          /*!< D2ERR0ST (Bit 2)                                      */
+ #define R_POEG0_POEG0GC1_D2ERR0ST_Msk    (0x4UL)        /*!< D2ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D3ERR0ST_Pos    (3UL)          /*!< D3ERR0ST (Bit 3)                                      */
+ #define R_POEG0_POEG0GC1_D3ERR0ST_Msk    (0x8UL)        /*!< D3ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D4ERR0ST_Pos    (4UL)          /*!< D4ERR0ST (Bit 4)                                      */
+ #define R_POEG0_POEG0GC1_D4ERR0ST_Msk    (0x10UL)       /*!< D4ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D5ERR0ST_Pos    (5UL)          /*!< D5ERR0ST (Bit 5)                                      */
+ #define R_POEG0_POEG0GC1_D5ERR0ST_Msk    (0x20UL)       /*!< D5ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D6ERR0ST_Pos    (6UL)          /*!< D6ERR0ST (Bit 6)                                      */
+ #define R_POEG0_POEG0GC1_D6ERR0ST_Msk    (0x40UL)       /*!< D6ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D7ERR0ST_Pos    (7UL)          /*!< D7ERR0ST (Bit 7)                                      */
+ #define R_POEG0_POEG0GC1_D7ERR0ST_Msk    (0x80UL)       /*!< D7ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D8ERR0ST_Pos    (8UL)          /*!< D8ERR0ST (Bit 8)                                      */
+ #define R_POEG0_POEG0GC1_D8ERR0ST_Msk    (0x100UL)      /*!< D8ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D9ERR0ST_Pos    (9UL)          /*!< D9ERR0ST (Bit 9)                                      */
+ #define R_POEG0_POEG0GC1_D9ERR0ST_Msk    (0x200UL)      /*!< D9ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D0ERR1ST_Pos    (16UL)         /*!< D0ERR1ST (Bit 16)                                     */
+ #define R_POEG0_POEG0GC1_D0ERR1ST_Msk    (0x10000UL)    /*!< D0ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D1ERR1ST_Pos    (17UL)         /*!< D1ERR1ST (Bit 17)                                     */
+ #define R_POEG0_POEG0GC1_D1ERR1ST_Msk    (0x20000UL)    /*!< D1ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D2ERR1ST_Pos    (18UL)         /*!< D2ERR1ST (Bit 18)                                     */
+ #define R_POEG0_POEG0GC1_D2ERR1ST_Msk    (0x40000UL)    /*!< D2ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D3ERR1ST_Pos    (19UL)         /*!< D3ERR1ST (Bit 19)                                     */
+ #define R_POEG0_POEG0GC1_D3ERR1ST_Msk    (0x80000UL)    /*!< D3ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D4ERR1ST_Pos    (20UL)         /*!< D4ERR1ST (Bit 20)                                     */
+ #define R_POEG0_POEG0GC1_D4ERR1ST_Msk    (0x100000UL)   /*!< D4ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D5ERR1ST_Pos    (21UL)         /*!< D5ERR1ST (Bit 21)                                     */
+ #define R_POEG0_POEG0GC1_D5ERR1ST_Msk    (0x200000UL)   /*!< D5ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D6ERR1ST_Pos    (22UL)         /*!< D6ERR1ST (Bit 22)                                     */
+ #define R_POEG0_POEG0GC1_D6ERR1ST_Msk    (0x400000UL)   /*!< D6ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D7ERR1ST_Pos    (23UL)         /*!< D7ERR1ST (Bit 23)                                     */
+ #define R_POEG0_POEG0GC1_D7ERR1ST_Msk    (0x800000UL)   /*!< D7ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D8ERR1ST_Pos    (24UL)         /*!< D8ERR1ST (Bit 24)                                     */
+ #define R_POEG0_POEG0GC1_D8ERR1ST_Msk    (0x1000000UL)  /*!< D8ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GC1_D9ERR1ST_Pos    (25UL)         /*!< D9ERR1ST (Bit 25)                                     */
+ #define R_POEG0_POEG0GC1_D9ERR1ST_Msk    (0x2000000UL)  /*!< D9ERR1ST (Bitfield-Mask: 0x01)                        */
+/* =======================================================  POEG0GC2  ======================================================== */
+ #define R_POEG0_POEG0GC2_D0ERR0E_Pos     (0UL)          /*!< D0ERR0E (Bit 0)                                       */
+ #define R_POEG0_POEG0GC2_D0ERR0E_Msk     (0x1UL)        /*!< D0ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D1ERR0E_Pos     (1UL)          /*!< D1ERR0E (Bit 1)                                       */
+ #define R_POEG0_POEG0GC2_D1ERR0E_Msk     (0x2UL)        /*!< D1ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D2ERR0E_Pos     (2UL)          /*!< D2ERR0E (Bit 2)                                       */
+ #define R_POEG0_POEG0GC2_D2ERR0E_Msk     (0x4UL)        /*!< D2ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D3ERR0E_Pos     (3UL)          /*!< D3ERR0E (Bit 3)                                       */
+ #define R_POEG0_POEG0GC2_D3ERR0E_Msk     (0x8UL)        /*!< D3ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D4ERR0E_Pos     (4UL)          /*!< D4ERR0E (Bit 4)                                       */
+ #define R_POEG0_POEG0GC2_D4ERR0E_Msk     (0x10UL)       /*!< D4ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D5ERR0E_Pos     (5UL)          /*!< D5ERR0E (Bit 5)                                       */
+ #define R_POEG0_POEG0GC2_D5ERR0E_Msk     (0x20UL)       /*!< D5ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D6ERR0E_Pos     (6UL)          /*!< D6ERR0E (Bit 6)                                       */
+ #define R_POEG0_POEG0GC2_D6ERR0E_Msk     (0x40UL)       /*!< D6ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D7ERR0E_Pos     (7UL)          /*!< D7ERR0E (Bit 7)                                       */
+ #define R_POEG0_POEG0GC2_D7ERR0E_Msk     (0x80UL)       /*!< D7ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D8ERR0E_Pos     (8UL)          /*!< D8ERR0E (Bit 8)                                       */
+ #define R_POEG0_POEG0GC2_D8ERR0E_Msk     (0x100UL)      /*!< D8ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D9ERR0E_Pos     (9UL)          /*!< D9ERR0E (Bit 9)                                       */
+ #define R_POEG0_POEG0GC2_D9ERR0E_Msk     (0x200UL)      /*!< D9ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D0ERR1E_Pos     (16UL)         /*!< D0ERR1E (Bit 16)                                      */
+ #define R_POEG0_POEG0GC2_D0ERR1E_Msk     (0x10000UL)    /*!< D0ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D1ERR1E_Pos     (17UL)         /*!< D1ERR1E (Bit 17)                                      */
+ #define R_POEG0_POEG0GC2_D1ERR1E_Msk     (0x20000UL)    /*!< D1ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D2ERR1E_Pos     (18UL)         /*!< D2ERR1E (Bit 18)                                      */
+ #define R_POEG0_POEG0GC2_D2ERR1E_Msk     (0x40000UL)    /*!< D2ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D3ERR1E_Pos     (19UL)         /*!< D3ERR1E (Bit 19)                                      */
+ #define R_POEG0_POEG0GC2_D3ERR1E_Msk     (0x80000UL)    /*!< D3ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D4ERR1E_Pos     (20UL)         /*!< D4ERR1E (Bit 20)                                      */
+ #define R_POEG0_POEG0GC2_D4ERR1E_Msk     (0x100000UL)   /*!< D4ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D5ERR1E_Pos     (21UL)         /*!< D5ERR1E (Bit 21)                                      */
+ #define R_POEG0_POEG0GC2_D5ERR1E_Msk     (0x200000UL)   /*!< D5ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D6ERR1E_Pos     (22UL)         /*!< D6ERR1E (Bit 22)                                      */
+ #define R_POEG0_POEG0GC2_D6ERR1E_Msk     (0x400000UL)   /*!< D6ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D7ERR1E_Pos     (23UL)         /*!< D7ERR1E (Bit 23)                                      */
+ #define R_POEG0_POEG0GC2_D7ERR1E_Msk     (0x800000UL)   /*!< D7ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D8ERR1E_Pos     (24UL)         /*!< D8ERR1E (Bit 24)                                      */
+ #define R_POEG0_POEG0GC2_D8ERR1E_Msk     (0x1000000UL)  /*!< D8ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GC2_D9ERR1E_Pos     (25UL)         /*!< D9ERR1E (Bit 25)                                      */
+ #define R_POEG0_POEG0GC2_D9ERR1E_Msk     (0x2000000UL)  /*!< D9ERR1E (Bitfield-Mask: 0x01)                         */
+/* =======================================================  POEG0GD0  ======================================================== */
+ #define R_POEG0_POEG0GD0_PIDF_Pos        (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_POEG0_POEG0GD0_PIDF_Msk        (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD0_IOCF_Pos        (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_POEG0_POEG0GD0_IOCF_Msk        (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD0_OSTPF_Pos       (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_POEG0_POEG0GD0_OSTPF_Msk       (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GD0_SSF_Pos         (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_POEG0_POEG0GD0_SSF_Msk         (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GD0_PIDE_Pos        (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_POEG0_POEG0GD0_PIDE_Msk        (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD0_IOCE_Pos        (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_POEG0_POEG0GD0_IOCE_Msk        (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD0_OSTPE_Pos       (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_POEG0_POEG0GD0_OSTPE_Msk       (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_POEG0_POEG0GD0_ST_Pos          (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_POEG0_POEG0GD0_ST_Msk          (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_POEG0_POEG0GD0_INV_Pos         (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_POEG0_POEG0GD0_INV_Msk         (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_POEG0_POEG0GD0_NFEN_Pos        (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_POEG0_POEG0GD0_NFEN_Msk        (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_POEG0_POEG0GD0_NFCS_Pos        (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_POEG0_POEG0GD0_NFCS_Msk        (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+/* =======================================================  POEG0GD1  ======================================================== */
+ #define R_POEG0_POEG0GD1_D0ERR0ST_Pos    (0UL)          /*!< D0ERR0ST (Bit 0)                                      */
+ #define R_POEG0_POEG0GD1_D0ERR0ST_Msk    (0x1UL)        /*!< D0ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D1ERR0ST_Pos    (1UL)          /*!< D1ERR0ST (Bit 1)                                      */
+ #define R_POEG0_POEG0GD1_D1ERR0ST_Msk    (0x2UL)        /*!< D1ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D2ERR0ST_Pos    (2UL)          /*!< D2ERR0ST (Bit 2)                                      */
+ #define R_POEG0_POEG0GD1_D2ERR0ST_Msk    (0x4UL)        /*!< D2ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D3ERR0ST_Pos    (3UL)          /*!< D3ERR0ST (Bit 3)                                      */
+ #define R_POEG0_POEG0GD1_D3ERR0ST_Msk    (0x8UL)        /*!< D3ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D4ERR0ST_Pos    (4UL)          /*!< D4ERR0ST (Bit 4)                                      */
+ #define R_POEG0_POEG0GD1_D4ERR0ST_Msk    (0x10UL)       /*!< D4ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D5ERR0ST_Pos    (5UL)          /*!< D5ERR0ST (Bit 5)                                      */
+ #define R_POEG0_POEG0GD1_D5ERR0ST_Msk    (0x20UL)       /*!< D5ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D6ERR0ST_Pos    (6UL)          /*!< D6ERR0ST (Bit 6)                                      */
+ #define R_POEG0_POEG0GD1_D6ERR0ST_Msk    (0x40UL)       /*!< D6ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D7ERR0ST_Pos    (7UL)          /*!< D7ERR0ST (Bit 7)                                      */
+ #define R_POEG0_POEG0GD1_D7ERR0ST_Msk    (0x80UL)       /*!< D7ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D8ERR0ST_Pos    (8UL)          /*!< D8ERR0ST (Bit 8)                                      */
+ #define R_POEG0_POEG0GD1_D8ERR0ST_Msk    (0x100UL)      /*!< D8ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D9ERR0ST_Pos    (9UL)          /*!< D9ERR0ST (Bit 9)                                      */
+ #define R_POEG0_POEG0GD1_D9ERR0ST_Msk    (0x200UL)      /*!< D9ERR0ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D0ERR1ST_Pos    (16UL)         /*!< D0ERR1ST (Bit 16)                                     */
+ #define R_POEG0_POEG0GD1_D0ERR1ST_Msk    (0x10000UL)    /*!< D0ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D1ERR1ST_Pos    (17UL)         /*!< D1ERR1ST (Bit 17)                                     */
+ #define R_POEG0_POEG0GD1_D1ERR1ST_Msk    (0x20000UL)    /*!< D1ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D2ERR1ST_Pos    (18UL)         /*!< D2ERR1ST (Bit 18)                                     */
+ #define R_POEG0_POEG0GD1_D2ERR1ST_Msk    (0x40000UL)    /*!< D2ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D3ERR1ST_Pos    (19UL)         /*!< D3ERR1ST (Bit 19)                                     */
+ #define R_POEG0_POEG0GD1_D3ERR1ST_Msk    (0x80000UL)    /*!< D3ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D4ERR1ST_Pos    (20UL)         /*!< D4ERR1ST (Bit 20)                                     */
+ #define R_POEG0_POEG0GD1_D4ERR1ST_Msk    (0x100000UL)   /*!< D4ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D5ERR1ST_Pos    (21UL)         /*!< D5ERR1ST (Bit 21)                                     */
+ #define R_POEG0_POEG0GD1_D5ERR1ST_Msk    (0x200000UL)   /*!< D5ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D6ERR1ST_Pos    (22UL)         /*!< D6ERR1ST (Bit 22)                                     */
+ #define R_POEG0_POEG0GD1_D6ERR1ST_Msk    (0x400000UL)   /*!< D6ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D7ERR1ST_Pos    (23UL)         /*!< D7ERR1ST (Bit 23)                                     */
+ #define R_POEG0_POEG0GD1_D7ERR1ST_Msk    (0x800000UL)   /*!< D7ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D8ERR1ST_Pos    (24UL)         /*!< D8ERR1ST (Bit 24)                                     */
+ #define R_POEG0_POEG0GD1_D8ERR1ST_Msk    (0x1000000UL)  /*!< D8ERR1ST (Bitfield-Mask: 0x01)                        */
+ #define R_POEG0_POEG0GD1_D9ERR1ST_Pos    (25UL)         /*!< D9ERR1ST (Bit 25)                                     */
+ #define R_POEG0_POEG0GD1_D9ERR1ST_Msk    (0x2000000UL)  /*!< D9ERR1ST (Bitfield-Mask: 0x01)                        */
+/* =======================================================  POEG0GD2  ======================================================== */
+ #define R_POEG0_POEG0GD2_D0ERR0E_Pos     (0UL)          /*!< D0ERR0E (Bit 0)                                       */
+ #define R_POEG0_POEG0GD2_D0ERR0E_Msk     (0x1UL)        /*!< D0ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D1ERR0E_Pos     (1UL)          /*!< D1ERR0E (Bit 1)                                       */
+ #define R_POEG0_POEG0GD2_D1ERR0E_Msk     (0x2UL)        /*!< D1ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D2ERR0E_Pos     (2UL)          /*!< D2ERR0E (Bit 2)                                       */
+ #define R_POEG0_POEG0GD2_D2ERR0E_Msk     (0x4UL)        /*!< D2ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D3ERR0E_Pos     (3UL)          /*!< D3ERR0E (Bit 3)                                       */
+ #define R_POEG0_POEG0GD2_D3ERR0E_Msk     (0x8UL)        /*!< D3ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D4ERR0E_Pos     (4UL)          /*!< D4ERR0E (Bit 4)                                       */
+ #define R_POEG0_POEG0GD2_D4ERR0E_Msk     (0x10UL)       /*!< D4ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D5ERR0E_Pos     (5UL)          /*!< D5ERR0E (Bit 5)                                       */
+ #define R_POEG0_POEG0GD2_D5ERR0E_Msk     (0x20UL)       /*!< D5ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D6ERR0E_Pos     (6UL)          /*!< D6ERR0E (Bit 6)                                       */
+ #define R_POEG0_POEG0GD2_D6ERR0E_Msk     (0x40UL)       /*!< D6ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D7ERR0E_Pos     (7UL)          /*!< D7ERR0E (Bit 7)                                       */
+ #define R_POEG0_POEG0GD2_D7ERR0E_Msk     (0x80UL)       /*!< D7ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D8ERR0E_Pos     (8UL)          /*!< D8ERR0E (Bit 8)                                       */
+ #define R_POEG0_POEG0GD2_D8ERR0E_Msk     (0x100UL)      /*!< D8ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D9ERR0E_Pos     (9UL)          /*!< D9ERR0E (Bit 9)                                       */
+ #define R_POEG0_POEG0GD2_D9ERR0E_Msk     (0x200UL)      /*!< D9ERR0E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D0ERR1E_Pos     (16UL)         /*!< D0ERR1E (Bit 16)                                      */
+ #define R_POEG0_POEG0GD2_D0ERR1E_Msk     (0x10000UL)    /*!< D0ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D1ERR1E_Pos     (17UL)         /*!< D1ERR1E (Bit 17)                                      */
+ #define R_POEG0_POEG0GD2_D1ERR1E_Msk     (0x20000UL)    /*!< D1ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D2ERR1E_Pos     (18UL)         /*!< D2ERR1E (Bit 18)                                      */
+ #define R_POEG0_POEG0GD2_D2ERR1E_Msk     (0x40000UL)    /*!< D2ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D3ERR1E_Pos     (19UL)         /*!< D3ERR1E (Bit 19)                                      */
+ #define R_POEG0_POEG0GD2_D3ERR1E_Msk     (0x80000UL)    /*!< D3ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D4ERR1E_Pos     (20UL)         /*!< D4ERR1E (Bit 20)                                      */
+ #define R_POEG0_POEG0GD2_D4ERR1E_Msk     (0x100000UL)   /*!< D4ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D5ERR1E_Pos     (21UL)         /*!< D5ERR1E (Bit 21)                                      */
+ #define R_POEG0_POEG0GD2_D5ERR1E_Msk     (0x200000UL)   /*!< D5ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D6ERR1E_Pos     (22UL)         /*!< D6ERR1E (Bit 22)                                      */
+ #define R_POEG0_POEG0GD2_D6ERR1E_Msk     (0x400000UL)   /*!< D6ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D7ERR1E_Pos     (23UL)         /*!< D7ERR1E (Bit 23)                                      */
+ #define R_POEG0_POEG0GD2_D7ERR1E_Msk     (0x800000UL)   /*!< D7ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D8ERR1E_Pos     (24UL)         /*!< D8ERR1E (Bit 24)                                      */
+ #define R_POEG0_POEG0GD2_D8ERR1E_Msk     (0x1000000UL)  /*!< D8ERR1E (Bitfield-Mask: 0x01)                         */
+ #define R_POEG0_POEG0GD2_D9ERR1E_Pos     (25UL)         /*!< D9ERR1E (Bit 25)                                      */
+ #define R_POEG0_POEG0GD2_D9ERR1E_Msk     (0x2000000UL)  /*!< D9ERR1E (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_DSMIF0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  DSCCSCR  ======================================================== */
+ #define R_DSMIF0_DSCCSCR_CLKSEL_Pos         (0UL)        /*!< CLKSEL (Bit 0)                                        */
+ #define R_DSMIF0_DSCCSCR_CLKSEL_Msk         (0x1UL)      /*!< CLKSEL (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DSSEICR  ======================================================== */
+ #define R_DSMIF0_DSSEICR_ISEL_Pos           (0UL)        /*!< ISEL (Bit 0)                                          */
+ #define R_DSMIF0_DSSEICR_ISEL_Msk           (0x1UL)      /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSSEICR_ISEH_Pos           (1UL)        /*!< ISEH (Bit 1)                                          */
+ #define R_DSMIF0_DSSEICR_ISEH_Msk           (0x2UL)      /*!< ISEH (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DSSECSR  ======================================================== */
+ #define R_DSMIF0_DSSECSR_SEDM_Pos           (0UL)        /*!< SEDM (Bit 0)                                          */
+ #define R_DSMIF0_DSSECSR_SEDM_Msk           (0x7UL)      /*!< SEDM (Bitfield-Mask: 0x07)                            */
+/* ========================================================  DSSELTR  ======================================================== */
+ #define R_DSMIF0_DSSELTR_SCMPTBL_Pos        (0UL)        /*!< SCMPTBL (Bit 0)                                       */
+ #define R_DSMIF0_DSSELTR_SCMPTBL_Msk        (0x3ffffUL)  /*!< SCMPTBL (Bitfield-Mask: 0x3ffff)                      */
+/* ========================================================  DSSEHTR  ======================================================== */
+ #define R_DSMIF0_DSSEHTR_SCMPTBH_Pos        (0UL)        /*!< SCMPTBH (Bit 0)                                       */
+ #define R_DSMIF0_DSSEHTR_SCMPTBH_Msk        (0x3ffffUL)  /*!< SCMPTBH (Bitfield-Mask: 0x3ffff)                      */
+/* ========================================================  DSSECR  ========================================================= */
+ #define R_DSMIF0_DSSECR_SEEL_Pos            (0UL)        /*!< SEEL (Bit 0)                                          */
+ #define R_DSMIF0_DSSECR_SEEL_Msk            (0x1UL)      /*!< SEEL (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSSECR_SEEH_Pos            (1UL)        /*!< SEEH (Bit 1)                                          */
+ #define R_DSMIF0_DSSECR_SEEH_Msk            (0x2UL)      /*!< SEEH (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DSSECDR  ======================================================== */
+ #define R_DSMIF0_DSSECDR_SECDR_Pos          (0UL)        /*!< SECDR (Bit 0)                                         */
+ #define R_DSMIF0_DSSECDR_SECDR_Msk          (0xffffUL)   /*!< SECDR (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  DSCMSR  ========================================================= */
+ #define R_DSMIF0_DSCMSR_DFS_Pos             (0UL)        /*!< DFS (Bit 0)                                           */
+ #define R_DSMIF0_DSCMSR_DFS_Msk             (0x1UL)      /*!< DFS (Bitfield-Mask: 0x01)                             */
+ #define R_DSMIF0_DSCMSR_CISM_Pos            (1UL)        /*!< CISM (Bit 1)                                          */
+ #define R_DSMIF0_DSCMSR_CISM_Msk            (0x6UL)      /*!< CISM (Bitfield-Mask: 0x03)                            */
+/* ========================================================  DSCICR  ========================================================= */
+ #define R_DSMIF0_DSCICR_IUCE_Pos            (0UL)        /*!< IUCE (Bit 0)                                          */
+ #define R_DSMIF0_DSCICR_IUCE_Msk            (0x1UL)      /*!< IUCE (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCICR_IAUCE_Pos           (1UL)        /*!< IAUCE (Bit 1)                                         */
+ #define R_DSMIF0_DSCICR_IAUCE_Msk           (0x2UL)      /*!< IAUCE (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCICR_IBUCE_Pos           (2UL)        /*!< IBUCE (Bit 2)                                         */
+ #define R_DSMIF0_DSCICR_IBUCE_Msk           (0x4UL)      /*!< IBUCE (Bitfield-Mask: 0x01)                           */
+/* =======================================================  DSCSTRTR  ======================================================== */
+ #define R_DSMIF0_DSCSTRTR_STRTRG0_Pos       (0UL)        /*!< STRTRG0 (Bit 0)                                       */
+ #define R_DSMIF0_DSCSTRTR_STRTRG0_Msk       (0x1UL)      /*!< STRTRG0 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSTRTR_STRTRG1_Pos       (1UL)        /*!< STRTRG1 (Bit 1)                                       */
+ #define R_DSMIF0_DSCSTRTR_STRTRG1_Msk       (0x2UL)      /*!< STRTRG1 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSTRTR_STRTRG2_Pos       (2UL)        /*!< STRTRG2 (Bit 2)                                       */
+ #define R_DSMIF0_DSCSTRTR_STRTRG2_Msk       (0x4UL)      /*!< STRTRG2 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DSCSTPTR  ======================================================== */
+ #define R_DSMIF0_DSCSTPTR_STPTRG0_Pos       (0UL)        /*!< STPTRG0 (Bit 0)                                       */
+ #define R_DSMIF0_DSCSTPTR_STPTRG0_Msk       (0x1UL)      /*!< STPTRG0 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSTPTR_STPTRG1_Pos       (1UL)        /*!< STPTRG1 (Bit 1)                                       */
+ #define R_DSMIF0_DSCSTPTR_STPTRG1_Msk       (0x2UL)      /*!< STPTRG1 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSTPTR_STPTRG2_Pos       (2UL)        /*!< STPTRG2 (Bit 2)                                       */
+ #define R_DSMIF0_DSCSTPTR_STPTRG2_Msk       (0x4UL)      /*!< STPTRG2 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DSCESR  ========================================================= */
+ #define R_DSMIF0_DSCESR_SCF0_Pos            (0UL)        /*!< SCF0 (Bit 0)                                          */
+ #define R_DSMIF0_DSCESR_SCF0_Msk            (0x1UL)      /*!< SCF0 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCESR_SCF1_Pos            (1UL)        /*!< SCF1 (Bit 1)                                          */
+ #define R_DSMIF0_DSCESR_SCF1_Msk            (0x2UL)      /*!< SCF1 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCESR_SCF2_Pos            (2UL)        /*!< SCF2 (Bit 2)                                          */
+ #define R_DSMIF0_DSCESR_SCF2_Msk            (0x4UL)      /*!< SCF2 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCESR_SUMERRL_Pos         (16UL)       /*!< SUMERRL (Bit 16)                                      */
+ #define R_DSMIF0_DSCESR_SUMERRL_Msk         (0x10000UL)  /*!< SUMERRL (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCESR_SUMERRH_Pos         (17UL)       /*!< SUMERRH (Bit 17)                                      */
+ #define R_DSMIF0_DSCESR_SUMERRH_Msk         (0x20000UL)  /*!< SUMERRH (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DSCOCESR  ======================================================== */
+ #define R_DSMIF0_DSCOCESR_OC0FL0_Pos        (0UL)        /*!< OC0FL0 (Bit 0)                                        */
+ #define R_DSMIF0_DSCOCESR_OC0FL0_Msk        (0x1UL)      /*!< OC0FL0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC0FL1_Pos        (1UL)        /*!< OC0FL1 (Bit 1)                                        */
+ #define R_DSMIF0_DSCOCESR_OC0FL1_Msk        (0x2UL)      /*!< OC0FL1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC0FL2_Pos        (2UL)        /*!< OC0FL2 (Bit 2)                                        */
+ #define R_DSMIF0_DSCOCESR_OC0FL2_Msk        (0x4UL)      /*!< OC0FL2 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC0FH0_Pos        (4UL)        /*!< OC0FH0 (Bit 4)                                        */
+ #define R_DSMIF0_DSCOCESR_OC0FH0_Msk        (0x10UL)     /*!< OC0FH0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC0FH1_Pos        (5UL)        /*!< OC0FH1 (Bit 5)                                        */
+ #define R_DSMIF0_DSCOCESR_OC0FH1_Msk        (0x20UL)     /*!< OC0FH1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC0FH2_Pos        (6UL)        /*!< OC0FH2 (Bit 6)                                        */
+ #define R_DSMIF0_DSCOCESR_OC0FH2_Msk        (0x40UL)     /*!< OC0FH2 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC1FL0_Pos        (8UL)        /*!< OC1FL0 (Bit 8)                                        */
+ #define R_DSMIF0_DSCOCESR_OC1FL0_Msk        (0x100UL)    /*!< OC1FL0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC1FL1_Pos        (9UL)        /*!< OC1FL1 (Bit 9)                                        */
+ #define R_DSMIF0_DSCOCESR_OC1FL1_Msk        (0x200UL)    /*!< OC1FL1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC1FL2_Pos        (10UL)       /*!< OC1FL2 (Bit 10)                                       */
+ #define R_DSMIF0_DSCOCESR_OC1FL2_Msk        (0x400UL)    /*!< OC1FL2 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC1FH0_Pos        (12UL)       /*!< OC1FH0 (Bit 12)                                       */
+ #define R_DSMIF0_DSCOCESR_OC1FH0_Msk        (0x1000UL)   /*!< OC1FH0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC1FH1_Pos        (13UL)       /*!< OC1FH1 (Bit 13)                                       */
+ #define R_DSMIF0_DSCOCESR_OC1FH1_Msk        (0x2000UL)   /*!< OC1FH1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC1FH2_Pos        (14UL)       /*!< OC1FH2 (Bit 14)                                       */
+ #define R_DSMIF0_DSCOCESR_OC1FH2_Msk        (0x4000UL)   /*!< OC1FH2 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC2FL0_Pos        (16UL)       /*!< OC2FL0 (Bit 16)                                       */
+ #define R_DSMIF0_DSCOCESR_OC2FL0_Msk        (0x10000UL)  /*!< OC2FL0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC2FL1_Pos        (17UL)       /*!< OC2FL1 (Bit 17)                                       */
+ #define R_DSMIF0_DSCOCESR_OC2FL1_Msk        (0x20000UL)  /*!< OC2FL1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC2FL2_Pos        (18UL)       /*!< OC2FL2 (Bit 18)                                       */
+ #define R_DSMIF0_DSCOCESR_OC2FL2_Msk        (0x40000UL)  /*!< OC2FL2 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC2FH0_Pos        (20UL)       /*!< OC2FH0 (Bit 20)                                       */
+ #define R_DSMIF0_DSCOCESR_OC2FH0_Msk        (0x100000UL) /*!< OC2FH0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC2FH1_Pos        (21UL)       /*!< OC2FH1 (Bit 21)                                       */
+ #define R_DSMIF0_DSCOCESR_OC2FH1_Msk        (0x200000UL) /*!< OC2FH1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCESR_OC2FH2_Pos        (22UL)       /*!< OC2FH2 (Bit 22)                                       */
+ #define R_DSMIF0_DSCOCESR_OC2FH2_Msk        (0x400000UL) /*!< OC2FH2 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DSCOCNSR  ======================================================== */
+ #define R_DSMIF0_DSCOCNSR_OWD0N0_Pos        (0UL)        /*!< OWD0N0 (Bit 0)                                        */
+ #define R_DSMIF0_DSCOCNSR_OWD0N0_Msk        (0x1UL)      /*!< OWD0N0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD0N1_Pos        (1UL)        /*!< OWD0N1 (Bit 1)                                        */
+ #define R_DSMIF0_DSCOCNSR_OWD0N1_Msk        (0x2UL)      /*!< OWD0N1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD0N2_Pos        (2UL)        /*!< OWD0N2 (Bit 2)                                        */
+ #define R_DSMIF0_DSCOCNSR_OWD0N2_Msk        (0x4UL)      /*!< OWD0N2 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD1N0_Pos        (4UL)        /*!< OWD1N0 (Bit 4)                                        */
+ #define R_DSMIF0_DSCOCNSR_OWD1N0_Msk        (0x10UL)     /*!< OWD1N0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD1N1_Pos        (5UL)        /*!< OWD1N1 (Bit 5)                                        */
+ #define R_DSMIF0_DSCOCNSR_OWD1N1_Msk        (0x20UL)     /*!< OWD1N1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD1N2_Pos        (6UL)        /*!< OWD1N2 (Bit 6)                                        */
+ #define R_DSMIF0_DSCOCNSR_OWD1N2_Msk        (0x40UL)     /*!< OWD1N2 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD2N0_Pos        (8UL)        /*!< OWD2N0 (Bit 8)                                        */
+ #define R_DSMIF0_DSCOCNSR_OWD2N0_Msk        (0x100UL)    /*!< OWD2N0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD2N1_Pos        (9UL)        /*!< OWD2N1 (Bit 9)                                        */
+ #define R_DSMIF0_DSCOCNSR_OWD2N1_Msk        (0x200UL)    /*!< OWD2N1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD2N2_Pos        (10UL)       /*!< OWD2N2 (Bit 10)                                       */
+ #define R_DSMIF0_DSCOCNSR_OWD2N2_Msk        (0x400UL)    /*!< OWD2N2 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD3N0_Pos        (12UL)       /*!< OWD3N0 (Bit 12)                                       */
+ #define R_DSMIF0_DSCOCNSR_OWD3N0_Msk        (0x1000UL)   /*!< OWD3N0 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD3N1_Pos        (13UL)       /*!< OWD3N1 (Bit 13)                                       */
+ #define R_DSMIF0_DSCOCNSR_OWD3N1_Msk        (0x2000UL)   /*!< OWD3N1 (Bitfield-Mask: 0x01)                          */
+ #define R_DSMIF0_DSCOCNSR_OWD3N2_Pos        (14UL)       /*!< OWD3N2 (Bit 14)                                       */
+ #define R_DSMIF0_DSCOCNSR_OWD3N2_Msk        (0x4000UL)   /*!< OWD3N2 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DSCOCRMR  ======================================================== */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPL0_Pos      (0UL)        /*!< OC0CMPL0 (Bit 0)                                      */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPL0_Msk      (0x1UL)      /*!< OC0CMPL0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPL1_Pos      (1UL)        /*!< OC0CMPL1 (Bit 1)                                      */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPL1_Msk      (0x2UL)      /*!< OC0CMPL1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPL2_Pos      (2UL)        /*!< OC0CMPL2 (Bit 2)                                      */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPL2_Msk      (0x4UL)      /*!< OC0CMPL2 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPH0_Pos      (4UL)        /*!< OC0CMPH0 (Bit 4)                                      */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPH0_Msk      (0x10UL)     /*!< OC0CMPH0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPH1_Pos      (5UL)        /*!< OC0CMPH1 (Bit 5)                                      */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPH1_Msk      (0x20UL)     /*!< OC0CMPH1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPH2_Pos      (6UL)        /*!< OC0CMPH2 (Bit 6)                                      */
+ #define R_DSMIF0_DSCOCRMR_OC0CMPH2_Msk      (0x40UL)     /*!< OC0CMPH2 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPL0_Pos      (8UL)        /*!< OC1CMPL0 (Bit 8)                                      */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPL0_Msk      (0x100UL)    /*!< OC1CMPL0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPL1_Pos      (9UL)        /*!< OC1CMPL1 (Bit 9)                                      */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPL1_Msk      (0x200UL)    /*!< OC1CMPL1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPL2_Pos      (10UL)       /*!< OC1CMPL2 (Bit 10)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPL2_Msk      (0x400UL)    /*!< OC1CMPL2 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPH0_Pos      (12UL)       /*!< OC1CMPH0 (Bit 12)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPH0_Msk      (0x1000UL)   /*!< OC1CMPH0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPH1_Pos      (13UL)       /*!< OC1CMPH1 (Bit 13)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPH1_Msk      (0x2000UL)   /*!< OC1CMPH1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPH2_Pos      (14UL)       /*!< OC1CMPH2 (Bit 14)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC1CMPH2_Msk      (0x4000UL)   /*!< OC1CMPH2 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPL0_Pos      (16UL)       /*!< OC2CMPL0 (Bit 16)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPL0_Msk      (0x10000UL)  /*!< OC2CMPL0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPL1_Pos      (17UL)       /*!< OC2CMPL1 (Bit 17)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPL1_Msk      (0x20000UL)  /*!< OC2CMPL1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPL2_Pos      (18UL)       /*!< OC2CMPL2 (Bit 18)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPL2_Msk      (0x40000UL)  /*!< OC2CMPL2 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPH0_Pos      (20UL)       /*!< OC2CMPH0 (Bit 20)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPH0_Msk      (0x100000UL) /*!< OC2CMPH0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPH1_Pos      (21UL)       /*!< OC2CMPH1 (Bit 21)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPH1_Msk      (0x200000UL) /*!< OC2CMPH1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPH2_Pos      (22UL)       /*!< OC2CMPH2 (Bit 22)                                     */
+ #define R_DSMIF0_DSCOCRMR_OC2CMPH2_Msk      (0x400000UL) /*!< OC2CMPH2 (Bitfield-Mask: 0x01)                        */
+/* =========================================================  DSCSR  ========================================================= */
+ #define R_DSMIF0_DSCSR_DUF0_Pos             (0UL)        /*!< DUF0 (Bit 0)                                          */
+ #define R_DSMIF0_DSCSR_DUF0_Msk             (0x1UL)      /*!< DUF0 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCSR_DUF1_Pos             (1UL)        /*!< DUF1 (Bit 1)                                          */
+ #define R_DSMIF0_DSCSR_DUF1_Msk             (0x2UL)      /*!< DUF1 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCSR_DUF2_Pos             (2UL)        /*!< DUF2 (Bit 2)                                          */
+ #define R_DSMIF0_DSCSR_DUF2_Msk             (0x4UL)      /*!< DUF2 (Bitfield-Mask: 0x01)                            */
+ #define R_DSMIF0_DSCSR_CAUF0_Pos            (4UL)        /*!< CAUF0 (Bit 4)                                         */
+ #define R_DSMIF0_DSCSR_CAUF0_Msk            (0x10UL)     /*!< CAUF0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCSR_CAUF1_Pos            (5UL)        /*!< CAUF1 (Bit 5)                                         */
+ #define R_DSMIF0_DSCSR_CAUF1_Msk            (0x20UL)     /*!< CAUF1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCSR_CAUF2_Pos            (6UL)        /*!< CAUF2 (Bit 6)                                         */
+ #define R_DSMIF0_DSCSR_CAUF2_Msk            (0x40UL)     /*!< CAUF2 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCSR_CBUF0_Pos            (8UL)        /*!< CBUF0 (Bit 8)                                         */
+ #define R_DSMIF0_DSCSR_CBUF0_Msk            (0x100UL)    /*!< CBUF0 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCSR_CBUF1_Pos            (9UL)        /*!< CBUF1 (Bit 9)                                         */
+ #define R_DSMIF0_DSCSR_CBUF1_Msk            (0x200UL)    /*!< CBUF1 (Bitfield-Mask: 0x01)                           */
+ #define R_DSMIF0_DSCSR_CBUF2_Pos            (10UL)       /*!< CBUF2 (Bit 10)                                        */
+ #define R_DSMIF0_DSCSR_CBUF2_Msk            (0x400UL)    /*!< CBUF2 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DSCSSR  ========================================================= */
+ #define R_DSMIF0_DSCSSR_CHSTATE0_Pos        (0UL)        /*!< CHSTATE0 (Bit 0)                                      */
+ #define R_DSMIF0_DSCSSR_CHSTATE0_Msk        (0x1UL)      /*!< CHSTATE0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSSR_CHSTATE1_Pos        (4UL)        /*!< CHSTATE1 (Bit 4)                                      */
+ #define R_DSMIF0_DSCSSR_CHSTATE1_Msk        (0x10UL)     /*!< CHSTATE1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSSR_CHSTATE2_Pos        (8UL)        /*!< CHSTATE2 (Bit 8)                                      */
+ #define R_DSMIF0_DSCSSR_CHSTATE2_Msk        (0x100UL)    /*!< CHSTATE2 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DSCESCR  ======================================================== */
+ #define R_DSMIF0_DSCESCR_CLRSCF0_Pos        (0UL)        /*!< CLRSCF0 (Bit 0)                                       */
+ #define R_DSMIF0_DSCESCR_CLRSCF0_Msk        (0x1UL)      /*!< CLRSCF0 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCESCR_CLRSCF1_Pos        (1UL)        /*!< CLRSCF1 (Bit 1)                                       */
+ #define R_DSMIF0_DSCESCR_CLRSCF1_Msk        (0x2UL)      /*!< CLRSCF1 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCESCR_CLRSCF2_Pos        (2UL)        /*!< CLRSCF2 (Bit 2)                                       */
+ #define R_DSMIF0_DSCESCR_CLRSCF2_Msk        (0x4UL)      /*!< CLRSCF2 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCESCR_CLRSUMERRL_Pos     (16UL)       /*!< CLRSUMERRL (Bit 16)                                   */
+ #define R_DSMIF0_DSCESCR_CLRSUMERRL_Msk     (0x10000UL)  /*!< CLRSUMERRL (Bitfield-Mask: 0x01)                      */
+ #define R_DSMIF0_DSCESCR_CLRSUMERRH_Pos     (17UL)       /*!< CLRSUMERRH (Bit 17)                                   */
+ #define R_DSMIF0_DSCESCR_CLRSUMERRH_Msk     (0x20000UL)  /*!< CLRSUMERRH (Bitfield-Mask: 0x01)                      */
+/* =======================================================  DSCOCESCR  ======================================================= */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FL0_Pos    (0UL)        /*!< CLROC0FL0 (Bit 0)                                     */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FL0_Msk    (0x1UL)      /*!< CLROC0FL0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FL1_Pos    (1UL)        /*!< CLROC0FL1 (Bit 1)                                     */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FL1_Msk    (0x2UL)      /*!< CLROC0FL1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FL2_Pos    (2UL)        /*!< CLROC0FL2 (Bit 2)                                     */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FL2_Msk    (0x4UL)      /*!< CLROC0FL2 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FH0_Pos    (4UL)        /*!< CLROC0FH0 (Bit 4)                                     */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FH0_Msk    (0x10UL)     /*!< CLROC0FH0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FH1_Pos    (5UL)        /*!< CLROC0FH1 (Bit 5)                                     */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FH1_Msk    (0x20UL)     /*!< CLROC0FH1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FH2_Pos    (6UL)        /*!< CLROC0FH2 (Bit 6)                                     */
+ #define R_DSMIF0_DSCOCESCR_CLROC0FH2_Msk    (0x40UL)     /*!< CLROC0FH2 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FL0_Pos    (8UL)        /*!< CLROC1FL0 (Bit 8)                                     */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FL0_Msk    (0x100UL)    /*!< CLROC1FL0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FL1_Pos    (9UL)        /*!< CLROC1FL1 (Bit 9)                                     */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FL1_Msk    (0x200UL)    /*!< CLROC1FL1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FL2_Pos    (10UL)       /*!< CLROC1FL2 (Bit 10)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FL2_Msk    (0x400UL)    /*!< CLROC1FL2 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FH0_Pos    (12UL)       /*!< CLROC1FH0 (Bit 12)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FH0_Msk    (0x1000UL)   /*!< CLROC1FH0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FH1_Pos    (13UL)       /*!< CLROC1FH1 (Bit 13)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FH1_Msk    (0x2000UL)   /*!< CLROC1FH1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FH2_Pos    (14UL)       /*!< CLROC1FH2 (Bit 14)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC1FH2_Msk    (0x4000UL)   /*!< CLROC1FH2 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FL0_Pos    (16UL)       /*!< CLROC2FL0 (Bit 16)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FL0_Msk    (0x10000UL)  /*!< CLROC2FL0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FL1_Pos    (17UL)       /*!< CLROC2FL1 (Bit 17)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FL1_Msk    (0x20000UL)  /*!< CLROC2FL1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FL2_Pos    (18UL)       /*!< CLROC2FL2 (Bit 18)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FL2_Msk    (0x40000UL)  /*!< CLROC2FL2 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FH0_Pos    (20UL)       /*!< CLROC2FH0 (Bit 20)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FH0_Msk    (0x100000UL) /*!< CLROC2FH0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FH1_Pos    (21UL)       /*!< CLROC2FH1 (Bit 21)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FH1_Msk    (0x200000UL) /*!< CLROC2FH1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FH2_Pos    (22UL)       /*!< CLROC2FH2 (Bit 22)                                    */
+ #define R_DSMIF0_DSCOCESCR_CLROC2FH2_Msk    (0x400000UL) /*!< CLROC2FH2 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  DSCOCNSCR  ======================================================= */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD0N0_Pos    (0UL)        /*!< CLROWD0N0 (Bit 0)                                     */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD0N0_Msk    (0x1UL)      /*!< CLROWD0N0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD0N1_Pos    (1UL)        /*!< CLROWD0N1 (Bit 1)                                     */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD0N1_Msk    (0x2UL)      /*!< CLROWD0N1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD0N2_Pos    (2UL)        /*!< CLROWD0N2 (Bit 2)                                     */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD0N2_Msk    (0x4UL)      /*!< CLROWD0N2 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD1N0_Pos    (4UL)        /*!< CLROWD1N0 (Bit 4)                                     */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD1N0_Msk    (0x10UL)     /*!< CLROWD1N0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD1N1_Pos    (5UL)        /*!< CLROWD1N1 (Bit 5)                                     */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD1N1_Msk    (0x20UL)     /*!< CLROWD1N1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD1N2_Pos    (6UL)        /*!< CLROWD1N2 (Bit 6)                                     */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD1N2_Msk    (0x40UL)     /*!< CLROWD1N2 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD2N0_Pos    (8UL)        /*!< CLROWD2N0 (Bit 8)                                     */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD2N0_Msk    (0x100UL)    /*!< CLROWD2N0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD2N1_Pos    (9UL)        /*!< CLROWD2N1 (Bit 9)                                     */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD2N1_Msk    (0x200UL)    /*!< CLROWD2N1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD2N2_Pos    (10UL)       /*!< CLROWD2N2 (Bit 10)                                    */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD2N2_Msk    (0x400UL)    /*!< CLROWD2N2 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD3N0_Pos    (12UL)       /*!< CLROWD3N0 (Bit 12)                                    */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD3N0_Msk    (0x1000UL)   /*!< CLROWD3N0 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD3N1_Pos    (13UL)       /*!< CLROWD3N1 (Bit 13)                                    */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD3N1_Msk    (0x2000UL)   /*!< CLROWD3N1 (Bitfield-Mask: 0x01)                       */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD3N2_Pos    (14UL)       /*!< CLROWD3N2 (Bit 14)                                    */
+ #define R_DSMIF0_DSCOCNSCR_CLROWD3N2_Msk    (0x4000UL)   /*!< CLROWD3N2 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  DSCSCR  ========================================================= */
+ #define R_DSMIF0_DSCSCR_CLRDUF0_Pos         (0UL)        /*!< CLRDUF0 (Bit 0)                                       */
+ #define R_DSMIF0_DSCSCR_CLRDUF0_Msk         (0x1UL)      /*!< CLRDUF0 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSCR_CLRDUF1_Pos         (1UL)        /*!< CLRDUF1 (Bit 1)                                       */
+ #define R_DSMIF0_DSCSCR_CLRDUF1_Msk         (0x2UL)      /*!< CLRDUF1 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSCR_CLRDUF2_Pos         (2UL)        /*!< CLRDUF2 (Bit 2)                                       */
+ #define R_DSMIF0_DSCSCR_CLRDUF2_Msk         (0x4UL)      /*!< CLRDUF2 (Bitfield-Mask: 0x01)                         */
+ #define R_DSMIF0_DSCSCR_CLRCAUF0_Pos        (4UL)        /*!< CLRCAUF0 (Bit 4)                                      */
+ #define R_DSMIF0_DSCSCR_CLRCAUF0_Msk        (0x10UL)     /*!< CLRCAUF0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSCR_CLRCAUF1_Pos        (5UL)        /*!< CLRCAUF1 (Bit 5)                                      */
+ #define R_DSMIF0_DSCSCR_CLRCAUF1_Msk        (0x20UL)     /*!< CLRCAUF1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSCR_CLRCAUF2_Pos        (6UL)        /*!< CLRCAUF2 (Bit 6)                                      */
+ #define R_DSMIF0_DSCSCR_CLRCAUF2_Msk        (0x40UL)     /*!< CLRCAUF2 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSCR_CLRCBUF0_Pos        (8UL)        /*!< CLRCBUF0 (Bit 8)                                      */
+ #define R_DSMIF0_DSCSCR_CLRCBUF0_Msk        (0x100UL)    /*!< CLRCBUF0 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSCR_CLRCBUF1_Pos        (9UL)        /*!< CLRCBUF1 (Bit 9)                                      */
+ #define R_DSMIF0_DSCSCR_CLRCBUF1_Msk        (0x200UL)    /*!< CLRCBUF1 (Bitfield-Mask: 0x01)                        */
+ #define R_DSMIF0_DSCSCR_CLRCBUF2_Pos        (10UL)       /*!< CLRCBUF2 (Bit 10)                                     */
+ #define R_DSMIF0_DSCSCR_CLRCBUF2_Msk        (0x400UL)    /*!< CLRCBUF2 (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                         R_HDSLD0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  SYS_CTRL  ======================================================== */
+ #define R_HDSLD0_SYS_CTRL_OEN_Pos         (0UL)    /*!< OEN (Bit 0)                                           */
+ #define R_HDSLD0_SYS_CTRL_OEN_Msk         (0x1UL)  /*!< OEN (Bitfield-Mask: 0x01)                             */
+ #define R_HDSLD0_SYS_CTRL_SPOL_Pos        (1UL)    /*!< SPOL (Bit 1)                                          */
+ #define R_HDSLD0_SYS_CTRL_SPOL_Msk        (0x2UL)  /*!< SPOL (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_SYS_CTRL_LOOP_Pos        (4UL)    /*!< LOOP (Bit 4)                                          */
+ #define R_HDSLD0_SYS_CTRL_LOOP_Msk        (0x10UL) /*!< LOOP (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_SYS_CTRL_FRST_Pos        (5UL)    /*!< FRST (Bit 5)                                          */
+ #define R_HDSLD0_SYS_CTRL_FRST_Msk        (0x20UL) /*!< FRST (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_SYS_CTRL_MRST_Pos        (6UL)    /*!< MRST (Bit 6)                                          */
+ #define R_HDSLD0_SYS_CTRL_MRST_Msk        (0x40UL) /*!< MRST (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_SYS_CTRL_PRST_Pos        (7UL)    /*!< PRST (Bit 7)                                          */
+ #define R_HDSLD0_SYS_CTRL_PRST_Msk        (0x80UL) /*!< PRST (Bitfield-Mask: 0x01)                            */
+/* =======================================================  SYNC_CTRL  ======================================================= */
+ #define R_HDSLD0_SYNC_CTRL_ES_Pos         (0UL)    /*!< ES (Bit 0)                                            */
+ #define R_HDSLD0_SYNC_CTRL_ES_Msk         (0xffUL) /*!< ES (Bitfield-Mask: 0xff)                              */
+/* =======================================================  MASTER_QM  ======================================================= */
+ #define R_HDSLD0_MASTER_QM_QM_Pos         (0UL)    /*!< QM (Bit 0)                                            */
+ #define R_HDSLD0_MASTER_QM_QM_Msk         (0xfUL)  /*!< QM (Bitfield-Mask: 0x0f)                              */
+ #define R_HDSLD0_MASTER_QM_LINK_Pos       (7UL)    /*!< LINK (Bit 7)                                          */
+ #define R_HDSLD0_MASTER_QM_LINK_Msk       (0x80UL) /*!< LINK (Bitfield-Mask: 0x01)                            */
+/* ========================================================  EVENT_H  ======================================================== */
+ #define R_HDSLD0_EVENT_H_PRST_Pos         (0UL)    /*!< PRST (Bit 0)                                          */
+ #define R_HDSLD0_EVENT_H_PRST_Msk         (0x1UL)  /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_EVENT_H_DTE_Pos          (1UL)    /*!< DTE (Bit 1)                                           */
+ #define R_HDSLD0_EVENT_H_DTE_Msk          (0x2UL)  /*!< DTE (Bitfield-Mask: 0x01)                             */
+ #define R_HDSLD0_EVENT_H_POS_Pos          (3UL)    /*!< POS (Bit 3)                                           */
+ #define R_HDSLD0_EVENT_H_POS_Msk          (0x8UL)  /*!< POS (Bitfield-Mask: 0x01)                             */
+ #define R_HDSLD0_EVENT_H_SUM_Pos          (6UL)    /*!< SUM (Bit 6)                                           */
+ #define R_HDSLD0_EVENT_H_SUM_Msk          (0x40UL) /*!< SUM (Bitfield-Mask: 0x01)                             */
+ #define R_HDSLD0_EVENT_H_INT_Pos          (7UL)    /*!< INT (Bit 7)                                           */
+ #define R_HDSLD0_EVENT_H_INT_Msk          (0x80UL) /*!< INT (Bitfield-Mask: 0x01)                             */
+/* ========================================================  EVENT_L  ======================================================== */
+ #define R_HDSLD0_EVENT_L_FREL_Pos         (1UL)    /*!< FREL (Bit 1)                                          */
+ #define R_HDSLD0_EVENT_L_FREL_Msk         (0x2UL)  /*!< FREL (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_EVENT_L_QMLW_Pos         (2UL)    /*!< QMLW (Bit 2)                                          */
+ #define R_HDSLD0_EVENT_L_QMLW_Msk         (0x4UL)  /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_EVENT_L_ANS_Pos          (4UL)    /*!< ANS (Bit 4)                                           */
+ #define R_HDSLD0_EVENT_L_ANS_Msk          (0x10UL) /*!< ANS (Bitfield-Mask: 0x01)                             */
+ #define R_HDSLD0_EVENT_L_MIN_Pos          (5UL)    /*!< MIN (Bit 5)                                           */
+ #define R_HDSLD0_EVENT_L_MIN_Msk          (0x20UL) /*!< MIN (Bitfield-Mask: 0x01)                             */
+/* ========================================================  MASK_H  ========================================================= */
+ #define R_HDSLD0_MASK_H_MPRST_Pos         (0UL)    /*!< MPRST (Bit 0)                                         */
+ #define R_HDSLD0_MASK_H_MPRST_Msk         (0x1UL)  /*!< MPRST (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLD0_MASK_H_MDTE_Pos          (1UL)    /*!< MDTE (Bit 1)                                          */
+ #define R_HDSLD0_MASK_H_MDTE_Msk          (0x2UL)  /*!< MDTE (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_MASK_H_MPOS_Pos          (3UL)    /*!< MPOS (Bit 3)                                          */
+ #define R_HDSLD0_MASK_H_MPOS_Msk          (0x8UL)  /*!< MPOS (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_MASK_H_MSUM_Pos          (6UL)    /*!< MSUM (Bit 6)                                          */
+ #define R_HDSLD0_MASK_H_MSUM_Msk          (0x40UL) /*!< MSUM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  MASK_L  ========================================================= */
+ #define R_HDSLD0_MASK_L_MFREL_Pos         (1UL)    /*!< MFREL (Bit 1)                                         */
+ #define R_HDSLD0_MASK_L_MFREL_Msk         (0x2UL)  /*!< MFREL (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLD0_MASK_L_MQMLW_Pos         (2UL)    /*!< MQMLW (Bit 2)                                         */
+ #define R_HDSLD0_MASK_L_MQMLW_Msk         (0x4UL)  /*!< MQMLW (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLD0_MASK_L_MANS_Pos          (4UL)    /*!< MANS (Bit 4)                                          */
+ #define R_HDSLD0_MASK_L_MANS_Msk          (0x10UL) /*!< MANS (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_MASK_L_MMIN_Pos          (5UL)    /*!< MMIN (Bit 5)                                          */
+ #define R_HDSLD0_MASK_L_MMIN_Msk          (0x20UL) /*!< MMIN (Bitfield-Mask: 0x01)                            */
+/* =======================================================  MASK_SUM  ======================================================== */
+ #define R_HDSLD0_MASK_SUM_MSUM_Pos        (0UL)    /*!< MSUM (Bit 0)                                          */
+ #define R_HDSLD0_MASK_SUM_MSUM_Msk        (0xffUL) /*!< MSUM (Bitfield-Mask: 0xff)                            */
+/* =========================================================  EDGES  ========================================================= */
+ #define R_HDSLD0_EDGES_EDGES_Pos          (0UL)    /*!< EDGES (Bit 0)                                         */
+ #define R_HDSLD0_EDGES_EDGES_Msk          (0xffUL) /*!< EDGES (Bitfield-Mask: 0xff)                           */
+/* =========================================================  DELAY  ========================================================= */
+ #define R_HDSLD0_DELAY_CBLDLY_Pos         (0UL)    /*!< CBLDLY (Bit 0)                                        */
+ #define R_HDSLD0_DELAY_CBLDLY_Msk         (0xfUL)  /*!< CBLDLY (Bitfield-Mask: 0x0f)                          */
+ #define R_HDSLD0_DELAY_RSSI_Pos           (4UL)    /*!< RSSI (Bit 4)                                          */
+ #define R_HDSLD0_DELAY_RSSI_Msk           (0xf0UL) /*!< RSSI (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  VERSION  ======================================================== */
+ #define R_HDSLD0_VERSION_MINOR_Pos        (0UL)    /*!< MINOR (Bit 0)                                         */
+ #define R_HDSLD0_VERSION_MINOR_Msk        (0xfUL)  /*!< MINOR (Bitfield-Mask: 0x0f)                           */
+ #define R_HDSLD0_VERSION_MAJOR_Pos        (4UL)    /*!< MAJOR (Bit 4)                                         */
+ #define R_HDSLD0_VERSION_MAJOR_Msk        (0x30UL) /*!< MAJOR (Bitfield-Mask: 0x03)                           */
+ #define R_HDSLD0_VERSION_CODE_Pos         (6UL)    /*!< CODE (Bit 6)                                          */
+ #define R_HDSLD0_VERSION_CODE_Msk         (0xc0UL) /*!< CODE (Bitfield-Mask: 0x03)                            */
+/* ========================================================  ENC_ID2  ======================================================== */
+ #define R_HDSLD0_ENC_ID2_ENCID_Pos        (0UL)    /*!< ENCID (Bit 0)                                         */
+ #define R_HDSLD0_ENC_ID2_ENCID_Msk        (0xfUL)  /*!< ENCID (Bitfield-Mask: 0x0f)                           */
+ #define R_HDSLD0_ENC_ID2_SCI_Pos          (4UL)    /*!< SCI (Bit 4)                                           */
+ #define R_HDSLD0_ENC_ID2_SCI_Msk          (0x70UL) /*!< SCI (Bitfield-Mask: 0x07)                             */
+/* ========================================================  ENC_ID1  ======================================================== */
+ #define R_HDSLD0_ENC_ID1_ENCID_Pos        (0UL)    /*!< ENCID (Bit 0)                                         */
+ #define R_HDSLD0_ENC_ID1_ENCID_Msk        (0xffUL) /*!< ENCID (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ENC_ID0  ======================================================== */
+ #define R_HDSLD0_ENC_ID0_ENCID_Pos        (0UL)    /*!< ENCID (Bit 0)                                         */
+ #define R_HDSLD0_ENC_ID0_ENCID_Msk        (0xffUL) /*!< ENCID (Bitfield-Mask: 0xff)                           */
+/* =========================================================  POS4  ========================================================== */
+ #define R_HDSLD0_POS4_POS_Pos             (0UL)    /*!< POS (Bit 0)                                           */
+ #define R_HDSLD0_POS4_POS_Msk             (0xffUL) /*!< POS (Bitfield-Mask: 0xff)                             */
+/* =========================================================  POS3  ========================================================== */
+ #define R_HDSLD0_POS3_POS_Pos             (0UL)    /*!< POS (Bit 0)                                           */
+ #define R_HDSLD0_POS3_POS_Msk             (0xffUL) /*!< POS (Bitfield-Mask: 0xff)                             */
+/* =========================================================  POS2  ========================================================== */
+ #define R_HDSLD0_POS2_POS_Pos             (0UL)    /*!< POS (Bit 0)                                           */
+ #define R_HDSLD0_POS2_POS_Msk             (0xffUL) /*!< POS (Bitfield-Mask: 0xff)                             */
+/* =========================================================  POS1  ========================================================== */
+ #define R_HDSLD0_POS1_POS_Pos             (0UL)    /*!< POS (Bit 0)                                           */
+ #define R_HDSLD0_POS1_POS_Msk             (0xffUL) /*!< POS (Bitfield-Mask: 0xff)                             */
+/* =========================================================  POS0  ========================================================== */
+ #define R_HDSLD0_POS0_POS_Pos             (0UL)    /*!< POS (Bit 0)                                           */
+ #define R_HDSLD0_POS0_POS_Msk             (0xffUL) /*!< POS (Bitfield-Mask: 0xff)                             */
+/* =========================================================  VEL2  ========================================================== */
+ #define R_HDSLD0_VEL2_VEL_Pos             (0UL)    /*!< VEL (Bit 0)                                           */
+ #define R_HDSLD0_VEL2_VEL_Msk             (0xffUL) /*!< VEL (Bitfield-Mask: 0xff)                             */
+/* =========================================================  VEL1  ========================================================== */
+ #define R_HDSLD0_VEL1_VEL_Pos             (0UL)    /*!< VEL (Bit 0)                                           */
+ #define R_HDSLD0_VEL1_VEL_Msk             (0xffUL) /*!< VEL (Bitfield-Mask: 0xff)                             */
+/* =========================================================  VEL0  ========================================================== */
+ #define R_HDSLD0_VEL0_VEL_Pos             (0UL)    /*!< VEL (Bit 0)                                           */
+ #define R_HDSLD0_VEL0_VEL_Msk             (0xffUL) /*!< VEL (Bitfield-Mask: 0xff)                             */
+/* ========================================================  MIR_SUM  ======================================================== */
+ #define R_HDSLD0_MIR_SUM_SUM_Pos          (0UL)    /*!< SUM (Bit 0)                                           */
+ #define R_HDSLD0_MIR_SUM_SUM_Msk          (0xffUL) /*!< SUM (Bitfield-Mask: 0xff)                             */
+/* ========================================================  PC_BUF  ========================================================= */
+ #define R_HDSLD0_PC_BUF_PCBUF_Pos         (0UL)    /*!< PCBUF (Bit 0)                                         */
+ #define R_HDSLD0_PC_BUF_PCBUF_Msk         (0xffUL) /*!< PCBUF (Bitfield-Mask: 0xff)                           */
+/* =======================================================  PC_ADD_H  ======================================================== */
+ #define R_HDSLD0_PC_ADD_H_LADDH_Pos       (0UL)    /*!< LADDH (Bit 0)                                         */
+ #define R_HDSLD0_PC_ADD_H_LADDH_Msk       (0x3UL)  /*!< LADDH (Bitfield-Mask: 0x03)                           */
+ #define R_HDSLD0_PC_ADD_H_LLEN_Pos        (2UL)    /*!< LLEN (Bit 2)                                          */
+ #define R_HDSLD0_PC_ADD_H_LLEN_Msk        (0xcUL)  /*!< LLEN (Bitfield-Mask: 0x03)                            */
+ #define R_HDSLD0_PC_ADD_H_LIND_Pos        (4UL)    /*!< LIND (Bit 4)                                          */
+ #define R_HDSLD0_PC_ADD_H_LIND_Msk        (0x10UL) /*!< LIND (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_PC_ADD_H_LOFF_Pos        (5UL)    /*!< LOFF (Bit 5)                                          */
+ #define R_HDSLD0_PC_ADD_H_LOFF_Msk        (0x20UL) /*!< LOFF (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_PC_ADD_H_LRW_Pos         (6UL)    /*!< LRW (Bit 6)                                           */
+ #define R_HDSLD0_PC_ADD_H_LRW_Msk         (0x40UL) /*!< LRW (Bitfield-Mask: 0x01)                             */
+/* =======================================================  PC_ADD_L  ======================================================== */
+ #define R_HDSLD0_PC_ADD_L_LADDL_Pos       (0UL)    /*!< LADDL (Bit 0)                                         */
+ #define R_HDSLD0_PC_ADD_L_LADDL_Msk       (0xffUL) /*!< LADDL (Bitfield-Mask: 0xff)                           */
+/* =======================================================  PC_OFF_H  ======================================================== */
+ #define R_HDSLD0_PC_OFF_H_LOFFADDH_Pos    (0UL)    /*!< LOFFADDH (Bit 0)                                      */
+ #define R_HDSLD0_PC_OFF_H_LOFFADDH_Msk    (0x7fUL) /*!< LOFFADDH (Bitfield-Mask: 0x7f)                        */
+ #define R_HDSLD0_PC_OFF_H_LID_Pos         (7UL)    /*!< LID (Bit 7)                                           */
+ #define R_HDSLD0_PC_OFF_H_LID_Msk         (0x80UL) /*!< LID (Bitfield-Mask: 0x01)                             */
+/* =======================================================  PC_OFF_L  ======================================================== */
+ #define R_HDSLD0_PC_OFF_L_LOFFADDL_Pos    (0UL)    /*!< LOFFADDL (Bit 0)                                      */
+ #define R_HDSLD0_PC_OFF_L_LOFFADDL_Msk    (0xffUL) /*!< LOFFADDL (Bitfield-Mask: 0xff)                        */
+/* ========================================================  PC_CTRL  ======================================================== */
+ #define R_HDSLD0_PC_CTRL_LSTA_Pos         (0UL)    /*!< LSTA (Bit 0)                                          */
+ #define R_HDSLD0_PC_CTRL_LSTA_Msk         (0x1UL)  /*!< LSTA (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PIPE_S  ========================================================= */
+ #define R_HDSLD0_PIPE_S_PSCI_Pos          (0UL)    /*!< PSCI (Bit 0)                                          */
+ #define R_HDSLD0_PIPE_S_PSCI_Msk          (0x1UL)  /*!< PSCI (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_PIPE_S_PERR_Pos          (1UL)    /*!< PERR (Bit 1)                                          */
+ #define R_HDSLD0_PIPE_S_PERR_Msk          (0x2UL)  /*!< PERR (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_PIPE_S_PEMP_Pos          (2UL)    /*!< PEMP (Bit 2)                                          */
+ #define R_HDSLD0_PIPE_S_PEMP_Msk          (0x4UL)  /*!< PEMP (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLD0_PIPE_S_POVR_Pos          (3UL)    /*!< POVR (Bit 3)                                          */
+ #define R_HDSLD0_PIPE_S_POVR_Msk          (0x8UL)  /*!< POVR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PIPE_D  ========================================================= */
+ #define R_HDSLD0_PIPE_D_SCDATA_Pos        (0UL)    /*!< SCDATA (Bit 0)                                        */
+ #define R_HDSLD0_PIPE_D_SCDATA_Msk        (0xffUL) /*!< SCDATA (Bitfield-Mask: 0xff)                          */
+/* ========================================================  PC_DATA  ======================================================== */
+ #define R_HDSLD0_PC_DATA_PCDATA_Pos       (0UL)    /*!< PCDATA (Bit 0)                                        */
+ #define R_HDSLD0_PC_DATA_PCDATA_Msk       (0xffUL) /*!< PCDATA (Bitfield-Mask: 0xff)                          */
+/* ======================================================  ACC_ERR_CNT  ====================================================== */
+ #define R_HDSLD0_ACC_ERR_CNT_CNT_Pos      (0UL)    /*!< CNT (Bit 0)                                           */
+ #define R_HDSLD0_ACC_ERR_CNT_CNT_Msk      (0x1fUL) /*!< CNT (Bitfield-Mask: 0x1f)                             */
+/* ========================================================  MAXACC  ========================================================= */
+ #define R_HDSLD0_MAXACC_MNT_Pos           (0UL)    /*!< MNT (Bit 0)                                           */
+ #define R_HDSLD0_MAXACC_MNT_Msk           (0x3fUL) /*!< MNT (Bitfield-Mask: 0x3f)                             */
+ #define R_HDSLD0_MAXACC_RES_Pos           (6UL)    /*!< RES (Bit 6)                                           */
+ #define R_HDSLD0_MAXACC_RES_Msk           (0xc0UL) /*!< RES (Bitfield-Mask: 0x03)                             */
+/* =======================================================  MAXDEV_H  ======================================================== */
+ #define R_HDSLD0_MAXDEV_H_DEVH_Pos        (0UL)    /*!< DEVH (Bit 0)                                          */
+ #define R_HDSLD0_MAXDEV_H_DEVH_Msk        (0xffUL) /*!< DEVH (Bitfield-Mask: 0xff)                            */
+/* =======================================================  MAXDEV_L  ======================================================== */
+ #define R_HDSLD0_MAXDEV_L_DEVL_Pos        (0UL)    /*!< DEVL (Bit 0)                                          */
+ #define R_HDSLD0_MAXDEV_L_DEVL_Msk        (0xffUL) /*!< DEVL (Bitfield-Mask: 0xff)                            */
+/* =========================================================  DUMMY  ========================================================= */
+ #define R_HDSLD0_DUMMY_DUMMY_Pos          (0UL)    /*!< DUMMY (Bit 0)                                         */
+ #define R_HDSLD0_DUMMY_DUMMY_Msk          (0xffUL) /*!< DUMMY (Bitfield-Mask: 0xff)                           */
+/* ========================================================  MIR_ST  ========================================================= */
+ #define R_HDSLD0_MIR_ST_MIRST_Pos         (0UL)    /*!< MIRST (Bit 0)                                         */
+ #define R_HDSLD0_MIR_ST_MIRST_Msk         (0xffUL) /*!< MIRST (Bitfield-Mask: 0xff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                         R_HDSLS10                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  EDGES  ========================================================= */
+ #define R_HDSLS10_EDGES_EDGES_Pos           (0UL)    /*!< EDGES (Bit 0)                                         */
+ #define R_HDSLS10_EDGES_EDGES_Msk           (0xffUL) /*!< EDGES (Bitfield-Mask: 0xff)                           */
+/* =========================================================  DELAY  ========================================================= */
+ #define R_HDSLS10_DELAY_CBLDLY_Pos          (0UL)    /*!< CBLDLY (Bit 0)                                        */
+ #define R_HDSLS10_DELAY_CBLDLY_Msk          (0xfUL)  /*!< CBLDLY (Bitfield-Mask: 0x0f)                          */
+ #define R_HDSLS10_DELAY_RSSI_Pos            (4UL)    /*!< RSSI (Bit 4)                                          */
+ #define R_HDSLS10_DELAY_RSSI_Msk            (0xf0UL) /*!< RSSI (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  VERSION  ======================================================== */
+ #define R_HDSLS10_VERSION_MINOR_Pos         (0UL)    /*!< MINOR (Bit 0)                                         */
+ #define R_HDSLS10_VERSION_MINOR_Msk         (0xfUL)  /*!< MINOR (Bitfield-Mask: 0x0f)                           */
+ #define R_HDSLS10_VERSION_MAJOR_Pos         (4UL)    /*!< MAJOR (Bit 4)                                         */
+ #define R_HDSLS10_VERSION_MAJOR_Msk         (0x30UL) /*!< MAJOR (Bitfield-Mask: 0x03)                           */
+ #define R_HDSLS10_VERSION_CODE_Pos          (6UL)    /*!< CODE (Bit 6)                                          */
+ #define R_HDSLS10_VERSION_CODE_Msk          (0xc0UL) /*!< CODE (Bitfield-Mask: 0x03)                            */
+/* ========================================================  ENC_ID2  ======================================================== */
+ #define R_HDSLS10_ENC_ID2_ENCID_Pos         (0UL)    /*!< ENCID (Bit 0)                                         */
+ #define R_HDSLS10_ENC_ID2_ENCID_Msk         (0xfUL)  /*!< ENCID (Bitfield-Mask: 0x0f)                           */
+ #define R_HDSLS10_ENC_ID2_SCI_Pos           (4UL)    /*!< SCI (Bit 4)                                           */
+ #define R_HDSLS10_ENC_ID2_SCI_Msk           (0x70UL) /*!< SCI (Bitfield-Mask: 0x07)                             */
+/* ========================================================  ENC_ID1  ======================================================== */
+ #define R_HDSLS10_ENC_ID1_ENCID_Pos         (0UL)    /*!< ENCID (Bit 0)                                         */
+ #define R_HDSLS10_ENC_ID1_ENCID_Msk         (0xffUL) /*!< ENCID (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ENC_ID0  ======================================================== */
+ #define R_HDSLS10_ENC_ID0_ENCID_Pos         (0UL)    /*!< ENCID (Bit 0)                                         */
+ #define R_HDSLS10_ENC_ID0_ENCID_Msk         (0xffUL) /*!< ENCID (Bitfield-Mask: 0xff)                           */
+/* =========================================================  VPOS4  ========================================================= */
+ #define R_HDSLS10_VPOS4_VPOS_Pos            (0UL)    /*!< VPOS (Bit 0)                                          */
+ #define R_HDSLS10_VPOS4_VPOS_Msk            (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff)                            */
+/* =========================================================  VPOS3  ========================================================= */
+ #define R_HDSLS10_VPOS3_VPOS_Pos            (0UL)    /*!< VPOS (Bit 0)                                          */
+ #define R_HDSLS10_VPOS3_VPOS_Msk            (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff)                            */
+/* =========================================================  VPOS2  ========================================================= */
+ #define R_HDSLS10_VPOS2_VPOS_Pos            (0UL)    /*!< VPOS (Bit 0)                                          */
+ #define R_HDSLS10_VPOS2_VPOS_Msk            (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff)                            */
+/* =========================================================  VPOS1  ========================================================= */
+ #define R_HDSLS10_VPOS1_VPOS_Pos            (0UL)    /*!< VPOS (Bit 0)                                          */
+ #define R_HDSLS10_VPOS1_VPOS_Msk            (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff)                            */
+/* =========================================================  VPOS0  ========================================================= */
+ #define R_HDSLS10_VPOS0_VPOS_Pos            (0UL)    /*!< VPOS (Bit 0)                                          */
+ #define R_HDSLS10_VPOS0_VPOS_Msk            (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff)                            */
+/* =======================================================  VPOSCRC_H  ======================================================= */
+ #define R_HDSLS10_VPOSCRC_H_VPOSCRCH_Pos    (0UL)    /*!< VPOSCRCH (Bit 0)                                      */
+ #define R_HDSLS10_VPOSCRC_H_VPOSCRCH_Msk    (0xffUL) /*!< VPOSCRCH (Bitfield-Mask: 0xff)                        */
+/* =======================================================  VPOSCRC_L  ======================================================= */
+ #define R_HDSLS10_VPOSCRC_L_VPOSCRCL_Pos    (0UL)    /*!< VPOSCRCL (Bit 0)                                      */
+ #define R_HDSLS10_VPOSCRC_L_VPOSCRCL_Msk    (0xffUL) /*!< VPOSCRCL (Bitfield-Mask: 0xff)                        */
+/* =======================================================  SAFE_CTRL  ======================================================= */
+ #define R_HDSLS10_SAFE_CTRL_MRST_Pos        (6UL)    /*!< MRST (Bit 6)                                          */
+ #define R_HDSLS10_SAFE_CTRL_MRST_Msk        (0x40UL) /*!< MRST (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS10_SAFE_CTRL_PRST_Pos        (7UL)    /*!< PRST (Bit 7)                                          */
+ #define R_HDSLS10_SAFE_CTRL_PRST_Msk        (0x80UL) /*!< PRST (Bitfield-Mask: 0x01)                            */
+/* =======================================================  SAFE_SUM  ======================================================== */
+ #define R_HDSLS10_SAFE_SUM_SSUM_Pos         (0UL)    /*!< SSUM (Bit 0)                                          */
+ #define R_HDSLS10_SAFE_SUM_SSUM_Msk         (0xffUL) /*!< SSUM (Bitfield-Mask: 0xff)                            */
+/* =======================================================  S_PC_DATA  ======================================================= */
+ #define R_HDSLS10_S_PC_DATA_SPCDATA_Pos     (0UL)    /*!< SPCDATA (Bit 0)                                       */
+ #define R_HDSLS10_S_PC_DATA_SPCDATA_Msk     (0xffUL) /*!< SPCDATA (Bitfield-Mask: 0xff)                         */
+/* ========================================================  EVENT_S  ======================================================== */
+ #define R_HDSLS10_EVENT_S_FRES_Pos          (0UL)    /*!< FRES (Bit 0)                                          */
+ #define R_HDSLS10_EVENT_S_FRES_Msk          (0x1UL)  /*!< FRES (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS10_EVENT_S_MIN_Pos           (1UL)    /*!< MIN (Bit 1)                                           */
+ #define R_HDSLS10_EVENT_S_MIN_Msk           (0x2UL)  /*!< MIN (Bitfield-Mask: 0x01)                             */
+ #define R_HDSLS10_EVENT_S_PRST_Pos          (2UL)    /*!< PRST (Bit 2)                                          */
+ #define R_HDSLS10_EVENT_S_PRST_Msk          (0x4UL)  /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS10_EVENT_S_QMLW_Pos          (3UL)    /*!< QMLW (Bit 3)                                          */
+ #define R_HDSLS10_EVENT_S_QMLW_Msk          (0x8UL)  /*!< QMLW (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS10_EVENT_S_VPOS_Pos          (4UL)    /*!< VPOS (Bit 4)                                          */
+ #define R_HDSLS10_EVENT_S_VPOS_Msk          (0x10UL) /*!< VPOS (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS10_EVENT_S_SCE_Pos           (5UL)    /*!< SCE (Bit 5)                                           */
+ #define R_HDSLS10_EVENT_S_SCE_Msk           (0x20UL) /*!< SCE (Bitfield-Mask: 0x01)                             */
+ #define R_HDSLS10_EVENT_S_SSUM_Pos          (6UL)    /*!< SSUM (Bit 6)                                          */
+ #define R_HDSLS10_EVENT_S_SSUM_Msk          (0x40UL) /*!< SSUM (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS10_EVENT_S_SINT_Pos          (7UL)    /*!< SINT (Bit 7)                                          */
+ #define R_HDSLS10_EVENT_S_SINT_Msk          (0x80UL) /*!< SINT (Bitfield-Mask: 0x01)                            */
+/* ========================================================  MASK_S  ========================================================= */
+ #define R_HDSLS10_MASK_S_MFRES_Pos          (0UL)    /*!< MFRES (Bit 0)                                         */
+ #define R_HDSLS10_MASK_S_MFRES_Msk          (0x1UL)  /*!< MFRES (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLS10_MASK_S_MMIN_Pos           (1UL)    /*!< MMIN (Bit 1)                                          */
+ #define R_HDSLS10_MASK_S_MMIN_Msk           (0x2UL)  /*!< MMIN (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS10_MASK_S_MPRST_Pos          (2UL)    /*!< MPRST (Bit 2)                                         */
+ #define R_HDSLS10_MASK_S_MPRST_Msk          (0x4UL)  /*!< MPRST (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLS10_MASK_S_MQMLW_Pos          (3UL)    /*!< MQMLW (Bit 3)                                         */
+ #define R_HDSLS10_MASK_S_MQMLW_Msk          (0x8UL)  /*!< MQMLW (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLS10_MASK_S_MVPOS_Pos          (4UL)    /*!< MVPOS (Bit 4)                                         */
+ #define R_HDSLS10_MASK_S_MVPOS_Msk          (0x10UL) /*!< MVPOS (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLS10_MASK_S_MSCE_Pos           (5UL)    /*!< MSCE (Bit 5)                                          */
+ #define R_HDSLS10_MASK_S_MSCE_Msk           (0x20UL) /*!< MSCE (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS10_MASK_S_MSSUM_Pos          (6UL)    /*!< MSSUM (Bit 6)                                         */
+ #define R_HDSLS10_MASK_S_MSSUM_Msk          (0x40UL) /*!< MSSUM (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DUMMY  ========================================================= */
+ #define R_HDSLS10_DUMMY_DUMMY_Pos           (0UL)    /*!< DUMMY (Bit 0)                                         */
+ #define R_HDSLS10_DUMMY_DUMMY_Msk           (0xffUL) /*!< DUMMY (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ENC_ST  ========================================================= */
+ #define R_HDSLS10_ENC_ST_ENCST_Pos          (0UL)    /*!< ENCST (Bit 0)                                         */
+ #define R_HDSLS10_ENC_ST_ENCST_Msk          (0xffUL) /*!< ENCST (Bitfield-Mask: 0xff)                           */
+/* =========================================================  SRSSI  ========================================================= */
+ #define R_HDSLS10_SRSSI_SRSSI_Pos           (0UL)    /*!< SRSSI (Bit 0)                                         */
+ #define R_HDSLS10_SRSSI_SRSSI_Msk           (0x7UL)  /*!< SRSSI (Bitfield-Mask: 0x07)                           */
+/* =========================================================  MAIL  ========================================================== */
+ #define R_HDSLS10_MAIL_MAIL_Pos             (0UL)    /*!< MAIL (Bit 0)                                          */
+ #define R_HDSLS10_MAIL_MAIL_Msk             (0xffUL) /*!< MAIL (Bitfield-Mask: 0xff)                            */
+/* =========================================================  PING  ========================================================== */
+ #define R_HDSLS10_PING_PING_Pos             (0UL)    /*!< PING (Bit 0)                                          */
+ #define R_HDSLS10_PING_PING_Msk             (0xffUL) /*!< PING (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_HDSLS20                                         ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  VERSION2  ======================================================== */
+ #define R_HDSLS20_VERSION2_MINOR_Pos          (0UL)    /*!< MINOR (Bit 0)                                         */
+ #define R_HDSLS20_VERSION2_MINOR_Msk          (0xfUL)  /*!< MINOR (Bitfield-Mask: 0x0f)                           */
+ #define R_HDSLS20_VERSION2_MAJOR_Pos          (4UL)    /*!< MAJOR (Bit 4)                                         */
+ #define R_HDSLS20_VERSION2_MAJOR_Msk          (0x30UL) /*!< MAJOR (Bitfield-Mask: 0x03)                           */
+ #define R_HDSLS20_VERSION2_CODE_Pos           (6UL)    /*!< CODE (Bit 6)                                          */
+ #define R_HDSLS20_VERSION2_CODE_Msk           (0xc0UL) /*!< CODE (Bitfield-Mask: 0x03)                            */
+/* ========================================================  ENC2_ID  ======================================================== */
+ #define R_HDSLS20_ENC2_ID_ENC2ID_Pos          (0UL)    /*!< ENC2ID (Bit 0)                                        */
+ #define R_HDSLS20_ENC2_ID_ENC2ID_Msk          (0xffUL) /*!< ENC2ID (Bitfield-Mask: 0xff)                          */
+/* ========================================================  STATUS2  ======================================================== */
+ #define R_HDSLS20_STATUS2_FIX2_Pos            (0UL)    /*!< FIX2 (Bit 0)                                          */
+ #define R_HDSLS20_STATUS2_FIX2_Msk            (0x1fUL) /*!< FIX2 (Bitfield-Mask: 0x1f)                            */
+ #define R_HDSLS20_STATUS2_ERR2_Pos            (5UL)    /*!< ERR2 (Bit 5)                                          */
+ #define R_HDSLS20_STATUS2_ERR2_Msk            (0x20UL) /*!< ERR2 (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS20_STATUS2_TEST2_Pos           (6UL)    /*!< TEST2 (Bit 6)                                         */
+ #define R_HDSLS20_STATUS2_TEST2_Msk           (0x40UL) /*!< TEST2 (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLS20_STATUS2_TOG2_Pos            (7UL)    /*!< TOG2 (Bit 7)                                          */
+ #define R_HDSLS20_STATUS2_TOG2_Msk            (0x80UL) /*!< TOG2 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  VPOS24  ========================================================= */
+ #define R_HDSLS20_VPOS24_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS20_VPOS24_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  VPOS23  ========================================================= */
+ #define R_HDSLS20_VPOS23_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS20_VPOS23_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  VPOS22  ========================================================= */
+ #define R_HDSLS20_VPOS22_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS20_VPOS22_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  VPOS21  ========================================================= */
+ #define R_HDSLS20_VPOS21_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS20_VPOS21_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  VPOS20  ========================================================= */
+ #define R_HDSLS20_VPOS20_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS20_VPOS20_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ======================================================  VPOSCRC2_H  ======================================================= */
+ #define R_HDSLS20_VPOSCRC2_H_VPOSCRC2H_Pos    (0UL)    /*!< VPOSCRC2H (Bit 0)                                     */
+ #define R_HDSLS20_VPOSCRC2_H_VPOSCRC2H_Msk    (0xffUL) /*!< VPOSCRC2H (Bitfield-Mask: 0xff)                       */
+/* ======================================================  VPOSCRC2_L  ======================================================= */
+ #define R_HDSLS20_VPOSCRC2_L_VPOSCRC2L_Pos    (0UL)    /*!< VPOSCRC2L (Bit 0)                                     */
+ #define R_HDSLS20_VPOSCRC2_L_VPOSCRC2L_Msk    (0xffUL) /*!< VPOSCRC2L (Bitfield-Mask: 0xff)                       */
+/* ========================================================  DUMMY2  ========================================================= */
+ #define R_HDSLS20_DUMMY2_DUMMY_Pos            (0UL)    /*!< DUMMY (Bit 0)                                         */
+ #define R_HDSLS20_DUMMY2_DUMMY_Msk            (0xffUL) /*!< DUMMY (Bitfield-Mask: 0xff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_BISS0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  RDATA  ========================================================= */
+/* ========================================================  CNFSLV  ========================================================= */
+ #define R_BISS0_CNFSLV_SCDLEN_Pos           (0UL)          /*!< SCDLEN (Bit 0)                                        */
+ #define R_BISS0_CNFSLV_SCDLEN_Msk           (0x3fUL)       /*!< SCDLEN (Bitfield-Mask: 0x3f)                          */
+ #define R_BISS0_CNFSLV_ENSCD_Pos            (6UL)          /*!< ENSCD (Bit 6)                                         */
+ #define R_BISS0_CNFSLV_ENSCD_Msk            (0x40UL)       /*!< ENSCD (Bitfield-Mask: 0x01)                           */
+ #define R_BISS0_CNFSLV_GRAYS_Pos            (7UL)          /*!< GRAYS (Bit 7)                                         */
+ #define R_BISS0_CNFSLV_GRAYS_Msk            (0x80UL)       /*!< GRAYS (Bitfield-Mask: 0x01)                           */
+ #define R_BISS0_CNFSLV_SCRCLENPOLY_Pos      (8UL)          /*!< SCRCLENPOLY (Bit 8)                                   */
+ #define R_BISS0_CNFSLV_SCRCLENPOLY_Msk      (0x7f00UL)     /*!< SCRCLENPOLY (Bitfield-Mask: 0x7f)                     */
+ #define R_BISS0_CNFSLV_SELCRCS_Pos          (15UL)         /*!< SELCRCS (Bit 15)                                      */
+ #define R_BISS0_CNFSLV_SELCRCS_Msk          (0x8000UL)     /*!< SELCRCS (Bitfield-Mask: 0x01)                         */
+ #define R_BISS0_CNFSLV_SCRCSTART_Pos        (16UL)         /*!< SCRCSTART (Bit 16)                                    */
+ #define R_BISS0_CNFSLV_SCRCSTART_Msk        (0xffff0000UL) /*!< SCRCSTART (Bitfield-Mask: 0xffff)                     */
+/* ========================================================  REGACC  ========================================================= */
+ #define R_BISS0_REGACC_REGADR_Pos           (16UL)         /*!< REGADR (Bit 16)                                       */
+ #define R_BISS0_REGACC_REGADR_Msk           (0x7f0000UL)   /*!< REGADR (Bitfield-Mask: 0x7f)                          */
+ #define R_BISS0_REGACC_WNR_Pos              (23UL)         /*!< WNR (Bit 23)                                          */
+ #define R_BISS0_REGACC_WNR_Msk              (0x800000UL)   /*!< WNR (Bitfield-Mask: 0x01)                             */
+ #define R_BISS0_REGACC_REGNUM_Pos           (24UL)         /*!< REGNUM (Bit 24)                                       */
+ #define R_BISS0_REGACC_REGNUM_Msk           (0x3f000000UL) /*!< REGNUM (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  CTRLCOMM  ======================================================== */
+ #define R_BISS0_CTRLCOMM_HOLDCDM_Pos        (8UL)          /*!< HOLDCDM (Bit 8)                                       */
+ #define R_BISS0_CTRLCOMM_HOLDCDM_Msk        (0x100UL)      /*!< HOLDCDM (Bitfield-Mask: 0x01)                         */
+ #define R_BISS0_CTRLCOMM_SID_CMD_IDT_Pos    (11UL)         /*!< SID_CMD_IDT (Bit 11)                                  */
+ #define R_BISS0_CTRLCOMM_SID_CMD_IDT_Msk    (0x3800UL)     /*!< SID_CMD_IDT (Bitfield-Mask: 0x07)                     */
+ #define R_BISS0_CTRLCOMM_REGVERS_Pos        (14UL)         /*!< REGVERS (Bit 14)                                      */
+ #define R_BISS0_CTRLCOMM_REGVERS_Msk        (0x4000UL)     /*!< REGVERS (Bitfield-Mask: 0x01)                         */
+ #define R_BISS0_CTRLCOMM_CTS_Pos            (15UL)         /*!< CTS (Bit 15)                                          */
+ #define R_BISS0_CTRLCOMM_CTS_Msk            (0x8000UL)     /*!< CTS (Bitfield-Mask: 0x01)                             */
+ #define R_BISS0_CTRLCOMM_FREQS_Pos          (16UL)         /*!< FREQS (Bit 16)                                        */
+ #define R_BISS0_CTRLCOMM_FREQS_Msk          (0x1f0000UL)   /*!< FREQS (Bitfield-Mask: 0x1f)                           */
+ #define R_BISS0_CTRLCOMM_FREQR_Pos          (21UL)         /*!< FREQR (Bit 21)                                        */
+ #define R_BISS0_CTRLCOMM_FREQR_Msk          (0xe00000UL)   /*!< FREQR (Bitfield-Mask: 0x07)                           */
+ #define R_BISS0_CTRLCOMM_SINGLEBANK_Pos     (24UL)         /*!< SINGLEBANK (Bit 24)                                   */
+ #define R_BISS0_CTRLCOMM_SINGLEBANK_Msk     (0x1000000UL)  /*!< SINGLEBANK (Bitfield-Mask: 0x01)                      */
+ #define R_BISS0_CTRLCOMM_NOCRC_Pos          (25UL)         /*!< NOCRC (Bit 25)                                        */
+ #define R_BISS0_CTRLCOMM_NOCRC_Msk          (0x2000000UL)  /*!< NOCRC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  MSTRCNF  ======================================================== */
+ #define R_BISS0_MSTRCNF_FREQAGS_Pos         (0UL)          /*!< FREQAGS (Bit 0)                                       */
+ #define R_BISS0_MSTRCNF_FREQAGS_Msk         (0xffUL)       /*!< FREQAGS (Bitfield-Mask: 0xff)                         */
+ #define R_BISS0_MSTRCNF_REVISION_Pos        (16UL)         /*!< REVISION (Bit 16)                                     */
+ #define R_BISS0_MSTRCNF_REVISION_Msk        (0xff0000UL)   /*!< REVISION (Bitfield-Mask: 0xff)                        */
+ #define R_BISS0_MSTRCNF_VERSION_Pos         (24UL)         /*!< VERSION (Bit 24)                                      */
+ #define R_BISS0_MSTRCNF_VERSION_Msk         (0xff000000UL) /*!< VERSION (Bitfield-Mask: 0xff)                         */
+/* =========================================================  CHCNF  ========================================================= */
+ #define R_BISS0_CHCNF_CFGCH1_Pos            (8UL)          /*!< CFGCH1 (Bit 8)                                        */
+ #define R_BISS0_CHCNF_CFGCH1_Msk            (0x300UL)      /*!< CFGCH1 (Bitfield-Mask: 0x03)                          */
+/* =========================================================  STINF  ========================================================= */
+ #define R_BISS0_STINF_EOT_Pos               (0UL)          /*!< EOT (Bit 0)                                           */
+ #define R_BISS0_STINF_EOT_Msk               (0x1UL)        /*!< EOT (Bitfield-Mask: 0x01)                             */
+ #define R_BISS0_STINF_REGEND_Pos            (2UL)          /*!< REGEND (Bit 2)                                        */
+ #define R_BISS0_STINF_REGEND_Msk            (0x4UL)        /*!< REGEND (Bitfield-Mask: 0x01)                          */
+ #define R_BISS0_STINF_nREGERR_Pos           (3UL)          /*!< nREGERR (Bit 3)                                       */
+ #define R_BISS0_STINF_nREGERR_Msk           (0x8UL)        /*!< nREGERR (Bitfield-Mask: 0x01)                         */
+ #define R_BISS0_STINF_nSCDERR_Pos           (4UL)          /*!< nSCDERR (Bit 4)                                       */
+ #define R_BISS0_STINF_nSCDERR_Msk           (0x10UL)       /*!< nSCDERR (Bitfield-Mask: 0x01)                         */
+ #define R_BISS0_STINF_nDELAYERR_Pos         (5UL)          /*!< nDELAYERR (Bit 5)                                     */
+ #define R_BISS0_STINF_nDELAYERR_Msk         (0x20UL)       /*!< nDELAYERR (Bitfield-Mask: 0x01)                       */
+ #define R_BISS0_STINF_nAGSERR_Pos           (6UL)          /*!< nAGSERR (Bit 6)                                       */
+ #define R_BISS0_STINF_nAGSERR_Msk           (0x40UL)       /*!< nAGSERR (Bitfield-Mask: 0x01)                         */
+ #define R_BISS0_STINF_nERR_Pos              (7UL)          /*!< nERR (Bit 7)                                          */
+ #define R_BISS0_STINF_nERR_Msk              (0x80UL)       /*!< nERR (Bitfield-Mask: 0x01)                            */
+ #define R_BISS0_STINF_SVALID_Pos            (8UL)          /*!< SVALID (Bit 8)                                        */
+ #define R_BISS0_STINF_SVALID_Msk            (0xffff00UL)   /*!< SVALID (Bitfield-Mask: 0xffff)                        */
+ #define R_BISS0_STINF_REGBYTES_Pos          (24UL)         /*!< REGBYTES (Bit 24)                                     */
+ #define R_BISS0_STINF_REGBYTES_Msk          (0x3f000000UL) /*!< REGBYTES (Bitfield-Mask: 0x3f)                        */
+ #define R_BISS0_STINF_CDSSEL_Pos            (30UL)         /*!< CDSSEL (Bit 30)                                       */
+ #define R_BISS0_STINF_CDSSEL_Msk            (0x40000000UL) /*!< CDSSEL (Bitfield-Mask: 0x01)                          */
+ #define R_BISS0_STINF_CDMTIMEOUT_Pos        (31UL)         /*!< CDMTIMEOUT (Bit 31)                                   */
+ #define R_BISS0_STINF_CDMTIMEOUT_Msk        (0x80000000UL) /*!< CDMTIMEOUT (Bitfield-Mask: 0x01)                      */
+/* ========================================================  INSTREG  ======================================================== */
+ #define R_BISS0_INSTREG_AGS_Pos             (0UL)          /*!< AGS (Bit 0)                                           */
+ #define R_BISS0_INSTREG_AGS_Msk             (0x1UL)        /*!< AGS (Bitfield-Mask: 0x01)                             */
+ #define R_BISS0_INSTREG_INSTR_Pos           (1UL)          /*!< INSTR (Bit 1)                                         */
+ #define R_BISS0_INSTREG_INSTR_Msk           (0xeUL)        /*!< INSTR (Bitfield-Mask: 0x07)                           */
+ #define R_BISS0_INSTREG_INIT_Pos            (4UL)          /*!< INIT (Bit 4)                                          */
+ #define R_BISS0_INSTREG_INIT_Msk            (0x10UL)       /*!< INIT (Bitfield-Mask: 0x01)                            */
+ #define R_BISS0_INSTREG_SWBANK_Pos          (5UL)          /*!< SWBANK (Bit 5)                                        */
+ #define R_BISS0_INSTREG_SWBANK_Msk          (0x20UL)       /*!< SWBANK (Bitfield-Mask: 0x01)                          */
+ #define R_BISS0_INSTREG_HOLDBANK_Pos        (6UL)          /*!< HOLDBANK (Bit 6)                                      */
+ #define R_BISS0_INSTREG_HOLDBANK_Msk        (0x40UL)       /*!< HOLDBANK (Bitfield-Mask: 0x01)                        */
+ #define R_BISS0_INSTREG_BREAK_Pos           (7UL)          /*!< BREAK (Bit 7)                                         */
+ #define R_BISS0_INSTREG_BREAK_Msk           (0x80UL)       /*!< BREAK (Bitfield-Mask: 0x01)                           */
+ #define R_BISS0_INSTREG_MAFS_Pos            (12UL)         /*!< MAFS (Bit 12)                                         */
+ #define R_BISS0_INSTREG_MAFS_Msk            (0x1000UL)     /*!< MAFS (Bitfield-Mask: 0x01)                            */
+ #define R_BISS0_INSTREG_MAVS_Pos            (13UL)         /*!< MAVS (Bit 13)                                         */
+ #define R_BISS0_INSTREG_MAVS_Msk            (0x2000UL)     /*!< MAVS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  STINF2  ========================================================= */
+ #define R_BISS0_STINF2_SL1_Pos              (0UL)          /*!< SL1 (Bit 0)                                           */
+ #define R_BISS0_STINF2_SL1_Msk              (0x1UL)        /*!< SL1 (Bitfield-Mask: 0x01)                             */
+ #define R_BISS0_STINF2_CDS1_Pos             (1UL)          /*!< CDS1 (Bit 1)                                          */
+ #define R_BISS0_STINF2_CDS1_Msk             (0x2UL)        /*!< CDS1 (Bitfield-Mask: 0x01)                            */
+ #define R_BISS0_STINF2_IDL_Pos              (16UL)         /*!< IDL (Bit 16)                                          */
+ #define R_BISS0_STINF2_IDL_Msk              (0xf0000UL)    /*!< IDL (Bitfield-Mask: 0x0f)                             */
+ #define R_BISS0_STINF2_SWBANKFAIL_Pos       (24UL)         /*!< SWBANKFAIL (Bit 24)                                   */
+ #define R_BISS0_STINF2_SWBANKFAIL_Msk       (0x1000000UL)  /*!< SWBANKFAIL (Bitfield-Mask: 0x01)                      */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ENDAT0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SEND  ========================================================== */
+ #define R_ENDAT0_SEND_D_Pos               (0UL)          /*!< D (Bit 0)                                             */
+ #define R_ENDAT0_SEND_D_Msk               (0xffffUL)     /*!< D (Bitfield-Mask: 0xffff)                             */
+ #define R_ENDAT0_SEND_A_Pos               (16UL)         /*!< A (Bit 16)                                            */
+ #define R_ENDAT0_SEND_A_Msk               (0xff0000UL)   /*!< A (Bitfield-Mask: 0xff)                               */
+ #define R_ENDAT0_SEND_M_Pos               (24UL)         /*!< M (Bit 24)                                            */
+ #define R_ENDAT0_SEND_M_Msk               (0x3f000000UL) /*!< M (Bitfield-Mask: 0x3f)                               */
+/* =======================================================  EMPFR1_L  ======================================================== */
+ #define R_ENDAT0_EMPFR1_L_RDATA_L_Pos     (0UL)          /*!< RDATA_L (Bit 0)                                       */
+ #define R_ENDAT0_EMPFR1_L_RDATA_L_Msk     (0xffffffffUL) /*!< RDATA_L (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  EMPFR1_H  ======================================================== */
+ #define R_ENDAT0_EMPFR1_H_RDATA_H_Pos     (0UL)          /*!< RDATA_H (Bit 0)                                       */
+ #define R_ENDAT0_EMPFR1_H_RDATA_H_Msk     (0xffffUL)     /*!< RDATA_H (Bitfield-Mask: 0xffff)                       */
+ #define R_ENDAT0_EMPFR1_H_CRC_Pos         (16UL)         /*!< CRC (Bit 16)                                          */
+ #define R_ENDAT0_EMPFR1_H_CRC_Msk         (0x1f0000UL)   /*!< CRC (Bitfield-Mask: 0x1f)                             */
+ #define R_ENDAT0_EMPFR1_H_F1_Pos          (21UL)         /*!< F1 (Bit 21)                                           */
+ #define R_ENDAT0_EMPFR1_H_F1_Msk          (0x200000UL)   /*!< F1 (Bitfield-Mask: 0x01)                              */
+ #define R_ENDAT0_EMPFR1_H_IF2_Pos         (22UL)         /*!< IF2 (Bit 22)                                          */
+ #define R_ENDAT0_EMPFR1_H_IF2_Msk         (0x400000UL)   /*!< IF2 (Bitfield-Mask: 0x01)                             */
+ #define R_ENDAT0_EMPFR1_H_POS1_Pos        (23UL)         /*!< POS1 (Bit 23)                                         */
+ #define R_ENDAT0_EMPFR1_H_POS1_Msk        (0x800000UL)   /*!< POS1 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  EMPFR2  ========================================================= */
+ #define R_ENDAT0_EMPFR2_RDATA2_Pos        (0UL)          /*!< RDATA2 (Bit 0)                                        */
+ #define R_ENDAT0_EMPFR2_RDATA2_Msk        (0xffffffffUL) /*!< RDATA2 (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  EMPFR3  ========================================================= */
+ #define R_ENDAT0_EMPFR3_D_Pos             (0UL)          /*!< D (Bit 0)                                             */
+ #define R_ENDAT0_EMPFR3_D_Msk             (0xffffUL)     /*!< D (Bitfield-Mask: 0xffff)                             */
+ #define R_ENDAT0_EMPFR3_C_Pos             (16UL)         /*!< C (Bit 16)                                            */
+ #define R_ENDAT0_EMPFR3_C_Msk             (0xff0000UL)   /*!< C (Bitfield-Mask: 0xff)                               */
+ #define R_ENDAT0_EMPFR3_CRC_Pos           (24UL)         /*!< CRC (Bit 24)                                          */
+ #define R_ENDAT0_EMPFR3_CRC_Msk           (0x1f000000UL) /*!< CRC (Bitfield-Mask: 0x1f)                             */
+/* ========================================================  KONFR1  ========================================================= */
+ #define R_ENDAT0_KONFR1_HWSTRB_Pos        (0UL)          /*!< HWSTRB (Bit 0)                                        */
+ #define R_ENDAT0_KONFR1_HWSTRB_Msk        (0x1UL)        /*!< HWSTRB (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_KONFR1_DU_Pos            (1UL)          /*!< DU (Bit 1)                                            */
+ #define R_ENDAT0_KONFR1_DU_Msk            (0x2UL)        /*!< DU (Bitfield-Mask: 0x01)                              */
+ #define R_ENDAT0_KONFR1_DT_Pos            (2UL)          /*!< DT (Bit 2)                                            */
+ #define R_ENDAT0_KONFR1_DT_Msk            (0x4UL)        /*!< DT (Bitfield-Mask: 0x01)                              */
+ #define R_ENDAT0_KONFR1_FTCLK_Pos         (4UL)          /*!< FTCLK (Bit 4)                                         */
+ #define R_ENDAT0_KONFR1_FTCLK_Msk         (0xf0UL)       /*!< FTCLK (Bitfield-Mask: 0x0f)                           */
+ #define R_ENDAT0_KONFR1_DWLG_Pos          (8UL)          /*!< DWLG (Bit 8)                                          */
+ #define R_ENDAT0_KONFR1_DWLG_Msk          (0x3f00UL)     /*!< DWLG (Bitfield-Mask: 0x3f)                            */
+ #define R_ENDAT0_KONFR1_RSTWD_Pos         (14UL)         /*!< RSTWD (Bit 14)                                        */
+ #define R_ENDAT0_KONFR1_RSTWD_Msk         (0x4000UL)     /*!< RSTWD (Bitfield-Mask: 0x01)                           */
+ #define R_ENDAT0_KONFR1_AUTORST_Pos       (15UL)         /*!< AUTORST (Bit 15)                                      */
+ #define R_ENDAT0_KONFR1_AUTORST_Msk       (0x8000UL)     /*!< AUTORST (Bitfield-Mask: 0x01)                         */
+ #define R_ENDAT0_KONFR1_CPTIME_Pos        (16UL)         /*!< CPTIME (Bit 16)                                       */
+ #define R_ENDAT0_KONFR1_CPTIME_Msk        (0xff0000UL)   /*!< CPTIME (Bitfield-Mask: 0xff)                          */
+ #define R_ENDAT0_KONFR1_DELAYCMP_Pos      (24UL)         /*!< DELAYCMP (Bit 24)                                     */
+ #define R_ENDAT0_KONFR1_DELAYCMP_Msk      (0x1000000UL)  /*!< DELAYCMP (Bitfield-Mask: 0x01)                        */
+ #define R_ENDAT0_KONFR1_FSYS_Pos          (26UL)         /*!< FSYS (Bit 26)                                         */
+ #define R_ENDAT0_KONFR1_FSYS_Msk          (0x1c000000UL) /*!< FSYS (Bitfield-Mask: 0x07)                            */
+ #define R_ENDAT0_KONFR1_ICRST_Pos         (29UL)         /*!< ICRST (Bit 29)                                        */
+ #define R_ENDAT0_KONFR1_ICRST_Msk         (0x20000000UL) /*!< ICRST (Bitfield-Mask: 0x01)                           */
+ #define R_ENDAT0_KONFR1_SET_Pos           (30UL)         /*!< SET (Bit 30)                                          */
+ #define R_ENDAT0_KONFR1_SET_Msk           (0xc0000000UL) /*!< SET (Bitfield-Mask: 0x03)                             */
+/* ========================================================  KONFR2  ========================================================= */
+ #define R_ENDAT0_KONFR2_TMSMPLRATE_Pos    (0UL)          /*!< TMSMPLRATE (Bit 0)                                    */
+ #define R_ENDAT0_KONFR2_TMSMPLRATE_Msk    (0xffUL)       /*!< TMSMPLRATE (Bitfield-Mask: 0xff)                      */
+ #define R_ENDAT0_KONFR2_WTDOG_Pos         (8UL)          /*!< WTDOG (Bit 8)                                         */
+ #define R_ENDAT0_KONFR2_WTDOG_Msk         (0xff00UL)     /*!< WTDOG (Bitfield-Mask: 0xff)                           */
+ #define R_ENDAT0_KONFR2_RCVTIME_Pos       (16UL)         /*!< RCVTIME (Bit 16)                                      */
+ #define R_ENDAT0_KONFR2_RCVTIME_Msk       (0x70000UL)    /*!< RCVTIME (Bitfield-Mask: 0x07)                         */
+ #define R_ENDAT0_KONFR2_FILTER_Pos        (19UL)         /*!< FILTER (Bit 19)                                       */
+ #define R_ENDAT0_KONFR2_FILTER_Msk        (0x380000UL)   /*!< FILTER (Bitfield-Mask: 0x07)                          */
+ #define R_ENDAT0_KONFR2_HWSTRBDLY_Pos     (24UL)         /*!< HWSTRBDLY (Bit 24)                                    */
+ #define R_ENDAT0_KONFR2_HWSTRBDLY_Msk     (0xff000000UL) /*!< HWSTRBDLY (Bitfield-Mask: 0xff)                       */
+/* =========================================================  STATR  ========================================================= */
+ #define R_ENDAT0_STATR_EMPFR1_Pos         (0UL)          /*!< EMPFR1 (Bit 0)                                        */
+ #define R_ENDAT0_STATR_EMPFR1_Msk         (0x1UL)        /*!< EMPFR1 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_STATR_ERR1_Pos           (1UL)          /*!< ERR1 (Bit 1)                                          */
+ #define R_ENDAT0_STATR_ERR1_Msk           (0x2UL)        /*!< ERR1 (Bitfield-Mask: 0x01)                            */
+ #define R_ENDAT0_STATR_CRC_PRTY_Pos       (2UL)          /*!< CRC_PRTY (Bit 2)                                      */
+ #define R_ENDAT0_STATR_CRC_PRTY_Msk       (0x4UL)        /*!< CRC_PRTY (Bitfield-Mask: 0x01)                        */
+ #define R_ENDAT0_STATR_FTYPI_Pos          (3UL)          /*!< FTYPI (Bit 3)                                         */
+ #define R_ENDAT0_STATR_FTYPI_Msk          (0x8UL)        /*!< FTYPI (Bitfield-Mask: 0x01)                           */
+ #define R_ENDAT0_STATR_FTYPII_Pos         (4UL)          /*!< FTYPII (Bit 4)                                        */
+ #define R_ENDAT0_STATR_FTYPII_Msk         (0x10UL)       /*!< FTYPII (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_STATR_MRS_ADR_Pos        (5UL)          /*!< MRS_ADR (Bit 5)                                       */
+ #define R_ENDAT0_STATR_MRS_ADR_Msk        (0x20UL)       /*!< MRS_ADR (Bitfield-Mask: 0x01)                         */
+ #define R_ENDAT0_STATR_EMPFR2_Pos         (8UL)          /*!< EMPFR2 (Bit 8)                                        */
+ #define R_ENDAT0_STATR_EMPFR2_Msk         (0x100UL)      /*!< EMPFR2 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_STATR_EMPFR3_Pos         (9UL)          /*!< EMPFR3 (Bit 9)                                        */
+ #define R_ENDAT0_STATR_EMPFR3_Msk         (0x200UL)      /*!< EMPFR3 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_STATR_IERR2_Pos          (10UL)         /*!< IERR2 (Bit 10)                                        */
+ #define R_ENDAT0_STATR_IERR2_Msk          (0x400UL)      /*!< IERR2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENDAT0_STATR_CRCZI1_Pos         (11UL)         /*!< CRCZI1 (Bit 11)                                       */
+ #define R_ENDAT0_STATR_CRCZI1_Msk         (0x800UL)      /*!< CRCZI1 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_STATR_CRCZI2_Pos         (12UL)         /*!< CRCZI2 (Bit 12)                                       */
+ #define R_ENDAT0_STATR_CRCZI2_Msk         (0x1000UL)     /*!< CRCZI2 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_STATR_BUSY_Pos           (13UL)         /*!< BUSY (Bit 13)                                         */
+ #define R_ENDAT0_STATR_BUSY_Msk           (0x2000UL)     /*!< BUSY (Bitfield-Mask: 0x01)                            */
+ #define R_ENDAT0_STATR_RM_Pos             (14UL)         /*!< RM (Bit 14)                                           */
+ #define R_ENDAT0_STATR_RM_Msk             (0x4000UL)     /*!< RM (Bitfield-Mask: 0x01)                              */
+ #define R_ENDAT0_STATR_WRN_Pos            (15UL)         /*!< WRN (Bit 15)                                          */
+ #define R_ENDAT0_STATR_WRN_Msk            (0x8000UL)     /*!< WRN (Bitfield-Mask: 0x01)                             */
+ #define R_ENDAT0_STATR_SPIKE_Pos          (16UL)         /*!< SPIKE (Bit 16)                                        */
+ #define R_ENDAT0_STATR_SPIKE_Msk          (0x10000UL)    /*!< SPIKE (Bitfield-Mask: 0x01)                           */
+ #define R_ENDAT0_STATR_WTDG_Pos           (17UL)         /*!< WTDG (Bit 17)                                         */
+ #define R_ENDAT0_STATR_WTDG_Msk           (0x20000UL)    /*!< WTDG (Bitfield-Mask: 0x01)                            */
+ #define R_ENDAT0_STATR_FTYPIII_Pos        (18UL)         /*!< FTYPIII (Bit 18)                                      */
+ #define R_ENDAT0_STATR_FTYPIII_Msk        (0x40000UL)    /*!< FTYPIII (Bitfield-Mask: 0x01)                         */
+ #define R_ENDAT0_STATR_LZK_Pos            (22UL)         /*!< LZK (Bit 22)                                          */
+ #define R_ENDAT0_STATR_LZK_Msk            (0x400000UL)   /*!< LZK (Bitfield-Mask: 0x01)                             */
+ #define R_ENDAT0_STATR_LZM_Pos            (23UL)         /*!< LZM (Bit 23)                                          */
+ #define R_ENDAT0_STATR_LZM_Msk            (0x800000UL)   /*!< LZM (Bitfield-Mask: 0x01)                             */
+ #define R_ENDAT0_STATR_SPDRDY_Pos         (29UL)         /*!< SPDRDY (Bit 29)                                       */
+ #define R_ENDAT0_STATR_SPDRDY_Msk         (0x20000000UL) /*!< SPDRDY (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_STATR_RDY4STRB_Pos       (30UL)         /*!< RDY4STRB (Bit 30)                                     */
+ #define R_ENDAT0_STATR_RDY4STRB_Msk       (0x40000000UL) /*!< RDY4STRB (Bitfield-Mask: 0x01)                        */
+ #define R_ENDAT0_STATR_RDY_Pos            (31UL)         /*!< RDY (Bit 31)                                          */
+ #define R_ENDAT0_STATR_RDY_Msk            (0x80000000UL) /*!< RDY (Bitfield-Mask: 0x01)                             */
+/* =========================================================  INTMR  ========================================================= */
+ #define R_ENDAT0_INTMR_EMPFR1_Pos         (0UL)          /*!< EMPFR1 (Bit 0)                                        */
+ #define R_ENDAT0_INTMR_EMPFR1_Msk         (0x1UL)        /*!< EMPFR1 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_INTMR_ERR1_Pos           (1UL)          /*!< ERR1 (Bit 1)                                          */
+ #define R_ENDAT0_INTMR_ERR1_Msk           (0x2UL)        /*!< ERR1 (Bitfield-Mask: 0x01)                            */
+ #define R_ENDAT0_INTMR_CRC_PRTY_Pos       (2UL)          /*!< CRC_PRTY (Bit 2)                                      */
+ #define R_ENDAT0_INTMR_CRC_PRTY_Msk       (0x4UL)        /*!< CRC_PRTY (Bitfield-Mask: 0x01)                        */
+ #define R_ENDAT0_INTMR_FTYPI_Pos          (3UL)          /*!< FTYPI (Bit 3)                                         */
+ #define R_ENDAT0_INTMR_FTYPI_Msk          (0x8UL)        /*!< FTYPI (Bitfield-Mask: 0x01)                           */
+ #define R_ENDAT0_INTMR_FTYPII_Pos         (4UL)          /*!< FTYPII (Bit 4)                                        */
+ #define R_ENDAT0_INTMR_FTYPII_Msk         (0x10UL)       /*!< FTYPII (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_INTMR_MRS_ADR_Pos        (5UL)          /*!< MRS_ADR (Bit 5)                                       */
+ #define R_ENDAT0_INTMR_MRS_ADR_Msk        (0x20UL)       /*!< MRS_ADR (Bitfield-Mask: 0x01)                         */
+ #define R_ENDAT0_INTMR_EMPFR2_Pos         (8UL)          /*!< EMPFR2 (Bit 8)                                        */
+ #define R_ENDAT0_INTMR_EMPFR2_Msk         (0x100UL)      /*!< EMPFR2 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_INTMR_EMPFR3_Pos         (9UL)          /*!< EMPFR3 (Bit 9)                                        */
+ #define R_ENDAT0_INTMR_EMPFR3_Msk         (0x200UL)      /*!< EMPFR3 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_INTMR_IERR2_Pos          (10UL)         /*!< IERR2 (Bit 10)                                        */
+ #define R_ENDAT0_INTMR_IERR2_Msk          (0x400UL)      /*!< IERR2 (Bitfield-Mask: 0x01)                           */
+ #define R_ENDAT0_INTMR_CRCZI1_Pos         (11UL)         /*!< CRCZI1 (Bit 11)                                       */
+ #define R_ENDAT0_INTMR_CRCZI1_Msk         (0x800UL)      /*!< CRCZI1 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_INTMR_CRCZI2_Pos         (12UL)         /*!< CRCZI2 (Bit 12)                                       */
+ #define R_ENDAT0_INTMR_CRCZI2_Msk         (0x1000UL)     /*!< CRCZI2 (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_INTMR_BUSY_Pos           (13UL)         /*!< BUSY (Bit 13)                                         */
+ #define R_ENDAT0_INTMR_BUSY_Msk           (0x2000UL)     /*!< BUSY (Bitfield-Mask: 0x01)                            */
+ #define R_ENDAT0_INTMR_RM_Pos             (14UL)         /*!< RM (Bit 14)                                           */
+ #define R_ENDAT0_INTMR_RM_Msk             (0x4000UL)     /*!< RM (Bitfield-Mask: 0x01)                              */
+ #define R_ENDAT0_INTMR_WRN_Pos            (15UL)         /*!< WRN (Bit 15)                                          */
+ #define R_ENDAT0_INTMR_WRN_Msk            (0x8000UL)     /*!< WRN (Bitfield-Mask: 0x01)                             */
+ #define R_ENDAT0_INTMR_SPIKE_Pos          (16UL)         /*!< SPIKE (Bit 16)                                        */
+ #define R_ENDAT0_INTMR_SPIKE_Msk          (0x10000UL)    /*!< SPIKE (Bitfield-Mask: 0x01)                           */
+ #define R_ENDAT0_INTMR_WTDG_Pos           (17UL)         /*!< WTDG (Bit 17)                                         */
+ #define R_ENDAT0_INTMR_WTDG_Msk           (0x20000UL)    /*!< WTDG (Bitfield-Mask: 0x01)                            */
+ #define R_ENDAT0_INTMR_FTYPIII_Pos        (18UL)         /*!< FTYPIII (Bit 18)                                      */
+ #define R_ENDAT0_INTMR_FTYPIII_Msk        (0x40000UL)    /*!< FTYPIII (Bitfield-Mask: 0x01)                         */
+ #define R_ENDAT0_INTMR_SPDRDY_Pos         (29UL)         /*!< SPDRDY (Bit 29)                                       */
+ #define R_ENDAT0_INTMR_SPDRDY_Msk         (0x20000000UL) /*!< SPDRDY (Bitfield-Mask: 0x01)                          */
+ #define R_ENDAT0_INTMR_RDY_Pos            (31UL)         /*!< RDY (Bit 31)                                          */
+ #define R_ENDAT0_INTMR_RDY_Msk            (0x80000000UL) /*!< RDY (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SWSTRBR  ======================================================== */
+/* ==========================================================  IDR  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_AFMT0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  COMMAND  ======================================================== */
+ #define R_AFMT0_COMMAND_XEA_Pos         (0UL)          /*!< XEA (Bit 0)                                           */
+ #define R_AFMT0_COMMAND_XEA_Msk         (0x7UL)        /*!< XEA (Bitfield-Mask: 0x07)                             */
+ #define R_AFMT0_COMMAND_CC_Pos          (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_AFMT0_COMMAND_CC_Msk          (0xf8UL)       /*!< CC (Bitfield-Mask: 0x1f)                              */
+ #define R_AFMT0_COMMAND_SID_Pos         (8UL)          /*!< SID (Bit 8)                                           */
+ #define R_AFMT0_COMMAND_SID_Msk         (0x1f00UL)     /*!< SID (Bitfield-Mask: 0x1f)                             */
+/* ======================================================  ENC1RXDATA0  ====================================================== */
+ #define R_AFMT0_ENC1RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC1RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA0  ====================================================== */
+ #define R_AFMT0_ENC2RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC2RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA0  ====================================================== */
+ #define R_AFMT0_ENC3RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC3RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA0  ====================================================== */
+ #define R_AFMT0_ENC4RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC4RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA0  ====================================================== */
+ #define R_AFMT0_ENC5RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC5RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA0  ====================================================== */
+ #define R_AFMT0_ENC6RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC6RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA0  ====================================================== */
+ #define R_AFMT0_ENC7RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC7RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA0  ====================================================== */
+ #define R_AFMT0_ENC8RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC8RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA1  ====================================================== */
+ #define R_AFMT0_ENC1RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC1RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA1  ====================================================== */
+ #define R_AFMT0_ENC2RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC2RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA1  ====================================================== */
+ #define R_AFMT0_ENC3RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC3RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA1  ====================================================== */
+ #define R_AFMT0_ENC4RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC4RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA1  ====================================================== */
+ #define R_AFMT0_ENC5RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC5RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA1  ====================================================== */
+ #define R_AFMT0_ENC6RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC6RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA1  ====================================================== */
+ #define R_AFMT0_ENC7RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC7RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA1  ====================================================== */
+ #define R_AFMT0_ENC8RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC8RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  ROMDATA  ======================================================== */
+ #define R_AFMT0_ROMDATA_DATA_Pos        (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ROMDATA_DATA_Msk        (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
+ #define R_AFMT0_ROMDATA_ADDR_Pos        (16UL)         /*!< ADDR (Bit 16)                                         */
+ #define R_AFMT0_ROMDATA_ADDR_Msk        (0xff0000UL)   /*!< ADDR (Bitfield-Mask: 0xff)                            */
+/* ======================================================  ENC1RXDATA2  ====================================================== */
+ #define R_AFMT0_ENC1RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC1RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA2  ====================================================== */
+ #define R_AFMT0_ENC2RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC2RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA2  ====================================================== */
+ #define R_AFMT0_ENC3RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC3RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA2  ====================================================== */
+ #define R_AFMT0_ENC4RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC4RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA2  ====================================================== */
+ #define R_AFMT0_ENC5RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC5RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA2  ====================================================== */
+ #define R_AFMT0_ENC6RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC6RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA2  ====================================================== */
+ #define R_AFMT0_ENC7RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC7RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA2  ====================================================== */
+ #define R_AFMT0_ENC8RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC8RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ==========================================================  ID  =========================================================== */
+ #define R_AFMT0_ID_ID_L_Pos             (0UL)          /*!< ID_L (Bit 0)                                          */
+ #define R_AFMT0_ID_ID_L_Msk             (0xffffUL)     /*!< ID_L (Bitfield-Mask: 0xffff)                          */
+ #define R_AFMT0_ID_ID_H_Pos             (16UL)         /*!< ID_H (Bit 16)                                         */
+ #define R_AFMT0_ID_ID_H_Msk             (0xff0000UL)   /*!< ID_H (Bitfield-Mask: 0xff)                            */
+/* ======================================================  ENC1RXDATA3  ====================================================== */
+ #define R_AFMT0_ENC1RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC1RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA3  ====================================================== */
+ #define R_AFMT0_ENC2RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC2RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA3  ====================================================== */
+ #define R_AFMT0_ENC3RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC3RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA3  ====================================================== */
+ #define R_AFMT0_ENC4RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC4RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA3  ====================================================== */
+ #define R_AFMT0_ENC5RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC5RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA3  ====================================================== */
+ #define R_AFMT0_ENC6RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC6RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA3  ====================================================== */
+ #define R_AFMT0_ENC7RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC7RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA3  ====================================================== */
+ #define R_AFMT0_ENC8RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC8RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA4  ====================================================== */
+ #define R_AFMT0_ENC1RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC1RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA4  ====================================================== */
+ #define R_AFMT0_ENC2RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC2RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA4  ====================================================== */
+ #define R_AFMT0_ENC3RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC3RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA4  ====================================================== */
+ #define R_AFMT0_ENC4RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC4RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA4  ====================================================== */
+ #define R_AFMT0_ENC5RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC5RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA4  ====================================================== */
+ #define R_AFMT0_ENC6RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC6RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA4  ====================================================== */
+ #define R_AFMT0_ENC7RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC7RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA4  ====================================================== */
+ #define R_AFMT0_ENC8RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC8RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA5  ====================================================== */
+ #define R_AFMT0_ENC1RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC1RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA5  ====================================================== */
+ #define R_AFMT0_ENC2RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC2RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA5  ====================================================== */
+ #define R_AFMT0_ENC3RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC3RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA5  ====================================================== */
+ #define R_AFMT0_ENC4RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC4RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA5  ====================================================== */
+ #define R_AFMT0_ENC5RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC5RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA5  ====================================================== */
+ #define R_AFMT0_ENC6RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC6RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA5  ====================================================== */
+ #define R_AFMT0_ENC7RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC7RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA5  ====================================================== */
+ #define R_AFMT0_ENC8RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC8RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA6  ====================================================== */
+ #define R_AFMT0_ENC1RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC1RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA6  ====================================================== */
+ #define R_AFMT0_ENC2RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC2RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA6  ====================================================== */
+ #define R_AFMT0_ENC3RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC3RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA6  ====================================================== */
+ #define R_AFMT0_ENC4RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC4RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA6  ====================================================== */
+ #define R_AFMT0_ENC5RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC5RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA6  ====================================================== */
+ #define R_AFMT0_ENC6RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC6RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA6  ====================================================== */
+ #define R_AFMT0_ENC7RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC7RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA6  ====================================================== */
+ #define R_AFMT0_ENC8RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC8RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA7  ====================================================== */
+ #define R_AFMT0_ENC1RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC1RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA7  ====================================================== */
+ #define R_AFMT0_ENC2RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC2RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA7  ====================================================== */
+ #define R_AFMT0_ENC3RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC3RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA7  ====================================================== */
+ #define R_AFMT0_ENC4RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC4RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA7  ====================================================== */
+ #define R_AFMT0_ENC5RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC5RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA7  ====================================================== */
+ #define R_AFMT0_ENC6RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC6RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA7  ====================================================== */
+ #define R_AFMT0_ENC7RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC7RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA7  ====================================================== */
+ #define R_AFMT0_ENC8RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT0_ENC8RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  TRGSEL  ========================================================= */
+ #define R_AFMT0_TRGSEL_EXT_Pos          (0UL)          /*!< EXT (Bit 0)                                           */
+ #define R_AFMT0_TRGSEL_EXT_Msk          (0x1UL)        /*!< EXT (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TXTRG  ========================================================= */
+ #define R_AFMT0_TXTRG_TRG_Pos           (0UL)          /*!< TRG (Bit 0)                                           */
+ #define R_AFMT0_TXTRG_TRG_Msk           (0x1UL)        /*!< TRG (Bitfield-Mask: 0x01)                             */
+/* =========================================================  BRSEL  ========================================================= */
+ #define R_AFMT0_BRSEL_BR_Pos            (0UL)          /*!< BR (Bit 0)                                            */
+ #define R_AFMT0_BRSEL_BR_Msk            (0x7UL)        /*!< BR (Bitfield-Mask: 0x07)                              */
+ #define R_AFMT0_BRSEL_AS_Pos            (3UL)          /*!< AS (Bit 3)                                            */
+ #define R_AFMT0_BRSEL_AS_Msk            (0x8UL)        /*!< AS (Bitfield-Mask: 0x01)                              */
+ #define R_AFMT0_BRSEL_TM_Pos            (4UL)          /*!< TM (Bit 4)                                            */
+ #define R_AFMT0_BRSEL_TM_Msk            (0xff0UL)      /*!< TM (Bitfield-Mask: 0xff)                              */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ENCOUT                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CTL  ========================================================== */
+ #define R_ENCOUT_CTL_POL_Pos                 (0UL)          /*!< POL (Bit 0)                                           */
+ #define R_ENCOUT_CTL_POL_Msk                 (0x1UL)        /*!< POL (Bitfield-Mask: 0x01)                             */
+ #define R_ENCOUT_CTL_ZW_Pos                  (1UL)          /*!< ZW (Bit 1)                                            */
+ #define R_ENCOUT_CTL_ZW_Msk                  (0xeUL)        /*!< ZW (Bitfield-Mask: 0x07)                              */
+ #define R_ENCOUT_CTL_ZS_Pos                  (4UL)          /*!< ZS (Bit 4)                                            */
+ #define R_ENCOUT_CTL_ZS_Msk                  (0x10UL)       /*!< ZS (Bitfield-Mask: 0x01)                              */
+/* ==========================================================  STR  ========================================================== */
+ #define R_ENCOUT_STR_ENCE_Pos                (0UL)          /*!< ENCE (Bit 0)                                          */
+ #define R_ENCOUT_STR_ENCE_Msk                (0x1UL)        /*!< ENCE (Bitfield-Mask: 0x01)                            */
+/* =====================================================  POSMAX_PERIOD  ===================================================== */
+ #define R_ENCOUT_POSMAX_PERIOD_PERIOD_Pos    (0UL)          /*!< PERIOD (Bit 0)                                        */
+ #define R_ENCOUT_POSMAX_PERIOD_PERIOD_Msk    (0xffffUL)     /*!< PERIOD (Bitfield-Mask: 0xffff)                        */
+ #define R_ENCOUT_POSMAX_PERIOD_POSMAX_Pos    (16UL)         /*!< POSMAX (Bit 16)                                       */
+ #define R_ENCOUT_POSMAX_PERIOD_POSMAX_Msk    (0xffff0000UL) /*!< POSMAX (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  OUTCNT  ========================================================= */
+ #define R_ENCOUT_OUTCNT_EDGCNT_Pos           (0UL)          /*!< EDGCNT (Bit 0)                                        */
+ #define R_ENCOUT_OUTCNT_EDGCNT_Msk           (0xffffUL)     /*!< EDGCNT (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  POSCNT  ========================================================= */
+ #define R_ENCOUT_POSCNT_POSCNT_Pos           (0UL)          /*!< POSCNT (Bit 0)                                        */
+ #define R_ENCOUT_POSCNT_POSCNT_Msk           (0xffffUL)     /*!< POSCNT (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                        R_HDSLS212                                         ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  VERSION2  ======================================================== */
+ #define R_HDSLS212_VERSION2_MINOR_Pos          (0UL)    /*!< MINOR (Bit 0)                                         */
+ #define R_HDSLS212_VERSION2_MINOR_Msk          (0xfUL)  /*!< MINOR (Bitfield-Mask: 0x0f)                           */
+ #define R_HDSLS212_VERSION2_MAJOR_Pos          (4UL)    /*!< MAJOR (Bit 4)                                         */
+ #define R_HDSLS212_VERSION2_MAJOR_Msk          (0x30UL) /*!< MAJOR (Bitfield-Mask: 0x03)                           */
+ #define R_HDSLS212_VERSION2_CODE_Pos           (6UL)    /*!< CODE (Bit 6)                                          */
+ #define R_HDSLS212_VERSION2_CODE_Msk           (0xc0UL) /*!< CODE (Bitfield-Mask: 0x03)                            */
+/* ========================================================  ENC2_ID  ======================================================== */
+ #define R_HDSLS212_ENC2_ID_ENC2ID_Pos          (0UL)    /*!< ENC2ID (Bit 0)                                        */
+ #define R_HDSLS212_ENC2_ID_ENC2ID_Msk          (0xffUL) /*!< ENC2ID (Bitfield-Mask: 0xff)                          */
+/* ========================================================  STATUS2  ======================================================== */
+ #define R_HDSLS212_STATUS2_FIX2_Pos            (0UL)    /*!< FIX2 (Bit 0)                                          */
+ #define R_HDSLS212_STATUS2_FIX2_Msk            (0x1fUL) /*!< FIX2 (Bitfield-Mask: 0x1f)                            */
+ #define R_HDSLS212_STATUS2_ERR2_Pos            (5UL)    /*!< ERR2 (Bit 5)                                          */
+ #define R_HDSLS212_STATUS2_ERR2_Msk            (0x20UL) /*!< ERR2 (Bitfield-Mask: 0x01)                            */
+ #define R_HDSLS212_STATUS2_TEST2_Pos           (6UL)    /*!< TEST2 (Bit 6)                                         */
+ #define R_HDSLS212_STATUS2_TEST2_Msk           (0x40UL) /*!< TEST2 (Bitfield-Mask: 0x01)                           */
+ #define R_HDSLS212_STATUS2_TOG2_Pos            (7UL)    /*!< TOG2 (Bit 7)                                          */
+ #define R_HDSLS212_STATUS2_TOG2_Msk            (0x80UL) /*!< TOG2 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  VPOS24  ========================================================= */
+ #define R_HDSLS212_VPOS24_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS212_VPOS24_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  VPOS23  ========================================================= */
+ #define R_HDSLS212_VPOS23_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS212_VPOS23_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  VPOS22  ========================================================= */
+ #define R_HDSLS212_VPOS22_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS212_VPOS22_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  VPOS21  ========================================================= */
+ #define R_HDSLS212_VPOS21_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS212_VPOS21_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  VPOS20  ========================================================= */
+ #define R_HDSLS212_VPOS20_VPOS2_Pos            (0UL)    /*!< VPOS2 (Bit 0)                                         */
+ #define R_HDSLS212_VPOS20_VPOS2_Msk            (0xffUL) /*!< VPOS2 (Bitfield-Mask: 0xff)                           */
+/* ======================================================  VPOSCRC2_H  ======================================================= */
+ #define R_HDSLS212_VPOSCRC2_H_VPOSCRC2H_Pos    (0UL)    /*!< VPOSCRC2H (Bit 0)                                     */
+ #define R_HDSLS212_VPOSCRC2_H_VPOSCRC2H_Msk    (0xffUL) /*!< VPOSCRC2H (Bitfield-Mask: 0xff)                       */
+/* ======================================================  VPOSCRC2_L  ======================================================= */
+ #define R_HDSLS212_VPOSCRC2_L_VPOSCRC2L_Pos    (0UL)    /*!< VPOSCRC2L (Bit 0)                                     */
+ #define R_HDSLS212_VPOSCRC2_L_VPOSCRC2L_Msk    (0xffUL) /*!< VPOSCRC2L (Bitfield-Mask: 0xff)                       */
+/* ========================================================  DUMMY2  ========================================================= */
+ #define R_HDSLS212_DUMMY2_DUMMY_Pos            (0UL)    /*!< DUMMY (Bit 0)                                         */
+ #define R_HDSLS212_DUMMY2_DUMMY_Msk            (0xffUL) /*!< DUMMY (Bitfield-Mask: 0xff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                         R_AFMT12                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  COMMAND  ======================================================== */
+ #define R_AFMT12_COMMAND_XEA_Pos         (0UL)          /*!< XEA (Bit 0)                                           */
+ #define R_AFMT12_COMMAND_XEA_Msk         (0x7UL)        /*!< XEA (Bitfield-Mask: 0x07)                             */
+ #define R_AFMT12_COMMAND_CC_Pos          (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_AFMT12_COMMAND_CC_Msk          (0xf8UL)       /*!< CC (Bitfield-Mask: 0x1f)                              */
+ #define R_AFMT12_COMMAND_SID_Pos         (8UL)          /*!< SID (Bit 8)                                           */
+ #define R_AFMT12_COMMAND_SID_Msk         (0x1f00UL)     /*!< SID (Bitfield-Mask: 0x1f)                             */
+/* ======================================================  ENC1RXDATA0  ====================================================== */
+ #define R_AFMT12_ENC1RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC1RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA0  ====================================================== */
+ #define R_AFMT12_ENC2RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC2RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA0  ====================================================== */
+ #define R_AFMT12_ENC3RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC3RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA0  ====================================================== */
+ #define R_AFMT12_ENC4RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC4RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA0  ====================================================== */
+ #define R_AFMT12_ENC5RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC5RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA0  ====================================================== */
+ #define R_AFMT12_ENC6RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC6RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA0  ====================================================== */
+ #define R_AFMT12_ENC7RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC7RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA0  ====================================================== */
+ #define R_AFMT12_ENC8RXDATA0_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC8RXDATA0_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA1  ====================================================== */
+ #define R_AFMT12_ENC1RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC1RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA1  ====================================================== */
+ #define R_AFMT12_ENC2RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC2RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA1  ====================================================== */
+ #define R_AFMT12_ENC3RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC3RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA1  ====================================================== */
+ #define R_AFMT12_ENC4RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC4RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA1  ====================================================== */
+ #define R_AFMT12_ENC5RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC5RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA1  ====================================================== */
+ #define R_AFMT12_ENC6RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC6RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA1  ====================================================== */
+ #define R_AFMT12_ENC7RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC7RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA1  ====================================================== */
+ #define R_AFMT12_ENC8RXDATA1_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC8RXDATA1_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  ROMDATA  ======================================================== */
+ #define R_AFMT12_ROMDATA_DATA_Pos        (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ROMDATA_DATA_Msk        (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
+ #define R_AFMT12_ROMDATA_ADDR_Pos        (16UL)         /*!< ADDR (Bit 16)                                         */
+ #define R_AFMT12_ROMDATA_ADDR_Msk        (0xff0000UL)   /*!< ADDR (Bitfield-Mask: 0xff)                            */
+/* ======================================================  ENC1RXDATA2  ====================================================== */
+ #define R_AFMT12_ENC1RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC1RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA2  ====================================================== */
+ #define R_AFMT12_ENC2RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC2RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA2  ====================================================== */
+ #define R_AFMT12_ENC3RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC3RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA2  ====================================================== */
+ #define R_AFMT12_ENC4RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC4RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA2  ====================================================== */
+ #define R_AFMT12_ENC5RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC5RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA2  ====================================================== */
+ #define R_AFMT12_ENC6RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC6RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA2  ====================================================== */
+ #define R_AFMT12_ENC7RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC7RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA2  ====================================================== */
+ #define R_AFMT12_ENC8RXDATA2_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC8RXDATA2_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ==========================================================  ID  =========================================================== */
+ #define R_AFMT12_ID_ID_L_Pos             (0UL)          /*!< ID_L (Bit 0)                                          */
+ #define R_AFMT12_ID_ID_L_Msk             (0xffffUL)     /*!< ID_L (Bitfield-Mask: 0xffff)                          */
+ #define R_AFMT12_ID_ID_H_Pos             (16UL)         /*!< ID_H (Bit 16)                                         */
+ #define R_AFMT12_ID_ID_H_Msk             (0xff0000UL)   /*!< ID_H (Bitfield-Mask: 0xff)                            */
+/* ======================================================  ENC1RXDATA3  ====================================================== */
+ #define R_AFMT12_ENC1RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC1RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA3  ====================================================== */
+ #define R_AFMT12_ENC2RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC2RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA3  ====================================================== */
+ #define R_AFMT12_ENC3RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC3RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA3  ====================================================== */
+ #define R_AFMT12_ENC4RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC4RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA3  ====================================================== */
+ #define R_AFMT12_ENC5RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC5RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA3  ====================================================== */
+ #define R_AFMT12_ENC6RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC6RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA3  ====================================================== */
+ #define R_AFMT12_ENC7RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC7RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA3  ====================================================== */
+ #define R_AFMT12_ENC8RXDATA3_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC8RXDATA3_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA4  ====================================================== */
+ #define R_AFMT12_ENC1RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC1RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA4  ====================================================== */
+ #define R_AFMT12_ENC2RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC2RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA4  ====================================================== */
+ #define R_AFMT12_ENC3RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC3RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA4  ====================================================== */
+ #define R_AFMT12_ENC4RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC4RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA4  ====================================================== */
+ #define R_AFMT12_ENC5RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC5RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA4  ====================================================== */
+ #define R_AFMT12_ENC6RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC6RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA4  ====================================================== */
+ #define R_AFMT12_ENC7RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC7RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA4  ====================================================== */
+ #define R_AFMT12_ENC8RXDATA4_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC8RXDATA4_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA5  ====================================================== */
+ #define R_AFMT12_ENC1RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC1RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA5  ====================================================== */
+ #define R_AFMT12_ENC2RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC2RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA5  ====================================================== */
+ #define R_AFMT12_ENC3RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC3RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA5  ====================================================== */
+ #define R_AFMT12_ENC4RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC4RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA5  ====================================================== */
+ #define R_AFMT12_ENC5RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC5RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA5  ====================================================== */
+ #define R_AFMT12_ENC6RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC6RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA5  ====================================================== */
+ #define R_AFMT12_ENC7RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC7RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA5  ====================================================== */
+ #define R_AFMT12_ENC8RXDATA5_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC8RXDATA5_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA6  ====================================================== */
+ #define R_AFMT12_ENC1RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC1RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA6  ====================================================== */
+ #define R_AFMT12_ENC2RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC2RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA6  ====================================================== */
+ #define R_AFMT12_ENC3RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC3RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA6  ====================================================== */
+ #define R_AFMT12_ENC4RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC4RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA6  ====================================================== */
+ #define R_AFMT12_ENC5RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC5RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA6  ====================================================== */
+ #define R_AFMT12_ENC6RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC6RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA6  ====================================================== */
+ #define R_AFMT12_ENC7RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC7RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA6  ====================================================== */
+ #define R_AFMT12_ENC8RXDATA6_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC8RXDATA6_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC1RXDATA7  ====================================================== */
+ #define R_AFMT12_ENC1RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC1RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC2RXDATA7  ====================================================== */
+ #define R_AFMT12_ENC2RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC2RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC3RXDATA7  ====================================================== */
+ #define R_AFMT12_ENC3RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC3RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC4RXDATA7  ====================================================== */
+ #define R_AFMT12_ENC4RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC4RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC5RXDATA7  ====================================================== */
+ #define R_AFMT12_ENC5RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC5RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC6RXDATA7  ====================================================== */
+ #define R_AFMT12_ENC6RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC6RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC7RXDATA7  ====================================================== */
+ #define R_AFMT12_ENC7RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC7RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  ENC8RXDATA7  ====================================================== */
+ #define R_AFMT12_ENC8RXDATA7_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_AFMT12_ENC8RXDATA7_DATA_Msk    (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  TRGSEL  ========================================================= */
+ #define R_AFMT12_TRGSEL_EXT_Pos          (0UL)          /*!< EXT (Bit 0)                                           */
+ #define R_AFMT12_TRGSEL_EXT_Msk          (0x1UL)        /*!< EXT (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TXTRG  ========================================================= */
+ #define R_AFMT12_TXTRG_TRG_Pos           (0UL)          /*!< TRG (Bit 0)                                           */
+ #define R_AFMT12_TXTRG_TRG_Msk           (0x1UL)        /*!< TRG (Bitfield-Mask: 0x01)                             */
+/* =========================================================  BRSEL  ========================================================= */
+ #define R_AFMT12_BRSEL_BR_Pos            (0UL)          /*!< BR (Bit 0)                                            */
+ #define R_AFMT12_BRSEL_BR_Msk            (0x7UL)        /*!< BR (Bitfield-Mask: 0x07)                              */
+ #define R_AFMT12_BRSEL_AS_Pos            (3UL)          /*!< AS (Bit 3)                                            */
+ #define R_AFMT12_BRSEL_AS_Msk            (0x8UL)        /*!< AS (Bitfield-Mask: 0x01)                              */
+ #define R_AFMT12_BRSEL_TM_Pos            (4UL)          /*!< TM (Bit 4)                                            */
+ #define R_AFMT12_BRSEL_TM_Msk            (0xff0UL)      /*!< TM (Bitfield-Mask: 0xff)                              */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GMAC1                                          ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================  MAC_Configuration  =================================================== */
+ #define R_GMAC1_MAC_Configuration_RE_Pos                                   (0UL)          /*!< RE (Bit 0)                                            */
+ #define R_GMAC1_MAC_Configuration_RE_Msk                                   (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_TE_Pos                                   (1UL)          /*!< TE (Bit 1)                                            */
+ #define R_GMAC1_MAC_Configuration_TE_Msk                                   (0x2UL)        /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_PRELEN_Pos                               (2UL)          /*!< PRELEN (Bit 2)                                        */
+ #define R_GMAC1_MAC_Configuration_PRELEN_Msk                               (0xcUL)        /*!< PRELEN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_Configuration_DC_Pos                                   (4UL)          /*!< DC (Bit 4)                                            */
+ #define R_GMAC1_MAC_Configuration_DC_Msk                                   (0x10UL)       /*!< DC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_BL_Pos                                   (5UL)          /*!< BL (Bit 5)                                            */
+ #define R_GMAC1_MAC_Configuration_BL_Msk                                   (0x60UL)       /*!< BL (Bitfield-Mask: 0x03)                              */
+ #define R_GMAC1_MAC_Configuration_DR_Pos                                   (8UL)          /*!< DR (Bit 8)                                            */
+ #define R_GMAC1_MAC_Configuration_DR_Msk                                   (0x100UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_DCRS_Pos                                 (9UL)          /*!< DCRS (Bit 9)                                          */
+ #define R_GMAC1_MAC_Configuration_DCRS_Msk                                 (0x200UL)      /*!< DCRS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Configuration_DO_Pos                                   (10UL)         /*!< DO (Bit 10)                                           */
+ #define R_GMAC1_MAC_Configuration_DO_Msk                                   (0x400UL)      /*!< DO (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_ECRSFD_Pos                               (11UL)         /*!< ECRSFD (Bit 11)                                       */
+ #define R_GMAC1_MAC_Configuration_ECRSFD_Msk                               (0x800UL)      /*!< ECRSFD (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Configuration_LM_Pos                                   (12UL)         /*!< LM (Bit 12)                                           */
+ #define R_GMAC1_MAC_Configuration_LM_Msk                                   (0x1000UL)     /*!< LM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_DM_Pos                                   (13UL)         /*!< DM (Bit 13)                                           */
+ #define R_GMAC1_MAC_Configuration_DM_Msk                                   (0x2000UL)     /*!< DM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_FES_Pos                                  (14UL)         /*!< FES (Bit 14)                                          */
+ #define R_GMAC1_MAC_Configuration_FES_Msk                                  (0x4000UL)     /*!< FES (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Configuration_PS_Pos                                   (15UL)         /*!< PS (Bit 15)                                           */
+ #define R_GMAC1_MAC_Configuration_PS_Msk                                   (0x8000UL)     /*!< PS (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_JE_Pos                                   (16UL)         /*!< JE (Bit 16)                                           */
+ #define R_GMAC1_MAC_Configuration_JE_Msk                                   (0x10000UL)    /*!< JE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_JD_Pos                                   (17UL)         /*!< JD (Bit 17)                                           */
+ #define R_GMAC1_MAC_Configuration_JD_Msk                                   (0x20000UL)    /*!< JD (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_BE_Pos                                   (18UL)         /*!< BE (Bit 18)                                           */
+ #define R_GMAC1_MAC_Configuration_BE_Msk                                   (0x40000UL)    /*!< BE (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_WD_Pos                                   (19UL)         /*!< WD (Bit 19)                                           */
+ #define R_GMAC1_MAC_Configuration_WD_Msk                                   (0x80000UL)    /*!< WD (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Configuration_ACS_Pos                                  (20UL)         /*!< ACS (Bit 20)                                          */
+ #define R_GMAC1_MAC_Configuration_ACS_Msk                                  (0x100000UL)   /*!< ACS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Configuration_CST_Pos                                  (21UL)         /*!< CST (Bit 21)                                          */
+ #define R_GMAC1_MAC_Configuration_CST_Msk                                  (0x200000UL)   /*!< CST (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Configuration_S2KP_Pos                                 (22UL)         /*!< S2KP (Bit 22)                                         */
+ #define R_GMAC1_MAC_Configuration_S2KP_Msk                                 (0x400000UL)   /*!< S2KP (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Configuration_GPSLCE_Pos                               (23UL)         /*!< GPSLCE (Bit 23)                                       */
+ #define R_GMAC1_MAC_Configuration_GPSLCE_Msk                               (0x800000UL)   /*!< GPSLCE (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Configuration_IPG_Pos                                  (24UL)         /*!< IPG (Bit 24)                                          */
+ #define R_GMAC1_MAC_Configuration_IPG_Msk                                  (0x7000000UL)  /*!< IPG (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MAC_Configuration_IPC_Pos                                  (27UL)         /*!< IPC (Bit 27)                                          */
+ #define R_GMAC1_MAC_Configuration_IPC_Msk                                  (0x8000000UL)  /*!< IPC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Configuration_ARPEN_Pos                                (31UL)         /*!< ARPEN (Bit 31)                                        */
+ #define R_GMAC1_MAC_Configuration_ARPEN_Msk                                (0x80000000UL) /*!< ARPEN (Bitfield-Mask: 0x01)                           */
+/* =================================================  MAC_Ext_Configuration  ================================================= */
+ #define R_GMAC1_MAC_Ext_Configuration_GPSL_Pos                             (0UL)          /*!< GPSL (Bit 0)                                          */
+ #define R_GMAC1_MAC_Ext_Configuration_GPSL_Msk                             (0x3fffUL)     /*!< GPSL (Bitfield-Mask: 0x3fff)                          */
+ #define R_GMAC1_MAC_Ext_Configuration_DCRCC_Pos                            (16UL)         /*!< DCRCC (Bit 16)                                        */
+ #define R_GMAC1_MAC_Ext_Configuration_DCRCC_Msk                            (0x10000UL)    /*!< DCRCC (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Ext_Configuration_SPEN_Pos                             (17UL)         /*!< SPEN (Bit 17)                                         */
+ #define R_GMAC1_MAC_Ext_Configuration_SPEN_Msk                             (0x20000UL)    /*!< SPEN (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Ext_Configuration_USP_Pos                              (18UL)         /*!< USP (Bit 18)                                          */
+ #define R_GMAC1_MAC_Ext_Configuration_USP_Msk                              (0x40000UL)    /*!< USP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Ext_Configuration_PDC_Pos                              (19UL)         /*!< PDC (Bit 19)                                          */
+ #define R_GMAC1_MAC_Ext_Configuration_PDC_Msk                              (0x80000UL)    /*!< PDC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Ext_Configuration_HDSMS_Pos                            (20UL)         /*!< HDSMS (Bit 20)                                        */
+ #define R_GMAC1_MAC_Ext_Configuration_HDSMS_Msk                            (0x700000UL)   /*!< HDSMS (Bitfield-Mask: 0x07)                           */
+ #define R_GMAC1_MAC_Ext_Configuration_EIPGEN_Pos                           (24UL)         /*!< EIPGEN (Bit 24)                                       */
+ #define R_GMAC1_MAC_Ext_Configuration_EIPGEN_Msk                           (0x1000000UL)  /*!< EIPGEN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Ext_Configuration_EIPG_Pos                             (25UL)         /*!< EIPG (Bit 25)                                         */
+ #define R_GMAC1_MAC_Ext_Configuration_EIPG_Msk                             (0x3e000000UL) /*!< EIPG (Bitfield-Mask: 0x1f)                            */
+ #define R_GMAC1_MAC_Ext_Configuration_APDIM_Pos                            (30UL)         /*!< APDIM (Bit 30)                                        */
+ #define R_GMAC1_MAC_Ext_Configuration_APDIM_Msk                            (0x40000000UL) /*!< APDIM (Bitfield-Mask: 0x01)                           */
+/* ===================================================  MAC_Packet_Filter  =================================================== */
+ #define R_GMAC1_MAC_Packet_Filter_PR_Pos                                   (0UL)          /*!< PR (Bit 0)                                            */
+ #define R_GMAC1_MAC_Packet_Filter_PR_Msk                                   (0x1UL)        /*!< PR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Packet_Filter_HUC_Pos                                  (1UL)          /*!< HUC (Bit 1)                                           */
+ #define R_GMAC1_MAC_Packet_Filter_HUC_Msk                                  (0x2UL)        /*!< HUC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Packet_Filter_HMC_Pos                                  (2UL)          /*!< HMC (Bit 2)                                           */
+ #define R_GMAC1_MAC_Packet_Filter_HMC_Msk                                  (0x4UL)        /*!< HMC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Packet_Filter_DAIF_Pos                                 (3UL)          /*!< DAIF (Bit 3)                                          */
+ #define R_GMAC1_MAC_Packet_Filter_DAIF_Msk                                 (0x8UL)        /*!< DAIF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Packet_Filter_PM_Pos                                   (4UL)          /*!< PM (Bit 4)                                            */
+ #define R_GMAC1_MAC_Packet_Filter_PM_Msk                                   (0x10UL)       /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Packet_Filter_DBF_Pos                                  (5UL)          /*!< DBF (Bit 5)                                           */
+ #define R_GMAC1_MAC_Packet_Filter_DBF_Msk                                  (0x20UL)       /*!< DBF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Packet_Filter_PCF_Pos                                  (6UL)          /*!< PCF (Bit 6)                                           */
+ #define R_GMAC1_MAC_Packet_Filter_PCF_Msk                                  (0xc0UL)       /*!< PCF (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MAC_Packet_Filter_SAIF_Pos                                 (8UL)          /*!< SAIF (Bit 8)                                          */
+ #define R_GMAC1_MAC_Packet_Filter_SAIF_Msk                                 (0x100UL)      /*!< SAIF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Packet_Filter_SAF_Pos                                  (9UL)          /*!< SAF (Bit 9)                                           */
+ #define R_GMAC1_MAC_Packet_Filter_SAF_Msk                                  (0x200UL)      /*!< SAF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Packet_Filter_HPF_Pos                                  (10UL)         /*!< HPF (Bit 10)                                          */
+ #define R_GMAC1_MAC_Packet_Filter_HPF_Msk                                  (0x400UL)      /*!< HPF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Packet_Filter_VTFE_Pos                                 (16UL)         /*!< VTFE (Bit 16)                                         */
+ #define R_GMAC1_MAC_Packet_Filter_VTFE_Msk                                 (0x10000UL)    /*!< VTFE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Packet_Filter_IPFE_Pos                                 (20UL)         /*!< IPFE (Bit 20)                                         */
+ #define R_GMAC1_MAC_Packet_Filter_IPFE_Msk                                 (0x100000UL)   /*!< IPFE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Packet_Filter_DNTU_Pos                                 (21UL)         /*!< DNTU (Bit 21)                                         */
+ #define R_GMAC1_MAC_Packet_Filter_DNTU_Msk                                 (0x200000UL)   /*!< DNTU (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Packet_Filter_RA_Pos                                   (31UL)         /*!< RA (Bit 31)                                           */
+ #define R_GMAC1_MAC_Packet_Filter_RA_Msk                                   (0x80000000UL) /*!< RA (Bitfield-Mask: 0x01)                              */
+/* =================================================  MAC_Watchdog_Timeout  ================================================== */
+ #define R_GMAC1_MAC_Watchdog_Timeout_WTO_Pos                               (0UL)          /*!< WTO (Bit 0)                                           */
+ #define R_GMAC1_MAC_Watchdog_Timeout_WTO_Msk                               (0xfUL)        /*!< WTO (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MAC_Watchdog_Timeout_PWE_Pos                               (8UL)          /*!< PWE (Bit 8)                                           */
+ #define R_GMAC1_MAC_Watchdog_Timeout_PWE_Msk                               (0x100UL)      /*!< PWE (Bitfield-Mask: 0x01)                             */
+/* ==================================================  MAC_HASH_TABLE_REG0  ================================================== */
+ #define R_GMAC1_MAC_HASH_TABLE_REG0_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC1_MAC_HASH_TABLE_REG0_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG1  ================================================== */
+ #define R_GMAC1_MAC_HASH_TABLE_REG1_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC1_MAC_HASH_TABLE_REG1_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG2  ================================================== */
+ #define R_GMAC1_MAC_HASH_TABLE_REG2_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC1_MAC_HASH_TABLE_REG2_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG3  ================================================== */
+ #define R_GMAC1_MAC_HASH_TABLE_REG3_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC1_MAC_HASH_TABLE_REG3_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG4  ================================================== */
+ #define R_GMAC1_MAC_HASH_TABLE_REG4_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC1_MAC_HASH_TABLE_REG4_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG5  ================================================== */
+ #define R_GMAC1_MAC_HASH_TABLE_REG5_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC1_MAC_HASH_TABLE_REG5_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG6  ================================================== */
+ #define R_GMAC1_MAC_HASH_TABLE_REG6_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC1_MAC_HASH_TABLE_REG6_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ==================================================  MAC_HASH_TABLE_REG7  ================================================== */
+ #define R_GMAC1_MAC_HASH_TABLE_REG7_HT_Pos                                 (0UL)          /*!< HT (Bit 0)                                            */
+ #define R_GMAC1_MAC_HASH_TABLE_REG7_HT_Msk                                 (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
+/* ===================================================  MAC_VLAN_Tag_Ctrl  =================================================== */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_OB_Pos                                   (0UL)          /*!< OB (Bit 0)                                            */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_OB_Msk                                   (0x1UL)        /*!< OB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_CT_Pos                                   (1UL)          /*!< CT (Bit 1)                                            */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_CT_Msk                                   (0x2UL)        /*!< CT (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_OFS_Pos                                  (2UL)          /*!< OFS (Bit 2)                                           */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_OFS_Msk                                  (0x3cUL)       /*!< OFS (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_ETV_Pos                                  (16UL)         /*!< ETV (Bit 16)                                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_ETV_Msk                                  (0x10000UL)    /*!< ETV (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_VTIM_Pos                                 (17UL)         /*!< VTIM (Bit 17)                                         */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_VTIM_Msk                                 (0x20000UL)    /*!< VTIM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_ESVL_Pos                                 (18UL)         /*!< ESVL (Bit 18)                                         */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_ESVL_Msk                                 (0x40000UL)    /*!< ESVL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_ERSVLM_Pos                               (19UL)         /*!< ERSVLM (Bit 19)                                       */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_ERSVLM_Msk                               (0x80000UL)    /*!< ERSVLM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_DOVLTC_Pos                               (20UL)         /*!< DOVLTC (Bit 20)                                       */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_DOVLTC_Msk                               (0x100000UL)   /*!< DOVLTC (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EVLS_Pos                                 (21UL)         /*!< EVLS (Bit 21)                                         */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EVLS_Msk                                 (0x600000UL)   /*!< EVLS (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EVLRXS_Pos                               (24UL)         /*!< EVLRXS (Bit 24)                                       */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EVLRXS_Msk                               (0x1000000UL)  /*!< EVLRXS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_VTHM_Pos                                 (25UL)         /*!< VTHM (Bit 25)                                         */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_VTHM_Msk                                 (0x2000000UL)  /*!< VTHM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EDVLP_Pos                                (26UL)         /*!< EDVLP (Bit 26)                                        */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EDVLP_Msk                                (0x4000000UL)  /*!< EDVLP (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_ERIVLT_Pos                               (27UL)         /*!< ERIVLT (Bit 27)                                       */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_ERIVLT_Msk                               (0x8000000UL)  /*!< ERIVLT (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EIVLS_Pos                                (28UL)         /*!< EIVLS (Bit 28)                                        */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EIVLS_Msk                                (0x30000000UL) /*!< EIVLS (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EIVLRXS_Pos                              (31UL)         /*!< EIVLRXS (Bit 31)                                      */
+ #define R_GMAC1_MAC_VLAN_Tag_Ctrl_EIVLRXS_Msk                              (0x80000000UL) /*!< EIVLRXS (Bitfield-Mask: 0x01)                         */
+/* ===================================================  MAC_VLAN_Tag_Data  =================================================== */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_VID_Pos                                  (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_VID_Msk                                  (0xffffUL)     /*!< VID (Bitfield-Mask: 0xffff)                           */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_VEN_Pos                                  (16UL)         /*!< VEN (Bit 16)                                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_VEN_Msk                                  (0x10000UL)    /*!< VEN (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_ETV_Pos                                  (17UL)         /*!< ETV (Bit 17)                                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_ETV_Msk                                  (0x20000UL)    /*!< ETV (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_DOVLTC_Pos                               (18UL)         /*!< DOVLTC (Bit 18)                                       */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_DOVLTC_Msk                               (0x40000UL)    /*!< DOVLTC (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_ERSVLM_Pos                               (19UL)         /*!< ERSVLM (Bit 19)                                       */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_ERSVLM_Msk                               (0x80000UL)    /*!< ERSVLM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_RIVLT_Pos                                (20UL)         /*!< RIVLT (Bit 20)                                        */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_RIVLT_Msk                                (0x100000UL)   /*!< RIVLT (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_DMACHEN_Pos                              (24UL)         /*!< DMACHEN (Bit 24)                                      */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_DMACHEN_Msk                              (0x1000000UL)  /*!< DMACHEN (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_DMACHN_Pos                               (25UL)         /*!< DMACHN (Bit 25)                                       */
+ #define R_GMAC1_MAC_VLAN_Tag_Data_DMACHN_Msk                               (0xe000000UL)  /*!< DMACHN (Bitfield-Mask: 0x07)                          */
+/* ==================================================  MAC_VLAN_Hash_Table  ================================================== */
+ #define R_GMAC1_MAC_VLAN_Hash_Table_VLHT_Pos                               (0UL)          /*!< VLHT (Bit 0)                                          */
+ #define R_GMAC1_MAC_VLAN_Hash_Table_VLHT_Msk                               (0xffffUL)     /*!< VLHT (Bitfield-Mask: 0xffff)                          */
+/* ==================================================  MAC_Q0_Tx_Flow_Ctrl  ================================================== */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_FCB_BPA_Pos                            (0UL)          /*!< FCB_BPA (Bit 0)                                       */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_FCB_BPA_Msk                            (0x1UL)        /*!< FCB_BPA (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_TFE_Pos                                (1UL)          /*!< TFE (Bit 1)                                           */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_TFE_Msk                                (0x2UL)        /*!< TFE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_PLT_Pos                                (4UL)          /*!< PLT (Bit 4)                                           */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_PLT_Msk                                (0x70UL)       /*!< PLT (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_DZPQ_Pos                               (7UL)          /*!< DZPQ (Bit 7)                                          */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_DZPQ_Msk                               (0x80UL)       /*!< DZPQ (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_PT_Pos                                 (16UL)         /*!< PT (Bit 16)                                           */
+ #define R_GMAC1_MAC_Q0_Tx_Flow_Ctrl_PT_Msk                                 (0xffff0000UL) /*!< PT (Bitfield-Mask: 0xffff)                            */
+/* ===================================================  MAC_Rx_Flow_Ctrl  ==================================================== */
+ #define R_GMAC1_MAC_Rx_Flow_Ctrl_RFE_Pos                                   (0UL)          /*!< RFE (Bit 0)                                           */
+ #define R_GMAC1_MAC_Rx_Flow_Ctrl_RFE_Msk                                   (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Rx_Flow_Ctrl_UP_Pos                                    (1UL)          /*!< UP (Bit 1)                                            */
+ #define R_GMAC1_MAC_Rx_Flow_Ctrl_UP_Msk                                    (0x2UL)        /*!< UP (Bitfield-Mask: 0x01)                              */
+/* =====================================================  MAC_RxQ_Ctrl4  ===================================================== */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_UFFQE_Pos                                    (0UL)          /*!< UFFQE (Bit 0)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_UFFQE_Msk                                    (0x1UL)        /*!< UFFQE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_UFFQ_Pos                                     (1UL)          /*!< UFFQ (Bit 1)                                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_UFFQ_Msk                                     (0xeUL)        /*!< UFFQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_MFFQE_Pos                                    (8UL)          /*!< MFFQE (Bit 8)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_MFFQE_Msk                                    (0x100UL)      /*!< MFFQE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_MFFQ_Pos                                     (9UL)          /*!< MFFQ (Bit 9)                                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_MFFQ_Msk                                     (0xe00UL)      /*!< MFFQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_VFFQE_Pos                                    (16UL)         /*!< VFFQE (Bit 16)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_VFFQE_Msk                                    (0x10000UL)    /*!< VFFQE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_VFFQ_Pos                                     (17UL)         /*!< VFFQ (Bit 17)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl4_VFFQ_Msk                                     (0xe0000UL)    /*!< VFFQ (Bitfield-Mask: 0x07)                            */
+/* =====================================================  MAC_RxQ_Ctrl0  ===================================================== */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ0EN_Pos                                   (0UL)          /*!< RXQ0EN (Bit 0)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ0EN_Msk                                   (0x3UL)        /*!< RXQ0EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ1EN_Pos                                   (2UL)          /*!< RXQ1EN (Bit 2)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ1EN_Msk                                   (0xcUL)        /*!< RXQ1EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ2EN_Pos                                   (4UL)          /*!< RXQ2EN (Bit 4)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ2EN_Msk                                   (0x30UL)       /*!< RXQ2EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ3EN_Pos                                   (6UL)          /*!< RXQ3EN (Bit 6)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ3EN_Msk                                   (0xc0UL)       /*!< RXQ3EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ4EN_Pos                                   (8UL)          /*!< RXQ4EN (Bit 8)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ4EN_Msk                                   (0x300UL)      /*!< RXQ4EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ5EN_Pos                                   (10UL)         /*!< RXQ5EN (Bit 10)                                       */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ5EN_Msk                                   (0xc00UL)      /*!< RXQ5EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ6EN_Pos                                   (12UL)         /*!< RXQ6EN (Bit 12)                                       */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ6EN_Msk                                   (0x3000UL)     /*!< RXQ6EN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ7EN_Pos                                   (14UL)         /*!< RXQ7EN (Bit 14)                                       */
+ #define R_GMAC1_MAC_RxQ_Ctrl0_RXQ7EN_Msk                                   (0xc000UL)     /*!< RXQ7EN (Bitfield-Mask: 0x03)                          */
+/* =====================================================  MAC_RxQ_Ctrl1  ===================================================== */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_AVCPQ_Pos                                    (0UL)          /*!< AVCPQ (Bit 0)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_AVCPQ_Msk                                    (0x7UL)        /*!< AVCPQ (Bitfield-Mask: 0x07)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_PTPQ_Pos                                     (4UL)          /*!< PTPQ (Bit 4)                                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_PTPQ_Msk                                     (0x70UL)       /*!< PTPQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_UPQ_Pos                                      (12UL)         /*!< UPQ (Bit 12)                                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_UPQ_Msk                                      (0x7000UL)     /*!< UPQ (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_MCBCQ_Pos                                    (16UL)         /*!< MCBCQ (Bit 16)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_MCBCQ_Msk                                    (0x70000UL)    /*!< MCBCQ (Bitfield-Mask: 0x07)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_MCBCQEN_Pos                                  (20UL)         /*!< MCBCQEN (Bit 20)                                      */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_MCBCQEN_Msk                                  (0x100000UL)   /*!< MCBCQEN (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_TACPQE_Pos                                   (21UL)         /*!< TACPQE (Bit 21)                                       */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_TACPQE_Msk                                   (0x200000UL)   /*!< TACPQE (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_TPQC_Pos                                     (22UL)         /*!< TPQC (Bit 22)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_TPQC_Msk                                     (0xc00000UL)   /*!< TPQC (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_FPRQ_Pos                                     (24UL)         /*!< FPRQ (Bit 24)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_FPRQ_Msk                                     (0x7000000UL)  /*!< FPRQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_OMCBCQ_Pos                                   (28UL)         /*!< OMCBCQ (Bit 28)                                       */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_OMCBCQ_Msk                                   (0x10000000UL) /*!< OMCBCQ (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_TBRQE_Pos                                    (29UL)         /*!< TBRQE (Bit 29)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl1_TBRQE_Msk                                    (0x20000000UL) /*!< TBRQE (Bitfield-Mask: 0x01)                           */
+/* =====================================================  MAC_RxQ_Ctrl2  ===================================================== */
+ #define R_GMAC1_MAC_RxQ_Ctrl2_PSRQ0_Pos                                    (0UL)          /*!< PSRQ0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl2_PSRQ0_Msk                                    (0xffUL)       /*!< PSRQ0 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl2_PSRQ1_Pos                                    (8UL)          /*!< PSRQ1 (Bit 8)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl2_PSRQ1_Msk                                    (0xff00UL)     /*!< PSRQ1 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl2_PSRQ2_Pos                                    (16UL)         /*!< PSRQ2 (Bit 16)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl2_PSRQ2_Msk                                    (0xff0000UL)   /*!< PSRQ2 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl2_PSRQ3_Pos                                    (24UL)         /*!< PSRQ3 (Bit 24)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl2_PSRQ3_Msk                                    (0xff000000UL) /*!< PSRQ3 (Bitfield-Mask: 0xff)                           */
+/* =====================================================  MAC_RxQ_Ctrl3  ===================================================== */
+ #define R_GMAC1_MAC_RxQ_Ctrl3_PSRQ4_Pos                                    (0UL)          /*!< PSRQ4 (Bit 0)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl3_PSRQ4_Msk                                    (0xffUL)       /*!< PSRQ4 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl3_PSRQ5_Pos                                    (8UL)          /*!< PSRQ5 (Bit 8)                                         */
+ #define R_GMAC1_MAC_RxQ_Ctrl3_PSRQ5_Msk                                    (0xff00UL)     /*!< PSRQ5 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl3_PSRQ6_Pos                                    (16UL)         /*!< PSRQ6 (Bit 16)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl3_PSRQ6_Msk                                    (0xff0000UL)   /*!< PSRQ6 (Bitfield-Mask: 0xff)                           */
+ #define R_GMAC1_MAC_RxQ_Ctrl3_PSRQ7_Pos                                    (24UL)         /*!< PSRQ7 (Bit 24)                                        */
+ #define R_GMAC1_MAC_RxQ_Ctrl3_PSRQ7_Msk                                    (0xff000000UL) /*!< PSRQ7 (Bitfield-Mask: 0xff)                           */
+/* =================================================  MAC_Interrupt_Status  ================================================== */
+ #define R_GMAC1_MAC_Interrupt_Status_PMTIS_Pos                             (4UL)          /*!< PMTIS (Bit 4)                                         */
+ #define R_GMAC1_MAC_Interrupt_Status_PMTIS_Msk                             (0x10UL)       /*!< PMTIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Status_LPIIS_Pos                             (5UL)          /*!< LPIIS (Bit 5)                                         */
+ #define R_GMAC1_MAC_Interrupt_Status_LPIIS_Msk                             (0x20UL)       /*!< LPIIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Status_MMCIS_Pos                             (8UL)          /*!< MMCIS (Bit 8)                                         */
+ #define R_GMAC1_MAC_Interrupt_Status_MMCIS_Msk                             (0x100UL)      /*!< MMCIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Status_MMCRXIS_Pos                           (9UL)          /*!< MMCRXIS (Bit 9)                                       */
+ #define R_GMAC1_MAC_Interrupt_Status_MMCRXIS_Msk                           (0x200UL)      /*!< MMCRXIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Interrupt_Status_MMCTXIS_Pos                           (10UL)         /*!< MMCTXIS (Bit 10)                                      */
+ #define R_GMAC1_MAC_Interrupt_Status_MMCTXIS_Msk                           (0x400UL)      /*!< MMCTXIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Interrupt_Status_MMCRXIPIS_Pos                         (11UL)         /*!< MMCRXIPIS (Bit 11)                                    */
+ #define R_GMAC1_MAC_Interrupt_Status_MMCRXIPIS_Msk                         (0x800UL)      /*!< MMCRXIPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_Interrupt_Status_TSIS_Pos                              (12UL)         /*!< TSIS (Bit 12)                                         */
+ #define R_GMAC1_MAC_Interrupt_Status_TSIS_Msk                              (0x1000UL)     /*!< TSIS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Interrupt_Status_TXSTSIS_Pos                           (13UL)         /*!< TXSTSIS (Bit 13)                                      */
+ #define R_GMAC1_MAC_Interrupt_Status_TXSTSIS_Msk                           (0x2000UL)     /*!< TXSTSIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Interrupt_Status_RXSTSIS_Pos                           (14UL)         /*!< RXSTSIS (Bit 14)                                      */
+ #define R_GMAC1_MAC_Interrupt_Status_RXSTSIS_Msk                           (0x4000UL)     /*!< RXSTSIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Interrupt_Status_FPEIS_Pos                             (17UL)         /*!< FPEIS (Bit 17)                                        */
+ #define R_GMAC1_MAC_Interrupt_Status_FPEIS_Msk                             (0x20000UL)    /*!< FPEIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Status_MDIOIS_Pos                            (18UL)         /*!< MDIOIS (Bit 18)                                       */
+ #define R_GMAC1_MAC_Interrupt_Status_MDIOIS_Msk                            (0x40000UL)    /*!< MDIOIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Interrupt_Status_MFTIS_Pos                             (19UL)         /*!< MFTIS (Bit 19)                                        */
+ #define R_GMAC1_MAC_Interrupt_Status_MFTIS_Msk                             (0x80000UL)    /*!< MFTIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Status_MFRIS_Pos                             (20UL)         /*!< MFRIS (Bit 20)                                        */
+ #define R_GMAC1_MAC_Interrupt_Status_MFRIS_Msk                             (0x100000UL)   /*!< MFRIS (Bitfield-Mask: 0x01)                           */
+/* =================================================  MAC_Interrupt_Enable  ================================================== */
+ #define R_GMAC1_MAC_Interrupt_Enable_PHYIE_Pos                             (3UL)          /*!< PHYIE (Bit 3)                                         */
+ #define R_GMAC1_MAC_Interrupt_Enable_PHYIE_Msk                             (0x8UL)        /*!< PHYIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Enable_PMTIE_Pos                             (4UL)          /*!< PMTIE (Bit 4)                                         */
+ #define R_GMAC1_MAC_Interrupt_Enable_PMTIE_Msk                             (0x10UL)       /*!< PMTIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Enable_LPIIE_Pos                             (5UL)          /*!< LPIIE (Bit 5)                                         */
+ #define R_GMAC1_MAC_Interrupt_Enable_LPIIE_Msk                             (0x20UL)       /*!< LPIIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Enable_TSIE_Pos                              (12UL)         /*!< TSIE (Bit 12)                                         */
+ #define R_GMAC1_MAC_Interrupt_Enable_TSIE_Msk                              (0x1000UL)     /*!< TSIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Interrupt_Enable_TXSTSIE_Pos                           (13UL)         /*!< TXSTSIE (Bit 13)                                      */
+ #define R_GMAC1_MAC_Interrupt_Enable_TXSTSIE_Msk                           (0x2000UL)     /*!< TXSTSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Interrupt_Enable_RXSTSIE_Pos                           (14UL)         /*!< RXSTSIE (Bit 14)                                      */
+ #define R_GMAC1_MAC_Interrupt_Enable_RXSTSIE_Msk                           (0x4000UL)     /*!< RXSTSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Interrupt_Enable_FPEIE_Pos                             (17UL)         /*!< FPEIE (Bit 17)                                        */
+ #define R_GMAC1_MAC_Interrupt_Enable_FPEIE_Msk                             (0x20000UL)    /*!< FPEIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Interrupt_Enable_MDIOIE_Pos                            (18UL)         /*!< MDIOIE (Bit 18)                                       */
+ #define R_GMAC1_MAC_Interrupt_Enable_MDIOIE_Msk                            (0x40000UL)    /*!< MDIOIE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_Rx_Tx_Status  ==================================================== */
+ #define R_GMAC1_MAC_Rx_Tx_Status_TJT_Pos                                   (0UL)          /*!< TJT (Bit 0)                                           */
+ #define R_GMAC1_MAC_Rx_Tx_Status_TJT_Msk                                   (0x1UL)        /*!< TJT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Rx_Tx_Status_NCARR_Pos                                 (1UL)          /*!< NCARR (Bit 1)                                         */
+ #define R_GMAC1_MAC_Rx_Tx_Status_NCARR_Msk                                 (0x2UL)        /*!< NCARR (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Rx_Tx_Status_LCARR_Pos                                 (2UL)          /*!< LCARR (Bit 2)                                         */
+ #define R_GMAC1_MAC_Rx_Tx_Status_LCARR_Msk                                 (0x4UL)        /*!< LCARR (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Rx_Tx_Status_EXDEF_Pos                                 (3UL)          /*!< EXDEF (Bit 3)                                         */
+ #define R_GMAC1_MAC_Rx_Tx_Status_EXDEF_Msk                                 (0x8UL)        /*!< EXDEF (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Rx_Tx_Status_LCOL_Pos                                  (4UL)          /*!< LCOL (Bit 4)                                          */
+ #define R_GMAC1_MAC_Rx_Tx_Status_LCOL_Msk                                  (0x10UL)       /*!< LCOL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Rx_Tx_Status_EXCOL_Pos                                 (5UL)          /*!< EXCOL (Bit 5)                                         */
+ #define R_GMAC1_MAC_Rx_Tx_Status_EXCOL_Msk                                 (0x20UL)       /*!< EXCOL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Rx_Tx_Status_RWT_Pos                                   (8UL)          /*!< RWT (Bit 8)                                           */
+ #define R_GMAC1_MAC_Rx_Tx_Status_RWT_Msk                                   (0x100UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+/* ================================================  MAC_PMT_Control_Status  ================================================= */
+ #define R_GMAC1_MAC_PMT_Control_Status_PWRDWN_Pos                          (0UL)          /*!< PWRDWN (Bit 0)                                        */
+ #define R_GMAC1_MAC_PMT_Control_Status_PWRDWN_Msk                          (0x1UL)        /*!< PWRDWN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_PMT_Control_Status_MGKPKTEN_Pos                        (1UL)          /*!< MGKPKTEN (Bit 1)                                      */
+ #define R_GMAC1_MAC_PMT_Control_Status_MGKPKTEN_Msk                        (0x2UL)        /*!< MGKPKTEN (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKPKTEN_Pos                        (2UL)          /*!< RWKPKTEN (Bit 2)                                      */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKPKTEN_Msk                        (0x4UL)        /*!< RWKPKTEN (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_PMT_Control_Status_MGKPRCVD_Pos                        (5UL)          /*!< MGKPRCVD (Bit 5)                                      */
+ #define R_GMAC1_MAC_PMT_Control_Status_MGKPRCVD_Msk                        (0x20UL)       /*!< MGKPRCVD (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKPRCVD_Pos                        (6UL)          /*!< RWKPRCVD (Bit 6)                                      */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKPRCVD_Msk                        (0x40UL)       /*!< RWKPRCVD (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_PMT_Control_Status_GLBLUCAST_Pos                       (9UL)          /*!< GLBLUCAST (Bit 9)                                     */
+ #define R_GMAC1_MAC_PMT_Control_Status_GLBLUCAST_Msk                       (0x200UL)      /*!< GLBLUCAST (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKPFE_Pos                          (10UL)         /*!< RWKPFE (Bit 10)                                       */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKPFE_Msk                          (0x400UL)      /*!< RWKPFE (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKPTR_Pos                          (24UL)         /*!< RWKPTR (Bit 24)                                       */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKPTR_Msk                          (0x1f000000UL) /*!< RWKPTR (Bitfield-Mask: 0x1f)                          */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKFILTRST_Pos                      (31UL)         /*!< RWKFILTRST (Bit 31)                                   */
+ #define R_GMAC1_MAC_PMT_Control_Status_RWKFILTRST_Msk                      (0x80000000UL) /*!< RWKFILTRST (Bitfield-Mask: 0x01)                     */
+/* =================================================  MAC_RWK_Packet_Filter  ================================================= */
+ #define R_GMAC1_MAC_RWK_Packet_Filter_WKUPFRMFTR_Pos                       (0UL)          /*!< WKUPFRMFTR (Bit 0)                                    */
+ #define R_GMAC1_MAC_RWK_Packet_Filter_WKUPFRMFTR_Msk                       (0xffffffffUL) /*!< WKUPFRMFTR (Bitfield-Mask: 0xffffffff)                */
+/* ================================================  MAC_LPI_Control_Status  ================================================= */
+ #define R_GMAC1_MAC_LPI_Control_Status_TLPIEN_Pos                          (0UL)          /*!< TLPIEN (Bit 0)                                        */
+ #define R_GMAC1_MAC_LPI_Control_Status_TLPIEN_Msk                          (0x1UL)        /*!< TLPIEN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_LPI_Control_Status_TLPIEX_Pos                          (1UL)          /*!< TLPIEX (Bit 1)                                        */
+ #define R_GMAC1_MAC_LPI_Control_Status_TLPIEX_Msk                          (0x2UL)        /*!< TLPIEX (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_LPI_Control_Status_RLPIEN_Pos                          (2UL)          /*!< RLPIEN (Bit 2)                                        */
+ #define R_GMAC1_MAC_LPI_Control_Status_RLPIEN_Msk                          (0x4UL)        /*!< RLPIEN (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_LPI_Control_Status_RLPIEX_Pos                          (3UL)          /*!< RLPIEX (Bit 3)                                        */
+ #define R_GMAC1_MAC_LPI_Control_Status_RLPIEX_Msk                          (0x8UL)        /*!< RLPIEX (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_LPI_Control_Status_TLPIST_Pos                          (8UL)          /*!< TLPIST (Bit 8)                                        */
+ #define R_GMAC1_MAC_LPI_Control_Status_TLPIST_Msk                          (0x100UL)      /*!< TLPIST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_LPI_Control_Status_RLPIST_Pos                          (9UL)          /*!< RLPIST (Bit 9)                                        */
+ #define R_GMAC1_MAC_LPI_Control_Status_RLPIST_Msk                          (0x200UL)      /*!< RLPIST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_LPI_Control_Status_LPIEN_Pos                           (16UL)         /*!< LPIEN (Bit 16)                                        */
+ #define R_GMAC1_MAC_LPI_Control_Status_LPIEN_Msk                           (0x10000UL)    /*!< LPIEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_LPI_Control_Status_PLS_Pos                             (17UL)         /*!< PLS (Bit 17)                                          */
+ #define R_GMAC1_MAC_LPI_Control_Status_PLS_Msk                             (0x20000UL)    /*!< PLS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_LPI_Control_Status_LPITXA_Pos                          (19UL)         /*!< LPITXA (Bit 19)                                       */
+ #define R_GMAC1_MAC_LPI_Control_Status_LPITXA_Msk                          (0x80000UL)    /*!< LPITXA (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_LPI_Control_Status_LPIATE_Pos                          (20UL)         /*!< LPIATE (Bit 20)                                       */
+ #define R_GMAC1_MAC_LPI_Control_Status_LPIATE_Msk                          (0x100000UL)   /*!< LPIATE (Bitfield-Mask: 0x01)                          */
+/* ================================================  MAC_LPI_Timers_Control  ================================================= */
+ #define R_GMAC1_MAC_LPI_Timers_Control_TWT_Pos                             (0UL)          /*!< TWT (Bit 0)                                           */
+ #define R_GMAC1_MAC_LPI_Timers_Control_TWT_Msk                             (0xffffUL)     /*!< TWT (Bitfield-Mask: 0xffff)                           */
+ #define R_GMAC1_MAC_LPI_Timers_Control_LST_Pos                             (16UL)         /*!< LST (Bit 16)                                          */
+ #define R_GMAC1_MAC_LPI_Timers_Control_LST_Msk                             (0x3ff0000UL)  /*!< LST (Bitfield-Mask: 0x3ff)                            */
+/* ==================================================  MAC_LPI_Entry_Timer  ================================================== */
+ #define R_GMAC1_MAC_LPI_Entry_Timer_LPIET_Pos                              (3UL)          /*!< LPIET (Bit 3)                                         */
+ #define R_GMAC1_MAC_LPI_Entry_Timer_LPIET_Msk                              (0xffff8UL)    /*!< LPIET (Bitfield-Mask: 0x1ffff)                        */
+/* ==================================================  MAC_1US_Tic_Counter  ================================================== */
+ #define R_GMAC1_MAC_1US_Tic_Counter_TIC_1US_CNTR_Pos                       (0UL)          /*!< TIC_1US_CNTR (Bit 0)                                  */
+ #define R_GMAC1_MAC_1US_Tic_Counter_TIC_1US_CNTR_Msk                       (0xfffUL)      /*!< TIC_1US_CNTR (Bitfield-Mask: 0xfff)                   */
+/* ======================================================  MAC_Version  ====================================================== */
+ #define R_GMAC1_MAC_Version_VER_Pos                                        (0UL)          /*!< VER (Bit 0)                                           */
+ #define R_GMAC1_MAC_Version_VER_Msk                                        (0xffffUL)     /*!< VER (Bitfield-Mask: 0xffff)                           */
+/* =======================================================  MAC_Debug  ======================================================= */
+ #define R_GMAC1_MAC_Debug_RPESTS_Pos                                       (0UL)          /*!< RPESTS (Bit 0)                                        */
+ #define R_GMAC1_MAC_Debug_RPESTS_Msk                                       (0x1UL)        /*!< RPESTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Debug_RFCFCSTS_Pos                                     (1UL)          /*!< RFCFCSTS (Bit 1)                                      */
+ #define R_GMAC1_MAC_Debug_RFCFCSTS_Msk                                     (0x6UL)        /*!< RFCFCSTS (Bitfield-Mask: 0x03)                        */
+ #define R_GMAC1_MAC_Debug_TPESTS_Pos                                       (16UL)         /*!< TPESTS (Bit 16)                                       */
+ #define R_GMAC1_MAC_Debug_TPESTS_Msk                                       (0x10000UL)    /*!< TPESTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Debug_TFCSTS_Pos                                       (17UL)         /*!< TFCSTS (Bit 17)                                       */
+ #define R_GMAC1_MAC_Debug_TFCSTS_Msk                                       (0x60000UL)    /*!< TFCSTS (Bitfield-Mask: 0x03)                          */
+/* ====================================================  MAC_HW_Feature0  ==================================================== */
+ #define R_GMAC1_MAC_HW_Feature0_MIISEL_Pos                                 (0UL)          /*!< MIISEL (Bit 0)                                        */
+ #define R_GMAC1_MAC_HW_Feature0_MIISEL_Msk                                 (0x1UL)        /*!< MIISEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature0_GMIISEL_Pos                                (1UL)          /*!< GMIISEL (Bit 1)                                       */
+ #define R_GMAC1_MAC_HW_Feature0_GMIISEL_Msk                                (0x2UL)        /*!< GMIISEL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_HW_Feature0_HDSEL_Pos                                  (2UL)          /*!< HDSEL (Bit 2)                                         */
+ #define R_GMAC1_MAC_HW_Feature0_HDSEL_Msk                                  (0x4UL)        /*!< HDSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_HW_Feature0_VLHASH_Pos                                 (4UL)          /*!< VLHASH (Bit 4)                                        */
+ #define R_GMAC1_MAC_HW_Feature0_VLHASH_Msk                                 (0x10UL)       /*!< VLHASH (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature0_SMASEL_Pos                                 (5UL)          /*!< SMASEL (Bit 5)                                        */
+ #define R_GMAC1_MAC_HW_Feature0_SMASEL_Msk                                 (0x20UL)       /*!< SMASEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature0_RWKSEL_Pos                                 (6UL)          /*!< RWKSEL (Bit 6)                                        */
+ #define R_GMAC1_MAC_HW_Feature0_RWKSEL_Msk                                 (0x40UL)       /*!< RWKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature0_MGKSEL_Pos                                 (7UL)          /*!< MGKSEL (Bit 7)                                        */
+ #define R_GMAC1_MAC_HW_Feature0_MGKSEL_Msk                                 (0x80UL)       /*!< MGKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature0_MMCSEL_Pos                                 (8UL)          /*!< MMCSEL (Bit 8)                                        */
+ #define R_GMAC1_MAC_HW_Feature0_MMCSEL_Msk                                 (0x100UL)      /*!< MMCSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature0_ARPOFFSEL_Pos                              (9UL)          /*!< ARPOFFSEL (Bit 9)                                     */
+ #define R_GMAC1_MAC_HW_Feature0_ARPOFFSEL_Msk                              (0x200UL)      /*!< ARPOFFSEL (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_HW_Feature0_TSSEL_Pos                                  (12UL)         /*!< TSSEL (Bit 12)                                        */
+ #define R_GMAC1_MAC_HW_Feature0_TSSEL_Msk                                  (0x1000UL)     /*!< TSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_HW_Feature0_EEESEL_Pos                                 (13UL)         /*!< EEESEL (Bit 13)                                       */
+ #define R_GMAC1_MAC_HW_Feature0_EEESEL_Msk                                 (0x2000UL)     /*!< EEESEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature0_TXCOESEL_Pos                               (14UL)         /*!< TXCOESEL (Bit 14)                                     */
+ #define R_GMAC1_MAC_HW_Feature0_TXCOESEL_Msk                               (0x4000UL)     /*!< TXCOESEL (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_HW_Feature0_RXCOESEL_Pos                               (16UL)         /*!< RXCOESEL (Bit 16)                                     */
+ #define R_GMAC1_MAC_HW_Feature0_RXCOESEL_Msk                               (0x10000UL)    /*!< RXCOESEL (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_HW_Feature0_ADDMACADRSEL_Pos                           (18UL)         /*!< ADDMACADRSEL (Bit 18)                                 */
+ #define R_GMAC1_MAC_HW_Feature0_ADDMACADRSEL_Msk                           (0x7c0000UL)   /*!< ADDMACADRSEL (Bitfield-Mask: 0x1f)                    */
+ #define R_GMAC1_MAC_HW_Feature0_TSSTSSEL_Pos                               (25UL)         /*!< TSSTSSEL (Bit 25)                                     */
+ #define R_GMAC1_MAC_HW_Feature0_TSSTSSEL_Msk                               (0x6000000UL)  /*!< TSSTSSEL (Bitfield-Mask: 0x03)                        */
+/* ====================================================  MAC_HW_Feature1  ==================================================== */
+ #define R_GMAC1_MAC_HW_Feature1_RXFIFOSIZE_Pos                             (0UL)          /*!< RXFIFOSIZE (Bit 0)                                    */
+ #define R_GMAC1_MAC_HW_Feature1_RXFIFOSIZE_Msk                             (0x1fUL)       /*!< RXFIFOSIZE (Bitfield-Mask: 0x1f)                      */
+ #define R_GMAC1_MAC_HW_Feature1_TXFIFOSIZE_Pos                             (6UL)          /*!< TXFIFOSIZE (Bit 6)                                    */
+ #define R_GMAC1_MAC_HW_Feature1_TXFIFOSIZE_Msk                             (0x7c0UL)      /*!< TXFIFOSIZE (Bitfield-Mask: 0x1f)                      */
+ #define R_GMAC1_MAC_HW_Feature1_OSTEN_Pos                                  (11UL)         /*!< OSTEN (Bit 11)                                        */
+ #define R_GMAC1_MAC_HW_Feature1_OSTEN_Msk                                  (0x800UL)      /*!< OSTEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_HW_Feature1_PTOEN_Pos                                  (12UL)         /*!< PTOEN (Bit 12)                                        */
+ #define R_GMAC1_MAC_HW_Feature1_PTOEN_Msk                                  (0x1000UL)     /*!< PTOEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_HW_Feature1_ADDR64_Pos                                 (14UL)         /*!< ADDR64 (Bit 14)                                       */
+ #define R_GMAC1_MAC_HW_Feature1_ADDR64_Msk                                 (0xc000UL)     /*!< ADDR64 (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_HW_Feature1_SPHEN_Pos                                  (17UL)         /*!< SPHEN (Bit 17)                                        */
+ #define R_GMAC1_MAC_HW_Feature1_SPHEN_Msk                                  (0x20000UL)    /*!< SPHEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_HW_Feature1_AVSEL_Pos                                  (20UL)         /*!< AVSEL (Bit 20)                                        */
+ #define R_GMAC1_MAC_HW_Feature1_AVSEL_Msk                                  (0x100000UL)   /*!< AVSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_HW_Feature1_POUOST_Pos                                 (23UL)         /*!< POUOST (Bit 23)                                       */
+ #define R_GMAC1_MAC_HW_Feature1_POUOST_Msk                                 (0x800000UL)   /*!< POUOST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature1_HASHTBLSZ_Pos                              (24UL)         /*!< HASHTBLSZ (Bit 24)                                    */
+ #define R_GMAC1_MAC_HW_Feature1_HASHTBLSZ_Msk                              (0x3000000UL)  /*!< HASHTBLSZ (Bitfield-Mask: 0x03)                       */
+ #define R_GMAC1_MAC_HW_Feature1_L3L4FNUM_Pos                               (27UL)         /*!< L3L4FNUM (Bit 27)                                     */
+ #define R_GMAC1_MAC_HW_Feature1_L3L4FNUM_Msk                               (0x78000000UL) /*!< L3L4FNUM (Bitfield-Mask: 0x0f)                        */
+/* ====================================================  MAC_HW_Feature2  ==================================================== */
+ #define R_GMAC1_MAC_HW_Feature2_RXQCNT_Pos                                 (0UL)          /*!< RXQCNT (Bit 0)                                        */
+ #define R_GMAC1_MAC_HW_Feature2_RXQCNT_Msk                                 (0xfUL)        /*!< RXQCNT (Bitfield-Mask: 0x0f)                          */
+ #define R_GMAC1_MAC_HW_Feature2_TXQCNT_Pos                                 (6UL)          /*!< TXQCNT (Bit 6)                                        */
+ #define R_GMAC1_MAC_HW_Feature2_TXQCNT_Msk                                 (0x3c0UL)      /*!< TXQCNT (Bitfield-Mask: 0x0f)                          */
+ #define R_GMAC1_MAC_HW_Feature2_RXCHCNT_Pos                                (12UL)         /*!< RXCHCNT (Bit 12)                                      */
+ #define R_GMAC1_MAC_HW_Feature2_RXCHCNT_Msk                                (0xf000UL)     /*!< RXCHCNT (Bitfield-Mask: 0x0f)                         */
+ #define R_GMAC1_MAC_HW_Feature2_TXCHCNT_Pos                                (18UL)         /*!< TXCHCNT (Bit 18)                                      */
+ #define R_GMAC1_MAC_HW_Feature2_TXCHCNT_Msk                                (0x3c0000UL)   /*!< TXCHCNT (Bitfield-Mask: 0x0f)                         */
+ #define R_GMAC1_MAC_HW_Feature2_AUXSNAPNUM_Pos                             (28UL)         /*!< AUXSNAPNUM (Bit 28)                                   */
+ #define R_GMAC1_MAC_HW_Feature2_AUXSNAPNUM_Msk                             (0x70000000UL) /*!< AUXSNAPNUM (Bitfield-Mask: 0x07)                      */
+/* ====================================================  MAC_HW_Feature3  ==================================================== */
+ #define R_GMAC1_MAC_HW_Feature3_NRVF_Pos                                   (0UL)          /*!< NRVF (Bit 0)                                          */
+ #define R_GMAC1_MAC_HW_Feature3_NRVF_Msk                                   (0x7UL)        /*!< NRVF (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MAC_HW_Feature3_DVLAN_Pos                                  (5UL)          /*!< DVLAN (Bit 5)                                         */
+ #define R_GMAC1_MAC_HW_Feature3_DVLAN_Msk                                  (0x20UL)       /*!< DVLAN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_HW_Feature3_PDUPSEL_Pos                                (9UL)          /*!< PDUPSEL (Bit 9)                                       */
+ #define R_GMAC1_MAC_HW_Feature3_PDUPSEL_Msk                                (0x200UL)      /*!< PDUPSEL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_HW_Feature3_ESTSEL_Pos                                 (16UL)         /*!< ESTSEL (Bit 16)                                       */
+ #define R_GMAC1_MAC_HW_Feature3_ESTSEL_Msk                                 (0x10000UL)    /*!< ESTSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature3_ESTDEP_Pos                                 (17UL)         /*!< ESTDEP (Bit 17)                                       */
+ #define R_GMAC1_MAC_HW_Feature3_ESTDEP_Msk                                 (0xe0000UL)    /*!< ESTDEP (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_HW_Feature3_ESTWID_Pos                                 (20UL)         /*!< ESTWID (Bit 20)                                       */
+ #define R_GMAC1_MAC_HW_Feature3_ESTWID_Msk                                 (0x300000UL)   /*!< ESTWID (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_HW_Feature3_FPESEL_Pos                                 (26UL)         /*!< FPESEL (Bit 26)                                       */
+ #define R_GMAC1_MAC_HW_Feature3_FPESEL_Msk                                 (0x4000000UL)  /*!< FPESEL (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_HW_Feature3_TBSSEL_Pos                                 (27UL)         /*!< TBSSEL (Bit 27)                                       */
+ #define R_GMAC1_MAC_HW_Feature3_TBSSEL_Msk                                 (0x8000000UL)  /*!< TBSSEL (Bitfield-Mask: 0x01)                          */
+/* ===================================================  MAC_MDIO_Address  ==================================================== */
+ #define R_GMAC1_MAC_MDIO_Address_GB_Pos                                    (0UL)          /*!< GB (Bit 0)                                            */
+ #define R_GMAC1_MAC_MDIO_Address_GB_Msk                                    (0x1UL)        /*!< GB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_MDIO_Address_C45E_Pos                                  (1UL)          /*!< C45E (Bit 1)                                          */
+ #define R_GMAC1_MAC_MDIO_Address_C45E_Msk                                  (0x2UL)        /*!< C45E (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_MDIO_Address_GOC_Pos                                   (2UL)          /*!< GOC (Bit 2)                                           */
+ #define R_GMAC1_MAC_MDIO_Address_GOC_Msk                                   (0xcUL)        /*!< GOC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MAC_MDIO_Address_SKAP_Pos                                  (4UL)          /*!< SKAP (Bit 4)                                          */
+ #define R_GMAC1_MAC_MDIO_Address_SKAP_Msk                                  (0x10UL)       /*!< SKAP (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_MDIO_Address_CR_Pos                                    (8UL)          /*!< CR (Bit 8)                                            */
+ #define R_GMAC1_MAC_MDIO_Address_CR_Msk                                    (0xf00UL)      /*!< CR (Bitfield-Mask: 0x0f)                              */
+ #define R_GMAC1_MAC_MDIO_Address_NTC_Pos                                   (12UL)         /*!< NTC (Bit 12)                                          */
+ #define R_GMAC1_MAC_MDIO_Address_NTC_Msk                                   (0x7000UL)     /*!< NTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MAC_MDIO_Address_RDA_Pos                                   (16UL)         /*!< RDA (Bit 16)                                          */
+ #define R_GMAC1_MAC_MDIO_Address_RDA_Msk                                   (0x1f0000UL)   /*!< RDA (Bitfield-Mask: 0x1f)                             */
+ #define R_GMAC1_MAC_MDIO_Address_PA_Pos                                    (21UL)         /*!< PA (Bit 21)                                           */
+ #define R_GMAC1_MAC_MDIO_Address_PA_Msk                                    (0x3e00000UL)  /*!< PA (Bitfield-Mask: 0x1f)                              */
+ #define R_GMAC1_MAC_MDIO_Address_BTB_Pos                                   (26UL)         /*!< BTB (Bit 26)                                          */
+ #define R_GMAC1_MAC_MDIO_Address_BTB_Msk                                   (0x4000000UL)  /*!< BTB (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_MDIO_Address_PSE_Pos                                   (27UL)         /*!< PSE (Bit 27)                                          */
+ #define R_GMAC1_MAC_MDIO_Address_PSE_Msk                                   (0x8000000UL)  /*!< PSE (Bitfield-Mask: 0x01)                             */
+/* =====================================================  MAC_MDIO_Data  ===================================================== */
+ #define R_GMAC1_MAC_MDIO_Data_GD_Pos                                       (0UL)          /*!< GD (Bit 0)                                            */
+ #define R_GMAC1_MAC_MDIO_Data_GD_Msk                                       (0xffffUL)     /*!< GD (Bitfield-Mask: 0xffff)                            */
+ #define R_GMAC1_MAC_MDIO_Data_RA_Pos                                       (16UL)         /*!< RA (Bit 16)                                           */
+ #define R_GMAC1_MAC_MDIO_Data_RA_Msk                                       (0xffff0000UL) /*!< RA (Bitfield-Mask: 0xffff)                            */
+/* ====================================================  MAC_ARP_Address  ==================================================== */
+ #define R_GMAC1_MAC_ARP_Address_ARPPA_Pos                                  (0UL)          /*!< ARPPA (Bit 0)                                         */
+ #define R_GMAC1_MAC_ARP_Address_ARPPA_Msk                                  (0xffffffffUL) /*!< ARPPA (Bitfield-Mask: 0xffffffff)                     */
+/* ====================================================  MAC_CSR_SW_Ctrl  ==================================================== */
+ #define R_GMAC1_MAC_CSR_SW_Ctrl_RCWE_Pos                                   (0UL)          /*!< RCWE (Bit 0)                                          */
+ #define R_GMAC1_MAC_CSR_SW_Ctrl_RCWE_Msk                                   (0x1UL)        /*!< RCWE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_CSR_SW_Ctrl_SEEN_Pos                                   (8UL)          /*!< SEEN (Bit 8)                                          */
+ #define R_GMAC1_MAC_CSR_SW_Ctrl_SEEN_Msk                                   (0x100UL)      /*!< SEEN (Bitfield-Mask: 0x01)                            */
+/* ===================================================  MAC_FPE_CTRL_STS  ==================================================== */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_EFPE_Pos                                  (0UL)          /*!< EFPE (Bit 0)                                          */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_EFPE_Msk                                  (0x1UL)        /*!< EFPE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_SVER_Pos                                  (1UL)          /*!< SVER (Bit 1)                                          */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_SVER_Msk                                  (0x2UL)        /*!< SVER (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_SRSP_Pos                                  (2UL)          /*!< SRSP (Bit 2)                                          */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_SRSP_Msk                                  (0x4UL)        /*!< SRSP (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_S1_SET_0_Pos                              (3UL)          /*!< S1_SET_0 (Bit 3)                                      */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_S1_SET_0_Msk                              (0x8UL)        /*!< S1_SET_0 (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_RVER_Pos                                  (16UL)         /*!< RVER (Bit 16)                                         */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_RVER_Msk                                  (0x10000UL)    /*!< RVER (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_RRSP_Pos                                  (17UL)         /*!< RRSP (Bit 17)                                         */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_RRSP_Msk                                  (0x20000UL)    /*!< RRSP (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_TVER_Pos                                  (18UL)         /*!< TVER (Bit 18)                                         */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_TVER_Msk                                  (0x40000UL)    /*!< TVER (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_TRSP_Pos                                  (19UL)         /*!< TRSP (Bit 19)                                         */
+ #define R_GMAC1_MAC_FPE_CTRL_STS_TRSP_Msk                                  (0x80000UL)    /*!< TRSP (Bitfield-Mask: 0x01)                            */
+/* =====================================================  MAC_Ext_Cfg1  ====================================================== */
+ #define R_GMAC1_MAC_Ext_Cfg1_SPLOFST_Pos                                   (0UL)          /*!< SPLOFST (Bit 0)                                       */
+ #define R_GMAC1_MAC_Ext_Cfg1_SPLOFST_Msk                                   (0x7fUL)       /*!< SPLOFST (Bitfield-Mask: 0x7f)                         */
+ #define R_GMAC1_MAC_Ext_Cfg1_SPLM_Pos                                      (8UL)          /*!< SPLM (Bit 8)                                          */
+ #define R_GMAC1_MAC_Ext_Cfg1_SPLM_Msk                                      (0x300UL)      /*!< SPLM (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC1_MAC_Ext_Cfg1_SAVO_Pos                                      (16UL)         /*!< SAVO (Bit 16)                                         */
+ #define R_GMAC1_MAC_Ext_Cfg1_SAVO_Msk                                      (0x7f0000UL)   /*!< SAVO (Bitfield-Mask: 0x7f)                            */
+ #define R_GMAC1_MAC_Ext_Cfg1_SAVE_Pos                                      (24UL)         /*!< SAVE (Bit 24)                                         */
+ #define R_GMAC1_MAC_Ext_Cfg1_SAVE_Msk                                      (0x1000000UL)  /*!< SAVE (Bitfield-Mask: 0x01)                            */
+/* ===================================================  MAC_ADDRESS0_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS0_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS0_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS0_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS0_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS0_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS0_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS0_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS0_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS0_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS1_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS1_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS2_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS2_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS3_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS3_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS4_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS4_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS5_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS5_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS6_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS6_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS7_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS7_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS8_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS8_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS9_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_ADDRHI_Pos                               (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_ADDRHI_Msk                               (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_DCS_Pos                                  (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_DCS_Msk                                  (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_MBC_Pos                                  (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_MBC_Msk                                  (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_SA_Pos                                   (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_SA_Msk                                   (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_AE_Pos                                   (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS9_HIGH_AE_Msk                                   (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS10_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS10_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS11_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS11_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS12_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS12_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS13_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS13_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS14_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS14_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS15_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS15_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS16_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS16_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS17_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS17_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS18_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS18_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS19_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS19_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS20_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS20_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS21_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS21_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS22_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS22_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS23_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS23_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS24_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS24_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS25_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS25_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS26_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS26_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS27_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS27_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS28_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS28_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS29_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS29_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS30_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS30_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ==================================================  MAC_ADDRESS31_HIGH  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_ADDRHI_Pos                              (0UL)          /*!< ADDRHI (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_ADDRHI_Msk                              (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_DCS_Pos                                 (16UL)         /*!< DCS (Bit 16)                                          */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_DCS_Msk                                 (0xff0000UL)   /*!< DCS (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_MBC_Pos                                 (24UL)         /*!< MBC (Bit 24)                                          */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_MBC_Msk                                 (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_SA_Pos                                  (30UL)         /*!< SA (Bit 30)                                           */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_SA_Msk                                  (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_AE_Pos                                  (31UL)         /*!< AE (Bit 31)                                           */
+ #define R_GMAC1_MAC_ADDRESS31_HIGH_AE_Msk                                  (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
+/* ===================================================  MAC_ADDRESS1_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS1_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS1_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS2_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS2_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS2_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS3_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS3_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS3_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS4_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS4_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS4_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS5_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS5_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS5_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS6_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS6_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS6_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS7_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS7_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS7_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS8_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS8_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS8_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS9_LOW  ==================================================== */
+ #define R_GMAC1_MAC_ADDRESS9_LOW_ADDRLO_Pos                                (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS9_LOW_ADDRLO_Msk                                (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS10_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS10_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS10_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS11_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS11_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS11_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS12_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS12_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS12_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS13_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS13_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS13_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS14_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS14_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS14_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS15_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS15_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS15_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS16_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS16_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS16_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS17_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS17_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS17_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS18_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS18_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS18_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS19_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS19_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS19_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS20_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS20_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS20_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS21_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS21_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS21_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS22_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS22_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS22_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS23_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS23_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS23_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS24_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS24_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS24_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS25_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS25_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS25_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS26_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS26_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS26_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS27_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS27_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS27_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS28_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS28_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS28_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS29_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS29_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS29_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS30_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS30_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS30_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  MAC_ADDRESS31_LOW  =================================================== */
+ #define R_GMAC1_MAC_ADDRESS31_LOW_ADDRLO_Pos                               (0UL)          /*!< ADDRLO (Bit 0)                                        */
+ #define R_GMAC1_MAC_ADDRESS31_LOW_ADDRLO_Msk                               (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
+/* ======================================================  MMC_Control  ====================================================== */
+ #define R_GMAC1_MMC_Control_CNTRST_Pos                                     (0UL)          /*!< CNTRST (Bit 0)                                        */
+ #define R_GMAC1_MMC_Control_CNTRST_Msk                                     (0x1UL)        /*!< CNTRST (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MMC_Control_CNTSTOPRO_Pos                                  (1UL)          /*!< CNTSTOPRO (Bit 1)                                     */
+ #define R_GMAC1_MMC_Control_CNTSTOPRO_Msk                                  (0x2UL)        /*!< CNTSTOPRO (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Control_RSTONRD_Pos                                    (2UL)          /*!< RSTONRD (Bit 2)                                       */
+ #define R_GMAC1_MMC_Control_RSTONRD_Msk                                    (0x4UL)        /*!< RSTONRD (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MMC_Control_CNTFREEZ_Pos                                   (3UL)          /*!< CNTFREEZ (Bit 3)                                      */
+ #define R_GMAC1_MMC_Control_CNTFREEZ_Msk                                   (0x8UL)        /*!< CNTFREEZ (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Control_CNTPRST_Pos                                    (4UL)          /*!< CNTPRST (Bit 4)                                       */
+ #define R_GMAC1_MMC_Control_CNTPRST_Msk                                    (0x10UL)       /*!< CNTPRST (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MMC_Control_CNTPRSTLVL_Pos                                 (5UL)          /*!< CNTPRSTLVL (Bit 5)                                    */
+ #define R_GMAC1_MMC_Control_CNTPRSTLVL_Msk                                 (0x20UL)       /*!< CNTPRSTLVL (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Control_UCDBC_Pos                                      (8UL)          /*!< UCDBC (Bit 8)                                         */
+ #define R_GMAC1_MMC_Control_UCDBC_Msk                                      (0x100UL)      /*!< UCDBC (Bitfield-Mask: 0x01)                           */
+/* ===================================================  MMC_Rx_Interrupt  ==================================================== */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXGBPKTIS_Pos                             (0UL)          /*!< RXGBPKTIS (Bit 0)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXGBPKTIS_Msk                             (0x1UL)        /*!< RXGBPKTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXGBOCTIS_Pos                             (1UL)          /*!< RXGBOCTIS (Bit 1)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXGBOCTIS_Msk                             (0x2UL)        /*!< RXGBOCTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXGOCTIS_Pos                              (2UL)          /*!< RXGOCTIS (Bit 2)                                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXGOCTIS_Msk                              (0x4UL)        /*!< RXGOCTIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXBCGPIS_Pos                              (3UL)          /*!< RXBCGPIS (Bit 3)                                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXBCGPIS_Msk                              (0x8UL)        /*!< RXBCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXMCGPIS_Pos                              (4UL)          /*!< RXMCGPIS (Bit 4)                                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXMCGPIS_Msk                              (0x10UL)       /*!< RXMCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXCRCERPIS_Pos                            (5UL)          /*!< RXCRCERPIS (Bit 5)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXCRCERPIS_Msk                            (0x20UL)       /*!< RXCRCERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXALGNERPIS_Pos                           (6UL)          /*!< RXALGNERPIS (Bit 6)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXALGNERPIS_Msk                           (0x40UL)       /*!< RXALGNERPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXRUNTPIS_Pos                             (7UL)          /*!< RXRUNTPIS (Bit 7)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXRUNTPIS_Msk                             (0x80UL)       /*!< RXRUNTPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXJABERPIS_Pos                            (8UL)          /*!< RXJABERPIS (Bit 8)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXJABERPIS_Msk                            (0x100UL)      /*!< RXJABERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXUSIZEGPIS_Pos                           (9UL)          /*!< RXUSIZEGPIS (Bit 9)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXUSIZEGPIS_Msk                           (0x200UL)      /*!< RXUSIZEGPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXOSIZEGPIS_Pos                           (10UL)         /*!< RXOSIZEGPIS (Bit 10)                                  */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXOSIZEGPIS_Msk                           (0x400UL)      /*!< RXOSIZEGPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX64OCTGBPIS_Pos                          (11UL)         /*!< RX64OCTGBPIS (Bit 11)                                 */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX64OCTGBPIS_Msk                          (0x800UL)      /*!< RX64OCTGBPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX65T127OCTGBPIS_Pos                      (12UL)         /*!< RX65T127OCTGBPIS (Bit 12)                             */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX65T127OCTGBPIS_Msk                      (0x1000UL)     /*!< RX65T127OCTGBPIS (Bitfield-Mask: 0x01)                */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX128T255OCTGBPIS_Pos                     (13UL)         /*!< RX128T255OCTGBPIS (Bit 13)                            */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX128T255OCTGBPIS_Msk                     (0x2000UL)     /*!< RX128T255OCTGBPIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX256T511OCTGBPIS_Pos                     (14UL)         /*!< RX256T511OCTGBPIS (Bit 14)                            */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX256T511OCTGBPIS_Msk                     (0x4000UL)     /*!< RX256T511OCTGBPIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX512T1023OCTGBPIS_Pos                    (15UL)         /*!< RX512T1023OCTGBPIS (Bit 15)                           */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX512T1023OCTGBPIS_Msk                    (0x8000UL)     /*!< RX512T1023OCTGBPIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX1024TMAXOCTGBPIS_Pos                    (16UL)         /*!< RX1024TMAXOCTGBPIS (Bit 16)                           */
+ #define R_GMAC1_MMC_Rx_Interrupt_RX1024TMAXOCTGBPIS_Msk                    (0x10000UL)    /*!< RX1024TMAXOCTGBPIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXUCGPIS_Pos                              (17UL)         /*!< RXUCGPIS (Bit 17)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXUCGPIS_Msk                              (0x20000UL)    /*!< RXUCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXLENERPIS_Pos                            (18UL)         /*!< RXLENERPIS (Bit 18)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXLENERPIS_Msk                            (0x40000UL)    /*!< RXLENERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXORANGEPIS_Pos                           (19UL)         /*!< RXORANGEPIS (Bit 19)                                  */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXORANGEPIS_Msk                           (0x80000UL)    /*!< RXORANGEPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXPAUSPIS_Pos                             (20UL)         /*!< RXPAUSPIS (Bit 20)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXPAUSPIS_Msk                             (0x100000UL)   /*!< RXPAUSPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXFOVPIS_Pos                              (21UL)         /*!< RXFOVPIS (Bit 21)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXFOVPIS_Msk                              (0x200000UL)   /*!< RXFOVPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXVLANGBPIS_Pos                           (22UL)         /*!< RXVLANGBPIS (Bit 22)                                  */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXVLANGBPIS_Msk                           (0x400000UL)   /*!< RXVLANGBPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXWDOGPIS_Pos                             (23UL)         /*!< RXWDOGPIS (Bit 23)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXWDOGPIS_Msk                             (0x800000UL)   /*!< RXWDOGPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXRCVERRPIS_Pos                           (24UL)         /*!< RXRCVERRPIS (Bit 24)                                  */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXRCVERRPIS_Msk                           (0x1000000UL)  /*!< RXRCVERRPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXCTRLPIS_Pos                             (25UL)         /*!< RXCTRLPIS (Bit 25)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXCTRLPIS_Msk                             (0x2000000UL)  /*!< RXCTRLPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXLPIUSCIS_Pos                            (26UL)         /*!< RXLPIUSCIS (Bit 26)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXLPIUSCIS_Msk                            (0x4000000UL)  /*!< RXLPIUSCIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXLPITRCIS_Pos                            (27UL)         /*!< RXLPITRCIS (Bit 27)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_RXLPITRCIS_Msk                            (0x8000000UL)  /*!< RXLPITRCIS (Bitfield-Mask: 0x01)                      */
+/* ===================================================  MMC_Tx_Interrupt  ==================================================== */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXGBOCTIS_Pos                             (0UL)          /*!< TXGBOCTIS (Bit 0)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXGBOCTIS_Msk                             (0x1UL)        /*!< TXGBOCTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXGBPKTIS_Pos                             (1UL)          /*!< TXGBPKTIS (Bit 1)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXGBPKTIS_Msk                             (0x2UL)        /*!< TXGBPKTIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXBCGPIS_Pos                              (2UL)          /*!< TXBCGPIS (Bit 2)                                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXBCGPIS_Msk                              (0x4UL)        /*!< TXBCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXMCGPIS_Pos                              (3UL)          /*!< TXMCGPIS (Bit 3)                                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXMCGPIS_Msk                              (0x8UL)        /*!< TXMCGPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX64OCTGBPIS_Pos                          (4UL)          /*!< TX64OCTGBPIS (Bit 4)                                  */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX64OCTGBPIS_Msk                          (0x10UL)       /*!< TX64OCTGBPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX65T127OCTGBPIS_Pos                      (5UL)          /*!< TX65T127OCTGBPIS (Bit 5)                              */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX65T127OCTGBPIS_Msk                      (0x20UL)       /*!< TX65T127OCTGBPIS (Bitfield-Mask: 0x01)                */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX128T255OCTGBPIS_Pos                     (6UL)          /*!< TX128T255OCTGBPIS (Bit 6)                             */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX128T255OCTGBPIS_Msk                     (0x40UL)       /*!< TX128T255OCTGBPIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX256T511OCTGBPIS_Pos                     (7UL)          /*!< TX256T511OCTGBPIS (Bit 7)                             */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX256T511OCTGBPIS_Msk                     (0x80UL)       /*!< TX256T511OCTGBPIS (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX512T1023OCTGBPIS_Pos                    (8UL)          /*!< TX512T1023OCTGBPIS (Bit 8)                            */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX512T1023OCTGBPIS_Msk                    (0x100UL)      /*!< TX512T1023OCTGBPIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX1024TMAXOCTGBPIS_Pos                    (9UL)          /*!< TX1024TMAXOCTGBPIS (Bit 9)                            */
+ #define R_GMAC1_MMC_Tx_Interrupt_TX1024TMAXOCTGBPIS_Msk                    (0x200UL)      /*!< TX1024TMAXOCTGBPIS (Bitfield-Mask: 0x01)              */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXUCGBPIS_Pos                             (10UL)         /*!< TXUCGBPIS (Bit 10)                                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXUCGBPIS_Msk                             (0x400UL)      /*!< TXUCGBPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXMCGBPIS_Pos                             (11UL)         /*!< TXMCGBPIS (Bit 11)                                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXMCGBPIS_Msk                             (0x800UL)      /*!< TXMCGBPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXBCGBPIS_Pos                             (12UL)         /*!< TXBCGBPIS (Bit 12)                                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXBCGBPIS_Msk                             (0x1000UL)     /*!< TXBCGBPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXUFLOWERPIS_Pos                          (13UL)         /*!< TXUFLOWERPIS (Bit 13)                                 */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXUFLOWERPIS_Msk                          (0x2000UL)     /*!< TXUFLOWERPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXSCOLGPIS_Pos                            (14UL)         /*!< TXSCOLGPIS (Bit 14)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXSCOLGPIS_Msk                            (0x4000UL)     /*!< TXSCOLGPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXMCOLGPIS_Pos                            (15UL)         /*!< TXMCOLGPIS (Bit 15)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXMCOLGPIS_Msk                            (0x8000UL)     /*!< TXMCOLGPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXDEFPIS_Pos                              (16UL)         /*!< TXDEFPIS (Bit 16)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXDEFPIS_Msk                              (0x10000UL)    /*!< TXDEFPIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXLATCOLPIS_Pos                           (17UL)         /*!< TXLATCOLPIS (Bit 17)                                  */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXLATCOLPIS_Msk                           (0x20000UL)    /*!< TXLATCOLPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXEXCOLPIS_Pos                            (18UL)         /*!< TXEXCOLPIS (Bit 18)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXEXCOLPIS_Msk                            (0x40000UL)    /*!< TXEXCOLPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXCARERPIS_Pos                            (19UL)         /*!< TXCARERPIS (Bit 19)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXCARERPIS_Msk                            (0x80000UL)    /*!< TXCARERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXGOCTIS_Pos                              (20UL)         /*!< TXGOCTIS (Bit 20)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXGOCTIS_Msk                              (0x100000UL)   /*!< TXGOCTIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXGPKTIS_Pos                              (21UL)         /*!< TXGPKTIS (Bit 21)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXGPKTIS_Msk                              (0x200000UL)   /*!< TXGPKTIS (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXEXDEFPIS_Pos                            (22UL)         /*!< TXEXDEFPIS (Bit 22)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXEXDEFPIS_Msk                            (0x400000UL)   /*!< TXEXDEFPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXPAUSPIS_Pos                             (23UL)         /*!< TXPAUSPIS (Bit 23)                                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXPAUSPIS_Msk                             (0x800000UL)   /*!< TXPAUSPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXVLANGPIS_Pos                            (24UL)         /*!< TXVLANGPIS (Bit 24)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXVLANGPIS_Msk                            (0x1000000UL)  /*!< TXVLANGPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXOSIZEGPIS_Pos                           (25UL)         /*!< TXOSIZEGPIS (Bit 25)                                  */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXOSIZEGPIS_Msk                           (0x2000000UL)  /*!< TXOSIZEGPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXLPIUSCIS_Pos                            (26UL)         /*!< TXLPIUSCIS (Bit 26)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXLPIUSCIS_Msk                            (0x4000000UL)  /*!< TXLPIUSCIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXLPITRCIS_Pos                            (27UL)         /*!< TXLPITRCIS (Bit 27)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_TXLPITRCIS_Msk                            (0x8000000UL)  /*!< TXLPITRCIS (Bitfield-Mask: 0x01)                      */
+/* =================================================  MMC_Rx_Interrupt_Mask  ================================================= */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXGBPKTIM_Pos                        (0UL)          /*!< RXGBPKTIM (Bit 0)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXGBPKTIM_Msk                        (0x1UL)        /*!< RXGBPKTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXGBOCTIM_Pos                        (1UL)          /*!< RXGBOCTIM (Bit 1)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXGBOCTIM_Msk                        (0x2UL)        /*!< RXGBOCTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXGOCTIM_Pos                         (2UL)          /*!< RXGOCTIM (Bit 2)                                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXGOCTIM_Msk                         (0x4UL)        /*!< RXGOCTIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXBCGPIM_Pos                         (3UL)          /*!< RXBCGPIM (Bit 3)                                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXBCGPIM_Msk                         (0x8UL)        /*!< RXBCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXMCGPIM_Pos                         (4UL)          /*!< RXMCGPIM (Bit 4)                                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXMCGPIM_Msk                         (0x10UL)       /*!< RXMCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXCRCERPIM_Pos                       (5UL)          /*!< RXCRCERPIM (Bit 5)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXCRCERPIM_Msk                       (0x20UL)       /*!< RXCRCERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXALGNERPIM_Pos                      (6UL)          /*!< RXALGNERPIM (Bit 6)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXALGNERPIM_Msk                      (0x40UL)       /*!< RXALGNERPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXRUNTPIM_Pos                        (7UL)          /*!< RXRUNTPIM (Bit 7)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXRUNTPIM_Msk                        (0x80UL)       /*!< RXRUNTPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXJABERPIM_Pos                       (8UL)          /*!< RXJABERPIM (Bit 8)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXJABERPIM_Msk                       (0x100UL)      /*!< RXJABERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXUSIZEGPIM_Pos                      (9UL)          /*!< RXUSIZEGPIM (Bit 9)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXUSIZEGPIM_Msk                      (0x200UL)      /*!< RXUSIZEGPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXOSIZEGPIM_Pos                      (10UL)         /*!< RXOSIZEGPIM (Bit 10)                                  */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXOSIZEGPIM_Msk                      (0x400UL)      /*!< RXOSIZEGPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX64OCTGBPIM_Pos                     (11UL)         /*!< RX64OCTGBPIM (Bit 11)                                 */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX64OCTGBPIM_Msk                     (0x800UL)      /*!< RX64OCTGBPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX65T127OCTGBPIM_Pos                 (12UL)         /*!< RX65T127OCTGBPIM (Bit 12)                             */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX65T127OCTGBPIM_Msk                 (0x1000UL)     /*!< RX65T127OCTGBPIM (Bitfield-Mask: 0x01)              */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX128T255OCTGBPIM_Pos                (13UL)         /*!< RX128T255OCTGBPIM (Bit 13)                            */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX128T255OCTGBPIM_Msk                (0x2000UL)     /*!< RX128T255OCTGBPIM (Bitfield-Mask: 0x01)            */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX256T511OCTGBPIM_Pos                (14UL)         /*!< RX256T511OCTGBPIM (Bit 14)                            */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX256T511OCTGBPIM_Msk                (0x4000UL)     /*!< RX256T511OCTGBPIM (Bitfield-Mask: 0x01)            */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX512T1023OCTGBPIM_Pos               (15UL)         /*!< RX512T1023OCTGBPIM (Bit 15)                           */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX512T1023OCTGBPIM_Msk               (0x8000UL)     /*!< RX512T1023OCTGBPIM (Bitfield-Mask: 0x01)          */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX1024TMAXOCTGBPIM_Pos               (16UL)         /*!< RX1024TMAXOCTGBPIM (Bit 16)                           */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RX1024TMAXOCTGBPIM_Msk               (0x10000UL)    /*!< RX1024TMAXOCTGBPIM (Bitfield-Mask: 0x01)         */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXUCGPIM_Pos                         (17UL)         /*!< RXUCGPIM (Bit 17)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXUCGPIM_Msk                         (0x20000UL)    /*!< RXUCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXLENERPIM_Pos                       (18UL)         /*!< RXLENERPIM (Bit 18)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXLENERPIM_Msk                       (0x40000UL)    /*!< RXLENERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXORANGEPIM_Pos                      (19UL)         /*!< RXORANGEPIM (Bit 19)                                  */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXORANGEPIM_Msk                      (0x80000UL)    /*!< RXORANGEPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXPAUSPIM_Pos                        (20UL)         /*!< RXPAUSPIM (Bit 20)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXPAUSPIM_Msk                        (0x100000UL)   /*!< RXPAUSPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXFOVPIM_Pos                         (21UL)         /*!< RXFOVPIM (Bit 21)                                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXFOVPIM_Msk                         (0x200000UL)   /*!< RXFOVPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXVLANGBPIM_Pos                      (22UL)         /*!< RXVLANGBPIM (Bit 22)                                  */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXVLANGBPIM_Msk                      (0x400000UL)   /*!< RXVLANGBPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXWDOGPIM_Pos                        (23UL)         /*!< RXWDOGPIM (Bit 23)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXWDOGPIM_Msk                        (0x800000UL)   /*!< RXWDOGPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXRCVERRPIM_Pos                      (24UL)         /*!< RXRCVERRPIM (Bit 24)                                  */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXRCVERRPIM_Msk                      (0x1000000UL)  /*!< RXRCVERRPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXCTRLPIM_Pos                        (25UL)         /*!< RXCTRLPIM (Bit 25)                                    */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXCTRLPIM_Msk                        (0x2000000UL)  /*!< RXCTRLPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXLPIUSCIM_Pos                       (26UL)         /*!< RXLPIUSCIM (Bit 26)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXLPIUSCIM_Msk                       (0x4000000UL)  /*!< RXLPIUSCIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXLPITRCIM_Pos                       (27UL)         /*!< RXLPITRCIM (Bit 27)                                   */
+ #define R_GMAC1_MMC_Rx_Interrupt_Mask_RXLPITRCIM_Msk                       (0x8000000UL)  /*!< RXLPITRCIM (Bitfield-Mask: 0x01)                      */
+/* =================================================  MMC_Tx_Interrupt_Mask  ================================================= */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXGBOCTIM_Pos                        (0UL)          /*!< TXGBOCTIM (Bit 0)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXGBOCTIM_Msk                        (0x1UL)        /*!< TXGBOCTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXGBPKTIM_Pos                        (1UL)          /*!< TXGBPKTIM (Bit 1)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXGBPKTIM_Msk                        (0x2UL)        /*!< TXGBPKTIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXBCGPIM_Pos                         (2UL)          /*!< TXBCGPIM (Bit 2)                                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXBCGPIM_Msk                         (0x4UL)        /*!< TXBCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXMCGPIM_Pos                         (3UL)          /*!< TXMCGPIM (Bit 3)                                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXMCGPIM_Msk                         (0x8UL)        /*!< TXMCGPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX64OCTGBPIM_Pos                     (4UL)          /*!< TX64OCTGBPIM (Bit 4)                                  */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX64OCTGBPIM_Msk                     (0x10UL)       /*!< TX64OCTGBPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX65T127OCTGBPIM_Pos                 (5UL)          /*!< TX65T127OCTGBPIM (Bit 5)                              */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX65T127OCTGBPIM_Msk                 (0x20UL)       /*!< TX65T127OCTGBPIM (Bitfield-Mask: 0x01)                */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX128T255OCTGBPIM_Pos                (6UL)          /*!< TX128T255OCTGBPIM (Bit 6)                             */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX128T255OCTGBPIM_Msk                (0x40UL)       /*!< TX128T255OCTGBPIM (Bitfield-Mask: 0x01)              */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX256T511OCTGBPIM_Pos                (7UL)          /*!< TX256T511OCTGBPIM (Bit 7)                             */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX256T511OCTGBPIM_Msk                (0x80UL)       /*!< TX256T511OCTGBPIM (Bitfield-Mask: 0x01)              */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX512T1023OCTGBPIM_Pos               (8UL)          /*!< TX512T1023OCTGBPIM (Bit 8)                            */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX512T1023OCTGBPIM_Msk               (0x100UL)      /*!< TX512T1023OCTGBPIM (Bitfield-Mask: 0x01)           */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX1024TMAXOCTGBPIM_Pos               (9UL)          /*!< TX1024TMAXOCTGBPIM (Bit 9)                            */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TX1024TMAXOCTGBPIM_Msk               (0x200UL)      /*!< TX1024TMAXOCTGBPIM (Bitfield-Mask: 0x01)           */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXUCGBPIM_Pos                        (10UL)         /*!< TXUCGBPIM (Bit 10)                                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXUCGBPIM_Msk                        (0x400UL)      /*!< TXUCGBPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXMCGBPIM_Pos                        (11UL)         /*!< TXMCGBPIM (Bit 11)                                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXMCGBPIM_Msk                        (0x800UL)      /*!< TXMCGBPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXBCGBPIM_Pos                        (12UL)         /*!< TXBCGBPIM (Bit 12)                                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXBCGBPIM_Msk                        (0x1000UL)     /*!< TXBCGBPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXUFLOWERPIM_Pos                     (13UL)         /*!< TXUFLOWERPIM (Bit 13)                                 */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXUFLOWERPIM_Msk                     (0x2000UL)     /*!< TXUFLOWERPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXSCOLGPIM_Pos                       (14UL)         /*!< TXSCOLGPIM (Bit 14)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXSCOLGPIM_Msk                       (0x4000UL)     /*!< TXSCOLGPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXMCOLGPIM_Pos                       (15UL)         /*!< TXMCOLGPIM (Bit 15)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXMCOLGPIM_Msk                       (0x8000UL)     /*!< TXMCOLGPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXDEFPIM_Pos                         (16UL)         /*!< TXDEFPIM (Bit 16)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXDEFPIM_Msk                         (0x10000UL)    /*!< TXDEFPIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXLATCOLPIM_Pos                      (17UL)         /*!< TXLATCOLPIM (Bit 17)                                  */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXLATCOLPIM_Msk                      (0x20000UL)    /*!< TXLATCOLPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXEXCOLPIM_Pos                       (18UL)         /*!< TXEXCOLPIM (Bit 18)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXEXCOLPIM_Msk                       (0x40000UL)    /*!< TXEXCOLPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXCARERPIM_Pos                       (19UL)         /*!< TXCARERPIM (Bit 19)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXCARERPIM_Msk                       (0x80000UL)    /*!< TXCARERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXGOCTIM_Pos                         (20UL)         /*!< TXGOCTIM (Bit 20)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXGOCTIM_Msk                         (0x100000UL)   /*!< TXGOCTIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXGPKTIM_Pos                         (21UL)         /*!< TXGPKTIM (Bit 21)                                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXGPKTIM_Msk                         (0x200000UL)   /*!< TXGPKTIM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXEXDEFPIM_Pos                       (22UL)         /*!< TXEXDEFPIM (Bit 22)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXEXDEFPIM_Msk                       (0x400000UL)   /*!< TXEXDEFPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXPAUSPIM_Pos                        (23UL)         /*!< TXPAUSPIM (Bit 23)                                    */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXPAUSPIM_Msk                        (0x800000UL)   /*!< TXPAUSPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXVLANGPIM_Pos                       (24UL)         /*!< TXVLANGPIM (Bit 24)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXVLANGPIM_Msk                       (0x1000000UL)  /*!< TXVLANGPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXOSIZEGPIM_Pos                      (25UL)         /*!< TXOSIZEGPIM (Bit 25)                                  */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXOSIZEGPIM_Msk                      (0x2000000UL)  /*!< TXOSIZEGPIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXLPIUSCIM_Pos                       (26UL)         /*!< TXLPIUSCIM (Bit 26)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXLPIUSCIM_Msk                       (0x4000000UL)  /*!< TXLPIUSCIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXLPITRCIM_Pos                       (27UL)         /*!< TXLPITRCIM (Bit 27)                                   */
+ #define R_GMAC1_MMC_Tx_Interrupt_Mask_TXLPITRCIM_Msk                       (0x8000000UL)  /*!< TXLPITRCIM (Bitfield-Mask: 0x01)                      */
+/* ================================================  Tx_Octet_Count_Good_Bad  ================================================ */
+ #define R_GMAC1_Tx_Octet_Count_Good_Bad_TXOCTGB_Pos                        (0UL)          /*!< TXOCTGB (Bit 0)                                       */
+ #define R_GMAC1_Tx_Octet_Count_Good_Bad_TXOCTGB_Msk                        (0xffffffffUL) /*!< TXOCTGB (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Tx_Packet_Count_Good_Bad  ================================================ */
+ #define R_GMAC1_Tx_Packet_Count_Good_Bad_TXPKTGB_Pos                       (0UL)          /*!< TXPKTGB (Bit 0)                                       */
+ #define R_GMAC1_Tx_Packet_Count_Good_Bad_TXPKTGB_Msk                       (0xffffffffUL) /*!< TXPKTGB (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Tx_Broadcast_Packets_Good  =============================================== */
+ #define R_GMAC1_Tx_Broadcast_Packets_Good_TXBCASTG_Pos                     (0UL)          /*!< TXBCASTG (Bit 0)                                      */
+ #define R_GMAC1_Tx_Broadcast_Packets_Good_TXBCASTG_Msk                     (0xffffffffUL) /*!< TXBCASTG (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  Tx_Multicast_Packets_Good  =============================================== */
+ #define R_GMAC1_Tx_Multicast_Packets_Good_TXMCASTG_Pos                     (0UL)          /*!< TXMCASTG (Bit 0)                                      */
+ #define R_GMAC1_Tx_Multicast_Packets_Good_TXMCASTG_Msk                     (0xffffffffUL) /*!< TXMCASTG (Bitfield-Mask: 0xffffffff)                */
+/* =============================================  Tx_64Octets_Packets_Good_Bad  ============================================== */
+ #define R_GMAC1_Tx_64Octets_Packets_Good_Bad_TX64OCTGB_Pos                 (0UL)          /*!< TX64OCTGB (Bit 0)                                     */
+ #define R_GMAC1_Tx_64Octets_Packets_Good_Bad_TX64OCTGB_Msk                 (0xffffffffUL) /*!< TX64OCTGB (Bitfield-Mask: 0xffffffff)           */
+/* ===========================================  Tx_65To127Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC1_Tx_65To127Octets_Packets_Good_Bad_TX65_127OCTGB_Pos        (0UL)          /*!< TX65_127OCTGB (Bit 0)                           */
+ #define R_GMAC1_Tx_65To127Octets_Packets_Good_Bad_TX65_127OCTGB_Msk        (0xffffffffUL) /*!< TX65_127OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_128To255Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC1_Tx_128To255Octets_Packets_Good_Bad_TX128_255OCTGB_Pos      (0UL)          /*!< TX128_255OCTGB (Bit 0)                        */
+ #define R_GMAC1_Tx_128To255Octets_Packets_Good_Bad_TX128_255OCTGB_Msk      (0xffffffffUL) /*!< TX128_255OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_256To511Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC1_Tx_256To511Octets_Packets_Good_Bad_TX256_511OCTGB_Pos      (0UL)          /*!< TX256_511OCTGB (Bit 0)                        */
+ #define R_GMAC1_Tx_256To511Octets_Packets_Good_Bad_TX256_511OCTGB_Msk      (0xffffffffUL) /*!< TX256_511OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_512To1023Octets_Packets_Good_Bad  ========================================== */
+ #define R_GMAC1_Tx_512To1023Octets_Packets_Good_Bad_TX512_1023OCTGB_Pos    (0UL)          /*!< TX512_1023OCTGB (Bit 0)                     */
+ #define R_GMAC1_Tx_512To1023Octets_Packets_Good_Bad_TX512_1023OCTGB_Msk    (0xffffffffUL) /*!< TX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Tx_1024ToMaxOctets_Packets_Good_Bad  ========================================== */
+ #define R_GMAC1_Tx_1024ToMaxOctets_Packets_Good_Bad_TX1024_MAXOCTGB_Pos    (0UL)          /*!< TX1024_MAXOCTGB (Bit 0)                     */
+ #define R_GMAC1_Tx_1024ToMaxOctets_Packets_Good_Bad_TX1024_MAXOCTGB_Msk    (0xffffffffUL) /*!< TX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==============================================  Tx_Unicast_Packets_Good_Bad  ============================================== */
+ #define R_GMAC1_Tx_Unicast_Packets_Good_Bad_TXUCASTGB_Pos                  (0UL)          /*!< TXUCASTGB (Bit 0)                                     */
+ #define R_GMAC1_Tx_Unicast_Packets_Good_Bad_TXUCASTGB_Msk                  (0xffffffffUL) /*!< TXUCASTGB (Bitfield-Mask: 0xffffffff)            */
+/* =============================================  Tx_Multicast_Packets_Good_Bad  ============================================= */
+ #define R_GMAC1_Tx_Multicast_Packets_Good_Bad_TXMCASTGB_Pos                (0UL)          /*!< TXMCASTGB (Bit 0)                                     */
+ #define R_GMAC1_Tx_Multicast_Packets_Good_Bad_TXMCASTGB_Msk                (0xffffffffUL) /*!< TXMCASTGB (Bitfield-Mask: 0xffffffff)          */
+/* =============================================  Tx_Broadcast_Packets_Good_Bad  ============================================= */
+ #define R_GMAC1_Tx_Broadcast_Packets_Good_Bad_TXBCASTGB_Pos                (0UL)          /*!< TXBCASTGB (Bit 0)                                     */
+ #define R_GMAC1_Tx_Broadcast_Packets_Good_Bad_TXBCASTGB_Msk                (0xffffffffUL) /*!< TXBCASTGB (Bitfield-Mask: 0xffffffff)          */
+/* ==============================================  Tx_Underflow_Error_Packets  =============================================== */
+ #define R_GMAC1_Tx_Underflow_Error_Packets_TXUNDRFLW_Pos                   (0UL)          /*!< TXUNDRFLW (Bit 0)                                     */
+ #define R_GMAC1_Tx_Underflow_Error_Packets_TXUNDRFLW_Msk                   (0xffffffffUL) /*!< TXUNDRFLW (Bitfield-Mask: 0xffffffff)             */
+/* ===========================================  Tx_Single_Collision_Good_Packets  ============================================ */
+ #define R_GMAC1_Tx_Single_Collision_Good_Packets_TXSNGLCOLG_Pos            (0UL)          /*!< TXSNGLCOLG (Bit 0)                                  */
+ #define R_GMAC1_Tx_Single_Collision_Good_Packets_TXSNGLCOLG_Msk            (0xffffffffUL) /*!< TXSNGLCOLG (Bitfield-Mask: 0xffffffff)     */
+/* ==========================================  Tx_Multiple_Collision_Good_Packets  =========================================== */
+ #define R_GMAC1_Tx_Multiple_Collision_Good_Packets_TXMULTCOLG_Pos          (0UL)          /*!< TXMULTCOLG (Bit 0)                                */
+ #define R_GMAC1_Tx_Multiple_Collision_Good_Packets_TXMULTCOLG_Msk          (0xffffffffUL) /*!< TXMULTCOLG (Bitfield-Mask: 0xffffffff)   */
+/* ==================================================  Tx_Deferred_Packets  ================================================== */
+ #define R_GMAC1_Tx_Deferred_Packets_TXDEFRD_Pos                            (0UL)          /*!< TXDEFRD (Bit 0)                                       */
+ #define R_GMAC1_Tx_Deferred_Packets_TXDEFRD_Msk                            (0xffffffffUL) /*!< TXDEFRD (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Tx_Late_Collision_Packets  =============================================== */
+ #define R_GMAC1_Tx_Late_Collision_Packets_TXLATECOL_Pos                    (0UL)          /*!< TXLATECOL (Bit 0)                                     */
+ #define R_GMAC1_Tx_Late_Collision_Packets_TXLATECOL_Msk                    (0xffffffffUL) /*!< TXLATECOL (Bitfield-Mask: 0xffffffff)              */
+/* ============================================  Tx_Excessive_Collision_Packets  ============================================= */
+ #define R_GMAC1_Tx_Excessive_Collision_Packets_TXEXSCOL_Pos                (0UL)          /*!< TXEXSCOL (Bit 0)                                      */
+ #define R_GMAC1_Tx_Excessive_Collision_Packets_TXEXSCOL_Msk                (0xffffffffUL) /*!< TXEXSCOL (Bitfield-Mask: 0xffffffff)           */
+/* ===============================================  Tx_Carrier_Error_Packets  ================================================ */
+ #define R_GMAC1_Tx_Carrier_Error_Packets_TXCARR_Pos                        (0UL)          /*!< TXCARR (Bit 0)                                        */
+ #define R_GMAC1_Tx_Carrier_Error_Packets_TXCARR_Msk                        (0xffffffffUL) /*!< TXCARR (Bitfield-Mask: 0xffffffff)                    */
+/* ==================================================  Tx_Octet_Count_Good  ================================================== */
+ #define R_GMAC1_Tx_Octet_Count_Good_TXOCTG_Pos                             (0UL)          /*!< TXOCTG (Bit 0)                                        */
+ #define R_GMAC1_Tx_Octet_Count_Good_TXOCTG_Msk                             (0xffffffffUL) /*!< TXOCTG (Bitfield-Mask: 0xffffffff)                    */
+/* =================================================  Tx_Packet_Count_Good  ================================================== */
+ #define R_GMAC1_Tx_Packet_Count_Good_TXPKTG_Pos                            (0UL)          /*!< TXPKTG (Bit 0)                                        */
+ #define R_GMAC1_Tx_Packet_Count_Good_TXPKTG_Msk                            (0xffffffffUL) /*!< TXPKTG (Bitfield-Mask: 0xffffffff)                    */
+/* ==============================================  Tx_Excessive_Deferral_Error  ============================================== */
+ #define R_GMAC1_Tx_Excessive_Deferral_Error_TXEXSDEF_Pos                   (0UL)          /*!< TXEXSDEF (Bit 0)                                      */
+ #define R_GMAC1_Tx_Excessive_Deferral_Error_TXEXSDEF_Msk                   (0xffffffffUL) /*!< TXEXSDEF (Bitfield-Mask: 0xffffffff)              */
+/* ===================================================  Tx_Pause_Packets  ==================================================== */
+ #define R_GMAC1_Tx_Pause_Packets_TXPAUSE_Pos                               (0UL)          /*!< TXPAUSE (Bit 0)                                       */
+ #define R_GMAC1_Tx_Pause_Packets_TXPAUSE_Msk                               (0xffffffffUL) /*!< TXPAUSE (Bitfield-Mask: 0xffffffff)                   */
+/* =================================================  Tx_VLAN_Packets_Good  ================================================== */
+ #define R_GMAC1_Tx_VLAN_Packets_Good_TXVLANG_Pos                           (0UL)          /*!< TXVLANG (Bit 0)                                       */
+ #define R_GMAC1_Tx_VLAN_Packets_Good_TXVLANG_Msk                           (0xffffffffUL) /*!< TXVLANG (Bitfield-Mask: 0xffffffff)                   */
+/* =================================================  Tx_OSize_Packets_Good  ================================================= */
+ #define R_GMAC1_Tx_OSize_Packets_Good_TXOSIZG_Pos                          (0UL)          /*!< TXOSIZG (Bit 0)                                       */
+ #define R_GMAC1_Tx_OSize_Packets_Good_TXOSIZG_Msk                          (0xffffffffUL) /*!< TXOSIZG (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  Rx_Packets_Count_Good_Bad  =============================================== */
+ #define R_GMAC1_Rx_Packets_Count_Good_Bad_RXPKTGB_Pos                      (0UL)          /*!< RXPKTGB (Bit 0)                                       */
+ #define R_GMAC1_Rx_Packets_Count_Good_Bad_RXPKTGB_Msk                      (0xffffffffUL) /*!< RXPKTGB (Bitfield-Mask: 0xffffffff)                  */
+/* ================================================  Rx_Octet_Count_Good_Bad  ================================================ */
+ #define R_GMAC1_Rx_Octet_Count_Good_Bad_RXOCTGB_Pos                        (0UL)          /*!< RXOCTGB (Bit 0)                                       */
+ #define R_GMAC1_Rx_Octet_Count_Good_Bad_RXOCTGB_Msk                        (0xffffffffUL) /*!< RXOCTGB (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  Rx_Octet_Count_Good  ================================================== */
+ #define R_GMAC1_Rx_Octet_Count_Good_RXOCTG_Pos                             (0UL)          /*!< RXOCTG (Bit 0)                                        */
+ #define R_GMAC1_Rx_Octet_Count_Good_RXOCTG_Msk                             (0xffffffffUL) /*!< RXOCTG (Bitfield-Mask: 0xffffffff)                    */
+/* ===============================================  Rx_Broadcast_Packets_Good  =============================================== */
+ #define R_GMAC1_Rx_Broadcast_Packets_Good_RXBCASTG_Pos                     (0UL)          /*!< RXBCASTG (Bit 0)                                      */
+ #define R_GMAC1_Rx_Broadcast_Packets_Good_RXBCASTG_Msk                     (0xffffffffUL) /*!< RXBCASTG (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  Rx_Multicast_Packets_Good  =============================================== */
+ #define R_GMAC1_Rx_Multicast_Packets_Good_RXMCASTG_Pos                     (0UL)          /*!< RXMCASTG (Bit 0)                                      */
+ #define R_GMAC1_Rx_Multicast_Packets_Good_RXMCASTG_Msk                     (0xffffffffUL) /*!< RXMCASTG (Bitfield-Mask: 0xffffffff)                */
+/* =================================================  Rx_CRC_Error_Packets  ================================================== */
+ #define R_GMAC1_Rx_CRC_Error_Packets_RXCRCERR_Pos                          (0UL)          /*!< RXCRCERR (Bit 0)                                      */
+ #define R_GMAC1_Rx_CRC_Error_Packets_RXCRCERR_Msk                          (0xffffffffUL) /*!< RXCRCERR (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  Rx_Alignment_Error_Packets  =============================================== */
+ #define R_GMAC1_Rx_Alignment_Error_Packets_RXALGNERR_Pos                   (0UL)          /*!< RXALGNERR (Bit 0)                                     */
+ #define R_GMAC1_Rx_Alignment_Error_Packets_RXALGNERR_Msk                   (0xffffffffUL) /*!< RXALGNERR (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  Rx_Runt_Error_Packets  ================================================= */
+ #define R_GMAC1_Rx_Runt_Error_Packets_RXRUNTERR_Pos                        (0UL)          /*!< RXRUNTERR (Bit 0)                                     */
+ #define R_GMAC1_Rx_Runt_Error_Packets_RXRUNTERR_Msk                        (0xffffffffUL) /*!< RXRUNTERR (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  Rx_Jabber_Error_Packets  ================================================ */
+ #define R_GMAC1_Rx_Jabber_Error_Packets_RXJABERR_Pos                       (0UL)          /*!< RXJABERR (Bit 0)                                      */
+ #define R_GMAC1_Rx_Jabber_Error_Packets_RXJABERR_Msk                       (0xffffffffUL) /*!< RXJABERR (Bitfield-Mask: 0xffffffff)                  */
+/* ===============================================  Rx_Undersize_Packets_Good  =============================================== */
+ #define R_GMAC1_Rx_Undersize_Packets_Good_RXUNDERSZG_Pos                   (0UL)          /*!< RXUNDERSZG (Bit 0)                                    */
+ #define R_GMAC1_Rx_Undersize_Packets_Good_RXUNDERSZG_Msk                   (0xffffffffUL) /*!< RXUNDERSZG (Bitfield-Mask: 0xffffffff)            */
+/* ===============================================  Rx_Oversize_Packets_Good  ================================================ */
+ #define R_GMAC1_Rx_Oversize_Packets_Good_RXOVERSZG_Pos                     (0UL)          /*!< RXOVERSZG (Bit 0)                                     */
+ #define R_GMAC1_Rx_Oversize_Packets_Good_RXOVERSZG_Msk                     (0xffffffffUL) /*!< RXOVERSZG (Bitfield-Mask: 0xffffffff)               */
+/* =============================================  Rx_64Octets_Packets_Good_Bad  ============================================== */
+ #define R_GMAC1_Rx_64Octets_Packets_Good_Bad_RX64OCTGB_Pos                 (0UL)          /*!< RX64OCTGB (Bit 0)                                     */
+ #define R_GMAC1_Rx_64Octets_Packets_Good_Bad_RX64OCTGB_Msk                 (0xffffffffUL) /*!< RX64OCTGB (Bitfield-Mask: 0xffffffff)           */
+/* ===========================================  Rx_65To127Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC1_Rx_65To127Octets_Packets_Good_Bad_RX65_127OCTGB_Pos        (0UL)          /*!< RX65_127OCTGB (Bit 0)                           */
+ #define R_GMAC1_Rx_65To127Octets_Packets_Good_Bad_RX65_127OCTGB_Msk        (0xffffffffUL) /*!< RX65_127OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_128To255Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC1_Rx_128To255Octets_Packets_Good_Bad_RX128_255OCTGB_Pos      (0UL)          /*!< RX128_255OCTGB (Bit 0)                        */
+ #define R_GMAC1_Rx_128To255Octets_Packets_Good_Bad_RX128_255OCTGB_Msk      (0xffffffffUL) /*!< RX128_255OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_256To511Octets_Packets_Good_Bad  =========================================== */
+ #define R_GMAC1_Rx_256To511Octets_Packets_Good_Bad_RX256_511OCTGB_Pos      (0UL)          /*!< RX256_511OCTGB (Bit 0)                        */
+ #define R_GMAC1_Rx_256To511Octets_Packets_Good_Bad_RX256_511OCTGB_Msk      (0xffffffffUL) /*!< RX256_511OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_512To1023Octets_Packets_Good_Bad  ========================================== */
+ #define R_GMAC1_Rx_512To1023Octets_Packets_Good_Bad_RX512_1023OCTGB_Pos    (0UL)          /*!< RX512_1023OCTGB (Bit 0)                     */
+ #define R_GMAC1_Rx_512To1023Octets_Packets_Good_Bad_RX512_1023OCTGB_Msk    (0xffffffffUL) /*!< RX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */
+/* ==========================================  Rx_1024ToMaxOctets_Packets_Good_Bad  ========================================== */
+ #define R_GMAC1_Rx_1024ToMaxOctets_Packets_Good_Bad_RX1024_MAXOCTGB_Pos    (0UL)          /*!< RX1024_MAXOCTGB (Bit 0)                     */
+ #define R_GMAC1_Rx_1024ToMaxOctets_Packets_Good_Bad_RX1024_MAXOCTGB_Msk    (0xffffffffUL) /*!< RX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */
+/* ================================================  Rx_Unicast_Packets_Good  ================================================ */
+ #define R_GMAC1_Rx_Unicast_Packets_Good_RXUCASTG_Pos                       (0UL)          /*!< RXUCASTG (Bit 0)                                      */
+ #define R_GMAC1_Rx_Unicast_Packets_Good_RXUCASTG_Msk                       (0xffffffffUL) /*!< RXUCASTG (Bitfield-Mask: 0xffffffff)                  */
+/* ================================================  Rx_Length_Error_Packets  ================================================ */
+ #define R_GMAC1_Rx_Length_Error_Packets_RXLENERR_Pos                       (0UL)          /*!< RXLENERR (Bit 0)                                      */
+ #define R_GMAC1_Rx_Length_Error_Packets_RXLENERR_Msk                       (0xffffffffUL) /*!< RXLENERR (Bitfield-Mask: 0xffffffff)                  */
+/* =============================================  Rx_Out_Of_Range_Type_Packets  ============================================== */
+ #define R_GMAC1_Rx_Out_Of_Range_Type_Packets_RXOUTOFRNG_Pos                (0UL)          /*!< RXOUTOFRNG (Bit 0)                                    */
+ #define R_GMAC1_Rx_Out_Of_Range_Type_Packets_RXOUTOFRNG_Msk                (0xffffffffUL) /*!< RXOUTOFRNG (Bitfield-Mask: 0xffffffff)         */
+/* ===================================================  Rx_Pause_Packets  ==================================================== */
+ #define R_GMAC1_Rx_Pause_Packets_RXPAUSEPKT_Pos                            (0UL)          /*!< RXPAUSEPKT (Bit 0)                                    */
+ #define R_GMAC1_Rx_Pause_Packets_RXPAUSEPKT_Msk                            (0xffffffffUL) /*!< RXPAUSEPKT (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  Rx_FIFO_Overflow_Packets  ================================================ */
+ #define R_GMAC1_Rx_FIFO_Overflow_Packets_RXFIFOOVFL_Pos                    (0UL)          /*!< RXFIFOOVFL (Bit 0)                                    */
+ #define R_GMAC1_Rx_FIFO_Overflow_Packets_RXFIFOOVFL_Msk                    (0xffffffffUL) /*!< RXFIFOOVFL (Bitfield-Mask: 0xffffffff)             */
+/* ===============================================  Rx_VLAN_Packets_Good_Bad  ================================================ */
+ #define R_GMAC1_Rx_VLAN_Packets_Good_Bad_RXVLANPKTGB_Pos                   (0UL)          /*!< RXVLANPKTGB (Bit 0)                                   */
+ #define R_GMAC1_Rx_VLAN_Packets_Good_Bad_RXVLANPKTGB_Msk                   (0xffffffffUL) /*!< RXVLANPKTGB (Bitfield-Mask: 0xffffffff)           */
+/* ===============================================  Rx_Watchdog_Error_Packets  =============================================== */
+ #define R_GMAC1_Rx_Watchdog_Error_Packets_RXWDGERR_Pos                     (0UL)          /*!< RXWDGERR (Bit 0)                                      */
+ #define R_GMAC1_Rx_Watchdog_Error_Packets_RXWDGERR_Msk                     (0xffffffffUL) /*!< RXWDGERR (Bitfield-Mask: 0xffffffff)                */
+/* ===============================================  Rx_Receive_Error_Packets  ================================================ */
+ #define R_GMAC1_Rx_Receive_Error_Packets_RXRCVERR_Pos                      (0UL)          /*!< RXRCVERR (Bit 0)                                      */
+ #define R_GMAC1_Rx_Receive_Error_Packets_RXRCVERR_Msk                      (0xffffffffUL) /*!< RXRCVERR (Bitfield-Mask: 0xffffffff)                 */
+/* ================================================  Rx_Control_Packets_Good  ================================================ */
+ #define R_GMAC1_Rx_Control_Packets_Good_RXCTRLG_Pos                        (0UL)          /*!< RXCTRLG (Bit 0)                                       */
+ #define R_GMAC1_Rx_Control_Packets_Good_RXCTRLG_Msk                        (0xffffffffUL) /*!< RXCTRLG (Bitfield-Mask: 0xffffffff)                   */
+/* ===================================================  Tx_LPI_USEC_Cntr  ==================================================== */
+ #define R_GMAC1_Tx_LPI_USEC_Cntr_TXLPIUSC_Pos                              (0UL)          /*!< TXLPIUSC (Bit 0)                                      */
+ #define R_GMAC1_Tx_LPI_USEC_Cntr_TXLPIUSC_Msk                              (0xffffffffUL) /*!< TXLPIUSC (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  Tx_LPI_Tran_Cntr  ==================================================== */
+ #define R_GMAC1_Tx_LPI_Tran_Cntr_TXLPITRC_Pos                              (0UL)          /*!< TXLPITRC (Bit 0)                                      */
+ #define R_GMAC1_Tx_LPI_Tran_Cntr_TXLPITRC_Msk                              (0xffffffffUL) /*!< TXLPITRC (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  Rx_LPI_USEC_Cntr  ==================================================== */
+ #define R_GMAC1_Rx_LPI_USEC_Cntr_RXLPIUSC_Pos                              (0UL)          /*!< RXLPIUSC (Bit 0)                                      */
+ #define R_GMAC1_Rx_LPI_USEC_Cntr_RXLPIUSC_Msk                              (0xffffffffUL) /*!< RXLPIUSC (Bitfield-Mask: 0xffffffff)                  */
+/* ===================================================  Rx_LPI_Tran_Cntr  ==================================================== */
+ #define R_GMAC1_Rx_LPI_Tran_Cntr_RXLPITRC_Pos                              (0UL)          /*!< RXLPITRC (Bit 0)                                      */
+ #define R_GMAC1_Rx_LPI_Tran_Cntr_RXLPITRC_Msk                              (0xffffffffUL) /*!< RXLPITRC (Bitfield-Mask: 0xffffffff)                  */
+/* ===============================================  MMC_IPC_Rx_Interrupt_Mask  =============================================== */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4GPIM_Pos                   (0UL)          /*!< RXIPV4GPIM (Bit 0)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4GPIM_Msk                   (0x1UL)        /*!< RXIPV4GPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4HERPIM_Pos                 (1UL)          /*!< RXIPV4HERPIM (Bit 1)                                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4HERPIM_Msk                 (0x2UL)        /*!< RXIPV4HERPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4NOPAYPIM_Pos               (2UL)          /*!< RXIPV4NOPAYPIM (Bit 2)                                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4NOPAYPIM_Msk               (0x4UL)        /*!< RXIPV4NOPAYPIM (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4FRAGPIM_Pos                (3UL)          /*!< RXIPV4FRAGPIM (Bit 3)                                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4FRAGPIM_Msk                (0x8UL)        /*!< RXIPV4FRAGPIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4UDSBLPIM_Pos               (4UL)          /*!< RXIPV4UDSBLPIM (Bit 4)                                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4UDSBLPIM_Msk               (0x10UL)       /*!< RXIPV4UDSBLPIM (Bitfield-Mask: 0x01)                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6GPIM_Pos                   (5UL)          /*!< RXIPV6GPIM (Bit 5)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6GPIM_Msk                   (0x20UL)       /*!< RXIPV6GPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6HERPIM_Pos                 (6UL)          /*!< RXIPV6HERPIM (Bit 6)                                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6HERPIM_Msk                 (0x40UL)       /*!< RXIPV6HERPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6NOPAYPIM_Pos               (7UL)          /*!< RXIPV6NOPAYPIM (Bit 7)                                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6NOPAYPIM_Msk               (0x80UL)       /*!< RXIPV6NOPAYPIM (Bitfield-Mask: 0x01)                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXUDPGPIM_Pos                    (8UL)          /*!< RXUDPGPIM (Bit 8)                                     */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXUDPGPIM_Msk                    (0x100UL)      /*!< RXUDPGPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXUDPERPIM_Pos                   (9UL)          /*!< RXUDPERPIM (Bit 9)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXUDPERPIM_Msk                   (0x200UL)      /*!< RXUDPERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXTCPGPIM_Pos                    (10UL)         /*!< RXTCPGPIM (Bit 10)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXTCPGPIM_Msk                    (0x400UL)      /*!< RXTCPGPIM (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXTCPERPIM_Pos                   (11UL)         /*!< RXTCPERPIM (Bit 11)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXTCPERPIM_Msk                   (0x800UL)      /*!< RXTCPERPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXICMPGPIM_Pos                   (12UL)         /*!< RXICMPGPIM (Bit 12)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXICMPGPIM_Msk                   (0x1000UL)     /*!< RXICMPGPIM (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXICMPERPIM_Pos                  (13UL)         /*!< RXICMPERPIM (Bit 13)                                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXICMPERPIM_Msk                  (0x2000UL)     /*!< RXICMPERPIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4GOIM_Pos                   (16UL)         /*!< RXIPV4GOIM (Bit 16)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4GOIM_Msk                   (0x10000UL)    /*!< RXIPV4GOIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4HEROIM_Pos                 (17UL)         /*!< RXIPV4HEROIM (Bit 17)                                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4HEROIM_Msk                 (0x20000UL)    /*!< RXIPV4HEROIM (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4NOPAYOIM_Pos               (18UL)         /*!< RXIPV4NOPAYOIM (Bit 18)                               */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4NOPAYOIM_Msk               (0x40000UL)    /*!< RXIPV4NOPAYOIM (Bitfield-Mask: 0x01)             */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4FRAGOIM_Pos                (19UL)         /*!< RXIPV4FRAGOIM (Bit 19)                                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4FRAGOIM_Msk                (0x80000UL)    /*!< RXIPV4FRAGOIM (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4UDSBLOIM_Pos               (20UL)         /*!< RXIPV4UDSBLOIM (Bit 20)                               */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV4UDSBLOIM_Msk               (0x100000UL)   /*!< RXIPV4UDSBLOIM (Bitfield-Mask: 0x01)            */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6GOIM_Pos                   (21UL)         /*!< RXIPV6GOIM (Bit 21)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6GOIM_Msk                   (0x200000UL)   /*!< RXIPV6GOIM (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6HEROIM_Pos                 (22UL)         /*!< RXIPV6HEROIM (Bit 22)                                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6HEROIM_Msk                 (0x400000UL)   /*!< RXIPV6HEROIM (Bitfield-Mask: 0x01)                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6NOPAYOIM_Pos               (23UL)         /*!< RXIPV6NOPAYOIM (Bit 23)                               */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXIPV6NOPAYOIM_Msk               (0x800000UL)   /*!< RXIPV6NOPAYOIM (Bitfield-Mask: 0x01)            */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXUDPGOIM_Pos                    (24UL)         /*!< RXUDPGOIM (Bit 24)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXUDPGOIM_Msk                    (0x1000000UL)  /*!< RXUDPGOIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXUDPEROIM_Pos                   (25UL)         /*!< RXUDPEROIM (Bit 25)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXUDPEROIM_Msk                   (0x2000000UL)  /*!< RXUDPEROIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXTCPGOIM_Pos                    (26UL)         /*!< RXTCPGOIM (Bit 26)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXTCPGOIM_Msk                    (0x4000000UL)  /*!< RXTCPGOIM (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXTCPEROIM_Pos                   (27UL)         /*!< RXTCPEROIM (Bit 27)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXTCPEROIM_Msk                   (0x8000000UL)  /*!< RXTCPEROIM (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXICMPGOIM_Pos                   (28UL)         /*!< RXICMPGOIM (Bit 28)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXICMPGOIM_Msk                   (0x10000000UL) /*!< RXICMPGOIM (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXICMPEROIM_Pos                  (29UL)         /*!< RXICMPEROIM (Bit 29)                                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_Mask_RXICMPEROIM_Msk                  (0x20000000UL) /*!< RXICMPEROIM (Bitfield-Mask: 0x01)                */
+/* =================================================  MMC_IPC_Rx_Interrupt  ================================================== */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4GPIS_Pos                        (0UL)          /*!< RXIPV4GPIS (Bit 0)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4GPIS_Msk                        (0x1UL)        /*!< RXIPV4GPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4HERPIS_Pos                      (1UL)          /*!< RXIPV4HERPIS (Bit 1)                                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4HERPIS_Msk                      (0x2UL)        /*!< RXIPV4HERPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4NOPAYPIS_Pos                    (2UL)          /*!< RXIPV4NOPAYPIS (Bit 2)                                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4NOPAYPIS_Msk                    (0x4UL)        /*!< RXIPV4NOPAYPIS (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4FRAGPIS_Pos                     (3UL)          /*!< RXIPV4FRAGPIS (Bit 3)                                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4FRAGPIS_Msk                     (0x8UL)        /*!< RXIPV4FRAGPIS (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4UDSBLPIS_Pos                    (4UL)          /*!< RXIPV4UDSBLPIS (Bit 4)                                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4UDSBLPIS_Msk                    (0x10UL)       /*!< RXIPV4UDSBLPIS (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6GPIS_Pos                        (5UL)          /*!< RXIPV6GPIS (Bit 5)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6GPIS_Msk                        (0x20UL)       /*!< RXIPV6GPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6HERPIS_Pos                      (6UL)          /*!< RXIPV6HERPIS (Bit 6)                                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6HERPIS_Msk                      (0x40UL)       /*!< RXIPV6HERPIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6NOPAYPIS_Pos                    (7UL)          /*!< RXIPV6NOPAYPIS (Bit 7)                                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6NOPAYPIS_Msk                    (0x80UL)       /*!< RXIPV6NOPAYPIS (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXUDPGPIS_Pos                         (8UL)          /*!< RXUDPGPIS (Bit 8)                                     */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXUDPGPIS_Msk                         (0x100UL)      /*!< RXUDPGPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXUDPERPIS_Pos                        (9UL)          /*!< RXUDPERPIS (Bit 9)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXUDPERPIS_Msk                        (0x200UL)      /*!< RXUDPERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXTCPGPIS_Pos                         (10UL)         /*!< RXTCPGPIS (Bit 10)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXTCPGPIS_Msk                         (0x400UL)      /*!< RXTCPGPIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXTCPERPIS_Pos                        (11UL)         /*!< RXTCPERPIS (Bit 11)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXTCPERPIS_Msk                        (0x800UL)      /*!< RXTCPERPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXICMPGPIS_Pos                        (12UL)         /*!< RXICMPGPIS (Bit 12)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXICMPGPIS_Msk                        (0x1000UL)     /*!< RXICMPGPIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXICMPERPIS_Pos                       (13UL)         /*!< RXICMPERPIS (Bit 13)                                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXICMPERPIS_Msk                       (0x2000UL)     /*!< RXICMPERPIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4GOIS_Pos                        (16UL)         /*!< RXIPV4GOIS (Bit 16)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4GOIS_Msk                        (0x10000UL)    /*!< RXIPV4GOIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4HEROIS_Pos                      (17UL)         /*!< RXIPV4HEROIS (Bit 17)                                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4HEROIS_Msk                      (0x20000UL)    /*!< RXIPV4HEROIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4NOPAYOIS_Pos                    (18UL)         /*!< RXIPV4NOPAYOIS (Bit 18)                               */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4NOPAYOIS_Msk                    (0x40000UL)    /*!< RXIPV4NOPAYOIS (Bitfield-Mask: 0x01)                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4FRAGOIS_Pos                     (19UL)         /*!< RXIPV4FRAGOIS (Bit 19)                                */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4FRAGOIS_Msk                     (0x80000UL)    /*!< RXIPV4FRAGOIS (Bitfield-Mask: 0x01)                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4UDSBLOIS_Pos                    (20UL)         /*!< RXIPV4UDSBLOIS (Bit 20)                               */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV4UDSBLOIS_Msk                    (0x100000UL)   /*!< RXIPV4UDSBLOIS (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6GOIS_Pos                        (21UL)         /*!< RXIPV6GOIS (Bit 21)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6GOIS_Msk                        (0x200000UL)   /*!< RXIPV6GOIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6HEROIS_Pos                      (22UL)         /*!< RXIPV6HEROIS (Bit 22)                                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6HEROIS_Msk                      (0x400000UL)   /*!< RXIPV6HEROIS (Bitfield-Mask: 0x01)                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6NOPAYOIS_Pos                    (23UL)         /*!< RXIPV6NOPAYOIS (Bit 23)                               */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXIPV6NOPAYOIS_Msk                    (0x800000UL)   /*!< RXIPV6NOPAYOIS (Bitfield-Mask: 0x01)                 */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXUDPGOIS_Pos                         (24UL)         /*!< RXUDPGOIS (Bit 24)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXUDPGOIS_Msk                         (0x1000000UL)  /*!< RXUDPGOIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXUDPEROIS_Pos                        (25UL)         /*!< RXUDPEROIS (Bit 25)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXUDPEROIS_Msk                        (0x2000000UL)  /*!< RXUDPEROIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXTCPGOIS_Pos                         (26UL)         /*!< RXTCPGOIS (Bit 26)                                    */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXTCPGOIS_Msk                         (0x4000000UL)  /*!< RXTCPGOIS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXTCPEROIS_Pos                        (27UL)         /*!< RXTCPEROIS (Bit 27)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXTCPEROIS_Msk                        (0x8000000UL)  /*!< RXTCPEROIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXICMPGOIS_Pos                        (28UL)         /*!< RXICMPGOIS (Bit 28)                                   */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXICMPGOIS_Msk                        (0x10000000UL) /*!< RXICMPGOIS (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXICMPEROIS_Pos                       (29UL)         /*!< RXICMPEROIS (Bit 29)                                  */
+ #define R_GMAC1_MMC_IPC_Rx_Interrupt_RXICMPEROIS_Msk                       (0x20000000UL) /*!< RXICMPEROIS (Bitfield-Mask: 0x01)                     */
+/* ==================================================  RxIPv4_Good_Packets  ================================================== */
+ #define R_GMAC1_RxIPv4_Good_Packets_RXIPV4GDPKT_Pos                        (0UL)          /*!< RXIPV4GDPKT (Bit 0)                                   */
+ #define R_GMAC1_RxIPv4_Good_Packets_RXIPV4GDPKT_Msk                        (0xffffffffUL) /*!< RXIPV4GDPKT (Bitfield-Mask: 0xffffffff)               */
+/* ==============================================  RxIPv4_Header_Error_Packets  ============================================== */
+ #define R_GMAC1_RxIPv4_Header_Error_Packets_RXIPV4HDRERRPKT_Pos            (0UL)          /*!< RXIPV4HDRERRPKT (Bit 0)                             */
+ #define R_GMAC1_RxIPv4_Header_Error_Packets_RXIPV4HDRERRPKT_Msk            (0xffffffffUL) /*!< RXIPV4HDRERRPKT (Bitfield-Mask: 0xffffffff) */
+/* ===============================================  RxIPv4_No_Payload_Packets  =============================================== */
+ #define R_GMAC1_RxIPv4_No_Payload_Packets_RXIPV4NOPAYPKT_Pos               (0UL)          /*!< RXIPV4NOPAYPKT (Bit 0)                                */
+ #define R_GMAC1_RxIPv4_No_Payload_Packets_RXIPV4NOPAYPKT_Msk               (0xffffffffUL) /*!< RXIPV4NOPAYPKT (Bitfield-Mask: 0xffffffff)    */
+/* ===============================================  RxIPv4_Fragmented_Packets  =============================================== */
+ #define R_GMAC1_RxIPv4_Fragmented_Packets_RXIPV4FRAGPKT_Pos                (0UL)          /*!< RXIPV4FRAGPKT (Bit 0)                                 */
+ #define R_GMAC1_RxIPv4_Fragmented_Packets_RXIPV4FRAGPKT_Msk                (0xffffffffUL) /*!< RXIPV4FRAGPKT (Bitfield-Mask: 0xffffffff)      */
+/* =========================================  RxIPv4_UDP_Checksum_Disabled_Packets  ========================================== */
+ #define R_GMAC1_RxIPv4_UDP_Checksum_Disabled_Packets_RXIPV4UDSBLPKT_Pos    (0UL)          /*!< RXIPV4UDSBLPKT (Bit 0)                      */
+ #define R_GMAC1_RxIPv4_UDP_Checksum_Disabled_Packets_RXIPV4UDSBLPKT_Msk    (0xffffffffUL) /*!< RXIPV4UDSBLPKT (Bitfield-Mask: 0xffffffff) */
+/* ==================================================  RxIPv6_Good_Packets  ================================================== */
+ #define R_GMAC1_RxIPv6_Good_Packets_RXIPV6GDPKT_Pos                        (0UL)          /*!< RXIPV6GDPKT (Bit 0)                                   */
+ #define R_GMAC1_RxIPv6_Good_Packets_RXIPV6GDPKT_Msk                        (0xffffffffUL) /*!< RXIPV6GDPKT (Bitfield-Mask: 0xffffffff)               */
+/* ==============================================  RxIPv6_Header_Error_Packets  ============================================== */
+ #define R_GMAC1_RxIPv6_Header_Error_Packets_RXIPV6HDRERRPKT_Pos            (0UL)          /*!< RXIPV6HDRERRPKT (Bit 0)                             */
+ #define R_GMAC1_RxIPv6_Header_Error_Packets_RXIPV6HDRERRPKT_Msk            (0xffffffffUL) /*!< RXIPV6HDRERRPKT (Bitfield-Mask: 0xffffffff) */
+/* ===============================================  RxIPv6_No_Payload_Packets  =============================================== */
+ #define R_GMAC1_RxIPv6_No_Payload_Packets_RXIPV6NOPAYPKT_Pos               (0UL)          /*!< RXIPV6NOPAYPKT (Bit 0)                                */
+ #define R_GMAC1_RxIPv6_No_Payload_Packets_RXIPV6NOPAYPKT_Msk               (0xffffffffUL) /*!< RXIPV6NOPAYPKT (Bitfield-Mask: 0xffffffff)    */
+/* ==================================================  RxUDP_Good_Packets  =================================================== */
+ #define R_GMAC1_RxUDP_Good_Packets_RXUDPGDPKT_Pos                          (0UL)          /*!< RXUDPGDPKT (Bit 0)                                    */
+ #define R_GMAC1_RxUDP_Good_Packets_RXUDPGDPKT_Msk                          (0xffffffffUL) /*!< RXUDPGDPKT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  RxUDP_Error_Packets  ================================================== */
+ #define R_GMAC1_RxUDP_Error_Packets_RXUDPERRPKT_Pos                        (0UL)          /*!< RXUDPERRPKT (Bit 0)                                   */
+ #define R_GMAC1_RxUDP_Error_Packets_RXUDPERRPKT_Msk                        (0xffffffffUL) /*!< RXUDPERRPKT (Bitfield-Mask: 0xffffffff)               */
+/* ==================================================  RxTCP_Good_Packets  =================================================== */
+ #define R_GMAC1_RxTCP_Good_Packets_RXTCPGDPKT_Pos                          (0UL)          /*!< RXTCPGDPKT (Bit 0)                                    */
+ #define R_GMAC1_RxTCP_Good_Packets_RXTCPGDPKT_Msk                          (0xffffffffUL) /*!< RXTCPGDPKT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  RxTCP_Error_Packets  ================================================== */
+ #define R_GMAC1_RxTCP_Error_Packets_RXTCPERRPKT_Pos                        (0UL)          /*!< RXTCPERRPKT (Bit 0)                                   */
+ #define R_GMAC1_RxTCP_Error_Packets_RXTCPERRPKT_Msk                        (0xffffffffUL) /*!< RXTCPERRPKT (Bitfield-Mask: 0xffffffff)               */
+/* ==================================================  RxICMP_Good_Packets  ================================================== */
+ #define R_GMAC1_RxICMP_Good_Packets_RXICMPGDPKT_Pos                        (0UL)          /*!< RXICMPGDPKT (Bit 0)                                   */
+ #define R_GMAC1_RxICMP_Good_Packets_RXICMPGDPKT_Msk                        (0xffffffffUL) /*!< RXICMPGDPKT (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  RxICMP_Error_Packets  ================================================== */
+ #define R_GMAC1_RxICMP_Error_Packets_RXICMPERRPKT_Pos                      (0UL)          /*!< RXICMPERRPKT (Bit 0)                                  */
+ #define R_GMAC1_RxICMP_Error_Packets_RXICMPERRPKT_Msk                      (0xffffffffUL) /*!< RXICMPERRPKT (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  RxIPv4_Good_Octets  =================================================== */
+ #define R_GMAC1_RxIPv4_Good_Octets_RXIPV4GDOCT_Pos                         (0UL)          /*!< RXIPV4GDOCT (Bit 0)                                   */
+ #define R_GMAC1_RxIPv4_Good_Octets_RXIPV4GDOCT_Msk                         (0xffffffffUL) /*!< RXIPV4GDOCT (Bitfield-Mask: 0xffffffff)               */
+/* ==============================================  RxIPv4_Header_Error_Octets  =============================================== */
+ #define R_GMAC1_RxIPv4_Header_Error_Octets_RXIPV4HDRERROCT_Pos             (0UL)          /*!< RXIPV4HDRERROCT (Bit 0)                              */
+ #define R_GMAC1_RxIPv4_Header_Error_Octets_RXIPV4HDRERROCT_Msk             (0xffffffffUL) /*!< RXIPV4HDRERROCT (Bitfield-Mask: 0xffffffff) */
+/* ===============================================  RxIPv4_No_Payload_Octets  ================================================ */
+ #define R_GMAC1_RxIPv4_No_Payload_Octets_RXIPV4NOPAYOCT_Pos                (0UL)          /*!< RXIPV4NOPAYOCT (Bit 0)                                */
+ #define R_GMAC1_RxIPv4_No_Payload_Octets_RXIPV4NOPAYOCT_Msk                (0xffffffffUL) /*!< RXIPV4NOPAYOCT (Bitfield-Mask: 0xffffffff)     */
+/* ===============================================  RxIPv4_Fragmented_Octets  ================================================ */
+ #define R_GMAC1_RxIPv4_Fragmented_Octets_RXIPV4FRAGOCT_Pos                 (0UL)          /*!< RXIPV4FRAGOCT (Bit 0)                                 */
+ #define R_GMAC1_RxIPv4_Fragmented_Octets_RXIPV4FRAGOCT_Msk                 (0xffffffffUL) /*!< RXIPV4FRAGOCT (Bitfield-Mask: 0xffffffff)       */
+/* ==========================================  RxIPv4_UDP_Checksum_Disable_Octets  =========================================== */
+ #define R_GMAC1_RxIPv4_UDP_Checksum_Disable_Octets_RXIPV4UDSBLOCT_Pos      (0UL)          /*!< RXIPV4UDSBLOCT (Bit 0)                        */
+ #define R_GMAC1_RxIPv4_UDP_Checksum_Disable_Octets_RXIPV4UDSBLOCT_Msk      (0xffffffffUL) /*!< RXIPV4UDSBLOCT (Bitfield-Mask: 0xffffffff) */
+/* ==================================================  RxIPv6_Good_Octets  =================================================== */
+ #define R_GMAC1_RxIPv6_Good_Octets_RXIPV6GDOCT_Pos                         (0UL)          /*!< RXIPV6GDOCT (Bit 0)                                   */
+ #define R_GMAC1_RxIPv6_Good_Octets_RXIPV6GDOCT_Msk                         (0xffffffffUL) /*!< RXIPV6GDOCT (Bitfield-Mask: 0xffffffff)               */
+/* ==============================================  RxIPv6_Header_Error_Octets  =============================================== */
+ #define R_GMAC1_RxIPv6_Header_Error_Octets_RXIPV6HDRERROCT_Pos             (0UL)          /*!< RXIPV6HDRERROCT (Bit 0)                              */
+ #define R_GMAC1_RxIPv6_Header_Error_Octets_RXIPV6HDRERROCT_Msk             (0xffffffffUL) /*!< RXIPV6HDRERROCT (Bitfield-Mask: 0xffffffff) */
+/* ===============================================  RxIPv6_No_Payload_Octets  ================================================ */
+ #define R_GMAC1_RxIPv6_No_Payload_Octets_RXIPV6NOPAYOCT_Pos                (0UL)          /*!< RXIPV6NOPAYOCT (Bit 0)                                */
+ #define R_GMAC1_RxIPv6_No_Payload_Octets_RXIPV6NOPAYOCT_Msk                (0xffffffffUL) /*!< RXIPV6NOPAYOCT (Bitfield-Mask: 0xffffffff)     */
+/* ===================================================  RxUDP_Good_Octets  =================================================== */
+ #define R_GMAC1_RxUDP_Good_Octets_RXUDPGDOCT_Pos                           (0UL)          /*!< RXUDPGDOCT (Bit 0)                                    */
+ #define R_GMAC1_RxUDP_Good_Octets_RXUDPGDOCT_Msk                           (0xffffffffUL) /*!< RXUDPGDOCT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  RxUDP_Error_Octets  =================================================== */
+ #define R_GMAC1_RxUDP_Error_Octets_RXUDPERROCT_Pos                         (0UL)          /*!< RXUDPERROCT (Bit 0)                                   */
+ #define R_GMAC1_RxUDP_Error_Octets_RXUDPERROCT_Msk                         (0xffffffffUL) /*!< RXUDPERROCT (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  RxTCP_Good_Octets  =================================================== */
+ #define R_GMAC1_RxTCP_Good_Octets_RXTCPGDOCT_Pos                           (0UL)          /*!< RXTCPGDOCT (Bit 0)                                    */
+ #define R_GMAC1_RxTCP_Good_Octets_RXTCPGDOCT_Msk                           (0xffffffffUL) /*!< RXTCPGDOCT (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  RxTCP_Error_Octets  =================================================== */
+ #define R_GMAC1_RxTCP_Error_Octets_RXTCPERROCT_Pos                         (0UL)          /*!< RXTCPERROCT (Bit 0)                                   */
+ #define R_GMAC1_RxTCP_Error_Octets_RXTCPERROCT_Msk                         (0xffffffffUL) /*!< RXTCPERROCT (Bitfield-Mask: 0xffffffff)               */
+/* ==================================================  RxICMP_Good_Octets  =================================================== */
+ #define R_GMAC1_RxICMP_Good_Octets_RXICMPGDOCT_Pos                         (0UL)          /*!< RXICMPGDOCT (Bit 0)                                   */
+ #define R_GMAC1_RxICMP_Good_Octets_RXICMPGDOCT_Msk                         (0xffffffffUL) /*!< RXICMPGDOCT (Bitfield-Mask: 0xffffffff)               */
+/* ==================================================  RxICMP_Error_Octets  ================================================== */
+ #define R_GMAC1_RxICMP_Error_Octets_RXICMPERROCT_Pos                       (0UL)          /*!< RXICMPERROCT (Bit 0)                                  */
+ #define R_GMAC1_RxICMP_Error_Octets_RXICMPERROCT_Msk                       (0xffffffffUL) /*!< RXICMPERROCT (Bitfield-Mask: 0xffffffff)              */
+/* =================================================  MMC_FPE_Tx_Interrupt  ================================================== */
+ #define R_GMAC1_MMC_FPE_Tx_Interrupt_FCIS_Pos                              (0UL)          /*!< FCIS (Bit 0)                                          */
+ #define R_GMAC1_MMC_FPE_Tx_Interrupt_FCIS_Msk                              (0x1UL)        /*!< FCIS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MMC_FPE_Tx_Interrupt_HRCIS_Pos                             (1UL)          /*!< HRCIS (Bit 1)                                         */
+ #define R_GMAC1_MMC_FPE_Tx_Interrupt_HRCIS_Msk                             (0x2UL)        /*!< HRCIS (Bitfield-Mask: 0x01)                           */
+/* ===============================================  MMC_FPE_Tx_Interrupt_Mask  =============================================== */
+ #define R_GMAC1_MMC_FPE_Tx_Interrupt_Mask_FCIM_Pos                         (0UL)          /*!< FCIM (Bit 0)                                          */
+ #define R_GMAC1_MMC_FPE_Tx_Interrupt_Mask_FCIM_Msk                         (0x1UL)        /*!< FCIM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MMC_FPE_Tx_Interrupt_Mask_HRCIM_Pos                        (1UL)          /*!< HRCIM (Bit 1)                                         */
+ #define R_GMAC1_MMC_FPE_Tx_Interrupt_Mask_HRCIM_Msk                        (0x2UL)        /*!< HRCIM (Bitfield-Mask: 0x01)                           */
+/* ===============================================  MMC_Tx_FPE_Fragment_Cntr  ================================================ */
+ #define R_GMAC1_MMC_Tx_FPE_Fragment_Cntr_TXFFC_Pos                         (0UL)          /*!< TXFFC (Bit 0)                                         */
+ #define R_GMAC1_MMC_Tx_FPE_Fragment_Cntr_TXFFC_Msk                         (0xffffffffUL) /*!< TXFFC (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MMC_Tx_Hold_Req_Cntr  ================================================== */
+ #define R_GMAC1_MMC_Tx_Hold_Req_Cntr_TXHRC_Pos                             (0UL)          /*!< TXHRC (Bit 0)                                         */
+ #define R_GMAC1_MMC_Tx_Hold_Req_Cntr_TXHRC_Msk                             (0xffffffffUL) /*!< TXHRC (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MMC_FPE_Rx_Interrupt  ================================================== */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_PAECIS_Pos                            (0UL)          /*!< PAECIS (Bit 0)                                        */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_PAECIS_Msk                            (0x1UL)        /*!< PAECIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_PSECIS_Pos                            (1UL)          /*!< PSECIS (Bit 1)                                        */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_PSECIS_Msk                            (0x2UL)        /*!< PSECIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_PAOCIS_Pos                            (2UL)          /*!< PAOCIS (Bit 2)                                        */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_PAOCIS_Msk                            (0x4UL)        /*!< PAOCIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_FCIS_Pos                              (3UL)          /*!< FCIS (Bit 3)                                          */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_FCIS_Msk                              (0x8UL)        /*!< FCIS (Bitfield-Mask: 0x01)                            */
+/* ===============================================  MMC_FPE_Rx_Interrupt_Mask  =============================================== */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_Mask_PAECIM_Pos                       (0UL)          /*!< PAECIM (Bit 0)                                        */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_Mask_PAECIM_Msk                       (0x1UL)        /*!< PAECIM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_Mask_PSECIM_Pos                       (1UL)          /*!< PSECIM (Bit 1)                                        */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_Mask_PSECIM_Msk                       (0x2UL)        /*!< PSECIM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_Mask_PAOCIM_Pos                       (2UL)          /*!< PAOCIM (Bit 2)                                        */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_Mask_PAOCIM_Msk                       (0x4UL)        /*!< PAOCIM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_Mask_FCIM_Pos                         (3UL)          /*!< FCIM (Bit 3)                                          */
+ #define R_GMAC1_MMC_FPE_Rx_Interrupt_Mask_FCIM_Msk                         (0x8UL)        /*!< FCIM (Bitfield-Mask: 0x01)                            */
+/* ============================================  MMC_Rx_Packet_Assembly_Err_Cntr  ============================================ */
+ #define R_GMAC1_MMC_Rx_Packet_Assembly_Err_Cntr_PAEC_Pos                   (0UL)          /*!< PAEC (Bit 0)                                          */
+ #define R_GMAC1_MMC_Rx_Packet_Assembly_Err_Cntr_PAEC_Msk                   (0xffffffffUL) /*!< PAEC (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  MMC_Rx_Packet_SMD_Err_Cntr  =============================================== */
+ #define R_GMAC1_MMC_Rx_Packet_SMD_Err_Cntr_PSEC_Pos                        (0UL)          /*!< PSEC (Bit 0)                                          */
+ #define R_GMAC1_MMC_Rx_Packet_SMD_Err_Cntr_PSEC_Msk                        (0xffffffffUL) /*!< PSEC (Bitfield-Mask: 0xffffffff)                      */
+/* ============================================  MMC_Rx_Packet_Assembly_OK_Cntr  ============================================= */
+ #define R_GMAC1_MMC_Rx_Packet_Assembly_OK_Cntr_PAOC_Pos                    (0UL)          /*!< PAOC (Bit 0)                                          */
+ #define R_GMAC1_MMC_Rx_Packet_Assembly_OK_Cntr_PAOC_Msk                    (0xffffffffUL) /*!< PAOC (Bitfield-Mask: 0xffffffff)                   */
+/* ===============================================  MMC_Rx_FPE_Fragment_Cntr  ================================================ */
+ #define R_GMAC1_MMC_Rx_FPE_Fragment_Cntr_FFC_Pos                           (0UL)          /*!< FFC (Bit 0)                                           */
+ #define R_GMAC1_MMC_Rx_FPE_Fragment_Cntr_FFC_Msk                           (0xffffffffUL) /*!< FFC (Bitfield-Mask: 0xffffffff)                       */
+/* ==================================================  MAC_L3_L4_CONTROL0  =================================================== */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL0_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL1  =================================================== */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL1_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL2  =================================================== */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL2_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL3  =================================================== */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL3_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL4  =================================================== */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL4_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL5  =================================================== */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL5_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL6  =================================================== */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL6_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_L3_L4_CONTROL7  =================================================== */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3PEN0_Pos                              (0UL)          /*!< L3PEN0 (Bit 0)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3PEN0_Msk                              (0x1UL)        /*!< L3PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3SAM0_Pos                              (2UL)          /*!< L3SAM0 (Bit 2)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3SAM0_Msk                              (0x4UL)        /*!< L3SAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3SAIM0_Pos                             (3UL)          /*!< L3SAIM0 (Bit 3)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3SAIM0_Msk                             (0x8UL)        /*!< L3SAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3DAM0_Pos                              (4UL)          /*!< L3DAM0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3DAM0_Msk                              (0x10UL)       /*!< L3DAM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3DAIM0_Pos                             (5UL)          /*!< L3DAIM0 (Bit 5)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3DAIM0_Msk                             (0x20UL)       /*!< L3DAIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3HSBM0_Pos                             (6UL)          /*!< L3HSBM0 (Bit 6)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3HSBM0_Msk                             (0x7c0UL)      /*!< L3HSBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3HDBM0_Pos                             (11UL)         /*!< L3HDBM0 (Bit 11)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L3HDBM0_Msk                             (0xf800UL)     /*!< L3HDBM0 (Bitfield-Mask: 0x1f)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4PEN0_Pos                              (16UL)         /*!< L4PEN0 (Bit 16)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4PEN0_Msk                              (0x10000UL)    /*!< L4PEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4SPM0_Pos                              (18UL)         /*!< L4SPM0 (Bit 18)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4SPM0_Msk                              (0x40000UL)    /*!< L4SPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4SPIM0_Pos                             (19UL)         /*!< L4SPIM0 (Bit 19)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4SPIM0_Msk                             (0x80000UL)    /*!< L4SPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4DPM0_Pos                              (20UL)         /*!< L4DPM0 (Bit 20)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4DPM0_Msk                              (0x100000UL)   /*!< L4DPM0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4DPIM0_Pos                             (21UL)         /*!< L4DPIM0 (Bit 21)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_L4DPIM0_Msk                             (0x200000UL)   /*!< L4DPIM0 (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_DMCHN0_Pos                              (24UL)         /*!< DMCHN0 (Bit 24)                                       */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_DMCHN0_Msk                              (0x7000000UL)  /*!< DMCHN0 (Bitfield-Mask: 0x07)                          */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_DMCHEN0_Pos                             (28UL)         /*!< DMCHEN0 (Bit 28)                                      */
+ #define R_GMAC1_MAC_L3_L4_CONTROL7_DMCHEN0_Msk                             (0x10000000UL) /*!< DMCHEN0 (Bitfield-Mask: 0x01)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS0  ================================================== */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS0_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS0_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS0_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS0_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS1  ================================================== */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS1_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS1_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS1_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS1_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS2  ================================================== */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS2_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS2_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS2_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS2_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS3  ================================================== */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS3_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS3_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS3_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS3_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS4  ================================================== */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS4_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS4_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS4_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS4_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS5  ================================================== */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS5_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS5_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS5_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS5_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS6  ================================================== */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS6_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS6_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS6_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS6_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* ==================================================  MAC_LAYER4_ADDRESS7  ================================================== */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS7_L4SP0_Pos                              (0UL)          /*!< L4SP0 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS7_L4SP0_Msk                              (0xffffUL)     /*!< L4SP0 (Bitfield-Mask: 0xffff)                         */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS7_L4DP0_Pos                              (16UL)         /*!< L4DP0 (Bit 16)                                        */
+ #define R_GMAC1_MAC_LAYER4_ADDRESS7_L4DP0_Msk                              (0xffff0000UL) /*!< L4DP0 (Bitfield-Mask: 0xffff)                         */
+/* =================================================  MAC_LAYER3_ADDR0_REG0  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG0_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG0_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG1  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG1_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG1_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG2  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG2_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG2_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG3  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG3_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG3_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG4  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG4_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG4_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG5  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG5_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG5_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG6  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG6_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG6_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR0_REG7  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG7_L3A00_Pos                            (0UL)          /*!< L3A00 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR0_REG7_L3A00_Msk                            (0xffffffffUL) /*!< L3A00 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG0  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG0_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG0_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG1  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG1_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG1_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG2  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG2_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG2_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG3  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG3_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG3_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG4  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG4_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG4_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG5  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG5_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG5_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG6  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG6_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG6_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR1_REG7  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG7_L3A10_Pos                            (0UL)          /*!< L3A10 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR1_REG7_L3A10_Msk                            (0xffffffffUL) /*!< L3A10 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG0  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG0_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG0_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG1  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG1_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG1_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG2  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG2_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG2_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG3  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG3_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG3_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG4  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG4_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG4_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG5  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG5_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG5_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG6  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG6_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG6_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR2_REG7  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG7_L3A20_Pos                            (0UL)          /*!< L3A20 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR2_REG7_L3A20_Msk                            (0xffffffffUL) /*!< L3A20 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG0  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG0_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG0_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG1  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG1_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG1_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG2  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG2_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG2_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG3  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG3_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG3_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG4  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG4_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG4_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG5  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG5_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG5_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG6  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG6_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG6_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_LAYER3_ADDR3_REG7  ================================================= */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG7_L3A30_Pos                            (0UL)          /*!< L3A30 (Bit 0)                                         */
+ #define R_GMAC1_MAC_LAYER3_ADDR3_REG7_L3A30_Msk                            (0xffffffffUL) /*!< L3A30 (Bitfield-Mask: 0xffffffff)                     */
+/* =================================================  MAC_Indir_Access_Ctrl  ================================================= */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_OB_Pos                               (0UL)          /*!< OB (Bit 0)                                            */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_OB_Msk                               (0x1UL)        /*!< OB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_COM_Pos                              (1UL)          /*!< COM (Bit 1)                                           */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_COM_Msk                              (0x2UL)        /*!< COM (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_AUTO_Pos                             (5UL)          /*!< AUTO (Bit 5)                                          */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_AUTO_Msk                             (0x20UL)       /*!< AUTO (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_AOFF_Pos                             (8UL)          /*!< AOFF (Bit 8)                                          */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_AOFF_Msk                             (0xff00UL)     /*!< AOFF (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_MSEL_Pos                             (16UL)         /*!< MSEL (Bit 16)                                         */
+ #define R_GMAC1_MAC_Indir_Access_Ctrl_MSEL_Msk                             (0xf0000UL)    /*!< MSEL (Bitfield-Mask: 0x0f)                            */
+/* =================================================  MAC_Indir_Access_Data  ================================================= */
+ #define R_GMAC1_MAC_Indir_Access_Data_DATA_Pos                             (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_GMAC1_MAC_Indir_Access_Data_DATA_Msk                             (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
+/* =================================================  MAC_Timestamp_Control  ================================================= */
+ #define R_GMAC1_MAC_Timestamp_Control_TSENA_Pos                            (0UL)          /*!< TSENA (Bit 0)                                         */
+ #define R_GMAC1_MAC_Timestamp_Control_TSENA_Msk                            (0x1UL)        /*!< TSENA (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Timestamp_Control_TSTRIG_Pos                           (4UL)          /*!< TSTRIG (Bit 4)                                        */
+ #define R_GMAC1_MAC_Timestamp_Control_TSTRIG_Msk                           (0x10UL)       /*!< TSTRIG (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Timestamp_Control_TSENALL_Pos                          (8UL)          /*!< TSENALL (Bit 8)                                       */
+ #define R_GMAC1_MAC_Timestamp_Control_TSENALL_Msk                          (0x100UL)      /*!< TSENALL (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Timestamp_Control_TSCTRLSSR_Pos                        (9UL)          /*!< TSCTRLSSR (Bit 9)                                     */
+ #define R_GMAC1_MAC_Timestamp_Control_TSCTRLSSR_Msk                        (0x200UL)      /*!< TSCTRLSSR (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_Timestamp_Control_TSVER2ENA_Pos                        (10UL)         /*!< TSVER2ENA (Bit 10)                                    */
+ #define R_GMAC1_MAC_Timestamp_Control_TSVER2ENA_Msk                        (0x400UL)      /*!< TSVER2ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_Timestamp_Control_TSIPENA_Pos                          (11UL)         /*!< TSIPENA (Bit 11)                                      */
+ #define R_GMAC1_MAC_Timestamp_Control_TSIPENA_Msk                          (0x800UL)      /*!< TSIPENA (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Timestamp_Control_TSIPV6ENA_Pos                        (12UL)         /*!< TSIPV6ENA (Bit 12)                                    */
+ #define R_GMAC1_MAC_Timestamp_Control_TSIPV6ENA_Msk                        (0x1000UL)     /*!< TSIPV6ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_Timestamp_Control_TSIPV4ENA_Pos                        (13UL)         /*!< TSIPV4ENA (Bit 13)                                    */
+ #define R_GMAC1_MAC_Timestamp_Control_TSIPV4ENA_Msk                        (0x2000UL)     /*!< TSIPV4ENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_Timestamp_Control_TSEVNTENA_Pos                        (14UL)         /*!< TSEVNTENA (Bit 14)                                    */
+ #define R_GMAC1_MAC_Timestamp_Control_TSEVNTENA_Msk                        (0x4000UL)     /*!< TSEVNTENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_Timestamp_Control_TSMSTRENA_Pos                        (15UL)         /*!< TSMSTRENA (Bit 15)                                    */
+ #define R_GMAC1_MAC_Timestamp_Control_TSMSTRENA_Msk                        (0x8000UL)     /*!< TSMSTRENA (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_Timestamp_Control_SNAPTYPSEL_Pos                       (16UL)         /*!< SNAPTYPSEL (Bit 16)                                   */
+ #define R_GMAC1_MAC_Timestamp_Control_SNAPTYPSEL_Msk                       (0x30000UL)    /*!< SNAPTYPSEL (Bitfield-Mask: 0x03)                      */
+ #define R_GMAC1_MAC_Timestamp_Control_TSENMACADDR_Pos                      (18UL)         /*!< TSENMACADDR (Bit 18)                                  */
+ #define R_GMAC1_MAC_Timestamp_Control_TSENMACADDR_Msk                      (0x40000UL)    /*!< TSENMACADDR (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MAC_Timestamp_Control_CSC_Pos                              (19UL)         /*!< CSC (Bit 19)                                          */
+ #define R_GMAC1_MAC_Timestamp_Control_CSC_Msk                              (0x80000UL)    /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MAC_Timestamp_Control_TXTSSTSM_Pos                         (24UL)         /*!< TXTSSTSM (Bit 24)                                     */
+ #define R_GMAC1_MAC_Timestamp_Control_TXTSSTSM_Msk                         (0x1000000UL)  /*!< TXTSSTSM (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_Timestamp_Control_AV8021ASMEN_Pos                      (28UL)         /*!< AV8021ASMEN (Bit 28)                                  */
+ #define R_GMAC1_MAC_Timestamp_Control_AV8021ASMEN_Msk                      (0x10000000UL) /*!< AV8021ASMEN (Bitfield-Mask: 0x01)                    */
+/* ================================================  MAC_System_Time_Seconds  ================================================ */
+ #define R_GMAC1_MAC_System_Time_Seconds_TSS_Pos                            (0UL)          /*!< TSS (Bit 0)                                           */
+ #define R_GMAC1_MAC_System_Time_Seconds_TSS_Msk                            (0xffffffffUL) /*!< TSS (Bitfield-Mask: 0xffffffff)                       */
+/* ==============================================  MAC_System_Time_Nanoseconds  ============================================== */
+ #define R_GMAC1_MAC_System_Time_Nanoseconds_TSSS_Pos                       (0UL)          /*!< TSSS (Bit 0)                                          */
+ #define R_GMAC1_MAC_System_Time_Nanoseconds_TSSS_Msk                       (0x7fffffffUL) /*!< TSSS (Bitfield-Mask: 0x7fffffff)                      */
+/* =================================================  MAC_Timestamp_Status  ================================================== */
+ #define R_GMAC1_MAC_Timestamp_Status_AUXTSTRIG_Pos                         (2UL)          /*!< AUXTSTRIG (Bit 2)                                     */
+ #define R_GMAC1_MAC_Timestamp_Status_AUXTSTRIG_Msk                         (0x4UL)        /*!< AUXTSTRIG (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_Timestamp_Status_TXTSSIS_Pos                           (15UL)         /*!< TXTSSIS (Bit 15)                                      */
+ #define R_GMAC1_MAC_Timestamp_Status_TXTSSIS_Msk                           (0x8000UL)     /*!< TXTSSIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_Timestamp_Status_ATSSTN_Pos                            (16UL)         /*!< ATSSTN (Bit 16)                                       */
+ #define R_GMAC1_MAC_Timestamp_Status_ATSSTN_Msk                            (0x30000UL)    /*!< ATSSTN (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MAC_Timestamp_Status_ATSSTM_Pos                            (24UL)         /*!< ATSSTM (Bit 24)                                       */
+ #define R_GMAC1_MAC_Timestamp_Status_ATSSTM_Msk                            (0x1000000UL)  /*!< ATSSTM (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Timestamp_Status_ATSNS_Pos                             (25UL)         /*!< ATSNS (Bit 25)                                        */
+ #define R_GMAC1_MAC_Timestamp_Status_ATSNS_Msk                             (0x3e000000UL) /*!< ATSNS (Bitfield-Mask: 0x1f)                           */
+/* ==========================================  MAC_Tx_Timestamp_Status_Nanoseconds  ========================================== */
+ #define R_GMAC1_MAC_Tx_Timestamp_Status_Nanoseconds_TXTSSLO_Pos            (0UL)          /*!< TXTSSLO (Bit 0)                                     */
+ #define R_GMAC1_MAC_Tx_Timestamp_Status_Nanoseconds_TXTSSLO_Msk            (0x7fffffffUL) /*!< TXTSSLO (Bitfield-Mask: 0x7fffffff)        */
+ #define R_GMAC1_MAC_Tx_Timestamp_Status_Nanoseconds_TXTSSMIS_Pos           (31UL)         /*!< TXTSSMIS (Bit 31)                                 */
+ #define R_GMAC1_MAC_Tx_Timestamp_Status_Nanoseconds_TXTSSMIS_Msk           (0x80000000UL) /*!< TXTSSMIS (Bitfield-Mask: 0x01)            */
+/* ============================================  MAC_Tx_Timestamp_Status_Seconds  ============================================ */
+ #define R_GMAC1_MAC_Tx_Timestamp_Status_Seconds_TXTSSHI_Pos                (0UL)          /*!< TXTSSHI (Bit 0)                                       */
+ #define R_GMAC1_MAC_Tx_Timestamp_Status_Seconds_TXTSSHI_Msk                (0xffffffffUL) /*!< TXTSSHI (Bitfield-Mask: 0xffffffff)            */
+/* =================================================  MAC_Auxiliary_Control  ================================================= */
+ #define R_GMAC1_MAC_Auxiliary_Control_ATSFC_Pos                            (0UL)          /*!< ATSFC (Bit 0)                                         */
+ #define R_GMAC1_MAC_Auxiliary_Control_ATSFC_Msk                            (0x1UL)        /*!< ATSFC (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_Auxiliary_Control_ATSEN0_Pos                           (4UL)          /*!< ATSEN0 (Bit 4)                                        */
+ #define R_GMAC1_MAC_Auxiliary_Control_ATSEN0_Msk                           (0x10UL)       /*!< ATSEN0 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_Auxiliary_Control_ATSEN1_Pos                           (5UL)          /*!< ATSEN1 (Bit 5)                                        */
+ #define R_GMAC1_MAC_Auxiliary_Control_ATSEN1_Msk                           (0x20UL)       /*!< ATSEN1 (Bitfield-Mask: 0x01)                          */
+/* ==========================================  MAC_Auxiliary_Timestamp_Nanoseconds  ========================================== */
+ #define R_GMAC1_MAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Pos            (0UL)          /*!< AUXTSLO (Bit 0)                                     */
+ #define R_GMAC1_MAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Msk            (0x7fffffffUL) /*!< AUXTSLO (Bitfield-Mask: 0x7fffffff)        */
+/* ============================================  MAC_Auxiliary_Timestamp_Seconds  ============================================ */
+ #define R_GMAC1_MAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Pos                (0UL)          /*!< AUXTSHI (Bit 0)                                       */
+ #define R_GMAC1_MAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Msk                (0xffffffffUL) /*!< AUXTSHI (Bitfield-Mask: 0xffffffff)            */
+/* ============================================  MAC_Timestamp_Ingress_Asym_Corr  ============================================ */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Asym_Corr_OSTIAC_Pos                 (0UL)          /*!< OSTIAC (Bit 0)                                        */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Asym_Corr_OSTIAC_Msk                 (0xffffffffUL) /*!< OSTIAC (Bitfield-Mask: 0xffffffff)              */
+/* ============================================  MAC_Timestamp_Egress_Asym_Corr  ============================================= */
+ #define R_GMAC1_MAC_Timestamp_Egress_Asym_Corr_OSTEAC_Pos                  (0UL)          /*!< OSTEAC (Bit 0)                                        */
+ #define R_GMAC1_MAC_Timestamp_Egress_Asym_Corr_OSTEAC_Msk                  (0xffffffffUL) /*!< OSTEAC (Bitfield-Mask: 0xffffffff)               */
+/* =========================================  MAC_Timestamp_Ingress_Corr_Nanosecond  ========================================= */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Corr_Nanosecond_TSIC_Pos             (0UL)          /*!< TSIC (Bit 0)                                         */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Corr_Nanosecond_TSIC_Msk             (0xffffffffUL) /*!< TSIC (Bitfield-Mask: 0xffffffff)            */
+/* =========================================  MAC_Timestamp_Egress_Corr_Nanosecond  ========================================== */
+ #define R_GMAC1_MAC_Timestamp_Egress_Corr_Nanosecond_TSEC_Pos              (0UL)          /*!< TSEC (Bit 0)                                          */
+ #define R_GMAC1_MAC_Timestamp_Egress_Corr_Nanosecond_TSEC_Msk              (0xffffffffUL) /*!< TSEC (Bitfield-Mask: 0xffffffff)             */
+/* =========================================  MAC_Timestamp_Ingress_Corr_Subnanosec  ========================================= */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Corr_Subnanosec_TSICSNS_Pos          (8UL)          /*!< TSICSNS (Bit 8)                                   */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Corr_Subnanosec_TSICSNS_Msk          (0xff00UL)     /*!< TSICSNS (Bitfield-Mask: 0xff)                */
+/* =========================================  MAC_Timestamp_Egress_Corr_Subnanosec  ========================================== */
+ #define R_GMAC1_MAC_Timestamp_Egress_Corr_Subnanosec_TSECSNS_Pos           (8UL)          /*!< TSECSNS (Bit 8)                                    */
+ #define R_GMAC1_MAC_Timestamp_Egress_Corr_Subnanosec_TSECSNS_Msk           (0xff00UL)     /*!< TSECSNS (Bitfield-Mask: 0xff)                 */
+/* =============================================  MAC_Timestamp_Ingress_Latency  ============================================= */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Latency_ITLSNS_Pos                   (8UL)          /*!< ITLSNS (Bit 8)                                        */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Latency_ITLSNS_Msk                   (0xff00UL)     /*!< ITLSNS (Bitfield-Mask: 0xff)                          */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Latency_ITLNS_Pos                    (16UL)         /*!< ITLNS (Bit 16)                                        */
+ #define R_GMAC1_MAC_Timestamp_Ingress_Latency_ITLNS_Msk                    (0xfff0000UL)  /*!< ITLNS (Bitfield-Mask: 0xfff)                        */
+/* =============================================  MAC_Timestamp_Egress_Latency  ============================================== */
+ #define R_GMAC1_MAC_Timestamp_Egress_Latency_ETLSNS_Pos                    (8UL)          /*!< ETLSNS (Bit 8)                                        */
+ #define R_GMAC1_MAC_Timestamp_Egress_Latency_ETLSNS_Msk                    (0xff00UL)     /*!< ETLSNS (Bitfield-Mask: 0xff)                          */
+ #define R_GMAC1_MAC_Timestamp_Egress_Latency_ETLNS_Pos                     (16UL)         /*!< ETLNS (Bit 16)                                        */
+ #define R_GMAC1_MAC_Timestamp_Egress_Latency_ETLNS_Msk                     (0xfff0000UL)  /*!< ETLNS (Bitfield-Mask: 0xfff)                         */
+/* ====================================================  MAC_PTO_Control  ==================================================== */
+ #define R_GMAC1_MAC_PTO_Control_PTOEN_Pos                                  (0UL)          /*!< PTOEN (Bit 0)                                         */
+ #define R_GMAC1_MAC_PTO_Control_PTOEN_Msk                                  (0x1UL)        /*!< PTOEN (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MAC_PTO_Control_ASYNCEN_Pos                                (1UL)          /*!< ASYNCEN (Bit 1)                                       */
+ #define R_GMAC1_MAC_PTO_Control_ASYNCEN_Msk                                (0x2UL)        /*!< ASYNCEN (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MAC_PTO_Control_APDREQEN_Pos                               (2UL)          /*!< APDREQEN (Bit 2)                                      */
+ #define R_GMAC1_MAC_PTO_Control_APDREQEN_Msk                               (0x4UL)        /*!< APDREQEN (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MAC_PTO_Control_ASYNCTRIG_Pos                              (4UL)          /*!< ASYNCTRIG (Bit 4)                                     */
+ #define R_GMAC1_MAC_PTO_Control_ASYNCTRIG_Msk                              (0x10UL)       /*!< ASYNCTRIG (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MAC_PTO_Control_APDREQTRIG_Pos                             (5UL)          /*!< APDREQTRIG (Bit 5)                                    */
+ #define R_GMAC1_MAC_PTO_Control_APDREQTRIG_Msk                             (0x20UL)       /*!< APDREQTRIG (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MAC_PTO_Control_DRRDIS_Pos                                 (6UL)          /*!< DRRDIS (Bit 6)                                        */
+ #define R_GMAC1_MAC_PTO_Control_DRRDIS_Msk                                 (0x40UL)       /*!< DRRDIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_PTO_Control_PDRDIS_Pos                                 (7UL)          /*!< PDRDIS (Bit 7)                                        */
+ #define R_GMAC1_MAC_PTO_Control_PDRDIS_Msk                                 (0x80UL)       /*!< PDRDIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MAC_PTO_Control_DN_Pos                                     (8UL)          /*!< DN (Bit 8)                                            */
+ #define R_GMAC1_MAC_PTO_Control_DN_Msk                                     (0xff00UL)     /*!< DN (Bitfield-Mask: 0xff)                              */
+/* ===============================================  MAC_Source_Port_Identity0  =============================================== */
+ #define R_GMAC1_MAC_Source_Port_Identity0_SPI0_Pos                         (0UL)          /*!< SPI0 (Bit 0)                                          */
+ #define R_GMAC1_MAC_Source_Port_Identity0_SPI0_Msk                         (0xffffffffUL) /*!< SPI0 (Bitfield-Mask: 0xffffffff)                      */
+/* ===============================================  MAC_Source_Port_Identity1  =============================================== */
+ #define R_GMAC1_MAC_Source_Port_Identity1_SPI1_Pos                         (0UL)          /*!< SPI1 (Bit 0)                                          */
+ #define R_GMAC1_MAC_Source_Port_Identity1_SPI1_Msk                         (0xffffffffUL) /*!< SPI1 (Bitfield-Mask: 0xffffffff)                      */
+/* ===============================================  MAC_Source_Port_Identity2  =============================================== */
+ #define R_GMAC1_MAC_Source_Port_Identity2_SPI2_Pos                         (0UL)          /*!< SPI2 (Bit 0)                                          */
+ #define R_GMAC1_MAC_Source_Port_Identity2_SPI2_Msk                         (0xffffUL)     /*!< SPI2 (Bitfield-Mask: 0xffff)                          */
+/* ===============================================  MAC_Log_Message_Interval  ================================================ */
+ #define R_GMAC1_MAC_Log_Message_Interval_LSI_Pos                           (0UL)          /*!< LSI (Bit 0)                                           */
+ #define R_GMAC1_MAC_Log_Message_Interval_LSI_Msk                           (0xffUL)       /*!< LSI (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MAC_Log_Message_Interval_DRSYNCR_Pos                       (8UL)          /*!< DRSYNCR (Bit 8)                                       */
+ #define R_GMAC1_MAC_Log_Message_Interval_DRSYNCR_Msk                       (0x700UL)      /*!< DRSYNCR (Bitfield-Mask: 0x07)                         */
+ #define R_GMAC1_MAC_Log_Message_Interval_LMPDRI_Pos                        (24UL)         /*!< LMPDRI (Bit 24)                                       */
+ #define R_GMAC1_MAC_Log_Message_Interval_LMPDRI_Msk                        (0xff000000UL) /*!< LMPDRI (Bitfield-Mask: 0xff)                          */
+/* ==================================================  MTL_Operation_Mode  =================================================== */
+ #define R_GMAC1_MTL_Operation_Mode_DTXSTS_Pos                              (1UL)          /*!< DTXSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Operation_Mode_DTXSTS_Msk                              (0x2UL)        /*!< DTXSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Operation_Mode_RAA_Pos                                 (2UL)          /*!< RAA (Bit 2)                                           */
+ #define R_GMAC1_MTL_Operation_Mode_RAA_Msk                                 (0x4UL)        /*!< RAA (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_Operation_Mode_SCHALG_Pos                              (5UL)          /*!< SCHALG (Bit 5)                                        */
+ #define R_GMAC1_MTL_Operation_Mode_SCHALG_Msk                              (0x60UL)       /*!< SCHALG (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_Operation_Mode_CNTPRST_Pos                             (8UL)          /*!< CNTPRST (Bit 8)                                       */
+ #define R_GMAC1_MTL_Operation_Mode_CNTPRST_Msk                             (0x100UL)      /*!< CNTPRST (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Operation_Mode_CNTCLR_Pos                              (9UL)          /*!< CNTCLR (Bit 9)                                        */
+ #define R_GMAC1_MTL_Operation_Mode_CNTCLR_Msk                              (0x200UL)      /*!< CNTCLR (Bitfield-Mask: 0x01)                          */
+/* =================================================  MTL_Interrupt_Status  ================================================== */
+ #define R_GMAC1_MTL_Interrupt_Status_Q0IS_Pos                              (0UL)          /*!< Q0IS (Bit 0)                                          */
+ #define R_GMAC1_MTL_Interrupt_Status_Q0IS_Msk                              (0x1UL)        /*!< Q0IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_Interrupt_Status_Q1IS_Pos                              (1UL)          /*!< Q1IS (Bit 1)                                          */
+ #define R_GMAC1_MTL_Interrupt_Status_Q1IS_Msk                              (0x2UL)        /*!< Q1IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_Interrupt_Status_Q2IS_Pos                              (2UL)          /*!< Q2IS (Bit 2)                                          */
+ #define R_GMAC1_MTL_Interrupt_Status_Q2IS_Msk                              (0x4UL)        /*!< Q2IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_Interrupt_Status_Q3IS_Pos                              (3UL)          /*!< Q3IS (Bit 3)                                          */
+ #define R_GMAC1_MTL_Interrupt_Status_Q3IS_Msk                              (0x8UL)        /*!< Q3IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_Interrupt_Status_Q4IS_Pos                              (4UL)          /*!< Q4IS (Bit 4)                                          */
+ #define R_GMAC1_MTL_Interrupt_Status_Q4IS_Msk                              (0x10UL)       /*!< Q4IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_Interrupt_Status_Q5IS_Pos                              (5UL)          /*!< Q5IS (Bit 5)                                          */
+ #define R_GMAC1_MTL_Interrupt_Status_Q5IS_Msk                              (0x20UL)       /*!< Q5IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_Interrupt_Status_Q6IS_Pos                              (6UL)          /*!< Q6IS (Bit 6)                                          */
+ #define R_GMAC1_MTL_Interrupt_Status_Q6IS_Msk                              (0x40UL)       /*!< Q6IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_Interrupt_Status_Q7IS_Pos                              (7UL)          /*!< Q7IS (Bit 7)                                          */
+ #define R_GMAC1_MTL_Interrupt_Status_Q7IS_Msk                              (0x80UL)       /*!< Q7IS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_Interrupt_Status_ESTIS_Pos                             (18UL)         /*!< ESTIS (Bit 18)                                        */
+ #define R_GMAC1_MTL_Interrupt_Status_ESTIS_Msk                             (0x40000UL)    /*!< ESTIS (Bitfield-Mask: 0x01)                           */
+/* ===================================================  MTL_RxQ_DMA_Map0  ==================================================== */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q0MDMACH_Pos                              (0UL)          /*!< Q0MDMACH (Bit 0)                                      */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q0MDMACH_Msk                              (0x7UL)        /*!< Q0MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q0DDMACH_Pos                              (4UL)          /*!< Q0DDMACH (Bit 4)                                      */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q0DDMACH_Msk                              (0x10UL)       /*!< Q0DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q1MDMACH_Pos                              (8UL)          /*!< Q1MDMACH (Bit 8)                                      */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q1MDMACH_Msk                              (0x700UL)      /*!< Q1MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q1DDMACH_Pos                              (12UL)         /*!< Q1DDMACH (Bit 12)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q1DDMACH_Msk                              (0x1000UL)     /*!< Q1DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q2MDMACH_Pos                              (16UL)         /*!< Q2MDMACH (Bit 16)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q2MDMACH_Msk                              (0x70000UL)    /*!< Q2MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q2DDMACH_Pos                              (20UL)         /*!< Q2DDMACH (Bit 20)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q2DDMACH_Msk                              (0x100000UL)   /*!< Q2DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q3MDMACH_Pos                              (24UL)         /*!< Q3MDMACH (Bit 24)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q3MDMACH_Msk                              (0x7000000UL)  /*!< Q3MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q3DDMACH_Pos                              (28UL)         /*!< Q3DDMACH (Bit 28)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map0_Q3DDMACH_Msk                              (0x10000000UL) /*!< Q3DDMACH (Bitfield-Mask: 0x01)                        */
+/* ===================================================  MTL_RxQ_DMA_Map1  ==================================================== */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q4MDMACH_Pos                              (0UL)          /*!< Q4MDMACH (Bit 0)                                      */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q4MDMACH_Msk                              (0x7UL)        /*!< Q4MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q4DDMACH_Pos                              (4UL)          /*!< Q4DDMACH (Bit 4)                                      */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q4DDMACH_Msk                              (0x10UL)       /*!< Q4DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q5MDMACH_Pos                              (8UL)          /*!< Q5MDMACH (Bit 8)                                      */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q5MDMACH_Msk                              (0x700UL)      /*!< Q5MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q5DDMACH_Pos                              (12UL)         /*!< Q5DDMACH (Bit 12)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q5DDMACH_Msk                              (0x1000UL)     /*!< Q5DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q6MDMACH_Pos                              (16UL)         /*!< Q6MDMACH (Bit 16)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q6MDMACH_Msk                              (0x70000UL)    /*!< Q6MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q6DDMACH_Pos                              (20UL)         /*!< Q6DDMACH (Bit 20)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q6DDMACH_Msk                              (0x100000UL)   /*!< Q6DDMACH (Bitfield-Mask: 0x01)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q7MDMACH_Pos                              (24UL)         /*!< Q7MDMACH (Bit 24)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q7MDMACH_Msk                              (0x7000000UL)  /*!< Q7MDMACH (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q7DDMACH_Pos                              (28UL)         /*!< Q7DDMACH (Bit 28)                                     */
+ #define R_GMAC1_MTL_RxQ_DMA_Map1_Q7DDMACH_Msk                              (0x10000000UL) /*!< Q7DDMACH (Bitfield-Mask: 0x01)                        */
+/* =====================================================  MTL_TBS_CTRL  ====================================================== */
+ #define R_GMAC1_MTL_TBS_CTRL_ESTM_Pos                                      (0UL)          /*!< ESTM (Bit 0)                                          */
+ #define R_GMAC1_MTL_TBS_CTRL_ESTM_Msk                                      (0x1UL)        /*!< ESTM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_TBS_CTRL_LEOV_Pos                                      (1UL)          /*!< LEOV (Bit 1)                                          */
+ #define R_GMAC1_MTL_TBS_CTRL_LEOV_Msk                                      (0x2UL)        /*!< LEOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_TBS_CTRL_LEGOS_Pos                                     (4UL)          /*!< LEGOS (Bit 4)                                         */
+ #define R_GMAC1_MTL_TBS_CTRL_LEGOS_Msk                                     (0x70UL)       /*!< LEGOS (Bitfield-Mask: 0x07)                           */
+ #define R_GMAC1_MTL_TBS_CTRL_LEOS_Pos                                      (8UL)          /*!< LEOS (Bit 8)                                          */
+ #define R_GMAC1_MTL_TBS_CTRL_LEOS_Msk                                      (0xffffff00UL) /*!< LEOS (Bitfield-Mask: 0xffffff)                        */
+/* ====================================================  MTL_EST_Control  ==================================================== */
+ #define R_GMAC1_MTL_EST_Control_EEST_Pos                                   (0UL)          /*!< EEST (Bit 0)                                          */
+ #define R_GMAC1_MTL_EST_Control_EEST_Msk                                   (0x1UL)        /*!< EEST (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Control_SSWL_Pos                                   (1UL)          /*!< SSWL (Bit 1)                                          */
+ #define R_GMAC1_MTL_EST_Control_SSWL_Msk                                   (0x2UL)        /*!< SSWL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Control_QHLBF_Pos                                  (3UL)          /*!< QHLBF (Bit 3)                                         */
+ #define R_GMAC1_MTL_EST_Control_QHLBF_Msk                                  (0x8UL)        /*!< QHLBF (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_EST_Control_DDBF_Pos                                   (4UL)          /*!< DDBF (Bit 4)                                          */
+ #define R_GMAC1_MTL_EST_Control_DDBF_Msk                                   (0x10UL)       /*!< DDBF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Control_DFBS_Pos                                   (5UL)          /*!< DFBS (Bit 5)                                          */
+ #define R_GMAC1_MTL_EST_Control_DFBS_Msk                                   (0x20UL)       /*!< DFBS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Control_LCSE_Pos                                   (6UL)          /*!< LCSE (Bit 6)                                          */
+ #define R_GMAC1_MTL_EST_Control_LCSE_Msk                                   (0xc0UL)       /*!< LCSE (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC1_MTL_EST_Control_TILS_Pos                                   (8UL)          /*!< TILS (Bit 8)                                          */
+ #define R_GMAC1_MTL_EST_Control_TILS_Msk                                   (0x700UL)      /*!< TILS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_EST_Control_CTOV_Pos                                   (12UL)         /*!< CTOV (Bit 12)                                         */
+ #define R_GMAC1_MTL_EST_Control_CTOV_Msk                                   (0xfff000UL)   /*!< CTOV (Bitfield-Mask: 0xfff)                           */
+ #define R_GMAC1_MTL_EST_Control_PTOV_Pos                                   (24UL)         /*!< PTOV (Bit 24)                                         */
+ #define R_GMAC1_MTL_EST_Control_PTOV_Msk                                   (0xff000000UL) /*!< PTOV (Bitfield-Mask: 0xff)                            */
+/* ==================================================  MTL_EST_Ext_Control  ================================================== */
+ #define R_GMAC1_MTL_EST_Ext_Control_OVHD_Pos                               (0UL)          /*!< OVHD (Bit 0)                                          */
+ #define R_GMAC1_MTL_EST_Ext_Control_OVHD_Msk                               (0x3fUL)       /*!< OVHD (Bitfield-Mask: 0x3f)                            */
+/* ====================================================  MTL_EST_Status  ===================================================== */
+ #define R_GMAC1_MTL_EST_Status_SWLC_Pos                                    (0UL)          /*!< SWLC (Bit 0)                                          */
+ #define R_GMAC1_MTL_EST_Status_SWLC_Msk                                    (0x1UL)        /*!< SWLC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Status_BTRE_Pos                                    (1UL)          /*!< BTRE (Bit 1)                                          */
+ #define R_GMAC1_MTL_EST_Status_BTRE_Msk                                    (0x2UL)        /*!< BTRE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Status_HLBF_Pos                                    (2UL)          /*!< HLBF (Bit 2)                                          */
+ #define R_GMAC1_MTL_EST_Status_HLBF_Msk                                    (0x4UL)        /*!< HLBF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Status_HLBS_Pos                                    (3UL)          /*!< HLBS (Bit 3)                                          */
+ #define R_GMAC1_MTL_EST_Status_HLBS_Msk                                    (0x8UL)        /*!< HLBS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Status_CGCE_Pos                                    (4UL)          /*!< CGCE (Bit 4)                                          */
+ #define R_GMAC1_MTL_EST_Status_CGCE_Msk                                    (0x10UL)       /*!< CGCE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Status_SWOL_Pos                                    (7UL)          /*!< SWOL (Bit 7)                                          */
+ #define R_GMAC1_MTL_EST_Status_SWOL_Msk                                    (0x80UL)       /*!< SWOL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Status_BTRL_Pos                                    (8UL)          /*!< BTRL (Bit 8)                                          */
+ #define R_GMAC1_MTL_EST_Status_BTRL_Msk                                    (0xff00UL)     /*!< BTRL (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_MTL_EST_Status_CGSN_Pos                                    (16UL)         /*!< CGSN (Bit 16)                                         */
+ #define R_GMAC1_MTL_EST_Status_CGSN_Msk                                    (0xf0000UL)    /*!< CGSN (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  MTL_EST_Sch_Error  =================================================== */
+ #define R_GMAC1_MTL_EST_Sch_Error_SEQN_Pos                                 (0UL)          /*!< SEQN (Bit 0)                                          */
+ #define R_GMAC1_MTL_EST_Sch_Error_SEQN_Msk                                 (0xffUL)       /*!< SEQN (Bitfield-Mask: 0xff)                            */
+/* ================================================  MTL_EST_Frm_Size_Error  ================================================= */
+ #define R_GMAC1_MTL_EST_Frm_Size_Error_FEQN_Pos                            (0UL)          /*!< FEQN (Bit 0)                                          */
+ #define R_GMAC1_MTL_EST_Frm_Size_Error_FEQN_Msk                            (0xffUL)       /*!< FEQN (Bitfield-Mask: 0xff)                            */
+/* ===============================================  MTL_EST_Frm_Size_Capture  ================================================ */
+ #define R_GMAC1_MTL_EST_Frm_Size_Capture_HBFS_Pos                          (0UL)          /*!< HBFS (Bit 0)                                          */
+ #define R_GMAC1_MTL_EST_Frm_Size_Capture_HBFS_Msk                          (0x7fffUL)     /*!< HBFS (Bitfield-Mask: 0x7fff)                          */
+ #define R_GMAC1_MTL_EST_Frm_Size_Capture_HBFQ_Pos                          (16UL)         /*!< HBFQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_EST_Frm_Size_Capture_HBFQ_Msk                          (0x70000UL)    /*!< HBFQ (Bitfield-Mask: 0x07)                            */
+/* ==================================================  MTL_EST_Intr_Enable  ================================================== */
+ #define R_GMAC1_MTL_EST_Intr_Enable_IECC_Pos                               (0UL)          /*!< IECC (Bit 0)                                          */
+ #define R_GMAC1_MTL_EST_Intr_Enable_IECC_Msk                               (0x1UL)        /*!< IECC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Intr_Enable_IEBE_Pos                               (1UL)          /*!< IEBE (Bit 1)                                          */
+ #define R_GMAC1_MTL_EST_Intr_Enable_IEBE_Msk                               (0x2UL)        /*!< IEBE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Intr_Enable_IEHF_Pos                               (2UL)          /*!< IEHF (Bit 2)                                          */
+ #define R_GMAC1_MTL_EST_Intr_Enable_IEHF_Msk                               (0x4UL)        /*!< IEHF (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Intr_Enable_IEHS_Pos                               (3UL)          /*!< IEHS (Bit 3)                                          */
+ #define R_GMAC1_MTL_EST_Intr_Enable_IEHS_Msk                               (0x8UL)        /*!< IEHS (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_Intr_Enable_CGCE_Pos                               (4UL)          /*!< CGCE (Bit 4)                                          */
+ #define R_GMAC1_MTL_EST_Intr_Enable_CGCE_Msk                               (0x10UL)       /*!< CGCE (Bitfield-Mask: 0x01)                            */
+/* ==================================================  MTL_EST_GCL_Control  ================================================== */
+ #define R_GMAC1_MTL_EST_GCL_Control_SRWO_Pos                               (0UL)          /*!< SRWO (Bit 0)                                          */
+ #define R_GMAC1_MTL_EST_GCL_Control_SRWO_Msk                               (0x1UL)        /*!< SRWO (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_GCL_Control_R1W0_Pos                               (1UL)          /*!< R1W0 (Bit 1)                                          */
+ #define R_GMAC1_MTL_EST_GCL_Control_R1W0_Msk                               (0x2UL)        /*!< R1W0 (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_GCL_Control_GCRR_Pos                               (2UL)          /*!< GCRR (Bit 2)                                          */
+ #define R_GMAC1_MTL_EST_GCL_Control_GCRR_Msk                               (0x4UL)        /*!< GCRR (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_GCL_Control_DBGM_Pos                               (4UL)          /*!< DBGM (Bit 4)                                          */
+ #define R_GMAC1_MTL_EST_GCL_Control_DBGM_Msk                               (0x10UL)       /*!< DBGM (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_GCL_Control_DBGB_Pos                               (5UL)          /*!< DBGB (Bit 5)                                          */
+ #define R_GMAC1_MTL_EST_GCL_Control_DBGB_Msk                               (0x20UL)       /*!< DBGB (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_EST_GCL_Control_ADDR_Pos                               (8UL)          /*!< ADDR (Bit 8)                                          */
+ #define R_GMAC1_MTL_EST_GCL_Control_ADDR_Msk                               (0xff00UL)     /*!< ADDR (Bitfield-Mask: 0xff)                            */
+/* ===================================================  MTL_EST_GCL_Data  ==================================================== */
+ #define R_GMAC1_MTL_EST_GCL_Data_GCD_Pos                                   (0UL)          /*!< GCD (Bit 0)                                           */
+ #define R_GMAC1_MTL_EST_GCL_Data_GCD_Msk                                   (0xffffffffUL) /*!< GCD (Bitfield-Mask: 0xffffffff)                       */
+/* ===================================================  MTL_FPE_CTRL_STS  ==================================================== */
+ #define R_GMAC1_MTL_FPE_CTRL_STS_AFSZ_Pos                                  (0UL)          /*!< AFSZ (Bit 0)                                          */
+ #define R_GMAC1_MTL_FPE_CTRL_STS_AFSZ_Msk                                  (0x3UL)        /*!< AFSZ (Bitfield-Mask: 0x03)                            */
+ #define R_GMAC1_MTL_FPE_CTRL_STS_PEC_Pos                                   (8UL)          /*!< PEC (Bit 8)                                           */
+ #define R_GMAC1_MTL_FPE_CTRL_STS_PEC_Msk                                   (0xff00UL)     /*!< PEC (Bitfield-Mask: 0xff)                             */
+ #define R_GMAC1_MTL_FPE_CTRL_STS_HRS_Pos                                   (28UL)         /*!< HRS (Bit 28)                                          */
+ #define R_GMAC1_MTL_FPE_CTRL_STS_HRS_Msk                                   (0x10000000UL) /*!< HRS (Bitfield-Mask: 0x01)                             */
+/* ====================================================  MTL_FPE_Advance  ==================================================== */
+ #define R_GMAC1_MTL_FPE_Advance_HADV_Pos                                   (0UL)          /*!< HADV (Bit 0)                                          */
+ #define R_GMAC1_MTL_FPE_Advance_HADV_Msk                                   (0xffffUL)     /*!< HADV (Bitfield-Mask: 0xffff)                          */
+ #define R_GMAC1_MTL_FPE_Advance_RADV_Pos                                   (16UL)         /*!< RADV (Bit 16)                                         */
+ #define R_GMAC1_MTL_FPE_Advance_RADV_Msk                                   (0xffff0000UL) /*!< RADV (Bitfield-Mask: 0xffff)                          */
+/* ================================================  MTL_TXQ0_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC1_MTL_TXQ0_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ==================================================  MTL_TXQ0_UNDERFLOW  =================================================== */
+ #define R_GMAC1_MTL_TXQ0_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC1_MTL_TXQ0_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC1_MTL_TXQ0_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC1_MTL_TXQ0_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ====================================================  MTL_TXQ0_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC1_MTL_TXQ0_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ==================================================  MTL_TXQ0_ETS_STATUS  ================================================== */
+ #define R_GMAC1_MTL_TXQ0_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ0_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ================================================  MTL_TXQ0_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC1_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC1_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ============================================  MTL_Q0_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC1_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ================================================  MTL_RXQ0_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC1_MTL_RXQ0_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ==========================================  MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC1_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC1_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC1_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC1_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC1_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC1_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC1_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ====================================================  MTL_RXQ0_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_RXQ0_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC1_MTL_RXQ0_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_RXQ0_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_RXQ0_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ0_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_RXQ0_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ0_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_RXQ0_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ===================================================  MTL_RXQ0_CONTROL  ==================================================== */
+ #define R_GMAC1_MTL_RXQ0_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC1_MTL_RXQ0_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC1_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ================================================  MTL_TXQ1_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC1_MTL_TXQ1_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ2_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC1_MTL_TXQ2_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ3_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC1_MTL_TXQ3_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ4_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC1_MTL_TXQ4_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ5_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC1_MTL_TXQ5_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ6_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC1_MTL_TXQ6_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_TXQ7_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_FTQ_Pos                            (0UL)          /*!< FTQ (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_FTQ_Msk                            (0x1UL)        /*!< FTQ (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_TSF_Pos                            (1UL)          /*!< TSF (Bit 1)                                           */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_TSF_Msk                            (0x2UL)        /*!< TSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_TXQEN_Pos                          (2UL)          /*!< TXQEN (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_TXQEN_Msk                          (0xcUL)        /*!< TXQEN (Bitfield-Mask: 0x03)                           */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_TTC_Pos                            (4UL)          /*!< TTC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_TTC_Msk                            (0x70UL)       /*!< TTC (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_TQS_Pos                            (16UL)         /*!< TQS (Bit 16)                                          */
+ #define R_GMAC1_MTL_TXQ7_OPERATION_MODE_TQS_Msk                            (0x1f0000UL)   /*!< TQS (Bitfield-Mask: 0x1f)                             */
+/* ==================================================  MTL_TXQ1_UNDERFLOW  =================================================== */
+ #define R_GMAC1_MTL_TXQ1_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC1_MTL_TXQ1_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC1_MTL_TXQ1_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC1_MTL_TXQ1_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ2_UNDERFLOW  =================================================== */
+ #define R_GMAC1_MTL_TXQ2_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC1_MTL_TXQ2_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC1_MTL_TXQ2_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC1_MTL_TXQ2_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ3_UNDERFLOW  =================================================== */
+ #define R_GMAC1_MTL_TXQ3_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC1_MTL_TXQ3_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC1_MTL_TXQ3_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC1_MTL_TXQ3_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ4_UNDERFLOW  =================================================== */
+ #define R_GMAC1_MTL_TXQ4_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC1_MTL_TXQ4_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC1_MTL_TXQ4_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC1_MTL_TXQ4_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ5_UNDERFLOW  =================================================== */
+ #define R_GMAC1_MTL_TXQ5_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC1_MTL_TXQ5_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC1_MTL_TXQ5_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC1_MTL_TXQ5_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ6_UNDERFLOW  =================================================== */
+ #define R_GMAC1_MTL_TXQ6_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC1_MTL_TXQ6_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC1_MTL_TXQ6_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC1_MTL_TXQ6_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ==================================================  MTL_TXQ7_UNDERFLOW  =================================================== */
+ #define R_GMAC1_MTL_TXQ7_UNDERFLOW_UFFRMCNT_Pos                            (0UL)          /*!< UFFRMCNT (Bit 0)                                      */
+ #define R_GMAC1_MTL_TXQ7_UNDERFLOW_UFFRMCNT_Msk                            (0x7ffUL)      /*!< UFFRMCNT (Bitfield-Mask: 0x7ff)                       */
+ #define R_GMAC1_MTL_TXQ7_UNDERFLOW_UFCNTOVF_Pos                            (11UL)         /*!< UFCNTOVF (Bit 11)                                     */
+ #define R_GMAC1_MTL_TXQ7_UNDERFLOW_UFCNTOVF_Msk                            (0x800UL)      /*!< UFCNTOVF (Bitfield-Mask: 0x01)                        */
+/* ====================================================  MTL_TXQ1_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC1_MTL_TXQ1_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ2_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC1_MTL_TXQ2_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ3_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC1_MTL_TXQ3_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ4_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC1_MTL_TXQ4_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ5_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC1_MTL_TXQ5_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ6_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC1_MTL_TXQ6_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* ====================================================  MTL_TXQ7_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TXQPAUSED_Pos                               (0UL)          /*!< TXQPAUSED (Bit 0)                                     */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TXQPAUSED_Msk                               (0x1UL)        /*!< TXQPAUSED (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TRCSTS_Pos                                  (1UL)          /*!< TRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TRCSTS_Msk                                  (0x6UL)        /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TWCSTS_Pos                                  (3UL)          /*!< TWCSTS (Bit 3)                                        */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TWCSTS_Msk                                  (0x8UL)        /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TXQSTS_Pos                                  (4UL)          /*!< TXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TXQSTS_Msk                                  (0x10UL)       /*!< TXQSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TXSTSFSTS_Pos                               (5UL)          /*!< TXSTSFSTS (Bit 5)                                     */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_TXSTSFSTS_Msk                               (0x20UL)       /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_PTXQ_Pos                                    (16UL)         /*!< PTXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_PTXQ_Msk                                    (0x70000UL)    /*!< PTXQ (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_STXSTSF_Pos                                 (20UL)         /*!< STXSTSF (Bit 20)                                      */
+ #define R_GMAC1_MTL_TXQ7_DEBUG_STXSTSF_Msk                                 (0x700000UL)   /*!< STXSTSF (Bitfield-Mask: 0x07)                         */
+/* =================================================  MTL_TXQ1_ETS_CONTROL  ================================================== */
+ #define R_GMAC1_MTL_TXQ1_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ1_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_TXQ1_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC1_MTL_TXQ1_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MTL_TXQ1_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ1_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ2_ETS_CONTROL  ================================================== */
+ #define R_GMAC1_MTL_TXQ2_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ2_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_TXQ2_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC1_MTL_TXQ2_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MTL_TXQ2_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ2_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ3_ETS_CONTROL  ================================================== */
+ #define R_GMAC1_MTL_TXQ3_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ3_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_TXQ3_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC1_MTL_TXQ3_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MTL_TXQ3_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ3_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ4_ETS_CONTROL  ================================================== */
+ #define R_GMAC1_MTL_TXQ4_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ4_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_TXQ4_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC1_MTL_TXQ4_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MTL_TXQ4_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ4_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ5_ETS_CONTROL  ================================================== */
+ #define R_GMAC1_MTL_TXQ5_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ5_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_TXQ5_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC1_MTL_TXQ5_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MTL_TXQ5_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ5_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ6_ETS_CONTROL  ================================================== */
+ #define R_GMAC1_MTL_TXQ6_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ6_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_TXQ6_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC1_MTL_TXQ6_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MTL_TXQ6_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ6_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* =================================================  MTL_TXQ7_ETS_CONTROL  ================================================== */
+ #define R_GMAC1_MTL_TXQ7_ETS_CONTROL_AVALG_Pos                             (2UL)          /*!< AVALG (Bit 2)                                         */
+ #define R_GMAC1_MTL_TXQ7_ETS_CONTROL_AVALG_Msk                             (0x4UL)        /*!< AVALG (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_TXQ7_ETS_CONTROL_CC_Pos                                (3UL)          /*!< CC (Bit 3)                                            */
+ #define R_GMAC1_MTL_TXQ7_ETS_CONTROL_CC_Msk                                (0x8UL)        /*!< CC (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_MTL_TXQ7_ETS_CONTROL_SLC_Pos                               (4UL)          /*!< SLC (Bit 4)                                           */
+ #define R_GMAC1_MTL_TXQ7_ETS_CONTROL_SLC_Msk                               (0x70UL)       /*!< SLC (Bitfield-Mask: 0x07)                             */
+/* ==================================================  MTL_TXQ1_ETS_STATUS  ================================================== */
+ #define R_GMAC1_MTL_TXQ1_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ1_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ2_ETS_STATUS  ================================================== */
+ #define R_GMAC1_MTL_TXQ2_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ2_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ3_ETS_STATUS  ================================================== */
+ #define R_GMAC1_MTL_TXQ3_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ3_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ4_ETS_STATUS  ================================================== */
+ #define R_GMAC1_MTL_TXQ4_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ4_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ5_ETS_STATUS  ================================================== */
+ #define R_GMAC1_MTL_TXQ5_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ5_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ6_ETS_STATUS  ================================================== */
+ #define R_GMAC1_MTL_TXQ6_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ6_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ==================================================  MTL_TXQ7_ETS_STATUS  ================================================== */
+ #define R_GMAC1_MTL_TXQ7_ETS_STATUS_ABS_Pos                                (0UL)          /*!< ABS (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ7_ETS_STATUS_ABS_Msk                                (0xffffffUL)   /*!< ABS (Bitfield-Mask: 0xffffff)                         */
+/* ================================================  MTL_TXQ1_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC1_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC1_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ2_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC1_MTL_TXQ2_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC1_MTL_TXQ2_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ3_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC1_MTL_TXQ3_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC1_MTL_TXQ3_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ4_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC1_MTL_TXQ4_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC1_MTL_TXQ4_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ5_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC1_MTL_TXQ5_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC1_MTL_TXQ5_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ6_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC1_MTL_TXQ6_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC1_MTL_TXQ6_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ================================================  MTL_TXQ7_QUANTUM_WEIGHT  ================================================ */
+ #define R_GMAC1_MTL_TXQ7_QUANTUM_WEIGHT_ISCQW_Pos                          (0UL)          /*!< ISCQW (Bit 0)                                         */
+ #define R_GMAC1_MTL_TXQ7_QUANTUM_WEIGHT_ISCQW_Msk                          (0x1fffffUL)   /*!< ISCQW (Bitfield-Mask: 0x1fffff)                       */
+/* ===============================================  MTL_TXQ1_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC1_MTL_TXQ1_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ1_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ2_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC1_MTL_TXQ2_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ2_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ3_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC1_MTL_TXQ3_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ3_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ4_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC1_MTL_TXQ4_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ4_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ5_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC1_MTL_TXQ5_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ5_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ6_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC1_MTL_TXQ6_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ6_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===============================================  MTL_TXQ7_SENDSLOPECREDIT  ================================================ */
+ #define R_GMAC1_MTL_TXQ7_SENDSLOPECREDIT_SSC_Pos                           (0UL)          /*!< SSC (Bit 0)                                           */
+ #define R_GMAC1_MTL_TXQ7_SENDSLOPECREDIT_SSC_Msk                           (0x3fffUL)     /*!< SSC (Bitfield-Mask: 0x3fff)                           */
+/* ===================================================  MTL_TXQ1_HICREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ1_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ1_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ2_HICREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ2_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ2_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ3_HICREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ3_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ3_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ4_HICREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ4_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ4_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ5_HICREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ5_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ5_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ6_HICREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ6_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ6_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ7_HICREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ7_HICREDIT_HC_Pos                                   (0UL)          /*!< HC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ7_HICREDIT_HC_Msk                                   (0x1fffffffUL) /*!< HC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ1_LOCREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ1_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ1_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ2_LOCREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ2_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ2_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ3_LOCREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ3_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ3_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ4_LOCREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ4_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ4_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ5_LOCREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ5_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ5_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ6_LOCREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ6_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ6_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ===================================================  MTL_TXQ7_LOCREDIT  =================================================== */
+ #define R_GMAC1_MTL_TXQ7_LOCREDIT_LC_Pos                                   (0UL)          /*!< LC (Bit 0)                                            */
+ #define R_GMAC1_MTL_TXQ7_LOCREDIT_LC_Msk                                   (0x1fffffffUL) /*!< LC (Bitfield-Mask: 0x1fffffff)                        */
+/* ============================================  MTL_Q1_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC1_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q2_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC1_MTL_Q2_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q3_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC1_MTL_Q3_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q4_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC1_MTL_Q4_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q5_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC1_MTL_Q5_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q6_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC1_MTL_Q6_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ============================================  MTL_Q7_INTERRUPT_CONTROL_STATUS  ============================================ */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_TXUNFIS_Pos                (0UL)          /*!< TXUNFIS (Bit 0)                                       */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_TXUNFIS_Msk                (0x1UL)        /*!< TXUNFIS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_ABPSIS_Pos                 (1UL)          /*!< ABPSIS (Bit 1)                                        */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_ABPSIS_Msk                 (0x2UL)        /*!< ABPSIS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_TXUIE_Pos                  (8UL)          /*!< TXUIE (Bit 8)                                         */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_TXUIE_Msk                  (0x100UL)      /*!< TXUIE (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_ABPSIE_Pos                 (9UL)          /*!< ABPSIE (Bit 9)                                        */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_ABPSIE_Msk                 (0x200UL)      /*!< ABPSIE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_RXOVFIS_Pos                (16UL)         /*!< RXOVFIS (Bit 16)                                      */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_RXOVFIS_Msk                (0x10000UL)    /*!< RXOVFIS (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_RXOIE_Pos                  (24UL)         /*!< RXOIE (Bit 24)                                        */
+ #define R_GMAC1_MTL_Q7_INTERRUPT_CONTROL_STATUS_RXOIE_Msk                  (0x1000000UL)  /*!< RXOIE (Bitfield-Mask: 0x01)                       */
+/* ================================================  MTL_RXQ1_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC1_MTL_RXQ1_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ2_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC1_MTL_RXQ2_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ3_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC1_MTL_RXQ3_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ4_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC1_MTL_RXQ4_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ5_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC1_MTL_RXQ5_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ6_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC1_MTL_RXQ6_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ================================================  MTL_RXQ7_OPERATION_MODE  ================================================ */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RTC_Pos                            (0UL)          /*!< RTC (Bit 0)                                           */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RTC_Msk                            (0x3UL)        /*!< RTC (Bitfield-Mask: 0x03)                             */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_FUP_Pos                            (3UL)          /*!< FUP (Bit 3)                                           */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_FUP_Msk                            (0x8UL)        /*!< FUP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_FEP_Pos                            (4UL)          /*!< FEP (Bit 4)                                           */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_FEP_Msk                            (0x10UL)       /*!< FEP (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RSF_Pos                            (5UL)          /*!< RSF (Bit 5)                                           */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RSF_Msk                            (0x20UL)       /*!< RSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_DIS_TCP_EF_Pos                     (6UL)          /*!< DIS_TCP_EF (Bit 6)                                    */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_DIS_TCP_EF_Msk                     (0x40UL)       /*!< DIS_TCP_EF (Bitfield-Mask: 0x01)                      */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_EHFC_Pos                           (7UL)          /*!< EHFC (Bit 7)                                          */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_EHFC_Msk                           (0x80UL)       /*!< EHFC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RFA_Pos                            (8UL)          /*!< RFA (Bit 8)                                           */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RFA_Msk                            (0xf00UL)      /*!< RFA (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RFD_Pos                            (14UL)         /*!< RFD (Bit 14)                                          */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RFD_Msk                            (0x3c000UL)    /*!< RFD (Bitfield-Mask: 0x0f)                             */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RQS_Pos                            (20UL)         /*!< RQS (Bit 20)                                          */
+ #define R_GMAC1_MTL_RXQ7_OPERATION_MODE_RQS_Msk                            (0x1f00000UL)  /*!< RQS (Bitfield-Mask: 0x1f)                             */
+/* ==========================================  MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC1_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC1_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC1_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC1_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC1_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC1_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC1_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC1_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC1_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC1_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC1_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC1_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC1_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC1_MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC1_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC1_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC1_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC1_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC1_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC1_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC1_MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC1_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC1_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC1_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC1_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC1_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC1_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC1_MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC1_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC1_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC1_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC1_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC1_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC1_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC1_MTL_RXQ5_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC1_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC1_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC1_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC1_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC1_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC1_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC1_MTL_RXQ6_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ==========================================  MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT  ========================================== */
+ #define R_GMAC1_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Pos          (0UL)          /*!< OVFPKTCNT (Bit 0)                                 */
+ #define R_GMAC1_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_Msk          (0x7ffUL)      /*!< OVFPKTCNT (Bitfield-Mask: 0x7ff)              */
+ #define R_GMAC1_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Pos          (11UL)         /*!< OVFCNTOVF (Bit 11)                               */
+ #define R_GMAC1_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_Msk          (0x800UL)      /*!< OVFCNTOVF (Bitfield-Mask: 0x01)               */
+ #define R_GMAC1_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Pos          (16UL)         /*!< MISPKTCNT (Bit 16)                               */
+ #define R_GMAC1_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_Msk          (0x7ff0000UL)  /*!< MISPKTCNT (Bitfield-Mask: 0x7ff)          */
+ #define R_GMAC1_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Pos          (27UL)         /*!< MISCNTOVF (Bit 27)                               */
+ #define R_GMAC1_MTL_RXQ7_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_Msk          (0x8000000UL)  /*!< MISCNTOVF (Bitfield-Mask: 0x01)           */
+/* ====================================================  MTL_RXQ1_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_RXQ1_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC1_MTL_RXQ1_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_RXQ1_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_RXQ1_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ1_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_RXQ1_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ1_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_RXQ1_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ2_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_RXQ2_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC1_MTL_RXQ2_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_RXQ2_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_RXQ2_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ2_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_RXQ2_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ2_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_RXQ2_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ3_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_RXQ3_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC1_MTL_RXQ3_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_RXQ3_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_RXQ3_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ3_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_RXQ3_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ3_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_RXQ3_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ4_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_RXQ4_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC1_MTL_RXQ4_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_RXQ4_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_RXQ4_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ4_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_RXQ4_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ4_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_RXQ4_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ5_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_RXQ5_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC1_MTL_RXQ5_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_RXQ5_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_RXQ5_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ5_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_RXQ5_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ5_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_RXQ5_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ6_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_RXQ6_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC1_MTL_RXQ6_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_RXQ6_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_RXQ6_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ6_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_RXQ6_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ6_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_RXQ6_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ====================================================  MTL_RXQ7_DEBUG  ===================================================== */
+ #define R_GMAC1_MTL_RXQ7_DEBUG_RWCSTS_Pos                                  (0UL)          /*!< RWCSTS (Bit 0)                                        */
+ #define R_GMAC1_MTL_RXQ7_DEBUG_RWCSTS_Msk                                  (0x1UL)        /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_MTL_RXQ7_DEBUG_RRCSTS_Pos                                  (1UL)          /*!< RRCSTS (Bit 1)                                        */
+ #define R_GMAC1_MTL_RXQ7_DEBUG_RRCSTS_Msk                                  (0x6UL)        /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ7_DEBUG_RXQSTS_Pos                                  (4UL)          /*!< RXQSTS (Bit 4)                                        */
+ #define R_GMAC1_MTL_RXQ7_DEBUG_RXQSTS_Msk                                  (0x30UL)       /*!< RXQSTS (Bitfield-Mask: 0x03)                          */
+ #define R_GMAC1_MTL_RXQ7_DEBUG_PRXQ_Pos                                    (16UL)         /*!< PRXQ (Bit 16)                                         */
+ #define R_GMAC1_MTL_RXQ7_DEBUG_PRXQ_Msk                                    (0x3fff0000UL) /*!< PRXQ (Bitfield-Mask: 0x3fff)                          */
+/* ===================================================  MTL_RXQ1_CONTROL  ==================================================== */
+ #define R_GMAC1_MTL_RXQ1_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC1_MTL_RXQ1_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC1_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ2_CONTROL  ==================================================== */
+ #define R_GMAC1_MTL_RXQ2_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC1_MTL_RXQ2_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RXQ2_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC1_MTL_RXQ2_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ3_CONTROL  ==================================================== */
+ #define R_GMAC1_MTL_RXQ3_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC1_MTL_RXQ3_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RXQ3_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC1_MTL_RXQ3_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ4_CONTROL  ==================================================== */
+ #define R_GMAC1_MTL_RXQ4_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC1_MTL_RXQ4_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RXQ4_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC1_MTL_RXQ4_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ5_CONTROL  ==================================================== */
+ #define R_GMAC1_MTL_RXQ5_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC1_MTL_RXQ5_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RXQ5_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC1_MTL_RXQ5_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ6_CONTROL  ==================================================== */
+ #define R_GMAC1_MTL_RXQ6_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC1_MTL_RXQ6_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RXQ6_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC1_MTL_RXQ6_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* ===================================================  MTL_RXQ7_CONTROL  ==================================================== */
+ #define R_GMAC1_MTL_RXQ7_CONTROL_RXQ_WEGT_Pos                              (0UL)          /*!< RXQ_WEGT (Bit 0)                                      */
+ #define R_GMAC1_MTL_RXQ7_CONTROL_RXQ_WEGT_Msk                              (0x7UL)        /*!< RXQ_WEGT (Bitfield-Mask: 0x07)                        */
+ #define R_GMAC1_MTL_RXQ7_CONTROL_RXQ_FRM_ARBIT_Pos                         (3UL)          /*!< RXQ_FRM_ARBIT (Bit 3)                                 */
+ #define R_GMAC1_MTL_RXQ7_CONTROL_RXQ_FRM_ARBIT_Msk                         (0x8UL)        /*!< RXQ_FRM_ARBIT (Bitfield-Mask: 0x01)                   */
+/* =======================================================  DMA_Mode  ======================================================== */
+ #define R_GMAC1_DMA_Mode_SWR_Pos                                           (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_GMAC1_DMA_Mode_SWR_Msk                                           (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_Mode_TAA_Pos                                           (2UL)          /*!< TAA (Bit 2)                                           */
+ #define R_GMAC1_DMA_Mode_TAA_Msk                                           (0x1cUL)       /*!< TAA (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_Mode_DSPW_Pos                                          (8UL)          /*!< DSPW (Bit 8)                                          */
+ #define R_GMAC1_DMA_Mode_DSPW_Msk                                          (0x100UL)      /*!< DSPW (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_Mode_TXPR_Pos                                          (11UL)         /*!< TXPR (Bit 11)                                         */
+ #define R_GMAC1_DMA_Mode_TXPR_Msk                                          (0x800UL)      /*!< TXPR (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_Mode_INTM_Pos                                          (16UL)         /*!< INTM (Bit 16)                                         */
+ #define R_GMAC1_DMA_Mode_INTM_Msk                                          (0x30000UL)    /*!< INTM (Bitfield-Mask: 0x03)                            */
+/* ====================================================  DMA_SysBus_Mode  ==================================================== */
+ #define R_GMAC1_DMA_SysBus_Mode_FB_Pos                                     (0UL)          /*!< FB (Bit 0)                                            */
+ #define R_GMAC1_DMA_SysBus_Mode_FB_Msk                                     (0x1UL)        /*!< FB (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_SysBus_Mode_BLEN4_Pos                                  (1UL)          /*!< BLEN4 (Bit 1)                                         */
+ #define R_GMAC1_DMA_SysBus_Mode_BLEN4_Msk                                  (0x2UL)        /*!< BLEN4 (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_SysBus_Mode_BLEN8_Pos                                  (2UL)          /*!< BLEN8 (Bit 2)                                         */
+ #define R_GMAC1_DMA_SysBus_Mode_BLEN8_Msk                                  (0x4UL)        /*!< BLEN8 (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_SysBus_Mode_BLEN16_Pos                                 (3UL)          /*!< BLEN16 (Bit 3)                                        */
+ #define R_GMAC1_DMA_SysBus_Mode_BLEN16_Msk                                 (0x8UL)        /*!< BLEN16 (Bitfield-Mask: 0x01)                          */
+ #define R_GMAC1_DMA_SysBus_Mode_AALE_Pos                                   (10UL)         /*!< AALE (Bit 10)                                         */
+ #define R_GMAC1_DMA_SysBus_Mode_AALE_Msk                                   (0x400UL)      /*!< AALE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_SysBus_Mode_AAL_Pos                                    (12UL)         /*!< AAL (Bit 12)                                          */
+ #define R_GMAC1_DMA_SysBus_Mode_AAL_Msk                                    (0x1000UL)     /*!< AAL (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_SysBus_Mode_ONEKBBE_Pos                                (13UL)         /*!< ONEKBBE (Bit 13)                                      */
+ #define R_GMAC1_DMA_SysBus_Mode_ONEKBBE_Msk                                (0x2000UL)     /*!< ONEKBBE (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_DMA_SysBus_Mode_RD_OSR_LMT_Pos                             (16UL)         /*!< RD_OSR_LMT (Bit 16)                                   */
+ #define R_GMAC1_DMA_SysBus_Mode_RD_OSR_LMT_Msk                             (0xf0000UL)    /*!< RD_OSR_LMT (Bitfield-Mask: 0x0f)                      */
+ #define R_GMAC1_DMA_SysBus_Mode_WR_OSR_LMT_Pos                             (24UL)         /*!< WR_OSR_LMT (Bit 24)                                   */
+ #define R_GMAC1_DMA_SysBus_Mode_WR_OSR_LMT_Msk                             (0xf000000UL)  /*!< WR_OSR_LMT (Bitfield-Mask: 0x0f)                      */
+ #define R_GMAC1_DMA_SysBus_Mode_LPI_XIT_PKT_Pos                            (30UL)         /*!< LPI_XIT_PKT (Bit 30)                                  */
+ #define R_GMAC1_DMA_SysBus_Mode_LPI_XIT_PKT_Msk                            (0x40000000UL) /*!< LPI_XIT_PKT (Bitfield-Mask: 0x01)                     */
+ #define R_GMAC1_DMA_SysBus_Mode_EN_LPI_Pos                                 (31UL)         /*!< EN_LPI (Bit 31)                                       */
+ #define R_GMAC1_DMA_SysBus_Mode_EN_LPI_Msk                                 (0x80000000UL) /*!< EN_LPI (Bitfield-Mask: 0x01)                          */
+/* =================================================  DMA_Interrupt_Status  ================================================== */
+ #define R_GMAC1_DMA_Interrupt_Status_DC0IS_Pos                             (0UL)          /*!< DC0IS (Bit 0)                                         */
+ #define R_GMAC1_DMA_Interrupt_Status_DC0IS_Msk                             (0x1UL)        /*!< DC0IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_DC1IS_Pos                             (1UL)          /*!< DC1IS (Bit 1)                                         */
+ #define R_GMAC1_DMA_Interrupt_Status_DC1IS_Msk                             (0x2UL)        /*!< DC1IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_DC2IS_Pos                             (2UL)          /*!< DC2IS (Bit 2)                                         */
+ #define R_GMAC1_DMA_Interrupt_Status_DC2IS_Msk                             (0x4UL)        /*!< DC2IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_DC3IS_Pos                             (3UL)          /*!< DC3IS (Bit 3)                                         */
+ #define R_GMAC1_DMA_Interrupt_Status_DC3IS_Msk                             (0x8UL)        /*!< DC3IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_DC4IS_Pos                             (4UL)          /*!< DC4IS (Bit 4)                                         */
+ #define R_GMAC1_DMA_Interrupt_Status_DC4IS_Msk                             (0x10UL)       /*!< DC4IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_DC5IS_Pos                             (5UL)          /*!< DC5IS (Bit 5)                                         */
+ #define R_GMAC1_DMA_Interrupt_Status_DC5IS_Msk                             (0x20UL)       /*!< DC5IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_DC6IS_Pos                             (6UL)          /*!< DC6IS (Bit 6)                                         */
+ #define R_GMAC1_DMA_Interrupt_Status_DC6IS_Msk                             (0x40UL)       /*!< DC6IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_DC7IS_Pos                             (7UL)          /*!< DC7IS (Bit 7)                                         */
+ #define R_GMAC1_DMA_Interrupt_Status_DC7IS_Msk                             (0x80UL)       /*!< DC7IS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_MTLIS_Pos                             (16UL)         /*!< MTLIS (Bit 16)                                        */
+ #define R_GMAC1_DMA_Interrupt_Status_MTLIS_Msk                             (0x10000UL)    /*!< MTLIS (Bitfield-Mask: 0x01)                           */
+ #define R_GMAC1_DMA_Interrupt_Status_MACIS_Pos                             (17UL)         /*!< MACIS (Bit 17)                                        */
+ #define R_GMAC1_DMA_Interrupt_Status_MACIS_Msk                             (0x20000UL)    /*!< MACIS (Bitfield-Mask: 0x01)                           */
+/* ===================================================  DMA_Debug_Status0  =================================================== */
+ #define R_GMAC1_DMA_Debug_Status0_AXWHSTS_Pos                              (0UL)          /*!< AXWHSTS (Bit 0)                                       */
+ #define R_GMAC1_DMA_Debug_Status0_AXWHSTS_Msk                              (0x1UL)        /*!< AXWHSTS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_DMA_Debug_Status0_AXRHSTS_Pos                              (1UL)          /*!< AXRHSTS (Bit 1)                                       */
+ #define R_GMAC1_DMA_Debug_Status0_AXRHSTS_Msk                              (0x2UL)        /*!< AXRHSTS (Bitfield-Mask: 0x01)                         */
+ #define R_GMAC1_DMA_Debug_Status0_RPS0_Pos                                 (8UL)          /*!< RPS0 (Bit 8)                                          */
+ #define R_GMAC1_DMA_Debug_Status0_RPS0_Msk                                 (0xf00UL)      /*!< RPS0 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status0_TPS0_Pos                                 (12UL)         /*!< TPS0 (Bit 12)                                         */
+ #define R_GMAC1_DMA_Debug_Status0_TPS0_Msk                                 (0xf000UL)     /*!< TPS0 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status0_RPS1_Pos                                 (16UL)         /*!< RPS1 (Bit 16)                                         */
+ #define R_GMAC1_DMA_Debug_Status0_RPS1_Msk                                 (0xf0000UL)    /*!< RPS1 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status0_TPS1_Pos                                 (20UL)         /*!< TPS1 (Bit 20)                                         */
+ #define R_GMAC1_DMA_Debug_Status0_TPS1_Msk                                 (0xf00000UL)   /*!< TPS1 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status0_RPS2_Pos                                 (24UL)         /*!< RPS2 (Bit 24)                                         */
+ #define R_GMAC1_DMA_Debug_Status0_RPS2_Msk                                 (0xf000000UL)  /*!< RPS2 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status0_TPS2_Pos                                 (28UL)         /*!< TPS2 (Bit 28)                                         */
+ #define R_GMAC1_DMA_Debug_Status0_TPS2_Msk                                 (0xf0000000UL) /*!< TPS2 (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  DMA_Debug_Status1  =================================================== */
+ #define R_GMAC1_DMA_Debug_Status1_RPS3_Pos                                 (0UL)          /*!< RPS3 (Bit 0)                                          */
+ #define R_GMAC1_DMA_Debug_Status1_RPS3_Msk                                 (0xfUL)        /*!< RPS3 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status1_TPS3_Pos                                 (4UL)          /*!< TPS3 (Bit 4)                                          */
+ #define R_GMAC1_DMA_Debug_Status1_TPS3_Msk                                 (0xf0UL)       /*!< TPS3 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status1_RPS4_Pos                                 (8UL)          /*!< RPS4 (Bit 8)                                          */
+ #define R_GMAC1_DMA_Debug_Status1_RPS4_Msk                                 (0xf00UL)      /*!< RPS4 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status1_TPS4_Pos                                 (12UL)         /*!< TPS4 (Bit 12)                                         */
+ #define R_GMAC1_DMA_Debug_Status1_TPS4_Msk                                 (0xf000UL)     /*!< TPS4 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status1_RPS5_Pos                                 (16UL)         /*!< RPS5 (Bit 16)                                         */
+ #define R_GMAC1_DMA_Debug_Status1_RPS5_Msk                                 (0xf0000UL)    /*!< RPS5 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status1_TPS5_Pos                                 (20UL)         /*!< TPS5 (Bit 20)                                         */
+ #define R_GMAC1_DMA_Debug_Status1_TPS5_Msk                                 (0xf00000UL)   /*!< TPS5 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status1_RPS6_Pos                                 (24UL)         /*!< RPS6 (Bit 24)                                         */
+ #define R_GMAC1_DMA_Debug_Status1_RPS6_Msk                                 (0xf000000UL)  /*!< RPS6 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status1_TPS6_Pos                                 (28UL)         /*!< TPS6 (Bit 28)                                         */
+ #define R_GMAC1_DMA_Debug_Status1_TPS6_Msk                                 (0xf0000000UL) /*!< TPS6 (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  DMA_Debug_Status2  =================================================== */
+ #define R_GMAC1_DMA_Debug_Status2_RPS7_Pos                                 (0UL)          /*!< RPS7 (Bit 0)                                          */
+ #define R_GMAC1_DMA_Debug_Status2_RPS7_Msk                                 (0xfUL)        /*!< RPS7 (Bitfield-Mask: 0x0f)                            */
+ #define R_GMAC1_DMA_Debug_Status2_TPS7_Pos                                 (4UL)          /*!< TPS7 (Bit 4)                                          */
+ #define R_GMAC1_DMA_Debug_Status2_TPS7_Msk                                 (0xf0UL)       /*!< TPS7 (Bitfield-Mask: 0x0f)                            */
+/* ================================================  AXI_LPI_Entry_Interval  ================================================= */
+ #define R_GMAC1_AXI_LPI_Entry_Interval_LPIEI_Pos                           (0UL)          /*!< LPIEI (Bit 0)                                         */
+ #define R_GMAC1_AXI_LPI_Entry_Interval_LPIEI_Msk                           (0xfUL)        /*!< LPIEI (Bitfield-Mask: 0x0f)                           */
+/* =====================================================  DMA_TBS_CTRL0  ===================================================== */
+ #define R_GMAC1_DMA_TBS_CTRL0_FTOV_Pos                                     (0UL)          /*!< FTOV (Bit 0)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL0_FTOV_Msk                                     (0x1UL)        /*!< FTOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_TBS_CTRL0_FGOS_Pos                                     (4UL)          /*!< FGOS (Bit 4)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL0_FGOS_Msk                                     (0x70UL)       /*!< FGOS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_DMA_TBS_CTRL0_FTOS_Pos                                     (8UL)          /*!< FTOS (Bit 8)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL0_FTOS_Msk                                     (0xffffff00UL) /*!< FTOS (Bitfield-Mask: 0xffffff)                        */
+/* =====================================================  DMA_TBS_CTRL1  ===================================================== */
+ #define R_GMAC1_DMA_TBS_CTRL1_FTOV_Pos                                     (0UL)          /*!< FTOV (Bit 0)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL1_FTOV_Msk                                     (0x1UL)        /*!< FTOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_TBS_CTRL1_FGOS_Pos                                     (4UL)          /*!< FGOS (Bit 4)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL1_FGOS_Msk                                     (0x70UL)       /*!< FGOS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_DMA_TBS_CTRL1_FTOS_Pos                                     (8UL)          /*!< FTOS (Bit 8)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL1_FTOS_Msk                                     (0xffffff00UL) /*!< FTOS (Bitfield-Mask: 0xffffff)                        */
+/* =====================================================  DMA_TBS_CTRL2  ===================================================== */
+ #define R_GMAC1_DMA_TBS_CTRL2_FTOV_Pos                                     (0UL)          /*!< FTOV (Bit 0)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL2_FTOV_Msk                                     (0x1UL)        /*!< FTOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_TBS_CTRL2_FGOS_Pos                                     (4UL)          /*!< FGOS (Bit 4)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL2_FGOS_Msk                                     (0x70UL)       /*!< FGOS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_DMA_TBS_CTRL2_FTOS_Pos                                     (8UL)          /*!< FTOS (Bit 8)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL2_FTOS_Msk                                     (0xffffff00UL) /*!< FTOS (Bitfield-Mask: 0xffffff)                        */
+/* =====================================================  DMA_TBS_CTRL3  ===================================================== */
+ #define R_GMAC1_DMA_TBS_CTRL3_FTOV_Pos                                     (0UL)          /*!< FTOV (Bit 0)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL3_FTOV_Msk                                     (0x1UL)        /*!< FTOV (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_TBS_CTRL3_FGOS_Pos                                     (4UL)          /*!< FGOS (Bit 4)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL3_FGOS_Msk                                     (0x70UL)       /*!< FGOS (Bitfield-Mask: 0x07)                            */
+ #define R_GMAC1_DMA_TBS_CTRL3_FTOS_Pos                                     (8UL)          /*!< FTOS (Bit 8)                                          */
+ #define R_GMAC1_DMA_TBS_CTRL3_FTOS_Msk                                     (0xffffff00UL) /*!< FTOS (Bitfield-Mask: 0xffffff)                        */
+/* ====================================================  DMA_CH0_CONTROL  ==================================================== */
+ #define R_GMAC1_DMA_CH0_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC1_DMA_CH0_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH0_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC1_DMA_CH0_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH1_CONTROL  ==================================================== */
+ #define R_GMAC1_DMA_CH1_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC1_DMA_CH1_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH1_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC1_DMA_CH1_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH2_CONTROL  ==================================================== */
+ #define R_GMAC1_DMA_CH2_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC1_DMA_CH2_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH2_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC1_DMA_CH2_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH3_CONTROL  ==================================================== */
+ #define R_GMAC1_DMA_CH3_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC1_DMA_CH3_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH3_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC1_DMA_CH3_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH4_CONTROL  ==================================================== */
+ #define R_GMAC1_DMA_CH4_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC1_DMA_CH4_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH4_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC1_DMA_CH4_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH5_CONTROL  ==================================================== */
+ #define R_GMAC1_DMA_CH5_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC1_DMA_CH5_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH5_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC1_DMA_CH5_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH6_CONTROL  ==================================================== */
+ #define R_GMAC1_DMA_CH6_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC1_DMA_CH6_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH6_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC1_DMA_CH6_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ====================================================  DMA_CH7_CONTROL  ==================================================== */
+ #define R_GMAC1_DMA_CH7_CONTROL_DSL_Pos                                    (18UL)         /*!< DSL (Bit 18)                                          */
+ #define R_GMAC1_DMA_CH7_CONTROL_DSL_Msk                                    (0x1c0000UL)   /*!< DSL (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH7_CONTROL_SPH_Pos                                    (24UL)         /*!< SPH (Bit 24)                                          */
+ #define R_GMAC1_DMA_CH7_CONTROL_SPH_Msk                                    (0x1000000UL)  /*!< SPH (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH0_TX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC1_DMA_CH0_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH1_TX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC1_DMA_CH1_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH2_TX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC1_DMA_CH2_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH3_TX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC1_DMA_CH3_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH4_TX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC1_DMA_CH4_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH5_TX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC1_DMA_CH5_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH6_TX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC1_DMA_CH6_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH7_TX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_ST_Pos                                  (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_ST_Msk                                  (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_TCW_Pos                                 (1UL)          /*!< TCW (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_TCW_Msk                                 (0xeUL)        /*!< TCW (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_OSF_Pos                                 (4UL)          /*!< OSF (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_OSF_Msk                                 (0x10UL)       /*!< OSF (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_IPBL_Pos                                (15UL)         /*!< IPBL (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_IPBL_Msk                                (0x8000UL)     /*!< IPBL (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_TxPBL_Pos                               (16UL)         /*!< TxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_TxPBL_Msk                               (0x3f0000UL)   /*!< TxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_EDSE_Pos                                (28UL)         /*!< EDSE (Bit 28)                                         */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_EDSE_Msk                                (0x10000000UL) /*!< EDSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_TFSEL_Pos                               (29UL)         /*!< TFSEL (Bit 29)                                        */
+ #define R_GMAC1_DMA_CH7_TX_CONTROL_TFSEL_Msk                               (0x60000000UL) /*!< TFSEL (Bitfield-Mask: 0x03)                           */
+/* ==================================================  DMA_CH0_RX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH1_RX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH2_RX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH3_RX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH4_RX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH5_RX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH6_RX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==================================================  DMA_CH7_RX_CONTROL  =================================================== */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_SR_Pos                                  (0UL)          /*!< SR (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_SR_Msk                                  (0x1UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_RBSZ_x_0_Pos                            (1UL)          /*!< RBSZ_x_0 (Bit 1)                                      */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_RBSZ_x_0_Msk                            (0x1eUL)       /*!< RBSZ_x_0 (Bitfield-Mask: 0x0f)                        */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_RBSZ_13_y_Pos                           (5UL)          /*!< RBSZ_13_y (Bit 5)                                     */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_RBSZ_13_y_Msk                           (0x7fe0UL)     /*!< RBSZ_13_y (Bitfield-Mask: 0x3ff)                      */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_RxPBL_Pos                               (16UL)         /*!< RxPBL (Bit 16)                                        */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_RxPBL_Msk                               (0x3f0000UL)   /*!< RxPBL (Bitfield-Mask: 0x3f)                           */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_RPF_Pos                                 (31UL)         /*!< RPF (Bit 31)                                          */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL_RPF_Msk                                 (0x80000000UL) /*!< RPF (Bitfield-Mask: 0x01)                             */
+/* ==============================================  DMA_CH0_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH1_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH2_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH2_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH2_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH3_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH3_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH3_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH4_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH4_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH4_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH5_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH5_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH5_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH6_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH6_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH6_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH7_TXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH7_TXDESC_LIST_ADDRESS_TDESLA_Pos                     (0UL)          /*!< TDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH7_TXDESC_LIST_ADDRESS_TDESLA_Msk                     (0xffffffffUL) /*!< TDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH0_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH1_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH2_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH2_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH2_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH3_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH3_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH3_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH4_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH4_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH4_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH5_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH5_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH5_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH6_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH6_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH6_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH7_RXDESC_LIST_ADDRESS  ============================================== */
+ #define R_GMAC1_DMA_CH7_RXDESC_LIST_ADDRESS_RDESLA_Pos                     (0UL)          /*!< RDESLA (Bit 0)                                        */
+ #define R_GMAC1_DMA_CH7_RXDESC_LIST_ADDRESS_RDESLA_Msk                     (0xffffffffUL) /*!< RDESLA (Bitfield-Mask: 0xffffffff)                  */
+/* ==============================================  DMA_CH0_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH1_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH2_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH2_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH2_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH3_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH3_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH3_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH4_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH4_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH4_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH5_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH5_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH5_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH6_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH6_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH6_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH7_TXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH7_TXDESC_TAIL_POINTER_TDTP_Pos                       (0UL)          /*!< TDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH7_TXDESC_TAIL_POINTER_TDTP_Msk                       (0xffffffffUL) /*!< TDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH0_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH1_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH2_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH2_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH2_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH3_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH3_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH3_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH4_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH4_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH4_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH5_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH5_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH5_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH6_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH6_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH6_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH7_RXDESC_TAIL_POINTER  ============================================== */
+ #define R_GMAC1_DMA_CH7_RXDESC_TAIL_POINTER_RDTP_Pos                       (0UL)          /*!< RDTP (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH7_RXDESC_TAIL_POINTER_RDTP_Msk                       (0xffffffffUL) /*!< RDTP (Bitfield-Mask: 0xffffffff)                      */
+/* ==============================================  DMA_CH0_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC1_DMA_CH0_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH0_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH1_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC1_DMA_CH1_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH1_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH2_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC1_DMA_CH2_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH2_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH3_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC1_DMA_CH3_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH3_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH4_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC1_DMA_CH4_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH4_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH5_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC1_DMA_CH5_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH5_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH6_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC1_DMA_CH6_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH6_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  DMA_CH7_TXDESC_RING_LENGTH  =============================================== */
+ #define R_GMAC1_DMA_CH7_TXDESC_RING_LENGTH_TDRL_Pos                        (0UL)          /*!< TDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH7_TXDESC_RING_LENGTH_TDRL_Msk                        (0x3ffUL)      /*!< TDRL (Bitfield-Mask: 0x3ff)                           */
+/* ==================================================  DMA_CH0_RX_CONTROL2  ================================================== */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC1_DMA_CH0_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH1_RX_CONTROL2  ================================================== */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC1_DMA_CH1_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH2_RX_CONTROL2  ================================================== */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC1_DMA_CH2_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH3_RX_CONTROL2  ================================================== */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC1_DMA_CH3_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH4_RX_CONTROL2  ================================================== */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC1_DMA_CH4_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH5_RX_CONTROL2  ================================================== */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC1_DMA_CH5_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH6_RX_CONTROL2  ================================================== */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC1_DMA_CH6_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ==================================================  DMA_CH7_RX_CONTROL2  ================================================== */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL2_RDRL_Pos                               (0UL)          /*!< RDRL (Bit 0)                                          */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL2_RDRL_Msk                               (0x3ffUL)      /*!< RDRL (Bitfield-Mask: 0x3ff)                           */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL2_ARBS_Pos                               (18UL)         /*!< ARBS (Bit 18)                                         */
+ #define R_GMAC1_DMA_CH7_RX_CONTROL2_ARBS_Msk                               (0xfc0000UL)   /*!< ARBS (Bitfield-Mask: 0x3f)                            */
+/* ===============================================  DMA_CH0_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH0_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH1_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH1_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH2_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH2_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH3_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH3_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH4_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH4_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH5_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH5_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH6_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH6_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ===============================================  DMA_CH7_INTERRUPT_ENABLE  ================================================ */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_TIE_Pos                           (0UL)          /*!< TIE (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_TIE_Msk                           (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_TXSE_Pos                          (1UL)          /*!< TXSE (Bit 1)                                          */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_TXSE_Msk                          (0x2UL)        /*!< TXSE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_TBUE_Pos                          (2UL)          /*!< TBUE (Bit 2)                                          */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_TBUE_Msk                          (0x4UL)        /*!< TBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_RIE_Pos                           (6UL)          /*!< RIE (Bit 6)                                           */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_RIE_Msk                           (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_RBUE_Pos                          (7UL)          /*!< RBUE (Bit 7)                                          */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_RBUE_Msk                          (0x80UL)       /*!< RBUE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_RSE_Pos                           (8UL)          /*!< RSE (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_RSE_Msk                           (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_RWTE_Pos                          (9UL)          /*!< RWTE (Bit 9)                                          */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_RWTE_Msk                          (0x200UL)      /*!< RWTE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_ETIE_Pos                          (10UL)         /*!< ETIE (Bit 10)                                         */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_ETIE_Msk                          (0x400UL)      /*!< ETIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_ERIE_Pos                          (11UL)         /*!< ERIE (Bit 11)                                         */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_ERIE_Msk                          (0x800UL)      /*!< ERIE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_FBEE_Pos                          (12UL)         /*!< FBEE (Bit 12)                                         */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_FBEE_Msk                          (0x1000UL)     /*!< FBEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_CDEE_Pos                          (13UL)         /*!< CDEE (Bit 13)                                         */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_CDEE_Msk                          (0x2000UL)     /*!< CDEE (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_AIE_Pos                           (14UL)         /*!< AIE (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_AIE_Msk                           (0x4000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_NIE_Pos                           (15UL)         /*!< NIE (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH7_INTERRUPT_ENABLE_NIE_Msk                           (0x8000UL)     /*!< NIE (Bitfield-Mask: 0x01)                             */
+/* ==========================================  DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC1_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC1_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC1_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC1_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC1_DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC1_DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC1_DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC1_DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC1_DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC1_DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC1_DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC1_DMA_CH5_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC1_DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC1_DMA_CH6_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* ==========================================  DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER  ========================================== */
+ #define R_GMAC1_DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Pos                (0UL)          /*!< RWT (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER_RWT_Msk                (0xffUL)       /*!< RWT (Bitfield-Mask: 0xff)                            */
+ #define R_GMAC1_DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Pos               (16UL)         /*!< RWTU (Bit 16)                                         */
+ #define R_GMAC1_DMA_CH7_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_Msk               (0x30000UL)    /*!< RWTU (Bitfield-Mask: 0x03)                       */
+/* =========================================  DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC1_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC1_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC1_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC1_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC1_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC1_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC1_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC1_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC1_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC1_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC1_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC1_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH5_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC1_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC1_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH6_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* =========================================  DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS  ========================================== */
+ #define R_GMAC1_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_ESC_Pos               (0UL)          /*!< ESC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_ESC_Msk               (0x1UL)        /*!< ESC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_ASC_Pos               (1UL)          /*!< ASC (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_ASC_Msk               (0x2UL)        /*!< ASC (Bitfield-Mask: 0x01)                            */
+ #define R_GMAC1_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_SIV_Pos               (4UL)          /*!< SIV (Bit 4)                                           */
+ #define R_GMAC1_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_SIV_Msk               (0xfff0UL)     /*!< SIV (Bitfield-Mask: 0xfff)                        */
+ #define R_GMAC1_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_RSN_Pos               (16UL)         /*!< RSN (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH7_SLOT_FUNCTION_CONTROL_STATUS_RSN_Msk               (0xf0000UL)    /*!< RSN (Bitfield-Mask: 0x0f)                        */
+/* ==============================================  DMA_CH0_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH1_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH2_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH2_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH2_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH3_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH3_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH3_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH4_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH4_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH4_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH5_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH5_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH5_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH6_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH6_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH6_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH7_CURRENT_APP_TXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH7_CURRENT_APP_TXDESC_CURTDESAPTR_Pos                 (0UL)          /*!< CURTDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH7_CURRENT_APP_TXDESC_CURTDESAPTR_Msk                 (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH0_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH1_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH2_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH2_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH2_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH3_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH3_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH3_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH4_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH4_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH4_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH5_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH5_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH5_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH6_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH6_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH6_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* ==============================================  DMA_CH7_CURRENT_APP_RXDESC  =============================================== */
+ #define R_GMAC1_DMA_CH7_CURRENT_APP_RXDESC_CURRDESAPTR_Pos                 (0UL)          /*!< CURRDESAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH7_CURRENT_APP_RXDESC_CURRDESAPTR_Msk                 (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)         */
+/* =============================================  DMA_CH0_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH1_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH2_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH2_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH2_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH3_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH3_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH3_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH4_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH4_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH4_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH5_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH5_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH5_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH6_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH6_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH6_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH7_CURRENT_APP_TXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH7_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Pos               (0UL)          /*!< CURTBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH7_CURRENT_APP_TXBUFFER_CURTBUFAPTR_Msk               (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH0_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH1_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH2_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH2_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH2_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH3_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH3_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH3_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH4_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH4_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH4_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH5_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH5_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH5_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH6_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH6_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH6_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* =============================================  DMA_CH7_CURRENT_APP_RXBUFFER  ============================================== */
+ #define R_GMAC1_DMA_CH7_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Pos               (0UL)          /*!< CURRBUFAPTR (Bit 0)                                   */
+ #define R_GMAC1_DMA_CH7_CURRENT_APP_RXBUFFER_CURRBUFAPTR_Msk               (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff)       */
+/* ====================================================  DMA_CH0_STATUS  ===================================================== */
+ #define R_GMAC1_DMA_CH0_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH0_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH0_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH0_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC1_DMA_CH0_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC1_DMA_CH0_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH0_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC1_DMA_CH0_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH0_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC1_DMA_CH0_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC1_DMA_CH0_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC1_DMA_CH0_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC1_DMA_CH0_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC1_DMA_CH0_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH0_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH0_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH0_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH0_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC1_DMA_CH0_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH1_STATUS  ===================================================== */
+ #define R_GMAC1_DMA_CH1_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH1_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH1_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH1_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC1_DMA_CH1_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC1_DMA_CH1_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH1_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC1_DMA_CH1_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH1_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC1_DMA_CH1_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC1_DMA_CH1_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC1_DMA_CH1_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC1_DMA_CH1_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC1_DMA_CH1_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH1_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH1_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH1_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH1_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC1_DMA_CH1_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH2_STATUS  ===================================================== */
+ #define R_GMAC1_DMA_CH2_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH2_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH2_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH2_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC1_DMA_CH2_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC1_DMA_CH2_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH2_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC1_DMA_CH2_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH2_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC1_DMA_CH2_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC1_DMA_CH2_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC1_DMA_CH2_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC1_DMA_CH2_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC1_DMA_CH2_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH2_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH2_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH2_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH2_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC1_DMA_CH2_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH3_STATUS  ===================================================== */
+ #define R_GMAC1_DMA_CH3_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH3_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH3_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH3_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC1_DMA_CH3_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC1_DMA_CH3_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH3_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC1_DMA_CH3_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH3_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC1_DMA_CH3_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC1_DMA_CH3_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC1_DMA_CH3_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC1_DMA_CH3_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC1_DMA_CH3_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH3_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH3_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH3_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH3_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC1_DMA_CH3_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH4_STATUS  ===================================================== */
+ #define R_GMAC1_DMA_CH4_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH4_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH4_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH4_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC1_DMA_CH4_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC1_DMA_CH4_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH4_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC1_DMA_CH4_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH4_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC1_DMA_CH4_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC1_DMA_CH4_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC1_DMA_CH4_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC1_DMA_CH4_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC1_DMA_CH4_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH4_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH4_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH4_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH4_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC1_DMA_CH4_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH5_STATUS  ===================================================== */
+ #define R_GMAC1_DMA_CH5_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH5_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH5_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH5_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC1_DMA_CH5_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC1_DMA_CH5_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH5_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC1_DMA_CH5_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH5_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC1_DMA_CH5_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC1_DMA_CH5_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC1_DMA_CH5_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC1_DMA_CH5_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC1_DMA_CH5_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH5_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH5_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH5_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH5_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC1_DMA_CH5_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH6_STATUS  ===================================================== */
+ #define R_GMAC1_DMA_CH6_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH6_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH6_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH6_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC1_DMA_CH6_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC1_DMA_CH6_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH6_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC1_DMA_CH6_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH6_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC1_DMA_CH6_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC1_DMA_CH6_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC1_DMA_CH6_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC1_DMA_CH6_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC1_DMA_CH6_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH6_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH6_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH6_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH6_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC1_DMA_CH6_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ====================================================  DMA_CH7_STATUS  ===================================================== */
+ #define R_GMAC1_DMA_CH7_STATUS_TI_Pos                                      (0UL)          /*!< TI (Bit 0)                                            */
+ #define R_GMAC1_DMA_CH7_STATUS_TI_Msk                                      (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH7_STATUS_TPS_Pos                                     (1UL)          /*!< TPS (Bit 1)                                           */
+ #define R_GMAC1_DMA_CH7_STATUS_TPS_Msk                                     (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_TBU_Pos                                     (2UL)          /*!< TBU (Bit 2)                                           */
+ #define R_GMAC1_DMA_CH7_STATUS_TBU_Msk                                     (0x4UL)        /*!< TBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_RI_Pos                                      (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_GMAC1_DMA_CH7_STATUS_RI_Msk                                      (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_GMAC1_DMA_CH7_STATUS_RBU_Pos                                     (7UL)          /*!< RBU (Bit 7)                                           */
+ #define R_GMAC1_DMA_CH7_STATUS_RBU_Msk                                     (0x80UL)       /*!< RBU (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_RPS_Pos                                     (8UL)          /*!< RPS (Bit 8)                                           */
+ #define R_GMAC1_DMA_CH7_STATUS_RPS_Msk                                     (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_RWT_Pos                                     (9UL)          /*!< RWT (Bit 9)                                           */
+ #define R_GMAC1_DMA_CH7_STATUS_RWT_Msk                                     (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_ETI_Pos                                     (10UL)         /*!< ETI (Bit 10)                                          */
+ #define R_GMAC1_DMA_CH7_STATUS_ETI_Msk                                     (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_ERI_Pos                                     (11UL)         /*!< ERI (Bit 11)                                          */
+ #define R_GMAC1_DMA_CH7_STATUS_ERI_Msk                                     (0x800UL)      /*!< ERI (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_FBE_Pos                                     (12UL)         /*!< FBE (Bit 12)                                          */
+ #define R_GMAC1_DMA_CH7_STATUS_FBE_Msk                                     (0x1000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_CDE_Pos                                     (13UL)         /*!< CDE (Bit 13)                                          */
+ #define R_GMAC1_DMA_CH7_STATUS_CDE_Msk                                     (0x2000UL)     /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_AIS_Pos                                     (14UL)         /*!< AIS (Bit 14)                                          */
+ #define R_GMAC1_DMA_CH7_STATUS_AIS_Msk                                     (0x4000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_NIS_Pos                                     (15UL)         /*!< NIS (Bit 15)                                          */
+ #define R_GMAC1_DMA_CH7_STATUS_NIS_Msk                                     (0x8000UL)     /*!< NIS (Bitfield-Mask: 0x01)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_TEB_Pos                                     (16UL)         /*!< TEB (Bit 16)                                          */
+ #define R_GMAC1_DMA_CH7_STATUS_TEB_Msk                                     (0x70000UL)    /*!< TEB (Bitfield-Mask: 0x07)                             */
+ #define R_GMAC1_DMA_CH7_STATUS_REB_Pos                                     (19UL)         /*!< REB (Bit 19)                                          */
+ #define R_GMAC1_DMA_CH7_STATUS_REB_Msk                                     (0x380000UL)   /*!< REB (Bitfield-Mask: 0x07)                             */
+/* ================================================  DMA_CH0_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC1_DMA_CH0_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH0_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC1_DMA_CH0_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH0_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH1_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC1_DMA_CH1_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH1_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC1_DMA_CH1_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH1_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH2_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC1_DMA_CH2_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH2_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC1_DMA_CH2_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH2_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH3_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC1_DMA_CH3_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH3_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC1_DMA_CH3_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH3_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH4_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC1_DMA_CH4_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH4_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC1_DMA_CH4_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH4_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH5_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC1_DMA_CH5_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH5_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC1_DMA_CH5_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH5_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH6_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC1_DMA_CH6_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH6_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC1_DMA_CH6_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH6_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+/* ================================================  DMA_CH7_MISS_FRAME_CNT  ================================================= */
+ #define R_GMAC1_DMA_CH7_MISS_FRAME_CNT_MFC_Pos                             (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_GMAC1_DMA_CH7_MISS_FRAME_CNT_MFC_Msk                             (0x7ffUL)      /*!< MFC (Bitfield-Mask: 0x7ff)                            */
+ #define R_GMAC1_DMA_CH7_MISS_FRAME_CNT_MFCO_Pos                            (15UL)         /*!< MFCO (Bit 15)                                         */
+ #define R_GMAC1_DMA_CH7_MISS_FRAME_CNT_MFCO_Msk                            (0x8000UL)     /*!< MFCO (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USBHC                                          ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  HCREVISION  ======================================================= */
+ #define R_USBHC_HCREVISION_REV_Pos              (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_USBHC_HCREVISION_REV_Msk              (0xffUL)       /*!< REV (Bitfield-Mask: 0xff)                             */
+/* =======================================================  HCCONTROL  ======================================================= */
+ #define R_USBHC_HCCONTROL_CBSR_Pos              (0UL)          /*!< CBSR (Bit 0)                                          */
+ #define R_USBHC_HCCONTROL_CBSR_Msk              (0x3UL)        /*!< CBSR (Bitfield-Mask: 0x03)                            */
+ #define R_USBHC_HCCONTROL_PLE_Pos               (2UL)          /*!< PLE (Bit 2)                                           */
+ #define R_USBHC_HCCONTROL_PLE_Msk               (0x4UL)        /*!< PLE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCONTROL_IE_Pos                (3UL)          /*!< IE (Bit 3)                                            */
+ #define R_USBHC_HCCONTROL_IE_Msk                (0x8UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCCONTROL_CLE_Pos               (4UL)          /*!< CLE (Bit 4)                                           */
+ #define R_USBHC_HCCONTROL_CLE_Msk               (0x10UL)       /*!< CLE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCONTROL_BLE_Pos               (5UL)          /*!< BLE (Bit 5)                                           */
+ #define R_USBHC_HCCONTROL_BLE_Msk               (0x20UL)       /*!< BLE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCONTROL_HCFS_Pos              (6UL)          /*!< HCFS (Bit 6)                                          */
+ #define R_USBHC_HCCONTROL_HCFS_Msk              (0xc0UL)       /*!< HCFS (Bitfield-Mask: 0x03)                            */
+ #define R_USBHC_HCCONTROL_IR_Pos                (8UL)          /*!< IR (Bit 8)                                            */
+ #define R_USBHC_HCCONTROL_IR_Msk                (0x100UL)      /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCCONTROL_RWC_Pos               (9UL)          /*!< RWC (Bit 9)                                           */
+ #define R_USBHC_HCCONTROL_RWC_Msk               (0x200UL)      /*!< RWC (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCONTROL_RWE_Pos               (10UL)         /*!< RWE (Bit 10)                                          */
+ #define R_USBHC_HCCONTROL_RWE_Msk               (0x400UL)      /*!< RWE (Bitfield-Mask: 0x01)                             */
+/* ====================================================  HCCOMMANDSTATUS  ==================================================== */
+ #define R_USBHC_HCCOMMANDSTATUS_HCR_Pos         (0UL)          /*!< HCR (Bit 0)                                           */
+ #define R_USBHC_HCCOMMANDSTATUS_HCR_Msk         (0x1UL)        /*!< HCR (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCOMMANDSTATUS_CLF_Pos         (1UL)          /*!< CLF (Bit 1)                                           */
+ #define R_USBHC_HCCOMMANDSTATUS_CLF_Msk         (0x2UL)        /*!< CLF (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCOMMANDSTATUS_BLF_Pos         (2UL)          /*!< BLF (Bit 2)                                           */
+ #define R_USBHC_HCCOMMANDSTATUS_BLF_Msk         (0x4UL)        /*!< BLF (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCOMMANDSTATUS_OCR_Pos         (3UL)          /*!< OCR (Bit 3)                                           */
+ #define R_USBHC_HCCOMMANDSTATUS_OCR_Msk         (0x8UL)        /*!< OCR (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCCOMMANDSTATUS_SOC_Pos         (16UL)         /*!< SOC (Bit 16)                                          */
+ #define R_USBHC_HCCOMMANDSTATUS_SOC_Msk         (0x30000UL)    /*!< SOC (Bitfield-Mask: 0x03)                             */
+/* ===================================================  HCINTERRUPTSTATUS  =================================================== */
+ #define R_USBHC_HCINTERRUPTSTATUS_SO_Pos        (0UL)          /*!< SO (Bit 0)                                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_SO_Msk        (0x1UL)        /*!< SO (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCINTERRUPTSTATUS_WDH_Pos       (1UL)          /*!< WDH (Bit 1)                                           */
+ #define R_USBHC_HCINTERRUPTSTATUS_WDH_Msk       (0x2UL)        /*!< WDH (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTSTATUS_SF_Pos        (2UL)          /*!< SF (Bit 2)                                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_SF_Msk        (0x4UL)        /*!< SF (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCINTERRUPTSTATUS_RD_Pos        (3UL)          /*!< RD (Bit 3)                                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_RD_Msk        (0x8UL)        /*!< RD (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCINTERRUPTSTATUS_UE_Pos        (4UL)          /*!< UE (Bit 4)                                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_UE_Msk        (0x10UL)       /*!< UE (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCINTERRUPTSTATUS_FNO_Pos       (5UL)          /*!< FNO (Bit 5)                                           */
+ #define R_USBHC_HCINTERRUPTSTATUS_FNO_Msk       (0x20UL)       /*!< FNO (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Pos      (6UL)          /*!< RHSC (Bit 6)                                          */
+ #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Msk      (0x40UL)       /*!< RHSC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTSTATUS_OC_Pos        (30UL)         /*!< OC (Bit 30)                                           */
+ #define R_USBHC_HCINTERRUPTSTATUS_OC_Msk        (0x40000000UL) /*!< OC (Bitfield-Mask: 0x01)                              */
+/* ===================================================  HCINTERRUPTENABLE  =================================================== */
+ #define R_USBHC_HCINTERRUPTENABLE_SOE_Pos       (0UL)          /*!< SOE (Bit 0)                                           */
+ #define R_USBHC_HCINTERRUPTENABLE_SOE_Msk       (0x1UL)        /*!< SOE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_WDHE_Pos      (1UL)          /*!< WDHE (Bit 1)                                          */
+ #define R_USBHC_HCINTERRUPTENABLE_WDHE_Msk      (0x2UL)        /*!< WDHE (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTENABLE_SFE_Pos       (2UL)          /*!< SFE (Bit 2)                                           */
+ #define R_USBHC_HCINTERRUPTENABLE_SFE_Msk       (0x4UL)        /*!< SFE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_RDE_Pos       (3UL)          /*!< RDE (Bit 3)                                           */
+ #define R_USBHC_HCINTERRUPTENABLE_RDE_Msk       (0x8UL)        /*!< RDE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_UEE_Pos       (4UL)          /*!< UEE (Bit 4)                                           */
+ #define R_USBHC_HCINTERRUPTENABLE_UEE_Msk       (0x10UL)       /*!< UEE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_FNOE_Pos      (5UL)          /*!< FNOE (Bit 5)                                          */
+ #define R_USBHC_HCINTERRUPTENABLE_FNOE_Msk      (0x20UL)       /*!< FNOE (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Pos     (6UL)          /*!< RHSCE (Bit 6)                                         */
+ #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Msk     (0x40UL)       /*!< RHSCE (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_HCINTERRUPTENABLE_OCE_Pos       (30UL)         /*!< OCE (Bit 30)                                          */
+ #define R_USBHC_HCINTERRUPTENABLE_OCE_Msk       (0x40000000UL) /*!< OCE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTENABLE_MIE_Pos       (31UL)         /*!< MIE (Bit 31)                                          */
+ #define R_USBHC_HCINTERRUPTENABLE_MIE_Msk       (0x80000000UL) /*!< MIE (Bitfield-Mask: 0x01)                             */
+/* ==================================================  HCINTERRUPTDISABLE  =================================================== */
+ #define R_USBHC_HCINTERRUPTDISABLE_SOD_Pos      (0UL)          /*!< SOD (Bit 0)                                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_SOD_Msk      (0x1UL)        /*!< SOD (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Pos     (1UL)          /*!< WDHD (Bit 1)                                          */
+ #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Msk     (0x2UL)        /*!< WDHD (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTDISABLE_SFD_Pos      (2UL)          /*!< SFD (Bit 2)                                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_SFD_Msk      (0x4UL)        /*!< SFD (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_RDD_Pos      (3UL)          /*!< RDD (Bit 3)                                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_RDD_Msk      (0x8UL)        /*!< RDD (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_UED_Pos      (4UL)          /*!< UED (Bit 4)                                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_UED_Msk      (0x10UL)       /*!< UED (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Pos     (5UL)          /*!< FNOD (Bit 5)                                          */
+ #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Msk     (0x20UL)       /*!< FNOD (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Pos    (6UL)          /*!< RHSCD (Bit 6)                                         */
+ #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Msk    (0x40UL)       /*!< RHSCD (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_HCINTERRUPTDISABLE_OCD_Pos      (30UL)         /*!< OCD (Bit 30)                                          */
+ #define R_USBHC_HCINTERRUPTDISABLE_OCD_Msk      (0x40000000UL) /*!< OCD (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCINTERRUPTDISABLE_MID_Pos      (31UL)         /*!< MID (Bit 31)                                          */
+ #define R_USBHC_HCINTERRUPTDISABLE_MID_Msk      (0x80000000UL) /*!< MID (Bitfield-Mask: 0x01)                             */
+/* ========================================================  HCHCCA  ========================================================= */
+ #define R_USBHC_HCHCCA_RAMBA_Pos                (8UL)          /*!< RAMBA (Bit 8)                                         */
+ #define R_USBHC_HCHCCA_RAMBA_Msk                (0xffffff00UL) /*!< RAMBA (Bitfield-Mask: 0xffffff)                       */
+/* ==================================================  HCPERIODCCURRENTIED  ================================================== */
+ #define R_USBHC_HCPERIODCCURRENTIED_PCED_Pos    (4UL)          /*!< PCED (Bit 4)                                          */
+ #define R_USBHC_HCPERIODCCURRENTIED_PCED_Msk    (0xfffffff0UL) /*!< PCED (Bitfield-Mask: 0xfffffff)                       */
+/* ====================================================  HCCONTROLHEADED  ==================================================== */
+ #define R_USBHC_HCCONTROLHEADED_CHED_Pos        (4UL)          /*!< CHED (Bit 4)                                          */
+ #define R_USBHC_HCCONTROLHEADED_CHED_Msk        (0xfffffff0UL) /*!< CHED (Bitfield-Mask: 0xfffffff)                       */
+/* ==================================================  HCCONTROLCURRENTED  =================================================== */
+ #define R_USBHC_HCCONTROLCURRENTED_CCED_Pos     (4UL)          /*!< CCED (Bit 4)                                          */
+ #define R_USBHC_HCCONTROLCURRENTED_CCED_Msk     (0xfffffff0UL) /*!< CCED (Bitfield-Mask: 0xfffffff)                       */
+/* =====================================================  HCBULKHEADED  ====================================================== */
+ #define R_USBHC_HCBULKHEADED_BHED_Pos           (4UL)          /*!< BHED (Bit 4)                                          */
+ #define R_USBHC_HCBULKHEADED_BHED_Msk           (0xfffffff0UL) /*!< BHED (Bitfield-Mask: 0xfffffff)                       */
+/* ====================================================  HCBULKCURRENTED  ==================================================== */
+ #define R_USBHC_HCBULKCURRENTED_BCED_Pos        (4UL)          /*!< BCED (Bit 4)                                          */
+ #define R_USBHC_HCBULKCURRENTED_BCED_Msk        (0xfffffff0UL) /*!< BCED (Bitfield-Mask: 0xfffffff)                       */
+/* ======================================================  HCDONEHEAD  ======================================================= */
+ #define R_USBHC_HCDONEHEAD_DH_Pos               (4UL)          /*!< DH (Bit 4)                                            */
+ #define R_USBHC_HCDONEHEAD_DH_Msk               (0xfffffff0UL) /*!< DH (Bitfield-Mask: 0xfffffff)                         */
+/* =====================================================  HCFMINTERVAL  ====================================================== */
+ #define R_USBHC_HCFMINTERVAL_FI_Pos             (0UL)          /*!< FI (Bit 0)                                            */
+ #define R_USBHC_HCFMINTERVAL_FI_Msk             (0x3fffUL)     /*!< FI (Bitfield-Mask: 0x3fff)                            */
+ #define R_USBHC_HCFMINTERVAL_FSMPS_Pos          (16UL)         /*!< FSMPS (Bit 16)                                        */
+ #define R_USBHC_HCFMINTERVAL_FSMPS_Msk          (0x7fff0000UL) /*!< FSMPS (Bitfield-Mask: 0x7fff)                         */
+ #define R_USBHC_HCFMINTERVAL_FIT_Pos            (31UL)         /*!< FIT (Bit 31)                                          */
+ #define R_USBHC_HCFMINTERVAL_FIT_Msk            (0x80000000UL) /*!< FIT (Bitfield-Mask: 0x01)                             */
+/* =====================================================  HCFNREMAINING  ===================================================== */
+ #define R_USBHC_HCFNREMAINING_FR_Pos            (0UL)          /*!< FR (Bit 0)                                            */
+ #define R_USBHC_HCFNREMAINING_FR_Msk            (0x3fffUL)     /*!< FR (Bitfield-Mask: 0x3fff)                            */
+ #define R_USBHC_HCFNREMAINING_FRT_Pos           (31UL)         /*!< FRT (Bit 31)                                          */
+ #define R_USBHC_HCFNREMAINING_FRT_Msk           (0x80000000UL) /*!< FRT (Bitfield-Mask: 0x01)                             */
+/* ======================================================  HCFMNUMBER  ======================================================= */
+ #define R_USBHC_HCFMNUMBER_FN_Pos               (0UL)          /*!< FN (Bit 0)                                            */
+ #define R_USBHC_HCFMNUMBER_FN_Msk               (0xffffUL)     /*!< FN (Bitfield-Mask: 0xffff)                            */
+/* =====================================================  HCPERIODSTART  ===================================================== */
+ #define R_USBHC_HCPERIODSTART_PS_Pos            (0UL)          /*!< PS (Bit 0)                                            */
+ #define R_USBHC_HCPERIODSTART_PS_Msk            (0x3fffUL)     /*!< PS (Bitfield-Mask: 0x3fff)                            */
+/* =====================================================  HCLSTHRESHOLD  ===================================================== */
+ #define R_USBHC_HCLSTHRESHOLD_LS_Pos            (0UL)          /*!< LS (Bit 0)                                            */
+ #define R_USBHC_HCLSTHRESHOLD_LS_Msk            (0xfffUL)      /*!< LS (Bitfield-Mask: 0xfff)                             */
+/* ====================================================  HCRHDESCRIPTORA  ==================================================== */
+ #define R_USBHC_HCRHDESCRIPTORA_NDP_Pos         (0UL)          /*!< NDP (Bit 0)                                           */
+ #define R_USBHC_HCRHDESCRIPTORA_NDP_Msk         (0xffUL)       /*!< NDP (Bitfield-Mask: 0xff)                             */
+ #define R_USBHC_HCRHDESCRIPTORA_PSM_Pos         (8UL)          /*!< PSM (Bit 8)                                           */
+ #define R_USBHC_HCRHDESCRIPTORA_PSM_Msk         (0x100UL)      /*!< PSM (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHDESCRIPTORA_NPS_Pos         (9UL)          /*!< NPS (Bit 9)                                           */
+ #define R_USBHC_HCRHDESCRIPTORA_NPS_Msk         (0x200UL)      /*!< NPS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHDESCRIPTORA_DT_Pos          (10UL)         /*!< DT (Bit 10)                                           */
+ #define R_USBHC_HCRHDESCRIPTORA_DT_Msk          (0x400UL)      /*!< DT (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCRHDESCRIPTORA_OCPM_Pos        (11UL)         /*!< OCPM (Bit 11)                                         */
+ #define R_USBHC_HCRHDESCRIPTORA_OCPM_Msk        (0x800UL)      /*!< OCPM (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHDESCRIPTORA_NOCP_Pos        (12UL)         /*!< NOCP (Bit 12)                                         */
+ #define R_USBHC_HCRHDESCRIPTORA_NOCP_Msk        (0x1000UL)     /*!< NOCP (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Pos      (24UL)         /*!< POTPGT (Bit 24)                                       */
+ #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Msk      (0xff000000UL) /*!< POTPGT (Bitfield-Mask: 0xff)                          */
+/* ====================================================  HCRHDESCRIPTORB  ==================================================== */
+ #define R_USBHC_HCRHDESCRIPTORB_DR_Pos          (0UL)          /*!< DR (Bit 0)                                            */
+ #define R_USBHC_HCRHDESCRIPTORB_DR_Msk          (0xffffUL)     /*!< DR (Bitfield-Mask: 0xffff)                            */
+ #define R_USBHC_HCRHDESCRIPTORB_PPCM_Pos        (16UL)         /*!< PPCM (Bit 16)                                         */
+ #define R_USBHC_HCRHDESCRIPTORB_PPCM_Msk        (0xffff0000UL) /*!< PPCM (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  HCRHSTATUS  ======================================================= */
+ #define R_USBHC_HCRHSTATUS_LPS_Pos              (0UL)          /*!< LPS (Bit 0)                                           */
+ #define R_USBHC_HCRHSTATUS_LPS_Msk              (0x1UL)        /*!< LPS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHSTATUS_OCI_Pos              (1UL)          /*!< OCI (Bit 1)                                           */
+ #define R_USBHC_HCRHSTATUS_OCI_Msk              (0x2UL)        /*!< OCI (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHSTATUS_DRWE_Pos             (15UL)         /*!< DRWE (Bit 15)                                         */
+ #define R_USBHC_HCRHSTATUS_DRWE_Msk             (0x8000UL)     /*!< DRWE (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHSTATUS_LPSC_Pos             (16UL)         /*!< LPSC (Bit 16)                                         */
+ #define R_USBHC_HCRHSTATUS_LPSC_Msk             (0x10000UL)    /*!< LPSC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHSTATUS_OCIC_Pos             (17UL)         /*!< OCIC (Bit 17)                                         */
+ #define R_USBHC_HCRHSTATUS_OCIC_Msk             (0x20000UL)    /*!< OCIC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHSTATUS_CRWE_Pos             (31UL)         /*!< CRWE (Bit 31)                                         */
+ #define R_USBHC_HCRHSTATUS_CRWE_Msk             (0x80000000UL) /*!< CRWE (Bitfield-Mask: 0x01)                            */
+/* ====================================================  HCRHPORTSTATUS1  ==================================================== */
+ #define R_USBHC_HCRHPORTSTATUS1_CCS_Pos         (0UL)          /*!< CCS (Bit 0)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_CCS_Msk         (0x1UL)        /*!< CCS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_PES_Pos         (1UL)          /*!< PES (Bit 1)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_PES_Msk         (0x2UL)        /*!< PES (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_PSS_Pos         (2UL)          /*!< PSS (Bit 2)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_PSS_Msk         (0x4UL)        /*!< PSS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_POCI_Pos        (3UL)          /*!< POCI (Bit 3)                                          */
+ #define R_USBHC_HCRHPORTSTATUS1_POCI_Msk        (0x8UL)        /*!< POCI (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_PRS_Pos         (4UL)          /*!< PRS (Bit 4)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_PRS_Msk         (0x10UL)       /*!< PRS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_PPS_Pos         (8UL)          /*!< PPS (Bit 8)                                           */
+ #define R_USBHC_HCRHPORTSTATUS1_PPS_Msk         (0x100UL)      /*!< PPS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_LSDA_Pos        (9UL)          /*!< LSDA (Bit 9)                                          */
+ #define R_USBHC_HCRHPORTSTATUS1_LSDA_Msk        (0x200UL)      /*!< LSDA (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_CSC_Pos         (16UL)         /*!< CSC (Bit 16)                                          */
+ #define R_USBHC_HCRHPORTSTATUS1_CSC_Msk         (0x10000UL)    /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCRHPORTSTATUS1_PESC_Pos        (17UL)         /*!< PESC (Bit 17)                                         */
+ #define R_USBHC_HCRHPORTSTATUS1_PESC_Msk        (0x20000UL)    /*!< PESC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_PSSC_Pos        (18UL)         /*!< PSSC (Bit 18)                                         */
+ #define R_USBHC_HCRHPORTSTATUS1_PSSC_Msk        (0x40000UL)    /*!< PSSC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_OCIC_Pos        (19UL)         /*!< OCIC (Bit 19)                                         */
+ #define R_USBHC_HCRHPORTSTATUS1_OCIC_Msk        (0x80000UL)    /*!< OCIC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCRHPORTSTATUS1_PRSC_Pos        (20UL)         /*!< PRSC (Bit 20)                                         */
+ #define R_USBHC_HCRHPORTSTATUS1_PRSC_Msk        (0x100000UL)   /*!< PRSC (Bitfield-Mask: 0x01)                            */
+/* =====================================================  CAPL_VERSION  ====================================================== */
+ #define R_USBHC_CAPL_VERSION_CRL_Pos            (0UL)          /*!< CRL (Bit 0)                                           */
+ #define R_USBHC_CAPL_VERSION_CRL_Msk            (0xffUL)       /*!< CRL (Bitfield-Mask: 0xff)                             */
+ #define R_USBHC_CAPL_VERSION_HCIVN_Pos          (16UL)         /*!< HCIVN (Bit 16)                                        */
+ #define R_USBHC_CAPL_VERSION_HCIVN_Msk          (0xffff0000UL) /*!< HCIVN (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  HCSPARAMS  ======================================================= */
+ #define R_USBHC_HCSPARAMS_N_PORTS_Pos           (0UL)          /*!< N_PORTS (Bit 0)                                       */
+ #define R_USBHC_HCSPARAMS_N_PORTS_Msk           (0xfUL)        /*!< N_PORTS (Bitfield-Mask: 0x0f)                         */
+ #define R_USBHC_HCSPARAMS_PPC_Pos               (4UL)          /*!< PPC (Bit 4)                                           */
+ #define R_USBHC_HCSPARAMS_PPC_Msk               (0x10UL)       /*!< PPC (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_HCSPARAMS_PTRR_Pos              (7UL)          /*!< PTRR (Bit 7)                                          */
+ #define R_USBHC_HCSPARAMS_PTRR_Msk              (0x80UL)       /*!< PTRR (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCSPARAMS_N_PCC_Pos             (8UL)          /*!< N_PCC (Bit 8)                                         */
+ #define R_USBHC_HCSPARAMS_N_PCC_Msk             (0xf00UL)      /*!< N_PCC (Bitfield-Mask: 0x0f)                           */
+ #define R_USBHC_HCSPARAMS_N_CC_Pos              (12UL)         /*!< N_CC (Bit 12)                                         */
+ #define R_USBHC_HCSPARAMS_N_CC_Msk              (0xf000UL)     /*!< N_CC (Bitfield-Mask: 0x0f)                            */
+ #define R_USBHC_HCSPARAMS_P_INDICATOR_Pos       (16UL)         /*!< P_INDICATOR (Bit 16)                                  */
+ #define R_USBHC_HCSPARAMS_P_INDICATOR_Msk       (0x10000UL)    /*!< P_INDICATOR (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_HCSPARAMS_DBGPTNUM_Pos          (20UL)         /*!< DBGPTNUM (Bit 20)                                     */
+ #define R_USBHC_HCSPARAMS_DBGPTNUM_Msk          (0xf00000UL)   /*!< DBGPTNUM (Bitfield-Mask: 0x0f)                        */
+/* =======================================================  HCCPARAMS  ======================================================= */
+ #define R_USBHC_HCCPARAMS_AC64_Pos              (0UL)          /*!< AC64 (Bit 0)                                          */
+ #define R_USBHC_HCCPARAMS_AC64_Msk              (0x1UL)        /*!< AC64 (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_PFLF_Pos              (1UL)          /*!< PFLF (Bit 1)                                          */
+ #define R_USBHC_HCCPARAMS_PFLF_Msk              (0x2UL)        /*!< PFLF (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_ASPC_Pos              (2UL)          /*!< ASPC (Bit 2)                                          */
+ #define R_USBHC_HCCPARAMS_ASPC_Msk              (0x4UL)        /*!< ASPC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_IST_Pos               (4UL)          /*!< IST (Bit 4)                                           */
+ #define R_USBHC_HCCPARAMS_IST_Msk               (0xf0UL)       /*!< IST (Bitfield-Mask: 0x0f)                             */
+ #define R_USBHC_HCCPARAMS_EECP_Pos              (8UL)          /*!< EECP (Bit 8)                                          */
+ #define R_USBHC_HCCPARAMS_EECP_Msk              (0xff00UL)     /*!< EECP (Bitfield-Mask: 0xff)                            */
+ #define R_USBHC_HCCPARAMS_HP_Pos                (16UL)         /*!< HP (Bit 16)                                           */
+ #define R_USBHC_HCCPARAMS_HP_Msk                (0x10000UL)    /*!< HP (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_HCCPARAMS_LPMC_Pos              (17UL)         /*!< LPMC (Bit 17)                                         */
+ #define R_USBHC_HCCPARAMS_LPMC_Msk              (0x20000UL)    /*!< LPMC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_PCEC_Pos              (18UL)         /*!< PCEC (Bit 18)                                         */
+ #define R_USBHC_HCCPARAMS_PCEC_Msk              (0x40000UL)    /*!< PCEC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_HCCPARAMS_PL32_Pos              (19UL)         /*!< PL32 (Bit 19)                                         */
+ #define R_USBHC_HCCPARAMS_PL32_Msk              (0x80000UL)    /*!< PL32 (Bitfield-Mask: 0x01)                            */
+/* ====================================================  HCSP_PORTROUTE  ===================================================== */
+/* ========================================================  USBCMD  ========================================================= */
+ #define R_USBHC_USBCMD_RS_Pos                   (0UL)          /*!< RS (Bit 0)                                            */
+ #define R_USBHC_USBCMD_RS_Msk                   (0x1UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_USBCMD_HCRESET_Pos              (1UL)          /*!< HCRESET (Bit 1)                                       */
+ #define R_USBHC_USBCMD_HCRESET_Msk              (0x2UL)        /*!< HCRESET (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_USBCMD_FLS_Pos                  (2UL)          /*!< FLS (Bit 2)                                           */
+ #define R_USBHC_USBCMD_FLS_Msk                  (0xcUL)        /*!< FLS (Bitfield-Mask: 0x03)                             */
+ #define R_USBHC_USBCMD_PSE_Pos                  (4UL)          /*!< PSE (Bit 4)                                           */
+ #define R_USBHC_USBCMD_PSE_Msk                  (0x10UL)       /*!< PSE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_USBCMD_ASYNSE_Pos               (5UL)          /*!< ASYNSE (Bit 5)                                        */
+ #define R_USBHC_USBCMD_ASYNSE_Msk               (0x20UL)       /*!< ASYNSE (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBCMD_IAAD_Pos                 (6UL)          /*!< IAAD (Bit 6)                                          */
+ #define R_USBHC_USBCMD_IAAD_Msk                 (0x40UL)       /*!< IAAD (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_USBCMD_LHCR_Pos                 (7UL)          /*!< LHCR (Bit 7)                                          */
+ #define R_USBHC_USBCMD_LHCR_Msk                 (0x80UL)       /*!< LHCR (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_USBCMD_ASPMC_Pos                (8UL)          /*!< ASPMC (Bit 8)                                         */
+ #define R_USBHC_USBCMD_ASPMC_Msk                (0x300UL)      /*!< ASPMC (Bitfield-Mask: 0x03)                           */
+ #define R_USBHC_USBCMD_ASPME_Pos                (11UL)         /*!< ASPME (Bit 11)                                        */
+ #define R_USBHC_USBCMD_ASPME_Msk                (0x800UL)      /*!< ASPME (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBCMD_PPCEE_Pos                (15UL)         /*!< PPCEE (Bit 15)                                        */
+ #define R_USBHC_USBCMD_PPCEE_Msk                (0x8000UL)     /*!< PPCEE (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBCMD_ITC_Pos                  (16UL)         /*!< ITC (Bit 16)                                          */
+ #define R_USBHC_USBCMD_ITC_Msk                  (0xff0000UL)   /*!< ITC (Bitfield-Mask: 0xff)                             */
+ #define R_USBHC_USBCMD_HIRD_Pos                 (24UL)         /*!< HIRD (Bit 24)                                         */
+ #define R_USBHC_USBCMD_HIRD_Msk                 (0xf000000UL)  /*!< HIRD (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  USBSTS  ========================================================= */
+ #define R_USBHC_USBSTS_USBINT_Pos               (0UL)          /*!< USBINT (Bit 0)                                        */
+ #define R_USBHC_USBSTS_USBINT_Msk               (0x1UL)        /*!< USBINT (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBSTS_USBERRINT_Pos            (1UL)          /*!< USBERRINT (Bit 1)                                     */
+ #define R_USBHC_USBSTS_USBERRINT_Msk            (0x2UL)        /*!< USBERRINT (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_USBSTS_PTCGDET_Pos              (2UL)          /*!< PTCGDET (Bit 2)                                       */
+ #define R_USBHC_USBSTS_PTCGDET_Msk              (0x4UL)        /*!< PTCGDET (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_USBSTS_FLROV_Pos                (3UL)          /*!< FLROV (Bit 3)                                         */
+ #define R_USBHC_USBSTS_FLROV_Msk                (0x8UL)        /*!< FLROV (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBSTS_HSYSE_Pos                (4UL)          /*!< HSYSE (Bit 4)                                         */
+ #define R_USBHC_USBSTS_HSYSE_Msk                (0x10UL)       /*!< HSYSE (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBSTS_IAAIS_Pos                (5UL)          /*!< IAAIS (Bit 5)                                         */
+ #define R_USBHC_USBSTS_IAAIS_Msk                (0x20UL)       /*!< IAAIS (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBSTS_EHCSTS_Pos               (12UL)         /*!< EHCSTS (Bit 12)                                       */
+ #define R_USBHC_USBSTS_EHCSTS_Msk               (0x1000UL)     /*!< EHCSTS (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBSTS_RECLAM_Pos               (13UL)         /*!< RECLAM (Bit 13)                                       */
+ #define R_USBHC_USBSTS_RECLAM_Msk               (0x2000UL)     /*!< RECLAM (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBSTS_PSCHSTS_Pos              (14UL)         /*!< PSCHSTS (Bit 14)                                      */
+ #define R_USBHC_USBSTS_PSCHSTS_Msk              (0x4000UL)     /*!< PSCHSTS (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_USBSTS_ASS_Pos                  (15UL)         /*!< ASS (Bit 15)                                          */
+ #define R_USBHC_USBSTS_ASS_Msk                  (0x8000UL)     /*!< ASS (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_USBSTS_PTCGDETC_Pos             (16UL)         /*!< PTCGDETC (Bit 16)                                     */
+ #define R_USBHC_USBSTS_PTCGDETC_Msk             (0xffff0000UL) /*!< PTCGDETC (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  USBINTR  ======================================================== */
+ #define R_USBHC_USBINTR_USBIE_Pos               (0UL)          /*!< USBIE (Bit 0)                                         */
+ #define R_USBHC_USBINTR_USBIE_Msk               (0x1UL)        /*!< USBIE (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_USBINTR_USBEIE_Pos              (1UL)          /*!< USBEIE (Bit 1)                                        */
+ #define R_USBHC_USBINTR_USBEIE_Msk              (0x2UL)        /*!< USBEIE (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBINTR_PTCGIE_Pos              (2UL)          /*!< PTCGIE (Bit 2)                                        */
+ #define R_USBHC_USBINTR_PTCGIE_Msk              (0x4UL)        /*!< PTCGIE (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_USBINTR_FMLSTROE_Pos            (3UL)          /*!< FMLSTROE (Bit 3)                                      */
+ #define R_USBHC_USBINTR_FMLSTROE_Msk            (0x8UL)        /*!< FMLSTROE (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_USBINTR_HSEE_Pos                (4UL)          /*!< HSEE (Bit 4)                                          */
+ #define R_USBHC_USBINTR_HSEE_Msk                (0x10UL)       /*!< HSEE (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_USBINTR_INTAADVE_Pos            (5UL)          /*!< INTAADVE (Bit 5)                                      */
+ #define R_USBHC_USBINTR_INTAADVE_Msk            (0x20UL)       /*!< INTAADVE (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_USBINTR_PCGIE_Pos               (16UL)         /*!< PCGIE (Bit 16)                                        */
+ #define R_USBHC_USBINTR_PCGIE_Msk               (0xffff0000UL) /*!< PCGIE (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  FRINDEX  ======================================================== */
+ #define R_USBHC_FRINDEX_FRAMEINDEX_Pos          (0UL)          /*!< FRAMEINDEX (Bit 0)                                    */
+ #define R_USBHC_FRINDEX_FRAMEINDEX_Msk          (0x3fffUL)     /*!< FRAMEINDEX (Bitfield-Mask: 0x3fff)                    */
+/* =====================================================  CTRLDSSEGMENT  ===================================================== */
+/* ===================================================  PERIODICLISTBASE  ==================================================== */
+ #define R_USBHC_PERIODICLISTBASE_PFLSA_Pos      (12UL)         /*!< PFLSA (Bit 12)                                        */
+ #define R_USBHC_PERIODICLISTBASE_PFLSA_Msk      (0xfffff000UL) /*!< PFLSA (Bitfield-Mask: 0xfffff)                        */
+/* =====================================================  ASYNCLISTADDR  ===================================================== */
+ #define R_USBHC_ASYNCLISTADDR_LPL_Pos           (5UL)          /*!< LPL (Bit 5)                                           */
+ #define R_USBHC_ASYNCLISTADDR_LPL_Msk           (0xffffffe0UL) /*!< LPL (Bitfield-Mask: 0x7ffffff)                        */
+/* ======================================================  CONFIGFLAG  ======================================================= */
+ #define R_USBHC_CONFIGFLAG_CF_Pos               (0UL)          /*!< CF (Bit 0)                                            */
+ #define R_USBHC_CONFIGFLAG_CF_Msk               (0x1UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
+/* ========================================================  PORTSC1  ======================================================== */
+ #define R_USBHC_PORTSC1_CCSTS_Pos               (0UL)          /*!< CCSTS (Bit 0)                                         */
+ #define R_USBHC_PORTSC1_CCSTS_Msk               (0x1UL)        /*!< CCSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_PORTSC1_CSC_Pos                 (1UL)          /*!< CSC (Bit 1)                                           */
+ #define R_USBHC_PORTSC1_CSC_Msk                 (0x2UL)        /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_PORTSC1_PTE_Pos                 (2UL)          /*!< PTE (Bit 2)                                           */
+ #define R_USBHC_PORTSC1_PTE_Msk                 (0x4UL)        /*!< PTE (Bitfield-Mask: 0x01)                             */
+ #define R_USBHC_PORTSC1_PTESC_Pos               (3UL)          /*!< PTESC (Bit 3)                                         */
+ #define R_USBHC_PORTSC1_PTESC_Msk               (0x8UL)        /*!< PTESC (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_PORTSC1_OVCACT_Pos              (4UL)          /*!< OVCACT (Bit 4)                                        */
+ #define R_USBHC_PORTSC1_OVCACT_Msk              (0x10UL)       /*!< OVCACT (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PORTSC1_OVCC_Pos                (5UL)          /*!< OVCC (Bit 5)                                          */
+ #define R_USBHC_PORTSC1_OVCC_Msk                (0x20UL)       /*!< OVCC (Bitfield-Mask: 0x01)                            */
+ #define R_USBHC_PORTSC1_FRCPTRSM_Pos            (6UL)          /*!< FRCPTRSM (Bit 6)                                      */
+ #define R_USBHC_PORTSC1_FRCPTRSM_Msk            (0x40UL)       /*!< FRCPTRSM (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_PORTSC1_SUSPEND_Pos             (7UL)          /*!< SUSPEND (Bit 7)                                       */
+ #define R_USBHC_PORTSC1_SUSPEND_Msk             (0x80UL)       /*!< SUSPEND (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_PORTSC1_PTRST_Pos               (8UL)          /*!< PTRST (Bit 8)                                         */
+ #define R_USBHC_PORTSC1_PTRST_Msk               (0x100UL)      /*!< PTRST (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_PORTSC1_LPMCTL_Pos              (9UL)          /*!< LPMCTL (Bit 9)                                        */
+ #define R_USBHC_PORTSC1_LPMCTL_Msk              (0x200UL)      /*!< LPMCTL (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PORTSC1_LINESTS_Pos             (10UL)         /*!< LINESTS (Bit 10)                                      */
+ #define R_USBHC_PORTSC1_LINESTS_Msk             (0xc00UL)      /*!< LINESTS (Bitfield-Mask: 0x03)                         */
+ #define R_USBHC_PORTSC1_PP_Pos                  (12UL)         /*!< PP (Bit 12)                                           */
+ #define R_USBHC_PORTSC1_PP_Msk                  (0x1000UL)     /*!< PP (Bitfield-Mask: 0x01)                              */
+ #define R_USBHC_PORTSC1_PTOWNR_Pos              (13UL)         /*!< PTOWNR (Bit 13)                                       */
+ #define R_USBHC_PORTSC1_PTOWNR_Msk              (0x2000UL)     /*!< PTOWNR (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PORTSC1_PTINDCTL_Pos            (14UL)         /*!< PTINDCTL (Bit 14)                                     */
+ #define R_USBHC_PORTSC1_PTINDCTL_Msk            (0xc000UL)     /*!< PTINDCTL (Bitfield-Mask: 0x03)                        */
+ #define R_USBHC_PORTSC1_PTTST_Pos               (16UL)         /*!< PTTST (Bit 16)                                        */
+ #define R_USBHC_PORTSC1_PTTST_Msk               (0xf0000UL)    /*!< PTTST (Bitfield-Mask: 0x0f)                           */
+ #define R_USBHC_PORTSC1_WKCNNT_E_Pos            (20UL)         /*!< WKCNNT_E (Bit 20)                                     */
+ #define R_USBHC_PORTSC1_WKCNNT_E_Msk            (0x100000UL)   /*!< WKCNNT_E (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_PORTSC1_WKDSCNNT_E_Pos          (21UL)         /*!< WKDSCNNT_E (Bit 21)                                   */
+ #define R_USBHC_PORTSC1_WKDSCNNT_E_Msk          (0x200000UL)   /*!< WKDSCNNT_E (Bitfield-Mask: 0x01)                      */
+ #define R_USBHC_PORTSC1_WKOC_E_Pos              (22UL)         /*!< WKOC_E (Bit 22)                                       */
+ #define R_USBHC_PORTSC1_WKOC_E_Msk              (0x400000UL)   /*!< WKOC_E (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PORTSC1_SUSPSTS_Pos             (23UL)         /*!< SUSPSTS (Bit 23)                                      */
+ #define R_USBHC_PORTSC1_SUSPSTS_Msk             (0x1800000UL)  /*!< SUSPSTS (Bitfield-Mask: 0x03)                         */
+ #define R_USBHC_PORTSC1_DVADDR_Pos              (25UL)         /*!< DVADDR (Bit 25)                                       */
+ #define R_USBHC_PORTSC1_DVADDR_Msk              (0xfe000000UL) /*!< DVADDR (Bitfield-Mask: 0x7f)                          */
+/* =======================================================  INTENABLE  ======================================================= */
+ #define R_USBHC_INTENABLE_AHB_INTEN_Pos         (0UL)          /*!< AHB_INTEN (Bit 0)                                     */
+ #define R_USBHC_INTENABLE_AHB_INTEN_Msk         (0x1UL)        /*!< AHB_INTEN (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_INTENABLE_USBH_INTAEN_Pos       (1UL)          /*!< USBH_INTAEN (Bit 1)                                   */
+ #define R_USBHC_INTENABLE_USBH_INTAEN_Msk       (0x2UL)        /*!< USBH_INTAEN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_INTENABLE_USBH_INTBEN_Pos       (2UL)          /*!< USBH_INTBEN (Bit 2)                                   */
+ #define R_USBHC_INTENABLE_USBH_INTBEN_Msk       (0x4UL)        /*!< USBH_INTBEN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_INTENABLE_UCOM_INTEN_Pos        (3UL)          /*!< UCOM_INTEN (Bit 3)                                    */
+ #define R_USBHC_INTENABLE_UCOM_INTEN_Msk        (0x8UL)        /*!< UCOM_INTEN (Bitfield-Mask: 0x01)                      */
+ #define R_USBHC_INTENABLE_WAKEON_INTEN_Pos      (4UL)          /*!< WAKEON_INTEN (Bit 4)                                  */
+ #define R_USBHC_INTENABLE_WAKEON_INTEN_Msk      (0x10UL)       /*!< WAKEON_INTEN (Bitfield-Mask: 0x01)                    */
+/* =======================================================  INTSTATUS  ======================================================= */
+ #define R_USBHC_INTSTATUS_AHB_INT_Pos           (0UL)          /*!< AHB_INT (Bit 0)                                       */
+ #define R_USBHC_INTSTATUS_AHB_INT_Msk           (0x1UL)        /*!< AHB_INT (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_INTSTATUS_USBH_INTA_Pos         (1UL)          /*!< USBH_INTA (Bit 1)                                     */
+ #define R_USBHC_INTSTATUS_USBH_INTA_Msk         (0x2UL)        /*!< USBH_INTA (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_INTSTATUS_USBH_INTB_Pos         (2UL)          /*!< USBH_INTB (Bit 2)                                     */
+ #define R_USBHC_INTSTATUS_USBH_INTB_Msk         (0x4UL)        /*!< USBH_INTB (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_INTSTATUS_UCOM_INT_Pos          (3UL)          /*!< UCOM_INT (Bit 3)                                      */
+ #define R_USBHC_INTSTATUS_UCOM_INT_Msk          (0x8UL)        /*!< UCOM_INT (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_INTSTATUS_WAKEON_INT_Pos        (4UL)          /*!< WAKEON_INT (Bit 4)                                    */
+ #define R_USBHC_INTSTATUS_WAKEON_INT_Msk        (0x10UL)       /*!< WAKEON_INT (Bitfield-Mask: 0x01)                      */
+/* =======================================================  AHBBUSCTR  ======================================================= */
+ #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Pos     (0UL)          /*!< MAX_BURST_LEN (Bit 0)                                 */
+ #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Msk     (0x3UL)        /*!< MAX_BURST_LEN (Bitfield-Mask: 0x03)                   */
+ #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Pos     (4UL)          /*!< ALIGN_ADDRESS (Bit 4)                                 */
+ #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Msk     (0x30UL)       /*!< ALIGN_ADDRESS (Bitfield-Mask: 0x03)                   */
+ #define R_USBHC_AHBBUSCTR_PROT_MODE_Pos         (8UL)          /*!< PROT_MODE (Bit 8)                                     */
+ #define R_USBHC_AHBBUSCTR_PROT_MODE_Msk         (0x100UL)      /*!< PROT_MODE (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_AHBBUSCTR_PROT_TYPE_Pos         (12UL)         /*!< PROT_TYPE (Bit 12)                                    */
+ #define R_USBHC_AHBBUSCTR_PROT_TYPE_Msk         (0xf000UL)     /*!< PROT_TYPE (Bitfield-Mask: 0x0f)                       */
+/* ========================================================  USBCTR  ========================================================= */
+ #define R_USBHC_USBCTR_USBH_RST_Pos             (0UL)          /*!< USBH_RST (Bit 0)                                      */
+ #define R_USBHC_USBCTR_USBH_RST_Msk             (0x1UL)        /*!< USBH_RST (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_USBCTR_PLL_RST_Pos              (1UL)          /*!< PLL_RST (Bit 1)                                       */
+ #define R_USBHC_USBCTR_PLL_RST_Msk              (0x2UL)        /*!< PLL_RST (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_USBCTR_DIRPD_Pos                (2UL)          /*!< DIRPD (Bit 2)                                         */
+ #define R_USBHC_USBCTR_DIRPD_Msk                (0x4UL)        /*!< DIRPD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  REVID  ========================================================= */
+ #define R_USBHC_REVID_MINV_Pos                  (0UL)          /*!< MINV (Bit 0)                                          */
+ #define R_USBHC_REVID_MINV_Msk                  (0xffUL)       /*!< MINV (Bitfield-Mask: 0xff)                            */
+ #define R_USBHC_REVID_MAJV_Pos                  (8UL)          /*!< MAJV (Bit 8)                                          */
+ #define R_USBHC_REVID_MAJV_Msk                  (0xff00UL)     /*!< MAJV (Bitfield-Mask: 0xff)                            */
+ #define R_USBHC_REVID_COREID_Pos                (24UL)         /*!< COREID (Bit 24)                                       */
+ #define R_USBHC_REVID_COREID_Msk                (0xff000000UL) /*!< COREID (Bitfield-Mask: 0xff)                          */
+/* ======================================================  OCSLPTIMSET  ====================================================== */
+ #define R_USBHC_OCSLPTIMSET_TIMER_OC_Pos        (0UL)          /*!< TIMER_OC (Bit 0)                                      */
+ #define R_USBHC_OCSLPTIMSET_TIMER_OC_Msk        (0xfffffUL)    /*!< TIMER_OC (Bitfield-Mask: 0xfffff)                     */
+ #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Pos     (20UL)         /*!< TIMER_SLEEP (Bit 20)                                  */
+ #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Msk     (0x1ff00000UL) /*!< TIMER_SLEEP (Bitfield-Mask: 0x1ff)                    */
+/* =======================================================  COMMCTRL  ======================================================== */
+ #define R_USBHC_COMMCTRL_PERI_Pos               (31UL)         /*!< PERI (Bit 31)                                         */
+ #define R_USBHC_COMMCTRL_PERI_Msk               (0x80000000UL) /*!< PERI (Bitfield-Mask: 0x01)                            */
+/* =======================================================  OBINTSTA  ======================================================== */
+ #define R_USBHC_OBINTSTA_IDCHG_STA_Pos          (0UL)          /*!< IDCHG_STA (Bit 0)                                     */
+ #define R_USBHC_OBINTSTA_IDCHG_STA_Msk          (0x1UL)        /*!< IDCHG_STA (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_OBINTSTA_OCINT_STA_Pos          (1UL)          /*!< OCINT_STA (Bit 1)                                     */
+ #define R_USBHC_OBINTSTA_OCINT_STA_Msk          (0x2UL)        /*!< OCINT_STA (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_OBINTSTA_VBSTACHG_STA_Pos       (2UL)          /*!< VBSTACHG_STA (Bit 2)                                  */
+ #define R_USBHC_OBINTSTA_VBSTACHG_STA_Msk       (0x4UL)        /*!< VBSTACHG_STA (Bitfield-Mask: 0x01)                    */
+ #define R_USBHC_OBINTSTA_VBSTAINT_STA_Pos       (3UL)          /*!< VBSTAINT_STA (Bit 3)                                  */
+ #define R_USBHC_OBINTSTA_VBSTAINT_STA_Msk       (0x8UL)        /*!< VBSTAINT_STA (Bitfield-Mask: 0x01)                    */
+ #define R_USBHC_OBINTSTA_VVLDCHG_STA_Pos        (10UL)         /*!< VVLDCHG_STA (Bit 10)                                  */
+ #define R_USBHC_OBINTSTA_VVLDCHG_STA_Msk        (0x400UL)      /*!< VVLDCHG_STA (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_OBINTSTA_IDDIGCHG_STA_Pos       (11UL)         /*!< IDDIGCHG_STA (Bit 11)                                 */
+ #define R_USBHC_OBINTSTA_IDDIGCHG_STA_Msk       (0x800UL)      /*!< IDDIGCHG_STA (Bitfield-Mask: 0x01)                    */
+ #define R_USBHC_OBINTSTA_SESSVLDCHG_STA_Pos     (12UL)         /*!< SESSVLDCHG_STA (Bit 12)                               */
+ #define R_USBHC_OBINTSTA_SESSVLDCHG_STA_Msk     (0x1000UL)     /*!< SESSVLDCHG_STA (Bitfield-Mask: 0x01)                  */
+ #define R_USBHC_OBINTSTA_DMMONCHG_STA_Pos       (16UL)         /*!< DMMONCHG_STA (Bit 16)                                 */
+ #define R_USBHC_OBINTSTA_DMMONCHG_STA_Msk       (0x10000UL)    /*!< DMMONCHG_STA (Bitfield-Mask: 0x01)                    */
+ #define R_USBHC_OBINTSTA_DPMONCHG_STA_Pos       (17UL)         /*!< DPMONCHG_STA (Bit 17)                                 */
+ #define R_USBHC_OBINTSTA_DPMONCHG_STA_Msk       (0x20000UL)    /*!< DPMONCHG_STA (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OBINTEN  ======================================================== */
+ #define R_USBHC_OBINTEN_IDCHG_EN_Pos            (0UL)          /*!< IDCHG_EN (Bit 0)                                      */
+ #define R_USBHC_OBINTEN_IDCHG_EN_Msk            (0x1UL)        /*!< IDCHG_EN (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_OBINTEN_OCINT_EN_Pos            (1UL)          /*!< OCINT_EN (Bit 1)                                      */
+ #define R_USBHC_OBINTEN_OCINT_EN_Msk            (0x2UL)        /*!< OCINT_EN (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_OBINTEN_VBSTACHG_EN_Pos         (2UL)          /*!< VBSTACHG_EN (Bit 2)                                   */
+ #define R_USBHC_OBINTEN_VBSTACHG_EN_Msk         (0x4UL)        /*!< VBSTACHG_EN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_OBINTEN_VBSTAINT_EN_Pos         (3UL)          /*!< VBSTAINT_EN (Bit 3)                                   */
+ #define R_USBHC_OBINTEN_VBSTAINT_EN_Msk         (0x8UL)        /*!< VBSTAINT_EN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_OBINTEN_VVLDCHG_EN_Pos          (10UL)         /*!< VVLDCHG_EN (Bit 10)                                   */
+ #define R_USBHC_OBINTEN_VVLDCHG_EN_Msk          (0x400UL)      /*!< VVLDCHG_EN (Bitfield-Mask: 0x01)                      */
+ #define R_USBHC_OBINTEN_IDDIGCHG_EN_Pos         (11UL)         /*!< IDDIGCHG_EN (Bit 11)                                  */
+ #define R_USBHC_OBINTEN_IDDIGCHG_EN_Msk         (0x800UL)      /*!< IDDIGCHG_EN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_OBINTEN_SESSVLDCHG_EN_Pos       (12UL)         /*!< SESSVLDCHG_EN (Bit 12)                                */
+ #define R_USBHC_OBINTEN_SESSVLDCHG_EN_Msk       (0x1000UL)     /*!< SESSVLDCHG_EN (Bitfield-Mask: 0x01)                   */
+ #define R_USBHC_OBINTEN_DMMONCHG_EN_Pos         (16UL)         /*!< DMMONCHG_EN (Bit 16)                                  */
+ #define R_USBHC_OBINTEN_DMMONCHG_EN_Msk         (0x10000UL)    /*!< DMMONCHG_EN (Bitfield-Mask: 0x01)                     */
+ #define R_USBHC_OBINTEN_DPMONCHG_EN_Pos         (17UL)         /*!< DPMONCHG_EN (Bit 17)                                  */
+ #define R_USBHC_OBINTEN_DPMONCHG_EN_Msk         (0x20000UL)    /*!< DPMONCHG_EN (Bitfield-Mask: 0x01)                     */
+/* ========================================================  VBCTRL  ========================================================= */
+ #define R_USBHC_VBCTRL_VBOUT_Pos                (0UL)          /*!< VBOUT (Bit 0)                                         */
+ #define R_USBHC_VBCTRL_VBOUT_Msk                (0x1UL)        /*!< VBOUT (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_VBCTRL_VBUSENSEL_Pos            (1UL)          /*!< VBUSENSEL (Bit 1)                                     */
+ #define R_USBHC_VBCTRL_VBUSENSEL_Msk            (0x2UL)        /*!< VBUSENSEL (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_VBCTRL_SIDDQREL_Pos             (2UL)          /*!< SIDDQREL (Bit 2)                                      */
+ #define R_USBHC_VBCTRL_SIDDQREL_Msk             (0x4UL)        /*!< SIDDQREL (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_VBCTRL_VGPUO_Pos                (4UL)          /*!< VGPUO (Bit 4)                                         */
+ #define R_USBHC_VBCTRL_VGPUO_Msk                (0x10UL)       /*!< VGPUO (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_VBCTRL_OCCLRIEN_Pos             (16UL)         /*!< OCCLRIEN (Bit 16)                                     */
+ #define R_USBHC_VBCTRL_OCCLRIEN_Msk             (0x10000UL)    /*!< OCCLRIEN (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_VBCTRL_OCISEL_Pos               (17UL)         /*!< OCISEL (Bit 17)                                       */
+ #define R_USBHC_VBCTRL_OCISEL_Msk               (0x20000UL)    /*!< OCISEL (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_VBCTRL_VBLVL_Pos                (20UL)         /*!< VBLVL (Bit 20)                                        */
+ #define R_USBHC_VBCTRL_VBLVL_Msk                (0xf00000UL)   /*!< VBLVL (Bitfield-Mask: 0x0f)                           */
+ #define R_USBHC_VBCTRL_VBSTA_Pos                (28UL)         /*!< VBSTA (Bit 28)                                        */
+ #define R_USBHC_VBCTRL_VBSTA_Msk                (0xf0000000UL) /*!< VBSTA (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  LINECTRL1  ======================================================= */
+ #define R_USBHC_LINECTRL1_IDMON_Pos             (0UL)          /*!< IDMON (Bit 0)                                         */
+ #define R_USBHC_LINECTRL1_IDMON_Msk             (0x1UL)        /*!< IDMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_LINECTRL1_DMMON_Pos             (2UL)          /*!< DMMON (Bit 2)                                         */
+ #define R_USBHC_LINECTRL1_DMMON_Msk             (0x4UL)        /*!< DMMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_LINECTRL1_DPMON_Pos             (3UL)          /*!< DPMON (Bit 3)                                         */
+ #define R_USBHC_LINECTRL1_DPMON_Msk             (0x8UL)        /*!< DPMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBHC_LINECTRL1_DM_RPD_Pos            (16UL)         /*!< DM_RPD (Bit 16)                                       */
+ #define R_USBHC_LINECTRL1_DM_RPD_Msk            (0x10000UL)    /*!< DM_RPD (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_LINECTRL1_DMRPD_EN_Pos          (17UL)         /*!< DMRPD_EN (Bit 17)                                     */
+ #define R_USBHC_LINECTRL1_DMRPD_EN_Msk          (0x20000UL)    /*!< DMRPD_EN (Bitfield-Mask: 0x01)                        */
+ #define R_USBHC_LINECTRL1_DP_RPD_Pos            (18UL)         /*!< DP_RPD (Bit 18)                                       */
+ #define R_USBHC_LINECTRL1_DP_RPD_Msk            (0x40000UL)    /*!< DP_RPD (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_LINECTRL1_DPRPD_EN_Pos          (19UL)         /*!< DPRPD_EN (Bit 19)                                     */
+ #define R_USBHC_LINECTRL1_DPRPD_EN_Msk          (0x80000UL)    /*!< DPRPD_EN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  PHYCTRL  ======================================================== */
+ #define R_USBHC_PHYCTRL_DRVVBUS_Pos             (4UL)          /*!< DRVVBUS (Bit 4)                                       */
+ #define R_USBHC_PHYCTRL_DRVVBUS_Msk             (0x10UL)       /*!< DRVVBUS (Bitfield-Mask: 0x01)                         */
+ #define R_USBHC_PHYCTRL_IDPULLUP0_Pos           (5UL)          /*!< IDPULLUP0 (Bit 5)                                     */
+ #define R_USBHC_PHYCTRL_IDPULLUP0_Msk           (0x20UL)       /*!< IDPULLUP0 (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_PHYCTRL_VBUSVALID_Pos           (18UL)         /*!< VBUSVALID (Bit 18)                                    */
+ #define R_USBHC_PHYCTRL_VBUSVALID_Msk           (0x40000UL)    /*!< VBUSVALID (Bitfield-Mask: 0x01)                       */
+ #define R_USBHC_PHYCTRL_IDDIG0_Pos              (19UL)         /*!< IDDIG0 (Bit 19)                                       */
+ #define R_USBHC_PHYCTRL_IDDIG0_Msk              (0x80000UL)    /*!< IDDIG0 (Bitfield-Mask: 0x01)                          */
+ #define R_USBHC_PHYCTRL_OTGSESSVLD_Pos          (20UL)         /*!< OTGSESSVLD (Bit 20)                                   */
+ #define R_USBHC_PHYCTRL_OTGSESSVLD_Msk          (0x100000UL)   /*!< OTGSESSVLD (Bitfield-Mask: 0x01)                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USBF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SYSCFG0  ======================================================== */
+ #define R_USBF_SYSCFG0_USBE_Pos            (0UL)          /*!< USBE (Bit 0)                                          */
+ #define R_USBF_SYSCFG0_USBE_Msk            (0x1UL)        /*!< USBE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_SYSCFG0_DPRPU_Pos           (4UL)          /*!< DPRPU (Bit 4)                                         */
+ #define R_USBF_SYSCFG0_DPRPU_Msk           (0x10UL)       /*!< DPRPU (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_SYSCFG0_DRPD_Pos            (5UL)          /*!< DRPD (Bit 5)                                          */
+ #define R_USBF_SYSCFG0_DRPD_Msk            (0x20UL)       /*!< DRPD (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_SYSCFG0_HSE_Pos             (7UL)          /*!< HSE (Bit 7)                                           */
+ #define R_USBF_SYSCFG0_HSE_Msk             (0x80UL)       /*!< HSE (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_SYSCFG0_CNEN_Pos            (8UL)          /*!< CNEN (Bit 8)                                          */
+ #define R_USBF_SYSCFG0_CNEN_Msk            (0x100UL)      /*!< CNEN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SYSCFG1  ======================================================== */
+ #define R_USBF_SYSCFG1_BWAIT_Pos           (0UL)          /*!< BWAIT (Bit 0)                                         */
+ #define R_USBF_SYSCFG1_BWAIT_Msk           (0x3fUL)       /*!< BWAIT (Bitfield-Mask: 0x3f)                           */
+ #define R_USBF_SYSCFG1_AWAIT_Pos           (8UL)          /*!< AWAIT (Bit 8)                                         */
+ #define R_USBF_SYSCFG1_AWAIT_Msk           (0x3f00UL)     /*!< AWAIT (Bitfield-Mask: 0x3f)                           */
+/* ========================================================  SYSSTS0  ======================================================== */
+ #define R_USBF_SYSSTS0_LNST_Pos            (0UL)          /*!< LNST (Bit 0)                                          */
+ #define R_USBF_SYSSTS0_LNST_Msk            (0x3UL)        /*!< LNST (Bitfield-Mask: 0x03)                            */
+/* =======================================================  DVSTCTR0  ======================================================== */
+ #define R_USBF_DVSTCTR0_RHST_Pos           (0UL)          /*!< RHST (Bit 0)                                          */
+ #define R_USBF_DVSTCTR0_RHST_Msk           (0x7UL)        /*!< RHST (Bitfield-Mask: 0x07)                            */
+ #define R_USBF_DVSTCTR0_WKUP_Pos           (8UL)          /*!< WKUP (Bit 8)                                          */
+ #define R_USBF_DVSTCTR0_WKUP_Msk           (0x100UL)      /*!< WKUP (Bitfield-Mask: 0x01)                            */
+/* =======================================================  TESTMODE  ======================================================== */
+ #define R_USBF_TESTMODE_UTST_Pos           (0UL)          /*!< UTST (Bit 0)                                          */
+ #define R_USBF_TESTMODE_UTST_Msk           (0xfUL)        /*!< UTST (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  CFIFO  ========================================================= */
+ #define R_USBF_CFIFO_FIFOPORT_Pos          (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_CFIFO_FIFOPORT_Msk          (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  CFIFOL  ========================================================= */
+/* ========================================================  CFIFOLL  ======================================================== */
+/* ========================================================  CFIFOH  ========================================================= */
+ #define R_USBF_CFIFOH_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_CFIFOH_FIFOPORT_Msk         (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  CFIFOHH  ======================================================== */
+ #define R_USBF_CFIFOHH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_CFIFOHH_FIFOPORT_Msk        (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
+/* ========================================================  D0FIFO  ========================================================= */
+ #define R_USBF_D0FIFO_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D0FIFO_FIFOPORT_Msk         (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  D0FIFOL  ======================================================== */
+/* =======================================================  D0FIFOLL  ======================================================== */
+/* ========================================================  D0FIFOH  ======================================================== */
+ #define R_USBF_D0FIFOH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D0FIFOH_FIFOPORT_Msk        (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  D0FIFOHH  ======================================================== */
+ #define R_USBF_D0FIFOHH_FIFOPORT_Pos       (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D0FIFOHH_FIFOPORT_Msk       (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
+/* ========================================================  D1FIFO  ========================================================= */
+ #define R_USBF_D1FIFO_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D1FIFO_FIFOPORT_Msk         (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  D1FIFOL  ======================================================== */
+/* =======================================================  D1FIFOLL  ======================================================== */
+/* ========================================================  D1FIFOH  ======================================================== */
+ #define R_USBF_D1FIFOH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D1FIFOH_FIFOPORT_Msk        (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  D1FIFOHH  ======================================================== */
+ #define R_USBF_D1FIFOHH_FIFOPORT_Pos       (0UL)          /*!< FIFOPORT (Bit 0)                                      */
+ #define R_USBF_D1FIFOHH_FIFOPORT_Msk       (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
+/* =======================================================  CFIFOSEL  ======================================================== */
+ #define R_USBF_CFIFOSEL_CURPIPE_Pos        (0UL)          /*!< CURPIPE (Bit 0)                                       */
+ #define R_USBF_CFIFOSEL_CURPIPE_Msk        (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+ #define R_USBF_CFIFOSEL_ISEL_Pos           (5UL)          /*!< ISEL (Bit 5)                                          */
+ #define R_USBF_CFIFOSEL_ISEL_Msk           (0x20UL)       /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CFIFOSEL_BIGEND_Pos         (8UL)          /*!< BIGEND (Bit 8)                                        */
+ #define R_USBF_CFIFOSEL_BIGEND_Msk         (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_CFIFOSEL_MBW_Pos            (10UL)         /*!< MBW (Bit 10)                                          */
+ #define R_USBF_CFIFOSEL_MBW_Msk            (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_CFIFOSEL_REW_Pos            (14UL)         /*!< REW (Bit 14)                                          */
+ #define R_USBF_CFIFOSEL_REW_Msk            (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_CFIFOSEL_RCNT_Pos           (15UL)         /*!< RCNT (Bit 15)                                         */
+ #define R_USBF_CFIFOSEL_RCNT_Msk           (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFIFOCTR  ======================================================== */
+ #define R_USBF_CFIFOCTR_DTLN_Pos           (0UL)          /*!< DTLN (Bit 0)                                          */
+ #define R_USBF_CFIFOCTR_DTLN_Msk           (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+ #define R_USBF_CFIFOCTR_FRDY_Pos           (13UL)         /*!< FRDY (Bit 13)                                         */
+ #define R_USBF_CFIFOCTR_FRDY_Msk           (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CFIFOCTR_BCLR_Pos           (14UL)         /*!< BCLR (Bit 14)                                         */
+ #define R_USBF_CFIFOCTR_BCLR_Msk           (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_CFIFOCTR_BVAL_Pos           (15UL)         /*!< BVAL (Bit 15)                                         */
+ #define R_USBF_CFIFOCTR_BVAL_Msk           (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
+/* =======================================================  D0FIFOSEL  ======================================================= */
+ #define R_USBF_D0FIFOSEL_CURPIPE_Pos       (0UL)          /*!< CURPIPE (Bit 0)                                       */
+ #define R_USBF_D0FIFOSEL_CURPIPE_Msk       (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+ #define R_USBF_D0FIFOSEL_BIGEND_Pos        (8UL)          /*!< BIGEND (Bit 8)                                        */
+ #define R_USBF_D0FIFOSEL_BIGEND_Msk        (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_D0FIFOSEL_MBW_Pos           (10UL)         /*!< MBW (Bit 10)                                          */
+ #define R_USBF_D0FIFOSEL_MBW_Msk           (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_D0FIFOSEL_DREQE_Pos         (12UL)         /*!< DREQE (Bit 12)                                        */
+ #define R_USBF_D0FIFOSEL_DREQE_Msk         (0x1000UL)     /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_D0FIFOSEL_DCLRM_Pos         (13UL)         /*!< DCLRM (Bit 13)                                        */
+ #define R_USBF_D0FIFOSEL_DCLRM_Msk         (0x2000UL)     /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_D0FIFOSEL_REW_Pos           (14UL)         /*!< REW (Bit 14)                                          */
+ #define R_USBF_D0FIFOSEL_REW_Msk           (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_D0FIFOSEL_RCNT_Pos          (15UL)         /*!< RCNT (Bit 15)                                         */
+ #define R_USBF_D0FIFOSEL_RCNT_Msk          (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  D1FIFOSEL  ======================================================= */
+ #define R_USBF_D1FIFOSEL_CURPIPE_Pos       (0UL)          /*!< CURPIPE (Bit 0)                                       */
+ #define R_USBF_D1FIFOSEL_CURPIPE_Msk       (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+ #define R_USBF_D1FIFOSEL_BIGEND_Pos        (8UL)          /*!< BIGEND (Bit 8)                                        */
+ #define R_USBF_D1FIFOSEL_BIGEND_Msk        (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_D1FIFOSEL_MBW_Pos           (10UL)         /*!< MBW (Bit 10)                                          */
+ #define R_USBF_D1FIFOSEL_MBW_Msk           (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_D1FIFOSEL_DREQE_Pos         (12UL)         /*!< DREQE (Bit 12)                                        */
+ #define R_USBF_D1FIFOSEL_DREQE_Msk         (0x1000UL)     /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_D1FIFOSEL_DCLRM_Pos         (13UL)         /*!< DCLRM (Bit 13)                                        */
+ #define R_USBF_D1FIFOSEL_DCLRM_Msk         (0x2000UL)     /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_D1FIFOSEL_REW_Pos           (14UL)         /*!< REW (Bit 14)                                          */
+ #define R_USBF_D1FIFOSEL_REW_Msk           (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_D1FIFOSEL_RCNT_Pos          (15UL)         /*!< RCNT (Bit 15)                                         */
+ #define R_USBF_D1FIFOSEL_RCNT_Msk          (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  D0FIFOCTR  ======================================================= */
+ #define R_USBF_D0FIFOCTR_DTLN_Pos          (0UL)          /*!< DTLN (Bit 0)                                          */
+ #define R_USBF_D0FIFOCTR_DTLN_Msk          (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+ #define R_USBF_D0FIFOCTR_FRDY_Pos          (13UL)         /*!< FRDY (Bit 13)                                         */
+ #define R_USBF_D0FIFOCTR_FRDY_Msk          (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_D0FIFOCTR_BCLR_Pos          (14UL)         /*!< BCLR (Bit 14)                                         */
+ #define R_USBF_D0FIFOCTR_BCLR_Msk          (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_D0FIFOCTR_BVAL_Pos          (15UL)         /*!< BVAL (Bit 15)                                         */
+ #define R_USBF_D0FIFOCTR_BVAL_Msk          (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
+/* =======================================================  D1FIFOCTR  ======================================================= */
+ #define R_USBF_D1FIFOCTR_DTLN_Pos          (0UL)          /*!< DTLN (Bit 0)                                          */
+ #define R_USBF_D1FIFOCTR_DTLN_Msk          (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+ #define R_USBF_D1FIFOCTR_FRDY_Pos          (13UL)         /*!< FRDY (Bit 13)                                         */
+ #define R_USBF_D1FIFOCTR_FRDY_Msk          (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_D1FIFOCTR_BCLR_Pos          (14UL)         /*!< BCLR (Bit 14)                                         */
+ #define R_USBF_D1FIFOCTR_BCLR_Msk          (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_D1FIFOCTR_BVAL_Pos          (15UL)         /*!< BVAL (Bit 15)                                         */
+ #define R_USBF_D1FIFOCTR_BVAL_Msk          (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
+/* ========================================================  INTENB0  ======================================================== */
+ #define R_USBF_INTENB0_BRDYE_Pos           (8UL)          /*!< BRDYE (Bit 8)                                         */
+ #define R_USBF_INTENB0_BRDYE_Msk           (0x100UL)      /*!< BRDYE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTENB0_NRDYE_Pos           (9UL)          /*!< NRDYE (Bit 9)                                         */
+ #define R_USBF_INTENB0_NRDYE_Msk           (0x200UL)      /*!< NRDYE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTENB0_BEMPE_Pos           (10UL)         /*!< BEMPE (Bit 10)                                        */
+ #define R_USBF_INTENB0_BEMPE_Msk           (0x400UL)      /*!< BEMPE (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTENB0_CTRE_Pos            (11UL)         /*!< CTRE (Bit 11)                                         */
+ #define R_USBF_INTENB0_CTRE_Msk            (0x800UL)      /*!< CTRE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTENB0_DVSE_Pos            (12UL)         /*!< DVSE (Bit 12)                                         */
+ #define R_USBF_INTENB0_DVSE_Msk            (0x1000UL)     /*!< DVSE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTENB0_SOFE_Pos            (13UL)         /*!< SOFE (Bit 13)                                         */
+ #define R_USBF_INTENB0_SOFE_Msk            (0x2000UL)     /*!< SOFE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTENB0_RSME_Pos            (14UL)         /*!< RSME (Bit 14)                                         */
+ #define R_USBF_INTENB0_RSME_Msk            (0x4000UL)     /*!< RSME (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTENB0_VBSE_Pos            (15UL)         /*!< VBSE (Bit 15)                                         */
+ #define R_USBF_INTENB0_VBSE_Msk            (0x8000UL)     /*!< VBSE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  INTENB1  ======================================================== */
+ #define R_USBF_INTENB1_PDDETINTE_Pos       (0UL)          /*!< PDDETINTE (Bit 0)                                     */
+ #define R_USBF_INTENB1_PDDETINTE_Msk       (0x1UL)        /*!< PDDETINTE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  BRDYENB  ======================================================== */
+ #define R_USBF_BRDYENB_PIPEBRDYE_Pos       (0UL)          /*!< PIPEBRDYE (Bit 0)                                     */
+ #define R_USBF_BRDYENB_PIPEBRDYE_Msk       (0x3ffUL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff)                      */
+/* ========================================================  NRDYENB  ======================================================== */
+ #define R_USBF_NRDYENB_PIPENRDYE_Pos       (0UL)          /*!< PIPENRDYE (Bit 0)                                     */
+ #define R_USBF_NRDYENB_PIPENRDYE_Msk       (0x3ffUL)      /*!< PIPENRDYE (Bitfield-Mask: 0x3ff)                      */
+/* ========================================================  BEMPENB  ======================================================== */
+ #define R_USBF_BEMPENB_PIPEBEMPE_Pos       (0UL)          /*!< PIPEBEMPE (Bit 0)                                     */
+ #define R_USBF_BEMPENB_PIPEBEMPE_Msk       (0x3ffUL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff)                      */
+/* ========================================================  SOFCFG  ========================================================= */
+ #define R_USBF_SOFCFG_EDGESTS_Pos          (4UL)          /*!< EDGESTS (Bit 4)                                       */
+ #define R_USBF_SOFCFG_EDGESTS_Msk          (0x10UL)       /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
+ #define R_USBF_SOFCFG_INTL_Pos             (5UL)          /*!< INTL (Bit 5)                                          */
+ #define R_USBF_SOFCFG_INTL_Msk             (0x20UL)       /*!< INTL (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_SOFCFG_BRDYM_Pos            (6UL)          /*!< BRDYM (Bit 6)                                         */
+ #define R_USBF_SOFCFG_BRDYM_Msk            (0x40UL)       /*!< BRDYM (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTSTS0  ======================================================== */
+ #define R_USBF_INTSTS0_CTSQ_Pos            (0UL)          /*!< CTSQ (Bit 0)                                          */
+ #define R_USBF_INTSTS0_CTSQ_Msk            (0x7UL)        /*!< CTSQ (Bitfield-Mask: 0x07)                            */
+ #define R_USBF_INTSTS0_VALID_Pos           (3UL)          /*!< VALID (Bit 3)                                         */
+ #define R_USBF_INTSTS0_VALID_Msk           (0x8UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTSTS0_DVSQ_Pos            (4UL)          /*!< DVSQ (Bit 4)                                          */
+ #define R_USBF_INTSTS0_DVSQ_Msk            (0x70UL)       /*!< DVSQ (Bitfield-Mask: 0x07)                            */
+ #define R_USBF_INTSTS0_VBSTS_Pos           (7UL)          /*!< VBSTS (Bit 7)                                         */
+ #define R_USBF_INTSTS0_VBSTS_Msk           (0x80UL)       /*!< VBSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_INTSTS0_BRDY_Pos            (8UL)          /*!< BRDY (Bit 8)                                          */
+ #define R_USBF_INTSTS0_BRDY_Msk            (0x100UL)      /*!< BRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_NRDY_Pos            (9UL)          /*!< NRDY (Bit 9)                                          */
+ #define R_USBF_INTSTS0_NRDY_Msk            (0x200UL)      /*!< NRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_BEMP_Pos            (10UL)         /*!< BEMP (Bit 10)                                         */
+ #define R_USBF_INTSTS0_BEMP_Msk            (0x400UL)      /*!< BEMP (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_CTRT_Pos            (11UL)         /*!< CTRT (Bit 11)                                         */
+ #define R_USBF_INTSTS0_CTRT_Msk            (0x800UL)      /*!< CTRT (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_DVST_Pos            (12UL)         /*!< DVST (Bit 12)                                         */
+ #define R_USBF_INTSTS0_DVST_Msk            (0x1000UL)     /*!< DVST (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_SOFR_Pos            (13UL)         /*!< SOFR (Bit 13)                                         */
+ #define R_USBF_INTSTS0_SOFR_Msk            (0x2000UL)     /*!< SOFR (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_RESM_Pos            (14UL)         /*!< RESM (Bit 14)                                         */
+ #define R_USBF_INTSTS0_RESM_Msk            (0x4000UL)     /*!< RESM (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_INTSTS0_VBINT_Pos           (15UL)         /*!< VBINT (Bit 15)                                        */
+ #define R_USBF_INTSTS0_VBINT_Msk           (0x8000UL)     /*!< VBINT (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTSTS1  ======================================================== */
+ #define R_USBF_INTSTS1_PDDETINT_Pos        (0UL)          /*!< PDDETINT (Bit 0)                                      */
+ #define R_USBF_INTSTS1_PDDETINT_Msk        (0x1UL)        /*!< PDDETINT (Bitfield-Mask: 0x01)                        */
+/* ========================================================  BRDYSTS  ======================================================== */
+ #define R_USBF_BRDYSTS_PIPEBRDY_Pos        (0UL)          /*!< PIPEBRDY (Bit 0)                                      */
+ #define R_USBF_BRDYSTS_PIPEBRDY_Msk        (0x3ffUL)      /*!< PIPEBRDY (Bitfield-Mask: 0x3ff)                       */
+/* ========================================================  NRDYSTS  ======================================================== */
+ #define R_USBF_NRDYSTS_PIPENRDY_Pos        (0UL)          /*!< PIPENRDY (Bit 0)                                      */
+ #define R_USBF_NRDYSTS_PIPENRDY_Msk        (0x3ffUL)      /*!< PIPENRDY (Bitfield-Mask: 0x3ff)                       */
+/* ========================================================  BEMPSTS  ======================================================== */
+ #define R_USBF_BEMPSTS_PIPEBEMP_Pos        (0UL)          /*!< PIPEBEMP (Bit 0)                                      */
+ #define R_USBF_BEMPSTS_PIPEBEMP_Msk        (0x3ffUL)      /*!< PIPEBEMP (Bitfield-Mask: 0x3ff)                       */
+/* ========================================================  FRMNUM  ========================================================= */
+ #define R_USBF_FRMNUM_FRNM_Pos             (0UL)          /*!< FRNM (Bit 0)                                          */
+ #define R_USBF_FRMNUM_FRNM_Msk             (0x7ffUL)      /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
+ #define R_USBF_FRMNUM_CRCE_Pos             (14UL)         /*!< CRCE (Bit 14)                                         */
+ #define R_USBF_FRMNUM_CRCE_Msk             (0x4000UL)     /*!< CRCE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_FRMNUM_OVRN_Pos             (15UL)         /*!< OVRN (Bit 15)                                         */
+ #define R_USBF_FRMNUM_OVRN_Msk             (0x8000UL)     /*!< OVRN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  UFRMNUM  ======================================================== */
+ #define R_USBF_UFRMNUM_UFRNM_Pos           (0UL)          /*!< UFRNM (Bit 0)                                         */
+ #define R_USBF_UFRMNUM_UFRNM_Msk           (0x7UL)        /*!< UFRNM (Bitfield-Mask: 0x07)                           */
+/* ========================================================  USBADDR  ======================================================== */
+ #define R_USBF_USBADDR_USBADDR_Pos         (0UL)          /*!< USBADDR (Bit 0)                                       */
+ #define R_USBF_USBADDR_USBADDR_Msk         (0x7fUL)       /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
+/* ========================================================  USBREQ  ========================================================= */
+ #define R_USBF_USBREQ_BMREQUESTTYPE_Pos    (0UL)          /*!< BMREQUESTTYPE (Bit 0)                                 */
+ #define R_USBF_USBREQ_BMREQUESTTYPE_Msk    (0xffUL)       /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
+ #define R_USBF_USBREQ_BREQUEST_Pos         (8UL)          /*!< BREQUEST (Bit 8)                                      */
+ #define R_USBF_USBREQ_BREQUEST_Msk         (0xff00UL)     /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
+/* ========================================================  USBVAL  ========================================================= */
+ #define R_USBF_USBVAL_WVALUE_Pos           (0UL)          /*!< WVALUE (Bit 0)                                        */
+ #define R_USBF_USBVAL_WVALUE_Msk           (0xffffUL)     /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBINDX  ======================================================== */
+ #define R_USBF_USBINDX_WINDEX_Pos          (0UL)          /*!< WINDEX (Bit 0)                                        */
+ #define R_USBF_USBINDX_WINDEX_Msk          (0xffffUL)     /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBLENG  ======================================================== */
+ #define R_USBF_USBLENG_WLENGTH_Pos         (0UL)          /*!< WLENGTH (Bit 0)                                       */
+ #define R_USBF_USBLENG_WLENGTH_Msk         (0xffffUL)     /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  DCPCFG  ========================================================= */
+ #define R_USBF_DCPCFG_SHTNAK_Pos           (7UL)          /*!< SHTNAK (Bit 7)                                        */
+ #define R_USBF_DCPCFG_SHTNAK_Msk           (0x80UL)       /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_DCPCFG_CNTMD_Pos            (8UL)          /*!< CNTMD (Bit 8)                                         */
+ #define R_USBF_DCPCFG_CNTMD_Msk            (0x100UL)      /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DCPMAXP  ======================================================== */
+ #define R_USBF_DCPMAXP_MXPS_Pos            (0UL)          /*!< MXPS (Bit 0)                                          */
+ #define R_USBF_DCPMAXP_MXPS_Msk            (0x7fUL)       /*!< MXPS (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  DCPCTR  ========================================================= */
+ #define R_USBF_DCPCTR_PID_Pos              (0UL)          /*!< PID (Bit 0)                                           */
+ #define R_USBF_DCPCTR_PID_Msk              (0x3UL)        /*!< PID (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_DCPCTR_CCPL_Pos             (2UL)          /*!< CCPL (Bit 2)                                          */
+ #define R_USBF_DCPCTR_CCPL_Msk             (0x4UL)        /*!< CCPL (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_DCPCTR_PBUSY_Pos            (5UL)          /*!< PBUSY (Bit 5)                                         */
+ #define R_USBF_DCPCTR_PBUSY_Msk            (0x20UL)       /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_DCPCTR_SQMON_Pos            (6UL)          /*!< SQMON (Bit 6)                                         */
+ #define R_USBF_DCPCTR_SQMON_Msk            (0x40UL)       /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_DCPCTR_SQSET_Pos            (7UL)          /*!< SQSET (Bit 7)                                         */
+ #define R_USBF_DCPCTR_SQSET_Msk            (0x80UL)       /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_DCPCTR_SQCLR_Pos            (8UL)          /*!< SQCLR (Bit 8)                                         */
+ #define R_USBF_DCPCTR_SQCLR_Msk            (0x100UL)      /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_DCPCTR_BSTS_Pos             (15UL)         /*!< BSTS (Bit 15)                                         */
+ #define R_USBF_DCPCTR_BSTS_Msk             (0x8000UL)     /*!< BSTS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PIPESEL  ======================================================== */
+ #define R_USBF_PIPESEL_PIPESEL_Pos         (0UL)          /*!< PIPESEL (Bit 0)                                       */
+ #define R_USBF_PIPESEL_PIPESEL_Msk         (0xfUL)        /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
+/* ========================================================  PIPECFG  ======================================================== */
+ #define R_USBF_PIPECFG_EPNUM_Pos           (0UL)          /*!< EPNUM (Bit 0)                                         */
+ #define R_USBF_PIPECFG_EPNUM_Msk           (0xfUL)        /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
+ #define R_USBF_PIPECFG_DIR_Pos             (4UL)          /*!< DIR (Bit 4)                                           */
+ #define R_USBF_PIPECFG_DIR_Msk             (0x10UL)       /*!< DIR (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_PIPECFG_SHTNAK_Pos          (7UL)          /*!< SHTNAK (Bit 7)                                        */
+ #define R_USBF_PIPECFG_SHTNAK_Msk          (0x80UL)       /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_PIPECFG_CNTMD_Pos           (8UL)          /*!< CNTMD (Bit 8)                                         */
+ #define R_USBF_PIPECFG_CNTMD_Msk           (0x100UL)      /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPECFG_DBLB_Pos            (9UL)          /*!< DBLB (Bit 9)                                          */
+ #define R_USBF_PIPECFG_DBLB_Msk            (0x200UL)      /*!< DBLB (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_PIPECFG_BFRE_Pos            (10UL)         /*!< BFRE (Bit 10)                                         */
+ #define R_USBF_PIPECFG_BFRE_Msk            (0x400UL)      /*!< BFRE (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_PIPECFG_TYPE_Pos            (14UL)         /*!< TYPE (Bit 14)                                         */
+ #define R_USBF_PIPECFG_TYPE_Msk            (0xc000UL)     /*!< TYPE (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PIPEBUF  ======================================================== */
+ #define R_USBF_PIPEBUF_BUFNMB_Pos          (0UL)          /*!< BUFNMB (Bit 0)                                        */
+ #define R_USBF_PIPEBUF_BUFNMB_Msk          (0xffUL)       /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
+ #define R_USBF_PIPEBUF_BUFSIZE_Pos         (10UL)         /*!< BUFSIZE (Bit 10)                                      */
+ #define R_USBF_PIPEBUF_BUFSIZE_Msk         (0x7c00UL)     /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  PIPEMAXP  ======================================================== */
+ #define R_USBF_PIPEMAXP_MXPS_Pos           (0UL)          /*!< MXPS (Bit 0)                                          */
+ #define R_USBF_PIPEMAXP_MXPS_Msk           (0x7ffUL)      /*!< MXPS (Bitfield-Mask: 0x7ff)                           */
+/* =======================================================  PIPEPERI  ======================================================== */
+ #define R_USBF_PIPEPERI_IITV_Pos           (0UL)          /*!< IITV (Bit 0)                                          */
+ #define R_USBF_PIPEPERI_IITV_Msk           (0x7UL)        /*!< IITV (Bitfield-Mask: 0x07)                            */
+ #define R_USBF_PIPEPERI_IFIS_Pos           (12UL)         /*!< IFIS (Bit 12)                                         */
+ #define R_USBF_PIPEPERI_IFIS_Msk           (0x1000UL)     /*!< IFIS (Bitfield-Mask: 0x01)                            */
+/* =======================================================  PIPE_CTR  ======================================================== */
+ #define R_USBF_PIPE_CTR_PID_Pos            (0UL)          /*!< PID (Bit 0)                                           */
+ #define R_USBF_PIPE_CTR_PID_Msk            (0x3UL)        /*!< PID (Bitfield-Mask: 0x03)                             */
+ #define R_USBF_PIPE_CTR_PBUSY_Pos          (5UL)          /*!< PBUSY (Bit 5)                                         */
+ #define R_USBF_PIPE_CTR_PBUSY_Msk          (0x20UL)       /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_SQMON_Pos          (6UL)          /*!< SQMON (Bit 6)                                         */
+ #define R_USBF_PIPE_CTR_SQMON_Msk          (0x40UL)       /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_SQSET_Pos          (7UL)          /*!< SQSET (Bit 7)                                         */
+ #define R_USBF_PIPE_CTR_SQSET_Msk          (0x80UL)       /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_SQCLR_Pos          (8UL)          /*!< SQCLR (Bit 8)                                         */
+ #define R_USBF_PIPE_CTR_SQCLR_Msk          (0x100UL)      /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_ACLRM_Pos          (9UL)          /*!< ACLRM (Bit 9)                                         */
+ #define R_USBF_PIPE_CTR_ACLRM_Msk          (0x200UL)      /*!< ACLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USBF_PIPE_CTR_ATREPM_Pos         (10UL)         /*!< ATREPM (Bit 10)                                       */
+ #define R_USBF_PIPE_CTR_ATREPM_Msk         (0x400UL)      /*!< ATREPM (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_PIPE_CTR_INBUFM_Pos         (14UL)         /*!< INBUFM (Bit 14)                                       */
+ #define R_USBF_PIPE_CTR_INBUFM_Msk         (0x4000UL)     /*!< INBUFM (Bitfield-Mask: 0x01)                          */
+ #define R_USBF_PIPE_CTR_BSTS_Pos           (15UL)         /*!< BSTS (Bit 15)                                         */
+ #define R_USBF_PIPE_CTR_BSTS_Msk           (0x8000UL)     /*!< BSTS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  LPSTS  ========================================================= */
+ #define R_USBF_LPSTS_SUSPM_Pos             (14UL)         /*!< SUSPM (Bit 14)                                        */
+ #define R_USBF_LPSTS_SUSPM_Msk             (0x4000UL)     /*!< SUSPM (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DCTRL  ========================================================= */
+ #define R_USBF_DCTRL_PR_Pos                (0UL)          /*!< PR (Bit 0)                                            */
+ #define R_USBF_DCTRL_PR_Msk                (0x1UL)        /*!< PR (Bitfield-Mask: 0x01)                              */
+ #define R_USBF_DCTRL_LDPR_Pos              (16UL)         /*!< LDPR (Bit 16)                                         */
+ #define R_USBF_DCTRL_LDPR_Msk              (0xf0000UL)    /*!< LDPR (Bitfield-Mask: 0x0f)                            */
+ #define R_USBF_DCTRL_LWPR_Pos              (24UL)         /*!< LWPR (Bit 24)                                         */
+ #define R_USBF_DCTRL_LWPR_Msk              (0xf000000UL)  /*!< LWPR (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  DSCITVL  ======================================================== */
+ #define R_USBF_DSCITVL_DITVL_Pos           (8UL)          /*!< DITVL (Bit 8)                                         */
+ #define R_USBF_DSCITVL_DITVL_Msk           (0xff00UL)     /*!< DITVL (Bitfield-Mask: 0xff)                           */
+/* =======================================================  DSTAT_EN  ======================================================== */
+ #define R_USBF_DSTAT_EN_EN0_Pos            (0UL)          /*!< EN0 (Bit 0)                                           */
+ #define R_USBF_DSTAT_EN_EN0_Msk            (0x1UL)        /*!< EN0 (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_DSTAT_EN_EN1_Pos            (1UL)          /*!< EN1 (Bit 1)                                           */
+ #define R_USBF_DSTAT_EN_EN1_Msk            (0x2UL)        /*!< EN1 (Bitfield-Mask: 0x01)                             */
+/* =======================================================  DSTAT_ER  ======================================================== */
+ #define R_USBF_DSTAT_ER_ER0_Pos            (0UL)          /*!< ER0 (Bit 0)                                           */
+ #define R_USBF_DSTAT_ER_ER0_Msk            (0x1UL)        /*!< ER0 (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_DSTAT_ER_ER1_Pos            (1UL)          /*!< ER1 (Bit 1)                                           */
+ #define R_USBF_DSTAT_ER_ER1_Msk            (0x2UL)        /*!< ER1 (Bitfield-Mask: 0x01)                             */
+/* =======================================================  DSTAT_END  ======================================================= */
+ #define R_USBF_DSTAT_END_END0_Pos          (0UL)          /*!< END0 (Bit 0)                                          */
+ #define R_USBF_DSTAT_END_END0_Msk          (0x1UL)        /*!< END0 (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_DSTAT_END_END1_Pos          (1UL)          /*!< END1 (Bit 1)                                          */
+ #define R_USBF_DSTAT_END_END1_Msk          (0x2UL)        /*!< END1 (Bitfield-Mask: 0x01)                            */
+/* =======================================================  DSTAT_TC  ======================================================== */
+ #define R_USBF_DSTAT_TC_TC0_Pos            (0UL)          /*!< TC0 (Bit 0)                                           */
+ #define R_USBF_DSTAT_TC_TC0_Msk            (0x1UL)        /*!< TC0 (Bitfield-Mask: 0x01)                             */
+ #define R_USBF_DSTAT_TC_TC1_Pos            (1UL)          /*!< TC1 (Bit 1)                                           */
+ #define R_USBF_DSTAT_TC_TC1_Msk            (0x2UL)        /*!< TC1 (Bitfield-Mask: 0x01)                             */
+/* =======================================================  DSTAT_SUS  ======================================================= */
+ #define R_USBF_DSTAT_SUS_SUS0_Pos          (0UL)          /*!< SUS0 (Bit 0)                                          */
+ #define R_USBF_DSTAT_SUS_SUS0_Msk          (0x1UL)        /*!< SUS0 (Bitfield-Mask: 0x01)                            */
+ #define R_USBF_DSTAT_SUS_SUS1_Pos          (1UL)          /*!< SUS1 (Bit 1)                                          */
+ #define R_USBF_DSTAT_SUS_SUS1_Msk          (0x2UL)        /*!< SUS1 (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SDHI0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SD_CMD  ========================================================= */
+ #define R_SDHI0_SD_CMD_CF45CF40_Pos                    (0UL)          /*!< CF45CF40 (Bit 0)                                      */
+ #define R_SDHI0_SD_CMD_CF45CF40_Msk                    (0x3fUL)       /*!< CF45CF40 (Bitfield-Mask: 0x3f)                        */
+ #define R_SDHI0_SD_CMD_C1C0_Pos                        (6UL)          /*!< C1C0 (Bit 6)                                          */
+ #define R_SDHI0_SD_CMD_C1C0_Msk                        (0xc0UL)       /*!< C1C0 (Bitfield-Mask: 0x03)                            */
+ #define R_SDHI0_SD_CMD_MD2MD0_Pos                      (8UL)          /*!< MD2MD0 (Bit 8)                                        */
+ #define R_SDHI0_SD_CMD_MD2MD0_Msk                      (0x700UL)      /*!< MD2MD0 (Bitfield-Mask: 0x07)                          */
+ #define R_SDHI0_SD_CMD_MD3_Pos                         (11UL)         /*!< MD3 (Bit 11)                                          */
+ #define R_SDHI0_SD_CMD_MD3_Msk                         (0x800UL)      /*!< MD3 (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_CMD_MD4_Pos                         (12UL)         /*!< MD4 (Bit 12)                                          */
+ #define R_SDHI0_SD_CMD_MD4_Msk                         (0x1000UL)     /*!< MD4 (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_CMD_MD5_Pos                         (13UL)         /*!< MD5 (Bit 13)                                          */
+ #define R_SDHI0_SD_CMD_MD5_Msk                         (0x2000UL)     /*!< MD5 (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_CMD_MD7MD6_Pos                      (14UL)         /*!< MD7MD6 (Bit 14)                                       */
+ #define R_SDHI0_SD_CMD_MD7MD6_Msk                      (0xc000UL)     /*!< MD7MD6 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  SD_ARG  ========================================================= */
+/* ========================================================  SD_ARG1  ======================================================== */
+/* ========================================================  SD_STOP  ======================================================== */
+ #define R_SDHI0_SD_STOP_STP_Pos                        (0UL)          /*!< STP (Bit 0)                                           */
+ #define R_SDHI0_SD_STOP_STP_Msk                        (0x1UL)        /*!< STP (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_STOP_SEC_Pos                        (8UL)          /*!< SEC (Bit 8)                                           */
+ #define R_SDHI0_SD_STOP_SEC_Msk                        (0x100UL)      /*!< SEC (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_STOP_HPICMD_Pos                     (16UL)         /*!< HPICMD (Bit 16)                                       */
+ #define R_SDHI0_SD_STOP_HPICMD_Msk                     (0x10000UL)    /*!< HPICMD (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_STOP_HPIMODE_Pos                    (17UL)         /*!< HPIMODE (Bit 17)                                      */
+ #define R_SDHI0_SD_STOP_HPIMODE_Msk                    (0x20000UL)    /*!< HPIMODE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  SD_SECCNT  ======================================================= */
+ #define R_SDHI0_SD_SECCNT_CNT31CNT0_Pos                (0UL)          /*!< CNT31CNT0 (Bit 0)                                     */
+ #define R_SDHI0_SD_SECCNT_CNT31CNT0_Msk                (0xffffffffUL) /*!< CNT31CNT0 (Bitfield-Mask: 0xffffffff)                 */
+/* =======================================================  SD_RSP10L  ======================================================= */
+ #define R_SDHI0_SD_RSP10L_R39R8_Pos                    (0UL)          /*!< R39R8 (Bit 0)                                         */
+ #define R_SDHI0_SD_RSP10L_R39R8_Msk                    (0xffffffffUL) /*!< R39R8 (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  SD_RSP1  ======================================================== */
+ #define R_SDHI0_SD_RSP1_R39R24_Pos                     (0UL)          /*!< R39R24 (Bit 0)                                        */
+ #define R_SDHI0_SD_RSP1_R39R24_Msk                     (0xffffUL)     /*!< R39R24 (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  SD_RSP10H  ======================================================= */
+ #define R_SDHI0_SD_RSP10H_R71R40_Pos                   (0UL)          /*!< R71R40 (Bit 0)                                        */
+ #define R_SDHI0_SD_RSP10H_R71R40_Msk                   (0xffffffffUL) /*!< R71R40 (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  SD_RSP32  ======================================================== */
+ #define R_SDHI0_SD_RSP32_R71R40_Pos                    (0UL)          /*!< R71R40 (Bit 0)                                        */
+ #define R_SDHI0_SD_RSP32_R71R40_Msk                    (0xffffffffUL) /*!< R71R40 (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  SD_RSP3  ======================================================== */
+ #define R_SDHI0_SD_RSP3_R71R56_Pos                     (0UL)          /*!< R71R56 (Bit 0)                                        */
+ #define R_SDHI0_SD_RSP3_R71R56_Msk                     (0xffffUL)     /*!< R71R56 (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  SD_RSP54L  ======================================================= */
+ #define R_SDHI0_SD_RSP54L_R103R72_Pos                  (0UL)          /*!< R103R72 (Bit 0)                                       */
+ #define R_SDHI0_SD_RSP54L_R103R72_Msk                  (0xffffffffUL) /*!< R103R72 (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  SD_RSP5  ======================================================== */
+ #define R_SDHI0_SD_RSP5_R103R88_Pos                    (0UL)          /*!< R103R88 (Bit 0)                                       */
+ #define R_SDHI0_SD_RSP5_R103R88_Msk                    (0xffffUL)     /*!< R103R88 (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  SD_RSP54H  ======================================================= */
+ #define R_SDHI0_SD_RSP54H_R127R104_Pos                 (0UL)          /*!< R127R104 (Bit 0)                                      */
+ #define R_SDHI0_SD_RSP54H_R127R104_Msk                 (0xffffffUL)   /*!< R127R104 (Bitfield-Mask: 0xffffff)                    */
+/* =======================================================  SD_RSP76  ======================================================== */
+ #define R_SDHI0_SD_RSP76_R127R104_Pos                  (0UL)          /*!< R127R104 (Bit 0)                                      */
+ #define R_SDHI0_SD_RSP76_R127R104_Msk                  (0xffffffUL)   /*!< R127R104 (Bitfield-Mask: 0xffffff)                    */
+/* ========================================================  SD_RSP7  ======================================================== */
+ #define R_SDHI0_SD_RSP7_R127R120_Pos                   (0UL)          /*!< R127R120 (Bit 0)                                      */
+ #define R_SDHI0_SD_RSP7_R127R120_Msk                   (0xffUL)       /*!< R127R120 (Bitfield-Mask: 0xff)                        */
+/* =======================================================  SD_INFO1  ======================================================== */
+ #define R_SDHI0_SD_INFO1_INFO0_Pos                     (0UL)          /*!< INFO0 (Bit 0)                                         */
+ #define R_SDHI0_SD_INFO1_INFO0_Msk                     (0x1UL)        /*!< INFO0 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_INFO2_Pos                     (2UL)          /*!< INFO2 (Bit 2)                                         */
+ #define R_SDHI0_SD_INFO1_INFO2_Msk                     (0x4UL)        /*!< INFO2 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_INFO3_Pos                     (3UL)          /*!< INFO3 (Bit 3)                                         */
+ #define R_SDHI0_SD_INFO1_INFO3_Msk                     (0x8UL)        /*!< INFO3 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_INFO4_Pos                     (4UL)          /*!< INFO4 (Bit 4)                                         */
+ #define R_SDHI0_SD_INFO1_INFO4_Msk                     (0x10UL)       /*!< INFO4 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_INFO5_Pos                     (5UL)          /*!< INFO5 (Bit 5)                                         */
+ #define R_SDHI0_SD_INFO1_INFO5_Msk                     (0x20UL)       /*!< INFO5 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_INFO7_Pos                     (7UL)          /*!< INFO7 (Bit 7)                                         */
+ #define R_SDHI0_SD_INFO1_INFO7_Msk                     (0x80UL)       /*!< INFO7 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_INFO8_Pos                     (8UL)          /*!< INFO8 (Bit 8)                                         */
+ #define R_SDHI0_SD_INFO1_INFO8_Msk                     (0x100UL)      /*!< INFO8 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_INFO9_Pos                     (9UL)          /*!< INFO9 (Bit 9)                                         */
+ #define R_SDHI0_SD_INFO1_INFO9_Msk                     (0x200UL)      /*!< INFO9 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_INFO10_Pos                    (10UL)         /*!< INFO10 (Bit 10)                                       */
+ #define R_SDHI0_SD_INFO1_INFO10_Msk                    (0x400UL)      /*!< INFO10 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_HPIRES_Pos                    (16UL)         /*!< HPIRES (Bit 16)                                       */
+ #define R_SDHI0_SD_INFO1_HPIRES_Msk                    (0x10000UL)    /*!< HPIRES (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SD_INFO2  ======================================================== */
+ #define R_SDHI0_SD_INFO2_ERR0_Pos                      (0UL)          /*!< ERR0 (Bit 0)                                          */
+ #define R_SDHI0_SD_INFO2_ERR0_Msk                      (0x1UL)        /*!< ERR0 (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_ERR1_Pos                      (1UL)          /*!< ERR1 (Bit 1)                                          */
+ #define R_SDHI0_SD_INFO2_ERR1_Msk                      (0x2UL)        /*!< ERR1 (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_ERR2_Pos                      (2UL)          /*!< ERR2 (Bit 2)                                          */
+ #define R_SDHI0_SD_INFO2_ERR2_Msk                      (0x4UL)        /*!< ERR2 (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_ERR3_Pos                      (3UL)          /*!< ERR3 (Bit 3)                                          */
+ #define R_SDHI0_SD_INFO2_ERR3_Msk                      (0x8UL)        /*!< ERR3 (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_ERR4_Pos                      (4UL)          /*!< ERR4 (Bit 4)                                          */
+ #define R_SDHI0_SD_INFO2_ERR4_Msk                      (0x10UL)       /*!< ERR4 (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_ERR5_Pos                      (5UL)          /*!< ERR5 (Bit 5)                                          */
+ #define R_SDHI0_SD_INFO2_ERR5_Msk                      (0x20UL)       /*!< ERR5 (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_ERR6_Pos                      (6UL)          /*!< ERR6 (Bit 6)                                          */
+ #define R_SDHI0_SD_INFO2_ERR6_Msk                      (0x40UL)       /*!< ERR6 (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_DAT0_Pos                      (7UL)          /*!< DAT0 (Bit 7)                                          */
+ #define R_SDHI0_SD_INFO2_DAT0_Msk                      (0x80UL)       /*!< DAT0 (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_BRE_Pos                       (8UL)          /*!< BRE (Bit 8)                                           */
+ #define R_SDHI0_SD_INFO2_BRE_Msk                       (0x100UL)      /*!< BRE (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_INFO2_BWE_Pos                       (9UL)          /*!< BWE (Bit 9)                                           */
+ #define R_SDHI0_SD_INFO2_BWE_Msk                       (0x200UL)      /*!< BWE (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_INFO2_SCLKDIVEN_Pos                 (13UL)         /*!< SCLKDIVEN (Bit 13)                                    */
+ #define R_SDHI0_SD_INFO2_SCLKDIVEN_Msk                 (0x2000UL)     /*!< SCLKDIVEN (Bitfield-Mask: 0x01)                       */
+ #define R_SDHI0_SD_INFO2_CBSY_Pos                      (14UL)         /*!< CBSY (Bit 14)                                         */
+ #define R_SDHI0_SD_INFO2_CBSY_Msk                      (0x4000UL)     /*!< CBSY (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_ILA_Pos                       (15UL)         /*!< ILA (Bit 15)                                          */
+ #define R_SDHI0_SD_INFO2_ILA_Msk                       (0x8000UL)     /*!< ILA (Bitfield-Mask: 0x01)                             */
+/* =====================================================  SD_INFO1_MASK  ===================================================== */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK0_Pos               (0UL)          /*!< IMASK0 (Bit 0)                                        */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK0_Msk               (0x1UL)        /*!< IMASK0 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK2_Pos               (2UL)          /*!< IMASK2 (Bit 2)                                        */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK2_Msk               (0x4UL)        /*!< IMASK2 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK3_Pos               (3UL)          /*!< IMASK3 (Bit 3)                                        */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK3_Msk               (0x8UL)        /*!< IMASK3 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK4_Pos               (4UL)          /*!< IMASK4 (Bit 4)                                        */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK4_Msk               (0x10UL)       /*!< IMASK4 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK8_Pos               (8UL)          /*!< IMASK8 (Bit 8)                                        */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK8_Msk               (0x100UL)      /*!< IMASK8 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK9_Pos               (9UL)          /*!< IMASK9 (Bit 9)                                        */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK9_Msk               (0x200UL)      /*!< IMASK9 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK16_Pos              (16UL)         /*!< IMASK16 (Bit 16)                                      */
+ #define R_SDHI0_SD_INFO1_MASK_IMASK16_Msk              (0x10000UL)    /*!< IMASK16 (Bitfield-Mask: 0x01)                         */
+/* =====================================================  SD_INFO2_MASK  ===================================================== */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK0_Pos               (0UL)          /*!< EMASK0 (Bit 0)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK0_Msk               (0x1UL)        /*!< EMASK0 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK1_Pos               (1UL)          /*!< EMASK1 (Bit 1)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK1_Msk               (0x2UL)        /*!< EMASK1 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK2_Pos               (2UL)          /*!< EMASK2 (Bit 2)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK2_Msk               (0x4UL)        /*!< EMASK2 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK3_Pos               (3UL)          /*!< EMASK3 (Bit 3)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK3_Msk               (0x8UL)        /*!< EMASK3 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK4_Pos               (4UL)          /*!< EMASK4 (Bit 4)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK4_Msk               (0x10UL)       /*!< EMASK4 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK5_Pos               (5UL)          /*!< EMASK5 (Bit 5)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK5_Msk               (0x20UL)       /*!< EMASK5 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK6_Pos               (6UL)          /*!< EMASK6 (Bit 6)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_EMASK6_Msk               (0x40UL)       /*!< EMASK6 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_BMASK0_Pos               (8UL)          /*!< BMASK0 (Bit 8)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_BMASK0_Msk               (0x100UL)      /*!< BMASK0 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_BMASK1_Pos               (9UL)          /*!< BMASK1 (Bit 9)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_BMASK1_Msk               (0x200UL)      /*!< BMASK1 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_IMASK_Pos                (15UL)         /*!< IMASK (Bit 15)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_IMASK_Msk                (0x8000UL)     /*!< IMASK (Bitfield-Mask: 0x01)                           */
+/* ======================================================  SD_CLK_CTRL  ====================================================== */
+ #define R_SDHI0_SD_CLK_CTRL_DIV7DIV0_Pos               (0UL)          /*!< DIV7DIV0 (Bit 0)                                      */
+ #define R_SDHI0_SD_CLK_CTRL_DIV7DIV0_Msk               (0xffUL)       /*!< DIV7DIV0 (Bitfield-Mask: 0xff)                        */
+ #define R_SDHI0_SD_CLK_CTRL_SCLKEN_Pos                 (8UL)          /*!< SCLKEN (Bit 8)                                        */
+ #define R_SDHI0_SD_CLK_CTRL_SCLKEN_Msk                 (0x100UL)      /*!< SCLKEN (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_CLK_CTRL_SDCLKOFFEN_Pos             (9UL)          /*!< SDCLKOFFEN (Bit 9)                                    */
+ #define R_SDHI0_SD_CLK_CTRL_SDCLKOFFEN_Msk             (0x200UL)      /*!< SDCLKOFFEN (Bitfield-Mask: 0x01)                      */
+/* ========================================================  SD_SIZE  ======================================================== */
+ #define R_SDHI0_SD_SIZE_LEN9LEN0_Pos                   (0UL)          /*!< LEN9LEN0 (Bit 0)                                      */
+ #define R_SDHI0_SD_SIZE_LEN9LEN0_Msk                   (0x3ffUL)      /*!< LEN9LEN0 (Bitfield-Mask: 0x3ff)                       */
+/* =======================================================  SD_OPTION  ======================================================= */
+ #define R_SDHI0_SD_OPTION_CTOP24CTOP21_Pos             (0UL)          /*!< CTOP24CTOP21 (Bit 0)                                  */
+ #define R_SDHI0_SD_OPTION_CTOP24CTOP21_Msk             (0xfUL)        /*!< CTOP24CTOP21 (Bitfield-Mask: 0x0f)                    */
+ #define R_SDHI0_SD_OPTION_TOP27TOP24_Pos               (4UL)          /*!< TOP27TOP24 (Bit 4)                                    */
+ #define R_SDHI0_SD_OPTION_TOP27TOP24_Msk               (0xf0UL)       /*!< TOP27TOP24 (Bitfield-Mask: 0x0f)                      */
+ #define R_SDHI0_SD_OPTION_TOUTMASK_Pos                 (8UL)          /*!< TOUTMASK (Bit 8)                                      */
+ #define R_SDHI0_SD_OPTION_TOUTMASK_Msk                 (0x100UL)      /*!< TOUTMASK (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SD_OPTION_EXTOP_Pos                    (9UL)          /*!< EXTOP (Bit 9)                                         */
+ #define R_SDHI0_SD_OPTION_EXTOP_Msk                    (0x200UL)      /*!< EXTOP (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_OPTION_WIDTH8_Pos                   (13UL)         /*!< WIDTH8 (Bit 13)                                       */
+ #define R_SDHI0_SD_OPTION_WIDTH8_Msk                   (0x2000UL)     /*!< WIDTH8 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_OPTION_WIDTH_Pos                    (15UL)         /*!< WIDTH (Bit 15)                                        */
+ #define R_SDHI0_SD_OPTION_WIDTH_Msk                    (0x8000UL)     /*!< WIDTH (Bitfield-Mask: 0x01)                           */
+/* ======================================================  SD_ERR_STS1  ====================================================== */
+ #define R_SDHI0_SD_ERR_STS1_E0_Pos                     (0UL)          /*!< E0 (Bit 0)                                            */
+ #define R_SDHI0_SD_ERR_STS1_E0_Msk                     (0x1UL)        /*!< E0 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS1_E1_Pos                     (1UL)          /*!< E1 (Bit 1)                                            */
+ #define R_SDHI0_SD_ERR_STS1_E1_Msk                     (0x2UL)        /*!< E1 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS1_E2_Pos                     (2UL)          /*!< E2 (Bit 2)                                            */
+ #define R_SDHI0_SD_ERR_STS1_E2_Msk                     (0x4UL)        /*!< E2 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS1_E3_Pos                     (3UL)          /*!< E3 (Bit 3)                                            */
+ #define R_SDHI0_SD_ERR_STS1_E3_Msk                     (0x8UL)        /*!< E3 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS1_E4_Pos                     (4UL)          /*!< E4 (Bit 4)                                            */
+ #define R_SDHI0_SD_ERR_STS1_E4_Msk                     (0x10UL)       /*!< E4 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS1_E5_Pos                     (5UL)          /*!< E5 (Bit 5)                                            */
+ #define R_SDHI0_SD_ERR_STS1_E5_Msk                     (0x20UL)       /*!< E5 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS1_E8_Pos                     (8UL)          /*!< E8 (Bit 8)                                            */
+ #define R_SDHI0_SD_ERR_STS1_E8_Msk                     (0x100UL)      /*!< E8 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS1_E9_Pos                     (9UL)          /*!< E9 (Bit 9)                                            */
+ #define R_SDHI0_SD_ERR_STS1_E9_Msk                     (0x200UL)      /*!< E9 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS1_E10_Pos                    (10UL)         /*!< E10 (Bit 10)                                          */
+ #define R_SDHI0_SD_ERR_STS1_E10_Msk                    (0x400UL)      /*!< E10 (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_ERR_STS1_E11_Pos                    (11UL)         /*!< E11 (Bit 11)                                          */
+ #define R_SDHI0_SD_ERR_STS1_E11_Msk                    (0x800UL)      /*!< E11 (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_ERR_STS1_E14E12_Pos                 (12UL)         /*!< E14E12 (Bit 12)                                       */
+ #define R_SDHI0_SD_ERR_STS1_E14E12_Msk                 (0x7000UL)     /*!< E14E12 (Bitfield-Mask: 0x07)                          */
+/* ======================================================  SD_ERR_STS2  ====================================================== */
+ #define R_SDHI0_SD_ERR_STS2_E0_Pos                     (0UL)          /*!< E0 (Bit 0)                                            */
+ #define R_SDHI0_SD_ERR_STS2_E0_Msk                     (0x1UL)        /*!< E0 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS2_E1_Pos                     (1UL)          /*!< E1 (Bit 1)                                            */
+ #define R_SDHI0_SD_ERR_STS2_E1_Msk                     (0x2UL)        /*!< E1 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS2_E2_Pos                     (2UL)          /*!< E2 (Bit 2)                                            */
+ #define R_SDHI0_SD_ERR_STS2_E2_Msk                     (0x4UL)        /*!< E2 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS2_E3_Pos                     (3UL)          /*!< E3 (Bit 3)                                            */
+ #define R_SDHI0_SD_ERR_STS2_E3_Msk                     (0x8UL)        /*!< E3 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS2_E4_Pos                     (4UL)          /*!< E4 (Bit 4)                                            */
+ #define R_SDHI0_SD_ERR_STS2_E4_Msk                     (0x10UL)       /*!< E4 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS2_E5_Pos                     (5UL)          /*!< E5 (Bit 5)                                            */
+ #define R_SDHI0_SD_ERR_STS2_E5_Msk                     (0x20UL)       /*!< E5 (Bitfield-Mask: 0x01)                              */
+ #define R_SDHI0_SD_ERR_STS2_E6_Pos                     (6UL)          /*!< E6 (Bit 6)                                            */
+ #define R_SDHI0_SD_ERR_STS2_E6_Msk                     (0x40UL)       /*!< E6 (Bitfield-Mask: 0x01)                              */
+/* =======================================================  SD_BUF0H  ======================================================== */
+/* =======================================================  SD_BUF0L  ======================================================== */
+/* =======================================================  SDIO_MODE  ======================================================= */
+ #define R_SDHI0_SDIO_MODE_IOMOD_Pos                    (0UL)          /*!< IOMOD (Bit 0)                                         */
+ #define R_SDHI0_SDIO_MODE_IOMOD_Msk                    (0x1UL)        /*!< IOMOD (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SDIO_MODE_RWREQ_Pos                    (2UL)          /*!< RWREQ (Bit 2)                                         */
+ #define R_SDHI0_SDIO_MODE_RWREQ_Msk                    (0x4UL)        /*!< RWREQ (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SDIO_MODE_IOABT_Pos                    (8UL)          /*!< IOABT (Bit 8)                                         */
+ #define R_SDHI0_SDIO_MODE_IOABT_Msk                    (0x100UL)      /*!< IOABT (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SDIO_MODE_C52PUB_Pos                   (9UL)          /*!< C52PUB (Bit 9)                                        */
+ #define R_SDHI0_SDIO_MODE_C52PUB_Msk                   (0x200UL)      /*!< C52PUB (Bitfield-Mask: 0x01)                          */
+/* ======================================================  SDIO_INFO1  ======================================================= */
+ #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos                   (0UL)          /*!< IOIRQ (Bit 0)                                         */
+ #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk                   (0x1UL)        /*!< IOIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos                 (14UL)         /*!< EXPUB52 (Bit 14)                                      */
+ #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk                 (0x4000UL)     /*!< EXPUB52 (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SDIO_INFO1_EXWT_Pos                    (15UL)         /*!< EXWT (Bit 15)                                         */
+ #define R_SDHI0_SDIO_INFO1_EXWT_Msk                    (0x8000UL)     /*!< EXWT (Bitfield-Mask: 0x01)                            */
+/* ====================================================  SDIO_INFO1_MASK  ==================================================== */
+ #define R_SDHI0_SDIO_INFO1_MASK_IOMSK_Pos              (0UL)          /*!< IOMSK (Bit 0)                                         */
+ #define R_SDHI0_SDIO_INFO1_MASK_IOMSK_Msk              (0x1UL)        /*!< IOMSK (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SDIO_INFO1_MASK_MEXPUB52_Pos           (14UL)         /*!< MEXPUB52 (Bit 14)                                     */
+ #define R_SDHI0_SDIO_INFO1_MASK_MEXPUB52_Msk           (0x4000UL)     /*!< MEXPUB52 (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SDIO_INFO1_MASK_MEXWT_Pos              (15UL)         /*!< MEXWT (Bit 15)                                        */
+ #define R_SDHI0_SDIO_INFO1_MASK_MEXWT_Msk              (0x8000UL)     /*!< MEXWT (Bitfield-Mask: 0x01)                           */
+/* ======================================================  CC_EXT_MODE  ====================================================== */
+ #define R_SDHI0_CC_EXT_MODE_DMASDRW_Pos                (1UL)          /*!< DMASDRW (Bit 1)                                       */
+ #define R_SDHI0_CC_EXT_MODE_DMASDRW_Msk                (0x2UL)        /*!< DMASDRW (Bitfield-Mask: 0x01)                         */
+/* =======================================================  SOFT_RST  ======================================================== */
+ #define R_SDHI0_SOFT_RST_SDRST_Pos                     (0UL)          /*!< SDRST (Bit 0)                                         */
+ #define R_SDHI0_SOFT_RST_SDRST_Msk                     (0x1UL)        /*!< SDRST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  VERSION  ======================================================== */
+ #define R_SDHI0_VERSION_IP7IP0_Pos                     (0UL)          /*!< IP7IP0 (Bit 0)                                        */
+ #define R_SDHI0_VERSION_IP7IP0_Msk                     (0xffUL)       /*!< IP7IP0 (Bitfield-Mask: 0xff)                          */
+ #define R_SDHI0_VERSION_UR3UR0_Pos                     (8UL)          /*!< UR3UR0 (Bit 8)                                        */
+ #define R_SDHI0_VERSION_UR3UR0_Msk                     (0xf00UL)      /*!< UR3UR0 (Bitfield-Mask: 0x0f)                          */
+/* =======================================================  HOST_MODE  ======================================================= */
+ #define R_SDHI0_HOST_MODE_WMODE_Pos                    (0UL)          /*!< WMODE (Bit 0)                                         */
+ #define R_SDHI0_HOST_MODE_WMODE_Msk                    (0x1UL)        /*!< WMODE (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_HOST_MODE_ENDIAN_Pos                   (1UL)          /*!< ENDIAN (Bit 1)                                        */
+ #define R_SDHI0_HOST_MODE_ENDIAN_Msk                   (0x2UL)        /*!< ENDIAN (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_HOST_MODE_BUSWIDTH_Pos                 (8UL)          /*!< BUSWIDTH (Bit 8)                                      */
+ #define R_SDHI0_HOST_MODE_BUSWIDTH_Msk                 (0x100UL)      /*!< BUSWIDTH (Bitfield-Mask: 0x01)                        */
+/* =======================================================  SDIF_MODE  ======================================================= */
+ #define R_SDHI0_SDIF_MODE_DDR_Pos                      (0UL)          /*!< DDR (Bit 0)                                           */
+ #define R_SDHI0_SDIF_MODE_DDR_Msk                      (0x1UL)        /*!< DDR (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos                  (8UL)          /*!< NOCHKCR (Bit 8)                                       */
+ #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk                  (0x100UL)      /*!< NOCHKCR (Bitfield-Mask: 0x01)                         */
+/* =======================================================  SD_STATUS  ======================================================= */
+ #define R_SDHI0_SD_STATUS_SD_PWEN_Pos                  (0UL)          /*!< SD_PWEN (Bit 0)                                       */
+ #define R_SDHI0_SD_STATUS_SD_PWEN_Msk                  (0x1UL)        /*!< SD_PWEN (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_STATUS_SD_RST_Pos                   (1UL)          /*!< SD_RST (Bit 1)                                        */
+ #define R_SDHI0_SD_STATUS_SD_RST_Msk                   (0x2UL)        /*!< SD_RST (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_STATUS_SD_IOVS_Pos                  (16UL)         /*!< SD_IOVS (Bit 16)                                      */
+ #define R_SDHI0_SD_STATUS_SD_IOVS_Msk                  (0x10000UL)    /*!< SD_IOVS (Bitfield-Mask: 0x01)                         */
+/* ===================================================  DM_CM_DTRAN_MODE  ==================================================== */
+ #define R_SDHI0_DM_CM_DTRAN_MODE_BUS_WIDTH_Pos         (4UL)          /*!< BUS_WIDTH (Bit 4)                                     */
+ #define R_SDHI0_DM_CM_DTRAN_MODE_BUS_WIDTH_Msk         (0x30UL)       /*!< BUS_WIDTH (Bitfield-Mask: 0x03)                       */
+ #define R_SDHI0_DM_CM_DTRAN_MODE_CH_NUM_Pos            (16UL)         /*!< CH_NUM (Bit 16)                                       */
+ #define R_SDHI0_DM_CM_DTRAN_MODE_CH_NUM_Msk            (0x30000UL)    /*!< CH_NUM (Bitfield-Mask: 0x03)                          */
+/* ===================================================  DM_CM_DTRAN_CTRL  ==================================================== */
+ #define R_SDHI0_DM_CM_DTRAN_CTRL_DM_START_Pos          (0UL)          /*!< DM_START (Bit 0)                                      */
+ #define R_SDHI0_DM_CM_DTRAN_CTRL_DM_START_Msk          (0x1UL)        /*!< DM_START (Bitfield-Mask: 0x01)                        */
+/* =======================================================  DM_CM_RST  ======================================================= */
+ #define R_SDHI0_DM_CM_RST_DTRANRST0_Pos                (8UL)          /*!< DTRANRST0 (Bit 8)                                     */
+ #define R_SDHI0_DM_CM_RST_DTRANRST0_Msk                (0x100UL)      /*!< DTRANRST0 (Bitfield-Mask: 0x01)                       */
+ #define R_SDHI0_DM_CM_RST_DTRANRST1_Pos                (9UL)          /*!< DTRANRST1 (Bit 9)                                     */
+ #define R_SDHI0_DM_CM_RST_DTRANRST1_Msk                (0x200UL)      /*!< DTRANRST1 (Bitfield-Mask: 0x01)                       */
+/* ======================================================  DM_CM_INFO1  ====================================================== */
+ #define R_SDHI0_DM_CM_INFO1_DTRANEND0_Pos              (16UL)         /*!< DTRANEND0 (Bit 16)                                    */
+ #define R_SDHI0_DM_CM_INFO1_DTRANEND0_Msk              (0x10000UL)    /*!< DTRANEND0 (Bitfield-Mask: 0x01)                       */
+ #define R_SDHI0_DM_CM_INFO1_DTRANEND1_Pos              (20UL)         /*!< DTRANEND1 (Bit 20)                                    */
+ #define R_SDHI0_DM_CM_INFO1_DTRANEND1_Msk              (0x100000UL)   /*!< DTRANEND1 (Bitfield-Mask: 0x01)                       */
+/* ===================================================  DM_CM_INFO1_MASK  ==================================================== */
+ #define R_SDHI0_DM_CM_INFO1_MASK_DTRANEND0_MASK_Pos    (16UL)         /*!< DTRANEND0_MASK (Bit 16)                               */
+ #define R_SDHI0_DM_CM_INFO1_MASK_DTRANEND0_MASK_Msk    (0x10000UL)    /*!< DTRANEND0_MASK (Bitfield-Mask: 0x01)                  */
+ #define R_SDHI0_DM_CM_INFO1_MASK_DTRANEND1_MASK_Pos    (20UL)         /*!< DTRANEND1_MASK (Bit 20)                               */
+ #define R_SDHI0_DM_CM_INFO1_MASK_DTRANEND1_MASK_Msk    (0x100000UL)   /*!< DTRANEND1_MASK (Bitfield-Mask: 0x01)                  */
+/* ======================================================  DM_CM_INFO2  ====================================================== */
+ #define R_SDHI0_DM_CM_INFO2_DTRANERR0_Pos              (16UL)         /*!< DTRANERR0 (Bit 16)                                    */
+ #define R_SDHI0_DM_CM_INFO2_DTRANERR0_Msk              (0x10000UL)    /*!< DTRANERR0 (Bitfield-Mask: 0x01)                       */
+ #define R_SDHI0_DM_CM_INFO2_DTRANERR1_Pos              (17UL)         /*!< DTRANERR1 (Bit 17)                                    */
+ #define R_SDHI0_DM_CM_INFO2_DTRANERR1_Msk              (0x20000UL)    /*!< DTRANERR1 (Bitfield-Mask: 0x01)                       */
+/* ===================================================  DM_CM_INFO2_MASK  ==================================================== */
+ #define R_SDHI0_DM_CM_INFO2_MASK_DTRANERR0_MASK_Pos    (16UL)         /*!< DTRANERR0_MASK (Bit 16)                               */
+ #define R_SDHI0_DM_CM_INFO2_MASK_DTRANERR0_MASK_Msk    (0x10000UL)    /*!< DTRANERR0_MASK (Bitfield-Mask: 0x01)                  */
+ #define R_SDHI0_DM_CM_INFO2_MASK_DTRANERR1_MASK_Pos    (17UL)         /*!< DTRANERR1_MASK (Bit 17)                               */
+ #define R_SDHI0_DM_CM_INFO2_MASK_DTRANERR1_MASK_Msk    (0x20000UL)    /*!< DTRANERR1_MASK (Bitfield-Mask: 0x01)                  */
+/* =====================================================  DM_DTRAN_ADDR  ===================================================== */
+ #define R_SDHI0_DM_DTRAN_ADDR_DADDR_Pos                (3UL)          /*!< DADDR (Bit 3)                                         */
+ #define R_SDHI0_DM_DTRAN_ADDR_DADDR_Msk                (0xfffffff8UL) /*!< DADDR (Bitfield-Mask: 0x1fffffff)                     */
+/* ======================================================  SCC_DTCNTL  ======================================================= */
+ #define R_SDHI0_SCC_DTCNTL_TAPEN_Pos                   (0UL)          /*!< TAPEN (Bit 0)                                         */
+ #define R_SDHI0_SCC_DTCNTL_TAPEN_Msk                   (0x1UL)        /*!< TAPEN (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SCC_DTCNTL_TAPNUM7TAPNUM0_Pos          (16UL)         /*!< TAPNUM7TAPNUM0 (Bit 16)                               */
+ #define R_SDHI0_SCC_DTCNTL_TAPNUM7TAPNUM0_Msk          (0xff0000UL)   /*!< TAPNUM7TAPNUM0 (Bitfield-Mask: 0xff)                  */
+/* ======================================================  SCC_TAPSET  ======================================================= */
+ #define R_SDHI0_SCC_TAPSET_TAPSET7TAPSET0_Pos          (0UL)          /*!< TAPSET7TAPSET0 (Bit 0)                                */
+ #define R_SDHI0_SCC_TAPSET_TAPSET7TAPSET0_Msk          (0xffUL)       /*!< TAPSET7TAPSET0 (Bitfield-Mask: 0xff)                  */
+/* =======================================================  SCC_DT2FF  ======================================================= */
+ #define R_SDHI0_SCC_DT2FF_DT2NS_Pos                    (0UL)          /*!< DT2NS (Bit 0)                                         */
+ #define R_SDHI0_SCC_DT2FF_DT2NS_Msk                    (0xffUL)       /*!< DT2NS (Bitfield-Mask: 0xff)                           */
+ #define R_SDHI0_SCC_DT2FF_DT2NE_Pos                    (8UL)          /*!< DT2NE (Bit 8)                                         */
+ #define R_SDHI0_SCC_DT2FF_DT2NE_Msk                    (0xff00UL)     /*!< DT2NE (Bitfield-Mask: 0xff)                           */
+/* =======================================================  SCC_CKSEL  ======================================================= */
+ #define R_SDHI0_SCC_CKSEL_DTSEL_Pos                    (0UL)          /*!< DTSEL (Bit 0)                                         */
+ #define R_SDHI0_SCC_CKSEL_DTSEL_Msk                    (0x1UL)        /*!< DTSEL (Bitfield-Mask: 0x01)                           */
+/* ======================================================  SCC_RVSCNTL  ====================================================== */
+ #define R_SDHI0_SCC_RVSCNTL_RVSEN_Pos                  (0UL)          /*!< RVSEN (Bit 0)                                         */
+ #define R_SDHI0_SCC_RVSCNTL_RVSEN_Msk                  (0x1UL)        /*!< RVSEN (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SCC_RVSCNTL_TAPSEL_Pos                 (8UL)          /*!< TAPSEL (Bit 8)                                        */
+ #define R_SDHI0_SCC_RVSCNTL_TAPSEL_Msk                 (0xff00UL)     /*!< TAPSEL (Bitfield-Mask: 0xff)                          */
+/* ======================================================  SCC_RVSREQ  ======================================================= */
+ #define R_SDHI0_SCC_RVSREQ_REQTAPDWN_Pos               (0UL)          /*!< REQTAPDWN (Bit 0)                                     */
+ #define R_SDHI0_SCC_RVSREQ_REQTAPDWN_Msk               (0x1UL)        /*!< REQTAPDWN (Bitfield-Mask: 0x01)                       */
+ #define R_SDHI0_SCC_RVSREQ_REQTAPUP_Pos                (1UL)          /*!< REQTAPUP (Bit 1)                                      */
+ #define R_SDHI0_SCC_RVSREQ_REQTAPUP_Msk                (0x2UL)        /*!< REQTAPUP (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SCC_RVSREQ_RVSERR_Pos                  (2UL)          /*!< RVSERR (Bit 2)                                        */
+ #define R_SDHI0_SCC_RVSREQ_RVSERR_Msk                  (0x4UL)        /*!< RVSERR (Bitfield-Mask: 0x01)                          */
+/* ======================================================  SCC_SMPCMP  ======================================================= */
+ #define R_SDHI0_SCC_SMPCMP_CMPNGD_Pos                  (0UL)          /*!< CMPNGD (Bit 0)                                        */
+ #define R_SDHI0_SCC_SMPCMP_CMPNGD_Msk                  (0x1ffUL)      /*!< CMPNGD (Bitfield-Mask: 0x1ff)                         */
+ #define R_SDHI0_SCC_SMPCMP_CMPNGU_Pos                  (16UL)         /*!< CMPNGU (Bit 16)                                       */
+ #define R_SDHI0_SCC_SMPCMP_CMPNGU_Msk                  (0x1ff0000UL)  /*!< CMPNGU (Bitfield-Mask: 0x1ff)                         */
+/* ======================================================  SCC_TMPPORT  ====================================================== */
+ #define R_SDHI0_SCC_TMPPORT_TMPOUT_Pos                 (0UL)          /*!< TMPOUT (Bit 0)                                        */
+ #define R_SDHI0_SCC_TMPPORT_TMPOUT_Msk                 (0xffffUL)     /*!< TMPOUT (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_LCDC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  DU_MCR0  ======================================================== */
+ #define R_LCDC_DU_MCR0_DPI_OE_Pos                        (0UL)          /*!< DPI_OE (Bit 0)                                        */
+ #define R_LCDC_DU_MCR0_DPI_OE_Msk                        (0x1UL)        /*!< DPI_OE (Bitfield-Mask: 0x01)                          */
+ #define R_LCDC_DU_MCR0_DI_EN_Pos                         (8UL)          /*!< DI_EN (Bit 8)                                         */
+ #define R_LCDC_DU_MCR0_DI_EN_Msk                         (0x100UL)      /*!< DI_EN (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_DU_MCR0_PB_CLR_Pos                        (16UL)         /*!< PB_CLR (Bit 16)                                       */
+ #define R_LCDC_DU_MCR0_PB_CLR_Msk                        (0x10000UL)    /*!< PB_CLR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DU_MSR0  ======================================================== */
+ #define R_LCDC_DU_MSR0_ST_DI_BSY_Pos                     (8UL)          /*!< ST_DI_BSY (Bit 8)                                     */
+ #define R_LCDC_DU_MSR0_ST_DI_BSY_Msk                     (0x100UL)      /*!< ST_DI_BSY (Bitfield-Mask: 0x01)                       */
+ #define R_LCDC_DU_MSR0_ST_PB_WFULL_Pos                   (16UL)         /*!< ST_PB_WFULL (Bit 16)                                  */
+ #define R_LCDC_DU_MSR0_ST_PB_WFULL_Msk                   (0x10000UL)    /*!< ST_PB_WFULL (Bitfield-Mask: 0x01)                     */
+ #define R_LCDC_DU_MSR0_ST_PB_WINIT_Pos                   (18UL)         /*!< ST_PB_WINIT (Bit 18)                                  */
+ #define R_LCDC_DU_MSR0_ST_PB_WINIT_Msk                   (0x40000UL)    /*!< ST_PB_WINIT (Bitfield-Mask: 0x01)                     */
+ #define R_LCDC_DU_MSR0_ST_PB_REMPTY_Pos                  (20UL)         /*!< ST_PB_REMPTY (Bit 20)                                 */
+ #define R_LCDC_DU_MSR0_ST_PB_REMPTY_Msk                  (0x100000UL)   /*!< ST_PB_REMPTY (Bitfield-Mask: 0x01)                    */
+ #define R_LCDC_DU_MSR0_ST_PB_RUF_Pos                     (21UL)         /*!< ST_PB_RUF (Bit 21)                                    */
+ #define R_LCDC_DU_MSR0_ST_PB_RUF_Msk                     (0x200000UL)   /*!< ST_PB_RUF (Bitfield-Mask: 0x01)                       */
+ #define R_LCDC_DU_MSR0_ST_PB_RINIT_Pos                   (22UL)         /*!< ST_PB_RINIT (Bit 22)                                  */
+ #define R_LCDC_DU_MSR0_ST_PB_RINIT_Msk                   (0x400000UL)   /*!< ST_PB_RINIT (Bitfield-Mask: 0x01)                     */
+/* ========================================================  DU_MSR1  ======================================================== */
+ #define R_LCDC_DU_MSR1_UF_HACT_Pos                       (0UL)          /*!< UF_HACT (Bit 0)                                       */
+ #define R_LCDC_DU_MSR1_UF_HACT_Msk                       (0x1fffUL)     /*!< UF_HACT (Bitfield-Mask: 0x1fff)                       */
+ #define R_LCDC_DU_MSR1_UF_VACT_Pos                       (16UL)         /*!< UF_VACT (Bit 16)                                      */
+ #define R_LCDC_DU_MSR1_UF_VACT_Msk                       (0x1fff0000UL) /*!< UF_VACT (Bitfield-Mask: 0x1fff)                       */
+/* ========================================================  DU_IMR0  ======================================================== */
+ #define R_LCDC_DU_IMR0_IM_PB_RUF_Pos                     (0UL)          /*!< IM_PB_RUF (Bit 0)                                     */
+ #define R_LCDC_DU_IMR0_IM_PB_RUF_Msk                     (0x1UL)        /*!< IM_PB_RUF (Bitfield-Mask: 0x01)                       */
+/* =======================================================  DU_DITR0  ======================================================== */
+ #define R_LCDC_DU_DITR0_DPI_CLKMD_Pos                    (0UL)          /*!< DPI_CLKMD (Bit 0)                                     */
+ #define R_LCDC_DU_DITR0_DPI_CLKMD_Msk                    (0x1UL)        /*!< DPI_CLKMD (Bitfield-Mask: 0x01)                       */
+ #define R_LCDC_DU_DITR0_DEMD_Pos                         (8UL)          /*!< DEMD (Bit 8)                                          */
+ #define R_LCDC_DU_DITR0_DEMD_Msk                         (0x300UL)      /*!< DEMD (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_DU_DITR0_VSPOL_Pos                        (16UL)         /*!< VSPOL (Bit 16)                                        */
+ #define R_LCDC_DU_DITR0_VSPOL_Msk                        (0x10000UL)    /*!< VSPOL (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_DU_DITR0_HSPOL_Pos                        (17UL)         /*!< HSPOL (Bit 17)                                        */
+ #define R_LCDC_DU_DITR0_HSPOL_Msk                        (0x20000UL)    /*!< HSPOL (Bitfield-Mask: 0x01)                           */
+/* =======================================================  DU_DITR1  ======================================================== */
+ #define R_LCDC_DU_DITR1_VSA_Pos                          (0UL)          /*!< VSA (Bit 0)                                           */
+ #define R_LCDC_DU_DITR1_VSA_Msk                          (0xfffUL)      /*!< VSA (Bitfield-Mask: 0xfff)                            */
+ #define R_LCDC_DU_DITR1_VACTIVE_Pos                      (16UL)         /*!< VACTIVE (Bit 16)                                      */
+ #define R_LCDC_DU_DITR1_VACTIVE_Msk                      (0x1fff0000UL) /*!< VACTIVE (Bitfield-Mask: 0x1fff)                       */
+/* =======================================================  DU_DITR2  ======================================================== */
+ #define R_LCDC_DU_DITR2_VBP_Pos                          (0UL)          /*!< VBP (Bit 0)                                           */
+ #define R_LCDC_DU_DITR2_VBP_Msk                          (0x1fffUL)     /*!< VBP (Bitfield-Mask: 0x1fff)                           */
+ #define R_LCDC_DU_DITR2_VFP_Pos                          (16UL)         /*!< VFP (Bit 16)                                          */
+ #define R_LCDC_DU_DITR2_VFP_Msk                          (0x1fff0000UL) /*!< VFP (Bitfield-Mask: 0x1fff)                           */
+/* =======================================================  DU_DITR3  ======================================================== */
+ #define R_LCDC_DU_DITR3_HSA_Pos                          (0UL)          /*!< HSA (Bit 0)                                           */
+ #define R_LCDC_DU_DITR3_HSA_Msk                          (0xfffUL)      /*!< HSA (Bitfield-Mask: 0xfff)                            */
+ #define R_LCDC_DU_DITR3_HACTIVE_Pos                      (16UL)         /*!< HACTIVE (Bit 16)                                      */
+ #define R_LCDC_DU_DITR3_HACTIVE_Msk                      (0x1fff0000UL) /*!< HACTIVE (Bitfield-Mask: 0x1fff)                       */
+/* =======================================================  DU_DITR4  ======================================================== */
+ #define R_LCDC_DU_DITR4_HBP_Pos                          (0UL)          /*!< HBP (Bit 0)                                           */
+ #define R_LCDC_DU_DITR4_HBP_Msk                          (0x1fffUL)     /*!< HBP (Bitfield-Mask: 0x1fff)                           */
+ #define R_LCDC_DU_DITR4_HFP_Pos                          (16UL)         /*!< HFP (Bit 16)                                          */
+ #define R_LCDC_DU_DITR4_HFP_Msk                          (0x1fff0000UL) /*!< HFP (Bitfield-Mask: 0x1fff)                           */
+/* ========================================================  DU_MCR1  ======================================================== */
+ #define R_LCDC_DU_MCR1_OPMD_Pos                          (0UL)          /*!< OPMD (Bit 0)                                          */
+ #define R_LCDC_DU_MCR1_OPMD_Msk                          (0x3UL)        /*!< OPMD (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_DU_MCR1_PB_AUTOCLR_Pos                    (16UL)         /*!< PB_AUTOCLR (Bit 16)                                   */
+ #define R_LCDC_DU_MCR1_PB_AUTOCLR_Msk                    (0x10000UL)    /*!< PB_AUTOCLR (Bitfield-Mask: 0x01)                      */
+/* =======================================================  DU_PBCR0  ======================================================== */
+ #define R_LCDC_DU_PBCR0_PB_DEP_Pos                       (0UL)          /*!< PB_DEP (Bit 0)                                        */
+ #define R_LCDC_DU_PBCR0_PB_DEP_Msk                       (0x1fUL)       /*!< PB_DEP (Bitfield-Mask: 0x1f)                          */
+/* =======================================================  DU_PBCR1  ======================================================== */
+ #define R_LCDC_DU_PBCR1_PB_RUFOP_Pos                     (0UL)          /*!< PB_RUFOP (Bit 0)                                      */
+ #define R_LCDC_DU_PBCR1_PB_RUFOP_Msk                     (0x1UL)        /*!< PB_RUFOP (Bitfield-Mask: 0x01)                        */
+/* =======================================================  DU_PBCR2  ======================================================== */
+ #define R_LCDC_DU_PBCR2_PB_RUFDAT_Pos                    (0UL)          /*!< PB_RUFDAT (Bit 0)                                     */
+ #define R_LCDC_DU_PBCR2_PB_RUFDAT_Msk                    (0xffffffUL)   /*!< PB_RUFDAT (Bitfield-Mask: 0xffffff)                   */
+/* ========================================================  FCP_VCR  ======================================================== */
+ #define R_LCDC_FCP_VCR_REVISION_Pos                      (0UL)          /*!< REVISION (Bit 0)                                      */
+ #define R_LCDC_FCP_VCR_REVISION_Msk                      (0xffUL)       /*!< REVISION (Bitfield-Mask: 0xff)                        */
+ #define R_LCDC_FCP_VCR_CATEGORY_Pos                      (8UL)          /*!< CATEGORY (Bit 8)                                      */
+ #define R_LCDC_FCP_VCR_CATEGORY_Msk                      (0xff00UL)     /*!< CATEGORY (Bitfield-Mask: 0xff)                        */
+/* =======================================================  VI6_CMD0  ======================================================== */
+ #define R_LCDC_VI6_CMD0_STRCMD_Pos                       (0UL)          /*!< STRCMD (Bit 0)                                        */
+ #define R_LCDC_VI6_CMD0_STRCMD_Msk                       (0x1UL)        /*!< STRCMD (Bitfield-Mask: 0x01)                          */
+ #define R_LCDC_VI6_CMD0_UPDHDR_Pos                       (4UL)          /*!< UPDHDR (Bit 4)                                        */
+ #define R_LCDC_VI6_CMD0_UPDHDR_Msk                       (0x10UL)       /*!< UPDHDR (Bitfield-Mask: 0x01)                          */
+/* =====================================================  VI6_CLK_CTRL0  ===================================================== */
+ #define R_LCDC_VI6_CLK_CTRL0_GCS3_Pos                    (0UL)          /*!< GCS3 (Bit 0)                                          */
+ #define R_LCDC_VI6_CLK_CTRL0_GCS3_Msk                    (0x1fUL)       /*!< GCS3 (Bitfield-Mask: 0x1f)                            */
+ #define R_LCDC_VI6_CLK_CTRL0_GCS2_Pos                    (8UL)          /*!< GCS2 (Bit 8)                                          */
+ #define R_LCDC_VI6_CLK_CTRL0_GCS2_Msk                    (0xf00UL)      /*!< GCS2 (Bitfield-Mask: 0x0f)                            */
+ #define R_LCDC_VI6_CLK_CTRL0_GCS1_Pos                    (16UL)         /*!< GCS1 (Bit 16)                                         */
+ #define R_LCDC_VI6_CLK_CTRL0_GCS1_Msk                    (0x10000UL)    /*!< GCS1 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_CLK_CTRL0_GCS0_Pos                    (28UL)         /*!< GCS0 (Bit 28)                                         */
+ #define R_LCDC_VI6_CLK_CTRL0_GCS0_Msk                    (0x10000000UL) /*!< GCS0 (Bitfield-Mask: 0x01)                            */
+/* =====================================================  VI6_CLK_CTRL1  ===================================================== */
+ #define R_LCDC_VI6_CLK_CTRL1_GCS5_Pos                    (0UL)          /*!< GCS5 (Bit 0)                                          */
+ #define R_LCDC_VI6_CLK_CTRL1_GCS5_Msk                    (0xffffUL)     /*!< GCS5 (Bitfield-Mask: 0xffff)                          */
+ #define R_LCDC_VI6_CLK_CTRL1_GCS6_Pos                    (20UL)         /*!< GCS6 (Bit 20)                                         */
+ #define R_LCDC_VI6_CLK_CTRL1_GCS6_Msk                    (0x100000UL)   /*!< GCS6 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_CLK_CTRL1_GCS4_Pos                    (24UL)         /*!< GCS4 (Bit 24)                                         */
+ #define R_LCDC_VI6_CLK_CTRL1_GCS4_Msk                    (0xff000000UL) /*!< GCS4 (Bitfield-Mask: 0xff)                            */
+/* =====================================================  VI6_CLK_DCSWT  ===================================================== */
+ #define R_LCDC_VI6_CLK_DCSWT_CSTRW_Pos                   (0UL)          /*!< CSTRW (Bit 0)                                         */
+ #define R_LCDC_VI6_CLK_DCSWT_CSTRW_Msk                   (0xffUL)       /*!< CSTRW (Bitfield-Mask: 0xff)                           */
+ #define R_LCDC_VI6_CLK_DCSWT_CSTPW_Pos                   (8UL)          /*!< CSTPW (Bit 8)                                         */
+ #define R_LCDC_VI6_CLK_DCSWT_CSTPW_Msk                   (0xff00UL)     /*!< CSTPW (Bitfield-Mask: 0xff)                           */
+ #define R_LCDC_VI6_CLK_DCSWT_DCC2_Pos                    (16UL)         /*!< DCC2 (Bit 16)                                         */
+ #define R_LCDC_VI6_CLK_DCSWT_DCC2_Msk                    (0x10000UL)    /*!< DCC2 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_CLK_DCSWT_DCC1_Pos                    (17UL)         /*!< DCC1 (Bit 17)                                         */
+ #define R_LCDC_VI6_CLK_DCSWT_DCC1_Msk                    (0x20000UL)    /*!< DCC1 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_CLK_DCSWT_DCC0_Pos                    (20UL)         /*!< DCC0 (Bit 20)                                         */
+ #define R_LCDC_VI6_CLK_DCSWT_DCC0_Msk                    (0x300000UL)   /*!< DCC0 (Bitfield-Mask: 0x03)                            */
+/* =====================================================  VI6_CLK_DCSM0  ===================================================== */
+ #define R_LCDC_VI6_CLK_DCSM0_DCD2_Pos                    (0UL)          /*!< DCD2 (Bit 0)                                          */
+ #define R_LCDC_VI6_CLK_DCSM0_DCD2_Msk                    (0x1fUL)       /*!< DCD2 (Bitfield-Mask: 0x1f)                            */
+ #define R_LCDC_VI6_CLK_DCSM0_DCD1_Pos                    (8UL)          /*!< DCD1 (Bit 8)                                          */
+ #define R_LCDC_VI6_CLK_DCSM0_DCD1_Msk                    (0xf00UL)      /*!< DCD1 (Bitfield-Mask: 0x0f)                            */
+ #define R_LCDC_VI6_CLK_DCSM0_DCD0_Pos                    (16UL)         /*!< DCD0 (Bit 16)                                         */
+ #define R_LCDC_VI6_CLK_DCSM0_DCD0_Msk                    (0x1fff0000UL) /*!< DCD0 (Bitfield-Mask: 0x1fff)                          */
+/* =====================================================  VI6_CLK_DCSM1  ===================================================== */
+ #define R_LCDC_VI6_CLK_DCSM1_DCD4_Pos                    (0UL)          /*!< DCD4 (Bit 0)                                          */
+ #define R_LCDC_VI6_CLK_DCSM1_DCD4_Msk                    (0xffffUL)     /*!< DCD4 (Bitfield-Mask: 0xffff)                          */
+ #define R_LCDC_VI6_CLK_DCSM1_DCD5_Pos                    (20UL)         /*!< DCD5 (Bit 20)                                         */
+ #define R_LCDC_VI6_CLK_DCSM1_DCD5_Msk                    (0x100000UL)   /*!< DCD5 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_CLK_DCSM1_DCD3_Pos                    (24UL)         /*!< DCD3 (Bit 24)                                         */
+ #define R_LCDC_VI6_CLK_DCSM1_DCD3_Msk                    (0xff000000UL) /*!< DCD3 (Bitfield-Mask: 0xff)                            */
+/* ======================================================  VI6_SRESET  ======================================================= */
+ #define R_LCDC_VI6_SRESET_SRST0_Pos                      (0UL)          /*!< SRST0 (Bit 0)                                         */
+ #define R_LCDC_VI6_SRESET_SRST0_Msk                      (0x1UL)        /*!< SRST0 (Bitfield-Mask: 0x01)                           */
+/* ====================================================  VI6_MRESET_ENB0  ==================================================== */
+ #define R_LCDC_VI6_MRESET_ENB0_MRSTE2_Pos                (0UL)          /*!< MRSTE2 (Bit 0)                                        */
+ #define R_LCDC_VI6_MRESET_ENB0_MRSTE2_Msk                (0x1fUL)       /*!< MRSTE2 (Bitfield-Mask: 0x1f)                          */
+ #define R_LCDC_VI6_MRESET_ENB0_MRSTE1_Pos                (8UL)          /*!< MRSTE1 (Bit 8)                                        */
+ #define R_LCDC_VI6_MRESET_ENB0_MRSTE1_Msk                (0xf00UL)      /*!< MRSTE1 (Bitfield-Mask: 0x0f)                          */
+ #define R_LCDC_VI6_MRESET_ENB0_MRSTE0_Pos                (28UL)         /*!< MRSTE0 (Bit 28)                                       */
+ #define R_LCDC_VI6_MRESET_ENB0_MRSTE0_Msk                (0x30000000UL) /*!< MRSTE0 (Bitfield-Mask: 0x03)                          */
+/* ====================================================  VI6_MRESET_ENB1  ==================================================== */
+ #define R_LCDC_VI6_MRESET_ENB1_MRSTE4_Pos                (0UL)          /*!< MRSTE4 (Bit 0)                                        */
+ #define R_LCDC_VI6_MRESET_ENB1_MRSTE4_Msk                (0xffffUL)     /*!< MRSTE4 (Bitfield-Mask: 0xffff)                        */
+ #define R_LCDC_VI6_MRESET_ENB1_MRSTE3_Pos                (24UL)         /*!< MRSTE3 (Bit 24)                                       */
+ #define R_LCDC_VI6_MRESET_ENB1_MRSTE3_Msk                (0xff000000UL) /*!< MRSTE3 (Bitfield-Mask: 0xff)                          */
+/* ======================================================  VI6_MRESET  ======================================================= */
+ #define R_LCDC_VI6_MRESET_MRST_Pos                       (0UL)          /*!< MRST (Bit 0)                                          */
+ #define R_LCDC_VI6_MRESET_MRST_Msk                       (0x1UL)        /*!< MRST (Bitfield-Mask: 0x01)                            */
+/* ======================================================  VI6_STATUS  ======================================================= */
+ #define R_LCDC_VI6_STATUS_SYS0_ACT_Pos                   (8UL)          /*!< SYS0_ACT (Bit 8)                                      */
+ #define R_LCDC_VI6_STATUS_SYS0_ACT_Msk                   (0x100UL)      /*!< SYS0_ACT (Bitfield-Mask: 0x01)                        */
+ #define R_LCDC_VI6_STATUS_FLDST0_Pos                     (28UL)         /*!< FLDST0 (Bit 28)                                       */
+ #define R_LCDC_VI6_STATUS_FLDST0_Msk                     (0x10000000UL) /*!< FLDST0 (Bitfield-Mask: 0x01)                          */
+/* ===================================================  VI6_WPF0_IRQ_ENB  ==================================================== */
+ #define R_LCDC_VI6_WPF0_IRQ_ENB_FREE_Pos                 (0UL)          /*!< FREE (Bit 0)                                          */
+ #define R_LCDC_VI6_WPF0_IRQ_ENB_FREE_Msk                 (0x1UL)        /*!< FREE (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_WPF0_IRQ_ENB_DFEE_Pos                 (1UL)          /*!< DFEE (Bit 1)                                          */
+ #define R_LCDC_VI6_WPF0_IRQ_ENB_DFEE_Msk                 (0x2UL)        /*!< DFEE (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_WPF0_IRQ_ENB_UNDE_Pos                 (16UL)         /*!< UNDE (Bit 16)                                         */
+ #define R_LCDC_VI6_WPF0_IRQ_ENB_UNDE_Msk                 (0x10000UL)    /*!< UNDE (Bitfield-Mask: 0x01)                            */
+/* ===================================================  VI6_WPF0_IRQ_STA  ==================================================== */
+ #define R_LCDC_VI6_WPF0_IRQ_STA_FRE_Pos                  (0UL)          /*!< FRE (Bit 0)                                           */
+ #define R_LCDC_VI6_WPF0_IRQ_STA_FRE_Msk                  (0x1UL)        /*!< FRE (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_WPF0_IRQ_STA_DFE_Pos                  (1UL)          /*!< DFE (Bit 1)                                           */
+ #define R_LCDC_VI6_WPF0_IRQ_STA_DFE_Msk                  (0x2UL)        /*!< DFE (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_WPF0_IRQ_STA_UND_Pos                  (16UL)         /*!< UND (Bit 16)                                          */
+ #define R_LCDC_VI6_WPF0_IRQ_STA_UND_Msk                  (0x10000UL)    /*!< UND (Bitfield-Mask: 0x01)                             */
+/* ===================================================  VI6_DISP0_IRQ_ENB  =================================================== */
+ #define R_LCDC_VI6_DISP0_IRQ_ENB_MAEE_Pos                (5UL)          /*!< MAEE (Bit 5)                                          */
+ #define R_LCDC_VI6_DISP0_IRQ_ENB_MAEE_Msk                (0x20UL)       /*!< MAEE (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_DISP0_IRQ_ENB_DSTE_Pos                (8UL)          /*!< DSTE (Bit 8)                                          */
+ #define R_LCDC_VI6_DISP0_IRQ_ENB_DSTE_Msk                (0x100UL)      /*!< DSTE (Bitfield-Mask: 0x01)                            */
+/* ===================================================  VI6_DISP0_IRQ_STA  =================================================== */
+ #define R_LCDC_VI6_DISP0_IRQ_STA_MAE_Pos                 (5UL)          /*!< MAE (Bit 5)                                           */
+ #define R_LCDC_VI6_DISP0_IRQ_STA_MAE_Msk                 (0x20UL)       /*!< MAE (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_DISP0_IRQ_STA_DST_Pos                 (8UL)          /*!< DST (Bit 8)                                           */
+ #define R_LCDC_VI6_DISP0_IRQ_STA_DST_Msk                 (0x100UL)      /*!< DST (Bitfield-Mask: 0x01)                             */
+/* ======================================================  VI6_DL_CTRL  ====================================================== */
+ #define R_LCDC_VI6_DL_CTRL_DLE0_Pos                      (0UL)          /*!< DLE0 (Bit 0)                                          */
+ #define R_LCDC_VI6_DL_CTRL_DLE0_Msk                      (0x1UL)        /*!< DLE0 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_DL_CTRL_NH0_Pos                       (1UL)          /*!< NH0 (Bit 1)                                           */
+ #define R_LCDC_VI6_DL_CTRL_NH0_Msk                       (0x2UL)        /*!< NH0 (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_DL_CTRL_CFM0_Pos                      (2UL)          /*!< CFM0 (Bit 2)                                          */
+ #define R_LCDC_VI6_DL_CTRL_CFM0_Msk                      (0x4UL)        /*!< CFM0 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_DL_CTRL_RLM0_Pos                      (3UL)          /*!< RLM0 (Bit 3)                                          */
+ #define R_LCDC_VI6_DL_CTRL_RLM0_Msk                      (0x8UL)        /*!< RLM0 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_DL_CTRL_DLE1_Pos                      (4UL)          /*!< DLE1 (Bit 4)                                          */
+ #define R_LCDC_VI6_DL_CTRL_DLE1_Msk                      (0x10UL)       /*!< DLE1 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_DL_CTRL_DC1_Pos                       (8UL)          /*!< DC1 (Bit 8)                                           */
+ #define R_LCDC_VI6_DL_CTRL_DC1_Msk                       (0x100UL)      /*!< DC1 (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_DL_CTRL_DC2_Pos                       (12UL)         /*!< DC2 (Bit 12)                                          */
+ #define R_LCDC_VI6_DL_CTRL_DC2_Msk                       (0x1000UL)     /*!< DC2 (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_DL_CTRL_AR_WAIT_Pos                   (16UL)         /*!< AR_WAIT (Bit 16)                                      */
+ #define R_LCDC_VI6_DL_CTRL_AR_WAIT_Msk                   (0xffff0000UL) /*!< AR_WAIT (Bitfield-Mask: 0xffff)                       */
+/* ===================================================  VI6_DL_HDR_ADDR0  ==================================================== */
+/* =====================================================  VI6_DL_SWAP0  ====================================================== */
+ #define R_LCDC_VI6_DL_SWAP0_BTS_Pos                      (0UL)          /*!< BTS (Bit 0)                                           */
+ #define R_LCDC_VI6_DL_SWAP0_BTS_Msk                      (0x1UL)        /*!< BTS (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_DL_SWAP0_WDS_Pos                      (1UL)          /*!< WDS (Bit 1)                                           */
+ #define R_LCDC_VI6_DL_SWAP0_WDS_Msk                      (0x2UL)        /*!< WDS (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_DL_SWAP0_LWS_Pos                      (2UL)          /*!< LWS (Bit 2)                                           */
+ #define R_LCDC_VI6_DL_SWAP0_LWS_Msk                      (0x4UL)        /*!< LWS (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_DL_SWAP0_IND_Pos                      (31UL)         /*!< IND (Bit 31)                                          */
+ #define R_LCDC_VI6_DL_SWAP0_IND_Msk                      (0x80000000UL) /*!< IND (Bitfield-Mask: 0x01)                             */
+/* ===================================================  VI6_DL_EXT_CTRL0  ==================================================== */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_EXT_Pos                  (0UL)          /*!< EXT (Bit 0)                                           */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_EXT_Msk                  (0x1UL)        /*!< EXT (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_EXPRI_Pos                (4UL)          /*!< EXPRI (Bit 4)                                         */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_EXPRI_Msk                (0x10UL)       /*!< EXPRI (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_DLPRI_Pos                (5UL)          /*!< DLPRI (Bit 5)                                         */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_DLPRI_Msk                (0x20UL)       /*!< DLPRI (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_POLINT_Pos               (8UL)          /*!< POLINT (Bit 8)                                        */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_POLINT_Msk               (0x3f00UL)     /*!< POLINT (Bitfield-Mask: 0x3f)                          */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_NWE_Pos                  (16UL)         /*!< NWE (Bit 16)                                          */
+ #define R_LCDC_VI6_DL_EXT_CTRL0_NWE_Msk                  (0x10000UL)    /*!< NWE (Bitfield-Mask: 0x01)                             */
+/* ===================================================  VI6_DL_BODY_SIZE0  =================================================== */
+ #define R_LCDC_VI6_DL_BODY_SIZE0_BS0_Pos                 (0UL)          /*!< BS0 (Bit 0)                                           */
+ #define R_LCDC_VI6_DL_BODY_SIZE0_BS0_Msk                 (0x1ffffUL)    /*!< BS0 (Bitfield-Mask: 0x1ffff)                          */
+ #define R_LCDC_VI6_DL_BODY_SIZE0_UPD0_Pos                (24UL)         /*!< UPD0 (Bit 24)                                         */
+ #define R_LCDC_VI6_DL_BODY_SIZE0_UPD0_Msk                (0x1000000UL)  /*!< UPD0 (Bitfield-Mask: 0x01)                            */
+/* =================================================  VI6_DL_HDR_REF_ADDR0  ================================================== */
+/* ==================================================  VI6_RPF0_SRC_BSIZE  =================================================== */
+ #define R_LCDC_VI6_RPF0_SRC_BSIZE_BVSIZE_Pos             (0UL)          /*!< BVSIZE (Bit 0)                                        */
+ #define R_LCDC_VI6_RPF0_SRC_BSIZE_BVSIZE_Msk             (0x1fffUL)     /*!< BVSIZE (Bitfield-Mask: 0x1fff)                        */
+ #define R_LCDC_VI6_RPF0_SRC_BSIZE_BHSIZE_Pos             (16UL)         /*!< BHSIZE (Bit 16)                                       */
+ #define R_LCDC_VI6_RPF0_SRC_BSIZE_BHSIZE_Msk             (0x1fff0000UL) /*!< BHSIZE (Bitfield-Mask: 0x1fff)                        */
+/* ==================================================  VI6_RPF1_SRC_BSIZE  =================================================== */
+ #define R_LCDC_VI6_RPF1_SRC_BSIZE_BVSIZE_Pos             (0UL)          /*!< BVSIZE (Bit 0)                                        */
+ #define R_LCDC_VI6_RPF1_SRC_BSIZE_BVSIZE_Msk             (0x1fffUL)     /*!< BVSIZE (Bitfield-Mask: 0x1fff)                        */
+ #define R_LCDC_VI6_RPF1_SRC_BSIZE_BHSIZE_Pos             (16UL)         /*!< BHSIZE (Bit 16)                                       */
+ #define R_LCDC_VI6_RPF1_SRC_BSIZE_BHSIZE_Msk             (0x1fff0000UL) /*!< BHSIZE (Bitfield-Mask: 0x1fff)                        */
+/* ==================================================  VI6_RPF0_SRC_ESIZE  =================================================== */
+ #define R_LCDC_VI6_RPF0_SRC_ESIZE_EVSIZE_Pos             (0UL)          /*!< EVSIZE (Bit 0)                                        */
+ #define R_LCDC_VI6_RPF0_SRC_ESIZE_EVSIZE_Msk             (0x1fffUL)     /*!< EVSIZE (Bitfield-Mask: 0x1fff)                        */
+ #define R_LCDC_VI6_RPF0_SRC_ESIZE_EHSIZE_Pos             (16UL)         /*!< EHSIZE (Bit 16)                                       */
+ #define R_LCDC_VI6_RPF0_SRC_ESIZE_EHSIZE_Msk             (0x1fff0000UL) /*!< EHSIZE (Bitfield-Mask: 0x1fff)                        */
+/* ==================================================  VI6_RPF1_SRC_ESIZE  =================================================== */
+ #define R_LCDC_VI6_RPF1_SRC_ESIZE_EVSIZE_Pos             (0UL)          /*!< EVSIZE (Bit 0)                                        */
+ #define R_LCDC_VI6_RPF1_SRC_ESIZE_EVSIZE_Msk             (0x1fffUL)     /*!< EVSIZE (Bitfield-Mask: 0x1fff)                        */
+ #define R_LCDC_VI6_RPF1_SRC_ESIZE_EHSIZE_Pos             (16UL)         /*!< EHSIZE (Bit 16)                                       */
+ #define R_LCDC_VI6_RPF1_SRC_ESIZE_EHSIZE_Msk             (0x1fff0000UL) /*!< EHSIZE (Bitfield-Mask: 0x1fff)                        */
+/* ====================================================  VI6_RPF0_INFMT  ===================================================== */
+ #define R_LCDC_VI6_RPF0_INFMT_RDFMT_Pos                  (0UL)          /*!< RDFMT (Bit 0)                                         */
+ #define R_LCDC_VI6_RPF0_INFMT_RDFMT_Msk                  (0x7fUL)       /*!< RDFMT (Bitfield-Mask: 0x7f)                           */
+ #define R_LCDC_VI6_RPF0_INFMT_CSC_Pos                    (8UL)          /*!< CSC (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF0_INFMT_CSC_Msk                    (0x100UL)      /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_RPF0_INFMT_RDTM_Pos                   (9UL)          /*!< RDTM (Bit 9)                                          */
+ #define R_LCDC_VI6_RPF0_INFMT_RDTM_Msk                   (0xe00UL)      /*!< RDTM (Bitfield-Mask: 0x07)                            */
+ #define R_LCDC_VI6_RPF0_INFMT_CEXT_Pos                   (12UL)         /*!< CEXT (Bit 12)                                         */
+ #define R_LCDC_VI6_RPF0_INFMT_CEXT_Msk                   (0x3000UL)     /*!< CEXT (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_VI6_RPF0_INFMT_SPUVS_Pos                  (14UL)         /*!< SPUVS (Bit 14)                                        */
+ #define R_LCDC_VI6_RPF0_INFMT_SPUVS_Msk                  (0x4000UL)     /*!< SPUVS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_INFMT_SPYCS_Pos                  (15UL)         /*!< SPYCS (Bit 15)                                        */
+ #define R_LCDC_VI6_RPF0_INFMT_SPYCS_Msk                  (0x8000UL)     /*!< SPYCS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_INFMT_CIPM_Pos                   (16UL)         /*!< CIPM (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF0_INFMT_CIPM_Msk                   (0x10000UL)    /*!< CIPM (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_RPF0_INFMT_VIR_Pos                    (28UL)         /*!< VIR (Bit 28)                                          */
+ #define R_LCDC_VI6_RPF0_INFMT_VIR_Msk                    (0x10000000UL) /*!< VIR (Bitfield-Mask: 0x01)                             */
+/* ====================================================  VI6_RPF1_INFMT  ===================================================== */
+ #define R_LCDC_VI6_RPF1_INFMT_RDFMT_Pos                  (0UL)          /*!< RDFMT (Bit 0)                                         */
+ #define R_LCDC_VI6_RPF1_INFMT_RDFMT_Msk                  (0x7fUL)       /*!< RDFMT (Bitfield-Mask: 0x7f)                           */
+ #define R_LCDC_VI6_RPF1_INFMT_CSC_Pos                    (8UL)          /*!< CSC (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF1_INFMT_CSC_Msk                    (0x100UL)      /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_RPF1_INFMT_RDTM_Pos                   (9UL)          /*!< RDTM (Bit 9)                                          */
+ #define R_LCDC_VI6_RPF1_INFMT_RDTM_Msk                   (0xe00UL)      /*!< RDTM (Bitfield-Mask: 0x07)                            */
+ #define R_LCDC_VI6_RPF1_INFMT_CEXT_Pos                   (12UL)         /*!< CEXT (Bit 12)                                         */
+ #define R_LCDC_VI6_RPF1_INFMT_CEXT_Msk                   (0x3000UL)     /*!< CEXT (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_VI6_RPF1_INFMT_SPUVS_Pos                  (14UL)         /*!< SPUVS (Bit 14)                                        */
+ #define R_LCDC_VI6_RPF1_INFMT_SPUVS_Msk                  (0x4000UL)     /*!< SPUVS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_INFMT_SPYCS_Pos                  (15UL)         /*!< SPYCS (Bit 15)                                        */
+ #define R_LCDC_VI6_RPF1_INFMT_SPYCS_Msk                  (0x8000UL)     /*!< SPYCS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_INFMT_CIPM_Pos                   (16UL)         /*!< CIPM (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF1_INFMT_CIPM_Msk                   (0x10000UL)    /*!< CIPM (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_RPF1_INFMT_VIR_Pos                    (28UL)         /*!< VIR (Bit 28)                                          */
+ #define R_LCDC_VI6_RPF1_INFMT_VIR_Msk                    (0x10000000UL) /*!< VIR (Bitfield-Mask: 0x01)                             */
+/* ====================================================  VI6_RPF0_DSWAP  ===================================================== */
+ #define R_LCDC_VI6_RPF0_DSWAP_P_BTS_Pos                  (0UL)          /*!< P_BTS (Bit 0)                                         */
+ #define R_LCDC_VI6_RPF0_DSWAP_P_BTS_Msk                  (0x1UL)        /*!< P_BTS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_DSWAP_P_WDS_Pos                  (1UL)          /*!< P_WDS (Bit 1)                                         */
+ #define R_LCDC_VI6_RPF0_DSWAP_P_WDS_Msk                  (0x2UL)        /*!< P_WDS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_DSWAP_P_LWS_Pos                  (2UL)          /*!< P_LWS (Bit 2)                                         */
+ #define R_LCDC_VI6_RPF0_DSWAP_P_LWS_Msk                  (0x4UL)        /*!< P_LWS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_DSWAP_P_LLS_Pos                  (3UL)          /*!< P_LLS (Bit 3)                                         */
+ #define R_LCDC_VI6_RPF0_DSWAP_P_LLS_Msk                  (0x8UL)        /*!< P_LLS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_DSWAP_A_BTS_Pos                  (8UL)          /*!< A_BTS (Bit 8)                                         */
+ #define R_LCDC_VI6_RPF0_DSWAP_A_BTS_Msk                  (0x100UL)      /*!< A_BTS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_DSWAP_A_WDS_Pos                  (9UL)          /*!< A_WDS (Bit 9)                                         */
+ #define R_LCDC_VI6_RPF0_DSWAP_A_WDS_Msk                  (0x200UL)      /*!< A_WDS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_DSWAP_A_LWS_Pos                  (10UL)         /*!< A_LWS (Bit 10)                                        */
+ #define R_LCDC_VI6_RPF0_DSWAP_A_LWS_Msk                  (0x400UL)      /*!< A_LWS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_DSWAP_A_LLS_Pos                  (11UL)         /*!< A_LLS (Bit 11)                                        */
+ #define R_LCDC_VI6_RPF0_DSWAP_A_LLS_Msk                  (0x800UL)      /*!< A_LLS (Bitfield-Mask: 0x01)                           */
+/* ====================================================  VI6_RPF1_DSWAP  ===================================================== */
+ #define R_LCDC_VI6_RPF1_DSWAP_P_BTS_Pos                  (0UL)          /*!< P_BTS (Bit 0)                                         */
+ #define R_LCDC_VI6_RPF1_DSWAP_P_BTS_Msk                  (0x1UL)        /*!< P_BTS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_DSWAP_P_WDS_Pos                  (1UL)          /*!< P_WDS (Bit 1)                                         */
+ #define R_LCDC_VI6_RPF1_DSWAP_P_WDS_Msk                  (0x2UL)        /*!< P_WDS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_DSWAP_P_LWS_Pos                  (2UL)          /*!< P_LWS (Bit 2)                                         */
+ #define R_LCDC_VI6_RPF1_DSWAP_P_LWS_Msk                  (0x4UL)        /*!< P_LWS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_DSWAP_P_LLS_Pos                  (3UL)          /*!< P_LLS (Bit 3)                                         */
+ #define R_LCDC_VI6_RPF1_DSWAP_P_LLS_Msk                  (0x8UL)        /*!< P_LLS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_DSWAP_A_BTS_Pos                  (8UL)          /*!< A_BTS (Bit 8)                                         */
+ #define R_LCDC_VI6_RPF1_DSWAP_A_BTS_Msk                  (0x100UL)      /*!< A_BTS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_DSWAP_A_WDS_Pos                  (9UL)          /*!< A_WDS (Bit 9)                                         */
+ #define R_LCDC_VI6_RPF1_DSWAP_A_WDS_Msk                  (0x200UL)      /*!< A_WDS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_DSWAP_A_LWS_Pos                  (10UL)         /*!< A_LWS (Bit 10)                                        */
+ #define R_LCDC_VI6_RPF1_DSWAP_A_LWS_Msk                  (0x400UL)      /*!< A_LWS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_DSWAP_A_LLS_Pos                  (11UL)         /*!< A_LLS (Bit 11)                                        */
+ #define R_LCDC_VI6_RPF1_DSWAP_A_LLS_Msk                  (0x800UL)      /*!< A_LLS (Bitfield-Mask: 0x01)                           */
+/* =====================================================  VI6_RPF0_LOC  ====================================================== */
+ #define R_LCDC_VI6_RPF0_LOC_VCOORD_Pos                   (0UL)          /*!< VCOORD (Bit 0)                                        */
+ #define R_LCDC_VI6_RPF0_LOC_VCOORD_Msk                   (0x1fffUL)     /*!< VCOORD (Bitfield-Mask: 0x1fff)                        */
+ #define R_LCDC_VI6_RPF0_LOC_HCOORD_Pos                   (16UL)         /*!< HCOORD (Bit 16)                                       */
+ #define R_LCDC_VI6_RPF0_LOC_HCOORD_Msk                   (0x1fff0000UL) /*!< HCOORD (Bitfield-Mask: 0x1fff)                        */
+/* =====================================================  VI6_RPF1_LOC  ====================================================== */
+ #define R_LCDC_VI6_RPF1_LOC_VCOORD_Pos                   (0UL)          /*!< VCOORD (Bit 0)                                        */
+ #define R_LCDC_VI6_RPF1_LOC_VCOORD_Msk                   (0x1fffUL)     /*!< VCOORD (Bitfield-Mask: 0x1fff)                        */
+ #define R_LCDC_VI6_RPF1_LOC_HCOORD_Pos                   (16UL)         /*!< HCOORD (Bit 16)                                       */
+ #define R_LCDC_VI6_RPF1_LOC_HCOORD_Msk                   (0x1fff0000UL) /*!< HCOORD (Bitfield-Mask: 0x1fff)                        */
+/* ===================================================  VI6_RPF0_ALPH_SEL  =================================================== */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_ALPHA0_Pos              (0UL)          /*!< ALPHA0 (Bit 0)                                        */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_ALPHA0_Msk              (0xffUL)       /*!< ALPHA0 (Bitfield-Mask: 0xff)                          */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_ALPHA1_Pos              (8UL)          /*!< ALPHA1 (Bit 8)                                        */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_ALPHA1_Msk              (0xff00UL)     /*!< ALPHA1 (Bitfield-Mask: 0xff)                          */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_AEXT_Pos                (18UL)         /*!< AEXT (Bit 18)                                         */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_AEXT_Msk                (0xc0000UL)    /*!< AEXT (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_BSEL_Pos                (23UL)         /*!< BSEL (Bit 23)                                         */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_BSEL_Msk                (0x800000UL)   /*!< BSEL (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_IROP_Pos                (24UL)         /*!< IROP (Bit 24)                                         */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_IROP_Msk                (0xf000000UL)  /*!< IROP (Bitfield-Mask: 0x0f)                            */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_ASEL_Pos                (28UL)         /*!< ASEL (Bit 28)                                         */
+ #define R_LCDC_VI6_RPF0_ALPH_SEL_ASEL_Msk                (0x70000000UL) /*!< ASEL (Bitfield-Mask: 0x07)                            */
+/* ===================================================  VI6_RPF1_ALPH_SEL  =================================================== */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_ALPHA0_Pos              (0UL)          /*!< ALPHA0 (Bit 0)                                        */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_ALPHA0_Msk              (0xffUL)       /*!< ALPHA0 (Bitfield-Mask: 0xff)                          */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_ALPHA1_Pos              (8UL)          /*!< ALPHA1 (Bit 8)                                        */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_ALPHA1_Msk              (0xff00UL)     /*!< ALPHA1 (Bitfield-Mask: 0xff)                          */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_AEXT_Pos                (18UL)         /*!< AEXT (Bit 18)                                         */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_AEXT_Msk                (0xc0000UL)    /*!< AEXT (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_BSEL_Pos                (23UL)         /*!< BSEL (Bit 23)                                         */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_BSEL_Msk                (0x800000UL)   /*!< BSEL (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_IROP_Pos                (24UL)         /*!< IROP (Bit 24)                                         */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_IROP_Msk                (0xf000000UL)  /*!< IROP (Bitfield-Mask: 0x0f)                            */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_ASEL_Pos                (28UL)         /*!< ASEL (Bit 28)                                         */
+ #define R_LCDC_VI6_RPF1_ALPH_SEL_ASEL_Msk                (0x70000000UL) /*!< ASEL (Bitfield-Mask: 0x07)                            */
+/* ==================================================  VI6_RPF0_VRTCOL_SET  ================================================== */
+ #define R_LCDC_VI6_RPF0_VRTCOL_SET_LAYB_Pos              (0UL)          /*!< LAYB (Bit 0)                                          */
+ #define R_LCDC_VI6_RPF0_VRTCOL_SET_LAYB_Msk              (0xffUL)       /*!< LAYB (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_VRTCOL_SET_LAYG_Pos              (8UL)          /*!< LAYG (Bit 8)                                          */
+ #define R_LCDC_VI6_RPF0_VRTCOL_SET_LAYG_Msk              (0xff00UL)     /*!< LAYG (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_VRTCOL_SET_LAYR_Pos              (16UL)         /*!< LAYR (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF0_VRTCOL_SET_LAYR_Msk              (0xff0000UL)   /*!< LAYR (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_VRTCOL_SET_LAYA_Pos              (24UL)         /*!< LAYA (Bit 24)                                         */
+ #define R_LCDC_VI6_RPF0_VRTCOL_SET_LAYA_Msk              (0xff000000UL) /*!< LAYA (Bitfield-Mask: 0xff)                            */
+/* ==================================================  VI6_RPF1_VRTCOL_SET  ================================================== */
+ #define R_LCDC_VI6_RPF1_VRTCOL_SET_LAYB_Pos              (0UL)          /*!< LAYB (Bit 0)                                          */
+ #define R_LCDC_VI6_RPF1_VRTCOL_SET_LAYB_Msk              (0xffUL)       /*!< LAYB (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_VRTCOL_SET_LAYG_Pos              (8UL)          /*!< LAYG (Bit 8)                                          */
+ #define R_LCDC_VI6_RPF1_VRTCOL_SET_LAYG_Msk              (0xff00UL)     /*!< LAYG (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_VRTCOL_SET_LAYR_Pos              (16UL)         /*!< LAYR (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF1_VRTCOL_SET_LAYR_Msk              (0xff0000UL)   /*!< LAYR (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_VRTCOL_SET_LAYA_Pos              (24UL)         /*!< LAYA (Bit 24)                                         */
+ #define R_LCDC_VI6_RPF1_VRTCOL_SET_LAYA_Msk              (0xff000000UL) /*!< LAYA (Bitfield-Mask: 0xff)                            */
+/* ===================================================  VI6_RPF0_MSKCTRL  ==================================================== */
+ #define R_LCDC_VI6_RPF0_MSKCTRL_MGB_Pos                  (0UL)          /*!< MGB (Bit 0)                                           */
+ #define R_LCDC_VI6_RPF0_MSKCTRL_MGB_Msk                  (0xffUL)       /*!< MGB (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF0_MSKCTRL_MGG_Pos                  (8UL)          /*!< MGG (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF0_MSKCTRL_MGG_Msk                  (0xff00UL)     /*!< MGG (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF0_MSKCTRL_MGR_Pos                  (16UL)         /*!< MGR (Bit 16)                                          */
+ #define R_LCDC_VI6_RPF0_MSKCTRL_MGR_Msk                  (0xff0000UL)   /*!< MGR (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF0_MSKCTRL_MSK_EN_Pos               (24UL)         /*!< MSK_EN (Bit 24)                                       */
+ #define R_LCDC_VI6_RPF0_MSKCTRL_MSK_EN_Msk               (0x1000000UL)  /*!< MSK_EN (Bitfield-Mask: 0x01)                          */
+/* ===================================================  VI6_RPF1_MSKCTRL  ==================================================== */
+ #define R_LCDC_VI6_RPF1_MSKCTRL_MGB_Pos                  (0UL)          /*!< MGB (Bit 0)                                           */
+ #define R_LCDC_VI6_RPF1_MSKCTRL_MGB_Msk                  (0xffUL)       /*!< MGB (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF1_MSKCTRL_MGG_Pos                  (8UL)          /*!< MGG (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF1_MSKCTRL_MGG_Msk                  (0xff00UL)     /*!< MGG (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF1_MSKCTRL_MGR_Pos                  (16UL)         /*!< MGR (Bit 16)                                          */
+ #define R_LCDC_VI6_RPF1_MSKCTRL_MGR_Msk                  (0xff0000UL)   /*!< MGR (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF1_MSKCTRL_MSK_EN_Pos               (24UL)         /*!< MSK_EN (Bit 24)                                       */
+ #define R_LCDC_VI6_RPF1_MSKCTRL_MSK_EN_Msk               (0x1000000UL)  /*!< MSK_EN (Bitfield-Mask: 0x01)                          */
+/* ===================================================  VI6_RPF0_MSKSET0  ==================================================== */
+ #define R_LCDC_VI6_RPF0_MSKSET0_MSB0_Pos                 (0UL)          /*!< MSB0 (Bit 0)                                          */
+ #define R_LCDC_VI6_RPF0_MSKSET0_MSB0_Msk                 (0xffUL)       /*!< MSB0 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_MSKSET0_MSG0_Pos                 (8UL)          /*!< MSG0 (Bit 8)                                          */
+ #define R_LCDC_VI6_RPF0_MSKSET0_MSG0_Msk                 (0xff00UL)     /*!< MSG0 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_MSKSET0_MSR0_Pos                 (16UL)         /*!< MSR0 (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF0_MSKSET0_MSR0_Msk                 (0xff0000UL)   /*!< MSR0 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_MSKSET0_MSA0_Pos                 (24UL)         /*!< MSA0 (Bit 24)                                         */
+ #define R_LCDC_VI6_RPF0_MSKSET0_MSA0_Msk                 (0xff000000UL) /*!< MSA0 (Bitfield-Mask: 0xff)                            */
+/* ===================================================  VI6_RPF1_MSKSET0  ==================================================== */
+ #define R_LCDC_VI6_RPF1_MSKSET0_MSB0_Pos                 (0UL)          /*!< MSB0 (Bit 0)                                          */
+ #define R_LCDC_VI6_RPF1_MSKSET0_MSB0_Msk                 (0xffUL)       /*!< MSB0 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_MSKSET0_MSG0_Pos                 (8UL)          /*!< MSG0 (Bit 8)                                          */
+ #define R_LCDC_VI6_RPF1_MSKSET0_MSG0_Msk                 (0xff00UL)     /*!< MSG0 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_MSKSET0_MSR0_Pos                 (16UL)         /*!< MSR0 (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF1_MSKSET0_MSR0_Msk                 (0xff0000UL)   /*!< MSR0 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_MSKSET0_MSA0_Pos                 (24UL)         /*!< MSA0 (Bit 24)                                         */
+ #define R_LCDC_VI6_RPF1_MSKSET0_MSA0_Msk                 (0xff000000UL) /*!< MSA0 (Bitfield-Mask: 0xff)                            */
+/* ===================================================  VI6_RPF0_MSKSET1  ==================================================== */
+ #define R_LCDC_VI6_RPF0_MSKSET1_MSB1_Pos                 (0UL)          /*!< MSB1 (Bit 0)                                          */
+ #define R_LCDC_VI6_RPF0_MSKSET1_MSB1_Msk                 (0xffUL)       /*!< MSB1 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_MSKSET1_MSG1_Pos                 (8UL)          /*!< MSG1 (Bit 8)                                          */
+ #define R_LCDC_VI6_RPF0_MSKSET1_MSG1_Msk                 (0xff00UL)     /*!< MSG1 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_MSKSET1_MSR1_Pos                 (16UL)         /*!< MSR1 (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF0_MSKSET1_MSR1_Msk                 (0xff0000UL)   /*!< MSR1 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF0_MSKSET1_MSA1_Pos                 (24UL)         /*!< MSA1 (Bit 24)                                         */
+ #define R_LCDC_VI6_RPF0_MSKSET1_MSA1_Msk                 (0xff000000UL) /*!< MSA1 (Bitfield-Mask: 0xff)                            */
+/* ===================================================  VI6_RPF1_MSKSET1  ==================================================== */
+ #define R_LCDC_VI6_RPF1_MSKSET1_MSB1_Pos                 (0UL)          /*!< MSB1 (Bit 0)                                          */
+ #define R_LCDC_VI6_RPF1_MSKSET1_MSB1_Msk                 (0xffUL)       /*!< MSB1 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_MSKSET1_MSG1_Pos                 (8UL)          /*!< MSG1 (Bit 8)                                          */
+ #define R_LCDC_VI6_RPF1_MSKSET1_MSG1_Msk                 (0xff00UL)     /*!< MSG1 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_MSKSET1_MSR1_Pos                 (16UL)         /*!< MSR1 (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF1_MSKSET1_MSR1_Msk                 (0xff0000UL)   /*!< MSR1 (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_RPF1_MSKSET1_MSA1_Pos                 (24UL)         /*!< MSA1 (Bit 24)                                         */
+ #define R_LCDC_VI6_RPF1_MSKSET1_MSA1_Msk                 (0xff000000UL) /*!< MSA1 (Bitfield-Mask: 0xff)                            */
+/* ==================================================  VI6_RPF0_CKEY_CTRL  =================================================== */
+ #define R_LCDC_VI6_RPF0_CKEY_CTRL_SAPE0_Pos              (0UL)          /*!< SAPE0 (Bit 0)                                         */
+ #define R_LCDC_VI6_RPF0_CKEY_CTRL_SAPE0_Msk              (0x1UL)        /*!< SAPE0 (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_CKEY_CTRL_SAPE1_Pos              (1UL)          /*!< SAPE1 (Bit 1)                                         */
+ #define R_LCDC_VI6_RPF0_CKEY_CTRL_SAPE1_Msk              (0x2UL)        /*!< SAPE1 (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF0_CKEY_CTRL_CV_Pos                 (4UL)          /*!< CV (Bit 4)                                            */
+ #define R_LCDC_VI6_RPF0_CKEY_CTRL_CV_Msk                 (0x10UL)       /*!< CV (Bitfield-Mask: 0x01)                              */
+ #define R_LCDC_VI6_RPF0_CKEY_CTRL_LTH_Pos                (8UL)          /*!< LTH (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF0_CKEY_CTRL_LTH_Msk                (0x100UL)      /*!< LTH (Bitfield-Mask: 0x01)                             */
+/* ==================================================  VI6_RPF1_CKEY_CTRL  =================================================== */
+ #define R_LCDC_VI6_RPF1_CKEY_CTRL_SAPE0_Pos              (0UL)          /*!< SAPE0 (Bit 0)                                         */
+ #define R_LCDC_VI6_RPF1_CKEY_CTRL_SAPE0_Msk              (0x1UL)        /*!< SAPE0 (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_CKEY_CTRL_SAPE1_Pos              (1UL)          /*!< SAPE1 (Bit 1)                                         */
+ #define R_LCDC_VI6_RPF1_CKEY_CTRL_SAPE1_Msk              (0x2UL)        /*!< SAPE1 (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_RPF1_CKEY_CTRL_CV_Pos                 (4UL)          /*!< CV (Bit 4)                                            */
+ #define R_LCDC_VI6_RPF1_CKEY_CTRL_CV_Msk                 (0x10UL)       /*!< CV (Bitfield-Mask: 0x01)                              */
+ #define R_LCDC_VI6_RPF1_CKEY_CTRL_LTH_Pos                (8UL)          /*!< LTH (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF1_CKEY_CTRL_LTH_Msk                (0x100UL)      /*!< LTH (Bitfield-Mask: 0x01)                             */
+/* ==================================================  VI6_RPF0_CKEY_SET0  =================================================== */
+ #define R_LCDC_VI6_RPF0_CKEY_SET0_B0_Pos                 (0UL)          /*!< B0 (Bit 0)                                            */
+ #define R_LCDC_VI6_RPF0_CKEY_SET0_B0_Msk                 (0xffUL)       /*!< B0 (Bitfield-Mask: 0xff)                              */
+ #define R_LCDC_VI6_RPF0_CKEY_SET0_GY0_Pos                (8UL)          /*!< GY0 (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF0_CKEY_SET0_GY0_Msk                (0xff00UL)     /*!< GY0 (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF0_CKEY_SET0_R0_Pos                 (16UL)         /*!< R0 (Bit 16)                                           */
+ #define R_LCDC_VI6_RPF0_CKEY_SET0_R0_Msk                 (0xff0000UL)   /*!< R0 (Bitfield-Mask: 0xff)                              */
+ #define R_LCDC_VI6_RPF0_CKEY_SET0_AP0_Pos                (24UL)         /*!< AP0 (Bit 24)                                          */
+ #define R_LCDC_VI6_RPF0_CKEY_SET0_AP0_Msk                (0xff000000UL) /*!< AP0 (Bitfield-Mask: 0xff)                             */
+/* ==================================================  VI6_RPF1_CKEY_SET0  =================================================== */
+ #define R_LCDC_VI6_RPF1_CKEY_SET0_B0_Pos                 (0UL)          /*!< B0 (Bit 0)                                            */
+ #define R_LCDC_VI6_RPF1_CKEY_SET0_B0_Msk                 (0xffUL)       /*!< B0 (Bitfield-Mask: 0xff)                              */
+ #define R_LCDC_VI6_RPF1_CKEY_SET0_GY0_Pos                (8UL)          /*!< GY0 (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF1_CKEY_SET0_GY0_Msk                (0xff00UL)     /*!< GY0 (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF1_CKEY_SET0_R0_Pos                 (16UL)         /*!< R0 (Bit 16)                                           */
+ #define R_LCDC_VI6_RPF1_CKEY_SET0_R0_Msk                 (0xff0000UL)   /*!< R0 (Bitfield-Mask: 0xff)                              */
+ #define R_LCDC_VI6_RPF1_CKEY_SET0_AP0_Pos                (24UL)         /*!< AP0 (Bit 24)                                          */
+ #define R_LCDC_VI6_RPF1_CKEY_SET0_AP0_Msk                (0xff000000UL) /*!< AP0 (Bitfield-Mask: 0xff)                             */
+/* ==================================================  VI6_RPF0_CKEY_SET1  =================================================== */
+ #define R_LCDC_VI6_RPF0_CKEY_SET1_B1_Pos                 (0UL)          /*!< B1 (Bit 0)                                            */
+ #define R_LCDC_VI6_RPF0_CKEY_SET1_B1_Msk                 (0xffUL)       /*!< B1 (Bitfield-Mask: 0xff)                              */
+ #define R_LCDC_VI6_RPF0_CKEY_SET1_GY1_Pos                (8UL)          /*!< GY1 (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF0_CKEY_SET1_GY1_Msk                (0xff00UL)     /*!< GY1 (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF0_CKEY_SET1_R1_Pos                 (16UL)         /*!< R1 (Bit 16)                                           */
+ #define R_LCDC_VI6_RPF0_CKEY_SET1_R1_Msk                 (0xff0000UL)   /*!< R1 (Bitfield-Mask: 0xff)                              */
+ #define R_LCDC_VI6_RPF0_CKEY_SET1_AP1_Pos                (24UL)         /*!< AP1 (Bit 24)                                          */
+ #define R_LCDC_VI6_RPF0_CKEY_SET1_AP1_Msk                (0xff000000UL) /*!< AP1 (Bitfield-Mask: 0xff)                             */
+/* ==================================================  VI6_RPF1_CKEY_SET1  =================================================== */
+ #define R_LCDC_VI6_RPF1_CKEY_SET1_B1_Pos                 (0UL)          /*!< B1 (Bit 0)                                            */
+ #define R_LCDC_VI6_RPF1_CKEY_SET1_B1_Msk                 (0xffUL)       /*!< B1 (Bitfield-Mask: 0xff)                              */
+ #define R_LCDC_VI6_RPF1_CKEY_SET1_GY1_Pos                (8UL)          /*!< GY1 (Bit 8)                                           */
+ #define R_LCDC_VI6_RPF1_CKEY_SET1_GY1_Msk                (0xff00UL)     /*!< GY1 (Bitfield-Mask: 0xff)                             */
+ #define R_LCDC_VI6_RPF1_CKEY_SET1_R1_Pos                 (16UL)         /*!< R1 (Bit 16)                                           */
+ #define R_LCDC_VI6_RPF1_CKEY_SET1_R1_Msk                 (0xff0000UL)   /*!< R1 (Bitfield-Mask: 0xff)                              */
+ #define R_LCDC_VI6_RPF1_CKEY_SET1_AP1_Pos                (24UL)         /*!< AP1 (Bit 24)                                          */
+ #define R_LCDC_VI6_RPF1_CKEY_SET1_AP1_Msk                (0xff000000UL) /*!< AP1 (Bitfield-Mask: 0xff)                             */
+/* =================================================  VI6_RPF0_SRCM_PSTRIDE  ================================================= */
+ #define R_LCDC_VI6_RPF0_SRCM_PSTRIDE_PICT_STRD_C_Pos     (0UL)          /*!< PICT_STRD_C (Bit 0)                                   */
+ #define R_LCDC_VI6_RPF0_SRCM_PSTRIDE_PICT_STRD_C_Msk     (0xffffUL)     /*!< PICT_STRD_C (Bitfield-Mask: 0xffff)                   */
+ #define R_LCDC_VI6_RPF0_SRCM_PSTRIDE_PICT_STRD_Y_Pos     (16UL)         /*!< PICT_STRD_Y (Bit 16)                                  */
+ #define R_LCDC_VI6_RPF0_SRCM_PSTRIDE_PICT_STRD_Y_Msk     (0xffff0000UL) /*!< PICT_STRD_Y (Bitfield-Mask: 0xffff)                   */
+/* =================================================  VI6_RPF1_SRCM_PSTRIDE  ================================================= */
+ #define R_LCDC_VI6_RPF1_SRCM_PSTRIDE_PICT_STRD_C_Pos     (0UL)          /*!< PICT_STRD_C (Bit 0)                                   */
+ #define R_LCDC_VI6_RPF1_SRCM_PSTRIDE_PICT_STRD_C_Msk     (0xffffUL)     /*!< PICT_STRD_C (Bitfield-Mask: 0xffff)                   */
+ #define R_LCDC_VI6_RPF1_SRCM_PSTRIDE_PICT_STRD_Y_Pos     (16UL)         /*!< PICT_STRD_Y (Bit 16)                                  */
+ #define R_LCDC_VI6_RPF1_SRCM_PSTRIDE_PICT_STRD_Y_Msk     (0xffff0000UL) /*!< PICT_STRD_Y (Bitfield-Mask: 0xffff)                   */
+/* =================================================  VI6_RPF0_SRCM_ASTRIDE  ================================================= */
+ #define R_LCDC_VI6_RPF0_SRCM_ASTRIDE_ALPH_STRD_Pos       (0UL)          /*!< ALPH_STRD (Bit 0)                                     */
+ #define R_LCDC_VI6_RPF0_SRCM_ASTRIDE_ALPH_STRD_Msk       (0xffffUL)     /*!< ALPH_STRD (Bitfield-Mask: 0xffff)                     */
+/* =================================================  VI6_RPF1_SRCM_ASTRIDE  ================================================= */
+ #define R_LCDC_VI6_RPF1_SRCM_ASTRIDE_ALPH_STRD_Pos       (0UL)          /*!< ALPH_STRD (Bit 0)                                     */
+ #define R_LCDC_VI6_RPF1_SRCM_ASTRIDE_ALPH_STRD_Msk       (0xffffUL)     /*!< ALPH_STRD (Bitfield-Mask: 0xffff)                     */
+/* =================================================  VI6_RPF0_SRCM_ADDR_Y  ================================================== */
+ #define R_LCDC_VI6_RPF0_SRCM_ADDR_Y_SRCM_ADDR_Y_Pos      (0UL)          /*!< SRCM_ADDR_Y (Bit 0)                                   */
+ #define R_LCDC_VI6_RPF0_SRCM_ADDR_Y_SRCM_ADDR_Y_Msk      (0xffffffffUL) /*!< SRCM_ADDR_Y (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  VI6_RPF1_SRCM_ADDR_Y  ================================================== */
+ #define R_LCDC_VI6_RPF1_SRCM_ADDR_Y_SRCM_ADDR_Y_Pos      (0UL)          /*!< SRCM_ADDR_Y (Bit 0)                                   */
+ #define R_LCDC_VI6_RPF1_SRCM_ADDR_Y_SRCM_ADDR_Y_Msk      (0xffffffffUL) /*!< SRCM_ADDR_Y (Bitfield-Mask: 0xffffffff)               */
+/* =================================================  VI6_RPF0_SRCM_ADDR_C0  ================================================= */
+ #define R_LCDC_VI6_RPF0_SRCM_ADDR_C0_SRCM_ADDR_C0_Pos    (0UL)          /*!< SRCM_ADDR_C0 (Bit 0)                                  */
+ #define R_LCDC_VI6_RPF0_SRCM_ADDR_C0_SRCM_ADDR_C0_Msk    (0xffffffffUL) /*!< SRCM_ADDR_C0 (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VI6_RPF1_SRCM_ADDR_C0  ================================================= */
+ #define R_LCDC_VI6_RPF1_SRCM_ADDR_C0_SRCM_ADDR_C0_Pos    (0UL)          /*!< SRCM_ADDR_C0 (Bit 0)                                  */
+ #define R_LCDC_VI6_RPF1_SRCM_ADDR_C0_SRCM_ADDR_C0_Msk    (0xffffffffUL) /*!< SRCM_ADDR_C0 (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VI6_RPF0_SRCM_ADDR_C1  ================================================= */
+ #define R_LCDC_VI6_RPF0_SRCM_ADDR_C1_SRCM_ADDR_C1_Pos    (0UL)          /*!< SRCM_ADDR_C1 (Bit 0)                                  */
+ #define R_LCDC_VI6_RPF0_SRCM_ADDR_C1_SRCM_ADDR_C1_Msk    (0xffffffffUL) /*!< SRCM_ADDR_C1 (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VI6_RPF1_SRCM_ADDR_C1  ================================================= */
+ #define R_LCDC_VI6_RPF1_SRCM_ADDR_C1_SRCM_ADDR_C1_Pos    (0UL)          /*!< SRCM_ADDR_C1 (Bit 0)                                  */
+ #define R_LCDC_VI6_RPF1_SRCM_ADDR_C1_SRCM_ADDR_C1_Msk    (0xffffffffUL) /*!< SRCM_ADDR_C1 (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VI6_RPF0_SRCM_ADDR_AI  ================================================= */
+ #define R_LCDC_VI6_RPF0_SRCM_ADDR_AI_SRCM_ADDR_AI_Pos    (0UL)          /*!< SRCM_ADDR_AI (Bit 0)                                  */
+ #define R_LCDC_VI6_RPF0_SRCM_ADDR_AI_SRCM_ADDR_AI_Msk    (0xffffffffUL) /*!< SRCM_ADDR_AI (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VI6_RPF1_SRCM_ADDR_AI  ================================================= */
+ #define R_LCDC_VI6_RPF1_SRCM_ADDR_AI_SRCM_ADDR_AI_Pos    (0UL)          /*!< SRCM_ADDR_AI (Bit 0)                                  */
+ #define R_LCDC_VI6_RPF1_SRCM_ADDR_AI_SRCM_ADDR_AI_Msk    (0xffffffffUL) /*!< SRCM_ADDR_AI (Bitfield-Mask: 0xffffffff)             */
+/* =====================================================  VI6_RPF0_BAC  ====================================================== */
+ #define R_LCDC_VI6_RPF0_BAC_B512_Pos                     (16UL)         /*!< B512 (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF0_BAC_B512_Msk                     (0x10000UL)    /*!< B512 (Bitfield-Mask: 0x01)                            */
+/* =====================================================  VI6_RPF1_BAC  ====================================================== */
+ #define R_LCDC_VI6_RPF1_BAC_B512_Pos                     (16UL)         /*!< B512 (Bit 16)                                         */
+ #define R_LCDC_VI6_RPF1_BAC_B512_Msk                     (0x10000UL)    /*!< B512 (Bitfield-Mask: 0x01)                            */
+/* ==================================================  VI6_RPF0_MULT_ALPH  =================================================== */
+ #define R_LCDC_VI6_RPF0_MULT_ALPH_ALPHA_RATIO_Pos        (0UL)          /*!< ALPHA_RATIO (Bit 0)                                   */
+ #define R_LCDC_VI6_RPF0_MULT_ALPH_ALPHA_RATIO_Msk        (0xffUL)       /*!< ALPHA_RATIO (Bitfield-Mask: 0xff)                     */
+ #define R_LCDC_VI6_RPF0_MULT_ALPH_P_MMD_Pos              (8UL)          /*!< P_MMD (Bit 8)                                         */
+ #define R_LCDC_VI6_RPF0_MULT_ALPH_P_MMD_Msk              (0x300UL)      /*!< P_MMD (Bitfield-Mask: 0x03)                           */
+ #define R_LCDC_VI6_RPF0_MULT_ALPH_A_MMD_Pos              (12UL)         /*!< A_MMD (Bit 12)                                        */
+ #define R_LCDC_VI6_RPF0_MULT_ALPH_A_MMD_Msk              (0x1000UL)     /*!< A_MMD (Bitfield-Mask: 0x01)                           */
+/* ==================================================  VI6_RPF1_MULT_ALPH  =================================================== */
+ #define R_LCDC_VI6_RPF1_MULT_ALPH_ALPHA_RATIO_Pos        (0UL)          /*!< ALPHA_RATIO (Bit 0)                                   */
+ #define R_LCDC_VI6_RPF1_MULT_ALPH_ALPHA_RATIO_Msk        (0xffUL)       /*!< ALPHA_RATIO (Bitfield-Mask: 0xff)                     */
+ #define R_LCDC_VI6_RPF1_MULT_ALPH_P_MMD_Pos              (8UL)          /*!< P_MMD (Bit 8)                                         */
+ #define R_LCDC_VI6_RPF1_MULT_ALPH_P_MMD_Msk              (0x300UL)      /*!< P_MMD (Bitfield-Mask: 0x03)                           */
+ #define R_LCDC_VI6_RPF1_MULT_ALPH_A_MMD_Pos              (12UL)         /*!< A_MMD (Bit 12)                                        */
+ #define R_LCDC_VI6_RPF1_MULT_ALPH_A_MMD_Msk              (0x1000UL)     /*!< A_MMD (Bitfield-Mask: 0x01)                           */
+/* ====================================================  VI6_WPF0_SRCRPF  ==================================================== */
+ #define R_LCDC_VI6_WPF0_SRCRPF_RPF0_ACT_Pos              (0UL)          /*!< RPF0_ACT (Bit 0)                                      */
+ #define R_LCDC_VI6_WPF0_SRCRPF_RPF0_ACT_Msk              (0x3UL)        /*!< RPF0_ACT (Bitfield-Mask: 0x03)                        */
+ #define R_LCDC_VI6_WPF0_SRCRPF_RPF1_ACT_Pos              (2UL)          /*!< RPF1_ACT (Bit 2)                                      */
+ #define R_LCDC_VI6_WPF0_SRCRPF_RPF1_ACT_Msk              (0xcUL)        /*!< RPF1_ACT (Bitfield-Mask: 0x03)                        */
+ #define R_LCDC_VI6_WPF0_SRCRPF_VIR_ACT2_Pos              (24UL)         /*!< VIR_ACT2 (Bit 24)                                     */
+ #define R_LCDC_VI6_WPF0_SRCRPF_VIR_ACT2_Msk              (0x3000000UL)  /*!< VIR_ACT2 (Bitfield-Mask: 0x03)                        */
+/* ===================================================  VI6_WPF0_HSZCLIP  ==================================================== */
+ #define R_LCDC_VI6_WPF0_HSZCLIP_HCL_SIZE_Pos             (0UL)          /*!< HCL_SIZE (Bit 0)                                      */
+ #define R_LCDC_VI6_WPF0_HSZCLIP_HCL_SIZE_Msk             (0x1fffUL)     /*!< HCL_SIZE (Bitfield-Mask: 0x1fff)                      */
+ #define R_LCDC_VI6_WPF0_HSZCLIP_HCL_OFST_Pos             (16UL)         /*!< HCL_OFST (Bit 16)                                     */
+ #define R_LCDC_VI6_WPF0_HSZCLIP_HCL_OFST_Msk             (0xff0000UL)   /*!< HCL_OFST (Bitfield-Mask: 0xff)                        */
+ #define R_LCDC_VI6_WPF0_HSZCLIP_HCEN_Pos                 (28UL)         /*!< HCEN (Bit 28)                                         */
+ #define R_LCDC_VI6_WPF0_HSZCLIP_HCEN_Msk                 (0x10000000UL) /*!< HCEN (Bitfield-Mask: 0x01)                            */
+/* ===================================================  VI6_WPF0_VSZCLIP  ==================================================== */
+ #define R_LCDC_VI6_WPF0_VSZCLIP_VCL_SIZE_Pos             (0UL)          /*!< VCL_SIZE (Bit 0)                                      */
+ #define R_LCDC_VI6_WPF0_VSZCLIP_VCL_SIZE_Msk             (0x1fffUL)     /*!< VCL_SIZE (Bitfield-Mask: 0x1fff)                      */
+ #define R_LCDC_VI6_WPF0_VSZCLIP_VCL_OFST_Pos             (16UL)         /*!< VCL_OFST (Bit 16)                                     */
+ #define R_LCDC_VI6_WPF0_VSZCLIP_VCL_OFST_Msk             (0xff0000UL)   /*!< VCL_OFST (Bitfield-Mask: 0xff)                        */
+ #define R_LCDC_VI6_WPF0_VSZCLIP_VCEN_Pos                 (28UL)         /*!< VCEN (Bit 28)                                         */
+ #define R_LCDC_VI6_WPF0_VSZCLIP_VCEN_Msk                 (0x10000000UL) /*!< VCEN (Bitfield-Mask: 0x01)                            */
+/* ====================================================  VI6_WPF0_OUTFMT  ==================================================== */
+ #define R_LCDC_VI6_WPF0_OUTFMT_WRFMT_Pos                 (0UL)          /*!< WRFMT (Bit 0)                                         */
+ #define R_LCDC_VI6_WPF0_OUTFMT_WRFMT_Msk                 (0x7fUL)       /*!< WRFMT (Bitfield-Mask: 0x7f)                           */
+ #define R_LCDC_VI6_WPF0_OUTFMT_CSC_Pos                   (8UL)          /*!< CSC (Bit 8)                                           */
+ #define R_LCDC_VI6_WPF0_OUTFMT_CSC_Msk                   (0x100UL)      /*!< CSC (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_WPF0_OUTFMT_WRTM_Pos                  (9UL)          /*!< WRTM (Bit 9)                                          */
+ #define R_LCDC_VI6_WPF0_OUTFMT_WRTM_Msk                  (0xe00UL)      /*!< WRTM (Bitfield-Mask: 0x07)                            */
+ #define R_LCDC_VI6_WPF0_OUTFMT_DITH_Pos                  (12UL)         /*!< DITH (Bit 12)                                         */
+ #define R_LCDC_VI6_WPF0_OUTFMT_DITH_Msk                  (0x3000UL)     /*!< DITH (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_VI6_WPF0_OUTFMT_SPUVS_Pos                 (14UL)         /*!< SPUVS (Bit 14)                                        */
+ #define R_LCDC_VI6_WPF0_OUTFMT_SPUVS_Msk                 (0x4000UL)     /*!< SPUVS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_WPF0_OUTFMT_SPYCS_Pos                 (15UL)         /*!< SPYCS (Bit 15)                                        */
+ #define R_LCDC_VI6_WPF0_OUTFMT_SPYCS_Msk                 (0x8000UL)     /*!< SPYCS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_WPF0_OUTFMT_ROT_Pos                   (16UL)         /*!< ROT (Bit 16)                                          */
+ #define R_LCDC_VI6_WPF0_OUTFMT_ROT_Msk                   (0x70000UL)    /*!< ROT (Bitfield-Mask: 0x07)                             */
+ #define R_LCDC_VI6_WPF0_OUTFMT_ODE_Pos                   (22UL)         /*!< ODE (Bit 22)                                          */
+ #define R_LCDC_VI6_WPF0_OUTFMT_ODE_Msk                   (0x400000UL)   /*!< ODE (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_WPF0_OUTFMT_PXA_Pos                   (23UL)         /*!< PXA (Bit 23)                                          */
+ #define R_LCDC_VI6_WPF0_OUTFMT_PXA_Msk                   (0x800000UL)   /*!< PXA (Bitfield-Mask: 0x01)                             */
+ #define R_LCDC_VI6_WPF0_OUTFMT_PDV_Pos                   (24UL)         /*!< PDV (Bit 24)                                          */
+ #define R_LCDC_VI6_WPF0_OUTFMT_PDV_Msk                   (0xff000000UL) /*!< PDV (Bitfield-Mask: 0xff)                             */
+/* ====================================================  VI6_WPF0_DSWAP  ===================================================== */
+ #define R_LCDC_VI6_WPF0_DSWAP_P_BTS_Pos                  (0UL)          /*!< P_BTS (Bit 0)                                         */
+ #define R_LCDC_VI6_WPF0_DSWAP_P_BTS_Msk                  (0x1UL)        /*!< P_BTS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_WPF0_DSWAP_P_WDS_Pos                  (1UL)          /*!< P_WDS (Bit 1)                                         */
+ #define R_LCDC_VI6_WPF0_DSWAP_P_WDS_Msk                  (0x2UL)        /*!< P_WDS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_WPF0_DSWAP_P_LWS_Pos                  (2UL)          /*!< P_LWS (Bit 2)                                         */
+ #define R_LCDC_VI6_WPF0_DSWAP_P_LWS_Msk                  (0x4UL)        /*!< P_LWS (Bitfield-Mask: 0x01)                           */
+ #define R_LCDC_VI6_WPF0_DSWAP_P_LLS_Pos                  (3UL)          /*!< P_LLS (Bit 3)                                         */
+ #define R_LCDC_VI6_WPF0_DSWAP_P_LLS_Msk                  (0x8UL)        /*!< P_LLS (Bitfield-Mask: 0x01)                           */
+/* ===================================================  VI6_WPF0_RNDCTRL  ==================================================== */
+ #define R_LCDC_VI6_WPF0_RNDCTRL_CLMD_Pos                 (12UL)         /*!< CLMD (Bit 12)                                         */
+ #define R_LCDC_VI6_WPF0_RNDCTRL_CLMD_Msk                 (0x3000UL)     /*!< CLMD (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_VI6_WPF0_RNDCTRL_ATHRESH_Pos              (16UL)         /*!< ATHRESH (Bit 16)                                      */
+ #define R_LCDC_VI6_WPF0_RNDCTRL_ATHRESH_Msk              (0xff0000UL)   /*!< ATHRESH (Bitfield-Mask: 0xff)                         */
+ #define R_LCDC_VI6_WPF0_RNDCTRL_ABRM_Pos                 (24UL)         /*!< ABRM (Bit 24)                                         */
+ #define R_LCDC_VI6_WPF0_RNDCTRL_ABRM_Msk                 (0x3000000UL)  /*!< ABRM (Bitfield-Mask: 0x03)                            */
+ #define R_LCDC_VI6_WPF0_RNDCTRL_CBRM_Pos                 (28UL)         /*!< CBRM (Bit 28)                                         */
+ #define R_LCDC_VI6_WPF0_RNDCTRL_CBRM_Msk                 (0x10000000UL) /*!< CBRM (Bitfield-Mask: 0x01)                            */
+/* ================================================  VI6_WPF0_DSTM_STRIDE_Y  ================================================= */
+ #define R_LCDC_VI6_WPF0_DSTM_STRIDE_Y_PICT_STRD_Y_Pos    (0UL)          /*!< PICT_STRD_Y (Bit 0)                                   */
+ #define R_LCDC_VI6_WPF0_DSTM_STRIDE_Y_PICT_STRD_Y_Msk    (0xffffUL)     /*!< PICT_STRD_Y (Bitfield-Mask: 0xffff)                   */
+/* ================================================  VI6_WPF0_DSTM_STRIDE_C  ================================================= */
+ #define R_LCDC_VI6_WPF0_DSTM_STRIDE_C_PICT_STRD_C_Pos    (0UL)          /*!< PICT_STRD_C (Bit 0)                                   */
+ #define R_LCDC_VI6_WPF0_DSTM_STRIDE_C_PICT_STRD_C_Msk    (0xffffUL)     /*!< PICT_STRD_C (Bitfield-Mask: 0xffff)                   */
+/* =================================================  VI6_WPF0_DSTM_ADDR_C0  ================================================= */
+ #define R_LCDC_VI6_WPF0_DSTM_ADDR_C0_DSTM_ADDR_C0_Pos    (0UL)          /*!< DSTM_ADDR_C0 (Bit 0)                                  */
+ #define R_LCDC_VI6_WPF0_DSTM_ADDR_C0_DSTM_ADDR_C0_Msk    (0xffffffffUL) /*!< DSTM_ADDR_C0 (Bitfield-Mask: 0xffffffff)             */
+/* =================================================  VI6_WPF0_DSTM_ADDR_C1  ================================================= */
+ #define R_LCDC_VI6_WPF0_DSTM_ADDR_C1_DSTM_ADDR_C1_Pos    (0UL)          /*!< DSTM_ADDR_C1 (Bit 0)                                  */
+ #define R_LCDC_VI6_WPF0_DSTM_ADDR_C1_DSTM_ADDR_C1_Msk    (0xffffffffUL) /*!< DSTM_ADDR_C1 (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  VI6_WPF0_WRBCK_CTRL  ================================================== */
+ #define R_LCDC_VI6_WPF0_WRBCK_CTRL_WBMD_Pos              (0UL)          /*!< WBMD (Bit 0)                                          */
+ #define R_LCDC_VI6_WPF0_WRBCK_CTRL_WBMD_Msk              (0x3UL)        /*!< WBMD (Bitfield-Mask: 0x03)                            */
+/* ==================================================  VI6_DPR_RPF0_ROUTE  =================================================== */
+ #define R_LCDC_VI6_DPR_RPF0_ROUTE_RT_RPF0_Pos            (0UL)          /*!< RT_RPF0 (Bit 0)                                       */
+ #define R_LCDC_VI6_DPR_RPF0_ROUTE_RT_RPF0_Msk            (0x3fUL)       /*!< RT_RPF0 (Bitfield-Mask: 0x3f)                         */
+/* ==================================================  VI6_DPR_RPF1_ROUTE  =================================================== */
+ #define R_LCDC_VI6_DPR_RPF1_ROUTE_RT_RPF1_Pos            (0UL)          /*!< RT_RPF1 (Bit 0)                                       */
+ #define R_LCDC_VI6_DPR_RPF1_ROUTE_RT_RPF1_Msk            (0x3fUL)       /*!< RT_RPF1 (Bitfield-Mask: 0x3f)                         */
+/* ==================================================  VI6_DPR_WPF0_FPORCH  ================================================== */
+ #define R_LCDC_VI6_DPR_WPF0_FPORCH_FP_WPF0_Pos           (8UL)          /*!< FP_WPF0 (Bit 8)                                       */
+ #define R_LCDC_VI6_DPR_WPF0_FPORCH_FP_WPF0_Msk           (0x3f00UL)     /*!< FP_WPF0 (Bitfield-Mask: 0x3f)                         */
+/* ===================================================  VI6_DPR_LUT_ROUTE  =================================================== */
+ #define R_LCDC_VI6_DPR_LUT_ROUTE_RT_Pos                  (0UL)          /*!< RT (Bit 0)                                            */
+ #define R_LCDC_VI6_DPR_LUT_ROUTE_RT_Msk                  (0x3fUL)       /*!< RT (Bitfield-Mask: 0x3f)                              */
+ #define R_LCDC_VI6_DPR_LUT_ROUTE_FP_Pos                  (8UL)          /*!< FP (Bit 8)                                            */
+ #define R_LCDC_VI6_DPR_LUT_ROUTE_FP_Msk                  (0x3f00UL)     /*!< FP (Bitfield-Mask: 0x3f)                              */
+ #define R_LCDC_VI6_DPR_LUT_ROUTE_FXA_Pos                 (16UL)         /*!< FXA (Bit 16)                                          */
+ #define R_LCDC_VI6_DPR_LUT_ROUTE_FXA_Msk                 (0xff0000UL)   /*!< FXA (Bitfield-Mask: 0xff)                             */
+/* ===================================================  VI6_DPR_BRS_ROUTE  =================================================== */
+ #define R_LCDC_VI6_DPR_BRS_ROUTE_RT_Pos                  (0UL)          /*!< RT (Bit 0)                                            */
+ #define R_LCDC_VI6_DPR_BRS_ROUTE_RT_Msk                  (0x3fUL)       /*!< RT (Bitfield-Mask: 0x3f)                              */
+ #define R_LCDC_VI6_DPR_BRS_ROUTE_FP_Pos                  (8UL)          /*!< FP (Bit 8)                                            */
+ #define R_LCDC_VI6_DPR_BRS_ROUTE_FP_Msk                  (0x3f00UL)     /*!< FP (Bitfield-Mask: 0x3f)                              */
+ #define R_LCDC_VI6_DPR_BRS_ROUTE_BRSSEL_Pos              (28UL)         /*!< BRSSEL (Bit 28)                                       */
+ #define R_LCDC_VI6_DPR_BRS_ROUTE_BRSSEL_Msk              (0x10000000UL) /*!< BRSSEL (Bitfield-Mask: 0x01)                          */
+/* =====================================================  VI6_LUT_CTRL  ====================================================== */
+ #define R_LCDC_VI6_LUT_CTRL_LUT_EN_Pos                   (0UL)          /*!< LUT_EN (Bit 0)                                        */
+ #define R_LCDC_VI6_LUT_CTRL_LUT_EN_Msk                   (0x1UL)        /*!< LUT_EN (Bitfield-Mask: 0x01)                          */
+/* ====================================================  VI6_BRS_INCTRL  ===================================================== */
+ #define R_LCDC_VI6_BRS_INCTRL_DITH0_Pos                  (0UL)          /*!< DITH0 (Bit 0)                                         */
+ #define R_LCDC_VI6_BRS_INCTRL_DITH0_Msk                  (0x7UL)        /*!< DITH0 (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRS_INCTRL_ODE0_Pos                   (3UL)          /*!< ODE0 (Bit 3)                                          */
+ #define R_LCDC_VI6_BRS_INCTRL_ODE0_Msk                   (0x8UL)        /*!< ODE0 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_BRS_INCTRL_DITH1_Pos                  (4UL)          /*!< DITH1 (Bit 4)                                         */
+ #define R_LCDC_VI6_BRS_INCTRL_DITH1_Msk                  (0x70UL)       /*!< DITH1 (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRS_INCTRL_ODE1_Pos                   (7UL)          /*!< ODE1 (Bit 7)                                          */
+ #define R_LCDC_VI6_BRS_INCTRL_ODE1_Msk                   (0x80UL)       /*!< ODE1 (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_BRS_INCTRL_D0ON_Pos                   (16UL)         /*!< D0ON (Bit 16)                                         */
+ #define R_LCDC_VI6_BRS_INCTRL_D0ON_Msk                   (0x10000UL)    /*!< D0ON (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_BRS_INCTRL_D1ON_Pos                   (17UL)         /*!< D1ON (Bit 17)                                         */
+ #define R_LCDC_VI6_BRS_INCTRL_D1ON_Msk                   (0x20000UL)    /*!< D1ON (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_BRS_INCTRL_NRM_Pos                    (28UL)         /*!< NRM (Bit 28)                                          */
+ #define R_LCDC_VI6_BRS_INCTRL_NRM_Msk                    (0x10000000UL) /*!< NRM (Bitfield-Mask: 0x01)                             */
+/* ==================================================  VI6_BRS_VIRRPF_SIZE  ================================================== */
+ #define R_LCDC_VI6_BRS_VIRRPF_SIZE_VIR_VSIZE_Pos         (0UL)          /*!< VIR_VSIZE (Bit 0)                                     */
+ #define R_LCDC_VI6_BRS_VIRRPF_SIZE_VIR_VSIZE_Msk         (0x1fffUL)     /*!< VIR_VSIZE (Bitfield-Mask: 0x1fff)                     */
+ #define R_LCDC_VI6_BRS_VIRRPF_SIZE_VIR_HSIZE_Pos         (16UL)         /*!< VIR_HSIZE (Bit 16)                                    */
+ #define R_LCDC_VI6_BRS_VIRRPF_SIZE_VIR_HSIZE_Msk         (0x1fff0000UL) /*!< VIR_HSIZE (Bitfield-Mask: 0x1fff)                     */
+/* ==================================================  VI6_BRS_VIRRPF_LOC  =================================================== */
+ #define R_LCDC_VI6_BRS_VIRRPF_LOC_VCOORD_Pos             (0UL)          /*!< VCOORD (Bit 0)                                        */
+ #define R_LCDC_VI6_BRS_VIRRPF_LOC_VCOORD_Msk             (0x1fffUL)     /*!< VCOORD (Bitfield-Mask: 0x1fff)                        */
+ #define R_LCDC_VI6_BRS_VIRRPF_LOC_HCOORD_Pos             (16UL)         /*!< HCOORD (Bit 16)                                       */
+ #define R_LCDC_VI6_BRS_VIRRPF_LOC_HCOORD_Msk             (0x1fff0000UL) /*!< HCOORD (Bitfield-Mask: 0x1fff)                        */
+/* ==================================================  VI6_BRS_VIRRPF_COL  =================================================== */
+ #define R_LCDC_VI6_BRS_VIRRPF_COL_COL_BCB_Pos            (0UL)          /*!< COL_BCB (Bit 0)                                       */
+ #define R_LCDC_VI6_BRS_VIRRPF_COL_COL_BCB_Msk            (0xffUL)       /*!< COL_BCB (Bitfield-Mask: 0xff)                         */
+ #define R_LCDC_VI6_BRS_VIRRPF_COL_COL_GY_Pos             (8UL)          /*!< COL_GY (Bit 8)                                        */
+ #define R_LCDC_VI6_BRS_VIRRPF_COL_COL_GY_Msk             (0xff00UL)     /*!< COL_GY (Bitfield-Mask: 0xff)                          */
+ #define R_LCDC_VI6_BRS_VIRRPF_COL_COL_RCR_Pos            (16UL)         /*!< COL_RCR (Bit 16)                                      */
+ #define R_LCDC_VI6_BRS_VIRRPF_COL_COL_RCR_Msk            (0xff0000UL)   /*!< COL_RCR (Bitfield-Mask: 0xff)                         */
+ #define R_LCDC_VI6_BRS_VIRRPF_COL_COL_A_Pos              (24UL)         /*!< COL_A (Bit 24)                                        */
+ #define R_LCDC_VI6_BRS_VIRRPF_COL_COL_A_Msk              (0xff000000UL) /*!< COL_A (Bitfield-Mask: 0xff)                           */
+/* =====================================================  VI6_BRSA_CTRL  ===================================================== */
+ #define R_LCDC_VI6_BRSA_CTRL_AROP_Pos                    (0UL)          /*!< AROP (Bit 0)                                          */
+ #define R_LCDC_VI6_BRSA_CTRL_AROP_Msk                    (0xfUL)        /*!< AROP (Bitfield-Mask: 0x0f)                            */
+ #define R_LCDC_VI6_BRSA_CTRL_CROP_Pos                    (4UL)          /*!< CROP (Bit 4)                                          */
+ #define R_LCDC_VI6_BRSA_CTRL_CROP_Msk                    (0xf0UL)       /*!< CROP (Bitfield-Mask: 0x0f)                            */
+ #define R_LCDC_VI6_BRSA_CTRL_SRCSEL_Pos                  (16UL)         /*!< SRCSEL (Bit 16)                                       */
+ #define R_LCDC_VI6_BRSA_CTRL_SRCSEL_Msk                  (0x70000UL)    /*!< SRCSEL (Bitfield-Mask: 0x07)                          */
+ #define R_LCDC_VI6_BRSA_CTRL_DSTSEL_Pos                  (20UL)         /*!< DSTSEL (Bit 20)                                       */
+ #define R_LCDC_VI6_BRSA_CTRL_DSTSEL_Msk                  (0x700000UL)   /*!< DSTSEL (Bitfield-Mask: 0x07)                          */
+ #define R_LCDC_VI6_BRSA_CTRL_RBC_Pos                     (31UL)         /*!< RBC (Bit 31)                                          */
+ #define R_LCDC_VI6_BRSA_CTRL_RBC_Msk                     (0x80000000UL) /*!< RBC (Bitfield-Mask: 0x01)                             */
+/* =====================================================  VI6_BRSA_BLD  ====================================================== */
+ #define R_LCDC_VI6_BRSA_BLD_COEFY_Pos                    (0UL)          /*!< COEFY (Bit 0)                                         */
+ #define R_LCDC_VI6_BRSA_BLD_COEFY_Msk                    (0xffUL)       /*!< COEFY (Bitfield-Mask: 0xff)                           */
+ #define R_LCDC_VI6_BRSA_BLD_COEFX_Pos                    (8UL)          /*!< COEFX (Bit 8)                                         */
+ #define R_LCDC_VI6_BRSA_BLD_COEFX_Msk                    (0xff00UL)     /*!< COEFX (Bitfield-Mask: 0xff)                           */
+ #define R_LCDC_VI6_BRSA_BLD_ACMDY_Pos                    (16UL)         /*!< ACMDY (Bit 16)                                        */
+ #define R_LCDC_VI6_BRSA_BLD_ACMDY_Msk                    (0x70000UL)    /*!< ACMDY (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRSA_BLD_ACMDX_Pos                    (20UL)         /*!< ACMDX (Bit 20)                                        */
+ #define R_LCDC_VI6_BRSA_BLD_ACMDX_Msk                    (0x700000UL)   /*!< ACMDX (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRSA_BLD_ABES_Pos                     (23UL)         /*!< ABES (Bit 23)                                         */
+ #define R_LCDC_VI6_BRSA_BLD_ABES_Msk                     (0x800000UL)   /*!< ABES (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_BRSA_BLD_CCMDY_Pos                    (24UL)         /*!< CCMDY (Bit 24)                                        */
+ #define R_LCDC_VI6_BRSA_BLD_CCMDY_Msk                    (0x7000000UL)  /*!< CCMDY (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRSA_BLD_CCMDX_Pos                    (28UL)         /*!< CCMDX (Bit 28)                                        */
+ #define R_LCDC_VI6_BRSA_BLD_CCMDX_Msk                    (0x70000000UL) /*!< CCMDX (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRSA_BLD_CBES_Pos                     (31UL)         /*!< CBES (Bit 31)                                         */
+ #define R_LCDC_VI6_BRSA_BLD_CBES_Msk                     (0x80000000UL) /*!< CBES (Bitfield-Mask: 0x01)                            */
+/* =====================================================  VI6_BRSB_CTRL  ===================================================== */
+ #define R_LCDC_VI6_BRSB_CTRL_AROP_Pos                    (0UL)          /*!< AROP (Bit 0)                                          */
+ #define R_LCDC_VI6_BRSB_CTRL_AROP_Msk                    (0xfUL)        /*!< AROP (Bitfield-Mask: 0x0f)                            */
+ #define R_LCDC_VI6_BRSB_CTRL_CROP_Pos                    (4UL)          /*!< CROP (Bit 4)                                          */
+ #define R_LCDC_VI6_BRSB_CTRL_CROP_Msk                    (0xf0UL)       /*!< CROP (Bitfield-Mask: 0x0f)                            */
+ #define R_LCDC_VI6_BRSB_CTRL_RBC_Pos                     (31UL)         /*!< RBC (Bit 31)                                          */
+ #define R_LCDC_VI6_BRSB_CTRL_RBC_Msk                     (0x80000000UL) /*!< RBC (Bitfield-Mask: 0x01)                             */
+/* =====================================================  VI6_BRSB_BLD  ====================================================== */
+ #define R_LCDC_VI6_BRSB_BLD_COEFY_Pos                    (0UL)          /*!< COEFY (Bit 0)                                         */
+ #define R_LCDC_VI6_BRSB_BLD_COEFY_Msk                    (0xffUL)       /*!< COEFY (Bitfield-Mask: 0xff)                           */
+ #define R_LCDC_VI6_BRSB_BLD_COEFX_Pos                    (8UL)          /*!< COEFX (Bit 8)                                         */
+ #define R_LCDC_VI6_BRSB_BLD_COEFX_Msk                    (0xff00UL)     /*!< COEFX (Bitfield-Mask: 0xff)                           */
+ #define R_LCDC_VI6_BRSB_BLD_ACMDY_Pos                    (16UL)         /*!< ACMDY (Bit 16)                                        */
+ #define R_LCDC_VI6_BRSB_BLD_ACMDY_Msk                    (0x70000UL)    /*!< ACMDY (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRSB_BLD_ACMDX_Pos                    (20UL)         /*!< ACMDX (Bit 20)                                        */
+ #define R_LCDC_VI6_BRSB_BLD_ACMDX_Msk                    (0x700000UL)   /*!< ACMDX (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRSB_BLD_ABES_Pos                     (23UL)         /*!< ABES (Bit 23)                                         */
+ #define R_LCDC_VI6_BRSB_BLD_ABES_Msk                     (0x800000UL)   /*!< ABES (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_BRSB_BLD_CCMDY_Pos                    (24UL)         /*!< CCMDY (Bit 24)                                        */
+ #define R_LCDC_VI6_BRSB_BLD_CCMDY_Msk                    (0x7000000UL)  /*!< CCMDY (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRSB_BLD_CCMDX_Pos                    (28UL)         /*!< CCMDX (Bit 28)                                        */
+ #define R_LCDC_VI6_BRSB_BLD_CCMDX_Msk                    (0x70000000UL) /*!< CCMDX (Bitfield-Mask: 0x07)                           */
+ #define R_LCDC_VI6_BRSB_BLD_CBES_Pos                     (31UL)         /*!< CBES (Bit 31)                                         */
+ #define R_LCDC_VI6_BRSB_BLD_CBES_Msk                     (0x80000000UL) /*!< CBES (Bitfield-Mask: 0x01)                            */
+/* =====================================================  VI6_LIF0_CTRL  ===================================================== */
+ #define R_LCDC_VI6_LIF0_CTRL_LIF_EN_Pos                  (0UL)          /*!< LIF_EN (Bit 0)                                        */
+ #define R_LCDC_VI6_LIF0_CTRL_LIF_EN_Msk                  (0x1UL)        /*!< LIF_EN (Bitfield-Mask: 0x01)                          */
+ #define R_LCDC_VI6_LIF0_CTRL_REQSEL_Pos                  (1UL)          /*!< REQSEL (Bit 1)                                        */
+ #define R_LCDC_VI6_LIF0_CTRL_REQSEL_Msk                  (0x2UL)        /*!< REQSEL (Bitfield-Mask: 0x01)                          */
+ #define R_LCDC_VI6_LIF0_CTRL_CFMT_Pos                    (4UL)          /*!< CFMT (Bit 4)                                          */
+ #define R_LCDC_VI6_LIF0_CTRL_CFMT_Msk                    (0x10UL)       /*!< CFMT (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_LIF0_CTRL_PADL_Pos                    (8UL)          /*!< PADL (Bit 8)                                          */
+ #define R_LCDC_VI6_LIF0_CTRL_PADL_Msk                    (0x100UL)      /*!< PADL (Bitfield-Mask: 0x01)                            */
+ #define R_LCDC_VI6_LIF0_CTRL_OBTH_Pos                    (16UL)         /*!< OBTH (Bit 16)                                         */
+ #define R_LCDC_VI6_LIF0_CTRL_OBTH_Msk                    (0xfff0000UL)  /*!< OBTH (Bitfield-Mask: 0xfff)                           */
+/* ====================================================  VI6_LIF0_CSBTH  ===================================================== */
+ #define R_LCDC_VI6_LIF0_CSBTH_LBTH_Pos                   (0UL)          /*!< LBTH (Bit 0)                                          */
+ #define R_LCDC_VI6_LIF0_CSBTH_LBTH_Msk                   (0xfffUL)      /*!< LBTH (Bitfield-Mask: 0xfff)                           */
+ #define R_LCDC_VI6_LIF0_CSBTH_HBTH_Pos                   (16UL)         /*!< HBTH (Bit 16)                                         */
+ #define R_LCDC_VI6_LIF0_CSBTH_HBTH_Msk                   (0xfff0000UL)  /*!< HBTH (Bitfield-Mask: 0xfff)                           */
+/* =====================================================  VI6_LIF0_LBA  ====================================================== */
+ #define R_LCDC_VI6_LIF0_LBA_LBA2_Pos                     (0UL)          /*!< LBA2 (Bit 0)                                          */
+ #define R_LCDC_VI6_LIF0_LBA_LBA2_Msk                     (0xfffUL)      /*!< LBA2 (Bitfield-Mask: 0xfff)                           */
+ #define R_LCDC_VI6_LIF0_LBA_LBA1_Pos                     (16UL)         /*!< LBA1 (Bit 16)                                         */
+ #define R_LCDC_VI6_LIF0_LBA_LBA1_Msk                     (0xfff0000UL)  /*!< LBA1 (Bitfield-Mask: 0xfff)                           */
+ #define R_LCDC_VI6_LIF0_LBA_LBA0_Pos                     (31UL)         /*!< LBA0 (Bit 31)                                         */
+ #define R_LCDC_VI6_LIF0_LBA_LBA0_Msk                     (0x80000000UL) /*!< LBA0 (Bitfield-Mask: 0x01)                            */
+/* ==================================================  VI6_LIF0_PADLN_CYC  =================================================== */
+ #define R_LCDC_VI6_LIF0_PADLN_CYC_PADLN_CYC_Pos          (0UL)          /*!< PADLN_CYC (Bit 0)                                     */
+ #define R_LCDC_VI6_LIF0_PADLN_CYC_PADLN_CYC_Msk          (0x3fUL)       /*!< PADLN_CYC (Bitfield-Mask: 0x3f)                       */
+/* ===================================================  VI6_LIF0_PADLN_PT  =================================================== */
+ #define R_LCDC_VI6_LIF0_PADLN_PT_PADLN_PATTERN_Pos       (0UL)          /*!< PADLN_PATTERN (Bit 0)                                 */
+ #define R_LCDC_VI6_LIF0_PADLN_PT_PADLN_PATTERN_Msk       (0xffffffffUL) /*!< PADLN_PATTERN (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  VI6_LIF0_PADLN_VAL  =================================================== */
+ #define R_LCDC_VI6_LIF0_PADLN_VAL_PADB_Pos               (0UL)          /*!< PADB (Bit 0)                                          */
+ #define R_LCDC_VI6_LIF0_PADLN_VAL_PADB_Msk               (0xffUL)       /*!< PADB (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_LIF0_PADLN_VAL_PADG_Pos               (8UL)          /*!< PADG (Bit 8)                                          */
+ #define R_LCDC_VI6_LIF0_PADLN_VAL_PADG_Msk               (0xff00UL)     /*!< PADG (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_LIF0_PADLN_VAL_PADR_Pos               (16UL)         /*!< PADR (Bit 16)                                         */
+ #define R_LCDC_VI6_LIF0_PADLN_VAL_PADR_Msk               (0xff0000UL)   /*!< PADR (Bitfield-Mask: 0xff)                            */
+ #define R_LCDC_VI6_LIF0_PADLN_VAL_PADA_Pos               (24UL)         /*!< PADA (Bit 24)                                         */
+ #define R_LCDC_VI6_LIF0_PADLN_VAL_PADA_Msk               (0xff000000UL) /*!< PADA (Bitfield-Mask: 0xff)                            */
+/* ==================================================  VI6_LIF0_PADLN_SIZE  ================================================== */
+ #define R_LCDC_VI6_LIF0_PADLN_SIZE_PADLN_VSIZE_Pos       (0UL)          /*!< PADLN_VSIZE (Bit 0)                                   */
+ #define R_LCDC_VI6_LIF0_PADLN_SIZE_PADLN_VSIZE_Msk       (0x1fffUL)     /*!< PADLN_VSIZE (Bitfield-Mask: 0x1fff)                   */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PCIE0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================  PCI_EP_REQRCVDAT  ==================================================== */
+/* ===================================================  PCI_RC_REQRCVDAT  ==================================================== */
+/* ====================================================  PCI_EP_REQADR1  ===================================================== */
+/* ====================================================  PCI_RC_REQADR1  ===================================================== */
+/* ====================================================  PCI_EP_REQADR2  ===================================================== */
+/* ====================================================  PCI_RC_REQADR2  ===================================================== */
+/* =====================================================  PCI_EP_REQBE  ====================================================== */
+ #define R_PCIE0_PCI_EP_REQBE_RBE_Pos              (0UL)          /*!< RBE (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_REQBE_RBE_Msk              (0xfUL)        /*!< RBE (Bitfield-Mask: 0x0f)                             */
+/* =====================================================  PCI_RC_REQBE  ====================================================== */
+ #define R_PCIE0_PCI_RC_REQBE_RBE_Pos              (0UL)          /*!< RBE (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_REQBE_RBE_Msk              (0xfUL)        /*!< RBE (Bitfield-Mask: 0x0f)                             */
+/* =====================================================  PCI_EP_REQISS  ===================================================== */
+ #define R_PCIE0_PCI_EP_REQISS_RI_Pos              (0UL)          /*!< RI (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_REQISS_RI_Msk              (0x1UL)        /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_REQISS_TR_TYPE_Pos         (8UL)          /*!< TR_TYPE (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_REQISS_TR_TYPE_Msk         (0xf00UL)      /*!< TR_TYPE (Bitfield-Mask: 0x0f)                         */
+ #define R_PCIE0_PCI_EP_REQISS_FUNC_Pos            (12UL)         /*!< FUNC (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_REQISS_FUNC_Msk            (0x7000UL)     /*!< FUNC (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_REQISS_MOR_STATUS_Pos      (16UL)         /*!< MOR_STATUS (Bit 16)                                   */
+ #define R_PCIE0_PCI_EP_REQISS_MOR_STATUS_Msk      (0x70000UL)    /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_REQISS_MOR_EP_ERR_Pos      (19UL)         /*!< MOR_EP_ERR (Bit 19)                                   */
+ #define R_PCIE0_PCI_EP_REQISS_MOR_EP_ERR_Msk      (0x80000UL)    /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_REQISS_MOR_CH_PERR_Pos     (20UL)         /*!< MOR_CH_PERR (Bit 20)                                  */
+ #define R_PCIE0_PCI_EP_REQISS_MOR_CH_PERR_Msk     (0x100000UL)   /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_REQISS_MOR_CD_PERR_Pos     (21UL)         /*!< MOR_CD_PERR (Bit 21)                                  */
+ #define R_PCIE0_PCI_EP_REQISS_MOR_CD_PERR_Msk     (0x200000UL)   /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_REQISS_RR_Pos              (22UL)         /*!< RR (Bit 22)                                           */
+ #define R_PCIE0_PCI_EP_REQISS_RR_Msk              (0x400000UL)   /*!< RR (Bitfield-Mask: 0x01)                              */
+/* =====================================================  PCI_RC_REQISS  ===================================================== */
+ #define R_PCIE0_PCI_RC_REQISS_RI_Pos              (0UL)          /*!< RI (Bit 0)                                            */
+ #define R_PCIE0_PCI_RC_REQISS_RI_Msk              (0x1UL)        /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_REQISS_TR_TYPE_Pos         (8UL)          /*!< TR_TYPE (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_REQISS_TR_TYPE_Msk         (0xf00UL)      /*!< TR_TYPE (Bitfield-Mask: 0x0f)                         */
+ #define R_PCIE0_PCI_RC_REQISS_FUNC_Pos            (12UL)         /*!< FUNC (Bit 12)                                         */
+ #define R_PCIE0_PCI_RC_REQISS_FUNC_Msk            (0x7000UL)     /*!< FUNC (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_RC_REQISS_MOR_STATUS_Pos      (16UL)         /*!< MOR_STATUS (Bit 16)                                   */
+ #define R_PCIE0_PCI_RC_REQISS_MOR_STATUS_Msk      (0x70000UL)    /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_REQISS_MOR_EP_ERR_Pos      (19UL)         /*!< MOR_EP_ERR (Bit 19)                                   */
+ #define R_PCIE0_PCI_RC_REQISS_MOR_EP_ERR_Msk      (0x80000UL)    /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_REQISS_MOR_CH_PERR_Pos     (20UL)         /*!< MOR_CH_PERR (Bit 20)                                  */
+ #define R_PCIE0_PCI_RC_REQISS_MOR_CH_PERR_Msk     (0x100000UL)   /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_REQISS_MOR_CD_PERR_Pos     (21UL)         /*!< MOR_CD_PERR (Bit 21)                                  */
+ #define R_PCIE0_PCI_RC_REQISS_MOR_CD_PERR_Msk     (0x200000UL)   /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_REQISS_RR_Pos              (22UL)         /*!< RR (Bit 22)                                           */
+ #define R_PCIE0_PCI_RC_REQISS_RR_Msk              (0x400000UL)   /*!< RR (Bitfield-Mask: 0x01)                              */
+/* ==================================================  PCI_RC_MSIRCVWADRL  =================================================== */
+ #define R_PCIE0_PCI_RC_MSIRCVWADRL_MSIRWE_Pos     (0UL)          /*!< MSIRWE (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_MSIRCVWADRL_MSIRWE_Msk     (0x1UL)        /*!< MSIRWE (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_MSIRCVWADRL_MDE_Pos        (1UL)          /*!< MDE (Bit 1)                                           */
+ #define R_PCIE0_PCI_RC_MSIRCVWADRL_MDE_Msk        (0x2UL)        /*!< MDE (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_MSIRCVWADRL_MSIRWAL_Pos    (3UL)          /*!< MSIRWAL (Bit 3)                                       */
+ #define R_PCIE0_PCI_RC_MSIRCVWADRL_MSIRWAL_Msk    (0xfffffff8UL) /*!< MSIRWAL (Bitfield-Mask: 0x1fffffff)                   */
+/* ==================================================  PCI_RC_MSIRCVWADRU  =================================================== */
+ #define R_PCIE0_PCI_RC_MSIRCVWADRU_MSIRWAU_Pos    (0UL)          /*!< MSIRWAU (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_MSIRCVWADRU_MSIRWAU_Msk    (0xffffffffUL) /*!< MSIRWAU (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_RC_MSIRCVWMSKL  =================================================== */
+ #define R_PCIE0_PCI_RC_MSIRCVWMSKL_MSIRWML_Pos    (0UL)          /*!< MSIRWML (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_MSIRCVWMSKL_MSIRWML_Msk    (0xffffffffUL) /*!< MSIRWML (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_RC_MSIRCVWMSKU  =================================================== */
+ #define R_PCIE0_PCI_RC_MSIRCVWMSKU_MSIRWMU_Pos    (0UL)          /*!< MSIRWMU (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_MSIRCVWMSKU_MSIRWMU_Msk    (0x7fffffffUL) /*!< MSIRWMU (Bitfield-Mask: 0x7fffffff)                   */
+/* ===================================================  PCI_RC_PINTRCVIE  ==================================================== */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_INTARIE_Pos      (0UL)          /*!< INTARIE (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_INTARIE_Msk      (0x1UL)        /*!< INTARIE (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_INTBRIE_Pos      (1UL)          /*!< INTBRIE (Bit 1)                                       */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_INTBRIE_Msk      (0x2UL)        /*!< INTBRIE (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_INTCRIE_Pos      (2UL)          /*!< INTCRIE (Bit 2)                                       */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_INTCRIE_Msk      (0x4UL)        /*!< INTCRIE (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_INTDRIE_Pos      (3UL)          /*!< INTDRIE (Bit 3)                                       */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_INTDRIE_Msk      (0x8UL)        /*!< INTDRIE (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_MSIRIE_Pos       (4UL)          /*!< MSIRIE (Bit 4)                                        */
+ #define R_PCIE0_PCI_RC_PINTRCVIE_MSIRIE_Msk       (0x10UL)       /*!< MSIRIE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  PCI_RC_PINTRCVIS  ==================================================== */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_INTARIS_Pos      (0UL)          /*!< INTARIS (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_INTARIS_Msk      (0x1UL)        /*!< INTARIS (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_INTBRIS_Pos      (1UL)          /*!< INTBRIS (Bit 1)                                       */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_INTBRIS_Msk      (0x2UL)        /*!< INTBRIS (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_INTCRIS_Pos      (2UL)          /*!< INTCRIS (Bit 2)                                       */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_INTCRIS_Msk      (0x4UL)        /*!< INTCRIS (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_INTDRIS_Pos      (3UL)          /*!< INTDRIS (Bit 3)                                       */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_INTDRIS_Msk      (0x8UL)        /*!< INTDRIS (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_MSIRIS_Pos       (4UL)          /*!< MSIRIS (Bit 4)                                        */
+ #define R_PCIE0_PCI_RC_PINTRCVIS_MSIRIS_Msk       (0x10UL)       /*!< MSIRIS (Bitfield-Mask: 0x01)                          */
+/* ====================================================  PCI_EP_INTXOUTS  ==================================================== */
+ #define R_PCIE0_PCI_EP_INTXOUTS_INTAS_Pos         (0UL)          /*!< INTAS (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_INTXOUTS_INTAS_Msk         (0x1UL)        /*!< INTAS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_INTXOUTS_INTBS_Pos         (1UL)          /*!< INTBS (Bit 1)                                         */
+ #define R_PCIE0_PCI_EP_INTXOUTS_INTBS_Msk         (0x2UL)        /*!< INTBS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_INTXOUTS_INTCS_Pos         (2UL)          /*!< INTCS (Bit 2)                                         */
+ #define R_PCIE0_PCI_EP_INTXOUTS_INTCS_Msk         (0x4UL)        /*!< INTCS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_INTXOUTS_INTDS_Pos         (3UL)          /*!< INTDS (Bit 3)                                         */
+ #define R_PCIE0_PCI_EP_INTXOUTS_INTDS_Msk         (0x8UL)        /*!< INTDS (Bitfield-Mask: 0x01)                           */
+/* ====================================================  PCI_EP_MSGRCVIE  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_PMETOARIE_Pos     (16UL)         /*!< PMETOARIE (Bit 16)                                    */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_PMETOARIE_Msk     (0x10000UL)    /*!< PMETOARIE (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_PMETORIE_Pos      (17UL)         /*!< PMETORIE (Bit 17)                                     */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_PMETORIE_Msk      (0x20000UL)    /*!< PMETORIE (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_PMPMERIE_Pos      (18UL)         /*!< PMPMERIE (Bit 18)                                     */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_PMPMERIE_Msk      (0x40000UL)    /*!< PMPMERIE (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_PMASNRI_Pos       (19UL)         /*!< PMASNRI (Bit 19)                                      */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_PMASNRI_Msk       (0x80000UL)    /*!< PMASNRI (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_MRIE_Pos          (24UL)         /*!< MRIE (Bit 24)                                         */
+ #define R_PCIE0_PCI_EP_MSGRCVIE_MRIE_Msk          (0x1000000UL)  /*!< MRIE (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_RC_MSGRCVIE  ==================================================== */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_PMETOARI_Pos      (16UL)         /*!< PMETOARI (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_PMETOARI_Msk      (0x10000UL)    /*!< PMETOARI (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_PMETORI_Pos       (17UL)         /*!< PMETORI (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_PMETORI_Msk       (0x20000UL)    /*!< PMETORI (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_PMPMERI_Pos       (18UL)         /*!< PMPMERI (Bit 18)                                      */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_PMPMERI_Msk       (0x40000UL)    /*!< PMPMERI (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_PMASNR_Pos        (19UL)         /*!< PMASNR (Bit 19)                                       */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_PMASNR_Msk        (0x80000UL)    /*!< PMASNR (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_MRI_Pos           (24UL)         /*!< MRI (Bit 24)                                          */
+ #define R_PCIE0_PCI_RC_MSGRCVIE_MRI_Msk           (0x1000000UL)  /*!< MRI (Bitfield-Mask: 0x01)                             */
+/* ====================================================  PCI_EP_MSGRCVIS  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_PMETOARI_Pos      (16UL)         /*!< PMETOARI (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_PMETOARI_Msk      (0x10000UL)    /*!< PMETOARI (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_PMETORI_Pos       (17UL)         /*!< PMETORI (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_PMETORI_Msk       (0x20000UL)    /*!< PMETORI (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_PMPMERI_Pos       (18UL)         /*!< PMPMERI (Bit 18)                                      */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_PMPMERI_Msk       (0x40000UL)    /*!< PMPMERI (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_PMASNR_Pos        (19UL)         /*!< PMASNR (Bit 19)                                       */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_PMASNR_Msk        (0x80000UL)    /*!< PMASNR (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_MRI_Pos           (24UL)         /*!< MRI (Bit 24)                                          */
+ #define R_PCIE0_PCI_EP_MSGRCVIS_MRI_Msk           (0x1000000UL)  /*!< MRI (Bitfield-Mask: 0x01)                             */
+/* ====================================================  PCI_RC_MSGRCVIS  ==================================================== */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_PMETOARI_Pos      (16UL)         /*!< PMETOARI (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_PMETOARI_Msk      (0x10000UL)    /*!< PMETOARI (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_PMETORI_Pos       (17UL)         /*!< PMETORI (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_PMETORI_Msk       (0x20000UL)    /*!< PMETORI (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_PMPMERI_Pos       (18UL)         /*!< PMPMERI (Bit 18)                                      */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_PMPMERI_Msk       (0x40000UL)    /*!< PMPMERI (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_PMASNR_Pos        (19UL)         /*!< PMASNR (Bit 19)                                       */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_PMASNR_Msk        (0x80000UL)    /*!< PMASNR (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_MRI_Pos           (24UL)         /*!< MRI (Bit 24)                                          */
+ #define R_PCIE0_PCI_RC_MSGRCVIS_MRI_Msk           (0x1000000UL)  /*!< MRI (Bitfield-Mask: 0x01)                             */
+/* ====================================================  PCI_EP_MSGCODE  ===================================================== */
+ #define R_PCIE0_PCI_EP_MSGCODE_MP_Pos             (0UL)          /*!< MP (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_MSGCODE_MP_Msk             (0x1UL)        /*!< MP (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_MSGCODE_R_Pos              (5UL)          /*!< R (Bit 5)                                             */
+ #define R_PCIE0_PCI_EP_MSGCODE_R_Msk              (0xe0UL)       /*!< R (Bitfield-Mask: 0x07)                               */
+ #define R_PCIE0_PCI_EP_MSGCODE_MC_Pos             (8UL)          /*!< MC (Bit 8)                                            */
+ #define R_PCIE0_PCI_EP_MSGCODE_MC_Msk             (0xff00UL)     /*!< MC (Bitfield-Mask: 0xff)                              */
+/* ====================================================  PCI_RC_MSGCODE  ===================================================== */
+ #define R_PCIE0_PCI_RC_MSGCODE_MP_Pos             (0UL)          /*!< MP (Bit 0)                                            */
+ #define R_PCIE0_PCI_RC_MSGCODE_MP_Msk             (0x1UL)        /*!< MP (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_MSGCODE_R_Pos              (5UL)          /*!< R (Bit 5)                                             */
+ #define R_PCIE0_PCI_RC_MSGCODE_R_Msk              (0xe0UL)       /*!< R (Bitfield-Mask: 0x07)                               */
+ #define R_PCIE0_PCI_RC_MSGCODE_MC_Pos             (8UL)          /*!< MC (Bit 8)                                            */
+ #define R_PCIE0_PCI_RC_MSGCODE_MC_Msk             (0xff00UL)     /*!< MC (Bitfield-Mask: 0xff)                              */
+/* ====================================================  PCI_EP_MSGDATA  ===================================================== */
+/* ====================================================  PCI_RC_MSGDATA  ===================================================== */
+/* ====================================================  PCI_EP_MSGH3DW  ===================================================== */
+/* ====================================================  PCI_RC_MSGH3DW  ===================================================== */
+/* ====================================================  PCI_EP_MSGH4DW  ===================================================== */
+/* ====================================================  PCI_RC_MSGH4DW  ===================================================== */
+/* ====================================================  PCI_EP_INTTABLE  ==================================================== */
+ #define R_PCIE0_PCI_EP_INTTABLE_MSG_INT_Pos                                     (8UL)          /*!< MSG_INT (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_INTTABLE_MSG_INT_Msk                                     (0x100UL)      /*!< MSG_INT (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_INTTABLE_PCIE_EVT_INT_Pos                                (9UL)          /*!< PCIE_EVT_INT (Bit 9)                                  */
+ #define R_PCIE0_PCI_EP_INTTABLE_PCIE_EVT_INT_Msk                                (0x200UL)      /*!< PCIE_EVT_INT (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_INTTABLE_AXI_ERR_IN_Pos                                  (10UL)         /*!< AXI_ERR_IN (Bit 10)                                   */
+ #define R_PCIE0_PCI_EP_INTTABLE_AXI_ERR_IN_Msk                                  (0x400UL)      /*!< AXI_ERR_IN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_INTTABLE_DMA_INT_Pos                                     (24UL)         /*!< DMA_INT (Bit 24)                                      */
+ #define R_PCIE0_PCI_EP_INTTABLE_DMA_INT_Msk                                     (0xff000000UL) /*!< DMA_INT (Bitfield-Mask: 0xff)                         */
+/* ====================================================  PCI_RC_INTTABLE  ==================================================== */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTA_RC_Pos                                     (0UL)          /*!< INTA_RC (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTA_RC_Msk                                     (0x1UL)        /*!< INTA_RC (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTB_RC_Pos                                     (1UL)          /*!< INTB_RC (Bit 1)                                       */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTB_RC_Msk                                     (0x2UL)        /*!< INTB_RC (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTC_RC_Pos                                     (2UL)          /*!< INTC_RC (Bit 2)                                       */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTC_RC_Msk                                     (0x4UL)        /*!< INTC_RC (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTD_RC_Pos                                     (3UL)          /*!< INTD_RC (Bit 3)                                       */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTD_RC_Msk                                     (0x8UL)        /*!< INTD_RC (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTMSI_RC_Pos                                   (4UL)          /*!< INTMSI_RC (Bit 4)                                     */
+ #define R_PCIE0_PCI_RC_INTTABLE_INTMSI_RC_Msk                                   (0x10UL)       /*!< INTMSI_RC (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_RC_INTTABLE_MSG_INT_Pos                                     (8UL)          /*!< MSG_INT (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_INTTABLE_MSG_INT_Msk                                     (0x100UL)      /*!< MSG_INT (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_INTTABLE_PCIE_EVT_INT_Pos                                (9UL)          /*!< PCIE_EVT_INT (Bit 9)                                  */
+ #define R_PCIE0_PCI_RC_INTTABLE_PCIE_EVT_INT_Msk                                (0x200UL)      /*!< PCIE_EVT_INT (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_INTTABLE_AXI_ERR_IN_Pos                                  (10UL)         /*!< AXI_ERR_IN (Bit 10)                                   */
+ #define R_PCIE0_PCI_RC_INTTABLE_AXI_ERR_IN_Msk                                  (0x400UL)      /*!< AXI_ERR_IN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_INTTABLE_INT_LINK_EQUALIZATION_REQUEST_Pos               (15UL)         /*!< INT_LINK_EQUALIZATION_REQUEST (Bit 15)           */
+ #define R_PCIE0_PCI_RC_INTTABLE_INT_LINK_EQUALIZATION_REQUEST_Msk               (0x8000UL)     /*!< INT_LINK_EQUALIZATION_REQUEST (Bitfield-Mask: 0x01) */
+/* =====================================================  PCI_EP_PEIE0  ====================================================== */
+ #define R_PCIE0_PCI_EP_PEIE0_DLUDEN_Pos                                         (9UL)          /*!< DLUDEN (Bit 9)                                        */
+ #define R_PCIE0_PCI_EP_PEIE0_DLUDEN_Msk                                         (0x200UL)      /*!< DLUDEN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_PEIE0_ASPML1REN_Pos                                      (10UL)         /*!< ASPML1REN (Bit 10)                                    */
+ #define R_PCIE0_PCI_EP_PEIE0_ASPML1REN_Msk                                      (0x400UL)      /*!< ASPML1REN (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_EP_PEIE0_RX_DLLP_PM_ENTER_L23_EN_Pos                        (12UL)         /*!< RX_DLLP_PM_ENTER_L23_EN (Bit 12)                      */
+ #define R_PCIE0_PCI_EP_PEIE0_RX_DLLP_PM_ENTER_L23_EN_Msk                        (0x1000UL)     /*!< RX_DLLP_PM_ENTER_L23_EN (Bitfield-Mask: 0x01)         */
+ #define R_PCIE0_PCI_EP_PEIE0_BME_PERR_EN_Pos                                    (15UL)         /*!< BME_PERR_EN (Bit 15)                                  */
+ #define R_PCIE0_PCI_EP_PEIE0_BME_PERR_EN_Msk                                    (0x8000UL)     /*!< BME_PERR_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_PEIE0_CA_EN_Pos                                          (24UL)         /*!< CA_EN (Bit 24)                                        */
+ #define R_PCIE0_PCI_EP_PEIE0_CA_EN_Msk                                          (0x1000000UL)  /*!< CA_EN (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PEIE0_AXI_PERR_EN_Pos                                    (25UL)         /*!< AXI_PERR_EN (Bit 25)                                  */
+ #define R_PCIE0_PCI_EP_PEIE0_AXI_PERR_EN_Msk                                    (0x2000000UL)  /*!< AXI_PERR_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_PEIE0_RDEN_Pos                                           (28UL)         /*!< RDEN (Bit 28)                                         */
+ #define R_PCIE0_PCI_EP_PEIE0_RDEN_Msk                                           (0x10000000UL) /*!< RDEN (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_PEIE0_UI_LINK_SPEED_CHANGE_DONE_EN_Pos                   (29UL)         /*!< UI_LINK_SPEED_CHANGE_DONE_EN (Bit 29)                */
+ #define R_PCIE0_PCI_EP_PEIE0_UI_LINK_SPEED_CHANGE_DONE_EN_Msk                   (0x20000000UL) /*!< UI_LINK_SPEED_CHANGE_DONE_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIE0_UI_LINK_WIDTH_CHANGE_DONE_EN_Pos                   (30UL)         /*!< UI_LINK_WIDTH_CHANGE_DONE_EN (Bit 30)                */
+ #define R_PCIE0_PCI_EP_PEIE0_UI_LINK_WIDTH_CHANGE_DONE_EN_Msk                   (0x40000000UL) /*!< UI_LINK_WIDTH_CHANGE_DONE_EN (Bitfield-Mask: 0x01) */
+/* =====================================================  PCI_RC_PEIE0  ====================================================== */
+ #define R_PCIE0_PCI_RC_PEIE0_DLUDEN_Pos                                         (9UL)          /*!< DLUDEN (Bit 9)                                        */
+ #define R_PCIE0_PCI_RC_PEIE0_DLUDEN_Msk                                         (0x200UL)      /*!< DLUDEN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_PEIE0_ASPML1REN_Pos                                      (10UL)         /*!< ASPML1REN (Bit 10)                                    */
+ #define R_PCIE0_PCI_RC_PEIE0_ASPML1REN_Msk                                      (0x400UL)      /*!< ASPML1REN (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_RC_PEIE0_RX_DLLP_PM_ENTER_L23_EN_Pos                        (12UL)         /*!< RX_DLLP_PM_ENTER_L23_EN (Bit 12)                      */
+ #define R_PCIE0_PCI_RC_PEIE0_RX_DLLP_PM_ENTER_L23_EN_Msk                        (0x1000UL)     /*!< RX_DLLP_PM_ENTER_L23_EN (Bitfield-Mask: 0x01)         */
+ #define R_PCIE0_PCI_RC_PEIE0_CA_EN_Pos                                          (24UL)         /*!< CA_EN (Bit 24)                                        */
+ #define R_PCIE0_PCI_RC_PEIE0_CA_EN_Msk                                          (0x1000000UL)  /*!< CA_EN (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PEIE0_RDEN_Pos                                           (28UL)         /*!< RDEN (Bit 28)                                         */
+ #define R_PCIE0_PCI_RC_PEIE0_RDEN_Msk                                           (0x10000000UL) /*!< RDEN (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_PEIE0_UI_LINK_SPEED_CHANGE_DONE_EN_Pos                   (29UL)         /*!< UI_LINK_SPEED_CHANGE_DONE_EN (Bit 29)                */
+ #define R_PCIE0_PCI_RC_PEIE0_UI_LINK_SPEED_CHANGE_DONE_EN_Msk                   (0x20000000UL) /*!< UI_LINK_SPEED_CHANGE_DONE_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIE0_UI_LINK_WIDTH_CHANGE_DONE_EN_Pos                   (30UL)         /*!< UI_LINK_WIDTH_CHANGE_DONE_EN (Bit 30)                */
+ #define R_PCIE0_PCI_RC_PEIE0_UI_LINK_WIDTH_CHANGE_DONE_EN_Msk                   (0x40000000UL) /*!< UI_LINK_WIDTH_CHANGE_DONE_EN (Bitfield-Mask: 0x01) */
+/* =====================================================  PCI_EP_PEIS0  ====================================================== */
+ #define R_PCIE0_PCI_EP_PEIS0_DLUDEN_Pos                                         (9UL)          /*!< DLUDEN (Bit 9)                                        */
+ #define R_PCIE0_PCI_EP_PEIS0_DLUDEN_Msk                                         (0x200UL)      /*!< DLUDEN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_PEIS0_ASPML1_Pos                                         (10UL)         /*!< ASPML1 (Bit 10)                                       */
+ #define R_PCIE0_PCI_EP_PEIS0_ASPML1_Msk                                         (0x400UL)      /*!< ASPML1 (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_PEIS0_RX_DLLP_PM_ENTER_L23_Pos                           (12UL)         /*!< RX_DLLP_PM_ENTER_L23 (Bit 12)                         */
+ #define R_PCIE0_PCI_EP_PEIS0_RX_DLLP_PM_ENTER_L23_Msk                           (0x1000UL)     /*!< RX_DLLP_PM_ENTER_L23 (Bitfield-Mask: 0x01)            */
+ #define R_PCIE0_PCI_EP_PEIS0_BME_PERR_Pos                                       (15UL)         /*!< BME_PERR (Bit 15)                                     */
+ #define R_PCIE0_PCI_EP_PEIS0_BME_PERR_Msk                                       (0x8000UL)     /*!< BME_PERR (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_PEIS0_CA_Pos                                             (24UL)         /*!< CA (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_PEIS0_CA_Msk                                             (0x1000000UL)  /*!< CA (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_PEIS0_AXIM_PERR_Pos                                      (25UL)         /*!< AXIM_PERR (Bit 25)                                    */
+ #define R_PCIE0_PCI_EP_PEIS0_AXIM_PERR_Msk                                      (0x2000000UL)  /*!< AXIM_PERR (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_EP_PEIS0_RD_Pos                                             (28UL)         /*!< RD (Bit 28)                                           */
+ #define R_PCIE0_PCI_EP_PEIS0_RD_Msk                                             (0x10000000UL) /*!< RD (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_PEIS0_UI_LINK_SPEED_CHANGE_DONE_Pos                      (29UL)         /*!< UI_LINK_SPEED_CHANGE_DONE (Bit 29)                    */
+ #define R_PCIE0_PCI_EP_PEIS0_UI_LINK_SPEED_CHANGE_DONE_Msk                      (0x20000000UL) /*!< UI_LINK_SPEED_CHANGE_DONE (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIS0_UI_LINK_WIDTH_CHANGE_DONE_Pos                      (30UL)         /*!< UI_LINK_WIDTH_CHANGE_DONE (Bit 30)                    */
+ #define R_PCIE0_PCI_EP_PEIS0_UI_LINK_WIDTH_CHANGE_DONE_Msk                      (0x40000000UL) /*!< UI_LINK_WIDTH_CHANGE_DONE (Bitfield-Mask: 0x01) */
+/* =====================================================  PCI_RC_PEIS0  ====================================================== */
+ #define R_PCIE0_PCI_RC_PEIS0_DLUDEN_Pos                                         (9UL)          /*!< DLUDEN (Bit 9)                                        */
+ #define R_PCIE0_PCI_RC_PEIS0_DLUDEN_Msk                                         (0x200UL)      /*!< DLUDEN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_PEIS0_ASPML1R_Pos                                        (10UL)         /*!< ASPML1R (Bit 10)                                      */
+ #define R_PCIE0_PCI_RC_PEIS0_ASPML1R_Msk                                        (0x400UL)      /*!< ASPML1R (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_PEIS0_RX_DLLP_PM_ENTER_L23_Pos                           (12UL)         /*!< RX_DLLP_PM_ENTER_L23 (Bit 12)                         */
+ #define R_PCIE0_PCI_RC_PEIS0_RX_DLLP_PM_ENTER_L23_Msk                           (0x1000UL)     /*!< RX_DLLP_PM_ENTER_L23 (Bitfield-Mask: 0x01)            */
+ #define R_PCIE0_PCI_RC_PEIS0_CA_Pos                                             (24UL)         /*!< CA (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_PEIS0_CA_Msk                                             (0x1000000UL)  /*!< CA (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_PEIS0_RD_Pos                                             (28UL)         /*!< RD (Bit 28)                                           */
+ #define R_PCIE0_PCI_RC_PEIS0_RD_Msk                                             (0x10000000UL) /*!< RD (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_PEIS0_UI_LINK_SPEED_CHANGE_DONE_Pos                      (29UL)         /*!< UI_LINK_SPEED_CHANGE_DONE (Bit 29)                    */
+ #define R_PCIE0_PCI_RC_PEIS0_UI_LINK_SPEED_CHANGE_DONE_Msk                      (0x20000000UL) /*!< UI_LINK_SPEED_CHANGE_DONE (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIS0_UI_LINK_WIDTH_CHANGE_DONE_Pos                      (30UL)         /*!< UI_LINK_WIDTH_CHANGE_DONE (Bit 30)                    */
+ #define R_PCIE0_PCI_RC_PEIS0_UI_LINK_WIDTH_CHANGE_DONE_Msk                      (0x40000000UL) /*!< UI_LINK_WIDTH_CHANGE_DONE (Bitfield-Mask: 0x01) */
+/* =====================================================  PCI_EP_PEIE1  ====================================================== */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN_Pos        (0UL)          /*!< ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN (Bit 0) */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN_Msk        (0x1UL)        /*!< ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN_Pos        (1UL)          /*!< ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN (Bit 1) */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN_Msk        (0x2UL)        /*!< ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN_Pos          (8UL)          /*!< ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN (Bit 8) */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN_Msk          (0x100UL)      /*!< ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN_Pos          (9UL)          /*!< ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN (Bit 9) */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN_Msk          (0x200UL)      /*!< ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_RPC_REPLAYFIFO_PERR_EN_Pos                     (16UL)         /*!< ERR_RPC_REPLAYFIFO_PERR_EN (Bit 16)                   */
+ #define R_PCIE0_PCI_EP_PEIE1_ERR_RPC_REPLAYFIFO_PERR_EN_Msk                     (0x10000UL)    /*!< ERR_RPC_REPLAYFIFO_PERR_EN (Bitfield-Mask: 0x01)  */
+ #define R_PCIE0_PCI_EP_PEIE1_TXB_PARITY_ERR_EN_Pos                              (17UL)         /*!< TXB_PARITY_ERR_EN (Bit 17)                            */
+ #define R_PCIE0_PCI_EP_PEIE1_TXB_PARITY_ERR_EN_Msk                              (0x20000UL)    /*!< TXB_PARITY_ERR_EN (Bitfield-Mask: 0x01)               */
+/* =====================================================  PCI_RC_PEIE1  ====================================================== */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN_Pos        (0UL)          /*!< ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN (Bit 0) */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN_Msk        (0x1UL)        /*!< ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN_Pos        (1UL)          /*!< ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN (Bit 1) */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN_Msk        (0x2UL)        /*!< ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN_Pos          (8UL)          /*!< ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN (Bit 8) */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN_Msk          (0x100UL)      /*!< ERR_REPLAY_LOWER_CORRECTABLE_ERROR_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN_Pos          (9UL)          /*!< ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN (Bit 9) */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN_Msk          (0x200UL)      /*!< ERR_REPLAY_UPPER_CORRECTABLE_ERROR_EN (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_RPC_REPLAYFIFO_PERR_EN_Pos                     (16UL)         /*!< ERR_RPC_REPLAYFIFO_PERR_EN (Bit 16)                   */
+ #define R_PCIE0_PCI_RC_PEIE1_ERR_RPC_REPLAYFIFO_PERR_EN_Msk                     (0x10000UL)    /*!< ERR_RPC_REPLAYFIFO_PERR_EN (Bitfield-Mask: 0x01)  */
+ #define R_PCIE0_PCI_RC_PEIE1_TXB_PARITY_ERR_EN_Pos                              (17UL)         /*!< TXB_PARITY_ERR_EN (Bit 17)                            */
+ #define R_PCIE0_PCI_RC_PEIE1_TXB_PARITY_ERR_EN_Msk                              (0x20000UL)    /*!< TXB_PARITY_ERR_EN (Bitfield-Mask: 0x01)               */
+/* =====================================================  PCI_EP_PEIS1  ====================================================== */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_Pos           (0UL)          /*!< ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR (Bit 0)  */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_Msk           (0x1UL)        /*!< ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_Pos           (1UL)          /*!< ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR (Bit 1)  */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_Msk           (0x2UL)        /*!< ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_REPLAY_LOWER_CORRECTABLE_ERROR_Pos             (8UL)          /*!< ERR_REPLAY_LOWER_CORRECTABLE_ERROR (Bit 8)      */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_REPLAY_LOWER_CORRECTABLE_ERROR_Msk             (0x100UL)      /*!< ERR_REPLAY_LOWER_CORRECTABLE_ERROR (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_REPLAY_UPPER_CORRECTABLE_ERROR_Pos             (9UL)          /*!< ERR_REPLAY_UPPER_CORRECTABLE_ERROR (Bit 9)      */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_REPLAY_UPPER_CORRECTABLE_ERROR_Msk             (0x200UL)      /*!< ERR_REPLAY_UPPER_CORRECTABLE_ERROR (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_RPC_REPLAYFIFO_PERR_Pos                        (16UL)         /*!< ERR_RPC_REPLAYFIFO_PERR (Bit 16)                      */
+ #define R_PCIE0_PCI_EP_PEIS1_ERR_RPC_REPLAYFIFO_PERR_Msk                        (0x10000UL)    /*!< ERR_RPC_REPLAYFIFO_PERR (Bitfield-Mask: 0x01)        */
+ #define R_PCIE0_PCI_EP_PEIS1_TXB_PARITY_ERR_Pos                                 (17UL)         /*!< TXB_PARITY_ERR (Bit 17)                               */
+ #define R_PCIE0_PCI_EP_PEIS1_TXB_PARITY_ERR_Msk                                 (0x20000UL)    /*!< TXB_PARITY_ERR (Bitfield-Mask: 0x01)                  */
+/* =====================================================  PCI_RC_PEIS1  ====================================================== */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_Pos           (0UL)          /*!< ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR (Bit 0)  */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR_Msk           (0x1UL)        /*!< ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_Pos           (1UL)          /*!< ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR (Bit 1)  */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR_Msk           (0x2UL)        /*!< ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_REPLAY_LOWER_CORRECTABLE_ERROR_Pos             (8UL)          /*!< ERR_REPLAY_LOWER_CORRECTABLE_ERROR (Bit 8)      */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_REPLAY_LOWER_CORRECTABLE_ERROR_Msk             (0x100UL)      /*!< ERR_REPLAY_LOWER_CORRECTABLE_ERROR (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_REPLAY_UPPER_CORRECTABLE_ERROR_Pos             (9UL)          /*!< ERR_REPLAY_UPPER_CORRECTABLE_ERROR (Bit 9)      */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_REPLAY_UPPER_CORRECTABLE_ERROR_Msk             (0x200UL)      /*!< ERR_REPLAY_UPPER_CORRECTABLE_ERROR (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_RPC_REPLAYFIFO_PERR_Pos                        (16UL)         /*!< ERR_RPC_REPLAYFIFO_PERR (Bit 16)                      */
+ #define R_PCIE0_PCI_RC_PEIS1_ERR_RPC_REPLAYFIFO_PERR_Msk                        (0x10000UL)    /*!< ERR_RPC_REPLAYFIFO_PERR (Bitfield-Mask: 0x01)        */
+ #define R_PCIE0_PCI_RC_PEIS1_TXB_PARITY_ERR_Pos                                 (17UL)         /*!< TXB_PARITY_ERR (Bit 17)                               */
+ #define R_PCIE0_PCI_RC_PEIS1_TXB_PARITY_ERR_Msk                                 (0x20000UL)    /*!< TXB_PARITY_ERR (Bitfield-Mask: 0x01)                  */
+/* =====================================================  PCI_EP_AMEIE  ====================================================== */
+ #define R_PCIE0_PCI_EP_AMEIE_RMSTERRINTEN_Pos                                   (0UL)          /*!< RMSTERRINTEN (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_AMEIE_RMSTERRINTEN_Msk                                   (0xfUL)        /*!< RMSTERRINTEN (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_AMEIE_WMSTERRINTEN_Pos                                   (8UL)          /*!< WMSTERRINTEN (Bit 8)                                  */
+ #define R_PCIE0_PCI_EP_AMEIE_WMSTERRINTEN_Msk                                   (0xf00UL)      /*!< WMSTERRINTEN (Bitfield-Mask: 0x0f)                    */
+/* =====================================================  PCI_RC_AMEIE  ====================================================== */
+ #define R_PCIE0_PCI_RC_AMEIE_RMSTERRINTEN_Pos                                   (0UL)          /*!< RMSTERRINTEN (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_AMEIE_RMSTERRINTEN_Msk                                   (0xfUL)        /*!< RMSTERRINTEN (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_AMEIE_WMSTERRINTEN_Pos                                   (8UL)          /*!< WMSTERRINTEN (Bit 8)                                  */
+ #define R_PCIE0_PCI_RC_AMEIE_WMSTERRINTEN_Msk                                   (0xf00UL)      /*!< WMSTERRINTEN (Bitfield-Mask: 0x0f)                    */
+/* =====================================================  PCI_EP_AMEIS  ====================================================== */
+ #define R_PCIE0_PCI_EP_AMEIS_RMSTERRINT_Pos                                     (0UL)          /*!< RMSTERRINT (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_AMEIS_RMSTERRINT_Msk                                     (0xfUL)        /*!< RMSTERRINT (Bitfield-Mask: 0x0f)                      */
+ #define R_PCIE0_PCI_EP_AMEIS_WMSTERRINT_Pos                                     (8UL)          /*!< WMSTERRINT (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_AMEIS_WMSTERRINT_Msk                                     (0xf00UL)      /*!< WMSTERRINT (Bitfield-Mask: 0x0f)                      */
+ #define R_PCIE0_PCI_EP_AMEIS_RERRID_Pos                                         (16UL)         /*!< RERRID (Bit 16)                                       */
+ #define R_PCIE0_PCI_EP_AMEIS_RERRID_Msk                                         (0xf0000UL)    /*!< RERRID (Bitfield-Mask: 0x0f)                          */
+ #define R_PCIE0_PCI_EP_AMEIS_WERRID_Pos                                         (24UL)         /*!< WERRID (Bit 24)                                       */
+ #define R_PCIE0_PCI_EP_AMEIS_WERRID_Msk                                         (0xf000000UL)  /*!< WERRID (Bitfield-Mask: 0x0f)                          */
+/* =====================================================  PCI_RC_AMEIS  ====================================================== */
+ #define R_PCIE0_PCI_RC_AMEIS_RMSTERRINT_Pos                                     (0UL)          /*!< RMSTERRINT (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_AMEIS_RMSTERRINT_Msk                                     (0xfUL)        /*!< RMSTERRINT (Bitfield-Mask: 0x0f)                      */
+ #define R_PCIE0_PCI_RC_AMEIS_WMSTERRINT_Pos                                     (8UL)          /*!< WMSTERRINT (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_AMEIS_WMSTERRINT_Msk                                     (0xf00UL)      /*!< WMSTERRINT (Bitfield-Mask: 0x0f)                      */
+ #define R_PCIE0_PCI_RC_AMEIS_RERRID_Pos                                         (16UL)         /*!< RERRID (Bit 16)                                       */
+ #define R_PCIE0_PCI_RC_AMEIS_RERRID_Msk                                         (0xf0000UL)    /*!< RERRID (Bitfield-Mask: 0x0f)                          */
+ #define R_PCIE0_PCI_RC_AMEIS_WERRID_Pos                                         (24UL)         /*!< WERRID (Bit 24)                                       */
+ #define R_PCIE0_PCI_RC_AMEIS_WERRID_Msk                                         (0xf000000UL)  /*!< WERRID (Bitfield-Mask: 0x0f)                          */
+/* =====================================================  PCI_EP_ASEIE1  ===================================================== */
+ #define R_PCIE0_PCI_EP_ASEIE1_RSLVERRINTEN_Pos                                  (0UL)          /*!< RSLVERRINTEN (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_ASEIE1_RSLVERRINTEN_Msk                                  (0x3UL)        /*!< RSLVERRINTEN (Bitfield-Mask: 0x03)                    */
+ #define R_PCIE0_PCI_EP_ASEIE1_WSLVERRINTEN_Pos                                  (8UL)          /*!< WSLVERRINTEN (Bit 8)                                  */
+ #define R_PCIE0_PCI_EP_ASEIE1_WSLVERRINTEN_Msk                                  (0xf00UL)      /*!< WSLVERRINTEN (Bitfield-Mask: 0x0f)                    */
+/* =====================================================  PCI_RC_ASEIE1  ===================================================== */
+ #define R_PCIE0_PCI_RC_ASEIE1_RSLVERRINTEN_Pos                                  (0UL)          /*!< RSLVERRINTEN (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_ASEIE1_RSLVERRINTEN_Msk                                  (0x3UL)        /*!< RSLVERRINTEN (Bitfield-Mask: 0x03)                    */
+ #define R_PCIE0_PCI_RC_ASEIE1_WSLVERRINTEN_Pos                                  (8UL)          /*!< WSLVERRINTEN (Bit 8)                                  */
+ #define R_PCIE0_PCI_RC_ASEIE1_WSLVERRINTEN_Msk                                  (0xf00UL)      /*!< WSLVERRINTEN (Bitfield-Mask: 0x0f)                    */
+/* =====================================================  PCI_EP_ASEIS1  ===================================================== */
+ #define R_PCIE0_PCI_EP_ASEIS1_RSLVERRINT_Pos                                    (0UL)          /*!< RSLVERRINT (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_ASEIS1_RSLVERRINT_Msk                                    (0x3UL)        /*!< RSLVERRINT (Bitfield-Mask: 0x03)                      */
+ #define R_PCIE0_PCI_EP_ASEIS1_WSLVERRINT_Pos                                    (8UL)          /*!< WSLVERRINT (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_ASEIS1_WSLVERRINT_Msk                                    (0xf00UL)      /*!< WSLVERRINT (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  PCI_RC_ASEIS1  ===================================================== */
+ #define R_PCIE0_PCI_RC_ASEIS1_RSLVERRINT_Pos                                    (0UL)          /*!< RSLVERRINT (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_ASEIS1_RSLVERRINT_Msk                                    (0x3UL)        /*!< RSLVERRINT (Bitfield-Mask: 0x03)                      */
+ #define R_PCIE0_PCI_RC_ASEIS1_WSLVERRINT_Pos                                    (8UL)          /*!< WSLVERRINT (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_ASEIS1_WSLVERRINT_Msk                                    (0xf00UL)      /*!< WSLVERRINT (Bitfield-Mask: 0x0f)                      */
+/* =====================================================  PCI_EP_ASEIS3  ===================================================== */
+/* =====================================================  PCI_RC_ASEIS3  ===================================================== */
+/* =====================================================  PCI_EP_PEIE2  ====================================================== */
+ #define R_PCIE0_PCI_EP_PEIE2_D3_HOT_ERR_EN_Pos                                  (8UL)          /*!< D3_HOT_ERR_EN (Bit 8)                                 */
+ #define R_PCIE0_PCI_EP_PEIE2_D3_HOT_ERR_EN_Msk                                  (0xff00UL)     /*!< D3_HOT_ERR_EN (Bitfield-Mask: 0xff)                   */
+ #define R_PCIE0_PCI_EP_PEIE2_LTR_MECHANISM_EN_Pos                               (16UL)         /*!< LTR_MECHANISM_EN (Bit 16)                             */
+ #define R_PCIE0_PCI_EP_PEIE2_LTR_MECHANISM_EN_Msk                               (0x10000UL)    /*!< LTR_MECHANISM_EN (Bitfield-Mask: 0x01)                */
+/* =====================================================  PCI_EP_PEIS2  ====================================================== */
+ #define R_PCIE0_PCI_EP_PEIS2_D3_HOT_ERR_Pos                                     (8UL)          /*!< D3_HOT_ERR (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_PEIS2_D3_HOT_ERR_Msk                                     (0xff00UL)     /*!< D3_HOT_ERR (Bitfield-Mask: 0xff)                      */
+ #define R_PCIE0_PCI_EP_PEIS2_LTR_MECHANISM_Pos                                  (16UL)         /*!< LTR_MECHANISM (Bit 16)                                */
+ #define R_PCIE0_PCI_EP_PEIS2_LTR_MECHANISM_Msk                                  (0x10000UL)    /*!< LTR_MECHANISM (Bitfield-Mask: 0x01)                   */
+/* ======================================================  PCI_EP_PERM  ====================================================== */
+ #define R_PCIE0_PCI_EP_PERM_PHY_REG_CLK_EN_Pos                                  (1UL)          /*!< PHY_REG_CLK_EN (Bit 1)                                */
+ #define R_PCIE0_PCI_EP_PERM_PHY_REG_CLK_EN_Msk                                  (0x2UL)        /*!< PHY_REG_CLK_EN (Bitfield-Mask: 0x01)                  */
+/* ======================================================  PCI_RC_PERM  ====================================================== */
+ #define R_PCIE0_PCI_RC_PERM_PHY_REG_CLK_EN_Pos                                  (1UL)          /*!< PHY_REG_CLK_EN (Bit 1)                                */
+ #define R_PCIE0_PCI_RC_PERM_PHY_REG_CLK_EN_Msk                                  (0x2UL)        /*!< PHY_REG_CLK_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_PERM_CFG_HWINIT_EN_Pos                                   (2UL)          /*!< CFG_HWINIT_EN (Bit 2)                                 */
+ #define R_PCIE0_PCI_RC_PERM_CFG_HWINIT_EN_Msk                                   (0x4UL)        /*!< CFG_HWINIT_EN (Bitfield-Mask: 0x01)                   */
+/* =====================================================  PCI_EP_RESET  ====================================================== */
+ #define R_PCIE0_PCI_EP_RESET_RST_B_Pos                                          (0UL)          /*!< RST_B (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_RESET_RST_B_Msk                                          (0x1UL)        /*!< RST_B (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_RESET_RST_GP_B_Pos                                       (1UL)          /*!< RST_GP_B (Bit 1)                                      */
+ #define R_PCIE0_PCI_EP_RESET_RST_GP_B_Msk                                       (0x2UL)        /*!< RST_GP_B (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_RESET_RST_RSM_B_Pos                                      (2UL)          /*!< RST_RSM_B (Bit 2)                                     */
+ #define R_PCIE0_PCI_EP_RESET_RST_RSM_B_Msk                                      (0x4UL)        /*!< RST_RSM_B (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_EP_RESET_RST_CFG_B_Pos                                      (3UL)          /*!< RST_CFG_B (Bit 3)                                     */
+ #define R_PCIE0_PCI_EP_RESET_RST_CFG_B_Msk                                      (0x8UL)        /*!< RST_CFG_B (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_EP_RESET_RST_LOAD_B_Pos                                     (4UL)          /*!< RST_LOAD_B (Bit 4)                                    */
+ #define R_PCIE0_PCI_EP_RESET_RST_LOAD_B_Msk                                     (0x10UL)       /*!< RST_LOAD_B (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_RESET_RST_PS_B_Pos                                       (5UL)          /*!< RST_PS_B (Bit 5)                                      */
+ #define R_PCIE0_PCI_EP_RESET_RST_PS_B_Msk                                       (0x20UL)       /*!< RST_PS_B (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_RESET_RST_OUT_B_Pos                                      (6UL)          /*!< RST_OUT_B (Bit 6)                                     */
+ #define R_PCIE0_PCI_EP_RESET_RST_OUT_B_Msk                                      (0x40UL)       /*!< RST_OUT_B (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_EP_RESET_RST_PREG_B_Pos                                     (7UL)          /*!< RST_PREG_B (Bit 7)                                    */
+ #define R_PCIE0_PCI_EP_RESET_RST_PREG_B_Msk                                     (0x80UL)       /*!< RST_PREG_B (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_RESET_FTD0_Pos                                           (16UL)         /*!< FTD0 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_RESET_FTD0_Msk                                           (0x10000UL)    /*!< FTD0 (Bitfield-Mask: 0x01)                            */
+/* =====================================================  PCI_RC_RESET  ====================================================== */
+ #define R_PCIE0_PCI_RC_RESET_RST_B_Pos                                          (0UL)          /*!< RST_B (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_RESET_RST_B_Msk                                          (0x1UL)        /*!< RST_B (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_RESET_RST_GP_B_Pos                                       (1UL)          /*!< RST_GP_B (Bit 1)                                      */
+ #define R_PCIE0_PCI_RC_RESET_RST_GP_B_Msk                                       (0x2UL)        /*!< RST_GP_B (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_RESET_RST_RSM_B_Pos                                      (2UL)          /*!< RST_RSM_B (Bit 2)                                     */
+ #define R_PCIE0_PCI_RC_RESET_RST_RSM_B_Msk                                      (0x4UL)        /*!< RST_RSM_B (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_RC_RESET_RST_CFG_B_Pos                                      (3UL)          /*!< RST_CFG_B (Bit 3)                                     */
+ #define R_PCIE0_PCI_RC_RESET_RST_CFG_B_Msk                                      (0x8UL)        /*!< RST_CFG_B (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_RC_RESET_RST_LOAD_B_Pos                                     (4UL)          /*!< RST_LOAD_B (Bit 4)                                    */
+ #define R_PCIE0_PCI_RC_RESET_RST_LOAD_B_Msk                                     (0x10UL)       /*!< RST_LOAD_B (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_RESET_RST_PS_B_Pos                                       (5UL)          /*!< RST_PS_B (Bit 5)                                      */
+ #define R_PCIE0_PCI_RC_RESET_RST_PS_B_Msk                                       (0x20UL)       /*!< RST_PS_B (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_RESET_RST_OUT_B_Pos                                      (6UL)          /*!< RST_OUT_B (Bit 6)                                     */
+ #define R_PCIE0_PCI_RC_RESET_RST_OUT_B_Msk                                      (0x40UL)       /*!< RST_OUT_B (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_RC_RESET_RST_PREG_B_Pos                                     (7UL)          /*!< RST_PREG_B (Bit 7)                                    */
+ #define R_PCIE0_PCI_RC_RESET_RST_PREG_B_Msk                                     (0x80UL)       /*!< RST_PREG_B (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_RESET_FTD0_Pos                                           (16UL)         /*!< FTD0 (Bit 16)                                         */
+ #define R_PCIE0_PCI_RC_RESET_FTD0_Msk                                           (0x10000UL)    /*!< FTD0 (Bitfield-Mask: 0x01)                            */
+/* =====================================================  PCI_EP_MSET0  ====================================================== */
+ #define R_PCIE0_PCI_EP_MSET0_ARCACHE_Pos                                        (0UL)          /*!< ARCACHE (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_MSET0_ARCACHE_Msk                                        (0xfUL)        /*!< ARCACHE (Bitfield-Mask: 0x0f)                         */
+ #define R_PCIE0_PCI_EP_MSET0_ARLOCK_Pos                                         (4UL)          /*!< ARLOCK (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_MSET0_ARLOCK_Msk                                         (0x30UL)       /*!< ARLOCK (Bitfield-Mask: 0x03)                          */
+ #define R_PCIE0_PCI_EP_MSET0_ARPROT_Pos                                         (12UL)         /*!< ARPROT (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_MSET0_ARPROT_Msk                                         (0x7000UL)     /*!< ARPROT (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_MSET0_AWCACHE_D_Pos                                      (16UL)         /*!< AWCACHE_D (Bit 16)                                    */
+ #define R_PCIE0_PCI_EP_MSET0_AWCACHE_D_Msk                                      (0xf0000UL)    /*!< AWCACHE_D (Bitfield-Mask: 0x0f)                       */
+ #define R_PCIE0_PCI_EP_MSET0_AWLOCK_Pos                                         (20UL)         /*!< AWLOCK (Bit 20)                                       */
+ #define R_PCIE0_PCI_EP_MSET0_AWLOCK_Msk                                         (0x300000UL)   /*!< AWLOCK (Bitfield-Mask: 0x03)                          */
+ #define R_PCIE0_PCI_EP_MSET0_AWCACHE_L_Pos                                      (24UL)         /*!< AWCACHE_L (Bit 24)                                    */
+ #define R_PCIE0_PCI_EP_MSET0_AWCACHE_L_Msk                                      (0xf000000UL)  /*!< AWCACHE_L (Bitfield-Mask: 0x0f)                       */
+ #define R_PCIE0_PCI_EP_MSET0_AWPROT_Pos                                         (28UL)         /*!< AWPROT (Bit 28)                                       */
+ #define R_PCIE0_PCI_EP_MSET0_AWPROT_Msk                                         (0x70000000UL) /*!< AWPROT (Bitfield-Mask: 0x07)                          */
+/* =====================================================  PCI_RC_MSET0  ====================================================== */
+ #define R_PCIE0_PCI_RC_MSET0_ARCACHE_Pos                                        (0UL)          /*!< ARCACHE (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_MSET0_ARCACHE_Msk                                        (0xfUL)        /*!< ARCACHE (Bitfield-Mask: 0x0f)                         */
+ #define R_PCIE0_PCI_RC_MSET0_ARLOCK_Pos                                         (4UL)          /*!< ARLOCK (Bit 4)                                        */
+ #define R_PCIE0_PCI_RC_MSET0_ARLOCK_Msk                                         (0x30UL)       /*!< ARLOCK (Bitfield-Mask: 0x03)                          */
+ #define R_PCIE0_PCI_RC_MSET0_ARPROT_Pos                                         (12UL)         /*!< ARPROT (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_MSET0_ARPROT_Msk                                         (0x7000UL)     /*!< ARPROT (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_MSET0_AWCACHE_D_Pos                                      (16UL)         /*!< AWCACHE_D (Bit 16)                                    */
+ #define R_PCIE0_PCI_RC_MSET0_AWCACHE_D_Msk                                      (0xf0000UL)    /*!< AWCACHE_D (Bitfield-Mask: 0x0f)                       */
+ #define R_PCIE0_PCI_RC_MSET0_AWLOCK_Pos                                         (20UL)         /*!< AWLOCK (Bit 20)                                       */
+ #define R_PCIE0_PCI_RC_MSET0_AWLOCK_Msk                                         (0x300000UL)   /*!< AWLOCK (Bitfield-Mask: 0x03)                          */
+ #define R_PCIE0_PCI_RC_MSET0_AWCACHE_L_Pos                                      (24UL)         /*!< AWCACHE_L (Bit 24)                                    */
+ #define R_PCIE0_PCI_RC_MSET0_AWCACHE_L_Msk                                      (0xf000000UL)  /*!< AWCACHE_L (Bitfield-Mask: 0x0f)                       */
+ #define R_PCIE0_PCI_RC_MSET0_AWPROT_Pos                                         (28UL)         /*!< AWPROT (Bit 28)                                       */
+ #define R_PCIE0_PCI_RC_MSET0_AWPROT_Msk                                         (0x70000000UL) /*!< AWPROT (Bitfield-Mask: 0x07)                          */
+/* =====================================================  PCI_EP_MSET1  ====================================================== */
+ #define R_PCIE0_PCI_EP_MSET1_PCIERO_Pos                                         (0UL)          /*!< PCIERO (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_MSET1_PCIERO_Msk                                         (0x1UL)        /*!< PCIERO (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_MSET1_RAMPE_Pos                                          (1UL)          /*!< RAMPE (Bit 1)                                         */
+ #define R_PCIE0_PCI_EP_MSET1_RAMPE_Msk                                          (0x2UL)        /*!< RAMPE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_MSET1_AXIMMB_Pos                                         (4UL)          /*!< AXIMMB (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_MSET1_AXIMMB_Msk                                         (0xf0UL)       /*!< AXIMMB (Bitfield-Mask: 0x0f)                          */
+ #define R_PCIE0_PCI_EP_MSET1_AXIMIR_Pos                                         (8UL)          /*!< AXIMIR (Bit 8)                                        */
+ #define R_PCIE0_PCI_EP_MSET1_AXIMIR_Msk                                         (0xf00UL)      /*!< AXIMIR (Bitfield-Mask: 0x0f)                          */
+ #define R_PCIE0_PCI_EP_MSET1_AXIMIW_Pos                                         (12UL)         /*!< AXIMIW (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_MSET1_AXIMIW_Msk                                         (0xf000UL)     /*!< AXIMIW (Bitfield-Mask: 0x0f)                          */
+/* =====================================================  PCI_RC_MSET1  ====================================================== */
+ #define R_PCIE0_PCI_RC_MSET1_PCIERO_Pos                                         (0UL)          /*!< PCIERO (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_MSET1_PCIERO_Msk                                         (0x1UL)        /*!< PCIERO (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_MSET1_RAMPE_Pos                                          (1UL)          /*!< RAMPE (Bit 1)                                         */
+ #define R_PCIE0_PCI_RC_MSET1_RAMPE_Msk                                          (0x2UL)        /*!< RAMPE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_MSET1_AXIMMB_Pos                                         (4UL)          /*!< AXIMMB (Bit 4)                                        */
+ #define R_PCIE0_PCI_RC_MSET1_AXIMMB_Msk                                         (0xf0UL)       /*!< AXIMMB (Bitfield-Mask: 0x0f)                          */
+ #define R_PCIE0_PCI_RC_MSET1_AXIMIR_Pos                                         (8UL)          /*!< AXIMIR (Bit 8)                                        */
+ #define R_PCIE0_PCI_RC_MSET1_AXIMIR_Msk                                         (0xf00UL)      /*!< AXIMIR (Bitfield-Mask: 0x0f)                          */
+ #define R_PCIE0_PCI_RC_MSET1_AXIMIW_Pos                                         (12UL)         /*!< AXIMIW (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_MSET1_AXIMIW_Msk                                         (0xf000UL)     /*!< AXIMIW (Bitfield-Mask: 0x0f)                          */
+/* =====================================================  PCI_EP_MSET3  ====================================================== */
+ #define R_PCIE0_PCI_EP_MSET3_ASPML1IT_Pos                                       (0UL)          /*!< ASPML1IT (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_MSET3_ASPML1IT_Msk                                       (0xffUL)       /*!< ASPML1IT (Bitfield-Mask: 0xff)                        */
+/* =====================================================  PCI_RC_MSET3  ====================================================== */
+ #define R_PCIE0_PCI_RC_MSET3_ASPML1IT_Pos                                       (0UL)          /*!< ASPML1IT (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_MSET3_ASPML1IT_Msk                                       (0xffUL)       /*!< ASPML1IT (Bitfield-Mask: 0xff)                        */
+/* =====================================================  PCI_EP_MSET4  ====================================================== */
+ #define R_PCIE0_PCI_EP_MSET4_UI_EQ_REQUEST_Pos                                  (0UL)          /*!< UI_EQ_REQUEST (Bit 0)                                 */
+ #define R_PCIE0_PCI_EP_MSET4_UI_EQ_REQUEST_Msk                                  (0x1UL)        /*!< UI_EQ_REQUEST (Bitfield-Mask: 0x01)                   */
+ #define R_PCIE0_PCI_EP_MSET4_UI_EQ_REQTYPE_Pos                                  (1UL)          /*!< UI_EQ_REQTYPE (Bit 1)                                 */
+ #define R_PCIE0_PCI_EP_MSET4_UI_EQ_REQTYPE_Msk                                  (0x6UL)        /*!< UI_EQ_REQTYPE (Bitfield-Mask: 0x03)                   */
+ #define R_PCIE0_PCI_EP_MSET4_MODE_EQ_AUTONOMOUS1_Pos                            (5UL)          /*!< MODE_EQ_AUTONOMOUS1 (Bit 5)                           */
+ #define R_PCIE0_PCI_EP_MSET4_MODE_EQ_AUTONOMOUS1_Msk                            (0x20UL)       /*!< MODE_EQ_AUTONOMOUS1 (Bitfield-Mask: 0x01)             */
+ #define R_PCIE0_PCI_EP_MSET4_MODE_EQ_PHASE23_ENABLE1_Pos                        (6UL)          /*!< MODE_EQ_PHASE23_ENABLE1 (Bit 6)                       */
+ #define R_PCIE0_PCI_EP_MSET4_MODE_EQ_PHASE23_ENABLE1_Msk                        (0x40UL)       /*!< MODE_EQ_PHASE23_ENABLE1 (Bitfield-Mask: 0x01)         */
+ #define R_PCIE0_PCI_EP_MSET4_MODE_8GT_EQTS2_Pos                                 (7UL)          /*!< MODE_8GT_EQTS2 (Bit 7)                                */
+ #define R_PCIE0_PCI_EP_MSET4_MODE_8GT_EQTS2_Msk                                 (0x80UL)       /*!< MODE_8GT_EQTS2 (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_MSET4_MODE_EQ_RX_EVAL_WAIT_Pos                           (12UL)         /*!< MODE_EQ_RX_EVAL_WAIT (Bit 12)                         */
+ #define R_PCIE0_PCI_EP_MSET4_MODE_EQ_RX_EVAL_WAIT_Msk                           (0xfffff000UL) /*!< MODE_EQ_RX_EVAL_WAIT (Bitfield-Mask: 0xfffff)        */
+/* =====================================================  PCI_RC_MSET4  ====================================================== */
+ #define R_PCIE0_PCI_RC_MSET4_UI_EQ_REQUEST_Pos                                  (0UL)          /*!< UI_EQ_REQUEST (Bit 0)                                 */
+ #define R_PCIE0_PCI_RC_MSET4_UI_EQ_REQUEST_Msk                                  (0x1UL)        /*!< UI_EQ_REQUEST (Bitfield-Mask: 0x01)                   */
+ #define R_PCIE0_PCI_RC_MSET4_UI_EQ_REQTYPE_Pos                                  (1UL)          /*!< UI_EQ_REQTYPE (Bit 1)                                 */
+ #define R_PCIE0_PCI_RC_MSET4_UI_EQ_REQTYPE_Msk                                  (0x6UL)        /*!< UI_EQ_REQTYPE (Bitfield-Mask: 0x03)                   */
+ #define R_PCIE0_PCI_RC_MSET4_MODE_EQ_AUTONOMOUS1_Pos                            (5UL)          /*!< MODE_EQ_AUTONOMOUS1 (Bit 5)                           */
+ #define R_PCIE0_PCI_RC_MSET4_MODE_EQ_AUTONOMOUS1_Msk                            (0x20UL)       /*!< MODE_EQ_AUTONOMOUS1 (Bitfield-Mask: 0x01)             */
+ #define R_PCIE0_PCI_RC_MSET4_MODE_EQ_PHASE23_ENABLE1_Pos                        (6UL)          /*!< MODE_EQ_PHASE23_ENABLE1 (Bit 6)                       */
+ #define R_PCIE0_PCI_RC_MSET4_MODE_EQ_PHASE23_ENABLE1_Msk                        (0x40UL)       /*!< MODE_EQ_PHASE23_ENABLE1 (Bitfield-Mask: 0x01)         */
+ #define R_PCIE0_PCI_RC_MSET4_MODE_8GT_EQTS2_Pos                                 (7UL)          /*!< MODE_8GT_EQTS2 (Bit 7)                                */
+ #define R_PCIE0_PCI_RC_MSET4_MODE_8GT_EQTS2_Msk                                 (0x80UL)       /*!< MODE_8GT_EQTS2 (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_MSET4_MODE_EQ_RX_EVAL_WAIT_Pos                           (12UL)         /*!< MODE_EQ_RX_EVAL_WAIT (Bit 12)                         */
+ #define R_PCIE0_PCI_RC_MSET4_MODE_EQ_RX_EVAL_WAIT_Msk                           (0xfffff000UL) /*!< MODE_EQ_RX_EVAL_WAIT (Bitfield-Mask: 0xfffff)        */
+/* =====================================================  PCI_EP_MSET5  ====================================================== */
+ #define R_PCIE0_PCI_EP_MSET5_MODE_8GT_EQTS2_PRESET_Pos                          (0UL)          /*!< MODE_8GT_EQTS2_PRESET (Bit 0)                         */
+ #define R_PCIE0_PCI_EP_MSET5_MODE_8GT_EQTS2_PRESET_Msk                          (0xffffUL)     /*!< MODE_8GT_EQTS2_PRESET (Bitfield-Mask: 0xffff)         */
+/* =====================================================  PCI_RC_MSET5  ====================================================== */
+ #define R_PCIE0_PCI_RC_MSET5_MODE_8GT_EQTS2_PRESET_Pos                          (0UL)          /*!< MODE_8GT_EQTS2_PRESET (Bit 0)                         */
+ #define R_PCIE0_PCI_RC_MSET5_MODE_8GT_EQTS2_PRESET_Msk                          (0xffffUL)     /*!< MODE_8GT_EQTS2_PRESET (Bitfield-Mask: 0xffff)         */
+/* =====================================================  PCI_EP_MSTAT0  ===================================================== */
+ #define R_PCIE0_PCI_EP_MSTAT0_UI_EQ_DONE_Pos                                    (0UL)          /*!< UI_EQ_DONE (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_MSTAT0_UI_EQ_DONE_Msk                                    (0x1UL)        /*!< UI_EQ_DONE (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_MSTAT0_RX_EQ_REQUEST_Pos                                 (1UL)          /*!< RX_EQ_REQUEST (Bit 1)                                 */
+ #define R_PCIE0_PCI_EP_MSTAT0_RX_EQ_REQUEST_Msk                                 (0x2UL)        /*!< RX_EQ_REQUEST (Bitfield-Mask: 0x01)                   */
+ #define R_PCIE0_PCI_EP_MSTAT0_RX_EQ_REQTYPE_Pos                                 (2UL)          /*!< RX_EQ_REQTYPE (Bit 2)                                 */
+ #define R_PCIE0_PCI_EP_MSTAT0_RX_EQ_REQTYPE_Msk                                 (0xcUL)        /*!< RX_EQ_REQTYPE (Bitfield-Mask: 0x03)                   */
+/* =====================================================  PCI_RC_MSTAT0  ===================================================== */
+ #define R_PCIE0_PCI_RC_MSTAT0_UI_EQ_DONE_Pos                                    (0UL)          /*!< UI_EQ_DONE (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_MSTAT0_UI_EQ_DONE_Msk                                    (0x1UL)        /*!< UI_EQ_DONE (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_MSTAT0_RX_EQ_REQUEST_Pos                                 (1UL)          /*!< RX_EQ_REQUEST (Bit 1)                                 */
+ #define R_PCIE0_PCI_RC_MSTAT0_RX_EQ_REQUEST_Msk                                 (0x2UL)        /*!< RX_EQ_REQUEST (Bitfield-Mask: 0x01)                   */
+ #define R_PCIE0_PCI_RC_MSTAT0_RX_EQ_REQTYPE_Pos                                 (2UL)          /*!< RX_EQ_REQTYPE (Bit 2)                                 */
+ #define R_PCIE0_PCI_RC_MSTAT0_RX_EQ_REQTYPE_Msk                                 (0xcUL)        /*!< RX_EQ_REQTYPE (Bitfield-Mask: 0x03)                   */
+/* ====================================================  PCI_EP_PCMSET1  ===================================================== */
+ #define R_PCIE0_PCI_EP_PCMSET1_MODE_PORT_Pos                                    (1UL)          /*!< MODE_PORT (Bit 1)                                     */
+ #define R_PCIE0_PCI_EP_PCMSET1_MODE_PORT_Msk                                    (0x2UL)        /*!< MODE_PORT (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_EP_PCMSET1_MODE_SELECTABLE_DEEMPHASIS_Pos                   (8UL)          /*!< MODE_SELECTABLE_DEEMPHASIS (Bit 8)                    */
+ #define R_PCIE0_PCI_EP_PCMSET1_MODE_SELECTABLE_DEEMPHASIS_Msk                   (0x100UL)      /*!< MODE_SELECTABLE_DEEMPHASIS (Bitfield-Mask: 0x01)  */
+ #define R_PCIE0_PCI_EP_PCMSET1_MODE_TXSWING_Pos                                 (10UL)         /*!< MODE_TXSWING (Bit 10)                                 */
+ #define R_PCIE0_PCI_EP_PCMSET1_MODE_TXSWING_Msk                                 (0x400UL)      /*!< MODE_TXSWING (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_PCMSET1_MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED_Pos    (12UL)         /*!< MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED (Bit 12) */
+ #define R_PCIE0_PCI_EP_PCMSET1_MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED_Msk    (0x1000UL)     /*!< MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PCMSET1_ASPM_L1_INTERVAL_TIME_Pos                        (16UL)         /*!< ASPM_L1_INTERVAL_TIME (Bit 16)                        */
+ #define R_PCIE0_PCI_EP_PCMSET1_ASPM_L1_INTERVAL_TIME_Msk                        (0xfff0000UL)  /*!< ASPM_L1_INTERVAL_TIME (Bitfield-Mask: 0xfff)       */
+/* ====================================================  PCI_RC_PCMSET1  ===================================================== */
+ #define R_PCIE0_PCI_RC_PCMSET1_MODE_PORT_Pos                                    (1UL)          /*!< MODE_PORT (Bit 1)                                     */
+ #define R_PCIE0_PCI_RC_PCMSET1_MODE_PORT_Msk                                    (0x2UL)        /*!< MODE_PORT (Bitfield-Mask: 0x01)                       */
+ #define R_PCIE0_PCI_RC_PCMSET1_MODE_TXSWING_Pos                                 (10UL)         /*!< MODE_TXSWING (Bit 10)                                 */
+ #define R_PCIE0_PCI_RC_PCMSET1_MODE_TXSWING_Msk                                 (0x400UL)      /*!< MODE_TXSWING (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_PCMSET1_MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED_Pos    (12UL)         /*!< MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED (Bit 12) */
+ #define R_PCIE0_PCI_RC_PCMSET1_MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED_Msk    (0x1000UL)     /*!< MODE_LINK_UPCONFIGURE_CAPABILITY_DISABLED (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PCMSET1_ASPM_L1_INTERVAL_TIME_Pos                        (16UL)         /*!< ASPM_L1_INTERVAL_TIME (Bit 16)                        */
+ #define R_PCIE0_PCI_RC_PCMSET1_ASPM_L1_INTERVAL_TIME_Msk                        (0xfff0000UL)  /*!< ASPM_L1_INTERVAL_TIME (Bitfield-Mask: 0xfff)       */
+/* ====================================================  PCI_EP_PCCTRL1  ===================================================== */
+ #define R_PCIE0_PCI_EP_PCCTRL1_MODE_RESET_EIEOS_INTERVALL0S_Pos                 (8UL)          /*!< MODE_RESET_EIEOS_INTERVALL0S (Bit 8)                */
+ #define R_PCIE0_PCI_EP_PCCTRL1_MODE_RESET_EIEOS_INTERVALL0S_Msk                 (0x100UL)      /*!< MODE_RESET_EIEOS_INTERVALL0S (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PCCTRL1_MODE_EQ_PHASE23_ENABLE_Pos                       (9UL)          /*!< MODE_EQ_PHASE23_ENABLE (Bit 9)                        */
+ #define R_PCIE0_PCI_EP_PCCTRL1_MODE_EQ_PHASE23_ENABLE_Msk                       (0x200UL)      /*!< MODE_EQ_PHASE23_ENABLE (Bitfield-Mask: 0x01)          */
+ #define R_PCIE0_PCI_EP_PCCTRL1_MODE_EQ_AUTONOMOUS_Pos                           (10UL)         /*!< MODE_EQ_AUTONOMOUS (Bit 10)                           */
+ #define R_PCIE0_PCI_EP_PCCTRL1_MODE_EQ_AUTONOMOUS_Msk                           (0x400UL)      /*!< MODE_EQ_AUTONOMOUS (Bitfield-Mask: 0x01)              */
+ #define R_PCIE0_PCI_EP_PCCTRL1_UI_ENTER_TXMODE_SRIS_Pos                         (11UL)         /*!< UI_ENTER_TXMODE_SRIS (Bit 11)                         */
+ #define R_PCIE0_PCI_EP_PCCTRL1_UI_ENTER_TXMODE_SRIS_Msk                         (0x800UL)      /*!< UI_ENTER_TXMODE_SRIS (Bitfield-Mask: 0x01)            */
+ #define R_PCIE0_PCI_EP_PCCTRL1_MODE_QUIESCE_GUARANTEE_Pos                       (12UL)         /*!< MODE_QUIESCE_GUARANTEE (Bit 12)                       */
+ #define R_PCIE0_PCI_EP_PCCTRL1_MODE_QUIESCE_GUARANTEE_Msk                       (0x1000UL)     /*!< MODE_QUIESCE_GUARANTEE (Bitfield-Mask: 0x01)         */
+ #define R_PCIE0_PCI_EP_PCCTRL1_UI_ENTER_TXL0S_Pos                               (16UL)         /*!< UI_ENTER_TXL0S (Bit 16)                               */
+ #define R_PCIE0_PCI_EP_PCCTRL1_UI_ENTER_TXL0S_Msk                               (0x10000UL)    /*!< UI_ENTER_TXL0S (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_PCCTRL1_UI_ENTER_L1_STATUS_Pos                           (21UL)         /*!< UI_ENTER_L1_STATUS (Bit 21)                           */
+ #define R_PCIE0_PCI_EP_PCCTRL1_UI_ENTER_L1_STATUS_Msk                           (0x200000UL)   /*!< UI_ENTER_L1_STATUS (Bitfield-Mask: 0x01)              */
+ #define R_PCIE0_PCI_EP_PCCTRL1_UI_ENTER_L1S_Pos                                 (22UL)         /*!< UI_ENTER_L1S (Bit 22)                                 */
+ #define R_PCIE0_PCI_EP_PCCTRL1_UI_ENTER_L1S_Msk                                 (0x400000UL)   /*!< UI_ENTER_L1S (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_PCCTRL1_BLB_RELAX_ORDERING_EN_Pos                        (28UL)         /*!< BLB_RELAX_ORDERING_EN (Bit 28)                        */
+ #define R_PCIE0_PCI_EP_PCCTRL1_BLB_RELAX_ORDERING_EN_Msk                        (0x10000000UL) /*!< BLB_RELAX_ORDERING_EN (Bitfield-Mask: 0x01)       */
+/* ====================================================  PCI_RC_PCCTRL1  ===================================================== */
+ #define R_PCIE0_PCI_RC_PCCTRL1_MODE_RESET_EIEOS_INTERVALL0S_Pos                 (8UL)          /*!< MODE_RESET_EIEOS_INTERVALL0S (Bit 8)                */
+ #define R_PCIE0_PCI_RC_PCCTRL1_MODE_RESET_EIEOS_INTERVALL0S_Msk                 (0x100UL)      /*!< MODE_RESET_EIEOS_INTERVALL0S (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PCCTRL1_MODE_EQ_PHASE23_ENABLE_Pos                       (9UL)          /*!< MODE_EQ_PHASE23_ENABLE (Bit 9)                        */
+ #define R_PCIE0_PCI_RC_PCCTRL1_MODE_EQ_PHASE23_ENABLE_Msk                       (0x200UL)      /*!< MODE_EQ_PHASE23_ENABLE (Bitfield-Mask: 0x01)          */
+ #define R_PCIE0_PCI_RC_PCCTRL1_MODE_EQ_AUTONOMOUS_Pos                           (10UL)         /*!< MODE_EQ_AUTONOMOUS (Bit 10)                           */
+ #define R_PCIE0_PCI_RC_PCCTRL1_MODE_EQ_AUTONOMOUS_Msk                           (0x400UL)      /*!< MODE_EQ_AUTONOMOUS (Bitfield-Mask: 0x01)              */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_ENTER_TXMODE_SRIS_Pos                         (11UL)         /*!< UI_ENTER_TXMODE_SRIS (Bit 11)                         */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_ENTER_TXMODE_SRIS_Msk                         (0x800UL)      /*!< UI_ENTER_TXMODE_SRIS (Bitfield-Mask: 0x01)            */
+ #define R_PCIE0_PCI_RC_PCCTRL1_MODE_QUIESCE_GUARANTEE_Pos                       (12UL)         /*!< MODE_QUIESCE_GUARANTEE (Bit 12)                       */
+ #define R_PCIE0_PCI_RC_PCCTRL1_MODE_QUIESCE_GUARANTEE_Msk                       (0x1000UL)     /*!< MODE_QUIESCE_GUARANTEE (Bitfield-Mask: 0x01)         */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_ENTER_TXL0S_Pos                               (16UL)         /*!< UI_ENTER_TXL0S (Bit 16)                               */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_ENTER_TXL0S_Msk                               (0x10000UL)    /*!< UI_ENTER_TXL0S (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_ENTER_L2_Pos                                  (17UL)         /*!< UI_ENTER_L2 (Bit 17)                                  */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_ENTER_L2_Msk                                  (0x20000UL)    /*!< UI_ENTER_L2 (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_PCCTRL1_APMASN_Pos                                       (18UL)         /*!< APMASN (Bit 18)                                       */
+ #define R_PCIE0_PCI_RC_PCCTRL1_APMASN_Msk                                       (0x40000UL)    /*!< APMASN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_RC_REJECT_ASPML1_Pos                          (19UL)         /*!< UI_RC_REJECT_ASPML1 (Bit 19)                          */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_RC_REJECT_ASPML1_Msk                          (0x80000UL)    /*!< UI_RC_REJECT_ASPML1 (Bitfield-Mask: 0x01)             */
+ #define R_PCIE0_PCI_RC_PCCTRL1_RETURN_TO_L0_Pos                                 (20UL)         /*!< RETURN_TO_L0 (Bit 20)                                 */
+ #define R_PCIE0_PCI_RC_PCCTRL1_RETURN_TO_L0_Msk                                 (0x100000UL)   /*!< RETURN_TO_L0 (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_ENTER_L1S_Pos                                 (22UL)         /*!< UI_ENTER_L1S (Bit 22)                                 */
+ #define R_PCIE0_PCI_RC_PCCTRL1_UI_ENTER_L1S_Msk                                 (0x400000UL)   /*!< UI_ENTER_L1S (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_PCCTRL1_BLB_RELAX_ORDERING_EN_Pos                        (28UL)         /*!< BLB_RELAX_ORDERING_EN (Bit 28)                        */
+ #define R_PCIE0_PCI_RC_PCCTRL1_BLB_RELAX_ORDERING_EN_Msk                        (0x10000000UL) /*!< BLB_RELAX_ORDERING_EN (Bitfield-Mask: 0x01)       */
+/* ====================================================  PCI_EP_PCSTAT1  ===================================================== */
+ #define R_PCIE0_PCI_EP_PCSTAT1_DLDS_Pos                                         (0UL)          /*!< DLDS (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_PCSTAT1_DLDS_Msk                                         (0x1UL)        /*!< DLDS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_PCSTAT1_STATE_VC0_NEGOTIATION_PENDING_Pos                (1UL)          /*!< STATE_VC0_NEGOTIATION_PENDING (Bit 1)              */
+ #define R_PCIE0_PCI_EP_PCSTAT1_STATE_VC0_NEGOTIATION_PENDING_Msk                (0x2UL)        /*!< STATE_VC0_NEGOTIATION_PENDING (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PCSTAT1_PMU_LINKSTATE_Pos                                (4UL)          /*!< PMU_LINKSTATE (Bit 4)                                 */
+ #define R_PCIE0_PCI_EP_PCSTAT1_PMU_LINKSTATE_Msk                                (0xf0UL)       /*!< PMU_LINKSTATE (Bitfield-Mask: 0x0f)                   */
+ #define R_PCIE0_PCI_EP_PCSTAT1_LTSSM_STATE_Pos                                  (8UL)          /*!< LTSSM_STATE (Bit 8)                                   */
+ #define R_PCIE0_PCI_EP_PCSTAT1_LTSSM_STATE_Msk                                  (0x7f00UL)     /*!< LTSSM_STATE (Bitfield-Mask: 0x7f)                     */
+ #define R_PCIE0_PCI_EP_PCSTAT1_BD_Pos                                           (17UL)         /*!< BD (Bit 17)                                           */
+ #define R_PCIE0_PCI_EP_PCSTAT1_BD_Msk                                           (0x20000UL)    /*!< BD (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_PCSTAT1_TURN_OFF_EVENT_Pos                               (26UL)         /*!< TURN_OFF_EVENT (Bit 26)                               */
+ #define R_PCIE0_PCI_EP_PCSTAT1_TURN_OFF_EVENT_Msk                               (0x4000000UL)  /*!< TURN_OFF_EVENT (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_PCSTAT1_TURN_OFF_EVENT_ACK_Pos                           (27UL)         /*!< TURN_OFF_EVENT_ACK (Bit 27)                           */
+ #define R_PCIE0_PCI_EP_PCSTAT1_TURN_OFF_EVENT_ACK_Msk                           (0x8000000UL)  /*!< TURN_OFF_EVENT_ACK (Bitfield-Mask: 0x01)              */
+/* ====================================================  PCI_RC_PCSTAT1  ===================================================== */
+ #define R_PCIE0_PCI_RC_PCSTAT1_DLDS_Pos                                         (0UL)          /*!< DLDS (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_PCSTAT1_DLDS_Msk                                         (0x1UL)        /*!< DLDS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_PCSTAT1_STATE_VC0_NEGOTIATION_PENDING_Pos                (1UL)          /*!< STATE_VC0_NEGOTIATION_PENDING (Bit 1)              */
+ #define R_PCIE0_PCI_RC_PCSTAT1_STATE_VC0_NEGOTIATION_PENDING_Msk                (0x2UL)        /*!< STATE_VC0_NEGOTIATION_PENDING (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PCSTAT1_PMU_LINKSTATE_Pos                                (4UL)          /*!< PMU_LINKSTATE (Bit 4)                                 */
+ #define R_PCIE0_PCI_RC_PCSTAT1_PMU_LINKSTATE_Msk                                (0xf0UL)       /*!< PMU_LINKSTATE (Bitfield-Mask: 0x0f)                   */
+ #define R_PCIE0_PCI_RC_PCSTAT1_LTSSM_STATE_Pos                                  (8UL)          /*!< LTSSM_STATE (Bit 8)                                   */
+ #define R_PCIE0_PCI_RC_PCSTAT1_LTSSM_STATE_Msk                                  (0x7f00UL)     /*!< LTSSM_STATE (Bitfield-Mask: 0x7f)                     */
+ #define R_PCIE0_PCI_RC_PCSTAT1_BD_Pos                                           (17UL)         /*!< BD (Bit 17)                                           */
+ #define R_PCIE0_PCI_RC_PCSTAT1_BD_Msk                                           (0x20000UL)    /*!< BD (Bitfield-Mask: 0x01)                              */
+/* ====================================================  PCI_EP_PCCTRL2  ===================================================== */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_SPEED_CHANGE_REQ_Pos                     (0UL)          /*!< UI_LINK_SPEED_CHANGE_REQ (Bit 0)                      */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_SPEED_CHANGE_REQ_Msk                     (0x1UL)        /*!< UI_LINK_SPEED_CHANGE_REQ (Bitfield-Mask: 0x01)        */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_CHANGE_AUTONOMOUS_Pos                    (4UL)          /*!< UI_LINK_CHANGE_AUTONOMOUS (Bit 4)                     */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_CHANGE_AUTONOMOUS_Msk                    (0x10UL)       /*!< UI_LINK_CHANGE_AUTONOMOUS (Bitfield-Mask: 0x01)     */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_SPEED_CHANGE_Pos                         (8UL)          /*!< UI_LINK_SPEED_CHANGE (Bit 8)                          */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_SPEED_CHANGE_Msk                         (0x300UL)      /*!< UI_LINK_SPEED_CHANGE (Bitfield-Mask: 0x03)            */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_WIDTH_CHANGE_REQ_Pos                     (16UL)         /*!< UI_LINK_WIDTH_CHANGE_REQ (Bit 16)                     */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_WIDTH_CHANGE_REQ_Msk                     (0x10000UL)    /*!< UI_LINK_WIDTH_CHANGE_REQ (Bitfield-Mask: 0x01)    */
+ #define R_PCIE0_PCI_EP_PCCTRL2_MODE_PRESET_ENABLE_Pos                           (17UL)         /*!< MODE_PRESET_ENABLE (Bit 17)                           */
+ #define R_PCIE0_PCI_EP_PCCTRL2_MODE_PRESET_ENABLE_Msk                           (0x3e0000UL)   /*!< MODE_PRESET_ENABLE (Bitfield-Mask: 0x1f)              */
+ #define R_PCIE0_PCI_EP_PCCTRL2_MODE_NODEEMPHASIS_Pos                            (22UL)         /*!< MODE_NODEEMPHASIS (Bit 22)                            */
+ #define R_PCIE0_PCI_EP_PCCTRL2_MODE_NODEEMPHASIS_Msk                            (0xc00000UL)   /*!< MODE_NODEEMPHASIS (Bitfield-Mask: 0x03)               */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_WIDTH_CHANGE_ENABLE_Pos                  (24UL)         /*!< UI_LINK_WIDTH_CHANGE_ENABLE (Bit 24)                */
+ #define R_PCIE0_PCI_EP_PCCTRL2_UI_LINK_WIDTH_CHANGE_ENABLE_Msk                  (0xff000000UL) /*!< UI_LINK_WIDTH_CHANGE_ENABLE (Bitfield-Mask: 0xff) */
+/* ====================================================  PCI_RC_PCCTRL2  ===================================================== */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_SPEED_CHANGE_REQ_Pos                     (0UL)          /*!< UI_LINK_SPEED_CHANGE_REQ (Bit 0)                      */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_SPEED_CHANGE_REQ_Msk                     (0x1UL)        /*!< UI_LINK_SPEED_CHANGE_REQ (Bitfield-Mask: 0x01)        */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_CHANGE_AUTONOMOUS_Pos                    (4UL)          /*!< UI_LINK_CHANGE_AUTONOMOUS (Bit 4)                     */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_CHANGE_AUTONOMOUS_Msk                    (0x10UL)       /*!< UI_LINK_CHANGE_AUTONOMOUS (Bitfield-Mask: 0x01)     */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_SPEED_CHANGE_Pos                         (8UL)          /*!< UI_LINK_SPEED_CHANGE (Bit 8)                          */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_SPEED_CHANGE_Msk                         (0x300UL)      /*!< UI_LINK_SPEED_CHANGE (Bitfield-Mask: 0x03)            */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_WIDTH_CHANGE_REQ_Pos                     (16UL)         /*!< UI_LINK_WIDTH_CHANGE_REQ (Bit 16)                     */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_WIDTH_CHANGE_REQ_Msk                     (0x10000UL)    /*!< UI_LINK_WIDTH_CHANGE_REQ (Bitfield-Mask: 0x01)    */
+ #define R_PCIE0_PCI_RC_PCCTRL2_MODE_PRESET_ENABLE_Pos                           (17UL)         /*!< MODE_PRESET_ENABLE (Bit 17)                           */
+ #define R_PCIE0_PCI_RC_PCCTRL2_MODE_PRESET_ENABLE_Msk                           (0x3e0000UL)   /*!< MODE_PRESET_ENABLE (Bitfield-Mask: 0x1f)              */
+ #define R_PCIE0_PCI_RC_PCCTRL2_MODE_NODEEMPHASIS_Pos                            (22UL)         /*!< MODE_NODEEMPHASIS (Bit 22)                            */
+ #define R_PCIE0_PCI_RC_PCCTRL2_MODE_NODEEMPHASIS_Msk                            (0xc00000UL)   /*!< MODE_NODEEMPHASIS (Bitfield-Mask: 0x03)               */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_WIDTH_CHANGE_ENABLE_Pos                  (24UL)         /*!< UI_LINK_WIDTH_CHANGE_ENABLE (Bit 24)                */
+ #define R_PCIE0_PCI_RC_PCCTRL2_UI_LINK_WIDTH_CHANGE_ENABLE_Msk                  (0xff000000UL) /*!< UI_LINK_WIDTH_CHANGE_ENABLE (Bitfield-Mask: 0xff) */
+/* ====================================================  PCI_EP_PCSTAT2  ===================================================== */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_DATA_RATE_IDENTIFIER_RECEIVED_Pos          (0UL)          /*!< STATE_DATA_RATE_IDENTIFIER_RECEIVED (Bit 0)  */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_DATA_RATE_IDENTIFIER_RECEIVED_Msk          (0xffUL)       /*!< STATE_DATA_RATE_IDENTIFIER_RECEIVED (Bitfield-Mask: 0xff) */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_RECEIVER_DETECTED_Pos                      (8UL)          /*!< STATE_RECEIVER_DETECTED (Bit 8)                       */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_RECEIVER_DETECTED_Msk                      (0xff00UL)     /*!< STATE_RECEIVER_DETECTED (Bitfield-Mask: 0xff)       */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_NEGOTIATED_LANE_START_Pos                  (16UL)         /*!< STATE_NEGOTIATED_LANE_START (Bit 16)                */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_NEGOTIATED_LANE_START_Msk                  (0x70000UL)    /*!< STATE_NEGOTIATED_LANE_START (Bitfield-Mask: 0x07) */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_NEGOTIATED_LANE_END_Pos                    (20UL)         /*!< STATE_NEGOTIATED_LANE_END (Bit 20)                    */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_NEGOTIATED_LANE_END_Msk                    (0x700000UL)   /*!< STATE_NEGOTIATED_LANE_END (Bitfield-Mask: 0x07) */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_UPCONFIGURE_CAPABLE_Pos                    (24UL)         /*!< STATE_UPCONFIGURE_CAPABLE (Bit 24)                    */
+ #define R_PCIE0_PCI_EP_PCSTAT2_STATE_UPCONFIGURE_CAPABLE_Msk                    (0x1000000UL)  /*!< STATE_UPCONFIGURE_CAPABLE (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PCSTAT2_UI_LINK_SPEED_CHANGE_DONE_Pos                    (28UL)         /*!< UI_LINK_SPEED_CHANGE_DONE (Bit 28)                    */
+ #define R_PCIE0_PCI_EP_PCSTAT2_UI_LINK_SPEED_CHANGE_DONE_Msk                    (0x10000000UL) /*!< UI_LINK_SPEED_CHANGE_DONE (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_EP_PCSTAT2_UI_LINK_WIDTH_CHANGE_DONE_Pos                    (29UL)         /*!< UI_LINK_WIDTH_CHANGE_DONE (Bit 29)                    */
+ #define R_PCIE0_PCI_EP_PCSTAT2_UI_LINK_WIDTH_CHANGE_DONE_Msk                    (0x20000000UL) /*!< UI_LINK_WIDTH_CHANGE_DONE (Bitfield-Mask: 0x01) */
+/* ====================================================  PCI_RC_PCSTAT2  ===================================================== */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_DATA_RATE_IDENTIFIER_RECEIVED_Pos          (0UL)          /*!< STATE_DATA_RATE_IDENTIFIER_RECEIVED (Bit 0)  */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_DATA_RATE_IDENTIFIER_RECEIVED_Msk          (0xffUL)       /*!< STATE_DATA_RATE_IDENTIFIER_RECEIVED (Bitfield-Mask: 0xff) */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_RECEIVER_DETECTED_Pos                      (8UL)          /*!< STATE_RECEIVER_DETECTED (Bit 8)                       */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_RECEIVER_DETECTED_Msk                      (0xff00UL)     /*!< STATE_RECEIVER_DETECTED (Bitfield-Mask: 0xff)       */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_NEGOTIATED_LANE_START_Pos                  (16UL)         /*!< STATE_NEGOTIATED_LANE_START (Bit 16)                */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_NEGOTIATED_LANE_START_Msk                  (0x70000UL)    /*!< STATE_NEGOTIATED_LANE_START (Bitfield-Mask: 0x07) */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_NEGOTIATED_LANE_END_Pos                    (20UL)         /*!< STATE_NEGOTIATED_LANE_END (Bit 20)                    */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_NEGOTIATED_LANE_END_Msk                    (0x700000UL)   /*!< STATE_NEGOTIATED_LANE_END (Bitfield-Mask: 0x07) */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_UPCONFIGURE_CAPABLE_Pos                    (24UL)         /*!< STATE_UPCONFIGURE_CAPABLE (Bit 24)                    */
+ #define R_PCIE0_PCI_RC_PCSTAT2_STATE_UPCONFIGURE_CAPABLE_Msk                    (0x1000000UL)  /*!< STATE_UPCONFIGURE_CAPABLE (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PCSTAT2_UI_LINK_SPEED_CHANGE_DONE_Pos                    (28UL)         /*!< UI_LINK_SPEED_CHANGE_DONE (Bit 28)                    */
+ #define R_PCIE0_PCI_RC_PCSTAT2_UI_LINK_SPEED_CHANGE_DONE_Msk                    (0x10000000UL) /*!< UI_LINK_SPEED_CHANGE_DONE (Bitfield-Mask: 0x01) */
+ #define R_PCIE0_PCI_RC_PCSTAT2_UI_LINK_WIDTH_CHANGE_DONE_Pos                    (29UL)         /*!< UI_LINK_WIDTH_CHANGE_DONE (Bit 29)                    */
+ #define R_PCIE0_PCI_RC_PCSTAT2_UI_LINK_WIDTH_CHANGE_DONE_Msk                    (0x20000000UL) /*!< UI_LINK_WIDTH_CHANGE_DONE (Bitfield-Mask: 0x01) */
+/* ====================================================  PCI_EP_PCSTAT5  ===================================================== */
+ #define R_PCIE0_PCI_EP_PCSTAT5_ORT_TRANSACTION_PENDING_Pos                      (0UL)          /*!< ORT_TRANSACTION_PENDING (Bit 0)                       */
+ #define R_PCIE0_PCI_EP_PCSTAT5_ORT_TRANSACTION_PENDING_Msk                      (0xffUL)       /*!< ORT_TRANSACTION_PENDING (Bitfield-Mask: 0xff)         */
+ #define R_PCIE0_PCI_EP_PCSTAT5_D3_EVENT_ACK_Pos                                 (8UL)          /*!< D3_EVENT_ACK (Bit 8)                                  */
+ #define R_PCIE0_PCI_EP_PCSTAT5_D3_EVENT_ACK_Msk                                 (0xff00UL)     /*!< D3_EVENT_ACK (Bitfield-Mask: 0xff)                    */
+ #define R_PCIE0_PCI_EP_PCSTAT5_D3_EVENT_Pos                                     (16UL)         /*!< D3_EVENT (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_PCSTAT5_D3_EVENT_Msk                                     (0xff0000UL)   /*!< D3_EVENT (Bitfield-Mask: 0xff)                        */
+ #define R_PCIE0_PCI_EP_PCSTAT5_SBME_Pos                                         (24UL)         /*!< SBME (Bit 24)                                         */
+ #define R_PCIE0_PCI_EP_PCSTAT5_SBME_Msk                                         (0xff000000UL) /*!< SBME (Bitfield-Mask: 0xff)                            */
+/* ====================================================  PCI_RC_PCSTAT5  ===================================================== */
+ #define R_PCIE0_PCI_RC_PCSTAT5_ORT_TRANSACTION_PENDING_Pos                      (0UL)          /*!< ORT_TRANSACTION_PENDING (Bit 0)                       */
+ #define R_PCIE0_PCI_RC_PCSTAT5_ORT_TRANSACTION_PENDING_Msk                      (0x3UL)        /*!< ORT_TRANSACTION_PENDING (Bitfield-Mask: 0x03)         */
+/* ===================================================  PCI_EP_DMAINTVEC0  =================================================== */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH0_V_Pos                                 (0UL)          /*!< DMA_CH0_V (Bit 0)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH0_V_Msk                                 (0x1fUL)       /*!< DMA_CH0_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH0_MSI_EN_Pos                            (5UL)          /*!< DMA_CH0_MSI_EN (Bit 5)                                */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH0_MSI_EN_Msk                            (0x20UL)       /*!< DMA_CH0_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH1_V_Pos                                 (8UL)          /*!< DMA_CH1_V (Bit 8)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH1_V_Msk                                 (0x1f00UL)     /*!< DMA_CH1_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH1_MSI_EN_Pos                            (13UL)         /*!< DMA_CH1_MSI_EN (Bit 13)                               */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH1_MSI_EN_Msk                            (0x2000UL)     /*!< DMA_CH1_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH2_V_Pos                                 (16UL)         /*!< DMA_CH2_V (Bit 16)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH2_V_Msk                                 (0x1f0000UL)   /*!< DMA_CH2_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH2_MSI_EN_Pos                            (21UL)         /*!< DMA_CH2_MSI_EN (Bit 21)                               */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH2_MSI_EN_Msk                            (0x200000UL)   /*!< DMA_CH2_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH3_V_Pos                                 (24UL)         /*!< DMA_CH3_V (Bit 24)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH3_V_Msk                                 (0x1f000000UL) /*!< DMA_CH3_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH3_MSI_EN_Pos                            (29UL)         /*!< DMA_CH3_MSI_EN (Bit 29)                               */
+ #define R_PCIE0_PCI_EP_DMAINTVEC0_DMA_CH3_MSI_EN_Msk                            (0x20000000UL) /*!< DMA_CH3_MSI_EN (Bitfield-Mask: 0x01)                  */
+/* ===================================================  PCI_RC_DMAINTVEC0  =================================================== */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH0_V_Pos                                 (0UL)          /*!< DMA_CH0_V (Bit 0)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH0_V_Msk                                 (0x1fUL)       /*!< DMA_CH0_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH0_MSI_EN_Pos                            (5UL)          /*!< DMA_CH0_MSI_EN (Bit 5)                                */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH0_MSI_EN_Msk                            (0x20UL)       /*!< DMA_CH0_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH1_V_Pos                                 (8UL)          /*!< DMA_CH1_V (Bit 8)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH1_V_Msk                                 (0x1f00UL)     /*!< DMA_CH1_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH1_MSI_EN_Pos                            (13UL)         /*!< DMA_CH1_MSI_EN (Bit 13)                               */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH1_MSI_EN_Msk                            (0x2000UL)     /*!< DMA_CH1_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH2_V_Pos                                 (16UL)         /*!< DMA_CH2_V (Bit 16)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH2_V_Msk                                 (0x1f0000UL)   /*!< DMA_CH2_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH2_MSI_EN_Pos                            (21UL)         /*!< DMA_CH2_MSI_EN (Bit 21)                               */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH2_MSI_EN_Msk                            (0x200000UL)   /*!< DMA_CH2_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH3_V_Pos                                 (24UL)         /*!< DMA_CH3_V (Bit 24)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH3_V_Msk                                 (0x1f000000UL) /*!< DMA_CH3_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH3_MSI_EN_Pos                            (29UL)         /*!< DMA_CH3_MSI_EN (Bit 29)                               */
+ #define R_PCIE0_PCI_RC_DMAINTVEC0_DMA_CH3_MSI_EN_Msk                            (0x20000000UL) /*!< DMA_CH3_MSI_EN (Bitfield-Mask: 0x01)                  */
+/* ===================================================  PCI_EP_DMAINTVEC1  =================================================== */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH4_V_Pos                                 (0UL)          /*!< DMA_CH4_V (Bit 0)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH4_V_Msk                                 (0x1fUL)       /*!< DMA_CH4_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH4_MSI_EN_Pos                            (5UL)          /*!< DMA_CH4_MSI_EN (Bit 5)                                */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH4_MSI_EN_Msk                            (0x20UL)       /*!< DMA_CH4_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH5_V_Pos                                 (8UL)          /*!< DMA_CH5_V (Bit 8)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH5_V_Msk                                 (0x1f00UL)     /*!< DMA_CH5_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH5_MSI_EN_Pos                            (13UL)         /*!< DMA_CH5_MSI_EN (Bit 13)                               */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH5_MSI_EN_Msk                            (0x2000UL)     /*!< DMA_CH5_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH6_V_Pos                                 (16UL)         /*!< DMA_CH6_V (Bit 16)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH6_V_Msk                                 (0x1f0000UL)   /*!< DMA_CH6_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH6_MSI_EN_Pos                            (21UL)         /*!< DMA_CH6_MSI_EN (Bit 21)                               */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH6_MSI_EN_Msk                            (0x200000UL)   /*!< DMA_CH6_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH7_V_Pos                                 (24UL)         /*!< DMA_CH7_V (Bit 24)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH7_V_Msk                                 (0x1f000000UL) /*!< DMA_CH7_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH7_MSI_EN_Pos                            (29UL)         /*!< DMA_CH7_MSI_EN (Bit 29)                               */
+ #define R_PCIE0_PCI_EP_DMAINTVEC1_DMA_CH7_MSI_EN_Msk                            (0x20000000UL) /*!< DMA_CH7_MSI_EN (Bitfield-Mask: 0x01)                  */
+/* ===================================================  PCI_RC_DMAINTVEC1  =================================================== */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH4_V_Pos                                 (0UL)          /*!< DMA_CH4_V (Bit 0)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH4_V_Msk                                 (0x1fUL)       /*!< DMA_CH4_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH4_MSI_EN_Pos                            (5UL)          /*!< DMA_CH4_MSI_EN (Bit 5)                                */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH4_MSI_EN_Msk                            (0x20UL)       /*!< DMA_CH4_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH5_V_Pos                                 (8UL)          /*!< DMA_CH5_V (Bit 8)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH5_V_Msk                                 (0x1f00UL)     /*!< DMA_CH5_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH5_MSI_EN_Pos                            (13UL)         /*!< DMA_CH5_MSI_EN (Bit 13)                               */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH5_MSI_EN_Msk                            (0x2000UL)     /*!< DMA_CH5_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH6_V_Pos                                 (16UL)         /*!< DMA_CH6_V (Bit 16)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH6_V_Msk                                 (0x1f0000UL)   /*!< DMA_CH6_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH6_MSI_EN_Pos                            (21UL)         /*!< DMA_CH6_MSI_EN (Bit 21)                               */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH6_MSI_EN_Msk                            (0x200000UL)   /*!< DMA_CH6_MSI_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH7_V_Pos                                 (24UL)         /*!< DMA_CH7_V (Bit 24)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH7_V_Msk                                 (0x1f000000UL) /*!< DMA_CH7_V (Bitfield-Mask: 0x1f)                       */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH7_MSI_EN_Pos                            (29UL)         /*!< DMA_CH7_MSI_EN (Bit 29)                               */
+ #define R_PCIE0_PCI_RC_DMAINTVEC1_DMA_CH7_MSI_EN_Msk                            (0x20000000UL) /*!< DMA_CH7_MSI_EN (Bitfield-Mask: 0x01)                  */
+/* ====================================================  PCI_EP_DMACTRL  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMACTRL_D_PMRS_Pos                                       (0UL)          /*!< D_PMRS (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_DMACTRL_D_PMRS_Msk                                       (0x7UL)        /*!< D_PMRS (Bitfield-Mask: 0x07)                          */
+/* ====================================================  PCI_RC_DMACTRL  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMACTRL_D_PMRS_Pos                                       (0UL)          /*!< D_PMRS (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_DMACTRL_D_PMRS_Msk                                       (0x7UL)        /*!< D_PMRS (Bitfield-Mask: 0x07)                          */
+/* ====================================================  PCI_EP_DMAINTE  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH0_END_EN_Pos                                   (0UL)          /*!< CH0_END_EN (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH0_END_EN_Msk                                   (0x1UL)        /*!< CH0_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH0_STOP_EN_Pos                                  (1UL)          /*!< CH0_STOP_EN (Bit 1)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH0_STOP_EN_Msk                                  (0x2UL)        /*!< CH0_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH0_QUE_EMP_EN_Pos                               (2UL)          /*!< CH0_QUE_EMP_EN (Bit 2)                                */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH0_QUE_EMP_EN_Msk                               (0x4UL)        /*!< CH0_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH0_ERR_EN_Pos                                   (3UL)          /*!< CH0_ERR_EN (Bit 3)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH0_ERR_EN_Msk                                   (0x8UL)        /*!< CH0_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH1_END_EN_Pos                                   (4UL)          /*!< CH1_END_EN (Bit 4)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH1_END_EN_Msk                                   (0x10UL)       /*!< CH1_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH1_STOP_EN_Pos                                  (5UL)          /*!< CH1_STOP_EN (Bit 5)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH1_STOP_EN_Msk                                  (0x20UL)       /*!< CH1_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH1_QUE_EMP_EN_Pos                               (6UL)          /*!< CH1_QUE_EMP_EN (Bit 6)                                */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH1_QUE_EMP_EN_Msk                               (0x40UL)       /*!< CH1_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH1_ERR_EN_Pos                                   (7UL)          /*!< CH1_ERR_EN (Bit 7)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH1_ERR_EN_Msk                                   (0x80UL)       /*!< CH1_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH2_END_EN_Pos                                   (8UL)          /*!< CH2_END_EN (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH2_END_EN_Msk                                   (0x100UL)      /*!< CH2_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH2_STOP_EN_Pos                                  (9UL)          /*!< CH2_STOP_EN (Bit 9)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH2_STOP_EN_Msk                                  (0x200UL)      /*!< CH2_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH2_QUE_EMP_EN_Pos                               (10UL)         /*!< CH2_QUE_EMP_EN (Bit 10)                               */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH2_QUE_EMP_EN_Msk                               (0x400UL)      /*!< CH2_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH2_ERR_EN_Pos                                   (11UL)         /*!< CH2_ERR_EN (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH2_ERR_EN_Msk                                   (0x800UL)      /*!< CH2_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH3_END_EN_Pos                                   (12UL)         /*!< CH3_END_EN (Bit 12)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH3_END_EN_Msk                                   (0x1000UL)     /*!< CH3_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH3_STOP_EN_Pos                                  (13UL)         /*!< CH3_STOP_EN (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH3_STOP_EN_Msk                                  (0x2000UL)     /*!< CH3_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH3_QUE_EMP_EN_Pos                               (14UL)         /*!< CH3_QUE_EMP_EN (Bit 14)                               */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH3_QUE_EMP_EN_Msk                               (0x4000UL)     /*!< CH3_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH3_ERR_EN_Pos                                   (15UL)         /*!< CH3_ERR_EN (Bit 15)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH3_ERR_EN_Msk                                   (0x8000UL)     /*!< CH3_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH4_END_EN_Pos                                   (16UL)         /*!< CH4_END_EN (Bit 16)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH4_END_EN_Msk                                   (0x10000UL)    /*!< CH4_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH4_STOP_EN_Pos                                  (17UL)         /*!< CH4_STOP_EN (Bit 17)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH4_STOP_EN_Msk                                  (0x20000UL)    /*!< CH4_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH4_QUE_EMP_EN_Pos                               (18UL)         /*!< CH4_QUE_EMP_EN (Bit 18)                               */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH4_QUE_EMP_EN_Msk                               (0x40000UL)    /*!< CH4_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH4_ERR_EN_Pos                                   (19UL)         /*!< CH4_ERR_EN (Bit 19)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH4_ERR_EN_Msk                                   (0x80000UL)    /*!< CH4_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH5_END_EN_Pos                                   (20UL)         /*!< CH5_END_EN (Bit 20)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH5_END_EN_Msk                                   (0x100000UL)   /*!< CH5_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH5_STOP_EN_Pos                                  (21UL)         /*!< CH5_STOP_EN (Bit 21)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH5_STOP_EN_Msk                                  (0x200000UL)   /*!< CH5_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH5_QUE_EMP_EN_Pos                               (22UL)         /*!< CH5_QUE_EMP_EN (Bit 22)                               */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH5_QUE_EMP_EN_Msk                               (0x400000UL)   /*!< CH5_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH5_ERR_EN_Pos                                   (23UL)         /*!< CH5_ERR_EN (Bit 23)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH5_ERR_EN_Msk                                   (0x800000UL)   /*!< CH5_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH6_END_EN_Pos                                   (24UL)         /*!< CH6_END_EN (Bit 24)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH6_END_EN_Msk                                   (0x1000000UL)  /*!< CH6_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH6_STOP_EN_Pos                                  (25UL)         /*!< CH6_STOP_EN (Bit 25)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH6_STOP_EN_Msk                                  (0x2000000UL)  /*!< CH6_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH6_QUE_EMP_EN_Pos                               (26UL)         /*!< CH6_QUE_EMP_EN (Bit 26)                               */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH6_QUE_EMP_EN_Msk                               (0x4000000UL)  /*!< CH6_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH6_ERR_EN_Pos                                   (27UL)         /*!< CH6_ERR_EN (Bit 27)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH6_ERR_EN_Msk                                   (0x8000000UL)  /*!< CH6_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH7_END_EN_Pos                                   (28UL)         /*!< CH7_END_EN (Bit 28)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH7_END_EN_Msk                                   (0x10000000UL) /*!< CH7_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH7_STOP_EN_Pos                                  (29UL)         /*!< CH7_STOP_EN (Bit 29)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH7_STOP_EN_Msk                                  (0x20000000UL) /*!< CH7_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH7_QUE_EMP_EN_Pos                               (30UL)         /*!< CH7_QUE_EMP_EN (Bit 30)                               */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH7_QUE_EMP_EN_Msk                               (0x40000000UL) /*!< CH7_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH7_ERR_EN_Pos                                   (31UL)         /*!< CH7_ERR_EN (Bit 31)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTE_CH7_ERR_EN_Msk                                   (0x80000000UL) /*!< CH7_ERR_EN (Bitfield-Mask: 0x01)                      */
+/* ====================================================  PCI_RC_DMAINTE  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH0_END_EN_Pos                                   (0UL)          /*!< CH0_END_EN (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH0_END_EN_Msk                                   (0x1UL)        /*!< CH0_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH0_STOP_EN_Pos                                  (1UL)          /*!< CH0_STOP_EN (Bit 1)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH0_STOP_EN_Msk                                  (0x2UL)        /*!< CH0_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH0_QUE_EMP_EN_Pos                               (2UL)          /*!< CH0_QUE_EMP_EN (Bit 2)                                */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH0_QUE_EMP_EN_Msk                               (0x4UL)        /*!< CH0_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH0_ERR_EN_Pos                                   (3UL)          /*!< CH0_ERR_EN (Bit 3)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH0_ERR_EN_Msk                                   (0x8UL)        /*!< CH0_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH1_END_EN_Pos                                   (4UL)          /*!< CH1_END_EN (Bit 4)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH1_END_EN_Msk                                   (0x10UL)       /*!< CH1_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH1_STOP_EN_Pos                                  (5UL)          /*!< CH1_STOP_EN (Bit 5)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH1_STOP_EN_Msk                                  (0x20UL)       /*!< CH1_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH1_QUE_EMP_EN_Pos                               (6UL)          /*!< CH1_QUE_EMP_EN (Bit 6)                                */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH1_QUE_EMP_EN_Msk                               (0x40UL)       /*!< CH1_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH1_ERR_EN_Pos                                   (7UL)          /*!< CH1_ERR_EN (Bit 7)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH1_ERR_EN_Msk                                   (0x80UL)       /*!< CH1_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH2_END_EN_Pos                                   (8UL)          /*!< CH2_END_EN (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH2_END_EN_Msk                                   (0x100UL)      /*!< CH2_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH2_STOP_EN_Pos                                  (9UL)          /*!< CH2_STOP_EN (Bit 9)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH2_STOP_EN_Msk                                  (0x200UL)      /*!< CH2_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH2_QUE_EMP_EN_Pos                               (10UL)         /*!< CH2_QUE_EMP_EN (Bit 10)                               */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH2_QUE_EMP_EN_Msk                               (0x400UL)      /*!< CH2_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH2_ERR_EN_Pos                                   (11UL)         /*!< CH2_ERR_EN (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH2_ERR_EN_Msk                                   (0x800UL)      /*!< CH2_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH3_END_EN_Pos                                   (12UL)         /*!< CH3_END_EN (Bit 12)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH3_END_EN_Msk                                   (0x1000UL)     /*!< CH3_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH3_STOP_EN_Pos                                  (13UL)         /*!< CH3_STOP_EN (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH3_STOP_EN_Msk                                  (0x2000UL)     /*!< CH3_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH3_QUE_EMP_EN_Pos                               (14UL)         /*!< CH3_QUE_EMP_EN (Bit 14)                               */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH3_QUE_EMP_EN_Msk                               (0x4000UL)     /*!< CH3_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH3_ERR_EN_Pos                                   (15UL)         /*!< CH3_ERR_EN (Bit 15)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH3_ERR_EN_Msk                                   (0x8000UL)     /*!< CH3_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH4_END_EN_Pos                                   (16UL)         /*!< CH4_END_EN (Bit 16)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH4_END_EN_Msk                                   (0x10000UL)    /*!< CH4_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH4_STOP_EN_Pos                                  (17UL)         /*!< CH4_STOP_EN (Bit 17)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH4_STOP_EN_Msk                                  (0x20000UL)    /*!< CH4_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH4_QUE_EMP_EN_Pos                               (18UL)         /*!< CH4_QUE_EMP_EN (Bit 18)                               */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH4_QUE_EMP_EN_Msk                               (0x40000UL)    /*!< CH4_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH4_ERR_EN_Pos                                   (19UL)         /*!< CH4_ERR_EN (Bit 19)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH4_ERR_EN_Msk                                   (0x80000UL)    /*!< CH4_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH5_END_EN_Pos                                   (20UL)         /*!< CH5_END_EN (Bit 20)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH5_END_EN_Msk                                   (0x100000UL)   /*!< CH5_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH5_STOP_EN_Pos                                  (21UL)         /*!< CH5_STOP_EN (Bit 21)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH5_STOP_EN_Msk                                  (0x200000UL)   /*!< CH5_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH5_QUE_EMP_EN_Pos                               (22UL)         /*!< CH5_QUE_EMP_EN (Bit 22)                               */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH5_QUE_EMP_EN_Msk                               (0x400000UL)   /*!< CH5_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH5_ERR_EN_Pos                                   (23UL)         /*!< CH5_ERR_EN (Bit 23)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH5_ERR_EN_Msk                                   (0x800000UL)   /*!< CH5_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH6_END_EN_Pos                                   (24UL)         /*!< CH6_END_EN (Bit 24)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH6_END_EN_Msk                                   (0x1000000UL)  /*!< CH6_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH6_STOP_EN_Pos                                  (25UL)         /*!< CH6_STOP_EN (Bit 25)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH6_STOP_EN_Msk                                  (0x2000000UL)  /*!< CH6_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH6_QUE_EMP_EN_Pos                               (26UL)         /*!< CH6_QUE_EMP_EN (Bit 26)                               */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH6_QUE_EMP_EN_Msk                               (0x4000000UL)  /*!< CH6_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH6_ERR_EN_Pos                                   (27UL)         /*!< CH6_ERR_EN (Bit 27)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH6_ERR_EN_Msk                                   (0x8000000UL)  /*!< CH6_ERR_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH7_END_EN_Pos                                   (28UL)         /*!< CH7_END_EN (Bit 28)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH7_END_EN_Msk                                   (0x10000000UL) /*!< CH7_END_EN (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH7_STOP_EN_Pos                                  (29UL)         /*!< CH7_STOP_EN (Bit 29)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH7_STOP_EN_Msk                                  (0x20000000UL) /*!< CH7_STOP_EN (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH7_QUE_EMP_EN_Pos                               (30UL)         /*!< CH7_QUE_EMP_EN (Bit 30)                               */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH7_QUE_EMP_EN_Msk                               (0x40000000UL) /*!< CH7_QUE_EMP_EN (Bitfield-Mask: 0x01)                  */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH7_ERR_EN_Pos                                   (31UL)         /*!< CH7_ERR_EN (Bit 31)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTE_CH7_ERR_EN_Msk                                   (0x80000000UL) /*!< CH7_ERR_EN (Bitfield-Mask: 0x01)                      */
+/* ====================================================  PCI_EP_DMAINTS  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH0_END_Pos                                      (0UL)          /*!< CH0_END (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH0_END_Msk                                      (0x1UL)        /*!< CH0_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH0_STOP_Pos                                     (1UL)          /*!< CH0_STOP (Bit 1)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH0_STOP_Msk                                     (0x2UL)        /*!< CH0_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH0_QUE_EMP_Pos                                  (2UL)          /*!< CH0_QUE_EMP (Bit 2)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH0_QUE_EMP_Msk                                  (0x4UL)        /*!< CH0_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH0_ERR_Pos                                      (3UL)          /*!< CH0_ERR (Bit 3)                                       */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH0_ERR_Msk                                      (0x8UL)        /*!< CH0_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH1_END_Pos                                      (4UL)          /*!< CH1_END (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH1_END_Msk                                      (0x10UL)       /*!< CH1_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH1_STOP_Pos                                     (5UL)          /*!< CH1_STOP (Bit 5)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH1_STOP_Msk                                     (0x20UL)       /*!< CH1_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH1_QUE_EMP_Pos                                  (6UL)          /*!< CH1_QUE_EMP (Bit 6)                                   */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH1_QUE_EMP_Msk                                  (0x40UL)       /*!< CH1_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH1_ERR_Pos                                      (7UL)          /*!< CH1_ERR (Bit 7)                                       */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH1_ERR_Msk                                      (0x80UL)       /*!< CH1_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH2_END_Pos                                      (8UL)          /*!< CH2_END (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH2_END_Msk                                      (0x100UL)      /*!< CH2_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH2_STOP_Pos                                     (9UL)          /*!< CH2_STOP (Bit 9)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH2_STOP_Msk                                     (0x200UL)      /*!< CH2_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH2_QUE_EMP_Pos                                  (10UL)         /*!< CH2_QUE_EMP (Bit 10)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH2_QUE_EMP_Msk                                  (0x400UL)      /*!< CH2_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH2_ERR_Pos                                      (11UL)         /*!< CH2_ERR (Bit 11)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH2_ERR_Msk                                      (0x800UL)      /*!< CH2_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH3_END_Pos                                      (12UL)         /*!< CH3_END (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH3_END_Msk                                      (0x1000UL)     /*!< CH3_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH3_STOP_Pos                                     (13UL)         /*!< CH3_STOP (Bit 13)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH3_STOP_Msk                                     (0x2000UL)     /*!< CH3_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH3_QUE_EMP_Pos                                  (14UL)         /*!< CH3_QUE_EMP (Bit 14)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH3_QUE_EMP_Msk                                  (0x4000UL)     /*!< CH3_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH3_ERR_Pos                                      (15UL)         /*!< CH3_ERR (Bit 15)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH3_ERR_Msk                                      (0x8000UL)     /*!< CH3_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH4_END_Pos                                      (16UL)         /*!< CH4_END (Bit 16)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH4_END_Msk                                      (0x10000UL)    /*!< CH4_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH4_STOP_Pos                                     (17UL)         /*!< CH4_STOP (Bit 17)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH4_STOP_Msk                                     (0x20000UL)    /*!< CH4_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH4_QUE_EMP_Pos                                  (18UL)         /*!< CH4_QUE_EMP (Bit 18)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH4_QUE_EMP_Msk                                  (0x40000UL)    /*!< CH4_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH4_ERR_Pos                                      (19UL)         /*!< CH4_ERR (Bit 19)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH4_ERR_Msk                                      (0x80000UL)    /*!< CH4_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH5_END_Pos                                      (20UL)         /*!< CH5_END (Bit 20)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH5_END_Msk                                      (0x100000UL)   /*!< CH5_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH5_STOP_Pos                                     (21UL)         /*!< CH5_STOP (Bit 21)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH5_STOP_Msk                                     (0x200000UL)   /*!< CH5_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH5_QUE_EMP_Pos                                  (22UL)         /*!< CH5_QUE_EMP (Bit 22)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH5_QUE_EMP_Msk                                  (0x400000UL)   /*!< CH5_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH5_ERR_Pos                                      (23UL)         /*!< CH5_ERR (Bit 23)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH5_ERR_Msk                                      (0x800000UL)   /*!< CH5_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH6_END_Pos                                      (24UL)         /*!< CH6_END (Bit 24)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH6_END_Msk                                      (0x1000000UL)  /*!< CH6_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH6_STOP_Pos                                     (25UL)         /*!< CH6_STOP (Bit 25)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH6_STOP_Msk                                     (0x2000000UL)  /*!< CH6_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH6_QUE_EMP_Pos                                  (26UL)         /*!< CH6_QUE_EMP (Bit 26)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH6_QUE_EMP_Msk                                  (0x4000000UL)  /*!< CH6_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH6_ERR_Pos                                      (27UL)         /*!< CH6_ERR (Bit 27)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH6_ERR_Msk                                      (0x8000000UL)  /*!< CH6_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH7_END_Pos                                      (28UL)         /*!< CH7_END (Bit 28)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH7_END_Msk                                      (0x10000000UL) /*!< CH7_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH7_STOP_Pos                                     (29UL)         /*!< CH7_STOP (Bit 29)                                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH7_STOP_Msk                                     (0x20000000UL) /*!< CH7_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH7_QUE_EMP_Pos                                  (30UL)         /*!< CH7_QUE_EMP (Bit 30)                                  */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH7_QUE_EMP_Msk                                  (0x40000000UL) /*!< CH7_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH7_ERR_Pos                                      (31UL)         /*!< CH7_ERR (Bit 31)                                      */
+ #define R_PCIE0_PCI_EP_DMAINTS_CH7_ERR_Msk                                      (0x80000000UL) /*!< CH7_ERR (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_DMAINTS  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH0_END_Pos                                      (0UL)          /*!< CH0_END (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH0_END_Msk                                      (0x1UL)        /*!< CH0_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH0_STOP_Pos                                     (1UL)          /*!< CH0_STOP (Bit 1)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH0_STOP_Msk                                     (0x2UL)        /*!< CH0_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH0_QUE_EMP_Pos                                  (2UL)          /*!< CH0_QUE_EMP (Bit 2)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH0_QUE_EMP_Msk                                  (0x4UL)        /*!< CH0_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH0_ERR_Pos                                      (3UL)          /*!< CH0_ERR (Bit 3)                                       */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH0_ERR_Msk                                      (0x8UL)        /*!< CH0_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH1_END_Pos                                      (4UL)          /*!< CH1_END (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH1_END_Msk                                      (0x10UL)       /*!< CH1_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH1_STOP_Pos                                     (5UL)          /*!< CH1_STOP (Bit 5)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH1_STOP_Msk                                     (0x20UL)       /*!< CH1_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH1_QUE_EMP_Pos                                  (6UL)          /*!< CH1_QUE_EMP (Bit 6)                                   */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH1_QUE_EMP_Msk                                  (0x40UL)       /*!< CH1_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH1_ERR_Pos                                      (7UL)          /*!< CH1_ERR (Bit 7)                                       */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH1_ERR_Msk                                      (0x80UL)       /*!< CH1_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH2_END_Pos                                      (8UL)          /*!< CH2_END (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH2_END_Msk                                      (0x100UL)      /*!< CH2_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH2_STOP_Pos                                     (9UL)          /*!< CH2_STOP (Bit 9)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH2_STOP_Msk                                     (0x200UL)      /*!< CH2_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH2_QUE_EMP_Pos                                  (10UL)         /*!< CH2_QUE_EMP (Bit 10)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH2_QUE_EMP_Msk                                  (0x400UL)      /*!< CH2_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH2_ERR_Pos                                      (11UL)         /*!< CH2_ERR (Bit 11)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH2_ERR_Msk                                      (0x800UL)      /*!< CH2_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH3_END_Pos                                      (12UL)         /*!< CH3_END (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH3_END_Msk                                      (0x1000UL)     /*!< CH3_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH3_STOP_Pos                                     (13UL)         /*!< CH3_STOP (Bit 13)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH3_STOP_Msk                                     (0x2000UL)     /*!< CH3_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH3_QUE_EMP_Pos                                  (14UL)         /*!< CH3_QUE_EMP (Bit 14)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH3_QUE_EMP_Msk                                  (0x4000UL)     /*!< CH3_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH3_ERR_Pos                                      (15UL)         /*!< CH3_ERR (Bit 15)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH3_ERR_Msk                                      (0x8000UL)     /*!< CH3_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH4_END_Pos                                      (16UL)         /*!< CH4_END (Bit 16)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH4_END_Msk                                      (0x10000UL)    /*!< CH4_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH4_STOP_Pos                                     (17UL)         /*!< CH4_STOP (Bit 17)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH4_STOP_Msk                                     (0x20000UL)    /*!< CH4_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH4_QUE_EMP_Pos                                  (18UL)         /*!< CH4_QUE_EMP (Bit 18)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH4_QUE_EMP_Msk                                  (0x40000UL)    /*!< CH4_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH4_ERR_Pos                                      (19UL)         /*!< CH4_ERR (Bit 19)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH4_ERR_Msk                                      (0x80000UL)    /*!< CH4_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH5_END_Pos                                      (20UL)         /*!< CH5_END (Bit 20)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH5_END_Msk                                      (0x100000UL)   /*!< CH5_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH5_STOP_Pos                                     (21UL)         /*!< CH5_STOP (Bit 21)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH5_STOP_Msk                                     (0x200000UL)   /*!< CH5_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH5_QUE_EMP_Pos                                  (22UL)         /*!< CH5_QUE_EMP (Bit 22)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH5_QUE_EMP_Msk                                  (0x400000UL)   /*!< CH5_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH5_ERR_Pos                                      (23UL)         /*!< CH5_ERR (Bit 23)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH5_ERR_Msk                                      (0x800000UL)   /*!< CH5_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH6_END_Pos                                      (24UL)         /*!< CH6_END (Bit 24)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH6_END_Msk                                      (0x1000000UL)  /*!< CH6_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH6_STOP_Pos                                     (25UL)         /*!< CH6_STOP (Bit 25)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH6_STOP_Msk                                     (0x2000000UL)  /*!< CH6_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH6_QUE_EMP_Pos                                  (26UL)         /*!< CH6_QUE_EMP (Bit 26)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH6_QUE_EMP_Msk                                  (0x4000000UL)  /*!< CH6_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH6_ERR_Pos                                      (27UL)         /*!< CH6_ERR (Bit 27)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH6_ERR_Msk                                      (0x8000000UL)  /*!< CH6_ERR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH7_END_Pos                                      (28UL)         /*!< CH7_END (Bit 28)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH7_END_Msk                                      (0x10000000UL) /*!< CH7_END (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH7_STOP_Pos                                     (29UL)         /*!< CH7_STOP (Bit 29)                                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH7_STOP_Msk                                     (0x20000000UL) /*!< CH7_STOP (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH7_QUE_EMP_Pos                                  (30UL)         /*!< CH7_QUE_EMP (Bit 30)                                  */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH7_QUE_EMP_Msk                                  (0x40000000UL) /*!< CH7_QUE_EMP (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH7_ERR_Pos                                      (31UL)         /*!< CH7_ERR (Bit 31)                                      */
+ #define R_PCIE0_PCI_RC_DMAINTS_CH7_ERR_Msk                                      (0x80000000UL) /*!< CH7_ERR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACHCTL0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACHCTL0_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL0_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACHCTL0_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_EP_DMACHCTL0_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_DMACHCTL0_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL0_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACHCTL1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACHCTL1_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL1_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACHCTL1_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_EP_DMACHCTL1_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_DMACHCTL1_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL1_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACHCTL2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACHCTL2_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL2_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACHCTL2_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_EP_DMACHCTL2_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_DMACHCTL2_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL2_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACHCTL3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACHCTL3_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL3_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACHCTL3_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_EP_DMACHCTL3_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_DMACHCTL3_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL3_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACHCTL4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACHCTL4_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL4_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACHCTL4_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_EP_DMACHCTL4_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_DMACHCTL4_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL4_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACHCTL5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACHCTL5_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL5_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACHCTL5_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_EP_DMACHCTL5_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_DMACHCTL5_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL5_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACHCTL6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACHCTL6_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL6_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACHCTL6_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_EP_DMACHCTL6_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_DMACHCTL6_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL6_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACHCTL7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACHCTL7_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL7_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACHCTL7_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_EP_DMACHCTL7_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_DMACHCTL7_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMACHCTL7_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_RC_DMACHCTL0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACHCTL0_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL0_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACHCTL0_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_DMACHCTL0_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_DMACHCTL0_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL0_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_RC_DMACHCTL1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACHCTL1_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL1_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACHCTL1_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_DMACHCTL1_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_DMACHCTL1_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL1_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_RC_DMACHCTL2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACHCTL2_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL2_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACHCTL2_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_DMACHCTL2_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_DMACHCTL2_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL2_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_RC_DMACHCTL3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACHCTL3_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL3_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACHCTL3_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_DMACHCTL3_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_DMACHCTL3_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL3_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_RC_DMACHCTL4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACHCTL4_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL4_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACHCTL4_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_DMACHCTL4_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_DMACHCTL4_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL4_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_RC_DMACHCTL5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACHCTL5_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL5_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACHCTL5_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_DMACHCTL5_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_DMACHCTL5_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL5_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_RC_DMACHCTL6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACHCTL6_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL6_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACHCTL6_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_DMACHCTL6_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_DMACHCTL6_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL6_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_RC_DMACHCTL7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACHCTL7_RDMA_EN_Pos                                    (0UL)          /*!< RDMA_EN (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL7_RDMA_EN_Msk                                    (0x1UL)        /*!< RDMA_EN (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACHCTL7_QUE_EN_Pos                                     (1UL)          /*!< QUE_EN (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_DMACHCTL7_QUE_EN_Msk                                     (0x2UL)        /*!< QUE_EN (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_DMACHCTL7_QUE_CLR_Pos                                    (8UL)          /*!< QUE_CLR (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMACHCTL7_QUE_CLR_Msk                                    (0x100UL)      /*!< QUE_CLR (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_EP_DPSADRL0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRL0_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL0_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_EP_DPSADRL0_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL0_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_EP_DPSADRL1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRL1_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL1_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_EP_DPSADRL1_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL1_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_EP_DPSADRL2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRL2_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL2_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_EP_DPSADRL2_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL2_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_EP_DPSADRL3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRL3_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL3_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_EP_DPSADRL3_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL3_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_EP_DPSADRL4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRL4_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL4_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_EP_DPSADRL4_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL4_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_EP_DPSADRL5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRL5_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL5_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_EP_DPSADRL5_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL5_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_EP_DPSADRL6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRL6_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL6_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_EP_DPSADRL6_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL6_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_EP_DPSADRL7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRL7_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL7_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_EP_DPSADRL7_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_EP_DPSADRL7_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_RC_DPSADRL0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRL0_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL0_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_RC_DPSADRL0_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL0_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_RC_DPSADRL1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRL1_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL1_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_RC_DPSADRL1_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL1_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_RC_DPSADRL2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRL2_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL2_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_RC_DPSADRL2_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL2_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_RC_DPSADRL3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRL3_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL3_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_RC_DPSADRL3_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL3_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_RC_DPSADRL4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRL4_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL4_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_RC_DPSADRL4_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL4_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_RC_DPSADRL5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRL5_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL5_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_RC_DPSADRL5_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL5_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_RC_DPSADRL6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRL6_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL6_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_RC_DPSADRL6_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL6_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_RC_DPSADRL7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRL7_QUE_ENTRY_DSA0500_Pos                           (0UL)          /*!< QUE_ENTRY_DSA0500 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL7_QUE_ENTRY_DSA0500_Msk                           (0x3fUL)       /*!< QUE_ENTRY_DSA0500 (Bitfield-Mask: 0x3f)               */
+ #define R_PCIE0_PCI_RC_DPSADRL7_QUE_ENTRY_DSA3106_Pos                           (6UL)          /*!< QUE_ENTRY_DSA3106 (Bit 6)                             */
+ #define R_PCIE0_PCI_RC_DPSADRL7_QUE_ENTRY_DSA3106_Msk                           (0xffffffc0UL) /*!< QUE_ENTRY_DSA3106 (Bitfield-Mask: 0x3ffffff)         */
+/* ====================================================  PCI_EP_DPSADRU0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRU0_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRU0_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_EP_DPSADRU1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRU1_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRU1_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_EP_DPSADRU2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRU2_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRU2_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_EP_DPSADRU3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRU3_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRU3_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_EP_DPSADRU4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRU4_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRU4_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_EP_DPSADRU5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRU5_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRU5_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_EP_DPSADRU6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRU6_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRU6_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_EP_DPSADRU7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DPSADRU7_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_DPSADRU7_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_RC_DPSADRU0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRU0_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRU0_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_RC_DPSADRU1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRU1_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRU1_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_RC_DPSADRU2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRU2_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRU2_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_RC_DPSADRU3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRU3_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRU3_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_RC_DPSADRU4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRU4_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRU4_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_RC_DPSADRU5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRU5_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRU5_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_RC_DPSADRU6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRU6_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRU6_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* ====================================================  PCI_RC_DPSADRU7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DPSADRU7_QUE_ENTRY_DSA6332_Pos                           (0UL)          /*!< QUE_ENTRY_DSA6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_DPSADRU7_QUE_ENTRY_DSA6332_Msk                           (0xffffffffUL) /*!< QUE_ENTRY_DSA6332 (Bitfield-Mask: 0xffffffff)        */
+/* =====================================================  PCI_EP_QUEE0  ====================================================== */
+ #define R_PCIE0_PCI_EP_QUEE0_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_EP_QUEE0_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_EP_QUEE0_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_EP_QUEE0_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE0_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_EP_QUEE0_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE0_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_QUEE0_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_EP_QUEE1  ====================================================== */
+ #define R_PCIE0_PCI_EP_QUEE1_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_EP_QUEE1_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_EP_QUEE1_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_EP_QUEE1_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE1_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_EP_QUEE1_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE1_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_QUEE1_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_EP_QUEE2  ====================================================== */
+ #define R_PCIE0_PCI_EP_QUEE2_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_EP_QUEE2_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_EP_QUEE2_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_EP_QUEE2_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE2_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_EP_QUEE2_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE2_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_QUEE2_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_EP_QUEE3  ====================================================== */
+ #define R_PCIE0_PCI_EP_QUEE3_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_EP_QUEE3_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_EP_QUEE3_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_EP_QUEE3_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE3_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_EP_QUEE3_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE3_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_QUEE3_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_EP_QUEE4  ====================================================== */
+ #define R_PCIE0_PCI_EP_QUEE4_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_EP_QUEE4_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_EP_QUEE4_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_EP_QUEE4_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE4_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_EP_QUEE4_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE4_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_QUEE4_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_EP_QUEE5  ====================================================== */
+ #define R_PCIE0_PCI_EP_QUEE5_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_EP_QUEE5_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_EP_QUEE5_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_EP_QUEE5_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE5_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_EP_QUEE5_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE5_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_QUEE5_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_EP_QUEE6  ====================================================== */
+ #define R_PCIE0_PCI_EP_QUEE6_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_EP_QUEE6_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_EP_QUEE6_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_EP_QUEE6_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE6_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_EP_QUEE6_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE6_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_QUEE6_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_EP_QUEE7  ====================================================== */
+ #define R_PCIE0_PCI_EP_QUEE7_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_EP_QUEE7_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_EP_QUEE7_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_EP_QUEE7_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE7_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_EP_QUEE7_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_EP_QUEE7_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_QUEE7_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_RC_QUEE0  ====================================================== */
+ #define R_PCIE0_PCI_RC_QUEE0_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_RC_QUEE0_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_RC_QUEE0_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_RC_QUEE0_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE0_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_RC_QUEE0_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE0_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_RC_QUEE0_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_RC_QUEE1  ====================================================== */
+ #define R_PCIE0_PCI_RC_QUEE1_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_RC_QUEE1_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_RC_QUEE1_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_RC_QUEE1_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE1_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_RC_QUEE1_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE1_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_RC_QUEE1_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_RC_QUEE2  ====================================================== */
+ #define R_PCIE0_PCI_RC_QUEE2_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_RC_QUEE2_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_RC_QUEE2_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_RC_QUEE2_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE2_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_RC_QUEE2_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE2_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_RC_QUEE2_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_RC_QUEE3  ====================================================== */
+ #define R_PCIE0_PCI_RC_QUEE3_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_RC_QUEE3_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_RC_QUEE3_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_RC_QUEE3_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE3_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_RC_QUEE3_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE3_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_RC_QUEE3_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_RC_QUEE4  ====================================================== */
+ #define R_PCIE0_PCI_RC_QUEE4_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_RC_QUEE4_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_RC_QUEE4_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_RC_QUEE4_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE4_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_RC_QUEE4_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE4_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_RC_QUEE4_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_RC_QUEE5  ====================================================== */
+ #define R_PCIE0_PCI_RC_QUEE5_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_RC_QUEE5_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_RC_QUEE5_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_RC_QUEE5_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE5_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_RC_QUEE5_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE5_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_RC_QUEE5_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_RC_QUEE6  ====================================================== */
+ #define R_PCIE0_PCI_RC_QUEE6_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_RC_QUEE6_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_RC_QUEE6_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_RC_QUEE6_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE6_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_RC_QUEE6_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE6_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_RC_QUEE6_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* =====================================================  PCI_RC_QUEE7  ====================================================== */
+ #define R_PCIE0_PCI_RC_QUEE7_QUE_ENTRY_LABEL_Pos                                (0UL)          /*!< QUE_ENTRY_LABEL (Bit 0)                               */
+ #define R_PCIE0_PCI_RC_QUEE7_QUE_ENTRY_LABEL_Msk                                (0xffffUL)     /*!< QUE_ENTRY_LABEL (Bitfield-Mask: 0xffff)               */
+ #define R_PCIE0_PCI_RC_QUEE7_QUE_ENTRY_LS_Pos                                   (24UL)         /*!< QUE_ENTRY_LS (Bit 24)                                 */
+ #define R_PCIE0_PCI_RC_QUEE7_QUE_ENTRY_LS_Msk                                   (0x1000000UL)  /*!< QUE_ENTRY_LS (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE7_QUE_ENTRY_EI_Pos                                   (25UL)         /*!< QUE_ENTRY_EI (Bit 25)                                 */
+ #define R_PCIE0_PCI_RC_QUEE7_QUE_ENTRY_EI_Msk                                   (0x2000000UL)  /*!< QUE_ENTRY_EI (Bitfield-Mask: 0x01)                    */
+ #define R_PCIE0_PCI_RC_QUEE7_QUE_R_Pos                                          (26UL)         /*!< QUE_R (Bit 26)                                        */
+ #define R_PCIE0_PCI_RC_QUEE7_QUE_R_Msk                                          (0xfc000000UL) /*!< QUE_R (Bitfield-Mask: 0x3f)                           */
+/* ===================================================  PCI_EP_DMADPCTL0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_EP_DMADPCTL0_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_EP_DMADPCTL1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_EP_DMADPCTL1_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_EP_DMADPCTL2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_EP_DMADPCTL2_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_EP_DMADPCTL3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_EP_DMADPCTL3_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_EP_DMADPCTL4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_EP_DMADPCTL4_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_EP_DMADPCTL5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_EP_DMADPCTL5_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_EP_DMADPCTL6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_EP_DMADPCTL6_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_EP_DMADPCTL7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_EP_DMADPCTL7_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_RC_DMADPCTL0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_RC_DMADPCTL0_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_RC_DMADPCTL1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_RC_DMADPCTL1_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_RC_DMADPCTL2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_RC_DMADPCTL2_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_RC_DMADPCTL3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_RC_DMADPCTL3_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_RC_DMADPCTL4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_RC_DMADPCTL4_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_RC_DMADPCTL5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_RC_DMADPCTL5_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_RC_DMADPCTL6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_RC_DMADPCTL6_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ===================================================  PCI_RC_DMADPCTL7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_STS_Pos                                        (0UL)          /*!< STS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_STS_Msk                                        (0xffffUL)     /*!< STS (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_D_Pos                                          (23UL)         /*!< D (Bit 23)                                            */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_D_Msk                                          (0x800000UL)   /*!< D (Bitfield-Mask: 0x01)                               */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_LV_Pos                                         (24UL)         /*!< LV (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_LV_Msk                                         (0x1000000UL)  /*!< LV (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_LE_Pos                                         (25UL)         /*!< LE (Bit 25)                                           */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_LE_Msk                                         (0x2000000UL)  /*!< LE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_WBD_Pos                                        (26UL)         /*!< WBD (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_WBD_Msk                                        (0x4000000UL)  /*!< WBD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_DSCFM_Pos                                      (28UL)         /*!< DSCFM (Bit 28)                                        */
+ #define R_PCIE0_PCI_RC_DMADPCTL7_DSCFM_Msk                                      (0xf0000000UL) /*!< DSCFM (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMATCTL0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMATCTL0_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL0_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL0_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_EP_DMATCTL0_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_EP_DMATCTL0_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL0_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL0_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL0_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_DMATCTL0_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL0_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_DMATCTL0_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL0_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMATCTL1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMATCTL1_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL1_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL1_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_EP_DMATCTL1_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_EP_DMATCTL1_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL1_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL1_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL1_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_DMATCTL1_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL1_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_DMATCTL1_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL1_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMATCTL2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMATCTL2_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL2_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL2_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_EP_DMATCTL2_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_EP_DMATCTL2_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL2_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL2_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL2_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_DMATCTL2_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL2_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_DMATCTL2_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL2_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMATCTL3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMATCTL3_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL3_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL3_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_EP_DMATCTL3_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_EP_DMATCTL3_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL3_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL3_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL3_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_DMATCTL3_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL3_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_DMATCTL3_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL3_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMATCTL4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMATCTL4_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL4_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL4_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_EP_DMATCTL4_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_EP_DMATCTL4_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL4_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL4_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL4_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_DMATCTL4_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL4_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_DMATCTL4_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL4_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMATCTL5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMATCTL5_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL5_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL5_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_EP_DMATCTL5_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_EP_DMATCTL5_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL5_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL5_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL5_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_DMATCTL5_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL5_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_DMATCTL5_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL5_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMATCTL6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMATCTL6_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL6_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL6_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_EP_DMATCTL6_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_EP_DMATCTL6_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL6_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL6_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL6_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_DMATCTL6_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL6_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_DMATCTL6_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL6_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMATCTL7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMATCTL7_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL7_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL7_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_EP_DMATCTL7_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_EP_DMATCTL7_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL7_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_EP_DMATCTL7_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_DMATCTL7_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_DMATCTL7_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL7_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_DMATCTL7_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_EP_DMATCTL7_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_RC_DMATCTL0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMATCTL0_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL0_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL0_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_RC_DMATCTL0_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_RC_DMATCTL0_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL0_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL0_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL0_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_DMATCTL0_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL0_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_DMATCTL0_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL0_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_RC_DMATCTL1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMATCTL1_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL1_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL1_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_RC_DMATCTL1_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_RC_DMATCTL1_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL1_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL1_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL1_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_DMATCTL1_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL1_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_DMATCTL1_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL1_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_RC_DMATCTL2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMATCTL2_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL2_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL2_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_RC_DMATCTL2_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_RC_DMATCTL2_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL2_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL2_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL2_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_DMATCTL2_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL2_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_DMATCTL2_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL2_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_RC_DMATCTL3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMATCTL3_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL3_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL3_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_RC_DMATCTL3_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_RC_DMATCTL3_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL3_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL3_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL3_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_DMATCTL3_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL3_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_DMATCTL3_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL3_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_RC_DMATCTL4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMATCTL4_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL4_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL4_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_RC_DMATCTL4_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_RC_DMATCTL4_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL4_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL4_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL4_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_DMATCTL4_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL4_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_DMATCTL4_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL4_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_RC_DMATCTL5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMATCTL5_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL5_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL5_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_RC_DMATCTL5_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_RC_DMATCTL5_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL5_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL5_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL5_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_DMATCTL5_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL5_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_DMATCTL5_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL5_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_RC_DMATCTL6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMATCTL6_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL6_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL6_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_RC_DMATCTL6_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_RC_DMATCTL6_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL6_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL6_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL6_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_DMATCTL6_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL6_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_DMATCTL6_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL6_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_RC_DMATCTL7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMATCTL7_DMA_DIR_Pos                                     (0UL)          /*!< DMA_DIR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL7_DMA_DIR_Msk                                     (0x1UL)        /*!< DMA_DIR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL7_DMA_FUNC_Pos                                    (4UL)          /*!< DMA_FUNC (Bit 4)                                      */
+ #define R_PCIE0_PCI_RC_DMATCTL7_DMA_FUNC_Msk                                    (0x70UL)       /*!< DMA_FUNC (Bitfield-Mask: 0x07)                        */
+ #define R_PCIE0_PCI_RC_DMATCTL7_DMA_ATB_Pos                                     (8UL)          /*!< DMA_ATB (Bit 8)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL7_DMA_ATB_Msk                                     (0x300UL)      /*!< DMA_ATB (Bitfield-Mask: 0x03)                         */
+ #define R_PCIE0_PCI_RC_DMATCTL7_DMA_TC_Pos                                      (12UL)         /*!< DMA_TC (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_DMATCTL7_DMA_TC_Msk                                      (0x7000UL)     /*!< DMA_TC (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_DMATCTL7_CCH_D_Pos                                       (16UL)         /*!< CCH_D (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL7_CCH_D_Msk                                       (0xf0000UL)    /*!< CCH_D (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_DMATCTL7_CCH_L_Pos                                       (20UL)         /*!< CCH_L (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_DMATCTL7_CCH_L_Msk                                       (0xf00000UL)   /*!< CCH_L (Bitfield-Mask: 0x0f)                           */
+/* ====================================================  PCI_EP_DMASIZE0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMASIZE0_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE0_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_DMASIZE0_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE0_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_EP_DMASIZE1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMASIZE1_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE1_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_DMASIZE1_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE1_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_EP_DMASIZE2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMASIZE2_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE2_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_DMASIZE2_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE2_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_EP_DMASIZE3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMASIZE3_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE3_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_DMASIZE3_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE3_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_EP_DMASIZE4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMASIZE4_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE4_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_DMASIZE4_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE4_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_EP_DMASIZE5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMASIZE5_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE5_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_DMASIZE5_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE5_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_EP_DMASIZE6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMASIZE6_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE6_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_DMASIZE6_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE6_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_EP_DMASIZE7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMASIZE7_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE7_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_EP_DMASIZE7_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_EP_DMASIZE7_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_RC_DMASIZE0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMASIZE0_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE0_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_DMASIZE0_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE0_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_RC_DMASIZE1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMASIZE1_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE1_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_DMASIZE1_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE1_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_RC_DMASIZE2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMASIZE2_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE2_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_DMASIZE2_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE2_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_RC_DMASIZE3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMASIZE3_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE3_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_DMASIZE3_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE3_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_RC_DMASIZE4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMASIZE4_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE4_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_DMASIZE4_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE4_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_RC_DMASIZE5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMASIZE5_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE5_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_DMASIZE5_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE5_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_RC_DMASIZE6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMASIZE6_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE6_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_DMASIZE6_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE6_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_RC_DMASIZE7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMASIZE7_DMA_SIZE0300_Pos                                (0UL)          /*!< DMA_SIZE0300 (Bit 0)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE7_DMA_SIZE0300_Msk                                (0xfUL)        /*!< DMA_SIZE0300 (Bitfield-Mask: 0x0f)                    */
+ #define R_PCIE0_PCI_RC_DMASIZE7_DMA_SIZE3104_Pos                                (4UL)          /*!< DMA_SIZE3104 (Bit 4)                                  */
+ #define R_PCIE0_PCI_RC_DMASIZE7_DMA_SIZE3104_Msk                                (0xfffffff0UL) /*!< DMA_SIZE3104 (Bitfield-Mask: 0xfffffff)               */
+/* ====================================================  PCI_EP_DMASLA0  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASLA0_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASLA0_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMASLA0_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMASLA0_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_EP_DMASLA1  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASLA1_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASLA1_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMASLA1_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMASLA1_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_EP_DMASLA2  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASLA2_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASLA2_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMASLA2_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMASLA2_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_EP_DMASLA3  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASLA3_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASLA3_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMASLA3_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMASLA3_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_EP_DMASLA4  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASLA4_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASLA4_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMASLA4_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMASLA4_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_EP_DMASLA5  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASLA5_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASLA5_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMASLA5_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMASLA5_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_EP_DMASLA6  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASLA6_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASLA6_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMASLA6_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMASLA6_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_EP_DMASLA7  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASLA7_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASLA7_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMASLA7_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMASLA7_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_RC_DMASLA0  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASLA0_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASLA0_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMASLA0_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMASLA0_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_RC_DMASLA1  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASLA1_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASLA1_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMASLA1_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMASLA1_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_RC_DMASLA2  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASLA2_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASLA2_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMASLA2_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMASLA2_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_RC_DMASLA3  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASLA3_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASLA3_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMASLA3_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMASLA3_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_RC_DMASLA4  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASLA4_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASLA4_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMASLA4_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMASLA4_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_RC_DMASLA5  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASLA5_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASLA5_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMASLA5_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMASLA5_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_RC_DMASLA6  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASLA6_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASLA6_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMASLA6_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMASLA6_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_RC_DMASLA7  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASLA7_DMA_S_ADDR0300_Pos                               (0UL)          /*!< DMA_S_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASLA7_DMA_S_ADDR0300_Msk                               (0xfUL)        /*!< DMA_S_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMASLA7_DMA_S_ADDR3104_Pos                               (4UL)          /*!< DMA_S_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMASLA7_DMA_S_ADDR3104_Msk                               (0xfffffff0UL) /*!< DMA_S_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ====================================================  PCI_EP_DMASUA0  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASUA0_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASUA0_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_EP_DMASUA1  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASUA1_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASUA1_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_EP_DMASUA2  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASUA2_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASUA2_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_EP_DMASUA3  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASUA3_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASUA3_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_EP_DMASUA4  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASUA4_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASUA4_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_EP_DMASUA5  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASUA5_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASUA5_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_EP_DMASUA6  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASUA6_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASUA6_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_EP_DMASUA7  ===================================================== */
+ #define R_PCIE0_PCI_EP_DMASUA7_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMASUA7_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_RC_DMASUA0  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASUA0_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASUA0_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_RC_DMASUA1  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASUA1_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASUA1_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_RC_DMASUA2  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASUA2_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASUA2_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_RC_DMASUA3  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASUA3_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASUA3_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_RC_DMASUA4  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASUA4_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASUA4_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_RC_DMASUA5  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASUA5_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASUA5_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_RC_DMASUA6  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASUA6_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASUA6_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ====================================================  PCI_RC_DMASUA7  ===================================================== */
+ #define R_PCIE0_PCI_RC_DMASUA7_DMA_S_ADDR6332_Pos                               (0UL)          /*!< DMA_S_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMASUA7_DMA_S_ADDR6332_Msk                               (0xffffffffUL) /*!< DMA_S_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADESTLA0  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTLA0_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA0_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMADESTLA0_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA0_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_EP_DMADESTLA1  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTLA1_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA1_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMADESTLA1_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA1_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_EP_DMADESTLA2  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTLA2_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA2_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMADESTLA2_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA2_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_EP_DMADESTLA3  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTLA3_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA3_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMADESTLA3_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA3_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_EP_DMADESTLA4  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTLA4_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA4_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMADESTLA4_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA4_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_EP_DMADESTLA5  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTLA5_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA5_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMADESTLA5_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA5_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_EP_DMADESTLA6  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTLA6_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA6_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMADESTLA6_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA6_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_EP_DMADESTLA7  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTLA7_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA7_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_EP_DMADESTLA7_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_EP_DMADESTLA7_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_RC_DMADESTLA0  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTLA0_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA0_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMADESTLA0_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA0_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_RC_DMADESTLA1  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTLA1_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA1_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMADESTLA1_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA1_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_RC_DMADESTLA2  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTLA2_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA2_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMADESTLA2_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA2_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_RC_DMADESTLA3  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTLA3_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA3_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMADESTLA3_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA3_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_RC_DMADESTLA4  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTLA4_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA4_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMADESTLA4_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA4_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_RC_DMADESTLA5  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTLA5_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA5_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMADESTLA5_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA5_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_RC_DMADESTLA6  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTLA6_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA6_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMADESTLA6_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA6_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_RC_DMADESTLA7  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTLA7_DMA_D_ADDR0300_Pos                            (0UL)          /*!< DMA_D_ADDR0300 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA7_DMA_D_ADDR0300_Msk                            (0xfUL)        /*!< DMA_D_ADDR0300 (Bitfield-Mask: 0x0f)                  */
+ #define R_PCIE0_PCI_RC_DMADESTLA7_DMA_D_ADDR3104_Pos                            (4UL)          /*!< DMA_D_ADDR3104 (Bit 4)                                */
+ #define R_PCIE0_PCI_RC_DMADESTLA7_DMA_D_ADDR3104_Msk                            (0xfffffff0UL) /*!< DMA_D_ADDR3104 (Bitfield-Mask: 0xfffffff)             */
+/* ===================================================  PCI_EP_DMADESTUA0  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTUA0_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTUA0_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADESTUA1  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTUA1_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTUA1_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADESTUA2  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTUA2_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTUA2_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADESTUA3  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTUA3_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTUA3_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADESTUA4  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTUA4_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTUA4_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADESTUA5  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTUA5_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTUA5_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADESTUA6  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTUA6_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTUA6_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADESTUA7  =================================================== */
+ #define R_PCIE0_PCI_EP_DMADESTUA7_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_EP_DMADESTUA7_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_RC_DMADESTUA0  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTUA0_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTUA0_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_RC_DMADESTUA1  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTUA1_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTUA1_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_RC_DMADESTUA2  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTUA2_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTUA2_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_RC_DMADESTUA3  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTUA3_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTUA3_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_RC_DMADESTUA4  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTUA4_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTUA4_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_RC_DMADESTUA5  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTUA5_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTUA5_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_RC_DMADESTUA6  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTUA6_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTUA6_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_RC_DMADESTUA7  =================================================== */
+ #define R_PCIE0_PCI_RC_DMADESTUA7_DMA_D_ADDR6332_Pos                            (0UL)          /*!< DMA_D_ADDR6332 (Bit 0)                                */
+ #define R_PCIE0_PCI_RC_DMADESTUA7_DMA_D_ADDR6332_Msk                            (0xffffffffUL) /*!< DMA_D_ADDR6332 (Bitfield-Mask: 0xffffffff)            */
+/* ===================================================  PCI_EP_DMADPLLP0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPLLP0_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPLLP0_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPLLP1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPLLP1_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPLLP1_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPLLP2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPLLP2_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPLLP2_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPLLP3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPLLP3_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPLLP3_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPLLP4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPLLP4_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPLLP4_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPLLP5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPLLP5_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPLLP5_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPLLP6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPLLP6_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPLLP6_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPLLP7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPLLP7_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPLLP7_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPLLP0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPLLP0_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPLLP0_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPLLP1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPLLP1_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPLLP1_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPLLP2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPLLP2_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPLLP2_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPLLP3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPLLP3_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPLLP3_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPLLP4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPLLP4_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPLLP4_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPLLP5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPLLP5_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPLLP5_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPLLP6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPLLP6_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPLLP6_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPLLP7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPLLP7_DMA_LP3100_Pos                                 (0UL)          /*!< DMA_LP3100 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPLLP7_DMA_LP3100_Msk                                 (0xffffffffUL) /*!< DMA_LP3100 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPULP0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPULP0_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPULP0_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPULP1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPULP1_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPULP1_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPULP2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPULP2_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPULP2_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPULP3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPULP3_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPULP3_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPULP4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPULP4_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPULP4_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPULP5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPULP5_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPULP5_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPULP6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPULP6_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPULP6_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_EP_DMADPULP7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMADPULP7_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_EP_DMADPULP7_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPULP0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPULP0_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPULP0_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPULP1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPULP1_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPULP1_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPULP2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPULP2_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPULP2_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPULP3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPULP3_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPULP3_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPULP4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPULP4_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPULP4_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPULP5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPULP5_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPULP5_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPULP6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPULP6_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPULP6_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  PCI_RC_DMADPULP7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMADPULP7_DMA_LP6332_Pos                                 (0UL)          /*!< DMA_LP6332 (Bit 0)                                    */
+ #define R_PCIE0_PCI_RC_DMADPULP7_DMA_LP6332_Msk                                 (0xffffffffUL) /*!< DMA_LP6332 (Bitfield-Mask: 0xffffffff)                */
+/* ==================================================  PCI_EP_DMARESTSIZE0  ================================================== */
+/* ==================================================  PCI_EP_DMARESTSIZE1  ================================================== */
+/* ==================================================  PCI_EP_DMARESTSIZE2  ================================================== */
+/* ==================================================  PCI_EP_DMARESTSIZE3  ================================================== */
+/* ==================================================  PCI_EP_DMARESTSIZE4  ================================================== */
+/* ==================================================  PCI_EP_DMARESTSIZE5  ================================================== */
+/* ==================================================  PCI_EP_DMARESTSIZE6  ================================================== */
+/* ==================================================  PCI_EP_DMARESTSIZE7  ================================================== */
+/* ==================================================  PCI_RC_DMARESTSIZE0  ================================================== */
+/* ==================================================  PCI_RC_DMARESTSIZE1  ================================================== */
+/* ==================================================  PCI_RC_DMARESTSIZE2  ================================================== */
+/* ==================================================  PCI_RC_DMARESTSIZE3  ================================================== */
+/* ==================================================  PCI_RC_DMARESTSIZE4  ================================================== */
+/* ==================================================  PCI_RC_DMARESTSIZE5  ================================================== */
+/* ==================================================  PCI_RC_DMARESTSIZE6  ================================================== */
+/* ==================================================  PCI_RC_DMARESTSIZE7  ================================================== */
+/* ====================================================  PCI_EP_AREQAL0  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAL0_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAL0_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAL1  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAL1_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAL1_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAL2  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAL2_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAL2_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAL3  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAL3_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAL3_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAL4  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAL4_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAL4_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAL5  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAL5_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAL5_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAL6  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAL6_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAL6_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAL7  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAL7_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAL7_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAL0  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAL0_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAL0_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAL1  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAL1_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAL1_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAL2  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAL2_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAL2_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAL3  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAL3_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAL3_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAL4  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAL4_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAL4_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAL5  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAL5_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAL5_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAL6  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAL6_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAL6_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAL7  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAL7_AXI_REQ_ADDR3100_Pos     (0UL)          /*!< AXI_REQ_ADDR3100 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAL7_AXI_REQ_ADDR3100_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAU0  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAU0_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAU0_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAU1  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAU1_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAU1_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAU2  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAU2_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAU2_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAU3  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAU3_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAU3_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAU4  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAU4_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAU4_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAU5  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAU5_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAU5_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAU6  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAU6_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAU6_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_AREQAU7  ===================================================== */
+ #define R_PCIE0_PCI_EP_AREQAU7_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_EP_AREQAU7_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAU0  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAU0_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAU0_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAU1  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAU1_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAU1_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAU2  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAU2_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAU2_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAU3  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAU3_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAU3_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAU4  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAU4_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAU4_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAU5  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAU5_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAU5_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAU6  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAU6_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAU6_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_RC_AREQAU7  ===================================================== */
+ #define R_PCIE0_PCI_RC_AREQAU7_AXI_REQ_ADDR6332_Pos     (0UL)          /*!< AXI_REQ_ADDR6332 (Bit 0)                              */
+ #define R_PCIE0_PCI_RC_AREQAU7_AXI_REQ_ADDR6332_Msk     (0xffffffffUL) /*!< AXI_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)          */
+/* ====================================================  PCI_EP_PREQAL0  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAL0_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAL0_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAL1  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAL1_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAL1_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAL2  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAL2_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAL2_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAL3  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAL3_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAL3_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAL4  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAL4_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAL4_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAL5  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAL5_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAL5_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAL6  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAL6_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAL6_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAL7  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAL7_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAL7_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAL0  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAL0_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAL0_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAL1  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAL1_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAL1_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAL2  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAL2_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAL2_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAL3  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAL3_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAL3_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAL4  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAL4_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAL4_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAL5  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAL5_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAL5_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAL6  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAL6_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAL6_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAL7  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAL7_PCIE_REQ_ADDR3100_Pos    (0UL)          /*!< PCIE_REQ_ADDR3100 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAL7_PCIE_REQ_ADDR3100_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR3100 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAU0  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAU0_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAU0_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAU1  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAU1_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAU1_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAU2  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAU2_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAU2_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAU3  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAU3_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAU3_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAU4  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAU4_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAU4_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAU5  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAU5_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAU5_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAU6  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAU6_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAU6_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_PREQAU7  ===================================================== */
+ #define R_PCIE0_PCI_EP_PREQAU7_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_EP_PREQAU7_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAU0  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAU0_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAU0_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAU1  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAU1_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAU1_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAU2  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAU2_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAU2_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAU3  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAU3_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAU3_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAU4  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAU4_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAU4_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAU5  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAU5_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAU5_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAU6  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAU6_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAU6_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_RC_PREQAU7  ===================================================== */
+ #define R_PCIE0_PCI_RC_PREQAU7_PCIE_REQ_ADDR6332_Pos    (0UL)          /*!< PCIE_REQ_ADDR6332 (Bit 0)                             */
+ #define R_PCIE0_PCI_RC_PREQAU7_PCIE_REQ_ADDR6332_Msk    (0xffffffffUL) /*!< PCIE_REQ_ADDR6332 (Bitfield-Mask: 0xffffffff)         */
+/* ====================================================  PCI_EP_QUESTA0  ===================================================== */
+ #define R_PCIE0_PCI_EP_QUESTA0_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_QUESTA0_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_EP_QUESTA0_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_QUESTA0_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_EP_QUESTA1  ===================================================== */
+ #define R_PCIE0_PCI_EP_QUESTA1_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_QUESTA1_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_EP_QUESTA1_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_QUESTA1_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_EP_QUESTA2  ===================================================== */
+ #define R_PCIE0_PCI_EP_QUESTA2_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_QUESTA2_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_EP_QUESTA2_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_QUESTA2_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_EP_QUESTA3  ===================================================== */
+ #define R_PCIE0_PCI_EP_QUESTA3_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_QUESTA3_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_EP_QUESTA3_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_QUESTA3_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_EP_QUESTA4  ===================================================== */
+ #define R_PCIE0_PCI_EP_QUESTA4_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_QUESTA4_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_EP_QUESTA4_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_QUESTA4_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_EP_QUESTA5  ===================================================== */
+ #define R_PCIE0_PCI_EP_QUESTA5_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_QUESTA5_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_EP_QUESTA5_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_QUESTA5_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_EP_QUESTA6  ===================================================== */
+ #define R_PCIE0_PCI_EP_QUESTA6_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_QUESTA6_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_EP_QUESTA6_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_QUESTA6_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_EP_QUESTA7  ===================================================== */
+ #define R_PCIE0_PCI_EP_QUESTA7_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_QUESTA7_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_EP_QUESTA7_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_QUESTA7_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_QUESTA0  ===================================================== */
+ #define R_PCIE0_PCI_RC_QUESTA0_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_QUESTA0_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_RC_QUESTA0_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_QUESTA0_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_QUESTA1  ===================================================== */
+ #define R_PCIE0_PCI_RC_QUESTA1_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_QUESTA1_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_RC_QUESTA1_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_QUESTA1_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_QUESTA2  ===================================================== */
+ #define R_PCIE0_PCI_RC_QUESTA2_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_QUESTA2_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_RC_QUESTA2_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_QUESTA2_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_QUESTA3  ===================================================== */
+ #define R_PCIE0_PCI_RC_QUESTA3_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_QUESTA3_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_RC_QUESTA3_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_QUESTA3_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_QUESTA4  ===================================================== */
+ #define R_PCIE0_PCI_RC_QUESTA4_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_QUESTA4_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_RC_QUESTA4_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_QUESTA4_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_QUESTA5  ===================================================== */
+ #define R_PCIE0_PCI_RC_QUESTA5_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_QUESTA5_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_RC_QUESTA5_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_QUESTA5_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_QUESTA6  ===================================================== */
+ #define R_PCIE0_PCI_RC_QUESTA6_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_QUESTA6_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_RC_QUESTA6_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_QUESTA6_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ====================================================  PCI_RC_QUESTA7  ===================================================== */
+ #define R_PCIE0_PCI_RC_QUESTA7_LIST_NUM_Pos             (0UL)          /*!< LIST_NUM (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_QUESTA7_LIST_NUM_Msk             (0xfUL)        /*!< LIST_NUM (Bitfield-Mask: 0x0f)                        */
+ #define R_PCIE0_PCI_RC_QUESTA7_GO_LIST_Pos              (4UL)          /*!< GO_LIST (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_QUESTA7_GO_LIST_Msk              (0x10UL)       /*!< GO_LIST (Bitfield-Mask: 0x01)                         */
+/* ===================================================  PCI_EP_DMACESTA0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACESTA0_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA0_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA0_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMACESTA0_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA0_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMACESTA0_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA0_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA0_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA0_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA0_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA0_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_DMACESTA0_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA0_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA0_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACESTA0_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_EP_DMACESTA0_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_EP_DMACESTA1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACESTA1_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA1_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA1_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMACESTA1_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA1_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMACESTA1_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA1_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA1_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA1_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA1_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA1_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_DMACESTA1_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA1_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA1_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACESTA1_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_EP_DMACESTA1_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_EP_DMACESTA2  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACESTA2_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA2_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA2_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMACESTA2_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA2_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMACESTA2_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA2_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA2_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA2_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA2_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA2_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_DMACESTA2_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA2_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA2_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACESTA2_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_EP_DMACESTA2_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_EP_DMACESTA3  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACESTA3_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA3_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA3_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMACESTA3_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA3_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMACESTA3_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA3_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA3_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA3_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA3_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA3_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_DMACESTA3_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA3_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA3_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACESTA3_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_EP_DMACESTA3_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_EP_DMACESTA4  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACESTA4_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA4_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA4_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMACESTA4_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA4_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMACESTA4_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA4_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA4_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA4_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA4_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA4_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_DMACESTA4_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA4_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA4_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACESTA4_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_EP_DMACESTA4_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_EP_DMACESTA5  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACESTA5_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA5_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA5_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMACESTA5_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA5_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMACESTA5_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA5_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA5_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA5_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA5_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA5_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_DMACESTA5_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA5_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA5_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACESTA5_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_EP_DMACESTA5_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_EP_DMACESTA6  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACESTA6_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA6_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA6_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMACESTA6_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA6_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMACESTA6_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA6_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA6_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA6_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA6_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA6_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_DMACESTA6_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA6_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA6_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACESTA6_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_EP_DMACESTA6_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_EP_DMACESTA7  ==================================================== */
+ #define R_PCIE0_PCI_EP_DMACESTA7_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA7_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA7_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_EP_DMACESTA7_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA7_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_EP_DMACESTA7_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_EP_DMACESTA7_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA7_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA7_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_EP_DMACESTA7_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_DMACESTA7_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_EP_DMACESTA7_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_EP_DMACESTA7_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_EP_DMACESTA7_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_DMACESTA7_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_EP_DMACESTA7_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_RC_DMACESTA0  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACESTA0_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA0_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA0_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMACESTA0_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA0_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMACESTA0_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA0_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA0_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA0_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA0_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA0_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_DMACESTA0_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA0_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA0_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACESTA0_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_RC_DMACESTA0_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_RC_DMACESTA1  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACESTA1_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA1_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA1_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMACESTA1_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA1_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMACESTA1_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA1_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA1_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA1_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA1_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA1_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_DMACESTA1_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA1_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA1_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACESTA1_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_RC_DMACESTA1_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_RC_DMACESTA2  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACESTA2_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA2_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA2_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMACESTA2_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA2_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMACESTA2_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA2_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA2_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA2_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA2_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA2_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_DMACESTA2_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA2_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA2_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACESTA2_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_RC_DMACESTA2_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_RC_DMACESTA3  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACESTA3_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA3_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA3_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMACESTA3_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA3_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMACESTA3_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA3_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA3_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA3_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA3_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA3_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_DMACESTA3_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA3_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA3_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACESTA3_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_RC_DMACESTA3_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_RC_DMACESTA4  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACESTA4_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA4_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA4_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMACESTA4_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA4_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMACESTA4_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA4_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA4_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA4_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA4_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA4_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_DMACESTA4_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA4_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA4_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACESTA4_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_RC_DMACESTA4_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_RC_DMACESTA5  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACESTA5_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA5_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA5_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMACESTA5_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA5_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMACESTA5_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA5_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA5_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA5_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA5_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA5_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_DMACESTA5_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA5_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA5_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACESTA5_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_RC_DMACESTA5_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_RC_DMACESTA6  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACESTA6_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA6_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA6_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMACESTA6_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA6_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMACESTA6_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA6_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA6_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA6_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA6_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA6_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_DMACESTA6_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA6_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA6_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACESTA6_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_RC_DMACESTA6_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ===================================================  PCI_RC_DMACESTA7  ==================================================== */
+ #define R_PCIE0_PCI_RC_DMACESTA7_AXI_RESP_Pos           (0UL)          /*!< AXI_RESP (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA7_AXI_RESP_Msk           (0x3UL)        /*!< AXI_RESP (Bitfield-Mask: 0x03)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA7_MOR_STATUS_Pos         (8UL)          /*!< MOR_STATUS (Bit 8)                                    */
+ #define R_PCIE0_PCI_RC_DMACESTA7_MOR_STATUS_Msk         (0x700UL)      /*!< MOR_STATUS (Bitfield-Mask: 0x07)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA7_MOR_EP_ERR_Pos         (11UL)         /*!< MOR_EP_ERR (Bit 11)                                   */
+ #define R_PCIE0_PCI_RC_DMACESTA7_MOR_EP_ERR_Msk         (0x800UL)      /*!< MOR_EP_ERR (Bitfield-Mask: 0x01)                      */
+ #define R_PCIE0_PCI_RC_DMACESTA7_MOR_CH_PERR_Pos        (12UL)         /*!< MOR_CH_PERR (Bit 12)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA7_MOR_CH_PERR_Msk        (0x1000UL)     /*!< MOR_CH_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA7_MOR_CD_PERR_Pos        (13UL)         /*!< MOR_CD_PERR (Bit 13)                                  */
+ #define R_PCIE0_PCI_RC_DMACESTA7_MOR_CD_PERR_Msk        (0x2000UL)     /*!< MOR_CD_PERR (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_DMACESTA7_BME_DOWN_Pos           (16UL)         /*!< BME_DOWN (Bit 16)                                     */
+ #define R_PCIE0_PCI_RC_DMACESTA7_BME_DOWN_Msk           (0x10000UL)    /*!< BME_DOWN (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_DMACESTA7_BME_SUP_Pos            (17UL)         /*!< BME_SUP (Bit 17)                                      */
+ #define R_PCIE0_PCI_RC_DMACESTA7_BME_SUP_Msk            (0x20000UL)    /*!< BME_SUP (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_DMACESTA7_CFG_BM_DIS_EP_Pos      (18UL)         /*!< CFG_BM_DIS_EP (Bit 18)                                */
+ #define R_PCIE0_PCI_RC_DMACESTA7_CFG_BM_DIS_EP_Msk      (0x40000UL)    /*!< CFG_BM_DIS_EP (Bitfield-Mask: 0x01)                   */
+/* ==================================================  PCI_EP_AWBASEL0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F0_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F0_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F0_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F0_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F0_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F0_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F0_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F0_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F0_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F0_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F0_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F0_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F0_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F0_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F0_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F0_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F0_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F0_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F0_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F0_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F0_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F0_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F0_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F0_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F0_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F0_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F0_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F0_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F0_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F0_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F0_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F0_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F0_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F0_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F0_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F0_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F0_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F0_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F0_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F0_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F0_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F0_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F0_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F0_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F0_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F0_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F0_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F0_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWBASEL0  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEL0_AXIWE_Pos               (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_AWBASEL0_AXIWE_Msk               (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_AWBASEL0_AWB1104_Pos             (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEL0_AWB1104_Msk             (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_AWBASEL0_AWB3112_Pos             (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWBASEL0_AWB3112_Msk             (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWBASEL1  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEL1_AXIWE_Pos               (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_AWBASEL1_AXIWE_Msk               (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_AWBASEL1_AWB1104_Pos             (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEL1_AWB1104_Msk             (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_AWBASEL1_AWB3112_Pos             (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWBASEL1_AWB3112_Msk             (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWBASEL2  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEL2_AXIWE_Pos               (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_AWBASEL2_AXIWE_Msk               (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_AWBASEL2_AWB1104_Pos             (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEL2_AWB1104_Msk             (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_AWBASEL2_AWB3112_Pos             (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWBASEL2_AWB3112_Msk             (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWBASEL3  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEL3_AXIWE_Pos               (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_AWBASEL3_AXIWE_Msk               (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_AWBASEL3_AWB1104_Pos             (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEL3_AWB1104_Msk             (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_AWBASEL3_AWB3112_Pos             (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWBASEL3_AWB3112_Msk             (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWBASEL4  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEL4_AXIWE_Pos               (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_AWBASEL4_AXIWE_Msk               (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_AWBASEL4_AWB1104_Pos             (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEL4_AWB1104_Msk             (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_AWBASEL4_AWB3112_Pos             (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWBASEL4_AWB3112_Msk             (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWBASEL5  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEL5_AXIWE_Pos               (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_AWBASEL5_AXIWE_Msk               (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_AWBASEL5_AWB1104_Pos             (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEL5_AWB1104_Msk             (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_AWBASEL5_AWB3112_Pos             (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWBASEL5_AWB3112_Msk             (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWBASEL6  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEL6_AXIWE_Pos               (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_AWBASEL6_AXIWE_Msk               (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_AWBASEL6_AWB1104_Pos             (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEL6_AWB1104_Msk             (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_AWBASEL6_AWB3112_Pos             (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWBASEL6_AWB3112_Msk             (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWBASEL7  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEL7_AXIWE_Pos               (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_AWBASEL7_AXIWE_Msk               (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_AWBASEL7_AWB1104_Pos             (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEL7_AWB1104_Msk             (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_AWBASEL7_AWB3112_Pos             (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWBASEL7_AWB3112_Msk             (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEU0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU0_F0_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU0_F0_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU1_F0_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU1_F0_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU2_F0_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU2_F0_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU3_F0_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU3_F0_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU4_F0_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU4_F0_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU5_F0_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU5_F0_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU6_F0_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU6_F0_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU7_F0_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU7_F0_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_AWBASEU0  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEU0_AWB6332_Pos             (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEU0_AWB6332_Msk             (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_AWBASEU1  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEU1_AWB6332_Pos             (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEU1_AWB6332_Msk             (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_AWBASEU2  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEU2_AWB6332_Pos             (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEU2_AWB6332_Msk             (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_AWBASEU3  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEU3_AWB6332_Pos             (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEU3_AWB6332_Msk             (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_AWBASEU4  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEU4_AWB6332_Pos             (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEU4_AWB6332_Msk             (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_AWBASEU5  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEU5_AWB6332_Pos             (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEU5_AWB6332_Msk             (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_AWBASEU6  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEU6_AWB6332_Pos             (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEU6_AWB6332_Msk             (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_AWBASEU7  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWBASEU7_AWB6332_Pos             (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWBASEU7_AWB6332_Msk             (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWMASKL0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL0_F0_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL0_F0_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL0_F0_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL0_F0_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL1_F0_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL1_F0_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL1_F0_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL1_F0_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL2_F0_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL2_F0_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL2_F0_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL2_F0_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL3_F0_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL3_F0_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL3_F0_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL3_F0_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL4_F0_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL4_F0_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL4_F0_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL4_F0_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL5_F0_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL5_F0_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL5_F0_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL5_F0_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL6_F0_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL6_F0_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL6_F0_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL6_F0_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL7_F0_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL7_F0_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL7_F0_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL7_F0_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWMASKL0  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKL0_AWM1100_Pos             (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKL0_AWM1100_Msk             (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_AWMASKL0_AWM3112_Pos             (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWMASKL0_AWM3112_Msk             (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWMASKL1  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKL1_AWM1100_Pos             (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKL1_AWM1100_Msk             (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_AWMASKL1_AWM3112_Pos             (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWMASKL1_AWM3112_Msk             (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWMASKL2  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKL2_AWM1100_Pos             (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKL2_AWM1100_Msk             (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_AWMASKL2_AWM3112_Pos             (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWMASKL2_AWM3112_Msk             (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWMASKL3  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKL3_AWM1100_Pos             (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKL3_AWM1100_Msk             (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_AWMASKL3_AWM3112_Pos             (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWMASKL3_AWM3112_Msk             (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWMASKL4  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKL4_AWM1100_Pos             (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKL4_AWM1100_Msk             (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_AWMASKL4_AWM3112_Pos             (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWMASKL4_AWM3112_Msk             (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWMASKL5  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKL5_AWM1100_Pos             (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKL5_AWM1100_Msk             (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_AWMASKL5_AWM3112_Pos             (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWMASKL5_AWM3112_Msk             (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWMASKL6  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKL6_AWM1100_Pos             (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKL6_AWM1100_Msk             (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_AWMASKL6_AWM3112_Pos             (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWMASKL6_AWM3112_Msk             (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_AWMASKL7  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKL7_AWM1100_Pos             (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKL7_AWM1100_Msk             (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_AWMASKL7_AWM3112_Pos             (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_AWMASKL7_AWM3112_Msk             (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKU0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU0_F0_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU0_F0_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU1_F0_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU1_F0_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU2_F0_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU2_F0_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU3_F0_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU3_F0_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU4_F0_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU4_F0_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU5_F0_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU5_F0_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU6_F0_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU6_F0_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU7_F0_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU7_F0_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_AWMASKU0  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKU0_AWM6232_Pos             (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKU0_AWM6232_Msk             (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_AWMASKU1  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKU1_AWM6232_Pos             (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKU1_AWM6232_Msk             (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_AWMASKU2  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKU2_AWM6232_Pos             (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKU2_AWM6232_Msk             (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_AWMASKU3  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKU3_AWM6232_Pos             (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKU3_AWM6232_Msk             (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_AWMASKU4  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKU4_AWM6232_Pos             (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKU4_AWM6232_Msk             (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_AWMASKU5  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKU5_AWM6232_Pos             (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKU5_AWM6232_Msk             (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_AWMASKU6  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKU6_AWM6232_Pos             (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKU6_AWM6232_Msk             (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_AWMASKU7  ==================================================== */
+ #define R_PCIE0_PCI_RC_AWMASKU7_AWM6232_Pos             (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_AWMASKU7_AWM6232_Msk             (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ===================================================  PCI_EP_ADESTL0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL0_F0_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL0_F0_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL0_F0_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL0_F0_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL1_F0_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL1_F0_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL1_F0_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL1_F0_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL2_F0_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL2_F0_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL2_F0_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL2_F0_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL3_F0_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL3_F0_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL3_F0_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL3_F0_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL4_F0_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL4_F0_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL4_F0_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL4_F0_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL5_F0_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL5_F0_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL5_F0_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL5_F0_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL6_F0_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL6_F0_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL6_F0_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL6_F0_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL7_F0_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL7_F0_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL7_F0_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL7_F0_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_ADESTL0  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTL0_AD1100_Pos               (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTL0_AD1100_Msk               (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_ADESTL0_AD3112_Pos               (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_ADESTL0_AD3112_Msk               (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_ADESTL1  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTL1_AD1100_Pos               (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTL1_AD1100_Msk               (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_ADESTL1_AD3112_Pos               (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_ADESTL1_AD3112_Msk               (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_ADESTL2  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTL2_AD1100_Pos               (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTL2_AD1100_Msk               (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_ADESTL2_AD3112_Pos               (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_ADESTL2_AD3112_Msk               (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_ADESTL3  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTL3_AD1100_Pos               (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTL3_AD1100_Msk               (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_ADESTL3_AD3112_Pos               (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_ADESTL3_AD3112_Msk               (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_ADESTL4  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTL4_AD1100_Pos               (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTL4_AD1100_Msk               (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_ADESTL4_AD3112_Pos               (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_ADESTL4_AD3112_Msk               (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_ADESTL5  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTL5_AD1100_Pos               (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTL5_AD1100_Msk               (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_ADESTL5_AD3112_Pos               (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_ADESTL5_AD3112_Msk               (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_ADESTL6  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTL6_AD1100_Pos               (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTL6_AD1100_Msk               (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_ADESTL6_AD3112_Pos               (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_ADESTL6_AD3112_Msk               (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_ADESTL7  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTL7_AD1100_Pos               (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTL7_AD1100_Msk               (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_ADESTL7_AD3112_Pos               (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_ADESTL7_AD3112_Msk               (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTU0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU0_F0_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU0_F0_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU1_F0_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU1_F0_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU2_F0_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU2_F0_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU3_F0_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU3_F0_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU4_F0_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU4_F0_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU5_F0_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU5_F0_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU6_F0_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU6_F0_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU7_F0_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU7_F0_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_ADESTU0  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTU0_AD6332_Pos               (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTU0_AD6332_Msk               (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_ADESTU1  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTU1_AD6332_Pos               (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTU1_AD6332_Msk               (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_ADESTU2  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTU2_AD6332_Pos               (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTU2_AD6332_Msk               (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_ADESTU3  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTU3_AD6332_Pos               (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTU3_AD6332_Msk               (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_ADESTU4  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTU4_AD6332_Pos               (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTU4_AD6332_Msk               (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_ADESTU5  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTU5_AD6332_Pos               (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTU5_AD6332_Msk               (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_ADESTU6  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTU6_AD6332_Pos               (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTU6_AD6332_Msk               (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_ADESTU7  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADESTU7_AD6332_Pos               (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ADESTU7_AD6332_Msk               (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ==================================================  PCI_EP_PWBASEL0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F0_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F0_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F0_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F0_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F0_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F0_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F0_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F0_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F0_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F0_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F0_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F0_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F0_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F0_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F0_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F0_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F0_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F0_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F0_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F0_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F0_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F0_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F0_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F0_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F0_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F0_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F0_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F0_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F0_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F0_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F0_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F0_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F0_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F0_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F0_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F0_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F0_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F0_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F0_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F0_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F0_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F0_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F0_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F0_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F0_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F0_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F0_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F0_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWBASEL0  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEL0_PCIWE_Pos               (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_PWBASEL0_PCIWE_Msk               (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PWBASEL0_PWB1104_Pos             (4UL)          /*!< PWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEL0_PWB1104_Msk             (0xff0UL)      /*!< PWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_PWBASEL0_PWB3112_Pos             (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWBASEL0_PWB3112_Msk             (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWBASEL1  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEL1_PCIWE_Pos               (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_PWBASEL1_PCIWE_Msk               (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PWBASEL1_PWB1104_Pos             (4UL)          /*!< PWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEL1_PWB1104_Msk             (0xff0UL)      /*!< PWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_PWBASEL1_PWB3112_Pos             (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWBASEL1_PWB3112_Msk             (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWBASEL2  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEL2_PCIWE_Pos               (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_PWBASEL2_PCIWE_Msk               (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PWBASEL2_PWB1104_Pos             (4UL)          /*!< PWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEL2_PWB1104_Msk             (0xff0UL)      /*!< PWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_PWBASEL2_PWB3112_Pos             (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWBASEL2_PWB3112_Msk             (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWBASEL3  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEL3_PCIWE_Pos               (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_PWBASEL3_PCIWE_Msk               (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PWBASEL3_PWB1104_Pos             (4UL)          /*!< PWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEL3_PWB1104_Msk             (0xff0UL)      /*!< PWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_PWBASEL3_PWB3112_Pos             (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWBASEL3_PWB3112_Msk             (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWBASEL4  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEL4_PCIWE_Pos               (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_PWBASEL4_PCIWE_Msk               (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PWBASEL4_PWB1104_Pos             (4UL)          /*!< PWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEL4_PWB1104_Msk             (0xff0UL)      /*!< PWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_PWBASEL4_PWB3112_Pos             (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWBASEL4_PWB3112_Msk             (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWBASEL5  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEL5_PCIWE_Pos               (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_PWBASEL5_PCIWE_Msk               (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PWBASEL5_PWB1104_Pos             (4UL)          /*!< PWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEL5_PWB1104_Msk             (0xff0UL)      /*!< PWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_PWBASEL5_PWB3112_Pos             (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWBASEL5_PWB3112_Msk             (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWBASEL6  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEL6_PCIWE_Pos               (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_PWBASEL6_PCIWE_Msk               (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PWBASEL6_PWB1104_Pos             (4UL)          /*!< PWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEL6_PWB1104_Msk             (0xff0UL)      /*!< PWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_PWBASEL6_PWB3112_Pos             (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWBASEL6_PWB3112_Msk             (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWBASEL7  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEL7_PCIWE_Pos               (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_PWBASEL7_PCIWE_Msk               (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PWBASEL7_PWB1104_Pos             (4UL)          /*!< PWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEL7_PWB1104_Msk             (0xff0UL)      /*!< PWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_RC_PWBASEL7_PWB3112_Pos             (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWBASEL7_PWB3112_Msk             (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEU0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU0_F0_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU0_F0_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU1_F0_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU1_F0_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU2_F0_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU2_F0_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU3_F0_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU3_F0_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU4_F0_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU4_F0_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU5_F0_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU5_F0_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU6_F0_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU6_F0_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU7_F0_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU7_F0_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_PWBASEU0  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEU0_PWB6332_Pos             (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEU0_PWB6332_Msk             (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_PWBASEU1  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEU1_PWB6332_Pos             (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEU1_PWB6332_Msk             (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_PWBASEU2  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEU2_PWB6332_Pos             (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEU2_PWB6332_Msk             (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_PWBASEU3  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEU3_PWB6332_Pos             (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEU3_PWB6332_Msk             (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_PWBASEU4  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEU4_PWB6332_Pos             (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEU4_PWB6332_Msk             (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_PWBASEU5  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEU5_PWB6332_Pos             (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEU5_PWB6332_Msk             (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_PWBASEU6  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEU6_PWB6332_Pos             (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEU6_PWB6332_Msk             (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ====================================================  PCI_RC_PWBASEU7  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWBASEU7_PWB6332_Pos             (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWBASEU7_PWB6332_Msk             (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWMASKL0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL0_F0_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL0_F0_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL0_F0_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL0_F0_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL1_F0_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL1_F0_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL1_F0_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL1_F0_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL2_F0_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL2_F0_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL2_F0_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL2_F0_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL3_F0_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL3_F0_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL3_F0_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL3_F0_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL4_F0_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL4_F0_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL4_F0_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL4_F0_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL5_F0_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL5_F0_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL5_F0_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL5_F0_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL6_F0_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL6_F0_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL6_F0_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL6_F0_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL7_F0_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL7_F0_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL7_F0_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL7_F0_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWMASKL0  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKL0_PWM1100_Pos             (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKL0_PWM1100_Msk             (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_PWMASKL0_PWM3112_Pos             (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWMASKL0_PWM3112_Msk             (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWMASKL1  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKL1_PWM1100_Pos             (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKL1_PWM1100_Msk             (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_PWMASKL1_PWM3112_Pos             (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWMASKL1_PWM3112_Msk             (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWMASKL2  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKL2_PWM1100_Pos             (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKL2_PWM1100_Msk             (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_PWMASKL2_PWM3112_Pos             (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWMASKL2_PWM3112_Msk             (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWMASKL3  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKL3_PWM1100_Pos             (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKL3_PWM1100_Msk             (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_PWMASKL3_PWM3112_Pos             (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWMASKL3_PWM3112_Msk             (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWMASKL4  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKL4_PWM1100_Pos             (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKL4_PWM1100_Msk             (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_PWMASKL4_PWM3112_Pos             (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWMASKL4_PWM3112_Msk             (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWMASKL5  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKL5_PWM1100_Pos             (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKL5_PWM1100_Msk             (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_PWMASKL5_PWM3112_Pos             (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWMASKL5_PWM3112_Msk             (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWMASKL6  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKL6_PWM1100_Pos             (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKL6_PWM1100_Msk             (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_PWMASKL6_PWM3112_Pos             (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWMASKL6_PWM3112_Msk             (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ====================================================  PCI_RC_PWMASKL7  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKL7_PWM1100_Pos             (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKL7_PWM1100_Msk             (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_RC_PWMASKL7_PWM3112_Pos             (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_RC_PWMASKL7_PWM3112_Msk             (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKU0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU0_F0_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU0_F0_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU1_F0_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU1_F0_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU2_F0_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU2_F0_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU3_F0_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU3_F0_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU4_F0_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU4_F0_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU5_F0_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU5_F0_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU6_F0_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU6_F0_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU7_F0_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU7_F0_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_PWMASKU0  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKU0_PWM6232_Pos             (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKU0_PWM6232_Msk             (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_PWMASKU1  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKU1_PWM6232_Pos             (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKU1_PWM6232_Msk             (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_PWMASKU2  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKU2_PWM6232_Pos             (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKU2_PWM6232_Msk             (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_PWMASKU3  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKU3_PWM6232_Pos             (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKU3_PWM6232_Msk             (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_PWMASKU4  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKU4_PWM6232_Pos             (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKU4_PWM6232_Msk             (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_PWMASKU5  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKU5_PWM6232_Pos             (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKU5_PWM6232_Msk             (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_PWMASKU6  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKU6_PWM6232_Pos             (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKU6_PWM6232_Msk             (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ====================================================  PCI_RC_PWMASKU7  ==================================================== */
+ #define R_PCIE0_PCI_RC_PWMASKU7_PWM6232_Pos             (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_PWMASKU7_PWM6232_Msk             (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ===================================================  PCI_EP_PDESTL0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL0_F0_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL0_F0_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL0_F0_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL0_F0_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL1_F0_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL1_F0_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL1_F0_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL1_F0_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL2_F0_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL2_F0_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL2_F0_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL2_F0_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL3_F0_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL3_F0_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL3_F0_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL3_F0_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL4_F0_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL4_F0_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL4_F0_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL4_F0_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL5_F0_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL5_F0_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL5_F0_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL5_F0_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL6_F0_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL6_F0_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL6_F0_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL6_F0_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL7_F0_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL7_F0_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL7_F0_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL7_F0_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_PDESTL0  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTL0_PD1100_Pos               (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTL0_PD1100_Msk               (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_PDESTL0_PD3112_Pos               (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_PDESTL0_PD3112_Msk               (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_PDESTL1  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTL1_PD1100_Pos               (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTL1_PD1100_Msk               (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_PDESTL1_PD3112_Pos               (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_PDESTL1_PD3112_Msk               (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_PDESTL2  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTL2_PD1100_Pos               (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTL2_PD1100_Msk               (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_PDESTL2_PD3112_Pos               (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_PDESTL2_PD3112_Msk               (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_PDESTL3  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTL3_PD1100_Pos               (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTL3_PD1100_Msk               (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_PDESTL3_PD3112_Pos               (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_PDESTL3_PD3112_Msk               (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_PDESTL4  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTL4_PD1100_Pos               (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTL4_PD1100_Msk               (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_PDESTL4_PD3112_Pos               (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_PDESTL4_PD3112_Msk               (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_PDESTL5  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTL5_PD1100_Pos               (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTL5_PD1100_Msk               (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_PDESTL5_PD3112_Pos               (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_PDESTL5_PD3112_Msk               (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_PDESTL6  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTL6_PD1100_Pos               (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTL6_PD1100_Msk               (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_PDESTL6_PD3112_Pos               (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_PDESTL6_PD3112_Msk               (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ====================================================  PCI_RC_PDESTL7  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTL7_PD1100_Pos               (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTL7_PD1100_Msk               (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_RC_PDESTL7_PD3112_Pos               (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_PDESTL7_PD3112_Msk               (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTU0_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU0_F0_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU0_F0_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU1_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU1_F0_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU1_F0_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU2_F0_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU2_F0_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU3_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU3_F0_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU3_F0_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU4_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU4_F0_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU4_F0_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU5_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU5_F0_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU5_F0_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU6_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU6_F0_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU6_F0_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU7_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU7_F0_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU7_F0_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_PDESTU0  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTU0_PD6332_Pos               (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTU0_PD6332_Msk               (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_PDESTU1  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTU1_PD6332_Pos               (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTU1_PD6332_Msk               (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_PDESTU2  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTU2_PD6332_Pos               (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTU2_PD6332_Msk               (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_PDESTU3  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTU3_PD6332_Pos               (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTU3_PD6332_Msk               (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_PDESTU4  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTU4_PD6332_Pos               (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTU4_PD6332_Msk               (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_PDESTU5  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTU5_PD6332_Pos               (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTU5_PD6332_Msk               (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_PDESTU6  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTU6_PD6332_Pos               (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTU6_PD6332_Msk               (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_RC_PDESTU7  ===================================================== */
+ #define R_PCIE0_PCI_RC_PDESTU7_PD6332_Pos               (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_PDESTU7_PD6332_Msk               (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ==================================================  PCI_EP_AWBASEL0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F1_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F1_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F1_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F1_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F1_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL0_F1_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F1_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F1_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F1_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F1_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F1_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL1_F1_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F1_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F1_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F1_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F1_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F1_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL2_F1_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F1_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F1_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F1_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F1_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F1_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL3_F1_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F1_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F1_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F1_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F1_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F1_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL4_F1_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F1_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F1_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F1_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F1_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F1_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL5_F1_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F1_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F1_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F1_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F1_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F1_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL6_F1_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEL7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F1_AXIWE_Pos            (0UL)          /*!< AXIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F1_AXIWE_Msk            (0x1UL)        /*!< AXIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F1_AWB1104_Pos          (4UL)          /*!< AWB1104 (Bit 4)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F1_AWB1104_Msk          (0xff0UL)      /*!< AWB1104 (Bitfield-Mask: 0xff)                         */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F1_AWB3112_Pos          (12UL)         /*!< AWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWBASEL7_F1_AWB3112_Msk          (0xfffff000UL) /*!< AWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWBASEU0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU0_F1_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU0_F1_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU1_F1_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU1_F1_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU2_F1_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU2_F1_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU3_F1_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU3_F1_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU4_F1_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU4_F1_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU5_F1_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU5_F1_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU6_F1_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU6_F1_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWBASEU7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWBASEU7_F1_AWB6332_Pos          (0UL)          /*!< AWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWBASEU7_F1_AWB6332_Msk          (0xffffffffUL) /*!< AWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_AWMASKL0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL0_F1_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL0_F1_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL0_F1_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL0_F1_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL1_F1_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL1_F1_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL1_F1_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL1_F1_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL2_F1_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL2_F1_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL2_F1_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL2_F1_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL3_F1_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL3_F1_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL3_F1_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL3_F1_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL4_F1_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL4_F1_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL4_F1_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL4_F1_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL5_F1_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL5_F1_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL5_F1_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL5_F1_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL6_F1_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL6_F1_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL6_F1_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL6_F1_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKL7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKL7_F1_AWM1100_Pos          (0UL)          /*!< AWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKL7_F1_AWM1100_Msk          (0xfffUL)      /*!< AWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_AWMASKL7_F1_AWM3112_Pos          (12UL)         /*!< AWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_AWMASKL7_F1_AWM3112_Msk          (0xfffff000UL) /*!< AWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_AWMASKU0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU0_F1_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU0_F1_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU1_F1_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU1_F1_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU2_F1_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU2_F1_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU3_F1_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU3_F1_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU4_F1_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU4_F1_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU5_F1_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU5_F1_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU6_F1_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU6_F1_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_AWMASKU7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_AWMASKU7_F1_AWM6232_Pos          (0UL)          /*!< AWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_AWMASKU7_F1_AWM6232_Msk          (0x7fffffffUL) /*!< AWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ===================================================  PCI_EP_ADESTL0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL0_F1_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL0_F1_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL0_F1_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL0_F1_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL1_F1_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL1_F1_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL1_F1_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL1_F1_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL2_F1_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL2_F1_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL2_F1_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL2_F1_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL3_F1_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL3_F1_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL3_F1_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL3_F1_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL4_F1_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL4_F1_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL4_F1_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL4_F1_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL5_F1_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL5_F1_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL5_F1_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL5_F1_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL6_F1_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL6_F1_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL6_F1_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL6_F1_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTL7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTL7_F1_AD1100_Pos            (0UL)          /*!< AD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTL7_F1_AD1100_Msk            (0xfffUL)      /*!< AD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_ADESTL7_F1_AD3112_Pos            (12UL)         /*!< AD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_ADESTL7_F1_AD3112_Msk            (0xfffff000UL) /*!< AD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_ADESTU0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU0_F1_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU0_F1_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU1_F1_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU1_F1_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU2_F1_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU2_F1_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU3_F1_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU3_F1_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU4_F1_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU4_F1_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU5_F1_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU5_F1_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU6_F1_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU6_F1_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_ADESTU7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_ADESTU7_F1_AD6332_Pos            (0UL)          /*!< AD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_ADESTU7_F1_AD6332_Msk            (0xffffffffUL) /*!< AD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ==================================================  PCI_EP_PWBASEL0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F1_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F1_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F1_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F1_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F1_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL0_F1_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F1_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F1_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F1_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F1_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F1_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL1_F1_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F1_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F1_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F1_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F1_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F1_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL2_F1_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F1_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F1_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F1_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F1_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F1_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL3_F1_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F1_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F1_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F1_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F1_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F1_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL4_F1_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F1_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F1_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F1_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F1_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F1_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL5_F1_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F1_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F1_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F1_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F1_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F1_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL6_F1_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEL7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F1_PCIWE_Pos            (0UL)          /*!< PCIWE (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F1_PCIWE_Msk            (0x1UL)        /*!< PCIWE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F1_PWB114_Pos           (4UL)          /*!< PWB114 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F1_PWB114_Msk           (0xff0UL)      /*!< PWB114 (Bitfield-Mask: 0xff)                          */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F1_PWB3112_Pos          (12UL)         /*!< PWB3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWBASEL7_F1_PWB3112_Msk          (0xfffff000UL) /*!< PWB3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWBASEU0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU0_F1_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU0_F1_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU1_F1_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU1_F1_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU2_F1_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU2_F1_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU3_F1_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU3_F1_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU4_F1_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU4_F1_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU5_F1_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU5_F1_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU6_F1_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU6_F1_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWBASEU7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWBASEU7_F1_PWB6332_Pos          (0UL)          /*!< PWB6332 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWBASEU7_F1_PWB6332_Msk          (0xffffffffUL) /*!< PWB6332 (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_PWMASKL0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL0_F1_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL0_F1_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL0_F1_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL0_F1_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL1_F1_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL1_F1_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL1_F1_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL1_F1_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL2_F1_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL2_F1_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL2_F1_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL2_F1_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL3_F1_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL3_F1_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL3_F1_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL3_F1_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL4_F1_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL4_F1_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL4_F1_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL4_F1_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL5_F1_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL5_F1_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL5_F1_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL5_F1_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL6_F1_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL6_F1_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL6_F1_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL6_F1_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKL7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKL7_F1_PWM1100_Pos          (0UL)          /*!< PWM1100 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKL7_F1_PWM1100_Msk          (0xfffUL)      /*!< PWM1100 (Bitfield-Mask: 0xfff)                        */
+ #define R_PCIE0_PCI_EP_PWMASKL7_F1_PWM3112_Pos          (12UL)         /*!< PWM3112 (Bit 12)                                      */
+ #define R_PCIE0_PCI_EP_PWMASKL7_F1_PWM3112_Msk          (0xfffff000UL) /*!< PWM3112 (Bitfield-Mask: 0xfffff)                      */
+/* ==================================================  PCI_EP_PWMASKU0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU0_F1_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU0_F1_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU1_F1_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU1_F1_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU2_F1_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU2_F1_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU3_F1_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU3_F1_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU4_F1_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU4_F1_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU5_F1_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU5_F1_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU6_F1_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU6_F1_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ==================================================  PCI_EP_PWMASKU7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PWMASKU7_F1_PWM6232_Pos          (0UL)          /*!< PWM6232 (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_PWMASKU7_F1_PWM6232_Msk          (0x7fffffffUL) /*!< PWM6232 (Bitfield-Mask: 0x7fffffff)                   */
+/* ===================================================  PCI_EP_PDESTL0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL0_F1_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL0_F1_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL0_F1_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL0_F1_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL1_F1_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL1_F1_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL1_F1_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL1_F1_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL2_F1_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL2_F1_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL2_F1_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL2_F1_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL3_F1_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL3_F1_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL3_F1_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL3_F1_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL4_F1_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL4_F1_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL4_F1_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL4_F1_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL5_F1_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL5_F1_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL5_F1_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL5_F1_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL6_F1_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL6_F1_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL6_F1_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL6_F1_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTL7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTL7_F1_PD1100_Pos            (0UL)          /*!< PD1100 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTL7_F1_PD1100_Msk            (0xfffUL)      /*!< PD1100 (Bitfield-Mask: 0xfff)                         */
+ #define R_PCIE0_PCI_EP_PDESTL7_F1_PD3112_Pos            (12UL)         /*!< PD3112 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_PDESTL7_F1_PD3112_Msk            (0xfffff000UL) /*!< PD3112 (Bitfield-Mask: 0xfffff)                       */
+/* ===================================================  PCI_EP_PDESTU0_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU0_F1_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU0_F1_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU1_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU1_F1_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU1_F1_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU2_F1_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU2_F1_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU3_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU3_F1_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU3_F1_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU4_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU4_F1_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU4_F1_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU5_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU5_F1_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU5_F1_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU6_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU6_F1_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU6_F1_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* ===================================================  PCI_EP_PDESTU7_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PDESTU7_F1_PD6332_Pos            (0UL)          /*!< PD6332 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_PDESTU7_F1_PD6332_Msk            (0xffffffffUL) /*!< PD6332 (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  PCI_EP_VID_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_VID_F0_VID_Pos                   (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_VID_F0_VID_Msk                   (0xffffUL)     /*!< VID (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_VID_F0_DID_Pos                   (16UL)         /*!< DID (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_VID_F0_DID_Msk                   (0xffff0000UL) /*!< DID (Bitfield-Mask: 0xffff)                           */
+/* =====================================================  PCI_EP_VID_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_VID_F1_VID_Pos                   (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_VID_F1_VID_Msk                   (0xffffUL)     /*!< VID (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_EP_VID_F1_DID_Pos                   (16UL)         /*!< DID (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_VID_F1_DID_Msk                   (0xffff0000UL) /*!< DID (Bitfield-Mask: 0xffff)                           */
+/* ======================================================  PCI_RC_VID  ======================================================= */
+ #define R_PCIE0_PCI_RC_VID_VID_Pos                      (0UL)          /*!< VID (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_VID_VID_Msk                      (0xffffUL)     /*!< VID (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_VID_DID_Pos                      (16UL)         /*!< DID (Bit 16)                                          */
+ #define R_PCIE0_PCI_RC_VID_DID_Msk                      (0xffff0000UL) /*!< DID (Bitfield-Mask: 0xffff)                           */
+/* ===================================================  PCI_EP_COM_STA_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_IOSE_Pos              (0UL)          /*!< IOSE (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_IOSE_Msk              (0x1UL)        /*!< IOSE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_MSE_Pos               (1UL)          /*!< MSE (Bit 1)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_MSE_Msk               (0x2UL)        /*!< MSE (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_BME_Pos               (2UL)          /*!< BME (Bit 2)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_BME_Msk               (0x4UL)        /*!< BME (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_PER_Pos               (6UL)          /*!< PER (Bit 6)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_PER_Msk               (0x40UL)       /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_SERRE_Pos             (8UL)          /*!< SERRE (Bit 8)                                         */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_SERRE_Msk             (0x100UL)      /*!< SERRE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_ID_Pos                (10UL)         /*!< ID (Bit 10)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_ID_Msk                (0x400UL)      /*!< ID (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_IR_Pos                (16UL)         /*!< IR (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_IR_Msk                (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_IS_Pos                (19UL)         /*!< IS (Bit 19)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_IS_Msk                (0x80000UL)    /*!< IS (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_CL_Pos                (20UL)         /*!< CL (Bit 20)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_CL_Msk                (0x100000UL)   /*!< CL (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_MDPE_Pos              (24UL)         /*!< MDPE (Bit 24)                                         */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_MDPE_Msk              (0x1000000UL)  /*!< MDPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_STA_Pos               (27UL)         /*!< STA (Bit 27)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_STA_Msk               (0x8000000UL)  /*!< STA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_RTA_Pos               (28UL)         /*!< RTA (Bit 28)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_RTA_Msk               (0x10000000UL) /*!< RTA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_RMA_Pos               (29UL)         /*!< RMA (Bit 29)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_RMA_Msk               (0x20000000UL) /*!< RMA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_SSE_Pos               (30UL)         /*!< SSE (Bit 30)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_SSE_Msk               (0x40000000UL) /*!< SSE (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_DPE_Pos               (31UL)         /*!< DPE (Bit 31)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F0_DPE_Msk               (0x80000000UL) /*!< DPE (Bitfield-Mask: 0x01)                             */
+/* ===================================================  PCI_EP_COM_STA_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_IOSE_Pos              (0UL)          /*!< IOSE (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_IOSE_Msk              (0x1UL)        /*!< IOSE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_MSE_Pos               (1UL)          /*!< MSE (Bit 1)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_MSE_Msk               (0x2UL)        /*!< MSE (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_BME_Pos               (2UL)          /*!< BME (Bit 2)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_BME_Msk               (0x4UL)        /*!< BME (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_PER_Pos               (6UL)          /*!< PER (Bit 6)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_PER_Msk               (0x40UL)       /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_SERRE_Pos             (8UL)          /*!< SERRE (Bit 8)                                         */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_SERRE_Msk             (0x100UL)      /*!< SERRE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_ID_Pos                (10UL)         /*!< ID (Bit 10)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_ID_Msk                (0x400UL)      /*!< ID (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_IR_Pos                (16UL)         /*!< IR (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_IR_Msk                (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_IS_Pos                (19UL)         /*!< IS (Bit 19)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_IS_Msk                (0x80000UL)    /*!< IS (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_CL_Pos                (20UL)         /*!< CL (Bit 20)                                           */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_CL_Msk                (0x100000UL)   /*!< CL (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_MDPE_Pos              (24UL)         /*!< MDPE (Bit 24)                                         */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_MDPE_Msk              (0x1000000UL)  /*!< MDPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_STA_Pos               (27UL)         /*!< STA (Bit 27)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_STA_Msk               (0x8000000UL)  /*!< STA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_RTA_Pos               (28UL)         /*!< RTA (Bit 28)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_RTA_Msk               (0x10000000UL) /*!< RTA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_RMA_Pos               (29UL)         /*!< RMA (Bit 29)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_RMA_Msk               (0x20000000UL) /*!< RMA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_SSE_Pos               (30UL)         /*!< SSE (Bit 30)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_SSE_Msk               (0x40000000UL) /*!< SSE (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_DPE_Pos               (31UL)         /*!< DPE (Bit 31)                                          */
+ #define R_PCIE0_PCI_EP_COM_STA_F1_DPE_Msk               (0x80000000UL) /*!< DPE (Bitfield-Mask: 0x01)                             */
+/* ====================================================  PCI_RC_COM_STA  ===================================================== */
+ #define R_PCIE0_PCI_RC_COM_STA_IOSE_Pos                 (0UL)          /*!< IOSE (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_COM_STA_IOSE_Msk                 (0x1UL)        /*!< IOSE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_COM_STA_MSE_Pos                  (1UL)          /*!< MSE (Bit 1)                                           */
+ #define R_PCIE0_PCI_RC_COM_STA_MSE_Msk                  (0x2UL)        /*!< MSE (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_COM_STA_BME_Pos                  (2UL)          /*!< BME (Bit 2)                                           */
+ #define R_PCIE0_PCI_RC_COM_STA_BME_Msk                  (0x4UL)        /*!< BME (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_COM_STA_PER_Pos                  (6UL)          /*!< PER (Bit 6)                                           */
+ #define R_PCIE0_PCI_RC_COM_STA_PER_Msk                  (0x40UL)       /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_COM_STA_SERRE_Pos                (8UL)          /*!< SERRE (Bit 8)                                         */
+ #define R_PCIE0_PCI_RC_COM_STA_SERRE_Msk                (0x100UL)      /*!< SERRE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_COM_STA_ID_Pos                   (10UL)         /*!< ID (Bit 10)                                           */
+ #define R_PCIE0_PCI_RC_COM_STA_ID_Msk                   (0x400UL)      /*!< ID (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_COM_STA_IS_Pos                   (19UL)         /*!< IS (Bit 19)                                           */
+ #define R_PCIE0_PCI_RC_COM_STA_IS_Msk                   (0x80000UL)    /*!< IS (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_COM_STA_CL_Pos                   (20UL)         /*!< CL (Bit 20)                                           */
+ #define R_PCIE0_PCI_RC_COM_STA_CL_Msk                   (0x100000UL)   /*!< CL (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_COM_STA_SSE_Pos                  (30UL)         /*!< SSE (Bit 30)                                          */
+ #define R_PCIE0_PCI_RC_COM_STA_SSE_Msk                  (0x40000000UL) /*!< SSE (Bitfield-Mask: 0x01)                             */
+/* ===================================================  PCI_EP_RID_CC_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_RID_CC_F0_RID_Pos                (0UL)          /*!< RID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_RID_CC_F0_RID_Msk                (0xffUL)       /*!< RID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_RID_CC_F0_CC_Pos                 (8UL)          /*!< CC (Bit 8)                                            */
+ #define R_PCIE0_PCI_EP_RID_CC_F0_CC_Msk                 (0xffffff00UL) /*!< CC (Bitfield-Mask: 0xffffff)                          */
+/* ===================================================  PCI_EP_RID_CC_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_RID_CC_F1_RID_Pos                (0UL)          /*!< RID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_RID_CC_F1_RID_Msk                (0xffUL)       /*!< RID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_RID_CC_F1_CC_Pos                 (8UL)          /*!< CC (Bit 8)                                            */
+ #define R_PCIE0_PCI_EP_RID_CC_F1_CC_Msk                 (0xffffff00UL) /*!< CC (Bitfield-Mask: 0xffffff)                          */
+/* =====================================================  PCI_RC_RID_CC  ===================================================== */
+ #define R_PCIE0_PCI_RC_RID_CC_RID_Pos                   (0UL)          /*!< RID (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_RID_CC_RID_Msk                   (0xffUL)       /*!< RID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_RID_CC_CC_Pos                    (8UL)          /*!< CC (Bit 8)                                            */
+ #define R_PCIE0_PCI_RC_RID_CC_CC_Msk                    (0xffffff00UL) /*!< CC (Bitfield-Mask: 0xffffff)                          */
+/* ====================================================  PCI_EP_CL_HT_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_CL_HT_F0_CLS_Pos                 (0UL)          /*!< CLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_CL_HT_F0_CLS_Msk                 (0xffUL)       /*!< CLS (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_CL_HT_F0_HT_Pos                  (16UL)         /*!< HT (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_CL_HT_F0_HT_Msk                  (0xff0000UL)   /*!< HT (Bitfield-Mask: 0xff)                              */
+/* ====================================================  PCI_EP_CL_HT_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_CL_HT_F1_CLS_Pos                 (0UL)          /*!< CLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_CL_HT_F1_CLS_Msk                 (0xffUL)       /*!< CLS (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_CL_HT_F1_HT_Pos                  (16UL)         /*!< HT (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_CL_HT_F1_HT_Msk                  (0xff0000UL)   /*!< HT (Bitfield-Mask: 0xff)                              */
+/* =====================================================  PCI_RC_CL_HT  ====================================================== */
+ #define R_PCIE0_PCI_RC_CL_HT_CLS_Pos                    (0UL)          /*!< CLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_CL_HT_CLS_Msk                    (0xffUL)       /*!< CLS (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_CL_HT_HT_Pos                     (16UL)         /*!< HT (Bit 16)                                           */
+ #define R_PCIE0_PCI_RC_CL_HT_HT_Msk                     (0xff0000UL)   /*!< HT (Bitfield-Mask: 0xff)                              */
+/* ====================================================  PCI_EP_BAR0_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR0_F0_MSI_Pos                  (0UL)          /*!< MSI (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_BAR0_F0_MSI_Msk                  (0x1UL)        /*!< MSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_BAR0_F0_TYPE_Pos                 (2UL)          /*!< TYPE (Bit 2)                                          */
+ #define R_PCIE0_PCI_EP_BAR0_F0_TYPE_Msk                 (0x4UL)        /*!< TYPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_BAR0_F0_PF_Pos                   (3UL)          /*!< PF (Bit 3)                                            */
+ #define R_PCIE0_PCI_EP_BAR0_F0_PF_Msk                   (0x8UL)        /*!< PF (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_BAR0_F0_BAR0_Pos                 (4UL)          /*!< BAR0 (Bit 4)                                          */
+ #define R_PCIE0_PCI_EP_BAR0_F0_BAR0_Msk                 (0xfffffff0UL) /*!< BAR0 (Bitfield-Mask: 0xfffffff)                       */
+/* ====================================================  PCI_EP_BAR0_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR0_F1_MSI_Pos                  (0UL)          /*!< MSI (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_BAR0_F1_MSI_Msk                  (0x1UL)        /*!< MSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_BAR0_F1_TYPE_Pos                 (2UL)          /*!< TYPE (Bit 2)                                          */
+ #define R_PCIE0_PCI_EP_BAR0_F1_TYPE_Msk                 (0x4UL)        /*!< TYPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_BAR0_F1_PF_Pos                   (3UL)          /*!< PF (Bit 3)                                            */
+ #define R_PCIE0_PCI_EP_BAR0_F1_PF_Msk                   (0x8UL)        /*!< PF (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_BAR0_F1_BAR0_Pos                 (4UL)          /*!< BAR0 (Bit 4)                                          */
+ #define R_PCIE0_PCI_EP_BAR0_F1_BAR0_Msk                 (0xfffffff0UL) /*!< BAR0 (Bitfield-Mask: 0xfffffff)                       */
+/* ======================================================  PCI_RC_BAR0  ====================================================== */
+ #define R_PCIE0_PCI_RC_BAR0_MSI_Pos                     (0UL)          /*!< MSI (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_BAR0_MSI_Msk                     (0x1UL)        /*!< MSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_BAR0_TYPE_Pos                    (2UL)          /*!< TYPE (Bit 2)                                          */
+ #define R_PCIE0_PCI_RC_BAR0_TYPE_Msk                    (0x4UL)        /*!< TYPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_BAR0_PF_Pos                      (3UL)          /*!< PF (Bit 3)                                            */
+ #define R_PCIE0_PCI_RC_BAR0_PF_Msk                      (0x8UL)        /*!< PF (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_BAR0_BAR0_Pos                    (4UL)          /*!< BAR0 (Bit 4)                                          */
+ #define R_PCIE0_PCI_RC_BAR0_BAR0_Msk                    (0xfffffff0UL) /*!< BAR0 (Bitfield-Mask: 0xfffffff)                       */
+/* ====================================================  PCI_EP_BAR1_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR1_F0_BAR1_Pos                 (0UL)          /*!< BAR1 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BAR1_F0_BAR1_Msk                 (0xffffffffUL) /*!< BAR1 (Bitfield-Mask: 0xffffffff)                      */
+/* ====================================================  PCI_EP_BAR1_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR1_F1_BAR1_Pos                 (0UL)          /*!< BAR1 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BAR1_F1_BAR1_Msk                 (0xffffffffUL) /*!< BAR1 (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  PCI_RC_BAR1  ====================================================== */
+ #define R_PCIE0_PCI_RC_BAR1_BAR1_Pos                    (0UL)          /*!< BAR1 (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_BAR1_BAR1_Msk                    (0xffffffffUL) /*!< BAR1 (Bitfield-Mask: 0xffffffff)                      */
+/* ====================================================  PCI_EP_BAR2_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR2_F0_MSI_Pos                  (0UL)          /*!< MSI (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_BAR2_F0_MSI_Msk                  (0x1UL)        /*!< MSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_BAR2_F0_TYPE_Pos                 (2UL)          /*!< TYPE (Bit 2)                                          */
+ #define R_PCIE0_PCI_EP_BAR2_F0_TYPE_Msk                 (0x4UL)        /*!< TYPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_BAR2_F0_PF_Pos                   (3UL)          /*!< PF (Bit 3)                                            */
+ #define R_PCIE0_PCI_EP_BAR2_F0_PF_Msk                   (0x8UL)        /*!< PF (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_BAR2_F0_BAR2_Pos                 (4UL)          /*!< BAR2 (Bit 4)                                          */
+ #define R_PCIE0_PCI_EP_BAR2_F0_BAR2_Msk                 (0xfffffff0UL) /*!< BAR2 (Bitfield-Mask: 0xfffffff)                       */
+/* ====================================================  PCI_EP_BAR2_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR2_F1_MSI_Pos                  (0UL)          /*!< MSI (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_BAR2_F1_MSI_Msk                  (0x1UL)        /*!< MSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_BAR2_F1_TYPE_Pos                 (2UL)          /*!< TYPE (Bit 2)                                          */
+ #define R_PCIE0_PCI_EP_BAR2_F1_TYPE_Msk                 (0x4UL)        /*!< TYPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_BAR2_F1_PF_Pos                   (3UL)          /*!< PF (Bit 3)                                            */
+ #define R_PCIE0_PCI_EP_BAR2_F1_PF_Msk                   (0x8UL)        /*!< PF (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_BAR2_F1_BAR2_Pos                 (4UL)          /*!< BAR2 (Bit 4)                                          */
+ #define R_PCIE0_PCI_EP_BAR2_F1_BAR2_Msk                 (0xfffffff0UL) /*!< BAR2 (Bitfield-Mask: 0xfffffff)                       */
+/* ======================================================  PCI_RC_BNR  ======================================================= */
+ #define R_PCIE0_PCI_RC_BNR_PBN_Pos                      (0UL)          /*!< PBN (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_BNR_PBN_Msk                      (0xffUL)       /*!< PBN (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_BNR_SBN_Pos                      (8UL)          /*!< SBN (Bit 8)                                           */
+ #define R_PCIE0_PCI_RC_BNR_SBN_Msk                      (0xff00UL)     /*!< SBN (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_BNR_SB_Pos                       (16UL)         /*!< SB (Bit 16)                                           */
+ #define R_PCIE0_PCI_RC_BNR_SB_Msk                       (0xff0000UL)   /*!< SB (Bitfield-Mask: 0xff)                              */
+/* ====================================================  PCI_EP_BAR3_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR3_F0_BAR3_Pos                 (0UL)          /*!< BAR3 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BAR3_F0_BAR3_Msk                 (0xffffffffUL) /*!< BAR3 (Bitfield-Mask: 0xffffffff)                      */
+/* ====================================================  PCI_EP_BAR3_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR3_F1_BAR3_Pos                 (0UL)          /*!< BAR3 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BAR3_F1_BAR3_Msk                 (0xffffffffUL) /*!< BAR3 (Bitfield-Mask: 0xffffffff)                      */
+/* ====================================================  PCI_RC_IOBL_SS  ===================================================== */
+ #define R_PCIE0_PCI_RC_IOBL_SS_IOB_Pos                  (0UL)          /*!< IOB (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_IOBL_SS_IOB_Msk                  (0xffUL)       /*!< IOB (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_IOBL_SS_IOL_Pos                  (8UL)          /*!< IOL (Bit 8)                                           */
+ #define R_PCIE0_PCI_RC_IOBL_SS_IOL_Msk                  (0xff00UL)     /*!< IOL (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_IOBL_SS_MDPE_Pos                 (24UL)         /*!< MDPE (Bit 24)                                         */
+ #define R_PCIE0_PCI_RC_IOBL_SS_MDPE_Msk                 (0x1000000UL)  /*!< MDPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_IOBL_SS_STA_Pos                  (27UL)         /*!< STA (Bit 27)                                          */
+ #define R_PCIE0_PCI_RC_IOBL_SS_STA_Msk                  (0x8000000UL)  /*!< STA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_IOBL_SS_RTA_Pos                  (28UL)         /*!< RTA (Bit 28)                                          */
+ #define R_PCIE0_PCI_RC_IOBL_SS_RTA_Msk                  (0x10000000UL) /*!< RTA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_IOBL_SS_RMA_Pos                  (29UL)         /*!< RMA (Bit 29)                                          */
+ #define R_PCIE0_PCI_RC_IOBL_SS_RMA_Msk                  (0x20000000UL) /*!< RMA (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_IOBL_SS_RSE_Pos                  (30UL)         /*!< RSE (Bit 30)                                          */
+ #define R_PCIE0_PCI_RC_IOBL_SS_RSE_Msk                  (0x40000000UL) /*!< RSE (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_IOBL_SS_DPE_Pos                  (31UL)         /*!< DPE (Bit 31)                                          */
+ #define R_PCIE0_PCI_RC_IOBL_SS_DPE_Msk                  (0x80000000UL) /*!< DPE (Bitfield-Mask: 0x01)                             */
+/* ====================================================  PCI_EP_BAR4_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR4_F0_MSI_Pos                  (0UL)          /*!< MSI (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_BAR4_F0_MSI_Msk                  (0x1UL)        /*!< MSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_BAR4_F0_TYPE_Pos                 (2UL)          /*!< TYPE (Bit 2)                                          */
+ #define R_PCIE0_PCI_EP_BAR4_F0_TYPE_Msk                 (0x4UL)        /*!< TYPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_BAR4_F0_PF_Pos                   (3UL)          /*!< PF (Bit 3)                                            */
+ #define R_PCIE0_PCI_EP_BAR4_F0_PF_Msk                   (0x8UL)        /*!< PF (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_BAR4_F0_BAR4_Pos                 (4UL)          /*!< BAR4 (Bit 4)                                          */
+ #define R_PCIE0_PCI_EP_BAR4_F0_BAR4_Msk                 (0xfffffff0UL) /*!< BAR4 (Bitfield-Mask: 0xfffffff)                       */
+/* ====================================================  PCI_EP_BAR4_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR4_F1_MSI_Pos                  (0UL)          /*!< MSI (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_BAR4_F1_MSI_Msk                  (0x1UL)        /*!< MSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_BAR4_F1_TYPE_Pos                 (2UL)          /*!< TYPE (Bit 2)                                          */
+ #define R_PCIE0_PCI_EP_BAR4_F1_TYPE_Msk                 (0x4UL)        /*!< TYPE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_BAR4_F1_PF_Pos                   (3UL)          /*!< PF (Bit 3)                                            */
+ #define R_PCIE0_PCI_EP_BAR4_F1_PF_Msk                   (0x8UL)        /*!< PF (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_BAR4_F1_BAR4_Pos                 (4UL)          /*!< BAR4 (Bit 4)                                          */
+ #define R_PCIE0_PCI_EP_BAR4_F1_BAR4_Msk                 (0xfffffff0UL) /*!< BAR4 (Bitfield-Mask: 0xfffffff)                       */
+/* =====================================================  PCI_RC_MEMBL  ====================================================== */
+ #define R_PCIE0_PCI_RC_MEMBL_MB_Pos                     (4UL)          /*!< MB (Bit 4)                                            */
+ #define R_PCIE0_PCI_RC_MEMBL_MB_Msk                     (0xfff0UL)     /*!< MB (Bitfield-Mask: 0xfff)                             */
+ #define R_PCIE0_PCI_RC_MEMBL_ML_Pos                     (20UL)         /*!< ML (Bit 20)                                           */
+ #define R_PCIE0_PCI_RC_MEMBL_ML_Msk                     (0xfff00000UL) /*!< ML (Bitfield-Mask: 0xfff)                             */
+/* ====================================================  PCI_EP_BAR5_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR5_F0_BAR5_Pos                 (0UL)          /*!< BAR5 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BAR5_F0_BAR5_Msk                 (0xffffffffUL) /*!< BAR5 (Bitfield-Mask: 0xffffffff)                      */
+/* ====================================================  PCI_EP_BAR5_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_BAR5_F1_BAR5_Pos                 (0UL)          /*!< BAR5 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BAR5_F1_BAR5_Msk                 (0xffffffffUL) /*!< BAR5 (Bitfield-Mask: 0xffffffff)                      */
+/* ======================================================  PCI_RC_PMBL  ====================================================== */
+ #define R_PCIE0_PCI_RC_PMBL_PMB_Pos                     (0UL)          /*!< PMB (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_PMBL_PMB_Msk                     (0xffffUL)     /*!< PMB (Bitfield-Mask: 0xffff)                           */
+ #define R_PCIE0_PCI_RC_PMBL_PML_Pos                     (16UL)         /*!< PML (Bit 16)                                          */
+ #define R_PCIE0_PCI_RC_PMBL_PML_Msk                     (0xffff0000UL) /*!< PML (Bitfield-Mask: 0xffff)                           */
+/* =====================================================  PCI_RC_PBUP32  ===================================================== */
+/* ===================================================  PCI_EP_SUBSID_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_SUBSID_F0_SVID_Pos               (0UL)          /*!< SVID (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_SUBSID_F0_SVID_Msk               (0xffffUL)     /*!< SVID (Bitfield-Mask: 0xffff)                          */
+ #define R_PCIE0_PCI_EP_SUBSID_F0_SID_Pos                (16UL)         /*!< SID (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_SUBSID_F0_SID_Msk                (0xffff0000UL) /*!< SID (Bitfield-Mask: 0xffff)                           */
+/* ===================================================  PCI_EP_SUBSID_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_SUBSID_F1_SVID_Pos               (0UL)          /*!< SVID (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_SUBSID_F1_SVID_Msk               (0xffffUL)     /*!< SVID (Bitfield-Mask: 0xffff)                          */
+ #define R_PCIE0_PCI_EP_SUBSID_F1_SID_Pos                (16UL)         /*!< SID (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_SUBSID_F1_SID_Msk                (0xffff0000UL) /*!< SID (Bitfield-Mask: 0xffff)                           */
+/* =====================================================  PCI_RC_PLUP32  ===================================================== */
+/* ====================================================  PCI_RC_IOBLUP16  ==================================================== */
+ #define R_PCIE0_PCI_RC_IOBLUP16_IOBU16_Pos              (0UL)          /*!< IOBU16 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_IOBLUP16_IOBU16_Msk              (0xffffUL)     /*!< IOBU16 (Bitfield-Mask: 0xffff)                        */
+ #define R_PCIE0_PCI_RC_IOBLUP16_IOLU16_Pos              (16UL)         /*!< IOLU16 (Bit 16)                                       */
+ #define R_PCIE0_PCI_RC_IOBLUP16_IOLU16_Msk              (0xffff0000UL) /*!< IOLU16 (Bitfield-Mask: 0xffff)                        */
+/* =====================================================  PCI_EP_CP_F0  ====================================================== */
+ #define R_PCIE0_PCI_EP_CP_F0_CP_Pos                     (0UL)          /*!< CP (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_CP_F0_CP_Msk                     (0xffUL)       /*!< CP (Bitfield-Mask: 0xff)                              */
+/* =====================================================  PCI_EP_CP_F1  ====================================================== */
+ #define R_PCIE0_PCI_EP_CP_F1_CP_Pos                     (0UL)          /*!< CP (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_CP_F1_CP_Msk                     (0xffUL)       /*!< CP (Bitfield-Mask: 0xff)                              */
+/* =======================================================  PCI_RC_CP  ======================================================= */
+ #define R_PCIE0_PCI_RC_CP_CP_Pos                        (0UL)          /*!< CP (Bit 0)                                            */
+ #define R_PCIE0_PCI_RC_CP_CP_Msk                        (0xffUL)       /*!< CP (Bitfield-Mask: 0xff)                              */
+/* =====================================================  PCI_EP_INT_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_INT_F0_IL_Pos                    (0UL)          /*!< IL (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_INT_F0_IL_Msk                    (0xffUL)       /*!< IL (Bitfield-Mask: 0xff)                              */
+ #define R_PCIE0_PCI_EP_INT_F0_IP_Pos                    (8UL)          /*!< IP (Bit 8)                                            */
+ #define R_PCIE0_PCI_EP_INT_F0_IP_Msk                    (0xff00UL)     /*!< IP (Bitfield-Mask: 0xff)                              */
+/* =====================================================  PCI_EP_INT_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_INT_F1_IL_Pos                    (0UL)          /*!< IL (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_INT_F1_IL_Msk                    (0xffUL)       /*!< IL (Bitfield-Mask: 0xff)                              */
+ #define R_PCIE0_PCI_EP_INT_F1_IP_Pos                    (8UL)          /*!< IP (Bit 8)                                            */
+ #define R_PCIE0_PCI_EP_INT_F1_IP_Msk                    (0xff00UL)     /*!< IP (Bitfield-Mask: 0xff)                              */
+/* =====================================================  PCI_RC_BC_INT  ===================================================== */
+ #define R_PCIE0_PCI_RC_BC_INT_IL_Pos                    (0UL)          /*!< IL (Bit 0)                                            */
+ #define R_PCIE0_PCI_RC_BC_INT_IL_Msk                    (0xffUL)       /*!< IL (Bitfield-Mask: 0xff)                              */
+ #define R_PCIE0_PCI_RC_BC_INT_IP_Pos                    (8UL)          /*!< IP (Bit 8)                                            */
+ #define R_PCIE0_PCI_RC_BC_INT_IP_Msk                    (0xff00UL)     /*!< IP (Bitfield-Mask: 0xff)                              */
+ #define R_PCIE0_PCI_RC_BC_INT_PERE_Pos                  (16UL)         /*!< PERE (Bit 16)                                         */
+ #define R_PCIE0_PCI_RC_BC_INT_PERE_Msk                  (0x10000UL)    /*!< PERE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_BC_INT_SERRE_Pos                 (17UL)         /*!< SERRE (Bit 17)                                        */
+ #define R_PCIE0_PCI_RC_BC_INT_SERRE_Msk                 (0x20000UL)    /*!< SERRE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_BC_INT_ISAE_Pos                  (18UL)         /*!< ISAE (Bit 18)                                         */
+ #define R_PCIE0_PCI_RC_BC_INT_ISAE_Msk                  (0x40000UL)    /*!< ISAE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_BC_INT_VGAE_Pos                  (19UL)         /*!< VGAE (Bit 19)                                         */
+ #define R_PCIE0_PCI_RC_BC_INT_VGAE_Msk                  (0x80000UL)    /*!< VGAE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_BC_INT_VGA16D_Pos                (20UL)         /*!< VGA16D (Bit 20)                                       */
+ #define R_PCIE0_PCI_RC_BC_INT_VGA16D_Msk                (0x100000UL)   /*!< VGA16D (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_BC_INT_SBR_Pos                   (22UL)         /*!< SBR (Bit 22)                                          */
+ #define R_PCIE0_PCI_RC_BC_INT_SBR_Msk                   (0x400000UL)   /*!< SBR (Bitfield-Mask: 0x01)                             */
+/* =====================================================  PCI_EP_PMC_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_PMC_F0_CID_Pos                   (0UL)          /*!< CID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_PMC_F0_CID_Msk                   (0xffUL)       /*!< CID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_PMC_F0_NCP_Pos                   (8UL)          /*!< NCP (Bit 8)                                           */
+ #define R_PCIE0_PCI_EP_PMC_F0_NCP_Msk                   (0xff00UL)     /*!< NCP (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_PMC_F0_V_Pos                     (16UL)         /*!< V (Bit 16)                                            */
+ #define R_PCIE0_PCI_EP_PMC_F0_V_Msk                     (0x70000UL)    /*!< V (Bitfield-Mask: 0x07)                               */
+ #define R_PCIE0_PCI_EP_PMC_F0_IRORTD0_Pos               (20UL)         /*!< IRORTD0 (Bit 20)                                      */
+ #define R_PCIE0_PCI_EP_PMC_F0_IRORTD0_Msk               (0x100000UL)   /*!< IRORTD0 (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_PMC_F0_DSI_Pos                   (21UL)         /*!< DSI (Bit 21)                                          */
+ #define R_PCIE0_PCI_EP_PMC_F0_DSI_Msk                   (0x200000UL)   /*!< DSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_PMC_F0_AUXC_Pos                  (22UL)         /*!< AUXC (Bit 22)                                         */
+ #define R_PCIE0_PCI_EP_PMC_F0_AUXC_Msk                  (0x1c00000UL)  /*!< AUXC (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_PMC_F0_D1S_Pos                   (25UL)         /*!< D1S (Bit 25)                                          */
+ #define R_PCIE0_PCI_EP_PMC_F0_D1S_Msk                   (0x2000000UL)  /*!< D1S (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_PMC_F0_D2S_Pos                   (26UL)         /*!< D2S (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_PMC_F0_D2S_Msk                   (0x4000000UL)  /*!< D2S (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_PMC_F0_PMES_Pos                  (27UL)         /*!< PMES (Bit 27)                                         */
+ #define R_PCIE0_PCI_EP_PMC_F0_PMES_Msk                  (0xf8000000UL) /*!< PMES (Bitfield-Mask: 0x1f)                            */
+/* =====================================================  PCI_EP_PMC_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_PMC_F1_CID_Pos                   (0UL)          /*!< CID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_PMC_F1_CID_Msk                   (0xffUL)       /*!< CID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_PMC_F1_NCP_Pos                   (8UL)          /*!< NCP (Bit 8)                                           */
+ #define R_PCIE0_PCI_EP_PMC_F1_NCP_Msk                   (0xff00UL)     /*!< NCP (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_PMC_F1_V_Pos                     (16UL)         /*!< V (Bit 16)                                            */
+ #define R_PCIE0_PCI_EP_PMC_F1_V_Msk                     (0x70000UL)    /*!< V (Bitfield-Mask: 0x07)                               */
+ #define R_PCIE0_PCI_EP_PMC_F1_IRORTD0_Pos               (20UL)         /*!< IRORTD0 (Bit 20)                                      */
+ #define R_PCIE0_PCI_EP_PMC_F1_IRORTD0_Msk               (0x100000UL)   /*!< IRORTD0 (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_PMC_F1_DSI_Pos                   (21UL)         /*!< DSI (Bit 21)                                          */
+ #define R_PCIE0_PCI_EP_PMC_F1_DSI_Msk                   (0x200000UL)   /*!< DSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_PMC_F1_AUXC_Pos                  (22UL)         /*!< AUXC (Bit 22)                                         */
+ #define R_PCIE0_PCI_EP_PMC_F1_AUXC_Msk                  (0x1c00000UL)  /*!< AUXC (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_PMC_F1_D1S_Pos                   (25UL)         /*!< D1S (Bit 25)                                          */
+ #define R_PCIE0_PCI_EP_PMC_F1_D1S_Msk                   (0x2000000UL)  /*!< D1S (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_PMC_F1_D2S_Pos                   (26UL)         /*!< D2S (Bit 26)                                          */
+ #define R_PCIE0_PCI_EP_PMC_F1_D2S_Msk                   (0x4000000UL)  /*!< D2S (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_PMC_F1_PMES_Pos                  (27UL)         /*!< PMES (Bit 27)                                         */
+ #define R_PCIE0_PCI_EP_PMC_F1_PMES_Msk                  (0xf8000000UL) /*!< PMES (Bitfield-Mask: 0x1f)                            */
+/* ======================================================  PCI_RC_PMC  ======================================================= */
+ #define R_PCIE0_PCI_RC_PMC_CID_Pos                      (0UL)          /*!< CID (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_PMC_CID_Msk                      (0xffUL)       /*!< CID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_PMC_NCP_Pos                      (8UL)          /*!< NCP (Bit 8)                                           */
+ #define R_PCIE0_PCI_RC_PMC_NCP_Msk                      (0xff00UL)     /*!< NCP (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_PMC_V_Pos                        (16UL)         /*!< V (Bit 16)                                            */
+ #define R_PCIE0_PCI_RC_PMC_V_Msk                        (0x70000UL)    /*!< V (Bitfield-Mask: 0x07)                               */
+ #define R_PCIE0_PCI_RC_PMC_IRRD0_Pos                    (20UL)         /*!< IRRD0 (Bit 20)                                        */
+ #define R_PCIE0_PCI_RC_PMC_IRRD0_Msk                    (0x100000UL)   /*!< IRRD0 (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_PMC_DSI_Pos                      (21UL)         /*!< DSI (Bit 21)                                          */
+ #define R_PCIE0_PCI_RC_PMC_DSI_Msk                      (0x200000UL)   /*!< DSI (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_PMC_AUXC_Pos                     (22UL)         /*!< AUXC (Bit 22)                                         */
+ #define R_PCIE0_PCI_RC_PMC_AUXC_Msk                     (0x1c00000UL)  /*!< AUXC (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_RC_PMC_D1S_Pos                      (25UL)         /*!< D1S (Bit 25)                                          */
+ #define R_PCIE0_PCI_RC_PMC_D1S_Msk                      (0x2000000UL)  /*!< D1S (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_PMC_D2S_Pos                      (26UL)         /*!< D2S (Bit 26)                                          */
+ #define R_PCIE0_PCI_RC_PMC_D2S_Msk                      (0x4000000UL)  /*!< D2S (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_PMC_PMES_Pos                     (27UL)         /*!< PMES (Bit 27)                                         */
+ #define R_PCIE0_PCI_RC_PMC_PMES_Msk                     (0xf8000000UL) /*!< PMES (Bitfield-Mask: 0x1f)                            */
+/* ====================================================  PCI_EP_PMSC_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_PMSC_F0_PS_Pos                   (0UL)          /*!< PS (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_PMSC_F0_PS_Msk                   (0x3UL)        /*!< PS (Bitfield-Mask: 0x03)                              */
+ #define R_PCIE0_PCI_EP_PMSC_F0_NSR_Pos                  (3UL)          /*!< NSR (Bit 3)                                           */
+ #define R_PCIE0_PCI_EP_PMSC_F0_NSR_Msk                  (0x8UL)        /*!< NSR (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_PMSC_F0_PMEE_Pos                 (8UL)          /*!< PMEE (Bit 8)                                          */
+ #define R_PCIE0_PCI_EP_PMSC_F0_PMEE_Msk                 (0x100UL)      /*!< PMEE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_PMSC_F0_PMES_Pos                 (15UL)         /*!< PMES (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_PMSC_F0_PMES_Msk                 (0x8000UL)     /*!< PMES (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_EP_PMSC_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_PMSC_F1_PS_Pos                   (0UL)          /*!< PS (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_PMSC_F1_PS_Msk                   (0x3UL)        /*!< PS (Bitfield-Mask: 0x03)                              */
+ #define R_PCIE0_PCI_EP_PMSC_F1_NSR_Pos                  (3UL)          /*!< NSR (Bit 3)                                           */
+ #define R_PCIE0_PCI_EP_PMSC_F1_NSR_Msk                  (0x8UL)        /*!< NSR (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_PMSC_F1_PMEE_Pos                 (8UL)          /*!< PMEE (Bit 8)                                          */
+ #define R_PCIE0_PCI_EP_PMSC_F1_PMEE_Msk                 (0x100UL)      /*!< PMEE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_PMSC_F1_PMES_Pos                 (15UL)         /*!< PMES (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_PMSC_F1_PMES_Msk                 (0x8000UL)     /*!< PMES (Bitfield-Mask: 0x01)                            */
+/* ======================================================  PCI_RC_PMSC  ====================================================== */
+ #define R_PCIE0_PCI_RC_PMSC_PS_Pos                      (0UL)          /*!< PS (Bit 0)                                            */
+ #define R_PCIE0_PCI_RC_PMSC_PS_Msk                      (0x3UL)        /*!< PS (Bitfield-Mask: 0x03)                              */
+ #define R_PCIE0_PCI_RC_PMSC_NSR_Pos                     (3UL)          /*!< NSR (Bit 3)                                           */
+ #define R_PCIE0_PCI_RC_PMSC_NSR_Msk                     (0x8UL)        /*!< NSR (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_PMSC_PMEE_Pos                    (8UL)          /*!< PMEE (Bit 8)                                          */
+ #define R_PCIE0_PCI_RC_PMSC_PMEE_Msk                    (0x100UL)      /*!< PMEE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_PMSC_PMES_Pos                    (15UL)         /*!< PMES (Bit 15)                                         */
+ #define R_PCIE0_PCI_RC_PMSC_PMES_Msk                    (0x8000UL)     /*!< PMES (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_EP_PCIEC_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_CID_Pos                 (0UL)          /*!< CID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_CID_Msk                 (0xffUL)       /*!< CID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_NCP_Pos                 (8UL)          /*!< NCP (Bit 8)                                           */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_NCP_Msk                 (0xff00UL)     /*!< NCP (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_CV_Pos                  (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_CV_Msk                  (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_DPT_Pos                 (20UL)         /*!< DPT (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_DPT_Msk                 (0xf00000UL)   /*!< DPT (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_IMN_Pos                 (25UL)         /*!< IMN (Bit 25)                                          */
+ #define R_PCIE0_PCI_EP_PCIEC_F0_IMN_Msk                 (0x3e000000UL) /*!< IMN (Bitfield-Mask: 0x1f)                             */
+/* ====================================================  PCI_EP_PCIEC_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_CID_Pos                 (0UL)          /*!< CID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_CID_Msk                 (0xffUL)       /*!< CID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_NCP_Pos                 (8UL)          /*!< NCP (Bit 8)                                           */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_NCP_Msk                 (0xff00UL)     /*!< NCP (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_CV_Pos                  (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_CV_Msk                  (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_DPT_Pos                 (20UL)         /*!< DPT (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_DPT_Msk                 (0xf00000UL)   /*!< DPT (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_IMN_Pos                 (25UL)         /*!< IMN (Bit 25)                                          */
+ #define R_PCIE0_PCI_EP_PCIEC_F1_IMN_Msk                 (0x3e000000UL) /*!< IMN (Bitfield-Mask: 0x1f)                             */
+/* =====================================================  PCI_RC_PCIEC  ====================================================== */
+ #define R_PCIE0_PCI_RC_PCIEC_CID_Pos                    (0UL)          /*!< CID (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_PCIEC_CID_Msk                    (0xffUL)       /*!< CID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_PCIEC_NCP_Pos                    (8UL)          /*!< NCP (Bit 8)                                           */
+ #define R_PCIE0_PCI_RC_PCIEC_NCP_Msk                    (0xff00UL)     /*!< NCP (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_RC_PCIEC_CV_Pos                     (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_RC_PCIEC_CV_Msk                     (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_RC_PCIEC_DPT_Pos                    (20UL)         /*!< DPT (Bit 20)                                          */
+ #define R_PCIE0_PCI_RC_PCIEC_DPT_Msk                    (0xf00000UL)   /*!< DPT (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_RC_PCIEC_SI_Pos                     (24UL)         /*!< SI (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_PCIEC_SI_Msk                     (0x1000000UL)  /*!< SI (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_PCIEC_IMN_Pos                    (25UL)         /*!< IMN (Bit 25)                                          */
+ #define R_PCIE0_PCI_RC_PCIEC_IMN_Msk                    (0x3e000000UL) /*!< IMN (Bitfield-Mask: 0x1f)                             */
+/* ====================================================  PCI_EP_DEVC_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_DEVC_F0_MPSS_Pos                 (0UL)          /*!< MPSS (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_DEVC_F0_MPSS_Msk                 (0x7UL)        /*!< MPSS (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_DEVC_F0_ETFS_Pos                 (5UL)          /*!< ETFS (Bit 5)                                          */
+ #define R_PCIE0_PCI_EP_DEVC_F0_ETFS_Msk                 (0x20UL)       /*!< ETFS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVC_F0_EL0AL_Pos                (6UL)          /*!< EL0AL (Bit 6)                                         */
+ #define R_PCIE0_PCI_EP_DEVC_F0_EL0AL_Msk                (0x1c0UL)      /*!< EL0AL (Bitfield-Mask: 0x07)                           */
+ #define R_PCIE0_PCI_EP_DEVC_F0_EL1AL_Pos                (9UL)          /*!< EL1AL (Bit 9)                                         */
+ #define R_PCIE0_PCI_EP_DEVC_F0_EL1AL_Msk                (0xe00UL)      /*!< EL1AL (Bitfield-Mask: 0x07)                           */
+ #define R_PCIE0_PCI_EP_DEVC_F0_RBER_Pos                 (15UL)         /*!< RBER (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_DEVC_F0_RBER_Msk                 (0x8000UL)     /*!< RBER (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVC_F0_CSPLV_Pos                (18UL)         /*!< CSPLV (Bit 18)                                        */
+ #define R_PCIE0_PCI_EP_DEVC_F0_CSPLV_Msk                (0x3fc0000UL)  /*!< CSPLV (Bitfield-Mask: 0xff)                           */
+ #define R_PCIE0_PCI_EP_DEVC_F0_CSPLS_Pos                (26UL)         /*!< CSPLS (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_DEVC_F0_CSPLS_Msk                (0xc000000UL)  /*!< CSPLS (Bitfield-Mask: 0x03)                           */
+ #define R_PCIE0_PCI_EP_DEVC_F0_FLRC_Pos                 (28UL)         /*!< FLRC (Bit 28)                                         */
+ #define R_PCIE0_PCI_EP_DEVC_F0_FLRC_Msk                 (0x10000000UL) /*!< FLRC (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_EP_DEVC_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_DEVC_F1_MPSS_Pos                 (0UL)          /*!< MPSS (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_DEVC_F1_MPSS_Msk                 (0x7UL)        /*!< MPSS (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_DEVC_F1_ETFS_Pos                 (5UL)          /*!< ETFS (Bit 5)                                          */
+ #define R_PCIE0_PCI_EP_DEVC_F1_ETFS_Msk                 (0x20UL)       /*!< ETFS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVC_F1_EL0AL_Pos                (6UL)          /*!< EL0AL (Bit 6)                                         */
+ #define R_PCIE0_PCI_EP_DEVC_F1_EL0AL_Msk                (0x1c0UL)      /*!< EL0AL (Bitfield-Mask: 0x07)                           */
+ #define R_PCIE0_PCI_EP_DEVC_F1_EL1AL_Pos                (9UL)          /*!< EL1AL (Bit 9)                                         */
+ #define R_PCIE0_PCI_EP_DEVC_F1_EL1AL_Msk                (0xe00UL)      /*!< EL1AL (Bitfield-Mask: 0x07)                           */
+ #define R_PCIE0_PCI_EP_DEVC_F1_RBER_Pos                 (15UL)         /*!< RBER (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_DEVC_F1_RBER_Msk                 (0x8000UL)     /*!< RBER (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVC_F1_CSPLV_Pos                (18UL)         /*!< CSPLV (Bit 18)                                        */
+ #define R_PCIE0_PCI_EP_DEVC_F1_CSPLV_Msk                (0x3fc0000UL)  /*!< CSPLV (Bitfield-Mask: 0xff)                           */
+ #define R_PCIE0_PCI_EP_DEVC_F1_CSPLS_Pos                (26UL)         /*!< CSPLS (Bit 26)                                        */
+ #define R_PCIE0_PCI_EP_DEVC_F1_CSPLS_Msk                (0xc000000UL)  /*!< CSPLS (Bitfield-Mask: 0x03)                           */
+ #define R_PCIE0_PCI_EP_DEVC_F1_FLRC_Pos                 (28UL)         /*!< FLRC (Bit 28)                                         */
+ #define R_PCIE0_PCI_EP_DEVC_F1_FLRC_Msk                 (0x10000000UL) /*!< FLRC (Bitfield-Mask: 0x01)                            */
+/* ======================================================  PCI_RC_DEVC  ====================================================== */
+ #define R_PCIE0_PCI_RC_DEVC_MPSS_Pos                    (0UL)          /*!< MPSS (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_DEVC_MPSS_Msk                    (0x7UL)        /*!< MPSS (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_RC_DEVC_RBER_Pos                    (15UL)         /*!< RBER (Bit 15)                                         */
+ #define R_PCIE0_PCI_RC_DEVC_RBER_Msk                    (0x8000UL)     /*!< RBER (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_EP_DEVCS_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_CERE_Pos                (0UL)          /*!< CERE (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_CERE_Msk                (0x1UL)        /*!< CERE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_NFERE_Pos               (1UL)          /*!< NFERE (Bit 1)                                         */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_NFERE_Msk               (0x2UL)        /*!< NFERE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_FERE_Pos                (2UL)          /*!< FERE (Bit 2)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_FERE_Msk                (0x4UL)        /*!< FERE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_URRE_Pos                (3UL)          /*!< URRE (Bit 3)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_URRE_Msk                (0x8UL)        /*!< URRE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_ERO_Pos                 (4UL)          /*!< ERO (Bit 4)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_ERO_Msk                 (0x10UL)       /*!< ERO (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_MPS_Pos                 (5UL)          /*!< MPS (Bit 5)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_MPS_Msk                 (0xe0UL)       /*!< MPS (Bitfield-Mask: 0x07)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_MRRS_Pos                (12UL)         /*!< MRRS (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_MRRS_Msk                (0x7000UL)     /*!< MRRS (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_IFLR_Pos                (15UL)         /*!< IFLR (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_IFLR_Msk                (0x8000UL)     /*!< IFLR (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_CED_Pos                 (16UL)         /*!< CED (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_CED_Msk                 (0x10000UL)    /*!< CED (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_NFED_Pos                (17UL)         /*!< NFED (Bit 17)                                         */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_NFED_Msk                (0x20000UL)    /*!< NFED (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_FED_Pos                 (18UL)         /*!< FED (Bit 18)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_FED_Msk                 (0x40000UL)    /*!< FED (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_URD_Pos                 (19UL)         /*!< URD (Bit 19)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_URD_Msk                 (0x80000UL)    /*!< URD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_TP_Pos                  (21UL)         /*!< TP (Bit 21)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS_F0_TP_Msk                  (0x200000UL)   /*!< TP (Bitfield-Mask: 0x01)                              */
+/* ====================================================  PCI_EP_DEVCS_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_CERE_Pos                (0UL)          /*!< CERE (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_CERE_Msk                (0x1UL)        /*!< CERE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_NFERE_Pos               (1UL)          /*!< NFERE (Bit 1)                                         */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_NFERE_Msk               (0x2UL)        /*!< NFERE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_FERE_Pos                (2UL)          /*!< FERE (Bit 2)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_FERE_Msk                (0x4UL)        /*!< FERE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_URRE_Pos                (3UL)          /*!< URRE (Bit 3)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_URRE_Msk                (0x8UL)        /*!< URRE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_ERO_Pos                 (4UL)          /*!< ERO (Bit 4)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_ERO_Msk                 (0x10UL)       /*!< ERO (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_MPS_Pos                 (5UL)          /*!< MPS (Bit 5)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_MPS_Msk                 (0xe0UL)       /*!< MPS (Bitfield-Mask: 0x07)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_MRRS_Pos                (12UL)         /*!< MRRS (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_MRRS_Msk                (0x7000UL)     /*!< MRRS (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_IFLR_Pos                (15UL)         /*!< IFLR (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_IFLR_Msk                (0x8000UL)     /*!< IFLR (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_CED_Pos                 (16UL)         /*!< CED (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_CED_Msk                 (0x10000UL)    /*!< CED (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_NFED_Pos                (17UL)         /*!< NFED (Bit 17)                                         */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_NFED_Msk                (0x20000UL)    /*!< NFED (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_FED_Pos                 (18UL)         /*!< FED (Bit 18)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_FED_Msk                 (0x40000UL)    /*!< FED (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_URD_Pos                 (19UL)         /*!< URD (Bit 19)                                          */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_URD_Msk                 (0x80000UL)    /*!< URD (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_TP_Pos                  (21UL)         /*!< TP (Bit 21)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS_F1_TP_Msk                  (0x200000UL)   /*!< TP (Bitfield-Mask: 0x01)                              */
+/* =====================================================  PCI_RC_DEVCS  ====================================================== */
+ #define R_PCIE0_PCI_RC_DEVCS_CERE_Pos                   (0UL)          /*!< CERE (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_DEVCS_CERE_Msk                   (0x1UL)        /*!< CERE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_DEVCS_NFERE_Pos                  (1UL)          /*!< NFERE (Bit 1)                                         */
+ #define R_PCIE0_PCI_RC_DEVCS_NFERE_Msk                  (0x2UL)        /*!< NFERE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_DEVCS_FERE_Pos                   (2UL)          /*!< FERE (Bit 2)                                          */
+ #define R_PCIE0_PCI_RC_DEVCS_FERE_Msk                   (0x4UL)        /*!< FERE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_DEVCS_URRE_Pos                   (3UL)          /*!< URRE (Bit 3)                                          */
+ #define R_PCIE0_PCI_RC_DEVCS_URRE_Msk                   (0x8UL)        /*!< URRE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_DEVCS_ERO_Pos                    (4UL)          /*!< ERO (Bit 4)                                           */
+ #define R_PCIE0_PCI_RC_DEVCS_ERO_Msk                    (0x10UL)       /*!< ERO (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DEVCS_MPS_Pos                    (5UL)          /*!< MPS (Bit 5)                                           */
+ #define R_PCIE0_PCI_RC_DEVCS_MPS_Msk                    (0xe0UL)       /*!< MPS (Bitfield-Mask: 0x07)                             */
+ #define R_PCIE0_PCI_RC_DEVCS_MRRS_Pos                   (12UL)         /*!< MRRS (Bit 12)                                         */
+ #define R_PCIE0_PCI_RC_DEVCS_MRRS_Msk                   (0x7000UL)     /*!< MRRS (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_RC_DEVCS_CED_Pos                    (16UL)         /*!< CED (Bit 16)                                          */
+ #define R_PCIE0_PCI_RC_DEVCS_CED_Msk                    (0x10000UL)    /*!< CED (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DEVCS_NFED_Pos                   (17UL)         /*!< NFED (Bit 17)                                         */
+ #define R_PCIE0_PCI_RC_DEVCS_NFED_Msk                   (0x20000UL)    /*!< NFED (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_DEVCS_FED_Pos                    (18UL)         /*!< FED (Bit 18)                                          */
+ #define R_PCIE0_PCI_RC_DEVCS_FED_Msk                    (0x40000UL)    /*!< FED (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_DEVCS_URD_Pos                    (19UL)         /*!< URD (Bit 19)                                          */
+ #define R_PCIE0_PCI_RC_DEVCS_URD_Msk                    (0x80000UL)    /*!< URD (Bitfield-Mask: 0x01)                             */
+/* ====================================================  PCI_EP_LINKC_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_LINKC_F0_MLS_Pos                 (0UL)          /*!< MLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_LINKC_F0_MLS_Msk                 (0xfUL)        /*!< MLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_LINKC_F0_MLW_Pos                 (4UL)          /*!< MLW (Bit 4)                                           */
+ #define R_PCIE0_PCI_EP_LINKC_F0_MLW_Msk                 (0x3f0UL)      /*!< MLW (Bitfield-Mask: 0x3f)                             */
+ #define R_PCIE0_PCI_EP_LINKC_F0_ASPMS_Pos               (10UL)         /*!< ASPMS (Bit 10)                                        */
+ #define R_PCIE0_PCI_EP_LINKC_F0_ASPMS_Msk               (0xc00UL)      /*!< ASPMS (Bitfield-Mask: 0x03)                           */
+ #define R_PCIE0_PCI_EP_LINKC_F0_L0EL_Pos                (12UL)         /*!< L0EL (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_LINKC_F0_L0EL_Msk                (0x7000UL)     /*!< L0EL (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_LINKC_F0_L1EL_Pos                (15UL)         /*!< L1EL (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_LINKC_F0_L1EL_Msk                (0x38000UL)    /*!< L1EL (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_LINKC_F0_CPM_Pos                 (18UL)         /*!< CPM (Bit 18)                                          */
+ #define R_PCIE0_PCI_EP_LINKC_F0_CPM_Msk                 (0x40000UL)    /*!< CPM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKC_F0_ASPMOC_Pos              (22UL)         /*!< ASPMOC (Bit 22)                                       */
+ #define R_PCIE0_PCI_EP_LINKC_F0_ASPMOC_Msk              (0x400000UL)   /*!< ASPMOC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_LINKC_F0_PN_Pos                  (24UL)         /*!< PN (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_LINKC_F0_PN_Msk                  (0xff000000UL) /*!< PN (Bitfield-Mask: 0xff)                              */
+/* ====================================================  PCI_EP_LINKC_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_LINKC_F1_MLS_Pos                 (0UL)          /*!< MLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_LINKC_F1_MLS_Msk                 (0xfUL)        /*!< MLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_LINKC_F1_MLW_Pos                 (4UL)          /*!< MLW (Bit 4)                                           */
+ #define R_PCIE0_PCI_EP_LINKC_F1_MLW_Msk                 (0x3f0UL)      /*!< MLW (Bitfield-Mask: 0x3f)                             */
+ #define R_PCIE0_PCI_EP_LINKC_F1_ASPMS_Pos               (10UL)         /*!< ASPMS (Bit 10)                                        */
+ #define R_PCIE0_PCI_EP_LINKC_F1_ASPMS_Msk               (0xc00UL)      /*!< ASPMS (Bitfield-Mask: 0x03)                           */
+ #define R_PCIE0_PCI_EP_LINKC_F1_L0EL_Pos                (12UL)         /*!< L0EL (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_LINKC_F1_L0EL_Msk                (0x7000UL)     /*!< L0EL (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_LINKC_F1_L1EL_Pos                (15UL)         /*!< L1EL (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_LINKC_F1_L1EL_Msk                (0x38000UL)    /*!< L1EL (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_EP_LINKC_F1_CPM_Pos                 (18UL)         /*!< CPM (Bit 18)                                          */
+ #define R_PCIE0_PCI_EP_LINKC_F1_CPM_Msk                 (0x40000UL)    /*!< CPM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKC_F1_ASPMOC_Pos              (22UL)         /*!< ASPMOC (Bit 22)                                       */
+ #define R_PCIE0_PCI_EP_LINKC_F1_ASPMOC_Msk              (0x400000UL)   /*!< ASPMOC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_LINKC_F1_PN_Pos                  (24UL)         /*!< PN (Bit 24)                                           */
+ #define R_PCIE0_PCI_EP_LINKC_F1_PN_Msk                  (0xff000000UL) /*!< PN (Bitfield-Mask: 0xff)                              */
+/* =====================================================  PCI_RC_LINKC  ====================================================== */
+ #define R_PCIE0_PCI_RC_LINKC_SLS_Pos                    (0UL)          /*!< SLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_LINKC_SLS_Msk                    (0xfUL)        /*!< SLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_RC_LINKC_MLW_Pos                    (4UL)          /*!< MLW (Bit 4)                                           */
+ #define R_PCIE0_PCI_RC_LINKC_MLW_Msk                    (0x3f0UL)      /*!< MLW (Bitfield-Mask: 0x3f)                             */
+ #define R_PCIE0_PCI_RC_LINKC_ASPMS_Pos                  (10UL)         /*!< ASPMS (Bit 10)                                        */
+ #define R_PCIE0_PCI_RC_LINKC_ASPMS_Msk                  (0xc00UL)      /*!< ASPMS (Bitfield-Mask: 0x03)                           */
+ #define R_PCIE0_PCI_RC_LINKC_L0EL_Pos                   (12UL)         /*!< L0EL (Bit 12)                                         */
+ #define R_PCIE0_PCI_RC_LINKC_L0EL_Msk                   (0x7000UL)     /*!< L0EL (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_RC_LINKC_L1EL_Pos                   (15UL)         /*!< L1EL (Bit 15)                                         */
+ #define R_PCIE0_PCI_RC_LINKC_L1EL_Msk                   (0x38000UL)    /*!< L1EL (Bitfield-Mask: 0x07)                            */
+ #define R_PCIE0_PCI_RC_LINKC_DLLLARC_Pos                (20UL)         /*!< DLLLARC (Bit 20)                                      */
+ #define R_PCIE0_PCI_RC_LINKC_DLLLARC_Msk                (0x100000UL)   /*!< DLLLARC (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_LINKC_LBNC_Pos                   (21UL)         /*!< LBNC (Bit 21)                                         */
+ #define R_PCIE0_PCI_RC_LINKC_LBNC_Msk                   (0x200000UL)   /*!< LBNC (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_LINKC_ASPMOC_Pos                 (22UL)         /*!< ASPMOC (Bit 22)                                       */
+ #define R_PCIE0_PCI_RC_LINKC_ASPMOC_Msk                 (0x400000UL)   /*!< ASPMOC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_LINKC_PN_Pos                     (24UL)         /*!< PN (Bit 24)                                           */
+ #define R_PCIE0_PCI_RC_LINKC_PN_Msk                     (0xff000000UL) /*!< PN (Bitfield-Mask: 0xff)                              */
+/* ===================================================  PCI_EP_LINKCS_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_ASPMC_Pos              (0UL)          /*!< ASPMC (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_ASPMC_Msk              (0x3UL)        /*!< ASPMC (Bitfield-Mask: 0x03)                           */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_RCB_Pos                (3UL)          /*!< RCB (Bit 3)                                           */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_RCB_Msk                (0x8UL)        /*!< RCB (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_CCC_Pos                (6UL)          /*!< CCC (Bit 6)                                           */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_CCC_Msk                (0x40UL)       /*!< CCC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_ES_Pos                 (7UL)          /*!< ES (Bit 7)                                            */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_ES_Msk                 (0x80UL)       /*!< ES (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_ECPM_Pos               (8UL)          /*!< ECPM (Bit 8)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_ECPM_Msk               (0x100UL)      /*!< ECPM (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_HAWD_Pos               (9UL)          /*!< HAWD (Bit 9)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_HAWD_Msk               (0x200UL)      /*!< HAWD (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_CLS_Pos                (16UL)         /*!< CLS (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_CLS_Msk                (0xf0000UL)    /*!< CLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_NLW_Pos                (20UL)         /*!< NLW (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_NLW_Msk                (0x3f00000UL)  /*!< NLW (Bitfield-Mask: 0x3f)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_SCC_Pos                (28UL)         /*!< SCC (Bit 28)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_SCC_Msk                (0x10000000UL) /*!< SCC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_DLLLA_Pos              (29UL)         /*!< DLLLA (Bit 29)                                        */
+ #define R_PCIE0_PCI_EP_LINKCS_F0_DLLLA_Msk              (0x20000000UL) /*!< DLLLA (Bitfield-Mask: 0x01)                           */
+/* ===================================================  PCI_EP_LINKCS_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_ASPMC_Pos              (0UL)          /*!< ASPMC (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_ASPMC_Msk              (0x3UL)        /*!< ASPMC (Bitfield-Mask: 0x03)                           */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_RCB_Pos                (3UL)          /*!< RCB (Bit 3)                                           */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_RCB_Msk                (0x8UL)        /*!< RCB (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_CCC_Pos                (6UL)          /*!< CCC (Bit 6)                                           */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_CCC_Msk                (0x40UL)       /*!< CCC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_ES_Pos                 (7UL)          /*!< ES (Bit 7)                                            */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_ES_Msk                 (0x80UL)       /*!< ES (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_ECPM_Pos               (8UL)          /*!< ECPM (Bit 8)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_ECPM_Msk               (0x100UL)      /*!< ECPM (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_HAWD_Pos               (9UL)          /*!< HAWD (Bit 9)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_HAWD_Msk               (0x200UL)      /*!< HAWD (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_CLS_Pos                (16UL)         /*!< CLS (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_CLS_Msk                (0xf0000UL)    /*!< CLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_NLW_Pos                (20UL)         /*!< NLW (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_NLW_Msk                (0x3f00000UL)  /*!< NLW (Bitfield-Mask: 0x3f)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_SCC_Pos                (28UL)         /*!< SCC (Bit 28)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_SCC_Msk                (0x10000000UL) /*!< SCC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_DLLLA_Pos              (29UL)         /*!< DLLLA (Bit 29)                                        */
+ #define R_PCIE0_PCI_EP_LINKCS_F1_DLLLA_Msk              (0x20000000UL) /*!< DLLLA (Bitfield-Mask: 0x01)                           */
+/* =====================================================  PCI_RC_LINKCS  ===================================================== */
+ #define R_PCIE0_PCI_RC_LINKCS_ASPMC_Pos                 (0UL)          /*!< ASPMC (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_LINKCS_ASPMC_Msk                 (0x3UL)        /*!< ASPMC (Bitfield-Mask: 0x03)                           */
+ #define R_PCIE0_PCI_RC_LINKCS_RCB_Pos                   (3UL)          /*!< RCB (Bit 3)                                           */
+ #define R_PCIE0_PCI_RC_LINKCS_RCB_Msk                   (0x8UL)        /*!< RCB (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_LINKCS_LD_Pos                    (4UL)          /*!< LD (Bit 4)                                            */
+ #define R_PCIE0_PCI_RC_LINKCS_LD_Msk                    (0x10UL)       /*!< LD (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_LINKCS_RL_Pos                    (5UL)          /*!< RL (Bit 5)                                            */
+ #define R_PCIE0_PCI_RC_LINKCS_RL_Msk                    (0x20UL)       /*!< RL (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_LINKCS_CCC_Pos                   (6UL)          /*!< CCC (Bit 6)                                           */
+ #define R_PCIE0_PCI_RC_LINKCS_CCC_Msk                   (0x40UL)       /*!< CCC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_LINKCS_ES_Pos                    (7UL)          /*!< ES (Bit 7)                                            */
+ #define R_PCIE0_PCI_RC_LINKCS_ES_Msk                    (0x80UL)       /*!< ES (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_LINKCS_HAWD_Pos                  (9UL)          /*!< HAWD (Bit 9)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS_HAWD_Msk                  (0x200UL)      /*!< HAWD (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_LINKCS_LBMIE_Pos                 (10UL)         /*!< LBMIE (Bit 10)                                        */
+ #define R_PCIE0_PCI_RC_LINKCS_LBMIE_Msk                 (0x400UL)      /*!< LBMIE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_LINKCS_LABIE_Pos                 (11UL)         /*!< LABIE (Bit 11)                                        */
+ #define R_PCIE0_PCI_RC_LINKCS_LABIE_Msk                 (0x800UL)      /*!< LABIE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_LINKCS_CLS_Pos                   (16UL)         /*!< CLS (Bit 16)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS_CLS_Msk                   (0xf0000UL)    /*!< CLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_RC_LINKCS_NLW_Pos                   (20UL)         /*!< NLW (Bit 20)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS_NLW_Msk                   (0x3f00000UL)  /*!< NLW (Bitfield-Mask: 0x3f)                             */
+ #define R_PCIE0_PCI_RC_LINKCS_LT_Pos                    (27UL)         /*!< LT (Bit 27)                                           */
+ #define R_PCIE0_PCI_RC_LINKCS_LT_Msk                    (0x8000000UL)  /*!< LT (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_LINKCS_SCC_Pos                   (28UL)         /*!< SCC (Bit 28)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS_SCC_Msk                   (0x10000000UL) /*!< SCC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_LINKCS_DLLLA_Pos                 (29UL)         /*!< DLLLA (Bit 29)                                        */
+ #define R_PCIE0_PCI_RC_LINKCS_DLLLA_Msk                 (0x20000000UL) /*!< DLLLA (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_LINKCS_LBMS_Pos                  (30UL)         /*!< LBMS (Bit 30)                                         */
+ #define R_PCIE0_PCI_RC_LINKCS_LBMS_Msk                  (0x40000000UL) /*!< LBMS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_LINKCS_LABS_Pos                  (31UL)         /*!< LABS (Bit 31)                                         */
+ #define R_PCIE0_PCI_RC_LINKCS_LABS_Msk                  (0x80000000UL) /*!< LABS (Bitfield-Mask: 0x01)                            */
+/* =====================================================  PCI_RC_SLOTC  ====================================================== */
+ #define R_PCIE0_PCI_RC_SLOTC_ABP_Pos                    (0UL)          /*!< ABP (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_SLOTC_ABP_Msk                    (0x1UL)        /*!< ABP (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_SLOTC_PCP_Pos                    (1UL)          /*!< PCP (Bit 1)                                           */
+ #define R_PCIE0_PCI_RC_SLOTC_PCP_Msk                    (0x2UL)        /*!< PCP (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_SLOTC_MRLSP_Pos                  (2UL)          /*!< MRLSP (Bit 2)                                         */
+ #define R_PCIE0_PCI_RC_SLOTC_MRLSP_Msk                  (0x4UL)        /*!< MRLSP (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_SLOTC_AIP_Pos                    (3UL)          /*!< AIP (Bit 3)                                           */
+ #define R_PCIE0_PCI_RC_SLOTC_AIP_Msk                    (0x8UL)        /*!< AIP (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_SLOTC_PIP_Pos                    (4UL)          /*!< PIP (Bit 4)                                           */
+ #define R_PCIE0_PCI_RC_SLOTC_PIP_Msk                    (0x10UL)       /*!< PIP (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_SLOTC_HPS_Pos                    (5UL)          /*!< HPS (Bit 5)                                           */
+ #define R_PCIE0_PCI_RC_SLOTC_HPS_Msk                    (0x20UL)       /*!< HPS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_SLOTC_HPC_Pos                    (6UL)          /*!< HPC (Bit 6)                                           */
+ #define R_PCIE0_PCI_RC_SLOTC_HPC_Msk                    (0x40UL)       /*!< HPC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_SLOTC_SPLV_Pos                   (7UL)          /*!< SPLV (Bit 7)                                          */
+ #define R_PCIE0_PCI_RC_SLOTC_SPLV_Msk                   (0x7f80UL)     /*!< SPLV (Bitfield-Mask: 0xff)                            */
+ #define R_PCIE0_PCI_RC_SLOTC_SPLS_Pos                   (15UL)         /*!< SPLS (Bit 15)                                         */
+ #define R_PCIE0_PCI_RC_SLOTC_SPLS_Msk                   (0x18000UL)    /*!< SPLS (Bitfield-Mask: 0x03)                            */
+ #define R_PCIE0_PCI_RC_SLOTC_EIP_Pos                    (17UL)         /*!< EIP (Bit 17)                                          */
+ #define R_PCIE0_PCI_RC_SLOTC_EIP_Msk                    (0x20000UL)    /*!< EIP (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_SLOTC_NCCS_Pos                   (18UL)         /*!< NCCS (Bit 18)                                         */
+ #define R_PCIE0_PCI_RC_SLOTC_NCCS_Msk                   (0x40000UL)    /*!< NCCS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_SLOTC_PSN_Pos                    (19UL)         /*!< PSN (Bit 19)                                          */
+ #define R_PCIE0_PCI_RC_SLOTC_PSN_Msk                    (0xfff80000UL) /*!< PSN (Bitfield-Mask: 0x1fff)                           */
+/* =====================================================  PCI_RC_SLOTCS  ===================================================== */
+/* =====================================================  PCI_RC_ROOTCC  ===================================================== */
+ #define R_PCIE0_PCI_RC_ROOTCC_SECEE_Pos                 (0UL)          /*!< SECEE (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_ROOTCC_SECEE_Msk                 (0x1UL)        /*!< SECEE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_ROOTCC_SENFEE_Pos                (1UL)          /*!< SENFEE (Bit 1)                                        */
+ #define R_PCIE0_PCI_RC_ROOTCC_SENFEE_Msk                (0x2UL)        /*!< SENFEE (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_ROOTCC_SEFEE_Pos                 (2UL)          /*!< SEFEE (Bit 2)                                         */
+ #define R_PCIE0_PCI_RC_ROOTCC_SEFEE_Msk                 (0x4UL)        /*!< SEFEE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_ROOTCC_PMEIE_Pos                 (3UL)          /*!< PMEIE (Bit 3)                                         */
+ #define R_PCIE0_PCI_RC_ROOTCC_PMEIE_Msk                 (0x8UL)        /*!< PMEIE (Bitfield-Mask: 0x01)                           */
+/* =====================================================  PCI_RC_ROOTS  ====================================================== */
+ #define R_PCIE0_PCI_RC_ROOTS_PMERID_Pos                 (0UL)          /*!< PMERID (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_ROOTS_PMERID_Msk                 (0xffffUL)     /*!< PMERID (Bitfield-Mask: 0xffff)                        */
+ #define R_PCIE0_PCI_RC_ROOTS_PMES_Pos                   (16UL)         /*!< PMES (Bit 16)                                         */
+ #define R_PCIE0_PCI_RC_ROOTS_PMES_Msk                   (0x10000UL)    /*!< PMES (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_ROOTS_PMEP_Pos                   (17UL)         /*!< PMEP (Bit 17)                                         */
+ #define R_PCIE0_PCI_RC_ROOTS_PMEP_Msk                   (0x20000UL)    /*!< PMEP (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_EP_DEVC2_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DEVC2_F0_CTRS_Pos                (0UL)          /*!< CTRS (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_DEVC2_F0_CTRS_Msk                (0xfUL)        /*!< CTRS (Bitfield-Mask: 0x0f)                            */
+ #define R_PCIE0_PCI_EP_DEVC2_F0_CTDS_Pos                (4UL)          /*!< CTDS (Bit 4)                                          */
+ #define R_PCIE0_PCI_EP_DEVC2_F0_CTDS_Msk                (0x10UL)       /*!< CTDS (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_EP_DEVC2_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DEVC2_F1_CTRS_Pos                (0UL)          /*!< CTRS (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_DEVC2_F1_CTRS_Msk                (0xfUL)        /*!< CTRS (Bitfield-Mask: 0x0f)                            */
+ #define R_PCIE0_PCI_EP_DEVC2_F1_CTDS_Pos                (4UL)          /*!< CTDS (Bit 4)                                          */
+ #define R_PCIE0_PCI_EP_DEVC2_F1_CTDS_Msk                (0x10UL)       /*!< CTDS (Bitfield-Mask: 0x01)                            */
+/* =====================================================  PCI_RC_DEVC2  ====================================================== */
+ #define R_PCIE0_PCI_RC_DEVC2_CTRS_Pos                   (0UL)          /*!< CTRS (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_DEVC2_CTRS_Msk                   (0xfUL)        /*!< CTRS (Bitfield-Mask: 0x0f)                            */
+ #define R_PCIE0_PCI_RC_DEVC2_CTDS_Pos                   (4UL)          /*!< CTDS (Bit 4)                                          */
+ #define R_PCIE0_PCI_RC_DEVC2_CTDS_Msk                   (0x10UL)       /*!< CTDS (Bitfield-Mask: 0x01)                            */
+/* ===================================================  PCI_EP_DEVCS2_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_DEVCS2_F0_CTV_Pos                (0UL)          /*!< CTV (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS2_F0_CTV_Msk                (0xfUL)        /*!< CTV (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_DEVCS2_F0_CTD_Pos                (4UL)          /*!< CTD (Bit 4)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS2_F0_CTD_Msk                (0x10UL)       /*!< CTD (Bitfield-Mask: 0x01)                             */
+/* ===================================================  PCI_EP_DEVCS2_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_DEVCS2_F1_CTV_Pos                (0UL)          /*!< CTV (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS2_F1_CTV_Msk                (0xfUL)        /*!< CTV (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_DEVCS2_F1_CTD_Pos                (4UL)          /*!< CTD (Bit 4)                                           */
+ #define R_PCIE0_PCI_EP_DEVCS2_F1_CTD_Msk                (0x10UL)       /*!< CTD (Bitfield-Mask: 0x01)                             */
+/* =====================================================  PCI_RC_DEVCS2  ===================================================== */
+ #define R_PCIE0_PCI_RC_DEVCS2_CTV_Pos                   (0UL)          /*!< CTV (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_DEVCS2_CTV_Msk                   (0xfUL)        /*!< CTV (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_RC_DEVCS2_CTD_Pos                   (4UL)          /*!< CTD (Bit 4)                                           */
+ #define R_PCIE0_PCI_RC_DEVCS2_CTD_Msk                   (0x10UL)       /*!< CTD (Bitfield-Mask: 0x01)                             */
+/* ===================================================  PCI_EP_LINKC2_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_LINKC2_F0_SLSV_Pos               (1UL)          /*!< SLSV (Bit 1)                                          */
+ #define R_PCIE0_PCI_EP_LINKC2_F0_SLSV_Msk               (0xfeUL)       /*!< SLSV (Bitfield-Mask: 0x7f)                            */
+/* ===================================================  PCI_EP_LINKC2_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_LINKC2_F1_SLSV_Pos               (1UL)          /*!< SLSV (Bit 1)                                          */
+ #define R_PCIE0_PCI_EP_LINKC2_F1_SLSV_Msk               (0xfeUL)       /*!< SLSV (Bitfield-Mask: 0x7f)                            */
+/* =====================================================  PCI_RC_LINKC2  ===================================================== */
+ #define R_PCIE0_PCI_RC_LINKC2_SLSV_Pos                  (1UL)          /*!< SLSV (Bit 1)                                          */
+ #define R_PCIE0_PCI_RC_LINKC2_SLSV_Msk                  (0xfeUL)       /*!< SLSV (Bitfield-Mask: 0x7f)                            */
+/* ===================================================  PCI_EP_LINKCS2_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_TLS_Pos               (0UL)          /*!< TLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_TLS_Msk               (0xfUL)        /*!< TLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_ETC_Pos               (4UL)          /*!< ETC (Bit 4)                                           */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_ETC_Msk               (0x10UL)       /*!< ETC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_HASD_Pos              (5UL)          /*!< HASD (Bit 5)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_HASD_Msk              (0x20UL)       /*!< HASD (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_TM_Pos                (7UL)          /*!< TM (Bit 7)                                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_TM_Msk                (0x380UL)      /*!< TM (Bitfield-Mask: 0x07)                              */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EMC_Pos               (10UL)         /*!< EMC (Bit 10)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EMC_Msk               (0x400UL)      /*!< EMC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_CSOS_Pos              (11UL)         /*!< CSOS (Bit 11)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_CSOS_Msk              (0x800UL)      /*!< CSOS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_CPD_Pos               (12UL)         /*!< CPD (Bit 12)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_CPD_Msk               (0xf000UL)     /*!< CPD (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_CDL_Pos               (16UL)         /*!< CDL (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_CDL_Msk               (0x10000UL)    /*!< CDL (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EQC_Pos               (17UL)         /*!< EQC (Bit 17)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EQC_Msk               (0x20000UL)    /*!< EQC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EP1S_Pos              (18UL)         /*!< EP1S (Bit 18)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EP1S_Msk              (0x40000UL)    /*!< EP1S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EP2S_Pos              (19UL)         /*!< EP2S (Bit 19)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EP2S_Msk              (0x80000UL)    /*!< EP2S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EP3S_Pos              (20UL)         /*!< EP3S (Bit 20)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_EP3S_Msk              (0x100000UL)   /*!< EP3S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_LER_Pos               (21UL)         /*!< LER (Bit 21)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F0_LER_Msk               (0x200000UL)   /*!< LER (Bitfield-Mask: 0x01)                             */
+/* ===================================================  PCI_EP_LINKCS2_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_TLS_Pos               (0UL)          /*!< TLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_TLS_Msk               (0xfUL)        /*!< TLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_ETC_Pos               (4UL)          /*!< ETC (Bit 4)                                           */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_ETC_Msk               (0x10UL)       /*!< ETC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_HASD_Pos              (5UL)          /*!< HASD (Bit 5)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_HASD_Msk              (0x20UL)       /*!< HASD (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_TM_Pos                (7UL)          /*!< TM (Bit 7)                                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_TM_Msk                (0x380UL)      /*!< TM (Bitfield-Mask: 0x07)                              */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EMC_Pos               (10UL)         /*!< EMC (Bit 10)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EMC_Msk               (0x400UL)      /*!< EMC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_CSOS_Pos              (11UL)         /*!< CSOS (Bit 11)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_CSOS_Msk              (0x800UL)      /*!< CSOS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_CPD_Pos               (12UL)         /*!< CPD (Bit 12)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_CPD_Msk               (0xf000UL)     /*!< CPD (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_CDL_Pos               (16UL)         /*!< CDL (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_CDL_Msk               (0x10000UL)    /*!< CDL (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EQC_Pos               (17UL)         /*!< EQC (Bit 17)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EQC_Msk               (0x20000UL)    /*!< EQC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EP1S_Pos              (18UL)         /*!< EP1S (Bit 18)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EP1S_Msk              (0x40000UL)    /*!< EP1S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EP2S_Pos              (19UL)         /*!< EP2S (Bit 19)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EP2S_Msk              (0x80000UL)    /*!< EP2S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EP3S_Pos              (20UL)         /*!< EP3S (Bit 20)                                         */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_EP3S_Msk              (0x100000UL)   /*!< EP3S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_LER_Pos               (21UL)         /*!< LER (Bit 21)                                          */
+ #define R_PCIE0_PCI_EP_LINKCS2_F1_LER_Msk               (0x200000UL)   /*!< LER (Bitfield-Mask: 0x01)                             */
+/* ====================================================  PCI_RC_LINKCS2  ===================================================== */
+ #define R_PCIE0_PCI_RC_LINKCS2_TLS_Pos                  (0UL)          /*!< TLS (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_LINKCS2_TLS_Msk                  (0xfUL)        /*!< TLS (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_RC_LINKCS2_ETC_Pos                  (4UL)          /*!< ETC (Bit 4)                                           */
+ #define R_PCIE0_PCI_RC_LINKCS2_ETC_Msk                  (0x10UL)       /*!< ETC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_LINKCS2_HASD_Pos                 (5UL)          /*!< HASD (Bit 5)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS2_HASD_Msk                 (0x20UL)       /*!< HASD (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_LINKCS2_SD_Pos                   (6UL)          /*!< SD (Bit 6)                                            */
+ #define R_PCIE0_PCI_RC_LINKCS2_SD_Msk                   (0x40UL)       /*!< SD (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_LINKCS2_TM_Pos                   (7UL)          /*!< TM (Bit 7)                                            */
+ #define R_PCIE0_PCI_RC_LINKCS2_TM_Msk                   (0x380UL)      /*!< TM (Bitfield-Mask: 0x07)                              */
+ #define R_PCIE0_PCI_RC_LINKCS2_EMC_Pos                  (10UL)         /*!< EMC (Bit 10)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS2_EMC_Msk                  (0x400UL)      /*!< EMC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_LINKCS2_CSOS_Pos                 (11UL)         /*!< CSOS (Bit 11)                                         */
+ #define R_PCIE0_PCI_RC_LINKCS2_CSOS_Msk                 (0x800UL)      /*!< CSOS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_LINKCS2_CPD_Pos                  (12UL)         /*!< CPD (Bit 12)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS2_CPD_Msk                  (0xf000UL)     /*!< CPD (Bitfield-Mask: 0x0f)                             */
+ #define R_PCIE0_PCI_RC_LINKCS2_CDL_Pos                  (16UL)         /*!< CDL (Bit 16)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS2_CDL_Msk                  (0x10000UL)    /*!< CDL (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_LINKCS2_EQC_Pos                  (17UL)         /*!< EQC (Bit 17)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS2_EQC_Msk                  (0x20000UL)    /*!< EQC (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_LINKCS2_EP1S_Pos                 (18UL)         /*!< EP1S (Bit 18)                                         */
+ #define R_PCIE0_PCI_RC_LINKCS2_EP1S_Msk                 (0x40000UL)    /*!< EP1S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_LINKCS2_EP2S_Pos                 (19UL)         /*!< EP2S (Bit 19)                                         */
+ #define R_PCIE0_PCI_RC_LINKCS2_EP2S_Msk                 (0x80000UL)    /*!< EP2S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_LINKCS2_EP3S_Pos                 (20UL)         /*!< EP3S (Bit 20)                                         */
+ #define R_PCIE0_PCI_RC_LINKCS2_EP3S_Msk                 (0x100000UL)   /*!< EP3S (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_LINKCS2_LER_Pos                  (21UL)         /*!< LER (Bit 21)                                          */
+ #define R_PCIE0_PCI_RC_LINKCS2_LER_Msk                  (0x200000UL)   /*!< LER (Bitfield-Mask: 0x01)                             */
+/* ==================================================  PCI_EP_BARMSK00L_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK00L_F0_BARM00L_Pos         (0UL)          /*!< BARM00L (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK00L_F0_BARM00L_Msk         (0xffffffffUL) /*!< BARM00L (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK00L_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK00L_F1_BARM00L_Pos         (0UL)          /*!< BARM00L (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK00L_F1_BARM00L_Msk         (0xffffffffUL) /*!< BARM00L (Bitfield-Mask: 0xffffffff)                   */
+/* ===================================================  PCI_RC_BARMSK00L  ==================================================== */
+ #define R_PCIE0_PCI_RC_BARMSK00L_BARM00L_Pos            (0UL)          /*!< BARM00L (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_BARMSK00L_BARM00L_Msk            (0xffffffffUL) /*!< BARM00L (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK00U_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK00U_F0_BARM00U_Pos         (0UL)          /*!< BARM00U (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK00U_F0_BARM00U_Msk         (0xffffffffUL) /*!< BARM00U (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK00U_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK00U_F1_BARM00U_Pos         (0UL)          /*!< BARM00U (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK00U_F1_BARM00U_Msk         (0xffffffffUL) /*!< BARM00U (Bitfield-Mask: 0xffffffff)                   */
+/* ===================================================  PCI_RC_BARMSK00U  ==================================================== */
+ #define R_PCIE0_PCI_RC_BARMSK00U_BARM00U_Pos            (0UL)          /*!< BARM00U (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_BARMSK00U_BARM00U_Msk            (0xffffffffUL) /*!< BARM00U (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK01L_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK01L_F0_BARM01L_Pos         (0UL)          /*!< BARM01L (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK01L_F0_BARM01L_Msk         (0xffffffffUL) /*!< BARM01L (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK01L_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK01L_F1_BARM01L_Pos         (0UL)          /*!< BARM01L (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK01L_F1_BARM01L_Msk         (0xffffffffUL) /*!< BARM01L (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK01U_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK01U_F0_BARM01U_Pos         (0UL)          /*!< BARM01U (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK01U_F0_BARM01U_Msk         (0xffffffffUL) /*!< BARM01U (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK01U_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK01U_F1_BARM01U_Pos         (0UL)          /*!< BARM01U (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK01U_F1_BARM01U_Msk         (0xffffffffUL) /*!< BARM01U (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK02L_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK02L_F0_BARM02L_Pos         (0UL)          /*!< BARM02L (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK02L_F0_BARM02L_Msk         (0xffffffffUL) /*!< BARM02L (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK02L_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK02L_F1_BARM02L_Pos         (0UL)          /*!< BARM02L (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK02L_F1_BARM02L_Msk         (0xffffffffUL) /*!< BARM02L (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK02U_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK02U_F0_BARM02U_Pos         (0UL)          /*!< BARM02U (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK02U_F0_BARM02U_Msk         (0xffffffffUL) /*!< BARM02U (Bitfield-Mask: 0xffffffff)                   */
+/* ==================================================  PCI_EP_BARMSK02U_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BARMSK02U_F1_BARM02U_Pos         (0UL)          /*!< BARM02U (Bit 0)                                       */
+ #define R_PCIE0_PCI_EP_BARMSK02U_F1_BARM02U_Msk         (0xffffffffUL) /*!< BARM02U (Bitfield-Mask: 0xffffffff)                   */
+/* =================================================  PCI_EP_BSIZE00_01_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BSIZE00_01_F0_BS00_Pos           (0UL)          /*!< BS00 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BSIZE00_01_F0_BS00_Msk           (0x3ffUL)      /*!< BS00 (Bitfield-Mask: 0x3ff)                           */
+ #define R_PCIE0_PCI_EP_BSIZE00_01_F0_BS01_Pos           (16UL)         /*!< BS01 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_BSIZE00_01_F0_BS01_Msk           (0x3ff0000UL)  /*!< BS01 (Bitfield-Mask: 0x3ff)                           */
+/* =================================================  PCI_EP_BSIZE00_01_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BSIZE00_01_F1_BS00_Pos           (0UL)          /*!< BS00 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BSIZE00_01_F1_BS00_Msk           (0x3ffUL)      /*!< BS00 (Bitfield-Mask: 0x3ff)                           */
+ #define R_PCIE0_PCI_EP_BSIZE00_01_F1_BS01_Pos           (16UL)         /*!< BS01 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_BSIZE00_01_F1_BS01_Msk           (0x3ff0000UL)  /*!< BS01 (Bitfield-Mask: 0x3ff)                           */
+/* ===================================================  PCI_RC_BSIZE00_01  =================================================== */
+ #define R_PCIE0_PCI_RC_BSIZE00_01_BS00_Pos              (0UL)          /*!< BS00 (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_BSIZE00_01_BS00_Msk              (0x3ffUL)      /*!< BS00 (Bitfield-Mask: 0x3ff)                           */
+/* =================================================  PCI_EP_BSIZE02_03_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BSIZE02_03_F0_BS02_Pos           (0UL)          /*!< BS02 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BSIZE02_03_F0_BS02_Msk           (0x3ffUL)      /*!< BS02 (Bitfield-Mask: 0x3ff)                           */
+ #define R_PCIE0_PCI_EP_BSIZE02_03_F0_BS03_Pos           (16UL)         /*!< BS03 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_BSIZE02_03_F0_BS03_Msk           (0x3ff0000UL)  /*!< BS03 (Bitfield-Mask: 0x3ff)                           */
+/* =================================================  PCI_EP_BSIZE02_03_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BSIZE02_03_F1_BS02_Pos           (0UL)          /*!< BS02 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BSIZE02_03_F1_BS02_Msk           (0x3ffUL)      /*!< BS02 (Bitfield-Mask: 0x3ff)                           */
+ #define R_PCIE0_PCI_EP_BSIZE02_03_F1_BS03_Pos           (16UL)         /*!< BS03 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_BSIZE02_03_F1_BS03_Msk           (0x3ff0000UL)  /*!< BS03 (Bitfield-Mask: 0x3ff)                           */
+/* =================================================  PCI_EP_BSIZE04_05_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_BSIZE04_05_F0_BS04_Pos           (0UL)          /*!< BS04 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BSIZE04_05_F0_BS04_Msk           (0x3ffUL)      /*!< BS04 (Bitfield-Mask: 0x3ff)                           */
+ #define R_PCIE0_PCI_EP_BSIZE04_05_F0_BS05_Pos           (16UL)         /*!< BS05 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_BSIZE04_05_F0_BS05_Msk           (0x3ff0000UL)  /*!< BS05 (Bitfield-Mask: 0x3ff)                           */
+/* =================================================  PCI_EP_BSIZE04_05_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_BSIZE04_05_F1_BS04_Pos           (0UL)          /*!< BS04 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BSIZE04_05_F1_BS04_Msk           (0x3ffUL)      /*!< BS04 (Bitfield-Mask: 0x3ff)                           */
+ #define R_PCIE0_PCI_EP_BSIZE04_05_F1_BS05_Pos           (16UL)         /*!< BS05 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_BSIZE04_05_F1_BS05_Msk           (0x3ff0000UL)  /*!< BS05 (Bitfield-Mask: 0x3ff)                           */
+/* ===================================================  PCI_EP_BSIZE06_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_BSIZE06_F0_BS06_Pos              (0UL)          /*!< BS06 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BSIZE06_F0_BS06_Msk              (0x3ffUL)      /*!< BS06 (Bitfield-Mask: 0x3ff)                           */
+/* ===================================================  PCI_EP_BSIZE06_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_BSIZE06_F1_BS06_Pos              (0UL)          /*!< BS06 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_BSIZE06_F1_BS06_Msk              (0x3ffUL)      /*!< BS06 (Bitfield-Mask: 0x3ff)                           */
+/* ==============================================  PCI_EP_TSUPPORT00_01_02_F0  =============================================== */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F0_TS00_Pos     (0UL)          /*!< TS00 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F0_TS00_Msk     (0xffUL)       /*!< TS00 (Bitfield-Mask: 0xff)                            */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F0_TS01_Pos     (8UL)          /*!< TS01 (Bit 8)                                          */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F0_TS01_Msk     (0xff00UL)     /*!< TS01 (Bitfield-Mask: 0xff)                            */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F0_TS02_Pos     (16UL)         /*!< TS02 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F0_TS02_Msk     (0xff0000UL)   /*!< TS02 (Bitfield-Mask: 0xff)                            */
+/* ==============================================  PCI_EP_TSUPPORT00_01_02_F1  =============================================== */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F1_TS00_Pos     (0UL)          /*!< TS00 (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F1_TS00_Msk     (0xffUL)       /*!< TS00 (Bitfield-Mask: 0xff)                            */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F1_TS01_Pos     (8UL)          /*!< TS01 (Bit 8)                                          */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F1_TS01_Msk     (0xff00UL)     /*!< TS01 (Bitfield-Mask: 0xff)                            */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F1_TS02_Pos     (16UL)         /*!< TS02 (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_TSUPPORT00_01_02_F1_TS02_Msk     (0xff0000UL)   /*!< TS02 (Bitfield-Mask: 0xff)                            */
+/* ================================================  PCI_RC_TSUPPORT00_01_02  ================================================ */
+ #define R_PCIE0_PCI_RC_TSUPPORT00_01_02_TS00_Pos        (0UL)          /*!< TS00 (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_TSUPPORT00_01_02_TS00_Msk        (0xffUL)       /*!< TS00 (Bitfield-Mask: 0xff)                            */
+/* ===================================================  PCI_EP_MSICAP_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_CID_Pos                (0UL)          /*!< CID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_CID_Msk                (0xffUL)       /*!< CID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_NCP_Pos                (8UL)          /*!< NCP (Bit 8)                                           */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_NCP_Msk                (0xff00UL)     /*!< NCP (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_MSIE_Pos               (16UL)         /*!< MSIE (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_MSIE_Msk               (0x10000UL)    /*!< MSIE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_MMC_Pos                (17UL)         /*!< MMC (Bit 17)                                          */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_MMC_Msk                (0xe0000UL)    /*!< MMC (Bitfield-Mask: 0x07)                             */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_MME_Pos                (20UL)         /*!< MME (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_MME_Msk                (0x700000UL)   /*!< MME (Bitfield-Mask: 0x07)                             */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_AC64_Pos               (23UL)         /*!< AC64 (Bit 23)                                         */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_AC64_Msk               (0x800000UL)   /*!< AC64 (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_PVMC_Pos               (24UL)         /*!< PVMC (Bit 24)                                         */
+ #define R_PCIE0_PCI_EP_MSICAP_F0_PVMC_Msk               (0x1000000UL)  /*!< PVMC (Bitfield-Mask: 0x01)                            */
+/* ===================================================  PCI_EP_MSICAP_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_CID_Pos                (0UL)          /*!< CID (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_CID_Msk                (0xffUL)       /*!< CID (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_NCP_Pos                (8UL)          /*!< NCP (Bit 8)                                           */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_NCP_Msk                (0xff00UL)     /*!< NCP (Bitfield-Mask: 0xff)                             */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_MSIE_Pos               (16UL)         /*!< MSIE (Bit 16)                                         */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_MSIE_Msk               (0x10000UL)    /*!< MSIE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_MMC_Pos                (17UL)         /*!< MMC (Bit 17)                                          */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_MMC_Msk                (0xe0000UL)    /*!< MMC (Bitfield-Mask: 0x07)                             */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_MME_Pos                (20UL)         /*!< MME (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_MME_Msk                (0x700000UL)   /*!< MME (Bitfield-Mask: 0x07)                             */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_AC64_Pos               (23UL)         /*!< AC64 (Bit 23)                                         */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_AC64_Msk               (0x800000UL)   /*!< AC64 (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_PVMC_Pos               (24UL)         /*!< PVMC (Bit 24)                                         */
+ #define R_PCIE0_PCI_EP_MSICAP_F1_PVMC_Msk               (0x1000000UL)  /*!< PVMC (Bitfield-Mask: 0x01)                            */
+/* ===================================================  PCI_EP_MSGADR_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSGADR_F0_MA_Pos                 (2UL)          /*!< MA (Bit 2)                                            */
+ #define R_PCIE0_PCI_EP_MSGADR_F0_MA_Msk                 (0xfffffffcUL) /*!< MA (Bitfield-Mask: 0x3fffffff)                        */
+/* ===================================================  PCI_EP_MSGADR_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSGADR_F1_MA_Pos                 (2UL)          /*!< MA (Bit 2)                                            */
+ #define R_PCIE0_PCI_EP_MSGADR_F1_MA_Msk                 (0xfffffffcUL) /*!< MA (Bitfield-Mask: 0x3fffffff)                        */
+/* ===================================================  PCI_EP_MSGUADR_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_MSGUADR_F0_MUA_Pos               (0UL)          /*!< MUA (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_MSGUADR_F0_MUA_Msk               (0xffffffffUL) /*!< MUA (Bitfield-Mask: 0xffffffff)                       */
+/* ===================================================  PCI_EP_MSGUADR_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_MSGUADR_F1_MUA_Pos               (0UL)          /*!< MUA (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_MSGUADR_F1_MUA_Msk               (0xffffffffUL) /*!< MUA (Bitfield-Mask: 0xffffffff)                       */
+/* ===================================================  PCI_EP_MSGDAT_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSGDAT_F0_MD_Pos                 (0UL)          /*!< MD (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_MSGDAT_F0_MD_Msk                 (0xffffUL)     /*!< MD (Bitfield-Mask: 0xffff)                            */
+/* ===================================================  PCI_EP_MSGDAT_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSGDAT_F1_MD_Pos                 (0UL)          /*!< MD (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_MSGDAT_F1_MD_Msk                 (0xffffUL)     /*!< MD (Bitfield-Mask: 0xffff)                            */
+/* ===================================================  PCI_EP_MSKBIT_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSKBIT_F0_MB_Pos                 (0UL)          /*!< MB (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_MSKBIT_F0_MB_Msk                 (0xffffffffUL) /*!< MB (Bitfield-Mask: 0xffffffff)                        */
+/* ===================================================  PCI_EP_MSKBIT_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_MSKBIT_F1_MB_Pos                 (0UL)          /*!< MB (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_MSKBIT_F1_MB_Msk                 (0xffffffffUL) /*!< MB (Bitfield-Mask: 0xffffffff)                        */
+/* ===================================================  PCI_EP_PENDBIT_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_PENDBIT_F0_PB_Pos                (0UL)          /*!< PB (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_PENDBIT_F0_PB_Msk                (0xffffffffUL) /*!< PB (Bitfield-Mask: 0xffffffff)                        */
+/* ===================================================  PCI_EP_PENDBIT_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_PENDBIT_F1_PB_Pos                (0UL)          /*!< PB (Bit 0)                                            */
+ #define R_PCIE0_PCI_EP_PENDBIT_F1_PB_Msk                (0xffffffffUL) /*!< PB (Bitfield-Mask: 0xffffffff)                        */
+/* ===================================================  PCI_EP_ADVERC_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_ADVERC_F0_PCIEECID_Pos           (0UL)          /*!< PCIEECID (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_ADVERC_F0_PCIEECID_Msk           (0xffffUL)     /*!< PCIEECID (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_EP_ADVERC_F0_CV_Pos                 (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_ADVERC_F0_CV_Msk                 (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_EP_ADVERC_F0_NCO_Pos                (20UL)         /*!< NCO (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_ADVERC_F0_NCO_Msk                (0xfff00000UL) /*!< NCO (Bitfield-Mask: 0xfff)                            */
+/* ===================================================  PCI_EP_ADVERC_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_ADVERC_F1_PCIEECID_Pos           (0UL)          /*!< PCIEECID (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_ADVERC_F1_PCIEECID_Msk           (0xffffUL)     /*!< PCIEECID (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_EP_ADVERC_F1_CV_Pos                 (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_ADVERC_F1_CV_Msk                 (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_EP_ADVERC_F1_NCO_Pos                (20UL)         /*!< NCO (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_ADVERC_F1_NCO_Msk                (0xfff00000UL) /*!< NCO (Bitfield-Mask: 0xfff)                            */
+/* =====================================================  PCI_RC_ADVERC  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADVERC_PCIEECID_Pos              (0UL)          /*!< PCIEECID (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_ADVERC_PCIEECID_Msk              (0xffffUL)     /*!< PCIEECID (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_RC_ADVERC_CV_Pos                    (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_RC_ADVERC_CV_Msk                    (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_RC_ADVERC_NCO_Pos                   (20UL)         /*!< NCO (Bit 20)                                          */
+ #define R_PCIE0_PCI_RC_ADVERC_NCO_Msk                   (0xfff00000UL) /*!< NCO (Bitfield-Mask: 0xfff)                            */
+/* ===================================================  PCI_EP_UNCESTS_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_DLPES_Pos             (4UL)          /*!< DLPES (Bit 4)                                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_DLPES_Msk             (0x10UL)       /*!< DLPES (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_PTLPRS_Pos            (12UL)         /*!< PTLPRS (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_PTLPRS_Msk            (0x1000UL)     /*!< PTLPRS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_CTS_Pos               (14UL)         /*!< CTS (Bit 14)                                          */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_CTS_Msk               (0x4000UL)     /*!< CTS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_CASO_Pos              (15UL)         /*!< CASO (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_CASO_Msk              (0x8000UL)     /*!< CASO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_UCS_Pos               (16UL)         /*!< UCS (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_UCS_Msk               (0x10000UL)    /*!< UCS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_ROSO_Pos              (17UL)         /*!< ROSO (Bit 17)                                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_ROSO_Msk              (0x20000UL)    /*!< ROSO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_MTLPS_Pos             (18UL)         /*!< MTLPS (Bit 18)                                        */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_MTLPS_Msk             (0x40000UL)    /*!< MTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_ECRCESO_Pos           (19UL)         /*!< ECRCESO (Bit 19)                                      */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_ECRCESO_Msk           (0x80000UL)    /*!< ECRCESO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_URES_Pos              (20UL)         /*!< URES (Bit 20)                                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F0_URES_Msk              (0x100000UL)   /*!< URES (Bitfield-Mask: 0x01)                            */
+/* ===================================================  PCI_EP_UNCESTS_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_DLPES_Pos             (4UL)          /*!< DLPES (Bit 4)                                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_DLPES_Msk             (0x10UL)       /*!< DLPES (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_PTLPRS_Pos            (12UL)         /*!< PTLPRS (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_PTLPRS_Msk            (0x1000UL)     /*!< PTLPRS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_CTS_Pos               (14UL)         /*!< CTS (Bit 14)                                          */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_CTS_Msk               (0x4000UL)     /*!< CTS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_CASO_Pos              (15UL)         /*!< CASO (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_CASO_Msk              (0x8000UL)     /*!< CASO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_UCS_Pos               (16UL)         /*!< UCS (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_UCS_Msk               (0x10000UL)    /*!< UCS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_ROSO_Pos              (17UL)         /*!< ROSO (Bit 17)                                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_ROSO_Msk              (0x20000UL)    /*!< ROSO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_MTLPS_Pos             (18UL)         /*!< MTLPS (Bit 18)                                        */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_MTLPS_Msk             (0x40000UL)    /*!< MTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_ECRCESO_Pos           (19UL)         /*!< ECRCESO (Bit 19)                                      */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_ECRCESO_Msk           (0x80000UL)    /*!< ECRCESO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_URES_Pos              (20UL)         /*!< URES (Bit 20)                                         */
+ #define R_PCIE0_PCI_EP_UNCESTS_F1_URES_Msk              (0x100000UL)   /*!< URES (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_RC_UNCESTS  ===================================================== */
+ #define R_PCIE0_PCI_RC_UNCESTS_DLPES_Pos                (4UL)          /*!< DLPES (Bit 4)                                         */
+ #define R_PCIE0_PCI_RC_UNCESTS_DLPES_Msk                (0x10UL)       /*!< DLPES (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_UNCESTS_PTLPRS_Pos               (12UL)         /*!< PTLPRS (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_UNCESTS_PTLPRS_Msk               (0x1000UL)     /*!< PTLPRS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_UNCESTS_CTS_Pos                  (14UL)         /*!< CTS (Bit 14)                                          */
+ #define R_PCIE0_PCI_RC_UNCESTS_CTS_Msk                  (0x4000UL)     /*!< CTS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_UNCESTS_CASO_Pos                 (15UL)         /*!< CASO (Bit 15)                                         */
+ #define R_PCIE0_PCI_RC_UNCESTS_CASO_Msk                 (0x8000UL)     /*!< CASO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_UNCESTS_UCS_Pos                  (16UL)         /*!< UCS (Bit 16)                                          */
+ #define R_PCIE0_PCI_RC_UNCESTS_UCS_Msk                  (0x10000UL)    /*!< UCS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_UNCESTS_ROSO_Pos                 (17UL)         /*!< ROSO (Bit 17)                                         */
+ #define R_PCIE0_PCI_RC_UNCESTS_ROSO_Msk                 (0x20000UL)    /*!< ROSO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_UNCESTS_MTLPS_Pos                (18UL)         /*!< MTLPS (Bit 18)                                        */
+ #define R_PCIE0_PCI_RC_UNCESTS_MTLPS_Msk                (0x40000UL)    /*!< MTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_UNCESTS_ECRCESO_Pos              (19UL)         /*!< ECRCESO (Bit 19)                                      */
+ #define R_PCIE0_PCI_RC_UNCESTS_ECRCESO_Msk              (0x80000UL)    /*!< ECRCESO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_UNCESTS_URES_Pos                 (20UL)         /*!< URES (Bit 20)                                         */
+ #define R_PCIE0_PCI_RC_UNCESTS_URES_Msk                 (0x100000UL)   /*!< URES (Bitfield-Mask: 0x01)                            */
+/* ==================================================  PCI_EP_UNCEMASK_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_DLPEM_Pos            (4UL)          /*!< DLPEM (Bit 4)                                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_DLPEM_Msk            (0x10UL)       /*!< DLPEM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_PTLPRM_Pos           (12UL)         /*!< PTLPRM (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_PTLPRM_Msk           (0x1000UL)     /*!< PTLPRM (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_CTM_Pos              (14UL)         /*!< CTM (Bit 14)                                          */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_CTM_Msk              (0x4000UL)     /*!< CTM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_CAMO_Pos             (15UL)         /*!< CAMO (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_CAMO_Msk             (0x8000UL)     /*!< CAMO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_UCM_Pos              (16UL)         /*!< UCM (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_UCM_Msk              (0x10000UL)    /*!< UCM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_ROMO_Pos             (17UL)         /*!< ROMO (Bit 17)                                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_ROMO_Msk             (0x20000UL)    /*!< ROMO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_MTLPM_Pos            (18UL)         /*!< MTLPM (Bit 18)                                        */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_MTLPM_Msk            (0x40000UL)    /*!< MTLPM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_ECRCEMO_Pos          (19UL)         /*!< ECRCEMO (Bit 19)                                      */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_ECRCEMO_Msk          (0x80000UL)    /*!< ECRCEMO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_UREM_Pos             (20UL)         /*!< UREM (Bit 20)                                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F0_UREM_Msk             (0x100000UL)   /*!< UREM (Bitfield-Mask: 0x01)                            */
+/* ==================================================  PCI_EP_UNCEMASK_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_DLPEM_Pos            (4UL)          /*!< DLPEM (Bit 4)                                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_DLPEM_Msk            (0x10UL)       /*!< DLPEM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_PTLPRM_Pos           (12UL)         /*!< PTLPRM (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_PTLPRM_Msk           (0x1000UL)     /*!< PTLPRM (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_CTM_Pos              (14UL)         /*!< CTM (Bit 14)                                          */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_CTM_Msk              (0x4000UL)     /*!< CTM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_CAMO_Pos             (15UL)         /*!< CAMO (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_CAMO_Msk             (0x8000UL)     /*!< CAMO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_UCM_Pos              (16UL)         /*!< UCM (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_UCM_Msk              (0x10000UL)    /*!< UCM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_ROMO_Pos             (17UL)         /*!< ROMO (Bit 17)                                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_ROMO_Msk             (0x20000UL)    /*!< ROMO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_MTLPM_Pos            (18UL)         /*!< MTLPM (Bit 18)                                        */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_MTLPM_Msk            (0x40000UL)    /*!< MTLPM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_ECRCEMO_Pos          (19UL)         /*!< ECRCEMO (Bit 19)                                      */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_ECRCEMO_Msk          (0x80000UL)    /*!< ECRCEMO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_UREM_Pos             (20UL)         /*!< UREM (Bit 20)                                         */
+ #define R_PCIE0_PCI_EP_UNCEMASK_F1_UREM_Msk             (0x100000UL)   /*!< UREM (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_RC_UNCEMASK  ==================================================== */
+ #define R_PCIE0_PCI_RC_UNCEMASK_DLPEM_Pos               (4UL)          /*!< DLPEM (Bit 4)                                         */
+ #define R_PCIE0_PCI_RC_UNCEMASK_DLPEM_Msk               (0x10UL)       /*!< DLPEM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_UNCEMASK_PTLPRM_Pos              (12UL)         /*!< PTLPRM (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_UNCEMASK_PTLPRM_Msk              (0x1000UL)     /*!< PTLPRM (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_UNCEMASK_CTM_Pos                 (14UL)         /*!< CTM (Bit 14)                                          */
+ #define R_PCIE0_PCI_RC_UNCEMASK_CTM_Msk                 (0x4000UL)     /*!< CTM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_UNCEMASK_CAMO_Pos                (15UL)         /*!< CAMO (Bit 15)                                         */
+ #define R_PCIE0_PCI_RC_UNCEMASK_CAMO_Msk                (0x8000UL)     /*!< CAMO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_UNCEMASK_UCM_Pos                 (16UL)         /*!< UCM (Bit 16)                                          */
+ #define R_PCIE0_PCI_RC_UNCEMASK_UCM_Msk                 (0x10000UL)    /*!< UCM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_UNCEMASK_ROMO_Pos                (17UL)         /*!< ROMO (Bit 17)                                         */
+ #define R_PCIE0_PCI_RC_UNCEMASK_ROMO_Msk                (0x20000UL)    /*!< ROMO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_UNCEMASK_MTLPM_Pos               (18UL)         /*!< MTLPM (Bit 18)                                        */
+ #define R_PCIE0_PCI_RC_UNCEMASK_MTLPM_Msk               (0x40000UL)    /*!< MTLPM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_UNCEMASK_ECRCEMO_Pos             (19UL)         /*!< ECRCEMO (Bit 19)                                      */
+ #define R_PCIE0_PCI_RC_UNCEMASK_ECRCEMO_Msk             (0x80000UL)    /*!< ECRCEMO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_UNCEMASK_UREM_Pos                (20UL)         /*!< UREM (Bit 20)                                         */
+ #define R_PCIE0_PCI_RC_UNCEMASK_UREM_Msk                (0x100000UL)   /*!< UREM (Bitfield-Mask: 0x01)                            */
+/* ===================================================  PCI_EP_UNCESVY_F0  =================================================== */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_DLPES_Pos             (4UL)          /*!< DLPES (Bit 4)                                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_DLPES_Msk             (0x10UL)       /*!< DLPES (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_PTLPRS_Pos            (12UL)         /*!< PTLPRS (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_PTLPRS_Msk            (0x1000UL)     /*!< PTLPRS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_CTS_Pos               (14UL)         /*!< CTS (Bit 14)                                          */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_CTS_Msk               (0x4000UL)     /*!< CTS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_CASO_Pos              (15UL)         /*!< CASO (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_CASO_Msk              (0x8000UL)     /*!< CASO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_UCS_Pos               (16UL)         /*!< UCS (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_UCS_Msk               (0x10000UL)    /*!< UCS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_ROSO_Pos              (17UL)         /*!< ROSO (Bit 17)                                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_ROSO_Msk              (0x20000UL)    /*!< ROSO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_MTLPS_Pos             (18UL)         /*!< MTLPS (Bit 18)                                        */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_MTLPS_Msk             (0x40000UL)    /*!< MTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_ECRCESO_Pos           (19UL)         /*!< ECRCESO (Bit 19)                                      */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_ECRCESO_Msk           (0x80000UL)    /*!< ECRCESO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_URES_Pos              (20UL)         /*!< URES (Bit 20)                                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F0_URES_Msk              (0x100000UL)   /*!< URES (Bitfield-Mask: 0x01)                            */
+/* ===================================================  PCI_EP_UNCESVY_F1  =================================================== */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_DLPES_Pos             (4UL)          /*!< DLPES (Bit 4)                                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_DLPES_Msk             (0x10UL)       /*!< DLPES (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_PTLPRS_Pos            (12UL)         /*!< PTLPRS (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_PTLPRS_Msk            (0x1000UL)     /*!< PTLPRS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_CTS_Pos               (14UL)         /*!< CTS (Bit 14)                                          */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_CTS_Msk               (0x4000UL)     /*!< CTS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_CASO_Pos              (15UL)         /*!< CASO (Bit 15)                                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_CASO_Msk              (0x8000UL)     /*!< CASO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_UCS_Pos               (16UL)         /*!< UCS (Bit 16)                                          */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_UCS_Msk               (0x10000UL)    /*!< UCS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_ROSO_Pos              (17UL)         /*!< ROSO (Bit 17)                                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_ROSO_Msk              (0x20000UL)    /*!< ROSO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_MTLPS_Pos             (18UL)         /*!< MTLPS (Bit 18)                                        */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_MTLPS_Msk             (0x40000UL)    /*!< MTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_ECRCESO_Pos           (19UL)         /*!< ECRCESO (Bit 19)                                      */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_ECRCESO_Msk           (0x80000UL)    /*!< ECRCESO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_URES_Pos              (20UL)         /*!< URES (Bit 20)                                         */
+ #define R_PCIE0_PCI_EP_UNCESVY_F1_URES_Msk              (0x100000UL)   /*!< URES (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_RC_UNCESVY  ===================================================== */
+ #define R_PCIE0_PCI_RC_UNCESVY_DLPES_Pos                (4UL)          /*!< DLPES (Bit 4)                                         */
+ #define R_PCIE0_PCI_RC_UNCESVY_DLPES_Msk                (0x10UL)       /*!< DLPES (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_UNCESVY_PTLPRS_Pos               (12UL)         /*!< PTLPRS (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_UNCESVY_PTLPRS_Msk               (0x1000UL)     /*!< PTLPRS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_UNCESVY_CTS_Pos                  (14UL)         /*!< CTS (Bit 14)                                          */
+ #define R_PCIE0_PCI_RC_UNCESVY_CTS_Msk                  (0x4000UL)     /*!< CTS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_UNCESVY_CASO_Pos                 (15UL)         /*!< CASO (Bit 15)                                         */
+ #define R_PCIE0_PCI_RC_UNCESVY_CASO_Msk                 (0x8000UL)     /*!< CASO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_UNCESVY_UCS_Pos                  (16UL)         /*!< UCS (Bit 16)                                          */
+ #define R_PCIE0_PCI_RC_UNCESVY_UCS_Msk                  (0x10000UL)    /*!< UCS (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_UNCESVY_ROSO_Pos                 (17UL)         /*!< ROSO (Bit 17)                                         */
+ #define R_PCIE0_PCI_RC_UNCESVY_ROSO_Msk                 (0x20000UL)    /*!< ROSO (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_UNCESVY_MTLPS_Pos                (18UL)         /*!< MTLPS (Bit 18)                                        */
+ #define R_PCIE0_PCI_RC_UNCESVY_MTLPS_Msk                (0x40000UL)    /*!< MTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_UNCESVY_ECRCESO_Pos              (19UL)         /*!< ECRCESO (Bit 19)                                      */
+ #define R_PCIE0_PCI_RC_UNCESVY_ECRCESO_Msk              (0x80000UL)    /*!< ECRCESO (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_UNCESVY_URES_Pos                 (20UL)         /*!< URES (Bit 20)                                         */
+ #define R_PCIE0_PCI_RC_UNCESVY_URES_Msk                 (0x100000UL)   /*!< URES (Bitfield-Mask: 0x01)                            */
+/* ====================================================  PCI_EP_CESTS_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_CESTS_F0_RES_Pos                 (0UL)          /*!< RES (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_CESTS_F0_RES_Msk                 (0x1UL)        /*!< RES (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_CESTS_F0_BTLPS_Pos               (6UL)          /*!< BTLPS (Bit 6)                                         */
+ #define R_PCIE0_PCI_EP_CESTS_F0_BTLPS_Msk               (0x40UL)       /*!< BTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_CESTS_F0_BDLLPS_Pos              (7UL)          /*!< BDLLPS (Bit 7)                                        */
+ #define R_PCIE0_PCI_EP_CESTS_F0_BDLLPS_Msk              (0x80UL)       /*!< BDLLPS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_CESTS_F0_REPLAYNUMRS_Pos         (8UL)          /*!< REPLAYNUMRS (Bit 8)                                   */
+ #define R_PCIE0_PCI_EP_CESTS_F0_REPLAYNUMRS_Msk         (0x100UL)      /*!< REPLAYNUMRS (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_CESTS_F0_RTTS_Pos                (12UL)         /*!< RTTS (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_CESTS_F0_RTTS_Msk                (0x1000UL)     /*!< RTTS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_CESTS_F0_ANFES_Pos               (13UL)         /*!< ANFES (Bit 13)                                        */
+ #define R_PCIE0_PCI_EP_CESTS_F0_ANFES_Msk               (0x2000UL)     /*!< ANFES (Bitfield-Mask: 0x01)                           */
+/* ====================================================  PCI_EP_CESTS_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_CESTS_F1_RES_Pos                 (0UL)          /*!< RES (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_CESTS_F1_RES_Msk                 (0x1UL)        /*!< RES (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_CESTS_F1_BTLPS_Pos               (6UL)          /*!< BTLPS (Bit 6)                                         */
+ #define R_PCIE0_PCI_EP_CESTS_F1_BTLPS_Msk               (0x40UL)       /*!< BTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_CESTS_F1_BDLLPS_Pos              (7UL)          /*!< BDLLPS (Bit 7)                                        */
+ #define R_PCIE0_PCI_EP_CESTS_F1_BDLLPS_Msk              (0x80UL)       /*!< BDLLPS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_CESTS_F1_REPLAYNUMRS_Pos         (8UL)          /*!< REPLAYNUMRS (Bit 8)                                   */
+ #define R_PCIE0_PCI_EP_CESTS_F1_REPLAYNUMRS_Msk         (0x100UL)      /*!< REPLAYNUMRS (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_CESTS_F1_RTTS_Pos                (12UL)         /*!< RTTS (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_CESTS_F1_RTTS_Msk                (0x1000UL)     /*!< RTTS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_CESTS_F1_ANFES_Pos               (13UL)         /*!< ANFES (Bit 13)                                        */
+ #define R_PCIE0_PCI_EP_CESTS_F1_ANFES_Msk               (0x2000UL)     /*!< ANFES (Bitfield-Mask: 0x01)                           */
+/* =====================================================  PCI_RC_CESTS  ====================================================== */
+ #define R_PCIE0_PCI_RC_CESTS_RES_Pos                    (0UL)          /*!< RES (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_CESTS_RES_Msk                    (0x1UL)        /*!< RES (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_CESTS_BTLPS_Pos                  (6UL)          /*!< BTLPS (Bit 6)                                         */
+ #define R_PCIE0_PCI_RC_CESTS_BTLPS_Msk                  (0x40UL)       /*!< BTLPS (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_CESTS_BDLLPS_Pos                 (7UL)          /*!< BDLLPS (Bit 7)                                        */
+ #define R_PCIE0_PCI_RC_CESTS_BDLLPS_Msk                 (0x80UL)       /*!< BDLLPS (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_CESTS_REPLAYNUMRS_Pos            (8UL)          /*!< REPLAYNUMRS (Bit 8)                                   */
+ #define R_PCIE0_PCI_RC_CESTS_REPLAYNUMRS_Msk            (0x100UL)      /*!< REPLAYNUMRS (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_CESTS_RTTS_Pos                   (12UL)         /*!< RTTS (Bit 12)                                         */
+ #define R_PCIE0_PCI_RC_CESTS_RTTS_Msk                   (0x1000UL)     /*!< RTTS (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_CESTS_ANFES_Pos                  (13UL)         /*!< ANFES (Bit 13)                                        */
+ #define R_PCIE0_PCI_RC_CESTS_ANFES_Msk                  (0x2000UL)     /*!< ANFES (Bitfield-Mask: 0x01)                           */
+/* ===================================================  PCI_EP_CEMASK_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_REM_Pos                (0UL)          /*!< REM (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_REM_Msk                (0x1UL)        /*!< REM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_BTLPM_Pos              (6UL)          /*!< BTLPM (Bit 6)                                         */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_BTLPM_Msk              (0x40UL)       /*!< BTLPM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_BDLLPM_Pos             (7UL)          /*!< BDLLPM (Bit 7)                                        */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_BDLLPM_Msk             (0x80UL)       /*!< BDLLPM (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_REPLAYNUMRM_Pos        (8UL)          /*!< REPLAYNUMRM (Bit 8)                                   */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_REPLAYNUMRM_Msk        (0x100UL)      /*!< REPLAYNUMRM (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_RTTM_Pos               (12UL)         /*!< RTTM (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_RTTM_Msk               (0x1000UL)     /*!< RTTM (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_ANFEM_Pos              (13UL)         /*!< ANFEM (Bit 13)                                        */
+ #define R_PCIE0_PCI_EP_CEMASK_F0_ANFEM_Msk              (0x2000UL)     /*!< ANFEM (Bitfield-Mask: 0x01)                           */
+/* ===================================================  PCI_EP_CEMASK_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_REM_Pos                (0UL)          /*!< REM (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_REM_Msk                (0x1UL)        /*!< REM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_BTLPM_Pos              (6UL)          /*!< BTLPM (Bit 6)                                         */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_BTLPM_Msk              (0x40UL)       /*!< BTLPM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_BDLLPM_Pos             (7UL)          /*!< BDLLPM (Bit 7)                                        */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_BDLLPM_Msk             (0x80UL)       /*!< BDLLPM (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_REPLAYNUMRM_Pos        (8UL)          /*!< REPLAYNUMRM (Bit 8)                                   */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_REPLAYNUMRM_Msk        (0x100UL)      /*!< REPLAYNUMRM (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_RTTM_Pos               (12UL)         /*!< RTTM (Bit 12)                                         */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_RTTM_Msk               (0x1000UL)     /*!< RTTM (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_ANFEM_Pos              (13UL)         /*!< ANFEM (Bit 13)                                        */
+ #define R_PCIE0_PCI_EP_CEMASK_F1_ANFEM_Msk              (0x2000UL)     /*!< ANFEM (Bitfield-Mask: 0x01)                           */
+/* =====================================================  PCI_RC_CEMASK  ===================================================== */
+ #define R_PCIE0_PCI_RC_CEMASK_REM_Pos                   (0UL)          /*!< REM (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_CEMASK_REM_Msk                   (0x1UL)        /*!< REM (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_CEMASK_BTLPM_Pos                 (6UL)          /*!< BTLPM (Bit 6)                                         */
+ #define R_PCIE0_PCI_RC_CEMASK_BTLPM_Msk                 (0x40UL)       /*!< BTLPM (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_CEMASK_BDLLPM_Pos                (7UL)          /*!< BDLLPM (Bit 7)                                        */
+ #define R_PCIE0_PCI_RC_CEMASK_BDLLPM_Msk                (0x80UL)       /*!< BDLLPM (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_CEMASK_REPLAYNUMRM_Pos           (8UL)          /*!< REPLAYNUMRM (Bit 8)                                   */
+ #define R_PCIE0_PCI_RC_CEMASK_REPLAYNUMRM_Msk           (0x100UL)      /*!< REPLAYNUMRM (Bitfield-Mask: 0x01)                     */
+ #define R_PCIE0_PCI_RC_CEMASK_RTTM_Pos                  (12UL)         /*!< RTTM (Bit 12)                                         */
+ #define R_PCIE0_PCI_RC_CEMASK_RTTM_Msk                  (0x1000UL)     /*!< RTTM (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_CEMASK_ANFEM_Pos                 (13UL)         /*!< ANFEM (Bit 13)                                        */
+ #define R_PCIE0_PCI_RC_CEMASK_ANFEM_Msk                 (0x2000UL)     /*!< ANFEM (Bitfield-Mask: 0x01)                           */
+/* ===================================================  PCI_EP_ADVECC_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_FEP_Pos                (0UL)          /*!< FEP (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_FEP_Msk                (0x1fUL)       /*!< FEP (Bitfield-Mask: 0x1f)                             */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_ECRCGC_Pos             (5UL)          /*!< ECRCGC (Bit 5)                                        */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_ECRCGC_Msk             (0x20UL)       /*!< ECRCGC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_ECRCGE_Pos             (6UL)          /*!< ECRCGE (Bit 6)                                        */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_ECRCGE_Msk             (0x40UL)       /*!< ECRCGE (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_ECRCCC_Pos             (7UL)          /*!< ECRCCC (Bit 7)                                        */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_ECRCCC_Msk             (0x80UL)       /*!< ECRCCC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_ECRCCE_Pos             (8UL)          /*!< ECRCCE (Bit 8)                                        */
+ #define R_PCIE0_PCI_EP_ADVECC_F0_ECRCCE_Msk             (0x100UL)      /*!< ECRCCE (Bitfield-Mask: 0x01)                          */
+/* ===================================================  PCI_EP_ADVECC_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_FEP_Pos                (0UL)          /*!< FEP (Bit 0)                                           */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_FEP_Msk                (0x1fUL)       /*!< FEP (Bitfield-Mask: 0x1f)                             */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_ECRCGC_Pos             (5UL)          /*!< ECRCGC (Bit 5)                                        */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_ECRCGC_Msk             (0x20UL)       /*!< ECRCGC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_ECRCGE_Pos             (6UL)          /*!< ECRCGE (Bit 6)                                        */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_ECRCGE_Msk             (0x40UL)       /*!< ECRCGE (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_ECRCCC_Pos             (7UL)          /*!< ECRCCC (Bit 7)                                        */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_ECRCCC_Msk             (0x80UL)       /*!< ECRCCC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_ECRCCE_Pos             (8UL)          /*!< ECRCCE (Bit 8)                                        */
+ #define R_PCIE0_PCI_EP_ADVECC_F1_ECRCCE_Msk             (0x100UL)      /*!< ECRCCE (Bitfield-Mask: 0x01)                          */
+/* =====================================================  PCI_RC_ADVECC  ===================================================== */
+ #define R_PCIE0_PCI_RC_ADVECC_FEP_Pos                   (0UL)          /*!< FEP (Bit 0)                                           */
+ #define R_PCIE0_PCI_RC_ADVECC_FEP_Msk                   (0x1fUL)       /*!< FEP (Bitfield-Mask: 0x1f)                             */
+ #define R_PCIE0_PCI_RC_ADVECC_ECRCGC_Pos                (5UL)          /*!< ECRCGC (Bit 5)                                        */
+ #define R_PCIE0_PCI_RC_ADVECC_ECRCGC_Msk                (0x20UL)       /*!< ECRCGC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_ADVECC_ECRCGE_Pos                (6UL)          /*!< ECRCGE (Bit 6)                                        */
+ #define R_PCIE0_PCI_RC_ADVECC_ECRCGE_Msk                (0x40UL)       /*!< ECRCGE (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_ADVECC_ECRCCC_Pos                (7UL)          /*!< ECRCCC (Bit 7)                                        */
+ #define R_PCIE0_PCI_RC_ADVECC_ECRCCC_Msk                (0x80UL)       /*!< ECRCCC (Bitfield-Mask: 0x01)                          */
+ #define R_PCIE0_PCI_RC_ADVECC_ECRCCE_Pos                (8UL)          /*!< ECRCCE (Bit 8)                                        */
+ #define R_PCIE0_PCI_RC_ADVECC_ECRCCE_Msk                (0x100UL)      /*!< ECRCCE (Bitfield-Mask: 0x01)                          */
+/* ====================================================  PCI_EP_HLOG0_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_HLOG0_F0_HTLPE0_Pos              (0UL)          /*!< HTLPE0 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_HLOG0_F0_HTLPE0_Msk              (0xffffffffUL) /*!< HTLPE0 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_EP_HLOG0_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_HLOG0_F1_HTLPE0_Pos              (0UL)          /*!< HTLPE0 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_HLOG0_F1_HTLPE0_Msk              (0xffffffffUL) /*!< HTLPE0 (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  PCI_RC_HLOG0  ====================================================== */
+ #define R_PCIE0_PCI_RC_HLOG0_HTLPE0_Pos                 (0UL)          /*!< HTLPE0 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_HLOG0_HTLPE0_Msk                 (0xffffffffUL) /*!< HTLPE0 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_EP_HLOG1_Fi  ==================================================== */
+ #define R_PCIE0_PCI_EP_HLOG1_Fi_HTLPE1_Pos              (0UL)          /*!< HTLPE1 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_HLOG1_Fi_HTLPE1_Msk              (0xffffffffUL) /*!< HTLPE1 (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  PCI_RC_HLOG1  ====================================================== */
+ #define R_PCIE0_PCI_RC_HLOG1_HTLPE1_Pos                 (0UL)          /*!< HTLPE1 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_HLOG1_HTLPE1_Msk                 (0xffffffffUL) /*!< HTLPE1 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_EP_HLOG2_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_HLOG2_F0_HTLPE2_Pos              (0UL)          /*!< HTLPE2 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_HLOG2_F0_HTLPE2_Msk              (0xffffffffUL) /*!< HTLPE2 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_EP_HLOG2_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_HLOG2_F1_HTLPE2_Pos              (0UL)          /*!< HTLPE2 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_HLOG2_F1_HTLPE2_Msk              (0xffffffffUL) /*!< HTLPE2 (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  PCI_RC_HLOG2  ====================================================== */
+ #define R_PCIE0_PCI_RC_HLOG2_HTLPE2_Pos                 (0UL)          /*!< HTLPE2 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_HLOG2_HTLPE2_Msk                 (0xffffffffUL) /*!< HTLPE2 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_EP_HLOG3_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_HLOG3_F0_HTLPE3_Pos              (0UL)          /*!< HTLPE3 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_HLOG3_F0_HTLPE3_Msk              (0xffffffffUL) /*!< HTLPE3 (Bitfield-Mask: 0xffffffff)                    */
+/* ====================================================  PCI_EP_HLOG3_F1  ==================================================== */
+ #define R_PCIE0_PCI_EP_HLOG3_F1_HTLPE3_Pos              (0UL)          /*!< HTLPE3 (Bit 0)                                        */
+ #define R_PCIE0_PCI_EP_HLOG3_F1_HTLPE3_Msk              (0xffffffffUL) /*!< HTLPE3 (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  PCI_RC_HLOG3  ====================================================== */
+ #define R_PCIE0_PCI_RC_HLOG3_HTLPE3_Pos                 (0UL)          /*!< HTLPE3 (Bit 0)                                        */
+ #define R_PCIE0_PCI_RC_HLOG3_HTLPE3_Msk                 (0xffffffffUL) /*!< HTLPE3 (Bitfield-Mask: 0xffffffff)                    */
+/* =====================================================  PCI_RC_ROOTEC  ===================================================== */
+ #define R_PCIE0_PCI_RC_ROOTEC_CERE_Pos                  (0UL)          /*!< CERE (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_ROOTEC_CERE_Msk                  (0x1UL)        /*!< CERE (Bitfield-Mask: 0x01)                            */
+ #define R_PCIE0_PCI_RC_ROOTEC_NFERE_Pos                 (1UL)          /*!< NFERE (Bit 1)                                         */
+ #define R_PCIE0_PCI_RC_ROOTEC_NFERE_Msk                 (0x2UL)        /*!< NFERE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_ROOTEC_FERE_Pos                  (2UL)          /*!< FERE (Bit 2)                                          */
+ #define R_PCIE0_PCI_RC_ROOTEC_FERE_Msk                  (0x4UL)        /*!< FERE (Bitfield-Mask: 0x01)                            */
+/* =====================================================  PCI_RC_ROOTES  ===================================================== */
+ #define R_PCIE0_PCI_RC_ROOTES_ERRCORR_Pos               (0UL)          /*!< ERRCORR (Bit 0)                                       */
+ #define R_PCIE0_PCI_RC_ROOTES_ERRCORR_Msk               (0x1UL)        /*!< ERRCORR (Bitfield-Mask: 0x01)                         */
+ #define R_PCIE0_PCI_RC_ROOTES_MERRCORR_Pos              (1UL)          /*!< MERRCORR (Bit 1)                                      */
+ #define R_PCIE0_PCI_RC_ROOTES_MERRCORR_Msk              (0x2UL)        /*!< MERRCORR (Bitfield-Mask: 0x01)                        */
+ #define R_PCIE0_PCI_RC_ROOTES_ERRFATALNONFATALR_Pos     (2UL)          /*!< ERRFATALNONFATALR (Bit 2)                             */
+ #define R_PCIE0_PCI_RC_ROOTES_ERRFATALNONFATALR_Msk     (0x4UL)        /*!< ERRFATALNONFATALR (Bitfield-Mask: 0x01)               */
+ #define R_PCIE0_PCI_RC_ROOTES_MERRFATALNONFATALR_Pos    (3UL)          /*!< MERRFATALNONFATALR (Bit 3)                            */
+ #define R_PCIE0_PCI_RC_ROOTES_MERRFATALNONFATALR_Msk    (0x8UL)        /*!< MERRFATALNONFATALR (Bitfield-Mask: 0x01)              */
+ #define R_PCIE0_PCI_RC_ROOTES_FUF_Pos                   (4UL)          /*!< FUF (Bit 4)                                           */
+ #define R_PCIE0_PCI_RC_ROOTES_FUF_Msk                   (0x10UL)       /*!< FUF (Bitfield-Mask: 0x01)                             */
+ #define R_PCIE0_PCI_RC_ROOTES_NFEMR_Pos                 (5UL)          /*!< NFEMR (Bit 5)                                         */
+ #define R_PCIE0_PCI_RC_ROOTES_NFEMR_Msk                 (0x20UL)       /*!< NFEMR (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_ROOTES_FEMR_Pos                  (6UL)          /*!< FEMR (Bit 6)                                          */
+ #define R_PCIE0_PCI_RC_ROOTES_FEMR_Msk                  (0x40UL)       /*!< FEMR (Bitfield-Mask: 0x01)                            */
+/* =====================================================  PCI_RC_ERRSI  ====================================================== */
+ #define R_PCIE0_PCI_RC_ERRSI_ERRCORSI_Pos               (0UL)          /*!< ERRCORSI (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_ERRSI_ERRCORSI_Msk               (0xffffUL)     /*!< ERRCORSI (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_RC_ERRSI_ERRFATALNONFATALSI_Pos     (16UL)         /*!< ERRFATALNONFATALSI (Bit 16)                           */
+ #define R_PCIE0_PCI_RC_ERRSI_ERRFATALNONFATALSI_Msk     (0xffff0000UL) /*!< ERRFATALNONFATALSI (Bitfield-Mask: 0xffff)            */
+/* ==================================================  PCI_EP_DEVSNEXTC_F0  ================================================== */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F0_PCIEECID_Pos        (0UL)          /*!< PCIEECID (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F0_PCIEECID_Msk        (0xffffUL)     /*!< PCIEECID (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F0_CV_Pos              (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F0_CV_Msk              (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F0_NCO_Pos             (20UL)         /*!< NCO (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F0_NCO_Msk             (0xfff00000UL) /*!< NCO (Bitfield-Mask: 0xfff)                            */
+/* ==================================================  PCI_EP_DEVSNEXTC_F1  ================================================== */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F1_PCIEECID_Pos        (0UL)          /*!< PCIEECID (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F1_PCIEECID_Msk        (0xffffUL)     /*!< PCIEECID (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F1_CV_Pos              (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F1_CV_Msk              (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F1_NCO_Pos             (20UL)         /*!< NCO (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_DEVSNEXTC_F1_NCO_Msk             (0xfff00000UL) /*!< NCO (Bitfield-Mask: 0xfff)                            */
+/* ===================================================  PCI_RC_DEVSNEXTC  ==================================================== */
+ #define R_PCIE0_PCI_RC_DEVSNEXTC_PCIEECID_Pos           (0UL)          /*!< PCIEECID (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_DEVSNEXTC_PCIEECID_Msk           (0xffffUL)     /*!< PCIEECID (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_RC_DEVSNEXTC_CV_Pos                 (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_RC_DEVSNEXTC_CV_Msk                 (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_RC_DEVSNEXTC_NCO_Pos                (20UL)         /*!< NCO (Bit 20)                                          */
+ #define R_PCIE0_PCI_RC_DEVSNEXTC_NCO_Msk                (0xfff00000UL) /*!< NCO (Bitfield-Mask: 0xfff)                            */
+/* =====================================================  PCI_EP_SNL_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_SNL_F0_PCIEDSN_LDW_Pos           (0UL)          /*!< PCIEDSN_LDW (Bit 0)                                   */
+ #define R_PCIE0_PCI_EP_SNL_F0_PCIEDSN_LDW_Msk           (0xffffffffUL) /*!< PCIEDSN_LDW (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  PCI_EP_SNL_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_SNL_F1_PCIEDSN_LDW_Pos           (0UL)          /*!< PCIEDSN_LDW (Bit 0)                                   */
+ #define R_PCIE0_PCI_EP_SNL_F1_PCIEDSN_LDW_Msk           (0xffffffffUL) /*!< PCIEDSN_LDW (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  PCI_RC_SNL  ======================================================= */
+ #define R_PCIE0_PCI_RC_SNL_PCIEDSN_LDW_Pos              (0UL)          /*!< PCIEDSN_LDW (Bit 0)                                   */
+ #define R_PCIE0_PCI_RC_SNL_PCIEDSN_LDW_Msk              (0xffffffffUL) /*!< PCIEDSN_LDW (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  PCI_EP_SNU_F0  ===================================================== */
+ #define R_PCIE0_PCI_EP_SNU_F0_PCIEDSN_UDW_Pos           (0UL)          /*!< PCIEDSN_UDW (Bit 0)                                   */
+ #define R_PCIE0_PCI_EP_SNU_F0_PCIEDSN_UDW_Msk           (0xffffffffUL) /*!< PCIEDSN_UDW (Bitfield-Mask: 0xffffffff)               */
+/* =====================================================  PCI_EP_SNU_F1  ===================================================== */
+ #define R_PCIE0_PCI_EP_SNU_F1_PCIEDSN_UDW_Pos           (0UL)          /*!< PCIEDSN_UDW (Bit 0)                                   */
+ #define R_PCIE0_PCI_EP_SNU_F1_PCIEDSN_UDW_Msk           (0xffffffffUL) /*!< PCIEDSN_UDW (Bitfield-Mask: 0xffffffff)               */
+/* ======================================================  PCI_RC_SNU  ======================================================= */
+ #define R_PCIE0_PCI_RC_SNU_PCIEDSN_UDW_Pos              (0UL)          /*!< PCIEDSN_UDW (Bit 0)                                   */
+ #define R_PCIE0_PCI_RC_SNU_PCIEDSN_UDW_Msk              (0xffffffffUL) /*!< PCIEDSN_UDW (Bitfield-Mask: 0xffffffff)               */
+/* ===================================================  PCI_EP_SPEECH_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_SPEECH_F0_PCIEECID_Pos           (0UL)          /*!< PCIEECID (Bit 0)                                      */
+ #define R_PCIE0_PCI_EP_SPEECH_F0_PCIEECID_Msk           (0xffffUL)     /*!< PCIEECID (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_EP_SPEECH_F0_CV_Pos                 (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_EP_SPEECH_F0_CV_Msk                 (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_EP_SPEECH_F0_NCO_Pos                (20UL)         /*!< NCO (Bit 20)                                          */
+ #define R_PCIE0_PCI_EP_SPEECH_F0_NCO_Msk                (0xfff00000UL) /*!< NCO (Bitfield-Mask: 0xfff)                            */
+/* =====================================================  PCI_RC_SPEECH  ===================================================== */
+ #define R_PCIE0_PCI_RC_SPEECH_PCIEECID_Pos              (0UL)          /*!< PCIEECID (Bit 0)                                      */
+ #define R_PCIE0_PCI_RC_SPEECH_PCIEECID_Msk              (0xffffUL)     /*!< PCIEECID (Bitfield-Mask: 0xffff)                      */
+ #define R_PCIE0_PCI_RC_SPEECH_CV_Pos                    (16UL)         /*!< CV (Bit 16)                                           */
+ #define R_PCIE0_PCI_RC_SPEECH_CV_Msk                    (0xf0000UL)    /*!< CV (Bitfield-Mask: 0x0f)                              */
+ #define R_PCIE0_PCI_RC_SPEECH_NCO_Pos                   (20UL)         /*!< NCO (Bit 20)                                          */
+ #define R_PCIE0_PCI_RC_SPEECH_NCO_Msk                   (0xfff00000UL) /*!< NCO (Bitfield-Mask: 0xfff)                            */
+/* ====================================================  PCI_EP_LINC3_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_LINC3_F0_ELSKPOSGV_Pos           (9UL)          /*!< ELSKPOSGV (Bit 9)                                     */
+ #define R_PCIE0_PCI_EP_LINC3_F0_ELSKPOSGV_Msk           (0xfe00UL)     /*!< ELSKPOSGV (Bitfield-Mask: 0x7f)                       */
+/* =====================================================  PCI_RC_LINC3  ====================================================== */
+ #define R_PCIE0_PCI_RC_LINC3_PE_Pos                     (0UL)          /*!< PE (Bit 0)                                            */
+ #define R_PCIE0_PCI_RC_LINC3_PE_Msk                     (0x1UL)        /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_PCIE0_PCI_RC_LINC3_LERIE_Pos                  (1UL)          /*!< LERIE (Bit 1)                                         */
+ #define R_PCIE0_PCI_RC_LINC3_LERIE_Msk                  (0x2UL)        /*!< LERIE (Bitfield-Mask: 0x01)                           */
+ #define R_PCIE0_PCI_RC_LINC3_ELSKPOSGV_Pos              (9UL)          /*!< ELSKPOSGV (Bit 9)                                     */
+ #define R_PCIE0_PCI_RC_LINC3_ELSKPOSGV_Msk              (0xfe00UL)     /*!< ELSKPOSGV (Bitfield-Mask: 0x7f)                       */
+/* ====================================================  PCI_EP_LESTA_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_LESTA_F0_LESB_Pos                (0UL)          /*!< LESB (Bit 0)                                          */
+ #define R_PCIE0_PCI_EP_LESTA_F0_LESB_Msk                (0x3UL)        /*!< LESB (Bitfield-Mask: 0x03)                            */
+/* =====================================================  PCI_RC_LESTA  ====================================================== */
+ #define R_PCIE0_PCI_RC_LESTA_LESB_Pos                   (0UL)          /*!< LESB (Bit 0)                                          */
+ #define R_PCIE0_PCI_RC_LESTA_LESB_Msk                   (0xfUL)        /*!< LESB (Bitfield-Mask: 0x0f)                            */
+/* ===================================================  PCI_EP_LEQCTL_F0  ==================================================== */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_DPTP0_Pos              (0UL)          /*!< DPTP0 (Bit 0)                                         */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_DPTP0_Msk              (0xfUL)        /*!< DPTP0 (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_DPRPH0_Pos             (4UL)          /*!< DPRPH0 (Bit 4)                                        */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_DPRPH0_Msk             (0x70UL)       /*!< DPRPH0 (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_UPTP0_Pos              (8UL)          /*!< UPTP0 (Bit 8)                                         */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_UPTP0_Msk              (0xf00UL)      /*!< UPTP0 (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_UPRPH0_Pos             (12UL)         /*!< UPRPH0 (Bit 12)                                       */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_UPRPH0_Msk             (0x7000UL)     /*!< UPRPH0 (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_DPTP1_Pos              (16UL)         /*!< DPTP1 (Bit 16)                                        */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_DPTP1_Msk              (0xf0000UL)    /*!< DPTP1 (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_DPRPH1_Pos             (20UL)         /*!< DPRPH1 (Bit 20)                                       */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_DPRPH1_Msk             (0x700000UL)   /*!< DPRPH1 (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_UPTP1_Pos              (24UL)         /*!< UPTP1 (Bit 24)                                        */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_UPTP1_Msk              (0xf000000UL)  /*!< UPTP1 (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_UPRPH1_Pos             (28UL)         /*!< UPRPH1 (Bit 28)                                       */
+ #define R_PCIE0_PCI_EP_LEQCTL_F0_UPRPH1_Msk             (0x70000000UL) /*!< UPRPH1 (Bitfield-Mask: 0x07)                          */
+/* =====================================================  PCI_RC_LEQCTL  ===================================================== */
+ #define R_PCIE0_PCI_RC_LEQCTL_DPTP0_Pos                 (0UL)          /*!< DPTP0 (Bit 0)                                         */
+ #define R_PCIE0_PCI_RC_LEQCTL_DPTP0_Msk                 (0xfUL)        /*!< DPTP0 (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_LEQCTL_DPRPH0_Pos                (4UL)          /*!< DPRPH0 (Bit 4)                                        */
+ #define R_PCIE0_PCI_RC_LEQCTL_DPRPH0_Msk                (0x70UL)       /*!< DPRPH0 (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_LEQCTL_UPTP0_Pos                 (8UL)          /*!< UPTP0 (Bit 8)                                         */
+ #define R_PCIE0_PCI_RC_LEQCTL_UPTP0_Msk                 (0xf00UL)      /*!< UPTP0 (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_LEQCTL_UPRPH0_Pos                (12UL)         /*!< UPRPH0 (Bit 12)                                       */
+ #define R_PCIE0_PCI_RC_LEQCTL_UPRPH0_Msk                (0x7000UL)     /*!< UPRPH0 (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_LEQCTL_DPTP1_Pos                 (16UL)         /*!< DPTP1 (Bit 16)                                        */
+ #define R_PCIE0_PCI_RC_LEQCTL_DPTP1_Msk                 (0xf0000UL)    /*!< DPTP1 (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_LEQCTL_DPRPH1_Pos                (20UL)         /*!< DPRPH1 (Bit 20)                                       */
+ #define R_PCIE0_PCI_RC_LEQCTL_DPRPH1_Msk                (0x700000UL)   /*!< DPRPH1 (Bitfield-Mask: 0x07)                          */
+ #define R_PCIE0_PCI_RC_LEQCTL_UPTP1_Pos                 (24UL)         /*!< UPTP1 (Bit 24)                                        */
+ #define R_PCIE0_PCI_RC_LEQCTL_UPTP1_Msk                 (0xf000000UL)  /*!< UPTP1 (Bitfield-Mask: 0x0f)                           */
+ #define R_PCIE0_PCI_RC_LEQCTL_UPRPH1_Pos                (28UL)         /*!< UPRPH1 (Bit 28)                                       */
+ #define R_PCIE0_PCI_RC_LEQCTL_UPRPH1_Msk                (0x70000000UL) /*!< UPRPH1 (Bitfield-Mask: 0x07)                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_PCIE_PHY                                         ================ */
+/* =========================================================================================================================== */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif                                 /* R9A09G087_H */
+
+/** @} */ /* End of group R9A09G087 */
+
+/** @} */ /* End of group Renesas Electronics Corporation */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
new file mode 100644
index 00000000..727c5a8e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/* Ensure Renesas MCU variation definitions are included to ensure MCU
+ * specific register variations are handled correctly. */
+#ifndef BSP_FEATURE_H
+ #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h."
+#endif
+
+/** @addtogroup Renesas Electronics Corporation
+ * @{
+ */
+
+/** @addtogroup RZN2
+ * @{
+ */
+
+#ifndef RZN2_H
+ #define RZN2_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+ #include "../../../../mcu/all/bsp_compiler_support.h"
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5. */
+ #if defined(__ICCARM__)
+  #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+
+/* Macros already defined */
+  #else
+   #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__    1
+   #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__    1
+   #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+     #define __ARM_ARCH_6M__        1
+    #elif __ARM_ARCH == 7
+     #if __ARM_FEATURE_DSP
+      #define __ARM_ARCH_7EM__      1
+     #else
+      #define __ARM_ARCH_7M__       1
+     #endif
+    #endif                             /* __ARM_ARCH */
+   #endif                              /* __ARM_ARCH_PROFILE == 'M' */
+  #endif
+
+/* Alternative core deduction for older ICCARM's */
+  #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+   #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__         1
+   #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__         1
+   #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__        1
+   #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__    1
+   #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__    1
+   #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__    1
+   #elif defined(__ARM8R__) && (__CORE__ == __ARM8R__)
+    #define __ARM_ARCH_8R__         1
+   #elif defined(__ARM8A__) && (__CORE__ == __ARM8A__)
+    #define __ARM_ARCH_8A__         1
+   #else
+    #error "Unknown target."
+   #endif
+  #endif
+ #endif
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+/* IRQn_Type is generated as part of an FSP project. It can be found in vector_data.h. */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+ #if   __ARM_ARCH_7EM__
+  #define RENESAS_CORTEX_M4
+ #elif __ARM_ARCH_6M__
+  #define RENESAS_CORTEX_M0PLUS
+ #elif __ARM_ARCH_8M_BASE__
+  #define RENESAS_CORTEX_M23
+ #elif __ARM_ARCH_8M_MAIN__
+  #define RENESAS_CORTEX_M33
+ #elif __ARM_ARCH_8R__
+  #define RENESAS_CORTEX_R52
+ #elif __ARM_ARCH_8A__ || __ARM_ARCH_8A
+  #define RENESAS_CORTEX_A55
+ #else
+  #warning Unsupported Architecture
+ #endif
+
+ #if BSP_MCU_GROUP_RZN2L
+  #include "R9A07G084.h"
+ #elif BSP_MCU_GROUP_RZN2H
+  #include "R9A09G087.h"
+ #else
+  #warning Unsupported MCU
+ #endif
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif                                 /* RZN2_H */
+
+/** @} */ /* End of group RZN2 */
+
+/** @} */ /* End of group Renesas Electronics Corporation */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
new file mode 100644
index 00000000..68d60372
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
@@ -0,0 +1,44 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef SYSTEM_RENESAS_ARM_H
+ #define SYSTEM_RENESAS_ARM_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+ #include <stdint.h>
+
+extern uint32_t SystemCoreClock;       /** System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate(void);
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c
new file mode 100644
index 00000000..75cbe368
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c
@@ -0,0 +1,376 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_HACTLR_BIT_L                    (0xB783)     /* HACTLR EL1 access enable(0b1011 0111 1000 0011) */
+#define BSP_HCR_HCD_DISABLE                 (0x20000000) /* HCR.HCD = 1 : HVC disable */
+#define BSP_MODE_MASK                       (0x1F)       /* Bit mask for mode bits in CPSR */
+#define BSP_SVC_MODE                        (0x13)       /* Supervisor mode */
+
+#if defined(__ICCARM__)
+ #define BSP_IRQ_STACK_END_ADDRESS          __section_end(".irq_stack")
+ #define BSP_FIQ_STACK_END_ADDRESS          __section_end(".fiq_stack")
+ #define BSP_SVC_STACK_END_ADDRESS          __section_end(".svc_stack")
+ #define BSP_ABORT_STACK_END_ADDRESS        __section_end(".abt_stack")
+ #define BSP_UNDEFINED_STACK_END_ADDRESS    __section_end(".und_stack")
+ #define BSP_SYSTEM_STACK_END_ADDRESS       __section_end(".sys_stack")
+
+#elif defined(__GNUC__)
+ #define BSP_IRQ_STACK_END_ADDRESS          &__IrqStackLimit
+ #define BSP_FIQ_STACK_END_ADDRESS          &__FiqStackLimit
+ #define BSP_SVC_STACK_END_ADDRESS          &__SvcStackLimit
+ #define BSP_ABORT_STACK_END_ADDRESS        &__AbtStackLimit
+ #define BSP_UNDEFINED_STACK_END_ADDRESS    &__UndStackLimit
+ #define BSP_SYSTEM_STACK_END_ADDRESS       &__SysStackLimit
+
+#endif
+
+#if (0 == BSP_CFG_CORE_CR52)
+ #define BSP_IMP_BTCMREGIONR_MASK_L         (0x1FFC) /* Masked out BASEADDRESS and ENABLEELx bits(L) */
+ #define BSP_IMP_BTCMREGIONR_ENABLEEL_L     (0x0003) /* Set base address and enable EL2, EL1, EL0 access(L) */
+ #define BSP_IMP_BTCMREGIONR_ENABLEEL_H     (0x0010) /* Set base address and enable EL2, EL1, EL0 access(H) */
+
+/* Cortex-A55 Core0 access permission control. */
+ #define BSP_CA550_CTRL_ENABLE              (0x00000100)
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+#if defined(__ICCARM__)
+ #pragma section=".irq_stack"
+ #pragma section=".fiq_stack"
+ #pragma section=".svc_stack"
+ #pragma section=".abt_stack"
+ #pragma section=".und_stack"
+ #pragma section=".sys_stack"
+
+#elif defined(__GNUC__)
+extern void * __IrqStackLimit;
+extern void * __FiqStackLimit;
+extern void * __SvcStackLimit;
+extern void * __AbtStackLimit;
+extern void * __UndStackLimit;
+extern void * __SysStackLimit;
+
+#endif
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+#if __FPU_USED
+extern void bsp_fpu_advancedsimd_init(void);
+
+#endif
+
+#if (0 == BSP_CFG_CORE_CR52)
+extern void bsp_slavetcm_enable(void);
+
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+int32_t main(void);
+
+BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void system_init(void) BSP_PLACE_IN_SECTION(".loader_text");
+BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void stack_init(void);
+BSP_TARGET_ARM void                         fpu_slavetcm_init(void);
+
+BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void        __Vectors(void) BSP_PLACE_IN_SECTION(".intvec");
+__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void IRQ_Handler(void);
+__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void Reset_Handler(void) BSP_PLACE_IN_SECTION(".reset_handler");
+
+void Default_Handler(void);
+
+/* Stacks */
+BSP_DONT_REMOVE static uint8_t g_fiq_stack[BSP_CFG_STACK_FIQ_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
+BSP_PLACE_IN_SECTION(BSP_SECTION_FIQ_STACK);
+BSP_DONT_REMOVE static uint8_t g_irq_stack[BSP_CFG_STACK_IRQ_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
+BSP_PLACE_IN_SECTION(BSP_SECTION_IRQ_STACK);
+BSP_DONT_REMOVE static uint8_t g_abt_stack[BSP_CFG_STACK_ABT_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
+BSP_PLACE_IN_SECTION(BSP_SECTION_ABT_STACK);
+BSP_DONT_REMOVE static uint8_t g_und_stack[BSP_CFG_STACK_UND_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
+BSP_PLACE_IN_SECTION(BSP_SECTION_UND_STACK);
+BSP_DONT_REMOVE static uint8_t g_sys_stack[BSP_CFG_STACK_SYS_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
+BSP_PLACE_IN_SECTION(BSP_SECTION_SYS_STACK);
+BSP_DONT_REMOVE static uint8_t g_svc_stack[BSP_CFG_STACK_SVC_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
+BSP_PLACE_IN_SECTION(BSP_SECTION_SVC_STACK);
+
+/* Heap */
+#if (BSP_CFG_HEAP_BYTES > 0)
+
+BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \
+    BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP);
+#endif
+
+BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors (void)
+{
+    __asm volatile (
+        "    LDR pc,=Reset_Handler            \n"
+        "    LDR pc,=Undefined_Handler        \n"
+        "    LDR pc,=SVC_Handler              \n"
+        "    LDR pc,=Prefetch_Handler         \n"
+        "    LDR pc,=Abort_Handler            \n"
+        "    LDR pc,=Reserved_Handler         \n"
+        "    LDR pc,=IRQ_Handler              \n"
+        "    LDR pc,=FIQ_Handler              \n"
+        ::: "memory");
+}
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Default exception handler.
+ **********************************************************************************************************************/
+void Default_Handler (void)
+{
+    /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption
+     *  or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status
+     *  registers for more information.
+     */
+    BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
+}
+
+/*******************************************************************************************************************//**
+ * After boot processing, LSI starts executing here.
+ **********************************************************************************************************************/
+BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void system_init (void)
+{
+#if 1
+    __asm volatile (
+        "    mov   r0, #0                               \n"
+        "    movw  r1, #0xf07f                    \n"
+        "    movt  r1, #0x2fa                        \n"
+        "software_loop:                              \n"
+        "    adds  r0, #1                                 \n"
+        "    cmp   r0, r1                                 \n"
+        "    bne   software_loop                  \n"
+        ::: "memory");
+#endif
+    __asm volatile (
+        "set_hactlr:                              \n"
+        "    MOVW  r0, %[bsp_hactlr_bit_l]        \n" /* Set HACTLR bits(L) */
+        "    MOVT  r0, #0                         \n"
+        "    MCR   p15, #4, r0, c1, c0, #1        \n" /* Write r0 to HACTLR */
+        ::[bsp_hactlr_bit_l] "i" (BSP_HACTLR_BIT_L) : "memory");
+
+    __asm volatile (
+        "set_hcr:                                 \n"
+        "    MRC   p15, #4, r1, c1, c1, #0        \n" /* Read Hyp Configuration Register */
+        "    ORR   r1, r1, %[bsp_hcr_hcd_disable] \n" /* HVC instruction disable */
+        "    MCR   p15, #4, r1, c1, c1, #0        \n" /* Write Hyp Configuration Register */
+        ::[bsp_hcr_hcd_disable] "i" (BSP_HCR_HCD_DISABLE) : "memory");
+
+    __asm volatile (
+        "set_vbar:                                \n"
+        "    LDR   r0, =__Vectors                 \n"
+        "    MCR   p15, #0, r0, c12, c0, #0       \n" /* Write r0 to VBAR */
+        ::: "memory");
+
+#if (0 == BSP_CFG_CORE_CR52) || (1 == BSP_FEATURE_BSP_HAS_CR52_CPU1_LLPP)
+    __asm volatile (
+        "LLPP_access_enable:                      \n"
+
+        /* Enable PERIPHPREGIONR (LLPP) */
+        "    MRC   p15, #0, r1, c15, c0,#0        \n" /* PERIPHPREGIONR */
+        "    ORR   r1, r1, #(0x1 << 1)            \n" /* Enable PERIPHPREGIONR EL2 */
+        "    ORR   r1, r1, #(0x1)                 \n" /* Enable PERIPHPREGIONR EL1 and EL0 */
+        "    DSB                                  \n" /* Ensuring memory access complete */
+        "    MCR   p15, #0, r1, c15, c0,#0        \n" /* PERIPHREGIONR */
+        "    ISB                                  \n" /* Ensuring Context-changing */
+        ::: "memory");
+#endif
+
+    __asm volatile (
+        "cpsr_save:                               \n"
+        "    MRS   r0, CPSR                       \n" /* Original PSR value */
+        "    BIC   r0, r0, %[bsp_mode_mask]       \n" /* Clear the mode bits */
+        "    ORR   r0, r0, %[bsp_svc_mode]        \n" /* Set SVC mode bits */
+        "    MSR   SPSR_hyp, r0                   \n"
+        ::[bsp_mode_mask] "i" (BSP_MODE_MASK), [bsp_svc_mode] "i" (BSP_SVC_MODE) : "memory");
+
+    __asm volatile (
+        "exception_return:                        \n"
+        "    LDR   r1, =stack_init                \n"
+        "    MSR   ELR_hyp, r1                    \n"
+        "    ERET                                 \n" /* Branch to stack_init and enter EL1 */
+        ::: "memory");
+}
+
+/** @} (end addtogroup BSP_MCU) */
+
+#if defined(__ICCARM__)
+ #define BSP_SYSTEMINIT_B_INSTRUCTION    SystemInit();
+
+ #define WEAK_REF_ATTRIBUTE
+
+ #pragma weak Undefined_Handler     = Default_Handler
+ #pragma weak SVC_Handler           = Default_Handler
+ #pragma weak Prefetch_Handler      = Default_Handler
+ #pragma weak Abort_Handler         = Default_Handler
+ #pragma weak Reserved_Handler      = Default_Handler
+ #pragma weak FIQ_Handler           = Default_Handler
+#elif defined(__GNUC__)
+
+ #define BSP_SYSTEMINIT_B_INSTRUCTION    __asm volatile ("B SystemInit");
+
+ #define WEAK_REF_ATTRIBUTE              __attribute__((weak, alias("Default_Handler")))
+#endif
+
+void Undefined_Handler(void) WEAK_REF_ATTRIBUTE;
+void SVC_Handler(void) WEAK_REF_ATTRIBUTE;
+void Prefetch_Handler(void) WEAK_REF_ATTRIBUTE;
+void Abort_Handler(void) WEAK_REF_ATTRIBUTE;
+void Reserved_Handler(void) WEAK_REF_ATTRIBUTE;
+void FIQ_Handler(void) WEAK_REF_ATTRIBUTE;
+
+/*******************************************************************************************************************//**
+ * After system_init, EL1 settings start here.
+ **********************************************************************************************************************/
+BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void stack_init (void)
+{
+    __asm volatile (
+        "stack_initialization:                           \n"
+
+        /* Stack setting for EL1 */
+        "    CPS  #17                                    \n" /* FIQ mode */
+        "    MOV  sp, %[bsp_fiq_stack_end_address]       \n"
+        "    CPS  #18                                    \n" /* IRQ mode */
+        "    MOV  sp, %[bsp_irq_stack_end_address]       \n"
+        "    CPS  #23                                    \n" /* Abort mode */
+        "    MOV  sp, %[bsp_abort_stack_end_address]     \n"
+        "    CPS  #27                                    \n" /* Undefined mode */
+        "    MOV  sp, %[bsp_undefined_stack_end_address] \n"
+        "    CPS  #31                                    \n" /* System mode */
+        "    MOV  sp, %[bsp_system_stack_end_address]    \n"
+        "    CPS  #19                                    \n" /* SVC mode */
+        "    MOV  sp, %[bsp_svc_stack_end_address]       \n"
+
+        "    B    fpu_slavetcm_init                      \n" /* Branch to fpu_slavetcm_init */
+        ::[bsp_fiq_stack_end_address] "r" (BSP_FIQ_STACK_END_ADDRESS),
+        [bsp_irq_stack_end_address] "r" (BSP_IRQ_STACK_END_ADDRESS),
+        [bsp_abort_stack_end_address] "r" (BSP_ABORT_STACK_END_ADDRESS),
+        [bsp_undefined_stack_end_address] "r" (BSP_UNDEFINED_STACK_END_ADDRESS),
+        [bsp_system_stack_end_address] "r" (BSP_SYSTEM_STACK_END_ADDRESS),
+        [bsp_svc_stack_end_address] "r" (BSP_SVC_STACK_END_ADDRESS) : "memory");
+}
+
+/*******************************************************************************************************************//**
+ * Enable FPU and enable privileged/unprivileged access for TCM.
+ **********************************************************************************************************************/
+BSP_TARGET_ARM void fpu_slavetcm_init (void)
+{
+#if __FPU_USED
+
+    /* Initialize FPU and Advanced SIMD setting */
+    bsp_fpu_advancedsimd_init();
+#endif
+
+#if (0 == BSP_CFG_CORE_CR52)
+
+    /* Enable SLAVEPCTLR TCM access lvl slaves */
+    bsp_slavetcm_enable();
+#endif
+
+#if defined(BSP_MCU_GROUP_RZN2H)
+ #if (0 == BSP_CFG_CORE_CR52)
+
+    /* Permit access to the Master-MPU related registers of Cortex-A55 Core0. */
+    R_MPU_AC->CPU_CTRL |= BSP_CA550_CTRL_ENABLE;
+ #endif
+#endif
+
+    BSP_SYSTEMINIT_B_INSTRUCTION
+}
+
+__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void IRQ_Handler (void)
+{
+    __asm volatile (
+        "SUB     lr, lr, #4                       \n"
+        "SRSDB   sp!, #31                         \n" /* Store LR_irq and SPSR_irq in system mode stack. */
+        "CPS     #31                              \n" /* Switch to system mode. */
+        "PUSH    {r0-r3, r12}                     \n" /* Store other AAPCS registers. */
+
+#if __FPU_USED
+        "VMRS    r0, FPSCR                        \n"
+        "STMDB   sp!, {r0}                        \n" /* Store FPSCR register. */
+        "SUB     sp, sp, #4                       \n"
+        "VPUSH   {d0-d15}                         \n" /* Store FPU registers. */
+        "VPUSH   {d16-d31}                        \n" /* Store FPU registers. */
+#endif
+
+        "MRC     p15, #0, r3, c12, c12, #2        \n" /* Read HPPIR1 to r3. */
+        "MRC     p15, #0, r0, c12, c12, #0        \n" /* Read IAR1 to r0. */
+
+        "PUSH    {r0}                             \n" /* Store the INTID. */
+        "MOV     r1, sp                           \n" /* Make alignment for stack. */
+        "AND     r1, r1, #4                       \n"
+        "SUB     sp, sp, r1                       \n"
+        "PUSH    {r1, lr}                         \n"
+
+        "LDR     r1,=bsp_common_interrupt_handler \n"
+        "BLX     r1                               \n" /* Jump to bsp_common_interrupt_handler, First argument (r0) = ICC_IAR1 read value. */
+
+        "POP     {r1, lr}                         \n"
+        "ADD     sp, sp, r1                       \n"
+        "POP     {r0}                             \n" /* Restore the INTID to r0. */
+
+        "MCR     p15, #0, r0, c12, c12, #1        \n" /* Write INTID to EOIR. */
+
+#if __FPU_USED
+        "VPOP    {d16-d31}                        \n" /* Restore FPU registers. */
+        "VPOP    {d0-d15}                         \n" /* Restore FPU registers. */
+        "ADD     sp, sp, #4                       \n"
+        "POP     {r0}                             \n"
+        "VMSR    FPSCR, r0                        \n" /* Restore FPSCR register. */
+#endif
+
+        "POP     {r0-r3, r12}                     \n" /* Restore registers. */
+        "RFEIA   sp!                              \n" /* Return from system mode tack using RFE. */
+        ::: "memory");
+}
+
+__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void Reset_Handler (void)
+{
+#if (0 == BSP_CFG_CORE_CR52)
+
+    /* Enable access to BTCM */
+    __asm volatile (
+        "set_IMP_BTCMREGIONR:                            \n"
+        "   MRC   p15, #0, r0, c9, c1, #1                \n" /* Read IMP_BTCMREGIONR to r0 */
+        "   MOVW  r1, %[bsp_imp_btcmregionr_mask_l]      \n"
+        "   MOVT  r1, #0                                 \n"
+        "   AND   r0, r0, r1                             \n" /* Masked out BASEADDRESS and ENABLEELx bits */
+        "   MOVW  r1, %[bsp_imp_btcmregionr_enableel_l]  \n"
+        "   MOVT  r1, %[bsp_imp_btcmregionr_enableel_h]  \n"
+        "   ORR   r0, r0, r1                             \n" /* Set base address and enable EL2, EL1, EL0 access */
+        "   DSB                                          \n" /* Ensuring memory access complete */
+
+        "   MCR   p15, #0, r0, c9, c1, #1                \n" /* Write r0 to IMP_BTCMREGIONR */
+        "   ISB                                          \n" /* Ensuring Context-changing */
+        ::[bsp_imp_btcmregionr_mask_l] "i" (BSP_IMP_BTCMREGIONR_MASK_L),
+        [bsp_imp_btcmregionr_enableel_l] "i" (BSP_IMP_BTCMREGIONR_ENABLEEL_L),
+        [bsp_imp_btcmregionr_enableel_h] "i" (BSP_IMP_BTCMREGIONR_ENABLEEL_H) : "memory");
+#endif
+
+    /* Branch to system_init */
+    __asm volatile ("B system_init");
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c
new file mode 100644
index 00000000..9ea91848
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c
@@ -0,0 +1,699 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include <string.h>
+#include "bsp_api.h"
+
+#include "../../../../../mcu/all/bsp_clocks.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_CPCAR_CP_ENABLE             (0x00F00000)
+#define BSP_FPEXC_EN_ENABLE             (0x40000000)
+#define BSP_TCM_ALL_ACCESS_ENABLE       (0x00000003)
+
+#define BSP_PRIORITY_MASK               BSP_FEATURE_BSP_IRQ_PRIORITY_MASK /* Priority mask value for GIC */
+#define BSP_ENABLE_GROUP_INT            (0x00000001)                      /* Enable Group1 interrupt value */
+#define BSP_ICC_CTLR                    (0x00000001)                      /* ICC_BPR0 is used for Group1 interrupt */
+
+#define BSP_BG_REGION_ENABLE            (0x00020000)                      /* Enable EL1 background region */
+#define BSP_BG_REGION_DISABLE           (0x00000000)                      /* Disable EL1 background region */
+#define BSP_SCTLR_BR_BIT                (BSP_CFG_SCTLR_BR_BIT)            /* Enable EL1 background region */
+
+#define BSP_ICACHE_ENABLE               (0x00001000)
+#define BSP_ICACHE_DISABLE              (0x00000000)
+
+#define BSP_DATACACHE_ENABLE            (0x00000004)
+#define BSP_DATACACHE_DISABLE           (0x00000000)
+
+#define BSP_WRITE_THROUGH_TRANSIENT     (0x0003) /* Normal-Memory: Write-Through transient */
+#define BSP_NON_CACHEABLE               (0x0004) /* Normal-Memory: Non-Cacheable */
+#define BSP_WRITE_BACK_TRANSIENT        (0x0007) /* Normal-Memory: Write-Back transient */
+#define BSP_WRITE_NON_THROUGH           (0x000B) /* Normal-Memory: Write-Through non-transient. */
+#define BSP_WRITE_BACK_NON_TRANSIENT    (0x000F) /* Normal-Memory: Write-Back non-transient. */
+
+#define BSP_TYPE_NORMAL_MEMORY          (0)
+#define BSP_TYPE_DEVICE_MEMORY          (1)
+
+#define BSP_READ_ALLOCATE               (0xFFFF) /* Read allocate (bit1=1, "1" mask except bit1) */
+#define BSP_READ_NOT_ALLOCATE           (0xFFFD) /* Read not allocate (bit1=0, "1" mask except bit1) */
+#define BSP_WRITE_ALLOCATE              (0xFFFF) /* Write allocate (bit0=1, "1" mask except bit0) */
+#define BSP_WRITE_NOT_ALLOCATE          (0xFFFE) /* Write not allocate (bit0=0, "1" mask except bit0) */
+
+#define BSP_DEVICE_NGNRNE               (0x0000) /* Device-nGnRnE memory */
+#define BSP_DEVICE_NGNRE                (0x0004) /* Device-nGnRE memory */
+#define BSP_DEVICE_NGRE                 (0x0008) /* Device-nGRE memory */
+#define BSP_DEVICE_GRE                  (0x000C) /* Device-GRE memory */
+
+#define BSP_OFFSET_ATTR0_INNER          (0)
+#define BSP_OFFSET_ATTR0_OUTER          (4)
+#define BSP_OFFSET_ATTR0_DEVICE         (0)
+#define BSP_OFFSET_ATTR1_INNER          (8)
+#define BSP_OFFSET_ATTR1_OUTER          (12)
+#define BSP_OFFSET_ATTR1_DEVICE         (8)
+
+#define BSP_OFFSET_ATTR2_INNER          (16)
+#define BSP_OFFSET_ATTR2_OUTER          (20)
+#define BSP_OFFSET_ATTR2_DEVICE         (16)
+#define BSP_OFFSET_ATTR3_INNER          (24)
+#define BSP_OFFSET_ATTR3_OUTER          (28)
+#define BSP_OFFSET_ATTR3_DEVICE         (24)
+
+#define BSP_OFFSET_ATTR4_INNER          (0)
+#define BSP_OFFSET_ATTR4_OUTER          (4)
+#define BSP_OFFSET_ATTR4_DEVICE         (0)
+#define BSP_OFFSET_ATTR5_INNER          (8)
+#define BSP_OFFSET_ATTR5_OUTER          (12)
+#define BSP_OFFSET_ATTR5_DEVICE         (8)
+
+#define BSP_OFFSET_ATTR6_INNER          (16)
+#define BSP_OFFSET_ATTR6_OUTER          (20)
+#define BSP_OFFSET_ATTR6_DEVICE         (16)
+#define BSP_OFFSET_ATTR7_INNER          (24)
+#define BSP_OFFSET_ATTR7_OUTER          (28)
+#define BSP_OFFSET_ATTR7_DEVICE         (24)
+
+#define BSP_NON_SHAREABLE               (0 << 3)
+#define BSP_OUTER_SHAREABLE             (2 << 3)
+#define BSP_INNER_SHAREABLE             (3 << 3)
+#define BSP_EL1RW_EL0NO                 (0 << 1)
+#define BSP_EL1RW_EL0RW                 (1 << 1)
+#define BSP_EL1RO_EL0NO                 (2 << 1)
+#define BSP_EL1RO_EL0RO                 (3 << 1)
+#define BSP_EXECUTE_ENABLE              (0)
+#define BSP_EXECUTE_NEVER               (1)
+#define BSP_REGION_DISABLE              (0)
+#define BSP_REGION_ENABLE               (1)
+#define BSP_ATTRINDEX0                  (0 << 1)
+#define BSP_ATTRINDEX1                  (1 << 1)
+#define BSP_ATTRINDEX2                  (2 << 1)
+#define BSP_ATTRINDEX3                  (3 << 1)
+#define BSP_ATTRINDEX4                  (4 << 1)
+#define BSP_ATTRINDEX5                  (5 << 1)
+#define BSP_ATTRINDEX6                  (6 << 1)
+#define BSP_ATTRINDEX7                  (7 << 1)
+
+/* Attr0 */
+#if BSP_CFG_CPU_MPU_ATTR0_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
+ #define BSP_CFG_CPU_MPU_ATTR0          (BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE << BSP_OFFSET_ATTR0_DEVICE)
+#else                                                    /* MEMORY TYPE == NORMAL MEMORY */
+ #define BSP_CFG_CPU_MPU_ATTR0          (((BSP_CFG_CPU_MPU_ATTR0_INNER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR0_INNER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE)) << BSP_OFFSET_ATTR0_INNER) | \
+                                         ((BSP_CFG_CPU_MPU_ATTR0_OUTER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE)) << BSP_OFFSET_ATTR0_OUTER))
+#endif                                                   /* BSP_CFG_CPU_MPU_ATTR0_TYPE */
+
+/* Attr1 */
+#if BSP_CFG_CPU_MPU_ATTR1_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
+ #define BSP_CFG_CPU_MPU_ATTR1          (BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE << BSP_OFFSET_ATTR1_DEVICE)
+#else                                                    /* MEMORY TYPE == NORMAL MEMORY */
+ #define BSP_CFG_CPU_MPU_ATTR1          (((BSP_CFG_CPU_MPU_ATTR1_INNER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR1_INNER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE)) << BSP_OFFSET_ATTR1_INNER) | \
+                                         ((BSP_CFG_CPU_MPU_ATTR1_OUTER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE)) << BSP_OFFSET_ATTR1_OUTER))
+#endif                                                   /* BSP_CFG_CPU_MPU_ATTR1_TYPE */
+
+/* Attr2 */
+#if BSP_CFG_CPU_MPU_ATTR2_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
+ #define BSP_CFG_CPU_MPU_ATTR2          (BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE << BSP_OFFSET_ATTR2_DEVICE)
+#else                                                    /* MEMORY TYPE == NORMAL MEMORY */
+ #define BSP_CFG_CPU_MPU_ATTR2          (((BSP_CFG_CPU_MPU_ATTR2_INNER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR2_INNER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE)) << BSP_OFFSET_ATTR2_INNER) | \
+                                         ((BSP_CFG_CPU_MPU_ATTR2_OUTER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE)) << BSP_OFFSET_ATTR2_OUTER))
+#endif                                                   /* BSP_CFG_CPU_MPU_ATTR2_TYPE */
+
+/* Attr3 */
+#if BSP_CFG_CPU_MPU_ATTR3_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
+ #define BSP_CFG_CPU_MPU_ATTR3          (BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE << BSP_OFFSET_ATTR3_DEVICE)
+#else                                                    /* MEMORY TYPE == NORMAL MEMORY */
+ #define BSP_CFG_CPU_MPU_ATTR3          (((BSP_CFG_CPU_MPU_ATTR3_INNER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR3_INNER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE)) << BSP_OFFSET_ATTR3_INNER) | \
+                                         ((BSP_CFG_CPU_MPU_ATTR3_OUTER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE)) << BSP_OFFSET_ATTR3_OUTER))
+#endif                                                   /* BSP_CFG_CPU_MPU_ATTR3_TYPE */
+
+/* Attr4 */
+#if BSP_CFG_CPU_MPU_ATTR4_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
+ #define BSP_CFG_CPU_MPU_ATTR4          (BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE << BSP_OFFSET_ATTR4_DEVICE)
+#else                                                    /* MEMORY TYPE == NORMAL MEMORY */
+ #define BSP_CFG_CPU_MPU_ATTR4          (((BSP_CFG_CPU_MPU_ATTR4_INNER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR4_INNER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE)) << BSP_OFFSET_ATTR4_INNER) | \
+                                         ((BSP_CFG_CPU_MPU_ATTR4_OUTER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE)) << BSP_OFFSET_ATTR4_OUTER))
+#endif                                                   /* BSP_CFG_CPU_MPU_ATTR4_TYPE */
+
+/* Attr5 */
+#if BSP_CFG_CPU_MPU_ATTR5_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
+ #define BSP_CFG_CPU_MPU_ATTR5          (BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE << BSP_OFFSET_ATTR5_DEVICE)
+#else                                                    /* MEMORY TYPE == NORMAL MEMORY */
+ #define BSP_CFG_CPU_MPU_ATTR5          (((BSP_CFG_CPU_MPU_ATTR5_INNER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR5_INNER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE)) << BSP_OFFSET_ATTR5_INNER) | \
+                                         ((BSP_CFG_CPU_MPU_ATTR5_OUTER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE)) << BSP_OFFSET_ATTR5_OUTER))
+#endif                                                   /* BSP_CFG_CPU_MPU_ATTR5_TYPE */
+
+/* Attr6 */
+#if BSP_CFG_CPU_MPU_ATTR6_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
+ #define BSP_CFG_CPU_MPU_ATTR6          (BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE << BSP_OFFSET_ATTR6_DEVICE)
+#else                                                    /* MEMORY TYPE == NORMAL MEMORY */
+ #define BSP_CFG_CPU_MPU_ATTR6          (((BSP_CFG_CPU_MPU_ATTR6_INNER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR6_INNER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE)) << BSP_OFFSET_ATTR6_INNER) | \
+                                         ((BSP_CFG_CPU_MPU_ATTR6_OUTER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE)) << BSP_OFFSET_ATTR6_OUTER))
+#endif                                                   /* BSP_CFG_CPU_MPU_ATTR6_TYPE */
+
+/* Attr7 */
+#if BSP_CFG_CPU_MPU_ATTR7_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
+ #define BSP_CFG_CPU_MPU_ATTR7          (BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE << BSP_OFFSET_ATTR7_DEVICE)
+#else                                                    /* MEMORY TYPE == NORMAL MEMORY */
+ #define BSP_CFG_CPU_MPU_ATTR7          (((BSP_CFG_CPU_MPU_ATTR7_INNER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR7_INNER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE)) << BSP_OFFSET_ATTR7_INNER) | \
+                                         ((BSP_CFG_CPU_MPU_ATTR7_OUTER &                                     \
+                                           (BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) &                              \
+                                           (BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE)) << BSP_OFFSET_ATTR7_OUTER))
+#endif                                 /* BSP_CFG_CPU_MPU_ATTR7_TYPE */
+
+#define ATTR_3_2_1_0                    (BSP_CFG_CPU_MPU_ATTR3 | BSP_CFG_CPU_MPU_ATTR2 | BSP_CFG_CPU_MPU_ATTR1 | \
+                                         BSP_CFG_CPU_MPU_ATTR0)
+#define ATTR_7_6_5_4                    (BSP_CFG_CPU_MPU_ATTR7 | BSP_CFG_CPU_MPU_ATTR6 | BSP_CFG_CPU_MPU_ATTR5 | \
+                                         BSP_CFG_CPU_MPU_ATTR4)
+
+#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR0_TYPE)
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_INNER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_OUTER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+#endif
+
+#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR1_TYPE)
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_INNER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_OUTER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+#endif
+
+#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR2_TYPE)
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_INNER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_OUTER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+#endif
+
+#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR3_TYPE)
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_INNER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_OUTER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+#endif
+
+#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR4_TYPE)
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_INNER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_OUTER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+#endif
+
+#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR5_TYPE)
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_INNER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_OUTER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+#endif
+
+#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR6_TYPE)
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_INNER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_OUTER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+#endif
+
+#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR7_TYPE)
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_INNER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+ #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_OUTER) && \
+    (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) &&    \
+    (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE))
+  #error "If you select Write-Through transient, set either Read or Write to allocate."
+ #endif
+#endif
+
+/* Region template */
+#define EL1_MPU_REGION_ADDRESS_MASK                         (0xFFFFFFC0)
+
+#if (1 != _RZN_ORDINAL) && (0 == BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA)
+ #define EL1_MPU_REGION_ATTRIBUTE_MASK                      (0x3F)
+ #define EL1_MPU_REGION_SYSTEMRAM_CACHE_ADDRESS_START       (0x10000000)
+ #define EL1_MPU_REGION_SYSTEMRAM_CACHE_ADDRESS_END         (0x100FFFC0)
+ #define EL1_MPU_REGION_SYSTEMRAM_NONCACHE_ADDRESS_START    (0x10100000)
+ #define EL1_MPU_REGION_SYSTEMRAM_NONCACHE_ADDRESS_END      (0x101FFFC0)
+
+#endif
+
+#define EL1_MPU_REGION_COUNT                                (24)
+
+#define EL1_MPU_REGIONXX_BASE(n)     ((BSP_CFG_EL1_MPU_REGION ## n ## _BASE & EL1_MPU_REGION_ADDRESS_MASK) | \
+                                      BSP_CFG_EL1_MPU_REGION ## n ## _SH |                                   \
+                                      BSP_CFG_EL1_MPU_REGION ## n ## _AP |                                   \
+                                      BSP_CFG_EL1_MPU_REGION ## n ## _XN)
+
+#define EL1_MPU_REGIONXX_LIMIT(n)    ((BSP_CFG_EL1_MPU_REGION ## n ## _LIMIT & EL1_MPU_REGION_ADDRESS_MASK) | \
+                                      BSP_CFG_EL1_MPU_REGION ## n ## _ATTRINDEX |                             \
+                                      BSP_CFG_EL1_MPU_REGION ## n ## _ENABLE)
+
+/* region 0 */
+#define EL1_MPU_REGION00_BASE     EL1_MPU_REGIONXX_BASE(00)
+#define EL1_MPU_REGION00_LIMIT    EL1_MPU_REGIONXX_LIMIT(00)
+
+/* region 1 */
+#define EL1_MPU_REGION01_BASE     EL1_MPU_REGIONXX_BASE(01)
+#define EL1_MPU_REGION01_LIMIT    EL1_MPU_REGIONXX_LIMIT(01)
+
+/* region 2 */
+#define EL1_MPU_REGION02_BASE     EL1_MPU_REGIONXX_BASE(02)
+#define EL1_MPU_REGION02_LIMIT    EL1_MPU_REGIONXX_LIMIT(02)
+
+/* region 3 */
+#define EL1_MPU_REGION03_BASE     EL1_MPU_REGIONXX_BASE(03)
+#define EL1_MPU_REGION03_LIMIT    EL1_MPU_REGIONXX_LIMIT(03)
+
+/* region 4 */
+#define EL1_MPU_REGION04_BASE     EL1_MPU_REGIONXX_BASE(04)
+#define EL1_MPU_REGION04_LIMIT    EL1_MPU_REGIONXX_LIMIT(04)
+
+/* region 5 */
+#define EL1_MPU_REGION05_BASE     EL1_MPU_REGIONXX_BASE(05)
+#define EL1_MPU_REGION05_LIMIT    EL1_MPU_REGIONXX_LIMIT(05)
+
+/* region 6 */
+#define EL1_MPU_REGION06_BASE     EL1_MPU_REGIONXX_BASE(06)
+#define EL1_MPU_REGION06_LIMIT    EL1_MPU_REGIONXX_LIMIT(06)
+
+/* region 7 */
+#define EL1_MPU_REGION07_BASE     EL1_MPU_REGIONXX_BASE(07)
+#define EL1_MPU_REGION07_LIMIT    EL1_MPU_REGIONXX_LIMIT(07)
+
+/* region 8 */
+#define EL1_MPU_REGION08_BASE     EL1_MPU_REGIONXX_BASE(08)
+#define EL1_MPU_REGION08_LIMIT    EL1_MPU_REGIONXX_LIMIT(08)
+
+/* region 9 */
+#define EL1_MPU_REGION09_BASE     EL1_MPU_REGIONXX_BASE(09)
+#define EL1_MPU_REGION09_LIMIT    EL1_MPU_REGIONXX_LIMIT(09)
+
+/* region 10 */
+#define EL1_MPU_REGION10_BASE     EL1_MPU_REGIONXX_BASE(10)
+#define EL1_MPU_REGION10_LIMIT    EL1_MPU_REGIONXX_LIMIT(10)
+
+/* region 11 */
+#define EL1_MPU_REGION11_BASE     EL1_MPU_REGIONXX_BASE(11)
+#define EL1_MPU_REGION11_LIMIT    EL1_MPU_REGIONXX_LIMIT(11)
+
+/* region 12 */
+#define EL1_MPU_REGION12_BASE     EL1_MPU_REGIONXX_BASE(12)
+#define EL1_MPU_REGION12_LIMIT    EL1_MPU_REGIONXX_LIMIT(12)
+
+/* region 13 */
+#define EL1_MPU_REGION13_BASE     EL1_MPU_REGIONXX_BASE(13)
+#define EL1_MPU_REGION13_LIMIT    EL1_MPU_REGIONXX_LIMIT(13)
+
+/* region 14 */
+#define EL1_MPU_REGION14_BASE     EL1_MPU_REGIONXX_BASE(14)
+#define EL1_MPU_REGION14_LIMIT    EL1_MPU_REGIONXX_LIMIT(14)
+
+/* region 15 */
+#define EL1_MPU_REGION15_BASE     EL1_MPU_REGIONXX_BASE(15)
+#define EL1_MPU_REGION15_LIMIT    EL1_MPU_REGIONXX_LIMIT(15)
+
+/* region 16 */
+#define EL1_MPU_REGION16_BASE     EL1_MPU_REGIONXX_BASE(16)
+#define EL1_MPU_REGION16_LIMIT    EL1_MPU_REGIONXX_LIMIT(16)
+
+/* region 17 */
+#define EL1_MPU_REGION17_BASE     EL1_MPU_REGIONXX_BASE(17)
+#define EL1_MPU_REGION17_LIMIT    EL1_MPU_REGIONXX_LIMIT(17)
+
+/* region 18 */
+#define EL1_MPU_REGION18_BASE     EL1_MPU_REGIONXX_BASE(18)
+#define EL1_MPU_REGION18_LIMIT    EL1_MPU_REGIONXX_LIMIT(18)
+
+/* region 19 */
+#define EL1_MPU_REGION19_BASE     EL1_MPU_REGIONXX_BASE(19)
+#define EL1_MPU_REGION19_LIMIT    EL1_MPU_REGIONXX_LIMIT(19)
+
+/* region 20 */
+#define EL1_MPU_REGION20_BASE     EL1_MPU_REGIONXX_BASE(20)
+#define EL1_MPU_REGION20_LIMIT    EL1_MPU_REGIONXX_LIMIT(20)
+
+/* region 21 */
+#define EL1_MPU_REGION21_BASE     EL1_MPU_REGIONXX_BASE(21)
+#define EL1_MPU_REGION21_LIMIT    EL1_MPU_REGIONXX_LIMIT(21)
+
+/* region 22 */
+#define EL1_MPU_REGION22_BASE     EL1_MPU_REGIONXX_BASE(22)
+#define EL1_MPU_REGION22_LIMIT    EL1_MPU_REGIONXX_LIMIT(22)
+
+/* region 23 */
+#define EL1_MPU_REGION23_BASE     EL1_MPU_REGIONXX_BASE(23)
+#define EL1_MPU_REGION23_LIMIT    EL1_MPU_REGIONXX_LIMIT(23)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef struct st_bsp_mpu_config
+{
+    uint32_t base;
+    uint32_t limit;
+} bsp_mpu_config_t;
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/* This vector table is for SGI and PPI interrupts. */
+BSP_DONT_REMOVE fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES] =
+{
+    NULL,                              /* INTID0    : SOFTWARE_GENERATE_INT0                   */
+    NULL,                              /* INTID1    : SOFTWARE_GENERATE_INT1                   */
+    NULL,                              /* INTID2    : SOFTWARE_GENERATE_INT2                   */
+    NULL,                              /* INTID3    : SOFTWARE_GENERATE_INT3                   */
+    NULL,                              /* INTID4    : SOFTWARE_GENERATE_INT4                   */
+    NULL,                              /* INTID5    : SOFTWARE_GENERATE_INT5                   */
+    NULL,                              /* INTID6    : SOFTWARE_GENERATE_INT6                   */
+    NULL,                              /* INTID7    : SOFTWARE_GENERATE_INT7                   */
+    NULL,                              /* INTID8    : SOFTWARE_GENERATE_INT8                   */
+    NULL,                              /* INTID9    : SOFTWARE_GENERATE_INT9                   */
+    NULL,                              /* INTID10   : SOFTWARE_GENERATE_INT10                  */
+    NULL,                              /* INTID11   : SOFTWARE_GENERATE_INT11                  */
+    NULL,                              /* INTID12   : SOFTWARE_GENERATE_INT12                  */
+    NULL,                              /* INTID13   : SOFTWARE_GENERATE_INT13                  */
+    NULL,                              /* INTID14   : SOFTWARE_GENERATE_INT14                  */
+    NULL,                              /* INTID15   : SOFTWARE_GENERATE_INT15                  */
+    NULL,                              /* INTID16   : RESERVED                                 */
+    NULL,                              /* INTID17   : RESERVED                                 */
+    NULL,                              /* INTID18   : RESERVED                                 */
+    NULL,                              /* INTID19   : RESERVED                                 */
+    NULL,                              /* INTID20   : RESERVED                                 */
+    NULL,                              /* INTID21   : RESERVED                                 */
+    NULL,                              /* INTID22   : DEBUG_COMMUNICATIONS_CHANNEL_INT         */
+    NULL,                              /* INTID23   : PERFORMANCE_MONITOR_COUNTER_OVERFLOW_INT */
+    NULL,                              /* INTID24   : CROSS_TRIGGER_INTERFACE_INT              */
+    NULL,                              /* INTID25   : VIRTUAL_CPU_INTERFACE_MAINTENANCE_INT    */
+    NULL,                              /* INTID26   : HYPERVISOR_TIMER_INT                     */
+    NULL,                              /* INTID27   : VIRTUAL_TIMER_INT                        */
+    NULL,                              /* INTID28   : RESERVED                                 */
+    NULL,                              /* INTID29   : RESERVED                                 */
+    NULL,                              /* INTID30   : NON-SECURE_PHYSICAL_TIMER_INT            */
+    NULL,                              /* INTID31   : RESERVED                                 */
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+static const bsp_mpu_config_t g_bsp_el1_mpu[EL1_MPU_REGION_COUNT] =
+{
+    {EL1_MPU_REGION00_BASE, EL1_MPU_REGION00_LIMIT},
+    {EL1_MPU_REGION01_BASE, EL1_MPU_REGION01_LIMIT},
+    {EL1_MPU_REGION02_BASE, EL1_MPU_REGION02_LIMIT},
+    {EL1_MPU_REGION03_BASE, EL1_MPU_REGION03_LIMIT},
+    {EL1_MPU_REGION04_BASE, EL1_MPU_REGION04_LIMIT},
+    {EL1_MPU_REGION05_BASE, EL1_MPU_REGION05_LIMIT},
+    {EL1_MPU_REGION06_BASE, EL1_MPU_REGION06_LIMIT},
+    {EL1_MPU_REGION07_BASE, EL1_MPU_REGION07_LIMIT},
+    {EL1_MPU_REGION08_BASE, EL1_MPU_REGION08_LIMIT},
+    {EL1_MPU_REGION09_BASE, EL1_MPU_REGION09_LIMIT},
+    {EL1_MPU_REGION10_BASE, EL1_MPU_REGION10_LIMIT},
+    {EL1_MPU_REGION11_BASE, EL1_MPU_REGION11_LIMIT},
+    {EL1_MPU_REGION12_BASE, EL1_MPU_REGION12_LIMIT},
+    {EL1_MPU_REGION13_BASE, EL1_MPU_REGION13_LIMIT},
+    {EL1_MPU_REGION14_BASE, EL1_MPU_REGION14_LIMIT},
+    {EL1_MPU_REGION15_BASE, EL1_MPU_REGION15_LIMIT},
+    {EL1_MPU_REGION16_BASE, EL1_MPU_REGION16_LIMIT},
+    {EL1_MPU_REGION17_BASE, EL1_MPU_REGION17_LIMIT},
+    {EL1_MPU_REGION18_BASE, EL1_MPU_REGION18_LIMIT},
+    {EL1_MPU_REGION19_BASE, EL1_MPU_REGION19_LIMIT},
+    {EL1_MPU_REGION20_BASE, EL1_MPU_REGION20_LIMIT},
+    {EL1_MPU_REGION21_BASE, EL1_MPU_REGION21_LIMIT},
+    {EL1_MPU_REGION22_BASE, EL1_MPU_REGION22_LIMIT},
+    {EL1_MPU_REGION23_BASE, EL1_MPU_REGION23_LIMIT},
+};
+
+#if __FPU_USED
+void bsp_fpu_advancedsimd_init(void);
+
+#endif
+
+#if (0 == BSP_CFG_CORE_CR52)
+void bsp_slavetcm_enable(void);
+
+#endif
+
+void bsp_memory_protect_setting(void);
+void bsp_mpu_init(uint32_t region, uint32_t base, uint32_t limit);
+void bsp_irq_cfg_common(void);
+
+#if __FPU_USED
+
+/*******************************************************************************************************************//**
+ * Initialize FPU and Advanced SIMD setting.
+ **********************************************************************************************************************/
+void bsp_fpu_advancedsimd_init (void)
+{
+    uint32_t apacr;
+    uint32_t fpexc;
+
+    /* Enables cp10 and cp11 accessing */
+    apacr  = __get_CPACR();
+    apacr |= BSP_CPCAR_CP_ENABLE;
+    __set_CPACR(apacr);
+    __ISB();
+
+    /* Enables the FPU */
+    fpexc  = __get_FPEXC();
+    fpexc |= BSP_FPEXC_EN_ENABLE;
+    __set_FPEXC(fpexc);
+    __ISB();
+}
+
+#endif
+
+#if (0 == BSP_CFG_CORE_CR52)
+
+/*******************************************************************************************************************//**
+ * Settings the privilege level required for the AXIS to access the TCM.
+ **********************************************************************************************************************/
+void bsp_slavetcm_enable (void)
+{
+    uint32_t imp_slavepctlr;
+
+    /* Enable TCM access privilege and non privilege */
+    imp_slavepctlr  = __get_IMP_SLAVEPCTLR();
+    imp_slavepctlr |= BSP_TCM_ALL_ACCESS_ENABLE;
+    __DSB();
+
+    __set_IMP_SLAVEPCTLR(imp_slavepctlr);
+    __ISB();
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Initialize memory protection settings.
+ **********************************************************************************************************************/
+void bsp_memory_protect_setting (void)
+{
+    uint32_t sctlr;
+    uint32_t mair0;
+    uint32_t mair1;
+    uint32_t region;
+    uint32_t base_address;
+    uint32_t limit_address;
+
+#if (1 != _RZN_ORDINAL) && (0 == BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA)
+ #if defined(__ICCARM__)
+  #pragma section="USER_DATA_NONCACHE_WBLOCK"
+    uint32_t cache_end      = (uint32_t) __section_begin("USER_DATA_NONCACHE_WBLOCK") - 1;
+    uint32_t noncache_start = (uint32_t) __section_begin("USER_DATA_NONCACHE_WBLOCK");
+ #elif defined(__GNUC__)
+    extern void * _data_noncache_start;
+    uint32_t      cache_end      = (uint32_t) &_data_noncache_start - 1;
+    uint32_t      noncache_start = (uint32_t) &_data_noncache_start;
+ #endif
+#endif
+
+    /* Adopt EL1 default memory map as background map */
+    sctlr  = __get_SCTLR();
+    sctlr |= BSP_SCTLR_BR_BIT;
+    __DSB();
+    __set_SCTLR(sctlr);
+    __ISB();
+
+    /* Configure Memory Attribute Indirection Registers */
+    mair0 = ATTR_3_2_1_0;
+    mair1 = ATTR_7_6_5_4;
+    __set_MAIR0(mair0);
+    __set_MAIR1(mair1);
+    __DSB();
+
+    /* Setup region. */
+    for (region = 0; region < EL1_MPU_REGION_COUNT; region++)
+    {
+        base_address  = g_bsp_el1_mpu[region].base;
+        limit_address = g_bsp_el1_mpu[region].limit;
+
+#if (1 != _RZN_ORDINAL) && (0 == BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA)
+        if ((EL1_MPU_REGION_SYSTEMRAM_CACHE_ADDRESS_START == (base_address & EL1_MPU_REGION_ADDRESS_MASK)) &&
+            (EL1_MPU_REGION_SYSTEMRAM_CACHE_ADDRESS_END == (limit_address & EL1_MPU_REGION_ADDRESS_MASK)))
+        {
+            limit_address = (cache_end & EL1_MPU_REGION_ADDRESS_MASK) |
+                            (g_bsp_el1_mpu[region].limit & EL1_MPU_REGION_ATTRIBUTE_MASK);
+        }
+        else if ((EL1_MPU_REGION_SYSTEMRAM_NONCACHE_ADDRESS_START == (base_address & EL1_MPU_REGION_ADDRESS_MASK)) &&
+                 (EL1_MPU_REGION_SYSTEMRAM_NONCACHE_ADDRESS_END == (limit_address & EL1_MPU_REGION_ADDRESS_MASK)))
+        {
+            base_address = (noncache_start & EL1_MPU_REGION_ADDRESS_MASK) |
+                           (g_bsp_el1_mpu[region].base & EL1_MPU_REGION_ATTRIBUTE_MASK);
+        }
+        else
+        {
+            // Do Nothing
+        }
+#endif
+
+        bsp_mpu_init(region, base_address, limit_address);
+    }
+
+    R_BSP_CacheInvalidateAll();
+
+    R_BSP_CacheEnableMemoryProtect();
+
+#if (BSP_ICACHE_ENABLE == BSP_CFG_SCTLR_I_BIT)
+    R_BSP_CacheEnableInst();
+#else
+    R_BSP_CacheDisableInst();
+#endif
+
+#if (BSP_DATACACHE_ENABLE == BSP_CFG_SCTLR_C_BIT)
+    R_BSP_CacheEnableData();
+#else
+    R_BSP_CacheDisableData();
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Core MPU initialization block.
+ **********************************************************************************************************************/
+void bsp_mpu_init (uint32_t region, uint32_t base, uint32_t limit)
+{
+    /* Selects the current EL1-controlled MPU region registers, PRBAR, and PRLAR */
+    __set_PRSELR(region);
+    __DSB();
+
+    /* Set the base address and attributes of the MPU region controlled by EL1 */
+    __set_PRBAR(base);
+    __DSB();
+
+    /* Set the limit address and attributes of the MPU region controlled by EL1 */
+    __set_PRLAR(limit);
+    __DSB();
+}
+
+/*******************************************************************************************************************//**
+ * Initialize common configuration settings for interrupts
+ **********************************************************************************************************************/
+void bsp_irq_cfg_common (void)
+{
+    uint32_t icc_pmr;
+    uint32_t icc_igrpen1;
+    uint32_t icc_ctlr;
+
+    /* Set priority mask level for CPU interface */
+    icc_pmr = BSP_PRIORITY_MASK;
+    __set_ICC_PMR(icc_pmr);
+
+    /* Enable group 1 interrupts */
+    icc_igrpen1 = BSP_ENABLE_GROUP_INT;
+    __set_ICC_IGRPEN1(icc_igrpen1);
+
+    /* Use ICC_BPR0 for interrupt preemption for both group 0 and group 1 interrupts */
+    icc_ctlr  = __get_ICC_CTLR();
+    icc_ctlr |= BSP_ICC_CTLR;
+    __set_ICC_CTLR(icc_ctlr);
+
+    __ISB();
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
new file mode 100644
index 00000000..b3d30afd
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
@@ -0,0 +1,221 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+#if (1 == _RZN_ORDINAL)
+extern void bsp_master_mpu_init(void);
+extern void bsp_global_system_counter_init(void);
+
+#endif
+
+#if defined(BSP_CFG_CORE_CR52)
+ #if (BSP_FEATURE_TFU_SUPPORTED & BSP_CFG_USE_TFU_MATHLIB)
+extern void bsp_tfu_init(void);
+
+ #endif
+#endif
+
+#if BSP_CFG_C_RUNTIME_INIT
+extern void bsp_static_constructor_init(void);
+extern void bsp_loader_data_init(void);
+extern void bsp_loader_bss_init(void);
+
+#endif
+
+#if !BSP_CFG_PORT_PROTECT
+extern void bsp_release_port_protect(void);
+
+#endif
+
+#if !(BSP_CFG_RAM_EXECUTION)
+
+extern void bsp_copy_to_ram(void);
+
+extern void bsp_application_bss_init(void);
+
+#endif
+
+extern void bsp_memory_protect_setting(void);
+extern void bsp_irq_cfg_common(void);
+
+extern void R_BSP_WarmStart(bsp_warm_start_event_t event);
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+int32_t main(void);
+
+#if BSP_CFG_EARLY_INIT
+static void bsp_init_uninitialized_vars(void);
+
+#endif
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initialize the MCU and the runtime environment.
+ **********************************************************************************************************************/
+void SystemInit (void)
+{
+#if BSP_CFG_EARLY_INIT
+
+    /* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */
+    bsp_init_uninitialized_vars();
+#endif
+
+    /* Call before initializing clock and variables. */
+    R_BSP_WarmStart(BSP_WARM_START_RESET);
+
+#if (1 == _RZN_ORDINAL)
+
+    /* Configure system clocks. */
+    bsp_clock_init();
+#endif
+
+    /* Call post clock initialization hook. */
+    R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);
+
+#if BSP_CFG_C_RUNTIME_INIT
+
+    /* Copy the primary core loader data from external Flash to internal RAM. */
+    bsp_loader_data_init();
+
+    /* Clear loader bss section in internal RAM. */
+    bsp_loader_bss_init();
+#endif
+
+#if BSP_FEATURE_ADDRESS_EXPANDER_SUPPORTED
+ #if (1 == _RZN_ORDINAL)
+
+    /* Initialize the Address Expander settings. */
+    bsp_address_expander_init();
+ #endif
+#endif
+
+#if BSP_FEATURE_TZC400_SUPPORTED
+ #if (1 == _RZN_ORDINAL)
+
+    /* Initialize the TZC-400 settings. */
+    bsp_tzc_400_cfg();
+ #endif
+#endif
+
+    /* Initialize SystemCoreClock variable. */
+    SystemCoreClockUpdate();
+
+    /* Set memory attributes, etc. */
+    bsp_memory_protect_setting();
+
+#if !(BSP_CFG_RAM_EXECUTION)
+
+    /* Copy the application program from external Flash to internal RAM.
+     * In the case of multi-core operation, copies each section (vector, loader(program/data), user(program/data)) of
+     * the secondary core (or later). */
+    bsp_copy_to_ram();
+
+    /* Clear bss section in internal RAM. */
+    bsp_application_bss_init();
+#endif
+
+#if BSP_CFG_C_RUNTIME_INIT
+
+    /* Initialize static constructors */
+    bsp_static_constructor_init();
+#endif
+
+#if !BSP_CFG_PORT_PROTECT
+
+    /* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+     * disable writes. */
+    bsp_release_port_protect();
+#endif
+
+    /* Call Post C runtime initialization hook. */
+    R_BSP_WarmStart(BSP_WARM_START_POST_C);
+
+#if (1 == _RZN_ORDINAL)
+ #if BSP_CFG_SEMAPHORE_ENABLE
+
+    /* Initialize semaphores required for synchronization and exclusive control between CPUs. */
+    bsp_semaphore_init();
+ #endif
+
+    /* Initialize the Master-MPU settings. */
+    bsp_master_mpu_init();
+
+    /* Initialize global system counter. The counter is enabled and is incrementing. */
+    bsp_global_system_counter_init();
+#endif
+
+    /* GIC initialization */
+    bsp_irq_cfg_common();
+
+    /* Initialize GIC interrupts. */
+    bsp_irq_cfg();
+
+#if defined(BSP_CFG_CORE_CR52)
+ #if (BSP_FEATURE_TFU_SUPPORTED & BSP_CFG_USE_TFU_MATHLIB)
+
+    /* Initialize the TFU settings. */
+    bsp_tfu_init();
+ #endif
+#endif
+
+#if defined(__GNUC__)
+    extern void entry(void);
+    entry();
+#elif defined(__ICCARM__)
+    extern void __low_level_init(void);
+    __low_level_init();
+#else
+    /* Jump to main. */
+    main();
+#endif
+}
+
+/** @} (end addtogroup BSP_MCU) */
+
+#if BSP_CFG_EARLY_INIT
+
+/*******************************************************************************************************************//**
+ * Initialize BSP variables not handled by C runtime startup.
+ **********************************************************************************************************************/
+static void bsp_init_uninitialized_vars (void)
+{
+    g_protect_port_counter = 0;
+
+    extern volatile uint16_t g_protect_counters[];
+    for (uint32_t i = 0; i < 4; i++)
+    {
+        g_protect_counters[i] = 0;
+    }
+
+    SystemCoreClockUpdate();
+}
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
new file mode 100644
index 00000000..793d7a08
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
@@ -0,0 +1,1703 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_PRV_SECONDARY_ADDRESS_ALIGN     (0x20000U)
+
+#if BSP_CFG_XSPI0_X1_BOOT || BSP_CFG_XSPI0_X8_BOOT
+ #define BSP_PRV_ROM_BASE_ADDRESS           BSP_FEATURE_BSP_XSPI0_CS0_BASE_ADDRESS
+ #define BSP_PRV_ROM_SIZE                   BSP_FEATURE_BSP_XSPI0_CS0_SIZE
+
+#elif BSP_CFG_XSPI1_X1_BOOT
+ #define BSP_PRV_ROM_BASE_ADDRESS           BSP_FEATURE_BSP_XSPI1_CS0_BASE_ADDRESS
+ #define BSP_PRV_ROM_SIZE                   BSP_FEATURE_BSP_XSPI1_CS0_SIZE
+
+#elif BSP_CFG_16BIT_NOR_BOOT || BSP_CFG_32BIT_NOR_BOOT
+ #define BSP_PRV_ROM_BASE_ADDRESS           BSP_FEATURE_BSP_CS0_BASE_ADDRESS
+ #define BSP_PRV_ROM_SIZE                   BSP_FEATURE_BSP_CS0_SIZE
+
+#endif
+
+#if defined(BSP_CFG_CORE_CR52)
+ #define BSP_PRV_SOFTWARE_RESET_OCCURRED    (0)
+
+ #if (0 == BSP_CFG_CORE_CR52)
+  #define BSP_PRV_RSTSR0_CPU_RESET_MASK     (0x10)
+
+ #elif (1 == BSP_CFG_CORE_CR52)
+  #define BSP_PRV_RSTSR0_CPU_RESET_MASK     (0x20)
+
+ #endif
+#elif defined(BSP_CFG_CORE_CA55)
+ #define BSP_PRV_SOFTWARE_RESET_OCCURRED    g_bsp_software_reset_occurred
+ #define BSP_PRV_RSTSR0_CPU_RESET_MASK      (0x40)
+
+#endif
+
+#if (1 == _RZN_ORDINAL)
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+  #define BSP_PRV_MASTER_MPU_REGION_NUM      (8)
+ #elif (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+  #define BSP_PRV_MASTER_MPU_REGION_NUM      (16)
+ #endif
+ #define BSP_PRV_M_MPU_35BIT_ADDRESS_MASK    (0x700000000UL)
+
+ #define BSP_PRV_MASTER_MPU_STADD(master,                                                         \
+                                  region)     (((BSP_CFG_MPU ## master ## _STADD ## region) &~    \
+                                                BSP_PRV_M_MPU_35BIT_ADDRESS_MASK) |               \
+                                               (((BSP_CFG_MPU ## master ## _STADD ## region) &    \
+                                                 BSP_PRV_M_MPU_35BIT_ADDRESS_MASK) >> 28) |       \
+                                               (BSP_CFG_MPU ## master ## _WRITE ## region << 1) | \
+                                               BSP_CFG_MPU ## master ## _READ ## region)
+
+ #define BSP_PRV_MASTER_MPU_ENDADD(master,                                                     \
+                                   region)    ((BSP_CFG_MPU ## master ## _ENDADD ## region) &~ \
+                                               BSP_PRV_M_MPU_35BIT_ADDRESS_MASK) |             \
+    (((BSP_CFG_MPU ## master ## _ENDADD ## region) &                                           \
+      BSP_PRV_M_MPU_35BIT_ADDRESS_MASK) >> 28)
+
+ #define BSP_PRV_GLOBAL_SYSTEM_COUNTER_ENABLE    (1)
+#endif
+
+#if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+ #if !(BSP_CFG_RAM_EXECUTION)
+
+  #define BSP_PRV_LOADER_TEXT_OFFSET                     (0x1000U)
+  #define BSP_PRV_ATCM_AXIS_CR520_ADDRESS                (0x20000000)
+  #define BSP_PRV_ATCM_AXIS_CR521_ADDRESS                (0x21000000)
+
+  #define BSP_PRV_IMAGE_INFO_OFFSET                      (0x800)
+  #define BSP_PRV_IMAGE_INFO_BRANCH_INSTRUCTION_CR520    (0xE51FF004)
+  #define BSP_PRV_IMAGE_INFO_BRANCH_INSTRUCTION_CR521    (0xE51FF000)
+  #define BSP_PRV_IMAGE_INFO_BRANCH_ADDRESS              ((uint32_t) ((uintptr_t) BSP_PRV_SECTION_SECONDARY_RAM_START + \
+                                                                      BSP_PRV_LOADER_TEXT_OFFSET))
+  #define BSP_PRV_IMAGE_INFO_NEXT_CORE_ADDRESS           ((uint32_t) ((uintptr_t) BSP_PRV_SECTION_SECONDARY_RAM_START))
+
+  #if defined(BSP_CFG_CORE_CR52)
+   #if (0 == BSP_CFG_CORE_CR52)
+    #define BSP_PRV_IMAGE_INFO_CPU                       (BSP_PRIV_ASSIGNMENT_CPU_CR52_0)
+
+   #elif (1 == BSP_CFG_CORE_CR52)
+    #define BSP_PRV_IMAGE_INFO_CPU                       (BSP_PRIV_ASSIGNMENT_CPU_CR52_1)
+
+   #endif
+  #elif defined(BSP_CFG_CORE_CA55)
+   #if (0 == BSP_CFG_CORE_CA55)
+    #define BSP_PRV_IMAGE_INFO_CPU                       (BSP_PRIV_ASSIGNMENT_CPU_CA55_0)
+
+   #elif (1 == BSP_CFG_CORE_CA55)
+    #define BSP_PRV_IMAGE_INFO_CPU                       (BSP_PRIV_ASSIGNMENT_CPU_CA55_1)
+
+   #elif (2 == BSP_CFG_CORE_CA55)
+    #define BSP_PRV_IMAGE_INFO_CPU                       (BSP_PRIV_ASSIGNMENT_CPU_CA55_2)
+
+   #elif (3 == BSP_CFG_CORE_CA55)
+    #define BSP_PRV_IMAGE_INFO_CPU                       (BSP_PRIV_ASSIGNMENT_CPU_CA55_3)
+
+   #endif
+  #endif
+ #endif
+#endif
+
+#if defined(__ICCARM__)
+ #if BSP_CFG_C_RUNTIME_INIT
+  #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS                  __section_begin("LDR_DATA_RBLOCK")
+  #define BSP_PRV_SECTION_LDR_DATA_RAM_START                    __section_begin("LDR_DATA_WBLOCK")
+  #define BSP_PRV_SECTION_LDR_DATA_RAM_END                      __section_end("LDR_DATA_WBLOCK")
+
+  #define BSP_PRV_SECTION_LDR_DATA_BSS_START                    __section_begin("LDR_DATA_ZBLOCK")
+  #define BSP_PRV_SECTION_LDR_DATA_BSS_END                      __section_end("LDR_DATA_ZBLOCK")
+
+ #endif
+
+ #if !(BSP_CFG_RAM_EXECUTION)
+  #define BSP_PRV_SECTION_VECTOR_ROM_ADDRESS                    __section_begin("VECTOR_RBLOCK")
+  #define BSP_PRV_SECTION_VECTOR_RAM_START                      __section_begin("VECTOR_WBLOCK")
+  #define BSP_PRV_SECTION_VECTOR_RAM_END                        __section_end("VECTOR_WBLOCK")
+
+  #define BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS                  __section_begin("USER_PRG_RBLOCK")
+  #define BSP_PRV_SECTION_USER_PRG_RAM_START                    __section_begin("USER_PRG_WBLOCK")
+  #define BSP_PRV_SECTION_USER_PRG_RAM_END                      __section_end("USER_PRG_WBLOCK")
+
+  #define BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS                 __section_begin("USER_DATA_RBLOCK")
+  #define BSP_PRV_SECTION_USER_DATA_RAM_START                   __section_begin("USER_DATA_WBLOCK")
+  #define BSP_PRV_SECTION_USER_DATA_RAM_END                     __section_end("USER_DATA_WBLOCK")
+
+  #define BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS        __section_begin("USER_DATA_NONCACHE_RBLOCK")
+  #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START          __section_begin("USER_DATA_NONCACHE_WBLOCK")
+  #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END            __section_end("USER_DATA_NONCACHE_WBLOCK")
+
+  #define BSP_PRV_SECTION_DMAC_LINK_MODE_ROM_ADDRESS            __section_begin("DMAC_LINK_MODE_RBLOCK")
+  #define BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_START              __section_begin("DMAC_LINK_MODE_WBLOCK")
+  #define BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_END                __section_end("DMAC_LINK_MODE_WBLOCK")
+
+  #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_ROM_ADDRESS    __section_begin("SHARED_NONCACHE_BUFFER_RBLOCK")
+  #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_RAM_START      __section_begin("SHARED_NONCACHE_BUFFER_WBLOCK")
+  #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_RAM_END        __section_end("SHARED_NONCACHE_BUFFER_WBLOCK")
+
+  #define BSP_PRV_SECTION_NONCACHE_BUFFER_ROM_ADDRESS           __section_begin("NONCACHE_BUFFER_RBLOCK")
+  #define BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_START             __section_begin("NONCACHE_BUFFER_WBLOCK")
+  #define BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_END               __section_end("NONCACHE_BUFFER_WBLOCK")
+
+  #define BSP_PRV_SECTION_LDR_PRG_ROM_ADDRESS                   __section_begin("LDR_PRG_RBLOCK")
+  #define BSP_PRV_SECTION_LDR_PRG_RAM_START                     __section_begin("LDR_PRG_WBLOCK")
+  #define BSP_PRV_SECTION_LDR_PRG_RAM_END                       __section_end("LDR_PRG_WBLOCK")
+
+  #define BSP_PRV_SECTION_USER_DATA_BSS_START                   __section_begin("USER_DATA_ZBLOCK")
+  #define BSP_PRV_SECTION_USER_DATA_BSS_END                     __section_end("USER_DATA_ZBLOCK")
+
+  #define BSP_PRV_SECTION_USER_DATA_NONCACHE_BSS_START          __section_begin("USER_DATA_NONCACHE_ZBLOCK")
+  #define BSP_PRV_SECTION_USER_DATA_NONCACHE_BSS_END            __section_end("USER_DATA_NONCACHE_ZBLOCK")
+
+  #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START              __section_begin("DMAC_LINK_MODE_ZBLOCK")
+  #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END                __section_end("DMAC_LINK_MODE_ZBLOCK")
+
+  #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START      __section_begin("SHARED_NONCACHE_BUFFER_ZBLOCK")
+  #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END        __section_end("SHARED_NONCACHE_BUFFER_ZBLOCK")
+
+  #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START             __section_begin("NONCACHE_BUFFER_ZBLOCK")
+  #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END               __section_end("NONCACHE_BUFFER_ZBLOCK")
+
+  #if !(BSP_CFG_C_RUNTIME_INIT)
+   #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS                 __section_begin("LDR_DATA_RBLOCK")
+   #define BSP_PRV_SECTION_LDR_DATA_RAM_START                   __section_begin("LDR_DATA_WBLOCK")
+   #define BSP_PRV_SECTION_LDR_DATA_RAM_END                     __section_end("LDR_DATA_WBLOCK")
+
+  #endif
+ #endif
+
+ #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+  #define BSP_PRV_SECTION_SECONDARY_ROM_ADDRESS    __section_begin("SECONDARY_RBLOCK")
+  #define BSP_PRV_SECTION_SECONDARY_RAM_START      __section_begin("SECONDARY_WBLOCK")
+  #define BSP_PRV_SECTION_SECONDARY_RAM_END        __section_end("SECONDARY_WBLOCK")
+
+ #endif
+
+#elif defined(__GNUC__)
+ #if BSP_CFG_C_RUNTIME_INIT
+  #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS                  &LOADER_DATA_IMAGE
+  #define BSP_PRV_SECTION_LDR_DATA_RAM_START                    &__loader_data_start
+  #define BSP_PRV_SECTION_LDR_DATA_RAM_END                      &__loader_data_end
+
+  #define BSP_PRV_SECTION_LDR_DATA_BSS_START                    &__loader_bss_start
+  #define BSP_PRV_SECTION_LDR_DATA_BSS_END                      &__loader_bss_end
+
+ #endif
+
+ #if !(BSP_CFG_RAM_EXECUTION)
+  #define BSP_PRV_SECTION_VECTOR_ROM_ADDRESS                    &INTVEC_IMAGE
+  #define BSP_PRV_SECTION_VECTOR_RAM_START                      &_fvector_start
+  #define BSP_PRV_SECTION_VECTOR_RAM_END                        &_fvector_end
+
+  #define BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS                  &TEXT_IMAGE
+  #define BSP_PRV_SECTION_USER_PRG_RAM_START                    &_text_start
+  #define BSP_PRV_SECTION_USER_PRG_RAM_END                      &_text_end
+
+  #define BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS                 &DATA_IMAGE
+  #define BSP_PRV_SECTION_USER_DATA_RAM_START                   &_data_start
+  #define BSP_PRV_SECTION_USER_DATA_RAM_END                     &_data_end
+
+  #define BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS        &_mdata_noncache
+  #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START          &_data_noncache_start
+  #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END            &_data_noncache_end
+
+  #define BSP_PRV_SECTION_DMAC_LINK_MODE_ROM_ADDRESS            &_mdmac_link_mode
+  #define BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_START              &_dmac_link_mode_start
+  #define BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_END                &_dmac_link_mode_end
+
+  #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_ROM_ADDRESS    &_msncbuffer
+  #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_RAM_START      &_sncbuffer_start
+  #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_RAM_END        &_sncbuffer_end
+
+  #define BSP_PRV_SECTION_NONCACHE_BUFFER_ROM_ADDRESS           &_mncbuffer
+  #define BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_START             &_ncbuffer_start
+  #define BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_END               &_ncbuffer_end
+
+  #define BSP_PRV_SECTION_LDR_PRG_ROM_ADDRESS                   &LOADER_TEXT_IMAGE
+  #define BSP_PRV_SECTION_LDR_PRG_RAM_START                     &_loader_text_start
+  #define BSP_PRV_SECTION_LDR_PRG_RAM_END                       &_loader_text_end
+
+  #if !(BSP_CFG_C_RUNTIME_INIT)
+   #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS                 &LOADER_DATA_IMAGE
+   #define BSP_PRV_SECTION_LDR_DATA_RAM_START                   &__loader_data_start
+   #define BSP_PRV_SECTION_LDR_DATA_RAM_END                     &__loader_data_end
+
+  #endif
+ #endif
+
+ #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+  #define BSP_PRV_SECTION_SECONDARY_ROM_ADDRESS    &SECONDARY_IMAGE
+  #define BSP_PRV_SECTION_SECONDARY_RAM_START      &_secondary_start
+  #define BSP_PRV_SECTION_SECONDARY_RAM_END        &_secondary_end
+
+ #endif
+
+ #define BSP_PRV_SECTION_USER_DATA_BSS_START       &__bss_start__
+ #define BSP_PRV_SECTION_USER_DATA_BSS_END         &__bss_end__
+
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+#if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+
+typedef enum e_bsp_assignment_cpu
+{
+    BSP_PRIV_ASSIGNMENT_CPU_CR52_0 = 0xAC54E000,
+    BSP_PRIV_ASSIGNMENT_CPU_CR52_1 = 0xAC54E001,
+    BSP_PRIV_ASSIGNMENT_CPU_CA55_0 = 0xAC54E002,
+    BSP_PRIV_ASSIGNMENT_CPU_CA55_1 = 0xAC54E003,
+    BSP_PRIV_ASSIGNMENT_CPU_CA55_2 = 0xAC54E004,
+    BSP_PRIV_ASSIGNMENT_CPU_CA55_3 = 0xAC54E005
+} bsp_assignment_cpu_t;
+
+#endif
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/** System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock = 0U;
+
+/** @} (end addtogroup BSP_MCU) */
+
+#if defined(__ICCARM__)
+ #if BSP_CFG_C_RUNTIME_INIT
+  #pragma section="LDR_DATA_RBLOCK"
+  #pragma section="LDR_DATA_WBLOCK"
+  #pragma section="LDR_DATA_ZBLOCK"
+
+ #endif
+
+ #if !(BSP_CFG_RAM_EXECUTION)
+  #pragma section="VECTOR_RBLOCK"
+  #pragma section="VECTOR_WBLOCK"
+
+  #pragma section="USER_PRG_RBLOCK"
+  #pragma section="USER_PRG_WBLOCK"
+
+  #pragma section="USER_DATA_RBLOCK"
+  #pragma section="USER_DATA_WBLOCK"
+  #pragma section="USER_DATA_ZBLOCK"
+
+  #pragma section="USER_DATA_NONCACHE_RBLOCK"
+  #pragma section="USER_DATA_NONCACHE_WBLOCK"
+  #pragma section="USER_DATA_NONCACHE_ZBLOCK"
+
+  #pragma section="DMAC_LINK_MODE_RBLOCK"
+  #pragma section="DMAC_LINK_MODE_WBLOCK"
+  #pragma section="DMAC_LINK_MODE_ZBLOCK"
+
+  #pragma section="SHARED_NONCACHE_BUFFER_RBLOCK"
+  #pragma section="SHARED_NONCACHE_BUFFER_WBLOCK"
+  #pragma section="SHARED_NONCACHE_BUFFER_ZBLOCK"
+
+  #pragma section="NONCACHE_BUFFER_RBLOCK"
+  #pragma section="NONCACHE_BUFFER_WBLOCK"
+  #pragma section="NONCACHE_BUFFER_ZBLOCK"
+
+  #pragma section="LDR_PRG_RBLOCK"
+  #pragma section="LDR_PRG_WBLOCK"
+
+  #if !(BSP_CFG_C_RUNTIME_INIT)
+   #pragma section="LDR_DATA_RBLOCK"
+   #pragma section="LDR_DATA_WBLOCK"
+
+  #endif
+ #endif
+
+ #pragma section="SECONDARY_RBLOCK"
+ #pragma section="SECONDARY_WBLOCK"
+
+#elif defined(__GNUC__)
+ #if BSP_CFG_C_RUNTIME_INIT
+extern void * LOADER_DATA_IMAGE;
+extern void * __loader_data_start;
+extern void * __loader_data_end;
+
+extern void * __loader_bss_start;
+extern void * __loader_bss_end;
+
+extern void (* __preinit_array_start[])(void);
+extern void (* __preinit_array_end[])(void);
+extern void (* __init_array_start[])(void);
+extern void (* __init_array_end[])(void);
+
+ #endif
+
+ #if !(BSP_CFG_RAM_EXECUTION)
+extern void * INTVEC_IMAGE;
+extern void * _fvector_start;
+extern void * _fvector_end;
+
+extern void * TEXT_IMAGE;
+extern void * _text_start;
+extern void * _text_end;
+
+extern void * DATA_IMAGE;
+extern void * _data_start;
+extern void * _data_end;
+
+extern void * _mdata_noncache;
+extern void * _data_noncache_start;
+extern void * _data_noncache_end;
+
+extern void * _mdmac_link_mode;
+extern void * _dmac_link_mode_start;
+extern void * _dmac_link_mode_end;
+
+extern void * _msncbuffer;
+extern void * _sncbuffer_start;
+extern void * _sncbuffer_end;
+
+extern void * _mncbuffer;
+extern void * _ncbuffer_start;
+extern void * _ncbuffer_end;
+
+extern void * LOADER_TEXT_IMAGE;
+extern void * _loader_text_start;
+extern void * _loader_text_end;
+
+  #if !(BSP_CFG_C_RUNTIME_INIT)
+extern void * LOADER_DATA_IMAGE;
+extern void * __loader_data_start;
+extern void * __loader_data_end;
+
+  #endif
+ #endif
+
+ #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+extern void * SECONDARY_IMAGE;
+extern void * _secondary_start;
+extern void * _secondary_end;
+
+ #endif
+
+extern void * __bss_start__;
+extern void * __bss_end__;
+
+#endif
+
+#if defined(BSP_CFG_CORE_CA55)
+extern bool g_bsp_software_reset_occurred;
+
+#endif
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+#if defined(__ICCARM__)
+ #if BSP_CFG_C_RUNTIME_INIT
+extern void __iar_data_init3(void);
+
+ #endif
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+#if (1 == _RZN_ORDINAL)
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED)
+const uint32_t g_bsp_master_mpu0_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(0, 0),  BSP_PRV_MASTER_MPU_ENDADD(0, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 1),  BSP_PRV_MASTER_MPU_ENDADD(0, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 2),  BSP_PRV_MASTER_MPU_ENDADD(0, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 3),  BSP_PRV_MASTER_MPU_ENDADD(0, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 4),  BSP_PRV_MASTER_MPU_ENDADD(0, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 5),  BSP_PRV_MASTER_MPU_ENDADD(0, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 6),  BSP_PRV_MASTER_MPU_ENDADD(0, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 7),  BSP_PRV_MASTER_MPU_ENDADD(0, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(0, 8),  BSP_PRV_MASTER_MPU_ENDADD(0, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 9),  BSP_PRV_MASTER_MPU_ENDADD(0, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(0, 10), BSP_PRV_MASTER_MPU_ENDADD(0, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(0, 11), BSP_PRV_MASTER_MPU_ENDADD(0, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(0, 12), BSP_PRV_MASTER_MPU_ENDADD(0, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(0, 13), BSP_PRV_MASTER_MPU_ENDADD(0, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(0, 14), BSP_PRV_MASTER_MPU_ENDADD(0, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(0, 15), BSP_PRV_MASTER_MPU_ENDADD(0, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED)
+const uint32_t g_bsp_master_mpu1_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(1, 0),  BSP_PRV_MASTER_MPU_ENDADD(1, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 1),  BSP_PRV_MASTER_MPU_ENDADD(1, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 2),  BSP_PRV_MASTER_MPU_ENDADD(1, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 3),  BSP_PRV_MASTER_MPU_ENDADD(1, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 4),  BSP_PRV_MASTER_MPU_ENDADD(1, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 5),  BSP_PRV_MASTER_MPU_ENDADD(1, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 6),  BSP_PRV_MASTER_MPU_ENDADD(1, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 7),  BSP_PRV_MASTER_MPU_ENDADD(1, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(1, 8),  BSP_PRV_MASTER_MPU_ENDADD(1, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 9),  BSP_PRV_MASTER_MPU_ENDADD(1, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(1, 10), BSP_PRV_MASTER_MPU_ENDADD(1, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(1, 11), BSP_PRV_MASTER_MPU_ENDADD(1, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(1, 12), BSP_PRV_MASTER_MPU_ENDADD(1, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(1, 13), BSP_PRV_MASTER_MPU_ENDADD(1, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(1, 14), BSP_PRV_MASTER_MPU_ENDADD(1, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(1, 15), BSP_PRV_MASTER_MPU_ENDADD(1, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED)
+const uint32_t g_bsp_master_mpu2_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(2, 0),  BSP_PRV_MASTER_MPU_ENDADD(2, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 1),  BSP_PRV_MASTER_MPU_ENDADD(2, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 2),  BSP_PRV_MASTER_MPU_ENDADD(2, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 3),  BSP_PRV_MASTER_MPU_ENDADD(2, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 4),  BSP_PRV_MASTER_MPU_ENDADD(2, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 5),  BSP_PRV_MASTER_MPU_ENDADD(2, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 6),  BSP_PRV_MASTER_MPU_ENDADD(2, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 7),  BSP_PRV_MASTER_MPU_ENDADD(2, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(2, 8),  BSP_PRV_MASTER_MPU_ENDADD(2, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 9),  BSP_PRV_MASTER_MPU_ENDADD(2, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(2, 10), BSP_PRV_MASTER_MPU_ENDADD(2, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(2, 11), BSP_PRV_MASTER_MPU_ENDADD(2, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(2, 12), BSP_PRV_MASTER_MPU_ENDADD(2, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(2, 13), BSP_PRV_MASTER_MPU_ENDADD(2, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(2, 14), BSP_PRV_MASTER_MPU_ENDADD(2, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(2, 15), BSP_PRV_MASTER_MPU_ENDADD(2, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED)
+const uint32_t g_bsp_master_mpu3_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(3, 0),  BSP_PRV_MASTER_MPU_ENDADD(3, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 1),  BSP_PRV_MASTER_MPU_ENDADD(3, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 2),  BSP_PRV_MASTER_MPU_ENDADD(3, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 3),  BSP_PRV_MASTER_MPU_ENDADD(3, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 4),  BSP_PRV_MASTER_MPU_ENDADD(3, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 5),  BSP_PRV_MASTER_MPU_ENDADD(3, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 6),  BSP_PRV_MASTER_MPU_ENDADD(3, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 7),  BSP_PRV_MASTER_MPU_ENDADD(3, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(3, 8),  BSP_PRV_MASTER_MPU_ENDADD(3, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 9),  BSP_PRV_MASTER_MPU_ENDADD(3, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(3, 10), BSP_PRV_MASTER_MPU_ENDADD(3, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(3, 11), BSP_PRV_MASTER_MPU_ENDADD(3, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(3, 12), BSP_PRV_MASTER_MPU_ENDADD(3, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(3, 13), BSP_PRV_MASTER_MPU_ENDADD(3, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(3, 14), BSP_PRV_MASTER_MPU_ENDADD(3, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(3, 15), BSP_PRV_MASTER_MPU_ENDADD(3, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED)
+const uint32_t g_bsp_master_mpu4_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(4, 0),  BSP_PRV_MASTER_MPU_ENDADD(4, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 1),  BSP_PRV_MASTER_MPU_ENDADD(4, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 2),  BSP_PRV_MASTER_MPU_ENDADD(4, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 3),  BSP_PRV_MASTER_MPU_ENDADD(4, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 4),  BSP_PRV_MASTER_MPU_ENDADD(4, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 5),  BSP_PRV_MASTER_MPU_ENDADD(4, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 6),  BSP_PRV_MASTER_MPU_ENDADD(4, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 7),  BSP_PRV_MASTER_MPU_ENDADD(4, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(4, 8),  BSP_PRV_MASTER_MPU_ENDADD(4, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 9),  BSP_PRV_MASTER_MPU_ENDADD(4, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(4, 10), BSP_PRV_MASTER_MPU_ENDADD(4, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(4, 11), BSP_PRV_MASTER_MPU_ENDADD(4, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(4, 12), BSP_PRV_MASTER_MPU_ENDADD(4, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(4, 13), BSP_PRV_MASTER_MPU_ENDADD(4, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(4, 14), BSP_PRV_MASTER_MPU_ENDADD(4, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(4, 15), BSP_PRV_MASTER_MPU_ENDADD(4, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU5_SUPPORTED)
+const uint32_t g_bsp_master_mpu5_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(5, 0),  BSP_PRV_MASTER_MPU_ENDADD(5, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 1),  BSP_PRV_MASTER_MPU_ENDADD(5, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 2),  BSP_PRV_MASTER_MPU_ENDADD(5, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 3),  BSP_PRV_MASTER_MPU_ENDADD(5, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 4),  BSP_PRV_MASTER_MPU_ENDADD(5, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 5),  BSP_PRV_MASTER_MPU_ENDADD(5, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 6),  BSP_PRV_MASTER_MPU_ENDADD(5, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 7),  BSP_PRV_MASTER_MPU_ENDADD(5, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(5, 8),  BSP_PRV_MASTER_MPU_ENDADD(5, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 9),  BSP_PRV_MASTER_MPU_ENDADD(5, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(5, 10), BSP_PRV_MASTER_MPU_ENDADD(5, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(5, 11), BSP_PRV_MASTER_MPU_ENDADD(5, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(5, 12), BSP_PRV_MASTER_MPU_ENDADD(5, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(5, 13), BSP_PRV_MASTER_MPU_ENDADD(5, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(5, 14), BSP_PRV_MASTER_MPU_ENDADD(5, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(5, 15), BSP_PRV_MASTER_MPU_ENDADD(5, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED)
+const uint32_t g_bsp_master_mpu6_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(6, 0),  BSP_PRV_MASTER_MPU_ENDADD(6, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 1),  BSP_PRV_MASTER_MPU_ENDADD(6, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 2),  BSP_PRV_MASTER_MPU_ENDADD(6, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 3),  BSP_PRV_MASTER_MPU_ENDADD(6, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 4),  BSP_PRV_MASTER_MPU_ENDADD(6, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 5),  BSP_PRV_MASTER_MPU_ENDADD(6, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 6),  BSP_PRV_MASTER_MPU_ENDADD(6, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 7),  BSP_PRV_MASTER_MPU_ENDADD(6, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(6, 8),  BSP_PRV_MASTER_MPU_ENDADD(6, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 9),  BSP_PRV_MASTER_MPU_ENDADD(6, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(6, 10), BSP_PRV_MASTER_MPU_ENDADD(6, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(6, 11), BSP_PRV_MASTER_MPU_ENDADD(6, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(6, 12), BSP_PRV_MASTER_MPU_ENDADD(6, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(6, 13), BSP_PRV_MASTER_MPU_ENDADD(6, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(6, 14), BSP_PRV_MASTER_MPU_ENDADD(6, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(6, 15), BSP_PRV_MASTER_MPU_ENDADD(6, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED)
+const uint32_t g_bsp_master_mpu7_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(7, 0),  BSP_PRV_MASTER_MPU_ENDADD(7, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 1),  BSP_PRV_MASTER_MPU_ENDADD(7, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 2),  BSP_PRV_MASTER_MPU_ENDADD(7, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 3),  BSP_PRV_MASTER_MPU_ENDADD(7, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 4),  BSP_PRV_MASTER_MPU_ENDADD(7, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 5),  BSP_PRV_MASTER_MPU_ENDADD(7, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 6),  BSP_PRV_MASTER_MPU_ENDADD(7, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 7),  BSP_PRV_MASTER_MPU_ENDADD(7, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(7, 8),  BSP_PRV_MASTER_MPU_ENDADD(7, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 9),  BSP_PRV_MASTER_MPU_ENDADD(7, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(7, 10), BSP_PRV_MASTER_MPU_ENDADD(7, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(7, 11), BSP_PRV_MASTER_MPU_ENDADD(7, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(7, 12), BSP_PRV_MASTER_MPU_ENDADD(7, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(7, 13), BSP_PRV_MASTER_MPU_ENDADD(7, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(7, 14), BSP_PRV_MASTER_MPU_ENDADD(7, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(7, 15), BSP_PRV_MASTER_MPU_ENDADD(7, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED)
+const uint32_t g_bsp_master_mpu8_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(8, 0),  BSP_PRV_MASTER_MPU_ENDADD(8, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 1),  BSP_PRV_MASTER_MPU_ENDADD(8, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 2),  BSP_PRV_MASTER_MPU_ENDADD(8, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 3),  BSP_PRV_MASTER_MPU_ENDADD(8, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 4),  BSP_PRV_MASTER_MPU_ENDADD(8, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 5),  BSP_PRV_MASTER_MPU_ENDADD(8, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 6),  BSP_PRV_MASTER_MPU_ENDADD(8, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 7),  BSP_PRV_MASTER_MPU_ENDADD(8, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(8, 8),  BSP_PRV_MASTER_MPU_ENDADD(8, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 9),  BSP_PRV_MASTER_MPU_ENDADD(8, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(8, 10), BSP_PRV_MASTER_MPU_ENDADD(8, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(8, 11), BSP_PRV_MASTER_MPU_ENDADD(8, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(8, 12), BSP_PRV_MASTER_MPU_ENDADD(8, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(8, 13), BSP_PRV_MASTER_MPU_ENDADD(8, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(8, 14), BSP_PRV_MASTER_MPU_ENDADD(8, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(8, 15), BSP_PRV_MASTER_MPU_ENDADD(8, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU9_SUPPORTED)
+const uint32_t g_bsp_master_mpu9_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(9, 0),  BSP_PRV_MASTER_MPU_ENDADD(9, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 1),  BSP_PRV_MASTER_MPU_ENDADD(9, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 2),  BSP_PRV_MASTER_MPU_ENDADD(9, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 3),  BSP_PRV_MASTER_MPU_ENDADD(9, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 4),  BSP_PRV_MASTER_MPU_ENDADD(9, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 5),  BSP_PRV_MASTER_MPU_ENDADD(9, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 6),  BSP_PRV_MASTER_MPU_ENDADD(9, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 7),  BSP_PRV_MASTER_MPU_ENDADD(9, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(9, 8),  BSP_PRV_MASTER_MPU_ENDADD(9, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 9),  BSP_PRV_MASTER_MPU_ENDADD(9, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(9, 10), BSP_PRV_MASTER_MPU_ENDADD(9, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(9, 11), BSP_PRV_MASTER_MPU_ENDADD(9, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(9, 12), BSP_PRV_MASTER_MPU_ENDADD(9, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(9, 13), BSP_PRV_MASTER_MPU_ENDADD(9, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(9, 14), BSP_PRV_MASTER_MPU_ENDADD(9, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(9, 15), BSP_PRV_MASTER_MPU_ENDADD(9, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU10_SUPPORTED)
+const uint32_t g_bsp_master_mpu10_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(10, 0),  BSP_PRV_MASTER_MPU_ENDADD(10, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 1),  BSP_PRV_MASTER_MPU_ENDADD(10, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 2),  BSP_PRV_MASTER_MPU_ENDADD(10, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 3),  BSP_PRV_MASTER_MPU_ENDADD(10, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 4),  BSP_PRV_MASTER_MPU_ENDADD(10, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 5),  BSP_PRV_MASTER_MPU_ENDADD(10, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 6),  BSP_PRV_MASTER_MPU_ENDADD(10, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 7),  BSP_PRV_MASTER_MPU_ENDADD(10, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(10, 8),  BSP_PRV_MASTER_MPU_ENDADD(10, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 9),  BSP_PRV_MASTER_MPU_ENDADD(10, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(10, 10), BSP_PRV_MASTER_MPU_ENDADD(10, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(10, 11), BSP_PRV_MASTER_MPU_ENDADD(10, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(10, 12), BSP_PRV_MASTER_MPU_ENDADD(10, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(10, 13), BSP_PRV_MASTER_MPU_ENDADD(10, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(10, 14), BSP_PRV_MASTER_MPU_ENDADD(10, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(10, 15), BSP_PRV_MASTER_MPU_ENDADD(10, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU11_SUPPORTED)
+const uint32_t g_bsp_master_mpu11_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(11, 0),  BSP_PRV_MASTER_MPU_ENDADD(11, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 1),  BSP_PRV_MASTER_MPU_ENDADD(11, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 2),  BSP_PRV_MASTER_MPU_ENDADD(11, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 3),  BSP_PRV_MASTER_MPU_ENDADD(11, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 4),  BSP_PRV_MASTER_MPU_ENDADD(11, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 5),  BSP_PRV_MASTER_MPU_ENDADD(11, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 6),  BSP_PRV_MASTER_MPU_ENDADD(11, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 7),  BSP_PRV_MASTER_MPU_ENDADD(11, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(11, 8),  BSP_PRV_MASTER_MPU_ENDADD(11, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 9),  BSP_PRV_MASTER_MPU_ENDADD(11, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(11, 10), BSP_PRV_MASTER_MPU_ENDADD(11, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(11, 11), BSP_PRV_MASTER_MPU_ENDADD(11, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(11, 12), BSP_PRV_MASTER_MPU_ENDADD(11, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(11, 13), BSP_PRV_MASTER_MPU_ENDADD(11, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(11, 14), BSP_PRV_MASTER_MPU_ENDADD(11, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(11, 15), BSP_PRV_MASTER_MPU_ENDADD(11, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU12_SUPPORTED)
+const uint32_t g_bsp_master_mpu12_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(12, 0),  BSP_PRV_MASTER_MPU_ENDADD(12, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 1),  BSP_PRV_MASTER_MPU_ENDADD(12, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 2),  BSP_PRV_MASTER_MPU_ENDADD(12, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 3),  BSP_PRV_MASTER_MPU_ENDADD(12, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 4),  BSP_PRV_MASTER_MPU_ENDADD(12, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 5),  BSP_PRV_MASTER_MPU_ENDADD(12, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 6),  BSP_PRV_MASTER_MPU_ENDADD(12, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 7),  BSP_PRV_MASTER_MPU_ENDADD(12, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(12, 8),  BSP_PRV_MASTER_MPU_ENDADD(12, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 9),  BSP_PRV_MASTER_MPU_ENDADD(12, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(12, 10), BSP_PRV_MASTER_MPU_ENDADD(12, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(12, 11), BSP_PRV_MASTER_MPU_ENDADD(12, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(12, 12), BSP_PRV_MASTER_MPU_ENDADD(12, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(12, 13), BSP_PRV_MASTER_MPU_ENDADD(12, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(12, 14), BSP_PRV_MASTER_MPU_ENDADD(12, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(12, 15), BSP_PRV_MASTER_MPU_ENDADD(12, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU13_SUPPORTED)
+const uint32_t g_bsp_master_mpu13_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(13, 0),  BSP_PRV_MASTER_MPU_ENDADD(13, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 1),  BSP_PRV_MASTER_MPU_ENDADD(13, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 2),  BSP_PRV_MASTER_MPU_ENDADD(13, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 3),  BSP_PRV_MASTER_MPU_ENDADD(13, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 4),  BSP_PRV_MASTER_MPU_ENDADD(13, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 5),  BSP_PRV_MASTER_MPU_ENDADD(13, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 6),  BSP_PRV_MASTER_MPU_ENDADD(13, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 7),  BSP_PRV_MASTER_MPU_ENDADD(13, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(13, 8),  BSP_PRV_MASTER_MPU_ENDADD(13, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 9),  BSP_PRV_MASTER_MPU_ENDADD(13, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(13, 10), BSP_PRV_MASTER_MPU_ENDADD(13, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(13, 11), BSP_PRV_MASTER_MPU_ENDADD(13, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(13, 12), BSP_PRV_MASTER_MPU_ENDADD(13, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(13, 13), BSP_PRV_MASTER_MPU_ENDADD(13, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(13, 14), BSP_PRV_MASTER_MPU_ENDADD(13, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(13, 15), BSP_PRV_MASTER_MPU_ENDADD(13, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU14_SUPPORTED)
+const uint32_t g_bsp_master_mpu14_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(14, 0),  BSP_PRV_MASTER_MPU_ENDADD(14, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 1),  BSP_PRV_MASTER_MPU_ENDADD(14, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 2),  BSP_PRV_MASTER_MPU_ENDADD(14, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 3),  BSP_PRV_MASTER_MPU_ENDADD(14, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 4),  BSP_PRV_MASTER_MPU_ENDADD(14, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 5),  BSP_PRV_MASTER_MPU_ENDADD(14, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 6),  BSP_PRV_MASTER_MPU_ENDADD(14, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 7),  BSP_PRV_MASTER_MPU_ENDADD(14, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(14, 8),  BSP_PRV_MASTER_MPU_ENDADD(14, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 9),  BSP_PRV_MASTER_MPU_ENDADD(14, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(14, 10), BSP_PRV_MASTER_MPU_ENDADD(14, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(14, 11), BSP_PRV_MASTER_MPU_ENDADD(14, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(14, 12), BSP_PRV_MASTER_MPU_ENDADD(14, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(14, 13), BSP_PRV_MASTER_MPU_ENDADD(14, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(14, 14), BSP_PRV_MASTER_MPU_ENDADD(14, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(14, 15), BSP_PRV_MASTER_MPU_ENDADD(14, 15)},
+  #endif
+};
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU15_SUPPORTED)
+const uint32_t g_bsp_master_mpu15_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
+{
+    {BSP_PRV_MASTER_MPU_STADD(15, 0),  BSP_PRV_MASTER_MPU_ENDADD(15, 0) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 1),  BSP_PRV_MASTER_MPU_ENDADD(15, 1) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 2),  BSP_PRV_MASTER_MPU_ENDADD(15, 2) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 3),  BSP_PRV_MASTER_MPU_ENDADD(15, 3) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 4),  BSP_PRV_MASTER_MPU_ENDADD(15, 4) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 5),  BSP_PRV_MASTER_MPU_ENDADD(15, 5) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 6),  BSP_PRV_MASTER_MPU_ENDADD(15, 6) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 7),  BSP_PRV_MASTER_MPU_ENDADD(15, 7) },
+  #if (2 == BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE)
+    {BSP_PRV_MASTER_MPU_STADD(15, 8),  BSP_PRV_MASTER_MPU_ENDADD(15, 8) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 9),  BSP_PRV_MASTER_MPU_ENDADD(15, 9) },
+    {BSP_PRV_MASTER_MPU_STADD(15, 10), BSP_PRV_MASTER_MPU_ENDADD(15, 10)},
+    {BSP_PRV_MASTER_MPU_STADD(15, 11), BSP_PRV_MASTER_MPU_ENDADD(15, 11)},
+    {BSP_PRV_MASTER_MPU_STADD(15, 12), BSP_PRV_MASTER_MPU_ENDADD(15, 12)},
+    {BSP_PRV_MASTER_MPU_STADD(15, 13), BSP_PRV_MASTER_MPU_ENDADD(15, 13)},
+    {BSP_PRV_MASTER_MPU_STADD(15, 14), BSP_PRV_MASTER_MPU_ENDADD(15, 14)},
+    {BSP_PRV_MASTER_MPU_STADD(15, 15), BSP_PRV_MASTER_MPU_ENDADD(15, 15)},
+  #endif
+};
+ #endif
+#endif
+
+#if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+ #if !(BSP_CFG_RAM_EXECUTION)
+  #if (1 != _RZN_ORDINAL)
+uint32_t g_bsp_image_info_cpu BSP_PLACE_IN_SECTION(".image_info") = BSP_PRV_IMAGE_INFO_CPU;
+
+  #endif
+ #endif
+
+ #if defined(__ICCARM__)
+  #if (1 == _RZN_ORDINAL)
+   #if defined(BSP_CFG_CORE_CR52)
+BSP_DONT_REMOVE const void * __ddsc_ATCM_END BSP_PLACE_IN_SECTION(".ddsc_atcm_end");
+BSP_DONT_REMOVE const void * __ddsc_BTCM_END BSP_PLACE_IN_SECTION(".ddsc_btcm_end");
+
+   #else
+BSP_DONT_REMOVE const void * __ddsc_SYSTEM_RAM_END BSP_PLACE_IN_SECTION(".ddsc_system_ram_end");
+
+   #endif
+
+   #if BSP_CFG_XSPI0_X1_BOOT || BSP_CFG_XSPI0_X8_BOOT
+BSP_DONT_REMOVE const void * __ddsc_xSPI0_CS0_SPACE_END BSP_PLACE_IN_SECTION(".ddsc_xspi0_cs0_space_end");
+
+   #elif BSP_CFG_XSPI1_X1_BOOT
+BSP_DONT_REMOVE const void * __ddsc_xSPI1_CS0_SPACE_END BSP_PLACE_IN_SECTION(".ddsc_xspi1_cs0_space_end");
+
+   #elif BSP_CFG_16BIT_NOR_BOOT || BSP_CFG_32BIT_NOR_BOOT
+BSP_DONT_REMOVE const void * __ddsc_CS0_SPACE_END BSP_PLACE_IN_SECTION(".ddsc_cs0_space_end");
+
+   #endif
+
+  #else
+BSP_DONT_REMOVE const void * __ddsc_SYSTEM_RAM_END BSP_PLACE_IN_SECTION(".ddsc_system_ram_end");
+
+  #endif
+ #endif
+#endif
+
+#if defined(__ICCARM__)
+
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+
+ #pragma weak R_BSP_WarmStart
+
+#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+
+void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak));
+
+#endif
+
+#if BSP_CFG_C_RUNTIME_INIT
+void bsp_loader_data_init(void);
+void bsp_loader_bss_init(void);
+void bsp_static_constructor_init(void);
+
+#endif
+
+void bsp_copy_multibyte(volatile uintptr_t * src, volatile uintptr_t * dst, volatile uintptr_t bytesize);
+void bsp_bss_init_multibyte(volatile uintptr_t * src, volatile uintptr_t bytesize);
+
+#if !(BSP_CFG_RAM_EXECUTION)
+void bsp_application_bss_init(void);
+void bsp_copy_to_ram(void);
+
+ #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+void bsp_cpu_reset_release(void);
+
+ #endif
+
+ #if (1 != _RZN_ORDINAL)
+uintptr_t bsp_secondary_search_rom_address(void);
+
+ #endif
+#endif
+
+#if (1 == _RZN_ORDINAL)
+void bsp_master_mpu_init(void);
+void bsp_global_system_counter_init(void);
+
+#endif
+
+#if defined(BSP_CFG_CORE_CR52)
+ #if (BSP_FEATURE_TFU_SUPPORTED & BSP_CFG_USE_TFU_MATHLIB)
+void bsp_tfu_init(void);
+
+ #endif
+#endif
+
+#if !BSP_CFG_PORT_PROTECT
+void bsp_release_port_protect(void);
+
+#endif
+
+#if (1 == _RZN_ORDINAL)
+
+/*******************************************************************************************************************//**
+ * Initialize the Master-MPU settings.
+ **********************************************************************************************************************/
+void bsp_master_mpu_init (void)
+{
+    /* Disable register protection for Master-MPU related registers. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+
+    for (uint8_t region_num = 0; region_num < BSP_PRV_MASTER_MPU_REGION_NUM; region_num++)
+    {
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED)
+        R_MPU0->RGN[region_num].STADD  = g_bsp_master_mpu0_cfg[region_num][0];
+        R_MPU0->RGN[region_num].ENDADD = g_bsp_master_mpu0_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED)
+        R_MPU1->RGN[region_num].STADD  = g_bsp_master_mpu1_cfg[region_num][0];
+        R_MPU1->RGN[region_num].ENDADD = g_bsp_master_mpu1_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED)
+        R_MPU2->RGN[region_num].STADD  = g_bsp_master_mpu2_cfg[region_num][0];
+        R_MPU2->RGN[region_num].ENDADD = g_bsp_master_mpu2_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED)
+        R_MPU3->RGN[region_num].STADD  = g_bsp_master_mpu3_cfg[region_num][0];
+        R_MPU3->RGN[region_num].ENDADD = g_bsp_master_mpu3_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED)
+        R_MPU4->RGN[region_num].STADD  = g_bsp_master_mpu4_cfg[region_num][0];
+        R_MPU4->RGN[region_num].ENDADD = g_bsp_master_mpu4_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU5_SUPPORTED)
+        R_MPU5->RGN[region_num].STADD  = g_bsp_master_mpu5_cfg[region_num][0];
+        R_MPU5->RGN[region_num].ENDADD = g_bsp_master_mpu5_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED)
+        R_MPU6->RGN[region_num].STADD  = g_bsp_master_mpu6_cfg[region_num][0];
+        R_MPU6->RGN[region_num].ENDADD = g_bsp_master_mpu6_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED)
+        R_MPU7->RGN[region_num].STADD  = g_bsp_master_mpu7_cfg[region_num][0];
+        R_MPU7->RGN[region_num].ENDADD = g_bsp_master_mpu7_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED)
+        R_MPU8->RGN[region_num].STADD  = g_bsp_master_mpu8_cfg[region_num][0];
+        R_MPU8->RGN[region_num].ENDADD = g_bsp_master_mpu8_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU9_SUPPORTED)
+        R_MPU9->RGN[region_num].STADD  = g_bsp_master_mpu9_cfg[region_num][0];
+        R_MPU9->RGN[region_num].ENDADD = g_bsp_master_mpu9_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU10_SUPPORTED)
+        R_MPU10->RGN[region_num].STADD  = g_bsp_master_mpu10_cfg[region_num][0];
+        R_MPU10->RGN[region_num].ENDADD = g_bsp_master_mpu10_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU11_SUPPORTED)
+        R_MPU11->RGN[region_num].STADD  = g_bsp_master_mpu11_cfg[region_num][0];
+        R_MPU11->RGN[region_num].ENDADD = g_bsp_master_mpu11_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU12_SUPPORTED)
+        R_MPU12->RGN[region_num].STADD  = g_bsp_master_mpu12_cfg[region_num][0];
+        R_MPU12->RGN[region_num].ENDADD = g_bsp_master_mpu12_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU13_SUPPORTED)
+        R_MPU13->RGN[region_num].STADD  = g_bsp_master_mpu13_cfg[region_num][0];
+        R_MPU13->RGN[region_num].ENDADD = g_bsp_master_mpu13_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU14_SUPPORTED)
+        R_MPU14->RGN[region_num].STADD  = g_bsp_master_mpu14_cfg[region_num][0];
+        R_MPU14->RGN[region_num].ENDADD = g_bsp_master_mpu14_cfg[region_num][1];
+ #endif
+ #if (1 == BSP_FEATURE_BSP_MASTER_MPU15_SUPPORTED)
+        R_MPU15->RGN[region_num].STADD  = g_bsp_master_mpu15_cfg[region_num][0];
+        R_MPU15->RGN[region_num].ENDADD = g_bsp_master_mpu15_cfg[region_num][1];
+ #endif
+    }
+
+    /* Enable register protection for Master-MPU related registers. */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+}
+
+/*******************************************************************************************************************//**
+ * Initialize global system counter. The counter is enabled and is incrementing.
+ **********************************************************************************************************************/
+void bsp_global_system_counter_init (void)
+{
+    /* If the global system counter is already running, initialization will be skipped. */
+    if (BSP_PRV_GLOBAL_SYSTEM_COUNTER_ENABLE != R_GSC->CNTCR_b.EN)
+    {
+        /* Initialize registers related the global system counter. */
+        R_GSC->CNTCR  &= (uint32_t) (~R_GSC_CNTCR_EN_Msk);
+        R_GSC->CNTFID0 = BSP_GLOBAL_SYSTEM_COUNTER_CLOCK_HZ;
+        R_GSC->CNTCVL  = 0;
+        R_GSC->CNTCVU  = 0;
+        R_GSC->CNTCR  |= R_GSC_CNTCR_EN_Msk;
+    }
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.
+ * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user
+ * implemented version. One of the main uses for this function is to call functional safety code during the startup
+ * process. To use this function just copy this function into your own code and modify it to meet your needs.
+ *
+ * @param[in]  event    Where the code currently is in the start up process
+ *
+ * @note All programs that are executed when a BSP_WARM_START_RESET, or BSP_WARM_START_POST_CLOCK event occurs
+ *       must be placed in the LOADER section(BTCM for CR52 core, SystemRAM for CA55 core).
+ *       These events occur before the copy of the application program in the startup code is executed,
+ *       so the application program is on ROM and cannot be executed at that time.
+ *       The FSP linker script specifies that the .warm_start section be placed in the LOADER section.
+ *       Adding a section specification to the definition of a function or
+ *       variable makes it easier to place it in the LOADER section.
+ **********************************************************************************************************************/
+void R_BSP_WarmStart (bsp_warm_start_event_t event)
+{
+    if (BSP_WARM_START_RESET == event)
+    {
+        /* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */
+    }
+
+    if (BSP_WARM_START_POST_CLOCK == event)
+    {
+        /* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */
+    }
+    else if (BSP_WARM_START_POST_C == event)
+    {
+        /* C runtime environment, system clocks, and pins are all setup. */
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}
+
+/** @} (end addtogroup BSP_MCU) */
+
+#if BSP_CFG_C_RUNTIME_INIT
+
+/*******************************************************************************************************************//**
+ * Copy the loader data block from external Flash to internal RAM.
+ **********************************************************************************************************************/
+void bsp_loader_data_init (void)
+{
+ #if !(BSP_CFG_RAM_EXECUTION)
+
+    /* Define destination/source address pointer and block size */
+    uintptr_t * src;
+    uintptr_t * dst;
+    uintptr_t   size;
+
+  #if (1 != _RZN_ORDINAL)
+    uintptr_t secondary_rom_address = 0;
+    uintptr_t address_diff          = 0;
+
+    if ((0 != (R_SYSC_NS->RSTSR0 & BSP_PRV_RSTSR0_CPU_RESET_MASK)) || BSP_PRV_SOFTWARE_RESET_OCCURRED)
+    {
+        secondary_rom_address = bsp_secondary_search_rom_address();
+    }
+  #endif
+
+  #if (1 == _RZN_ORDINAL)
+
+    /* Copy loader data block */
+    src  = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_START;
+    bsp_copy_multibyte(src, dst, size);
+  #else
+    if ((0 != (R_SYSC_NS->RSTSR0 & BSP_PRV_RSTSR0_CPU_RESET_MASK)) || BSP_PRV_SOFTWARE_RESET_OCCURRED)
+    {
+        if (0 != secondary_rom_address)
+        {
+            address_diff = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS -
+                           (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START;
+
+            /* Copy secondary loader data block */
+            src  = (uintptr_t *) (secondary_rom_address + address_diff);
+            dst  = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_RAM_START;
+            size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_START;
+            bsp_copy_multibyte(src, dst, size);
+        }
+    }
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Clear the loader bss block in internal RAM.
+ **********************************************************************************************************************/
+void bsp_loader_bss_init (void)
+{
+    /* Define source address pointer and block size */
+    uintptr_t * src;
+    uintptr_t   size;
+
+    /* Clear loader bss block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_BSS_START;
+    size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_BSS_START;
+    bsp_bss_init_multibyte(src, size);
+
+ #if BSP_CFG_RAM_EXECUTION
+  #if defined(__ICCARM__)
+
+    /* Initialize the application data and clear the application bss.
+     * This code is for RAM Execution. If you want to boot with ROM,
+     * enable app_copy and app_bss_init, and disable this code.
+     * Also need to change icf file. */
+    __iar_data_init3();
+  #elif defined(__GNUC__)
+
+    /* Clear application bss block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_BSS_START;
+    size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_START;
+    bsp_bss_init_multibyte(src, size);
+  #endif
+ #endif
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Copy the memory block from Source address to Destination address by the multi byte unit.
+ **********************************************************************************************************************/
+void bsp_copy_multibyte (volatile uintptr_t * src, volatile uintptr_t * dst, volatile uintptr_t bytesize)
+{
+    uintptr_t i;
+    uintptr_t cnt;
+
+    volatile uintptr_t bytesize_mod;
+    volatile uint8_t * src_single_byte;
+    volatile uint8_t * dst_single_byte;
+
+    if (0 != bytesize)
+    {
+        /* Copy Count in multi byte unit */
+        cnt = bytesize / sizeof(uintptr_t);
+
+        for (i = 0; i < cnt; i++)
+        {
+            *dst++ = *src++;
+        }
+
+        /* Copy Count in single byte unit */
+        bytesize_mod = bytesize % sizeof(uintptr_t);
+
+        if (0 != bytesize_mod)
+        {
+            src_single_byte = (volatile uint8_t *) src;
+            dst_single_byte = (volatile uint8_t *) dst;
+
+            for (i = 0; i < bytesize_mod; i++)
+            {
+                *dst_single_byte++ = *src_single_byte++;
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+
+        /* Ensuring data-changing */
+        __asm volatile ("DSB SY");
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Clear the bss block by the multi byte unit.
+ **********************************************************************************************************************/
+void bsp_bss_init_multibyte (volatile uintptr_t * src, volatile uintptr_t bytesize)
+{
+    uintptr_t i;
+    uintptr_t cnt;
+    uintptr_t zero = 0;
+
+    volatile uintptr_t bytesize_mod;
+    volatile uint8_t * src_single_byte;
+    uint8_t            zero_single_byte = 0;
+
+    if (0 != bytesize)
+    {
+        /* Clear Count in multi byte unit */
+        cnt = bytesize / sizeof(uintptr_t);
+
+        for (i = 0; i < cnt; i++)
+        {
+            *src++ = zero;
+        }
+
+        /* Clear Count in single byte unit */
+        bytesize_mod = bytesize % sizeof(uintptr_t);
+
+        if (0 != bytesize_mod)
+        {
+            src_single_byte = (volatile uint8_t *) src;
+
+            for (i = 0; i < bytesize_mod; i++)
+            {
+                *src_single_byte++ = zero_single_byte;
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+
+        /* Ensuring data-changing */
+        __asm volatile ("DSB SY");
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}
+
+#if !(BSP_CFG_RAM_EXECUTION)
+
+/*******************************************************************************************************************//**
+ * Clear the application bss block in internal RAM.
+ **********************************************************************************************************************/
+void bsp_application_bss_init (void)
+{
+    /* Define source address pointer and block size */
+    uintptr_t * src;
+    uintptr_t   size;
+
+    /* Clear application bss block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_BSS_START;
+    size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_START;
+    bsp_bss_init_multibyte(src, size);
+
+ #if defined(__ICCARM__)
+
+    /* Clear user data_noncache block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_BSS_START;
+    size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_BSS_END -
+           (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_BSS_START;
+    bsp_bss_init_multibyte(src, size);
+
+    /* Clear DMAC link mode data block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START;
+    size = (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END -
+           (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START;
+    bsp_bss_init_multibyte(src, size);
+
+  #if (1 == _RZN_ORDINAL)
+
+    /* Clear shared non-cache buffer block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START;
+    size = (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END -
+           (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START;
+    bsp_bss_init_multibyte(src, size);
+  #endif
+
+    /* Clear non-cache buffer block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START;
+    size = (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END -
+           (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START;
+    bsp_bss_init_multibyte(src, size);
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Copy the application program block from external Flash to internal RAM.
+ * In the case of multi-core operation, copies each section (vector, loader(program/data), user(program/data)) of
+ * the secondary core (or later).
+ **********************************************************************************************************************/
+void bsp_copy_to_ram (void)
+{
+    /* Define destination/source address pointer and block size */
+    uintptr_t * src;
+    uintptr_t * dst;
+    uintptr_t   size;
+
+ #if (1 != _RZN_ORDINAL)
+    uintptr_t secondary_rom_address = 0;
+    uintptr_t address_diff          = 0;
+
+    if ((0 != (R_SYSC_NS->RSTSR0 & BSP_PRV_RSTSR0_CPU_RESET_MASK)) || BSP_PRV_SOFTWARE_RESET_OCCURRED)
+    {
+        secondary_rom_address = bsp_secondary_search_rom_address();
+    }
+ #endif
+
+ #if (1 == _RZN_ORDINAL)
+
+    /* Copy exception vector block */
+    src  = (uintptr_t *) BSP_PRV_SECTION_VECTOR_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_VECTOR_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_END - (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START;
+    bsp_copy_multibyte(src, dst, size);
+
+    /* Copy user program block */
+    src  = (uintptr_t *) BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_USER_PRG_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_USER_PRG_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_PRG_RAM_START;
+    bsp_copy_multibyte(src, dst, size);
+
+    /* Copy user data block */
+    src  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_START;
+    bsp_copy_multibyte(src, dst, size);
+
+    /* Copy shared non-cache buffer block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_RAM_END -
+           (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_RAM_START;
+    bsp_copy_multibyte(src, dst, size);
+ #else
+    if ((0 != (R_SYSC_NS->RSTSR0 & BSP_PRV_RSTSR0_CPU_RESET_MASK)) || BSP_PRV_SOFTWARE_RESET_OCCURRED)
+    {
+        if (0 != secondary_rom_address)
+        {
+            address_diff = (uintptr_t) BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS -
+                           (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START;
+
+            /* Copy secondary user data block */
+            src  = (uintptr_t *) (secondary_rom_address + address_diff);
+            dst  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_RAM_START;
+            size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_START;
+            bsp_copy_multibyte(src, dst, size);
+        }
+    }
+ #endif
+ #if (1 == _RZN_ORDINAL) || \
+    (defined(__ICCARM__) && (BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA || defined(BSP_CFG_CORE_CA55)))
+
+    /* Copy user data_noncache block */
+    src  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END -
+           (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START;
+    bsp_copy_multibyte(src, dst, size);
+
+    /* Copy DMAC link mode data block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_DMAC_LINK_MODE_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_END -
+           (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_START;
+    bsp_copy_multibyte(src, dst, size);
+
+    /* Copy non-cache buffer block. */
+    src  = (uintptr_t *) BSP_PRV_SECTION_NONCACHE_BUFFER_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_END -
+           (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_START;
+    bsp_copy_multibyte(src, dst, size);
+ #else
+    if ((0 != (R_SYSC_NS->RSTSR0 & BSP_PRV_RSTSR0_CPU_RESET_MASK)) || BSP_PRV_SOFTWARE_RESET_OCCURRED)
+    {
+        if (0 != secondary_rom_address)
+        {
+            address_diff = (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS -
+                           (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START;
+
+            /* Copy secondary user data_noncache block */
+            src  = (uintptr_t *) (secondary_rom_address + address_diff);
+            dst  = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START;
+            size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END -
+                   (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START;
+            bsp_copy_multibyte(src, dst, size);
+
+            address_diff = (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_ROM_ADDRESS -
+                           (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START;
+
+            /* Copy secondary DMAC link mode data block. */
+            src  = (uintptr_t *) (secondary_rom_address + address_diff);
+            dst  = (uintptr_t *) BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_START;
+            size = (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_END -
+                   (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_RAM_START;
+            bsp_copy_multibyte(src, dst, size);
+
+            address_diff = (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_ROM_ADDRESS -
+                           (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START;
+
+            /* Copy secondary non-cache buffer block. */
+            src  = (uintptr_t *) (secondary_rom_address + address_diff);
+            dst  = (uintptr_t *) BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_START;
+            size = (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_END -
+                   (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_RAM_START;
+            bsp_copy_multibyte(src, dst, size);
+        }
+    }
+ #endif
+ #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+  #if (1 == _RZN_ORDINAL)
+
+    /* Copy secondary core application */
+    src  = (uintptr_t *) BSP_PRV_SECTION_SECONDARY_ROM_ADDRESS;
+    dst  = (uintptr_t *) BSP_PRV_SECTION_SECONDARY_RAM_START;
+    size = (uintptr_t) BSP_PRV_SECTION_SECONDARY_RAM_END -
+           (uintptr_t) BSP_PRV_SECTION_SECONDARY_RAM_START;
+
+    if ((0 == (R_SYSC_NS->RSTSR0 & BSP_PRV_RSTSR0_CPU_RESET_MASK)) && !BSP_PRV_SOFTWARE_RESET_OCCURRED)
+    {
+        bsp_copy_multibyte(src, dst, size);
+    }
+    else
+    {
+        size = 0;
+    }
+  #else
+    size = (uintptr_t) BSP_PRV_SECTION_SECONDARY_RAM_END -
+           (uintptr_t) BSP_PRV_SECTION_SECONDARY_RAM_START;
+  #endif
+
+    if (0 != size)
+    {
+        bsp_cpu_reset_release();
+    }
+ #endif
+
+    R_BSP_CacheCleanAll();
+}
+
+ #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM) || (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+
+/*******************************************************************************************************************//**
+ * Reset release each CPU
+ **********************************************************************************************************************/
+void bsp_cpu_reset_release (void)
+{
+    uint32_t image_info_cpu;
+
+  #if (1 == BSP_FEATURE_BSP_HAS_CR52_CPU1_TCM)
+    uint32_t * dst;
+  #endif
+
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+
+    image_info_cpu = *(uint32_t *) (BSP_PRV_IMAGE_INFO_NEXT_CORE_ADDRESS + BSP_PRV_IMAGE_INFO_OFFSET);
+
+    switch (image_info_cpu)
+    {
+        case BSP_PRIV_ASSIGNMENT_CPU_CR52_0:
+        {
+  #if (1 == BSP_FEATURE_BSP_HAS_CR52_CPU1_TCM)
+            R_BSP_CacheCleanAll();
+
+            dst    = (uint32_t *) BSP_PRV_ATCM_AXIS_CR520_ADDRESS;
+            *dst++ = BSP_PRV_IMAGE_INFO_BRANCH_INSTRUCTION_CR520;
+            __asm volatile ("DSB SY");
+            *dst++ = BSP_PRV_IMAGE_INFO_BRANCH_ADDRESS;
+            __asm volatile ("DSB SY");
+
+            R_BSP_CPUResetAutoRelease(BSP_RESET_CR52_0);
+  #endif
+
+            break;
+        }
+
+        case BSP_PRIV_ASSIGNMENT_CPU_CR52_1:
+        {
+  #if (0 == BSP_FEATURE_BSP_HAS_CR52_CPU1_TCM)
+
+            /* Release CR52_CPU1 reset state. */
+            R_BSP_CPUResetRelease(BSP_RESET_CR52_1);
+  #elif (1 == BSP_FEATURE_BSP_HAS_CR52_CPU1_TCM)
+            R_BSP_CacheCleanAll();
+
+            R_BSP_MODULE_START(FSP_IP_CR52, 1U);
+
+            /* Release CR52_CPU1 reset state. */
+            R_BSP_CPUResetRelease(BSP_RESET_CR52_1);
+
+            /* Release from the slave stop state */
+            R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+            R_SSC->SSTPCR7 = (uint32_t) ((uintptr_t) (R_SSC->SSTPCR7 & ~R_SSC_SSTPCR7_AXIS1_REQ_Msk));
+
+            /* Polling ACK bit in SSTPCR */
+            FSP_HARDWARE_REGISTER_WAIT(R_SSC->SSTPCR7_b.AXIS1_ACK, 0);
+
+   #if defined(BSP_CFG_CORE_CR52)
+            __asm volatile (
+                "    MOVS   r1, #0                    \n"
+                "    MOVS   r2, %[dst_cpu1]           \n"
+                "    MOVS   r0, %[inst]               \n"
+                "    STRD   r0, r1, [r2]              \n"
+                "    DSB SY                           \n"
+                "    MOVS   r0, %[addr]               \n"
+                "    STRD   r0, r1, [r2, #8]          \n"
+                "    DSB SY                           \n"
+                ::[inst] "r" (BSP_PRV_IMAGE_INFO_BRANCH_INSTRUCTION_CR521),
+                [addr] "r" (BSP_PRV_IMAGE_INFO_BRANCH_ADDRESS),
+                [dst_cpu1] "r" (BSP_PRV_ATCM_AXIS_CR521_ADDRESS) : "memory", "r0", "r1", "r2");
+   #elif defined(BSP_CFG_CORE_CA55)
+            uint64_t * dst_cpu1 = (uint64_t *) BSP_PRV_ATCM_AXIS_CR521_ADDRESS;
+            *dst_cpu1++ = BSP_PRV_IMAGE_INFO_BRANCH_INSTRUCTION_CR521;
+            __asm volatile ("DSB SY");
+            *dst_cpu1++ = BSP_PRV_IMAGE_INFO_BRANCH_ADDRESS;
+            __asm volatile ("DSB SY");
+   #endif
+
+            R_TCMAW->CPU1HALT = 0x00000000;
+            R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+  #endif
+
+            break;
+        }
+
+  #if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+        case BSP_PRIV_ASSIGNMENT_CPU_CA55_0:
+        {
+            R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+            R_CA55->RVBA[0].L = (uint32_t) (BSP_PRV_IMAGE_INFO_NEXT_CORE_ADDRESS + BSP_PRV_LOADER_TEXT_OFFSET);
+            R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+
+            R_BSP_MODULE_START(FSP_IP_CA55, 0U);
+
+            R_BSP_CPUResetRelease(BSP_RESET_CA55_CLUSTER);
+            R_BSP_CacheCleanAll();
+            R_BSP_CPUResetRelease(BSP_RESET_CA55_0);
+            R_BSP_CacheCleanAll();
+
+            break;
+        }
+
+        case BSP_PRIV_ASSIGNMENT_CPU_CA55_1:
+        {
+            R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+            R_CA55->RVBA[1].L = (uint32_t) (BSP_PRV_IMAGE_INFO_NEXT_CORE_ADDRESS + BSP_PRV_LOADER_TEXT_OFFSET);
+            R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+
+            R_BSP_MODULE_START(FSP_IP_CA55, 1U);
+
+            R_BSP_CPUResetRelease(BSP_RESET_CA55_CLUSTER);
+            R_BSP_CacheCleanAll();
+            R_BSP_CPUResetRelease(BSP_RESET_CA55_1);
+            R_BSP_CacheCleanAll();
+
+            break;
+        }
+
+        case BSP_PRIV_ASSIGNMENT_CPU_CA55_2:
+        {
+            R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+            R_CA55->RVBA[2].L = (uint32_t) (BSP_PRV_IMAGE_INFO_NEXT_CORE_ADDRESS + BSP_PRV_LOADER_TEXT_OFFSET);
+            R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+
+            R_BSP_MODULE_START(FSP_IP_CA55, 2U);
+
+            R_BSP_CPUResetRelease(BSP_RESET_CA55_CLUSTER);
+            R_BSP_CacheCleanAll();
+            R_BSP_CPUResetRelease(BSP_RESET_CA55_2);
+            R_BSP_CacheCleanAll();
+
+            break;
+        }
+
+        case BSP_PRIV_ASSIGNMENT_CPU_CA55_3:
+        {
+            R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+            R_CA55->RVBA[3].L = (uint32_t) (BSP_PRV_IMAGE_INFO_NEXT_CORE_ADDRESS + BSP_PRV_LOADER_TEXT_OFFSET);
+            R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+
+            R_BSP_MODULE_START(FSP_IP_CA55, 3U);
+
+            R_BSP_CPUResetRelease(BSP_RESET_CA55_CLUSTER);
+            R_BSP_CacheCleanAll();
+            R_BSP_CPUResetRelease(BSP_RESET_CA55_3);
+            R_BSP_CacheCleanAll();
+
+            break;
+        }
+  #endif
+
+        default:
+        {
+            break;
+        }
+    }
+
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+}
+
+ #endif
+
+ #if (1 != _RZN_ORDINAL)
+
+/*******************************************************************************************************************//**
+ * Searches for the ROM address where its binary is located.
+ *
+ * @retval ROM address where its binary is located.
+ **********************************************************************************************************************/
+uintptr_t bsp_secondary_search_rom_address (void)
+{
+    uintptr_t secondary_rom_address_start;
+    uintptr_t secondary_rom_address_end;
+    uint32_t  image_info_cpu;
+
+    secondary_rom_address_start = (BSP_PRV_ROM_BASE_ADDRESS + BSP_PRV_SECONDARY_ADDRESS_ALIGN);
+    secondary_rom_address_end   = (BSP_PRV_ROM_BASE_ADDRESS + BSP_PRV_ROM_SIZE);
+
+    while (secondary_rom_address_end > secondary_rom_address_start)
+    {
+        image_info_cpu = *(uint32_t *) (secondary_rom_address_start + BSP_PRV_IMAGE_INFO_OFFSET);
+        switch (image_info_cpu)
+        {
+  #if defined(BSP_CFG_CORE_CR52)
+   #if (0 == BSP_CFG_CORE_CR52)
+            case BSP_PRIV_ASSIGNMENT_CPU_CR52_0:
+   #elif (1 == BSP_CFG_CORE_CR52)
+            case BSP_PRIV_ASSIGNMENT_CPU_CR52_1:
+   #endif
+  #elif defined(BSP_CFG_CORE_CA55)
+   #if (0 == BSP_CFG_CORE_CA55)
+            case BSP_PRIV_ASSIGNMENT_CPU_CA55_0:
+   #elif (1 == BSP_CFG_CORE_CA55)
+            case BSP_PRIV_ASSIGNMENT_CPU_CA55_1:
+   #elif (2 == BSP_CFG_CORE_CA55)
+            case BSP_PRIV_ASSIGNMENT_CPU_CA55_2:
+   #elif (3 == BSP_CFG_CORE_CA55)
+            case BSP_PRIV_ASSIGNMENT_CPU_CA55_3:
+   #endif
+  #endif
+                {
+                    return secondary_rom_address_start;
+                }
+
+            default:
+            {
+                secondary_rom_address_start += BSP_PRV_SECONDARY_ADDRESS_ALIGN;
+                break;
+            }
+        }
+    }
+
+    return 0;
+}
+
+ #endif
+#endif
+
+#if defined(BSP_CFG_CORE_CR52)
+ #if (BSP_FEATURE_TFU_SUPPORTED & BSP_CFG_USE_TFU_MATHLIB)
+void bsp_tfu_init (void)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+  #if (1 != BSP_FEATURE_TFU_UNIT_NUMBER)
+    R_BSP_MODULE_START(FSP_IP_TFU, 0U);
+  #else
+    R_BSP_MODULE_START(FSP_IP_TFU, 1U);
+  #endif
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+  #if 2 == BSP_FEATURE_TFU_VERSION
+   #if (1 == BSP_FEATURE_TFU_UNIT)
+    #if (1 == _RZN_ORDINAL)
+    R_TFU->FXSCIOC_b.IUF = BSP_CFG_TFU_FIXED_POINT_SINCOS_INPUT_SETTING;
+    R_TFU->FXSCIOC_b.OF  = BSP_CFG_TFU_FIXED_POINT_SINCOS_OUTPUT_SETTING;
+    R_TFU->FXATIOC_b.OUF = BSP_CFG_TFU_FIXED_POINT_ARCTAN_OUTPUT_SETTING;
+    #endif
+   #else
+    #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+    R_TFU0->FXSCIOC_b.IUF = BSP_CFG_TFU_FIXED_POINT_SINCOS_INPUT_SETTING;
+    R_TFU0->FXSCIOC_b.OF  = BSP_CFG_TFU_FIXED_POINT_SINCOS_OUTPUT_SETTING;
+    R_TFU0->FXATIOC_b.OUF = BSP_CFG_TFU_FIXED_POINT_ARCTAN_OUTPUT_SETTING;
+    #else
+    R_TFU1->FXSCIOC_b.IUF = BSP_CFG_TFU_FIXED_POINT_SINCOS_INPUT_SETTING;
+    R_TFU1->FXSCIOC_b.OF  = BSP_CFG_TFU_FIXED_POINT_SINCOS_OUTPUT_SETTING;
+    R_TFU1->FXATIOC_b.OUF = BSP_CFG_TFU_FIXED_POINT_ARCTAN_OUTPUT_SETTING;
+    #endif
+   #endif
+  #endif
+}
+
+ #endif
+#endif
+
+#if !BSP_CFG_PORT_PROTECT
+void bsp_release_port_protect (void)
+{
+    /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+     * disable writes. */
+    R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO);
+    R_RWP_S->PRCRS  = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO);
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Initialize static constructors.
+ **********************************************************************************************************************/
+#if BSP_CFG_C_RUNTIME_INIT
+void bsp_static_constructor_init (void)
+{
+ #if defined(__ICCARM__)
+  #if !(BSP_CFG_RAM_EXECUTION)
+
+    /* In the case of ROM boot, initialization of static constructors is performed by __iar_data_init3(). */
+    __iar_data_init3();
+  #endif
+ #elif defined(__GNUC__)
+    intptr_t count;
+    intptr_t i;
+
+    count = __preinit_array_end - __preinit_array_start;
+    for (i = 0; i < count; i++)
+    {
+        __preinit_array_start[i]();
+    }
+
+    count = __init_array_end - __init_array_start;
+    for (i = 0; i < count; i++)
+    {
+        __init_array_start[i]();
+    }
+ #endif
+}
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.c
new file mode 100644
index 00000000..fe81b9a9
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.c
@@ -0,0 +1,77 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "bsp_address_expander.h"
+
+#if (1 == BSP_FEATURE_ADDRESS_EXPANDER_SUPPORTED)
+ #if (1 == _RZN_ORDINAL)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Private definition to set address expander values. */
+  #define BSP_PRV_ADX_DDRMIR1_BITS     (24)
+  #define BSP_PRV_ADX_DDRMIR0_BITS     (16)
+  #define BSP_PRV_ADX_PCIE1MIR_BITS    (8)
+  #define BSP_PRV_ADX_PCIE0MIR_BITS    (0)
+
+  #define BSP_PRV_STARTUP_ADX(index)                                               \
+    (BSP_CFG_ADX ## index ## _DDR_MIRROR1_ADDRESS << BSP_PRV_ADX_DDRMIR1_BITS) |   \
+    (BSP_CFG_ADX ## index ## _DDR_MIRROR0_ADDRESS << BSP_PRV_ADX_DDRMIR0_BITS) |   \
+    (BSP_CFG_ADX ## index ## _PCIE1_MIRROR_ADDRESS << BSP_PRV_ADX_PCIE1MIR_BITS) | \
+    (BSP_CFG_ADX ## index ## _PCIE0_MIRROR_ADDRESS << BSP_PRV_ADX_PCIE0MIR_BITS)
+
+  #define BSP_PRV_STARTUP_ADX_NO_PCIE(index)                                     \
+    (BSP_CFG_ADX ## index ## _DDR_MIRROR1_ADDRESS << BSP_PRV_ADX_DDRMIR1_BITS) | \
+    (BSP_CFG_ADX ## index ## _DDR_MIRROR0_ADDRESS << BSP_PRV_ADX_DDRMIR0_BITS)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Configure Address Expander.
+ * @param[in]    None
+ * @param[out]   None
+ * @note         This function supports configurable the registers of Address Expander.
+ * @retval       None
+ **********************************************************************************************************************/
+void bsp_address_expander_init (void)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+
+    R_ADXC0->ADXCTL0  = BSP_PRV_STARTUP_ADX(0);
+    R_ADXC0->ADXCTL1  = BSP_PRV_STARTUP_ADX(1);
+    R_ADXC0->ADXCTL2  = BSP_PRV_STARTUP_ADX(2);
+    R_ADXC0->ADXCTL3  = BSP_PRV_STARTUP_ADX(3);
+    R_ADXC0->ADXCTL4  = BSP_PRV_STARTUP_ADX(4);
+    R_ADXC0->ADXCTL5  = BSP_PRV_STARTUP_ADX_NO_PCIE(5);
+    R_ADXC1->ADXCTL6  = BSP_PRV_STARTUP_ADX_NO_PCIE(6);
+    R_ADXC1->ADXCTL7  = BSP_PRV_STARTUP_ADX_NO_PCIE(7);
+    R_ADXC1->ADXCTL8  = BSP_PRV_STARTUP_ADX_NO_PCIE(8);
+    R_ADXC1->ADXCTL9  = BSP_PRV_STARTUP_ADX_NO_PCIE(9);
+    R_ADXC1->ADXCTL10 = BSP_PRV_STARTUP_ADX_NO_PCIE(10);
+    R_ADXC1->ADXCTL11 = BSP_PRV_STARTUP_ADX_NO_PCIE(11);
+    R_ADXC1->ADXCTL12 = BSP_PRV_STARTUP_ADX_NO_PCIE(12);
+
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+}
+
+ #endif
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.h
new file mode 100644
index 00000000..5d40cf1c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.h
@@ -0,0 +1,48 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_ADDRESS_EXPANDER_H
+#define BSP_ADDRESS_EXPANDER_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+#if BSP_FEATURE_ADDRESS_EXPANDER_SUPPORTED
+ #if (1 == _RZN_ORDINAL)
+
+void bsp_address_expander_init(void);  // Used internally by BSP
+
+ #endif
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_cache.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_cache.c
new file mode 100644
index 00000000..3fc9f2af
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_cache.c
@@ -0,0 +1,738 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_PRV_SCTLR_ELX_BIT_I                 (0x1000U)
+#define BSP_PRV_SCTLR_ELX_BIT_C                 (0x4U)
+#define BSP_PRV_SCTLR_ELX_BIT_M                 (0x1U)
+
+#define BSP_PRV_CLIDR_CTYPE_OFFSET              (3U)
+#define BSP_PRV_CLIDR_CTYPE_MASK                (7U)
+#define BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE     (2U)
+#define BSP_PRV_CLIDR_LOC_OFFSET                (24U)
+#define BSP_PRV_CLIDR_LOC_MASK                  (7U)
+
+#define BSP_PRV_CCSIDR_LINESIZE_OFFSET          (0U)
+#define BSP_PRV_CCSIDR_LINESIZE_MASK            (7U)
+#define BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE    (4U)
+#define BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET     (3U)
+#define BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK       (0x3FFU)
+#define BSP_PRV_CCSIDR_NUMSETS_OFFSET           (13U)
+#define BSP_PRV_CCSIDR_NUMSETS_MASK             (0x7FFFU)
+#define BSP_PRV_CCSIDR_SHIFT_MAX                (32U)
+
+#define BSP_PRV_CSSELR_LEVEL_OFFSET             (1U)
+
+#define BSP_PRV_CTR_IMINLINE_OFFSET             (0U)
+#define BSP_PRV_CTR_IMINLINE_MASK               (0xFU)
+#define BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS    (4U)
+#define BSP_PRV_CTR_IMINLINE_ADDRESS_MASK       (1U)
+#define BSP_PRV_CTR_DMINLINE_OFFSET             (16U)
+#define BSP_PRV_CTR_DMINLINE_MASK               (0xFU)
+#define BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS    (4U)
+#define BSP_PRV_CTR_DMINLINE_ADDRESS_MASK       (1U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Enable instruction caching.
+ **********************************************************************************************************************/
+void R_BSP_CacheEnableInst (void)
+{
+    uintptr_t sctlr;
+
+    sctlr  = __get_SCTLR();
+    sctlr |= BSP_PRV_SCTLR_ELX_BIT_I;
+
+    __asm volatile ("DSB SY");
+
+    __set_SCTLR(sctlr);
+
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Enable data caching.
+ **********************************************************************************************************************/
+void R_BSP_CacheEnableData (void)
+{
+    uintptr_t sctlr;
+
+    sctlr  = __get_SCTLR();
+    sctlr |= BSP_PRV_SCTLR_ELX_BIT_C;
+
+    __asm volatile ("DSB SY");
+
+    __set_SCTLR(sctlr);
+
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Enable memory protect.
+ **********************************************************************************************************************/
+void R_BSP_CacheEnableMemoryProtect (void)
+{
+    uintptr_t sctlr;
+
+    sctlr  = __get_SCTLR();
+    sctlr |= BSP_PRV_SCTLR_ELX_BIT_M;
+
+    __asm volatile ("DSB SY");
+
+    __set_SCTLR(sctlr);
+
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Disable instruction caching.
+ **********************************************************************************************************************/
+void R_BSP_CacheDisableInst (void)
+{
+    uintptr_t sctlr;
+
+    sctlr  = __get_SCTLR();
+    sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_I);
+
+    __asm volatile ("DSB SY");
+
+    __set_SCTLR(sctlr);
+
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Disable data caching.
+ **********************************************************************************************************************/
+void R_BSP_CacheDisableData (void)
+{
+    uintptr_t sctlr;
+
+    sctlr  = __get_SCTLR();
+    sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_C);
+
+    __asm volatile ("DSB SY");
+
+    __set_SCTLR(sctlr);
+
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Disable memory protect.
+ **********************************************************************************************************************/
+void R_BSP_CacheDisableMemoryProtect (void)
+{
+    uintptr_t sctlr;
+
+    sctlr  = __get_SCTLR();
+    sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_M);
+
+    __asm volatile ("DSB SY");
+
+    __set_SCTLR(sctlr);
+
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Clean data cache by set/way.
+ * Clean means writing the cache data to memory and clear the dirty bits
+ * if there is a discrepancy between the cache and memory data.
+ **********************************************************************************************************************/
+void R_BSP_CacheCleanAll (void)
+{
+    uintptr_t clidr;
+    uintptr_t clidr_loc;
+    uintptr_t clidr_ctype;
+    uintptr_t clidr_ctype_shift;
+
+    uintptr_t csselr;
+    uintptr_t csselr_level;
+
+    uintptr_t ccsidr;
+    uintptr_t ccsidr_linesize;
+    uintptr_t ccsidr_associativity;
+    uintptr_t ccsidr_associativity_clz;
+    uintptr_t ccsidr_associativity_value;
+    uintptr_t ccsidr_associativity_msb;
+    uintptr_t ccsidr_numsets;
+    uintptr_t ccsidr_numsets_total;
+
+    uintptr_t dccsw;
+
+    __asm volatile ("DSB SY");
+
+    __set_ICIALLU(0);
+
+    __asm volatile ("DMB SY");
+
+    /* Reads the maximum level of cache implemented */
+    clidr     = __get_CLIDR();
+    clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK;
+
+    /* If the cache does not exist, do not process */
+    if (0 != clidr_loc)
+    {
+        /* Loop until all levels of cache are processed */
+        for (csselr = 0; csselr < clidr_loc; csselr++)
+        {
+            /* Read the current level cache type */
+            clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET;
+            clidr_ctype       = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK;
+
+            /* If no data cache exists in the current level of cache, do not process  */
+            if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype)
+            {
+                /* Set the current level to Cache Size Selection Register */
+                csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET;
+                __set_CSSELR(csselr_level);
+
+                __asm volatile ("DSB SY");
+
+                /* Read the line size, number of ways, and number of sets for the current level of cache */
+                ccsidr          = __get_CCSIDR();
+                ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) +
+                                  BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE;
+                ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) &
+                                       BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK;
+                ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK;
+
+                /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */
+                ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity);
+                if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz)
+                {
+                    ccsidr_associativity_clz--;
+                }
+                else
+                {
+                    /* Do Nothing */
+                }
+
+                /* Loop until all sets are processed */
+                while (1)
+                {
+                    /* Working copy of number of ways */
+                    ccsidr_associativity_value = ccsidr_associativity;
+
+                    /* Loop until all ways are processed */
+                    while (1)
+                    {
+                        ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) |
+                                                   csselr_level;                                /* Left shift way */
+                        ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize;               /* Left shift set */
+                        dccsw                = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */
+
+                        /* DCCSW - Data or unified Cache line Clean by Set/Way */
+                        __set_DCCSW(dccsw);
+
+                        if (0 != ccsidr_associativity_value)
+                        {
+                            ccsidr_associativity_value--;
+                        }
+                        else
+                        {
+                            break;
+                        }
+                    }
+
+                    if (0 != ccsidr_numsets)
+                    {
+                        ccsidr_numsets--;
+                    }
+                    else
+                    {
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                /* Do Nothing */
+            }
+        }
+
+        __asm volatile ("DSB SY");
+        __asm volatile ("ISB SY");
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Invalidate data cache by set/way.
+ * Also Invalidate instruction cache.
+ *
+ * Invalidate means to delete cache data.
+ **********************************************************************************************************************/
+void R_BSP_CacheInvalidateAll (void)
+{
+    uintptr_t clidr;
+    uintptr_t clidr_loc;
+    uintptr_t clidr_ctype;
+    uintptr_t clidr_ctype_shift;
+
+    uintptr_t csselr;
+    uintptr_t csselr_level;
+
+    uintptr_t ccsidr;
+    uintptr_t ccsidr_linesize;
+    uintptr_t ccsidr_associativity;
+    uintptr_t ccsidr_associativity_clz;
+    uintptr_t ccsidr_associativity_value;
+    uintptr_t ccsidr_associativity_msb;
+    uintptr_t ccsidr_numsets;
+    uintptr_t ccsidr_numsets_total;
+
+    uintptr_t dcisw;
+
+    __asm volatile ("DSB SY");
+
+    __set_ICIALLU(0);
+
+    __asm volatile ("DMB SY");
+
+    /* Reads the maximum level of cache implemented */
+    clidr     = __get_CLIDR();
+    clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK;
+
+    /* If the cache does not exist, do not process */
+    if (0 != clidr_loc)
+    {
+        /* Loop until all levels of cache are processed */
+        for (csselr = 0; csselr < clidr_loc; csselr++)
+        {
+            /* Read the current level cache type */
+            clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET;
+            clidr_ctype       = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK;
+
+            /* If no data cache exists in the current level of cache, do not process  */
+            if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype)
+            {
+                /* Set the current level to Cache Size Selection Register */
+                csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET;
+                __set_CSSELR(csselr_level);
+
+                __asm volatile ("DSB SY");
+
+                /* Read the line size, number of ways, and number of sets for the current level of cache */
+                ccsidr          = __get_CCSIDR();
+                ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) +
+                                  BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE;
+                ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) &
+                                       BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK;
+                ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK;
+
+                /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */
+                ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity);
+                if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz)
+                {
+                    ccsidr_associativity_clz--;
+                }
+                else
+                {
+                    /* Do Nothing */
+                }
+
+                /* Loop until all sets are processed */
+                while (1)
+                {
+                    /* Working copy of number of ways */
+                    ccsidr_associativity_value = ccsidr_associativity;
+
+                    /* Loop until all ways are processed */
+                    while (1)
+                    {
+                        ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) |
+                                                   csselr_level;                                /* Left shift way */
+                        ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize;               /* Left shift set */
+                        dcisw                = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */
+
+                        /* DCISW - Data or unified Cache line Invalidate by Set/Way */
+                        __set_DCISW(dcisw);
+
+                        if (0 != ccsidr_associativity_value)
+                        {
+                            ccsidr_associativity_value--;
+                        }
+                        else
+                        {
+                            break;
+                        }
+                    }
+
+                    if (0 != ccsidr_numsets)
+                    {
+                        ccsidr_numsets--;
+                    }
+                    else
+                    {
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                /* Do Nothing */
+            }
+        }
+
+        __asm volatile ("DSB SY");
+        __asm volatile ("ISB SY");
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Clean and Invalidate data cache by set/way.
+ * Also Invalidate instruction cache.
+ *
+ * Clean means writing the cache data to memory and clear the dirty bits
+ * if there is a discrepancy between the cache and memory data.
+ *
+ * Invalidate means to delete cache data.
+ **********************************************************************************************************************/
+void R_BSP_CacheCleanInvalidateAll (void)
+{
+    uintptr_t clidr;
+    uintptr_t clidr_loc;
+    uintptr_t clidr_ctype;
+    uintptr_t clidr_ctype_shift;
+
+    uintptr_t csselr;
+    uintptr_t csselr_level;
+
+    uintptr_t ccsidr;
+    uintptr_t ccsidr_linesize;
+    uintptr_t ccsidr_associativity;
+    uintptr_t ccsidr_associativity_clz;
+    uintptr_t ccsidr_associativity_value;
+    uintptr_t ccsidr_associativity_msb;
+    uintptr_t ccsidr_numsets;
+    uintptr_t ccsidr_numsets_total;
+
+    uintptr_t dccisw;
+
+    __asm volatile ("DSB SY");
+
+    __set_ICIALLU(0);
+
+    __asm volatile ("DMB SY");
+
+    /* Reads the maximum level of cache implemented */
+    clidr     = __get_CLIDR();
+    clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK;
+
+    /* If the cache does not exist, do not process */
+    if (0 != clidr_loc)
+    {
+        /* Loop until all levels of cache are processed */
+        for (csselr = 0; csselr < clidr_loc; csselr++)
+        {
+            /* Read the current level cache type */
+            clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET;
+            clidr_ctype       = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK;
+
+            /* If no data cache exists in the current level of cache, do not process  */
+            if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype)
+            {
+                /* Set the current level to Cache Size Selection Register */
+                csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET;
+                __set_CSSELR(csselr_level);
+
+                __asm volatile ("DSB SY");
+
+                /* Read the line size, number of ways, and number of sets for the current level of cache */
+                ccsidr          = __get_CCSIDR();
+                ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) +
+                                  BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE;
+                ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) &
+                                       BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK;
+                ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK;
+
+                /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */
+                ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity);
+                if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz)
+                {
+                    ccsidr_associativity_clz--;
+                }
+                else
+                {
+                    /* Do Nothing */
+                }
+
+                /* Loop until all sets are processed */
+                while (1)
+                {
+                    /* Working copy of number of ways */
+                    ccsidr_associativity_value = ccsidr_associativity;
+
+                    /* Loop until all ways are processed */
+                    while (1)
+                    {
+                        ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) |
+                                                   csselr_level;                                /* Left shift way */
+                        ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize;               /* Left shift set */
+                        dccisw               = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */
+
+                        /* DCCISW - Data or unified Cache line Clean and Invalidate by Set/Way */
+                        __set_DCCISW(dccisw);
+
+                        if (0 != ccsidr_associativity_value)
+                        {
+                            ccsidr_associativity_value--;
+                        }
+                        else
+                        {
+                            break;
+                        }
+                    }
+
+                    if (0 != ccsidr_numsets)
+                    {
+                        ccsidr_numsets--;
+                    }
+                    else
+                    {
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                /* Do Nothing */
+            }
+        }
+
+        __asm volatile ("DSB SY");
+        __asm volatile ("ISB SY");
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Clean data cache and Invalidate instruction cache by address.
+ *
+ * Clean means writing the cache data to memory and clear the dirty bits
+ * if there is a discrepancy between the cache and memory data.
+ *
+ * Invalidate means to delete cache data.
+ *
+ * @param[in] base_address    Start address of area you want to Clean.
+ * @param[in] length          Size of area you want to Clean.
+ **********************************************************************************************************************/
+void R_BSP_CacheCleanRange (uintptr_t base_address, uintptr_t length)
+{
+    uintptr_t end_address;
+    uintptr_t ctr;
+
+    uintptr_t dminline;
+    uintptr_t dminline_size;
+    uintptr_t dccvac;
+
+    uintptr_t iminline;
+    uintptr_t iminline_size;
+    uintptr_t icivau;
+
+    end_address = base_address + length;
+
+    /* Calculate data cache line size */
+    ctr           = __get_CTR();
+    dminline      = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK;
+    dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline);
+
+    /* Align base address with cache line */
+    dccvac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK);
+    do
+    {
+        /* Data or unified Cache line Clean by VA to PoC */
+        __set_DCCVAC(dccvac);
+
+        dccvac += dminline_size;       /* Next data line */
+    } while (end_address > dccvac);
+
+    __asm volatile ("DSB SY");
+
+    /* Calculate instruction cache line size */
+    iminline      = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK;
+    iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline);
+
+    /* Align base address with cache line */
+    icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK);
+    do
+    {
+        /* Instruction Cache line Invalidate by VA to PoU */
+        __set_ICIVAU(icivau);
+
+        icivau += iminline_size;       /* Next data line */
+    } while (end_address == icivau);
+
+    __asm volatile ("DSB SY");
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Invalidate instruction and data cache by address.
+ *
+ * Invalidate means to delete cache data.
+ *
+ * @param[in] base_address    Start address of area you want to Invalidate.
+ * @param[in] length          Size of area you want to Invalidate.
+ **********************************************************************************************************************/
+void R_BSP_CacheInvalidateRange (uintptr_t base_address, uintptr_t length)
+{
+    uintptr_t end_address;
+    uintptr_t ctr;
+
+    uintptr_t dminline;
+    uintptr_t dminline_size;
+    uintptr_t dcivac;
+
+    uintptr_t iminline;
+    uintptr_t iminline_size;
+    uintptr_t icivau;
+
+    end_address = base_address + length;
+
+    /* Calculate data cache line size */
+    ctr           = __get_CTR();
+    dminline      = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK;
+    dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline);
+
+    /* Align base address with cache line */
+    dcivac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK);
+    do
+    {
+        /* Data or unified Cache line Invalidate by VA to PoC */
+        __set_DCIVAC(dcivac);
+
+        dcivac += dminline_size;       /* Next data line */
+    } while (end_address > dcivac);
+
+    __asm volatile ("DSB SY");
+
+    /* Calculate instruction cache line size */
+    iminline      = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK;
+    iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline);
+
+    /* Align base address with cache line */
+    icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK);
+    do
+    {
+        /* Instruction Cache line Invalidate by VA to PoU */
+        __set_ICIVAU(icivau);
+
+        icivau += iminline_size;       /* Next data line */
+    } while (end_address == icivau);
+
+    __asm volatile ("DSB SY");
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Clean and Invalidate data cache and Invalidate instruction cache by address.
+ *
+ * Clean means writing the cache data to memory and clear the dirty bits
+ * if there is a discrepancy between the cache and memory data.
+ *
+ * Invalidate means to delete cache data.
+ *
+ * @param[in] base_address    Start address of area you want to Clean and Invalidate.
+ * @param[in] length          Size of area you want to Clean and Invalidate.
+ **********************************************************************************************************************/
+void R_BSP_CacheCleanInvalidateRange (uintptr_t base_address, uintptr_t length)
+{
+    uintptr_t end_address;
+    uintptr_t ctr;
+
+    uintptr_t dminline;
+    uintptr_t dminline_size;
+    uintptr_t dccivac;
+
+    uintptr_t iminline;
+    uintptr_t iminline_size;
+    uintptr_t icivau;
+
+    end_address = base_address + length;
+
+    /* Calculate data cache line size */
+    ctr           = __get_CTR();
+    dminline      = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK;
+    dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline);
+
+    /* Align base address with cache line */
+    dccivac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK);
+    do
+    {
+        /* Data or unified Cache line Clean and Invalidate by VA to PoC */
+        __set_DCCIVAC(dccivac);
+
+        dccivac += dminline_size;      /* Next data line */
+    } while (end_address > dccivac);
+
+    __asm volatile ("DSB SY");
+
+    /* Calculate instruction cache line size */
+    iminline      = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK;
+    iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline);
+
+    /* Align base address with cache line */
+    icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK);
+    do
+    {
+        /* Instruction Cache line Invalidate by VA to PoU */
+        __set_ICIVAU(icivau);
+
+        icivau += iminline_size;       /* Next data line */
+    } while (end_address == icivau);
+
+    __asm volatile ("DSB SY");
+    __asm volatile ("ISB SY");
+}
+
+/*******************************************************************************************************************//**
+ * Powers on and off the L3 cache way.
+ * CA55 only.
+ **********************************************************************************************************************/
+void R_BSP_CacheL3PowerCtrl (void)
+{
+    r_bsp_cache_l3_power_ctrl();
+}
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup BSP_MCU)
+ **********************************************************************************************************************/
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_cache.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_cache.h
new file mode 100644
index 00000000..45b8f305
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_cache.h
@@ -0,0 +1,55 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_CACHE_H
+#define BSP_CACHE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#if defined(BSP_CFG_CORE_CR52)
+ #include "cr/bsp_cache_core.h"
+#elif defined(BSP_CFG_CORE_CA55)
+ #include "ca/bsp_cache_core.h"
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+void R_BSP_CacheEnableInst(void);
+void R_BSP_CacheEnableData(void);
+void R_BSP_CacheEnableMemoryProtect(void);
+void R_BSP_CacheDisableInst(void);
+void R_BSP_CacheDisableData(void);
+void R_BSP_CacheDisableMemoryProtect(void);
+void R_BSP_CacheCleanAll(void);
+void R_BSP_CacheInvalidateAll(void);
+void R_BSP_CacheCleanInvalidateAll(void);
+void R_BSP_CacheCleanRange(uintptr_t base_address, uintptr_t length);
+void R_BSP_CacheInvalidateRange(uintptr_t base_address, uintptr_t length);
+void R_BSP_CacheCleanInvalidateRange(uintptr_t base_address, uintptr_t length);
+void R_BSP_CacheL3PowerCtrl(void);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_clocks.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_clocks.c
new file mode 100644
index 00000000..491be5bf
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_clocks.c
@@ -0,0 +1,798 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_clocks.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY                                     (0xA500U)
+#define BSP_PRV_PRCR_CGC_UNLOCK                              ((BSP_PRV_PRCR_KEY) | 0x3U)
+#define BSP_PRV_PRCR_LOCK                                    ((BSP_PRV_PRCR_KEY) | 0x0U)
+
+/* Key code for writing  PCMD register. */
+#define BSP_PRV_PCMD_KEY                                     (0xA5U)
+
+/* Calculate the value to write to SCKCR. */
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS    (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U)
+ #define BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS    ((BSP_CFG_FSELXSPI1_DIVSELXSPI1 & 0x47U) << 8U)
+ #define BSP_PRV_STARTUP_SCKCR_CKIO_BITS                     ((BSP_CFG_CKIO & 7U) << 16U)
+ #define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS                ((BSP_CFG_FSELCANFD & 1U) << 20U)
+ #define BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS                   ((BSP_CFG_PHYSEL & 1U) << 21U)
+ #define BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS                  ((BSP_CFG_CLMASEL & 1U) << 22U)
+ #define BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS             ((BSP_CFG_SPI0ASYNCCLK & 1U) << 24U)
+ #define BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS             ((BSP_CFG_SPI1ASYNCCLK & 1U) << 25U)
+ #define BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS             ((BSP_CFG_SPI2ASYNCCLK & 1U) << 26U)
+ #define BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS             ((BSP_CFG_SCI0ASYNCCLK & 1U) << 27U)
+ #define BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS             ((BSP_CFG_SCI1ASYNCCLK & 1U) << 28U)
+ #define BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS             ((BSP_CFG_SCI2ASYNCCLK & 1U) << 29U)
+ #define BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS             ((BSP_CFG_SCI3ASYNCCLK & 1U) << 30U)
+ #define BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS             ((BSP_CFG_SCI4ASYNCCLK & 1U) << 31U)
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS    (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U)
+ #define BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS    ((BSP_CFG_FSELXSPI1_DIVSELXSPI1 & 0x47U) << 8U)
+ #define BSP_PRV_STARTUP_SCKCR_CKIO_BITS                     ((BSP_CFG_CKIO & 7U) << 16U)
+ #define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS                ((BSP_CFG_FSELCANFD & 1U) << 20U)
+ #define BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS                   ((BSP_CFG_PHYSEL & 1U) << 21U)
+ #define BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS                  ((BSP_CFG_CLMASEL & 1U) << 22U)
+#endif
+
+/* Calculate the value to write to SCKCR2. */
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS                (BSP_CFG_FSELCPU0 & 3U)
+ #if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM)
+  #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS               ((BSP_CFG_FSELCPU1 & 3U) << 2U)
+ #else
+  #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS               (0U)
+ #endif
+ #define BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS           (1U << 4U) // The write value should be 1.
+ #define BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS               ((BSP_CFG_DIVSELSUB & 1U) << 5U)
+ #define BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS            ((BSP_CFG_SPI3ASYNCCLK & 1U) << 24U)
+ #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS            ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U)
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR2_CR52CPU0_BITS                (BSP_CFG_CR52C0CLK & 3U)
+ #define BSP_PRV_STARTUP_SCKCR2_CR52CPU1_BITS                ((BSP_CFG_CR52C1CLK & 3U) << 2U)
+ #define BSP_PRV_STARTUP_SCKCR2_CA55CORE0_BITS               ((BSP_CFG_CA55CORE0 & 1U) << 8U)
+ #define BSP_PRV_STARTUP_SCKCR2_CA55CORE1_BITS               ((BSP_CFG_CA55CORE1 & 1U) << 9U)
+ #define BSP_PRV_STARTUP_SCKCR2_CA55CORE2_BITS               ((BSP_CFG_CA55CORE2 & 1U) << 10U)
+ #define BSP_PRV_STARTUP_SCKCR2_CA55CORE3_BITS               ((BSP_CFG_CA55CORE3 & 1U) << 11U)
+ #define BSP_PRV_STARTUP_SCKCR2_CA55SCLK_BITS                ((BSP_CFG_CA55SCLK & 1U) << 12U)
+ #define BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS            ((BSP_CFG_SPI3ASYNCCLK & 3U) << 16U)
+ #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS            ((BSP_CFG_SCI5ASYNCCLK & 3U) << 18U)
+#endif
+
+/* Calculate the value to write to SCKCR3. */
+#if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR3_SPI0ASYNCSEL_BITS            (BSP_CFG_SPI0ASYNCCLK & 3U)
+ #define BSP_PRV_STARTUP_SCKCR3_SPI1ASYNCSEL_BITS            ((BSP_CFG_SPI1ASYNCCLK & 3U) << 2U)
+ #define BSP_PRV_STARTUP_SCKCR3_SPI2ASYNCSEL_BITS            ((BSP_CFG_SPI2ASYNCCLK & 3U) << 4U)
+ #define BSP_PRV_STARTUP_SCKCR3_SCI0ASYNCSEL_BITS            ((BSP_CFG_SCI0ASYNCCLK & 3U) << 6U)
+ #define BSP_PRV_STARTUP_SCKCR3_SCI1ASYNCSEL_BITS            ((BSP_CFG_SCI1ASYNCCLK & 3U) << 8U)
+ #define BSP_PRV_STARTUP_SCKCR3_SCI2ASYNCSEL_BITS            ((BSP_CFG_SCI2ASYNCCLK & 3U) << 10U)
+ #define BSP_PRV_STARTUP_SCKCR3_SCI3ASYNCSEL_BITS            ((BSP_CFG_SCI3ASYNCCLK & 3U) << 12U)
+ #define BSP_PRV_STARTUP_SCKCR3_SCI4ASYNCSEL_BITS            ((BSP_CFG_SCI4ASYNCCLK & 3U) << 14U)
+ #define BSP_PRV_STARTUP_SCKCR3_LCDCDIVSEL_BITS              ((BSP_CFG_LCDCDIVSEL & 15U) << 20U)
+#endif
+
+/* Calculate the value to write to SCKCR4. */
+#if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE0ASYNCSEL_BITS           (BSP_CFG_SCIE0ASYNCCLK & 3U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE1ASYNCSEL_BITS           ((BSP_CFG_SCIE1ASYNCCLK & 3U) << 2U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE2ASYNCSEL_BITS           ((BSP_CFG_SCIE2ASYNCCLK & 3U) << 4U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE3ASYNCSEL_BITS           ((BSP_CFG_SCIE3ASYNCCLK & 3U) << 6U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE4ASYNCSEL_BITS           ((BSP_CFG_SCIE4ASYNCCLK & 3U) << 8U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE5ASYNCSEL_BITS           ((BSP_CFG_SCIE5ASYNCCLK & 3U) << 10U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE6ASYNCSEL_BITS           ((BSP_CFG_SCIE6ASYNCCLK & 3U) << 12U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE7ASYNCSEL_BITS           ((BSP_CFG_SCIE7ASYNCCLK & 3U) << 14U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE8ASYNCSEL_BITS           ((BSP_CFG_SCIE8ASYNCCLK & 3U) << 16U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE9ASYNCSEL_BITS           ((BSP_CFG_SCIE9ASYNCCLK & 3U) << 18U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE10ASYNCSEL_BITS          ((BSP_CFG_SCIE10ASYNCCLK & 3U) << 20U)
+ #define BSP_PRV_STARTUP_SCKCR4_SCIE11ASYNCSEL_BITS          ((BSP_CFG_SCIE11ASYNCCLK & 3U) << 22U)
+ #define BSP_PRV_STARTUP_SCKCR4_ENCOUTCLK_BITS               ((BSP_CFG_ENCOUTCLK & 1U) << 24U)
+#endif
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR                               (BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR_CKIO_BITS |                  \
+                                                              BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS |             \
+                                                              BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS |                \
+                                                              BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS |               \
+                                                              BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS |          \
+                                                              BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS |          \
+                                                              BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS |          \
+                                                              BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS |          \
+                                                              BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS |          \
+                                                              BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS |          \
+                                                              BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS |          \
+                                                              BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS)
+
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR                               (BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR_CKIO_BITS |                  \
+                                                              BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS |             \
+                                                              BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS |                \
+                                                              BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS)
+#endif
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR2                              (BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS |      \
+                                                              BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS |      \
+                                                              BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS |     \
+                                                              BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS)
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR2                              (BSP_PRV_STARTUP_SCKCR2_CR52CPU0_BITS |     \
+                                                              BSP_PRV_STARTUP_SCKCR2_CR52CPU1_BITS |     \
+                                                              BSP_PRV_STARTUP_SCKCR2_CA55CORE0_BITS |    \
+                                                              BSP_PRV_STARTUP_SCKCR2_CA55CORE1_BITS |    \
+                                                              BSP_PRV_STARTUP_SCKCR2_CA55CORE2_BITS |    \
+                                                              BSP_PRV_STARTUP_SCKCR2_CA55CORE3_BITS |    \
+                                                              BSP_PRV_STARTUP_SCKCR2_CA55SCLK_BITS |     \
+                                                              BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS)
+#endif
+
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR3                              (0U)
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR3                              (BSP_PRV_STARTUP_SCKCR3_SPI0ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR3_SPI1ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR3_SPI2ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR3_SCI0ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR3_SCI1ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR3_SCI2ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR3_SCI3ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR3_SCI4ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR3_LCDCDIVSEL_BITS)
+#endif
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR4                              (0U)
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #define BSP_PRV_STARTUP_SCKCR4                              (BSP_PRV_STARTUP_SCKCR4_SCIE0ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE1ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE2ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE3ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE4ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE5ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE6ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE7ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE8ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE9ASYNCSEL_BITS |  \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE10ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR4_SCIE11ASYNCSEL_BITS | \
+                                                              BSP_PRV_STARTUP_SCKCR4_ENCOUTCLK_BITS)
+#endif
+
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+
+ #define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_ICLK_MUL2           (BSP_CLOCKS_FSELCPU0_ICLK_MUL2 << \
+                                                              R_SYSC_S_SCKCR2_FSELCPU0_Pos)
+ #if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM)
+  #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_ICLK_MUL2          (BSP_CLOCKS_FSELCPU1_ICLK_MUL2 << \
+                                                              R_SYSC_S_SCKCR2_FSELCPU1_Pos)
+ #endif
+
+#endif
+
+/* Calculate the value to write to HIZCTRLEN. */
+#if (4 == BSP_FEATURE_CGC_CLMA_UNIT)
+ #define BSP_PRV_STARTUP_HIZCTRLEN       ((BSP_CFG_CLMA1MASK << 2) | (BSP_CFG_CLMA0MASK << 1) | \
+                                          BSP_CFG_CLMA3MASK)
+#elif (7 == BSP_FEATURE_CGC_CLMA_UNIT)
+ #define BSP_PRV_STARTUP_HIZCTRLEN       ((BSP_CFG_CLMA4MASK << 5) | \
+                                          (BSP_CFG_CLMA3MASK << 4) | \
+                                          (BSP_CFG_CLMA2MASK << 3) | \
+                                          (BSP_CFG_CLMA1MASK << 2) | \
+                                          (BSP_CFG_CLMA0MASK << 1) | \
+                                          (BSP_CFG_CLMA6MASK))
+#endif
+
+/* Calculate the value to write to PLL0_SSC_CTR */
+#if BSP_FEATURE_CGC_PLL0_STANDBY_STATE_SUPPORTED
+ #define BSP_PRV_STARTUP_PLL0_SSC_CTR    ((BSP_CFG_PLL0MFR << 24) | \
+                                          (BSP_CFG_PLL0MRR << 16) | \
+                                          (BSP_CFG_PLL0SSCEN << 0))
+#endif
+
+/* Calculate the value to write to PLL2_SSC_CTR */
+#if BSP_FEATURE_CGC_PLL2_STANDBY_STATE_SUPPORTED
+ #define BSP_PRV_STARTUP_PLL2_SSC_CTR    ((BSP_CFG_PLL2MFR << 24) | \
+                                          (BSP_CFG_PLL2MRR << 16) | \
+                                          (BSP_CFG_PLL2SSCEN << 0))
+
+#endif
+
+/* Calculate the value to write to PLL3_VCO_CTR */
+#if BSP_FEATURE_CGC_PLL3_STANDBY_STATE_SUPPORTED
+ #define BSP_PRV_STARTUP_PLL3_VCO_CTR0         ((BSP_CFG_PLL3P << 16) | \
+                                                (BSP_CFG_PLL3M << 0))
+
+ #define BSP_PRV_STARTUP_PLL3_VCO_CTR1         ((BSP_CFG_PLL3K << 16) | \
+                                                (BSP_CFG_PLL3S << 0))
+#endif
+
+/* Frequencies of clocks. */
+#define BSP_PRV_CPU_FREQ_600_MHZ               (600000000U) // CPU frequency is 600 MHz
+#define BSP_PRV_CPU_FREQ_500_MHZ               (500000000U) // CPU frequency is 500 MHz
+#define BSP_PRV_CPU_FREQ_200_MHZ               (200000000U) // CPU frequency is 200 MHz
+#define BSP_PRV_CPU_FREQ_150_MHZ               (150000000U) // CPU frequency is 150 MHz
+
+/* Command sequence for enabling CLMA. */
+#define BSP_PRV_CTL0_ENABLE_TARGET_CMD         (0x01)
+#define BSP_PRV_CTL0_ENABLE_REVERSED_CMD       (0xFE)
+#define BSP_PRV_CTL0_ENABLE_SETTING_TIMEOUT    (10U)
+
+#define BSP_PRV_LOCO_STABILIZATION_COUNT       (40000)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+#if !BSP_CFG_SOFT_RESET_SUPPORTED
+static void bsp_prv_clock_set_hard_reset(void);
+
+#endif
+
+/*******************************************************************************************************************//**
+ * @internal
+ * @addtogroup BSP_MCU_PRV Internal BSP Documentation
+ * @ingroup RENESAS_INTERNAL
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Update SystemCoreClock variable based on current clock settings.
+ **********************************************************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #if defined(BSP_CFG_CORE_CR52)
+    uint32_t devselsub = R_SYSC_S->SCKCR2_b.DIVSELSUB;
+    uint32_t fselcpu   = R_SYSC_S->SCKCR2_b.FSELCPU0;
+
+    if (0U == devselsub)
+    {
+        SystemCoreClock = BSP_PRV_CPU_FREQ_200_MHZ << fselcpu;
+    }
+    else
+    {
+        SystemCoreClock = BSP_PRV_CPU_FREQ_150_MHZ << fselcpu;
+    }
+ #endif
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+ #if defined(BSP_CFG_CORE_CR52)
+  #if (0 == BSP_CFG_CORE_CR52)
+    uint32_t cr52cpu = R_SYSC_S->SCKCR2_b.CR52CPU0;
+  #elif (1 == BSP_CFG_CORE_CR52)
+    uint32_t cr52cpu = R_SYSC_S->SCKCR2_b.CR52CPU1;
+  #endif
+    SystemCoreClock = BSP_PRV_CPU_FREQ_500_MHZ << cr52cpu;
+ #elif defined(BSP_CFG_CORE_CA55)
+  #if (0 == BSP_CFG_CORE_CA55)
+    uint32_t ca55core = R_SYSC_S->SCKCR2_b.CA55CORE0;
+  #elif (1 == BSP_CFG_CORE_CA55)
+    uint32_t ca55core = R_SYSC_S->SCKCR2_b.CA55CORE1;
+  #elif (2 == BSP_CFG_CORE_CA55)
+    uint32_t ca55core = R_SYSC_S->SCKCR2_b.CA55CORE2;
+  #elif (3 == BSP_CFG_CORE_CA55)
+    uint32_t ca55core = R_SYSC_S->SCKCR2_b.CA55CORE3;
+  #endif
+    SystemCoreClock = BSP_PRV_CPU_FREQ_600_MHZ << ca55core;
+ #endif
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Applies system core clock source and divider changes.  The MCU is expected to be in high speed mode during this
+ * configuration and the CGC registers are expected to be unlocked in PRCR.
+ *
+ * @param[in] sckcr                  Value to set in SCKCR register
+ * @param[in] sckcr2                 Value to set in SCKCR2 register
+ * @param[in] sckcr3                 Value to set in SCKCR3 register
+ * @param[in] sckcr4                 Value to set in SCKCR4 register
+ **********************************************************************************************************************/
+void bsp_prv_clock_set (uint32_t sckcr, uint32_t sckcr2, uint32_t sckcr3, uint32_t sckcr4)
+{
+    volatile uint32_t dummy;
+    sckcr  = sckcr & BSP_PRV_SCKCR_MASK;
+    sckcr2 = sckcr2 & BSP_PRV_SCKCR2_MASK;
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+    FSP_PARAMETER_NOT_USED(sckcr3);
+    FSP_PARAMETER_NOT_USED(sckcr4);
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+    sckcr3 = sckcr3 & BSP_PRV_SCKCR3_MASK;
+    sckcr4 = sckcr4 & BSP_PRV_SCKCR4_MASK;
+#endif
+
+    /* Set the system source clock */
+    R_SYSC_S->SCKCR2 = sckcr2;
+
+    /** In order to secure processing after clock frequency is changed,
+     *  dummy read the same register at least eight times.
+     *  Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+
+    R_SYSC_NS->SCKCR = sckcr;
+
+    /** In order to secure processing after clock frequency is changed,
+     *  dummy read the same register at least eight times.
+     *  Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+
+#if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+    R_SYSC_NS->SCKCR3 = sckcr3;
+
+    /** In order to secure processing after clock frequency is changed,
+     *  dummy read the same register at least eight times.
+     *  Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+
+    R_SYSC_NS->SCKCR4 = sckcr4;
+
+    /** In order to secure processing after clock frequency is changed,
+     *  dummy read the same register at least eight times.
+     *  Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+#endif
+
+    FSP_PARAMETER_NOT_USED(dummy);
+
+    /* Clock is now at requested frequency. */
+
+    /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
+    SystemCoreClockUpdate();
+}
+
+#if !BSP_CFG_SOFT_RESET_SUPPORTED
+
+static void bsp_prv_clock_set_hard_reset (void)
+{
+    volatile uint32_t dummy;
+    uint32_t          sckcr  = BSP_PRV_STARTUP_SCKCR & BSP_PRV_SCKCR_MASK;
+    uint32_t          sckcr2 = BSP_PRV_STARTUP_SCKCR2 & BSP_PRV_SCKCR2_MASK;
+ #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+    uint32_t sckcr3 = BSP_PRV_STARTUP_SCKCR3 & BSP_PRV_SCKCR3_MASK;
+    uint32_t sckcr4 = BSP_PRV_STARTUP_SCKCR4 & BSP_PRV_SCKCR4_MASK;
+ #endif
+
+    /* Set the system source clock */
+    R_SYSC_S->SCKCR2 = sckcr2;
+
+    /** In order to secure processing after clock frequency is changed,
+     *  dummy read the same register at least eight times.
+     *  Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+    dummy = R_SYSC_S->SCKCR2;
+
+    R_SYSC_NS->SCKCR = sckcr;
+
+    /** In order to secure processing after clock frequency is changed,
+     *  dummy read the same register at least eight times.
+     *  Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+    dummy = R_SYSC_NS->SCKCR;
+
+ #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+    R_SYSC_NS->SCKCR3 = sckcr3;
+
+    /** In order to secure processing after clock frequency is changed,
+     *  dummy read the same register at least eight times.
+     *  Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+    dummy = R_SYSC_NS->SCKCR3;
+
+    R_SYSC_NS->SCKCR4 = sckcr4;
+
+    /** In order to secure processing after clock frequency is changed,
+     *  dummy read the same register at least eight times.
+     *  Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+    dummy = R_SYSC_NS->SCKCR4;
+ #endif
+
+    FSP_PARAMETER_NOT_USED(dummy);
+
+    /* Clock is now at requested frequency. */
+
+    /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
+    SystemCoreClockUpdate();
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Initializes system clocks.  Makes no assumptions about current register settings.
+ **********************************************************************************************************************/
+void bsp_clock_init (void)
+{
+    volatile uint32_t dummy = 0;
+
+    /* Unlock CGC protection registers. */
+    R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK;
+    R_RWP_S->PRCRS  = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK;
+
+    /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */
+    SystemCoreClockUpdate();
+
+    /* Set source clock and dividers. */
+#if BSP_CFG_SOFT_RESET_SUPPORTED
+    bsp_prv_clock_set(BSP_PRV_STARTUP_SCKCR, BSP_PRV_STARTUP_SCKCR2, BSP_PRV_STARTUP_SCKCR3, BSP_PRV_STARTUP_SCKCR4);
+#else
+    bsp_prv_clock_set_hard_reset();
+#endif
+
+#if (BSP_FEATURE_CGC_PLL0_STANDBY_STATE_SUPPORTED)
+    if (BSP_CLOCKS_PLL0_NORMAL == BSP_CFG_PLL0)
+    {
+        if (BSP_CLOCKS_PLL0_STANDBY == R_SYSC_S->PLL0EN_b.PLL0EN)
+        {
+            /* Configure SSC settings. */
+            if (BSP_CFG_PLL0SSCEN == BSP_CLOCKS_PLL0SSCEN_ENABLE)
+            {
+                R_SYSC_S->PLL0_SSC_CTR = BSP_PRV_STARTUP_PLL0_SSC_CTR;
+            }
+
+            /* Release PLL from standby state. */
+            R_SYSC_S->PLL0EN = BSP_CFG_PLL0;
+
+            /* Confirm transition to normal mode. */
+            FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PLL0MON_b.PLL0MON, 1U);
+
+            /* Confirm clock source change of PLL clock domain. */
+            FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PMSEL_b.PMSEL0MON, 1U);
+        }
+    }
+#endif
+
+#if (BSP_FEATURE_CGC_PLL1_STANDBY_STATE_SUPPORTED)
+ #if (BSP_CLOCKS_PLL1_INITIAL != BSP_CFG_PLL1)
+
+    /* Release PLL from standby state. */
+    R_SYSC_S->PLL1EN = BSP_CFG_PLL1;
+ #endif
+#endif
+
+#if (BSP_FEATURE_CGC_PLL2_STANDBY_STATE_SUPPORTED)
+    if (BSP_CLOCKS_PLL2_NORMAL == BSP_CFG_PLL2)
+    {
+        if (BSP_CLOCKS_PLL2_STANDBY == R_SYSC_S->PLL2EN_b.PLL2EN)
+        {
+            /* Configure SSC settings. */
+            if (BSP_CFG_PLL0SSCEN == BSP_CLOCKS_PLL0SSCEN_ENABLE)
+            {
+                R_SYSC_S->PLL2_SSC_CTR = BSP_PRV_STARTUP_PLL2_SSC_CTR;
+            }
+
+            /* Release PLL from standby state. */
+            R_SYSC_S->PLL2EN = BSP_CFG_PLL2;
+
+            /* Confirm transition to normal mode. */
+            FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PLL2MON_b.PLL2MON, 1U);
+
+            /* Confirm clock source change of PLL clock domain. */
+            FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PMSEL_b.PMSEL2MON, 1U);
+        }
+    }
+#endif
+
+#if (BSP_FEATURE_CGC_PLL3_STANDBY_STATE_SUPPORTED)
+    if (BSP_CLOCKS_PLL3_NORMAL == BSP_CFG_PLL3)
+    {
+        if (BSP_CLOCKS_PLL3_STANDBY == R_SYSC_S->PLL3EN_b.PLL3EN)
+        {
+            /* Configure PLL3 settings. */
+            R_SYSC_S->PLL3_VCO_CTR0 = BSP_PRV_STARTUP_PLL3_VCO_CTR0;
+            R_SYSC_S->PLL3_VCO_CTR1 = BSP_PRV_STARTUP_PLL3_VCO_CTR1;
+
+            /* Release PLL from standby state. */
+            R_SYSC_S->PLL3EN = BSP_CFG_PLL3;
+
+            /* Confirm transition to normal mode. */
+            FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PLL3MON_b.PLL3MON, 1U);
+
+            /* Confirm clock source change of PLL clock domain. */
+            FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PMSEL_b.PMSEL3MON, 1U);
+        }
+    }
+#endif
+
+#if (BSP_CLOCKS_LOCO_ENABLE == BSP_CFG_LOCO_ENABLE)
+    R_SYSC_S->LOCOCR = BSP_CLOCKS_LOCO_ENABLE;
+
+    /* Only start using the LOCO clock after
+     * the LOCO oscillation stabilization time (tLOCOWT) has elapsed. */
+    for (uint16_t i = 0; i < BSP_PRV_LOCO_STABILIZATION_COUNT; i++)
+    {
+        __asm volatile ("nop");
+    }
+#endif
+
+    R_SYSC_S->HIZCTRLEN = BSP_PRV_STARTUP_HIZCTRLEN;
+
+#if (BSP_CLOCKS_CLMA0_ENABLE == BSP_CFG_CLMA0_ENABLE)
+
+    /* Set the lower and upper limit for comparing frequency domains. */
+    R_CLMA0->CMPL = BSP_CFG_CLMA0_CMPL;
+    R_CLMA0->CMPH = BSP_CFG_CLMA0_CMPH;
+
+    /* Enabling CLMA0 operation. */
+    volatile uint32_t timeout_clma0 = BSP_PRV_CTL0_ENABLE_SETTING_TIMEOUT;
+
+    do
+    {
+        /* If the setting that enables CLMA0 times out, the assertion will fail. */
+        FSP_ASSERT_NOT_RETURN_VALUE(0 != timeout_clma0);
+
+        R_CLMA0->PCMD = BSP_PRV_PCMD_KEY;
+
+        R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+        R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
+        R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+
+        if (1 != R_CLMA0->CTL0)
+        {
+            /* Check the value of PROTSR register. */
+            dummy = R_CLMA0->PROTSR;
+        }
+
+        timeout_clma0--;
+    } while (1 == R_CLMA0->PROTSR_b.PRERR);
+#endif
+
+#if (BSP_CLOCKS_CLMA1_ENABLE == BSP_CFG_CLMA1_ENABLE)
+
+    /* Set the lower and upper limit for comparing frequency domains. */
+    R_CLMA1->CMPL = BSP_CFG_CLMA1_CMPL;
+    R_CLMA1->CMPH = BSP_CFG_CLMA1_CMPH;
+
+    /* Enabling CLMA1 operation. */
+    volatile uint32_t timeout_clma1 = BSP_PRV_CTL0_ENABLE_SETTING_TIMEOUT;
+
+    do
+    {
+        /* If the setting that enables CLMA1 times out, the assertion will fail. */
+        FSP_ASSERT_NOT_RETURN_VALUE(0 != timeout_clma1);
+
+        R_CLMA1->PCMD = BSP_PRV_PCMD_KEY;
+
+        R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+        R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
+        R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+
+        if (1 != R_CLMA1->CTL0)
+        {
+            /* Check the value of PROTSR register. */
+            dummy = R_CLMA1->PROTSR;
+        }
+
+        timeout_clma1--;
+    } while (1 == R_CLMA1->PROTSR_b.PRERR);
+#endif
+
+#if (BSP_CLOCKS_CLMA2_ENABLE == BSP_CFG_CLMA2_ENABLE)
+
+    /* Set the lower and upper limit for comparing frequency domains. */
+    R_CLMA2->CMPL = BSP_CFG_CLMA2_CMPL;
+    R_CLMA2->CMPH = BSP_CFG_CLMA2_CMPH;
+
+    /* Enabling CLMA2 operation. */
+    volatile uint32_t timeout_clma2 = BSP_PRV_CTL0_ENABLE_SETTING_TIMEOUT;
+
+    do
+    {
+        /* If the setting that enables CLMA2 times out, the assertion will fail. */
+        FSP_ASSERT_NOT_RETURN_VALUE(0 != timeout_clma2);
+
+        R_CLMA2->PCMD = BSP_PRV_PCMD_KEY;
+
+        R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+        R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
+        R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+
+        if (1 != R_CLMA2->CTL0)
+        {
+            /* Check the value of PROTSR register. */
+            dummy = R_CLMA2->PROTSR;
+        }
+
+        timeout_clma2--;
+    } while (1 == R_CLMA2->PROTSR_b.PRERR);
+#endif
+
+#if (BSP_CLOCKS_CLMA3_ENABLE == BSP_CFG_CLMA3_ENABLE)
+
+    /* Set the lower and upper limit for comparing frequency domains. */
+    R_CLMA3->CMPL = BSP_CFG_CLMA3_CMPL;
+    R_CLMA3->CMPH = BSP_CFG_CLMA3_CMPH;
+
+    /* Enabling CLMA3 operation. */
+    volatile uint32_t timeout_clma3 = BSP_PRV_CTL0_ENABLE_SETTING_TIMEOUT;
+
+    do
+    {
+        /* If the setting that enables CLMA3 times out, the assertion will fail. */
+        FSP_ASSERT_NOT_RETURN_VALUE(0 != timeout_clma3);
+
+        R_CLMA3->PCMD = BSP_PRV_PCMD_KEY;
+
+        R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+        R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
+        R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+
+        if (1 != R_CLMA3->CTL0)
+        {
+            /* Check the value of PROTSR register. */
+            dummy = R_CLMA3->PROTSR;
+        }
+
+        timeout_clma3--;
+    } while (1 == R_CLMA3->PROTSR_b.PRERR);
+#endif
+
+#if (BSP_CLOCKS_CLMA4_ENABLE == BSP_CFG_CLMA4_ENABLE)
+
+    /* Set the lower and upper limit for comparing frequency domains. */
+    R_CLMA4->CMPL = BSP_CFG_CLMA4_CMPL;
+    R_CLMA4->CMPH = BSP_CFG_CLMA4_CMPH;
+
+    /* Enabling CLMA4 operation. */
+    volatile uint32_t timeout_clma4 = BSP_PRV_CTL0_ENABLE_SETTING_TIMEOUT;
+
+    do
+    {
+        /* If the setting that enables CLMA4 times out, the assertion will fail. */
+        FSP_ASSERT_NOT_RETURN_VALUE(0 != timeout_clma4);
+
+        R_CLMA4->PCMD = BSP_PRV_PCMD_KEY;
+
+        R_CLMA4->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+        R_CLMA4->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
+        R_CLMA4->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+
+        if (1 != R_CLMA4->CTL0)
+        {
+            /* Check the value of PROTSR register. */
+            dummy = R_CLMA4->PROTSR;
+        }
+
+        timeout_clma4--;
+    } while (1 == R_CLMA4->PROTSR_b.PRERR);
+#endif
+
+#if (BSP_CLOCKS_CLMA5_ENABLE == BSP_CFG_CLMA5_ENABLE)
+
+    /* Set the lower and upper limit for comparing frequency domains. */
+    R_CLMA5->CMPL = BSP_CFG_CLMA5_CMPL;
+    R_CLMA5->CMPH = BSP_CFG_CLMA5_CMPH;
+
+    /* Enabling CLMA5 operation. */
+    volatile uint32_t timeout_clma5 = BSP_PRV_CTL0_ENABLE_SETTING_TIMEOUT;
+
+    do
+    {
+        /* If the setting that enables CLMA5 times out, the assertion will fail. */
+        FSP_ASSERT_NOT_RETURN_VALUE(0 != timeout_clma5);
+
+        R_CLMA5->PCMD = BSP_PRV_PCMD_KEY;
+
+        R_CLMA5->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+        R_CLMA5->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
+        R_CLMA5->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+
+        if (1 != R_CLMA5->CTL0)
+        {
+            /* Check the value of PROTSR register. */
+            dummy = R_CLMA5->PROTSR;
+        }
+
+        timeout_clma5--;
+    } while (1 == R_CLMA5->PROTSR_b.PRERR);
+#endif
+
+#if (BSP_CLOCKS_CLMA6_ENABLE == BSP_CFG_CLMA6_ENABLE)
+
+    /* Set the lower and upper limit for comparing frequency domains. */
+    R_CLMA6->CMPL = BSP_CFG_CLMA6_CMPL;
+    R_CLMA6->CMPH = BSP_CFG_CLMA6_CMPH;
+
+    /* Enabling CLMA6 operation. */
+    volatile uint32_t timeout_clma6 = BSP_PRV_CTL0_ENABLE_SETTING_TIMEOUT;
+
+    do
+    {
+        /* If the setting that enables CLMA6 times out, the assertion will fail. */
+        FSP_ASSERT_NOT_RETURN_VALUE(0 != timeout_clma6);
+
+        R_CLMA6->PCMD = BSP_PRV_PCMD_KEY;
+
+        R_CLMA6->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+        R_CLMA6->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
+        R_CLMA6->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
+
+        if (1 != R_CLMA6->CTL0)
+        {
+            /* Check the value of PROTSR register. */
+            dummy = R_CLMA6->PROTSR;
+        }
+
+        timeout_clma6--;
+    } while (1 == R_CLMA6->PROTSR_b.PRERR);
+#endif
+
+    /* Lock CGC and LPM protection registers. */
+    R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_LOCK;
+    R_RWP_S->PRCRS  = (uint16_t) BSP_PRV_PRCR_LOCK;
+
+    FSP_PARAMETER_NOT_USED(dummy);
+}
+
+/** @} (end addtogroup BSP_MCU_PRV) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_clocks.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_clocks.h
new file mode 100644
index 00000000..c7f92282
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_clocks.h
@@ -0,0 +1,503 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_CLOCKS_H
+#define BSP_CLOCKS_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_clock_cfg.h"
+#include "bsp_api.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have
+ * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */
+
+/* xSPI unit0 clock options. */
+#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_150_0_MHZ                   (0x01) // xSPI0 base clock 800MHz and xSPI0 clock 150.0MHz.
+#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_133_3_MHZ                   (0x02) // xSPI0 base clock 800MHz and xSPI0 clock 133.3MHz.
+#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_100_0_MHZ                   (0x03) // xSPI0 base clock 800MHz and xSPI0 clock 100.0 MHz.
+#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_50_0_MHZ                    (0x04) // xSPI0 base clock 800MHz and xSPI0 clock 50.0 MHz.
+#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_25_0_MHZ                    (0x05) // xSPI0 base clock 800MHz and xSPI0 clock 25.0 MHz.
+#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ                    (0x06) // xSPI0 base clock 800MHz and xSPI0 clock 12.5 MHz.
+#define BSP_CLOCKS_XSPI0_CLOCK_DIV1_75_0_MHZ                    (0x43) // xSPI0 base clock 600MHz and xSPI0 clock 75.0 MHz.
+#define BSP_CLOCKS_XSPI0_CLOCK_DIV1_37_5_MHZ                    (0x44) // xSPI0 base clock 600MHz and xSPI0 clock 37.5 MHz.
+
+/* xSPI unit1 clock options. */
+#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_150_0_MHZ                   (0x01) // xSPI1 base clock 800MHz and xSPI1 clock 150.0MHz.
+#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_133_3_MHZ                   (0x02) // xSPI1 base clock 800MHz and xSPI1 clock 133.3MHz.
+#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_100_0_MHZ                   (0x03) // xSPI1 base clock 800MHz and xSPI1 clock 100.0 MHz.
+#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_50_0_MHZ                    (0x04) // xSPI1 base clock 800MHz and xSPI1 clock 50.0 MHz.
+#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_25_0_MHZ                    (0x05) // xSPI1 base clock 800MHz and xSPI1 clock 25.0 MHz.
+#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ                    (0x06) // xSPI1 base clock 800MHz and xSPI1 clock 12.5 MHz.
+#define BSP_CLOCKS_XSPI1_CLOCK_DIV1_75_0_MHZ                    (0x43) // xSPI1 base clock 600MHz and xSPI1 clock 75.0 MHz.
+#define BSP_CLOCKS_XSPI1_CLOCK_DIV1_37_5_MHZ                    (0x44) // xSPI1 base clock 600MHz and xSPI1 clock 37.5 MHz.
+
+/* CKIO clock options. */
+#if (1U == BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE)
+ #define BSP_CLOCKS_CKIO_ICLK_DIV2                              (0)    // CKIO clock 100.0 MHz  (when SCKCR2.DIVSELSUB = 0),
+                                                                       // or 75.0 MHz  (when SCKCR2.DIVSELSUB = 1).
+ #define BSP_CLOCKS_CKIO_ICLK_DIV3                              (1)    // CKIO clock 66.7 MHz  (when SCKCR2.DIVSELSUB = 0),
+                                                                       // or 50.0 MHz  (when SCKCR2.DIVSELSUB = 1).
+ #define BSP_CLOCKS_CKIO_ICLK_DIV4                              (2)    // CKIO clock 50.0 MHz  (when SCKCR2.DIVSELSUB = 0),
+                                                                       // or 37.5 MHz  (when SCKCR2.DIVSELSUB = 1).
+ #define BSP_CLOCKS_CKIO_ICLK_DIV5                              (3)    // CKIO clock 40.0 MHz  (when SCKCR2.DIVSELSUB = 0),
+                                                                       // or 30.0 MHz  (when SCKCR2.DIVSELSUB = 1).
+ #define BSP_CLOCKS_CKIO_ICLK_DIV6                              (4)    // CKIO clock 33.3 MHz  (when SCKCR2.DIVSELSUB = 0),
+                                                                       // or 25.0 MHz  (when SCKCR2.DIVSELSUB = 1).
+ #define BSP_CLOCKS_CKIO_ICLK_DIV7                              (5)    // CKIO clock 28.6 MHz  (when SCKCR2.DIVSELSUB = 0),
+                                                                       // or 21.4 MHz  (when SCKCR2.DIVSELSUB = 1).
+ #define BSP_CLOCKS_CKIO_ICLK_DIV8                              (6)    // CKIO clock 25.0 MHz  (when SCKCR2.DIVSELSUB = 0),
+                                                                       // or 18.75 MHz (when SCKCR2.DIVSELSUB = 1).
+#elif (2U == BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE)
+ #define BSP_CLOCKS_CKIO_125_0_MHZ                              (0)    // CKIO clock 125.0 MHz.
+ #define BSP_CLOCKS_CKIO_83_3_MHZ                               (1)    // CKIO clock 83.3 MHz.
+ #define BSP_CLOCKS_CKIO_62_5_MHZ                               (2)    // CKIO clock 62.5 MHz.
+ #define BSP_CLOCKS_CKIO_50_0_MHZ                               (3)    // CKIO clock 50.0 MHz.
+ #define BSP_CLOCKS_CKIO_41_7_MHZ                               (4)    // CKIO clock 41.7 MHz.
+ #define BSP_CLOCKS_CKIO_35_7_MHZ                               (5)    // CKIO clock 35.7 MHz.
+ #define BSP_CLOCKS_CKIO_31_25_MHZ                              (6)    // CKIO clock 31.25 MHz.
+#endif
+
+/* CANFD clock options. */
+#define BSP_CLOCKS_CANFD_CLOCK_80_MHZ                           (0)    // CANFD clock 80 MHz.
+#define BSP_CLOCKS_CANFD_CLOCK_40_MHZ                           (1)    // CANFD clock 40 MHz.
+#define BSP_CLOCKS_CANFD_CLOCK_PCLKM                            (1)    // CANFD clock source PCLKM.
+
+/* ENCOUT clock options. */
+#define BSP_CLOCKS_ENCO_CLOCK_80_MHZ                            (1)    // ENCOUT clock 80 MHz.
+#define BSP_CLOCKS_ENCO_CLOCK_20_MHZ                            (0)    // ENCOUT clock 20 MHz.
+
+/* Ethernet PHY reference clock (ETHn_REFCLK : n = 0 to 2) options. */
+#define BSP_CLOCKS_PHYSEL_PLL1_DIV                              (0)    // PLL1 devider clock.
+#define BSP_CLOCKS_PHYSEL_MAINOSC_DIV                           (1)    // Main clock oscillator.
+
+/* Alternative clock options when main clock abnormal oscillation is detected. */
+#define BSP_CLOCKS_CLMASEL_LOCO                                 (0)    // LOCO clock.
+#define BSP_CLOCKS_CLMASEL_PLL                                  (1)    // PLL clock.
+
+/* LCDC clock options. */
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_2                             (0x00) // Divide LCDC source clock by 2.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_4                             (0x01) // Divide LCDC source clock by 4.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_6                             (0x02) // Divide LCDC source clock by 6.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_8                             (0x03) // Divide LCDC source clock by 8.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_10                            (0x04) // Divide LCDC source clock by 10.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_12                            (0x05) // Divide LCDC source clock by 12.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_14                            (0x06) // Divide LCDC source clock by 14.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_16                            (0x07) // Divide LCDC source clock by 16.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_18                            (0x08) // Divide LCDC source clock by 18.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_20                            (0x09) // Divide LCDC source clock by 20.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_22                            (0x0A) // Divide LCDC source clock by 22.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_24                            (0x0B) // Divide LCDC source clock by 24.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_26                            (0x0C) // Divide LCDC source clock by 26.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_28                            (0x0D) // Divide LCDC source clock by 28.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_30                            (0x0E) // Divide LCDC source clock by 30.
+#define BSP_CLOCKS_LCDCDIVSEL_DIV_32                            (0x0F) // Divide LCDC source clock by 32.
+
+/* SPI clock options. */
+#if (1U == BSP_FEATURE_CGC_PCLKSPI_CLOCK_FREQ_TYPE)
+ #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SPI0 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SPI0 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SPI1 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SPI1 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SPI2 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SPI2 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SPI3 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SPI3 asynchronous serial clock 96.0 MHz.
+
+#elif (2U == BSP_FEATURE_CGC_PCLKSPI_CLOCK_FREQ_TYPE)
+ #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SPI0 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SPI0 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SPI0 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SPI0 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SPI1 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SPI1 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SPI1 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SPI1 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SPI2 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SPI2 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SPI2 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SPI2 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SPI3 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SPI3 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SPI3 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SPI3 asynchronous serial clock 100.0 MHz.
+#endif
+
+/* SCI clock options. */
+#if (1U == BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE)
+ #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SCI0 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SCI0 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SCI1 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SCI1 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SCI2 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SCI2 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SCI3 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SCI3 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SCI4 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SCI4 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0)    // SCI5 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (1)    // SCI5 asynchronous serial clock 96.0 MHz.
+#elif (2U == BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE)
+ #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SCI0 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SCI0 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SCI0 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SCI0 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SCI1 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SCI1 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SCI1 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SCI1 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SCI2 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SCI2 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SCI2 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SCI2 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SCI3 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SCI3 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SCI3 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SCI3 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SCI4 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SCI4 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SCI4 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SCI4 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ       (0x00) // SCI5 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ       (0x01) // SCI5 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ       (0x02) // SCI5 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ      (0x03) // SCI5 asynchronous serial clock 100.0 MHz.
+#endif
+
+/* SCIE clock options. */
+#if (1U == BSP_FEATURE_SCIE_SUPPORTED)
+ #define BSP_CLOCKS_SCIE0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE0 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE0_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE0 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE0 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE0_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE0 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE1 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE1_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE1 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE1 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE1_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE1 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE2 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE2_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE2 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE2 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE2_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE2 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE3 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE3_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE3 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE3 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE3_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE3 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE4 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE4_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE4 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE4 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE4_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE4 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE5 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE5_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE5 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE5 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE5_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE5 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE6_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE6 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE6_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE6 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE6_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE6 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE6_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE6 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE7_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE7 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE7_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE7 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE7_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE7 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE7_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE7 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE8_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE8 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE8_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE8 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE8_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE8 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE8_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE8 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE9_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ      (0x00) // SCIE9 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE9_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ      (0x01) // SCIE9 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE9_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ      (0x02) // SCIE9 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE9_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ     (0x03) // SCIE9 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE10_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ     (0x00) // SCIE10 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE10_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ     (0x01) // SCIE10 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE10_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ     (0x02) // SCIE10 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE10_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ    (0x03) // SCIE10 asynchronous serial clock 100.0 MHz.
+ #define BSP_CLOCKS_SCIE11_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ     (0x00) // SCIE11 asynchronous serial clock 75.0 MHz.
+ #define BSP_CLOCKS_SCIE11_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ     (0x01) // SCIE11 asynchronous serial clock 80.0 MHz.
+ #define BSP_CLOCKS_SCIE11_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ     (0x02) // SCIE11 asynchronous serial clock 96.0 MHz.
+ #define BSP_CLOCKS_SCIE11_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ    (0x03) // SCIE11 asynchronous serial clock 100.0 MHz.
+#endif
+
+#if (1U == BSP_FEATURE_CGC_SCKCR_TYPE)
+
+/* CR52 CPU0 clock options. */
+ #define BSP_CLOCKS_FSELCPU0_ICLK_MUL2    (1) // CPU0 clock 400 MHz (when SCKCR2.DIVSELSUB = 0),
+                                              // or 300 MHz (when SCKCR2.DIVSELSUB = 1).
+ #define BSP_CLOCKS_FSELCPU0_ICLK_MUL1    (0) // CPU0 clock 200 MHz (when SCKCR2.DIVSELSUB = 0),
+                                              // or 150 MHz (when SCKCR2.DIVSELSUB = 1).
+
+/* Peripheral module base clock options. */
+ #define BSP_CLOCKS_DIVSELSUB_0           (0) // ICLK:200MHz, PCLKH:200MHz, PCLKM:100MHz,
+                                              // PCLKL:50MHz, PCLKADC:25MHz, PCLKGPTL:400MHz.
+ #define BSP_CLOCKS_DIVSELSUB_1           (1) // ICLK:150MHz, PCLKH:150MHz, PCLKM:75 MHz,
+                                              // PCLKL:37.5MHz, PCLKADC:18.75MHz, PCLKGPTL:300MHz.
+
+#elif (2U == BSP_FEATURE_CGC_SCKCR_TYPE)
+
+/* CR52 CPU0 clock options. */
+ #define BSP_CLOCKS_CR52CPU0_500_MHZ           (0)    // CPU0 clock 500 MHz.
+ #define BSP_CLOCKS_CR52CPU0_1000_MHZ          (1)    // CPU0 clock 1000 MHz.
+
+/* CR52 CPU1 clock options. */
+ #define BSP_CLOCKS_CR52CPU1_500_MHZ           (0)    // CPU1 clock 500 MHz.
+ #define BSP_CLOCKS_CR52CPU1_1000_MHZ          (1)    // CPU1 clock 1000 MHz.
+
+/* CA55 core0 clock options. */
+ #define BSP_CLOCKS_CA55CORE0_600_MHZ          (0)    // CA55 core0 clock 600 MHz.
+ #define BSP_CLOCKS_CA55CORE0_1200_MHZ         (1)    // CA55 core0 clock 1200 MHz.
+
+/* CA55 core1 clock options. */
+ #define BSP_CLOCKS_CA55CORE1_600_MHZ          (0)    // CA55 core1 clock 600 MHz.
+ #define BSP_CLOCKS_CA55CORE1_1200_MHZ         (1)    // CA55 core1 clock 1200 MHz.
+
+/* CA55 core2 clock options. */
+ #define BSP_CLOCKS_CA55CORE2_600_MHZ          (0)    // CA55 core2 clock 600 MHz.
+ #define BSP_CLOCKS_CA55CORE2_1200_MHZ         (1)    // CA55 core2 clock 1200 MHz.
+
+/* CA55 core3 clock options. */
+ #define BSP_CLOCKS_CA55CORE3_600_MHZ          (0)    // CA55 core3 clock 600 MHz.
+ #define BSP_CLOCKS_CA55CORE3_1200_MHZ         (1)    // CA55 core3 clock 1200 MHz.
+
+/* CA55 SCU CLOCK options. */
+ #define BSP_CLOCKS_CA55SCLK_500_MHZ           (0)    // CA55 SCU clock 500 MHz.
+ #define BSP_CLOCKS_CA55SCLK_1000_MHZ          (1)    // CA55 SCU clock 1000 MHz.
+#endif
+
+/* LOCO enable options. */
+#define BSP_CLOCKS_LOCO_DISABLE                (0)    // LOCO Stop
+#define BSP_CLOCKS_LOCO_ENABLE                 (1)    // LOCO Run
+
+/* PLL0 enable options. */
+#define BSP_CLOCKS_PLL0_STANDBY                (0)    // PLL0 is standby state.
+#define BSP_CLOCKS_PLL0_NORMAL                 (1)    // PLL0 is normal state.
+
+/* PLL1 enable options. */
+#define BSP_CLOCKS_PLL1_INITIAL                (0xFF) // Initial (This value should not be reflected in the register)
+#define BSP_CLOCKS_PLL1_STANDBY                (0)    // PLL1 is standby state.
+#define BSP_CLOCKS_PLL1_NORMAL                 (1)    // PLL1 is normal state.
+
+/* PLL2 enable options. */
+#define BSP_CLOCKS_PLL2_STANDBY                (0)    // PLL2 is standby state.
+#define BSP_CLOCKS_PLL2_NORMAL                 (1)    // PLL2 is normal state.
+
+/* PLL3 enable options. */
+#define BSP_CLOCKS_PLL3_STANDBY                (0)    // PLL3 is standby state.
+#define BSP_CLOCKS_PLL3_NORMAL                 (1)    // PLL3 is normal state.
+
+/* PLL0 SSC options. */
+#define BSP_CLOCKS_PLL0SSCEN_DISABLE           (0)    // PLL0 SSC function is enabled
+#define BSP_CLOCKS_PLL0SSCEN_ENABLE            (1)    // PLL0 SSC function is disabled
+
+/* PLL2 SSC options. */
+#define BSP_CLOCKS_PLL2SSCEN_DISABLE           (0)    // PLL2 SSC function is enabled
+#define BSP_CLOCKS_PLL2SSCEN_ENABLE            (1)    // PLL2 SSC function is disabled
+
+/* CLMA error mask options. */
+#define BSP_CLOCKS_CLMA0_ERROR_MASK            (0)    // CLMA0 error is not transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA0_ERROR_NOT_MASK        (1)    // CLMA0 error is transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA1_ERROR_MASK            (0)    // CLMA1 error is not transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA1_ERROR_NOT_MASK        (1)    // CLMA1 error is transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA2_ERROR_MASK            (0)    // CLMA0 error is not transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA2_ERROR_NOT_MASK        (1)    // CLMA0 error is transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA3_ERROR_MASK            (0)    // CLMA3 error is not transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA3_ERROR_NOT_MASK        (1)    // CLMA3 error is transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA4_ERROR_MASK            (0)    // CLMA4 error is not transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA4_ERROR_NOT_MASK        (1)    // CLMA4 error is transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA5_ERROR_MASK            (0)    // CLMA5 error is not transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA5_ERROR_NOT_MASK        (1)    // CLMA5 error is transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA6_ERROR_MASK            (0)    // CLMA6 error is not transferred to POE3 and POEG.
+#define BSP_CLOCKS_CLMA6_ERROR_NOT_MASK        (1)    // CLMA6 error is transferred to POE3 and POEG.
+
+/* CLMA enable options. */
+#define BSP_CLOCKS_CLMA0_DISABLE               (0)    // Disable CLMA0 operation.
+#define BSP_CLOCKS_CLMA0_ENABLE                (1)    // Enable CLMA0 operation.
+#define BSP_CLOCKS_CLMA1_DISABLE               (0)    // Disable CLMA1 operation.
+#define BSP_CLOCKS_CLMA1_ENABLE                (1)    // Enable CLMA1 operation.
+#define BSP_CLOCKS_CLMA2_DISABLE               (0)    // Disable CLMA2 operation.
+#define BSP_CLOCKS_CLMA2_ENABLE                (1)    // Enable CLMA2 operation.
+#define BSP_CLOCKS_CLMA3_DISABLE               (0)    // Disable CLMA3 operation.
+#define BSP_CLOCKS_CLMA3_ENABLE                (1)    // Enable CLMA3 operation.
+#define BSP_CLOCKS_CLMA4_DISABLE               (0)    // Disable CLMA4 operation.
+#define BSP_CLOCKS_CLMA4_ENABLE                (1)    // Enable CLMA4 operation.
+#define BSP_CLOCKS_CLMA5_DISABLE               (0)    // Disable CLMA5 operation.
+#define BSP_CLOCKS_CLMA5_ENABLE                (1)    // Enable CLMA5 operation.
+#define BSP_CLOCKS_CLMA6_DISABLE               (0)    // Disable CLMA6 operation.
+#define BSP_CLOCKS_CLMA6_ENABLE                (1)    // Enable CLMA6 operation.
+
+#if (1U == BSP_FEATURE_CGC_SCKCR_TYPE)
+
+/* Create a mask of valid bits in SCKCR. */
+ #define BSP_PRV_SCKCR_FSELXSPI0_MASK          (7U << 0)
+ #define BSP_PRV_SCKCR_DIVSELXSPI0_MASK        (1U << 6)
+ #define BSP_PRV_SCKCR_FSELXSPI1_MASK          (7U << 8)
+ #define BSP_PRV_SCKCR_DIVSELXSPI1_MASK        (1U << 14)
+ #define BSP_PRV_SCKCR_CKIO_MASK               (7U << 16)
+ #define BSP_PRV_SCKCR_FSELCANFD_MASK          (1U << 20)
+ #define BSP_PRV_SCKCR_PHYSEL_MASK             (1U << 21)
+ #define BSP_PRV_SCKCR_CLMASEL_MASK            (1U << 22)
+ #define BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK       (1U << 24)
+ #define BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK       (1U << 25)
+ #define BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK       (1U << 26)
+ #define BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK       (1U << 27)
+ #define BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK       (1U << 28)
+ #define BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK       (1U << 29)
+ #define BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK       (1U << 30)
+ #define BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK       (1U << 31)
+ #define BSP_PRV_SCKCR_MASK                    (((((((((((((((BSP_PRV_SCKCR_FSELXSPI0_MASK |    \
+                                                              BSP_PRV_SCKCR_DIVSELXSPI0_MASK) | \
+                                                             BSP_PRV_SCKCR_FSELXSPI1_MASK) |    \
+                                                            BSP_PRV_SCKCR_DIVSELXSPI1_MASK) |   \
+                                                           BSP_PRV_SCKCR_CKIO_MASK) |           \
+                                                          BSP_PRV_SCKCR_FSELCANFD_MASK) |       \
+                                                         BSP_PRV_SCKCR_PHYSEL_MASK) |           \
+                                                        BSP_PRV_SCKCR_CLMASEL_MASK) |           \
+                                                       BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK) |       \
+                                                      BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK) |        \
+                                                     BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK) |         \
+                                                    BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK) |          \
+                                                   BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK) |           \
+                                                  BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK) |            \
+                                                 BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK) |             \
+                                                BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK)
+
+ #define BSP_PRV_SCKCR_DIVSELXSPI_MASK         (BSP_PRV_SCKCR_DIVSELXSPI0_MASK | \
+                                                BSP_PRV_SCKCR_DIVSELXSPI1_MASK)
+
+/* Create a mask of valid bits in SCKCR2. */
+ #define BSP_PRV_SCKCR2_FSELCPU0_MASK          (3U << 0)
+ #define BSP_PRV_SCKCR2_RESERVED_BIT4_MASK     (1U << 4)
+ #define BSP_PRV_SCKCR2_DIVSELSUB_MASK         (1U << 5)
+ #define BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK      (1U << 24)
+ #define BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK      (1U << 25)
+ #define BSP_PRV_SCKCR2_MASK                   ((((BSP_PRV_SCKCR2_FSELCPU0_MASK |       \
+                                                   BSP_PRV_SCKCR2_RESERVED_BIT4_MASK) | \
+                                                  BSP_PRV_SCKCR2_DIVSELSUB_MASK) |      \
+                                                 BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK) |    \
+                                                BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK)
+
+#elif (2U == BSP_FEATURE_CGC_SCKCR_TYPE)
+
+/* Create a mask of valid bits in SCKCR. */
+ #define BSP_PRV_SCKCR_FSELXSPI0_MASK          (7U << 0)
+ #define BSP_PRV_SCKCR_DIVSELXSPI0_MASK        (1U << 6)
+ #define BSP_PRV_SCKCR_FSELXSPI1_MASK          (7U << 8)
+ #define BSP_PRV_SCKCR_DIVSELXSPI1_MASK        (1U << 14)
+ #define BSP_PRV_SCKCR_CKIO_MASK               (7U << 16)
+ #define BSP_PRV_SCKCR_FSELCANFD_MASK          (1U << 20)
+ #define BSP_PRV_SCKCR_PHYSEL_MASK             (1U << 21)
+ #define BSP_PRV_SCKCR_CLMASEL_MASK            (1U << 22)
+
+ #define BSP_PRV_SCKCR_MASK                    (((((((BSP_PRV_SCKCR_FSELXSPI0_MASK |    \
+                                                      BSP_PRV_SCKCR_DIVSELXSPI0_MASK) | \
+                                                     BSP_PRV_SCKCR_FSELXSPI1_MASK) |    \
+                                                    BSP_PRV_SCKCR_DIVSELXSPI1_MASK) |   \
+                                                   BSP_PRV_SCKCR_CKIO_MASK) |           \
+                                                  BSP_PRV_SCKCR_FSELCANFD_MASK) |       \
+                                                 BSP_PRV_SCKCR_PHYSEL_MASK) |           \
+                                                BSP_PRV_SCKCR_CLMASEL_MASK)
+
+ #define BSP_PRV_SCKCR_DIVSELXSPI_MASK         (BSP_PRV_SCKCR_DIVSELXSPI0_MASK | \
+                                                BSP_PRV_SCKCR_DIVSELXSPI1_MASK)
+
+/* Create a mask of valid bits in SCKCR2. */
+ #define BSP_PRV_SCKCR2_CR52CPU0_MASK          (3U << 0)
+ #define BSP_PRV_SCKCR2_CR52CPU1_MASK          (3U << 2)
+ #define BSP_PRV_SCKCR2_CA55CORE0_MASK         (1U << 8)
+ #define BSP_PRV_SCKCR2_CA55CORE1_MASK         (1U << 9)
+ #define BSP_PRV_SCKCR2_CA55CORE2_MASK         (1U << 10)
+ #define BSP_PRV_SCKCR2_CA55CORE3_MASK         (1U << 11)
+ #define BSP_PRV_SCKCR2_CA55SCLK_MASK          (1U << 12)
+ #define BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK      (3U << 16)
+ #define BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK      (3U << 18)
+ #define BSP_PRV_SCKCR2_MASK                   ((((((((BSP_PRV_SCKCR2_CR52CPU0_MASK |  \
+                                                       BSP_PRV_SCKCR2_CR52CPU1_MASK) | \
+                                                      BSP_PRV_SCKCR2_CA55CORE0_MASK) | \
+                                                     BSP_PRV_SCKCR2_CA55CORE1_MASK) |  \
+                                                    BSP_PRV_SCKCR2_CA55CORE2_MASK) |   \
+                                                   BSP_PRV_SCKCR2_CA55CORE3_MASK) |    \
+                                                  BSP_PRV_SCKCR2_CA55SCLK_MASK) |      \
+                                                 BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK) |   \
+                                                BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK)
+
+/* Create a mask of valid bits in SCKCR3. */
+ #define BSP_PRV_SCKCR3_SPI0ASYNCSEL_MASK      (3U << 0)
+ #define BSP_PRV_SCKCR3_SPI1ASYNCSEL_MASK      (3U << 2)
+ #define BSP_PRV_SCKCR3_SPI2ASYNCSEL_MASK      (3U << 4)
+ #define BSP_PRV_SCKCR3_SCI0ASYNCSEL_MASK      (3U << 6)
+ #define BSP_PRV_SCKCR3_SCI1ASYNCSEL_MASK      (3U << 8)
+ #define BSP_PRV_SCKCR3_SCI2ASYNCSEL_MASK      (3U << 10)
+ #define BSP_PRV_SCKCR3_SCI3ASYNCSEL_MASK      (3U << 12)
+ #define BSP_PRV_SCKCR3_SCI4ASYNCSEL_MASK      (3U << 14)
+ #define BSP_PRV_SCKCR3_LCDCDIVSEL_MASK        (15U << 20)
+ #define BSP_PRV_SCKCR3_MASK                   (((((((((BSP_PRV_SCKCR3_SPI0ASYNCSEL_MASK) | \
+                                                       BSP_PRV_SCKCR3_SPI1ASYNCSEL_MASK) |  \
+                                                      BSP_PRV_SCKCR3_SPI2ASYNCSEL_MASK) |   \
+                                                     BSP_PRV_SCKCR3_SCI0ASYNCSEL_MASK) |    \
+                                                    BSP_PRV_SCKCR3_SCI1ASYNCSEL_MASK) |     \
+                                                   BSP_PRV_SCKCR3_SCI2ASYNCSEL_MASK) |      \
+                                                  BSP_PRV_SCKCR3_SCI3ASYNCSEL_MASK) |       \
+                                                 BSP_PRV_SCKCR3_SCI4ASYNCSEL_MASK) |        \
+                                                BSP_PRV_SCKCR3_LCDCDIVSEL_MASK)
+
+/* Create a mask of valid bits in SCKCR4. */
+ #define BSP_PRV_SCKCR4_SCIE0ASYNCSEL_MASK     (3U << 0)
+ #define BSP_PRV_SCKCR4_SCIE1ASYNCSEL_MASK     (3U << 2)
+ #define BSP_PRV_SCKCR4_SCIE2ASYNCSEL_MASK     (3U << 4)
+ #define BSP_PRV_SCKCR4_SCIE3ASYNCSEL_MASK     (3U << 6)
+ #define BSP_PRV_SCKCR4_SCIE4ASYNCSEL_MASK     (3U << 8)
+ #define BSP_PRV_SCKCR4_SCIE5ASYNCSEL_MASK     (3U << 10)
+ #define BSP_PRV_SCKCR4_SCIE6ASYNCSEL_MASK     (3U << 12)
+ #define BSP_PRV_SCKCR4_SCIE7ASYNCSEL_MASK     (3U << 14)
+ #define BSP_PRV_SCKCR4_SCIE8ASYNCSEL_MASK     (3U << 16)
+ #define BSP_PRV_SCKCR4_SCIE9ASYNCSEL_MASK     (3U << 18)
+ #define BSP_PRV_SCKCR4_SCIE10ASYNCSEL_MASK    (3U << 20)
+ #define BSP_PRV_SCKCR4_SCIE11ASYNCSEL_MASK    (3U << 22)
+ #define BSP_PRV_SCKCR4_ENCOUTCLK_MASK         (1U << 24)
+ #define BSP_PRV_SCKCR4_MASK                   (((((((((((((BSP_PRV_SCKCR4_SCIE0ASYNCSEL_MASK) | \
+                                                           BSP_PRV_SCKCR4_SCIE1ASYNCSEL_MASK) |  \
+                                                          BSP_PRV_SCKCR4_SCIE2ASYNCSEL_MASK) |   \
+                                                         BSP_PRV_SCKCR4_SCIE3ASYNCSEL_MASK) |    \
+                                                        BSP_PRV_SCKCR4_SCIE4ASYNCSEL_MASK) |     \
+                                                       BSP_PRV_SCKCR4_SCIE5ASYNCSEL_MASK) |      \
+                                                      BSP_PRV_SCKCR4_SCIE6ASYNCSEL_MASK) |       \
+                                                     BSP_PRV_SCKCR4_SCIE7ASYNCSEL_MASK) |        \
+                                                    BSP_PRV_SCKCR4_SCIE8ASYNCSEL_MASK) |         \
+                                                   BSP_PRV_SCKCR4_SCIE9ASYNCSEL_MASK) |          \
+                                                  BSP_PRV_SCKCR4_SCIE10ASYNCSEL_MASK) |          \
+                                                 BSP_PRV_SCKCR4_SCIE11ASYNCSEL_MASK) |           \
+                                                BSP_PRV_SCKCR4_ENCOUTCLK_MASK)
+
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+void bsp_clock_init(void);             // Used internally by BSP
+
+/* Used internally by CGC */
+
+void bsp_prv_clock_set(uint32_t sckcr, uint32_t sckcr2, uint32_t sckcr3, uint32_t sckcr4);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_common.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_common.c
new file mode 100644
index 00000000..17a4a347
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_common.c
@@ -0,0 +1,273 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+#if (2 == BSP_CFG_RTOS)                // FreeRTOS
+ #include "FreeRTOS.h"
+#endif
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#if defined(__ICCARM__)
+ #define WEAK_ERROR_ATTRIBUTE
+ #define WEAK_INIT_ATTRIBUTE
+ #pragma weak fsp_error_log                            = fsp_error_log_internal
+ #pragma weak bsp_init                                 = bsp_init_internal
+#elif defined(__GNUC__)
+
+ #define WEAK_ERROR_ATTRIBUTE    __attribute__((weak, alias("fsp_error_log_internal")))
+
+ #define WEAK_INIT_ATTRIBUTE     __attribute__((weak, alias("bsp_init_internal")))
+#endif
+
+#define FSP_SECTION_VERSION      ".version"
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* System clock frequency information for CKIO */
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+const uint32_t g_bsp_system_clock_select_ckio[][2] =
+{
+    {BSP_PRV_CKIO_FREQ_100_MHZ,       BSP_PRV_CKIO_FREQ_75_MHZ       }, // CKIO = 000b
+    {BSP_PRV_CKIO_FREQ_66_7_MHZ,      BSP_PRV_CKIO_FREQ_50_MHZ       }, // CKIO = 001b
+    {BSP_PRV_CKIO_FREQ_50_MHZ,        BSP_PRV_CKIO_FREQ_37_5_MHZ     }, // CKIO = 010b
+    {BSP_PRV_CKIO_FREQ_40_MHZ,        BSP_PRV_CKIO_FREQ_30_MHZ       }, // CKIO = 011b
+    {BSP_PRV_CKIO_FREQ_33_3_MHZ,      BSP_PRV_CKIO_FREQ_25_MHZ       }, // CKIO = 100b
+    {BSP_PRV_CKIO_FREQ_28_6_MHZ,      BSP_PRV_CKIO_FREQ_21_4_MHZ     }, // CKIO = 101b
+    {BSP_PRV_CKIO_FREQ_25_MHZ,        BSP_PRV_CKIO_FREQ_18_75_MHZ    }, // CKIO = 110b
+    {BSP_PRV_CKIO_FREQ_NOT_SUPPORTED, BSP_PRV_CKIO_FREQ_NOT_SUPPORTED}, // CKIO = 111b
+};
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+const uint32_t g_bsp_system_clock_select_ckio[] =
+{
+    BSP_PRV_CKIO_FREQ_125_MHZ,         // CKIO = 000b
+    BSP_PRV_CKIO_FREQ_83_3_MHZ,        // CKIO = 001b
+    BSP_PRV_CKIO_FREQ_62_5_MHZ,        // CKIO = 010b
+    BSP_PRV_CKIO_FREQ_50_MHZ,          // CKIO = 011b
+    BSP_PRV_CKIO_FREQ_41_7_MHZ,        // CKIO = 100b
+    BSP_PRV_CKIO_FREQ_35_7_MHZ,        // CKIO = 101b
+    BSP_PRV_CKIO_FREQ_31_25_MHZ,       // CKIO = 110b
+    BSP_PRV_CKIO_FREQ_NOT_SUPPORTED,   // CKIO = 111b
+};
+#endif
+
+/* System clock frequency information for XSPI_CLK */
+const uint32_t g_bsp_system_clock_select_xspi_clk[][2] =
+{
+    {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_150_MHZ      }, // FSELXSPIn = 000b
+    {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 001b
+    {BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ,     BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 010b
+    {BSP_PRV_XSPI_CLK_FREQ_100_MHZ,       BSP_PRV_XSPI_CLK_FREQ_75_MHZ       }, // FSELXSPIn = 011b
+    {BSP_PRV_XSPI_CLK_FREQ_50_MHZ,        BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ     }, // FSELXSPIn = 100b
+    {BSP_PRV_XSPI_CLK_FREQ_25_MHZ,        BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 101b
+    {BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ,      BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 110b
+    {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 111b
+};
+
+/* System clock frequency information for SPI_CLK */
+#if (1 == BSP_FEATURE_CGC_PCLKSPI_CLOCK_FREQ_TYPE)
+const uint32_t g_bsp_system_clock_select_spi_clk[] =
+{
+    BSP_PRV_PCLKSPI_FREQ_75_MHZ,       // SPInASYNCSEL = 0b
+    BSP_PRV_PCLKSPI_FREQ_96_MHZ,       // SPInASYNCSEL = 1b
+};
+#elif (2 == BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE)
+const uint32_t g_bsp_system_clock_select_spi_clk[] =
+{
+    BSP_PRV_PCLKSPI_FREQ_75_MHZ,       // SPInASYNCSEL = 00b
+    BSP_PRV_PCLKSPI_FREQ_80_MHZ,       // SPInASYNCSEL = 01b
+    BSP_PRV_PCLKSPI_FREQ_96_MHZ,       // SPInASYNCSEL = 10b
+    BSP_PRV_PCLKSPI_FREQ_100_MHZ,      // SPInASYNCSEL = 11b
+};
+#endif
+
+/* System clock frequency information for SCI_CLK */
+#if (1 == BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE)
+const uint32_t g_bsp_system_clock_select_sci_clk[] =
+{
+    BSP_PRV_PCLKSCI_FREQ_75_MHZ,       // SCInASYNCSEL = 0b
+    BSP_PRV_PCLKSCI_FREQ_96_MHZ,       // SCInASYNCSEL = 1b
+};
+#elif (2 == BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE)
+const uint32_t g_bsp_system_clock_select_sci_clk[] =
+{
+    BSP_PRV_PCLKSCI_FREQ_75_MHZ,       // SCInASYNCSEL = 00b
+    BSP_PRV_PCLKSCI_FREQ_80_MHZ,       // SCInASYNCSEL = 01b
+    BSP_PRV_PCLKSCI_FREQ_96_MHZ,       // SCInASYNCSEL = 10b
+    BSP_PRV_PCLKSCI_FREQ_100_MHZ,      // SCInASYNCSEL = 11b
+};
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/* FSP pack version structure. */
+static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) =
+{
+    .version_id_b =
+    {
+        .minor = FSP_VERSION_MINOR,
+        .major = FSP_VERSION_MAJOR,
+        .build = FSP_VERSION_BUILD,
+        .patch = FSP_VERSION_PATCH
+    }
+};
+
+/* Public FSP version name. */
+static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
+    FSP_VERSION_STRING;
+
+/* Unique FSP version ID. */
+static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
+    FSP_VERSION_BUILD_STRING;
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+
+/** Prototype of initialization function called before main.  This prototype sets the weak association of this
+ * function to an internal example implementation. If this function is defined in the application code, the
+ * application code version is used. */
+
+void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE;
+
+void bsp_init_internal(void * p_args); /// Default initialization function
+
+#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
+
+/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1.  This
+ * prototype sets the weak association of this function to an internal example implementation. */
+
+void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE;
+
+void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function
+
+#endif
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Get the FSP version based on compile time macros.
+ *
+ * @param[out] p_version        Memory address to return version information to.
+ *
+ * @retval FSP_SUCCESS          Version information stored.
+ * @retval FSP_ERR_ASSERTION    The parameter p_version is NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version)
+{
+#if BSP_CFG_PARAM_CHECKING_ENABLE
+
+    /** Verify parameters are valid */
+    FSP_ASSERT(NULL != p_version);
+#endif
+
+    *p_version = g_fsp_version;
+
+    return FSP_SUCCESS;
+}
+
+#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
+
+/*******************************************************************************************************************//**
+ * Default error logger function, used only if fsp_error_log is not defined in the user application.
+ *
+ * @param[in]  err     The error code encountered.
+ * @param[in]  file    The file name in which the error code was encountered.
+ * @param[in]  line    The line number at which the error code was encountered.
+ **********************************************************************************************************************/
+void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line)
+{
+    /** Do nothing. Do not generate any 'unused' warnings. */
+    FSP_PARAMETER_NOT_USED(err);
+    FSP_PARAMETER_NOT_USED(file);
+    FSP_PARAMETER_NOT_USED(line);
+}
+
+#endif
+
+/** @} (end addtogroup BSP_MCU) */
+
+/*******************************************************************************************************************//**
+ * Default initialization function, used only if bsp_init is not defined in the user application.
+ **********************************************************************************************************************/
+void bsp_init_internal (void * p_args)
+{
+    /* Do nothing. */
+    FSP_PARAMETER_NOT_USED(p_args);
+}
+
+#if defined(__ARMCC_VERSION)
+
+/*******************************************************************************************************************//**
+ * Default implementation of assert for AC6.
+ **********************************************************************************************************************/
+__attribute__((weak, noreturn))
+void __aeabi_assert (const char * expr, const char * file, int line) {
+    FSP_PARAMETER_NOT_USED(expr);
+    FSP_PARAMETER_NOT_USED(file);
+    FSP_PARAMETER_NOT_USED(line);
+    __BKPT(0);
+    while (1)
+    {
+        /* Do nothing. */
+    }
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Allocate memory dynamically to heap.
+ *
+ * @param[in]   size    Size of memory allocated.
+ *
+ * @return      Returns a void pointer to the allocated area. If no memory is allocated, returns NULL.
+ **********************************************************************************************************************/
+void * bsp_prv_malloc (size_t size)
+{
+#if (2 == BSP_CFG_RTOS) && configSUPPORT_DYNAMIC_ALLOCATION
+
+    /* Use FreeRTOS heap */
+    return pvPortMalloc(size);
+#else
+
+    /* If RTOS dynamic allocation is disabled or RTOS is not in use, allocate heap data to the main heap. */
+    return malloc(size);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Free dynamically allocated memory on heap.
+ *
+ * @param[in]   ptr     Pointer to memory to be released
+ **********************************************************************************************************************/
+void bsp_prv_free (void * ptr)
+{
+#if (2 == BSP_CFG_RTOS) && configSUPPORT_DYNAMIC_ALLOCATION
+
+    /* Use FreeRTOS heap */
+    vPortFree(ptr);
+#else
+
+    /* If RTOS dynamic allocation is disabled or RTOS is not in use, use free(). */
+    free(ptr);
+#endif
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_common.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_common.h
new file mode 100644
index 00000000..71c77f56
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_common.h
@@ -0,0 +1,737 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_COMMON_H
+#define BSP_COMMON_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* C99 includes. */
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <assert.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* Different compiler support. */
+#include "../../inc/fsp_common_api.h"
+#include "bsp_compiler_support.h"
+#include "bsp_cfg.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** Used to signify that an ELC event is not able to be used as an interrupt. */
+#define BSP_IRQ_DISABLED                       (0xFFU)
+
+/* Vector Number offset */
+#define BSP_VECTOR_NUM_OFFSET                  (32)
+#define BSP_INTERRUPT_TYPE_OFFSET              (16U)
+
+#define FSP_CONTEXT_SAVE
+#define FSP_CONTEXT_RESTORE
+
+#define BSP_PRV_CPU_FREQ_1000_MHZ              (1000000000U) // CPU frequency is 1000 MHz
+#define BSP_PRV_CPU_FREQ_500_MHZ               (500000000U)  // CPU frequency is 500 MHz
+#define BSP_PRV_CPU_FREQ_200_MHZ               (200000000U)  // CPU frequency is 200 MHz
+#define BSP_PRV_CPU_FREQ_150_MHZ               (150000000U)  // CPU frequency is 150 MHz
+
+#define BSP_PRV_CA55CLK_FREQ_1200_MHZ          (1200000000U) // CA55CLK frequency is 1200 MHz
+#define BSP_PRV_CA55CLK_FREQ_600_MHZ           (600000000U)  // CA55CLK frequency is 600 MHz
+
+#define BSP_PRV_CA55SCLK_FREQ_1000_MHZ         (1000000000U) // CA55SCLK frequency is 500 MHz
+#define BSP_PRV_CA55SCLK_FREQ_500_MHZ          (500000000U)  // CA55SCLK frequency is 500 MHz
+
+#define BSP_PRV_ICLK_FREQ_200_MHZ              (200000000U)  // ICLK frequency is 200 MHz
+#define BSP_PRV_ICLK_FREQ_150_MHZ              (150000000U)  // ICLK frequency is 150 MHz
+
+#define BSP_PRV_PCLKAM_FREQ_200_MHz            (200000000U)  // PCLKAM frequency is 200 MHz
+
+#define BSP_PRV_PCLKH_FREQ_250_MHZ             (250000000U)  // PCLKH frequency is 250 MHz
+#define BSP_PRV_PCLKH_FREQ_200_MHZ             (200000000U)  // PCLKH frequency is 200 MHz
+#define BSP_PRV_PCLKH_FREQ_150_MHZ             (150000000U)  // PCLKH frequency is 150 MHz
+
+#define BSP_PRV_PCLKM_FREQ_125_MHZ             (125000000U)  // PCLKM frequency is 125 MHz
+#define BSP_PRV_PCLKM_FREQ_100_MHZ             (100000000U)  // PCLKM frequency is 100 MHz
+#define BSP_PRV_PCLKM_FREQ_75_MHZ              (75000000U)   // PCLKM frequency is 750 MHz
+
+#define BSP_PRV_PCLKL_FREQ_62_5_MHZ            (62500000U)   // PCLKL frequency is 62.5 MHz
+#define BSP_PRV_PCLKL_FREQ_50_MHZ              (50000000U)   // PCLKL frequency is 50 MHz
+#define BSP_PRV_PCLKL_FREQ_37_5_MHZ            (37500000U)   // PCLKL frequency is 37.5 MHz
+
+#define BSP_PRV_PCLKADC_FREQ_25_MHZ            (25000000U)   // PCLKADC frequency is 25 MHz
+#define BSP_PRV_PCLKADC_FREQ_18_75_MHZ         (18750000U)   // PCLKADC frequency is 18.75 MHz
+
+#define BSP_PRV_PCLKGPTL_FREQ_500_MHZ          (500000000U)  // PCLKGPTL frequency is 500 MHz
+#define BSP_PRV_PCLKGPTL_FREQ_400_MHZ          (400000000U)  // PCLKGPTL frequency is 400 MHz
+#define BSP_PRV_PCLKGPTL_FREQ_300_MHZ          (300000000U)  // PCLKGPTL frequency is 300 MHz
+
+#define BSP_PRV_PCLKSCI_FREQ_75_MHZ            (75000000U)   // PCLKSCI frequency is 75 MHz
+#define BSP_PRV_PCLKSCI_FREQ_80_MHZ            (80000000U)   // PCLKSCI frequency is 80 MHz
+#define BSP_PRV_PCLKSCI_FREQ_96_MHZ            (96000000U)   // PCLKSCI frequency is 96 MHz
+#define BSP_PRV_PCLKSCI_FREQ_100_MHZ           (100000000U)  // PCLKSCI frequency is 100 MHz
+
+#define BSP_PRV_PCLKSPI_FREQ_75_MHZ            (75000000U)   // PCLKSPI frequency is 75 MHz
+#define BSP_PRV_PCLKSPI_FREQ_80_MHZ            (80000000U)   // PCLKSPI frequency is 80 MHz
+#define BSP_PRV_PCLKSPI_FREQ_96_MHZ            (96000000U)   // PCLKSPI frequency is 96 MHz
+#define BSP_PRV_PCLKSPI_FREQ_100_MHZ           (100000000U)  // PCLKSPI frequency is 100 MHz
+
+#define BSP_PRV_PCLKENCO_FREQ_20_MHZ           (20000000U)   // PCLKENCO frequency is 20 MHz
+#define BSP_PRV_PCLKENCO_FREQ_80_MHZ           (80000000U)   // PCLKENCO frequency is 80 MHz
+
+#define BSP_PRV_PCLKCAN_FREQ_80_MHZ            (80000000U)   // PCLKCAN frequency is 80 MHz
+#define BSP_PRV_PCLKCAN_FREQ_40_MHZ            (40000000U)   // PCLKCAN frequency is 40 MHz
+
+#define BSP_PRV_CKIO_FREQ_125_MHZ              (125000000U)  // CKIO frequency is 125 MHz
+#define BSP_PRV_CKIO_FREQ_100_MHZ              (100000000U)  // CKIO frequency is 100 MHz
+#define BSP_PRV_CKIO_FREQ_83_3_MHZ             (83333333U)   // CKIO frequency is 83.3 MHz
+#define BSP_PRV_CKIO_FREQ_75_MHZ               (75000000U)   // CKIO frequency is 75 MHz
+#define BSP_PRV_CKIO_FREQ_66_7_MHZ             (66666666U)   // CKIO frequency is 66.7 MHz
+#define BSP_PRV_CKIO_FREQ_62_5_MHZ             (62500000U)   // CKIO frequency is 62.5 MHz
+#define BSP_PRV_CKIO_FREQ_50_MHZ               (50000000U)   // CKIO frequency is 50 MHz
+#define BSP_PRV_CKIO_FREQ_41_7_MHZ             (41666666U)   // CKIO frequency is 41.6 MHz
+#define BSP_PRV_CKIO_FREQ_40_MHZ               (40000000U)   // CKIO frequency is 40 MHz
+#define BSP_PRV_CKIO_FREQ_37_5_MHZ             (37500000U)   // CKIO frequency is 37.5 MHz
+#define BSP_PRV_CKIO_FREQ_35_7_MHZ             (35714285U)   // CKIO frequency is 125 MHz
+#define BSP_PRV_CKIO_FREQ_33_3_MHZ             (33333333U)   // CKIO frequency is 33.3MHz
+#define BSP_PRV_CKIO_FREQ_31_25_MHZ            (31250000U)   // CKIO frequency is 31.25 MHz
+#define BSP_PRV_CKIO_FREQ_30_MHZ               (30000000U)   // CKIO frequency is 30 MHz
+#define BSP_PRV_CKIO_FREQ_28_6_MHZ             (28571428U)   // CKIO frequency is 28.6 MHz
+#define BSP_PRV_CKIO_FREQ_25_MHZ               (25000000U)   // CKIO frequency is 25 MHz
+#define BSP_PRV_CKIO_FREQ_21_4_MHZ             (21428571U)   // CKIO frequency is 21.4 MHz
+#define BSP_PRV_CKIO_FREQ_18_75_MHZ            (18750000U)   // CKIO frequency is 18.75 MHz
+#define BSP_PRV_CKIO_FREQ_NOT_SUPPORTED        (0xFFFFFFFFU) // CKIO frequency is not supported
+
+#define BSP_PRV_XSPI_CLK_FREQ_150_MHZ          (150000000U)  // XSPI_CLK frequency is 150.0 MHz
+#define BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ        (133333333U)  // XSPI_CLK frequency is 133.3 MHz
+#define BSP_PRV_XSPI_CLK_FREQ_100_MHZ          (100000000U)  // XSPI_CLK frequency is 100.0 MHz
+#define BSP_PRV_XSPI_CLK_FREQ_75_MHZ           (75000000U)   // XSPI_CLK frequency is 75.0 MHz
+#define BSP_PRV_XSPI_CLK_FREQ_50_MHZ           (50000000U)   // XSPI_CLK frequency is 50.0 MHz
+#define BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ         (37500000U)   // XSPI_CLK frequency is 37.5 MHz
+#define BSP_PRV_XSPI_CLK_FREQ_25_MHZ           (25000000U)   // XSPI_CLK frequency is 25.0 MHz
+#define BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ         (12500000U)   // XSPI_CLK frequency is 12.5 MHz
+#define BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED    (0xFFFFFFFFU) // XSPI_CLK frequency is not supported
+
+/** Macro to log and return error without an assertion. */
+#ifndef FSP_RETURN
+
+ #define FSP_RETURN(err)    FSP_ERROR_LOG((err)); \
+    return err;
+#endif
+
+/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
+ * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
+#if (1 == BSP_CFG_ERROR_LOG)
+
+ #ifndef FSP_ERROR_LOG
+  #define FSP_ERROR_LOG(err) \
+    fsp_error_log((err), __FILE__, __LINE__);
+ #endif
+#else
+
+ #define FSP_ERROR_LOG(err)
+#endif
+
+/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
+ * functions. */
+#if (3 == BSP_CFG_ASSERT)
+ #define FSP_ASSERT(a)
+ #define FSP_ASSERT_NOT_RETURN_VALUE(a)
+#elif (2 == BSP_CFG_ASSERT)
+ #define FSP_ASSERT(a)                     {assert(a);}
+ #define FSP_ASSERT_NOT_RETURN_VALUE(a)    {assert(a);}
+#else
+ #define FSP_ASSERT(a)                     FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
+ #define FSP_ASSERT_NOT_RETURN_VALUE(a)    FSP_ERROR_NOT_RETURN_VALUE((a), FSP_ERR_ASSERTION)
+#endif                                 // ifndef FSP_ASSERT
+
+/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
+ * to identify runtime errors in FSP functions. */
+
+#define FSP_ERROR_RETURN(a, err)                        \
+    {                                                   \
+        if ((a))                                        \
+        {                                               \
+            (void) 0;                  /* Do nothing */ \
+        }                                               \
+        else                                            \
+        {                                               \
+            FSP_ERROR_LOG(err);                         \
+            return err;                                 \
+        }                                               \
+    }
+
+/** This function performs the same operation as ::FSP_ERROR_RETURN, but can be applied to functions that do not return
+ *  an error code. */
+
+#define FSP_ERROR_NOT_RETURN_VALUE(a, err)              \
+    {                                                   \
+        if ((a))                                        \
+        {                                               \
+            (void) 0;                  /* Do nothing */ \
+        }                                               \
+        else                                            \
+        {                                               \
+            FSP_ERROR_LOG(err);                         \
+            return;                                     \
+        }                                               \
+    }
+
+/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
+ * This macro can be redefined to add a timeout if necessary. */
+#ifndef FSP_HARDWARE_REGISTER_WAIT
+ #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value)    while (reg != required_value) { /* Wait. */}
+#endif
+
+/* Function-like macro used to wait for a condition to be met with timeout,
+ * most often used to wait for hardware register updates. */
+#define BSP_HARDWARE_REGISTER_WAIT_WTIH_TIMEOUT(reg, required_value, timeout) \
+    while ((timeout))                                                         \
+    {                                                                         \
+        if ((required_value) == (reg))                                        \
+        {                                                                     \
+            break;                                                            \
+        }                                                                     \
+        (timeout)--;                                                          \
+    }
+
+#ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
+ #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION    (0U)
+#endif
+
+/* This macro defines a variable for saving previous mask value */
+#ifndef FSP_CRITICAL_SECTION_DEFINE
+
+ #define FSP_CRITICAL_SECTION_DEFINE              uintptr_t old_mask_level = 0U
+#endif
+
+/* These macros abstract methods to save and restore the interrupt state. */
+#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE    __get_ICC_PMR
+#define FSP_CRITICAL_SECTION_SET_STATE            __set_ICC_PMR
+#define FSP_CRITICAL_SECTION_IRQ_MASK_SET         ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
+                                                              BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT))
+
+/** This macro temporarily saves the current interrupt state and disables interrupts. */
+#ifndef FSP_CRITICAL_SECTION_ENTER
+ #define FSP_CRITICAL_SECTION_ENTER                            \
+    old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
+    FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
+#endif
+
+/** This macro restores the previously saved interrupt state, reenabling interrupts. */
+#ifndef FSP_CRITICAL_SECTION_EXIT
+ #define FSP_CRITICAL_SECTION_EXIT              FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
+#endif
+
+/* Number of Cortex processor exceptions. */
+#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS    (32U)
+
+/** Used to signify that the requested IRQ vector is not defined in this system. */
+#define FSP_INVALID_VECTOR                      ((IRQn_Type) - 33)
+
+/* This macro Enable or Disable interrupts. */
+#if defined(BSP_CFG_CORE_CA55)
+ #define BSP_INTERRUPT_ENABLE                   __enable_fiq()
+
+ #define BSP_INTERRUPT_DISABLE                  __disable_fiq()
+
+#elif defined(BSP_CFG_CORE_CR52)
+ #define BSP_INTERRUPT_ENABLE                   __asm volatile ("cpsie i"); \
+    __asm volatile ("isb");
+
+ #define BSP_INTERRUPT_DISABLE                  __asm volatile ("cpsid i"); \
+    __asm volatile ("isb");
+#endif
+
+/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
+ *  alert the user of the error. The user can override this default behavior by defining their own
+ *  BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
+ */
+#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
+
+ #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x)    __BKPT((x))
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Different warm start entry locations in the BSP. */
+typedef enum e_bsp_warm_start_event
+{
+    BSP_WARM_START_RESET = 0,          ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
+    BSP_WARM_START_POST_CLOCK,         ///< Called after clock initialization. No C runtime environment or IRQs.
+    BSP_WARM_START_POST_C,             ///< Called after clocks and C runtime environment have been set up
+} bsp_warm_start_event_t;
+
+/* Private enum used in R_FSP_SystemClockHzGet. */
+typedef enum e_fsp_priv_clock
+{
+    FSP_PRIV_CLOCK_CPU0,
+    FSP_PRIV_CLOCK_CPU1,
+    FSP_PRIV_CLOCK_CA55C0,
+    FSP_PRIV_CLOCK_CA55C1,
+    FSP_PRIV_CLOCK_CA55C2,
+    FSP_PRIV_CLOCK_CA55C3,
+    FSP_PRIV_CLOCK_CA55SCLK,
+    FSP_PRIV_CLOCK_ICLK,
+    FSP_PRIV_CLOCK_PCLKH,
+    FSP_PRIV_CLOCK_PCLKM,
+    FSP_PRIV_CLOCK_PCLKL,
+    FSP_PRIV_CLOCK_PCLKADC,
+    FSP_PRIV_CLOCK_PCLKGPTL,
+    FSP_PRIV_CLOCK_PCLKENCO,
+    FSP_PRIV_CLOCK_PCLKSPI0,
+    FSP_PRIV_CLOCK_PCLKSPI1,
+    FSP_PRIV_CLOCK_PCLKSPI2,
+    FSP_PRIV_CLOCK_PCLKSPI3,
+    FSP_PRIV_CLOCK_PCLKSCI0,
+    FSP_PRIV_CLOCK_PCLKSCI1,
+    FSP_PRIV_CLOCK_PCLKSCI2,
+    FSP_PRIV_CLOCK_PCLKSCI3,
+    FSP_PRIV_CLOCK_PCLKSCI4,
+    FSP_PRIV_CLOCK_PCLKSCI5,
+    FSP_PRIV_CLOCK_PCLKSCIE0,
+    FSP_PRIV_CLOCK_PCLKSCIE1,
+    FSP_PRIV_CLOCK_PCLKSCIE2,
+    FSP_PRIV_CLOCK_PCLKSCIE3,
+    FSP_PRIV_CLOCK_PCLKSCIE4,
+    FSP_PRIV_CLOCK_PCLKSCIE5,
+    FSP_PRIV_CLOCK_PCLKSCIE6,
+    FSP_PRIV_CLOCK_PCLKSCIE7,
+    FSP_PRIV_CLOCK_PCLKSCIE8,
+    FSP_PRIV_CLOCK_PCLKSCIE9,
+    FSP_PRIV_CLOCK_PCLKSCIE10,
+    FSP_PRIV_CLOCK_PCLKSCIE11,
+    FSP_PRIV_CLOCK_PCLKCAN,
+    FSP_PRIV_CLOCK_CKIO,
+    FSP_PRIV_CLOCK_XSPI0_CLK,
+    FSP_PRIV_CLOCK_XSPI1_CLK,
+    FSP_PRIV_CLOCK_PCLKAM
+} fsp_priv_clock_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+#if (1 == BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE)
+extern const uint32_t g_bsp_system_clock_select_ckio[][2];
+#elif (2 == BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE)
+extern const uint32_t g_bsp_system_clock_select_ckio[];
+#endif
+extern const uint32_t g_bsp_system_clock_select_xspi_clk[][2];
+extern const uint32_t g_bsp_system_clock_select_spi_clk[];
+extern const uint32_t g_bsp_system_clock_select_sci_clk[];
+
+extern IRQn_Type g_current_interrupt_num[];
+extern uint8_t   g_current_interrupt_pointer;
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Inline Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Return active interrupt vector number value
+ *
+ * @return     Active interrupt vector number value
+ **********************************************************************************************************************/
+__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
+{
+    /* Return the current interrupt number. */
+    return g_current_interrupt_num[(g_current_interrupt_pointer - 1U)];
+}
+
+/*******************************************************************************************************************//**
+ * Gets the frequency of a system clock.
+ *
+ * @return     Frequency of requested clock in Hertz.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
+{
+    uint32_t clock_hz = 0;
+
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+    uint32_t fselcpu0  = R_SYSC_S->SCKCR2_b.FSELCPU0;
+    uint32_t divselsub = R_SYSC_S->SCKCR2_b.DIVSELSUB;
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+    uint32_t cr52cpu0 = R_SYSC_S->SCKCR2_b.CR52CPU0;
+    uint32_t cr52cpu1 = R_SYSC_S->SCKCR2_b.CR52CPU1;
+#endif
+    switch (clock)
+    {
+        case FSP_PRIV_CLOCK_CPU0:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == divselsub) ? BSP_PRV_CPU_FREQ_200_MHZ : BSP_PRV_CPU_FREQ_150_MHZ;
+            clock_hz = clock_hz << fselcpu0;
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == cr52cpu0) ? BSP_PRV_CPU_FREQ_500_MHZ : BSP_PRV_CPU_FREQ_1000_MHZ;
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_CPU1:
+        {
+#if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == cr52cpu1) ? BSP_PRV_CPU_FREQ_500_MHZ : BSP_PRV_CPU_FREQ_1000_MHZ;
+#endif
+            break;
+        }
+
+#if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+        case FSP_PRIV_CLOCK_CA55C0:
+        {
+            uint32_t ca55core0 = R_SYSC_S->SCKCR2_b.CA55CORE0;
+            clock_hz = (0 == ca55core0) ? BSP_PRV_CA55CLK_FREQ_600_MHZ : BSP_PRV_CA55CLK_FREQ_1200_MHZ;
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_CA55C1:
+        {
+            uint32_t ca55core1 = R_SYSC_S->SCKCR2_b.CA55CORE1;
+            clock_hz = (0 == ca55core1) ? BSP_PRV_CA55CLK_FREQ_600_MHZ : BSP_PRV_CA55CLK_FREQ_1200_MHZ;
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_CA55C2:
+        {
+            uint32_t ca55core2 = R_SYSC_S->SCKCR2_b.CA55CORE2;
+            clock_hz = (0 == ca55core2) ? BSP_PRV_CA55CLK_FREQ_600_MHZ : BSP_PRV_CA55CLK_FREQ_1200_MHZ;
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_CA55C3:
+        {
+            uint32_t ca55core3 = R_SYSC_S->SCKCR2_b.CA55CORE3;
+            clock_hz = (0 == ca55core3) ? BSP_PRV_CA55CLK_FREQ_600_MHZ : BSP_PRV_CA55CLK_FREQ_1200_MHZ;
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_CA55SCLK:
+        {
+            uint32_t ca55sclk = R_SYSC_S->SCKCR2_b.CA55SCLK;
+            clock_hz = (0 == ca55sclk) ? BSP_PRV_CA55SCLK_FREQ_500_MHZ : BSP_PRV_CA55SCLK_FREQ_1000_MHZ;
+            break;
+        }
+#endif
+
+        case FSP_PRIV_CLOCK_ICLK:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == divselsub) ? BSP_PRV_ICLK_FREQ_200_MHZ : BSP_PRV_ICLK_FREQ_150_MHZ;
+#endif
+            break;
+        }
+
+#if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+        case FSP_PRIV_CLOCK_PCLKAM:
+        {
+            clock_hz = BSP_PRV_PCLKAM_FREQ_200_MHz;
+            break;
+        }
+#endif
+
+        case FSP_PRIV_CLOCK_PCLKH:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == divselsub) ? BSP_PRV_PCLKH_FREQ_200_MHZ : BSP_PRV_PCLKH_FREQ_150_MHZ;
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = BSP_PRV_PCLKH_FREQ_250_MHZ;
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKM:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == divselsub) ? BSP_PRV_PCLKM_FREQ_100_MHZ : BSP_PRV_PCLKM_FREQ_75_MHZ;
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = BSP_PRV_PCLKM_FREQ_125_MHZ;
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKL:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == divselsub) ? BSP_PRV_PCLKL_FREQ_50_MHZ : BSP_PRV_PCLKL_FREQ_37_5_MHZ;
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = BSP_PRV_PCLKL_FREQ_62_5_MHZ;
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKADC:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == divselsub) ? BSP_PRV_PCLKADC_FREQ_25_MHZ : BSP_PRV_PCLKADC_FREQ_18_75_MHZ;
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = BSP_PRV_PCLKADC_FREQ_25_MHZ;
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKGPTL:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = (0 == divselsub) ? BSP_PRV_PCLKGPTL_FREQ_400_MHZ : BSP_PRV_PCLKGPTL_FREQ_300_MHZ;
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = BSP_PRV_PCLKGPTL_FREQ_500_MHZ;
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSPI0:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI0ASYNCSEL];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI0ASYNCSEL];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSPI1:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI1ASYNCSEL];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI1ASYNCSEL];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSPI2:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI2ASYNCSEL];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI2ASYNCSEL];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSPI3:
+        {
+            clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_S->SCKCR2_b.SPI3ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCI0:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI0ASYNCSEL];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI0ASYNCSEL];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCI1:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI1ASYNCSEL];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI1ASYNCSEL];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCI2:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI2ASYNCSEL];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI2ASYNCSEL];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCI3:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI3ASYNCSEL];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI3ASYNCSEL];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCI4:
+        {
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI4ASYNCSEL];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI4ASYNCSEL];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCI5:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_S->SCKCR2_b.SCI5ASYNCSEL];
+            break;
+        }
+
+#if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+        case FSP_PRIV_CLOCK_PCLKSCIE0:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE0ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE1:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE1ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE2:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE2ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE3:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE3ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE4:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE4ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE5:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE5ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE6:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE6ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE7:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE7ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE8:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE8ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE9:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE9ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE10:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE10ASYNCSEL];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_PCLKSCIE11:
+        {
+            clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE11ASYNCSEL];
+            break;
+        }
+#endif
+
+        case FSP_PRIV_CLOCK_PCLKCAN:
+        {
+            uint32_t fselcanfd = R_SYSC_NS->SCKCR_b.FSELCANFD;
+            clock_hz = (0 == fselcanfd) ? BSP_PRV_PCLKCAN_FREQ_80_MHZ : BSP_PRV_PCLKCAN_FREQ_40_MHZ;
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_CKIO:
+        {
+            uint32_t ckio = R_SYSC_NS->SCKCR_b.CKIO;
+#if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_ckio[ckio][divselsub];
+#elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = g_bsp_system_clock_select_ckio[ckio];
+#endif
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_XSPI0_CLK:
+        {
+            uint32_t fselxspi0 = R_SYSC_NS->SCKCR_b.FSELXSPI0;
+            clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi0][R_SYSC_NS->SCKCR_b.DIVSELXSPI0];
+            break;
+        }
+
+        case FSP_PRIV_CLOCK_XSPI1_CLK:
+        {
+            uint32_t fselxspi1 = R_SYSC_NS->SCKCR_b.FSELXSPI1;
+            clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi1][R_SYSC_NS->SCKCR_b.DIVSELXSPI1];
+            break;
+        }
+
+#if (BSP_FEATURE_BSP_ENCOUT_SUPPORTED)
+        case FSP_PRIV_CLOCK_PCLKENCO:
+        {
+ #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            clock_hz = BSP_PRV_PCLKENCO_FREQ_20_MHZ;
+ #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
+            uint32_t encoutclk = R_SYSC_NS->SCKCR4_b.ENCOUTCLK;
+            clock_hz = (0 == encoutclk) ? BSP_PRV_PCLKENCO_FREQ_20_MHZ : BSP_PRV_PCLKENCO_FREQ_80_MHZ;
+ #endif
+            break;
+        }
+#endif
+
+        default:
+        {
+            break;
+        }
+    }
+
+    return clock_hz;
+}
+
+#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
+
+/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
+void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
+
+#endif
+
+/** @} (end addtogroup BSP_MCU) */
+
+void * bsp_prv_malloc(size_t size);
+void   bsp_prv_free(void * ptr);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h
new file mode 100644
index 00000000..60cc7d00
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h
@@ -0,0 +1,104 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BSP_COMPILER_SUPPORT_H
+#define BSP_COMPILER_SUPPORT_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ #include <arm_cmse.h>
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#if defined(__ARMCC_VERSION)           /* AC6 compiler */
+
+/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load
+ * memory (ROM) is reserved unnecessarily. */
+ #define BSP_UNINIT_SECTION_PREFIX         ".bss"
+ #define BSP_SECTION_HEAP                  BSP_UNINIT_SECTION_PREFIX ".heap"
+ #define BSP_DONT_REMOVE
+ #define BSP_ATTRIBUTE_STACKLESS           __attribute__((naked))
+ #define BSP_FORCE_INLINE                  __attribute__((always_inline))
+ #define BSP_TARGET_ARM                    #pragma arm
+#elif   defined(__GNUC__)              /* GCC compiler */
+ #define BSP_UNINIT_SECTION_PREFIX
+ #define BSP_SECTION_HEAP                  ".heap"
+ #define BSP_DONT_REMOVE
+ #define BSP_LP64_SUPPORT                  __LP64__
+ #if 1 == BSP_LP64_SUPPORT
+  #define BSP_ATTRIBUTE_STACKLESS
+ #else
+  #define BSP_ATTRIBUTE_STACKLESS          __attribute__((naked))
+ #endif
+ #define BSP_FORCE_INLINE                  __attribute__((always_inline))
+ #define BSP_TARGET_ARM                    __attribute__((target("arm")))
+#elif defined(__ICCARM__)              /* IAR compiler */
+ #define BSP_UNINIT_SECTION_PREFIX
+ #define BSP_SECTION_HEAP                  "HEAP"
+ #define BSP_DONT_REMOVE                   __root
+ #define BSP_LP64_SUPPORT                  __lp64__
+ #define BSP_ATTRIBUTE_STACKLESS           __stackless
+ #define BSP_FORCE_INLINE                  _Pragma("inline=forced")
+ #define BSP_TARGET_ARM                    __arm
+#endif
+
+#define BSP_SECTION_AARCH64_STACK          BSP_UNINIT_SECTION_PREFIX ".aarch64_stack"
+#define BSP_SECTION_FIQ_STACK              BSP_UNINIT_SECTION_PREFIX ".fiq_stack"
+#define BSP_SECTION_IRQ_STACK              BSP_UNINIT_SECTION_PREFIX ".irq_stack"
+#define BSP_SECTION_ABT_STACK              BSP_UNINIT_SECTION_PREFIX ".abt_stack"
+#define BSP_SECTION_UND_STACK              BSP_UNINIT_SECTION_PREFIX ".und_stack"
+#define BSP_SECTION_SYS_STACK              BSP_UNINIT_SECTION_PREFIX ".sys_stack"
+#define BSP_SECTION_SVC_STACK              BSP_UNINIT_SECTION_PREFIX ".svc_stack"
+#define BSP_SECTION_NOINIT                 BSP_UNINIT_SECTION_PREFIX ".noinit"
+#define BSP_SECTION_FIXED_VECTORS          ".fixed_vectors"
+#define BSP_SECTION_APPLICATION_VECTORS    ".application_vectors"
+#define BSP_SECTION_ROM_REGISTERS          ".rom_registers"
+#define BSP_SECTION_ID_CODE                ".id_code"
+#define BSP_SECTION_LOADER_PARAM           ".loader_param"
+#define BSP_SECTION_MMU_TABLE_SECTION      ".ttbr"
+
+/* Compiler neutral macros. */
+#define BSP_PLACE_IN_SECTION(x)    __attribute__((section(x))) __attribute__((__used__))
+
+#define BSP_ALIGN_VARIABLE(x)      __attribute__((aligned(x)))
+
+#define BSP_PACKED             __attribute__((aligned(1)))
+
+#define BSP_WEAK_REFERENCE     __attribute__((weak))
+
+/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */
+#define BSP_STACK_ALIGNMENT    (8)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** @} (end of addtogroup BSP_MCU) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr.c
new file mode 100644
index 00000000..47a155ae
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr.c
@@ -0,0 +1,727 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include <stdio.h>
+#include "bsp_api.h"
+
+#if (BSP_FEATURE_DDR_SUPPORTED)
+ #if (1 == BSP_CFG_DDR_INIT_ENABLE)
+  #include "bsp_ddr.h"
+  #include "bsp_ddr_fw_param.h"
+
+  #if (1 == BSP_CFG_BOARD_RZN2H_EVB)
+   #include "../../../../../board/rzn2h_evb/board_ddr_param.h"
+  #elif (1 == BSP_CFG_BOARD_CUSTOM)
+   #include "../../../../../board/custom/board_ddr_param.h"
+  #endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+  #define ARRAY_SIZE(a)    (sizeof(a) / sizeof(a[0]))
+  #define BSP_PRV_DDR_PHYINIT_TIMEOUT    (500000U)
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_reg_init(void);
+static void bsp_prv_ddr_phyinit_c(void);
+static void bsp_prv_ddr_phyinit_d2h_1d(void);
+static void bsp_prv_ddr_phyinit_d2h_2d(void);
+static void bsp_prv_ddr_phyinit_mc(void);
+static void bsp_prv_ddr_phyinit_i(void);
+static void bsp_prv_ddr_phyinit_j(void);
+
+  #if (1 == BSP_CFG_DDR_ZERO_INITIALIZED_ENABLE)
+static void bsp_prv_ddr_prog_all0(uint64_t start_addr, uint32_t addr_space);
+
+  #endif
+
+static int8_t bsp_prv_dwc_ddrphy_cdd_int(uint8_t val);
+static int8_t bsp_prv_dwc_ddrphy_cdd_abs(uint8_t val);
+
+static uint32_t bsp_get_mail(uint8_t mode_32bits);
+static void     bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone(uint8_t sel_train);
+static void     bsp_prv_ddr_setup_mc(void);
+static void     bsp_prv_ddr_update_mc(void);
+
+static void bsp_prv_ddr_phyinit_configuration(void);
+static void bsp_prv_ddr_phyinit_pin_swizzling(void);
+static void bsp_prv_ddr_phyinit_load_1d_image(void);
+static void bsp_prv_ddr_phyinit_exec_1d_image(void);
+static void bsp_prv_ddr_phyinit_load_2d_image(void);
+static void bsp_prv_ddr_phyinit_exec_2d_image(void);
+static void bsp_prv_ddr_phyinit_load_eng_image(void);
+
+const uint32_t param_phyinit_c_size       = ARRAY_SIZE(param_phyinit_c);
+const uint32_t param_phyinit_i_size       = ARRAY_SIZE(param_phyinit_i);
+const uint32_t param_phyinit_f_1d_0_size  = ARRAY_SIZE(param_phyinit_f_1d_0);
+const uint32_t param_phyinit_f_2d_0_size  = ARRAY_SIZE(param_phyinit_f_2d_0);
+const uint32_t param_phyinit_swizzle_size = ARRAY_SIZE(param_phyinit_swizzle);
+const uint32_t param_mcinit_size          = ARRAY_SIZE(param_mcinit);
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_reg_init
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_reg_init (void)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_RST_N);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_RST_PWROKLN);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_RESET);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI0_ARESETN);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI1_ARESETN);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI2_ARESETN);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI3_ARESETN);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI4_ARESETN);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_MC_PRESETN);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_PHY_PRESETN);
+
+    R_BSP_MODULE_START(FSP_IP_DDRSS, 0);
+
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_ddr_init
+ **********************************************************************************************************************/
+void bsp_ddr_init (void)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+
+    R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_A0_IF);
+    R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_A1_IF);
+    R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_R2_IF);
+    R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_R3_IF);
+    R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_A4_IF);
+    R_SSC->SSTPCR4_b.DDRAPB = 0;
+
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+
+    bsp_prv_ddr_reg_init();
+
+    bsp_prv_ddr_setup_mc();
+
+    bsp_prv_ddr_phyinit_c();
+    bsp_prv_ddr_phyinit_d2h_1d();
+    bsp_prv_ddr_phyinit_d2h_2d();
+
+    bsp_prv_ddr_phyinit_mc();
+
+    bsp_prv_ddr_phyinit_i();
+    bsp_prv_ddr_phyinit_j();
+
+  #if (1 == BSP_CFG_DDR_ZERO_INITIALIZED_ENABLE)
+    uint32_t val;
+    uint32_t addr_space, end_addr17;
+
+    val = R_DDRSS->DDR_MEMC_DENALI_CTL_312_b.CS_MAP;
+    if (val == 0x01)
+    {
+        end_addr17 = R_DDRSS->DDR_MEMC_DENALI_CTL_304_b.CS_VAL_UPPER_0;
+    }
+    else
+    {
+        end_addr17 = R_DDRSS->DDR_MEMC_DENALI_CTL_306_b.CS_VAL_UPPER_1;
+    }
+
+    if (end_addr17 == 0xdfff)
+    {
+        addr_space = 33;
+    }
+    else if (end_addr17 == 0x6fff)
+    {
+        addr_space = 32;
+    }
+    else if (end_addr17 == 0x37ff)
+    {
+        addr_space = 31;
+    }
+    else if (end_addr17 == 0x1bff)
+    {
+        addr_space = 30;
+    }
+    else if (end_addr17 == 0x0dff)
+    {
+        addr_space = 29;
+    }
+    else
+    {
+        addr_space = 33;
+    }
+    bsp_prv_ddr_prog_all0(BPS_DDR_BASE_ADDR, addr_space);
+  #endif
+
+    bsp_prv_ddr_update_mc();
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_c
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_c (void)
+{
+    bsp_prv_ddr_phyinit_configuration();
+    bsp_prv_ddr_phyinit_pin_swizzling();
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_d2h_1d
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_d2h_1d (void)
+{
+    bsp_prv_ddr_phyinit_load_1d_image();
+    bsp_prv_ddr_phyinit_exec_1d_image();
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_d2h_2d
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_d2h_2d (void)
+{
+    bsp_prv_ddr_phyinit_load_2d_image();
+    bsp_prv_ddr_phyinit_exec_2d_image();
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_i
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_i (void)
+{
+    bsp_prv_ddr_phyinit_load_eng_image();
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_j
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_j (void)
+{
+    R_DDRSS->DDR_MEMC_DENALI_CTL_00_b.start = 1;
+    FSP_HARDWARE_REGISTER_WAIT((R_DDRSS->DDR_MEMC_DENALI_CTL_335_b.INT_STATUS_INIT & 0x02), 0x02);
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_mc
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_mc (void)
+{
+    uint32_t val, num_rank, num_byte, tctrl_delay, bl, x, tx_dqs_dly;
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
+
+    val      = R_DDRSS->DDR_MEMC_DENALI_CTL_312_b.CS_MAP;
+    num_rank = (val == 3) ? 2 : 1;
+
+    val = R_DDRSS->DDR_MEMC_DENALI_CTL_313_b.MEM_DP_REDUCTION;
+
+    num_byte    = (val == 1) ? 2 : 4;
+    val         = bsp_dwc_ddrphy_apb_rd(0x02002e);
+    tctrl_delay = ((val >> 1) + (val & 1)) + 8;
+
+    val = R_DDRSS->DDR_MEMC_DENALI_CTL_64_b.BSTLEN;
+    bl  = (1 << val);
+
+    x = 0;
+    if (num_byte > 0)
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x010020);
+        x   = (val > x) ? val : x;
+    }
+
+    if (num_byte > 1)
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x011020);
+        x   = (val > x) ? val : x;
+    }
+
+    if (num_byte > 2)
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x012020); x = (val > x) ? val : x;
+    }
+
+    if (num_byte > 3)
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x013020); x = (val > x) ? val : x;
+    }
+
+    val = 16 + tctrl_delay + (2 * x);
+    R_DDRSS->DDR_MEMC_DENALI_CTL_732_b.TDFI_PHY_RDLAT_F0 = (val & 0x7F);
+
+    x = 0;
+    if ((num_rank > 0) && (num_byte > 0))
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x0100d0);
+        x   = (val > x) ? val : x;
+        val = bsp_dwc_ddrphy_apb_rd(0x0101d0);
+        x   = (val > x) ? val : x;
+    }
+
+    if ((num_rank > 0) && (num_byte > 1))
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x0110d0);
+        x   = (val > x) ? val : x;
+        val = bsp_dwc_ddrphy_apb_rd(0x0111d0);
+        x   = (val > x) ? val : x;
+    }
+
+    if ((num_rank > 0) && (num_byte > 2))
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x0120d0);
+        x   = (val > x) ? val : x;
+        val = bsp_dwc_ddrphy_apb_rd(0x0121d0);
+        x   = (val > x) ? val : x;
+    }
+
+    if ((num_rank > 0) && (num_byte > 3))
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x0130d0);
+        x   = (val > x) ? val : x;
+        val = bsp_dwc_ddrphy_apb_rd(0x0131d0);
+        x   = (val > x) ? val : x;
+    }
+
+    if ((num_rank > 1) && (num_byte > 0))
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x0100d1);
+        x   = (val > x) ? val : x;
+        val = bsp_dwc_ddrphy_apb_rd(0x0101d1);
+        x   = (val > x) ? val : x;
+    }
+
+    if ((num_rank > 1) && (num_byte > 1))
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x0110d1);
+        x   = (val > x) ? val : x;
+        val = bsp_dwc_ddrphy_apb_rd(0x0111d1);
+        x   = (val > x) ? val : x;
+    }
+
+    if ((num_rank > 1) && (num_byte > 2))
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x0120d1);
+        x   = (val > x) ? val : x;
+        val = bsp_dwc_ddrphy_apb_rd(0x0121d1);
+        x   = (val > x) ? val : x;
+    }
+
+    if ((num_rank > 1) && (num_byte > 3))
+    {
+        val = bsp_dwc_ddrphy_apb_rd(0x0130d1);
+        x   = (val > x) ? val : x;
+        val = bsp_dwc_ddrphy_apb_rd(0x0131d1);
+        x   = (val > x) ? val : x;
+    }
+
+    tx_dqs_dly = ((x >> 6) & 0xf) + (((x >> 4) & 0x01) + ((x >> 3) & 0x1));
+    val        = tctrl_delay + (6 + (bl / 2)) + tx_dqs_dly;
+    R_DDRSS->DDR_MEMC_DENALI_CTL_761_b.TDFI_WRDATA = (val & 0xff);
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+}
+
+  #if (1 == BSP_CFG_DDR_ZERO_INITIALIZED_ENABLE)
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_prog_all0
+ *
+ * @param[in] start_addr    First argument
+ * @param[in] addr_space    Second argument
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_prog_all0 (uint64_t start_addr, uint32_t addr_space)
+{
+    uint32_t bak_lp_auto_entry_en;
+
+    R_DDRSS->DDR_MEMC_DENALI_CTL_232_b.ECC_DISABLE_W_UC_ERR = 1;
+
+    bak_lp_auto_entry_en = R_DDRSS->DDR_MEMC_DENALI_CTL_160_b.LP_AUTO_ENTRY_EN;
+
+    R_DDRSS->DDR_MEMC_DENALI_CTL_160_b.LP_AUTO_ENTRY_EN = 0x0;
+
+    R_DDRSS->DDR_MEMC_DENALI_CTL_221_b.BIST_START_ADDRESS   = (start_addr & 0xffffffff);
+    R_DDRSS->DDR_MEMC_DENALI_CTL_222_b.BIST_START_ADDRESS32 = ((start_addr >> 32) & 0x00000001);
+    R_DDRSS->DDR_MEMC_DENALI_CTL_219_b.ADDR_SPACE           = (addr_space & 0x3F);
+    R_DDRSS->DDR_MEMC_DENALI_CTL_220_b.BIST_DATA_CHECK      = 1;
+    R_DDRSS->DDR_MEMC_DENALI_CTL_225_b.BIST_TEST_MODE       = 0b100;
+    R_DDRSS->DDR_MEMC_DENALI_CTL_226_b.BIST_DATA_PATTERN0   = 0x00000000;
+    R_DDRSS->DDR_MEMC_DENALI_CTL_227_b.BIST_DATA_PATTERN1   = 0x00000000;
+    R_DDRSS->DDR_MEMC_DENALI_CTL_228_b.BIST_DATA_PATTERN2   = 0x00000000;
+    R_DDRSS->DDR_MEMC_DENALI_CTL_229_b.BIST_DATA_PATTERN3   = 0x00000000;
+
+    R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
+
+    R_DDRSS->DDR_MEMC_DENALI_CTL_219_b.BIST_GO = 1;
+    FSP_HARDWARE_REGISTER_WAIT((R_DDRSS->DDR_MEMC_DENALI_CTL_334_b.INT_STATUS_BIST & 0x01), 0x01);
+
+    R_DDRSS->DDR_MEMC_DENALI_CTL_219_b.BIST_GO      = 0;
+    R_DDRSS->DDR_MEMC_DENALI_CTL_343_b.INT_ACK_BIST = 1;
+    R_DDRSS->DDR_MEMC_DENALI_CTL_338_b.INT_ACK_ECC  = 0x000001CF;
+
+    FSP_HARDWARE_REGISTER_WAIT(R_DDRSS->DDR_MEMC_DENALI_CTL_334_b.INT_STATUS_BIST, 0);
+    FSP_HARDWARE_REGISTER_WAIT(R_DDRSS->DDR_MEMC_DENALI_CTL_329_b.INT_STATUS_ECC, 0);
+
+    R_DDRSS->DDR_MEMC_DENALI_CTL_160_b.LP_AUTO_ENTRY_EN     = (bak_lp_auto_entry_en & 0xf);
+    R_DDRSS->DDR_MEMC_DENALI_CTL_232_b.ECC_DISABLE_W_UC_ERR = 0;
+
+    R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
+}
+
+  #endif
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone
+ *
+ * @param[in] sel_train     First argument
+ **********************************************************************************************************************/
+void bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone (uint8_t sel_train)
+{
+    volatile uint32_t train_done = 0;
+    volatile uint32_t mail       = 0;
+    volatile uint32_t data       = 0;
+    volatile uint32_t timeout    = BSP_PRV_DDR_PHYINIT_TIMEOUT;
+
+    while (train_done == 0)
+    {
+        FSP_ASSERT_NOT_RETURN_VALUE(0 != timeout);
+
+        data = bsp_dwc_ddrphy_apb_rd(0x0d0004);
+
+        if ((data & 0x1) == 0)
+        {
+            mail = bsp_get_mail(0);
+            if ((mail == 0xff) || (mail == 0x07))
+            {
+                train_done = 1;
+            }
+        }
+
+        timeout--;
+    }
+
+    FSP_PARAMETER_NOT_USED(sel_train);
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_get_mail
+ *
+ * @param[in] mode_32bits   First argument
+ *
+ * @retval                  Returns the value of uint32_t
+ **********************************************************************************************************************/
+uint32_t bsp_get_mail (uint8_t mode_32bits)
+{
+    uint32_t mail = 0;
+
+    FSP_HARDWARE_REGISTER_WAIT((bsp_dwc_ddrphy_apb_rd(0x0d0004) & 0x1), 0);
+
+    mail = bsp_dwc_ddrphy_apb_rd(0x0d0032);
+
+    if (mode_32bits != 0)
+    {
+        mail = (bsp_dwc_ddrphy_apb_rd(0x0d0034) << 16) | mail;
+    }
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0031, 0x0000);
+
+    FSP_HARDWARE_REGISTER_WAIT((bsp_dwc_ddrphy_apb_rd(0x0d0004) & 0x1), 1);
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0031, 0x0001);
+
+    return mail;
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_dwc_ddrphy_cdd_int
+ *
+ * @param[in] val           First argument
+ *
+ * @return                  Returns the value of uint8_t
+ **********************************************************************************************************************/
+static int8_t bsp_prv_dwc_ddrphy_cdd_int (uint8_t val)
+{
+    return (int8_t) ((((val >> 7) & 0x1) == 1) ? -((0x7f ^ ((val >> 0) & 0x7f)) + 1) : ((val >> 0) & 0x7f));
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_dwc_ddrphy_cdd_abs
+ *
+ * @param[in] val           First argument
+ *
+ * @return                  Returns the value of uint8_t
+ **********************************************************************************************************************/
+static int8_t bsp_prv_dwc_ddrphy_cdd_abs (uint8_t val)
+{
+    return (uint8_t) ((((val >> 7) & 0x1) == 1) ? ((0x7f ^ ((val >> 0) & 0x7f)) + 1) : ((val >> 0) & 0x7f));
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_setup_mc
+ **********************************************************************************************************************/
+void bsp_prv_ddr_setup_mc (void)
+{
+    uint32_t i;
+
+    for (i = 0; i < param_mcinit_size; i++)
+    {
+        bsp_ddrtop_mc_apb_wr(param_mcinit[i][0], param_mcinit[i][1]);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_configuration
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_configuration (void)
+{
+    uint32_t i;
+
+    for (i = 0; i < param_phyinit_c_size; i++)
+    {
+        bsp_dwc_ddrphy_apb_wr(param_phyinit_c[i][0], param_phyinit_c[i][1]);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_pin_swizzling
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_pin_swizzling (void)
+{
+    uint32_t i;
+
+    for (i = 0; i < param_phyinit_swizzle_size; i++)
+    {
+        bsp_dwc_ddrphy_apb_wr(param_phyinit_swizzle[i][0], param_phyinit_swizzle[i][1]);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_load_1d_image
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_load_1d_image (void)
+{
+    uint32_t i;
+
+    bsp_dwc_ddrphy_apb_wr(0x020060, 0x2);
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
+
+    for (i = 0x0; i <= 0x3fff; i++)
+    {
+        bsp_dwc_ddrphy_apb_wr((uint32_t) (0x50000 + i), (uint32_t) (phyinit_fw_1d[i]));
+    }
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+
+    for (i = 0; i < param_phyinit_f_1d_0_size; i++)
+    {
+        bsp_dwc_ddrphy_apb_wr(param_phyinit_f_1d_0[i][0], param_phyinit_f_1d_0[i][1]);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_exec_1d_image
+ **********************************************************************************************************************/
+static void bsp_prv_ddr_phyinit_exec_1d_image (void)
+{
+    uint8_t  sel_train;
+    uint32_t val;
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
+    val       = bsp_dwc_ddrphy_apb_rd(0x01005f);
+    sel_train = ((val & 0x700) == 0x100) ? 0 : 2;
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+    bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x9);
+    bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x1);
+    bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x0);
+    bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone(sel_train);
+    bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x1);
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
+
+    uint32_t num_rank;
+    val      = R_DDRSS->DDR_MEMC_DENALI_CTL_312_b.CS_MAP;
+    num_rank = (val == 3) ? 2 : 1;
+
+    int8_t val0;
+    int8_t val1;
+    int8_t cdd_rr;
+    int8_t cdd_rw_abs;
+    int8_t cdd_ww;
+    int8_t cdd_ww_abs;
+
+    if (num_rank > 1)
+    {
+        val    = bsp_dwc_ddrphy_apb_rd(0x54013);
+        val0   = bsp_prv_dwc_ddrphy_cdd_int((val >> 0) & 0xff);
+        val1   = bsp_prv_dwc_ddrphy_cdd_int((val >> 8) & 0xff);
+        cdd_rr = val0;
+        cdd_rr = (val1 > cdd_rr) ? val1 : cdd_rr;
+
+        val        = bsp_dwc_ddrphy_apb_rd(0x54014);
+        val0       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
+        val1       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
+        cdd_rw_abs = val0;
+        cdd_rw_abs = (val1 > cdd_rw_abs) ? val1 : cdd_rw_abs;
+
+        val        = bsp_dwc_ddrphy_apb_rd(0x54015);
+        val0       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
+        val1       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
+        cdd_rw_abs = (val0 > cdd_rw_abs) ? val0 : cdd_rw_abs;
+        cdd_rw_abs = (val1 > cdd_rw_abs) ? val1 : cdd_rw_abs;
+
+        val        = bsp_dwc_ddrphy_apb_rd(0x54018);
+        val0       = bsp_prv_dwc_ddrphy_cdd_int((val >> 0) & 0xff);
+        val1       = bsp_prv_dwc_ddrphy_cdd_int((val >> 8) & 0xff);
+        cdd_ww     = val0;
+        cdd_ww     = (val1 > cdd_ww) ? val1 : cdd_ww;
+        val0       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
+        val1       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
+        cdd_ww_abs = val0;
+        cdd_ww_abs = (val1 > cdd_ww_abs) ? val1 : cdd_ww_abs;
+
+        val    = bsp_dwc_ddrphy_apb_rd(0x5402c);
+        val1   = bsp_prv_dwc_ddrphy_cdd_int((val >> 8) & 0xff);
+        cdd_rr = (val1 > cdd_rr) ? val1 : cdd_rr;
+
+        val        = bsp_dwc_ddrphy_apb_rd(0x5402d);
+        val0       = bsp_prv_dwc_ddrphy_cdd_int((val >> 0) & 0xff);
+        cdd_rr     = (val0 > cdd_rr) ? val0 : cdd_rr;
+        val1       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
+        cdd_rw_abs = (val1 > cdd_rw_abs) ? val1 : cdd_rw_abs;
+
+        val        = bsp_dwc_ddrphy_apb_rd(0x5402e);
+        val0       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
+        val1       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
+        cdd_rw_abs = (val0 > cdd_rw_abs) ? val0 : cdd_rw_abs;
+        cdd_rw_abs = (val1 > cdd_rw_abs) ? val1 : cdd_rw_abs;
+
+        val        = bsp_dwc_ddrphy_apb_rd(0x5402f);
+        val0       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
+        cdd_rw_abs = (val0 > cdd_rw_abs) ? val0 : cdd_rw_abs;
+
+        val        = bsp_dwc_ddrphy_apb_rd(0x54031);
+        val1       = bsp_prv_dwc_ddrphy_cdd_int((val >> 8) & 0xff);
+        cdd_ww     = (val1 > cdd_ww) ? val1 : cdd_ww;
+        val1       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
+        cdd_ww_abs = (val1 > cdd_ww_abs) ? val1 : cdd_ww_abs;
+
+        val        = bsp_dwc_ddrphy_apb_rd(0x54032);
+        val0       = bsp_prv_dwc_ddrphy_cdd_int((val >> 0) & 0xff);
+        cdd_ww     = (val0 > cdd_ww) ? val0 : cdd_ww;
+        val0       = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
+        cdd_ww_abs = (val0 > cdd_ww_abs) ? val0 : cdd_ww_abs;
+
+        if (cdd_rr > 0)
+        {
+            val  = R_DDRSS->DDR_MEMC_DENALI_CTL_376_b.R2R_DIFFCS_DLY_F0;
+            val += (uint32_t) ((uint8_t) cdd_rr);
+            R_DDRSS->DDR_MEMC_DENALI_CTL_376_b.R2R_DIFFCS_DLY_F0 = (val & 0x1F);
+        }
+
+        if (cdd_ww > 0)
+        {
+            val  = R_DDRSS->DDR_MEMC_DENALI_CTL_377_b.W2W_DIFFCS_DLY_F0;
+            val += (uint32_t) ((uint8_t) cdd_ww);
+            R_DDRSS->DDR_MEMC_DENALI_CTL_377_b.W2W_DIFFCS_DLY_F0 = (val & 0x1F);
+        }
+
+        val  = R_DDRSS->DDR_MEMC_DENALI_CTL_376_b.R2W_DIFFCS_DLY_F0;
+        val += (uint32_t) ((uint8_t) cdd_rw_abs);
+        R_DDRSS->DDR_MEMC_DENALI_CTL_376_b.R2W_DIFFCS_DLY_F0 = (val & 0x1F);
+
+        val  = R_DDRSS->DDR_MEMC_DENALI_CTL_377_b.W2R_DIFFCS_DLY_F0;
+        val += (uint32_t) ((uint8_t) cdd_ww_abs);
+        R_DDRSS->DDR_MEMC_DENALI_CTL_377_b.W2R_DIFFCS_DLY_F0 = (val & 0x1F);
+    }
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_load_2d_image
+ **********************************************************************************************************************/
+void bsp_prv_ddr_phyinit_load_2d_image (void)
+{
+    uint32_t i;
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
+    for (i = 0x0; i <= 0x3fff; i++)
+    {
+        bsp_dwc_ddrphy_apb_wr((uint32_t) (0x50000 + i), (uint32_t) (phyinit_fw_2d[i]));
+    }
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+
+    for (i = 0; i < param_phyinit_f_2d_0_size; i++)
+    {
+        bsp_dwc_ddrphy_apb_wr(param_phyinit_f_2d_0[i][0], param_phyinit_f_2d_0[i][1]);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_exec_2d_image
+ **********************************************************************************************************************/
+void bsp_prv_ddr_phyinit_exec_2d_image (void)
+{
+    uint8_t  sel_train;
+    uint32_t val;
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
+    val       = bsp_dwc_ddrphy_apb_rd(0x01005f);
+    sel_train = ((val & 0x700) == 0x100) ? 1 : 3;
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+    bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x9);
+    bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x1);
+    bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x0);
+    bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone(sel_train);
+    bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x1);
+
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
+    bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_phyinit_load_eng_image
+ **********************************************************************************************************************/
+void bsp_prv_ddr_phyinit_load_eng_image (void)
+{
+    uint32_t i;
+
+    for (i = 0; i < param_phyinit_i_size; i++)
+    {
+        bsp_dwc_ddrphy_apb_wr(param_phyinit_i[i][0], param_phyinit_i[i][1]);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_prv_ddr_update_mc
+ **********************************************************************************************************************/
+void bsp_prv_ddr_update_mc (void)
+{
+    uint32_t val;
+
+    R_DDRSS->DDR_MEMC_DENALI_CTL_327_b.INT_MASK_MASTER = 0;
+
+    val = R_DDRSS->DDR_MEMC_DENALI_CTL_167_b.PCPCS_PD_EN;
+    if (val == 1)
+    {
+        R_DDRSS->DDR_MEMC_DENALI_CTL_158_b.LPI_WAKEUP_EN = 0x1E;
+    }
+    else
+    {
+        R_DDRSS->DDR_MEMC_DENALI_CTL_158_b.LPI_WAKEUP_EN = 0x1F;
+    }
+}
+
+ #endif
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr.h
new file mode 100644
index 00000000..5ae85f50
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr.h
@@ -0,0 +1,105 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef __BSP_DDR_H__
+#define __BSP_DDR_H__
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_DDR_PHY_BASE                     ((uintptr_t) 0x88000000)
+
+#define BPS_DDR_BASE_ADDR                    (0x200000000)
+
+#define BSP_DDR_RETENTION_1D_SIZE            (283)
+#define BSP_DDR_RETENTION_2D_SIZE            (52)
+#define BSP_DDR_RETENTION_CONTROLLER_SIZE    (4)
+
+#define BSP_DDR_INIT_ENABLE                  (1)
+#define BSP_DDR_INIT_DISABLE                 (0)
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+extern void bsp_ddr_init(void);
+
+/*******************************************************************************************************************//**
+ * Executes bsp_mmio_write_32
+ *
+ * @param[in] addr          First argument
+ * @param[in] value         Second argument
+ **********************************************************************************************************************/
+__STATIC_INLINE void bsp_mmio_write_32 (uintptr_t addr, uint32_t value)
+{
+    *(volatile uint32_t *) addr = value;
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_mmio_read_32
+ *
+ * @param[in] addr          First argument
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t bsp_mmio_read_32 (uintptr_t addr)
+{
+    return *(volatile uint32_t *) addr;
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_ddrtop_mc_apb_wr
+ *
+ * @param[in] addr          First argument
+ * @param[in] data          Second argument
+ **********************************************************************************************************************/
+__STATIC_INLINE void bsp_ddrtop_mc_apb_wr (uint32_t addr, uint32_t data)
+{
+    bsp_mmio_write_32(R_DDRSS_BASE + (addr << 2), data);
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_dwc_ddrphy_apb_wr
+ *
+ * @param[in] addr          First argument
+ * @param[in] data          Second argument
+ **********************************************************************************************************************/
+__STATIC_INLINE void bsp_dwc_ddrphy_apb_wr (uint32_t addr, uint32_t data)
+{
+    bsp_mmio_write_32(BSP_DDR_PHY_BASE + (addr << 2), data);
+}
+
+/*******************************************************************************************************************//**
+ * Executes bsp_dwc_ddrphy_apb_rd
+ *
+ * @param[in] addr          First argument
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t bsp_dwc_ddrphy_apb_rd (uint32_t addr)
+{
+    return bsp_mmio_read_32(BSP_DDR_PHY_BASE + (addr << 2));
+}
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+#if ((BSP_CLOCKS_PLL2_NORMAL != BSP_CFG_PLL2) && (1 == BSP_CFG_DDR_INIT_ENABLE))
+ #error "When using DDR, please set to 'PLL2 is released from standby state'"
+#endif
+
+#endif                                 /*__BSP_DDR_H__*/
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.c
new file mode 100644
index 00000000..c2ed218a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.c
@@ -0,0 +1,32797 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include <stdio.h>
+#include "bsp_api.h"
+
+#if (BSP_FEATURE_DDR_SUPPORTED)
+ #if (1 == BSP_CFG_DDR_INIT_ENABLE)
+  #include "bsp_ddr_fw_param.h"
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+const uint32_t phyinit_fw_1d[] =
+{
+    0x0114,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x2069,
+    0x0040,
+    0x264a,
+    0x7000,
+    0x264a,
+    0x7000,
+    0x264a,
+    0x7000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x7054,
+    0x7ce0,
+    0x4300,
+    0x1101,
+    0x048c,
+    0x2242,
+    0x8042,
+    0x1b01,
+    0x0312,
+    0xf5fb,
+    0x7ee0,
+    0x78e0,
+    0xc4e1,
+    0x240a,
+    0x1f80,
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+    0x7d25,
+    0xc190,
+    0x79f4,
+    0xb1a0,
+    0x2642,
+    0x1801,
+    0x7a3b,
+    0x2284,
+    0x0001,
+    0xb9c4,
+    0x7a25,
+    0xc101,
+    0xc396,
+    0x7bf4,
+    0x7930,
+    0x230c,
+    0x9040,
+    0xc101,
+    0xb340,
+    0x21ca,
+    0x02c5,
+    0xc141,
+    0xc103,
+    0x7930,
+    0x7030,
+    0xc103,
+    0x21ca,
+    0x0005,
+    0xc143,
+    0x71e5,
+    0xc002,
+    0x7710,
+    0x06d4,
+    0xffe5,
+    0xc09c,
+    0xc003,
+    0x2454,
+    0x380b,
+    0x7910,
+    0xc001,
+    0x7810,
+    0x0841,
+    0x0065,
+    0xc289,
+    0x2216,
+    0x0782,
+    0x8a06,
+    0xdb40,
+    0x2454,
+    0x3b0b,
+    0x201a,
+    0x0f81,
+    0x0000,
+    0x1000,
+    0xc005,
+    0x7825,
+    0x781b,
+    0x41c3,
+    0x9000,
+    0x0000,
+    0x7825,
+    0xb060,
+    0x8a07,
+    0x201a,
+    0x0f82,
+    0x0000,
+    0x1000,
+    0xc005,
+    0x7845,
+    0x781b,
+    0x7825,
+    0xb060,
+    0x702c,
+    0xf016,
+    0xc09c,
+    0x6028,
+    0x0e23,
+    0x3021,
+    0x2456,
+    0x3d40,
+    0x6028,
+    0x23f4,
+    0x1042,
+    0x201a,
+    0x0f83,
+    0x0000,
+    0x1000,
+    0xc005,
+    0x7865,
+    0x781b,
+    0xb89c,
+    0xb89f,
+    0xb040,
+    0x7124,
+    0xc002,
+    0x09d9,
+    0x8004,
+    0x2640,
+    0x305e,
+    0x264c,
+    0xb080,
+    0x0628,
+    0xffe5,
+    0xc090,
+    0xc004,
+    0x41c3,
+    0x00a9,
+    0x0000,
+    0x08de,
+    0xffef,
+    0x2078,
+    0x0000,
+    0x0c2a,
+    0x0080,
+    0x0a8a,
+    0x0280,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x001b,
+    0xb8e0,
+    0x0b4c,
+    0x0102,
+    0x2400,
+    0x3f81,
+    0x0000,
+    0x0334,
+    0x0c4a,
+    0x0160,
+    0x700c,
+    0x2480,
+    0x320d,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0xb8e6,
+    0x781d,
+    0x781d,
+    0x781d,
+    0xb8c2,
+    0x742c,
+    0xf403,
+    0x7914,
+    0xf006,
+    0x7915,
+    0x0909,
+    0x0354,
+    0x762c,
+    0x7915,
+    0x7fe0,
+    0x6901,
+    0x42c3,
+    0x8000,
+    0x07c9,
+    0x8a20,
+    0x215f,
+    0x0c81,
+    0x6038,
+    0x8a21,
+    0x215f,
+    0x0641,
+    0x6119,
+    0x8903,
+    0xb8e6,
+    0x8902,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x001c,
+    0xb8c2,
+    0xf409,
+    0x7034,
+    0x41c3,
+    0x8000,
+    0x0640,
+    0xf209,
+    0xe108,
+    0xf007,
+    0x7034,
+    0x41c3,
+    0x8000,
+    0x0630,
+    0xf203,
+    0xe108,
+    0x6119,
+    0x7fe0,
+    0x8900,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1b5,
+    0xc254,
+    0x4528,
+    0x4200,
+    0x41c3,
+    0x00ef,
+    0x0001,
+    0x087e,
+    0x0060,
+    0x750c,
+    0x706f,
+    0xf035,
+    0x4261,
+    0xf009,
+    0xc014,
+    0x20f4,
+    0x0083,
+    0xc08e,
+    0x7834,
+    0xb060,
+    0x62ba,
+    0x7124,
+    0x09f3,
+    0x8294,
+    0x4183,
+    0x911c,
+    0x1446,
+    0x3103,
+    0x915f,
+    0xc053,
+    0x1448,
+    0x3101,
+    0x144a,
+    0x3100,
+    0x143a,
+    0x311f,
+    0x143c,
+    0x311e,
+    0x1440,
+    0x310f,
+    0x1442,
+    0x310e,
+    0x1444,
+    0x310c,
+    0xc346,
+    0xc313,
+    0xc048,
+    0xc147,
+    0xc242,
+    0x750c,
+    0x41c3,
+    0x00f0,
+    0x000b,
+    0xc445,
+    0xc644,
+    0xc743,
+    0x1c04,
+    0x3780,
+    0x1c00,
+    0x37c0,
+    0x0816,
+    0x0060,
+    0x4261,
+    0x7167,
+    0x232f,
+    0x16c8,
+    0x0b97,
+    0x9364,
+    0x702c,
+    0xc0b5,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0xc2e4,
+    0xc1a4,
+    0x4608,
+    0x700c,
+    0x0866,
+    0x0020,
+    0x702c,
+    0x702c,
+    0xd8ff,
+    0x754c,
+    0x726c,
+    0x1c0c,
+    0x30c1,
+    0x4528,
+    0xc142,
+    0xc141,
+    0x0926,
+    0x0020,
+    0xc140,
+    0x265f,
+    0x1100,
+    0x702c,
+    0xb98d,
+    0x734c,
+    0x78c5,
+    0x2084,
+    0x0f03,
+    0xc042,
+    0xd8ff,
+    0x746c,
+    0xc543,
+    0xc541,
+    0x0906,
+    0x0020,
+    0xc540,
+    0xd8ff,
+    0xd980,
+    0x754c,
+    0x726c,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x08f2,
+    0x0020,
+    0xc540,
+    0xc0a4,
+    0xc6c4,
+    0x78e0,
+    0x700c,
+    0x1e00,
+    0x7004,
+    0x9004,
+    0x0102,
+    0x7ee0,
+    0xc2e4,
+    0x4308,
+    0x70ad,
+    0x46cb,
+    0x9008,
+    0x01e4,
+    0x218c,
+    0x8fc3,
+    0xb6a0,
+    0xb6a1,
+    0xb6a2,
+    0xf224,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0004,
+    0x201a,
+    0x0f83,
+    0x0020,
+    0x0000,
+    0x2305,
+    0x0f80,
+    0x9004,
+    0x0040,
+    0xb020,
+    0x40c3,
+    0x8000,
+    0x07cd,
+    0x8881,
+    0x8800,
+    0xf00c,
+    0x201a,
+    0x0f82,
+    0x0000,
+    0x2000,
+    0x7104,
+    0x7a65,
+    0x2205,
+    0x0f82,
+    0x9002,
+    0x0040,
+    0xb220,
+    0x0ceb,
+    0x9005,
+    0x089a,
+    0x0280,
+    0x208a,
+    0x021a,
+    0x41c3,
+    0x900e,
+    0x002a,
+    0x1efc,
+    0x92c4,
+    0xb100,
+    0x40c3,
+    0x8000,
+    0x0446,
+    0xa8a0,
+    0x40c3,
+    0x0000,
+    0x0fac,
+    0xb101,
+    0x700c,
+    0xc6c4,
+    0x704c,
+    0x7210,
+    0x20e0,
+    0x07ca,
+    0x1600,
+    0x7101,
+    0x9008,
+    0x01d6,
+    0x09f3,
+    0x803e,
+    0x7144,
+    0x7ee0,
+    0xc2e2,
+    0x4328,
+    0x09f2,
+    0x00a0,
+    0x260a,
+    0x3000,
+    0x45cb,
+    0x9004,
+    0x00f2,
+    0x1d00,
+    0x1045,
+    0x1d00,
+    0x1005,
+    0x1e00,
+    0x7784,
+    0x9008,
+    0x01e2,
+    0x093e,
+    0x01a0,
+    0x760c,
+    0x0b17,
+    0x1030,
+    0x1d10,
+    0x1045,
+    0x40c3,
+    0x0000,
+    0x61a8,
+    0x0fb6,
+    0xffcf,
+    0x1d10,
+    0x1005,
+    0xc6c2,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a6,
+    0x260a,
+    0x3080,
+    0xc20b,
+    0xc345,
+    0xdb7f,
+    0xc040,
+    0x7b44,
+    0xd84b,
+    0x2338,
+    0x000f,
+    0x279a,
+    0x1002,
+    0xbae6,
+    0x208a,
+    0x003e,
+    0x234f,
+    0x004c,
+    0x27ca,
+    0x1001,
+    0xe4cf,
+    0x27ca,
+    0x1001,
+    0xe3d1,
+    0x27ca,
+    0x1001,
+    0xc000,
+    0x1600,
+    0x7083,
+    0x8000,
+    0x0446,
+    0x1400,
+    0x301f,
+    0x208c,
+    0x8fc3,
+    0xc00e,
+    0x2642,
+    0x304b,
+    0x27ca,
+    0x30c1,
+    0xc043,
+    0xc00d,
+    0xc044,
+    0xc00c,
+    0x0b51,
+    0x16b5,
+    0xc042,
+    0xdb50,
+    0xc341,
+    0xdb20,
+    0xd810,
+    0xde30,
+    0xdd60,
+    0x4378,
+    0x708d,
+    0x2025,
+    0x02c0,
+    0xf01a,
+    0xf01a,
+    0xf018,
+    0xf018,
+    0xf05c,
+    0xf019,
+    0xf014,
+    0xf016,
+    0xf045,
+    0xf048,
+    0xf010,
+    0xf010,
+    0xf047,
+    0xf03b,
+    0xf00e,
+    0xf00c,
+    0xf00a,
+    0xf00a,
+    0xf008,
+    0xf008,
+    0xf006,
+    0xf006,
+    0xf03f,
+    0xf034,
+    0xf005,
+    0xf0a8,
+    0x706c,
+    0xf003,
+    0xdb10,
+    0x264c,
+    0xb640,
+    0x014a,
+    0x002d,
+    0x4060,
+    0x726c,
+    0x748d,
+    0xc041,
+    0x4608,
+    0x4318,
+    0x4508,
+    0x4708,
+    0x2025,
+    0x0780,
+    0xf036,
+    0xf02c,
+    0xf02b,
+    0xf017,
+    0xf017,
+    0xf093,
+    0xf099,
+    0xf093,
+    0xf015,
+    0xf019,
+    0xf01c,
+    0xf091,
+    0xf00f,
+    0xf01b,
+    0xf00f,
+    0xf00d,
+    0xf089,
+    0xf087,
+    0xf087,
+    0xf085,
+    0xf085,
+    0xf018,
+    0xf017,
+    0xf013,
+    0xf008,
+    0xf006,
+    0xdb07,
+    0xf012,
+    0xc701,
+    0x758d,
+    0xf018,
+    0x758d,
+    0x47a9,
+    0xf014,
+    0x758d,
+    0x47c9,
+    0xf012,
+    0x718d,
+    0x476b,
+    0xf00e,
+    0x768d,
+    0xf00b,
+    0x708d,
+    0xf00a,
+    0x736c,
+    0x0e0d,
+    0x30d1,
+    0xc402,
+    0x249a,
+    0x1004,
+    0x7a85,
+    0x4468,
+    0x4708,
+    0x238a,
+    0x0ffd,
+    0x7b24,
+    0x783d,
+    0x2044,
+    0x0c0b,
+    0xe3b0,
+    0xdb58,
+    0x23cf,
+    0x11e1,
+    0x7b24,
+    0x2084,
+    0x0001,
+    0x2305,
+    0x02c3,
+    0x7885,
+    0x7b05,
+    0x783d,
+    0x239a,
+    0x0004,
+    0x781d,
+    0xc405,
+    0x781d,
+    0x2004,
+    0x0f80,
+    0x0000,
+    0x2000,
+    0x7c05,
+    0x7c65,
+    0x232f,
+    0x17c0,
+    0x43c3,
+    0x9008,
+    0x0000,
+    0x2305,
+    0x10c0,
+    0xb080,
+    0x4020,
+    0x209a,
+    0x0004,
+    0x7154,
+    0x2104,
+    0x0f81,
+    0x0000,
+    0xff00,
+    0x2004,
+    0x0f8c,
+    0x0000,
+    0x0f00,
+    0xc002,
+    0x201a,
+    0x0f80,
+    0x0000,
+    0x1000,
+    0x7c05,
+    0x40e1,
+    0x20cf,
+    0x01a1,
+    0x264c,
+    0xb180,
+    0x27ca,
+    0x1001,
+    0xc004,
+    0xb8c3,
+    0x7f05,
+    0x78ef,
+    0x7c05,
+    0x2354,
+    0x1800,
+    0x7865,
+    0xb080,
+    0x2355,
+    0x1800,
+    0x7865,
+    0xb040,
+    0xc003,
+    0x7905,
+    0x2355,
+    0x1c00,
+    0x7b05,
+    0xb320,
+    0xc000,
+    0x2740,
+    0x3041,
+    0x208c,
+    0x8fc3,
+    0xf405,
+    0x1e00,
+    0x7042,
+    0x8000,
+    0x0446,
+    0x782f,
+    0xc0a6,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x738d,
+    0xdf10,
+    0xf19e,
+    0x708d,
+    0xf19b,
+    0x718d,
+    0xf199,
+    0xdc20,
+    0xf197,
+    0x758d,
+    0xf195,
+    0x78e0,
+    0xc0f1,
+    0xc1a4,
+    0xc408,
+    0xc443,
+    0xc407,
+    0xc442,
+    0xc406,
+    0xc441,
+    0xc405,
+    0x0de2,
+    0xffef,
+    0xc440,
+    0xc0a4,
+    0xc0d1,
+    0x7ee0,
+    0x78e0,
+    0x41c3,
+    0x8000,
+    0x0446,
+    0x8920,
+    0x208c,
+    0x8fc3,
+    0x20ca,
+    0x0041,
+    0x1e00,
+    0x7004,
+    0x9008,
+    0x01e8,
+    0x7ee0,
+    0x78e0,
+    0x41c3,
+    0x8000,
+    0x0446,
+    0x8920,
+    0x208c,
+    0x8fc3,
+    0x20ca,
+    0x0041,
+    0x1e00,
+    0x7004,
+    0x9008,
+    0x01e6,
+    0x7ee0,
+    0x78e0,
+    0x41c3,
+    0x900e,
+    0x004c,
+    0x9160,
+    0x9141,
+    0x221a,
+    0x0f81,
+    0x0001,
+    0x0000,
+    0x7965,
+    0xe807,
+    0x231a,
+    0x0f80,
+    0x8000,
+    0x0000,
+    0x793d,
+    0xf008,
+    0x4040,
+    0xda0f,
+    0xba61,
+    0x0aff,
+    0x8031,
+    0x781d,
+    0x793b,
+    0x7825,
+    0x41c3,
+    0x900f,
+    0xfe4c,
+    0xda10,
+    0xb100,
+    0xba61,
+    0x0a01,
+    0x0031,
+    0x781d,
+    0x7fe0,
+    0xb101,
+    0x264a,
+    0x3000,
+    0xf010,
+    0x265a,
+    0x3c83,
+    0x607c,
+    0x235a,
+    0x1643,
+    0x7165,
+    0x639b,
+    0x633b,
+    0x8b80,
+    0x7c44,
+    0xab80,
+    0x0beb,
+    0x9094,
+    0x2640,
+    0x305e,
+    0x0ef9,
+    0xb0b4,
+    0x706d,
+    0x7ee0,
+    0xc0f1,
+    0xc1a4,
+    0x700c,
+    0x0c4a,
+    0xffef,
+    0xd9ff,
+    0x700c,
+    0xc043,
+    0xc042,
+    0xc041,
+    0xc040,
+    0xd8ff,
+    0xd988,
+    0x754c,
+    0x0d0a,
+    0xffef,
+    0xdb40,
+    0x700c,
+    0x0cc2,
+    0xffef,
+    0x712c,
+    0xc0a4,
+    0xc0d1,
+    0x7ee0,
+    0x7014,
+    0x20c0,
+    0x0fe9,
+    0x7fe0,
+    0x2884,
+    0x0001,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0x2482,
+    0x360a,
+    0x0b42,
+    0x0020,
+    0x712c,
+    0x1600,
+    0x709b,
+    0x8000,
+    0x0004,
+    0x0ab6,
+    0x0020,
+    0xc043,
+    0xc042,
+    0x2400,
+    0x3f80,
+    0x0000,
+    0x023c,
+    0x702c,
+    0x0932,
+    0x01a0,
+    0xda5a,
+    0x2456,
+    0x3c40,
+    0x0926,
+    0x01a0,
+    0xdab4,
+    0x0896,
+    0x0160,
+    0x208a,
+    0x0b04,
+    0x082e,
+    0x0160,
+    0xc041,
+    0x704c,
+    0x1e00,
+    0x7084,
+    0x9003,
+    0xfec4,
+    0xc002,
+    0x2079,
+    0x0000,
+    0xe008,
+    0xc040,
+    0xf012,
+    0x4300,
+    0x2244,
+    0x07c0,
+    0x6a21,
+    0x229a,
+    0x0008,
+    0xe806,
+    0xb861,
+    0x0801,
+    0x0031,
+    0x7b7b,
+    0x2205,
+    0x0f80,
+    0x9003,
+    0xe0c4,
+    0xb060,
+    0x4220,
+    0xc000,
+    0x0adf,
+    0x8024,
+    0x710c,
+    0xd880,
+    0xb88e,
+    0x1e00,
+    0x7004,
+    0x9003,
+    0xe004,
+    0x231a,
+    0x3f80,
+    0x0020,
+    0x0000,
+    0x2005,
+    0x0f81,
+    0x9003,
+    0xfe86,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0086,
+    0x9000,
+    0xb8a0,
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+    0x3f9b,
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+    0x0000,
+    0x0b1b,
+    0x1030,
+    0x750c,
+    0x41c3,
+    0x00f5,
+    0x0001,
+    0x0bda,
+    0xffef,
+    0x4260,
+    0xdd09,
+    0xdec0,
+    0xd8d0,
+    0xf00a,
+    0x41c3,
+    0x00f4,
+    0x0001,
+    0x0bc6,
+    0xffef,
+    0x4260,
+    0x72ad,
+    0xde8c,
+    0xd880,
+    0x60f8,
+    0x2005,
+    0x06c0,
+    0xc180,
+    0x0aaa,
+    0x0220,
+    0x724c,
+    0x700c,
+    0x722c,
+    0x0b1a,
+    0xffaf,
+    0xc280,
+    0xc080,
+    0x702c,
+    0x095a,
+    0x0160,
+    0xdab4,
+    0x66fe,
+    0x2605,
+    0x16c0,
+    0xc180,
+    0x0a8a,
+    0x0220,
+    0x42a1,
+    0x710c,
+    0x41a1,
+    0x0af6,
+    0xffaf,
+    0xc280,
+    0x2480,
+    0x3d02,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0xc3e2,
+    0x2482,
+    0x3d02,
+    0x4528,
+    0x4300,
+    0xc080,
+    0x702c,
+    0x0926,
+    0x0160,
+    0xdab4,
+    0x2354,
+    0x0d00,
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+    0x0a56,
+    0x0220,
+    0xda09,
+    0x750c,
+    0x41c3,
+    0x00f6,
+    0x0001,
+    0x0b4e,
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+    0x42a1,
+    0x700c,
+    0xd909,
+    0x0ab6,
+    0xffaf,
+    0xc280,
+    0xc7c2,
+    0x78e0,
+    0xc0f1,
+    0x2482,
+    0x3d02,
+    0xc080,
+    0x702c,
+    0x08ee,
+    0x0160,
+    0xdab4,
+    0x41c3,
+    0x00f8,
+    0x0000,
+    0x0b26,
+    0xffef,
+    0x750c,
+    0xd840,
+    0xc180,
+    0x0a12,
+    0x0220,
+    0xda09,
+    0x700c,
+    0xd909,
+    0x0a82,
+    0xffaf,
+    0xc280,
+    0x2480,
+    0x3d02,
+    0xc0d1,
+    0x7ee0,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x0012,
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+    0x20e0,
+    0x07c5,
+    0x7fe0,
+    0x1a09,
+    0x3002,
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+    0x44cb,
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+    0x00e4,
+    0x42c3,
+    0x8000,
+    0x07cb,
+    0x0835,
+    0x00b0,
+    0x716c,
+    0x7114,
+    0xd825,
+    0x46cb,
+    0x9004,
+    0x0030,
+    0xb89f,
+    0xf42a,
+    0x8a25,
+    0xaa23,
+    0x8aa4,
+    0x7b34,
+    0xaaa2,
+    0x96c0,
+    0x88e0,
+    0x78bb,
+    0xb4e0,
+    0xaa00,
+    0x0e5f,
+    0x1171,
+    0xaa61,
+    0xb4e1,
+    0xf02d,
+    0x700c,
+    0xb400,
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+    0x7081,
+    0x8000,
+    0x0058,
+    0xb421,
+    0x44cb,
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+    0x00f6,
+    0xb400,
+    0xb404,
+    0x1c06,
+    0x13c5,
+    0x8a27,
+    0xaa23,
+    0x8a06,
+    0x7b34,
+    0xaa02,
+    0x781b,
+    0xaa00,
+    0xd8ff,
+    0xaa61,
+    0x1cfe,
+    0x9004,
+    0xc4c6,
+    0x88a0,
+    0xb4a0,
+    0x8a27,
+    0xaa23,
+    0x8a04,
+    0x7b34,
+    0xaa02,
+    0x781b,
+    0xaa00,
+    0xaa61,
+    0x9600,
+    0x0829,
+    0x0151,
+    0xb4a1,
+    0xf015,
+    0x1c02,
+    0x1005,
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+    0xd8ff,
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+    0x03c5,
+    0x19f8,
+    0x8004,
+    0x19f6,
+    0x8005,
+    0x19fe,
+    0x8005,
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+    0x7080,
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+    0x0058,
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+    0x40c3,
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+    0x00f6,
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+    0x8044,
+    0xb023,
+    0xc4c6,
+    0x78e0,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a5,
+    0x4708,
+    0x40c3,
+    0x8000,
+    0x07c9,
+    0x88c0,
+    0x2753,
+    0x1040,
+    0x2078,
+    0x0080,
+    0xc042,
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+    0xc102,
+    0x0d0e,
+    0x00e0,
+    0x40c1,
+    0x45cb,
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+    0x0fbe,
+    0x00e0,
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+    0x40a1,
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+    0x1100,
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+    0x3080,
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+    0x61b9,
+    0x0a66,
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+    0xf00b,
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+    0xb964,
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+    0xb300,
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+    0x61b9,
+    0x09ae,
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+    0xf018,
+    0xc002,
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+    0x0000,
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+    0x1401,
+    0xc002,
+    0x7916,
+    0x61b8,
+    0x2032,
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+    0x204f,
+    0x0243,
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+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0x265f,
+    0x1c82,
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+    0x78ef,
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+    0x265f,
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+    0x40c3,
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+    0x8800,
+    0x2653,
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+    0xe81c,
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+    0x1080,
+    0x235f,
+    0x3c82,
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+    0x40c1,
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+    0x61b9,
+    0x704c,
+    0x0f16,
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+    0xc6c6,
+    0x78e0,
+    0xc2e2,
+    0x45cb,
+    0x9004,
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+    0x700c,
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+    0x7c9d,
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+    0x710d,
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+    0x01c6,
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+    0x9002,
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+    0xb7a0,
+    0xb8c9,
+    0xc6c6,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a7,
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+    0x1600,
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+    0xff6f,
+    0xd9ff,
+    0x710c,
+    0x4508,
+    0x2344,
+    0x37c0,
+    0xe805,
+    0xb861,
+    0x08ff,
+    0x8031,
+    0x7dbb,
+    0x70cd,
+    0x2553,
+    0x1040,
+    0xc045,
+    0xc042,
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+    0xda09,
+    0xdbff,
+    0xc643,
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+    0x096e,
+    0xff6f,
+    0xc640,
+    0x255a,
+    0x110d,
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+    0x734c,
+    0xdb22,
+    0x250f,
+    0x16c0,
+    0x7d0f,
+    0xd840,
+    0xc040,
+    0xd8ff,
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+    0x094e,
+    0xff6f,
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+    0x35c1,
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+    0xd8ff,
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+    0x746c,
+    0xc643,
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+    0x712c,
+    0x0942,
+    0x01c0,
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+    0x00e0,
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+    0x40c3,
+    0x0000,
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+    0x0a8a,
+    0x00e0,
+    0xd908,
+    0x700c,
+    0x0836,
+    0xff6f,
+    0xd9ff,
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+    0x0000,
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+    0xda0d,
+    0xdb20,
+    0xc643,
+    0xc542,
+    0xc641,
+    0x08f6,
+    0xff6f,
+    0xc740,
+    0x2756,
+    0x1800,
+    0xc040,
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+    0xd988,
+    0xda0d,
+    0xdb08,
+    0xc643,
+    0xc542,
+    0x08de,
+    0xff6f,
+    0xc641,
+    0x700c,
+    0x0896,
+    0xff6f,
+    0x712c,
+    0x46cb,
+    0x8000,
+    0x07cd,
+    0x8ea0,
+    0xf00e,
+    0x4063,
+    0x0b62,
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+    0x41e1,
+    0xe809,
+    0x40e1,
+    0x0eb6,
+    0x01a0,
+    0x702c,
+    0xc104,
+    0x79b4,
+    0xb100,
+    0x71a5,
+    0x8e41,
+    0x0ae7,
+    0x8365,
+    0x7faf,
+    0x8ee0,
+    0xf03c,
+    0x4063,
+    0x0b3e,
+    0x0020,
+    0x41a1,
+    0xe834,
+    0x40a1,
+    0x0e8e,
+    0x01a0,
+    0xd910,
+    0xc504,
+    0x209a,
+    0x0004,
+    0x42e1,
+    0x7df4,
+    0x9520,
+    0x7825,
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+    0x7810,
+    0x41c3,
+    0x00e1,
+    0x0001,
+    0x0ed6,
+    0xfeef,
+    0x2079,
+    0x0000,
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+    0x7100,
+    0x8000,
+    0x0006,
+    0x208c,
+    0x81c3,
+    0xf706,
+    0x710c,
+    0x1d00,
+    0x1045,
+    0xf00e,
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+    0x080f,
+    0x0095,
+    0x40c3,
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+    0x7000,
+    0x0001,
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+    0x41c3,
+    0x00e2,
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+    0x42e1,
+    0x8e41,
+    0x71e5,
+    0x0a8d,
+    0x83e5,
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+    0x0ac2,
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+    0xe88a,
+    0xc004,
+    0x0d0b,
+    0x103f,
+    0x78b4,
+    0x9021,
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+    0x8101,
+    0xb020,
+    0x8e41,
+    0x71a5,
+    0x0ae3,
+    0x8365,
+    0x79af,
+    0x8e60,
+    0xf016,
+    0xc106,
+    0x40c3,
+    0x9002,
+    0x015c,
+    0x211a,
+    0x0f81,
+    0x0020,
+    0x0000,
+    0x20c0,
+    0x00a2,
+    0x7905,
+    0x231a,
+    0x0f80,
+    0x0000,
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+    0x7905,
+    0xc004,
+    0x20f4,
+    0x00c0,
+    0x7164,
+    0xb100,
+    0x0ad7,
+    0x80e5,
+    0x7077,
+    0x700c,
+    0x0eee,
+    0xff2f,
+    0xd9ff,
+    0xc005,
+    0x702c,
+    0xda0a,
+    0xc042,
+    0xd8ff,
+    0x746c,
+    0x4528,
+    0xc143,
+    0xc141,
+    0x0fae,
+    0xff2f,
+    0xc140,
+    0xd8ff,
+    0x702c,
+    0x754c,
+    0x766c,
+    0x4608,
+    0xc043,
+    0xc542,
+    0xc541,
+    0x0f9a,
+    0xff2f,
+    0xc540,
+    0xc005,
+    0x702c,
+    0xda0e,
+    0xc042,
+    0xd8ff,
+    0x746c,
+    0xc543,
+    0xc541,
+    0x0f82,
+    0xff2f,
+    0xc540,
+    0xd8ff,
+    0xd980,
+    0x754c,
+    0x766c,
+    0xc643,
+    0xc542,
+    0xc541,
+    0x0f6e,
+    0xff2f,
+    0xc540,
+    0x700c,
+    0x0f26,
+    0xff2f,
+    0x712c,
+    0x0f7a,
+    0x0180,
+    0xc0a7,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0xc0f1,
+    0x4300,
+    0x4328,
+    0x4020,
+    0x0d06,
+    0xffef,
+    0x4160,
+    0xe8b8,
+    0x246f,
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+    0x208a,
+    0x0a46,
+    0x1e6c,
+    0x1004,
+    0x208a,
+    0x0a44,
+    0x1e6c,
+    0x1004,
+    0x1e6c,
+    0x1004,
+    0x40c3,
+    0x0000,
+    0x6000,
+    0x1e72,
+    0x935c,
+    0x1ed0,
+    0x9344,
+    0x1e72,
+    0x90dd,
+    0x0932,
+    0x00a0,
+    0x1ed0,
+    0x92c4,
+    0x1e72,
+    0x935c,
+    0x1e72,
+    0x92dc,
+    0xf046,
+    0x45cb,
+    0x9004,
+    0x0116,
+    0x1d08,
+    0x1094,
+    0x71cd,
+    0x1d02,
+    0x1055,
+    0x234a,
+    0x1200,
+    0x702c,
+    0xbf8b,
+    0x40c3,
+    0x000f,
+    0x4240,
+    0xb5c0,
+    0x1d6c,
+    0x12c4,
+    0x260a,
+    0x3040,
+    0x1df2,
+    0x9044,
+    0x1d66,
+    0x1044,
+    0x1d6c,
+    0x13c4,
+    0x0946,
+    0x00a0,
+    0x4318,
+    0xbf70,
+    0x202f,
+    0x06c2,
+    0x702c,
+    0x0936,
+    0x00a0,
+    0x1d6c,
+    0x13c4,
+    0x40c3,
+    0x0098,
+    0x9680,
+    0x702c,
+    0x0926,
+    0x00a0,
+    0x1d6c,
+    0x12c4,
+    0xd888,
+    0x1d6c,
+    0x1004,
+    0x40c3,
+    0x0000,
+    0x6000,
+    0x1d6c,
+    0x12c4,
+    0x1d6c,
+    0x1784,
+    0x1d72,
+    0x939c,
+    0x1dd0,
+    0x9384,
+    0x1d72,
+    0x90dd,
+    0x08a6,
+    0x00a0,
+    0x1dd0,
+    0x9784,
+    0x1d72,
+    0x939c,
+    0x1d72,
+    0x979c,
+    0x700c,
+    0x08ee,
+    0x00a0,
+    0xd920,
+    0x45cb,
+    0x9004,
+    0x01f0,
+    0xd820,
+    0x0886,
+    0x00a0,
+    0x1d00,
+    0x1005,
+    0xd820,
+    0x087e,
+    0x00a0,
+    0x1d00,
+    0x1045,
+    0x740c,
+    0x0872,
+    0x00a0,
+    0x1d00,
+    0x1005,
+    0x1d0a,
+    0x909d,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0x2088,
+    0x0901,
+    0x2089,
+    0x0906,
+    0x2080,
+    0x078e,
+    0x781d,
+    0x781d,
+    0x0009,
+    0x0020,
+    0x780f,
+    0x78e0,
+    0x080b,
+    0x08f4,
+    0x4100,
+    0xb97e,
+    0xb986,
+    0x7fe0,
+    0x782f,
+    0x78e0,
+    0xc3e6,
+    0xc1aa,
+    0x70cd,
+    0x40c3,
+    0x8000,
+    0x07c9,
+    0xa8cd,
+    0x40c3,
+    0x8000,
+    0x07c9,
+    0xa8cc,
+    0x40c3,
+    0x8000,
+    0x07c9,
+    0xa8cb,
+    0x40c3,
+    0x8000,
+    0x07c9,
+    0xa8ca,
+    0x41c3,
+    0x0089,
+    0x0000,
+    0x0da2,
+    0xff2f,
+    0xd80a,
+    0x0249,
+    0x0000,
+    0x2644,
+    0x17c1,
+    0xe906,
+    0xb961,
+    0x0901,
+    0x0031,
+    0x781b,
+    0x1be4,
+    0xb000,
+    0x021f,
+    0x0020,
+    0x702c,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x001b,
+    0x081f,
+    0x005e,
+    0xea07,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x007d,
+    0xf005,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x004a,
+    0x7610,
+    0xf4fa,
+    0x78cf,
+    0x1bf0,
+    0xb000,
+    0x13f0,
+    0xb001,
+    0x0c5a,
+    0xffaf,
+    0x4040,
+    0x4508,
+    0xea0b,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x0058,
+    0x13e4,
+    0xb000,
+    0x782b,
+    0x712c,
+    0xf40c,
+    0xf0e6,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x0025,
+    0x13e4,
+    0xb000,
+    0x782b,
+    0x702c,
+    0xf2de,
+    0x710c,
+    0xbac4,
+    0xea05,
+    0xba61,
+    0x0aff,
+    0x8031,
+    0x781b,
+    0x0a2a,
+    0xff6f,
+    0x780f,
+    0x13e4,
+    0xb000,
+    0x41a1,
+    0x1e00,
+    0x7043,
+    0x8000,
+    0x06e0,
+    0x780f,
+    0x0ae2,
+    0xff6f,
+    0x1be8,
+    0xb000,
+    0x702c,
+    0xd854,
+    0x1be0,
+    0xb040,
+    0x1e00,
+    0x7042,
+    0x8000,
+    0x06e0,
+    0x1bf8,
+    0xb700,
+    0x2402,
+    0x301c,
+    0xc082,
+    0x0bd2,
+    0xfeaf,
+    0x1bec,
+    0xb000,
+    0xf005,
+    0x1801,
+    0x0013,
+    0x7124,
+    0xe1d0,
+    0xf7fc,
+    0x70ed,
+    0xf048,
+    0x0eea,
+    0xffef,
+    0x78ef,
+    0x4508,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x07c9,
+    0x13e8,
+    0xb000,
+    0x42a1,
+    0x0e66,
+    0x0020,
+    0x1bf4,
+    0xb001,
+    0x0f0d,
+    0x18d1,
+    0x40c3,
+    0x0003,
+    0xd090,
+    0xf005,
+    0x40c3,
+    0x0001,
+    0x3880,
+    0x0f56,
+    0x0060,
+    0x702c,
+    0x0c96,
+    0xfeef,
+    0x13e8,
+    0xb000,
+    0x13f0,
+    0xb000,
+    0x2342,
+    0x3301,
+    0x0c8e,
+    0xfeaf,
+    0x724c,
+    0x13f4,
+    0xb000,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x07c9,
+    0x42a1,
+    0x2004,
+    0x0f80,
+    0x0000,
+    0x3f00,
+    0x1bfc,
+    0xb000,
+    0x1bf4,
+    0xb000,
+    0xc041,
+    0xc140,
+    0x740c,
+    0x41c3,
+    0x008a,
+    0x0004,
+    0x0c4e,
+    0xff2f,
+    0x43c1,
+    0x13fc,
+    0xb000,
+    0xe807,
+    0x13ec,
+    0xb000,
+    0x60f8,
+    0x1800,
+    0x0043,
+    0x71e5,
+    0xe7d0,
+    0x0772,
+    0xffee,
+    0x774c,
+    0x4548,
+    0x4748,
+    0x4140,
+    0xf023,
+    0x13ec,
+    0xb000,
+    0x1001,
+    0x0483,
+    0x1bec,
+    0xb000,
+    0xf211,
+    0x13e0,
+    0xb000,
+    0xe0d0,
+    0xf202,
+    0xeb12,
+    0x13e0,
+    0xb000,
+    0x4fb4,
+    0x7704,
+    0x4833,
+    0x7391,
+    0x27ca,
+    0x1009,
+    0x25ca,
+    0x1049,
+    0xf002,
+    0xeb04,
+    0x772c,
+    0xf004,
+    0x13e0,
+    0xb001,
+    0x13e0,
+    0xb000,
+    0x7104,
+    0x1be0,
+    0xb000,
+    0x13e0,
+    0xb000,
+    0xe0d1,
+    0x07b8,
+    0xffe5,
+    0x7734,
+    0x2139,
+    0x0083,
+    0x2538,
+    0x1080,
+    0x786b,
+    0xd850,
+    0x753c,
+    0x771c,
+    0x77b5,
+    0x700c,
+    0xf205,
+    0x4fb0,
+    0x207f,
+    0x0100,
+    0x1600,
+    0x7083,
+    0x8000,
+    0x07c9,
+    0x41c3,
+    0x008c,
+    0x0002,
+    0x0b5a,
+    0xfeaf,
+    0x42c1,
+    0x67b8,
+    0x2844,
+    0x0080,
+    0x0dc6,
+    0xffef,
+    0x780f,
+    0x1e00,
+    0x7043,
+    0x8000,
+    0x06e0,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x07c9,
+    0x2614,
+    0x1041,
+    0x2100,
+    0x0f81,
+    0x8000,
+    0x07c9,
+    0xa90a,
+    0x0cbe,
+    0xff6f,
+    0x13e8,
+    0xb000,
+    0x13f8,
+    0xb01c,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x07c9,
+    0x7124,
+    0x7a2f,
+    0x7154,
+    0x1e00,
+    0x7042,
+    0x8000,
+    0x07c9,
+    0x05de,
+    0xffce,
+    0x71c5,
+    0x72d5,
+    0x05be,
+    0xffe5,
+    0x710c,
+    0x40c3,
+    0x8000,
+    0x07c9,
+    0x180e,
+    0x0043,
+    0xc7c6,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1bd,
+    0xd925,
+    0xb99f,
+    0x8900,
+    0x1c3a,
+    0x3002,
+    0x1133,
+    0x0080,
+    0x1c3b,
+    0x3002,
+    0x40c3,
+    0x8000,
+    0x07c8,
+    0x8827,
+    0x88a0,
+    0xc16e,
+    0x8829,
+    0x1c39,
+    0x3042,
+    0x8828,
+    0x1c36,
+    0x3042,
+    0x882a,
+    0x710c,
+    0x1c37,
+    0x3042,
+    0x0e46,
+    0x0020,
+    0xc193,
+    0x702c,
+    0xc146,
+    0xf005,
+    0x7a34,
+    0x700c,
+    0xb200,
+    0x7124,
+    0x09fb,
+    0x82b4,
+    0xc298,
+    0xd90c,
+    0x2905,
+    0x0341,
+    0x740c,
+    0x7835,
+    0xc049,
+    0x040d,
+    0x0020,
+    0x700c,
+    0x03ff,
+    0x0020,
+    0x706f,
+    0xc005,
+    0x712c,
+    0x2044,
+    0x07c2,
+    0x4020,
+    0xc105,
+    0xea05,
+    0xba61,
+    0x0aff,
+    0x8031,
+    0x781b,
+    0xc047,
+    0x202f,
+    0x06c7,
+    0x0dca,
+    0x0020,
+    0x792f,
+    0x46cb,
+    0x8000,
+    0x06e0,
+    0xc048,
+    0x8e00,
+    0x7014,
+    0xf2f6,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0xb8e3,
+    0xf4f0,
+    0x0a86,
+    0xff4f,
+    0x70ed,
+    0x700c,
+    0xf07e,
+    0xc004,
+    0x2079,
+    0x0080,
+    0x7704,
+    0xc04a,
+    0xc004,
+    0xb882,
+    0x0815,
+    0x0131,
+    0xd9ff,
+    0x40c3,
+    0x0000,
+    0x0a00,
+    0x0aea,
+    0xfecf,
+    0x0baa,
+    0x0180,
+    0x8e01,
+    0x71ad,
+    0x702c,
+    0xc043,
+    0xc007,
+    0x704c,
+    0x726c,
+    0x780f,
+    0xc04b,
+    0xc042,
+    0xc00a,
+    0xc541,
+    0x780f,
+    0xc04c,
+    0x781d,
+    0x781d,
+    0x2044,
+    0x0800,
+    0x2045,
+    0x0180,
+    0xc040,
+    0x0b92,
+    0xfeef,
+    0xd8ff,
+    0x8e01,
+    0xc742,
+    0xc541,
+    0xc043,
+    0xc004,
+    0x702c,
+    0x704c,
+    0x726c,
+    0x2032,
+    0x0f80,
+    0x8000,
+    0x0448,
+    0xb8c5,
+    0xc040,
+    0x0b6e,
+    0xfeef,
+    0xd8ff,
+    0x8e01,
+    0x702c,
+    0x704c,
+    0xc043,
+    0xc00b,
+    0x726c,
+    0xc541,
+    0xc042,
+    0xc00c,
+    0x781d,
+    0x2044,
+    0x0800,
+    0x2045,
+    0x0580,
+    0xc040,
+    0x0b4a,
+    0xfeef,
+    0xd8ff,
+    0x8e01,
+    0x702c,
+    0x704c,
+    0xc043,
+    0xc00a,
+    0x726c,
+    0xc742,
+    0xb8c5,
+    0xc040,
+    0xd8ff,
+    0x0b32,
+    0xfeef,
+    0xc541,
+    0x40c3,
+    0x0000,
+    0x2710,
+    0x0cba,
+    0x0060,
+    0xd90a,
+    0x781d,
+    0x781d,
+    0x7704,
+    0x7d0f,
+    0xf8dd,
+    0xc742,
+    0xc741,
+    0xc740,
+    0x0b0e,
+    0xfeef,
+    0xc543,
+    0xf8da,
+    0xc543,
+    0xc742,
+    0xc741,
+    0x0b02,
+    0xfeef,
+    0xc740,
+    0xc004,
+    0xb863,
+    0x0811,
+    0x0095,
+    0x0a86,
+    0x0180,
+    0x700c,
+    0x0aae,
+    0xfeef,
+    0x712c,
+    0xc004,
+    0x7104,
+    0xc044,
+    0xc004,
+    0x7514,
+    0x0702,
+    0xffe5,
+    0xd9ff,
+    0x40c3,
+    0x0000,
+    0x0a00,
+    0x09fa,
+    0xfecf,
+    0x0aba,
+    0x0180,
+    0x8e01,
+    0x702c,
+    0x71ed,
+    0xc043,
+    0xd8ff,
+    0x704c,
+    0xdb18,
+    0x4528,
+    0xc142,
+    0xc741,
+    0x0ab6,
+    0xfeef,
+    0xc140,
+    0x0cfa,
+    0xfeef,
+    0xd8ff,
+    0x8e01,
+    0x702c,
+    0x704c,
+    0xc043,
+    0xc007,
+    0x726c,
+    0xc741,
+    0x780f,
+    0xc044,
+    0xc042,
+    0xd820,
+    0xc040,
+    0x0a92,
+    0xfeef,
+    0xd8ff,
+    0x8e01,
+    0x702c,
+    0x704c,
+    0xc043,
+    0xd8ff,
+    0x726c,
+    0xc542,
+    0xc741,
+    0x0a7a,
+    0xfeef,
+    0x1c00,
+    0x30c1,
+    0x8e01,
+    0x702c,
+    0x704c,
+    0xc043,
+    0xc004,
+    0x726c,
+    0xc741,
+    0xc042,
+    0xd8ff,
+    0x0a62,
+    0xfeef,
+    0x1c00,
+    0x3481,
+    0x8e01,
+    0x702c,
+    0x704c,
+    0xc043,
+    0xd8ff,
+    0x726c,
+    0xc542,
+    0xc741,
+    0x0a4a,
+    0xfeef,
+    0xc540,
+    0x8e01,
+    0x702c,
+    0x704c,
+    0xc043,
+    0xd8ff,
+    0xdb08,
+    0xc542,
+    0xc741,
+    0x0a32,
+    0xfeef,
+    0xc540,
+    0x0c5e,
+    0xfeef,
+    0xd8ff,
+    0x8e01,
+    0x702c,
+    0x704c,
+    0xc043,
+    0xd8ff,
+    0xdb18,
+    0xc542,
+    0xc741,
+    0x0a16,
+    0xfeef,
+    0xc540,
+    0x09a6,
+    0x0180,
+    0xf07f,
+    0x700c,
+    0x0932,
+    0xfeef,
+    0xd9ff,
+    0xc007,
+    0x70ad,
+    0x734c,
+    0x205a,
+    0x0101,
+    0xdb22,
+    0xc543,
+    0xc540,
+    0x7825,
+    0x7e0f,
+    0xd820,
+    0xc041,
+    0xd8ff,
+    0x702c,
+    0x0bf6,
+    0xfeef,
+    0xc642,
+    0xd828,
+    0xc041,
+    0xf88c,
+    0xc543,
+    0xc642,
+    0x0be6,
+    0xfeef,
+    0xc540,
+    0xf889,
+    0xc543,
+    0xc642,
+    0x1c04,
+    0x33c1,
+    0x0bd6,
+    0xfeef,
+    0xc040,
+    0xf885,
+    0xc543,
+    0xc642,
+    0x1c04,
+    0x3501,
+    0x0bc6,
+    0xfeef,
+    0xc540,
+    0xd8ff,
+    0xd980,
+    0x734c,
+    0xdb22,
+    0xc543,
+    0xc642,
+    0x1c04,
+    0x3081,
+    0x0bb2,
+    0xfeef,
+    0xc540,
+    0x700c,
+    0x095a,
+    0xfeef,
+    0x712c,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0004,
+    0xdae0,
+    0x201a,
+    0x0f81,
+    0x0020,
+    0x0000,
+    0x40c3,
+    0x9008,
+    0x0100,
+    0x2105,
+    0x0003,
+    0x7204,
+    0x7825,
+    0xb340,
+    0x1800,
+    0x0485,
+    0x700c,
+    0x0892,
+    0xfeef,
+    0xd9ff,
+    0x0bb2,
+    0xfeef,
+    0xd8ff,
+    0xc007,
+    0x702c,
+    0xb990,
+    0x780f,
+    0xc042,
+    0xd8ff,
+    0x714c,
+    0x746c,
+    0xc543,
+    0xc541,
+    0x094a,
+    0xfeef,
+    0xc540,
+    0xd90c,
+    0xd8ff,
+    0xb98d,
+    0x734c,
+    0x746c,
+    0xc543,
+    0xc642,
+    0xc541,
+    0x0936,
+    0xfeef,
+    0xc540,
+    0x0b5e,
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+    0x3f80,
+    0x0000,
+    0x02c8,
+    0x0e82,
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+    0xdaa0,
+    0x2400,
+    0x3f80,
+    0x0000,
+    0x0228,
+    0x0e76,
+    0x0020,
+    0xdaa0,
+    0x2456,
+    0x3c40,
+    0x0e6a,
+    0x0020,
+    0xdaa0,
+    0x2455,
+    0x3e80,
+    0x0e62,
+    0x0020,
+    0xdaa0,
+    0x261a,
+    0x1f8e,
+    0x0010,
+    0x0000,
+    0x4338,
+    0xf064,
+    0x702c,
+    0x0e4e,
+    0x0020,
+    0xda28,
+    0x2455,
+    0x3980,
+    0x0e42,
+    0x0020,
+    0xda28,
+    0xc09c,
+    0x0e3a,
+    0x0020,
+    0xda28,
+    0x2355,
+    0x3800,
+    0x78c5,
+    0x2455,
+    0x3c01,
+    0x0f66,
+    0x00e0,
+    0x724c,
+    0x2355,
+    0x38c0,
+    0x78c5,
+    0x0f5a,
+    0x00e0,
+    0x2455,
+    0x3981,
+    0x2355,
+    0x3d00,
+    0x78c5,
+    0x0f4e,
+    0x00e0,
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+    0x40c3,
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+    0x07c9,
+    0x1003,
+    0x008b,
+    0x40c3,
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+    0x07c9,
+    0x8862,
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+    0x3c00,
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+    0x00de,
+    0x0862,
+    0xfeef,
+    0x200a,
+    0x0780,
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+    0x2455,
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+    0x3f81,
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+    0x212f,
+    0x0782,
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+    0x3e81,
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+    0x1283,
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+    0x7b3d,
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+    0x1e00,
+    0x7043,
+    0x8000,
+    0x06e0,
+    0x206f,
+    0x0143,
+    0x8802,
+    0x1a00,
+    0x3103,
+    0x216f,
+    0x0143,
+    0xc041,
+    0x201a,
+    0x0f80,
+    0x0020,
+    0x0000,
+    0x91c7,
+    0xc040,
+    0x2005,
+    0x0f80,
+    0x9004,
+    0x0032,
+    0x9000,
+    0xc042,
+    0xc000,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0040,
+    0x9000,
+    0x0f7e,
+    0x00e0,
+    0xc046,
+    0xbee0,
+    0x02b8,
+    0x0001,
+    0xc000,
+    0x2005,
+    0x0f81,
+    0x9005,
+    0xe032,
+    0xc002,
+    0xb880,
+    0xb100,
+    0xc000,
+    0x2005,
+    0x0f80,
+    0x9003,
+    0xe090,
+    0x0cde,
+    0x0020,
+    0x1800,
+    0x0005,
+    0x256f,
+    0x1cc3,
+    0x8d00,
+    0xe886,
+    0x1e00,
+    0x7085,
+    0x9004,
+    0x00c0,
+    0x0ce6,
+    0xffcf,
+    0x0fc2,
+    0xff0f,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0x0841,
+    0x001e,
+    0x43c3,
+    0x9004,
+    0x0014,
+    0x9320,
+    0xca01,
+    0x080f,
+    0x01b0,
+    0x214f,
+    0x0082,
+    0x080d,
+    0x00d1,
+    0x2185,
+    0x0108,
+    0x4220,
+    0xb340,
+    0xd823,
+    0x42c3,
+    0x9005,
+    0xe034,
+    0xb200,
+    0x702c,
+    0x40c3,
+    0x9003,
+    0xe034,
+    0xb020,
+    0xb8b1,
+    0xb020,
+    0x0cde,
+    0x0020,
+    0xb221,
+    0x8d00,
+    0x7014,
+    0xf4ba,
+    0x206f,
+    0x0143,
+    0x8802,
+    0x1600,
+    0x708b,
+    0x8000,
+    0x0000,
+    0xc045,
+    0x201a,
+    0x0f80,
+    0x0020,
+    0x0000,
+    0xc044,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0086,
+    0x9000,
+    0xc043,
+    0x781d,
+    0x781d,
+    0x781d,
+    0x781d,
+    0xb8c2,
+    0x0827,
+    0x0090,
+    0x0835,
+    0x00f1,
+    0x238b,
+    0x903e,
+    0xce08,
+    0x45cb,
+    0x8000,
+    0x041c,
+    0x751c,
+    0x1a03,
+    0x3358,
+    0xce0e,
+    0x47cb,
+    0x8000,
+    0x0434,
+    0xf017,
+    0x45cb,
+    0x8000,
+    0x0418,
+    0x1a03,
+    0x3358,
+    0x47cb,
+    0x8000,
+    0x0430,
+    0xf010,
+    0x238b,
+    0x903e,
+    0xce05,
+    0x45cb,
+    0x8000,
+    0x0410,
+    0x751c,
+    0xce0b,
+    0x47cb,
+    0x8000,
+    0x0428,
+    0x1a03,
+    0x3358,
+    0x771c,
+    0x1a09,
+    0x33d8,
+    0x1600,
+    0x7082,
+    0x8000,
+    0x000c,
+    0x238b,
+    0x903e,
+    0x221a,
+    0x0f9b,
+    0x0001,
+    0x86a0,
+    0xf20a,
+    0x233c,
+    0x3f80,
+    0x00a6,
+    0x0400,
+    0x41c3,
+    0x0142,
+    0x0001,
+    0x081a,
+    0xfe0f,
+    0x212f,
+    0x06c2,
+    0x793d,
+    0x793d,
+    0x793d,
+    0xc005,
+    0x793d,
+    0x793d,
+    0x793d,
+    0xe895,
+    0xc003,
+    0x2044,
+    0x0080,
+    0x6512,
+    0x6710,
+    0x4910,
+    0x2048,
+    0x0000,
+    0x2805,
+    0x0080,
+    0x42c3,
+    0x9003,
+    0xfe80,
+    0x780f,
+    0x2089,
+    0x0fc1,
+    0xb200,
+    0x1ae0,
+    0x8004,
+    0xc501,
+    0x2b05,
+    0x3f80,
+    0x0000,
+    0xfa00,
+    0x251a,
+    0x1f8d,
+    0x0010,
+    0x0000,
+    0x7104,
+    0x0821,
+    0x01fe,
+    0x744c,
+    0x2100,
+    0x0f80,
+    0xffff,
+    0x793c,
+    0x208c,
+    0x8d47,
+    0x704c,
+    0xf685,
+    0x2885,
+    0x0d07,
+    0xf002,
+    0x710c,
+    0x780f,
+    0x2089,
+    0x0fc1,
+    0x205a,
+    0x0200,
+    0xc104,
+    0x7a05,
+    0x1600,
+    0x7100,
+    0x9004,
+    0x0164,
+    0x2105,
+    0x0f81,
+    0x9005,
+    0xe164,
+    0xb8c1,
+    0x7845,
+    0xb100,
+    0xc000,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0086,
+    0x0e46,
+    0x00e0,
+    0x90e0,
+    0x0dd2,
+    0x00e0,
+    0x40a1,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x001f,
+    0xc001,
+    0x2111,
+    0x8000,
+    0xc000,
+    0x27cf,
+    0x1021,
+    0x2005,
+    0x0f80,
+    0x9003,
+    0xfe86,
+    0xb0e0,
+    0x0b1e,
+    0x0000,
+    0x0b52,
+    0xff8f,
+    0x081a,
+    0xfe8f,
+    0x0c5a,
+    0xff4f,
+    0xca04,
+    0x704c,
+    0x708d,
+    0xf038,
+    0x245a,
+    0x149e,
+    0x2600,
+    0x3f83,
+    0x8000,
+    0x06e0,
+    0xb341,
+    0xf02d,
+    0x241a,
+    0x1f81,
+    0x0000,
+    0x1000,
+    0x79a5,
+    0x793b,
+    0x2105,
+    0x0f81,
+    0x9002,
+    0x0140,
+    0x9120,
+    0x7f2f,
+    0x0d11,
+    0x13e1,
+    0x716d,
+    0x8b22,
+    0x210f,
+    0x0341,
+    0xab22,
+    0xf018,
+    0x8b23,
+    0x2744,
+    0x17db,
+    0x7124,
+    0xab23,
+    0x792f,
+    0x2614,
+    0x3041,
+    0x2100,
+    0x0f81,
+    0x8000,
+    0x06e0,
+    0x4769,
+    0xa9a3,
+    0x0b0f,
+    0x3010,
+    0x2342,
+    0x305b,
+    0x0bfd,
+    0xb031,
+    0x7ffb,
+    0xa9e2,
+    0x71a5,
+    0x0dad,
+    0x9214,
+    0x7185,
+    0x0c95,
+    0x9024,
+    0x70ad,
+    0x0e0b,
+    0x133f,
+    0x710c,
+    0xf009,
+    0x0ace,
+    0x0000,
+    0x0ffe,
+    0xfdcf,
+    0x0aaa,
+    0x0020,
+    0xd80d,
+    0x700c,
+    0x0cd2,
+    0x0180,
+    0x0b2a,
+    0xfe4f,
+    0x1e00,
+    0x7003,
+    0x8000,
+    0x06e0,
+    0x0a92,
+    0x0020,
+    0x700c,
+    0xca04,
+    0x706d,
+    0x704c,
+    0xf01a,
+    0x702c,
+    0xf015,
+    0x221a,
+    0x0f83,
+    0x0000,
+    0x1000,
+    0x2400,
+    0x1f8d,
+    0x8000,
+    0x07f0,
+    0x7185,
+    0x7b25,
+    0x7b7b,
+    0x2305,
+    0x0f83,
+    0x9002,
+    0x0140,
+    0x93e0,
+    0xade0,
+    0xb320,
+    0x7124,
+    0x09dd,
+    0x8214,
+    0x7144,
+    0x0ad1,
+    0x8024,
+    0x2316,
+    0x108c,
+    0x0bae,
+    0xfeaf,
+    0x710c,
+    0x0e13,
+    0x10be,
+    0x700c,
+    0x0896,
+    0x0100,
+    0x0a3a,
+    0x0020,
+    0x720c,
+    0x2644,
+    0x908d,
+    0xf208,
+    0x0886,
+    0x0120,
+    0x710c,
+    0x0a2a,
+    0x0020,
+    0x710c,
+    0x0e19,
+    0x123e,
+    0x206f,
+    0x0143,
+    0x8802,
+    0xe888,
+    0x086e,
+    0x0120,
+    0x730c,
+    0x0a12,
+    0x0020,
+    0xd80a,
+    0x2644,
+    0x920f,
+    0xf207,
+    0x085e,
+    0x0120,
+    0x750c,
+    0x09fe,
+    0x0020,
+    0xd8fd,
+    0xed08,
+    0x084e,
+    0x0120,
+    0x720c,
+    0x09f2,
+    0x0020,
+    0xd8fe,
+    0x0e11,
+    0x113e,
+    0x760c,
+    0x083e,
+    0x0100,
+    0x09e2,
+    0x0020,
+    0x740c,
+    0x0e15,
+    0x1051,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0019,
+    0xe884,
+    0x0826,
+    0x0120,
+    0xd80d,
+    0xef07,
+    0x081e,
+    0x0120,
+    0x740c,
+    0x09be,
+    0x0020,
+    0x730c,
+    0x0e23,
+    0x127f,
+    0x206f,
+    0x0143,
+    0x8802,
+    0x201a,
+    0x0f80,
+    0x0020,
+    0x0000,
+    0x2005,
+    0x0f81,
+    0x9003,
+    0xe040,
+    0xc006,
+    0xb100,
+    0xf040,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0x71ad,
+    0x46cb,
+    0x8000,
+    0x07c9,
+    0xb8e2,
+    0x25ca,
+    0x13e1,
+    0x700c,
+    0xae00,
+    0x780f,
+    0x084f,
+    0x0095,
+    0xe81d,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0058,
+    0x7014,
+    0x710c,
+    0xf213,
+    0x0d9e,
+    0xfe4f,
+    0x8e00,
+    0x7104,
+    0x0ada,
+    0xfeaf,
+    0x780f,
+    0x09e6,
+    0xfe4f,
+    0x0cea,
+    0xfe6f,
+    0x1e01,
+    0x1003,
+    0x4100,
+    0x0af2,
+    0x0120,
+    0x40a1,
+    0x8e00,
+    0x7104,
+    0xf1e1,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0025,
+    0x7014,
+    0x700c,
+    0xf5e7,
+    0xf1f7,
+    0x0aaa,
+    0xfeaf,
+    0x730c,
+    0xca09,
+    0xe885,
+    0x0922,
+    0xfeaf,
+    0xc001,
+    0x0922,
+    0x0020,
+    0xd809,
+    0xca09,
+    0xe837,
+    0xd925,
+    0xb99f,
+    0x8900,
+    0x1133,
+    0x008f,
+    0x70cd,
+    0x7f05,
+    0xf022,
+    0x2644,
+    0x17c1,
+    0xe905,
+    0xb961,
+    0x09ff,
+    0x8031,
+    0x781b,
+    0x78eb,
+    0xf217,
+    0x40c1,
+    0x0d02,
+    0xfe6f,
+    0x712c,
+    0xc101,
+    0x4508,
+    0x7bcf,
+    0x710c,
+    0x42a1,
+    0x091e,
+    0xfeaf,
+    0x4378,
+    0xc101,
+    0x700c,
+    0x42a1,
+    0x0912,
+    0xfeaf,
+    0x4363,
+    0x4163,
+    0x09be,
+    0xfeaf,
+    0x40a1,
+    0x71c5,
+    0x0ec1,
+    0x90b4,
+    0x710c,
+    0x08be,
+    0xfeaf,
+    0xc001,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0000,
+    0xb8e5,
+    0x09dc,
+    0xfe82,
+    0x0b16,
+    0xff8f,
+    0xca04,
+    0x706f,
+    0x704c,
+    0xf017,
+    0x706c,
+    0xf012,
+    0x221a,
+    0x0f81,
+    0x0000,
+    0x1000,
+    0x7965,
+    0x793b,
+    0x2105,
+    0x0f8c,
+    0x9002,
+    0x0140,
+    0x2332,
+    0x1f81,
+    0x8000,
+    0x07f0,
+    0x7164,
+    0x7165,
+    0xb420,
+    0x0bdf,
+    0x8214,
+    0x7144,
+    0x0ad7,
+    0x8024,
+    0x2316,
+    0x308b,
+    0xc000,
+    0x2005,
+    0x0f81,
+    0x9005,
+    0xe032,
+    0xc002,
+    0xb100,
+    0x09c2,
+    0xfeaf,
+    0x700c,
+    0x09f6,
+    0x00c0,
+    0x0d26,
+    0x0120,
+    0xd807,
+    0x23ab,
+    0x30c4,
+    0x7fff,
+    0xf000,
+    0xc2e2,
+    0x45cb,
+    0x9004,
+    0x0004,
+    0x9500,
+    0xb8a1,
+    0xb500,
+    0x0f06,
+    0xffaf,
+    0x740c,
+    0xd81f,
+    0x0efe,
+    0xffaf,
+    0x1df6,
+    0x105d,
+    0xc6c2,
+    0xc2e2,
+    0x0ef2,
+    0xffaf,
+    0xd81f,
+    0x45cb,
+    0x9004,
+    0x01f0,
+    0x740c,
+    0x0ee2,
+    0xffaf,
+    0x1d00,
+    0x1005,
+    0x150a,
+    0x9700,
+    0xb881,
+    0x1d0a,
+    0x901c,
+    0xc6c2,
+    0xc0f1,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x0012,
+    0x218c,
+    0x8203,
+    0x0cc4,
+    0x010e,
+    0x080e,
+    0x0000,
+    0xc0d1,
+    0x7ee0,
+    0x78e0,
+    0xc2e2,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0x081b,
+    0x003e,
+    0xd80a,
+    0x45cb,
+    0x9005,
+    0xe036,
+    0x0e9e,
+    0xffaf,
+    0x1d00,
+    0x1045,
+    0x1d00,
+    0x1005,
+    0xc6c2,
+    0x40c3,
+    0x9004,
+    0x00f2,
+    0x1800,
+    0x0045,
+    0x7fe0,
+    0x1800,
+    0x0005,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0x2482,
+    0x3402,
+    0xc34e,
+    0x4608,
+    0xc00e,
+    0xdc08,
+    0xc24f,
+    0xbc61,
+    0x0c01,
+    0x1031,
+    0x781d,
+    0x2044,
+    0x004d,
+    0x40a1,
+    0x0ad6,
+    0xff2f,
+    0xc151,
+    0xc00e,
+    0x42c3,
+    0x9003,
+    0xe0c4,
+    0x70b5,
+    0xb8c3,
+    0xb200,
+    0xd9f0,
+    0x208a,
+    0x0c07,
+    0x20ca,
+    0x0041,
+    0xc10e,
+    0xba8b,
+    0xc39a,
+    0x7904,
+    0xb220,
+    0xc09a,
+    0x702c,
+    0x0986,
+    0xffef,
+    0xda28,
+    0xc00e,
+    0x714c,
+    0xc346,
+    0x780f,
+    0x20b8,
+    0x0fc3,
+    0xc06d,
+    0xc00e,
+    0x2644,
+    0x17c3,
+    0x4338,
+    0xc04c,
+    0x40c3,
+    0x0000,
+    0x0f00,
+    0xc04b,
+    0xd820,
+    0xc053,
+    0xc04a,
+    0xc011,
+    0xc10f,
+    0x1c24,
+    0x3003,
+    0xc048,
+    0x14b0,
+    0x3000,
+    0x1c1c,
+    0x3103,
+    0xc643,
+    0xc050,
+    0xc045,
+    0x14ac,
+    0x3000,
+    0xc052,
+    0xc044,
+    0xc00f,
+    0x1c25,
+    0x3002,
+    0x4040,
+    0xeb06,
+    0xbb61,
+    0x0b01,
+    0x0031,
+    0x781b,
+    0x205a,
+    0x0100,
+    0x200f,
+    0x0380,
+    0x0b6a,
+    0x0020,
+    0x780f,
+    0xc00f,
+    0xb863,
+    0x0849,
+    0x0135,
+    0xc058,
+    0x41c3,
+    0x9008,
+    0x01ea,
+    0x9100,
+    0x2004,
+    0x0f82,
+    0x0000,
+    0xc0ff,
+    0x2004,
+    0x0f80,
+    0x0000,
+    0x3f00,
+    0x2080,
+    0x0010,
+    0x7845,
+    0xb100,
+    0x1e00,
+    0x76c4,
+    0x900f,
+    0xe022,
+    0x1600,
+    0x7100,
+    0x9004,
+    0x00ee,
+    0x2050,
+    0x0141,
+    0xb885,
+    0x1e00,
+    0x7044,
+    0x9005,
+    0xe0ee,
+    0xc053,
+    0x14a8,
+    0x3000,
+    0xc059,
+    0x14a4,
+    0x3000,
+    0xc057,
+    0x0b26,
+    0x0060,
+    0xc083,
+    0x40c3,
+    0x8000,
+    0x07cb,
+    0x8861,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x07cb,
+    0xf00f,
+    0xc212,
+    0x7a34,
+    0x9200,
+    0xe88a,
+    0xc09a,
+    0x20f5,
+    0x0040,
+    0x080d,
+    0x0833,
+    0x2042,
+    0x0800,
+    0xb200,
+    0x7124,
+    0x0be9,
+    0x8045,
+    0xc00f,
+    0x7704,
+    0x0837,
+    0x00b5,
+    0x70b5,
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+    0xdab4,
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+    0x18fe,
+    0x8044,
+    0x40c1,
+    0x0b92,
+    0x00a0,
+    0x702c,
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+    0x712c,
+    0x08a2,
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+    0x0e4a,
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+    0x0fc7,
+    0x46cb,
+    0x9003,
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+    0x0ff1,
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+    0x1a09,
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+    0x1a22,
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+    0xc6c6,
+    0x78e0,
+    0x43c3,
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+    0x7a1b,
+    0x2205,
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+    0x0164,
+    0xb220,
+    0x0beb,
+    0x8305,
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+    0x0006,
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+    0x2d85,
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+    0x7aaf,
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+    0x00b0,
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+    0xd80a,
+    0x40c3,
+    0x8000,
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+    0xa8a0,
+    0xc6c2,
+    0x78e0,
+    0xc2e6,
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+    0x15c3,
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+    0x4508,
+    0xea17,
+    0x0f32,
+    0xfeaf,
+    0x4040,
+    0x4708,
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+    0xfd2f,
+    0x700c,
+    0x40e1,
+    0x209a,
+    0x0001,
+    0x7f05,
+    0x78bb,
+    0x2005,
+    0x0f80,
+    0x9003,
+    0xfe92,
+    0xb0e0,
+    0x16ff,
+    0x9082,
+    0xea18,
+    0x0f02,
+    0xfeaf,
+    0x4040,
+    0x228c,
+    0x8fc3,
+    0xf209,
+    0xe888,
+    0x41c3,
+    0x00d8,
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+    0xfd2f,
+    0x700c,
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+    0x209a,
+    0x0001,
+    0x79bb,
+    0x2105,
+    0x0f81,
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+    0xfe9a,
+    0xb100,
+    0xc6c6,
+    0x78e0,
+    0xc0f1,
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+    0x7082,
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+    0xea1a,
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+    0x0a30,
+    0x720c,
+    0x228c,
+    0x8c03,
+    0xf20c,
+    0xe2f8,
+    0xf404,
+    0x710c,
+    0xf009,
+    0x41c3,
+    0x00d9,
+    0x0001,
+    0x0916,
+    0xfd2f,
+    0x700c,
+    0x700c,
+    0x205f,
+    0x0401,
+    0x7825,
+    0x1e00,
+    0x7004,
+    0x9005,
+    0xe0a0,
+    0xc0d1,
+    0x7ee0,
+    0xc0e6,
+    0x4328,
+    0x70ed,
+    0x41c3,
+    0x9003,
+    0xff64,
+    0xb1e0,
+    0x1904,
+    0x0045,
+    0x42c3,
+    0x8000,
+    0x07cd,
+    0x8a21,
+    0x8ac0,
+    0xf039,
+    0x228c,
+    0x8fc3,
+    0xf418,
+    0x261a,
+    0x1f83,
+    0x0000,
+    0x2000,
+    0x42c3,
+    0x9002,
+    0x1f64,
+    0x2305,
+    0x008c,
+    0x7444,
+    0x7a65,
+    0xb400,
+    0x0b51,
+    0x123f,
+    0xb2e0,
+    0x42c3,
+    0x9003,
+    0xf164,
+    0xb2e0,
+    0x1a04,
+    0x0045,
+    0xf020,
+    0x260a,
+    0x32c0,
+    0x708d,
+    0xf016,
+    0xf753,
+    0x4381,
+    0x261a,
+    0x1f82,
+    0x0000,
+    0x2000,
+    0x239a,
+    0x0008,
+    0x7b45,
+    0x42c3,
+    0x9002,
+    0x0164,
+    0x2305,
+    0x008d,
+    0x7444,
+    0x7b45,
+    0xb500,
+    0x1b00,
+    0x0005,
+    0x7185,
+    0x0e0d,
+    0x3010,
+    0x0cd5,
+    0x9274,
+    0x262f,
+    0xb782,
+    0x71c5,
+    0x0993,
+    0x83a5,
+    0x222f,
+    0x02c7,
+    0xc4c6,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a1,
+    0x40c3,
+    0x9004,
+    0x0030,
+    0x10b4,
+    0x0501,
+    0x1600,
+    0x708f,
+    0x8000,
+    0x0025,
+    0x090d,
+    0x0171,
+    0xb0e0,
+    0xb0e1,
+    0xf007,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x0058,
+    0xb021,
+    0x0f6f,
+    0x1030,
+    0x716f,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0032,
+    0x2744,
+    0x108d,
+    0xb8e3,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x07cf,
+    0x23ca,
+    0x30a1,
+    0x2744,
+    0x104e,
+    0xc040,
+    0xf01b,
+    0x209a,
+    0x0004,
+    0x2753,
+    0x1041,
+    0x7905,
+    0x40a1,
+    0xf848,
+    0xc000,
+    0xf841,
+    0xee07,
+    0xc000,
+    0x4263,
+    0x790f,
+    0x0aaa,
+    0xfdef,
+    0x700c,
+    0xed08,
+    0xc000,
+    0x4263,
+    0x790f,
+    0x0a9e,
+    0xfdef,
+    0x710c,
+    0xc000,
+    0x7104,
+    0xc040,
+    0x40c3,
+    0x8000,
+    0x07cf,
+    0x8821,
+    0xc000,
+    0x09c3,
+    0x8025,
+    0x40c1,
+    0x1600,
+    0x708d,
+    0x8000,
+    0x0058,
+    0x0d6f,
+    0x1030,
+    0x716f,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0065,
+    0x2544,
+    0x108e,
+    0xb8e3,
+    0x40c3,
+    0x8000,
+    0x07cf,
+    0x8802,
+    0x23ca,
+    0x30a1,
+    0x2544,
+    0x104f,
+    0xc040,
+    0xf01b,
+    0x209a,
+    0x0004,
+    0x2553,
+    0x1041,
+    0x7905,
+    0x40c1,
+    0xf82b,
+    0xc000,
+    0xf824,
+    0xef07,
+    0xc000,
+    0x4263,
+    0x790f,
+    0x0a36,
+    0xfdef,
+    0x700c,
+    0xee08,
+    0xc000,
+    0x4263,
+    0x790f,
+    0x0a2a,
+    0xfdef,
+    0x710c,
+    0xc000,
+    0x7104,
+    0xc040,
+    0x40c3,
+    0x8000,
+    0x07cf,
+    0x8823,
+    0xc000,
+    0x09c3,
+    0x8025,
+    0x40e1,
+    0x1600,
+    0x708e,
+    0x8000,
+    0x0004,
+    0x0aae,
+    0xfe0f,
+    0x0ab6,
+    0xfe2f,
+    0x4508,
+    0x4100,
+    0x0cfe,
+    0xffef,
+    0x40a1,
+    0x261a,
+    0x1f8c,
+    0x0020,
+    0x0000,
+    0x43c3,
+    0x9008,
+    0x01ea,
+    0x9300,
+    0x45cb,
+    0x9012,
+    0x0402,
+    0x2405,
+    0x1342,
+    0x2004,
+    0x0f81,
+    0x0000,
+    0x3f00,
+    0xb220,
+    0x6d44,
+    0x7a85,
+    0x2196,
+    0x0006,
+    0xb220,
+    0x9321,
+    0x6d02,
+    0x7885,
+    0xb9c5,
+    0xb020,
+    0x7487,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x201a,
+    0x0f80,
+    0x0000,
+    0x2000,
+    0x2005,
+    0x0f81,
+    0x9002,
+    0x0154,
+    0x9100,
+    0x7845,
+    0xb100,
+    0x7ee0,
+    0x209a,
+    0x0004,
+    0x7905,
+    0x4063,
+    0x209a,
+    0x0010,
+    0x2105,
+    0x0002,
+    0x7ee0,
+    0x78e0,
+    0xc2e2,
+    0xc1a4,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x06e1,
+    0x702c,
+    0x754c,
+    0xc043,
+    0xd8ff,
+    0xdb08,
+    0x4528,
+    0xc142,
+    0xc141,
+    0x0852,
+    0xfd6f,
+    0xc140,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x06e1,
+    0xd910,
+    0x754c,
+    0xc043,
+    0xd8ff,
+    0xdb0c,
+    0xc542,
+    0xc541,
+    0x0836,
+    0xfd6f,
+    0xc540,
+    0xd8ff,
+    0xd980,
+    0x754c,
+    0x726c,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x0822,
+    0xfd6f,
+    0xc540,
+    0xc0a4,
+    0xc6c2,
+    0x78e0,
+    0xc2e4,
+    0xc1a4,
+    0x70ad,
+    0xd8ff,
+    0x702c,
+    0x754c,
+    0x736c,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x0802,
+    0xfd6f,
+    0xc540,
+    0x46cb,
+    0x8000,
+    0x06e1,
+    0x8e00,
+    0x0825,
+    0x00b4,
+    0x702c,
+    0x7104,
+    0x781d,
+    0xb862,
+    0x780f,
+    0xc043,
+    0xd8ff,
+    0x754c,
+    0x726c,
+    0xc542,
+    0xc541,
+    0x0fda,
+    0xfd2f,
+    0xc540,
+    0x8e00,
+    0xc043,
+    0xd8ff,
+    0x702c,
+    0x754c,
+    0xdb08,
+    0xc542,
+    0xc541,
+    0x0fc6,
+    0xfd2f,
+    0xc540,
+    0x8e00,
+    0xd908,
+    0x754c,
+    0xc043,
+    0xd8ff,
+    0xdb0c,
+    0xc542,
+    0xc541,
+    0x0fae,
+    0xfd2f,
+    0xc540,
+    0xc0a4,
+    0xc6c4,
+    0x78e0,
+    0x42c3,
+    0x9004,
+    0x0110,
+    0x9200,
+    0x204f,
+    0x0101,
+    0xb8a4,
+    0xb220,
+    0x7fe0,
+    0xb200,
+    0xc0e6,
+    0x215f,
+    0x0483,
+    0x44cb,
+    0x8000,
+    0x06e2,
+    0x638d,
+    0x6479,
+    0x89c1,
+    0x7d04,
+    0x702c,
+    0xf009,
+    0x629a,
+    0x8ae3,
+    0x0809,
+    0x03ce,
+    0x8a42,
+    0x7d45,
+    0x7124,
+    0x09f5,
+    0x83a4,
+    0x2314,
+    0x0042,
+    0x40a1,
+    0xc4c6,
+    0x78e0,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0x2482,
+    0x3d09,
+    0xc044,
+    0x206f,
+    0x0243,
+    0x8820,
+    0x1054,
+    0x0083,
+    0x1021,
+    0x008d,
+    0x10fd,
+    0x808e,
+    0x1209,
+    0x308b,
+    0x1208,
+    0x308f,
+    0xc149,
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+    0x3f80,
+    0x0000,
+    0x010c,
+    0x702c,
+    0x0b9a,
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+    0x0b92,
+    0xfeef,
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+    0xbee2,
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+    0x03e1,
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+    0x7ba5,
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+    0xc34d,
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+    0xb882,
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+    0x2078,
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+    0xc04a,
+    0xc004,
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+    0x2644,
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+    0xc10a,
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+    0xb861,
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+    0x7b7b,
+    0x0d16,
+    0xfd6f,
+    0x40c1,
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+    0xc00d,
+    0x7b0b,
+    0x0266,
+    0x0001,
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+    0xb880,
+    0x2078,
+    0x0141,
+    0xc00c,
+    0x7825,
+    0xc050,
+    0x0215,
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+    0xc110,
+    0x704c,
+    0x0976,
+    0xfeaf,
+    0xc045,
+    0x7014,
+    0x01f6,
+    0x0021,
+    0x70ed,
+    0x40c3,
+    0x8000,
+    0x07c9,
+    0xa8c1,
+    0xc004,
+    0xb863,
+    0x7214,
+    0x0c54,
+    0xfd45,
+    0x4508,
+    0xf79a,
+    0xc004,
+    0x0831,
+    0x01b1,
+    0x70ad,
+    0x1600,
+    0x7080,
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+    0x265a,
+    0x1641,
+    0x205f,
+    0x0c80,
+    0x6038,
+    0x2032,
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+    0x7dbd,
+    0x7dbd,
+    0x7dbd,
+    0x7dbd,
+    0x7dbd,
+    0x7dbd,
+    0x7dbd,
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+    0x3e00,
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+    0x0f8e,
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+    0xc308,
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+    0x0dcf,
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+    0x40c3,
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+    0xed0d,
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+    0x7114,
+    0x05e8,
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+    0x083e,
+    0xfdaf,
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+    0xca09,
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+    0x0fa2,
+    0xfd6f,
+    0xc007,
+    0xf00d,
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+    0x0134,
+    0x7bcf,
+    0xc00a,
+    0xc109,
+    0xc207,
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+    0x2052,
+    0x0000,
+    0x71c5,
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+    0x0000,
+    0xb8e5,
+    0x0fa0,
+    0xfd42,
+    0x1e00,
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+    0x3d09,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1b0,
+    0xc04f,
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+    0x7080,
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+    0xc046,
+    0x098e,
+    0xfe2f,
+    0x4020,
+    0x40c3,
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+    0x0e76,
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+    0x1ffc,
+    0x9004,
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+    0x781b,
+    0xae02,
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+    0xae03,
+    0x70ad,
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+    0x716f,
+    0xc043,
+    0xf0cd,
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+    0x781b,
+    0x1e01,
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+    0x790b,
+    0xc042,
+    0xf2b0,
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+    0x06c7,
+    0x41c3,
+    0x8000,
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+    0x706c,
+    0x0c06,
+    0xfe6f,
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+    0xc002,
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+    0x0f80,
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+    0xb0a0,
+    0x206f,
+    0x0243,
+    0x10fd,
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+    0x015f,
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+    0xf00e,
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+    0x7865,
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+    0x9002,
+    0x0040,
+    0xb0a0,
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+    0x8085,
+    0xf00e,
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+    0x0f81,
+    0x0000,
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+    0xc005,
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+    0x781b,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0040,
+    0xb0a0,
+    0x0b9a,
+    0xfeaf,
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+    0x0a32,
+    0xfd2f,
+    0x7810,
+    0x8e04,
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+    0xc047,
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+    0x0f81,
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+    0x2105,
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+    0xc003,
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+    0x2049,
+    0x07c1,
+    0xb220,
+    0x206f,
+    0x0243,
+    0x10fd,
+    0x809e,
+    0x0e39,
+    0x315f,
+    0x8e65,
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+    0xf00f,
+    0x221a,
+    0x0f8c,
+    0x0000,
+    0x1000,
+    0xc005,
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+    0x7885,
+    0x781b,
+    0x2005,
+    0x0f80,
+    0x9002,
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+    0xb020,
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+    0x0243,
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+    0xc001,
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+    0x0f82,
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+    0xc005,
+    0x7845,
+    0x781b,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0040,
+    0xb020,
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+    0xc041,
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+    0xc00d,
+    0x7110,
+    0x05ac,
+    0xffce,
+    0x0e17,
+    0x315e,
+    0xc00c,
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+    0xae03,
+    0xc00a,
+    0xae02,
+    0x700c,
+    0x1fa7,
+    0x101c,
+    0x1fa8,
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+    0xc0b0,
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+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0x208c,
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+    0x0821,
+    0x01d1,
+    0x41c3,
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+    0x1900,
+    0x0045,
+    0xf006,
+    0x41c3,
+    0x9004,
+    0x0238,
+    0x1900,
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+    0x3081,
+    0xe903,
+    0x0019,
+    0x0000,
+    0x41c3,
+    0x9018,
+    0x0064,
+    0xb100,
+    0x0059,
+    0x0020,
+    0x1902,
+    0x0005,
+    0x78e0,
+    0xc0f1,
+    0x1209,
+    0x3081,
+    0xe90a,
+    0x1222,
+    0x3702,
+    0x228c,
+    0x8010,
+    0xf793,
+    0x0aae,
+    0xfd4f,
+    0xf019,
+    0x41c3,
+    0x9018,
+    0x0064,
+    0xda10,
+    0xb100,
+    0xba61,
+    0x0aff,
+    0x8031,
+    0x781d,
+    0xb102,
+    0x0822,
+    0x0020,
+    0x1902,
+    0x0005,
+    0xf009,
+    0x2615,
+    0x7081,
+    0x8000,
+    0x08e8,
+    0xa100,
+    0x6a01,
+    0x1a22,
+    0x301c,
+    0xc0d1,
+    0x7ee0,
+    0x78e0,
+    0x41c3,
+    0x9018,
+    0x0008,
+    0x9100,
+    0x08ff,
+    0x801f,
+    0x195e,
+    0x0045,
+    0x9100,
+    0x0801,
+    0x001e,
+    0x7ee0,
+    0xc2e6,
+    0x4708,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0x083b,
+    0x013f,
+    0x4528,
+    0xca09,
+    0x7ef0,
+    0xe80a,
+    0xcc22,
+    0x218a,
+    0x0010,
+    0x7902,
+    0x6e02,
+    0x7030,
+    0x0a34,
+    0xfd4a,
+    0x0f36,
+    0xffef,
+    0xd808,
+    0x0f72,
+    0xffef,
+    0x40e1,
+    0x70ed,
+    0xf007,
+    0x0f66,
+    0xffef,
+    0x1504,
+    0x1400,
+    0x71e5,
+    0x0ff9,
+    0x9384,
+    0xc6c6,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0x2482,
+    0x3009,
+    0xc352,
+    0xc245,
+    0xc153,
+    0x4318,
+    0x206f,
+    0x0243,
+    0x88a0,
+    0x10fc,
+    0x808e,
+    0x1600,
+    0x710f,
+    0x9008,
+    0x01e0,
+    0x4063,
+    0x0e32,
+    0xfd2f,
+    0x702c,
+    0xc050,
+    0x40c3,
+    0x0000,
+    0xffff,
+    0x4100,
+    0x4200,
+    0x0a4a,
+    0xfdef,
+    0x4300,
+    0x40c3,
+    0x0000,
+    0xff7f,
+    0x78e4,
+    0x1e00,
+    0x7004,
+    0x9009,
+    0xe1e0,
+    0x2456,
+    0x3f00,
+    0x41c3,
+    0x8000,
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+    0x0d2e,
+    0xfcaf,
+    0xda60,
+    0x2456,
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+    0x0b0e,
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+    0x4060,
+    0x2344,
+    0x37cf,
+    0xef05,
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+    0x0fff,
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+    0x781b,
+    0x7edd,
+    0x205a,
+    0x0100,
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+    0x200f,
+    0x06c2,
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+    0x7edd,
+    0xe807,
+    0xd8ff,
+    0x1e00,
+    0x7004,
+    0x9003,
+    0xf0c4,
+    0xf016,
+    0x700c,
+    0xf011,
+    0x2044,
+    0x07c1,
+    0xe906,
+    0xb961,
+    0x0901,
+    0x0031,
+    0x7c9b,
+    0x6821,
+    0x209a,
+    0x0008,
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+    0x0f80,
+    0x9003,
+    0xe0c4,
+    0xb080,
+    0x4020,
+    0x08e3,
+    0x8234,
+    0x4468,
+    0x1497,
+    0x3600,
+    0x251a,
+    0x1f8d,
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+    0x0000,
+    0x7bc6,
+    0xc04d,
+    0x1496,
+    0x3600,
+    0x702c,
+    0xc34c,
+    0xc04e,
+    0x1495,
+    0x3600,
+    0xc551,
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+    0x784f,
+    0x0dc6,
+    0xfeef,
+    0x704c,
+    0x700c,
+    0xc04a,
+    0xf00c,
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+    0x7a7b,
+    0x7034,
+    0x2456,
+    0x3e01,
+    0x22ce,
+    0x0021,
+    0x6038,
+    0xa840,
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+    0x08ed,
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+    0x2044,
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+    0x40c3,
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+    0x250a,
+    0x1780,
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+    0x706c,
+    0xf044,
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+    0x0c01,
+    0xc011,
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+    0x261a,
+    0x1f81,
+    0x0000,
+    0x1000,
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+    0x4060,
+    0x209a,
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+    0xb891,
+    0xb89c,
+    0xb89f,
+    0x90e0,
+    0xc005,
+    0x2378,
+    0x0201,
+    0x2079,
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+    0x807e,
+    0xf429,
+    0x78fd,
+    0x781d,
+    0x781d,
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+    0x781d,
+    0xbfc4,
+    0x702c,
+    0xe807,
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+    0x219a,
+    0x0010,
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+    0x265f,
+    0x148b,
+    0x2400,
+    0x3f82,
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+    0xb220,
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+    0x0000,
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+    0x0813,
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+    0x03c1,
+    0xc096,
+    0x7061,
+    0x7874,
+    0xb020,
+    0x7164,
+    0x0b7b,
+    0x8254,
+    0x71a5,
+    0x7eaf,
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+    0x1e00,
+    0x1f84,
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+    0x40c3,
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+    0x7dcf,
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+    0x0f80,
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+    0x0a11,
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+    0x2242,
+    0x104a,
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+    0x9031,
+    0x781b,
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+    0x11e2,
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+    0xc143,
+    0x1c04,
+    0x3081,
+    0x0d66,
+    0xfcef,
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+    0xc0a4,
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+    0xc6c6,
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+    0xb6c8,
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+    0x1c0c,
+    0x36c0,
+    0xc742,
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+    0x1c0c,
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+    0x0a22,
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+    0xbfc1,
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+    0x0a0e,
+    0xfcef,
+    0x1c00,
+    0x3041,
+    0x0c36,
+    0xfcef,
+    0xd8ff,
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+    0x754c,
+    0x746c,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x09f2,
+    0xfcef,
+    0xc540,
+    0xc0a4,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0xd8ff,
+    0xd90c,
+    0x714c,
+    0xdb08,
+    0x7ee0,
+    0x78e0,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a8,
+    0xc145,
+    0x4318,
+    0x700c,
+    0xd9ff,
+    0xc346,
+    0x08ee,
+    0xfcef,
+    0xc244,
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+    0xda14,
+    0xc041,
+    0x0f26,
+    0xfe2f,
+    0x2455,
+    0x3bc0,
+    0x0c4a,
+    0x0000,
+    0x40a1,
+    0x08e2,
+    0xfd6f,
+    0x2455,
+    0x3bc1,
+    0x710c,
+    0x2544,
+    0x17ce,
+    0x4318,
+    0xee05,
+    0xbe61,
+    0x0eff,
+    0x9031,
+    0x781b,
+    0x205a,
+    0x0100,
+    0x200f,
+    0x0340,
+    0x0846,
+    0xfdaf,
+    0x780f,
+    0x702c,
+    0x40c3,
+    0x9003,
+    0xfe64,
+    0x1e00,
+    0x7044,
+    0x9003,
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+    0x1882,
+    0x005c,
+    0x208a,
+    0x0808,
+    0x1e00,
+    0x7004,
+    0x9003,
+    0xe004,
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+    0x76c4,
+    0x900f,
+    0xe0c0,
+    0x1e00,
+    0x7044,
+    0x9003,
+    0xfe64,
+    0xf010,
+    0x6941,
+    0x219a,
+    0x0008,
+    0x4363,
+    0xe806,
+    0xb861,
+    0x0801,
+    0x0031,
+    0x7b7b,
+    0x2105,
+    0x0f80,
+    0x9003,
+    0xe0c4,
+    0xb060,
+    0x4140,
+    0x09e3,
+    0x8234,
+    0x2144,
+    0x07c0,
+    0x47cb,
+    0x0000,
+    0xaaaa,
+    0xd80f,
+    0x41e1,
+    0x42e1,
+    0x43e1,
+    0x0c62,
+    0xfd6f,
+    0xc740,
+    0xd80f,
+    0x0826,
+    0xfcef,
+    0xd90f,
+    0x40c3,
+    0x0000,
+    0x0f00,
+    0x0e52,
+    0xff2f,
+    0x712c,
+    0x45cb,
+    0x9003,
+    0xe174,
+    0x700c,
+    0xb500,
+    0x208a,
+    0x0fc7,
+    0xb501,
+    0xd830,
+    0x1d58,
+    0x9f9c,
+    0x0000,
+    0xffff,
+    0x1d5e,
+    0x96dc,
+    0x09a2,
+    0xfcaf,
+    0x1d57,
+    0x96dc,
+    0xd80f,
+    0x702c,
+    0x43c3,
+    0x0000,
+    0xffff,
+    0x1c00,
+    0x3f80,
+    0x0000,
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+    0x0c0e,
+    0xfd6f,
+    0x704c,
+    0x740c,
+    0x097e,
+    0xfcaf,
+    0x712c,
+    0xd80f,
+    0x41e1,
+    0x42e1,
+    0x43e1,
+    0x0bfa,
+    0xfd6f,
+    0xc740,
+    0x700c,
+    0xb500,
+    0xb501,
+    0xd820,
+    0x1d58,
+    0x901c,
+    0x208a,
+    0x0844,
+    0x1d5e,
+    0x96dc,
+    0x1d57,
+    0x901c,
+    0x40c3,
+    0x0000,
+    0x0f00,
+    0x0dda,
+    0xff2f,
+    0x732c,
+    0xd830,
+    0x0946,
+    0xfcaf,
+    0x712c,
+    0xc001,
+    0x1600,
+    0x7082,
+    0x8000,
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+    0x201a,
+    0x0f80,
+    0x0010,
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+    0xc044,
+    0x40c3,
+    0x8000,
+    0x07cd,
+    0x8821,
+    0xf021,
+    0x700c,
+    0x2016,
+    0x0083,
+    0xf019,
+    0x209a,
+    0x0008,
+    0x221a,
+    0x0f8c,
+    0x0000,
+    0x2000,
+    0x7885,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0064,
+    0x9000,
+    0x7c1d,
+    0x7c9d,
+    0x7c9d,
+    0x7c9d,
+    0x7c9d,
+    0xb8c4,
+    0x7c05,
+    0xc087,
+    0x7874,
+    0xb080,
+    0x7164,
+    0x40c1,
+    0x08d3,
+    0x8234,
+    0x68c1,
+    0x7144,
+    0x09c3,
+    0x80a5,
+    0x208a,
+    0x0fc7,
+    0xb500,
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+    0x208a,
+    0x07d0,
+    0x1d58,
+    0x9f9c,
+    0x0000,
+    0xffff,
+    0x1d5e,
+    0x905c,
+    0x1d57,
+    0x905c,
+    0x1e00,
+    0x7004,
+    0x9003,
+    0xfe64,
+    0xd830,
+    0x08b2,
+    0xfcaf,
+    0x4628,
+    0xd80f,
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+    0x43c3,
+    0x0000,
+    0xffff,
+    0x1c00,
+    0x3f80,
+    0x0000,
+    0xffff,
+    0x0b22,
+    0xfd6f,
+    0x704c,
+    0x740c,
+    0x0892,
+    0xfcaf,
+    0x712c,
+    0xd80f,
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+    0xb500,
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+    0x40c3,
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+    0xd820,
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+    0x1d57,
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+    0x1600,
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+    0x781b,
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+    0x2253,
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+    0xd90f,
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+    0x41c3,
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+    0x780f,
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+    0xfc6f,
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+    0xffaf,
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+    0x46cb,
+    0x9009,
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+    0x0c7e,
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+    0xc740,
+    0xd8ff,
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+    0x0c6a,
+    0xfc6f,
+    0xc740,
+    0x0e96,
+    0xfc6f,
+    0xd8ff,
+    0xf838,
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+    0xc740,
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+    0x8000,
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+    0x0606,
+    0xf002,
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+    0x712c,
+    0xc008,
+    0x704c,
+    0x1ef2,
+    0x9004,
+    0x0862,
+    0xffaf,
+    0xc005,
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+    0x0e02,
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+    0xb5e0,
+    0x0b2a,
+    0xfc6f,
+    0xb5f2,
+    0x1200,
+    0x3083,
+    0xd8ff,
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+    0x754c,
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+    0x0bea,
+    0xfc6f,
+    0xc740,
+    0xc006,
+    0xc304,
+    0x702c,
+    0xc042,
+    0xd8ff,
+    0xb990,
+    0x724c,
+    0xc743,
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+    0x0bd2,
+    0xfc6f,
+    0xc740,
+    0xf814,
+    0xc743,
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+    0xc741,
+    0x0bc6,
+    0xfc6f,
+    0xc740,
+    0x700c,
+    0x0b7e,
+    0xfc6f,
+    0x712c,
+    0xc00c,
+    0x702c,
+    0x704c,
+    0xb600,
+    0xc009,
+    0xb0e0,
+    0xb5e1,
+    0x0aaa,
+    0xfeef,
+    0xc00a,
+    0xc005,
+    0x0a02,
+    0xfcaf,
+    0x702c,
+    0xc10b,
+    0x2055,
+    0x0d00,
+    0x714c,
+    0x7825,
+    0xc10a,
+    0x0f62,
+    0xffaf,
+    0x706c,
+    0x0e1a,
+    0xfe0f,
+    0x0b9e,
+    0xfecf,
+    0xc7c6,
+    0xd8ff,
+    0xd980,
+    0x754c,
+    0x746c,
+    0x7ee0,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+};
+
+const uint32_t phyinit_fw_2d[] =
+{
+    0x0204,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x0050,
+    0x0000,
+    0x2069,
+    0x0040,
+    0x264a,
+    0x7000,
+    0x264a,
+    0x7000,
+    0x264a,
+    0x7000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x7054,
+    0x7ce0,
+    0x4300,
+    0x1101,
+    0x048c,
+    0x2242,
+    0x8042,
+    0x1b01,
+    0x0312,
+    0xf5fb,
+    0x7ee0,
+    0x78e0,
+    0x1cfc,
+    0xb3c8,
+    0x1cfc,
+    0xb388,
+    0x7fe0,
+    0x1cfc,
+    0xb348,
+    0x78e0,
+    0x7ee0,
+    0x78e0,
+    0x748d,
+    0xdd0c,
+    0xf00c,
+    0x78e0,
+    0x748d,
+    0xdd08,
+    0xf009,
+    0x78e0,
+    0x748d,
+    0x74ad,
+    0xf006,
+    0x78e0,
+    0x748d,
+    0xf006,
+    0xc702,
+    0xc601,
+    0x24b0,
+    0x334d,
+    0x24b0,
+    0x331f,
+    0x7ee0,
+    0x78e0,
+    0xc5e1,
+    0xc6e1,
+    0xc7e1,
+    0x2107,
+    0x00cb,
+    0x262f,
+    0xf040,
+    0x704d,
+    0x0010,
+    0x0026,
+    0x232f,
+    0x12c4,
+    0x200e,
+    0x8280,
+    0x2203,
+    0x1041,
+    0x0b19,
+    0x07de,
+    0x220e,
+    0x8282,
+    0x2203,
+    0x10c3,
+    0xf006,
+    0x78e0,
+    0xc5e1,
+    0xc6e1,
+    0xc7e1,
+    0x706d,
+    0x250a,
+    0x9080,
+    0x23cc,
+    0x8021,
+    0xf260,
+    0x7034,
+    0xf20c,
+    0x003c,
+    0x002b,
+    0xdc40,
+    0x202f,
+    0x8000,
+    0x212f,
+    0x804b,
+    0x07f8,
+    0xffe3,
+    0xbc61,
+    0xf014,
+    0xdc20,
+    0x210a,
+    0x8000,
+    0x22ca,
+    0x0021,
+    0x23ca,
+    0x0021,
+    0xf222,
+    0x0014,
+    0x0024,
+    0x700c,
+    0x212f,
+    0x8040,
+    0xbc61,
+    0x07fe,
+    0xffe3,
+    0x21c0,
+    0x8043,
+    0x240a,
+    0x7300,
+    0x260a,
+    0x90c0,
+    0x704c,
+    0x0046,
+    0x0022,
+    0x706c,
+    0x20a8,
+    0x0380,
+    0x2000,
+    0x8000,
+    0x2101,
+    0x8041,
+    0x2201,
+    0x8082,
+    0x25cc,
+    0x9086,
+    0x20c0,
+    0x006e,
+    0x22c2,
+    0x034e,
+    0x7075,
+    0xf22f,
+    0xf645,
+    0x220e,
+    0x8282,
+    0x2203,
+    0x10c3,
+    0x232f,
+    0x92c0,
+    0x004e,
+    0x0003,
+    0x200e,
+    0x8280,
+    0x0047,
+    0x0020,
+    0x2203,
+    0x1041,
+    0x20a8,
+    0x0580,
+    0x2000,
+    0x8000,
+    0x2101,
+    0x8041,
+    0x2201,
+    0x8082,
+    0x2301,
+    0x00c3,
+    0x2202,
+    0x8342,
+    0x2303,
+    0x8383,
+    0xf746,
+    0x2200,
+    0x8342,
+    0x2301,
+    0x8383,
+    0x20c0,
+    0x0066,
+    0x7075,
+    0x0012,
+    0x0001,
+    0xf1da,
+    0x4241,
+    0x4341,
+    0x6a09,
+    0x212f,
+    0x0002,
+    0xc7c1,
+    0xc6c1,
+    0xc5c1,
+    0x7ee0,
+    0x78e0,
+    0x2244,
+    0x8ffc,
+    0x264a,
+    0x7000,
+    0x20e8,
+    0x01a2,
+    0x202f,
+    0x8000,
+    0x212f,
+    0x004b,
+    0x7ee0,
+    0x78e0,
+    0x702c,
+    0x704c,
+    0x706c,
+    0x704d,
+    0x706d,
+    0x708d,
+    0x70ad,
+    0x70cd,
+    0x70ed,
+    0x206a,
+    0x0280,
+    0xb88d,
+    0x2029,
+    0x8000,
+    0x44db,
+    0x8000,
+    0x4000,
+    0x42db,
+    0x8000,
+    0x0400,
+    0x706f,
+    0x78e0,
+    0x2022,
+    0x0f80,
+    0x0000,
+    0x2640,
+    0x2069,
+    0x0040,
+    0x78e0,
+    0xf1fe,
+    0xc3e1,
+    0xc2e1,
+    0xc1e1,
+    0xc0e1,
+    0xc0f1,
+    0xc5e1,
+    0xc1a1,
+    0xe806,
+    0x7487,
+    0xdc14,
+    0x066b,
+    0xffcf,
+    0xda25,
+    0xba9f,
+    0x8a60,
+    0x1233,
+    0x0080,
+    0x7865,
+    0x1aea,
+    0x8002,
+    0x12ed,
+    0x8080,
+    0x208c,
+    0x8fc3,
+    0xf20d,
+    0xc085,
+    0xc040,
+    0x4020,
+    0x0cae,
+    0x0260,
+    0xc185,
+    0x41c3,
+    0x0402,
+    0x0000,
+    0x0f6e,
+    0x0020,
+    0xd8ff,
+    0x70ad,
+    0x0b62,
+    0x0220,
+    0x1a10,
+    0x3003,
+    0x0bee,
+    0x0260,
+    0xd8ff,
+    0x25ab,
+    0x10c4,
+    0x7fff,
+    0xf1ff,
+    0x78e0,
+    0xb8e6,
+    0x781d,
+    0x781d,
+    0x781d,
+    0xb8c2,
+    0x742c,
+    0xf403,
+    0x7914,
+    0xf006,
+    0x7915,
+    0x0909,
+    0x0354,
+    0x762c,
+    0x7915,
+    0x7fe0,
+    0x6901,
+    0x42c3,
+    0x8000,
+    0x06cd,
+    0x8a20,
+    0x215f,
+    0x0c81,
+    0x6038,
+    0x8a21,
+    0x215f,
+    0x0641,
+    0x6119,
+    0x8903,
+    0xb8e6,
+    0x8902,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x001c,
+    0xb8c2,
+    0xf409,
+    0x7034,
+    0x41c3,
+    0x8000,
+    0x0544,
+    0xf209,
+    0xe108,
+    0xf007,
+    0x7034,
+    0x41c3,
+    0x8000,
+    0x0534,
+    0xf203,
+    0xe108,
+    0x6119,
+    0x7fe0,
+    0x8900,
+    0xc0e2,
+    0x2053,
+    0x014c,
+    0x781d,
+    0x781d,
+    0x781d,
+    0x781d,
+    0x781d,
+    0x781d,
+    0x2044,
+    0x004d,
+    0x702c,
+    0x704c,
+    0xf00b,
+    0x1070,
+    0x0083,
+    0x0d19,
+    0x10e0,
+    0x792f,
+    0x106e,
+    0x0080,
+    0x7144,
+    0x6119,
+    0x784f,
+    0x08ed,
+    0x80b4,
+    0x7043,
+    0xf003,
+    0x6199,
+    0x782f,
+    0xc4c2,
+    0x78e0,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1b6,
+    0x4548,
+    0xc153,
+    0x4200,
+    0x750c,
+    0x41c3,
+    0x018c,
+    0x0001,
+    0x0e92,
+    0x0020,
+    0xc354,
+    0x706f,
+    0xf041,
+    0x4261,
+    0xf015,
+    0xc014,
+    0x0819,
+    0x00b0,
+    0xc08e,
+    0xc014,
+    0x087f,
+    0x0071,
+    0xc38e,
+    0x6548,
+    0x7b34,
+    0xb300,
+    0xf006,
+    0x25f4,
+    0x1083,
+    0x7834,
+    0xb060,
+    0xc013,
+    0x7124,
+    0x621a,
+    0x09dd,
+    0x8294,
+    0x4183,
+    0x911c,
+    0x1446,
+    0x3103,
+    0x915f,
+    0xc055,
+    0x1448,
+    0x3101,
+    0x144a,
+    0x3100,
+    0x143a,
+    0x311f,
+    0x143c,
+    0x311e,
+    0x1440,
+    0x310f,
+    0x1442,
+    0x310e,
+    0x1444,
+    0x310c,
+    0xc346,
+    0xc315,
+    0xc048,
+    0xc147,
+    0xc242,
+    0x750c,
+    0x41c3,
+    0x018d,
+    0x000b,
+    0xc445,
+    0xc644,
+    0xc743,
+    0x1c04,
+    0x3780,
+    0x1c00,
+    0x37c0,
+    0x0e12,
+    0x0020,
+    0x4261,
+    0x7167,
+    0xc013,
+    0x232f,
+    0x16c8,
+    0x0b7d,
+    0x9024,
+    0x702c,
+    0xc0b6,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0x700c,
+    0x1e00,
+    0x7004,
+    0x9004,
+    0x0102,
+    0x7ee0,
+    0xc2e4,
+    0x4308,
+    0x70ad,
+    0x46cb,
+    0x9008,
+    0x01e4,
+    0x218c,
+    0x8fc3,
+    0xb6a0,
+    0xb6a1,
+    0xb6a2,
+    0xf224,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0004,
+    0x201a,
+    0x0f83,
+    0x0020,
+    0x0000,
+    0x2305,
+    0x0f80,
+    0x9004,
+    0x0040,
+    0xb020,
+    0x40c3,
+    0x8000,
+    0x06d1,
+    0x8881,
+    0x8800,
+    0xf00c,
+    0x201a,
+    0x0f82,
+    0x0000,
+    0x2000,
+    0x7104,
+    0x7a65,
+    0x2205,
+    0x0f82,
+    0x9002,
+    0x0040,
+    0xb220,
+    0x0ceb,
+    0x9005,
+    0x09be,
+    0x01c0,
+    0x208a,
+    0x021a,
+    0x41c3,
+    0x900e,
+    0x002a,
+    0x1efc,
+    0x92c4,
+    0xb100,
+    0x40c3,
+    0x8000,
+    0x04bc,
+    0xa8a0,
+    0x40c3,
+    0x0000,
+    0x0fac,
+    0xb101,
+    0x700c,
+    0xc6c4,
+    0x704c,
+    0x7210,
+    0x20e0,
+    0x07ca,
+    0x1600,
+    0x7101,
+    0x9008,
+    0x01d6,
+    0x09f3,
+    0x803e,
+    0x7144,
+    0x7ee0,
+    0xc2e2,
+    0x4328,
+    0x0fb2,
+    0x0060,
+    0x260a,
+    0x3000,
+    0x45cb,
+    0x9004,
+    0x00f2,
+    0x1d00,
+    0x1045,
+    0x1d00,
+    0x1005,
+    0x1e00,
+    0x7784,
+    0x9008,
+    0x01e2,
+    0x0fea,
+    0x0120,
+    0x760c,
+    0x0b17,
+    0x1030,
+    0x1d10,
+    0x1045,
+    0x40c3,
+    0x0000,
+    0x61a8,
+    0x0fb6,
+    0xffcf,
+    0x1d10,
+    0x1005,
+    0xc6c2,
+    0xc2e2,
+    0x70ad,
+    0xf007,
+    0xca11,
+    0x7704,
+    0x0fba,
+    0xffef,
+    0x7810,
+    0x71a5,
+    0xc813,
+    0x0df3,
+    0x9024,
+    0x712c,
+    0xc6c2,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a6,
+    0x260a,
+    0x3080,
+    0xc20b,
+    0xc345,
+    0xdb7f,
+    0xc040,
+    0x7b44,
+    0xd84b,
+    0x2338,
+    0x000f,
+    0x279a,
+    0x1002,
+    0xbae6,
+    0x208a,
+    0x003e,
+    0x234f,
+    0x004c,
+    0x27ca,
+    0x1001,
+    0xe4cf,
+    0x27ca,
+    0x1001,
+    0xe3d1,
+    0x27ca,
+    0x1001,
+    0xc000,
+    0x1600,
+    0x7083,
+    0x8000,
+    0x04bc,
+    0x1400,
+    0x301f,
+    0x208c,
+    0x8fc3,
+    0xc00e,
+    0x2642,
+    0x304b,
+    0x27ca,
+    0x30c1,
+    0xc043,
+    0xc00d,
+    0xc044,
+    0xc00c,
+    0x0b51,
+    0x16b5,
+    0xc042,
+    0xdb50,
+    0xc341,
+    0xdb20,
+    0xd810,
+    0xde30,
+    0xdd60,
+    0x4378,
+    0x708d,
+    0x2025,
+    0x02c0,
+    0xf01a,
+    0xf01a,
+    0xf018,
+    0xf018,
+    0xf05c,
+    0xf019,
+    0xf014,
+    0xf016,
+    0xf045,
+    0xf048,
+    0xf010,
+    0xf010,
+    0xf047,
+    0xf03b,
+    0xf00e,
+    0xf00c,
+    0xf00a,
+    0xf00a,
+    0xf008,
+    0xf008,
+    0xf006,
+    0xf006,
+    0xf03f,
+    0xf034,
+    0xf005,
+    0xf0a8,
+    0x706c,
+    0xf003,
+    0xdb10,
+    0x264c,
+    0xb640,
+    0x014a,
+    0x002d,
+    0x4060,
+    0x726c,
+    0x748d,
+    0xc041,
+    0x4608,
+    0x4318,
+    0x4508,
+    0x4708,
+    0x2025,
+    0x0780,
+    0xf036,
+    0xf02c,
+    0xf02b,
+    0xf017,
+    0xf017,
+    0xf093,
+    0xf099,
+    0xf093,
+    0xf015,
+    0xf019,
+    0xf01c,
+    0xf091,
+    0xf00f,
+    0xf01b,
+    0xf00f,
+    0xf00d,
+    0xf089,
+    0xf087,
+    0xf087,
+    0xf085,
+    0xf085,
+    0xf018,
+    0xf017,
+    0xf013,
+    0xf008,
+    0xf006,
+    0xdb07,
+    0xf012,
+    0xc701,
+    0x758d,
+    0xf018,
+    0x758d,
+    0x47a9,
+    0xf014,
+    0x758d,
+    0x47c9,
+    0xf012,
+    0x718d,
+    0x476b,
+    0xf00e,
+    0x768d,
+    0xf00b,
+    0x708d,
+    0xf00a,
+    0x736c,
+    0x0e0d,
+    0x30d1,
+    0xc402,
+    0x249a,
+    0x1004,
+    0x7a85,
+    0x4468,
+    0x4708,
+    0x238a,
+    0x0ffd,
+    0x7b24,
+    0x783d,
+    0x2044,
+    0x0c0b,
+    0xe3b0,
+    0xdb58,
+    0x23cf,
+    0x11e1,
+    0x7b24,
+    0x2084,
+    0x0001,
+    0x2305,
+    0x02c3,
+    0x7885,
+    0x7b05,
+    0x783d,
+    0x239a,
+    0x0004,
+    0x781d,
+    0xc405,
+    0x781d,
+    0x2004,
+    0x0f80,
+    0x0000,
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+    0x8000,
+    0x05e4,
+    0x206f,
+    0x0143,
+    0x88c2,
+    0x1a00,
+    0x3103,
+    0x261a,
+    0x1f80,
+    0x0020,
+    0x0000,
+    0x43d9,
+    0xc040,
+    0x2005,
+    0x0f81,
+    0x9004,
+    0x0032,
+    0x206f,
+    0x0143,
+    0x90a7,
+    0x9100,
+    0xc042,
+    0xc000,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0040,
+    0x0d8a,
+    0x00a0,
+    0x9000,
+    0xbde0,
+    0x0286,
+    0x0001,
+    0xc000,
+    0x2005,
+    0x0f81,
+    0x9005,
+    0xe032,
+    0xc002,
+    0xb880,
+    0xb100,
+    0xc000,
+    0x2005,
+    0x0f80,
+    0x9003,
+    0xe090,
+    0x0ce2,
+    0x0020,
+    0x1800,
+    0x0005,
+    0x266f,
+    0x1cc3,
+    0x8e00,
+    0xe886,
+    0x1e00,
+    0x7085,
+    0x9004,
+    0x00c0,
+    0x0cba,
+    0xffcf,
+    0x0c6a,
+    0xff4f,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0x0841,
+    0x001e,
+    0x43c3,
+    0x9004,
+    0x0014,
+    0x9320,
+    0xca01,
+    0x080f,
+    0x01b0,
+    0x214f,
+    0x0082,
+    0x080d,
+    0x00d1,
+    0x2185,
+    0x0108,
+    0x4220,
+    0xb340,
+    0xd823,
+    0x42c3,
+    0x9005,
+    0xe034,
+    0xb200,
+    0x702c,
+    0x40c3,
+    0x9003,
+    0xe034,
+    0xb020,
+    0xb8b1,
+    0xb020,
+    0x0ce2,
+    0x0020,
+    0xb221,
+    0x8e00,
+    0x089d,
+    0x0031,
+    0x206f,
+    0x0143,
+    0x8802,
+    0x41c3,
+    0x9002,
+    0x0086,
+    0x1600,
+    0x7082,
+    0x8000,
+    0x0000,
+    0x201a,
+    0x0f80,
+    0x0020,
+    0x0000,
+    0x231a,
+    0x3f9b,
+    0x0010,
+    0x0000,
+    0x7825,
+    0x9000,
+    0x781d,
+    0x781d,
+    0x781d,
+    0x781d,
+    0xb8c2,
+    0x0823,
+    0x0090,
+    0x0827,
+    0x00f1,
+    0x228b,
+    0x803e,
+    0x42c3,
+    0x8000,
+    0x042c,
+    0xce0a,
+    0x705c,
+    0x5016,
+    0x42c3,
+    0x8000,
+    0x0444,
+    0xce10,
+    0xf011,
+    0xce09,
+    0x5016,
+    0xce0f,
+    0xf00e,
+    0x228b,
+    0x803e,
+    0x42c3,
+    0x8000,
+    0x0420,
+    0xce07,
+    0x705c,
+    0x5016,
+    0x42c3,
+    0x8000,
+    0x0438,
+    0xce0d,
+    0x705c,
+    0x5034,
+    0xc000,
+    0x7825,
+    0x0d1e,
+    0x00a0,
+    0x90c0,
+    0x0caa,
+    0x00a0,
+    0x4063,
+    0xc000,
+    0xbea0,
+    0x2005,
+    0x0f81,
+    0x9003,
+    0xfe86,
+    0xb1c0,
+    0x0bfe,
+    0x0000,
+    0x0bca,
+    0xff8f,
+    0x083e,
+    0xfecf,
+    0x0d66,
+    0xff4f,
+    0xca06,
+    0x704c,
+    0x708d,
+    0xf038,
+    0x245a,
+    0x149e,
+    0x2600,
+    0x3f83,
+    0x8000,
+    0x05e4,
+    0xb341,
+    0xf02d,
+    0x241a,
+    0x1f81,
+    0x0000,
+    0x1000,
+    0x79c5,
+    0x793b,
+    0x2105,
+    0x0f81,
+    0x9002,
+    0x0140,
+    0x9120,
+    0x7f2f,
+    0x0e11,
+    0x13e1,
+    0x716d,
+    0x8b22,
+    0x210f,
+    0x0381,
+    0xab22,
+    0xf018,
+    0x8b23,
+    0x2744,
+    0x17db,
+    0x7124,
+    0xab23,
+    0x792f,
+    0x2614,
+    0x3041,
+    0x2100,
+    0x0f81,
+    0x8000,
+    0x05e4,
+    0x4769,
+    0xa9c3,
+    0x0b0f,
+    0x3010,
+    0x2342,
+    0x305b,
+    0x0bfd,
+    0xb031,
+    0x7ffb,
+    0xa9e2,
+    0x71c5,
+    0x0ead,
+    0x9214,
+    0x7185,
+    0x0c95,
+    0x9024,
+    0x70cd,
+    0x1600,
+    0x708f,
+    0x8000,
+    0x0025,
+    0xef28,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0032,
+    0x1600,
+    0x709b,
+    0x8000,
+    0x06d3,
+    0x71cd,
+    0xb8e3,
+    0x26ca,
+    0x10a1,
+    0xf014,
+    0x0f15,
+    0x103e,
+    0x212f,
+    0x06c7,
+    0x700c,
+    0x42c1,
+    0x08fe,
+    0xff2f,
+    0x706c,
+    0x0f13,
+    0x107e,
+    0x212f,
+    0x06c7,
+    0x710c,
+    0x42c1,
+    0x08ea,
+    0xff2f,
+    0x706c,
+    0x7167,
+    0x40c3,
+    0x8000,
+    0x06d3,
+    0x8801,
+    0x08d3,
+    0x86c5,
+    0x1600,
+    0x708f,
+    0x8000,
+    0x0058,
+    0xef28,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0065,
+    0x71cd,
+    0xb8e3,
+    0x40c3,
+    0x8000,
+    0x06d3,
+    0x1002,
+    0x009b,
+    0x26ca,
+    0x10a1,
+    0xf014,
+    0x0f15,
+    0x103e,
+    0x212f,
+    0x06c7,
+    0x700c,
+    0x42c1,
+    0x08a6,
+    0xff2f,
+    0x706c,
+    0x0f13,
+    0x107e,
+    0x212f,
+    0x06c7,
+    0x710c,
+    0x42c1,
+    0x0892,
+    0xff2f,
+    0x706c,
+    0x7167,
+    0x40c3,
+    0x8000,
+    0x06d3,
+    0x8803,
+    0x08d3,
+    0x86c5,
+    0x0d09,
+    0x133f,
+    0x710c,
+    0xf008,
+    0x0afe,
+    0x0000,
+    0x0ade,
+    0x0020,
+    0xd80d,
+    0x700c,
+    0x0d12,
+    0x0140,
+    0x0c56,
+    0xfe8f,
+    0x1e00,
+    0x7003,
+    0x8000,
+    0x05e4,
+    0x0ac6,
+    0x0020,
+    0x700c,
+    0xca06,
+    0x70ed,
+    0x704c,
+    0xf019,
+    0x702c,
+    0xf014,
+    0x221a,
+    0x0f83,
+    0x0000,
+    0x1000,
+    0x2300,
+    0x1f8c,
+    0x8000,
+    0x1b9c,
+    0x7165,
+    0x7b25,
+    0x7b7b,
+    0x2305,
+    0x0f83,
+    0x9002,
+    0x0140,
+    0x93c0,
+    0xacc0,
+    0xb320,
+    0x7124,
+    0x09db,
+    0x8214,
+    0x7144,
+    0x0ad3,
+    0x8024,
+    0x2716,
+    0x108b,
+    0x0d63,
+    0x11be,
+    0x700c,
+    0x46cb,
+    0x8000,
+    0x06cd,
+    0xae00,
+    0x780f,
+    0x084d,
+    0x0095,
+    0xe81c,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0058,
+    0x7014,
+    0x710c,
+    0xf212,
+    0x0e0e,
+    0xfe8f,
+    0x8e00,
+    0x7104,
+    0x0bbe,
+    0xfeef,
+    0x780f,
+    0x0bd2,
+    0xfe8f,
+    0x0c8e,
+    0x00e0,
+    0x1e01,
+    0x1003,
+    0x0a42,
+    0x0020,
+    0x760c,
+    0x8e00,
+    0x7104,
+    0xf1e3,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0025,
+    0x7014,
+    0x700c,
+    0xf5e7,
+    0xf1f8,
+    0x0b8e,
+    0xfeef,
+    0x730c,
+    0xbde5,
+    0xf4ae,
+    0xf0b9,
+    0xe809,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0058,
+    0x7014,
+    0x710c,
+    0xf40a,
+    0xf0a3,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0025,
+    0x7014,
+    0x700c,
+    0xf29d,
+    0x0daa,
+    0xfe8f,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x06cd,
+    0x7104,
+    0x0b56,
+    0xfeef,
+    0x780f,
+    0x0b6a,
+    0xfe8f,
+    0x700c,
+    0xc041,
+    0x40c3,
+    0x8000,
+    0x06cd,
+    0x1801,
+    0x0003,
+    0x0b72,
+    0xff2f,
+    0x710c,
+    0x40c3,
+    0x8000,
+    0x06cd,
+    0x8801,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x06cd,
+    0x205f,
+    0x0640,
+    0x215f,
+    0x0c81,
+    0x6038,
+    0x2000,
+    0x0f80,
+    0x8000,
+    0x0580,
+    0x88a3,
+    0x206f,
+    0x0143,
+    0x88c2,
+    0x261a,
+    0x1f8e,
+    0x0020,
+    0x0000,
+    0x2605,
+    0x1f8f,
+    0x9002,
+    0x0086,
+    0x0ab2,
+    0xff2f,
+    0x710c,
+    0x97e0,
+    0x712c,
+    0x0ffa,
+    0x0020,
+    0x4318,
+    0x2605,
+    0x1f8e,
+    0x9003,
+    0xfe86,
+    0x2746,
+    0x1340,
+    0xc043,
+    0xb600,
+    0xbde6,
+    0xd8ff,
+    0x258a,
+    0x1fc7,
+    0x25ca,
+    0x1001,
+    0x4063,
+    0x41a1,
+    0x714c,
+    0x0d4e,
+    0x0020,
+    0x706c,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x001d,
+    0x087f,
+    0x001e,
+    0xc003,
+    0x41c3,
+    0x0093,
+    0x0000,
+    0xb882,
+    0xb600,
+    0x0d26,
+    0xfeaf,
+    0x740c,
+    0x4063,
+    0x41a1,
+    0x704c,
+    0x0d26,
+    0x0020,
+    0xdb40,
+    0x41c3,
+    0x0094,
+    0x0000,
+    0x0d0e,
+    0xfeaf,
+    0x740c,
+    0x4063,
+    0x41a1,
+    0x704c,
+    0x0d0e,
+    0x0020,
+    0xdb30,
+    0x4063,
+    0x41a1,
+    0x724c,
+    0x0d02,
+    0x0020,
+    0x706c,
+    0xf01b,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x001f,
+    0xc001,
+    0x0925,
+    0x000e,
+    0xc001,
+    0x201a,
+    0x0f81,
+    0x0020,
+    0x0000,
+    0x2105,
+    0x0f80,
+    0x9003,
+    0xfe86,
+    0x2105,
+    0x0f81,
+    0x9002,
+    0x0086,
+    0x9120,
+    0xb9a0,
+    0xb020,
+    0xc001,
+    0x7104,
+    0xc041,
+    0xc001,
+    0x08cb,
+    0x8134,
+    0x750c,
+    0x08d2,
+    0x0000,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x06cd,
+    0x68e1,
+    0x78ef,
+    0x7114,
+    0x1e00,
+    0x73c2,
+    0x8000,
+    0x06cd,
+    0x069c,
+    0xffce,
+    0x0a1a,
+    0xfeef,
+    0x730c,
+    0x0c1a,
+    0xff8f,
+    0xca06,
+    0x706f,
+    0x704c,
+    0xf017,
+    0x706c,
+    0xf012,
+    0x221a,
+    0x0f81,
+    0x0000,
+    0x1000,
+    0x7965,
+    0x793b,
+    0x2105,
+    0x0f8c,
+    0x9002,
+    0x0140,
+    0x2332,
+    0x1f81,
+    0x8000,
+    0x1b9c,
+    0x7164,
+    0x7165,
+    0xb420,
+    0x0bdf,
+    0x8214,
+    0x7144,
+    0x0ad7,
+    0x8024,
+    0x2316,
+    0x308b,
+    0xc000,
+    0x2005,
+    0x0f81,
+    0x9005,
+    0xe032,
+    0xc002,
+    0xb100,
+    0x09b2,
+    0xfeef,
+    0x700c,
+    0x0836,
+    0x0080,
+    0x08c6,
+    0x00e0,
+    0xd807,
+    0x23ab,
+    0x30c4,
+    0x7fff,
+    0xf000,
+    0xc2e2,
+    0x45cb,
+    0x9004,
+    0x0004,
+    0x9500,
+    0xb8a1,
+    0xb500,
+    0x0ed6,
+    0xffaf,
+    0x740c,
+    0xd81f,
+    0x0ece,
+    0xffaf,
+    0x1df6,
+    0x105d,
+    0xc6c2,
+    0xc2e2,
+    0x0ec2,
+    0xffaf,
+    0xd81f,
+    0x45cb,
+    0x9004,
+    0x01f0,
+    0x740c,
+    0x0eb2,
+    0xffaf,
+    0x1d00,
+    0x1005,
+    0x150a,
+    0x9700,
+    0xb881,
+    0x1d0a,
+    0x901c,
+    0xc6c2,
+    0xc0f1,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x0012,
+    0x218c,
+    0x8203,
+    0x0864,
+    0x00ce,
+    0x080e,
+    0x0000,
+    0xc0d1,
+    0x7ee0,
+    0x78e0,
+    0xc2e2,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0x081b,
+    0x003e,
+    0xd80a,
+    0x45cb,
+    0x9005,
+    0xe036,
+    0x0e6e,
+    0xffaf,
+    0x1d00,
+    0x1045,
+    0x1d00,
+    0x1005,
+    0xc6c2,
+    0x40c3,
+    0x9004,
+    0x00f2,
+    0x1800,
+    0x0045,
+    0x7fe0,
+    0x1800,
+    0x0005,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a7,
+    0xc044,
+    0x40c3,
+    0x8000,
+    0x06d1,
+    0x8800,
+    0xc146,
+    0x702c,
+    0x201a,
+    0x0f80,
+    0x0000,
+    0x2000,
+    0x2005,
+    0x0f80,
+    0x9002,
+    0x0040,
+    0x90c0,
+    0x0d86,
+    0xfe6f,
+    0x700c,
+    0x1200,
+    0x3083,
+    0xd981,
+    0x70ad,
+    0xd8ff,
+    0xb98e,
+    0x754c,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x0e62,
+    0xfe6f,
+    0xc540,
+    0x700c,
+    0x0dfe,
+    0xfe6f,
+    0x712c,
+    0x08a6,
+    0xff0f,
+    0x08ae,
+    0xff2f,
+    0xc045,
+    0x40c3,
+    0x0000,
+    0x2710,
+    0x0e66,
+    0xffaf,
+    0xd908,
+    0x40c3,
+    0x900f,
+    0xe0c0,
+    0x1800,
+    0x0205,
+    0xb0a5,
+    0x79cf,
+    0x0d3a,
+    0xfe6f,
+    0x700c,
+    0x702c,
+    0x716f,
+    0xd8ff,
+    0xb98e,
+    0x754c,
+    0x746c,
+    0xc543,
+    0xc542,
+    0x1c04,
+    0x36c0,
+    0x0e16,
+    0xfe6f,
+    0xc540,
+    0xd8ff,
+    0x702c,
+    0x754c,
+    0x746c,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x0e02,
+    0xfe6f,
+    0xc540,
+    0x0846,
+    0xfeaf,
+    0xd8ff,
+    0xc004,
+    0x702c,
+    0x704c,
+    0x7f0f,
+    0xd8ff,
+    0x746c,
+    0xc543,
+    0xc742,
+    0xc541,
+    0x0de2,
+    0xfe6f,
+    0xc540,
+    0xd8ff,
+    0x702c,
+    0x754c,
+    0xdb28,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x0dce,
+    0xfe6f,
+    0xc540,
+    0xc105,
+    0x79d4,
+    0x4968,
+    0xb8c0,
+    0x6038,
+    0xe030,
+    0xc045,
+    0xc004,
+    0x46cb,
+    0x0000,
+    0x3100,
+    0xb8c1,
+    0xc044,
+    0xc006,
+    0xe805,
+    0x1c0c,
+    0x3441,
+    0xf067,
+    0xf8a5,
+    0xc543,
+    0xc742,
+    0xc541,
+    0x0d9e,
+    0xfe6f,
+    0xc540,
+    0xf89e,
+    0xc543,
+    0xc742,
+    0x1c04,
+    0x36c0,
+    0x0d8e,
+    0xfe6f,
+    0xc540,
+    0xf897,
+    0x1c0c,
+    0x36c0,
+    0xc742,
+    0xc541,
+    0x0d7e,
+    0xfe6f,
+    0xc540,
+    0xf899,
+    0xc543,
+    0xc742,
+    0xc541,
+    0x0d6e,
+    0xfe6f,
+    0xc540,
+    0x750c,
+    0xc041,
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+    0xb100,
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+    0x78e0,
+    0xc2e6,
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+    0xb6c8,
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+    0x024d,
+    0x7e9b,
+    0x7c7b,
+    0x7ee5,
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+    0xab80,
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+    0x01e0,
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+    0xe1f2,
+    0xb100,
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+    0x208a,
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+    0xb1e1,
+    0xb102,
+    0x710c,
+    0x2644,
+    0x17c1,
+    0xe906,
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+    0x9002,
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+    0x40c3,
+    0x0000,
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+    0x4200,
+    0x0936,
+    0xfeef,
+    0x4300,
+    0xc091,
+    0x702c,
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+    0x40c3,
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+    0xf032,
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+    0x036e,
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+    0x1800,
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+    0xb700,
+    0x71a5,
+    0x7285,
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+    0xfe0f,
+    0x40c3,
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+    0x2455,
+    0x3e8f,
+    0x43cb,
+    0x8000,
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+    0x0480,
+    0x671f,
+    0x40c3,
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+    0x0000,
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+    0x0166,
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+    0x218c,
+    0x8004,
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+    0x0002,
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+    0x262f,
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+    0x301e,
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+    0x0000,
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+    0x109e,
+    0x262f,
+    0xf088,
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+    0x3787,
+    0x2314,
+    0x1000,
+    0x8821,
+    0x2608,
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+    0x2044,
+    0x07c2,
+    0x4020,
+    0xc108,
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+    0xba61,
+    0x0aff,
+    0x8031,
+    0x781b,
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+    0xc046,
+    0xc006,
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+    0x7080,
+    0x8000,
+    0x06cd,
+    0x205f,
+    0x0c81,
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+    0x6119,
+    0x2100,
+    0x0f80,
+    0x8000,
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+    0x882e,
+    0x0d72,
+    0x00a0,
+    0x40a1,
+    0xc00a,
+    0xe80f,
+    0xc004,
+    0xc302,
+    0x41c3,
+    0x001e,
+    0x0004,
+    0xc041,
+    0x740c,
+    0x724c,
+    0x0c36,
+    0xfe2f,
+    0xc540,
+    0x0f5a,
+    0xfe2f,
+    0xc004,
+    0xc00b,
+    0xe80a,
+    0x1600,
+    0x7001,
+    0x8000,
+    0x06dc,
+    0xc002,
+    0x704c,
+    0x0e82,
+    0xfeef,
+    0x706c,
+    0x2480,
+    0x3706,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0xc2e6,
+    0x1210,
+    0x308d,
+    0x70cd,
+    0x70ed,
+    0x1a10,
+    0x3382,
+    0xf009,
+    0x26f0,
+    0x73c0,
+    0x8000,
+    0x1ca8,
+    0x08be,
+    0x0040,
+    0x71e5,
+    0xcc36,
+    0x0ff1,
+    0x9004,
+    0x1a10,
+    0x3342,
+    0x1a36,
+    0x339c,
+    0xc6c6,
+    0x78e0,
+    0x43c3,
+    0x9008,
+    0x01ea,
+    0x9340,
+    0x209a,
+    0x0004,
+    0x2000,
+    0x0f80,
+    0x0000,
+    0xfe00,
+    0x2204,
+    0x0f82,
+    0x0000,
+    0xc0ff,
+    0x7845,
+    0x9341,
+    0xb300,
+    0xb962,
+    0x226c,
+    0x0140,
+    0x7825,
+    0x7fe0,
+    0xb301,
+    0x78e0,
+    0xc2e2,
+    0x1600,
+    0x710d,
+    0x8000,
+    0x0006,
+    0xe56d,
+    0x2d85,
+    0x1b81,
+    0x2553,
+    0x9041,
+    0xf205,
+    0x78af,
+    0x214e,
+    0x010d,
+    0x651d,
+    0x7aaf,
+    0x41c3,
+    0x014d,
+    0x0001,
+    0x0b82,
+    0xfe2f,
+    0xd80a,
+    0x40c3,
+    0x8000,
+    0x06cc,
+    0xa8a0,
+    0xc6c2,
+    0x78e0,
+    0xc2e6,
+    0x266f,
+    0x15c3,
+    0x8e40,
+    0x4508,
+    0xea17,
+    0x084e,
+    0xff2f,
+    0x4040,
+    0x4708,
+    0xe887,
+    0x41c3,
+    0x0174,
+    0x0001,
+    0x0ba2,
+    0xfdef,
+    0x700c,
+    0x40e1,
+    0x209a,
+    0x0001,
+    0x7f05,
+    0x78bb,
+    0x2005,
+    0x0f80,
+    0x9003,
+    0xfe92,
+    0xb0e0,
+    0x16ff,
+    0x9082,
+    0xea18,
+    0x081e,
+    0xff2f,
+    0x4040,
+    0x228c,
+    0x8fc3,
+    0xf209,
+    0xe888,
+    0x41c3,
+    0x0175,
+    0x0001,
+    0x0b6e,
+    0xfdef,
+    0x700c,
+    0x700c,
+    0x209a,
+    0x0001,
+    0x79bb,
+    0x2105,
+    0x0f81,
+    0x9003,
+    0xfe9a,
+    0xb100,
+    0xc6c6,
+    0x78e0,
+    0xc0f1,
+    0x1600,
+    0x7082,
+    0x8000,
+    0x0009,
+    0xea1a,
+    0x0a23,
+    0x0a30,
+    0x720c,
+    0x228c,
+    0x8c03,
+    0xf20c,
+    0xe2f8,
+    0xf404,
+    0x710c,
+    0xf009,
+    0x41c3,
+    0x0176,
+    0x0001,
+    0x0b2e,
+    0xfdef,
+    0x700c,
+    0x700c,
+    0x205f,
+    0x0401,
+    0x7825,
+    0x1e00,
+    0x7004,
+    0x9005,
+    0xe0a0,
+    0xc0d1,
+    0x7ee0,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a2,
+    0x4528,
+    0x2009,
+    0x0041,
+    0x0ac1,
+    0x0065,
+    0x4748,
+    0x1600,
+    0x7081,
+    0x8000,
+    0x0004,
+    0x46cb,
+    0x8000,
+    0x0474,
+    0x78e2,
+    0x211a,
+    0x0f81,
+    0x0020,
+    0x0000,
+    0x2614,
+    0x13db,
+    0xc041,
+    0x2614,
+    0x1000,
+    0x1324,
+    0x3103,
+    0x9052,
+    0xc140,
+    0x41c3,
+    0x0063,
+    0x0002,
+    0x0a7e,
+    0xfe2f,
+    0x750c,
+    0x7de2,
+    0x2614,
+    0x1340,
+    0x9072,
+    0x1324,
+    0x3102,
+    0x41c3,
+    0x0064,
+    0x0002,
+    0x0a66,
+    0xfe2f,
+    0x750c,
+    0x40c3,
+    0x8000,
+    0x06cf,
+    0x1001,
+    0x008b,
+    0x8840,
+    0xf02b,
+    0x66b9,
+    0xc001,
+    0x8970,
+    0x7144,
+    0x60d8,
+    0x239a,
+    0x0001,
+    0x8810,
+    0x7b05,
+    0x241a,
+    0x1f80,
+    0x0000,
+    0x1000,
+    0x249a,
+    0x1008,
+    0x2004,
+    0x0f81,
+    0x000f,
+    0xe000,
+    0xc000,
+    0x2484,
+    0x1008,
+    0x7825,
+    0x2005,
+    0x0301,
+    0x40c3,
+    0x9002,
+    0x0082,
+    0x2105,
+    0x000c,
+    0xe014,
+    0xb460,
+    0x2105,
+    0x0003,
+    0x66f8,
+    0x8830,
+    0x4020,
+    0x209a,
+    0x0001,
+    0x7825,
+    0xb300,
+    0x7c4f,
+    0x0bad,
+    0x9325,
+    0x710c,
+    0xf009,
+    0x41c3,
+    0x0062,
+    0x0000,
+    0x09f2,
+    0xfe2f,
+    0x740c,
+    0x700c,
+    0xc0a2,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0xc0e6,
+    0x4328,
+    0x70ed,
+    0x41c3,
+    0x9003,
+    0xff64,
+    0xb1e0,
+    0x1904,
+    0x0045,
+    0x42c3,
+    0x8000,
+    0x06d1,
+    0x8a21,
+    0x8ac0,
+    0xf039,
+    0x228c,
+    0x8fc3,
+    0xf418,
+    0x261a,
+    0x1f83,
+    0x0000,
+    0x2000,
+    0x42c3,
+    0x9002,
+    0x1f64,
+    0x2305,
+    0x008c,
+    0x7444,
+    0x7a65,
+    0xb400,
+    0x0b51,
+    0x123f,
+    0xb2e0,
+    0x42c3,
+    0x9003,
+    0xf164,
+    0xb2e0,
+    0x1a04,
+    0x0045,
+    0xf020,
+    0x260a,
+    0x32c0,
+    0x708d,
+    0xf016,
+    0xf753,
+    0x4381,
+    0x261a,
+    0x1f82,
+    0x0000,
+    0x2000,
+    0x239a,
+    0x0008,
+    0x7b45,
+    0x42c3,
+    0x9002,
+    0x0164,
+    0x2305,
+    0x008d,
+    0x7444,
+    0x7b45,
+    0xb500,
+    0x1b00,
+    0x0005,
+    0x7185,
+    0x0e0d,
+    0x3010,
+    0x0cd5,
+    0x9274,
+    0x262f,
+    0xb782,
+    0x71c5,
+    0x0993,
+    0x83a5,
+    0x222f,
+    0x02c7,
+    0xc4c6,
+    0xc2e2,
+    0xc1a4,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x05e5,
+    0x702c,
+    0x754c,
+    0xc043,
+    0xd8ff,
+    0xdb08,
+    0x4528,
+    0xc142,
+    0xc141,
+    0x0c3a,
+    0xfdef,
+    0xc140,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x05e5,
+    0xd910,
+    0x754c,
+    0xc043,
+    0xd8ff,
+    0xdb0c,
+    0xc542,
+    0xc541,
+    0x0c1e,
+    0xfdef,
+    0xc540,
+    0xd8ff,
+    0xd980,
+    0x754c,
+    0x726c,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x0c0a,
+    0xfdef,
+    0xc540,
+    0xc0a4,
+    0xc6c2,
+    0x78e0,
+    0xc2e4,
+    0xc1a4,
+    0x70ad,
+    0xd8ff,
+    0x702c,
+    0x754c,
+    0x736c,
+    0xc543,
+    0xc542,
+    0xc541,
+    0x0bea,
+    0xfdef,
+    0xc540,
+    0x46cb,
+    0x8000,
+    0x05e5,
+    0x8e00,
+    0x0825,
+    0x00b4,
+    0x702c,
+    0x7104,
+    0x781d,
+    0xb862,
+    0x780f,
+    0xc043,
+    0xd8ff,
+    0x754c,
+    0x726c,
+    0xc542,
+    0xc541,
+    0x0bc2,
+    0xfdef,
+    0xc540,
+    0x8e00,
+    0xc043,
+    0xd8ff,
+    0x702c,
+    0x754c,
+    0xdb08,
+    0xc542,
+    0xc541,
+    0x0bae,
+    0xfdef,
+    0xc540,
+    0x8e00,
+    0xd908,
+    0x754c,
+    0xc043,
+    0xd8ff,
+    0xdb0c,
+    0xc542,
+    0xc541,
+    0x0b96,
+    0xfdef,
+    0xc540,
+    0xc0a4,
+    0xc6c4,
+    0x78e0,
+    0x42c3,
+    0x9004,
+    0x0110,
+    0x9200,
+    0x204f,
+    0x0101,
+    0xb8a4,
+    0xb220,
+    0x7fe0,
+    0xb200,
+    0xc2e2,
+    0x4200,
+    0x0d02,
+    0xfe6f,
+    0x4020,
+    0x4408,
+    0x706c,
+    0x786f,
+    0x791b,
+    0x2144,
+    0x07cd,
+    0x4181,
+    0xed05,
+    0xbd61,
+    0x0dff,
+    0x9031,
+    0x793d,
+    0xb9c1,
+    0x09eb,
+    0x80a1,
+    0x7164,
+    0xc6c2,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0x2482,
+    0x3002,
+    0xc24c,
+    0xc15d,
+    0xc04b,
+    0xc09e,
+    0x702c,
+    0x0e46,
+    0xff2f,
+    0x764c,
+    0xc00b,
+    0x0df2,
+    0xfdef,
+    0xc19e,
+    0xca13,
+    0xe807,
+    0xc00b,
+    0x0a26,
+    0x0020,
+    0xc10c,
+    0x0217,
+    0x0000,
+    0x700c,
+    0xc050,
+    0xc00c,
+    0x2079,
+    0x0040,
+    0x781b,
+    0x781b,
+    0x7204,
+    0xc056,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x000e,
+    0x781d,
+    0x781d,
+    0x781d,
+    0x781d,
+    0x2044,
+    0x8041,
+    0xc016,
+    0x20ca,
+    0x00a1,
+    0xc056,
+    0xca0b,
+    0x2105,
+    0x803e,
+    0x740c,
+    0xc058,
+    0x20ca,
+    0x0061,
+    0xc058,
+    0xd810,
+    0xc059,
+    0x20ca,
+    0x0061,
+    0xc059,
+    0x700c,
+    0xc04e,
+    0xf0c5,
+    0xc010,
+    0x6038,
+    0x88e1,
+    0x88a0,
+    0xc00b,
+    0x42e1,
+    0x0d5a,
+    0x0020,
+    0x41a1,
+    0x4608,
+    0x700c,
+    0xc05c,
+    0xc019,
+    0x1460,
+    0x301b,
+    0xc04f,
+    0xc01d,
+    0xc057,
+    0xf094,
+    0x78af,
+    0xc04d,
+    0xc00c,
+    0xc64a,
+    0x7114,
+    0x700c,
+    0xc052,
+    0xc053,
+    0xf226,
+    0xc00d,
+    0x252f,
+    0x16c8,
+    0x78a2,
+    0x790f,
+    0x78ef,
+    0xc04a,
+    0xc00b,
+    0x0d1e,
+    0x0020,
+    0xc20a,
+    0xc053,
+    0xc00d,
+    0xc20a,
+    0x60b8,
+    0x790f,
+    0x0d0e,
+    0x0020,
+    0xc00b,
+    0xc052,
+    0xc013,
+    0x0e0f,
+    0x1025,
+    0x78b3,
+    0xc113,
+    0xc14a,
+    0xf00a,
+    0xc012,
+    0x0e0f,
+    0x1025,
+    0x700c,
+    0xc012,
+    0xc04a,
+    0x4063,
+    0xf002,
+    0xc64a,
+    0x780e,
+    0xc05b,
+    0xc00d,
+    0xc51b,
+    0x651d,
+    0x78ef,
+    0xc04d,
+    0xc00c,
+    0x080d,
+    0x00b1,
+    0x702c,
+    0x700c,
+    0xc151,
+    0xf023,
+    0xc00f,
+    0x7f10,
+    0xc00d,
+    0x78e2,
+    0x7a0f,
+    0x78af,
+    0xc05a,
+    0xc00b,
+    0x0cba,
+    0x0020,
+    0xc11a,
+    0xc051,
+    0xc00d,
+    0xc11a,
+    0x60f8,
+    0x7a0f,
+    0x0caa,
+    0x0020,
+    0xc00b,
+    0xc211,
+    0xc10a,
+    0x090f,
+    0x00a5,
+    0x79f3,
+    0xc211,
+    0xc24a,
+    0xf007,
+    0xc10a,
+    0x090b,
+    0x0025,
+    0x702c,
+    0xc10f,
+    0xc04a,
+    0xc70d,
+    0x1212,
+    0x3602,
+    0x1203,
+    0x3083,
+    0x792e,
+    0x0a37,
+    0x00e4,
+    0x673f,
+    0x1202,
+    0x3083,
+    0x0b2b,
+    0x00a4,
+    0x7bef,
+    0xc045,
+    0xc012,
+    0xc211,
+    0xc141,
+    0xc043,
+    0xc013,
+    0xc246,
+    0x7aaf,
+    0xc042,
+    0xc01b,
+    0x41c3,
+    0x0051,
+    0x0009,
+    0xc040,
+    0x740c,
+    0x0ea2,
+    0xfdef,
+    0xc644,
+    0xc01c,
+    0x7104,
+    0x2053,
+    0x807e,
+    0xc05c,
+    0xf405,
+    0xc00f,
+    0x7767,
+    0xb864,
+    0xc04f,
+    0xc017,
+    0xc60a,
+    0x7704,
+    0xc057,
+    0xc00f,
+    0x780e,
+    0x2048,
+    0x0040,
+    0xc04f,
+    0x202f,
+    0x06c6,
+    0x2048,
+    0x005b,
+    0xc017,
+    0x262f,
+    0xf007,
+    0xf56b,
+    0xc00e,
+    0x082d,
+    0x0385,
+    0x5042,
+    0xca03,
+    0x091f,
+    0x0004,
+    0xca02,
+    0x0817,
+    0x0064,
+    0x740c,
+    0xc210,
+    0xc30e,
+    0x41c3,
+    0x0052,
+    0x0003,
+    0x0e46,
+    0xfdef,
+    0xc640,
+    0xc555,
+    0xc754,
+    0xc64e,
+    0xc010,
+    0x7204,
+    0xc050,
+    0xc110,
+    0xc016,
+    0x7110,
+    0x0674,
+    0xffe5,
+    0xc19e,
+    0xc00c,
+    0x082f,
+    0x00d0,
+    0x41c3,
+    0x0053,
+    0x0000,
+    0x0e6e,
+    0xfdaf,
+    0xc00e,
+    0xc00c,
+    0x0811,
+    0x0050,
+    0xc115,
+    0xc00b,
+    0xb96f,
+    0x183f,
+    0x0042,
+    0xc00c,
+    0x080f,
+    0x0090,
+    0xc10b,
+    0xc014,
+    0x1940,
+    0x0002,
+    0x2480,
+    0x3002,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0x2482,
+    0x3802,
+    0xc145,
+    0x4508,
+    0xc088,
+    0x702c,
+    0x0bfe,
+    0xff2f,
+    0xda80,
+    0x704c,
+    0x70cd,
+    0xc242,
+    0xf02b,
+    0x8880,
+    0x8861,
+    0x4081,
+    0xf015,
+    0x60f8,
+    0x1000,
+    0x008b,
+    0x7165,
+    0x1800,
+    0x02c2,
+    0x716d,
+    0xca15,
+    0x2044,
+    0x07db,
+    0x4061,
+    0x0b11,
+    0x3010,
+    0x2342,
+    0x305b,
+    0x0bff,
+    0xb031,
+    0x781b,
+    0x60f8,
+    0x7f10,
+    0x0bd9,
+    0x83e5,
+    0xc088,
+    0x4b90,
+    0x7714,
+    0x7104,
+    0x20ca,
+    0x002c,
+    0x242f,
+    0x9007,
+    0xf206,
+    0x7b4f,
+    0x7124,
+    0x7470,
+    0x22ca,
+    0x000d,
+    0x71c5,
+    0x0eb1,
+    0x97f4,
+    0x2514,
+    0x1380,
+    0x700c,
+    0x708d,
+    0x70cd,
+    0x4318,
+    0xc044,
+    0xc047,
+    0xf01f,
+    0x8860,
+    0x8801,
+    0x7862,
+    0x6861,
+    0x7714,
+    0xca0f,
+    0x7b70,
+    0x23ca,
+    0x002c,
+    0x631f,
+    0x784f,
+    0x0825,
+    0x03e5,
+    0x7b6a,
+    0xc004,
+    0x7b70,
+    0x2600,
+    0x90ce,
+    0x7b8c,
+    0x2041,
+    0x8000,
+    0xc044,
+    0xc007,
+    0x2300,
+    0xb0db,
+    0x2041,
+    0x8000,
+    0xc047,
+    0x7185,
+    0x0cc9,
+    0x97f4,
+    0x2514,
+    0x1300,
+    0xca67,
+    0x1266,
+    0x3082,
+    0x70ed,
+    0x706c,
+    0xc343,
+    0xc346,
+    0xf02d,
+    0x626a,
+    0x120f,
+    0x308c,
+    0x2400,
+    0x108b,
+    0x7c2f,
+    0x0c3b,
+    0x12c5,
+    0x221f,
+    0x008c,
+    0xda1f,
+    0x241a,
+    0x10df,
+    0x260a,
+    0x37c0,
+    0xba61,
+    0x0a01,
+    0x0031,
+    0x262f,
+    0x3781,
+    0xc203,
+    0x2200,
+    0x87c2,
+    0xc243,
+    0xc206,
+    0x2201,
+    0x8782,
+    0xc246,
+    0xc202,
+    0x2200,
+    0x8302,
+    0x2741,
+    0x900f,
+    0xc242,
+    0x1215,
+    0x308c,
+    0x714c,
+    0xbcc4,
+    0xec06,
+    0xbc61,
+    0x0c01,
+    0x1031,
+    0x7a5b,
+    0x627a,
+    0x7b50,
+    0x08a7,
+    0x80e5,
+    0xc288,
+    0xc812,
+    0x1203,
+    0x3081,
+    0x0825,
+    0x0044,
+    0x1202,
+    0x3081,
+    0x091d,
+    0x0024,
+    0x4263,
+    0xc002,
+    0x41c3,
+    0x0047,
+    0x0004,
+    0xc041,
+    0xc003,
+    0x43c1,
+    0xc040,
+    0x0c92,
+    0xfdef,
+    0x740c,
+    0xc005,
+    0x088f,
+    0x00d0,
+    0xc002,
+    0xc104,
+    0x78e5,
+    0x79c5,
+    0x2079,
+    0x0000,
+    0x2179,
+    0x0001,
+    0x7824,
+    0x41c3,
+    0x0048,
+    0x0000,
+    0x0cbe,
+    0xfd8f,
+    0xc107,
+    0xc304,
+    0x4063,
+    0x0b7a,
+    0xfdaf,
+    0x42c1,
+    0x4608,
+    0xc003,
+    0xc106,
+    0xc202,
+    0x0b6e,
+    0xfdaf,
+    0x43e1,
+    0xc105,
+    0x0917,
+    0x0070,
+    0x4300,
+    0x2642,
+    0x13c1,
+    0x1d3f,
+    0x1042,
+    0xc105,
+    0x090b,
+    0x0090,
+    0x1d40,
+    0x10c2,
+    0x5042,
+    0xca03,
+    0x0937,
+    0x0004,
+    0xca02,
+    0x082f,
+    0x0064,
+    0x7acf,
+    0x7b6f,
+    0x41c3,
+    0x0049,
+    0x0002,
+    0x0c1e,
+    0xfdef,
+    0x740c,
+    0x1540,
+    0x1080,
+    0x153f,
+    0x10c3,
+    0x153e,
+    0x1082,
+    0xc040,
+    0x41c3,
+    0x004a,
+    0x0003,
+    0x0c02,
+    0xfdef,
+    0x740c,
+    0xca0f,
+    0x2480,
+    0x3802,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0x78e0,
+    0xc2e6,
+    0x08ca,
+    0xfe6f,
+    0x4548,
+    0x153f,
+    0x1081,
+    0x4300,
+    0x2140,
+    0x03ce,
+    0x44c9,
+    0x222f,
+    0x8307,
+    0xf20e,
+    0x785b,
+    0x60b8,
+    0x10ff,
+    0x808f,
+    0x1540,
+    0x108b,
+    0x0f11,
+    0x12e4,
+    0x7785,
+    0x10fe,
+    0x8080,
+    0x0be5,
+    0x9005,
+    0x7ccf,
+    0x0c1f,
+    0x17b5,
+    0x720c,
+    0x7894,
+    0x60b8,
+    0x88e1,
+    0x1540,
+    0x108b,
+    0x0f0f,
+    0x12e4,
+    0x71c5,
+    0x8800,
+    0x0be9,
+    0x9005,
+    0x491f,
+    0x790f,
+    0x4950,
+    0x7a0f,
+    0x4c30,
+    0x780f,
+    0x2009,
+    0x0082,
+    0xca0c,
+    0xb8c4,
+    0xe806,
+    0xb861,
+    0x0801,
+    0x0031,
+    0x7a5b,
+    0x794f,
+    0x8b00,
+    0x0907,
+    0x0005,
+    0xab40,
+    0xc6c6,
+    0x208c,
+    0x8fc3,
+    0xf209,
+    0x0821,
+    0x01d1,
+    0x41c3,
+    0x9004,
+    0x0238,
+    0x1900,
+    0x0045,
+    0xf006,
+    0x41c3,
+    0x9004,
+    0x0238,
+    0x1900,
+    0x0105,
+    0x1900,
+    0x0005,
+    0x1210,
+    0x3081,
+    0xe903,
+    0x0019,
+    0x0000,
+    0x41c3,
+    0x9018,
+    0x0064,
+    0xb100,
+    0x0059,
+    0x0020,
+    0x1902,
+    0x0005,
+    0x78e0,
+    0xc0f1,
+    0x1210,
+    0x3081,
+    0xe90a,
+    0x1236,
+    0x3702,
+    0x228c,
+    0x8010,
+    0xf793,
+    0x0e1e,
+    0xfdcf,
+    0xf019,
+    0x41c3,
+    0x9018,
+    0x0064,
+    0xda10,
+    0xb100,
+    0xba61,
+    0x0aff,
+    0x8031,
+    0x781d,
+    0xb102,
+    0x0822,
+    0x0020,
+    0x1902,
+    0x0005,
+    0xf009,
+    0x2615,
+    0x7081,
+    0x8000,
+    0x1ca8,
+    0xa100,
+    0x6a01,
+    0x1a36,
+    0x301c,
+    0xc0d1,
+    0x7ee0,
+    0x78e0,
+    0x41c3,
+    0x9018,
+    0x0008,
+    0x9100,
+    0x08ff,
+    0x801f,
+    0x195e,
+    0x0045,
+    0x9100,
+    0x0801,
+    0x001e,
+    0x7ee0,
+    0xc2e6,
+    0x4708,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0x083b,
+    0x013f,
+    0x4528,
+    0xca10,
+    0x7ef0,
+    0xe80a,
+    0xcc36,
+    0x218a,
+    0x0010,
+    0x7902,
+    0x6e02,
+    0x7030,
+    0x0da4,
+    0xfdca,
+    0x0f36,
+    0xffef,
+    0xd808,
+    0x0f72,
+    0xffef,
+    0x40e1,
+    0x70ed,
+    0xf007,
+    0x0f66,
+    0xffef,
+    0x1504,
+    0x1400,
+    0x71e5,
+    0x0ff9,
+    0x9384,
+    0xc6c6,
+    0x708d,
+    0x706c,
+    0xf009,
+    0x2100,
+    0x0680,
+    0x106e,
+    0x0081,
+    0x0915,
+    0x00a5,
+    0x7164,
+    0x4a30,
+    0x796f,
+    0x09ef,
+    0x80b4,
+    0x7a0f,
+    0xf007,
+    0x1070,
+    0x008c,
+    0x249a,
+    0x1001,
+    0x7c45,
+    0x7fe0,
+    0x788f,
+    0x78e0,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0xc1a6,
+    0x4508,
+    0x2440,
+    0x3540,
+    0xc041,
+    0x2440,
+    0x35c0,
+    0x706c,
+    0xc040,
+    0x40a1,
+    0xc243,
+    0xc142,
+    0x1c17,
+    0x30c2,
+    0x1c16,
+    0x30c2,
+    0x1c15,
+    0x30c2,
+    0x0b36,
+    0xfe2f,
+    0xc365,
+    0xc085,
+    0xc102,
+    0xc203,
+    0xc041,
+    0x2440,
+    0x3580,
+    0xc040,
+    0x40a1,
+    0x0b1e,
+    0xfe2f,
+    0x716c,
+    0x1416,
+    0x3083,
+    0x1417,
+    0x3082,
+    0xc814,
+    0x1414,
+    0x309b,
+    0x2209,
+    0x00c1,
+    0x211a,
+    0x000e,
+    0x1415,
+    0x3080,
+    0x1203,
+    0x308c,
+    0xc044,
+    0x2009,
+    0x06cf,
+    0xc818,
+    0x78ec,
+    0x661e,
+    0xc812,
+    0x083f,
+    0x0304,
+    0x1202,
+    0x308c,
+    0x0c37,
+    0x1024,
+    0x740c,
+    0x45cb,
+    0x003e,
+    0x0003,
+    0xc140,
+    0x09ce,
+    0xfdef,
+    0x41a1,
+    0xc204,
+    0x254f,
+    0x1401,
+    0x740c,
+    0x4363,
+    0x09be,
+    0xfdef,
+    0xc740,
+    0xc202,
+    0xc303,
+    0x732c,
+    0x740c,
+    0xb996,
+    0x09ae,
+    0xfdef,
+    0xc640,
+    0x40c1,
+    0xc0a6,
+    0x1404,
+    0x341b,
+    0xc6c6,
+    0xc2e6,
+    0x1cfc,
+    0xb6c8,
+    0x2482,
+    0x3411,
+    0x0f52,
+    0xfe2f,
+    0x700c,
+    0x1600,
+    0x708d,
+    0x8000,
+    0x0004,
+    0x40c3,
+    0x8000,
+    0x1b74,
+    0x702c,
+    0x0f9e,
+    0xfeef,
+    0xda28,
+    0x0eb6,
+    0xfe2f,
+    0x700c,
+    0xc046,
+    0x40c3,
+    0x8000,
+    0x06cd,
+    0x8801,
+    0x1c28,
+    0x3001,
+    0x1c2c,
+    0x3003,
+    0x205f,
+    0x0641,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x06cd,
+    0x205f,
+    0x0c80,
+    0x6119,
+    0x2100,
+    0x0f80,
+    0x8000,
+    0x0580,
+    0x1003,
+    0x00cf,
+    0xc006,
+    0x0bd2,
+    0xff6f,
+    0x702c,
+    0x251a,
+    0x1f8d,
+    0x0020,
+    0x0000,
+    0x2505,
+    0x1f80,
+    0x9002,
+    0x0092,
+    0x90c0,
+    0x2653,
+    0x115e,
+    0x0ebe,
+    0xfe2f,
+    0x200a,
+    0x0780,
+    0x4318,
+    0xf96c,
+    0xb8c5,
+    0x0eae,
+    0xfe2f,
+    0xc044,
+    0x4608,
+    0x750c,
+    0x41c3,
+    0x0095,
+    0x0001,
+    0x0906,
+    0xfdef,
+    0x220a,
+    0x0780,
+    0xc204,
+    0x41c3,
+    0x0096,
+    0x0001,
+    0x08f6,
+    0xfdef,
+    0x750c,
+    0xc006,
+    0x712c,
+    0x734c,
+    0x0d92,
+    0x0020,
+    0xc38a,
+    0x206f,
+    0x0243,
+    0x881a,
+    0x08a1,
+    0x003e,
+    0x710c,
+    0xc044,
+    0x41c3,
+    0x0097,
+    0x0000,
+    0x08d2,
+    0xfdef,
+    0x740c,
+    0x2505,
+    0x1f8d,
+    0x9003,
+    0xe090,
+    0x1d00,
+    0x1045,
+    0xf016,
+    0x41c3,
+    0x0098,
+    0x0000,
+    0x08b6,
+    0xfdef,
+    0x750c,
+    0xc207,
+    0x4063,
+    0x0dee,
+    0xffaf,
+    0x41c1,
+    0xe807,
+    0xc006,
+    0x722c,
+    0x704c,
+    0x0d46,
+    0x0020,
+    0xc38a,
+    0xc004,
+    0x7104,
+    0xc044,
+    0xc004,
+    0x780f,
+    0x08d3,
+    0x8134,
+    0xc047,
+    0x41c3,
+    0x0099,
+    0x0000,
+    0x0882,
+    0xfdef,
+    0x750c,
+    0xc22b,
+    0x4063,
+    0x0dba,
+    0xffaf,
+    0x41c1,
+    0xc02b,
+    0xe88a,
+    0x41c3,
+    0x009a,
+    0x0000,
+    0x086a,
+    0xfdef,
+    0x750c,
+    0x1d00,
+    0x1005,
+    0x41c3,
+    0x009b,
+    0x0000,
+    0x085a,
+    0xfdef,
+    0x740c,
+    0xc006,
+    0x0ae2,
+    0xff6f,
+    0x702c,
+    0xc006,
+    0x712c,
+    0x734c,
+    0x0cee,
+    0x0020,
+    0x706c,
+    0x70f5,
+    0x04c8,
+    0x002a,
+    0x2456,
+    0x3800,
+    0x1600,
+    0x7083,
+    0x8000,
+    0x0004,
+    0x702c,
+    0x0e4a,
+    0xfeef,
+    0xdab4,
+    0xc093,
+    0x0e42,
+    0xfeef,
+    0xdab4,
+    0x231a,
+    0x0f83,
+    0x0010,
+    0x0000,
+    0x1600,
+    0x7080,
+    0x8000,
+    0x0001,
+    0xc051,
+    0x700c,
+    0x048b,
+    0x0020,
+    0xc350,
+    0xc105,
+    0xc006,
+    0x2011,
+    0x8040,
+    0x0476,
+    0x0021,
+    0x702c,
+    0xc005,
+    0x780f,
+    0x0f8e,
+    0xffaf,
+    0xc04c,
+    0x4608,
+    0x2400,
+    0x3f80,
+    0x0000,
+    0x01b4,
+    0x702c,
+    0x0dfe,
+    0xfeef,
+    0xdab4,
+    0xc005,
+    0x70ad,
+    0x70ed,
+    0x2055,
+    0x0c01,
+    0xc010,
+    0x43db,
+    0x9002,
+    0x0000,
+    0x7825,
+    0xc04d,
+    0xca06,
+    0xc047,
+    0xf03b,
+    0x260a,
+    0x33c0,
+    0xf034,
+    0x251a,
+    0x1f81,
+    0x0000,
+    0x1000,
+    0x209a,
+    0x0004,
+    0x7825,
+    0xc044,
+    0xc104,
+    0xc00d,
+    0x7825,
+    0x781b,
+    0x2005,
+    0x06c0,
+    0x0fca,
+    0xfdaf,
+    0x9000,
+    0x7a1c,
+    0x2400,
+    0x3f81,
+    0x0000,
+    0x01b4,
+    0x7a5c,
+    0x2114,
+    0x0781,
+    0x7a5c,
+    0xb100,
+    0x7a5c,
+    0xd91b,
+    0xb961,
+    0x09ff,
+    0x8031,
+    0x7a5d,
+    0x7164,
+    0x6059,
+    0x2844,
+    0x0800,
+    0xb9c4,
+    0x7942,
+    0x2354,
+    0x3c82,
+    0x2640,
+    0x305e,
+    0x209a,
+    0x0010,
+    0x7905,
+    0xc004,
+    0x781b,
+    0x7845,
+    0xb020,
+    0x0b9d,
+    0x8234,
+    0x4060,
+    0x71a5,
+    0xe709,
+    0xc007,
+    0x0d8b,
+    0x9024,
+    0x706c,
+    0xc005,
+    0xc305,
+    0x41c3,
+    0x0092,
+    0x0002,
+    0x2038,
+    0x0380,
+    0x0f82,
+    0xfd6f,
+    0x42c1,
+    0x40c3,
+    0x8000,
+    0x06cd,
+    0xa8c1,
+    0x1600,
+    0x7001,
+    0x8000,
+    0x06dc,
+    0xc00c,
+    0x704c,
+    0x0982,
+    0xfeaf,
+    0x716c,
+    0x1600,
+    0x709b,
+    0x8000,
+    0x0004,
+    0x1600,
+    0x710d,
+    0x9008,
+    0x01e0,
+    0x40c1,
+    0x0eae,
+    0xfdaf,
+    0x702c,
+    0xc04e,
+    0x40c3,
+    0x0000,
+    0xffff,
+    0x4100,
+    0x4200,
+    0x0eaa,
+    0xfe2f,
+    0x4300,
+    0x40c3,
+    0x0000,
+    0xff7f,
+    0x78a4,
+    0x1e00,
+    0x7004,
+    0x9009,
+    0xe1e0,
+    0x2400,
+    0x3f80,
+    0x0000,
+    0x03f0,
+    0x41c3,
+    0x8000,
+    0x04c5,
+    0x0d5a,
+    0xfd6f,
+    0xda60,
+    0x2400,
+    0x3f80,
+    0x0000,
+    0x03f0,
+    0x0c12,
+    0x0060,
+    0xd960,
+    0xd8ff,
+    0x1e00,
+    0x7004,
+    0x9003,
+    0xf0c4,
+    0x710c,
+    0x2644,
+    0x17cd,
+    0xed05,
+    0xbd61,
+    0x0dff,
+    0x9031,
+    0x781b,
+    0x702c,
+    0x205a,
+    0x0100,
+    0x200f,
+    0x0380,
+    0x0b02,
+    0xff2f,
+    0x780f,
+    0x700c,
+    0xc048,
+    0xf00e,
+    0x6861,
+    0x7a7b,
+    0x7034,
+    0x2400,
+    0x3f81,
+    0x0000,
+    0x03d0,
+    0x22ce,
+    0x0021,
+    0x6038,
+    0xa840,
+    0x4060,
+    0x08e9,
+    0x8434,
+    0x2044,
+    0x0041,
+    0x40c3,
+    0x8000,
+    0x06cd,
+    0x1005,
+    0x009e,
+    0x40c3,
+    0x8000,
+    0x06cd,
+    0x231a,
+    0x3f9b,
+    0x0010,
+    0x0000,
+    0x8864,
+    0x4468,
+    0x1c3c,
+    0x36c0,
+    0xf03f,
+    0x70ed,
+    0xf03a,
+    0xc00e,
+    0x2055,
+    0x0c01,
+    0xc00f,
+    0x7825,
+    0x251a,
+    0x1f81,
+    0x0000,
+    0x1000,
+    0x7905,
+    0x40e1,
+    0x209a,
+    0x0004,
+    0x7825,
+    0x781b,
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+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+};
+
+ #endif
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.h
new file mode 100644
index 00000000..0ed0b329
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.h
@@ -0,0 +1,29 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_DDR_FW_PARAM_H
+#define BSP_DDR_FW_PARAM_H
+
+/***********************************************************************************************************************
+ * Includes <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include <stdio.h>
+#include "bsp_api.h"
+
+#if (BSP_FEATURE_DDR_SUPPORTED)
+ #if (1 == BSP_CFG_DDR_INIT_ENABLE)
+  #include "bsp_ddr_fw_param.h"
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+extern const uint32_t phyinit_fw_1d[];
+extern const uint32_t phyinit_fw_2d[];
+
+ #endif
+#endif
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_delay.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_delay.c
new file mode 100644
index 00000000..8d17283d
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_delay.c
@@ -0,0 +1,145 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "bsp_delay.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_DELAY_NS_PER_SECOND         (1000000000)
+#define BSP_DELAY_NS_PER_US             (1000)
+#define BSP_DELAY_SIGNIFICANT_DIGITS    (10000)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ *              Delay for at least the specified duration in units and return.
+ * @param[in]   delay  The number of 'units' to delay.
+ * @param[in]   units  The 'base' (bsp_delay_units_t) for the units specified. Valid values are:
+ *              BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n
+ *              For example:@n
+ *              At 200 MHz one cycle takes 1/200 microsecond or 5 nanoseconds.@n
+ *              At 800 MHz one cycle takes 1/800 microsecond or 1.25 nanoseconds.@n
+ *              Therefore one run through bsp_prv_software_delay_loop() takes:
+ *              ~ (1.25 * BSP_DELAY_LOOP_CYCLES) or 5 ns.
+ *              A delay of 2 us therefore requires 2000ns/5ns or 400 loops.
+ *
+ *              The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate.
+ *              @200MHz:  ((0xFFFFFFFF loops * 4 cycles /loop) / 200000000) = 85 seconds.
+ *              @800MHz:  ((0xFFFFFFFF loops * 4 cycles /loop) / 800000000) = 21 seconds.
+ *
+ *              Note that requests for very large delays will be affected by rounding in the calculations and the actual delay
+ *              achieved may be slightly longer. @200 MHz, for example, a request for 85 seconds will be closer to 86 seconds.
+ *
+ *              Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called
+ *              at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the
+ *              overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.
+ *
+ *
+ * @note R_BSP_SoftwareDelay() obtains the system clock value by reading the SystemCoreClock variable.
+ *       Therefore, R_BSP_SoftwareDelay() cannot be used until after the SystemCoreClock has been updated.
+ *       The SystemCoreClock is updated by executing SystemCoreClockUpdate() in startup;
+ *       users cannot call R_BSP_SoftwareDelay() inside R_BSP_WarmStart(BSP_WARM_START_RESET) and
+ *       R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK) since they are invoked before SystemCoreClockUpdate() in startup.
+ *
+ * @note This function will delay for **at least** the specified duration. Due to overhead in calculating the correct number
+ *       of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified.
+ *       Approximate overhead for this function is as follows:
+ *           - CR52: 87-94 cycles
+ *
+ * @note If more accurate microsecond timing must be performed in software it is recommended to use
+ *       bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE()
+ *       to convert a calculated delay cycle count to a number of software delay loops.
+ *
+ * @note Delays may be longer than expected when compiler optimization is turned off.
+ **********************************************************************************************************************/
+
+void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
+{
+    uint32_t cpu_hz;
+    uint32_t cycles_requested;
+    uint32_t ns_per_cycle;
+    uint32_t loops_required = 0;
+    uint32_t total_us       = (delay * units);                                        /** Convert the requested time to microseconds. */
+    uint64_t ns_64bits;
+
+    cpu_hz = SystemCoreClock;                                                         /** Get the system clock frequency in Hz. */
+
+    /* BSP_DELAY_SIGNIFICANT_DIGITS to keep the decimal point. */
+    ns_per_cycle = BSP_DELAY_NS_PER_SECOND / (cpu_hz / BSP_DELAY_SIGNIFICANT_DIGITS); /** Get the # of nanoseconds/cycle. */
+
+    /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */
+    /* division as that pulls in a division library. */
+    ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US;                 // Convert to ns.
+
+    /* Have we overflowed 32 bits? */
+    if (ns_64bits <= UINT32_MAX)
+    {
+        ns_64bits = ns_64bits * (uint64_t) BSP_DELAY_SIGNIFICANT_DIGITS;
+
+        /* No, we will not overflow.
+         * Multiply the calculation result by BSP_DELAY_SIGNIFICANT_DIGITS to disable the retention of the decimal point.*/
+        cycles_requested = (uint32_t) (ns_64bits / (uint64_t) ns_per_cycle);
+        loops_required   = cycles_requested / BSP_DELAY_LOOP_CYCLES;
+    }
+    else
+    {
+        /* We did overflow. Try dividing down first.
+         * Multiply the calculation result by BSP_DELAY_SIGNIFICANT_DIGITS to disable the retention of the decimal point.*/
+        total_us  = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)) * BSP_DELAY_SIGNIFICANT_DIGITS;
+        ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns.
+
+        /* Have we overflowed 32 bits? */
+        if (ns_64bits <= UINT32_MAX)
+        {
+            /* No, we will not overflow. */
+            loops_required = (uint32_t) ns_64bits;
+        }
+        else
+        {
+            /* We still overflowed, use the max count for cycles */
+            loops_required = UINT32_MAX;
+        }
+    }
+
+    /** Only delay if the supplied parameters constitute a delay. */
+    if (loops_required > (uint32_t) 0)
+    {
+        bsp_prv_software_delay_loop(loops_required);
+    }
+}
+
+/** @} (end addtogroup BSP_MCU) */
+
+/*******************************************************************************************************************//**
+ *        This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles
+ *        occur when the loop exits. The 'naked' attribute  indicates that the specified function does not need
+ *        prologue/epilogue sequences generated by the compiler.
+ * @param[in]     loop_cnt  The number of loops to iterate.
+ **********************************************************************************************************************/
+void bsp_prv_software_delay_loop (uint32_t loop_cnt)
+{
+    r_bsp_software_delay_loop(loop_cnt);
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_delay.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_delay.h
new file mode 100644
index 00000000..3a96f4ac
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_delay.h
@@ -0,0 +1,59 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_DELAY_H
+#define BSP_DELAY_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#if defined(BSP_CFG_CORE_CR52)
+ #include "cr/bsp_delay_core.h"
+#elif defined(BSP_CFG_CORE_CA55)
+ #include "ca/bsp_delay_core.h"
+#endif
+
+#include "bsp_compiler_support.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */
+typedef enum
+{
+    BSP_DELAY_UNITS_SECONDS      = 1000000, ///< Requested delay amount is in seconds
+    BSP_DELAY_UNITS_MILLISECONDS = 1000,    ///< Requested delay amount is in milliseconds
+    BSP_DELAY_UNITS_MICROSECONDS = 1        ///< Requested delay amount is in microseconds
+} bsp_delay_units_t;
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+void bsp_prv_software_delay_loop(uint32_t loop_cnt);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h
new file mode 100644
index 00000000..bd53a406
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h
@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_EXCEPTIONS_H
+#define BSP_EXCEPTIONS_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_io.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_io.c
new file mode 100644
index 00000000..4a33b6c4
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_io.c
@@ -0,0 +1,27 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+volatile uint32_t g_protect_port_counter;
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_io.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_io.h
new file mode 100644
index 00000000..00986a95
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_io.h
@@ -0,0 +1,713 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @defgroup BSP_IO BSP I/O access
+ * @ingroup RENESAS_COMMON
+ * @brief This module provides basic read/write/toggle access to port pins and read/write access to port.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BSP_IO_H
+#define BSP_IO_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Private definition to set enumeration values. */
+#define BSP_IO_PRV_8BIT_MASK       (0xFF)
+#define BSP_IO_PM_OUTPUT           (3U)
+
+/* Key code for writing PRCR register. */
+#define BSP_IO_PRV_PRCR_KEY        (0xA500U)
+#define BSP_IO_REG_PROTECT_GPIO    (0x0004U)
+
+/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
+#define BSP_IO_PRV_PORT_OFFSET     (8U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Levels that can be set and read for individual pins */
+typedef enum e_bsp_io_level
+{
+    BSP_IO_LEVEL_LOW = 0,              ///< Low
+    BSP_IO_LEVEL_HIGH                  ///< High
+} bsp_io_level_t;
+
+/** Direction of individual pins */
+typedef enum e_bsp_io_dir
+{
+    BSP_IO_DIRECTION_INPUT = 0,        ///< Input
+    BSP_IO_DIRECTION_OUTPUT            ///< Output
+} bsp_io_direction_t;
+
+/** Superset list of all possible IO ports. */
+typedef enum e_bsp_io_port
+{
+    BSP_IO_PORT_00 = 0x0000,           ///< IO port 0
+    BSP_IO_PORT_01 = 0x0100,           ///< IO port 1
+    BSP_IO_PORT_02 = 0x0200,           ///< IO port 2
+    BSP_IO_PORT_03 = 0x0300,           ///< IO port 3
+    BSP_IO_PORT_04 = 0x0400,           ///< IO port 4
+    BSP_IO_PORT_05 = 0x0500,           ///< IO port 5
+    BSP_IO_PORT_06 = 0x0600,           ///< IO port 6
+    BSP_IO_PORT_07 = 0x0700,           ///< IO port 7
+    BSP_IO_PORT_08 = 0x0800,           ///< IO port 8
+    BSP_IO_PORT_09 = 0x0900,           ///< IO port 9
+    BSP_IO_PORT_10 = 0x0A00,           ///< IO port 10
+    BSP_IO_PORT_11 = 0x0B00,           ///< IO port 11
+    BSP_IO_PORT_12 = 0x0C00,           ///< IO port 12
+    BSP_IO_PORT_13 = 0x0D00,           ///< IO port 13
+    BSP_IO_PORT_14 = 0x0E00,           ///< IO port 14
+    BSP_IO_PORT_15 = 0x0F00,           ///< IO port 15
+    BSP_IO_PORT_16 = 0x1000,           ///< IO port 16
+    BSP_IO_PORT_17 = 0x1100,           ///< IO port 17
+    BSP_IO_PORT_18 = 0x1200,           ///< IO port 18
+    BSP_IO_PORT_19 = 0x1300,           ///< IO port 19
+    BSP_IO_PORT_20 = 0x1400,           ///< IO port 20
+    BSP_IO_PORT_21 = 0x1500,           ///< IO port 21
+    BSP_IO_PORT_22 = 0x1600,           ///< IO port 22
+    BSP_IO_PORT_23 = 0x1700,           ///< IO port 23
+    BSP_IO_PORT_24 = 0x1800,           ///< IO port 24
+    BSP_IO_PORT_25 = 0x1900,           ///< IO port 25
+    BSP_IO_PORT_26 = 0x1A00,           ///< IO port 26
+    BSP_IO_PORT_27 = 0x1B00,           ///< IO port 27
+    BSP_IO_PORT_29 = 0x1D00,           ///< IO port 29
+    BSP_IO_PORT_30 = 0x1E00,           ///< IO port 30
+    BSP_IO_PORT_31 = 0x1F00,           ///< IO port 31
+    BSP_IO_PORT_33 = 0x2100,           ///< IO port 33
+    BSP_IO_PORT_34 = 0x2200,           ///< IO port 34
+} bsp_io_port_t;
+
+/** Superset list of all possible IO port pins. */
+typedef enum e_bsp_io_port_pin
+{
+    BSP_IO_PORT_00_PIN_0 = 0x0000,     ///< IO port 0 pin 0
+    BSP_IO_PORT_00_PIN_1 = 0x0001,     ///< IO port 0 pin 1
+    BSP_IO_PORT_00_PIN_2 = 0x0002,     ///< IO port 0 pin 2
+    BSP_IO_PORT_00_PIN_3 = 0x0003,     ///< IO port 0 pin 3
+    BSP_IO_PORT_00_PIN_4 = 0x0004,     ///< IO port 0 pin 4
+    BSP_IO_PORT_00_PIN_5 = 0x0005,     ///< IO port 0 pin 5
+    BSP_IO_PORT_00_PIN_6 = 0x0006,     ///< IO port 0 pin 6
+    BSP_IO_PORT_00_PIN_7 = 0x0007,     ///< IO port 0 pin 7
+
+    BSP_IO_PORT_01_PIN_0 = 0x0100,     ///< IO port 1 pin 0
+    BSP_IO_PORT_01_PIN_1 = 0x0101,     ///< IO port 1 pin 1
+    BSP_IO_PORT_01_PIN_2 = 0x0102,     ///< IO port 1 pin 2
+    BSP_IO_PORT_01_PIN_3 = 0x0103,     ///< IO port 1 pin 3
+    BSP_IO_PORT_01_PIN_4 = 0x0104,     ///< IO port 1 pin 4
+    BSP_IO_PORT_01_PIN_5 = 0x0105,     ///< IO port 1 pin 5
+    BSP_IO_PORT_01_PIN_6 = 0x0106,     ///< IO port 1 pin 6
+    BSP_IO_PORT_01_PIN_7 = 0x0107,     ///< IO port 1 pin 7
+
+    BSP_IO_PORT_02_PIN_0 = 0x0200,     ///< IO port 2 pin 0
+    BSP_IO_PORT_02_PIN_1 = 0x0201,     ///< IO port 2 pin 1
+    BSP_IO_PORT_02_PIN_2 = 0x0202,     ///< IO port 2 pin 2
+    BSP_IO_PORT_02_PIN_3 = 0x0203,     ///< IO port 2 pin 3
+    BSP_IO_PORT_02_PIN_4 = 0x0204,     ///< IO port 2 pin 4
+    BSP_IO_PORT_02_PIN_5 = 0x0205,     ///< IO port 2 pin 5
+    BSP_IO_PORT_02_PIN_6 = 0x0206,     ///< IO port 2 pin 6
+    BSP_IO_PORT_02_PIN_7 = 0x0207,     ///< IO port 2 pin 7
+
+    BSP_IO_PORT_03_PIN_0 = 0x0300,     ///< IO port 3 pin 0
+    BSP_IO_PORT_03_PIN_1 = 0x0301,     ///< IO port 3 pin 1
+    BSP_IO_PORT_03_PIN_2 = 0x0302,     ///< IO port 3 pin 2
+    BSP_IO_PORT_03_PIN_3 = 0x0303,     ///< IO port 3 pin 3
+    BSP_IO_PORT_03_PIN_4 = 0x0304,     ///< IO port 3 pin 4
+    BSP_IO_PORT_03_PIN_5 = 0x0305,     ///< IO port 3 pin 5
+    BSP_IO_PORT_03_PIN_6 = 0x0306,     ///< IO port 3 pin 6
+    BSP_IO_PORT_03_PIN_7 = 0x0307,     ///< IO port 3 pin 7
+
+    BSP_IO_PORT_04_PIN_0 = 0x0400,     ///< IO port 4 pin 0
+    BSP_IO_PORT_04_PIN_1 = 0x0401,     ///< IO port 4 pin 1
+    BSP_IO_PORT_04_PIN_2 = 0x0402,     ///< IO port 4 pin 2
+    BSP_IO_PORT_04_PIN_3 = 0x0403,     ///< IO port 4 pin 3
+    BSP_IO_PORT_04_PIN_4 = 0x0404,     ///< IO port 4 pin 4
+    BSP_IO_PORT_04_PIN_5 = 0x0405,     ///< IO port 4 pin 5
+    BSP_IO_PORT_04_PIN_6 = 0x0406,     ///< IO port 4 pin 6
+    BSP_IO_PORT_04_PIN_7 = 0x0407,     ///< IO port 4 pin 7
+
+    BSP_IO_PORT_05_PIN_0 = 0x0500,     ///< IO port 5 pin 0
+    BSP_IO_PORT_05_PIN_1 = 0x0501,     ///< IO port 5 pin 1
+    BSP_IO_PORT_05_PIN_2 = 0x0502,     ///< IO port 5 pin 2
+    BSP_IO_PORT_05_PIN_3 = 0x0503,     ///< IO port 5 pin 3
+    BSP_IO_PORT_05_PIN_4 = 0x0504,     ///< IO port 5 pin 4
+    BSP_IO_PORT_05_PIN_5 = 0x0505,     ///< IO port 5 pin 5
+    BSP_IO_PORT_05_PIN_6 = 0x0506,     ///< IO port 5 pin 6
+    BSP_IO_PORT_05_PIN_7 = 0x0507,     ///< IO port 5 pin 7
+
+    BSP_IO_PORT_06_PIN_0 = 0x0600,     ///< IO port 6 pin 0
+    BSP_IO_PORT_06_PIN_1 = 0x0601,     ///< IO port 6 pin 1
+    BSP_IO_PORT_06_PIN_2 = 0x0602,     ///< IO port 6 pin 2
+    BSP_IO_PORT_06_PIN_3 = 0x0603,     ///< IO port 6 pin 3
+    BSP_IO_PORT_06_PIN_4 = 0x0604,     ///< IO port 6 pin 4
+    BSP_IO_PORT_06_PIN_5 = 0x0605,     ///< IO port 6 pin 5
+    BSP_IO_PORT_06_PIN_6 = 0x0606,     ///< IO port 6 pin 6
+    BSP_IO_PORT_06_PIN_7 = 0x0607,     ///< IO port 6 pin 7
+
+    BSP_IO_PORT_07_PIN_0 = 0x0700,     ///< IO port 7 pin 0
+    BSP_IO_PORT_07_PIN_1 = 0x0701,     ///< IO port 7 pin 1
+    BSP_IO_PORT_07_PIN_2 = 0x0702,     ///< IO port 7 pin 2
+    BSP_IO_PORT_07_PIN_3 = 0x0703,     ///< IO port 7 pin 3
+    BSP_IO_PORT_07_PIN_4 = 0x0704,     ///< IO port 7 pin 4
+    BSP_IO_PORT_07_PIN_5 = 0x0705,     ///< IO port 7 pin 5
+    BSP_IO_PORT_07_PIN_6 = 0x0706,     ///< IO port 7 pin 6
+    BSP_IO_PORT_07_PIN_7 = 0x0707,     ///< IO port 7 pin 7
+
+    BSP_IO_PORT_08_PIN_0 = 0x0800,     ///< IO port 8 pin 0
+    BSP_IO_PORT_08_PIN_1 = 0x0801,     ///< IO port 8 pin 1
+    BSP_IO_PORT_08_PIN_2 = 0x0802,     ///< IO port 8 pin 2
+    BSP_IO_PORT_08_PIN_3 = 0x0803,     ///< IO port 8 pin 3
+    BSP_IO_PORT_08_PIN_4 = 0x0804,     ///< IO port 8 pin 4
+    BSP_IO_PORT_08_PIN_5 = 0x0805,     ///< IO port 8 pin 5
+    BSP_IO_PORT_08_PIN_6 = 0x0806,     ///< IO port 8 pin 6
+    BSP_IO_PORT_08_PIN_7 = 0x0807,     ///< IO port 8 pin 7
+
+    BSP_IO_PORT_09_PIN_0 = 0x0900,     ///< IO port 9 pin 0
+    BSP_IO_PORT_09_PIN_1 = 0x0901,     ///< IO port 9 pin 1
+    BSP_IO_PORT_09_PIN_2 = 0x0902,     ///< IO port 9 pin 2
+    BSP_IO_PORT_09_PIN_3 = 0x0903,     ///< IO port 9 pin 3
+    BSP_IO_PORT_09_PIN_4 = 0x0904,     ///< IO port 9 pin 4
+    BSP_IO_PORT_09_PIN_5 = 0x0905,     ///< IO port 9 pin 5
+    BSP_IO_PORT_09_PIN_6 = 0x0906,     ///< IO port 9 pin 6
+    BSP_IO_PORT_09_PIN_7 = 0x0907,     ///< IO port 9 pin 7
+
+    BSP_IO_PORT_10_PIN_0 = 0x0A00,     ///< IO port 10 pin 0
+    BSP_IO_PORT_10_PIN_1 = 0x0A01,     ///< IO port 10 pin 1
+    BSP_IO_PORT_10_PIN_2 = 0x0A02,     ///< IO port 10 pin 2
+    BSP_IO_PORT_10_PIN_3 = 0x0A03,     ///< IO port 10 pin 3
+    BSP_IO_PORT_10_PIN_4 = 0x0A04,     ///< IO port 10 pin 4
+    BSP_IO_PORT_10_PIN_5 = 0x0A05,     ///< IO port 10 pin 5
+    BSP_IO_PORT_10_PIN_6 = 0x0A06,     ///< IO port 10 pin 6
+    BSP_IO_PORT_10_PIN_7 = 0x0A07,     ///< IO port 10 pin 7
+
+    BSP_IO_PORT_11_PIN_0 = 0x0B00,     ///< IO port 11 pin 0
+    BSP_IO_PORT_11_PIN_1 = 0x0B01,     ///< IO port 11 pin 1
+    BSP_IO_PORT_11_PIN_2 = 0x0B02,     ///< IO port 11 pin 2
+    BSP_IO_PORT_11_PIN_3 = 0x0B03,     ///< IO port 11 pin 3
+    BSP_IO_PORT_11_PIN_4 = 0x0B04,     ///< IO port 11 pin 4
+    BSP_IO_PORT_11_PIN_5 = 0x0B05,     ///< IO port 11 pin 5
+    BSP_IO_PORT_11_PIN_6 = 0x0B06,     ///< IO port 11 pin 6
+    BSP_IO_PORT_11_PIN_7 = 0x0B07,     ///< IO port 11 pin 7
+
+    BSP_IO_PORT_12_PIN_0 = 0x0C00,     ///< IO port 12 pin 0
+    BSP_IO_PORT_12_PIN_1 = 0x0C01,     ///< IO port 12 pin 1
+    BSP_IO_PORT_12_PIN_2 = 0x0C02,     ///< IO port 12 pin 2
+    BSP_IO_PORT_12_PIN_3 = 0x0C03,     ///< IO port 12 pin 3
+    BSP_IO_PORT_12_PIN_4 = 0x0C04,     ///< IO port 12 pin 4
+    BSP_IO_PORT_12_PIN_5 = 0x0C05,     ///< IO port 12 pin 5
+    BSP_IO_PORT_12_PIN_6 = 0x0C06,     ///< IO port 12 pin 6
+    BSP_IO_PORT_12_PIN_7 = 0x0C07,     ///< IO port 12 pin 7
+
+    BSP_IO_PORT_13_PIN_0 = 0x0D00,     ///< IO port 13 pin 0
+    BSP_IO_PORT_13_PIN_1 = 0x0D01,     ///< IO port 13 pin 1
+    BSP_IO_PORT_13_PIN_2 = 0x0D02,     ///< IO port 13 pin 2
+    BSP_IO_PORT_13_PIN_3 = 0x0D03,     ///< IO port 13 pin 3
+    BSP_IO_PORT_13_PIN_4 = 0x0D04,     ///< IO port 13 pin 4
+    BSP_IO_PORT_13_PIN_5 = 0x0D05,     ///< IO port 13 pin 5
+    BSP_IO_PORT_13_PIN_6 = 0x0D06,     ///< IO port 13 pin 6
+    BSP_IO_PORT_13_PIN_7 = 0x0D07,     ///< IO port 13 pin 7
+
+    BSP_IO_PORT_14_PIN_0 = 0x0E00,     ///< IO port 14 pin 0
+    BSP_IO_PORT_14_PIN_1 = 0x0E01,     ///< IO port 14 pin 1
+    BSP_IO_PORT_14_PIN_2 = 0x0E02,     ///< IO port 14 pin 2
+    BSP_IO_PORT_14_PIN_3 = 0x0E03,     ///< IO port 14 pin 3
+    BSP_IO_PORT_14_PIN_4 = 0x0E04,     ///< IO port 14 pin 4
+    BSP_IO_PORT_14_PIN_5 = 0x0E05,     ///< IO port 14 pin 5
+    BSP_IO_PORT_14_PIN_6 = 0x0E06,     ///< IO port 14 pin 6
+    BSP_IO_PORT_14_PIN_7 = 0x0E07,     ///< IO port 14 pin 7
+
+    BSP_IO_PORT_15_PIN_0 = 0x0F00,     ///< IO port 15 pin 0
+    BSP_IO_PORT_15_PIN_1 = 0x0F01,     ///< IO port 15 pin 1
+    BSP_IO_PORT_15_PIN_2 = 0x0F02,     ///< IO port 15 pin 2
+    BSP_IO_PORT_15_PIN_3 = 0x0F03,     ///< IO port 15 pin 3
+    BSP_IO_PORT_15_PIN_4 = 0x0F04,     ///< IO port 15 pin 4
+    BSP_IO_PORT_15_PIN_5 = 0x0F05,     ///< IO port 15 pin 5
+    BSP_IO_PORT_15_PIN_6 = 0x0F06,     ///< IO port 15 pin 6
+    BSP_IO_PORT_15_PIN_7 = 0x0F07,     ///< IO port 15 pin 7
+
+    BSP_IO_PORT_16_PIN_0 = 0x1000,     ///< IO port 16 pin 0
+    BSP_IO_PORT_16_PIN_1 = 0x1001,     ///< IO port 16 pin 1
+    BSP_IO_PORT_16_PIN_2 = 0x1002,     ///< IO port 16 pin 2
+    BSP_IO_PORT_16_PIN_3 = 0x1003,     ///< IO port 16 pin 3
+    BSP_IO_PORT_16_PIN_4 = 0x1004,     ///< IO port 16 pin 4
+    BSP_IO_PORT_16_PIN_5 = 0x1005,     ///< IO port 16 pin 5
+    BSP_IO_PORT_16_PIN_6 = 0x1006,     ///< IO port 16 pin 6
+    BSP_IO_PORT_16_PIN_7 = 0x1007,     ///< IO port 16 pin 7
+
+    BSP_IO_PORT_17_PIN_0 = 0x1100,     ///< IO port 17 pin 0
+    BSP_IO_PORT_17_PIN_1 = 0x1101,     ///< IO port 17 pin 1
+    BSP_IO_PORT_17_PIN_2 = 0x1102,     ///< IO port 17 pin 2
+    BSP_IO_PORT_17_PIN_3 = 0x1103,     ///< IO port 17 pin 3
+    BSP_IO_PORT_17_PIN_4 = 0x1104,     ///< IO port 17 pin 4
+    BSP_IO_PORT_17_PIN_5 = 0x1105,     ///< IO port 17 pin 5
+    BSP_IO_PORT_17_PIN_6 = 0x1106,     ///< IO port 17 pin 6
+    BSP_IO_PORT_17_PIN_7 = 0x1107,     ///< IO port 17 pin 7
+
+    BSP_IO_PORT_18_PIN_0 = 0x1200,     ///< IO port 18 pin 0
+    BSP_IO_PORT_18_PIN_1 = 0x1201,     ///< IO port 18 pin 1
+    BSP_IO_PORT_18_PIN_2 = 0x1202,     ///< IO port 18 pin 2
+    BSP_IO_PORT_18_PIN_3 = 0x1203,     ///< IO port 18 pin 3
+    BSP_IO_PORT_18_PIN_4 = 0x1204,     ///< IO port 18 pin 4
+    BSP_IO_PORT_18_PIN_5 = 0x1205,     ///< IO port 18 pin 5
+    BSP_IO_PORT_18_PIN_6 = 0x1206,     ///< IO port 18 pin 6
+    BSP_IO_PORT_18_PIN_7 = 0x1207,     ///< IO port 18 pin 7
+
+    BSP_IO_PORT_19_PIN_0 = 0x1300,     ///< IO port 19 pin 0
+    BSP_IO_PORT_19_PIN_1 = 0x1301,     ///< IO port 19 pin 1
+    BSP_IO_PORT_19_PIN_2 = 0x1302,     ///< IO port 19 pin 2
+    BSP_IO_PORT_19_PIN_3 = 0x1303,     ///< IO port 19 pin 3
+    BSP_IO_PORT_19_PIN_4 = 0x1304,     ///< IO port 19 pin 4
+    BSP_IO_PORT_19_PIN_5 = 0x1305,     ///< IO port 19 pin 5
+    BSP_IO_PORT_19_PIN_6 = 0x1306,     ///< IO port 19 pin 6
+    BSP_IO_PORT_19_PIN_7 = 0x1307,     ///< IO port 19 pin 7
+
+    BSP_IO_PORT_20_PIN_0 = 0x1400,     ///< IO port 20 pin 0
+    BSP_IO_PORT_20_PIN_1 = 0x1401,     ///< IO port 20 pin 1
+    BSP_IO_PORT_20_PIN_2 = 0x1402,     ///< IO port 20 pin 2
+    BSP_IO_PORT_20_PIN_3 = 0x1403,     ///< IO port 20 pin 3
+    BSP_IO_PORT_20_PIN_4 = 0x1404,     ///< IO port 20 pin 4
+    BSP_IO_PORT_20_PIN_5 = 0x1405,     ///< IO port 20 pin 5
+    BSP_IO_PORT_20_PIN_6 = 0x1406,     ///< IO port 20 pin 6
+    BSP_IO_PORT_20_PIN_7 = 0x1407,     ///< IO port 20 pin 7
+
+    BSP_IO_PORT_21_PIN_0 = 0x1500,     ///< IO port 21 pin 0
+    BSP_IO_PORT_21_PIN_1 = 0x1501,     ///< IO port 21 pin 1
+    BSP_IO_PORT_21_PIN_2 = 0x1502,     ///< IO port 21 pin 2
+    BSP_IO_PORT_21_PIN_3 = 0x1503,     ///< IO port 21 pin 3
+    BSP_IO_PORT_21_PIN_4 = 0x1504,     ///< IO port 21 pin 4
+    BSP_IO_PORT_21_PIN_5 = 0x1505,     ///< IO port 21 pin 5
+    BSP_IO_PORT_21_PIN_6 = 0x1506,     ///< IO port 21 pin 6
+    BSP_IO_PORT_21_PIN_7 = 0x1507,     ///< IO port 21 pin 7
+
+    BSP_IO_PORT_22_PIN_0 = 0x1600,     ///< IO port 22 pin 0
+    BSP_IO_PORT_22_PIN_1 = 0x1601,     ///< IO port 22 pin 1
+    BSP_IO_PORT_22_PIN_2 = 0x1602,     ///< IO port 22 pin 2
+    BSP_IO_PORT_22_PIN_3 = 0x1603,     ///< IO port 22 pin 3
+    BSP_IO_PORT_22_PIN_4 = 0x1604,     ///< IO port 22 pin 4
+    BSP_IO_PORT_22_PIN_5 = 0x1605,     ///< IO port 22 pin 5
+    BSP_IO_PORT_22_PIN_6 = 0x1606,     ///< IO port 22 pin 6
+    BSP_IO_PORT_22_PIN_7 = 0x1607,     ///< IO port 22 pin 7
+
+    BSP_IO_PORT_23_PIN_0 = 0x1700,     ///< IO port 23 pin 0
+    BSP_IO_PORT_23_PIN_1 = 0x1701,     ///< IO port 23 pin 1
+    BSP_IO_PORT_23_PIN_2 = 0x1702,     ///< IO port 23 pin 2
+    BSP_IO_PORT_23_PIN_3 = 0x1703,     ///< IO port 23 pin 3
+    BSP_IO_PORT_23_PIN_4 = 0x1704,     ///< IO port 23 pin 4
+    BSP_IO_PORT_23_PIN_5 = 0x1705,     ///< IO port 23 pin 5
+    BSP_IO_PORT_23_PIN_6 = 0x1706,     ///< IO port 23 pin 6
+    BSP_IO_PORT_23_PIN_7 = 0x1707,     ///< IO port 23 pin 7
+
+    BSP_IO_PORT_24_PIN_0 = 0x1800,     ///< IO port 24 pin 0
+    BSP_IO_PORT_24_PIN_1 = 0x1801,     ///< IO port 24 pin 1
+    BSP_IO_PORT_24_PIN_2 = 0x1802,     ///< IO port 24 pin 2
+    BSP_IO_PORT_24_PIN_3 = 0x1803,     ///< IO port 24 pin 3
+    BSP_IO_PORT_24_PIN_4 = 0x1804,     ///< IO port 24 pin 4
+    BSP_IO_PORT_24_PIN_5 = 0x1805,     ///< IO port 24 pin 5
+    BSP_IO_PORT_24_PIN_6 = 0x1806,     ///< IO port 24 pin 6
+    BSP_IO_PORT_24_PIN_7 = 0x1807,     ///< IO port 24 pin 7
+
+    BSP_IO_PORT_25_PIN_0 = 0x1900,     ///< IO port 25 pin 0
+    BSP_IO_PORT_25_PIN_1 = 0x1901,     ///< IO port 25 pin 1
+    BSP_IO_PORT_25_PIN_2 = 0x1902,     ///< IO port 25 pin 2
+    BSP_IO_PORT_25_PIN_3 = 0x1903,     ///< IO port 25 pin 3
+    BSP_IO_PORT_25_PIN_4 = 0x1904,     ///< IO port 25 pin 4
+    BSP_IO_PORT_25_PIN_5 = 0x1905,     ///< IO port 25 pin 5
+    BSP_IO_PORT_25_PIN_6 = 0x1906,     ///< IO port 25 pin 6
+    BSP_IO_PORT_25_PIN_7 = 0x1907,     ///< IO port 25 pin 7
+
+    BSP_IO_PORT_26_PIN_0 = 0x1A00,     ///< IO port 26 pin 0
+    BSP_IO_PORT_26_PIN_1 = 0x1A01,     ///< IO port 26 pin 1
+    BSP_IO_PORT_26_PIN_2 = 0x1A02,     ///< IO port 26 pin 2
+    BSP_IO_PORT_26_PIN_3 = 0x1A03,     ///< IO port 26 pin 3
+    BSP_IO_PORT_26_PIN_4 = 0x1A04,     ///< IO port 26 pin 4
+    BSP_IO_PORT_26_PIN_5 = 0x1A05,     ///< IO port 26 pin 5
+    BSP_IO_PORT_26_PIN_6 = 0x1A06,     ///< IO port 26 pin 6
+    BSP_IO_PORT_26_PIN_7 = 0x1A07,     ///< IO port 26 pin 7
+
+    BSP_IO_PORT_27_PIN_0 = 0x1B00,     ///< IO port 27 pin 0
+    BSP_IO_PORT_27_PIN_1 = 0x1B01,     ///< IO port 27 pin 1
+    BSP_IO_PORT_27_PIN_2 = 0x1B02,     ///< IO port 27 pin 2
+    BSP_IO_PORT_27_PIN_3 = 0x1B03,     ///< IO port 27 pin 3
+    BSP_IO_PORT_27_PIN_4 = 0x1B04,     ///< IO port 27 pin 4
+    BSP_IO_PORT_27_PIN_5 = 0x1B05,     ///< IO port 27 pin 5
+    BSP_IO_PORT_27_PIN_6 = 0x1B06,     ///< IO port 27 pin 6
+    BSP_IO_PORT_27_PIN_7 = 0x1B07,     ///< IO port 27 pin 7
+
+    BSP_IO_PORT_28_PIN_0 = 0x1C00,     ///< IO port 28 pin 0
+    BSP_IO_PORT_28_PIN_1 = 0x1C01,     ///< IO port 28 pin 1
+    BSP_IO_PORT_28_PIN_2 = 0x1C02,     ///< IO port 28 pin 2
+    BSP_IO_PORT_28_PIN_3 = 0x1C03,     ///< IO port 28 pin 3
+    BSP_IO_PORT_28_PIN_4 = 0x1C04,     ///< IO port 28 pin 4
+    BSP_IO_PORT_28_PIN_5 = 0x1C05,     ///< IO port 28 pin 5
+    BSP_IO_PORT_28_PIN_6 = 0x1C06,     ///< IO port 28 pin 6
+    BSP_IO_PORT_28_PIN_7 = 0x1C07,     ///< IO port 28 pin 7
+
+    BSP_IO_PORT_29_PIN_0 = 0x1D00,     ///< IO port 29 pin 0
+    BSP_IO_PORT_29_PIN_1 = 0x1D01,     ///< IO port 29 pin 1
+    BSP_IO_PORT_29_PIN_2 = 0x1D02,     ///< IO port 29 pin 2
+    BSP_IO_PORT_29_PIN_3 = 0x1D03,     ///< IO port 29 pin 3
+    BSP_IO_PORT_29_PIN_4 = 0x1D04,     ///< IO port 29 pin 4
+    BSP_IO_PORT_29_PIN_5 = 0x1D05,     ///< IO port 29 pin 5
+    BSP_IO_PORT_29_PIN_6 = 0x1D06,     ///< IO port 29 pin 6
+    BSP_IO_PORT_29_PIN_7 = 0x1D07,     ///< IO port 29 pin 7
+
+    BSP_IO_PORT_30_PIN_0 = 0x1E00,     ///< IO port 30 pin 0
+    BSP_IO_PORT_30_PIN_1 = 0x1E01,     ///< IO port 30 pin 1
+    BSP_IO_PORT_30_PIN_2 = 0x1E02,     ///< IO port 30 pin 2
+    BSP_IO_PORT_30_PIN_3 = 0x1E03,     ///< IO port 30 pin 3
+    BSP_IO_PORT_30_PIN_4 = 0x1E04,     ///< IO port 30 pin 4
+    BSP_IO_PORT_30_PIN_5 = 0x1E05,     ///< IO port 30 pin 5
+    BSP_IO_PORT_30_PIN_6 = 0x1E06,     ///< IO port 30 pin 6
+    BSP_IO_PORT_30_PIN_7 = 0x1E07,     ///< IO port 30 pin 7
+
+    BSP_IO_PORT_31_PIN_0 = 0x1F00,     ///< IO port 31 pin 0
+    BSP_IO_PORT_31_PIN_1 = 0x1F01,     ///< IO port 31 pin 1
+    BSP_IO_PORT_31_PIN_2 = 0x1F02,     ///< IO port 31 pin 2
+    BSP_IO_PORT_31_PIN_3 = 0x1F03,     ///< IO port 31 pin 3
+    BSP_IO_PORT_31_PIN_4 = 0x1F04,     ///< IO port 31 pin 4
+    BSP_IO_PORT_31_PIN_5 = 0x1F05,     ///< IO port 31 pin 5
+    BSP_IO_PORT_31_PIN_6 = 0x1F06,     ///< IO port 31 pin 6
+    BSP_IO_PORT_31_PIN_7 = 0x1F07,     ///< IO port 31 pin 7
+
+    BSP_IO_PORT_32_PIN_0 = 0x2000,     ///< IO port 32 pin 0
+    BSP_IO_PORT_32_PIN_1 = 0x2001,     ///< IO port 32 pin 1
+    BSP_IO_PORT_32_PIN_2 = 0x2002,     ///< IO port 32 pin 2
+    BSP_IO_PORT_32_PIN_3 = 0x2003,     ///< IO port 32 pin 3
+    BSP_IO_PORT_32_PIN_4 = 0x2004,     ///< IO port 32 pin 4
+    BSP_IO_PORT_32_PIN_5 = 0x2005,     ///< IO port 32 pin 5
+    BSP_IO_PORT_32_PIN_6 = 0x2006,     ///< IO port 32 pin 6
+    BSP_IO_PORT_32_PIN_7 = 0x2007,     ///< IO port 32 pin 7
+
+    BSP_IO_PORT_33_PIN_0 = 0x2100,     ///< IO port 33 pin 0
+    BSP_IO_PORT_33_PIN_1 = 0x2101,     ///< IO port 33 pin 1
+    BSP_IO_PORT_33_PIN_2 = 0x2102,     ///< IO port 33 pin 2
+    BSP_IO_PORT_33_PIN_3 = 0x2103,     ///< IO port 33 pin 3
+    BSP_IO_PORT_33_PIN_4 = 0x2104,     ///< IO port 33 pin 4
+    BSP_IO_PORT_33_PIN_5 = 0x2105,     ///< IO port 33 pin 5
+    BSP_IO_PORT_33_PIN_6 = 0x2106,     ///< IO port 33 pin 6
+    BSP_IO_PORT_33_PIN_7 = 0x2107,     ///< IO port 33 pin 7
+
+    BSP_IO_PORT_34_PIN_0 = 0x2200,     ///< IO port 34 pin 0
+    BSP_IO_PORT_34_PIN_1 = 0x2201,     ///< IO port 34 pin 1
+    BSP_IO_PORT_34_PIN_2 = 0x2202,     ///< IO port 34 pin 2
+    BSP_IO_PORT_34_PIN_3 = 0x2203,     ///< IO port 34 pin 3
+    BSP_IO_PORT_34_PIN_4 = 0x2204,     ///< IO port 34 pin 4
+    BSP_IO_PORT_34_PIN_5 = 0x2205,     ///< IO port 34 pin 5
+    BSP_IO_PORT_34_PIN_6 = 0x2206,     ///< IO port 34 pin 6
+    BSP_IO_PORT_34_PIN_7 = 0x2207,     ///< IO port 34 pin 7
+} bsp_io_port_pin_t;
+
+/** Offset for pin safety region access */
+typedef enum e_bsp_io_region
+{
+    BSP_IO_REGION_NOT_SAFE           = 0,                                                 ///< Non safety region
+    BSP_IO_REGION_SAFE               = BSP_FEATURE_BSP_IO_REGION_ADDRESS_DIFF_SELECTABLE, ///< Safety region
+    BSP_IO_REGION_NOT_SAFE_DEDICATED = BSP_FEATURE_BSP_IO_REGION_ADDRESS_DIFF_DEDICATED,  ///< Non safety dedicated region
+} bsp_io_region_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+extern volatile uint32_t g_protect_port_counter;
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Inline Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Set the output level of the pin in the specified region.
+ *
+ * @param[in]  region          The target IO region
+ * @param[in]  pin             The pin
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinSet (bsp_io_region_t region, bsp_io_port_pin_t pin)
+{
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (region == BSP_IO_REGION_NOT_SAFE_DEDICATED)
+    {
+        /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
+         * the right side. */
+        R_PORT_NSR->P[pin >> 8] |=
+            (uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK));
+    }
+    else
+#endif
+    {
+        /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
+         * the right side. */
+        ((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->P[pin >>
+                                                                                             BSP_IO_PRV_PORT_OFFSET] |=
+            (uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK));
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Clear the output level of the pin in the specified region.
+ *
+ * @param[in]  region          The target IO region
+ * @param[in]  pin             The pin
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinClear (bsp_io_region_t region, bsp_io_port_pin_t pin)
+{
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (region == BSP_IO_REGION_NOT_SAFE_DEDICATED)
+    {
+        /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
+         * the right side. */
+        R_PORT_NSR->P[pin >> 8] &=
+            (uint8_t) (~(1UL << (pin & BSP_IO_PRV_8BIT_MASK)));
+    }
+    else
+#endif
+    {
+        /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
+         * the right side. */
+        ((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->P[pin >>
+                                                                                             BSP_IO_PRV_PORT_OFFSET] &=
+            (uint8_t) (~(1UL << (pin & BSP_IO_PRV_8BIT_MASK)));
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Toggle the output level of the pin in the specified region.
+ *
+ * @param[in]  region          The target IO region
+ * @param[in]  pin             The pin
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinToggle (bsp_io_region_t region, bsp_io_port_pin_t pin)
+{
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (region == BSP_IO_REGION_NOT_SAFE_DEDICATED)
+    {
+        /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
+         * the right side. */
+        R_PORT_NSR->P[pin >> 8] ^=
+            (uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK));
+    }
+    else
+#endif
+    {
+        /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
+         * the right side. */
+        ((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->P[pin >>
+                                                                                             BSP_IO_PRV_PORT_OFFSET] ^=
+            (uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK));
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Read the input level of the pin in the specified region.
+ *
+ * @param[in]  region          The target IO region
+ * @param[in]  pin             The pin
+ *
+ * @retval     Current input level
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_BSP_FastPinRead (bsp_io_region_t region, bsp_io_port_pin_t pin)
+{
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (region == BSP_IO_REGION_NOT_SAFE_DEDICATED)
+    {
+        return (uint32_t) ((R_PORT_NSR->PIN[pin >> 8]) >>
+                           (pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL;
+    }
+#endif
+
+    return (uint32_t) ((((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->PIN[pin >>
+                                                                                                               BSP_IO_PRV_PORT_OFFSET
+                        ]) >>
+                       (pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL;
+}
+
+/*******************************************************************************************************************//**
+ * Set the output value of the port in the specified region. All pins in the port must be set to the same IO region to
+ * use this function.
+ *
+ * @param[in]  region           The target IO region
+ * @param[in]  port             The port
+ * @param[in]  set_value        The setting value
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PortWrite (bsp_io_region_t region, bsp_io_port_t port, uint8_t set_value)
+{
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (region == BSP_IO_REGION_NOT_SAFE_DEDICATED)
+    {
+        R_PORT_NSR->P[port >> 8] = set_value;
+    }
+    else
+#endif
+    {
+        ((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->P[port >>
+                                                                                             BSP_IO_PRV_PORT_OFFSET] =
+            set_value;
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Read the input value of the port in the specified region. All pins in the port must be set to the same IO region to
+ * use this function.
+ *
+ * @param[in]  region           The target IO region
+ * @param[in]  port             The port
+ *
+ * @retval     Current input value
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_BSP_PortRead (bsp_io_region_t region, bsp_io_port_t port)
+{
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (region == BSP_IO_REGION_NOT_SAFE_DEDICATED)
+    {
+        return (uint32_t) (R_PORT_NSR->PIN[port >> 8]);
+    }
+#endif
+
+    return (uint32_t) (((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->PIN[port >>
+                                                                                                              BSP_IO_PRV_PORT_OFFSET
+                       ]);
+}
+
+/*******************************************************************************************************************//**
+ * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur
+ * via multiple threads or an ISR re-entering this code.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinAccessEnable (void)
+{
+#if BSP_CFG_PORT_PROTECT
+
+    /** Get the current state of interrupts */
+    FSP_CRITICAL_SECTION_DEFINE;
+    FSP_CRITICAL_SECTION_ENTER;
+
+    /** If this is first entry then allow writing of PFS. */
+    if (0 == g_protect_port_counter)
+    {
+        /** Disable protection using PRCR register. */
+
+        /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+         * disable writes. */
+        R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO);
+        R_RWP_S->PRCRS  = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO);
+    }
+
+    /** Increment the protect counter */
+    g_protect_port_counter++;
+
+    /** Restore the interrupt state */
+    FSP_CRITICAL_SECTION_EXIT;
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via
+ * multiple threads or an ISR re-entering this code.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinAccessDisable (void)
+{
+#if BSP_CFG_PORT_PROTECT
+
+    /** Get the current state of interrupts */
+    FSP_CRITICAL_SECTION_DEFINE;
+    FSP_CRITICAL_SECTION_ENTER;
+
+    /** Is it safe to disable PFS register? */
+    if (0 != g_protect_port_counter)
+    {
+        /* Decrement the protect counter */
+        g_protect_port_counter--;
+    }
+
+    /** Is it safe to disable writing of PFS? */
+    if (0 == g_protect_port_counter)
+    {
+        /** Enable protection using PRCR register. */
+
+        /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+         * disable writes. */
+        R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) & (uint16_t) (~BSP_IO_REG_PROTECT_GPIO));
+        R_RWP_S->PRCRS  = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) & (uint16_t) (~BSP_IO_REG_PROTECT_GPIO));
+    }
+
+    /** Restore the interrupt state */
+    FSP_CRITICAL_SECTION_EXIT;
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Read IO region of the pin.
+ *
+ * @param[in]  pin                   The pin
+ *
+ * @retval BSP_IO_REGION_SAFE                   IO region of the pin is safety
+ * @retval BSP_IO_REGION_NOT_SAFE               IO region of the pin is non-safety
+ * @retval BSP_IO_REGION_NOT_SAFE_DEDICATED     IO region of the pin is non-safety (dedicated)
+ *
+ * This function can be given as an argument to pin/port access functions described below. When used in a function
+ * starting with R_BSP_Port, any one pin in the port should be given as an argument to this function.
+ * R_BSP_PinSet(), R_BSP_PinClear(), R_BSP_PinToggle(), R_BSP_FastPinRead(), R_BSP_PortWrite(), R_BSP_PortRead()
+ *
+ * @note This function can be used to get the region of a specified pin, but the overhead should be considered if this
+ *       function is executed each time the pin is accessed. When accessing the same pin repeatedly, it is recommended
+ *       that the value obtained by this function be held in a variable beforehand, and the value of the variable be
+ *       used as the region argument of the pin access function.
+ **********************************************************************************************************************/
+__STATIC_INLINE bsp_io_region_t R_BSP_IoRegionGet (bsp_io_port_pin_t pin)
+{
+    uint32_t aselp = 0;
+
+    /* Casting to a uint32_t type is valid because the range of values represented by uint32_t is not over in the
+     * calculation process of the right-hand side. */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_PORT > (uint32_t) (pin >> BSP_IO_PRV_PORT_OFFSET))
+    {
+        aselp =
+            ((uint32_t) ((R_PORT_SRS->RSELP[pin >> BSP_IO_PRV_PORT_OFFSET]) >> (pin & BSP_IO_PRV_8BIT_MASK)) &
+             0x00000001UL);
+    }
+    else
+    {
+        aselp = (uint32_t) BSP_IO_REGION_NOT_SAFE_DEDICATED;
+    }
+#else
+    aselp =
+        ((uint32_t) ((R_PTADR->RSELP[pin >> BSP_IO_PRV_PORT_OFFSET]) >> (pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL);
+#endif
+
+    if (0U == aselp)
+    {
+        return BSP_IO_REGION_SAFE;
+    }
+    else if (1U == aselp)
+    {
+        return BSP_IO_REGION_NOT_SAFE;
+    }
+    else
+    {
+        return BSP_IO_REGION_NOT_SAFE_DEDICATED;
+    }
+}
+
+/** @} (end addtogroup BSP_IO) */
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_irq.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_irq.c
new file mode 100644
index 00000000..8d4b8bc5
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_irq.c
@@ -0,0 +1,273 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+/* Pointer to control structure table. */
+void ** gp_bsp_gpt_combined_ctrl_table[BSP_IRQ_GPT_COMBINED_GROUP_NUM] =
+{
+    NULL,                              /* Pointer to Group 0 control structure table.  (Use NS_GPT_INTSTAT0) */
+    NULL,                              /* Pointer to Group 1 control structure table.  (Use NS_GPT_INTSTAT1) */
+    NULL,                              /* Pointer to Group 2 control structure table.  (Use NS_GPT_INTSTAT2) */
+    NULL,                              /* Pointer to Group 3 control structure table.  (Use NS_GPT_INTSTAT3) */
+    NULL,                              /* Pointer to Group 4 control structure table.  (Use NS_GPT_INTSTAT4) */
+    NULL,                              /* Pointer to Group 5 control structure table.  (Use NS_GPT_INTSTAT5) */
+    NULL,                              /* Pointer to Group 6 control structure table.  (Use NS_GPT_INTSTAT6) */
+    NULL,                              /* Pointer to Group 7 control structure table.  (Use NS_GPT_INTSTAT7) */
+    NULL,                              /* Pointer to Group 8 control structure table.  (Use NS_GPT_INTSTAT8) */
+    NULL,                              /* Pointer to Group 9 control structure table.  (Use NS_GPT_INTSTAT9) */
+    NULL,                              /* Pointer to Group 10 control structure table. (Use NS_GPT_INTSTAT10) */
+    NULL,                              /* Pointer to Group 11 control structure table. (Use NS_GPT_INTSTAT11) */
+    NULL,                              /* Pointer to Group 12 control structure table. (Use NS_GPT_INTSTAT12) */
+    NULL,                              /* Pointer to Group 13 control structure table. (Use NS_GPT_INTSTAT13) */
+    NULL,                              /* Pointer to Group 14 control structure table. (Use NS_GPT_INTSTAT14) */
+    NULL,                              /* Pointer to Group 15 control structure table. (Use NS_GPT_INTSTAT15) */
+    NULL,                              /* Pointer to Group 16 control structure table. (Use NS_GPT_INTSTAT16) */
+    NULL,                              /* Pointer to Group 17 control structure table. (Use NS_GPT_INTSTAT17) */
+    NULL,                              /* Pointer to Group 18 control structure table. (Use NS_GPT_INTSTAT18) */
+    NULL,                              /* Pointer to Group 19 control structure table. (Use NS_GPT_INTSTAT19) */
+    NULL,                              /* Pointer to Group 20 control structure table. (Use NS_GPT_INTSTAT20) */
+    NULL,                              /* Pointer to Group 21 control structure table. (Use NS_GPT_INTSTAT21) */
+    NULL,                              /* Pointer to Group 22 control structure table. (Use NS_GPT_INTSTAT22) */
+    NULL,                              /* Pointer to Group 23 control structure table. (Use NS_GPT_INTSTAT23) */
+    NULL,                              /* Pointer to Group 24 control structure table. (Use NS_GPT_INTSTAT24) */
+    NULL,                              /* Pointer to Group 25 control structure table. (Use NS_GPT_INTSTAT25) */
+    NULL,                              /* Pointer to Group 26 control structure table. (Use S_GPT_INTSTAT0) */
+    NULL,                              /* Pointer to Group 27 control structure table. (Use S_GPT_INTSTAT1) */
+};
+
+/* Pointer to interrupt handler table. */
+fsp_vector_t * gp_bsp_gpt_combined_isr_table[BSP_IRQ_GPT_COMBINED_GROUP_NUM] =
+{
+    NULL,                              /* Pointer to Group 0 interrupt handler table.  (Use NS_GPT_INTSTAT0) */
+    NULL,                              /* Pointer to Group 1 interrupt handler table.  (Use NS_GPT_INTSTAT1) */
+    NULL,                              /* Pointer to Group 2 interrupt handler table.  (Use NS_GPT_INTSTAT2) */
+    NULL,                              /* Pointer to Group 3 interrupt handler table.  (Use NS_GPT_INTSTAT3) */
+    NULL,                              /* Pointer to Group 4 interrupt handler table.  (Use NS_GPT_INTSTAT4) */
+    NULL,                              /* Pointer to Group 5 interrupt handler table.  (Use NS_GPT_INTSTAT5) */
+    NULL,                              /* Pointer to Group 6 interrupt handler table.  (Use NS_GPT_INTSTAT6) */
+    NULL,                              /* Pointer to Group 7 interrupt handler table.  (Use NS_GPT_INTSTAT7) */
+    NULL,                              /* Pointer to Group 8 interrupt handler table.  (Use NS_GPT_INTSTAT8) */
+    NULL,                              /* Pointer to Group 9 interrupt handler table.  (Use NS_GPT_INTSTAT9) */
+    NULL,                              /* Pointer to Group 10 interrupt handler table. (Use NS_GPT_INTSTAT10) */
+    NULL,                              /* Pointer to Group 11 interrupt handler table. (Use NS_GPT_INTSTAT11) */
+    NULL,                              /* Pointer to Group 12 interrupt handler table. (Use NS_GPT_INTSTAT12) */
+    NULL,                              /* Pointer to Group 13 interrupt handler table. (Use NS_GPT_INTSTAT13) */
+    NULL,                              /* Pointer to Group 14 interrupt handler table. (Use NS_GPT_INTSTAT14) */
+    NULL,                              /* Pointer to Group 15 interrupt handler table. (Use NS_GPT_INTSTAT15) */
+    NULL,                              /* Pointer to Group 16 interrupt handler table. (Use NS_GPT_INTSTAT16) */
+    NULL,                              /* Pointer to Group 17 interrupt handler table. (Use NS_GPT_INTSTAT17) */
+    NULL,                              /* Pointer to Group 18 interrupt handler table. (Use NS_GPT_INTSTAT18) */
+    NULL,                              /* Pointer to Group 19 interrupt handler table. (Use NS_GPT_INTSTAT19) */
+    NULL,                              /* Pointer to Group 20 interrupt handler table. (Use NS_GPT_INTSTAT20) */
+    NULL,                              /* Pointer to Group 21 interrupt handler table. (Use NS_GPT_INTSTAT21) */
+    NULL,                              /* Pointer to Group 22 interrupt handler table. (Use NS_GPT_INTSTAT22) */
+    NULL,                              /* Pointer to Group 23 interrupt handler table. (Use NS_GPT_INTSTAT23) */
+    NULL,                              /* Pointer to Group 24 interrupt handler table. (Use NS_GPT_INTSTAT24) */
+    NULL,                              /* Pointer to Group 25 interrupt handler table. (Use NS_GPT_INTSTAT25) */
+    NULL,                              /* Pointer to Group 26 control structure table. (Use S_GPT_INTSTAT0) */
+    NULL,                              /* Pointer to Group 27 control structure table. (Use S_GPT_INTSTAT1) */
+};
+
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initialize interrupt controller.
+ *
+ * @retval       None
+ **********************************************************************************************************************/
+void bsp_irq_cfg (void)
+{
+    bsp_irq_core_cfg();
+}
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+/*******************************************************************************************************************//**
+ * Get GPT_INT channel number.
+ *
+ * @param[in]   irq     IRQ number
+ *
+ * @return      GPT_INT channel number.
+ **********************************************************************************************************************/
+uint32_t bsp_prv_irq_gpt_channel_get (IRQn_Type irq)
+{
+    return ((uint32_t) irq - BSP_IRQ_GPT_EVENT_NUM_BASE) / BSP_IRQ_GPT_INT_NUM_MAX;
+}
+
+/*******************************************************************************************************************//**
+ * Get GPT_INT register number.
+ *
+ * @param[in]   channel     GPT_INT channel number
+ *
+ * @return      GPT_INT register number.
+ **********************************************************************************************************************/
+uint32_t bsp_prv_irq_gpt_reg_num_get (uint32_t channel)
+{
+    return (channel % BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL) / BSP_IRQ_GPT_REGISTER_DIVISION;
+}
+
+/*******************************************************************************************************************//**
+ * Get bit shift value of the GPT_INTSELn register.
+ *
+ * @param[in]   irq         IRQ number
+ * @param[in]   channel     GPT_INT channel number
+ *
+ * @return      Bit shift value.
+ **********************************************************************************************************************/
+uint32_t bsp_prv_irq_gpt_selected_shift_num_get (IRQn_Type irq, uint32_t channel)
+{
+    uint32_t irqdiff = (uint32_t) irq - BSP_IRQ_GPT_EVENT_NUM_BASE;
+
+    return channel % BSP_IRQ_GPT_REGISTER_DIVISION ?
+           BSP_IRQ_GPT_SELECTED_INTERVAL * (irqdiff % BSP_IRQ_GPT_INT_NUM_MAX) + BSP_IRQ_GPT_IY_SHIFT_NUM :
+           BSP_IRQ_GPT_SELECTED_INTERVAL * (irqdiff % BSP_IRQ_GPT_INT_NUM_MAX) + BSP_IRQ_GPT_IX_SHIFT_NUM;
+}
+
+/*******************************************************************************************************************//**
+ * Get GPT_INT table number.
+ *
+ * @param[in]   channel     GPT_INT channel number
+ *
+ * @return      GPT_INT table number.
+ **********************************************************************************************************************/
+uint32_t bsp_prv_irq_gpt_combined_table_num_get (uint32_t channel)
+{
+    return (channel % BSP_FEATURE_GPT_CHANNEL) / BSP_IRQ_GPT_REGISTER_DIVISION;
+}
+
+/*******************************************************************************************************************//**
+ * Allocate memory for 'groupIndex'th control structure table.
+ *
+ * @param[in]   groupIndex         Register number
+ *
+ * @return      Allocated memory address
+ **********************************************************************************************************************/
+void * bsp_prv_irq_gpt_combined_ctrl_table_allocate (uint32_t groupIndex)
+{
+    /* Allocate memory for 'groupIndex'th control structure table. */
+    gp_bsp_gpt_combined_ctrl_table[groupIndex] =
+        bsp_prv_malloc(BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP * sizeof(uintptr_t));
+    if (NULL != gp_bsp_gpt_combined_ctrl_table[groupIndex])
+    {
+        /* Set initial value at malloc area. */
+        for (uint32_t elementIndex = 0U; elementIndex < BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP; elementIndex++)
+        {
+            gp_bsp_gpt_combined_ctrl_table[groupIndex][elementIndex] = NULL;
+        }
+    }
+
+    return gp_bsp_gpt_combined_ctrl_table[groupIndex];
+}
+
+/*******************************************************************************************************************//**
+ * Allocate memory for 'groupIndex'th interrupt handler table.
+ *
+ * @param[in]   groupIndex         Register number
+ *
+ * @return      Allocated memory address
+ **********************************************************************************************************************/
+void * bsp_prv_irq_gpt_combined_isr_table_allocate (uint32_t groupIndex)
+{
+    /* Allocate memory for 'groupIndex'th structure table. */
+    gp_bsp_gpt_combined_isr_table[groupIndex] =
+        bsp_prv_malloc(BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP * sizeof(uintptr_t));
+    if (NULL != gp_bsp_gpt_combined_isr_table[groupIndex])
+    {
+        /* Set initial value at malloc area. */
+        for (uint32_t elementIndex = 0U; elementIndex < BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP; elementIndex++)
+        {
+            gp_bsp_gpt_combined_isr_table[groupIndex][elementIndex] = NULL;
+        }
+    }
+
+    return gp_bsp_gpt_combined_isr_table[groupIndex];
+}
+
+/*******************************************************************************************************************//**
+ * Get bit shift value of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn registers.
+ *
+ * @param[in]   channel       GPT_INT channel number
+ * @param[in]   event_source  Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ *
+ * @return      Bit shift value.
+ **********************************************************************************************************************/
+uint32_t bsp_prv_irq_gpt_combined_shift_num_get (uint32_t channel, bsp_irq_gpt_combined_event_t event_source)
+{
+    return channel % BSP_IRQ_GPT_REGISTER_DIVISION ? (uint32_t) event_source + BSP_IRQ_GPT_IY_SHIFT_NUM :
+           (uint32_t) event_source + BSP_IRQ_GPT_IX_SHIFT_NUM;
+}
+
+/*******************************************************************************************************************//**
+ * Called when a GPT combined interrupt occurs, clears the GPT/MTU3 interrupt and executes the ISR function.
+ **********************************************************************************************************************/
+void bsp_irq_gpt_combined_interrupt_handler (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    uint32_t gpt_intstat = R_BSP_IrqGptCombinedStatusRead(irq);
+
+    /* Since the GPT/MTU interrupt status is divided into upper 16 bits and lower 16 bits,
+     * the bit positions are adjusted for the upper bits. */
+    if (bsp_prv_irq_gpt_channel_get(irq) % BSP_IRQ_GPT_REGISTER_DIVISION)
+    {
+        gpt_intstat >>= BSP_IRQ_GPT_IY_SHIFT_NUM;
+    }
+
+    bsp_irq_gpt_combined_event_t event_source;
+    uint32_t next_event  = 0;
+    uint32_t event_shift = 0;
+    void   * p_context;
+    void     (* p_interrupt_handler)(void);
+
+    while (gpt_intstat)
+    {
+        /* Scan and search for GPT and MTU3 interrupts factors one by one. */
+        next_event    = __CLZ(__RBIT(gpt_intstat));
+        gpt_intstat >>= next_event;
+        event_shift  += next_event;
+        event_source  = (bsp_irq_gpt_combined_event_t) (event_shift & BSP_IRQ_GPT_COMBINED_EVENT_ENUM_MASK);
+
+        /* Obtains the context and interrupt handler from the table and executes interrupt processing. */
+        R_BSP_IrqGptCombinedStatusClear(irq, event_source);
+        p_context = R_BSP_IrqGptCombinedCtrlGet(irq, event_source);
+        R_FSP_IsrContextSet(irq, p_context);
+        p_interrupt_handler = R_BSP_IrqGptCombinedIsrGet(irq, event_source);
+        p_interrupt_handler();
+
+        /* Clear the scanned flags one by one. */
+        gpt_intstat &= (uint32_t) ~(1UL);
+    }
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+}
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_irq.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_irq.h
new file mode 100644
index 00000000..073e5346
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_irq.h
@@ -0,0 +1,624 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_IRQ_H
+#define BSP_IRQ_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+#if defined(BSP_CFG_CORE_CR52)
+ #include "cr/bsp_irq_core.h"
+#elif defined(BSP_CFG_CORE_CA55)
+ #include "ca/bsp_irq_core.h"
+#endif
+
+#include "fsp_features.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_IRQ_GPT_EVENT_NUM_BASE                  ((IRQn_Type) ELC_EVENT_GPT00_0_INT0) // IRQ number of GPT_INT00_0.
+#define BSP_IRQ_GPT_INT_NUM_MAX                     (5U)                                 // Total size from GPT_INT0 to GPT_INT4.
+#define BSP_IRQ_GPT_REGISTER_DIVISION               (2U)                                 // Divide GPT channel number.
+#define BSP_IRQ_GPT_IY_SHIFT_NUM                    (16U)                                // Upper bits shift of GPT_INTSELn.
+#define BSP_IRQ_GPT_IX_SHIFT_NUM                    (0U)                                 // Low bits shift of GPT_INTSELn.
+
+#define BSP_IRQ_GPT_SELECTED_INTERVAL               (4U)                                 // Bit interval of GPT_INTSELn.
+#define BSP_IRQ_GPT_SELECTED_EVENT_MASK             (0xFU)                               // Bits mask of GPT_INTSELn.
+
+#define BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP    (32)                                 // 32bit state bit per GPT_INTSTATn and so on.
+#define BSP_IRQ_GPT_COMBINED_GROUP_NUM              (28)                                 // NS_GPT_INTSTAT0 to 25 and S_GPT_INTSTAT0 to 1.
+#define BSP_IRQ_GPT_COMBINED_EVENT_MASK             (0x1U)                               // Bit mask of GPT_INTMSKn
+#define BSP_IRQ_GPT_COMBINED_EVENT_ENUM_MASK        (0xFU)                               // Bit mask of bsp_irq_gpt_combined_event_t
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+#ifndef BSP_OVERRIDE_BSP_IRQ_GPT_SELECTED_EVENT_T
+
+/** GPT selected interrupt event */
+typedef enum e_bsp_irq_gpt_selected_event
+{
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_CCMPA = 0x0, ///< GPT_CCMPA event source
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_CCMPB = 0x1, ///< GPT_CCMPB event source
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_CMPC  = 0x2, ///< GPT_CMPC event source
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_CMPD  = 0x3, ///< GPT_CMPD event source
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_CMPE  = 0x4, ///< GPT_CMPE event source
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_CMPF  = 0x5, ///< GPT_CMPF event source
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_OVF   = 0x6, ///< GPT_OVF event source
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_UDF   = 0x7, ///< GPT_UDF event source
+    BSP_IRQ_GPT_SELECTED_EVENT_GPT_DTE   = 0x8, ///< GPT_DTE event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIA0     = 0x9, ///< MTU3 TGIA0 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIB0     = 0xA, ///< MTU3 TGIB0 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIC0     = 0xB, ///< MTU3 TGIC0 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGID0     = 0xC, ///< MTU3 TGID0 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV0     = 0xD, ///< MTU3 TCIV0 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIE0     = 0x9, ///< MTU3 TGIE0 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIF0     = 0xA, ///< MTU3 TGIF0 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIA1     = 0xB, ///< MTU3 TGIA1 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIB1     = 0xC, ///< MTU3 TGIB1 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV1     = 0xD, ///< MTU3 TCIV1 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIU1     = 0x9, ///< MTU3 TCIU1 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIA2     = 0xA, ///< MTU3 TGIA2 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIB2     = 0xB, ///< MTU3 TGIB2 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV2     = 0xC, ///< MTU3 TCIV2 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIU2     = 0xD, ///< MTU3 TCIU2 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIA3     = 0x9, ///< MTU3 TGIA3 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIB3     = 0xA, ///< MTU3 TGIB3 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIC3     = 0xB, ///< MTU3 TGIC3 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGID3     = 0xC, ///< MTU3 TGID3 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV3     = 0xD, ///< MTU3 TCIV3 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIA4     = 0x9, ///< MTU3 TGIA4 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIB4     = 0xA, ///< MTU3 TGIB4 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIC4     = 0xB, ///< MTU3 TGIC4 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGID4     = 0xC, ///< MTU3 TGID4 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV4     = 0xD, ///< MTU3 TCIV4 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIU5     = 0x9, ///< MTU3 TCIU5 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV5     = 0xA, ///< MTU3 TCIV5 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIW5     = 0xB, ///< MTU3 TGIW5 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIA6     = 0x9, ///< MTU3 TGIA6 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIB6     = 0xA, ///< MTU3 TGIB6 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIC6     = 0xB, ///< MTU3 TGIC6 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGID6     = 0xC, ///< MTU3 TGID6 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV6     = 0xD, ///< MTU3 TCIV6 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIA7     = 0x9, ///< MTU3 TGIA7 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIB7     = 0xA, ///< MTU3 TGIB7 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIC7     = 0xB, ///< MTU3 TGIC7 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGID7     = 0xC, ///< MTU3 TGID7 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV7     = 0xD, ///< MTU3 TCIV7 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIA8     = 0x9, ///< MTU3 TGIA8 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIB8     = 0xA, ///< MTU3 TGIB8 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGIC8     = 0xB, ///< MTU3 TGIC8 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TGID8     = 0xC, ///< MTU3 TGID8 event source
+    BSP_IRQ_GPT_SELECTED_EVENT_TCIV8     = 0xD, ///< MTU3 TCIV8 event source
+} bsp_irq_gpt_selected_event_t;
+
+#endif
+
+#ifndef BSP_OVERRIDE_BSP_IRQ_GPT_COMBINED_EVENT_T
+
+/** GPT combined interrupt event */
+typedef enum e_bsp_irq_gpt_combined_event
+{
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_CCMPA = 0x0, ///< GPT_CCMPA event source
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_CCMPB = 0x1, ///< GPT_CCMPB event source
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_CMPC  = 0x2, ///< GPT_CMPC event source
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_CMPD  = 0x3, ///< GPT_CMPD event source
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_CMPE  = 0x4, ///< GPT_CMPE event source
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_CMPF  = 0x5, ///< GPT_CMPF event source
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_OVF   = 0x6, ///< GPT_OVF event source
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_UDF   = 0x7, ///< GPT_UDF event source
+    BSP_IRQ_GPT_COMBINED_EVENT_GPT_DTE   = 0x8, ///< GPT_DTE event source
+    BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0    = 0x9, ///< MTU3 event source 0
+    BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1    = 0xA, ///< MTU3 event source 1
+    BSP_IRQ_GPT_COMBINED_EVENT_MTU3_2    = 0xB, ///< MTU3 event source 2
+    BSP_IRQ_GPT_COMBINED_EVENT_MTU3_3    = 0xC, ///< MTU3 event source 3
+    BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4    = 0xD, ///< MTU3 event source 4
+    BSP_IRQ_GPT_COMBINED_EVENT_RESERVED1 = 0xE, ///< Reserved bit
+    BSP_IRQ_GPT_COMBINED_EVENT_RESERVED2 = 0xF, ///< Reserved bit
+} bsp_irq_gpt_combined_event_t;
+
+#endif
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+extern void ** gp_bsp_gpt_combined_ctrl_table[BSP_IRQ_GPT_COMBINED_GROUP_NUM];
+extern fsp_vector_t * gp_bsp_gpt_combined_isr_table[BSP_IRQ_GPT_COMBINED_GROUP_NUM];
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+uint32_t bsp_prv_irq_gpt_channel_get(IRQn_Type irq);
+uint32_t bsp_prv_irq_gpt_reg_num_get(uint32_t channel);
+uint32_t bsp_prv_irq_gpt_selected_shift_num_get(IRQn_Type irq, uint32_t channel);
+uint32_t bsp_prv_irq_gpt_combined_shift_num_get(uint32_t channel, bsp_irq_gpt_combined_event_t event_source);
+void   * bsp_prv_irq_gpt_combined_ctrl_table_allocate(uint32_t groupIndex);
+void   * bsp_prv_irq_gpt_combined_isr_table_allocate(uint32_t groupIndex);
+bool     bsp_prv_irq_gpt_combined_table_status_get(uintptr_t * p_table, uint32_t size);
+uint32_t bsp_prv_irq_gpt_combined_table_num_get(uint32_t channel);
+void     bsp_irq_gpt_combined_interrupt_handler(void);
+
+#endif
+
+/***********************************************************************************************************************
+ * Inline Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief      Sets the ISR context associated with the requested IRQ.
+ *
+ * @param[in]  irq            IRQ number (parameter checking must ensure the IRQ number is valid before calling this
+ *                            function.
+ * @param[in]  p_context      ISR context for IRQ.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
+{
+    /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
+     * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
+    r_fsp_irq_context_set(irq, p_context);
+}
+
+/*******************************************************************************************************************//**
+ * Clear the GIC pending interrupt.
+ *
+ * @param[in] irq            Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
+{
+    r_bsp_irq_clear_pending(irq);
+}
+
+/*******************************************************************************************************************//**
+ * Get the GIC pending interrupt.
+ *
+ * @param[in] irq            Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ *
+ * @return  Value indicating the status of the level interrupt.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_BSP_IrqPendingGet (IRQn_Type irq)
+{
+    return r_bsp_irq_pending_get(irq);
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt priority and context.
+ *
+ * @param[in] irq            The IRQ number to configure.
+ * @param[in] priority       GIC priority of the interrupt
+ * @param[in] p_context      The interrupt context is a pointer to data required in the ISR.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
+{
+    r_bsp_irq_cfg(irq, priority);
+
+    /* Store the context. The context is recovered in the ISR. */
+    R_FSP_IsrContextSet(irq, p_context);
+}
+
+/*******************************************************************************************************************//**
+ * Enable the IRQ in the GIC (Without clearing the pending bit).
+ *
+ * @param[in] irq            The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
+ *                           Cortex Processor Exceptions Numbers.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
+{
+    r_bsp_irq_enable_no_clear(irq);
+}
+
+/*******************************************************************************************************************//**
+ * Enable the IRQ in the GIC (With clearing the pending bit).
+ *
+ * @param[in] irq            The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
+ *                           Cortex Processor Exceptions Numbers.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
+{
+    /* Clear pending interrupts in the GIC. */
+    R_BSP_IrqClearPending(irq);
+
+    /* Enable the interrupt in the GIC. */
+    R_BSP_IrqEnableNoClear(irq);
+}
+
+/*******************************************************************************************************************//**
+ * Disables interrupts in the GIC.
+ *
+ * @param[in] irq            The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
+{
+    r_bsp_irq_disable(irq);
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
+ *
+ * @param[in] irq            Interrupt number.
+ * @param[in] priority       GIC priority of the interrupt
+ * @param[in] p_context      The interrupt context is a pointer to data required in the ISR.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
+{
+    R_BSP_IrqCfg(irq, priority, p_context);
+    R_BSP_IrqEnable(irq);
+}
+
+/*******************************************************************************************************************//**
+ * @brief      Finds the ISR context associated with the requested IRQ.
+ *
+ * @param[in]  irq            IRQ number (parameter checking must ensure the IRQ number is valid before calling this
+ *                            function.
+ * @return  ISR context for IRQ.
+ **********************************************************************************************************************/
+__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
+{
+
+    /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
+     * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
+    return gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET];
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt detect type.
+ *
+ * @param[in] irq             The IRQ number to configure.
+ * @param[in] detect_type     GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd).
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type)
+{
+    r_bsp_irq_detect_type_set(irq, detect_type);
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt Group.
+ *
+ * @param[in] irq               The IRQ number to configure.
+ * @param[in] interrupt_group   GIC interrupt group number ( 0 : FIQ, 1 : IRQ ).
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group)
+{
+    r_bsp_irq_group_set(irq, interrupt_group);
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt mask level.
+ *
+ * @param[in] mask_level          The interrupt mask level
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqMaskLevelSet (uint32_t mask_level)
+{
+    FSP_CRITICAL_SECTION_SET_STATE(mask_level << BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT);
+}
+
+/*******************************************************************************************************************//**
+ * Gets the interrupt mask level.
+ *
+ * @return  Value indicating the interrupt mask level.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_BSP_IrqMaskLevelGet (void)
+{
+    return (uint32_t) ((FSP_CRITICAL_SECTION_GET_CURRENT_STATE() >> BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT) &
+                       0x0000001FUL);
+}
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+/*******************************************************************************************************************//**
+ * Manipulate GPT_INTSELn and specify the GPT/MTU3 interrupt source as GPT_INT0-3.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the INTSEL bit value of GPT_INTSELn as an enum
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqGptSelectedSet (IRQn_Type irq, bsp_irq_gpt_selected_event_t event_source)
+{
+    if (irq >= BSP_IRQ_GPT_EVENT_NUM_BASE)
+    {
+        uint32_t channel   = bsp_prv_irq_gpt_channel_get(irq);
+        uint32_t reg_num   = bsp_prv_irq_gpt_reg_num_get(channel);
+        uint32_t shift_num = bsp_prv_irq_gpt_selected_shift_num_get(irq, channel);
+
+        if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
+        {
+            R_ICU_NS->NS_GPT_INTSEL[reg_num] &= ~(BSP_IRQ_GPT_SELECTED_EVENT_MASK << shift_num);
+            R_ICU_NS->NS_GPT_INTSEL[reg_num] |= (uint32_t) event_source << shift_num;
+        }
+        else
+        {
+            R_ICU_S->S_GPT_INTSEL[reg_num] &= ~(BSP_IRQ_GPT_SELECTED_EVENT_MASK << shift_num);
+            R_ICU_S->S_GPT_INTSEL[reg_num] |= (uint32_t) event_source << shift_num;
+        }
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Manipulate GPT_INTSELn to clear the GPT/MTU3 interrupt cause setting to 0.
+ *
+ * @param[in]   irq                 IRQ number
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqGptSelectedClear (IRQn_Type irq)
+{
+    if (irq >= BSP_IRQ_GPT_EVENT_NUM_BASE)
+    {
+        uint32_t channel   = bsp_prv_irq_gpt_channel_get(irq);
+        uint32_t reg_num   = bsp_prv_irq_gpt_reg_num_get(channel);
+        uint32_t shift_num = bsp_prv_irq_gpt_selected_shift_num_get(irq, channel);
+
+        if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
+        {
+            R_ICU_NS->NS_GPT_INTSEL[reg_num] &= ~(BSP_IRQ_GPT_SELECTED_EVENT_MASK << shift_num);
+        }
+        else
+        {
+            R_ICU_S->S_GPT_INTSEL[reg_num] &= ~(BSP_IRQ_GPT_SELECTED_EVENT_MASK << shift_num);
+        }
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Registers pointer addresses for control structure and interrupt handler.
+ * If there is no management table, memory is allocated.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ * @param[in]   p_context           Control structure
+ * @param[in]   p_interrupt_handler Interrupt handler
+ *
+ * @note        Function uses the malloc function to create management tables for "control structures" and
+ *              "interrupt handlers". The management table is created in units of 1 group, with 2 channels of
+ *              GPT/MTU3 as 1 group.
+ *              The following memory is consumed for each group. The consumption can be calculated by
+ *              "address size * number of elements * number of tables".
+ *                  256 bytes for CR52 (=4*32*2)
+ *                  512 bytes for CA55 (=8*32*2)
+ *
+ * @retval      FSP_SUCCESS                 Successful.
+ * @retval      FSP_ERR_NOT_INITIALIZED     Memory allocation failed.
+ **********************************************************************************************************************/
+__STATIC_INLINE fsp_err_t R_BSP_IrqGptCombinedTableSet (IRQn_Type                    irq,
+                                                        bsp_irq_gpt_combined_event_t event_source,
+                                                        void                       * p_context,
+                                                        void (                     * p_interrupt_handler)(void))
+{
+    uint32_t channel      = bsp_prv_irq_gpt_channel_get(irq);
+    uint32_t groupIndex   = bsp_prv_irq_gpt_combined_table_num_get(channel);
+    uint32_t elementIndex = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
+    void   * p_table;
+
+    /* If not exist 'groupIndex'th control structure table,
+     * allocate memory for 'groupIndex'th control structure table. */
+    if (NULL == gp_bsp_gpt_combined_ctrl_table[groupIndex])
+    {
+        p_table = bsp_prv_irq_gpt_combined_ctrl_table_allocate(groupIndex);
+        FSP_ERROR_RETURN(NULL != p_table, FSP_ERR_NOT_INITIALIZED);
+    }
+
+    /* If not exist 'groupIndex'th interrupt handler table,
+     * allocate memory for 'groupIndex'th interrupt handler table. */
+    if (NULL == gp_bsp_gpt_combined_isr_table[groupIndex])
+    {
+        p_table = bsp_prv_irq_gpt_combined_isr_table_allocate(groupIndex);
+        FSP_ERROR_RETURN(NULL != p_table, FSP_ERR_NOT_INITIALIZED);
+    }
+
+    /* Registers pointer addresses for control structure and interrupt handler. */
+    gp_bsp_gpt_combined_ctrl_table[groupIndex][elementIndex] = p_context;
+    gp_bsp_gpt_combined_isr_table[groupIndex][elementIndex]  = p_interrupt_handler;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Get pointer addresses for control structure.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ *
+ * @return      Pointer addresses for control structure.
+ **********************************************************************************************************************/
+__STATIC_INLINE void * R_BSP_IrqGptCombinedCtrlGet (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
+{
+    uint32_t channel      = bsp_prv_irq_gpt_channel_get(irq);
+    uint32_t groupIndex   = bsp_prv_irq_gpt_combined_table_num_get(channel);
+    uint32_t elementIndex = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
+
+    return gp_bsp_gpt_combined_ctrl_table[groupIndex][elementIndex];
+}
+
+/*******************************************************************************************************************//**
+ * Get pointer addresses for interrupt handler.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ *
+ * @return      Pointer addresses for interrupt handler.
+ **********************************************************************************************************************/
+__STATIC_INLINE fsp_vector_t R_BSP_IrqGptCombinedIsrGet (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
+{
+    uint32_t channel      = bsp_prv_irq_gpt_channel_get(irq);
+    uint32_t groupIndex   = bsp_prv_irq_gpt_combined_table_num_get(channel);
+    uint32_t elementIndex = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
+
+    return gp_bsp_gpt_combined_isr_table[groupIndex][elementIndex];
+}
+
+/*******************************************************************************************************************//**
+ * Releases pointer addresses for control structure and interrupt handler.
+ * If there are no more values to manage in the management table, memory is free.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqGptCombinedTableClear (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
+{
+    uint32_t channel      = bsp_prv_irq_gpt_channel_get(irq);
+    uint32_t groupIndex   = bsp_prv_irq_gpt_combined_table_num_get(channel);
+    uint32_t elementIndex = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
+
+    gp_bsp_gpt_combined_ctrl_table[groupIndex][elementIndex] = NULL;
+    gp_bsp_gpt_combined_isr_table[groupIndex][elementIndex]  = NULL;
+
+    uint32_t cnt;
+    for (cnt = 0; cnt < BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP; cnt++)
+    {
+        if (NULL != gp_bsp_gpt_combined_ctrl_table[groupIndex][cnt])
+        {
+            break;
+        }
+    }
+
+    if (BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP == cnt)
+    {
+        bsp_prv_free(gp_bsp_gpt_combined_ctrl_table[groupIndex]);
+        gp_bsp_gpt_combined_ctrl_table[groupIndex] = NULL;
+    }
+
+    for (cnt = 0; cnt < BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP; cnt++)
+    {
+        if (NULL != gp_bsp_gpt_combined_isr_table[groupIndex][cnt])
+        {
+            break;
+        }
+    }
+
+    if (BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP == cnt)
+    {
+        bsp_prv_free(gp_bsp_gpt_combined_ctrl_table[groupIndex]);
+        gp_bsp_gpt_combined_isr_table[groupIndex] = NULL;
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Manipulate GPT_INTMSKn to mask GPT/MTU3 interrupts.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqGptCombinedMaskSet (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
+{
+    uint32_t channel   = bsp_prv_irq_gpt_channel_get(irq);
+    uint32_t reg_num   = bsp_prv_irq_gpt_reg_num_get(channel);
+    uint32_t shift_num = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
+
+    if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
+    {
+        R_ICU_NS->NS_GPT_INTMSK[reg_num] |= BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num;
+    }
+    else
+    {
+        R_ICU_S->S_GPT_INTMSK[reg_num] |= BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num;
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Manipulate GPT_INTMSKn to unmask the GPT/MTU3 interrupt.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqGptCombinedMaskClear (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
+{
+    uint32_t channel   = bsp_prv_irq_gpt_channel_get(irq);
+    uint32_t reg_num   = bsp_prv_irq_gpt_reg_num_get(channel);
+    uint32_t shift_num = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
+
+    if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
+    {
+        R_ICU_NS->NS_GPT_INTMSK[reg_num] &= ~(BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num);
+    }
+    else
+    {
+        R_ICU_S->S_GPT_INTMSK[reg_num] &= ~(BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Read GPT_INTSTATn and return the status of the GPT/MTU3 interrupt.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ *
+ * @return      GPT_INTSTATn value.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_BSP_IrqGptCombinedStatusRead (IRQn_Type irq)
+{
+    uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
+    uint32_t reg_num = bsp_prv_irq_gpt_reg_num_get(channel);
+    uint32_t intmsk  = 0;
+    uint32_t intstat = 0;
+
+    if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
+    {
+        intmsk  = ~(R_ICU_NS->NS_GPT_INTMSK[reg_num]);
+        intstat = R_ICU_NS->NS_GPT_INTSTAT[reg_num] & intmsk;
+    }
+    else
+    {
+        intmsk  = ~(R_ICU_S->S_GPT_INTMSK[reg_num]);
+        intstat = R_ICU_S->S_GPT_INTSTAT[reg_num] & intmsk;
+    }
+
+    return intstat;
+}
+
+/*******************************************************************************************************************//**
+ * Write to GPT_INTCLRn to clear the GPT/MTU3 event occurrence state.
+ *
+ * @param[in]   irq                 IRQ number
+ * @param[in]   event_source        Define the bit shift values ​​of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqGptCombinedStatusClear (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
+{
+    uint32_t channel   = bsp_prv_irq_gpt_channel_get(irq);
+    uint32_t reg_num   = bsp_prv_irq_gpt_reg_num_get(channel);
+    uint32_t shift_num = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
+
+    if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
+    {
+        R_ICU_NS->NS_GPT_INTCLR[reg_num] |= (BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num);
+    }
+    else
+    {
+        R_ICU_S->S_GPT_INTCLR[reg_num] |= (BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num);
+    }
+}
+
+#endif
+
+/** @} (end addtogroup BSP_MCU) */
+
+/*******************************************************************************************************************//**
+ * @internal
+ * @addtogroup BSP_MCU_PRV Internal BSP Documentation
+ * @ingroup RENESAS_INTERNAL
+ * @{
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+void bsp_irq_cfg(void);                // Used internally by BSP
+
+/** @} (end addtogroup BSP_MCU_PRV) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h
new file mode 100644
index 00000000..b640552f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h
@@ -0,0 +1,62 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_MCU_API_H
+#define BSP_MCU_API_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef struct st_bsp_event_info
+{
+    IRQn_Type   irq;
+    elc_event_t event;
+} bsp_event_info_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect);
+void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect);
+void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units);
+void R_BSP_SystemReset(void);
+void R_BSP_CPUReset(bsp_reset_t cpu);
+void R_BSP_CPUResetAutoRelease(bsp_reset_t cpu);
+void R_BSP_CPUResetRelease(bsp_reset_t cpu);
+void R_BSP_ModuleResetEnable(bsp_module_reset_t module_to_enable);
+void R_BSP_ModuleResetDisable(bsp_module_reset_t module_to_disable);
+
+#if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+void R_BSP_CPUClusterResetAutoReleaseControl(bsp_reset_t cpu, bsp_cluster_reset_auto_release_t release);
+
+#endif
+
+#if BSP_FEATURE_BSP_SLAVE_STOP_SUPPORTED
+void R_BSP_SlaveStop(bsp_bus_slave_t bus_slave);
+void R_BSP_SlaveStopRelease(bsp_bus_slave_t bus_slave);
+
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h
new file mode 100644
index 00000000..9d372b26
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h
@@ -0,0 +1,487 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_MODULE_H
+#define BSP_MODULE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Cancels the module stop state.
+ *
+ * @param      ip       fsp_ip_t enum value for the module to be stopped
+ * @param      channel  The channel. Use channel 0 for modules without channels.
+ **********************************************************************************************************************/
+#define R_BSP_MODULE_START(ip, channel)             {FSP_CRITICAL_SECTION_DEFINE;                                   \
+                                                     FSP_CRITICAL_SECTION_ENTER;                                    \
+                                                     BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \
+                                                     BSP_MSTP_REG_ ## ip(channel);                                  \
+                                                     BSP_MSTP_DMY_ ## ip(channel);                                  \
+                                                     BSP_MSTP_DMY_ ## ip(channel);                                  \
+                                                     BSP_MSTP_DMY_ ## ip(channel);                                  \
+                                                     BSP_MSTP_DMY_ ## ip(channel);                                  \
+                                                     BSP_MSTP_DMY_ ## ip(channel);                                  \
+                                                     BSP_MSTP_DMY_ ## ip(channel);                                  \
+                                                     BSP_MSTP_DMY_ ## ip(channel);                                  \
+                                                     FSP_CRITICAL_SECTION_EXIT;}
+
+/*******************************************************************************************************************//**
+ * Enables the module stop state.
+ *
+ * @param      ip       fsp_ip_t enum value for the module to be stopped
+ * @param      channel  The channel. Use channel 0 for modules without channels.
+ **********************************************************************************************************************/
+#define R_BSP_MODULE_STOP(ip, channel)              {FSP_CRITICAL_SECTION_DEFINE;                                  \
+                                                     FSP_CRITICAL_SECTION_ENTER;                                   \
+                                                     BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \
+                                                     BSP_MSTP_REG_ ## ip(channel);                                 \
+                                                     FSP_CRITICAL_SECTION_EXIT;}
+
+/** @} (end addtogroup BSP_MCU) */
+
+#define BSP_MSTP_REG_FSP_IP_BSC(channel)            R_SYSC_NS->MSTPCRA
+#define BSP_MSTP_BIT_FSP_IP_BSC(channel)            (1U)
+#define BSP_MSTP_DMY_FSP_IP_BSC(channel)            R_BSC->TOENR
+
+#define BSP_MSTP_REG_FSP_IP_XSPI(channel)           R_SYSC_NS->MSTPCRA
+#define BSP_MSTP_BIT_FSP_IP_XSPI(channel)           (1U << (4U + channel))
+#define BSP_MSTP_DMY_FSP_IP_XSPI(channel)           (0 >= channel) ? R_XSPI0->WRAPCFG : R_XSPI1->WRAPCFG
+
+#define BSP_MSTP_REG_FSP_IP_SCI(channel)            *((4U >= channel) ? &R_SYSC_NS->MSTPCRA : &R_SYSC_S->MSTPCRG)
+#define BSP_MSTP_BIT_FSP_IP_SCI(channel)            ((4U >= channel) ? (1U << (8U + channel)) : (1U))
+#define BSP_MSTP_DMY_FSP_IP_SCI(channel)            (0 >= channel) ? R_SCI0->RDR : ((1 >= channel) ? R_SCI1->RDR :         \
+                                                                                    ((2 >=                                 \
+                                                                                      channel) ? R_SCI2->RDR : ((3 >=      \
+                                                                                                                 channel)  \
+                                                                                                                ? R_SCI3   \
+                                                                                                                ->RDR :    \
+                                                                                                                ((4        \
+                                                                                                                  >=       \
+                                                                                                                  channel) \
+                                                                                                                 ?         \
+                                                                                                                 R_SCI4    \
+                                                                                                                 ->RDR :   \
+                                                                                                                 R_SCI5    \
+                                                                                                                 ->        \
+                                                                                                                 RDR))))
+
+#if BSP_FEATURE_SCIE_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_SCIE(channel)          R_SYSC_NS->MSTPCRA
+ #define BSP_MSTP_BIT_FSP_IP_SCIE(channel)          (1U << (16U + channel))
+ #define BSP_MSTP_DMY_FSP_IP_SCIE(channel)          (0 >= channel) ? R_SCIE0->RDR : \
+    ((1 >= channel) ? R_SCIE1->RDR :                                                \
+     ((2 >= channel) ? R_SCIE2->RDR :                                               \
+      ((3 >= channel) ? R_SCIE3->RDR :                                              \
+       ((4 >= channel) ? R_SCIE4->RDR :                                             \
+        ((5 >= channel) ? R_SCIE5->RDR :                                            \
+         ((6 >= channel) ? R_SCIE6->RDR :                                           \
+          ((7 >= channel) ? R_SCIE7->RDR :                                          \
+           ((8 >= channel) ? R_SCIE8->RDR :                                         \
+            ((9 >= channel) ? R_SCIE9->RDR :                                        \
+             ((10 >= channel) ? R_SCIE10->RDR :                                     \
+              R_SCIE11->RDR))))))))))
+#endif
+
+#define BSP_MSTP_REG_FSP_IP_IIC(channel)            *((1U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SYSC_S->MSTPCRG)
+#define BSP_MSTP_BIT_FSP_IP_IIC(channel)            ((1U >= channel) ? (1U << (0U + channel)) : (1U << (1U)))
+#define BSP_MSTP_DMY_FSP_IP_IIC(channel)            (0 >= channel) ? R_IIC0->ICCR1 : ((1 >= channel) ? R_IIC1->ICCR1 \
+                                                                                      : R_IIC2->ICCR1)
+
+#define BSP_MSTP_REG_FSP_IP_SPI(channel)            *((2U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SYSC_S->MSTPCRG)
+#define BSP_MSTP_BIT_FSP_IP_SPI(channel)            ((2U >= channel) ? (1U << (4U + channel)) : (1U << (2U)))
+#define BSP_MSTP_DMY_FSP_IP_SPI(channel)            (0 >= channel) ? R_SPI0->SPCKD : ((1 >= channel) ? R_SPI1->SPCKD : \
+                                                                                      ((2 >=                           \
+                                                                                        channel) ? R_SPI2->SPCKD :     \
+                                                                                       R_SPI3                          \
+                                                                                       ->SPCKD))
+
+#define BSP_MSTP_REG_FSP_IP_MTU3(channel)           R_SYSC_NS->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_MTU3(channel)           (1U)
+#define BSP_MSTP_DMY_FSP_IP_MTU3(channel)           R_MTU0->TCR
+
+#if (18 == BSP_FEATURE_GPT_CHANNEL)
+ #define BSP_MSTP_REG_FSP_IP_GPT(channel)           *((13U >= channel) ? &R_SYSC_NS->MSTPCRC : &R_SYSC_S->MSTPCRG)
+ #define BSP_MSTP_BIT_FSP_IP_GPT(channel)           ((6U >= channel) ? (1U << (1U)) : ((13U >= channel) ? \
+                                                                                       (1U << (2U)) : (1U << (3U))))
+ #define BSP_MSTP_DMY_FSP_IP_GPT(channel)           (6 >=                                                              \
+                                                     channel) ? R_GPT0->GTSTR : ((13 >=                                \
+                                                                                  channel) ? R_GPT7->GTSTR : R_GPT14-> \
+                                                                                 GTSTR)
+#elif (56 == BSP_FEATURE_GPT_CHANNEL)
+ #define BSP_MSTP_REG_FSP_IP_GPT(channel)           *((51U >= channel) ? &R_SYSC_NS->MSTPCRC : &R_SYSC_S->MSTPCRG)
+ #define BSP_MSTP_BIT_FSP_IP_GPT(channel)           ((4U >= channel) ? (1U << (1U)) :            \
+                                                     ((9U >= channel) ? (1U << (2U)) :           \
+                                                      ((14U >= channel) ? (1U << (16U)) :        \
+                                                       ((19U >= channel) ? (1U << (17U)) :       \
+                                                        ((24U >= channel) ? (1U << (18U)) :      \
+                                                         ((29U >= channel) ? (1U << (19U)) :     \
+                                                          ((34U >= channel) ? (1U << (20U)) :    \
+                                                           ((39U >= channel) ? (1U << (21U)) :   \
+                                                            ((44U >= channel) ? (1U << (22U)) :  \
+                                                             ((51U >= channel) ? (1U << (23U)) : \
+                                                              (1U << (3U))))))))))))
+
+ #define BSP_MSTP_DMY_FSP_IP_GPT(channel)           (4 >= channel) ? R_GPT00_0->GTSTR : \
+    ((9 >= channel) ? R_GPT01_0->GTSTR :                                                \
+     ((14 >= channel) ? R_GPT02_0->GTSTR :                                              \
+      ((19 >= channel) ? R_GPT03_0->GTSTR :                                             \
+       ((24 >= channel) ? R_GPT04_0->GTSTR :                                            \
+        ((29 >= channel) ? R_GPT05_0->GTSTR :                                           \
+         ((34 >= channel) ? R_GPT06_0->GTSTR :                                          \
+          ((39 >= channel) ? R_GPT07_0->GTSTR :                                         \
+           ((44 >= channel) ? R_GPT08_0->GTSTR :                                        \
+            ((51 >= channel) ? R_GPT09_0->GTSTR :                                       \
+             R_GPT10_0->GTSTR)))))))))
+
+#endif
+#if (1 == BSP_FEATURE_TFU_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_TFU(channel)           R_SYSC_NS->MSTPCRC
+ #define BSP_MSTP_BIT_FSP_IP_TFU(channel)           (1U << (5U))
+ #define BSP_MSTP_DMY_FSP_IP_TFU(channel)           R_TFU->TRGSTS
+#elif (2 == BSP_FEATURE_TFU_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_TFU(channel)           R_SYSC_NS->MSTPCRC
+ #define BSP_MSTP_BIT_FSP_IP_TFU(channel)           ((0 == channel) ? (1U << (5U)) : (1U << (24U)))
+ #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+  #define BSP_MSTP_DMY_FSP_IP_TFU(channel)          R_TFU0->TRGSTS
+ #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+  #define BSP_MSTP_DMY_FSP_IP_TFU(channel)          R_TFU1->TRGSTS
+ #endif
+#endif
+
+#if (2 == BSP_FEATURE_ADC_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_ADC12(channel)         R_SYSC_NS->MSTPCRC
+ #define BSP_MSTP_BIT_FSP_IP_ADC12(channel)         (1U << (6U + channel))
+ #define BSP_MSTP_DMY_FSP_IP_ADC12(channel)         (0 >= channel) ? R_ADC120->ADCSR : R_ADC121->ADCSR
+#elif (3 == BSP_FEATURE_ADC_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_ADC12(channel)         R_SYSC_NS->MSTPCRC
+ #define BSP_MSTP_BIT_FSP_IP_ADC12(channel)         ((1 >= channel) ? (1U << (6U + channel)) : (1U << (25U)))
+ #define BSP_MSTP_DMY_FSP_IP_ADC12(channel)         ((0 >= channel) ? R_ADC120->ADCSR :  \
+                                                     ((1 >= channel) ? R_ADC121->ADCSR : \
+                                                      R_ADC122->ADCSR))
+#endif
+
+#if (2 == BSP_FEATURE_DSMIF_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_DSMIF(channel)         R_SYSC_NS->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_DSMIF(channel)         (1U << (0U + channel))
+ #define BSP_MSTP_DMY_FSP_IP_DSMIF(channel)         (0 >= channel) ? R_DSMIF0->DSSEICR : R_DSMIF1->DSSEICR
+#elif (10 == BSP_FEATURE_DSMIF_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_DSMIF(channel)         R_SYSC_NS->MSTPCRD
+ #define BSP_MSTP_BIT_FSP_IP_DSMIF(channel)         ((1 >= channel) ? (1U << (0U + channel)) : (1U << (14U + channel)))
+ #define BSP_MSTP_DMY_FSP_IP_DSMIF(channel)         (0 >= channel) ? R_DSMIF0->DSSEICR : \
+    ((1 >= channel) ? R_DSMIF1->DSSEICR :                                                \
+     ((2 >= channel) ? R_DSMIF2->DSSEICR :                                               \
+      ((3 >= channel) ? R_DSMIF3->DSSEICR :                                              \
+       ((4 >= channel) ? R_DSMIF4->DSSEICR :                                             \
+        ((5 >= channel) ? R_DSMIF5->DSSEICR :                                            \
+         ((6 >= channel) ? R_DSMIF6->DSSEICR :                                           \
+          ((7 >= channel) ? R_DSMIF7->DSSEICR :                                          \
+           ((8 >= channel) ? R_DSMIF8->DSSEICR :                                         \
+            R_DSMIF9->DSSEICR))))))))
+#endif
+
+#define BSP_MSTP_REG_FSP_IP_CMT(channel)            R_SYSC_NS->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_CMT(channel)            (1U << (2U + channel))
+#define BSP_MSTP_DMY_FSP_IP_CMT(channel)            (0 >=                                                                \
+                                                     channel) ? R_CMT->UNT[0].CMSTR0 : ((1 >=                            \
+                                                                                         channel) ? R_CMT->UNT[1].CMSTR0 \
+                                                                                        : R_CMT->UNT[2].CMSTR0)
+
+#define BSP_MSTP_REG_FSP_IP_CMTW(channel)           R_SYSC_NS->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_CMTW(channel)           (1U << (5U + channel))
+#define BSP_MSTP_DMY_FSP_IP_CMTW(channel)           (0 >= channel) ? R_CMTW0->CMWSTR : R_CMTW1->CMWSTR
+
+#define BSP_MSTP_REG_FSP_IP_TSU(channel)            R_SYSC_NS->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_TSU(channel)            (1U << (7U))
+#if (1 == BSP_FEATURE_TSU_VERSION)
+ #define BSP_MSTP_DMY_FSP_IP_TSU(channel)           R_TSU->TSUSS
+#else
+ #define BSP_MSTP_DMY_FSP_IP_TSU(channel)           R_TSU_B0->SSR
+#endif
+
+#define BSP_MSTP_REG_FSP_IP_DOC(channel)            R_SYSC_NS->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_DOC(channel)            (1U << (8U))
+#define BSP_MSTP_DMY_FSP_IP_DOC(channel)            R_DOC->DOCR
+
+#define BSP_MSTP_REG_FSP_IP_CRC(channel)            *((0U == channel) ? &R_SYSC_NS->MSTPCRD : &R_SYSC_S->MSTPCRG)
+#define BSP_MSTP_BIT_FSP_IP_CRC(channel)            ((0U == channel) ? (1U << (9U)) : (1U << (4U)))
+#define BSP_MSTP_DMY_FSP_IP_CRC(channel)            (0 >= channel) ? R_CRC0->CRCDIR : R_CRC1->CRCDIR
+
+#define BSP_MSTP_REG_FSP_IP_CANFD(channel)          R_SYSC_NS->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_CANFD(channel)          (1U << (10U))
+#define BSP_MSTP_DMY_FSP_IP_CANFD(channel)          R_CANFD->CFDGIPV
+
+#define BSP_MSTP_REG_FSP_IP_CKIO(channel)           R_SYSC_NS->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_CKIO(channel)           (1U << (11U))
+#define BSP_MSTP_DMY_FSP_IP_CKIO(channel)           R_BSC->TOENR
+
+#if (1 == BSP_FEATURE_GMAC_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_GMAC(channel)          R_SYSC_NS->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_GMAC(channel)          (1U)
+ #define BSP_MSTP_DMY_FSP_IP_GMAC(channel)          R_GMAC->MAC_Configuration
+#elif (3 == BSP_FEATURE_GMAC_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_GMAC(channel)          R_SYSC_NS->MSTPCRE
+ #define BSP_MSTP_BIT_FSP_IP_GMAC(channel)          ((0U == channel) ? (1U) : (1U << (15U + channel)))
+ #define BSP_MSTP_DMY_FSP_IP_GMAC(channel)          ((0 >= channel) ? R_GMAC0->MAC_Configuration :  \
+                                                     ((1 >= channel) ? R_GMAC1->MAC_Configuration : \
+                                                      R_GMAC2->MAC_Configuration))
+#endif
+
+#define BSP_MSTP_REG_FSP_IP_ETHSW(channel)          R_SYSC_NS->MSTPCRE
+#define BSP_MSTP_BIT_FSP_IP_ETHSW(channel)          (1U << (1U))
+#define BSP_MSTP_DMY_FSP_IP_ETHSW(channel)          R_ETHSW->REVISION
+
+#define BSP_MSTP_REG_FSP_IP_ESC(channel)            R_SYSC_NS->MSTPCRE
+#define BSP_MSTP_BIT_FSP_IP_ESC(channel)            (1U << (2U))
+#define BSP_MSTP_DMY_FSP_IP_ESC(channel)            R_ESC->TYPE
+
+#define BSP_MSTP_REG_FSP_IP_ETHSS(channel)          R_SYSC_NS->MSTPCRE
+#define BSP_MSTP_BIT_FSP_IP_ETHSS(channel)          (1U << (3U))
+#define BSP_MSTP_DMY_FSP_IP_ETHSS(channel)          R_ETHSS->PRCMD
+
+#define BSP_MSTP_REG_FSP_IP_USBHS(channel)          R_SYSC_NS->MSTPCRE
+#define BSP_MSTP_BIT_FSP_IP_USBHS(channel)          (1U << (8U))
+#define BSP_MSTP_DMY_FSP_IP_USBHS(channel)          R_USBHC->HCREVISION
+
+#if BSP_FEATURE_BSP_TRACE_CLOCK_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_TRACECLOCK(channel)    R_SYSC_S->MSTPCRF
+ #define BSP_MSTP_BIT_FSP_IP_TRACECLOCK(channel)    (1U << (0U))
+ #define BSP_MSTP_DMY_FSP_IP_TRACECLOCK(channel) /* No dummy read is required after module stop. */
+#endif
+
+#define BSP_MSTP_REG_FSP_IP_RTC(channel)            R_SYSC_S->MSTPCRG
+#define BSP_MSTP_BIT_FSP_IP_RTC(channel)            (1U << (5U))
+#define BSP_MSTP_DMY_FSP_IP_RTC(channel) /* After module stop release, the waiting process is performed by the driver, \
+                                          * so this macro does not define a register for dummy read. */
+
+#if (4 == BSP_FEATURE_CGC_CLMA_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_CLMA(channel)          R_SYSC_S->MSTPCRG
+ #define BSP_MSTP_BIT_FSP_IP_CLMA(channel)          ((2U >= channel) ? \
+                                                     (1U << (9U + channel)) : (1U << (8U)))
+ #define BSP_MSTP_DMY_FSP_IP_CLMA(channel)          (0 >=                                                               \
+                                                     channel) ? R_CLMA0->CTL0 : ((1 >=                                  \
+                                                                                  channel) ? R_CLMA1->CTL0 : ((2 >=     \
+                                                                                                               channel) \
+                                                                                                              ?         \
+                                                                                                              R_CLMA2-> \
+                                                                                                              CTL0 :    \
+                                                                                                              R_CLMA3-> \
+                                                                                                              CTL0))
+#elif (7 == BSP_FEATURE_CGC_CLMA_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_CLMA(channel)          R_SYSC_S->MSTPCRG
+ #define BSP_MSTP_BIT_FSP_IP_CLMA(channel)          ((5U >= channel) ? \
+                                                     (1U << (9U + channel)) : (1U << (8U)))
+ #define BSP_MSTP_DMY_FSP_IP_CLMA(channel)          ((0 >= channel) ? R_CLMA0->CTL0 :      \
+                                                     ((1 >= channel) ? R_CLMA1->CTL0 :     \
+                                                      ((2 >= channel) ? R_CLMA2->CTL0 :    \
+                                                       ((3 >= channel) ? R_CLMA3->CTL0 :   \
+                                                        ((4 >= channel) ? R_CLMA4->CTL0 :  \
+                                                         ((5 >= channel) ? R_CLMA5->CTL0 : \
+                                                          R_CLMA6->CTL0))))))
+#endif
+
+#if BSP_FEATURE_BSP_SHOSTIF_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_SHOSTIF(channel)       R_SYSC_S->MSTPCRI
+ #define BSP_MSTP_BIT_FSP_IP_SHOSTIF(channel)       (1U << (1U))
+ #define BSP_MSTP_DMY_FSP_IP_SHOSTIF(channel)       R_SHOSTIF->CTRLR0
+#endif
+
+#if BSP_FEATURE_BSP_PHOSTIF_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_PHOSTIF(channel)       R_SYSC_S->MSTPCRI
+ #define BSP_MSTP_BIT_FSP_IP_PHOSTIF(channel)       (1U << (0U))
+ #define BSP_MSTP_DMY_FSP_IP_PHOSTIF(channel)       R_PHOSTIF->HIFBCC
+#endif
+
+#if (2U == BSP_FEATURE_BSP_AFMT_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_AFMT(channel)          *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK)
+ #define BSP_MSTP_BIT_FSP_IP_AFMT(channel)          (1U << (0U))
+ #define BSP_MSTP_DMY_FSP_IP_AFMT(channel)          (0 == channel) ? R_AFMT0->ENC1RXDATA0 : R_AFMT1->ENC1RXDATA0
+#elif (14U == BSP_FEATURE_BSP_AFMT_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_AFMT(channel)          *((8U >= channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK)
+ #define BSP_MSTP_BIT_FSP_IP_AFMT(channel)          ((8U >= channel) ? \
+                                                     (1U << (channel * 4U)) : (1U << ((channel - 8U) * 4U)))
+ #define BSP_MSTP_DMY_FSP_IP_AFMT(channel)          (0 >= channel) ? R_AFMT0->ENC1RXDATA0 : \
+    ((1 >= channel) ? R_AFMT1->ENC1RXDATA0 :                                                \
+     ((2 >= channel) ? R_AFMT2->ENC1RXDATA0 :                                               \
+      ((3 >= channel) ? R_AFMT3->ENC1RXDATA0 :                                              \
+       ((4 >= channel) ? R_AFMT4->ENC1RXDATA0 :                                             \
+        ((5 >= channel) ? R_AFMT5->ENC1RXDATA0 :                                            \
+         ((6 >= channel) ? R_AFMT6->ENC1RXDATA0 :                                           \
+          ((7 >= channel) ? R_AFMT7->ENC1RXDATA0 :                                          \
+           ((8 >= channel) ? R_AFMT8->ENC1RXDATA0 :                                         \
+            ((9 >= channel) ? R_AFMT9->ENC1RXDATA0 :                                        \
+             ((10 >= channel) ? R_AFMT10->ENC1RXDATA0 :                                     \
+              ((11 >= channel) ? R_AFMT11->ENC1RXDATA0 :                                    \
+               ((12 >= channel) ? R_AFMT12->ENC1RXDATA0 :                                   \
+                ((13 >= channel) ? R_AFMT13->ENC1RXDATA0 :                                  \
+                 ((14 >= channel) ? R_AFMT14->ENC1RXDATA0 :                                 \
+                  R_AFMT15->ENC1RXDATA0))))))))))))))
+#endif
+
+#if (2 == BSP_FEATURE_BSP_HDSL_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_HDSL(channel)          *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK)
+ #define BSP_MSTP_BIT_FSP_IP_HDSL(channel)          (1U << (1U))
+ #define BSP_MSTP_DMY_FSP_IP_HDSL(channel)          (0 == channel) ? R_HDSLD0->SYS_CTRL : R_HDSLD1->SYS_CTRL
+#elif (14 == BSP_FEATURE_BSP_HDSL_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_HDSL(channel)          *((8U >= channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK)
+ #define BSP_MSTP_BIT_FSP_IP_HDSL(channel)          ((8U >= channel) ?                      \
+                                                     (1U << ((channel * 4U) + 1U)) : (1U << \
+                                                                                      (((channel - 8U) * 4U) + 1U)))
+ #define BSP_MSTP_DMY_FSP_IP_HDSL(channel)          (0 >= channel) ? R_HDSLD0->SYS_CTRL : \
+    ((1 >= channel) ? R_HDSLD1->SYS_CTRL :                                                \
+     ((2 >= channel) ? R_HDSLD2->SYS_CTRL :                                               \
+      ((3 >= channel) ? R_HDSLD3->SYS_CTRL :                                              \
+       ((4 >= channel) ? R_HDSLD4->SYS_CTRL :                                             \
+        ((5 >= channel) ? R_HDSLD5->SYS_CTRL :                                            \
+         ((6 >= channel) ? R_HDSLD6->SYS_CTRL :                                           \
+          ((7 >= channel) ? R_HDSLD7->SYS_CTRL :                                          \
+           ((8 >= channel) ? R_HDSLD8->SYS_CTRL :                                         \
+            ((9 >= channel) ? R_HDSLD9->SYS_CTRL :                                        \
+             ((10 >= channel) ? R_HDSLD10->SYS_CTRL :                                     \
+              ((11 >= channel) ? R_HDSLD11->SYS_CTRL :                                    \
+               ((12 >= channel) ? R_HDSLD12->SYS_CTRL :                                   \
+                ((13 >= channel) ? R_HDSLD13->SYS_CTRL :                                  \
+                 ((14 >= channel) ? R_HDSLD14->SYS_CTRL :                                 \
+                  R_HDSLD15->SYS_CTRL))))))))))))))
+#endif
+
+#if (2 == BSP_FEATURE_BSP_BISS_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_BISS(channel)          *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK)
+ #define BSP_MSTP_BIT_FSP_IP_BISS(channel)          (1U << (2U))
+ #define BSP_MSTP_DMY_FSP_IP_BISS(channel)          (0 == channel) ? R_BISS0->SCDATA[0].L : R_BISS1->SCDATA[0].L
+#elif (14 == BSP_FEATURE_BSP_BISS_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_BISS(channel)          *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK)
+ #define BSP_MSTP_BIT_FSP_IP_BISS(channel)          ((8U >= channel) ?                      \
+                                                     (1U << ((channel * 4U) + 2U)) : (1U << \
+                                                                                      (((channel - 8U) * 4U) + 2U)))
+
+ #define BSP_MSTP_DMY_FSP_IP_BISS(channel)          (0 == channel) ? R_BISS0->SCDATAL1 : \
+    ((1 >= channel) ? R_BISS1->SCDATAL1 :                                                \
+     ((2 >= channel) ? R_BISS2->SCDATAL1 :                                               \
+      ((3 >= channel) ? R_BISS3->SCDATAL1 :                                              \
+       ((4 >= channel) ? R_BISS4->SCDATAL1 :                                             \
+        ((5 >= channel) ? R_BISS5->SCDATAL1 :                                            \
+         ((6 >= channel) ? R_BISS6->SCDATAL1 :                                           \
+          ((7 >= channel) ? R_BISS7->SCDATAL1 :                                          \
+           ((8 >= channel) ? R_BISS8->SCDATAL1 :                                         \
+            ((9 >= channel) ? R_BISS9->SCDATAL1 :                                        \
+             ((10 >= channel) ? R_BISS10->SCDATAL1 :                                     \
+              ((11 >= channel) ? R_BISS11->SCDATAL1 :                                    \
+               ((12 >= channel) ? R_BISS12->SCDATAL1 :                                   \
+                ((13 >= channel) ? R_BISS13->SCDATAL1 :                                  \
+                 ((14 >= channel) ? R_BISS14->SCDATAL1 :                                 \
+                  R_BISS5->SCDATAL1))))))))))))))
+#endif
+
+#if (2 == BSP_FEATURE_BSP_ENDAT_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_ENDAT(channel)         *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK)
+ #define BSP_MSTP_BIT_FSP_IP_ENDAT(channel)         (1U << (3U))
+ #define BSP_MSTP_DMY_FSP_IP_ENDAT(channel)         (0 == channel) ? R_ENDAT0->SEND : R_ENDAT1->SEND
+#elif (14 == BSP_FEATURE_BSP_ENDAT_UNIT)
+ #define BSP_MSTP_REG_FSP_IP_ENDAT(channel)         *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK)
+ #define BSP_MSTP_BIT_FSP_IP_ENDAT(channel)         ((8U >= channel) ?                      \
+                                                     (1U << ((channel * 4U) + 3U)) : (1U << \
+                                                                                      (((channel - 8U) * 4U) + 3U)))
+ #define BSP_MSTP_DMY_FSP_IP_ENDAT(channel)         (0 >= channel) ? R_ENDAT0->SEND : \
+    ((1 >= channel) ? R_ENDAT1->SEND :                                                \
+     ((2 >= channel) ? R_ENDAT2->SEND :                                               \
+      ((3 >= channel) ? R_ENDAT3->SEND :                                              \
+       ((4 >= channel) ? R_ENDAT4->SEND :                                             \
+        ((5 >= channel) ? R_ENDAT5->SEND :                                            \
+         ((6 >= channel) ? R_ENDAT6->SEND :                                           \
+          ((7 >= channel) ? R_ENDAT7->SEND :                                          \
+           ((8 >= channel) ? R_ENDAT8->SEND :                                         \
+            ((9 >= channel) ? R_ENDAT9->SEND :                                        \
+             ((10 >= channel) ? R_ENDAT10->SEND :                                     \
+              ((11 >= channel) ? R_ENDAT11->SEND :                                    \
+               ((12 >= channel) ? R_ENDAT12->SEND :                                   \
+                ((13 >= channel) ? R_ENDAT13->SEND :                                  \
+                 ((14 >= channel) ? R_ENDAT14->SEND :                                 \
+                  R_ENDAT15->SEND))))))))))))))
+#endif
+
+#if BSP_FEATURE_BSP_ENCOUT_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_ENCOUT(channel)        R_SYSC_NS->MSTPCRL
+ #define BSP_MSTP_BIT_FSP_IP_ENCOUT(channel)        (1U << (0U))
+ #define BSP_MSTP_DMY_FSP_IP_ENCOUT(channel)        R_ENCOUT->CTL
+#endif
+
+#if BSP_FEATURE_BSP_DDRSS_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_DDRSS(channel)         R_SYSC_NS->MSTPCRM
+ #define BSP_MSTP_BIT_FSP_IP_DDRSS(channel)         (1U << (0U))
+ #define BSP_MSTP_DMY_FSP_IP_DDRSS(channel)         R_DDRSS->DDR_MEMC_DENALI_CTL_00
+#endif
+
+#if BSP_FEATURE_BSP_LCDC_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_LCDC(channel)          R_SYSC_NS->MSTPCRM
+ #define BSP_MSTP_BIT_FSP_IP_LCDC(channel)          (1U << (4U))
+ #define BSP_MSTP_DMY_FSP_IP_LCDC(channel) /* After module stop release, the waiting process is performed by the driver, \
+                                            * so this macro does not define a register for dummy read. */
+#endif
+
+#if BSP_FEATURE_BSP_PCIE_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_PCIE(channel)          R_SYSC_NS->MSTPCRM
+ #define BSP_MSTP_BIT_FSP_IP_PCIE(channel)          (1U << (8U))
+ #define BSP_MSTP_DMY_FSP_IP_PCIE(channel)          R_PCIE_LNK->PCIE_LINKMODE
+#endif
+
+#if BSP_FEATURE_BSP_SDHI_SUPPORTED
+ #define BSP_MSTP_REG_FSP_IP_SDHI(channel)          R_SYSC_NS->MSTPCRM
+ #define BSP_MSTP_BIT_FSP_IP_SDHI(channel)          (1U << (12U + channel))
+ #define BSP_MSTP_DMY_FSP_IP_SDHI(channel)          (0 == channel) ? R_SDHI0->SD_CMD : R_SDHI1->SD_CMD
+#endif
+
+#if BSP_FEATURE_BSP_MSTP_CR52_CPU1_HAS_MSTPCRH
+ #define BSP_MSTP_REG_FSP_IP_CPU1(channel)          R_SYSC_S->MSTPCRH
+ #define BSP_MSTP_BIT_FSP_IP_CPU1(channel)          (1U << (1U))
+ #define BSP_MSTP_DMY_FSP_IP_CPU1(channel) /* No dummy read is required after module stop. */
+#endif
+
+#if BSP_FEATURE_BSP_MSTP_CR52_HAS_MSTPCRN
+ #define BSP_MSTP_REG_FSP_IP_CR52(channel)          R_SYSC_S->MSTPCRN
+ #define BSP_MSTP_BIT_FSP_IP_CR52(channel)          (1U << (channel))
+ #define BSP_MSTP_DMY_FSP_IP_CR52(channel)          (0 == channel) ? R_TCMAW->CPU0WAIT : \
+    R_TCMAW->CPU1WAIT
+#endif
+
+#if BSP_FEATURE_BSP_MSTP_CA55_HAS_MSTPCRN
+ #define BSP_MSTP_REG_FSP_IP_CA55(channel)          R_SYSC_S->MSTPCRN
+ #define BSP_MSTP_BIT_FSP_IP_CA55(channel)          (1U << (channel + 2U))
+ #define BSP_MSTP_DMY_FSP_IP_CA55(channel)          (0 == channel) ? R_CA55->RVBA[0].L : \
+    ((1 >= channel) ? R_CA55->RVBA[1].L :                                                \
+     ((2 >= channel) ? R_CA55->RVBA[2].L :                                               \
+      R_CA55->RVBA[3].L))
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c
new file mode 100644
index 00000000..3bf9799d
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c
@@ -0,0 +1,102 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY    (0xA500U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Used for holding reference counters for protection bits. */
+volatile uint16_t g_protect_counters[] =
+{
+    0U, 0U, 0U, 0U
+};
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */
+static const uint16_t g_prcr_masks[] =
+{
+    0x0001U,                           /* PRC0. */
+    0x0002U,                           /* PRC1. */
+    0x0004U,                           /* PRC2. */
+    0x0008U,                           /* PRC3. */
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ *        Enable register protection. Registers that are protected cannot be written to. Register protection is
+ *          enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
+ *
+ * @param[in] regs_to_protect Registers which have write protection enabled.
+ **********************************************************************************************************************/
+void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
+{
+    /* Is it safe to disable write access? */
+    if (0U != g_protect_counters[regs_to_protect])
+    {
+        /* Decrement the protect counter */
+        g_protect_counters[regs_to_protect]--;
+    }
+
+    /* Is it safe to disable write access? */
+    if (0U == g_protect_counters[regs_to_protect])
+    {
+        /** Enable protection using PRCR register. */
+
+        /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+         * disable writes. */
+        R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect]));
+        R_RWP_S->PRCRS  = ((R_RWP_S->PRCRS | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect]));
+    }
+}
+
+/*******************************************************************************************************************//**
+ *        Disable register protection. Registers that are protected cannot be written to. Register protection is
+ *          disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
+ *
+ * @param[in] regs_to_unprotect Registers which have write protection disabled.
+ **********************************************************************************************************************/
+void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)
+{
+    /* If this is first entry then disable protection. */
+    if (0U == g_protect_counters[regs_to_unprotect])
+    {
+        /** Disable protection using PRCR register. */
+
+        /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+         * disable writes. */
+        R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]);
+        R_RWP_S->PRCRS  = ((R_RWP_S->PRCRS | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]);
+    }
+
+    /** Increment the protect counter */
+    g_protect_counters[regs_to_unprotect]++;
+}
+
+/** @} (end addtogroup BSP_MCU) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h
new file mode 100644
index 00000000..130a82c8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h
@@ -0,0 +1,62 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_REGISTER_PROTECTION_H
+#define BSP_REGISTER_PROTECTION_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/** The different types of registers that can be protected. */
+typedef enum e_bsp_reg_protect
+{
+    /** Enables writing to the registers related to the clock generation circuit. */
+    BSP_REG_PROTECT_CGC = 0,
+
+    /** Enables writing to the registers related to low power consumption and reset. */
+    BSP_REG_PROTECT_LPC_RESET,
+
+    /** Enables writing to the registers related to GPIO. */
+    BSP_REG_PROTECT_GPIO,
+
+    /** Enables writing to the registers related to Non-Safety reg. */
+    BSP_REG_PROTECT_SYSTEM,
+} bsp_reg_protect_t;
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+void bsp_register_protect_open(void);  // Used internally by BSP
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_reset.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_reset.c
new file mode 100644
index 00000000..9342d583
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_reset.c
@@ -0,0 +1,372 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_RESET_MRCTL_BIT_SHIFT_MASK         (0x0000001FU)
+#define BSP_RESET_MRCTL_SELECT_MASK            (0x001F0000U)
+#define BSP_RESET_MRCTL_REGION_SELECT_MASK     (0x00400000U)
+
+#define BSP_RESET_RMR_RESET_REQUEST_AARCH64    (0x3)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Occur the system software reset.
+ **********************************************************************************************************************/
+void R_BSP_SystemReset (void)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+
+    /* System software reset. */
+    R_SYSC_S->SWRSYS = BSP_PRV_RESET_KEY;
+}
+
+/*******************************************************************************************************************//**
+ * Occur the CPU software reset.
+ *
+ * @param[in] cpu to be reset state.
+ *
+ * @note With Cortex-A55, you cannot use resets that are not automatically released when a software reset is executed.
+ **********************************************************************************************************************/
+void R_BSP_CPUReset (bsp_reset_t cpu)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+
+    if (BSP_RESET_CR52_0 == cpu)
+    {
+        /* CR52_0 software reset. */
+        R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_KEY;
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+#if defined(BSP_CFG_CORE_CR52) && (0 == BSP_CFG_CORE_CR52)
+        __asm volatile ("WFI");
+#endif
+    }
+
+#if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM)
+    else if (BSP_RESET_CR52_1 == cpu)
+    {
+        /* CR52_1 software reset. */
+        R_SYSC_S->SWRCPU1 = BSP_PRV_RESET_KEY;
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+ #if defined(BSP_CFG_CORE_CR52) && (1 == BSP_CFG_CORE_CR52)
+        __asm volatile ("WFI");
+ #endif
+    }
+#endif
+#if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+    else if (BSP_RESET_CA55_CLUSTER == cpu)
+    {
+        /* CA55_cluster software reset. */
+        R_SYSC_S->SWR55C = BSP_PRV_RESET_KEY;
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+    }
+#endif
+    else
+    {
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Occur the CPU software reset. When using this function, the CPU reset state is automatically released
+ * after an elapsed time corresponding to the setting value in SCKCR2.DIVSELSUB bit.
+ *
+ * @param[in] cpu to be reset state.
+ **********************************************************************************************************************/
+void R_BSP_CPUResetAutoRelease (bsp_reset_t cpu)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+
+    if (BSP_RESET_CR52_0 == cpu)
+    {
+        /* CR52_0 software reset. */
+        R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_KEY_AUTO_RELEASE;
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+#if defined(BSP_CFG_CORE_CR52) && (0 == BSP_CFG_CORE_CR52)
+        __asm volatile ("WFI");
+#endif
+    }
+
+#if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM)
+    else if (BSP_RESET_CR52_1 == cpu)
+    {
+        /* CR52_1 software reset. */
+        R_SYSC_S->SWRCPU1 = BSP_PRV_RESET_KEY_AUTO_RELEASE;
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+ #if defined(BSP_CFG_CORE_CR52) && (1 == BSP_CFG_CORE_CR52)
+        __asm volatile ("WFI");
+ #endif
+    }
+#endif
+#if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+    else if (BSP_RESET_CA55_CLUSTER == cpu)
+    {
+        /* CA55_cluster software reset. */
+        R_SYSC_S->SWR55C = BSP_PRV_RESET_KEY_AUTO_RELEASE;
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+    }
+ #if defined(BSP_CFG_CORE_CA55)
+    else if (BSP_RESET_CA55_0 == cpu)
+    {
+        /* CA55_0 software reset. */
+        __asm volatile (
+            "MOV  x0, %0                                              \n"
+            "MSR  RMR_EL3, x0                                         \n"
+            ::"r" (BSP_RESET_RMR_RESET_REQUEST_AARCH64) : "memory");
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+  #if (0 == BSP_CFG_CORE_CA55)
+        __asm volatile ("WFI");
+  #endif
+    }
+    else if (BSP_RESET_CA55_1 == cpu)
+    {
+        /* CA55_1 software reset. */
+        __asm volatile (
+            "MOV  x0, %0                                              \n"
+            "MSR  RMR_EL3, x0                                         \n"
+            ::"r" (BSP_RESET_RMR_RESET_REQUEST_AARCH64) : "memory");
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+  #if (1 == BSP_CFG_CORE_CA55)
+        __asm volatile ("WFI");
+  #endif
+    }
+    else if (BSP_RESET_CA55_2 == cpu)
+    {
+        /* CA55_2 software reset. */
+        __asm volatile (
+            "MOV  x0, %0                                              \n"
+            "MSR  RMR_EL3, x0                                         \n"
+            ::"r" (BSP_RESET_RMR_RESET_REQUEST_AARCH64) : "memory");
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+  #if (2 == BSP_CFG_CORE_CA55)
+        __asm volatile ("WFI");
+  #endif
+    }
+    else if (BSP_RESET_CA55_3 == cpu)
+    {
+        /* CA55_3 software reset. */
+        __asm volatile (
+            "MOV  x0, %0                                              \n"
+            "MSR  RMR_EL3, x0                                         \n"
+            ::"r" (BSP_RESET_RMR_RESET_REQUEST_AARCH64) : "memory");
+
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+  #if (3 == BSP_CFG_CORE_CA55)
+        __asm volatile ("WFI");
+  #endif
+    }
+ #endif
+#endif
+    else
+    {
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Release the CPU reset state.
+ *
+ * @param[in] cpu to be release reset state.
+ **********************************************************************************************************************/
+void R_BSP_CPUResetRelease (bsp_reset_t cpu)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+
+    if (BSP_RESET_CR52_0 == cpu)
+    {
+        /* Release CR52_0 reset state. */
+        R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_RELEASE_KEY;
+    }
+
+#if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM)
+    else if (BSP_RESET_CR52_1 == cpu)
+    {
+        /* Release CR52_1 reset state. */
+        R_SYSC_S->SWRCPU1 = BSP_PRV_RESET_RELEASE_KEY;
+    }
+#endif
+#if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+    else if (BSP_RESET_CA55_CLUSTER == cpu)
+    {
+        /* Release CA55_cluster software reset. */
+        R_SYSC_S->SWR55C = BSP_PRV_RESET_RELEASE_KEY;
+    }
+    else if (BSP_RESET_CA55_0 == cpu)
+    {
+        /* Release CA55_0 reset state. */
+        R_SYSC_S->SWR550 = BSP_PRV_RESET_RELEASE_KEY;
+    }
+    else if (BSP_RESET_CA55_1 == cpu)
+    {
+        /* Release CA55_1 reset state. */
+        R_SYSC_S->SWR551 = BSP_PRV_RESET_RELEASE_KEY;
+    }
+    else if (BSP_RESET_CA55_2 == cpu)
+    {
+        /* Release CA55_2 reset state. */
+        R_SYSC_S->SWR552 = BSP_PRV_RESET_RELEASE_KEY;
+    }
+    else if (BSP_RESET_CA55_3 == cpu)
+    {
+        /* Release CA55_3 reset state. */
+        R_SYSC_S->SWR553 = BSP_PRV_RESET_RELEASE_KEY;
+    }
+#endif
+    else
+    {
+        /* Do Nothing. */
+    }
+
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+}
+
+#if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
+
+/*******************************************************************************************************************//**
+ * Controls whether the core is automatically released from reset when a CA55 cluster reset is performed.
+ *
+ * @param[in] cpu to be release reset state.
+ * @param[in] release Enable/disable automatic reset release.
+ **********************************************************************************************************************/
+void R_BSP_CPUClusterResetAutoReleaseControl (bsp_reset_t cpu, bsp_cluster_reset_auto_release_t release)
+{
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+
+    if (BSP_RESET_CA55_0 == cpu)
+    {
+        /* Controls the automatic reset release of CA55_0. */
+        R_SYSC_S->SWR55ARC_b.ARC550 = release;
+    }
+    else if (BSP_RESET_CA55_1 == cpu)
+    {
+        /* Controls the automatic reset release of CA55_1. */
+        R_SYSC_S->SWR55ARC_b.ARC551 = release;
+    }
+    else if (BSP_RESET_CA55_2 == cpu)
+    {
+        /* Controls the automatic reset release of CA55_2. */
+        R_SYSC_S->SWR55ARC_b.ARC552 = release;
+    }
+    else if (BSP_RESET_CA55_3 == cpu)
+    {
+        /* Controls the automatic reset release of CA55_3. */
+        R_SYSC_S->SWR55ARC_b.ARC553 = release;
+    }
+    else
+    {
+        /* Do Nothing. */
+    }
+
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ *        Enable module reset state.
+ *
+ * @param[in] module_to_enable Modules to enable module reset state.
+ **********************************************************************************************************************/
+void R_BSP_ModuleResetEnable (bsp_module_reset_t module_to_enable)
+{
+    volatile uint32_t mrctl;
+    uint32_t        * p_reg;
+
+    /** When MRCTLn register exists in the safety region,
+     *  it is necessary to add an offset of safety region. */
+    p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA +
+            (((module_to_enable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) +
+             (module_to_enable & BSP_RESET_MRCTL_REGION_SELECT_MASK));
+    mrctl = 1U << (module_to_enable & BSP_RESET_MRCTL_BIT_SHIFT_MASK);
+
+    /** Enable module reset state using MRCTLE register. */
+    *p_reg |= mrctl;
+
+    /** To ensure processing after module reset. */
+    mrctl = *(volatile uint32_t *) (p_reg);
+}
+
+/*******************************************************************************************************************//**
+ * Disable module reset state.
+ *
+ * @param[in] module_to_disable Modules to disable module reset state.
+ *
+ * @note      After reset release is performed by the module control register, a dummy read is performed to allow access
+ *            to other than the RTC and LCDC. This is done several times according to the RZ microprocessor manual.
+ *            However, the dummy read count for the RTC and LCDC may not be met depending on the device used.
+ *            In that case, please perform additional dummy read processing after API execution.
+ *            For example, in the case of RZN2H, 300 dummy reads are required for RTC and
+ *            100 dummy reads are required for LCDC.
+ *
+ **********************************************************************************************************************/
+void R_BSP_ModuleResetDisable (bsp_module_reset_t module_to_disable)
+{
+    volatile uint32_t mrctl;
+    uint32_t        * p_reg;
+
+    /** When MRCTLn register exists in the safety region,
+     *  it is necessary to add an offset of safety region. */
+    p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA +
+            (((module_to_disable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) +
+             (module_to_disable & BSP_RESET_MRCTL_REGION_SELECT_MASK));
+    mrctl = 1U << (module_to_disable & BSP_RESET_MRCTL_BIT_SHIFT_MASK);
+
+    /** Disable module stop state using MRCTLn register. */
+    *p_reg &= ~mrctl;
+
+    /** In order to secure processing after release from module reset,
+     *  dummy read the same register.
+     *  Refer to "Notes on Module Reset Control Register Operation" of the RZ microprocessor manual. */
+    uint32_t dummy_read_cnt = BSP_FEATURE_BSP_MODULE_RESET_DUMMY_READ_COUNT;
+
+    while (dummy_read_cnt)
+    {
+        mrctl = *(volatile uint32_t *) (p_reg);
+        dummy_read_cnt--;
+    }
+}
+
+/** @} (end addtogroup BSP_MCU) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_reset.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_reset.h
new file mode 100644
index 00000000..78e5ad2d
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_reset.h
@@ -0,0 +1,196 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_RESET_H
+#define BSP_RESET_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Key code for writing reset register. */
+#define BSP_PRV_RESET_KEY                 (0x4321A501U)
+#define BSP_PRV_RESET_KEY_AUTO_RELEASE    (0x4321A502U)
+#define BSP_PRV_RESET_RELEASE_KEY         (0x00000000U)
+
+/* MRCTL register selection. Bits 16-20 assign values in order for the module control registers (A=0, E=4).
+ * Bit 24 indicates whether MRCTLn register is in the safety region. */
+#define BSP_RESET_MRCTLA_SELECT           (0x00000000U)
+#define BSP_RESET_MRCTLE_SELECT           (0x00040000U)
+#define BSP_RESET_MRCTLI_SELECT           (0x00480000U)
+#define BSP_RESET_MRCTLM_SELECT           (0x000C0000U)
+
+/* MRCTL register bit number.  */
+#define BSP_RESET_MRCTL_BIT0_SHIFT        (0x00000000U)
+#define BSP_RESET_MRCTL_BIT1_SHIFT        (0x00000001U)
+#define BSP_RESET_MRCTL_BIT2_SHIFT        (0x00000002U)
+#define BSP_RESET_MRCTL_BIT3_SHIFT        (0x00000003U)
+#define BSP_RESET_MRCTL_BIT4_SHIFT        (0x00000004U)
+#define BSP_RESET_MRCTL_BIT5_SHIFT        (0x00000005U)
+#define BSP_RESET_MRCTL_BIT6_SHIFT        (0x00000006U)
+#define BSP_RESET_MRCTL_BIT7_SHIFT        (0x00000007U)
+#define BSP_RESET_MRCTL_BIT8_SHIFT        (0x00000008U)
+#define BSP_RESET_MRCTL_BIT9_SHIFT        (0x00000009U)
+#define BSP_RESET_MRCTL_BIT10_SHIFT       (0x0000000AU)
+#define BSP_RESET_MRCTL_BIT11_SHIFT       (0x0000000BU)
+#define BSP_RESET_MRCTL_BIT12_SHIFT       (0x0000000CU)
+#define BSP_RESET_MRCTL_BIT13_SHIFT       (0x0000000DU)
+#define BSP_RESET_MRCTL_BIT14_SHIFT       (0x0000000EU)
+#define BSP_RESET_MRCTL_BIT15_SHIFT       (0x0000000FU)
+#define BSP_RESET_MRCTL_BIT16_SHIFT       (0x00000010U)
+#define BSP_RESET_MRCTL_BIT17_SHIFT       (0x00000011U)
+#define BSP_RESET_MRCTL_BIT18_SHIFT       (0x00000012U)
+#define BSP_RESET_MRCTL_BIT19_SHIFT       (0x00000013U)
+#define BSP_RESET_MRCTL_BIT20_SHIFT       (0x00000014U)
+#define BSP_RESET_MRCTL_BIT21_SHIFT       (0x00000015U)
+#define BSP_RESET_MRCTL_BIT22_SHIFT       (0x00000016U)
+#define BSP_RESET_MRCTL_BIT23_SHIFT       (0x00000017U)
+#define BSP_RESET_MRCTL_BIT24_SHIFT       (0x00000018U)
+#define BSP_RESET_MRCTL_BIT25_SHIFT       (0x00000019U)
+#define BSP_RESET_MRCTL_BIT26_SHIFT       (0x0000001AU)
+#define BSP_RESET_MRCTL_BIT27_SHIFT       (0x0000001BU)
+#define BSP_RESET_MRCTL_BIT28_SHIFT       (0x0000001CU)
+#define BSP_RESET_MRCTL_BIT29_SHIFT       (0x0000001DU)
+#define BSP_RESET_MRCTL_BIT30_SHIFT       (0x0000001EU)
+#define BSP_RESET_MRCTL_BIT31_SHIFT       (0x0000001FU)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/** CPU to be reset target.*/
+typedef enum e_bsp_reset
+{
+    BSP_RESET_CR52_0       = 0,        ///< Software reset for CR52_0
+    BSP_RESET_CR52_1       = 1,        ///< Software reset for CR52_1
+    BSP_RESET_CA55_CLUSTER = 2,        ///< Software reset for CA55_CLUSTER
+    BSP_RESET_CA55_0       = 3,        ///< Software reset for CA55_0
+    BSP_RESET_CA55_1       = 4,        ///< Software reset for CA55_1
+    BSP_RESET_CA55_2       = 5,        ///< Software reset for CA55_2
+    BSP_RESET_CA55_3       = 6,        ///< Software reset for CA55_3
+} bsp_reset_t;
+
+/** CA55 cluster reset auto reset release status. */
+typedef enum e_bsp_cluster_reset_auto_release
+{
+    BSP_CLUSTER_RESET_AUTO_RELEASE_DISABLE = 0,
+    BSP_CLUSTER_RESET_AUTO_RELEASE_ENABLE  = 1,
+} bsp_cluster_reset_auto_release_t;
+
+/** The different types of registers that can control the reset of peripheral modules related to Ethernet. */
+typedef enum e_bsp_module_reset
+{
+    /** Enables writing to the registers related to xSPI Unit 0 reset control. */
+    BSP_MODULE_RESET_XSPI0 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT),
+
+    /** Enables writing to the registers related to xSPI Unit 1 reset control. */
+    BSP_MODULE_RESET_XSPI1 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT),
+
+    /** Enables writing to the registers related to GMAC (PCLKH clock domain) reset control. */
+    BSP_MODULE_RESET_GMAC0_PCLKH = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT),
+
+    /** Enables writing to the registers related to GMAC (PCLKM clock domain) reset control. */
+    BSP_MODULE_RESET_GMAC0_PCLKM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT),
+
+    /** Enables writing to the registers related to ETHSW reset control. */
+    BSP_MODULE_RESET_ETHSW = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT),
+
+    /** Enables writing to the registers related to ESC (Bus clock domain) reset control. */
+    BSP_MODULE_RESET_ESC_BUS = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT),
+
+    /** Enables writing to the registers related to ESC (IP clock domain) reset control. */
+    BSP_MODULE_RESET_ESC_IP = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT),
+
+    /** Enables writing to the registers related to Ethernet subsystem register reset control. */
+    BSP_MODULE_RESET_ESC_ETH_SUBSYSTEM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT),
+
+    /** Enables writing to the registers related to MII converter reset control. */
+    BSP_MODULE_RESET_MII = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT6_SHIFT),
+
+    /** Enables writing to the registers related to GMAC Unit 1 (PCLKAH clock domain) reset control. */
+    BSP_MODULE_RESET_GMAC1_ACLK = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT16_SHIFT),
+
+    /** Enables writing to the registers related to GMAC Unit 1 (PCLKAM clock domain) reset control. */
+    BSP_MODULE_RESET_GMAC1_HCLK = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT17_SHIFT),
+
+    /** Enables writing to the registers related to GMAC Unit 2 (PCLKAH clock domain) reset control. */
+    BSP_MODULE_RESET_GMAC2_ACLK = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT18_SHIFT),
+
+    /** Enables writing to the registers related to GMAC Unit 2 (PCLKAM clock domain) reset control. */
+    BSP_MODULE_RESET_GMAC2_HCLK = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT19_SHIFT),
+
+    /** Enables writing to the registers related to PHOSTIF reset control. */
+    BSP_MODULE_RESET_PHOSTIF = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT),
+
+    /** Enables writing to the registers related to SHOSTIF (Master bus clock domain) reset control. */
+    BSP_MODULE_RESET_SHOSTIF_MASTER_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT),
+
+    /** Enables writing to the registers related to SHOSTIF (Slave bus clock domain) reset control. */
+    BSP_MODULE_RESET_SHOSTIF_SLAVE_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT),
+
+    /** Enables writing to the registers related to SHOSTIF (IP clock domain) reset control. */
+    BSP_MODULE_RESET_SHOSTIF_IP_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT),
+
+    /** Enables writing to the registers related to PCIE reset control. */
+    BSP_MODULE_RESET_PCIE = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT8_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS rst_n reset control. */
+    BSP_MODULE_RESET_DDRSS_RST_N = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT16_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS PwrOkln reset control. */
+    BSP_MODULE_RESET_DDRSS_RST_PWROKLN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT17_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS Reset reset control. */
+    BSP_MODULE_RESET_DDRSS_RESET = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT18_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS axi0_ARESETn reset control. */
+    BSP_MODULE_RESET_DDRSS_AXI0_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT19_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS axi1_ARESETn reset control. */
+    BSP_MODULE_RESET_DDRSS_AXI1_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT20_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS axi2_ARESETn reset control. */
+    BSP_MODULE_RESET_DDRSS_AXI2_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT21_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS axi3_ARESETn reset control. */
+    BSP_MODULE_RESET_DDRSS_AXI3_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT22_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS axi4_ARESETn reset control. */
+    BSP_MODULE_RESET_DDRSS_AXI4_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT23_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS MC_PRESETn reset control. */
+    BSP_MODULE_RESET_DDRSS_MC_PRESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT24_SHIFT),
+
+    /** Enables writing to the registers related to DDRSS PHY_PRESETn reset control. */
+    BSP_MODULE_RESET_DDRSS_PHY_PRESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT25_SHIFT),
+} bsp_module_reset_t;
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c
new file mode 100644
index 00000000..e0caa52e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c
@@ -0,0 +1,94 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#include <sys/types.h>
+#include <errno.h>
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+caddr_t _sbrk(int incr);
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * FSP implementation of the standard library _sbrk() function.
+ * @param[in]   inc  The number of bytes being asked for by malloc().
+ *
+ * @note This function overrides the _sbrk version that exists in the newlib library that is linked with.
+ *       That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and
+ *       worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc()
+ *       only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by
+ *       malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc().
+ * @retval        Address of allocated area if successful, -1 otherwise.
+ **********************************************************************************************************************/
+caddr_t _sbrk (int incr)
+{
+    extern char _Heap_Begin __asm("__HeapBase");  ///< Defined by the linker.
+
+    extern char _Heap_Limit __asm("__HeapLimit"); ///< Defined by the linker.
+
+    uint32_t      bytes            = (uint32_t) incr;
+    static char * current_heap_end = 0;
+    char        * current_block_address;
+
+    if (current_heap_end == 0)
+    {
+        current_heap_end = &_Heap_Begin;
+    }
+
+    current_block_address = current_heap_end;
+
+    /* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support
+     * unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple
+     * of 4. */
+    bytes = (bytes + 3U) & (~3U);
+    if (current_heap_end + bytes > &_Heap_Limit)
+    {
+        /** Heap has overflowed */
+        errno = ENOMEM;
+
+        return (caddr_t) -1;
+    }
+
+    current_heap_end += bytes;
+
+    return (caddr_t) current_block_address;
+}
+
+#endif
+
+/******************************************************************************************************************//**
+ * @} (end addtogroup BSP_MCU)
+ *********************************************************************************************************************/
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.c
new file mode 100644
index 00000000..f7cdd3b7
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.c
@@ -0,0 +1,84 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Private definition to set enumeration values. */
+#define BSP_PRV_SYTSEMFEN_ENABLE      (0x00000001U)
+#define BSP_PRV_RESOURCE_NOT_USED     (0x00000001U)
+#define BSP_SEMAPHORE_RESOURCE_MAX    (8U)
+#define BSP_PRV_SEMRCEN_ENABLE        (0xFFU)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Semaphore initialization.
+ **********************************************************************************************************************/
+void bsp_semaphore_init (void)
+{
+#if BSP_FEATURE_BSP_SEMAPHORE_SUPPORTED
+ #if BSP_FEATURE_SEM_SUPPORTED
+    uint32_t sem_num;
+
+    /* Disable register protection for semaphore related registers. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+
+    /* Enable read clear function. */
+    R_SEM->SYTSEMFEN = BSP_PRV_SYTSEMFEN_ENABLE;
+
+    for (sem_num = 0; sem_num < BSP_SEMAPHORE_RESOURCE_MAX; sem_num++)
+    {
+        /* Set the semaphore state not being used. */
+        R_SEM->SYTSEMF[sem_num] = BSP_PRV_RESOURCE_NOT_USED;
+    }
+
+    /* Enable register protection for semaphore related registers. */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+ #endif
+
+ #if BSP_FEATURE_MAILBOX_SEM_SUPPORTED
+    uint32_t sem_num;
+
+    /* Disable register protection for semaphore related registers. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
+
+    /* Enable read clear function for External Host and Internal CPUs. */
+    R_MBXSEM->SEMRCEN = BSP_PRV_SEMRCEN_ENABLE;
+
+    /* Enable read clear function for Internal CPUs. */
+    R_MBXSEM->SEMRCENAR = BSP_PRV_SEMRCEN_ENABLE;
+
+    for (sem_num = 0; sem_num < BSP_SEMAPHORE_RESOURCE_MAX; sem_num++)
+    {
+        /* Set the semaphore state not being used for External Host and Internal CPUs. */
+        R_MBXSEM->SEM[sem_num] = BSP_PRV_RESOURCE_NOT_USED;
+
+        /* Set the semaphore state not being used for Internal CPUs. */
+        R_MBXSEM->SEMAR[sem_num] = BSP_PRV_RESOURCE_NOT_USED;
+    }
+
+    /* Enable register protection for semaphore related registers. */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
+ #endif
+#endif
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.h
new file mode 100644
index 00000000..1703bde8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.h
@@ -0,0 +1,86 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_SEMAPHORE_H
+#define BSP_SEMAPHORE_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/** The semaphore resource state shared by CPU0 and CPU1 */
+typedef enum e_bsp_resource_state
+{
+    BSP_RESOURCE_STATE_BEING_USED     = 0, ///< Semaphore resource being used.
+    BSP_RESOURCE_STATE_NOT_BEING_USED = 1, ///< Semaphore resource not being used.
+} bsp_resource_state_t;
+
+/** The semaphore resource number shared by CPU0 and CPU1 */
+typedef enum e_bsp_resource_num
+{
+    BSP_RESOURCE_NUM_0 = 0,            ///< Semaphore resource number 0
+    BSP_RESOURCE_NUM_1 = 1,            ///< Semaphore resource number 1
+    BSP_RESOURCE_NUM_2 = 2,            ///< Semaphore resource number 2
+    BSP_RESOURCE_NUM_3 = 3,            ///< Semaphore resource number 3
+    BSP_RESOURCE_NUM_4 = 4,            ///< Semaphore resource number 4
+    BSP_RESOURCE_NUM_5 = 5,            ///< Semaphore resource number 5
+    BSP_RESOURCE_NUM_6 = 6,            ///< Semaphore resource number 6
+    BSP_RESOURCE_NUM_7 = 7,            ///< Semaphore resource number 7
+} bsp_resource_num_t;
+
+/** @} (end addtogroup BSP_MCU) */
+
+#if BSP_FEATURE_BSP_SEMAPHORE_SUPPORTED
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Read semaphore resource status. When SYTSEMFEN = 1, reading this status clear the resource status.
+ *
+ * @param[in]  sem_num Semaphore number to read resource status.
+ *
+ * @retval     Resource status.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_BSP_SemaphoreStateRead (bsp_resource_num_t sem_num)
+{
+ #if BSP_FEATURE_SEM_SUPPORTED
+    uint32_t sem = R_SEM->SYTSEMF[sem_num];
+ #elif BSP_FEATURE_MAILBOX_SEM_SUPPORTED
+    uint32_t sem = R_MBXSEM->SEM[sem_num];
+ #else
+    uint32_t sem = 0;
+ #endif
+
+    return sem;
+}
+
+#endif
+
+/* Public functions defined in bsp.h */
+void bsp_semaphore_init(void);         // Used internally by BSP
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.c
new file mode 100644
index 00000000..7345579c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.c
@@ -0,0 +1,88 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_SLAVE_STOP_SSTPCR_OFFSET_MASK    (0xFFFFU << 16U)
+#define BSP_SLAVE_STOP_REQ_POS_MASK          (0xFFU << 8U)
+#define BSP_SLAVE_STOP_ACK_POS_MASK          (0xFFU)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ *
+ * @{
+ **********************************************************************************************************************/
+#if BSP_FEATURE_BSP_SLAVE_STOP_SUPPORTED
+
+/*******************************************************************************************************************//**
+ * Change the bus slaves from bus stop to normal operation in order to access to the AXI-type slave I/F safely
+ *
+ * @param[in] bus_slave to be released from bus stop state.
+ **********************************************************************************************************************/
+void R_BSP_SlaveStopRelease (bsp_bus_slave_t bus_slave)
+{
+    uint32_t            req_pos;
+    uint32_t            req_bit_msk;
+    uint32_t            ack_pos;
+    uint32_t            ack_bit_msk;
+    volatile uint32_t * p_reg;
+
+    p_reg       = (uint32_t *) &R_SSC->SSTPCR4 + ((bus_slave & BSP_SLAVE_STOP_SSTPCR_OFFSET_MASK) >> 16U);
+    req_pos     = (bus_slave & BSP_SLAVE_STOP_REQ_POS_MASK) >> 8U;
+    req_bit_msk = 1U << req_pos;
+    *p_reg     &= ~req_bit_msk;
+
+    ack_pos     = (bus_slave & BSP_SLAVE_STOP_ACK_POS_MASK);
+    ack_bit_msk = 1U << ack_pos;
+
+    FSP_HARDWARE_REGISTER_WAIT((*p_reg & ack_bit_msk) >> ack_pos, 0);
+}
+
+/*******************************************************************************************************************//**
+ * Stop the access to the bus slaves
+ *
+ * @param[in] bus_slave to be stoped
+ **********************************************************************************************************************/
+void R_BSP_SlaveStop (bsp_bus_slave_t bus_slave)
+{
+    uint32_t            req_pos;
+    uint32_t            req_bit_msk;
+    uint32_t            ack_pos;
+    uint32_t            ack_bit_msk;
+    volatile uint32_t * p_reg;
+
+    p_reg       = (uint32_t *) &R_SSC->SSTPCR4 + ((bus_slave & BSP_SLAVE_STOP_SSTPCR_OFFSET_MASK) >> 16U);
+    req_pos     = (bus_slave & BSP_SLAVE_STOP_REQ_POS_MASK) >> 8U;
+    req_bit_msk = 1U << req_pos;
+    *p_reg     |= req_bit_msk;
+
+    ack_pos     = (bus_slave & BSP_SLAVE_STOP_ACK_POS_MASK);
+    ack_bit_msk = 1U << ack_pos;
+
+    FSP_HARDWARE_REGISTER_WAIT((*p_reg & ack_bit_msk) >> ack_pos, 1);
+}
+
+#endif
+
+/** @} (end addtogroup BSP_MCU) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.h
new file mode 100644
index 00000000..7514c808
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.h
@@ -0,0 +1,69 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_SLAVE_STOP_H
+#define BSP_SLAVE_STOP_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_SLAVE_STOP_SSTPCR0_SELECT    (0x04000000U)
+#define BSP_SLAVE_STOP_SSTPCR1_SELECT    (0x04010000U)
+#define BSP_SLAVE_STOP_SSTPCR4_SELECT    (0x00000000U)
+#define BSP_SLAVE_STOP_SSTPCR5_SELECT    (0x00010000U)
+#define BSP_SLAVE_STOP_SSTPCR6_SELECT    (0x00020000U)
+#define BSP_SLAVE_STOP_SSTPCR7_SELECT    (0x00030000U)
+
+#define BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(req_pos, ack_pos)    (((req_pos) << 8U) | ((ack_pos) << 0U))
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+typedef enum e_bsp_bus_slave
+{
+    BSP_BUS_SLAVE_DDRSS_A0_IF = (BSP_SLAVE_STOP_SSTPCR0_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(0, 1)),
+    BSP_BUS_SLAVE_DDRSS_A1_IF = (BSP_SLAVE_STOP_SSTPCR0_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(4, 5)),
+    BSP_BUS_SLAVE_DDRSS_R2_IF = (BSP_SLAVE_STOP_SSTPCR4_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(0, 1)),
+    BSP_BUS_SLAVE_DDRSS_R3_IF = (BSP_SLAVE_STOP_SSTPCR4_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(4, 5)),
+    BSP_BUS_SLAVE_DDRSS_A4_IF = (BSP_SLAVE_STOP_SSTPCR0_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(8, 9)),
+    BSP_BUS_SLAVE_PCIE0       = (BSP_SLAVE_STOP_SSTPCR1_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(0, 1)),
+    BSP_BUS_SLAVE_PCIE1       = (BSP_SLAVE_STOP_SSTPCR1_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(4, 5)),
+    BSP_BUS_SLAVE_SDHI0       = (BSP_SLAVE_STOP_SSTPCR1_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(16, 17)),
+    BSP_BUS_SLAVE_SDHI1       = (BSP_SLAVE_STOP_SSTPCR1_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(20, 21)),
+    BSP_BUS_SLAVE_GIC600      = (BSP_SLAVE_STOP_SSTPCR5_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(16, 17)),
+    BSP_BUS_SLAVE_XSPI0       = (BSP_SLAVE_STOP_SSTPCR6_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(0, 1)),
+    BSP_BUS_SLAVE_XSPI1       = (BSP_SLAVE_STOP_SSTPCR6_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(4, 5)),
+    BSP_BUS_SLAVE_CR520_AXIS  = (BSP_SLAVE_STOP_SSTPCR7_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(0, 1)),
+    BSP_BUS_SLAVE_CR521_AXIS  = (BSP_SLAVE_STOP_SSTPCR7_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(4, 5)),
+    BSP_BUS_SLAVE_DDRAPB      = (BSP_SLAVE_STOP_SSTPCR4_SELECT | BSP_SLAVE_STOP_SSTPCR_REQ_ACK_POS(8, 8)),
+} bsp_bus_slave_t;
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tfu.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tfu.h
new file mode 100644
index 00000000..298c3108
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tfu.h
@@ -0,0 +1,836 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef RENESAS_TFU
+#define RENESAS_TFU
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* Mathematical Functions includes. */
+#ifdef __cplusplus
+ #include <cmath>
+#else
+ #include <math.h>
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+#define R_TFU_HYPOT_SCALING_FACTOR          0.607252935F
+#define R_TFU_HYPOT_SCALING_FACTOR_FIXED    326016448
+#define FIXED_POINT_FRACTIONAL_BITS         29U
+
+#ifdef __GNUC__                        /* and (arm)clang */
+ #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus)
+
+/* No form of inline is available, it happens only when -std=c89, gnu89 and
+ * above are OK */
+  #warning \
+    "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99"
+ #else
+  #ifdef __GNUC_GNU_INLINE__
+
+/* gnu89 semantics of inline and extern inline are essentially the exact
+ * opposite of those in C99 */
+   #define BSP_TFU_INLINE    extern inline __attribute__((always_inline))
+  #else                                /* __GNUC_STDC_INLINE__ */
+   #define BSP_TFU_INLINE    static inline __attribute__((always_inline))
+  #endif
+ #endif
+#elif __ICCARM__
+ #define BSP_TFU_INLINE
+#else
+ #error "Compiler not supported!"
+#endif
+
+#if BSP_CFG_USE_TFU_MATHLIB
+ #define sinf(x)                     __sinf(x)
+ #define cosf(x)                     __cosf(x)
+ #define atan2f(y, x)                __atan2f(y, x)
+ #define hypotf(x, y)                __hypotf(x, y)
+ #define atan2hypotf(y, x, a, h)     __atan2hypotf(y, x, a, h)
+ #define sincosf(a, s, c)            __sincosf(a, s, c)
+ #define sinfx(x)                    __sinfx(x)
+ #define cosfx(x)                    __cosfx(x)
+ #define atan2fx(y, x)               __atan2fx(y, x)
+ #define hypotfx(x, y)               __hypotfx(x, y)
+ #define atan2hypotfx(y, x, a, h)    __atan2hypotfx(y, x, a, h)
+ #define sincosfx(a, s, c)           __sincosfx(a, s, c)
+#endif
+
+#if BSP_CFG_TFU_DATA_SAVE_RESTORE_ENABLE
+ #define BSP_CFG_TFU_SAVE_ENABLE       BSP_TFU_SAVE_ENABLE
+ #define BSP_CFG_TFU_RESTORE_ENABLE    BSP_TFU_RESTORE_ENABLE
+#else
+ #define BSP_CFG_TFU_SAVE_ENABLE
+ #define BSP_CFG_TFU_RESTORE_ENABLE
+#endif
+
+#if 2 == BSP_FEATURE_TFU_VERSION
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+  #define BSP_TFU_DTSR0_ADDRESS     (&R_TFU->DTSR0)
+  #define BSP_TFU_DTSR1_ADDRESS     (&R_TFU->DTSR1)
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+   #define BSP_TFU_DTSR0_ADDRESS    (&R_TFU0->DTSR0)
+   #define BSP_TFU_DTSR1_ADDRESS    (&R_TFU0->DTSR1)
+  #else
+   #define BSP_TFU_DTSR0_ADDRESS    (&R_TFU1->DTSR0)
+   #define BSP_TFU_DTSR1_ADDRESS    (&R_TFU1->DTSR1)
+  #endif
+ #endif
+
+ #define BSP_TFU_SAVE_ENABLE        uint32_t dtsr0 = *(volatile uint32_t *) BSP_TFU_DTSR0_ADDRESS; \
+    uint32_t dtsr1 = *(volatile uint32_t *) BSP_TFU_DTSR1_ADDRESS;                                 \
+    __asm volatile (                                                                               \
+        "PUSH {%[DTSR0]}      \n"                                                                  \
+        "PUSH {%[DTSR1]}      \n"                                                                  \
+        ::[DTSR0] "r" (dtsr0), [DTSR1] "r" (dtsr1) : "memory");
+
+ #define BSP_TFU_RESTORE_ENABLE     __asm volatile (            \
+        "POP {%[DTSR1]}      \n"                                \
+        "POP {%[DTSR0]}      \n"                                \
+        :[DTSR1] "=r" (dtsr1), [DTSR0] "=r" (dtsr0)::"memory"); \
+    *(volatile uint32_t *) BSP_TFU_DTSR0_ADDRESS = dtsr0;       \
+    *(volatile uint32_t *) BSP_TFU_DTSR1_ADDRESS = dtsr1;
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+#if (1 == BSP_LP64_SUPPORT)
+extern float g_bsp_tfu_convert_result;
+#endif
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Inline Functions
+ **********************************************************************************************************************/
+
+#if (1 == BSP_LP64_SUPPORT)
+
+/*******************************************************************************************************************//**
+ * Convert unsigned int type to float type.
+ * @param[in]    target_value  Value before conversion.
+ *
+ * @retval Value after conversion.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float bsp_prv_conversion_uint_to_float (uint32_t target_value)
+{
+    __asm volatile (
+        "ADR  x9,  g_bsp_tfu_convert_result    \n"
+        "MOV  x10, %0                          \n"
+        "FMOV s0, w10                          \n"
+        "STR  s0, [x9]                         \n"
+        ::"r" (target_value) : "memory");
+
+    return g_bsp_tfu_convert_result;
+}
+
+#endif
+
+#if 1 == BSP_FEATURE_TFU_VERSION
+
+/*******************************************************************************************************************//**
+ * Calculates sine of the given angle.
+ * @param[in]    angle  The value of an angle in radian.
+ *
+ * @retval Sine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float __sinf (float angle)
+{
+    /* Set the angle to R_TFU->SCDT1 */
+    R_TFU->SCDT1 = angle;
+
+    /* Read sin from R_TFU->SCDT1 */
+    return R_TFU->SCDT1;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates cosine of the given angle.
+ * @param[in]    angle  The value of an angle in radian.
+ *
+ * @retval Cosine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float __cosf (float angle)
+{
+    /* Set the angle to R_TFU->SCDT1 */
+    R_TFU->SCDT1 = angle;
+
+    /* Read cos from R_TFU->SCDT1 */
+    return R_TFU->SCDT0;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates sine and cosine of the given angle.
+ * @param[in]    angle  The value of an angle in radian.
+ * @param[out]   sin    Sine value of an angle.
+ * @param[out]   cos    Cosine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos)
+{
+    /* Set the angle to R_TFU->SCDT1 */
+    R_TFU->SCDT1 = angle;
+
+    /* Read sin from R_TFU->SCDT1 */
+    *sin = R_TFU->SCDT1;
+
+    /* Read cos from R_TFU->SCDT0 */
+    *cos = R_TFU->SCDT0;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the arc tangent based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-Axis cordinate value.
+ * @param[in]    x_cord  X-Axis cordinate value.
+ *
+ * @retval Arc tangent for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord)
+{
+    /* Set X-cordinate to R_TFU->ATDT0 */
+    R_TFU->ATDT0 = x_cord;
+
+    /* set Y-cordinate to R_TFU->ATDT1 */
+    R_TFU->ATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->ATDT1 */
+    return R_TFU->ATDT1;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-cordinate value.
+ * @param[in]    x_cord  X-cordinate value.
+ *
+ * @retval Hypotenuse for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord)
+{
+    /* Set X-coordinate to R_TFU->ATDT0 */
+    R_TFU->ATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->ATDT1 */
+    R_TFU->ATDT1 = y_cord;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */
+    return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-cordinate value.
+ * @param[in]    x_cord  X-cordinate value.
+ * @param[out]   atan2   Arc tangent for given values.
+ * @param[out]   hypot   Hypotenuse for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot)
+{
+    /* Set X-coordinate to R_TFU->ATDT0 */
+    R_TFU->ATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->ATDT1 */
+    R_TFU->ATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->ATDT1 */
+    *atan2 = R_TFU->ATDT1;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */
+    *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+}
+
+#else
+
+/*******************************************************************************************************************//**
+ * Calculates sine of the given angle.
+ * @param[in]    angle  The value of an angle in radian.
+ *
+ * @retval Sine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float __sinf (float angle)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU->FPSCDT1 = angle;
+
+    /* Read sin from R_TFU->FPSCDT1 */
+    return R_TFU->FPSCDT1;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU0->FPSCDT1 = angle;
+
+    /* Read sin from R_TFU->FPSCDT1 */
+    return R_TFU0->FPSCDT1;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU1->FPSCDT1 = angle;
+
+    /* Read sin from R_TFU->FPSCDT1 */
+    return R_TFU1->FPSCDT1;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates cosine of the given angle.
+ * @param[in]    angle  The value of an angle in radian.
+ *
+ * @retval Cosine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float __cosf (float angle)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU->FPSCDT1 = angle;
+
+    /* Read cos from R_TFU->FPSCDT0 */
+    return R_TFU->FPSCDT0;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU0->FPSCDT1 = angle;
+
+    /* Read cos from R_TFU->FPSCDT0 */
+    return R_TFU0->FPSCDT0;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU1->FPSCDT1 = angle;
+
+    /* Read cos from R_TFU->FPSCDT0 */
+    return R_TFU1->FPSCDT0;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates sine and cosine of the given angle.
+ * @param[in]    angle  The value of an angle in radian.
+ * @param[out]   sin    Sine value of an angle.
+ * @param[out]   cos    Cosine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU->FPSCDT1 = angle;
+
+    /* Read sin from R_TFU->FPSCDT1 */
+    *sin = R_TFU->FPSCDT1;
+
+    /* Read sin from R_TFU->FPSCDT0 */
+    *cos = R_TFU->FPSCDT0;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU0->FPSCDT1 = angle;
+
+    /* Read sin from R_TFU->FPSCDT1 */
+    *sin = R_TFU0->FPSCDT1;
+
+    /* Read sin from R_TFU->FPSCDT0 */
+    *cos = R_TFU0->FPSCDT0;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FPSCDT1 */
+    R_TFU1->FPSCDT1 = angle;
+
+    /* Read sin from R_TFU->FPSCDT1 */
+    *sin = R_TFU1->FPSCDT1;
+
+    /* Read sin from R_TFU->FPSCDT0 */
+    *cos = R_TFU1->FPSCDT0;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the arc tangent based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-Axis cordinate value.
+ * @param[in]    x_cord  X-Axis cordinate value.
+ *
+ * @retval Arc tangent for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set X-cordinate to R_TFU->FPATDT0 */
+    R_TFU->FPATDT0 = x_cord;
+
+    /* set Y-cordinate to R_TFU->FPATDT1 */
+    R_TFU->FPATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FPATDT1 */
+    return R_TFU->FPATDT1;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-cordinate to R_TFU->FPATDT0 */
+    R_TFU0->FPATDT0 = x_cord;
+
+    /* set Y-cordinate to R_TFU->FPATDT1 */
+    R_TFU0->FPATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FPATDT1 */
+    return R_TFU0->FPATDT1;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-cordinate to R_TFU->FPATDT0 */
+    R_TFU1->FPATDT0 = x_cord;
+
+    /* set Y-cordinate to R_TFU->FPATDT1 */
+    R_TFU1->FPATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FPATDT1 */
+    return R_TFU1->FPATDT1;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-cordinate value.
+ * @param[in]    x_cord  X-cordinate value.
+ *
+ * @retval Hypotenuse for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set X-coordinate to R_TFU->FPATDT0 */
+    R_TFU->FPATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FPATDT1 */
+    R_TFU->FPATDT1 = y_cord;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FPATDT0 */
+    return R_TFU->FPATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-coordinate to R_TFU->FPATDT0 */
+    R_TFU0->FPATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FPATDT1 */
+    R_TFU0->FPATDT1 = y_cord;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FPATDT0 */
+    return R_TFU0->FPATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-coordinate to R_TFU->FPATDT0 */
+    R_TFU1->FPATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FPATDT1 */
+    R_TFU1->FPATDT1 = y_cord;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FPATDT0 */
+    return R_TFU1->FPATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-cordinate value.
+ * @param[in]    x_cord  X-cordinate value.
+ * @param[out]   atan2   Arc tangent for given values.
+ * @param[out]   hypot   Hypotenuse for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set X-coordinate to R_TFU->FPATDT0 */
+    R_TFU->FPATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FPATDT1 */
+    R_TFU->FPATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FPATDT1 */
+    *atan2 = R_TFU->FPATDT1;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FPATDT0 */
+    *hypot = R_TFU->FPATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-coordinate to R_TFU->FPATDT0 */
+    R_TFU0->FPATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FPATDT1 */
+    R_TFU0->FPATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FPATDT1 */
+    *atan2 = R_TFU0->FPATDT1;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FPATDT0 */
+    *hypot = R_TFU0->FPATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-coordinate to R_TFU->FPATDT0 */
+    R_TFU1->FPATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FPATDT1 */
+    R_TFU1->FPATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FPATDT1 */
+    *atan2 = R_TFU1->FPATDT1;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FPATDT0 */
+    *hypot = R_TFU1->FPATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates sine of the given angle.
+ * @param[in]    angle  The value of an angle.
+ *
+ * @retval Sine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE uint32_t __sinfx (uint32_t angle)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT1 */
+    return R_TFU->FXSCDT1;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU0->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT1 */
+    return R_TFU0->FXSCDT1;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU1->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT1 */
+    return R_TFU1->FXSCDT1;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates cosine of the given angle.
+ * @param[in]    angle  The value of an angle in radian.
+ *
+ * @retval Cosine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE uint32_t __cosfx (uint32_t angle)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT0 */
+    return R_TFU->FXSCDT0;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU0->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT0 */
+    return R_TFU0->FXSCDT0;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU1->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT0 */
+    return R_TFU1->FXSCDT0;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates sine and cosine of the given angle.
+ * @param[in]    angle  The value of an angle.
+ * @param[out]   sin    Sine value of an angle.
+ * @param[out]   cos    Cosine value of an angle.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE void __sincosfx (uint32_t angle, uint32_t * sin, uint32_t * cos)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT1 */
+    *sin = R_TFU->FXSCDT1;
+
+    /* Read sin from R_TFU->FXSCDT0 */
+    *cos = R_TFU->FXSCDT0;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU0->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT1 */
+    *sin = R_TFU0->FXSCDT1;
+
+    /* Read sin from R_TFU->FXSCDT0 */
+    *cos = R_TFU0->FXSCDT0;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set the angle to R_TFU->FXSCDT1 */
+    R_TFU1->FXSCDT1 = angle;
+
+    /* Read sin from R_TFU->FXSCDT1 */
+    *sin = R_TFU1->FXSCDT1;
+
+    /* Read sin from R_TFU->FXSCDT0 */
+    *cos = R_TFU1->FXSCDT0;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the arc tangent based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-Axis cordinate value.
+ * @param[in]    x_cord  X-Axis cordinate value.
+ *
+ * @retval Arc tangent for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE uint32_t __atan2fx (uint32_t y_cord, uint32_t x_cord)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set X-cordinate to R_TFU->FXATDT0 */
+    R_TFU->FXATDT0 = x_cord;
+
+    /* set Y-cordinate to R_TFU->FXATDT1 */
+    R_TFU->FXATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FXATDT1 */
+    return R_TFU->FXATDT1;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-cordinate to R_TFU->FXATDT0 */
+    R_TFU0->FXATDT0 = x_cord;
+
+    /* set Y-cordinate to R_TFU->FXATDT1 */
+    R_TFU0->FXATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FXATDT1 */
+    return R_TFU0->FXATDT1;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-cordinate to R_TFU->FXATDT0 */
+    R_TFU1->FXATDT0 = x_cord;
+
+    /* set Y-cordinate to R_TFU->FXATDT1 */
+    R_TFU1->FXATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FXATDT1 */
+    return R_TFU1->FXATDT1;
+  #endif
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-cordinate value.
+ * @param[in]    x_cord  X-cordinate value.
+ *
+ * @retval Hypotenuse for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE int32_t __hypotfx (uint32_t x_cord, uint32_t y_cord)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set X-coordinate to R_TFU->FXATDT0 */
+    R_TFU->FXATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FXATDT1 */
+    R_TFU->FXATDT1 = y_cord;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FXATDT0 */
+    int64_t calc_hypotValue = (int64_t) R_TFU->FXATDT0 * R_TFU_HYPOT_SCALING_FACTOR_FIXED;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-coordinate to R_TFU->FXATDT0 */
+    R_TFU0->FXATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FXATDT1 */
+    R_TFU0->FXATDT1 = y_cord;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FXATDT0 */
+    int64_t calc_hypotValue = (int64_t) R_TFU0->FXATDT0 * R_TFU_HYPOT_SCALING_FACTOR_FIXED;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-coordinate to R_TFU->FXATDT0 */
+    R_TFU1->FXATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FXATDT1 */
+    R_TFU1->FXATDT1 = y_cord;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FXATDT0 */
+    int64_t calc_hypotValue = (int64_t) R_TFU1->FXATDT0 * R_TFU_HYPOT_SCALING_FACTOR_FIXED;
+  #endif
+ #endif
+
+    return (int32_t) (calc_hypotValue >> FIXED_POINT_FRACTIONAL_BITS);
+}
+
+/*******************************************************************************************************************//**
+ * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values.
+ * @param[in]    y_cord  Y-cordinate value.
+ * @param[in]    x_cord  X-cordinate value.
+ * @param[out]   atan2   Arc tangent for given values.
+ * @param[out]   hypot   Hypotenuse for given values.
+ **********************************************************************************************************************/
+ #if __ICCARM__
+  #pragma inline = forced
+ #endif
+BSP_TFU_INLINE void __atan2hypotfx (uint32_t y_cord, uint32_t x_cord, uint32_t * atan2, int32_t * hypot)
+{
+ #if (1 == BSP_FEATURE_TFU_UNIT)
+
+    /* Set X-coordinate to R_TFU->FXATDT0 */
+    R_TFU->FXATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FXATDT1 */
+    R_TFU->FXATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FXATDT1 */
+    *atan2 = R_TFU->FXATDT1;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FXATDT0 */
+    int64_t calc_hypotValue = (int64_t) R_TFU->FXATDT0 * R_TFU_HYPOT_SCALING_FACTOR_FIXED;
+ #else
+  #if (0 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-coordinate to R_TFU->FXATDT0 */
+    R_TFU0->FXATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FXATDT1 */
+    R_TFU0->FXATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FXATDT1 */
+    *atan2 = R_TFU0->FXATDT1;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FXATDT0 */
+    int64_t calc_hypotValue = (int64_t) R_TFU0->FXATDT0 * R_TFU_HYPOT_SCALING_FACTOR_FIXED;
+  #elif (1 == BSP_FEATURE_TFU_UNIT_NUMBER)
+
+    /* Set X-coordinate to R_TFU->FXATDT0 */
+    R_TFU1->FXATDT0 = x_cord;
+
+    /* set Y-coordinate to R_TFU->FXATDT1 */
+    R_TFU1->FXATDT1 = y_cord;
+
+    /* Read arctan(y/x) from R_TFU->FXATDT1 */
+    *atan2 = R_TFU1->FXATDT1;
+
+    /* Read sqrt (x_cord2 + y_cord2) from R_TFU->FXATDT0 */
+    int64_t calc_hypotValue = (int64_t) R_TFU1->FXATDT0 * R_TFU_HYPOT_SCALING_FACTOR_FIXED;
+  #endif
+ #endif
+    *hypot = (int32_t) (calc_hypotValue >> FIXED_POINT_FRACTIONAL_BITS);
+}
+
+#endif
+
+/** @} (end addtogroup BSP_MCU) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 /* RENESAS_TFU */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.c
new file mode 100644
index 00000000..52b8b3f0
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.c
@@ -0,0 +1,146 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#if (1 == BSP_FEATURE_TZC400_SUPPORTED)
+ #include "bsp_tzc400.h"
+#endif
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#if BSP_FEATURE_TZC400_SUPPORTED
+ #if (1 == _RZN_ORDINAL)
+  #define BSP_TZC_400_BASEADRESS                               (0x81100000)
+  #define BSP_TZC_400_MODULE_OFFSET                            (uint32_t) (0x1000)
+  #define BSP_TZC_400_REGION_ACTION_OFFSET                     (uint32_t) (0x004)
+  #define BSP_TZC_400_REGION_SPEC_DISABLEULATION_CTL_OFFSET    (uint32_t) (0x00C)
+  #define BSP_TZC_400_REGION_GATEKEEPER_OFFSET                 (uint32_t) (0x008)
+  #define BSP_TZC_400_REGION_ATTR_N_OFFSET(n)         (uint32_t) (0x110 + (0x20 * n))
+  #define BSP_TZC_400_REGION_ID_ACCESS_N_OFFSET(n)    (uint32_t) (0x114 + (0x20 * n))
+  #define BSP_TZC_400_NUMBER_SHIFT_NSAID_WR_EN                 16U
+  #define BSP_TZC_400_NUMBER_SHIFT_NSAID_RD_EN                 0U
+  #define BSP_TZC_400_MAX_MODULE                               9U
+  #define BSP_TZC_400_MAX_REGION_SUPPORT                       1U
+  #define BSP_TZC_400_MAX_FILTER                               4U
+
+  #define BSP_TZC400_REGION(module, region)                                    \
+    {                                                                          \
+        BSP_CFG_TZC400_ ## module ## _REGION_ID_ACCESS_NSAID_RD_EN_ ## region, \
+        BSP_CFG_TZC400_ ## module ## _REGION_ID_ACCESS_NSAID_WR_EN_ ## region, \
+        BSP_CFG_TZC400_ ## module ## _REGION_ATTR_S_RD_EN_ ## region,          \
+        BSP_CFG_TZC400_ ## module ## _REGION_ATTR_S_WR_EN_ ## region,          \
+        BSP_CFG_TZC400_ ## module ## _REGION_ATTR_FILTER_UNIT_ ## region,      \
+    }
+  #define BSP_TZC400_MODULE(module)                       \
+    {                                                     \
+        BSP_CFG_TZC400_ ## module ## _GATEKEEPER,         \
+        BSP_CFG_TZC400_ ## module ## _WRITE_SPEC_DISABLE, \
+        BSP_CFG_TZC400_ ## module ## _READ_SPEC_DISABLE,  \
+        {                                                 \
+            BSP_TZC400_REGION(module, 0),                 \
+        }                                                 \
+    }
+ #endif
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+#if BSP_FEATURE_TZC400_SUPPORTED
+ #if (1 == _RZN_ORDINAL)
+typedef struct st_bsp_tzc400_region_cfg_data
+{
+    uint16_t id_access_rd_en;
+    uint16_t id_access_wr_en;
+    uint8_t  attr_rd_en;
+    uint8_t  attr_wr_en;
+    uint8_t  attr_filter;
+} bsp_tzc400_region_cfg_data_t;
+
+typedef struct st_bsp_tzc400_cfg_data
+{
+    uint32_t gatekeeper;
+    uint8_t  write_spec_disable;
+    uint8_t  read_spec_disable;
+
+    bsp_tzc400_region_cfg_data_t region[BSP_TZC_400_MAX_REGION_SUPPORT];
+} bsp_tzc400_cfg_data_t;
+ #endif
+#endif
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+#if BSP_FEATURE_TZC400_SUPPORTED
+ #if (1 == _RZN_ORDINAL)
+static const bsp_tzc400_cfg_data_t g_bsp_tzc_module_cfg_data[] =
+{
+    BSP_TZC400_MODULE(0),
+    BSP_TZC400_MODULE(1),
+    BSP_TZC400_MODULE(2),
+    BSP_TZC400_MODULE(3),
+    BSP_TZC400_MODULE(4),
+    BSP_TZC400_MODULE(5),
+    BSP_TZC400_MODULE(6),
+    BSP_TZC400_MODULE(7),
+    BSP_TZC400_MODULE(8),
+};
+
+/*******************************************************************************************************************//**
+ * Configure TrustedZone 400.
+ * @param[in]    None
+ * @param[out]   None
+ * @note         This function supports configurable the registers of TZC-400.
+ * @retval       None
+ **********************************************************************************************************************/
+void bsp_tzc_400_cfg (void)
+{
+    /* Initialize local variable */
+    uint8_t             tzc400module;
+    uintptr_t           basetzc400;
+    volatile uint32_t * p_reg;
+
+    /* Loop all modules of TZC400 */
+    for (tzc400module = 0; tzc400module < BSP_TZC_400_MAX_MODULE; tzc400module++)
+    {
+        /* Get base address of each module */
+        basetzc400 = (uintptr_t) (BSP_TZC_400_BASEADRESS + (BSP_TZC_400_MODULE_OFFSET * tzc400module));
+
+        /* Setting for GATE_KEEPER */
+        p_reg  = (uint32_t *) (basetzc400 + BSP_TZC_400_REGION_GATEKEEPER_OFFSET);
+        *p_reg = g_bsp_tzc_module_cfg_data[tzc400module].gatekeeper;
+
+        /* Setting for SPECULATION_CTRL */
+        p_reg  = (uint32_t *) (basetzc400 + BSP_TZC_400_REGION_SPEC_DISABLEULATION_CTL_OFFSET);
+        *p_reg = (uint32_t) ((g_bsp_tzc_module_cfg_data[tzc400module].write_spec_disable << 1) |
+                             (g_bsp_tzc_module_cfg_data[tzc400module].read_spec_disable << 0));
+
+        /* Setting attribute for region 0 only as BSP_TZC_400_MAX_REGION_SUPPORT */
+        p_reg  = (uint32_t *) (basetzc400 + BSP_TZC_400_REGION_ATTR_N_OFFSET(0));
+        *p_reg = (uint32_t) ((g_bsp_tzc_module_cfg_data[tzc400module].region[0].attr_rd_en << 30) |
+                             (g_bsp_tzc_module_cfg_data[tzc400module].region[0].attr_wr_en << 31) |
+                             (g_bsp_tzc_module_cfg_data[tzc400module].region[0].attr_filter));
+
+        /* Setting id access for region 0 only as BSP_TZC_400_MAX_REGION_SUPPORT */
+        p_reg  = (uint32_t *) (basetzc400 + BSP_TZC_400_REGION_ID_ACCESS_N_OFFSET(0));
+        *p_reg =
+            (uint32_t) ((g_bsp_tzc_module_cfg_data[tzc400module].region[0].id_access_rd_en <<
+                         BSP_TZC_400_NUMBER_SHIFT_NSAID_RD_EN) |
+                        (g_bsp_tzc_module_cfg_data[tzc400module].region[0].id_access_wr_en <<
+                         BSP_TZC_400_NUMBER_SHIFT_NSAID_WR_EN));
+    }
+}
+
+ #endif
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.h
new file mode 100644
index 00000000..f22fa3bc
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.h
@@ -0,0 +1,58 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_TZC400_H
+#define BSP_TZC400_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#if (1 == BSP_FEATURE_TZC400_SUPPORTED)
+ #define BSP_TZC400_GATEKEEPER_FILTER_0    (1 << 0)
+ #define BSP_TZC400_GATEKEEPER_FILTER_1    (1 << 1)
+ #define BSP_TZC400_GATEKEEPER_FILTER_2    (1 << 2)
+ #define BSP_TZC400_GATEKEEPER_FILTER_3    (1 << 3)
+ #define BSP_TZC400_ATTR_FILTER_0          (1 << 0)
+ #define BSP_TZC400_ATTR_FILTER_1          (1 << 1)
+ #define BSP_TZC400_ATTR_FILTER_2          (1 << 2)
+ #define BSP_TZC400_ATTR_FILTER_3          (1 << 3)
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+#if BSP_FEATURE_TZC400_SUPPORTED
+ #if (1 == _RZN_ORDINAL)
+
+void bsp_tzc_400_cfg(void);            // Used internally by BSP
+
+ #endif
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c
new file mode 100644
index 00000000..cf44b284
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c
@@ -0,0 +1,34 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Powers on and off the L3 cache way.
+ **********************************************************************************************************************/
+void r_bsp_cache_l3_power_ctrl (void)
+{
+    /* Does nothing because CR52 does not have the CLUSTERPWRCTLR register. */
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h
new file mode 100644
index 00000000..ac075fc9
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h
@@ -0,0 +1,38 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_CACHE_CORE_H
+#define BSP_CACHE_CORE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+void r_bsp_cache_l3_power_ctrl(void);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c
new file mode 100644
index 00000000..290b9be0
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c
@@ -0,0 +1,49 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ *        This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles
+ *        occur when the loop exits. The 'naked' attribute  indicates that the specified function does not need
+ *        prologue/epilogue sequences generated by the compiler.
+ * @param[in]     loop_cnt  The number of loops to iterate.
+ **********************************************************************************************************************/
+BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt)
+{
+    __asm volatile ("sw_delay_loop:         \n"
+
+#if defined(__ICCARM__) || defined(__ARMCC_VERSION)
+                    "   subs r0, #1         \n"   ///< 1 cycle
+#elif defined(__GNUC__)
+                    "   sub r0, r0, #1      \n"   ///< 1 cycle
+#endif
+
+                    "   cmp r0, #0          \n"   ///< 1 cycle
+
+                    "   bne sw_delay_loop   \n"   ///< 2 cycles
+
+                    "   bx lr               \n"); ///< 2 cycles
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h
new file mode 100644
index 00000000..9afead5b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h
@@ -0,0 +1,49 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_DELAY_CORE_H
+#define BSP_DELAY_CORE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* The number of cycles required per software delay loop. */
+#ifndef BSP_DELAY_LOOP_CYCLES
+ #define BSP_DELAY_LOOP_CYCLES    (4)
+#endif
+
+/* Calculates the number of delay loops to pass to r_bsp_software_delay_loop to achieve at least the requested cycle
+ * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures
+ * the requested number of loops is at least 1 since r_bsp_software_delay_loop cannot be called with a loop count
+ * of 0. */
+#define BSP_DELAY_LOOPS_CALCULATE(cycles)    (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop(uint32_t loop_cnt);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c
new file mode 100644
index 00000000..b1308ddb
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c
@@ -0,0 +1,256 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/** ELC event definitions. */
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_IRQ_UINT32_MAX                       (0xFFFFFFFFU)
+
+#define BSP_PRV_CLEAR_REG_MAX                    (13U)
+#define BSP_PRV_ALL_BIT_CLEAR                    (0xFFFFFFFFU)
+
+#define BSP_PRV_ID_MASK                          (0x000003FFU)
+#define BSP_PRV_INTERRUPTABLE_NUM                (32U)
+
+#define BSP_PRV_ICFGR_EVENT_TYPE_SETTING_MASK    (0x3U)
+#define BSP_PRV_ICFGR_EDGE_DETECTION_TYPE        (0x2U)
+#define BSP_PRV_ICFGR_REG_FIELD_NUM              (16U)
+#define BSP_PRV_ICFGR_FIELD_WIDTH_BITS           (2U)
+
+#define BSP_PRV_CR52_INTSEL_INIT                 (0x03FF03FFUL)
+
+#define R_BSP_GIC_INTID_1023                     (1023)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+#if VECTOR_DATA_IRQ_COUNT > 0
+extern fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES];
+#endif
+extern fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES];
+
+#if (0 == BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED)
+extern const uint32_t BSP_GICD_ICFGR_INIT[BSP_NON_SELECTABLE_ICFGR_MAX];
+
+#elif (1 == BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED)
+extern const uint32_t BSP_GICD_ICFGR_INIT[BSP_EVENT_ARRAY_NUM];
+
+#endif
+
+/* This table is used to store the context in the ISR. */
+void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
+
+/* GIC current interrupt ID and variable. */
+IRQn_Type g_current_interrupt_num[BSP_PRV_INTERRUPTABLE_NUM];
+uint8_t   g_current_interrupt_pointer = 0;
+
+const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE =
+{
+    (bsp_interrupt_event_t) 0
+};
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+#if (1 == BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED)
+
+/*******************************************************************************************************************//**
+ * Set the events to CR52_SEL. Events can be set through the configurator.
+ *
+ **********************************************************************************************************************/
+static void bsp_prv_cr52_sel_cfg (void)
+{
+    for (uint32_t intsel_reg_num = 0;
+         intsel_reg_num < BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_EVENT_NUM / 2U;
+         intsel_reg_num++)
+    {
+        /* Get interrupt number of SELECT0_IRQn */
+        uint32_t select0_irqx = (2U * intsel_reg_num) + BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_START;
+        uint32_t select0_irqy = (2U * intsel_reg_num + 1U) + BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_START;
+
+        /* Get user-setting event number from vector_data.c */
+        uint32_t intselx = g_interrupt_event_link_select[select0_irqx];
+        uint32_t intsely = g_interrupt_event_link_select[select0_irqy];
+
+        uint32_t intseln = BSP_PRV_CR52_INTSEL_INIT;
+
+        /* 0 in g_interrupt_event_link_select indicates that either INTCPU0 event is registered
+         * or no event is registered. INTCPU0 is not a target of selected interrupt
+         * and does not appear as a value after 384 in the array.
+         * Therefore, 0 means that user registered no event in SELECT0_IRQn with FSP configurator. */
+        if (intselx != 0U)             // Set INTSELX of CR520_INTSELn register
+        {
+            intseln &= (intselx << R_ICU_NS_CR520_INTSEL_INTSELX_Pos) | R_ICU_NS_CR520_INTSEL_INTSELY_Msk;
+        }
+
+        if (intsely != 0U)             // Set INTSELY of CR520_INTSELn register
+        {
+            intseln &= (intsely << R_ICU_NS_CR520_INTSEL_INTSELY_Pos) | R_ICU_NS_CR520_INTSEL_INTSELX_Msk;
+        }
+
+ #if (0 == BSP_CFG_CORE_CR52)
+        R_ICU_NS->CR520_INTSEL[intsel_reg_num] = intseln;
+ #elif (1 == BSP_CFG_CORE_CR52)
+        R_ICU_NS->CR521_INTSEL[intsel_reg_num] = intseln;
+ #endif
+    }
+}
+
+#endif
+
+#if (1 == BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED)
+
+/*******************************************************************************************************************//**
+ * Identifies the event interrupt type of selected interrupts to be set in GICD_ICFGR.
+ *
+ * @param[in]  gicd_reg_num    Register number of GICD_ICFGR.
+ **********************************************************************************************************************/
+static uint32_t bsp_prv_gicd_icfgr_set (uint32_t gicd_reg_num)
+{
+    uint32_t gicd_reg_icfgr = 0;
+
+    /* GICD_ICFGR sets 16 events per register */
+    for (uint32_t field_num = 0; field_num < BSP_PRV_ICFGR_REG_FIELD_NUM; field_num++)
+    {
+        bsp_interrupt_event_t event =
+            g_interrupt_event_link_select[gicd_reg_num * BSP_PRV_ICFGR_REG_FIELD_NUM + field_num];
+
+        /* Identify the location in BSP_GICD_ICFGR_INIT where type of the event is stored */
+        uint32_t event_type_array_num   = event / BSP_PRV_ICFGR_REG_FIELD_NUM;
+        uint32_t event_type_array_shift = (event % BSP_PRV_ICFGR_REG_FIELD_NUM) * BSP_PRV_ICFGR_FIELD_WIDTH_BITS;
+
+        /* 0 in g_interrupt_event_link_select indicates that either INTCPU0 event is registered
+         * or no event is registered. INTCPU0 is not a target of selected interrupt
+         * and does not appear as a value after 384 in the array.
+         * Therefore, 0 means that user registered no event in SELECT0_IRQn with FSP configurator. */
+        if (event != 0)
+        {
+            gicd_reg_icfgr |=
+                ((BSP_GICD_ICFGR_INIT[event_type_array_num] >> event_type_array_shift) &
+                 BSP_PRV_ICFGR_EVENT_TYPE_SETTING_MASK) <<
+                    field_num * BSP_PRV_ICFGR_FIELD_WIDTH_BITS;
+        }
+        else
+        {
+            /* SELECT0_IRQn is level/edge type. Therefore, interrupt type is initialized by edge. */
+            gicd_reg_icfgr |= (BSP_PRV_ICFGR_EDGE_DETECTION_TYPE & BSP_PRV_ICFGR_EVENT_TYPE_SETTING_MASK) <<
+                              field_num * BSP_PRV_ICFGR_FIELD_WIDTH_BITS;
+        }
+    }
+
+    return gicd_reg_icfgr;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ *        Using the vector table information section that has been built by the linker and placed into ROM in the
+ * .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts
+ * in the NVIC.
+ *
+ **********************************************************************************************************************/
+void bsp_irq_core_cfg (void)
+{
+    uint32_t                   gicd_reg_num;
+    GICD_Type                * GICD;
+    GICR_CONTROL_TARGET_Type * GICR_TARGET0_IFREG;
+
+    GICD               = BSP_PRV_GICD_ADDRESS;
+    GICR_TARGET0_IFREG = BSP_PRV_GICR_TARGET0_IFREG_ADDRESS;
+
+#if (1 == BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED)
+
+    /* Set events to CR520_INTSELn */
+    bsp_prv_cr52_sel_cfg();
+#endif
+
+    /* Enable Group1 interrupts from the GIC Distributor to the GIC CPU interface. */
+    GICD->GICD_CTLR |= 0x00000002UL;
+
+    /* Release Processor Sleep state of the target. */
+    GICR_TARGET0_IFREG->GICR_WAKER = 0x00000000UL;
+
+    /* Initialize GICD_ICFGR register for the edge-triggered interrupt. */
+    for (gicd_reg_num = 0; gicd_reg_num < BSP_NON_SELECTABLE_ICFGR_MAX; gicd_reg_num++)
+    {
+        GICD->GICD_ICFGR[gicd_reg_num] = BSP_GICD_ICFGR_INIT[gicd_reg_num];
+    }
+
+#if (1 == BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED)
+
+    /* Initialize GICD_ICFGR register of SELECT0_IRQn interrupt. */
+    for (gicd_reg_num = BSP_NON_SELECTABLE_ICFGR_MAX; gicd_reg_num < BSP_ICFGR_MAX; gicd_reg_num++)
+    {
+        GICD->GICD_ICFGR[gicd_reg_num] = bsp_prv_gicd_icfgr_set(gicd_reg_num);
+    }
+#endif
+
+    /* Clear the Pending and Active bit for the all interrupts. */
+    for (gicd_reg_num = 0; gicd_reg_num < BSP_PRV_CLEAR_REG_MAX; gicd_reg_num++)
+    {
+        GICD->GICD_ICPENDR[gicd_reg_num]   = BSP_PRV_ALL_BIT_CLEAR;
+        GICD->GICD_ICACTIVER[gicd_reg_num] = BSP_PRV_ALL_BIT_CLEAR;
+    }
+
+    __asm volatile ("cpsie i    \n"    /* Enable IRQ Interrupts */
+                    "cpsie f    \n"    /* Enable FIQ Interrupts */
+                    "cpsie a    \n"    /* Enable SError Interrupts */
+                    "isb");            /* Ensuring Context-changing */
+}
+
+/*******************************************************************************************************************//**
+ * This function is called first when an interrupt is generated and branches to each interrupt isr function.
+ *
+ * @param[in]  id    GIC INTID used to identify the interrupt.
+ **********************************************************************************************************************/
+void bsp_common_interrupt_handler (uint32_t id)
+{
+    uint16_t  gic_intid;
+    IRQn_Type irq;
+
+    /* Get interrupt ID (GIC INTID). */
+    gic_intid = (uint16_t) (id & BSP_PRV_ID_MASK);
+
+    irq = (IRQn_Type) (gic_intid - BSP_CORTEX_VECTOR_TABLE_ENTRIES);
+
+    FSP_ASSERT_NOT_RETURN_VALUE(R_BSP_GIC_INTID_1023 != gic_intid);
+
+    /* Remain the interrupt number */
+    g_current_interrupt_num[g_current_interrupt_pointer++] = irq;
+    __asm volatile ("dmb");
+
+    BSP_CFG_TFU_SAVE_ENABLE;
+    BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+#if VECTOR_DATA_IRQ_COUNT > 0
+    if (BSP_CORTEX_VECTOR_TABLE_ENTRIES <= gic_intid)
+    {
+        /* Branch to an interrupt handler. */
+        g_vector_table[irq]();
+    }
+    else
+#endif
+    {
+        /* Branch to an interrupt handler. */
+        g_sgi_ppi_vector_table[gic_intid]();
+    }
+
+    BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+    BSP_CFG_TFU_RESTORE_ENABLE;
+
+    g_current_interrupt_pointer--;
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h
new file mode 100644
index 00000000..a72dd1b0
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h
@@ -0,0 +1,348 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_IRQ_CORE_H
+#define BSP_IRQ_CORE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_ICU_VECTOR_MAX_ENTRIES              (BSP_VECTOR_TABLE_MAX_ENTRIES)
+
+#if (0 == BSP_CFG_CORE_CR52)
+ #define BSP_PRV_GICD_ADDRESS                   (GICD0)
+ #define BSP_PRV_GICR_TARGET0_INTREG_ADDRESS    (GICR0_TARGET0_INTREG)
+ #define BSP_PRV_GICR_TARGET0_IFREG_ADDRESS     (GICR0_TARGET0_IFREG)
+
+#elif (1 == BSP_CFG_CORE_CR52)
+ #define BSP_PRV_GICD_ADDRESS                   (GICD1)
+ #define BSP_PRV_GICR_TARGET0_INTREG_ADDRESS    (GICR1_TARGET0_INTREG)
+ #define BSP_PRV_GICR_TARGET0_IFREG_ADDRESS     (GICR1_TARGET0_IFREG)
+
+#endif
+
+#define BSP_EVENT_SGI_PPI_ARRAY_NUM             (2U)
+#define BSP_NON_SELECTABLE_ICFGR_MAX            (BSP_FEATURE_BSP_NON_SELECTABLE_INTERRUPT_EVENT_NUM / \
+                                                 BSP_INTERRUPT_TYPE_OFFSET)
+
+#define BSP_ICFGR_MAX                           ((BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_START +      \
+                                                  BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_EVENT_NUM) / \
+                                                 BSP_INTERRUPT_TYPE_OFFSET)
+#define BSP_EVENT_ARRAY_NUM                     (BSP_FEATURE_BSP_EVENT_NUM_MAX / \
+                                                 BSP_INTERRUPT_TYPE_OFFSET + 1U)
+
+#define BSP_PRV_IRQ_CONFIG_MASK                 (0x000000FFU)
+#define BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK      (1UL << 1UL)
+
+#define BSP_PRV_GIC_REG_STRIDE04                (4U)
+#define BSP_PRV_GIC_REG_STRIDE16                (16U)
+#define BSP_PRV_GIC_REG_STRIDE32                (32U)
+
+#define BSP_PRV_GIC_REG_BITS1                   (1U)
+#define BSP_PRV_GIC_REG_BITS2                   (2U)
+#define BSP_PRV_GIC_REG_BITS8                   (8U)
+
+#define BSP_PRV_GIC_REG_MASK_1BIT               (1U)
+
+#define BSP_PRV_GIC_LOWEST_PPI_INTERRUPT_NUM    (-17)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Inline Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief      Sets the ISR context associated with the requested IRQ.
+ *
+ * @param[in]  irq            IRQ number (parameter checking must ensure the IRQ number is valid before calling this
+ *                            function.
+ * @param[in]  p_context      ISR context for IRQ.
+ **********************************************************************************************************************/
+__STATIC_INLINE void r_fsp_irq_context_set (IRQn_Type const irq, void * p_context)
+{
+    /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
+     * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
+    gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET] = p_context;
+}
+
+/*******************************************************************************************************************//**
+ * Clear the GIC pending interrupt.
+ *
+ * @param[in] irq            Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ **********************************************************************************************************************/
+__STATIC_INLINE void r_bsp_irq_clear_pending (IRQn_Type irq)
+{
+    GICD_Type         * GICD;
+    GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
+
+    GICD                = BSP_PRV_GICD_ADDRESS;
+    GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
+
+    if (irq >= 0)
+    {
+        uint32_t _irq = (uint32_t) irq;
+        GICD->GICD_ICPENDR[_irq / BSP_PRV_GIC_REG_STRIDE32] =
+            (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32));
+    }
+    else
+    {
+        uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
+        GICR_TARGET0_INTREG->GICR_ICPENDR0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Get the GIC pending interrupt.
+ *
+ * @param[in] irq            Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ *
+ * @return  Value indicating the status of the level interrupt.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t r_bsp_irq_pending_get (IRQn_Type irq)
+{
+    GICD_Type         * GICD;
+    GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
+    uint32_t            value = 0;
+
+    GICD                = BSP_PRV_GICD_ADDRESS;
+    GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
+
+    if (irq >= 0)
+    {
+        uint32_t _irq  = (uint32_t) irq;
+        uint32_t shift = (_irq % BSP_PRV_GIC_REG_STRIDE32);
+        value = (GICD->GICD_ISPENDR[_irq / BSP_PRV_GIC_REG_STRIDE32] >> shift) & (uint32_t) (BSP_PRV_GIC_REG_MASK_1BIT);
+    }
+    else
+    {
+        uint32_t _irq  = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
+        uint32_t shift = _irq;
+        value = (GICR_TARGET0_INTREG->GICR_ISPENDR0 >> shift) & (uint32_t) (BSP_PRV_GIC_REG_MASK_1BIT);
+    }
+
+    return value;
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt priority and context.
+ *
+ * @param[in] irq            The IRQ number to configure.
+ * @param[in] priority       GIC priority of the interrupt
+ **********************************************************************************************************************/
+__STATIC_INLINE void r_bsp_irq_cfg (IRQn_Type const irq, uint32_t priority)
+{
+#if (52U == __CORTEX_R)
+    GICD_Type         * GICD;
+    GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
+
+    GICD                = BSP_PRV_GICD_ADDRESS;
+    GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
+
+    if (irq >= 0)
+    {
+        uint32_t _irq = (uint32_t) irq;
+
+        /* Set the interrupt group to 1 (IRQ) */
+        GICD->GICD_IGROUPR[_irq / BSP_PRV_GIC_REG_STRIDE32] |=
+            (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32));
+
+        /* Set the interrupt priority */
+        GICD->GICD_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] &=
+            (uint32_t) (~(BSP_PRV_IRQ_CONFIG_MASK << (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04))));
+        GICD->GICD_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] |=
+            (priority <<
+             (BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT + (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04))));
+    }
+    else
+    {
+        uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
+
+        /* Set the interrupt group to 1 (IRQ) */
+        GICR_TARGET0_INTREG->GICR_IGROUPR0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq);
+
+        /* Set the interrupt priority */
+        GICR_TARGET0_INTREG->GICR_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] &=
+            (uint32_t) (~(BSP_PRV_IRQ_CONFIG_MASK << (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04))));
+        GICR_TARGET0_INTREG->GICR_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] |=
+            (priority <<
+             (BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT + (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04))));
+    }
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Enable the IRQ in the GIC (Without clearing the pending bit).
+ *
+ * @param[in] irq            The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
+ *                           Cortex Processor Exceptions Numbers.
+ **********************************************************************************************************************/
+__STATIC_INLINE void r_bsp_irq_enable_no_clear (IRQn_Type const irq)
+{
+    GICD_Type         * GICD;
+    GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
+
+    GICD                = BSP_PRV_GICD_ADDRESS;
+    GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
+
+    if (irq >= 0)
+    {
+        uint32_t _irq = (uint32_t) irq;
+        GICD->GICD_ISENABLER[_irq / BSP_PRV_GIC_REG_STRIDE32] |=
+            (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32));
+    }
+    else
+    {
+        uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
+        GICR_TARGET0_INTREG->GICR_ISENABLER0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Disables interrupts in the GIC.
+ *
+ * @param[in] irq            The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ **********************************************************************************************************************/
+__STATIC_INLINE void r_bsp_irq_disable (IRQn_Type const irq)
+{
+    GICD_Type         * GICD;
+    GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
+
+    GICD                = BSP_PRV_GICD_ADDRESS;
+    GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
+
+    if (irq >= 0)
+    {
+        uint32_t _irq = (uint32_t) irq;
+        GICD->GICD_ICENABLER[_irq / BSP_PRV_GIC_REG_STRIDE32] =
+            (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32));
+    }
+    else
+    {
+        uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
+        GICR_TARGET0_INTREG->GICR_ICENABLER0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq);
+    }
+
+    __DSB();
+    __ISB();
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt detect type.
+ *
+ * @param[in] irq             The IRQ number to configure.
+ * @param[in] detect_type     GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd).
+ **********************************************************************************************************************/
+__STATIC_INLINE void r_bsp_irq_detect_type_set (IRQn_Type const irq, uint32_t detect_type)
+{
+    GICD_Type         * GICD;
+    GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
+
+    GICD                = BSP_PRV_GICD_ADDRESS;
+    GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
+
+    if (irq >= 0)
+    {
+        uint32_t _irq = (uint32_t) irq;
+        if (0 != detect_type)
+        {
+            GICD->GICD_ICFGR[_irq / BSP_PRV_GIC_REG_STRIDE16] |=
+                (uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK <<
+                            (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16)));
+        }
+        else
+        {
+            GICD->GICD_ICFGR[_irq / BSP_PRV_GIC_REG_STRIDE16] &=
+                ~((uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK <<
+                              (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16))));
+        }
+    }
+    else if (irq >= BSP_PRV_GIC_LOWEST_PPI_INTERRUPT_NUM)
+    {
+        uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
+        if (0 != detect_type)
+        {
+            GICR_TARGET0_INTREG->GICR_ICFGR1 |=
+                (uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK <<
+                            (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16)));
+        }
+        else
+        {
+            GICR_TARGET0_INTREG->GICR_ICFGR1 &=
+                ~((uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK <<
+                              (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16))));
+        }
+    }
+    else
+    {
+        /* The register that sets the SGI interrupt type (GICR_ICFGR0) is read-only, so do not set it. */
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt Group.
+ *
+ * @param[in] irq               The IRQ number to configure.
+ * @param[in] interrupt_group   GIC interrupt group number ( 0 : FIQ, 1 : IRQ ).
+ **********************************************************************************************************************/
+__STATIC_INLINE void r_bsp_irq_group_set (IRQn_Type const irq, uint32_t interrupt_group)
+{
+    GICD_Type         * GICD;
+    GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
+
+    GICD                = BSP_PRV_GICD_ADDRESS;
+    GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
+
+    if (irq >= 0)
+    {
+        uint32_t _irq = (uint32_t) irq;
+        GICD->GICD_IGROUPR[_irq / BSP_PRV_GIC_REG_STRIDE32] |= (interrupt_group << (_irq % BSP_PRV_GIC_REG_STRIDE32));
+    }
+    else
+    {
+        uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
+        GICR_TARGET0_INTREG->GICR_IGROUPR0 |= interrupt_group << _irq;
+    }
+}
+
+/*******************************************************************************************************************//**
+ * @internal
+ * @addtogroup BSP_MCU_PRV Internal BSP Documentation
+ * @ingroup RENESAS_INTERNAL
+ * @{
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+void bsp_irq_core_cfg(void);           // Used internally by BSP
+void bsp_common_interrupt_handler(uint32_t id);
+
+/** @} (end addtogroup BSP_MCU_PRV) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h
new file mode 100644
index 00000000..1d72d7aa
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h
@@ -0,0 +1,509 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_ELC_H
+#define BSP_ELC_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU_RZN2L
+ * @{
+ **********************************************************************************************************************/
+
+/** Sources of event signals to be linked to other peripherals or the CPU
+ * @note This list may change based on based on the device.
+ * */
+typedef enum e_elc_event_rzn2l
+{
+    ELC_EVENT_INTCPU0        = (0),    // Software interrupt 0
+    ELC_EVENT_INTCPU1        = (1),    // Software interrupt 1
+    ELC_EVENT_INTCPU2        = (2),    // Software interrupt 2
+    ELC_EVENT_INTCPU3        = (3),    // Software interrupt 3
+    ELC_EVENT_INTCPU4        = (4),    // Software interrupt 4
+    ELC_EVENT_INTCPU5        = (5),    // Software interrupt 5
+    ELC_EVENT_IRQ0           = (6),    // External pin interrupt 0
+    ELC_EVENT_IRQ1           = (7),    // External pin interrupt 1
+    ELC_EVENT_IRQ2           = (8),    // External pin interrupt 2
+    ELC_EVENT_IRQ3           = (9),    // External pin interrupt 3
+    ELC_EVENT_IRQ4           = (10),   // External pin interrupt 4
+    ELC_EVENT_IRQ5           = (11),   // External pin interrupt 5
+    ELC_EVENT_IRQ6           = (12),   // External pin interrupt 6
+    ELC_EVENT_IRQ7           = (13),   // External pin interrupt 7
+    ELC_EVENT_IRQ8           = (14),   // External pin interrupt 8
+    ELC_EVENT_IRQ9           = (15),   // External pin interrupt 9
+    ELC_EVENT_IRQ10          = (16),   // External pin interrupt 10
+    ELC_EVENT_IRQ11          = (17),   // External pin interrupt 11
+    ELC_EVENT_IRQ12          = (18),   // External pin interrupt 12
+    ELC_EVENT_IRQ13          = (19),   // External pin interrupt 13
+    ELC_EVENT_BSC_CMI        = (20),   // Refresh compare match interrupt
+    ELC_EVENT_DMAC0_INT0     = (21),   // DMAC0 transfer completion 0
+    ELC_EVENT_DMAC0_INT1     = (22),   // DMAC0 transfer completion 1
+    ELC_EVENT_DMAC0_INT2     = (23),   // DMAC0 transfer completion 2
+    ELC_EVENT_DMAC0_INT3     = (24),   // DMAC0 transfer completion 3
+    ELC_EVENT_DMAC0_INT4     = (25),   // DMAC0 transfer completion 4
+    ELC_EVENT_DMAC0_INT5     = (26),   // DMAC0 transfer completion 5
+    ELC_EVENT_DMAC0_INT6     = (27),   // DMAC0 transfer completion 6
+    ELC_EVENT_DMAC0_INT7     = (28),   // DMAC0 transfer completion 7
+    ELC_EVENT_DMAC1_INT0     = (37),   // DMAC1 transfer completion 0
+    ELC_EVENT_DMAC1_INT1     = (38),   // DMAC1 transfer completion 1
+    ELC_EVENT_DMAC1_INT2     = (39),   // DMAC1 transfer completion 2
+    ELC_EVENT_DMAC1_INT3     = (40),   // DMAC1 transfer completion 3
+    ELC_EVENT_DMAC1_INT4     = (41),   // DMAC1 transfer completion 4
+    ELC_EVENT_DMAC1_INT5     = (42),   // DMAC1 transfer completion 5
+    ELC_EVENT_DMAC1_INT6     = (43),   // DMAC1 transfer completion 6
+    ELC_EVENT_DMAC1_INT7     = (44),   // DMAC1 transfer completion 7
+    ELC_EVENT_CMT0_CMI       = (53),   // CMT0 Compare match
+    ELC_EVENT_CMT1_CMI       = (54),   // CMT1 Compare match
+    ELC_EVENT_CMT2_CMI       = (55),   // CMT2 Compare match
+    ELC_EVENT_CMT3_CMI       = (56),   // CMT3 Compare match
+    ELC_EVENT_CMT4_CMI       = (57),   // CMT4 Compare match
+    ELC_EVENT_CMT5_CMI       = (58),   // CMT5 Compare match
+    ELC_EVENT_CMTW0_CMWI     = (59),   // CMTW0 Compare match
+    ELC_EVENT_CMTW0_IC0I     = (60),   // CMTW0 Input capture of register 0
+    ELC_EVENT_CMTW0_IC1I     = (61),   // CMTW0 Input capture of register 1
+    ELC_EVENT_CMTW0_OC0I     = (62),   // CMTW0 Output compare of register 0
+    ELC_EVENT_CMTW0_OC1I     = (63),   // CMTW0 Output compare of register 1
+    ELC_EVENT_CMTW1_CMWI     = (64),   // CMTW1 Compare match
+    ELC_EVENT_CMTW1_IC0I     = (65),   // CMTW1 Input capture of register 0
+    ELC_EVENT_CMTW1_IC1I     = (66),   // CMTW1 Input capture of register 1
+    ELC_EVENT_CMTW1_OC0I     = (67),   // CMTW1 Output compare of register 0
+    ELC_EVENT_CMTW1_OC1I     = (68),   // CMTW1 Output compare of register 1
+    ELC_EVENT_TGIA0          = (69),   // MTU0.TGRA input capture/compare match
+    ELC_EVENT_TGIB0          = (70),   // MTU0.TGRB input capture/compare match
+    ELC_EVENT_TGIC0          = (71),   // MTU0.TGRC input capture/compare match
+    ELC_EVENT_TGID0          = (72),   // MTU0.TGRD input capture/compare match
+    ELC_EVENT_TCIV0          = (73),   // MTU0.TCNT overflow
+    ELC_EVENT_TGIE0          = (74),   // MTU0.TGRE compare match
+    ELC_EVENT_TGIF0          = (75),   // MTU0.TGRF compare match
+    ELC_EVENT_TGIA1          = (76),   // MTU1.TGRA input capture/compare match
+    ELC_EVENT_TGIB1          = (77),   // MTU1.TGRB input capture/compare match
+    ELC_EVENT_TCIV1          = (78),   // MTU1.TCNT overflow
+    ELC_EVENT_TCIU1          = (79),   // MTU1.TCNT underflow
+    ELC_EVENT_TGIA2          = (80),   // MTU2.TGRA input capture/compare match
+    ELC_EVENT_TGIB2          = (81),   // MTU2.TGRB input capture/compare match
+    ELC_EVENT_TCIV2          = (82),   // MTU2.TCNT overflow
+    ELC_EVENT_TCIU2          = (83),   // MTU2.TCNT underflow
+    ELC_EVENT_TGIA3          = (84),   // MTU3.TGRA input capture/compare match
+    ELC_EVENT_TGIB3          = (85),   // MTU3.TGRB input capture/compare match
+    ELC_EVENT_TGIC3          = (86),   // MTU3.TGRC input capture/compare match
+    ELC_EVENT_TGID3          = (87),   // MTU3.TGRD input capture/compare match
+    ELC_EVENT_TCIV3          = (88),   // MTU3.TCNT overflow
+    ELC_EVENT_TGIA4          = (89),   // MTU4.TGRA input capture/compare match
+    ELC_EVENT_TGIB4          = (90),   // MTU4.TGRB input capture/compare match
+    ELC_EVENT_TGIC4          = (91),   // MTU4.TGRC input capture/compare match
+    ELC_EVENT_TGID4          = (92),   // MTU4.TGRD input capture/compare match
+    ELC_EVENT_TCIV4          = (93),   // MTU4.TCNT overflow/underflow
+    ELC_EVENT_TGIU5          = (94),   // MTU5.TGRU input capture/compare match
+    ELC_EVENT_TGIV5          = (95),   // MTU5.TGRV input capture/compare match
+    ELC_EVENT_TGIW5          = (96),   // MTU5.TGRW input capture/compare match
+    ELC_EVENT_TGIA6          = (97),   // MTU6.TGRA input capture/compare match
+    ELC_EVENT_TGIB6          = (98),   // MTU6.TGRB input capture/compare match
+    ELC_EVENT_TGIC6          = (99),   // MTU6.TGRC input capture/compare match
+    ELC_EVENT_TGID6          = (100),  // MTU6.TGRD input capture/compare match
+    ELC_EVENT_TCIV6          = (101),  // MTU6.TCNT overflow
+    ELC_EVENT_TGIA7          = (102),  // MTU7.TGRA input capture/compare match
+    ELC_EVENT_TGIB7          = (103),  // MTU7.TGRB input capture/compare match
+    ELC_EVENT_TGIC7          = (104),  // MTU7.TGRC input capture/compare match
+    ELC_EVENT_TGID7          = (105),  // MTU7.TGRD input capture/compare match
+    ELC_EVENT_TCIV7          = (106),  // MTU7.TCNT overflow/underflow
+    ELC_EVENT_TGIA8          = (107),  // MTU8.TGRA input capture/compare match
+    ELC_EVENT_TGIB8          = (108),  // MTU8.TGRB input capture/compare match
+    ELC_EVENT_TGIC8          = (109),  // MTU8.TGRC input capture/compare match
+    ELC_EVENT_TGID8          = (110),  // MTU8.TGRD input capture/compare match
+    ELC_EVENT_TCIV8          = (111),  // MTU8.TCNT overflow
+    ELC_EVENT_OEI1           = (112),  // Output enable interrupt 1
+    ELC_EVENT_OEI2           = (113),  // Output enable interrupt 2
+    ELC_EVENT_OEI3           = (114),  // Output enable interrupt 3
+    ELC_EVENT_OEI4           = (115),  // Output enable interrupt 4
+    ELC_EVENT_GPT0_CCMPA     = (116),  // GPT0 GTCCRA input capture/compare match
+    ELC_EVENT_GPT0_CCMPB     = (117),  // GPT0 GTCCRB input capture/compare match
+    ELC_EVENT_GPT0_CMPC      = (118),  // GPT0 GTCCRC compare match
+    ELC_EVENT_GPT0_CMPD      = (119),  // GPT0 GTCCRD compare match
+    ELC_EVENT_GPT0_CMPE      = (120),  // GPT0 GTCCRE compare match
+    ELC_EVENT_GPT0_CMPF      = (121),  // GPT0 GTCCRF compare match
+    ELC_EVENT_GPT0_OVF       = (122),  // GPT0 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT0_UDF       = (123),  // GPT0 GTCNT underflow
+    ELC_EVENT_GPT0_DTE       = (124),  // GPT0 Dead time error
+    ELC_EVENT_GPT1_CCMPA     = (125),  // GPT1 GTCCRA input capture/compare match
+    ELC_EVENT_GPT1_CCMPB     = (126),  // GPT1 GTCCRB input capture/compare match
+    ELC_EVENT_GPT1_CMPC      = (127),  // GPT1 GTCCRC compare match
+    ELC_EVENT_GPT1_CMPD      = (128),  // GPT1 GTCCRD compare match
+    ELC_EVENT_GPT1_CMPE      = (129),  // GPT1 GTCCRE compare match
+    ELC_EVENT_GPT1_CMPF      = (130),  // GPT1 GTCCRF compare match
+    ELC_EVENT_GPT1_OVF       = (131),  // GPT1 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT1_UDF       = (132),  // GPT1 GTCNT underflow
+    ELC_EVENT_GPT1_DTE       = (133),  // GPT1 Dead time error
+    ELC_EVENT_GPT2_CCMPA     = (134),  // GPT2 GTCCRA input capture/compare match
+    ELC_EVENT_GPT2_CCMPB     = (135),  // GPT2 GTCCRB input capture/compare match
+    ELC_EVENT_GPT2_CMPC      = (136),  // GPT2 GTCCRC compare match
+    ELC_EVENT_GPT2_CMPD      = (137),  // GPT2 GTCCRD compare match
+    ELC_EVENT_GPT2_CMPE      = (138),  // GPT2 GTCCRE compare match
+    ELC_EVENT_GPT2_CMPF      = (139),  // GPT2 GTCCRF compare match
+    ELC_EVENT_GPT2_OVF       = (140),  // GPT2 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT2_UDF       = (141),  // GPT2 GTCNT underflow
+    ELC_EVENT_GPT2_DTE       = (142),  // GPT2 Dead time error
+    ELC_EVENT_GPT3_CCMPA     = (143),  // GPT3 GTCCRA input capture/compare match
+    ELC_EVENT_GPT3_CCMPB     = (144),  // GPT3 GTCCRB input capture/compare match
+    ELC_EVENT_GPT3_CMPC      = (145),  // GPT3 GTCCRC compare match
+    ELC_EVENT_GPT3_CMPD      = (146),  // GPT3 GTCCRD compare match
+    ELC_EVENT_GPT3_CMPE      = (147),  // GPT3 GTCCRE compare match
+    ELC_EVENT_GPT3_CMPF      = (148),  // GPT3 GTCCRF compare match
+    ELC_EVENT_GPT3_OVF       = (149),  // GPT3 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT3_UDF       = (150),  // GPT3 GTCNT underflow
+    ELC_EVENT_GPT3_DTE       = (151),  // GPT3 Dead time error
+    ELC_EVENT_GPT4_CCMPA     = (152),  // GPT4 GTCCRA input capture/compare match
+    ELC_EVENT_GPT4_CCMPB     = (153),  // GPT4 GTCCRB input capture/compare match
+    ELC_EVENT_GPT4_CMPC      = (154),  // GPT4 GTCCRC compare match
+    ELC_EVENT_GPT4_CMPD      = (155),  // GPT4 GTCCRD compare match
+    ELC_EVENT_GPT4_CMPE      = (156),  // GPT4 GTCCRE compare match
+    ELC_EVENT_GPT4_CMPF      = (157),  // GPT4 GTCCRF compare match
+    ELC_EVENT_GPT4_OVF       = (158),  // GPT4 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT4_UDF       = (159),  // GPT4 GTCNT underflow
+    ELC_EVENT_GPT4_DTE       = (160),  // GPT4 Dead time error
+    ELC_EVENT_GPT5_CCMPA     = (161),  // GPT5 GTCCRA input capture/compare match
+    ELC_EVENT_GPT5_CCMPB     = (162),  // GPT5 GTCCRB input capture/compare match
+    ELC_EVENT_GPT5_CMPC      = (163),  // GPT5 GTCCRC compare match
+    ELC_EVENT_GPT5_CMPD      = (164),  // GPT5 GTCCRD compare match
+    ELC_EVENT_GPT5_CMPE      = (165),  // GPT5 GTCCRE compare match
+    ELC_EVENT_GPT5_CMPF      = (166),  // GPT5 GTCCRF compare match
+    ELC_EVENT_GPT5_OVF       = (167),  // GPT5 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT5_UDF       = (168),  // GPT5 GTCNT underflow
+    ELC_EVENT_GPT5_DTE       = (169),  // GPT5 Dead time error
+    ELC_EVENT_GPT6_CCMPA     = (170),  // GPT6 GTCCRA input capture/compare match
+    ELC_EVENT_GPT6_CCMPB     = (171),  // GPT6 GTCCRB input capture/compare match
+    ELC_EVENT_GPT6_CMPC      = (172),  // GPT6 GTCCRC compare match
+    ELC_EVENT_GPT6_CMPD      = (173),  // GPT6 GTCCRD compare match
+    ELC_EVENT_GPT6_CMPE      = (174),  // GPT6 GTCCRE compare match
+    ELC_EVENT_GPT6_CMPF      = (175),  // GPT6 GTCCRF compare match
+    ELC_EVENT_GPT6_OVF       = (176),  // GPT6 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT6_UDF       = (177),  // GPT6 GTCNT underflow
+    ELC_EVENT_GPT6_DTE       = (178),  // GPT6 Dead time error
+    ELC_EVENT_GPT7_CCMPA     = (179),  // GPT7 GTCCRA input capture/compare match
+    ELC_EVENT_GPT7_CCMPB     = (180),  // GPT7 GTCCRB input capture/compare match
+    ELC_EVENT_GPT7_CMPC      = (181),  // GPT7 GTCCRC compare match
+    ELC_EVENT_GPT7_CMPD      = (182),  // GPT7 GTCCRD compare match
+    ELC_EVENT_GPT7_CMPE      = (183),  // GPT7 GTCCRE compare match
+    ELC_EVENT_GPT7_CMPF      = (184),  // GPT7 GTCCRF compare match
+    ELC_EVENT_GPT7_OVF       = (185),  // GPT7 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT7_UDF       = (186),  // GPT7 GTCNT underflow
+    ELC_EVENT_GPT7_DTE       = (187),  // GPT7 Dead time error
+    ELC_EVENT_GPT8_CCMPA     = (188),  // GPT8 GTCCRA input capture/compare match
+    ELC_EVENT_GPT8_CCMPB     = (189),  // GPT8 GTCCRB input capture/compare match
+    ELC_EVENT_GPT8_CMPC      = (190),  // GPT8 GTCCRC compare match
+    ELC_EVENT_GPT8_CMPD      = (191),  // GPT8 GTCCRD compare match
+    ELC_EVENT_GPT8_CMPE      = (192),  // GPT8 GTCCRE compare match
+    ELC_EVENT_GPT8_CMPF      = (193),  // GPT8 GTCCRF compare match
+    ELC_EVENT_GPT8_OVF       = (194),  // GPT8 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT8_UDF       = (195),  // GPT8 GTCNT underflow
+    ELC_EVENT_GPT8_DTE       = (196),  // GPT8 Dead time error
+    ELC_EVENT_GPT9_CCMPA     = (197),  // GPT9 GTCCRA input capture/compare match
+    ELC_EVENT_GPT9_CCMPB     = (198),  // GPT9 GTCCRB input capture/compare match
+    ELC_EVENT_GPT9_CMPC      = (199),  // GPT9 GTCCRC compare match
+    ELC_EVENT_GPT9_CMPD      = (200),  // GPT9 GTCCRD compare match
+    ELC_EVENT_GPT9_CMPE      = (201),  // GPT9 GTCCRE compare match
+    ELC_EVENT_GPT9_CMPF      = (202),  // GPT9 GTCCRF compare match
+    ELC_EVENT_GPT9_OVF       = (203),  // GPT9 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT9_UDF       = (204),  // GPT9 GTCNT underflow
+    ELC_EVENT_GPT9_DTE       = (205),  // GPT9 Dead time error
+    ELC_EVENT_GPT10_CCMPA    = (206),  // GPT10 GTCCRA input capture/compare match
+    ELC_EVENT_GPT10_CCMPB    = (207),  // GPT10 GTCCRB input capture/compare match
+    ELC_EVENT_GPT10_CMPC     = (208),  // GPT10 GTCCRC compare match
+    ELC_EVENT_GPT10_CMPD     = (209),  // GPT10 GTCCRD compare match
+    ELC_EVENT_GPT10_CMPE     = (210),  // GPT10 GTCCRE compare match
+    ELC_EVENT_GPT10_CMPF     = (211),  // GPT10 GTCCRF compare match
+    ELC_EVENT_GPT10_OVF      = (212),  // GPT10 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT10_UDF      = (213),  // GPT10 GTCNT underflow
+    ELC_EVENT_GPT10_DTE      = (214),  // GPT10 Dead time error
+    ELC_EVENT_GPT11_CCMPA    = (215),  // GPT11 GTCCRA input capture/compare match
+    ELC_EVENT_GPT11_CCMPB    = (216),  // GPT11 GTCCRB input capture/compare match
+    ELC_EVENT_GPT11_CMPC     = (217),  // GPT11 GTCCRC compare match
+    ELC_EVENT_GPT11_CMPD     = (218),  // GPT11 GTCCRD compare match
+    ELC_EVENT_GPT11_CMPE     = (219),  // GPT11 GTCCRE compare match
+    ELC_EVENT_GPT11_CMPF     = (220),  // GPT11 GTCCRF compare match
+    ELC_EVENT_GPT11_OVF      = (221),  // GPT11 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT11_UDF      = (222),  // GPT11 GTCNT underflow
+    ELC_EVENT_GPT11_DTE      = (223),  // GPT11 Dead time error
+    ELC_EVENT_GPT12_CCMPA    = (224),  // GPT12 GTCCRA input capture/compare match
+    ELC_EVENT_GPT12_CCMPB    = (225),  // GPT12 GTCCRB input capture/compare match
+    ELC_EVENT_GPT12_CMPC     = (226),  // GPT12 GTCCRC compare match
+    ELC_EVENT_GPT12_CMPD     = (227),  // GPT12 GTCCRD compare match
+    ELC_EVENT_GPT12_CMPE     = (228),  // GPT12 GTCCRE compare match
+    ELC_EVENT_GPT12_CMPF     = (229),  // GPT12 GTCCRF compare match
+    ELC_EVENT_GPT12_OVF      = (230),  // GPT12 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT12_UDF      = (231),  // GPT12 GTCNT underflow
+    ELC_EVENT_GPT12_DTE      = (232),  // GPT12 Dead time error
+    ELC_EVENT_GPT13_CCMPA    = (233),  // GPT13 GTCCRA input capture/compare match
+    ELC_EVENT_GPT13_CCMPB    = (234),  // GPT13 GTCCRB input capture/compare match
+    ELC_EVENT_GPT13_CMPC     = (235),  // GPT13 GTCCRC compare match
+    ELC_EVENT_GPT13_CMPD     = (236),  // GPT13 GTCCRD compare match
+    ELC_EVENT_GPT13_CMPE     = (237),  // GPT13 GTCCRE compare match
+    ELC_EVENT_GPT13_CMPF     = (238),  // GPT13 GTCCRF compare match
+    ELC_EVENT_GPT13_OVF      = (239),  // GPT13 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT13_UDF      = (240),  // GPT13 GTCNT underflow
+    ELC_EVENT_GPT13_DTE      = (241),  // GPT13 Dead time error
+    ELC_EVENT_POEG0_GROUP0   = (242),  // POEG group A interrupt for channels in LLPP
+    ELC_EVENT_POEG0_GROUP1   = (243),  // POEG group B interrupt for channels in LLPP
+    ELC_EVENT_POEG0_GROUP2   = (244),  // POEG group C interrupt for channels in LLPP
+    ELC_EVENT_POEG0_GROUP3   = (245),  // POEG group D interrupt for channels in LLPP
+    ELC_EVENT_POEG1_GROUP0   = (246),  // POEG group A interrupt for channels in NONSAFETY
+    ELC_EVENT_POEG1_GROUP1   = (247),  // POEG group B interrupt for channels in NONSAFETY
+    ELC_EVENT_POEG1_GROUP2   = (248),  // POEG group C interrupt for channels in NONSAFETY
+    ELC_EVENT_POEG1_GROUP3   = (249),  // POEG group D interrupt for channels in NONSAFETY
+    ELC_EVENT_GMAC_LPI       = (250),  // GMAC1 energy efficient
+    ELC_EVENT_GMAC_PMT       = (251),  // GMAC1 power management
+    ELC_EVENT_GMAC_SBD       = (252),  // GMAC1 general interrupt
+    ELC_EVENT_ETHSW_INTR     = (253),  // Ethernet Switch interrupt
+    ELC_EVENT_ETHSW_DLR      = (254),  // Ethernet Switch DLR interrupt
+    ELC_EVENT_ETHSW_PRP      = (255),  // Ethernet Switch PRP interrupt
+    ELC_EVENT_ETHSW_IHUB     = (256),  // Ethernet Switch Integrated Hub interrupt
+    ELC_EVENT_ETHSW_PTRN0    = (257),  // Ethernet Switch RX Pattern Matcher interrupt 0
+    ELC_EVENT_ETHSW_PTRN1    = (258),  // Ethernet Switch RX Pattern Matcher interrupt 1
+    ELC_EVENT_ETHSW_PTRN2    = (259),  // Ethernet Switch RX Pattern Matcher interrupt 2
+    ELC_EVENT_ETHSW_PTRN3    = (260),  // Ethernet Switch RX Pattern Matcher interrupt 3
+    ELC_EVENT_ETHSW_PTRN4    = (261),  // Ethernet Switch RX Pattern Matcher interrupt 4
+    ELC_EVENT_ETHSW_PTRN5    = (262),  // Ethernet Switch RX Pattern Matcher interrupt 5
+    ELC_EVENT_ETHSW_PTRN6    = (263),  // Ethernet Switch RX Pattern Matcher interrupt 6
+    ELC_EVENT_ETHSW_PTRN7    = (264),  // Ethernet Switch RX Pattern Matcher interrupt 7
+    ELC_EVENT_ETHSW_PTRN8    = (265),  // Ethernet Switch RX Pattern Matcher interrupt 8
+    ELC_EVENT_ETHSW_PTRN9    = (266),  // Ethernet Switch RX Pattern Matcher interrupt 9
+    ELC_EVENT_ETHSW_PTRN10   = (267),  // Ethernet Switch RX Pattern Matcher interrupt 10
+    ELC_EVENT_ETHSW_PTRN11   = (268),  // Ethernet Switch RX Pattern Matcher interrupt 11
+    ELC_EVENT_ETHSW_PTPOUT0  = (269),  // Ethernet switch timer pulse output 0
+    ELC_EVENT_ETHSW_PTPOUT1  = (270),  // Ethernet switch timer pulse output 1
+    ELC_EVENT_ETHSW_PTPOUT2  = (271),  // Ethernet switch timer pulse output 2
+    ELC_EVENT_ETHSW_PTPOUT3  = (272),  // Ethernet switch timer pulse output 3
+    ELC_EVENT_ETHSW_TDMAOUT0 = (273),  // Ethernet Switch TDMA timer output 0
+    ELC_EVENT_ETHSW_TDMAOUT1 = (274),  // Ethernet Switch TDMA timer output 1
+    ELC_EVENT_ETHSW_TDMAOUT2 = (275),  // Ethernet Switch TDMA timer output 2
+    ELC_EVENT_ETHSW_TDMAOUT3 = (276),  // Ethernet Switch TDMA timer output 3
+    ELC_EVENT_ESC_SYNC0      = (277),  // EtherCAT Sync0 interrupt
+    ELC_EVENT_ESC_SYNC1      = (278),  // EtherCAT Sync1 interrupt
+    ELC_EVENT_ESC_CAT        = (279),  // EtherCAT interrupt
+    ELC_EVENT_ESC_SOF        = (280),  // EtherCAT SOF interrupt
+    ELC_EVENT_ESC_EOF        = (281),  // EtherCAT EOF interrupt
+    ELC_EVENT_ESC_WDT        = (282),  // EtherCAT WDT interrupt
+    ELC_EVENT_ESC_RST        = (283),  // EtherCAT RESET interrupt
+    ELC_EVENT_USB_HI         = (284),  // USB (Host) interrupt
+    ELC_EVENT_USB_FI         = (285),  // USB (Function) interrupt
+    ELC_EVENT_USB_FDMA0      = (286),  // USB (Function) DMA 0 transmit completion
+    ELC_EVENT_USB_FDMA1      = (287),  // USB (Function) DMA 1 transmit completion
+    ELC_EVENT_SCI0_ERI       = (288),  // SCI0 Receive error
+    ELC_EVENT_SCI0_RXI       = (289),  // SCI0 Receive data full
+    ELC_EVENT_SCI0_TXI       = (290),  // SCI0 Transmit data empty
+    ELC_EVENT_SCI0_TEI       = (291),  // SCI0 Transmit end
+    ELC_EVENT_SCI1_ERI       = (292),  // SCI1 Receive error
+    ELC_EVENT_SCI1_RXI       = (293),  // SCI1 Receive data full
+    ELC_EVENT_SCI1_TXI       = (294),  // SCI1 Transmit data empty
+    ELC_EVENT_SCI1_TEI       = (295),  // SCI1 Transmit end
+    ELC_EVENT_SCI2_ERI       = (296),  // SCI2 Receive error
+    ELC_EVENT_SCI2_RXI       = (297),  // SCI2 Receive data full
+    ELC_EVENT_SCI2_TXI       = (298),  // SCI2 Transmit data empty
+    ELC_EVENT_SCI2_TEI       = (299),  // SCI2 Transmit end
+    ELC_EVENT_SCI3_ERI       = (300),  // SCI3 Receive error
+    ELC_EVENT_SCI3_RXI       = (301),  // SCI3 Receive data full
+    ELC_EVENT_SCI3_TXI       = (302),  // SCI3 Transmit data empty
+    ELC_EVENT_SCI3_TEI       = (303),  // SCI3 Transmit end
+    ELC_EVENT_SCI4_ERI       = (304),  // SCI4 Receive error
+    ELC_EVENT_SCI4_RXI       = (305),  // SCI4 Receive data full
+    ELC_EVENT_SCI4_TXI       = (306),  // SCI4 Transmit data empty
+    ELC_EVENT_SCI4_TEI       = (307),  // SCI4 Transmit end
+    ELC_EVENT_IIC0_EEI       = (308),  // IIC0 Transfer error or event generation
+    ELC_EVENT_IIC0_RXI       = (309),  // IIC0 Receive data full
+    ELC_EVENT_IIC0_TXI       = (310),  // IIC0 Transmit data empty
+    ELC_EVENT_IIC0_TEI       = (311),  // IIC0 Transmit end
+    ELC_EVENT_IIC1_EEI       = (312),  // IIC1 Transfer error or event generation
+    ELC_EVENT_IIC1_RXI       = (313),  // IIC1 Receive data full
+    ELC_EVENT_IIC1_TXI       = (314),  // IIC1 Transmit data empty
+    ELC_EVENT_IIC1_TEI       = (315),  // IIC1 Transmit end
+    ELC_EVENT_CAN_RXF        = (316),  // CANFD RX FIFO interrupt
+    ELC_EVENT_CAN_GLERR      = (317),  // CANFD Global error interrupt
+    ELC_EVENT_CAN0_TX        = (318),  // CAFND0 Channel TX interrupt
+    ELC_EVENT_CAN0_CHERR     = (319),  // CAFND0 Channel CAN error interrupt
+    ELC_EVENT_CAN0_COMFRX    = (320),  // CAFND0 Common RX FIFO or TXQ interrupt
+    ELC_EVENT_CAN1_TX        = (321),  // CAFND1 Channel TX interrupt
+    ELC_EVENT_CAN1_CHERR     = (322),  // CAFND1 Channel CAN error interrupt
+    ELC_EVENT_CAN1_COMFRX    = (323),  // CAFND1 Common RX FIFO or TXQ interrupt
+    ELC_EVENT_SPI0_SPRI      = (324),  // SPI0 Reception buffer full
+    ELC_EVENT_SPI0_SPTI      = (325),  // SPI0 Transmit buffer empty
+    ELC_EVENT_SPI0_SPII      = (326),  // SPI0 SPI idle
+    ELC_EVENT_SPI0_SPEI      = (327),  // SPI0 errors
+    ELC_EVENT_SPI0_SPCEND    = (328),  // SPI0 Communication complete
+    ELC_EVENT_SPI1_SPRI      = (329),  // SPI1 Reception buffer full
+    ELC_EVENT_SPI1_SPTI      = (330),  // SPI1 Transmit buffer empty
+    ELC_EVENT_SPI1_SPII      = (331),  // SPI1 SPI idle
+    ELC_EVENT_SPI1_SPEI      = (332),  // SPI1 errors
+    ELC_EVENT_SPI1_SPCEND    = (333),  // SPI1 Communication complete
+    ELC_EVENT_SPI2_SPRI      = (334),  // SPI2 Reception buffer full
+    ELC_EVENT_SPI2_SPTI      = (335),  // SPI2 Transmit buffer empty
+    ELC_EVENT_SPI2_SPII      = (336),  // SPI2 SPI idle
+    ELC_EVENT_SPI2_SPEI      = (337),  // SPI2 errors
+    ELC_EVENT_SPI2_SPCEND    = (338),  // SPI2 Communication complete
+    ELC_EVENT_XSPI0_INT      = (339),  // xSPI0 Interrupt
+    ELC_EVENT_XSPI0_INTERR   = (340),  // xSPI0 Error interrupt
+    ELC_EVENT_XSPI1_INT      = (341),  // xSPI1 Interrupt
+    ELC_EVENT_XSPI1_INTERR   = (342),  // xSPI1 Error interrupt
+    ELC_EVENT_DSMIF0_CDRUI   = (343),  // DSMIF0 current data register update (ORed ch0 to ch2)
+    ELC_EVENT_DSMIF1_CDRUI   = (344),  // DSMIF1 current data register update (ORed ch3 to ch5)
+    ELC_EVENT_ADC0_ADI       = (345),  // ADC0 A/D scan end interrupt
+    ELC_EVENT_ADC0_GBADI     = (346),  // ADC0 A/D scan end interrupt for Group B
+    ELC_EVENT_ADC0_GCADI     = (347),  // ADC0 A/D scan end interrupt for Group C
+    ELC_EVENT_ADC0_CMPAI     = (348),  // ADC0 Window A compare match
+    ELC_EVENT_ADC0_CMPBI     = (349),  // ADC0 Window B compare match
+    ELC_EVENT_ADC1_ADI       = (350),  // ADC1 A/D scan end interrupt
+    ELC_EVENT_ADC1_GBADI     = (351),  // ADC1 A/D scan end interrupt for Group B
+    ELC_EVENT_ADC1_GCADI     = (352),  // ADC1 A/D scan end interrupt for Group C
+    ELC_EVENT_ADC1_CMPAI     = (353),  // ADC1 Window A compare match
+    ELC_EVENT_ADC1_CMPBI     = (354),  // ADC1 Window B compare match
+    ELC_EVENT_MBX_INT0       = (372),  // Mailbox (Host CPU to Cortex-R52) interrupt 0
+    ELC_EVENT_MBX_INT1       = (373),  // Mailbox (Host CPU to Cortex-R52) interrupt 1
+    ELC_EVENT_MBX_INT2       = (374),  // Mailbox (Host CPU to Cortex-R52) interrupt 2
+    ELC_EVENT_MBX_INT3       = (375),  // Mailbox (Host CPU to Cortex-R52) interrupt 3
+    ELC_EVENT_CPU0_ERR0      = (384),  // Cortex-R52 CPU0 error event 0
+    ELC_EVENT_CPU0_ERR1      = (385),  // Cortex-R52 CPU0 error event 1
+    ELC_EVENT_PERI_ERR0      = (388),  // Peripherals error event 0
+    ELC_EVENT_PERI_ERR1      = (389),  // Peripherals error event 1
+    ELC_EVENT_SHOST_INT      = (390),  // SHOSTIF interrupt
+    ELC_EVENT_PHOST_INT      = (391),  // PHOSTIF interrupt
+    ELC_EVENT_INTCPU6        = (392),  // Software interrupt 6
+    ELC_EVENT_INTCPU7        = (393),  // Software interrupt 7
+    ELC_EVENT_IRQ14          = (394),  // External pin interrupt 14
+    ELC_EVENT_IRQ15          = (395),  // External pin interrupt 15
+    ELC_EVENT_GPT14_CCMPA    = (396),  // GPT14 GTCCRA input capture/compare match
+    ELC_EVENT_GPT14_CCMPB    = (397),  // GPT14 GTCCRB input capture/compare match
+    ELC_EVENT_GPT14_CMPC     = (398),  // GPT14 GTCCRC compare match
+    ELC_EVENT_GPT14_CMPD     = (399),  // GPT14 GTCCRD compare match
+    ELC_EVENT_GPT14_CMPE     = (400),  // GPT14 GTCCRE compare match
+    ELC_EVENT_GPT14_CMPF     = (401),  // GPT14 GTCCRF compare match
+    ELC_EVENT_GPT14_OVF      = (402),  // GPT14 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT14_UDF      = (403),  // GPT14 GTCNT underflow
+    ELC_EVENT_GPT15_CCMPA    = (404),  // GPT15 GTCCRA input capture/compare match
+    ELC_EVENT_GPT15_CCMPB    = (405),  // GPT15 GTCCRB input capture/compare match
+    ELC_EVENT_GPT15_CMPC     = (406),  // GPT15 GTCCRC compare match
+    ELC_EVENT_GPT15_CMPD     = (407),  // GPT15 GTCCRD compare match
+    ELC_EVENT_GPT15_CMPE     = (408),  // GPT15 GTCCRE compare match
+    ELC_EVENT_GPT15_CMPF     = (409),  // GPT15 GTCCRF compare match
+    ELC_EVENT_GPT15_OVF      = (410),  // GPT15 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT15_UDF      = (411),  // GPT15 GTCNT underflow
+    ELC_EVENT_GPT16_CCMPA    = (412),  // GPT16 GTCCRA input capture/compare match
+    ELC_EVENT_GPT16_CCMPB    = (413),  // GPT16 GTCCRB input capture/compare match
+    ELC_EVENT_GPT16_CMPC     = (414),  // GPT16 GTCCRC compare match
+    ELC_EVENT_GPT16_CMPD     = (415),  // GPT16 GTCCRD compare match
+    ELC_EVENT_GPT16_CMPE     = (416),  // GPT16 GTCCRE compare match
+    ELC_EVENT_GPT16_CMPF     = (417),  // GPT16 GTCCRF compare match
+    ELC_EVENT_GPT16_OVF      = (418),  // GPT16 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT16_UDF      = (419),  // GPT16 GTCNT underflow
+    ELC_EVENT_GPT17_CCMPA    = (420),  // GPT17 GTCCRA input capture/compare match
+    ELC_EVENT_GPT17_CCMPB    = (421),  // GPT17 GTCCRB input capture/compare match
+    ELC_EVENT_GPT17_CMPC     = (422),  // GPT17 GTCCRC compare match
+    ELC_EVENT_GPT17_CMPD     = (423),  // GPT17 GTCCRD compare match
+    ELC_EVENT_GPT17_CMPE     = (424),  // GPT17 GTCCRE compare match
+    ELC_EVENT_GPT17_CMPF     = (425),  // GPT17 GTCCRF compare match
+    ELC_EVENT_GPT17_OVF      = (426),  // GPT17 GTCNT overflow (GTPR compare match)
+    ELC_EVENT_GPT17_UDF      = (427),  // GPT17 GTCNT underflow
+    ELC_EVENT_POEG2_GROUP0   = (428),  // POEG group A interrupt for channels in SAFETY
+    ELC_EVENT_POEG2_GROUP1   = (429),  // POEG group B interrupt for channels in SAFETY
+    ELC_EVENT_POEG2_GROUP2   = (430),  // POEG group C interrupt for channels in SAFETY
+    ELC_EVENT_POEG2_GROUP3   = (431),  // POEG group D interrupt for channels in SAFETY
+    ELC_EVENT_RTC_ALM        = (432),  // Alarm interrupt
+    ELC_EVENT_RTC_1S         = (433),  // 1 second interrupt
+    ELC_EVENT_RTC_PRD        = (434),  // Fixed interval interrupt
+    ELC_EVENT_SCI5_ERI       = (435),  // SCI5 Receive error
+    ELC_EVENT_SCI5_RXI       = (436),  // SCI5 Receive data full
+    ELC_EVENT_SCI5_TXI       = (437),  // SCI5 Transmit data empty
+    ELC_EVENT_SCI5_TEI       = (438),  // SCI5 Transmit end
+    ELC_EVENT_IIC2_EEI       = (439),  // IIC2 Transfer error or event generation
+    ELC_EVENT_IIC2_RXI       = (440),  // IIC2 Receive data full
+    ELC_EVENT_IIC2_TXI       = (441),  // IIC2 Transmit data empty
+    ELC_EVENT_IIC2_TEI       = (442),  // IIC2 Transmit end
+    ELC_EVENT_SPI3_SPRI      = (443),  // SPI3 Reception buffer full
+    ELC_EVENT_SPI3_SPTI      = (444),  // SPI3 Transmit buffer empty
+    ELC_EVENT_SPI3_SPII      = (445),  // SPI3 SPI idle
+    ELC_EVENT_SPI3_SPEI      = (446),  // SPI3 errors
+    ELC_EVENT_SPI3_SPCEND    = (447),  // SPI3 Communication complete
+    ELC_EVENT_DREQ           = (448),  // External DMA request
+    ELC_EVENT_CAN_RF_DMAREQ0 = (449),  // CAFND RX FIFO 0 DMA request
+    ELC_EVENT_CAN_RF_DMAREQ1 = (450),  // CAFND RX FIFO 1 DMA request
+    ELC_EVENT_CAN_RF_DMAREQ2 = (451),  // CAFND RX FIFO 2 DMA request
+    ELC_EVENT_CAN_RF_DMAREQ3 = (452),  // CAFND RX FIFO 3 DMA request
+    ELC_EVENT_CAN_RF_DMAREQ4 = (453),  // CAFND RX FIFO 4 DMA request
+    ELC_EVENT_CAN_RF_DMAREQ5 = (454),  // CAFND RX FIFO 5 DMA request
+    ELC_EVENT_CAN_RF_DMAREQ6 = (455),  // CAFND RX FIFO 6 DMA request
+    ELC_EVENT_CAN_RF_DMAREQ7 = (456),  // CAFND RX FIFO 7 DMA request
+    ELC_EVENT_CAN0_CF_DMAREQ = (457),  // CAFND0 First common FIFO DMA request
+    ELC_EVENT_CAN1_CF_DMAREQ = (458),  // CAFND1 First common FIFO DMA request
+    ELC_EVENT_ADC0_WCMPM     = (459),  // ADC0 compare match
+    ELC_EVENT_ADC0_WCMPUM    = (460),  // ADC0 compare mismatch
+    ELC_EVENT_ADC1_WCMPM     = (461),  // ADC1 compare match
+    ELC_EVENT_ADC1_WCMPUM    = (462),  // ADC1 compare mismatch
+    ELC_EVENT_TCIV4_OF       = (463),  // MTU4.TCNT overflow
+    ELC_EVENT_TCIV4_UF       = (464),  // MTU4.TCNT underflow
+    ELC_EVENT_TCIV7_OF       = (465),  // MTU7.TCNT overflow
+    ELC_EVENT_TCIV7_UF       = (466),  // MTU7.TCNT underflow
+    ELC_EVENT_IOPORT_GROUP1  = (467),  // Input edge detection of input port group 1
+    ELC_EVENT_IOPORT_GROUP2  = (468),  // Input edge detection of input port group 2
+    ELC_EVENT_IOPORT_SINGLE0 = (469),  // Input edge detection of single input port 0
+    ELC_EVENT_IOPORT_SINGLE1 = (470),  // Input edge detection of single input port 1
+    ELC_EVENT_IOPORT_SINGLE2 = (471),  // Input edge detection of single input port 2
+    ELC_EVENT_IOPORT_SINGLE3 = (472),  // Input edge detection of single input port 3
+    ELC_EVENT_GPT0_ADTRGA    = (473),  // GPT0 GTADTRA compare match
+    ELC_EVENT_GPT0_ADTRGB    = (474),  // GPT0 GTADTRB compare match
+    ELC_EVENT_GPT1_ADTRGA    = (475),  // GPT1 GTADTRA compare match
+    ELC_EVENT_GPT1_ADTRGB    = (476),  // GPT1 GTADTRB compare match
+    ELC_EVENT_GPT2_ADTRGA    = (477),  // GPT2 GTADTRA compare match
+    ELC_EVENT_GPT2_ADTRGB    = (478),  // GPT2 GTADTRB compare match
+    ELC_EVENT_GPT3_ADTRGA    = (479),  // GPT3 GTADTRA compare match
+    ELC_EVENT_GPT3_ADTRGB    = (480),  // GPT3 GTADTRB compare match
+    ELC_EVENT_GPT4_ADTRGA    = (481),  // GPT4 GTADTRA compare match
+    ELC_EVENT_GPT4_ADTRGB    = (482),  // GPT4 GTADTRB compare match
+    ELC_EVENT_GPT5_ADTRGA    = (483),  // GPT5 GTADTRA compare match
+    ELC_EVENT_GPT5_ADTRGB    = (484),  // GPT5 GTADTRB compare match
+    ELC_EVENT_GPT6_ADTRGA    = (485),  // GPT6 GTADTRA compare match
+    ELC_EVENT_GPT6_ADTRGB    = (486),  // GPT6 GTADTRB compare match
+    ELC_EVENT_GPT7_ADTRGA    = (487),  // GPT7 GTADTRA compare match
+    ELC_EVENT_GPT7_ADTRGB    = (488),  // GPT7 GTADTRB compare match
+    ELC_EVENT_GPT8_ADTRGA    = (489),  // GPT8 GTADTRA compare match
+    ELC_EVENT_GPT8_ADTRGB    = (490),  // GPT8 GTADTRB compare match
+    ELC_EVENT_GPT9_ADTRGA    = (491),  // GPT9 GTADTRA compare match
+    ELC_EVENT_GPT9_ADTRGB    = (492),  // GPT9 GTADTRB compare match
+    ELC_EVENT_GPT10_ADTRGA   = (493),  // GPT10 GTADTRA compare match
+    ELC_EVENT_GPT10_ADTRGB   = (494),  // GPT10 GTADTRB compare match
+    ELC_EVENT_GPT11_ADTRGA   = (495),  // GPT11 GTADTRA compare match
+    ELC_EVENT_GPT11_ADTRGB   = (496),  // GPT11 GTADTRB compare match
+    ELC_EVENT_GPT12_ADTRGA   = (497),  // GPT12 GTADTRA compare match
+    ELC_EVENT_GPT12_ADTRGB   = (498),  // GPT12 GTADTRB compare match
+    ELC_EVENT_GPT13_ADTRGA   = (499),  // GPT13 GTADTRA compare match
+    ELC_EVENT_GPT13_ADTRGB   = (500),  // GPT13 GTADTRB compare match
+    ELC_EVENT_NONE
+} elc_event_t;
+
+/** @} (end addtogroup BSP_MCU_RZN2L) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h
new file mode 100644
index 00000000..1d6e7f19
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h
@@ -0,0 +1,455 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BSP_FEATURE_H
+#define BSP_FEATURE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_FEATURE_ADC_ADDITION_SUPPORTED                     (1U)
+#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE              (0U)
+#define BSP_FEATURE_ADC_CLOCK_SOURCE                           (FSP_PRIV_CLOCK_PCLKADC)
+#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED                (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC                        (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT                       (1U)
+#define BSP_FEATURE_ADC_HAS_PGA                                (1U)
+#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG                    (1U)
+#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_UNIT_NUM               (1U)
+#define BSP_FEATURE_ADC_HAS_VREFAMPCNT                         (0U)
+#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS                    (12U)
+#define BSP_FEATURE_ADC_REGISTER_MASK_TYPE                     (1U)
+#define BSP_FEATURE_ADC_SAMPLE_STATE_COUNT_TYPE                (1U)
+#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME               (4150U)
+#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE                      (0U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE              (0U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE            (1U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK                 (0x00000FFFU)
+#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE                  (1U)
+#define BSP_FEATURE_ADC_TSN_SLOPE                              (4000U)
+#define BSP_FEATURE_ADC_UNIT_0_CHANNELS                        (0x000FU) // 0 to 3 in unit0
+#define BSP_FEATURE_ADC_UNIT_1_CHANNELS                        (0x00FFU) // 0 to 7 in unit1
+#define BSP_FEATURE_ADC_UNIT_2_CHANNELS                        (0x0000U) // unit2 is unsupported
+#define BSP_FEATURE_ADC_UNIT                                   (2U)
+#define BSP_FEATURE_ADC_VALID_UNIT_MASK                        (3U)
+
+#define BSP_FEATURE_ADDRESS_EXPANDER_SUPPORTED                 (0U)
+
+#define BSP_FEATURE_BSC_32BIT_DATA_BUS_WIDTH_SUPPORTED         (0U)
+#define BSP_FEATURE_BSC_HAS_CS_MIRROR_AREA                     (1U)
+#define BSP_FEATURE_BSC_NOR_CS0_BASE_ADDRESS                   (0x00000000U)
+#define BSP_FEATURE_BSC_NOR_CS2_BASE_ADDRESS                   (0x00000000U)
+#define BSP_FEATURE_BSC_NOR_CS3_BASE_ADDRESS                   (0x00000000U)
+#define BSP_FEATURE_BSC_NOR_CS5_BASE_ADDRESS                   (0x00000000U)
+#define BSP_FEATURE_BSC_NOR_CS0_BASE_MIRROR_ADDRESS            (0x50000000U)
+#define BSP_FEATURE_BSC_NOR_CS2_BASE_MIRROR_ADDRESS            (0x54000000U)
+#define BSP_FEATURE_BSC_NOR_CS3_BASE_MIRROR_ADDRESS            (0x58000000U)
+#define BSP_FEATURE_BSC_NOR_CS5_BASE_MIRROR_ADDRESS            (0x5C000000U)
+
+#define BSP_FEATURE_BSP_AFMT_UNIT                              (0U)
+#define BSP_FEATURE_BSP_BISS_UNIT                              (0U)
+#define BSP_FEATURE_BSP_BOOT_PARAMETER                         (1U)
+#define BSP_FEATURE_BSP_CA55_CORE_NUM                          (0U)
+#define BSP_FEATURE_BSP_CR52_CORE_NUM                          (1U)
+#define BSP_FEATURE_BSP_CS0_BASE_ADDRESS                       (0x70000000U)
+#define BSP_FEATURE_BSP_CS0_SIZE                               (0x10000000U)
+#define BSP_FEATURE_BSP_DDRSS_SUPPORTED                        (0U)
+#define BSP_FEATURE_BSP_ENCOUT_SUPPORTED                       (0U)
+#define BSP_FEATURE_BSP_ENDAT_UNIT                             (0U)
+#define BSP_FEATURE_BSP_EVENT_NUM_MAX                          (500)
+#define BSP_FEATURE_BSP_HAS_CR52_CPU1_TCM                      (0U)
+#define BSP_FEATURE_BSP_HAS_CR52_CPU1_LLPP                     (0U)
+#define BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA              (1U)
+#define BSP_FEATURE_BSP_HDSL_UNIT                              (0U)
+#define BSP_FEATURE_BSP_IO_REGION_ADDRESS_DIFF_DEDICATED       (0U)
+#define BSP_FEATURE_BSP_IO_REGION_ADDRESS_DIFF_SELECTABLE      (R_PORT_SR_BASE - R_PORT_NSR_BASE)
+#define BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE          (R_PORT_NSR_BASE)
+#define BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_PORT          (25U)
+#define BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED                 (0U)
+#define BSP_FEATURE_BSP_IRQ_ENCIF_SEL_SUPPORTED                (0U)
+#define BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED                  (0U)
+#define BSP_FEATURE_BSP_IRQ_PRIORITY_MASK                      (0xF8U)
+#define BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT                   (3U)
+#define BSP_FEATURE_BSP_LCDC_SUPPORTED                         (0U)
+#define BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE                 (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU5_SUPPORTED                  (0U)
+#define BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_MASTER_MPU9_SUPPORTED                  (0U)
+#define BSP_FEATURE_BSP_MASTER_MPU10_SUPPORTED                 (0U)
+#define BSP_FEATURE_BSP_MASTER_MPU11_SUPPORTED                 (0U)
+#define BSP_FEATURE_BSP_MASTER_MPU12_SUPPORTED                 (0U)
+#define BSP_FEATURE_BSP_MASTER_MPU13_SUPPORTED                 (0U)
+#define BSP_FEATURE_BSP_MASTER_MPU14_SUPPORTED                 (0U)
+#define BSP_FEATURE_BSP_MASTER_MPU15_SUPPORTED                 (0U)
+#define BSP_FEATURE_BSP_MODULE_RESET_DUMMY_READ_COUNT          (3U)
+#define BSP_FEATURE_BSP_MSTP_CA55_HAS_MSTPCRN                  (0U)
+#define BSP_FEATURE_BSP_MSTP_CR52_CPU1_HAS_MSTPCRH             (0U)
+#define BSP_FEATURE_BSP_MSTP_CR52_HAS_MSTPCRN                  (0U)
+#define BSP_FEATURE_BSP_NON_SELECTABLE_INTERRUPT_EVENT_NUM     (448)
+#define BSP_FEATURE_BSP_PCIE_SUPPORTED                         (0U)
+#define BSP_FEATURE_BSP_SDHI_SUPPORTED                         (0U)
+#define BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_EVENT_NUM         (0)
+#define BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_START             (0)
+#define BSP_FEATURE_BSP_SEMAPHORE_SUPPORTED                    (0U)
+#define BSP_FEATURE_BSP_SHOSTIF_SUPPORTED                      (1U)
+#define BSP_FEATURE_BSP_PHOSTIF_SUPPORTED                      (1U)
+#define BSP_FEATURE_BSP_SLAVE_STOP_SUPPORTED                   (0U)
+#define BSP_FEATURE_BSP_TRACE_CLOCK_SUPPORTED                  (1U)
+#define BSP_FEATURE_BSP_XSPI0_CS0_BASE_ADDRESS                 (0x60000000U)
+#define BSP_FEATURE_BSP_XSPI0_CS0_SIZE                         (0x8000000U)
+#define BSP_FEATURE_BSP_XSPI1_CS0_BASE_ADDRESS                 (0x68000000U)
+#define BSP_FEATURE_BSP_XSPI1_CS0_SIZE                         (0x8000000U)
+
+#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO                      (0U)
+#define BSP_FEATURE_CAN_CLOCK                                  (0U)
+#define BSP_FEATURE_CAN_MCLOCK_ONLY                            (0U)
+#define BSP_FEATURE_CAN_NUM_CHANNELS                           (2U)
+
+#define BSP_FEATURE_CANFD_NUM_CHANNELS                         (2U)
+#define BSP_FEATURE_CANFD_NUM_INSTANCES                        (1U)
+
+#define BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE                   (1U)
+#define BSP_FEATURE_CGC_CLMA_UNIT                              (4U)
+#define BSP_FEATURE_CGC_CLOCK_SOURCE_NUM                       (3)
+#define BSP_FEATURE_CGC_CR52_ATCM_0WAIT_MAX_FREQ_HZ            (400000000U)
+#define BSP_FEATURE_CGC_CR52_CLOCK_TYPE                        (1U)
+#define BSP_FEATURE_CGC_HAS_BCLK                               (1U)
+#define BSP_FEATURE_CGC_HAS_FCLK                               (1U)
+#define BSP_FEATURE_CGC_HAS_FLDWAITR                           (0U)
+#define BSP_FEATURE_CGC_HAS_FLWT                               (1U)
+#define BSP_FEATURE_CGC_HAS_HOCOWTCR                           (1U)
+#define BSP_FEATURE_CGC_HAS_MEMWAIT                            (0U)
+#define BSP_FEATURE_CGC_HAS_PCLKA                              (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKB                              (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKC                              (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKD                              (1U)
+#define BSP_FEATURE_CGC_HAS_PLL                                (1U)
+#define BSP_FEATURE_CGC_HAS_PLL2                               (0U)
+#define BSP_FEATURE_CGC_HAS_PLL3                               (0U)
+#define BSP_FEATURE_CGC_HAS_PLL4                               (0U)
+#define BSP_FEATURE_CGC_HAS_SRAMPRCR2                          (0U)
+#define BSP_FEATURE_CGC_HAS_SRAMWTSC                           (1U)
+#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR                    (0U)
+#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY                    (0U)
+#define BSP_FEATURE_CGC_ICLK_DIV_RESET                         (BSP_CLOCKS_SYS_CLOCK_DIV_4)
+#define BSP_FEATURE_CGC_LOCO_CONTROL_ADDRESS                   (0x81280070U)
+#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US              (61U)
+#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ                  (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
+#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ                (0U)       // This MCU does not have Low Voltage Mode
+#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ               (0U)       // This MCU does not have Middle Speed Mode
+#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US              (15U)
+#define BSP_FEATURE_CGC_MODRV_MASK                             (0x30U)
+#define BSP_FEATURE_CGC_MODRV_SHIFT                            (0x4U)
+#define BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE                (1U)
+#define BSP_FEATURE_CGC_PCLKSPI_CLOCK_FREQ_TYPE                (1U)
+#define BSP_FEATURE_CGC_PLL_OR_MAIN_CLOCK_SELECTABLE           (0U)
+#define BSP_FEATURE_CGC_PLL_START_PROCESS_TYPE                 (1U)
+#define BSP_FEATURE_CGC_PLL0_CONTROL_ADDRESS                   (NULL)
+#define BSP_FEATURE_CGC_PLL0_PROTECT                           (NULL)
+#define BSP_FEATURE_CGC_PLL0_SSC_SUPPORTED                     (0U)
+#define BSP_FEATURE_CGC_PLL0_STANDBY_STATE_SUPPORTED           (0U)
+#define BSP_FEATURE_CGC_PLL1_CONTROL_ADDRESS                   (0x81280050U)
+#define BSP_FEATURE_CGC_PLL1_PROTECT                           (BSP_REG_PROTECT_LPC_RESET)
+#define BSP_FEATURE_CGC_PLL1_STANDBY_STATE_SUPPORTED           (1U)
+#define BSP_FEATURE_CGC_PLL2_CONTROL_ADDRESS                   (NULL)
+#define BSP_FEATURE_CGC_PLL2_PROTECT                           (NULL)
+#define BSP_FEATURE_CGC_PLL2_SSC_SUPPORTED                     (0U)
+#define BSP_FEATURE_CGC_PLL2_STANDBY_STATE_SUPPORTED           (0U)
+#define BSP_FEATURE_CGC_PLL3_CONTROL_ADDRESS                   (NULL)
+#define BSP_FEATURE_CGC_PLL3_PROTECT                           (NULL)
+#define BSP_FEATURE_CGC_PLL3_STANDBY_STATE_SUPPORTED           (0U)
+#define BSP_FEATURE_CGC_PLL3_VCO_SETTING_SUPPORTED             (0U)
+#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ                          (240000000U)
+#define BSP_FEATURE_CGC_PLLCCR_TYPE                            (1U)
+#define BSP_FEATURE_CGC_PLLCCR_WAIT_US                         (0U)
+#define BSP_FEATURE_CGC_SCKCR_TYPE                             (1U)
+#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB            (0U)
+#define BSP_FEATURE_CGC_SODRV_MASK                             (0x02U)
+#define BSP_FEATURE_CGC_SODRV_SHIFT                            (0x1U)
+#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE                     (0U)
+
+#define BSP_FEATURE_CMT_VALID_CHANNEL_MASK                     (0x3FU)
+
+#define BSP_FEATURE_CMTW_VALID_CHANNEL_MASK                    (0x3U)
+
+#define BSP_FEATURE_CRC_VALID_CHANNEL_MASK                     (0x3U)
+
+#define BSP_FEATURE_DDR_SUPPORTED                              (0U)
+#define BSP_FEATURE_DMAC_HAS_CPU1_TCM_AREA                     (0U)
+#define BSP_FEATURE_DMAC_MAX_CHANNEL                           (8U)
+#define BSP_FEATURE_DMAC_MAX_UNIT                              (2U)
+#define BSP_FEATURE_DMAC_UNIT0_ERROR_NUM                       (5U)
+
+#define BSP_FEATURE_DSMIF_ADDRESS_OFFSET                       (0x0400)
+#define BSP_FEATURE_DSMIF_CHANNEL_STATUS                       (1U)
+#define BSP_FEATURE_DSMIF_CORE_CLOCK_SELECTABLE                (0U)
+#define BSP_FEATURE_DSMIF_DATA_FORMAT_SEL                      (0U)
+#define BSP_FEATURE_DSMIF_ERROR_STATUS_CLR                     (5U)
+#define BSP_FEATURE_DSMIF_HAS_LLPP_UNIT                        (2U)
+#define BSP_FEATURE_DSMIF_LLPP_BASE_ADDRESS                    (R_DSMIF0_BASE)
+#define BSP_FEATURE_DSMIF_LLPP1_BASE_ADDRESS                   (0)
+#define BSP_FEATURE_DSMIF_MCLK_FREQ_TYPE                       (1U)
+#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_CONTROL           (1U)
+#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_ISR               (1U)
+#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_NOTIFY            (0U)
+#define BSP_FEATURE_DSMIF_OVERCURRENT_ERROR_STATUS             (1U)
+#define BSP_FEATURE_DSMIF_OVERCURRENT_NOTIFY_STATUS            (0U)
+#define BSP_FEATURE_DSMIF_UNIT                                 (2U)
+#define BSP_FEATURE_DSMIF_VALID_UNIT_MASK                      (0x3U)
+#define BSP_FEATURE_DSMIF_VERSION                              (1U)
+
+#define BSP_FEATURE_ELC_ELC_SSEL_NUM                           (19)
+#define BSP_FEATURE_ELC_EVENT_MASK_NUM                         (4U)
+#define BSP_FEATURE_ELC_GPT_EVENT_MASK_NUM                     (0U)
+#define BSP_FEATURE_ELC_GPT_EVENT_SOURCE_NUM                   (0U)
+#define BSP_FEATURE_ELC_GROUP1_PORT_NUM                        (BSP_IO_PORT_16)
+#define BSP_FEATURE_ELC_GROUP2_PORT_NUM                        (BSP_IO_PORT_18)
+#define BSP_FEATURE_ELC_PERIPHERAL_0_MASK                      (0xFFFFFFFFU) // ELC event source no.0 to 31 available on this MCU
+#define BSP_FEATURE_ELC_PERIPHERAL_1_MASK                      (0x007FF9FFU) // ELC event source no.32 to 63 available on this MCU.
+#define BSP_FEATURE_ELC_PERIPHERAL_2_MASK                      (0x00000000U) // ELC event source no.64 to 95 available on this MCU.
+#define BSP_FEATURE_ELC_PERIPHERAL_3_MASK                      (0x00000000U) // ELC event source no.96 to 127 available on this MCU.
+#define BSP_FEATURE_ELC_PERIPHERAL_4_MASK                      (0x00000000U) // ELC event source no.128 to 159 available on this MCU.
+#define BSP_FEATURE_ELC_PERIPHERAL_5_MASK                      (0x00000000U) // ELC event source no.160 to 191 available on this MCU.
+#define BSP_FEATURE_ELC_PERIPHERAL_6_MASK                      (0x00000000U) // ELC event source no.192 to 223 available on this MCU.
+#define BSP_FEATURE_ELC_PERIPHERAL_7_MASK                      (0x00000000U) // ELC event source no.224 to 255 available on this MCU.
+#define BSP_FEATURE_ELC_PERIPHERAL_TYPE                        (1U)
+
+#define BSP_FEATURE_ESC_MAX_PORTS                              (3U)
+#define BSP_FEATURE_ETHER_FIFO_DEPTH                           (0x0000070FU)
+#define BSP_FEATURE_ETHER_PHY_MAX_CHANNELS                     (3U)
+#define BSP_FEATURE_ETHSS_MAX_PORTS                            (3U)
+#define BSP_FEATURE_ETHSS_SWITCH_MODE_BIT_MASK                 (3U)
+#define BSP_FEATURE_ETHSW_MAX_CHANNELS                         (1U)
+#define BSP_FEATURE_ETHSW_SUPPORTED                            (1U)
+#define BSP_FEATURE_GMAC_B_SUPPORTED                           (0U)
+#define BSP_FEATURE_GMAC_MAX_CHANNELS                          (1U)
+#define BSP_FEATURE_GMAC_MAX_PORTS                             (3U)
+#define BSP_FEATURE_GMAC_UNIT                                  (1U)
+
+#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK                     (0x3FFFF)
+#define BSP_FEATURE_GPT_CHANNEL                                (18U)
+#define BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE        (0U)
+#define BSP_FEATURE_GPT_LLPP_BASE_ADDRESS                      (R_GPT0_BASE)
+#define BSP_FEATURE_GPT_LLPP_BASE_CHANNEL                      (0U) // LLPP channel: ch0-6
+#define BSP_FEATURE_GPT_LLPP_CHANNEL_ADDRESS_OFFSET            (R_GPT1_BASE - R_GPT0_BASE)
+#define BSP_FEATURE_GPT_LLPP_CHANNEL_MASK                      (0x007F)
+#define BSP_FEATURE_GPT_LLPP_CHANNEL_PER_UNIT                  (7U)
+#define BSP_FEATURE_GPT_LLPP_UNIT_ADDRESS_OFFSET               (0U)
+#define BSP_FEATURE_GPT_LLPP1_BASE_ADDRESS                     (0)
+#define BSP_FEATURE_GPT_LLPP1_BASE_CHANNEL                     (0U) // LLPP1 is unsupported
+#define BSP_FEATURE_GPT_LLPP1_CHANNEL_ADDRESS_OFFSET           (0)
+#define BSP_FEATURE_GPT_LLPP1_CHANNEL_MASK                     (0x0000)
+#define BSP_FEATURE_GPT_LLPP1_UNIT_ADDRESS_OFFSET              (0U)
+#define BSP_FEATURE_GPT_NONSAFETY_BASE_ADDRESS                 (R_GPT7_BASE)
+#define BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL                 (7U) // Non-safety channel: ch7-13
+#define BSP_FEATURE_GPT_NONSAFETY_CHANNEL_ADDRESS_OFFSET       (R_GPT8_BASE - R_GPT7_BASE)
+#define BSP_FEATURE_GPT_NONSAFETY_CHANNEL_MASK                 (0x007F)
+#define BSP_FEATURE_GPT_REGISTER_MASK_TYPE                     (1U)
+#define BSP_FEATURE_GPT_SAFETY_BASE_ADDRESS                    (R_GPT14_BASE)
+#define BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL                    (14U) // safety channel: ch14-17
+#define BSP_FEATURE_GPT_SAFETY_CHANNEL_ADDRESS_OFFSET          (R_GPT15_BASE - R_GPT14_BASE)
+#define BSP_FEATURE_GPT_SAFETY_CHANNEL_MASK                    (0x000F)
+#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK                     (0x3FFFF)
+#define BSP_FEATURE_GPTE_CHANNEL_MASK                          (0xF0)
+#define BSP_FEATURE_GPTEH_CHANNEL_MASK                         (0xF)
+
+#define BSP_FEATURE_ICU_ERROR_CA55_SUPPORTED                   (0U)
+#define BSP_FEATURE_ICU_ERROR_CR52_CPU1_SUPPORTED              (0U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR_INTERRUPT_SUPPORTED    (0U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR_REG_NUM                (0U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR0_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR1_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR2_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR3_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR4_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR5_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR7_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR8_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR10_REG_MASK             (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_DSMIF_ERR11_REG_MASK             (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_ENCIF_ERR_INTERRUPT_SUPPORTED    (0U)
+#define BSP_FEATURE_ICU_ERROR_ENCIF_ERR_REG_NUM                (0U)
+#define BSP_FEATURE_ICU_ERROR_ENCIF_ERR0_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_ENCIF_ERR1_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_ENCIF_ERR2_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_ENCIF_ERR3_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_ENCIF_ERR4_REG_MASK              (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_ERR_SOURCE_NUM                   (4U)
+#define BSP_FEATURE_ICU_ERROR_PERI_ERR_REG_NUM                 (2U)
+#define BSP_FEATURE_ICU_ERROR_PERI_ERR0_REG_MASK               (0xFFFFFEFFU)
+#define BSP_FEATURE_ICU_ERROR_PERI_ERR1_REG_MASK               (0x19FFA3FFU)
+#define BSP_FEATURE_ICU_ERROR_PERI_ERR2_REG_MASK               (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_PERI_ERR3_REG_MASK               (0x00000000U)
+#define BSP_FEATURE_ICU_ERROR_PERIPHERAL_TYPE                  (1U)
+#define BSP_FEATURE_ICU_HAS_WUPEN1                             (0U)
+#define BSP_FEATURE_ICU_INTER_CPU_IRQ_CHANNEL                  (0U)
+#define BSP_FEATURE_ICU_INTER_CPU_IRQ_CHANNELS_MASK            (0x00U)
+#define BSP_FEATURE_ICU_INTER_CPU_IRQ_NS_SWINT_MASK            (0x00U) // Non-safety channel: ch0-5  (bit0-5)
+#define BSP_FEATURE_ICU_INTER_CPU_IRQ_S_SWINT_MASK             (0x00U) // Safety channel: ch6-7  (bit6-7)
+#define BSP_FEATURE_ICU_INTER_CPU_IRQ_S_SWINT_SHIFT            (0U)
+#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK                      (0xFFFFU)
+#define BSP_FEATURE_ICU_SAFETY_REGISTER_TYPE                   (1)
+#define BSP_FEATURE_ICU_WUPEN_MASK                             (0xFF4FFFFFU)
+
+#define BSP_FEATURE_IIC_FAST_MODE_PLUS                         (0U)
+#define BSP_FEATURE_IIC_SAFETY_CHANNEL                         (2U)
+#define BSP_FEATURE_IIC_SAFETY_CHANNEL_BASE_ADDRESS            (R_IIC2_BASE)
+#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK                     (0x07)
+
+#define BSP_FEATURE_IOPORT_ELC_PORTS                           (4U)
+#define BSP_FEATURE_IOPORT_HAS_ETHERNET                        (1U)
+#define BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT        (0U)
+#define BSP_FEATURE_IOPORT_PIN_PFC_TYPE                        (1U)
+#define BSP_FEATURE_IOPORT_PORT_NUM                            (25U)
+#define BSP_FEATURE_IOPORT_SELECTABLE_PORT_MAX                 (24U)
+
+#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY                      {{0, 15}, {0, 13}, {1, 31}, {1, 6}, {1, 5}, {1, 4}, \
+                                                                {2, 5}                                             \
+}
+#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED                   (1U)
+#define BSP_FEATURE_LPM_DPSIEGR_MASK                           (0x00137FFFU)
+#define BSP_FEATURE_LPM_DPSIER_MASK                            (0x071F7FFFU)
+#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY                       (1U)
+#define BSP_FEATURE_LPM_HAS_SBYCR_OPE                          (1U)
+#define BSP_FEATURE_LPM_HAS_SNZEDCR1                           (0U)
+#define BSP_FEATURE_LPM_HAS_SNZREQCR1                          (0U)
+#define BSP_FEATURE_LPM_HAS_STCONR                             (1U)
+#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14                       (0U)
+#define BSP_FEATURE_LPM_SNZEDCR_MASK                           (0x000000FFU)
+#define BSP_FEATURE_LPM_SNZREQCR_MASK                          (0x7342FFFFU)
+
+#define BSP_FEATURE_MAILBOX_SEM_SUPPORTED                      (0U)
+
+#define BSP_FEATURE_MTU3_MAX_CHANNELS                          (9U)
+#define BSP_FEATURE_MTU3_UVW_MAX_CHANNELS                      (3U)
+#define BSP_FEATURE_MTU3_VALID_CHANNEL_MASK                    (0x01FF)
+
+#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS                (0x0U)
+#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS                (0x0U)
+
+#define BSP_FEATURE_PCIE_CHANNEL0_ERROR_AXI_NUM                (0)
+#define BSP_FEATURE_PCIE_CHANNEL0_ERROR_CORRECTABLE_RC_NUM     (0)
+#define BSP_FEATURE_PCIE_CHANNEL0_ERROR_FATAL_RC_NUM           (0)
+#define BSP_FEATURE_PCIE_CHANNEL0_ERROR_NON_FATAL_RC_NUM       (0)
+#define BSP_FEATURE_PCIE_CHANNEL0_ERROR_RC_NUM                 (0)
+#define BSP_FEATURE_PCIE_CHANNEL1_ERROR_AXI_NUM                (0)
+#define BSP_FEATURE_PCIE_CHANNEL1_ERROR_CORRECTABLE_RC_NUM     (0)
+#define BSP_FEATURE_PCIE_CHANNEL1_ERROR_FATAL_RC_NUM           (0)
+#define BSP_FEATURE_PCIE_CHANNEL1_ERROR_NON_FATAL_RC_NUM       (0)
+#define BSP_FEATURE_PCIE_CHANNEL1_ERROR_RC_NUM                 (0)
+
+#define BSP_FEATURE_POE3_ERROR_SIGNAL_TYPE                     (1U)
+#define BSP_FEATURE_POE3_PIN_SELECT_TYPE                       (1U)
+
+#define BSP_FEATURE_POEG_CHANNEL_MASK                          (0xFU)
+#define BSP_FEATURE_POEG_ERROR_SIGNAL_TYPE                     (1U)
+#define BSP_FEATURE_POEG_GROUP_OFSSET_ADDRESS                  (0x400)
+#define BSP_FEATURE_POEG_LLPP_UNIT                             (0U)
+#define BSP_FEATURE_POEG_MAX_UNIT                              (2U)
+#define BSP_FEATURE_POEG_NONSAFETY_UNIT                        (1U)
+#define BSP_FEATURE_POEG_SAFETY_UNIT                           (2U)
+
+#define BSP_FEATURE_RSIP_JTAG_DEBUG_AUTH_LEVEL1                (1U)
+#define BSP_FEATURE_RSIP_JTAG_DEBUG_AUTH_LEVEL2                (1U)
+#define BSP_FEATURE_RSIP_SCI_USB_BOOT_AUTH                     (0U)
+#define BSP_FEATURE_RSIP_OTP_ADDRESS_SPACE                     (1U)
+#define BSP_FEATURE_RSIP_OTF_CHANNEL                           (0U)
+
+#define BSP_FEATURE_RTC_MODULE_START_TYPE                      (1U)
+
+#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS                 (BSP_FEATURE_SCI_CHANNELS)
+#define BSP_FEATURE_SCI_CHANNELS                               (0x3FU)
+#define BSP_FEATURE_SCI_SAFETY_CHANNEL                         (5U)
+#define BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS            (R_SCI5_BASE)
+#define BSP_FEATURE_SCI_SPI_MAX_CPUCLK_MHZ                     (800U)
+#define BSP_FEATURE_SCI_SPI_MIN_PCLKM_MHZ                      (100U) // Minimum PCLKM greater than minimum SCInASYNCCLK
+#define BSP_FEATURE_SCI_SPI_MIN_SCINASYNCCLK_MHZ               (75U)
+#define BSP_FEATURE_SCI_UART_CTSPEN_CHANNELS                   (0x03FU)
+#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS                     (0x3FFU)
+#define BSP_FEATURE_SCI_UART_FIFO_DEPTH                        (16U)
+#define BSP_FEATURE_SCIE_SUPPORTED                             (0U)
+
+#define BSP_FEATURE_SDHI_CLOCK                                 (0xFFU) // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION                    (0)     // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_MAX_CHANNELS                          (0)     // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT              (0)     // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC                    (0)     // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK                    (0)     // Feature not available on this MCU
+
+#define BSP_FEATURE_SEM_SUPPORTED                              (0U)
+#define BSP_FEATURE_SHARED_MEMORY_SETTING_TYPE                 (1U)
+
+#define BSP_FEATURE_SPI_HAS_BYTE_SWAP                          (1U)
+#define BSP_FEATURE_SPI_HAS_SPCR3                              (0U)
+#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP                     (1U)
+#define BSP_FEATURE_SPI_MAX_CHANNEL                            (4U)
+#define BSP_FEATURE_SPI_SAFETY_CHANNEL                         (3U)
+#define BSP_FEATURE_SPI_SAFETY_CHANNEL_BASE_ADDRESS            (R_SPI3_BASE)
+
+#define BSP_FEATURE_TFU_FIXED_POINT_SUPPORTED                  (0)
+#define BSP_FEATURE_TFU_SUPPORTED                              (1U)
+#define BSP_FEATURE_TFU_UNIT                                   (1U)
+#define BSP_FEATURE_TFU_UNIT_NUMBER                            (0)
+#define BSP_FEATURE_TFU_VERSION                                (1)
+
+#define BSP_FEATURE_TSU_B_CALIBRAION_DATA_CHECK_ENABLE         (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_B_CALIBRAION_DATA_INVALID              (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_B_CALIBRAION_DATA_MASK                 (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_B_CONTINUOUS_MODE_SUPPORTED            (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_B_ELC_TRIGGER_SUPPORTED                (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_B_HIGH_TEMPERATURE                     (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_B_LOW_TEMPERATURE                      (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_B_UNIT_0_HIGH_TEMPERATURE_REGISTER     (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_B_UNIT_0_LOW_TEMPERATURE_REGISTER      (0) // Feature not available on this MCU
+#define BSP_FEATURE_TSU_VERSION                                (1U)
+
+#define BSP_FEATURE_TZC400_SUPPORTED                           (0U)
+
+#define BSP_FEATURE_USB_HOST_HS_SET_TYPE                       (1U)
+#define BSP_FEATURE_USB_HOST_INIT_TYPE                         (1U)
+#define BSP_FEATURE_USB_PERI_INIT_TYPE                         (1U)
+
+#define BSP_FEATURE_XSPI_CHANNELS                              (0x03U)
+#define BSP_FEATURE_XSPI_CS_ADDRESS_SPACE_SETTING_TYPE         (1U)
+#define BSP_FEATURE_XSPI_DEVICE_0_MIRROR_START_ADDRESS         (0x40000000U)
+#define BSP_FEATURE_XSPI_DEVICE_0_START_ADDRESS                (0x60000000U)
+#define BSP_FEATURE_XSPI_DEVICE_1_MIRROR_START_ADDRESS         (0x48000000U)
+#define BSP_FEATURE_XSPI_DEVICE_1_START_ADDRESS                (0x68000000U)
+#define BSP_FEATURE_XSPI_DEVICE_ADDRESS_SPACE_SIZE             (0x8000000U)
+#define BSP_FEATURE_XSPI_HAS_AXI_BRIDGE                        (0U)
+#define BSP_FEATURE_XSPI_NUM_CHIP_SELECT                       (2U)
+#define BSP_FEATURE_XSPI_VOLTAGE_SETTING_SUPPORTED             (0U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c
new file mode 100644
index 00000000..cfb87364
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c
@@ -0,0 +1,72 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU_RZN2L
+ * @{
+ **********************************************************************************************************************/
+
+/** Array of GICD_ICFGR initialization value. */
+const uint32_t BSP_GICD_ICFGR_INIT[BSP_NON_SELECTABLE_ICFGR_MAX] =
+{
+    0xAAAAAAAAUL,                      /* Event No. 0 to 15    */
+    0x000000AAUL,                      /* Event No. 16 to 31   */
+    0x00000000UL,                      /* Event No. 32 to 47   */
+    0xAAAAA800UL,                      /* Event No. 48 to 63   */
+    0xAAAAAAAAUL,                      /* Event No. 64 to 79   */
+    0xAAAAAAAAUL,                      /* Event No. 80 to 95   */
+    0xAAAAAAAAUL,                      /* Event No. 96 to 111  */
+    0xAAAAAA00UL,                      /* Event No. 112 to 127 */
+    0xAAAAAAAAUL,                      /* Event No. 128 to 143 */
+    0xAAAAAAAAUL,                      /* Event No. 144 to 159 */
+    0xAAAAAAAAUL,                      /* Event No. 160 to 175 */
+    0xAAAAAAAAUL,                      /* Event No. 176 to 191 */
+    0xAAAAAAAAUL,                      /* Event No. 192 to 207 */
+    0xAAAAAAAAUL,                      /* Event No. 208 to 223 */
+    0xAAAAAAAAUL,                      /* Event No. 224 to 239 */
+    0x0000000AUL,                      /* Event No. 240 to 255 */
+    0xA8000000UL,                      /* Event No. 256 to 271 */
+    0xA82A2AAAUL,                      /* Event No. 272 to 287 */
+    0x28282828UL,                      /* Event No. 288 to 303 */
+    0x00282828UL,                      /* Event No. 304 to 319 */
+    0xA82A0A00UL,                      /* Event No. 320 to 335 */
+    0xA0AA8020UL,                      /* Event No. 336 to 351 */
+    0x00000002UL,                      /* Event No. 352 to 367 */
+    0x00000000UL,                      /* Event No. 368 to 383 */
+    0xAAAA0A0AUL,                      /* Event No. 384 to 399 */
+    0xAAAAAAAAUL,                      /* Event No. 400 to 415 */
+    0x00AAAAAAUL,                      /* Event No. 416 to 431 */
+    0x828A0A2AUL,                      /* Event No. 432 to 447 */
+};
+
+const uint32_t BSP_GICR_SGI_PPI_ICFGR_INIT[BSP_EVENT_SGI_PPI_ARRAY_NUM] =
+{
+    0xAAAAAAAAUL,                      /* event SGI */
+    0x00020000UL,                      /* event PPI */
+};
+
+/** @} (end addtogroup BSP_MCU_RZN2L) */
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c
new file mode 100644
index 00000000..f42deec8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c
@@ -0,0 +1,54 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+#if !(BSP_CFG_RAM_EXECUTION) && (BSP_CFG_USE_LOADER_PARAMETER)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+ #define BSP_LOADER_PARAM_MAX    (19)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* Parameter Information for the Loader. */
+BSP_DONT_REMOVE const uint32_t g_bsp_loader_param[BSP_LOADER_PARAM_MAX] BSP_PLACE_IN_SECTION(BSP_SECTION_LOADER_PARAM) =
+{
+    BSP_CFG_CACHE_FLG,
+    BSP_CFG_CS0BCR_V_WRAPCFG_V,
+    BSP_CFG_CS0WCR_V_COMCFG_V,
+    BSP_CFG_DUMMY0_BMCFG_V,
+    BSP_CFG_BSC_FLG_xSPI_FLG,
+    BSP_CFG_LDR_ADDR_NML,
+    BSP_CFG_LDR_SIZE_NML,
+    BSP_CFG_DEST_ADDR_NML,
+    BSP_CFG_DUMMY1,
+    BSP_CFG_DUMMY2,
+    BSP_CFG_DUMMY3_CSSCTL_V,
+    BSP_CFG_DUMMY4_LIOCFGCS0_V,
+    BSP_CFG_DUMMY5,
+    BSP_CFG_DUMMY6,
+    BSP_CFG_DUMMY7,
+    BSP_CFG_DUMMY8,
+    BSP_CFG_DUMMY9,
+    BSP_CFG_DUMMY10_ACCESS_SPEED,
+    BSP_CFG_CHECK_SUM
+};
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h
new file mode 100644
index 00000000..ead934a8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h
@@ -0,0 +1,50 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @ingroup BSP_MCU
+ * @defgroup BSP_MCU_RZN2L RZN2L
+ * @includedoc config_bsp_rzn2l_fsp.html
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BSP_MCU_RZN2L) */
+
+#ifndef BSP_MCU_INFO_H
+#define BSP_MCU_INFO_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP MCU Specific Includes. */
+#include "bsp_elc.h"
+#include "bsp_feature.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef elc_event_t bsp_interrupt_event_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h
new file mode 100644
index 00000000..2a7410a9
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h
@@ -0,0 +1,1431 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU_RZN2L
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end addtogroup BSP_MCU_RZN2L) */
+
+#ifndef BSP_OVERRIDE_H
+#define BSP_OVERRIDE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP Common Includes. */
+#include "../../src/bsp/mcu/all/bsp_common.h"
+
+/* BSP MPU Specific Includes. */
+#include "../../src/bsp/mcu/all/bsp_register_protection.h"
+#include "../../src/bsp/mcu/all/bsp_irq.h"
+#include "../../src/bsp/mcu/all/bsp_io.h"
+#include "../../src/bsp/mcu/all/bsp_clocks.h"
+#include "../../src/bsp/mcu/all/bsp_module_stop.h"
+#include "../../src/bsp/mcu/all/bsp_semaphore.h"
+#include "../../src/bsp/mcu/all/bsp_reset.h"
+#include "../../src/bsp/mcu/all/bsp_cache.h"
+
+/* Factory MPU information. */
+#include "../../inc/fsp_features.h"
+
+/* BSP Common Includes (Other than bsp_common.h) */
+#include "../../src/bsp/mcu/all/bsp_delay.h"
+#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
+
+/* BSP TFU Includes. */
+#if BSP_FEATURE_TFU_SUPPORTED
+ #include "../../src/bsp/mcu/all/bsp_tfu.h"
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Define overrides required for this MPU. */
+#define BSP_OVERRIDE_ADC_CHANNEL_T
+#define BSP_OVERRIDE_CGC_CLOCK_T
+#define BSP_OVERRIDE_CGC_PLL_CFG_T
+#define BSP_OVERRIDE_CGC_DIVIDER_CFG_T
+#define BSP_OVERRIDE_CGC_CLOCK_CHANGE_T
+#define BSP_OVERRIDE_CGC_CLOCKS_CFG_T
+#define BSP_OVERRIDE_ELC_PERIPHERAL_T
+#define BSP_OVERRIDE_ERROR_EVENT_T
+#define BSP_OVERRIDE_ETHER_EVENT_T
+#define BSP_OVERRIDE_ETHER_CALLBACK_ARGS_T
+#define BSP_OVERRIDE_ETHER_PHY_LSI_TYPE_T
+#define BSP_OVERRIDE_ETHER_SWITCH_CALLBACK_ARGS_T
+#define BSP_OVERRIDE_POE3_STATE_T
+#define BSP_OVERRIDE_POEG_STATE_T
+#define BSP_OVERRIDE_POEG_TRIGGER_T
+#define BSP_OVERRIDE_TRANSFER_MODE_T
+#define BSP_OVERRIDE_TRANSFER_SIZE_T
+#define BSP_OVERRIDE_TRANSFER_ADDR_MODE_T
+#define BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T
+#define BSP_OVERRIDE_TRANSFER_INFO_T
+
+/* Override definitions. */
+
+#define ELC_PERIPHERAL_NUM     (55U)
+
+/* Private definition to set enumeration values. */
+#define IOPORT_P_OFFSET        (0U)
+#define IOPORT_PM_OFFSET       (1U)
+#define IOPORT_PMC_OFFSET      (3U)
+#define IOPORT_PFC_OFFSET      (4U)
+#define IOPORT_DRCTL_OFFSET    (8U)
+#define IOPORT_RSELP_OFFSET    (14U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*==============================================
+ * ADC API Overrides
+ *==============================================*/
+
+/** ADC channels */
+typedef enum e_adc_channel
+{
+    ADC_CHANNEL_0                 = 0,     ///< ADC channel 0
+    ADC_CHANNEL_1                 = 1,     ///< ADC channel 1
+    ADC_CHANNEL_2                 = 2,     ///< ADC channel 2
+    ADC_CHANNEL_3                 = 3,     ///< ADC channel 3
+    ADC_CHANNEL_4                 = 4,     ///< ADC channel 4
+    ADC_CHANNEL_5                 = 5,     ///< ADC channel 5
+    ADC_CHANNEL_6                 = 6,     ///< ADC channel 6
+    ADC_CHANNEL_7                 = 7,     ///< ADC channel 7
+    ADC_CHANNEL_8                 = 8,     ///< ADC channel 8
+    ADC_CHANNEL_9                 = 9,     ///< ADC channel 9
+    ADC_CHANNEL_10                = 10,    ///< ADC channel 10
+    ADC_CHANNEL_11                = 11,    ///< ADC channel 11
+    ADC_CHANNEL_12                = 12,    ///< ADC channel 12
+    ADC_CHANNEL_13                = 13,    ///< ADC channel 13
+    ADC_CHANNEL_14                = 14,    ///< ADC channel 14
+    ADC_CHANNEL_15                = 15,    ///< ADC channel 15
+    ADC_CHANNEL_16                = 16,    ///< ADC channel 16
+    ADC_CHANNEL_17                = 17,    ///< ADC channel 17
+    ADC_CHANNEL_18                = 18,    ///< ADC channel 18
+    ADC_CHANNEL_19                = 19,    ///< ADC channel 19
+    ADC_CHANNEL_20                = 20,    ///< ADC channel 20
+    ADC_CHANNEL_21                = 21,    ///< ADC channel 21
+    ADC_CHANNEL_22                = 22,    ///< ADC channel 22
+    ADC_CHANNEL_23                = 23,    ///< ADC channel 23
+    ADC_CHANNEL_24                = 24,    ///< ADC channel 24
+    ADC_CHANNEL_25                = 25,    ///< ADC channel 25
+    ADC_CHANNEL_26                = 26,    ///< ADC channel 26
+    ADC_CHANNEL_27                = 27,    ///< ADC channel 27
+    ADC_CHANNEL_DUPLEX_A          = 50,    ///< Data duplexing register A
+    ADC_CHANNEL_DUPLEX_B          = 51,    ///< Data duplexing register B
+    ADC_CHANNEL_DUPLEX            = -4,    ///< Data duplexing register
+    ADC_CHANNEL_TEMPERATURE       = -3,    ///< Temperature sensor output
+    ADC_CHANNEL_VOLT              = -2,    ///< Internal reference voltage
+    ADC_CHANNEL_0_DSMIF_CAPTURE_A = 0x100, ///< ADC channel 0 Capture Current Data Register A
+    ADC_CHANNEL_0_DSMIF_CAPTURE_B = 0x200, ///< ADC channel 0 Capture Current Data Register B
+    ADC_CHANNEL_1_DSMIF_CAPTURE_A = 0x101, ///< ADC channel 1 Capture Current Data Register A
+    ADC_CHANNEL_1_DSMIF_CAPTURE_B = 0x201, ///< ADC channel 1 Capture Current Data Register B
+    ADC_CHANNEL_2_DSMIF_CAPTURE_A = 0x102, ///< ADC channel 2 Capture Current Data Register A
+    ADC_CHANNEL_2_DSMIF_CAPTURE_B = 0x202, ///< ADC channel 2 Capture Current Data Register B
+} adc_channel_t;
+
+/*==============================================
+ * CGC API Overrides
+ *==============================================*/
+
+/** Divider values of clock provided to xSPI */
+typedef enum e_cgc_fsel_xspi_clock_div
+{
+    CGC_FSEL_XSPI_CLOCK_DIV_6  = 0x02, ///< XSPI_CLKn 133.3MHz (XSPI base clock divided by 3)
+    CGC_FSEL_XSPI_CLOCK_DIV_8  = 0x03, ///< XSPI_CLKn 100.0MHz / 75.0MHz (XSPI base clock divided by 3 / divided by 4)
+    CGC_FSEL_XSPI_CLOCK_DIV_16 = 0x04, ///< XSPI_CLKn 50.0MHz / 37.5MHz (XSPI base clock divided by 3 / divided by 4)
+    CGC_FSEL_XSPI_CLOCK_DIV_32 = 0x05, ///< XSPI_CLKn 25.0MHz (XSPI base clock divided by 3)
+    CGC_FSEL_XSPI_CLOCK_DIV_64 = 0x06, ///< XSPI_CLKn 12.5MHz (XSPI base clock divided by 3)
+} cgc_fsel_xspi_clock_div_t;
+
+/** Divider values of base clock generated for xSPI */
+typedef enum e_cgc_divsel_xspi_clock_div
+{
+    CGC_DIVSEL_XSPI_CLOCK_DIV_3 = 0x00, ///< XSPI base clock divided by 3
+    CGC_DIVSEL_XSPI_CLOCK_DIV_4 = 0x01, ///< XSPI base clock divided by 4
+} cgc_divsel_xspi_clock_div_t;
+
+/** Clock output divider values */
+typedef enum e_cgc_clock_out_clock_div
+{
+    CGC_CLOCK_OUT_CLOCK_DIV_2 = 0,     ///< CKIO 100.0MHz / 75.0MHz (Base clock divided by 3 / divided by 4)
+    CGC_CLOCK_OUT_CLOCK_DIV_3 = 1,     ///< CKIO 66.7MHz / 50.0MHz (Base clock divided by 3 / divided by 4)
+    CGC_CLOCK_OUT_CLOCK_DIV_4 = 2,     ///< CKIO 50.0MHz / 37.5MHz (Base clock divided by 3 / divided by 4)
+    CGC_CLOCK_OUT_CLOCK_DIV_5 = 3,     ///< CKIO 40.0MHz / 30.0MHz (Base clock divided by 3 / divided by 4)
+    CGC_CLOCK_OUT_CLOCK_DIV_6 = 4,     ///< CKIO 33.3MHz / 25.0MHz (Base clock divided by 3 / divided by 4)
+    CGC_CLOCK_OUT_CLOCK_DIV_7 = 5,     ///< CKIO 28.6MHz / 21.4MHz (Base clock divided by 3 / divided by 4)
+    CGC_CLOCK_OUT_CLOCK_DIV_8 = 6,     ///< CKIO 25.0MHz / 18.75MHz (Base clock divided by 3 / divided by 4)
+} cgc_clock_out_clock_div_t;
+
+/** CANFD clock divider values */
+typedef enum e_cgc_canfd_clock_div
+{
+    CGC_CANFD_CLOCK_DIV_10 = 0,        ///< CANFD clock 80.0MHz
+    CGC_CANFD_CLOCK_DIV_20 = 1,        ///< CANFD clock 40.0MHz
+} cgc_canfd_clock_div_t;
+
+/** PHY clock source identifiers */
+typedef enum e_cgc_phy_clock
+{
+    CGC_PHY_CLOCK_PLL1     = 0,        ///< PLL1 divider clock
+    CGC_PHY_CLOCK_MAIN_OSC = 1,        ///< Main clock oscillator
+} cgc_phy_clock_t;
+
+/** SPI asynchronous serial clock frequency */
+typedef enum e_cgc_spi_async_clock
+{
+    CGC_SPI_ASYNC_CLOCK_75MHZ = 0,     ///< SPI asynchronous serial clock 75MHz
+    CGC_SPI_ASYNC_CLOCK_96MHZ = 1,     ///< SPI asynchronous serial clock 96MHz
+} cgc_spi_async_clock_t;
+
+/** SCI asynchronous serial clock frequency */
+typedef enum e_cgc_sci_async_clock
+{
+    CGC_SCI_ASYNC_CLOCK_75MHZ = 0,     ///< SCI asynchronous serial clock 75MHz
+    CGC_SCI_ASYNC_CLOCK_96MHZ = 1,     ///< SCI asynchronous serial clock 96MHz
+} cgc_sci_async_clock_t;
+
+/** CPU clock divider values */
+typedef enum e_cgc_cpu_clock_div
+{
+    CGC_CPU_CLOCK_DIV_2 = 0,           ///< CPU 200.0MHz / 150.0MHz (Base clock divided by 3 / divided by 4)
+    CGC_CPU_CLOCK_DIV_1 = 1,           ///< CPU 400.0MHz / 300.0MHz (Base clock divided by 3 / divided by 4)
+} cgc_cpu_clock_div_t;
+
+/** Base clock divider values */
+typedef enum e_cgc_baseclock_div
+{
+    CGC_BASECLOCK_DIV_3 = 0,           ///< Base clock divided by 3 (ICLK=200.0MHz etc.)
+    CGC_BASECLOCK_DIV_4 = 1,           ///< Base clock divided by 4 (ICLK=150.0MHz etc.)
+} cgc_baseclock_div_t;
+
+/** System clock source identifiers */
+typedef enum e_cgc_clock
+{
+    CGC_CLOCK_LOCO = 0,                ///< The low speed on chip oscillator
+    CGC_CLOCK_PLL0 = 1,                ///< The PLL0 oscillator
+    CGC_CLOCK_PLL1 = 2,                ///< The PLL1 oscillator
+} cgc_clock_t;
+
+/** Clock configuration structure - Dummy definition because it is not used in this MPU.
+ * Set NULL as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */
+typedef struct st_cgc_pll_cfg
+{
+    uint32_t dummy;                    /* Dummy. */
+} cgc_pll_cfg_t;
+
+/** Clock configuration structure */
+typedef struct st_cgc_divider_cfg
+{
+    union
+    {
+        uint32_t sckcr_w;                                ///< System Clock Control Register
+
+        struct
+        {
+            cgc_fsel_xspi_clock_div_t fselxspi0     : 3; ///< Divider value for XSPI_CLK0
+            uint32_t                                : 3;
+            cgc_divsel_xspi_clock_div_t divselxspi0 : 1; ///< Divider base value for XSPI_CLK0
+            uint32_t                                : 1;
+            cgc_fsel_xspi_clock_div_t fselxspi1     : 3; ///< Divider value for XSPI_CLK1
+            uint32_t                                : 3;
+            cgc_divsel_xspi_clock_div_t divselxspi1 : 1; ///< Divider base value for XSPI_CLK1
+            uint32_t                                : 1;
+            cgc_clock_out_clock_div_t ckio_div      : 3; ///< Divider value for CKIO
+            uint32_t                                : 1;
+            cgc_canfd_clock_div_t fselcanfd_div     : 1; ///< Divider value for CANFD clock
+            cgc_phy_clock_t       phy_sel           : 1; ///< Ethernet PHY reference clock output
+            uint32_t                                : 2;
+            cgc_spi_async_clock_t spi0_async_sel    : 1; ///< SPI0 asynchronous serial clock
+            cgc_spi_async_clock_t spi1_async_sel    : 1; ///< SPI1 asynchronous serial clock
+            cgc_spi_async_clock_t spi2_async_sel    : 1; ///< SPI2 asynchronous serial clock
+            cgc_sci_async_clock_t sci0_async_sel    : 1; ///< SCI0 asynchronous serial clock
+            cgc_sci_async_clock_t sci1_async_sel    : 1; ///< SCI1 asynchronous serial clock
+            cgc_sci_async_clock_t sci2_async_sel    : 1; ///< SCI2 asynchronous serial clock
+            cgc_sci_async_clock_t sci3_async_sel    : 1; ///< SCI3 asynchronous serial clock
+            cgc_sci_async_clock_t sci4_async_sel    : 1; ///< SCI4 asynchronous serial clock
+        } sckcr_b;
+    };
+
+    union
+    {
+        uint32_t sckcr2_w;                            ///< System Clock Control Register 2
+
+        struct
+        {
+            cgc_cpu_clock_div_t fsel0cr52        : 1; ///< Divider value for Cortex-R52 CPU0
+            uint32_t                             : 4;
+            cgc_baseclock_div_t div_sub_sel      : 1; ///< Divider value for base clock
+            uint32_t                             : 18;
+            cgc_spi_async_clock_t spi3_async_sel : 1; ///< SPI3 asynchronous serial clock
+            cgc_sci_async_clock_t sci5_async_sel : 1; ///< SCI5 asynchronous serial clock
+            uint32_t                             : 6;
+        } sckcr2_b;
+    };
+} cgc_divider_cfg_t;
+
+/** Clock options */
+typedef enum e_cgc_clock_change
+{
+    CGC_CLOCK_CHANGE_START = 0,        ///< Start the clock
+    CGC_CLOCK_CHANGE_STOP  = 1,        ///< Stop the clock
+    CGC_CLOCK_CHANGE_NONE  = 2,        ///< No change to the clock
+} cgc_clock_change_t;
+
+/** Clock configuration */
+typedef struct st_cgc_clocks_cfg
+{
+    cgc_divider_cfg_t  divider_cfg;    ///< Clock dividers structure
+    cgc_clock_change_t loco_state;     ///< State of LOCO
+    cgc_clock_change_t pll1_state;     ///< State of PLL1
+} cgc_clocks_cfg_t;
+
+/*==============================================
+ * ELC API Overrides
+ *==============================================*/
+
+/** Possible peripherals to be linked to event signals (not all available on all MPUs) */
+typedef enum e_elc_peripheral
+{
+    ELC_PERIPHERAL_MTU0          = (0),
+    ELC_PERIPHERAL_MTU3          = (1),
+    ELC_PERIPHERAL_MTU4          = (2),
+    ELC_PERIPHERAL_LLPPGPT_A     = (3),
+    ELC_PERIPHERAL_LLPPGPT_B     = (4),
+    ELC_PERIPHERAL_LLPPGPT_C     = (5),
+    ELC_PERIPHERAL_LLPPGPT_D     = (6),
+    ELC_PERIPHERAL_LLPPGPT_E     = (7),
+    ELC_PERIPHERAL_LLPPGPT_F     = (8),
+    ELC_PERIPHERAL_LLPPGPT_G     = (9),
+    ELC_PERIPHERAL_LLPPGPT_H     = (10),
+    ELC_PERIPHERAL_NONSAFTYGPT_A = (11),
+    ELC_PERIPHERAL_NONSAFTYGPT_B = (12),
+    ELC_PERIPHERAL_NONSAFTYGPT_C = (13),
+    ELC_PERIPHERAL_NONSAFTYGPT_D = (14),
+    ELC_PERIPHERAL_NONSAFTYGPT_E = (15),
+    ELC_PERIPHERAL_NONSAFTYGPT_F = (16),
+    ELC_PERIPHERAL_NONSAFTYGPT_G = (17),
+    ELC_PERIPHERAL_NONSAFTYGPT_H = (18),
+    ELC_PERIPHERAL_ADC0_A        = (19),
+    ELC_PERIPHERAL_ADC0_B        = (20),
+    ELC_PERIPHERAL_ADC1_A        = (21),
+    ELC_PERIPHERAL_ADC1_B        = (22),
+    ELC_PERIPHERAL_DSMIF0_CAP0   = (23),
+    ELC_PERIPHERAL_DSMIF0_CAP1   = (24),
+    ELC_PERIPHERAL_DSMIF0_CAP2   = (25),
+    ELC_PERIPHERAL_DSMIF0_CAP3   = (26),
+    ELC_PERIPHERAL_DSMIF0_CAP4   = (27),
+    ELC_PERIPHERAL_DSMIF0_CAP5   = (28),
+    ELC_PERIPHERAL_DSMIF0_CDCNT0 = (29),
+    ELC_PERIPHERAL_DSMIF0_CDCNT1 = (30),
+    ELC_PERIPHERAL_DSMIF0_CDCNT2 = (31),
+    ELC_PERIPHERAL_DSMIF1_CAP0   = (32),
+    ELC_PERIPHERAL_DSMIF1_CAP1   = (33),
+    ELC_PERIPHERAL_DSMIF1_CAP2   = (34),
+    ELC_PERIPHERAL_DSMIF1_CAP3   = (35),
+    ELC_PERIPHERAL_DSMIF1_CAP4   = (36),
+    ELC_PERIPHERAL_DSMIF1_CAP5   = (37),
+    ELC_PERIPHERAL_DSMIF1_CDCNT0 = (38),
+    ELC_PERIPHERAL_DSMIF1_CDCNT1 = (39),
+    ELC_PERIPHERAL_DSMIF1_CDCNT2 = (40),
+    ELC_PERIPHERAL_ESC0          = (43),
+    ELC_PERIPHERAL_ESC1          = (44),
+    ELC_PERIPHERAL_GMA0          = (45),
+    ELC_PERIPHERAL_GMA1          = (46),
+    ELC_PERIPHERAL_OUTPORTGR1    = (47),
+    ELC_PERIPHERAL_OUTPORTGR2    = (48),
+    ELC_PERIPHERAL_INPORTGR1     = (49),
+    ELC_PERIPHERAL_INPORTGR2     = (50),
+    ELC_PERIPHERAL_SINGLEPORT0   = (51),
+    ELC_PERIPHERAL_SINGLEPORT1   = (52),
+    ELC_PERIPHERAL_SINGLEPORT2   = (53),
+    ELC_PERIPHERAL_SINGLEPORT3   = (54),
+} elc_peripheral_t;
+
+/*==============================================
+ * ERROR API Overrides
+ *==============================================*/
+
+/** Error event source. */
+typedef enum e_error_event
+{
+    ERROR_EVENT_CPU0,                  ///< Error event from CPU0
+    ERROR_EVENT_PERIPHERAL_0,          ///< Error event from Peripheral 0
+    ERROR_EVENT_PERIPHERAL_1,          ///< Error event from Peripheral 1
+} error_event_t;
+
+/*==============================================
+ * ETHER API Overrides
+ *==============================================*/
+
+/** Event code of callback function */
+typedef enum e_ether_event
+{
+    ETHER_EVENT_WAKEON_LAN,            ///< Magic packet detection event
+    ETHER_EVENT_LINK_ON,               ///< Link up detection event
+    ETHER_EVENT_LINK_OFF,              ///< Link down detection event
+    ETHER_EVENT_SBD_INTERRUPT,         ///< SBD Interrupt event
+    ETHER_EVENT_PMT_INTERRUPT          ///< PMT Interrupt event
+} ether_event_t;
+
+/** Ether Callback function parameter data */
+typedef struct st_ether_callback_args
+{
+    uint32_t      channel;             ///< Device channel number
+    ether_event_t event;               ///< Event code
+
+    uint32_t status_ether;             ///< Interrupt status of SDB or PMT
+    uint32_t status_link;              ///< Link status
+
+    void const * p_context;            ///< Placeholder for user data.
+} ether_callback_args_t;
+
+/*==============================================
+ * ETHER PHY API Overrides
+ *==============================================*/
+
+/** Phy LSI */
+typedef enum e_ether_phy_lsi_type
+{
+    ETHER_PHY_LSI_TYPE_DEFAULT = 0,     ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option.
+    ETHER_PHY_LSI_TYPE_VSC8541 = 1,     ///< Select configuration forVSC8541
+    ETHER_PHY_LSI_TYPE_KSZ9131 = 2,     ///< Select configuration forKSZ9131
+    ETHER_PHY_LSI_TYPE_KSZ9031 = 3,     ///< Select configuration forKSZ9031
+    ETHER_PHY_LSI_TYPE_KSZ8081 = 4,     ///< Select configuration forKSZ8081
+    ETHER_PHY_LSI_TYPE_KSZ8041 = 5,     ///< Select configuration forKSZ8041
+    ETHER_PHY_LSI_TYPE_CUSTOM  = 0xFFU, ///< Select configuration for User custom.
+} ether_phy_lsi_type_t;
+
+/*==============================================
+ * ETHER SWITCH API Overrides
+ *==============================================*/
+
+/** Ether Switch Event code of callback function */
+typedef enum e_ether_switch_event
+{
+    ETHER_SWITCH_EVENT_LINK_CHANGE     ///< Change Link status
+} ether_switch_event_t;
+
+/** Ether Switch Callback function parameter data */
+typedef struct st_ether_switch_callback_args
+{
+    uint32_t             channel;      ///< Device channel number
+    ether_switch_event_t event;        ///< Event code
+
+    uint32_t status_link;              ///< Link status bit0:port0. bit1:port1. bit2:port2, bit3:port3
+
+    void const * p_context;            ///< Placeholder for user data.
+} ether_switch_callback_args_t;
+
+/*==============================================
+ * IOPORT API Overrides
+ *==============================================*/
+
+/** Superset of all peripheral functions.  */
+typedef enum e_ioport_pin_pfc
+{
+    IOPORT_PIN_P000_PFC_00_ETH2_RXD3       = (0x00U << IOPORT_PFC_OFFSET), ///< P00_0 / ETHER_ETHn / ETH2_RXD3
+    IOPORT_PIN_P000_PFC_02_D15             = (0x02U << IOPORT_PFC_OFFSET), ///< P00_0 / BSC / D15
+    IOPORT_PIN_P000_PFC_03_SCK2            = (0x03U << IOPORT_PFC_OFFSET), ///< P00_0 / SCIn / SCK2
+    IOPORT_PIN_P000_PFC_04_DE2             = (0x04U << IOPORT_PFC_OFFSET), ///< P00_0 / SCIn / DE2
+    IOPORT_PIN_P000_PFC_05_HD15            = (0x05U << IOPORT_PFC_OFFSET), ///< P00_0 / PHOSTIF / HD15
+    IOPORT_PIN_P001_PFC_00_IRQ0            = (0x00U << IOPORT_PFC_OFFSET), ///< P00_1 / IRQ / IRQ0
+    IOPORT_PIN_P001_PFC_01_ETH2_RXDV       = (0x01U << IOPORT_PFC_OFFSET), ///< P00_1 / ETHER_ETHn / ETH2_RXDV
+    IOPORT_PIN_P001_PFC_03_A13             = (0x03U << IOPORT_PFC_OFFSET), ///< P00_1 / BSC / A13
+    IOPORT_PIN_P001_PFC_04_MTIC5U          = (0x04U << IOPORT_PFC_OFFSET), ///< P00_1 / MTU3n / MTIC5U
+    IOPORT_PIN_P001_PFC_05_RXD2_SCL2_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P00_1 / SCIn / RXD2_SCL2_MISO2
+    IOPORT_PIN_P002_PFC_00_ETH2_TXEN       = (0x00U << IOPORT_PFC_OFFSET), ///< P00_2 / ETHER_ETHn / ETH2_TXEN
+    IOPORT_PIN_P002_PFC_02_RD              = (0x02U << IOPORT_PFC_OFFSET), ///< P00_2 / BSC / RD
+    IOPORT_PIN_P002_PFC_03_MTIC5V          = (0x03U << IOPORT_PFC_OFFSET), ///< P00_2 / MTU3n / MTIC5V
+    IOPORT_PIN_P002_PFC_04_TXD2_SDA2_MOSI2 = (0x04U << IOPORT_PFC_OFFSET), ///< P00_2 / SCIn / TXD2_SDA2_MOSI2
+    IOPORT_PIN_P002_PFC_05_USB_OVRCUR      = (0x05U << IOPORT_PFC_OFFSET), ///< P00_2 / USB_HS / USB_OVRCUR
+    IOPORT_PIN_P003_PFC_00_IRQ1            = (0x00U << IOPORT_PFC_OFFSET), ///< P00_3 / IRQ / IRQ1
+    IOPORT_PIN_P003_PFC_01_ETH2_REFCLK     = (0x01U << IOPORT_PFC_OFFSET), ///< P00_3 / ETHER_ETHn / ETH2_REFCLK
+    IOPORT_PIN_P003_PFC_02_RMII2_REFCLK    = (0x02U << IOPORT_PFC_OFFSET), ///< P00_3 / ETHER_ETHn / RMII2_REFCLK
+    IOPORT_PIN_P003_PFC_04_RD_WR           = (0x04U << IOPORT_PFC_OFFSET), ///< P00_3 / BSC / RD_WR
+    IOPORT_PIN_P003_PFC_05_MTIC5W          = (0x05U << IOPORT_PFC_OFFSET), ///< P00_3 / MTU3n / MTIC5W
+    IOPORT_PIN_P003_PFC_06_SS2_CTS2_RTS2   = (0x06U << IOPORT_PFC_OFFSET), ///< P00_3 / SCIn / SS2_CTS2_RTS2
+    IOPORT_PIN_P004_PFC_00_IRQ13           = (0x00U << IOPORT_PFC_OFFSET), ///< P00_4 / IRQ / IRQ13
+    IOPORT_PIN_P004_PFC_01_ETH2_RXER       = (0x01U << IOPORT_PFC_OFFSET), ///< P00_4 / ETHER_ETHn / ETH2_RXER
+    IOPORT_PIN_P004_PFC_03_WAIT            = (0x03U << IOPORT_PFC_OFFSET), ///< P00_4 / BSC / WAIT
+    IOPORT_PIN_P004_PFC_04_MTIOC3A         = (0x04U << IOPORT_PFC_OFFSET), ///< P00_4 / MTU3n / MTIOC3A
+    IOPORT_PIN_P004_PFC_05_GTIOC0A         = (0x05U << IOPORT_PFC_OFFSET), ///< P00_4 / GPTn / GTIOC0A
+    IOPORT_PIN_P004_PFC_06_MCLK0           = (0x06U << IOPORT_PFC_OFFSET), ///< P00_4 / DSMIFn / MCLK0
+    IOPORT_PIN_P004_PFC_07_HWAIT           = (0x07U << IOPORT_PFC_OFFSET), ///< P00_4 / PHOSTIF / HWAIT
+    IOPORT_PIN_P005_PFC_00_ETHSW_PHYLINK2  = (0x00U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ETHSW / ETHSW_PHYLINK2
+    IOPORT_PIN_P005_PFC_02_CS0             = (0x02U << IOPORT_PFC_OFFSET), ///< P00_5 / BSC / CS0
+    IOPORT_PIN_P005_PFC_03_ESC_PHYLINK2    = (0x03U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ESC / ESC_PHYLINK2
+    IOPORT_PIN_P005_PFC_04_MTIOC3C         = (0x04U << IOPORT_PFC_OFFSET), ///< P00_5 / MTU3n / MTIOC3C
+    IOPORT_PIN_P005_PFC_05_GTIOC0B         = (0x05U << IOPORT_PFC_OFFSET), ///< P00_5 / GPTn / GTIOC0B
+    IOPORT_PIN_P005_PFC_06_MDAT0           = (0x06U << IOPORT_PFC_OFFSET), ///< P00_5 / DSMIFn / MDAT0
+    IOPORT_PIN_P005_PFC_07_ETHSW_PHYLINK0  = (0x07U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ETHSW / ETHSW_PHYLINK0
+    IOPORT_PIN_P005_PFC_08_ESC_PHYLINK0    = (0x08U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ESC / ESC_PHYLINK0
+    IOPORT_PIN_P006_PFC_00_ETH2_TXCLK      = (0x00U << IOPORT_PFC_OFFSET), ///< P00_6 / ETHER_ETHn / ETH2_TXCLK
+    IOPORT_PIN_P006_PFC_01_CS5             = (0x01U << IOPORT_PFC_OFFSET), ///< P00_6 / BSC / CS5
+    IOPORT_PIN_P006_PFC_02_MTIOC3B         = (0x02U << IOPORT_PFC_OFFSET), ///< P00_6 / MTU3n / MTIOC3B
+    IOPORT_PIN_P006_PFC_03_GTIOC1A         = (0x03U << IOPORT_PFC_OFFSET), ///< P00_6 / GPTn / GTIOC1A
+    IOPORT_PIN_P007_PFC_00_IRQ13           = (0x00U << IOPORT_PFC_OFFSET), ///< P00_7 / IRQ / IRQ13
+    IOPORT_PIN_P007_PFC_01_RAS             = (0x01U << IOPORT_PFC_OFFSET), ///< P00_7 / BSC / RAS
+    IOPORT_PIN_P007_PFC_02_MTIOC4A         = (0x02U << IOPORT_PFC_OFFSET), ///< P00_7 / MTU3n / MTIOC4A
+    IOPORT_PIN_P007_PFC_03_GTIOC2A         = (0x03U << IOPORT_PFC_OFFSET), ///< P00_7 / GPTn / GTIOC2A
+    IOPORT_PIN_P010_PFC_00_GMAC_MDIO       = (0x00U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_GMAC / GMAC_MDIO
+    IOPORT_PIN_P010_PFC_01_ETHSW_MDIO      = (0x01U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_ETHSW / ETHSW_MDIO
+    IOPORT_PIN_P010_PFC_02_CAS             = (0x02U << IOPORT_PFC_OFFSET), ///< P01_0 / BSC / CAS
+    IOPORT_PIN_P010_PFC_03_ESC_MDIO        = (0x03U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_ESC / ESC_MDIO
+    IOPORT_PIN_P010_PFC_04_MTIOC4C         = (0x04U << IOPORT_PFC_OFFSET), ///< P01_0 / MTU3n / MTIOC4C
+    IOPORT_PIN_P010_PFC_05_GTIOC3A         = (0x05U << IOPORT_PFC_OFFSET), ///< P01_0 / GPTn / GTIOC3A
+    IOPORT_PIN_P010_PFC_06_CTS2            = (0x06U << IOPORT_PFC_OFFSET), ///< P01_0 / SCIn / CTS2
+    IOPORT_PIN_P010_PFC_07_MCLK1           = (0x07U << IOPORT_PFC_OFFSET), ///< P01_0 / DSMIFn / MCLK1
+    IOPORT_PIN_P011_PFC_00_GMAC_MDC        = (0x00U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_GMAC / GMAC_MDC
+    IOPORT_PIN_P011_PFC_01_ETHSW_MDC       = (0x01U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_ETHSW / ETHSW_MDC
+    IOPORT_PIN_P011_PFC_02_CKE             = (0x02U << IOPORT_PFC_OFFSET), ///< P01_1 / BSC / CKE
+    IOPORT_PIN_P011_PFC_03_ESC_MDC         = (0x03U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_ESC / ESC_MDC
+    IOPORT_PIN_P011_PFC_04_MTIOC3D         = (0x04U << IOPORT_PFC_OFFSET), ///< P01_1 / MTU3n / MTIOC3D
+    IOPORT_PIN_P011_PFC_05_GTIOC1B         = (0x05U << IOPORT_PFC_OFFSET), ///< P01_1 / GPTn / GTIOC1B
+    IOPORT_PIN_P011_PFC_06_DE2             = (0x06U << IOPORT_PFC_OFFSET), ///< P01_1 / SCIn / DE2
+    IOPORT_PIN_P011_PFC_07_MDAT1           = (0x07U << IOPORT_PFC_OFFSET), ///< P01_1 / DSMIFn / MDAT1
+    IOPORT_PIN_P012_PFC_00_IRQ2            = (0x00U << IOPORT_PFC_OFFSET), ///< P01_2 / IRQ / IRQ2
+    IOPORT_PIN_P012_PFC_01_ETH2_TXD3       = (0x01U << IOPORT_PFC_OFFSET), ///< P01_2 / ETHER_ETHn / ETH2_TXD3
+    IOPORT_PIN_P012_PFC_02_CS2             = (0x02U << IOPORT_PFC_OFFSET), ///< P01_2 / BSC / CS2
+    IOPORT_PIN_P012_PFC_03_MTIOC4B         = (0x03U << IOPORT_PFC_OFFSET), ///< P01_2 / MTU3n / MTIOC4B
+    IOPORT_PIN_P012_PFC_04_GTIOC2B         = (0x04U << IOPORT_PFC_OFFSET), ///< P01_2 / GPTn / GTIOC2B
+    IOPORT_PIN_P013_PFC_00_ETH2_TXD2       = (0x00U << IOPORT_PFC_OFFSET), ///< P01_3 / ETHER_ETHn / ETH2_TXD2
+    IOPORT_PIN_P013_PFC_01_AH              = (0x01U << IOPORT_PFC_OFFSET), ///< P01_3 / BSC / AH
+    IOPORT_PIN_P013_PFC_02_MTIOC4D         = (0x02U << IOPORT_PFC_OFFSET), ///< P01_3 / MTU3n / MTIOC4D
+    IOPORT_PIN_P013_PFC_03_GTIOC3B         = (0x03U << IOPORT_PFC_OFFSET), ///< P01_3 / GPTn / GTIOC3B
+    IOPORT_PIN_P014_PFC_00_IRQ3            = (0x00U << IOPORT_PFC_OFFSET), ///< P01_4 / IRQ / IRQ3
+    IOPORT_PIN_P014_PFC_01_ETH2_TXD1       = (0x01U << IOPORT_PFC_OFFSET), ///< P01_4 / ETHER_ETHn / ETH2_TXD1
+    IOPORT_PIN_P014_PFC_02_WE1_DQMLU       = (0x02U << IOPORT_PFC_OFFSET), ///< P01_4 / BSC / WE1_DQMLU
+    IOPORT_PIN_P014_PFC_03_POE0            = (0x03U << IOPORT_PFC_OFFSET), ///< P01_4 / MTU_POE3 / POE0
+    IOPORT_PIN_P015_PFC_00_ETH2_TXD0       = (0x00U << IOPORT_PFC_OFFSET), ///< P01_5 / ETHER_ETHn / ETH2_TXD0
+    IOPORT_PIN_P015_PFC_01_WE0_DQMLL       = (0x01U << IOPORT_PFC_OFFSET), ///< P01_5 / BSC / WE0_DQMLL
+    IOPORT_PIN_P016_PFC_00_GMAC_PTPTRG1    = (0x00U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_GMAC / GMAC_PTPTRG1
+    IOPORT_PIN_P016_PFC_01_TRACEDATA0      = (0x01U << IOPORT_PFC_OFFSET), ///< P01_6 / TRACE / TRACEDATA0
+    IOPORT_PIN_P016_PFC_02_A20             = (0x02U << IOPORT_PFC_OFFSET), ///< P01_6 / BSC / A20
+    IOPORT_PIN_P016_PFC_03_ESC_LATCH1      = (0x03U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_ESC / ESC_LATCH1
+    IOPORT_PIN_P016_PFC_04_ESC_LATCH0      = (0x04U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_ESC / ESC_LATCH0
+    IOPORT_PIN_P016_PFC_05_MTIOC1A         = (0x05U << IOPORT_PFC_OFFSET), ///< P01_6 / MTU3n / MTIOC1A
+    IOPORT_PIN_P016_PFC_06_GTIOC9A         = (0x06U << IOPORT_PFC_OFFSET), ///< P01_6 / GPTn / GTIOC9A
+    IOPORT_PIN_P016_PFC_07_CTS1            = (0x07U << IOPORT_PFC_OFFSET), ///< P01_6 / SCIn / CTS1
+    IOPORT_PIN_P016_PFC_08_CANTXDP1        = (0x08U << IOPORT_PFC_OFFSET), ///< P01_6 / CANFDn / CANTXDP1
+    IOPORT_PIN_P016_PFC_0A_HA20            = (0x0AU << IOPORT_PFC_OFFSET), ///< P01_6 / PHOSTIF / HA20
+    IOPORT_PIN_P017_PFC_00_ETHSW_LPI1      = (0x00U << IOPORT_PFC_OFFSET), ///< P01_7 / ETHER_ETHSW / ETHSW_LPI1
+    IOPORT_PIN_P017_PFC_01_TRACEDATA1      = (0x01U << IOPORT_PFC_OFFSET), ///< P01_7 / TRACE / TRACEDATA1
+    IOPORT_PIN_P017_PFC_02_A19             = (0x02U << IOPORT_PFC_OFFSET), ///< P01_7 / BSC / A19
+    IOPORT_PIN_P017_PFC_03_MTIOC1B         = (0x03U << IOPORT_PFC_OFFSET), ///< P01_7 / MTU3n / MTIOC1B
+    IOPORT_PIN_P017_PFC_04_GTIOC9B         = (0x04U << IOPORT_PFC_OFFSET), ///< P01_7 / GPTn / GTIOC9B
+    IOPORT_PIN_P017_PFC_05_ADTRG0          = (0x05U << IOPORT_PFC_OFFSET), ///< P01_7 / ADCn / ADTRG0
+    IOPORT_PIN_P017_PFC_06_SCK1            = (0x06U << IOPORT_PFC_OFFSET), ///< P01_7 / SCIn / SCK1
+    IOPORT_PIN_P017_PFC_07_SPI_RSPCK3      = (0x07U << IOPORT_PFC_OFFSET), ///< P01_7 / SPIn / SPI_RSPCK3
+    IOPORT_PIN_P017_PFC_08_CANRX0          = (0x08U << IOPORT_PFC_OFFSET), ///< P01_7 / CANFDn / CANRX0
+    IOPORT_PIN_P017_PFC_0A_HA19            = (0x0AU << IOPORT_PFC_OFFSET), ///< P01_7 / PHOSTIF / HA19
+    IOPORT_PIN_P020_PFC_00_IRQ4            = (0x00U << IOPORT_PFC_OFFSET), ///< P02_0 / IRQ / IRQ4
+    IOPORT_PIN_P020_PFC_01_ETHSW_LPI2      = (0x01U << IOPORT_PFC_OFFSET), ///< P02_0 / ETHER_ETHSW / ETHSW_LPI2
+    IOPORT_PIN_P020_PFC_02_TRACEDATA2      = (0x02U << IOPORT_PFC_OFFSET), ///< P02_0 / TRACE / TRACEDATA2
+    IOPORT_PIN_P020_PFC_03_A18             = (0x03U << IOPORT_PFC_OFFSET), ///< P02_0 / BSC / A18
+    IOPORT_PIN_P020_PFC_04_GTADSML0        = (0x04U << IOPORT_PFC_OFFSET), ///< P02_0 / GPT / GTADSML0
+    IOPORT_PIN_P020_PFC_05_RXD1_SCL1_MISO1 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_0 / SCIn / RXD1_SCL1_MISO1
+    IOPORT_PIN_P020_PFC_06_SPI_MISO3       = (0x06U << IOPORT_PFC_OFFSET), ///< P02_0 / SPIn / SPI_MISO3
+    IOPORT_PIN_P020_PFC_07_CANTX1          = (0x07U << IOPORT_PFC_OFFSET), ///< P02_0 / CANFDn / CANTX1
+    IOPORT_PIN_P020_PFC_08_USB_OTGID       = (0x08U << IOPORT_PFC_OFFSET), ///< P02_0 / USB_HS / USB_OTGID
+    IOPORT_PIN_P020_PFC_0A_HA18            = (0x0AU << IOPORT_PFC_OFFSET), ///< P02_0 / PHOSTIF / HA18
+    IOPORT_PIN_P021_PFC_00_ETHSW_PTPOUT1   = (0x00U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ETHSW / ETHSW_PTPOUT1
+    IOPORT_PIN_P021_PFC_01_A17             = (0x01U << IOPORT_PFC_OFFSET), ///< P02_1 / BSC / A17
+    IOPORT_PIN_P021_PFC_02_ESC_SYNC1       = (0x02U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ESC / ESC_SYNC1
+    IOPORT_PIN_P021_PFC_03_ESC_SYNC0       = (0x03U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ESC / ESC_SYNC0
+    IOPORT_PIN_P021_PFC_04_DE1             = (0x04U << IOPORT_PFC_OFFSET), ///< P02_1 / SCIn / DE1
+    IOPORT_PIN_P021_PFC_05_HA17            = (0x05U << IOPORT_PFC_OFFSET), ///< P02_1 / PHOSTIF / HA17
+    IOPORT_PIN_P022_PFC_00_IRQ14           = (0x00U << IOPORT_PFC_OFFSET), ///< P02_2 / IRQ / IRQ14
+    IOPORT_PIN_P022_PFC_01_ETHSW_TDMAOUT0  = (0x01U << IOPORT_PFC_OFFSET), ///< P02_2 / ETHER_ETHSW / ETHSW_TDMAOUT0
+    IOPORT_PIN_P022_PFC_02_A16             = (0x02U << IOPORT_PFC_OFFSET), ///< P02_2 / BSC / A16
+    IOPORT_PIN_P022_PFC_03_MTIOC2A         = (0x03U << IOPORT_PFC_OFFSET), ///< P02_2 / MTU3n / MTIOC2A
+    IOPORT_PIN_P022_PFC_04_GTIOC10A        = (0x04U << IOPORT_PFC_OFFSET), ///< P02_2 / GPTn / GTIOC10A
+    IOPORT_PIN_P022_PFC_05_POE10           = (0x05U << IOPORT_PFC_OFFSET), ///< P02_2 / MTU_POE3 / POE10
+    IOPORT_PIN_P022_PFC_06_TXD1_SDA1_MOSI1 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_2 / SCIn / TXD1_SDA1_MOSI1
+    IOPORT_PIN_P022_PFC_07_SPI_MOSI3       = (0x07U << IOPORT_PFC_OFFSET), ///< P02_2 / SPIn / SPI_MOSI3
+    IOPORT_PIN_P022_PFC_08_CANTX0          = (0x08U << IOPORT_PFC_OFFSET), ///< P02_2 / CANFDn / CANTX0
+    IOPORT_PIN_P022_PFC_0A_RTCAT1HZ        = (0x0AU << IOPORT_PFC_OFFSET), ///< P02_2 / RTC / RTCAT1HZ
+    IOPORT_PIN_P022_PFC_0B_HA16            = (0x0BU << IOPORT_PFC_OFFSET), ///< P02_2 / PHOSTIF / HA16
+    IOPORT_PIN_P023_PFC_00_IRQ15           = (0x00U << IOPORT_PFC_OFFSET), ///< P02_3 / IRQ / IRQ15
+    IOPORT_PIN_P023_PFC_01_ETHSW_TDMAOUT1  = (0x01U << IOPORT_PFC_OFFSET), ///< P02_3 / ETHER_ETHSW / ETHSW_TDMAOUT1
+    IOPORT_PIN_P023_PFC_02_A15             = (0x02U << IOPORT_PFC_OFFSET), ///< P02_3 / BSC / A15
+    IOPORT_PIN_P023_PFC_03_AH              = (0x03U << IOPORT_PFC_OFFSET), ///< P02_3 / BSC / AH
+    IOPORT_PIN_P023_PFC_04_MTIOC2B         = (0x04U << IOPORT_PFC_OFFSET), ///< P02_3 / MTU3n / MTIOC2B
+    IOPORT_PIN_P023_PFC_05_GTIOC10B        = (0x05U << IOPORT_PFC_OFFSET), ///< P02_3 / GPTn / GTIOC10B
+    IOPORT_PIN_P023_PFC_06_POE11           = (0x06U << IOPORT_PFC_OFFSET), ///< P02_3 / MTU_POE3 / POE11
+    IOPORT_PIN_P023_PFC_07_SS1_CTS1_RTS1   = (0x07U << IOPORT_PFC_OFFSET), ///< P02_3 / SCIn / SS1_CTS1_RTS1
+    IOPORT_PIN_P023_PFC_08_SPI_SSL30       = (0x08U << IOPORT_PFC_OFFSET), ///< P02_3 / SPIn / SPI_SSL30
+    IOPORT_PIN_P023_PFC_09_CANRX1          = (0x09U << IOPORT_PFC_OFFSET), ///< P02_3 / CANFDn / CANRX1
+    IOPORT_PIN_P023_PFC_0B_HA15            = (0x0BU << IOPORT_PFC_OFFSET), ///< P02_3 / PHOSTIF / HA15
+    IOPORT_PIN_P024_PFC_00_TDO             = (0x00U << IOPORT_PFC_OFFSET), ///< P02_4 / JTAG/SWD / TDO
+    IOPORT_PIN_P024_PFC_01_WE0_DQMLL       = (0x01U << IOPORT_PFC_OFFSET), ///< P02_4 / BSC / WE0_DQMLL
+    IOPORT_PIN_P024_PFC_02_DE1             = (0x02U << IOPORT_PFC_OFFSET), ///< P02_4 / SCIn / DE1
+    IOPORT_PIN_P024_PFC_03_SPI_SSL33       = (0x03U << IOPORT_PFC_OFFSET), ///< P02_4 / SPIn / SPI_SSL33
+    IOPORT_PIN_P025_PFC_00_ETHSW_TDMAOUT3  = (0x00U << IOPORT_PFC_OFFSET), ///< P02_5 / ETHER_ETHSW / ETHSW_TDMAOUT3
+    IOPORT_PIN_P025_PFC_01_TDI             = (0x01U << IOPORT_PFC_OFFSET), ///< P02_5 / JTAG/SWD / TDI
+    IOPORT_PIN_P025_PFC_02_WE1_DQMLU       = (0x02U << IOPORT_PFC_OFFSET), ///< P02_5 / BSC / WE1_DQMLU
+    IOPORT_PIN_P025_PFC_03_SCK5            = (0x03U << IOPORT_PFC_OFFSET), ///< P02_5 / SCIn / SCK5
+    IOPORT_PIN_P025_PFC_04_SPI_SSL31       = (0x04U << IOPORT_PFC_OFFSET), ///< P02_5 / SPIn / SPI_SSL31
+    IOPORT_PIN_P026_PFC_00_TMS_SWDIO       = (0x00U << IOPORT_PFC_OFFSET), ///< P02_6 / JTAG/SWD / TMS_SWDIO
+    IOPORT_PIN_P026_PFC_01_RXD5_SCL5_MISO5 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_6 / SCIn / RXD5_SCL5_MISO5
+    IOPORT_PIN_P027_PFC_00_TCK_SWCLK       = (0x00U << IOPORT_PFC_OFFSET), ///< P02_7 / JTAG/SWD / TCK_SWCLK
+    IOPORT_PIN_P027_PFC_01_TXD5_SDA5_MOSI5 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_7 / SCIn / TXD5_SDA5_MOSI5
+    IOPORT_PIN_P030_PFC_00_IRQ14           = (0x00U << IOPORT_PFC_OFFSET), ///< P03_0 / IRQ / IRQ14
+    IOPORT_PIN_P030_PFC_01_TRACEDATA3      = (0x01U << IOPORT_PFC_OFFSET), ///< P03_0 / TRACE / TRACEDATA3
+    IOPORT_PIN_P030_PFC_02_A14             = (0x02U << IOPORT_PFC_OFFSET), ///< P03_0 / BSC / A14
+    IOPORT_PIN_P030_PFC_03_CS5             = (0x03U << IOPORT_PFC_OFFSET), ///< P03_0 / BSC / CS5
+    IOPORT_PIN_P030_PFC_04_GTADSML1        = (0x04U << IOPORT_PFC_OFFSET), ///< P03_0 / GPT / GTADSML1
+    IOPORT_PIN_P030_PFC_05_SCK2            = (0x05U << IOPORT_PFC_OFFSET), ///< P03_0 / SCIn / SCK2
+    IOPORT_PIN_P030_PFC_06_SPI_SSL32       = (0x06U << IOPORT_PFC_OFFSET), ///< P03_0 / SPIn / SPI_SSL32
+    IOPORT_PIN_P030_PFC_07_CANTXDP1        = (0x07U << IOPORT_PFC_OFFSET), ///< P03_0 / CANFDn / CANTXDP1
+    IOPORT_PIN_P030_PFC_09_HA14            = (0x09U << IOPORT_PFC_OFFSET), ///< P03_0 / PHOSTIF / HA14
+    IOPORT_PIN_P035_PFC_00_IRQ5            = (0x00U << IOPORT_PFC_OFFSET), ///< P03_5 / IRQ / IRQ5
+    IOPORT_PIN_P035_PFC_01_ETH2_CRS        = (0x01U << IOPORT_PFC_OFFSET), ///< P03_5 / ETHER_ETHn / ETH2_CRS
+    IOPORT_PIN_P035_PFC_02_A12             = (0x02U << IOPORT_PFC_OFFSET), ///< P03_5 / BSC / A12
+    IOPORT_PIN_P035_PFC_03_MTIOC3A         = (0x03U << IOPORT_PFC_OFFSET), ///< P03_5 / MTU3n / MTIOC3A
+    IOPORT_PIN_P035_PFC_04_GTIOC4A         = (0x04U << IOPORT_PFC_OFFSET), ///< P03_5 / GPTn / GTIOC4A
+    IOPORT_PIN_P035_PFC_05_RXD2_SCL2_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P03_5 / SCIn / RXD2_SCL2_MISO2
+    IOPORT_PIN_P035_PFC_06_MCLK2           = (0x06U << IOPORT_PFC_OFFSET), ///< P03_5 / DSMIFn / MCLK2
+    IOPORT_PIN_P035_PFC_07_HA12            = (0x07U << IOPORT_PFC_OFFSET), ///< P03_5 / PHOSTIF / HA12
+    IOPORT_PIN_P036_PFC_00_IRQ8            = (0x00U << IOPORT_PFC_OFFSET), ///< P03_6 / IRQ / IRQ8
+    IOPORT_PIN_P036_PFC_01_ETH2_COL        = (0x01U << IOPORT_PFC_OFFSET), ///< P03_6 / ETHER_ETHn / ETH2_COL
+    IOPORT_PIN_P036_PFC_02_TRACEDATA4      = (0x02U << IOPORT_PFC_OFFSET), ///< P03_6 / TRACE / TRACEDATA4
+    IOPORT_PIN_P036_PFC_03_A11             = (0x03U << IOPORT_PFC_OFFSET), ///< P03_6 / BSC / A11
+    IOPORT_PIN_P036_PFC_04_MTIOC3B         = (0x04U << IOPORT_PFC_OFFSET), ///< P03_6 / MTU3n / MTIOC3B
+    IOPORT_PIN_P036_PFC_05_GTIOC4B         = (0x05U << IOPORT_PFC_OFFSET), ///< P03_6 / GPTn / GTIOC4B
+    IOPORT_PIN_P036_PFC_06_TXD2_SDA2_MOSI2 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_6 / SCIn / TXD2_SDA2_MOSI2
+    IOPORT_PIN_P036_PFC_07_SPI_SSL13       = (0x07U << IOPORT_PFC_OFFSET), ///< P03_6 / SPIn / SPI_SSL13
+    IOPORT_PIN_P036_PFC_08_MDAT2           = (0x08U << IOPORT_PFC_OFFSET), ///< P03_6 / DSMIFn / MDAT2
+    IOPORT_PIN_P036_PFC_09_HA11            = (0x09U << IOPORT_PFC_OFFSET), ///< P03_6 / PHOSTIF / HA11
+    IOPORT_PIN_P037_PFC_00_IRQ9            = (0x00U << IOPORT_PFC_OFFSET), ///< P03_7 / IRQ / IRQ9
+    IOPORT_PIN_P037_PFC_01_ETH2_TXER       = (0x01U << IOPORT_PFC_OFFSET), ///< P03_7 / ETHER_ETHn / ETH2_TXER
+    IOPORT_PIN_P037_PFC_02_TRACEDATA5      = (0x02U << IOPORT_PFC_OFFSET), ///< P03_7 / TRACE / TRACEDATA5
+    IOPORT_PIN_P037_PFC_03_A10             = (0x03U << IOPORT_PFC_OFFSET), ///< P03_7 / BSC / A10
+    IOPORT_PIN_P037_PFC_04_MTIOC3C         = (0x04U << IOPORT_PFC_OFFSET), ///< P03_7 / MTU3n / MTIOC3C
+    IOPORT_PIN_P037_PFC_05_GTIOC5A         = (0x05U << IOPORT_PFC_OFFSET), ///< P03_7 / GPTn / GTIOC5A
+    IOPORT_PIN_P037_PFC_06_SCK3            = (0x06U << IOPORT_PFC_OFFSET), ///< P03_7 / SCIn / SCK3
+    IOPORT_PIN_P037_PFC_07_HA10            = (0x07U << IOPORT_PFC_OFFSET), ///< P03_7 / PHOSTIF / HA10
+    IOPORT_PIN_P040_PFC_00_TRACEDATA6      = (0x00U << IOPORT_PFC_OFFSET), ///< P04_0 / TRACE / TRACEDATA6
+    IOPORT_PIN_P040_PFC_01_A9              = (0x01U << IOPORT_PFC_OFFSET), ///< P04_0 / BSC / A9
+    IOPORT_PIN_P040_PFC_02_MTIOC3D         = (0x02U << IOPORT_PFC_OFFSET), ///< P04_0 / MTU3n / MTIOC3D
+    IOPORT_PIN_P040_PFC_03_GTIOC5B         = (0x03U << IOPORT_PFC_OFFSET), ///< P04_0 / GPTn / GTIOC5B
+    IOPORT_PIN_P040_PFC_04_RXD3_SCL3_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_0 / SCIn / RXD3_SCL3_MISO3
+    IOPORT_PIN_P040_PFC_05_HA9             = (0x05U << IOPORT_PFC_OFFSET), ///< P04_0 / PHOSTIF / HA9
+    IOPORT_PIN_P041_PFC_00_CKIO            = (0x00U << IOPORT_PFC_OFFSET), ///< P04_1 / BSC / CKIO
+    IOPORT_PIN_P041_PFC_01_TXD3_SDA3_MOSI3 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_1 / SCIn / TXD3_SDA3_MOSI3
+    IOPORT_PIN_P041_PFC_02_SPI_MOSI0       = (0x02U << IOPORT_PFC_OFFSET), ///< P04_1 / SPIn / SPI_MOSI0
+    IOPORT_PIN_P041_PFC_03_IIC_SDA2        = (0x03U << IOPORT_PFC_OFFSET), ///< P04_1 / IICn / IIC_SDA2
+    IOPORT_PIN_P041_PFC_04_HCKIO           = (0x04U << IOPORT_PFC_OFFSET), ///< P04_1 / PHOSTIF / HCKIO
+    IOPORT_PIN_P044_PFC_00_IRQ10           = (0x00U << IOPORT_PFC_OFFSET), ///< P04_4 / IRQ / IRQ10
+    IOPORT_PIN_P044_PFC_01_TRACEDATA7      = (0x01U << IOPORT_PFC_OFFSET), ///< P04_4 / TRACE / TRACEDATA7
+    IOPORT_PIN_P044_PFC_02_A8              = (0x02U << IOPORT_PFC_OFFSET), ///< P04_4 / BSC / A8
+    IOPORT_PIN_P044_PFC_03_GTADSMP0        = (0x03U << IOPORT_PFC_OFFSET), ///< P04_4 / GPT / GTADSMP0
+    IOPORT_PIN_P044_PFC_04_POE10           = (0x04U << IOPORT_PFC_OFFSET), ///< P04_4 / MTU_POE3 / POE10
+    IOPORT_PIN_P044_PFC_05_CTS3            = (0x05U << IOPORT_PFC_OFFSET), ///< P04_4 / SCIn / CTS3
+    IOPORT_PIN_P044_PFC_06_SPI_RSPCK1      = (0x06U << IOPORT_PFC_OFFSET), ///< P04_4 / SPIn / SPI_RSPCK1
+    IOPORT_PIN_P044_PFC_08_HA8             = (0x08U << IOPORT_PFC_OFFSET), ///< P04_4 / PHOSTIF / HA8
+    IOPORT_PIN_P045_PFC_00_A7              = (0x00U << IOPORT_PFC_OFFSET), ///< P04_5 / BSC / A7
+    IOPORT_PIN_P045_PFC_01_DE3             = (0x01U << IOPORT_PFC_OFFSET), ///< P04_5 / SCIn / DE3
+    IOPORT_PIN_P045_PFC_02_ETHSW_PTPOUT0   = (0x02U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ETHSW / ETHSW_PTPOUT0
+    IOPORT_PIN_P045_PFC_03_ESC_SYNC0       = (0x03U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ESC / ESC_SYNC0
+    IOPORT_PIN_P045_PFC_04_ESC_SYNC1       = (0x04U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ESC / ESC_SYNC1
+    IOPORT_PIN_P045_PFC_05_HA7             = (0x05U << IOPORT_PFC_OFFSET), ///< P04_5 / PHOSTIF / HA7
+    IOPORT_PIN_P046_PFC_00_ETH1_TXER       = (0x00U << IOPORT_PFC_OFFSET), ///< P04_6 / ETHER_ETHn / ETH1_TXER
+    IOPORT_PIN_P046_PFC_01_A6              = (0x01U << IOPORT_PFC_OFFSET), ///< P04_6 / BSC / A6
+    IOPORT_PIN_P046_PFC_02_DACK            = (0x02U << IOPORT_PFC_OFFSET), ///< P04_6 / DMAC / DACK
+    IOPORT_PIN_P046_PFC_03_RTCAT1HZ        = (0x03U << IOPORT_PFC_OFFSET), ///< P04_6 / RTC / RTCAT1HZ
+    IOPORT_PIN_P046_PFC_04_HA6             = (0x04U << IOPORT_PFC_OFFSET), ///< P04_6 / PHOSTIF / HA6
+    IOPORT_PIN_P047_PFC_00_ETH0_TXER       = (0x00U << IOPORT_PFC_OFFSET), ///< P04_7 / ETHER_ETHn / ETH0_TXER
+    IOPORT_PIN_P047_PFC_01_A5              = (0x01U << IOPORT_PFC_OFFSET), ///< P04_7 / BSC / A5
+    IOPORT_PIN_P047_PFC_02_SPI_SSL21       = (0x02U << IOPORT_PFC_OFFSET), ///< P04_7 / SPIn / SPI_SSL21
+    IOPORT_PIN_P047_PFC_03_ETH2_TXER       = (0x03U << IOPORT_PFC_OFFSET), ///< P04_7 / ETHER_ETHn / ETH2_TXER
+    IOPORT_PIN_P047_PFC_04_HA5             = (0x04U << IOPORT_PFC_OFFSET), ///< P04_7 / PHOSTIF / HA5
+    IOPORT_PIN_P050_PFC_00_IRQ12           = (0x00U << IOPORT_PFC_OFFSET), ///< P05_0 / IRQ / IRQ12
+    IOPORT_PIN_P050_PFC_01_ETH1_CRS        = (0x01U << IOPORT_PFC_OFFSET), ///< P05_0 / ETHER_ETHn / ETH1_CRS
+    IOPORT_PIN_P050_PFC_02_A4              = (0x02U << IOPORT_PFC_OFFSET), ///< P05_0 / BSC / A4
+    IOPORT_PIN_P050_PFC_03_MTIOC4A         = (0x03U << IOPORT_PFC_OFFSET), ///< P05_0 / MTU3n / MTIOC4A
+    IOPORT_PIN_P050_PFC_04_GTIOC6A         = (0x04U << IOPORT_PFC_OFFSET), ///< P05_0 / GPTn / GTIOC6A
+    IOPORT_PIN_P050_PFC_05_CMTW0_TOC0      = (0x05U << IOPORT_PFC_OFFSET), ///< P05_0 / CMTWn / CMTW0_TOC0
+    IOPORT_PIN_P050_PFC_06_SS5_CTS5_RTS5   = (0x06U << IOPORT_PFC_OFFSET), ///< P05_0 / SCIn / SS5_CTS5_RTS5
+    IOPORT_PIN_P050_PFC_07_CANTXDP0        = (0x07U << IOPORT_PFC_OFFSET), ///< P05_0 / CANFDn / CANTXDP0
+    IOPORT_PIN_P050_PFC_08_USB_VBUSEN      = (0x08U << IOPORT_PFC_OFFSET), ///< P05_0 / USB_HS / USB_VBUSEN
+    IOPORT_PIN_P050_PFC_09_MCLK3           = (0x09U << IOPORT_PFC_OFFSET), ///< P05_0 / DSMIFn / MCLK3
+    IOPORT_PIN_P050_PFC_0B_HA4             = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_0 / PHOSTIF / HA4
+    IOPORT_PIN_P051_PFC_00_IRQ13           = (0x00U << IOPORT_PFC_OFFSET), ///< P05_1 / IRQ / IRQ13
+    IOPORT_PIN_P051_PFC_01_ETH1_COL        = (0x01U << IOPORT_PFC_OFFSET), ///< P05_1 / ETHER_ETHn / ETH1_COL
+    IOPORT_PIN_P051_PFC_02_A3              = (0x02U << IOPORT_PFC_OFFSET), ///< P05_1 / BSC / A3
+    IOPORT_PIN_P051_PFC_03_MTIOC4B         = (0x03U << IOPORT_PFC_OFFSET), ///< P05_1 / MTU3n / MTIOC4B
+    IOPORT_PIN_P051_PFC_04_GTIOC6B         = (0x04U << IOPORT_PFC_OFFSET), ///< P05_1 / GPTn / GTIOC6B
+    IOPORT_PIN_P051_PFC_05_CMTW0_TIC1      = (0x05U << IOPORT_PFC_OFFSET), ///< P05_1 / CMTWn / CMTW0_TIC1
+    IOPORT_PIN_P051_PFC_06_CTS5            = (0x06U << IOPORT_PFC_OFFSET), ///< P05_1 / SCIn / CTS5
+    IOPORT_PIN_P051_PFC_07_CANRXDP0        = (0x07U << IOPORT_PFC_OFFSET), ///< P05_1 / CANFDn / CANRXDP0
+    IOPORT_PIN_P051_PFC_08_USB_EXICEN      = (0x08U << IOPORT_PFC_OFFSET), ///< P05_1 / USB_HS / USB_EXICEN
+    IOPORT_PIN_P051_PFC_09_MDAT3           = (0x09U << IOPORT_PFC_OFFSET), ///< P05_1 / DSMIFn / MDAT3
+    IOPORT_PIN_P051_PFC_0B_HA3             = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_1 / PHOSTIF / HA3
+    IOPORT_PIN_P052_PFC_00_IRQ14           = (0x00U << IOPORT_PFC_OFFSET), ///< P05_2 / IRQ / IRQ14
+    IOPORT_PIN_P052_PFC_01_ETH0_CRS        = (0x01U << IOPORT_PFC_OFFSET), ///< P05_2 / ETHER_ETHn / ETH0_CRS
+    IOPORT_PIN_P052_PFC_02_A2              = (0x02U << IOPORT_PFC_OFFSET), ///< P05_2 / BSC / A2
+    IOPORT_PIN_P052_PFC_03_MTIOC4C         = (0x03U << IOPORT_PFC_OFFSET), ///< P05_2 / MTU3n / MTIOC4C
+    IOPORT_PIN_P052_PFC_04_GTETRGSA        = (0x04U << IOPORT_PFC_OFFSET), ///< P05_2 / GPT_POEG / GTETRGSA
+    IOPORT_PIN_P052_PFC_05_GTIOC7A         = (0x05U << IOPORT_PFC_OFFSET), ///< P05_2 / GPTn / GTIOC7A
+    IOPORT_PIN_P052_PFC_06_CMTW0_TOC0      = (0x06U << IOPORT_PFC_OFFSET), ///< P05_2 / CMTWn / CMTW0_TOC0
+    IOPORT_PIN_P052_PFC_07_DE5             = (0x07U << IOPORT_PFC_OFFSET), ///< P05_2 / SCIn / DE5
+    IOPORT_PIN_P052_PFC_08_IIC_SCL1        = (0x08U << IOPORT_PFC_OFFSET), ///< P05_2 / IICn / IIC_SCL1
+    IOPORT_PIN_P052_PFC_09_CANRX0          = (0x09U << IOPORT_PFC_OFFSET), ///< P05_2 / CANFDn / CANRX0
+    IOPORT_PIN_P052_PFC_0A_DREQ            = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_2 / DMAC / DREQ
+    IOPORT_PIN_P052_PFC_0B_USB_VBUSEN      = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_2 / USB_HS / USB_VBUSEN
+    IOPORT_PIN_P052_PFC_0D_HA2             = (0x0DU << IOPORT_PFC_OFFSET), ///< P05_2 / PHOSTIF / HA2
+    IOPORT_PIN_P053_PFC_00_IRQ15           = (0x00U << IOPORT_PFC_OFFSET), ///< P05_3 / IRQ / IRQ15
+    IOPORT_PIN_P053_PFC_01_ETH0_COL        = (0x01U << IOPORT_PFC_OFFSET), ///< P05_3 / ETHER_ETHn / ETH0_COL
+    IOPORT_PIN_P053_PFC_02_A1              = (0x02U << IOPORT_PFC_OFFSET), ///< P05_3 / BSC / A1
+    IOPORT_PIN_P053_PFC_03_MTIOC4D         = (0x03U << IOPORT_PFC_OFFSET), ///< P05_3 / MTU3n / MTIOC4D
+    IOPORT_PIN_P053_PFC_04_GTETRGSB        = (0x04U << IOPORT_PFC_OFFSET), ///< P05_3 / GPT_POEG / GTETRGSB
+    IOPORT_PIN_P053_PFC_05_GTIOC7B         = (0x05U << IOPORT_PFC_OFFSET), ///< P05_3 / GPTn / GTIOC7B
+    IOPORT_PIN_P053_PFC_06_POE11           = (0x06U << IOPORT_PFC_OFFSET), ///< P05_3 / MTU_POE3 / POE11
+    IOPORT_PIN_P053_PFC_07_CMTW0_TIC0      = (0x07U << IOPORT_PFC_OFFSET), ///< P05_3 / CMTWn / CMTW0_TIC0
+    IOPORT_PIN_P053_PFC_08_SCK4            = (0x08U << IOPORT_PFC_OFFSET), ///< P05_3 / SCIn / SCK4
+    IOPORT_PIN_P053_PFC_09_IIC_SDA1        = (0x09U << IOPORT_PFC_OFFSET), ///< P05_3 / IICn / IIC_SDA1
+    IOPORT_PIN_P053_PFC_0A_CANTX0          = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_3 / CANFDn / CANTX0
+    IOPORT_PIN_P053_PFC_0B_USB_EXICEN      = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_3 / USB_HS / USB_EXICEN
+    IOPORT_PIN_P053_PFC_0D_HA1             = (0x0DU << IOPORT_PFC_OFFSET), ///< P05_3 / PHOSTIF / HA1
+    IOPORT_PIN_P054_PFC_00_IRQ12           = (0x00U << IOPORT_PFC_OFFSET), ///< P05_4 / IRQ / IRQ12
+    IOPORT_PIN_P054_PFC_01_ETHSW_LPI0      = (0x01U << IOPORT_PFC_OFFSET), ///< P05_4 / ETHER_ETHSW / ETHSW_LPI0
+    IOPORT_PIN_P054_PFC_02_A0              = (0x02U << IOPORT_PFC_OFFSET), ///< P05_4 / BSC / A0
+    IOPORT_PIN_P054_PFC_03_GTIOC14A        = (0x03U << IOPORT_PFC_OFFSET), ///< P05_4 / GPTn / GTIOC14A
+    IOPORT_PIN_P054_PFC_04_RXD4_SCL4_MISO4 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_4 / SCIn / RXD4_SCL4_MISO4
+    IOPORT_PIN_P054_PFC_05_SPI_SSL00       = (0x05U << IOPORT_PFC_OFFSET), ///< P05_4 / SPIn / SPI_SSL00
+    IOPORT_PIN_P054_PFC_06_CANTXDP0        = (0x06U << IOPORT_PFC_OFFSET), ///< P05_4 / CANFDn / CANTXDP0
+    IOPORT_PIN_P054_PFC_07_DACK            = (0x07U << IOPORT_PFC_OFFSET), ///< P05_4 / DMAC / DACK
+    IOPORT_PIN_P054_PFC_08_USB_OVRCUR      = (0x08U << IOPORT_PFC_OFFSET), ///< P05_4 / USB_HS / USB_OVRCUR
+    IOPORT_PIN_P054_PFC_0A_HA0             = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_4 / PHOSTIF / HA0
+    IOPORT_PIN_P055_PFC_00_ETHSW_PHYLINK1  = (0x00U << IOPORT_PFC_OFFSET), ///< P05_5 / ETHER_ETHSW / ETHSW_PHYLINK1
+    IOPORT_PIN_P055_PFC_02_ESC_PHYLINK1    = (0x02U << IOPORT_PFC_OFFSET), ///< P05_5 / ETHER_ESC / ESC_PHYLINK1
+    IOPORT_PIN_P055_PFC_03_GTIOC14B        = (0x03U << IOPORT_PFC_OFFSET), ///< P05_5 / GPTn / GTIOC14B
+    IOPORT_PIN_P055_PFC_04_CMTW0_TOC1      = (0x04U << IOPORT_PFC_OFFSET), ///< P05_5 / CMTWn / CMTW0_TOC1
+    IOPORT_PIN_P055_PFC_05_SPI_RSPCK2      = (0x05U << IOPORT_PFC_OFFSET), ///< P05_5 / SPIn / SPI_RSPCK2
+    IOPORT_PIN_P056_PFC_00_IRQ12           = (0x00U << IOPORT_PFC_OFFSET), ///< P05_6 / IRQ / IRQ12
+    IOPORT_PIN_P056_PFC_01_ETH1_RXER       = (0x01U << IOPORT_PFC_OFFSET), ///< P05_6 / ETHER_ETHn / ETH1_RXER
+    IOPORT_PIN_P056_PFC_03_GTIOC15A        = (0x03U << IOPORT_PFC_OFFSET), ///< P05_6 / GPTn / GTIOC15A
+    IOPORT_PIN_P056_PFC_04_CMTW1_TIC0      = (0x04U << IOPORT_PFC_OFFSET), ///< P05_6 / CMTWn / CMTW1_TIC0
+    IOPORT_PIN_P056_PFC_05_SPI_SSL22       = (0x05U << IOPORT_PFC_OFFSET), ///< P05_6 / SPIn / SPI_SSL22
+    IOPORT_PIN_P057_PFC_00_ETH1_TXD2       = (0x00U << IOPORT_PFC_OFFSET), ///< P05_7 / ETHER_ETHn / ETH1_TXD2
+    IOPORT_PIN_P057_PFC_02_GTIOC15B        = (0x02U << IOPORT_PFC_OFFSET), ///< P05_7 / GPTn / GTIOC15B
+    IOPORT_PIN_P057_PFC_03_CMTW1_TOC1      = (0x03U << IOPORT_PFC_OFFSET), ///< P05_7 / CMTWn / CMTW1_TOC1
+    IOPORT_PIN_P057_PFC_04_TXD4_SDA4_MOSI4 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_7 / SCIn / TXD4_SDA4_MOSI4
+    IOPORT_PIN_P057_PFC_05_SPI_SSL23       = (0x05U << IOPORT_PFC_OFFSET), ///< P05_7 / SPIn / SPI_SSL23
+    IOPORT_PIN_P060_PFC_00_ETH1_TXD3       = (0x00U << IOPORT_PFC_OFFSET), ///< P06_0 / ETHER_ETHn / ETH1_TXD3
+    IOPORT_PIN_P060_PFC_02_GTIOC16A        = (0x02U << IOPORT_PFC_OFFSET), ///< P06_0 / GPTn / GTIOC16A
+    IOPORT_PIN_P060_PFC_03_CMTW1_TOC0      = (0x03U << IOPORT_PFC_OFFSET), ///< P06_0 / CMTWn / CMTW1_TOC0
+    IOPORT_PIN_P060_PFC_04_SS4_CTS4_RTS4   = (0x04U << IOPORT_PFC_OFFSET), ///< P06_0 / SCIn / SS4_CTS4_RTS4
+    IOPORT_PIN_P060_PFC_05_SPI_SSL23       = (0x05U << IOPORT_PFC_OFFSET), ///< P06_0 / SPIn / SPI_SSL23
+    IOPORT_PIN_P060_PFC_06_CANRX1          = (0x06U << IOPORT_PFC_OFFSET), ///< P06_0 / CANFDn / CANRX1
+    IOPORT_PIN_P061_PFC_00_ETH1_REFCLK     = (0x00U << IOPORT_PFC_OFFSET), ///< P06_1 / ETHER_ETHn / ETH1_REFCLK
+    IOPORT_PIN_P061_PFC_01_RMII1_REFCLK    = (0x01U << IOPORT_PFC_OFFSET), ///< P06_1 / ETHER_ETHn / RMII1_REFCLK
+    IOPORT_PIN_P061_PFC_03_GTIOC16B        = (0x03U << IOPORT_PFC_OFFSET), ///< P06_1 / GPTn / GTIOC16B
+    IOPORT_PIN_P061_PFC_04_CTS4            = (0x04U << IOPORT_PFC_OFFSET), ///< P06_1 / SCIn / CTS4
+    IOPORT_PIN_P061_PFC_05_SPI_SSL22       = (0x05U << IOPORT_PFC_OFFSET), ///< P06_1 / SPIn / SPI_SSL22
+    IOPORT_PIN_P061_PFC_06_CANTX1          = (0x06U << IOPORT_PFC_OFFSET), ///< P06_1 / CANFDn / CANTX1
+    IOPORT_PIN_P062_PFC_00_ETH1_TXD1       = (0x00U << IOPORT_PFC_OFFSET), ///< P06_2 / ETHER_ETHn / ETH1_TXD1
+    IOPORT_PIN_P062_PFC_02_GTIOC17A        = (0x02U << IOPORT_PFC_OFFSET), ///< P06_2 / GPTn / GTIOC17A
+    IOPORT_PIN_P062_PFC_03_CANRXDP1        = (0x03U << IOPORT_PFC_OFFSET), ///< P06_2 / CANFDn / CANRXDP1
+    IOPORT_PIN_P063_PFC_00_ETH1_TXD0       = (0x00U << IOPORT_PFC_OFFSET), ///< P06_3 / ETHER_ETHn / ETH1_TXD0
+    IOPORT_PIN_P063_PFC_02_GTIOC17B        = (0x02U << IOPORT_PFC_OFFSET), ///< P06_3 / GPTn / GTIOC17B
+    IOPORT_PIN_P063_PFC_03_CMTW1_TIC1      = (0x03U << IOPORT_PFC_OFFSET), ///< P06_3 / CMTWn / CMTW1_TIC1
+    IOPORT_PIN_P063_PFC_04_DE4             = (0x04U << IOPORT_PFC_OFFSET), ///< P06_3 / SCIn / DE4
+    IOPORT_PIN_P063_PFC_05_SPI_MISO1       = (0x05U << IOPORT_PFC_OFFSET), ///< P06_3 / SPIn / SPI_MISO1
+    IOPORT_PIN_P063_PFC_06_CANTXDP1        = (0x06U << IOPORT_PFC_OFFSET), ///< P06_3 / CANFDn / CANTXDP1
+    IOPORT_PIN_P064_PFC_00_ETH1_TXCLK      = (0x00U << IOPORT_PFC_OFFSET), ///< P06_4 / ETHER_ETHn / ETH1_TXCLK
+    IOPORT_PIN_P064_PFC_02_GTIOC11A        = (0x02U << IOPORT_PFC_OFFSET), ///< P06_4 / GPTn / GTIOC11A
+    IOPORT_PIN_P064_PFC_03_SPI_MOSI1       = (0x03U << IOPORT_PFC_OFFSET), ///< P06_4 / SPIn / SPI_MOSI1
+    IOPORT_PIN_P065_PFC_00_ETH1_TXEN       = (0x00U << IOPORT_PFC_OFFSET), ///< P06_5 / ETHER_ETHn / ETH1_TXEN
+    IOPORT_PIN_P065_PFC_02_GTIOC11B        = (0x02U << IOPORT_PFC_OFFSET), ///< P06_5 / GPTn / GTIOC11B
+    IOPORT_PIN_P066_PFC_00_ETH1_RXD0       = (0x00U << IOPORT_PFC_OFFSET), ///< P06_6 / ETHER_ETHn / ETH1_RXD0
+    IOPORT_PIN_P066_PFC_02_GTIOC12A        = (0x02U << IOPORT_PFC_OFFSET), ///< P06_6 / GPTn / GTIOC12A
+    IOPORT_PIN_P066_PFC_03_SPI_SSL10       = (0x03U << IOPORT_PFC_OFFSET), ///< P06_6 / SPIn / SPI_SSL10
+    IOPORT_PIN_P067_PFC_00_ETH1_RXD1       = (0x00U << IOPORT_PFC_OFFSET), ///< P06_7 / ETHER_ETHn / ETH1_RXD1
+    IOPORT_PIN_P067_PFC_02_GTIOC12B        = (0x02U << IOPORT_PFC_OFFSET), ///< P06_7 / GPTn / GTIOC12B
+    IOPORT_PIN_P067_PFC_03_SPI_SSL11       = (0x03U << IOPORT_PFC_OFFSET), ///< P06_7 / SPIn / SPI_SSL11
+    IOPORT_PIN_P070_PFC_00_ETH1_RXD2       = (0x00U << IOPORT_PFC_OFFSET), ///< P07_0 / ETHER_ETHn / ETH1_RXD2
+    IOPORT_PIN_P070_PFC_02_GTIOC13A        = (0x02U << IOPORT_PFC_OFFSET), ///< P07_0 / GPTn / GTIOC13A
+    IOPORT_PIN_P071_PFC_00_ETH1_RXD3       = (0x00U << IOPORT_PFC_OFFSET), ///< P07_1 / ETHER_ETHn / ETH1_RXD3
+    IOPORT_PIN_P071_PFC_02_GTIOC13B        = (0x02U << IOPORT_PFC_OFFSET), ///< P07_1 / GPTn / GTIOC13B
+    IOPORT_PIN_P072_PFC_00_ETH1_RXDV       = (0x00U << IOPORT_PFC_OFFSET), ///< P07_2 / ETHER_ETHn / ETH1_RXDV
+    IOPORT_PIN_P073_PFC_00_ETH1_RXCLK      = (0x00U << IOPORT_PFC_OFFSET), ///< P07_3 / ETHER_ETHn / ETH1_RXCLK
+    IOPORT_PIN_P074_PFC_00_IRQ1            = (0x00U << IOPORT_PFC_OFFSET), ///< P07_4 / IRQ / IRQ1
+    IOPORT_PIN_P074_PFC_01_ADTRG0          = (0x01U << IOPORT_PFC_OFFSET), ///< P07_4 / ADCn / ADTRG0
+    IOPORT_PIN_P074_PFC_02_USB_VBUSIN      = (0x02U << IOPORT_PFC_OFFSET), ///< P07_4 / USB_HS / USB_VBUSIN
+    IOPORT_PIN_P084_PFC_00_ETH0_RXD3       = (0x00U << IOPORT_PFC_OFFSET), ///< P08_4 / ETHER_ETHn / ETH0_RXD3
+    IOPORT_PIN_P084_PFC_02_MTIOC6A         = (0x02U << IOPORT_PFC_OFFSET), ///< P08_4 / MTU3n / MTIOC6A
+    IOPORT_PIN_P085_PFC_00_ETH0_RXDV       = (0x00U << IOPORT_PFC_OFFSET), ///< P08_5 / ETHER_ETHn / ETH0_RXDV
+    IOPORT_PIN_P085_PFC_01_MTIOC6B         = (0x01U << IOPORT_PFC_OFFSET), ///< P08_5 / MTU3n / MTIOC6B
+    IOPORT_PIN_P086_PFC_00_ETH0_RXCLK      = (0x00U << IOPORT_PFC_OFFSET), ///< P08_6 / ETHER_ETHn / ETH0_RXCLK
+    IOPORT_PIN_P086_PFC_01_MTIOC6C         = (0x01U << IOPORT_PFC_OFFSET), ///< P08_6 / MTU3n / MTIOC6C
+    IOPORT_PIN_P087_PFC_00_GMAC_MDC        = (0x00U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_GMAC / GMAC_MDC
+    IOPORT_PIN_P087_PFC_01_ETHSW_MDC       = (0x01U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_ETHSW / ETHSW_MDC
+    IOPORT_PIN_P087_PFC_03_ESC_MDC         = (0x03U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_ESC / ESC_MDC
+    IOPORT_PIN_P087_PFC_04_MTIOC6D         = (0x04U << IOPORT_PFC_OFFSET), ///< P08_7 / MTU3n / MTIOC6D
+    IOPORT_PIN_P090_PFC_00_GMAC_MDIO       = (0x00U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_GMAC / GMAC_MDIO
+    IOPORT_PIN_P090_PFC_01_ETHSW_MDIO      = (0x01U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_ETHSW / ETHSW_MDIO
+    IOPORT_PIN_P090_PFC_03_ESC_MDIO        = (0x03U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_ESC / ESC_MDIO
+    IOPORT_PIN_P090_PFC_04_MTIOC7A         = (0x04U << IOPORT_PFC_OFFSET), ///< P09_0 / MTU3n / MTIOC7A
+    IOPORT_PIN_P091_PFC_00_ETH0_REFCLK     = (0x00U << IOPORT_PFC_OFFSET), ///< P09_1 / ETHER_ETHn / ETH0_REFCLK
+    IOPORT_PIN_P091_PFC_01_RMII0_REFCLK    = (0x01U << IOPORT_PFC_OFFSET), ///< P09_1 / ETHER_ETHn / RMII0_REFCLK
+    IOPORT_PIN_P091_PFC_02_MTIOC7B         = (0x02U << IOPORT_PFC_OFFSET), ///< P09_1 / MTU3n / MTIOC7B
+    IOPORT_PIN_P092_PFC_00_IRQ0            = (0x00U << IOPORT_PFC_OFFSET), ///< P09_2 / IRQ / IRQ0
+    IOPORT_PIN_P092_PFC_01_ETH0_RXER       = (0x01U << IOPORT_PFC_OFFSET), ///< P09_2 / ETHER_ETHn / ETH0_RXER
+    IOPORT_PIN_P092_PFC_03_MTIOC7C         = (0x03U << IOPORT_PFC_OFFSET), ///< P09_2 / MTU3n / MTIOC7C
+    IOPORT_PIN_P093_PFC_00_ETH0_TXD3       = (0x00U << IOPORT_PFC_OFFSET), ///< P09_3 / ETHER_ETHn / ETH0_TXD3
+    IOPORT_PIN_P093_PFC_01_MTIOC7D         = (0x01U << IOPORT_PFC_OFFSET), ///< P09_3 / MTU3n / MTIOC7D
+    IOPORT_PIN_P094_PFC_00_ETH0_TXD2       = (0x00U << IOPORT_PFC_OFFSET), ///< P09_4 / ETHER_ETHn / ETH0_TXD2
+    IOPORT_PIN_P095_PFC_00_ETH0_TXD1       = (0x00U << IOPORT_PFC_OFFSET), ///< P09_5 / ETHER_ETHn / ETH0_TXD1
+    IOPORT_PIN_P096_PFC_00_ETH0_TXD0       = (0x00U << IOPORT_PFC_OFFSET), ///< P09_6 / ETHER_ETHn / ETH0_TXD0
+    IOPORT_PIN_P097_PFC_00_ETH0_TXCLK      = (0x00U << IOPORT_PFC_OFFSET), ///< P09_7 / ETHER_ETHn / ETH0_TXCLK
+    IOPORT_PIN_P100_PFC_00_ETH0_TXEN       = (0x00U << IOPORT_PFC_OFFSET), ///< P10_0 / ETHER_ETHn / ETH0_TXEN
+    IOPORT_PIN_P101_PFC_00_ETH0_RXD0       = (0x00U << IOPORT_PFC_OFFSET), ///< P10_1 / ETHER_ETHn / ETH0_RXD0
+    IOPORT_PIN_P102_PFC_00_ETH0_RXD1       = (0x00U << IOPORT_PFC_OFFSET), ///< P10_2 / ETHER_ETHn / ETH0_RXD1
+    IOPORT_PIN_P103_PFC_00_ETH0_RXD2       = (0x00U << IOPORT_PFC_OFFSET), ///< P10_3 / ETHER_ETHn / ETH0_RXD2
+    IOPORT_PIN_P103_PFC_01_RTCAT1HZ        = (0x01U << IOPORT_PFC_OFFSET), ///< P10_3 / RTC / RTCAT1HZ
+    IOPORT_PIN_P104_PFC_00_IRQ11           = (0x00U << IOPORT_PFC_OFFSET), ///< P10_4 / IRQ / IRQ11
+    IOPORT_PIN_P104_PFC_01_ETHSW_PHYLINK0  = (0x01U << IOPORT_PFC_OFFSET), ///< P10_4 / ETHER_ETHSW / ETHSW_PHYLINK0
+    IOPORT_PIN_P104_PFC_03_ESC_PHYLINK0    = (0x03U << IOPORT_PFC_OFFSET), ///< P10_4 / ETHER_ESC / ESC_PHYLINK0
+    IOPORT_PIN_P124_PFC_01_ETH1_CRS        = (0x01U << IOPORT_PFC_OFFSET), ///< P12_4 / ETHER_ETHn / ETH1_CRS
+    IOPORT_PIN_P124_PFC_02_TRACEDATA0      = (0x02U << IOPORT_PFC_OFFSET), ///< P12_4 / TRACE / TRACEDATA0
+    IOPORT_PIN_P124_PFC_03_D15             = (0x03U << IOPORT_PFC_OFFSET), ///< P12_4 / BSC / D15
+    IOPORT_PIN_P124_PFC_04_MTIOC8B         = (0x04U << IOPORT_PFC_OFFSET), ///< P12_4 / MTU3n / MTIOC8B
+    IOPORT_PIN_P124_PFC_05_GTIOC8B         = (0x05U << IOPORT_PFC_OFFSET), ///< P12_4 / GPTn / GTIOC8B
+    IOPORT_PIN_P124_PFC_06_SPI_SSL01       = (0x06U << IOPORT_PFC_OFFSET), ///< P12_4 / SPIn / SPI_SSL01
+    IOPORT_PIN_P124_PFC_08_MBX_HINT        = (0x08U << IOPORT_PFC_OFFSET), ///< P12_4 / MBXSEM / MBX_HINT
+    IOPORT_PIN_P132_PFC_00_IRQ5            = (0x00U << IOPORT_PFC_OFFSET), ///< P13_2 / IRQ / IRQ5
+    IOPORT_PIN_P132_PFC_02_ETHSW_PTPOUT2   = (0x02U << IOPORT_PFC_OFFSET), ///< P13_2 / ETHER_ETHSW / ETHSW_PTPOUT2
+    IOPORT_PIN_P132_PFC_03_TRACEDATA6      = (0x03U << IOPORT_PFC_OFFSET), ///< P13_2 / TRACE / TRACEDATA6
+    IOPORT_PIN_P132_PFC_04_D9              = (0x04U << IOPORT_PFC_OFFSET), ///< P13_2 / BSC / D9
+    IOPORT_PIN_P132_PFC_05_ESC_I2CCLK      = (0x05U << IOPORT_PFC_OFFSET), ///< P13_2 / ETHER_ESC / ESC_I2CCLK
+    IOPORT_PIN_P132_PFC_06_MTIOC0A         = (0x06U << IOPORT_PFC_OFFSET), ///< P13_2 / MTU3n / MTIOC0A
+    IOPORT_PIN_P132_PFC_07_GTIOC10A        = (0x07U << IOPORT_PFC_OFFSET), ///< P13_2 / GPTn / GTIOC10A
+    IOPORT_PIN_P132_PFC_08_POE8            = (0x08U << IOPORT_PFC_OFFSET), ///< P13_2 / MTU_POE3 / POE8
+    IOPORT_PIN_P132_PFC_09_SS1_CTS1_RTS1   = (0x09U << IOPORT_PFC_OFFSET), ///< P13_2 / SCIn / SS1_CTS1_RTS1
+    IOPORT_PIN_P132_PFC_0A_SPI_MISO0       = (0x0AU << IOPORT_PFC_OFFSET), ///< P13_2 / SPIn / SPI_MISO0
+    IOPORT_PIN_P132_PFC_0B_IIC_SCL0        = (0x0BU << IOPORT_PFC_OFFSET), ///< P13_2 / IICn / IIC_SCL0
+    IOPORT_PIN_P132_PFC_0C_MCLK4           = (0x0CU << IOPORT_PFC_OFFSET), ///< P13_2 / DSMIFn / MCLK4
+    IOPORT_PIN_P132_PFC_0E_A13             = (0x0EU << IOPORT_PFC_OFFSET), ///< P13_2 / BSC / A13
+    IOPORT_PIN_P133_PFC_01_ETHSW_PTPOUT3   = (0x01U << IOPORT_PFC_OFFSET), ///< P13_3 / ETHER_ETHSW / ETHSW_PTPOUT3
+    IOPORT_PIN_P133_PFC_02_TRACEDATA7      = (0x02U << IOPORT_PFC_OFFSET), ///< P13_3 / TRACE / TRACEDATA7
+    IOPORT_PIN_P133_PFC_03_D8              = (0x03U << IOPORT_PFC_OFFSET), ///< P13_3 / BSC / D8
+    IOPORT_PIN_P133_PFC_04_ESC_I2CDATA     = (0x04U << IOPORT_PFC_OFFSET), ///< P13_3 / ETHER_ESC / ESC_I2CDATA
+    IOPORT_PIN_P133_PFC_05_MTIOC0C         = (0x05U << IOPORT_PFC_OFFSET), ///< P13_3 / MTU3n / MTIOC0C
+    IOPORT_PIN_P133_PFC_06_MTIOC0B         = (0x06U << IOPORT_PFC_OFFSET), ///< P13_3 / MTU3n / MTIOC0B
+    IOPORT_PIN_P133_PFC_07_GTIOC10B        = (0x07U << IOPORT_PFC_OFFSET), ///< P13_3 / GPTn / GTIOC10B
+    IOPORT_PIN_P133_PFC_08_CMTW1_TOC0      = (0x08U << IOPORT_PFC_OFFSET), ///< P13_3 / CMTWn / CMTW1_TOC0
+    IOPORT_PIN_P133_PFC_09_CTS1            = (0x09U << IOPORT_PFC_OFFSET), ///< P13_3 / SCIn / CTS1
+    IOPORT_PIN_P133_PFC_0A_SPI_RSPCK0      = (0x0AU << IOPORT_PFC_OFFSET), ///< P13_3 / SPIn / SPI_RSPCK0
+    IOPORT_PIN_P133_PFC_0B_IIC_SDA0        = (0x0BU << IOPORT_PFC_OFFSET), ///< P13_3 / IICn / IIC_SDA0
+    IOPORT_PIN_P133_PFC_0C_MDAT4           = (0x0CU << IOPORT_PFC_OFFSET), ///< P13_3 / DSMIFn / MDAT4
+    IOPORT_PIN_P133_PFC_0E_RD              = (0x0EU << IOPORT_PFC_OFFSET), ///< P13_3 / BSC / RD
+    IOPORT_PIN_P134_PFC_01_ESC_RESETOUT    = (0x01U << IOPORT_PFC_OFFSET), ///< P13_4 / ETHER_ESC / ESC_RESETOUT
+    IOPORT_PIN_P134_PFC_02_MTIOC0D         = (0x02U << IOPORT_PFC_OFFSET), ///< P13_4 / MTU3n / MTIOC0D
+    IOPORT_PIN_P134_PFC_03_GTIOC8B         = (0x03U << IOPORT_PFC_OFFSET), ///< P13_4 / GPTn / GTIOC8B
+    IOPORT_PIN_P134_PFC_05_A0              = (0x05U << IOPORT_PFC_OFFSET), ///< P13_4 / BSC / A0
+    IOPORT_PIN_P135_PFC_00_XSPI0_WP1       = (0x00U << IOPORT_PFC_OFFSET), ///< P13_5 / XSPIn / XSPI0_WP1
+    IOPORT_PIN_P135_PFC_01_GMAC_PTPTRG0    = (0x01U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_GMAC / GMAC_PTPTRG0
+    IOPORT_PIN_P135_PFC_02_ESC_LATCH0      = (0x02U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_ESC / ESC_LATCH0
+    IOPORT_PIN_P135_PFC_03_ESC_LATCH1      = (0x03U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_ESC / ESC_LATCH1
+    IOPORT_PIN_P135_PFC_04_MTCLKA          = (0x04U << IOPORT_PFC_OFFSET), ///< P13_5 / MTU3 / MTCLKA
+    IOPORT_PIN_P135_PFC_05_SPI_RSPCK1      = (0x05U << IOPORT_PFC_OFFSET), ///< P13_5 / SPIn / SPI_RSPCK1
+    IOPORT_PIN_P135_PFC_06_IIC_SCL2        = (0x06U << IOPORT_PFC_OFFSET), ///< P13_5 / IICn / IIC_SCL2
+    IOPORT_PIN_P136_PFC_00_XSPI0_WP0       = (0x00U << IOPORT_PFC_OFFSET), ///< P13_6 / XSPIn / XSPI0_WP0
+    IOPORT_PIN_P136_PFC_01_ETHSW_PTPOUT0   = (0x01U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ETHSW / ETHSW_PTPOUT0
+    IOPORT_PIN_P136_PFC_02_ESC_SYNC0       = (0x02U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ESC / ESC_SYNC0
+    IOPORT_PIN_P136_PFC_03_ESC_SYNC1       = (0x03U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ESC / ESC_SYNC1
+    IOPORT_PIN_P136_PFC_04_MTCLKB          = (0x04U << IOPORT_PFC_OFFSET), ///< P13_6 / MTU3 / MTCLKB
+    IOPORT_PIN_P137_PFC_00_XSPI0_ECS1      = (0x00U << IOPORT_PFC_OFFSET), ///< P13_7 / XSPIn / XSPI0_ECS1
+    IOPORT_PIN_P137_PFC_01_GMAC_PTPTRG1    = (0x01U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_GMAC / GMAC_PTPTRG1
+    IOPORT_PIN_P137_PFC_02_ESC_LATCH1      = (0x02U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_ESC / ESC_LATCH1
+    IOPORT_PIN_P137_PFC_03_ESC_LATCH0      = (0x03U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_ESC / ESC_LATCH0
+    IOPORT_PIN_P137_PFC_04_MTCLKC          = (0x04U << IOPORT_PFC_OFFSET), ///< P13_7 / MTU3 / MTCLKC
+    IOPORT_PIN_P137_PFC_05_MBX_HINT        = (0x05U << IOPORT_PFC_OFFSET), ///< P13_7 / MBXSEM / MBX_HINT
+    IOPORT_PIN_P140_PFC_00_XSPI0_INT0      = (0x00U << IOPORT_PFC_OFFSET), ///< P14_0 / XSPIn / XSPI0_INT0
+    IOPORT_PIN_P140_PFC_01_ETHSW_PTPOUT1   = (0x01U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ETHSW / ETHSW_PTPOUT1
+    IOPORT_PIN_P140_PFC_02_ESC_SYNC1       = (0x02U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ESC / ESC_SYNC1
+    IOPORT_PIN_P140_PFC_03_ESC_SYNC0       = (0x03U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ESC / ESC_SYNC0
+    IOPORT_PIN_P140_PFC_04_MTCLKD          = (0x04U << IOPORT_PFC_OFFSET), ///< P14_0 / MTU3 / MTCLKD
+    IOPORT_PIN_P141_PFC_00_XSPI0_INT1      = (0x00U << IOPORT_PFC_OFFSET), ///< P14_1 / XSPIn / XSPI0_INT1
+    IOPORT_PIN_P141_PFC_01_ETH1_COL        = (0x01U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ETHn / ETH1_COL
+    IOPORT_PIN_P141_PFC_03_MTIOC8A         = (0x03U << IOPORT_PFC_OFFSET), ///< P14_1 / MTU3n / MTIOC8A
+    IOPORT_PIN_P141_PFC_04_GTIOC8A         = (0x04U << IOPORT_PFC_OFFSET), ///< P14_1 / GPTn / GTIOC8A
+    IOPORT_PIN_P141_PFC_06_GMAC_PTPTRG1    = (0x06U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_GMAC / GMAC_PTPTRG1
+    IOPORT_PIN_P141_PFC_07_ESC_LATCH0      = (0x07U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ESC / ESC_LATCH0
+    IOPORT_PIN_P141_PFC_08_ESC_LATCH1      = (0x08U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ESC / ESC_LATCH1
+    IOPORT_PIN_P141_PFC_09_HSPI_IO0        = (0x09U << IOPORT_PFC_OFFSET), ///< P14_1 / SHOSTIF / HSPI_IO0
+    IOPORT_PIN_P142_PFC_00_IRQ6            = (0x00U << IOPORT_PFC_OFFSET), ///< P14_2 / IRQ / IRQ6
+    IOPORT_PIN_P142_PFC_01_XSPI0_ECS0      = (0x01U << IOPORT_PFC_OFFSET), ///< P14_2 / XSPIn / XSPI0_ECS0
+    IOPORT_PIN_P142_PFC_02_ETH0_CRS        = (0x02U << IOPORT_PFC_OFFSET), ///< P14_2 / ETHER_ETHn / ETH0_CRS
+    IOPORT_PIN_P142_PFC_04_MTIOC8B         = (0x04U << IOPORT_PFC_OFFSET), ///< P14_2 / MTU3n / MTIOC8B
+    IOPORT_PIN_P142_PFC_05_GTIOC8B         = (0x05U << IOPORT_PFC_OFFSET), ///< P14_2 / GPTn / GTIOC8B
+    IOPORT_PIN_P142_PFC_07_ETH2_CRS        = (0x07U << IOPORT_PFC_OFFSET), ///< P14_2 / ETHER_ETHn / ETH2_CRS
+    IOPORT_PIN_P142_PFC_08_HSPI_CK         = (0x08U << IOPORT_PFC_OFFSET), ///< P14_2 / SHOSTIF / HSPI_CK
+    IOPORT_PIN_P143_PFC_00_XSPI0_RSTO1     = (0x00U << IOPORT_PFC_OFFSET), ///< P14_3 / XSPIn / XSPI0_RSTO1
+    IOPORT_PIN_P143_PFC_01_ETH0_COL        = (0x01U << IOPORT_PFC_OFFSET), ///< P14_3 / ETHER_ETHn / ETH0_COL
+    IOPORT_PIN_P143_PFC_04_MTIOC0A         = (0x04U << IOPORT_PFC_OFFSET), ///< P14_3 / MTU3n / MTIOC0A
+    IOPORT_PIN_P143_PFC_06_ETH2_COL        = (0x06U << IOPORT_PFC_OFFSET), ///< P14_3 / ETHER_ETHn / ETH2_COL
+    IOPORT_PIN_P143_PFC_07_HSPI_IO1        = (0x07U << IOPORT_PFC_OFFSET), ///< P14_3 / SHOSTIF / HSPI_IO1
+    IOPORT_PIN_P144_PFC_00_XSPI0_DS        = (0x00U << IOPORT_PFC_OFFSET), ///< P14_4 / XSPIn / XSPI0_DS
+    IOPORT_PIN_P144_PFC_01_BS              = (0x01U << IOPORT_PFC_OFFSET), ///< P14_4 / BSC / BS
+    IOPORT_PIN_P144_PFC_02_ESC_IRQ         = (0x02U << IOPORT_PFC_OFFSET), ///< P14_4 / ETHER_ESC / ESC_IRQ
+    IOPORT_PIN_P144_PFC_03_MTIOC0B         = (0x03U << IOPORT_PFC_OFFSET), ///< P14_4 / MTU3n / MTIOC0B
+    IOPORT_PIN_P144_PFC_04_HBS             = (0x04U << IOPORT_PFC_OFFSET), ///< P14_4 / PHOSTIF / HBS
+    IOPORT_PIN_P145_PFC_00_XSPI0_CKN       = (0x00U << IOPORT_PFC_OFFSET), ///< P14_5 / XSPIn / XSPI0_CKN
+    IOPORT_PIN_P145_PFC_01_CS3             = (0x01U << IOPORT_PFC_OFFSET), ///< P14_5 / BSC / CS3
+    IOPORT_PIN_P145_PFC_02_POE8            = (0x02U << IOPORT_PFC_OFFSET), ///< P14_5 / MTU_POE3 / POE8
+    IOPORT_PIN_P145_PFC_03_HSPI_INT        = (0x03U << IOPORT_PFC_OFFSET), ///< P14_5 / SHOSTIF / HSPI_INT
+    IOPORT_PIN_P146_PFC_00_XSPI0_CKP       = (0x00U << IOPORT_PFC_OFFSET), ///< P14_6 / XSPIn / XSPI0_CKP
+    IOPORT_PIN_P146_PFC_01_A21             = (0x01U << IOPORT_PFC_OFFSET), ///< P14_6 / BSC / A21
+    IOPORT_PIN_P147_PFC_00_XSPI0_IO0       = (0x00U << IOPORT_PFC_OFFSET), ///< P14_7 / XSPIn / XSPI0_IO0
+    IOPORT_PIN_P147_PFC_01_A22             = (0x01U << IOPORT_PFC_OFFSET), ///< P14_7 / BSC / A22
+    IOPORT_PIN_P147_PFC_02_SCK5            = (0x02U << IOPORT_PFC_OFFSET), ///< P14_7 / SCIn / SCK5
+    IOPORT_PIN_P147_PFC_03_SPI_MISO1       = (0x03U << IOPORT_PFC_OFFSET), ///< P14_7 / SPIn / SPI_MISO1
+    IOPORT_PIN_P147_PFC_04_BS              = (0x04U << IOPORT_PFC_OFFSET), ///< P14_7 / BSC / BS
+    IOPORT_PIN_P150_PFC_00_XSPI0_IO1       = (0x00U << IOPORT_PFC_OFFSET), ///< P15_0 / XSPIn / XSPI0_IO1
+    IOPORT_PIN_P150_PFC_01_A23             = (0x01U << IOPORT_PFC_OFFSET), ///< P15_0 / BSC / A23
+    IOPORT_PIN_P150_PFC_02_RXD5_SCL5_MISO5 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_0 / SCIn / RXD5_SCL5_MISO5
+    IOPORT_PIN_P150_PFC_03_SPI_MOSI1       = (0x03U << IOPORT_PFC_OFFSET), ///< P15_0 / SPIn / SPI_MOSI1
+    IOPORT_PIN_P150_PFC_04_CKE             = (0x04U << IOPORT_PFC_OFFSET), ///< P15_0 / BSC / CKE
+    IOPORT_PIN_P151_PFC_00_XSPI0_IO2       = (0x00U << IOPORT_PFC_OFFSET), ///< P15_1 / XSPIn / XSPI0_IO2
+    IOPORT_PIN_P151_PFC_01_A24             = (0x01U << IOPORT_PFC_OFFSET), ///< P15_1 / BSC / A24
+    IOPORT_PIN_P151_PFC_02_MTIOC0C         = (0x02U << IOPORT_PFC_OFFSET), ///< P15_1 / MTU3n / MTIOC0C
+    IOPORT_PIN_P151_PFC_03_TXD5_SDA5_MOSI5 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_1 / SCIn / TXD5_SDA5_MOSI5
+    IOPORT_PIN_P151_PFC_04_SPI_SSL10       = (0x04U << IOPORT_PFC_OFFSET), ///< P15_1 / SPIn / SPI_SSL10
+    IOPORT_PIN_P151_PFC_05_CAS             = (0x05U << IOPORT_PFC_OFFSET), ///< P15_1 / BSC / CAS
+    IOPORT_PIN_P152_PFC_00_XSPI0_IO3       = (0x00U << IOPORT_PFC_OFFSET), ///< P15_2 / XSPIn / XSPI0_IO3
+    IOPORT_PIN_P152_PFC_01_A25             = (0x01U << IOPORT_PFC_OFFSET), ///< P15_2 / BSC / A25
+    IOPORT_PIN_P152_PFC_02_MTIOC0D         = (0x02U << IOPORT_PFC_OFFSET), ///< P15_2 / MTU3n / MTIOC0D
+    IOPORT_PIN_P152_PFC_03_SS5_CTS5_RTS5   = (0x03U << IOPORT_PFC_OFFSET), ///< P15_2 / SCIn / SS5_CTS5_RTS5
+    IOPORT_PIN_P152_PFC_04_SPI_SSL11       = (0x04U << IOPORT_PFC_OFFSET), ///< P15_2 / SPIn / SPI_SSL11
+    IOPORT_PIN_P152_PFC_05_RAS             = (0x05U << IOPORT_PFC_OFFSET), ///< P15_2 / BSC / RAS
+    IOPORT_PIN_P153_PFC_00_XSPI0_IO4       = (0x00U << IOPORT_PFC_OFFSET), ///< P15_3 / XSPIn / XSPI0_IO4
+    IOPORT_PIN_P153_PFC_01_MTIOC8C         = (0x01U << IOPORT_PFC_OFFSET), ///< P15_3 / MTU3n / MTIOC8C
+    IOPORT_PIN_P153_PFC_02_MCLK1           = (0x02U << IOPORT_PFC_OFFSET), ///< P15_3 / DSMIFn / MCLK1
+    IOPORT_PIN_P153_PFC_03_D11             = (0x03U << IOPORT_PFC_OFFSET), ///< P15_3 / BSC / D11
+    IOPORT_PIN_P154_PFC_00_XSPI0_IO5       = (0x00U << IOPORT_PFC_OFFSET), ///< P15_4 / XSPIn / XSPI0_IO5
+    IOPORT_PIN_P154_PFC_01_MTIOC8D         = (0x01U << IOPORT_PFC_OFFSET), ///< P15_4 / MTU3n / MTIOC8D
+    IOPORT_PIN_P154_PFC_02_MDAT1           = (0x02U << IOPORT_PFC_OFFSET), ///< P15_4 / DSMIFn / MDAT1
+    IOPORT_PIN_P154_PFC_03_D12             = (0x03U << IOPORT_PFC_OFFSET), ///< P15_4 / BSC / D12
+    IOPORT_PIN_P155_PFC_00_XSPI0_IO6       = (0x00U << IOPORT_PFC_OFFSET), ///< P15_5 / XSPIn / XSPI0_IO6
+    IOPORT_PIN_P155_PFC_01_MCLK2           = (0x01U << IOPORT_PFC_OFFSET), ///< P15_5 / DSMIFn / MCLK2
+    IOPORT_PIN_P155_PFC_02_D13             = (0x02U << IOPORT_PFC_OFFSET), ///< P15_5 / BSC / D13
+    IOPORT_PIN_P156_PFC_00_XSPI0_IO7       = (0x00U << IOPORT_PFC_OFFSET), ///< P15_6 / XSPIn / XSPI0_IO7
+    IOPORT_PIN_P156_PFC_01_SPI_SSL12       = (0x01U << IOPORT_PFC_OFFSET), ///< P15_6 / SPIn / SPI_SSL12
+    IOPORT_PIN_P156_PFC_02_MDAT2           = (0x02U << IOPORT_PFC_OFFSET), ///< P15_6 / DSMIFn / MDAT2
+    IOPORT_PIN_P156_PFC_03_D14             = (0x03U << IOPORT_PFC_OFFSET), ///< P15_6 / BSC / D14
+    IOPORT_PIN_P157_PFC_00_XSPI0_CS0       = (0x00U << IOPORT_PFC_OFFSET), ///< P15_7 / XSPIn / XSPI0_CS0
+    IOPORT_PIN_P157_PFC_01_CTS5            = (0x01U << IOPORT_PFC_OFFSET), ///< P15_7 / SCIn / CTS5
+    IOPORT_PIN_P157_PFC_02_SPI_SSL13       = (0x02U << IOPORT_PFC_OFFSET), ///< P15_7 / SPIn / SPI_SSL13
+    IOPORT_PIN_P157_PFC_03_TEND            = (0x03U << IOPORT_PFC_OFFSET), ///< P15_7 / DMAC / TEND
+    IOPORT_PIN_P160_PFC_00_XSPI0_CS1       = (0x00U << IOPORT_PFC_OFFSET), ///< P16_0 / XSPIn / XSPI0_CS1
+    IOPORT_PIN_P160_PFC_01_ETH0_TXER       = (0x01U << IOPORT_PFC_OFFSET), ///< P16_0 / ETHER_ETHn / ETH0_TXER
+    IOPORT_PIN_P160_PFC_02_TXD0_SDA0_MOSI0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_0 / SCIn / TXD0_SDA0_MOSI0
+    IOPORT_PIN_P160_PFC_03_SPI_MOSI3       = (0x03U << IOPORT_PFC_OFFSET), ///< P16_0 / SPIn / SPI_MOSI3
+    IOPORT_PIN_P160_PFC_04_MCLK3           = (0x04U << IOPORT_PFC_OFFSET), ///< P16_0 / DSMIFn / MCLK3
+    IOPORT_PIN_P160_PFC_06_ETH2_REFCLK     = (0x06U << IOPORT_PFC_OFFSET), ///< P16_0 / ETHER_ETHn / ETH2_REFCLK
+    IOPORT_PIN_P160_PFC_07_HSPI_CS         = (0x07U << IOPORT_PFC_OFFSET), ///< P16_0 / SHOSTIF / HSPI_CS
+    IOPORT_PIN_P161_PFC_00_XSPI0_RESET0    = (0x00U << IOPORT_PFC_OFFSET), ///< P16_1 / XSPIn / XSPI0_RESET0
+    IOPORT_PIN_P161_PFC_01_CMTW0_TOC1      = (0x01U << IOPORT_PFC_OFFSET), ///< P16_1 / CMTWn / CMTW0_TOC1
+    IOPORT_PIN_P161_PFC_02_ADTRG0          = (0x02U << IOPORT_PFC_OFFSET), ///< P16_1 / ADCn / ADTRG0
+    IOPORT_PIN_P161_PFC_03_RXD0_SCL0_MISO0 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_1 / SCIn / RXD0_SCL0_MISO0
+    IOPORT_PIN_P161_PFC_04_SPI_MISO3       = (0x04U << IOPORT_PFC_OFFSET), ///< P16_1 / SPIn / SPI_MISO3
+    IOPORT_PIN_P161_PFC_05_MDAT3           = (0x05U << IOPORT_PFC_OFFSET), ///< P16_1 / DSMIFn / MDAT3
+    IOPORT_PIN_P161_PFC_07_CS2             = (0x07U << IOPORT_PFC_OFFSET), ///< P16_1 / BSC / CS2
+    IOPORT_PIN_P161_PFC_08_HCS1            = (0x08U << IOPORT_PFC_OFFSET), ///< P16_1 / PHOSTIF / HCS1
+    IOPORT_PIN_P162_PFC_00_NMI             = (0x00U << IOPORT_PFC_OFFSET), ///< P16_2 / IRQ / NMI
+    IOPORT_PIN_P162_PFC_01_XSPI0_RESET1    = (0x01U << IOPORT_PFC_OFFSET), ///< P16_2 / XSPIn / XSPI0_RESET1
+    IOPORT_PIN_P162_PFC_02_CTS0            = (0x02U << IOPORT_PFC_OFFSET), ///< P16_2 / SCIn / CTS0
+    IOPORT_PIN_P162_PFC_03_SPI_RSPCK3      = (0x03U << IOPORT_PFC_OFFSET), ///< P16_2 / SPIn / SPI_RSPCK3
+    IOPORT_PIN_P162_PFC_04_USB_EXICEN      = (0x04U << IOPORT_PFC_OFFSET), ///< P16_2 / USB_HS / USB_EXICEN
+    IOPORT_PIN_P162_PFC_06_HSPI_IO2        = (0x06U << IOPORT_PFC_OFFSET), ///< P16_2 / SHOSTIF / HSPI_IO2
+    IOPORT_PIN_P162_PFC_07_HERROUT         = (0x07U << IOPORT_PFC_OFFSET), ///< P16_2 / PHOSTIF / HERROUT
+    IOPORT_PIN_P163_PFC_00_IRQ7            = (0x00U << IOPORT_PFC_OFFSET), ///< P16_3 / IRQ / IRQ7
+    IOPORT_PIN_P163_PFC_01_XSPI0_RSTO0     = (0x01U << IOPORT_PFC_OFFSET), ///< P16_3 / XSPIn / XSPI0_RSTO0
+    IOPORT_PIN_P163_PFC_02_ETH1_TXER       = (0x02U << IOPORT_PFC_OFFSET), ///< P16_3 / ETHER_ETHn / ETH1_TXER
+    IOPORT_PIN_P163_PFC_03_GTADSMP1        = (0x03U << IOPORT_PFC_OFFSET), ///< P16_3 / GPT / GTADSMP1
+    IOPORT_PIN_P163_PFC_04_SCK0            = (0x04U << IOPORT_PFC_OFFSET), ///< P16_3 / SCIn / SCK0
+    IOPORT_PIN_P163_PFC_05_SPI_SSL30       = (0x05U << IOPORT_PFC_OFFSET), ///< P16_3 / SPIn / SPI_SSL30
+    IOPORT_PIN_P163_PFC_07_ETH1_CRS        = (0x07U << IOPORT_PFC_OFFSET), ///< P16_3 / ETHER_ETHn / ETH1_CRS
+    IOPORT_PIN_P163_PFC_08_CS3             = (0x08U << IOPORT_PFC_OFFSET), ///< P16_3 / BSC / CS3
+    IOPORT_PIN_P163_PFC_09_HSPI_IO3        = (0x09U << IOPORT_PFC_OFFSET), ///< P16_3 / SHOSTIF / HSPI_IO3
+    IOPORT_PIN_P165_PFC_00_MTIC5U          = (0x00U << IOPORT_PFC_OFFSET), ///< P16_5 / MTU3n / MTIC5U
+    IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_5 / SCIn / TXD0_SDA0_MOSI0
+    IOPORT_PIN_P165_PFC_02_A15             = (0x02U << IOPORT_PFC_OFFSET), ///< P16_5 / BSC / A15
+    IOPORT_PIN_P165_PFC_03_HSPI_IO4        = (0x03U << IOPORT_PFC_OFFSET), ///< P16_5 / SHOSTIF / HSPI_IO4
+    IOPORT_PIN_P166_PFC_00_IRQ8            = (0x00U << IOPORT_PFC_OFFSET), ///< P16_6 / IRQ / IRQ8
+    IOPORT_PIN_P166_PFC_01_MTIC5V          = (0x01U << IOPORT_PFC_OFFSET), ///< P16_6 / MTU3n / MTIC5V
+    IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_6 / SCIn / RXD0_SCL0_MISO0
+    IOPORT_PIN_P166_PFC_03_CS0             = (0x03U << IOPORT_PFC_OFFSET), ///< P16_6 / BSC / CS0
+    IOPORT_PIN_P166_PFC_04_HSPI_IO5        = (0x04U << IOPORT_PFC_OFFSET), ///< P16_6 / SHOSTIF / HSPI_IO5
+    IOPORT_PIN_P166_PFC_05_HCS0            = (0x05U << IOPORT_PFC_OFFSET), ///< P16_6 / PHOSTIF / HCS0
+    IOPORT_PIN_P167_PFC_00_MTIC5W          = (0x00U << IOPORT_PFC_OFFSET), ///< P16_7 / MTU3n / MTIC5W
+    IOPORT_PIN_P167_PFC_01_SCK0            = (0x01U << IOPORT_PFC_OFFSET), ///< P16_7 / SCIn / SCK0
+    IOPORT_PIN_P167_PFC_02_XSPI1_IO0       = (0x02U << IOPORT_PFC_OFFSET), ///< P16_7 / XSPIn / XSPI1_IO0
+    IOPORT_PIN_P167_PFC_03_A13             = (0x03U << IOPORT_PFC_OFFSET), ///< P16_7 / BSC / A13
+    IOPORT_PIN_P167_PFC_04_HA13            = (0x04U << IOPORT_PFC_OFFSET), ///< P16_7 / PHOSTIF / HA13
+    IOPORT_PIN_P170_PFC_00_ESC_IRQ         = (0x00U << IOPORT_PFC_OFFSET), ///< P17_0 / ETHER_ESC / ESC_IRQ
+    IOPORT_PIN_P170_PFC_01_SS0_CTS0_RTS0   = (0x01U << IOPORT_PFC_OFFSET), ///< P17_0 / SCIn / SS0_CTS0_RTS0
+    IOPORT_PIN_P170_PFC_02_XSPI1_IO1       = (0x02U << IOPORT_PFC_OFFSET), ///< P17_0 / XSPIn / XSPI1_IO1
+    IOPORT_PIN_P173_PFC_00_TRACECTL        = (0x00U << IOPORT_PFC_OFFSET), ///< P17_3 / TRACE / TRACECTL
+    IOPORT_PIN_P173_PFC_01_GTETRGA         = (0x01U << IOPORT_PFC_OFFSET), ///< P17_3 / GPT_POEG / GTETRGA
+    IOPORT_PIN_P173_PFC_02_POE0            = (0x02U << IOPORT_PFC_OFFSET), ///< P17_3 / MTU_POE3 / POE0
+    IOPORT_PIN_P173_PFC_03_ADTRG1          = (0x03U << IOPORT_PFC_OFFSET), ///< P17_3 / ADCn / ADTRG1
+    IOPORT_PIN_P173_PFC_04_SPI_SSL31       = (0x04U << IOPORT_PFC_OFFSET), ///< P17_3 / SPIn / SPI_SSL31
+    IOPORT_PIN_P173_PFC_05_DREQ            = (0x05U << IOPORT_PFC_OFFSET), ///< P17_3 / DMAC / DREQ
+    IOPORT_PIN_P173_PFC_07_XSPI1_IO2       = (0x07U << IOPORT_PFC_OFFSET), ///< P17_3 / XSPIn / XSPI1_IO2
+    IOPORT_PIN_P174_PFC_00_TRACECLK        = (0x00U << IOPORT_PFC_OFFSET), ///< P17_4 / TRACE / TRACECLK
+    IOPORT_PIN_P174_PFC_01_MTIOC3C         = (0x01U << IOPORT_PFC_OFFSET), ///< P17_4 / MTU3n / MTIOC3C
+    IOPORT_PIN_P174_PFC_02_GTETRGB         = (0x02U << IOPORT_PFC_OFFSET), ///< P17_4 / GPT_POEG / GTETRGB
+    IOPORT_PIN_P174_PFC_03_GTIOC0A         = (0x03U << IOPORT_PFC_OFFSET), ///< P17_4 / GPTn / GTIOC0A
+    IOPORT_PIN_P174_PFC_04_CTS3            = (0x04U << IOPORT_PFC_OFFSET), ///< P17_4 / SCIn / CTS3
+    IOPORT_PIN_P174_PFC_05_SPI_SSL32       = (0x05U << IOPORT_PFC_OFFSET), ///< P17_4 / SPIn / SPI_SSL32
+    IOPORT_PIN_P174_PFC_07_XSPI1_IO3       = (0x07U << IOPORT_PFC_OFFSET), ///< P17_4 / XSPIn / XSPI1_IO3
+    IOPORT_PIN_P174_PFC_08_DACK            = (0x08U << IOPORT_PFC_OFFSET), ///< P17_4 / DMAC / DACK
+    IOPORT_PIN_P175_PFC_01_MTIOC3A         = (0x01U << IOPORT_PFC_OFFSET), ///< P17_5 / MTU3n / MTIOC3A
+    IOPORT_PIN_P175_PFC_02_GTETRGC         = (0x02U << IOPORT_PFC_OFFSET), ///< P17_5 / GPT_POEG / GTETRGC
+    IOPORT_PIN_P175_PFC_03_GTIOC0B         = (0x03U << IOPORT_PFC_OFFSET), ///< P17_5 / GPTn / GTIOC0B
+    IOPORT_PIN_P175_PFC_04_TEND            = (0x04U << IOPORT_PFC_OFFSET), ///< P17_5 / DMAC / TEND
+    IOPORT_PIN_P175_PFC_05_USB_OVRCUR      = (0x05U << IOPORT_PFC_OFFSET), ///< P17_5 / USB_HS / USB_OVRCUR
+    IOPORT_PIN_P176_PFC_00_MTIOC3B         = (0x00U << IOPORT_PFC_OFFSET), ///< P17_6 / MTU3n / MTIOC3B
+    IOPORT_PIN_P176_PFC_01_GTIOC1A         = (0x01U << IOPORT_PFC_OFFSET), ///< P17_6 / GPTn / GTIOC1A
+    IOPORT_PIN_P176_PFC_02_SCK3            = (0x02U << IOPORT_PFC_OFFSET), ///< P17_6 / SCIn / SCK3
+    IOPORT_PIN_P176_PFC_04_XSPI1_DS        = (0x04U << IOPORT_PFC_OFFSET), ///< P17_6 / XSPIn / XSPI1_DS
+    IOPORT_PIN_P176_PFC_05_RD_WR           = (0x05U << IOPORT_PFC_OFFSET), ///< P17_6 / BSC / RD_WR
+    IOPORT_PIN_P176_PFC_06_HWRSTB          = (0x06U << IOPORT_PFC_OFFSET), ///< P17_6 / PHOSTIF / HWRSTB
+    IOPORT_PIN_P177_PFC_00_MTIOC4A         = (0x00U << IOPORT_PFC_OFFSET), ///< P17_7 / MTU3n / MTIOC4A
+    IOPORT_PIN_P177_PFC_01_MTIOC4C         = (0x01U << IOPORT_PFC_OFFSET), ///< P17_7 / MTU3n / MTIOC4C
+    IOPORT_PIN_P177_PFC_02_GTIOC2A         = (0x02U << IOPORT_PFC_OFFSET), ///< P17_7 / GPTn / GTIOC2A
+    IOPORT_PIN_P177_PFC_03_GTIOC3A         = (0x03U << IOPORT_PFC_OFFSET), ///< P17_7 / GPTn / GTIOC3A
+    IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_7 / SCIn / RXD3_SCL3_MISO3
+    IOPORT_PIN_P177_PFC_05_DACK            = (0x05U << IOPORT_PFC_OFFSET), ///< P17_7 / DMAC / DACK
+    IOPORT_PIN_P177_PFC_07_XSPI1_CKP       = (0x07U << IOPORT_PFC_OFFSET), ///< P17_7 / XSPIn / XSPI1_CKP
+    IOPORT_PIN_P177_PFC_08_RD              = (0x08U << IOPORT_PFC_OFFSET), ///< P17_7 / BSC / RD
+    IOPORT_PIN_P177_PFC_09_HRD             = (0x09U << IOPORT_PFC_OFFSET), ///< P17_7 / PHOSTIF / HRD
+    IOPORT_PIN_P180_PFC_00_MTIOC4C         = (0x00U << IOPORT_PFC_OFFSET), ///< P18_0 / MTU3n / MTIOC4C
+    IOPORT_PIN_P180_PFC_01_MTIOC4A         = (0x01U << IOPORT_PFC_OFFSET), ///< P18_0 / MTU3n / MTIOC4A
+    IOPORT_PIN_P180_PFC_02_GTIOC3A         = (0x02U << IOPORT_PFC_OFFSET), ///< P18_0 / GPTn / GTIOC3A
+    IOPORT_PIN_P180_PFC_03_GTIOC2A         = (0x03U << IOPORT_PFC_OFFSET), ///< P18_0 / GPTn / GTIOC2A
+    IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_0 / SCIn / TXD3_SDA3_MOSI3
+    IOPORT_PIN_P180_PFC_05_WE0_DQMLL       = (0x05U << IOPORT_PFC_OFFSET), ///< P18_0 / BSC / WE0_DQMLL
+    IOPORT_PIN_P180_PFC_06_HSPI_IO6        = (0x06U << IOPORT_PFC_OFFSET), ///< P18_0 / SHOSTIF / HSPI_IO6
+    IOPORT_PIN_P180_PFC_07_HWR0            = (0x07U << IOPORT_PFC_OFFSET), ///< P18_0 / PHOSTIF / HWR0
+    IOPORT_PIN_P181_PFC_00_IRQ10           = (0x00U << IOPORT_PFC_OFFSET), ///< P18_1 / IRQ / IRQ10
+    IOPORT_PIN_P181_PFC_01_MTIOC3D         = (0x01U << IOPORT_PFC_OFFSET), ///< P18_1 / MTU3n / MTIOC3D
+    IOPORT_PIN_P181_PFC_02_GTIOC1B         = (0x02U << IOPORT_PFC_OFFSET), ///< P18_1 / GPTn / GTIOC1B
+    IOPORT_PIN_P181_PFC_03_ADTRG1          = (0x03U << IOPORT_PFC_OFFSET), ///< P18_1 / ADCn / ADTRG1
+    IOPORT_PIN_P181_PFC_04_SS3_CTS3_RTS3   = (0x04U << IOPORT_PFC_OFFSET), ///< P18_1 / SCIn / SS3_CTS3_RTS3
+    IOPORT_PIN_P181_PFC_06_WE1_DQMLU       = (0x06U << IOPORT_PFC_OFFSET), ///< P18_1 / BSC / WE1_DQMLU
+    IOPORT_PIN_P181_PFC_07_HSPI_IO7        = (0x07U << IOPORT_PFC_OFFSET), ///< P18_1 / SHOSTIF / HSPI_IO7
+    IOPORT_PIN_P181_PFC_08_HWR1            = (0x08U << IOPORT_PFC_OFFSET), ///< P18_1 / PHOSTIF / HWR1
+    IOPORT_PIN_P182_PFC_00_MTIOC4B         = (0x00U << IOPORT_PFC_OFFSET), ///< P18_2 / MTU3n / MTIOC4B
+    IOPORT_PIN_P182_PFC_01_MTIOC4D         = (0x01U << IOPORT_PFC_OFFSET), ///< P18_2 / MTU3n / MTIOC4D
+    IOPORT_PIN_P182_PFC_02_GTIOC2B         = (0x02U << IOPORT_PFC_OFFSET), ///< P18_2 / GPTn / GTIOC2B
+    IOPORT_PIN_P182_PFC_03_GTIOC3B         = (0x03U << IOPORT_PFC_OFFSET), ///< P18_2 / GPTn / GTIOC3B
+    IOPORT_PIN_P182_PFC_05_XSPI1_CS0       = (0x05U << IOPORT_PFC_OFFSET), ///< P18_2 / XSPIn / XSPI1_CS0
+    IOPORT_PIN_P182_PFC_06_ETH1_COL        = (0x06U << IOPORT_PFC_OFFSET), ///< P18_2 / ETHER_ETHn / ETH1_COL
+    IOPORT_PIN_P182_PFC_07_BS              = (0x07U << IOPORT_PFC_OFFSET), ///< P18_2 / BSC / BS
+    IOPORT_PIN_P182_PFC_08_SCK0            = (0x08U << IOPORT_PFC_OFFSET), ///< P18_2 / SCIn / SCK0
+    IOPORT_PIN_P182_PFC_09_IIC_SDA2        = (0x09U << IOPORT_PFC_OFFSET), ///< P18_2 / IICn / IIC_SDA2
+    IOPORT_PIN_P183_PFC_00_IRQ0            = (0x00U << IOPORT_PFC_OFFSET), ///< P18_3 / IRQ / IRQ0
+    IOPORT_PIN_P183_PFC_01_MTIOC4D         = (0x01U << IOPORT_PFC_OFFSET), ///< P18_3 / MTU3n / MTIOC4D
+    IOPORT_PIN_P183_PFC_02_MTIOC4B         = (0x02U << IOPORT_PFC_OFFSET), ///< P18_3 / MTU3n / MTIOC4B
+    IOPORT_PIN_P183_PFC_03_GTIOC3B         = (0x03U << IOPORT_PFC_OFFSET), ///< P18_3 / GPTn / GTIOC3B
+    IOPORT_PIN_P183_PFC_04_GTIOC2B         = (0x04U << IOPORT_PFC_OFFSET), ///< P18_3 / GPTn / GTIOC2B
+    IOPORT_PIN_P183_PFC_05_CMTW1_TIC1      = (0x05U << IOPORT_PFC_OFFSET), ///< P18_3 / CMTWn / CMTW1_TIC1
+    IOPORT_PIN_P183_PFC_06_CANRXDP1        = (0x06U << IOPORT_PFC_OFFSET), ///< P18_3 / CANFDn / CANRXDP1
+    IOPORT_PIN_P183_PFC_08_XSPI1_IO4       = (0x08U << IOPORT_PFC_OFFSET), ///< P18_3 / XSPIn / XSPI1_IO4
+    IOPORT_PIN_P183_PFC_09_ETH2_CRS        = (0x09U << IOPORT_PFC_OFFSET), ///< P18_3 / ETHER_ETHn / ETH2_CRS
+    IOPORT_PIN_P183_PFC_0A_CKE             = (0x0AU << IOPORT_PFC_OFFSET), ///< P18_3 / BSC / CKE
+    IOPORT_PIN_P184_PFC_00_IRQ1            = (0x00U << IOPORT_PFC_OFFSET), ///< P18_4 / IRQ / IRQ1
+    IOPORT_PIN_P184_PFC_01_MTIC5U          = (0x01U << IOPORT_PFC_OFFSET), ///< P18_4 / MTU3n / MTIC5U
+    IOPORT_PIN_P184_PFC_02_TXD4_SDA4_MOSI4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_4 / SCIn / TXD4_SDA4_MOSI4
+    IOPORT_PIN_P184_PFC_03_SPI_RSPCK2      = (0x03U << IOPORT_PFC_OFFSET), ///< P18_4 / SPIn / SPI_RSPCK2
+    IOPORT_PIN_P184_PFC_05_XSPI1_IO5       = (0x05U << IOPORT_PFC_OFFSET), ///< P18_4 / XSPIn / XSPI1_IO5
+    IOPORT_PIN_P184_PFC_06_ETH1_CRS        = (0x06U << IOPORT_PFC_OFFSET), ///< P18_4 / ETHER_ETHn / ETH1_CRS
+    IOPORT_PIN_P184_PFC_07_CAS             = (0x07U << IOPORT_PFC_OFFSET), ///< P18_4 / BSC / CAS
+    IOPORT_PIN_P184_PFC_08_CANTX0          = (0x08U << IOPORT_PFC_OFFSET), ///< P18_4 / CANFDn / CANTX0
+    IOPORT_PIN_P185_PFC_00_TRACECTL        = (0x00U << IOPORT_PFC_OFFSET), ///< P18_5 / TRACE / TRACECTL
+    IOPORT_PIN_P185_PFC_01_MTIC5V          = (0x01U << IOPORT_PFC_OFFSET), ///< P18_5 / MTU3n / MTIC5V
+    IOPORT_PIN_P185_PFC_02_RXD4_SCL4_MISO4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_5 / SCIn / RXD4_SCL4_MISO4
+    IOPORT_PIN_P185_PFC_03_SPI_MOSI2       = (0x03U << IOPORT_PFC_OFFSET), ///< P18_5 / SPIn / SPI_MOSI2
+    IOPORT_PIN_P185_PFC_05_XSPI1_IO6       = (0x05U << IOPORT_PFC_OFFSET), ///< P18_5 / XSPIn / XSPI1_IO6
+    IOPORT_PIN_P185_PFC_06_ETH2_COL        = (0x06U << IOPORT_PFC_OFFSET), ///< P18_5 / ETHER_ETHn / ETH2_COL
+    IOPORT_PIN_P185_PFC_07_RAS             = (0x07U << IOPORT_PFC_OFFSET), ///< P18_5 / BSC / RAS
+    IOPORT_PIN_P185_PFC_08_CANRX0          = (0x08U << IOPORT_PFC_OFFSET), ///< P18_5 / CANFDn / CANRX0
+    IOPORT_PIN_P186_PFC_00_IRQ11           = (0x00U << IOPORT_PFC_OFFSET), ///< P18_6 / IRQ / IRQ11
+    IOPORT_PIN_P186_PFC_01_TRACECLK        = (0x01U << IOPORT_PFC_OFFSET), ///< P18_6 / TRACE / TRACECLK
+    IOPORT_PIN_P186_PFC_02_MTIC5W          = (0x02U << IOPORT_PFC_OFFSET), ///< P18_6 / MTU3n / MTIC5W
+    IOPORT_PIN_P186_PFC_03_ADTRG0          = (0x03U << IOPORT_PFC_OFFSET), ///< P18_6 / ADCn / ADTRG0
+    IOPORT_PIN_P186_PFC_04_SCK4            = (0x04U << IOPORT_PFC_OFFSET), ///< P18_6 / SCIn / SCK4
+    IOPORT_PIN_P186_PFC_05_SPI_MISO2       = (0x05U << IOPORT_PFC_OFFSET), ///< P18_6 / SPIn / SPI_MISO2
+    IOPORT_PIN_P186_PFC_06_IIC_SCL2        = (0x06U << IOPORT_PFC_OFFSET), ///< P18_6 / IICn / IIC_SCL2
+    IOPORT_PIN_P186_PFC_08_XSPI1_IO7       = (0x08U << IOPORT_PFC_OFFSET), ///< P18_6 / XSPIn / XSPI1_IO7
+    IOPORT_PIN_P186_PFC_09_ETH1_COL        = (0x09U << IOPORT_PFC_OFFSET), ///< P18_6 / ETHER_ETHn / ETH1_COL
+    IOPORT_PIN_P186_PFC_0A_DE4             = (0x0AU << IOPORT_PFC_OFFSET), ///< P18_6 / SCIn / DE4
+    IOPORT_PIN_P190_PFC_00_USB_VBUSEN      = (0x00U << IOPORT_PFC_OFFSET), ///< P19_0 / USB_HS / USB_VBUSEN
+    IOPORT_PIN_P201_PFC_00_ETHSW_TDMAOUT0  = (0x00U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ETHSW / ETHSW_TDMAOUT0
+    IOPORT_PIN_P201_PFC_01_ESC_LINKACT0    = (0x01U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ESC / ESC_LINKACT0
+    IOPORT_PIN_P201_PFC_02_ETHSW_PTPOUT3   = (0x02U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ETHSW / ETHSW_PTPOUT3
+    IOPORT_PIN_P202_PFC_00_ETHSW_TDMAOUT1  = (0x00U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ETHSW / ETHSW_TDMAOUT1
+    IOPORT_PIN_P202_PFC_01_ESC_LEDRUN      = (0x01U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ESC / ESC_LEDRUN
+    IOPORT_PIN_P202_PFC_02_ESC_LEDSTER     = (0x02U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ESC / ESC_LEDSTER
+    IOPORT_PIN_P202_PFC_03_DE3             = (0x03U << IOPORT_PFC_OFFSET), ///< P20_2 / SCIn / DE3
+    IOPORT_PIN_P202_PFC_04_ETHSW_PTPOUT2   = (0x04U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ETHSW / ETHSW_PTPOUT2
+    IOPORT_PIN_P203_PFC_00_ETHSW_TDMAOUT2  = (0x00U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ETHSW / ETHSW_TDMAOUT2
+    IOPORT_PIN_P203_PFC_01_ESC_LEDERR      = (0x01U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ESC / ESC_LEDERR
+    IOPORT_PIN_P203_PFC_02_ETHSW_PTPOUT1   = (0x02U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ETHSW / ETHSW_PTPOUT1
+    IOPORT_PIN_P204_PFC_00_ETHSW_TDMAOUT3  = (0x00U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ETHSW / ETHSW_TDMAOUT3
+    IOPORT_PIN_P204_PFC_01_ESC_LINKACT1    = (0x01U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ESC / ESC_LINKACT1
+    IOPORT_PIN_P204_PFC_02_ETHSW_PTPOUT0   = (0x02U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ETHSW / ETHSW_PTPOUT0
+    IOPORT_PIN_P211_PFC_00_TRACEDATA0      = (0x00U << IOPORT_PFC_OFFSET), ///< P21_1 / TRACE / TRACEDATA0
+    IOPORT_PIN_P211_PFC_01_D0              = (0x01U << IOPORT_PFC_OFFSET), ///< P21_1 / BSC / D0
+    IOPORT_PIN_P211_PFC_02_MTIOC6A         = (0x02U << IOPORT_PFC_OFFSET), ///< P21_1 / MTU3n / MTIOC6A
+    IOPORT_PIN_P211_PFC_03_GTIOC14A        = (0x03U << IOPORT_PFC_OFFSET), ///< P21_1 / GPTn / GTIOC14A
+    IOPORT_PIN_P211_PFC_04_CMTW0_TIC0      = (0x04U << IOPORT_PFC_OFFSET), ///< P21_1 / CMTWn / CMTW0_TIC0
+    IOPORT_PIN_P211_PFC_05_SCK5            = (0x05U << IOPORT_PFC_OFFSET), ///< P21_1 / SCIn / SCK5
+    IOPORT_PIN_P211_PFC_06_SPI_SSL20       = (0x06U << IOPORT_PFC_OFFSET), ///< P21_1 / SPIn / SPI_SSL20
+    IOPORT_PIN_P211_PFC_07_IIC_SCL1        = (0x07U << IOPORT_PFC_OFFSET), ///< P21_1 / IICn / IIC_SCL1
+    IOPORT_PIN_P211_PFC_08_MCLK0           = (0x08U << IOPORT_PFC_OFFSET), ///< P21_1 / DSMIFn / MCLK0
+    IOPORT_PIN_P211_PFC_0A_ESC_SYNC0       = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_1 / ETHER_ESC / ESC_SYNC0
+    IOPORT_PIN_P211_PFC_0B_ESC_SYNC1       = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_1 / ETHER_ESC / ESC_SYNC1
+    IOPORT_PIN_P211_PFC_0C_HSPI_INT        = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_1 / SHOSTIF / HSPI_INT
+    IOPORT_PIN_P211_PFC_0D_HD0             = (0x0DU << IOPORT_PFC_OFFSET), ///< P21_1 / PHOSTIF / HD0
+    IOPORT_PIN_P212_PFC_00_TRACEDATA1      = (0x00U << IOPORT_PFC_OFFSET), ///< P21_2 / TRACE / TRACEDATA1
+    IOPORT_PIN_P212_PFC_01_D1              = (0x01U << IOPORT_PFC_OFFSET), ///< P21_2 / BSC / D1
+    IOPORT_PIN_P212_PFC_02_MTIOC6B         = (0x02U << IOPORT_PFC_OFFSET), ///< P21_2 / MTU3n / MTIOC6B
+    IOPORT_PIN_P212_PFC_03_GTIOC14B        = (0x03U << IOPORT_PFC_OFFSET), ///< P21_2 / GPTn / GTIOC14B
+    IOPORT_PIN_P212_PFC_04_CMTW0_TIC1      = (0x04U << IOPORT_PFC_OFFSET), ///< P21_2 / CMTWn / CMTW0_TIC1
+    IOPORT_PIN_P212_PFC_05_RXD5_SCL5_MISO5 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_2 / SCIn / RXD5_SCL5_MISO5
+    IOPORT_PIN_P212_PFC_06_SPI_MISO2       = (0x06U << IOPORT_PFC_OFFSET), ///< P21_2 / SPIn / SPI_MISO2
+    IOPORT_PIN_P212_PFC_07_IIC_SDA1        = (0x07U << IOPORT_PFC_OFFSET), ///< P21_2 / IICn / IIC_SDA1
+    IOPORT_PIN_P212_PFC_08_MDAT0           = (0x08U << IOPORT_PFC_OFFSET), ///< P21_2 / DSMIFn / MDAT0
+    IOPORT_PIN_P212_PFC_0A_ESC_SYNC0       = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_2 / ETHER_ESC / ESC_SYNC0
+    IOPORT_PIN_P212_PFC_0B_ESC_SYNC1       = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_2 / ETHER_ESC / ESC_SYNC1
+    IOPORT_PIN_P212_PFC_0C_HD1             = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_2 / PHOSTIF / HD1
+    IOPORT_PIN_P213_PFC_00_TRACEDATA2      = (0x00U << IOPORT_PFC_OFFSET), ///< P21_3 / TRACE / TRACEDATA2
+    IOPORT_PIN_P213_PFC_01_D2              = (0x01U << IOPORT_PFC_OFFSET), ///< P21_3 / BSC / D2
+    IOPORT_PIN_P213_PFC_02_MTIOC6C         = (0x02U << IOPORT_PFC_OFFSET), ///< P21_3 / MTU3n / MTIOC6C
+    IOPORT_PIN_P213_PFC_03_GTIOC15A        = (0x03U << IOPORT_PFC_OFFSET), ///< P21_3 / GPTn / GTIOC15A
+    IOPORT_PIN_P213_PFC_04_TXD5_SDA5_MOSI5 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_3 / SCIn / TXD5_SDA5_MOSI5
+    IOPORT_PIN_P213_PFC_05_SPI_SSL33       = (0x05U << IOPORT_PFC_OFFSET), ///< P21_3 / SPIn / SPI_SSL33
+    IOPORT_PIN_P213_PFC_06_MCLK1           = (0x06U << IOPORT_PFC_OFFSET), ///< P21_3 / DSMIFn / MCLK1
+    IOPORT_PIN_P213_PFC_08_NMI             = (0x08U << IOPORT_PFC_OFFSET), ///< P21_3 / IRQ / NMI
+    IOPORT_PIN_P213_PFC_09_HD2             = (0x09U << IOPORT_PFC_OFFSET), ///< P21_3 / PHOSTIF / HD2
+    IOPORT_PIN_P214_PFC_00_TRACEDATA3      = (0x00U << IOPORT_PFC_OFFSET), ///< P21_4 / TRACE / TRACEDATA3
+    IOPORT_PIN_P214_PFC_01_D3              = (0x01U << IOPORT_PFC_OFFSET), ///< P21_4 / BSC / D3
+    IOPORT_PIN_P214_PFC_02_MTIOC6D         = (0x02U << IOPORT_PFC_OFFSET), ///< P21_4 / MTU3n / MTIOC6D
+    IOPORT_PIN_P214_PFC_03_GTIOC15B        = (0x03U << IOPORT_PFC_OFFSET), ///< P21_4 / GPTn / GTIOC15B
+    IOPORT_PIN_P214_PFC_04_SS5_CTS5_RTS5   = (0x04U << IOPORT_PFC_OFFSET), ///< P21_4 / SCIn / SS5_CTS5_RTS5
+    IOPORT_PIN_P214_PFC_05_SPI_SSL02       = (0x05U << IOPORT_PFC_OFFSET), ///< P21_4 / SPIn / SPI_SSL02
+    IOPORT_PIN_P214_PFC_06_MDAT1           = (0x06U << IOPORT_PFC_OFFSET), ///< P21_4 / DSMIFn / MDAT1
+    IOPORT_PIN_P214_PFC_08_ETHSW_PTPOUT1   = (0x08U << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ETHSW / ETHSW_PTPOUT1
+    IOPORT_PIN_P214_PFC_09_ESC_SYNC0       = (0x09U << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ESC / ESC_SYNC0
+    IOPORT_PIN_P214_PFC_0A_ESC_SYNC1       = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ESC / ESC_SYNC1
+    IOPORT_PIN_P214_PFC_0B_HD3             = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_4 / PHOSTIF / HD3
+    IOPORT_PIN_P214_PFC_0C_MBX_HINT        = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_4 / MBXSEM / MBX_HINT
+    IOPORT_PIN_P215_PFC_00_IRQ6            = (0x00U << IOPORT_PFC_OFFSET), ///< P21_5 / IRQ / IRQ6
+    IOPORT_PIN_P215_PFC_01_TRACEDATA4      = (0x01U << IOPORT_PFC_OFFSET), ///< P21_5 / TRACE / TRACEDATA4
+    IOPORT_PIN_P215_PFC_02_D4              = (0x02U << IOPORT_PFC_OFFSET), ///< P21_5 / BSC / D4
+    IOPORT_PIN_P215_PFC_03_MTIOC7A         = (0x03U << IOPORT_PFC_OFFSET), ///< P21_5 / MTU3n / MTIOC7A
+    IOPORT_PIN_P215_PFC_04_GTIOC16A        = (0x04U << IOPORT_PFC_OFFSET), ///< P21_5 / GPTn / GTIOC16A
+    IOPORT_PIN_P215_PFC_05_CMTW1_TOC1      = (0x05U << IOPORT_PFC_OFFSET), ///< P21_5 / CMTWn / CMTW1_TOC1
+    IOPORT_PIN_P215_PFC_06_ADTRG1          = (0x06U << IOPORT_PFC_OFFSET), ///< P21_5 / ADCn / ADTRG1
+    IOPORT_PIN_P215_PFC_07_CTS5            = (0x07U << IOPORT_PFC_OFFSET), ///< P21_5 / SCIn / CTS5
+    IOPORT_PIN_P215_PFC_08_SPI_MISO0       = (0x08U << IOPORT_PFC_OFFSET), ///< P21_5 / SPIn / SPI_MISO0
+    IOPORT_PIN_P215_PFC_09_MCLK2           = (0x09U << IOPORT_PFC_OFFSET), ///< P21_5 / DSMIFn / MCLK2
+    IOPORT_PIN_P215_PFC_0B_HD4             = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_5 / PHOSTIF / HD4
+    IOPORT_PIN_P216_PFC_00_IRQ9            = (0x00U << IOPORT_PFC_OFFSET), ///< P21_6 / IRQ / IRQ9
+    IOPORT_PIN_P216_PFC_01_TRACEDATA5      = (0x01U << IOPORT_PFC_OFFSET), ///< P21_6 / TRACE / TRACEDATA5
+    IOPORT_PIN_P216_PFC_02_D5              = (0x02U << IOPORT_PFC_OFFSET), ///< P21_6 / BSC / D5
+    IOPORT_PIN_P216_PFC_03_MTIOC7B         = (0x03U << IOPORT_PFC_OFFSET), ///< P21_6 / MTU3n / MTIOC7B
+    IOPORT_PIN_P216_PFC_04_GTIOC16B        = (0x04U << IOPORT_PFC_OFFSET), ///< P21_6 / GPTn / GTIOC16B
+    IOPORT_PIN_P216_PFC_05_CTS0            = (0x05U << IOPORT_PFC_OFFSET), ///< P21_6 / SCIn / CTS0
+    IOPORT_PIN_P216_PFC_06_TEND            = (0x06U << IOPORT_PFC_OFFSET), ///< P21_6 / DMAC / TEND
+    IOPORT_PIN_P216_PFC_07_MDAT2           = (0x07U << IOPORT_PFC_OFFSET), ///< P21_6 / DSMIFn / MDAT2
+    IOPORT_PIN_P216_PFC_08_HD5             = (0x08U << IOPORT_PFC_OFFSET), ///< P21_6 / PHOSTIF / HD5
+    IOPORT_PIN_P217_PFC_00_IRQ10           = (0x00U << IOPORT_PFC_OFFSET), ///< P21_7 / IRQ / IRQ10
+    IOPORT_PIN_P217_PFC_01_TRACEDATA6      = (0x01U << IOPORT_PFC_OFFSET), ///< P21_7 / TRACE / TRACEDATA6
+    IOPORT_PIN_P217_PFC_02_D6              = (0x02U << IOPORT_PFC_OFFSET), ///< P21_7 / BSC / D6
+    IOPORT_PIN_P217_PFC_03_MTIOC7C         = (0x03U << IOPORT_PFC_OFFSET), ///< P21_7 / MTU3n / MTIOC7C
+    IOPORT_PIN_P217_PFC_04_GTIOC17A        = (0x04U << IOPORT_PFC_OFFSET), ///< P21_7 / GPTn / GTIOC17A
+    IOPORT_PIN_P217_PFC_05_DE0             = (0x05U << IOPORT_PFC_OFFSET), ///< P21_7 / SCIn / DE0
+    IOPORT_PIN_P217_PFC_06_DREQ            = (0x06U << IOPORT_PFC_OFFSET), ///< P21_7 / DMAC / DREQ
+    IOPORT_PIN_P217_PFC_07_MCLK3           = (0x07U << IOPORT_PFC_OFFSET), ///< P21_7 / DSMIFn / MCLK3
+    IOPORT_PIN_P217_PFC_08_HD6             = (0x08U << IOPORT_PFC_OFFSET), ///< P21_7 / PHOSTIF / HD6
+    IOPORT_PIN_P220_PFC_00_IRQ15           = (0x00U << IOPORT_PFC_OFFSET), ///< P22_0 / IRQ / IRQ15
+    IOPORT_PIN_P220_PFC_01_TRACEDATA7      = (0x01U << IOPORT_PFC_OFFSET), ///< P22_0 / TRACE / TRACEDATA7
+    IOPORT_PIN_P220_PFC_02_D7              = (0x02U << IOPORT_PFC_OFFSET), ///< P22_0 / BSC / D7
+    IOPORT_PIN_P220_PFC_03_MTIOC7D         = (0x03U << IOPORT_PFC_OFFSET), ///< P22_0 / MTU3n / MTIOC7D
+    IOPORT_PIN_P220_PFC_04_GTIOC17B        = (0x04U << IOPORT_PFC_OFFSET), ///< P22_0 / GPTn / GTIOC17B
+    IOPORT_PIN_P220_PFC_05_DE5             = (0x05U << IOPORT_PFC_OFFSET), ///< P22_0 / SCIn / DE5
+    IOPORT_PIN_P220_PFC_06_MDAT3           = (0x06U << IOPORT_PFC_OFFSET), ///< P22_0 / DSMIFn / MDAT3
+    IOPORT_PIN_P220_PFC_07_HD7             = (0x07U << IOPORT_PFC_OFFSET), ///< P22_0 / PHOSTIF / HD7
+    IOPORT_PIN_P221_PFC_00_TRACECTL        = (0x00U << IOPORT_PFC_OFFSET), ///< P22_1 / TRACE / TRACECTL
+    IOPORT_PIN_P221_PFC_01_D8              = (0x01U << IOPORT_PFC_OFFSET), ///< P22_1 / BSC / D8
+    IOPORT_PIN_P221_PFC_02_ESC_LINKACT2    = (0x02U << IOPORT_PFC_OFFSET), ///< P22_1 / ETHER_ESC / ESC_LINKACT2
+    IOPORT_PIN_P221_PFC_03_POE4            = (0x03U << IOPORT_PFC_OFFSET), ///< P22_1 / MTU_POE3 / POE4
+    IOPORT_PIN_P221_PFC_04_SS4_CTS4_RTS4   = (0x04U << IOPORT_PFC_OFFSET), ///< P22_1 / SCIn / SS4_CTS4_RTS4
+    IOPORT_PIN_P221_PFC_05_HD8             = (0x05U << IOPORT_PFC_OFFSET), ///< P22_1 / PHOSTIF / HD8
+    IOPORT_PIN_P221_PFC_06_GTETRGB         = (0x06U << IOPORT_PFC_OFFSET), ///< P22_1 / GPT_POEG / GTETRGB
+    IOPORT_PIN_P222_PFC_00_IRQ4            = (0x00U << IOPORT_PFC_OFFSET), ///< P22_2 / IRQ / IRQ4
+    IOPORT_PIN_P222_PFC_01_TRACECLK        = (0x01U << IOPORT_PFC_OFFSET), ///< P22_2 / TRACE / TRACECLK
+    IOPORT_PIN_P222_PFC_02_D9              = (0x02U << IOPORT_PFC_OFFSET), ///< P22_2 / BSC / D9
+    IOPORT_PIN_P222_PFC_03_MTIOC8C         = (0x03U << IOPORT_PFC_OFFSET), ///< P22_2 / MTU3n / MTIOC8C
+    IOPORT_PIN_P222_PFC_04_GTETRGSA        = (0x04U << IOPORT_PFC_OFFSET), ///< P22_2 / GPT_POEG / GTETRGSA
+    IOPORT_PIN_P222_PFC_05_SPI_SSL12       = (0x05U << IOPORT_PFC_OFFSET), ///< P22_2 / SPIn / SPI_SSL12
+    IOPORT_PIN_P222_PFC_07_HD9             = (0x07U << IOPORT_PFC_OFFSET), ///< P22_2 / PHOSTIF / HD9
+    IOPORT_PIN_P222_PFC_08_MCLK1           = (0x08U << IOPORT_PFC_OFFSET), ///< P22_2 / DSMIFn / MCLK1
+    IOPORT_PIN_P223_PFC_00_D10             = (0x00U << IOPORT_PFC_OFFSET), ///< P22_3 / BSC / D10
+    IOPORT_PIN_P223_PFC_01_MTIOC8D         = (0x01U << IOPORT_PFC_OFFSET), ///< P22_3 / MTU3n / MTIOC8D
+    IOPORT_PIN_P223_PFC_02_GTETRGSB        = (0x02U << IOPORT_PFC_OFFSET), ///< P22_3 / GPT_POEG / GTETRGSB
+    IOPORT_PIN_P223_PFC_04_RXD5_SCL5_MISO5 = (0x04U << IOPORT_PFC_OFFSET), ///< P22_3 / SCIn / RXD5_SCL5_MISO5
+    IOPORT_PIN_P223_PFC_05_HD10            = (0x05U << IOPORT_PFC_OFFSET), ///< P22_3 / PHOSTIF / HD10
+    IOPORT_PIN_P237_PFC_00_ETH2_RXD0       = (0x00U << IOPORT_PFC_OFFSET), ///< P23_7 / ETHER_ETHn / ETH2_RXD0
+    IOPORT_PIN_P237_PFC_02_D11             = (0x02U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / D11
+    IOPORT_PIN_P237_PFC_03_BS              = (0x03U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / BS
+    IOPORT_PIN_P237_PFC_04_MTIOC0A         = (0x04U << IOPORT_PFC_OFFSET), ///< P23_7 / MTU3n / MTIOC0A
+    IOPORT_PIN_P237_PFC_05_GTETRGA         = (0x05U << IOPORT_PFC_OFFSET), ///< P23_7 / GPT_POEG / GTETRGA
+    IOPORT_PIN_P237_PFC_06_SCK1            = (0x06U << IOPORT_PFC_OFFSET), ///< P23_7 / SCIn / SCK1
+    IOPORT_PIN_P237_PFC_07_MCLK4           = (0x07U << IOPORT_PFC_OFFSET), ///< P23_7 / DSMIFn / MCLK4
+    IOPORT_PIN_P237_PFC_09_HD11            = (0x09U << IOPORT_PFC_OFFSET), ///< P23_7 / PHOSTIF / HD11
+    IOPORT_PIN_P240_PFC_00_ETH2_RXD1       = (0x00U << IOPORT_PFC_OFFSET), ///< P24_0 / ETHER_ETHn / ETH2_RXD1
+    IOPORT_PIN_P240_PFC_02_D12             = (0x02U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / D12
+    IOPORT_PIN_P240_PFC_03_CKE             = (0x03U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / CKE
+    IOPORT_PIN_P240_PFC_04_MTIOC0B         = (0x04U << IOPORT_PFC_OFFSET), ///< P24_0 / MTU3n / MTIOC0B
+    IOPORT_PIN_P240_PFC_05_GTETRGB         = (0x05U << IOPORT_PFC_OFFSET), ///< P24_0 / GPT_POEG / GTETRGB
+    IOPORT_PIN_P240_PFC_06_RXD1_SCL1_MISO1 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_0 / SCIn / RXD1_SCL1_MISO1
+    IOPORT_PIN_P240_PFC_07_DREQ            = (0x07U << IOPORT_PFC_OFFSET), ///< P24_0 / DMAC / DREQ
+    IOPORT_PIN_P240_PFC_08_MDAT4           = (0x08U << IOPORT_PFC_OFFSET), ///< P24_0 / DSMIFn / MDAT4
+    IOPORT_PIN_P240_PFC_0A_HD12            = (0x0AU << IOPORT_PFC_OFFSET), ///< P24_0 / PHOSTIF / HD12
+    IOPORT_PIN_P241_PFC_00_ETH2_RXCLK      = (0x00U << IOPORT_PFC_OFFSET), ///< P24_1 / ETHER_ETHn / ETH2_RXCLK
+    IOPORT_PIN_P241_PFC_02_D13             = (0x02U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / D13
+    IOPORT_PIN_P241_PFC_03_CAS             = (0x03U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / CAS
+    IOPORT_PIN_P241_PFC_04_MTIOC0C         = (0x04U << IOPORT_PFC_OFFSET), ///< P24_1 / MTU3n / MTIOC0C
+    IOPORT_PIN_P241_PFC_05_GTETRGC         = (0x05U << IOPORT_PFC_OFFSET), ///< P24_1 / GPT_POEG / GTETRGC
+    IOPORT_PIN_P241_PFC_06_POE8            = (0x06U << IOPORT_PFC_OFFSET), ///< P24_1 / MTU_POE3 / POE8
+    IOPORT_PIN_P241_PFC_07_MCLK5           = (0x07U << IOPORT_PFC_OFFSET), ///< P24_1 / DSMIFn / MCLK5
+    IOPORT_PIN_P241_PFC_09_HD13            = (0x09U << IOPORT_PFC_OFFSET), ///< P24_1 / PHOSTIF / HD13
+    IOPORT_PIN_P242_PFC_00_ETH2_RXD2       = (0x00U << IOPORT_PFC_OFFSET), ///< P24_2 / ETHER_ETHn / ETH2_RXD2
+    IOPORT_PIN_P242_PFC_02_D14             = (0x02U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / D14
+    IOPORT_PIN_P242_PFC_03_RAS             = (0x03U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / RAS
+    IOPORT_PIN_P242_PFC_04_MTIOC0D         = (0x04U << IOPORT_PFC_OFFSET), ///< P24_2 / MTU3n / MTIOC0D
+    IOPORT_PIN_P242_PFC_05_GTETRGD         = (0x05U << IOPORT_PFC_OFFSET), ///< P24_2 / GPT_POEG / GTETRGD
+    IOPORT_PIN_P242_PFC_06_TXD1_SDA1_MOSI1 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_2 / SCIn / TXD1_SDA1_MOSI1
+    IOPORT_PIN_P242_PFC_07_MDAT5           = (0x07U << IOPORT_PFC_OFFSET), ///< P24_2 / DSMIFn / MDAT5
+    IOPORT_PIN_P242_PFC_09_HD14            = (0x09U << IOPORT_PFC_OFFSET), ///< P24_2 / PHOSTIF / HD14
+
+    /** Marks end of enum - used by parameter checking */
+    IOPORT_PERIPHERAL_END
+} ioport_pin_pfc_t;
+
+/** Options to configure pin functions  */
+typedef enum e_ioport_cfg_options
+{
+    IOPORT_CFG_PORT_DIRECTION_HIZ          = 0x00000000 << IOPORT_PM_OFFSET, ///< Sets the pin direction to Hi-Z
+    IOPORT_CFG_PORT_DIRECTION_INPUT        = 0x00000001 << IOPORT_PM_OFFSET, ///< Sets the pin direction to input (default)
+    IOPORT_CFG_PORT_DIRECTION_OUTPUT       = 0x00000002 << IOPORT_PM_OFFSET, ///< Sets the pin direction to output
+    IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT = 0x00000003 << IOPORT_PM_OFFSET, ///< Sets the pin direction to output (data is input to input buffer)
+    IOPORT_CFG_PORT_OUTPUT_LOW             = 0x00000000 << IOPORT_P_OFFSET,  ///< Sets the pin level to low
+    IOPORT_CFG_PORT_OUTPUT_HIGH            = 0x00000001 << IOPORT_P_OFFSET,  ///< Sets the pin level to high
+    IOPORT_CFG_PORT_GPIO               = 0x00000000 << IOPORT_PMC_OFFSET,    ///< Enables pin to operate as an GPIO pin
+    IOPORT_CFG_PORT_PERI               = 0x00000001 << IOPORT_PMC_OFFSET,    ///< Enables pin to operate as a peripheral pin
+    IOPORT_CFG_DRIVE_LOW               = 0x00000000 << IOPORT_DRCTL_OFFSET,  ///< Sets pin drive output to low
+    IOPORT_CFG_DRIVE_MID               = 0x00000001 << IOPORT_DRCTL_OFFSET,  ///< Sets pin drive output to medium
+    IOPORT_CFG_DRIVE_HIGH              = 0x00000002 << IOPORT_DRCTL_OFFSET,  ///< Sets pin drive output to high
+    IOPORT_CFG_DRIVE_UHIGH             = 0x00000003 << IOPORT_DRCTL_OFFSET,  ///< Sets pin drive output to ultra high
+    IOPORT_CFG_PULLUP_DOWN_DISABLE     = 0x00000000 << IOPORT_DRCTL_OFFSET,  ///< Disables the pin's pull-up / pull-down
+    IOPORT_CFG_PULLUP_ENABLE           = 0x00000004 << IOPORT_DRCTL_OFFSET,  ///< Enables the pin's internal pull-up
+    IOPORT_CFG_PULLDOWN_ENABLE         = 0x00000008 << IOPORT_DRCTL_OFFSET,  ///< Enables the pin's pull-down
+    IOPORT_CFG_SCHMITT_TRIGGER_DISABLE = 0x00000000 << IOPORT_DRCTL_OFFSET,  ///< Disables schmitt trigger input
+    IOPORT_CFG_SCHMITT_TRIGGER_ENABLE  = 0x00000010 << IOPORT_DRCTL_OFFSET,  ///< Enables schmitt trigger input
+    IOPORT_CFG_SLEW_RATE_SLOW          = 0x00000000 << IOPORT_DRCTL_OFFSET,  ///< Sets the slew rate to slow
+    IOPORT_CFG_SLEW_RATE_FAST          = 0x00000020 << IOPORT_DRCTL_OFFSET,  ///< Sets the slew rate to fast
+    IOPORT_CFG_REGION_SAFETY           = 0x00000000 << IOPORT_RSELP_OFFSET,  ///< Selects safety region
+    IOPORT_CFG_REGION_NSAFETY          = 0x00000001 << IOPORT_RSELP_OFFSET,  ///< Selects non safety region
+    IOPORT_CFG_PIM_TTL                 = 0x00000020,                         ///< This macro has been unsupported
+    IOPORT_CFG_NMOS_ENABLE             = 0x00000040,                         ///< This macro has been unsupported
+    IOPORT_CFG_PMOS_ENABLE             = 0x00000080,                         ///< This macro has been unsupported
+    IOPORT_CFG_DRIVE_HS_HIGH           = 0x00000800,                         ///< This macro has been unsupported
+    IOPORT_CFG_DRIVE_MID_IIC           = 0x00000C00,                         ///< This macro has been unsupported
+    IOPORT_CFG_EVENT_RISING_EDGE       = 0x00001000,                         ///< This macro has been unsupported
+    IOPORT_CFG_EVENT_FALLING_EDGE      = 0x00002000,                         ///< This macro has been unsupported
+    IOPORT_CFG_EVENT_BOTH_EDGES        = 0x00003000,                         ///< This macro has been unsupported
+    IOPORT_CFG_IRQ_ENABLE              = 0x00004000,                         ///< This macro has been unsupported
+    IOPORT_CFG_ANALOG_ENABLE           = 0x00008000,                         ///< This macro has been unsupported
+    IOPORT_CFG_PERIPHERAL_PIN          = 0x00010000                          ///< This macro has been unsupported
+} ioport_cfg_options_t;
+
+/*==============================================
+ * POE3 API Overrides
+ *==============================================*/
+
+/** POE3 states. */
+typedef enum e_poe3_state
+{
+    POE3_STATE_NO_DISABLE_REQUEST           = 0,                ///< Timer output is not disabled by POE3
+    POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST  = 1U,               ///< Timer output disabled due to POE0# pin
+    POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST  = 1U << 1,          ///< Timer output disabled due to POE4# pin
+    POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST  = 1U << 2,          ///< Timer output disabled due to POE8# pin
+    POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST = 1U << 3,          ///< Timer output disabled due to POE10# pin
+    POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST = 1U << 4,          ///< Timer output disabled due to POE11# pin
+
+    POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST    = 1U << 5,      ///< Timer output disabled due to poe3_api_t::outputDisable()
+    POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST = 1U << 6,      ///< Timer output disabled due to main oscillator stop
+
+    POE3_STATE_DSMIF0_ERROR_REQUEST = 1U << 7,                  ///< Timer output disabled due to DSMIF0 error
+    POE3_STATE_DSMIF1_ERROR_REQUEST = 1U << 8,                  ///< Timer output disabled due to DSMIF1 error
+
+    POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST = 1U << 9,  ///< Timer output disabled due to output short circuit 1
+    POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST = 1U << 10, ///< Timer output disabled due to output short circuit 2
+} poe3_state_t;
+
+/*==============================================
+ * POEG API Overrides
+ *==============================================*/
+
+/** POEG states. */
+typedef enum e_poeg_state
+{
+    POEG_STATE_NO_DISABLE_REQUEST                = 0,       ///< GPT output is not disabled by POEG
+    POEG_STATE_PIN_DISABLE_REQUEST               = 1U << 0, ///< GPT output disabled due to GTETRG pin level
+    POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST = 1U << 1, ///< GPT output disabled due to high speed analog comparator or GPT
+    POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST  = 1U << 2, ///< GPT output disabled due to main oscillator stop
+    POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST     = 1U << 3, ///< GPT output disabled due to poeg_api_t::outputDisable()
+
+    /** GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of
+     * the filtered input. */
+    POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE = 1U << 16,
+    POEG_STATE_DSMIF0_DISABLE_REQUEST     = 1U << 24,       ///< GPT output disabled due to DSMIF0 error 0
+    POEG_STATE_DSMIF1_DISABLE_REQUEST     = 1U << 25,       ///< GPT output disabled due to DSMIF1 error 0
+} poeg_state_t;
+
+/** Triggers that will disable GPT output pins. */
+typedef enum e_poeg_trigger
+{
+    /** Software disable is always supported with POEG. Select this option if no other triggers are used. */
+    POEG_TRIGGER_SOFTWARE         = 0U,
+    POEG_TRIGGER_PIN              = 1U << 0, ///< Disable GPT output based on GTETRG input level
+    POEG_TRIGGER_GPT_OUTPUT_LEVEL = 1U << 1, ///< Disable GPT output based on GPT output pin levels
+    POEG_TRIGGER_OSCILLATION_STOP = 1U << 2, ///< Disable GPT output based on main oscillator stop
+    POEG_TRIGGER_ACMPHS0          = 1U << 4, ///< Disable GPT output based on ACMPHS0 comparator result
+    POEG_TRIGGER_ACMPHS1          = 1U << 5, ///< Disable GPT output based on ACMPHS1 comparator result
+    POEG_TRIGGER_ACMPHS2          = 1U << 6, ///< Disable GPT output based on ACMPHS2 comparator result
+    POEG_TRIGGER_ACMPHS3          = 1U << 7, ///< Disable GPT output based on ACMPHS3 comparator result
+    POEG_TRIGGER_ACMPHS4          = 1U << 8, ///< Disable GPT output based on ACMPHS4 comparator result
+    POEG_TRIGGER_ACMPHS5          = 1U << 9, ///< Disable GPT output based on ACMPHS5 comparator result
+
+    /** The GPT output pins can be disabled when DSMIF error occurs (LLPP only). */
+    POEG_TRIGGER_DERR0E = 1U << 22,          ///< Permit output disabled by DSMIF0 error detection
+    POEG_TRIGGER_DERR1E = 1U << 23,          ///< Permit output disabled by DSMIF1 error detection
+} poeg_trigger_t;
+
+/*==============================================
+ * Transfer API Overrides
+ *==============================================*/
+
+/** Events that can trigger a callback function. */
+typedef enum e_transfer_event
+{
+    TRANSFER_EVENT_TRANSFER_END   = 0, ///< Transfer has completed.
+    TRANSFER_EVENT_TRANSFER_ERROR = 1, ///< Transfer error has occurred.
+} transfer_event_t;
+
+/** Transfer mode describes what will happen when a transfer request occurs. */
+typedef enum e_transfer_mode
+{
+    /** Normal mode. */
+    TRANSFER_MODE_NORMAL = 0,
+
+    /** Block mode. */
+    TRANSFER_MODE_BLOCK = 1
+} transfer_mode_t;
+
+/** Transfer size specifies the size of each individual transfer. */
+typedef enum e_transfer_size
+{
+    TRANSFER_SIZE_1_BYTE  = 0,         ///< Each transfer transfers a 8-bit value
+    TRANSFER_SIZE_2_BYTE  = 1,         ///< Each transfer transfers a 16-bit value
+    TRANSFER_SIZE_4_BYTE  = 2,         ///< Each transfer transfers a 32-bit value
+    TRANSFER_SIZE_8_BYTE  = 3,         ///< Each transfer transfers a 64-bit value
+    TRANSFER_SIZE_16_BYTE = 4,         ///< Each transfer transfers a 128-bit value
+    TRANSFER_SIZE_32_BYTE = 5,         ///< Each transfer transfers a 256-bit value
+    TRANSFER_SIZE_64_BYTE = 6          ///< Each transfer transfers a 512-bit value
+} transfer_size_t;
+
+/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
+typedef enum e_transfer_addr_mode
+{
+    /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
+    TRANSFER_ADDR_MODE_INCREMENTED = 0,
+
+    /** Address pointer remains fixed after each transfer. */
+    TRANSFER_ADDR_MODE_FIXED = 1
+} transfer_addr_mode_t;
+
+/** Callback function parameter data. */
+typedef struct st_transfer_callback_args_t
+{
+    transfer_event_t event;            ///< Event code
+    void const     * p_context;        ///< Placeholder for user data. Set in transfer_api_t::open function in ::transfer_cfg_t.
+} transfer_callback_args_t;
+
+/** This structure specifies the properties of the transfer. */
+typedef struct st_transfer_info
+{
+    /** Select what happens to destination pointer after each transfer. */
+    transfer_addr_mode_t dest_addr_mode;
+
+    /** Select what happens to source pointer after each transfer. */
+    transfer_addr_mode_t src_addr_mode;
+
+    /** Select mode from @ref transfer_mode_t. */
+    transfer_mode_t mode;
+
+    /** Source pointer. */
+    void const * volatile p_src;
+
+    /** Destination pointer. */
+    void * volatile p_dest;
+
+    /** Length of each transfer. */
+    volatile uint32_t length;
+
+    /** Select number of source bytes to transfer at once. */
+    transfer_size_t src_size;
+
+    /** Select number of destination bytes to transfer at once. */
+    transfer_size_t dest_size;
+
+    /** Next1 Register set settings */
+    void const * p_next1_src;
+    void       * p_next1_dest;
+    uint32_t     next1_length;
+} transfer_info_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ether_phy/r_ether_phy.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ether_phy/r_ether_phy.c
new file mode 100644
index 00000000..a07089d9
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ether_phy/r_ether_phy.c
@@ -0,0 +1,2120 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+
+#include "bsp_api.h"
+#include "r_ether_phy.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ ***********************************************************************************************************************/
+#ifndef ETHER_PHY_ERROR_RETURN
+
+/*LDRA_INSPECTED 77 S This macro does not work when surrounded by parentheses. */
+ #define ETHER_PHY_ERROR_RETURN(a, err)    FSP_ERROR_RETURN((a), (err))
+#endif
+
+#define ETHERC_REG_SIZE                               (0x400UL)
+
+/** "RPHY" in ASCII.  Used to determine if the control block is open. */
+#define ETHER_PHY_OPEN                                (0x52504859U)
+
+/* Media Independent Interface */
+#define ETHER_PHY_MII_ST                              (1)
+#define ETHER_PHY_MII_READ                            (2)
+#define ETHER_PHY_MII_WRITE                           (1)
+
+/* Standard PHY Registers */
+#define ETHER_PHY_REG_CONTROL                         (0)
+#define ETHER_PHY_REG_STATUS                          (1)
+#define ETHER_PHY_REG_IDENTIFIER1                     (2)
+#define ETHER_PHY_REG_IDENTIFIER2                     (3)
+#define ETHER_PHY_REG_AN_ADVERTISEMENT                (4)
+#define ETHER_PHY_REG_AN_LINK_PARTNER                 (5)
+#define ETHER_PHY_REG_AN_EXPANSION                    (6)
+#define ETHER_PHY_REG_1000BT_CONTROL                  (9)
+#define ETHER_PHY_REG_1000BT_STATUS                   (10)
+
+/* Basic Mode Control Register Bit Definitions */
+#define ETHER_PHY_CONTROL_RESET                       (1 << 15)
+#define ETHER_PHY_CONTROL_LOOPBACK                    (1 << 14)
+#define ETHER_PHY_CONTROL_100_MBPS                    (1 << 13)
+#define ETHER_PHY_CONTROL_AN_ENABLE                   (1 << 12)
+#define ETHER_PHY_CONTROL_POWER_DOWN                  (1 << 11)
+#define ETHER_PHY_CONTROL_ISOLATE                     (1 << 10)
+#define ETHER_PHY_CONTROL_AN_RESTART                  (1 << 9)
+#define ETHER_PHY_CONTROL_FULL_DUPLEX                 (1 << 8)
+#define ETHER_PHY_CONTROL_COLLISION                   (1 << 7)
+#define ETHER_PHY_CONTROL_SPEED_SELCT                 (1 << 6)
+
+/* Basic Mode Status Register Bit Definitions */
+#define ETHER_PHY_STATUS_100_T4                       (1 << 15)
+#define ETHER_PHY_STATUS_100F                         (1 << 14)
+#define ETHER_PHY_STATUS_100H                         (1 << 13)
+#define ETHER_PHY_STATUS_10F                          (1 << 12)
+#define ETHER_PHY_STATUS_10H                          (1 << 11)
+#define ETHER_PHY_STATUS_EX_STATUS                    (1 << 8)
+#define ETHER_PHY_STATUS_AN_COMPLETE                  (1 << 5)
+#define ETHER_PHY_STATUS_RM_FAULT                     (1 << 4)
+#define ETHER_PHY_STATUS_AN_ABILITY                   (1 << 3)
+#define ETHER_PHY_STATUS_LINK_UP                      (1 << 2)
+#define ETHER_PHY_STATUS_JABBER                       (1 << 1)
+#define ETHER_PHY_STATUS_EX_CAPABILITY                (1 << 0)
+
+/* Auto Negotiation Advertisement Bit Definitions */
+#define ETHER_PHY_AN_ADVERTISEMENT_NEXT_PAGE          (1 << 15)
+#define ETHER_PHY_AN_ADVERTISEMENT_RM_FAULT           (1 << 13)
+#define ETHER_PHY_AN_ADVERTISEMENT_ASM_DIR            (1 << 11)
+#define ETHER_PHY_AN_ADVERTISEMENT_PAUSE              (1 << 10)
+#define ETHER_PHY_AN_ADVERTISEMENT_100_T4             (1 << 9)
+#define ETHER_PHY_AN_ADVERTISEMENT_100F               (1 << 8)
+#define ETHER_PHY_AN_ADVERTISEMENT_100H               (1 << 7)
+#define ETHER_PHY_AN_ADVERTISEMENT_10F                (1 << 6)
+#define ETHER_PHY_AN_ADVERTISEMENT_10H                (1 << 5)
+#define ETHER_PHY_AN_ADVERTISEMENT_SELECTOR           (1 << 0)
+#define ETHER_PHY_AN_ADVERTISEMENT_SELECTOR_MASK      (1 << 0)
+
+/* Auto Negotiate Link Partner Ability Bit Definitions */
+#define ETHER_PHY_AN_LINK_PARTNER_NEXT_PAGE           (1 << 15)
+#define ETHER_PHY_AN_LINK_PARTNER_ACK                 (1 << 14)
+#define ETHER_PHY_AN_LINK_PARTNER_RM_FAULT            (1 << 13)
+#define ETHER_PHY_AN_LINK_PARTNER_ASM_DIR             (1 << 11)
+#define ETHER_PHY_AN_LINK_PARTNER_PAUSE               (1 << 10)
+#define ETHER_PHY_AN_LINK_PARTNER_100_T4              (1 << 9)
+#define ETHER_PHY_AN_LINK_PARTNER_100F                (1 << 8)
+#define ETHER_PHY_AN_LINK_PARTNER_100H                (1 << 7)
+#define ETHER_PHY_AN_LINK_PARTNER_10F                 (1 << 6)
+#define ETHER_PHY_AN_LINK_PARTNER_10H                 (1 << 5)
+#define ETHER_PHY_AN_LINK_PARTNER_SELECTOR            (1 << 0)
+
+/* 1000BASE-T Control */
+#define ETHER_PHY_1000BT_CONTROL_1000F                (1 << 9)
+#define ETHER_PHY_1000BT_CONTROL_1000H                (1 << 8)
+
+/* 1000BASE-T Status */
+#define ETHER_PHY_1000BT_STATUS_PARTNER_1000F         (1 << 11)
+#define ETHER_PHY_1000BT_STATUS_PARTNER_1000H         (1 << 10)
+
+#define ETHER_PHY_PIR_MDI_MASK                        (1 << 3)
+#define ETHER_PHY_PIR_MDO_HIGH                        (0x04)
+#define ETHER_PHY_PIR_MDO_LOW                         (0x00)
+#define ETHER_PHY_PIR_MMD_WRITE                       (0x02)
+#define ETHER_PHY_PIR_MMD_READ                        (0x00)
+#define ETHER_PHY_PIR_MDC_HIGH                        (0x01)
+#define ETHER_PHY_PIR_MDC_LOW                         (0x00)
+
+#define ETHER_PHY_PREAMBLE_LENGTH                     (32U)
+#define ETHER_PHY_WRITE_DATA_BIT_MASK                 (0x8000)
+
+/* Define for MDIO_CFG_STATUS of MDIO_ETHSW */
+#define ETHER_PHY_ETHSW_MDIO_CFG_STATUS_BUSY          (1 << 0)  /**< busy bit mask */
+#define ETHER_PHY_ETHSW_MDIO_CFG_STATUS_READERR       (1 << 1)  /**< read error mask */
+
+/* Define for MDIO_COMMAND of MDIO_ETHSW */
+#define ETHER_PHY_ETHSW_MDIO_COMMAND_REGADDR_MASK     (0x1f)    /**< REG address mask */
+#define ETHER_PHY_ETHSW_MDIO_COMMAND_PHYADDR_SHIFT    (5)       /**< PHY address shift */
+                                                                /**< PHY address mask */
+#define ETHER_PHY_ETHSW_MDIO_COMMAND_PHYADDR_MASK     (0x1f << ETHER_PHY_ETHSW_MDIO_COMMAND_PHYADDR_SHIFT)
+#define ETHER_PHY_ETHSW_MDIO_COMMAND_TRANINIT_READ    (1 << 15) /**< transaction init read */
+
+#define ETHER_PHY_16BIT_DATA_MASK                     (0xffff)
+
+/* Define for delay time */
+#define ETHER_PHY_DELAY_2US                           (2) /* 2us */
+
+/* Initial value of down counter for timeout detection */
+#define ETHER_PHY_TIMEOUT_COUNT                       (1000000000)
+
+/* Illegal PHY register read value  */
+#define ETHER_PHY_REGISTER_READ_ERROR                 (0xffff)
+#if defined(BSP_MCU_GROUP_RZN2H)
+
+/* Bit definen of MDIO Address Register */
+ #define ETHER_PHY_MDIO_ADDRESS_PA_SHIFT              (21) /**< Physical Layer Address */
+ #define ETHER_PHY_MDIO_ADDRESS_PA_MASK               (0x1f << ETHER_PHY_MDIO_ADDRESS_PA_SHIFT)
+ #define ETHER_PHY_MDIO_ADDRESS_RDA_SHIFT             (16) /**< GMII Register */
+ #define ETHER_PHY_MDIO_ADDRESS_RDA_MASK              (0x1f << ETHER_PHY_MDIO_ADDRESS_RDA_SHIFT)
+ #define ETHER_PHY_MDIO_ADDRESS_CR_SHIFT              (8)  /**< CSR Clock Range */
+ #define ETHER_PHY_MDIO_ADDRESS_CR_MASK               (0x0f << ETHER_PHY_MDIO_ADDRESS_CR_SHIFT)
+ #define ETHER_PHY_MDIO_ADDRESS_GOC1                  (1 << 3)
+ #define ETHER_PHY_MDIO_ADDRESS_GOC0                  (1 << 2)
+ #define ETHER_PHY_MDIO_ADDRESS_C45E                  (1 << 1)
+ #define ETHER_PHY_MDIO_ADDRESS_GB                    (1 << 0) /**< MDIO Busy */
+
+ #define ETHER_PHY_MDIO_ADDRESS_READ                  (ETHER_PHY_MDIO_ADDRESS_GOC1 | ETHER_PHY_MDIO_ADDRESS_GOC0)
+ #define ETHER_PHY_MDIO_ADDRESS_WRITE                 (ETHER_PHY_MDIO_ADDRESS_GOC0)
+
+ #define ETHER_PHY_MDIO_ADDRESS_CR                    4 /* CSR clock/102 */
+
+#else // !BSP_MCU_GROUP_RZN2H
+
+/* Bit definen of GMII_Address Register */
+ #define ETHER_PHY_GMII_ADDRESS_PA_SHIFT              (11)     /**< Physical Layer Address */
+ #define ETHER_PHY_GMII_ADDRESS_PA_MASK               (0x1f << ETHER_PHY_GMII_ADDRESS_PA_SHIFT)
+ #define ETHER_PHY_GMII_ADDRESS_GR_SHIFT              (6)      /**< GMII Register */
+ #define ETHER_PHY_GMII_ADDRESS_GR_MASK               (0x1f << ETHER_PHY_GMII_ADDRESS_GR_SHIFT)
+ #define ETHER_PHY_GMII_ADDRESS_CR                    (4 << 2) /**< CSR Clock Range */
+ #define ETHER_PHY_GMII_ADDRESS_GW                    (1 << 1) /**< GMII Write */
+ #define ETHER_PHY_GMII_ADDRESS_GB                    (1 << 0) /**< GMII Busy */
+
+#endif // !BSP_MCU_GROUP_RZN2H
+
+#define ETHER_PHY_ADDRESS_SIZE                        (0x1fU)
+#define ETHER_PHY_REGISTER_DATA_SIZE                  (0xffffU)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global function
+ ***********************************************************************************************************************/
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+static fsp_err_t ether_phy_open_param_check(ether_phy_instance_ctrl_t   * p_instance_ctrl,
+                                            ether_phy_cfg_t const * const p_cfg);
+
+#endif
+
+static ether_selector_speed_t  ether_phy_get_selector_speed(ether_phy_speed_t bps);
+static ether_selector_duplex_t ether_phy_get_selector_duplex(ether_phy_duplex_t duplex);
+
+static fsp_err_t ether_phy_reset(ether_phy_instance_ctrl_t * p_instance_ctrl, ether_phy_cfg_t const * const p_cfg);
+
+static fsp_err_t ether_phy_set_auto_negotiate_off(ether_phy_instance_ctrl_t * p_instance_ctrl);
+static fsp_err_t ether_phy_set_auto_negotiate_on(ether_phy_instance_ctrl_t * p_instance_ctrl);
+
+static fsp_err_t ether_phy_get_ability_auto_negotiate_on(ether_phy_instance_ctrl_t * p_instance_ctrl,
+                                                         uint32_t * const            p_line_speed_duplex,
+                                                         uint32_t * const            p_local_pause,
+                                                         uint32_t * const            p_partner_pause);
+static fsp_err_t ether_phy_get_ability_auto_negotiate_off(ether_phy_instance_ctrl_t * p_instance_ctrl,
+                                                          uint32_t * const            p_line_speed_duplex,
+                                                          uint32_t * const            p_local_pause,
+                                                          uint32_t * const            p_partner_pause);
+
+void ether_phy_convert_speed_duplex(uint32_t                  line_speed_duple,
+                                    ether_selector_speed_t  * p_selector_speed,
+                                    ether_selector_duplex_t * p_selector_duplex);
+
+static void ether_phy_read_gmac(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr,
+                                uint32_t * const p_data);
+
+static void ether_phy_read_ethsw(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_add,
+                                 uint32_t * const p_data);
+static void ether_phy_read_esc(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_add, uint32_t * const p_data);
+
+static void ether_phy_write_gmac(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t data);
+static void ether_phy_write_ethsw(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t data);
+static void ether_phy_write_esc(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t data);
+
+static void ether_phy_targets_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl);
+
+#if (ETHER_PHY_CFG_TARGET_VSC8541_ENABLE)
+static void ether_phy_targets_initialize_vsc8541(ether_phy_instance_ctrl_t * p_instance_ctrl);
+
+#endif
+
+#if (ETHER_PHY_CFG_TARGET_KSZ9131_ENABLE)
+static void ether_phy_targets_initialize_ksz9131(ether_phy_instance_ctrl_t * p_instance_ctrl);
+
+#endif
+
+#if (ETHER_PHY_CFG_TARGET_KSZ9031_ENABLE)
+static void ether_phy_targets_initialize_ksz9031(ether_phy_instance_ctrl_t * p_instance_ctrl);
+
+#endif
+
+#if (ETHER_PHY_CFG_TARGET_KSZ8081_ENABLE)
+static void ether_phy_targets_initialize_ksz8081(ether_phy_instance_ctrl_t * p_instance_ctrl);
+
+#endif
+
+#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE)
+static void ether_phy_targets_initialize_ksz8041(ether_phy_instance_ctrl_t * p_instance_ctrl);
+
+#endif
+
+/** ETHER_PHY HAL API mapping for Ethernet PHY Controller interface */
+/*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */
+const ether_phy_api_t g_ether_phy_on_ether_phy =
+{
+    .open                  = R_ETHER_PHY_Open,
+    .close                 = R_ETHER_PHY_Close,
+    .startAutoNegotiate    = R_ETHER_PHY_StartAutoNegotiate,
+    .linkPartnerAbilityGet = R_ETHER_PHY_LinkPartnerAbilityGet,
+    .linkStatusGet         = R_ETHER_PHY_LinkStatusGet,
+    .chipInit              = R_ETHER_PHY_ChipInit,
+    .read                  = R_ETHER_PHY_Read,
+    .write                 = R_ETHER_PHY_Write
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup ETHER_PHY
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/********************************************************************************************************************//**
+ * Resets Ethernet PHY device. Implements @ref ether_phy_api_t::open.
+ *
+ * @retval  FSP_SUCCESS                             Channel opened successfully.
+ * @retval  FSP_ERR_ASSERTION                       Pointer to ETHER_PHY control block or configuration structure is NULL.
+ * @retval  FSP_ERR_ALREADY_OPEN                    Control block has already been opened or channel is being used by another
+ *                                                  instance. Call close() then open() to reconfigure.
+ * @retval  FSP_ERR_INVALID_CHANNEL                 Invalid channel number is given.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                Invalid arguments.
+ * @retval  FSP_ERR_TIMEOUT                         PHY-LSI Reset wait timeout.
+ * @retval  FSP_ERR_INVALID_POINTER                 Pointer to p_cfg is NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_Open (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl;
+    ether_phy_extend_cfg_t    * p_extend;
+    ether_selector_instance_t * p_selector_instance;
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+
+    /** Check parameters. */
+    err = ether_phy_open_param_check(p_instance_ctrl, p_cfg); /** check arguments */
+    ETHER_PHY_ERROR_RETURN((FSP_SUCCESS == err), err);
+#endif
+
+    p_extend = (ether_phy_extend_cfg_t *) p_cfg->p_extend;
+
+    /* Initialize configuration of ethernet phy module. */
+    p_instance_ctrl->p_ether_phy_cfg = p_cfg;
+
+    switch (p_extend->mdio_type)
+    {
+#if defined(BSP_MCU_GROUP_RZN2H)
+        case ETHER_PHY_MDIO_GMAC:
+        default:
+        {
+            p_instance_ctrl->p_reg_etherc = (uint32_t *) R_GMAC0_BASE;
+            break;
+        }
+
+        case ETHER_PHY_MDIO_GMAC1:
+        {
+            p_instance_ctrl->p_reg_etherc = (uint32_t *) R_GMAC1_BASE;
+            break;
+        }
+
+        case ETHER_PHY_MDIO_GMAC2:
+        {
+            p_instance_ctrl->p_reg_etherc = (uint32_t *) R_GMAC2_BASE;
+            break;
+        }
+
+#else                                  // !BSP_MCU_GROUP_RZN2H
+        case ETHER_PHY_MDIO_GMAC:
+        default:
+        {
+            p_instance_ctrl->p_reg_etherc = (uint32_t *) R_GMAC_BASE;
+            break;
+        }
+#endif                                 // !BSP_MCU_GROUP_RZN2H
+
+        case ETHER_PHY_MDIO_ETHSW:
+        {
+            p_instance_ctrl->p_reg_etherc = (uint32_t *) R_ETHSW_BASE;
+            break;
+        }
+
+        case ETHER_PHY_MDIO_ESC:
+        {
+            p_instance_ctrl->p_reg_etherc = (uint32_t *) R_ESC_BASE;
+            break;
+        }
+    }
+
+    p_instance_ctrl->local_advertise = 0;
+
+    p_selector_instance = p_extend->p_selector_instance;
+
+    err = p_selector_instance->p_api->open(p_selector_instance->p_ctrl, p_selector_instance->p_cfg);
+
+    if (FSP_SUCCESS == err)
+    {
+        err =
+            p_selector_instance->p_api->converterSet(p_selector_instance->p_ctrl,
+                                                     ether_phy_get_selector_speed(p_extend->bps),
+                                                     ether_phy_get_selector_duplex(p_extend->duplex));
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        if (p_extend->port_type == ETHER_PHY_PORT_TYPE_ETHERNET)
+        {
+            err = ether_phy_reset(p_instance_ctrl, p_cfg);
+        }
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        ether_phy_targets_initialize(p_instance_ctrl);
+
+        if (ETHER_PHY_AUTO_NEGOTIATION_ON == p_extend->auto_negotiation)
+        {
+            err = ether_phy_set_auto_negotiate_on(p_instance_ctrl);
+        }
+        else
+        {
+            err = ether_phy_set_auto_negotiate_off(p_instance_ctrl);
+        }
+
+        if (FSP_SUCCESS == err)
+        {
+            p_instance_ctrl->open = ETHER_PHY_OPEN;
+        }
+    }
+
+    return err;
+}                                      /* End of function R_ETHER_PHY_Open() */
+
+/********************************************************************************************************************//**
+ * Close Ethernet PHY device. Implements @ref ether_phy_api_t::close.
+ *
+ * @retval  FSP_SUCCESS                                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened
+ *
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_Close (ether_phy_ctrl_t * const p_ctrl)
+{
+    ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl;
+    ether_phy_extend_cfg_t    * p_extend;
+    ether_selector_instance_t * p_selector_instance;
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_extend            = (ether_phy_extend_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend;
+    p_selector_instance = p_extend->p_selector_instance;
+
+    p_selector_instance->p_api->close(p_selector_instance->p_ctrl);
+
+    /** Clear configure block parameters. */
+    p_instance_ctrl->p_ether_phy_cfg = NULL;
+    p_instance_ctrl->p_reg_etherc    = 0;
+    p_instance_ctrl->open            = 0;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHER_PHY_Close() */
+
+/********************************************************************************************************************//**
+ * Starts auto-negotiate. Implements @ref ether_phy_api_t::startAutoNegotiate.
+ *
+ * @retval  FSP_SUCCESS                 ETHER_PHY successfully starts auto-negotiate.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_MODE        It was aborted the process because it is not auto-negotiation mode.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Register address is incorrect
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to read buffer is NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_StartAutoNegotiate (ether_phy_ctrl_t * const p_ctrl)
+{
+    ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl;
+    ether_phy_extend_cfg_t    * p_extend;
+    uint32_t reg;
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_extend = (ether_phy_extend_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend;
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_AUTO_NEGOTIATION_ON == (p_extend->auto_negotiation), FSP_ERR_INVALID_MODE);
+
+    /* Restart Auto-Negoration */
+    R_ETHER_PHY_Write(p_instance_ctrl,
+                      ETHER_PHY_REG_CONTROL,
+                      (ETHER_PHY_CONTROL_AN_ENABLE |
+                       ETHER_PHY_CONTROL_AN_RESTART));
+
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_AN_ADVERTISEMENT, &reg);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHER_PHY_StartAutoNegotiate() */
+
+/********************************************************************************************************************//**
+ * Reports the other side's physical capability. Implements @ref ether_phy_api_t::linkPartnerAbilityGet.
+ *
+ * @retval  FSP_SUCCESS                                 ETHER_PHY successfully get link partner ability.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_INVALID_POINTER                     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened
+ * @retval  FSP_ERR_ETHER_PHY_ERROR_LINK                PHY-LSI is not link up.
+ * @retval  FSP_ERR_ETHER_PHY_NOT_READY                 The auto-negotiation isn't completed
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Status register address is incorrect
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_LinkPartnerAbilityGet (ether_phy_ctrl_t * const p_ctrl,
+                                             uint32_t * const         p_line_speed_duplex,
+                                             uint32_t * const         p_local_pause,
+                                             uint32_t * const         p_partner_pause)
+{
+    ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl;
+    fsp_err_t                err;
+    ether_phy_extend_cfg_t * p_extend;
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHER_PHY_ERROR_RETURN(NULL != p_line_speed_duplex, FSP_ERR_INVALID_POINTER);
+    ETHER_PHY_ERROR_RETURN(NULL != p_local_pause, FSP_ERR_INVALID_POINTER);
+    ETHER_PHY_ERROR_RETURN(NULL != p_partner_pause, FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_extend = (ether_phy_extend_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend;
+
+    if (ETHER_PHY_AUTO_NEGOTIATION_ON == p_extend->auto_negotiation)
+    {
+        err = ether_phy_get_ability_auto_negotiate_on(p_instance_ctrl,
+                                                      p_line_speed_duplex,
+                                                      p_local_pause,
+                                                      p_partner_pause);
+        if (FSP_SUCCESS == err)
+        {
+            ether_selector_speed_t      selector_speed;
+            ether_selector_duplex_t     selector_duplex;
+            ether_selector_instance_t * p_selector_instance;
+
+            ether_phy_convert_speed_duplex(*p_line_speed_duplex, &selector_speed, &selector_duplex);
+
+            p_selector_instance = p_extend->p_selector_instance;
+
+            err =
+                p_selector_instance->p_api->converterSet(p_selector_instance->p_ctrl, selector_speed, selector_duplex);
+        }
+    }
+    else
+    {
+        err = ether_phy_get_ability_auto_negotiate_off(p_instance_ctrl,
+                                                       p_line_speed_duplex,
+                                                       p_local_pause,
+                                                       p_partner_pause);
+    }
+
+    return err;
+}                                      /* End of function R_ETHER_PHY_LinkPartnerAbilityGet() */
+
+/********************************************************************************************************************//**
+ * Returns the status of the physical link. Implements @ref ether_phy_api_t::linkStatusGet.
+ *
+ * @retval  FSP_SUCCESS                                 ETHER_PHY successfully get link partner ability.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened
+ * @retval  FSP_ERR_ETHER_PHY_ERROR_LINK                PHY-LSI is not link up.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Status register address is incorrect
+ * @retval  FSP_ERR_INVALID_POINTER                     Pointer to read buffer is NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_LinkStatusGet (ether_phy_ctrl_t * const p_ctrl)
+{
+    ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl;
+    uint32_t  reg;
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Because reading the first time shows the previous state, the Link status bit is read twice. */
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_STATUS, &reg);
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_STATUS, &reg);
+
+    /* When the link isn't up, return error */
+    if ((ETHER_PHY_REGISTER_READ_ERROR == (reg & ETHER_PHY_REGISTER_READ_ERROR)) ||
+        (ETHER_PHY_STATUS_LINK_UP != (reg & ETHER_PHY_STATUS_LINK_UP)))
+    {
+        /* Link is down */
+        err = FSP_ERR_ETHER_PHY_ERROR_LINK;
+    }
+    else
+    {
+        /* Link is up */
+        err = FSP_SUCCESS;
+    }
+
+    return err;
+}                                      /* End of function R_ETHER_PHY_LinkStatusGet() */
+
+/********************************************************************************************************************//**
+ * @brief Initialize Ethernet PHY device. Implements @ref ether_phy_api_t::chipInit.
+ *
+ * @retval  FSP_ERR_UNSUPPORTED                     Initialize Ethernet PHY device is not supported.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_ChipInit (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg)
+{
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(p_cfg);
+
+    return FSP_ERR_UNSUPPORTED;
+}                                      /* End of function R_ETHER_PHY_ChipInit() */
+
+/********************************************************************************************************************//**
+ * @brief Read data from register of PHY-LSI . Implements @ref ether_phy_api_t::read.
+ *
+ * @retval  FSP_SUCCESS                                 ETHER_PHY successfully read data.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_INVALID_POINTER                     Pointer to read buffer is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Address is not a valid size
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_Read (ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data)
+{
+    ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl;
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHER_PHY_ERROR_RETURN(NULL != p_data, FSP_ERR_INVALID_POINTER);
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_ADDRESS_SIZE >= reg_addr, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    ether_phy_extend_cfg_t * p_extend = (ether_phy_extend_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend;
+
+    switch (p_extend->mdio_type)
+    {
+        case ETHER_PHY_MDIO_GMAC:
+#if defined(BSP_MCU_GROUP_RZN2H)
+        case ETHER_PHY_MDIO_GMAC1:
+        case ETHER_PHY_MDIO_GMAC2:
+#endif
+            {
+                ether_phy_read_gmac(p_instance_ctrl, reg_addr, p_data);
+                break;
+            }
+
+        case ETHER_PHY_MDIO_ETHSW:
+        {
+            ether_phy_read_ethsw(p_instance_ctrl, reg_addr, p_data);
+            break;
+        }
+
+        case ETHER_PHY_MDIO_ESC:
+        {
+            ether_phy_read_esc(p_instance_ctrl, reg_addr, p_data);
+            break;
+        }
+
+        default:
+        {
+            *p_data = ETHER_PHY_REGISTER_READ_ERROR;
+            break;
+        }
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHER_PHY_Read() */
+
+/********************************************************************************************************************//**
+ * @brief Write data to register of PHY-LSI . Implements @ref ether_phy_api_t::write.
+ *
+ * @retval  FSP_SUCCESS                                 ETHER_PHY successfully write data.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Address or data is not a valid size
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHER_PHY_Write (ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data)
+{
+    ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl;
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_ADDRESS_SIZE >= reg_addr, FSP_ERR_INVALID_ARGUMENT);
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_REGISTER_DATA_SIZE >= data, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    ether_phy_extend_cfg_t * p_extend = (ether_phy_extend_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend;
+
+    switch (p_extend->mdio_type)
+    {
+        case ETHER_PHY_MDIO_GMAC:
+#if defined(BSP_MCU_GROUP_RZN2H)
+        case ETHER_PHY_MDIO_GMAC1:
+        case ETHER_PHY_MDIO_GMAC2:
+#endif
+            {
+                ether_phy_write_gmac(p_instance_ctrl, reg_addr, data);
+                break;
+            }
+
+        case ETHER_PHY_MDIO_ETHSW:
+        {
+            ether_phy_write_ethsw(p_instance_ctrl, reg_addr, data);
+            break;
+        }
+
+        case ETHER_PHY_MDIO_ESC:
+        {
+            ether_phy_write_esc(p_instance_ctrl, reg_addr, data);
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHER_PHY_Write() */
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ETHER_PHY)
+ **********************************************************************************************************************/
+
+/**
+ * Private functions
+ */
+
+#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE)
+
+/*******************************************************************************************************************//**
+ * Parameter error check function for open.
+ *
+ * @param[in] p_instance_ctrl   Pointer to the control block for the channel
+ * @param[in] p_cfg             Pointer to pin configuration structure
+ *
+ * @retval  FSP_SUCCESS                  No parameter error found
+ * @retval  FSP_ERR_ASSERTION            Pointer to ETHER control block or configuration structure is NULL
+ * @retval  FSP_ERR_ALREADY_OPEN         Control block has already been opened
+ * @retval  FSP_ERR_INVALID_CHANNEL      Invalid channel number is given.
+ * @retval  FSP_ERR_INVALID_ARGUMENT     Irq number lower then 0.
+ * @retval  FSP_ERR_INVALID_POINTER      Pointer to p_cfg or p_extend is NULL.
+ **********************************************************************************************************************/
+static fsp_err_t ether_phy_open_param_check (ether_phy_instance_ctrl_t   * p_instance_ctrl,
+                                             ether_phy_cfg_t const * const p_cfg)
+{
+    ether_phy_extend_cfg_t * p_extend;
+
+    FSP_ASSERT(p_instance_ctrl);
+    ETHER_PHY_ERROR_RETURN(NULL != p_cfg, FSP_ERR_INVALID_POINTER);
+    ETHER_PHY_ERROR_RETURN(NULL != p_cfg->p_extend, FSP_ERR_INVALID_POINTER);
+
+    p_extend = (ether_phy_extend_cfg_t *) p_cfg->p_extend;
+
+    ETHER_PHY_ERROR_RETURN((ETHER_PHY_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN);
+    ETHER_PHY_ERROR_RETURN((BSP_FEATURE_ETHER_PHY_MAX_CHANNELS > p_cfg->channel), FSP_ERR_INVALID_CHANNEL);
+
+    ETHER_PHY_ERROR_RETURN(((ETHER_PHY_MDIO_GMAC == p_extend->mdio_type) ||
+                            (ETHER_PHY_MDIO_ETHSW == p_extend->mdio_type) ||
+ #if defined(BSP_MCU_GROUP_RZN2H)
+                            (ETHER_PHY_MDIO_GMAC1 == p_extend->mdio_type) ||
+                            (ETHER_PHY_MDIO_GMAC2 == p_extend->mdio_type) ||
+ #endif
+                            (ETHER_PHY_MDIO_ESC == p_extend->mdio_type)),
+                           FSP_ERR_INVALID_ARGUMENT);
+
+    ETHER_PHY_ERROR_RETURN(((ETHER_PHY_SPEED_10_100 == p_extend->bps) ||
+                            (ETHER_PHY_SPEED_10_1000 == p_extend->bps) ||
+                            (ETHER_PHY_SPEED_10 == p_extend->bps) ||
+                            (ETHER_PHY_SPEED_100 == p_extend->bps) ||
+                            (ETHER_PHY_SPEED_1000 == p_extend->bps)),
+                           FSP_ERR_INVALID_ARGUMENT);
+
+    ETHER_PHY_ERROR_RETURN(((ETHER_PHY_DUPLEX_HALF == p_extend->duplex) ||
+                            (ETHER_PHY_DUPLEX_FULL == p_extend->duplex)),
+                           FSP_ERR_INVALID_ARGUMENT);
+
+    return FSP_SUCCESS;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Get link speed for selector deiver.
+ *
+ * @param[in]   bps     Configured link speed for PHY driver
+ *
+ * @retval  Link speed for selector deiver
+ **********************************************************************************************************************/
+static ether_selector_speed_t ether_phy_get_selector_speed (ether_phy_speed_t bps)
+{
+    ether_selector_speed_t selector_speed;
+
+    switch (bps)
+    {
+        case ETHER_PHY_SPEED_10_100:
+        {
+            selector_speed = ETHER_SELECTOR_SPEED_100_MBPS;
+            break;
+        }
+
+        case ETHER_PHY_SPEED_10_1000:
+        {
+            selector_speed = ETHER_SELECTOR_SPEED_1000_MBPS;
+            break;
+        }
+
+        case ETHER_PHY_SPEED_10:
+        {
+            selector_speed = ETHER_SELECTOR_SPEED_10_MBPS;
+            break;
+        }
+
+        case ETHER_PHY_SPEED_100:
+        {
+            selector_speed = ETHER_SELECTOR_SPEED_100_MBPS;
+            break;
+        }
+
+        case ETHER_PHY_SPEED_1000:
+        {
+            selector_speed = ETHER_SELECTOR_SPEED_1000_MBPS;
+            break;
+        }
+
+        default:
+        {
+            selector_speed = (ether_selector_speed_t) -1;
+            break;
+        }
+    }
+
+    return selector_speed;
+}
+
+/*******************************************************************************************************************//**
+ * Get duplex for selector deiver.
+ *
+ * @param[in]   duplex  Configured duplex for PHY driver
+ *
+ * @retval  Duplex for selector deiver
+ **********************************************************************************************************************/
+static ether_selector_duplex_t ether_phy_get_selector_duplex (ether_phy_duplex_t duplex)
+{
+    ether_selector_duplex_t selector_duplex;
+
+    switch (duplex)
+    {
+        case ETHER_PHY_DUPLEX_HALF:
+        {
+            selector_duplex = ETHER_SELECTOR_DUPLEX_HALF;
+            break;
+        }
+
+        case ETHER_PHY_DUPLEX_FULL:
+        {
+            selector_duplex = ETHER_SELECTOR_DUPLEX_FULL;
+            break;
+        }
+
+        default:
+            selector_duplex = (ether_selector_duplex_t) -1;
+    }
+
+    return selector_duplex;
+}
+
+/*******************************************************************************************************************//**
+ * PHY reset
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[in]   p_cfg               Pointer to pin configuration structure
+ *
+ * @retval  FSP_SUCCESS                                 Successfully
+ * @retval  FSP_ERR_TIMEOUT                             Reset timeout
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_INVALID_POINTER                     Pointer to read buffer is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Address or data is not a valid size
+ **********************************************************************************************************************/
+fsp_err_t ether_phy_reset (ether_phy_instance_ctrl_t * p_instance_ctrl, ether_phy_cfg_t const * const p_cfg)
+{
+    bool phy_state_initialized;
+    static bsp_io_port_pin_t g_phy_reset_pin_initialized[BSP_FEATURE_ETHER_PHY_MAX_CHANNELS] = {(bsp_io_port_pin_t) 0U};
+    uint32_t                 index;
+    ether_phy_extend_cfg_t * p_extend = (ether_phy_extend_cfg_t *) p_cfg->p_extend;
+    fsp_err_t                err      = FSP_SUCCESS;
+
+    phy_state_initialized = false;
+
+    for (index = 0U; index < BSP_FEATURE_ETHER_PHY_MAX_CHANNELS; index++)
+    {
+        if (g_phy_reset_pin_initialized[index] == p_extend->phy_reset_pin)
+        {
+            phy_state_initialized = true;
+            break;
+        }
+    }
+
+    g_phy_reset_pin_initialized[p_cfg->channel] = p_extend->phy_reset_pin;
+
+    if (!phy_state_initialized)
+    {
+        /* This code uses BSP IO functions to show how it is used.*/
+        R_BSP_PinAccessEnable();
+
+        /* Write Low-output to ESC_RESETOUT# as PHY reset */
+        R_BSP_PinClear(R_BSP_IoRegionGet(p_extend->phy_reset_pin), p_extend->phy_reset_pin);
+
+        /* Assertion time for reset  */
+        R_BSP_SoftwareDelay(p_extend->phy_reset_time, BSP_DELAY_UNITS_MICROSECONDS);
+
+        /* Write High-output to ESC_RESETOUT# as release */
+        R_BSP_PinSet(R_BSP_IoRegionGet(p_extend->phy_reset_pin), p_extend->phy_reset_pin);
+
+        /* Delay after release */
+        R_BSP_SoftwareDelay(p_extend->phy_reset_time, BSP_DELAY_UNITS_MICROSECONDS);
+
+        /* Protect PFS registers */
+        R_BSP_PinAccessDisable();
+    }
+    else
+    {
+        if (ETHER_PHY_AUTO_NEGOTIATION_ON == p_extend->auto_negotiation)
+        {
+            uint32_t reg;
+            uint32_t count = 0;
+
+            /* Reset PHY by soft */
+            R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_CONTROL, ETHER_PHY_CONTROL_RESET);
+
+            while (1)
+            {
+                R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_CONTROL, &reg);
+
+                if ((ETHER_PHY_REGISTER_READ_ERROR != (reg & ETHER_PHY_REGISTER_READ_ERROR)) &&
+                    (0 == (reg & ETHER_PHY_CONTROL_RESET)))
+                {
+                    break;
+                }
+
+                if (count > p_cfg->phy_reset_wait_time)
+                {
+                    err = FSP_ERR_TIMEOUT;
+                    break;
+                }
+
+                count++;
+            }
+        }
+    }
+
+    return err;
+}                                      /* End of function ether_phy_reset() */
+
+/*******************************************************************************************************************//**
+ * Sets the communication conditions when auto-negotiation is OFF.
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval  FSP_SUCCESS                                 Successfully
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Invalid arguments.
+ **********************************************************************************************************************/
+fsp_err_t ether_phy_set_auto_negotiate_off (ether_phy_instance_ctrl_t * p_instance_ctrl)
+{
+    ether_phy_extend_cfg_t * p_extend = (ether_phy_extend_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend;
+
+    uint32_t reg = 0;
+
+    switch (p_extend->bps)
+    {
+        case ETHER_PHY_SPEED_10:
+        {
+            break;
+        }
+
+        case ETHER_PHY_SPEED_100:
+        {
+            reg |= ETHER_PHY_CONTROL_100_MBPS;
+            break;
+        }
+
+        case ETHER_PHY_SPEED_1000:
+        {
+            reg |= ETHER_PHY_CONTROL_SPEED_SELCT;
+            break;
+        }
+
+        case ETHER_PHY_SPEED_10_100:
+        case ETHER_PHY_SPEED_10_1000:
+        default:
+
+            return FSP_ERR_INVALID_ARGUMENT;
+    }
+
+    switch (p_extend->duplex)
+    {
+        case ETHER_PHY_DUPLEX_HALF:
+        {
+            reg &= ~(uint32_t) ETHER_PHY_CONTROL_FULL_DUPLEX;
+            break;
+        }
+
+        case ETHER_PHY_DUPLEX_FULL:
+        {
+            reg |= ETHER_PHY_CONTROL_FULL_DUPLEX;
+            break;
+        }
+
+        default:
+
+            return FSP_ERR_INVALID_ARGUMENT;
+    }
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_CONTROL, reg);
+
+    p_instance_ctrl->local_advertise = 0;
+
+    return FSP_SUCCESS;
+}                                      /* End of function ether_phy_set_auto_negotiate_off() */
+
+/*******************************************************************************************************************//**
+ * Sets the advertisement when auto-negotiation is ON.
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval  FSP_SUCCESS                                 Successfully
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Invalid arguments.
+ **********************************************************************************************************************/
+fsp_err_t ether_phy_set_auto_negotiate_on (ether_phy_instance_ctrl_t * p_instance_ctrl)
+{
+    ether_phy_extend_cfg_t * p_extend = (ether_phy_extend_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend;
+
+    uint32_t reg_adv = ETHER_PHY_AN_ADVERTISEMENT_SELECTOR;
+    uint32_t reg_ctr = 0;
+
+    switch (p_extend->bps)
+    {
+        case ETHER_PHY_SPEED_10_100:
+        {
+            if (ETHER_PHY_DUPLEX_FULL == p_extend->duplex)
+            {
+                reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_10H |
+                           ETHER_PHY_AN_ADVERTISEMENT_100H |
+                           ETHER_PHY_AN_ADVERTISEMENT_10F |
+                           ETHER_PHY_AN_ADVERTISEMENT_100F;
+            }
+            else
+            {
+                reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_10H |
+                           ETHER_PHY_AN_ADVERTISEMENT_100H;
+            }
+
+            break;
+        }
+
+        case ETHER_PHY_SPEED_10_1000:
+        {
+            if (ETHER_PHY_DUPLEX_FULL == p_extend->duplex)
+            {
+                reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_10H |
+                           ETHER_PHY_AN_ADVERTISEMENT_100H |
+                           ETHER_PHY_AN_ADVERTISEMENT_10F |
+                           ETHER_PHY_AN_ADVERTISEMENT_100F;
+
+                reg_ctr |= ETHER_PHY_1000BT_CONTROL_1000H |
+                           ETHER_PHY_1000BT_CONTROL_1000F;
+            }
+            else
+            {
+                reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_10H |
+                           ETHER_PHY_AN_ADVERTISEMENT_100H;
+
+                reg_ctr |= ETHER_PHY_1000BT_CONTROL_1000H;
+            }
+
+            break;
+        }
+
+        case ETHER_PHY_SPEED_10:
+        {
+            if (ETHER_PHY_DUPLEX_FULL == p_extend->duplex)
+            {
+                reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_10H |
+                           ETHER_PHY_AN_ADVERTISEMENT_10F;
+            }
+            else
+            {
+                reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_10H;
+            }
+
+            break;
+        }
+
+        case ETHER_PHY_SPEED_100:
+        {
+            if (ETHER_PHY_DUPLEX_FULL == p_extend->duplex)
+            {
+                reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_100H |
+                           ETHER_PHY_AN_ADVERTISEMENT_100F;
+            }
+            else
+            {
+                reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_100H;
+            }
+
+            break;
+        }
+
+        case ETHER_PHY_SPEED_1000:
+        {
+            if (ETHER_PHY_DUPLEX_FULL == p_extend->duplex)
+            {
+                reg_ctr |= ETHER_PHY_1000BT_CONTROL_1000H |
+                           ETHER_PHY_1000BT_CONTROL_1000F;
+            }
+            else
+            {
+                reg_ctr |= ETHER_PHY_1000BT_CONTROL_1000H;
+            }
+
+            break;
+        }
+
+        default:
+
+            return FSP_ERR_INVALID_ARGUMENT;
+    }
+
+    /* When pause frame is used */
+    if (ETHER_PHY_FLOW_CONTROL_ENABLE == p_instance_ctrl->p_ether_phy_cfg->flow_control)
+    {
+        reg_adv |= ETHER_PHY_AN_ADVERTISEMENT_ASM_DIR |
+                   ETHER_PHY_AN_ADVERTISEMENT_PAUSE;
+    }
+
+    p_instance_ctrl->local_advertise = reg_adv;
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_AN_ADVERTISEMENT, reg_adv);
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_1000BT_CONTROL, reg_ctr);
+
+    return FSP_SUCCESS;
+}                                      /* End of function ether_phy_set_auto_negotiate_on() */
+
+/********************************************************************************************************************//**
+ * Gets link ability when auto-negotiation is OFF.
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[out] p_line_speed_duplex  Pointer to the location of both the line speed and the duplex.
+ * @param[out] p_local_pause        Pointer to the location to store the local pause bits.
+ * @param[out] p_partner_pause      Pointer to the location to store the partner pause bits.
+ *
+ * @retval  FSP_SUCCESS                                 ETHER_PHY successfully get link partner ability.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Address or data is not a valid size
+ * @retval  FSP_ERR_INVALID_POINTER                     Pointer to read buffer is NULL.
+ ***********************************************************************************************************************/
+fsp_err_t ether_phy_get_ability_auto_negotiate_off (ether_phy_instance_ctrl_t * p_instance_ctrl,
+                                                    uint32_t * const            p_line_speed_duplex,
+                                                    uint32_t * const            p_local_pause,
+                                                    uint32_t * const            p_partner_pause)
+{
+    uint32_t reg;
+
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_CONTROL, &reg);
+
+    if (ETHER_PHY_CONTROL_SPEED_SELCT == (reg & ETHER_PHY_CONTROL_SPEED_SELCT))
+    {
+        if (ETHER_PHY_CONTROL_FULL_DUPLEX == (reg & ETHER_PHY_CONTROL_FULL_DUPLEX))
+        {
+            (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_1000F;
+        }
+        else
+        {
+            (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_1000H;
+        }
+    }
+    else if (ETHER_PHY_CONTROL_100_MBPS == (reg & ETHER_PHY_CONTROL_100_MBPS))
+    {
+        if (ETHER_PHY_CONTROL_FULL_DUPLEX == (reg & ETHER_PHY_CONTROL_FULL_DUPLEX))
+        {
+            (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_100F;
+        }
+        else
+        {
+            (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_100H;
+        }
+    }
+    else
+    {
+        if (ETHER_PHY_CONTROL_FULL_DUPLEX == (reg & ETHER_PHY_CONTROL_FULL_DUPLEX))
+        {
+            (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_10F;
+        }
+        else
+        {
+            (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_10H;
+        }
+    }
+
+    *p_local_pause   = 0;
+    *p_partner_pause = 0;
+
+    return FSP_SUCCESS;
+}                                      /* End of function ether_phy_get_ability_auto_negotiate_off() */
+
+/********************************************************************************************************************//**
+ * Gets link ability when auto-negotiation is ON.
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[out] p_line_speed_duplex  Pointer to the location of both the line speed and the duplex.
+ * @param[out] p_local_pause        Pointer to the location to store the local pause bits.
+ * @param[out] p_partner_pause      Pointer to the location to store the partner pause bits.
+ *
+ * @retval  FSP_SUCCESS                                 ETHER_PHY successfully get link partner ability.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER_PHY control block is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Address or data is not a valid size
+ * @retval  FSP_ERR_INVALID_POINTER                     Pointer to read buffer is NULL.
+ * @retval  FSP_ERR_ETHER_PHY_ERROR_LINK                PHY-LSI is not link up.
+ * @retval  FSP_ERR_ETHER_PHY_NOT_READY                 The auto-negotiation isn't completed
+ ***********************************************************************************************************************/
+fsp_err_t ether_phy_get_ability_auto_negotiate_on (ether_phy_instance_ctrl_t * p_instance_ctrl,
+                                                   uint32_t * const            p_line_speed_duplex,
+                                                   uint32_t * const            p_local_pause,
+                                                   uint32_t * const            p_partner_pause)
+{
+    uint32_t reg_status;
+    uint32_t reg_4  = 0U;
+    uint32_t reg_5  = 0U;
+    uint32_t reg_9  = 0U;
+    uint32_t reg_10 = 0U;
+
+    /* Because reading the first time shows the previous state, the Link status bit is read twice. */
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_STATUS, &reg_status);
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_STATUS, &reg_status);
+
+    /* When the link isn't up, return error */
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_STATUS_LINK_UP == (reg_status & ETHER_PHY_STATUS_LINK_UP),
+                           FSP_ERR_ETHER_PHY_ERROR_LINK);
+
+    /* When the auto-negotiation isn't completed, return error */
+    ETHER_PHY_ERROR_RETURN(ETHER_PHY_STATUS_AN_COMPLETE == (reg_status & ETHER_PHY_STATUS_AN_COMPLETE),
+                           FSP_ERR_ETHER_PHY_NOT_READY);
+
+    reg_4 = p_instance_ctrl->local_advertise;
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_AN_LINK_PARTNER, &reg_5);
+
+    /* Establish local pause capability */
+    *p_local_pause = 0;
+
+    if (ETHER_PHY_AN_ADVERTISEMENT_PAUSE == (reg_4 & ETHER_PHY_AN_ADVERTISEMENT_PAUSE))
+    {
+        (*p_local_pause) |= (1 << 1);
+    }
+
+    if (ETHER_PHY_AN_ADVERTISEMENT_ASM_DIR == (reg_4 & ETHER_PHY_AN_ADVERTISEMENT_ASM_DIR))
+    {
+        (*p_local_pause) |= 1;
+    }
+
+    /* Establish partner pause capability */
+    *p_partner_pause = 0;
+
+    if (ETHER_PHY_AN_LINK_PARTNER_PAUSE == (reg_5 & ETHER_PHY_AN_LINK_PARTNER_PAUSE))
+    {
+        (*p_partner_pause) |= (1 << 1);
+    }
+
+    if (ETHER_PHY_AN_LINK_PARTNER_ASM_DIR == (reg_5 & ETHER_PHY_AN_LINK_PARTNER_ASM_DIR))
+    {
+        (*p_partner_pause) |= 1;
+    }
+
+    if ((ETHER_PHY_AN_LINK_PARTNER_10H == (reg_5 & ETHER_PHY_AN_LINK_PARTNER_10H)) &&
+        (ETHER_PHY_AN_ADVERTISEMENT_10H == (reg_4 & ETHER_PHY_AN_ADVERTISEMENT_10H)))
+    {
+        (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_10H;
+    }
+
+    if ((ETHER_PHY_AN_LINK_PARTNER_10F == (reg_5 & ETHER_PHY_AN_LINK_PARTNER_10F)) &&
+        (ETHER_PHY_AN_ADVERTISEMENT_10F == (reg_4 & ETHER_PHY_AN_ADVERTISEMENT_10F)))
+    {
+        (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_10F;
+    }
+
+    if ((ETHER_PHY_AN_LINK_PARTNER_100H == (reg_5 & ETHER_PHY_AN_LINK_PARTNER_100H)) &&
+        (ETHER_PHY_AN_ADVERTISEMENT_100H == (reg_4 & ETHER_PHY_AN_ADVERTISEMENT_100H)))
+    {
+        (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_100H;
+    }
+
+    if ((ETHER_PHY_AN_LINK_PARTNER_100F == (reg_5 & ETHER_PHY_AN_LINK_PARTNER_100F)) &&
+        (ETHER_PHY_AN_ADVERTISEMENT_100F == (reg_4 & ETHER_PHY_AN_ADVERTISEMENT_100F)))
+    {
+        (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_100F;
+    }
+
+    if (reg_status & ETHER_PHY_STATUS_EX_STATUS)
+    {
+        R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_1000BT_CONTROL, &reg_9);
+        R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_1000BT_STATUS, &reg_10);
+
+        if ((ETHER_PHY_1000BT_STATUS_PARTNER_1000H == (reg_10 & ETHER_PHY_1000BT_STATUS_PARTNER_1000H)) &&
+            (ETHER_PHY_1000BT_CONTROL_1000H == (reg_9 & ETHER_PHY_1000BT_CONTROL_1000H)))
+        {
+            (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_1000H;
+        }
+
+        if ((ETHER_PHY_1000BT_STATUS_PARTNER_1000F == (reg_10 & ETHER_PHY_1000BT_STATUS_PARTNER_1000F)) &&
+            (ETHER_PHY_1000BT_CONTROL_1000F == (reg_9 & ETHER_PHY_1000BT_CONTROL_1000F)))
+        {
+            (*p_line_speed_duplex) = ETHER_PHY_LINK_SPEED_1000F;
+        }
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function ether_phy_get_ability_auto_negotiate_on() */
+
+/********************************************************************************************************************//**
+ * Convert link speed and duplex for sector driver
+ *
+ * @param[in]   line_speed_duple    Link speed and duplex
+ * @param[out]  p_selector_speed    Speed for sector driver
+ * @param[out]  p_selector_duplex   Duplex for sector driver
+ *
+ * @retval  none
+ ***********************************************************************************************************************/
+void ether_phy_convert_speed_duplex (uint32_t                  line_speed_duple,
+                                     ether_selector_speed_t  * p_selector_speed,
+                                     ether_selector_duplex_t * p_selector_duplex)
+{
+    switch (line_speed_duple)
+    {
+        case ETHER_PHY_LINK_SPEED_10H:
+        {
+            *p_selector_speed  = ETHER_SELECTOR_SPEED_10_MBPS;
+            *p_selector_duplex = ETHER_SELECTOR_DUPLEX_HALF;
+            break;
+        }
+
+        case ETHER_PHY_LINK_SPEED_10F:
+        {
+            *p_selector_speed  = ETHER_SELECTOR_SPEED_10_MBPS;
+            *p_selector_duplex = ETHER_SELECTOR_DUPLEX_FULL;
+            break;
+        }
+
+        case ETHER_PHY_LINK_SPEED_100H:
+        {
+            *p_selector_speed  = ETHER_SELECTOR_SPEED_100_MBPS;
+            *p_selector_duplex = ETHER_SELECTOR_DUPLEX_HALF;
+            break;
+        }
+
+        case ETHER_PHY_LINK_SPEED_100F:
+        {
+            *p_selector_speed  = ETHER_SELECTOR_SPEED_100_MBPS;
+            *p_selector_duplex = ETHER_SELECTOR_DUPLEX_FULL;
+            break;
+        }
+
+        case ETHER_PHY_LINK_SPEED_1000H:
+        {
+            *p_selector_speed  = ETHER_SELECTOR_SPEED_1000_MBPS;
+            *p_selector_duplex = ETHER_SELECTOR_DUPLEX_HALF;
+            break;
+        }
+
+        case ETHER_PHY_LINK_SPEED_1000F:
+        default:
+        {
+            *p_selector_speed  = ETHER_SELECTOR_SPEED_1000_MBPS;
+            *p_selector_duplex = ETHER_SELECTOR_DUPLEX_FULL;
+            break;
+        }
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Reads a PHY register by GMAC control
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[in]   reg_addr            Address of the PHY register
+ * @param[out]  p_data              Pointer to the location to store read data.
+ *
+ * @retval      read value
+ **********************************************************************************************************************/
+#if defined(BSP_MCU_GROUP_RZN2H)
+void ether_phy_read_gmac (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t * const p_data)
+{
+    volatile R_GMAC_Type * p_reg_etherc = (R_GMAC_Type *) p_instance_ctrl->p_reg_etherc;
+    uint32_t               timeout;
+    uint32_t               val_tmp;
+
+    val_tmp =
+        ((p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << ETHER_PHY_MDIO_ADDRESS_PA_SHIFT) &
+         ETHER_PHY_MDIO_ADDRESS_PA_MASK) |
+        ((reg_addr << ETHER_PHY_MDIO_ADDRESS_RDA_SHIFT) & ETHER_PHY_MDIO_ADDRESS_RDA_MASK) |                /* phy reg address */
+        ((ETHER_PHY_MDIO_ADDRESS_CR << ETHER_PHY_MDIO_ADDRESS_CR_SHIFT) & ETHER_PHY_MDIO_ADDRESS_CR_MASK) | /* clock range */
+        ETHER_PHY_MDIO_ADDRESS_READ |                                                                       /* mode read */
+        ETHER_PHY_MDIO_ADDRESS_GB;                                                                          /* busy */
+
+    p_reg_etherc->MAC_MDIO_Address = val_tmp;
+
+    /* calculate timeout based on current timestamp */
+    timeout = ETHER_PHY_TIMEOUT_COUNT;
+
+    while (1)
+    {
+        /* Wait read complete */
+        if (!(p_reg_etherc->MAC_MDIO_Address_b.GB))
+        {
+            *p_data = p_reg_etherc->MAC_MDIO_Data_b.GD;
+            break;
+        }
+
+        if (0 == timeout)
+        {
+            /* Timeout */
+            *p_data = ETHER_PHY_REGISTER_READ_ERROR;
+            break;
+        }
+
+        timeout--;
+    }
+}                                      /* End of function ether_phy_read_gmac() */
+
+#else                                  // !BSP_MCU_GROUP_RZN2H
+
+void ether_phy_read_gmac (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t * const p_data)
+{
+    volatile R_GMAC_Type * p_reg_etherc = (R_GMAC_Type *) p_instance_ctrl->p_reg_etherc;
+    uint32_t               timeout;
+    uint32_t               val_tmp;
+
+    val_tmp =
+        ((p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << ETHER_PHY_GMII_ADDRESS_PA_SHIFT) &
+         ETHER_PHY_GMII_ADDRESS_PA_MASK) |
+        ((reg_addr << ETHER_PHY_GMII_ADDRESS_GR_SHIFT) & ETHER_PHY_GMII_ADDRESS_GR_MASK) | ///< Phy reg address
+        ETHER_PHY_GMII_ADDRESS_CR |                                                        ///< Speed
+        ETHER_PHY_GMII_ADDRESS_GB;                                                         ///< Busy
+
+    p_reg_etherc->GMII_Address = val_tmp;
+
+    /* calculate timeout based on current timestamp */
+    timeout = ETHER_PHY_TIMEOUT_COUNT;
+
+    while (1)
+    {
+        /* Wait read complete */
+        if (!(p_reg_etherc->GMII_Address_b.GB))
+        {
+            *p_data = p_reg_etherc->GMII_Data & ETHER_PHY_16BIT_DATA_MASK;
+            break;
+        }
+
+        if (0 == timeout)
+        {
+            /* Timeout */
+            *p_data = ETHER_PHY_REGISTER_READ_ERROR;
+            break;
+        }
+
+        timeout--;
+    }
+}                                      /* End of function ether_phy_read_gmac() */
+
+#endif                                 // !BSP_MCU_GROUP_RZN2H
+
+/*******************************************************************************************************************//**
+ * Reads a PHY register by ETHSW control
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[in]   reg_addr            Address of the PHY register
+ * @param[out]  p_data              Pointer to the location to store read data.
+ *
+ * @retval      read value
+ **********************************************************************************************************************/
+void ether_phy_read_ethsw (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t * const p_data)
+{
+    R_ETHSW_Type * p_Reg_Ethsw = (R_ETHSW_Type *) p_instance_ctrl->p_reg_etherc;
+    uint32_t       timeout;
+    uint32_t       reg;
+
+    /* initialize and execute read command */
+    reg  = reg_addr & ETHER_PHY_ETHSW_MDIO_COMMAND_REGADDR_MASK;
+    reg |= ((p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << ETHER_PHY_ETHSW_MDIO_COMMAND_PHYADDR_SHIFT) &
+            ETHER_PHY_ETHSW_MDIO_COMMAND_PHYADDR_MASK);
+    reg |= ETHER_PHY_ETHSW_MDIO_COMMAND_TRANINIT_READ;
+
+    p_Reg_Ethsw->MDIO_COMMAND = reg;
+
+    /* calculate timeout based on current timestamp */
+    timeout = ETHER_PHY_TIMEOUT_COUNT;
+
+    /* wait until MDIO is ready */
+    while (1)
+    {
+        reg = p_Reg_Ethsw->MDIO_CFG_STATUS;
+
+        if (ETHER_PHY_ETHSW_MDIO_CFG_STATUS_BUSY != (reg & ETHER_PHY_ETHSW_MDIO_CFG_STATUS_BUSY))
+        {
+            if (ETHER_PHY_ETHSW_MDIO_CFG_STATUS_READERR != (reg & ETHER_PHY_ETHSW_MDIO_CFG_STATUS_READERR))
+            {
+                *p_data = p_Reg_Ethsw->MDIO_DATA & ETHER_PHY_16BIT_DATA_MASK;
+            }
+            else
+            {
+                *p_data = ETHER_PHY_REGISTER_READ_ERROR;
+            }
+
+            break;
+        }
+
+        if (0 == timeout)
+        {
+            /* Timeout */
+            *p_data = ETHER_PHY_REGISTER_READ_ERROR;
+            break;
+        }
+
+        timeout--;
+    }
+}                                      /* End of function ether_phy_read_ethsw() */
+
+/*******************************************************************************************************************//**
+ * Reads a PHY register by ESC control
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[in]   reg_addr            Address of the PHY register
+ * @param[out]  p_data              Pointer to the location to store read data.
+ *
+ * @retval      read value
+ **********************************************************************************************************************/
+void ether_phy_read_esc (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t * const p_data)
+{
+    R_ESC_Type * p_Reg_Esc = (R_ESC_Type *) p_instance_ctrl->p_reg_etherc;
+    uint32_t     timeout;
+    fsp_err_t    err = FSP_SUCCESS;
+
+    /* WAIT_LOOP */
+    timeout = ETHER_PHY_TIMEOUT_COUNT;
+    while (p_Reg_Esc->MII_CONT_STAT_b.BUSY == 1)
+    {
+        if (0 == timeout)
+        {
+            /* Timeout */
+            err = FSP_ERR_TIMEOUT;
+            break;
+        }
+
+        timeout--;
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Get PDI access right */
+        p_Reg_Esc->MII_PDI_ACS_STAT_b.ACSMII = 1;
+
+        /* WAIT_LOOP */
+        timeout = ETHER_PHY_TIMEOUT_COUNT;
+        while (p_Reg_Esc->MII_ECAT_ACS_STAT_b.ACSMII == 1)
+        {
+            if (0 == timeout)
+            {
+                /* Timeout */
+                err = FSP_ERR_TIMEOUT;
+                break;
+            }
+
+            timeout--;
+        }
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Read PHY register */
+        p_Reg_Esc->PHY_ADR       = p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address;
+        p_Reg_Esc->PHY_REG_ADR   = (uint8_t) reg_addr;
+        p_Reg_Esc->MII_CONT_STAT = (1 << 8) | (1 << 0); ///< Read command
+
+        /* WAIT_LOOP */
+        timeout = ETHER_PHY_TIMEOUT_COUNT;
+        while (p_Reg_Esc->MII_CONT_STAT_b.BUSY == 1)
+        {
+            if (0 == timeout)
+            {
+                /* Timeout */
+                err = FSP_ERR_TIMEOUT;
+                break;
+            }
+
+            timeout--;
+        }
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Check the error bit */
+        if ((p_Reg_Esc->MII_CONT_STAT_b.CMDERR == 1) ||
+            (p_Reg_Esc->MII_CONT_STAT_b.READERR == 1))
+        {
+            /* Error operation */
+
+            // Clear error bit
+            // p_Reg_Esc->MIICONTSTAT.WORD = 0x0000;
+        }
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Get read data */
+        *p_data = p_Reg_Esc->PHY_DATA;
+
+        /* Give the access right to ECAT */
+        p_Reg_Esc->MII_PDI_ACS_STAT_b.ACSMII = 0;
+    }
+    else
+    {
+        *p_data = ETHER_PHY_REGISTER_READ_ERROR;
+    }
+}                                      /* End of function ether_phy_read_esc() */
+
+/***********************************************************************************************************************
+ * Writes to a PHY register by GMAC control
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[in]   reg_addr            Address of the PHY register
+ * @param[in]   data                Data written to register.
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+#if defined(BSP_MCU_GROUP_RZN2H)
+
+void ether_phy_write_gmac (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t data)
+{
+    volatile R_GMAC_Type * p_reg_etherc = (R_GMAC_Type *) p_instance_ctrl->p_reg_etherc;
+    uint32_t               timeout;
+    uint32_t               val_tmp;
+
+    val_tmp =
+        ((p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << ETHER_PHY_MDIO_ADDRESS_PA_SHIFT) &
+         ETHER_PHY_MDIO_ADDRESS_PA_MASK) |
+        ((reg_addr << ETHER_PHY_MDIO_ADDRESS_RDA_SHIFT) & ETHER_PHY_MDIO_ADDRESS_RDA_MASK) |                /* phy reg address */
+        ((ETHER_PHY_MDIO_ADDRESS_CR << ETHER_PHY_MDIO_ADDRESS_CR_SHIFT) & ETHER_PHY_MDIO_ADDRESS_CR_MASK) | /* clock range */
+        ETHER_PHY_MDIO_ADDRESS_WRITE |                                                                      /* mode write */
+        ETHER_PHY_MDIO_ADDRESS_GB;                                                                          /* busy */
+
+    p_reg_etherc->MAC_MDIO_Data_b.GD = (uint16_t) data;
+    p_reg_etherc->MAC_MDIO_Address   = val_tmp;
+
+    /* calculate timeout based on current timestamp */
+    timeout = ETHER_PHY_TIMEOUT_COUNT;
+
+    while (1)
+    {
+        /* wait write complete */
+        if (!(p_reg_etherc->MAC_MDIO_Address_b.GB))
+        {
+            /* Sucess */
+            break;
+        }
+
+        if (0 == timeout)
+        {
+            /* Timeout */
+            break;
+        }
+
+        timeout--;
+    }
+}                                      /* End of function ether_phy_write_gmac() */
+
+#else // !BSP_MCU_GROUP_RZN2H
+
+void ether_phy_write_gmac (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t data)
+{
+    volatile R_GMAC_Type * p_reg_etherc = (R_GMAC_Type *) p_instance_ctrl->p_reg_etherc;
+    uint32_t               timeout;
+    uint32_t               val_tmp;
+
+    val_tmp =
+        ((p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << ETHER_PHY_GMII_ADDRESS_PA_SHIFT) &
+         ETHER_PHY_GMII_ADDRESS_PA_MASK) |
+        ((reg_addr << ETHER_PHY_GMII_ADDRESS_GR_SHIFT) & ETHER_PHY_GMII_ADDRESS_GR_MASK) | ///< Phy reg address
+        ETHER_PHY_GMII_ADDRESS_CR |                                                        ///< Speed
+        ETHER_PHY_GMII_ADDRESS_GW |                                                        ///< Write
+        ETHER_PHY_GMII_ADDRESS_GB;                                                         ///< Busy
+
+    p_reg_etherc->GMII_Data    = data;                                                     ///< Set write value
+    p_reg_etherc->GMII_Address = val_tmp;                                                  ///< Write phy register
+
+    /* calculate timeout based on current timestamp */
+    timeout = ETHER_PHY_TIMEOUT_COUNT;
+
+    while (1)
+    {
+        /* wait write complete */
+        if (!(p_reg_etherc->GMII_Address_b.GB))
+        {
+            /* Sucess */
+            break;
+        }
+
+        if (0 == timeout)
+        {
+            /* Timeout */
+            break;
+        }
+
+        timeout--;
+    }
+}                                      /* End of function ether_phy_write_gmac() */
+
+#endif // !BSP_MCU_GROUP_RZN2H
+
+/*******************************************************************************************************************//**
+ * Writes to a PHY register by ETHSW control
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[in]   reg_addr            Address of the PHY register
+ * @param[in]   data                Data written to register.
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ether_phy_write_ethsw (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t data)
+{
+    R_ETHSW_Type * p_Reg_Ethsw = (R_ETHSW_Type *) p_instance_ctrl->p_reg_etherc;
+    uint32_t       timeout;
+    uint32_t       reg;
+
+    /* initialize and execute write command */
+    reg  = reg_addr & ETHER_PHY_ETHSW_MDIO_COMMAND_REGADDR_MASK;
+    reg |= ((p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << ETHER_PHY_ETHSW_MDIO_COMMAND_PHYADDR_SHIFT) &
+            ETHER_PHY_ETHSW_MDIO_COMMAND_PHYADDR_MASK);
+
+    p_Reg_Ethsw->MDIO_COMMAND = reg;
+    p_Reg_Ethsw->MDIO_DATA    = data & ETHER_PHY_16BIT_DATA_MASK;
+
+    /* calculate timeout based on current timestamp */
+    timeout = ETHER_PHY_TIMEOUT_COUNT;
+
+    /* wait until MDIO is ready */
+    while (1)
+    {
+        reg = p_Reg_Ethsw->MDIO_CFG_STATUS;
+
+        if (ETHER_PHY_ETHSW_MDIO_CFG_STATUS_BUSY != (reg & ETHER_PHY_ETHSW_MDIO_CFG_STATUS_BUSY))
+        {
+            break;
+        }
+
+        if (0 == timeout)
+        {
+            /* Timeout */
+            break;
+        }
+
+        timeout--;
+    }
+}                                      /* End of function ether_phy_write_ethsw() */
+
+/*******************************************************************************************************************//**
+ * Writes to a PHY register by ESC control
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ * @param[in]   reg_addr            Address of the PHY register
+ * @param[in]   data                Data written to register.
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ether_phy_write_esc (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, uint32_t data)
+{
+    R_ESC_Type * p_Reg_Esc = (R_ESC_Type *) p_instance_ctrl->p_reg_etherc;
+    uint32_t     timeout;
+    fsp_err_t    err = FSP_SUCCESS;
+
+    /* WAIT_LOOP */
+    timeout = ETHER_PHY_TIMEOUT_COUNT;
+    while (p_Reg_Esc->MII_CONT_STAT_b.BUSY == 1)
+    {
+        if (0 == timeout)
+        {
+            err = FSP_ERR_TIMEOUT;
+            break;
+        }
+
+        timeout--;
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Get PDI access right */
+        p_Reg_Esc->MII_PDI_ACS_STAT_b.ACSMII = 1;
+
+        /* WAIT_LOOP */
+        timeout = ETHER_PHY_TIMEOUT_COUNT;
+        while (p_Reg_Esc->MII_ECAT_ACS_STAT_b.ACSMII == 1)
+        {
+            if (0 == timeout)
+            {
+                err = FSP_ERR_TIMEOUT;
+                break;
+            }
+
+            timeout--;
+        }
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Write PHY register */
+        p_Reg_Esc->PHY_ADR       = p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address;
+        p_Reg_Esc->PHY_REG_ADR   = (uint8_t) reg_addr;
+        p_Reg_Esc->PHY_DATA      = (uint16_t) data;
+        p_Reg_Esc->MII_CONT_STAT = (2 << 8) | (1 << 0); ///< Write command
+
+        /* WAIT_LOOP */
+        timeout = ETHER_PHY_TIMEOUT_COUNT;
+        while (p_Reg_Esc->MII_CONT_STAT_b.BUSY == 1)
+        {
+            if (0 == timeout)
+            {
+                err = FSP_ERR_TIMEOUT;
+                break;
+            }
+
+            timeout--;
+        }
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Check the error bit */
+        if ((p_Reg_Esc->MII_CONT_STAT_b.CMDERR == 1) ||
+            (p_Reg_Esc->MII_CONT_STAT_b.READERR == 1))
+        {
+            /*  Error operation */
+
+            // Clear error bit
+            // p_Reg_Esc->MIICONTSTAT.WORD = 0x0000;
+        }
+
+        /* Give the access right to ECAT */
+        p_Reg_Esc->MII_PDI_ACS_STAT_b.ACSMII = 0;
+    }
+}                                      /* End of function ether_phy_write_esc() */
+
+/*******************************************************************************************************************//**
+ * PHY-LSI specific initialization processing
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ether_phy_targets_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl)
+{
+    switch (p_instance_ctrl->p_ether_phy_cfg->phy_lsi_type)
+    {
+        /* User VSC8541 */
+#if (ETHER_PHY_CFG_TARGET_VSC8541_ENABLE)
+        case ETHER_PHY_LSI_TYPE_VSC8541:
+        {
+            ether_phy_targets_initialize_vsc8541(p_instance_ctrl);
+            break;
+        }
+#endif
+
+        /* User KSZ9131 */
+#if (ETHER_PHY_CFG_TARGET_KSZ9131_ENABLE)
+        case ETHER_PHY_LSI_TYPE_KSZ9131:
+        {
+            ether_phy_targets_initialize_ksz9131(p_instance_ctrl);
+            break;
+        }
+#endif
+
+        /* User KSZ9031 */
+#if (ETHER_PHY_CFG_TARGET_KSZ9031_ENABLE)
+        case ETHER_PHY_LSI_TYPE_KSZ9031:
+        {
+            ether_phy_targets_initialize_ksz9031(p_instance_ctrl);
+            break;
+        }
+#endif
+
+        /* User KSZ8081 */
+#if (ETHER_PHY_CFG_TARGET_KSZ8081_ENABLE)
+        case ETHER_PHY_LSI_TYPE_KSZ8081:
+        {
+            ether_phy_targets_initialize_ksz8081(p_instance_ctrl);
+            break;
+        }
+#endif
+
+        /* User KSZ8041 */
+#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE)
+        case ETHER_PHY_LSI_TYPE_KSZ8041:
+        {
+            ether_phy_targets_initialize_ksz8041(p_instance_ctrl);
+            break;
+        }
+#endif
+
+        /* User custom */
+#if (ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE)
+        case ETHER_PHY_LSI_TYPE_CUSTOM:
+        {
+            if (NULL != p_instance_ctrl->p_ether_phy_cfg->p_extend)
+            {
+                ether_phy_extend_cfg_t const * p_extend = p_instance_ctrl->p_ether_phy_cfg->p_extend;
+
+                if (NULL != p_extend->p_target_init)
+                {
+                    p_extend->p_target_init(p_instance_ctrl);
+                }
+            }
+
+            break;
+        }
+#endif
+
+        default:
+        {
+            break;
+        }
+    }
+}                                      /* End of function ether_phy_targets_initialize() */
+
+#if (ETHER_PHY_CFG_TARGET_VSC8541_ENABLE)
+
+/*******************************************************************************************************************//**
+ * PHY-LSI specific initialization processing for VSC8541
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ether_phy_targets_initialize_vsc8541 (ether_phy_instance_ctrl_t * p_instance_ctrl)
+{
+    /* Vendor Specific PHY Registers */
+ #define ETHER_PHY_REG_LED_MODE_SELECT                 (0x1D)
+ #define ETHER_PHY_REG_LED_BEHAVIOR                    (0x1E)
+ #define ETHER_PHY_REG_EXTEND_GPIO_PAGE                (0x1F)
+
+ #define ETHER_PHY_REG_LED0_MODE_SELECT_OFFSET         (0x0)
+ #define ETHER_PHY_REG_LED1_MODE_SELECT_OFFSET         (0x4)
+ #define ETHER_PHY_REG_LED0_FEATURE_DISABLE_OFFSET     (0x0)
+ #define ETHER_PHY_REG_LED1_FEATURE_DISABLE_OFFSET     (0x1)
+
+ #define ETHER_PHY_LEDMODE_ANYSPEED_LINK_ACTIVITY      (0x0)
+ #define ETHER_PHY_LEDMODE_1000M_LINK_ACTIVITY         (0x1)
+ #define ETHER_PHY_LEDMODE_100M_LINK_ACTIVITY          (0x2)
+ #define ETHER_PHY_LEDMODE_10M_LINK_ACTIVITY           (0x3)
+ #define ETHER_PHY_LEDMODE_100M_1000M_LINK_ACTIVITY    (0x4)
+ #define ETHER_PHY_LEDMODE_10M_1000M_LINK_ACTIVITY     (0x5)
+ #define ETHER_PHY_LEDMODE_10M_100M_LINK_ACTIVITY      (0x6)
+ #define ETHER_PHY_LEDMODE_BIT_MASK                    (0xF)
+
+    /* Vendor Specific PHY Registers: Extended Page 2 */
+ #define ETHER_PHY_REG_EXPAGE2_RGMII_CTRL              (0x14)
+
+ #define ETHER_PHY_TXCLKDLY_OFFSET                     (0)
+ #define ETHER_PHY_RXCLKDLY_OFFSET                     (4)
+ #define ETHER_PHY_TXCLKDLY_MASK                       (0x7)
+ #define ETHER_PHY_RXCLKDLY_MASK                       (0x7)
+
+    uint32_t reg = 0U;
+
+    /*
+     * When VSC8541-02 of the Microsemi Corporation is used,
+     * the pin that outputs the state of LINK is used combinedly with LINK/ACTIVITY in default.
+     * The setting of the pin is changed so that only the state of LINK is output.
+     * LED Mode Select (0x1D)
+     * b7:4 = 0000b : LED1 mode any speed LINK/ACTIVITY
+     * b3:0 = 0000b : LED0 mode any speed LINK/ACTIVITY
+     * LED Behavior (0x1E)
+     * b1 = 1 : LED1 combination feature disable (link only, duplex only)
+     * b0 = 0 : LED0 combination feature enable  (link/activity)
+     *//* LED Mode Select */
+    R_ETHER_PHY_Write(p_instance_ctrl,
+                      ETHER_PHY_REG_LED_MODE_SELECT,
+                      (ETHER_PHY_LEDMODE_ANYSPEED_LINK_ACTIVITY << ETHER_PHY_REG_LED1_MODE_SELECT_OFFSET) |
+                      (ETHER_PHY_LEDMODE_ANYSPEED_LINK_ACTIVITY << ETHER_PHY_REG_LED0_MODE_SELECT_OFFSET));
+
+    /* LED Behavior */
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_LED_BEHAVIOR, &reg);
+    reg &= ~(1U << ETHER_PHY_REG_LED0_FEATURE_DISABLE_OFFSET);
+    reg |= 1U << ETHER_PHY_REG_LED1_FEATURE_DISABLE_OFFSET;
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_LED_BEHAVIOR, reg);
+}                                      /* End of function ether_phy_targets_initialize() */
+
+#endif /* ETHER_PHY_CFG_TARGET_VSC8541_ENABLE */
+
+#if (ETHER_PHY_CFG_TARGET_KSZ9131_ENABLE)
+
+/*******************************************************************************************************************//**
+ * PHY-LSI specific initialization processing for KSZ9131
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ether_phy_targets_initialize_ksz9131 (ether_phy_instance_ctrl_t * p_instance_ctrl)
+{
+    /* Vendor Specific PHY Registers */
+ #define ETHER_PHY_REG_MMD_ACCESS_CONTROL           (0x0D)
+ #define ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET    (0xE)
+ #define ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA     (0x0E)
+
+ #define ETHER_PHY_MMD_DEVICE_ADDRESS_2             (2)
+
+ #define ETHER_PHY_MMD_REGISTER_77                  (77)
+
+    uint32_t reg;
+
+    /* 2.77 TX DLL */
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_CONTROL,
+                      (0 << ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET | ETHER_PHY_MMD_DEVICE_ADDRESS_2));
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, ETHER_PHY_MMD_REGISTER_77);
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_CONTROL,
+                      (1 << ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET | ETHER_PHY_MMD_DEVICE_ADDRESS_2));
+
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, &reg);
+    reg &= ~(1U << 12);                /* Enable TX DLL */
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, (uint16_t) reg);
+
+    /* Reset TX DLL */
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, &reg);
+    reg |= (1U << 13);                 /* Set Reset bit */
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, (uint16_t) reg);
+
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, &reg);
+    reg &= ~(1U << 13);                /* Clear reset bit */
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, (uint16_t) reg);
+}                                      /* End of function ether_phy_targets_initialize() */
+
+#endif  /* ETHER_PHY_CFG_TARGET_KSZ9131_ENABLE */
+
+#if (ETHER_PHY_CFG_TARGET_KSZ9031_ENABLE)
+
+/*******************************************************************************************************************//**
+ * PHY-LSI specific initialization processing for KSZ9031
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ether_phy_targets_initialize_ksz9031 (ether_phy_instance_ctrl_t * p_instance_ctrl)
+{
+ #define ETHER_PHY_REG_MMD_ACCESS_CONTROL           (0x0D)
+ #define ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA     (0x0E)
+ #define ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET    (0xE)
+ #define ETHER_PHY_REG_LED_OVERRIDE_OFFSET          (0x4)
+
+ #define ETHER_PHY_MMD_DEVICE_ADDRESS_2             (2)
+ #define ETHER_PHY_MMD_REGISTER_0                   (0)
+ #define ETHER_PHY_MMD_REGISTER_6                   (6)
+ #define ETHER_PHY_MMD_REGISTER_8                   (8)
+ #define ETHER_PHY_MMD_REGISTER_77                  (77)
+
+ #define ETHER_PHY_MMD_REGISTER_6_KSZ9031_DATA      (0)
+ #define ETHER_PHY_MMD_REGISTER_8_KSZ9031_DATA      ((31 << 5) | (7 << 0))
+ #define ETHER_PHY_MMD_REGISTER_77_KSZ9031_DATA     (0x0851)
+
+    uint32_t reg;
+
+    /*
+     * When KSZ9031 of the Micrel, Inc. is used,
+     * the pin that outputs the state of LINK is used combinedly with LINK/ACTIVITY in default.
+     * The setting of the pin is changed so that only the state of LINK is output.
+     * MMD Device Addres - 2
+     * MMD Register      - 0
+     * LED Mode Override Mode 2.0.4
+     * b4 = 1 : Single LED Mode (LINK)
+     * b4 = 0 : Dual LED Mode (LINK/ACTIVITY)
+     * The b4 is write only. The value of b4 can be read by b3.
+     */
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_CONTROL,
+                      (0 << ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET | ETHER_PHY_MMD_DEVICE_ADDRESS_2));
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, ETHER_PHY_MMD_REGISTER_0);
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_CONTROL,
+                      (1 << ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET | ETHER_PHY_MMD_DEVICE_ADDRESS_2));
+
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, &reg);
+    reg |= 1 << ETHER_PHY_REG_LED_OVERRIDE_OFFSET;
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, reg);
+
+    /* 2.8 Clock Pad skew */
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_CONTROL,
+                      (0 << ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET | ETHER_PHY_MMD_DEVICE_ADDRESS_2));
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, ETHER_PHY_MMD_REGISTER_8);
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_CONTROL,
+                      (1 << ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET | ETHER_PHY_MMD_DEVICE_ADDRESS_2));
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, ETHER_PHY_MMD_REGISTER_8_KSZ9031_DATA);
+
+    /* 2.6 TX Data Pad skew */
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_CONTROL,
+                      (0 << ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET | ETHER_PHY_MMD_DEVICE_ADDRESS_2));
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, ETHER_PHY_MMD_REGISTER_6);
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_CONTROL,
+                      (1 << ETHER_PHY_REG_MMD_OPERATION_MODE_OFFSET | ETHER_PHY_MMD_DEVICE_ADDRESS_2));
+
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_MMD_ACCESS_REGISTER_DATA, ETHER_PHY_MMD_REGISTER_6_KSZ9031_DATA);
+}                                      /* End of function ether_phy_targets_initialize() */
+
+#endif /* ETHER_PHY_CFG_TARGET_KSZ9031_ENABLE */
+
+#if (ETHER_PHY_CFG_TARGET_KSZ8081_ENABLE)
+
+/*******************************************************************************************************************//**
+ * PHY-LSI specific initialization processing for KSZ8081
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ether_phy_targets_initialize_ksz8081 (ether_phy_instance_ctrl_t * p_instance_ctrl)
+{
+    (void) p_instance_ctrl;
+}                                      /* End of function ether_phy_targets_initialize() */
+
+#endif /* ETHER_PHY_CFG_TARGET_KSZ8081_ENABLE */
+
+#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE)
+
+/*******************************************************************************************************************//**
+ * PHY-LSI specific initialization processing for KSZ8041
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ether_phy_targets_initialize_ksz8041 (ether_phy_instance_ctrl_t * p_instance_ctrl)
+{
+    /* Vendor Specific PHY Registers */
+ #define ETHER_PHY_REG_PHY_CONTROL_1    (0x1E)
+
+    uint32_t reg;
+
+    /*
+     * When KSZ8041NL of the Micrel, Inc. is used,
+     * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default.
+     * The setting of the pin is changed so that only the state of LINK is output.
+     */
+    R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_1, &reg);
+    reg &= ~(1U << 15);
+    reg |= (1U << 14);
+    R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_1, reg);
+}                                      /* End of function ether_phy_targets_initialize() */
+
+#endif /* ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ether_selector/r_ether_selector.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ether_selector/r_ether_selector.c
new file mode 100644
index 00000000..bc72e87f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ether_selector/r_ether_selector.c
@@ -0,0 +1,464 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_ether_selector.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** "ETHS" in ASCII, used to determine if channel is open. */
+#define ETHER_SELECTOR_OPEN                       (('E' << 24U) | ('T' << 16U) | ('H' << 8U) | ('S' << 0U))
+
+/*CONVCTRL[m] register defines*/
+#define ETHER_SELECTOR_FULLD                      (1 << 8)
+#define ETHER_SELECTOR_HALFD                      (0 << 8)
+
+#define ETHER_SELECTOR_CONV_MODE_MASK             (0x1f) /* Mask of Converter operation mode */
+#define ETHER_SELECTOR_CONV_MODE_MII_MODE         (0x00) /* MII mode (Through mode) */
+#define ETHER_SELECTOR_CONV_MODE_RMII_10M_IN      (0x04) /* RMII mode 10Mbps REF_CLK input */
+#define ETHER_SELECTOR_CONV_MODE_RMII_100M_IN     (0x05) /* RMII mode 100Mbps REF_CLK input */
+#define ETHER_SELECTOR_CONV_MODE_RMII_10M_OUT     (0x14) /* RMII mode 10Mbps REF_CLK output */
+#define ETHER_SELECTOR_CONV_MODE_RMII_100M_OUT    (0x15) /* RMII mode 100Mbps REF_CLK output */
+#define ETHER_SELECTOR_CONV_MODE_RGMII_1000M      (0x0a) /* RGMII mode 1000Mbps */
+#define ETHER_SELECTOR_CONV_MODE_RGMII_100M       (0x09) /* RGMII mode 100Mbps */
+#define ETHER_SELECTOR_CONV_MODE_RGMII_10M        (0x08) /* RGMII mode 10Mbps */
+
+#define ETHER_SELECTOR_CONV_BIT_SPEED_10M         (0x00) /* 10Mbps */
+#define ETHER_SELECTOR_CONV_BIT_SPEED_100M        (0x01) /* 100Mbps */
+#define ETHER_SELECTOR_CONV_BIT_SPEED_1000M       (0x02) /* 1000Mbps */
+#define ETHER_SELECTOR_CONV_BIT_SPEED_MASK        (0x03) /* Mask of Converter speed */
+
+#define ETHER_SELECTOR_CONV_BIT_MODE_MII          (0x00) /* MII mode */
+#define ETHER_SELECTOR_CONV_BIT_MODE_RMII         (0x04) /* RMII mode */
+#define ETHER_SELECTOR_CONV_BIT_MODE_RGMII        (0x08) /* RGMII mode */
+#define ETHER_SELECTOR_CONV_BIT_MODE_MASK         (0x0c) /* Mask of Converter mode */
+
+#define ETHER_SELECTOR_CONV_BIT_REF_CLK_IN        (0x00) /* REF_CLK input */
+#define ETHER_SELECTOR_CONV_BIT_REF_CLK_OUT       (0x10) /* RE_CLK  output */
+#define ETHER_SELECTOR_CONV_BIT_REF_CLK_MASK      (0x10) /* Mask of Converter REF_CLK */
+
+#define ETHER_SELECTOR_MODCTRL_BIT_SWMODE_MASK    (0x07) /* Mask of SW_MODE[2:0] */
+#define ETHER_SELECTOR_PHYLNK_BIT_SWLINK_MASK     (0x07) /* Mask of SWLINK[2:0] */
+#define ETHER_SELECTOR_PHYLNK_BIT_CATLNK_MASK     (0x07) /* Mask of CATLNK[2:0] */
+
+#if defined(BSP_MCU_GROUP_RZN2H)
+ #define ETHER_SELECTOR_CONVRST_BIT_PHYIR_MASK    (0x0F) /* Mask of PHYIR[3:0] */
+#else /* RZN2L */
+ #define ETHER_SELECTOR_CONVRST_BIT_PHYIR_MASK    (0x07) /* Mask of PHYIR[2:0] */
+#endif
+
+/* Key code for PRCMD register */
+#define ETHER_SELECTOR_PRCMD_UNLOCK1              (0x000000A5U)
+#define ETHER_SELECTOR_PRCMD_UNLOCK2              (0x00000001U)
+#define ETHER_SELECTOR_PRCMD_UNLOCK3              (0x0000FFFEU)
+#define ETHER_SELECTOR_PRCMD_UNLOCK4              (0x00000001U)
+#define ETHER_SELECTOR_PRCMD_LOCK                 (0x00000000U)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void r_ether_selector_reg_protection_disable(void * const p_reg_base);
+static void r_ether_selector_reg_protection_enable(void * const p_reg_base);
+static void r_ether_selector_state_initialize(void);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/** ETHER_SELECTOR Implementation of General Timer Driver  */
+const ether_selector_api_t g_ether_selector_on_ether_selector =
+{
+    .open         = R_ETHER_SELECTOR_Open,
+    .converterSet = R_ETHER_SELECTOR_ConverterSet,
+    .close        = R_ETHER_SELECTOR_Close,
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup ETHER_SELECTOR
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes the ETHER_SELECTOR module instance. Implements @ref ether_selector_api_t::open.
+ *
+ *
+ * @retval FSP_SUCCESS                 Ethernet port configuration set successfully.
+ * @retval FSP_ERR_ASSERTION           Pointer to ETHER_SELECTOR control block or configuration structure is NULL.
+ * @retval FSP_ERR_INVALID_CHANNEL     Invalid channel number is given.
+ * @retval FSP_ERR_INVALID_ARGUMENT    Configuration parameter error.
+ * @retval FSP_ERR_ALREADY_OPEN        R_ETHER_SELECTOR_Open has already been called for this p_ctrl.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHER_SELECTOR_Open (ether_selector_ctrl_t * const p_ctrl, ether_selector_cfg_t const * const p_cfg)
+{
+    ether_selector_instance_ctrl_t * p_instance_ctrl = (ether_selector_instance_ctrl_t *) p_ctrl;
+    R_ETHSS_Type * p_reg_ethss = R_ETHSS;
+
+    volatile uint32_t * p_reg_convctrl;
+    uint32_t            sw_mode;
+    uint32_t            convctrl;
+    uint32_t            phylink;
+    uint32_t            convrst;
+    uint8_t             port;
+
+#if ETHER_SELECTOR_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+#endif
+
+    port = p_cfg->channel;
+
+#if ETHER_SELECTOR_CFG_PARAM_CHECKING_ENABLE
+    FSP_ERROR_RETURN((BSP_FEATURE_ETHSS_MAX_PORTS > port), FSP_ERR_INVALID_CHANNEL);
+    if (ETHER_SELECTOR_SPEED_1000_MBPS == p_instance_ctrl->p_cfg->speed)
+    {
+        FSP_ERROR_RETURN((ETHER_SELECTOR_INTERFACE_RGMII == p_instance_ctrl->p_cfg->interface),
+                         FSP_ERR_INVALID_ARGUMENT);
+    }
+#endif
+
+    FSP_ERROR_RETURN(ETHER_SELECTOR_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
+    p_instance_ctrl->p_reg = p_reg_ethss;
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    /* One time initialization for all ETHER_SELECTOR instances. */
+    r_ether_selector_state_initialize();
+
+    /* Unlock write access protection for Ethernet subsystem registers */
+    r_ether_selector_reg_protection_disable(p_reg_ethss);
+
+    /* Set the function of Ethernet ports. */
+    sw_mode = ETHER_SELECTOR_CFG_MODE;
+    p_reg_ethss->MODCTRL_b.SW_MODE = sw_mode & ETHER_SELECTOR_MODCTRL_BIT_SWMODE_MASK;
+
+    /* Set the MAC of all port for half-duplex.  */
+    p_reg_ethss->SWDUPC_b.PHY_DUPLEX = 0;
+
+    /* Set all Ethernet switch port to select not use 10Mbps.  */
+    p_reg_ethss->SWCTRL_b.SET10 = 0;
+
+    /* Set RGMII/RMII Converter configuration */
+    switch (port)
+    {
+        case 0:
+        {
+            p_reg_convctrl = (uint32_t *) &p_reg_ethss->CONVCTRL[0];
+            break;
+        }
+
+        case 1:
+        {
+            p_reg_convctrl = (uint32_t *) &p_reg_ethss->CONVCTRL[1];
+            break;
+        }
+
+        case 2:
+        default:
+        {
+            p_reg_convctrl = (uint32_t *) &p_reg_ethss->CONVCTRL[2];
+            break;
+        }
+
+#if defined(BSP_MCU_GROUP_RZN2H)
+        case 3:
+        {
+            p_reg_convctrl = (uint32_t *) &p_reg_ethss->CONVCTRL[3];
+            break;
+        }
+#endif
+    }
+
+    convctrl  = *p_reg_convctrl;
+    convctrl &= ~(uint32_t) (ETHER_SELECTOR_FULLD | ETHER_SELECTOR_CONV_MODE_MASK);
+
+    if (ETHER_SELECTOR_INTERFACE_MII == p_instance_ctrl->p_cfg->interface)
+    {
+        convctrl |= ETHER_SELECTOR_CONV_MODE_MII_MODE;
+    }
+    else if (ETHER_SELECTOR_INTERFACE_RMII == p_instance_ctrl->p_cfg->interface)
+    {
+        if (ETHER_SELECTOR_SPEED_10_MBPS == p_instance_ctrl->p_cfg->speed)
+        {
+            convctrl |= ETHER_SELECTOR_CONV_MODE_RMII_10M_IN;
+        }
+        else
+        {
+            convctrl |= ETHER_SELECTOR_CONV_MODE_RMII_100M_IN;
+        }
+
+        if (ETHER_SELECTOR_REF_CLOCK_OUTPUT == p_instance_ctrl->p_cfg->ref_clock)
+        {
+            convctrl |= ETHER_SELECTOR_CONV_BIT_REF_CLK_OUT;
+        }
+    }
+    else if (ETHER_SELECTOR_INTERFACE_RGMII == p_instance_ctrl->p_cfg->interface)
+    {
+        if (ETHER_SELECTOR_SPEED_10_MBPS == p_instance_ctrl->p_cfg->speed)
+        {
+            convctrl |= ETHER_SELECTOR_CONV_MODE_RGMII_10M;
+        }
+        else if (ETHER_SELECTOR_SPEED_100_MBPS == p_instance_ctrl->p_cfg->speed)
+        {
+            convctrl |= ETHER_SELECTOR_CONV_MODE_RGMII_100M;
+        }
+        else
+        {
+            convctrl |= ETHER_SELECTOR_CONV_MODE_RGMII_1000M;
+        }
+    }
+    else
+    {
+        /* Other Interface doesn't change the register value */
+        convctrl = *p_reg_convctrl;
+    }
+
+    if (ETHER_SELECTOR_DUPLEX_FULL == p_instance_ctrl->p_cfg->duplex)
+    {
+        convctrl |= ETHER_SELECTOR_FULLD;
+    }
+    else
+    {
+        convctrl |= ETHER_SELECTOR_HALFD;
+    }
+
+    *p_reg_convctrl = convctrl;
+
+    /* Set active level of PHYLINK signal using the Ethernet switch interface. */
+    /* The SWLINK goes Active-High with a value of 0. */
+    phylink  = p_reg_ethss->PHYLNK_b.SWLINK;
+    phylink &= ~(uint32_t) (1 << port);
+    phylink |= ((uint32_t) (~(p_instance_ctrl->p_cfg->phylink) << port));
+    p_reg_ethss->PHYLNK_b.SWLINK = phylink & ETHER_SELECTOR_PHYLNK_BIT_SWLINK_MASK;
+
+    /* Set active level of PHYLINK signal using the EtherCAT interface. */
+    /* The CATLNK goes Active-High with a value of 1. */
+    phylink  = p_reg_ethss->PHYLNK_b.CATLNK;
+    phylink &= ~(uint32_t) (1 << port);
+    phylink |= ((uint32_t) p_instance_ctrl->p_cfg->phylink << port);
+    p_reg_ethss->PHYLNK_b.CATLNK = phylink & ETHER_SELECTOR_PHYLNK_BIT_CATLNK_MASK;
+
+    /* Release reset of RGMII/RMII converter. */
+    convrst  = p_reg_ethss->CONVRST_b.PHYIR;
+    convrst &= ~(uint32_t) (1 << port);
+    convrst |= (uint32_t) (1 << port);
+    p_reg_ethss->CONVRST_b.PHYIR = convrst & ETHER_SELECTOR_CONVRST_BIT_PHYIR_MASK;
+
+    /* Lock write access protection for Ethernet subsystem registers */
+    r_ether_selector_reg_protection_enable(p_reg_ethss);
+
+    /* Mark instance as opened. */
+    p_instance_ctrl->open = ETHER_SELECTOR_OPEN;
+
+    /* All done.  */
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set the converter speed and duplex after initilaize. Speed 1000Mbps is valid for only RGMII.
+ * Implements @ref ether_selector_api_t::converterSet.
+ *
+ *
+ * @retval FSP_SUCCESS                 Speed adn duplex seetings successfully changed.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ * @retval FSP_ERR_INVALID_ARGUMENT    Invalid parameter in the argument.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHER_SELECTOR_ConverterSet (ether_selector_ctrl_t * const p_ctrl,
+                                         ether_selector_speed_t        speed,
+                                         ether_selector_duplex_t       duplex)
+
+{
+    ether_selector_instance_ctrl_t * p_instance_ctrl = (ether_selector_instance_ctrl_t *) p_ctrl;
+    R_ETHSS_Type      * p_reg_ethss;
+    volatile uint32_t * p_reg_convctrl;
+
+    uint32_t convctrl;
+    uint8_t  port;
+
+#if ETHER_SELECTOR_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(ETHER_SELECTOR_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    if (ETHER_SELECTOR_SPEED_1000_MBPS == speed)
+    {
+        FSP_ERROR_RETURN((ETHER_SELECTOR_INTERFACE_RGMII == p_instance_ctrl->p_cfg->interface),
+                         FSP_ERR_INVALID_ARGUMENT);
+    }
+#endif
+
+    port        = p_instance_ctrl->p_cfg->channel;
+    p_reg_ethss = p_instance_ctrl->p_reg;
+
+    /* Unlock write access protection for Ethernet subsystem registers */
+    r_ether_selector_reg_protection_disable(p_reg_ethss);
+
+    switch (port)
+    {
+        case 0:
+        {
+            p_reg_convctrl = (uint32_t *) &p_reg_ethss->CONVCTRL[0];
+            break;
+        }
+
+        case 1:
+        {
+            p_reg_convctrl = (uint32_t *) &p_reg_ethss->CONVCTRL[1];
+            break;
+        }
+
+        case 2:
+        default:
+        {
+            p_reg_convctrl = (uint32_t *) &p_reg_ethss->CONVCTRL[2];
+            break;
+        }
+
+#if defined(BSP_MCU_GROUP_RZN2H)
+        case 3:
+        {
+            p_reg_convctrl = (uint32_t *) &p_reg_ethss->CONVCTRL[3];
+            break;
+        }
+#endif
+    }
+
+    convctrl  = *p_reg_convctrl;
+    convctrl &= (uint32_t) (~(ETHER_SELECTOR_FULLD | ETHER_SELECTOR_CONV_BIT_SPEED_MASK));
+
+    if (ETHER_SELECTOR_INTERFACE_MII != p_instance_ctrl->p_cfg->interface)
+    {
+        if (ETHER_SELECTOR_SPEED_10_MBPS == speed)
+        {
+            convctrl |= ETHER_SELECTOR_CONV_BIT_SPEED_10M;
+        }
+        else if (ETHER_SELECTOR_SPEED_100_MBPS == speed)
+        {
+            convctrl |= ETHER_SELECTOR_CONV_BIT_SPEED_100M;
+        }
+        else if (ETHER_SELECTOR_SPEED_1000_MBPS == speed)
+        {
+            convctrl |= ETHER_SELECTOR_CONV_BIT_SPEED_1000M;
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+
+    if (ETHER_SELECTOR_DUPLEX_FULL == duplex)
+    {
+        convctrl |= ETHER_SELECTOR_FULLD;
+    }
+    else
+    {
+        convctrl |= ETHER_SELECTOR_HALFD;
+    }
+
+    *p_reg_convctrl = convctrl;
+
+    /* Lock write access protection for Ethernet subsystem registers */
+    r_ether_selector_reg_protection_enable(p_reg_ethss);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Close driver data.  Implements @ref ether_selector_api_t::close.
+ *
+ * @retval FSP_SUCCESS                 Ethernet selector closed.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHER_SELECTOR_Close (ether_selector_ctrl_t * const p_ctrl)
+{
+    ether_selector_instance_ctrl_t * p_instance_ctrl = (ether_selector_instance_ctrl_t *) p_ctrl;
+
+#if ETHER_SELECTOR_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(ETHER_SELECTOR_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Mark instance as closed. */
+    p_instance_ctrl->open = 0U;
+
+    return FSP_SUCCESS;
+}
+
+/** @} (end addtogroup ETHER_SELECTOR) */
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Unlock write access protection for Ethernet subsystem registers
+ *
+ **********************************************************************************************************************/
+static void r_ether_selector_reg_protection_disable (void * const p_reg_base)
+{
+    R_ETHSS_Type * p_reg_ethss = (R_ETHSS_Type *) p_reg_base;
+
+    /* Unlock the protection of ethernet subsystem register */
+    p_reg_ethss->PRCMD = ETHER_SELECTOR_PRCMD_UNLOCK1;
+    p_reg_ethss->PRCMD = ETHER_SELECTOR_PRCMD_UNLOCK2;
+    p_reg_ethss->PRCMD = ETHER_SELECTOR_PRCMD_UNLOCK3;
+    p_reg_ethss->PRCMD = ETHER_SELECTOR_PRCMD_UNLOCK4;
+}
+
+/*******************************************************************************************************************//**
+ * Lock write access protection for Ethernet subsystem registers
+ *
+ **********************************************************************************************************************/
+static void r_ether_selector_reg_protection_enable (void * const p_reg_base)
+{
+    R_ETHSS_Type * p_reg_ethss = (R_ETHSS_Type *) p_reg_base;
+
+    /* Lock the protection of ethernet access register */
+    p_reg_ethss->PRCMD = ETHER_SELECTOR_PRCMD_LOCK;
+}
+
+/*******************************************************************************************************************//**
+ * One time state initialization for all ETHER_SELECTOR instances.
+ **********************************************************************************************************************/
+static void r_ether_selector_state_initialize (void)
+{
+    /* Stores initialization state to skip initialization in ::R_ETHER_SELECTOR_Open after the first call. */
+    static bool g_ether_selector_state_initialized = false;
+
+    /* ETHER_SELECTOR requires a one time initialization.
+     *  This will be handled only the first time this function is called.
+     *  This initialization:
+     *  -# Powers on the ETHSS block.
+     *  -# Release reset control of the ETHSS and the MII Converter  */
+    if (!g_ether_selector_state_initialized)
+    {
+        g_ether_selector_state_initialized = true;
+
+        /* Power on ETHSS*/
+        R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+        R_BSP_MODULE_START(FSP_IP_ETHSS, 0);
+
+        /* Release modules */
+        R_BSP_ModuleResetDisable(BSP_MODULE_RESET_ESC_ETH_SUBSYSTEM);
+        R_BSP_ModuleResetDisable(BSP_MODULE_RESET_MII);
+        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+    }
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ethsw/r_ethsw.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ethsw/r_ethsw.c
new file mode 100644
index 00000000..bb4d5e29
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ethsw/r_ethsw.c
@@ -0,0 +1,6491 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+#include <string.h>
+
+#include "bsp_api.h"
+#include "r_ethsw.h"
+#include <math.h>
+
+/***********************************************************************************************************************
+ * Macro definitions
+ ***********************************************************************************************************************/
+
+#ifndef ETHSW_ERROR_RETURN
+
+/*LDRA_INSPECTED 77 S This macro does not work when surrounded by parentheses. */
+ #define ETHSW_ERROR_RETURN(a, err)    FSP_ERROR_RETURN((a), (err))
+#endif                                 /* !ETHSW_ERROR_RETURN */
+
+/** "SWIT" in ASCII.  Used to determine if the control block is open. */
+#define ETHSW_OPEN                            (0x53574954U)
+
+/* Initial value of down counter for timeout detection */
+#define ETHSW_TIMEOUT_COUNT                   (1000000000U)
+
+/* Maximum Frame Length */
+#define ETHSW_FRAME_SIZE                      (0x2408U)
+
+/* ENABLE PORT Bit Definitions(PORT_ENA,UCAST_DEFAULT_MASK,BCAST_DEFAULT_MASK,MCAST_DEFAULT_MASK Register) */
+#define ETHSW_ENABLE_PORT0                    (1UL << 0)
+#define ETHSW_ENABLE_PORT1                    (1UL << 1)
+#define ETHSW_ENABLE_PORT2                    (1UL << 2)
+#define ETHSW_ENABLE_PORT3                    (1UL << 3)
+
+/* COMMAND_CONFIG Register Bit Definitions */
+#define ETHSW_COMMAND_CONFIG_ENA_10           (1UL << 25)
+#define ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK    (1UL << 24)
+#define ETHSW_COMMAND_CONFIG_CNTL_FRM_ENA     (1UL << 23)
+#define ETHSW_COMMAND_CONFIG_LOOP_ENA         (1UL << 15)
+#define ETHSW_COMMAND_CONFIG_SW_RESET         (1UL << 13)
+#define ETHSW_COMMAND_CONFIG_TX_CRC_APPEND    (1UL << 11)
+#define ETHSW_COMMAND_CONFIG_HD_ENA           (1UL << 10)
+#define ETHSW_COMMAND_CONFIG_TX_ADDR_INS      (1UL << 9)
+#define ETHSW_COMMAND_CONFIG_PAUSE_IGNORE     (1UL << 8)
+#define ETHSW_COMMAND_CONFIG_PAUSE_FWD        (1UL << 7)
+#define ETHSW_COMMAND_CONFIG_CRC_FWD          (1UL << 6)
+#define ETHSW_COMMAND_CONFIG_PAD_EN           (1UL << 5)
+#define ETHSW_COMMAND_CONFIG_PROMIS_EN        (1UL << 4)
+#define ETHSW_COMMAND_CONFIG_ETH_SPEED        (1UL << 3)
+#define ETHSW_COMMAND_CONFIG_RX_ENA           (1UL << 1)
+#define ETHSW_COMMAND_CONFIG_TX_ENA           (1UL << 0)
+
+/* INT_CONFIG Register Bit Number Definitions */
+#define ETHSW_INT_CONFIG_PATTERN_INT          (1UL << 31)
+#define ETHSW_INT_CONFIG_TDMA_INT             (1UL << 30)
+#define ETHSW_INT_CONFIG_TSM_INT              (1UL << 29)
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+ #define ETHSW_INT_CONFIG_EFP_INT             (1UL << 27)
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+#define ETHSW_INT_CONFIG_IRQ_LNK_SHIFT        (8U)
+#define ETHSW_INT_CONFIG_IRQ_LNK_MASK         (0x7 << ETHSW_INT_CONFIG_IRQ_LNK_SHIFT)
+#define ETHSW_INT_CONFIG_DLR_INT              (1UL << 5)
+#define ETHSW_INT_CONFIG_IRQ_EN               (1UL << 0)
+
+#define ETHSW_HEX_000000FF                    (0x000000ffU)
+#define ETHSW_HEX_0000FF00                    (0x0000ff00U)
+#define ETHSW_HEX_00FF0000                    (0x00ff0000U)
+#define ETHSW_HEX_FF000000                    (0xff000000U)
+#define ETHSW_HEX_0000FFFF                    (0x0000ffffU)
+#define ETHSW_DEC_100                         (100U)
+#define ETHSW_DEC_512                         (512U)
+#define ETHSW_DEC_1000                        (1000U)
+
+#define ETHSW_HOST_PORT_NUMBER                (3U)
+#define ETHSW_PORT_COUNT                      (3U) ///< Number of External port
+#define ETHSW_PORT_COUNT_ALL                  (4U) ///< Number of All port (include managemant port)
+
+/* Bit Mask for register access */
+#define ETHSW_1BIT_MASK                       (0x1U)
+#define ETHSW_2BITS_MASK                      (0x3U)
+#define ETHSW_3BITS_MASK                      (0x7U)
+#define ETHSW_4BITS_MASK                      (0xfU)
+#define ETHSW_9BITS_MASK                      (0x1ffU)
+#define ETHSW_12BITS_MASK                     (0xfffU)
+
+/* LK_CTRL Register Bit Definitions */
+#define ETHSW_LK_MASK                         (0x9E)
+#define ETHSW_LK_PERVLAN                      (7)
+#define ETHSW_LK_DISCUNKN                     (4)
+#define ETHSW_LK_MIGRAT                       (3)
+#define ETHSW_LK_AGING                        (2)
+#define ETHSW_LK_LEARN                        (1)
+#define ETHSW_LK_ADDR_CLEAR                   (1 << 29)
+#define ETHSW_LK_ADDR_LOOKUP                  (1 << 28)
+#define ETHSW_LK_ADDR_VALID                   (1)
+#define ETHSW_LK_ADDR_WRITE                   (1 << 25)
+#define ETHSW_LK_ADDR_REG_VALID               (1 << 16)
+#define ETHSW_LK_ADDR_REG_TYPE                (1 << 17)
+#define ETHSW_LK_ADDR_PORTMASK                (0xF << 21)
+#define ETHSW_LK_ADDR_PRIOMASK                (0x7 << 18)
+#define ETHSW_LK_ADDR_PORT_OFFSET             (5)
+#define ETHSW_LK_ADDR_PORT_REG_OFFSET         (21)
+#define ETHSW_LK_ADDR_PRIO_REG_OFFSET         (18)
+#define ETHSW_LK_ADDR_MASKANDFLAGS_MASK       (0xFFFFU << 16)
+
+/* FRM_LENGTH_P[n] Register Bit Definitions */
+#define ETHSW_FRAMESIZE_MASK                  0x3FFF ///< maximum frame size mask
+
+#define ETHSW_PORT_TX_MSK                     (1)    ///< COMMAND_CONFIG_P[n] - mask for tx_ena
+#define ETHSW_PORT_RX_MSK                     (2)    ///< COMMAND_CONFIG_P[n] - mask for rx_ena
+#define ETHSW_PORT_RXTX                       (ETHSW_PORT_TX_MSK | ETHSW_PORT_RX_MSK)
+
+#define ETHSW_PHY_LINK                        (4)
+
+/* Register offset for Port-n */
+#define ETHSW_PORT_OFFSET                     (0x400)
+#define ETHSW_PORT_OFFSET_4BYTES              (0x04)
+#define ETHSW_PORT_OFFSET_8BYTES              (0x08)
+#define ETHSW_PORT_OFFSET_16BYTES             (0x10)
+#define ETHSW_PORT_OFFSET_32BYTES             (0x20)
+
+/* DLR_IRQ_CONTROL Register Bit Definitions */
+#define ETHSW_TGT_DLR_INT_NEWSTATUS           (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Pos)   ///< new ring status
+#define ETHSW_TGT_DLR_INT_BEACONTMO_0         (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Pos) ///< beacon timeout port 0
+#define ETHSW_TGT_DLR_INT_BEACONTMO_1         (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Pos) ///< beacon timeout port 1
+#define ETHSW_TGT_DLR_INT_SUVICHNG            (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Pos)    ///< Supervisor changed
+#define ETHSW_TGT_DLR_INT_LNKCHNG_0           (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Pos)   ///< link status changed port 0
+#define ETHSW_TGT_DLR_INT_LNKCHNG_1           (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Pos)   ///< link status changed port 1
+#define ETHSW_TGT_DLR_INT_BECONRCV_0          (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Pos)     ///< beacon frame received port 0
+#define ETHSW_TGT_DLR_INT_BECONRCV_1          (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Pos)     ///< beacon frame received port 1
+#define ETHSW_TGT_DLR_INT_LOCALLOOP_0         (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Pos)       ///< loop detected port 0
+#define ETHSW_TGT_DLR_INT_LOCALLOOP_1         (1 << R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Pos)       ///< loop detected port 1
+
+#define ETHSW_RN_ADVSW_DLR_ETHTYPE            (0x80E1U)                                               ///< DLR EtherType for DLR module
+#define ETHSW_RN_ADVSW_DLR_TICKS              (200U)                                                  ///< ticks for 1 us
+
+/* Multicast MAC Address used by DLR */
+#define ETHSW_MULTICAST_BEACON                {0x01, 0x21, 0x6c, 0x00, 0x00, 0x01}
+#define ETHSW_MULTICAST_DLR                   {0x01, 0x21, 0x6c, 0x00, 0x00, 0x00}
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+
+/* extended frame parser related definitions */
+ #define ETHSW_EFP_DMACI_SZ                   (6U)
+ #define ETHSW_EFP_DVIDI_SZ                   (2U)
+ #define ETHSW_EFP_VICM_NUM_MAX               (4U)
+ #define ETHSW_EFP_SID_NUM_MAX                (8U)
+ #define ETHSW_EFP_GAID_NUM_MAX               (8U)
+ #define ETHSW_EFP_MEID_NUM_MAX               (8U)
+ #define ETHSW_EFP_ASI_ADDR_NUM               (128U)
+ #define ETHSW_EFP_ASI_ADDR_SZ                (7U)
+ #define ETHSW_EFP_ASI_HASH_DA_SZ             (48U)
+ #define ETHSW_EFP_ASI_HASH_VID_SZ            (12U)
+ #define ETHSW_EFP_ASI_HASH_VID_MASK          (0x0FFFU)
+ #define ETHSW_EFP_ASI_HASH_SZ                (64U)
+
+ #define ETHSW_COMMAND_CONFIG_OFFSET          (0x100U)
+ #define ETHSW_VLAN_MODE_OFFSET               (0x100U)
+ #define ETHSW_VLAN_TAG_OFFSET                (0x100U)
+ #define ETHSW_PCP_REMAP_OFFSET               (0x100U)
+ #define ETHSW_QSFTBL_OFFSET_PORT             (0x100U)
+ #define ETHSW_QSFTBL_OFFSET_SID              (0x0AU)
+ #define ETHSW_QSTMACU_OFFSET_PORT            (0x100U)
+ #define ETHSW_QSTMACU_OFFSET_SID             (0x0AU)
+ #define ETHSW_QSTMACD_OFFSET_PORT            (0x100U)
+ #define ETHSW_QSTMACD_OFFSET_SID             (0x0AU)
+ #define ETHSW_QSTMAMU_OFFSET_PORT            (0x100U)
+ #define ETHSW_QSTMAMU_OFFSET_SID             (0x0AU)
+ #define ETHSW_QSTMAMD_OFFSET_PORT            (0x100U)
+ #define ETHSW_QSTMAMD_OFFSET_SID             (0x0AU)
+ #define ETHSW_QSFTVL_OFFSET_PORT             (0x100U)
+ #define ETHSW_QSFTVL_OFFSET_SID              (0x0AU)
+ #define ETHSW_QSFTVLM_OFFSET_PORT            (0x100U)
+ #define ETHSW_QSFTVLM_OFFSET_SID             (0x0AU)
+ #define ETHSW_QSFTBL_OFFSET_PORT             (0x100U)
+ #define ETHSW_QSFTBL_OFFSET_SID              (0x0AU)
+ #define ETHSW_QGMOD_OFFSET                   (0x100U)
+ #define ETHSW_QMDESC_OFFSET_PORT             (0x100U)
+ #define ETHSW_QMDESC_OFFSET_METER            (0x05U)
+ #define ETHSW_QMCBSC_OFFSET_PORT             (0x100U)
+ #define ETHSW_QMCBSC_OFFSET_METER            (0x05U)
+ #define ETHSW_QMCIRC_OFFSET_PORT             (0x100U)
+ #define ETHSW_QMCIRC_OFFSET_METER            (0x05U)
+ #define ETHSW_QMEC_OFFSET                    (0x100U)
+ #define ETHSW_QSEIE_OFFSET                   (0x100U)
+ #define ETHSW_QSEID_OFFSET                   (0x100U)
+ #define ETHSW_QGEIE_OFFSET                   (0x100U)
+ #define ETHSW_QGEID_OFFSET                   (0x100U)
+ #define ETHSW_QMEIE_OFFSET                   (0x100U)
+ #define ETHSW_QMEID_OFFSET                   (0x100U)
+ #define ETHSW_ERROR_MASK_OFFSET              (0x100U)
+ #define ETHSW_QSEIS_OFFSET                   (0x100U)
+ #define ETHSW_QGEIS_OFFSET                   (0x100U)
+ #define ETHSW_QMEIS_OFFSET                   (0x100U)
+ #define ETHSW_ERROR_STATUS_OFFSET            (0x100U)
+ #define ETHSW_QSMOI_MASK                     (0xFFU)
+ #define ETHSW_QGMOI_MASK                     (0xFFU)
+ #define ETHSW_QRFI_MASK                      (0xFFU)
+ #define ETHSW_ERROR_STATUS_MASK              (R_ETHSW_P0_ERROR_STATUS_SOPERR_Msk | R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Msk | \
+                                               R_ETHSW_P0_ERROR_STATUS_POVRSZ_Msk | R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Msk | \
+                                               R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Msk)
+ #define ETHSW_CHANNEL_ENABLE_MASK            (R_ETHSW_CHANNEL_ENABLE_CH0ENA_Msk | R_ETHSW_CHANNEL_ENABLE_CH1ENA_Msk | \
+                                               R_ETHSW_CHANNEL_ENABLE_CH2ENA_Msk)
+ #define ETHSW_CHANNEL_DISABLE_MASK           (R_ETHSW_CHANNEL_DISABLE_CH0DIS_Msk | R_ETHSW_CHANNEL_DISABLE_CH1DIS_Msk | \
+                                               R_ETHSW_CHANNEL_DISABLE_CH2DIS_Msk)
+#endif                                              /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+/* driver local define */
+#define ETHSW_RX_PATTERN_MATCHER_COUNT        (12U) ///< Number of RX Pattern Matcher
+#define ETHSW_TIME_COUNT                      (2U)  ///< Number of timer
+#define ETHSW_GPIO_COUNT                      (8U)  ///< Number of timer
+#define ETHSW_PULSE_GENERATOR_COUNT           (4U)  ///< Number of Pulse Gennrator
+
+/* FramePreemption register access offset Definitions */
+#define ETHSW_BR_CONTROL_OFFSET               (0x100)
+#define ETHSW_STATUS_OFFSET                   (0x100)
+
+/* MMCTL_QTRIG Register Bit Definitions */
+#define ETHSW_MMCTL_QTRIG_QUEUE_TRIG_SHIFT    (16U)
+#define ETHSW_MMCTL_QTRIG_QUEUE_TRIG_MASK     (0xffffU << ETHSW_MMCTL_QTRIG_QUEUE_TRIG_SHIFT)
+#define ETHSW_MMCTL_QTRIG_PORT_MASK_SHIFT     (0U)
+#define ETHSW_MMCTL_QTRIG_PORT_MASK_MASK      (0xfU << ETHSW_MMCTL_QTRIG_PORT_MASK_SHIFT)
+
+/* Define for BCAST_STORM_LIMIT register */
+#define ETHSW_OPERATING_CLOCK_CYCLES          (200U * 1000 * 1000)
+#define ETHSW_DOS_TIMEFACTOR                  (65536U)
+
+/* Define for constant value */
+#define ETHSW_DEC_100                         (100U)
+#define ETHSW_DEC_512                         (512U)
+
+/* ASI_MEM_ADDR Register Bit Definitions */
+#define ETHSW_MEM_WEN_ENABLE                  (0x80U)
+#define ETHSW_MEM_REQ_ALL_ACCESS              (0x700U)
+
+/* Nanosecond count value for 1 second */
+#define NANO_COUNT_FOR_1SEC                   (1000000000)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ ***********************************************************************************************************************/
+
+typedef union
+{
+    ethsw_mac_addr_t mac_addr;         /* MAC address                                  */
+    uint32_t         reg_data[2];      /* datas for LK_DATA_LO and LK_DATA_HI register */
+} ethsw_mac_addr_reg_t;
+
+/** MAC table entry(for register access) */
+typedef struct st_ethsw_mactab_entry_reg
+{
+    ethsw_mac_addr_t mac;              ///< MAC address
+    uint16_t         mask_and_flags;   ///< Port bit mask and flags
+} ethsw_mactab_entry_reg_t;
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+
+static void ethsw_enable_icu(ethsw_instance_ctrl_t * const p_instance_ctrl);
+
+static void ethsw_disable_icu(ethsw_instance_ctrl_t * const p_instance_ctrl);
+
+void ethsw_isr_intr(void);
+
+static void ethsw_isr_dlr(ethsw_instance_ctrl_t * p_instance_ctrl);
+static void ethsw_isr_tdma(ethsw_instance_ctrl_t * p_instance_ctrl);
+static void ethsw_isr_tsm(ethsw_instance_ctrl_t * p_instance_ctrl);
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+static void    ethsw_isr_efp(ethsw_instance_ctrl_t * p_instance_ctrl);
+static void    r_ethsw_make_crc(char * bit_str, uint32_t len, char * crc_buf);
+static uint8_t r_ethsw_calc_hash(ethsw_mac_addr_t * dmaci, ethsw_vlan_vid_t * vidi);
+
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+static void ethsw_isr_rx_pattern_matcher(ethsw_instance_ctrl_t * p_instance_ctrl);
+
+static void r_ethsw_reg_protection_disable(void * const p_reg_base);
+static void r_ethsw_reg_protection_enable(void * const p_reg_base);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+#if defined(__GNUC__)
+
+/* This structure is affected by warnings from a GCC compiler bug. This pragma suppresses the warnings in this
+ * structure only.*/
+
+/*LDRA_INSPECTED 69 S */
+ #pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+#endif
+
+/** ETHER SWITCH HAL API mapping for Ethernet Controller interface */
+/*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */
+const ether_switch_api_t g_ether_switch_on_ethsw =
+{
+    .open  = R_ETHSW_Open,
+    .close = R_ETHSW_Close,
+};
+
+void (* gp_ethsw_dlr_callback)(        ///< pointer of callback function called when an DLR Interupt occurs
+    ethsw_dlr_event_t event,
+    uint32_t          port);
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+void (* gp_ethsw_efp_callback)(        ///< pointer of callback function called when an EFP Interupt occurs
+    uint32_t          port,
+    ethsw_efp_event_t id);
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+void (* gp_ethsw_rx_pattern_callback)( ///< pointer of callback function called when an Rx pattern matcher interupt occurs
+    ethsw_rx_pattern_event_t        event,
+    ethsw_rx_pattern_event_data_t * p_data);
+
+void (* gp_ethsw_tdma_callback)(       ///< pointer of callback function called when an TDMA Interupt occurs
+    ethsw_tdma_event_t           event,
+    ethsw_tdma_callback_data_t * p_tdma_data);
+
+void (* gp_ethsw_time_callback)(       ///< pointer of callback function called when an PTP Interupt occurs
+    ethsw_time_event_t  event,
+    uint32_t            port,
+    ethsw_timestamp_t * p_timestamp);
+
+/*******************************************************************************************************************//**
+ * @addtogroup ETHER_SWITCH
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/********************************************************************************************************************//**
+ * Open the switch ports and gets it ready to pass through the frames.
+ *
+ * @retval  FSP_SUCCESS                 Channel opened successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER SWITCH control block or configuration structure is NULL.
+ * @retval  FSP_ERR_ALREADY_OPEN        Control block has already been opened or channel is being used by another
+ *                                      instance. Call close() then open() to reconfigure.
+ * @retval  FSP_ERR_INVALID_CHANNEL     Invalid channel number is given.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Interrupt is not enabled.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_Open (ether_switch_ctrl_t * const p_ctrl, ether_switch_cfg_t const * const p_cfg)
+{
+    fsp_err_t               err             = FSP_SUCCESS;
+    ethsw_instance_ctrl_t * p_instance_ctrl =
+        (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN((NULL != p_cfg), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((BSP_FEATURE_ETHSW_MAX_CHANNELS > p_cfg->channel), FSP_ERR_INVALID_CHANNEL);
+    ETHSW_ERROR_RETURN((0 <= p_cfg->irq), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((ETHSW_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN);
+
+    if (ETHSW_PHYLINK_ENABLE == ((ethsw_extend_cfg_t *) p_cfg->p_extend)->phylink)
+    {
+        ETHSW_ERROR_RETURN((NULL != p_cfg->p_callback), FSP_ERR_INVALID_POINTER);
+        ETHSW_ERROR_RETURN((NULL != p_cfg->p_context), FSP_ERR_INVALID_POINTER);
+    }
+#endif
+
+    p_instance_ctrl->p_reg_switch    = (void *) R_ETHSW;
+    p_instance_ctrl->p_reg_ethsw_ptp = (void *) R_ETHSW_PTP;
+    p_instance_ctrl->p_reg_ethss     = (void *) R_ETHSS;
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /* Initialize configuration of Ethernet switch module. */
+    p_instance_ctrl->p_switch_cfg = p_cfg;
+
+    /* Module start */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+    R_BSP_MODULE_START(FSP_IP_ETHSW, p_cfg->channel);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_ETHSW);
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+    /* set Maximum Frame Length size */
+    p_reg_switch->FRM_LENGTH_P0_b.FRM_LENGTH = ETHSW_FRAME_SIZE;
+    p_reg_switch->FRM_LENGTH_P1_b.FRM_LENGTH = ETHSW_FRAME_SIZE;
+    p_reg_switch->FRM_LENGTH_P2_b.FRM_LENGTH = ETHSW_FRAME_SIZE;
+    p_reg_switch->FRM_LENGTH_P3_b.FRM_LENGTH = ETHSW_FRAME_SIZE;
+
+    /* Initialize COMMAND_CONFIG_p[0] Reg */
+    p_reg_switch->COMMAND_CONFIG_P0 = (ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK | ETHSW_COMMAND_CONFIG_TX_CRC_APPEND |
+                                       ETHSW_COMMAND_CONFIG_ETH_SPEED | ETHSW_COMMAND_CONFIG_RX_ENA |
+                                       ETHSW_COMMAND_CONFIG_TX_ENA);
+
+    /* Initialize COMMAND_CONFIG_p[1] Reg */
+    p_reg_switch->COMMAND_CONFIG_P1 = (ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK | ETHSW_COMMAND_CONFIG_TX_CRC_APPEND |
+                                       ETHSW_COMMAND_CONFIG_ETH_SPEED | ETHSW_COMMAND_CONFIG_RX_ENA |
+                                       ETHSW_COMMAND_CONFIG_TX_ENA);
+
+    /* Initialize COMMAND_CONFIG_p[2] Reg */
+    p_reg_switch->COMMAND_CONFIG_P2 = (ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK | ETHSW_COMMAND_CONFIG_TX_CRC_APPEND |
+                                       ETHSW_COMMAND_CONFIG_ETH_SPEED | ETHSW_COMMAND_CONFIG_RX_ENA |
+                                       ETHSW_COMMAND_CONFIG_TX_ENA);
+
+    /* Initialize COMMAND_CONFIG_p[3] Reg */
+    p_reg_switch->COMMAND_CONFIG_P3 = (ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK | ETHSW_COMMAND_CONFIG_TX_CRC_APPEND |
+                                       ETHSW_COMMAND_CONFIG_ETH_SPEED | ETHSW_COMMAND_CONFIG_RX_ENA |
+                                       ETHSW_COMMAND_CONFIG_TX_ENA);
+
+    /* Initialize PORT ENABLE Reg */
+    p_reg_switch->PORT_ENA_b.RXENA =
+        (ETHSW_ENABLE_PORT0 | ETHSW_ENABLE_PORT1 | ETHSW_ENABLE_PORT2 | ETHSW_ENABLE_PORT3);
+    p_reg_switch->PORT_ENA_b.TXENA =
+        (ETHSW_ENABLE_PORT0 | ETHSW_ENABLE_PORT1 | ETHSW_ENABLE_PORT2 | ETHSW_ENABLE_PORT3);
+
+    /* Initialize Learning/Lookup function global configuration Reg */
+    p_reg_switch->LK_CTRL            = 0;
+    p_reg_switch->LK_CTRL_b.ALW_MGRT = 1;
+    p_reg_switch->LK_CTRL_b.AGING_EN = 1;
+    p_reg_switch->LK_CTRL_b.LEARN_EN = 1;
+    p_reg_switch->LK_CTRL_b.LKUP_EN  = 1;
+
+    /* enable Default unicast resolution */
+    p_reg_switch->UCAST_DEFAULT_MASK0_b.UCASTDM =
+        (ETHSW_ENABLE_PORT0 | ETHSW_ENABLE_PORT1 | ETHSW_ENABLE_PORT2 | ETHSW_ENABLE_PORT3);
+
+    /* enable Default broadcast resolution */
+    p_reg_switch->BCAST_DEFAULT_MASK0_b.BCASTDM =
+        (ETHSW_ENABLE_PORT0 | ETHSW_ENABLE_PORT1 | ETHSW_ENABLE_PORT2 | ETHSW_ENABLE_PORT3);
+
+    /* enable Default multicast resolution */
+    p_reg_switch->MCAST_DEFAULT_MASK0_b.MCASTDM =
+        (ETHSW_ENABLE_PORT0 | ETHSW_ENABLE_PORT1 | ETHSW_ENABLE_PORT2 | ETHSW_ENABLE_PORT3);
+
+    /* set port in authorized state(Port 0 authentication control and configuration Reg) */
+    p_reg_switch->AUTH_PORT_b[0].AUTH = 1;
+
+    /* set port in authorized state(Port 1 authentication control and configuration Reg) */
+    p_reg_switch->AUTH_PORT_b[1].AUTH = 1;
+
+    /* set port in authorized state(Port 2 authentication control and configuration Reg) */
+    p_reg_switch->AUTH_PORT_b[2].AUTH = 1;
+
+    /* set port in authorized state(Port 3 authentication control and configuration Reg) */
+    p_reg_switch->AUTH_PORT_b[3].AUTH = 1;
+
+    /* Initialize MGMT_TAG_CONFIG Reg */
+    if (ETHSW_SPECIFIC_TAG_ENABLE == ((ethsw_extend_cfg_t *) p_cfg->p_extend)->specific_tag)
+    {
+        p_reg_switch->MGMT_TAG_CONFIG_b.TAGFIELD  = ((ethsw_extend_cfg_t *) p_cfg->p_extend)->specific_tag_id;
+        p_reg_switch->MGMT_TAG_CONFIG_b.TYPE2_EN  = 0;
+        p_reg_switch->MGMT_TAG_CONFIG_b.TYPE1_EN  = 0;
+        p_reg_switch->MGMT_TAG_CONFIG_b.AL_FRAMES = 1;
+        p_reg_switch->MGMT_TAG_CONFIG_b.ENABLE    = 1;
+    }
+    else
+    {
+        p_reg_switch->MGMT_TAG_CONFIG_b.ENABLE = 0;
+    }
+
+    /* Set Ethernet Switch interrupt level and enable */
+    ethsw_enable_icu(p_instance_ctrl);
+
+    if (ETHSW_PHYLINK_ENABLE == ((ethsw_extend_cfg_t *) p_cfg->p_extend)->phylink)
+    {
+        /* Set line port phy link change interrupt enable Bit (PORT0 - 2) */
+        p_reg_switch->INT_CONFIG_b.IRQ_LINK = (ETHSW_ENABLE_PORT0 | ETHSW_ENABLE_PORT1 | ETHSW_ENABLE_PORT2);
+
+        /* Set Interrupt global enable */
+        p_reg_switch->INT_CONFIG_b.IRQ_EN = 1;
+    }
+
+    p_instance_ctrl->open = ETHSW_OPEN;
+
+    return err;
+}                                      /* End of function R_ETHSW_Open() */
+
+/********************************************************************************************************************//**
+ * Close the switch ports
+ *
+ * @retval  FSP_SUCCESS                                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened
+ *
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_Close (ether_switch_ctrl_t * const p_ctrl)
+{
+    fsp_err_t               err             = FSP_SUCCESS;
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+
+    R_ETHSW_Type * p_reg_switch;
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Set line port phy link change interrupt disable Bit (PORT0 - 2) */
+    p_reg_switch->INT_CONFIG_b.IRQ_LINK = 0;
+
+    /* Set Interrupt global disable */
+    p_reg_switch->INT_CONFIG_b.IRQ_EN = 0;
+
+    /* set port in unauthorized state(Port 0 authentication control and configuration Reg) */
+    p_reg_switch->AUTH_PORT_b[0].AUTH = 0;
+
+    /* set port in unauthorized state(Port 1 authentication control and configuration Reg) */
+    p_reg_switch->AUTH_PORT_b[1].AUTH = 0;
+
+    /* set port in unauthorized state(Port 2 authentication control and configuration Reg) */
+    p_reg_switch->AUTH_PORT_b[2].AUTH = 0;
+
+    /* set port in unauthorized state(Port 3 authentication control and configuration Reg) */
+    p_reg_switch->AUTH_PORT_b[3].AUTH = 0;
+
+    /* clear Maximum Frame Length Value */
+    p_reg_switch->FRM_LENGTH_P0_b.FRM_LENGTH = ETHSW_FRAME_SIZE;
+    p_reg_switch->FRM_LENGTH_P1_b.FRM_LENGTH = ETHSW_FRAME_SIZE;
+    p_reg_switch->FRM_LENGTH_P2_b.FRM_LENGTH = ETHSW_FRAME_SIZE;
+    p_reg_switch->FRM_LENGTH_P3_b.FRM_LENGTH = ETHSW_FRAME_SIZE;
+
+    /* Disable PORT Rx Tx */
+    p_reg_switch->PORT_ENA_b.RXENA = 0U;
+    p_reg_switch->PORT_ENA_b.TXENA = 0U;
+
+    /* Disable the MAC reception function(COMMAND_CONFIG_p[1] Reg) */
+    p_reg_switch->COMMAND_CONFIG_P0 = (ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK | ETHSW_COMMAND_CONFIG_TX_CRC_APPEND);
+
+    /* Disable the MAC reception function(COMMAND_CONFIG_p[2] Reg) */
+    p_reg_switch->COMMAND_CONFIG_P1 = (ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK | ETHSW_COMMAND_CONFIG_TX_CRC_APPEND);
+
+    /* Disable the MAC reception function(COMMAND_CONFIG_p[2] Reg) */
+    p_reg_switch->COMMAND_CONFIG_P2 = (ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK | ETHSW_COMMAND_CONFIG_TX_CRC_APPEND);
+
+    /* Disable the MAC reception function(COMMAND_CONFIG_p[3] Reg) */
+    p_reg_switch->COMMAND_CONFIG_P3 = (ETHSW_COMMAND_CONFIG_NO_LGTH_CHECK | ETHSW_COMMAND_CONFIG_TX_CRC_APPEND);
+
+    /* Disable Ethernet interrupt. */
+    ethsw_disable_icu(p_instance_ctrl);
+
+    /** Clear configure block parameters. */
+    p_instance_ctrl->p_switch_cfg = NULL;
+
+    /** Mark the channel not open so other APIs cannot use it. */
+    p_instance_ctrl->open = 0U;
+
+    return err;
+}                                      /* End of function R_ETHER_Close() */
+
+/********************************************************************************************************************//**
+ * Configs speed and duplex of the port
+ *
+ * @retval  FSP_SUCCESS                                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    Invalid input parameter.
+ *
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_SpeedCfg (ether_switch_ctrl_t * const p_ctrl, uint32_t const port, ethsw_link_speed_t const speed)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+    uint32_t volatile     * p_reg_command_config;
+    uint32_t                command_config;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    switch (port)
+    {
+        case 0:
+        {
+            p_reg_command_config = &p_reg_switch->COMMAND_CONFIG_P0;
+            break;
+        }
+
+        case 1:
+        {
+            p_reg_command_config = &p_reg_switch->COMMAND_CONFIG_P1;
+            break;
+        }
+
+        case 2:
+        {
+            p_reg_command_config = &p_reg_switch->COMMAND_CONFIG_P2;
+            break;
+        }
+
+        default:
+        {
+            err = FSP_ERR_INVALID_ARGUMENT;
+            break;
+        }
+    }
+
+    if (err == FSP_SUCCESS)
+    {
+        command_config = *p_reg_command_config;
+
+        command_config &= (uint32_t) ~(ETHSW_COMMAND_CONFIG_ENA_10 |
+                                       ETHSW_COMMAND_CONFIG_HD_ENA |
+                                       ETHSW_COMMAND_CONFIG_ETH_SPEED);
+        switch (speed)
+        {
+            case ETHSW_LINK_SPEED_10H:
+            {
+                command_config |= (ETHSW_COMMAND_CONFIG_ENA_10 |
+                                   ETHSW_COMMAND_CONFIG_HD_ENA);
+                break;
+            }
+
+            case ETHSW_LINK_SPEED_10F:
+            {
+                command_config |= (ETHSW_COMMAND_CONFIG_ENA_10);
+                break;
+            }
+
+            case ETHSW_LINK_SPEED_100H:
+            {
+                command_config |= (ETHSW_COMMAND_CONFIG_HD_ENA);
+                break;
+            }
+
+            case ETHSW_LINK_SPEED_100F:
+            {
+                break;
+            }
+
+            case ETHSW_LINK_SPEED_1000H:
+            {
+                command_config |= (ETHSW_COMMAND_CONFIG_HD_ENA |
+                                   ETHSW_COMMAND_CONFIG_ETH_SPEED);
+                break;
+            }
+
+            case ETHSW_LINK_SPEED_1000F:
+            {
+                command_config |= (ETHSW_COMMAND_CONFIG_ETH_SPEED);
+                break;
+            }
+
+            default:
+            {
+                err = FSP_ERR_INVALID_ARGUMENT;
+                break;
+            }
+        }
+
+        *p_reg_command_config = command_config;
+    }
+
+    return err;
+}                                      /* End of function R_ETHSW_ConfSpeed() */
+
+/*******************************************************************************************************************//**
+ * Sets the static MAC address entry for the given MAC address.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_TIMEOUT             Timeout error
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_MacTableSet (ether_switch_ctrl_t * const    p_ctrl,
+                               ethsw_mac_table_entry_addr_t * p_mac_entry_addr,
+                               ethsw_mac_table_entry_info_t * p_mac_entry_info)
+{
+    ethsw_mac_addr_reg_t entry = {0};
+    uint64_t             timeout;      /* timeout */
+    uint32_t             port_mask;    /* converted portmask */
+    volatile uint32_t    dammy_read;
+
+    R_ETHSW_Type volatile * p_switch_reg;
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_mac_entry_addr), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != p_mac_entry_addr->mac_addr), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != *p_mac_entry_addr->mac_addr), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != p_mac_entry_info), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    port_mask = p_mac_entry_info->port_mask.mask;
+
+    /* copy mac address to get valid alignment */
+    memcpy(entry.mac_addr, *p_mac_entry_addr->mac_addr, ETHSW_MAC_ADDR_LENGTH);
+
+    p_switch_reg->LK_DATA_LO = entry.reg_data[0];
+    p_switch_reg->LK_DATA_HI = entry.reg_data[1];
+
+    p_switch_reg->LK_DATA_HI2_b.MEMDATA = p_mac_entry_addr->vlan_id &
+                                          (R_ETHSW_LK_DATA_HI2_MEMDATA_Msk >> R_ETHSW_LK_DATA_HI2_MEMDATA_Pos);
+
+    /* damy read */
+    dammy_read = p_switch_reg->LK_DATA_LO;
+    dammy_read = p_switch_reg->LK_DATA_HI;
+    dammy_read = dammy_read;
+
+    /* Delete entry? */
+    if (0 == port_mask)
+    {
+        p_switch_reg->LK_ADDR_CTRL |= (ETHSW_LK_ADDR_CLEAR | ETHSW_LK_ADDR_LOOKUP);
+    }
+    else
+    {
+        timeout = ETHSW_TIMEOUT_COUNT;
+
+        /* Perform lookup to get address entry */
+        p_switch_reg->LK_ADDR_CTRL |= ETHSW_LK_ADDR_LOOKUP;
+        while (true == p_switch_reg->LK_ADDR_CTRL_b.BUSY)
+        {
+            ETHSW_ERROR_RETURN((0 != timeout), FSP_ERR_TIMEOUT);
+            timeout--;
+        }
+
+        /* Address is already there. Just update the port mask and priority */
+        if (p_switch_reg->LK_DATA_HI & ETHSW_LK_ADDR_REG_VALID)
+        {
+            /* update port bit mask  */
+            p_switch_reg->LK_DATA_HI &= ~(uint32_t) ETHSW_LK_ADDR_PORTMASK;
+            p_switch_reg->LK_DATA_HI |= (port_mask << ETHSW_LK_ADDR_PORT_REG_OFFSET);
+
+            /* updated priority */
+            p_switch_reg->LK_DATA_HI &= ~(uint32_t) ETHSW_LK_ADDR_PRIOMASK;
+            p_switch_reg->LK_DATA_HI |= (p_mac_entry_info->priority << ETHSW_LK_ADDR_PRIO_REG_OFFSET) &
+                                        ETHSW_LK_ADDR_PRIOMASK;
+        }
+        else
+        {
+            /* New static entry to be created */
+            p_switch_reg->LK_DATA_HI &= ~ETHSW_LK_ADDR_MASKANDFLAGS_MASK;
+            p_switch_reg->LK_DATA_HI |= ETHSW_LK_ADDR_REG_VALID;
+            p_switch_reg->LK_DATA_HI |= ETHSW_LK_ADDR_REG_TYPE;
+            p_switch_reg->LK_DATA_HI |= port_mask << ETHSW_LK_ADDR_PORT_REG_OFFSET;
+            p_switch_reg->LK_DATA_HI |= (p_mac_entry_info->priority << ETHSW_LK_ADDR_PRIO_REG_OFFSET) &
+                                        ETHSW_LK_ADDR_PRIOMASK;
+        }
+
+        /* trigger MAC table write */
+        p_switch_reg->LK_ADDR_CTRL |= ETHSW_LK_ADDR_WRITE;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_MacTableSet() */
+
+/*******************************************************************************************************************//**
+ * Retrieves the port mask for the given MAC address from the static MAC table.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_TIMEOUT             Timeout error
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_MacTableGet (ether_switch_ctrl_t * const    p_ctrl,
+                               ethsw_mac_table_entry_addr_t * p_mac_entry_addr,
+                               ethsw_mac_table_entry_info_t * p_mac_entry_info)
+{
+    ethsw_mac_addr_reg_t entry = {0};
+    uint64_t             timeout;      /* timeout */
+    volatile uint32_t    dammy_read;
+    volatile uint32_t    lk_data_hi;
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_mac_entry_addr), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != p_mac_entry_addr->mac_addr), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != *p_mac_entry_addr->mac_addr), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != p_mac_entry_info), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* copy mac address to get valid alignment */
+    memcpy(entry.mac_addr, *p_mac_entry_addr->mac_addr, ETHSW_MAC_ADDR_LENGTH);
+
+    p_switch_reg->LK_DATA_LO = entry.reg_data[0];
+    p_switch_reg->LK_DATA_HI = entry.reg_data[1];
+
+    p_switch_reg->LK_DATA_HI2_b.MEMDATA = p_mac_entry_addr->vlan_id &
+                                          (R_ETHSW_LK_DATA_HI2_MEMDATA_Msk >> R_ETHSW_LK_DATA_HI2_MEMDATA_Pos);
+
+    /* damy read */
+    dammy_read = p_switch_reg->LK_DATA_LO;
+    dammy_read = p_switch_reg->LK_DATA_HI;
+    dammy_read = dammy_read;
+
+    timeout = ETHSW_TIMEOUT_COUNT;
+
+    /* Perform lookup to get address entry */
+    p_switch_reg->LK_ADDR_CTRL |= ETHSW_LK_ADDR_LOOKUP;
+    while (true == p_switch_reg->LK_ADDR_CTRL_b.BUSY)
+    {
+        ETHSW_ERROR_RETURN((0 != timeout), FSP_ERR_TIMEOUT);
+        timeout--;
+    }
+
+    /* Entry found? */
+    lk_data_hi = p_switch_reg->LK_DATA_HI;
+
+    if (ETHSW_LK_ADDR_REG_VALID & lk_data_hi)
+    {
+        /* prrt */
+        p_mac_entry_info->port_mask.mask = (lk_data_hi & ETHSW_LK_ADDR_PORTMASK) >> ETHSW_LK_ADDR_PORT_REG_OFFSET;
+
+        /* priority */
+        p_mac_entry_info->priority = (p_switch_reg->LK_DATA_HI & ETHSW_LK_ADDR_PRIOMASK) >>
+                                     ETHSW_LK_ADDR_PRIO_REG_OFFSET;
+    }
+    else
+    {
+        p_mac_entry_info->port_mask.mask = 0;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_MacTableGet() */
+
+/*******************************************************************************************************************//**
+ *  Configures the MAC learning and aging parameters of MAC table.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_MacTableConfigSet (ether_switch_ctrl_t * const p_ctrl, ethsw_mac_table_config_t * p_mac_table_config)
+{
+    uint32_t reg_val;                  /* Register value */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_mac_table_config), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    reg_val  = p_switch_reg->LK_CTRL & ~((uint32_t) ETHSW_LK_MASK);
+    reg_val |= ((uint32_t) p_mac_table_config->learning << ETHSW_LK_LEARN) |
+               ((uint32_t) p_mac_table_config->aging << ETHSW_LK_AGING) |
+               ((uint32_t) p_mac_table_config->migration << ETHSW_LK_MIGRAT) |
+               ((uint32_t) p_mac_table_config->discard_unknown << ETHSW_LK_DISCUNKN) |
+               ((uint32_t) p_mac_table_config->independent_vlan << ETHSW_LK_PERVLAN);
+
+    p_switch_reg->LK_CTRL = reg_val;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_MacTableConfSet() */
+
+/*******************************************************************************************************************//**
+ * Clears specific types of entries from the MAC table or clears the whole table.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_TIMEOUT             Timeout error
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_MacTableClear (ether_switch_ctrl_t * const p_ctrl, ethsw_mac_table_clear_mode_t * p_mac_table_clear)
+{
+    fsp_err_t res = FSP_ERR_TIMEOUT;   /* result */
+    uint64_t  timeout;                 /* timeout */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_mac_table_clear), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    timeout = ETHSW_TIMEOUT_COUNT;
+
+    switch (*p_mac_table_clear)
+    {
+        case ETHSW_MAC_TABLE_CLEAR_ALL:
+        {
+            p_switch_reg->LK_CTRL_b.CLRTBL = true;
+
+            while (true == p_switch_reg->LK_CTRL_b.CLRTBL)
+            {
+                ETHSW_ERROR_RETURN((0 != timeout), FSP_ERR_TIMEOUT);
+                timeout--;
+            }
+
+            res = FSP_SUCCESS;
+            break;
+        }
+
+        case ETHSW_MAC_TABLE_CLEAR_DYNAMIC:
+        {
+            p_switch_reg->LK_ADDR_CTRL_b.CLR_DYNAMIC = true;
+
+            while (true == p_switch_reg->LK_ADDR_CTRL_b.CLR_DYNAMIC)
+            {
+                ETHSW_ERROR_RETURN((0 != timeout), FSP_ERR_TIMEOUT);
+                timeout--;
+            }
+
+            res = FSP_SUCCESS;
+            break;
+        }
+
+        case ETHSW_MAC_TABLE_CLEAR_STATIC:
+        {
+            p_switch_reg->LK_ADDR_CTRL_b.CLR_STATIC = true;
+
+            while (true == p_switch_reg->LK_ADDR_CTRL_b.CLR_STATIC)
+            {
+                ETHSW_ERROR_RETURN((0 != timeout), FSP_ERR_TIMEOUT);
+                timeout--;
+            }
+
+            res = FSP_SUCCESS;
+            break;
+        }
+
+        default:
+        {
+            res = FSP_ERR_INVALID_ARGUMENT;
+            break;
+        }
+    }
+
+    return res;
+}                                      /* End of function R_ETHSW_MacTableClear() */
+
+/*******************************************************************************************************************//**
+ * Sets learning state for the given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_LearningSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool enable)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type          * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* set learning state */
+    if (true == enable)
+    {
+        p_switch_reg->INPUT_LEARN_BLOCK_b.LEARNDIS &= ~(1U << port) & ETHSW_4BITS_MASK;
+    }
+    else
+    {
+        p_switch_reg->INPUT_LEARN_BLOCK_b.LEARNDIS = (p_switch_reg->INPUT_LEARN_BLOCK_b.LEARNDIS | (1U << port)) &
+                                                     ETHSW_4BITS_MASK;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_LearningSet() */
+
+/*******************************************************************************************************************//**
+ * Enables the forwarding of incoming frames on a port for RSTP.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_PortForwardAdd (ether_switch_ctrl_t * const p_ctrl, uint32_t port)
+{
+    uint32_t block;                    /* register value */
+    uint32_t tx;                       /* register value */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    block  = p_switch_reg->INPUT_LEARN_BLOCK_b.BLOCKEN;
+    block &= ~(1U << port);
+
+    tx  = p_switch_reg->PORT_ENA_b.TXENA;
+    tx |= (1U << port);
+
+    p_switch_reg->INPUT_LEARN_BLOCK_b.BLOCKEN = block & ETHSW_4BITS_MASK;
+
+    p_switch_reg->PORT_ENA_b.TXENA = tx & ETHSW_4BITS_MASK;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disables the forwarding of incoming frames on a port for RSTP
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_PortForwardDel (ether_switch_ctrl_t * const p_ctrl, uint32_t port)
+{
+    uint32_t block;                    /* register value */
+    uint32_t tx;                       /* register value */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    block  = p_switch_reg->INPUT_LEARN_BLOCK_b.BLOCKEN;
+    block |= (1U << port);
+
+    tx  = p_switch_reg->PORT_ENA_b.TXENA;
+    tx &= ~(1U << port);
+
+    p_switch_reg->INPUT_LEARN_BLOCK_b.BLOCKEN = block & ETHSW_4BITS_MASK;
+
+    p_switch_reg->PORT_ENA_b.TXENA = tx & ETHSW_4BITS_MASK;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_PortForwardAdd() */
+
+/*******************************************************************************************************************//**
+ * Set the flood domain port masks for frames with unknown destinations
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_FloodUnknownSet (ether_switch_ctrl_t * const p_ctrl, ethsw_flood_unknown_config_t * p_flood_config)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_flood_config), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->BCAST_DEFAULT_MASK0_b.BCASTDM = p_flood_config->port_mask_bcast.mask &
+                                                  (R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Msk >>
+                                                   R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Pos);
+
+    p_switch_reg->MCAST_DEFAULT_MASK0_b.MCASTDM = p_flood_config->port_mask_mcast.mask &
+                                                  (R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Msk >>
+                                                   R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Pos);
+
+    p_switch_reg->UCAST_DEFAULT_MASK0_b.UCASTDM = p_flood_config->port_mask_ucast.mask &
+                                                  (R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Msk >>
+                                                   R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Pos);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_FloodUnknownSet() */
+
+/*******************************************************************************************************************//**
+ * Return link state for given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_LinkStateGet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_link_status_t * p_state_link)
+{
+    const volatile uint32_t * p_reg;   /* Register */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_state_link), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_reg = (const volatile uint32_t *) ((uint8_t *) &p_switch_reg->STATUS_P0 +
+                                         ETHSW_PORT_OFFSET * port);
+
+    *p_state_link = (*p_reg & ETHSW_PHY_LINK) ?
+                    ETHSW_LINK_STATE_UP : ETHSW_LINK_STATE_DOWN;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_LinkStateGet() */
+
+/*******************************************************************************************************************//**
+ * Sets maximum frame size of given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_FrameSizeMaxSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint32_t frame_size_max)
+{
+    volatile uint32_t * p_reg;         /* Register */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* calculate per port address of the frame size register */
+    p_reg = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->FRM_LENGTH_P0 + (ETHSW_PORT_OFFSET * port));
+
+    /* assign masked command data to register */
+    *p_reg = frame_size_max & ETHSW_FRAMESIZE_MASK;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_FrameSizeMaxSet() */
+
+/*******************************************************************************************************************//**
+ * Initialize DLR module
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_TIMEOUT             Timeout error
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrInitSet (ether_switch_ctrl_t * const p_ctrl, ethsw_dlr_init_t * p_dlr_init)
+{
+    ethsw_mac_table_entry_addr_t mac_entry_addr = {0}; // Address in MAC table entry
+    ethsw_mac_table_entry_info_t mac_entry_info = {0}; // Information in MAC table entry
+    fsp_err_t res;                                     // result
+    uint8_t   cnt;                                     // loop counter
+
+    /* Multicast MAC for Beacon Frames */
+    uint8_t dlr_mac[ETHSW_MAC_ADDR_LENGTH] = ETHSW_MULTICAST_BEACON;
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_dlr_init), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* Forced Forwarding via Static MAC Table entries */
+    mac_entry_addr.mac_addr = (ethsw_mac_addr_t *) &dlr_mac;
+
+    /* --> Beacon Frames (01:21:6c:00:00:01) ports 0, 1 */
+    dlr_mac[5] = 0x01;
+    mac_entry_info.port_mask.mask = ETHSW_PORT_BIT(0) | ETHSW_PORT_BIT(1);
+
+    res = R_ETHSW_MacTableSet(p_ctrl, &mac_entry_addr, &mac_entry_info);
+    if (FSP_SUCCESS != res)
+    {
+        return res;
+    }
+
+    /* --> Neighbor_Check/SignOn Frames (01:21:6c:00:00:02) port 3 */
+    dlr_mac[5] = 0x02;
+    mac_entry_info.port_mask.mask = ETHSW_PORT_BIT(ETHSW_PORT_MGMT);
+
+    res = R_ETHSW_MacTableSet(p_ctrl, &mac_entry_addr, &mac_entry_info);
+    if (FSP_SUCCESS != res)
+    {
+        return res;
+    }
+
+    /* --> other Frames (01:21:6c:00:00:{03..05}) ports 0, 1, 3 */
+    mac_entry_info.port_mask.mask = ETHSW_PORT_BIT(0) | ETHSW_PORT_BIT(1) | ETHSW_PORT_BIT(ETHSW_PORT_MGMT);
+    for (cnt = 3; cnt < 6; cnt++)
+    {
+        dlr_mac[5] = cnt;
+        res        = R_ETHSW_MacTableSet(p_ctrl, &mac_entry_addr, &mac_entry_info);
+        if (FSP_SUCCESS != res)
+        {
+            return res;
+        }
+    }
+
+    /* write local MAC for Loop Filter */
+    uint8_t * p_host_addr = (uint8_t *) p_dlr_init->p_host_addr;
+
+    p_switch_reg->DLR_LOC_MAClo = (((uint32_t) p_host_addr[0] << 0) |
+                                   ((uint32_t) p_host_addr[1] << 8) |
+                                   ((uint32_t) p_host_addr[2] << 16) |
+                                   ((uint32_t) p_host_addr[3] << 24));
+
+    p_switch_reg->DLR_LOC_MAChi = (((uint32_t) p_host_addr[4] << 0) |
+                                   ((uint32_t) p_host_addr[5] << 8));
+
+    /* callback function pointer  */
+    gp_ethsw_dlr_callback = p_dlr_init->p_dlr_callback;
+
+    /* set DLR EtherType */
+    p_switch_reg->DLR_ETH_TYP_b.DLR_ETH_TYP = ETHSW_RN_ADVSW_DLR_ETHTYPE;
+
+    /* set number of cycles for 1 us */
+    /* 200 MHz -> 200 Ticks = 1 us */
+    p_switch_reg->DLR_CONTROL_b.US_TIME = ETHSW_RN_ADVSW_DLR_TICKS;
+
+    /* discard Bacon frames with invalid Timeout values  */
+    p_switch_reg->DLR_CONTROL_b.IGNORE_INVTM = 0;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrInitSet() */
+
+/*******************************************************************************************************************//**
+ * Uninitialize DLR module
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_TIMEOUT             Timeout error
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrUninitSet (ether_switch_ctrl_t * const p_ctrl)
+{
+    uint8_t dlr_mac[ETHSW_MAC_ADDR_LENGTH]      = ETHSW_MULTICAST_DLR; // Multicast MAC for DLR
+    ethsw_mac_table_entry_addr_t mac_entry_addr = {0};                 // Address in MAC table entry
+    ethsw_mac_table_entry_info_t mac_entry_info = {0};                 // Information in MAC table entry
+    fsp_err_t res;                                                     // result
+    uint32_t  cnt;                                                     // count
+
+    /* initialize MAC Table entries */
+    mac_entry_addr.mac_addr = (ethsw_mac_addr_t *) &dlr_mac;
+
+    for (cnt = 1; cnt < 6; cnt++)
+    {
+        /* set DLR Multicast MAC address */
+        dlr_mac[5] = (uint8_t) cnt;
+
+        /* delete address entry from MAC Table */
+        mac_entry_info.port_mask.mask = 0;
+
+        res = R_ETHSW_MacTableSet(p_ctrl, &mac_entry_addr, &mac_entry_info);
+        if (FSP_SUCCESS != res)
+        {
+            return res;
+        }
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrUninitSet() */
+
+/*******************************************************************************************************************//**
+ * Enable DLR module
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrEnableSet (ether_switch_ctrl_t * const p_ctrl)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* interrupts */
+    p_switch_reg->DLR_IRQ_STAT_ACK = ETHSW_HEX_0000FFFF;
+
+    p_switch_reg->INT_CONFIG_b.IRQ_EN  = 1;
+    p_switch_reg->INT_CONFIG_b.DLR_INT = 1;
+
+    p_switch_reg->DLR_IRQ_CONTROL = ETHSW_TGT_DLR_INT_BEACONTMO_0 |
+                                    ETHSW_TGT_DLR_INT_BEACONTMO_1 |
+                                    ETHSW_TGT_DLR_INT_SUVICHNG |
+                                    ETHSW_TGT_DLR_INT_LNKCHNG_0 |
+                                    ETHSW_TGT_DLR_INT_LNKCHNG_1 |
+                                    ETHSW_TGT_DLR_INT_NEWSTATUS |
+                                    ETHSW_TGT_DLR_INT_LOCALLOOP_0 |
+                                    ETHSW_TGT_DLR_INT_LOCALLOOP_1;
+
+    p_switch_reg->DLR_CONTROL_b.LOOP_FILTER_ENA = 1;
+    p_switch_reg->DLR_CONTROL_b.ENABLE          = 1;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrEnableSet() */
+
+/*******************************************************************************************************************//**
+ * Disable DLR module.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrDisableSet (ether_switch_ctrl_t * const p_ctrl)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->DLR_CONTROL_b.ENABLE          = 0;
+    p_switch_reg->DLR_CONTROL_b.LOOP_FILTER_ENA = 0;
+
+    p_switch_reg->INT_CONFIG_b.DLR_INT = 0;
+    p_switch_reg->DLR_IRQ_CONTROL      = 0;
+    p_switch_reg->DLR_IRQ_STAT_ACK     = ETHSW_HEX_0000FFFF;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrDisableSet() */
+
+/*******************************************************************************************************************//**
+ * Gets the beacon receive status of the specified port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrBeaconStateGet (ether_switch_ctrl_t * const p_ctrl,
+                                     uint32_t                    port,
+                                     ethsw_dlr_beacon_state_t  * p_beacon_state)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_beacon_state), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((2 > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    if (((0 == port) && (0 != (p_switch_reg->DLR_STATUS_b.LastBcnRcvPort & 0x01))) ||
+        ((1 == port) && (0 != (p_switch_reg->DLR_STATUS_b.LastBcnRcvPort & 0x02))))
+    {
+        *p_beacon_state = ETHSW_DLR_BEACON_VALID;
+    }
+    else
+    {
+        *p_beacon_state = ETHSW_DLR_BEACON_INVALID;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrBeaconStateGet() */
+
+/*******************************************************************************************************************//**
+ * Gets DLR node status.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrNodeStateGet (ether_switch_ctrl_t * const p_ctrl, ethsw_dlr_node_state_t * p_node_state)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_node_state), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    *p_node_state = (ethsw_dlr_node_state_t) p_switch_reg->DLR_STATUS_b.NODE_STATE;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrNodeStateGet() */
+
+/*******************************************************************************************************************//**
+ * Gets IP address of DLR supervisor.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrSvIpGet (ether_switch_ctrl_t * const p_ctrl, uint32_t * p_ip_addr)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_ip_addr), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    *p_ip_addr = p_switch_reg->DLR_SUPR_IPADR;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrSvIpGet() */
+
+/*******************************************************************************************************************//**
+ * Gets preference of DLR supervisor.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrSvPriorityGet (ether_switch_ctrl_t * const p_ctrl, uint8_t * p_priority)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_priority), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    *p_priority = p_switch_reg->DLR_SUPR_MAChi_b.PRECE;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrSvPriorityGet() */
+
+/*******************************************************************************************************************//**
+ * Gets VLAN ID of DLR beacon frame.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrVlanGet (ether_switch_ctrl_t * const p_ctrl, uint16_t * p_vlan_info)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_vlan_info), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    *p_vlan_info = p_switch_reg->DLR_STATE_VLAN_b.VLANINFO;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrVlanGet() */
+
+/*******************************************************************************************************************//**
+ * Gets MAC address of DLR beacon frame.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_DlrSvMacGet (ether_switch_ctrl_t * const p_ctrl, ethsw_mac_addr_t * pp_addr_mac)
+{
+    uint32_t regVal;                   /* register value */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != pp_addr_mac), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    regVal            = p_switch_reg->DLR_SUPR_MAClo;
+    (*pp_addr_mac)[0] = (uint8_t) (regVal & ETHSW_HEX_000000FF) >> 0;
+    (*pp_addr_mac)[1] = (uint8_t) ((regVal & ETHSW_HEX_0000FF00) >> 8);
+    (*pp_addr_mac)[2] = (uint8_t) ((regVal & ETHSW_HEX_00FF0000) >> 16);
+    (*pp_addr_mac)[3] = (uint8_t) ((regVal & ETHSW_HEX_FF000000) >> 24);
+
+    regVal            = p_switch_reg->DLR_SUPR_MAChi;
+    (*pp_addr_mac)[4] = (uint8_t) (regVal & ETHSW_HEX_000000FF);
+    (*pp_addr_mac)[5] = (uint8_t) ((regVal & ETHSW_HEX_0000FF00) >> 8);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_DlrSvMacGet() */
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+
+/********************************************************************************************************************//**
+ * Initialization of the Active Stream Identification Table
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpInitilizeAsiTable (ether_switch_ctrl_t * const p_ctrl, ethsw_port_mask_t port_mask)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+ #endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /**************************************************************************
+     * 28.4.19.4 Active Stream Identification
+     **************************************************************************/
+
+    /** Figure 28.55 Active Stream Identification initialization **/
+    p_reg_switch->ASI_MEM_WDATA[0] = 0U;
+    p_reg_switch->ASI_MEM_WDATA[1] = 0U;
+    p_reg_switch->ASI_MEM_WDATA[2] = 0U;
+    p_reg_switch->ASI_MEM_WDATA[3] = 0U;
+
+    for (uint8_t addr = 0; addr < ETHSW_EFP_ASI_ADDR_NUM; addr++)
+    {
+        p_reg_switch->ASI_MEM_ADDR = (uint32_t) (ETHSW_MEM_REQ_ALL_ACCESS | ETHSW_MEM_WEN_ENABLE | addr); /* < 0x700 : MEM_REQ(10:8)=7 | 0x80 : MEM_WEN(7)=1 */
+    }
+
+    /* Extended Frame Parser (EFP) Enable */
+    volatile uint32_t * command_config_pn = &p_reg_switch->COMMAND_CONFIG_P0;
+    for (uint8_t port = 0; port < ETHSW_PORT_COUNT_ALL; port++)
+    {
+        if ((port_mask.mask & (1U << port)))
+        {
+            *command_config_pn = (
+                ((1U << R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Pos) & R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Msk) |
+                ((*command_config_pn) & ~R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Msk)
+                );
+        }
+
+        command_config_pn += ETHSW_COMMAND_CONFIG_OFFSET;
+    }
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpInitilizeAsiTable() */
+
+/********************************************************************************************************************//**
+ * Active Stream Identification entry setting
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_WRITE_FAILED;       Write operation failed ( The table entry is occupied )
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpAsiTableSet (ether_switch_ctrl_t * const p_ctrl, ethsw_efp_asi_t * p_efp_asi_entry)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+    uint8_t                 addr;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN((NULL != p_efp_asi_entry), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /** Figure 28.56 Active Stream Identification entry setting **/
+    /* Hash calculation (CRC-7) */
+    addr =
+        r_ethsw_calc_hash((ethsw_mac_addr_t *) &(p_efp_asi_entry->dmaci),
+                          (ethsw_vlan_vid_t *) &(p_efp_asi_entry->vidi));
+
+    p_reg_switch->ASI_MEM_ADDR_b.ADDR    = (addr & R_ETHSW_ASI_MEM_ADDR_ADDR_Msk);
+    p_reg_switch->ASI_MEM_ADDR_b.MEM_WEN = 0x0U;
+    p_reg_switch->ASI_MEM_ADDR_b.MEM_REQ =
+        (uint32_t) ((1UL << p_efp_asi_entry->port) &
+                    (R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk >> R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos));
+
+    if ((R_ETHSW->ASI_MEM_RDATA[0] & 0x1U) == 0)
+    {
+        p_reg_switch->ASI_MEM_WDATA[3] = (uint32_t) (
+            (p_efp_asi_entry->dmaci[0] << 24) |
+            (p_efp_asi_entry->dmaci[1] << 16) |
+            (p_efp_asi_entry->dmaci[2] << 8) |
+            (p_efp_asi_entry->dmaci[3])
+            );
+        p_reg_switch->ASI_MEM_WDATA[2] = (uint32_t) (
+            (p_efp_asi_entry->dmaci[4] << 24) |
+            (p_efp_asi_entry->dmaci[5] << 16) |
+            (p_efp_asi_entry->vidi[0] << 12) |
+            (p_efp_asi_entry->vidi[1] << 4) |
+            (p_efp_asi_entry->dmaco[0] >> 4)
+            );
+        p_reg_switch->ASI_MEM_WDATA[1] = (uint32_t) (
+            ((p_efp_asi_entry->dmaco[0] & 0x0F) << 28) |
+            (p_efp_asi_entry->dmaco[1] << 20) |
+            (p_efp_asi_entry->dmaco[2] << 12) |
+            (p_efp_asi_entry->dmaco[3] << 4) |
+            (p_efp_asi_entry->dmaco[4] >> 4)
+            );
+        p_reg_switch->ASI_MEM_WDATA[0] = (uint32_t) (
+            ((p_efp_asi_entry->dmaco[4] & 0x0F) << 28) |
+            (p_efp_asi_entry->dmaco[5] << 20) |
+            ((p_efp_asi_entry->vido[0] & 0x0F) << 16) |
+            (p_efp_asi_entry->vido[1] << 8) |
+            ((p_efp_asi_entry->pcpo & 0x07) << 5) |
+            (p_efp_asi_entry->sid << 2) |
+            (p_efp_asi_entry->fs << 1) |
+            (p_efp_asi_entry->ev)
+            );
+
+        p_reg_switch->ASI_MEM_ADDR_b.ADDR    = (addr & R_ETHSW_ASI_MEM_ADDR_ADDR_Msk);
+        p_reg_switch->ASI_MEM_ADDR_b.MEM_WEN = 0x1U;
+        p_reg_switch->ASI_MEM_ADDR_b.MEM_REQ =
+            (uint32_t) ((1UL << p_efp_asi_entry->port) &
+                        (R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk >> R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos));
+    }
+    else
+    {
+        /* The table entry is occupied */
+        err = FSP_ERR_WRITE_FAILED;    /* < Write operation failed */
+    }
+
+ #ifdef ASI_TBL_DEBUG
+
+    /* verify */
+    p_reg_switch->ASI_MEM_ADDR_b.ADDR    = (addr & R_ETHSW_ASI_MEM_ADDR_ADDR_Msk);
+    p_reg_switch->ASI_MEM_ADDR_b.MEM_WEN = 0x0U;
+    p_reg_switch->ASI_MEM_ADDR_b.MEM_REQ =
+        (uint32_t) ((1UL << p_efp_asi_entry->port) &
+                    (R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk >> R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos));
+
+    if ((R_ETHSW->ASI_MEM_RDATA[0] & 0x1U) != 0)
+    {
+        app_printf("table entry [3]:[%08X], [2]:[%08X], [1]:[%08X], [0]:[%08X]\n",
+                   R_ETHSW->ASI_MEM_RDATA[3],
+                   R_ETHSW->ASI_MEM_RDATA[2],
+                   R_ETHSW->ASI_MEM_RDATA[1],
+                   R_ETHSW->ASI_MEM_RDATA[0]);
+    }
+ #endif
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpAsiTableSet() */
+
+/********************************************************************************************************************//**
+ * Active Stream Identification entry deletion
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpAsiTableDelete (ether_switch_ctrl_t * const p_ctrl,
+                                     uint32_t                    port,
+                                     ethsw_mac_addr_t          * dmaci,
+                                     ethsw_vlan_vid_t          * vidi)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+    uint8_t                 addr;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((NULL != dmaci), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != vidi), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /** Figure 28.57 Active Stream Identification entry deletion **/
+    /* Hash calculation (CRC-7) */
+    addr = r_ethsw_calc_hash(dmaci, vidi);
+
+    p_reg_switch->ASI_MEM_ADDR_b.ADDR    = (addr & R_ETHSW_ASI_MEM_ADDR_ADDR_Msk);
+    p_reg_switch->ASI_MEM_ADDR_b.MEM_WEN = 0x0U;
+    p_reg_switch->ASI_MEM_ADDR_b.MEM_REQ = (1U << port) &
+                                           (R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk >> R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos);
+
+    if ((R_ETHSW->ASI_MEM_RDATA[0] & 0x1U) != 0)
+    {
+        p_reg_switch->ASI_MEM_WDATA[0] = 0U;
+        p_reg_switch->ASI_MEM_WDATA[1] = 0U;
+        p_reg_switch->ASI_MEM_WDATA[2] = 0U;
+        p_reg_switch->ASI_MEM_WDATA[3] = 0U;
+
+        p_reg_switch->ASI_MEM_ADDR_b.ADDR    = (addr & R_ETHSW_ASI_MEM_ADDR_ADDR_Msk);
+        p_reg_switch->ASI_MEM_ADDR_b.MEM_WEN = 0x1U;
+        p_reg_switch->ASI_MEM_ADDR_b.MEM_REQ = (1U << port) &
+                                               (R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk >> R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos);
+    }
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpAsiTableDelete() */
+
+/********************************************************************************************************************//**
+ * Set vlan ingress verification mode
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpVlanVerificationModeSet (ether_switch_ctrl_t * const          p_ctrl,
+                                              uint32_t                             port,
+                                              ethsw_vlan_input_verification_mode_t vicm)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN(ETHSW_EFP_VICM_NUM_MAX > vicm, FSP_ERR_INVALID_ARGUMENT);
+ #endif
+
+    /**************************************************************************
+     * 28.4.19.5 VLAN Ingress Verification
+     **************************************************************************/
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    volatile uint32_t * pn_vlan_mode = &p_reg_switch->P0_VLAN_MODE;
+    pn_vlan_mode += (ETHSW_VLAN_MODE_OFFSET * port);
+
+    *pn_vlan_mode = (uint32_t) (
+        ((uint32_t) (vicm << R_ETHSW_P0_VLAN_MODE_VICM_Pos) & R_ETHSW_P0_VLAN_MODE_VICM_Msk) |
+        (*pn_vlan_mode & R_ETHSW_P0_VLAN_MODE_VITM_Msk)
+        );
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpVlanVerificationModeSet() */
+
+/********************************************************************************************************************//**
+ * Set priority reegeneration parameters
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpPriorityRegenerationSet (ether_switch_ctrl_t * const         p_ctrl,
+                                              uint32_t                            port,
+                                              ethsw_efp_priority_regeneration_t * p_pri_regen)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((NULL != p_pri_regen), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    /**************************************************************************
+     * 28.4.19.6 Priority Regeneration
+     **************************************************************************/
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    volatile uint32_t * pn_vlan_mode = &p_reg_switch->P0_VLAN_MODE;
+    pn_vlan_mode += (ETHSW_VLAN_MODE_OFFSET * port);
+    *pn_vlan_mode = (uint32_t) (
+        ((uint32_t) (p_pri_regen->vitm << R_ETHSW_P0_VLAN_MODE_VITM_Pos) & R_ETHSW_P0_VLAN_MODE_VITM_Msk) |
+        (*pn_vlan_mode & R_ETHSW_P0_VLAN_MODE_VICM_Msk)
+        );
+
+    volatile uint32_t * pn_vlan_tag = &p_reg_switch->P0_VLAN_TAG;
+    pn_vlan_tag += (ETHSW_VLAN_TAG_OFFSET * port);
+    *pn_vlan_tag = (uint32_t) (
+        ((uint32_t) ((p_pri_regen->tpid[0] << 8 | p_pri_regen->tpid[1]) << R_ETHSW_P0_VLAN_TAG_TPID_Pos) &
+         R_ETHSW_P0_VLAN_TAG_TPID_Msk) |
+        ((uint32_t) (p_pri_regen->pcp << R_ETHSW_P0_VLAN_TAG_PCP_Pos) & R_ETHSW_P0_VLAN_TAG_PCP_Msk) |
+        ((uint32_t) (p_pri_regen->dei << R_ETHSW_P0_VLAN_TAG_DEI_Pos) & R_ETHSW_P0_VLAN_TAG_DEI_Msk) |
+        ((uint32_t) ((p_pri_regen->vid[0] << 8 | p_pri_regen->vid[1]) << R_ETHSW_P0_VLAN_TAG_VID_Pos) &
+         R_ETHSW_P0_VLAN_TAG_VID_Msk)
+        );
+
+    volatile uint32_t * pn_pcp_remap = &p_reg_switch->P0_PCP_REMAP;
+    pn_pcp_remap += (ETHSW_PCP_REMAP_OFFSET * port);
+    *pn_pcp_remap = (uint32_t) (
+        ((uint32_t) (p_pri_regen->pcp_remap[7] << R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Pos) &
+         R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Msk) |
+        ((uint32_t) (p_pri_regen->pcp_remap[6] << R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Pos) &
+         R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Msk) |
+        ((uint32_t) (p_pri_regen->pcp_remap[5] << R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Pos) &
+         R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Msk) |
+        ((uint32_t) (p_pri_regen->pcp_remap[4] << R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Pos) &
+         R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Msk) |
+        ((uint32_t) (p_pri_regen->pcp_remap[3] << R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Pos) &
+         R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Msk) |
+        ((uint32_t) (p_pri_regen->pcp_remap[2] << R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Pos) &
+         R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Msk) |
+        ((uint32_t) (p_pri_regen->pcp_remap[1] << R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Pos) &
+         R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Msk) |
+        ((uint32_t) (p_pri_regen->pcp_remap[0] << R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Pos) &
+         R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Msk)
+        );
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpPriorityRegenerationSet()*/
+
+/********************************************************************************************************************//**
+ * Set filter function parameters
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpFilterTableSet (ether_switch_ctrl_t * const     p_ctrl,
+                                     uint32_t                        port,
+                                     uint32_t                        sid,
+                                     ethsw_efp_qci_stream_filter_t * p_flt_entry)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN(ETHSW_EFP_SID_NUM_MAX > sid, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((NULL != p_flt_entry), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    /**************************************************************************
+     * 28.4.19.7 Filtering Function
+     **************************************************************************/
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /* Figure 28.61 Qci stream filter table setting flow */
+    volatile uint32_t * pn_qsftbls = &p_reg_switch->P0_QSFTBL0;
+    pn_qsftbls  += ((ETHSW_QSFTBL_OFFSET_PORT * port) + (ETHSW_QSFTBL_OFFSET_SID * sid));
+    *pn_qsftbls &= (uint32_t) ~(R_ETHSW_P0_QSFTBL0_QSTE_Msk);
+    while ((*pn_qsftbls & R_ETHSW_P0_QSFTBL0_QSTE_Msk) != 0)
+    {
+        ;
+    }
+
+    volatile uint32_t * pn_qstmacus = &p_reg_switch->P0_QSTMACU0;
+    pn_qstmacus += ((ETHSW_QSTMACU_OFFSET_PORT * port) + (ETHSW_QSTMACU_OFFSET_SID * sid));
+    *pn_qstmacus = (uint32_t) (
+        (((uint32_t) p_flt_entry->qdasa << R_ETHSW_P1_QSTMACU0_DASA_Pos) & R_ETHSW_P1_QSTMACU0_DASA_Msk) |
+        (((uint32_t) (p_flt_entry->qmac[0] << 8 | p_flt_entry->qmac[1]) << R_ETHSW_P0_QSTMACU0_MACA_Pos) &
+         R_ETHSW_P0_QSTMACU0_MACA_Msk)
+        );
+
+    volatile uint32_t * pn_qstmacds = &p_reg_switch->P0_QSTMACD0;
+    pn_qstmacds += ((ETHSW_QSTMACD_OFFSET_PORT * port) + (ETHSW_QSTMACD_OFFSET_SID * sid));
+    *pn_qstmacds = (
+        ((uint32_t) p_flt_entry->qmac[2] << 24U) |
+        ((uint32_t) p_flt_entry->qmac[3] << 16U) |
+        ((uint32_t) p_flt_entry->qmac[4] << 8U) |
+        ((uint32_t) p_flt_entry->qmac[5])
+        );
+
+    volatile uint32_t * pn_qstmamus = &p_reg_switch->P0_QSTMAMU0;
+    pn_qstmamus += ((ETHSW_QSTMAMU_OFFSET_PORT * port) + (ETHSW_QSTMAMU_OFFSET_SID * sid));
+    *pn_qstmamus = ((uint32_t) (p_flt_entry->qmam[0] << 8 | p_flt_entry->qmam[1]) << R_ETHSW_P0_QSTMAMU0_MACAM_Pos) &
+                   R_ETHSW_P0_QSTMAMU0_MACAM_Msk;
+
+    volatile uint32_t * pn_qstmamds = &p_reg_switch->P0_QSTMAMD0;
+    pn_qstmamds += ((ETHSW_QSTMAMD_OFFSET_PORT * port) + (ETHSW_QSTMAMD_OFFSET_SID * sid));
+    *pn_qstmamds = (
+        ((uint32_t) p_flt_entry->qmam[2] << 24U) |
+        ((uint32_t) p_flt_entry->qmam[3] << 16U) |
+        ((uint32_t) p_flt_entry->qmam[4] << 8U) |
+        ((uint32_t) p_flt_entry->qmam[5])
+        );
+
+    volatile uint32_t * pn_qsftvls = &p_reg_switch->P0_QSFTVL0;
+    pn_qsftvls += ((ETHSW_QSFTVL_OFFSET_PORT * port) + (ETHSW_QSFTVL_OFFSET_SID * sid));
+    *pn_qsftvls = (uint32_t) (
+        ((uint32_t) (p_flt_entry->tagmd << R_ETHSW_P0_QSFTVL0_TAGMD_Pos) & R_ETHSW_P0_QSFTVL0_TAGMD_Msk) |
+        ((uint32_t) (p_flt_entry->dei << R_ETHSW_P0_QSFTVL0_DEI_Pos) & R_ETHSW_P0_QSFTVL0_DEI_Msk) |
+        ((uint32_t) (p_flt_entry->pcp << R_ETHSW_P0_QSFTVL0_PCP_Pos) & R_ETHSW_P0_QSFTVL0_PCP_Msk) |
+        ((uint32_t) ((p_flt_entry->vlanid[0] << 8 | p_flt_entry->vlanid[1]) << R_ETHSW_P0_QSFTVL0_VLANID_Pos) &
+         R_ETHSW_P0_QSFTVL0_VLANID_Msk)
+        );
+
+    volatile uint32_t * pn_qsftvlms = &p_reg_switch->P0_QSFTVLM0;
+    pn_qsftvlms += ((ETHSW_QSFTVLM_OFFSET_PORT * port) + (ETHSW_QSFTVLM_OFFSET_SID * sid));
+    *pn_qsftvlms = (uint32_t) (
+        ((uint32_t) (p_flt_entry->deim << R_ETHSW_P0_QSFTVLM0_DEIM_Pos) & R_ETHSW_P0_QSFTVLM0_DEIM_Msk) |
+        ((uint32_t) (p_flt_entry->pcpm << R_ETHSW_P0_QSFTVLM0_PCPM_Pos) & R_ETHSW_P0_QSFTVLM0_PCPM_Msk) |
+        ((uint32_t) ((p_flt_entry->vlanidm[0] << 8 | p_flt_entry->vlanidm[1]) << R_ETHSW_P0_QSFTVLM0_VLANIDM_Pos) &
+         R_ETHSW_P0_QSFTVLM0_VLANIDM_Msk)
+        );
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpFilterTableSet()*/
+
+/********************************************************************************************************************//**
+ * Qci stream filter table Enable
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpQsfTableEnable (ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint32_t sid, bool qste)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN(ETHSW_EFP_SID_NUM_MAX > sid, FSP_ERR_INVALID_ARGUMENT);
+ #endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    volatile uint32_t * pn_qsftbls = &p_reg_switch->P0_QSFTBL0;
+    pn_qsftbls  += ((ETHSW_QSFTBL_OFFSET_PORT * port) + (ETHSW_QSFTBL_OFFSET_SID * sid));
+    *pn_qsftbls &= (uint32_t) ~R_ETHSW_P0_QSFTBL0_QSTE_Msk;
+    *pn_qsftbls |= (uint32_t) ((uint32_t) (qste << R_ETHSW_P0_QSFTBL0_QSTE_Pos) & R_ETHSW_P0_QSFTBL0_QSTE_Msk);
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpQsfTableEnable()*/
+
+/********************************************************************************************************************//**
+ * Set gating check parameters
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpGatingCheckSet (ether_switch_ctrl_t * const p_ctrl,
+                                     uint32_t                    port,
+                                     uint32_t                    sid,
+                                     ethsw_efp_gating_check_t  * p_gt_chk)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN(ETHSW_EFP_SID_NUM_MAX > sid, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((NULL != p_gt_chk), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    /**************************************************************************
+     * 28.4.19.8 Gating Check
+     **************************************************************************/
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /* Figure 28.62 Gating check process flow */
+    volatile uint32_t * pn_qsftbls = &p_reg_switch->P0_QSFTBL0;
+    pn_qsftbls  += ((ETHSW_QSFTBL_OFFSET_PORT * port) + (ETHSW_QSFTBL_OFFSET_SID * sid));
+    *pn_qsftbls &= (uint32_t) ~R_ETHSW_P0_QSFTBL0_GAIDV_Msk;
+    *pn_qsftbls |=
+        (uint32_t) (((uint32_t) p_gt_chk->gaidv << R_ETHSW_P0_QSFTBL0_GAIDV_Pos) & R_ETHSW_P0_QSFTBL0_GAIDV_Msk);
+    *pn_qsftbls &= (uint32_t) ~R_ETHSW_P0_QSFTBL0_GAID_Msk;
+    *pn_qsftbls |=
+        (uint32_t) (((uint32_t) p_gt_chk->gaid << R_ETHSW_P0_QSFTBL0_GAID_Pos) & R_ETHSW_P0_QSFTBL0_GAID_Msk);
+
+    volatile uint32_t * pn_qgmod = &p_reg_switch->P0_QGMOD;
+    pn_qgmod  += (ETHSW_QGMOD_OFFSET * port);
+    *pn_qgmod &= ~((1U << p_gt_chk->gaid) << R_ETHSW_P0_QGMOD_QGMOD_Pos);
+    *pn_qgmod |= (uint32_t) ((uint32_t) (p_gt_chk->qgmod << p_gt_chk->gaid) & R_ETHSW_P0_QGMOD_QGMOD_Msk);
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpGatingCheckSet()*/
+
+/********************************************************************************************************************//**
+ * Set SDUmax verification parameters
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpSDUmaxVerificationSet (ether_switch_ctrl_t * const        p_ctrl,
+                                            uint32_t                           port,
+                                            uint32_t                           sid,
+                                            ethsw_efp_sdu_max_verification_t * p_sdumax)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN(ETHSW_EFP_SID_NUM_MAX > sid, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((NULL != p_sdumax), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    /**************************************************************************
+     * 28.4.19.9 SDUmax Verification
+     **************************************************************************/
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    volatile uint32_t * pn_qsftbls = &p_reg_switch->P0_QSFTBL0;
+    pn_qsftbls  += ((ETHSW_QSFTBL_OFFSET_PORT * port) + (ETHSW_QSFTBL_OFFSET_SID * sid));
+    *pn_qsftbls &=
+        (uint32_t) ~(R_ETHSW_P0_QSFTBL0_QSMSM_Msk | R_ETHSW_P0_QSFTBL0_MSDUE_Msk | R_ETHSW_P0_QSFTBL0_MSDU_Msk);
+    *pn_qsftbls |= (uint32_t) (
+        (((uint32_t) p_sdumax->qsmsm << R_ETHSW_P0_QSFTBL0_QSMSM_Pos) & R_ETHSW_P0_QSFTBL0_QSMSM_Msk) |
+        (((uint32_t) p_sdumax->msdue << R_ETHSW_P0_QSFTBL0_MSDUE_Pos) & R_ETHSW_P0_QSFTBL0_MSDUE_Msk) |
+        (((uint32_t) p_sdumax->msdu << R_ETHSW_P0_QSFTBL0_MSDU_Pos) & R_ETHSW_P0_QSFTBL0_MSDU_Msk)
+        );
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpSDUmaxVerificationSet()*/
+
+/********************************************************************************************************************//**
+ * Set flow metering parameters
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpFlowMeteringSet (ether_switch_ctrl_t * const p_ctrl,
+                                      uint32_t                    port,
+                                      uint32_t                    sid,
+                                      ethsw_efp_flow_metering_t * p_meter)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN(ETHSW_EFP_SID_NUM_MAX > sid, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((NULL != p_meter), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN(ETHSW_EFP_MEID_NUM_MAX > p_meter->meid, FSP_ERR_INVALID_ARGUMENT);
+ #endif
+
+    /**************************************************************************
+     * 28.4.19.10 Flow Metering
+     **************************************************************************/
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /* Figure 28.66 Flow Meter setting flow */
+    volatile uint32_t * pn_qsftbls = &p_reg_switch->P0_QSFTBL0;
+    pn_qsftbls  += ((ETHSW_QSFTBL_OFFSET_PORT * port) + (ETHSW_QSFTBL_OFFSET_SID * sid));
+    *pn_qsftbls &= (uint32_t) ~(R_ETHSW_P0_QSFTBL0_MEIDV_Msk | R_ETHSW_P0_QSFTBL0_MEID_Msk);
+    *pn_qsftbls |= (uint32_t) (
+        (((uint32_t) p_meter->meidv << R_ETHSW_P0_QSFTBL0_MEIDV_Pos) & R_ETHSW_P0_QSFTBL0_MEIDV_Msk) |
+        (((uint32_t) p_meter->meid << R_ETHSW_P0_QSFTBL0_MEID_Pos) & R_ETHSW_P0_QSFTBL0_MEID_Msk)
+        );
+
+    volatile uint32_t * pn_qmdescm = &p_reg_switch->P0_QMDESC0;
+    pn_qmdescm  += ((ETHSW_QMDESC_OFFSET_PORT * port) + (ETHSW_QMDESC_OFFSET_METER * p_meter->meid));
+    *pn_qmdescm &= (uint32_t) ~(R_ETHSW_P0_QMDESC0_CF_Msk | R_ETHSW_P0_QMDESC0_MM_Msk | R_ETHSW_P0_QMDESC0_RFD_Msk);
+    *pn_qmdescm |= (uint32_t) (
+        (((uint32_t) p_meter->cf << R_ETHSW_P0_QMDESC0_CF_Pos) |
+         ((uint32_t) p_meter->mm << R_ETHSW_P0_QMDESC0_MM_Pos) |
+         ((uint32_t) p_meter->rfd << R_ETHSW_P0_QMDESC0_RFD_Pos)) &
+        (R_ETHSW_P0_QMDESC0_CF_Msk | R_ETHSW_P0_QMDESC0_MM_Msk | R_ETHSW_P0_QMDESC0_RFD_Msk)
+        );
+
+    volatile uint32_t * pn_qmcbscm = &p_reg_switch->P0_QMCBSC0;
+    pn_qmcbscm += ((ETHSW_QMCBSC_OFFSET_PORT * port) + (ETHSW_QMCBSC_OFFSET_METER * p_meter->meid));
+    *pn_qmcbscm = (p_meter->cbs << R_ETHSW_P0_QMCBSC0_CBS_Pos) & R_ETHSW_P0_QMCBSC0_CBS_Msk;
+
+    volatile uint32_t * pn_qmcircm = &p_reg_switch->P0_QMCIRC0;
+    pn_qmcircm += ((ETHSW_QMCIRC_OFFSET_PORT * port) + (ETHSW_QMCIRC_OFFSET_METER * p_meter->meid));
+    *pn_qmcircm = (p_meter->cir << R_ETHSW_P0_QMCIRC0_CIR_Pos) & R_ETHSW_P0_QMCIRC0_CIR_Msk;
+
+    volatile uint32_t * pn_qmec = &p_reg_switch->P0_QMEC;
+    pn_qmec  += (ETHSW_QMEC_OFFSET * port);
+    *pn_qmec &= ~((1U << p_meter->meid) << R_ETHSW_P0_QMEC_ME_Pos);
+    *pn_qmec |= (uint32_t) (((uint32_t) p_meter->me << p_meter->meid) & R_ETHSW_P0_QMEC_ME_Msk);
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpFlowMeteringSet()*/
+
+/********************************************************************************************************************//**
+ * Configuration of interrupt source for Extended Frame Parser
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpInterruptEnable (ether_switch_ctrl_t * const p_ctrl,
+                                      uint32_t port,
+                                      ethsw_efp_interrupt_source_t * p_conf,
+                                      void (* p_efp_callback_func)(uint32_t, ethsw_efp_event_t))
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((NULL != p_conf), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != p_efp_callback_func), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /* Qci stream filter error interrupt (max SDU over drop) */
+    volatile uint32_t * pn_qseie = &p_reg_switch->P0_QSEIE;
+    volatile uint32_t * pn_qseid = &p_reg_switch->P0_QSEID;
+    pn_qseie  += (ETHSW_QSEIE_OFFSET * port);
+    pn_qseid  += (ETHSW_QSEID_OFFSET * port);
+    *pn_qseie |= (uint32_t) ((uint32_t) p_conf->qsmoi & R_ETHSW_P0_QSEIE_QSMOIE_Msk);
+    *pn_qseid |= (uint32_t) ((uint32_t) (p_conf->qsmoi ^ ETHSW_QSMOI_MASK) & R_ETHSW_P0_QSEID_QSMOID_Msk);
+
+    /* Qci stream gate error interrupt (gating error drop) */
+    volatile uint32_t * pn_qgeie = &p_reg_switch->P0_QGEIE;
+    volatile uint32_t * pn_qgeid = &p_reg_switch->P0_QGEID;
+    pn_qgeie  += (ETHSW_QGEIE_OFFSET * port);
+    pn_qgeid  += (ETHSW_QGEID_OFFSET * port);
+    *pn_qgeie |= (uint32_t) ((uint32_t) p_conf->qgmoi & R_ETHSW_P0_QGEIE_QGMOIE_Msk);
+    *pn_qgeid |= (uint32_t) ((uint32_t) (p_conf->qgmoi ^ ETHSW_QGMOI_MASK) & R_ETHSW_P0_QGEID_QGMOID_Msk);
+
+    /* Qci meter error interrupt (flow meter drop) */
+    volatile uint32_t * pn_qmeie = &p_reg_switch->P0_QMEIE;
+    volatile uint32_t * pn_qmeid = &p_reg_switch->P0_QMEID;
+    pn_qmeie  += (ETHSW_QMEIE_OFFSET * port);
+    pn_qmeid  += (ETHSW_QMEID_OFFSET * port);
+    *pn_qmeie |= (uint32_t) ((uint32_t) p_conf->qrfi & R_ETHSW_P0_QMEIE_QRFIE_Msk);
+    *pn_qmeid |= (uint32_t) ((uint32_t) (p_conf->qrfi ^ ETHSW_QRFI_MASK) & R_ETHSW_P0_QMEID_QRFID_Msk);
+
+    /* Frame parser error interrupt (runtime error) */
+    volatile uint32_t * pn_error_mask = &p_reg_switch->P0_ERROR_MASK;
+    pn_error_mask += (ETHSW_ERROR_MASK_OFFSET * port);
+    uint32_t err_msk_msk = (
+        R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Msk | R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Msk |
+        R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Msk | R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Msk |
+        R_ETHSW_P0_ERROR_MASK_MSOPERR_Msk
+        );
+    *pn_error_mask &= ~(err_msk_msk);
+    *pn_error_mask  = ((uint32_t) p_conf->errmask & err_msk_msk);
+
+    /* Register Extended Frame Parser (EFP) interrupt handler */
+    gp_ethsw_efp_callback = p_efp_callback_func;
+
+    /* Enable Interrupt for Extended Frame Parser */
+    if ((p_conf->qsmoi != 0) || (p_conf->qgmoi != 0) || (p_conf->qrfi != 0))
+    {
+        p_reg_switch->INT_CONFIG_b.EFP_INT = 1;
+    }
+    else
+    {
+        p_reg_switch->INT_CONFIG_b.EFP_INT = 0;
+    }
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpInterruptEnable()*/
+
+/********************************************************************************************************************//**
+ * Get statistics information related Extended Frame Parser
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpStatusGet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_efp_status_t * p_info)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((NULL != p_info), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /* Qci Stream Filter Error Interrupt Status */
+    volatile uint32_t * pn_qseis = &p_reg_switch->P0_QSEIS;
+    pn_qseis      += (ETHSW_QSEIS_OFFSET * port);
+    p_info->qsmois = (*pn_qseis & R_ETHSW_P0_QSEIS_QSMOIS_Msk);
+
+    /* Qci Gate Error Interrupt Status */
+    volatile uint32_t * pn_qgeis = &p_reg_switch->P0_QGEIS;
+    pn_qgeis      += (ETHSW_QGEIS_OFFSET * port);
+    p_info->qgmois = (*pn_qgeis & R_ETHSW_P0_QGEIS_QGMOIS_Msk);
+
+    /* Qci Meter Error Interrupt Statuss */
+    volatile uint32_t * pn_qmeis = &p_reg_switch->P0_QMEIS;
+    pn_qmeis     += (ETHSW_QMEIS_OFFSET * port);
+    p_info->qrfis = (*pn_qmeis & R_ETHSW_P0_QMEIS_QRFIS_Msk);
+
+    /* Frame Parser Runtime Error Status */
+    volatile uint32_t * pn_error_status = &p_reg_switch->P0_ERROR_STATUS;
+    pn_error_status     += (ETHSW_ERROR_STATUS_OFFSET * port);
+    p_info->error_status = (*pn_error_status & ETHSW_ERROR_STATUS_MASK);
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpStatusGet()*/
+
+/********************************************************************************************************************//**
+ * Enable channel by port for Extended Frame Parser
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_EfpChannelEnable (ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool enable)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+ #endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+    if (enable)
+    {
+        p_reg_switch->CHANNEL_ENABLE |= (uint32_t) ((1U << port) & ETHSW_CHANNEL_ENABLE_MASK);
+        while (((p_reg_switch->CHANNEL_STATE >> port) & 0x1U) != 1U)
+        {
+            ;
+        }
+    }
+    else
+    {
+        p_reg_switch->CHANNEL_DISABLE |= (uint32_t) ((1U << port) & ETHSW_CHANNEL_DISABLE_MASK);
+        while (((p_reg_switch->CHANNEL_STATE >> port) & 0x1U) != 0U)
+        {
+            ;
+        }
+    }
+
+    return err;
+}                                      /* End of function R_ETHSW_EfpChannelEnable()*/
+
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+/********************************************************************************************************************//**
+ * Sets Rx pattern matcher
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_RxPatternMatcherSet (ether_switch_ctrl_t * const  p_ctrl,
+                                       ethsw_rx_pattern_matcher_t * p_rx_pattern_matcher)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+
+    R_ETHSW_Type volatile * p_reg_switch;
+
+    uint32_t pattern_mask;
+    uint32_t pattern_ctrl;
+    uint32_t port_num;
+    uint32_t pattern_port_mask;
+    uint32_t port_mask;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_rx_pattern_matcher), FSP_ERR_INVALID_POINTER);
+
+    ETHSW_ERROR_RETURN(ETHSW_RX_PATTERN_MATCHER_COUNT > p_rx_pattern_matcher->pattern_sel, FSP_ERR_INVALID_ARGUMENT)
+    ETHSW_ERROR_RETURN((NULL != p_rx_pattern_matcher->p_pattern_ctrl), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != p_rx_pattern_matcher->p_pattern_data),
+                       FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+    pattern_mask = 1U << p_rx_pattern_matcher->pattern_sel;
+
+    // Disable Rx Patter Mattcher
+    p_reg_switch->RXMATCH_CONFIG_b[0].PATTERN_EN &= ~pattern_mask & R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk;
+    p_reg_switch->RXMATCH_CONFIG_b[1].PATTERN_EN &= ~pattern_mask & R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk;
+    p_reg_switch->RXMATCH_CONFIG_b[2].PATTERN_EN &= ~pattern_mask & R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk;
+    p_reg_switch->RXMATCH_CONFIG_b[3].PATTERN_EN &= ~pattern_mask & R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk;
+
+    pattern_port_mask = p_rx_pattern_matcher->pattern_port_mask.mask;
+
+    if (0 != pattern_port_mask)        // Enable
+    {
+        // Set Rx patter mattcher control
+        pattern_ctrl  = 0;
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->match_not << R_ETHSW_PATTERN_CTRL_MATCH_NOT_Pos) &
+            R_ETHSW_PATTERN_CTRL_MATCH_NOT_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->mgmt_fwd << R_ETHSW_PATTERN_CTRL_MGMTFWD_Pos) &
+            R_ETHSW_PATTERN_CTRL_MGMTFWD_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->discard << R_ETHSW_PATTERN_CTRL_DISCARD_Pos) &
+            R_ETHSW_PATTERN_CTRL_DISCARD_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->set_prio << R_ETHSW_PATTERN_CTRL_SET_PRIO_Pos) &
+            R_ETHSW_PATTERN_CTRL_SET_PRIO_Msk);
+        pattern_ctrl |=
+            (uint32_t) ((uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->mode << R_ETHSW_PATTERN_CTRL_MODE_Pos) &
+                        R_ETHSW_PATTERN_CTRL_MODE_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->timer_sel_ovr <<
+                        R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Pos) &
+            R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->force_forward <<
+                        R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Pos) &
+            R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->hub_trigger << R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Pos) &
+            R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->match_red << R_ETHSW_PATTERN_CTRL_MATCH_RED_Pos) &
+            R_ETHSW_PATTERN_CTRL_MATCH_RED_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->match_not_red <<
+                        R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Pos) &
+            R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->vlan_skip << R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Pos) &
+            R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->priority << R_ETHSW_PATTERN_CTRL_PRIORITY_Pos) &
+            R_ETHSW_PATTERN_CTRL_PRIORITY_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->learning_dis << R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Pos) &
+            R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Msk);
+
+        port_mask = p_rx_pattern_matcher->p_pattern_ctrl->port_mask.mask;
+
+        pattern_ctrl |=
+            (uint32_t) ((port_mask << R_ETHSW_PATTERN_CTRL_PORTMASK_Pos) & R_ETHSW_PATTERN_CTRL_PORTMASK_Msk);
+
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->imc_trigger << R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Pos) &
+            R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->imc_trigger_dely <<
+                        R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Pos) & R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->swap_bytes << R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Pos) &
+            R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->match_lt << R_ETHSW_PATTERN_CTRL_MATCH_LT_Pos) &
+            R_ETHSW_PATTERN_CTRL_MATCH_LT_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->timer_sel << R_ETHSW_PATTERN_CTRL_TIMER_SEL_Pos) &
+            R_ETHSW_PATTERN_CTRL_TIMER_SEL_Msk);
+        pattern_ctrl |= (uint32_t) (
+            (uint32_t) (p_rx_pattern_matcher->p_pattern_ctrl->queue_sel << R_ETHSW_PATTERN_CTRL_QUEUESEL_Pos) &
+            R_ETHSW_PATTERN_CTRL_QUEUESEL_Msk);
+
+        p_reg_switch->PATTERN_CTRL[p_rx_pattern_matcher->pattern_sel] = pattern_ctrl;
+
+        // Set Rx patter mattcher data
+        p_reg_switch->PATTERN_SEL  = p_rx_pattern_matcher->pattern_sel;
+        p_reg_switch->PTRN_CMP_30  = p_rx_pattern_matcher->p_pattern_data->reg.cmp_30;
+        p_reg_switch->PTRN_CMP_74  = p_rx_pattern_matcher->p_pattern_data->reg.cmp_74;
+        p_reg_switch->PTRN_CMP_118 = p_rx_pattern_matcher->p_pattern_data->reg.cmp_118;
+        p_reg_switch->PTRN_MSK_30  = p_rx_pattern_matcher->p_pattern_data->reg.msk_30;
+        p_reg_switch->PTRN_MSK_74  = p_rx_pattern_matcher->p_pattern_data->reg.msk_74;
+        p_reg_switch->PTRN_MSK_118 = p_rx_pattern_matcher->p_pattern_data->reg.msk_118;
+
+        if (true == p_rx_pattern_matcher->pattern_int) // IRQ enable
+        {
+            p_reg_switch->PATTERN_IRQ_CONTROL_b.MATCHINT =
+                (p_reg_switch->PATTERN_IRQ_CONTROL_b.MATCHINT | pattern_mask) &
+                R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Msk;
+            p_reg_switch->PATTERN_IRQ_CONTROL_b.ERROR_INT = 0xF;
+            p_reg_switch->INT_CONFIG_b.PATTERN_INT        = 1;
+        }
+        else                           // IRQ disabe
+        {
+            p_reg_switch->PATTERN_IRQ_CONTROL_b.MATCHINT &= ~pattern_mask & R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Msk;
+            if (0 == p_reg_switch->PATTERN_IRQ_CONTROL_b.MATCHINT)
+            {
+                p_reg_switch->PATTERN_IRQ_CONTROL_b.ERROR_INT = 0;
+                p_reg_switch->INT_CONFIG_b.PATTERN_INT        = 0;
+            }
+        }
+
+        // Enable Rx Patter Mattcher
+        for (port_num = 0; port_num <= ETHSW_HOST_PORT_NUMBER; port_num++)
+        {
+            if (pattern_port_mask & (1U << port_num))
+            {
+                p_reg_switch->RXMATCH_CONFIG[port_num] |= pattern_mask;
+            }
+        }
+    }
+    else                               // Disable
+    {
+        p_reg_switch->PATTERN_CTRL[p_rx_pattern_matcher->pattern_sel] = 0;
+
+        p_reg_switch->PATTERN_SEL  = p_rx_pattern_matcher->pattern_sel;
+        p_reg_switch->PTRN_CMP_30  = 0;
+        p_reg_switch->PTRN_CMP_74  = 0;
+        p_reg_switch->PTRN_CMP_118 = 0;
+        p_reg_switch->PTRN_MSK_30  = 0;
+        p_reg_switch->PTRN_MSK_74  = 0;
+        p_reg_switch->PTRN_MSK_118 = 0;
+
+        // IRQ disabe
+        p_reg_switch->PATTERN_IRQ_CONTROL_b.MATCHINT &= ~pattern_mask & R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Msk;
+        if (0 == p_reg_switch->PATTERN_IRQ_CONTROL_b.MATCHINT)
+        {
+            p_reg_switch->PATTERN_IRQ_CONTROL_b.ERROR_INT = 0;
+            p_reg_switch->INT_CONFIG_b.PATTERN_INT        = 0;
+        }
+    }
+
+    return err;
+}
+
+/********************************************************************************************************************//**
+ * Register the callback function for getting events from Rx pattern matcher.
+ * Unregister if NULL is specified in the callback function.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_RxPatternMatcherCallback (
+    ether_switch_ctrl_t * const         p_ctrl,
+    void (                            * p_rx_pattern_callback_func)(
+        ethsw_rx_pattern_event_t        event,
+        ethsw_rx_pattern_event_data_t * p_data))
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    gp_ethsw_rx_pattern_callback = p_rx_pattern_callback_func;
+
+    return err;
+}
+
+/********************************************************************************************************************//**
+ * Set Preemptable queues configures
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_PreemptQueueSet (ether_switch_ctrl_t * const p_ctrl, ethsw_preempt_queue_t * p_preempt_queue)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_preempt_queue), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->MMCTL_PREEMPT_QUEUES_b.PREEMPT_ENA       = p_preempt_queue->preempt_queues;
+    p_reg_switch->MMCTL_PREEMPT_QUEUES_b.PREEMPT_ON_QCLOSE = p_preempt_queue->preempt_on_qclose;
+
+    return err;
+}                                      /* End of function R_ETHSW_PreemptQueueSet() */
+
+/********************************************************************************************************************//**
+ * Set Qbu frame configuration of each ports
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_PreemptPortControlConfigSet (ether_switch_ctrl_t * const        p_ctrl,
+                                               uint32_t                           port,
+                                               ethsw_preempt_port_ctrl_config_t * p_preempt_port_ctrl)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_preempt_port_ctrl), FSP_ERR_INVALID_POINTER);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT > port), FSP_ERR_INVALID_ARGUMENT);                 /* port           : 0 to 2 */
+    ETHSW_ERROR_RETURN(((R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Msk >> R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Pos) >=
+                        p_preempt_port_ctrl->addfragsize),
+                       FSP_ERR_INVALID_ARGUMENT);                                            /* addfragsize    : 0 to 3 */
+    ETHSW_ERROR_RETURN((0 < p_preempt_port_ctrl->tx_verify_time), FSP_ERR_INVALID_ARGUMENT); /* tx_verity_time : 1 to 127 */
+    ETHSW_ERROR_RETURN(((R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Msk >> R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Pos) >=
+                        p_preempt_port_ctrl->tx_verify_time),
+                       FSP_ERR_INVALID_ARGUMENT);                                            /*                           */
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /* set to BR_CONTROL_Pn ( n = port : 0 to 2 ) */
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET * port))->VERIFY_DIS = p_preempt_port_ctrl->verify_dis;
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET * port))->RESPONSE_DIS = p_preempt_port_ctrl->response_dis;
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET *
+      port))->ADDFRAGSIZE =
+        (p_preempt_port_ctrl->addfragsize &
+         (R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Msk >> R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Pos));
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET *
+      port))->TX_VERIFY_TIME =
+        (p_preempt_port_ctrl->tx_verify_time &
+         (R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Msk >> R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Pos));
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET * port))->RX_STRICT_PRE = p_preempt_port_ctrl->rx_strict_pre;
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET * port))->RX_BR_SMD_DIS = p_preempt_port_ctrl->rx_br_smd_dis;
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET * port))->RX_STRICT_BR_CTL = p_preempt_port_ctrl->rx_strict_br_ctl;
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET * port))->TX_MCRC_INV = p_preempt_port_ctrl->tx_mcrc_inv;
+    ((&p_reg_switch->BR_CONTROL_P0_b) +
+     (ETHSW_BR_CONTROL_OFFSET * port))->RX_MCRC_INV = p_preempt_port_ctrl->rx_mcrc_inv;
+
+    return err;
+}                                      /* End of function R_ETHSW_PreemptPortControlConfigSet() */
+
+/********************************************************************************************************************//**
+ * Enable/Disable Qbu frame preempt at each ports
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_PreemptPortControlEnableSet (ether_switch_ctrl_t * const p_ctrl,
+                                               uint32_t                    port,
+                                               bool                        frame_preempt_enable)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT > port), FSP_ERR_INVALID_ARGUMENT); /* port : 0 to 2 */
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    /* set to BR_CONTROL_Pn.PREEMPT_ENA ( n = port : 0 to 2 ) */
+    ((&p_reg_switch->BR_CONTROL_P0_b) + (ETHSW_BR_CONTROL_OFFSET * port))->PREEMPT_ENA = frame_preempt_enable;
+
+    return err;
+}                                      /* End of function R_ETHSW_PreemptPortControlEnableSet() */
+
+/********************************************************************************************************************//**
+ * forces a preempt request using MM_CTL.request(hold_req).
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_PreemptHoldReqForceSet (ether_switch_ctrl_t * const p_ctrl,
+                                          ethsw_port_mask_t           holdreq_request_port_mask)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(((R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Msk >>
+                         R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Pos) >= holdreq_request_port_mask.mask),
+                       FSP_ERR_INVALID_ARGUMENT); /* portmask : 000b to 111b */
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->MMCTL_HOLD_CONTROL_b.Q_HOLD_REQ_FORCE = holdreq_request_port_mask.mask &
+                                                          (R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Msk >>
+                                                           R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Pos);
+
+    return err;
+}                                      /* End of function R_ETHSW_PreemptHoldReqForceSet() */
+
+/********************************************************************************************************************//**
+ * forces a release of preemption request using MM_CTL.request(hold_req).
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_PreemptHoldReqReleaseSet (ether_switch_ctrl_t * const p_ctrl,
+                                            ethsw_port_mask_t           holdreq_release_port_mask)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(((R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Msk >>
+                         R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Pos) >= holdreq_release_port_mask.mask),
+                       FSP_ERR_INVALID_ARGUMENT); /* portmask : 000b to 111b */
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->MMCTL_HOLD_CONTROL_b.Q_HOLD_REQ_RELEASE = holdreq_release_port_mask.mask &
+                                                            (R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Msk >>
+                                                             R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Pos);
+
+    return err;
+}                                      /* End of function R_ETHSW_PreemptHoldReqReleaseSet() */
+
+/********************************************************************************************************************//**
+ * Get a status of frame preemption
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_PreemptStatusGet (ether_switch_ctrl_t * const p_ctrl,
+                                    uint32_t                    port,
+                                    ethsw_preempt_status_t    * p_preempt_status)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_preempt_status), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT > port), FSP_ERR_INVALID_ARGUMENT); /* port : 0 to 2 */
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_preempt_status->verify_status =
+        (ethsw_preempt_verify_status_t) (((&p_reg_switch->STATUS_P0_b) + (ETHSW_STATUS_OFFSET * port))->BR_VERIF_ST);
+    p_preempt_status->preempt_state  = (bool) ((p_reg_switch->MMCTL_PREEMPT_STATUS_b.PREEMPT_STATE >> port) & 0x1);
+    p_preempt_status->hold_req_state = (bool) ((p_reg_switch->MMCTL_PREEMPT_STATUS_b.HOLD_REQ_STATE >> port) & 0x1);
+    p_preempt_status->min_pfrm_adj   =
+        (uint8_t) (p_reg_switch->MMCTL_PREEMPT_EXTRA_b.MIN_PFRM_ADJ &
+                   (R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Msk >> R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Pos));
+    p_preempt_status->last_pfrm_adj =
+        (uint8_t) (p_reg_switch->MMCTL_PREEMPT_EXTRA_b.LAST_PFRM_ADJ &
+                   (R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Msk >> R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Pos));
+
+    return err;
+}                                      /* End of function R_ETHSW_PreemptStatusGet() */
+
+/*******************************************************************************************************************//**
+ * Sets queue gate.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_MmctlQgateSet (ether_switch_ctrl_t * const p_ctrl, ethsw_mmclt_qgate_t * p_mmctl_qgate)
+{
+    uint32_t mmctl_qgate;
+    uint32_t port_mask;
+    uint32_t queue_gate;
+    uint32_t index;
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_mmctl_qgate), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    port_mask = p_mmctl_qgate->port_mask.mask;
+
+    queue_gate = 0;
+    for (index = 0; index < ETHSW_QUEUE_COUNT; index++)
+    {
+        queue_gate |= (uint32_t) (p_mmctl_qgate->action[index] & 0x3) << (index * 2);
+    }
+
+    mmctl_qgate  = (port_mask << R_ETHSW_MMCTL_QGATE_PORT_MASK_Pos) & R_ETHSW_MMCTL_QGATE_PORT_MASK_Msk;
+    mmctl_qgate |= (uint32_t) ((queue_gate << R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Pos) & R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Msk);
+
+    p_switch_reg->MMCTL_QGATE = mmctl_qgate;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_MmctlQgateSet() */
+
+/********************************************************************************************************************//**
+ * Sets memory pool size, in sells
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_MmctlPoolSizeSet (ether_switch_ctrl_t * const p_ctrl, ethsw_mmctl_pool_size_t * p_pool_size)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_pool_size), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN(((ETHSW_MMCTL_POOL_ID_0 == p_pool_size->pool_id) ||
+                        (ETHSW_MMCTL_POOL_ID_1 == p_pool_size->pool_id) ||
+                        (ETHSW_MMCTL_POOL_ID_GLOBAL == p_pool_size->pool_id)),
+                       FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    switch (p_pool_size->pool_id)
+    {
+        case ETHSW_MMCTL_POOL_ID_0:
+        {
+            p_reg_switch->MMCTL_POOL0_CTR_b.CELLS = p_pool_size->cells &
+                                                    (R_ETHSW_MMCTL_POOL0_CTR_CELLS_Msk >>
+                                                     R_ETHSW_MMCTL_POOL0_CTR_CELLS_Pos);
+            break;
+        }
+
+        case ETHSW_MMCTL_POOL_ID_1:
+        {
+            p_reg_switch->MMCTL_POOL1_CTR_b.CELLS = p_pool_size->cells &
+                                                    (R_ETHSW_MMCTL_POOL1_CTR_CELLS_Msk >>
+                                                     R_ETHSW_MMCTL_POOL1_CTR_CELLS_Pos);
+            break;
+        }
+
+        case ETHSW_MMCTL_POOL_ID_GLOBAL:
+        {
+            p_reg_switch->MMCTL_POOL_GLOBAL_b.CELLS = p_pool_size->cells & R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Msk;
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+
+    if ((0 != p_reg_switch->MMCTL_POOL0_CTR_b.CELLS) ||
+        (0 != p_reg_switch->MMCTL_POOL1_CTR_b.CELLS))
+    {
+        p_reg_switch->IMC_CONFIG_b.RSV_ENA = 1;
+    }
+    else
+    {
+        p_reg_switch->IMC_CONFIG_b.RSV_ENA = 0;
+    }
+
+    return err;
+}                                      /* End of function R_ETHSW_MmctlPoolSizeSet() */
+
+/********************************************************************************************************************//**
+ * Assigns a pool to the specified queue.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_MmctlQueueAssignSet (ether_switch_ctrl_t * const p_ctrl, ethsw_mmctl_queue_assign_t * p_queue_assign)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+    uint32_t                qmap;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_queue_assign), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN(((ETHSW_MMCTL_POOL_ID_0 == p_queue_assign->pool_id) ||
+                        (ETHSW_MMCTL_POOL_ID_1 == p_queue_assign->pool_id) ||
+                        (ETHSW_MMCTL_POOL_ID_GLOBAL == p_queue_assign->pool_id)),
+                       FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN(ETHSW_QUEUE_COUNT > p_queue_assign->queue_num, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    qmap  = p_reg_switch->MMCTL_POOL_QMAP;
+    qmap &= (uint32_t)
+            ~((R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Msk | R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Msk) <<
+              (p_queue_assign->queue_num * 4));
+
+    if (ETHSW_MMCTL_POOL_ID_GLOBAL != p_queue_assign->pool_id)
+    {
+        qmap |= (1U << R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Pos) << (p_queue_assign->queue_num * 4);
+        qmap |= (uint32_t)
+                ((uint32_t) (p_queue_assign->pool_id << R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Pos) &
+                 R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Msk) << (p_queue_assign->queue_num * 4);
+    }
+
+    p_reg_switch->MMCTL_POOL_QMAP = qmap;
+
+    return err;
+}                                      /* End of function R_ETHSW_MmctlQueueAssignSet() */
+
+/********************************************************************************************************************//**
+ * Sets length in bytes of the YELLOW period for specified port.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_MmctlYellowLengthSet (ether_switch_ctrl_t * const p_ctrl,
+                                        uint32_t                    port,
+                                        ethsw_yellow_length_t     * p_yellow_length)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+    uint32_t                mmctl_yellow_byte_length;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_yellow_length), FSP_ERR_INVALID_POINTER);
+#endif
+
+    mmctl_yellow_byte_length =
+        (uint32_t) ((uint32_t) (p_yellow_length->enable << R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Pos) &
+                    R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Msk);
+    mmctl_yellow_byte_length |=
+        (uint32_t) ((uint32_t) (p_yellow_length->length << R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Pos) &
+                    R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Msk);
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->MMCTL_YELLOW_BYTE_LENGTH_P[port] = mmctl_yellow_byte_length;
+
+    return err;
+}                                      /* End of function R_ETHSW_MmctlYellowLengthSet() */
+
+/********************************************************************************************************************//**
+ * Sets Queue Flush Event.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_QueueFlushEventSet (ether_switch_ctrl_t * const p_ctrl,
+                                      ethsw_queue_flush_event_t * p_queue_flush_event)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+    uint32_t                mmctl_qflush;
+    uint32_t                port_mask;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_queue_flush_event), FSP_ERR_INVALID_POINTER);
+#endif
+
+    /* remove portmask bit and translate host port if set */
+    port_mask = p_queue_flush_event->port_mask.mask;
+
+    mmctl_qflush = (port_mask << R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Pos) & R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Msk;
+
+    mmctl_qflush |= (uint32_t) (((uint32_t) p_queue_flush_event->queue_mask << R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Pos) &
+                                R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Msk);
+    mmctl_qflush |= (uint32_t) ((uint32_t) (p_queue_flush_event->action << R_ETHSW_MMCTL_QFLUSH_ACTION_Pos) &
+                                R_ETHSW_MMCTL_QFLUSH_ACTION_Msk);
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->MMCTL_QFLUSH = mmctl_qflush;
+
+    return err;
+}                                      /* End of function R_ETHSW_QueueFlushEventSet() */
+
+/********************************************************************************************************************//**
+ * Get the status shows whether there are frames left in the closed queue.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_MmctlQueueClosedNonemptyStatusGet (ether_switch_ctrl_t * const      p_ctrl,
+                                                     ethsw_mmctl_qclosed_nonempty_t * p_qclosed_nonempty)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_qclosed_nonempty), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    uint32_t temp = p_reg_switch->MMCTL_P0_3_QCLOSED_NONEMPTY;
+
+#define MASK_8_BIT    (0xff)
+
+    (*p_qclosed_nonempty)[0] =
+        (uint8_t) (((temp & R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Msk) >>
+                    R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Pos) & MASK_8_BIT);
+    (*p_qclosed_nonempty)[1] =
+        (uint8_t) (((temp & R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Msk) >>
+                    R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Pos) & MASK_8_BIT);
+    (*p_qclosed_nonempty)[2] =
+        (uint8_t) (((temp & R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Msk) >>
+                    R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Pos) & MASK_8_BIT);
+    (*p_qclosed_nonempty)[3] =
+        (uint8_t) (((temp & R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Msk) >>
+                    R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Pos) & MASK_8_BIT);
+
+    return err;
+}                                      /* End of function R_ETHSW_MMctlQueueClosedNonemptyStatusGet() */
+
+/*******************************************************************************************************************//**
+ * Gets Switch Base Statistics counters.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_StatisticsSwitchGet (ether_switch_ctrl_t * const      p_ctrl,
+                                       bool                             clear,
+                                       ethsw_statistics_switch_base_t * p_statistics_switch)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_statistics_switch), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_statistics_switch->total_disc      = p_switch_reg->TOTAL_DISC;
+    p_statistics_switch->total_byt_disc  = p_switch_reg->TOTAL_BYT_DISC;
+    p_statistics_switch->total_frame     = p_switch_reg->TOTAL_FRM;
+    p_statistics_switch->total_byt_frame = p_switch_reg->TOTAL_BYT_FRM;
+
+    if (true == clear)
+    {
+        /* Clear the Statistics counters */
+        p_switch_reg->MODE_CONFIG_b.STATSRESET = 1;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_StatisticSwitchGet() */
+
+/*******************************************************************************************************************//**
+ * Gets MAC Statistics counters for the specified port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_StatisticsMacGet (ether_switch_ctrl_t * const p_ctrl,
+                                    uint32_t                    port,
+                                    ethsw_statistics_mac_t    * p_statistics_mac)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#define SHIFT_32_BITS    32
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_statistics_mac), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_statistics_mac->a_frames_transmitted_ok =
+        ((uint64_t) *(&p_switch_reg->AFRAMESTRANSMITTEDOK_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_frames_transmitted_ok |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_frames_received_ok =
+        ((uint64_t) *(&p_switch_reg->AFRAMESRECEIVEDOK_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_frames_received_ok |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_frame_check_sequence_errors =
+        ((uint64_t) *(&p_switch_reg->AFRAMECHECKSEQUENCEERRORS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_frame_check_sequence_errors |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_alignment_errors =
+        ((uint64_t) *(&p_switch_reg->AALIGNMENTERRORS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_alignment_errors |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_octets_transmitted_ok =
+        ((uint64_t) *(&p_switch_reg->AOCTETSTRANSMITTEDOK_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_octets_transmitted_ok |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_octets_received_ok =
+        ((uint64_t) *(&p_switch_reg->AOCTETSRECEIVEDOK_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_octets_received_ok |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_tx_pause_mac_ctrl_frames =
+        ((uint64_t) *(&p_switch_reg->ATXPAUSEMACCTRLFRAMES_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_tx_pause_mac_ctrl_frames |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_rx_pause_mac_ctrl_frames =
+        ((uint64_t) *(&p_switch_reg->ARXPAUSEMACCTRLFRAMES_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_rx_pause_mac_ctrl_frames |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_in_errors =
+        ((uint64_t) *(&p_switch_reg->IFINERRORS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_in_errors |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_out_errors =
+        ((uint64_t) *(&p_switch_reg->IFOUTERRORS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_out_errors |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_in_ucast_pkts =
+        ((uint64_t) *(&p_switch_reg->IFINUCASTPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_in_ucast_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_in_multicast_pkts =
+        ((uint64_t) *(&p_switch_reg->IFINMULTICASTPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_in_multicast_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_in_broadcast_pkts =
+        ((uint64_t) *(&p_switch_reg->IFINBROADCASTPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_in_broadcast_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_out_discards =
+        ((uint64_t) *(&p_switch_reg->IFOUTDISCARDS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_out_discards |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_out_ucast_pkts =
+        ((uint64_t) *(&p_switch_reg->IFOUTUCASTPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_out_ucast_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_out_multicast_pkts =
+        ((uint64_t) *(&p_switch_reg->IFOUTMULTICASTPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_out_multicast_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->if_out_broadcast_pkts =
+        ((uint64_t) *(&p_switch_reg->IFOUTBROADCASTPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->if_out_broadcast_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_drop_events =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSDROPEVENTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_drop_events |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_octets =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSOCTETS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_octets |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_pkts =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_undersize_pkts =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSUNDERSIZEPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_undersize_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_oversize_pkts =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSOVERSIZEPKTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_oversize_pkts |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_pkts_64_octets =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSPKTS64OCTETS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_pkts_64_octets |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_pkts_65_to_127_octets =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSPKTS65TO127OCTETS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_pkts_65_to_127_octets |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_pkts_128_to_255_octets =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSPKTS128TO255OCTETS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_pkts_128_to_255_octets |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_pkts_256_to_511_octets =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSPKTS256TO511OCTETS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_pkts_256_to_511_octets |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_pkts_512_to_1023_octets =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSPKTS512TO1023OCTETS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_pkts_512_to_1023_octets |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_pkts_1024_to_1518_octets =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSPKTS1024TO1518OCTETS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_pkts_1024_to_1518_octets |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_pkts_1519_to_x_octets =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSPKTS1519TOXOCTETS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_pkts_1519_to_x_octets |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_jabbers =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSJABBERS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_jabbers |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->ether_stats_fragments =
+        ((uint64_t) *(&p_switch_reg->ETHERSTATSFRAGMENTS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->ether_stats_fragments |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->vlan_received_ok =
+        ((uint64_t) *(&p_switch_reg->VLANRECEIVEDOK_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->vlan_received_ok |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->vlan_transmitted_ok =
+        ((uint64_t) *(&p_switch_reg->VLANTRANSMITTEDOK_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->vlan_transmitted_ok |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->frames_retransmitted =
+        ((uint64_t) *(&p_switch_reg->FRAMESRETRANSMITTED_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->frames_retransmitted |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_deferred =
+        ((uint64_t) *(&p_switch_reg->ADEFERRED_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_deferred |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_multiple_collisions =
+        ((uint64_t) *(&p_switch_reg->AMULTIPLECOLLISIONS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_multiple_collisions |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_single_collisions =
+        ((uint64_t) *(&p_switch_reg->ASINGLECOLLISIONS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_single_collisions |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_late_collisions =
+        ((uint64_t) *(&p_switch_reg->ALATECOLLISIONS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_late_collisions |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_excessive_collisions =
+        ((uint64_t) *(&p_switch_reg->AEXCESSIVECOLLISIONS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_excessive_collisions |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    p_statistics_mac->a_carriersense_errors =
+        ((uint64_t) *(&p_switch_reg->ACARRIERSENSEERRORS_P0 + (port * ETHSW_PORT_OFFSET / 4)));
+    p_statistics_mac->a_carriersense_errors |=
+        (((uint64_t) *(&p_switch_reg->STATS_HIWORD_P0 + (port * ETHSW_PORT_OFFSET / 4))) << SHIFT_32_BITS);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_StatisticsMacGet() */
+
+/*******************************************************************************************************************//**
+ * Clears MAC Statistics counters for all ports.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_StatisticsMacClear (ether_switch_ctrl_t * const p_ctrl)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->COMMAND_CONFIG_P0_b.SW_RESET = 1;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_StatisticsMacClear() */
+
+#ifdef ETHSW_EFP_FEATURE_SUPPORTED
+
+/*******************************************************************************************************************//**
+ * Gets EFP Statistics counters for the specified port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_StatisticsEfpGet (ether_switch_ctrl_t * const p_ctrl,
+                                    uint32_t                    port,
+                                    ethsw_statistics_efp_t    * p_statistics_efp)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+ #if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_statistics_efp), FSP_ERR_INVALID_POINTER);
+ #endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+ #define ETHSW_QCI_SID_OFFSET      (0x028U / 4) // Register offset for Qci SID in uint32_t
+ #define ETHSW_QCI_GATE_OFFSET     (0x008U / 4) // Register offset for Qci Gate in uint32_t
+ #define ETHSW_QCI_MATER_OFFSET    (0x014U / 4) // Register offset for Qci Mate in uint32_t
+
+    /* Qci Stream Match Packet Count */
+    volatile const uint32_t * pn_qsmfcs = &p_switch_reg->P0_QSMFC0;
+    pn_qsmfcs += ((ETHSW_PORT_OFFSET / 4) * port);
+    for (uint32_t sid = 0; sid < ETHSW_EFP_SID_COUNT; sid++)
+    {
+        p_statistics_efp->qci_stream_match_pkts[sid] = (*pn_qsmfcs & R_ETHSW_P0_QSMFC0_QSMFC_Msk);
+        pn_qsmfcs += ETHSW_QCI_SID_OFFSET;
+    }
+
+    /* Qci MSDU Passed Packet Count */
+    volatile const uint32_t * pn_qmsppcs = &p_switch_reg->P0_QMSPPC0;
+    pn_qmsppcs += ((ETHSW_PORT_OFFSET / 4) * port);
+    for (uint32_t sid = 0; sid < ETHSW_EFP_SID_COUNT; sid++)
+    {
+        p_statistics_efp->qci_msdu_passed_pkts[sid] = (*pn_qmsppcs & R_ETHSW_P0_QMSPPC0_QMSPPC_Msk);
+        pn_qmsppcs += ETHSW_QCI_SID_OFFSET;
+    }
+
+    /* Qci MSDU Reject Packet Count */
+    volatile const uint32_t * pn_qmsrpcs = &p_switch_reg->P0_QMSRPC0;
+    pn_qmsrpcs += ((ETHSW_PORT_OFFSET / 4) * port);
+    for (uint32_t sid = 0; sid < ETHSW_EFP_SID_COUNT; sid++)
+    {
+        p_statistics_efp->qci_msdu_reject_pkts[sid] = (*pn_qmsrpcs & R_ETHSW_P0_QMSRPC0_QMSRPC_Msk);
+        pn_qmsrpcs += ETHSW_QCI_SID_OFFSET;
+    }
+
+    /* Qci Gate (All) Passed Packet Count */
+    volatile const uint32_t * pn_qgppc = &p_switch_reg->P0_QGPPC;
+    pn_qgppc += ((ETHSW_PORT_OFFSET / 4) * port);
+    p_statistics_efp->qci_gate_passed_pkts = (*pn_qgppc & R_ETHSW_P0_QGPPC_QGPPC_Msk);
+
+    /* Qci Gate g Dropped Packet Count */
+    volatile const uint32_t * pn_qgdpcg = &p_switch_reg->P0_QGDPC0;
+    pn_qgdpcg += ((ETHSW_PORT_OFFSET / 4) * port);
+    for (uint32_t gaid = 0; gaid < ETHER_SWITCH_TDMA_GPIO_COUNT; gaid++)
+    {
+        p_statistics_efp->qci_gate_dropped_pkts[gaid] = (*pn_qgdpcg & R_ETHSW_P0_QGDPC0_QGDPC_Msk);
+        pn_qgdpcg += ETHSW_QCI_GATE_OFFSET;
+    }
+
+    /* Qci Meter Green Packet Count */
+    volatile const uint32_t * pn_qmgpcm = &p_switch_reg->P0_QMGPC0;
+    pn_qmgpcm += ((ETHSW_PORT_OFFSET / 4) * port);
+    for (uint32_t meid = 0; meid < ETHSW_EFP_MEATER_COUNT; meid++)
+    {
+        p_statistics_efp->qci_mater_green_pkts[meid] = (*pn_qmgpcm & R_ETHSW_P0_QMGPC0_QMGPC_Msk);
+        pn_qmgpcm += ETHSW_QCI_MATER_OFFSET;
+    }
+
+    /* Qci Meter Red Packet Count */
+    volatile const uint32_t * pn_qmrpcm = &p_switch_reg->P0_QMRPC0;
+    pn_qmrpcm += ((ETHSW_PORT_OFFSET / 4) * port);
+    for (uint32_t meid = 0; meid < ETHSW_EFP_MEATER_COUNT; meid++)
+    {
+        p_statistics_efp->qci_mater_red_pkts[meid] = (*pn_qmrpcm & R_ETHSW_P0_QMRPC0_QMRPC_Msk);
+        pn_qmrpcm += ETHSW_QCI_MATER_OFFSET;
+    }
+
+    /* VLAN Ingress Check Drop Frame Counter */
+    volatile const uint32_t * pn_vic_drop_cnt = &p_switch_reg->P0_VIC_DROP_CNT;
+    pn_vic_drop_cnt               += ((ETHSW_PORT_OFFSET / 4) * port);
+    p_statistics_efp->vlan_in_drop = (*pn_vic_drop_cnt & R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Msk);
+
+    /* DST Address Lookup Hit Counter */
+    volatile const uint32_t * pn_lookup_hit_cnt = &p_switch_reg->P0_LOOKUP_HIT_CNT;
+    pn_lookup_hit_cnt           += ((ETHSW_PORT_OFFSET / 4) * port);
+    p_statistics_efp->lookup_hit = (*pn_lookup_hit_cnt & R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_StatisticsEfpGet() */
+
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+/*******************************************************************************************************************//**
+ * Gets Global Discard and 802.3br Statistics counters.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_Statistics8023brGet (ether_switch_ctrl_t * const p_ctrl,
+                                       uint32_t                    port,
+                                       bool                        clear,
+                                       ethsw_statistics_8023br_t * p_statistics_8023br)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_statistics_8023br), FSP_ERR_INVALID_POINTER);
+#endif
+
+#define ETHSW_8023BR_PORT_OFFSET    (0x048U / 4) // Register offset for Global Discard and 802.3br Statistics Registers in uint32_t
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->STATN_CONFIG_b.CLEAR_ON_READ = (true == clear) ? 1 : 0;
+
+    p_statistics_8023br->out_disc           = *(&p_switch_reg->ODISC0 + port * ETHSW_8023BR_PORT_OFFSET);
+    p_statistics_8023br->in_disc_vlan       = *(&p_switch_reg->IDISC_VLAN0 + port * ETHSW_8023BR_PORT_OFFSET);
+    p_statistics_8023br->in_disc_untagged   = *(&p_switch_reg->IDISC_UNTAGGED0 + port * ETHSW_8023BR_PORT_OFFSET);
+    p_statistics_8023br->in_disc_blocked    = *(&p_switch_reg->IDISC_BLOCKED0 + port * ETHSW_8023BR_PORT_OFFSET);
+    p_statistics_8023br->in_disc_any        = *(&p_switch_reg->IDISC_ANY0 + port * ETHSW_8023BR_PORT_OFFSET);
+    p_statistics_8023br->in_disc_src_filter = *(&p_switch_reg->IDISC_SRCFLT0 + port * ETHSW_8023BR_PORT_OFFSET);
+
+    if (ETHSW_PORT_COUNT > port)
+    {
+        p_statistics_8023br->tx_hold_req = *(&p_switch_reg->TX_HOLD_REQ_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->tx_frag     = *(&p_switch_reg->TX_FRAG_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->rx_frag     = *(&p_switch_reg->RX_FRAG_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->rx_assy_ok  = *(&p_switch_reg->RX_ASSY_OK_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+
+        p_statistics_8023br->rx_assy_err =
+            (uint16_t) *(&p_switch_reg->RX_ASSY_ERR_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->rx_smd_err =
+            (uint16_t) *(&p_switch_reg->RX_SMD_ERR_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+
+        p_statistics_8023br->tx_verify_ok =
+            (uint8_t) *(&p_switch_reg->TX_VERIFY_OK_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->tx_response_ok =
+            (uint8_t) *(&p_switch_reg->TX_RESPONSE_OK_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->rx_verify_ok =
+            (uint8_t) *(&p_switch_reg->RX_VERIFY_OK_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->rx_response_ok =
+            (uint8_t) *(&p_switch_reg->RX_RESPONSE_OK_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->rx_verify_bad =
+            (uint8_t) *(&p_switch_reg->RX_VERIFY_BAD_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+        p_statistics_8023br->rx_response_bad =
+            (uint8_t) *(&p_switch_reg->RX_RESPONSE_BAD_CNT0 + port * ETHSW_8023BR_PORT_OFFSET);
+    }
+    else
+    {
+        p_statistics_8023br->tx_hold_req     = 0;
+        p_statistics_8023br->tx_frag         = 0;
+        p_statistics_8023br->rx_frag         = 0;
+        p_statistics_8023br->rx_assy_ok      = 0;
+        p_statistics_8023br->rx_assy_err     = 0;
+        p_statistics_8023br->rx_smd_err      = 0;
+        p_statistics_8023br->tx_verify_ok    = 0;
+        p_statistics_8023br->tx_response_ok  = 0;
+        p_statistics_8023br->rx_verify_ok    = 0;
+        p_statistics_8023br->rx_response_ok  = 0;
+        p_statistics_8023br->rx_verify_bad   = 0;
+        p_statistics_8023br->rx_response_bad = 0;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_Statistics8023brGet() */
+
+/*******************************************************************************************************************//**
+ * Gets DLR Statistics counters for the specified port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_StatisticsDlrGet (ether_switch_ctrl_t * const p_ctrl, ethsw_statistics_dlr_t * p_statistics_dlr)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_statistics_dlr), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_statistics_dlr->rx_beacon_ok0  = p_switch_reg->DLR_RX_STAT0;
+    p_statistics_dlr->rx_beacon_err0 = p_switch_reg->DLR_RX_ERR_STAT0;
+    p_statistics_dlr->rx_disc_lf0    = p_switch_reg->DLR_RX_LF_STAT0;
+    p_statistics_dlr->rx_beacon_ok1  = p_switch_reg->DLR_RX_STAT1;
+    p_statistics_dlr->rx_beacon_err1 = p_switch_reg->DLR_RX_ERR_STAT1;
+    p_statistics_dlr->rx_disc_lf1    = p_switch_reg->DLR_RX_LF_STAT1;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_StatisticsDlrGet() */
+
+/*******************************************************************************************************************//**
+ * Sets enable CQF.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_CqfEnableSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_cqf_enable_t * p_cqf_enable)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_cqf_enable), FSP_ERR_INVALID_POINTER);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);                        /* port         : 0 to 3 */
+    ETHSW_ERROR_RETURN((ETHSW_QUEUE_COUNT - 1 > p_cqf_enable->cqf_queue), FSP_ERR_INVALID_ARGUMENT);    /* cqf_queue    : 0 to 6 */
+    ETHSW_ERROR_RETURN((ETHSW_TDMA_GPIO_COUNT > p_cqf_enable->cqf_gate_sel), FSP_ERR_INVALID_ARGUMENT); /* cqf_gate_sel : 0 to 7 */
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->MMCTL_CQF_CTRL_P_b[port].PRIO_ENABLE0 = p_cqf_enable->cqf_enable_priority;
+    p_reg_switch->MMCTL_CQF_CTRL_P_b[port].QUEUE_SEL0   =
+        (p_cqf_enable->cqf_queue &
+         (R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Msk >> R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Pos));
+    p_reg_switch->MMCTL_CQF_CTRL_P_b[port].GATE_SEL0 =
+        (p_cqf_enable->cqf_gate_sel &
+         (R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Msk >> R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Pos));
+    p_reg_switch->MMCTL_CQF_CTRL_P_b[port].USE_SOP0 = p_cqf_enable->use_sop;
+    p_reg_switch->MMCTL_CQF_CTRL_P_b[port].REF_SEL0 = p_cqf_enable->cqf_gate_ref_sel;
+
+    return err;
+}                                      /* End of function R_ETHSW_CqfEnableSet() */
+
+/*******************************************************************************************************************//**
+ * Sets a snooping parser configuration
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_SnoopParserSet (ether_switch_ctrl_t * const p_ctrl, ethsw_snoop_parser_config_t * p_parser_cnf)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+    uint32_t volatile     * p_gparser;
+    uint32_t volatile     * p_garith;
+    uint32_t                gparser;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_parser_cnf), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((2 > p_parser_cnf->arith_block), FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((4 > p_parser_cnf->parser_id), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    if (0 == p_parser_cnf->arith_block)
+    {
+        p_gparser = &p_switch_reg->GPARSER0 + p_parser_cnf->parser_id;
+        p_garith  = &p_switch_reg->GARITH3;
+    }
+    else
+    {
+        p_gparser = &p_switch_reg->GPARSER4 + p_parser_cnf->parser_id;
+        p_garith  = &p_switch_reg->GARITH7;
+    }
+
+    /* Disable parser */
+    *p_gparser &= (uint32_t) ~R_ETHSW_GPARSER0_VALID_Msk;
+    *p_garith  &= ~((1U << p_parser_cnf->parser_id) << R_ETHSW_GARITH0_SEL_MATCH_Pos);
+
+    if (true == p_parser_cnf->enable)
+    {
+        switch (p_parser_cnf->offs_type)
+        {
+            case ETHSW_SNOOP_OFFS_ETHER1:
+            {
+                gparser = R_ETHSW_GPARSER0_OFFSET_DA_Msk;
+                break;
+            }
+
+            case ETHSW_SNOOP_OFFS_ETHER2:
+            {
+                gparser = 0;
+                break;
+            }
+
+            case ETHSW_SNOOP_OFFS_VLAN:
+            {
+                gparser = R_ETHSW_GPARSER0_SKIPVLAN_Msk;
+                break;
+            }
+
+            case ETHSW_SNOOP_OFFS_IPDATA:
+            {
+                gparser = R_ETHSW_GPARSER0_IPDATA_Msk;
+                break;
+            }
+
+            case ETHSW_SNOOP_OFFS_IPPROT:
+            {
+                gparser = R_ETHSW_GPARSER0_IPPROTOCOL_Msk;
+                break;
+            }
+
+            default:
+            {
+                gparser = 0;
+                break;
+            }
+        }
+
+        switch (p_parser_cnf->comp_type)
+        {
+            case ETHSW_SNOOP_COMP_8:
+            {
+                break;
+            }
+
+            case ETHSW_SNOOP_COMP_8OR:
+            {
+                gparser |= R_ETHSW_GPARSER0_CMP_MASK_OR_Msk;
+                break;
+            }
+
+            case ETHSW_SNOOP_COMP_16:
+            {
+                gparser |= R_ETHSW_GPARSER0_CMP16_Msk;
+                break;
+            }
+
+            case ETHSW_SNOOP_COMP_16PLUS:
+            {
+                gparser |= R_ETHSW_GPARSER0_CMP16_Msk;
+                gparser |= R_ETHSW_GPARSER0_OFFSET_PLUS2_Msk;
+                break;
+            }
+
+            default:
+            {
+                break;
+            }
+        }
+
+        if (ETHSW_SNOOP_OFFS_IPPROT != p_parser_cnf->offs_type)
+        {
+            gparser |=
+                (uint32_t) (((uint32_t) p_parser_cnf->offset << R_ETHSW_GPARSER0_OFFSET_Pos) &
+                            R_ETHSW_GPARSER0_OFFSET_Msk);
+        }
+
+        gparser |= (uint32_t) (((uint32_t) p_parser_cnf->comp_value << R_ETHSW_GPARSER0_COMPARE_VAL_Pos) &
+                               R_ETHSW_GPARSER0_COMPARE_VAL_Msk);
+        gparser |= (uint32_t) (((uint32_t) p_parser_cnf->mask_value2 << R_ETHSW_GPARSER3_MASK_VAL2_Pos) &
+                               R_ETHSW_GPARSER3_MASK_VAL2_Msk);
+
+        gparser |= R_ETHSW_GPARSER0_VALID_Msk;
+
+        *p_gparser = gparser;
+
+        /* Enable parser */
+        *p_garith |= (1U << p_parser_cnf->parser_id) << R_ETHSW_GARITH0_SEL_MATCH_Pos;
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets snooping arithmetic configuration
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_SnoopArithSet (ether_switch_ctrl_t * const p_ctrl, ethsw_snoop_arith_config_t * p_arith_cnf)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+    uint32_t volatile     * p_garith;
+    uint32_t                garith;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_arith_cnf), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((2 > p_arith_cnf->arith_block), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    if (0 == p_arith_cnf->arith_block)
+    {
+        p_garith = &p_switch_reg->GARITH3;
+    }
+    else
+    {
+        p_garith = &p_switch_reg->GARITH7;
+    }
+
+    /* Read Snoop Configuration for Arithmetic Register */
+    garith = *p_garith;
+
+    /* Set AND/OR operation*/
+    garith &= (uint32_t) ~R_ETHSW_GARITH0_OP_Msk;
+    if (ETHSW_SNOOP_OPERAT_OR == p_arith_cnf->operat)
+    {
+        garith |= R_ETHSW_GARITH0_OP_Msk;
+    }
+
+    /* Set Snoop Mode*/
+    garith &= (uint32_t) ~R_ETHSW_GARITH0_SNP_MD_Msk;
+    garith |= (uint32_t) (((uint32_t) p_arith_cnf->action << R_ETHSW_GARITH0_SNP_MD_Pos) & R_ETHSW_GARITH0_SNP_MD_Msk);
+
+    /* Write Snoop Configuration for Arithmetic Register */
+    *p_garith = garith;
+
+    return FSP_SUCCESS;
+}                                      /* End of ethsw_snoop_init() */
+
+/*******************************************************************************************************************//**
+ * Enables/disables and configure the Energy Efficient Ethernet Mode of the switch.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_EeeSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_eee_t * p_cnf_eee)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_cnf_eee), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* Disable EEE */
+    (&p_switch_reg->EEE_CTL_STAT_P0_b + (ETHSW_PORT_OFFSET / 4) * port)->EEE_AUTO = 0;
+
+    if (true == p_cnf_eee->enable)
+    {
+        /* Enable EEE */
+        (&p_switch_reg->EEE_CTL_STAT_P0_b + (ETHSW_PORT_OFFSET / 4) * port)->EEE_AUTO = 1;
+
+        *(&p_switch_reg->EEE_IDLE_TIME_P0 + (ETHSW_PORT_OFFSET / 4) * port) = p_cnf_eee->idle_time;
+
+        *(&p_switch_reg->EEE_TWSYS_TIME_P0 + (ETHSW_PORT_OFFSET / 4) * port) = p_cnf_eee->wakeup_time;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_EeeSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the timeframe for the broadcast/multicast rate limiting in ms.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_StormTimeSet (ether_switch_ctrl_t * const p_ctrl, uint16_t storm_time)
+{
+    double val;                        /* value */
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#define ETHSW_ROUND_DECIMAL_PLACES_DOUBLE    ((double) 0.5)
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    val  = (double) storm_time;
+    val  = val * (ETHSW_OPERATING_CLOCK_CYCLES / ETHSW_DEC_1000) / ETHSW_DOS_TIMEFACTOR;
+    val += ETHSW_ROUND_DECIMAL_PLACES_DOUBLE;
+
+    p_switch_reg->BCAST_STORM_LIMIT_b.TMOUT = (uint16_t) val;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_StormTimeSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the max. allowed broadcast frames that can be received in a given time.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_BcastLimitSet (ether_switch_ctrl_t * const p_ctrl, uint16_t storm_frames)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->BCAST_STORM_LIMIT_b.BCASTLIMIT = storm_frames;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_BcastLimitSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the max. allowed multicast frames that can be received in a given time.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_McastLimitSet (ether_switch_ctrl_t * const p_ctrl, uint16_t storm_frames)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->MCAST_STORM_LIMIT_b.MCASTLIMIT = storm_frames;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_McastLimitSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the max. allowed bandwidth for the given port in percent.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TxRateSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, float rate)
+{
+    float               idleslope;     /* Idle Slope value */
+    volatile uint32_t * p_reg;         /* register */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#define ETHSW_RATE_IS_MAX                  (80U)
+#define ETHSW_IDLE_SLOPE_MAX               (2046U)
+#define ETHSW_ROUND_DECIMAL_PLACES_FLOT    (0.5F)
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((ETHSW_RATE_IS_MAX >= rate), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* calculate Traffic Shaper bandwidth control register addresse */
+    p_reg = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->IDLE_SLOPE_P0 + (ETHSW_PORT_OFFSET * port));
+
+    /* Calc idle slope and set it */
+    idleslope  = (ETHSW_DEC_512 * (rate / ETHSW_DEC_100)) / (1 - (rate / ETHSW_DEC_100));
+    idleslope += ETHSW_ROUND_DECIMAL_PLACES_FLOT;
+
+    /* check if calculated slope rate exceeds maximum */
+    if (ETHSW_IDLE_SLOPE_MAX < idleslope)
+    {
+        /* limit slope rate to maximum value */
+        idleslope = ETHSW_IDLE_SLOPE_MAX;
+    }
+
+    /* write slope rate to port specific register (IDLE_SLOPE_P[n]) */
+    *p_reg = (uint16_t) idleslope;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_TxRateSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the priority resolution mode to use for a specific port.
+ * It also defines the default priority if no priority resolution produced a result.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_QosModeSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_qos_mode_t * p_qos_mode)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_qos_mode), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->PRIORITY_CFG_b[port].VLANEN  = (true == p_qos_mode->vlan_enable) ? 1 : 0;
+    p_switch_reg->PRIORITY_CFG_b[port].IPEN    = (true == p_qos_mode->ip_enable) ? 1 : 0;
+    p_switch_reg->PRIORITY_CFG_b[port].MACEN   = (true == p_qos_mode->mac_enable) ? 1 : 0;
+    p_switch_reg->PRIORITY_CFG_b[port].TYPE_EN = (true == p_qos_mode->type_enable) ? 1 : 0;
+
+    p_switch_reg->PRIORITY_CFG_b[port].DEFAULTPRI = p_qos_mode->default_pri &
+                                                    (R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Msk >>
+                                                     R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Pos);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_QosModeSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the priority mapping between VLAN tag priorities and the switch core priorities.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_QosPrioValnSet (ether_switch_ctrl_t * const p_ctrl,
+                                  uint32_t                    port,
+                                  ethsw_qos_prio_vlan_t     * p_qos_prio_vlan)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_qos_prio_vlan), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->VLAN_PRIORITY_b[port].PRIORITY0 = p_qos_prio_vlan->priority0;
+    p_switch_reg->VLAN_PRIORITY_b[port].PRIORITY1 = p_qos_prio_vlan->priority1;
+    p_switch_reg->VLAN_PRIORITY_b[port].PRIORITY2 = p_qos_prio_vlan->priority2;
+    p_switch_reg->VLAN_PRIORITY_b[port].PRIORITY3 = p_qos_prio_vlan->priority3;
+    p_switch_reg->VLAN_PRIORITY_b[port].PRIORITY4 = p_qos_prio_vlan->priority4;
+    p_switch_reg->VLAN_PRIORITY_b[port].PRIORITY5 = p_qos_prio_vlan->priority5;
+    p_switch_reg->VLAN_PRIORITY_b[port].PRIORITY6 = p_qos_prio_vlan->priority6;
+    p_switch_reg->VLAN_PRIORITY_b[port].PRIORITY7 = p_qos_prio_vlan->priority7;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_QosPrioValnSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the priority for the given DiffServ field of an IP packet for the given port.
+ * Up to 64 different DiffServ entries may be defined per port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_QosPrioIpSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_qos_prio_ip_t * p_qos_prio_ip)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_qos_prio_ip), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->IP_PRIORITY[port] = (uint32_t) (
+        (((uint32_t) p_qos_prio_ip->priority << R_ETHSW_IP_PRIORITY_PRIORITY_Pos) & R_ETHSW_IP_PRIORITY_PRIORITY_Msk) |
+        (((uint32_t) p_qos_prio_ip->diffserv << R_ETHSW_IP_PRIORITY_ADDRESS_Pos) &
+         R_ETHSW_IP_PRIORITY_ADDRESS_Msk));
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_QosPrioIpSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the priority for the given Ethertypes to the given values.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_QosPrioTypeSet (ether_switch_ctrl_t * const p_ctrl, ethsw_qos_prio_type_t * p_qos_prio_ethtype)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_qos_prio_ethtype), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    if (0 == p_qos_prio_ethtype->type1)
+    {
+        p_switch_reg->PRIORITY_TYPE1_b.VALID    = 0;
+        p_switch_reg->PRIORITY_TYPE1_b.PRIORITY = 0;
+        p_switch_reg->PRIORITY_TYPE1_b.TYPEVAL  = 0;
+    }
+    else
+    {
+        p_switch_reg->PRIORITY_TYPE1_b.PRIORITY = (uint32_t) p_qos_prio_ethtype->prio1 &
+                                                  (R_ETHSW_PRIORITY_TYPE1_PRIORITY_Msk >>
+                                                   R_ETHSW_PRIORITY_TYPE1_PRIORITY_Pos);
+        p_switch_reg->PRIORITY_TYPE1_b.TYPEVAL = p_qos_prio_ethtype->type1;
+        p_switch_reg->PRIORITY_TYPE1_b.VALID   = 1;
+    }
+
+    if (0 == p_qos_prio_ethtype->type2)
+    {
+        p_switch_reg->PRIORITY_TYPE2_b.VALID    = 0;
+        p_switch_reg->PRIORITY_TYPE2_b.PRIORITY = 0;
+        p_switch_reg->PRIORITY_TYPE2_b.TYPEVAL  = 0;
+    }
+    else
+    {
+        p_switch_reg->PRIORITY_TYPE2_b.PRIORITY = (uint32_t) p_qos_prio_ethtype->prio2 &
+                                                  (R_ETHSW_PRIORITY_TYPE2_PRIORITY_Msk >>
+                                                   R_ETHSW_PRIORITY_TYPE2_PRIORITY_Pos);
+        p_switch_reg->PRIORITY_TYPE2_b.TYPEVAL = p_qos_prio_ethtype->type2;
+        p_switch_reg->PRIORITY_TYPE2_b.VALID   = 1;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_QosPrioTypeSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the dedicated port that will received all frames that are mirrored as well as the type of mirrored frames.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_MirrorSet (ether_switch_ctrl_t * const p_ctrl, ethsw_mirror_conf_t * p_mirror_conf)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+    ethsw_mac_addr_reg_t    entry = {0};
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_mirror_conf), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN(((!(ETHSW_MIRR_MODE_EGRESS_DA == p_mirror_conf->mirror_mode) &&
+                         !(ETHSW_MIRR_MODE_EGRESS_SA == p_mirror_conf->mirror_mode) &&
+                         !(ETHSW_MIRR_MODE_INGRESS_DA == p_mirror_conf->mirror_mode) &&
+                         !(ETHSW_MIRR_MODE_INGRESS_SA == p_mirror_conf->mirror_mode)) ||
+                        (NULL != p_mirror_conf->mac_addr)),
+                       FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* Disable mirroring */
+    p_switch_reg->MIRROR_CONTROL_b.MIRROR_EN = 0;
+
+    /* Set mirror port */
+    p_switch_reg->MIRROR_CONTROL_b.PORT = p_mirror_conf->mirror_port &
+                                          (R_ETHSW_MIRROR_CONTROL_PORT_Msk >> R_ETHSW_MIRROR_CONTROL_PORT_Pos);
+
+    switch (p_mirror_conf->mirror_mode)
+    {
+        /* Match egress dest. address */
+        case ETHSW_MIRR_MODE_EGRESS_DA:
+        {
+            memcpy(entry.mac_addr, *p_mirror_conf->mac_addr, ETHSW_MAC_ADDR_LENGTH);
+            p_switch_reg->MIRROR_EDST_0 = entry.reg_data[0];
+            p_switch_reg->MIRROR_EDST_1 = entry.reg_data[1];
+
+            p_switch_reg->MIRROR_CONTROL_b.EG_DA_MATCH = 1;
+            p_switch_reg->MIRROR_CONTROL_b.MIRROR_EN   = 1;
+            break;
+        }
+
+        /* Match egress src. address */
+        case ETHSW_MIRR_MODE_EGRESS_SA:
+        {
+            memcpy(entry.mac_addr, *p_mirror_conf->mac_addr, ETHSW_MAC_ADDR_LENGTH);
+            p_switch_reg->MIRROR_ESRC_0 = entry.reg_data[0];
+            p_switch_reg->MIRROR_ESRC_1 = entry.reg_data[1];
+
+            p_switch_reg->MIRROR_CONTROL_b.EG_SA_MATCH = 1;
+            p_switch_reg->MIRROR_CONTROL_b.MIRROR_EN   = 1;
+            break;
+        }
+
+        /* Match ingress dest. address */
+        case ETHSW_MIRR_MODE_INGRESS_DA:
+        {
+            memcpy(entry.mac_addr, *p_mirror_conf->mac_addr, ETHSW_MAC_ADDR_LENGTH);
+            p_switch_reg->MIRROR_IDST_0 = entry.reg_data[0];
+            p_switch_reg->MIRROR_IDST_1 = entry.reg_data[1];
+
+            p_switch_reg->MIRROR_CONTROL_b.ING_DA_MATCH = 1;
+            p_switch_reg->MIRROR_CONTROL_b.MIRROR_EN    = 1;
+            break;
+        }
+
+        /* Match ingress src. address */
+        case ETHSW_MIRR_MODE_INGRESS_SA:
+        {
+            memcpy(entry.mac_addr, *p_mirror_conf->mac_addr, ETHSW_MAC_ADDR_LENGTH);
+            p_switch_reg->MIRROR_ISRC_0 = entry.reg_data[0];
+            p_switch_reg->MIRROR_ISRC_1 = entry.reg_data[1];
+
+            p_switch_reg->MIRROR_CONTROL_b.ING_SA_MATCH = 1;
+            p_switch_reg->MIRROR_CONTROL_b.MIRROR_EN    = 1;
+            break;
+        }
+
+        /* Match egress port */
+        case ETHSW_MIRR_MODE_EGRESS_PORT:
+        {
+            /* remove portmask bit and translate host port if set */
+            p_switch_reg->MIRROR_EG_MAP_b.EMAP = p_mirror_conf->port_map.mask &
+                                                 (R_ETHSW_MIRROR_EG_MAP_EMAP_Msk >> R_ETHSW_MIRROR_EG_MAP_EMAP_Pos);
+
+            p_switch_reg->MIRROR_CONTROL_b.EG_MAP_EN = 1;
+            p_switch_reg->MIRROR_CONTROL_b.MIRROR_EN = 1;
+            break;
+        }
+
+        /* Match ingress port */
+        case ETHSW_MIRR_MODE_INGRESS_PORT:
+        {
+            /* remove portmask bit and translate host port if set */
+            p_switch_reg->MIRROR_ING_MAP_b.IMAP = p_mirror_conf->port_map.mask &
+                                                  (R_ETHSW_MIRROR_ING_MAP_IMAP_Msk >> R_ETHSW_MIRROR_ING_MAP_IMAP_Pos);
+
+            p_switch_reg->MIRROR_CONTROL_b.ING_MAP_EN = 1;
+            p_switch_reg->MIRROR_CONTROL_b.MIRROR_EN  = 1;
+            break;
+        }
+
+        /* Disable */
+        case ETHSW_MIRR_MODE_DISABLE:
+        default:
+        {
+            p_switch_reg->MIRROR_CONTROL = 0;
+            break;
+        }
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_MirrorSet() */
+
+/********************************************************************************************************************//**
+ * Sets enable cut-through for the specified port.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_CtEnableSet (ether_switch_ctrl_t * const p_ctrl, ethsw_port_mask_t port_mask)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->MODE_CONFIG_b.CUT_THRU_EN = port_mask.mask &
+                                              (R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Msk >>
+                                               R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Pos);
+
+    return err;
+}                                      /* End of function R_ETHSW_CtEnableSet() */
+
+/********************************************************************************************************************//**
+ * Sets the cut-through delay for the specified port,
+ * delay Value in 400 ns / 40 ns / 8 ns increments (fequency of the MII PHY interface).
+ * This is a programmable value in MII clock cycles that can delay the assertion of the cut-through flag
+ * to the forwarding engine in order to hide the variable latency of the forwarding decision.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_CtDelaySet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint32_t ct_delay)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+    uint32_t volatile     * p_ct_delay_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_ct_delay_reg = (uint32_t volatile *) ((uint8_t *) &p_reg_switch->CT_DELAY_P0 + (ETHSW_PORT_OFFSET * port));
+
+    *p_ct_delay_reg = ct_delay & (R_ETHSW_CT_DELAY_P0_CT_DELAY_Msk >> R_ETHSW_CT_DELAY_P0_CT_DELAY_Pos);
+
+    return err;
+}                                      /* End of function R_ETHSW_CtDelaySet() */
+
+/********************************************************************************************************************//**
+ * Initilize pulse generator.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_PulseGeneratorInit (ether_switch_ctrl_t * const p_ctrl, uint32_t time_num)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSS_Type volatile * p_reg_ethss;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(ETHSW_TIME_COUNT > time_num, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_reg_ethss = p_instance_ctrl->p_reg_ethss;
+
+    r_ethsw_reg_protection_disable(p_instance_ctrl->p_reg_ethss);
+
+    p_reg_ethss->PTPMCTRL_b.PTP_PLS_RSTn = 0;
+
+#if defined(BSP_MCU_GROUP_RZN2H)
+    p_reg_ethss->PTPMCTRL_b.PTP_MODE0 = time_num & (R_ETHSS_PTPMCTRL_PTP_MODE0_Msk >> R_ETHSS_PTPMCTRL_PTP_MODE0_Pos);
+#else
+    p_reg_ethss->PTPMCTRL_b.PTP_MODE = time_num & (R_ETHSS_PTPMCTRL_PTP_MODE_Msk >> R_ETHSS_PTPMCTRL_PTP_MODE_Pos);
+#endif
+
+    p_reg_ethss->PTPMCTRL_b.PTP_PLS_RSTn = 1;
+
+    r_ethsw_reg_protection_enable(p_instance_ctrl->p_reg_ethss);
+
+    return err;
+}                                      /* End of function R_ETHSW_PulseGeneratorInit() */
+
+/********************************************************************************************************************//**
+ * Sets pulse generator.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_PulseGeneratorSet (ether_switch_ctrl_t * const p_ctrl, ethsw_ts_pulse_generator_t * p_pulse)
+{
+    ethsw_instance_ctrl_t     * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t                   err             = FSP_SUCCESS;
+    R_ETHSW_PTP_Type volatile * p_reg_ethsw_ptp;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_pulse), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN(ETHSW_PULSE_GENERATOR_COUNT > p_pulse->pulse_num, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_reg_ethsw_ptp = p_instance_ctrl->p_reg_ethsw_ptp;
+
+    r_ethsw_reg_protection_disable(p_instance_ctrl->p_reg_ethss);
+
+    /* PTP Timer Pulse Output Disable */
+    p_reg_ethsw_ptp->SWTM[p_pulse->pulse_num].EN_b.OUTEN = 0;
+
+    if (true == p_pulse->enable)       // enable
+    {
+        /* Set the Pulse Width of ETHSW_PTPOUTn in the cycle number */
+        p_reg_ethsw_ptp->SWTM[p_pulse->pulse_num].WTH_b.WIDTH = p_pulse->wide;
+
+        /* PTP Timer Pulse Period */
+        p_reg_ethsw_ptp->SWTM[p_pulse->pulse_num].PSEC = p_pulse->period_sec;
+        p_reg_ethsw_ptp->SWTM[p_pulse->pulse_num].PNS  = p_pulse->period_ns;
+
+        /* PTP Timer Pulse Start */
+        p_reg_ethsw_ptp->SWTM[p_pulse->pulse_num].STSEC = p_pulse->start_sec;
+        p_reg_ethsw_ptp->SWTM[p_pulse->pulse_num].STNS  = p_pulse->start_ns;
+
+        /* PTP Timer Pulse Output Enable */
+        p_reg_ethsw_ptp->SWTM[p_pulse->pulse_num].EN_b.OUTEN = p_pulse->enable;
+    }
+
+    r_ethsw_reg_protection_enable(p_instance_ctrl->p_reg_ethss);
+
+    return err;
+}                                      /* End of function R_ETHSW_PulseGeneratorSet() */
+
+/*******************************************************************************************************************//**
+ * Sets authorization state for given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_PortAuthSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool auth_state)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* set authentication */
+    if (false == auth_state)
+    {
+        p_switch_reg->AUTH_PORT_b[port].AUTH = 0;
+    }
+    else
+    {
+        p_switch_reg->AUTH_PORT_b[port].AUTH = 1;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_PortAuhSet() */
+
+/*******************************************************************************************************************//**
+ * Sets controlled direction for given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_PortCtrlDirSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool dir_state)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* check given direction value */
+    if (false == dir_state)
+    {
+        /* set port to controll input and output */
+        p_switch_reg->AUTH_PORT_b[port].CTRL_BOTH = 0;
+    }
+    else
+    {
+        /* set port to control only input */
+        p_switch_reg->AUTH_PORT_b[port].CTRL_BOTH = 1;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_PortCtrlDirSet() */
+
+/*******************************************************************************************************************//**
+ * Sets EAPOL reception mode for given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_PortEapolSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool eapol_state)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN(ETHSW_PORT_COUNT > port, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* set EAPOL reception mode */
+    if (false == eapol_state)
+    {
+        /* enable reception of EAPOL frames */
+        p_switch_reg->AUTH_PORT_b[port].EAPOL_EN = 0;
+    }
+    else
+    {
+        /* disable reception of EAPOL frames */
+        p_switch_reg->AUTH_PORT_b[port].EAPOL_EN = 1;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_PortEapolSet() */
+
+/*******************************************************************************************************************//**
+ * Sest Bridge Protocol Frame (BPDU) forwarding mode.
+ * Enabling the BPDU forwarding mode this function will also disable the unchecked dropping of BPDU frames.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_BpduSet (ether_switch_ctrl_t * const p_ctrl, bool bpdu_state)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* set BPDU forwarding mode */
+    if (false == bpdu_state)
+    {
+        /* Disable BPDU forwarding */
+        p_switch_reg->MGMT_CONFIG_b.ENABLE = 0;
+
+        /* Enable discarding BPDU frames */
+        p_switch_reg->MGMT_CONFIG_b.MGMT_DISC = 1;
+    }
+    else
+    {
+        /* Enable BPDU forwarding */
+        p_switch_reg->MGMT_CONFIG_b.ENABLE = 1;
+
+        /* Disable discarding BPDU frames */
+        p_switch_reg->MGMT_CONFIG_b.DISCARD   = 0;
+        p_switch_reg->MGMT_CONFIG_b.MGMT_DISC = 0;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_BpduSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the default VLAN for input/output processing for the specified port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_VlanDefaultSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint16_t vlan_id)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_switch_reg->SYSTEM_TAGINFO_b[port].SYSVLANINFO = vlan_id &
+                                                       (R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Msk >>
+                                                        R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Pos);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_VlanDefaultSet() */
+
+/*******************************************************************************************************************//**
+ * Adds a VLAN for a given port to the VLAN domain table.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_VlanPortAdd (ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint16_t vlan_id)
+{
+    fsp_err_t err = FSP_ERR_INVALID_ARGUMENT;
+    uint32_t  index;
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* First run: check whether the vlan id entry is already in the table */
+    for (index = 0;
+         index < (sizeof(p_switch_reg->VLAN_RES_TABLE) / sizeof(p_switch_reg->VLAN_RES_TABLE[0]));
+         index++)
+    {
+        if (vlan_id == p_switch_reg->VLAN_RES_TABLE_b[index].VLANID)
+        {
+            uint32_t port_mask = p_switch_reg->VLAN_RES_TABLE_b[index].PORTMASK | (1U << port);
+
+            p_switch_reg->VLAN_RES_TABLE_b[index].PORTMASK = port_mask &
+                                                             (R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk >>
+                                                              R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos);
+
+            err = FSP_SUCCESS;
+            break;
+        }
+    }
+
+    if (FSP_SUCCESS != err)
+    {
+        /* Second run: find free entry and add VLAN id and port */
+        for (index = 0;
+             index < (sizeof(p_switch_reg->VLAN_RES_TABLE) / sizeof(p_switch_reg->VLAN_RES_TABLE[0]));
+             index++)
+        {
+            /* Default VLANid is all bit set */
+            if ((R_ETHSW_VLAN_RES_TABLE_VLANID_Msk >> R_ETHSW_VLAN_RES_TABLE_VLANID_Pos) ==
+                p_switch_reg->VLAN_RES_TABLE_b[index].VLANID)
+            {
+                p_switch_reg->VLAN_RES_TABLE_b[index].VLANID = vlan_id &
+                                                               (R_ETHSW_VLAN_RES_TABLE_VLANID_Msk >>
+                                                                R_ETHSW_VLAN_RES_TABLE_VLANID_Pos);
+                p_switch_reg->VLAN_RES_TABLE_b[index].PORTMASK = (1U << port) &
+                                                                 (R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk >>
+                                                                  R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos);
+
+                err = FSP_SUCCESS;
+                break;
+            }
+        }
+    }
+
+    /* If not FSP_SUCCESS, not VLAN not in table and no free entries left */
+    return err;
+}                                      /* End of function R_ETHSW_VlanPortAdd() */
+
+/*******************************************************************************************************************//**
+ * Removes a VLAN for a given port to the VLAN domain table.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_VlanPortRemove (ether_switch_ctrl_t * const p_ctrl, uint32_t port, uint16_t vlan_id)
+{
+    fsp_err_t err = FSP_ERR_INVALID_ARGUMENT;
+    uint32_t  index;
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* First run: check whether the vlan id entry is already in the table */
+    for (index = 0;
+         index < (sizeof(p_switch_reg->VLAN_RES_TABLE) / sizeof(p_switch_reg->VLAN_RES_TABLE[0]));
+         index++)
+    {
+        if (vlan_id == p_switch_reg->VLAN_RES_TABLE_b[index].VLANID)
+        {
+            /* Remove port from port mask */
+            p_switch_reg->VLAN_RES_TABLE_b[index].PORTMASK &= (~(1U << port)) &
+                                                              (R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk >>
+                                                               R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos);
+
+            /* Reset to default if no more ports are mapped
+             * so the entry is free again for new VLAN ids
+             */
+            if (0 == p_switch_reg->VLAN_RES_TABLE_b[index].PORTMASK)
+            {
+                p_switch_reg->VLAN_RES_TABLE_b[index].PORTMASK = R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk >>
+                                                                 R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos;
+                p_switch_reg->VLAN_RES_TABLE_b[index].VLANID = R_ETHSW_VLAN_RES_TABLE_VLANID_Msk >>
+                                                               R_ETHSW_VLAN_RES_TABLE_VLANID_Pos;
+            }
+
+            err = FSP_SUCCESS;
+            break;
+        }
+    }
+
+    /* If not FSP_SUCCESS, The VLAN id was not in the table so nothing to remove */
+    return err;
+}                                      /* End of function R_ETHSW_VlanPortRemove() */
+
+/*******************************************************************************************************************//**
+ * Sets the mode of VLAN input operations for the given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_VlanInModeSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, ethsw_vlan_in_mode_t vlan_in_mode)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN(((ETHSW_VLANIN_PASSTHROUGH_OVERRIDE == vlan_in_mode) ||
+                        (ETHSW_VLANIN_REPLACE == vlan_in_mode) ||
+                        (ETHSW_VLANIN_TAG_ALWAYS == vlan_in_mode) ||
+                        (ETHSW_VLANIN_DISABLE == vlan_in_mode)),
+                       FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* Disable VLAN input processing ? */
+    if (ETHSW_VLANIN_DISABLE == vlan_in_mode)
+    {
+        /* Disable input processing and reset mode */
+        p_switch_reg->VLAN_IN_MODE_ENA_b.VLANINMDEN &= ~(1U << port) &
+                                                       (R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Msk >>
+                                                        R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Pos);
+
+        switch (port)
+        {
+            case 0:
+            {
+                p_switch_reg->VLAN_IN_MODE_b.P0VLANINMD = 0;
+                break;
+            }
+
+            case 1:
+            {
+                p_switch_reg->VLAN_IN_MODE_b.P1VLANINMD = 0;
+                break;
+            }
+
+            case 2:
+            {
+                p_switch_reg->VLAN_IN_MODE_b.P2VLANINMD = 0;
+                break;
+            }
+
+            case 3:
+            {
+                p_switch_reg->VLAN_IN_MODE_b.P3VLANINMD = 0;
+                break;
+            }
+
+            default:
+            {
+                break;
+            }
+        }
+    }
+    else
+    {
+        switch (port)
+        {
+            case 0:
+            {
+                p_switch_reg->VLAN_IN_MODE_b.P0VLANINMD = vlan_in_mode &
+                                                          (R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Msk >>
+                                                           R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Pos);
+                break;
+            }
+
+            case 1:
+            {
+                p_switch_reg->VLAN_IN_MODE_b.P1VLANINMD = vlan_in_mode &
+                                                          (R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Msk >>
+                                                           R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Pos);
+                break;
+            }
+
+            case 2:
+            {
+                p_switch_reg->VLAN_IN_MODE_b.P2VLANINMD = vlan_in_mode &
+                                                          (R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Msk >>
+                                                           R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Pos);
+                break;
+            }
+
+            case 3:
+            {
+                p_switch_reg->VLAN_IN_MODE_b.P3VLANINMD = vlan_in_mode &
+                                                          (R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Msk >>
+                                                           R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Pos);
+                break;
+            }
+
+            default:
+            {
+                break;
+            }
+        }
+
+        p_switch_reg->VLAN_IN_MODE_ENA_b.VLANINMDEN = (p_switch_reg->VLAN_IN_MODE_ENA_b.VLANINMDEN | (1U << port)) &
+                                                      (R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Msk >>
+                                                       R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Pos);
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_VlanInModeSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the mode of VLAN output operations for the given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_VlanOutModeSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port,
+                                  ethsw_vlan_out_mode_t vlan_out_mode)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN(((ETHSW_VLANOUT_DISABLE == vlan_out_mode) ||
+                        (ETHSW_VLANOUT_STRIP == vlan_out_mode) ||
+                        (ETHSW_VLANOUT_TAGTHROUGH == vlan_out_mode) ||
+                        (ETHSW_VLANOUT_DOMAINTRANSP == vlan_out_mode)),
+                       FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    switch (port)
+    {
+        case 0:
+        {
+            p_switch_reg->VLAN_OUT_MODE_b.P0VLANOUTMD = vlan_out_mode &
+                                                        (R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Msk >>
+                                                         R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Pos);
+            break;
+        }
+
+        case 1:
+        {
+            p_switch_reg->VLAN_OUT_MODE_b.P1VLANOUTMD = vlan_out_mode &
+                                                        (R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Msk >>
+                                                         R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Pos);
+            break;
+        }
+
+        case 2:
+        {
+            p_switch_reg->VLAN_OUT_MODE_b.P2VLANOUTMD = vlan_out_mode &
+                                                        (R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Msk >>
+                                                         R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Pos);
+            break;
+        }
+
+        case 3:
+        {
+            p_switch_reg->VLAN_OUT_MODE_b.P3VLANOUTMD = vlan_out_mode &
+                                                        (R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Msk >>
+                                                         R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Pos);
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_VlanOutModeSet() */
+
+/*******************************************************************************************************************//**
+ * Set VLAN verification for the given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_VlanVerifySet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool enable)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    if (true == enable)
+    {
+        p_switch_reg->VLAN_VERIFY_b.VLANVERI = (p_switch_reg->VLAN_VERIFY_b.VLANVERI | (1U << port)) &
+                                               (R_ETHSW_VLAN_VERIFY_VLANVERI_Msk >> R_ETHSW_VLAN_VERIFY_VLANVERI_Pos);
+    }
+    else
+    {
+        p_switch_reg->VLAN_VERIFY_b.VLANVERI &= ~(1U << port) &
+                                                (R_ETHSW_VLAN_VERIFY_VLANVERI_Msk >> R_ETHSW_VLAN_VERIFY_VLANVERI_Pos);
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_VlanVerifySet() */
+
+/*******************************************************************************************************************//**
+ * Set VLAN discartion of unknown frames for the given port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_VlanDiscardUnknownSet (ether_switch_ctrl_t * const p_ctrl, uint32_t port, bool enable)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT_ALL > port), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    if (true == enable)
+    {
+        p_switch_reg->VLAN_VERIFY_b.VLANDISC = (p_switch_reg->VLAN_VERIFY_b.VLANDISC | (1U << port)) &
+                                               (R_ETHSW_VLAN_VERIFY_VLANDISC_Msk >> R_ETHSW_VLAN_VERIFY_VLANDISC_Pos);
+    }
+    else
+    {
+        p_switch_reg->VLAN_VERIFY_b.VLANDISC &= ~(1U << port) &
+                                                (R_ETHSW_VLAN_VERIFY_VLANDISC_Msk >> R_ETHSW_VLAN_VERIFY_VLANDISC_Pos);
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_VlanDiscardUnknownSet() */
+
+/*******************************************************************************************************************//**
+ * Enable or disable the TDMA scheduler.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TdmaEnableSet (ether_switch_ctrl_t * const p_ctrl, ethsw_tdma_enable_t * p_tdma_enable)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_tdma_enable), FSP_ERR_INVALID_POINTER);
+
+    ETHSW_ERROR_RETURN((ETHSW_TIME_COUNT > p_tdma_enable->time_num), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* disable operation */
+    p_switch_reg->TDMA_CONFIG_b.TDMA_ENA        = 0;
+    p_switch_reg->TDMA_IRQ_CONTROL_b.TCV_INT_EN = 0;
+    p_switch_reg->INT_CONFIG_b.TDMA_INT         = 0;
+
+    p_switch_reg->TDMA_IRQ_STAT_ACK = R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Msk | R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Msk;
+
+    if (true == p_tdma_enable->enable)
+    {
+        /* enable operation */
+
+        gp_ethsw_tdma_callback = p_tdma_enable->p_tdma_callback;
+
+        p_switch_reg->TDMA_START  = p_tdma_enable->tdma_start;
+        p_switch_reg->TDMA_MODULO = p_tdma_enable->tdma_modulo;
+        p_switch_reg->TDMA_CYCLE  = p_tdma_enable->tdma_cycle;
+
+        p_switch_reg->TDMA_ENA_CTRL_b.PORT_ENA = p_tdma_enable->port_mask.mask &
+                                                 (R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Msk >>
+                                                  R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Pos);
+
+        p_switch_reg->TDMA_CONFIG_b.TIMER_SEL = p_tdma_enable->time_num &
+                                                (R_ETHSW_TDMA_CONFIG_TIMER_SEL_Msk >>
+                                                 R_ETHSW_TDMA_CONFIG_TIMER_SEL_Pos);
+
+        p_switch_reg->TDMA_IRQ_CONTROL_b.TCV_INT_EN = 1;
+        p_switch_reg->INT_CONFIG_b.TDMA_INT         = 1;
+        p_switch_reg->INT_CONFIG_b.IRQ_EN           = 1;
+        p_switch_reg->TDMA_CONFIG_b.TDMA_ENA        = 1;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_TdmaEnableSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the TDMA scheduler entry.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TdmaScheduleSet (ether_switch_ctrl_t * const   p_ctrl,
+                                   ethsw_tdma_schedule_entry_t * p_tdma_schedule_entry,
+                                   uint16_t                      tdma_schedule_entry_count)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+    uint32_t index;
+    uint32_t tcv_seq_ctrl;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_tdma_schedule_entry), FSP_ERR_INVALID_POINTER);
+
+    ETHSW_ERROR_RETURN(((0 != tdma_schedule_entry_count) &&
+                        ((R_ETHSW_TCV_D_ADDR_ADDR_Msk >> R_ETHSW_TCV_D_ADDR_ADDR_Pos) >=
+                         tdma_schedule_entry_count) &&
+                        ((R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Msk >> R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Pos) >=
+                         tdma_schedule_entry_count)),
+                       FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    for (index = 0; index < tdma_schedule_entry_count; index++)
+    {
+        /* sets TCV sequence */
+        tcv_seq_ctrl = 0;
+
+        if (0 == index)
+        {
+            tcv_seq_ctrl |= R_ETHSW_TCV_SEQ_CTRL_START_Msk;
+        }
+
+        if (true == p_tdma_schedule_entry[index].interrupt)
+        {
+            tcv_seq_ctrl |= R_ETHSW_TCV_SEQ_CTRL_INT_Msk;
+        }
+
+        tcv_seq_ctrl |= (uint32_t) ((index << R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Pos) & R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Msk);
+        tcv_seq_ctrl |=
+            (uint32_t) (((uint32_t) p_tdma_schedule_entry[index].gpio_mask << R_ETHSW_TCV_SEQ_CTRL_GPIO_Pos) &
+                        R_ETHSW_TCV_SEQ_CTRL_GPIO_Msk);
+
+        p_switch_reg->TCV_SEQ_ADDR = (index << R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Pos) &
+                                     R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Msk;
+        p_switch_reg->TCV_SEQ_CTRL = tcv_seq_ctrl;
+
+        /* sets TCV data */
+        p_switch_reg->TCV_D_ADDR   = (index << R_ETHSW_TCV_D_ADDR_ADDR_Pos) & R_ETHSW_TCV_D_ADDR_ADDR_Msk;
+        p_switch_reg->TCV_D_OFFSET = p_tdma_schedule_entry[index].time_offset;
+
+        p_switch_reg->TCV_D_CTRL_b.QGATE = p_tdma_schedule_entry[index].gate_state &
+                                           (R_ETHSW_TCV_D_CTRL_QGATE_Msk >> R_ETHSW_TCV_D_CTRL_QGATE_Pos);
+
+        p_switch_reg->TCV_D_CTRL_b.PMASK = p_tdma_schedule_entry[index].port_mask.mask &
+                                           (R_ETHSW_TCV_D_CTRL_PMASK_Msk >> R_ETHSW_TCV_D_CTRL_PMASK_Pos);
+        p_switch_reg->TCV_D_CTRL_b.HOLD_REQ     = p_tdma_schedule_entry[index].hold_req;
+        p_switch_reg->TCV_D_CTRL_b.GATE_MODE    = p_tdma_schedule_entry[index].gate_mode;
+        p_switch_reg->TCV_D_CTRL_b.TRIGGER_MODE = p_tdma_schedule_entry[index].trigger_mode;
+        p_switch_reg->TCV_D_CTRL_b.IN_CT_ENA    = p_tdma_schedule_entry[index].in_ct_ena;
+        p_switch_reg->TCV_D_CTRL_b.OUT_CT_ENA   = p_tdma_schedule_entry[index].out_ct_ena;
+        p_switch_reg->TCV_D_CTRL_b.RED_PERIOD   = p_tdma_schedule_entry[index].red_period;
+        p_switch_reg->TCV_D_CTRL_b.INC_CTR1     = p_tdma_schedule_entry[index].inc_crt1;
+        p_switch_reg->TCV_D_CTRL_b.INC_CTR0     = p_tdma_schedule_entry[index].inc_crt0;
+    }
+
+    p_switch_reg->TDMA_TCV_START      = 0;
+    p_switch_reg->TCV_SEQ_LAST_b.LAST = (uint32_t) (tdma_schedule_entry_count - 1) &
+                                        (R_ETHSW_TCV_SEQ_LAST_LAST_Msk >> R_ETHSW_TCV_SEQ_LAST_LAST_Pos);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_TdmaScheduleSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the operation mode for the specified TDMA_GPIO number.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TdmaGpioModeSet (ether_switch_ctrl_t * const p_ctrl,
+                                   uint8_t                     gpio_num,
+                                   ethsw_tdma_gpio_mode_t      gpio_mode)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+    uint32_t                tdma_gpio_mode;
+
+#define ETHSW_TDMA_GPIO_MODE_MASK     (0x3U)
+#define ETHSW_TDMA_GPIO_MODE_SHIFT    (2U)
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_GPIO_COUNT > gpio_num), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    tdma_gpio_mode  = p_switch_reg->TDMA_GPIO_b.GPIO_MODE;
+    tdma_gpio_mode &= ~(ETHSW_TDMA_GPIO_MODE_MASK << (gpio_num * ETHSW_TDMA_GPIO_MODE_SHIFT));
+    tdma_gpio_mode |= (uint32_t) gpio_mode << (gpio_num * ETHSW_TDMA_GPIO_MODE_SHIFT);
+
+    p_switch_reg->TDMA_GPIO_b.GPIO_MODE = tdma_gpio_mode &
+                                          (R_ETHSW_TDMA_GPIO_GPIO_MODE_Msk >> R_ETHSW_TDMA_GPIO_GPIO_MODE_Pos);
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_TdmaGpioModeSet() */
+
+/********************************************************************************************************************//**
+ * Sets TDMA counter 0
+ * The Counter 0 is 32-bit counter that is incremented when the TCV field INC_CTR0 is set to 1.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_TdmaCounter0Set (ether_switch_ctrl_t * const p_ctrl, uint32_t tdma_counter0)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->TDMA_CTR0 = tdma_counter0;
+
+    return err;
+}                                      /* End of function R_ETHSW_TdmaCounter0Set() */
+
+/********************************************************************************************************************//**
+ * Gets TDMA counter 0
+ * The Counter 0 is 32-bit counter that is incremented when the TCV field INC_CTR0 is set to 1.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_TdmaCounter0Get (ether_switch_ctrl_t * const p_ctrl, uint32_t * p_tdma_counter0)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_tdma_counter0), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    *p_tdma_counter0 = p_reg_switch->TDMA_CTR0;
+
+    return err;
+}                                      /* End of function R_ETHSW_TdmaCounter0Get() */
+
+/********************************************************************************************************************//**
+ * Sets TDMA counter 1
+ * The counter 1 is an 8-bit counter that is incremented when the TCV field INC_CTR1 is set to 1.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_TdmaCounter1Set (ether_switch_ctrl_t * const p_ctrl, ethsw_tdma_counter1_t * p_tdma_counter1)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+    uint32_t                counter1;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_tdma_counter1), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    counter1 = 0;
+
+    if (true == p_tdma_counter1->write_value)
+    {
+        counter1  = (uint32_t) (p_tdma_counter1->value << R_ETHSW_TDMA_CTR1_VALUE_Pos) & R_ETHSW_TDMA_CTR1_VALUE_Msk;
+        counter1 |= (uint32_t) ((uint32_t) (p_tdma_counter1->write_value << R_ETHSW_TDMA_CTR1_WRITE_ENA_Pos) &
+                                R_ETHSW_TDMA_CTR1_WRITE_ENA_Msk);
+    }
+
+    counter1 |=
+        (uint32_t) ((uint32_t) (p_tdma_counter1->max_value << R_ETHSW_TDMA_CTR1_MAX_Pos) & R_ETHSW_TDMA_CTR1_MAX_Msk);
+    counter1 |= (uint32_t) ((uint32_t) (p_tdma_counter1->int_value << R_ETHSW_TDMA_CTR1_INT_VALUE_Pos) &
+                            R_ETHSW_TDMA_CTR1_INT_VALUE_Msk);
+
+    p_reg_switch->TDMA_CTR1 = counter1;
+
+    p_reg_switch->TDMA_IRQ_CONTROL_b.CTR1_INT_EN = p_tdma_counter1->int_enable;
+
+    return err;
+}                                      /* End of function R_ETHSW_TdmaCounter1Set() */
+
+/********************************************************************************************************************//**
+ * Gets TDMA counter 1
+ * The counter 1 is an 8-bit counter that is incremented when the TCV field INC_CTR1 is set to 1.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_TdmaCounter1Get (ether_switch_ctrl_t * const p_ctrl, ethsw_tdma_counter1_t * p_tdma_counter1)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_tdma_counter1), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_tdma_counter1->value      = p_reg_switch->TDMA_CTR1_b.VALUE;
+    p_tdma_counter1->max_value  = p_reg_switch->TDMA_CTR1_b.MAX;
+    p_tdma_counter1->int_value  = p_reg_switch->TDMA_CTR1_b.INT_VALUE;
+    p_tdma_counter1->int_enable = (bool) p_reg_switch->TDMA_IRQ_CONTROL_b.CTR1_INT_EN;
+
+    return err;
+}                                      /* End of function R_ETHSW_TdmaCounter1Get() */
+
+/*******************************************************************************************************************//**
+ * Clear the TDMA hold request
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TdmaHoldReqClear (ether_switch_ctrl_t * const p_ctrl)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    p_reg_switch->TDMA_CONFIG_b.HOLD_REQ_CLR = 1;
+
+    return err;
+}                                      /* End of function R_ETHSW_TdmaHoldReqClear() */
+
+/*******************************************************************************************************************//**
+ * Enables or disables the timer with the specified timer number.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimeEnableSet (ether_switch_ctrl_t * const p_ctrl, ethsw_time_enable_t * p_time_enable)
+{
+    volatile uint32_t * p_atime_ctrl;  /* time control for time */
+    volatile uint32_t * p_atime_inc;   /* Clock period of the timestamping clock */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_time_enable), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((ETHSW_TIME_COUNT > p_time_enable->time_num), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* Pointer ATIME_CTRL[n] register */
+    p_atime_ctrl = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->ATIME_CTRL0 +
+                                          (ETHSW_PORT_OFFSET_32BYTES * p_time_enable->time_num));
+
+    /* Pointer ATIME_INC[n] register */
+    p_atime_inc = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->ATIME_INC0 +
+                                         (ETHSW_PORT_OFFSET_32BYTES * p_time_enable->time_num));
+
+    if (true == p_time_enable->enable)
+    {
+        /* enable operation */
+        *p_atime_ctrl |= R_ETHSW_ATIME_CTRL1_ENABLE_Msk << R_ETHSW_ATIME_CTRL1_ENABLE_Pos;
+
+        *p_atime_inc &= (uint32_t) (~R_ETHSW_ATIME_INC1_CLK_PERIOD_Msk);
+        *p_atime_inc |= (uint32_t) ((uint32_t) (p_time_enable->clock_period << R_ETHSW_ATIME_INC1_CLK_PERIOD_Pos) &
+                                    R_ETHSW_ATIME_INC1_CLK_PERIOD_Msk);
+    }
+    else
+    {
+        /* disable operation */
+        *p_atime_ctrl &= (uint32_t) ~(R_ETHSW_ATIME_CTRL1_ENABLE_Msk << R_ETHSW_ATIME_CTRL1_ENABLE_Pos);
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enable Tx timestamping for an external port.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimeTransmitTimestampSet (ether_switch_ctrl_t * const p_ctrl, ethsw_time_transmit_t * p_time_transmit)
+{
+    uint32_t reg_config;               /* CONFIG */
+    uint32_t reg_int_config;           /* INT_CONFIG */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_time_transmit), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    reg_config     = p_switch_reg->TSM_CONFIG; /* CONFIG register */
+    reg_int_config = p_switch_reg->INT_CONFIG; /* INT_CONFIG register */
+
+    if (0 != p_time_transmit->port_mask.mask)
+    {
+        /* enable options */
+        reg_config &= (uint32_t) ~R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Msk;
+        reg_config |= (uint32_t) ((uint32_t) (p_time_transmit->port_mask.mask << R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Pos) &
+                                  R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Msk);
+        reg_config |= R_ETHSW_TSM_CONFIG_IRQ_EN_Msk;
+
+        p_switch_reg->TSM_CONFIG = reg_config;
+
+        reg_int_config |= R_ETHSW_INT_CONFIG_IRQ_EN_Msk |
+                          R_ETHSW_INT_CONFIG_TSM_INT_Msk;
+
+        p_switch_reg->INT_CONFIG = reg_int_config;
+
+        gp_ethsw_time_callback = p_time_transmit->p_time_callback;
+    }
+    else
+    {
+        /* disable options */
+        reg_config &= (uint32_t) ~R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Msk;
+
+        p_switch_reg->TSM_CONFIG = reg_config;
+
+        reg_int_config &= (uint32_t) ~R_ETHSW_INT_CONFIG_TSM_INT_Msk;
+
+        p_switch_reg->INT_CONFIG = reg_int_config;
+
+        gp_ethsw_time_callback = 0;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_TimeTransmitTimestampSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the current time value to the timer with the specified timer number.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimeValueSet (ether_switch_ctrl_t * const p_ctrl, ethsw_timestamp_t * p_timestamp)
+{
+    volatile uint32_t * p_atime;       /* nanoseconds time value */
+    volatile uint32_t * p_atime_sec;   /* seconds time value */
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_timestamp), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((ETHSW_TIME_COUNT > p_timestamp->time_num), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* Pointer ATIME[n] register */
+    p_atime = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->ATIME0 +
+                                     (ETHSW_PORT_OFFSET_32BYTES * p_timestamp->time_num));
+
+    /* Pointer ATIME_SEC[n] register */
+    p_atime_sec = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->ATIME_SEC0 +
+                                         (ETHSW_PORT_OFFSET_32BYTES * p_timestamp->time_num));
+
+    *p_atime_sec = p_timestamp->time_sec;
+    *p_atime     = p_timestamp->time_nsec;
+
+    return FSP_SUCCESS;
+}                                      /* End of R_ETHSW_TimeValueSet() */
+
+/*******************************************************************************************************************//**
+ * Gets the current time value to the timer with the specified timer number.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ * @retval  FSP_ERR_TIMEOUT             Timeout error
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimeValueGet (ether_switch_ctrl_t * const p_ctrl, ethsw_timestamp_t * p_timestamp)
+{
+    volatile uint32_t * p_atime_ctrl;  /* time control for time */
+    volatile uint32_t * p_atime;       /* nanoseconds time value */
+    volatile uint32_t * p_atime_sec;   /* seconds time value */
+    uint64_t            timeout;       /* timeout */
+    int32_t             sign_time_nano;
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_timestamp), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((ETHSW_TIME_COUNT > p_timestamp->time_num), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    /* Pointer ATIME_CTRL[n] register */
+    p_atime_ctrl = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->ATIME_CTRL0 +
+                                          (ETHSW_PORT_OFFSET_32BYTES * p_timestamp->time_num));
+
+    /* Pointer ATIME[n] register */
+    p_atime = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->ATIME0 +
+                                     (ETHSW_PORT_OFFSET_32BYTES * p_timestamp->time_num));
+
+    /* Pointer ATIME_SEC[n] register */
+    p_atime_sec = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->ATIME_SEC0 +
+                                         (ETHSW_PORT_OFFSET_32BYTES * p_timestamp->time_num));
+
+    *p_atime_ctrl |= 1 << R_ETHSW_ATIME_CTRL0_CAPTURE_Pos;
+
+    timeout = ETHSW_TIMEOUT_COUNT;
+
+    while (0 != (*p_atime_ctrl & R_ETHSW_ATIME_CTRL0_CAPTURE_Msk))
+    {
+        ETHSW_ERROR_RETURN((0 != timeout), FSP_ERR_TIMEOUT);
+        timeout--;
+    }
+
+    p_timestamp->time_sec = *p_atime_sec;
+    sign_time_nano        = (int32_t) *p_atime;
+
+    if (sign_time_nano < 0)
+    {
+        p_timestamp->time_sec -= 1;
+        sign_time_nano        += NANO_COUNT_FOR_1SEC;
+    }
+    else if (sign_time_nano >= NANO_COUNT_FOR_1SEC)
+    {
+        p_timestamp->time_sec += 1;
+        sign_time_nano        -= NANO_COUNT_FOR_1SEC;
+    }
+    else
+    {
+        ;
+    }
+
+    p_timestamp->time_nsec    = (uint32_t) sign_time_nano;
+    p_timestamp->timestamp_id = 0;
+
+    return FSP_SUCCESS;
+}                                      /* End of R_ETHSW_TimeValueGet() */
+
+/*******************************************************************************************************************//**
+ * Gets the current time value to all timer (timer number 0 and 1).
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_TIMEOUT             Timeout error
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimeValueGetAll (ether_switch_ctrl_t * const p_ctrl,
+                                   ethsw_timestamp_t         * p_timer0,
+                                   ethsw_timestamp_t         * p_timer1)
+{
+    uint64_t timeout;                  /* timeout */
+    uint8_t  corr_inc0;
+    uint8_t  corr_inc1;
+    uint8_t  clk_period0;
+    uint8_t  clk_period1;
+    uint8_t  set_clk_period0 = 0;
+    uint8_t  set_clk_period1 = 0;
+
+    R_ETHSW_Type volatile * p_switch_reg;
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_timer0), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((NULL != p_timer1), FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    corr_inc0   = p_switch_reg->ATIME_INC0_b.CORR_INC;
+    clk_period0 = p_switch_reg->ATIME_INC0_b.CLK_PERIOD;
+
+    if (clk_period0 != corr_inc0)
+    {
+        p_switch_reg->ATIME_INC0_b.CORR_INC = clk_period0 &
+                                              (R_ETHSW_ATIME_INC0_CORR_INC_Msk >> R_ETHSW_ATIME_INC0_CORR_INC_Pos);
+        set_clk_period0 = 1;
+    }
+
+    corr_inc1   = p_switch_reg->ATIME_INC1_b.CORR_INC;
+    clk_period1 = p_switch_reg->ATIME_INC1_b.CLK_PERIOD;
+
+    if (clk_period1 != corr_inc1)
+    {
+        p_switch_reg->ATIME_INC1_b.CORR_INC = clk_period1 &
+                                              (R_ETHSW_ATIME_INC0_CORR_INC_Msk >> R_ETHSW_ATIME_INC0_CORR_INC_Pos);
+        set_clk_period1 = 1;
+    }
+
+    p_switch_reg->ATIME_CTRL0_b.CAPTURE_ALL = 1;
+
+    timeout = ETHSW_TIMEOUT_COUNT;
+
+    while (0 != p_switch_reg->ATIME_CTRL0_b.CAPTURE_ALL)
+    {
+        ETHSW_ERROR_RETURN((0 != timeout), FSP_ERR_TIMEOUT);
+        timeout--;
+    }
+
+    p_timer0->time_sec  = p_switch_reg->ATIME_SEC0;
+    p_timer0->time_nsec = p_switch_reg->ATIME0;
+
+    p_timer1->time_sec  = p_switch_reg->ATIME_SEC1;
+    p_timer1->time_nsec = p_switch_reg->ATIME1;
+
+    p_timer0->timestamp_id = 0;
+    p_timer1->timestamp_id = 0;
+
+    p_timer0->time_num = 0;
+    p_timer1->time_num = 1;
+
+    if (set_clk_period0)
+    {
+        p_switch_reg->ATIME_INC0_b.CORR_INC = corr_inc0 &
+                                              (R_ETHSW_ATIME_INC0_CORR_INC_Msk >> R_ETHSW_ATIME_INC0_CORR_INC_Pos);
+    }
+
+    if (set_clk_period1)
+    {
+        p_switch_reg->ATIME_INC1_b.CORR_INC = corr_inc1 &
+                                              (R_ETHSW_ATIME_INC1_CORR_INC_Msk >> R_ETHSW_ATIME_INC1_CORR_INC_Pos);
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_TimeValueGetAll() */
+
+/*******************************************************************************************************************//**
+ * Sets the peer delay value for the specified timer number of the specified port number.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimePeerDelaySet (ether_switch_ctrl_t * const p_ctrl,
+                                    uint32_t                    port,
+                                    ethsw_time_peerdelay_t    * p_peerdelay)
+{
+    volatile uint32_t * p_peerdelay_reg;
+
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((ETHSW_PORT_COUNT > port), FSP_ERR_INVALID_ARGUMENT);
+
+    ETHSW_ERROR_RETURN((NULL != p_peerdelay), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((ETHSW_TIME_COUNT > p_peerdelay->time_num), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    p_peerdelay_reg = (volatile uint32_t *) ((uint8_t *) &p_switch_reg->PEERDELAY_P0_T0 +
+                                             (ETHSW_PORT_OFFSET_16BYTES * port) +
+                                             (ETHSW_PORT_OFFSET_4BYTES * p_peerdelay->time_num));
+
+    *p_peerdelay_reg = p_peerdelay->peerdelay;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_TimePeerDelaySet() */
+
+/********************************************************************************************************************//**
+ * Sets the offset correction for the specified timer number.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimeOffsetSet (ether_switch_ctrl_t * const p_ctrl, ethsw_time_offset_correction_t * p_offset)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_offset), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN(ETHSW_TIME_COUNT > p_offset->time_num, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    if (0 == p_offset->time_num)       // timer 0
+    {
+        p_reg_switch->ATIME_INC0_b.OFFS_CORR_INC = p_offset->offs_inc &
+                                                   (R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Msk >>
+                                                    R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Pos);
+
+        p_reg_switch->ATIME_OFFS_CORR0 = p_offset->offs_corr;
+
+        p_reg_switch->ATIME_OFFSET0 = p_offset->offset;
+    }
+    else                               // timer 1
+    {
+        p_reg_switch->ATIME_INC1_b.OFFS_CORR_INC = p_offset->offs_inc &
+                                                   (R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Msk >>
+                                                    R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Pos);
+
+        p_reg_switch->ATIME_OFFS_CORR1 = p_offset->offs_corr;
+
+        p_reg_switch->ATIME_OFFSET1 = p_offset->offset;
+    }
+
+    return err;
+}                                      /* End of function R_ETHSW_TimeOffsetSet() */
+
+/********************************************************************************************************************//**
+ * Sets clock rate corection for the specified timer.
+ *
+ * @retval  FSP_SUCCESS                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ ***********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimeRateSet (ether_switch_ctrl_t * const p_ctrl, ethsw_time_rate_correction_t * p_rate)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    fsp_err_t               err             = FSP_SUCCESS;
+    R_ETHSW_Type volatile * p_reg_switch;
+
+    uint32_t clock_period;
+    uint32_t atime_increment;
+    uint32_t atime_correct;
+    uint32_t abs_ppb;
+
+#define TS_CLK              125 * 1000 * 1000 /* 125MHz */
+#define CLOCK_CORRECTION    1                 /* Number of clocks increasing or decreasing */
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_rate), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN(ETHSW_TIME_COUNT > p_rate->time_num, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((+TS_CLK / 10) >= p_rate->rate, FSP_ERR_INVALID_ARGUMENT);
+    ETHSW_ERROR_RETURN((-TS_CLK / 10) <= p_rate->rate, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    if (0 == p_rate->rate)
+    {
+        atime_increment = 0;
+        atime_correct   = 0;
+    }
+    else
+    {
+        if (0 == p_rate->time_num)     // timer 0
+        {
+            clock_period = p_reg_switch->ATIME_INC0_b.CLK_PERIOD;
+        }
+        else                           // timer 1
+        {
+            clock_period = p_reg_switch->ATIME_INC1_b.CLK_PERIOD;
+        }
+
+        if (0 > p_rate->rate)
+        {
+            atime_increment = clock_period - CLOCK_CORRECTION;
+
+            abs_ppb = (uint32_t) (p_rate->rate * -1);
+        }
+        else
+        {
+            atime_increment = clock_period + CLOCK_CORRECTION;
+
+            abs_ppb = (uint32_t) p_rate->rate;
+        }
+
+        atime_correct = (uint32_t) ((TS_CLK * CLOCK_CORRECTION) / abs_ppb) - 1;
+    }
+
+    if (0 == p_rate->time_num)         // timer 0
+    {
+        p_reg_switch->ATIME_INC0_b.CORR_INC = atime_increment &
+                                              (R_ETHSW_ATIME_INC0_CORR_INC_Msk >> R_ETHSW_ATIME_INC0_CORR_INC_Pos);
+
+        p_reg_switch->ATIME_CORR0 = atime_correct;
+    }
+    else                               // timer 1
+    {
+        p_reg_switch->ATIME_INC1_b.CORR_INC = atime_increment &
+                                              (R_ETHSW_ATIME_INC1_CORR_INC_Msk >> R_ETHSW_ATIME_INC1_CORR_INC_Pos);
+
+        p_reg_switch->ATIME_CORR1 = atime_correct;
+    }
+
+    return err;
+}                                      /* End of function R_ETHSW_TimeRateSet() */
+
+/*******************************************************************************************************************//**
+ * Sets the domain number for the specified timer.
+ *
+ * @retval  FSP_SUCCESS                 Command successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER     Pointer to arguments are NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t R_ETHSW_TimeDomainSet (ether_switch_ctrl_t * const p_ctrl, ethsw_time_domain_t * p_domain)
+{
+    ethsw_instance_ctrl_t * p_instance_ctrl = (ethsw_instance_ctrl_t *) p_ctrl;
+    R_ETHSW_Type volatile * p_switch_reg;
+
+#if (ETHSW_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    ETHSW_ERROR_RETURN(ETHSW_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    ETHSW_ERROR_RETURN((NULL != p_domain), FSP_ERR_INVALID_POINTER);
+    ETHSW_ERROR_RETURN((ETHSW_TIME_COUNT > p_domain->time_num), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    if (0 == p_domain->time_num)
+    {
+        p_switch_reg->PTP_DOMAIN_b.DOMAIN0 = p_domain->domain_num;
+    }
+    else
+    {
+        p_switch_reg->PTP_DOMAIN_b.DOMAIN1 = p_domain->domain_num;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_ETHSW_TimeDomainSet() */
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ETHSW)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Interrupt handler for Ethernet switch.
+ * Supports the interrupts for DLR, PHY link change, TSM(Timestamping) and TDMA.
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void ethsw_isr_intr (void)
+{
+    ether_switch_callback_args_t callback_arg;
+    uint32_t          ulInt_Stat_Ack_Val;
+    R_ETHSW_Type    * p_reg_switch;
+    volatile uint32_t dammy_read;
+
+    IRQn_Type               irq             = R_FSP_CurrentIrqGet();
+    ethsw_instance_ctrl_t * p_instance_ctrl =
+        (ethsw_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    p_reg_switch = p_instance_ctrl->p_reg_switch;
+
+    ulInt_Stat_Ack_Val = p_reg_switch->INT_STAT_ACK;
+
+    /* Clear IRQ_LINK Interrupt */
+    p_reg_switch->INT_STAT_ACK = ulInt_Stat_Ack_Val;
+
+    /* Dammy read for Countermeasure when the CPU clock is 400 or 800MHz */
+    dammy_read = p_reg_switch->INT_STAT_ACK;
+    dammy_read = dammy_read;
+
+    /* Callback : Interrupt handler */
+    if ((0 != (ulInt_Stat_Ack_Val & ETHSW_INT_CONFIG_IRQ_LNK_MASK)) &&
+        (ETHSW_PHYLINK_ENABLE == ((ethsw_extend_cfg_t *) p_instance_ctrl->p_switch_cfg->p_extend)->phylink))
+    {
+        callback_arg.channel = p_instance_ctrl->p_switch_cfg->channel;
+
+        callback_arg.status_link  = p_reg_switch->STATUS_P0_b.PHYLINK;
+        callback_arg.status_link |= (uint32_t) (p_reg_switch->STATUS_P1_b.PHYLINK << 1);
+        callback_arg.status_link |= (uint32_t) (p_reg_switch->STATUS_P2_b.PHYLINK << 2);
+
+        callback_arg.event     = ETHER_SWITCH_EVENT_LINK_CHANGE;
+        callback_arg.p_context = p_instance_ctrl->p_switch_cfg->p_context;
+
+        (*p_instance_ctrl->p_switch_cfg->p_callback)((void *) &callback_arg);
+    }
+
+    /* DLR Interrupt */
+    if (ETHSW_INT_CONFIG_DLR_INT == (ulInt_Stat_Ack_Val & ETHSW_INT_CONFIG_DLR_INT))
+    {
+        ethsw_isr_dlr(p_instance_ctrl);
+    }
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+
+    /* EFP Interrupt */
+    if (ETHSW_INT_CONFIG_EFP_INT == (ulInt_Stat_Ack_Val & ETHSW_INT_CONFIG_EFP_INT))
+    {
+        ethsw_isr_efp(p_instance_ctrl);
+    }
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+    /* RX Pattern Matcher Interrupt */
+    if (ETHSW_INT_CONFIG_PATTERN_INT == (ulInt_Stat_Ack_Val & ETHSW_INT_CONFIG_PATTERN_INT))
+    {
+        ethsw_isr_rx_pattern_matcher(p_instance_ctrl);
+    }
+
+    /* TDMA Interrupt */
+    if (ETHSW_INT_CONFIG_TDMA_INT == (ulInt_Stat_Ack_Val & ETHSW_INT_CONFIG_TDMA_INT))
+    {
+        ethsw_isr_tdma(p_instance_ctrl);
+    }
+
+    /* TSM Interrupt */
+    if (ETHSW_INT_CONFIG_TSM_INT == (ulInt_Stat_Ack_Val & ETHSW_INT_CONFIG_TSM_INT))
+    {
+        ethsw_isr_tsm(p_instance_ctrl);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Call the callback function registered for the DLR.
+ *
+ * @param[in]   event           event ID
+ * @param[in]   port            source port of DLR event
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void ethsw_dlr_callback (ethsw_dlr_event_t event, uint32_t port)
+{
+    if (0 != gp_ethsw_dlr_callback)
+    {
+        (*gp_ethsw_dlr_callback)(event, port);
+    }
+}                                      /* End of ethsw_dlr_callback() */
+
+/*******************************************************************************************************************//**
+ * Interrupt handler for DLR
+ * This function is called by ethsw_isr_intr
+ *
+ * @param[in]   p_instance_ctrl     pointer to control structure
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void ethsw_isr_dlr (ethsw_instance_ctrl_t * p_instance_ctrl)
+{
+    R_ETHSW_Type      * p_switch_reg;
+    ethsw_link_status_t link_state = ETHSW_LINK_STATE_DOWN; /* link state */
+    uint32_t            int_ID;                             /* interrupt Flag */
+    uint32_t            reg_val;                            /* register content */
+    int32_t             cnt;                                /* loop counter */
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    while (p_switch_reg->DLR_IRQ_STAT_ACK)
+    {
+        reg_val = p_switch_reg->DLR_IRQ_STAT_ACK;
+        p_switch_reg->DLR_IRQ_STAT_ACK = reg_val;
+
+        /* scan all status bits */
+        for (cnt = 0; cnt < 16; cnt++)
+        {
+            int_ID = reg_val & (1U << cnt);
+
+            if (int_ID == 0)
+            {
+                /* bit wasn't set, check next one */
+                continue;
+            }
+
+            switch (int_ID)
+            {
+                case ETHSW_TGT_DLR_INT_NEWSTATUS:
+                {
+                    ethsw_dlr_callback(ETHSW_DLR_EVENT_NEWSTATE, ETHSW_PORT_MGMT);
+                    break;
+                }
+
+                case ETHSW_TGT_DLR_INT_BEACONTMO_0:
+                {
+                    ethsw_dlr_callback(ETHSW_DLR_EVENT_BEACONTIMEOUT, 0);
+                    break;
+                }
+
+                case ETHSW_TGT_DLR_INT_BEACONTMO_1:
+                {
+                    ethsw_dlr_callback(ETHSW_DLR_EVENT_BEACONTIMEOUT, 1);
+                    break;
+                }
+
+                case ETHSW_TGT_DLR_INT_SUVICHNG:
+                {
+                    ethsw_dlr_callback(ETHSW_DLR_EVENT_NEWSUPERVISOR, 0);
+                    break;
+                }
+
+                case ETHSW_TGT_DLR_INT_LNKCHNG_0:
+                {
+                    R_ETHSW_LinkStateGet((ether_switch_ctrl_t *) p_instance_ctrl, 0, &link_state);
+
+                    if (ETHSW_LINK_STATE_UP == link_state)
+                    {
+                        ethsw_dlr_callback(ETHSW_DLR_EVENT_LINKRESTORED, 0);
+                    }
+                    else
+                    {
+                        ethsw_dlr_callback(ETHSW_DLR_EVENT_LINKLOST, 0);
+                    }
+
+                    break;
+                }
+
+                case ETHSW_TGT_DLR_INT_LNKCHNG_1:
+                {
+                    R_ETHSW_LinkStateGet((ether_switch_ctrl_t *) p_instance_ctrl, 1, &link_state);
+
+                    if (ETHSW_LINK_STATE_UP == link_state)
+                    {
+                        ethsw_dlr_callback(ETHSW_DLR_EVENT_LINKRESTORED, 1);
+                    }
+                    else
+                    {
+                        ethsw_dlr_callback(ETHSW_DLR_EVENT_LINKLOST, 1);
+                    }
+
+                    break;
+                }
+
+                case ETHSW_TGT_DLR_INT_LOCALLOOP_0:
+                {
+                    ethsw_dlr_callback(ETHSW_DLR_EVENT_OWNFRAME, 0);
+                    break;
+                }
+
+                case ETHSW_TGT_DLR_INT_LOCALLOOP_1:
+                {
+                    ethsw_dlr_callback(ETHSW_DLR_EVENT_OWNFRAME, 1);
+                    break;
+                }
+
+                default:
+                {
+                    break;
+                }
+            }
+        }
+    }
+}                                      /* End of ethsw_isr_dlr() */
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+
+/*******************************************************************************************************************//**
+ * Interrupt handler for Extended Frame Parser.
+ * This function is called by ethsw_isr_intr.
+ *
+ * @param[in]   p_instance_ctrl     pointer to control structure
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void ethsw_isr_efp (ethsw_instance_ctrl_t * p_instance_ctrl)
+{
+    R_ETHSW_Type    * p_switch_reg = p_instance_ctrl->p_reg_switch;
+    uint32_t          port;
+    ethsw_efp_event_t id;
+    uint32_t          en_cb = 0;
+
+    if (0 != gp_ethsw_efp_callback)
+    {
+        volatile uint32_t * pn_qgeis        = &p_switch_reg->P0_QGEIS;
+        volatile uint32_t * pn_qseis        = &p_switch_reg->P0_QSEIS;
+        volatile uint32_t * pn_qmeis        = &p_switch_reg->P0_QMEIS;
+        volatile uint32_t * pn_error_status = &p_switch_reg->P0_ERROR_STATUS;
+
+        for (port = 0; port < ETHSW_PORT_COUNT; port++)
+        {
+            /* Check Qci stream gate error interrupt */
+            if ((*pn_qgeis & R_ETHSW_P0_QGEIS_QGMOIS_Msk) != 0)
+            {
+                id        = ETHSW_EFP_INT_SRC_GATE_ERROR_DROP;
+                *pn_qgeis = *pn_qgeis;
+                en_cb     = 1;
+                break;
+            }
+
+            /* Qci stream filter error interrupt */
+            if ((*pn_qseis & R_ETHSW_P0_QSEIS_QSMOIS_Msk) != 0)
+            {
+                id        = ETHSW_EFP_INT_SRC_SDU_OVER_DROP;
+                *pn_qseis = *pn_qseis;
+                en_cb     = 1;
+                break;
+            }
+
+            /* Qci meter error interrupt */
+            if ((*pn_qmeis & R_ETHSW_P0_QMEIS_QRFIS_Msk) != 0)
+            {
+                id        = ETHSW_EFP_INT_SRC_FLOW_METER_DROP;
+                *pn_qmeis = *pn_qmeis;
+                en_cb     = 1;
+                break;
+            }
+
+            /* Frame parser error interrupt */
+            if ((*pn_error_status & 0x1FU) != 0)
+            {
+                id               = ETHSW_EFP_INT_SRC_RUNTIME_ERROR;
+                *pn_error_status = *pn_error_status;
+                en_cb            = 1;
+                break;
+            }
+
+            pn_qgeis        += ETHSW_QGEIS_OFFSET;
+            pn_qseis        += ETHSW_QSEIS_OFFSET;
+            pn_qmeis        += ETHSW_QMEIS_OFFSET;
+            pn_error_status += ETHSW_ERROR_STATUS_OFFSET;
+        }
+
+        if (en_cb == 1)
+        {
+            (*gp_ethsw_efp_callback)(port, id);
+        }
+    }
+}
+
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+/*******************************************************************************************************************//**
+ * Interrupt handler for Rx pattern matcher
+ * This function is called by ethsw_isr_intr
+ *
+ * @param[in]   p_instance_ctrl     pointer to control structure
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void ethsw_isr_rx_pattern_matcher (ethsw_instance_ctrl_t * p_instance_ctrl)
+{
+    R_ETHSW_Type                * p_switch_reg = p_instance_ctrl->p_reg_switch;
+    ethsw_rx_pattern_event_data_t event_data;
+    uint32_t pattern_irq_stat_ack;
+
+    pattern_irq_stat_ack = p_switch_reg->PATTERN_IRQ_STAT_ACK;
+
+    p_switch_reg->PATTERN_IRQ_STAT_ACK = pattern_irq_stat_ack;
+
+    if (0 != gp_ethsw_rx_pattern_callback)
+    {
+        event_data.match_int = (pattern_irq_stat_ack & R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Msk) >>
+                               R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Pos;
+        event_data.error_int = (pattern_irq_stat_ack & R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Msk) >>
+                               R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Pos;
+
+        (*gp_ethsw_rx_pattern_callback)(ETHSW_RX_PATTERN_MATCHER, &event_data);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt handler for TDMA.
+ * This function is called by ethsw_isr_intr.
+ *
+ * @param[in]   p_instance_ctrl     pointer to control structure
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void ethsw_isr_tdma (ethsw_instance_ctrl_t * p_instance_ctrl)
+{
+    ethsw_tdma_callback_data_t callback_data;
+    R_ETHSW_Type             * p_switch_reg;
+    uint32_t tdma_irq_stat_ack;
+
+    p_switch_reg                    = p_instance_ctrl->p_reg_switch;
+    tdma_irq_stat_ack               = p_switch_reg->TDMA_IRQ_STAT_ACK;
+    p_switch_reg->TDMA_IRQ_STAT_ACK = tdma_irq_stat_ack;
+
+    if (0 != gp_ethsw_tdma_callback)
+    {
+        if (0 != (tdma_irq_stat_ack & R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Msk))
+        {
+            callback_data.tcv_s_idx = p_switch_reg->TCV_SEQ_LAST_b.ACTIVE;
+
+            (*gp_ethsw_tdma_callback)(ETHSW_TDMA_CALLBACK_TCV_INT, &callback_data);
+        }
+
+        if (0 != (tdma_irq_stat_ack & R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Msk))
+        {
+            callback_data.tcv_s_idx = 0;
+
+            (*gp_ethsw_tdma_callback)(ETHSW_TDMA_CALLBACK_COUNTER1_INT, &callback_data);
+        }
+    }
+}                                      /* End of ethsw_isr_tdma() */
+
+/*******************************************************************************************************************//**
+ * Interrupt handler for TSM(Timestamping)
+ *
+ * @param[in]   p_instance_ctrl     pointer to control structure
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void ethsw_isr_tsm (ethsw_instance_ctrl_t * p_instance_ctrl)
+{
+    ethsw_timestamp_t timestamp;
+    uint32_t          port;
+    uint32_t          irq_tx_en;
+    uint32_t          port_bit;
+    uint32_t          irq_stat_ack;
+    R_ETHSW_Type    * p_switch_reg;
+    uint32_t          ts_fifo_read_ctrl;
+    int32_t           sign_time_nano;
+
+    p_switch_reg = p_instance_ctrl->p_reg_switch;
+
+    irq_stat_ack = p_switch_reg->TSM_IRQ_STAT_ACK;
+    p_switch_reg->TSM_IRQ_STAT_ACK = irq_stat_ack;
+
+    irq_tx_en = (irq_stat_ack & R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Msk) >> R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Pos;
+    for (port = 0; irq_tx_en; port++)
+    {
+        port_bit = 1U << port;
+        if (irq_tx_en & port_bit)
+        {
+            irq_tx_en &= (~port_bit);
+
+            while (1)
+            {
+                ts_fifo_read_ctrl = (port << R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Pos) &
+                                    R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Msk;
+                p_switch_reg->TS_FIFO_READ_CTRL = ts_fifo_read_ctrl;
+
+                ts_fifo_read_ctrl = p_switch_reg->TS_FIFO_READ_CTRL;
+
+                if (0 == (ts_fifo_read_ctrl & R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Msk))
+                {
+                    break;
+                }
+
+                timestamp.time_num = (uint8_t) ((ts_fifo_read_ctrl & R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Msk) >>
+                                                R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Pos);
+
+                timestamp.timestamp_id = ((ts_fifo_read_ctrl & R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Msk) >>
+                                          R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Pos);
+
+                sign_time_nano = (int32_t) p_switch_reg->TS_FIFO_READ_TIMESTAMP;
+
+                if (sign_time_nano < 0)
+                {
+                    sign_time_nano += NANO_COUNT_FOR_1SEC;
+                }
+                else if (sign_time_nano >= NANO_COUNT_FOR_1SEC)
+                {
+                    sign_time_nano -= NANO_COUNT_FOR_1SEC;
+                }
+                else
+                {
+                    ;
+                }
+
+                timestamp.time_nsec = (uint32_t) sign_time_nano;
+
+                if (gp_ethsw_time_callback)
+                {
+                    (*gp_ethsw_time_callback)(ETHSW_TIME_CALLBACK_TIMESTAMP, (uint8_t) port, &timestamp);
+                }
+            }
+        }
+    }
+}                                      /* End of ethsw_isr_tsm() */
+
+/*******************************************************************************************************************//**
+ * Enable ICU for Ether Switcht
+ *
+ * @param[in]   p_instance_ctrl     pointer to control structure
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void ethsw_enable_icu (ethsw_instance_ctrl_t * const p_instance_ctrl)
+{
+    /** Configure the Ethernet Switch interrupt. */
+    R_BSP_IrqCfgEnable(p_instance_ctrl->p_switch_cfg->irq, p_instance_ctrl->p_switch_cfg->ipl, p_instance_ctrl);
+}                                      /* End of function ethsw_enable_icu() */
+
+/*******************************************************************************************************************//**
+ * Disable ICU for Ether Switcht
+ *
+ * @param[in]   p_instance_ctrl     pointer to control structure
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void ethsw_disable_icu (ethsw_instance_ctrl_t * const p_instance_ctrl)
+{
+    /* Get IRQ number for A5PSW_Int interrupt. */
+    R_BSP_IrqDisable(p_instance_ctrl->p_switch_cfg->irq);
+    R_FSP_IsrContextSet(p_instance_ctrl->p_switch_cfg->irq, NULL);
+}                                      /* End of function ether_disable_icu() */
+
+#ifdef  ETHSW_EFP_FEATURE_SUPPORTED
+
+/*******************************************************************************************************************//**
+ * Create the CRC value and set it in buffer
+ * The CRC value and source bit stream is string consisting of '1' or '0'.
+ *
+ * @param[in]     bit_str      Pointer to Source bit stream
+ * @param[in]     len          Length  of Source bit stream
+ * @param[in]     crc_buf      Pointer to CRC set buffer
+ *
+ * @retval        none
+ **********************************************************************************************************************/
+static void r_ethsw_make_crc (char * bit_str, uint32_t len, char * crc_buf)
+{
+    char     crc[7];
+    uint32_t i;
+    char     do_inv;
+
+    for (i = 0; i < 7; ++i)
+    {
+        crc[i] = 1;
+    }
+
+    for (i = 0; i < len; ++i)
+    {
+        do_inv = (char) (('1' == bit_str[i]) ^ crc[6]);
+
+        crc[6] = crc[5] ^ do_inv;
+        crc[5] = crc[4] ^ do_inv;
+        crc[4] = crc[3];
+        crc[3] = crc[2];
+        crc[2] = crc[1] ^ do_inv;
+        crc[1] = crc[0];
+        crc[0] = do_inv;
+    }
+
+    for (i = 0; i < 7; ++i)
+    {
+        crc_buf[6 - i] = crc[i] ? '1' : '0';
+    }
+
+    crc_buf[7] = 0;
+}
+
+/*******************************************************************************************************************//**
+ * Calculate the hash (CRC-7)
+ *
+ * @param[in]   dmaci      DMAC of incoming frame
+ * @param[in]   vidi       VID  of incoming frame
+ *
+ * @retval      calculated hash
+ **********************************************************************************************************************/
+static uint8_t r_ethsw_calc_hash (ethsw_mac_addr_t * dmaci, ethsw_vlan_vid_t * vidi)
+{
+    uint8_t  c_mes_bit[ETHSW_EFP_ASI_HASH_SZ];
+    char     c_crc[8];
+    uint8_t  c_veri_mes_bit[ETHSW_EFP_ASI_HASH_SZ + ETHSW_EFP_ASI_ADDR_SZ];
+    uint16_t test_vid = (uint16_t) (((*vidi)[0] << 8) + ((*vidi)[1])) & ETHSW_EFP_ASI_HASH_VID_MASK;
+    uint8_t  hash     = 0;
+ #ifdef HASH_CULC_DEBUG
+    char    vc_crc[8];
+    uint8_t hash_key = 0;
+ #endif
+
+    /* dmaci */
+    for (uint8_t i = 0; i < ETHSW_EFP_ASI_HASH_DA_SZ / 8; i++)
+    {
+        for (uint8_t j = 0; j < 8; j++)
+        {
+            c_mes_bit[(i * 8) + j] = (uint8_t) ((((*dmaci)[i] >> (7 - j)) & 0x01) + '0');
+        }
+    }
+
+    /* vidi */
+    for (uint8_t i = 0; i < ETHSW_EFP_ASI_HASH_VID_SZ; i++)
+    {
+        c_mes_bit[ETHSW_EFP_ASI_HASH_DA_SZ +
+                  (i)] = (uint8_t) (((test_vid >> (ETHSW_EFP_ASI_HASH_VID_SZ - 1 - i)) & 0x0001) + '0');
+    }
+
+    /* padding */
+    for (uint8_t i = ETHSW_EFP_ASI_HASH_DA_SZ + ETHSW_EFP_ASI_HASH_VID_SZ; i < ETHSW_EFP_ASI_HASH_SZ; i++)
+    {
+        c_mes_bit[i] = '0';
+    }
+
+    /* calculate crc value */
+    r_ethsw_make_crc((char *) c_mes_bit, ETHSW_EFP_ASI_HASH_SZ, c_crc);
+
+    /* verify crc value */
+    memcpy(c_veri_mes_bit, c_mes_bit, ETHSW_EFP_ASI_HASH_SZ);
+    memcpy(&c_veri_mes_bit[ETHSW_EFP_ASI_HASH_SZ], c_crc, ETHSW_EFP_ASI_ADDR_SZ);
+ #ifdef HASH_CULC_DEBUG
+    r_ethsw_make_crc((char *) c_veri_mes_bit, (ETHSW_EFP_ASI_HASH_SZ + ETHSW_EFP_ASI_ADDR_SZ), vc_crc);
+    for (uint8_t i = 0; i < ETHSW_EFP_ASI_ADDR_SZ; i++)
+    {
+        if (vc_crc[i] == '1')
+        {
+            hash_key |= (uint8_t) (1U << (ETHSW_EFP_ASI_ADDR_SZ - 1 - i));
+        }
+    }
+    app_printf("entry [dmaci] %02X %02X %02X %02X %02X %02X [vidi] %02X %02X\n",
+               (*dmaci)[0],
+               (*dmaci)[1],
+               (*dmaci)[2],
+               (*dmaci)[3],
+               (*dmaci)[4],
+               (*dmaci)[5],
+               (*vidi)[0],
+               (*vidi)[1]);
+ #endif
+
+    /* convert to hash key in binary */
+    for (uint8_t i = 0; i < ETHSW_EFP_ASI_ADDR_SZ; i++)
+    {
+        if (c_crc[i] == '1')
+        {
+            hash |= (uint8_t) (1U << (ETHSW_EFP_ASI_ADDR_SZ - 1 - i));
+        }
+    }
+
+ #ifdef HASH_CULC_DEBUG
+    app_printf("hash = 0x%02X, verified crc = 0x%02X\n", hash, hash_key);
+ #endif
+
+    return hash;
+}
+
+#endif                                 /* ETHSW_EFP_FEATURE_SUPPORTED */
+
+/*******************************************************************************************************************//**
+ * Unlock write access protection for Ethernet subsystem registers
+ *
+ * @param[in]   p_reg_base      Base address of Ethernet subsystem registers
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void r_ethsw_reg_protection_disable (void * const p_reg_base)
+{
+    /* Key code for PRCMD register */
+#define ETHSW_PRCMD_UNLOCK1    (0x000000A5U)
+#define ETHSW_PRCMD_UNLOCK2    (0x00000001U)
+#define ETHSW_PRCMD_UNLOCK3    (0x0000FFFEU)
+#define ETHSW_PRCMD_UNLOCK4    (0x00000001U)
+
+    R_ETHSS_Type * p_reg_ethss = (R_ETHSS_Type *) p_reg_base;
+
+    /* Unlock the protection of ethernet subsystem register */
+    p_reg_ethss->PRCMD = ETHSW_PRCMD_UNLOCK1;
+    p_reg_ethss->PRCMD = ETHSW_PRCMD_UNLOCK2;
+    p_reg_ethss->PRCMD = ETHSW_PRCMD_UNLOCK3;
+    p_reg_ethss->PRCMD = ETHSW_PRCMD_UNLOCK4;
+}                                      /* End of function r_ethsw_reg_protection_disable() */
+
+/*******************************************************************************************************************//**
+ * Lock write access protection for Ethernet subsystem registers
+ *
+ * @param[in]   p_reg_base      Base address of Ethernet subsystem registers
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void r_ethsw_reg_protection_enable (void * const p_reg_base)
+{
+    /* Key code for PRCMD register */
+#define ETHSW_PRCMD_LOCK    (0x00000000U)
+
+    R_ETHSS_Type * p_reg_ethss = (R_ETHSS_Type *) p_reg_base;
+
+    /* Lock the protection of ethernet access register */
+    p_reg_ethss->PRCMD = ETHSW_PRCMD_LOCK;
+}                                      /* End of function r_ethsw_reg_protection_enable() */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_gmac/r_gmac.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_gmac/r_gmac.c
new file mode 100644
index 00000000..ff7e7422
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_gmac/r_gmac.c
@@ -0,0 +1,2423 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+
+#include <string.h>
+
+#include "bsp_api.h"
+#include "r_gmac.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ ***********************************************************************************************************************/
+
+#ifndef GMAC_ERROR_RETURN
+
+/*LDRA_INSPECTED 77 S This macro does not work when surrounded by parentheses. */
+ #define GMAC_ERROR_RETURN(a, err)    FSP_ERROR_RETURN((a), (err))
+#endif
+
+#define GMAC_ETHERC_REG_SIZE                           (0x400UL)
+#define GMAC_ETHERC_EDMAC_REG_SIZE                     (0x100UL)
+
+#define GMAC_ETHERC_INITIALIZATION_WAIT_CYCLE          (0x64UL)
+
+/** "ETHE" in ASCII.  Used to determine if the control block is open. */
+#define GMAC_OPEN                                      (0x45544845U)
+
+/* Definition of the maximum of data that can be sent at one time in the Ethernet */
+#define GMAC_MINIMUM_FRAME_SIZE                        (60U) /* Minimum number of transmitted data */
+
+/* The number of byte for FCS in ethernet frame */
+#define GMAC_FCS_SIZE                                  (4U)
+
+/* Bit definitions of control/status member of Transmit Descriptor-0 */
+#define GMAC_TDES0_OWN                                 (1UL << 31)      /* Own Bit */
+#define GMAC_TDES0_IC                                  (1UL << 30)      /* Interrupt on Completion */
+#define GMAC_TDES0_LS                                  (1UL << 29)      /* Last Segment */
+#define GMAC_TDES0_FS                                  (1UL << 28)      /* First Segment */
+#define GMAC_TDES0_DC                                  (1UL << 27)      /* Disable CRC */
+#define GMAC_TDES0_DP                                  (1UL << 26)      /* Disable Pad */
+#define GMAC_TDES0_TTSE                                (1UL << 25)      /* Transmit Timestamp Enable */
+#define GMAC_TDES0_CIC_MASK                            (3UL << 22)      /* Checksum Insertion Control */
+#define GMAC_TDES0_TER                                 (1UL << 21)      /* Transmit End of Ring */
+#define GMAC_TDES0_TCH                                 (1UL << 20)      /* Second Address Chained */
+#define GMAC_TDES0_TTSS                                (1UL << 17)      /* Transmit Timestamp Status */
+#define GMAC_TDES0_IHE                                 (1UL << 16)      /* IP Header Error */
+#define GMAC_TDES0_ES                                  (1UL << 15)      /* Error Summary */
+#define GMAC_TDES0_JT                                  (1UL << 14)      /* Jabber Timeout */
+#define GMAC_TDES0_FF                                  (1UL << 13)      /* Frame Flushed */
+#define GMAC_TDES0_IPE                                 (1UL << 12)      /* IP Payload Error */
+#define GMAC_TDES0_LOC                                 (1UL << 11)      /* Loss of Carrier */
+#define GMAC_TDES0_NC                                  (1UL << 10)      /* No Carrier */
+#define GMAC_TDES0_LC                                  (1UL << 9)       /* Late Collision */
+#define GMAC_TDES0_EC                                  (1UL << 8)       /* Excessive Collision */
+#define GMAC_TDES0_VF                                  (1UL << 7)       /* VLAN Frame */
+#define GMAC_TDES0_CC_MASK                             (0xfUL << 3)     /* Collision Count (Status field) */
+#define GMAC_TDES0_ED                                  (1UL << 2)       /* Excessive Deferral */
+#define GMAC_TDES0_UF                                  (1UL << 1)       /* Underflow Error */
+#define GMAC_TDES0_DB                                  (1UL << 0)       /* Deferred Bit */
+
+/* Bit definitions of control/status member of Transmit Descriptor-1 */
+#define GMAC_RDES1_TBS2_MASK                           (0x1fffUL << 16) /* Receive Buffer 2 Size - Mask */
+#define GMAC_RDES1_TBS2_SHFIT                          16               /* Receive Buffer 2 Size - Shift */
+#define GMAC_RDES1_TBS1_MASK                           (0x1fffUL << 0)  /* Receive Buffer 1 Size -  */
+#define GMAC_RDES1_TBS1_SHFIT                          0                /* Receive Buffer 1 Size */
+
+/* Bit definitions of control/status member of Receive Descriptor-0 */
+#define GMAC_RDES0_OWN                                 (1UL << 31)      /* Own Bit */
+#define GMAC_RDES0_AFM                                 (1UL << 30)      /* Destination Address Filter Fail */
+#define GMAC_RDES0_FL_MASK                             (0x3fffUL << 16) /* Frame Length - Mask */
+#define GMAC_RDES0_FL_SHIFT                            16               /* Frame Length - Shift */
+#define GMAC_RDES0_ES                                  (1UL << 15)      /* Error Summary */
+#define GMAC_RDES0_DE                                  (1UL << 14)      /* Descriptor Error */
+#define GMAC_RDES0_SAF                                 (1UL << 13)      /* Source Address Filter Fail */
+#define GMAC_RDES0_LE                                  (1UL << 12)      /* Length Error */
+#define GMAC_RDES0_VLAN                                (1UL << 10)      /* VLAN Tag */
+#define GMAC_RDES0_FS                                  (1UL << 9)       /* First Descriptor */
+#define GMAC_RDES0_LS                                  (1UL << 8)       /* Last Descriptor */
+#define GMAC_RDES0_TAGF                                (1UL << 7)       /* Timestamp Available or Giant Frame */
+#define GMAC_RDES0_LC                                  (1UL << 6)       /* Late Collision */
+#define GMAC_RDES0_FT                                  (1UL << 5)       /* Frame Type */
+#define GMAC_RDES0_RWT                                 (1UL << 4)       /* Receive Watchdog Timeout */
+#define GMAC_RDES0_RE                                  (1UL << 3)       /* Receive Error */
+#define GMAC_RDES0_DBE                                 (1UL << 2)       /* Dribble Bit Error */
+#define GMAC_RDES0_CE                                  (1UL << 1)       /* CRC Error */
+#define GMAC_RDES0_ESA                                 (1UL << 0)       /* Extended Status Available */
+
+/* Bit definitions of control/status member of Receive Descriptor-1 */
+#define GMAC_RDES1_DIC                                 (1UL << 31)      /* Disable Interrupt on Completion */
+#define GMAC_RDES1_RBS2_MASK                           (0x1fffUL << 16) /* Receive Buffer 2 Size - Mask */
+#define GMAC_RDES1_RBS2_SHFIT                          16               /* Receive Buffer 2 Size - Shift */
+#define GMAC_RDES1_RER                                 (1UL << 15)      /* Receive End of Ring */
+#define GMAC_RDES1_RCH                                 (1UL << 14)      /* Second Address Chained */
+#define GMAC_RDES1_RBS1_MASK                           (0x1fffUL << 0)  /* Receive Buffer 1 Size -  */
+#define GMAC_RDES1_RBS1_SHFIT                          0                /* Receive Buffer 1 Size */
+
+/* Bit definition of Interrupt Enable Register */
+#define GMAC_INTERRUPT_ENABLE_NIE                      (1UL << 16)      /* Normal Interrupt Summary Enable */
+#define GMAC_INTERRUPT_ENABLE_AIE                      (1UL << 15)      /* Abnormal Interrupt Summary Enable */
+#define GMAC_INTERRUPT_ENABLE_ERE                      (1UL << 14)      /* Early Receive Interrupt Enable */
+#define GMAC_INTERRUPT_ENABLE_FBE                      (1UL << 13)      /* Fatal Bus Error Enable */
+#define GMAC_INTERRUPT_ENABLE_ETE                      (1UL << 10)      /* Early Transmit Interrupt Enable */
+#define GMAC_INTERRUPT_ENABLE_RWE                      (1UL << 9)       /* Receive Watchdog Timeout Enable */
+#define GMAC_INTERRUPT_ENABLE_RSE                      (1UL << 8)       /* Receive Stopped Enable */
+#define GMAC_INTERRUPT_ENABLE_RUE                      (1UL << 7)       /* Receive Buffer Unavailable Enable */
+#define GMAC_INTERRUPT_ENABLE_RIE                      (1UL << 6)       /* Receive Interrupt Enable */
+#define GMAC_INTERRUPT_ENABLE_UNE                      (1UL << 5)       /* Underflow Interrupt Enable */
+#define GMAC_INTERRUPT_ENABLE_OVE                      (1UL << 4)       /* Overflow Interrupt Enable */
+#define GMAC_INTERRUPT_ENABLE_TJE                      (1UL << 3)       /* Transmit Jabber Timeout Enable */
+#define GMAC_INTERRUPT_ENABLE_TUE                      (1UL << 2)       /* Transmit Buffer Unavailable Enable */
+#define GMAC_INTERRUPT_ENABLE_TSE                      (1UL << 1)       /* Transmit Stopped Enable */
+#define GMAC_INTERRUPT_ENABLE_TIE                      (1UL << 0)       /* Transmit Interrupt Enable */
+
+/* Bit definition of MAC Frame Filter Register */
+#define GMAC_MAC_FRAME_FILTER_RA                       (1UL << 31)      /* Receive All */
+#define GMAC_MAC_FRAME_FILTER_VTFE                     (1UL << 16)      /* VLAN Tag Filter Enable */
+#define GMAC_MAC_FRAME_FILTER_HPF                      (1UL << 10)      /* Hash or Perfect Filter */
+#define GMAC_MAC_FRAME_FILTER_SAF                      (1UL << 9)       /* Source Address Filter Enable */
+#define GMAC_MAC_FRAME_FILTER_SAIF                     (1UL << 8)       /* SA Inverse Filtering */
+#define GMAC_MAC_FRAME_FILTER_PCF_1                    (1UL << 7)       /* Pass Control Frames 1 */
+#define GMAC_MAC_FRAME_FILTER_PCF_0                    (1UL << 6)       /* Pass Control Frames 0 */
+#define GMAC_MAC_FRAME_FILTER_DBF                      (1UL << 5)       /* Disable Broadcast Frames */
+#define GMAC_MAC_FRAME_FILTER_PM                       (1UL << 4)       /* Pass All Multicast */
+#define GMAC_MAC_FRAME_FILTER_DAIF                     (1UL << 3)       /* DA Inverse Filtering */
+#define GMAC_MAC_FRAME_FILTER_HMC                      (1UL << 2)       /* Hash Multicast */
+#define GMAC_MAC_FRAME_FILTER_HUC                      (1UL << 1)       /* Hash Unicast */
+#define GMAC_MAC_FRAME_FILTER_PR                       (1UL << 0)       /* Promiscuous Mode */
+
+/* Bit definition of Flow Control Register */
+#define GMAC_FLOW_CONTROL_PT_VALUE                     (0x0000FFFFUL)
+#define GMAC_FLOW_CONTROL_PLT_VALUE                    (0x00000002UL)
+
+#define GMAC_FLOW_CONTROL_PT                           (GMAC_FLOW_CONTROL_PT_VALUE << 16) /* Pause Time (b31-b16) */
+#define GMAC_FLOW_CONTROL_DZPQ                         (1UL << 7)                         /* Disable Zero-Quanta Pause */
+#define GMAC_FLOW_CONTROL_PLT                          (GMAC_FLOW_CONTROL_PLT_VALUE << 4) /* Pause Low Threshold */
+#define GMAC_FLOW_CONTROL_UP                           (1UL << 3)                         /* Unicast Pause Frame Detect */
+#define GMAC_FLOW_CONTROL_RFE                          (1UL << 2)                         /* Receive Flow Control Enable */
+#define GMAC_FLOW_CONTROL_TFE                          (1UL << 1)                         /* Transmit Flow Control Enable */
+#define GMAC_FLOW_CONTROL_FCA_BPA                      (1UL << 0)                         /* Flow Control Busy or Backpressure Activate */
+
+/* Bit definition of Flow Control Register */
+#define GMAC_PMT_CONTROL_STATUS_RWKFILTRST             (1UL << 31)                        /* Wake-Up Frame Filter Register Pointer Reset */
+#define GMAC_PMT_CONTROL_STATUS_GLBLUCAST              (1UL << 9)                         /* Global Unicas */
+#define GMAC_PMT_CONTROL_STATUS_RWKPRCVD               (1UL << 6)                         /* Wake-Up Frame Received */
+#define GMAC_PMT_CONTROL_STATUS_MGKPRCVD               (1UL << 5)                         /* Magic Packet Received */
+#define GMAC_PMT_CONTROL_STATUS_RWKPKTEN               (1UL << 2)                         /* Wake-Up Frame Enable */
+#define GMAC_PMT_CONTROL_STATUS_MGKPKTEN               (1UL << 1)                         /* Magic Packet Enable */
+#define GMAC_PMT_CONTROL_STATUS_PWRDWN                 (1UL << 0)                         /* Power Down */
+
+/* Bit definition of MMC_Receive_Interrupt_Mask/MMC_Transmit_Interrupt_Mask Register */
+#define GMAC_MMC_RECEIVE_INTERRUPT_MASK_ALL_BIT        0x03FFFFFF
+#define GMAC_MMC_TRANSMIT_INTERRUPT_MASK_ALL_BIT       0x03FFFFFF
+
+/* Number of entries in PAUSE resolution table */
+#define GMAC_PAUSE_TABLE_ENTRIES                       (8)
+
+/* Local device and link partner PAUSE settings */
+#define GMAC_PAUSE_XMIT_OFF                            (0)     /* The pause frame transmission is prohibited. */
+#define GMAC_PAUSE_RECV_OFF                            (0)     /* The pause frame reception is prohibited.    */
+#define GMAC_PAUSE_XMIT_ON                             (1)     /* The pause frame transmission is permitted.  */
+#define GMAC_PAUSE_RECV_ON                             (1)     /* The pause frame reception is permitted.     */
+
+/* Macro definition for buffer alignment adjustment */
+#define GMAC_BUFFER_4BYTE_ALIGNMENT_MASK               (0x3UL) /* Mask for checking whether or not 4-byte alignment. */
+
+/* PAUSE link mask and shift values */
+
+/*
+ * The mask value and shift value which are for that shift the bits form a line and
+ * for comparing the bit information of PAUSE function which support the local device and
+ * Link partner with the assorted table(pause_resolution) which enable or disable the PAUSE frame.
+ */
+#define GMAC_LINK_RESOLUTION_ABILITY_MASK              (3)
+#define GMAC_LINK_RESOLUTION_LOCAL_ABILITY_BITSHIFT    (2)
+
+/* Etherc mode */
+#define GMAC_NO_USE_MAGIC_PACKET_DETECT                (0)
+#define GMAC_USE_MAGIC_PACKET_DETECT                   (1)
+
+/* GMAC_NO_DATA is the return value that indicates that no received data. */
+#define GMAC_NO_DATA                                   (0)
+
+#define GMAC_8BIT_MASK                                 (0xff)
+
+/* Define for TCM */
+#define TCM_CPU_ADR_END                                (0x0FFFFFFF)
+#define TCM_DMA_ADR_ST                                 (0x20000000)
+#define TCM_DMA_ADR_END                                (0x2010FFFF)
+#define TCM_DMA_ADR_OFFSET                             (TCM_DMA_ADR_ST)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+static fsp_err_t gmac_open_param_check(gmac_instance_ctrl_t const * const p_instance_ctrl,
+                                       ether_cfg_t const * const          p_cfg);
+
+#endif                                 /* GMAC_CFG_PARAM_CHECKING_ENABLE */
+
+static fsp_err_t gmac_read_param_check(gmac_instance_ctrl_t * p_instance_ctrl,
+                                       void * const           p_buffer,
+                                       uint32_t * const       length_bytes);
+
+static fsp_err_t gmac_write_param_check(gmac_instance_ctrl_t * p_instance_ctrl,
+                                        void * const           p_buffer,
+                                        uint32_t const         frame_length);
+
+static void gmac_enable_icu(gmac_instance_ctrl_t * const p_instance_ctrl);
+static void gmac_disable_icu(gmac_instance_ctrl_t * const p_instance_ctrl);
+static void gmac_reset_mac(volatile R_GMAC_Type * const p_reg);
+
+#ifdef GMAC_IMPLEMENT_ETHSW
+static fsp_err_t gmac_open_ethsw(gmac_instance_ctrl_t * p_instance_ctrl);
+
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+
+static fsp_err_t gmac_open_phy(gmac_instance_ctrl_t * p_instance_ctrl);
+static void      gmac_init_descriptors(gmac_instance_ctrl_t * const p_instance_ctrl);
+static fsp_err_t gmac_buffer_get(gmac_instance_ctrl_t * const p_instance_ctrl,
+                                 void ** const                p_buffer,
+                                 uint32_t                   * p_buffer_size);
+static void gmac_config_ethernet(gmac_instance_ctrl_t const * const p_instance_ctrl, const uint8_t mode);
+static void gmac_pause_resolution(uint32_t const local_ability,
+                                  uint32_t const partner_ability,
+                                  uint32_t     * p_tx_pause,
+                                  uint32_t     * p_rx_pause);
+static void gmac_configure_mac(gmac_instance_ctrl_t * const p_instance_ctrl,
+                               const uint8_t                mac_addr[],
+                               const uint8_t                mode);
+static void gmac_disable(gmac_instance_ctrl_t * const p_instance_ctrl);
+static void gmac_call_user_callback(gmac_instance_ctrl_t * p_instance_ctrl,
+                                    ether_event_t          event,
+                                    gmac_port_mask_t       link_status);
+static fsp_err_t          gmac_link_process(gmac_instance_ctrl_t * p_instance_ctrl, uint32_t port);
+static gmac_link_change_t gmac_link_change_check(gmac_instance_ctrl_t * p_instance_ctrl, uint32_t port);
+static fsp_err_t          gmac_do_link(gmac_instance_ctrl_t * const p_instance_ctrl, const uint32_t port);
+static void               gmac_configure_operation(gmac_instance_ctrl_t * const p_instance_ctrl);
+static void               gmac_magic_packet_detection(gmac_instance_ctrl_t * const p_instance_ctrl);
+
+static fsp_err_t gmac_link_status_check(gmac_instance_ctrl_t const * const p_instance_ctrl, uint32_t port);
+static uint8_t   gmac_check_magic_packet_detection_bit(gmac_instance_ctrl_t const * const p_instance_ctrl);
+
+static void gmac_call_callback(gmac_instance_ctrl_t * p_instance_ctrl, ether_callback_args_t * p_callback_args);
+void        gmac_isr_sbd(void);
+void        gmac_isr_pmt(void);
+
+#ifdef GMAC_IMPLEMENT_ETHSW
+void gmac_callback_ethsw(ether_switch_callback_args_t * const p_arg);
+
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/** Name of module used by error logger macro */
+#if BSP_CFG_ERROR_LOG != 0
+static const char g_module_name[] = "ether";
+#endif
+
+#if defined(__GNUC__)
+
+/* This structure is affected by warnings from a GCC compiler bug. This pragma suppresses the warnings in this
+ * structure only.*/
+
+/*LDRA_INSPECTED 69 S */
+ #pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+#endif
+
+/** ETHER HAL API mapping for Ethernet Controller interface */
+/*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */
+const ether_api_t g_ether_on_gmac =
+{
+    .open            = R_GMAC_Open,
+    .close           = R_GMAC_Close,
+    .read            = R_GMAC_Read,
+    .bufferRelease   = R_GMAC_BufferRelease,
+    .rxBufferUpdate  = R_GMAC_RxBufferUpdate,
+    .write           = R_GMAC_Write,
+    .linkProcess     = R_GMAC_LinkProcess,
+    .wakeOnLANEnable = R_GMAC_WakeOnLANEnable,
+    .txStatusGet     = R_GMAC_TxStatusGet,
+    .callbackSet     = R_GMAC_CallbackSet,
+};
+
+/*
+ * PAUSE Resolution as documented in IEEE 802.3-2008_section2 Annex
+ * 28B, Table 28B-3. The following table codify logic that
+ * determines how the PAUSE is configured for local transmitter
+ * and receiver and partner transmitter and receiver.
+ */
+static const gmac_pause_resolution_t pause_resolution[GMAC_PAUSE_TABLE_ENTRIES] =
+{
+    {GMAC_PAUSE_MASKC, GMAC_PAUSE_VAL0, GMAC_PAUSE_XMIT_OFF, GMAC_PAUSE_RECV_OFF  },
+    {GMAC_PAUSE_MASKE, GMAC_PAUSE_VAL4, GMAC_PAUSE_XMIT_OFF, GMAC_PAUSE_RECV_OFF  },
+    {GMAC_PAUSE_MASKF, GMAC_PAUSE_VAL6, GMAC_PAUSE_XMIT_OFF, GMAC_PAUSE_RECV_OFF  },
+    {GMAC_PAUSE_MASKF, GMAC_PAUSE_VAL7, GMAC_PAUSE_XMIT_ON,  GMAC_PAUSE_RECV_OFF  },
+    {GMAC_PAUSE_MASKE, GMAC_PAUSE_VAL8, GMAC_PAUSE_XMIT_OFF, GMAC_PAUSE_RECV_OFF  },
+    {GMAC_PAUSE_MASKA, GMAC_PAUSE_VALA, GMAC_PAUSE_XMIT_ON,  GMAC_PAUSE_RECV_ON   },
+    {GMAC_PAUSE_MASKF, GMAC_PAUSE_VALC, GMAC_PAUSE_XMIT_OFF, GMAC_PAUSE_RECV_OFF  },
+    {GMAC_PAUSE_MASKF, GMAC_PAUSE_VALD, GMAC_PAUSE_XMIT_OFF, GMAC_PAUSE_RECV_ON   }
+};
+
+static const gmac_port_mask_t g_gmac_port_mask[BSP_FEATURE_GMAC_MAX_PORTS] =
+{GMAC_PORT_MASK_0, GMAC_PORT_MASK_1, GMAC_PORT_MASK_2};
+
+/*******************************************************************************************************************//**
+ * @addtogroup ETHER
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/********************************************************************************************************************//**
+ * After ETHERC, EDMAC and PHY-LSI are reset in software, an auto negotiation of PHY-LSI is begun.
+ * Afterwards, the link signal change interrupt is permitted. Implements @ref ether_api_t::open.
+ *
+ * @retval  FSP_SUCCESS                             Channel opened successfully.
+ * @retval  FSP_ERR_ASSERTION                       Pointer to ETHER control block or configuration structure is NULL.
+ * @retval  FSP_ERR_ALREADY_OPEN                    Control block has already been opened or channel is being used by another
+ *                                                  instance. Call close() then open() to reconfigure.
+ * @retval  FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION   Initialization of PHY-LSI failed.
+ * @retval  FSP_ERR_INVALID_CHANNEL                 Invalid channel number is given.
+ * @retval  FSP_ERR_INVALID_POINTER                 Pointer to MAC address is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                Interrupt is not enabled.
+ * @retval  FSP_ERR_ETHER_PHY_ERROR_LINK            Initialization of PHY-LSI failed.
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p_cfg)
+{
+    fsp_err_t              err             = FSP_SUCCESS;
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+    volatile R_GMAC_Type * p_reg_gmac      = (R_GMAC_Type *) R_GMAC_BASE;
+    gmac_extend_cfg_t    * p_extend;
+    uint32_t               i;
+
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+
+    /** Check parameters. */
+    err = gmac_open_param_check(p_instance_ctrl, p_cfg); /** check arguments */
+    GMAC_ERROR_RETURN((FSP_SUCCESS == err), err);
+#endif
+
+    /** Make sure this channel exists. */
+    p_instance_ctrl->p_reg_gmac = (void *) p_reg_gmac;
+
+    /* Initialize configuration of Ethernet module. */
+    p_instance_ctrl->p_gmac_cfg = p_cfg;
+
+    /* Initialize the flags */
+    p_instance_ctrl->magic_packet = GMAC_MAGIC_PACKET_NOT_DETECTED;
+
+    /* Clear Link status */
+    p_instance_ctrl->link_status           = (gmac_port_mask_t) 0;
+    p_instance_ctrl->previous_link_status  = (gmac_port_mask_t) 0;
+    p_instance_ctrl->link_establish_status = (gmac_port_mask_t) 0;
+
+    /* Initialize the transmit and receive descriptor */
+    p_extend = (gmac_extend_cfg_t *) p_cfg->p_extend;
+
+    memset(p_extend->p_rx_descriptors,
+           0x00,
+           sizeof(gmac_instance_descriptor_t) *
+           p_instance_ctrl->p_gmac_cfg->num_rx_descriptors);
+
+    memset(p_extend->p_tx_descriptors,
+           0x00,
+           sizeof(gmac_instance_descriptor_t) *
+           p_instance_ctrl->p_gmac_cfg->num_tx_descriptors);
+
+    /* Initialize the Ether buffer */
+    for (i = 0;
+         i < (p_instance_ctrl->p_gmac_cfg->num_tx_descriptors + p_instance_ctrl->p_gmac_cfg->num_rx_descriptors);
+         i++)
+    {
+        memset(p_instance_ctrl->p_gmac_cfg->pp_ether_buffers[i], 0x00, p_instance_ctrl->p_gmac_cfg->ether_buffer_size);
+    }
+
+    /* Set callback and context pointers, if configured */
+    p_instance_ctrl->p_callback        = p_cfg->p_callback;
+    p_instance_ctrl->p_context         = p_cfg->p_context;
+    p_instance_ctrl->p_callback_memory = NULL;
+
+    /* Module start */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+    R_BSP_MODULE_START(FSP_IP_GMAC, p_cfg->channel);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_GMAC0_PCLKH);
+    R_BSP_ModuleResetDisable(BSP_MODULE_RESET_GMAC0_PCLKM);
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+#ifdef GMAC_IMPLEMENT_ETHSW
+
+    /* Open Ether-Switch Driver */
+    err = gmac_open_ethsw(p_instance_ctrl);
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Open Ether-Phy Driver */
+        err = gmac_open_phy(p_instance_ctrl);
+
+        if (FSP_ERR_ETHER_PHY_ERROR_LINK == err)
+        {
+            err = FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION;
+        }
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* Software reset */
+        gmac_reset_mac(p_instance_ctrl->p_reg_gmac);
+
+        p_reg_gmac->Interrupt_Mask_b.LPIIM = 1; /* LPI Interrupt Disable */
+        p_reg_gmac->Interrupt_Mask_b.TSIM  = 1; /* Timestamo Interrupt Disable */
+        p_reg_gmac->Interrupt_Mask_b.PMTIM = 1; /* PMT Interrupt Disable */
+
+        gmac_enable_icu(p_instance_ctrl);
+        p_instance_ctrl->open = GMAC_OPEN;
+    }
+
+    return err;
+}                                      /* End of function R_GMAC_Open() */
+
+/********************************************************************************************************************//**
+ * Disables interrupts. Removes power and releases hardware lock. Implements @ref ether_api_t::close.
+ *
+ * @retval  FSP_SUCCESS                                 Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened
+ *
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_Close (ether_ctrl_t * const p_ctrl)
+{
+    fsp_err_t               err = FSP_SUCCESS;
+    uint32_t                i;
+    ether_phy_instance_t ** pp_phy_instance;
+    gmac_extend_cfg_t     * p_extend;
+
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+    volatile R_GMAC_Type * p_reg_gmac;
+
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    /* Disable Ethernet interrupt. */
+    gmac_disable_icu(p_instance_ctrl);
+
+    p_extend        = (gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend;
+    pp_phy_instance = (ether_phy_instance_t **) p_extend->pp_phy_instance;
+
+    for (i = 0; BSP_FEATURE_GMAC_MAX_PORTS > i; i++)
+    {
+        if (NULL != pp_phy_instance[i])
+        {
+            pp_phy_instance[i]->p_api->close(pp_phy_instance[i]->p_ctrl);
+        }
+    }
+
+#ifdef GMAC_IMPLEMENT_ETHSW
+    p_extend->p_ethsw_instance->p_api->close(p_extend->p_ethsw_instance->p_ctrl);
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+
+    p_reg_gmac->Interrupt_Enable = 0;
+
+    /* Disable TE and RE  */
+    p_reg_gmac->MAC_Configuration_b.RE = 0;
+    p_reg_gmac->MAC_Configuration_b.TE = 0;
+
+    /* Initialize the flags */
+    p_instance_ctrl->magic_packet = GMAC_MAGIC_PACKET_NOT_DETECTED;
+
+    /* Clear Link status */
+    p_instance_ctrl->link_status           = (gmac_port_mask_t) 0;
+    p_instance_ctrl->previous_link_status  = (gmac_port_mask_t) 0;
+    p_instance_ctrl->link_establish_status = (gmac_port_mask_t) 0;
+
+    /** Clear configure block parameters. */
+    p_instance_ctrl->p_gmac_cfg = NULL;
+
+    /** Mark the channel not open so other APIs cannot use it. */
+    p_instance_ctrl->open = 0U;
+
+    return err;
+}                                      /* End of function R_GMAC_Close() */
+
+/********************************************************************************************************************//**
+ * Move to the next buffer in the circular receive buffer list. Implements @ref ether_api_t::bufferRelease.
+ *
+ * @retval  FSP_SUCCESS                             Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                       Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                        The control block has not been opened
+ * @retval  FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE   As a Magic Packet is being detected, transmission and reception is
+ *                                                  not enabled.
+ * @retval  FSP_ERR_ETHER_ERROR_LINK                Link is down.
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_BufferRelease (ether_ctrl_t * const p_ctrl)
+{
+    fsp_err_t              err             = FSP_SUCCESS;
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+    volatile R_GMAC_Type * p_reg_gmac;
+
+    /* Check argument */
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* When the Link up processing is not completed, return error */
+    GMAC_ERROR_RETURN(0 != p_instance_ctrl->previous_link_status, FSP_ERR_ETHER_ERROR_LINK);
+
+    /* In case of detection mode of magic packet, return error. */
+    GMAC_ERROR_RETURN(0 == gmac_check_magic_packet_detection_bit(p_instance_ctrl),
+                      FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE);
+
+    /* When receive data exists */
+    if (GMAC_RDES0_OWN != (p_instance_ctrl->p_rx_descriptor->des0 & GMAC_RDES0_OWN))
+    {
+        /* Enable current descriptor */
+        p_instance_ctrl->p_rx_descriptor->des0 |= GMAC_RDES0_OWN;
+
+        /* Update pointer to the currently referenced receive descriptor  */
+        if (GMAC_RDES1_RER == (p_instance_ctrl->p_rx_descriptor->des1 & GMAC_RDES1_RER))
+        {
+            p_instance_ctrl->p_rx_descriptor =
+                ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_rx_descriptors;
+        }
+        else
+        {
+            p_instance_ctrl->p_rx_descriptor++;
+        }
+    }
+
+    p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+    p_reg_gmac->Receive_Poll_Demand_b.RPD = 0;
+
+    err = FSP_SUCCESS;
+
+    return err;
+}                                      /* End of function R_GMAC_BufferRelease() */
+
+/********************************************************************************************************************//**
+ * Change the buffer pointer of the current rx buffer descriptor. Implements @ref ether_api_t::rxBufferUpdate.
+ *
+ * @retval  FSP_SUCCESS                             Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                       A pointer argument is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                        The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER                 The pointer of buffer is NULL or not aligned on a 32-bit boundary.
+ * @retval  FSP_ERR_INVALID_MODE                    Driver is configured to non zero copy mode.
+ * @retval  FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE     All descriptor is active.
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_RxBufferUpdate (ether_ctrl_t * const p_ctrl, void * const p_buffer)
+{
+    fsp_err_t              err             = FSP_SUCCESS;
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+    volatile R_GMAC_Type * p_reg_gmac;
+
+    /* Check argument */
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    GMAC_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN(ETHER_ZEROCOPY_ENABLE == p_instance_ctrl->p_gmac_cfg->zerocopy, FSP_ERR_INVALID_MODE);
+#endif
+
+    /* When receive data exists */
+    if (GMAC_RDES0_OWN != (p_instance_ctrl->p_rx_descriptor->des0 & GMAC_RDES0_OWN))
+    {
+        if (TCM_CPU_ADR_END >= (uint32_t) p_buffer)
+        {
+            /* Offset for DMA */
+            p_instance_ctrl->p_rx_descriptor->des2 = (uint32_t) p_buffer + TCM_DMA_ADR_OFFSET;
+        }
+        else
+        {
+            p_instance_ctrl->p_rx_descriptor->des2 = (uint32_t) p_buffer;
+        }
+
+        /* Enable current descriptor */
+        p_instance_ctrl->p_rx_descriptor->des0 |= GMAC_RDES0_OWN;
+
+        /* Update pointer to the currently referenced receive descriptor  */
+        if (GMAC_RDES1_RER == (p_instance_ctrl->p_rx_descriptor->des1 & GMAC_RDES1_RER))
+        {
+            p_instance_ctrl->p_rx_descriptor =
+                ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_rx_descriptors;
+        }
+        else
+        {
+            p_instance_ctrl->p_rx_descriptor++;
+        }
+
+        p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+        p_reg_gmac->Receive_Poll_Demand_b.RPD = 0;
+    }
+    else
+    {
+        err = FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE;
+    }
+
+    return err;
+}                                      /* End of function R_GMAC_RxBufferUpdate() */
+
+/********************************************************************************************************************//**
+ * The Link up processing, the Link down processing, and the magic packet detection processing are executed.
+ * Implements @ref ether_api_t::linkProcess.
+ *
+ * @retval  FSP_SUCCESS                             Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                       Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                        The control block has not been opened.
+ * @retval  FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION   When reopening the PHY interface initialization of the PHY-LSI failed.
+ * @retval  FSP_ERR_ALREADY_OPEN                    When reopening the PHY interface it was already opened.
+ * @retval  FSP_ERR_INVALID_CHANNEL                 When reopening the PHY interface an invalid channel was passed.
+ * @retval  FSP_ERR_INVALID_POINTER                 When reopening the PHY interface the MAC address pointer was NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                When reopening the PHY interface the interrupt was not enabled.
+ * @retval  FSP_ERR_ETHER_PHY_ERROR_LINK            Initialization of the PHY-LSI failed.
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_LinkProcess (ether_ctrl_t * const p_ctrl)
+{
+    fsp_err_t              err             = FSP_SUCCESS;
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+
+    ether_cfg_t const     * p_gmac_cfg;
+    gmac_port_mask_t        temp_previous_link_status;
+    gmac_port_mask_t        previous_link_establish_status;
+    ether_phy_instance_t ** pp_phy_instance;
+    gmac_extend_cfg_t     * p_extend;
+    void (* temp_p_callback)(ether_callback_args_t *);
+    ether_callback_args_t * temp_p_callback_memory;
+    void const            * temp_p_context;
+
+    uint32_t i;
+
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_gmac_cfg = p_instance_ctrl->p_gmac_cfg;
+
+    /* When the magic packet is detected. */
+    if (GMAC_MAGIC_PACKET_DETECTED == p_instance_ctrl->magic_packet)
+    {
+        p_instance_ctrl->magic_packet = GMAC_MAGIC_PACKET_NOT_DETECTED;
+
+        gmac_call_user_callback(p_instance_ctrl, ETHER_EVENT_WAKEON_LAN, (gmac_port_mask_t) 0);
+
+        /*
+         * After the close function is called, the open function is called
+         * to have to set ETHERC to a usual operational mode
+         * to usually communicate after magic packet is detected.
+         *//* back up previous_link_status */
+        temp_previous_link_status = p_instance_ctrl->previous_link_status;
+
+        /* back up callback and contex */
+        temp_p_callback        = p_instance_ctrl->p_callback;
+        temp_p_callback_memory = p_instance_ctrl->p_callback_memory;
+        temp_p_context         = p_instance_ctrl->p_context;
+
+        err = R_GMAC_Close((ether_ctrl_t *) p_instance_ctrl);
+        GMAC_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+        err = R_GMAC_Open((ether_ctrl_t *) p_instance_ctrl, (ether_cfg_t *) p_gmac_cfg);
+        GMAC_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+        /* restore previous_link_status */
+        p_instance_ctrl->previous_link_status = temp_previous_link_status;
+
+        /* restore callback and contex */
+        p_instance_ctrl->p_callback        = temp_p_callback;
+        p_instance_ctrl->p_callback_memory = temp_p_callback_memory;
+        p_instance_ctrl->p_context         = temp_p_context;
+    }
+
+    previous_link_establish_status = p_instance_ctrl->link_establish_status;
+
+    p_extend        = (gmac_extend_cfg_t *) p_gmac_cfg->p_extend;
+    pp_phy_instance = (ether_phy_instance_t **) p_extend->pp_phy_instance;
+
+    for (i = 0; BSP_FEATURE_GMAC_MAX_PORTS > i; i++)
+    {
+        if (NULL != pp_phy_instance[i])
+        {
+            /* Open Ether-Phy */
+            (void) gmac_link_process(p_instance_ctrl, i);
+        }
+    }
+
+    if (0 == previous_link_establish_status)
+    {
+        if (0 != p_instance_ctrl->link_establish_status)
+        {
+            /* Previous link status of all ports are down */
+            /* Initialize the transmit and receive descriptor */
+            memset(p_extend->p_rx_descriptors, 0x00,
+                   sizeof(gmac_instance_descriptor_t) * p_gmac_cfg->num_rx_descriptors);
+            memset(p_extend->p_tx_descriptors, 0x00,
+                   sizeof(gmac_instance_descriptor_t) * p_gmac_cfg->num_tx_descriptors);
+
+            /* Initialize the Ether buffer */
+            for (i = 0;
+                 i < (p_gmac_cfg->num_tx_descriptors + p_gmac_cfg->num_rx_descriptors);
+                 i++)
+            {
+                memset(p_gmac_cfg->pp_ether_buffers[i], 0x00, p_gmac_cfg->ether_buffer_size);
+            }
+
+            /*
+             * ETHERC and EDMAC are set after ETHERC and EDMAC are reset in software
+             * and sending and receiving is permitted.
+             */
+            gmac_configure_mac(p_instance_ctrl, p_gmac_cfg->p_mac_address, GMAC_NO_USE_MAGIC_PACKET_DETECT);
+            gmac_configure_operation(p_instance_ctrl);
+
+            if (GMAC_MAGIC_PACKET_DETECTING == p_instance_ctrl->magic_packet)
+            {
+                R_GMAC_WakeOnLANEnable(p_ctrl);
+            }
+        }
+    }
+    else
+    {
+        if (0 == p_instance_ctrl->previous_link_status)
+        {
+            // Reset GMAC to force "MTL RX FIFO Read Controller State" to idle.
+            // This is a countermeasure because the register Debug.RRCSTS does not become 0 (IDLE state).
+
+            volatile R_GMAC_Type * p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+            /* Reset GMAC. */
+            gmac_reset_mac(p_instance_ctrl->p_reg_gmac);
+
+            p_reg_gmac->Interrupt_Mask_b.LPIIM = 1; /* LPI Interrupt Disable */
+            p_reg_gmac->Interrupt_Mask_b.TSIM  = 1; /* Timestamo Interrupt Disable */
+            p_reg_gmac->Interrupt_Mask_b.PMTIM = 1; /* PMT Interrupt Disable */
+        }
+    }
+
+    return err;
+}                                      /* End of function R_GMAC_LinkProcess() */
+
+/********************************************************************************************************************//**
+ * Get link status of specificed port.
+ *
+ * @retval  FSP_SUCCESS                                 Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER                     Value of the pointer is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                    When reopening the PHY interface the interrupt was not enabled.
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_GetLinkStatus (ether_ctrl_t * const p_ctrl, uint8_t port, gmac_link_status_t * p_status)
+{
+    gmac_port_mask_t port_status;
+    fsp_err_t        err = FSP_SUCCESS;
+
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+
+    /* Check argument */
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    GMAC_ERROR_RETURN(NULL != p_status, FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN(BSP_FEATURE_GMAC_MAX_PORTS > port, FSP_ERR_INVALID_ARGUMENT);
+
+    GMAC_ERROR_RETURN(0 != (*((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->pp_phy_instance)[port],
+                      FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    port_status = g_gmac_port_mask[port];
+
+    if (port_status == (p_instance_ctrl->previous_link_status & port_status))
+    {
+        if (port_status == (p_instance_ctrl->link_establish_status & port_status))
+        {
+            *p_status = GMAC_LINK_STATUS_READY;
+        }
+        else
+        {
+            *p_status = GMAC_LINK_STATUS_UP;
+        }
+    }
+    else
+    {
+        *p_status = GMAC_LINK_STATUS_DOWN;
+    }
+
+    return err;
+}                                      /* End of function R_GMAC_GetLinkStatus() */
+
+/********************************************************************************************************************//**
+ * The setting of ETHERC is changed from normal sending and receiving mode to magic packet detection mode.
+ * Implements @ref ether_api_t::wakeOnLANEnable.
+ *
+ * @retval  FSP_SUCCESS                                 Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened.
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_WakeOnLANEnable (ether_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+
+    /* Check argument */
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_instance_ctrl->magic_packet = GMAC_MAGIC_PACKET_DETECTING;
+
+    /* When the Link up processing is completed */
+    /* Change to the magic packet detection mode.  */
+    gmac_configure_mac(p_instance_ctrl, p_instance_ctrl->p_gmac_cfg->p_mac_address, GMAC_USE_MAGIC_PACKET_DETECT);
+    gmac_magic_packet_detection(p_instance_ctrl);
+
+    return err;
+}                                      /* End of function R_GMAC_WakeOnLANEnable() */
+
+/********************************************************************************************************************//**
+ * Receive Ethernet frame. Receives data to the location specified by the pointer to the receive buffer.
+ * In zero copy mode, the address of the receive buffer is returned.
+ * In non zero copy mode, the received data in the internal buffer is copied to the pointer passed by the argument.
+ * Implements @ref ether_api_t::read.
+ *
+ * @retval  FSP_SUCCESS                                 Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened.
+ * @retval  FSP_ERR_ETHER_ERROR_NO_DATA                 There is no data in receive buffer.
+ * @retval  FSP_ERR_ETHER_ERROR_LINK                    Auto-negotiation is not completed, and reception is not enabled.
+ * @retval  FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE       As a Magic Packet is being detected, transmission and reception
+ *                                                      is not enabled.
+ * @retval  FSP_ERR_INVALID_POINTER                     Value of the pointer is NULL.
+ *
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_Read (ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t * const length_bytes)
+{
+    fsp_err_t              err             = FSP_SUCCESS;
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+    uint8_t              * p_read_buffer   = NULL; /* Buffer location controlled by the Ethernet driver */
+    uint32_t               received_size   = GMAC_NO_DATA;
+    uint8_t             ** pp_read_buffer  = (uint8_t **) p_buffer;
+
+    /* Check argument */
+    err = gmac_read_param_check(p_instance_ctrl, p_buffer, length_bytes);
+
+    while (FSP_SUCCESS == err)
+    {
+        /* When receive data exists. */
+
+        if (GMAC_RDES0_OWN != (p_instance_ctrl->p_rx_descriptor->des0 & GMAC_RDES0_OWN))
+        {
+            if ((GMAC_RDES0_ES == (p_instance_ctrl->p_rx_descriptor->des0 & GMAC_RDES0_ES)) ||
+                ((GMAC_RDES0_FS | GMAC_RDES0_LS) !=
+                 (p_instance_ctrl->p_rx_descriptor->des0 & (GMAC_RDES0_FS | GMAC_RDES0_LS))))
+            {
+                /* The buffer is released when it is at the error or when single-frame is not in single descriptor. */
+                err = R_GMAC_BufferRelease((ether_ctrl_t *) p_instance_ctrl);
+                continue;
+            }
+
+            /* If put in TCM, adjust offset for DMA */
+            if ((p_instance_ctrl->p_rx_descriptor->des2 >= TCM_DMA_ADR_ST) &&
+                (p_instance_ctrl->p_rx_descriptor->des2 <= TCM_DMA_ADR_END))
+            {
+                p_read_buffer = (uint8_t *) (p_instance_ctrl->p_rx_descriptor->des2 - TCM_DMA_ADR_OFFSET);
+            }
+            else
+            {
+                p_read_buffer = (uint8_t *) p_instance_ctrl->p_rx_descriptor->des2;
+            }
+
+            received_size = (p_instance_ctrl->p_rx_descriptor->des0 & GMAC_RDES0_FL_MASK) >>
+                            GMAC_RDES0_FL_SHIFT;
+
+            if (GMAC_MINIMUM_FRAME_SIZE > received_size)
+            {
+                /* bytes received is short */
+                err = R_GMAC_BufferRelease((ether_ctrl_t *) p_instance_ctrl);
+                continue;
+            }
+        }
+        else
+        {
+            err = FSP_ERR_ETHER_ERROR_NO_DATA;
+        }
+
+        break;
+    }
+
+    if (FSP_SUCCESS == err)
+    {
+        /* When there is data to receive */
+        if (received_size > GMAC_NO_DATA)
+        {
+            if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_gmac_cfg->zerocopy)
+            {
+                /* (2) Copy the data read from the receive buffer which is controlled
+                 *     by the descriptor to the buffer which is specified by the user (up to 1024 bytes). */
+                memcpy(p_buffer, p_read_buffer, received_size);
+
+                /* (3) Read the receive data from the receive buffer controlled by the descriptor,
+                 * and then release the receive buffer. */
+                err = R_GMAC_BufferRelease((ether_ctrl_t *) p_instance_ctrl);
+            }
+            else
+            {
+                *pp_read_buffer = p_read_buffer;
+            }
+
+            *length_bytes = received_size;
+        }
+        /* When there is no data to receive */
+        else
+        {
+            err = FSP_ERR_ETHER_ERROR_NO_DATA;
+        }
+    }
+
+    return err;
+}                                      /* End of function R_GMAC_Read() */
+
+/********************************************************************************************************************//**
+ * Transmit Ethernet frame. Transmits data from the location specified by the pointer to the transmit
+ *  buffer, with the data size equal to the specified frame length.
+ *  In the non zero copy mode, transmits data after being copied to the internal buffer.
+ *  Implements @ref ether_api_t::write.
+ *
+ * @retval  FSP_SUCCESS                                Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                          Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                           The control block has not been opened.
+ * @retval  FSP_ERR_ETHER_ERROR_LINK                    Auto-negotiation is not completed, and reception is not enabled.
+ * @retval  FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE       As a Magic Packet is being detected, transmission and reception
+ *                                                     is not enabled.
+ * @retval  FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL    Transmit buffer is not empty.
+ * @retval  FSP_ERR_INVALID_POINTER                    Value of the pointer is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                   Value of the send frame size is out of range.
+ *
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_Write (ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length)
+{
+    fsp_err_t              err             = FSP_SUCCESS;
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+    volatile R_GMAC_Type * p_reg_gmac;
+
+    uint8_t * p_write_buffer;
+    uint32_t  write_buffer_size;
+
+    /* Check argument */
+    err = gmac_write_param_check(p_instance_ctrl, p_buffer, frame_length);
+    GMAC_ERROR_RETURN((FSP_SUCCESS == err), err);
+
+    if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_gmac_cfg->zerocopy)
+    {
+        /* (1) Retrieve the transmit buffer location controlled by the  descriptor. */
+        err = gmac_buffer_get(p_instance_ctrl, (void **) &p_write_buffer, &write_buffer_size);
+
+        /* Writing to the transmit buffer (buf) is enabled. */
+        if (FSP_SUCCESS == err)
+        {
+            if (write_buffer_size < frame_length)
+            {
+                err = FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL; /* Transmit buffer overflow */
+            }
+            else
+            {
+                /* Write the transmit data to the transmit buffer. */
+
+                /* (2) Write the data to the transmit buffer controlled by the  descriptor. */
+                memcpy(p_write_buffer, p_buffer, frame_length);
+            }
+        }
+    }
+
+    /* Writing to the transmit buffer (buf) is enabled. */
+    if (FSP_SUCCESS == err)
+    {
+        /* (3) Enable the EDMAC to transmit data in the transmit buffer. */
+        /* When the Link up processing is not completed, return error */
+
+        /* The data of the buffer is made active.  */
+        if (ETHER_ZEROCOPY_ENABLE == p_instance_ctrl->p_gmac_cfg->zerocopy)
+        {
+            p_instance_ctrl->p_tx_descriptor->des2 = (uint32_t) p_buffer; // Set Buffer 1 Address of TDES
+
+            /* Offset for DMA */
+            if (p_instance_ctrl->p_tx_descriptor->des2 <= TCM_CPU_ADR_END)
+            {
+                p_instance_ctrl->p_tx_descriptor->des2 += TCM_DMA_ADR_OFFSET;
+            }
+        }
+
+        p_instance_ctrl->p_tx_descriptor->des1 = frame_length;
+
+        /* Update pointer to the currently referenced transmit descriptor  */
+        if (GMAC_TDES0_TER == (p_instance_ctrl->p_tx_descriptor->des0 & GMAC_TDES0_TER))
+        {
+            p_instance_ctrl->p_tx_descriptor->des0 = (GMAC_TDES0_OWN |
+                                                      GMAC_TDES0_IC |
+                                                      GMAC_TDES0_LS |
+                                                      GMAC_TDES0_FS |
+                                                      GMAC_TDES0_TER);
+
+            p_instance_ctrl->p_tx_descriptor =
+                ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_tx_descriptors;
+        }
+        else
+        {
+            p_instance_ctrl->p_tx_descriptor->des0 = (GMAC_TDES0_OWN |
+                                                      GMAC_TDES0_IC |
+                                                      GMAC_TDES0_LS |
+                                                      GMAC_TDES0_FS);
+            p_instance_ctrl->p_tx_descriptor++;
+        }
+
+        /* Restart transmit */
+        p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+        __asm("dmb");
+        p_reg_gmac->Transmit_Poll_Demand = 0;
+    }
+
+    return err;
+}                                      /* End of function R_GMAC_Write() */
+
+/**********************************************************************************************************************//**
+ * Provides status of Ethernet driver in the user provided pointer. Implements @ref ether_api_t::txStatusGet.
+ *
+ * @retval  FSP_SUCCESS                  Transmit buffer address is stored in provided p_buffer_address.
+ * @retval  FSP_ERR_ASSERTION            Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
+ * @retval  FSP_ERR_INVALID_POINTER      p_status is NULL.
+ * @retval  FSP_ERR_NOT_FOUND            Transmit buffer address has been overwritten in transmit descriptor.
+ ***********************************************************************************************************************/
+fsp_err_t R_GMAC_TxStatusGet (ether_ctrl_t * const p_ctrl, void * const p_buffer_address)
+{
+    gmac_instance_ctrl_t       * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+    volatile R_GMAC_Type       * p_reg_gmac;
+    gmac_instance_descriptor_t * p_descriptor;
+    uint8_t ** p_sent_buffer_address = (uint8_t **) p_buffer_address;
+    fsp_err_t  err = FSP_ERR_NOT_FOUND;
+    uint32_t   current_descriptor;
+
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    GMAC_ERROR_RETURN(NULL != p_buffer_address, FSP_ERR_INVALID_POINTER);
+#endif
+
+    p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    current_descriptor = p_reg_gmac->Current_Host_Transmit_Descriptor;
+
+    /* If put in TCM, adjust offset for DMA */
+    if ((current_descriptor >= TCM_DMA_ADR_ST) &&
+        (current_descriptor <= TCM_DMA_ADR_END))
+    {
+        current_descriptor -= TCM_DMA_ADR_OFFSET;
+    }
+
+    p_descriptor = (gmac_instance_descriptor_t *) current_descriptor;
+
+    /* Descriptor is NULL, when no packet transmitted. */
+    if (NULL != p_descriptor)
+    {
+        uint32_t num_tx_descriptors = p_instance_ctrl->p_gmac_cfg->num_tx_descriptors;
+        gmac_instance_descriptor_t * p_tx_descriptors =
+            ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_tx_descriptors;
+
+        p_descriptor = (gmac_instance_descriptor_t *) ((uint8_t *) p_descriptor - sizeof(gmac_instance_descriptor_t));
+
+        if (p_descriptor < p_tx_descriptors)
+        {
+            p_descriptor = &p_tx_descriptors[num_tx_descriptors - 1];
+        }
+
+        /* Check that the descriptor is not overridden. */
+        if ((0 != p_descriptor->des2) && (GMAC_TDES0_OWN != (p_descriptor->des0 & GMAC_TDES0_OWN)))
+        {
+            if ((p_descriptor->des2 >= TCM_DMA_ADR_ST) &&
+                (p_descriptor->des2 <= TCM_DMA_ADR_END))
+            {
+                *p_sent_buffer_address = (uint8_t *) (p_descriptor->des2 - TCM_DMA_ADR_OFFSET);
+            }
+            else
+            {
+                *p_sent_buffer_address = (uint8_t *) p_descriptor->des2;
+            }
+
+            err = FSP_SUCCESS;
+        }
+        else
+        {
+            ;
+        }
+    }
+
+    return err;
+}                                      /* End of function R_GMAC_TxStatusGet() */
+
+/*******************************************************************************************************************//**
+ * Updates the user callback with the option to provide memory for the callback argument structure.
+ * Implements @ref ether_api_t::callbackSet.
+ *
+ * @retval  FSP_SUCCESS                  Callback updated successfully.
+ * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GMAC_CallbackSet (ether_ctrl_t * const          p_ctrl,
+                              void (                      * p_callback)(ether_callback_args_t *),
+                              void const * const            p_context,
+                              ether_callback_args_t * const p_callback_memory)
+{
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_ctrl;
+
+#if ETHER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(p_callback);
+    FSP_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Store callback and context */
+    p_instance_ctrl->p_callback        = p_callback;
+    p_instance_ctrl->p_context         = p_context;
+    p_instance_ctrl->p_callback_memory = p_callback_memory;
+
+    return FSP_SUCCESS;
+}                                      /* End of function R_GMAC_CallbackSet() */
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ETHER)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+
+/*******************************************************************************************************************//**
+ * Parameter error check function for open.
+ *
+ * @param[in] p_instance_ctrl   Pointer to the control block for the channel
+ * @param[in] p_cfg             Pointer to the configuration structure specific to UART mode
+ *
+ * @retval  FSP_SUCCESS                  No parameter error found
+ * @retval  FSP_ERR_ASSERTION            Pointer to ETHER control block or configuration structure is NULL
+ * @retval  FSP_ERR_ALREADY_OPEN         Control block has already been opened
+ * @retval  FSP_ERR_INVALID_CHANNEL      Invalid channel number is given.
+ * @retval  FSP_ERR_INVALID_POINTER      Pointer to MAC address is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT      Irq number lower then 0.
+ **********************************************************************************************************************/
+static fsp_err_t gmac_open_param_check (gmac_instance_ctrl_t const * const p_instance_ctrl,
+                                        ether_cfg_t const * const          p_cfg)
+{
+    gmac_extend_cfg_t * p_extend;
+
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN((NULL != p_cfg), FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN((NULL != p_cfg->p_mac_address), FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN((BSP_FEATURE_GMAC_MAX_CHANNELS > p_cfg->channel), FSP_ERR_INVALID_CHANNEL);
+
+    GMAC_ERROR_RETURN((0 <= p_cfg->irq), FSP_ERR_INVALID_ARGUMENT);
+    GMAC_ERROR_RETURN((NULL != p_cfg->p_extend), FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN((NULL != p_cfg->pp_ether_buffers), FSP_ERR_INVALID_POINTER);
+
+    p_extend = (gmac_extend_cfg_t *) p_cfg->p_extend;
+
+    GMAC_ERROR_RETURN((NULL != p_extend->p_rx_descriptors), FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN((NULL != p_extend->p_tx_descriptors), FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN((0 <= p_extend->pmt_irq), FSP_ERR_INVALID_ARGUMENT);
+
+    GMAC_ERROR_RETURN((GMAC_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN);
+
+    return FSP_SUCCESS;
+}                                      /* End of function gmac_open_param_check() */
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Parameter error check function for read.
+ *
+ * @param[in] p_instance_ctrl   Pointer to the control block for the channel
+ * @param[in] p_buffer          Pointer to where to store read data.
+ * @param[in] length_bytes      Number of bytes in buffer
+ *
+ * @retval  FSP_SUCCESS                                 Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                           Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                            The control block has not been opened.
+ * @retval  FSP_ERR_ETHER_ERROR_LINK                     Auto-negotiation is not completed, and reception is not enabled.
+ * @retval  FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE        As a Magic Packet is being detected, transmission and reception
+ *                                                      is not enabled.
+ * @retval  FSP_ERR_INVALID_POINTER                     Value of the pointer is NULL.
+ **********************************************************************************************************************/
+static fsp_err_t gmac_read_param_check (gmac_instance_ctrl_t * p_instance_ctrl,
+                                        void * const           p_buffer,
+                                        uint32_t * const       length_bytes)
+{
+    /* Check argument */
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    GMAC_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN(NULL != length_bytes, FSP_ERR_INVALID_POINTER);
+#else
+    FSP_PARAMETER_NOT_USED(p_buffer);
+    FSP_PARAMETER_NOT_USED(length_bytes);
+#endif
+
+    /* (1) Retrieve the receive buffer location controlled by the  descriptor. */
+    /* When the Link up processing is not completed, return error */
+    GMAC_ERROR_RETURN(0 != p_instance_ctrl->link_establish_status, FSP_ERR_ETHER_ERROR_LINK);
+
+    /* In case of detection mode of magic packet, return error. */
+    GMAC_ERROR_RETURN(0 == gmac_check_magic_packet_detection_bit(p_instance_ctrl),
+                      FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE);
+
+    return FSP_SUCCESS;
+}                                      /* End of function gmac_read_param_check() */
+
+/*******************************************************************************************************************//**
+ * Parameter error check function for write.
+ *
+ * @param[in]  p_instance_ctrl  Pointer to the control block for the channel.
+ * @param[in]  p_buffer         Pointer to data to write.
+ * @param[in]  frame_length     Send ethernet frame size (without 4 bytes of CRC data size).
+ *
+ * @retval  FSP_SUCCESS                                Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION                          Pointer to ETHER control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN                           The control block has not been opened.
+ * @retval  FSP_ERR_ETHER_ERROR_LINK                    Auto-negotiation is not completed, and reception is not enabled.
+ * @retval  FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE       As a Magic Packet is being detected, transmission and reception
+ *                                                     is not enabled.
+ * @retval  FSP_ERR_INVALID_POINTER                    Value of the pointer is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT                   Value of the send frame size is out of range.
+ **********************************************************************************************************************/
+static fsp_err_t gmac_write_param_check (gmac_instance_ctrl_t * p_instance_ctrl,
+                                         void * const           p_buffer,
+                                         uint32_t const         frame_length)
+{
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    GMAC_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER);
+    GMAC_ERROR_RETURN(p_instance_ctrl->p_gmac_cfg->ether_buffer_size >= frame_length, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_buffer);
+    FSP_PARAMETER_NOT_USED(frame_length);
+#endif
+
+    /* When the Link up processing is not completed, return error */
+    GMAC_ERROR_RETURN(0 != p_instance_ctrl->link_establish_status, FSP_ERR_ETHER_ERROR_LINK);
+
+    /* In case of detection mode of magic packet, return error. */
+    GMAC_ERROR_RETURN(0 == gmac_check_magic_packet_detection_bit(p_instance_ctrl),
+                      FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE);
+
+    return FSP_SUCCESS;
+}                                      /* End of function gmac_write_param_check() */
+
+/*******************************************************************************************************************//**
+ * Reset The GMAC are reset through the software reset.
+ *
+ * @param[out]  p_reg       Base address of regeister for GMAC
+ *
+ * @retval  none
+ **********************************************************************************************************************/
+static void gmac_reset_mac (volatile R_GMAC_Type * const p_reg)
+{
+    p_reg->Bus_Mode_b.SWR = 1;
+
+    /* Wait for reset to complete */
+    while (p_reg->Bus_Mode_b.SWR == 1)
+    {
+        ;
+    }
+
+    /* Settings for TCM access */
+    p_reg->Bus_Mode_b.AAL       = 1;
+    p_reg->Bus_Mode_b.FB        = 1;
+    p_reg->Bus_Mode_b.USP       = 0;
+    p_reg->Bus_Mode_b.PBL       = 4;
+    p_reg->AXI_Bus_Mode_b.BLEN4 = 1;
+}                                      /* End of function gmac_reset_mac() */
+
+#ifdef GMAC_IMPLEMENT_ETHSW
+
+/*******************************************************************************************************************//**
+ * Open ether switch driver.
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval  FSP_SUCCESS                 Channel opened successfully.
+ **********************************************************************************************************************/
+fsp_err_t gmac_open_ethsw (gmac_instance_ctrl_t * p_instance_ctrl)
+{
+    ether_switch_instance_t const * p_ethsw_instance; ///< Pointer to ETHER_SWITCH instance
+    fsp_err_t err;
+
+    p_ethsw_instance = ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_ethsw_instance;
+
+    err = p_ethsw_instance->p_api->open(p_ethsw_instance->p_ctrl, p_ethsw_instance->p_cfg);
+    if (FSP_SUCCESS != err)
+    {
+        p_ethsw_instance->p_api->close(p_ethsw_instance->p_ctrl);
+    }
+
+    return err;
+}                                      /* End of function gmac_open_ethsw() */
+
+#endif // GMAC_IMPLEMENT_ETHSW
+
+/*******************************************************************************************************************//**
+ * Open ether phy driver.
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval  FSP_SUCCESS                             Channel opened successfully.
+ **********************************************************************************************************************/
+fsp_err_t gmac_open_phy (gmac_instance_ctrl_t * p_instance_ctrl)
+{
+    ether_phy_instance_t const *(*pp_phy_instance)[BSP_FEATURE_GMAC_MAX_PORTS];
+    ether_phy_instance_t const * p_phy_instance;
+
+    fsp_err_t err = FSP_SUCCESS;
+    uint32_t  i;
+
+    pp_phy_instance = ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->pp_phy_instance;
+
+    for (i = 0; BSP_FEATURE_GMAC_MAX_PORTS > i; i++)
+    {
+        p_phy_instance = (*pp_phy_instance)[i];
+
+        if (NULL != p_phy_instance)
+        {
+            /* Open Ether-Phy */
+            err = p_phy_instance->p_api->open(p_phy_instance->p_ctrl, p_phy_instance->p_cfg);
+            if (FSP_SUCCESS == err)
+            {
+                /* Start Auto-Negotiate */
+                p_phy_instance->p_api->startAutoNegotiate(p_phy_instance->p_ctrl);
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+
+    if (FSP_SUCCESS != err)
+    {
+        for (i = 0; BSP_FEATURE_GMAC_MAX_PORTS > i; i++)
+        {
+            p_phy_instance = (*pp_phy_instance)[i];
+
+            if (NULL != p_phy_instance)
+            {
+                p_phy_instance->p_api->close(p_phy_instance->p_ctrl);
+            }
+        }
+    }
+
+    return err;
+}                                      /* End of function gmac_open_phy() */
+
+/*******************************************************************************************************************//**
+ * The DMAC descriptors and the driver buffers are initialized.
+ *
+ * @param[in]   p_instance_ctrl     Pointer to the control block for the channel
+ *
+ * @retval  none
+ **********************************************************************************************************************/
+static void gmac_init_descriptors (gmac_instance_ctrl_t * const p_instance_ctrl)
+{
+    gmac_instance_descriptor_t * p_descriptor = NULL;
+    uint32_t i;
+
+    /* Initialize the receive descriptors */
+    for (i = 0; i < p_instance_ctrl->p_gmac_cfg->num_rx_descriptors; i++)
+    {
+        p_descriptor = &((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_rx_descriptors[i];
+
+        p_descriptor->des0 = GMAC_RDES0_OWN; /* receive status */
+        p_descriptor->des1 =                 /* Buffer 1 Byte Counte */
+                             p_instance_ctrl->p_gmac_cfg->ether_buffer_size;
+        p_descriptor->des2 =                 /* Buffer 1 Address */
+                             (uint32_t) p_instance_ctrl->p_gmac_cfg->pp_ether_buffers[i];
+
+        /* Offset for DMA */
+        if (p_descriptor->des2 <= TCM_CPU_ADR_END)
+        {
+            p_descriptor->des2 += TCM_DMA_ADR_OFFSET;
+        }
+
+        p_descriptor->des3 = 0;        /* Buffer 2 Address */
+    }
+
+    if (NULL != p_descriptor)
+    {
+        /* The last descriptor points back to the start */
+        p_descriptor->des1 |= GMAC_RDES1_RER; /* Receive End of Ring */
+
+        /* Initialize application receive descriptor pointer */
+        p_instance_ctrl->p_rx_descriptor =
+            &((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_rx_descriptors[0];
+    }
+
+    /* Initialize the transmit descriptors */
+    for (i = 0; i < p_instance_ctrl->p_gmac_cfg->num_tx_descriptors; i++)
+    {
+        p_descriptor = &((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_tx_descriptors[i];
+
+        p_descriptor->des0 = 0;        /* transmit control/status */
+        p_descriptor->des1 = 0;        /* Buffer 1 Byte Counte */
+        p_descriptor->des2 =           /* Buffer 1 Address */
+                             (uint32_t) p_instance_ctrl->p_gmac_cfg->pp_ether_buffers[p_instance_ctrl->p_gmac_cfg->
+                                                                                      num_rx_descriptors + i];
+
+        /* Offset for DMA */
+        if (p_descriptor->des2 <= TCM_CPU_ADR_END)
+        {
+            p_descriptor->des2 += TCM_DMA_ADR_OFFSET;
+        }
+
+        p_descriptor->des3 = 0;        /* Buffer 2 Address */
+    }
+
+    if (NULL != p_descriptor)
+    {
+        /* The last descriptor points back to the start */
+        p_descriptor->des0 |= GMAC_TDES0_TER; /* Transmit End of Ring */
+
+        /* Initialize application transmit descriptor pointer */
+        p_instance_ctrl->p_tx_descriptor =
+            &((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_tx_descriptors[0];
+    }
+}                                      /* End of function gmac_init_descriptors() */
+
+/********************************************************************************************************************//**
+ * Get Points to the buffer pointer used by the stack.
+ *
+ * @param[in]  p_instance_ctrl                              Ethernet driver control block.
+ * @param[out] p_buffer                                     Pointer to location to store the buffer pointer
+ * @param[out] p_buffer_size                                Pointer to location to store the buffer size
+ *
+ * @retval     FSP_SUCCESS                                  Processing completed successfully.
+ * @retval     FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL     Transmit buffer is not empty.
+ ***********************************************************************************************************************/
+static fsp_err_t gmac_buffer_get (gmac_instance_ctrl_t * const p_instance_ctrl,
+                                  void ** const                p_buffer,
+                                  uint32_t                   * p_buffer_size)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    /* When the Link up processing is completed */
+    /* All transmit buffers are full */
+    if (GMAC_TDES0_OWN == (p_instance_ctrl->p_tx_descriptor->des0 & GMAC_TDES0_OWN))
+    {
+        err = FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL;
+    }
+    else
+    {
+        /* Give application another buffer to work with */
+        if ((p_instance_ctrl->p_tx_descriptor->des2 >= TCM_DMA_ADR_ST) &&
+            (p_instance_ctrl->p_tx_descriptor->des2 <= TCM_DMA_ADR_END))
+        {
+            (*p_buffer) = (void *) (p_instance_ctrl->p_tx_descriptor->des2 - TCM_DMA_ADR_OFFSET);
+        }
+        else
+        {
+            (*p_buffer) = (void *) p_instance_ctrl->p_tx_descriptor->des2;
+        }
+
+        (*p_buffer_size) = p_instance_ctrl->p_gmac_cfg->ether_buffer_size;
+        err              = FSP_SUCCESS;
+    }
+
+    return err;
+}                                      /* End of function gmac_buffer_get() */
+
+/********************************************************************************************************************//**
+ * Configure the GMAC
+ *
+ * @param[in]   p_instance_ctrl         Ethernet driver control block.
+ * @param[in]   mode                    The operational mode is specified.
+ *                                      NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually
+ *                                      USE_MAGIC_PACKET_DETECT    (1) - Magic packet detection mode
+ *
+ * @retval      none
+ ***********************************************************************************************************************/
+static void gmac_config_ethernet (gmac_instance_ctrl_t const * const p_instance_ctrl, const uint8_t mode)
+{
+    R_GMAC_Type * p_reg_gmac;
+
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Check argument */
+    if ((NULL == p_instance_ctrl) || (GMAC_OPEN != p_instance_ctrl->open))
+    {
+        return;
+    }
+#endif
+
+    p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    /* Initialize Receive Descriptor List Address */
+    p_reg_gmac->Receive_Descriptor_List_Address =
+        (uint32_t) p_instance_ctrl->p_rx_descriptor & (~3U);
+
+    /* Initialize Transmit Descriptor List Address */
+    p_reg_gmac->Transmit_Descriptor_List_Address =
+        (uint32_t) p_instance_ctrl->p_tx_descriptor & (~3U);
+
+    /* Offset for DMA */
+    if (p_reg_gmac->Receive_Descriptor_List_Address <= TCM_CPU_ADR_END)
+    {
+        p_reg_gmac->Receive_Descriptor_List_Address += TCM_DMA_ADR_OFFSET;
+    }
+
+    if (p_reg_gmac->Transmit_Descriptor_List_Address <= TCM_CPU_ADR_END)
+    {
+        p_reg_gmac->Transmit_Descriptor_List_Address += TCM_DMA_ADR_OFFSET;
+    }
+
+    /* Initialize MAC Frame Filter */
+    p_reg_gmac->MAC_Frame_Filter_b.PR = /* promiscuous mode */
+                                        p_instance_ctrl->p_gmac_cfg->promiscuous;
+
+    /* Initialize MMC Receive/Transmit Interrupt Mask */
+    p_reg_gmac->MMC_Receive_Interrupt_Mask  = GMAC_MMC_RECEIVE_INTERRUPT_MASK_ALL_BIT;
+    p_reg_gmac->MMC_Transmit_Interrupt_Mask = GMAC_MMC_TRANSMIT_INTERRUPT_MASK_ALL_BIT;
+
+    /* Magic packet detection mode */
+    if (GMAC_USE_MAGIC_PACKET_DETECT == mode)
+    {
+        p_reg_gmac->Interrupt_Mask_b.PMTIM = 0; /* PMT Interrupt Enable */
+    }
+    /* Normal mode */
+    else
+    {
+        p_reg_gmac->Interrupt_Mask_b.PMTIM = 1; /* PMT Interrupt Disable */
+
+        /* Interrupt Enable Register */
+        p_reg_gmac->Interrupt_Enable =
+            GMAC_INTERRUPT_ENABLE_NIE |         /* Normal Interrupt Summary Enable */
+            GMAC_INTERRUPT_ENABLE_AIE |         /* Abnormal Interrupt Summary Enable */
+            GMAC_INTERRUPT_ENABLE_ERE |         /* Early Receive Interrupt Enable */
+            GMAC_INTERRUPT_ENABLE_FBE |         /* Fatal Bus Error Enable */
+            GMAC_INTERRUPT_ENABLE_ETE |         /* Early Transmit Interrupt Enable */
+            GMAC_INTERRUPT_ENABLE_RWE |         /* Receive Watchdog Timeout Enable */
+            GMAC_INTERRUPT_ENABLE_RUE |         /* Receive Buffer Unavailable Enable */
+            GMAC_INTERRUPT_ENABLE_RIE |         /* Receive Interrupt Enable */
+            GMAC_INTERRUPT_ENABLE_UNE |         /* Underflow Interrupt Enable */
+            GMAC_INTERRUPT_ENABLE_OVE |         /* Overflow Interrupt Enable */
+            GMAC_INTERRUPT_ENABLE_TIE;          /* Transmit Interrupt Enable */
+    }
+}                                               /* End of function gmac_config_ethernet() */
+
+/********************************************************************************************************************//**
+ * Description  : Determines PAUSE frame generation and handling. Uses the resolution Table 28B-3 of IEEE 802.3-2008.
+ *
+ * @param[in]   local_ability       local PAUSE capability (2 least significant bits)
+ * @param[in]   partner_ability     link partner PAUSE capability (2 least significant bits)
+ * @param[in]   p_tx_pause          pointer to location to store the result of the table lookup for transmit PAUSE.
+ *                                  1 is enable, 0 is disable.
+ * @param[in]   p_rx_pause          pointer to location to store the result of the table lookup for receive PAUSE.
+ *                                  1 is enable, 0 is disable.
+ *
+ * @retval      none
+ ***********************************************************************************************************************/
+static void gmac_pause_resolution (uint32_t const local_ability,
+                                   uint32_t const partner_ability,
+                                   uint32_t     * p_tx_pause,
+                                   uint32_t     * p_rx_pause)
+{
+    uint32_t i;
+    uint32_t ability_compare;
+
+    /*
+     * Arrange the bits so that they correspond to the Table 28B-3
+     * of the IEEE 802.3 values.
+     */
+    ability_compare =
+        (uint32_t) (((local_ability & GMAC_LINK_RESOLUTION_ABILITY_MASK) <<
+                     GMAC_LINK_RESOLUTION_LOCAL_ABILITY_BITSHIFT) |
+                    (partner_ability & GMAC_LINK_RESOLUTION_ABILITY_MASK));
+
+    /* Walk through the look up table */
+    for (i = 0; i < GMAC_PAUSE_TABLE_ENTRIES; i++)
+    {
+        if ((ability_compare & pause_resolution[i].mask) == pause_resolution[i].value)
+        {
+            (*p_tx_pause) = pause_resolution[i].transmit;
+            (*p_rx_pause) = pause_resolution[i].receive;
+
+            return;
+        }
+    }
+}                                      /* End of function gmac_pause_resolution() */
+
+/********************************************************************************************************************//**
+ * Description  : GMAC are configured.
+ *
+ * @param[in]   p_instance_ctrl         Ethernet driver control block.
+ * @param[in]   mac_addr                The MAC address of GMAC
+ * @param[in]   mode                    The operational mode is specified.
+ *                                      NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually
+ *                                      USE_MAGIC_PACKET_DETECT    (1) - Magic packet detection mode
+ *
+ * @retval      none
+ ***********************************************************************************************************************/
+static void gmac_configure_mac (gmac_instance_ctrl_t * const p_instance_ctrl,
+                                const uint8_t                mac_addr[],
+                                const uint8_t                mode)
+{
+    volatile R_GMAC_Type * p_reg_gmac;
+    uint32_t               mac_h;
+    uint32_t               mac_l;
+
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Check argument */
+    if ((NULL == p_instance_ctrl) || (GMAC_OPEN != p_instance_ctrl->open))
+    {
+        return;
+    }
+#endif
+
+    p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    /* Disable receive and transmit. */
+    gmac_disable(p_instance_ctrl);
+
+    /* Set MAC address */
+    mac_h = ((uint32_t) mac_addr[5] << 8) |
+            ((uint32_t) mac_addr[4] << 0);
+
+    mac_l = ((uint32_t) mac_addr[3] << 24) |
+            ((uint32_t) mac_addr[2] << 16) |
+            ((uint32_t) mac_addr[1] << 8) |
+            ((uint32_t) mac_addr[0] << 0);
+
+    p_reg_gmac->MAR0_H_b.ADDRHI = (uint16_t) mac_h;
+    p_reg_gmac->MAR0_L_b.ADDRLO = mac_l;
+
+    /* Set MAC address 1 */
+    uint8_t * mac_addr1 = ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_mac_address1;
+    if (0 != mac_addr1)
+    {
+        mac_h = ((uint32_t) mac_addr1[5] << 8) |
+                ((uint32_t) mac_addr1[4] << 0);
+
+        mac_l = ((uint32_t) mac_addr1[3] << 24) |
+                ((uint32_t) mac_addr1[2] << 16) |
+                ((uint32_t) mac_addr1[1] << 8) |
+                ((uint32_t) mac_addr1[0] << 0);
+
+        p_reg_gmac->MAR1_H_b.ADDRHI = (uint16_t) mac_h;
+        p_reg_gmac->MAR1_H_b.MBC    = 0;
+        p_reg_gmac->MAR1_H_b.SA     = 0;
+        p_reg_gmac->MAR1_H_b.AE     = 1;
+        p_reg_gmac->MAR1_L_b.ADDRLO = mac_l;
+    }
+
+    /* Set MAC address 2 */
+    uint8_t * mac_addr2 = ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->p_mac_address2;
+    if (0 != mac_addr2)
+    {
+        mac_h = ((uint32_t) mac_addr2[5] << 8) |
+                ((uint32_t) mac_addr2[4] << 0);
+
+        mac_l = ((uint32_t) mac_addr2[3] << 24) |
+                ((uint32_t) mac_addr2[2] << 16) |
+                ((uint32_t) mac_addr2[1] << 8) |
+                ((uint32_t) mac_addr2[0] << 0);
+
+        p_reg_gmac->MAR2_H_b.ADDRHI = (uint16_t) mac_h;
+        p_reg_gmac->MAR2_H_b.MBC    = 0;
+        p_reg_gmac->MAR2_H_b.SA     = 0;
+        p_reg_gmac->MAR2_H_b.AE     = 1;
+        p_reg_gmac->MAR2_L_b.ADDRLO = mac_l;
+    }
+
+    /* Initialize receive and transmit descriptors */
+    gmac_init_descriptors(p_instance_ctrl);
+
+    /* Perform reset of hardware interface configuration */
+
+    gmac_config_ethernet(p_instance_ctrl, mode);
+}                                      /* End of function gmac_configure_mac() */
+
+/*******************************************************************************************************************//**
+ * Disable receive and transmit
+ *
+ * @param[in] p_instance_ctrl           Ethernet driver control block.
+ *
+ * @retval      none
+ ***********************************************************************************************************************/
+static void gmac_disable (gmac_instance_ctrl_t * const p_instance_ctrl)
+{
+    volatile R_GMAC_Type * p_reg_gmac;
+
+    p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    p_reg_gmac->MAC_Configuration_b.TE = 0;
+    p_reg_gmac->MAC_Configuration_b.RE = 0;
+}                                      /* End of function gmac_disable() */
+
+/*******************************************************************************************************************//**
+ * Call user's callback function from R_GMAC_LinkProcess
+ *
+ * @param[in] p_instance_ctrl           Ethernet driver control block.
+ * @param[in] event                     Event code.
+ * @param[in] link_status               Link status.
+ *
+ * @retval      none
+ ***********************************************************************************************************************/
+void gmac_call_user_callback (gmac_instance_ctrl_t * p_instance_ctrl, ether_event_t event, gmac_port_mask_t link_status)
+{
+    ether_cfg_t const   * p_gmac_cfg = p_instance_ctrl->p_gmac_cfg;
+    ether_callback_args_t callback_arg;
+
+    if (NULL != p_instance_ctrl->p_callback)
+    {
+        callback_arg.channel      = p_gmac_cfg->channel;
+        callback_arg.event        = event;
+        callback_arg.status_ether = 0;
+        callback_arg.status_link  = link_status;
+        callback_arg.p_context    = p_gmac_cfg->p_context;
+
+        gmac_call_callback(p_instance_ctrl, &callback_arg);
+    }
+}                                      /* End of function gmac_call_user_callback() */
+
+/*******************************************************************************************************************//**
+ * Run Link process by port
+ *
+ * @param[in] p_instance_ctrl       Ethernet driver control block.
+ * @param[in] port                  The port number.
+ *
+ * @retval     FSP_SUCCESS                      Processing completed successfully.
+ * @retval     FSP_ERR_ASSERTION                Pointer to ETHER control block or configuration structure is NULL.
+ * @retval     FSP_ERR_NOT_OPEN                 The control block has not been opened.
+ * @retval     FSP_ERR_ETHER_ERROR_LINK         Auto-negotiation is not completed, and reception is not enabled.
+ ***********************************************************************************************************************/
+static fsp_err_t gmac_link_process (gmac_instance_ctrl_t * p_instance_ctrl, uint32_t port)
+{
+    fsp_err_t          err = FSP_SUCCESS;
+    gmac_link_change_t link_change;
+    gmac_port_mask_t   port_status = g_gmac_port_mask[port];
+
+    link_change = gmac_link_change_check(p_instance_ctrl, port);
+
+    /* When the change status is Link-up */
+    if (GMAC_LINK_CHANGE_LINK_UP == link_change)
+    {
+        err = gmac_do_link(p_instance_ctrl, port);
+        if (FSP_SUCCESS == err)
+        {
+            p_instance_ctrl->link_establish_status |= port_status;
+
+            gmac_call_user_callback(p_instance_ctrl, ETHER_EVENT_LINK_ON, port_status);
+        }
+        else
+        {
+            /* When PHY auto-negotiation is not completed */
+            p_instance_ctrl->link_establish_status &= ~port_status;
+        }
+    }
+    /* When the change status is Link-down */
+    else if (GMAC_LINK_CHANGE_LINK_DOWN == link_change)
+    {
+        p_instance_ctrl->link_establish_status &= ~port_status; // the establesh status is down
+
+        gmac_call_user_callback(p_instance_ctrl, ETHER_EVENT_LINK_OFF, port_status);
+
+        err = FSP_ERR_ETHER_ERROR_LINK;
+    }
+    /* When the change status is no change */
+    else
+    {
+        /* when the previous link status is Link-up and the establesh status is down */
+        if ((0 != (p_instance_ctrl->previous_link_status & port_status)) &&
+            (0 == (p_instance_ctrl->link_establish_status & port_status)))
+        {
+            err = gmac_do_link(p_instance_ctrl, port);
+            if (FSP_SUCCESS == err)
+            {
+                p_instance_ctrl->link_establish_status |= port_status; // the establesh status is up
+
+                gmac_call_user_callback(p_instance_ctrl, ETHER_EVENT_LINK_ON, port_status);
+            }
+        }
+        else
+        {
+            /* no operation */
+        }
+    }
+
+    return err;
+}                                      /* End of function gmac_link_process() */
+
+/*******************************************************************************************************************//**
+ * Check Link status change
+ *
+ * @param[in] p_instance_ctrl       Ethernet driver control block.
+ * @param[in] port                  The port number.
+ *
+ * @retval     GMAC_LINK_CHANGE_LINK_UP         Change from link down to link up.
+ * @retval     GMAC_LINK_CHANGE_LINK_DOWN       Change from link down to link up.
+ * @retval     GMAC_LINK_CHANGE_NO_CHANGE       No change link status.
+ ***********************************************************************************************************************/
+static gmac_link_change_t gmac_link_change_check (gmac_instance_ctrl_t * p_instance_ctrl, uint32_t port)
+{
+    gmac_link_change_t link_change = GMAC_LINK_CHANGE_NO_CHANGE;
+    gmac_port_mask_t   port_status = g_gmac_port_mask[port];
+    fsp_err_t          err;
+
+    if (GMAC_PHYLINK_ENABLE == ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->phylink)
+    {
+        if (0 != (p_instance_ctrl->link_status & port_status))
+        {
+            /* When becoming Link up */
+            if (0 == (p_instance_ctrl->previous_link_status & port_status))
+            {
+                /* When the previous link status is Link-down, the change status is Link-up */
+                link_change = GMAC_LINK_CHANGE_LINK_UP;
+
+                /* Update previous link status */
+                p_instance_ctrl->previous_link_status |= port_status;
+            }
+        }
+        else
+        {
+            /* When becoming Link down */
+            if (0 != (p_instance_ctrl->previous_link_status & port_status))
+            {
+                /* When the previous link status is Link-up, the change status is Link-down */
+                link_change = GMAC_LINK_CHANGE_LINK_DOWN;
+
+                /* Update previous link status */
+                p_instance_ctrl->previous_link_status &= ~port_status;
+            }
+        }
+    }
+    else
+    {
+        err = gmac_link_status_check(p_instance_ctrl, port);
+
+        /* The state of the link status in PHY-LSI is confirmed and Link Up/Down is judged. */
+        if (FSP_SUCCESS == err)
+        {
+            /* When becoming Link-up */
+            if (0 == (p_instance_ctrl->previous_link_status & port_status))
+            {
+                /* When the previous link status is Link-down, the change status is Link-up */
+                link_change = GMAC_LINK_CHANGE_LINK_UP;
+
+                /* Update previous link status */
+                p_instance_ctrl->previous_link_status |= port_status;
+            }
+        }
+        else
+        {
+            /* When becoming Link-down */
+            if (0 != (p_instance_ctrl->previous_link_status & port_status))
+            {
+                /* When the previous link status is Link-up, the change status is Link-down */
+                link_change = GMAC_LINK_CHANGE_LINK_DOWN;
+
+                /* Update previous link status */
+                p_instance_ctrl->previous_link_status &= ~port_status;
+            }
+        }
+    }
+
+    return link_change;
+}                                      /* End of function gmac_link_change_check() */
+
+/*******************************************************************************************************************//**
+ * Determines the partner PHY capability through auto-negotiation process.
+ * The link abilities are handled to determine duplex, speed and flow control (PAUSE frames).
+ *
+ * @param[in] p_instance_ctrl           Pointer to the control block for the channel
+ * @param[in] port                      Port number
+ *
+ * @retval  FSP_SUCCESS                 Processing completed successfully.
+ * @retval  FSP_ERR_ASSERTION           Pointer to ETHER control block or configuration structure is NULL.
+ * @retval  FSP_ERR_NOT_OPEN            The control block has not been opened.
+ * @retval  FSP_ERR_ETHER_ERROR_LINK    Auto-negotiation of PHY-LSI is not completed
+ *                                      or result of Auto-negotiation is abnormal.
+ ***********************************************************************************************************************/
+static fsp_err_t gmac_do_link (gmac_instance_ctrl_t * const p_instance_ctrl, const uint32_t port)
+{
+    ether_phy_instance_t const *(*pp_phy_instance)[BSP_FEATURE_GMAC_MAX_PORTS];
+
+    fsp_err_t err = FSP_SUCCESS;
+#ifdef GMAC_IMPLEMENT_ETHSW
+    ethsw_link_speed_t speed;
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+
+#if (GMAC_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    GMAC_ERROR_RETURN(GMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Get the link status */
+    pp_phy_instance = ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->pp_phy_instance;
+
+    err = (*pp_phy_instance)[port]->p_api->linkPartnerAbilityGet((*pp_phy_instance)[port]->p_ctrl,
+                                                                 &p_instance_ctrl->link_speed_duplex,
+                                                                 &p_instance_ctrl->local_pause_bits,
+                                                                 &p_instance_ctrl->partner_pause_bits);
+#ifdef GMAC_IMPLEMENT_ETHSW
+    if (FSP_SUCCESS == err)
+    {
+        switch (p_instance_ctrl->link_speed_duplex)
+        {
+            /* Half duplex link */
+            case ETHER_PHY_LINK_SPEED_1000H:
+            {
+                speed = ETHSW_LINK_SPEED_1000H;
+                break;
+            }
+
+            case ETHER_PHY_LINK_SPEED_100H:
+            {
+                speed = ETHSW_LINK_SPEED_100H;
+                break;
+            }
+
+            case ETHER_PHY_LINK_SPEED_10H:
+            {
+                speed = ETHSW_LINK_SPEED_10H;
+                break;
+            }
+
+            /* Full duplex link */
+            case ETHER_PHY_LINK_SPEED_1000F:
+            {
+                speed = ETHSW_LINK_SPEED_1000F;
+                break;
+            }
+
+            case ETHER_PHY_LINK_SPEED_100F:
+            {
+                speed = ETHSW_LINK_SPEED_100F;
+                break;
+            }
+
+            case ETHER_PHY_LINK_SPEED_10F:
+            {
+                speed = ETHSW_LINK_SPEED_10F;
+                break;
+            }
+
+            default:
+            {
+                err = FSP_ERR_ETHER_ERROR_LINK;
+                break;
+            }
+        }
+    }
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+
+    if (FSP_SUCCESS == err)
+    {
+#ifdef GMAC_IMPLEMENT_ETHSW
+        ether_switch_instance_t const * p_ethsw_instance = ///< Pointer to ETHER_SWITCH instance
+                                                           ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)
+                                                           ->
+                                                           p_ethsw_instance;
+
+        err = R_ETHSW_SpeedCfg(p_ethsw_instance->p_ctrl, port, speed);
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+    }
+    else
+    {
+        err = FSP_ERR_ETHER_ERROR_LINK;
+    }
+
+    return err;
+}                                      /* End of function gmac_do_link() */
+
+/*******************************************************************************************************************//**
+ * Set the GMAC operation mode and enable transmission/reception.
+ *
+ * Note: The flow control cannot be used in the mode of transmitting and receiving via ETHSW.
+ *       Therefore, currently, the code for the flow control is left for compatibility with RA.
+ *       Operation is not guaranteed when the flow control is enabled.
+ *
+ * @param[in] p_instance_ctrl           Pointer to the control block for the channel
+ *
+ * @retval  none
+ ***********************************************************************************************************************/
+void gmac_configure_operation (gmac_instance_ctrl_t * const p_instance_ctrl)
+{
+    volatile R_GMAC_Type * p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    uint32_t transmit_pause_set = 0;
+    uint32_t receive_pause_set  = 0;
+    bool     full_duplex        = false;
+    uint32_t flow_control;
+
+    /* Initialize MAC Configuration */
+#ifdef GMAC_IMPLEMENT_ETHSW
+    {
+        p_reg_gmac->MAC_Configuration_b.PS  = 0; /* Port Selec: 1Gbps */
+        p_reg_gmac->MAC_Configuration_b.FES = 1; /* Speed: 100Mbps */
+        p_reg_gmac->MAC_Configuration_b.DM  = 1; /* Duplex Mode: Full-duple */
+    }
+#else                                            // GMAC_IMPLEMENT_ETHSW
+    {
+        switch (p_instance_ctrl->link_speed_duplex)
+        {
+            /* Half duplex link */
+            case ETHER_PHY_LINK_SPEED_1000H:
+            {
+                p_reg_gmac->MAC_Configuration_b.PS  = 0; /* Port Selec: 1Gbps */
+                p_reg_gmac->MAC_Configuration_b.FES = 1;
+                p_reg_gmac->MAC_Configuration_b.DM  = 0; /* Duplex Mode: Half-duple */
+                break;
+            }
+
+            case ETHER_PHY_LINK_SPEED_100H:
+            {
+                p_reg_gmac->MAC_Configuration_b.PS  = 1; /* Port Selec: 10Mbps or 100Mbps */
+                p_reg_gmac->MAC_Configuration_b.FES = 1; /* Speed Select: 100Mbps */
+                p_reg_gmac->MAC_Configuration_b.DM  = 0; /* Duplex Mode: Half-duple */
+                break;
+            }
+
+            case ETHER_PHY_LINK_SPEED_10H:
+            {
+                p_reg_gmac->MAC_Configuration_b.PS  = 1; /* Port Selec: 10Mbps or 100Mbps */
+                p_reg_gmac->MAC_Configuration_b.FES = 0; /* Speed Select: 10Mbps */
+                p_reg_gmac->MAC_Configuration_b.DM  = 0; /* Duplex Mode: Half-duple */
+                break;
+            }
+
+            /* Full duplex link */
+            case ETHER_PHY_LINK_SPEED_1000F:
+            {
+                p_reg_gmac->MAC_Configuration_b.PS  = 0; /* Port Selec: 1Gbps */
+                p_reg_gmac->MAC_Configuration_b.FES = 1;
+                p_reg_gmac->MAC_Configuration_b.DM  = 1; /* Duplex Mode: Full-duple */
+                full_duplex = true;
+                break;
+            }
+
+            case ETHER_PHY_LINK_SPEED_100F:
+            {
+                p_reg_gmac->MAC_Configuration_b.PS  = 1; /* Port Selec: 10Mbps or 100Mbps */
+                p_reg_gmac->MAC_Configuration_b.FES = 1; /* Speed Select: 100Mbps */
+                p_reg_gmac->MAC_Configuration_b.DM  = 1; /* Duplex Mode: Full-duple */
+                full_duplex = true;
+                break;
+            }
+
+            case ETHER_PHY_LINK_SPEED_10F:
+            {
+                p_reg_gmac->MAC_Configuration_b.PS  = 1; /* Port Selec: 10Mbps or 100Mbps */
+                p_reg_gmac->MAC_Configuration_b.FES = 0; /* Speed Select: 10Mbps */
+                p_reg_gmac->MAC_Configuration_b.DM  = 1; /* Duplex Mode: Full-duple */
+                full_duplex = true;
+                break;
+            }
+
+            /* Unknown */
+            default:
+            {
+                p_reg_gmac->MAC_Configuration_b.PS  = 0; /* Port Selec: 1Gbps */
+                p_reg_gmac->MAC_Configuration_b.FES = 1;
+                p_reg_gmac->MAC_Configuration_b.DM  = 1; /* Duplex Mode: Full-duple */
+                break;
+            }
+        }
+    }
+#endif                                 // GMAC_IMPLEMENT_ETHSW
+
+    /* When pause frame is used */
+    if ((ETHER_FLOW_CONTROL_ENABLE == p_instance_ctrl->p_gmac_cfg->flow_control) &&
+        (true == full_duplex))
+    {
+        /* pause frame can be used when  when passing through the switch */
+        /* NOTE: not confirmed this operation !!! */
+
+        flow_control = GMAC_FLOW_CONTROL_PT | /* Pause Time (b31-b16) */
+                       GMAC_FLOW_CONTROL_PLT; /* Pause Low Threshold */
+
+        /**
+         * Enable PAUSE for full duplex link depending on
+         * the pause resolution results
+         */
+        gmac_pause_resolution(p_instance_ctrl->local_pause_bits,
+                              p_instance_ctrl->partner_pause_bits,
+                              &transmit_pause_set,
+                              &receive_pause_set);
+
+        if (GMAC_PAUSE_XMIT_ON == transmit_pause_set)
+        {
+            /* Enable automatic PAUSE frame transmission */
+            flow_control |= GMAC_FLOW_CONTROL_TFE; /* Transmit Flow Control Enable */
+
+            p_reg_gmac->Operation_Mode_b.RFD = 2;  /* Threshold for Deactivating Flow Control = FULL - 3KB */
+            p_reg_gmac->Operation_Mode_b.RFA = 1;  /* Threshold for Activating Flow Control = FULL - 2KB */
+            p_reg_gmac->Operation_Mode_b.EFC = 1;  /* Enable HW Flow Control */
+        }
+
+        if (GMAC_PAUSE_RECV_ON == receive_pause_set)
+        {
+            /* Enable reception of PAUSE frames */
+            flow_control |= GMAC_FLOW_CONTROL_RFE; /* Receive Flow Control Enable */
+        }
+
+        p_reg_gmac->Flow_Control = flow_control;
+    }
+    /* When pause frame is not used */
+    else
+    {
+        p_reg_gmac->Operation_Mode_b.EFC = 0;
+        p_reg_gmac->Flow_Control         = 0;
+    }
+
+    /* Initialize Operation Mode */
+    p_reg_gmac->Operation_Mode_b.RSF = 1; /* Receive Store and Forward */
+    p_reg_gmac->Operation_Mode_b.TSF = 1; /* Transmit Store and Forward */
+    p_reg_gmac->Operation_Mode_b.SR  = 1; /* Start or Stop Receive */
+    p_reg_gmac->Operation_Mode_b.ST  = 1; /* Start or Stop Transmission Command */
+
+    /* CRC Stripping for Type Frames */
+    p_reg_gmac->MAC_Configuration_b.CST = 1;
+
+    /* Automatic Pad or CRC Stripping */
+    p_reg_gmac->MAC_Configuration_b.ACS = 1;
+
+    /* Enable receive and transmit. */
+    p_reg_gmac->MAC_Configuration_b.RE = 1;
+    p_reg_gmac->MAC_Configuration_b.TE = 1;
+}
+
+/*******************************************************************************************************************//**
+ * The magic packet detection is permitted.
+ *
+ * @param[in]   p_instance_ctrl             Pointer to the control block for the channel
+ *
+ * @retval      non
+ ***********************************************************************************************************************/
+void gmac_magic_packet_detection (gmac_instance_ctrl_t * const p_instance_ctrl)
+{
+    volatile R_GMAC_Type * p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    /* The magic packet detection is permitted. */
+    p_reg_gmac->PMT_Control_Status =
+        GMAC_PMT_CONTROL_STATUS_MGKPKTEN | /* Magic Packet Enable */
+        GMAC_PMT_CONTROL_STATUS_PWRDWN;    /* Power Down */
+
+    /* Because data is not transmitted for the magic packet detection waiting,
+     * only the reception is permitted. */
+    p_reg_gmac->MAC_Configuration_b.RE = 1;
+}
+
+/*******************************************************************************************************************//**
+ * The magic packet detection is permitted.
+ *
+ * @param[in]   p_instance_ctrl             Pointer to the control block for the channel
+ *
+ * @retval      1: Magic Packet detection is enabled.
+ *              0: Magic Packet detection is disabled.
+ ***********************************************************************************************************************/
+static uint8_t gmac_check_magic_packet_detection_bit (gmac_instance_ctrl_t const * const p_instance_ctrl)
+{
+    uint8_t ret = 0;
+
+    volatile R_GMAC_Type * p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    if (1 == p_reg_gmac->PMT_Control_Status_b.MGKPKTEN)
+    {
+        ret = 1;
+    }
+    else
+    {
+        ret = 0;
+    }
+
+    return ret;
+}                                      /* End of function gmac_check_magic_packet_detection_bit() */
+
+/*******************************************************************************************************************//**
+ * Verifies the Etherent link is up or not.
+ *
+ * @param[in] p_instance_ctrl   Pointer to the control block for the channel
+ * @param[in] port              Port number
+ *
+ * @retval  FSP_SUCCESS:                  Link is up
+ * @retval  FSP_ERR_ETHER_ERROR_LINK      Link is down
+ * @retval  FSP_ERR_ETHER_PHY_ERROR_LINK  Initialization of PHY-LSI failed.
+ * @retval  FSP_ERR_INVALID_ARGUMENT      The ether_phy driver for the specified port cannot be used.
+ **********************************************************************************************************************/
+static fsp_err_t gmac_link_status_check (gmac_instance_ctrl_t const * const p_instance_ctrl, uint32_t port)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    fsp_err_t link_status;
+
+    ether_phy_instance_t const *(*pp_phy_instance)[BSP_FEATURE_GMAC_MAX_PORTS];
+
+    pp_phy_instance = ((gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend)->pp_phy_instance;
+
+    if (NULL == (*pp_phy_instance)[port])
+    {
+        return FSP_ERR_INVALID_ARGUMENT;
+    }
+
+    link_status = (*pp_phy_instance)[port]->p_api->linkStatusGet((*pp_phy_instance)[port]->p_ctrl);
+
+    if (FSP_ERR_ETHER_PHY_ERROR_LINK == link_status)
+    {
+        /* Link is down */
+        err = FSP_ERR_ETHER_ERROR_LINK;
+    }
+    else
+    {
+        /* Link is up */
+        err = FSP_SUCCESS;
+    }
+
+    return err;
+}                                      /* End of function gmac_link_status_check() */
+
+#ifdef GMAC_IMPLEMENT_ETHSW
+
+/*******************************************************************************************************************//**
+ * Callback function for link status change from switch
+ *
+ * @param[in] p_arg     Pointer to the callback parameter
+ *
+ * @retval  non
+ **********************************************************************************************************************/
+void gmac_callback_ethsw (ether_switch_callback_args_t * const p_arg)
+{
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) p_arg->p_context;
+
+    if (0 != p_instance_ctrl)
+    {
+        p_instance_ctrl->link_status = (gmac_port_mask_t) p_arg->status_link;
+    }
+}                                      /* End of function gmac_callback_ethsw() */
+
+#endif // GMAC_IMPLEMENT_ETHSW
+
+/*******************************************************************************************************************//**
+ * Calls user callback.
+ *
+ * @param[in]     p_instance_ctrl      Pointer to ether instance control block
+ * @param[in]     p_callback_args      Pointer to callback args
+ **********************************************************************************************************************/
+static void gmac_call_callback (gmac_instance_ctrl_t * p_instance_ctrl, ether_callback_args_t * p_callback_args)
+{
+    ether_callback_args_t args;
+
+    /* Store callback arguments in memory provided by user if available.  This allows callback arguments to be
+     * stored in non-secure memory so they can be accessed by a non-secure callback function. */
+    ether_callback_args_t * p_args = p_instance_ctrl->p_callback_memory;
+    if (NULL == p_args)
+    {
+        /* Store on stack */
+        p_args = &args;
+    }
+    else
+    {
+        /* Save current arguments on the stack in case this is a nested interrupt. */
+        args = *p_args;
+    }
+
+    p_args->channel      = p_instance_ctrl->p_gmac_cfg->channel;
+    p_args->event        = p_callback_args->event;
+    p_args->status_ether = p_callback_args->status_ether;
+    p_args->status_link  = p_callback_args->status_link;
+    p_args->p_context    = p_instance_ctrl->p_context;
+
+    /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */
+    p_instance_ctrl->p_callback(p_args);
+
+    if (NULL != p_instance_ctrl->p_callback_memory)
+    {
+        /* Restore callback memory in case this is a nested interrupt. */
+        *p_instance_ctrl->p_callback_memory = args;
+    }
+}                                      /* End of function gmac_call_callback() */
+
+/*******************************************************************************************************************//**
+ * Interrupt handler for SBD interrupts.
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void gmac_isr_sbd (void)
+{
+    ether_callback_args_t  callback_arg;
+    volatile R_GMAC_Type * p_reg_gmac;
+    uint32_t               status;
+    volatile uint32_t      dammy_read;
+
+    IRQn_Type              irq             = R_FSP_CurrentIrqGet();
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    status             = p_reg_gmac->Status;
+    p_reg_gmac->Status = status;
+
+    /* Dammy read for Countermeasure when the CPU clock is 400 or 800MHz */
+    dammy_read = p_reg_gmac->Status;
+    dammy_read = dammy_read;
+
+    /* Callback : Interrupt handler */
+    if (NULL != p_instance_ctrl->p_callback)
+    {
+        callback_arg.channel      = p_instance_ctrl->p_gmac_cfg->channel;
+        callback_arg.event        = ETHER_EVENT_SBD_INTERRUPT;
+        callback_arg.status_ether = status;
+        callback_arg.status_link  = 0;
+        callback_arg.p_context    = p_instance_ctrl->p_gmac_cfg->p_context;
+
+        gmac_call_callback(p_instance_ctrl, &callback_arg);
+    }
+}                                      /* End of function gmac_isr_sbd() */
+
+/*******************************************************************************************************************//**
+ * Interrupt handler for PMT interrupts.
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+void gmac_isr_pmt (void)
+{
+    ether_callback_args_t  callback_arg;
+    volatile R_GMAC_Type * p_reg_gmac;
+    uint32_t               pmt_control_status;
+
+    IRQn_Type              irq             = R_FSP_CurrentIrqGet();
+    gmac_instance_ctrl_t * p_instance_ctrl = (gmac_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    p_reg_gmac = (R_GMAC_Type *) p_instance_ctrl->p_reg_gmac;
+
+    pmt_control_status = p_reg_gmac->PMT_Control_Status;
+
+    /* Callback : Interrupt handler */
+    if (NULL != p_instance_ctrl->p_callback)
+    {
+        callback_arg.channel      = p_instance_ctrl->p_gmac_cfg->channel;
+        callback_arg.event        = ETHER_EVENT_PMT_INTERRUPT;
+        callback_arg.status_ether = pmt_control_status;
+        callback_arg.status_link  = 0;
+        callback_arg.p_context    = p_instance_ctrl->p_gmac_cfg->p_context;
+
+        gmac_call_callback(p_instance_ctrl, &callback_arg);
+    }
+
+    if ((GMAC_PMT_CONTROL_STATUS_MGKPRCVD == (GMAC_PMT_CONTROL_STATUS_MGKPRCVD & pmt_control_status)) ||
+        (GMAC_PMT_CONTROL_STATUS_PWRDWN != (GMAC_PMT_CONTROL_STATUS_PWRDWN & pmt_control_status)))
+    {
+        p_instance_ctrl->magic_packet = GMAC_MAGIC_PACKET_DETECTED;
+    }
+    else
+    {
+        p_reg_gmac->PMT_Control_Status =
+            GMAC_PMT_CONTROL_STATUS_MGKPKTEN | /* Magic Packet Enable */
+            GMAC_PMT_CONTROL_STATUS_PWRDWN;    /* Power Down */
+    }
+}                                              /* End of function gmac_isr_pmt() */
+
+/*******************************************************************************************************************//**
+ * Enable ICU
+ *
+ * @param[in] p_instance_ctrl   Pointer to the control block for the channel
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void gmac_enable_icu (gmac_instance_ctrl_t * const p_instance_ctrl)
+{
+    gmac_extend_cfg_t * p_extend = (gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend;
+
+    /** Configure the Ethernet interrupt. */
+    R_BSP_IrqCfgEnable(p_instance_ctrl->p_gmac_cfg->irq,
+                       p_instance_ctrl->p_gmac_cfg->interrupt_priority,
+                       p_instance_ctrl);
+
+    R_BSP_IrqCfgEnable(p_extend->pmt_irq, p_extend->pmt_interrupt_priority, p_instance_ctrl);
+}                                      /* End of function gmac_enable_icu() */
+
+/*******************************************************************************************************************//**
+ * Disable ICU
+ *
+ * @param[in] p_instance_ctrl   Pointer to the control block for the channel
+ *
+ * @retval      none
+ **********************************************************************************************************************/
+static void gmac_disable_icu (gmac_instance_ctrl_t * const p_instance_ctrl)
+{
+    gmac_extend_cfg_t * p_extend = (gmac_extend_cfg_t *) p_instance_ctrl->p_gmac_cfg->p_extend;
+
+    R_BSP_IrqDisable(p_instance_ctrl->p_gmac_cfg->irq);
+    R_FSP_IsrContextSet(p_instance_ctrl->p_gmac_cfg->irq, NULL);
+
+    R_BSP_IrqDisable(p_extend->pmt_irq);
+    R_FSP_IsrContextSet(p_extend->pmt_irq, NULL);
+}                                      /* End of function gmac_disable_icu() */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_gpt/r_gpt.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_gpt/r_gpt.c
new file mode 100644
index 00000000..0c8a00fb
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_gpt/r_gpt.c
@@ -0,0 +1,1939 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_gpt.h"
+#include "r_gpt_cfg.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* "GPT" in ASCII, used to determine if channel is open. */
+#define GPT_OPEN                                         (0x00475054ULL)
+
+#define GPT_PRV_GTWP_RESET_VALUE                         (0xA500U)
+#define GPT_PRV_GTWP_WRITE_PROTECT                       (0xA51FU)
+
+#define GPT_PRV_GTIOR_STOP_LEVEL_BIT                     (6)
+#define GPT_PRV_GTIOR_INITIAL_LEVEL_BIT                  (4)
+
+#define GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END    (0x6U)
+#define GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END    (0x9U)
+
+#define GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH                (0x3U)
+
+#define GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER       (0x550000U)
+
+#define GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE             (0x80000000U)
+
+#define GPT_PRV_GTCCRA                                   (0U)
+#define GPT_PRV_GTCCRB                                   (1U)
+#define GPT_PRV_GTCCRC                                   (2U)
+#define GPT_PRV_GTCCRE                                   (3U)
+#define GPT_PRV_GTCCRD                                   (4U)
+#define GPT_PRV_GTCCRF                                   (5U)
+
+/* GPT_CFG_OUTPUT_SUPPORT_ENABLE is set to 2 to enable extra features. */
+#define GPT_PRV_EXTRA_FEATURES_ENABLED                   (2U)
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+/* Macro definition of GPT_INT4 */
+ #define GPT_INT4                                        (4)
+
+/* Define the GPT_INTERRUPT_SELECT_ENABLE macro */
+ #define GPT_INTERRUPT_SELECT_ENABLE(irq, source_selected, selected, function)                                  \
+    if ((irq) > FSP_INVALID_VECTOR)                                                                             \
+    {                                                                                                           \
+        if ((GPT_INT4) != (source_selected))                                                                    \
+        {                                                                                                       \
+            R_BSP_IrqGptSelectedSet((irq), (BSP_IRQ_GPT_SELECTED_EVENT_GPT_ ## selected));                      \
+        }                                                                                                       \
+        else                                                                                                    \
+        {                                                                                                       \
+            R_BSP_IrqGptCombinedTableSet((irq), (BSP_IRQ_GPT_COMBINED_EVENT_GPT_ ## selected), p_instance_ctrl, \
+                                         function);                                                             \
+            R_BSP_IrqGptCombinedMaskClear((irq), (BSP_IRQ_GPT_COMBINED_EVENT_GPT_ ## selected));                \
+        }                                                                                                       \
+    }
+
+/* Define the GPT_INTERRUPT_SELECT_DISABLE macro. */
+ #define GPT_INTERRUPT_SELECT_DISABLE(irq, source_selected, selected)                             \
+    if ((irq) > FSP_INVALID_VECTOR)                                                               \
+    {                                                                                             \
+        if ((GPT_INT4) != (source_selected))                                                      \
+        {                                                                                         \
+            R_BSP_IrqGptSelectedClear((irq));                                                     \
+        }                                                                                         \
+        else                                                                                      \
+        {                                                                                         \
+            R_BSP_IrqGptCombinedMaskSet((irq), (BSP_IRQ_GPT_COMBINED_EVENT_GPT_ ## selected));    \
+            R_BSP_IrqGptCombinedTableClear((irq), (BSP_IRQ_GPT_COMBINED_EVENT_GPT_ ## selected)); \
+        }                                                                                         \
+    }
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/* Duty cycle mode. */
+typedef enum e_gpt_duty_cycle_mode
+{
+    GPT_DUTY_CYCLE_MODE_REGISTER    = 0, // Duty cycle depends on compare match
+    GPT_DUTY_CYCLE_MODE_0_PERCENT   = 2, // Output low
+    GPT_DUTY_CYCLE_MODE_100_PERCENT = 3, // Output high
+} gpt_duty_cycle_mode_t;
+
+/* Count direction */
+typedef enum e_gpt_dir
+{
+    GPT_DIR_COUNT_DOWN = 0,
+    GPT_DIR_COUNT_UP   = 1
+} gpt_dir_t;
+
+typedef struct st_gpt_prv_duty_registers
+{
+    uint32_t gtccr_buffer;
+    uint32_t omdty;
+} gpt_prv_duty_registers_t;
+
+typedef enum e_gpt_prv_capture_event
+{
+    GPT_PRV_CAPTURE_EVENT_A,
+    GPT_PRV_CAPTURE_EVENT_B,
+} gpt_prv_capture_event_t;
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void      gpt_counter_initialize(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+static fsp_err_t r_gpt_open_cfg_check(timer_cfg_t const * const p_cfg);
+static void      gpt_hardware_initialize(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+
+static void gpt_common_open(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+
+static uint32_t gpt_clock_frequency_get(gpt_instance_ctrl_t * const p_instance_ctrl);
+
+static void gpt_hardware_events_disable(gpt_instance_ctrl_t * p_instance_ctrl);
+
+static void r_gpt_disable_irq(IRQn_Type irq);
+static void gpt_disable_interrupt(gpt_instance_ctrl_t * const p_instance_ctrl);
+
+static inline void r_gpt_write_protect_enable(gpt_instance_ctrl_t * const p_instance_ctrl);
+static inline void r_gpt_write_protect_disable(gpt_instance_ctrl_t * const p_instance_ctrl);
+
+/* Noinline attribute added to reduce code size for CM23 GCC build. */
+static void r_gpt_enable_irq(IRQn_Type const irq, uint32_t priority, void * p_context) __attribute__((noinline));
+static void gpt_enable_interrupt(gpt_instance_ctrl_t * const p_instance_ctrl);
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+static void gpt_calculate_duty_cycle(gpt_instance_ctrl_t * const p_instance_ctrl,
+                                     uint32_t const              duty_cycle_counts,
+                                     gpt_prv_duty_registers_t  * p_duty_reg);
+
+static uint32_t gpt_gtior_calculate(timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level);
+
+#endif
+
+static void r_gpt_call_callback(gpt_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture);
+
+/***********************************************************************************************************************
+ * ISR prototypes
+ **********************************************************************************************************************/
+void gpt_counter_overflow_isr(void);
+
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+void gpt_counter_underflow_isr(void);
+
+#endif
+void gpt_dead_time_isr(void);
+void gpt_capture_a_isr(void);
+void gpt_capture_b_isr(void);
+
+#if 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+
+/* Function for GPT_INT0-3 */
+void gpt_int_select_isr(void);
+
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/* GPT implementation of timer interface  */
+const timer_api_t g_timer_on_gpt =
+{
+    .open         = R_GPT_Open,
+    .stop         = R_GPT_Stop,
+    .start        = R_GPT_Start,
+    .reset        = R_GPT_Reset,
+    .enable       = R_GPT_Enable,
+    .disable      = R_GPT_Disable,
+    .periodSet    = R_GPT_PeriodSet,
+    .dutyCycleSet = R_GPT_DutyCycleSet,
+    .infoGet      = R_GPT_InfoGet,
+    .statusGet    = R_GPT_StatusGet,
+    .callbackSet  = R_GPT_CallbackSet,
+    .close        = R_GPT_Close,
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup GPT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open.
+ *
+ * GPT hardware does not support one-shot functionality natively.  When using one-shot mode, the timer will be stopped
+ * in an ISR after the requested period has elapsed.
+ *
+ * The GPT implementation of the general timer can accept a gpt_extended_cfg_t extension parameter.
+ *
+ * @retval FSP_SUCCESS                    Initialization was successful and timer has started.
+ * @retval FSP_ERR_ASSERTION              A required input pointer is NULL or the source divider is invalid.
+ * @retval FSP_ERR_ALREADY_OPEN           Module is already open.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED       timer_cfg_t::mode is ::TIMER_MODE_ONE_SHOT or timer_cfg_t::p_callback is not
+ *                                        NULL, but ISR is not enabled.  ISR must be enabled to use one-shot mode or
+ *                                        callback.
+ * @retval FSP_ERR_INVALID_MODE           Triangle wave PWM is only supported if GPT_CFG_OUTPUT_SUPPORT_ENABLE is 2.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_extend);
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT((p_cfg->source_div != 7U) && (p_cfg->source_div != 9U) && (p_cfg->source_div <= 10));
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED != GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    FSP_ERROR_RETURN(p_cfg->mode <= TIMER_MODE_PWM, FSP_ERR_INVALID_MODE);
+ #endif
+    FSP_ERROR_RETURN(GPT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+#endif
+
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+
+    /** mask_bit GPTunit0 0-6bit, GPTunit1 0-6bit, GPTunit2 0-3bit*/
+    if (p_cfg->channel <= GPT_CHANNEL_UNIT0_6)
+    {
+        p_instance_ctrl->channel_mask = (1U << p_cfg->channel);
+    }
+    else if ((GPT_CHANNEL_UNIT1_0 <= p_cfg->channel) && (p_cfg->channel <= GPT_CHANNEL_UNIT1_6))
+    {
+        p_instance_ctrl->channel_mask = (1U << (p_cfg->channel - GPT_CHANNEL_UNIT1_0));
+    }
+    else
+    {
+        p_instance_ctrl->channel_mask = (1U << (p_cfg->channel - GPT_CHANNEL_UNIT2_0));
+    }
+
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    if (p_cfg->channel < BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL)
+    {
+        p_instance_ctrl->channel_mask = (1U << p_cfg->channel % BSP_FEATURE_GPT_LLPP_CHANNEL_PER_UNIT);
+    }
+    else if ((BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL <= p_cfg->channel) &&
+             (p_cfg->channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL))
+    {
+        p_instance_ctrl->channel_mask = (1U << (p_cfg->channel - BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL));
+    }
+    else
+    {
+        p_instance_ctrl->channel_mask = (1U << (p_cfg->channel - BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL));
+    }
+#endif
+
+    /* Verify the configuration parameters are valid   */
+    fsp_err_t err = r_gpt_open_cfg_check(p_cfg);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Initialize control structure based on configurations. */
+    gpt_common_open(p_instance_ctrl, p_cfg);
+
+    gpt_hardware_initialize(p_instance_ctrl, p_cfg);
+
+    p_instance_ctrl->open = GPT_OPEN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops timer. Implements @ref timer_api_t::stop.
+ *
+ * @retval FSP_SUCCESS                 Timer successfully stopped.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Stop (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Stop timer */
+    p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Starts timer. Implements @ref timer_api_t::start.
+ *
+ * @retval FSP_SUCCESS                 Timer successfully started.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Start (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Start timer */
+    p_instance_ctrl->p_reg->GTSTR = p_instance_ctrl->channel_mask;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Resets the counter value to 0. Implements @ref timer_api_t::reset.
+ *
+ * @note This function also updates to the new period if no counter overflow has occurred since the last call to
+ * R_GPT_PeriodSet().
+ *
+ * @retval FSP_SUCCESS                 Counter value written successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Reset (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Clear timer counter. */
+    p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable.
+ *
+ * @retval FSP_SUCCESS                 External events successfully enabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Enable (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+    uint32_t             gtssr    = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    uint32_t             gtpsr    = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    uint32_t             gtcsr    = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+
+    /* OR with user settings. */
+    gtssr |= p_extend->start_source;
+    gtpsr |= p_extend->stop_source;
+    gtcsr |= p_extend->clear_source;
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Set the count sources. Ensure stop and clear sources are set before start source, and capture sources are set
+     * after start source. */
+    p_instance_ctrl->p_reg->GTPSR   = gtpsr;
+    p_instance_ctrl->p_reg->GTCSR   = gtcsr;
+    p_instance_ctrl->p_reg->GTSSR   = gtssr;
+    p_instance_ctrl->p_reg->GTICASR = p_extend->capture_a_source;
+    p_instance_ctrl->p_reg->GTICBSR = p_extend->capture_b_source;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable.
+ *
+ * @note The timer could be running after R_GPT_Disable(). To ensure it is stopped, call R_GPT_Stop().
+ *
+ * @retval FSP_SUCCESS                 External events successfully disabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Disable (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    gpt_hardware_events_disable(p_instance_ctrl);
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets period value provided. If the timer is running, the period will be updated after the next counter overflow.
+ * If the timer is stopped, this function resets the counter and updates the period.
+ * Implements @ref timer_api_t::periodSet.
+ *
+ * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register.
+ * If this function is called while the timer is running and a GPT overflow occurs during processing, the duty cycle
+ * will not be the desired 50% duty cycle until the counter overflow after processing completes.
+ *
+ * @retval FSP_SUCCESS                 Period value written successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Update period buffer register. The actual period is one cycle longer than the register value for saw waves
+     * and twice the register value for triangle waves. Reference section "General PWM Timer Cycle Setting
+     * Register (GTPR)". The setting passed to the configuration is expected to be half the desired period for
+     * triangle waves. */
+    uint32_t new_gtpr = period_counts - 1U;
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+    {
+        new_gtpr = period_counts;
+    }
+#endif
+
+    p_instance_ctrl->p_reg->GTPBR = new_gtpr;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* Set a 50% duty cycle so the period of the waveform on the output pin matches the requested period. */
+    if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode)
+    {
+        /* The  GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used (see
+         * Section "PWM Output Operating Mode" in the RZ microprocessor User's Manual for details). To get a duty cycle
+         * as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */
+        uint32_t duty_cycle_50_percent = (period_counts >> 1) - 1U;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_cycle_50_percent;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRE] = duty_cycle_50_percent;
+    }
+#endif
+
+    /* If the counter is not counting, update period register and reset counter. */
+    if (0U == p_instance_ctrl->p_reg->GTCR_b.CST)
+    {
+        p_instance_ctrl->p_reg->GTPR = new_gtpr;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+        p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER;
+#endif
+
+        p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
+    }
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets duty cycle on requested pin. Implements @ref timer_api_t::dutyCycleSet.
+ *
+ * Duty cycle is updated in the buffer register. The updated duty cycle is reflected after the next cycle end (counter
+ * overflow).
+ *
+ * @param[in] p_ctrl                   Pointer to instance control block.
+ * @param[in] duty_cycle_counts        Duty cycle to set in counts.
+ * @param[in] pin                      Use gpt_io_pin_t to select GPT_IO_PIN_GTIOCA, GPT_IO_PIN_GTIOCB, or
+ *                                     GPT_IO_PIN_GTIOCA_AND_GTIOCB.
+ *
+ * @retval FSP_SUCCESS                 Duty cycle updated successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL or the pin is not one of gpt_io_pin_t
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ * @retval FSP_ERR_INVALID_ARGUMENT    Duty cycle is larger than period.
+ * @retval FSP_ERR_UNSUPPORTED         GPT_CFG_OUTPUT_SUPPORT_ENABLE is 0.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
+{
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    uint32_t              tmp_pin         = pin & 3U;
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+ #if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(tmp_pin <= GPT_IO_PIN_GTIOCA_AND_GTIOCB);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(duty_cycle_counts <= (p_instance_ctrl->p_reg->GTPBR + 1), FSP_ERR_INVALID_ARGUMENT);
+ #endif
+
+    /* Set duty cycle. */
+    gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0};
+    gpt_calculate_duty_cycle(p_instance_ctrl, duty_cycle_counts, &duty_regs);
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Only update GTCCR if 0% or 100% duty is not requested */
+    if (!duty_regs.omdty)
+    {
+        uint32_t reg_offset = 2U;
+        if (0 != (pin & GPT_IO_PIN_GTIOCA_AND_GTIOCB))
+        {
+            p_instance_ctrl->p_reg->GTCCR[reg_offset]     = duty_regs.gtccr_buffer;
+            p_instance_ctrl->p_reg->GTCCR[reg_offset + 1] = duty_regs.gtccr_buffer;
+        }
+        else
+        {
+            p_instance_ctrl->p_reg->GTCCR[tmp_pin + reg_offset] = duty_regs.gtccr_buffer;
+        }
+    }
+
+    /* Read modify write bitfield access is used to update GTUDDTYC to make sure we don't clobber settings for the
+     * other pin. */
+
+    uint32_t gtuddtyc = p_instance_ctrl->p_reg->GTUDDTYC;
+    if (GPT_IO_PIN_GTIOCB != tmp_pin)
+    {
+        /* GTIOCA or both GTIOCA and GTIOCB. */
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtuddtyc &= ~R_GPT7_GTUDDTYC_OADTY_Msk;
+        gtuddtyc |= duty_regs.omdty << R_GPT7_GTUDDTYC_OADTY_Pos;
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtuddtyc &= (uint32_t) ~R_GPT09_0_GTUDDTYC_OADTY_Msk;
+        gtuddtyc |= duty_regs.omdty << R_GPT09_0_GTUDDTYC_OADTY_Pos;
+ #endif
+    }
+
+    if (GPT_IO_PIN_GTIOCA != tmp_pin)
+    {
+        /* GTIOCB or both GTIOCA and GTIOCB. */
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtuddtyc &= ~R_GPT7_GTUDDTYC_OBDTY_Msk;
+        gtuddtyc |= duty_regs.omdty << R_GPT7_GTUDDTYC_OBDTY_Pos;
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtuddtyc &= (uint32_t) ~R_GPT09_0_GTUDDTYC_OBDTY_Msk;
+        gtuddtyc |= duty_regs.omdty << R_GPT09_0_GTUDDTYC_OBDTY_Pos;
+ #endif
+    }
+
+    p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(duty_cycle_counts);
+    FSP_PARAMETER_NOT_USED(pin);
+
+    FSP_RETURN(FSP_ERR_UNSUPPORTED);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Get timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet.
+ *
+ * @retval FSP_SUCCESS                 Period, count direction, frequency, and ELC event written to caller's
+ *                                     structure successfully.(External clock(GTETRGA - GTETRGD) cannot be acquired.)
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_info was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_info);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Get and store period */
+    uint32_t gtpr          = p_instance_ctrl->p_reg->GTPR;
+    uint32_t period_counts = gtpr + 1;
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+    {
+        period_counts = gtpr;
+    }
+#endif
+    p_info->period_counts = period_counts;
+
+    /* Get and store clock frequency */
+    p_info->clock_frequency = gpt_clock_frequency_get(p_instance_ctrl);
+
+    /* Get and store clock counting direction. Read count direction setting */
+    p_info->count_direction = TIMER_DIRECTION_UP;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Get current timer status and store it in provided pointer p_status. Implements @ref timer_api_t::statusGet.
+ *
+ * @retval FSP_SUCCESS                 Current timer state and counter value set successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_status);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Get counter state. */
+    p_status->state = (timer_state_t) p_instance_ctrl->p_reg->GTCR_b.CST;
+
+    /* Get counter value */
+    p_status->counter = p_instance_ctrl->p_reg->GTCNT;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set counter value.
+ *
+ * @note Do not call this API while the counter is counting.  The counter value can only be updated while the counter
+ * is stopped.
+ *
+ * @retval FSP_SUCCESS                 Counter value updated.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ * @retval FSP_ERR_IN_USE              The timer is running.  Stop the timer before calling this function.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_CounterSet (timer_ctrl_t * const p_ctrl, uint32_t counter)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->GTCR_b.CST, FSP_ERR_IN_USE);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Set counter value */
+    p_instance_ctrl->p_reg->GTCNT = counter;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enable output for GTIOCA and/or GTIOCB.
+ *
+ * @retval FSP_SUCCESS                 Output is enabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_OutputEnable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    uint32_t gtior = p_instance_ctrl->p_reg->GTIOR;
+    if (GPT_IO_PIN_GTIOCB != pin)
+    {
+        /* GTIOCA or both GTIOCA and GTIOCB. */
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= R_GPT7_GTIOR_OAE_Msk;
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= R_GPT09_0_GTIOR_OAE_Msk;
+#endif
+    }
+
+    if (GPT_IO_PIN_GTIOCA != pin)
+    {
+        /* GTIOCB or both GTIOCA and GTIOCB. */
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= R_GPT7_GTIOR_OBE_Msk;
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= R_GPT09_0_GTIOR_OBE_Msk;
+#endif
+    }
+
+    p_instance_ctrl->p_reg->GTIOR = gtior;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disable output for GTIOCA and/or GTIOCB.
+ *
+ * @retval FSP_SUCCESS                 Output is disabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_OutputDisable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    uint32_t gtior = p_instance_ctrl->p_reg->GTIOR;
+    if (GPT_IO_PIN_GTIOCB != pin)
+    {
+        /* GTIOCA or both GTIOCA and GTIOCB. */
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior &= ~R_GPT7_GTIOR_OAE_Msk;
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior &= (uint32_t) ~R_GPT09_0_GTIOR_OAE_Msk;
+#endif
+    }
+
+    if (GPT_IO_PIN_GTIOCA != pin)
+    {
+        /* GTIOCB or both GTIOCA and GTIOCB. */
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior &= ~R_GPT7_GTIOR_OBE_Msk;
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior &= (uint32_t) ~R_GPT09_0_GTIOR_OBE_Msk;
+#endif
+    }
+
+    p_instance_ctrl->p_reg->GTIOR = gtior;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set A/D converter start request compare match value.
+ *
+ * @retval FSP_SUCCESS                 Counter value updated.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_AdcTriggerSet (timer_ctrl_t * const    p_ctrl,
+                               gpt_adc_compare_match_t which_compare_match,
+                               uint32_t                compare_match_value)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(p_instance_ctrl->p_cfg->channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Set A/D converter start request compare match value. */
+    volatile uint32_t * p_gtadtr = &p_instance_ctrl->p_reg->GTADTRA;
+    p_gtadtr[which_compare_match] = compare_match_value;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Updates the user callback with the option to provide memory for the callback argument structure.
+ * Implements @ref timer_api_t::callbackSet.
+ *
+ * @retval  FSP_SUCCESS                  Callback updated successfully.
+ * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_CallbackSet (timer_ctrl_t * const          p_ctrl,
+                             void (                      * p_callback)(timer_callback_args_t *),
+                             void const * const            p_context,
+                             timer_callback_args_t * const p_callback_memory)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(p_callback);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Store callback and context */
+    p_instance_ctrl->p_callback        = p_callback;
+    p_instance_ctrl->p_context         = p_context;
+    p_instance_ctrl->p_callback_memory = p_callback_memory;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close.
+ *
+ * @retval FSP_SUCCESS                 Successful close.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Close (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+    fsp_err_t             err             = FSP_SUCCESS;
+
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Clear open flag. */
+    p_instance_ctrl->open = 0U;
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Stop counter. */
+    p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
+
+    /* Disable output. */
+    p_instance_ctrl->p_reg->GTIOR = 0U;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    /* Disable interrupts. */
+    gpt_disable_interrupt(p_instance_ctrl);
+
+    return err;
+}
+
+/** @} (end addtogroup GPT) */
+
+/*******************************************************************************************************************//**
+ * Private Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Enables write protection.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block.
+ **********************************************************************************************************************/
+static inline void r_gpt_write_protect_enable (gpt_instance_ctrl_t * const p_instance_ctrl)
+{
+#if GPT_CFG_WRITE_PROTECT_ENABLE
+    p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_WRITE_PROTECT;
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Disables write protection.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block.
+ **********************************************************************************************************************/
+static inline void r_gpt_write_protect_disable (gpt_instance_ctrl_t * const p_instance_ctrl)
+{
+#if GPT_CFG_WRITE_PROTECT_ENABLE
+    p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_RESET_VALUE;
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Validates the configuration arguments for illegal combinations or options.
+ *
+ * @param[in]  p_cfg                      Pointer to timer configuration.
+ *
+ * @retval FSP_SUCCESS                    No configuration errors detected
+ * @retval FSP_ERR_ASSERTION              An input argument is invalid.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED       timer_cfg_t::mode is ::TIMER_MODE_ONE_SHOT or timer_cfg_t::p_callback is not
+ *                                        NULL, but ISR is not enabled.  ISR must be enabled to use one-shot mode or
+ *                                        callback.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device.
+ **********************************************************************************************************************/
+static fsp_err_t r_gpt_open_cfg_check (timer_cfg_t const * const p_cfg)
+{
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    FSP_ERROR_RETURN((p_cfg->channel <= GPT_CHANNEL_UNIT2_3), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    FSP_ERROR_RETURN((p_cfg->channel < BSP_FEATURE_GPT_CHANNEL), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+ #endif
+
+    if ((p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode))
+    {
+        FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
+    }
+
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* Callback is required if underflow interrupt is enabled. */
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend;
+
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+    if (NULL != p_pwm_cfg)
+    {
+        if (p_pwm_cfg->trough_irq >= 0)
+        {
+            FSP_ASSERT(NULL != p_cfg->p_callback);
+        }
+    }
+ #endif
+#else
+    FSP_PARAMETER_NOT_USED(p_cfg);
+#endif
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Initializes control structure based on configuration.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block.
+ * @param[in]  p_cfg                   Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void gpt_common_open (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    /* Initialize control structure.  */
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    /* If callback is not null or timer mode is one shot, make sure the IRQ is enabled and store callback in the
+     *  control block.
+     *  @note The GPT hardware does not support one-shot mode natively.  To support one-shot mode, the timer will be
+     *  stopped and cleared using software in the ISR. *//* Determine if this is a 32-bit or a 16-bit timer. */
+    p_instance_ctrl->variant = TIMER_VARIANT_16_BIT;
+    if (0U != (p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_32BIT_CHANNEL_MASK))
+    {
+        p_instance_ctrl->variant = TIMER_VARIANT_32_BIT;
+    }
+
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+
+    /* Save register base address. */
+    uint32_t base_address;
+    if (p_cfg->channel <= GPT_CHANNEL_UNIT0_6)
+    {
+        base_address = (uint32_t) R_GPT0 + ((uint32_t) p_cfg->channel * ((uint32_t) R_GPT1 - (uint32_t) R_GPT0));
+    }
+    else if ((GPT_CHANNEL_UNIT1_0 <= p_cfg->channel) && (p_cfg->channel <= GPT_CHANNEL_UNIT1_6))
+    {
+        base_address = (uint32_t) R_GPT7 +
+                       (((uint32_t) p_cfg->channel - GPT_CHANNEL_UNIT1_0) * ((uint32_t) R_GPT8 - (uint32_t) R_GPT7));
+    }
+    else
+    {
+        base_address = (uint32_t) R_GPT14 +
+                       (((uint32_t) p_cfg->channel - GPT_CHANNEL_UNIT2_0) * ((uint32_t) R_GPT15 - (uint32_t) R_GPT14));
+    }
+
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+
+    /* Save register base address. */
+    uintptr_t base_address;
+ #if (BSP_FEATURE_GPT_LLPP1_BASE_CHANNEL != 0)
+    if (p_cfg->channel < BSP_FEATURE_GPT_LLPP1_BASE_CHANNEL)
+ #else
+    if (p_cfg->channel < BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL)
+ #endif
+    {
+        /* LLPP base address setting */
+        base_address = (uintptr_t) BSP_FEATURE_GPT_LLPP_BASE_ADDRESS +
+                       (uintptr_t) p_cfg->channel / BSP_FEATURE_GPT_LLPP_CHANNEL_PER_UNIT *
+                       BSP_FEATURE_GPT_LLPP_UNIT_ADDRESS_OFFSET +
+                       (uintptr_t) p_cfg->channel % BSP_FEATURE_GPT_LLPP_CHANNEL_PER_UNIT *
+                       BSP_FEATURE_GPT_LLPP_CHANNEL_ADDRESS_OFFSET;
+    }
+
+ #if (BSP_FEATURE_GPT_LLPP1_BASE_CHANNEL != 0)
+    else if ((p_cfg->channel >= BSP_FEATURE_GPT_LLPP1_BASE_CHANNEL) &&
+             (p_cfg->channel < BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL))
+    {
+        /* LLPP1 base address setting */
+        base_address = (uintptr_t) BSP_FEATURE_GPT_LLPP1_BASE_ADDRESS +
+                       ((uintptr_t) p_cfg->channel - BSP_FEATURE_GPT_LLPP1_BASE_CHANNEL) /
+                       BSP_FEATURE_GPT_LLPP_CHANNEL_PER_UNIT *
+                       BSP_FEATURE_GPT_LLPP1_UNIT_ADDRESS_OFFSET +
+                       (uintptr_t) p_cfg->channel % BSP_FEATURE_GPT_LLPP_CHANNEL_PER_UNIT *
+                       BSP_FEATURE_GPT_LLPP1_CHANNEL_ADDRESS_OFFSET;
+    }
+ #endif
+    else if ((p_cfg->channel >= BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL) &&
+             (p_cfg->channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL))
+    {
+        base_address =
+            (uintptr_t) BSP_FEATURE_GPT_NONSAFETY_BASE_ADDRESS +
+            ((uintptr_t) (p_cfg->channel - BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL) *
+             BSP_FEATURE_GPT_NONSAFETY_CHANNEL_ADDRESS_OFFSET);
+    }
+    else
+    {
+        base_address =
+            (uintptr_t) BSP_FEATURE_GPT_SAFETY_BASE_ADDRESS +
+            ((uintptr_t) (p_cfg->channel - BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL) *
+             BSP_FEATURE_GPT_SAFETY_CHANNEL_ADDRESS_OFFSET);
+    }
+#endif
+
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    p_instance_ctrl->p_reg = (R_GPT0_Type *) base_address;
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    p_instance_ctrl->p_reg = (R_GPT00_0_Type *) base_address;
+#endif
+#if 1U == BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE
+
+    /* Since it's a common channel, it keeps the previous value. */
+    p_instance_ctrl->p_reg_com = R_GPT_IC;
+#endif
+
+    /* Set callback and context pointers, if configured */
+    p_instance_ctrl->p_callback        = p_cfg->p_callback;
+    p_instance_ctrl->p_context         = p_cfg->p_context;
+    p_instance_ctrl->p_callback_memory = NULL;
+}
+
+/*******************************************************************************************************************//**
+ * Performs hardware initialization of the GPT.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ * @param[in]  p_cfg                  Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    /* Save pointer to extended configuration structure. */
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend;
+
+    /* Counter related initialization */
+    gpt_counter_initialize(p_instance_ctrl, p_cfg);
+
+    uint32_t gtuddtyc = 0U;
+    uint32_t gtior    = 0U;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* For one shot mode, the compare match buffer register must be loaded with a value that exceeds the timer
+     * cycle end value so that second compare match event would never occur and hence there will be only a
+     * single pulse.  Writing to the upper bits is ignored for 16-bit timers. */
+    gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0};
+
+    if (TIMER_MODE_PERIODIC == p_cfg->mode)
+    {
+        /* The  GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used (see
+         * Section "PWM Output Operating Mode" in the RZ microprocessor User's Manual for details). To get a duty cycle
+         * as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */
+        uint32_t duty_cycle_50_percent = (p_cfg->period_counts >> 1) - 1U;
+        duty_regs.gtccr_buffer = duty_cycle_50_percent;
+    }
+
+    if (p_cfg->mode >= TIMER_MODE_PWM)
+    {
+        gpt_calculate_duty_cycle(p_instance_ctrl, p_cfg->duty_cycle_counts, &duty_regs);
+    }
+
+    /* Set the compare match and compare match buffer registers based on previously calculated values. */
+    p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_regs.gtccr_buffer;
+    p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRE] = duty_regs.gtccr_buffer;
+
+    /* If the requested duty cycle is 0% or 100%, set this in the registers. */
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    gtuddtyc |= duty_regs.omdty << R_GPT7_GTUDDTYC_OADTY_Pos;
+    gtuddtyc |= duty_regs.omdty << R_GPT7_GTUDDTYC_OBDTY_Pos;
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    gtuddtyc |= duty_regs.omdty << R_GPT09_0_GTUDDTYC_OADTY_Pos;
+    gtuddtyc |= duty_regs.omdty << R_GPT09_0_GTUDDTYC_OBDTY_Pos;
+ #endif
+
+    /* Calculate GTIOR. */
+    if (p_extend->gtioca.output_enabled)
+    {
+        uint32_t gtioca_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtioca.stop_level);
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= gtioca_gtior << R_GPT7_GTIOR_GTIOA_Pos;
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= gtioca_gtior << R_GPT09_0_GTIOR_GTIOA_Pos;
+ #endif
+    }
+
+    if (p_extend->gtiocb.output_enabled)
+    {
+        uint32_t gtiocb_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtiocb.stop_level);
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= gtiocb_gtior << R_GPT7_GTIOR_GTIOB_Pos;
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= gtiocb_gtior << R_GPT09_0_GTIOR_GTIOB_Pos;
+ #endif
+    }
+#endif
+
+    /* It must be cleared before setting. When modifying the
+     * IVTT[2:0] bits, first set the IVTC[1:0] bits to 00b. */
+    p_instance_ctrl->p_reg->GTITC  = 0U;
+    p_instance_ctrl->p_reg->GTEITC = 0U;
+
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+    if (NULL != p_pwm_cfg)
+    {
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        p_instance_ctrl->p_reg->GTINTAD = ((uint32_t) p_pwm_cfg->output_disable << R_GPT7_GTINTAD_GRPDTE_Pos) |
+                                          ((uint32_t) p_pwm_cfg->poeg_link << R_GPT7_GTINTAD_GRP_Pos) |
+                                          ((uint32_t) p_pwm_cfg->adc_trigger << R_GPT7_GTINTAD_ADTRAUEN_Pos);
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        p_instance_ctrl->p_reg->GTINTAD = ((uint32_t) p_pwm_cfg->output_disable << R_GPT09_0_GTINTAD_GRPDTE_Pos) |
+                                          ((uint32_t) p_pwm_cfg->poeg_link << R_GPT09_0_GTINTAD_GRP_Pos) |
+                                          ((uint32_t) p_pwm_cfg->adc_trigger << R_GPT09_0_GTINTAD_ADTRAUEN_Pos);
+ #endif
+        p_instance_ctrl->p_reg->GTDVU = p_pwm_cfg->dead_time_count_up;
+
+        /* Set GTDTCR.TDE only if one of the dead time values is non-zero. */
+        uint32_t gtdtcr =
+            ((p_pwm_cfg->dead_time_count_up > 0) || (p_pwm_cfg->dead_time_count_down > 0));
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        p_instance_ctrl->p_reg->GTITC = ((uint32_t) p_pwm_cfg->interrupt_skip_source << R_GPT7_GTITC_IVTC_Pos) |
+                                        ((uint32_t) p_pwm_cfg->interrupt_skip_count << R_GPT7_GTITC_IVTT_Pos) |
+                                        ((uint32_t) p_pwm_cfg->interrupt_skip_adc << R_GPT7_GTITC_ADTAL_Pos);
+        p_instance_ctrl->p_reg->GTEITC =
+            ((uint32_t) p_pwm_cfg->interrupt_skip_source_ext1 << R_GPT7_GTEITC_EIVTC1_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_count_ext1 << R_GPT7_GTEITC_EIVTT1_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_source_ext2 <<
+                R_GPT7_GTEITC_EIVTC2_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_count_ext2 << R_GPT7_GTEITC_EIVTT2_Pos);
+        p_instance_ctrl->p_reg->GTEITLI1 =
+            ((uint32_t) p_pwm_cfg->interrupt_skip_func_ovf << R_GPT7_GTEITLI1_EITLV_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_func_unf << R_GPT7_GTEITLI1_EITLU_Pos);
+        p_instance_ctrl->p_reg->GTEITLI2 =
+            ((uint32_t) p_pwm_cfg->interrupt_skip_func_adc_a << R_GPT7_GTEITLI2_EADTAL_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_func_adc_b <<
+                R_GPT7_GTEITLI2_EADTBL_Pos);
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        p_instance_ctrl->p_reg->GTITC = ((uint32_t) p_pwm_cfg->interrupt_skip_source << R_GPT09_0_GTITC_IVTC_Pos) |
+                                        ((uint32_t) p_pwm_cfg->interrupt_skip_count << R_GPT09_0_GTITC_IVTT_Pos) |
+                                        ((uint32_t) p_pwm_cfg->interrupt_skip_adc << R_GPT09_0_GTITC_ADTAL_Pos);
+        p_instance_ctrl->p_reg->GTEITC =
+            ((uint32_t) p_pwm_cfg->interrupt_skip_source_ext1 << R_GPT09_0_GTEITC_EIVTC1_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_count_ext1 << R_GPT09_0_GTEITC_EIVTT1_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_source_ext2 <<
+                R_GPT09_0_GTEITC_EIVTC2_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_count_ext2 << R_GPT09_0_GTEITC_EIVTT2_Pos);
+        p_instance_ctrl->p_reg->GTEITLI1 =
+            ((uint32_t) p_pwm_cfg->interrupt_skip_func_ovf << R_GPT09_0_GTEITLI1_EITLV_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_func_unf << R_GPT09_0_GTEITLI1_EITLU_Pos);
+        p_instance_ctrl->p_reg->GTEITLI2 =
+            ((uint32_t) p_pwm_cfg->interrupt_skip_func_adc_a << R_GPT09_0_GTEITLI2_EADTAL_Pos) |
+            ((uint32_t) p_pwm_cfg->interrupt_skip_func_adc_b <<
+                R_GPT09_0_GTEITLI2_EADTBL_Pos);
+ #endif
+        p_instance_ctrl->p_reg->GTDVD = p_pwm_cfg->dead_time_count_down;
+
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+
+        /* GADTRm does not exist in the SAFETY area, so it is not accessed. */
+        if (0 ==
+            ((1U << (p_cfg->channel)) & (BSP_FEATURE_GPT_SAFETY_CHANNEL_MASK << BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)))
+        {
+            p_instance_ctrl->p_reg->GTADTRA = p_pwm_cfg->adc_a_compare_match;
+            p_instance_ctrl->p_reg->GTADTRB = p_pwm_cfg->adc_b_compare_match;
+        }
+
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        if (p_cfg->channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
+        {
+            p_instance_ctrl->p_reg->GTADTRA = p_pwm_cfg->adc_a_compare_match;
+            p_instance_ctrl->p_reg->GTADTRB = p_pwm_cfg->adc_b_compare_match;
+        }
+ #endif
+
+        /* If custom GTIOR settings are not provided, set gtioca_disable_settings and gtiocb_disable_settings. */
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= (uint32_t) (p_pwm_cfg->gtioca_disable_setting << R_GPT7_GTIOR_OADF_Pos);
+        gtior |= (uint32_t) (p_pwm_cfg->gtiocb_disable_setting << R_GPT7_GTIOR_OBDF_Pos);
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtior |= (uint32_t) (p_pwm_cfg->gtioca_disable_setting << R_GPT09_0_GTIOR_OADF_Pos);
+        gtior |= (uint32_t) (p_pwm_cfg->gtiocb_disable_setting << R_GPT09_0_GTIOR_OBDF_Pos);
+ #endif
+        p_instance_ctrl->p_reg->GTDTCR = gtdtcr;
+    }
+    else
+#endif
+    {
+        /* GTADTR* registers are unused if GTINTAD is cleared. */
+        p_instance_ctrl->p_reg->GTINTAD = 0U;
+        p_instance_ctrl->p_reg->GTDTCR  = 0U;
+
+        /* GTDVU, GTDVD, GTDBU, GTDBD, and GTSOTR are not used if GTDTCR is cleared. */
+    }
+
+    /* Configure the noise filter for the GTIOC pins. */
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    gtior |= (uint32_t) (p_extend->capture_filter_gtioca << R_GPT7_GTIOR_NFAEN_Pos);
+    gtior |= (uint32_t) (p_extend->capture_filter_gtiocb << R_GPT7_GTIOR_NFBEN_Pos);
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    gtior |= (uint32_t) (p_extend->capture_filter_gtioca << R_GPT09_0_GTIOR_NFAEN_Pos);
+    gtior |= (uint32_t) (p_extend->capture_filter_gtiocb << R_GPT09_0_GTIOR_NFBEN_Pos);
+#endif
+
+    /* Enable the compare match buffer. */
+    p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    if (TIMER_MODE_ONE_SHOT == p_cfg->mode)
+    {
+        /* In one shot mode, the output pin toggles when counting starts, then again when the period expires.
+         * The buffer is enabled to set the compare match to UINT32_MAX after the one shot pulse is output
+         * so that the pin level will not change if the period expires again before the timer is stopped in
+         * the interrupt.*/
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0U;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0U;
+    }
+#endif
+
+    /* Reset counter to 0. */
+    p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
+
+    /* Set the I/O control register. */
+    p_instance_ctrl->p_reg->GTIOR = gtior;
+
+    /* Configure duty cycle and force timer to count up. GTUDDTYC must be set, then cleared to force the count
+     * direction to be reflected when counting starts (see Section "General PWM Timer Count Direction
+     * and Duty Setting Register (GTUDDTYC)" in the RZ microprocessor User's Manual for details). */
+    p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 3U;
+    p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 1U;
+
+#if 1U == BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE
+    p_instance_ctrl->p_reg_com->GTIOCSEL |= p_extend->gtioc_isel;
+#endif
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    gpt_enable_interrupt(p_instance_ctrl);
+}
+
+/*******************************************************************************************************************//**
+ * Counter initialization of the GPT.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ * @param[in]  p_cfg                  Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void gpt_counter_initialize (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend;
+
+    /* Power on GPT before setting any hardware registers. Make sure the counter is stopped before setting mode
+     * register, PCLK divisor register, and counter register. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+    R_BSP_MODULE_START(FSP_IP_GPT, p_cfg->channel);
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+    /* Initialize all registers that may affect operation of this driver to reset values.  Skip these since they
+     * affect all channels, and are initialized in GTCR and GTCNT: GTSTR, GTSTP, GTCLR. GTCR is set immediately after
+     * clearing the module stop bit to ensure the timer is stopped before proceeding with configuration. */
+    p_instance_ctrl->p_reg->GTWP  = GPT_PRV_GTWP_RESET_VALUE;
+    p_instance_ctrl->p_reg->GTCR  = 0U;
+    p_instance_ctrl->p_reg->GTST  = 0U;
+    p_instance_ctrl->p_reg->GTCNT = 0U;
+
+    /* GTPR, GTCCRn, GTIOR, GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTPBR, and GTUDDTYC are set by this driver. */
+
+    /* Initialization sets all register required for up counting as described in hardware manual
+     * (see Section "Counter Operation" in the RZ microprocessor User's Manual for details) and
+     * other registers required by the driver. */
+
+    /* Dividers for GPT are half the enum value. */
+    uint32_t gtcr_tpcs = p_cfg->source_div;
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    uint32_t gtcr = ((uint32_t) (p_extend->icds << R_GPT7_GTCR_ICDS_Pos) | (gtcr_tpcs << R_GPT7_GTCR_TPCS_Pos));
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    uint32_t gtcr = ((uint32_t) (p_extend->icds << R_GPT09_0_GTCR_ICDS_Pos) | (gtcr_tpcs << R_GPT09_0_GTCR_TPCS_Pos));
+#endif
+
+    /* Store period register setting. The actual period and is one cycle longer than the register value for saw waves
+     * and twice the register value for triangle waves. Reference section "General PWM Timer Cycle Setting
+     * Register (GTPR)". The setting passed to the configuration is expected to be half the desired period for
+     * triangle waves. */
+    uint32_t gtpr = p_cfg->period_counts - 1U;
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* Saw-wave PWM mode is set in GTCR.MD for all modes except TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM and
+     * TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM. */
+    if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+    {
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtcr |= ((uint32_t) p_cfg->mode << R_GPT7_GTCR_MD_Pos);
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        gtcr |= ((uint32_t) p_cfg->mode << R_GPT09_0_GTCR_MD_Pos);
+ #endif
+        gtpr = p_cfg->period_counts;
+    }
+#endif
+
+    /* Counter must be stopped to update TPCS (see Section "General PWM Timer Control Register (GTCR)"
+     * in the RZ microprocessor User's Manual for details). */
+    p_instance_ctrl->p_reg->GTCR = gtcr;
+
+    gpt_hardware_events_disable(p_instance_ctrl);
+
+    /* Configure the up/down count sources. These are not affected by enable/disable. */
+    p_instance_ctrl->p_reg->GTUPSR = p_extend->count_up_source;
+    p_instance_ctrl->p_reg->GTDNSR = p_extend->count_down_source;
+
+    /* Set period. The actual period is one cycle longer than the register value. Reference section 19.2.21
+     * "General PWM Timer Cycle Setting Register (GTPR)". */
+    p_instance_ctrl->p_reg->GTPBR = gtpr;
+    p_instance_ctrl->p_reg->GTPR  = gtpr;
+}
+
+/*******************************************************************************************************************//**
+ * Disables hardware events that would cause the timer to start, stop, clear, or capture.
+ *
+ * @param[in]  p_instance_ctrl         Instance control structure
+ **********************************************************************************************************************/
+static void gpt_hardware_events_disable (gpt_instance_ctrl_t * p_instance_ctrl)
+{
+    /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */
+    p_instance_ctrl->p_reg->GTSSR   = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    p_instance_ctrl->p_reg->GTPSR   = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    p_instance_ctrl->p_reg->GTCSR   = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    p_instance_ctrl->p_reg->GTICASR = GPT_SOURCE_NONE;
+    p_instance_ctrl->p_reg->GTICBSR = GPT_SOURCE_NONE;
+}
+
+/*******************************************************************************************************************//**
+ * Disables interrupt if it is a valid vector number.
+ *
+ * @param[in]  irq                     Interrupt number
+ **********************************************************************************************************************/
+static void r_gpt_disable_irq (IRQn_Type irq)
+{
+    /* Disable interrupts. */
+    if (irq >= 0)
+    {
+        R_BSP_IrqDisable(irq);
+        R_FSP_IsrContextSet(irq, NULL);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Configures and enables interrupt if it is a valid vector number.
+ *
+ * @param[in]  irq                     Interrupt number
+ * @param[in]  priority                NVIC priority of the interrupt
+ * @param[in]  p_context               The interrupt context is a pointer to data required in the ISR.
+ **********************************************************************************************************************/
+static void r_gpt_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_context)
+{
+    if (irq >= 0)
+    {
+        R_BSP_IrqCfgEnable(irq, priority, p_context);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Disable interrupts
+ *
+ * @param[in]  p_instance_ctrl           Instance control block
+ **********************************************************************************************************************/
+static void gpt_disable_interrupt (gpt_instance_ctrl_t * const p_instance_ctrl)
+{
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+    if (p_instance_ctrl->p_cfg->cycle_end_irq > FSP_INVALID_VECTOR)
+    {
+#if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        p_instance_ctrl->p_reg->GTINTAD &= ~(1U << R_GPT7_GTINTAD_GTINTPR_Pos);
+#elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+        p_instance_ctrl->p_reg->GTINTAD &= ~(1U << R_GPT09_0_GTINTAD_GTINTPR_Pos);
+#endif
+    }
+
+    if (p_extend->capture_a_irq > FSP_INVALID_VECTOR)
+    {
+        p_instance_ctrl->p_reg->GTINTAD_b.GTINTA = 0U;
+    }
+
+    if (p_extend->capture_b_irq > FSP_INVALID_VECTOR)
+    {
+        p_instance_ctrl->p_reg->GTINTAD_b.GTINTB = 0U;
+    }
+
+    if (p_extend->dead_time_irq > FSP_INVALID_VECTOR)
+    {
+        p_instance_ctrl->p_reg->GTINTAD_b.GRPDTE = 0U;
+    }
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Use the GPT_INTERRUPT_SELECT_DISABLE macro for disable the cycle end interrupt. */
+    GPT_INTERRUPT_SELECT_DISABLE(p_instance_ctrl->p_cfg->cycle_end_irq, p_extend->cycle_end_source_select, OVF);
+
+    /* Use the GPT_INTERRUPT_SELECT_DISABLE macro for disable interrupt capture a. */
+    GPT_INTERRUPT_SELECT_DISABLE(p_extend->capture_a_irq, p_extend->capture_a_source_select, CCMPA);
+
+    /* Use the GPT_INTERRUPT_SELECT_DISABLE macro for disable interrupt capture b. */
+    GPT_INTERRUPT_SELECT_DISABLE(p_extend->capture_b_irq, p_extend->capture_b_source_select, CCMPB);
+
+    /* Use the GPT_INTERRUPT_SELECT_DISABLE macro for disable interrupt deadtime error. */
+    GPT_INTERRUPT_SELECT_DISABLE(p_extend->dead_time_irq, p_extend->dead_time_error_source_select, DTE);
+#endif
+
+    r_gpt_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq);
+    r_gpt_disable_irq(p_extend->capture_a_irq);
+    r_gpt_disable_irq(p_extend->capture_b_irq);
+    r_gpt_disable_irq(p_extend->dead_time_irq);
+
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+    if (NULL != p_pwm_cfg)
+    {
+        if (p_pwm_cfg->trough_irq > FSP_INVALID_VECTOR)
+        {
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+            p_instance_ctrl->p_reg->GTINTAD &= ~(2U << R_GPT7_GTINTAD_GTINTPR_Pos);
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+            p_instance_ctrl->p_reg->GTINTAD &= ~(2U << R_GPT09_0_GTINTAD_GTINTPR_Pos);
+ #endif
+        }
+
+ #if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+        /* Use the GPT_INTERRUPT_SELECT_DISABLE macro for disable the trough interrupt. */
+        GPT_INTERRUPT_SELECT_DISABLE(p_pwm_cfg->trough_irq, p_extend->trough_source_select, UDF);
+ #endif
+
+        r_gpt_disable_irq(p_pwm_cfg->trough_irq);
+    }
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Enable interrupts
+ *
+ * @param[in]  p_instance_ctrl           Instance control block
+ **********************************************************************************************************************/
+static void gpt_enable_interrupt (gpt_instance_ctrl_t * const p_instance_ctrl)
+{
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Enable CPU interrupts if callback is not null.  Also enable interrupts for one shot mode.
+     *  @note The GPT hardware does not support one-shot mode natively. To support one-shot mode, the timer will be
+     *  stopped and cleared using software in the ISR. */
+    if (p_instance_ctrl->p_cfg->cycle_end_irq > FSP_INVALID_VECTOR)
+    {
+        p_instance_ctrl->p_reg->GTINTAD_b.GTINTPR |= 0x01U;
+    }
+
+    if (p_extend->capture_a_irq > FSP_INVALID_VECTOR)
+    {
+        p_instance_ctrl->p_reg->GTINTAD_b.GTINTA = 1U;
+    }
+
+    if (p_extend->capture_b_irq > FSP_INVALID_VECTOR)
+    {
+        p_instance_ctrl->p_reg->GTINTAD_b.GTINTB = 1U;
+    }
+
+    if (p_extend->dead_time_irq > FSP_INVALID_VECTOR)
+    {
+        p_instance_ctrl->p_reg->GTINTAD_b.GRPDTE = 1U;
+    }
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* GPT_INT select  and combine enable */
+
+    /* Use the GPT_INTERRUPT_SELECT_ENABLE macro for enable the cycle end interrupt. */
+    GPT_INTERRUPT_SELECT_ENABLE(p_instance_ctrl->p_cfg->cycle_end_irq,
+                                p_extend->cycle_end_source_select,
+                                OVF,
+                                gpt_counter_overflow_isr);
+
+    /* Use the GPT_INTERRUPT_SELECT_ENABLE macro for enable interrupt capture a. */
+    GPT_INTERRUPT_SELECT_ENABLE(p_extend->capture_a_irq, p_extend->capture_a_source_select, CCMPA, gpt_capture_a_isr);
+
+    /* Use the GPT_INTERRUPT_SELECT_ENABLE macro for enable interrupt capture b. */
+    GPT_INTERRUPT_SELECT_ENABLE(p_extend->capture_b_irq, p_extend->capture_b_source_select, CCMPB, gpt_capture_b_isr);
+
+    /* Use the GPT_INTERRUPT_SELECT_ENABLE macro for enable interrupt deadtime error. */
+    GPT_INTERRUPT_SELECT_ENABLE(p_extend->dead_time_irq, p_extend->dead_time_error_source_select, DTE,
+                                gpt_dead_time_isr);
+#endif
+
+    r_gpt_enable_irq(p_instance_ctrl->p_cfg->cycle_end_irq, p_instance_ctrl->p_cfg->cycle_end_ipl, p_instance_ctrl);
+    r_gpt_enable_irq(p_extend->capture_a_irq, p_extend->capture_a_ipl, p_instance_ctrl);
+    r_gpt_enable_irq(p_extend->capture_b_irq, p_extend->capture_b_ipl, p_instance_ctrl);
+    r_gpt_enable_irq(p_extend->dead_time_irq, p_extend->dead_time_ipl, p_instance_ctrl);
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+    if (NULL != p_pwm_cfg)
+    {
+        if (p_pwm_cfg->trough_irq > FSP_INVALID_VECTOR)
+        {
+            p_instance_ctrl->p_reg->GTINTAD_b.GTINTPR |= 0x02U;
+        }
+
+ #if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+        /* Use the GPT_INTERRUPT_SELECT_ENABLE macro for enable the trough interrupt. */
+        GPT_INTERRUPT_SELECT_ENABLE(p_pwm_cfg->trough_irq,
+                                    p_extend->trough_source_select,
+                                    UDF,
+                                    gpt_counter_underflow_isr);
+ #endif
+
+        r_gpt_enable_irq(p_pwm_cfg->trough_irq, p_pwm_cfg->trough_ipl, p_instance_ctrl);
+    }
+#endif
+}
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+/*******************************************************************************************************************//**
+ * Calculates duty cycle register values.  GTPBR must be set before entering this function.
+ *
+ * @param[in]  p_instance_ctrl         Instance control structure
+ * @param[in]  duty_cycle_counts       Duty cycle to set
+ * @param[out] p_duty_reg              Duty cycle register values
+ **********************************************************************************************************************/
+static void gpt_calculate_duty_cycle (gpt_instance_ctrl_t * const p_instance_ctrl,
+                                      uint32_t const              duty_cycle_counts,
+                                      gpt_prv_duty_registers_t  * p_duty_reg)
+{
+    /* Determine the current period. The actual period is one cycle longer than the register value for saw waves
+     * and twice the register value for triangle waves. Reference section "General PWM Timer Cycle Setting Buffer
+     * Register (GTPBR)". The setting passed to the configuration is expected to be half the desired duty cycle for
+     * triangle waves. */
+    uint32_t current_period = p_instance_ctrl->p_reg->GTPBR;
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    if (p_instance_ctrl->p_cfg->mode < TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+ #endif
+    {
+        current_period++;
+    }
+
+    /* 0% and 100% duty cycle are supported in OADTY/OBDTY. */
+    if (0U == duty_cycle_counts)
+    {
+        p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_0_PERCENT;
+    }
+    else if (duty_cycle_counts >= current_period)
+    {
+        p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_100_PERCENT;
+    }
+    else
+    {
+        uint32_t temp_duty_cycle = duty_cycle_counts;
+
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+        if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+        {
+            p_duty_reg->gtccr_buffer = temp_duty_cycle;
+        }
+        else
+ #endif
+        {
+            /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used (see
+             * Section "PWM Output Operating Mode" in the RZ microprocessor User's Manual for details). */
+            temp_duty_cycle--;
+            p_duty_reg->gtccr_buffer = temp_duty_cycle;
+        }
+    }
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Calculates clock frequency of GPT counter.  Divides GPT clock by GPT clock divisor.
+ *
+ * @param[in]  p_instance_ctrl           Instance control block
+ *
+ * @return     Clock frequency of the GPT counter.
+ **********************************************************************************************************************/
+static uint32_t gpt_clock_frequency_get (gpt_instance_ctrl_t * const p_instance_ctrl)
+{
+    uint32_t pclk_freq_hz;
+
+    /* Look up PCLK frequency and divide it by GPT PCLK divider. */
+    timer_source_div_t pclk_divisor = (timer_source_div_t) (p_instance_ctrl->p_reg->GTCR_b.TPCS);
+    if (0U < (p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_LLPP_CHANNEL_MASK))
+    {
+        pclk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKGPTL);
+    }
+    else
+    {
+        pclk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKM);
+    }
+
+    return pclk_freq_hz >> pclk_divisor;
+}
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+/*******************************************************************************************************************//**
+ * Calculates GTIOR settings for given mode and stop level.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block
+ * @param[in]  p_cfg                   Timer configuration
+ * @param[in]  level                   Output level after timer stops
+ **********************************************************************************************************************/
+static uint32_t gpt_gtior_calculate (timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level)
+{
+    /* The stop level is used as both the initial level and the stop level. */
+ #if 1U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    uint32_t gtior = R_GPT7_GTIOR_OAE_Msk | ((uint32_t) stop_level << R_GPT7_GTIOR_OADFLT_Pos) |
+                     ((uint32_t) stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT);
+ #elif 2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE
+    uint32_t gtior = R_GPT09_0_GTIOR_OAE_Msk | ((uint32_t) stop_level << R_GPT09_0_GTIOR_OADFLT_Pos) |
+                     ((uint32_t) stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT);
+ #endif
+    uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END;
+
+    if (TIMER_MODE_PWM == p_cfg->mode)
+    {
+        /* Use default: GTIOn is high at cycle end, then low at compare match. */
+    }
+
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    else if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+    {
+        gtion = GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH;
+    }
+ #endif
+    else
+    {
+        /* In one-shot mode, the output pin goes high after the first compare match (one cycle after the timer starts counting). */
+        if (GPT_PIN_LEVEL_LOW == stop_level)
+        {
+            gtion = GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END;
+        }
+    }
+
+    gtior |= gtion;
+
+    return gtior;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Calls user callback.
+ *
+ * @param[in]     p_ctrl     Pointer to GPT instance control block
+ * @param[in]     event      Event code
+ * @param[in]     capture    Event capture counts (if applicable)
+ **********************************************************************************************************************/
+static void r_gpt_call_callback (gpt_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture)
+{
+    timer_callback_args_t args;
+
+    /* Store callback arguments in memory provided by user if available.  This allows callback arguments to be
+     * stored in non-secure memory so they can be accessed by a non-secure callback function. */
+    timer_callback_args_t * p_args = p_ctrl->p_callback_memory;
+    if (NULL == p_args)
+    {
+        /* Store on stack */
+        p_args = &args;
+    }
+    else
+    {
+        /* Save current arguments on the stack in case this is a nested interrupt. */
+        args = *p_args;
+    }
+
+    p_args->event     = event;
+    p_args->capture   = capture;
+    p_args->p_context = p_ctrl->p_context;
+
+    /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */
+    p_ctrl->p_callback(p_args);
+
+    if (NULL != p_ctrl->p_callback_memory)
+    {
+        /* Restore callback memory in case this is a nested interrupt. */
+        *p_ctrl->p_callback_memory = args;
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Common processing for input capture interrupt.
+ *
+ * @param[in]  event  Which input capture event occurred
+ **********************************************************************************************************************/
+static void r_gpt_capture_common_isr (gpt_prv_capture_event_t event)
+{
+    GPT_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+#endif
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+    uint32_t              counter;
+
+    /* Get captured value. */
+    if (event == GPT_PRV_CAPTURE_EVENT_A)
+    {
+        counter = p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA];
+    }
+    else
+    {
+        counter = p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB];
+    }
+
+    /* If we captured a one-shot pulse, then disable future captures. */
+    if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+        /* Disable captures. */
+        gpt_hardware_events_disable(p_instance_ctrl);
+
+        /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
+        R_BSP_IrqClearPending(irq);
+    }
+
+    /* If a callback is provided, then call it with the captured counter value. */
+    if (NULL != p_instance_ctrl->p_callback)
+    {
+        r_gpt_call_callback(p_instance_ctrl,
+                            (timer_event_t) ((uint32_t) TIMER_EVENT_CAPTURE_A + (uint32_t) event),
+                            counter);
+    }
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+#endif
+
+    GPT_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+/*******************************************************************************************************************//**
+ * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void gpt_counter_overflow_isr (void)
+{
+    GPT_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+#endif
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* If one-shot mode is selected, stop the timer since period has expired. */
+    if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+        r_gpt_write_protect_disable(p_instance_ctrl);
+
+        p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
+
+        /* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */
+        p_instance_ctrl->p_reg->GTCNT                 = 0;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0;
+
+        r_gpt_write_protect_enable(p_instance_ctrl);
+
+        /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
+        R_BSP_IrqClearPending(irq);
+    }
+
+    if (NULL != p_instance_ctrl->p_callback)
+    {
+        r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_CYCLE_END, 0);
+    }
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+#endif
+    GPT_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+/*******************************************************************************************************************//**
+ * Only supported for asymmetric triangle-wave PWM. Notifies application of trough event.
+ **********************************************************************************************************************/
+void gpt_counter_underflow_isr (void)
+{
+    GPT_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+ #if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+ #endif
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Call user callback. */
+    r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_TROUGH, 0);
+
+ #if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+ #endif
+
+    GPT_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void gpt_dead_time_isr (void)
+{
+    GPT_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+#endif
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Call user callback. */
+    r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_DEAD_TIME, 0);
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+#endif
+
+    GPT_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture A source.
+ *
+ * Clears interrupt, disables captures if one-shot mode, and calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void gpt_capture_a_isr (void)
+{
+    r_gpt_capture_common_isr(GPT_PRV_CAPTURE_EVENT_A);
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture B source.
+ *
+ * Clears interrupt, disables captures if one-shot mode, and calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void gpt_capture_b_isr (void)
+{
+    r_gpt_capture_common_isr(GPT_PRV_CAPTURE_EVENT_B);
+}
+
+#if 1U == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a INT0-3.
+ *
+ * Executes each interrupt process according to the cause of the interrupt.
+ **********************************************************************************************************************/
+void gpt_int_select_isr (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Save pointer to extended configuration structure. */
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+ #endif
+
+    /* Clearing event state and executing ISR function. */
+    if (irq == p_extend->capture_a_irq)
+    {
+        gpt_capture_a_isr();
+    }
+    else if (irq == p_extend->capture_b_irq)
+    {
+        gpt_capture_b_isr();
+    }
+    else if (irq == p_instance_ctrl->p_cfg->cycle_end_irq)
+    {
+        gpt_counter_overflow_isr();
+    }
+    else if (irq == p_extend->dead_time_irq)
+    {
+        gpt_dead_time_isr();
+    }
+
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    else if (irq == p_pwm_cfg->trough_irq)
+    {
+        gpt_counter_underflow_isr();
+    }
+ #endif
+    else
+    {
+        /* Do Nothing */
+        ;
+    }
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+}
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ioport/r_ioport.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ioport/r_ioport.c
new file mode 100644
index 00000000..1f6d4cc3
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_ioport/r_ioport.c
@@ -0,0 +1,1269 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "r_ioport_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* "PORT" in ASCII, used to determine if the module is open */
+#define IOPORT_OPEN                (0x504F5254U)
+#define IOPORT_CLOSED              (0x00000000U)
+
+/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
+#define IOPORT_PRV_PORT_OFFSET     (8U)
+
+#define IOPORT_PRV_PORT_BITS       (0xFF00U)
+#define IOPORT_PRV_PIN_BITS        (0x00FFU)
+
+#define IOPORT_PRV_8BIT_MASK       (0x00FFU)
+
+/* Added definitions */
+#define IOPORT_PIN_NUM_MUX         (8U)
+#define IOPORT_REGION_SEL_SAFE     (0U)
+#define IOPORT_REGION_SEL_NSAFE    (1U)
+#define IOPORT_RSEL_MASK           (0x01U)
+#define IOPORT_PM_BIT_MASK         (0x0003U)
+
+#if BSP_FEATURE_IOPORT_PIN_PFC_TYPE == 3
+ #define IOPORT_PFC_BIT_MASK       (0x0000003FU)
+#else
+ #define IOPORT_PFC_BIT_MASK       (0x0000000FU)
+#endif
+
+#define IOPORT_DRTCL_BIT_MASK      (0x000000FFU)
+#define IOPORT_ELC_PEL_MASK        (0x80)
+#define IOOPRT_ELC_PGC_MASK        (0x88)
+#define IOPORT_ELC_PEL_PSM_HIGH    (0x20)
+
+/* Switch IOPORT register region either safety or non safety */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+ #define IOPORT_PRV_PORT_ADDRESS(region_sel)    (region_sel == 1 ? (R_PORT_SRN) : (R_PORT_SRS))
+#else
+ #define IOPORT_PRV_PORT_ADDRESS(region_sel)    (region_sel == 1 ? (R_PORT_NSR) : (R_PORT_SR))
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+#if BSP_FEATURE_IOPORT_PIN_PFC_TYPE == 3
+typedef struct st_ioport_cfg_data
+{
+    uint32_t p_reg    : 1;
+    uint32_t pm_reg   : 2;
+    uint32_t pmc_reg  : 1;
+    uint32_t pfc_reg  : 6;
+    uint32_t drct_reg : 6;
+    uint32_t rsel_reg : 1;
+    uint32_t reserved : 15;
+} ioport_cfg_data_t;
+#else
+typedef struct st_ioport_cfg_data
+{
+    uint32_t p_reg    : 1;
+    uint32_t pm_reg   : 2;
+    uint32_t pmc_reg  : 1;
+    uint32_t pfc_reg  : 4;
+    uint32_t drct_reg : 6;
+    uint32_t rsel_reg : 1;
+    uint32_t reserved : 17;
+} ioport_cfg_data_t;
+#endif
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void r_ioport_pins_config(const ioport_cfg_t * p_cfg);
+static void r_ioport_pin_set(bsp_io_port_pin_t pin, ioport_cfg_data_t * p_cfg_data);
+static void r_ioport_event_config(const ioport_extend_cfg_t * p_extend_cfg_data);
+static void r_ioport_pin_set_safety(R_PORT_COMMON_Type * p_ioport_regs,
+                                    bsp_io_port_pin_t    pin,
+                                    ioport_cfg_data_t  * p_cfg_data);
+
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+static void r_ioport_pin_set_non_safety(R_PORT_NS_COMMON_Type * p_ioport_regs,
+                                        bsp_io_port_pin_t       pin,
+                                        ioport_cfg_data_t     * p_cfg_data);
+
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/* IOPort Implementation of IOPort Driver  */
+const ioport_api_t g_ioport_on_ioport =
+{
+    .open                 = R_IOPORT_Open,
+    .close                = R_IOPORT_Close,
+    .pinsCfg              = R_IOPORT_PinsCfg,
+    .pinCfg               = R_IOPORT_PinCfg,
+    .pinEventInputRead    = R_IOPORT_PinEventInputRead,
+    .pinEventOutputWrite  = R_IOPORT_PinEventOutputWrite,
+    .pinRead              = R_IOPORT_PinRead,
+    .pinWrite             = R_IOPORT_PinWrite,
+    .portDirectionSet     = R_IOPORT_PortDirectionSet,
+    .portEventInputRead   = R_IOPORT_PortEventInputRead,
+    .portEventOutputWrite = R_IOPORT_PortEventOutputWrite,
+    .portRead             = R_IOPORT_PortRead,
+    .portWrite            = R_IOPORT_PortWrite,
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup IOPORT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes internal driver data, then calls pin configuration function to configure pins.
+ *
+ * @retval FSP_SUCCESS                  Pin configuration data written to the multiple registers
+ * @retval FSP_ERR_ASSERTION            NULL pointer
+ * @retval FSP_ERR_ALREADY_OPEN         Module is already open.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg)
+{
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data);
+    FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+#endif
+
+    /* Set driver status to open */
+    p_instance_ctrl->open = IOPORT_OPEN;
+
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    r_ioport_pins_config(p_cfg);
+
+    r_ioport_event_config(p_cfg->p_extend);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Resets IOPORT registers. Implements @ref ioport_api_t::close
+ *
+ * @retval FSP_SUCCESS             The IOPORT was successfully uninitialized
+ * @retval FSP_ERR_ASSERTION       p_ctrl was NULL
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ *
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl)
+{
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Set state to closed */
+    p_instance_ctrl->open = IOPORT_CLOSED;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Configures the functions of multiple pins by loading configuration data into the multiple registers.
+ * Implements @ref ioport_api_t::pinsCfg.
+ *
+ * This function initializes the supplied list of the multiple registers with the supplied values. This data can be generated
+ * by the Pins tab of the RZ/N2L Configuration editor or manually by the developer. Different pin configurations can be
+ * loaded for different situations such as low power modes and testing.
+ *
+ * @retval FSP_SUCCESS             Pin configuration data written to the multiple registers
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ * @retval FSP_ERR_ASSERTION       NULL pointer
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    r_ioport_pins_config(p_cfg);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg.
+ *
+ * @retval FSP_SUCCESS             Pin configured
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ * @retval FSP_ERR_ASSERTION       NULL pointer
+ *
+ * @note This function is re-entrant for different pins.
+ * This function will change the configuration of the pin with the new configuration. For example it is not possible
+ * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To
+ * achieve this the original settings with the required change will need to be written using this function.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    R_BSP_PinAccessEnable();
+
+    r_ioport_pin_set(pin, (ioport_cfg_data_t *) &cfg);
+
+    R_BSP_PinAccessDisable();
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Reads the level on a pin. Implements @ref ioport_api_t::pinRead.
+ *
+ * The level for the specifed pin will be reterned by PINm register.
+ *
+ * @retval FSP_SUCCESS             Pin read
+ * @retval FSP_ERR_ASSERTION       NULL pointer
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ *
+ * @note This function is re-entrant for different pins.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_pin_value);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    *p_pin_value = (bsp_io_level_t) R_BSP_FastPinRead(R_BSP_IoRegionGet(pin), pin);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Reads the value on an IO port. Implements @ref ioport_api_t::portRead.
+ *
+ * The specified port will be read, and the levels for all the pins will be returned by PINm register.
+ * Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds
+ * to pin 7, bit 6 to pin 6, and so on.
+ *
+ * @retval FSP_SUCCESS             Port read
+ * @retval FSP_ERR_ASSERTION       NULL pointer
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ *
+ * @note This function is re-entrant for different ports.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_port_value);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    R_PORT_COMMON_Type * p_ioport_regs;
+    ioport_size_t        safe_value;
+    ioport_size_t        nsafe_value;
+
+    /* Get port number */
+    uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET;
+
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (port_num > BSP_FEATURE_IOPORT_SELECTABLE_PORT_MAX)
+    {
+        /* Read the specified port states */
+        *p_port_value = (ioport_size_t) R_PORT_NSR->PIN[port_num];
+
+        return FSP_SUCCESS;
+    }
+#endif
+
+    /* Get the RSELP register value */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    ioport_size_t rselp_value = (ioport_size_t) R_PORT_SRS->RSELP[port_num];
+#else
+    ioport_size_t rselp_value = (ioport_size_t) R_PTADR->RSELP[port_num];
+#endif
+
+    /* Get the port register address in non safety region */
+    p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
+
+    /* Read the specified port states in non safety region */
+    nsafe_value = (ioport_size_t) (p_ioport_regs->PIN[port_num] & rselp_value);
+
+    /* Get the port register address in safety region */
+    p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE);
+
+    /* Read the specified port states in safety region */
+    safe_value = (ioport_size_t) (p_ioport_regs->PIN[port_num] & ~(rselp_value));
+
+    /* Read the specified port states */
+    *p_port_value = nsafe_value | safe_value;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite.
+ *
+ * The output value will be written to the specified port. Each bit in the value parameter corresponds to a bit
+ * on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on.
+ * Each bit in the mask parameter corresponds to a pin on the port.
+ *
+ * Only the bits with the corresponding bit in the mask value set will be updated.
+ * For example, value = 0x00FF, mask = 0x0003 results in only bits 0 and 1 being updated.
+ *
+ * @retval FSP_SUCCESS                  Port written to
+ * @retval FSP_ERR_INVALID_ARGUMENT     The port and/or mask not valid
+ * @retval FSP_ERR_NOT_OPEN             The module has not been opened
+ * @retval FSP_ERR_ASSERTION            NULL pointerd
+ *
+ * @note This function is re-entrant for different ports. This function makes use of the Pm register to atomically
+ * modify the levels on the specified pins on a port.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    R_PORT_COMMON_Type * p_ioport_regs;
+    ioport_size_t        temp_value;
+    ioport_size_t        write_mask;
+
+    /* mask value: lower word is valid, upper word is invalid */
+    mask &= IOPORT_PRV_8BIT_MASK;
+
+    /* Get port number */
+    uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET;
+
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (port_num > BSP_FEATURE_IOPORT_SELECTABLE_PORT_MAX)
+    {
+        /* Output data store of the specified pins sets to low output */
+        temp_value = (ioport_size_t) (R_PORT_NSR->P[port_num] & (~mask));
+
+        /* Write output data to P register of the specified pins */
+        R_PORT_NSR->P[port_num] = (uint8_t) (temp_value | (value & mask));
+
+        return FSP_SUCCESS;
+    }
+#endif
+
+    /* Get the RSELP register value */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    ioport_size_t rselp_value = (ioport_size_t) R_PORT_SRS->RSELP[port_num];
+#else
+    ioport_size_t rselp_value = (ioport_size_t) R_PTADR->RSELP[port_num];
+#endif
+
+    /* Set value to non safety region register */
+    write_mask = rselp_value & mask;
+    if (write_mask)
+    {
+        /* Get the port register address */
+        p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
+
+        /* Output data store of the specified pins sets to low output */
+        temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask));
+
+        /* Write output data to P register of the specified pins */
+        p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask));
+    }
+
+    /* Set value to safety region register */
+    write_mask = (ioport_size_t) ((~rselp_value) & mask);
+    if (write_mask)
+    {
+        /* Get the port register address */
+        p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE);
+
+        /* Output data store of the specified pins sets to low output */
+        temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask));
+
+        /* Write output data to P register of the specified pins */
+        p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask));
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite.
+ *
+ * @retval FSP_SUCCESS                  Pin written to
+ * @retval FSP_ERR_INVALID_ARGUMENT     The pin and/or level not valid
+ * @retval FSP_ERR_NOT_OPEN             The module has not been opene
+ * @retval FSP_ERR_ASSERTION            NULL pointerd
+ *
+ * @note This function is re-entrant for different pins. This function makes use of the Pm register to atomically
+ * modify the level on the specified pin on a port.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Get port and pin number */
+    uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET;
+    uint32_t pin_num  = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin);
+
+    /* Get the port register address */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    if (port_num > BSP_FEATURE_IOPORT_SELECTABLE_PORT_MAX)
+    {
+        /* Get the port register address */
+        R_PORT_NS_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+
+        /* Set output level to P register of the specified pin */
+        if (BSP_IO_LEVEL_LOW == level)
+        {
+            p_ioport_regs->P[port_num] &= (uint8_t) (~(1U << pin_num));
+        }
+        else
+        {
+            p_ioport_regs->P[port_num] |= (uint8_t) (1U << pin_num);
+        }
+    }
+    else
+    {
+        /* Get the port register address */
+        R_PORT_COMMON_Type * p_ioport_regs =
+            (IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PORT_SRS->RSELP[port_num] >> pin_num) &
+                                      IOPORT_RSEL_MASK)));
+
+        /* Set output level to P register of the specified pin */
+        if (BSP_IO_LEVEL_LOW == level)
+        {
+            p_ioport_regs->P[port_num] &= (uint8_t) (~(1U << pin_num));
+        }
+        else
+        {
+            p_ioport_regs->P[port_num] |= (uint8_t) (1U << pin_num);
+        }
+    }
+
+#else
+
+    /* Get the port register address */
+    R_PORT_COMMON_Type * p_ioport_regs = (IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PTADR->RSELP[port_num] >> pin_num) &
+                                                                   IOPORT_RSEL_MASK)));
+
+    /* Set output level to P register of the specified pin */
+    if (BSP_IO_LEVEL_LOW == level)
+    {
+        p_ioport_regs->P[port_num] &= (uint8_t) (~(1U << pin_num));
+    }
+    else
+    {
+        p_ioport_regs->P[port_num] |= (uint8_t) (1U << pin_num);
+    }
+#endif
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet().
+ *
+ * Multiple pins on a port can be set to inputs or outputs at once.
+ * Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to
+ * pin 7, bit 6 to pin 6, and so on. If a mask bit is set to 1 then the corresponding pin will be changed to
+ * an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of
+ * the pin will not be changed.
+ *
+ * @retval FSP_SUCCESS                 Port direction updated
+ * @retval FSP_ERR_INVALID_ARGUMENT    The port and/or mask not valid
+ * @retval FSP_ERR_NOT_OPEN            The module has not been opened
+ * @retval FSP_ERR_ASSERTION           NULL pointer
+ *
+ * @note This function is re-entrant for different ports.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl,
+                                     bsp_io_port_t         port,
+                                     ioport_size_t         direction_values,
+                                     ioport_size_t         mask)
+{
+    uint32_t pin_num;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(mask > (uint16_t) 0, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* mask value: lower word is valid, upper word is invalid */
+    mask &= IOPORT_PRV_8BIT_MASK;
+
+    for (pin_num = 0U; pin_num < IOPORT_PIN_NUM_MUX; pin_num++)
+    {
+        if (mask & (1U << pin_num))
+        {
+            /* Get port number */
+            uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET;
+
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+            if (port_num > BSP_FEATURE_IOPORT_SELECTABLE_PORT_MAX)
+            {
+                /* Get the port register address */
+                R_PORT_NS_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+
+                /* Set  */
+                uint16_t set_bits = (uint16_t) (direction_values & (IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+
+                /* Set the direction value */
+                uint16_t temp_value =
+                    (uint16_t) (p_ioport_regs->PM[port_num] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+                p_ioport_regs->PM[port_num] = temp_value | set_bits;
+            }
+            else
+            {
+                /* Get the port register address */
+                R_PORT_COMMON_Type * p_ioport_regs =
+                    (IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PORT_SRS->RSELP[port_num] >> pin_num) &
+                                              IOPORT_RSEL_MASK)));
+
+                /* Set  */
+                uint16_t set_bits = (uint16_t) (direction_values & (IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+
+                /* Set the direction value */
+                uint16_t temp_value =
+                    (uint16_t) (p_ioport_regs->PM[port_num] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+                p_ioport_regs->PM[port_num] = temp_value | set_bits;
+            }
+
+#else
+
+            /* Get the port register address */
+            R_PORT_COMMON_Type * p_ioport_regs =
+                (IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PTADR->RSELP[port_num] >> pin_num) &
+                                          IOPORT_RSEL_MASK)));
+
+            /* Set  */
+            uint16_t set_bits = (uint16_t) (direction_values & (IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+
+            /* Set the direction value */
+            uint16_t temp_value = (uint16_t) (p_ioport_regs->PM[port_num] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+            p_ioport_regs->PM[port_num] = temp_value | set_bits;
+#endif
+        }
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead().
+ *
+ * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port.
+ * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on.
+ *
+ * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read.
+ * Using the event system allows the captured data to be stored when it occurs and then read back at a later time.
+ *
+ * @retval FSP_SUCCESS              Port read
+ * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port
+ * @retval FSP_ERR_ASSERTION        NULL pointer
+ * @retval FSP_ERR_NOT_OPEN         The module has not been opened
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data)
+{
+    uint8_t portgroup = 0U;
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_event_data);
+    FSP_ERROR_RETURN((port == BSP_FEATURE_ELC_GROUP1_PORT_NUM) || (port == BSP_FEATURE_ELC_GROUP2_PORT_NUM),
+                     FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend;
+
+    /* Get register address */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    R_PORT_NS_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+#else
+    R_PORT_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+#endif
+
+    /* Get port group number for the specified port */
+    if (BSP_FEATURE_ELC_GROUP1_PORT_NUM == port)
+    {
+        portgroup = 0U;
+    }
+    else if (BSP_FEATURE_ELC_GROUP2_PORT_NUM == port)
+    {
+        portgroup = 1U;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* Read current value of buffer value from ELC_PDBF register for the specified port group */
+    *p_event_data =
+        (uint16_t) (p_ioport_regs->ELC_PDBF[portgroup].BY & elc_cfg->port_group_input_cfg[portgroup].pin_select);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead.
+ *
+ * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read.
+ * Using the event system allows the captured data to be stored when it occurs and then read back at a later time.
+ *
+ * @retval FSP_SUCCESS                  Pin read
+ * @retval FSP_ERR_ASSERTION            NULL pointer
+ * @retval FSP_ERR_NOT_OPEN             The module has not been opened
+ * @retval FSP_ERR_INVALID_ARGUMENT     Port is not valid ELC PORT.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event)
+{
+    uint8_t portgroup = 0U;
+    uint8_t portvalue;
+    uint8_t mask;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_pin_event);
+    uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
+    FSP_ERROR_RETURN((port_number == BSP_FEATURE_ELC_GROUP1_PORT_NUM >> IOPORT_PRV_PORT_OFFSET) ||
+                     (port_number == BSP_FEATURE_ELC_GROUP2_PORT_NUM >> IOPORT_PRV_PORT_OFFSET),
+                     FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Get port and pin number */
+    uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin);
+    uint32_t pin_num  = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin);
+
+    /* Get register address */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    R_PORT_NS_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+#else
+    R_PORT_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+#endif
+
+    /* Get port group number for the specified port */
+    if (BSP_FEATURE_ELC_GROUP1_PORT_NUM == port_num)
+    {
+        portgroup = 0U;
+    }
+    else if (BSP_FEATURE_ELC_GROUP2_PORT_NUM == port_num)
+    {
+        portgroup = 1U;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* Read current value of buffer value from ELC_PDBF register for the specified port group */
+    portvalue = p_ioport_regs->ELC_PDBF[portgroup].BY;
+    mask      = (uint8_t) (1U << pin_num);
+
+    if ((portvalue & mask) == mask)
+    {
+        *p_pin_event = BSP_IO_LEVEL_HIGH;
+    }
+    else
+    {
+        *p_pin_event = BSP_IO_LEVEL_LOW;
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * This function writes the set and reset event output data for a port. Implements
+ * @ref ioport_api_t::portEventOutputWrite.
+ *
+ * Using the event system enables a port state to be stored by this function in advance of being output on the port.
+ * The output to the port will occur when the ELC event occurs.
+ *
+ * The input value will be written to the specified port when an ELC event configured for that port occurs.
+ * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7,
+ * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port.
+ *
+ * @retval FSP_SUCCESS                Port event data written
+ * @retval FSP_ERR_INVALID_ARGUMENT   Port or Mask not valid
+ * @retval FSP_ERR_NOT_OPEN           The module has not been opened
+ * @retval FSP_ERR_ASSERTION          NULL pointer
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl,
+                                         bsp_io_port_t         port,
+                                         ioport_size_t         event_data,
+                                         ioport_size_t         mask_value)
+{
+    uint8_t       portgroup = 0U;
+    ioport_size_t temp_value;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
+    FSP_ERROR_RETURN((port == BSP_FEATURE_ELC_GROUP1_PORT_NUM) || (port == BSP_FEATURE_ELC_GROUP2_PORT_NUM),
+                     FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    R_BSP_PinAccessEnable();           // Unlock Register Write Protection
+
+    /* Get register address */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    R_PORT_NS_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+#else
+    R_PORT_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+#endif
+
+    /* Get port group number for the specified port */
+    if (BSP_FEATURE_ELC_GROUP1_PORT_NUM == port)
+    {
+        portgroup = 0U;
+    }
+    else if (BSP_FEATURE_ELC_GROUP2_PORT_NUM == port)
+    {
+        portgroup = 1U;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    temp_value  = p_ioport_regs->ELC_PDBF[portgroup].BY;
+    temp_value &= (ioport_size_t) (~mask_value);
+
+    p_ioport_regs->ELC_PDBF[portgroup].BY = (uint8_t) (temp_value | event_data);
+
+    R_BSP_PinAccessDisable();          // Lock Register Write Protection
+
+    return FSP_SUCCESS;
+}
+
+/**********************************************************************************************************************//**
+ * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite.
+ *
+ * Using the event system enables a pin state to be stored by this function in advance of being output on the pin.
+ * The output to the pin will occur when the ELC event occurs.
+ *
+ * @retval FSP_SUCCESS               Pin event data written
+ * @retval FSP_ERR_INVALID_ARGUMENT  Port or Pin or value not valid
+ * @retval FSP_ERR_NOT_OPEN          The module has not been opened
+ * @retval FSP_ERR_ASSERTION         NULL pointer
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value)
+{
+    uint8_t singleport = 0U;
+    uint8_t cnt;
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT);
+    uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
+    FSP_ERROR_RETURN((port_number == BSP_FEATURE_ELC_GROUP1_PORT_NUM >> IOPORT_PRV_PORT_OFFSET) ||
+                     (port_number == BSP_FEATURE_ELC_GROUP2_PORT_NUM >> IOPORT_PRV_PORT_OFFSET),
+                     FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend;
+
+    R_BSP_PinAccessEnable();           // Unlock Register Write Protection
+
+    /* Get register address */
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    R_PORT_NS_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+#else
+    R_PORT_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+#endif
+
+    for (cnt = 0; cnt < IOPORT_SINGLE_PORT_NUM; cnt++)
+    {
+        if ((bsp_io_port_pin_t) elc_cfg->single_port_cfg[cnt].port_num == pin)
+        {
+            singleport = cnt;
+        }
+    }
+
+    if (BSP_IO_LEVEL_HIGH == pin_value)
+    {
+        p_ioport_regs->ELC_PEL[singleport] |= (uint8_t) IOPORT_ELC_PEL_PSM_HIGH;
+    }
+    else
+    {
+        p_ioport_regs->ELC_PEL[singleport] &= (uint8_t) (~IOPORT_ELC_PEL_PSM_HIGH);
+    }
+
+    R_BSP_PinAccessDisable();          // Lock Register Write Protection
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup IOPORT)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Configures pins.
+ *
+ * @param[in]    p_cfg          Pin configuration data
+ **********************************************************************************************************************/
+void r_ioport_pins_config (const ioport_cfg_t * p_cfg)
+{
+    uint16_t       pin_count;
+    ioport_cfg_t * p_pin_data;
+
+    p_pin_data = (ioport_cfg_t *) p_cfg;
+
+    R_BSP_PinAccessEnable();           // Unlock Register Write Protection
+
+    for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++)
+    {
+        r_ioport_pin_set(p_pin_data->p_pin_cfg_data[pin_count].pin,
+                         (ioport_cfg_data_t *) &p_pin_data->p_pin_cfg_data[pin_count].pin_cfg);
+    }
+
+    R_BSP_PinAccessDisable();          // Lock Register Write Protection
+}
+
+/*******************************************************************************************************************//**
+ * Writes to the specified pin's multiple registers
+ *
+ * @param[in]    pin        Pin to write parameter data for
+ * @param[in]    p_cfg_data Value to be written to the multiple registers
+ *
+ **********************************************************************************************************************/
+static void r_ioport_pin_set (bsp_io_port_pin_t pin, ioport_cfg_data_t * p_cfg_data)
+{
+    /* Get port and pin number */
+    uint32_t port    = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET;
+    uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin);
+
+    /* Setting for Safety region or Non safety region */
+    if (p_cfg_data->rsel_reg == 1U)    // Setting for Non safety region
+    {
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+        if (port > BSP_FEATURE_IOPORT_SELECTABLE_PORT_MAX)
+        {
+            R_PORT_NS_COMMON_Type * p_ioport_regs = R_PORT_NSR;
+            r_ioport_pin_set_non_safety(p_ioport_regs, pin, p_cfg_data);
+        }
+        else
+        {
+            R_PORT_SRS->RSELP[port] |= (uint8_t) (1U << pin_num);
+            R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
+            r_ioport_pin_set_safety(p_ioport_regs, pin, p_cfg_data);
+        }
+
+#else
+        R_PTADR->RSELP[port] |= (uint8_t) (1U << pin_num);
+        R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
+        r_ioport_pin_set_safety(p_ioport_regs, pin, p_cfg_data);
+#endif
+    }
+    else                               // Setting for Safety region
+    {
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+        R_PORT_SRS->RSELP[port] &= (uint8_t) (~(1U << pin_num));
+#else
+        R_PTADR->RSELP[port] &= (uint8_t) (~(1U << pin_num));
+#endif
+        R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE);
+        r_ioport_pin_set_safety(p_ioport_regs, pin, p_cfg_data);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Writes to the specified pin's multiple registers for safety port
+ *
+ * @param[in]    p_ioport_regs Base address of register to be accessed
+ * @param[in]    pin           Pin to write parameter data for
+ * @param[in]    p_cfg_data    Value to be written to the multiple registers
+ *
+ **********************************************************************************************************************/
+static void r_ioport_pin_set_safety (R_PORT_COMMON_Type * p_ioport_regs,
+                                     bsp_io_port_pin_t    pin,
+                                     ioport_cfg_data_t  * p_cfg_data)
+{
+    uint32_t temp_value;
+
+    /* Get port and pin number */
+    uint32_t port    = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET;
+    uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin);
+
+    /* Setting DRCTL register */
+    if (3U >= pin_num)
+    {
+        temp_value = p_ioport_regs->DRCTL[port].L & ~(IOPORT_DRTCL_BIT_MASK << (pin_num * 8U));
+        p_ioport_regs->DRCTL[port].L = temp_value | (uint32_t) (p_cfg_data->drct_reg << (pin_num * 8U));
+    }
+    else if (3U < pin_num)
+    {
+        temp_value = p_ioport_regs->DRCTL[port].H & ~(IOPORT_DRTCL_BIT_MASK << ((pin_num - 4U) * 8U));
+        p_ioport_regs->DRCTL[port].H = temp_value | (uint32_t) (p_cfg_data->drct_reg << ((pin_num - 4U) * 8U));
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* Setting for GPIO or peripheral */
+    if (1U == p_cfg_data->pmc_reg)     // Setting for peripheral
+    {
+#if BSP_FEATURE_IOPORT_PIN_PFC_TYPE == 3
+        if (3U >= pin_num)
+        {
+            /* Setting PFC register */
+            temp_value                 = p_ioport_regs->PFC[port].L & ~(IOPORT_PFC_BIT_MASK << (pin_num * 8U));
+            p_ioport_regs->PFC[port].L = temp_value | (uint32_t) (p_cfg_data->pfc_reg << (pin_num * 8U));
+        }
+        else if (3U < pin_num)
+        {
+            /* Setting PFC register */
+            temp_value                 = p_ioport_regs->PFC[port].H & ~(IOPORT_PFC_BIT_MASK << ((pin_num - 4U) * 8U));
+            p_ioport_regs->PFC[port].H = temp_value | (uint32_t) (p_cfg_data->pfc_reg << ((pin_num - 4U) * 8U));
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+
+#else
+
+        /* Setting PFC register */
+        temp_value               = p_ioport_regs->PFC[port] & ~(IOPORT_PFC_BIT_MASK << (pin_num * 4U));
+        p_ioport_regs->PFC[port] = temp_value | (uint32_t) (p_cfg_data->pfc_reg << (pin_num * 4U));
+#endif
+
+        /* Setting peripheral for port mode */
+        p_ioport_regs->PMC[port] |= (uint8_t) (p_cfg_data->pmc_reg << pin_num); // Setting PMC register
+    }
+    else // Setting for GPIO
+    {
+        /* Setting GPIO for port mode */
+        p_ioport_regs->PMC[port] &= (uint8_t) (~(1U << pin_num)); // Setting PMC register
+
+        /* Setting for input or output */
+        if (1U == p_cfg_data->pm_reg)                             // Setting for input
+        {
+            /* Setting PM register. */
+            /* 01b: Input           */
+            temp_value              = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+            p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (1U << (pin_num * 2U)));
+        }
+        else if (1U < p_cfg_data->pm_reg)     // Setting for two kinds of Output
+        {
+            /* Setting P register */
+            if (0U == p_cfg_data->p_reg)      // Low output setting
+            {
+                p_ioport_regs->P[port] &= (uint8_t) (~(1U << pin_num));
+            }
+            else if (1U == p_cfg_data->p_reg) // High output setting
+            {
+                p_ioport_regs->P[port] |= (uint8_t) (1U << pin_num);
+            }
+            else
+            {
+                /* Do Nothing */
+            }
+
+            /* Setting PM register.                              */
+            /* 10b: Output                                       */
+            /* 11b: Output(output data is input to input buffer) */
+            temp_value              = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+            p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (p_cfg_data->pm_reg << (pin_num * 2U)));
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+}
+
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+
+/*******************************************************************************************************************//**
+ * Writes to the specified pin's multiple registers for non safety port
+ *
+ * @param[in]    p_ioport_regs Base address of register to be accessed
+ * @param[in]    pin           Pin to write parameter data for
+ * @param[in]    p_cfg_data    Value to be written to the multiple registers
+ *
+ **********************************************************************************************************************/
+static void r_ioport_pin_set_non_safety (R_PORT_NS_COMMON_Type * p_ioport_regs,
+                                         bsp_io_port_pin_t       pin,
+                                         ioport_cfg_data_t     * p_cfg_data)
+{
+    uint32_t temp_value;
+
+    /* Get port and pin number */
+    uint32_t port    = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET;
+    uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin);
+
+    /* Setting DRCTL register */
+    if (3U >= pin_num)
+    {
+        temp_value = p_ioport_regs->DRCTL[port].L & ~(IOPORT_DRTCL_BIT_MASK << (pin_num * 8U));
+        p_ioport_regs->DRCTL[port].L = temp_value | (uint32_t) (p_cfg_data->drct_reg << (pin_num * 8U));
+    }
+    else if (3U < pin_num)
+    {
+        temp_value = p_ioport_regs->DRCTL[port].H & ~(IOPORT_DRTCL_BIT_MASK << ((pin_num - 4U) * 8U));
+        p_ioport_regs->DRCTL[port].H = temp_value | (uint32_t) (p_cfg_data->drct_reg << ((pin_num - 4U) * 8U));
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* Setting for GPIO or peripheral */
+    if (1U == p_cfg_data->pmc_reg)     // Setting for peripheral
+    {
+ #if BSP_FEATURE_IOPORT_PIN_PFC_TYPE == 3
+        if (3U >= pin_num)
+        {
+            /* Setting PFC register */
+            temp_value                 = p_ioport_regs->PFC[port].L & ~(IOPORT_PFC_BIT_MASK << (pin_num * 8U));
+            p_ioport_regs->PFC[port].L = temp_value | (uint32_t) (p_cfg_data->pfc_reg << (pin_num * 8U));
+        }
+        else if (3U < pin_num)
+        {
+            /* Setting PFC register */
+            temp_value                 = p_ioport_regs->PFC[port].H & ~(IOPORT_PFC_BIT_MASK << ((pin_num - 4U) * 8U));
+            p_ioport_regs->PFC[port].H = temp_value | (uint32_t) (p_cfg_data->pfc_reg << ((pin_num - 4U) * 8U));
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+
+ #else
+
+        /* Setting PFC register */
+        temp_value               = p_ioport_regs->PFC[port] & ~(IOPORT_PFC_BIT_MASK << (pin_num * 4U));
+        p_ioport_regs->PFC[port] = temp_value | (uint32_t) (p_cfg_data->pfc_reg << (pin_num * 4U));
+ #endif
+
+        /* Setting peripheral for port mode */
+        p_ioport_regs->PMC[port] |= (uint8_t) (p_cfg_data->pmc_reg << pin_num);
+    }
+    else                                                          // Setting for GPIO
+    {
+        /* Setting GPIO for port mode */
+        p_ioport_regs->PMC[port] &= (uint8_t) (~(1U << pin_num)); // Setting PMC register
+
+        /* Setting for input or output */
+        if (1U == p_cfg_data->pm_reg)                             // Setting for input
+        {
+            /* Setting PM register. */
+            /* 01b: Input           */
+            temp_value              = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+            p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (1U << (pin_num * 2U)));
+        }
+        else if (1U < p_cfg_data->pm_reg)     // Setting for two kinds of Output
+        {
+            /* Setting P register */
+            if (0U == p_cfg_data->p_reg)      // Low output setting
+            {
+                p_ioport_regs->P[port] &= (uint8_t) (~(1U << pin_num));
+            }
+            else if (1U == p_cfg_data->p_reg) // High output setting
+            {
+                p_ioport_regs->P[port] |= (uint8_t) (1U << pin_num);
+            }
+            else
+            {
+                /* Do Nothing */
+            }
+
+            /* Setting PM register.                              */
+            /* 10b: Output                                       */
+            /* 11b: Output(output data is input to input buffer) */
+            temp_value              = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
+            p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (p_cfg_data->pm_reg << (pin_num * 2U)));
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Writes to the specified pin's multiple registers to generate event link function
+ *
+ * @param[in]    p_extend_cfg_data Value to be written to the multiple registers
+ *
+ **********************************************************************************************************************/
+static void r_ioport_event_config (const ioport_extend_cfg_t * p_extend_cfg_data)
+{
+    uint8_t event_num;
+    uint8_t temp_value    = 0x00;
+    uint8_t single_enable = 0x00;
+    uint8_t group_enable  = 0x00;
+#if BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT
+    R_PORT_NS_COMMON_Type * p_ioport_regs;
+#else
+    R_PORT_COMMON_Type * p_ioport_regs;
+#endif
+
+    ioport_extend_cfg_t * ex_cfg;
+
+    ex_cfg = (ioport_extend_cfg_t *) p_extend_cfg_data;
+
+    R_BSP_PinAccessEnable();           // Unlock Register Write Protection
+
+    /* Get register address */
+    p_ioport_regs = R_PORT_NSR;
+
+    /* Single port configuration */
+    for (event_num = 0U; event_num < IOPORT_SINGLE_PORT_NUM; event_num++)
+    {
+        uint8_t port =
+            (uint8_t) ((ex_cfg->single_port_cfg[event_num].port_num & IOPORT_PRV_PORT_BITS) >> IOPORT_PRV_PORT_OFFSET);
+        uint8_t pin_num = (uint8_t) ex_cfg->single_port_cfg[event_num].port_num & IOPORT_PRV_PIN_BITS;
+
+        temp_value = p_ioport_regs->ELC_PEL[event_num] & IOPORT_ELC_PEL_MASK;
+
+        /* Port selection */
+        if ((BSP_FEATURE_ELC_GROUP1_PORT_NUM >> IOPORT_PRV_PORT_OFFSET) == port)
+        {
+            temp_value |= 1U << 3;
+        }
+        else if ((BSP_FEATURE_ELC_GROUP2_PORT_NUM >> IOPORT_PRV_PORT_OFFSET) == port)
+        {
+            temp_value |= 1U << 4;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+
+        temp_value |= pin_num;         // Pin number setting
+
+        /* When the pin specified as single input port, Set edge detection */
+        /* When the pin specified as single output port, Set output operation */
+        if (IOPORT_EVENT_DIRECTION_INPUT == ex_cfg->single_port_cfg[event_num].direction)
+        {
+            temp_value |= (uint8_t) (ex_cfg->single_port_cfg[event_num].edge_detection << 5); // Edge detection
+
+            /* Edge detection enable */
+            p_ioport_regs->ELC_DPTC |= (uint8_t) (1U << event_num);
+        }
+        else
+        {
+            temp_value |= (uint8_t) (ex_cfg->single_port_cfg[event_num].operation << 5); // Output operation
+        }
+
+        /* Set to ELC port setting register */
+        p_ioport_regs->ELC_PEL[event_num] = temp_value;
+
+        /* Single port event link function enable */
+        if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->single_port_cfg[event_num].event_control)
+        {
+            single_enable |= (uint8_t) (1U << event_num);
+        }
+    }
+
+    /* Port group configuration */
+    for (event_num = 0U; event_num < IOPORT_PORT_GROUP_NUM; event_num++)
+    {
+        /* Pin selection */
+        uint8_t group_pin = ex_cfg->port_group_input_cfg[event_num].pin_select |
+                            ex_cfg->port_group_output_cfg[event_num].pin_select;
+        p_ioport_regs->ELC_PGR[event_num] = group_pin;
+
+        if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->port_group_input_cfg[event_num].event_control)
+        {
+            /* Input port group control */
+            temp_value  = p_ioport_regs->ELC_PGC[event_num] & IOOPRT_ELC_PGC_MASK;
+            temp_value |= (uint8_t) (ex_cfg->port_group_input_cfg[event_num].edge_detection);          // Edge detection
+            temp_value |= (uint8_t) (ex_cfg->port_group_input_cfg[event_num].overwrite_control << 2U); // Overwrite setting
+
+            /* Buffer register initialization */
+            p_ioport_regs->ELC_PDBF[event_num].BY = ex_cfg->port_group_input_cfg[event_num].buffer_init_value;
+
+            /* Input port group event link function enable */
+            group_enable |= (uint8_t) (1U << event_num);
+        }
+
+        /* Output port group operation */
+        temp_value |= (uint8_t) (ex_cfg->port_group_output_cfg[event_num].operation << 4);
+
+        /* Set to port group control register */
+        p_ioport_regs->ELC_PGC[event_num] = temp_value;
+    }
+
+    /* Set to ELC port event control register */
+    p_ioport_regs->ELC_ELSR2 = (uint8_t) ((single_enable << 4) | (group_enable << 2));
+
+    R_BSP_PinAccessDisable();          // Lock Register Write Protection
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_mtu3/r_mtu3.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_mtu3/r_mtu3.c
new file mode 100644
index 00000000..ad0bf17c
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_mtu3/r_mtu3.c
@@ -0,0 +1,2501 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_mtu3_cfg.h"
+#include "r_mtu3.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* "MTU3" in ASCII, used to determine if channel is open. */
+#define MTU3_OPEN                           (0x4D545533ULL)
+
+/* MTU3_CFG_OUTPUT_SUPPORT_ENABLE is set to 2 to enable extra features. */
+#define MTU3_PRV_EXTRA_FEATURES_ENABLED     (2U)
+
+/* MTU3_CFG_UVW_SUPPORT_ENABLE is set to 3 to enable extra features. */
+#define MTU3_PRV_UVW_FEATURES_ENABLED       (3U)
+
+#define MTU3_TOERA_MSK                      (R_MTU_TOERA_OE4D_Msk | R_MTU_TOERA_OE4C_Msk | R_MTU_TOERA_OE3D_Msk | \
+                                             R_MTU_TOERA_OE4B_Msk | R_MTU_TOERA_OE4A_Msk | R_MTU_TOERA_OE3B_Msk)
+
+#define MTU3_TOERB_MSK                      (R_MTU_TOERB_OE7D_Msk | R_MTU_TOERB_OE7C_Msk | R_MTU_TOERB_OE6D_Msk | \
+                                             R_MTU_TOERB_OE7B_Msk | R_MTU_TOERB_OE7A_Msk | R_MTU_TOERB_OE6B_Msk)
+
+#define MTU3_TCR_TPSC_POS                   (3U) /* MTUx.TCR.TPSC bit2-0 */
+#define MTU3_TCR_TPSC_POS_CH5               (2U) /* MTU5.TCR.TPSC bit1-0 */
+
+#define MTU3_PCLK_DIV_1                     (1U)
+#define MTU3_PCLK_DIV_2                     (2U)
+#define MTU3_PCLK_DIV_4                     (4U)
+#define MTU3_PCLK_DIV_8                     (8U)
+#define MTU3_PCLK_DIV_16                    (16U)
+#define MTU3_PCLK_DIV_32                    (32U)
+#define MTU3_PCLK_DIV_64                    (64U)
+#define MTU3_PCLK_DIV_256                   (256U)
+#define MTU3_PCLK_DIV_1024                  (1024U)
+
+#define MTU3_TPSC_OFS_ARRAY                 (8U)  /* MTUxTCR.TPSC bit2-0(The value is 0-7) */
+#define MTU3_TPSC_OFS_ARRAY_CH5             (4U)  /* MTU5TCR.TPSC bit1-0(The value is 0-3) */
+
+#define MTU3_CLK_TPSC_NUM                   (15U) /* TPSC and TPSC2 setting range */
+
+/* Noise filter offset address */
+#define MTU0_NOISEFILTER_OFFSET_ADDRESS     (0x0000U)
+#define MTU1_NOISEFILTER_OFFSET_ADDRESS     (0x0001U)
+#define MTU2_NOISEFILTER_OFFSET_ADDRESS     (0x0002U)
+#define MTU3_NOISEFILTER_OFFSET_ADDRESS     (0x0003U)
+#define MTU4_NOISEFILTER_OFFSET_ADDRESS     (0x0004U)
+#define MTU5_NOISEFILTER_OFFSET_ADDRESS     (0x0805U)
+#define MTU6_NOISEFILTER_OFFSET_ADDRESS     (0x0803U)
+#define MTU7_NOISEFILTER_OFFSET_ADDRESS     (0x0804U)
+#define MTU8_NOISEFILTER_OFFSET_ADDRESS     (0x0008U)
+#define MTU_NOISEFILTER_C_OFFSET_ADDRESS    (0x0009U)
+
+/* MTUx.TCR offset address */
+#define MTU0_TCR_OFFSET_ADDRESS             (0x0000U)
+#define MTU1_TCR_OFFSET_ADDRESS             (0x0000U)
+#define MTU2_TCR_OFFSET_ADDRESS             (0x0000U)
+#define MTU3_TCR_OFFSET_ADDRESS             (0x0100U)
+#define MTU4_TCR_OFFSET_ADDRESS             (0x0001U)
+#define MTU5_TCR_OFFSET_ADDRESS             (0x0084U)
+#define MTU6_TCR_OFFSET_ADDRESS             (0x0100U)
+#define MTU7_TCR_OFFSET_ADDRESS             (0x0001U)
+#define MTU8_TCR_OFFSET_ADDRESS             (0x0000U)
+
+/* MTUx.TCR2 offset address */
+#define MTU0_TCR2_OFFSET_ADDRESS            (0x0028U)
+#define MTU1_TCR2_OFFSET_ADDRESS            (0x0014U)
+#define MTU2_TCR2_OFFSET_ADDRESS            (0x000CU)
+#define MTU3_TCR2_OFFSET_ADDRESS            (0x014CU)
+#define MTU4_TCR2_OFFSET_ADDRESS            (0x004DU)
+#define MTU5_TCR2_OFFSET_ADDRESS            (0x0085U)
+#define MTU6_TCR2_OFFSET_ADDRESS            (0x014CU)
+#define MTU7_TCR2_OFFSET_ADDRESS            (0x004DU)
+#define MTU8_TCR2_OFFSET_ADDRESS            (0x0006U)
+
+/* MTUx.TMDR1 offset address */
+#define MTU0_TMDR1_OFFSET_ADDRESS           (0x0001U)
+#define MTU1_TMDR1_OFFSET_ADDRESS           (0x0001U)
+#define MTU2_TMDR1_OFFSET_ADDRESS           (0x0001U)
+#define MTU3_TMDR1_OFFSET_ADDRESS           (0x0102U)
+#define MTU4_TMDR1_OFFSET_ADDRESS           (0x0003U)
+#define MTU5_TMDR1_OFFSET_ADDRESS           (0x0000U) /* Nothing */
+#define MTU6_TMDR1_OFFSET_ADDRESS           (0x0102U)
+#define MTU7_TMDR1_OFFSET_ADDRESS           (0x0003U)
+#define MTU8_TMDR1_OFFSET_ADDRESS           (0x0001U)
+
+/* MTUx.TIOR offset address */
+#define MTU0_TIOR_OFFSET_ADDRESS            (0x0002U)
+#define MTU1_TIOR_OFFSET_ADDRESS            (0x0002U)
+#define MTU2_TIOR_OFFSET_ADDRESS            (0x0002U)
+#define MTU3_TIOR_OFFSET_ADDRESS            (0x0104U)
+#define MTU4_TIOR_OFFSET_ADDRESS            (0x0006U)
+#define MTU5_TIOR_OFFSET_ADDRESS            (0x0086U)
+#define MTU6_TIOR_OFFSET_ADDRESS            (0x0104U)
+#define MTU7_TIOR_OFFSET_ADDRESS            (0x0006U)
+#define MTU8_TIOR_OFFSET_ADDRESS            (0x0002U)
+
+/* MTUx.TIER offset address */
+#define MTU0_TIER_OFFSET_ADDRESS            (0x0004U)
+#define MTU1_TIER_OFFSET_ADDRESS            (0x0004U)
+#define MTU2_TIER_OFFSET_ADDRESS            (0x0004U)
+#define MTU3_TIER_OFFSET_ADDRESS            (0x0108U)
+#define MTU4_TIER_OFFSET_ADDRESS            (0x0009U)
+#define MTU5_TIER_OFFSET_ADDRESS            (0x00B2U)
+#define MTU6_TIER_OFFSET_ADDRESS            (0x0108U)
+#define MTU7_TIER_OFFSET_ADDRESS            (0x0009U)
+#define MTU8_TIER_OFFSET_ADDRESS            (0x0004U)
+
+/* MTUx.TSR offset address */
+#define MTU0_TSR_OFFSET_ADDRESS             (0x0000U) /* Nothing */
+#define MTU1_TSR_OFFSET_ADDRESS             (0x0005U)
+#define MTU2_TSR_OFFSET_ADDRESS             (0x0005U)
+#define MTU3_TSR_OFFSET_ADDRESS             (0x012CU)
+#define MTU4_TSR_OFFSET_ADDRESS             (0x002DU)
+#define MTU5_TSR_OFFSET_ADDRESS             (0x0000U) /* Nothing */
+#define MTU6_TSR_OFFSET_ADDRESS             (0x012CU)
+#define MTU7_TSR_OFFSET_ADDRESS             (0x002DU)
+#define MTU8_TSR_OFFSET_ADDRESS             (0x0000U) /* Nothing */
+
+/* MTUx.TCNT offset address */
+#define MTU0_TCNT_OFFSET_ADDRESS            (0x0006U)
+#define MTU1_TCNT_OFFSET_ADDRESS            (0x0006U)
+#define MTU2_TCNT_OFFSET_ADDRESS            (0x0006U)
+#define MTU3_TCNT_OFFSET_ADDRESS            (0x0110U)
+#define MTU4_TCNT_OFFSET_ADDRESS            (0x0012U)
+#define MTU5_TCNT_OFFSET_ADDRESS            (0x0080U)
+#define MTU6_TCNT_OFFSET_ADDRESS            (0x0110U)
+#define MTU7_TCNT_OFFSET_ADDRESS            (0x0012U)
+#define MTU8_TCNT_OFFSET_ADDRESS            (0x0008U)
+
+/* MTUx.TGRA offset address */
+#define MTU0_TGRA_OFFSET_ADDRESS            (0x0008U)
+#define MTU1_TGRA_OFFSET_ADDRESS            (0x0008U)
+#define MTU2_TGRA_OFFSET_ADDRESS            (0x0008U)
+#define MTU3_TGRA_OFFSET_ADDRESS            (0x0118U)
+#define MTU4_TGRA_OFFSET_ADDRESS            (0x001CU)
+#define MTU5_TGRA_OFFSET_ADDRESS            (0x0082U) /* Nothing */
+#define MTU6_TGRA_OFFSET_ADDRESS            (0x0118U)
+#define MTU7_TGRA_OFFSET_ADDRESS            (0x001CU)
+#define MTU8_TGRA_OFFSET_ADDRESS            (0x000CU)
+
+/* MTUx.TGRC offset address */
+#define MTU0_TGRC_OFFSET_ADDRESS            (0x000CU)
+#define MTU1_TGRC_OFFSET_ADDRESS            (0x000AU) /* Nothing */
+#define MTU2_TGRC_OFFSET_ADDRESS            (0x000AU) /* Nothing */
+#define MTU3_TGRC_OFFSET_ADDRESS            (0x0124U)
+#define MTU4_TGRC_OFFSET_ADDRESS            (0x0028U)
+#define MTU5_TGRC_OFFSET_ADDRESS            (0x0082U) /* Nothing */
+#define MTU6_TGRC_OFFSET_ADDRESS            (0x0124U)
+#define MTU7_TGRC_OFFSET_ADDRESS            (0x0028U)
+#define MTU8_TGRC_OFFSET_ADDRESS            (0x0014U)
+
+/* MTUx.TADCR offset address */
+#define MTU0_TADCR_OFFSET_ADDRESS           (0x0000U) /* Nothing */
+#define MTU1_TADCR_OFFSET_ADDRESS           (0x0000U) /* Nothing */
+#define MTU2_TADCR_OFFSET_ADDRESS           (0x0000U) /* Nothing */
+#define MTU3_TADCR_OFFSET_ADDRESS           (0x0000U) /* Nothing */
+#define MTU4_TADCR_OFFSET_ADDRESS           (0x0040U)
+#define MTU5_TADCR_OFFSET_ADDRESS           (0x0000U) /* Nothing */
+#define MTU6_TADCR_OFFSET_ADDRESS           (0x0000U) /* Nothing */
+#define MTU7_TADCR_OFFSET_ADDRESS           (0x0040U)
+#define MTU8_TADCR_OFFSET_ADDRESS           (0x0000U) /* Nothing */
+
+/* TGR offset address */
+#define MTU3_TGRB_D_OFFSET_WORD             (0x2U)
+#define MTU3_TGRB_D_OFFSET_LONG             (0x4U)
+#define MTU3_TGRU_OFFSET_WORD               (0x0U)
+#define MTU3_TGRV_OFFSET_WORD               (0x10U)
+#define MTU3_TGRW_OFFSET_WORD               (0x20U)
+
+#define MTU3_TGRB_D_OFFSET_WORD             (0x2U)
+
+#define MTU1_TIOR_IOB_INPUT_MTU8_TGRC       (0x0EU)   /* Input capture at occurrence of compare match or input capture in the MTU8.TGRC register */
+#define MTU8_TCR_CCLR_TGRC_COMPARE          (0x05U)   /* TCNT cleared by TGRC compare match/input capture */
+#define MTU8_TIOR_IOB_INPUT_MTU1_TCNT       (0x0EU)   /* Capture input source is the clock source for counting in MTU1.Input capture on counting up or down by MTU1.TCNT */
+#define MTU0_TCR2_TPSC_MTIOC1A              (0x07U)   /* External clock: counts on MTIOC1A pin input */
+#define MTU0_TIOR_IOB_INPUT_MTU1_TCNT       (0x0CU)   /* Capture input source is the clock source for counting in MTU1.Input capture on counting up or down by MTU1.TCNT */
+#define MTU0_TIOR_IOA_INPUT_MTU8_TGTC       (0x0EU)   /* Input capture on generation of compare match with MTU8.TGRC */
+#define MTU0_TCR_CCLR_TGRC_COMPARE          (0x05U)   /* TCNT cleared by TGRC compare match/input capture */
+
+#define MTU_TIOR_INPUT_RISING_EDGE          (0x08U)   /* Input capture at rising edge */
+#define MTU_TIOR_INPUT_FALLING_EDGE         (0x09U)   /* Input capture at falling edge */
+#define MTU_TIOR_INPUT_BOTH_EDGE            (0x0AU)   /* Input capture at both edge */
+
+#define MTU_TGR_INITIAL_VAL                 (0xFFFFU) /* TGR initial value */
+
+#define MTU0_TGRA_16BIT_MODE_INITIAL_VAL    (40000)   /* 0.2ms(200MHz) */
+#define MTU0_TGRC_16BIT_MODE_INITIAL_VAL    (50000)   /* 0.25ms(200MHz) */
+#define MTU8_TGRC_32BIT_MODE_INITIAL_VAL    (200000)  /* 1ms(200MHz) */
+
+/* UVW offset address(ch5) */
+#define MTU5_U_OFFSET_ADDRESS               (0x0U)
+#define MTU5_V_OFFSET_ADDRESS               (0x10U)
+#define MTU5_W_OFFSET_ADDRESS               (0x20U)
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+/* GPT_SEL interrupt */
+ #define GPT_INT4                           (4)
+ #define GPT_COMBINE_TABLE                  (3U)
+ #define MTU3_IRQ                           (3)
+ #define MTU3_IRQ_SELECT                    (3)
+ #define MTU3_IRQ_FUNCTION                  (3)
+ #define GPT_EVENT_SELECT                   (3)
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+typedef enum e_mtu3_prv_capture_event
+{
+    MTU3_PRV_CAPTURE_EVENT_A = 0U,
+    MTU3_PRV_CAPTURE_EVENT_B = 1U,
+    MTU3_PRV_CAPTURE_EVENT_U = 6U,
+    MTU3_PRV_CAPTURE_EVENT_V = 7U,
+    MTU3_PRV_CAPTURE_EVENT_W = 8U,
+} mtu3_prv_capture_event_t;
+
+/** MTU3 Channel No */
+typedef enum e_mtu3_channel
+{
+    MTU3_CHANNEL_0 = 0,                ///< MTU3 channel0
+    MTU3_CHANNEL_1 = 1,                ///< MTU3 channel1
+    MTU3_CHANNEL_2 = 2,                ///< MTU3 channel2
+    MTU3_CHANNEL_3 = 3,                ///< MTU3 channel3
+    MTU3_CHANNEL_4 = 4,                ///< MTU3 channel4
+    MTU3_CHANNEL_5 = 5,                ///< MTU3 channel5
+    MTU3_CHANNEL_6 = 6,                ///< MTU3 channel6
+    MTU3_CHANNEL_7 = 7,                ///< MTU3 channel7
+    MTU3_CHANNEL_8 = 8,                ///< MTU3 channel8
+} mtu3_channel_t;
+
+#define MTU3_PHASE_COUNTING_MODE_1_MD     0x4U
+#define MTU3_PHASE_COUNTING_MODE_2_MD     0x5U
+#define MTU3_PHASE_COUNTING_MODE_3_MD     0x6U
+#define MTU3_PHASE_COUNTING_MODE_4_MD     0x7U
+#define MTU3_PHASE_COUNTING_MODE_5_MD     0x9U
+
+#define MTU3_PHASE_COUNTING_MODE_PCB_0    0x0U
+#define MTU3_PHASE_COUNTING_MODE_PCB_1    (0x1U << 3)
+#define MTU3_PHASE_COUNTING_MODE_PCB_2    (0x2U << 3)
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+/* Table for MTU3 GPT_COMBINE */
+static const bsp_irq_gpt_combined_event_t gpt_combined[BSP_FEATURE_MTU3_MAX_CHANNELS][GPT_COMBINE_TABLE] =
+{
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1, /* MTU3 ch0 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4},
+
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_2,                                    /* MTU3 ch1 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_3, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4},
+
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_2, /* MTU3 ch2 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_3},
+
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1, /* MTU3 ch3 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4},
+
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1, /* MTU3 ch4 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4},
+
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1, /* MTU3 ch5 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_2},
+
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1, /* MTU3 ch6 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4},
+
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1, /* MTU3 ch7 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4},
+
+    {BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0, BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1, /* MTU3 ch8 */
+     BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4},
+};
+#endif
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void     mtu3_hardware_initialize(mtu3_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+static void     mtu3_counter_initialize(mtu3_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+static void     mtu3_common_open(mtu3_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+static void     mtu3_set_count(mtu3_instance_ctrl_t * const p_instance_ctrl, uint32_t counter);
+static void     mtu3_stop_timer(mtu3_instance_ctrl_t * const p_instance_ctrl);
+static uint32_t mtu3_clock_frequency_get(mtu3_instance_ctrl_t * const p_instance_ctrl, uint32_t ch_addr_ofs);
+static uint8_t  mtu3_get_tstr(mtu3_instance_ctrl_t * const p_instance_ctrl);
+static void     r_mtu3_disable_irq(IRQn_Type irq);
+static void     r_mtu3_enable_irq(IRQn_Type const irq, uint32_t priority, void * p_context) __attribute__((noinline));
+static void     mtu3_enable_interrupt(mtu3_instance_ctrl_t * const p_instance_ctrl);
+static void     mtu3_disable_interrupt(mtu3_instance_ctrl_t * const p_instance_ctrl);
+static void     r_mtu3_call_callback(mtu3_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture);
+static void     mtu3_event_operation_config(mtu3_instance_ctrl_t * const p_instance_ctrl,
+                                            timer_cfg_t const * const    p_cfg);
+static void mtu3_count_mode_set(mtu3_instance_ctrl_t * const p_instance_ctrl, mtu3_phase_counting_mode_t mode);
+static void mtu3_count_mode_hardware_initialize(mtu3_instance_ctrl_t * const p_instance_ctrl,
+                                                timer_cfg_t const * const    p_cfg);
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+static void mtu3_gpt_INT0_4_interrupt_enable(mtu3_instance_ctrl_t * const p_instance_ctrl);
+static void mtu3_gpt_INT0_4_interrupt_disable(mtu3_instance_ctrl_t * const p_instance_ctrl);
+
+ #if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+static void mtu3_gpt_channel_5_interrupt_enable(mtu3_instance_ctrl_t * const p_instance_ctrl);
+static void mtu3_gpt_channel_5_interrupt_disable(mtu3_instance_ctrl_t * const p_instance_ctrl);
+
+ #endif
+#endif
+
+/***********************************************************************************************************************
+ * ISR prototypes
+ **********************************************************************************************************************/
+void mtu3_counter_overflow_isr(void);
+void mtu3_counter_underflow_isr(void);
+void mtu3_capture_a_isr(void);
+void mtu3_capture_b_isr(void);
+void mtu3_capture_u_isr(void);
+void mtu3_capture_v_isr(void);
+void mtu3_capture_w_isr(void);
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+void mtu3_int_isr(void);
+
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/* Divided value table of MTU3. */
+/* Defined based on the values of TCR.TPSC and TCR2.TPSC2.(External clock(MTCLKA, MTIOC1A, etc) is defined as 1 division) */
+/* [0]-[7]: TCR.TPSC setting value. [8]-[15]: TCR2.TPSC2 setting value(For other than ch5) */
+/* [0]-[3]: TCR.TPSC setting value. [4]-[12]: TCR2.TPSC2-TCR2.CKEG setting value(For ch5) */
+static const uint16_t mtu3_clk_div[BSP_FEATURE_MTU3_MAX_CHANNELS][MTU3_CLK_TPSC_NUM] =
+{
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1,      /* MTU ch0 */
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8, MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_256,
+     MTU3_PCLK_DIV_1024, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1,      /* MTU ch1 */
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8, MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_1024,
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1,      /* MTU ch2 */
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1024, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8, MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_256,
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_256, MTU3_PCLK_DIV_1024, /* MTU ch3 */
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8, MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_1,
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_256, MTU3_PCLK_DIV_1024, /* MTU ch4 */
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8, MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_1,
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8,      /* MTU ch5 */
+     MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_256, MTU3_PCLK_DIV_1024, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1,
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_256, MTU3_PCLK_DIV_1024, /* MTU ch6 */
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8, MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_1,
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_256, MTU3_PCLK_DIV_1024, /* MTU ch7 */
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8, MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_1,
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+    {MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_4, MTU3_PCLK_DIV_16, MTU3_PCLK_DIV_64, MTU3_PCLK_DIV_256, MTU3_PCLK_DIV_1024, /* MTU ch8 */
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_2, MTU3_PCLK_DIV_8, MTU3_PCLK_DIV_32, MTU3_PCLK_DIV_1,
+     MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1, MTU3_PCLK_DIV_1},
+};
+
+/* MTUx base address */
+static const uint32_t volatile * p_mtu3_base_address[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    (uint32_t *) R_MTU0,               /* 0x90001300UL */
+    (uint32_t *) R_MTU1,               /* 0x90001380UL */
+    (uint32_t *) R_MTU2,               /* 0x90001400UL */
+    (uint32_t *) R_MTU3,               /* 0x90001100UL */
+    (uint32_t *) R_MTU4,               /* 0x90001200UL */
+    (uint32_t *) R_MTU5,               /* 0x90001C00UL */
+    (uint32_t *) R_MTU6,               /* 0x90001900UL */
+    (uint32_t *) R_MTU7,               /* 0x90001A00UL */
+    (uint32_t *) R_MTU8,               /* 0x90001600UL */
+};
+
+/* Noise filter offset address */
+static const uint32_t nfcr_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_NOISEFILTER_OFFSET_ADDRESS,
+    MTU1_NOISEFILTER_OFFSET_ADDRESS,
+    MTU2_NOISEFILTER_OFFSET_ADDRESS,
+    MTU3_NOISEFILTER_OFFSET_ADDRESS,
+    MTU4_NOISEFILTER_OFFSET_ADDRESS,
+    MTU5_NOISEFILTER_OFFSET_ADDRESS,
+    MTU6_NOISEFILTER_OFFSET_ADDRESS,
+    MTU7_NOISEFILTER_OFFSET_ADDRESS,
+    MTU8_NOISEFILTER_OFFSET_ADDRESS,
+};
+
+/* MTUx.TCR offset address */
+static const uint32_t tcr_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TCR_OFFSET_ADDRESS,
+    MTU1_TCR_OFFSET_ADDRESS,
+    MTU2_TCR_OFFSET_ADDRESS,
+    MTU3_TCR_OFFSET_ADDRESS,
+    MTU4_TCR_OFFSET_ADDRESS,
+    MTU5_TCR_OFFSET_ADDRESS,
+    MTU6_TCR_OFFSET_ADDRESS,
+    MTU7_TCR_OFFSET_ADDRESS,
+    MTU8_TCR_OFFSET_ADDRESS,
+};
+
+/* MTUx.TCR2 offset address */
+static const uint32_t tcr2_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TCR2_OFFSET_ADDRESS,
+    MTU1_TCR2_OFFSET_ADDRESS,
+    MTU2_TCR2_OFFSET_ADDRESS,
+    MTU3_TCR2_OFFSET_ADDRESS,
+    MTU4_TCR2_OFFSET_ADDRESS,
+    MTU5_TCR2_OFFSET_ADDRESS,
+    MTU6_TCR2_OFFSET_ADDRESS,
+    MTU7_TCR2_OFFSET_ADDRESS,
+    MTU8_TCR2_OFFSET_ADDRESS,
+};
+
+/* MTUx.TMDR1 offset address */
+static const uint32_t tmdr1_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TMDR1_OFFSET_ADDRESS,
+    MTU1_TMDR1_OFFSET_ADDRESS,
+    MTU2_TMDR1_OFFSET_ADDRESS,
+    MTU3_TMDR1_OFFSET_ADDRESS,
+    MTU4_TMDR1_OFFSET_ADDRESS,
+    MTU5_TMDR1_OFFSET_ADDRESS,         /* Nothing */
+    MTU6_TMDR1_OFFSET_ADDRESS,
+    MTU7_TMDR1_OFFSET_ADDRESS,
+    MTU8_TMDR1_OFFSET_ADDRESS,
+};
+
+/* MTUx.TIOR offset address */
+static const uint32_t tior_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TIOR_OFFSET_ADDRESS,
+    MTU1_TIOR_OFFSET_ADDRESS,
+    MTU2_TIOR_OFFSET_ADDRESS,
+    MTU3_TIOR_OFFSET_ADDRESS,
+    MTU4_TIOR_OFFSET_ADDRESS,
+    MTU5_TIOR_OFFSET_ADDRESS,
+    MTU6_TIOR_OFFSET_ADDRESS,
+    MTU7_TIOR_OFFSET_ADDRESS,
+    MTU8_TIOR_OFFSET_ADDRESS,
+};
+
+/* MTUx.TIER offset address */
+static const uint32_t tier_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TIER_OFFSET_ADDRESS,
+    MTU1_TIER_OFFSET_ADDRESS,
+    MTU2_TIER_OFFSET_ADDRESS,
+    MTU3_TIER_OFFSET_ADDRESS,
+    MTU4_TIER_OFFSET_ADDRESS,
+    MTU5_TIER_OFFSET_ADDRESS,
+    MTU6_TIER_OFFSET_ADDRESS,
+    MTU7_TIER_OFFSET_ADDRESS,
+    MTU8_TIER_OFFSET_ADDRESS,
+};
+
+/* MTUx.TSR offset address */
+static const uint32_t tsr_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TSR_OFFSET_ADDRESS,
+    MTU1_TSR_OFFSET_ADDRESS,
+    MTU2_TSR_OFFSET_ADDRESS,
+    MTU3_TSR_OFFSET_ADDRESS,
+    MTU4_TSR_OFFSET_ADDRESS,
+    MTU5_TSR_OFFSET_ADDRESS,
+    MTU6_TSR_OFFSET_ADDRESS,
+    MTU7_TSR_OFFSET_ADDRESS,
+    MTU8_TSR_OFFSET_ADDRESS,
+};
+
+/* MTUx.TCNT offset address */
+static const uint32_t tcnt_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TCNT_OFFSET_ADDRESS,
+    MTU1_TCNT_OFFSET_ADDRESS,
+    MTU2_TCNT_OFFSET_ADDRESS,
+    MTU3_TCNT_OFFSET_ADDRESS,
+    MTU4_TCNT_OFFSET_ADDRESS,
+    MTU5_TCNT_OFFSET_ADDRESS,          /* (Nothing) */
+    MTU6_TCNT_OFFSET_ADDRESS,
+    MTU7_TCNT_OFFSET_ADDRESS,
+    MTU8_TCNT_OFFSET_ADDRESS,
+};
+
+/* MTUx.TGRA offset address */
+static const uint32_t tgra_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TGRA_OFFSET_ADDRESS,
+    MTU1_TGRA_OFFSET_ADDRESS,
+    MTU2_TGRA_OFFSET_ADDRESS,
+    MTU3_TGRA_OFFSET_ADDRESS,
+    MTU4_TGRA_OFFSET_ADDRESS,
+    MTU5_TGRA_OFFSET_ADDRESS,          /* (Nothing) */
+    MTU6_TGRA_OFFSET_ADDRESS,
+    MTU7_TGRA_OFFSET_ADDRESS,
+    MTU8_TGRA_OFFSET_ADDRESS,
+};
+
+/* MTUx.TGRC offset address */
+static const uint32_t tgrc_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TGRC_OFFSET_ADDRESS,
+    MTU1_TGRC_OFFSET_ADDRESS,          /* (Nothing) */
+    MTU2_TGRC_OFFSET_ADDRESS,          /* (Nothing) */
+    MTU3_TGRC_OFFSET_ADDRESS,
+    MTU4_TGRC_OFFSET_ADDRESS,
+    MTU5_TGRC_OFFSET_ADDRESS,          /* (Nothing) */
+    MTU6_TGRC_OFFSET_ADDRESS,
+    MTU7_TGRC_OFFSET_ADDRESS,
+    MTU8_TGRC_OFFSET_ADDRESS,
+};
+
+/* MTUx.TADCR offset address */
+static const uint32_t tadcr_ofs_addr[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    MTU0_TADCR_OFFSET_ADDRESS,         /* Nothing */
+    MTU1_TADCR_OFFSET_ADDRESS,         /* Nothing */
+    MTU2_TADCR_OFFSET_ADDRESS,         /* Nothing */
+    MTU3_TADCR_OFFSET_ADDRESS,         /* Nothing */
+    MTU4_TADCR_OFFSET_ADDRESS,
+    MTU5_TADCR_OFFSET_ADDRESS,         /* Nothing */
+    MTU6_TADCR_OFFSET_ADDRESS,         /* Nothing */
+    MTU7_TADCR_OFFSET_ADDRESS,
+    MTU8_TADCR_OFFSET_ADDRESS,         /* Nothing */
+};
+
+/* MTU3.TSTR value */
+static const uint8_t mtu3_tstr_val[BSP_FEATURE_MTU3_MAX_CHANNELS] =
+{
+    (1U << R_MTU_TSTRA_CST0_Pos),
+    (1U << R_MTU_TSTRA_CST1_Pos),
+    (1U << R_MTU_TSTRA_CST2_Pos),
+    (1U << R_MTU_TSTRA_CST3_Pos),
+    (1U << R_MTU_TSTRA_CST4_Pos),
+    0U,
+    (1U << R_MTU_TSTRB_CST6_Pos),
+    (1U << R_MTU_TSTRB_CST7_Pos),
+    (1U << R_MTU_TSTRA_CST8_Pos),
+};
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/* MTU3 implementation of timer interface  */
+const timer_api_t g_timer_on_mtu3 =
+{
+    .open        = R_MTU3_Open,
+    .stop        = R_MTU3_Stop,
+    .start       = R_MTU3_Start,
+    .reset       = R_MTU3_Reset,
+    .callbackSet = R_MTU3_CallbackSet,
+    .close       = R_MTU3_Close,
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup MTU3
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes the timer module and applies configurations.
+ *
+ * The MTU3 implementation of the general timer can accept a mtu3_extended_cfg_t extension parameter.
+ *
+ * @retval FSP_SUCCESS                    Initialization was successful and timer has started.
+ * @retval FSP_ERR_ASSERTION              A required input pointer is NULL.
+ * @retval FSP_ERR_ALREADY_OPEN           Module is already open.
+ * @retval FSP_ERR_INVALID_MODE           PWM is only supported if MTU3_CFG_OUTPUT_SUPPORT_ENABLE is 2.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_extend);
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(p_cfg->mode != TIMER_MODE_ONE_SHOT, FSP_ERR_INVALID_MODE);
+    FSP_ERROR_RETURN(p_cfg->mode <= TIMER_MODE_PWM, FSP_ERR_INVALID_MODE);
+    FSP_ERROR_RETURN(MTU3_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+#endif
+
+    /** mask_bit MTU3 0-8bit*/
+    p_instance_ctrl->channel_mask = (1U << p_cfg->channel);
+
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ERROR_RETURN((p_instance_ctrl->channel_mask & BSP_FEATURE_MTU3_VALID_CHANNEL_MASK),
+                     FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+#endif
+
+    /* Initialize control structure based on configurations. */
+    mtu3_common_open(p_instance_ctrl, p_cfg);
+
+    mtu3_hardware_initialize(p_instance_ctrl, p_cfg);
+
+    p_instance_ctrl->open = MTU3_OPEN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops timer.
+ *
+ * @retval FSP_SUCCESS                 Timer successfully stopped.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_Stop (timer_ctrl_t * const p_ctrl)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Stop timer */
+    mtu3_stop_timer(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Starts timer.
+ *
+ * @retval FSP_SUCCESS                 Timer successfully started.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_Start (timer_ctrl_t * const p_ctrl)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Start timer */
+    if ((MTU3_CHANNEL_6 == p_instance_ctrl->p_cfg->channel) || (MTU3_CHANNEL_7 == p_instance_ctrl->p_cfg->channel))
+    {
+        p_instance_ctrl->p_reg_com->TSTRB |= mtu3_tstr_val[p_instance_ctrl->p_cfg->channel];
+    }
+    /* Start timer for counting mode */
+    else if ((MTU3_PHASE_COUNTING_MODE_NONE != p_extend->counting_mode) &&
+             (MTU3_BIT_MODE_NORMAL_32BIT == p_extend->bit_mode))
+    {
+        p_instance_ctrl->p_reg_com->TSTRA |= (R_MTU_TSTRA_CST1_Msk | R_MTU_TSTRA_CST2_Msk);
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* Since it is a register dedicated to MTU5, set it directly. */
+        R_MTU5->TSTR = (R_MTU5_TSTR_CSTW5_Msk | R_MTU5_TSTR_CSTV5_Msk | R_MTU5_TSTR_CSTU5_Msk);
+    }
+#endif
+    else
+    {
+        p_instance_ctrl->p_reg_com->TSTRA |= mtu3_tstr_val[p_instance_ctrl->p_cfg->channel];
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Resets the counter value to 0.
+ *
+ * @note This function also updates to the new period if no counter overflow has occurred since the last call to
+ * R_MTU3_PeriodSet().
+ *
+ * @retval FSP_SUCCESS                 Counter value written successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_Reset (timer_ctrl_t * const p_ctrl)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    mtu3_set_count(p_instance_ctrl, 0U);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets period value provided. If the timer is running, the period will be updated after the next compare match.
+ * If the timer is stopped, this function resets the counter and updates the period.
+ *
+ * @retval FSP_SUCCESS                 Period value written successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_PeriodSet (timer_ctrl_t * const p_ctrl, mtu3_counter_t * const p_counter)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* In the case of ch5, there is no buffer register, so set a value in TGR and exit. */
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]) =
+            (uint16_t) (p_counter->tgru_counts - 1U);
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU5_V_OFFSET_ADDRESS) = (uint16_t) (p_counter->tgrv_counts - 1U);
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU5_W_OFFSET_ADDRESS) = (uint16_t) (p_counter->tgrw_counts - 1U);
+
+        return FSP_SUCCESS;
+    }
+#endif
+
+    /* Update period buffer register. The actual period is one cycle longer than the register value.
+     * Reference section 17.6.3 "Note on Period Setting" */
+    uint32_t new_tgra_counts = p_counter->tgra_counts - 1U;
+    uint32_t new_tgrb_counts = p_counter->tgrb_counts - 1U;
+
+    /* Update period register and reset counter. */
+    if (MTU3_CHANNEL_8 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* If the counter is not counting, TGRA and TGRB update */
+        if (0U == mtu3_get_tstr(p_instance_ctrl))
+        {
+            *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                           tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]) = new_tgra_counts;
+            *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                           MTU3_TGRB_D_OFFSET_LONG) = new_tgrb_counts;
+        }
+
+        *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                       tgrc_ofs_addr[p_instance_ctrl->p_cfg->channel]) = new_tgra_counts;
+        *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgrc_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                       MTU3_TGRB_D_OFFSET_LONG) = new_tgrb_counts;
+    }
+    else if ((MTU3_CHANNEL_1 == p_instance_ctrl->p_cfg->channel) ||
+             (MTU3_CHANNEL_2 == p_instance_ctrl->p_cfg->channel))
+    {
+        /* MTU1 and 2 without TGRC and TGRD should write TGRA and TGRB */
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (uint16_t) new_tgra_counts;
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU3_TGRB_D_OFFSET_WORD) = (uint16_t) new_tgrb_counts;
+    }
+    else
+    {
+        /* If the counter is not counting, TGRA and TGRB update */
+        if (0U == mtu3_get_tstr(p_instance_ctrl))
+        {
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (uint16_t) new_tgra_counts;
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                    MTU3_TGRB_D_OFFSET_WORD) = (uint16_t) new_tgrb_counts;
+        }
+
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                tgrc_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (uint16_t) new_tgra_counts;
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgrc_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU3_TGRB_D_OFFSET_WORD) = (uint16_t) new_tgrb_counts;
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Get timer information and store it in provided pointer p_info.
+ *
+ * @retval FSP_SUCCESS                 TGRx, count direction, frequency, structure successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_info was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_InfoGet (timer_ctrl_t * const p_ctrl, mtu3_info_t * const p_info)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_info);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Get tgrx value */
+    if (MTU3_CHANNEL_8 == p_instance_ctrl->p_cfg->channel)
+    {
+        p_info->count_param.tgra_counts =
+            *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]);
+        p_info->count_param.tgrb_counts =
+            *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                           MTU3_TGRB_D_OFFSET_LONG);
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* Since it is a register dedicated to MTU5, get it directly. */
+        p_info->count_param.tgru_counts = R_MTU5->TGRU;
+        p_info->count_param.tgrv_counts = R_MTU5->TGRV;
+        p_info->count_param.tgrw_counts = R_MTU5->TGRW;
+    }
+#endif
+    else
+    {
+        p_info->count_param.tgra_counts =
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]);
+        p_info->count_param.tgrb_counts =
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                    MTU3_TGRB_D_OFFSET_WORD);
+    }
+
+    /* Get and store clock frequency */
+    if (MTU3_CHANNEL_5 != p_instance_ctrl->p_cfg->channel)
+    {
+        p_info->clock_frequency[0] = mtu3_clock_frequency_get(p_instance_ctrl, 0U);
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else
+    {
+        for (uint8_t uvw_ch = 0U; uvw_ch < BSP_FEATURE_MTU3_UVW_MAX_CHANNELS; uvw_ch++)
+        {
+            p_info->clock_frequency[uvw_ch] =
+                mtu3_clock_frequency_get(p_instance_ctrl, (uvw_ch * MTU5_V_OFFSET_ADDRESS));
+        }
+    }
+#endif
+
+    /* Get and store clock counting direction. Read count direction setting */
+    p_info->count_direction = TIMER_DIRECTION_UP;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Get current timer status and store it in provided pointer p_status.
+ *
+ * @retval FSP_SUCCESS                 Current timer state and counter value set successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_StatusGet (timer_ctrl_t * const p_ctrl, mtu3_status_t * const p_status)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_status);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Get counter state. */
+    if (0U == mtu3_get_tstr(p_instance_ctrl))
+    {
+        p_status->state = TIMER_STATE_STOPPED;
+    }
+    else
+    {
+        p_status->state = TIMER_STATE_COUNTING;
+    }
+
+    /* Get counter value */
+    if (MTU3_CHANNEL_8 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* MTU8.TCNT should be accessed in 32-bit units */
+        p_status->counter =
+            *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel]);
+    }
+    else if ((MTU3_PHASE_COUNTING_MODE_NONE != p_extend->counting_mode) &&
+             (MTU3_BIT_MODE_NORMAL_32BIT == p_extend->bit_mode))
+    {
+        /* In the case of 32bit, the position information (encoder counter) is stored in MTU1.TCNTLW*/
+        p_status->counter = R_MTU1->TCNTLW;
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        p_status->tgru_counter =
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel]);
+        p_status->tgrv_counter =
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                    MTU5_V_OFFSET_ADDRESS);
+        p_status->tgrv_counter =
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                    MTU5_W_OFFSET_ADDRESS);
+    }
+#endif
+
+    else
+    {
+        p_status->counter =
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel]);
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set counter value.
+ *
+ * @note Do not call this API while the counter is counting.  The counter value can only be updated while the counter
+ * is stopped.
+ *
+ * @retval FSP_SUCCESS                 Counter value updated.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ * @retval FSP_ERR_IN_USE              The timer is running.  Stop the timer before calling this function.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_CounterSet (timer_ctrl_t * const p_ctrl, uint32_t counter)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(0U == mtu3_get_tstr(p_instance_ctrl), FSP_ERR_IN_USE);
+#endif
+
+    /* Set counter value */
+    mtu3_set_count(p_instance_ctrl, counter);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enable output for MTIOCA and/or MTIOCB.
+ *
+ * @retval FSP_SUCCESS                 Output is enabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_OutputEnable (timer_ctrl_t * const p_ctrl, mtu3_output_pin_t pin_level)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    *((uint8_t *) p_instance_ctrl->p_reg + tior_ofs_addr[p_instance_ctrl->p_cfg->channel]) =
+        (uint8_t) ((pin_level.output_pin_level_b << R_MTU0_TIORH_IOB_Pos) | pin_level.output_pin_level_a);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disable output for MTIOCA and/or MTIOCB.
+ *
+ * @retval FSP_SUCCESS                 Output is disabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_OutputDisable (timer_ctrl_t * const p_ctrl, mtu3_io_pin_t pin)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    uint8_t tior = *((uint8_t *) p_instance_ctrl->p_reg + tior_ofs_addr[p_instance_ctrl->p_cfg->channel]);
+    if (MTU3_IO_PIN_MTIOCB != pin)
+    {
+        /* MTIOCA or both MTIOCA and MTIOCB. */
+        tior &= (uint8_t) ~R_MTU0_TIORH_IOA_Msk;
+    }
+
+    if (MTU3_IO_PIN_MTIOCA != pin)
+    {
+        /* MTIOCB or both MTIOCA and MTIOCB. */
+        tior &= (uint8_t) ~R_MTU0_TIORH_IOB_Msk;
+    }
+
+    *((uint8_t *) p_instance_ctrl->p_reg + tior_ofs_addr[p_instance_ctrl->p_cfg->channel]) = tior;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set A/D converter start request compare match value.
+ *
+ * @note MTU ch4, ch7 only
+ *
+ * @retval FSP_SUCCESS                 Counter value updated.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_AdcTriggerSet (timer_ctrl_t * const     p_ctrl,
+                                mtu3_adc_compare_match_t which_compare_match,
+                                uint16_t                 compare_match_value)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Set A/D converter start request compare match value. */
+    if (MTU3_ADC_COMPARE_MATCH_ADC_A == which_compare_match)
+    {
+        if (MTU3_CHANNEL_4 == p_instance_ctrl->p_cfg->channel)
+        {
+            R_MTU4->TADCORA = compare_match_value;
+        }
+        else
+        {
+            R_MTU7->TADCORA = compare_match_value;
+        }
+    }
+
+    if (MTU3_ADC_COMPARE_MATCH_ADC_B == which_compare_match)
+    {
+        if (MTU3_CHANNEL_4 == p_instance_ctrl->p_cfg->channel)
+        {
+            R_MTU4->TADCORB = compare_match_value;
+        }
+        else
+        {
+            R_MTU7->TADCORB = compare_match_value;
+        }
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Updates the user callback with the option to provide memory for the callback argument structure.
+ *
+ * @retval  FSP_SUCCESS                  Callback updated successfully.
+ * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_CallbackSet (timer_ctrl_t * const          p_ctrl,
+                              void (                      * p_callback)(timer_callback_args_t *),
+                              void const * const            p_context,
+                              timer_callback_args_t * const p_callback_memory)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(p_callback);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Store callback and context */
+    p_instance_ctrl->p_callback        = p_callback;
+    p_instance_ctrl->p_context         = p_context;
+    p_instance_ctrl->p_callback_memory = p_callback_memory;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops counter, disables output pins, and clears internal driver data.
+ *
+ * @retval FSP_SUCCESS                 Successful close.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_MTU3_Close (timer_ctrl_t * const p_ctrl)
+{
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) p_ctrl;
+    fsp_err_t              err             = FSP_SUCCESS;
+
+#if MTU3_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(MTU3_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Stop counter. */
+    mtu3_stop_timer(p_instance_ctrl);
+
+    /* Clear open flag. */
+    p_instance_ctrl->open = 0U;
+
+    /* Disable output. */
+    *((uint8_t *) p_instance_ctrl->p_reg + tior_ofs_addr[p_instance_ctrl->p_cfg->channel]) = 0U;
+
+    /* Disable A/D Converter Start Request */
+    if ((MTU3_CHANNEL_5 != p_instance_ctrl->p_cfg->channel) && (MTU3_CHANNEL_8 != p_instance_ctrl->p_cfg->channel))
+    {
+        *((uint8_t *) p_instance_ctrl->p_reg + tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) &=
+            (uint8_t) ~((uint8_t) R_MTU0_TIER_TTGE_Msk);
+    }
+
+    /* Disable interrupts. */
+    mtu3_disable_interrupt(p_instance_ctrl);
+
+    return err;
+}
+
+/** @} (end addtogroup MTU3) */
+
+/*******************************************************************************************************************//**
+ * Private Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes control structure based on configuration.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block.
+ * @param[in]  p_cfg                   Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void mtu3_common_open (mtu3_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    /* Initialize control structure.  */
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    /* If callback is not null, make sure the IRQ is enabled and store callback in the control block. */
+
+    /* Save register base address. */
+    uintptr_t base_address;
+    base_address = (uintptr_t) (p_mtu3_base_address[p_cfg->channel]);
+
+    p_instance_ctrl->p_reg_com = R_MTU;
+    p_instance_ctrl->p_reg_nf  = (void *) R_MTU_NF;
+    p_instance_ctrl->p_reg     = (void *) base_address;
+
+    /* Set callback and context pointers, if configured */
+    p_instance_ctrl->p_callback        = p_cfg->p_callback;
+    p_instance_ctrl->p_context         = p_cfg->p_context;
+    p_instance_ctrl->p_callback_memory = NULL;
+}
+
+/*******************************************************************************************************************//**
+ * Performs hardware initialization of the MTU3.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ * @param[in]  p_cfg                  Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void mtu3_hardware_initialize (mtu3_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_cfg->p_extend;
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    mtu3_extended_uvw_cfg_t const * p_uvw_cfg = p_extend->p_uvw_cfg;
+#endif
+
+    /* Counter related initialization */
+    mtu3_counter_initialize(p_instance_ctrl, p_cfg);
+
+    /* In MTU3 and MTU4, set TOERA prior to setting TIOR. */
+    p_instance_ctrl->p_reg_com->TOERA = MTU3_TOERA_MSK;
+    p_instance_ctrl->p_reg_com->TOERB = MTU3_TOERB_MSK;
+
+#if MTU3_PRV_EXTRA_FEATURES_ENABLED == MTU3_CFG_OUTPUT_SUPPORT_ENABLE
+    mtu3_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+    if (NULL != p_pwm_cfg)
+    {
+        /* Interrupt Skipping Function Select */
+        p_instance_ctrl->p_reg_com->TITMRA = p_pwm_cfg->interrupt_skip_mode_a;
+        p_instance_ctrl->p_reg_com->TITMRB = p_pwm_cfg->interrupt_skip_mode_b;
+
+        switch (p_instance_ctrl->p_cfg->channel)
+        {
+            case MTU3_CHANNEL_3:
+            {
+                /* When TITMRA = 0 */
+                if (MTU3_INTERRUPT_SKIP_MODE_1 == p_pwm_cfg->interrupt_skip_mode_a)
+                {
+                    /* T3ACNT clear */
+                    p_instance_ctrl->p_reg_com->TITCR1A &=
+                        (uint8_t) ~((uint8_t) R_MTU_TITCR1A_T3AEN_Msk | R_MTU_TITCR1A_T3ACOR_Msk);
+                    p_instance_ctrl->p_reg_com->TITCR1A = (uint8_t) ((uint8_t) R_MTU_TITCR1A_T3AEN_Msk | \
+                                                                     (uint8_t) p_pwm_cfg->interrupt_skip_count_tgia3 <<
+                                                                     R_MTU_TITCR1A_T3ACOR_Pos);
+                }
+
+                break;
+            }
+
+            case MTU3_CHANNEL_4:
+            {
+                /* When TITMRA = 0 */
+                if (MTU3_INTERRUPT_SKIP_MODE_1 == p_pwm_cfg->interrupt_skip_mode_a)
+                {
+                    /* T4VCNT clear */
+                    p_instance_ctrl->p_reg_com->TITCR1A &=
+                        (uint8_t) ~((uint8_t) R_MTU_TITCR1A_T4VEN_Msk | R_MTU_TITCR1A_T4VCOR_Msk);
+                    p_instance_ctrl->p_reg_com->TITCR1A = (uint8_t) ((uint8_t) R_MTU_TITCR1A_T4VEN_Msk | \
+                                                                     (uint8_t) p_pwm_cfg->interrupt_skip_count_tciv4 <<
+                                                                     R_MTU_TITCR1A_T4VCOR_Pos);
+                }
+                /* When TITMRA = 1 */
+                else
+                {
+                    /* TRG4CNT clear */
+                    p_instance_ctrl->p_reg_com->TITCR2A &= (uint8_t) ~((uint8_t) R_MTU_TITCR2A_TRG4COR_Msk);
+                    p_instance_ctrl->p_reg_com->TITCR2A  = (uint8_t) (p_pwm_cfg->interrupt_skip_count_tgr4an_bn <<
+                                                                     R_MTU_TITCR2A_TRG4COR_Pos);
+                }
+
+                R_MTU4->TADCORA = p_pwm_cfg->adc_a_compare_match;
+                R_MTU4->TADCORB = p_pwm_cfg->adc_b_compare_match;
+                break;
+            }
+
+            case MTU3_CHANNEL_6:
+            {
+                /* When TITMRB = 0 */
+                if (MTU3_INTERRUPT_SKIP_MODE_1 == p_pwm_cfg->interrupt_skip_mode_b)
+                {
+                    /* T6ACNT clear */
+                    p_instance_ctrl->p_reg_com->TITCR1B &=
+                        (uint8_t) ~((uint8_t) R_MTU_TITCR1B_T6AEN_Msk | R_MTU_TITCR1B_T6ACOR_Msk);
+                    p_instance_ctrl->p_reg_com->TITCR1B = (uint8_t) ((uint8_t) R_MTU_TITCR1B_T6AEN_Msk | \
+                                                                     (uint8_t) p_pwm_cfg->interrupt_skip_count_tgia6 <<
+                                                                     R_MTU_TITCR1B_T6ACOR_Pos);
+                }
+
+                break;
+            }
+
+            case MTU3_CHANNEL_7:
+            {
+                /* When TITMRB = 0 */
+                if (MTU3_INTERRUPT_SKIP_MODE_1 == p_pwm_cfg->interrupt_skip_mode_b)
+                {
+                    /* T7VCNT clear */
+                    p_instance_ctrl->p_reg_com->TITCR1B &=
+                        (uint8_t) ~(R_MTU_TITCR1B_T7VEN_Msk | R_MTU_TITCR1B_T7VCOR_Msk);
+                    p_instance_ctrl->p_reg_com->TITCR1B = (uint8_t) ((uint8_t) R_MTU_TITCR1B_T7VEN_Msk | \
+                                                                     (uint8_t) p_pwm_cfg->interrupt_skip_count_tciv7 <<
+                                                                     R_MTU_TITCR1B_T7VCOR_Pos);
+                }
+                /* When TITMRB = 1 */
+                else
+                {
+                    /* TRG7CNT clear */
+                    p_instance_ctrl->p_reg_com->TITCR2B &= (uint8_t) ~(R_MTU_TITCR2B_TRG7COR_Msk);
+                    p_instance_ctrl->p_reg_com->TITCR2B  = (uint8_t) (p_pwm_cfg->interrupt_skip_count_tgr7an_bn <<
+                                                                     R_MTU_TITCR2B_TRG7COR_Pos);
+                }
+
+                R_MTU7->TADCORA = p_pwm_cfg->adc_a_compare_match;
+                R_MTU7->TADCORB = p_pwm_cfg->adc_b_compare_match;
+                break;
+            }
+
+            default:
+            {
+                break;
+            }
+        }
+    }
+#endif
+
+    /* Configure the noise filter for the MTIOC pins. */
+    uint8_t nfcr = 0U;
+    if (MTU3_CHANNEL_5 != p_instance_ctrl->p_cfg->channel)
+    {
+        nfcr =
+            (uint8_t) (p_extend->noise_filter_mtioc_setting & (R_MTU_NF_NFCR0_NFAEN_Msk | R_MTU_NF_NFCR0_NFBEN_Msk));
+        nfcr |= (uint8_t) (p_extend->noise_filter_mtioc_clk << R_MTU_NF_NFCR0_NFCS_Pos);
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else
+    {
+        nfcr =
+            (uint8_t) (p_uvw_cfg->noise_filter_mtioc_setting_uvw &
+                       (R_MTU_NF_NFCR5_NFUEN_Msk | R_MTU_NF_NFCR5_NFVEN_Msk | R_MTU_NF_NFCR5_NFWEN_Msk));
+        nfcr |= (uint8_t) (p_uvw_cfg->noise_filter_mtioc_clk_uvw << R_MTU_NF_NFCR5_NFCS_Pos);
+    }
+#endif
+    *((uint8_t *) p_instance_ctrl->p_reg_nf + nfcr_ofs_addr[p_instance_ctrl->p_cfg->channel]) = nfcr;
+
+    /* Configure the noise filter for the MTCLKx pins. */
+    uint8_t nfcrc = 0U;
+    nfcrc =
+        (uint8_t) (p_extend->noise_filter_mtclk_setting &
+                   (R_MTU_NF_NFCRC_NFAEN_Msk | R_MTU_NF_NFCRC_NFBEN_Msk | R_MTU_NF_NFCRC_NFCEN_Msk |
+                    R_MTU_NF_NFCRC_NFDEN_Msk));
+    nfcrc |= (uint8_t) (p_extend->noise_filter_mtclk_clk << R_MTU_NF_NFCRC_NFCS_Pos);
+    *((uint8_t *) p_instance_ctrl->p_reg_nf + MTU_NOISEFILTER_C_OFFSET_ADDRESS) = nfcrc;
+
+    uint8_t tmdr1 = 0U;
+
+    /* Enable the compare match buffer. */
+    if (!((MTU3_CHANNEL_1 == p_instance_ctrl->p_cfg->channel) || (MTU3_CHANNEL_2 == p_instance_ctrl->p_cfg->channel) ||
+          (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)))
+    {
+        tmdr1 = (R_MTU0_TMDR1_BFA_Msk | R_MTU0_TMDR1_BFB_Msk);
+    }
+
+    tmdr1 |= (uint8_t) (p_cfg->mode);
+    *((uint8_t *) p_instance_ctrl->p_reg + tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = tmdr1;
+
+    /* A/D converter start requests enable. */
+    if (((MTU3_CHANNEL_4 == p_instance_ctrl->p_cfg->channel) || (MTU3_CHANNEL_7 == p_instance_ctrl->p_cfg->channel)))
+    {
+        *(uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                       tadcr_ofs_addr[p_instance_ctrl->p_cfg->channel]) =
+            (R_MTU4_TADCR_UT4AE_Msk | R_MTU4_TADCR_DT4AE_Msk | \
+             R_MTU4_TADCR_UT4BE_Msk |
+             R_MTU4_TADCR_DT4BE_Msk);
+    }
+
+    /* Set the I/O control register. */
+    if (MTU3_CHANNEL_5 != p_instance_ctrl->p_cfg->channel)
+    {
+        uint8_t tior_ioa = p_extend->mtioc_ctrl_setting.output_pin_level_a;
+        uint8_t tior_iob = p_extend->mtioc_ctrl_setting.output_pin_level_b;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tior_ofs_addr[p_instance_ctrl->p_cfg->channel]) =
+            ((uint8_t) (tior_iob << R_MTU0_TIORH_IOB_Pos) | tior_ioa);
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else
+    {
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tior_ofs_addr[p_instance_ctrl->p_cfg->channel]) = p_uvw_cfg->output_pin_level_u;
+        *((uint8_t *) p_instance_ctrl->p_reg + tior_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+          MTU5_V_OFFSET_ADDRESS) = p_uvw_cfg->output_pin_level_v;
+        *((uint8_t *) p_instance_ctrl->p_reg + tior_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+          MTU5_W_OFFSET_ADDRESS) = p_uvw_cfg->output_pin_level_w;
+    }
+#endif
+    mtu3_enable_interrupt(p_instance_ctrl);
+
+    /* Enable A/D Converter Start Request */
+    if ((MTU3_CHANNEL_5 != p_instance_ctrl->p_cfg->channel) && (MTU3_CHANNEL_8 != p_instance_ctrl->p_cfg->channel))
+    {
+        *((uint8_t *) p_instance_ctrl->p_reg + tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) |=
+            (uint8_t) (p_extend->adc_request_enable << R_MTU0_TIER_TTGE_Pos);
+    }
+
+    /*Set MTU3 event link operation*/
+    mtu3_event_operation_config(p_instance_ctrl, p_cfg);
+
+    /* Enable counting mode */
+    if ((MTU3_PHASE_COUNTING_MODE_NONE != p_extend->counting_mode) &&
+        (MTU3_CHANNEL_1 == p_instance_ctrl->p_cfg->channel))
+    {
+        /*Initialization structure based on configurations */
+        mtu3_count_mode_hardware_initialize(p_instance_ctrl, p_cfg);
+
+        /* Configure the up/down count mode. These are not affected by enable/disable. */
+        mtu3_count_mode_set(p_instance_ctrl, p_extend->counting_mode);
+
+        if (MTU3_BIT_MODE_NORMAL_32BIT == p_extend->bit_mode)
+        {
+            p_instance_ctrl->p_reg_com->TSTRA |= mtu3_tstr_val[p_instance_ctrl->p_cfg->channel];
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_2_MD;
+
+            /* Set MTU1.TCNTLW count clear factor to MTU1.TGRALW input capture. */
+            R_MTU1->TCR_b.CCLR = MTU3_TCNT_CLEAR_TGRA;
+
+            switch (p_extend->counting_mode)
+            {
+                case MTU3_PHASE_COUNTING_MODE_NONE:
+                {
+                    break;
+                }
+
+                case MTU3_PHASE_COUNTING_MODE_1:
+                case MTU3_PHASE_COUNTING_MODE_210:
+                case MTU3_PHASE_COUNTING_MODE_310:
+                case MTU3_PHASE_COUNTING_MODE_4:
+                {
+                    /* Set the effective edge of both edge. */
+                    R_MTU1->TIOR_b.IOA = MTU_TIOR_INPUT_BOTH_EDGE;
+                    R_MTU1->TIOR_b.IOB = MTU_TIOR_INPUT_BOTH_EDGE;
+                    break;
+                }
+
+                case MTU3_PHASE_COUNTING_MODE_200:
+                case MTU3_PHASE_COUNTING_MODE_300:
+                case MTU3_PHASE_COUNTING_MODE_50:
+                case MTU3_PHASE_COUNTING_MODE_51:
+                {
+                    /* Set the effective edge of falling edge. */
+                    R_MTU1->TIOR_b.IOA = MTU_TIOR_INPUT_FALLING_EDGE;
+                    R_MTU1->TIOR_b.IOB = MTU_TIOR_INPUT_FALLING_EDGE;
+                    break;
+                }
+
+                case MTU3_PHASE_COUNTING_MODE_201:
+                case MTU3_PHASE_COUNTING_MODE_301:
+                {
+                    /* Set the effective edge of rising edge. */
+                    R_MTU1->TIOR_b.IOA = MTU_TIOR_INPUT_RISING_EDGE;
+                    R_MTU1->TIOR_b.IOB = MTU_TIOR_INPUT_RISING_EDGE;
+                    break;
+                }
+            }
+        }
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Writes to the ELOPA or ELOPB register in ELC driver to set up  MTU event operation
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ * @param[in]  p_cfg                  Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void mtu3_event_operation_config (mtu3_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    uint32_t elopa = 0;
+    uint32_t elopb = 0;
+
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_cfg->p_extend;
+
+    elopa = R_ELO->ELOPA;
+    elopb = R_ELO->ELOPB;
+
+    if (MTU3_CHANNEL_0 == p_instance_ctrl->p_cfg->channel)
+    {
+        elopa &= (uint32_t) ~R_ELO_ELOPA_MTU0MD_Msk;
+        elopa |= (uint32_t) ((p_extend->mtu3_elc_event_operation.mtu0_elc_operation) << R_ELO_ELOPA_MTU0MD_Pos);
+    }
+
+    if (MTU3_CHANNEL_3 == p_instance_ctrl->p_cfg->channel)
+    {
+        elopa &= (uint32_t) ~R_ELO_ELOPA_MTU3MD_Msk;
+        elopa |= (uint32_t) ((p_extend->mtu3_elc_event_operation.mtu3_elc_operation) << R_ELO_ELOPA_MTU3MD_Pos);
+    }
+
+    if (MTU3_CHANNEL_4 == p_instance_ctrl->p_cfg->channel)
+    {
+        elopb &= (uint32_t) ~R_ELO_ELOPB_MTU4MD_Msk;
+        elopb |= (uint32_t) ((p_extend->mtu3_elc_event_operation.mtu4_elc_operation) << R_ELO_ELOPB_MTU4MD_Pos);
+    }
+
+    /*Set the value for ELOPA, ELOPB*/
+    R_ELO->ELOPA = elopa;
+    R_ELO->ELOPB = elopb;
+}
+
+/*******************************************************************************************************************//**
+ * Performs hardware initialization of the MTU3 mode phase count
+ * @param[in]  p_instance_ctrl        Instance control block.
+ * @param[in]  p_cfg                  Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void mtu3_count_mode_hardware_initialize (mtu3_instance_ctrl_t * const p_instance_ctrl,
+                                                 timer_cfg_t const * const    p_cfg)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_cfg->p_extend;
+
+    /* Clear the TMDR3 register to zero */
+    R_MTU1->TMDR3 &= (uint8_t) ~(R_MTU1_TMDR3_LWA_Msk | R_MTU1_TMDR3_PHCKSEL_Msk);
+
+    /* Normal mode */
+    if (MTU3_BIT_MODE_NORMAL_16BIT == p_extend->bit_mode)
+    {
+        /* 16-bit access is enabled. */
+        R_MTU1->TMDR3 &= (uint8_t) ~R_MTU1_TMDR3_LWA_Msk;
+
+        /* Select phase counting mode. */
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) =
+            (uint8_t) (p_extend->counting_mode << R_MTU1_TMDR1_MD_Pos);
+    }
+    else
+    {
+        /* 32-bit access is enabled. */
+        R_MTU1->TMDR3 = R_MTU1_TMDR3_LWA_Msk;
+
+        /* Select phase counting mode. If LWA = 1, the MTU1 setting takes precedence. */
+        R_MTU1->TMDR1 = (uint8_t) (p_extend->counting_mode << R_MTU1_TMDR1_MD_Pos);
+    }
+
+    /* Select A- or B-phase input pin */
+    R_MTU1->TMDR3 |= (uint8_t) (p_extend->external_clock << R_MTU1_TMDR3_PHCKSEL_Pos);
+}
+
+/*******************************************************************************************************************//**
+ * Counter initialization of the MTU3.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ * @param[in]  p_cfg                  Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void mtu3_counter_initialize (mtu3_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_cfg->p_extend;
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    mtu3_extended_uvw_cfg_t const * p_uvw_cfg = p_extend->p_uvw_cfg;
+#endif
+
+    /* Power on MTU3 before setting any hardware registers. Make sure the counter is stopped before setting mode
+     * register, PCLK divisor register, and counter register. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+    R_BSP_MODULE_START(FSP_IP_MTU3, p_cfg->channel);
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+    /* Initialize all registers that may affect operation of this driver to reset values.  Skip these since they
+     * affect all channels, and are initialized in TSTR and TCNT is set immediately after
+     * clearing the module stop bit to ensure the timer is stopped before proceeding with configuration. */
+    mtu3_stop_timer(p_instance_ctrl);
+    mtu3_set_count(p_instance_ctrl, 0U);
+
+    /* Set the division ratio */
+    if (MTU3_CHANNEL_5 != p_instance_ctrl->p_cfg->channel)
+    {
+        uint8_t tcr = (uint8_t) ((uint8_t) (p_extend->mtu3_clear << R_MTU0_TCR_CCLR_Pos) |
+                                 (uint8_t) (p_extend->clk_edge << R_MTU0_TCR_CKEG_Pos) |
+                                 (uint8_t) (p_extend->mtu3_clk_div & R_MTU0_TCR_TPSC_Msk));
+        uint8_t tcr2 = ((p_extend->mtu3_clk_div >> MTU3_TCR_TPSC_POS) & R_MTU0_TCR2_TPSC2_Msk);
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr_ofs_addr[p_instance_ctrl->p_cfg->channel])  = tcr;
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = tcr2;
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else
+    {
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr_ofs_addr[p_instance_ctrl->p_cfg->channel]) =
+            (p_uvw_cfg->mtu3_clk_div_u & R_MTU5_TCRU_TPSC_Msk);
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) =
+            ((p_uvw_cfg->mtu3_clk_div_u >> MTU3_TCR_TPSC_POS_CH5) & (R_MTU5_TCR2U_TPSC2_Msk | R_MTU5_TCR2U_CKEG_Msk));
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr_ofs_addr[p_instance_ctrl->p_cfg->channel] + MTU5_V_OFFSET_ADDRESS) =
+            (p_uvw_cfg->mtu3_clk_div_v & R_MTU5_TCRU_TPSC_Msk);
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel] + MTU5_V_OFFSET_ADDRESS) =
+            ((p_uvw_cfg->mtu3_clk_div_v >> MTU3_TCR_TPSC_POS_CH5) & (R_MTU5_TCR2U_TPSC2_Msk | R_MTU5_TCR2U_CKEG_Msk));
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr_ofs_addr[p_instance_ctrl->p_cfg->channel] + MTU5_W_OFFSET_ADDRESS) =
+            (p_uvw_cfg->mtu3_clk_div_w & R_MTU5_TCRU_TPSC_Msk);
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel] + MTU5_W_OFFSET_ADDRESS) =
+            ((p_uvw_cfg->mtu3_clk_div_w >> MTU3_TCR_TPSC_POS_CH5) & (R_MTU5_TCR2U_TPSC2_Msk | R_MTU5_TCR2U_CKEG_Msk));
+    }
+#endif
+
+    /* Store period register setting. The actual period and is one cycle longer than the register value. */
+    if (MTU3_CHANNEL_8 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* MTU ch8 should be written in 32-bit length */
+        *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                       tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (p_extend->tgra_val - 1U);
+        *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                       MTU3_TGRB_D_OFFSET_LONG) = (p_extend->tgrb_val - 1U);
+        *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                       tgrc_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (p_extend->tgrc_val - 1U);
+        *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgrc_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                       MTU3_TGRB_D_OFFSET_LONG) = (p_extend->tgrd_val - 1U);
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (uint16_t) (p_uvw_cfg->tgru_val - 1U);
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU5_V_OFFSET_ADDRESS) = (uint16_t) (p_uvw_cfg->tgrv_val - 1U);
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU5_W_OFFSET_ADDRESS) = (uint16_t) (p_uvw_cfg->tgrw_val - 1U);
+    }
+#endif
+    else
+    {
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (uint16_t) (p_extend->tgra_val - 1U);
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU3_TGRB_D_OFFSET_WORD) = (uint16_t) (p_extend->tgrb_val - 1U);
+
+        /* TGRC and TGRD do not exist in MTU1 and MTU2 */
+        if (!((MTU3_CHANNEL_1 == p_instance_ctrl->p_cfg->channel) ||
+              (MTU3_CHANNEL_2 == p_instance_ctrl->p_cfg->channel)))
+        {
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tgrc_ofs_addr[p_instance_ctrl->p_cfg->channel]) =
+                (uint16_t) (p_extend->tgrc_val - 1U);
+            *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                    tgrc_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                    MTU3_TGRB_D_OFFSET_WORD) = (uint16_t) (p_extend->tgrd_val - 1U);
+        }
+    }
+}
+
+/*******************************************************************************************************************//**
+ * The counter value can only be updated while the counter
+ *
+ * @param[in]  p_instance_ctrl         Instance control structure
+ * @param[in]  counter                 Timer counter
+ **********************************************************************************************************************/
+static void mtu3_set_count (mtu3_instance_ctrl_t * const p_instance_ctrl, uint32_t counter)
+{
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Set timer counter. */
+    if (MTU3_CHANNEL_8 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* MTU8.TCNT should be accessed in 32-bit units */
+        *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel]) = counter;
+    }
+    else if ((MTU3_PHASE_COUNTING_MODE_NONE != p_extend->counting_mode) &&
+             (MTU3_BIT_MODE_NORMAL_32BIT == p_extend->bit_mode))
+    {
+        /* In the case of 32bit, value encoder counter is stored in MTU1. */
+        R_MTU1->TCNTLW = counter;
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* Since it is a register dedicated to MTU5, set it directly. */
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (uint16_t) counter;
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU5_V_OFFSET_ADDRESS) = (uint16_t) counter;
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg + tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                MTU5_W_OFFSET_ADDRESS) = (uint16_t) counter;
+    }
+#endif
+    else
+    {
+        *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                tcnt_ofs_addr[p_instance_ctrl->p_cfg->channel]) = (uint16_t) counter;
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Check the operating status
+ *
+ * @param[in]  p_instance_ctrl         Instance control structure
+ **********************************************************************************************************************/
+static uint8_t mtu3_get_tstr (mtu3_instance_ctrl_t * const p_instance_ctrl)
+{
+    uint8_t               ret_val;
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Check the operating status */
+    if ((MTU3_CHANNEL_6 == p_instance_ctrl->p_cfg->channel) || (MTU3_CHANNEL_7 == p_instance_ctrl->p_cfg->channel))
+    {
+        ret_val = (p_instance_ctrl->p_reg_com->TSTRB & mtu3_tstr_val[p_instance_ctrl->p_cfg->channel]);
+    }
+    else if ((MTU3_PHASE_COUNTING_MODE_NONE != p_extend->counting_mode) &&
+             (MTU3_BIT_MODE_NORMAL_32BIT == p_extend->bit_mode))
+    {
+        ret_val = (p_instance_ctrl->p_reg_com->TSTRA & (R_MTU_TSTRA_CST1_Msk | R_MTU_TSTRA_CST2_Msk));
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* Since it is a register dedicated to MTU5, get it directly. */
+        ret_val = R_MTU5->TSTR;
+    }
+#endif
+    else
+    {
+        ret_val = (p_instance_ctrl->p_reg_com->TSTRA & mtu3_tstr_val[p_instance_ctrl->p_cfg->channel]);
+    }
+
+    return ret_val;
+}
+
+/*******************************************************************************************************************//**
+ * Stops timer
+ *
+ * @param[in]  p_instance_ctrl         Instance control structure
+ **********************************************************************************************************************/
+static void mtu3_stop_timer (mtu3_instance_ctrl_t * const p_instance_ctrl)
+{
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Stop timer */
+    if ((MTU3_CHANNEL_6 == p_instance_ctrl->p_cfg->channel) || (MTU3_CHANNEL_7 == p_instance_ctrl->p_cfg->channel))
+    {
+        p_instance_ctrl->p_reg_com->TSTRB &= (uint8_t) ~mtu3_tstr_val[p_instance_ctrl->p_cfg->channel];
+    }
+    /* Stop timer for counting mode */
+    else if ((MTU3_PHASE_COUNTING_MODE_NONE == p_extend->counting_mode) &&
+             (MTU3_BIT_MODE_NORMAL_32BIT == p_extend->bit_mode))
+    {
+        p_instance_ctrl->p_reg_com->TSTRA &= (uint8_t) ~(R_MTU_TSTRA_CST1_Msk | R_MTU_TSTRA_CST2_Msk);
+    }
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        /* Since it is a register dedicated to MTU5, set it directly. */
+        R_MTU5->TSTR &= (uint8_t) ~(R_MTU5_TSTR_CSTW5_Msk | R_MTU5_TSTR_CSTV5_Msk | R_MTU5_TSTR_CSTU5_Msk);
+    }
+#endif
+    else
+    {
+        p_instance_ctrl->p_reg_com->TSTRA &= (uint8_t) ~mtu3_tstr_val[p_instance_ctrl->p_cfg->channel];
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Disables interrupt if it is a valid vector number.
+ *
+ * @param[in]  irq                     Interrupt number
+ **********************************************************************************************************************/
+static void r_mtu3_disable_irq (IRQn_Type irq)
+{
+    /* Disable interrupts. */
+    if (irq >= 0)
+    {
+        R_BSP_IrqDisable(irq);
+        R_FSP_IsrContextSet(irq, NULL);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Configures and enables interrupt if it is a valid vector number.
+ *
+ * @param[in]  irq                     Interrupt number
+ * @param[in]  priority                NVIC priority of the interrupt
+ * @param[in]  p_context               The interrupt context is a pointer to data required in the ISR.
+ **********************************************************************************************************************/
+static void r_mtu3_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_context)
+{
+    if (irq >= 0)
+    {
+        R_BSP_IrqCfgEnable(irq, priority, p_context);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Disable interrupts
+ *
+ * @param[in]  p_instance_ctrl           Instance control block
+ **********************************************************************************************************************/
+static void mtu3_disable_interrupt (mtu3_instance_ctrl_t * const p_instance_ctrl)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+ #if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+        mtu3_gpt_channel_5_interrupt_disable(p_instance_ctrl);
+ #endif
+        mtu3_extended_uvw_cfg_t const * p_uvw_cfg = p_extend->p_uvw_cfg;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) &= (uint8_t) ~R_MTU5_TIER_TGIE5U_Msk;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) &= (uint8_t) ~R_MTU5_TIER_TGIE5V_Msk;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) &= (uint8_t) ~R_MTU5_TIER_TGIE5W_Msk;
+
+        r_mtu3_disable_irq(p_uvw_cfg->capture_u_irq);
+        r_mtu3_disable_irq(p_uvw_cfg->capture_v_irq);
+        r_mtu3_disable_irq(p_uvw_cfg->capture_w_irq);
+    }
+    else
+#endif
+    {
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+        mtu3_gpt_INT0_4_interrupt_disable(p_instance_ctrl);
+#endif
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) &= (uint8_t) ~R_MTU0_TIER_TCIEV_Msk;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) &= (uint8_t) ~R_MTU0_TIER_TGIEA_Msk;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) &= (uint8_t) ~R_MTU0_TIER_TGIEB_Msk;
+
+        r_mtu3_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq);
+        r_mtu3_disable_irq(p_extend->capture_a_irq);
+        r_mtu3_disable_irq(p_extend->capture_b_irq);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Enable interrupts
+ *
+ * @param[in]  p_instance_ctrl           Instance control block
+ **********************************************************************************************************************/
+static void mtu3_enable_interrupt (mtu3_instance_ctrl_t * const p_instance_ctrl)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Initialize TIER */
+    *((uint8_t *) p_instance_ctrl->p_reg + tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) = 0x00U;
+
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+ #if  (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+        mtu3_gpt_channel_5_interrupt_enable(p_instance_ctrl);
+ #endif
+        mtu3_extended_uvw_cfg_t const * p_uvw_cfg = p_extend->p_uvw_cfg;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) |= R_MTU5_TIER_TGIE5U_Msk;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) |= R_MTU5_TIER_TGIE5V_Msk;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) |= R_MTU5_TIER_TGIE5W_Msk;
+
+        r_mtu3_enable_irq(p_uvw_cfg->capture_u_irq, p_uvw_cfg->capture_u_ipl, p_instance_ctrl);
+        r_mtu3_enable_irq(p_uvw_cfg->capture_v_irq, p_uvw_cfg->capture_v_ipl, p_instance_ctrl);
+        r_mtu3_enable_irq(p_uvw_cfg->capture_w_irq, p_uvw_cfg->capture_w_ipl, p_instance_ctrl);
+    }
+    else
+#endif
+    {
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+        mtu3_gpt_INT0_4_interrupt_enable(p_instance_ctrl);
+#endif
+
+        /* Enable CPU interrupts if callback is not null. */
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) |= R_MTU0_TIER_TCIEV_Msk;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) |= R_MTU0_TIER_TGIEA_Msk;
+        *((uint8_t *) p_instance_ctrl->p_reg +
+          tier_ofs_addr[p_instance_ctrl->p_cfg->channel]) |= R_MTU0_TIER_TGIEB_Msk;
+
+        r_mtu3_enable_irq(p_instance_ctrl->p_cfg->cycle_end_irq, p_instance_ctrl->p_cfg->cycle_end_ipl,
+                          p_instance_ctrl);
+        r_mtu3_enable_irq(p_extend->capture_a_irq, p_extend->capture_a_ipl, p_instance_ctrl);
+        r_mtu3_enable_irq(p_extend->capture_b_irq, p_extend->capture_b_ipl, p_instance_ctrl);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Calculates clock frequency of MTU3 counter.  Divides MTU3 clock by MTU3 clock divisor.
+ *
+ * @param[in]  p_instance_ctrl           Instance control block
+ * @param[in]  ch_addr_ofs               Offset address of register
+ *
+ * @return     Clock frequency of the MTU3 counter.
+ **********************************************************************************************************************/
+static uint32_t mtu3_clock_frequency_get (mtu3_instance_ctrl_t * const p_instance_ctrl, uint32_t ch_addr_ofs)
+{
+    uint32_t pclk_freq_hz;
+    uint16_t pclk_divisor;
+    uint8_t  tpsc;
+    uint8_t  tcr_tpsc;
+    uint8_t  tcr2_tpsc;
+
+    /* Get frequency division from TCR and TCR2. */
+    tcr_tpsc =
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr_ofs_addr[p_instance_ctrl->p_cfg->channel] + ch_addr_ofs);
+    tcr2_tpsc =
+        *((uint8_t *) p_instance_ctrl->p_reg + tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel] + ch_addr_ofs);
+
+    if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+    {
+        tcr_tpsc  &= R_MTU5_TCRU_TPSC_Msk;
+        tcr2_tpsc &= R_MTU5_TCR2U_TPSC2_Msk;
+    }
+    else
+    {
+        tcr_tpsc  &= R_MTU0_TCR_TPSC_Msk;
+        tcr2_tpsc &= R_MTU0_TCR2_TPSC2_Msk;
+    }
+
+    /* If TCR2.TPSC2 is 1 or greater, get from the array that stores the TCR2.TPSC2 settings. */
+    if (tcr2_tpsc >= 1U)
+    {
+        if (MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel)
+        {
+            /* Get from the 4th array(for ch5) */
+            tpsc = (uint8_t) ((tcr2_tpsc + MTU3_TPSC_OFS_ARRAY_CH5) - 1U);
+        }
+        else
+        {
+            /* Get from the 8th array */
+            tpsc = (uint8_t) ((tcr2_tpsc + MTU3_TPSC_OFS_ARRAY) - 1U);
+        }
+    }
+    else
+    {
+        tpsc = tcr_tpsc;
+    }
+
+    pclk_divisor = mtu3_clk_div[p_instance_ctrl->p_cfg->channel][tpsc];
+
+    pclk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKH);
+
+    return pclk_freq_hz / pclk_divisor;
+}
+
+/*******************************************************************************************************************//**
+ * Calls user callback.
+ *
+ * @param[in]     p_ctrl     Pointer to MTU3 instance control block
+ * @param[in]     event      Event code
+ * @param[in]     capture    Event capture counts (if applicable)
+ **********************************************************************************************************************/
+static void r_mtu3_call_callback (mtu3_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture)
+{
+    timer_callback_args_t args;
+
+    /* Store callback arguments in memory provided by user if available.  This allows callback arguments to be
+     * stored in non-secure memory so they can be accessed by a non-secure callback function. */
+    timer_callback_args_t * p_args = p_ctrl->p_callback_memory;
+    if (NULL == p_args)
+    {
+        /* Store on stack */
+        p_args = &args;
+    }
+    else
+    {
+        /* Save current arguments on the stack in case this is a nested interrupt. */
+        args = *p_args;
+    }
+
+    p_args->event     = event;
+    p_args->capture   = capture;
+    p_args->p_context = p_ctrl->p_context;
+
+    /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */
+    p_ctrl->p_callback(p_args);
+
+    if (NULL != p_ctrl->p_callback_memory)
+    {
+        /* Restore callback memory in case this is a nested interrupt. */
+        *p_ctrl->p_callback_memory = args;
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Common processing for input capture interrupt.
+ *
+ * @param[in]  event  Which input capture event occurred
+ **********************************************************************************************************************/
+static void r_mtu3_capture_common_isr (mtu3_prv_capture_event_t event)
+{
+    MTU3_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+#endif
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+    uint32_t               counter         = 0U;
+
+    /* Get captured value. */
+    if (event == MTU3_PRV_CAPTURE_EVENT_A)
+    {
+        if (MTU3_CHANNEL_8 == p_instance_ctrl->p_cfg->channel)
+        {
+            counter =
+                *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]);
+        }
+        else
+        {
+            counter =
+                *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                        tgra_ofs_addr[p_instance_ctrl->p_cfg->channel]);
+        }
+
+        /* TSR.TGFA Flag Clear(MTU ch1-ch4, ch6-ch7) */
+        if (((p_instance_ctrl->p_cfg->channel >= MTU3_CHANNEL_1) &&
+             (p_instance_ctrl->p_cfg->channel <= MTU3_CHANNEL_4)) ||
+            ((p_instance_ctrl->p_cfg->channel >= MTU3_CHANNEL_6) &&
+             (p_instance_ctrl->p_cfg->channel <= MTU3_CHANNEL_7)))
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tsr_ofs_addr[p_instance_ctrl->p_cfg->channel]) &= (uint8_t) ~R_MTU1_TSR_TGFA_Msk;
+        }
+    }
+    else if (event == MTU3_PRV_CAPTURE_EVENT_B)
+    {
+        if (MTU3_CHANNEL_8 == p_instance_ctrl->p_cfg->channel)
+        {
+            counter =
+                *(uint32_t *) ((uint8_t *) p_instance_ctrl->p_reg + tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                               MTU3_TGRB_D_OFFSET_LONG);
+        }
+        else
+        {
+            counter =
+                *(volatile uint16_t *) ((uint8_t *) p_instance_ctrl->p_reg +
+                                        tgra_ofs_addr[p_instance_ctrl->p_cfg->channel] +
+                                        MTU3_TGRB_D_OFFSET_WORD);
+        }
+
+        /* TSR.TGFB Flag Clear(MTU ch1-ch4, ch6-ch7) */
+        if (((p_instance_ctrl->p_cfg->channel >= MTU3_CHANNEL_1) &&
+             (p_instance_ctrl->p_cfg->channel <= MTU3_CHANNEL_4)) ||
+            ((p_instance_ctrl->p_cfg->channel >= MTU3_CHANNEL_6) &&
+             (p_instance_ctrl->p_cfg->channel <= MTU3_CHANNEL_7)))
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tsr_ofs_addr[p_instance_ctrl->p_cfg->channel]) &= (uint8_t) ~R_MTU1_TSR_TGFB_Msk;
+        }
+    }
+    else
+    {
+#if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+        if (event == MTU3_PRV_CAPTURE_EVENT_U)
+        {
+            counter = R_MTU5->TGRU;
+        }
+        else if (event == MTU3_PRV_CAPTURE_EVENT_V)
+        {
+            counter = R_MTU5->TGRV;
+        }
+        else
+        {
+            counter = R_MTU5->TGRW;
+        }
+#endif
+    }
+
+    /* If a callback is provided, then call it with the captured counter value. */
+    if (NULL != p_instance_ctrl->p_callback)
+    {
+        r_mtu3_call_callback(p_instance_ctrl,
+                             (timer_event_t) ((uint32_t) TIMER_EVENT_CAPTURE_A + (uint32_t) event),
+                             counter);
+    }
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+#endif
+    MTU3_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+/*******************************************************************************************************************//**
+ * Calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void mtu3_counter_overflow_isr (void)
+{
+    MTU3_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+#endif
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    if (NULL != p_instance_ctrl->p_callback)
+    {
+        r_mtu3_call_callback(p_instance_ctrl, TIMER_EVENT_CYCLE_END, 0);
+    }
+
+#if (0 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+#endif
+
+    MTU3_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture A source.
+ *
+ * Calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void mtu3_capture_a_isr (void)
+{
+    r_mtu3_capture_common_isr(MTU3_PRV_CAPTURE_EVENT_A);
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture B source.
+ *
+ * Calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void mtu3_capture_b_isr (void)
+{
+    r_mtu3_capture_common_isr(MTU3_PRV_CAPTURE_EVENT_B);
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture U source.(ch5)
+ *
+ * Calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void mtu3_capture_u_isr (void)
+{
+    r_mtu3_capture_common_isr(MTU3_PRV_CAPTURE_EVENT_U);
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture V source.(ch5)
+ *
+ * Calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void mtu3_capture_v_isr (void)
+{
+    r_mtu3_capture_common_isr(MTU3_PRV_CAPTURE_EVENT_V);
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture W source.(ch5)
+ *
+ * Calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void mtu3_capture_w_isr (void)
+{
+    r_mtu3_capture_common_isr(MTU3_PRV_CAPTURE_EVENT_W);
+}
+
+/*******************************************************************************************************************//**
+ * Performs mtu3_count_mode_set.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ * @param[in]  mode                   Set the mode.
+ **********************************************************************************************************************/
+static void mtu3_count_mode_set (mtu3_instance_ctrl_t * const p_instance_ctrl, mtu3_phase_counting_mode_t mode)
+{
+    switch (mode)
+    {
+        case MTU3_PHASE_COUNTING_MODE_1:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_1_MD;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_200:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_2_MD;
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_PCB_0;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_201:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_2_MD;
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_PCB_1;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_210:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_2_MD;
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_PCB_2;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_300:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_3_MD;
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_PCB_0;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_301:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_3_MD;
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_PCB_1;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_310:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_3_MD;
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_PCB_2;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_4:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_4_MD;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_50:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_5_MD;
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_PCB_0;
+            break;
+        }
+
+        case MTU3_PHASE_COUNTING_MODE_51:
+        {
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tmdr1_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_5_MD;
+            *((uint8_t *) p_instance_ctrl->p_reg +
+              tcr2_ofs_addr[p_instance_ctrl->p_cfg->channel]) = MTU3_PHASE_COUNTING_MODE_PCB_1;
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+}
+
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+
+/* Processing for MTU3_GPT_Interrupt */
+
+/*******************************************************************************************************************//**
+ * Enable  GPT/MTU3 Interrupt Select Register.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ **********************************************************************************************************************/
+static void mtu3_gpt_INT0_4_interrupt_enable (mtu3_instance_ctrl_t * const p_instance_ctrl)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Table IRQ for mtu3 */
+    IRQn_Type mtu3_irq[MTU3_IRQ] =
+    {
+        p_extend->capture_a_irq,
+        p_extend->capture_b_irq,
+        p_instance_ctrl->p_cfg->cycle_end_irq
+    };
+
+    uint8_t mtu3_irq_select[MTU3_IRQ_SELECT] =
+    {
+        p_extend->capture_a_source_select,
+        p_extend->capture_b_source_select,
+        p_extend->cycle_end_source_select
+    };
+
+    bsp_irq_gpt_selected_event_t gpt_selected_event[GPT_EVENT_SELECT] =
+    {
+        p_extend->capture_a_select_event,
+        p_extend->capture_b_select_event,
+        p_extend->cycle_end_select_event
+    };
+
+    /* Table interrupt function in mtu3 */
+    void (* irq_mtu3[MTU3_IRQ_FUNCTION])(void) =
+    {
+        mtu3_capture_a_isr,
+        mtu3_capture_b_isr,
+        mtu3_counter_overflow_isr
+    };
+
+    for (int gpt_int_num = 0; gpt_int_num < 3; gpt_int_num++)
+    {
+        if (mtu3_irq[gpt_int_num] > FSP_INVALID_VECTOR)
+        {
+            if (GPT_INT4 != mtu3_irq_select[gpt_int_num])
+            {
+                R_BSP_IrqGptSelectedSet(mtu3_irq[gpt_int_num], gpt_selected_event[gpt_int_num]);
+            }
+            else
+            {
+                R_BSP_IrqGptCombinedTableSet(mtu3_irq[gpt_int_num],
+                                             gpt_combined[p_instance_ctrl->p_cfg->channel][gpt_int_num],
+                                             p_instance_ctrl,
+                                             irq_mtu3[gpt_int_num]);
+                R_BSP_IrqGptCombinedMaskClear(mtu3_irq[gpt_int_num],
+                                              gpt_combined[p_instance_ctrl->p_cfg->channel][gpt_int_num]);
+            }
+        }
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Disable  GPT/MTU3 Interrupt Select Register.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ **********************************************************************************************************************/
+static void mtu3_gpt_INT0_4_interrupt_disable (mtu3_instance_ctrl_t * const p_instance_ctrl)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+    /* Table IRQ for mtu3 */
+    IRQn_Type mtu3_irq[MTU3_IRQ] =
+    {
+        p_extend->capture_a_irq,
+        p_extend->capture_b_irq,
+        p_instance_ctrl->p_cfg->cycle_end_irq
+    };
+
+    uint8_t mtu3_irq_select[MTU3_IRQ_SELECT] =
+    {
+        p_extend->capture_a_source_select,
+        p_extend->capture_b_source_select,
+        p_extend->cycle_end_source_select
+    };
+
+    for (int gpt_int_num = 0; gpt_int_num < 3; gpt_int_num++)
+    {
+        if (mtu3_irq[gpt_int_num] > FSP_INVALID_VECTOR)
+        {
+            if ((uint8_t) GPT_INT4 != mtu3_irq_select[gpt_int_num])
+            {
+                R_BSP_IrqGptSelectedClear(mtu3_irq[gpt_int_num]);
+            }
+            else
+            {
+                R_BSP_IrqGptCombinedMaskSet(mtu3_irq[gpt_int_num],
+                                            gpt_combined[p_instance_ctrl->p_cfg->channel][gpt_int_num]);
+                R_BSP_IrqGptCombinedTableClear(mtu3_irq[gpt_int_num],
+                                               gpt_combined[p_instance_ctrl->p_cfg->channel][gpt_int_num]);
+            }
+        }
+    }
+}
+
+/* Processing for MTU3_Channel_5_GPT_Interrupt */
+ #if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+
+/*******************************************************************************************************************//**
+ * Enable  GPT/MTU3 Interrupt Select Register.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ **********************************************************************************************************************/
+static void mtu3_gpt_channel_5_interrupt_enable (mtu3_instance_ctrl_t * const p_instance_ctrl)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t           * p_extend  = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+    mtu3_extended_uvw_cfg_t const * p_uvw_cfg = p_extend->p_uvw_cfg;
+
+    /* Table IRQ for mtu3 */
+    IRQn_Type mtu3_irq[MTU3_IRQ] =
+    {
+        p_uvw_cfg->capture_u_irq,
+        p_uvw_cfg->capture_v_irq,
+        p_uvw_cfg->capture_w_irq
+    };
+
+    /* Table interrupt function in mtu3 */
+    void (* irq_mtu3[MTU3_IRQ_FUNCTION])(void) =
+    {
+        mtu3_capture_u_isr,
+        mtu3_capture_v_isr,
+        mtu3_capture_w_isr
+    };
+
+    bsp_irq_gpt_selected_event_t gpt_selected_event[GPT_EVENT_SELECT] =
+    {
+        p_uvw_cfg->capture_u_select_event,
+        p_uvw_cfg->capture_v_select_event,
+        p_uvw_cfg->capture_w_select_event,
+    };
+
+    for (int gpt_int_num = 0; gpt_int_num < 3; gpt_int_num++)
+    {
+        if (mtu3_irq[gpt_int_num] > FSP_INVALID_VECTOR)
+        {
+            if ((MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel) && (GPT_INT4 != mtu3_irq[gpt_int_num]))
+            {
+                R_BSP_IrqGptSelectedSet(mtu3_irq[gpt_int_num], gpt_selected_event[gpt_int_num]);
+            }
+            else
+            {
+                R_BSP_IrqGptCombinedTableSet(mtu3_irq[gpt_int_num],
+                                             gpt_combined[p_instance_ctrl->p_cfg->channel][gpt_int_num],
+                                             p_instance_ctrl,
+                                             irq_mtu3[gpt_int_num]);
+                R_BSP_IrqGptCombinedMaskClear(mtu3_irq[gpt_int_num],
+                                              gpt_combined[p_instance_ctrl->p_cfg->channel][gpt_int_num]);
+            }
+        }
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Disable  GPT/MTU3 Interrupt Select Register.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ **********************************************************************************************************************/
+static void mtu3_gpt_channel_5_interrupt_disable (mtu3_instance_ctrl_t * const p_instance_ctrl)
+{
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t           * p_extend  = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+    mtu3_extended_uvw_cfg_t const * p_uvw_cfg = p_extend->p_uvw_cfg;
+
+    /* Table IRQ channel 5 for mtu3 */
+    IRQn_Type mtu3_irq[MTU3_IRQ] =
+    {
+        p_uvw_cfg->capture_u_irq,
+        p_uvw_cfg->capture_v_irq,
+        p_uvw_cfg->capture_w_irq
+    };
+
+    for (int gpt_int_num = 0; gpt_int_num < 3; gpt_int_num++)
+    {
+        if (mtu3_irq[gpt_int_num] > FSP_INVALID_VECTOR)
+        {
+            {
+                if ((MTU3_CHANNEL_5 == p_instance_ctrl->p_cfg->channel) && (GPT_INT4 != mtu3_irq[gpt_int_num]))
+                {
+                    R_BSP_IrqGptSelectedClear(mtu3_irq[gpt_int_num]);
+                }
+                else
+                {
+                    R_BSP_IrqGptCombinedMaskSet(mtu3_irq[gpt_int_num],
+                                                gpt_combined[p_instance_ctrl->p_cfg->channel][gpt_int_num]);
+                    R_BSP_IrqGptCombinedTableClear(mtu3_irq[gpt_int_num],
+                                                   gpt_combined[p_instance_ctrl->p_cfg->channel][gpt_int_num]);
+                }
+            }
+        }
+    }
+}
+
+ #endif                                /* #endif (MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE) */
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by GPT_INT_SEL.
+ *
+ * Executes each interrupt process according to the cause of the interrupt.
+ **********************************************************************************************************************/
+void mtu3_int_isr (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    mtu3_instance_ctrl_t * p_instance_ctrl = (mtu3_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Save pointer to extended configuration structure. */
+    mtu3_extended_cfg_t * p_extend = (mtu3_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+ #if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    mtu3_extended_uvw_cfg_t const * p_uvw_cfg = p_extend->p_uvw_cfg;
+ #endif
+
+    if (irq == p_extend->capture_a_irq)
+    {
+        mtu3_capture_a_isr();
+    }
+    else if (irq == p_extend->capture_b_irq)
+    {
+        mtu3_capture_b_isr();
+    }
+
+ #if MTU3_PRV_UVW_FEATURES_ENABLED == MTU3_CFG_UVW_SUPPORT_ENABLE
+    else if (irq == p_uvw_cfg->capture_u_irq)
+    {
+        mtu3_capture_u_isr();
+    }
+    else if (irq == p_uvw_cfg->capture_v_irq)
+    {
+        mtu3_capture_v_isr();
+    }
+    else if (irq == p_uvw_cfg->capture_w_irq)
+    {
+        mtu3_capture_w_isr();
+    }
+ #endif
+    else if (irq == p_instance_ctrl->p_cfg->cycle_end_irq)
+    {
+        mtu3_counter_overflow_isr();
+    }
+    else
+    {
+        /* Do Nothing */
+        ;
+    }
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+}
+
+#endif                                 /* #endif (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED) */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_sci_uart/r_sci_uart.c b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_sci_uart/r_sci_uart.c
new file mode 100644
index 00000000..a073f7b1
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn/fsp/src/r_sci_uart/r_sci_uart.c
@@ -0,0 +1,1920 @@
+/*
+* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_sci_uart.h"
+#include <string.h>
+
+#if SCI_UART_CFG_DMAC_SUPPORTED
+ #include "r_dmac.h"
+#endif
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#ifndef SCI_UART_CFG_RX_ENABLE
+ #define SCI_UART_CFG_RX_ENABLE             1
+#endif
+#ifndef SCI_UART_CFG_TX_ENABLE
+ #define SCI_UART_CFG_TX_ENABLE             1
+#endif
+
+/** Number of divisors in the data table used for baud rate calculation. */
+#define SCI_UART_NUM_DIVISORS_ASYNC         (13U)
+
+/** Valid range of values for the modulation duty register is 128 - 256 (256 = modulation disabled). */
+#define SCI_UART_MDDR_MIN                   (128U)
+#define SCI_UART_MDDR_MAX                   (256U)
+
+/** The bit rate register is 8-bits, so the maximum value is 255. */
+#define SCI_UART_BRR_MAX                    (255U)
+
+/** No limit to the number of bytes to read or write if DMAC is not used. */
+#define SCI_UART_MAX_READ_WRITE_NO_DMAC     (0xFFFFFFFFU)
+
+/** Mask of invalid data bits in 9-bit mode. */
+#define SCI_UART_ALIGN_2_BYTES              (0x1U)
+
+/** Clock frequency 96MHz. */
+#define SCI_UART_CLOCK_96MHZ                (96000000)
+
+/** "SCIU" in ASCII.  Used to determine if the control block is open. */
+#define SCI_UART_OPEN                       (0x53434955U)
+
+#define SCI_UART_BRR_DEFAULT_VALUE          (0xFFU)
+#define SCI_UART_MDDR_DEFAULT_VALUE         (0xFFU)
+#define SCI_UART_FCR_DEFAULT_VALUE          (0x1F1F0000)
+
+#define SCI_UART_CCR0_DEFAULT_VALUE         (0x00000000)
+#define SCI_UART_CCR1_DEFAULT_VALUE         (0x00000010)
+#define SCI_UART_CCR2_DEFAULT_VALUE         (0xFF00FF04)
+#define SCI_UART_CCR3_DEFAULT_VALUE         (0x00001203)
+#define SCI_UART_CCR4_DEFAULT_VALUE         (0x00000000)
+
+#define SCI_UART_CFCLR_ALL_FLAG_CLEAR       (0xBD070010)
+#define SCI_UART_FFCLR_ALL_FLAG_CLEAR       (0x00000001)
+
+/** SCI CCR0 register bit masks */
+#define SCI_UART_CCR0_IDSEL_MASK            (0x00000400)
+#define SCI_UART_CCR0_TEIE_MASK             (0x00200000)
+#define SCI_UART_CCR0_RE_MASK               (0x00000001)
+#define SCI_UART_CCR0_TE_MASK               (0x00000010)
+#define SCI_UART_CCR0_RIE_MASK              (0x00010000)
+#define SCI_UART_CCR0_TIE_MASK              (0x00100000)
+
+/** SCI CCR1 register bit offsets */
+#define SCI_UART_CCR1_CTSE_OFFSET           (0U)
+#define SCI_UART_CCR1_SPB2DT_BIT            (4U)
+#define SCI_UART_CCR1_OUTPUT_ENABLE_MASK    (0x00000020)
+#define SCI_UART_CCR1_PARITY_OFFSET         (8U)
+#define SCI_UART_CCR1_PARITY_MASK           (0x00000300U)
+#define SCI_UART_CCR1_FLOW_CTSRTS_MASK      (0x00000003U)
+#define SCI_UART_CCR1_NFCS_OFFSET           (24U)
+#define SCI_UART_CCR1_NFCS_VALUE_MASK       (0x07U)
+#define SCI_UART_CCR1_NFEN_OFFSET           (28U)
+
+/** SCI CCR2 register bit offsets */
+#define SCI_UART_CCR2_BRME_OFFSET           (16U)
+#define SCI_UART_CCR2_ABCSE_OFFSET          (6U)
+#define SCI_UART_CCR2_ABCS_OFFSET           (5U)
+#define SCI_UART_CCR2_BDGM_OFFSET           (4U)
+#define SCI_UART_CCR2_CKS_OFFSET            (20U)
+#define SCI_UART_CCR2_CKS_VALUE_MASK        (0x03U) ///< CKS: 2 bits
+#define SCI_UART_CCR2_BRR_OFFSET            (8U)
+#define SCI_UART_CCR2_BRR_VALUE_MASK        (0xFFU) ///< BRR: 8bits
+#define SCI_UART_CCR2_MDDR_OFFSET           (24U)
+#define SCI_UART_CCR2_MDDR_VALUE_MASK       (0xFFU) ///< MDDR: 8bits
+
+#define SCI_UART_CCR2_BAUD_SETTING_MASK     ((1U << SCI_UART_CCR2_BRME_OFFSET) |                          \
+                                             (1U << SCI_UART_CCR2_ABCSE_OFFSET) |                         \
+                                             (1U << SCI_UART_CCR2_ABCS_OFFSET) |                          \
+                                             (1U << SCI_UART_CCR2_BDGM_OFFSET) |                          \
+                                             (SCI_UART_CCR2_CKS_VALUE_MASK << SCI_UART_CCR2_CKS_OFFSET) | \
+                                             (SCI_UART_CCR2_BRR_VALUE_MASK << SCI_UART_CCR2_BRR_OFFSET) | \
+                                             (SCI_UART_CCR2_MDDR_VALUE_MASK << SCI_UART_CCR2_MDDR_OFFSET))
+
+/** SCI CCR3 register bit masks */
+#define SCI_UART_CCR3_BPEN_OFFSET           (7U)
+#define SCI_UART_CCR3_CHR_OFFSET            (8U)
+#define SCI_UART_CCR3_STP_OFFSET            (14U)
+#define SCI_UART_CCR3_RxDSEL_OFFSET         (15U)
+#define SCI_UART_CCR3_FM_OFFSET             (20U)
+#define SCI_UART_CCR3_CKE_OFFSET            (24U)
+#define SCI_UART_CCR3_CKE_MASK              (0x03000000U)
+#define SCI_UART_CCR3_CKE_VALUE_MASK        (0x03U)
+
+/** SCI CSR register receiver error bit masks */
+#define SCI_UART_CSR_ORER_MASK              (0x01000000)
+#define SCI_UART_CSR_FER_MASK               (0x10000000)
+#define SCI_UART_CSR_PER_MASK               (0x08000000)
+#define SCI_UART_RCVR_ERR_MASK              (SCI_UART_CSR_ORER_MASK | SCI_UART_CSR_FER_MASK | SCI_UART_CSR_PER_MASK)
+
+/** SCI CFCLR register receiver clear error bit masks */
+#define SCI_UART_CFCLR_ORERC_MASK           (0x01000000)
+#define SCI_UART_CFCLR_FERC_MASK            (0x10000000)
+#define SCI_UART_CFCLE_PERC_MASK            (0x08000000)
+#define SCI_UART_RCVR_ERRCLR_MASK           (SCI_UART_CFCLR_ORERC_MASK | SCI_UART_CFCLR_FERC_MASK | \
+                                             SCI_UART_CFCLE_PERC_MASK)
+
+#define SCI_REG_SIZE                        (R_SCI1_BASE - R_SCI0_BASE)
+
+#define SCI_UART_INVALID_8BIT_PARAM         (0xFFU)
+#define SCI_UART_INVALID_16BIT_PARAM        (0xFFFFU)
+
+#define SCI_UART_TDR_9BIT_MASK              (0x1FFU)
+
+#define SCI_UART_FCR_TRIGGER_MASK           (0xF)
+#define SCI_UART_FCR_RSTRG_OFFSET           (24U)
+#define SCI_UART_FCR_RTRG_OFFSET            (16U)
+#define SCI_UART_FCR_TTRG_OFFSET            (8U)
+#define SCI_UART_FCR_TTRG_DMAC_VALUE        (0x0F)
+#define SCI_UART_FCR_RESET_TX_RX            (0x00808000)
+
+#define SCI_UART_DMAC_MAX_TRANSFER          (0xFFFFFFFFU)
+
+/***********************************************************************************************************************
+ * Private constants
+ **********************************************************************************************************************/
+static const int32_t SCI_UART_100_PERCENT_X_1000 = 100000;
+static const int32_t SCI_UART_MDDR_DIVISOR       = 256;
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+static const uint32_t SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 = 15000;
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef struct st_baud_setting_const_t
+{
+    uint8_t bgdm  : 1;                 /**< BGDM value to get divisor */
+    uint8_t abcs  : 1;                 /**< ABCS value to get divisor */
+    uint8_t abcse : 1;                 /**< ABCSE value to get divisor */
+    uint8_t cks   : 2;                 /**< CKS  value to get divisor (CKS = N) */
+} baud_setting_const_t;
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+
+static fsp_err_t r_sci_read_write_param_check(sci_uart_instance_ctrl_t const * const p_instance_ctrl,
+                                              uint8_t const * const                  addr,
+                                              uint32_t const                         bytes);
+
+#endif
+
+static void r_sci_uart_config_set(sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg);
+
+#if SCI_UART_CFG_DMAC_SUPPORTED
+static fsp_err_t r_sci_uart_transfer_configure(sci_uart_instance_ctrl_t * const p_instance_ctrl,
+                                               transfer_instance_t const      * p_transfer,
+                                               uint32_t                       * p_transfer_reg,
+                                               uint32_t                         address);
+
+static fsp_err_t r_sci_uart_transfer_open(sci_uart_instance_ctrl_t * const p_instance_ctrl,
+                                          uart_cfg_t const * const         p_cfg);
+
+static void r_sci_uart_transfer_close(sci_uart_instance_ctrl_t * p_instance_ctrl);
+
+#endif
+
+static void r_sci_uart_baud_set(R_SCI0_Type * p_sci_reg, sci_baud_setting_t const * const p_baud_setting);
+static void r_sci_uart_call_callback(sci_uart_instance_ctrl_t * p_instance_ctrl, uint32_t data, uart_event_t event);
+
+#if SCI_UART_CFG_FIFO_SUPPORT
+static void r_sci_uart_fifo_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl);
+
+#endif
+
+static void r_sci_irq_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl, uint8_t const ipl, IRQn_Type const p_irq);
+
+static void r_sci_irqs_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg);
+
+#if (SCI_UART_CFG_TX_ENABLE)
+void r_sci_uart_write_no_transfer(sci_uart_instance_ctrl_t * const p_instance_ctrl);
+
+#endif
+
+#if (SCI_UART_CFG_RX_ENABLE)
+void r_sci_uart_rxi_read_no_transfer(sci_uart_instance_ctrl_t * const p_instance_ctrl);
+
+static void sci_uart_rxi_common(sci_uart_instance_ctrl_t * p_instance_ctrl);
+
+void sci_uart_rxi_isr(void);
+
+void sci_uart_rx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl);
+
+void r_sci_uart_read_data(sci_uart_instance_ctrl_t * const p_instance_ctrl, uint32_t * const p_data);
+
+void sci_uart_eri_isr(void);
+
+#endif
+
+#if (SCI_UART_CFG_TX_ENABLE)
+static void sci_uart_txi_common(sci_uart_instance_ctrl_t * p_instance_ctrl);
+
+void sci_uart_txi_isr(void);
+
+void sci_uart_tx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl);
+
+void sci_uart_tei_isr(void);
+
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/** Name of module used by error logger macro */
+#if BSP_CFG_ERROR_LOG != 0
+static const char g_module_name[] = "sci_uart";
+#endif
+
+/** Baud rate divisor information (UART mode) */
+static const baud_setting_const_t g_async_baud[SCI_UART_NUM_DIVISORS_ASYNC] =
+{
+    {0U, 0U, 1U, 0U},                  /* BGDM, ABCS, ABCSE, n */
+    {1U, 1U, 0U, 0U},
+    {1U, 0U, 0U, 0U},
+    {0U, 0U, 1U, 1U},
+    {0U, 0U, 0U, 0U},
+    {1U, 0U, 0U, 1U},
+    {0U, 0U, 1U, 2U},
+    {0U, 0U, 0U, 1U},
+    {1U, 0U, 0U, 2U},
+    {0U, 0U, 1U, 3U},
+    {0U, 0U, 0U, 2U},
+    {1U, 0U, 0U, 3U},
+    {0U, 0U, 0U, 3U}
+};
+
+static const uint16_t g_div_coefficient[SCI_UART_NUM_DIVISORS_ASYNC] =
+{
+    6U,
+    8U,
+    16U,
+    24U,
+    32U,
+    64U,
+    96U,
+    128U,
+    256U,
+    384U,
+    512U,
+    1024U,
+    2048U,
+};
+
+/** UART on SCI HAL API mapping for UART interface */
+const uart_api_t g_uart_on_sci =
+{
+    .open               = R_SCI_UART_Open,
+    .close              = R_SCI_UART_Close,
+    .write              = R_SCI_UART_Write,
+    .read               = R_SCI_UART_Read,
+    .infoGet            = R_SCI_UART_InfoGet,
+    .baudSet            = R_SCI_UART_BaudSet,
+    .communicationAbort = R_SCI_UART_Abort,
+    .callbackSet        = R_SCI_UART_CallbackSet,
+    .readStop           = R_SCI_UART_ReadStop,
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup SCI_UART
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Configures the UART driver based on the input configurations.  If reception is enabled at compile time, reception is
+ * enabled at the end of this function. Implements @ref uart_api_t::open
+ *
+ * @retval  FSP_SUCCESS                    Channel opened successfully.
+ * @retval  FSP_ERR_ASSERTION              Pointer to UART control block or configuration structure is NULL.
+ * @retval  FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU.
+ * @retval  FSP_ERR_ALREADY_OPEN           Control block has already been opened or channel is being used by another
+ *                                         instance. Call close() then open() to reconfigure.
+ * @retval  FSP_ERR_INVALID_ARGUMENT       Invalid input parameter.
+ *
+ * @return                       See @ref RENESAS_ERROR_CODES or functions called by this function for other possible
+ *                               return codes. This function calls:
+ *                                   * @ref transfer_api_t::open
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg)
+{
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Check parameters. */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(p_cfg);
+    FSP_ASSERT(p_cfg->p_callback);
+    FSP_ASSERT(p_cfg->p_extend);
+    FSP_ASSERT(((sci_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting);
+    FSP_ERROR_RETURN(SCI_UART_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
+    /* Make sure this channel exists. */
+    FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+  #if (SCI_UART_CFG_RX_ENABLE)
+    if (NULL != p_cfg->p_transfer_rx)
+    {
+        /* DMAC activation is not available for safety channel. */
+        FSP_ERROR_RETURN(BSP_FEATURE_SCI_SAFETY_CHANNEL != p_cfg->channel, FSP_ERR_INVALID_ARGUMENT);
+    }
+  #endif
+  #if (SCI_UART_CFG_TX_ENABLE)
+    if (NULL != p_cfg->p_transfer_tx)
+    {
+        /* DMAC activation is not available for safety channel. */
+        FSP_ERROR_RETURN(BSP_FEATURE_SCI_SAFETY_CHANNEL != p_cfg->channel, FSP_ERR_INVALID_ARGUMENT);
+    }
+  #endif
+ #endif
+
+    if (SCI_UART_FLOW_CONTROL_CTSRTS == ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control)
+    {
+        FSP_ERROR_RETURN(
+            ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM,
+            FSP_ERR_INVALID_ARGUMENT);
+    }
+
+    if (SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS == ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control)
+    {
+        FSP_ERROR_RETURN((0U != (((1U << (p_cfg->channel)) & BSP_FEATURE_SCI_UART_CTSPEN_CHANNELS))),
+                         FSP_ERR_INVALID_ARGUMENT);
+    }
+
+    FSP_ASSERT(UART_PARITY_ZERO != p_cfg->parity);
+    FSP_ASSERT(p_cfg->rxi_irq >= 0);
+    FSP_ASSERT(p_cfg->txi_irq >= 0);
+    FSP_ASSERT(p_cfg->tei_irq >= 0);
+    FSP_ASSERT(p_cfg->eri_irq >= 0);
+#endif
+
+    p_instance_ctrl->fifo_depth = 0U;
+#if SCI_UART_CFG_FIFO_SUPPORT
+
+    /* Check if the channel supports fifo */
+    if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS & (1U << p_cfg->channel))
+    {
+        p_instance_ctrl->fifo_depth = BSP_FEATURE_SCI_UART_FIFO_DEPTH;
+    }
+#endif
+
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    p_instance_ctrl->p_callback        = p_cfg->p_callback;
+    p_instance_ctrl->p_context         = p_cfg->p_context;
+    p_instance_ctrl->p_callback_memory = NULL;
+    sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend;
+
+    p_instance_ctrl->data_bytes = 1U;
+    if (UART_DATA_BITS_9 == p_cfg->data_bits)
+    {
+        p_instance_ctrl->data_bytes = 2U;
+    }
+
+    /* Configure the interrupts. */
+    r_sci_irqs_cfg(p_instance_ctrl, p_cfg);
+
+    /* Enable the SCI channel and reset the registers to their initial state. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+    R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel);
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+    if (p_cfg->channel != BSP_FEATURE_SCI_SAFETY_CHANNEL)
+    {
+        /* Non-Safety Peripheral */
+        p_instance_ctrl->p_reg =
+            (R_SCI0_Type *) ((uintptr_t) R_SCI0 + (p_cfg->channel * ((uintptr_t) R_SCI1 - (uintptr_t) R_SCI0)));
+    }
+    else
+    {
+        /* Safety Peripheral */
+        p_instance_ctrl->p_reg = (R_SCI0_Type *) BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS;
+    }
+
+#if SCI_UART_CFG_DMAC_SUPPORTED
+
+    /* Configure the transfer interface for transmission and reception if provided. */
+    fsp_err_t err = r_sci_uart_transfer_open(p_instance_ctrl, p_cfg);
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+#endif
+
+    p_instance_ctrl->p_reg->CCR0 = SCI_UART_CCR0_DEFAULT_VALUE;
+    FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0);
+    FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0);
+    p_instance_ctrl->p_reg->CCR1 = SCI_UART_CCR1_DEFAULT_VALUE;
+    p_instance_ctrl->p_reg->CCR2 = SCI_UART_CCR2_DEFAULT_VALUE;
+    p_instance_ctrl->p_reg->CCR3 = SCI_UART_CCR3_DEFAULT_VALUE;
+    p_instance_ctrl->p_reg->CCR4 = SCI_UART_CCR4_DEFAULT_VALUE;
+
+    /* Set the UART configuration settings provided in ::uart_cfg_t and ::sci_uart_extended_cfg_t. */
+    r_sci_uart_config_set(p_instance_ctrl, p_cfg);
+
+    p_instance_ctrl->p_reg->CFCLR = SCI_UART_CFCLR_ALL_FLAG_CLEAR;
+
+#if SCI_UART_CFG_FIFO_SUPPORT
+    p_instance_ctrl->p_reg->FFCLR = SCI_UART_FFCLR_ALL_FLAG_CLEAR;
+#endif
+
+    p_instance_ctrl->p_tx_src      = NULL;
+    p_instance_ctrl->tx_src_bytes  = 0U;
+    p_instance_ctrl->p_rx_dest     = NULL;
+    p_instance_ctrl->rx_dest_bytes = 0;
+
+    uint32_t ccr0 = SCI_UART_CCR0_IDSEL_MASK;
+#if (SCI_UART_CFG_RX_ENABLE)
+
+    /* If reception is enabled at build time, enable reception. */
+    /* NOTE: Transmitter and its interrupt are enabled in R_SCI_UART_Write(). */
+    R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq);
+    R_BSP_IrqEnable(p_instance_ctrl->p_cfg->eri_irq);
+
+    ccr0 |= (SCI_UART_CCR0_RIE_MASK | SCI_UART_CCR0_RE_MASK);
+#endif
+
+#if (SCI_UART_CFG_TX_ENABLE)
+    R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq);
+    R_BSP_IrqEnable(p_instance_ctrl->p_cfg->tei_irq);
+
+    ccr0 |= SCI_UART_CCR0_TE_MASK;
+#endif
+    p_instance_ctrl->p_reg->CCR0 = ccr0;
+
+    FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 1);
+    FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 1);
+
+    /* Set flow control pins. */
+    p_instance_ctrl->flow_pin = p_extend->flow_control_pin;
+
+#if SCI_UART_CFG_FLOW_CONTROL_SUPPORT
+    if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM)
+    {
+        R_BSP_PinAccessEnable();
+        R_BSP_PinClear(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin);
+        R_BSP_PinAccessDisable();
+    }
+#endif
+
+    p_instance_ctrl->open = SCI_UART_OPEN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer
+ * drivers if used. Removes power. Implements @ref uart_api_t::close
+ *
+ * @retval  FSP_SUCCESS              Channel successfully closed.
+ * @retval  FSP_ERR_ASSERTION        Pointer to UART control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN         The control block has not been opened
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_Close (uart_ctrl_t * const p_ctrl)
+{
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Mark the channel not open so other APIs cannot use it. */
+    p_instance_ctrl->open = 0U;
+
+    /* Disable interrupts, receiver, and transmitter. Disable baud clock output.*/
+    p_instance_ctrl->p_reg->CCR0 = SCI_UART_CCR0_DEFAULT_VALUE;
+    FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0);
+    FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0);
+    p_instance_ctrl->p_reg->CCR3 &= ~(SCI_UART_CCR3_CKE_MASK);
+
+#if (SCI_UART_CFG_RX_ENABLE)
+
+    /* If reception is enabled at build time, disable reception irqs. */
+    R_BSP_IrqDisable(p_instance_ctrl->p_cfg->rxi_irq);
+    R_BSP_IrqDisable(p_instance_ctrl->p_cfg->eri_irq);
+#endif
+#if (SCI_UART_CFG_TX_ENABLE)
+
+    /* If transmission is enabled at build time, disable transmission irqs. */
+    R_BSP_IrqDisable(p_instance_ctrl->p_cfg->txi_irq);
+    R_BSP_IrqDisable(p_instance_ctrl->p_cfg->tei_irq);
+#endif
+#if SCI_UART_CFG_DMAC_SUPPORTED
+
+    /* Close the lower level transfer instances. */
+    r_sci_uart_transfer_close(p_instance_ctrl);
+#endif
+
+    /* Remove power to the channel. */
+    /* Disable the clock to the SCI channel. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+    R_BSP_MODULE_STOP(FSP_IP_SCI, p_instance_ctrl->p_cfg->channel);
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read
+ *
+ * @retval  FSP_SUCCESS                  Data reception successfully ends.
+ * @retval  FSP_ERR_ASSERTION            Pointer to UART control block is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT     Destination address or data size is not valid for 9-bit mode.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened
+ * @retval  FSP_ERR_IN_USE               A previous read operation is still in progress.
+ * @retval  FSP_ERR_UNSUPPORTED          SCI_UART_CFG_RX_ENABLE is set to 0
+ *
+ * @return                       See @ref RENESAS_ERROR_CODES or functions called by this function for other possible
+ *                               return codes. This function calls:
+ *                                   * @ref transfer_api_t::reconfigure
+ *
+ * @note If 9-bit data length is specified at R_SCI_UART_Open call, p_dest must be aligned 16-bit boundary.
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_Read (uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes)
+{
+#if (SCI_UART_CFG_RX_ENABLE)
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+    fsp_err_t err = FSP_SUCCESS;
+
+ #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    err = r_sci_read_write_param_check(p_instance_ctrl, p_dest, bytes);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+    FSP_ERROR_RETURN(0U == p_instance_ctrl->rx_dest_bytes, FSP_ERR_IN_USE);
+ #endif
+
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+
+    /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */
+    if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx)
+    {
+        p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = (void *) p_dest;
+        p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = bytes;
+
+        /* Disable the corresponding IRQ when transferring using DMAC. */
+        R_BSP_IrqDisable(p_instance_ctrl->p_cfg->rxi_irq);
+
+        err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl,
+                                                                        p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info);
+        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+    }
+ #endif
+
+    /* Save the destination address and size for use in rxi_isr. */
+    p_instance_ctrl->p_rx_dest     = p_dest;
+    p_instance_ctrl->rx_dest_bytes = bytes;
+
+    return err;
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(p_dest);
+    FSP_PARAMETER_NOT_USED(bytes);
+
+    return FSP_ERR_UNSUPPORTED;
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write
+ *
+ * @retval  FSP_SUCCESS                  Data transmission finished successfully.
+ * @retval  FSP_ERR_ASSERTION            Pointer to UART control block is NULL.
+ * @retval  FSP_ERR_INVALID_ARGUMENT     Source address or data size is not valid for 9-bit mode.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened
+ * @retval  FSP_ERR_IN_USE               A UART transmission is in progress
+ * @retval  FSP_ERR_UNSUPPORTED          SCI_UART_CFG_TX_ENABLE is set to 0
+ *
+ * @return                       See @ref RENESAS_ERROR_CODES or functions called by this function for other possible
+ *                               return codes. This function calls:
+ *                                   * @ref transfer_api_t::reconfigure
+ *
+ * @note If 9-bit data length is specified at R_SCI_UART_Open call, p_src must be aligned on a 16-bit boundary.
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_Write (uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes)
+{
+#if (SCI_UART_CFG_TX_ENABLE)
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+ #if SCI_UART_CFG_PARAM_CHECKING_ENABLE || SCI_UART_CFG_DMAC_SUPPORTED
+    fsp_err_t err = FSP_SUCCESS;
+ #endif
+
+ #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    err = r_sci_read_write_param_check(p_instance_ctrl, p_src, bytes);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+    FSP_ERROR_RETURN(0U == p_instance_ctrl->tx_src_bytes, FSP_ERR_IN_USE);
+ #endif
+
+    /* Transmit interrupts must be disabled to start with. */
+    p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK);
+
+    p_instance_ctrl->tx_src_bytes = bytes - p_instance_ctrl->data_bytes;
+    p_instance_ctrl->p_tx_src     = p_src + p_instance_ctrl->data_bytes;
+
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+
+    /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested
+     * data. */
+    if ((NULL != p_instance_ctrl->p_cfg->p_transfer_tx) && p_instance_ctrl->tx_src_bytes)
+    {
+        uint32_t num_transfers = p_instance_ctrl->tx_src_bytes;
+        p_instance_ctrl->tx_src_bytes = 0U;
+
+        p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src  = (void const *) p_instance_ctrl->p_tx_src;
+        p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = num_transfers;
+
+        /* Disable the corresponding IRQ when transferring using DMAC. */
+        R_BSP_IrqDisable(p_instance_ctrl->p_cfg->txi_irq);
+
+        err = p_instance_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl,
+                                                                        p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info);
+        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+    }
+ #endif
+
+    /* Trigger a TXI interrupt. This triggers the transfer instance or a TXI interrupt if the transfer instance is
+     * not used. */
+    p_instance_ctrl->p_reg->CCR0 |= SCI_UART_CCR0_TIE_MASK;
+
+    /* The first byte is sent from this function to trigger the first TXI event.  This
+     * method is used instead of setting TE and TIE at the same time as recommended in the hardware manual to avoid
+     * the one frame delay that occurs when the TE bit is set. */
+    if (2U == p_instance_ctrl->data_bytes)
+    {
+        p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_src)) & SCI_UART_TDR_9BIT_MASK;
+    }
+    else
+    {
+        p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_src);
+    }
+
+ #if SCI_UART_CFG_FIFO_SUPPORT
+
+    /* The behavior of the TDRE flag differs between when FIFO is used and not used.
+     * When using FIFO, clear the flag manually to detect the interrupt at the edge. */
+    p_instance_ctrl->p_reg->CFCLR_b.TDREC = 1;
+ #endif
+
+    return FSP_SUCCESS;
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(p_src);
+    FSP_PARAMETER_NOT_USED(bytes);
+
+    return FSP_ERR_UNSUPPORTED;
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Updates the user callback and has option of providing memory for callback structure.
+ * Implements uart_api_t::callbackSet
+ *
+ * @retval  FSP_SUCCESS                  Callback updated successfully.
+ * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const          p_ctrl,
+                                  void (                     * p_callback)(uart_callback_args_t *),
+                                  void const * const           p_context,
+                                  uart_callback_args_t * const p_callback_memory)
+{
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(p_callback);
+    FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Store callback and context */
+    p_instance_ctrl->p_callback        = p_callback;
+    p_instance_ctrl->p_context         = p_context;
+    p_instance_ctrl->p_callback_memory = p_callback_memory;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a sci_baud_setting_t structure.
+ * Implements @ref uart_api_t::baudSet
+ *
+ * @warning This terminates any in-progress transmission.
+ *
+ * @retval  FSP_SUCCESS                  Baud rate was successfully changed.
+ * @retval  FSP_ERR_ASSERTION            Pointer to UART control block is NULL or the UART is not configured to use the
+ *                                       internal clock.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_ctrl, void const * const p_baud_setting)
+{
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    /* Verify that the On-Chip baud rate generator is currently selected. */
+    FSP_ASSERT((p_instance_ctrl->p_reg->CCR3_b.CKE & 0x2) == 0U);
+#endif
+
+    /* Save CCR0 configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is
+     * not supported. */
+    uint32_t preserved_ccr0 = p_instance_ctrl->p_reg->CCR0 & (uint32_t) ~(R_SCI0_CCR0_TIE_Msk | R_SCI0_CCR0_TEIE_Msk);
+
+    /* Disables transmitter and receiver. This terminates any in-progress transmission. */
+    p_instance_ctrl->p_reg->CCR0 = preserved_ccr0 &
+                                   (uint32_t) ~(R_SCI0_CCR0_TE_Msk | R_SCI0_CCR0_RE_Msk | R_SCI0_CCR0_RIE_Msk);
+    FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0);
+    FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0);
+    p_instance_ctrl->p_tx_src = NULL;
+
+    /* Apply new baud rate register settings. */
+    r_sci_uart_baud_set(p_instance_ctrl->p_reg, p_baud_setting);
+
+    /* Restore all settings except transmit interrupts. */
+    p_instance_ctrl->p_reg->CCR0 = preserved_ccr0;
+    FSP_HARDWARE_REGISTER_WAIT((p_instance_ctrl->p_reg->CCR0 & R_SCI0_CCR0_RE_Msk),
+                               (preserved_ccr0 & R_SCI0_CCR0_RE_Msk));
+    FSP_HARDWARE_REGISTER_WAIT((p_instance_ctrl->p_reg->CCR0 & R_SCI0_CCR0_TE_Msk),
+                               (preserved_ccr0 & R_SCI0_CCR0_TE_Msk));
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time.
+ * Implements @ref uart_api_t::infoGet
+ *
+ * @retval  FSP_SUCCESS                  Information stored in provided p_info.
+ * @retval  FSP_ERR_ASSERTION            Pointer to UART control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_InfoGet (uart_ctrl_t * const p_ctrl, uart_info_t * const p_info)
+{
+#if SCI_UART_CFG_PARAM_CHECKING_ENABLE || SCI_UART_CFG_DMAC_SUPPORTED
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(p_info);
+    FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_info->read_bytes_max  = SCI_UART_MAX_READ_WRITE_NO_DMAC;
+    p_info->write_bytes_max = SCI_UART_MAX_READ_WRITE_NO_DMAC;
+
+#if (SCI_UART_CFG_RX_ENABLE)
+
+    /* Store number of bytes that can be read at a time. */
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+    if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx)
+    {
+        p_info->read_bytes_max = SCI_UART_DMAC_MAX_TRANSFER;
+    }
+ #endif
+#endif
+
+#if (SCI_UART_CFG_TX_ENABLE)
+
+    /* Store number of bytes that can be written at a time. */
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+    if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx)
+    {
+        p_info->write_bytes_max = SCI_UART_DMAC_MAX_TRANSFER;
+    }
+ #endif
+#endif
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted.
+ * Reception is still enabled after abort(). Any characters received after abort() and before the transfer
+ * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR.
+ * Implements @ref uart_api_t::communicationAbort
+ *
+ * @retval  FSP_SUCCESS                  UART transaction aborted successfully.
+ * @retval  FSP_ERR_ASSERTION            Pointer to UART control block is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
+ * @retval  FSP_ERR_UNSUPPORTED          The requested Abort direction is unsupported.
+ *
+ * @return                       See @ref RENESAS_ERROR_CODES or functions called by this function for other possible
+ *                               return codes. This function calls:
+ *                                   * @ref transfer_api_t::disable
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_Abort (uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort)
+{
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+    fsp_err_t err = FSP_ERR_UNSUPPORTED;
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+#if (SCI_UART_CFG_TX_ENABLE)
+    if (UART_DIR_TX & communication_to_abort)
+    {
+        err = FSP_SUCCESS;
+        p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK);
+
+        /* Make sure no transmission is in progress. */
+        FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CSR_b.TEND, 1U);
+
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+        if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx)
+        {
+            err = p_instance_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl);
+
+            /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */
+            R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq);
+        }
+ #endif
+
+ #if SCI_UART_CFG_FIFO_SUPPORT
+        if (0U != p_instance_ctrl->fifo_depth)
+        {
+            /* Reset the transmit fifo */
+            p_instance_ctrl->p_reg->FCR_b.TFRST = 1U;
+        }
+ #endif
+        p_instance_ctrl->tx_src_bytes = 0U;
+
+        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+    }
+#endif
+#if (SCI_UART_CFG_RX_ENABLE)
+    if (UART_DIR_RX & communication_to_abort)
+    {
+        err = FSP_SUCCESS;
+
+        p_instance_ctrl->rx_dest_bytes = 0U;
+
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+        if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx)
+        {
+            err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl);
+
+            /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */
+            R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq);
+        }
+ #endif
+
+ #if SCI_UART_CFG_FIFO_SUPPORT
+        if (0U != p_instance_ctrl->fifo_depth)
+        {
+            /* Reset the receive fifo */
+            p_instance_ctrl->p_reg->FCR_b.RFRST = 1U;
+        }
+ #endif
+    }
+#endif
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort()
+ * and before the transfer is reset in the next call to read(), will arrive via the callback function with event
+ * UART_EVENT_RX_CHAR.
+ * Implements @ref uart_api_t::readStop
+ *
+ * @retval  FSP_SUCCESS                  UART transaction aborted successfully.
+ * @retval  FSP_ERR_ASSERTION            Pointer to UART control block or remaining_bytes is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
+ * @retval  FSP_ERR_UNSUPPORTED          The requested Abort direction is unsupported.
+ *
+ * @return                       See @ref RENESAS_ERROR_CODES or functions called by this function for other possible
+ *                               return codes. This function calls:
+ *                                   * @ref transfer_api_t::disable
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes)
+{
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl;
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(remaining_bytes);
+    FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+#if (SCI_UART_CFG_RX_ENABLE)
+    *remaining_bytes               = p_instance_ctrl->rx_dest_bytes;
+    p_instance_ctrl->rx_dest_bytes = 0U;
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+    if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx)
+    {
+        fsp_err_t err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->disable(
+            p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl);
+        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+        /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */
+        R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq);
+
+        transfer_properties_t transfer_info;
+        err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl,
+                                                                    &transfer_info);
+        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+        *remaining_bytes = transfer_info.transfer_length_remaining;
+    }
+ #endif
+ #if SCI_UART_CFG_FIFO_SUPPORT
+    if (0U != p_instance_ctrl->fifo_depth)
+    {
+        /* Reset the receive fifo */
+        p_instance_ctrl->p_reg->FCR_b.RFRST = 1U;
+    }
+ #endif
+#else
+
+    return FSP_ERR_UNSUPPORTED;
+#endif
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate
+ * related registers.
+ *
+ * @param[in]  p_baud_target             Baudrate calculation configuration.
+ * @param[in]  clock_source              Clock source (PCLKM or SCInASYNCCLK) used for baudrate calculation.
+ * @param[out] p_baud_setting            Baud setting information stored here if successful
+ *
+ * @retval     FSP_SUCCESS               Baud rate is set successfully
+ * @retval     FSP_ERR_ASSERTION         Null pointer
+ * @retval     FSP_ERR_INVALID_ARGUMENT  Baud rate is '0', error in calculated baud rate is larger than requested
+ *                                       max error, or requested max error in baud rate is larger than 15%.
+ *                                       Clock source frequency could not be get.
+ **********************************************************************************************************************/
+fsp_err_t R_SCI_UART_BaudCalculate (sci_uart_baud_calculation_t const * const p_baud_target,
+                                    sci_uart_clock_source_t                   clock_source,
+                                    sci_baud_setting_t * const                p_baud_setting)
+{
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_baud_target);
+    FSP_ASSERT(p_baud_setting);
+    FSP_ERROR_RETURN(SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 >= p_baud_target->baud_rate_error_x_1000,
+                     FSP_ERR_INVALID_ARGUMENT);
+    FSP_ERROR_RETURN((0U != p_baud_target->baudrate), FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_baud_setting->baudrate_bits_b.brr  = SCI_UART_BRR_MAX;
+    p_baud_setting->baudrate_bits_b.brme = 0U;
+    p_baud_setting->baudrate_bits_b.mddr = SCI_UART_MDDR_MIN;
+
+    /* Find the best BRR (bit rate register) value.
+     *  In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values.  Each set of divisors
+     *  is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as
+     *  follows and it must be 255 or less:
+     *  BRR = (PCLK / (div_coefficient * baud)) - 1
+     */
+    int32_t  hit_bit_err = SCI_UART_100_PERCENT_X_1000;
+    uint32_t hit_mddr    = 0U;
+    uint32_t divisor     = 0U;
+
+    uint32_t freq_hz = 0U;
+    if (SCI_UART_CLOCK_SOURCE_PCLKM == clock_source)
+    {
+        freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKM);
+    }
+    else
+    {
+        freq_hz =
+            R_FSP_SystemClockHzGet((fsp_priv_clock_t) ((uint8_t) FSP_PRIV_CLOCK_PCLKSCI0 + (uint8_t) clock_source));
+    }
+
+    FSP_ERROR_RETURN(0U != freq_hz, FSP_ERR_INVALID_ARGUMENT);
+
+    for (uint32_t select_16_base_clk_cycles = 0U;
+         select_16_base_clk_cycles <= 1U && (hit_bit_err > ((int32_t) p_baud_target->baud_rate_error_x_1000));
+         select_16_base_clk_cycles++)
+    {
+        for (uint32_t i = 0U; i < SCI_UART_NUM_DIVISORS_ASYNC; i++)
+        {
+            /* if select_16_base_clk_cycles == true:  Skip this calculation for divisors that are not acheivable with 16 base clk cycles per bit.
+             *  if select_16_base_clk_cycles == false: Skip this calculation for divisors that are only acheivable without 16 base clk cycles per bit.
+             */
+            if (((uint8_t) select_16_base_clk_cycles) ^ (g_async_baud[i].abcs | g_async_baud[i].abcse))
+            {
+                continue;
+            }
+
+            divisor = (uint32_t) g_div_coefficient[i] * p_baud_target->baudrate;
+            uint32_t temp_brr = freq_hz / divisor;
+
+            if (temp_brr <= (SCI_UART_BRR_MAX + 1U))
+            {
+                while (temp_brr > 0U)
+                {
+                    temp_brr -= 1U;
+
+                    /* Calculate the bit rate error. The formula is as follows:
+                     *  bit rate error[%] = {(PCLK / (baud * div_coefficient * (BRR + 1)) - 1} x 100
+                     *  calculates bit rate error[%] to three decimal places
+                     */
+                    int32_t err_divisor = (int32_t) (divisor * (temp_brr + 1U));
+
+                    /* Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as
+                     * described below, so this cast is safe.
+                     *    1. (temp_brr + 1) can be off by an upper limit of 1 due to rounding from the calculation:
+                     *       freq_hz / divisor, or:
+                     *       freq_hz / divisor <= (temp_brr + 1) < (freq_hz / divisor) + 1
+                     *    2. Solving for err_divisor:
+                     *       freq_hz <= err_divisor < freq_hz + divisor
+                     *    3. Solving for bit_err:
+                     *       0 >= bit_err >= (freq_hz * 100000 / (freq_hz + divisor)) - 100000
+                     *    4. freq_hz >= divisor (or temp_brr would be -1 and we would never enter this while loop), so:
+                     *       0 >= bit_err >= 100000 / freq_hz - 100000
+                     *    5. Larger frequencies yield larger bit errors (absolute value).  As the frequency grows,
+                     *       the bit_err approaches -100000, so:
+                     *       0 >= bit_err >= -100000
+                     *    6. bit_err is between -100000 and 0.  This entire range fits in an int32_t type, so the cast
+                     *       to (int32_t) is safe.
+                     */
+                    int32_t bit_err = (int32_t) (((((int64_t) freq_hz) * SCI_UART_100_PERCENT_X_1000) /
+                                                  err_divisor) - SCI_UART_100_PERCENT_X_1000);
+
+                    uint32_t mddr = 0U;
+                    if (p_baud_target->bitrate_modulation)
+                    {
+                        /* Calculate the MDDR (M) value if bit rate modulation is enabled,
+                         * The formula to calculate MBBR (from the M and N relationship given in the hardware manual) is as follows
+                         * and it must be between 128 and 256.
+                         * MDDR = ((div_coefficient * baud * 256) * (BRR + 1)) / PCLK */
+                        mddr = (uint32_t) err_divisor / (freq_hz / SCI_UART_MDDR_MAX);
+
+                        /* The maximum value that could result from the calculation above is 256, which is a valid MDDR
+                         * value, so only the lower bound is checked. */
+                        if (mddr < SCI_UART_MDDR_MIN)
+                        {
+                            break;
+                        }
+
+                        /* Adjust bit rate error for bit rate modulation. The following formula is used:
+                         *  bit rate error [%] = ((bit rate error [%, no modulation] + 100) * MDDR / 256) - 100
+                         */
+                        bit_err = (((bit_err + SCI_UART_100_PERCENT_X_1000) * (int32_t) mddr) /
+                                   SCI_UART_MDDR_DIVISOR) - SCI_UART_100_PERCENT_X_1000;
+                    }
+
+                    /* Take the absolute value of the bit rate error. */
+                    if (bit_err < 0)
+                    {
+                        bit_err = -bit_err;
+                    }
+
+                    /* If the absolute value of the bit rate error is less than the previous lowest absolute value of
+                     *  bit rate error, then store these settings as the best value.
+                     */
+                    if (bit_err < hit_bit_err)
+                    {
+                        p_baud_setting->baudrate_bits_b.bgdm  = g_async_baud[i].bgdm;
+                        p_baud_setting->baudrate_bits_b.abcs  = g_async_baud[i].abcs;
+                        p_baud_setting->baudrate_bits_b.abcse = g_async_baud[i].abcse;
+                        p_baud_setting->baudrate_bits_b.cks   = g_async_baud[i].cks;
+                        p_baud_setting->baudrate_bits_b.brr   = (uint8_t) temp_brr;
+                        hit_bit_err = bit_err;
+                        hit_mddr    = mddr;
+                    }
+
+                    if (p_baud_target->bitrate_modulation)
+                    {
+                        p_baud_setting->baudrate_bits_b.brme = 1U;
+                        p_baud_setting->baudrate_bits_b.mddr = (uint8_t) hit_mddr;
+                    }
+                    else
+                    {
+                        break;
+                    }
+                }
+            }
+        }
+    }
+
+    /* Return an error if the percent error is larger than the maximum percent error allowed for this instance */
+    FSP_ERROR_RETURN((hit_bit_err <= (int32_t) p_baud_target->baud_rate_error_x_1000), FSP_ERR_INVALID_ARGUMENT);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup SCI_UART)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+
+/*******************************************************************************************************************//**
+ * Parameter error check function for read/write.
+ *
+ * @param[in] p_instance_ctrl Pointer to the control block for the channel
+ * @param[in] addr            Pointer to the buffer
+ * @param[in] bytes           Number of bytes to read or write
+ *
+ * @retval  FSP_SUCCESS              No parameter error found
+ * @retval  FSP_ERR_NOT_OPEN         The control block has not been opened
+ * @retval  FSP_ERR_ASSERTION        Pointer to UART control block or configuration structure is NULL
+ * @retval  FSP_ERR_INVALID_ARGUMENT Address is not aligned to 2-byte boundary or size is the odd number when the data
+ *                                   length is 9-bit
+ **********************************************************************************************************************/
+static fsp_err_t r_sci_read_write_param_check (sci_uart_instance_ctrl_t const * const p_instance_ctrl,
+                                               uint8_t const * const                  addr,
+                                               uint32_t const                         bytes)
+{
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(addr);
+    FSP_ASSERT(0U != bytes);
+    FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    if (2U == p_instance_ctrl->data_bytes)
+    {
+        /* Do not allow odd buffer address if data length is 9 bits. */
+        FSP_ERROR_RETURN((0U == ((uintptr_t) addr & SCI_UART_ALIGN_2_BYTES)), FSP_ERR_INVALID_ARGUMENT);
+
+        /* Do not allow odd number of data bytes if data length is 9 bits. */
+        FSP_ERROR_RETURN(0U == (bytes % 2U), FSP_ERR_INVALID_ARGUMENT);
+    }
+
+    return FSP_SUCCESS;
+}
+
+#endif
+
+#if SCI_UART_CFG_DMAC_SUPPORTED
+
+/*******************************************************************************************************************//**
+ * Subroutine to apply common UART transfer settings.
+ *
+ * @param[in]  p_cfg              Pointer to UART specific configuration structure
+ * @param[in]  p_transfer         Pointer to transfer instance to configure
+ *
+ * @retval     FSP_SUCCESS        UART transfer drivers successfully configured
+ * @retval     FSP_ERR_ASSERTION  Invalid pointer
+ **********************************************************************************************************************/
+static fsp_err_t r_sci_uart_transfer_configure (sci_uart_instance_ctrl_t * const p_instance_ctrl,
+                                                transfer_instance_t const      * p_transfer,
+                                                uint32_t                       * p_transfer_reg,
+                                                uint32_t                         sci_buffer_address)
+{
+    /* Configure the transfer instance, if enabled. */
+ #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(NULL != p_transfer->p_api);
+    FSP_ASSERT(NULL != p_transfer->p_ctrl);
+    FSP_ASSERT(NULL != p_transfer->p_cfg);
+    FSP_ASSERT(NULL != p_transfer->p_cfg->p_info);
+    FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend);
+ #endif
+
+    /* Casting for compatibility with 7 or 8 bit mode. */
+    *p_transfer_reg = sci_buffer_address;
+
+    transfer_info_t * p_info = p_transfer->p_cfg->p_info;
+    if (UART_DATA_BITS_9 == p_instance_ctrl->p_cfg->data_bits)
+    {
+        p_info->src_size  = TRANSFER_SIZE_2_BYTE;
+        p_info->dest_size = TRANSFER_SIZE_2_BYTE;
+    }
+    else
+    {
+        p_info->src_size  = TRANSFER_SIZE_1_BYTE;
+        p_info->dest_size = TRANSFER_SIZE_1_BYTE;
+    }
+
+    fsp_err_t err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    return FSP_SUCCESS;
+}
+
+#endif
+
+#if SCI_UART_CFG_DMAC_SUPPORTED
+
+/*******************************************************************************************************************//**
+ * Configures UART related transfer drivers (if enabled).
+ *
+ * @param[in]     p_instance_ctrl  Pointer to UART control structure
+ * @param[in]     p_cfg            Pointer to UART specific configuration structure
+ *
+ * @retval        FSP_SUCCESS        UART transfer drivers successfully configured
+ * @retval        FSP_ERR_ASSERTION  Invalid pointer or required interrupt not enabled in vector table
+ *
+ * @return                       See @ref RENESAS_ERROR_CODES or functions called by this function for other possible
+ *                               return codes. This function calls:
+ *                                   * @ref transfer_api_t::open
+ **********************************************************************************************************************/
+static fsp_err_t r_sci_uart_transfer_open (sci_uart_instance_ctrl_t * const p_instance_ctrl,
+                                           uart_cfg_t const * const         p_cfg)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+ #if (SCI_UART_CFG_RX_ENABLE)
+
+    /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */
+    if (NULL != p_cfg->p_transfer_rx)
+    {
+        transfer_info_t * p_info = p_cfg->p_transfer_rx->p_cfg->p_info;
+
+        p_info->mode           = TRANSFER_MODE_NORMAL;
+        p_info->src_addr_mode  = TRANSFER_ADDR_MODE_FIXED;
+        p_info->dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED;
+
+        err =
+            r_sci_uart_transfer_configure(p_instance_ctrl,
+                                          p_cfg->p_transfer_rx,
+                                          (uint32_t *) &p_info->p_src,
+                                          (uint32_t) (uintptr_t) &(p_instance_ctrl->p_reg->RDR));
+        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+    }
+ #endif
+ #if (SCI_UART_CFG_TX_ENABLE)
+
+    /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */
+    if (NULL != p_cfg->p_transfer_tx)
+    {
+        transfer_info_t * p_info = p_cfg->p_transfer_tx->p_cfg->p_info;
+
+        p_info->mode           = TRANSFER_MODE_NORMAL;
+        p_info->src_addr_mode  = TRANSFER_ADDR_MODE_INCREMENTED;
+        p_info->dest_addr_mode = TRANSFER_ADDR_MODE_FIXED;
+
+        err =
+            r_sci_uart_transfer_configure(p_instance_ctrl,
+                                          p_cfg->p_transfer_tx,
+                                          (uint32_t *) &p_info->p_dest,
+                                          (uint32_t) (uintptr_t) &p_instance_ctrl->p_reg->TDR);
+
+  #if (SCI_UART_CFG_RX_ENABLE)
+        if ((err != FSP_SUCCESS) && (NULL != p_cfg->p_transfer_rx))
+        {
+            p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl);
+        }
+  #endif
+        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+    }
+ #endif
+
+    return err;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Configures UART related registers based on user configurations.
+ *
+ * @param[in]     p_instance_ctrl  Pointer to UART control structure
+ * @param[in]     p_cfg            Pointer to UART specific configuration structure
+ **********************************************************************************************************************/
+static void r_sci_uart_config_set (sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg)
+{
+    /* CCR3 register setting. */
+    uint32_t ccr3 = SCI_UART_CCR3_DEFAULT_VALUE;
+
+#if SCI_UART_CFG_FIFO_SUPPORT
+    ccr3 |= (1U << SCI_UART_CCR3_FM_OFFSET);
+
+    /* Configure FIFO related registers. */
+    r_sci_uart_fifo_cfg(p_instance_ctrl);
+#else
+
+    /* If fifo support is disabled and the current channel supports fifo make sure it's disabled. */
+    if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS & (1U << p_cfg->channel))
+    {
+        p_instance_ctrl->p_reg->FCR = SCI_UART_FCR_DEFAULT_VALUE;
+    }
+#endif
+
+    /* Configure data size. */
+    if (UART_DATA_BITS_7 == p_cfg->data_bits)
+    {
+        ccr3 |= (1U << SCI_UART_CCR3_CHR_OFFSET);
+    }
+    else if (UART_DATA_BITS_9 == p_cfg->data_bits)
+    {
+        ccr3 &= ~(1U << (SCI_UART_CCR3_CHR_OFFSET + 1));
+    }
+    else
+    {
+        /* Do nothing.  Default is 8-bit mode. */
+    }
+
+    /* Configure stop bits. */
+    ccr3 |= (uint32_t) p_cfg->stop_bits << SCI_UART_CCR3_STP_OFFSET;
+
+    /* Configure CKE bits. */
+    sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend;
+    ccr3 |= (p_extend->clock & SCI_UART_CCR3_CKE_VALUE_MASK) << SCI_UART_CCR3_CKE_OFFSET;
+
+    /* Starts reception on falling edge of RXD if enabled in extension (otherwise reception starts at low level
+     * of RXD). */
+    ccr3 |= (p_extend->rx_edge_start & 1U) << SCI_UART_CCR3_RxDSEL_OFFSET;
+
+    ccr3 |= ((uint32_t) p_extend->rs485_setting.enable << R_SCI0_CCR3_DEN_Pos) & (uint32_t) R_SCI0_CCR3_DEN_Msk;
+
+    /* Configure SPEN bit. */
+    if (SCI_UART_CLOCK_SOURCE_PCLKM == p_extend->clock_source)
+    {
+        ccr3 |= 1U << SCI_UART_CCR3_BPEN_OFFSET;
+    }
+
+    /* Write to the CCR3 register. */
+    p_instance_ctrl->p_reg->CCR3 = ccr3;
+
+    /* CCR1 register setting. */
+    uint32_t ccr1 = SCI_UART_CCR1_DEFAULT_VALUE;
+
+    /* Configure flow control pin. */
+    ccr1 |= ((uint32_t) (p_extend->flow_control << R_SCI0_CCR1_CTSE_Pos) & SCI_UART_CCR1_FLOW_CTSRTS_MASK);
+
+    /* Set the default level of the TX pin to 1. */
+    ccr1 |= (uint32_t) (1U << SCI_UART_CCR1_SPB2DT_BIT | SCI_UART_CCR1_OUTPUT_ENABLE_MASK);
+
+    /* Configure parity bits. */
+    if (0 != p_cfg->parity)
+    {
+        ccr1 |=
+            (((UART_PARITY_EVEN ==
+               p_cfg->parity) ? 1U : 3U) << SCI_UART_CCR1_PARITY_OFFSET) & SCI_UART_CCR1_PARITY_MASK;
+    }
+
+    if (SCI_UART_NOISE_CANCELLATION_DISABLE != p_extend->noise_cancel)
+    {
+        /* Select noise filter clock */
+        ccr1 |= (uint32_t) (((p_extend->noise_cancel & 0x07U) - 1) & SCI_UART_CCR1_NFCS_VALUE_MASK) <<
+                SCI_UART_CCR1_NFCS_OFFSET;
+
+        /* Enables the noise cancellation */
+        ccr1 |= (uint32_t) 1 << SCI_UART_CCR1_NFEN_OFFSET;
+    }
+
+    p_instance_ctrl->p_reg->CCR1 = ccr1;
+
+    if ((SCI_UART_CLOCK_EXT8X == p_extend->clock) || (SCI_UART_CLOCK_EXT16X == p_extend->clock))
+    {
+        /* Use external clock for baud rate */
+        p_instance_ctrl->p_reg->CCR2_b.BRR = SCI_UART_BRR_DEFAULT_VALUE;
+
+        if (SCI_UART_CLOCK_EXT8X == p_extend->clock)
+        {
+            /* Set baud rate as (external clock / 8) */
+            p_instance_ctrl->p_reg->CCR2 |= 1U << SCI_UART_CCR2_ABCS_OFFSET;
+        }
+    }
+    else
+    {
+        /* Set the baud rate settings for the internal baud rate generator. */
+        r_sci_uart_baud_set(p_instance_ctrl->p_reg, p_extend->p_baud_setting);
+    }
+
+    /* Configure RS-485 DE assertion settings. */
+    uint32_t dcr = ((uint32_t) (p_extend->rs485_setting.polarity << R_SCI0_DCR_DEPOL_Pos)) & R_SCI0_DCR_DEPOL_Msk;
+    dcr |= ((uint32_t) p_extend->rs485_setting.assertion_time << R_SCI0_DCR_DEAST_Pos) &
+           (uint32_t) R_SCI0_DCR_DEAST_Msk;
+    dcr |= ((uint32_t) p_extend->rs485_setting.negation_time << R_SCI0_DCR_DENGT_Pos) &
+           (uint32_t) R_SCI0_DCR_DENGT_Msk;
+    p_instance_ctrl->p_reg->DCR = dcr;
+}
+
+#if SCI_UART_CFG_FIFO_SUPPORT
+
+/*******************************************************************************************************************//**
+ * Resets FIFO related registers.
+ *
+ * @param[in] p_instance_ctrl  Pointer to UART instance control
+ * @param[in] p_cfg            Pointer to UART configuration structure
+ **********************************************************************************************************************/
+static void r_sci_uart_fifo_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl)
+{
+    if (0U != p_instance_ctrl->fifo_depth)
+    {
+        /* Set the tx and rx reset bits */
+        uint32_t fcr = 0U;
+
+ #if (SCI_UART_CFG_TX_ENABLE)
+  #if SCI_UART_CFG_DMAC_SUPPORTED
+        if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx)
+        {
+            /* When DMAC transfer is used, set TTRG[4:0] = 0x0F. */
+            fcr |= SCI_UART_FCR_TTRG_DMAC_VALUE << SCI_UART_FCR_TTRG_OFFSET;
+        }
+  #endif
+ #endif
+
+ #if (SCI_UART_CFG_RX_ENABLE)
+  #if SCI_UART_CFG_DMAC_SUPPORTED
+
+        /* If DMAC is used keep the receive trigger at the default level of 0. */
+        if (NULL == p_instance_ctrl->p_cfg->p_transfer_rx)
+  #endif
+        {
+            /* Otherwise, set receive trigger number as configured by the user. */
+            sci_uart_extended_cfg_t const * p_extend = p_instance_ctrl->p_cfg->p_extend;
+
+            /* RTRG(Receive FIFO Data Trigger Number) controls when the RXI interrupt will be generated. If data is
+             * received but the trigger number is not met the RXI interrupt will be generated after 15 ETUs from
+             * the last stop bit in asynchronous mode. */
+            fcr |= (((p_instance_ctrl->fifo_depth - 1U) & p_extend->rx_fifo_trigger) & SCI_UART_FCR_TRIGGER_MASK) <<
+                   SCI_UART_FCR_RTRG_OFFSET;
+        }
+
+        /* RTS asserts when the amount of received data stored in the fifo is equal or less than this value. */
+        fcr |= ((p_instance_ctrl->fifo_depth - 1U) & SCI_UART_FCR_TRIGGER_MASK) << SCI_UART_FCR_RSTRG_OFFSET;
+ #endif
+
+        /* Set the FCR and reset the fifos. */
+        p_instance_ctrl->p_reg->FCR = (uint32_t) (fcr | SCI_UART_FCR_RESET_TX_RX);
+    }
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Sets interrupt priority and initializes vector info.
+ *
+ * @param[in]  p_instance_ctrl           Pointer to driver control block
+ * @param[in]  ipl                       Interrupt priority level
+ * @param[in]  irq                       IRQ number for this interrupt
+ **********************************************************************************************************************/
+static void r_sci_irq_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl, uint8_t const ipl, IRQn_Type const irq)
+{
+    /* Disable interrupts, set priority, and store control block in the vector information so it can be accessed
+     * from the callback. */
+    R_BSP_IrqDisable(irq);
+
+    R_BSP_IrqCfg(irq, ipl, p_instance_ctrl);
+}
+
+/*******************************************************************************************************************//**
+ * Sets interrupt priority and initializes vector info for all interrupts.
+ *
+ * @param[in]  p_instance_ctrl           Pointer to UART instance control block
+ * @param[in]  p_cfg                     Pointer to UART specific configuration structure
+ **********************************************************************************************************************/
+static void r_sci_irqs_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg)
+{
+#if (SCI_UART_CFG_RX_ENABLE)
+
+    /* ERI is optional. */
+    r_sci_irq_cfg(p_instance_ctrl, p_cfg->eri_ipl, p_cfg->eri_irq);
+    r_sci_irq_cfg(p_instance_ctrl, p_cfg->rxi_ipl, p_cfg->rxi_irq);
+#endif
+#if (SCI_UART_CFG_TX_ENABLE)
+    r_sci_irq_cfg(p_instance_ctrl, p_cfg->txi_ipl, p_cfg->txi_irq);
+
+    r_sci_irq_cfg(p_instance_ctrl, p_cfg->tei_ipl, p_cfg->tei_irq);
+#endif
+}
+
+#if SCI_UART_CFG_DMAC_SUPPORTED
+
+/*******************************************************************************************************************//**
+ * Closes transfer interfaces.
+ *
+ * @param[in]     p_instance_ctrl     Pointer to UART instance control block
+ **********************************************************************************************************************/
+static void r_sci_uart_transfer_close (sci_uart_instance_ctrl_t * p_instance_ctrl)
+{
+ #if (SCI_UART_CFG_RX_ENABLE)
+    if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx)
+    {
+        p_instance_ctrl->p_cfg->p_transfer_rx->p_api->close(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl);
+    }
+ #endif
+ #if (SCI_UART_CFG_TX_ENABLE)
+    if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx)
+    {
+        p_instance_ctrl->p_cfg->p_transfer_tx->p_api->close(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl);
+    }
+ #endif
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Changes baud rate based on predetermined register settings.
+ *
+ * @param[in]  p_sci_reg       Base pointer for SCI registers
+ * @param[in]  p_baud_setting  Pointer to other divisor related settings
+ *
+ * @note       The transmitter and receiver (TE and RE bits in SCR) must be disabled prior to calling this function.
+ **********************************************************************************************************************/
+static void r_sci_uart_baud_set (R_SCI0_Type * p_sci_reg, sci_baud_setting_t const * const p_baud_setting)
+{
+    p_sci_reg->CCR2 = (uint32_t) ((p_sci_reg->CCR2 & ~(SCI_UART_CCR2_BAUD_SETTING_MASK)) |
+                                  (p_baud_setting->baudrate_bits & SCI_UART_CCR2_BAUD_SETTING_MASK));
+}
+
+/*******************************************************************************************************************//**
+ * Calls user callback.
+ *
+ * @param[in]     p_instance_ctrl     Pointer to UART instance control block
+ * @param[in]     data                See uart_callback_args_t in r_uart_api.h
+ * @param[in]     event               Event code
+ **********************************************************************************************************************/
+static void r_sci_uart_call_callback (sci_uart_instance_ctrl_t * p_instance_ctrl, uint32_t data, uart_event_t event)
+{
+    uart_callback_args_t args;
+
+    /* Store callback arguments in memory provided by user if available. */
+    uart_callback_args_t * p_args = p_instance_ctrl->p_callback_memory;
+    if (NULL == p_args)
+    {
+        /* Store on stack */
+        p_args = &args;
+    }
+    else
+    {
+        /* Save current arguments on the stack in case this is a nested interrupt. */
+        args = *p_args;
+    }
+
+    p_args->channel   = p_instance_ctrl->p_cfg->channel;
+    p_args->data      = data;
+    p_args->event     = event;
+    p_args->p_context = p_instance_ctrl->p_context;
+
+    p_instance_ctrl->p_callback(p_args);
+
+    if (NULL != p_instance_ctrl->p_callback_memory)
+    {
+        /* Restore callback memory in case this is a nested interrupt. */
+        *p_instance_ctrl->p_callback_memory = args;
+    }
+}
+
+#if (SCI_UART_CFG_TX_ENABLE)
+
+/*******************************************************************************************************************//**
+ * Common processing for TXI interrupt and DMA transfer completion interrupt in UART write mode. This function writes
+ * the next data. After the last data byte is written, this function disables the TXI interrupt and enables the TEI
+ * (transmit end) interrupt.
+ **********************************************************************************************************************/
+static void sci_uart_txi_common (sci_uart_instance_ctrl_t * p_instance_ctrl)
+{
+    if ((NULL == p_instance_ctrl->p_cfg->p_transfer_tx) && (0U != p_instance_ctrl->tx_src_bytes))
+    {
+        if (2U == p_instance_ctrl->data_bytes)
+        {
+            p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_instance_ctrl->p_tx_src)) & SCI_UART_TDR_9BIT_MASK;
+        }
+        else
+        {
+            p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_instance_ctrl->p_tx_src);
+        }
+
+        /* Update pointer to the next data and number of remaining bytes in the control block. */
+        p_instance_ctrl->tx_src_bytes -= p_instance_ctrl->data_bytes;
+        p_instance_ctrl->p_tx_src     += p_instance_ctrl->data_bytes;
+
+        /* If transfer is not used, write data until FIFO is full. */
+ #if SCI_UART_CFG_FIFO_SUPPORT
+        if (0U != p_instance_ctrl->fifo_depth)
+        {
+            uint32_t fifo_count = p_instance_ctrl->p_reg->FTSR_b.T;
+            for (uint32_t cnt = fifo_count; (cnt < p_instance_ctrl->fifo_depth) && p_instance_ctrl->tx_src_bytes; cnt++)
+            {
+                if (2U == p_instance_ctrl->data_bytes)
+                {
+                    p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_instance_ctrl->p_tx_src)) &
+                                                         SCI_UART_TDR_9BIT_MASK;
+                }
+                else
+                {
+                    p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_instance_ctrl->p_tx_src);
+                }
+
+                p_instance_ctrl->tx_src_bytes -= p_instance_ctrl->data_bytes;
+                p_instance_ctrl->p_tx_src     += p_instance_ctrl->data_bytes;
+            }
+
+            /* Clear TDRE flag */
+            p_instance_ctrl->p_reg->CFCLR_b.TDREC = 1;
+        }
+ #endif
+    }
+
+    if (0U == p_instance_ctrl->tx_src_bytes)
+    {
+        /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */
+        uint32_t ccr0_temp = p_instance_ctrl->p_reg->CCR0;
+        ccr0_temp |= SCI_UART_CCR0_TEIE_MASK;
+        ccr0_temp &= (uint32_t) ~SCI_UART_CCR0_TIE_MASK;
+        p_instance_ctrl->p_reg->CCR0 = ccr0_temp;
+
+        p_instance_ctrl->p_tx_src = NULL;
+        r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * TXI interrupt handler for UART mode. TXI interrupt fires when the data in the data register or FIFO register has been
+ * transferred to the data shift register, and the next data can be written. This function calls sci_uart_txi_common().
+ **********************************************************************************************************************/
+void sci_uart_txi_isr (void)
+{
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    sci_uart_txi_common(p_instance_ctrl);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+/*******************************************************************************************************************//**
+ * Callback that must be called after a TX DMAC transfer completes.
+ *
+ * @param[in]     p_instance_ctrl     Pointer to SCI_UART instance control block
+ **********************************************************************************************************************/
+void sci_uart_tx_dmac_callback (sci_uart_instance_ctrl_t * p_instance_ctrl)
+{
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+    /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */
+    R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq);
+
+    sci_uart_txi_common(p_instance_ctrl);
+
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+#endif
+
+#if (SCI_UART_CFG_RX_ENABLE)
+
+/*******************************************************************************************************************//**
+ * Common processing for RXI interrupt and DMA transfer completion interrupt in UART read mode. This function calls
+ * callback function when it meets conditions below.
+ *  - UART_EVENT_RX_COMPLETE: The number of data which has been read reaches to the number specified in R_SCI_UART_Read()
+ *    if a transfer instance is used for reception.
+ *  - UART_EVENT_RX_CHAR: Data is received asynchronously (read has not been called)
+ *
+ * This function also calls the callback function for RTS pin control if it is registered in R_SCI_UART_Open(). This is
+ * special functionality to expand SCI hardware capability and make RTS/CTS hardware flow control possible. If macro
+ * 'SCI_UART_CFG_FLOW_CONTROL_SUPPORT' is set, it is called at the beginning in this function to set the RTS pin high,
+ * then it is called again just before leaving this function to set the RTS pin low.
+ * @retval    none
+ **********************************************************************************************************************/
+static void sci_uart_rxi_common (sci_uart_instance_ctrl_t * p_instance_ctrl)
+{
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+    if ((p_instance_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_instance_ctrl->rx_dest_bytes))
+ #endif
+    {
+ #if (SCI_UART_CFG_FLOW_CONTROL_SUPPORT)
+        if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM)
+        {
+            R_BSP_PinAccessEnable();
+
+            /* Pause the transmission of data from the other device. */
+            R_BSP_PinSet(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin);
+        }
+ #endif
+
+        uint32_t data;
+ #if SCI_UART_CFG_FIFO_SUPPORT
+        do
+        {
+            if ((p_instance_ctrl->fifo_depth > 0U))
+            {
+                if (p_instance_ctrl->p_reg->FRSR_b.R > 0U)
+                {
+                    data = p_instance_ctrl->p_reg->RDR_b.RDAT;
+                }
+                else
+                {
+                    break;
+                }
+            }
+            else
+            {
+                data = p_instance_ctrl->p_reg->RDR_b.RDAT;
+            }
+
+ #else
+        {
+            data = p_instance_ctrl->p_reg->RDR_b.RDAT;
+ #endif
+            if (0 == p_instance_ctrl->rx_dest_bytes)
+            {
+                /* Call user callback with the data. */
+                r_sci_uart_call_callback(p_instance_ctrl, data, UART_EVENT_RX_CHAR);
+            }
+            else
+            {
+                memcpy((void *) p_instance_ctrl->p_rx_dest, &data, p_instance_ctrl->data_bytes);
+                p_instance_ctrl->p_rx_dest     += p_instance_ctrl->data_bytes;
+                p_instance_ctrl->rx_dest_bytes -= p_instance_ctrl->data_bytes;
+
+                if (0 == p_instance_ctrl->rx_dest_bytes)
+                {
+                    r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_RX_COMPLETE);
+                }
+            }
+
+ #if SCI_UART_CFG_FIFO_SUPPORT
+        } while ((p_instance_ctrl->fifo_depth > 0U) && ((p_instance_ctrl->p_reg->FRSR_b.R) > 0U));
+
+        if (p_instance_ctrl->fifo_depth > 0U)
+        {
+            p_instance_ctrl->p_reg->CFCLR_b.RDRFC = 1;
+        }
+
+ #else
+        }
+ #endif
+ #if (SCI_UART_CFG_FLOW_CONTROL_SUPPORT)
+        if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM)
+        {
+            /* Resume the transmission of data from the other device. */
+            R_BSP_PinClear(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin);
+            R_BSP_PinAccessDisable();
+        }
+ #endif
+    }
+
+ #if SCI_UART_CFG_DMAC_SUPPORTED
+    else
+    {
+        p_instance_ctrl->rx_dest_bytes = 0;
+        p_instance_ctrl->p_rx_dest     = NULL;
+
+        /* Call callback */
+        r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_RX_COMPLETE);
+    }
+ #endif
+}
+
+/*******************************************************************************************************************//**
+ * RXI interrupt handler for UART mode. RXI interrupt happens when data arrives to the data register or the FIFO
+ * register. This function calls sci_uart_rxi_common().
+ **********************************************************************************************************************/
+void sci_uart_rxi_isr (void)
+{
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    sci_uart_rxi_common(p_instance_ctrl);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+/*******************************************************************************************************************//**
+ * Callback that must be called after a RX DMAC transfer completes.
+ *
+ * @param[in]     p_instance_ctrl     Pointer to SCI_UART instance control block
+ **********************************************************************************************************************/
+void sci_uart_rx_dmac_callback (sci_uart_instance_ctrl_t * p_instance_ctrl)
+{
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+    /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */
+    R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq);
+
+    sci_uart_rxi_common(p_instance_ctrl);
+
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+#endif
+
+#if (SCI_UART_CFG_TX_ENABLE)
+
+/*******************************************************************************************************************//**
+ * TEI interrupt processing for UART mode. The TEI interrupt fires after the last byte is transmitted on the TX pin.
+ * The user callback function is called with the UART_EVENT_TX_COMPLETE event code (if it is registered in
+ * R_SCI_UART_Open()).
+ **********************************************************************************************************************/
+void sci_uart_tei_isr (void)
+{
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */
+    p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK);
+
+    /* Dummy read to ensure that interrupts are disabled. */
+    volatile uint32_t dummy = p_instance_ctrl->p_reg->CCR0;
+    FSP_PARAMETER_NOT_USED(dummy);
+
+    r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_TX_COMPLETE);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+#endif
+
+#if (SCI_UART_CFG_RX_ENABLE)
+
+/*******************************************************************************************************************//**
+ * ERI interrupt processing for UART mode. When an ERI interrupt fires, the user callback function is called if it is
+ * registered in R_SCI_UART_Open() with the event code that triggered the interrupt.
+ **********************************************************************************************************************/
+void sci_uart_eri_isr (void)
+{
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE;
+
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    uint32_t     data  = 0U;
+    uart_event_t event = (uart_event_t) 0U;
+
+    /* Read data. */
+    data = p_instance_ctrl->p_reg->RDR_b.RDAT;
+
+    /* Determine cause of error. */
+    uint32_t csr = p_instance_ctrl->p_reg->CSR & SCI_UART_RCVR_ERR_MASK;
+
+    if (csr & SCI_UART_CSR_ORER_MASK)
+    {
+        event |= UART_EVENT_ERR_OVERFLOW;
+    }
+
+    if (csr & SCI_UART_CSR_FER_MASK)
+    {
+        event |= UART_EVENT_ERR_FRAMING;
+    }
+
+    if (csr & SCI_UART_CSR_PER_MASK)
+    {
+        event |= UART_EVENT_ERR_PARITY;
+    }
+
+    /* Check if there is a break detected. */
+    if ((UART_EVENT_ERR_FRAMING == (event & UART_EVENT_ERR_FRAMING)) && (0U == p_instance_ctrl->p_reg->CSR_b.RXDMON))
+    {
+        event |= UART_EVENT_BREAK_DETECT;
+    }
+
+    /* Clear error condition. */
+    p_instance_ctrl->p_reg->CFCLR |= (uint32_t) (SCI_UART_RCVR_ERRCLR_MASK);
+
+    /* Dummy read to ensure that interrupt event is cleared. */
+    volatile uint32_t dummy = p_instance_ctrl->p_reg->CSR;
+    FSP_PARAMETER_NOT_USED(dummy);
+
+    /* Call callback. */
+    r_sci_uart_call_callback(p_instance_ctrl, data, event);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+
+    SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE;
+}
+
+#endif
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg.txt b/projects/etherkit_ethercat_cherryecat/rzn_cfg.txt
new file mode 100644
index 00000000..e0b74461
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg.txt
@@ -0,0 +1,1524 @@
+FSP Configuration
+  Board "RSK+RZN2L|RSK+RZN2L (xSPI0 x1 boot mode)"
+    Parameter information for the loader: CACHE_FLG: 0x00000000
+    Parameter information for the loader: WRAPCFG_V: 0x00000000
+    Parameter information for the loader: COMCFG_V: 0x00000000
+    Parameter information for the loader: BMCFG_V: 0x00000000
+    Parameter information for the loader: xSPI_FLG: 0x00000000
+    Parameter information for the loader: LDR_ADDR_NML: 0x6000004C
+    Parameter information for the loader: LDR_SIZE_NML: 0x00006000
+    Parameter information for the loader: DEST_ADDR_NML: 0x00102000
+    Parameter information for the loader: CSSCTL_V: 0x0000003F
+    Parameter information for the loader: LIOCFGCS0_V: 0x00070000
+    Parameter information for the loader: ACCESS_SPEED: 0x00000006
+    Parameter information for the loader: CHECK_SUM: Auto Calculate.
+    Use loader parameter: Used
+    
+  R9A07G084M04GBG
+    part_number: R9A07G084M04GBG
+    atcm_size_bytes: 131072
+    btcm_size_bytes: 131072
+    system_ram_size_bytes: 1572864
+    package_style: FBGA
+    package_pins: 225
+    Cortex-R52 CPU core: CPU0
+    
+  RZN2L Memory Config
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 0: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 0: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Region 0 Start: 0x00000000
+    Master MPU: MPU0 : DMAC Unit0: Region 0 End: 0x00000C00
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 1: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 1: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Region 1 Start: 0x00000000
+    Master MPU: MPU0 : DMAC Unit0: Region 1 End: 0x00000C00
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 2: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 2: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Region 2 Start: 0x00000000
+    Master MPU: MPU0 : DMAC Unit0: Region 2 End: 0x00000C00
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 3: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 3: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Region 3 Start: 0x00000000
+    Master MPU: MPU0 : DMAC Unit0: Region 3 End: 0x00000C00
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 4: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 4: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Region 4 Start: 0x00000000
+    Master MPU: MPU0 : DMAC Unit0: Region 4 End: 0x00000C00
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 5: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 5: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Region 5 Start: 0x00000000
+    Master MPU: MPU0 : DMAC Unit0: Region 5 End: 0x00000C00
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 6: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 6: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Region 6 Start: 0x00000000
+    Master MPU: MPU0 : DMAC Unit0: Region 6 End: 0x00000C00
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 7: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 7: Disabled
+    Master MPU: MPU0 : DMAC Unit0: Region 7 Start: 0x00000000
+    Master MPU: MPU0 : DMAC Unit0: Region 7 End: 0x00000C00
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 0: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 0: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Region 0 Start: 0x00000000
+    Master MPU: MPU1 : DMAC Unit1: Region 0 End: 0x00000C00
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 1: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 1: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Region 1 Start: 0x00000000
+    Master MPU: MPU1 : DMAC Unit1: Region 1 End: 0x00000C00
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 2: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 2: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Region 2 Start: 0x00000000
+    Master MPU: MPU1 : DMAC Unit1: Region 2 End: 0x00000C00
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 3: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 3: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Region 3 Start: 0x00000000
+    Master MPU: MPU1 : DMAC Unit1: Region 3 End: 0x00000C00
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 4: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 4: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Region 4 Start: 0x00000000
+    Master MPU: MPU1 : DMAC Unit1: Region 4 End: 0x00000C00
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 5: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 5: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Region 5 Start: 0x00000000
+    Master MPU: MPU1 : DMAC Unit1: Region 5 End: 0x00000C00
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 6: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 6: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Region 6 Start: 0x00000000
+    Master MPU: MPU1 : DMAC Unit1: Region 6 End: 0x00000C00
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 7: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 7: Disabled
+    Master MPU: MPU1 : DMAC Unit1: Region 7 Start: 0x00000000
+    Master MPU: MPU1 : DMAC Unit1: Region 7 End: 0x00000C00
+    Master MPU: MPU2 : GMAC: Enable or disable read control for Region 0: Disabled
+    Master MPU: MPU2 : GMAC: Enable or disable write control for Region 0: Disabled
+    Master MPU: MPU2 : GMAC: Region 0 Start: 0x00000000
+    Master MPU: MPU2 : GMAC: Region 0 End: 0x00000C00
+    Master MPU: MPU2 : GMAC: Enable or disable read control for Region 1: Disabled
+    Master MPU: MPU2 : GMAC: Enable or disable write control for Region 1: Disabled
+    Master MPU: MPU2 : GMAC: Region 1 Start: 0x00000000
+    Master MPU: MPU2 : GMAC: Region 1 End: 0x00000C00
+    Master MPU: MPU2 : GMAC: Enable or disable read control for Region 2: Disabled
+    Master MPU: MPU2 : GMAC: Enable or disable write control for Region 2: Disabled
+    Master MPU: MPU2 : GMAC: Region 2 Start: 0x00000000
+    Master MPU: MPU2 : GMAC: Region 2 End: 0x00000C00
+    Master MPU: MPU2 : GMAC: Enable or disable read control for Region 3: Disabled
+    Master MPU: MPU2 : GMAC: Enable or disable write control for Region 3: Disabled
+    Master MPU: MPU2 : GMAC: Region 3 Start: 0x00000000
+    Master MPU: MPU2 : GMAC: Region 3 End: 0x00000C00
+    Master MPU: MPU2 : GMAC: Enable or disable read control for Region 4: Disabled
+    Master MPU: MPU2 : GMAC: Enable or disable write control for Region 4: Disabled
+    Master MPU: MPU2 : GMAC: Region 4 Start: 0x00000000
+    Master MPU: MPU2 : GMAC: Region 4 End: 0x00000C00
+    Master MPU: MPU2 : GMAC: Enable or disable read control for Region 5: Disabled
+    Master MPU: MPU2 : GMAC: Enable or disable write control for Region 5: Disabled
+    Master MPU: MPU2 : GMAC: Region 5 Start: 0x00000000
+    Master MPU: MPU2 : GMAC: Region 5 End: 0x00000C00
+    Master MPU: MPU2 : GMAC: Enable or disable read control for Region 6: Disabled
+    Master MPU: MPU2 : GMAC: Enable or disable write control for Region 6: Disabled
+    Master MPU: MPU2 : GMAC: Region 6 Start: 0x00000000
+    Master MPU: MPU2 : GMAC: Region 6 End: 0x00000C00
+    Master MPU: MPU2 : GMAC: Enable or disable read control for Region 7: Disabled
+    Master MPU: MPU2 : GMAC: Enable or disable write control for Region 7: Disabled
+    Master MPU: MPU2 : GMAC: Region 7 Start: 0x00000000
+    Master MPU: MPU2 : GMAC: Region 7 End: 0x00000C00
+    Master MPU: MPU3 : USB Host: Enable or disable read control for Region 0: Disabled
+    Master MPU: MPU3 : USB Host: Enable or disable write control for Region 0: Disabled
+    Master MPU: MPU3 : USB Host: Region 0 Start: 0x00000000
+    Master MPU: MPU3 : USB Host: Region 0 End: 0x00000000
+    Master MPU: MPU3 : USB Host: Enable or disable read control for Region 1: Disabled
+    Master MPU: MPU3 : USB Host: Enable or disable write control for Region 1: Disabled
+    Master MPU: MPU3 : USB Host: Region 1 Start: 0x00000000
+    Master MPU: MPU3 : USB Host: Region 1 End: 0x00000000
+    Master MPU: MPU3 : USB Host: Enable or disable read control for Region 2: Disabled
+    Master MPU: MPU3 : USB Host: Enable or disable write control for Region 2: Disabled
+    Master MPU: MPU3 : USB Host: Region 2 Start: 0x00000000
+    Master MPU: MPU3 : USB Host: Region 2 End: 0x00000000
+    Master MPU: MPU3 : USB Host: Enable or disable read control for Region 3: Disabled
+    Master MPU: MPU3 : USB Host: Enable or disable write control for Region 3: Disabled
+    Master MPU: MPU3 : USB Host: Region 3 Start: 0x00000000
+    Master MPU: MPU3 : USB Host: Region 3 End: 0x00000000
+    Master MPU: MPU3 : USB Host: Enable or disable read control for Region 4: Disabled
+    Master MPU: MPU3 : USB Host: Enable or disable write control for Region 4: Disabled
+    Master MPU: MPU3 : USB Host: Region 4 Start: 0x00000000
+    Master MPU: MPU3 : USB Host: Region 4 End: 0x00000000
+    Master MPU: MPU3 : USB Host: Enable or disable read control for Region 5: Disabled
+    Master MPU: MPU3 : USB Host: Enable or disable write control for Region 5: Disabled
+    Master MPU: MPU3 : USB Host: Region 5 Start: 0x00000000
+    Master MPU: MPU3 : USB Host: Region 5 End: 0x00000000
+    Master MPU: MPU3 : USB Host: Enable or disable read control for Region 6: Disabled
+    Master MPU: MPU3 : USB Host: Enable or disable write control for Region 6: Disabled
+    Master MPU: MPU3 : USB Host: Region 6 Start: 0x00000000
+    Master MPU: MPU3 : USB Host: Region 6 End: 0x00000000
+    Master MPU: MPU3 : USB Host: Enable or disable read control for Region 7: Disabled
+    Master MPU: MPU3 : USB Host: Enable or disable write control for Region 7: Disabled
+    Master MPU: MPU3 : USB Host: Region 7 Start: 0x00000000
+    Master MPU: MPU3 : USB Host: Region 7 End: 0x00000000
+    Master MPU: MPU4 : USB Function: Enable or disable read control for Region 0: Disabled
+    Master MPU: MPU4 : USB Function: Enable or disable write control for Region 0: Disabled
+    Master MPU: MPU4 : USB Function: Region 0 Start: 0x00000000
+    Master MPU: MPU4 : USB Function: Region 0 End: 0x00000000
+    Master MPU: MPU4 : USB Function: Enable or disable read control for Region 1: Disabled
+    Master MPU: MPU4 : USB Function: Enable or disable write control for Region 1: Disabled
+    Master MPU: MPU4 : USB Function: Region 1 Start: 0x00000000
+    Master MPU: MPU4 : USB Function: Region 1 End: 0x00000000
+    Master MPU: MPU4 : USB Function: Enable or disable read control for Region 2: Disabled
+    Master MPU: MPU4 : USB Function: Enable or disable write control for Region 2: Disabled
+    Master MPU: MPU4 : USB Function: Region 2 Start: 0x00000000
+    Master MPU: MPU4 : USB Function: Region 2 End: 0x00000000
+    Master MPU: MPU4 : USB Function: Enable or disable read control for Region 3: Disabled
+    Master MPU: MPU4 : USB Function: Enable or disable write control for Region 3: Disabled
+    Master MPU: MPU4 : USB Function: Region 3 Start: 0x00000000
+    Master MPU: MPU4 : USB Function: Region 3 End: 0x00000000
+    Master MPU: MPU4 : USB Function: Enable or disable read control for Region 4: Disabled
+    Master MPU: MPU4 : USB Function: Enable or disable write control for Region 4: Disabled
+    Master MPU: MPU4 : USB Function: Region 4 Start: 0x00000000
+    Master MPU: MPU4 : USB Function: Region 4 End: 0x00000000
+    Master MPU: MPU4 : USB Function: Enable or disable read control for Region 5: Disabled
+    Master MPU: MPU4 : USB Function: Enable or disable write control for Region 5: Disabled
+    Master MPU: MPU4 : USB Function: Region 5 Start: 0x00000000
+    Master MPU: MPU4 : USB Function: Region 5 End: 0x00000000
+    Master MPU: MPU4 : USB Function: Enable or disable read control for Region 6: Disabled
+    Master MPU: MPU4 : USB Function: Enable or disable write control for Region 6: Disabled
+    Master MPU: MPU4 : USB Function: Region 6 Start: 0x00000000
+    Master MPU: MPU4 : USB Function: Region 6 End: 0x00000000
+    Master MPU: MPU4 : USB Function: Enable or disable read control for Region 7: Disabled
+    Master MPU: MPU4 : USB Function: Enable or disable write control for Region 7: Disabled
+    Master MPU: MPU4 : USB Function: Region 7 Start: 0x00000000
+    Master MPU: MPU4 : USB Function: Region 7 End: 0x00000000
+    Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 0: Disabled
+    Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 0: Disabled
+    Master MPU: MPU6 : CoreSight: Region 0 Start: 0x00000000
+    Master MPU: MPU6 : CoreSight: Region 0 End: 0x00000C00
+    Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 1: Disabled
+    Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 1: Disabled
+    Master MPU: MPU6 : CoreSight: Region 1 Start: 0x00000000
+    Master MPU: MPU6 : CoreSight: Region 1 End: 0x00000C00
+    Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 2: Disabled
+    Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 2: Disabled
+    Master MPU: MPU6 : CoreSight: Region 2 Start: 0x00000000
+    Master MPU: MPU6 : CoreSight: Region 2 End: 0x00000C00
+    Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 3: Disabled
+    Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 3: Disabled
+    Master MPU: MPU6 : CoreSight: Region 3 Start: 0x00000000
+    Master MPU: MPU6 : CoreSight: Region 3 End: 0x00000C00
+    Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 4: Disabled
+    Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 4: Disabled
+    Master MPU: MPU6 : CoreSight: Region 4 Start: 0x00000000
+    Master MPU: MPU6 : CoreSight: Region 4 End: 0x00000C00
+    Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 5: Disabled
+    Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 5: Disabled
+    Master MPU: MPU6 : CoreSight: Region 5 Start: 0x00000000
+    Master MPU: MPU6 : CoreSight: Region 5 End: 0x00000C00
+    Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 6: Disabled
+    Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 6: Disabled
+    Master MPU: MPU6 : CoreSight: Region 6 Start: 0x00000000
+    Master MPU: MPU6 : CoreSight: Region 6 End: 0x00000C00
+    Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 7: Disabled
+    Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 7: Disabled
+    Master MPU: MPU6 : CoreSight: Region 7 Start: 0x00000000
+    Master MPU: MPU6 : CoreSight: Region 7 End: 0x00000C00
+    Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 0: Disabled
+    Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 0: Disabled
+    Master MPU: MPU7 : SHOSTIF: Region 0 Start: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Region 0 End: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 1: Disabled
+    Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 1: Disabled
+    Master MPU: MPU7 : SHOSTIF: Region 1 Start: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Region 1 End: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 2: Disabled
+    Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 2: Disabled
+    Master MPU: MPU7 : SHOSTIF: Region 2 Start: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Region 2 End: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 3: Disabled
+    Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 3: Disabled
+    Master MPU: MPU7 : SHOSTIF: Region 3 Start: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Region 3 End: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 4: Disabled
+    Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 4: Disabled
+    Master MPU: MPU7 : SHOSTIF: Region 4 Start: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Region 4 End: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 5: Disabled
+    Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 5: Disabled
+    Master MPU: MPU7 : SHOSTIF: Region 5 Start: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Region 5 End: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 6: Disabled
+    Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 6: Disabled
+    Master MPU: MPU7 : SHOSTIF: Region 6 Start: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Region 6 End: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 7: Disabled
+    Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 7: Disabled
+    Master MPU: MPU7 : SHOSTIF: Region 7 Start: 0x00000000
+    Master MPU: MPU7 : SHOSTIF: Region 7 End: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 0: Disabled
+    Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 0: Disabled
+    Master MPU: MPU8 : PHOSTIF: Region 0 Start: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Region 0 End: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 1: Disabled
+    Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 1: Disabled
+    Master MPU: MPU8 : PHOSTIF: Region 1 Start: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Region 1 End: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 2: Disabled
+    Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 2: Disabled
+    Master MPU: MPU8 : PHOSTIF: Region 2 Start: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Region 2 End: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 3: Disabled
+    Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 3: Disabled
+    Master MPU: MPU8 : PHOSTIF: Region 3 Start: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Region 3 End: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 4: Disabled
+    Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 4: Disabled
+    Master MPU: MPU8 : PHOSTIF: Region 4 Start: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Region 4 End: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 5: Disabled
+    Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 5: Disabled
+    Master MPU: MPU8 : PHOSTIF: Region 5 Start: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Region 5 End: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 6: Disabled
+    Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 6: Disabled
+    Master MPU: MPU8 : PHOSTIF: Region 6 Start: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Region 6 End: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 7: Disabled
+    Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 7: Disabled
+    Master MPU: MPU8 : PHOSTIF: Region 7 Start: 0x00000000
+    Master MPU: MPU8 : PHOSTIF: Region 7 End: 0x00000000
+    CPU MPU: Attribute: Attribute 0: Memory Type: Normal memory
+    CPU MPU: Attribute: Attribute 0: Normal Memory: Inner: Memory Attribute Indirection: Write-Back non-transient
+    CPU MPU: Attribute: Attribute 0: Normal Memory: Inner: Read: Allocate
+    CPU MPU: Attribute: Attribute 0: Normal Memory: Inner: Write: Allocate
+    CPU MPU: Attribute: Attribute 0: Normal Memory: Outer: Memory Attribute Indirection: Write-Back non-transient
+    CPU MPU: Attribute: Attribute 0: Normal Memory: Outer: Read: Allocate
+    CPU MPU: Attribute: Attribute 0: Normal Memory: Outer: Write: Allocate
+    CPU MPU: Attribute: Attribute 0: Device Memory: Device Type: Device-nGnRnE memory
+    CPU MPU: Attribute: Attribute 1: Memory Type: Normal memory
+    CPU MPU: Attribute: Attribute 1: Normal Memory: Inner: Memory Attribute Indirection: Write-Through non-transient
+    CPU MPU: Attribute: Attribute 1: Normal Memory: Inner: Read: Allocate
+    CPU MPU: Attribute: Attribute 1: Normal Memory: Inner: Write: Allocate
+    CPU MPU: Attribute: Attribute 1: Normal Memory: Outer: Memory Attribute Indirection: Write-Through non-transient
+    CPU MPU: Attribute: Attribute 1: Normal Memory: Outer: Read: Allocate
+    CPU MPU: Attribute: Attribute 1: Normal Memory: Outer: Write: Allocate
+    CPU MPU: Attribute: Attribute 1: Device Memory: Device Type: Device-nGnRnE memory
+    CPU MPU: Attribute: Attribute 2: Memory Type: Normal memory
+    CPU MPU: Attribute: Attribute 2: Normal Memory: Inner: Memory Attribute Indirection: Write-Through non-transient
+    CPU MPU: Attribute: Attribute 2: Normal Memory: Inner: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 2: Normal Memory: Inner: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 2: Normal Memory: Outer: Memory Attribute Indirection: Write-Through non-transient
+    CPU MPU: Attribute: Attribute 2: Normal Memory: Outer: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 2: Normal Memory: Outer: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 2: Device Memory: Device Type: Device-nGnRnE memory
+    CPU MPU: Attribute: Attribute 3: Memory Type: Normal memory
+    CPU MPU: Attribute: Attribute 3: Normal Memory: Inner: Memory Attribute Indirection: Non-Cacheable
+    CPU MPU: Attribute: Attribute 3: Normal Memory: Inner: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 3: Normal Memory: Inner: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 3: Normal Memory: Outer: Memory Attribute Indirection: Non-Cacheable
+    CPU MPU: Attribute: Attribute 3: Normal Memory: Outer: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 3: Normal Memory: Outer: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 3: Device Memory: Device Type: Device-nGnRnE memory
+    CPU MPU: Attribute: Attribute 4: Memory Type: Device memory
+    CPU MPU: Attribute: Attribute 4: Normal Memory: Inner: Memory Attribute Indirection: Write-Through transient
+    CPU MPU: Attribute: Attribute 4: Normal Memory: Inner: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 4: Normal Memory: Inner: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 4: Normal Memory: Outer: Memory Attribute Indirection: Write-Through transient
+    CPU MPU: Attribute: Attribute 4: Normal Memory: Outer: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 4: Normal Memory: Outer: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 4: Device Memory: Device Type: Device-nGnRnE memory
+    CPU MPU: Attribute: Attribute 5: Memory Type: Device memory
+    CPU MPU: Attribute: Attribute 5: Normal Memory: Inner: Memory Attribute Indirection: Write-Through transient
+    CPU MPU: Attribute: Attribute 5: Normal Memory: Inner: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 5: Normal Memory: Inner: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 5: Normal Memory: Outer: Memory Attribute Indirection: Write-Through transient
+    CPU MPU: Attribute: Attribute 5: Normal Memory: Outer: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 5: Normal Memory: Outer: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 5: Device Memory: Device Type: Device-nGnRE memory
+    CPU MPU: Attribute: Attribute 6: Memory Type: Device memory
+    CPU MPU: Attribute: Attribute 6: Normal Memory: Inner: Memory Attribute Indirection: Write-Through transient
+    CPU MPU: Attribute: Attribute 6: Normal Memory: Inner: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 6: Normal Memory: Inner: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 6: Normal Memory: Outer: Memory Attribute Indirection: Write-Through transient
+    CPU MPU: Attribute: Attribute 6: Normal Memory: Outer: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 6: Normal Memory: Outer: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 6: Device Memory: Device Type: Device-nGRE memory
+    CPU MPU: Attribute: Attribute 7: Memory Type: Device memory
+    CPU MPU: Attribute: Attribute 7: Normal Memory: Inner: Memory Attribute Indirection: Write-Through transient
+    CPU MPU: Attribute: Attribute 7: Normal Memory: Inner: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 7: Normal Memory: Inner: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 7: Normal Memory: Outer: Memory Attribute Indirection: Write-Through transient
+    CPU MPU: Attribute: Attribute 7: Normal Memory: Outer: Read: Do not allocate
+    CPU MPU: Attribute: Attribute 7: Normal Memory: Outer: Write: Do not allocate
+    CPU MPU: Attribute: Attribute 7: Device Memory: Device Type: Device-GRE memory
+    CPU MPU: Region: Region 00: Name: ATCM
+    CPU MPU: Region: Region 00: Base: 0x00000000
+    CPU MPU: Region: Region 00: Limit: 0x0001FFFF
+    CPU MPU: Region: Region 00: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 00: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 00: Execute never: Execute Enable
+    CPU MPU: Region: Region 00: Attribute Index: Attribute 3
+    CPU MPU: Region: Region 00: Region enable: Enabled
+    CPU MPU: Region: Region 01: Name: BTCM
+    CPU MPU: Region: Region 01: Base: 0x00100000
+    CPU MPU: Region: Region 01: Limit: 0x0011FFFF
+    CPU MPU: Region: Region 01: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 01: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 01: Execute never: Execute Enable
+    CPU MPU: Region: Region 01: Attribute Index: Attribute 3
+    CPU MPU: Region: Region 01: Region enable: Enabled
+    CPU MPU: Region: Region 02: Name: System RAM
+    CPU MPU: Region: Region 02: Base: 0x10000000
+    CPU MPU: Region: Region 02: Limit: 0x1017FFFF
+    CPU MPU: Region: Region 02: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 02: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 02: Execute never: Execute Enable
+    CPU MPU: Region: Region 02: Attribute Index: Attribute 1
+    CPU MPU: Region: Region 02: Region enable: Enabled
+    CPU MPU: Region: Region 03: Name: Mirror area of System RAM
+    CPU MPU: Region: Region 03: Base: 0x30000000
+    CPU MPU: Region: Region 03: Limit: 0x3017FFFF
+    CPU MPU: Region: Region 03: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 03: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 03: Execute never: Execute Enable
+    CPU MPU: Region: Region 03: Attribute Index: Attribute 3
+    CPU MPU: Region: Region 03: Region enable: Enabled
+    CPU MPU: Region: Region 04: Name: Mirror area of external address space
+    CPU MPU: Region: Region 04: Base: 0x40000000
+    CPU MPU: Region: Region 04: Limit: 0x5FFFFFFF
+    CPU MPU: Region: Region 04: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 04: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 04: Execute never: Execute Enable
+    CPU MPU: Region: Region 04: Attribute Index: Attribute 3
+    CPU MPU: Region: Region 04: Region enable: Enabled
+    CPU MPU: Region: Region 05: Name: External address space
+    CPU MPU: Region: Region 05: Base: 0x60000000
+    CPU MPU: Region: Region 05: Limit: 0x7FFFFFFF
+    CPU MPU: Region: Region 05: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 05: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 05: Execute never: Execute Enable
+    CPU MPU: Region: Region 05: Attribute Index: Attribute 1
+    CPU MPU: Region: Region 05: Region enable: Enabled
+    CPU MPU: Region: Region 06: Name: Non-Safety Peripheral
+    CPU MPU: Region: Region 06: Base: 0x80000000
+    CPU MPU: Region: Region 06: Limit: 0x80FFFFFF
+    CPU MPU: Region: Region 06: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 06: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 06: Execute never: Execute Never
+    CPU MPU: Region: Region 06: Attribute Index: Attribute 5
+    CPU MPU: Region: Region 06: Region enable: Enabled
+    CPU MPU: Region: Region 07: Name: Safety Peripheral
+    CPU MPU: Region: Region 07: Base: 0x81000000
+    CPU MPU: Region: Region 07: Limit: 0x81FFFFFF
+    CPU MPU: Region: Region 07: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 07: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 07: Execute never: Execute Never
+    CPU MPU: Region: Region 07: Attribute Index: Attribute 5
+    CPU MPU: Region: Region 07: Region enable: Enabled
+    CPU MPU: Region: Region 08: Name: LLPP Peripheral
+    CPU MPU: Region: Region 08: Base: 0x90000000
+    CPU MPU: Region: Region 08: Limit: 0x901FFFFF
+    CPU MPU: Region: Region 08: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 08: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 08: Execute never: Execute Never
+    CPU MPU: Region: Region 08: Attribute Index: Attribute 5
+    CPU MPU: Region: Region 08: Region enable: Enabled
+    CPU MPU: Region: Region 09: Name: GIC0
+    CPU MPU: Region: Region 09: Base: 0x94000000
+    CPU MPU: Region: Region 09: Limit: 0x941FFFFF
+    CPU MPU: Region: Region 09: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 09: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 09: Execute never: Execute Never
+    CPU MPU: Region: Region 09: Attribute Index: Attribute 4
+    CPU MPU: Region: Region 09: Region enable: Enabled
+    CPU MPU: Region: Region 10: Name: Debug Private
+    CPU MPU: Region: Region 10: Base: 0xC0000000
+    CPU MPU: Region: Region 10: Limit: 0xC0FFFFFF
+    CPU MPU: Region: Region 10: Sharebility field: Outer Shareable
+    CPU MPU: Region: Region 10: Access Permission(EL1 / EL0): ReadWrite / ReadWrite
+    CPU MPU: Region: Region 10: Execute never: Execute Never
+    CPU MPU: Region: Region 10: Attribute Index: Attribute 4
+    CPU MPU: Region: Region 10: Region enable: Enabled
+    CPU MPU: Region: Region 11: Name: Not Used
+    CPU MPU: Region: Region 11: Base: 0x00000000
+    CPU MPU: Region: Region 11: Limit: 0x00000000
+    CPU MPU: Region: Region 11: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 11: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 11: Execute never: Execute Enable
+    CPU MPU: Region: Region 11: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 11: Region enable: Disabled
+    CPU MPU: Region: Region 12: Name: Not Used
+    CPU MPU: Region: Region 12: Base: 0x00000000
+    CPU MPU: Region: Region 12: Limit: 0x00000000
+    CPU MPU: Region: Region 12: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 12: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 12: Execute never: Execute Enable
+    CPU MPU: Region: Region 12: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 12: Region enable: Disabled
+    CPU MPU: Region: Region 13: Name: Not Used
+    CPU MPU: Region: Region 13: Base: 0x00000000
+    CPU MPU: Region: Region 13: Limit: 0x00000000
+    CPU MPU: Region: Region 13: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 13: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 13: Execute never: Execute Enable
+    CPU MPU: Region: Region 13: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 13: Region enable: Disabled
+    CPU MPU: Region: Region 14: Name: Not Used
+    CPU MPU: Region: Region 14: Base: 0x00000000
+    CPU MPU: Region: Region 14: Limit: 0x00000000
+    CPU MPU: Region: Region 14: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 14: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 14: Execute never: Execute Enable
+    CPU MPU: Region: Region 14: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 14: Region enable: Disabled
+    CPU MPU: Region: Region 15: Name: Not Used
+    CPU MPU: Region: Region 15: Base: 0x00000000
+    CPU MPU: Region: Region 15: Limit: 0x00000000
+    CPU MPU: Region: Region 15: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 15: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 15: Execute never: Execute Enable
+    CPU MPU: Region: Region 15: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 15: Region enable: Disabled
+    CPU MPU: Region: Region 16: Name: Not Used
+    CPU MPU: Region: Region 16: Base: 0x00000000
+    CPU MPU: Region: Region 16: Limit: 0x00000000
+    CPU MPU: Region: Region 16: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 16: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 16: Execute never: Execute Enable
+    CPU MPU: Region: Region 16: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 16: Region enable: Disabled
+    CPU MPU: Region: Region 17: Name: Not Used
+    CPU MPU: Region: Region 17: Base: 0x00000000
+    CPU MPU: Region: Region 17: Limit: 0x00000000
+    CPU MPU: Region: Region 17: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 17: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 17: Execute never: Execute Enable
+    CPU MPU: Region: Region 17: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 17: Region enable: Disabled
+    CPU MPU: Region: Region 18: Name: Not Used
+    CPU MPU: Region: Region 18: Base: 0x00000000
+    CPU MPU: Region: Region 18: Limit: 0x00000000
+    CPU MPU: Region: Region 18: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 18: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 18: Execute never: Execute Enable
+    CPU MPU: Region: Region 18: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 18: Region enable: Disabled
+    CPU MPU: Region: Region 19: Name: Not Used
+    CPU MPU: Region: Region 19: Base: 0x00000000
+    CPU MPU: Region: Region 19: Limit: 0x00000000
+    CPU MPU: Region: Region 19: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 19: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 19: Execute never: Execute Enable
+    CPU MPU: Region: Region 19: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 19: Region enable: Disabled
+    CPU MPU: Region: Region 20: Name: Not Used
+    CPU MPU: Region: Region 20: Base: 0x00000000
+    CPU MPU: Region: Region 20: Limit: 0x00000000
+    CPU MPU: Region: Region 20: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 20: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 20: Execute never: Execute Enable
+    CPU MPU: Region: Region 20: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 20: Region enable: Disabled
+    CPU MPU: Region: Region 21: Name: Not Used
+    CPU MPU: Region: Region 21: Base: 0x00000000
+    CPU MPU: Region: Region 21: Limit: 0x00000000
+    CPU MPU: Region: Region 21: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 21: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 21: Execute never: Execute Enable
+    CPU MPU: Region: Region 21: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 21: Region enable: Disabled
+    CPU MPU: Region: Region 22: Name: Not Used
+    CPU MPU: Region: Region 22: Base: 0x00000000
+    CPU MPU: Region: Region 22: Limit: 0x00000000
+    CPU MPU: Region: Region 22: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 22: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 22: Execute never: Execute Enable
+    CPU MPU: Region: Region 22: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 22: Region enable: Disabled
+    CPU MPU: Region: Region 23: Name: Not Used
+    CPU MPU: Region: Region 23: Base: 0x00000000
+    CPU MPU: Region: Region 23: Limit: 0x00000000
+    CPU MPU: Region: Region 23: Sharebility field: Non-shareable
+    CPU MPU: Region: Region 23: Access Permission(EL1 / EL0): ReadWrite / None
+    CPU MPU: Region: Region 23: Execute never: Execute Enable
+    CPU MPU: Region: Region 23: Attribute Index: Attribute 0
+    CPU MPU: Region: Region 23: Region enable: Disabled
+    CPU MPU: Background Region: Disabled
+    CPU MPU: Instruction Cache: Enabled
+    CPU MPU: Data Cache: Enabled
+    
+  RZN2L
+    stack size (bytes): FIQ stack size: 0x400
+    stack size (bytes): IRQ stack size: 0x400
+    stack size (bytes): ABT stack size: 0x400
+    stack size (bytes): UND stack size: 0x400
+    stack size (bytes): SYS stack size: 0x400
+    stack size (bytes): SVC stack size: 0x400
+    Heap size (bytes): 0x2000
+    C Runtime Initialization : Enabled
+    TFU Mathlib: Enabled
+    
+  RZN2L Family
+    
+  RZN Common
+    MCU Vcc (mV): 3300
+    Parameter checking: Disabled
+    Assert Failures: Return FSP_ERR_ASSERTION
+    Error Log: No Error Log
+    Soft Reset: Disabled
+    Port Protect: Enabled
+    Early BSP Initialization : Disabled
+    Multiplex Interrupt: Disabled
+    
+  Clocks
+    LOCO Enabled
+    PLL1 is initial state
+    Ethernet Clock src: Main clock oscillator
+    CLMA0 Enabled
+    CLMA0 error not mask
+    CLMA3 error not mask
+    CLMA1 error mask
+    CLMA3 Enabled
+    CLMA1 Enabled
+    CLMA2 Enabled
+    CLMA0 CMPL 1
+    CLMA1 CMPL 1
+    CLMA2 CMPL 1
+    CLMA3 CMPL 1
+    Alternative clock: LOCO
+    CLMA0 CMPH 1023
+    CLMA1 CMPH 1023
+    CLMA2 CMPH 1023
+    CLMA3 CMPH 1023
+    ICLK 200MHz
+    CPU0CLK Mulx2
+    CKIO Div/4
+    SCI0ASYNCCLK: 96MHz
+    SCI1ASYNCCLK: 96MHz
+    SCI2ASYNCCLK: 96MHz
+    SCI3ASYNCCLK: 96MHz
+    SCI4ASYNCCLK: 96MHz
+    SCI5ASYNCCLK: 96MHz
+    SPI0ASYNCCLK: 96MHz
+    SPI1ASYNCCLK: 96MHz
+    SPI2ASYNCCLK: 96MHz
+    SPI3ASYNCCLK: 96MHz
+    CANFDCLK Src: PCLKCAN 40MHz
+    XSPI_CLK0 133.3MHz
+    XSPI_CLK1 12.5MHz
+    
+  Pin Configurations
+    RSK+RZN2L -> g_bsp_pin_cfg
+      AN000 B13 SYSTEM_AN000 - - - - - - - - I "Read only" - 
+      AN001 C12 SYSTEM_AN001 - - - - - - - - I "Read only" - 
+      AN002 B14 SYSTEM_AN002 - - - - - - - - I "Read only" - 
+      AN003 C13 SYSTEM_AN003 - - - - - - - - I "Read only" - 
+      AN100 B12 SYSTEM_AN100 - - - - - - - - I "Read only" - 
+      AN101 A14 SYSTEM_AN101 - - - - - - - - I "Read only" - 
+      AN102 B11 SYSTEM_AN102 - - - - - - - - I "Read only" - 
+      AN103 A13 SYSTEM_AN103 - - - - - - - - I "Read only" - 
+      AN104 A12 SYSTEM_AN104 - - - - - - - - I "Read only" - 
+      AN105 B10 SYSTEM_AN105 - - - - - - - - I "Read only" - 
+      AN106 A11 SYSTEM_AN106 - - - - - - - - I "Read only" - 
+      AN107 C9 SYSTEM_AN107 - - - - - - - - I "Read only" - 
+      AVCC18_TSU C14 SYSTEM_AVCC18_TSU - - - - - - - - I "Read only" - 
+      AVCC18_USB P10 SYSTEM_AVCC18_USB - - - - - - - - I "Read only" - 
+      AVCC18_USB R10 SYSTEM_AVCC18_USB - - - - - - - - I "Read only" - 
+      BSCANP G2 SYSTEM_BSCANP - - - - - - - - I "Read only" - 
+      EXTAL R7 CGC_EXTAL - - - - - - - - I "Read only" - 
+      EXTCLKIN R6 CGC_EXTCLKIN - - - - - - - - I "Read only" - 
+      MDX P5 SYSTEM_MDX - - - - - - - - IO "Read only" - 
+      P00_0 C4 ETHER_ETH2_ETH2_RXD3 ETH2_RXD3 Low - "Peripheral mode" - - "BSC: D15; ETHER_ETH2: ETH2_RXD3; PHOSTIF: HD15; SCI2: DE2; SCI2: SCK2" - I - - 
+      P00_1 D5 ETHER_ETH2_ETH2_RXDV_CRSDV_RXCTL ETH2_RXDV Low - "Peripheral mode" - - "BSC: A13; ETHER_ETH2: ETH2_RXDV_CRSDV_RXCTL; IRQ: IRQ0; MTU35: MTIC5U; SCI2: RXD_MISO2; SCI2: SCL2" - I - - 
+      P00_2 A3 ETHER_ETH2_ETH2_TXEN_TXCTL ETH2_TXEN Low - "Peripheral mode" - - "BSC: RD#; ETHER_ETH2: ETH2_TXEN_TXCTL; MTU35: MTIC5V; SCI2: SDA2; SCI2: TXD_MOSI2; USB_HS: USB_OVRCUR" - O - - 
+      P00_3 B3 ETHER_ETH2_ETH2_REFCLK ETH2_REFCLK Low - "Peripheral mode" - - "BSC: RD_WR#; ETHER_ETH2: ETH2_REFCLK; ETHER_ETH2: ETH2_RMII2_REFCLK; IRQ: IRQ1; MTU35: MTIC5W; SCI2: CTS_RTS_SS2#" - O - - 
+      P00_4 A4 - - - - Disabled - - "BSC: WAIT#; DSMIF0: MCLK0; ETHER_ETH2: ETH2_RXER; GPT0: GTIOC0A; IRQ: IRQ13; MTU33: MTIOC3A; PHOSTIF: HWAIT#" - None - - 
+      P00_5 B4 ETHER_ETHSW_ETHSW_PHYLINK2 ETH2_LINK Low - "Peripheral mode" - - "BSC: CS0#; DSMIF0: MDAT0; ETHER_ESC: ESC_PHYLINK0; ETHER_ESC: ESC_PHYLINK2; ETHER_ETHSW: ETHSW_PHYLINK0; ETHER_ETHSW: ETHSW_PHYLINK2; GPT0: GTIOC0B; MTU33: MTIOC3C" - I - - 
+      P00_6 C3 ETHER_ETH2_ETH2_TXCLK_TXC ETH2_TXCLK High - "Peripheral mode" - - "BSC: CS5#; ETHER_ETH2: ETH2_TXCLK_TXC; GPT1: GTIOC1A; MTU33: MTIOC3B" - IO - - 
+      P00_7 D4 - - - - Disabled - - "BSC: RAS#; GPT2: GTIOC2A; IRQ: IRQ13; MTU34: MTIOC4A" - None - - 
+      P01_0 A2 - - - - Disabled - - "BSC: CAS#; DSMIF1: MCLK1; ETHER_ESC: ESC_MDIO; ETHER_ETHSW: ETHSW_MDIO; ETHER_GMAC: GMAC_MDIO; GPT3: GTIOC3A; MTU34: MTIOC4C; SCI2: CTS2#" - None - - 
+      P01_1 D3 - - - - Disabled - - "BSC: CKE; DSMIF1: MDAT1; ETHER_ESC: ESC_MDC; ETHER_ETHSW: ETHSW_MDC; ETHER_GMAC: GMAC_MDC; GPT1: GTIOC1B; MTU33: MTIOC3D; SCI2: DE2" - None - - 
+      P01_2 B2 ETHER_ETH2_ETH2_TXD3 ETH2_TXD3 High - "Peripheral mode" - - "BSC: CS2#; ETHER_ETH2: ETH2_TXD3; GPT2: GTIOC2B; IRQ: IRQ2; MTU34: MTIOC4B" - O - - 
+      P01_3 C2 ETHER_ETH2_ETH2_TXD2 ETH2_TXD2 High - "Peripheral mode" - - "BSC: AH#; ETHER_ETH2: ETH2_TXD2; GPT3: GTIOC3B; MTU34: MTIOC4D" - O - - 
+      P01_4 E4 ETHER_ETH2_ETH2_TXD1 ETH2_TXD1 High - "Peripheral mode" - - "BSC: WE1#_DQMLU; ETHER_ETH2: ETH2_TXD1; IRQ: IRQ3; MTU_POE3: POE0#" - O - - 
+      P01_5 B1 ETHER_ETH2_ETH2_TXD0 ETH2_TXD0 High - "Peripheral mode" - - "BSC: WE0#_DQMLL; ETHER_ETH2: ETH2_TXD0" - O - - 
+      P01_6 D2 - - - - Disabled - - "BSC: A20; CANFD1: CANTXDP1; ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG1; GPT9: GTIOC9A; MTU31: MTIOC1A; PHOSTIF: HA20; SCI1: CTS1#; TRACE: TRACEDATA0" - None - - 
+      P01_7 C1 CANFD0_CANRX0 CAN_RX Middle - "Peripheral mode" - - "ADC0: ADTRG0#; BSC: A19; CANFD0: CANRX0; ETHER_ETHSW: ETHSW_LPI1; GPT9: GTIOC9B; MTU31: MTIOC1B; PHOSTIF: HA19; SCI1: SCK1; SPI3: SPI_RSPCK3; TRACE: TRACEDATA1" - I - - 
+      P02_0 E3 - - - - Disabled - - "BSC: A18; CANFD1: CANTX1; ETHER_ETHSW: ETHSW_LPI2; GPT: GTADSML0; IRQ: IRQ4; PHOSTIF: HA18; SCI1: RXD_MISO1; SCI1: SCL1; SPI3: SPI_MISO3; TRACE: TRACEDATA2; USB_HS: USB_OTGID" - None - - 
+      P02_1 D1 - - - - Disabled - - "BSC: A17; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; PHOSTIF: HA17; SCI1: DE1" - None - - 
+      P02_2 F3 CANFD0_CANTX0 CAN_TX Middle - "Peripheral mode" - - "BSC: A16; CANFD0: CANTX0; ETHER_ETHSW: ETHSW_TDMAOUT0; GPT10: GTIOC10A; IRQ: IRQ14; MTU32: MTIOC2A; MTU_POE3: POE10#; PHOSTIF: HA16; RTC: RTCAT1HZ; SCI1: SDA1; SCI1: TXD_MOSI1; SPI3: SPI_MOSI3" - O - - 
+      P02_3 E1 - - - - Disabled - - "BSC: A15; BSC: AH#; CANFD1: CANRX1; ETHER_ETHSW: ETHSW_TDMAOUT1; GPT10: GTIOC10B; IRQ: IRQ15; MTU32: MTIOC2B; MTU_POE3: POE11#; PHOSTIF: HA15; SCI1: CTS_RTS_SS1#; SPI3: SPI_SSL30" - None - - 
+      P02_4 F4 JTAG/SWD_TDO TDO High - "Peripheral mode" - - "BSC: WE0#_DQMLL; JTAG/SWD: TDO; SCI1: DE1; SPI3: SPI_SSL33" - O - - 
+      P02_5 F2 JTAG/SWD_TDI TDI Low - "Peripheral mode" - - "BSC: WE1#_DQMLU; ETHER_ETHSW: ETHSW_TDMAOUT3; JTAG/SWD: TDI; SCI5: SCK5; SPI3: SPI_SSL31" - I - - 
+      P02_6 F5 JTAG/SWD_TMS_SWDIO TMS High - "Peripheral mode" - - "JTAG/SWD: TMS_SWDIO; SCI5: RXD_MISO5; SCI5: SCL5" - IO - - 
+      P02_7 F1 JTAG/SWD_TCK_SWCLK TCK Low - "Peripheral mode" - - "JTAG/SWD: TCK_SWCLK; SCI5: SDA5; SCI5: TXD_MOSI5" - I - - 
+      P03_0 G3 GPIO ETH_LED4 Low - "Output mode (Low & Not Into Input)" - - "BSC: A14; BSC: CS5#; CANFD1: CANTXDP1; GPT: GTADSML1; IRQ: IRQ14; PHOSTIF: HA14; SCI2: SCK2; SPI3: SPI_SSL32; TRACE: TRACEDATA3" - IO - - 
+      P03_5 G1 - - - - Disabled - - "BSC: A12; DSMIF2: MCLK2; ETHER_ETH2: ETH2_CRS; GPT4: GTIOC4A; IRQ: IRQ5; MTU33: MTIOC3A; PHOSTIF: HA12; SCI2: RXD_MISO2; SCI2: SCL2" - None - - 
+      P03_6 G4 - - - - Disabled - - "BSC: A11; DSMIF2: MDAT2; ETHER_ETH2: ETH2_COL; GPT4: GTIOC4B; IRQ: IRQ8; MTU33: MTIOC3B; PHOSTIF: HA11; SCI2: SDA2; SCI2: TXD_MOSI2; SPI1: SPI_SSL13; TRACE: TRACEDATA4" - None - - 
+      P03_7 G5 - - - - Disabled - - "BSC: A10; ETHER_ETH2: ETH2_TXER; GPT5: GTIOC5A; IRQ: IRQ9; MTU33: MTIOC3C; PHOSTIF: HA10; SCI3: SCK3; TRACE: TRACEDATA5" - None - - 
+      P04_0 H1 - - - - Disabled - - "BSC: A9; GPT5: GTIOC5B; MTU33: MTIOC3D; PHOSTIF: HA9; SCI3: RXD_MISO3; SCI3: SCL3; TRACE: TRACEDATA6" - None - - 
+      P04_1 H2 GPIO LED_RED1 Low - "Output mode (Low & Not Into Input)" - - "BSC: CKIO; IIC2: IIC_SDA2; PHOSTIF: HCKIO; SCI3: SDA3; SCI3: TXD_MOSI3; SPI0: SPI_MOSI0" - IO - - 
+      P04_4 H4 GPIO ETH_LED6 Low - "Output mode (Low & Not Into Input)" - - "BSC: A8; GPT: GTADSMP0; IRQ: IRQ10; MTU_POE3: POE10#; PHOSTIF: HA8; SCI3: CTS3#; SPI1: SPI_RSPCK1; TRACE: TRACEDATA7" - IO - - 
+      P04_5 H3 - - - - Disabled - - "BSC: A7; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT0; PHOSTIF: HA7; SCI3: DE3" - None - - 
+      P04_6 H5 - - - - Disabled - - "BSC: A6; DMAC: DACK; ETHER_ETH1: ETH1_TXER; PHOSTIF: HA6; RTC: RTCAT1HZ" - None - - 
+      P04_7 J1 - - - - Disabled - - "BSC: A5; ETHER_ETH0: ETH0_TXER; ETHER_ETH2: ETH2_TXER; PHOSTIF: HA5; SPI2: SPI_SSL21" - None - - 
+      P05_0 J5 GPIO ETH_LED7 Low - "Output mode (Low & Not Into Input)" - - "BSC: A4; CANFD0: CANTXDP0; CMTW0: CMTW0_TOC0; DSMIF3: MCLK3; ETHER_ETH1: ETH1_CRS; GPT6: GTIOC6A; IRQ: IRQ12; MTU34: MTIOC4A; PHOSTIF: HA4; SCI5: CTS_RTS_SS5#; USB_HS: USB_VBUSEN" - IO - - 
+      P05_1 J2 - - - - Disabled - - "BSC: A3; CANFD0: CANRXDP0; CMTW0: CMTW0_TIC1; DSMIF3: MDAT3; ETHER_ETH1: ETH1_COL; GPT6: GTIOC6B; IRQ: IRQ13; MTU34: MTIOC4B; PHOSTIF: HA3; SCI5: CTS5#; USB_HS: USB_EXICEN" - None - - 
+      P05_2 J4 IIC1_IIC_SCL1 SCL Middle - "Peripheral mode" - - "BSC: A2; CANFD0: CANRX0; CMTW0: CMTW0_TOC0; DMAC: DREQ; ETHER_ETH0: ETH0_CRS; GPT7: GTIOC7A; GPT_POEG: GTETRGSA; IIC1: IIC_SCL1; IRQ: IRQ14; MTU34: MTIOC4C; PHOSTIF: HA2; SCI5: DE5; USB_HS: USB_VBUSEN" - IO - - 
+      P05_3 J3 IIC1_IIC_SDA1 SDA Middle - "Peripheral mode" - - "BSC: A1; CANFD0: CANTX0; CMTW0: CMTW0_TIC0; ETHER_ETH0: ETH0_COL; GPT7: GTIOC7B; GPT_POEG: GTETRGSB; IIC1: IIC_SDA1; IRQ: IRQ15; MTU34: MTIOC4D; MTU_POE3: POE11#; PHOSTIF: HA1; SCI4: SCK4; USB_HS: USB_EXICEN" - IO - - 
+      P05_4 K1 GPIO SW2 - - "Input mode" - - "BSC: A0; CANFD0: CANTXDP0; DMAC: DACK; ETHER_ETHSW: ETHSW_LPI0; GPT14: GTIOC14A; IRQ: IRQ12; PHOSTIF: HA0; SCI4: RXD_MISO4; SCI4: SCL4; SPI0: SPI_SSL00; USB_HS: USB_OVRCUR" - IO - - 
+      P05_5 K2 ETHER_ETHSW_ETHSW_PHYLINK1 ETH1_LINK Low - "Peripheral mode" - - "CMTW0: CMTW0_TOC1; ETHER_ESC: ESC_PHYLINK1; ETHER_ETHSW: ETHSW_PHYLINK1; GPT14: GTIOC14B; SPI2: SPI_RSPCK2" - I - - 
+      P05_6 K3 - - - - Disabled - - "CMTW1: CMTW1_TIC0; ETHER_ETH1: ETH1_RXER; GPT15: GTIOC15A; IRQ: IRQ12; SPI2: SPI_SSL22" - None - - 
+      P05_7 M1 ETHER_ETH1_ETH1_TXD2 ETH1_TXD2 High - "Peripheral mode" - - "CMTW1: CMTW1_TOC1; ETHER_ETH1: ETH1_TXD2; GPT15: GTIOC15B; SCI4: SDA4; SCI4: TXD_MOSI4; SPI2: SPI_SSL23" - O - - 
+      P06_0 L2 ETHER_ETH1_ETH1_TXD3 ETH1_TXD3 High - "Peripheral mode" - - "CANFD1: CANRX1; CMTW1: CMTW1_TOC0; ETHER_ETH1: ETH1_TXD3; GPT16: GTIOC16A; SCI4: CTS_RTS_SS4#; SPI2: SPI_SSL23" - O - - 
+      P06_1 L3 ETHER_ETH1_ETH1_REFCLK ETH1_REFCLK Low - "Peripheral mode" - - "CANFD1: CANTX1; ETHER_ETH1: ETH1_REFCLK; ETHER_ETH1: ETH1_RMII1_REFCLK; GPT16: GTIOC16B; SCI4: CTS4#; SPI2: SPI_SSL22" - O - - 
+      P06_2 M2 ETHER_ETH1_ETH1_TXD1 ETH1_TXD1 High - "Peripheral mode" - - "CANFD1: CANRXDP1; ETHER_ETH1: ETH1_TXD1; GPT17: GTIOC17A" - O - - 
+      P06_3 K4 ETHER_ETH1_ETH1_TXD0 ETH1_TXD0 High - "Peripheral mode" - - "CANFD1: CANTXDP1; CMTW1: CMTW1_TIC1; ETHER_ETH1: ETH1_TXD0; GPT17: GTIOC17B; SCI4: DE4; SPI1: SPI_MISO1" - O - - 
+      P06_4 N1 ETHER_ETH1_ETH1_TXCLK_TXC ETH1_TXCLK High - "Peripheral mode" - - "ETHER_ETH1: ETH1_TXCLK_TXC; GPT11: GTIOC11A; SPI1: SPI_MOSI1" - IO - - 
+      P06_5 N2 ETHER_ETH1_ETH1_TXEN_TXCTL ETH1_TXEN Low - "Peripheral mode" - - "ETHER_ETH1: ETH1_TXEN_TXCTL; GPT11: GTIOC11B" - O - - 
+      P06_6 L4 ETHER_ETH1_ETH1_RXD0 ETH1_RXD0 Low - "Peripheral mode" - - "ETHER_ETH1: ETH1_RXD0; GPT12: GTIOC12A; SPI1: SPI_SSL10" - I - - 
+      P06_7 M3 ETHER_ETH1_ETH1_RXD1 ETH1_RXD1 Low - "Peripheral mode" - - "ETHER_ETH1: ETH1_RXD1; GPT12: GTIOC12B; SPI1: SPI_SSL11" - I - - 
+      P07_0 P1 ETHER_ETH1_ETH1_RXD2 ETH1_RXD2 Low - "Peripheral mode" - - "ETHER_ETH1: ETH1_RXD2; GPT13: GTIOC13A" - I - - 
+      P07_1 N3 ETHER_ETH1_ETH1_RXD3 ETH1_RXD3 Low - "Peripheral mode" - - "ETHER_ETH1: ETH1_RXD3; GPT13: GTIOC13B" - I - - 
+      P07_2 P2 ETHER_ETH1_ETH1_RXDV_CRSDV_RXCTL ETH1_RXDV Low - "Peripheral mode" - - "ETHER_ETH1: ETH1_RXDV_CRSDV_RXCTL" - I - - 
+      P07_3 M4 ETHER_ETH1_ETH1_RXCLK_REF_CLK_RXC ETH1_RXCLK Low - "Peripheral mode" - - "ETHER_ETH1: ETH1_RXCLK_REF_CLK_RXC" - I - - 
+      P07_4 R2 USB_HS_USB_VBUSIN USB_VBUSIN - - "Peripheral mode" - - "ADC0: ADTRG0#; IRQ: IRQ1; USB_HS: USB_VBUSIN" - I - - 
+      P08_4 N4 ETHER_ETH0_ETH0_RXD3 ETH0_RXD3 Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_RXD3; MTU36: MTIOC6A" - I - - 
+      P08_5 P3 ETHER_ETH0_ETH0_RXDV_CRSDV_RXCTL ETH0_RXDV Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_RXDV_CRSDV_RXCTL; MTU36: MTIOC6B" - I - - 
+      P08_6 M5 ETHER_ETH0_ETH0_RXCLK_REF_CLK_RXC ETH0_RXCLK Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_RXCLK_REF_CLK_RXC; MTU36: MTIOC6C" - I - - 
+      P08_7 N5 ETHER_GMAC_GMAC_MDC ETH_MDC Low - "Peripheral mode" - - "ETHER_ESC: ESC_MDC; ETHER_ETHSW: ETHSW_MDC; ETHER_GMAC: GMAC_MDC; MTU36: MTIOC6D" - O - - 
+      P09_0 P4 ETHER_GMAC_GMAC_MDIO ETH_MDIO Low - "Peripheral mode" - - "ETHER_ESC: ESC_MDIO; ETHER_ETHSW: ETHSW_MDIO; ETHER_GMAC: GMAC_MDIO; MTU37: MTIOC7A" - IO - - 
+      P09_1 R3 ETHER_ETH0_ETH0_REFCLK ETH0_REFCLK Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_REFCLK; ETHER_ETH0: ETH0_RMII0_REFCLK; MTU37: MTIOC7B" - O - - 
+      P09_2 N6 - - - - Disabled - - "ETHER_ETH0: ETH0_RXER; IRQ: IRQ0; MTU37: MTIOC7C" - None - - 
+      P09_3 R4 ETHER_ETH0_ETH0_TXD3 ETH0_TXD3 High - "Peripheral mode" - - "ETHER_ETH0: ETH0_TXD3; MTU37: MTIOC7D" - O - - 
+      P09_4 M6 ETHER_ETH0_ETH0_TXD2 ETH0_TXD2 High - "Peripheral mode" - - "ETHER_ETH0: ETH0_TXD2" - O - - 
+      P09_5 N7 ETHER_ETH0_ETH0_TXD1 ETH0_TXD1 High - "Peripheral mode" - - "ETHER_ETH0: ETH0_TXD1" - O - - 
+      P09_6 M7 ETHER_ETH0_ETH0_TXD0 ETH0_TXD0 High - "Peripheral mode" - - "ETHER_ETH0: ETH0_TXD0" - O - - 
+      P09_7 L7 ETHER_ETH0_ETH0_TXCLK_TXC ETH0_TXCLK High - "Peripheral mode" - - "ETHER_ETH0: ETH0_TXCLK_TXC" - IO - - 
+      P10_0 N8 ETHER_ETH0_ETH0_TXEN_TXCTL ETH0_TXEN Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_TXEN_TXCTL" - O - - 
+      P10_1 M8 ETHER_ETH0_ETH0_RXD0 ETH0_RXD0 Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_RXD0" - I - - 
+      P10_2 L8 ETHER_ETH0_ETH0_RXD1 ETH0_RXD1 Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_RXD1" - I - - 
+      P10_3 L9 ETHER_ETH0_ETH0_RXD2 ETH0_RXD2 Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_RXD2; RTC: RTCAT1HZ" - I - - 
+      P10_4 M9 ETHER_ETHSW_ETHSW_PHYLINK0 ETH0_LINK Low - "Peripheral mode" - - "ETHER_ESC: ESC_PHYLINK0; ETHER_ETHSW: ETHSW_PHYLINK0; IRQ: IRQ11" - I - - 
+      P12_4 N11 - - - - Disabled - - "BSC: D15; ETHER_ETH1: ETH1_CRS; GPT8: GTIOC8B; MBXSEM: MBX_HINT#; MTU38: MTIOC8B; SPI0: SPI_SSL01; TRACE: TRACEDATA0" - None - - 
+      P13_2 L10 IIC0_IIC_SCL0 EEPROM_SCL Middle - "Peripheral mode" - - "BSC: A13; BSC: D9; DSMIF4: MCLK4; ETHER_ESC: ESC_I2CCLK; ETHER_ETHSW: ETHSW_PTPOUT2; GPT10: GTIOC10A; IIC0: IIC_SCL0; IRQ: IRQ5; MTU30: MTIOC0A; MTU_POE3: POE8#; SCI1: CTS_RTS_SS1#; SPI0: SPI_MISO0; TRACE: TRACEDATA6" - IO - - 
+      P13_3 N12 IIC0_IIC_SDA0 EEPROM_SDA Middle - "Peripheral mode" - - "BSC: D8; BSC: RD#; CMTW1: CMTW1_TOC0; DSMIF4: MDAT4; ETHER_ESC: ESC_I2CDATA; ETHER_ETHSW: ETHSW_PTPOUT3; GPT10: GTIOC10B; IIC0: IIC_SDA0; MTU30: MTIOC0B; MTU30: MTIOC0C; SCI1: CTS1#; SPI0: SPI_RSPCK0; TRACE: TRACEDATA7" - IO - - 
+      P13_4 L12 GPIO ESC_RESETOUT Low - "Output mode (Low & Not Into Input)" - - "BSC: A0; ETHER_ESC: ESC_RESETOUT#; GPT8: GTIOC8B; MTU30: MTIOC0D" - IO - - 
+      P13_5 M12 GPIO SW3_Pin2 - - "Input mode" - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG0; IIC2: IIC_SCL2; MTU3: MTCLKA; SPI1: SPI_RSPCK1; XSPI0: XSPI0_WP1#" - IO - - 
+      P13_6 M13 GPIO SW3_Pin1 - - "Input mode" - - "ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT0; MTU3: MTCLKB; XSPI0: XSPI0_WP0#" - IO - - 
+      P13_7 M11 GPIO SW3_Pin4 - - "Input mode" - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG1; MBXSEM: MBX_HINT#; MTU3: MTCLKC; XSPI0: XSPI0_ECS1#" - IO - - 
+      P14_0 L13 GPIO SW3_Pin3 Low - "Output mode (Low & Not Into Input)" - - "ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; MTU3: MTCLKD; XSPI0: XSPI0_INT0#" - IO - - 
+      P14_1 L14 GPIO - Low - "Output mode (Low & Not Into Input)" - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_ETH1: ETH1_COL; ETHER_GMAC: GMAC_PTPTRG1; GPT8: GTIOC8A; MTU38: MTIOC8A; SHOSTIF: HSPI_IO0; XSPI0: XSPI0_INT1#" - IO - - 
+      P14_2 K12 XSPI0_XSPI0_ECS0# XSPI0_ECS Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_CRS; ETHER_ETH2: ETH2_CRS; GPT8: GTIOC8B; IRQ: IRQ6; MTU38: MTIOC8B; SHOSTIF: HSPI_CK; XSPI0: XSPI0_ECS0#" - I - - 
+      P14_3 M14 GPIO - Low - "Output mode (Low & Not Into Input)" - - "ETHER_ETH0: ETH0_COL; ETHER_ETH2: ETH2_COL; MTU30: MTIOC0A; SHOSTIF: HSPI_IO1; XSPI0: XSPI0_RSTO1#" - IO - - 
+      P14_4 J13 XSPI0_XSPI0_DS XSPI0_DS High - "Peripheral mode" - - "BSC: BS#; ETHER_ESC: ESC_IRQ; MTU30: MTIOC0B; PHOSTIF: HBS#; XSPI0: XSPI0_DS" - IO - - 
+      P14_5 J12 XSPI0_XSPI0_CKN XSPI0_CKN High - "Peripheral mode" - - "BSC: CS3#; MTU_POE3: POE8#; SHOSTIF: HSPI_INT#; XSPI0: XSPI0_CKN" - O - - 
+      P14_6 K13 XSPI0_XSPI0_CKP XSPI0_CKP High - "Peripheral mode" - - "BSC: A21; XSPI0: XSPI0_CKP" - O - - 
+      P14_7 M15 XSPI0_XSPI0_IO0 XSPI0_IO0 High - "Peripheral mode" - - "BSC: A22; BSC: BS#; SCI5: SCK5; SPI1: SPI_MISO1; XSPI0: XSPI0_IO0" - IO - - 
+      P15_0 L11 XSPI0_XSPI0_IO1 XSPI0_IO1 High - "Peripheral mode" - - "BSC: A23; BSC: CKE; SCI5: RXD_MISO5; SCI5: SCL5; SPI1: SPI_MOSI1; XSPI0: XSPI0_IO1" - IO - - 
+      P15_1 K14 XSPI0_XSPI0_IO2 XSPI0_IO2 High - "Peripheral mode" - - "BSC: A24; BSC: CAS#; MTU30: MTIOC0C; SCI5: SDA5; SCI5: TXD_MOSI5; SPI1: SPI_SSL10; XSPI0: XSPI0_IO2" - IO - - 
+      P15_2 K15 XSPI0_XSPI0_IO3 XSPI0_IO3 High - "Peripheral mode" - - "BSC: A25; BSC: RAS#; MTU30: MTIOC0D; SCI5: CTS_RTS_SS5#; SPI1: SPI_SSL11; XSPI0: XSPI0_IO3" - IO - - 
+      P15_3 K11 XSPI0_XSPI0_IO4 XSPI0_IO4 High - "Peripheral mode" - - "BSC: D11; DSMIF1: MCLK1; MTU38: MTIOC8C; XSPI0: XSPI0_IO4" - IO - - 
+      P15_4 H13 XSPI0_XSPI0_IO5 XSPI0_IO5 High - "Peripheral mode" - - "BSC: D12; DSMIF1: MDAT1; MTU38: MTIOC8D; XSPI0: XSPI0_IO5" - IO - - 
+      P15_5 J14 XSPI0_XSPI0_IO6 XSPI0_IO6 High - "Peripheral mode" - - "BSC: D13; DSMIF2: MCLK2; XSPI0: XSPI0_IO6" - IO - - 
+      P15_6 H12 XSPI0_XSPI0_IO7 XSPI0_IO7 High - "Peripheral mode" - - "BSC: D14; DSMIF2: MDAT2; SPI1: SPI_SSL12; XSPI0: XSPI0_IO7" - IO - - 
+      P15_7 J15 XSPI0_XSPI0_CS0# OSPI_CS High - "Peripheral mode" - - "DMAC: TEND; SCI5: CTS5#; SPI1: SPI_SSL13; XSPI0: XSPI0_CS0#" - O - - 
+      P16_0 G13 XSPI0_XSPI0_CS1# ORAM_CS0 High - "Peripheral mode" - - "DSMIF3: MCLK3; ETHER_ETH0: ETH0_TXER; ETHER_ETH2: ETH2_REFCLK; SCI0: SDA0; SCI0: TXD_MOSI0; SHOSTIF: HSPI_CS#; SPI3: SPI_MOSI3; XSPI0: XSPI0_CS1#" - O - - 
+      P16_1 H11 XSPI0_XSPI0_RESET0# XSPI0_RESET0 Low - "Peripheral mode" - - "ADC0: ADTRG0#; BSC: CS2#; CMTW0: CMTW0_TOC1; DSMIF3: MDAT3; PHOSTIF: HCS1#; SCI0: RXD_MISO0; SCI0: SCL0; SPI3: SPI_MISO3; XSPI0: XSPI0_RESET0#" - O - - 
+      P16_2 H14 - - - - Disabled - - "IRQ: NMI; PHOSTIF: HERROUT#; SCI0: CTS0#; SHOSTIF: HSPI_IO2; SPI3: SPI_RSPCK3; USB_HS: USB_EXICEN; XSPI0: XSPI0_RESET1#" - None - - 
+      P16_3 G12 GPIO SW1 - - "Input mode" - - "BSC: CS3#; ETHER_ETH1: ETH1_CRS; ETHER_ETH1: ETH1_TXER; GPT: GTADSMP1; IRQ: IRQ7; SCI0: SCK0; SHOSTIF: HSPI_IO3; SPI3: SPI_SSL30; XSPI0: XSPI0_RSTO0#" - IO - - 
+      P16_5 H15 SCI0_TXD_MOSI0 UART_USB_TX High - "Peripheral mode" - - "BSC: A15; MTU35: MTIC5U; SCI0: SDA0; SCI0: TXD_MOSI0; SHOSTIF: HSPI_IO4" - IO - - 
+      P16_6 G11 SCI0_RXD_MISO0 UART_USB_RX High - "Peripheral mode" - - "BSC: CS0#; IRQ: IRQ8; MTU35: MTIC5V; PHOSTIF: HCS0#; SCI0: RXD_MISO0; SCI0: SCL0; SHOSTIF: HSPI_IO5" - IO - - 
+      P16_7 G14 - - - - Disabled - - "BSC: A13; MTU35: MTIC5W; PHOSTIF: HA13; SCI0: SCK0; XSPI1: XSPI1_IO0" - None - - 
+      P17_0 F12 - - - - Disabled - - "ETHER_ESC: ESC_IRQ; SCI0: CTS_RTS_SS0#; XSPI1: XSPI1_IO1" - None - - 
+      P17_3 F14 GPIO LED_RED2 Low - "Output mode (Low & Not Into Input)" - - "ADC1: ADTRG1#; DMAC: DREQ; GPT_POEG: GTETRGA; MTU_POE3: POE0#; SPI3: SPI_SSL31; TRACE: TRACECTL; XSPI1: XSPI1_IO2" - IO - - 
+      P17_4 F13 - - - - Disabled - - "DMAC: DACK; GPT0: GTIOC0A; GPT_POEG: GTETRGB; MTU33: MTIOC3C; SCI3: CTS3#; SPI3: SPI_SSL32; TRACE: TRACECLK; XSPI1: XSPI1_IO3" - None - - 
+      P17_5 F15 USB_HS_USB_OVRCUR USB_OVRCUR Low - "Peripheral mode" - - "DMAC: TEND; GPT0: GTIOC0B; GPT_POEG: GTETRGC; MTU33: MTIOC3A; USB_HS: USB_OVRCUR" - I - - 
+      P17_6 G15 - - - - Disabled - - "BSC: RD_WR#; GPT1: GTIOC1A; MTU33: MTIOC3B; PHOSTIF: HWRSTB#; SCI3: SCK3; XSPI1: XSPI1_DS" - None - - 
+      P17_7 E15 SCI3_RXD_MISO3 SCI_RXD High - "Peripheral mode" - - "BSC: RD#; DMAC: DACK; GPT2: GTIOC2A; GPT3: GTIOC3A; MTU34: MTIOC4A; MTU34: MTIOC4C; PHOSTIF: HRD#; SCI3: RXD_MISO3; SCI3: SCL3; XSPI1: XSPI1_CKP" - IO - - 
+      P18_0 E14 SCI3_TXD_MOSI3 SCI_TXD High - "Peripheral mode" - - "BSC: WE0#_DQMLL; GPT2: GTIOC2A; GPT3: GTIOC3A; MTU34: MTIOC4A; MTU34: MTIOC4C; PHOSTIF: HWR0#; SCI3: SDA3; SCI3: TXD_MOSI3; SHOSTIF: HSPI_IO6" - IO - - 
+      P18_1 D15 - - - - Disabled - - "ADC1: ADTRG1#; BSC: WE1#_DQMLU; GPT1: GTIOC1B; IRQ: IRQ10; MTU33: MTIOC3D; PHOSTIF: HWR1#; SCI3: CTS_RTS_SS3#; SHOSTIF: HSPI_IO7" - None - - 
+      P18_2 D14 GPIO LED_GREEN Low - "Output mode (Low & Not Into Input)" - - "BSC: BS#; ETHER_ETH1: ETH1_COL; GPT2: GTIOC2B; GPT3: GTIOC3B; IIC2: IIC_SDA2; MTU34: MTIOC4B; MTU34: MTIOC4D; SCI0: SCK0; XSPI1: XSPI1_CS0#" - IO - - 
+      P18_3 E13 - - - - Disabled - - "BSC: CKE; CANFD1: CANRXDP1; CMTW1: CMTW1_TIC1; ETHER_ETH2: ETH2_CRS; GPT2: GTIOC2B; GPT3: GTIOC3B; IRQ: IRQ0; MTU34: MTIOC4B; MTU34: MTIOC4D; XSPI1: XSPI1_IO4" - None - - 
+      P18_4 E12 SPI2_SPI_RSPCK2 SCK High - "Peripheral mode" - - "BSC: CAS#; CANFD0: CANTX0; ETHER_ETH1: ETH1_CRS; IRQ: IRQ1; MTU35: MTIC5U; SCI4: SDA4; SCI4: TXD_MOSI4; SPI2: SPI_RSPCK2; XSPI1: XSPI1_IO5" - IO - - 
+      P18_5 D13 SPI2_SPI_MOSI2 MOSI High - "Peripheral mode" - - "BSC: RAS#; CANFD0: CANRX0; ETHER_ETH2: ETH2_COL; MTU35: MTIC5V; SCI4: RXD_MISO4; SCI4: SCL4; SPI2: SPI_MOSI2; TRACE: TRACECTL; XSPI1: XSPI1_IO6" - IO - - 
+      P18_6 C15 SPI2_SPI_MISO2 MISO High - "Peripheral mode" - - "ADC0: ADTRG0#; ETHER_ETH1: ETH1_COL; IIC2: IIC_SCL2; IRQ: IRQ11; MTU35: MTIC5W; SCI4: DE4; SCI4: SCK4; SPI2: SPI_MISO2; TRACE: TRACECLK; XSPI1: XSPI1_IO7" - IO - - 
+      P19_0 B15 USB_HS_USB_VBUSEN USB_VBUSEN Low - "Peripheral mode" - - "USB_HS: USB_VBUSEN" - O - - 
+      P20_1 B9 GPIO ETH_LED2_MDV0 Low - "Output mode (Low & Not Into Input)" - - "ETHER_ESC: ESC_LINKACT0; ETHER_ETHSW: ETHSW_PTPOUT3; ETHER_ETHSW: ETHSW_TDMAOUT0" - IO - - 
+      P20_2 D8 GPIO ETH_LED0_MDV1 Low - "Output mode (Low & Not Into Input)" - - "ETHER_ESC: ESC_LEDRUN; ETHER_ESC: ESC_LEDSTER; ETHER_ETHSW: ETHSW_PTPOUT2; ETHER_ETHSW: ETHSW_TDMAOUT1; SCI3: DE3" - IO - - 
+      P20_3 D9 GPIO ETH_LED1_MDV2 Low - "Output mode (Low & Not Into Input)" - - "ETHER_ESC: ESC_LEDERR; ETHER_ETHSW: ETHSW_PTPOUT1; ETHER_ETHSW: ETHSW_TDMAOUT2" - IO - - 
+      P20_4 A9 GPIO ETH_LED3_MDV3 Low - "Output mode (Low & Not Into Input)" - - "ETHER_ESC: ESC_LINKACT1; ETHER_ETHSW: ETHSW_PTPOUT0; ETHER_ETHSW: ETHSW_TDMAOUT3" - IO - - 
+      P21_1 B8 SPI2_SPI_SSL20 CS High - "Peripheral mode" - - "BSC: D0; CMTW0: CMTW0_TIC0; DSMIF0: MCLK0; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; GPT14: GTIOC14A; IIC1: IIC_SCL1; MTU36: MTIOC6A; PHOSTIF: HD0; SCI5: SCK5; SHOSTIF: HSPI_INT#; SPI2: SPI_SSL20; TRACE: TRACEDATA0" - IO - - 
+      P21_2 C8 - - - - Disabled - - "BSC: D1; CMTW0: CMTW0_TIC1; DSMIF0: MDAT0; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; GPT14: GTIOC14B; IIC1: IIC_SDA1; MTU36: MTIOC6B; PHOSTIF: HD1; SCI5: RXD_MISO5; SCI5: SCL5; SPI2: SPI_MISO2; TRACE: TRACEDATA1" - None - - 
+      P21_3 A8 - - - - Disabled - - "BSC: D2; DSMIF1: MCLK1; GPT15: GTIOC15A; IRQ: NMI; MTU36: MTIOC6C; PHOSTIF: HD2; SCI5: SDA5; SCI5: TXD_MOSI5; SPI3: SPI_SSL33; TRACE: TRACEDATA2" - None - - 
+      P21_4 E7 - - - - Disabled - - "BSC: D3; DSMIF1: MDAT1; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; GPT15: GTIOC15B; MBXSEM: MBX_HINT#; MTU36: MTIOC6D; PHOSTIF: HD3; SCI5: CTS_RTS_SS5#; SPI0: SPI_SSL02; TRACE: TRACEDATA3" - None - - 
+      P21_5 C7 - - - - Disabled - - "ADC1: ADTRG1#; BSC: D4; CMTW1: CMTW1_TOC1; DSMIF2: MCLK2; GPT16: GTIOC16A; IRQ: IRQ6; MTU37: MTIOC7A; PHOSTIF: HD4; SCI5: CTS5#; SPI0: SPI_MISO0; TRACE: TRACEDATA4" - None - - 
+      P21_6 D7 - - - - Disabled - - "BSC: D5; DMAC: TEND; DSMIF2: MDAT2; GPT16: GTIOC16B; IRQ: IRQ9; MTU37: MTIOC7B; PHOSTIF: HD5; SCI0: CTS0#; TRACE: TRACEDATA5" - None - - 
+      P21_7 B7 - - - - Disabled - - "BSC: D6; DMAC: DREQ; DSMIF3: MCLK3; GPT17: GTIOC17A; IRQ: IRQ10; MTU37: MTIOC7C; PHOSTIF: HD6; SCI0: DE0; TRACE: TRACEDATA6" - None - - 
+      P22_0 A7 - - - - Disabled - - "BSC: D7; DSMIF3: MDAT3; GPT17: GTIOC17B; IRQ: IRQ15; MTU37: MTIOC7D; PHOSTIF: HD7; SCI5: DE5; TRACE: TRACEDATA7" - None - - 
+      P22_1 A6 GPIO ETH_LED5 Low - "Output mode (Low & Not Into Input)" - - "BSC: D8; ETHER_ESC: ESC_LINKACT2; GPT_POEG: GTETRGB; MTU_POE3: POE4#; PHOSTIF: HD8; SCI4: CTS_RTS_SS4#; TRACE: TRACECTL" - IO - - 
+      P22_2 C6 - - - - Disabled - - "BSC: D9; DSMIF1: MCLK1; GPT_POEG: GTETRGSA; IRQ: IRQ4; MTU38: MTIOC8C; PHOSTIF: HD9; SPI1: SPI_SSL12; TRACE: TRACECLK" - None - - 
+      P22_3 B6 GPIO LED_ORANGE Low - "Output mode (Low & Not Into Input)" - - "BSC: D10; GPT_POEG: GTETRGSB; MTU38: MTIOC8D; PHOSTIF: HD10; SCI5: RXD_MISO5; SCI5: SCL5" - IO - - 
+      P23_7 D6 ETHER_ETH2_ETH2_RXD0 ETH2_RXD0 Low - "Peripheral mode" - - "BSC: BS#; BSC: D11; DSMIF4: MCLK4; ETHER_ETH2: ETH2_RXD0; GPT_POEG: GTETRGA; MTU30: MTIOC0A; PHOSTIF: HD11; SCI1: SCK1" - I - - 
+      P24_0 A5 ETHER_ETH2_ETH2_RXD1 ETH2_RXD1 Low - "Peripheral mode" - - "BSC: CKE; BSC: D12; DMAC: DREQ; DSMIF4: MDAT4; ETHER_ETH2: ETH2_RXD1; GPT_POEG: GTETRGB; MTU30: MTIOC0B; PHOSTIF: HD12; SCI1: RXD_MISO1; SCI1: SCL1" - I - - 
+      P24_1 B5 ETHER_ETH2_ETH2_RXCLK_REF_CLK_RXC ETH2_RXCLK Low - "Peripheral mode" - - "BSC: CAS#; BSC: D13; DSMIF5: MCLK5; ETHER_ETH2: ETH2_RXCLK_REF_CLK_RXC; GPT_POEG: GTETRGC; MTU30: MTIOC0C; MTU_POE3: POE8#; PHOSTIF: HD13" - I - - 
+      P24_2 C5 ETHER_ETH2_ETH2_RXD2 ETH2_RXD2 Low - "Peripheral mode" - - "BSC: D14; BSC: RAS#; DSMIF5: MDAT5; ETHER_ETH2: ETH2_RXD2; GPT_POEG: GTETRGD; MTU30: MTIOC0D; PHOSTIF: HD14; SCI1: SDA1; SCI1: TXD_MOSI1" - I - - 
+      RES# P6 SYSTEM_RES# - - - - - - - - I "Read only" - 
+      TRST# E2 SYSTEM_TRST# - - - - - - - - I "Read only" - 
+      USB_DM P13 SYSTEM_USB_DM - - - - - - - - IO "Read only" - 
+      USB_DP R13 SYSTEM_USB_DP - - - - - - - - IO "Read only" - 
+      USB_RREF P15 SYSTEM_USB_RREF - - - - - - - - I "Read only" - 
+      VCC1833_0 L6 SYSTEM_VCC1833_0 - - - - - - - - I "Read only" - 
+      VCC1833_1 K5 SYSTEM_VCC1833_1 - - - - - - - - I "Read only" - 
+      VCC1833_2 E5 SYSTEM_VCC1833_2 - - - - - - - - I "Read only" - 
+      VCC1833_3 J11 SYSTEM_VCC1833_3 - - - - - - - - I "Read only" - 
+      VCC1833_4 F11 SYSTEM_VCC1833_4 - - - - - - - - I "Read only" - 
+      VCC18_ADC0 E11 SYSTEM_VCC18_ADC0 - - - - - - - - I "Read only" - 
+      VCC18_ADC1 E9 SYSTEM_VCC18_ADC1 - - - - - - - - I "Read only" - 
+      VCC18_PLL0 P9 SYSTEM_VCC18_PLL0 - - - - - - - - I "Read only" - 
+      VCC18_PLL1 N9 SYSTEM_VCC18_PLL1 - - - - - - - - I "Read only" - 
+      VCC18_USB P11 SYSTEM_VCC18_USB - - - - - - - - I "Read only" - 
+      VCC33 E6 SYSTEM_VCC33 - - - - - - - - I "Read only" - 
+      VCC33 E8 SYSTEM_VCC33 - - - - - - - - I "Read only" - 
+      VCC33 M10 SYSTEM_VCC33 - - - - - - - - I "Read only" - 
+      VCC33 L5 SYSTEM_VCC33 - - - - - - - - I "Read only" - 
+      VCC33_USB R11 SYSTEM_VCC33_USB - - - - - - - - I "Read only" - 
+      VDD H10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD G10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD F6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD F8 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD F9 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD G6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD F10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD H6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD J6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD K6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD K7 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD K8 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD K10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD P7 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD J10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VREFH0 C11 SYSTEM_VREFH0 - - - - - - - - I "Read only" - 
+      VREFH1 C10 SYSTEM_VREFH1 - - - - - - - - I "Read only" - 
+      VSS A1 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS R1 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS A10 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS R5 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS A15 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS R9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS F7 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS G7 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS G8 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS G9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS N10 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS H7 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS N14 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS H8 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS H9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS E10 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS J7 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS J8 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS J9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS K9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS D10 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS D11 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS L1 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS L15 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS P8 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS R15 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS_ADC D12 SYSTEM_VSS_ADC - - - - - - - - I "Read only" - 
+      VSS_USB P12 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB P14 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB N13 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB N15 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB R12 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB R14 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      XTAL R8 CGC_XTAL - - - - - - - - O "Read only" - 
+    R9A07G084M04GBG.pincfg -> 
+      AN000 B13 SYSTEM_AN000 - - - - - - - - I "Read only" - 
+      AN001 C12 SYSTEM_AN001 - - - - - - - - I "Read only" - 
+      AN002 B14 SYSTEM_AN002 - - - - - - - - I "Read only" - 
+      AN003 C13 SYSTEM_AN003 - - - - - - - - I "Read only" - 
+      AN100 B12 SYSTEM_AN100 - - - - - - - - I "Read only" - 
+      AN101 A14 SYSTEM_AN101 - - - - - - - - I "Read only" - 
+      AN102 B11 SYSTEM_AN102 - - - - - - - - I "Read only" - 
+      AN103 A13 SYSTEM_AN103 - - - - - - - - I "Read only" - 
+      AN104 A12 SYSTEM_AN104 - - - - - - - - I "Read only" - 
+      AN105 B10 SYSTEM_AN105 - - - - - - - - I "Read only" - 
+      AN106 A11 SYSTEM_AN106 - - - - - - - - I "Read only" - 
+      AN107 C9 SYSTEM_AN107 - - - - - - - - I "Read only" - 
+      AVCC18_TSU C14 SYSTEM_AVCC18_TSU - - - - - - - - I "Read only" - 
+      AVCC18_USB P10 SYSTEM_AVCC18_USB - - - - - - - - I "Read only" - 
+      AVCC18_USB R10 SYSTEM_AVCC18_USB - - - - - - - - I "Read only" - 
+      BSCANP G2 SYSTEM_BSCANP - - - - - - - - I "Read only" - 
+      EXTAL R7 CGC_EXTAL - - - - - - - - I "Read only" - 
+      EXTCLKIN R6 CGC_EXTCLKIN - - - - - - - - I "Read only" - 
+      MDX P5 SYSTEM_MDX - - - - - - - - IO "Read only" - 
+      P00_0 C4 - ETH2_RXD3 Low - Disabled - - "BSC: D15; ETHER_ETH2: ETH2_RXD3; PHOSTIF: HD15; SCI2: DE2; SCI2: SCK2" - I - - 
+      P00_1 D5 - ETH2_RXDV Low - Disabled - - "BSC: A13; ETHER_ETH2: ETH2_RXDV_CRSDV_RXCTL; IRQ: IRQ0; MTU35: MTIC5U; SCI2: RXD_MISO2; SCI2: SCL2" - I - - 
+      P00_2 A3 - ETH2_TXEN Low - Disabled - - "BSC: RD#; ETHER_ETH2: ETH2_TXEN_TXCTL; MTU35: MTIC5V; SCI2: SDA2; SCI2: TXD_MOSI2; USB_HS: USB_OVRCUR" - O - - 
+      P00_3 B3 - ETH2_REFCLK Low - Disabled - - "BSC: RD_WR#; ETHER_ETH2: ETH2_REFCLK; ETHER_ETH2: ETH2_RMII2_REFCLK; IRQ: IRQ1; MTU35: MTIC5W; SCI2: CTS_RTS_SS2#" - O - - 
+      P00_4 A4 - - - - Disabled - - "BSC: WAIT#; DSMIF0: MCLK0; ETHER_ETH2: ETH2_RXER; GPT0: GTIOC0A; IRQ: IRQ13; MTU33: MTIOC3A; PHOSTIF: HWAIT#" - None - - 
+      P00_5 B4 - ETH2_LINK Low - Disabled - - "BSC: CS0#; DSMIF0: MDAT0; ETHER_ESC: ESC_PHYLINK0; ETHER_ESC: ESC_PHYLINK2; ETHER_ETHSW: ETHSW_PHYLINK0; ETHER_ETHSW: ETHSW_PHYLINK2; GPT0: GTIOC0B; MTU33: MTIOC3C" - I - - 
+      P00_6 C3 - ETH2_TXCLK Low - Disabled - - "BSC: CS5#; ETHER_ETH2: ETH2_TXCLK_TXC; GPT1: GTIOC1A; MTU33: MTIOC3B" - IO - - 
+      P00_7 D4 - - - - Disabled - - "BSC: RAS#; GPT2: GTIOC2A; IRQ: IRQ13; MTU34: MTIOC4A" - None - - 
+      P01_0 A2 - - - - Disabled - - "BSC: CAS#; DSMIF1: MCLK1; ETHER_ESC: ESC_MDIO; ETHER_ETHSW: ETHSW_MDIO; ETHER_GMAC: GMAC_MDIO; GPT3: GTIOC3A; MTU34: MTIOC4C; SCI2: CTS2#" - None - - 
+      P01_1 D3 - - - - Disabled - - "BSC: CKE; DSMIF1: MDAT1; ETHER_ESC: ESC_MDC; ETHER_ETHSW: ETHSW_MDC; ETHER_GMAC: GMAC_MDC; GPT1: GTIOC1B; MTU33: MTIOC3D; SCI2: DE2" - None - - 
+      P01_2 B2 - ETH2_TXD3 Low - Disabled - - "BSC: CS2#; ETHER_ETH2: ETH2_TXD3; GPT2: GTIOC2B; IRQ: IRQ2; MTU34: MTIOC4B" - O - - 
+      P01_3 C2 - ETH2_TXD2 Low - Disabled - - "BSC: AH#; ETHER_ETH2: ETH2_TXD2; GPT3: GTIOC3B; MTU34: MTIOC4D" - O - - 
+      P01_4 E4 - ETH2_TXD1 Low - Disabled - - "BSC: WE1#_DQMLU; ETHER_ETH2: ETH2_TXD1; IRQ: IRQ3; MTU_POE3: POE0#" - O - - 
+      P01_5 B1 - ETH2_TXD0 Low - Disabled - - "BSC: WE0#_DQMLL; ETHER_ETH2: ETH2_TXD0" - O - - 
+      P01_6 D2 - - - - Disabled - - "BSC: A20; CANFD1: CANTXDP1; ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG1; GPT9: GTIOC9A; MTU31: MTIOC1A; PHOSTIF: HA20; SCI1: CTS1#; TRACE: TRACEDATA0" - None - - 
+      P01_7 C1 - CAN_RX Low - Disabled - - "ADC0: ADTRG0#; BSC: A19; CANFD0: CANRX0; ETHER_ETHSW: ETHSW_LPI1; GPT9: GTIOC9B; MTU31: MTIOC1B; PHOSTIF: HA19; SCI1: SCK1; SPI3: SPI_RSPCK3; TRACE: TRACEDATA1" - I - - 
+      P02_0 E3 - - - - Disabled - - "BSC: A18; CANFD1: CANTX1; ETHER_ETHSW: ETHSW_LPI2; GPT: GTADSML0; IRQ: IRQ4; PHOSTIF: HA18; SCI1: RXD_MISO1; SCI1: SCL1; SPI3: SPI_MISO3; TRACE: TRACEDATA2; USB_HS: USB_OTGID" - None - - 
+      P02_1 D1 - - - - Disabled - - "BSC: A17; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; PHOSTIF: HA17; SCI1: DE1" - None - - 
+      P02_2 F3 - CAN_TX Low - Disabled - - "BSC: A16; CANFD0: CANTX0; ETHER_ETHSW: ETHSW_TDMAOUT0; GPT10: GTIOC10A; IRQ: IRQ14; MTU32: MTIOC2A; MTU_POE3: POE10#; PHOSTIF: HA16; RTC: RTCAT1HZ; SCI1: SDA1; SCI1: TXD_MOSI1; SPI3: SPI_MOSI3" - O - - 
+      P02_3 E1 - - - - Disabled - - "BSC: A15; BSC: AH#; CANFD1: CANRX1; ETHER_ETHSW: ETHSW_TDMAOUT1; GPT10: GTIOC10B; IRQ: IRQ15; MTU32: MTIOC2B; MTU_POE3: POE11#; PHOSTIF: HA15; SCI1: CTS_RTS_SS1#; SPI3: SPI_SSL30" - None - - 
+      P02_4 F4 JTAG/SWD_TDO TDO High - "Peripheral mode" - - "BSC: WE0#_DQMLL; JTAG/SWD: TDO; SCI1: DE1; SPI3: SPI_SSL33" - O - - 
+      P02_5 F2 JTAG/SWD_TDI TDI Low - "Peripheral mode" - - "BSC: WE1#_DQMLU; ETHER_ETHSW: ETHSW_TDMAOUT3; JTAG/SWD: TDI; SCI5: SCK5; SPI3: SPI_SSL31" - I - - 
+      P02_6 F5 JTAG/SWD_TMS_SWDIO TMS High - "Peripheral mode" - - "JTAG/SWD: TMS_SWDIO; SCI5: RXD_MISO5; SCI5: SCL5" - IO - - 
+      P02_7 F1 JTAG/SWD_TCK_SWCLK TCK Low - "Peripheral mode" - - "JTAG/SWD: TCK_SWCLK; SCI5: SDA5; SCI5: TXD_MOSI5" - I - - 
+      P03_0 G3 - ETH_LED4 Low - Disabled - - "BSC: A14; BSC: CS5#; CANFD1: CANTXDP1; GPT: GTADSML1; IRQ: IRQ14; PHOSTIF: HA14; SCI2: SCK2; SPI3: SPI_SSL32; TRACE: TRACEDATA3" - IO - - 
+      P03_5 G1 - - - - Disabled - - "BSC: A12; DSMIF2: MCLK2; ETHER_ETH2: ETH2_CRS; GPT4: GTIOC4A; IRQ: IRQ5; MTU33: MTIOC3A; PHOSTIF: HA12; SCI2: RXD_MISO2; SCI2: SCL2" - None - - 
+      P03_6 G4 - - - - Disabled - - "BSC: A11; DSMIF2: MDAT2; ETHER_ETH2: ETH2_COL; GPT4: GTIOC4B; IRQ: IRQ8; MTU33: MTIOC3B; PHOSTIF: HA11; SCI2: SDA2; SCI2: TXD_MOSI2; SPI1: SPI_SSL13; TRACE: TRACEDATA4" - None - - 
+      P03_7 G5 - - - - Disabled - - "BSC: A10; ETHER_ETH2: ETH2_TXER; GPT5: GTIOC5A; IRQ: IRQ9; MTU33: MTIOC3C; PHOSTIF: HA10; SCI3: SCK3; TRACE: TRACEDATA5" - None - - 
+      P04_0 H1 - - - - Disabled - - "BSC: A9; GPT5: GTIOC5B; MTU33: MTIOC3D; PHOSTIF: HA9; SCI3: RXD_MISO3; SCI3: SCL3; TRACE: TRACEDATA6" - None - - 
+      P04_1 H2 - LED_RED1 Low - Disabled - - "BSC: CKIO; IIC2: IIC_SDA2; PHOSTIF: HCKIO; SCI3: SDA3; SCI3: TXD_MOSI3; SPI0: SPI_MOSI0" - IO - - 
+      P04_4 H4 - ETH_LED6 Low - Disabled - - "BSC: A8; GPT: GTADSMP0; IRQ: IRQ10; MTU_POE3: POE10#; PHOSTIF: HA8; SCI3: CTS3#; SPI1: SPI_RSPCK1; TRACE: TRACEDATA7" - IO - - 
+      P04_5 H3 - - - - Disabled - - "BSC: A7; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT0; PHOSTIF: HA7; SCI3: DE3" - None - - 
+      P04_6 H5 - - - - Disabled - - "BSC: A6; DMAC: DACK; ETHER_ETH1: ETH1_TXER; PHOSTIF: HA6; RTC: RTCAT1HZ" - None - - 
+      P04_7 J1 - - - - Disabled - - "BSC: A5; ETHER_ETH0: ETH0_TXER; ETHER_ETH2: ETH2_TXER; PHOSTIF: HA5; SPI2: SPI_SSL21" - None - - 
+      P05_0 J5 - ETH_LED7 Low - Disabled - - "BSC: A4; CANFD0: CANTXDP0; CMTW0: CMTW0_TOC0; DSMIF3: MCLK3; ETHER_ETH1: ETH1_CRS; GPT6: GTIOC6A; IRQ: IRQ12; MTU34: MTIOC4A; PHOSTIF: HA4; SCI5: CTS_RTS_SS5#; USB_HS: USB_VBUSEN" - IO - - 
+      P05_1 J2 - - - - Disabled - - "BSC: A3; CANFD0: CANRXDP0; CMTW0: CMTW0_TIC1; DSMIF3: MDAT3; ETHER_ETH1: ETH1_COL; GPT6: GTIOC6B; IRQ: IRQ13; MTU34: MTIOC4B; PHOSTIF: HA3; SCI5: CTS5#; USB_HS: USB_EXICEN" - None - - 
+      P05_2 J4 - SCL Low - Disabled - - "BSC: A2; CANFD0: CANRX0; CMTW0: CMTW0_TOC0; DMAC: DREQ; ETHER_ETH0: ETH0_CRS; GPT7: GTIOC7A; GPT_POEG: GTETRGSA; IIC1: IIC_SCL1; IRQ: IRQ14; MTU34: MTIOC4C; PHOSTIF: HA2; SCI5: DE5; USB_HS: USB_VBUSEN" - IO - - 
+      P05_3 J3 - SDA Low - Disabled - - "BSC: A1; CANFD0: CANTX0; CMTW0: CMTW0_TIC0; ETHER_ETH0: ETH0_COL; GPT7: GTIOC7B; GPT_POEG: GTETRGSB; IIC1: IIC_SDA1; IRQ: IRQ15; MTU34: MTIOC4D; MTU_POE3: POE11#; PHOSTIF: HA1; SCI4: SCK4; USB_HS: USB_EXICEN" - IO - - 
+      P05_4 K1 - SW2 - - Disabled - - "BSC: A0; CANFD0: CANTXDP0; DMAC: DACK; ETHER_ETHSW: ETHSW_LPI0; GPT14: GTIOC14A; IRQ: IRQ12; PHOSTIF: HA0; SCI4: RXD_MISO4; SCI4: SCL4; SPI0: SPI_SSL00; USB_HS: USB_OVRCUR" - IO - - 
+      P05_5 K2 - ETH1_LINK Low - Disabled - - "CMTW0: CMTW0_TOC1; ETHER_ESC: ESC_PHYLINK1; ETHER_ETHSW: ETHSW_PHYLINK1; GPT14: GTIOC14B; SPI2: SPI_RSPCK2" - I - - 
+      P05_6 K3 - - - - Disabled - - "CMTW1: CMTW1_TIC0; ETHER_ETH1: ETH1_RXER; GPT15: GTIOC15A; IRQ: IRQ12; SPI2: SPI_SSL22" - None - - 
+      P05_7 M1 - ETH1_TXD2 Low - Disabled - - "CMTW1: CMTW1_TOC1; ETHER_ETH1: ETH1_TXD2; GPT15: GTIOC15B; SCI4: SDA4; SCI4: TXD_MOSI4; SPI2: SPI_SSL23" - O - - 
+      P06_0 L2 - ETH1_TXD3 Low - Disabled - - "CANFD1: CANRX1; CMTW1: CMTW1_TOC0; ETHER_ETH1: ETH1_TXD3; GPT16: GTIOC16A; SCI4: CTS_RTS_SS4#; SPI2: SPI_SSL23" - O - - 
+      P06_1 L3 - ETH1_REFCLK Low - Disabled - - "CANFD1: CANTX1; ETHER_ETH1: ETH1_REFCLK; ETHER_ETH1: ETH1_RMII1_REFCLK; GPT16: GTIOC16B; SCI4: CTS4#; SPI2: SPI_SSL22" - O - - 
+      P06_2 M2 - ETH1_TXD1 Low - Disabled - - "CANFD1: CANRXDP1; ETHER_ETH1: ETH1_TXD1; GPT17: GTIOC17A" - O - - 
+      P06_3 K4 - ETH1_TXD0 Low - Disabled - - "CANFD1: CANTXDP1; CMTW1: CMTW1_TIC1; ETHER_ETH1: ETH1_TXD0; GPT17: GTIOC17B; SCI4: DE4; SPI1: SPI_MISO1" - O - - 
+      P06_4 N1 - ETH1_TXCLK Low - Disabled - - "ETHER_ETH1: ETH1_TXCLK_TXC; GPT11: GTIOC11A; SPI1: SPI_MOSI1" - IO - - 
+      P06_5 N2 - ETH1_TXEN Low - Disabled - - "ETHER_ETH1: ETH1_TXEN_TXCTL; GPT11: GTIOC11B" - O - - 
+      P06_6 L4 - ETH1_RXD0 Low - Disabled - - "ETHER_ETH1: ETH1_RXD0; GPT12: GTIOC12A; SPI1: SPI_SSL10" - I - - 
+      P06_7 M3 - ETH1_RXD1 Low - Disabled - - "ETHER_ETH1: ETH1_RXD1; GPT12: GTIOC12B; SPI1: SPI_SSL11" - I - - 
+      P07_0 P1 - ETH1_RXD2 Low - Disabled - - "ETHER_ETH1: ETH1_RXD2; GPT13: GTIOC13A" - I - - 
+      P07_1 N3 - ETH1_RXD3 Low - Disabled - - "ETHER_ETH1: ETH1_RXD3; GPT13: GTIOC13B" - I - - 
+      P07_2 P2 - ETH1_RXDV Low - Disabled - - "ETHER_ETH1: ETH1_RXDV_CRSDV_RXCTL" - I - - 
+      P07_3 M4 - ETH1_RXCLK Low - Disabled - - "ETHER_ETH1: ETH1_RXCLK_REF_CLK_RXC" - I - - 
+      P07_4 R2 - USB_VBUSIN - - Disabled - - "ADC0: ADTRG0#; IRQ: IRQ1; USB_HS: USB_VBUSIN" - I - - 
+      P08_4 N4 - ETH0_RXD3 Low - Disabled - - "ETHER_ETH0: ETH0_RXD3; MTU36: MTIOC6A" - I - - 
+      P08_5 P3 - ETH0_RXDV Low - Disabled - - "ETHER_ETH0: ETH0_RXDV_CRSDV_RXCTL; MTU36: MTIOC6B" - I - - 
+      P08_6 M5 - ETH0_RXCLK Low - Disabled - - "ETHER_ETH0: ETH0_RXCLK_REF_CLK_RXC; MTU36: MTIOC6C" - I - - 
+      P08_7 N5 - ETH_MDC Low - Disabled - - "ETHER_ESC: ESC_MDC; ETHER_ETHSW: ETHSW_MDC; ETHER_GMAC: GMAC_MDC; MTU36: MTIOC6D" - O - - 
+      P09_0 P4 - ETH_MDIO Low - Disabled - - "ETHER_ESC: ESC_MDIO; ETHER_ETHSW: ETHSW_MDIO; ETHER_GMAC: GMAC_MDIO; MTU37: MTIOC7A" - IO - - 
+      P09_1 R3 - ETH0_REFCLK Low - Disabled - - "ETHER_ETH0: ETH0_REFCLK; ETHER_ETH0: ETH0_RMII0_REFCLK; MTU37: MTIOC7B" - O - - 
+      P09_2 N6 - - - - Disabled - - "ETHER_ETH0: ETH0_RXER; IRQ: IRQ0; MTU37: MTIOC7C" - None - - 
+      P09_3 R4 - ETH0_TXD3 Low - Disabled - - "ETHER_ETH0: ETH0_TXD3; MTU37: MTIOC7D" - O - - 
+      P09_4 M6 - ETH0_TXD2 Low - Disabled - - "ETHER_ETH0: ETH0_TXD2" - O - - 
+      P09_5 N7 - ETH0_TXD1 Low - Disabled - - "ETHER_ETH0: ETH0_TXD1" - O - - 
+      P09_6 M7 - ETH0_TXD0 Low - Disabled - - "ETHER_ETH0: ETH0_TXD0" - O - - 
+      P09_7 L7 - ETH0_TXCLK Low - Disabled - - "ETHER_ETH0: ETH0_TXCLK_TXC" - IO - - 
+      P10_0 N8 - ETH0_TXEN Low - Disabled - - "ETHER_ETH0: ETH0_TXEN_TXCTL" - O - - 
+      P10_1 M8 - ETH0_RXD0 Low - Disabled - - "ETHER_ETH0: ETH0_RXD0" - I - - 
+      P10_2 L8 - ETH0_RXD1 Low - Disabled - - "ETHER_ETH0: ETH0_RXD1" - I - - 
+      P10_3 L9 - ETH0_RXD2 Low - Disabled - - "ETHER_ETH0: ETH0_RXD2; RTC: RTCAT1HZ" - I - - 
+      P10_4 M9 - ETH0_LINK Low - Disabled - - "ETHER_ESC: ESC_PHYLINK0; ETHER_ETHSW: ETHSW_PHYLINK0; IRQ: IRQ11" - I - - 
+      P12_4 N11 - - - - Disabled - - "BSC: D15; ETHER_ETH1: ETH1_CRS; GPT8: GTIOC8B; MBXSEM: MBX_HINT#; MTU38: MTIOC8B; SPI0: SPI_SSL01; TRACE: TRACEDATA0" - None - - 
+      P13_2 L10 - EEPROM_SCL Low - Disabled - - "BSC: A13; BSC: D9; DSMIF4: MCLK4; ETHER_ESC: ESC_I2CCLK; ETHER_ETHSW: ETHSW_PTPOUT2; GPT10: GTIOC10A; IIC0: IIC_SCL0; IRQ: IRQ5; MTU30: MTIOC0A; MTU_POE3: POE8#; SCI1: CTS_RTS_SS1#; SPI0: SPI_MISO0; TRACE: TRACEDATA6" - IO - - 
+      P13_3 N12 - EEPROM_SDA Low - Disabled - - "BSC: D8; BSC: RD#; CMTW1: CMTW1_TOC0; DSMIF4: MDAT4; ETHER_ESC: ESC_I2CDATA; ETHER_ETHSW: ETHSW_PTPOUT3; GPT10: GTIOC10B; IIC0: IIC_SDA0; MTU30: MTIOC0B; MTU30: MTIOC0C; SCI1: CTS1#; SPI0: SPI_RSPCK0; TRACE: TRACEDATA7" - IO - - 
+      P13_4 L12 - ESC_RESETOUT Low - Disabled - - "BSC: A0; ETHER_ESC: ESC_RESETOUT#; GPT8: GTIOC8B; MTU30: MTIOC0D" - IO - - 
+      P13_5 M12 - SW3_Pin2 - - Disabled - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG0; IIC2: IIC_SCL2; MTU3: MTCLKA; SPI1: SPI_RSPCK1; XSPI0: XSPI0_WP1#" - IO - - 
+      P13_6 M13 - SW3_Pin1 - - Disabled - - "ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT0; MTU3: MTCLKB; XSPI0: XSPI0_WP0#" - IO - - 
+      P13_7 M11 - SW3_Pin4 - - Disabled - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG1; MBXSEM: MBX_HINT#; MTU3: MTCLKC; XSPI0: XSPI0_ECS1#" - IO - - 
+      P14_0 L13 - SW3_Pin3 Low - Disabled - - "ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; MTU3: MTCLKD; XSPI0: XSPI0_INT0#" - IO - - 
+      P14_1 L14 - - Low - Disabled - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_ETH1: ETH1_COL; ETHER_GMAC: GMAC_PTPTRG1; GPT8: GTIOC8A; MTU38: MTIOC8A; SHOSTIF: HSPI_IO0; XSPI0: XSPI0_INT1#" - IO - - 
+      P14_2 K12 - XSPI0_ECS Low - Disabled - - "ETHER_ETH0: ETH0_CRS; ETHER_ETH2: ETH2_CRS; GPT8: GTIOC8B; IRQ: IRQ6; MTU38: MTIOC8B; SHOSTIF: HSPI_CK; XSPI0: XSPI0_ECS0#" - I - - 
+      P14_3 M14 - - Low - Disabled - - "ETHER_ETH0: ETH0_COL; ETHER_ETH2: ETH2_COL; MTU30: MTIOC0A; SHOSTIF: HSPI_IO1; XSPI0: XSPI0_RSTO1#" - IO - - 
+      P14_4 J13 - XSPI0_DS Low - Disabled - - "BSC: BS#; ETHER_ESC: ESC_IRQ; MTU30: MTIOC0B; PHOSTIF: HBS#; XSPI0: XSPI0_DS" - IO - - 
+      P14_5 J12 - XSPI0_CKN Low - Disabled - - "BSC: CS3#; MTU_POE3: POE8#; SHOSTIF: HSPI_INT#; XSPI0: XSPI0_CKN" - O - - 
+      P14_6 K13 - XSPI0_CKP Low - Disabled - - "BSC: A21; XSPI0: XSPI0_CKP" - O - - 
+      P14_7 M15 - XSPI0_IO0 Low - Disabled - - "BSC: A22; BSC: BS#; SCI5: SCK5; SPI1: SPI_MISO1; XSPI0: XSPI0_IO0" - IO - - 
+      P15_0 L11 - XSPI0_IO1 Low - Disabled - - "BSC: A23; BSC: CKE; SCI5: RXD_MISO5; SCI5: SCL5; SPI1: SPI_MOSI1; XSPI0: XSPI0_IO1" - IO - - 
+      P15_1 K14 - XSPI0_IO2 Low - Disabled - - "BSC: A24; BSC: CAS#; MTU30: MTIOC0C; SCI5: SDA5; SCI5: TXD_MOSI5; SPI1: SPI_SSL10; XSPI0: XSPI0_IO2" - IO - - 
+      P15_2 K15 - XSPI0_IO3 Low - Disabled - - "BSC: A25; BSC: RAS#; MTU30: MTIOC0D; SCI5: CTS_RTS_SS5#; SPI1: SPI_SSL11; XSPI0: XSPI0_IO3" - IO - - 
+      P15_3 K11 - XSPI0_IO4 Low - Disabled - - "BSC: D11; DSMIF1: MCLK1; MTU38: MTIOC8C; XSPI0: XSPI0_IO4" - IO - - 
+      P15_4 H13 - XSPI0_IO5 Low - Disabled - - "BSC: D12; DSMIF1: MDAT1; MTU38: MTIOC8D; XSPI0: XSPI0_IO5" - IO - - 
+      P15_5 J14 - XSPI0_IO6 Low - Disabled - - "BSC: D13; DSMIF2: MCLK2; XSPI0: XSPI0_IO6" - IO - - 
+      P15_6 H12 - XSPI0_IO7 Low - Disabled - - "BSC: D14; DSMIF2: MDAT2; SPI1: SPI_SSL12; XSPI0: XSPI0_IO7" - IO - - 
+      P15_7 J15 - OSPI_CS Low - Disabled - - "DMAC: TEND; SCI5: CTS5#; SPI1: SPI_SSL13; XSPI0: XSPI0_CS0#" - O - - 
+      P16_0 G13 - ORAM_CS0 Low - Disabled - - "DSMIF3: MCLK3; ETHER_ETH0: ETH0_TXER; ETHER_ETH2: ETH2_REFCLK; SCI0: SDA0; SCI0: TXD_MOSI0; SHOSTIF: HSPI_CS#; SPI3: SPI_MOSI3; XSPI0: XSPI0_CS1#" - O - - 
+      P16_1 H11 - XSPI0_RESET0 Low - Disabled - - "ADC0: ADTRG0#; BSC: CS2#; CMTW0: CMTW0_TOC1; DSMIF3: MDAT3; PHOSTIF: HCS1#; SCI0: RXD_MISO0; SCI0: SCL0; SPI3: SPI_MISO3; XSPI0: XSPI0_RESET0#" - O - - 
+      P16_2 H14 - - - - Disabled - - "IRQ: NMI; PHOSTIF: HERROUT#; SCI0: CTS0#; SHOSTIF: HSPI_IO2; SPI3: SPI_RSPCK3; USB_HS: USB_EXICEN; XSPI0: XSPI0_RESET1#" - None - - 
+      P16_3 G12 - SW1 - - Disabled - - "BSC: CS3#; ETHER_ETH1: ETH1_CRS; ETHER_ETH1: ETH1_TXER; GPT: GTADSMP1; IRQ: IRQ7; SCI0: SCK0; SHOSTIF: HSPI_IO3; SPI3: SPI_SSL30; XSPI0: XSPI0_RSTO0#" - IO - - 
+      P16_5 H15 - UART_USB_TX Low - Disabled - - "BSC: A15; MTU35: MTIC5U; SCI0: SDA0; SCI0: TXD_MOSI0; SHOSTIF: HSPI_IO4" - IO - - 
+      P16_6 G11 - UART_USB_RX Low - Disabled - - "BSC: CS0#; IRQ: IRQ8; MTU35: MTIC5V; PHOSTIF: HCS0#; SCI0: RXD_MISO0; SCI0: SCL0; SHOSTIF: HSPI_IO5" - IO - - 
+      P16_7 G14 - - - - Disabled - - "BSC: A13; MTU35: MTIC5W; PHOSTIF: HA13; SCI0: SCK0; XSPI1: XSPI1_IO0" - None - - 
+      P17_0 F12 - - - - Disabled - - "ETHER_ESC: ESC_IRQ; SCI0: CTS_RTS_SS0#; XSPI1: XSPI1_IO1" - None - - 
+      P17_3 F14 - LED_RED2 Low - Disabled - - "ADC1: ADTRG1#; DMAC: DREQ; GPT_POEG: GTETRGA; MTU_POE3: POE0#; SPI3: SPI_SSL31; TRACE: TRACECTL; XSPI1: XSPI1_IO2" - IO - - 
+      P17_4 F13 - - - - Disabled - - "DMAC: DACK; GPT0: GTIOC0A; GPT_POEG: GTETRGB; MTU33: MTIOC3C; SCI3: CTS3#; SPI3: SPI_SSL32; TRACE: TRACECLK; XSPI1: XSPI1_IO3" - None - - 
+      P17_5 F15 - USB_OVRCUR Low - Disabled - - "DMAC: TEND; GPT0: GTIOC0B; GPT_POEG: GTETRGC; MTU33: MTIOC3A; USB_HS: USB_OVRCUR" - I - - 
+      P17_6 G15 - - - - Disabled - - "BSC: RD_WR#; GPT1: GTIOC1A; MTU33: MTIOC3B; PHOSTIF: HWRSTB#; SCI3: SCK3; XSPI1: XSPI1_DS" - None - - 
+      P17_7 E15 - SCI_RXD Low - Disabled - - "BSC: RD#; DMAC: DACK; GPT2: GTIOC2A; GPT3: GTIOC3A; MTU34: MTIOC4A; MTU34: MTIOC4C; PHOSTIF: HRD#; SCI3: RXD_MISO3; SCI3: SCL3; XSPI1: XSPI1_CKP" - IO - - 
+      P18_0 E14 - SCI_TXD Low - Disabled - - "BSC: WE0#_DQMLL; GPT2: GTIOC2A; GPT3: GTIOC3A; MTU34: MTIOC4A; MTU34: MTIOC4C; PHOSTIF: HWR0#; SCI3: SDA3; SCI3: TXD_MOSI3; SHOSTIF: HSPI_IO6" - IO - - 
+      P18_1 D15 - - - - Disabled - - "ADC1: ADTRG1#; BSC: WE1#_DQMLU; GPT1: GTIOC1B; IRQ: IRQ10; MTU33: MTIOC3D; PHOSTIF: HWR1#; SCI3: CTS_RTS_SS3#; SHOSTIF: HSPI_IO7" - None - - 
+      P18_2 D14 - LED_GREEN Low - Disabled - - "BSC: BS#; ETHER_ETH1: ETH1_COL; GPT2: GTIOC2B; GPT3: GTIOC3B; IIC2: IIC_SDA2; MTU34: MTIOC4B; MTU34: MTIOC4D; SCI0: SCK0; XSPI1: XSPI1_CS0#" - IO - - 
+      P18_3 E13 - - - - Disabled - - "BSC: CKE; CANFD1: CANRXDP1; CMTW1: CMTW1_TIC1; ETHER_ETH2: ETH2_CRS; GPT2: GTIOC2B; GPT3: GTIOC3B; IRQ: IRQ0; MTU34: MTIOC4B; MTU34: MTIOC4D; XSPI1: XSPI1_IO4" - None - - 
+      P18_4 E12 - SCK Low - Disabled - - "BSC: CAS#; CANFD0: CANTX0; ETHER_ETH1: ETH1_CRS; IRQ: IRQ1; MTU35: MTIC5U; SCI4: SDA4; SCI4: TXD_MOSI4; SPI2: SPI_RSPCK2; XSPI1: XSPI1_IO5" - IO - - 
+      P18_5 D13 - MOSI Low - Disabled - - "BSC: RAS#; CANFD0: CANRX0; ETHER_ETH2: ETH2_COL; MTU35: MTIC5V; SCI4: RXD_MISO4; SCI4: SCL4; SPI2: SPI_MOSI2; TRACE: TRACECTL; XSPI1: XSPI1_IO6" - IO - - 
+      P18_6 C15 - MISO Low - Disabled - - "ADC0: ADTRG0#; ETHER_ETH1: ETH1_COL; IIC2: IIC_SCL2; IRQ: IRQ11; MTU35: MTIC5W; SCI4: DE4; SCI4: SCK4; SPI2: SPI_MISO2; TRACE: TRACECLK; XSPI1: XSPI1_IO7" - IO - - 
+      P19_0 B15 - USB_VBUSEN Low - Disabled - - "USB_HS: USB_VBUSEN" - O - - 
+      P20_1 B9 - ETH_LED2_MDV0 Low - Disabled - - "ETHER_ESC: ESC_LINKACT0; ETHER_ETHSW: ETHSW_PTPOUT3; ETHER_ETHSW: ETHSW_TDMAOUT0" - IO - - 
+      P20_2 D8 - ETH_LED0_MDV1 Low - Disabled - - "ETHER_ESC: ESC_LEDRUN; ETHER_ESC: ESC_LEDSTER; ETHER_ETHSW: ETHSW_PTPOUT2; ETHER_ETHSW: ETHSW_TDMAOUT1; SCI3: DE3" - IO - - 
+      P20_3 D9 - ETH_LED1_MDV2 Low - Disabled - - "ETHER_ESC: ESC_LEDERR; ETHER_ETHSW: ETHSW_PTPOUT1; ETHER_ETHSW: ETHSW_TDMAOUT2" - IO - - 
+      P20_4 A9 - ETH_LED3_MDV3 Low - Disabled - - "ETHER_ESC: ESC_LINKACT1; ETHER_ETHSW: ETHSW_PTPOUT0; ETHER_ETHSW: ETHSW_TDMAOUT3" - IO - - 
+      P21_1 B8 - CS Low - Disabled - - "BSC: D0; CMTW0: CMTW0_TIC0; DSMIF0: MCLK0; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; GPT14: GTIOC14A; IIC1: IIC_SCL1; MTU36: MTIOC6A; PHOSTIF: HD0; SCI5: SCK5; SHOSTIF: HSPI_INT#; SPI2: SPI_SSL20; TRACE: TRACEDATA0" - IO - - 
+      P21_2 C8 - - - - Disabled - - "BSC: D1; CMTW0: CMTW0_TIC1; DSMIF0: MDAT0; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; GPT14: GTIOC14B; IIC1: IIC_SDA1; MTU36: MTIOC6B; PHOSTIF: HD1; SCI5: RXD_MISO5; SCI5: SCL5; SPI2: SPI_MISO2; TRACE: TRACEDATA1" - None - - 
+      P21_3 A8 - - - - Disabled - - "BSC: D2; DSMIF1: MCLK1; GPT15: GTIOC15A; IRQ: NMI; MTU36: MTIOC6C; PHOSTIF: HD2; SCI5: SDA5; SCI5: TXD_MOSI5; SPI3: SPI_SSL33; TRACE: TRACEDATA2" - None - - 
+      P21_4 E7 - - - - Disabled - - "BSC: D3; DSMIF1: MDAT1; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; GPT15: GTIOC15B; MBXSEM: MBX_HINT#; MTU36: MTIOC6D; PHOSTIF: HD3; SCI5: CTS_RTS_SS5#; SPI0: SPI_SSL02; TRACE: TRACEDATA3" - None - - 
+      P21_5 C7 - - - - Disabled - - "ADC1: ADTRG1#; BSC: D4; CMTW1: CMTW1_TOC1; DSMIF2: MCLK2; GPT16: GTIOC16A; IRQ: IRQ6; MTU37: MTIOC7A; PHOSTIF: HD4; SCI5: CTS5#; SPI0: SPI_MISO0; TRACE: TRACEDATA4" - None - - 
+      P21_6 D7 - - - - Disabled - - "BSC: D5; DMAC: TEND; DSMIF2: MDAT2; GPT16: GTIOC16B; IRQ: IRQ9; MTU37: MTIOC7B; PHOSTIF: HD5; SCI0: CTS0#; TRACE: TRACEDATA5" - None - - 
+      P21_7 B7 - - - - Disabled - - "BSC: D6; DMAC: DREQ; DSMIF3: MCLK3; GPT17: GTIOC17A; IRQ: IRQ10; MTU37: MTIOC7C; PHOSTIF: HD6; SCI0: DE0; TRACE: TRACEDATA6" - None - - 
+      P22_0 A7 - - - - Disabled - - "BSC: D7; DSMIF3: MDAT3; GPT17: GTIOC17B; IRQ: IRQ15; MTU37: MTIOC7D; PHOSTIF: HD7; SCI5: DE5; TRACE: TRACEDATA7" - None - - 
+      P22_1 A6 - ETH_LED5 Low - Disabled - - "BSC: D8; ETHER_ESC: ESC_LINKACT2; GPT_POEG: GTETRGB; MTU_POE3: POE4#; PHOSTIF: HD8; SCI4: CTS_RTS_SS4#; TRACE: TRACECTL" - IO - - 
+      P22_2 C6 - - - - Disabled - - "BSC: D9; DSMIF1: MCLK1; GPT_POEG: GTETRGSA; IRQ: IRQ4; MTU38: MTIOC8C; PHOSTIF: HD9; SPI1: SPI_SSL12; TRACE: TRACECLK" - None - - 
+      P22_3 B6 - LED_ORANGE Low - Disabled - - "BSC: D10; GPT_POEG: GTETRGSB; MTU38: MTIOC8D; PHOSTIF: HD10; SCI5: RXD_MISO5; SCI5: SCL5" - IO - - 
+      P23_7 D6 - ETH2_RXD0 Low - Disabled - - "BSC: BS#; BSC: D11; DSMIF4: MCLK4; ETHER_ETH2: ETH2_RXD0; GPT_POEG: GTETRGA; MTU30: MTIOC0A; PHOSTIF: HD11; SCI1: SCK1" - I - - 
+      P24_0 A5 - ETH2_RXD1 Low - Disabled - - "BSC: CKE; BSC: D12; DMAC: DREQ; DSMIF4: MDAT4; ETHER_ETH2: ETH2_RXD1; GPT_POEG: GTETRGB; MTU30: MTIOC0B; PHOSTIF: HD12; SCI1: RXD_MISO1; SCI1: SCL1" - I - - 
+      P24_1 B5 - ETH2_RXCLK Low - Disabled - - "BSC: CAS#; BSC: D13; DSMIF5: MCLK5; ETHER_ETH2: ETH2_RXCLK_REF_CLK_RXC; GPT_POEG: GTETRGC; MTU30: MTIOC0C; MTU_POE3: POE8#; PHOSTIF: HD13" - I - - 
+      P24_2 C5 - ETH2_RXD2 Low - Disabled - - "BSC: D14; BSC: RAS#; DSMIF5: MDAT5; ETHER_ETH2: ETH2_RXD2; GPT_POEG: GTETRGD; MTU30: MTIOC0D; PHOSTIF: HD14; SCI1: SDA1; SCI1: TXD_MOSI1" - I - - 
+      RES# P6 SYSTEM_RES# - - - - - - - - I "Read only" - 
+      TRST# E2 SYSTEM_TRST# - - - - - - - - I "Read only" - 
+      USB_DM P13 SYSTEM_USB_DM - - - - - - - - IO "Read only" - 
+      USB_DP R13 SYSTEM_USB_DP - - - - - - - - IO "Read only" - 
+      USB_RREF P15 SYSTEM_USB_RREF - - - - - - - - I "Read only" - 
+      VCC1833_0 L6 SYSTEM_VCC1833_0 - - - - - - - - I "Read only" - 
+      VCC1833_1 K5 SYSTEM_VCC1833_1 - - - - - - - - I "Read only" - 
+      VCC1833_2 E5 SYSTEM_VCC1833_2 - - - - - - - - I "Read only" - 
+      VCC1833_3 J11 SYSTEM_VCC1833_3 - - - - - - - - I "Read only" - 
+      VCC1833_4 F11 SYSTEM_VCC1833_4 - - - - - - - - I "Read only" - 
+      VCC18_ADC0 E11 SYSTEM_VCC18_ADC0 - - - - - - - - I "Read only" - 
+      VCC18_ADC1 E9 SYSTEM_VCC18_ADC1 - - - - - - - - I "Read only" - 
+      VCC18_PLL0 P9 SYSTEM_VCC18_PLL0 - - - - - - - - I "Read only" - 
+      VCC18_PLL1 N9 SYSTEM_VCC18_PLL1 - - - - - - - - I "Read only" - 
+      VCC18_USB P11 SYSTEM_VCC18_USB - - - - - - - - I "Read only" - 
+      VCC33 E6 SYSTEM_VCC33 - - - - - - - - I "Read only" - 
+      VCC33 E8 SYSTEM_VCC33 - - - - - - - - I "Read only" - 
+      VCC33 M10 SYSTEM_VCC33 - - - - - - - - I "Read only" - 
+      VCC33 L5 SYSTEM_VCC33 - - - - - - - - I "Read only" - 
+      VCC33_USB R11 SYSTEM_VCC33_USB - - - - - - - - I "Read only" - 
+      VDD H10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD G10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD F6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD F8 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD F9 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD G6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD F10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD H6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD J6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD K6 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD K7 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD K8 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD K10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD P7 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VDD J10 SYSTEM_VDD - - - - - - - - I "Read only" - 
+      VREFH0 C11 SYSTEM_VREFH0 - - - - - - - - I "Read only" - 
+      VREFH1 C10 SYSTEM_VREFH1 - - - - - - - - I "Read only" - 
+      VSS A1 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS R1 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS A10 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS R5 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS A15 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS R9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS F7 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS G7 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS G8 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS G9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS N10 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS H7 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS N14 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS H8 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS H9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS E10 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS J7 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS J8 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS J9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS K9 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS D10 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS D11 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS L1 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS L15 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS P8 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS R15 SYSTEM_VSS - - - - - - - - I "Read only" - 
+      VSS_ADC D12 SYSTEM_VSS_ADC - - - - - - - - I "Read only" - 
+      VSS_USB P12 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB P14 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB N13 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB N15 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB R12 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      VSS_USB R14 SYSTEM_VSS_USB - - - - - - - - I "Read only" - 
+      XTAL R8 CGC_XTAL - - - - - - - - O "Read only" - 
+    
+  User Events
+    
+  User Event Links
+    
+  Module "I/O Port (r_ioport)"
+    Parameter Checking: Default (BSP)
+    
+  Module "Memory config check"
+    MPU/MMU Type: MPU
+    
+  Module "UART (r_sci_uart)"
+    Parameter Checking: Default (BSP)
+    FIFO Support: Enable
+    DMAC Support: Disable
+    Flow Control Support: Disable
+    Multiplex Interrupt: Disabled
+    
+  Module "Ethernet (r_gmac)"
+    Parameter Checking: Default (BSP)
+    
+  Module "Ethernet (r_ether_phy)"
+    Parameter Checking: Default (BSP)
+    VSC8541 Target: Disabled
+    KSZ9131 Target: Disabled
+    KSZ9031 Target: Disabled
+    KSZ8081 Target: Disabled
+    KSZ8041 Target: Disabled
+    User Own Target: Enabled
+    
+  Module "Ethernet (r_ether_selector)"
+    Parameter Checking: Default (BSP)
+    Ethernet Mode: Ethernet Switch + Ethernet Switch + Ethernet Switch
+    
+  Module "Ethernet (r_ethsw)"
+    Parameter Checking: Default (BSP)
+    
+  Module "Timer, General PWM (r_gpt)"
+    Parameter Checking: Default (BSP)
+    Pin Output Support: Disabled
+    Write Protect Enable: Disabled
+    Multiplex Interrupt: Disabled
+    
+  Module "Timer , Multi-Function Timer Pulse Unit 3 (r_mtu3)"
+    Parameter Checking: Default (BSP)
+    Pin Output Support: Disabled
+    UVW Support: Disabled
+    Multiplex Interrupt: Disabled
+    
+  HAL
+    Instance "g_ioport I/O Port (r_ioport)"
+      General: Name: g_ioport
+      ELC Output Port Group 1: Trigger Source: Disabled
+      ELC Output Port Group 1: Port Selection: 
+      ELC Output Port Group 1: Output Operation: Low output
+      ELC Output Port Group 2: Trigger Source: Disabled
+      ELC Output Port Group 2: Port Selection: 
+      ELC Output Port Group 2: Output Operation: Low output
+      ELC Input Port Group 1: Trigger Source: Disabled
+      ELC Input Port Group 1: Event Link Control: Disabled
+      ELC Input Port Group 1: Port Selection: 
+      ELC Input Port Group 1: Edge Detection: Rising edge
+      ELC Input Port Group 1: Buffer Overwrite: Disabled
+      ELC Input Port Group 1: Buffer Initial Value: PIN0: Low Input (P16_0)
+      ELC Input Port Group 1: Buffer Initial Value: PIN1: Low Input (P16_1)
+      ELC Input Port Group 1: Buffer Initial Value: PIN2: Low Input (P16_2)
+      ELC Input Port Group 1: Buffer Initial Value: PIN3: Low Input (P16_3)
+      ELC Input Port Group 1: Buffer Initial Value: PIN4: Low Input (P16_4)
+      ELC Input Port Group 1: Buffer Initial Value: PIN5: Low Input (P16_5)
+      ELC Input Port Group 1: Buffer Initial Value: PIN6: Low Input (P16_6)
+      ELC Input Port Group 1: Buffer Initial Value: PIN7: Low Input (P16_7)
+      ELC Input Port Group 2: Trigger Source: Disabled
+      ELC Input Port Group 2: Event Link Control: Disabled
+      ELC Input Port Group 2: Port Selection: 
+      ELC Input Port Group 2: Edge Detection: Rising edge
+      ELC Input Port Group 2: Buffer Overwrite: Disabled
+      ELC Input Port Group 2: Buffer Initial Value: PIN0: Low Input (P18_0)
+      ELC Input Port Group 2: Buffer Initial Value: PIN1: Low Input (P18_1)
+      ELC Input Port Group 2: Buffer Initial Value: PIN2: Low Input (P18_2)
+      ELC Input Port Group 2: Buffer Initial Value: PIN3: Low Input (P18_3)
+      ELC Input Port Group 2: Buffer Initial Value: PIN4: Low Input (P18_4)
+      ELC Input Port Group 2: Buffer Initial Value: PIN5: Low Input (P18_5)
+      ELC Input Port Group 2: Buffer Initial Value: PIN6: Low Input (P18_6)
+      ELC Input Port Group 2: Buffer Initial Value: PIN7: Low Input (P18_7)
+      ELC Single Port 0: Common: Event Link Control: Disabled
+      ELC Single Port 0: Common: Event Direction: Output direction
+      ELC Single Port 0: Common: Port selection: P16_0
+      ELC Single Port 0: Output Direction Setting: Trigger Source: Disabled
+      ELC Single Port 0: Output Direction Setting: Output Operation: Low output
+      ELC Single Port 0: Input Direction Setting: Edge Detection: Rising edge
+      ELC Single Port 1: Common: Event Link Control: Disabled
+      ELC Single Port 1: Common: Event Direction: Output direction
+      ELC Single Port 1: Common: Port selection: P16_0
+      ELC Single Port 1: Output Direction Setting: Trigger Source: Disabled
+      ELC Single Port 1: Output Direction Setting: Output Operation: Low output
+      ELC Single Port 1: Input Direction Setting: Edge Detection: Rising edge
+      ELC Single Port 2: Common: Event Link Control: Disabled
+      ELC Single Port 2: Common: Event Direction: Output direction
+      ELC Single Port 2: Common: Port selection: P16_0
+      ELC Single Port 2: Output Direction Setting: Trigger Source: Disabled
+      ELC Single Port 2: Output Direction Setting: Output Operation: Low output
+      ELC Single Port 2: Input Direction Setting: Edge Detection: Rising edge
+      ELC Single Port 3: Common: Event Link Control: Disabled
+      ELC Single Port 3: Common: Event Direction: Output direction
+      ELC Single Port 3: Common: Port selection: P16_0
+      ELC Single Port 3: Output Direction Setting: Trigger Source: Disabled
+      ELC Single Port 3: Output Direction Setting: Output Operation: Low output
+      ELC Single Port 3: Input Direction Setting: Edge Detection: Rising edge
+      
+    Instance "Memory config check"
+    Instance "g_uart0 UART (r_sci_uart)"
+      General: Name: g_uart0
+      General: Channel: 0
+      General: Data Bits: 8bits
+      General: Parity: None
+      General: Stop Bits: 1bit
+      Baud: Baud Rate: 115200
+      Baud: Baud Rate Modulation: Disabled
+      Baud: Max Error (%): 5
+      Baud: Synchronizer Bypass: Not Bypassed (The operation clock is SCInASYNCCLK)
+      Flow Control: CTS/RTS Selection: Hardware RTS
+      Flow Control: Software RTS Port: Disabled
+      Flow Control: Software RTS Pin: Disabled
+      Extra: Clock Source: Internal Clock
+      Extra: Start bit detection: Falling Edge
+      Extra: Noise Filter: Disable
+      Extra: Receive FIFO Trigger Level: Max
+      Extra: RS-485: DE Pin: Disable
+      Extra: RS-485: DE Pin Polarity: Active High
+      Extra: RS-485: DE Pin Assertion Time: 1
+      Extra: RS-485: DE Pin Negation Time: 1
+      Interrupts: Callback: user_uart0_callback
+      Interrupts: Receive Interrupt Priority: Priority 12
+      Interrupts: Transmit Data Empty Interrupt Priority: Priority 12
+      Interrupts: Transmit End Interrupt Priority: Priority 12
+      Interrupts: Error Interrupt Priority: Priority 12
+      
+    Instance "g_ether0 Ethernet (r_gmac)"
+      General: Name: g_ether0
+      General: Channel: 0
+      General: MAC address 0: 00:11:22:33:44:55
+      General: MAC address 1: NULL
+      General: MAC address 2: NULL
+      General: Zero-copy Mode: Enable
+      General: Flow control functionality: Disable
+      Filters: Promiscuous Mode: Enable
+      Buffers: Number of TX buffer: 8
+      Buffers: Number of RX buffer: 8
+      Buffers: Buffer size: 1524
+      Interrupts: SBD Interrupt priority: Priority 12
+      Interrupts: PMT Interrupt priority: Priority 12
+      Interrupts: Callback: user_ether0_callback
+      Link signal change: Disable
+      
+      Instance "g_ether_phy0 Ethernet (r_ether_phy)"
+        Name: g_ether_phy0
+        Channel: 0
+        PHY-LSI Address: 1
+        PHY-LSI Reset Completion Timeout: 0x00020000
+        Flow Control: Disable
+        Port Type: Ethernet
+        Phy LSI type: User own PHY
+        Port Custom Init Function: ether_phy_targets_initialize_rtl8211_rgmii
+        Select MDIO type: GMAC
+        Auto Negotiation: ON
+        Speed: 100M
+        Duplex: FULL
+        Reset Port: 13
+        Reset Pin: 4
+        Reset assert time: 15000
+        
+        Instance "g_ether_selector0 Ethernet (r_ether_selector)"
+          Name: g_ether_selector0
+          Port: 0
+          PHY Link Signal Polarity: Active-Low
+          Interface Type: RGMII
+          Converter Speed: 100Mbps
+          Converter Duplex: full duplex
+          Reference Clock: input
+          
+      Instance "g_ether_phy1 Ethernet (r_ether_phy)"
+        Name: g_ether_phy1
+        Channel: 1
+        PHY-LSI Address: 2
+        PHY-LSI Reset Completion Timeout: 0x00020000
+        Flow Control: Disable
+        Port Type: Ethernet
+        Phy LSI type: User own PHY
+        Port Custom Init Function: ether_phy_targets_initialize_rtl8211_rgmii
+        Select MDIO type: GMAC
+        Auto Negotiation: ON
+        Speed: 100M
+        Duplex: FULL
+        Reset Port: 13
+        Reset Pin: 4
+        Reset assert time: 15000
+        
+        Instance "g_ether_selector1 Ethernet (r_ether_selector)"
+          Name: g_ether_selector1
+          Port: 1
+          PHY Link Signal Polarity: Active-Low
+          Interface Type: RGMII
+          Converter Speed: 100Mbps
+          Converter Duplex: full duplex
+          Reference Clock: input
+          
+      Instance "g_ether_phy2 Ethernet (r_ether_phy)"
+        Name: g_ether_phy2
+        Channel: 2
+        PHY-LSI Address: 3
+        PHY-LSI Reset Completion Timeout: 0x00020000
+        Flow Control: Disable
+        Port Type: Ethernet
+        Phy LSI type: User own PHY
+        Port Custom Init Function: ether_phy_targets_initialize_rtl8211_rgmii
+        Select MDIO type: GMAC
+        Auto Negotiation: ON
+        Speed: 100M
+        Duplex: FULL
+        Reset Port: 13
+        Reset Pin: 4
+        Reset assert time: 15000
+        
+        Instance "g_ether_selector2 Ethernet (r_ether_selector)"
+          Name: g_ether_selector2
+          Port: 2
+          PHY Link Signal Polarity: Active-Low
+          Interface Type: RGMII
+          Converter Speed: 100Mbps
+          Converter Duplex: full duplex
+          Reference Clock: input
+          
+      Instance "g_ethsw0 Ethernet (r_ethsw)"
+        Name: g_ethsw0
+        Channel: 0
+        Management: Management port specific tag: Disabled
+        Management: Management port specific tag ID: 0xE001
+        Link signal change: Disable
+        Interrupts: Interrupt Priority: Priority 12
+        Interrupts: Callback: gmac_callback_ethsw
+        Interrupts: Context: &g_ether0_ctrl
+        
+    Instance "g_timer0 Timer, General PWM (r_gpt)"
+      General: Name: g_timer0
+      General: Unit: 0
+      General: Channel: 0
+      General: Mode: Periodic
+      General: Period: 0x100000000
+      General: Period Unit: Raw Counts
+      Output: Duty Cycle Percent (only applicable in PWM mode): 50
+      Output: GTIOCA Output Enabled: False
+      Output: GTIOCA Stop Level: Pin Level Low
+      Output: GTIOCB Output Enabled: False
+      Output: GTIOCB Stop Level: Pin Level Low
+      Input: Count Up Source: 
+      Input: Count Down Source: 
+      Input: Phase Count Setting Automatically Enable: Disabled
+      Input: Counting Mode: Mode1
+      Input: Start Source: 
+      Input: Stop Source: 
+      Input: Clear Source: 
+      Input: Capture A Source: 
+      Input: Capture B Source: 
+      Input: Noise Filter A Sampling Clock Select: No Filter
+      Input: Noise Filter B Sampling Clock Select: No Filter
+      Interrupts: Callback: timer0_esc_callback
+      Interrupts: Overflow/Crest Interrupt Priority: Priority 10
+      Interrupts: Capture A Interrupt Priority: Disabled
+      Interrupts: Capture B Interrupt Priority: Disabled
+      Interrupts: Trough Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): Callback: NULL
+      Interrupts (GPT_SEL): Overflow/Crest Interrupt Source: 
+      Interrupts (GPT_SEL): Capture A Interrupt Source: 
+      Interrupts (GPT_SEL): Capture B Interrupt Source: 
+      Interrupts (GPT_SEL): Trough Interrupt Source: 
+      Interrupts (GPT_SEL): Dead Time Error Interrupt Source: 
+      Interrupts (GPT_SEL): INT0 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT1 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT2 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT3 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT4 Interrupt Priority: Disabled
+      Extra Features: Extra Features: Disabled
+      Extra Features: Output Disable: POEG Link: POEG Channel 0
+      Extra Features: Output Disable: Output Disable POEG Trigger: 
+      Extra Features: ADC Trigger: Start Event Trigger: 
+      Extra Features: Dead Time: Dead Time Count Up (Raw Counts): 0
+      Extra Features: Dead Time: Dead Time Count Down (Raw Counts): 0
+      Extra Features: ADC Trigger: ADC A Compare Match (Raw Counts): 0
+      Extra Features: ADC Trigger: ADC B Compare Match (Raw Counts): 0
+      Extra Features: Interrupt Skipping: Interrupt to Count: None
+      Extra Features: Interrupt Skipping: Interrupt Skip Count: 0
+      Extra Features: Interrupt Skipping: Skip ADC Events: None
+      Extra Features: Output Disable: GTIOCA Disable Setting: Disable Prohibited
+      Extra Features: Output Disable: GTIOCB Disable Setting: Disable Prohibited
+      Extra Features: Extended Interrupt Skipping 1: Interrupt to Count: None
+      Extra Features: Extended Interrupt Skipping 1: Interrupt Skip Count: 0
+      Extra Features: Extended Interrupt Skipping 2: Interrupt to Count: None
+      Extra Features: Extended Interrupt Skipping 2: Interrupt Skip Count: 0
+      Extra Features: Input Capture Interrupt Extended Skipping Function: Overflow Interrupt: None
+      Extra Features: Input Capture Interrupt Extended Skipping Function: Underflow Interrupt: None
+      Extra Features: Input Capture Interrupt Extended Skipping Function: GTADTRA A/D Converter Start Request: None
+      Extra Features: Input Capture Interrupt Extended Skipping Function: GTADTRB A/D Converter Start Request: None
+      Interrupts: Dead Time Error Interrupt Priority: Disabled
+      Extra Features: Input Capture at Count Stop: Enabled
+      Extra Features: Input Capture Signal: Not Supported
+      ELC: LLPP GPT event A: Trigger Source: Disabled
+      ELC: LLPP GPT event B: Trigger Source: Disabled
+      ELC: LLPP GPT event C: Trigger Source: Disabled
+      ELC: LLPP GPT event D: Trigger Source: Disabled
+      ELC: LLPP GPT event E: Trigger Source: Disabled
+      ELC: LLPP GPT event F: Trigger Source: Disabled
+      ELC: LLPP GPT event G: Trigger Source: Disabled
+      ELC: LLPP GPT event H: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event A: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event B: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event C: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event D: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event E: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event F: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event G: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event H: Trigger Source: Disabled
+      
+    Instance "g_mtu3 Timer , Multi-Function Timer Pulse Unit 3 (r_mtu3)"
+      General: Name: g_mtu3
+      General: Channel: 0
+      General: Mode: Periodic
+      General: TGRA(Output Compare or Input Capture Value): 0xFFFF
+      General: TGRB(Output Compare or Input Capture Value): 0xFFFF
+      General: Time Prescaler: PCLKH divided by 1  (common ch)
+      General: Clock Edge: Rising
+      General: Counter Clear Source: Disabled
+      Input: Phase Count: Bit Mode: 16-bit
+      Input: Phase Count: Counting Mode: None
+      Input: Phase Count: Clock Pin Select: MTCLKA, MTCLKB
+      Noise Filter: External Clock: Enable: 
+      Noise Filter: External Clock: Clock Select: PCLK divided by 1
+      Noise Filter: Input Capture: Enable: 
+      Noise Filter: Input Capture: Clock Select: PCLK divided by 1
+      Output: Initial Output A: No Output
+      Output: Initial Output B: No Output
+      Interrupts: Callback: g_mtu3_callback
+      Interrupts: Overflow/Crest Interrupt Priority: Priority 8
+      Interrupts: Capture A Interrupt Priority: Disabled
+      Interrupts: Capture B Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): Callback: NULL
+      Interrupts (GPT_SEL): Overflow/Crest Interrupt Source: 
+      Interrupts (GPT_SEL): Capture A Interrupt Source: 
+      Interrupts (GPT_SEL): Capture B Interrupt Source: 
+      Interrupts (GPT_SEL): INT0 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT1 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT2 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT3 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT4 Interrupt Priority: Disabled
+      Extra Features: Extra Features: Disabled
+      Extra Features: MTU5: U Count: 0x0000
+      Extra Features: MTU5: V Count: 0x0000
+      Extra Features: MTU5: W Count: 0x0000
+      Extra Features: MTU5: U Clock Select: PCLKH divided by 1
+      Extra Features: MTU5: V Clock Select: PCLKH divided by 1
+      Extra Features: MTU5: W Clock Select: PCLKH divided by 1
+      Extra Features: MTU5: U Input Capture: No func
+      Extra Features: MTU5: V Input Capture: No func
+      Extra Features: MTU5: W Input Capture: No func
+      Extra Features: MTU5: Interrupts: Capture U Interrupt Priority: Disabled
+      Extra Features: MTU5: Interrupts: Capture V Interrupt Priority: Disabled
+      Extra Features: MTU5: Interrupts: Capture W Interrupt Priority: Disabled
+      Extra Features: MTU5: Interrupts (GPT_SEL): Capture U Interrupt Source: 
+      Extra Features: MTU5: Interrupts (GPT_SEL): Capture V Interrupt Source: 
+      Extra Features: MTU5: Interrupts (GPT_SEL): Capture W Interrupt Source: 
+      Extra Features: MTU5: UVW Noise Filter Enable: Disabled
+      Extra Features: MTU5: UVW Noise Filter Clock Select: PCLKH divided by 1
+      Extra Features: Interrupt Skipping: Skip Mode A: Mode 1
+      Extra Features: Interrupt Skipping: Skip Mode B: Mode 1
+      Extra Features: ADC Trigger: ADC A Compare Match (Raw Counts): 0x0000
+      Extra Features: ADC Trigger: ADC B Compare Match (Raw Counts): 0x0000
+      Extra Features: Interrupt Skipping: TCIV4 Interrupt Skip Count: 0
+      Extra Features: Interrupt Skipping: TCIV3 Interrupt Skip Count: 0
+      Extra Features: Interrupt Skipping: TCIV7 Interrupt Skip Count: 0
+      Extra Features: Interrupt Skipping: TGIA6 Interrupt Skip Count: 0
+      Extra Features: Interrupt Skipping: TRG4AN/TRG4BN Interrupt Skip Count: 0
+      Extra Features: Interrupt Skipping: TRG7AN/TRG7BN Interrupt Skip Count: 0
+      Extra Features: ADC Trigger: MTUn.TGRA (n = 0 to 4, 6, 7) Input Capture/Compare Match: Disabled
+      ELC: MTU0: Trigger Source: Disabled
+      ELC: MTU0: Operation Select: Disabled
+      ELC: MTU3: Trigger Source: Disabled
+      ELC: MTU3: Operation Select: Disabled
+      ELC: MTU4: Trigger Source: Disabled
+      ELC: MTU4: Operation Select: Disabled
+      
+    Instance "g_timer1 Timer, General PWM (r_gpt)"
+      General: Name: g_timer1
+      General: Unit: 0
+      General: Channel: 1
+      General: Mode: Periodic
+      General: Period: 1
+      General: Period Unit: Microseconds
+      Output: Duty Cycle Percent (only applicable in PWM mode): 50
+      Output: GTIOCA Output Enabled: False
+      Output: GTIOCA Stop Level: Pin Level Low
+      Output: GTIOCB Output Enabled: False
+      Output: GTIOCB Stop Level: Pin Level Low
+      Input: Count Up Source: 
+      Input: Count Down Source: 
+      Input: Phase Count Setting Automatically Enable: Disabled
+      Input: Counting Mode: Mode1
+      Input: Start Source: 
+      Input: Stop Source: 
+      Input: Clear Source: 
+      Input: Capture A Source: 
+      Input: Capture B Source: 
+      Input: Noise Filter A Sampling Clock Select: No Filter
+      Input: Noise Filter B Sampling Clock Select: No Filter
+      Interrupts: Callback: g_timer1_callback
+      Interrupts: Overflow/Crest Interrupt Priority: Priority 10
+      Interrupts: Capture A Interrupt Priority: Disabled
+      Interrupts: Capture B Interrupt Priority: Disabled
+      Interrupts: Trough Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): Callback: NULL
+      Interrupts (GPT_SEL): Overflow/Crest Interrupt Source: 
+      Interrupts (GPT_SEL): Capture A Interrupt Source: 
+      Interrupts (GPT_SEL): Capture B Interrupt Source: 
+      Interrupts (GPT_SEL): Trough Interrupt Source: 
+      Interrupts (GPT_SEL): Dead Time Error Interrupt Source: 
+      Interrupts (GPT_SEL): INT0 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT1 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT2 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT3 Interrupt Priority: Disabled
+      Interrupts (GPT_SEL): INT4 Interrupt Priority: Disabled
+      Extra Features: Extra Features: Disabled
+      Extra Features: Output Disable: POEG Link: POEG Channel 0
+      Extra Features: Output Disable: Output Disable POEG Trigger: 
+      Extra Features: ADC Trigger: Start Event Trigger: 
+      Extra Features: Dead Time: Dead Time Count Up (Raw Counts): 0
+      Extra Features: Dead Time: Dead Time Count Down (Raw Counts): 0
+      Extra Features: ADC Trigger: ADC A Compare Match (Raw Counts): 0
+      Extra Features: ADC Trigger: ADC B Compare Match (Raw Counts): 0
+      Extra Features: Interrupt Skipping: Interrupt to Count: None
+      Extra Features: Interrupt Skipping: Interrupt Skip Count: 0
+      Extra Features: Interrupt Skipping: Skip ADC Events: None
+      Extra Features: Output Disable: GTIOCA Disable Setting: Disable Prohibited
+      Extra Features: Output Disable: GTIOCB Disable Setting: Disable Prohibited
+      Extra Features: Extended Interrupt Skipping 1: Interrupt to Count: None
+      Extra Features: Extended Interrupt Skipping 1: Interrupt Skip Count: 0
+      Extra Features: Extended Interrupt Skipping 2: Interrupt to Count: None
+      Extra Features: Extended Interrupt Skipping 2: Interrupt Skip Count: 0
+      Extra Features: Input Capture Interrupt Extended Skipping Function: Overflow Interrupt: None
+      Extra Features: Input Capture Interrupt Extended Skipping Function: Underflow Interrupt: None
+      Extra Features: Input Capture Interrupt Extended Skipping Function: GTADTRA A/D Converter Start Request: None
+      Extra Features: Input Capture Interrupt Extended Skipping Function: GTADTRB A/D Converter Start Request: None
+      Interrupts: Dead Time Error Interrupt Priority: Disabled
+      Extra Features: Input Capture at Count Stop: Enabled
+      Extra Features: Input Capture Signal: Not Supported
+      ELC: LLPP GPT event A: Trigger Source: Disabled
+      ELC: LLPP GPT event B: Trigger Source: Disabled
+      ELC: LLPP GPT event C: Trigger Source: Disabled
+      ELC: LLPP GPT event D: Trigger Source: Disabled
+      ELC: LLPP GPT event E: Trigger Source: Disabled
+      ELC: LLPP GPT event F: Trigger Source: Disabled
+      ELC: LLPP GPT event G: Trigger Source: Disabled
+      ELC: LLPP GPT event H: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event A: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event B: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event C: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event D: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event E: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event F: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event G: Trigger Source: Disabled
+      ELC: NONSAFTY GPT event H: Trigger Source: Disabled
+      
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/SConscript b/projects/etherkit_ethercat_cherryecat/rzn_cfg/SConscript
new file mode 100644
index 00000000..07150e96
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/SConscript
@@ -0,0 +1,17 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+from gcc import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM():
+    if rtconfig.PLATFORM == 'iccarm' or GetOption('target') != 'mdk5':
+        src = Glob('*.c')
+        CPPPATH = [cwd+'/fsp_cfg', cwd + '/fsp_cfg/bsp']
+
+group += DefineGroup('RZN_cfg', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/board_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/board_cfg.h
new file mode 100644
index 00000000..6986cdba
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/board_cfg.h
@@ -0,0 +1,26 @@
+/* generated configuration header file - do not edit */
+#ifndef BOARD_CFG_H_
+#define BOARD_CFG_H_
+#include "../../../rzn/board/rzn2l_rsk/board.h"
+            #define BSP_CFG_XSPI0_X1_BOOT (1)
+            #define BSP_CFG_USE_LOADER_PARAMETER (1)
+            #define BSP_CFG_CACHE_FLG (0x00000000)
+            #define BSP_CFG_CS0BCR_V_WRAPCFG_V (0x00000000)
+            #define BSP_CFG_CS0WCR_V_COMCFG_V (0x00000000)
+            #define BSP_CFG_DUMMY0_BMCFG_V (0x00000000)
+            #define BSP_CFG_BSC_FLG_xSPI_FLG (0x00000000)
+            #define BSP_CFG_LDR_ADDR_NML (0x6000004C)
+            #define BSP_CFG_LDR_SIZE_NML (0x00006000)
+            #define BSP_CFG_DEST_ADDR_NML (0x00102000)
+            #define BSP_CFG_DUMMY1 (0x00000000)
+            #define BSP_CFG_DUMMY2 (0x00000000)
+            #define BSP_CFG_DUMMY3_CSSCTL_V (0x0000003F)
+            #define BSP_CFG_DUMMY4_LIOCFGCS0_V (0x00070000)
+            #define BSP_CFG_DUMMY5 (0x00000000)
+            #define BSP_CFG_DUMMY6 (0x00000000)
+            #define BSP_CFG_DUMMY7 (0x00000000)
+            #define BSP_CFG_DUMMY8 (0x00000000)
+            #define BSP_CFG_DUMMY9 (0x00000000)
+            #define BSP_CFG_DUMMY10_ACCESS_SPEED (0x00000006)
+            #define BSP_CFG_CHECK_SUM (0xE0A8)
+#endif /* BOARD_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 00000000..989932e3
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,37 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define FSP_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #undef FSP_NOT_DEFINED
+            #define BSP_CFG_MCU_VCC_MV (3300)
+
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PORT_PROTECT (1)
+
+            #define BSP_CFG_SOFT_RESET_SUPPORTED (0)
+            #define BSP_CFG_EARLY_INIT (0)
+
+            #define BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0)
+            #if BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED
+             #define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE         BSP_INTERRUPT_ENABLE
+             #define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE        BSP_INTERRUPT_DISABLE
+            #else
+             #define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE
+             #define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE
+            #endif
+#endif /* BSP_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 00000000..d0551c4e
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,14 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_STACK_FIQ_BYTES (0x400)
+            #define BSP_CFG_STACK_IRQ_BYTES (0x400)
+            #define BSP_CFG_STACK_ABT_BYTES (0x400)
+            #define BSP_CFG_STACK_UND_BYTES (0x400)
+            #define BSP_CFG_STACK_SYS_BYTES (0x400)
+            #define BSP_CFG_STACK_SVC_BYTES (0x400)
+            #define BSP_CFG_HEAP_BYTES (0x2000)
+
+            #define BSP_CFG_C_RUNTIME_INIT (1)
+            #define BSP_CFG_USE_TFU_MATHLIB ((1))
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h
new file mode 100644
index 00000000..359058b8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h
@@ -0,0 +1,552 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_MEMORY_CFG_H_
+#define BSP_MCU_DEVICE_MEMORY_CFG_H_
+#define BSP_CFG_MPU0_READ0 (0)
+      #define BSP_CFG_MPU0_WRITE0 (0)
+      #define BSP_CFG_MPU0_STADD0 (0x00000000)
+      #define BSP_CFG_MPU0_ENDADD0 (0x00000C00)
+      #define BSP_CFG_MPU0_READ1 (0)
+      #define BSP_CFG_MPU0_WRITE1 (0)
+      #define BSP_CFG_MPU0_STADD1 (0x00000000)
+      #define BSP_CFG_MPU0_ENDADD1 (0x00000C00)
+      #define BSP_CFG_MPU0_READ2 (0)
+      #define BSP_CFG_MPU0_WRITE2 (0)
+      #define BSP_CFG_MPU0_STADD2 (0x00000000)
+      #define BSP_CFG_MPU0_ENDADD2 (0x00000C00)
+      #define BSP_CFG_MPU0_READ3 (0)
+      #define BSP_CFG_MPU0_WRITE3 (0)
+      #define BSP_CFG_MPU0_STADD3 (0x00000000)
+      #define BSP_CFG_MPU0_ENDADD3 (0x00000C00)
+      #define BSP_CFG_MPU0_READ4 (0)
+      #define BSP_CFG_MPU0_WRITE4 (0)
+      #define BSP_CFG_MPU0_STADD4 (0x00000000)
+      #define BSP_CFG_MPU0_ENDADD4 (0x00000C00)
+      #define BSP_CFG_MPU0_READ5 (0)
+      #define BSP_CFG_MPU0_WRITE5 (0)
+      #define BSP_CFG_MPU0_STADD5 (0x00000000)
+      #define BSP_CFG_MPU0_ENDADD5 (0x00000C00)
+      #define BSP_CFG_MPU0_READ6 (0)
+      #define BSP_CFG_MPU0_WRITE6 (0)
+      #define BSP_CFG_MPU0_STADD6 (0x00000000)
+      #define BSP_CFG_MPU0_ENDADD6 (0x00000C00)
+      #define BSP_CFG_MPU0_READ7 (0)
+      #define BSP_CFG_MPU0_WRITE7 (0)
+      #define BSP_CFG_MPU0_STADD7 (0x00000000)
+      #define BSP_CFG_MPU0_ENDADD7 (0x00000C00)
+      #define BSP_CFG_MPU1_READ0 (0)
+      #define BSP_CFG_MPU1_WRITE0 (0)
+      #define BSP_CFG_MPU1_STADD0 (0x00000000)
+      #define BSP_CFG_MPU1_ENDADD0 (0x00000C00)
+      #define BSP_CFG_MPU1_READ1 (0)
+      #define BSP_CFG_MPU1_WRITE1 (0)
+      #define BSP_CFG_MPU1_STADD1 (0x00000000)
+      #define BSP_CFG_MPU1_ENDADD1 (0x00000C00)
+      #define BSP_CFG_MPU1_READ2 (0)
+      #define BSP_CFG_MPU1_WRITE2 (0)
+      #define BSP_CFG_MPU1_STADD2 (0x00000000)
+      #define BSP_CFG_MPU1_ENDADD2 (0x00000C00)
+      #define BSP_CFG_MPU1_READ3 (0)
+      #define BSP_CFG_MPU1_WRITE3 (0)
+      #define BSP_CFG_MPU1_STADD3 (0x00000000)
+      #define BSP_CFG_MPU1_ENDADD3 (0x00000C00)
+      #define BSP_CFG_MPU1_READ4 (0)
+      #define BSP_CFG_MPU1_WRITE4 (0)
+      #define BSP_CFG_MPU1_STADD4 (0x00000000)
+      #define BSP_CFG_MPU1_ENDADD4 (0x00000C00)
+      #define BSP_CFG_MPU1_READ5 (0)
+      #define BSP_CFG_MPU1_WRITE5 (0)
+      #define BSP_CFG_MPU1_STADD5 (0x00000000)
+      #define BSP_CFG_MPU1_ENDADD5 (0x00000C00)
+      #define BSP_CFG_MPU1_READ6 (0)
+      #define BSP_CFG_MPU1_WRITE6 (0)
+      #define BSP_CFG_MPU1_STADD6 (0x00000000)
+      #define BSP_CFG_MPU1_ENDADD6 (0x00000C00)
+      #define BSP_CFG_MPU1_READ7 (0)
+      #define BSP_CFG_MPU1_WRITE7 (0)
+      #define BSP_CFG_MPU1_STADD7 (0x00000000)
+      #define BSP_CFG_MPU1_ENDADD7 (0x00000C00)
+      #define BSP_CFG_MPU2_READ0 (0)
+      #define BSP_CFG_MPU2_WRITE0 (0)
+      #define BSP_CFG_MPU2_STADD0 (0x00000000)
+      #define BSP_CFG_MPU2_ENDADD0 (0x00000C00)
+      #define BSP_CFG_MPU2_READ1 (0)
+      #define BSP_CFG_MPU2_WRITE1 (0)
+      #define BSP_CFG_MPU2_STADD1 (0x00000000)
+      #define BSP_CFG_MPU2_ENDADD1 (0x00000C00)
+      #define BSP_CFG_MPU2_READ2 (0)
+      #define BSP_CFG_MPU2_WRITE2 (0)
+      #define BSP_CFG_MPU2_STADD2 (0x00000000)
+      #define BSP_CFG_MPU2_ENDADD2 (0x00000C00)
+      #define BSP_CFG_MPU2_READ3 (0)
+      #define BSP_CFG_MPU2_WRITE3 (0)
+      #define BSP_CFG_MPU2_STADD3 (0x00000000)
+      #define BSP_CFG_MPU2_ENDADD3 (0x00000C00)
+      #define BSP_CFG_MPU2_READ4 (0)
+      #define BSP_CFG_MPU2_WRITE4 (0)
+      #define BSP_CFG_MPU2_STADD4 (0x00000000)
+      #define BSP_CFG_MPU2_ENDADD4 (0x00000C00)
+      #define BSP_CFG_MPU2_READ5 (0)
+      #define BSP_CFG_MPU2_WRITE5 (0)
+      #define BSP_CFG_MPU2_STADD5 (0x00000000)
+      #define BSP_CFG_MPU2_ENDADD5 (0x00000C00)
+      #define BSP_CFG_MPU2_READ6 (0)
+      #define BSP_CFG_MPU2_WRITE6 (0)
+      #define BSP_CFG_MPU2_STADD6 (0x00000000)
+      #define BSP_CFG_MPU2_ENDADD6 (0x00000C00)
+      #define BSP_CFG_MPU2_READ7 (0)
+      #define BSP_CFG_MPU2_WRITE7 (0)
+      #define BSP_CFG_MPU2_STADD7 (0x00000000)
+      #define BSP_CFG_MPU2_ENDADD7 (0x00000C00)
+      #define BSP_CFG_MPU3_READ0 (0)
+      #define BSP_CFG_MPU3_WRITE0 (0)
+      #define BSP_CFG_MPU3_STADD0 (0x00000000)
+      #define BSP_CFG_MPU3_ENDADD0 (0x00000000)
+      #define BSP_CFG_MPU3_READ1 (0)
+      #define BSP_CFG_MPU3_WRITE1 (0)
+      #define BSP_CFG_MPU3_STADD1 (0x00000000)
+      #define BSP_CFG_MPU3_ENDADD1 (0x00000000)
+      #define BSP_CFG_MPU3_READ2 (0)
+      #define BSP_CFG_MPU3_WRITE2 (0)
+      #define BSP_CFG_MPU3_STADD2 (0x00000000)
+      #define BSP_CFG_MPU3_ENDADD2 (0x00000000)
+      #define BSP_CFG_MPU3_READ3 (0)
+      #define BSP_CFG_MPU3_WRITE3 (0)
+      #define BSP_CFG_MPU3_STADD3 (0x00000000)
+      #define BSP_CFG_MPU3_ENDADD3 (0x00000000)
+      #define BSP_CFG_MPU3_READ4 (0)
+      #define BSP_CFG_MPU3_WRITE4 (0)
+      #define BSP_CFG_MPU3_STADD4 (0x00000000)
+      #define BSP_CFG_MPU3_ENDADD4 (0x00000000)
+      #define BSP_CFG_MPU3_READ5 (0)
+      #define BSP_CFG_MPU3_WRITE5 (0)
+      #define BSP_CFG_MPU3_STADD5 (0x00000000)
+      #define BSP_CFG_MPU3_ENDADD5 (0x00000000)
+      #define BSP_CFG_MPU3_READ6 (0)
+      #define BSP_CFG_MPU3_WRITE6 (0)
+      #define BSP_CFG_MPU3_STADD6 (0x00000000)
+      #define BSP_CFG_MPU3_ENDADD6 (0x00000000)
+      #define BSP_CFG_MPU3_READ7 (0)
+      #define BSP_CFG_MPU3_WRITE7 (0)
+      #define BSP_CFG_MPU3_STADD7 (0x00000000)
+      #define BSP_CFG_MPU3_ENDADD7 (0x00000000)
+      #define BSP_CFG_MPU4_READ0 (0)
+      #define BSP_CFG_MPU4_WRITE0 (0)
+      #define BSP_CFG_MPU4_STADD0 (0x00000000)
+      #define BSP_CFG_MPU4_ENDADD0 (0x00000000)
+      #define BSP_CFG_MPU4_READ1 (0)
+      #define BSP_CFG_MPU4_WRITE1 (0)
+      #define BSP_CFG_MPU4_STADD1 (0x00000000)
+      #define BSP_CFG_MPU4_ENDADD1 (0x00000000)
+      #define BSP_CFG_MPU4_READ2 (0)
+      #define BSP_CFG_MPU4_WRITE2 (0)
+      #define BSP_CFG_MPU4_STADD2 (0x00000000)
+      #define BSP_CFG_MPU4_ENDADD2 (0x00000000)
+      #define BSP_CFG_MPU4_READ3 (0)
+      #define BSP_CFG_MPU4_WRITE3 (0)
+      #define BSP_CFG_MPU4_STADD3 (0x00000000)
+      #define BSP_CFG_MPU4_ENDADD3 (0x00000000)
+      #define BSP_CFG_MPU4_READ4 (0)
+      #define BSP_CFG_MPU4_WRITE4 (0)
+      #define BSP_CFG_MPU4_STADD4 (0x00000000)
+      #define BSP_CFG_MPU4_ENDADD4 (0x00000000)
+      #define BSP_CFG_MPU4_READ5 (0)
+      #define BSP_CFG_MPU4_WRITE5 (0)
+      #define BSP_CFG_MPU4_STADD5 (0x00000000)
+      #define BSP_CFG_MPU4_ENDADD5 (0x00000000)
+      #define BSP_CFG_MPU4_READ6 (0)
+      #define BSP_CFG_MPU4_WRITE6 (0)
+      #define BSP_CFG_MPU4_STADD6 (0x00000000)
+      #define BSP_CFG_MPU4_ENDADD6 (0x00000000)
+      #define BSP_CFG_MPU4_READ7 (0)
+      #define BSP_CFG_MPU4_WRITE7 (0)
+      #define BSP_CFG_MPU4_STADD7 (0x00000000)
+      #define BSP_CFG_MPU4_ENDADD7 (0x00000000)
+      #define BSP_CFG_MPU6_READ0 (0)
+      #define BSP_CFG_MPU6_WRITE0 (0)
+      #define BSP_CFG_MPU6_STADD0 (0x00000000)
+      #define BSP_CFG_MPU6_ENDADD0 (0x00000C00)
+      #define BSP_CFG_MPU6_READ1 (0)
+      #define BSP_CFG_MPU6_WRITE1 (0)
+      #define BSP_CFG_MPU6_STADD1 (0x00000000)
+      #define BSP_CFG_MPU6_ENDADD1 (0x00000C00)
+      #define BSP_CFG_MPU6_READ2 (0)
+      #define BSP_CFG_MPU6_WRITE2 (0)
+      #define BSP_CFG_MPU6_STADD2 (0x00000000)
+      #define BSP_CFG_MPU6_ENDADD2 (0x00000C00)
+      #define BSP_CFG_MPU6_READ3 (0)
+      #define BSP_CFG_MPU6_WRITE3 (0)
+      #define BSP_CFG_MPU6_STADD3 (0x00000000)
+      #define BSP_CFG_MPU6_ENDADD3 (0x00000C00)
+      #define BSP_CFG_MPU6_READ4 (0)
+      #define BSP_CFG_MPU6_WRITE4 (0)
+      #define BSP_CFG_MPU6_STADD4 (0x00000000)
+      #define BSP_CFG_MPU6_ENDADD4 (0x00000C00)
+      #define BSP_CFG_MPU6_READ5 (0)
+      #define BSP_CFG_MPU6_WRITE5 (0)
+      #define BSP_CFG_MPU6_STADD5 (0x00000000)
+      #define BSP_CFG_MPU6_ENDADD5 (0x00000C00)
+      #define BSP_CFG_MPU6_READ6 (0)
+      #define BSP_CFG_MPU6_WRITE6 (0)
+      #define BSP_CFG_MPU6_STADD6 (0x00000000)
+      #define BSP_CFG_MPU6_ENDADD6 (0x00000C00)
+      #define BSP_CFG_MPU6_READ7 (0)
+      #define BSP_CFG_MPU6_WRITE7 (0)
+      #define BSP_CFG_MPU6_STADD7 (0x00000000)
+      #define BSP_CFG_MPU6_ENDADD7 (0x00000C00)
+      #define BSP_CFG_MPU7_READ0 (0)
+      #define BSP_CFG_MPU7_WRITE0 (0)
+      #define BSP_CFG_MPU7_STADD0 (0x00000000)
+      #define BSP_CFG_MPU7_ENDADD0 (0x00000000)
+      #define BSP_CFG_MPU7_READ1 (0)
+      #define BSP_CFG_MPU7_WRITE1 (0)
+      #define BSP_CFG_MPU7_STADD1 (0x00000000)
+      #define BSP_CFG_MPU7_ENDADD1 (0x00000000)
+      #define BSP_CFG_MPU7_READ2 (0)
+      #define BSP_CFG_MPU7_WRITE2 (0)
+      #define BSP_CFG_MPU7_STADD2 (0x00000000)
+      #define BSP_CFG_MPU7_ENDADD2 (0x00000000)
+      #define BSP_CFG_MPU7_READ3 (0)
+      #define BSP_CFG_MPU7_WRITE3 (0)
+      #define BSP_CFG_MPU7_STADD3 (0x00000000)
+      #define BSP_CFG_MPU7_ENDADD3 (0x00000000)
+      #define BSP_CFG_MPU7_READ4 (0)
+      #define BSP_CFG_MPU7_WRITE4 (0)
+      #define BSP_CFG_MPU7_STADD4 (0x00000000)
+      #define BSP_CFG_MPU7_ENDADD4 (0x00000000)
+      #define BSP_CFG_MPU7_READ5 (0)
+      #define BSP_CFG_MPU7_WRITE5 (0)
+      #define BSP_CFG_MPU7_STADD5 (0x00000000)
+      #define BSP_CFG_MPU7_ENDADD5 (0x00000000)
+      #define BSP_CFG_MPU7_READ6 (0)
+      #define BSP_CFG_MPU7_WRITE6 (0)
+      #define BSP_CFG_MPU7_STADD6 (0x00000000)
+      #define BSP_CFG_MPU7_ENDADD6 (0x00000000)
+      #define BSP_CFG_MPU7_READ7 (0)
+      #define BSP_CFG_MPU7_WRITE7 (0)
+      #define BSP_CFG_MPU7_STADD7 (0x00000000)
+      #define BSP_CFG_MPU7_ENDADD7 (0x00000000)
+      #define BSP_CFG_MPU8_READ0 (0)
+      #define BSP_CFG_MPU8_WRITE0 (0)
+      #define BSP_CFG_MPU8_STADD0 (0x00000000)
+      #define BSP_CFG_MPU8_ENDADD0 (0x00000000)
+      #define BSP_CFG_MPU8_READ1 (0)
+      #define BSP_CFG_MPU8_WRITE1 (0)
+      #define BSP_CFG_MPU8_STADD1 (0x00000000)
+      #define BSP_CFG_MPU8_ENDADD1 (0x00000000)
+      #define BSP_CFG_MPU8_READ2 (0)
+      #define BSP_CFG_MPU8_WRITE2 (0)
+      #define BSP_CFG_MPU8_STADD2 (0x00000000)
+      #define BSP_CFG_MPU8_ENDADD2 (0x00000000)
+      #define BSP_CFG_MPU8_READ3 (0)
+      #define BSP_CFG_MPU8_WRITE3 (0)
+      #define BSP_CFG_MPU8_STADD3 (0x00000000)
+      #define BSP_CFG_MPU8_ENDADD3 (0x00000000)
+      #define BSP_CFG_MPU8_READ4 (0)
+      #define BSP_CFG_MPU8_WRITE4 (0)
+      #define BSP_CFG_MPU8_STADD4 (0x00000000)
+      #define BSP_CFG_MPU8_ENDADD4 (0x00000000)
+      #define BSP_CFG_MPU8_READ5 (0)
+      #define BSP_CFG_MPU8_WRITE5 (0)
+      #define BSP_CFG_MPU8_STADD5 (0x00000000)
+      #define BSP_CFG_MPU8_ENDADD5 (0x00000000)
+      #define BSP_CFG_MPU8_READ6 (0)
+      #define BSP_CFG_MPU8_WRITE6 (0)
+      #define BSP_CFG_MPU8_STADD6 (0x00000000)
+      #define BSP_CFG_MPU8_ENDADD6 (0x00000000)
+      #define BSP_CFG_MPU8_READ7 (0)
+      #define BSP_CFG_MPU8_WRITE7 (0)
+      #define BSP_CFG_MPU8_STADD7 (0x00000000)
+      #define BSP_CFG_MPU8_ENDADD7 (0x00000000)
+
+      #define BSP_CFG_CPU_MPU_ATTR0_TYPE        (BSP_TYPE_NORMAL_MEMORY)
+      #define BSP_CFG_CPU_MPU_ATTR0_INNER       (BSP_WRITE_BACK_NON_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR0_INNER_READ  (BSP_READ_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE (BSP_WRITE_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR0_OUTER       (BSP_WRITE_BACK_NON_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR0_OUTER_READ  (BSP_READ_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE (BSP_WRITE_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
+
+      #define BSP_CFG_CPU_MPU_ATTR1_TYPE        (BSP_TYPE_NORMAL_MEMORY)
+      #define BSP_CFG_CPU_MPU_ATTR1_INNER       (BSP_WRITE_NON_THROUGH)
+      #define BSP_CFG_CPU_MPU_ATTR1_INNER_READ  (BSP_READ_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE (BSP_WRITE_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR1_OUTER       (BSP_WRITE_NON_THROUGH)
+      #define BSP_CFG_CPU_MPU_ATTR1_OUTER_READ  (BSP_READ_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE (BSP_WRITE_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
+
+      #define BSP_CFG_CPU_MPU_ATTR2_TYPE        (BSP_TYPE_NORMAL_MEMORY)
+      #define BSP_CFG_CPU_MPU_ATTR2_INNER       (BSP_WRITE_NON_THROUGH)
+      #define BSP_CFG_CPU_MPU_ATTR2_INNER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR2_OUTER       (BSP_WRITE_NON_THROUGH)
+      #define BSP_CFG_CPU_MPU_ATTR2_OUTER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
+
+      #define BSP_CFG_CPU_MPU_ATTR3_TYPE        (BSP_TYPE_NORMAL_MEMORY)
+      #define BSP_CFG_CPU_MPU_ATTR3_INNER       (BSP_NON_CACHEABLE)
+      #define BSP_CFG_CPU_MPU_ATTR3_INNER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR3_OUTER       (BSP_NON_CACHEABLE)
+      #define BSP_CFG_CPU_MPU_ATTR3_OUTER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
+
+      #define BSP_CFG_CPU_MPU_ATTR4_TYPE        (BSP_TYPE_DEVICE_MEMORY)
+      #define BSP_CFG_CPU_MPU_ATTR4_INNER       (BSP_WRITE_THROUGH_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR4_INNER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR4_OUTER       (BSP_WRITE_THROUGH_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR4_OUTER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
+
+      #define BSP_CFG_CPU_MPU_ATTR5_TYPE        (BSP_TYPE_DEVICE_MEMORY)
+      #define BSP_CFG_CPU_MPU_ATTR5_INNER       (BSP_WRITE_THROUGH_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR5_INNER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR5_OUTER       (BSP_WRITE_THROUGH_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR5_OUTER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE (BSP_DEVICE_NGNRE)
+
+      #define BSP_CFG_CPU_MPU_ATTR6_TYPE        (BSP_TYPE_DEVICE_MEMORY)
+      #define BSP_CFG_CPU_MPU_ATTR6_INNER       (BSP_WRITE_THROUGH_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR6_INNER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR6_OUTER       (BSP_WRITE_THROUGH_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR6_OUTER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE (BSP_DEVICE_NGRE)
+
+      #define BSP_CFG_CPU_MPU_ATTR7_TYPE        (BSP_TYPE_DEVICE_MEMORY)
+      #define BSP_CFG_CPU_MPU_ATTR7_INNER       (BSP_WRITE_THROUGH_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR7_INNER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR7_OUTER       (BSP_WRITE_THROUGH_TRANSIENT)
+      #define BSP_CFG_CPU_MPU_ATTR7_OUTER_READ  (BSP_READ_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
+      #define BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE (BSP_DEVICE_GRE)
+
+      /* Region00 : ATCM */
+      #define BSP_CFG_EL1_MPU_REGION00_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION00_LIMIT     (0x0001FFFF)
+      #define BSP_CFG_EL1_MPU_REGION00_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION00_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION00_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION00_ATTRINDEX (BSP_ATTRINDEX3)
+      #define BSP_CFG_EL1_MPU_REGION00_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region01 : BTCM */
+      #define BSP_CFG_EL1_MPU_REGION01_BASE      (0x00100000)
+      #define BSP_CFG_EL1_MPU_REGION01_LIMIT     (0x0011FFFF)
+      #define BSP_CFG_EL1_MPU_REGION01_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION01_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION01_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION01_ATTRINDEX (BSP_ATTRINDEX3)
+      #define BSP_CFG_EL1_MPU_REGION01_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region02 : System RAM */
+      #define BSP_CFG_EL1_MPU_REGION02_BASE      (0x10000000)
+      #define BSP_CFG_EL1_MPU_REGION02_LIMIT     (0x1017FFFF)
+      #define BSP_CFG_EL1_MPU_REGION02_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION02_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION02_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION02_ATTRINDEX (BSP_ATTRINDEX1)
+      #define BSP_CFG_EL1_MPU_REGION02_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region03 : Mirror area of System RAM */
+      #define BSP_CFG_EL1_MPU_REGION03_BASE      (0x30000000)
+      #define BSP_CFG_EL1_MPU_REGION03_LIMIT     (0x3017FFFF)
+      #define BSP_CFG_EL1_MPU_REGION03_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION03_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION03_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION03_ATTRINDEX (BSP_ATTRINDEX3)
+      #define BSP_CFG_EL1_MPU_REGION03_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region04 : Mirror area of external address space */
+      #define BSP_CFG_EL1_MPU_REGION04_BASE      (0x40000000)
+      #define BSP_CFG_EL1_MPU_REGION04_LIMIT     (0x5FFFFFFF)
+      #define BSP_CFG_EL1_MPU_REGION04_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION04_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION04_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION04_ATTRINDEX (BSP_ATTRINDEX3)
+      #define BSP_CFG_EL1_MPU_REGION04_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region05 : External address space */
+      #define BSP_CFG_EL1_MPU_REGION05_BASE      (0x60000000)
+      #define BSP_CFG_EL1_MPU_REGION05_LIMIT     (0x7FFFFFFF)
+      #define BSP_CFG_EL1_MPU_REGION05_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION05_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION05_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION05_ATTRINDEX (BSP_ATTRINDEX1)
+      #define BSP_CFG_EL1_MPU_REGION05_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region06 : Non-Safety Peripheral */
+      #define BSP_CFG_EL1_MPU_REGION06_BASE      (0x80000000)
+      #define BSP_CFG_EL1_MPU_REGION06_LIMIT     (0x80FFFFFF)
+      #define BSP_CFG_EL1_MPU_REGION06_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION06_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION06_XN        (BSP_EXECUTE_NEVER)
+      #define BSP_CFG_EL1_MPU_REGION06_ATTRINDEX (BSP_ATTRINDEX5)
+      #define BSP_CFG_EL1_MPU_REGION06_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region07 : Safety Peripheral */
+      #define BSP_CFG_EL1_MPU_REGION07_BASE      (0x81000000)
+      #define BSP_CFG_EL1_MPU_REGION07_LIMIT     (0x81FFFFFF)
+      #define BSP_CFG_EL1_MPU_REGION07_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION07_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION07_XN        (BSP_EXECUTE_NEVER)
+      #define BSP_CFG_EL1_MPU_REGION07_ATTRINDEX (BSP_ATTRINDEX5)
+      #define BSP_CFG_EL1_MPU_REGION07_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region08 : LLPP Peripheral */
+      #define BSP_CFG_EL1_MPU_REGION08_BASE      (0x90000000)
+      #define BSP_CFG_EL1_MPU_REGION08_LIMIT     (0x901FFFFF)
+      #define BSP_CFG_EL1_MPU_REGION08_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION08_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION08_XN        (BSP_EXECUTE_NEVER)
+      #define BSP_CFG_EL1_MPU_REGION08_ATTRINDEX (BSP_ATTRINDEX5)
+      #define BSP_CFG_EL1_MPU_REGION08_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region09 : GIC0 */
+      #define BSP_CFG_EL1_MPU_REGION09_BASE      (0x94000000)
+      #define BSP_CFG_EL1_MPU_REGION09_LIMIT     (0x941FFFFF)
+      #define BSP_CFG_EL1_MPU_REGION09_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION09_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION09_XN        (BSP_EXECUTE_NEVER)
+      #define BSP_CFG_EL1_MPU_REGION09_ATTRINDEX (BSP_ATTRINDEX4)
+      #define BSP_CFG_EL1_MPU_REGION09_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region10 : Debug Private */
+      #define BSP_CFG_EL1_MPU_REGION10_BASE      (0xC0000000)
+      #define BSP_CFG_EL1_MPU_REGION10_LIMIT     (0xC0FFFFFF)
+      #define BSP_CFG_EL1_MPU_REGION10_SH        (BSP_OUTER_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION10_AP        (BSP_EL1RW_EL0RW)
+      #define BSP_CFG_EL1_MPU_REGION10_XN        (BSP_EXECUTE_NEVER)
+      #define BSP_CFG_EL1_MPU_REGION10_ATTRINDEX (BSP_ATTRINDEX4)
+      #define BSP_CFG_EL1_MPU_REGION10_ENABLE    (BSP_REGION_ENABLE)
+
+      /* Region11 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION11_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION11_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION11_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION11_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION11_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION11_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION11_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region12 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION12_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION12_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION12_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION12_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION12_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION12_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION12_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region13 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION13_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION13_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION13_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION13_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION13_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION13_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION13_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region14 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION14_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION14_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION14_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION14_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION14_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION14_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION14_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region15 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION15_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION15_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION15_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION15_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION15_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION15_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION15_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region16 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION16_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION16_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION16_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION16_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION16_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION16_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION16_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region17 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION17_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION17_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION17_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION17_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION17_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION17_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION17_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region18 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION18_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION18_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION18_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION18_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION18_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION18_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION18_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region19 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION19_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION19_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION19_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION19_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION19_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION19_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION19_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region20 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION20_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION20_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION20_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION20_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION20_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION20_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION20_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region21 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION21_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION21_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION21_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION21_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION21_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION21_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION21_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region22 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION22_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION22_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION22_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION22_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION22_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION22_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION22_ENABLE    (BSP_REGION_DISABLE)
+
+      /* Region23 : Not Used */
+      #define BSP_CFG_EL1_MPU_REGION23_BASE      (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION23_LIMIT     (0x00000000)
+      #define BSP_CFG_EL1_MPU_REGION23_SH        (BSP_NON_SHAREABLE)
+      #define BSP_CFG_EL1_MPU_REGION23_AP        (BSP_EL1RW_EL0NO)
+      #define BSP_CFG_EL1_MPU_REGION23_XN        (BSP_EXECUTE_ENABLE)
+      #define BSP_CFG_EL1_MPU_REGION23_ATTRINDEX (BSP_ATTRINDEX0)
+      #define BSP_CFG_EL1_MPU_REGION23_ENABLE    (BSP_REGION_DISABLE)
+
+      #define BSP_CFG_SCTLR_BR_BIT               (BSP_BG_REGION_DISABLE)
+      #define BSP_CFG_SCTLR_I_BIT                (BSP_ICACHE_ENABLE)
+      #define BSP_CFG_SCTLR_C_BIT                (BSP_DATACACHE_ENABLE)
+#endif /* BSP_MCU_DEVICE_MEMORY_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 00000000..70e28786
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,12 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R9A07G084M04GBG
+      #define BSP_ATCM_SIZE_BYTES (131072)
+      #define BSP_BTCM_SIZE_BYTES (131072)
+      #define BSP_SYSTEM_RAM_SIZE_BYTES (1572864)
+      #define BSP_PACKAGE_FBGA
+      #define BSP_PACKAGE_PINS (225)
+
+      #define BSP_CFG_CORE_CR52 (0)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 00000000..3bfed56a
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,15 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "bsp_mcu_device_memory_cfg.h"
+            #include "../../../rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_API_OVERRIDE "../../src/bsp/mcu/rzn2l/bsp_override.h"
+            #define BSP_MCU_GROUP_RZN2L (1)
+            #define BSP_LOCO_HZ (240000)
+            #define BSP_GLOBAL_SYSTEM_COUNTER_CLOCK_HZ  (25000000)
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (32)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES (448)
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h
new file mode 100644
index 00000000..baaa5be8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MEMORY_CFG_H_
+#define BSP_MEMORY_CFG_H_
+#define BSP_MPU_SUPPORT
+#endif /* BSP_MEMORY_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 00000000..c0d922b3
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,105 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+#define ETH2_RXD3 (BSP_IO_PORT_00_PIN_0)
+#define ETH2_RXDV (BSP_IO_PORT_00_PIN_1)
+#define ETH2_TXEN (BSP_IO_PORT_00_PIN_2)
+#define ETH2_REFCLK (BSP_IO_PORT_00_PIN_3)
+#define ETH2_LINK (BSP_IO_PORT_00_PIN_5)
+#define ETH2_TXCLK (BSP_IO_PORT_00_PIN_6)
+#define ETH2_TXD3 (BSP_IO_PORT_01_PIN_2)
+#define ETH2_TXD2 (BSP_IO_PORT_01_PIN_3)
+#define ETH2_TXD1 (BSP_IO_PORT_01_PIN_4)
+#define ETH2_TXD0 (BSP_IO_PORT_01_PIN_5)
+#define CAN_RX (BSP_IO_PORT_01_PIN_7)
+#define CAN_TX (BSP_IO_PORT_02_PIN_2)
+#define TDO (BSP_IO_PORT_02_PIN_4)
+#define TDI (BSP_IO_PORT_02_PIN_5)
+#define TMS (BSP_IO_PORT_02_PIN_6)
+#define TCK (BSP_IO_PORT_02_PIN_7)
+#define ETH_LED4 (BSP_IO_PORT_03_PIN_0)
+#define LED_RED1 (BSP_IO_PORT_04_PIN_1)
+#define ETH_LED6 (BSP_IO_PORT_04_PIN_4)
+#define ETH_LED7 (BSP_IO_PORT_05_PIN_0)
+#define SCL (BSP_IO_PORT_05_PIN_2)
+#define SDA (BSP_IO_PORT_05_PIN_3)
+#define SW2 (BSP_IO_PORT_05_PIN_4)
+#define ETH1_LINK (BSP_IO_PORT_05_PIN_5)
+#define ETH1_TXD2 (BSP_IO_PORT_05_PIN_7)
+#define ETH1_TXD3 (BSP_IO_PORT_06_PIN_0)
+#define ETH1_REFCLK (BSP_IO_PORT_06_PIN_1)
+#define ETH1_TXD1 (BSP_IO_PORT_06_PIN_2)
+#define ETH1_TXD0 (BSP_IO_PORT_06_PIN_3)
+#define ETH1_TXCLK (BSP_IO_PORT_06_PIN_4)
+#define ETH1_TXEN (BSP_IO_PORT_06_PIN_5)
+#define ETH1_RXD0 (BSP_IO_PORT_06_PIN_6)
+#define ETH1_RXD1 (BSP_IO_PORT_06_PIN_7)
+#define ETH1_RXD2 (BSP_IO_PORT_07_PIN_0)
+#define ETH1_RXD3 (BSP_IO_PORT_07_PIN_1)
+#define ETH1_RXDV (BSP_IO_PORT_07_PIN_2)
+#define ETH1_RXCLK (BSP_IO_PORT_07_PIN_3)
+#define USB_VBUSIN (BSP_IO_PORT_07_PIN_4)
+#define ETH0_RXD3 (BSP_IO_PORT_08_PIN_4)
+#define ETH0_RXDV (BSP_IO_PORT_08_PIN_5)
+#define ETH0_RXCLK (BSP_IO_PORT_08_PIN_6)
+#define ETH_MDC (BSP_IO_PORT_08_PIN_7)
+#define ETH_MDIO (BSP_IO_PORT_09_PIN_0)
+#define ETH0_REFCLK (BSP_IO_PORT_09_PIN_1)
+#define ETH0_TXD3 (BSP_IO_PORT_09_PIN_3)
+#define ETH0_TXD2 (BSP_IO_PORT_09_PIN_4)
+#define ETH0_TXD1 (BSP_IO_PORT_09_PIN_5)
+#define ETH0_TXD0 (BSP_IO_PORT_09_PIN_6)
+#define ETH0_TXCLK (BSP_IO_PORT_09_PIN_7)
+#define ETH0_TXEN (BSP_IO_PORT_10_PIN_0)
+#define ETH0_RXD0 (BSP_IO_PORT_10_PIN_1)
+#define ETH0_RXD1 (BSP_IO_PORT_10_PIN_2)
+#define ETH0_RXD2 (BSP_IO_PORT_10_PIN_3)
+#define ETH0_LINK (BSP_IO_PORT_10_PIN_4)
+#define EEPROM_SCL (BSP_IO_PORT_13_PIN_2)
+#define EEPROM_SDA (BSP_IO_PORT_13_PIN_3)
+#define ESC_RESETOUT (BSP_IO_PORT_13_PIN_4)
+#define SW3_Pin2 (BSP_IO_PORT_13_PIN_5)
+#define SW3_Pin1 (BSP_IO_PORT_13_PIN_6)
+#define SW3_Pin4 (BSP_IO_PORT_13_PIN_7)
+#define SW3_Pin3 (BSP_IO_PORT_14_PIN_0)
+#define XSPI0_ECS (BSP_IO_PORT_14_PIN_2)
+#define XSPI0_DS (BSP_IO_PORT_14_PIN_4)
+#define XSPI0_CKN (BSP_IO_PORT_14_PIN_5)
+#define XSPI0_CKP (BSP_IO_PORT_14_PIN_6)
+#define XSPI0_IO0 (BSP_IO_PORT_14_PIN_7)
+#define XSPI0_IO1 (BSP_IO_PORT_15_PIN_0)
+#define XSPI0_IO2 (BSP_IO_PORT_15_PIN_1)
+#define XSPI0_IO3 (BSP_IO_PORT_15_PIN_2)
+#define XSPI0_IO4 (BSP_IO_PORT_15_PIN_3)
+#define XSPI0_IO5 (BSP_IO_PORT_15_PIN_4)
+#define XSPI0_IO6 (BSP_IO_PORT_15_PIN_5)
+#define XSPI0_IO7 (BSP_IO_PORT_15_PIN_6)
+#define OSPI_CS (BSP_IO_PORT_15_PIN_7)
+#define ORAM_CS0 (BSP_IO_PORT_16_PIN_0)
+#define XSPI0_RESET0 (BSP_IO_PORT_16_PIN_1)
+#define SW1 (BSP_IO_PORT_16_PIN_3)
+#define UART_USB_TX (BSP_IO_PORT_16_PIN_5)
+#define UART_USB_RX (BSP_IO_PORT_16_PIN_6)
+#define LED_RED2 (BSP_IO_PORT_17_PIN_3)
+#define USB_OVRCUR (BSP_IO_PORT_17_PIN_5)
+#define SCI_RXD (BSP_IO_PORT_17_PIN_7)
+#define SCI_TXD (BSP_IO_PORT_18_PIN_0)
+#define LED_GREEN (BSP_IO_PORT_18_PIN_2)
+#define SCK (BSP_IO_PORT_18_PIN_4)
+#define MOSI (BSP_IO_PORT_18_PIN_5)
+#define MISO (BSP_IO_PORT_18_PIN_6)
+#define USB_VBUSEN (BSP_IO_PORT_19_PIN_0)
+#define ETH_LED2_MDV0 (BSP_IO_PORT_20_PIN_1)
+#define ETH_LED0_MDV1 (BSP_IO_PORT_20_PIN_2)
+#define ETH_LED1_MDV2 (BSP_IO_PORT_20_PIN_3)
+#define ETH_LED3_MDV3 (BSP_IO_PORT_20_PIN_4)
+#define CS (BSP_IO_PORT_21_PIN_1)
+#define ETH_LED5 (BSP_IO_PORT_22_PIN_1)
+#define LED_ORANGE (BSP_IO_PORT_22_PIN_3)
+#define ETH2_RXD0 (BSP_IO_PORT_23_PIN_7)
+#define ETH2_RXD1 (BSP_IO_PORT_24_PIN_0)
+#define ETH2_RXCLK (BSP_IO_PORT_24_PIN_1)
+#define ETH2_RXD2 (BSP_IO_PORT_24_PIN_2)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RSK+RZN2L */
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_cfg.h
new file mode 100644
index 00000000..347f2d63
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_cfg.h
@@ -0,0 +1,9 @@
+/* generated configuration header file - do not edit */
+#ifndef R_ETHER_CFG_H_
+#define R_ETHER_CFG_H_
+#define GMAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+            #if (FSP_NOT_DEFINED != 1)
+            #define GMAC_IMPLEMENT_ETHSW
+            #endif
+#endif /* R_ETHER_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_phy_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_phy_cfg.h
new file mode 100644
index 00000000..82a09cb5
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_phy_cfg.h
@@ -0,0 +1,33 @@
+/* generated configuration header file - do not edit */
+#ifndef R_ETHER_PHY_CFG_H_
+#define R_ETHER_PHY_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #define ETHER_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+            #define ETHER_PHY_CHIP_DEFAULT  BOARD_PHY_TYPE
+
+#ifndef ETHER_PHY_CFG_TARGET_VSC8541_ENABLE
+            #define ETHER_PHY_CFG_TARGET_VSC8541_ENABLE          (0)
+#endif
+#ifndef ETHER_PHY_CFG_TARGET_KSZ9131_ENABLE
+            #define ETHER_PHY_CFG_TARGET_KSZ9131_ENABLE          (0)
+#endif
+#ifndef ETHER_PHY_CFG_TARGET_KSZ9031_ENABLE
+            #define ETHER_PHY_CFG_TARGET_KSZ9031_ENABLE          (0)
+#endif
+#ifndef ETHER_PHY_CFG_TARGET_KSZ8081_ENABLE
+            #define ETHER_PHY_CFG_TARGET_KSZ8081_ENABLE          (0)
+#endif
+#ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE
+            #define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE          (0)
+#endif
+#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE
+            #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE      (1)
+#endif
+
+            #ifdef __cplusplus
+            }
+            #endif
+#endif /* R_ETHER_PHY_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_selector_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_selector_cfg.h
new file mode 100644
index 00000000..4a1a78e4
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_selector_cfg.h
@@ -0,0 +1,6 @@
+/* generated configuration header file - do not edit */
+#ifndef R_ETHER_SELECTOR_CFG_H_
+#define R_ETHER_SELECTOR_CFG_H_
+#define ETHER_SELECTOR_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+            #define ETHER_SELECTOR_CFG_MODE       (0)
+#endif /* R_ETHER_SELECTOR_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_switch_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_switch_cfg.h
new file mode 100644
index 00000000..ba52606b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ether_switch_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef R_ETHER_SWITCH_CFG_H_
+#define R_ETHER_SWITCH_CFG_H_
+#define ETHSW_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#endif /* R_ETHER_SWITCH_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_gpt_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_gpt_cfg.h
new file mode 100644
index 00000000..a01c16a8
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_gpt_cfg.h
@@ -0,0 +1,16 @@
+/* generated configuration header file - do not edit */
+#ifndef R_GPT_CFG_H_
+#define R_GPT_CFG_H_
+#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (0)
+#define GPT_CFG_WRITE_PROTECT_ENABLE (0)
+
+#define GPT_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0)
+#if GPT_CFG_MULTIPLEX_INTERRUPT_SUPPORTED
+ #define GPT_CFG_MULTIPLEX_INTERRUPT_ENABLE         BSP_INTERRUPT_ENABLE
+ #define GPT_CFG_MULTIPLEX_INTERRUPT_DISABLE        BSP_INTERRUPT_DISABLE
+#else
+ #define GPT_CFG_MULTIPLEX_INTERRUPT_ENABLE
+ #define GPT_CFG_MULTIPLEX_INTERRUPT_DISABLE
+#endif
+#endif /* R_GPT_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ioport_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 00000000..d2688bf5
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_mtu3_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_mtu3_cfg.h
new file mode 100644
index 00000000..bf8207cf
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_mtu3_cfg.h
@@ -0,0 +1,15 @@
+/* generated configuration header file - do not edit */
+#ifndef R_MTU3_CFG_H_
+#define R_MTU3_CFG_H_
+#define MTU3_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define MTU3_CFG_OUTPUT_SUPPORT_ENABLE (0)
+#define MTU3_CFG_UVW_SUPPORT_ENABLE    (0)
+#define MTU3_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0)
+#if MTU3_CFG_MULTIPLEX_INTERRUPT_SUPPORTED
+  #define MTU3_CFG_MULTIPLEX_INTERRUPT_ENABLE        BSP_INTERRUPT_ENABLE
+  #define MTU3_CFG_MULTIPLEX_INTERRUPT_DISABLE       BSP_INTERRUPT_DISABLE
+#else
+  #define MTU3_CFG_MULTIPLEX_INTERRUPT_ENABLE
+  #define MTU3_CFG_MULTIPLEX_INTERRUPT_DISABLE
+#endif
+#endif /* R_MTU3_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_sci_uart_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_sci_uart_cfg.h
new file mode 100644
index 00000000..fe4cc09b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_cfg/fsp_cfg/r_sci_uart_cfg.h
@@ -0,0 +1,16 @@
+/* generated configuration header file - do not edit */
+#ifndef R_SCI_UART_CFG_H_
+#define R_SCI_UART_CFG_H_
+#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define SCI_UART_CFG_FIFO_SUPPORT (1)
+#define SCI_UART_CFG_DMAC_SUPPORTED (0)
+#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
+#define SCI_UART_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0)
+#if SCI_UART_CFG_MULTIPLEX_INTERRUPT_SUPPORTED
+ #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE         BSP_INTERRUPT_ENABLE
+ #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE        BSP_INTERRUPT_DISABLE
+#else
+ #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE
+ #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE
+#endif
+#endif /* R_SCI_UART_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/SConscript b/projects/etherkit_ethercat_cherryecat/rzn_gen/SConscript
new file mode 100644
index 00000000..e8470831
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/SConscript
@@ -0,0 +1,17 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+from gcc import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM():
+    if rtconfig.PLATFORM == 'iccarm' or GetOption('target') != 'mdk5':
+        src = Glob('*.c')
+        CPPPATH = [cwd, ]
+
+group = DefineGroup('RZN_gen', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/bsp_clock_cfg.h b/projects/etherkit_ethercat_cherryecat/rzn_gen/bsp_clock_cfg.h
new file mode 100644
index 00000000..ae4efb4d
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/bsp_clock_cfg.h
@@ -0,0 +1,42 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_MAIN_CLOCK_HZ (25000000) /* Main Clock: 25MHz */
+#define BSP_CFG_LOCO_ENABLE (BSP_CLOCKS_LOCO_ENABLE) /* LOCO Enabled */
+#define BSP_CFG_PLL1 (BSP_CLOCKS_PLL1_INITIAL) /* PLL1 is initial state */
+#define BSP_CFG_PHYSEL (BSP_CLOCKS_PHYSEL_MAINOSC_DIV) /* Ethernet Clock src: Main clock oscillator */
+#define BSP_CFG_CLMA0_ENABLE (BSP_CLOCKS_CLMA0_ENABLE) /* CLMA0 Enabled */
+#define BSP_CFG_CLMA0MASK (BSP_CLOCKS_CLMA0_ERROR_NOT_MASK) /* CLMA0 error not mask */
+#define BSP_CFG_CLMA3MASK (BSP_CLOCKS_CLMA3_ERROR_NOT_MASK) /* CLMA3 error not mask */
+#define BSP_CFG_CLMA1MASK (BSP_CLOCKS_CLMA1_ERROR_MASK) /* CLMA1 error mask */
+#define BSP_CFG_CLMA3_ENABLE (BSP_CLOCKS_CLMA3_ENABLE) /* CLMA3 Enabled */
+#define BSP_CFG_CLMA1_ENABLE (BSP_CLOCKS_CLMA1_ENABLE) /* CLMA1 Enabled */
+#define BSP_CFG_CLMA2_ENABLE (BSP_CLOCKS_CLMA2_ENABLE) /* CLMA2 Enabled */
+#define BSP_CFG_CLMA0_CMPL (1) /* CLMA0 CMPL 1 */
+#define BSP_CFG_CLMA1_CMPL (1) /* CLMA1 CMPL 1 */
+#define BSP_CFG_CLMA2_CMPL (1) /* CLMA2 CMPL 1 */
+#define BSP_CFG_CLMA3_CMPL (1) /* CLMA3 CMPL 1 */
+#define BSP_CFG_CLMASEL (BSP_CLOCKS_CLMASEL_LOCO) /* Alternative clock: LOCO */
+#define BSP_CFG_CLMA0_CMPH (1023) /* CLMA0 CMPH 1023 */
+#define BSP_CFG_CLMA1_CMPH (1023) /* CLMA1 CMPH 1023 */
+#define BSP_CFG_CLMA2_CMPH (1023) /* CLMA2 CMPH 1023 */
+#define BSP_CFG_CLMA3_CMPH (1023) /* CLMA3 CMPH 1023 */
+#define BSP_CFG_DIVSELSUB (BSP_CLOCKS_DIVSELSUB_0) /* ICLK 200MHz */
+#define BSP_CFG_FSELCPU0 (BSP_CLOCKS_FSELCPU0_ICLK_MUL2) /* CPU0CLK Mulx2 */
+#define BSP_CFG_CKIO (BSP_CLOCKS_CKIO_ICLK_DIV4) /* CKIO Div/4 */
+#define BSP_CFG_SCI0ASYNCCLK (BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI0ASYNCCLK: 96MHz */
+#define BSP_CFG_SCI1ASYNCCLK (BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI1ASYNCCLK: 96MHz */
+#define BSP_CFG_SCI2ASYNCCLK (BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI2ASYNCCLK: 96MHz */
+#define BSP_CFG_SCI3ASYNCCLK (BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI3ASYNCCLK: 96MHz */
+#define BSP_CFG_SCI4ASYNCCLK (BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI4ASYNCCLK: 96MHz */
+#define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96MHz */
+#define BSP_CFG_SPI0ASYNCCLK (BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI0ASYNCCLK: 96MHz */
+#define BSP_CFG_SPI1ASYNCCLK (BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI1ASYNCCLK: 96MHz */
+#define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96MHz */
+#define BSP_CFG_SPI3ASYNCCLK (BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI3ASYNCCLK: 96MHz */
+#define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* CANFDCLK Src: PCLKCAN 40MHz */
+#define BSP_CFG_FSELXSPI0_DIVSELXSPI0 (BSP_CLOCKS_XSPI0_CLOCK_DIV0_133_3_MHZ) /* XSPI_CLK0 133.3MHz */
+#define BSP_CFG_FSELXSPI1_DIVSELXSPI1 (BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK1 12.5MHz */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/common_data.c b/projects/etherkit_ethercat_cherryecat/rzn_gen/common_data.c
new file mode 100644
index 00000000..2c7f165b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/common_data.c
@@ -0,0 +1,75 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+/** IOPORT interface configuration for event link **/
+            const ioport_extend_cfg_t  g_ioport_cfg_extend =
+            {
+                .port_group_output_cfg[IOPORT_PORT_GROUP_1] =
+                {
+                    .pin_select   = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE),
+                    .operation    = IOPORT_EVENT_OUTPUT_OPERATION_LOW
+                },
+                .port_group_output_cfg[IOPORT_PORT_GROUP_2] =
+                {
+                    .pin_select   = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE),
+                    .operation    = IOPORT_EVENT_OUTPUT_OPERATION_LOW
+                },
+                .port_group_input_cfg[IOPORT_PORT_GROUP_1] =
+                {
+                    .event_control = IOPORT_EVENT_CONTROL_DISABLE,
+                    .pin_select    = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE),
+                    .edge_detection    = IOPORT_EVENT_DETECTION_RISING_EDGE,
+                    .overwrite_control = IOPORT_EVENT_CONTROL_DISABLE,
+                    .buffer_init_value = IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 7U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 6U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 5U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 4U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 3U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 2U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 1U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW
+                },
+                .port_group_input_cfg[IOPORT_PORT_GROUP_2] =
+                {
+                    .event_control = IOPORT_EVENT_CONTROL_DISABLE,
+                    .pin_select    = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE),
+                    .edge_detection    = IOPORT_EVENT_DETECTION_RISING_EDGE,
+                    .overwrite_control = IOPORT_EVENT_CONTROL_DISABLE,
+                    .buffer_init_value = IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 7U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 6U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 5U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 4U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 3U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 2U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 1U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW
+                },
+                .single_port_cfg[IOPORT_SINGLE_PORT_0] =
+                {
+                    .event_control = IOPORT_EVENT_CONTROL_DISABLE,
+                    .direction = IOPORT_EVENT_DIRECTION_OUTPUT,
+                    .port_num  = (uint16_t)BSP_IO_PORT_16_PIN_0,
+                    .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW,
+                    .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE
+                },
+                .single_port_cfg[IOPORT_SINGLE_PORT_1] =
+                {
+                    .event_control = IOPORT_EVENT_CONTROL_DISABLE,
+                    .direction = IOPORT_EVENT_DIRECTION_OUTPUT,
+                    .port_num  = (uint16_t)BSP_IO_PORT_16_PIN_0,
+                    .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW,
+                    .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE
+                },
+                .single_port_cfg[IOPORT_SINGLE_PORT_2] =
+                {
+                    .event_control = IOPORT_EVENT_CONTROL_DISABLE,
+                    .direction = IOPORT_EVENT_DIRECTION_OUTPUT,
+                    .port_num  = (uint16_t)BSP_IO_PORT_16_PIN_0,
+                    .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW,
+                    .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE
+                },
+                .single_port_cfg[IOPORT_SINGLE_PORT_3] =
+                {
+                    .event_control = IOPORT_EVENT_CONTROL_DISABLE,
+                    .direction = IOPORT_EVENT_DIRECTION_OUTPUT,
+                    .port_num  = (uint16_t)BSP_IO_PORT_16_PIN_0,
+                    .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW,
+                    .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE
+                }
+            };
+
+ioport_instance_ctrl_t g_ioport_ctrl;
+
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg
+        };
+void g_common_init(void) {
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/common_data.h b/projects/etherkit_ethercat_cherryecat/rzn_gen/common_data.h
new file mode 100644
index 00000000..e2eb7083
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/common_data.h
@@ -0,0 +1,16 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/hal_data.c b/projects/etherkit_ethercat_cherryecat/rzn_gen/hal_data.c
new file mode 100644
index 00000000..e3665cb1
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/hal_data.c
@@ -0,0 +1,791 @@
+/* generated HAL source file - do not edit */
+#include "hal_data.h"
+
+
+#if defined(BSP_MCU_GROUP_RZT2M) || defined(BSP_MCU_GROUP_RZN2L)
+#define ETHER_BUFFER_PLACE_IN_SECTION BSP_PLACE_IN_SECTION(".noncache_buffer.eth")
+#else
+#define ETHER_BUFFER_PLACE_IN_SECTION
+#endif
+
+mtu3_instance_ctrl_t g_mtu3_ctrl;
+#if 0
+const mtu3_extended_uvw_cfg_t g_mtu3_uvw_extend =
+{
+    .tgru_val                       = 0x0000,
+    .tgrv_val                       = 0x0000,
+    .tgrw_val                       = 0x0000,
+    .mtu3_clk_div_u                 = MTU3_DIV_UVW_PCLKH_1,
+    .mtu3_clk_div_v                 = MTU3_DIV_UVW_PCLKH_1,
+    .mtu3_clk_div_w                 = MTU3_DIV_UVW_PCLKH_1,
+    .output_pin_level_u             = MTU3_IO_PIN_LEVEL_UVW_NO_FUNC,
+    .output_pin_level_v             = MTU3_IO_PIN_LEVEL_UVW_NO_FUNC,
+    .output_pin_level_w             = MTU3_IO_PIN_LEVEL_UVW_NO_FUNC,
+    .noise_filter_mtioc_setting_uvw = (mtu3_noise_filter_setting_uvw_t)(MTU3_NOISE_FILTER_UVW_DISABLE),
+    .noise_filter_mtioc_clk_uvw     = MTU3_NOISE_FILTER_CLOCK_PCLKH_DIV_1,
+
+#if defined(VECTOR_NUMBER_TGIU5)
+    .capture_u_ipl                  = (BSP_IRQ_DISABLED),
+    .capture_u_irq                  = VECTOR_NUMBER_TGIU5,
+    .capture_u_select_event         = (bsp_irq_gpt_selected_event_t)0,
+#elif defined(VECTOR_NUMBER_GPT_GPT00_0_INT)
+    .capture_u_ipl                  = FSP_NOT_DEFINED,
+    .capture_u_irq                  = VECTOR_NUMBER_GPT_GPT00_0_INT,
+    .capture_u_select_event         = BSP_IRQ_GPT_SELECTED_EVENT_TCIU5,
+#else
+    .capture_u_ipl                  = (BSP_IRQ_DISABLED),
+    .capture_u_irq                  = FSP_INVALID_VECTOR,
+    .capture_u_select_event         = (bsp_irq_gpt_selected_event_t)0,
+#endif
+#if defined(VECTOR_NUMBER_TGIV5)
+    .capture_v_ipl                  = (BSP_IRQ_DISABLED),
+    .capture_v_irq                  = VECTOR_NUMBER_TGIV5,
+    .capture_v_select_event         = (bsp_irq_gpt_selected_event_t)0,
+#elif defined(VECTOR_NUMBER_GPT_GPT00_0_INT)
+    .capture_v_ipl                  = FSP_NOT_DEFINED,
+    .capture_v_irq                  = VECTOR_NUMBER_GPT_GPT00_0_INT,
+    .capture_v_select_event         = BSP_IRQ_GPT_SELECTED_EVENT_TCIV5,
+#else
+    .capture_v_ipl                  = (BSP_IRQ_DISABLED),
+    .capture_v_irq                  = FSP_INVALID_VECTOR,
+    .capture_v_select_event         = (bsp_irq_gpt_selected_event_t)0,
+#endif
+#if defined(VECTOR_NUMBER_TGIW5)
+    .capture_w_ipl                  = (BSP_IRQ_DISABLED),
+    .capture_w_irq                  = VECTOR_NUMBER_TGIW5,
+    .capture_w_select_event         = (bsp_irq_gpt_selected_event_t)0,
+#elif defined(VECTOR_NUMBER_GPT_GPT00_0_INT)
+    .capture_w_ipl                  = FSP_NOT_DEFINED,
+    .capture_w_irq                  = VECTOR_NUMBER_GPT_GPT00_0_INT,
+    .capture_w_select_event         = BSP_IRQ_GPT_SELECTED_EVENT_TGIW5,
+#else
+    .capture_w_ipl                  = (BSP_IRQ_DISABLED),
+    .capture_w_irq                  = FSP_INVALID_VECTOR,
+    .capture_w_select_event         = (bsp_irq_gpt_selected_event_t)0,
+#endif
+};
+const mtu3_extended_pwm_cfg_t g_mtu3_pwm_extend =
+{
+    .interrupt_skip_mode_a          = MTU3_INTERRUPT_SKIP_MODE_1,
+    .interrupt_skip_mode_b          = MTU3_INTERRUPT_SKIP_MODE_1,
+    .adc_a_compare_match            = 0x0000,
+    .adc_b_compare_match            = 0x0000,
+    .interrupt_skip_count_tciv4     = MTU3_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_count_tgia3     = MTU3_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_count_tciv7     = MTU3_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_count_tgia6     = MTU3_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_count_tgr4an_bn = MTU3_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_count_tgr7an_bn = MTU3_INTERRUPT_SKIP_COUNT_0,
+};
+#endif
+const mtu3_extended_cfg_t g_mtu3_extend =
+{
+    .tgra_val            = 0xFFFF,
+    .tgrb_val            = 0xFFFF,
+    .tgrc_val            = 0xFFFF,
+    .tgrd_val            = 0xFFFF,
+    .mtu3_clk_div        = MTU3_DIV_PCLKH_1,
+    .clk_edge            = MTU3_CLOCK_EDGE_RISING,
+    .mtu3_clear          = MTU3_TCNT_CLEAR_DISABLE,
+    .mtioc_ctrl_setting  = { .output_pin_level_a = MTU3_IO_PIN_LEVEL_NO_OUTPUT,
+                             .output_pin_level_b = MTU3_IO_PIN_LEVEL_NO_OUTPUT
+                           },
+    .bit_mode            = MTU3_BIT_MODE_NORMAL_16BIT,
+    .counting_mode       = MTU3_PHASE_COUNTING_MODE_NONE,
+    .external_clock      = MTU3_EXTERNAL_CLOCK_MTCLKA_B,
+#if defined(VECTOR_NUMBER_TGIA0)
+    .capture_a_ipl       = (BSP_IRQ_DISABLED),
+    .capture_a_irq       = VECTOR_NUMBER_TGIA0,
+    .capture_a_source_select = BSP_IRQ_DISABLED,
+    .capture_a_select_event  = (bsp_irq_gpt_selected_event_t)0,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .capture_a_ipl       = FSP_NOT_DEFINED,
+    .capture_a_irq       = VECTOR_NUMBER_GPT00_0_INT,
+    .capture_a_source_select = ,
+    .capture_a_select_event  = BSP_IRQ_GPT_SELECTED_EVENT_TGIA0,
+#else
+    .capture_a_ipl       = (BSP_IRQ_DISABLED),
+    .capture_a_irq       = FSP_INVALID_VECTOR,
+    .capture_a_source_select = BSP_IRQ_DISABLED,
+    .capture_a_select_event = (bsp_irq_gpt_selected_event_t)0,
+#endif
+#if defined(VECTOR_NUMBER_TGIB0)
+    .capture_b_ipl       = (BSP_IRQ_DISABLED),
+    .capture_b_irq       = VECTOR_NUMBER_TGIB0,
+    .capture_b_source_select = BSP_IRQ_DISABLED,
+    .capture_b_select_event  = (bsp_irq_gpt_selected_event_t)0,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .capture_b_ipl       = FSP_NOT_DEFINED,
+    .capture_b_irq       = VECTOR_NUMBER_GPT00_0_INT,
+    .capture_b_source_select = ,
+    .capture_b_select_event  = BSP_IRQ_GPT_SELECTED_EVENT_TGIB0,
+#else
+    .capture_b_ipl       = (BSP_IRQ_DISABLED),
+    .capture_b_irq       = FSP_INVALID_VECTOR,
+    .capture_b_source_select = BSP_IRQ_DISABLED,
+    .capture_b_select_event  = (bsp_irq_gpt_selected_event_t)0,
+#endif
+    .noise_filter_mtioc_setting  = (mtu3_noise_filter_setting_t)( MTU3_NOISE_FILTER_DISABLE),
+    .noise_filter_mtioc_clk      = MTU3_NOISE_FILTER_CLOCK_PCLKH_DIV_1,
+    .noise_filter_mtclk_setting  = (mtu3_noise_filter_mtclk_setting_t)( MTU3_NOISE_FILTER_EXTERNAL_DISABLE),
+    .noise_filter_mtclk_clk      = MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_1,
+    .adc_request_enable          = 0,
+    .mtu3_elc_event_operation    ={.mtu0_elc_operation = MTU3_EVENT_OPERATION_SELECT_DISABLE,
+                                   .mtu3_elc_operation = MTU3_EVENT_OPERATION_SELECT_DISABLE,
+                                   .mtu4_elc_operation = MTU3_EVENT_OPERATION_SELECT_DISABLE
+                                  },
+#if 0
+    .p_uvw_cfg                   = &g_mtu3_uvw_extend,
+    .p_pwm_cfg                   = &g_mtu3_pwm_extend,
+#else
+    .p_uvw_cfg                   = NULL,
+    .p_pwm_cfg                   = NULL,
+#endif
+
+#if defined(VECTOR_NUMBER_TCIV0)
+    .cycle_end_source_select = BSP_IRQ_DISABLED,
+    .cycle_end_select_event  = (bsp_irq_gpt_selected_event_t)0,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .cycle_end_source_select = ,
+    .cycle_end_select_event  = BSP_IRQ_GPT_SELECTED_EVENT_TCIV0,
+#else
+    .cycle_end_source_select = BSP_IRQ_DISABLED,
+    .cycle_end_select_event  = (bsp_irq_gpt_selected_event_t)0,
+#endif
+};
+const timer_cfg_t g_mtu3_cfg =
+{
+    .mode                = TIMER_MODE_PERIODIC,
+    .channel             = 0,
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+    .p_callback          = NULL,
+#else
+    .p_callback          = g_mtu3_callback,
+#endif
+    .p_context           = NULL,
+    .p_extend            = &g_mtu3_extend,
+#if defined(VECTOR_NUMBER_TCIV0)
+    .cycle_end_ipl       = (8),
+    .cycle_end_irq       = VECTOR_NUMBER_TCIV0,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .cycle_end_ipl       = FSP_NOT_DEFINED,
+    .cycle_end_irq       = VECTOR_NUMBER_GPT00_0_INT,
+#else
+    .cycle_end_ipl       = (8),
+    .cycle_end_irq       = FSP_INVALID_VECTOR,
+#endif
+};
+/* Instance structure to use this module. */
+const timer_instance_t g_mtu3 =
+{
+    .p_ctrl        = &g_mtu3_ctrl,
+    .p_cfg         = &g_mtu3_cfg,
+    .p_api         = &g_timer_on_mtu3
+};
+gpt_instance_ctrl_t g_timer0_ctrl;
+#if 0
+const gpt_extended_pwm_cfg_t g_timer0_pwm_extend =
+{
+#if defined(VECTOR_NUMBER_GPT0_UDF)
+    .trough_ipl          = (BSP_IRQ_DISABLED),
+    .trough_irq          = VECTOR_NUMBER_GPT0_UDF,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .trough_ipl          = FSP_NOT_DEFINED,
+    .trough_irq          = VECTOR_NUMBER_GPT00_0_INT,
+#else
+    .trough_ipl          = (BSP_IRQ_DISABLED),
+    .trough_irq          = FSP_INVALID_VECTOR,
+#endif
+    .poeg_link           = GPT_POEG_LINK_POEG0,
+    .output_disable      =  GPT_OUTPUT_DISABLE_NONE,
+    .adc_trigger         =  GPT_ADC_TRIGGER_NONE,
+    .dead_time_count_up  = 0,
+    .dead_time_count_down = 0,
+    .adc_a_compare_match = 0,
+    .adc_b_compare_match = 0,
+    .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE,
+    .interrupt_skip_count  = GPT_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_adc    = GPT_INTERRUPT_SKIP_ADC_NONE,
+    .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
+    .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
+    .interrupt_skip_source_ext1 = GPT_INTERRUPT_SKIP_SOURCE_NONE,
+    .interrupt_skip_count_ext1  = GPT_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_source_ext2 = GPT_INTERRUPT_SKIP_SOURCE_NONE,
+    .interrupt_skip_count_ext2  = GPT_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_func_ovf    = GPT_INTERRUPT_SKIP_SELECT_NONE,
+    .interrupt_skip_func_unf    = GPT_INTERRUPT_SKIP_SELECT_NONE,
+    .interrupt_skip_func_adc_a  = GPT_INTERRUPT_SKIP_SELECT_NONE,
+    .interrupt_skip_func_adc_b  = GPT_INTERRUPT_SKIP_SELECT_NONE,
+};
+#endif
+const gpt_extended_cfg_t g_timer0_extend =
+{
+    .gtioca = { .output_enabled = false,
+                .stop_level     = GPT_PIN_LEVEL_LOW
+              },
+    .gtiocb = { .output_enabled = false,
+                .stop_level     = GPT_PIN_LEVEL_LOW
+              },
+    .start_source        = (gpt_source_t) ( GPT_SOURCE_NONE),
+    .stop_source         = (gpt_source_t) ( GPT_SOURCE_NONE),
+    .clear_source        = (gpt_source_t) ( GPT_SOURCE_NONE),
+#if (0 == (0))
+    .count_up_source     = (gpt_source_t) ( GPT_SOURCE_NONE),
+    .count_down_source   = (gpt_source_t) ( GPT_SOURCE_NONE),
+#else
+    .count_up_source     = (gpt_source_t) ((GPT_PHASE_COUNTING_MODE_1_UP | (GPT_PHASE_COUNTING_MODE_1_DN << 16)) & 0x000FFFFU),
+    .count_down_source   = (gpt_source_t) (((GPT_PHASE_COUNTING_MODE_1_UP | (GPT_PHASE_COUNTING_MODE_1_DN << 16)) & 0xFFFF0000U) >> 16),
+#endif
+    .capture_a_source    = (gpt_source_t) ( GPT_SOURCE_NONE),
+    .capture_b_source    = (gpt_source_t) ( GPT_SOURCE_NONE),
+#if defined(VECTOR_NUMBER_GPT0_CCMPA)
+    .capture_a_ipl       = (BSP_IRQ_DISABLED),
+    .capture_a_irq       = VECTOR_NUMBER_GPT0_CCMPA,
+    .capture_a_source_select = BSP_IRQ_DISABLED,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .capture_a_ipl       = FSP_NOT_DEFINED,
+    .capture_a_irq       = VECTOR_NUMBER_GPT00_0_INT,
+    .capture_a_source_select = ,
+#else
+    .capture_a_ipl       = (BSP_IRQ_DISABLED),
+    .capture_a_irq       = FSP_INVALID_VECTOR,
+    .capture_a_source_select = BSP_IRQ_DISABLED,
+#endif
+#if defined(VECTOR_NUMBER_GPT0_CCMPB)
+    .capture_b_irq       = VECTOR_NUMBER_GPT0_CCMPB,
+    .capture_b_ipl       = (BSP_IRQ_DISABLED),
+    .capture_b_source_select = BSP_IRQ_DISABLED,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .capture_b_irq       = VECTOR_NUMBER_GPT00_0_INT,
+    .capture_b_ipl       = FSP_NOT_DEFINED,
+    .capture_b_source_select = ,
+#else
+    .capture_b_ipl       = (BSP_IRQ_DISABLED),
+    .capture_b_irq       = FSP_INVALID_VECTOR,
+    .capture_b_source_select = BSP_IRQ_DISABLED,
+#endif
+    .capture_filter_gtioca       = GPT_CAPTURE_FILTER_NONE,
+    .capture_filter_gtiocb       = GPT_CAPTURE_FILTER_NONE,
+#if 0
+    .p_pwm_cfg                   = &g_timer0_pwm_extend,
+#else
+    .p_pwm_cfg                   = NULL,
+#endif
+#if defined(VECTOR_NUMBER_GPT0_DTE)
+    .dead_time_ipl       = (BSP_IRQ_DISABLED),
+    .dead_time_irq       = VECTOR_NUMBER_GPT0_DTE,
+    .dead_time_error_source_select = BSP_IRQ_DISABLED,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .dead_time_ipl       = FSP_NOT_DEFINED,
+    .dead_time_irq       = VECTOR_NUMBER_GPT00_0_INT,
+    .dead_time_error_source_select = ,
+#else
+    .dead_time_ipl       = (BSP_IRQ_DISABLED),
+    .dead_time_irq       = FSP_INVALID_VECTOR,
+    .dead_time_error_source_select = BSP_IRQ_DISABLED,
+#endif
+    .icds                = 0,
+#if (2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE)
+ #if (1U == BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE)
+    .gtioc_isel          = 0,
+ #endif
+#endif
+#if defined(VECTOR_NUMBER_GPT0_OVF)
+    .cycle_end_source_select = BSP_IRQ_DISABLED,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .cycle_end_source_select = ,
+#else
+    .cycle_end_source_select = BSP_IRQ_DISABLED,
+#endif
+#if defined(VECTOR_NUMBER_GPT0_UDF)
+    .trough_source_select = BSP_IRQ_DISABLED,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .trough_source_select = ,
+#else
+    .trough_source_select  = BSP_IRQ_DISABLED,
+#endif
+};
+const timer_cfg_t g_timer0_cfg =
+{
+    .mode                = TIMER_MODE_PERIODIC,
+    /* Actual period: 10.73741824 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)0,
+    .channel             = GPT_CHANNEL_UNIT0_0,
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+    .p_callback          = NULL,
+#else
+    .p_callback          = timer0_esc_callback,
+#endif
+    .p_context           = NULL,
+    .p_extend            = &g_timer0_extend,
+#if defined(VECTOR_NUMBER_GPT0_OVF)
+    .cycle_end_ipl       = (10),
+    .cycle_end_irq       = VECTOR_NUMBER_GPT0_OVF,
+#elif defined(VECTOR_NUMBER_GPT00_0_INT)
+    .cycle_end_ipl       = FSP_NOT_DEFINED,
+    .cycle_end_irq       = VECTOR_NUMBER_GPT00_0_INT,
+#else
+    .cycle_end_ipl       = (10),
+    .cycle_end_irq       = FSP_INVALID_VECTOR,
+#endif
+};
+/* Instance structure to use this module. */
+const timer_instance_t g_timer0 =
+{
+    .p_ctrl        = &g_timer0_ctrl,
+    .p_cfg         = &g_timer0_cfg,
+    .p_api         = &g_timer_on_gpt
+};
+ethsw_instance_ctrl_t g_ethsw0_ctrl;
+
+const ethsw_extend_cfg_t g_ethsw0_extend_cfg =
+            {
+    .specific_tag    = ETHSW_SPECIFIC_TAG_DISABLE,
+    .specific_tag_id = 0xE001,
+    .phylink         = ETHSW_PHYLINK_DISABLE,
+
+};
+
+const ether_switch_cfg_t g_ethsw0_cfg =
+{
+    .channel    = 0,
+
+#if defined(VECTOR_NUMBER_ETHSW_INTR)
+    .irq        = VECTOR_NUMBER_ETHSW_INTR,
+#else
+    .irq        = FSP_INVALID_VECTOR,
+#endif
+    .ipl        = (12),
+    .p_callback = gmac_callback_ethsw,
+    .p_context  = &g_ether0_ctrl,
+    .p_extend   = &g_ethsw0_extend_cfg
+};
+
+/* Instance structure to use this module. */
+const ether_switch_instance_t g_ethsw0 =
+{
+    .p_ctrl        = &g_ethsw0_ctrl,
+    .p_cfg         = &g_ethsw0_cfg,
+    .p_api         = &g_ether_switch_on_ethsw
+};
+ether_selector_instance_ctrl_t g_ether_selector2_ctrl;
+
+const ether_selector_cfg_t g_ether_selector2_cfg =
+{
+    .channel                   = 2,
+    .phylink                   = ETHER_SELECTOR_PHYLINK_POLARITY_LOW,
+    .interface                 = ETHER_SELECTOR_INTERFACE_RGMII,
+    .speed                     = ETHER_SELECTOR_SPEED_100_MBPS,
+    .duplex                    = ETHER_SELECTOR_DUPLEX_FULL,
+    .ref_clock                 = ETHER_SELECTOR_REF_CLOCK_INPUT,
+    .p_extend                  = NULL,
+};
+
+/* Instance structure to use this module. */
+const ether_selector_instance_t g_ether_selector2 =
+{
+    .p_ctrl        = &g_ether_selector2_ctrl,
+    .p_cfg         = &g_ether_selector2_cfg,
+    .p_api         = &g_ether_selector_on_ether_selector
+};
+ether_phy_instance_ctrl_t g_ether_phy2_ctrl;
+
+const ether_phy_extend_cfg_t g_ether_phy2_extend =
+{
+    .port_type           = ETHER_PHY_PORT_TYPE_ETHERNET,
+    .mdio_type           = ETHER_PHY_MDIO_GMAC,
+    .bps                 = ETHER_PHY_SPEED_100,
+    .duplex              = ETHER_PHY_DUPLEX_FULL,
+    .auto_negotiation    = ETHER_PHY_AUTO_NEGOTIATION_ON,
+    .phy_reset_pin       = BSP_IO_PORT_13_PIN_4,
+    .phy_reset_time      = 15000,
+    .p_selector_instance = (ether_selector_instance_t *)&g_ether_selector2,
+    .p_target_init       = ether_phy_targets_initialize_rtl8211_rgmii,
+};
+
+const ether_phy_cfg_t g_ether_phy2_cfg =
+{
+
+    .channel                   = 2,
+    .phy_lsi_address           = 3,
+    .phy_reset_wait_time       = 0x00020000,
+    .mii_bit_access_wait_time  = 0,                         // Unused
+    .phy_lsi_type              = ETHER_PHY_LSI_TYPE_CUSTOM,
+    .flow_control              = ETHER_PHY_FLOW_CONTROL_DISABLE,
+    .mii_type                  = (ether_phy_mii_type_t) 0,  // Unused
+    .p_context                 = NULL,
+    .p_extend                  = &g_ether_phy2_extend
+};
+
+/* Instance structure to use this module. */
+const ether_phy_instance_t g_ether_phy2 =
+{
+    .p_ctrl        = &g_ether_phy2_ctrl,
+    .p_cfg         = &g_ether_phy2_cfg,
+    .p_api         = &g_ether_phy_on_ether_phy
+};
+ether_selector_instance_ctrl_t g_ether_selector1_ctrl;
+
+const ether_selector_cfg_t g_ether_selector1_cfg =
+{
+    .channel                   = 1,
+    .phylink                   = ETHER_SELECTOR_PHYLINK_POLARITY_LOW,
+    .interface                 = ETHER_SELECTOR_INTERFACE_RGMII,
+    .speed                     = ETHER_SELECTOR_SPEED_100_MBPS,
+    .duplex                    = ETHER_SELECTOR_DUPLEX_FULL,
+    .ref_clock                 = ETHER_SELECTOR_REF_CLOCK_INPUT,
+    .p_extend                  = NULL,
+};
+
+/* Instance structure to use this module. */
+const ether_selector_instance_t g_ether_selector1 =
+{
+    .p_ctrl        = &g_ether_selector1_ctrl,
+    .p_cfg         = &g_ether_selector1_cfg,
+    .p_api         = &g_ether_selector_on_ether_selector
+};
+ether_phy_instance_ctrl_t g_ether_phy1_ctrl;
+
+const ether_phy_extend_cfg_t g_ether_phy1_extend =
+{
+    .port_type           = ETHER_PHY_PORT_TYPE_ETHERNET,
+    .mdio_type           = ETHER_PHY_MDIO_GMAC,
+    .bps                 = ETHER_PHY_SPEED_100,
+    .duplex              = ETHER_PHY_DUPLEX_FULL,
+    .auto_negotiation    = ETHER_PHY_AUTO_NEGOTIATION_ON,
+    .phy_reset_pin       = BSP_IO_PORT_13_PIN_4,
+    .phy_reset_time      = 15000,
+    .p_selector_instance = (ether_selector_instance_t *)&g_ether_selector1,
+    .p_target_init       = ether_phy_targets_initialize_rtl8211_rgmii,
+};
+
+const ether_phy_cfg_t g_ether_phy1_cfg =
+{
+
+    .channel                   = 1,
+    .phy_lsi_address           = 2,
+    .phy_reset_wait_time       = 0x00020000,
+    .mii_bit_access_wait_time  = 0,                         // Unused
+    .phy_lsi_type              = ETHER_PHY_LSI_TYPE_CUSTOM,
+    .flow_control              = ETHER_PHY_FLOW_CONTROL_DISABLE,
+    .mii_type                  = (ether_phy_mii_type_t) 0,  // Unused
+    .p_context                 = NULL,
+    .p_extend                  = &g_ether_phy1_extend
+};
+
+/* Instance structure to use this module. */
+const ether_phy_instance_t g_ether_phy1 =
+{
+    .p_ctrl        = &g_ether_phy1_ctrl,
+    .p_cfg         = &g_ether_phy1_cfg,
+    .p_api         = &g_ether_phy_on_ether_phy
+};
+ether_selector_instance_ctrl_t g_ether_selector0_ctrl;
+
+const ether_selector_cfg_t g_ether_selector0_cfg =
+{
+    .channel                   = 0,
+    .phylink                   = ETHER_SELECTOR_PHYLINK_POLARITY_LOW,
+    .interface                 = ETHER_SELECTOR_INTERFACE_RGMII,
+    .speed                     = ETHER_SELECTOR_SPEED_100_MBPS,
+    .duplex                    = ETHER_SELECTOR_DUPLEX_FULL,
+    .ref_clock                 = ETHER_SELECTOR_REF_CLOCK_INPUT,
+    .p_extend                  = NULL,
+};
+
+/* Instance structure to use this module. */
+const ether_selector_instance_t g_ether_selector0 =
+{
+    .p_ctrl        = &g_ether_selector0_ctrl,
+    .p_cfg         = &g_ether_selector0_cfg,
+    .p_api         = &g_ether_selector_on_ether_selector
+};
+ether_phy_instance_ctrl_t g_ether_phy0_ctrl;
+
+const ether_phy_extend_cfg_t g_ether_phy0_extend =
+{
+    .port_type           = ETHER_PHY_PORT_TYPE_ETHERNET,
+    .mdio_type           = ETHER_PHY_MDIO_GMAC,
+    .bps                 = ETHER_PHY_SPEED_100,
+    .duplex              = ETHER_PHY_DUPLEX_FULL,
+    .auto_negotiation    = ETHER_PHY_AUTO_NEGOTIATION_ON,
+    .phy_reset_pin       = BSP_IO_PORT_13_PIN_4,
+    .phy_reset_time      = 15000,
+    .p_selector_instance = (ether_selector_instance_t *)&g_ether_selector0,
+    .p_target_init       = ether_phy_targets_initialize_rtl8211_rgmii,
+};
+
+const ether_phy_cfg_t g_ether_phy0_cfg =
+{
+
+    .channel                   = 0,
+    .phy_lsi_address           = 1,
+    .phy_reset_wait_time       = 0x00020000,
+    .mii_bit_access_wait_time  = 0,                         // Unused
+    .phy_lsi_type              = ETHER_PHY_LSI_TYPE_CUSTOM,
+    .flow_control              = ETHER_PHY_FLOW_CONTROL_DISABLE,
+    .mii_type                  = (ether_phy_mii_type_t) 0,  // Unused
+    .p_context                 = NULL,
+    .p_extend                  = &g_ether_phy0_extend
+};
+
+/* Instance structure to use this module. */
+const ether_phy_instance_t g_ether_phy0 =
+{
+    .p_ctrl        = &g_ether_phy0_ctrl,
+    .p_cfg         = &g_ether_phy0_cfg,
+    .p_api         = &g_ether_phy_on_ether_phy
+};
+const ether_phy_instance_t *g_ether0_phy_instance[BSP_FEATURE_GMAC_MAX_PORTS] =
+            {
+#define FSP_NOT_DEFINED (1)
+#if (FSP_NOT_DEFINED == g_ether_phy0)
+                    NULL,
+#else
+                    &g_ether_phy0,
+#endif
+#if (FSP_NOT_DEFINED == g_ether_phy1)
+                    NULL,
+#else
+                    &g_ether_phy1,
+#endif
+#if (FSP_NOT_DEFINED == g_ether_phy2)
+                    NULL,
+#else
+                    &g_ether_phy2,
+#endif
+#undef FSP_NOT_DEFINED
+            };
+
+            gmac_instance_ctrl_t g_ether0_ctrl;
+
+#define ETHER_MAC_ADDRESS_INVALID (0)
+#define ETHER_MAC_ADDRESS_VALID   (1)
+
+            uint8_t g_ether0_mac_address[6] = { 0x00,0x11,0x22,0x33,0x44,0x55 };
+
+#if ETHER_MAC_ADDRESS_INVALID == ETHER_MAC_ADDRESS_VALID
+            uint8_t g_ether0_mac_address_1[6] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+#endif
+
+#if ETHER_MAC_ADDRESS_INVALID == ETHER_MAC_ADDRESS_VALID
+            uint8_t g_ether0_mac_address_2[6] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+#endif
+
+            __attribute__((__aligned__(16))) gmac_instance_descriptor_t g_ether0_tx_descriptors[8] ETHER_BUFFER_PLACE_IN_SECTION;
+            __attribute__((__aligned__(16))) gmac_instance_descriptor_t g_ether0_rx_descriptors[8] ETHER_BUFFER_PLACE_IN_SECTION;
+
+            __attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer0[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer1[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer2[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer3[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer4[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer5[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer6[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer7[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer8[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer9[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer10[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer11[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer12[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer13[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer14[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+__attribute__((__aligned__(32)))uint8_t g_ether0_ether_buffer15[1524]ETHER_BUFFER_PLACE_IN_SECTION;
+
+
+uint8_t *pp_g_ether0_ether_buffers[( 8 + 8 )] = {
+            (uint8_t *) &g_ether0_ether_buffer0[0],
+(uint8_t *) &g_ether0_ether_buffer1[0],
+(uint8_t *) &g_ether0_ether_buffer2[0],
+(uint8_t *) &g_ether0_ether_buffer3[0],
+(uint8_t *) &g_ether0_ether_buffer4[0],
+(uint8_t *) &g_ether0_ether_buffer5[0],
+(uint8_t *) &g_ether0_ether_buffer6[0],
+(uint8_t *) &g_ether0_ether_buffer7[0],
+(uint8_t *) &g_ether0_ether_buffer8[0],
+(uint8_t *) &g_ether0_ether_buffer9[0],
+(uint8_t *) &g_ether0_ether_buffer10[0],
+(uint8_t *) &g_ether0_ether_buffer11[0],
+(uint8_t *) &g_ether0_ether_buffer12[0],
+(uint8_t *) &g_ether0_ether_buffer13[0],
+(uint8_t *) &g_ether0_ether_buffer14[0],
+(uint8_t *) &g_ether0_ether_buffer15[0],
+
+            };
+
+            const gmac_extend_cfg_t g_ether0_extend_cfg =
+            {
+                .p_rx_descriptors        = g_ether0_rx_descriptors,
+                .p_tx_descriptors        = g_ether0_tx_descriptors,
+
+                .phylink                 = GMAC_PHYLINK_DISABLE,
+
+#if defined(VECTOR_NUMBER_GMAC_PMT)
+                .pmt_irq                 = VECTOR_NUMBER_GMAC_PMT,
+#else
+                .pmt_irq                 = FSP_INVALID_VECTOR,
+#endif
+                .pmt_interrupt_priority  = (12),
+
+                .pp_phy_instance         = (ether_phy_instance_t const *(*)[BSP_FEATURE_GMAC_MAX_PORTS]) g_ether0_phy_instance,
+
+#if defined(GMAC_IMPLEMENT_ETHSW)
+                .p_ethsw_instance        = &g_ethsw0,
+#endif // GMAC_IMPLEMENT_ETHSW
+
+#if ETHER_MAC_ADDRESS_INVALID == ETHER_MAC_ADDRESS_VALID
+                .p_mac_address1          = g_ether0_mac_address_1,
+#else
+                .p_mac_address1          = NULL,
+#endif
+#if ETHER_MAC_ADDRESS_INVALID == ETHER_MAC_ADDRESS_VALID
+                .p_mac_address2          = g_ether0_mac_address_2
+#else
+                .p_mac_address2          = NULL,
+#endif
+            };
+
+            const ether_cfg_t g_ether0_cfg =
+            {
+                .channel                 = 0,
+                .zerocopy                = ETHER_ZEROCOPY_ENABLE,
+                .multicast               = (ether_multicast_t) 0,    // Unused
+                .promiscuous             = ETHER_PROMISCUOUS_ENABLE,
+                .flow_control            = ETHER_FLOW_CONTROL_DISABLE,
+                .broadcast_filter        = 0, // Unused
+                .p_mac_address           = g_ether0_mac_address,
+
+                .num_tx_descriptors      = 8,
+                .num_rx_descriptors      = 8,
+
+                .pp_ether_buffers        = pp_g_ether0_ether_buffers,
+
+                .ether_buffer_size       = 1524,
+
+#if defined(VECTOR_NUMBER_GMAC_SBD)
+                .irq                     = VECTOR_NUMBER_GMAC_SBD,
+#else
+                .irq                     = FSP_INVALID_VECTOR,
+#endif
+                .interrupt_priority      = (12),
+
+                .p_callback              = user_ether0_callback,
+                .p_ether_phy_instance    = (ether_phy_instance_t *) 0, // Unused
+                .p_context               = NULL,
+                .p_extend                = &g_ether0_extend_cfg
+            };
+
+/* Instance structure to use this module. */
+const ether_instance_t g_ether0 =
+{
+    .p_ctrl        = &g_ether0_ctrl,
+    .p_cfg         = &g_ether0_cfg,
+    .p_api         = &g_ether_on_gmac
+};
+sci_uart_instance_ctrl_t     g_uart0_ctrl;
+
+            #define FSP_NOT_DEFINED (1)
+            #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
+
+            /* If the transfer module is DMAC, define a DMAC transfer callback. */
+            extern void sci_uart_tx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl);
+
+            void g_uart0_tx_transfer_callback (transfer_callback_args_t * p_args)
+            {
+                FSP_PARAMETER_NOT_USED(p_args);
+                sci_uart_tx_dmac_callback(&g_uart0_ctrl);
+            }
+            #endif
+
+            #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
+
+            /* If the transfer module is DMAC, define a DMAC transfer callback. */
+            extern void sci_uart_rx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl);
+
+            void g_uart0_rx_transfer_callback (transfer_callback_args_t * p_args)
+            {
+                FSP_PARAMETER_NOT_USED(p_args);
+                sci_uart_rx_dmac_callback(&g_uart0_ctrl);
+            }
+            #endif
+            #undef FSP_NOT_DEFINED
+
+            sci_baud_setting_t           g_uart0_baud_setting =
+            {
+                /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 51, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false
+            };
+
+            /** UART extended configuration for UARTonSCI HAL driver */
+            const sci_uart_extended_cfg_t g_uart0_cfg_extend =
+            {
+                .clock                = SCI_UART_CLOCK_INT,
+                .rx_edge_start          = SCI_UART_START_BIT_FALLING_EDGE,
+                .noise_cancel         = SCI_UART_NOISE_CANCELLATION_DISABLE,
+                .rx_fifo_trigger        = SCI_UART_RX_FIFO_TRIGGER_MAX,
+                .p_baud_setting         = &g_uart0_baud_setting,
+#if 1
+                .clock_source           = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK,
+#else
+                .clock_source           = SCI_UART_CLOCK_SOURCE_PCLKM,
+#endif
+                .flow_control           = SCI_UART_FLOW_CONTROL_RTS,
+                #if 0xFF != 0xFF
+                .flow_control_pin       = BSP_IO_PORT_FF_PIN_0xFF,
+                #else
+                .flow_control_pin       = (bsp_io_port_pin_t) UINT16_MAX,
+                #endif
+                .rs485_setting          = {
+                    .enable = SCI_UART_RS485_DISABLE,
+                    .polarity = SCI_UART_RS485_DE_POLARITY_HIGH,
+                    .assertion_time = 1,
+                    .negation_time = 1,
+                },
+            };
+
+            /** UART interface configuration */
+            const uart_cfg_t g_uart0_cfg =
+            {
+                .channel             = 0,
+                .data_bits           = UART_DATA_BITS_8,
+                .parity              = UART_PARITY_OFF,
+                .stop_bits           = UART_STOP_BITS_1,
+                .p_callback          = user_uart0_callback,
+                .p_context           = NULL,
+                .p_extend            = &g_uart0_cfg_extend,
+                .p_transfer_tx       = g_uart0_P_TRANSFER_TX,
+                .p_transfer_rx       = g_uart0_P_TRANSFER_RX,
+                .rxi_ipl             = (12),
+                .txi_ipl             = (12),
+                .tei_ipl             = (12),
+                .eri_ipl             = (12),
+#if defined(VECTOR_NUMBER_SCI0_RXI)
+                .rxi_irq             = VECTOR_NUMBER_SCI0_RXI,
+#else
+                .rxi_irq             = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_SCI0_TXI)
+                .txi_irq             = VECTOR_NUMBER_SCI0_TXI,
+#else
+                .txi_irq             = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_SCI0_TEI)
+                .tei_irq             = VECTOR_NUMBER_SCI0_TEI,
+#else
+                .tei_irq             = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_SCI0_ERI)
+                .eri_irq             = VECTOR_NUMBER_SCI0_ERI,
+#else
+                .eri_irq             = FSP_INVALID_VECTOR,
+#endif
+            };
+
+/* Instance structure to use this module. */
+const uart_instance_t g_uart0 =
+{
+    .p_ctrl        = &g_uart0_ctrl,
+    .p_cfg         = &g_uart0_cfg,
+    .p_api         = &g_uart_on_sci
+};
+void g_hal_init(void) {
+g_common_init();
+}
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/hal_data.h b/projects/etherkit_ethercat_cherryecat/rzn_gen/hal_data.h
new file mode 100644
index 00000000..28483366
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/hal_data.h
@@ -0,0 +1,263 @@
+/* generated HAL header file - do not edit */
+#ifndef HAL_DATA_H_
+#define HAL_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "common_data.h"
+#include "r_gpt.h"
+#include "r_timer_api.h"
+#include "r_mtu3.h"
+#include "r_timer_api.h"
+#include "r_ethsw.h"
+#include "r_ether_switch_api.h"
+#include "r_ether_selector.h"
+#include "r_ether_selector_api.h"
+#include "r_ether_phy.h"
+#include "r_ether_phy_api.h"
+#include "r_gmac.h"
+#include "r_ether_api.h"
+#include "r_sci_uart.h"
+            #include "r_uart_api.h"
+FSP_HEADER
+/** Timer on GPT Instance. */
+extern const timer_instance_t g_timer1;
+
+/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */
+extern gpt_instance_ctrl_t g_timer1_ctrl;
+extern const timer_cfg_t g_timer1_cfg;
+
+#ifndef g_timer1_callback
+void g_timer1_callback(timer_callback_args_t * p_args);
+#endif
+#ifndef NULL
+void NULL(timer_callback_args_t * p_args);
+#endif
+
+/** Error check the duplicated channel number, same GPT_INT number between MTU3 and GPT */
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+ #ifndef TIMER_GPT00_1_INT0_DISABLE
+  #define TIMER_GPT00_1_INT0_DISABLE
+ #else
+  #ifdef TIMER_GPT00_1_INT0_ENABLE
+   #error "GPT_INT0 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_1_INT1_DISABLE
+  #define TIMER_GPT00_1_INT1_DISABLE
+ #else
+  #ifdef TIMER_GPT00_1_INT1_ENABLE
+   #error "GPT_INT1 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_1_INT2_DISABLE
+  #define TIMER_GPT00_1_INT2_DISABLE
+ #else
+  #ifdef TIMER_GPT00_1_INT2_ENABLE
+   #error "GPT_INT2 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_1_INT3_DISABLE
+  #define TIMER_GPT00_1_INT3_DISABLE
+ #else
+  #ifdef TIMER_GPT00_1_INT3_ENABLE
+   #error "GPT_INT3 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+#endif
+/** Timer on MTU3 Instance. */
+extern const timer_instance_t g_mtu3;
+
+/** Access the MTU3 instance using these structures when calling API functions directly (::p_api is not used). */
+extern mtu3_instance_ctrl_t g_mtu3_ctrl;
+extern const timer_cfg_t g_mtu3_cfg;
+
+#ifndef g_mtu3_callback
+void g_mtu3_callback(timer_callback_args_t * p_args);
+#endif
+#ifndef NULL
+void NULL(timer_callback_args_t * p_args);
+#endif
+
+/** Error check the duplicated channel number, same GPT_INT number between MTU3 and GPT */
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+ #ifndef TIMER_GPT00_0_INT0_DISABLE
+  #define TIMER_GPT00_0_INT0_DISABLE
+ #else
+  #ifdef TIMER_GPT00_0_INT0_ENABLE
+   #error "GPT_INT0 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_0_INT1_DISABLE
+  #define TIMER_GPT00_0_INT1_DISABLE
+ #else
+  #ifdef TIMER_GPT00_0_INT1_ENABLE
+   #error "GPT_INT1 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_0_INT2_DISABLE
+  #define TIMER_GPT00_0_INT2_DISABLE
+ #else
+  #ifdef TIMER_GPT00_0_INT2_ENABLE
+   #error "GPT_INT2 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_0_INT3_DISABLE
+  #define TIMER_GPT00_0_INT3_DISABLE
+ #else
+  #ifdef TIMER_GPT00_0_INT3_ENABLE
+   #error "GPT_INT3 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+#endif
+/** Timer on GPT Instance. */
+extern const timer_instance_t g_timer0;
+
+/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */
+extern gpt_instance_ctrl_t g_timer0_ctrl;
+extern const timer_cfg_t g_timer0_cfg;
+
+#ifndef timer0_esc_callback
+void timer0_esc_callback(timer_callback_args_t * p_args);
+#endif
+#ifndef NULL
+void NULL(timer_callback_args_t * p_args);
+#endif
+
+/** Error check the duplicated channel number, same GPT_INT number between MTU3 and GPT */
+#if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
+ #ifndef TIMER_GPT00_0_INT0_DISABLE
+  #define TIMER_GPT00_0_INT0_DISABLE
+ #else
+  #ifdef TIMER_GPT00_0_INT0_ENABLE
+   #error "GPT_INT0 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_0_INT1_DISABLE
+  #define TIMER_GPT00_0_INT1_DISABLE
+ #else
+  #ifdef TIMER_GPT00_0_INT1_ENABLE
+   #error "GPT_INT1 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_0_INT2_DISABLE
+  #define TIMER_GPT00_0_INT2_DISABLE
+ #else
+  #ifdef TIMER_GPT00_0_INT2_ENABLE
+   #error "GPT_INT2 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+ #ifndef TIMER_GPT00_0_INT3_DISABLE
+  #define TIMER_GPT00_0_INT3_DISABLE
+ #else
+  #ifdef TIMER_GPT00_0_INT3_ENABLE
+   #error "GPT_INT3 of GPT_SEL cannot be duplicated"
+  #endif
+ #endif
+#endif
+/** ether on ethsw Instance. */
+extern const ether_switch_instance_t g_ethsw0;
+
+/** Access the Ethernet PHY instance using these structures when calling API functions directly (::p_api is not used). */
+extern ethsw_instance_ctrl_t g_ethsw0_ctrl;
+extern const ether_switch_cfg_t g_ethsw0_cfg;
+#ifndef gmac_callback_ethsw
+void gmac_callback_ethsw(ether_switch_callback_args_t * const p_arg);
+#endif
+/** ether_selector on ether_selector Instance. */
+extern const ether_selector_instance_t g_ether_selector2;
+
+/** Access the Ethernet Selector instance using these structures when calling API functions directly (::p_api is not used). */
+extern ether_selector_instance_ctrl_t g_ether_selector2_ctrl;
+extern const ether_selector_cfg_t g_ether_selector2_cfg;
+#ifndef ETHER_PHY_LSI_TYPE_KIT_COMPONENT
+  #define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_DEFAULT
+#endif
+
+#ifndef ether_phy_targets_initialize_rtl8211_rgmii
+void ether_phy_targets_initialize_rtl8211_rgmii(ether_phy_instance_ctrl_t * p_instance_ctrl);
+#endif
+
+/** ether_phy on ether_phy Instance. */
+extern const ether_phy_instance_t g_ether_phy2;
+
+/** Access the Ethernet PHY instance using these structures when calling API functions directly (::p_api is not used). */
+extern ether_phy_instance_ctrl_t g_ether_phy2_ctrl;
+extern const ether_phy_cfg_t g_ether_phy2_cfg;
+/** ether_selector on ether_selector Instance. */
+extern const ether_selector_instance_t g_ether_selector1;
+
+/** Access the Ethernet Selector instance using these structures when calling API functions directly (::p_api is not used). */
+extern ether_selector_instance_ctrl_t g_ether_selector1_ctrl;
+extern const ether_selector_cfg_t g_ether_selector1_cfg;
+#ifndef ETHER_PHY_LSI_TYPE_KIT_COMPONENT
+  #define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_DEFAULT
+#endif
+
+#ifndef ether_phy_targets_initialize_rtl8211_rgmii
+void ether_phy_targets_initialize_rtl8211_rgmii(ether_phy_instance_ctrl_t * p_instance_ctrl);
+#endif
+
+/** ether_phy on ether_phy Instance. */
+extern const ether_phy_instance_t g_ether_phy1;
+
+/** Access the Ethernet PHY instance using these structures when calling API functions directly (::p_api is not used). */
+extern ether_phy_instance_ctrl_t g_ether_phy1_ctrl;
+extern const ether_phy_cfg_t g_ether_phy1_cfg;
+/** ether_selector on ether_selector Instance. */
+extern const ether_selector_instance_t g_ether_selector0;
+
+/** Access the Ethernet Selector instance using these structures when calling API functions directly (::p_api is not used). */
+extern ether_selector_instance_ctrl_t g_ether_selector0_ctrl;
+extern const ether_selector_cfg_t g_ether_selector0_cfg;
+#ifndef ETHER_PHY_LSI_TYPE_KIT_COMPONENT
+  #define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_DEFAULT
+#endif
+
+#ifndef ether_phy_targets_initialize_rtl8211_rgmii
+void ether_phy_targets_initialize_rtl8211_rgmii(ether_phy_instance_ctrl_t * p_instance_ctrl);
+#endif
+
+/** ether_phy on ether_phy Instance. */
+extern const ether_phy_instance_t g_ether_phy0;
+
+/** Access the Ethernet PHY instance using these structures when calling API functions directly (::p_api is not used). */
+extern ether_phy_instance_ctrl_t g_ether_phy0_ctrl;
+extern const ether_phy_cfg_t g_ether_phy0_cfg;
+/** ether on ether Instance. */
+extern const ether_instance_t g_ether0;
+
+/** Access the Ethernet instance using these structures when calling API functions directly (::p_api is not used). */
+extern gmac_instance_ctrl_t g_ether0_ctrl;
+extern const ether_cfg_t g_ether0_cfg;
+
+#ifndef user_ether0_callback
+void user_ether0_callback(ether_callback_args_t * p_args);
+#endif
+/** UART on SCI Instance. */
+            extern const uart_instance_t      g_uart0;
+
+            /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
+            extern sci_uart_instance_ctrl_t     g_uart0_ctrl;
+            extern const uart_cfg_t g_uart0_cfg;
+            extern const sci_uart_extended_cfg_t g_uart0_cfg_extend;
+
+            #ifndef user_uart0_callback
+            void user_uart0_callback(uart_callback_args_t * p_args);
+            #endif
+
+            #define FSP_NOT_DEFINED (1)
+            #if (FSP_NOT_DEFINED == FSP_NOT_DEFINED)
+                #define g_uart0_P_TRANSFER_TX (NULL)
+            #else
+                #define g_uart0_P_TRANSFER_TX (&FSP_NOT_DEFINED)
+            #endif
+            #if (FSP_NOT_DEFINED == FSP_NOT_DEFINED)
+                #define g_uart0_P_TRANSFER_RX (NULL)
+            #else
+                #define g_uart0_P_TRANSFER_RX (&FSP_NOT_DEFINED)
+            #endif
+            #undef FSP_NOT_DEFINED
+void hal_entry(void);
+void g_hal_init(void);
+FSP_FOOTER
+#endif /* HAL_DATA_H_ */
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/main.c b/projects/etherkit_ethercat_cherryecat/rzn_gen/main.c
new file mode 100644
index 00000000..42c59048
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/main.c
@@ -0,0 +1,6 @@
+/* generated main source file - do not edit */
+#include "hal_data.h"
+            int main(void) {
+              hal_entry();
+              return 0;
+            }
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/pin_data.c b/projects/etherkit_ethercat_cherryecat/rzn_gen/pin_data.c
new file mode 100644
index 00000000..b054b117
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/pin_data.c
@@ -0,0 +1,420 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport_api.h"
+#include "r_ioport.h"
+
+extern const ioport_extend_cfg_t  g_ioport_cfg_extend;
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_00_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P000_PFC_00_ETH2_RXD3)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P001_PFC_01_ETH2_RXDV)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P002_PFC_00_ETH2_TXEN)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P003_PFC_01_ETH2_REFCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P005_PFC_00_ETHSW_PHYLINK2)
+    },
+    {
+        .pin = BSP_IO_PORT_00_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P006_PFC_00_ETH2_TXCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P012_PFC_01_ETH2_TXD3)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P013_PFC_00_ETH2_TXD2)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P014_PFC_01_ETH2_TXD1)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P015_PFC_00_ETH2_TXD0)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P017_PFC_08_CANRX0)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P022_PFC_08_CANTX0)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P024_PFC_00_TDO)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P025_PFC_01_TDI)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P026_PFC_00_TMS_SWDIO)
+    },
+    {
+        .pin = BSP_IO_PORT_02_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P027_PFC_00_TCK_SWCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P052_PFC_08_IIC_SCL1)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P053_PFC_09_IIC_SDA1)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P055_PFC_00_ETHSW_PHYLINK1)
+    },
+    {
+        .pin = BSP_IO_PORT_05_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P057_PFC_00_ETH1_TXD2)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P060_PFC_00_ETH1_TXD3)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P061_PFC_00_ETH1_REFCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P062_PFC_00_ETH1_TXD1)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P063_PFC_00_ETH1_TXD0)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P064_PFC_00_ETH1_TXCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P065_PFC_00_ETH1_TXEN)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P066_PFC_00_ETH1_RXD0)
+    },
+    {
+        .pin = BSP_IO_PORT_06_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P067_PFC_00_ETH1_RXD1)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P070_PFC_00_ETH1_RXD2)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P071_PFC_00_ETH1_RXD3)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P072_PFC_00_ETH1_RXDV)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P073_PFC_00_ETH1_RXCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_07_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P074_PFC_02_USB_VBUSIN)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P084_PFC_00_ETH0_RXD3)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P085_PFC_00_ETH0_RXDV)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P086_PFC_00_ETH0_RXCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_08_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P087_PFC_00_GMAC_MDC)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P090_PFC_00_GMAC_MDIO)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P091_PFC_00_ETH0_REFCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P093_PFC_00_ETH0_TXD3)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P094_PFC_00_ETH0_TXD2)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P095_PFC_00_ETH0_TXD1)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P096_PFC_00_ETH0_TXD0)
+    },
+    {
+        .pin = BSP_IO_PORT_09_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P097_PFC_00_ETH0_TXCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P100_PFC_00_ETH0_TXEN)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P101_PFC_00_ETH0_RXD0)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P102_PFC_00_ETH0_RXD1)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P103_PFC_00_ETH0_RXD2)
+    },
+    {
+        .pin = BSP_IO_PORT_10_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P104_PFC_01_ETHSW_PHYLINK0)
+    },
+    {
+        .pin = BSP_IO_PORT_13_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P132_PFC_0B_IIC_SCL0)
+    },
+    {
+        .pin = BSP_IO_PORT_13_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P133_PFC_0B_IIC_SDA0)
+    },
+    {
+        .pin = BSP_IO_PORT_13_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_13_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_13_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_13_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_14_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_14_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_14_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P142_PFC_01_XSPI0_ECS0)
+    },
+    {
+        .pin = BSP_IO_PORT_14_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_14_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P144_PFC_00_XSPI0_DS)
+    },
+    {
+        .pin = BSP_IO_PORT_14_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P145_PFC_00_XSPI0_CKN)
+    },
+    {
+        .pin = BSP_IO_PORT_14_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P146_PFC_00_XSPI0_CKP)
+    },
+    {
+        .pin = BSP_IO_PORT_14_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P147_PFC_00_XSPI0_IO0)
+    },
+    {
+        .pin = BSP_IO_PORT_15_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P150_PFC_00_XSPI0_IO1)
+    },
+    {
+        .pin = BSP_IO_PORT_15_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P151_PFC_00_XSPI0_IO2)
+    },
+    {
+        .pin = BSP_IO_PORT_15_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P152_PFC_00_XSPI0_IO3)
+    },
+    {
+        .pin = BSP_IO_PORT_15_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P153_PFC_00_XSPI0_IO4)
+    },
+    {
+        .pin = BSP_IO_PORT_15_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P154_PFC_00_XSPI0_IO5)
+    },
+    {
+        .pin = BSP_IO_PORT_15_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P155_PFC_00_XSPI0_IO6)
+    },
+    {
+        .pin = BSP_IO_PORT_15_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P156_PFC_00_XSPI0_IO7)
+    },
+    {
+        .pin = BSP_IO_PORT_15_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P157_PFC_00_XSPI0_CS0)
+    },
+    {
+        .pin = BSP_IO_PORT_16_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P160_PFC_00_XSPI0_CS1)
+    },
+    {
+        .pin = BSP_IO_PORT_16_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P161_PFC_00_XSPI0_RESET0)
+    },
+    {
+        .pin = BSP_IO_PORT_16_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+    },
+    {
+        .pin = BSP_IO_PORT_16_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0)
+    },
+    {
+        .pin = BSP_IO_PORT_16_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0)
+    },
+    {
+        .pin = BSP_IO_PORT_17_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_17_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P175_PFC_05_USB_OVRCUR)
+    },
+    {
+        .pin = BSP_IO_PORT_17_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3)
+    },
+    {
+        .pin = BSP_IO_PORT_18_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3)
+    },
+    {
+        .pin = BSP_IO_PORT_18_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_18_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P184_PFC_03_SPI_RSPCK2)
+    },
+    {
+        .pin = BSP_IO_PORT_18_PIN_5,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P185_PFC_03_SPI_MOSI2)
+    },
+    {
+        .pin = BSP_IO_PORT_18_PIN_6,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P186_PFC_05_SPI_MISO2)
+    },
+    {
+        .pin = BSP_IO_PORT_19_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P190_PFC_00_USB_VBUSEN)
+    },
+    {
+        .pin = BSP_IO_PORT_20_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_20_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_20_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_20_PIN_4,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_21_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P211_PFC_06_SPI_SSL20)
+    },
+    {
+        .pin = BSP_IO_PORT_22_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_22_PIN_3,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_23_PIN_7,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P237_PFC_00_ETH2_RXD0)
+    },
+    {
+        .pin = BSP_IO_PORT_24_PIN_0,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P240_PFC_00_ETH2_RXD1)
+    },
+    {
+        .pin = BSP_IO_PORT_24_PIN_1,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P241_PFC_00_ETH2_RXCLK)
+    },
+    {
+        .pin = BSP_IO_PORT_24_PIN_2,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P242_PFC_00_ETH2_RXD2)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+    .p_extend = &g_ioport_cfg_extend,
+};
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/vector_data.c b/projects/etherkit_ethercat_cherryecat/rzn_gen/vector_data.c
new file mode 100644
index 00000000..2fac14a5
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/vector_data.c
@@ -0,0 +1,33 @@
+/* generated vector source file - do not edit */
+        #include "bsp_api.h"
+        /* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */
+        #if VECTOR_DATA_IRQ_COUNT > 0
+        BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] =
+        {
+                        [73] = mtu3_counter_overflow_isr, /* TCIV0 (MTU0.TCNT overflow) */
+            [122] = gpt_counter_overflow_isr, /* GPT_OVF (GPT0 GTCNT overflow (GTPR compare match)) */
+            [131] = gpt_counter_overflow_isr, /* GPT_OVF (GPT1 GTCNT overflow (GTPR compare match)) */
+            [251] = gmac_isr_pmt, /* GMAC_PMT (GMAC1 power management) */
+            [252] = gmac_isr_sbd, /* GMAC_SBD (GMAC1 general interrupt) */
+            [253] = ethsw_isr_intr, /* ETHSW_INTR (Ethernet Switch interrupt) */
+            [288] = sci_uart_eri_isr, /* SCI0_ERI (SCI0 Receive error) */
+            [289] = sci_uart_rxi_isr, /* SCI0_RXI (SCI0 Receive data full) */
+            [290] = sci_uart_txi_isr, /* SCI0_TXI (SCI0 Transmit data empty) */
+            [291] = sci_uart_tei_isr, /* SCI0_TEI (SCI0 Transmit end) */
+        };
+        #if (1 == BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED)
+        const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
+        {
+            [73] = BSP_PRV_CR52_SEL_ENUM(EVENT_TCIV0), /* TCIV0 (MTU0.TCNT overflow) */
+            [122] = BSP_PRV_CR52_SEL_ENUM(EVENT_GPT0_OVF), /* GPT_OVF (GPT0 GTCNT overflow (GTPR compare match)) */
+            [131] = BSP_PRV_CR52_SEL_ENUM(EVENT_GPT1_OVF), /* GPT_OVF (GPT1 GTCNT overflow (GTPR compare match)) */
+            [251] = BSP_PRV_CR52_SEL_ENUM(EVENT_GMAC_PMT), /* GMAC_PMT (GMAC1 power management) */
+            [252] = BSP_PRV_CR52_SEL_ENUM(EVENT_GMAC_SBD), /* GMAC_SBD (GMAC1 general interrupt) */
+            [253] = BSP_PRV_CR52_SEL_ENUM(EVENT_ETHSW_INTR), /* ETHSW_INTR (Ethernet Switch interrupt) */
+            [288] = BSP_PRV_CR52_SEL_ENUM(EVENT_SCI0_ERI), /* SCI0_ERI (SCI0 Receive error) */
+            [289] = BSP_PRV_CR52_SEL_ENUM(EVENT_SCI0_RXI), /* SCI0_RXI (SCI0 Receive data full) */
+            [290] = BSP_PRV_CR52_SEL_ENUM(EVENT_SCI0_TXI), /* SCI0_TXI (SCI0 Transmit data empty) */
+            [291] = BSP_PRV_CR52_SEL_ENUM(EVENT_SCI0_TEI), /* SCI0_TEI (SCI0 Transmit end) */
+        };
+        #endif
+        #endif
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/rzn_gen/vector_data.h b/projects/etherkit_ethercat_cherryecat/rzn_gen/vector_data.h
new file mode 100644
index 00000000..be876bc2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/rzn_gen/vector_data.h
@@ -0,0 +1,75 @@
+/* generated vector header file - do not edit */
+        #ifndef VECTOR_DATA_H
+        #define VECTOR_DATA_H
+        #include "bsp_api.h"
+
+        /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+        FSP_HEADER
+
+                /* Number of interrupts allocated */
+        #ifndef VECTOR_DATA_IRQ_COUNT
+        #define VECTOR_DATA_IRQ_COUNT    (10)
+        #endif
+        /* ISR prototypes */
+        void mtu3_counter_overflow_isr(void);
+        void gpt_counter_overflow_isr(void);
+        void gmac_isr_pmt(void);
+        void gmac_isr_sbd(void);
+        void ethsw_isr_intr(void);
+        void sci_uart_eri_isr(void);
+        void sci_uart_rxi_isr(void);
+        void sci_uart_txi_isr(void);
+        void sci_uart_tei_isr(void);
+
+        /* Vector table allocations */
+        #define VECTOR_NUMBER_TCIV0 ((IRQn_Type) 73) /* TCIV0 (MTU0.TCNT overflow) */
+        #define VECTOR_NUMBER_GPT0_OVF ((IRQn_Type) 122) /* GPT_OVF (GPT0 GTCNT overflow (GTPR compare match)) */
+        #define VECTOR_NUMBER_GPT1_OVF ((IRQn_Type) 131) /* GPT_OVF (GPT1 GTCNT overflow (GTPR compare match)) */
+        #define VECTOR_NUMBER_GMAC_PMT ((IRQn_Type) 251) /* GMAC_PMT (GMAC1 power management) */
+        #define VECTOR_NUMBER_GMAC_SBD ((IRQn_Type) 252) /* GMAC_SBD (GMAC1 general interrupt) */
+        #define VECTOR_NUMBER_ETHSW_INTR ((IRQn_Type) 253) /* ETHSW_INTR (Ethernet Switch interrupt) */
+        #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type) 288) /* SCI0_ERI (SCI0 Receive error) */
+        #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 289) /* SCI0_RXI (SCI0 Receive data full) */
+        #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type) 290) /* SCI0_TXI (SCI0 Transmit data empty) */
+        #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type) 291) /* SCI0_TEI (SCI0 Transmit end) */
+        typedef enum IRQn {
+            SoftwareGeneratedInt0 = -32,
+            SoftwareGeneratedInt1 = -31,
+            SoftwareGeneratedInt2 = -30,
+            SoftwareGeneratedInt3 = -29,
+            SoftwareGeneratedInt4 = -28,
+            SoftwareGeneratedInt5 = -27,
+            SoftwareGeneratedInt6 = -26,
+            SoftwareGeneratedInt7 = -25,
+            SoftwareGeneratedInt8 = -24,
+            SoftwareGeneratedInt9 = -23,
+            SoftwareGeneratedInt10 = -22,
+            SoftwareGeneratedInt11 = -21,
+            SoftwareGeneratedInt12 = -20,
+            SoftwareGeneratedInt13 = -19,
+            SoftwareGeneratedInt14 = -18,
+            SoftwareGeneratedInt15 = -17,
+            DebugCommunicationsChannelInt = -10,
+            PerformanceMonitorCounterOverflowInt = -9,
+            CrossTriggerInterfaceInt = -8,
+            VritualCPUInterfaceMaintenanceInt = -7,
+            HypervisorTimerInt = -6,
+            VirtualTimerInt = -5,
+            NonSecurePhysicalTimerInt = -2,
+            TCIV0_IRQn = 73, /* TCIV0 (MTU0.TCNT overflow) */
+            GPT0_OVF_IRQn = 122, /* GPT_OVF (GPT0 GTCNT overflow (GTPR compare match)) */
+            GPT1_OVF_IRQn = 131, /* GPT_OVF (GPT1 GTCNT overflow (GTPR compare match)) */
+            GMAC_PMT_IRQn = 251, /* GMAC_PMT (GMAC1 power management) */
+            GMAC_SBD_IRQn = 252, /* GMAC_SBD (GMAC1 general interrupt) */
+            ETHSW_INTR_IRQn = 253, /* ETHSW_INTR (Ethernet Switch interrupt) */
+            SCI0_ERI_IRQn = 288, /* SCI0_ERI (SCI0 Receive error) */
+            SCI0_RXI_IRQn = 289, /* SCI0_RXI (SCI0 Receive data full) */
+            SCI0_TXI_IRQn = 290, /* SCI0_TXI (SCI0 Transmit data empty) */
+            SCI0_TEI_IRQn = 291, /* SCI0_TEI (SCI0 Transmit end) */
+            SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = BSP_VECTOR_TABLE_MAX_ENTRIES
+        } IRQn_Type;
+
+        /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+        FSP_FOOTER
+
+        #endif /* VECTOR_DATA_H */
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot.icf b/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot.icf
new file mode 100644
index 00000000..a51fa05b
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot.icf
@@ -0,0 +1,735 @@
+/* generated memory regions file - do not edit */
+define symbol ATCM_START = 0x00000000;
+define symbol ATCM_LENGTH   = 0x20000;
+define symbol BTCM_START = 0x00100000;
+define symbol BTCM_LENGTH   = 0x20000;
+define symbol SYSTEM_RAM_START = 0x10000000;
+define symbol SYSTEM_RAM_LENGTH   = 0x180000;
+define symbol SYSTEM_RAM_MIRROR_START = 0x30000000;
+define symbol SYSTEM_RAM_MIRROR_LENGTH   = 0x180000;
+define symbol xSPI0_CS0_SPACE_MIRROR_START = 0x40000000;
+define symbol xSPI0_CS0_SPACE_MIRROR_LENGTH   = 0x4000000;
+define symbol xSPI0_CS1_SPACE_MIRROR_START = 0x44000000;
+define symbol xSPI0_CS1_SPACE_MIRROR_LENGTH   = 0x4000000;
+define symbol xSPI1_CS0_SPACE_MIRROR_START = 0x48000000;
+define symbol xSPI1_CS0_SPACE_MIRROR_LENGTH   = 0x4000000;
+define symbol CS0_SPACE_MIRROR_START = 0x50000000;
+define symbol CS0_SPACE_MIRROR_LENGTH   = 0x4000000;
+define symbol CS2_SPACE_MIRROR_START = 0x54000000;
+define symbol CS2_SPACE_MIRROR_LENGTH   = 0x4000000;
+define symbol CS3_SPACE_MIRROR_START = 0x58000000;
+define symbol CS3_SPACE_MIRROR_LENGTH   = 0x4000000;
+define symbol CS5_SPACE_MIRROR_START = 0x5C000000;
+define symbol CS5_SPACE_MIRROR_LENGTH   = 0x4000000;
+define symbol xSPI0_CS0_SPACE_START = 0x60000000;
+define symbol xSPI0_CS0_SPACE_LENGTH   = 0x4000000;
+define symbol xSPI0_CS1_SPACE_START = 0x64000000;
+define symbol xSPI0_CS1_SPACE_LENGTH   = 0x4000000;
+define symbol xSPI1_CS0_SPACE_START = 0x68000000;
+define symbol xSPI1_CS0_SPACE_LENGTH   = 0x4000000;
+define symbol CS0_SPACE_START = 0x70000000;
+define symbol CS0_SPACE_LENGTH   = 0x4000000;
+define symbol CS2_SPACE_START = 0x74000000;
+define symbol CS2_SPACE_LENGTH   = 0x4000000;
+define symbol CS3_SPACE_START = 0x78000000;
+define symbol CS3_SPACE_LENGTH   = 0x4000000;
+define symbol CS5_SPACE_START = 0x7C000000;
+define symbol CS5_SPACE_LENGTH   = 0x4000000;
+
+/* The memory information for each device is done in memory regions file.
+ * The starting address and length of memory not defined in memory regions file are defined as 0. */
+
+if (isdefinedsymbol(ATCM_START))
+{
+    define symbol ATCM_PRV_START = ATCM_START;
+}
+else
+{
+    define symbol ATCM_PRV_START = 0;
+}
+
+if (isdefinedsymbol(ATCM_LENGTH))
+{
+    define symbol ATCM_PRV_LENGTH = ATCM_LENGTH;
+}
+else
+{
+    define symbol ATCM_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(BTCM_START))
+{
+    define symbol BTCM_PRV_START = BTCM_START;
+}
+else
+{
+    define symbol BTCM_PRV_START = 0;
+}
+
+if (isdefinedsymbol(BTCM_LENGTH))
+{
+    define symbol BTCM_PRV_LENGTH = BTCM_LENGTH;
+}
+else
+{
+    define symbol BTCM_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(SYSTEM_RAM_START))
+{
+    define symbol SYSTEM_RAM_PRV_START = SYSTEM_RAM_START;
+}
+else
+{
+    define symbol SYSTEM_RAM_PRV_START = 0;
+}
+
+if (isdefinedsymbol(SYSTEM_RAM_LENGTH))
+{
+    define symbol SYSTEM_RAM_PRV_LENGTH = SYSTEM_RAM_LENGTH;
+}
+else
+{
+    define symbol SYSTEM_RAM_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(SYSTEM_RAM_MIRROR_START))
+{
+    define symbol SYSTEM_RAM_MIRROR_PRV_START = SYSTEM_RAM_MIRROR_START;
+}
+else
+{
+    define symbol SYSTEM_RAM_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(SYSTEM_RAM_MIRROR_LENGTH))
+{
+    define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = SYSTEM_RAM_MIRROR_LENGTH;
+}
+else
+{
+    define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_START))
+{
+    define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = xSPI0_CS0_SPACE_MIRROR_START;
+}
+else
+{
+    define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_LENGTH))
+{
+    define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS0_SPACE_MIRROR_LENGTH;
+}
+else
+{
+    define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_START))
+{
+    define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = xSPI0_CS1_SPACE_MIRROR_START;
+}
+else
+{
+    define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_LENGTH))
+{
+    define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS1_SPACE_MIRROR_LENGTH;
+}
+else
+{
+    define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_START))
+{
+    define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = xSPI1_CS0_SPACE_MIRROR_START;
+}
+else
+{
+    define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_LENGTH))
+{
+    define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS0_SPACE_MIRROR_LENGTH;
+}
+else
+{
+    define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_START))
+{
+    define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = xSPI1_CS1_SPACE_MIRROR_START;
+}
+else
+{
+    define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_LENGTH))
+{
+    define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS1_SPACE_MIRROR_LENGTH;
+}
+else
+{
+    define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(CS0_SPACE_MIRROR_START))
+{
+    define symbol CS0_SPACE_MIRROR_PRV_START = CS0_SPACE_MIRROR_START;
+}
+else
+{
+    define symbol CS0_SPACE_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(CS0_SPACE_MIRROR_LENGTH))
+{
+    define symbol CS0_SPACE_MIRROR_PRV_LENGTH = CS0_SPACE_MIRROR_LENGTH;
+}
+else
+{
+    define symbol CS0_SPACE_MIRROR_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(CS2_SPACE_MIRROR_START))
+{
+    define symbol CS2_SPACE_MIRROR_PRV_START = CS2_SPACE_MIRROR_START;
+}
+else
+{
+    define symbol CS2_SPACE_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(CS2_SPACE_MIRROR_LENGTH))
+{
+    define symbol CS2_SPACE_MIRROR_PRV_LENGTH = CS2_SPACE_MIRROR_LENGTH;
+}
+else
+{
+    define symbol CS2_SPACE_MIRROR_PRV_LENGTH = 0;
+}
+
+
+if (isdefinedsymbol(CS3_SPACE_MIRROR_START))
+{
+    define symbol CS3_SPACE_MIRROR_PRV_START = CS3_SPACE_MIRROR_START;
+}
+else
+{
+    define symbol CS3_SPACE_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(CS3_SPACE_MIRROR_LENGTH))
+{
+    define symbol CS3_SPACE_MIRROR_PRV_LENGTH = CS3_SPACE_MIRROR_LENGTH;
+}
+else
+{
+    define symbol CS3_SPACE_MIRROR_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(CS5_SPACE_MIRROR_START))
+{
+    define symbol CS5_SPACE_MIRROR_PRV_START = CS5_SPACE_MIRROR_START;
+}
+else
+{
+    define symbol CS5_SPACE_MIRROR_PRV_START = 0;
+}
+
+if (isdefinedsymbol(CS5_SPACE_MIRROR_LENGTH))
+{
+    define symbol CS5_SPACE_MIRROR_PRV_LENGTH = CS5_SPACE_MIRROR_LENGTH;
+}
+else
+{
+    define symbol CS5_SPACE_MIRROR_PRV_LENGTH = 0;
+}
+
+
+if (isdefinedsymbol(xSPI0_CS0_SPACE_START))
+{
+    define symbol xSPI0_CS0_SPACE_PRV_START = xSPI0_CS0_SPACE_START;
+}
+else
+{
+    define symbol xSPI0_CS0_SPACE_PRV_START = 0;
+}
+
+if (isdefinedsymbol(xSPI0_CS0_SPACE_LENGTH))
+{
+    define symbol xSPI0_CS0_SPACE_PRV_LENGTH = xSPI0_CS0_SPACE_LENGTH;
+}
+else
+{
+    define symbol xSPI0_CS0_SPACE_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(xSPI0_CS1_SPACE_START))
+{
+    define symbol xSPI0_CS1_SPACE_PRV_START = xSPI0_CS1_SPACE_START;
+}
+else
+{
+    define symbol xSPI0_CS1_SPACE_PRV_START = 0;
+}
+
+if (isdefinedsymbol(xSPI0_CS1_SPACE_LENGTH))
+{
+    define symbol xSPI0_CS1_SPACE_PRV_LENGTH = xSPI0_CS1_SPACE_LENGTH;
+}
+else
+{
+    define symbol xSPI0_CS1_SPACE_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(xSPI1_CS0_SPACE_START))
+{
+    define symbol xSPI1_CS0_SPACE_PRV_START = xSPI1_CS0_SPACE_START;
+}
+else
+{
+    define symbol xSPI1_CS0_SPACE_PRV_START = 0;
+}
+
+if (isdefinedsymbol(xSPI1_CS0_SPACE_LENGTH))
+{
+    define symbol xSPI1_CS0_SPACE_PRV_LENGTH = xSPI1_CS0_SPACE_LENGTH;
+}
+else
+{
+    define symbol xSPI1_CS0_SPACE_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(xSPI1_CS1_SPACE_START))
+{
+    define symbol xSPI1_CS1_SPACE_PRV_START = xSPI1_CS1_SPACE_START;
+}
+else
+{
+    define symbol xSPI1_CS1_SPACE_PRV_START = 0;
+}
+
+if (isdefinedsymbol(xSPI1_CS1_SPACE_LENGTH))
+{
+    define symbol xSPI1_CS1_SPACE_PRV_LENGTH = xSPI1_CS1_SPACE_LENGTH;
+}
+else
+{
+    define symbol xSPI1_CS1_SPACE_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(CS0_SPACE_START))
+{
+    define symbol CS0_SPACE_PRV_START = CS0_SPACE_START;
+}
+else
+{
+    define symbol CS0_SPACE_PRV_START = 0;
+}
+
+if (isdefinedsymbol(CS0_SPACE_LENGTH))
+{
+    define symbol CS0_SPACE_PRV_LENGTH = CS0_SPACE_LENGTH;
+}
+else
+{
+    define symbol CS0_SPACE_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(CS2_SPACE_START))
+{
+    define symbol CS2_SPACE_PRV_START = CS2_SPACE_START;
+}
+else
+{
+    define symbol CS2_SPACE_PRV_START = 0;
+}
+
+if (isdefinedsymbol(CS2_SPACE_LENGTH))
+{
+    define symbol CS2_SPACE_PRV_LENGTH = CS2_SPACE_LENGTH;
+}
+else
+{
+    define symbol CS2_SPACE_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(CS3_SPACE_START))
+{
+    define symbol CS3_SPACE_PRV_START = CS3_SPACE_START;
+}
+else
+{
+    define symbol CS3_SPACE_PRV_START = 0;
+}
+
+if (isdefinedsymbol(CS3_SPACE_LENGTH))
+{
+    define symbol CS3_SPACE_PRV_LENGTH = CS3_SPACE_LENGTH;
+}
+else
+{
+    define symbol CS3_SPACE_PRV_LENGTH = 0;
+}
+
+if (isdefinedsymbol(CS5_SPACE_START))
+{
+    define symbol CS5_SPACE_PRV_START = CS5_SPACE_START;
+}
+else
+{
+    define symbol CS5_SPACE_PRV_START = 0;
+}
+
+if (isdefinedsymbol(CS5_SPACE_LENGTH))
+{
+    define symbol CS5_SPACE_PRV_LENGTH = CS5_SPACE_LENGTH;
+}
+else
+{
+    define symbol CS5_SPACE_PRV_LENGTH = 0;
+}
+
+define symbol SYSTEM_RAM_END_OFFSET        = 0x00048000;
+define symbol FLASH_ADDRESS                = xSPI0_CS0_SPACE_PRV_START;
+
+/* 
+define symbol INTVEC_ADDRESS               = ATCM_PRV_START;
+define symbol RAM_ADDRESS                  = (ATCM_PRV_START + 0x100);
+define symbol RAM_END_ADDRESS              = (ATCM_PRV_START + ATCM_PRV_LENGTH - 1);
+define symbol LOADER_STACK_ADDRESS         = (BTCM_PRV_START + 0x2000);
+define symbol LOADER_STACK_END_ADDRESS     = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1);
+define symbol DATA_NONCACHE_OFFSET         = 0x00048000;
+define symbol DATA_NONCACHE_END_OFFSET     = 0x00044000;
+define symbol DMAC_LINK_MODE_OFFSET        = 0x00044000;
+define symbol DMAC_LINK_MODE_END_OFFSET    = 0x00040000;
+define symbol NONCACHE_BUFFER_OFFSET       = 0x00020000;
+define symbol NONCACHE_BUFFER_END_OFFSET   = 0;
+*/
+/************* Override define symbol to place EtherCAT protocol into SystemRAM ************/
+define symbol INTVEC_ADDRESS               = SYSTEM_RAM_PRV_START;
+define symbol RAM_ADDRESS                  = (SYSTEM_RAM_PRV_START + 0x100);
+define symbol RAM_END_ADDRESS              = (SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - 1);
+define symbol LOADER_STACK_ADDRESS         = (BTCM_PRV_START + 0x2000);
+define symbol LOADER_STACK_END_ADDRESS     = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1);
+define symbol DATA_NONCACHE_OFFSET         = 0x00048000;
+define symbol DATA_NONCACHE_END_OFFSET     = 0x00044000;
+define symbol DMAC_LINK_MODE_OFFSET        = 0x00044000;
+define symbol DMAC_LINK_MODE_END_OFFSET    = 0x00040000;
+define symbol NONCACHE_BUFFER_OFFSET       = 0x00020000;
+define symbol NONCACHE_BUFFER_END_OFFSET   = 0;
+/*********************************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = INTVEC_ADDRESS;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = FLASH_ADDRESS + 0x20100;
+define symbol __ICFEDIT_region_ROM_end__   = FLASH_ADDRESS + 0x6FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = RAM_ADDRESS;
+define symbol __ICFEDIT_region_RAM_end__   = RAM_END_ADDRESS;
+/**** End of ICF editor section. ###ICF###*/
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+define symbol __region_D_LOADER_STACK_start__     = LOADER_STACK_ADDRESS;
+define symbol __region_D_LOADER_STACK_end__       = LOADER_STACK_END_ADDRESS;
+
+define symbol __region_DATA_NONCACHE_start__          = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_OFFSET;
+define symbol __region_DATA_NONCACHE_end__            = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_END_OFFSET - 1;
+define symbol __region_DMAC_LINK_MODE_start__         = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_OFFSET;
+define symbol __region_DMAC_LINK_MODE_end__           = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_END_OFFSET - 1;
+define symbol __region_SHARED_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00040000;
+define symbol __region_SHARED_NONCACHE_BUFFER_end__   = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00020000 - 1;
+define symbol __region_NONCACHE_BUFFER_start__        = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_OFFSET;
+define symbol __region_NONCACHE_BUFFER_end__          = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_END_OFFSET - 1;
+
+define symbol __region_ATCM_start__              = ATCM_PRV_START;
+define symbol __region_ATCM_end__                = ATCM_PRV_START + ATCM_PRV_LENGTH - 1;
+define symbol __region_BTCM_start__              = BTCM_PRV_START;
+define symbol __region_BTCM_end__                = BTCM_PRV_START + BTCM_PRV_LENGTH - 1;
+define symbol __region_SYSTEM_RAM_start__        = SYSTEM_RAM_PRV_START;
+define symbol __region_SYSTEM_RAM_end__          = SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1;
+define symbol __region_SYSTEM_RAM_MIRROR_start__ = SYSTEM_RAM_MIRROR_PRV_START;
+define symbol __region_SYSTEM_RAM_MIRROR_end__   = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1;
+
+define symbol __region_XSPI0_CS0_MIRROR_start__ = xSPI0_CS0_SPACE_MIRROR_PRV_START;
+define symbol __region_XSPI0_CS0_MIRROR_end__   = xSPI0_CS0_SPACE_MIRROR_PRV_START + xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH - 1;
+define symbol __region_XSPI0_CS1_MIRROR_start__ = xSPI0_CS1_SPACE_MIRROR_PRV_START;
+define symbol __region_XSPI0_CS1_MIRROR_end__   = xSPI0_CS1_SPACE_MIRROR_PRV_START + xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH - 1;
+define symbol __region_XSPI1_CS0_MIRROR_start__ = xSPI1_CS0_SPACE_MIRROR_PRV_START;
+define symbol __region_XSPI1_CS0_MIRROR_end__   = xSPI1_CS0_SPACE_MIRROR_PRV_START + xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH - 1;
+define symbol __region_XSPI1_CS1_MIRROR_start__ = xSPI1_CS1_SPACE_MIRROR_PRV_START;
+define symbol __region_XSPI1_CS1_MIRROR_end__   = xSPI1_CS1_SPACE_MIRROR_PRV_START + xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH - 1;
+define symbol __region_CS0_MIRROR_start__       = CS0_SPACE_MIRROR_PRV_START;
+define symbol __region_CS0_MIRROR_end__         = CS0_SPACE_MIRROR_PRV_START + CS0_SPACE_MIRROR_PRV_LENGTH - 1;
+define symbol __region_CS2_MIRROR_start__       = CS2_SPACE_MIRROR_PRV_START;
+define symbol __region_CS2_MIRROR_end__         = CS2_SPACE_MIRROR_PRV_START + CS2_SPACE_MIRROR_PRV_LENGTH - 1;
+define symbol __region_CS3_MIRROR_start__       = CS3_SPACE_MIRROR_PRV_START;
+define symbol __region_CS3_MIRROR_end__         = CS3_SPACE_MIRROR_PRV_START + CS3_SPACE_MIRROR_PRV_LENGTH - 1;
+define symbol __region_CS5_MIRROR_start__       = CS5_SPACE_MIRROR_PRV_START;
+define symbol __region_CS5_MIRROR_end__         = CS5_SPACE_MIRROR_PRV_START + CS5_SPACE_MIRROR_PRV_LENGTH - 1;
+define symbol __region_XSPI0_CS0_start__        = xSPI0_CS0_SPACE_PRV_START;
+define symbol __region_XSPI0_CS0_end__          = xSPI0_CS0_SPACE_PRV_START + xSPI0_CS0_SPACE_PRV_LENGTH - 1;
+define symbol __region_XSPI0_CS1_start__        = xSPI0_CS1_SPACE_PRV_START;
+define symbol __region_XSPI0_CS1_end__          = xSPI0_CS1_SPACE_PRV_START + xSPI0_CS1_SPACE_PRV_LENGTH - 1;
+define symbol __region_XSPI1_CS0_start__        = xSPI1_CS0_SPACE_PRV_START;
+define symbol __region_XSPI1_CS0_end__          = xSPI1_CS0_SPACE_PRV_START + xSPI1_CS0_SPACE_PRV_LENGTH - 1;
+define symbol __region_XSPI1_CS1_start__        = xSPI1_CS1_SPACE_PRV_START;
+define symbol __region_XSPI1_CS1_end__          = xSPI1_CS1_SPACE_PRV_START + xSPI1_CS1_SPACE_PRV_LENGTH - 1;
+define symbol __region_CS0_start__              = CS0_SPACE_PRV_START;
+define symbol __region_CS0_end__                = CS0_SPACE_PRV_START + CS0_SPACE_PRV_LENGTH - 1;
+define symbol __region_CS2_start__              = CS2_SPACE_PRV_START;
+define symbol __region_CS2_end__                = CS2_SPACE_PRV_START + CS2_SPACE_PRV_LENGTH - 1;
+define symbol __region_CS3_start__              = CS3_SPACE_PRV_START;
+define symbol __region_CS3_end__                = CS3_SPACE_PRV_START + CS3_SPACE_PRV_LENGTH - 1;
+define symbol __region_CS5_start__              = CS5_SPACE_PRV_START;
+define symbol __region_CS5_end__                = CS5_SPACE_PRV_START + CS5_SPACE_PRV_LENGTH - 1;
+
+/************** SPI boot mode setting **************/
+define symbol __region_LDR_PARAM_start__        = FLASH_ADDRESS;
+define symbol __region_LDR_PARAM_end__          = FLASH_ADDRESS + 0x0000004B;
+define symbol __region_S_LOADER_STACK_start__   = FLASH_ADDRESS + 0x0000004C;
+define symbol __region_S_LOADER_STACK_end__     = FLASH_ADDRESS + 0x0000804B;
+
+define symbol __region_S_intvec_start__         = FLASH_ADDRESS + 0x20000;
+define symbol __region_S_intvec_end__           = FLASH_ADDRESS + 0x200FF;
+define symbol __region_S_RAM_start__            = FLASH_ADDRESS + 0x70000;
+define symbol __region_S_RAM_end__              = FLASH_ADDRESS + 0x7FFFF;
+/****************************************************/
+
+define region D_LOADER_STACK_region  = mem:[from __region_D_LOADER_STACK_start__   to __region_D_LOADER_STACK_end__];
+
+define region LDR_PARAM_region  = mem:[from __region_LDR_PARAM_start__   to __region_LDR_PARAM_end__];
+define region S_LOADER_STACK_region  = mem:[from __region_S_LOADER_STACK_start__   to __region_S_LOADER_STACK_end__];
+
+define region S_intvec_region = mem:[from __region_S_intvec_start__  to __region_S_intvec_end__];
+define region S_RAM_region    = mem:[from __region_S_RAM_start__  to __region_S_RAM_end__];
+
+define region DATA_NONCACHE_region           = mem:[from __region_DATA_NONCACHE_start__   to __region_DATA_NONCACHE_end__];
+define region DMAC_LINK_MODE_region          = mem:[from __region_DMAC_LINK_MODE_start__   to __region_DMAC_LINK_MODE_end__];
+define region SHARED_NONCACHE_BUFFER_region  = mem:[from __region_SHARED_NONCACHE_BUFFER_start__   to __region_SHARED_NONCACHE_BUFFER_end__];
+define region NONCACHE_BUFFER_region         = mem:[from __region_NONCACHE_BUFFER_start__   to __region_NONCACHE_BUFFER_end__];
+
+define region ATCM_region              = mem:[from __region_ATCM_start__  to __region_ATCM_end__ ];
+define region BTCM_region              = mem:[from __region_BTCM_start__  to __region_BTCM_end__ ];
+define region SYSTEM_RAM_region        = mem:[from __region_SYSTEM_RAM_start__  to __region_SYSTEM_RAM_end__ ];
+define region SYSTEM_RAM_MIRROR_region = mem:[from __region_SYSTEM_RAM_MIRROR_start__  to __region_SYSTEM_RAM_MIRROR_end__ ];
+define region XSPI0_CS0_MIRROR_region  = mem:[from __region_XSPI0_CS0_MIRROR_start__  to __region_XSPI0_CS0_MIRROR_end__ ];
+define region XSPI0_CS1_MIRROR_region  = mem:[from __region_XSPI0_CS1_MIRROR_start__  to __region_XSPI0_CS1_MIRROR_end__ ];
+define region XSPI1_CS0_MIRROR_region  = mem:[from __region_XSPI1_CS0_MIRROR_start__  to __region_XSPI1_CS0_MIRROR_end__ ];
+define region XSPI1_CS1_MIRROR_region  = mem:[from __region_XSPI1_CS1_MIRROR_start__  to __region_XSPI1_CS1_MIRROR_end__ ];
+define region CS0_MIRROR_region        = mem:[from __region_CS0_MIRROR_start__  to __region_CS0_MIRROR_end__ ];
+define region CS2_MIRROR_region        = mem:[from __region_CS2_MIRROR_start__  to __region_CS2_MIRROR_end__ ];
+define region CS3_MIRROR_region        = mem:[from __region_CS3_MIRROR_start__  to __region_CS3_MIRROR_end__ ];
+define region CS5_MIRROR_region        = mem:[from __region_CS5_MIRROR_start__  to __region_CS5_MIRROR_end__ ];
+define region XSPI0_CS0_region         = mem:[from __region_XSPI0_CS0_start__  to __region_XSPI0_CS0_end__ ];
+define region XSPI0_CS1_region         = mem:[from __region_XSPI0_CS1_start__  to __region_XSPI0_CS1_end__ ];
+define region XSPI1_CS0_region         = mem:[from __region_XSPI1_CS0_start__  to __region_XSPI1_CS0_end__ ];
+define region XSPI1_CS1_region         = mem:[from __region_XSPI1_CS1_start__  to __region_XSPI1_CS1_end__ ];
+define region CS0_region               = mem:[from __region_CS0_start__  to __region_CS0_end__ ];
+define region CS2_region               = mem:[from __region_CS2_start__  to __region_CS2_end__ ];
+define region CS3_region               = mem:[from __region_CS3_start__  to __region_CS3_end__ ];
+define region CS5_region               = mem:[from __region_CS5_start__  to __region_CS5_end__ ];
+
+define block LDR_PRG_RBLOCK with fixed order
+                             { ro code section .loader_text_init object startup_core.o,
+                               ro code object startup_core.o,
+                               ro code object system_core.o,
+                               ro code object startup.o,
+                               ro code object system.o,
+                               ro code object bsp_clocks.o,
+                               ro code object bsp_irq_core.o,
+                               ro code object bsp_irq.o,
+                               ro code object bsp_register_protection.o,
+                               ro code object r_ioport.o,
+                               ro code object bsp_cache.o,
+                               ro code section .warm_start_init }
+                               except { ro code section .intvec_init,
+                                        ro code section .reset_handler_init };
+define block LDR_PRG_WBLOCK with fixed order
+                             { rw code section .loader_text object startup_core.o,
+                               rw code object startup_core.o,
+                               rw code object system_core.o,
+                               rw code object startup.o,
+                               rw code object system.o,
+                               rw code object bsp_clocks.o,
+                               rw code object bsp_irq_core.o,
+                               rw code object bsp_irq.o,
+                               rw code object bsp_register_protection.o,
+                               rw code object r_ioport.o,
+                               rw code object bsp_cache.o,
+                               rw code section .warm_start }
+                               except { rw code section .intvec,
+                                        rw code section .reset_handler };
+define block LDR_DATA_ZBLOCK with alignment = 4
+                             { section .bss object startup_core.o,
+                               section .bss object system_core.o,
+                               section .bss object startup.o,
+                               section .bss object system.o,
+                               section .bss object bsp_clocks.o,
+                               section .bss object bsp_irq_core.o,
+                               section .bss object bsp_irq.o,
+                               section .bss object bsp_register_protection.o,
+                               section .bss object r_ioport.o,
+                               section .bss object bsp_cache.o,
+                               section .bss object bsp_io.o };
+define block LDR_DATA_RBLOCK with fixed order, alignment = 4
+                             { section .data_init object startup_core.o,
+                               section .data_init object system_core.o,
+                               section .data_init object startup.o,
+                               section .data_init object system.o,
+                               section .data_init object bsp_clocks.o,
+                               section .data_init object bsp_irq_core.o,
+                               section .data_init object bsp_irq.o,
+                               section .data_init object bsp_register_protection.o,
+                               section .data_init object r_ioport.o,
+                               section .data_init object bsp_cache.o,
+                               section .rodata_init object system_core.o };
+define block LDR_DATA_WBLOCK with fixed order, alignment = 4
+                             { section .data object startup_core.o,
+                               section .data object system_core.o,
+                               section .data object startup.o,
+                               section .data object system.o,
+                               section .data object bsp_clocks.o,
+                               section .data object bsp_irq_core.o,
+                               section .data object bsp_irq.o,
+                               section .data object bsp_register_protection.o,
+                               section .data object r_ioport.o,
+                               section .data object bsp_cache.o,
+                               section .rodata object system_core.o };
+
+define block HEAP_BLOCK with alignment = 8 { rw section HEAP };
+define block THREAD_STACK with alignment = 8 { rw section .stack* };
+define block SYS_STACK with alignment = 8 { rw section .sys_stack };
+define block SVC_STACK with alignment = 8 { rw section .svc_stack };
+define block IRQ_STACK with alignment = 8 { rw section .irq_stack };
+define block FIQ_STACK with alignment = 8 { rw section .fiq_stack };
+define block UND_STACK with alignment = 8 { rw section .und_stack };
+define block ABT_STACK with alignment = 8 { rw section .abt_stack };
+
+define block VECTOR_RBLOCK with alignment = 32 { ro code section .intvec_init};
+define block VECTOR_WBLOCK with alignment = 32 { rw code section .intvec};
+define block USER_PRG_RBLOCK with alignment = 4 { ro code };
+define block USER_PRG_WBLOCK with alignment = 4 { rw code };
+define block USER_DATA_ZBLOCK with alignment = 4 { section .bss };
+define block USER_DATA_RBLOCK with fixed order, alignment = 4
+                              { section .data_init,
+                                section __DLIB_PERTHREAD_init,
+                                section .rodata_init,
+                                section .version_init };
+define block USER_DATA_WBLOCK with fixed order, alignment = 4
+                              { section .data,
+                                section __DLIB_PERTHREAD,
+                                section .rodata,
+                                section .version };
+define block USER_DATA_NONCACHE_RBLOCK with alignment = 4 { section .data_noncache_init };
+define block USER_DATA_NONCACHE_WBLOCK with alignment = 4 { section .data_noncache };
+define block DMAC_LINK_MODE_ZBLOCK with alignment = 4 { section .dmac_link_mode* };
+define block SHARED_NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .shared_noncache_buffer* };
+define block NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .noncache_buffer* };
+
+initialize manually  { ro code object startup_core.o,
+                       ro code object system_core.o,
+                       ro code object startup.o,
+                       ro code object system.o,
+                       ro code object bsp_clocks.o,
+                       ro code object bsp_irq_core.o,
+                       ro code object bsp_irq.o,
+                       ro code object bsp_register_protection.o,
+                       ro code object r_ioport.o,
+                       ro code object bsp_cache.o,
+                       ro code section .intvec,
+                       ro code section .reset_handler,
+                       ro code section .warm_start,
+                       ro code,
+                       section .data,
+                       section __DLIB_PERTHREAD,
+                       section .rodata,
+                       section .version,
+                       section .data_noncache };
+
+do not initialize   { section .noinit,
+                      section .bss,
+                      section .dmac_link_mode*,
+                      section .shared_noncache_buffer*,
+                      section .noncache_buffer*,
+                      rw section HEAP,
+                      rw section .stack*,
+                      rw section .sys_stack,
+                      rw section .svc_stack,
+                      rw section .irq_stack,
+                      rw section .fiq_stack,
+                      rw section .und_stack,
+                      rw section .abt_stack };
+
+place at address mem: __ICFEDIT_intvec_start__ { block VECTOR_WBLOCK };
+
+place in LDR_PARAM_region { readonly section .loader_param };
+place at start of S_LOADER_STACK_region { block LDR_PRG_RBLOCK };
+place in S_LOADER_STACK_region { section LDR_DATA_RBLOCK, block LDR_DATA_RBLOCK };
+place in S_intvec_region { block VECTOR_RBLOCK };
+place in ROM_region   { block USER_PRG_RBLOCK, readonly };
+place in S_RAM_region { block USER_DATA_RBLOCK, block USER_DATA_NONCACHE_RBLOCK };
+
+place at start of D_LOADER_STACK_region { block LDR_PRG_WBLOCK };
+place in D_LOADER_STACK_region { section LDR_DATA_WBLOCK, block LDR_DATA_WBLOCK,
+                                 section LDR_DATA_ZBLOCK, block LDR_DATA_ZBLOCK };
+place in D_LOADER_STACK_region  { section SYS_STACK, block SYS_STACK,
+                                  section SVC_STACK, block SVC_STACK,
+                                  section IRQ_STACK, block IRQ_STACK,
+                                  section FIQ_STACK, block FIQ_STACK,
+                                  section UND_STACK, block UND_STACK,
+                                  section ABT_STACK, block ABT_STACK };
+place in RAM_region        { block USER_PRG_WBLOCK };
+place in RAM_region        { readwrite, last block CSTACK };
+place in RAM_region        { block USER_DATA_WBLOCK,
+                             block USER_DATA_ZBLOCK };
+place in RAM_region        { section HEAP_BLOCK, block HEAP_BLOCK,
+                             section THREAD_STACK, block THREAD_STACK };
+
+place in DATA_NONCACHE_region { block USER_DATA_NONCACHE_WBLOCK };
+place in DMAC_LINK_MODE_region { block DMAC_LINK_MODE_ZBLOCK };
+place in SHARED_NONCACHE_BUFFER_region { block SHARED_NONCACHE_BUFFER_ZBLOCK };
+place in NONCACHE_BUFFER_region { block NONCACHE_BUFFER_ZBLOCK };
+place in ATCM_region { };
+place in BTCM_region { };
+place in SYSTEM_RAM_region { };
+place in SYSTEM_RAM_MIRROR_region { };
+place in XSPI0_CS0_MIRROR_region { };
+place in XSPI0_CS1_MIRROR_region { };
+place in XSPI1_CS0_MIRROR_region { };
+place in XSPI1_CS1_MIRROR_region { };
+place in CS0_MIRROR_region { };
+place in CS2_MIRROR_region { };
+place in CS3_MIRROR_region { };
+place in CS5_MIRROR_region { };
+place in XSPI0_CS0_region { };
+place in XSPI0_CS1_region { };
+place in XSPI1_CS0_region { };
+place in XSPI1_CS1_region { };
+place in CS0_region { };
+place in CS2_region { };
+place in CS3_region { };
+place in CS5_region { };
\ No newline at end of file
diff --git a/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot.ld b/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot.ld
new file mode 100644
index 00000000..adfd80c2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot.ld
@@ -0,0 +1,689 @@
+/*
+                  Linker File for Renesas RZ/N2 FSP
+*/
+
+/* The memory information for each device is done in memory regions file.
+ * The starting address and length of memory not defined in memory regions file are defined as 0. */
+ 
+/* generated memory regions file - do not edit */
+ATCM_START  = 0x00000000;
+ATCM_LENGTH = 0x20000;
+BTCM_START  = 0x00100000;
+BTCM_LENGTH = 0x20000;
+SYSTEM_RAM_START  = 0x10000000;
+SYSTEM_RAM_LENGTH = 0x180000;
+SYSTEM_RAM_MIRROR_START  = 0x30000000;
+SYSTEM_RAM_MIRROR_LENGTH = 0x180000;
+xSPI0_CS0_SPACE_MIRROR_START  = 0x40000000;
+xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+xSPI0_CS1_SPACE_MIRROR_START  = 0x44000000;
+xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000;
+xSPI1_CS0_SPACE_MIRROR_START  = 0x48000000;
+xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+CS0_SPACE_MIRROR_START  = 0x50000000;
+CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+CS2_SPACE_MIRROR_START  = 0x54000000;
+CS2_SPACE_MIRROR_LENGTH = 0x4000000;
+CS3_SPACE_MIRROR_START  = 0x58000000;
+CS3_SPACE_MIRROR_LENGTH = 0x4000000;
+CS5_SPACE_MIRROR_START  = 0x5C000000;
+CS5_SPACE_MIRROR_LENGTH = 0x4000000;
+xSPI0_CS0_SPACE_START  = 0x60000000;
+xSPI0_CS0_SPACE_LENGTH = 0x4000000;
+xSPI0_CS1_SPACE_START  = 0x64000000;
+xSPI0_CS1_SPACE_LENGTH = 0x4000000;
+xSPI1_CS0_SPACE_START  = 0x68000000;
+xSPI1_CS0_SPACE_LENGTH = 0x4000000;
+CS0_SPACE_START  = 0x70000000;
+CS0_SPACE_LENGTH = 0x4000000;
+CS2_SPACE_START  = 0x74000000;
+CS2_SPACE_LENGTH = 0x4000000;
+CS3_SPACE_START  = 0x78000000;
+CS3_SPACE_LENGTH = 0x4000000;
+CS5_SPACE_START  = 0x7C000000;
+CS5_SPACE_LENGTH = 0x4000000;
+CR52_0 = 0;
+
+ATCM_PRV_START = DEFINED(ATCM_START) ? ATCM_START : 0;
+ATCM_PRV_LENGTH = DEFINED(ATCM_LENGTH) ? ATCM_LENGTH : 0;
+BTCM_PRV_START = DEFINED(BTCM_START) ? BTCM_START : 0;
+BTCM_PRV_LENGTH = DEFINED(BTCM_LENGTH) ? BTCM_LENGTH : 0;
+SYSTEM_RAM_PRV_START = DEFINED(SYSTEM_RAM_START) ? SYSTEM_RAM_START : 0;
+SYSTEM_RAM_PRV_LENGTH = DEFINED(SYSTEM_RAM_LENGTH) ? SYSTEM_RAM_LENGTH : 0;
+SYSTEM_RAM_MIRROR_PRV_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START : 0;
+SYSTEM_RAM_MIRROR_PRV_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? SYSTEM_RAM_MIRROR_LENGTH : 0;
+xSPI0_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS0_SPACE_MIRROR_START) ? xSPI0_CS0_SPACE_MIRROR_START : 0;
+xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_MIRROR_LENGTH) ? xSPI0_CS0_SPACE_MIRROR_LENGTH : 0;
+xSPI0_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS1_SPACE_MIRROR_START) ? xSPI0_CS1_SPACE_MIRROR_START : 0;
+xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_MIRROR_LENGTH) ? xSPI0_CS1_SPACE_MIRROR_LENGTH : 0;
+xSPI1_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS0_SPACE_MIRROR_START) ? xSPI1_CS0_SPACE_MIRROR_START : 0;
+xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_MIRROR_LENGTH) ? xSPI1_CS0_SPACE_MIRROR_LENGTH : 0;
+xSPI1_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS1_SPACE_MIRROR_START) ? xSPI1_CS1_SPACE_MIRROR_START : 0;
+xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_MIRROR_LENGTH) ? xSPI1_CS1_SPACE_MIRROR_LENGTH : 0;
+CS0_SPACE_MIRROR_PRV_START = DEFINED(CS0_SPACE_MIRROR_START) ? CS0_SPACE_MIRROR_START : 0;
+CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS0_SPACE_MIRROR_LENGTH) ? CS0_SPACE_MIRROR_LENGTH : 0;
+CS2_SPACE_MIRROR_PRV_START = DEFINED(CS2_SPACE_MIRROR_START) ? CS2_SPACE_MIRROR_START : 0;
+CS2_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS2_SPACE_MIRROR_LENGTH) ? CS2_SPACE_MIRROR_LENGTH : 0;
+CS3_SPACE_MIRROR_PRV_START = DEFINED(CS3_SPACE_MIRROR_START) ? CS3_SPACE_MIRROR_START : 0;
+CS3_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS3_SPACE_MIRROR_LENGTH) ? CS3_SPACE_MIRROR_LENGTH : 0;
+CS5_SPACE_MIRROR_PRV_START = DEFINED(CS5_SPACE_MIRROR_START) ? CS5_SPACE_MIRROR_START : 0;
+CS5_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS5_SPACE_MIRROR_LENGTH) ? CS5_SPACE_MIRROR_LENGTH : 0;
+xSPI0_CS0_SPACE_PRV_START = DEFINED(xSPI0_CS0_SPACE_START) ? xSPI0_CS0_SPACE_START : 0;
+xSPI0_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_LENGTH) ? xSPI0_CS0_SPACE_LENGTH : 0;
+xSPI0_CS1_SPACE_PRV_START = DEFINED(xSPI0_CS1_SPACE_START) ? xSPI0_CS1_SPACE_START : 0;
+xSPI0_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_LENGTH) ? xSPI0_CS1_SPACE_LENGTH : 0;
+xSPI1_CS0_SPACE_PRV_START = DEFINED(xSPI1_CS0_SPACE_START) ? xSPI1_CS0_SPACE_START : 0;
+xSPI1_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_LENGTH) ? xSPI1_CS0_SPACE_LENGTH : 0;
+xSPI1_CS1_SPACE_PRV_START = DEFINED(xSPI1_CS1_SPACE_START) ? xSPI1_CS1_SPACE_START : 0;
+xSPI1_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_LENGTH) ? xSPI1_CS1_SPACE_LENGTH : 0;
+CS0_SPACE_PRV_START = DEFINED(CS0_SPACE_START) ? CS0_SPACE_START : 0;
+CS0_SPACE_PRV_LENGTH = DEFINED(CS0_SPACE_LENGTH) ? CS0_SPACE_LENGTH : 0;
+CS2_SPACE_PRV_START = DEFINED(CS2_SPACE_START) ? CS2_SPACE_START : 0;
+CS2_SPACE_PRV_LENGTH = DEFINED(CS2_SPACE_LENGTH) ? CS2_SPACE_LENGTH : 0;
+CS3_SPACE_PRV_START = DEFINED(CS3_SPACE_START) ? CS3_SPACE_START : 0;
+CS3_SPACE_PRV_LENGTH = DEFINED(CS3_SPACE_LENGTH) ? CS3_SPACE_LENGTH : 0;
+CS5_SPACE_PRV_START = DEFINED(CS5_SPACE_START) ? CS5_SPACE_START : 0;
+CS5_SPACE_PRV_LENGTH = DEFINED(CS5_SPACE_LENGTH) ? CS5_SPACE_LENGTH : 0;
+PCIE0_MIRROR_PRV_START = DEFINED(PCIE0_MIRROR_START) ? PCIE0_MIRROR_START : 0;
+PCIE0_MIRROR_PRV_LENGTH = DEFINED(PCIE0_MIRROR_LENGTH) ? PCIE0_MIRROR_LENGTH : 0;
+PCIE1_MIRROR_PRV_START = DEFINED(PCIE1_MIRROR_START) ? PCIE1_MIRROR_START : 0;
+PCIE1_MIRROR_PRV_LENGTH = DEFINED(PCIE1_MIRROR_LENGTH) ? PCIE1_MIRROR_LENGTH : 0;
+DDR_MIRROR0_PRV_START = DEFINED(DDR_MIRROR0_START) ? DDR_MIRROR0_START : 0;
+DDR_MIRROR0_PRV_LENGTH = DEFINED(DDR_MIRROR0_LENGTH) ? DDR_MIRROR0_LENGTH : 0;
+DDR_MIRROR1_PRV_START = DEFINED(DDR_MIRROR1_START) ? DDR_MIRROR1_START : 0;
+DDR_MIRROR1_PRV_LENGTH = DEFINED(DDR_MIRROR1_LENGTH) ? DDR_MIRROR1_LENGTH : 0;
+DDR_MIRROR_PRV_START = DEFINED(DDR_MIRROR_START) ? DDR_MIRROR_START : 0;
+DDR_MIRROR_PRV_LENGTH = DEFINED(DDR_MIRROR_LENGTH) ? DDR_MIRROR_LENGTH : 0;
+DDR_PRV_START = DEFINED(DDR_START) ? DDR_START : 0;
+DDR_PRV_LENGTH = DEFINED(DDR_LENGTH) ? DDR_LENGTH : 0;
+PCIE0_PRV_START = DEFINED(PCIE0_START) ? PCIE0_START : 0;
+PCIE0_PRV_LENGTH = DEFINED(PCIE0_LENGTH) ? PCIE0_LENGTH : 0;
+PCIE1_PRV_START = DEFINED(PCIE1_START) ? PCIE1_START : 0;
+PCIE1_PRV_LENGTH = DEFINED(PCIE1_LENGTH) ? PCIE1_LENGTH : 0;
+SECONDARY_PRV = DEFINED(SECONDARY) ? SECONDARY : 0;
+
+_RZN_ORDINAL = (0 == SECONDARY_PRV) ? 1 : 2;
+HAS_SYSTEM_RAM_MIRROR = DEFINED(SYSTEM_RAM_MIRROR_START) ? 1 : 0;
+
+SYSTEM_RAM_ALIGN_START            = ALIGN(SYSTEM_RAM_PRV_START, 0x00020000);
+SYSTEM_RAM_ALIGN_LENGTH           = SYSTEM_RAM_PRV_LENGTH - (SYSTEM_RAM_PRV_LENGTH % 0x00020000);
+SYSTEM_RAM_MIRROR_OFFSET          = DEFINED(SYSTEM_RAM_START) ?
+                                        (0 == HAS_SYSTEM_RAM_MIRROR) ?
+                                            (DEFINED(CR52_0) || DEFINED(CR52_1)) ?
+                                                0x00000000 :
+                                                0x00200000 :
+                                            0x20000000 :
+                                        0;
+
+xSPI0_CS0_SPACE_ALIGN_START       = ALIGN(xSPI0_CS0_SPACE_PRV_START, 0x00020000);
+xSPI0_CS0_SPACE_ALIGN_LENGTH      = xSPI0_CS0_SPACE_PRV_LENGTH - (xSPI0_CS0_SPACE_PRV_LENGTH % 0x00020000);
+
+RAM_START                         = SYSTEM_RAM_ALIGN_START;
+RAM_LENGTH                        = SYSTEM_RAM_ALIGN_LENGTH;
+LOADER_START                      = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? BTCM_PRV_START : SYSTEM_RAM_ALIGN_START;
+LOADER_LENGTH                     = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? BTCM_PRV_LENGTH : SYSTEM_RAM_ALIGN_LENGTH;
+ROM_START                         = (1 == _RZN_ORDINAL) ? xSPI0_CS0_SPACE_ALIGN_START : SYSTEM_RAM_ALIGN_START;
+ROM_LENGTH                        = (1 == _RZN_ORDINAL) ? xSPI0_CS0_SPACE_ALIGN_LENGTH : SYSTEM_RAM_ALIGN_LENGTH;
+
+FLASH_CONTENTS_OFFSET             = (0 == HAS_SYSTEM_RAM_MIRROR) ? 0x00000050 : 0x0000004C;
+LOADER_TEXT_OFFSET                = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? 0x00002000 : 0x00001000;
+TEXT_OFFSET                       = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? 0x00000100 : 0x00010000;
+IMAGE_INFO_OFFSET                 = 0x00000800;
+
+INTVEC_ADDRESS                    = RAM_START;
+LOADER_TEXT_ADDRESS               = LOADER_START + LOADER_TEXT_OFFSET;
+TEXT_ADDRESS                      = ((1 == _RZN_ORDINAL) || ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1)))) ? RAM_START + TEXT_OFFSET : noncache_flash_contents_end;
+
+/* Define starting addresses and length for data_noncache, DMAC link mode data, CPU-shared non-cache, and CPU-specific non-cache areas. */
+DATA_NONCACHE_OFFSET              = DEFINED(SYSTEM_RAM_START) ? 0x00048000 : 0;
+DMAC_LINK_MODE_OFFSET             = DEFINED(SYSTEM_RAM_START) ? 0x00044000 : 0;
+SHARED_NONCACHE_BUFFER_OFFSET     = DEFINED(SYSTEM_RAM_START) ? 0x00040000 : 0;
+NONCACHE_BUFFER_OFFSET            = DEFINED(SYSTEM_RAM_START) ? 0x00020000 : 0;
+
+SYSTEM_RAM_END_ADDRESS            = SYSTEM_RAM_ALIGN_START + SYSTEM_RAM_ALIGN_LENGTH;
+SYSTEM_RAM_MIRROR_END_ADDRESS     = SYSTEM_RAM_ALIGN_START + SYSTEM_RAM_ALIGN_LENGTH + SYSTEM_RAM_MIRROR_OFFSET;
+
+DATA_NONCACHE_START               = (1 == _RZN_ORDINAL) ?
+                                        SYSTEM_RAM_MIRROR_END_ADDRESS - DATA_NONCACHE_OFFSET :
+                                        ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                            __ThreadStackLimit :
+                                            _mdata_noncache + SYSTEM_RAM_MIRROR_OFFSET;
+DMAC_LINK_MODE_START              = (1 == _RZN_ORDINAL) ?
+                                        SYSTEM_RAM_MIRROR_END_ADDRESS - DMAC_LINK_MODE_OFFSET :
+                                        ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                            _data_noncache_end :
+                                            _mdmac_link_mode + SYSTEM_RAM_MIRROR_OFFSET;
+NONCACHE_BUFFER_START             = (1 == _RZN_ORDINAL) ?
+                                        SYSTEM_RAM_MIRROR_END_ADDRESS - NONCACHE_BUFFER_OFFSET :
+                                        ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                            _dmac_link_mode_end :
+                                            _mncbuffer + SYSTEM_RAM_MIRROR_OFFSET;
+SHARED_NONCACHE_BUFFER_START      = SYSTEM_RAM_MIRROR_END_ADDRESS - SHARED_NONCACHE_BUFFER_OFFSET;
+
+data_noncache_size                = _data_noncache_end - _data_noncache_start;
+dmac_link_mode_size               = _dmac_link_mode_end - _dmac_link_mode_start;
+sncbuffer_size                    = _sncbuffer_end - _sncbuffer_start;
+ncbuffer_size                     = _ncbuffer_end - _ncbuffer_start;
+
+LCDC_FRAME_BUFFER_OFFSET          = (DEFINED(CR52_0) || DEFINED(CR52_1)) ?
+                                        DEFINED(DDR_MIRROR1_START) ?
+                                            0x04000000 :
+                                            0 :
+                                        DEFINED(DDR_MIRROR_START) ?
+                                            0x04000000 :
+                                            0;
+LCDC_FRAME_BUFFER_START           = (DEFINED(CR52_0) || DEFINED(CR52_1)) ?
+                                        DDR_MIRROR1_PRV_START + DDR_MIRROR1_PRV_LENGTH - LCDC_FRAME_BUFFER_OFFSET :
+                                        DDR_MIRROR_PRV_START + DDR_MIRROR_PRV_LENGTH - LCDC_FRAME_BUFFER_OFFSET;
+LCDC_FRAME_BUFFER_LENGTH          = LCDC_FRAME_BUFFER_OFFSET;
+
+MEMORY
+{
+    ATCM : ORIGIN = ATCM_PRV_START, LENGTH = ATCM_PRV_LENGTH
+    BTCM : ORIGIN = BTCM_PRV_START, LENGTH = BTCM_PRV_LENGTH
+    SYSTEM_RAM : ORIGIN = SYSTEM_RAM_ALIGN_START, LENGTH = SYSTEM_RAM_ALIGN_LENGTH
+    SYSTEM_RAM_MIRROR : ORIGIN = SYSTEM_RAM_MIRROR_PRV_START, LENGTH = SYSTEM_RAM_MIRROR_PRV_LENGTH
+    xSPI0_CS0_SPACE_MIRROR : ORIGIN = xSPI0_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH
+    xSPI0_CS1_SPACE_MIRROR : ORIGIN = xSPI0_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH
+    xSPI1_CS0_SPACE_MIRROR : ORIGIN = xSPI1_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH
+    xSPI1_CS1_SPACE_MIRROR : ORIGIN = xSPI1_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH
+    CS0_SPACE_MIRROR : ORIGIN = CS0_SPACE_MIRROR_PRV_START, LENGTH = CS0_SPACE_MIRROR_PRV_LENGTH
+    CS2_SPACE_MIRROR : ORIGIN = CS2_SPACE_MIRROR_PRV_START, LENGTH = CS2_SPACE_MIRROR_PRV_LENGTH
+    CS3_SPACE_MIRROR : ORIGIN = CS3_SPACE_MIRROR_PRV_START, LENGTH = CS3_SPACE_MIRROR_PRV_LENGTH
+    CS5_SPACE_MIRROR : ORIGIN = CS5_SPACE_MIRROR_PRV_START, LENGTH = CS5_SPACE_MIRROR_PRV_LENGTH
+    xSPI0_CS0_SPACE : ORIGIN = xSPI0_CS0_SPACE_ALIGN_START, LENGTH = xSPI0_CS0_SPACE_ALIGN_LENGTH
+    xSPI0_CS1_SPACE : ORIGIN = xSPI0_CS1_SPACE_PRV_START, LENGTH = xSPI0_CS1_SPACE_PRV_LENGTH
+    xSPI1_CS0_SPACE : ORIGIN = xSPI1_CS0_SPACE_PRV_START, LENGTH = xSPI1_CS0_SPACE_PRV_LENGTH
+    xSPI1_CS1_SPACE : ORIGIN = xSPI1_CS1_SPACE_PRV_START, LENGTH = xSPI1_CS1_SPACE_PRV_LENGTH
+    CS0_SPACE : ORIGIN = CS0_SPACE_PRV_START, LENGTH = CS0_SPACE_PRV_LENGTH
+    CS2_SPACE : ORIGIN = CS2_SPACE_PRV_START, LENGTH = CS2_SPACE_PRV_LENGTH
+    CS3_SPACE : ORIGIN = CS3_SPACE_PRV_START, LENGTH = CS3_SPACE_PRV_LENGTH
+    CS5_SPACE : ORIGIN = CS5_SPACE_PRV_START, LENGTH = CS5_SPACE_PRV_LENGTH
+    PCIE0_MIRROR : ORIGIN = PCIE0_MIRROR_PRV_START, LENGTH = PCIE0_MIRROR_PRV_LENGTH
+    PCIE1_MIRROR : ORIGIN = PCIE1_MIRROR_PRV_START, LENGTH = PCIE1_MIRROR_PRV_LENGTH
+    DDR_MIRROR0 : ORIGIN = DDR_MIRROR0_PRV_START, LENGTH = DDR_MIRROR0_PRV_LENGTH
+    DDR_MIRROR1 : ORIGIN = DDR_MIRROR1_PRV_START, LENGTH = DDR_MIRROR1_PRV_LENGTH
+    DDR_MIRROR : ORIGIN = DDR_MIRROR_PRV_START, LENGTH = DDR_MIRROR_PRV_LENGTH
+    DDR : ORIGIN = DDR_PRV_START, LENGTH = DDR_PRV_LENGTH
+    PCIE0 : ORIGIN = PCIE0_PRV_START, LENGTH = PCIE0_PRV_LENGTH
+    PCIE1 : ORIGIN = PCIE1_PRV_START, LENGTH = PCIE1_PRV_LENGTH
+    RAM_TEXT : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+    RAM_DATA : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+    LOADER_TEXT_STACK : ORIGIN = LOADER_START, LENGTH = LOADER_LENGTH
+    LOADER_DATA_STACK : ORIGIN = LOADER_START, LENGTH = LOADER_LENGTH
+    FLASH_CONTENTS : ORIGIN = ROM_START, LENGTH = ROM_LENGTH
+    NONCACHE : ORIGIN = SYSTEM_RAM_ALIGN_START + SYSTEM_RAM_MIRROR_OFFSET, LENGTH = SYSTEM_RAM_ALIGN_LENGTH
+    LCDC_FRAME_BUFFER : ORIGIN = LCDC_FRAME_BUFFER_START, LENGTH = LCDC_FRAME_BUFFER_LENGTH
+}
+
+SECTIONS
+{
+    LOADER_PARAM_ADDRESS = (1 == _RZN_ORDINAL) ? xSPI0_CS0_SPACE_ALIGN_START : _loader_text_start;
+    .loader_param LOADER_PARAM_ADDRESS : AT (LOADER_PARAM_ADDRESS)
+    {
+        KEEP(*(.loader_param))
+    } > FLASH_CONTENTS
+
+    FLASH_CONTENTS_ADDRESS = (1 == _RZN_ORDINAL) ? LOADER_PARAM_ADDRESS + FLASH_CONTENTS_OFFSET : _loader_text_start;
+    .flash_contents FLASH_CONTENTS_ADDRESS : AT (FLASH_CONTENTS_ADDRESS)
+    {
+        _mloader_text = .;
+        . = (1 == _RZN_ORDINAL) ? . + (_loader_text_end - _loader_text_start) : .;
+        . = ALIGN(8);
+        _mloader_data = .;
+        . = (1 == _RZN_ORDINAL) ? . + (_loader_data_end - _loader_data_start) : .;
+        . = ALIGN(8);
+        _mfvector = .;
+        . = (1 == _RZN_ORDINAL) ? . + (_fvector_end - _fvector_start) : .;
+        . = ALIGN(8);
+        _mtext = .;
+        . = (1 == _RZN_ORDINAL) ? . + (__text_end - __text_start) +
+                                      (_rvectors_end - _rvectors_start) +
+                                      (__extab_end - __extab_start) +
+                                      (__exidx_end - __exidx_start) : .;
+        . = ALIGN(8);
+        _mdata = .;
+        . = (1 == _RZN_ORDINAL) ? . + (__data_end - __data_start) +
+                                      (__got_end - __got_start) : .;
+        flash_contents_end = .;
+    } > FLASH_CONTENTS
+
+    NONCACHE_FLASH_CONTENTS_ADDRESS = (1 == _RZN_ORDINAL) ? flash_contents_end : RAM_START + TEXT_OFFSET;
+    .noncache_flash_contents NONCACHE_FLASH_CONTENTS_ADDRESS : AT (NONCACHE_FLASH_CONTENTS_ADDRESS)
+    {
+        . = (0 != data_noncache_size) ? ALIGN(8) : .;
+        _mdata_noncache = .;
+        . = . + data_noncache_size;
+        . = (0 != dmac_link_mode_size) ? ALIGN(8) : .;
+        _mdmac_link_mode = .;
+        . = . + dmac_link_mode_size;
+        . = (0 != sncbuffer_size) ? ALIGN(32) : .;
+        _msncbuffer = .;
+        . = . + sncbuffer_size;
+        . = (0 != ncbuffer_size) ? ALIGN(32) : .;
+        _mncbuffer = .;
+        . = . + ncbuffer_size;
+        noncache_flash_contents_end = .;
+    } > FLASH_CONTENTS
+
+    LOADER_TEXT_IMAGE                 = (1 == _RZN_ORDINAL) ? _mloader_text : _loader_text_start;
+    .loader_text LOADER_TEXT_ADDRESS : AT (LOADER_TEXT_IMAGE)
+    {
+        _loader_text_start = .;
+        *(.loader_text)
+        */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.text*)
+        */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.text*)
+        */fsp/src/bsp/mcu/all/bsp_clocks.o(.text*)
+        */fsp/src/bsp/mcu/all/bsp_irq.o(.text*)
+        */fsp/src/bsp/mcu/all/bsp_semaphore.o(.text*)
+        */fsp/src/bsp/mcu/all/bsp_register_protection.o(.text*)
+        */fsp/src/bsp/mcu/all/bsp_cache.o(.text*)
+        */fsp/src/bsp/mcu/all/bsp_tzc400.o(.text*)
+        */fsp/src/bsp/mcu/all/bsp_address_expander.o(.text*)
+        */fsp/src/r_ioport/r_ioport.o(.text*)
+        KEEP(*(.warm_start))
+        KEEP(*(.loader_user_data*))
+        . = ALIGN(0x200);
+        _loader_text_end = .;
+    } > LOADER_TEXT_STACK
+
+    LOADER_DATA_IMAGE = (1 == _RZN_ORDINAL) ? _mloader_data : _loader_data_start;
+    .loader_data _loader_text_end : AT (LOADER_DATA_IMAGE)
+    {
+        _loader_data_start = .;
+        __loader_data_start = .;
+        */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.data*)
+        */fsp/src/bsp/cmsis/Device/RENESAS/Source/*/system_core.o(.rodata*)
+        */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.data*)
+        */fsp/src/bsp/mcu/all/bsp_clocks.o(.data*)
+        */fsp/src/bsp/mcu/all/bsp_irq.o(.data*)
+        */fsp/src/bsp/mcu/all/bsp_semaphore.o(.data*)
+        */fsp/src/bsp/mcu/all/bsp_register_protection.o(.data*)
+        */fsp/src/bsp/mcu/all/bsp_register_protection.o(.rodata*)
+        */fsp/src/bsp/mcu/all/bsp_cache.o(.data*)
+        */fsp/src/bsp/mcu/all/bsp_tzc400.o(.data*)
+        */fsp/src/bsp/mcu/all/bsp_tzc400.o(.rodata*)
+        */fsp/src/bsp/mcu/all/bsp_address_expander.o(.data*)
+        */fsp/src/r_ioport/r_ioport.o(.data*)
+        . = ALIGN(8);
+        __loader_data_end = .;
+        __loader_bss_start = .;
+        */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.bss*)
+        */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.bss*)
+        */fsp/src/bsp/mcu/all/bsp_clocks.o(.bss*)
+        */fsp/src/bsp/mcu/all/bsp_irq.o(.bss*)
+        */fsp/src/bsp/mcu/all/bsp_semaphore.o(.bss*)
+        */fsp/src/bsp/mcu/all/bsp_register_protection.o(.bss*)
+        */fsp/src/bsp/mcu/all/bsp_cache.o(.bss*)
+        */fsp/src/bsp/mcu/all/bsp_tzc400.o(.bss*)
+        */fsp/src/bsp/mcu/all/bsp_address_expander.o(.bss*)
+        */fsp/src/r_ioport/r_ioport.o(.bss*)
+        KEEP(*(.ttbr))
+        */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(COMMON)
+        */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(COMMON)
+        */fsp/src/bsp/mcu/all/bsp_clocks.o(COMMON)
+        */fsp/src/bsp/mcu/all/bsp_irq.o(COMMON)
+        */fsp/src/bsp/mcu/all/bsp_semaphore.o(COMMON)
+        */fsp/src/bsp/mcu/all/bsp_register_protection.o(.COMMON)
+        */fsp/src/bsp/mcu/all/bsp_cache.o(COMMON)
+        */fsp/src/bsp/mcu/all/bsp_tzc400.o(COMMON)
+        */fsp/src/bsp/mcu/all/bsp_address_expander.o(COMMON)
+        */fsp/src/r_ioport/r_ioport.o(.COMMON)
+        . = ALIGN(8);
+        __loader_bss_end = . ;
+        */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.software_reset) /* Do not initialize */
+        _loader_data_end = .;
+    } > LOADER_DATA_STACK
+
+    INTVEC_IMAGE = (1 == _RZN_ORDINAL) ? _mfvector : _fvector_start;
+    .intvec INTVEC_ADDRESS : AT (INTVEC_IMAGE)
+    {
+        _fvector_start = .;
+        KEEP(*(.intvec))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x080))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x100))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x180))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x200))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x280))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x300))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x380))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x400))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x480))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x500))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x580))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x600))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x680))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x700))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x780))
+        _fvector_end = .;
+    } > RAM_TEXT
+
+    IMAGE_INFO_ADDRESS = RAM_START + IMAGE_INFO_OFFSET;
+    .image_info IMAGE_INFO_ADDRESS : AT (IMAGE_INFO_ADDRESS)
+    {
+        _image_info_start = .;
+        KEEP(*(.image_info))
+        _image_info_end = .;
+    } > RAM_DATA
+
+    TEXT_IMAGE = (1 == _RZN_ORDINAL) ? _mtext : _text_start;
+    .text TEXT_ADDRESS : AT (TEXT_IMAGE)
+    {
+        _text_start = .;
+        __text_start = .;
+
+        *(.text*)
+
+        KEEP(*(.reset_handler))
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+        _ctor_end = .;
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+        _dtor_end = .;
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        /* new GCC version uses .init_array */
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        KEEP(*(FalPartTable))
+
+        KEEP(*(.eh_frame*))
+
+        __text_end = .;
+    } > RAM_TEXT
+    .rvectors :
+    {
+        _rvectors_start = .;
+        KEEP(*(.rvectors))
+        _rvectors_end = .;
+    } > RAM_TEXT
+    .ARM.extab :
+    {
+        __extab_start = .;
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        __extab_end = .;
+    } > RAM_TEXT
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+        _text_end = .;
+    } > RAM_TEXT
+
+    DATA_IMAGE = (1 == _RZN_ORDINAL) ? _mdata : _data_start;
+    .data _text_end :  AT (DATA_IMAGE)
+    {
+        _data_start = .;
+        __data_start = .;
+
+        *(vtable)
+        *(.data.*)
+        *(.data)
+
+        *(.rodata*)
+        _erodata = .;
+
+        . = ALIGN(8);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(8);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(8);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(8);
+
+        __data_end = .;
+    } > RAM_DATA
+    .got :
+    {
+        __got_start = .;
+        *(.got)
+        *(.got.plt)
+        __got_end = .;
+
+        /* All data end */
+        _data_end = .;
+    } > RAM_DATA
+    .bss :
+    {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(8);
+        __bss_end__ = .;
+        _ebss = .;
+        _end = .;
+    } > RAM_DATA
+    .heap (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM_DATA
+    .aarch64_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __AArch64StackBase = .;
+        /* Place the Thread stacks here. */
+        KEEP(*(.aarch64_stack*))
+        __AArch64StackLimit = .;
+    } > RAM_DATA
+    .thread_stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        __ThreadStackBase = .;
+        /* Place the Thread stacks here. */
+        KEEP(*(.stack*))
+        __ThreadStackLimit = .;
+    } > RAM_DATA
+    .sys_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __SysStackBase = .;
+        /* Place the sys_stack here. */
+        KEEP(*(.sys_stack))
+        __SysStackLimit = .;
+    } > LOADER_DATA_STACK
+    .svc_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __SvcStackBase = .;
+        /* Place the svc_stack here. */
+        KEEP(*(.svc_stack))
+        __SvcStackLimit = .;
+    } > LOADER_DATA_STACK
+    .irq_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __IrqStackBase = .;
+        /* Place the irq_stack here. */
+        KEEP(*(.irq_stack))
+        __IrqStackLimit = .;
+    } > LOADER_DATA_STACK
+    .fiq_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __FiqStackBase = .;
+        /* Place the fiq_stack here. */
+        KEEP(*(.fiq_stack))
+        __FiqStackLimit = .;
+    } > LOADER_DATA_STACK
+    .und_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __UndStackBase = .;
+        /* Place the und_stack here. */
+        KEEP(*(.und_stack))
+        __UndStackLimit = .;
+    } > LOADER_DATA_STACK
+    .abt_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __AbtStackBase = .;
+        /* Place the abt_stack here. */
+        KEEP(*(.abt_stack))
+        __AbtStackLimit = .;
+    } > LOADER_DATA_STACK
+
+    DATA_NONCACHE_INIT_START = (1 == _RZN_ORDINAL) ?
+                                   _mdata_noncache :
+                                   ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                       __ThreadStackLimit :
+                                       _mdata_noncache;
+    .data_noncache DATA_NONCACHE_START : AT (DATA_NONCACHE_INIT_START)
+    {
+        . = ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ? ALIGN(64) : ALIGN(8);
+        _data_noncache_start = .;
+        KEEP(*(.data_noncache*))
+        _data_noncache_end = .;
+    } > NONCACHE
+
+    DMAC_LINK_MODE_INIT_START = (1 == _RZN_ORDINAL) ?
+                                    _mdmac_link_mode :
+                                    ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                        _data_noncache_end :
+                                        _mdmac_link_mode;
+    .dmac_link_mode DMAC_LINK_MODE_START : AT (DMAC_LINK_MODE_INIT_START)
+    {
+        . = ALIGN(8);
+        _dmac_link_mode_start = .;
+        KEEP(*(.dmac_link_mode*))
+        _dmac_link_mode_end = .;
+    } > NONCACHE
+
+    SHARED_NONCACHE_BUFFER_INIT_START = (1 == _RZN_ORDINAL) ?
+                                            _msncbuffer :
+                                            ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                                _ncbuffer_end :
+                                                _msncbuffer;
+    .shared_noncache_buffer SHARED_NONCACHE_BUFFER_START : AT (SHARED_NONCACHE_BUFFER_INIT_START)
+    {
+        . = ALIGN(32);
+        _sncbuffer_start = .;
+        KEEP(*(.shared_noncache_buffer*))
+        _sncbuffer_end = .;
+    } > NONCACHE
+
+    NONCACHE_BUFFER_INIT_START = (1 == _RZN_ORDINAL) ?
+                                     _mncbuffer :
+                                     ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                         _dmac_link_mode_end :
+                                         _mncbuffer;
+    .noncache_buffer NONCACHE_BUFFER_START : AT (NONCACHE_BUFFER_INIT_START)
+    {
+        . = ALIGN(32);
+        _ncbuffer_start = .;
+        KEEP(*(.noncache_buffer*))
+        _ncbuffer_end = .;
+    } > NONCACHE
+
+    .lcdc_frame_buffer (NOLOAD) :
+    {
+        . = ALIGN(512);
+        _lcdc_frame_buffer_start = .;
+        KEEP(*(.lcdc_frame_buffer*))
+        _lcdc_frame_buffer_end = .;
+    } > LCDC_FRAME_BUFFER
+
+    SECONDARY_START = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? SYSTEM_RAM_ALIGN_START : ALIGN(__ThreadStackLimit, 0x00020000);
+    SECONDARY_IMAGE = (1 == _RZN_ORDINAL) ? ALIGN(noncache_flash_contents_end, 0x00020000) : SECONDARY_START;
+    .secondary SECONDARY_START : AT (SECONDARY_IMAGE)
+    {
+        . = ALIGN(0x20000);
+        _secondary_start = .;
+        KEEP(*(.secondary))
+        _secondary_end = .;
+    } > SYSTEM_RAM
+}
+
+__ddsc_xSPI0_CS0_SPACE_START = ORIGIN(xSPI0_CS0_SPACE);
+__ddsc_xSPI0_CS0_SPACE_END   = (1 == _RZN_ORDINAL) ? noncache_flash_contents_end : __ddsc_xSPI0_CS0_SPACE_START;
+__ddsc_ATCM_START            = ORIGIN(ATCM);
+__ddsc_ATCM_END              = (1 == _RZN_ORDINAL) && DEFINED(CR52_0) ? __ThreadStackLimit : __ddsc_ATCM_START;
+__ddsc_BTCM_START            = ORIGIN(BTCM);
+__ddsc_BTCM_END              = (1 == _RZN_ORDINAL) && DEFINED(CR52_0) ? __AbtStackLimit : __ddsc_BTCM_START;
+__ddsc_SYSTEM_RAM_START      = ORIGIN(SYSTEM_RAM);
+__ddsc_SYSTEM_RAM_END         = (1 == _RZN_ORDINAL) ?
+                                    DEFINED(CR52_0) ?
+                                        __ddsc_SYSTEM_RAM_START :
+                                        __ThreadStackLimit :
+                                    ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                        _ncbuffer_end :
+                                        __ThreadStackLimit;
+__ddsc_SECONDARY_START        = (1 == _RZN_ORDINAL) ? 0 : 1;
+__ddsc_SECONDARY_END          = 1;
diff --git a/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot_scons.ld b/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot_scons.ld
new file mode 100644
index 00000000..921b7a70
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/script/fsp_xspi0_boot_scons.ld
@@ -0,0 +1,696 @@
+/*
+                  Linker File for Renesas RZ/N2 FSP
+*/
+
+/* The memory information for each device is done in memory regions file.
+ * The starting address and length of memory not defined in memory regions file are defined as 0. */
+ 
+/* generated memory regions file - do not edit */
+ATCM_START  = 0x00000000;
+ATCM_LENGTH = 0x20000;
+BTCM_START  = 0x00100000;
+BTCM_LENGTH = 0x20000;
+SYSTEM_RAM_START  = 0x10000000;
+SYSTEM_RAM_LENGTH = 0x180000;
+SYSTEM_RAM_MIRROR_START  = 0x30000000;
+SYSTEM_RAM_MIRROR_LENGTH = 0x180000;
+xSPI0_CS0_SPACE_MIRROR_START  = 0x40000000;
+xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+xSPI0_CS1_SPACE_MIRROR_START  = 0x44000000;
+xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000;
+xSPI1_CS0_SPACE_MIRROR_START  = 0x48000000;
+xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+CS0_SPACE_MIRROR_START  = 0x50000000;
+CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+CS2_SPACE_MIRROR_START  = 0x54000000;
+CS2_SPACE_MIRROR_LENGTH = 0x4000000;
+CS3_SPACE_MIRROR_START  = 0x58000000;
+CS3_SPACE_MIRROR_LENGTH = 0x4000000;
+CS5_SPACE_MIRROR_START  = 0x5C000000;
+CS5_SPACE_MIRROR_LENGTH = 0x4000000;
+xSPI0_CS0_SPACE_START  = 0x60000000;
+xSPI0_CS0_SPACE_LENGTH = 0x4000000;
+xSPI0_CS1_SPACE_START  = 0x64000000;
+xSPI0_CS1_SPACE_LENGTH = 0x4000000;
+xSPI1_CS0_SPACE_START  = 0x68000000;
+xSPI1_CS0_SPACE_LENGTH = 0x4000000;
+CS0_SPACE_START  = 0x70000000;
+CS0_SPACE_LENGTH = 0x4000000;
+CS2_SPACE_START  = 0x74000000;
+CS2_SPACE_LENGTH = 0x4000000;
+CS3_SPACE_START  = 0x78000000;
+CS3_SPACE_LENGTH = 0x4000000;
+CS5_SPACE_START  = 0x7C000000;
+CS5_SPACE_LENGTH = 0x4000000;
+CR52_0 = 0;
+
+ATCM_PRV_START = DEFINED(ATCM_START) ? ATCM_START : 0;
+ATCM_PRV_LENGTH = DEFINED(ATCM_LENGTH) ? ATCM_LENGTH : 0;
+BTCM_PRV_START = DEFINED(BTCM_START) ? BTCM_START : 0;
+BTCM_PRV_LENGTH = DEFINED(BTCM_LENGTH) ? BTCM_LENGTH : 0;
+SYSTEM_RAM_PRV_START = DEFINED(SYSTEM_RAM_START) ? SYSTEM_RAM_START : 0;
+SYSTEM_RAM_PRV_LENGTH = DEFINED(SYSTEM_RAM_LENGTH) ? SYSTEM_RAM_LENGTH : 0;
+SYSTEM_RAM_MIRROR_PRV_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START : 0;
+SYSTEM_RAM_MIRROR_PRV_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? SYSTEM_RAM_MIRROR_LENGTH : 0;
+xSPI0_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS0_SPACE_MIRROR_START) ? xSPI0_CS0_SPACE_MIRROR_START : 0;
+xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_MIRROR_LENGTH) ? xSPI0_CS0_SPACE_MIRROR_LENGTH : 0;
+xSPI0_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS1_SPACE_MIRROR_START) ? xSPI0_CS1_SPACE_MIRROR_START : 0;
+xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_MIRROR_LENGTH) ? xSPI0_CS1_SPACE_MIRROR_LENGTH : 0;
+xSPI1_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS0_SPACE_MIRROR_START) ? xSPI1_CS0_SPACE_MIRROR_START : 0;
+xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_MIRROR_LENGTH) ? xSPI1_CS0_SPACE_MIRROR_LENGTH : 0;
+xSPI1_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS1_SPACE_MIRROR_START) ? xSPI1_CS1_SPACE_MIRROR_START : 0;
+xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_MIRROR_LENGTH) ? xSPI1_CS1_SPACE_MIRROR_LENGTH : 0;
+CS0_SPACE_MIRROR_PRV_START = DEFINED(CS0_SPACE_MIRROR_START) ? CS0_SPACE_MIRROR_START : 0;
+CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS0_SPACE_MIRROR_LENGTH) ? CS0_SPACE_MIRROR_LENGTH : 0;
+CS2_SPACE_MIRROR_PRV_START = DEFINED(CS2_SPACE_MIRROR_START) ? CS2_SPACE_MIRROR_START : 0;
+CS2_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS2_SPACE_MIRROR_LENGTH) ? CS2_SPACE_MIRROR_LENGTH : 0;
+CS3_SPACE_MIRROR_PRV_START = DEFINED(CS3_SPACE_MIRROR_START) ? CS3_SPACE_MIRROR_START : 0;
+CS3_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS3_SPACE_MIRROR_LENGTH) ? CS3_SPACE_MIRROR_LENGTH : 0;
+CS5_SPACE_MIRROR_PRV_START = DEFINED(CS5_SPACE_MIRROR_START) ? CS5_SPACE_MIRROR_START : 0;
+CS5_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS5_SPACE_MIRROR_LENGTH) ? CS5_SPACE_MIRROR_LENGTH : 0;
+xSPI0_CS0_SPACE_PRV_START = DEFINED(xSPI0_CS0_SPACE_START) ? xSPI0_CS0_SPACE_START : 0;
+xSPI0_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_LENGTH) ? xSPI0_CS0_SPACE_LENGTH : 0;
+xSPI0_CS1_SPACE_PRV_START = DEFINED(xSPI0_CS1_SPACE_START) ? xSPI0_CS1_SPACE_START : 0;
+xSPI0_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_LENGTH) ? xSPI0_CS1_SPACE_LENGTH : 0;
+xSPI1_CS0_SPACE_PRV_START = DEFINED(xSPI1_CS0_SPACE_START) ? xSPI1_CS0_SPACE_START : 0;
+xSPI1_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_LENGTH) ? xSPI1_CS0_SPACE_LENGTH : 0;
+xSPI1_CS1_SPACE_PRV_START = DEFINED(xSPI1_CS1_SPACE_START) ? xSPI1_CS1_SPACE_START : 0;
+xSPI1_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_LENGTH) ? xSPI1_CS1_SPACE_LENGTH : 0;
+CS0_SPACE_PRV_START = DEFINED(CS0_SPACE_START) ? CS0_SPACE_START : 0;
+CS0_SPACE_PRV_LENGTH = DEFINED(CS0_SPACE_LENGTH) ? CS0_SPACE_LENGTH : 0;
+CS2_SPACE_PRV_START = DEFINED(CS2_SPACE_START) ? CS2_SPACE_START : 0;
+CS2_SPACE_PRV_LENGTH = DEFINED(CS2_SPACE_LENGTH) ? CS2_SPACE_LENGTH : 0;
+CS3_SPACE_PRV_START = DEFINED(CS3_SPACE_START) ? CS3_SPACE_START : 0;
+CS3_SPACE_PRV_LENGTH = DEFINED(CS3_SPACE_LENGTH) ? CS3_SPACE_LENGTH : 0;
+CS5_SPACE_PRV_START = DEFINED(CS5_SPACE_START) ? CS5_SPACE_START : 0;
+CS5_SPACE_PRV_LENGTH = DEFINED(CS5_SPACE_LENGTH) ? CS5_SPACE_LENGTH : 0;
+PCIE0_MIRROR_PRV_START = DEFINED(PCIE0_MIRROR_START) ? PCIE0_MIRROR_START : 0;
+PCIE0_MIRROR_PRV_LENGTH = DEFINED(PCIE0_MIRROR_LENGTH) ? PCIE0_MIRROR_LENGTH : 0;
+PCIE1_MIRROR_PRV_START = DEFINED(PCIE1_MIRROR_START) ? PCIE1_MIRROR_START : 0;
+PCIE1_MIRROR_PRV_LENGTH = DEFINED(PCIE1_MIRROR_LENGTH) ? PCIE1_MIRROR_LENGTH : 0;
+DDR_MIRROR0_PRV_START = DEFINED(DDR_MIRROR0_START) ? DDR_MIRROR0_START : 0;
+DDR_MIRROR0_PRV_LENGTH = DEFINED(DDR_MIRROR0_LENGTH) ? DDR_MIRROR0_LENGTH : 0;
+DDR_MIRROR1_PRV_START = DEFINED(DDR_MIRROR1_START) ? DDR_MIRROR1_START : 0;
+DDR_MIRROR1_PRV_LENGTH = DEFINED(DDR_MIRROR1_LENGTH) ? DDR_MIRROR1_LENGTH : 0;
+DDR_MIRROR_PRV_START = DEFINED(DDR_MIRROR_START) ? DDR_MIRROR_START : 0;
+DDR_MIRROR_PRV_LENGTH = DEFINED(DDR_MIRROR_LENGTH) ? DDR_MIRROR_LENGTH : 0;
+DDR_PRV_START = DEFINED(DDR_START) ? DDR_START : 0;
+DDR_PRV_LENGTH = DEFINED(DDR_LENGTH) ? DDR_LENGTH : 0;
+PCIE0_PRV_START = DEFINED(PCIE0_START) ? PCIE0_START : 0;
+PCIE0_PRV_LENGTH = DEFINED(PCIE0_LENGTH) ? PCIE0_LENGTH : 0;
+PCIE1_PRV_START = DEFINED(PCIE1_START) ? PCIE1_START : 0;
+PCIE1_PRV_LENGTH = DEFINED(PCIE1_LENGTH) ? PCIE1_LENGTH : 0;
+SECONDARY_PRV = DEFINED(SECONDARY) ? SECONDARY : 0;
+
+_RZN_ORDINAL = (0 == SECONDARY_PRV) ? 1 : 2;
+HAS_SYSTEM_RAM_MIRROR = DEFINED(SYSTEM_RAM_MIRROR_START) ? 1 : 0;
+
+SYSTEM_RAM_ALIGN_START            = ALIGN(SYSTEM_RAM_PRV_START, 0x00020000);
+SYSTEM_RAM_ALIGN_LENGTH           = SYSTEM_RAM_PRV_LENGTH - (SYSTEM_RAM_PRV_LENGTH % 0x00020000);
+SYSTEM_RAM_MIRROR_OFFSET          = DEFINED(SYSTEM_RAM_START) ?
+                                        (0 == HAS_SYSTEM_RAM_MIRROR) ?
+                                            (DEFINED(CR52_0) || DEFINED(CR52_1)) ?
+                                                0x00000000 :
+                                                0x00200000 :
+                                            0x20000000 :
+                                        0;
+
+xSPI0_CS0_SPACE_ALIGN_START       = ALIGN(xSPI0_CS0_SPACE_PRV_START, 0x00020000);
+xSPI0_CS0_SPACE_ALIGN_LENGTH      = xSPI0_CS0_SPACE_PRV_LENGTH - (xSPI0_CS0_SPACE_PRV_LENGTH % 0x00020000);
+
+RAM_START                         = SYSTEM_RAM_ALIGN_START;
+RAM_LENGTH                        = SYSTEM_RAM_ALIGN_LENGTH;
+LOADER_START                      = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? BTCM_PRV_START : SYSTEM_RAM_ALIGN_START;
+LOADER_LENGTH                     = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? BTCM_PRV_LENGTH : SYSTEM_RAM_ALIGN_LENGTH;
+ROM_START                         = (1 == _RZN_ORDINAL) ? xSPI0_CS0_SPACE_ALIGN_START : SYSTEM_RAM_ALIGN_START;
+ROM_LENGTH                        = (1 == _RZN_ORDINAL) ? xSPI0_CS0_SPACE_ALIGN_LENGTH : SYSTEM_RAM_ALIGN_LENGTH;
+
+FLASH_CONTENTS_OFFSET             = (0 == HAS_SYSTEM_RAM_MIRROR) ? 0x00000050 : 0x0000004C;
+LOADER_TEXT_OFFSET                = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? 0x00002000 : 0x00001000;
+TEXT_OFFSET                       = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? 0x00000100 : 0x00010000;
+IMAGE_INFO_OFFSET                 = 0x00000800;
+
+INTVEC_ADDRESS                    = RAM_START;
+LOADER_TEXT_ADDRESS               = LOADER_START + LOADER_TEXT_OFFSET;
+TEXT_ADDRESS                      = ((1 == _RZN_ORDINAL) || ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1)))) ? RAM_START + TEXT_OFFSET : noncache_flash_contents_end;
+
+/* Define starting addresses and length for data_noncache, DMAC link mode data, CPU-shared non-cache, and CPU-specific non-cache areas. */
+DATA_NONCACHE_OFFSET              = DEFINED(SYSTEM_RAM_START) ? 0x00048000 : 0;
+DMAC_LINK_MODE_OFFSET             = DEFINED(SYSTEM_RAM_START) ? 0x00044000 : 0;
+SHARED_NONCACHE_BUFFER_OFFSET     = DEFINED(SYSTEM_RAM_START) ? 0x00040000 : 0;
+NONCACHE_BUFFER_OFFSET            = DEFINED(SYSTEM_RAM_START) ? 0x00020000 : 0;
+
+SYSTEM_RAM_END_ADDRESS            = SYSTEM_RAM_ALIGN_START + SYSTEM_RAM_ALIGN_LENGTH;
+SYSTEM_RAM_MIRROR_END_ADDRESS     = SYSTEM_RAM_ALIGN_START + SYSTEM_RAM_ALIGN_LENGTH + SYSTEM_RAM_MIRROR_OFFSET;
+
+DATA_NONCACHE_START               = (1 == _RZN_ORDINAL) ?
+                                        SYSTEM_RAM_MIRROR_END_ADDRESS - DATA_NONCACHE_OFFSET :
+                                        ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                            __ThreadStackLimit :
+                                            _mdata_noncache + SYSTEM_RAM_MIRROR_OFFSET;
+DMAC_LINK_MODE_START              = (1 == _RZN_ORDINAL) ?
+                                        SYSTEM_RAM_MIRROR_END_ADDRESS - DMAC_LINK_MODE_OFFSET :
+                                        ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                            _data_noncache_end :
+                                            _mdmac_link_mode + SYSTEM_RAM_MIRROR_OFFSET;
+NONCACHE_BUFFER_START             = (1 == _RZN_ORDINAL) ?
+                                        SYSTEM_RAM_MIRROR_END_ADDRESS - NONCACHE_BUFFER_OFFSET :
+                                        ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                            _dmac_link_mode_end :
+                                            _mncbuffer + SYSTEM_RAM_MIRROR_OFFSET;
+SHARED_NONCACHE_BUFFER_START      = SYSTEM_RAM_MIRROR_END_ADDRESS - SHARED_NONCACHE_BUFFER_OFFSET;
+
+data_noncache_size                = _data_noncache_end - _data_noncache_start;
+dmac_link_mode_size               = _dmac_link_mode_end - _dmac_link_mode_start;
+sncbuffer_size                    = _sncbuffer_end - _sncbuffer_start;
+ncbuffer_size                     = _ncbuffer_end - _ncbuffer_start;
+
+LCDC_FRAME_BUFFER_OFFSET          = (DEFINED(CR52_0) || DEFINED(CR52_1)) ?
+                                        DEFINED(DDR_MIRROR1_START) ?
+                                            0x04000000 :
+                                            0 :
+                                        DEFINED(DDR_MIRROR_START) ?
+                                            0x04000000 :
+                                            0;
+LCDC_FRAME_BUFFER_START           = (DEFINED(CR52_0) || DEFINED(CR52_1)) ?
+                                        DDR_MIRROR1_PRV_START + DDR_MIRROR1_PRV_LENGTH - LCDC_FRAME_BUFFER_OFFSET :
+                                        DDR_MIRROR_PRV_START + DDR_MIRROR_PRV_LENGTH - LCDC_FRAME_BUFFER_OFFSET;
+LCDC_FRAME_BUFFER_LENGTH          = LCDC_FRAME_BUFFER_OFFSET;
+
+MEMORY
+{
+    ATCM : ORIGIN = ATCM_PRV_START, LENGTH = ATCM_PRV_LENGTH
+    BTCM : ORIGIN = BTCM_PRV_START, LENGTH = BTCM_PRV_LENGTH
+    SYSTEM_RAM : ORIGIN = SYSTEM_RAM_ALIGN_START, LENGTH = SYSTEM_RAM_ALIGN_LENGTH
+    SYSTEM_RAM_MIRROR : ORIGIN = SYSTEM_RAM_MIRROR_PRV_START, LENGTH = SYSTEM_RAM_MIRROR_PRV_LENGTH
+    xSPI0_CS0_SPACE_MIRROR : ORIGIN = xSPI0_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH
+    xSPI0_CS1_SPACE_MIRROR : ORIGIN = xSPI0_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH
+    xSPI1_CS0_SPACE_MIRROR : ORIGIN = xSPI1_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH
+    xSPI1_CS1_SPACE_MIRROR : ORIGIN = xSPI1_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH
+    CS0_SPACE_MIRROR : ORIGIN = CS0_SPACE_MIRROR_PRV_START, LENGTH = CS0_SPACE_MIRROR_PRV_LENGTH
+    CS2_SPACE_MIRROR : ORIGIN = CS2_SPACE_MIRROR_PRV_START, LENGTH = CS2_SPACE_MIRROR_PRV_LENGTH
+    CS3_SPACE_MIRROR : ORIGIN = CS3_SPACE_MIRROR_PRV_START, LENGTH = CS3_SPACE_MIRROR_PRV_LENGTH
+    CS5_SPACE_MIRROR : ORIGIN = CS5_SPACE_MIRROR_PRV_START, LENGTH = CS5_SPACE_MIRROR_PRV_LENGTH
+    xSPI0_CS0_SPACE : ORIGIN = xSPI0_CS0_SPACE_ALIGN_START, LENGTH = xSPI0_CS0_SPACE_ALIGN_LENGTH
+    xSPI0_CS1_SPACE : ORIGIN = xSPI0_CS1_SPACE_PRV_START, LENGTH = xSPI0_CS1_SPACE_PRV_LENGTH
+    xSPI1_CS0_SPACE : ORIGIN = xSPI1_CS0_SPACE_PRV_START, LENGTH = xSPI1_CS0_SPACE_PRV_LENGTH
+    xSPI1_CS1_SPACE : ORIGIN = xSPI1_CS1_SPACE_PRV_START, LENGTH = xSPI1_CS1_SPACE_PRV_LENGTH
+    CS0_SPACE : ORIGIN = CS0_SPACE_PRV_START, LENGTH = CS0_SPACE_PRV_LENGTH
+    CS2_SPACE : ORIGIN = CS2_SPACE_PRV_START, LENGTH = CS2_SPACE_PRV_LENGTH
+    CS3_SPACE : ORIGIN = CS3_SPACE_PRV_START, LENGTH = CS3_SPACE_PRV_LENGTH
+    CS5_SPACE : ORIGIN = CS5_SPACE_PRV_START, LENGTH = CS5_SPACE_PRV_LENGTH
+    PCIE0_MIRROR : ORIGIN = PCIE0_MIRROR_PRV_START, LENGTH = PCIE0_MIRROR_PRV_LENGTH
+    PCIE1_MIRROR : ORIGIN = PCIE1_MIRROR_PRV_START, LENGTH = PCIE1_MIRROR_PRV_LENGTH
+    DDR_MIRROR0 : ORIGIN = DDR_MIRROR0_PRV_START, LENGTH = DDR_MIRROR0_PRV_LENGTH
+    DDR_MIRROR1 : ORIGIN = DDR_MIRROR1_PRV_START, LENGTH = DDR_MIRROR1_PRV_LENGTH
+    DDR_MIRROR : ORIGIN = DDR_MIRROR_PRV_START, LENGTH = DDR_MIRROR_PRV_LENGTH
+    DDR : ORIGIN = DDR_PRV_START, LENGTH = DDR_PRV_LENGTH
+    PCIE0 : ORIGIN = PCIE0_PRV_START, LENGTH = PCIE0_PRV_LENGTH
+    PCIE1 : ORIGIN = PCIE1_PRV_START, LENGTH = PCIE1_PRV_LENGTH
+    RAM_TEXT : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+    RAM_DATA : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+    LOADER_TEXT_STACK : ORIGIN = LOADER_START, LENGTH = LOADER_LENGTH
+    LOADER_DATA_STACK : ORIGIN = LOADER_START, LENGTH = LOADER_LENGTH
+    FLASH_CONTENTS : ORIGIN = ROM_START, LENGTH = ROM_LENGTH
+    NONCACHE : ORIGIN = SYSTEM_RAM_ALIGN_START + SYSTEM_RAM_MIRROR_OFFSET, LENGTH = SYSTEM_RAM_ALIGN_LENGTH
+    LCDC_FRAME_BUFFER : ORIGIN = LCDC_FRAME_BUFFER_START, LENGTH = LCDC_FRAME_BUFFER_LENGTH
+}
+
+SECTIONS
+{
+    LOADER_PARAM_ADDRESS = (1 == _RZN_ORDINAL) ? xSPI0_CS0_SPACE_ALIGN_START : _loader_text_start;
+    .loader_param LOADER_PARAM_ADDRESS : AT (LOADER_PARAM_ADDRESS)
+    {
+        KEEP(*(.loader_param))
+    } > FLASH_CONTENTS
+
+    FLASH_CONTENTS_ADDRESS = (1 == _RZN_ORDINAL) ? LOADER_PARAM_ADDRESS + FLASH_CONTENTS_OFFSET : _loader_text_start;
+    .flash_contents FLASH_CONTENTS_ADDRESS : AT (FLASH_CONTENTS_ADDRESS)
+    {
+        _mloader_text = .;
+        . = (1 == _RZN_ORDINAL) ? . + (_loader_text_end - _loader_text_start) : .;
+        . = ALIGN(8);
+        _mloader_data = .;
+        . = (1 == _RZN_ORDINAL) ? . + (_loader_data_end - _loader_data_start) : .;
+        . = ALIGN(8);
+        _mfvector = .;
+        . = (1 == _RZN_ORDINAL) ? . + (_fvector_end - _fvector_start) : .;
+        . = ALIGN(8);
+        _mtext = .;
+        . = (1 == _RZN_ORDINAL) ? . + (__text_end - __text_start) +
+                                      (_rvectors_end - _rvectors_start) +
+                                      (__extab_end - __extab_start) +
+                                      (__exidx_end - __exidx_start) : .;
+        . = ALIGN(8);
+        _mdata = .;
+        . = (1 == _RZN_ORDINAL) ? . + (__data_end - __data_start) +
+                                      (__got_end - __got_start) : .;
+        flash_contents_end = .;
+    } > FLASH_CONTENTS
+
+    NONCACHE_FLASH_CONTENTS_ADDRESS = (1 == _RZN_ORDINAL) ? flash_contents_end : RAM_START + TEXT_OFFSET;
+    .noncache_flash_contents NONCACHE_FLASH_CONTENTS_ADDRESS : AT (NONCACHE_FLASH_CONTENTS_ADDRESS)
+    {
+        . = (0 != data_noncache_size) ? ALIGN(8) : .;
+        _mdata_noncache = .;
+        . = . + data_noncache_size;
+        . = (0 != dmac_link_mode_size) ? ALIGN(8) : .;
+        _mdmac_link_mode = .;
+        . = . + dmac_link_mode_size;
+        . = (0 != sncbuffer_size) ? ALIGN(32) : .;
+        _msncbuffer = .;
+        . = . + sncbuffer_size;
+        . = (0 != ncbuffer_size) ? ALIGN(32) : .;
+        _mncbuffer = .;
+        . = . + ncbuffer_size;
+        noncache_flash_contents_end = .;
+    } > FLASH_CONTENTS
+
+    LOADER_TEXT_IMAGE                 = (1 == _RZN_ORDINAL) ? _mloader_text : _loader_text_start;
+    .loader_text LOADER_TEXT_ADDRESS : AT (LOADER_TEXT_IMAGE)
+    {
+        _loader_text_start = .;
+        *(.loader_text)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.o(.text*)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.o(.text*)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o(.text*)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o(.text*)
+        build/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.o(.text*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_clocks.o(.text*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_irq.o(.text*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.o(.text*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.o(.text*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_cache.o(.text*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.o(.text*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.o(.text*)
+        build/rzn/fsp/src/r_ioport/r_ioport.o(.text*)
+        KEEP(*(.warm_start))
+        KEEP(*(.loader_user_data*))
+        . = ALIGN(0x200);
+        _loader_text_end = .;
+    } > LOADER_TEXT_STACK
+
+    LOADER_DATA_IMAGE = (1 == _RZN_ORDINAL) ? _mloader_data : _loader_data_start;
+    .loader_data _loader_text_end : AT (LOADER_DATA_IMAGE)
+    {
+        _loader_data_start = .;
+        __loader_data_start = .;
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.o(.data*)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.o(.rodata*)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/*/startup.o(.rodata*)
+        build/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.o(.data*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_clocks.o(.data*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_irq.o(.data*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.o(.data*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.o(.data*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.o(.rodata*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_cache.o(.data*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.o(.data*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.o(.rodata*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.o(.data*)
+        build/rzn/fsp/src/r_ioport/r_ioport.o(.data*)
+        . = ALIGN(8);
+        __loader_data_end = .;
+        __loader_bss_start = .;
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.o(.bss*)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.o(.bss*)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o(.bss*)
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o(.bss*)
+        build/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.o(.bss*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_clocks.o(.bss*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_irq.o(.bss*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.o(.bss*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.o(.bss*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_cache.o(.bss*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.o(.bss*)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.o(.bss*)
+        build/rzn/fsp/src/r_ioport/r_ioport.o(.bss*)
+        KEEP(*(.ttbr))
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(COMMON)
+        build/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.o(COMMON)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_clocks.o(COMMON)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_irq.o(COMMON)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_semaphore.o(COMMON)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.o(.COMMON)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_cache.o(COMMON)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_tzc400.o(COMMON)
+        build/rzn/fsp/src/bsp/mcu/all/bsp_address_expander.o(COMMON)
+        build/rzn/fsp/src/r_ioport/r_ioport.o(.COMMON)
+        . = ALIGN(8);
+        __loader_bss_end = . ;
+        build/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.software_reset) /* Do not initialize */
+        _loader_data_end = .;
+    } > LOADER_DATA_STACK
+
+    INTVEC_IMAGE = (1 == _RZN_ORDINAL) ? _mfvector : _fvector_start;
+    .intvec INTVEC_ADDRESS : AT (INTVEC_IMAGE)
+    {
+        _fvector_start = .;
+        KEEP(*(.intvec))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x080))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x100))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x180))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x200))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x280))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x300))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x380))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x400))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x480))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x500))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x580))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x600))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x680))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x700))
+        . = ALIGN(0x80);
+        KEEP(*(.intvec_0x780))
+        _fvector_end = .;
+    } > RAM_TEXT
+
+    IMAGE_INFO_ADDRESS = RAM_START + IMAGE_INFO_OFFSET;
+    .image_info IMAGE_INFO_ADDRESS : AT (IMAGE_INFO_ADDRESS)
+    {
+        _image_info_start = .;
+        KEEP(*(.image_info))
+        _image_info_end = .;
+    } > RAM_DATA
+
+    TEXT_IMAGE = (1 == _RZN_ORDINAL) ? _mtext : _text_start;
+    .text TEXT_ADDRESS : AT (TEXT_IMAGE)
+    {
+        _text_start = .;
+        __text_start = .;
+
+        *(.text*)
+
+        KEEP(*(.reset_handler))
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+        _ctor_end = .;
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+        _dtor_end = .;
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        /* new GCC version uses .init_array */
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        KEEP(*(FalPartTable))
+
+        KEEP(*(.eh_frame*))
+
+        __text_end = .;
+    } > RAM_TEXT
+    .rvectors :
+    {
+        _rvectors_start = .;
+        KEEP(*(.rvectors))
+        _rvectors_end = .;
+    } > RAM_TEXT
+    .ARM.extab :
+    {
+        __extab_start = .;
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        __extab_end = .;
+    } > RAM_TEXT
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+        _text_end = .;
+    } > RAM_TEXT
+
+    DATA_IMAGE = (1 == _RZN_ORDINAL) ? _mdata : _data_start;
+    .data _text_end :  AT (DATA_IMAGE)
+    {
+        _data_start = .;
+        __data_start = .;
+
+        *(vtable)
+        *(.data.*)
+        *(.data)
+
+        *(.rodata*)
+        _erodata = .;
+
+        . = ALIGN(8);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(8);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(8);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(8);
+
+        __data_end = .;
+    } > RAM_DATA
+    .got :
+    {
+        __got_start = .;
+        *(.got)
+        *(.got.plt)
+        __got_end = .;
+
+        /* All data end */
+        _data_end = .;
+    } > RAM_DATA
+    .bss :
+    {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(8);
+        __bss_end__ = .;
+        _ebss = .;
+        _end = .;
+    } > RAM_DATA
+    .heap (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM_DATA
+    .aarch64_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __AArch64StackBase = .;
+        /* Place the Thread stacks here. */
+        KEEP(*(.aarch64_stack*))
+        __AArch64StackLimit = .;
+    } > RAM_DATA
+    .thread_stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        __ThreadStackBase = .;
+        /* Place the Thread stacks here. */
+        KEEP(*(.stack*))
+        __ThreadStackLimit = .;
+    } > RAM_DATA
+    .sys_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __SysStackBase = .;
+        /* Place the sys_stack here. */
+        KEEP(*(.sys_stack))
+        __SysStackLimit = .;
+    } > LOADER_DATA_STACK
+    .svc_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __SvcStackBase = .;
+        /* Place the svc_stack here. */
+        KEEP(*(.svc_stack))
+        __SvcStackLimit = .;
+    } > LOADER_DATA_STACK
+    .irq_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __IrqStackBase = .;
+        /* Place the irq_stack here. */
+        KEEP(*(.irq_stack))
+        __IrqStackLimit = .;
+    } > LOADER_DATA_STACK
+    .fiq_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __FiqStackBase = .;
+        /* Place the fiq_stack here. */
+        KEEP(*(.fiq_stack))
+        __FiqStackLimit = .;
+    } > LOADER_DATA_STACK
+    .und_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __UndStackBase = .;
+        /* Place the und_stack here. */
+        KEEP(*(.und_stack))
+        __UndStackLimit = .;
+    } > LOADER_DATA_STACK
+    .abt_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        __AbtStackBase = .;
+        /* Place the abt_stack here. */
+        KEEP(*(.abt_stack))
+        __AbtStackLimit = .;
+    } > LOADER_DATA_STACK
+
+    DATA_NONCACHE_INIT_START = (1 == _RZN_ORDINAL) ?
+                                   _mdata_noncache :
+                                   ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                       __ThreadStackLimit :
+                                       _mdata_noncache;
+    .data_noncache DATA_NONCACHE_START : AT (DATA_NONCACHE_INIT_START)
+    {
+        . = ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ? ALIGN(64) : ALIGN(8);
+        _data_noncache_start = .;
+        KEEP(*(.data_noncache*))
+        _data_noncache_end = .;
+    } > NONCACHE
+
+    DMAC_LINK_MODE_INIT_START = (1 == _RZN_ORDINAL) ?
+                                    _mdmac_link_mode :
+                                    ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                        _data_noncache_end :
+                                        _mdmac_link_mode;
+    .dmac_link_mode DMAC_LINK_MODE_START : AT (DMAC_LINK_MODE_INIT_START)
+    {
+        . = ALIGN(8);
+        _dmac_link_mode_start = .;
+        KEEP(*(.dmac_link_mode*))
+        _dmac_link_mode_end = .;
+    } > NONCACHE
+
+    SHARED_NONCACHE_BUFFER_INIT_START = (1 == _RZN_ORDINAL) ?
+                                            _msncbuffer :
+                                            ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                                _ncbuffer_end :
+                                                _msncbuffer;
+    .shared_noncache_buffer SHARED_NONCACHE_BUFFER_START : AT (SHARED_NONCACHE_BUFFER_INIT_START)
+    {
+        . = ALIGN(32);
+        _sncbuffer_start = .;
+        KEEP(*(.shared_noncache_buffer*))
+        _sncbuffer_end = .;
+    } > NONCACHE
+
+    NONCACHE_BUFFER_INIT_START = (1 == _RZN_ORDINAL) ?
+                                     _mncbuffer :
+                                     ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                         _dmac_link_mode_end :
+                                         _mncbuffer;
+    .noncache_buffer NONCACHE_BUFFER_START : AT (NONCACHE_BUFFER_INIT_START)
+    {
+        . = ALIGN(32);
+        _ncbuffer_start = .;
+        KEEP(*(.noncache_buffer*))
+        _ncbuffer_end = .;
+    } > NONCACHE
+
+    .lcdc_frame_buffer (NOLOAD) :
+    {
+        . = ALIGN(512);
+        _lcdc_frame_buffer_start = .;
+        KEEP(*(.lcdc_frame_buffer*))
+        _lcdc_frame_buffer_end = .;
+    } > LCDC_FRAME_BUFFER
+
+    SECONDARY_START = ((1 == _RZN_ORDINAL) && DEFINED(CR52_0)) ? SYSTEM_RAM_ALIGN_START : ALIGN(__ThreadStackLimit, 0x00020000);
+    SECONDARY_IMAGE = (1 == _RZN_ORDINAL) ? ALIGN(noncache_flash_contents_end, 0x00020000) : SECONDARY_START;
+    .secondary SECONDARY_START : AT (SECONDARY_IMAGE)
+    {
+        . = ALIGN(0x20000);
+        _secondary_start = .;
+        KEEP(*(.secondary))
+        _secondary_end = .;
+    } > SYSTEM_RAM
+}
+
+__ddsc_xSPI0_CS0_SPACE_START = ORIGIN(xSPI0_CS0_SPACE);
+__ddsc_xSPI0_CS0_SPACE_END   = (1 == _RZN_ORDINAL) ? noncache_flash_contents_end : __ddsc_xSPI0_CS0_SPACE_START;
+__ddsc_ATCM_START            = ORIGIN(ATCM);
+__ddsc_ATCM_END              = (1 == _RZN_ORDINAL) && DEFINED(CR52_0) ? __ThreadStackLimit : __ddsc_ATCM_START;
+__ddsc_BTCM_START            = ORIGIN(BTCM);
+__ddsc_BTCM_END              = (1 == _RZN_ORDINAL) && DEFINED(CR52_0) ? __AbtStackLimit : __ddsc_BTCM_START;
+__ddsc_SYSTEM_RAM_START      = ORIGIN(SYSTEM_RAM);
+__ddsc_SYSTEM_RAM_END         = (1 == _RZN_ORDINAL) ?
+                                    DEFINED(CR52_0) ?
+                                        __ddsc_SYSTEM_RAM_START :
+                                        __ThreadStackLimit :
+                                    ((0 == HAS_SYSTEM_RAM_MIRROR) && (DEFINED(CR52_0) || DEFINED(CR52_1))) ?
+                                        _ncbuffer_end :
+                                        __ThreadStackLimit;
+__ddsc_SECONDARY_START        = (1 == _RZN_ORDINAL) ? 0 : 1;
+__ddsc_SECONDARY_END          = 1;
diff --git a/projects/etherkit_ethercat_cherryecat/src/hal_entry.c b/projects/etherkit_ethercat_cherryecat/src/hal_entry.c
new file mode 100644
index 00000000..51a206ef
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/src/hal_entry.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2024-03-11     Wangyuqiang   first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+#include "hal_data.h"
+#include "ec_master.h"
+
+#define LED_PIN_0    BSP_IO_PORT_14_PIN_3 /* Onboard LED pins */
+#define LED_PIN_1    BSP_IO_PORT_14_PIN_0 /* Onboard LED pins */
+#define LED_PIN_2    BSP_IO_PORT_14_PIN_1 /* Onboard LED pins */
+
+#define MOTOR_MODE_CSV_CSP  0
+#define MOTOR_MODE_CSP      1
+#define MOTOR_MODE_CSV      2
+
+volatile uint8_t motor_mode = MOTOR_MODE_CSP;
+
+ec_master_t g_ec_master;
+uint8_t cherryecat_eepromdata[2048];
+
+static ec_pdo_entry_info_t coe402_1601[] =
+{
+    { 0x6040, 0x00, 0x10 }, // Control Word
+    { 0x6072, 0x00, 0x10 }, // Max Torque
+    { 0x607A, 0x00, 0x20 }, // Target Position
+    { 0x60B0, 0x00, 0x20 }, // Position Offset
+    { 0x60B1, 0x00, 0x20 }, // Velocity Offset
+    { 0x60B2, 0x00, 0x10 }, // Torque Offset
+    { 0x60B8, 0x00, 0x10 }, // Touch Probe Function
+    { 0x60E0, 0x00, 0x10 }, // Positive Torque Limit Value
+    { 0x60E0, 0x00, 0x10 }, // Negative Torque Limit Value
+    { 0x60FE, 0x01, 0x20 }, // Digital Outputs
+};
+
+static ec_pdo_entry_info_t coe402_1a01[] =
+{
+    { 0x603F, 0x00, 0x10 }, // Error Code
+    { 0x6041, 0x00, 0x10 }, // Status Word
+    { 0x6064, 0x00, 0x20 }, // Actual Position
+    { 0x606C, 0x00, 0x20 }, // Actual Velocity
+    { 0x6077, 0x00, 0x10 }, // Actual Torque
+    { 0x60B9, 0x00, 0x10 }, // Touch Probe Status
+    { 0x60BA, 0x00, 0x20 }, // Touch Probe Position 1 Positive Value
+    { 0x60BC, 0x00, 0x20 }, // Touch Probe Position 2 Positive Value
+    { 0x60F4, 0x00, 0x20 }, // Following Error Actual Value
+    { 0x60FD, 0x00, 0x20 }, // Digital Inputs
+};
+
+static ec_pdo_info_t cia402_rxpdos[] =
+{
+    { 0x1601, 10, &coe402_1601[0] },
+};
+
+static ec_pdo_info_t cia402_txpdos[] =
+{
+    { 0x1a01, 10, &coe402_1a01[0] },
+};
+
+static ec_sync_info_t cia402_syncs[] =
+{
+    { 2, EC_DIR_OUTPUT, 1, cia402_rxpdos },
+    { 3, EC_DIR_INPUT, 1, cia402_txpdos },
+};
+
+int ec_start(int argc, const char **argv)
+{
+    static ec_slave_config_t slave_cia402_config;
+
+    if (g_ec_master.slave_count == 0)
+    {
+        printf("No slave found, please check the connection\r\n");
+        return -1;
+    }
+
+    slave_cia402_config.dc_assign_activate = 0x300;
+
+    slave_cia402_config.dc_sync[0].cycle_time = atoi(argv[1]) * 1000;
+    slave_cia402_config.dc_sync[0].shift_time = 500000;
+    slave_cia402_config.dc_sync[1].cycle_time = 0;
+    slave_cia402_config.dc_sync[1].shift_time = 0;
+
+    slave_cia402_config.sync = cia402_syncs;
+    slave_cia402_config.sync_count = sizeof(cia402_syncs) / sizeof(ec_sync_info_t);
+
+    for (uint32_t i = 0; i < g_ec_master.slave_count; i++)
+    {
+        if (g_ec_master.slaves[i].sii.vendor_id != 0x00000766)
+        {
+            EC_LOG_ERR("Unsupported slave found: vendor_id=0x%08x\n", g_ec_master.slaves[i].sii.vendor_id);
+            return -1;
+        }
+
+        g_ec_master.slaves[i].config = &slave_cia402_config;
+    }
+
+    ec_master_start(&g_ec_master, atoi(argv[1]));
+
+    return 0;
+}
+MSH_CMD_EXPORT(ec_start, ethercat start);
+
+int ec_stop(int argc, const char **argv)
+{
+    ec_master_stop(&g_ec_master);
+    return 0;
+}
+MSH_CMD_EXPORT(ec_stop, ethercat stop);
+
+void hal_entry(void)
+{
+    rt_kprintf("\nHello RT-Thread!\n");
+    rt_kprintf("==================================================\n");
+    rt_kprintf("This example project is an ethernet routine!\n");
+    rt_kprintf("==================================================\n");
+
+    ec_master_cmd_init(&g_ec_master);
+    ec_master_init(&g_ec_master, 0);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN_0, PIN_HIGH);
+        rt_pin_write(LED_PIN_1, PIN_HIGH);
+        rt_pin_write(LED_PIN_2, PIN_HIGH);
+        rt_thread_mdelay(1000);
+        rt_pin_write(LED_PIN_0, PIN_LOW);
+        rt_pin_write(LED_PIN_1, PIN_LOW);
+        rt_pin_write(LED_PIN_2, PIN_LOW);
+        rt_thread_mdelay(1000);
+    }
+}
diff --git a/projects/etherkit_ethercat_cherryecat/template.ewd b/projects/etherkit_ethercat_cherryecat/template.ewd
new file mode 100644
index 00000000..ae0c91ce
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/template.ewd
@@ -0,0 +1,3276 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>4</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>33</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state>$TOOLKIT_DIR$\config\debugger\Renesas\R9A07G084M04.ddf</state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state>--drv_reset_to_cpu_start</state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>8.50.4.26131</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>JLINK_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state>9.50.2.71646</state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state>$TOOLKIT_DIR$/config/flashloader/Renesas/FlashRSK_RZN2L.board</state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlavePath</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>C_32_64Device</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AuthSdmSelection</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthSdmManifest</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthSdmExplicitLib</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthEnforce</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>E2_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>E2PowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CE2UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CE2IdCodeEditB</name>
+                    <state>0xFFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF</state>
+                </option>
+                <option>
+                    <name>CE2LogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CE2LogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GPLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state>$TOOLKIT_DIR$/config/debugger/Renesas/RZN2L.ProbeConfig</state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVccEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSelectedCoreName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>33</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state>--drv_reset_to_cpu_start</state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>8.50.4.26131</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>IJET_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOverrideSlavePath</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>C_32_64Device</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AuthSdmSelection</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AuthSdmManifest</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthSdmExplicitLib</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AuthEnforce</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>E2_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>E2PowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CE2UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CE2IdCodeEditB</name>
+                    <state>0xFFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF'FFFF</state>
+                </option>
+                <option>
+                    <name>CE2LogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CE2LogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GPLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVccEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSelectedCoreName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>
diff --git a/projects/etherkit_ethercat_cherryecat/template.ewp b/projects/etherkit_ethercat_cherryecat/template.ewp
new file mode 100644
index 00000000..5139b3e2
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/template.ewp
@@ -0,0 +1,2281 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>4</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>36</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>BrowseInfoPath</name>
+                    <state>Debug\BrowseInfo</state>
+                </option>
+                <option>
+                    <name>OGAarch64Abi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OG_32_64Device</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>BuildFilesPath</name>
+                    <state>Debug\</state>
+                </option>
+                <option>
+                    <name>ExePath</name>
+                    <state>Debug\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>Debug\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>Debug\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state>A complete configuration of the C/C++14 runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>9.20.4.47112</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>9.50.2.71646</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>R9A07G084M04	Renesas R9A07G084M04</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>33</version>
+                    <state>49</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>33</version>
+                    <state>49</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>R9A07G084M04	Renesas R9A07G084M04</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>33</version>
+                    <state>49</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PointerAuthentication</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FPU64</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OG_32_64DeviceCoreSlave</name>
+                    <version>33</version>
+                    <state>49</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>38</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCDefines</name>
+                    <state>_LWIP_ADD_ON_APP=0</state>
+                    <state>ETHERCAT_SSC_PORT_GMAC_MDIO_SUPPORT=1</state>
+                    <state>_RZN_ORDINAL=1</state>
+                    <state>_RZN_CORE=CR52_0</state>
+                    <state>_RENESAS_RZN_</state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>10010100</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</state>
+                    <state>$PROJ_DIR$/rzn/aws/amazon-freertos/freertos_kernel/include</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/api</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/instances</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_ethercat_ssc_port</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_freertos_port/cr</state>
+                    <state>$PROJ_DIR$/rzn_cfg/aws</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</state>
+                    <state>$PROJ_DIR$/rzn_gen</state>
+                    <state>$PROJ_DIR$/src</state>
+                    <state>$PROJ_DIR$</state>
+                    <state>$PROJ_DIR$\src\ethercat\beckhoff\Src</state>
+                    <state>$PROJ_DIR$\src\ethercat\renesas</state>
+                    <state>$PROJ_DIR$\src\tcpip\renesas\module</state>
+                    <state>$PROJ_DIR$\src\tcpip\renesas\module\ether_netif</state>
+                    <state>$PROJ_DIR$\src\tcpip\renesas\module\lwip_port</state>
+                    <state>$PROJ_DIR$\src\tcpip\renesas\module\serial_io</state>
+                    <state>$PROJ_DIR$\src\tcpip\renesas\oss_deps\lwip</state>
+                    <state>$PROJ_DIR$\src\tcpip\oss\amazon-freertos\libraries\3rdparty\lwip_osal\include</state>
+                    <state>$PROJ_DIR$\src\tcpip\oss\lwip\src\include</state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPointerAutentiction</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCBranchTargetIdentification</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>12</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
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+                    <name>MacroChars</name>
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+                </option>
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+                    <name>AWarnWhat</name>
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+                <option>
+                    <name>AWarnOne</name>
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+                    <name>AWarnRange1</name>
+                    <state></state>
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+                    <name>AWarnRange2</name>
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+                <option>
+                    <name>AltRegisterNames</name>
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+                </option>
+                <option>
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+                    <state>_RZN_CORE=CR52_0</state>
+                    <state>_RENESAS_RZN_</state>
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+                <option>
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+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
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+                <option>
+                    <name>AOutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
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+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</state>
+                    <state>$PROJ_DIR$/rzn/aws/amazon-freertos/freertos_kernel/include</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/api</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/instances</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_ethercat_ssc_port</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_freertos_port/cr</state>
+                    <state>$PROJ_DIR$/rzn_cfg/aws</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</state>
+                    <state>$PROJ_DIR$/rzn_gen</state>
+                    <state>$PROJ_DIR$/src</state>
+                    <state>$PROJ_DIR$</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>A_32_64Device</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
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+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state>template.srec</state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>1</hasPrio>
+                <buildSequence>inputOutputBased</buildSequence>
+            </data>
+        </settings>
+        <settings>
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+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>27</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IlinkLogCrtRoutineSelection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFragmentInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInlining</name>
+                    <state>0</state>
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+                    <name>IlinkLogMerging</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDemangle</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFileEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>template.out</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$/script/fsp_xspi0_boot.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state>--config_search "$PROJ_DIR$"</state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>system_init</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
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+                    <name>FillerStart</name>
+                    <state>0x0</state>
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+                    <name>FillerEnd</name>
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+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
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+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
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+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
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+                    <name>CrcCompl</name>
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+                    <state>0</state>
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+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>template_import_lib.o</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
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+                    <name>IlinkProcessor</name>
+                    <state>1</state>
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+                <option>
+                    <name>IlinkFpuProcessor</name>
+                    <state>1</state>
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+        </settings>
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+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>2</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>36</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>BrowseInfoPath</name>
+                    <state>Release\BrowseInfo</state>
+                </option>
+                <option>
+                    <name>OGAarch64Abi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OG_32_64Device</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>BuildFilesPath</name>
+                    <state>Release\</state>
+                </option>
+                <option>
+                    <name>ExePath</name>
+                    <state>Release\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>Release\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>Release\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
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+                <option>
+                    <name>Input description</name>
+                    <state></state>
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+                    <state></state>
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+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
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+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
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+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
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+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
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+                <option>
+                    <name>RTDescription</name>
+                    <state></state>
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+                <option>
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+                    <state>9.20.4.47112</state>
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+                    <name>OGLastSavedByProductVersion</name>
+                    <state>9.50.1.69462</state>
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+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>R9A07G084M04	Renesas R9A07G084M04</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>0</state>
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+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>33</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>33</version>
+                    <state>38</state>
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+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>-</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>33</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
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+                <option>
+                    <name>OGLibAdditionalLocale</name>
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+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
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+                    <name>OGPrintfMultibyteSupport</name>
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+                    <version>0</version>
+                    <state>0</state>
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+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PointerAuthentication</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FPU64</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OG_32_64DeviceCoreSlave</name>
+                    <version>33</version>
+                    <state>38</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>38</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCDefines</name>
+                    <state>NDEBUG</state>
+                    <state>_RZN_ORDINAL=1</state>
+                    <state>_RZN_CORE=CR52_0</state>
+                    <state>_RENESAS_RZN_</state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>11111110</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</state>
+                    <state>$PROJ_DIR$/rzn/aws/amazon-freertos/freertos_kernel/include</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/api</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/instances</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_ethercat_ssc_port</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_freertos_port/cr</state>
+                    <state>$PROJ_DIR$/rzn_cfg/aws</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</state>
+                    <state>$PROJ_DIR$/rzn_gen</state>
+                    <state>$PROJ_DIR$/src</state>
+                    <state>$PROJ_DIR$</state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPointerAutentiction</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCBranchTargetIdentification</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>12</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state>_RZN_ORDINAL=1</state>
+                    <state>_RZN_CORE=CR52_0</state>
+                    <state>_RENESAS_RZN_</state>
+                </option>
+                <option>
+                    <name>AList</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Includes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefInternal</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</state>
+                    <state>$PROJ_DIR$/rzn/aws/amazon-freertos/freertos_kernel/include</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/api</state>
+                    <state>$PROJ_DIR$/rzn/fsp/inc/instances</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_ethercat_ssc_port</state>
+                    <state>$PROJ_DIR$/rzn/fsp/src/rm_freertos_port/cr</state>
+                    <state>$PROJ_DIR$/rzn_cfg/aws</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg</state>
+                    <state>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</state>
+                    <state>$PROJ_DIR$/rzn_gen</state>
+                    <state>$PROJ_DIR$/src</state>
+                    <state>$PROJ_DIR$</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>A_32_64Device</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+                <buildSequence>inputOutputBased</buildSequence>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>27</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IlinkLogCrtRoutineSelection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFragmentInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInlining</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogMerging</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDemangle</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFileEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$/script/fsp_xspi0_boot.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state>--config_search "$PROJ_DIR$"</state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>system_init</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkFpuProcessor</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <buildActions>
+                    <buildAction>
+                        <cmdline>cmd /c ""$PROJ_DIR$\rasc_launcher.bat" "$PROJ_DIR$\rasc_version.txt" -nosplash --launcher.suppressErrors --generate --compiler IAR --devicefamily $RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" 2&gt; "$BUILD_FILES_DIR$\.rasc_stderr.txt" &amp;&amp; echo. &gt; "$BUILD_FILES_DIR$\$TARGET_BNAME$.rasc""</cmdline>
+                        <workingDirectory>$PROJ_DIR$</workingDirectory>
+                        <buildSequence>preCompile</buildSequence>
+                        <outputs>
+                            <file>
+                                <name>$BUILD_FILES_DIR$/$TARGET_BNAME$.rasc</name>
+                            </file>
+                        </outputs>
+                        <dependencies>
+                            <file>
+                                <name>configuration.xml</name>
+                            </file>
+                        </dependencies>
+                    </buildAction>
+                    <buildAction>
+                        <cmdline>cmd /c ""$PROJ_DIR$\rasc_launcher.bat" "$PROJ_DIR$\rasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily $RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2&gt; "$BUILD_FILES_DIR$\.rasc_stderr.txt""</cmdline>
+                        <workingDirectory>$PROJ_DIR$</workingDirectory>
+                        <buildSequence>postLink</buildSequence>
+                        <outputs>
+                            <file>
+                                <name>$TARGET_BPATH$.sbd</name>
+                            </file>
+                        </outputs>
+                        <dependencies>
+                            <file>
+                                <name>$TARGET_PATH$</name>
+                            </file>
+                        </dependencies>
+                    </buildAction>
+                </buildActions>
+            </data>
+        </settings>
+    </configuration>
+    <file>
+        <name>$PROJ_DIR$\buildinfo.ipcf</name>
+        <tag>IAR.ControlFile</tag>
+    </file>
+</project>
diff --git a/projects/etherkit_ethercat_cherryecat/template.eww b/projects/etherkit_ethercat_cherryecat/template.eww
new file mode 100644
index 00000000..53e2ec6f
--- /dev/null
+++ b/projects/etherkit_ethercat_cherryecat/template.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<workspace>
+    <project>
+        <path>$WS_DIR$\template.ewp</path>
+    </project>
+    <batchBuild/>
+</workspace>
diff --git a/sdk-bsp-rzn2l-etherkit.yaml b/sdk-bsp-rzn2l-etherkit.yaml
index 71c7a30a..2ab15a17 100644
--- a/sdk-bsp-rzn2l-etherkit.yaml
+++ b/sdk-bsp-rzn2l-etherkit.yaml
@@ -479,6 +479,27 @@ example_projects:
     source_path_offset: '.'
     target_path_offset: '.'
     files_and_folders: []
+- project_name: etherkit_ethercat_cherryecat
+  project_description: CherryECAT 示例
+  project_type: rt-thread|@full|@5.1.0
+  builtin_files:
+  - source_path_offset: projects/etherkit_ethercat_cherryecat
+    target_path_offset: ''
+    files_and_folders:
+    - "*"
+  - source_path_offset: ''
+    target_path_offset: ''
+    files_and_folders:
+    - libraries
+    - rt-thread
+  external_files:
+  - package_name: GNU_Tools_for_ARM_Embedded_Processors
+    package_type: ToolChain_Support_Packages
+    package_vendor: 'ARM'
+    package_version: 10.2.1
+    source_path_offset: '.'
+    target_path_offset: '.'
+    files_and_folders: []
 - project_name: etherkit_ethercat_eoe
   project_description: EtherCAT EOE示例
   project_type: rt-thread|@full|@5.1.0